val 38 arch/alpha/include/asm/fpu.h wrfpcr(unsigned long val) val 48 arch/alpha/include/asm/fpu.h : "=&r"(tmp) : "r"(val)); val 55 arch/alpha/include/asm/fpu.h : "=m"(tmp) : "m"(val)); val 72 arch/alpha/include/asm/fpu.h extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); val 74 arch/alpha/include/asm/fpu.h extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); val 23 arch/alpha/include/asm/mc146818rtc.h #define CMOS_WRITE(val, addr) ({ \ val 25 arch/alpha/include/asm/mc146818rtc.h outb_p((val),RTC_PORT(1)); \ val 86 arch/alpha/include/asm/pci.h extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, val 88 arch/alpha/include/asm/pci.h extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, val 341 arch/alpha/include/asm/pgtable.h #define __swp_type(x) (((x).val >> 32) & 0xff) val 342 arch/alpha/include/asm/pgtable.h #define __swp_offset(x) ((x).val >> 40) val 345 arch/alpha/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 17 arch/alpha/include/asm/vga.h static inline void scr_writew(u16 val, volatile u16 *addr) val 20 arch/alpha/include/asm/vga.h __raw_writew(val, (volatile u16 __iomem *) addr); val 22 arch/alpha/include/asm/vga.h *addr = val; val 22 arch/alpha/include/asm/word-at-a-time.h static inline unsigned long has_zero(unsigned long val, unsigned long *bits, const struct word_at_a_time *c) val 24 arch/alpha/include/asm/word-at-a-time.h unsigned long zero_locations = __kernel_cmpbge(0, val); val 29 arch/alpha/include/asm/word-at-a-time.h static inline unsigned long prep_zero_mask(unsigned long val, unsigned long bits, const struct word_at_a_time *c) val 18 arch/alpha/include/asm/xchg.h ____xchg(_u8, volatile char *m, unsigned long val) val 34 arch/alpha/include/asm/xchg.h : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64) val 35 arch/alpha/include/asm/xchg.h : "r" ((long)m), "1" (val) : "memory"); val 41 arch/alpha/include/asm/xchg.h ____xchg(_u16, volatile short *m, unsigned long val) val 57 arch/alpha/include/asm/xchg.h : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64) val 58 arch/alpha/include/asm/xchg.h : "r" ((long)m), "1" (val) : "memory"); val 64 arch/alpha/include/asm/xchg.h ____xchg(_u32, volatile int *m, unsigned long val) val 76 arch/alpha/include/asm/xchg.h : "=&r" (val), "=&r" (dummy), "=m" (*m) val 77 arch/alpha/include/asm/xchg.h : "rI" (val), "m" (*m) : "memory"); val 79 arch/alpha/include/asm/xchg.h return val; val 83 arch/alpha/include/asm/xchg.h ____xchg(_u64, volatile long *m, unsigned long val) val 95 arch/alpha/include/asm/xchg.h : "=&r" (val), "=&r" (dummy), "=m" (*m) val 96 arch/alpha/include/asm/xchg.h : "rI" (val), "m" (*m) : "memory"); val 98 arch/alpha/include/asm/xchg.h return val; val 14 arch/alpha/include/uapi/asm/compiler.h # define __kernel_insbl(val, shift) __builtin_alpha_insbl(val, shift) val 15 arch/alpha/include/uapi/asm/compiler.h # define __kernel_inswl(val, shift) __builtin_alpha_inswl(val, shift) val 16 arch/alpha/include/uapi/asm/compiler.h # define __kernel_insql(val, shift) __builtin_alpha_insql(val, shift) val 17 arch/alpha/include/uapi/asm/compiler.h # define __kernel_inslh(val, shift) __builtin_alpha_inslh(val, shift) val 18 arch/alpha/include/uapi/asm/compiler.h # define __kernel_extbl(val, shift) __builtin_alpha_extbl(val, shift) val 19 arch/alpha/include/uapi/asm/compiler.h # define __kernel_extwl(val, shift) __builtin_alpha_extwl(val, shift) val 22 arch/alpha/include/uapi/asm/compiler.h # define __kernel_insbl(val, shift) \ val 24 arch/alpha/include/uapi/asm/compiler.h __asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ val 26 arch/alpha/include/uapi/asm/compiler.h # define __kernel_inswl(val, shift) \ val 28 arch/alpha/include/uapi/asm/compiler.h __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ val 30 arch/alpha/include/uapi/asm/compiler.h # define __kernel_insql(val, shift) \ val 32 arch/alpha/include/uapi/asm/compiler.h __asm__("insql %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ val 34 arch/alpha/include/uapi/asm/compiler.h # define __kernel_inslh(val, shift) \ val 36 arch/alpha/include/uapi/asm/compiler.h __asm__("inslh %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ val 38 arch/alpha/include/uapi/asm/compiler.h # define __kernel_extbl(val, shift) \ val 40 arch/alpha/include/uapi/asm/compiler.h __asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ val 42 arch/alpha/include/uapi/asm/compiler.h # define __kernel_extwl(val, shift) \ val 44 arch/alpha/include/uapi/asm/compiler.h __asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ val 96 arch/alpha/include/uapi/asm/compiler.h #define __kernel_stb(val,mem) ((mem) = (val)) val 97 arch/alpha/include/uapi/asm/compiler.h #define __kernel_stw(val,mem) ((mem) = (val)) val 109 arch/alpha/include/uapi/asm/compiler.h #define __kernel_stb(val,mem) \ val 111 arch/alpha/include/uapi/asm/compiler.h stb %1,%0" : "=m"(mem) : "r"(val)) val 112 arch/alpha/include/uapi/asm/compiler.h #define __kernel_stw(val,mem) \ val 114 arch/alpha/include/uapi/asm/compiler.h stw %1,%0" : "=m"(mem) : "r"(val)) val 1430 arch/alpha/kernel/osf_sys.c SYSCALL_DEFINE1(sethae, unsigned long, val) val 1432 arch/alpha/kernel/osf_sys.c current_pt_regs()->hae = val; val 45 arch/alpha/kernel/pc873xx.c int val, index = 0; val 52 arch/alpha/kernel/pc873xx.c val = pc873xx_read(base, REG_SID); val 53 arch/alpha/kernel/pc873xx.c if ((val & 0xf0) == 0x10) { val 56 arch/alpha/kernel/pc873xx.c } else if ((val & 0xf8) == 0x70) { val 59 arch/alpha/kernel/pc873xx.c } else if ((val & 0xf8) == 0x50) { val 62 arch/alpha/kernel/pc873xx.c } else if ((val & 0xf8) == 0x40) { val 322 arch/alpha/kernel/pci-sysfs.c int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) val 330 arch/alpha/kernel/pci-sysfs.c *((u8 *)val) = inb(port); val 335 arch/alpha/kernel/pci-sysfs.c *((u16 *)val) = inw(port); val 340 arch/alpha/kernel/pci-sysfs.c *((u32 *)val) = inl(port); val 346 arch/alpha/kernel/pci-sysfs.c int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) val 354 arch/alpha/kernel/pci-sysfs.c outb(port, val); val 359 arch/alpha/kernel/pci-sysfs.c outw(port, val); val 364 arch/alpha/kernel/pci-sysfs.c outl(port, val); val 233 arch/alpha/kernel/perf_event.c static inline void alpha_write_pmc(int idx, unsigned long val) val 235 arch/alpha/kernel/perf_event.c val &= alpha_pmu->pmc_count_mask[idx]; val 236 arch/alpha/kernel/perf_event.c val <<= alpha_pmu->pmc_count_shift[idx]; val 237 arch/alpha/kernel/perf_event.c val |= (1<<idx); val 238 arch/alpha/kernel/perf_event.c wrperfmon(PERFMON_CMD_WRITE, val); val 243 arch/alpha/kernel/perf_event.c unsigned long val; val 245 arch/alpha/kernel/perf_event.c val = wrperfmon(PERFMON_CMD_READ, 0); val 246 arch/alpha/kernel/perf_event.c val >>= alpha_pmu->pmc_count_shift[idx]; val 247 arch/alpha/kernel/perf_event.c val &= alpha_pmu->pmc_count_mask[idx]; val 248 arch/alpha/kernel/perf_event.c return val; val 159 arch/alpha/kernel/proto.h extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); val 178 arch/alpha/kernel/sys_marvel.c unsigned long val; val 180 arch/alpha/kernel/sys_marvel.c val = *csr; val 181 arch/alpha/kernel/sys_marvel.c val &= ~(0x1ffUL << 24); /* clear the target pid */ val 182 arch/alpha/kernel/sys_marvel.c val |= ((unsigned long)where << 24); /* set the new target pid */ val 184 arch/alpha/kernel/sys_marvel.c *csr = val; val 192 arch/alpha/kernel/sys_marvel.c unsigned long val; val 197 arch/alpha/kernel/sys_marvel.c val = io7->csrs->PO7_LSI_CTL[which].csr; val 198 arch/alpha/kernel/sys_marvel.c val &= ~(0x1ffUL << 14); /* clear the target pid */ val 199 arch/alpha/kernel/sys_marvel.c val |= ((unsigned long)where << 14); /* set the new target pid */ val 201 arch/alpha/kernel/sys_marvel.c io7->csrs->PO7_LSI_CTL[which].csr = val; val 209 arch/alpha/kernel/sys_marvel.c unsigned long val; val 214 arch/alpha/kernel/sys_marvel.c val = io7->csrs->PO7_MSI_CTL[which].csr; val 215 arch/alpha/kernel/sys_marvel.c val &= ~(0x1ffUL << 14); /* clear the target pid */ val 216 arch/alpha/kernel/sys_marvel.c val |= ((unsigned long)where << 14); /* set the new target pid */ val 218 arch/alpha/kernel/sys_marvel.c io7->csrs->PO7_MSI_CTL[which].csr = val; val 12 arch/alpha/lib/fpreg.c #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); val 14 arch/alpha/lib/fpreg.c #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); val 20 arch/alpha/lib/fpreg.c unsigned long val; val 23 arch/alpha/lib/fpreg.c case 0: STT( 0, val); break; val 24 arch/alpha/lib/fpreg.c case 1: STT( 1, val); break; val 25 arch/alpha/lib/fpreg.c case 2: STT( 2, val); break; val 26 arch/alpha/lib/fpreg.c case 3: STT( 3, val); break; val 27 arch/alpha/lib/fpreg.c case 4: STT( 4, val); break; val 28 arch/alpha/lib/fpreg.c case 5: STT( 5, val); break; val 29 arch/alpha/lib/fpreg.c case 6: STT( 6, val); break; val 30 arch/alpha/lib/fpreg.c case 7: STT( 7, val); break; val 31 arch/alpha/lib/fpreg.c case 8: STT( 8, val); break; val 32 arch/alpha/lib/fpreg.c case 9: STT( 9, val); break; val 33 arch/alpha/lib/fpreg.c case 10: STT(10, val); break; val 34 arch/alpha/lib/fpreg.c case 11: STT(11, val); break; val 35 arch/alpha/lib/fpreg.c case 12: STT(12, val); break; val 36 arch/alpha/lib/fpreg.c case 13: STT(13, val); break; val 37 arch/alpha/lib/fpreg.c case 14: STT(14, val); break; val 38 arch/alpha/lib/fpreg.c case 15: STT(15, val); break; val 39 arch/alpha/lib/fpreg.c case 16: STT(16, val); break; val 40 arch/alpha/lib/fpreg.c case 17: STT(17, val); break; val 41 arch/alpha/lib/fpreg.c case 18: STT(18, val); break; val 42 arch/alpha/lib/fpreg.c case 19: STT(19, val); break; val 43 arch/alpha/lib/fpreg.c case 20: STT(20, val); break; val 44 arch/alpha/lib/fpreg.c case 21: STT(21, val); break; val 45 arch/alpha/lib/fpreg.c case 22: STT(22, val); break; val 46 arch/alpha/lib/fpreg.c case 23: STT(23, val); break; val 47 arch/alpha/lib/fpreg.c case 24: STT(24, val); break; val 48 arch/alpha/lib/fpreg.c case 25: STT(25, val); break; val 49 arch/alpha/lib/fpreg.c case 26: STT(26, val); break; val 50 arch/alpha/lib/fpreg.c case 27: STT(27, val); break; val 51 arch/alpha/lib/fpreg.c case 28: STT(28, val); break; val 52 arch/alpha/lib/fpreg.c case 29: STT(29, val); break; val 53 arch/alpha/lib/fpreg.c case 30: STT(30, val); break; val 54 arch/alpha/lib/fpreg.c case 31: STT(31, val); break; val 57 arch/alpha/lib/fpreg.c return val; val 62 arch/alpha/lib/fpreg.c #define LDT(reg,val) asm volatile ("itoft %0,$f"#reg : : "r"(val)); val 64 arch/alpha/lib/fpreg.c #define LDT(reg,val) asm volatile ("ldt $f"#reg",%0" : : "m"(val)); val 68 arch/alpha/lib/fpreg.c alpha_write_fp_reg (unsigned long reg, unsigned long val) val 71 arch/alpha/lib/fpreg.c case 0: LDT( 0, val); break; val 72 arch/alpha/lib/fpreg.c case 1: LDT( 1, val); break; val 73 arch/alpha/lib/fpreg.c case 2: LDT( 2, val); break; val 74 arch/alpha/lib/fpreg.c case 3: LDT( 3, val); break; val 75 arch/alpha/lib/fpreg.c case 4: LDT( 4, val); break; val 76 arch/alpha/lib/fpreg.c case 5: LDT( 5, val); break; val 77 arch/alpha/lib/fpreg.c case 6: LDT( 6, val); break; val 78 arch/alpha/lib/fpreg.c case 7: LDT( 7, val); break; val 79 arch/alpha/lib/fpreg.c case 8: LDT( 8, val); break; val 80 arch/alpha/lib/fpreg.c case 9: LDT( 9, val); break; val 81 arch/alpha/lib/fpreg.c case 10: LDT(10, val); break; val 82 arch/alpha/lib/fpreg.c case 11: LDT(11, val); break; val 83 arch/alpha/lib/fpreg.c case 12: LDT(12, val); break; val 84 arch/alpha/lib/fpreg.c case 13: LDT(13, val); break; val 85 arch/alpha/lib/fpreg.c case 14: LDT(14, val); break; val 86 arch/alpha/lib/fpreg.c case 15: LDT(15, val); break; val 87 arch/alpha/lib/fpreg.c case 16: LDT(16, val); break; val 88 arch/alpha/lib/fpreg.c case 17: LDT(17, val); break; val 89 arch/alpha/lib/fpreg.c case 18: LDT(18, val); break; val 90 arch/alpha/lib/fpreg.c case 19: LDT(19, val); break; val 91 arch/alpha/lib/fpreg.c case 20: LDT(20, val); break; val 92 arch/alpha/lib/fpreg.c case 21: LDT(21, val); break; val 93 arch/alpha/lib/fpreg.c case 22: LDT(22, val); break; val 94 arch/alpha/lib/fpreg.c case 23: LDT(23, val); break; val 95 arch/alpha/lib/fpreg.c case 24: LDT(24, val); break; val 96 arch/alpha/lib/fpreg.c case 25: LDT(25, val); break; val 97 arch/alpha/lib/fpreg.c case 26: LDT(26, val); break; val 98 arch/alpha/lib/fpreg.c case 27: LDT(27, val); break; val 99 arch/alpha/lib/fpreg.c case 28: LDT(28, val); break; val 100 arch/alpha/lib/fpreg.c case 29: LDT(29, val); break; val 101 arch/alpha/lib/fpreg.c case 30: LDT(30, val); break; val 102 arch/alpha/lib/fpreg.c case 31: LDT(31, val); break; val 108 arch/alpha/lib/fpreg.c #define STS(reg,val) asm volatile ("ftois $f"#reg",%0" : "=r"(val)); val 110 arch/alpha/lib/fpreg.c #define STS(reg,val) asm volatile ("sts $f"#reg",%0" : "=m"(val)); val 116 arch/alpha/lib/fpreg.c unsigned long val; val 119 arch/alpha/lib/fpreg.c case 0: STS( 0, val); break; val 120 arch/alpha/lib/fpreg.c case 1: STS( 1, val); break; val 121 arch/alpha/lib/fpreg.c case 2: STS( 2, val); break; val 122 arch/alpha/lib/fpreg.c case 3: STS( 3, val); break; val 123 arch/alpha/lib/fpreg.c case 4: STS( 4, val); break; val 124 arch/alpha/lib/fpreg.c case 5: STS( 5, val); break; val 125 arch/alpha/lib/fpreg.c case 6: STS( 6, val); break; val 126 arch/alpha/lib/fpreg.c case 7: STS( 7, val); break; val 127 arch/alpha/lib/fpreg.c case 8: STS( 8, val); break; val 128 arch/alpha/lib/fpreg.c case 9: STS( 9, val); break; val 129 arch/alpha/lib/fpreg.c case 10: STS(10, val); break; val 130 arch/alpha/lib/fpreg.c case 11: STS(11, val); break; val 131 arch/alpha/lib/fpreg.c case 12: STS(12, val); break; val 132 arch/alpha/lib/fpreg.c case 13: STS(13, val); break; val 133 arch/alpha/lib/fpreg.c case 14: STS(14, val); break; val 134 arch/alpha/lib/fpreg.c case 15: STS(15, val); break; val 135 arch/alpha/lib/fpreg.c case 16: STS(16, val); break; val 136 arch/alpha/lib/fpreg.c case 17: STS(17, val); break; val 137 arch/alpha/lib/fpreg.c case 18: STS(18, val); break; val 138 arch/alpha/lib/fpreg.c case 19: STS(19, val); break; val 139 arch/alpha/lib/fpreg.c case 20: STS(20, val); break; val 140 arch/alpha/lib/fpreg.c case 21: STS(21, val); break; val 141 arch/alpha/lib/fpreg.c case 22: STS(22, val); break; val 142 arch/alpha/lib/fpreg.c case 23: STS(23, val); break; val 143 arch/alpha/lib/fpreg.c case 24: STS(24, val); break; val 144 arch/alpha/lib/fpreg.c case 25: STS(25, val); break; val 145 arch/alpha/lib/fpreg.c case 26: STS(26, val); break; val 146 arch/alpha/lib/fpreg.c case 27: STS(27, val); break; val 147 arch/alpha/lib/fpreg.c case 28: STS(28, val); break; val 148 arch/alpha/lib/fpreg.c case 29: STS(29, val); break; val 149 arch/alpha/lib/fpreg.c case 30: STS(30, val); break; val 150 arch/alpha/lib/fpreg.c case 31: STS(31, val); break; val 153 arch/alpha/lib/fpreg.c return val; val 158 arch/alpha/lib/fpreg.c #define LDS(reg,val) asm volatile ("itofs %0,$f"#reg : : "r"(val)); val 160 arch/alpha/lib/fpreg.c #define LDS(reg,val) asm volatile ("lds $f"#reg",%0" : : "m"(val)); val 164 arch/alpha/lib/fpreg.c alpha_write_fp_reg_s (unsigned long reg, unsigned long val) val 167 arch/alpha/lib/fpreg.c case 0: LDS( 0, val); break; val 168 arch/alpha/lib/fpreg.c case 1: LDS( 1, val); break; val 169 arch/alpha/lib/fpreg.c case 2: LDS( 2, val); break; val 170 arch/alpha/lib/fpreg.c case 3: LDS( 3, val); break; val 171 arch/alpha/lib/fpreg.c case 4: LDS( 4, val); break; val 172 arch/alpha/lib/fpreg.c case 5: LDS( 5, val); break; val 173 arch/alpha/lib/fpreg.c case 6: LDS( 6, val); break; val 174 arch/alpha/lib/fpreg.c case 7: LDS( 7, val); break; val 175 arch/alpha/lib/fpreg.c case 8: LDS( 8, val); break; val 176 arch/alpha/lib/fpreg.c case 9: LDS( 9, val); break; val 177 arch/alpha/lib/fpreg.c case 10: LDS(10, val); break; val 178 arch/alpha/lib/fpreg.c case 11: LDS(11, val); break; val 179 arch/alpha/lib/fpreg.c case 12: LDS(12, val); break; val 180 arch/alpha/lib/fpreg.c case 13: LDS(13, val); break; val 181 arch/alpha/lib/fpreg.c case 14: LDS(14, val); break; val 182 arch/alpha/lib/fpreg.c case 15: LDS(15, val); break; val 183 arch/alpha/lib/fpreg.c case 16: LDS(16, val); break; val 184 arch/alpha/lib/fpreg.c case 17: LDS(17, val); break; val 185 arch/alpha/lib/fpreg.c case 18: LDS(18, val); break; val 186 arch/alpha/lib/fpreg.c case 19: LDS(19, val); break; val 187 arch/alpha/lib/fpreg.c case 20: LDS(20, val); break; val 188 arch/alpha/lib/fpreg.c case 21: LDS(21, val); break; val 189 arch/alpha/lib/fpreg.c case 22: LDS(22, val); break; val 190 arch/alpha/lib/fpreg.c case 23: LDS(23, val); break; val 191 arch/alpha/lib/fpreg.c case 24: LDS(24, val); break; val 192 arch/alpha/lib/fpreg.c case 25: LDS(25, val); break; val 193 arch/alpha/lib/fpreg.c case 26: LDS(26, val); break; val 194 arch/alpha/lib/fpreg.c case 27: LDS(27, val); break; val 195 arch/alpha/lib/fpreg.c case 28: LDS(28, val); break; val 196 arch/alpha/lib/fpreg.c case 29: LDS(29, val); break; val 197 arch/alpha/lib/fpreg.c case 30: LDS(30, val); break; val 198 arch/alpha/lib/fpreg.c case 31: LDS(31, val); break; val 49 arch/alpha/math-emu/math.c extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); val 51 arch/alpha/math-emu/math.c extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); val 30 arch/arc/include/asm/atomic.h unsigned int val; \ val 37 arch/arc/include/asm/atomic.h : [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \ val 46 arch/arc/include/asm/atomic.h unsigned int val; \ val 59 arch/arc/include/asm/atomic.h : [val] "=&r" (val) \ val 66 arch/arc/include/asm/atomic.h return val; \ val 72 arch/arc/include/asm/atomic.h unsigned int val, orig; \ val 85 arch/arc/include/asm/atomic.h : [val] "=&r" (val), \ val 331 arch/arc/include/asm/atomic.h s64 val; val 335 arch/arc/include/asm/atomic.h : "=r"(val) val 338 arch/arc/include/asm/atomic.h return val; val 364 arch/arc/include/asm/atomic.h s64 val; \ val 373 arch/arc/include/asm/atomic.h : "=&r"(val) \ val 381 arch/arc/include/asm/atomic.h s64 val; \ val 392 arch/arc/include/asm/atomic.h : [val] "=&r"(val) \ val 398 arch/arc/include/asm/atomic.h return val; \ val 404 arch/arc/include/asm/atomic.h s64 val, orig; \ val 415 arch/arc/include/asm/atomic.h : "=&r"(orig), "=&r"(val) \ val 497 arch/arc/include/asm/atomic.h s64 val; val 509 arch/arc/include/asm/atomic.h : "=&r"(val) val 515 arch/arc/include/asm/atomic.h return val; val 112 arch/arc/include/asm/cmpxchg.h static inline unsigned long __xchg(unsigned long val, volatile void *ptr, val 123 arch/arc/include/asm/cmpxchg.h : "+r"(val) val 129 arch/arc/include/asm/cmpxchg.h return val; val 173 arch/arc/include/asm/cmpxchg.h static inline unsigned long __xchg(unsigned long val, volatile void *ptr, val 190 arch/arc/include/asm/cmpxchg.h : "+r"(val) val 196 arch/arc/include/asm/cmpxchg.h return val; val 110 arch/arc/include/asm/disasm.h void set_reg(int reg, long val, struct pt_regs *regs, val 36 arch/arc/include/asm/kprobes.h unsigned long val, void *data); val 376 arch/arc/include/asm/pgtable.h #define __swp_type(pte_lookalike) (((pte_lookalike).val) & 0x1f) val 377 arch/arc/include/asm/pgtable.h #define __swp_offset(pte_lookalike) ((pte_lookalike).val >> 13) val 381 arch/arc/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 19 arch/arc/include/asm/spinlock.h unsigned int val; val 27 arch/arc/include/asm/spinlock.h : [val] "=&r" (val) val 46 arch/arc/include/asm/spinlock.h unsigned int val, got_it = 0; val 56 arch/arc/include/asm/spinlock.h : [val] "=&r" (val), val 81 arch/arc/include/asm/spinlock.h unsigned int val; val 100 arch/arc/include/asm/spinlock.h : [val] "=&r" (val) val 111 arch/arc/include/asm/spinlock.h unsigned int val, got_it = 0; val 123 arch/arc/include/asm/spinlock.h : [val] "=&r" (val), val 136 arch/arc/include/asm/spinlock.h unsigned int val; val 157 arch/arc/include/asm/spinlock.h : [val] "=&r" (val) val 169 arch/arc/include/asm/spinlock.h unsigned int val, got_it = 0; val 181 arch/arc/include/asm/spinlock.h : [val] "=&r" (val), val 195 arch/arc/include/asm/spinlock.h unsigned int val; val 208 arch/arc/include/asm/spinlock.h : [val] "=&r" (val) val 224 arch/arc/include/asm/spinlock.h unsigned int val = __ARCH_SPIN_LOCK_LOCKED__; val 239 arch/arc/include/asm/spinlock.h : "+&r" (val) val 252 arch/arc/include/asm/spinlock.h unsigned int val = __ARCH_SPIN_LOCK_LOCKED__; val 258 arch/arc/include/asm/spinlock.h : "+r" (val) val 264 arch/arc/include/asm/spinlock.h return (val == __ARCH_SPIN_LOCK_UNLOCKED__); val 269 arch/arc/include/asm/spinlock.h unsigned int val = __ARCH_SPIN_LOCK_UNLOCKED__; val 285 arch/arc/include/asm/spinlock.h : "+r" (val) val 45 arch/arc/include/asm/syscall.h int error, long val) val 47 arch/arc/include/asm/syscall.h regs->r0 = (long) error ?: val; val 171 arch/arc/include/asm/uaccess.h char val; val 385 arch/arc/include/asm/uaccess.h : "=r" (res), "+r"(to), "+r"(from), "+r"(n), "=r"(val), val 398 arch/arc/include/asm/uaccess.h char val; val 607 arch/arc/include/asm/uaccess.h : "=r" (res), "+r"(to), "+r"(from), "+r"(n), "=r"(val), val 662 arch/arc/include/asm/uaccess.h char val; val 684 arch/arc/include/asm/uaccess.h : "+r"(res), "+r"(dst), "+r"(src), "=r"(val) val 694 arch/arc/include/asm/uaccess.h char val; val 714 arch/arc/include/asm/uaccess.h : "=r"(res), "=r"(tmp1), "=r"(cnt), "=r"(val) val 459 arch/arc/kernel/disasm.c void __kprobes set_reg(int reg, long val, struct pt_regs *regs, val 467 arch/arc/kernel/disasm.c p[-reg] = val; val 472 arch/arc/kernel/disasm.c p[13-reg] = val; val 476 arch/arc/kernel/disasm.c regs->r26 = val; val 479 arch/arc/kernel/disasm.c regs->fp = val; val 482 arch/arc/kernel/disasm.c regs->sp = val; val 485 arch/arc/kernel/disasm.c regs->blink = val; val 356 arch/arc/kernel/kprobes.c unsigned long val, void *data) val 362 arch/arc/kernel/kprobes.c switch (val) { val 26 arch/arc/kernel/unaligned.c #define __get8_unaligned_check(val, addr, err) \ val 39 arch/arc/kernel/unaligned.c : "=r" (err), "=&r" (val), "=r" (addr) \ val 42 arch/arc/kernel/unaligned.c #define get16_unaligned_check(val, addr) \ val 46 arch/arc/kernel/unaligned.c val = v << ((BE) ? 8 : 0); \ val 48 arch/arc/kernel/unaligned.c val |= v << ((BE) ? 0 : 8); \ val 53 arch/arc/kernel/unaligned.c #define get32_unaligned_check(val, addr) \ val 57 arch/arc/kernel/unaligned.c val = v << ((BE) ? 24 : 0); \ val 59 arch/arc/kernel/unaligned.c val |= v << ((BE) ? 16 : 8); \ val 61 arch/arc/kernel/unaligned.c val |= v << ((BE) ? 8 : 16); \ val 63 arch/arc/kernel/unaligned.c val |= v << ((BE) ? 0 : 24); \ val 68 arch/arc/kernel/unaligned.c #define put16_unaligned_check(val, addr) \ val 70 arch/arc/kernel/unaligned.c unsigned int err = 0, v = val, a = addr;\ val 95 arch/arc/kernel/unaligned.c #define put32_unaligned_check(val, addr) \ val 97 arch/arc/kernel/unaligned.c unsigned int err = 0, v = val, a = addr;\ val 135 arch/arc/kernel/unaligned.c int val; val 146 arch/arc/kernel/unaligned.c get32_unaligned_check(val, state->src1 + state->src2); val 148 arch/arc/kernel/unaligned.c get16_unaligned_check(val, state->src1 + state->src2); val 151 arch/arc/kernel/unaligned.c val = (val << 16) >> 16; val 155 arch/arc/kernel/unaligned.c set_reg(state->dest, val, regs, cregs); val 500 arch/arc/mm/cache.c unsigned int val = read_aux_reg(ctl); val 503 arch/arc/mm/cache.c val |= DC_CTRL_INV_MODE_FLUSH; val 511 arch/arc/mm/cache.c val &= ~DC_CTRL_RGN_OP_MSK; val 513 arch/arc/mm/cache.c val |= DC_CTRL_RGN_OP_INV; val 515 arch/arc/mm/cache.c write_aux_reg(ctl, val); val 84 arch/arc/plat-axs10x/axs10x.c unsigned int val; val 87 arch/arc/plat-axs10x/axs10x.c board.val = ioread32((void __iomem *)creg); val 40 arch/arm/boot/compressed/atags_to_fdt.c const char *property, uint32_t val) val 45 arch/arm/boot/compressed/atags_to_fdt.c return fdt_setprop_cell(fdt, offset, property, val); val 397 arch/arm/common/bL_switcher.c static int bL_activation_notify(unsigned long val) val 401 arch/arm/common/bL_switcher.c ret = blocking_notifier_call_chain(&bL_activation_notifier, val, NULL); val 21 arch/arm/common/bL_switcher_dummy_if.c unsigned char val[3]; val 30 arch/arm/common/bL_switcher_dummy_if.c if (copy_from_user(val, buf, 3)) val 34 arch/arm/common/bL_switcher_dummy_if.c if (val[0] < '0' || val[0] > '9' || val 35 arch/arm/common/bL_switcher_dummy_if.c val[1] != ',' || val 36 arch/arm/common/bL_switcher_dummy_if.c val[2] < '0' || val[2] > '1') val 39 arch/arm/common/bL_switcher_dummy_if.c cpu = val[0] - '0'; val 40 arch/arm/common/bL_switcher_dummy_if.c cluster = val[2] - '0'; val 12 arch/arm/common/krait-l2-accessors.c void krait_set_l2_indirect_reg(u32 addr, u32 val) val 23 arch/arm/common/krait-l2-accessors.c asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val)); val 32 arch/arm/common/krait-l2-accessors.c u32 val; val 42 arch/arm/common/krait-l2-accessors.c asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val)); val 46 arch/arm/common/krait-l2-accessors.c return val; val 145 arch/arm/common/mcpm_entry.c unsigned long val = ptr ? __pa_symbol(ptr) : 0; val 146 arch/arm/common/mcpm_entry.c mcpm_entry_vectors[cluster][cpu] = val; val 509 arch/arm/common/sa1111.c u32 val; val 511 arch/arm/common/sa1111.c val = readl_relaxed(reg); val 512 arch/arm/common/sa1111.c val &= ~mask; val 513 arch/arm/common/sa1111.c val |= mask & set; val 514 arch/arm/common/sa1111.c writel_relaxed(val, reg); val 587 arch/arm/common/sa1111.c u32 msk, val; val 590 arch/arm/common/sa1111.c val = *bits; val 593 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val); val 594 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val); val 595 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4); val 596 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4); val 597 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12); val 598 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12); val 878 arch/arm/common/sa1111.c unsigned int val; val 896 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKPCR); val 897 arch/arm/common/sa1111.c writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR); val 980 arch/arm/common/sa1111.c unsigned int val; val 1017 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKCR); val 1018 arch/arm/common/sa1111.c writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); val 1223 arch/arm/common/sa1111.c unsigned int val; val 1227 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKCR); val 1229 arch/arm/common/sa1111.c val &= ~SKCR_SELAC; val 1231 arch/arm/common/sa1111.c val |= SKCR_SELAC; val 1233 arch/arm/common/sa1111.c writel_relaxed(val, sachip->base + SA1111_SKCR); val 1294 arch/arm/common/sa1111.c unsigned int val; val 1302 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKPCR); val 1303 arch/arm/common/sa1111.c writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); val 1318 arch/arm/common/sa1111.c unsigned int val; val 1321 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKPCR); val 1322 arch/arm/common/sa1111.c writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); val 106 arch/arm/include/asm/arch_gicv3.h static inline void write_ ## a64(u32 val) \ val 108 arch/arm/include/asm/arch_gicv3.h write_sysreg(val, a32); \ val 116 arch/arm/include/asm/arch_gicv3.h static inline void write_ ## a64(u64 val) \ val 118 arch/arm/include/asm/arch_gicv3.h write_sysreg(lower_32_bits(val), a32lo);\ val 119 arch/arm/include/asm/arch_gicv3.h write_sysreg(upper_32_bits(val), a32hi);\ val 123 arch/arm/include/asm/arch_gicv3.h u64 val = read_sysreg(a32lo); \ val 125 arch/arm/include/asm/arch_gicv3.h val |= (u64)read_sysreg(a32hi) << 32; \ val 127 arch/arm/include/asm/arch_gicv3.h return val; \ val 185 arch/arm/include/asm/arch_gicv3.h static inline void gic_write_dir(u32 val) val 187 arch/arm/include/asm/arch_gicv3.h write_sysreg(val, ICC_DIR); val 200 arch/arm/include/asm/arch_gicv3.h static inline void gic_write_ctlr(u32 val) val 202 arch/arm/include/asm/arch_gicv3.h write_sysreg(val, ICC_CTLR); val 211 arch/arm/include/asm/arch_gicv3.h static inline void gic_write_grpen1(u32 val) val 213 arch/arm/include/asm/arch_gicv3.h write_sysreg(val, ICC_IGRPEN1); val 217 arch/arm/include/asm/arch_gicv3.h static inline void gic_write_sgi1r(u64 val) val 219 arch/arm/include/asm/arch_gicv3.h write_sysreg(val, ICC_SGI1R); val 227 arch/arm/include/asm/arch_gicv3.h static inline void gic_write_sre(u32 val) val 229 arch/arm/include/asm/arch_gicv3.h write_sysreg(val, ICC_SRE); val 233 arch/arm/include/asm/arch_gicv3.h static inline void gic_write_bpr1(u32 val) val 235 arch/arm/include/asm/arch_gicv3.h write_sysreg(val, ICC_BPR1); val 243 arch/arm/include/asm/arch_gicv3.h static inline void gic_write_pmr(u32 val) val 245 arch/arm/include/asm/arch_gicv3.h write_sysreg(val, ICC_PMR); val 262 arch/arm/include/asm/arch_gicv3.h static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr) val 264 arch/arm/include/asm/arch_gicv3.h writel_relaxed((u32)val, addr); val 265 arch/arm/include/asm/arch_gicv3.h writel_relaxed((u32)(val >> 32), addr + 4); val 270 arch/arm/include/asm/arch_gicv3.h u64 val; val 272 arch/arm/include/asm/arch_gicv3.h val = readl_relaxed(addr); val 273 arch/arm/include/asm/arch_gicv3.h val |= (u64)readl_relaxed(addr + 4) << 32; val 274 arch/arm/include/asm/arch_gicv3.h return val; val 336 arch/arm/include/asm/arch_gicv3.h static inline void gits_write_vpendbaser(u64 val, void * __iomem addr) val 350 arch/arm/include/asm/arch_gicv3.h __gic_writeq_nonatomic(val, addr); val 27 arch/arm/include/asm/arch_timer.h void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) val 32 arch/arm/include/asm/arch_timer.h asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); val 35 arch/arm/include/asm/arch_timer.h asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); val 41 arch/arm/include/asm/arch_timer.h asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); val 44 arch/arm/include/asm/arch_timer.h asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val)); val 55 arch/arm/include/asm/arch_timer.h u32 val = 0; val 60 arch/arm/include/asm/arch_timer.h asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); val 63 arch/arm/include/asm/arch_timer.h asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); val 69 arch/arm/include/asm/arch_timer.h asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); val 72 arch/arm/include/asm/arch_timer.h asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val)); val 77 arch/arm/include/asm/arch_timer.h return val; val 82 arch/arm/include/asm/arch_timer.h u32 val; val 83 arch/arm/include/asm/arch_timer.h asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); val 84 arch/arm/include/asm/arch_timer.h return val; val 81 arch/arm/include/asm/atomic.h int result, val; \ val 91 arch/arm/include/asm/atomic.h : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter) \ val 178 arch/arm/include/asm/atomic.h int val; \ val 182 arch/arm/include/asm/atomic.h val = v->counter; \ val 185 arch/arm/include/asm/atomic.h return val; \ val 192 arch/arm/include/asm/atomic.h int val; \ val 195 arch/arm/include/asm/atomic.h val = v->counter; \ val 199 arch/arm/include/asm/atomic.h return val; \ val 352 arch/arm/include/asm/atomic.h s64 result, val; \ val 364 arch/arm/include/asm/atomic.h : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter) \ val 79 arch/arm/include/asm/cachetype.h unsigned int val; val 81 arch/arm/include/asm/cachetype.h asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); val 82 arch/arm/include/asm/cachetype.h return val; val 77 arch/arm/include/asm/cp15.h unsigned long val; val 78 arch/arm/include/asm/cp15.h asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); val 79 arch/arm/include/asm/cp15.h return val; val 82 arch/arm/include/asm/cp15.h static inline void set_cr(unsigned long val) val 85 arch/arm/include/asm/cp15.h : : "r" (val) : "cc"); val 91 arch/arm/include/asm/cp15.h unsigned int val; val 92 arch/arm/include/asm/cp15.h asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); val 93 arch/arm/include/asm/cp15.h return val; val 96 arch/arm/include/asm/cp15.h static inline void set_auxcr(unsigned int val) val 99 arch/arm/include/asm/cp15.h : : "r" (val)); val 109 arch/arm/include/asm/cp15.h unsigned int val; val 111 arch/arm/include/asm/cp15.h : "=r" (val) : : "cc"); val 112 arch/arm/include/asm/cp15.h return val; val 115 arch/arm/include/asm/cp15.h static inline void set_copro_access(unsigned int val) val 118 arch/arm/include/asm/cp15.h : : "r" (val) : "cc"); val 88 arch/arm/include/asm/cti.h unsigned long val; val 90 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIINEN + trig_in * 4); val 91 arch/arm/include/asm/cti.h val |= BIT(chan); val 92 arch/arm/include/asm/cti.h __raw_writel(val, base + CTIINEN + trig_in * 4); val 94 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIOUTEN + trig_out * 4); val 95 arch/arm/include/asm/cti.h val |= BIT(chan); val 96 arch/arm/include/asm/cti.h __raw_writel(val, base + CTIOUTEN + trig_out * 4); val 130 arch/arm/include/asm/cti.h unsigned long val; val 132 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIINTACK); val 133 arch/arm/include/asm/cti.h val |= BIT(cti->trig_out_for_irq); val 134 arch/arm/include/asm/cti.h __raw_writel(val, base + CTIINTACK); val 97 arch/arm/include/asm/domain.h static __always_inline void set_domain(unsigned int val) val 101 arch/arm/include/asm/domain.h : : "r" (val) : "memory"); val 110 arch/arm/include/asm/domain.h static __always_inline void set_domain(unsigned int val) val 15 arch/arm/include/asm/floppy.h #define fd_outb(val,port) \ val 18 arch/arm/include/asm/floppy.h fd_setdor((val)); \ val 20 arch/arm/include/asm/floppy.h outb((val),(port)); \ val 51 arch/arm/include/asm/futex.h u32 val; val 69 arch/arm/include/asm/futex.h : "=&r" (ret), "=&r" (val) val 75 arch/arm/include/asm/futex.h *uval = val; val 105 arch/arm/include/asm/futex.h u32 val; val 119 arch/arm/include/asm/futex.h : "+r" (ret), "=&r" (val) val 124 arch/arm/include/asm/futex.h *uval = val; val 12 arch/arm/include/asm/hardware/cp14.h #define dbg_write(val, reg) WCP14_##reg(val) val 14 arch/arm/include/asm/hardware/cp14.h #define etm_write(val, reg) WCP14_##reg(val) val 19 arch/arm/include/asm/hardware/cp14.h u32 val; \ val 20 arch/arm/include/asm/hardware/cp14.h asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \ val 21 arch/arm/include/asm/hardware/cp14.h val; \ val 24 arch/arm/include/asm/hardware/cp14.h #define MCR14(val, op1, crn, crm, op2) \ val 26 arch/arm/include/asm/hardware/cp14.h asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\ val 152 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) val 153 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) val 154 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) val 155 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGECR(val) MCR14(val, 0, c0, c9, 0) val 156 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDSCCR(val) MCR14(val, 0, c0, c10, 0) val 157 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDSMCR(val) MCR14(val, 0, c0, c11, 0) val 158 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDTRRXext(val) MCR14(val, 0, c0, c0, 2) val 159 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDSCRext(val) MCR14(val, 0, c0, c2, 2) val 160 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDTRTXext(val) MCR14(val, 0, c0, c3, 2) val 161 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDRCR(val) MCR14(val, 0, c0, c4, 2) val 162 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR0(val) MCR14(val, 0, c0, c0, 4) val 163 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR1(val) MCR14(val, 0, c0, c1, 4) val 164 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR2(val) MCR14(val, 0, c0, c2, 4) val 165 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR3(val) MCR14(val, 0, c0, c3, 4) val 166 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR4(val) MCR14(val, 0, c0, c4, 4) val 167 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4) val 168 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4) val 169 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR7(val) MCR14(val, 0, c0, c7, 4) val 170 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4) val 171 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR9(val) MCR14(val, 0, c0, c9, 4) val 172 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR10(val) MCR14(val, 0, c0, c10, 4) val 173 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR11(val) MCR14(val, 0, c0, c11, 4) val 174 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR12(val) MCR14(val, 0, c0, c12, 4) val 175 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4) val 176 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR14(val) MCR14(val, 0, c0, c14, 4) val 177 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR15(val) MCR14(val, 0, c0, c15, 4) val 178 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR0(val) MCR14(val, 0, c0, c0, 5) val 179 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR1(val) MCR14(val, 0, c0, c1, 5) val 180 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR2(val) MCR14(val, 0, c0, c2, 5) val 181 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR3(val) MCR14(val, 0, c0, c3, 5) val 182 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR4(val) MCR14(val, 0, c0, c4, 5) val 183 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5) val 184 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5) val 185 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR7(val) MCR14(val, 0, c0, c7, 5) val 186 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5) val 187 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR9(val) MCR14(val, 0, c0, c9, 5) val 188 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR10(val) MCR14(val, 0, c0, c10, 5) val 189 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR11(val) MCR14(val, 0, c0, c11, 5) val 190 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR12(val) MCR14(val, 0, c0, c12, 5) val 191 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5) val 192 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR14(val) MCR14(val, 0, c0, c14, 5) val 193 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR15(val) MCR14(val, 0, c0, c15, 5) val 194 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR0(val) MCR14(val, 0, c0, c0, 6) val 195 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR1(val) MCR14(val, 0, c0, c1, 6) val 196 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR2(val) MCR14(val, 0, c0, c2, 6) val 197 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR3(val) MCR14(val, 0, c0, c3, 6) val 198 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR4(val) MCR14(val, 0, c0, c4, 6) val 199 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR5(val) MCR14(val, 0, c0, c5, 6) val 200 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6, 6) val 201 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR7(val) MCR14(val, 0, c0, c7, 6) val 202 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6) val 203 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR9(val) MCR14(val, 0, c0, c9, 6) val 204 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR10(val) MCR14(val, 0, c0, c10, 6) val 205 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR11(val) MCR14(val, 0, c0, c11, 6) val 206 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR12(val) MCR14(val, 0, c0, c12, 6) val 207 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6) val 208 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR14(val) MCR14(val, 0, c0, c14, 6) val 209 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR15(val) MCR14(val, 0, c0, c15, 6) val 210 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR0(val) MCR14(val, 0, c0, c0, 7) val 211 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR1(val) MCR14(val, 0, c0, c1, 7) val 212 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR2(val) MCR14(val, 0, c0, c2, 7) val 213 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR3(val) MCR14(val, 0, c0, c3, 7) val 214 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR4(val) MCR14(val, 0, c0, c4, 7) val 215 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR5(val) MCR14(val, 0, c0, c5, 7) val 216 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR6(val) MCR14(val, 0, c0, c6, 7) val 217 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR7(val) MCR14(val, 0, c0, c7, 7) val 218 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7) val 219 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR9(val) MCR14(val, 0, c0, c9, 7) val 220 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR10(val) MCR14(val, 0, c0, c10, 7) val 221 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR11(val) MCR14(val, 0, c0, c11, 7) val 222 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR12(val) MCR14(val, 0, c0, c12, 7) val 223 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7) val 224 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR14(val) MCR14(val, 0, c0, c14, 7) val 225 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR15(val) MCR14(val, 0, c0, c15, 7) val 226 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR0(val) MCR14(val, 0, c1, c0, 1) val 227 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR1(val) MCR14(val, 0, c1, c1, 1) val 228 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR2(val) MCR14(val, 0, c1, c2, 1) val 229 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR3(val) MCR14(val, 0, c1, c3, 1) val 230 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR4(val) MCR14(val, 0, c1, c4, 1) val 231 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR5(val) MCR14(val, 0, c1, c5, 1) val 232 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR6(val) MCR14(val, 0, c1, c6, 1) val 233 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR7(val) MCR14(val, 0, c1, c7, 1) val 234 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR8(val) MCR14(val, 0, c1, c8, 1) val 235 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR9(val) MCR14(val, 0, c1, c9, 1) val 236 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR10(val) MCR14(val, 0, c1, c10, 1) val 237 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR11(val) MCR14(val, 0, c1, c11, 1) val 238 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR12(val) MCR14(val, 0, c1, c12, 1) val 239 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1) val 240 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR14(val) MCR14(val, 0, c1, c14, 1) val 241 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR15(val) MCR14(val, 0, c1, c15, 1) val 242 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGOSLAR(val) MCR14(val, 0, c1, c0, 4) val 243 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGOSSRR(val) MCR14(val, 0, c1, c2, 4) val 244 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGOSDLR(val) MCR14(val, 0, c1, c3, 4) val 245 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGPRCR(val) MCR14(val, 0, c1, c4, 4) val 246 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGITCTRL(val) MCR14(val, 0, c7, c0, 4) val 247 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGCLAIMSET(val) MCR14(val, 0, c7, c8, 6) val 248 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGCLAIMCLR(val) MCR14(val, 0, c7, c9, 6) val 412 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCR(val) MCR14(val, 1, c0, c0, 0) val 413 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTRIGGER(val) MCR14(val, 1, c0, c2, 0) val 414 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMASICCR(val) MCR14(val, 1, c0, c3, 0) val 415 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSR(val) MCR14(val, 1, c0, c4, 0) val 416 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTSSCR(val) MCR14(val, 1, c0, c6, 0) val 417 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTECR2(val) MCR14(val, 1, c0, c7, 0) val 418 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTEEVR(val) MCR14(val, 1, c0, c8, 0) val 419 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTECR1(val) MCR14(val, 1, c0, c9, 0) val 420 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMFFRR(val) MCR14(val, 1, c0, c10, 0) val 421 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMFFLR(val) MCR14(val, 1, c0, c11, 0) val 422 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMVDEVR(val) MCR14(val, 1, c0, c12, 0) val 423 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMVDCR1(val) MCR14(val, 1, c0, c13, 0) val 424 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMVDCR2(val) MCR14(val, 1, c0, c14, 0) val 425 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMVDCR3(val) MCR14(val, 1, c0, c15, 0) val 426 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR0(val) MCR14(val, 1, c0, c0, 1) val 427 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR1(val) MCR14(val, 1, c0, c1, 1) val 428 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR2(val) MCR14(val, 1, c0, c2, 1) val 429 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR3(val) MCR14(val, 1, c0, c3, 1) val 430 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR4(val) MCR14(val, 1, c0, c4, 1) val 431 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR5(val) MCR14(val, 1, c0, c5, 1) val 432 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR6(val) MCR14(val, 1, c0, c6, 1) val 433 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR7(val) MCR14(val, 1, c0, c7, 1) val 434 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR8(val) MCR14(val, 1, c0, c8, 1) val 435 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR9(val) MCR14(val, 1, c0, c9, 1) val 436 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR10(val) MCR14(val, 1, c0, c10, 1) val 437 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR11(val) MCR14(val, 1, c0, c11, 1) val 438 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR12(val) MCR14(val, 1, c0, c12, 1) val 439 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR13(val) MCR14(val, 1, c0, c13, 1) val 440 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR14(val) MCR14(val, 1, c0, c14, 1) val 441 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR15(val) MCR14(val, 1, c0, c15, 1) val 442 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR0(val) MCR14(val, 1, c0, c0, 2) val 443 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR1(val) MCR14(val, 1, c0, c1, 2) val 444 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR2(val) MCR14(val, 1, c0, c2, 2) val 445 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR3(val) MCR14(val, 1, c0, c3, 2) val 446 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR4(val) MCR14(val, 1, c0, c4, 2) val 447 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR5(val) MCR14(val, 1, c0, c5, 2) val 448 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR6(val) MCR14(val, 1, c0, c6, 2) val 449 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR7(val) MCR14(val, 1, c0, c7, 2) val 450 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR8(val) MCR14(val, 1, c0, c8, 2) val 451 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR9(val) MCR14(val, 1, c0, c9, 2) val 452 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR10(val) MCR14(val, 1, c0, c10, 2) val 453 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR11(val) MCR14(val, 1, c0, c11, 2) val 454 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR12(val) MCR14(val, 1, c0, c12, 2) val 455 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR13(val) MCR14(val, 1, c0, c13, 2) val 456 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR14(val) MCR14(val, 1, c0, c14, 2) val 457 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR15(val) MCR14(val, 1, c0, c15, 2) val 458 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR0(val) MCR14(val, 1, c0, c0, 3) val 459 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR2(val) MCR14(val, 1, c0, c2, 3) val 460 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR4(val) MCR14(val, 1, c0, c4, 3) val 461 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR6(val) MCR14(val, 1, c0, c6, 3) val 462 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR8(val) MCR14(val, 1, c0, c8, 3) val 463 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR10(val) MCR14(val, 1, c0, c10, 3) val 464 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR12(val) MCR14(val, 1, c0, c12, 3) val 465 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR14(val) MCR14(val, 1, c0, c14, 3) val 466 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR0(val) MCR14(val, 1, c0, c0, 4) val 467 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR2(val) MCR14(val, 1, c0, c2, 4) val 468 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR4(val) MCR14(val, 1, c0, c4, 4) val 469 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR6(val) MCR14(val, 1, c0, c6, 4) val 470 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR8(val) MCR14(val, 1, c0, c8, 4) val 471 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR10(val) MCR14(val, 1, c0, c10, 4) val 472 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR12(val) MCR14(val, 1, c0, c12, 4) val 473 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR14(val) MCR14(val, 1, c0, c14, 4) val 474 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDVR0(val) MCR14(val, 1, c0, c0, 5) val 475 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDVR1(val) MCR14(val, 1, c0, c1, 5) val 476 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDVR2(val) MCR14(val, 1, c0, c2, 5) val 477 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDVR3(val) MCR14(val, 1, c0, c3, 5) val 478 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTENR0(val) MCR14(val, 1, c0, c4, 5) val 479 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTENR1(val) MCR14(val, 1, c0, c5, 5) val 480 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTENR2(val) MCR14(val, 1, c0, c6, 5) val 481 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTENR3(val) MCR14(val, 1, c0, c7, 5) val 482 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDEVR0(val) MCR14(val, 1, c0, c8, 5) val 483 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDEVR1(val) MCR14(val, 1, c0, c9, 5) val 484 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDEVR2(val) MCR14(val, 1, c0, c10, 5) val 485 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDEVR3(val) MCR14(val, 1, c0, c11, 5) val 486 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTVR0(val) MCR14(val, 1, c0, c12, 5) val 487 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTVR1(val) MCR14(val, 1, c0, c13, 5) val 488 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTVR2(val) MCR14(val, 1, c0, c14, 5) val 489 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTVR3(val) MCR14(val, 1, c0, c15, 5) val 490 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQ12EVR(val) MCR14(val, 1, c0, c0, 6) val 491 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQ21EVR(val) MCR14(val, 1, c0, c1, 6) val 492 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQ23EVR(val) MCR14(val, 1, c0, c2, 6) val 493 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQ31EVR(val) MCR14(val, 1, c0, c3, 6) val 494 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQ32EVR(val) MCR14(val, 1, c0, c4, 6) val 495 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQ13EVR(val) MCR14(val, 1, c0, c5, 6) val 496 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQR(val) MCR14(val, 1, c0, c7, 6) val 497 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMEXTOUTEVR0(val) MCR14(val, 1, c0, c8, 6) val 498 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMEXTOUTEVR1(val) MCR14(val, 1, c0, c9, 6) val 499 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMEXTOUTEVR2(val) MCR14(val, 1, c0, c10, 6) val 500 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMEXTOUTEVR3(val) MCR14(val, 1, c0, c11, 6) val 501 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCIDCVR0(val) MCR14(val, 1, c0, c12, 6) val 502 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCIDCVR1(val) MCR14(val, 1, c0, c13, 6) val 503 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCIDCVR2(val) MCR14(val, 1, c0, c14, 6) val 504 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCIDCMR(val) MCR14(val, 1, c0, c15, 6) val 505 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC0(val) MCR14(val, 1, c0, c0, 7) val 506 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC1(val) MCR14(val, 1, c0, c1, 7) val 507 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC2(val) MCR14(val, 1, c0, c2, 7) val 508 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC3(val) MCR14(val, 1, c0, c3, 7) val 509 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC4(val) MCR14(val, 1, c0, c4, 7) val 510 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC5(val) MCR14(val, 1, c0, c5, 7) val 511 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC6(val) MCR14(val, 1, c0, c6, 7) val 512 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC7(val) MCR14(val, 1, c0, c7, 7) val 514 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSYNCFR(val) MCR14(val, 1, c0, c8, 7) val 515 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMEXTINSELR(val) MCR14(val, 1, c0, c11, 7) val 516 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTESSEICR(val) MCR14(val, 1, c0, c12, 7) val 517 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMEIBCR(val) MCR14(val, 1, c0, c13, 7) val 518 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTSEVR(val) MCR14(val, 1, c0, c14, 7) val 519 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMAUXCR(val) MCR14(val, 1, c0, c15, 7) val 520 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTRACEIDR(val) MCR14(val, 1, c1, c0, 0) val 521 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIDR2(val) MCR14(val, 1, c1, c2, 0) val 522 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMVMIDCVR(val) MCR14(val, 1, c1, c0, 1) val 523 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMOSLAR(val) MCR14(val, 1, c1, c0, 4) val 525 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMOSSRR(val) MCR14(val, 1, c1, c2, 4) val 526 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMPDCR(val) MCR14(val, 1, c1, c4, 4) val 527 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMPDSR(val) MCR14(val, 1, c1, c5, 4) val 528 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMITCTRL(val) MCR14(val, 1, c7, c0, 4) val 529 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCLAIMSET(val) MCR14(val, 1, c7, c8, 6) val 530 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCLAIMCLR(val) MCR14(val, 1, c7, c9, 6) val 532 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMLAR(val) MCR14(val, 1, c7, c12, 6) val 20 arch/arm/include/asm/hardware/ioc.h #define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off)) val 22 arch/arm/include/asm/hardware/iomd.h #define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off)) val 23 arch/arm/include/asm/hardware/iomd.h #define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off)) val 16 arch/arm/include/asm/hardware/locomo.h #define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); }) val 14 arch/arm/include/asm/hardware/memc.h extern void memc_write(unsigned int reg, unsigned long val); val 126 arch/arm/include/asm/hw_breakpoint.h unsigned long val, void *data); val 68 arch/arm/include/asm/io.h static inline void __raw_writew(u16 val, volatile void __iomem *addr) val 71 arch/arm/include/asm/io.h : : "Q" (*(volatile u16 __force *)addr), "r" (val)); val 77 arch/arm/include/asm/io.h u16 val; val 79 arch/arm/include/asm/io.h : "=r" (val) val 81 arch/arm/include/asm/io.h return val; val 86 arch/arm/include/asm/io.h static inline void __raw_writeb(u8 val, volatile void __iomem *addr) val 89 arch/arm/include/asm/io.h : : "Qo" (*(volatile u8 __force *)addr), "r" (val)); val 93 arch/arm/include/asm/io.h static inline void __raw_writel(u32 val, volatile void __iomem *addr) val 96 arch/arm/include/asm/io.h : : "Qo" (*(volatile u32 __force *)addr), "r" (val)); val 102 arch/arm/include/asm/io.h u8 val; val 104 arch/arm/include/asm/io.h : "=r" (val) val 106 arch/arm/include/asm/io.h return val; val 112 arch/arm/include/asm/io.h u32 val; val 114 arch/arm/include/asm/io.h : "=r" (val) val 116 arch/arm/include/asm/io.h return val; val 44 arch/arm/include/asm/kprobes.h unsigned long val, void *data); val 6 arch/arm/include/asm/krait-l2-accessors.h extern void krait_set_l2_indirect_reg(u32 addr, u32 val); val 68 arch/arm/include/asm/kvm_emulate.h unsigned long val) val 70 arch/arm/include/asm/kvm_emulate.h *vcpu_reg(vcpu, reg_num) = val; val 26 arch/arm/include/asm/mc146818rtc.h #define CMOS_WRITE(val, addr) ({ \ val 28 arch/arm/include/asm/mc146818rtc.h outb_p((val),RTC_PORT(1)); \ val 38 arch/arm/include/asm/module.h u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val); val 198 arch/arm/include/asm/pgtable-3level.h #define pmd_isset(pmd, val) ((u32)(val) == (val) ? pmd_val(pmd) & (val) \ val 199 arch/arm/include/asm/pgtable-3level.h : !!(pmd_val(pmd) & (val))) val 200 arch/arm/include/asm/pgtable-3level.h #define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val))) val 49 arch/arm/include/asm/pgtable-nommu.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 219 arch/arm/include/asm/pgtable.h #define pte_isset(pte, val) ((u32)(val) == (val) ? pte_val(pte) & (val) \ val 220 arch/arm/include/asm/pgtable.h : !!(pte_val(pte) & (val))) val 221 arch/arm/include/asm/pgtable.h #define pte_isclear(pte, val) (!(pte_val(pte) & (val))) val 345 arch/arm/include/asm/pgtable.h #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) val 346 arch/arm/include/asm/pgtable.h #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) val 350 arch/arm/include/asm/pgtable.h #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) val 101 arch/arm/include/asm/ptrace.h unsigned long val) val 103 arch/arm/include/asm/ptrace.h instruction_pointer(regs) = val; val 49 arch/arm/include/asm/syscall.h int error, long val) val 51 arch/arm/include/asm/syscall.h regs->ARM_r0 = (long) error ? error : val; val 58 arch/arm/include/asm/tls.h static inline void set_tls(unsigned long val) val 64 arch/arm/include/asm/tls.h thread->tp_value[0] = val; val 83 arch/arm/include/asm/tls.h : : "r" (val)); val 93 arch/arm/include/asm/tls.h *((unsigned int *)0xffff0ff0) = val; val 110 arch/arm/include/asm/tls.h static inline void set_tpuser(unsigned long val) val 117 arch/arm/include/asm/tls.h : : "r" (val)); val 20 arch/arm/include/asm/xen/events.h #define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((long long*)(ptr),\ val 22 arch/arm/include/asm/xen/events.h counter), (val)) val 96 arch/arm/kernel/hw_breakpoint.c u32 val = 0; val 99 arch/arm/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); val 100 arch/arm/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); val 101 arch/arm/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); val 102 arch/arm/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); val 108 arch/arm/kernel/hw_breakpoint.c return val; val 111 arch/arm/kernel/hw_breakpoint.c static void write_wb_reg(int n, u32 val) val 114 arch/arm/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); val 115 arch/arm/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); val 116 arch/arm/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); val 117 arch/arm/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); val 687 arch/arm/kernel/hw_breakpoint.c u32 val, ctrl_reg, alignment_mask; val 719 arch/arm/kernel/hw_breakpoint.c val = read_wb_reg(ARM_BASE_WVR + i); val 720 arch/arm/kernel/hw_breakpoint.c if (val != (addr & ~alignment_mask)) val 792 arch/arm/kernel/hw_breakpoint.c u32 ctrl_reg, val, addr; val 814 arch/arm/kernel/hw_breakpoint.c val = read_wb_reg(ARM_BASE_BVR + i); val 815 arch/arm/kernel/hw_breakpoint.c if (val != (addr & ~0x3)) val 925 arch/arm/kernel/hw_breakpoint.c u32 val; val 945 arch/arm/kernel/hw_breakpoint.c ARM_DBG_READ(c1, c5, 4, val); val 946 arch/arm/kernel/hw_breakpoint.c if ((val & 0x1) == 0) val 956 arch/arm/kernel/hw_breakpoint.c ARM_DBG_READ(c1, c3, 4, val); val 957 arch/arm/kernel/hw_breakpoint.c if ((val & 0x1) == 1) val 1138 arch/arm/kernel/hw_breakpoint.c unsigned long val, void *data) val 36 arch/arm/kernel/module-plts.c u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val) val 53 arch/arm/kernel/module-plts.c if (plt->lit[idx] == val) val 68 arch/arm/kernel/module-plts.c { val, } val 71 arch/arm/kernel/module-plts.c plt->lit[idx] = val; val 182 arch/arm/kernel/perf_event_v6.c u32 val; val 183 arch/arm/kernel/perf_event_v6.c asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); val 184 arch/arm/kernel/perf_event_v6.c return val; val 188 arch/arm/kernel/perf_event_v6.c armv6_pmcr_write(unsigned long val) val 190 arch/arm/kernel/perf_event_v6.c asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); val 271 arch/arm/kernel/perf_event_v6.c unsigned long val, mask, evt, flags; val 298 arch/arm/kernel/perf_event_v6.c val = armv6_pmcr_read(); val 299 arch/arm/kernel/perf_event_v6.c val &= ~mask; val 300 arch/arm/kernel/perf_event_v6.c val |= evt; val 301 arch/arm/kernel/perf_event_v6.c armv6_pmcr_write(val); val 365 arch/arm/kernel/perf_event_v6.c unsigned long flags, val; val 369 arch/arm/kernel/perf_event_v6.c val = armv6_pmcr_read(); val 370 arch/arm/kernel/perf_event_v6.c val |= ARMV6_PMCR_ENABLE; val 371 arch/arm/kernel/perf_event_v6.c armv6_pmcr_write(val); val 377 arch/arm/kernel/perf_event_v6.c unsigned long flags, val; val 381 arch/arm/kernel/perf_event_v6.c val = armv6_pmcr_read(); val 382 arch/arm/kernel/perf_event_v6.c val &= ~ARMV6_PMCR_ENABLE; val 383 arch/arm/kernel/perf_event_v6.c armv6_pmcr_write(val); val 422 arch/arm/kernel/perf_event_v6.c unsigned long val, mask, evt, flags; val 448 arch/arm/kernel/perf_event_v6.c val = armv6_pmcr_read(); val 449 arch/arm/kernel/perf_event_v6.c val &= ~mask; val 450 arch/arm/kernel/perf_event_v6.c val |= evt; val 451 arch/arm/kernel/perf_event_v6.c armv6_pmcr_write(val); val 457 arch/arm/kernel/perf_event_v6.c unsigned long val, mask, flags, evt = 0; val 479 arch/arm/kernel/perf_event_v6.c val = armv6_pmcr_read(); val 480 arch/arm/kernel/perf_event_v6.c val &= ~mask; val 481 arch/arm/kernel/perf_event_v6.c val |= evt; val 482 arch/arm/kernel/perf_event_v6.c armv6_pmcr_write(val); val 711 arch/arm/kernel/perf_event_v7.c u32 val; val 712 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); val 713 arch/arm/kernel/perf_event_v7.c return val; val 716 arch/arm/kernel/perf_event_v7.c static inline void armv7_pmnc_write(u32 val) val 718 arch/arm/kernel/perf_event_v7.c val &= ARMV7_PMNC_MASK; val 720 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); val 783 arch/arm/kernel/perf_event_v7.c static inline void armv7_pmnc_write_evtsel(int idx, u32 val) val 786 arch/arm/kernel/perf_event_v7.c val &= ARMV7_EVTYPE_MASK; val 787 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); val 820 arch/arm/kernel/perf_event_v7.c u32 val; val 823 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); val 826 arch/arm/kernel/perf_event_v7.c val &= ARMV7_FLAG_MASK; val 827 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); val 829 arch/arm/kernel/perf_event_v7.c return val; val 835 arch/arm/kernel/perf_event_v7.c u32 val; val 840 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); val 841 arch/arm/kernel/perf_event_v7.c pr_info("PMNC =0x%08x\n", val); val 843 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); val 844 arch/arm/kernel/perf_event_v7.c pr_info("CNTENS=0x%08x\n", val); val 846 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); val 847 arch/arm/kernel/perf_event_v7.c pr_info("INTENS=0x%08x\n", val); val 849 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); val 850 arch/arm/kernel/perf_event_v7.c pr_info("FLAGS =0x%08x\n", val); val 852 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); val 853 arch/arm/kernel/perf_event_v7.c pr_info("SELECT=0x%08x\n", val); val 855 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); val 856 arch/arm/kernel/perf_event_v7.c pr_info("CCNT =0x%08x\n", val); val 861 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); val 863 arch/arm/kernel/perf_event_v7.c ARMV7_IDX_TO_COUNTER(cnt), val); val 864 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); val 866 arch/arm/kernel/perf_event_v7.c ARMV7_IDX_TO_COUNTER(cnt), val); val 1096 arch/arm/kernel/perf_event_v7.c u32 idx, nb_cnt = cpu_pmu->num_events, val; val 1099 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); val 1100 arch/arm/kernel/perf_event_v7.c val |= ARMV7_SDER_SUNIDEN; val 1101 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); val 1332 arch/arm/kernel/perf_event_v7.c u32 val; val 1336 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); val 1339 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); val 1342 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); val 1348 arch/arm/kernel/perf_event_v7.c return val; val 1351 arch/arm/kernel/perf_event_v7.c static void krait_write_pmresrn(int n, u32 val) val 1355 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); val 1358 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); val 1361 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); val 1370 arch/arm/kernel/perf_event_v7.c u32 val; val 1371 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); val 1372 arch/arm/kernel/perf_event_v7.c return val; val 1375 arch/arm/kernel/perf_event_v7.c static void venum_write_pmresr(u32 val) val 1377 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); val 1417 arch/arm/kernel/perf_event_v7.c u32 val; val 1431 arch/arm/kernel/perf_event_v7.c val = KRAIT_VPMRESR0_GROUP0; val 1433 arch/arm/kernel/perf_event_v7.c val = krait_get_pmresrn_event(region); val 1434 arch/arm/kernel/perf_event_v7.c val += group; val 1436 arch/arm/kernel/perf_event_v7.c val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); val 1437 arch/arm/kernel/perf_event_v7.c armv7_pmnc_write_evtsel(idx, val); val 1441 arch/arm/kernel/perf_event_v7.c val = venum_read_pmresr(); val 1442 arch/arm/kernel/perf_event_v7.c val &= ~mask; val 1443 arch/arm/kernel/perf_event_v7.c val |= code << group_shift; val 1444 arch/arm/kernel/perf_event_v7.c val |= PMRESRn_EN; val 1445 arch/arm/kernel/perf_event_v7.c venum_write_pmresr(val); val 1448 arch/arm/kernel/perf_event_v7.c val = krait_read_pmresrn(region); val 1449 arch/arm/kernel/perf_event_v7.c val &= ~mask; val 1450 arch/arm/kernel/perf_event_v7.c val |= code << group_shift; val 1451 arch/arm/kernel/perf_event_v7.c val |= PMRESRn_EN; val 1452 arch/arm/kernel/perf_event_v7.c krait_write_pmresrn(region, val); val 1456 arch/arm/kernel/perf_event_v7.c static u32 clear_pmresrn_group(u32 val, int group) val 1463 arch/arm/kernel/perf_event_v7.c val &= ~mask; val 1466 arch/arm/kernel/perf_event_v7.c if (val & ~PMRESRn_EN) val 1467 arch/arm/kernel/perf_event_v7.c return val |= PMRESRn_EN; val 1474 arch/arm/kernel/perf_event_v7.c u32 val; val 1482 arch/arm/kernel/perf_event_v7.c val = venum_read_pmresr(); val 1483 arch/arm/kernel/perf_event_v7.c val = clear_pmresrn_group(val, group); val 1484 arch/arm/kernel/perf_event_v7.c venum_write_pmresr(val); val 1487 arch/arm/kernel/perf_event_v7.c val = krait_read_pmresrn(region); val 1488 arch/arm/kernel/perf_event_v7.c val = clear_pmresrn_group(val, group); val 1489 arch/arm/kernel/perf_event_v7.c krait_write_pmresrn(region, val); val 1711 arch/arm/kernel/perf_event_v7.c u32 val; val 1715 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); val 1718 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); val 1721 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); val 1724 arch/arm/kernel/perf_event_v7.c asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); val 1730 arch/arm/kernel/perf_event_v7.c return val; val 1733 arch/arm/kernel/perf_event_v7.c static void scorpion_write_pmresrn(int n, u32 val) val 1737 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); val 1740 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); val 1743 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); val 1746 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); val 1764 arch/arm/kernel/perf_event_v7.c u32 val; val 1778 arch/arm/kernel/perf_event_v7.c val = SCORPION_VLPM_GROUP0; val 1780 arch/arm/kernel/perf_event_v7.c val = scorpion_get_pmresrn_event(region); val 1781 arch/arm/kernel/perf_event_v7.c val += group; val 1783 arch/arm/kernel/perf_event_v7.c val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); val 1784 arch/arm/kernel/perf_event_v7.c armv7_pmnc_write_evtsel(idx, val); val 1790 arch/arm/kernel/perf_event_v7.c val = venum_read_pmresr(); val 1791 arch/arm/kernel/perf_event_v7.c val &= ~mask; val 1792 arch/arm/kernel/perf_event_v7.c val |= code << group_shift; val 1793 arch/arm/kernel/perf_event_v7.c val |= PMRESRn_EN; val 1794 arch/arm/kernel/perf_event_v7.c venum_write_pmresr(val); val 1797 arch/arm/kernel/perf_event_v7.c val = scorpion_read_pmresrn(region); val 1798 arch/arm/kernel/perf_event_v7.c val &= ~mask; val 1799 arch/arm/kernel/perf_event_v7.c val |= code << group_shift; val 1800 arch/arm/kernel/perf_event_v7.c val |= PMRESRn_EN; val 1801 arch/arm/kernel/perf_event_v7.c scorpion_write_pmresrn(region, val); val 1807 arch/arm/kernel/perf_event_v7.c u32 val; val 1815 arch/arm/kernel/perf_event_v7.c val = venum_read_pmresr(); val 1816 arch/arm/kernel/perf_event_v7.c val = clear_pmresrn_group(val, group); val 1817 arch/arm/kernel/perf_event_v7.c venum_write_pmresr(val); val 1820 arch/arm/kernel/perf_event_v7.c val = scorpion_read_pmresrn(region); val 1821 arch/arm/kernel/perf_event_v7.c val = clear_pmresrn_group(val, group); val 1822 arch/arm/kernel/perf_event_v7.c scorpion_write_pmresrn(region, val); val 108 arch/arm/kernel/perf_event_xscale.c u32 val; val 109 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); val 110 arch/arm/kernel/perf_event_xscale.c return val; val 114 arch/arm/kernel/perf_event_xscale.c xscale1pmu_write_pmnc(u32 val) val 117 arch/arm/kernel/perf_event_xscale.c val &= 0xffff77f; val 118 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); val 206 arch/arm/kernel/perf_event_xscale.c unsigned long val, mask, evt, flags; val 233 arch/arm/kernel/perf_event_xscale.c val = xscale1pmu_read_pmnc(); val 234 arch/arm/kernel/perf_event_xscale.c val &= ~mask; val 235 arch/arm/kernel/perf_event_xscale.c val |= evt; val 236 arch/arm/kernel/perf_event_xscale.c xscale1pmu_write_pmnc(val); val 242 arch/arm/kernel/perf_event_xscale.c unsigned long val, mask, evt, flags; val 267 arch/arm/kernel/perf_event_xscale.c val = xscale1pmu_read_pmnc(); val 268 arch/arm/kernel/perf_event_xscale.c val &= ~mask; val 269 arch/arm/kernel/perf_event_xscale.c val |= evt; val 270 arch/arm/kernel/perf_event_xscale.c xscale1pmu_write_pmnc(val); val 303 arch/arm/kernel/perf_event_xscale.c unsigned long flags, val; val 307 arch/arm/kernel/perf_event_xscale.c val = xscale1pmu_read_pmnc(); val 308 arch/arm/kernel/perf_event_xscale.c val |= XSCALE_PMU_ENABLE; val 309 arch/arm/kernel/perf_event_xscale.c xscale1pmu_write_pmnc(val); val 315 arch/arm/kernel/perf_event_xscale.c unsigned long flags, val; val 319 arch/arm/kernel/perf_event_xscale.c val = xscale1pmu_read_pmnc(); val 320 arch/arm/kernel/perf_event_xscale.c val &= ~XSCALE_PMU_ENABLE; val 321 arch/arm/kernel/perf_event_xscale.c xscale1pmu_write_pmnc(val); val 329 arch/arm/kernel/perf_event_xscale.c u32 val = 0; val 333 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val)); val 336 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val)); val 339 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val)); val 343 arch/arm/kernel/perf_event_xscale.c return val; val 346 arch/arm/kernel/perf_event_xscale.c static inline void xscale1pmu_write_counter(struct perf_event *event, u64 val) val 353 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val)); val 356 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val)); val 359 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val)); val 411 arch/arm/kernel/perf_event_xscale.c u32 val; val 412 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val)); val 414 arch/arm/kernel/perf_event_xscale.c return val & 0xff000009; val 418 arch/arm/kernel/perf_event_xscale.c xscale2pmu_write_pmnc(u32 val) val 421 arch/arm/kernel/perf_event_xscale.c val &= 0xf; val 422 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val)); val 428 arch/arm/kernel/perf_event_xscale.c u32 val; val 429 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val)); val 430 arch/arm/kernel/perf_event_xscale.c return val; val 434 arch/arm/kernel/perf_event_xscale.c xscale2pmu_write_overflow_flags(u32 val) val 436 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val)); val 442 arch/arm/kernel/perf_event_xscale.c u32 val; val 443 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val)); val 444 arch/arm/kernel/perf_event_xscale.c return val; val 448 arch/arm/kernel/perf_event_xscale.c xscale2pmu_write_event_select(u32 val) val 450 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val)); val 456 arch/arm/kernel/perf_event_xscale.c u32 val; val 457 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val)); val 458 arch/arm/kernel/perf_event_xscale.c return val; val 462 arch/arm/kernel/perf_event_xscale.c xscale2pmu_write_int_enable(u32 val) val 464 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val)); val 666 arch/arm/kernel/perf_event_xscale.c unsigned long flags, val; val 670 arch/arm/kernel/perf_event_xscale.c val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; val 671 arch/arm/kernel/perf_event_xscale.c val |= XSCALE_PMU_ENABLE; val 672 arch/arm/kernel/perf_event_xscale.c xscale2pmu_write_pmnc(val); val 678 arch/arm/kernel/perf_event_xscale.c unsigned long flags, val; val 682 arch/arm/kernel/perf_event_xscale.c val = xscale2pmu_read_pmnc(); val 683 arch/arm/kernel/perf_event_xscale.c val &= ~XSCALE_PMU_ENABLE; val 684 arch/arm/kernel/perf_event_xscale.c xscale2pmu_write_pmnc(val); val 692 arch/arm/kernel/perf_event_xscale.c u32 val = 0; val 696 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val)); val 699 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val)); val 702 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val)); val 705 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val)); val 708 arch/arm/kernel/perf_event_xscale.c asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val)); val 712 arch/arm/kernel/perf_event_xscale.c return val; val 715 arch/arm/kernel/perf_event_xscale.c static inline void xscale2pmu_write_counter(struct perf_event *event, u64 val) val 722 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val)); val 725 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val)); val 728 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val)); val 731 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val)); val 734 arch/arm/kernel/perf_event_xscale.c asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val)); val 279 arch/arm/kernel/ptrace.c unsigned long val) val 287 arch/arm/kernel/ptrace.c return put_user_reg(tsk, off >> 2, val); val 758 arch/arm/kernel/smp.c unsigned long val, void *data) val 781 arch/arm/kernel/smp.c if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || val 782 arch/arm/kernel/smp.c (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { val 77 arch/arm/kernel/smp_scu.c unsigned int val; val 83 arch/arm/kernel/smp_scu.c val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu); val 84 arch/arm/kernel/smp_scu.c val &= ~SCU_CPU_STATUS_MASK; val 85 arch/arm/kernel/smp_scu.c val |= mode; val 86 arch/arm/kernel/smp_scu.c writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu); val 114 arch/arm/kernel/smp_scu.c unsigned int val; val 120 arch/arm/kernel/smp_scu.c val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu); val 121 arch/arm/kernel/smp_scu.c val &= SCU_CPU_STATUS_MASK; val 123 arch/arm/kernel/smp_scu.c return val; val 142 arch/arm/kernel/traps.c unsigned long val; val 143 arch/arm/kernel/traps.c if (__get_user(val, (unsigned long *)p) == 0) val 144 arch/arm/kernel/traps.c sprintf(str + i * 9, " %08lx", val); val 169 arch/arm/kernel/traps.c unsigned int val, bad; val 172 arch/arm/kernel/traps.c bad = get_user(val, &((u16 *)addr)[i]); val 174 arch/arm/kernel/traps.c bad = get_user(val, &((u32 *)addr)[i]); val 178 arch/arm/kernel/traps.c width, val); val 64 arch/arm/kvm/coproc.c u64 val) val 66 arch/arm/kvm/coproc.c vcpu_cp15(vcpu, r->reg) = val & 0xffffffff; val 67 arch/arm/kvm/coproc.c vcpu_cp15(vcpu, r->reg + 1) = val >> 32; val 73 arch/arm/kvm/coproc.c u64 val; val 75 arch/arm/kvm/coproc.c val = vcpu_cp15(vcpu, r->reg + 1); val 76 arch/arm/kvm/coproc.c val = val << 32; val 77 arch/arm/kvm/coproc.c val = val | vcpu_cp15(vcpu, r->reg); val 78 arch/arm/kvm/coproc.c return val; val 284 arch/arm/kvm/coproc.c u32 val; val 287 arch/arm/kvm/coproc.c val = *vcpu_reg(vcpu, p->Rt1); val 289 arch/arm/kvm/coproc.c TIMER_PTIMER, TIMER_REG_TVAL, val); val 291 arch/arm/kvm/coproc.c val = kvm_arm_timer_read_sysreg(vcpu, val 293 arch/arm/kvm/coproc.c *vcpu_reg(vcpu, p->Rt1) = val; val 303 arch/arm/kvm/coproc.c u32 val; val 306 arch/arm/kvm/coproc.c val = *vcpu_reg(vcpu, p->Rt1); val 308 arch/arm/kvm/coproc.c TIMER_PTIMER, TIMER_REG_CTL, val); val 310 arch/arm/kvm/coproc.c val = kvm_arm_timer_read_sysreg(vcpu, val 312 arch/arm/kvm/coproc.c *vcpu_reg(vcpu, p->Rt1) = val; val 322 arch/arm/kvm/coproc.c u64 val; val 325 arch/arm/kvm/coproc.c val = (u64)*vcpu_reg(vcpu, p->Rt2) << 32; val 326 arch/arm/kvm/coproc.c val |= *vcpu_reg(vcpu, p->Rt1); val 328 arch/arm/kvm/coproc.c TIMER_PTIMER, TIMER_REG_CVAL, val); val 330 arch/arm/kvm/coproc.c val = kvm_arm_timer_read_sysreg(vcpu, val 332 arch/arm/kvm/coproc.c *vcpu_reg(vcpu, p->Rt1) = val; val 333 arch/arm/kvm/coproc.c *vcpu_reg(vcpu, p->Rt2) = val >> 32; val 546 arch/arm/kvm/coproc.c unsigned long val; \ val 547 arch/arm/kvm/coproc.c val = (x)->CRn << 11; \ val 548 arch/arm/kvm/coproc.c val |= (x)->CRm << 7; \ val 549 arch/arm/kvm/coproc.c val |= (x)->Op1 << 4; \ val 550 arch/arm/kvm/coproc.c val |= (x)->Op2 << 1; \ val 551 arch/arm/kvm/coproc.c val |= !(x)->is_64bit; \ val 552 arch/arm/kvm/coproc.c val; \ val 804 arch/arm/kvm/coproc.c u32 val; \ val 809 arch/arm/kvm/coproc.c ", " __stringify(op2) "\n" : "=r" (val)); \ val 810 arch/arm/kvm/coproc.c ((struct coproc_reg *)r)->val = val; \ val 867 arch/arm/kvm/coproc.c static int reg_from_user(void *val, const void __user *uaddr, u64 id) val 869 arch/arm/kvm/coproc.c if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) val 878 arch/arm/kvm/coproc.c static int reg_to_user(void __user *uaddr, const void *val, u64 id) val 880 arch/arm/kvm/coproc.c if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) val 900 arch/arm/kvm/coproc.c u32 val = r->val; val 902 arch/arm/kvm/coproc.c ret = reg_to_user(uaddr, &val, id); val 904 arch/arm/kvm/coproc.c ret = reg_to_user(uaddr, &r->val, id); val 914 arch/arm/kvm/coproc.c u64 val; val 928 arch/arm/kvm/coproc.c val = val32; val 930 arch/arm/kvm/coproc.c err = reg_from_user(&val, uaddr, id); val 936 arch/arm/kvm/coproc.c if (r->val != val) val 942 arch/arm/kvm/coproc.c static bool is_valid_cache(u32 val) val 946 arch/arm/kvm/coproc.c if (val >= CSSELR_MAX) val 950 arch/arm/kvm/coproc.c level = (val >> 1); val 957 arch/arm/kvm/coproc.c return (val & 1); val 960 arch/arm/kvm/coproc.c return !(val & 1); val 987 arch/arm/kvm/coproc.c u32 val; val 999 arch/arm/kvm/coproc.c val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) val 1001 arch/arm/kvm/coproc.c if (!is_valid_cache(val)) val 1004 arch/arm/kvm/coproc.c return put_user(get_ccsidr(val), uval); val 1012 arch/arm/kvm/coproc.c u32 val, newval; val 1024 arch/arm/kvm/coproc.c val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) val 1026 arch/arm/kvm/coproc.c if (!is_valid_cache(val)) val 1033 arch/arm/kvm/coproc.c if (newval != get_ccsidr(val)) val 1089 arch/arm/kvm/coproc.c u32 val; val 1117 arch/arm/kvm/coproc.c val = fmrx(MVFR0); val 1118 arch/arm/kvm/coproc.c return reg_to_user(uaddr, &val, id); val 1120 arch/arm/kvm/coproc.c val = fmrx(MVFR1); val 1121 arch/arm/kvm/coproc.c return reg_to_user(uaddr, &val, id); val 1123 arch/arm/kvm/coproc.c val = fmrx(FPSID); val 1124 arch/arm/kvm/coproc.c return reg_to_user(uaddr, &val, id); val 1133 arch/arm/kvm/coproc.c u32 val; val 1162 arch/arm/kvm/coproc.c if (reg_from_user(&val, uaddr, id)) val 1164 arch/arm/kvm/coproc.c if (val != fmrx(MVFR0)) val 1168 arch/arm/kvm/coproc.c if (reg_from_user(&val, uaddr, id)) val 1170 arch/arm/kvm/coproc.c if (val != fmrx(MVFR1)) val 1174 arch/arm/kvm/coproc.c if (reg_from_user(&val, uaddr, id)) val 1176 arch/arm/kvm/coproc.c if (val != fmrx(FPSID)) val 1223 arch/arm/kvm/coproc.c u64 val; val 1225 arch/arm/kvm/coproc.c val = vcpu_cp15_reg64_get(vcpu, r); val 1226 arch/arm/kvm/coproc.c ret = reg_to_user(uaddr, &val, reg->id); val 1252 arch/arm/kvm/coproc.c u64 val; val 1254 arch/arm/kvm/coproc.c ret = reg_from_user(&val, uaddr, reg->id); val 1256 arch/arm/kvm/coproc.c vcpu_cp15_reg64_set(vcpu, r, val); val 1277 arch/arm/kvm/coproc.c u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; val 1280 arch/arm/kvm/coproc.c val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; val 1284 arch/arm/kvm/coproc.c if (put_user(val | i, uindices)) val 1293 arch/arm/kvm/coproc.c u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT); val 1295 arch/arm/kvm/coproc.c val |= KVM_REG_SIZE_U64; val 1296 arch/arm/kvm/coproc.c val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); val 1304 arch/arm/kvm/coproc.c val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT); val 1306 arch/arm/kvm/coproc.c val |= KVM_REG_SIZE_U32; val 1307 arch/arm/kvm/coproc.c val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); val 1308 arch/arm/kvm/coproc.c val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT); val 1309 arch/arm/kvm/coproc.c val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT); val 1310 arch/arm/kvm/coproc.c val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT); val 1312 arch/arm/kvm/coproc.c return val; val 42 arch/arm/kvm/coproc.h u64 val; val 85 arch/arm/kvm/coproc.h vcpu_cp15(vcpu, r->reg) = r->val; val 64 arch/arm/kvm/guest.c u64 off, val; val 74 arch/arm/kvm/guest.c if (get_user(val, uaddr) != 0) val 78 arch/arm/kvm/guest.c unsigned long mode = val & MODE_MASK; val 92 arch/arm/kvm/guest.c ((u32 *)regs)[off] = val; val 136 arch/arm/kvm/guest.c u64 val; val 139 arch/arm/kvm/guest.c ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id)); val 143 arch/arm/kvm/guest.c return kvm_arm_timer_set_reg(vcpu, reg->id, val); val 149 arch/arm/kvm/guest.c u64 val; val 151 arch/arm/kvm/guest.c val = kvm_arm_timer_get_reg(vcpu, reg->id); val 152 arch/arm/kvm/guest.c return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0; val 14 arch/arm/kvm/hyp/s2-setup.c u64 val; val 16 arch/arm/kvm/hyp/s2-setup.c val = read_sysreg(VTCR) & ~VTCR_MASK; val 18 arch/arm/kvm/hyp/s2-setup.c val |= read_sysreg(HTCR) & VTCR_HTCR_SH; val 19 arch/arm/kvm/hyp/s2-setup.c val |= KVM_VTCR_SL0 | KVM_VTCR_T0SZ | KVM_VTCR_S; val 21 arch/arm/kvm/hyp/s2-setup.c write_sysreg(val, VTCR); val 20 arch/arm/kvm/hyp/switch.c u32 val; val 29 arch/arm/kvm/hyp/switch.c val = read_sysreg(VFP_FPEXC); val 30 arch/arm/kvm/hyp/switch.c *fpexc_host = val; val 31 arch/arm/kvm/hyp/switch.c if (!(val & FPEXC_EN)) { val 32 arch/arm/kvm/hyp/switch.c write_sysreg(val | FPEXC_EN, VFP_FPEXC); val 40 arch/arm/kvm/hyp/switch.c val = read_sysreg(HDCR); val 41 arch/arm/kvm/hyp/switch.c val |= HDCR_TPM | HDCR_TPMCR; /* trap performance monitors */ val 42 arch/arm/kvm/hyp/switch.c val |= HDCR_TDRA | HDCR_TDOSA | HDCR_TDA; /* trap debug regs */ val 43 arch/arm/kvm/hyp/switch.c write_sysreg(val, HDCR); val 48 arch/arm/kvm/hyp/switch.c u32 val; val 61 arch/arm/kvm/hyp/switch.c val = read_sysreg(HDCR); val 62 arch/arm/kvm/hyp/switch.c write_sysreg(val & ~(HDCR_TPM | HDCR_TPMCR), HDCR); val 218 arch/arm/kvm/hyp/switch.c u32 val; val 221 arch/arm/kvm/hyp/switch.c val = read_sysreg(HDFAR); val 223 arch/arm/kvm/hyp/switch.c val = read_special(SPSR); val 239 arch/arm/kvm/hyp/switch.c __hyp_do_panic(__hyp_panic_string[cause], elr, val); val 45 arch/arm/mach-artpec/board-artpec6.c static void artpec6_l2c310_write_sec(unsigned long val, unsigned reg) val 49 arch/arm/mach-artpec/board-artpec6.c arm_smccc_smc(SECURE_OP_L2C_WRITEREG, reg, val, 0, val 133 arch/arm/mach-at91/pm.c unsigned int mode = 0, polarity = 0, val = 0; val 150 arch/arm/mach-at91/pm.c val = readl(soc_pm.data.shdwc + 0x04); val 162 arch/arm/mach-at91/pm.c if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) val 187 arch/arm/mach-at91/pm.c u32 val; val 190 arch/arm/mach-at91/pm.c val = readl(shdwc + 0x0c); val 191 arch/arm/mach-at91/pm.c *mode |= (val & 0x3ff); val 192 arch/arm/mach-at91/pm.c *polarity |= ((val >> 16) & 0x3ff); val 286 arch/arm/mach-at91/pm.c static int at91_suspend_finish(unsigned long val) val 61 arch/arm/mach-bcm/bcm63xx_pmb.c unsigned int addr, u32 off, u32 *val, val 66 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr(master, addr, off, *val); val 71 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_rd(master, addr, off, val); val 76 arch/arm/mach-bcm/bcm63xx_pmb.c } while (((*val >> shift) & mask) != cond); val 129 arch/arm/mach-bcm/bcm63xx_pmb.c u32 val, ctrl; val 156 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_rd(base, addr, ARM_PWR_CONTROL(cpu), &val); val 160 arch/arm/mach-bcm/bcm63xx_pmb.c val |= (PWR_CPU_MASK << PWR_ON_SHIFT); val 162 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, val 167 arch/arm/mach-bcm/bcm63xx_pmb.c val |= (PWR_CPU_MASK << PWR_OK_SHIFT); val 169 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, val 174 arch/arm/mach-bcm/bcm63xx_pmb.c val &= ~CLAMP_ON; val 176 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); val 181 arch/arm/mach-bcm/bcm63xx_pmb.c val &= ~(MEM_PDA_MASK << MEM_PDA_SHIFT); val 183 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); val 187 arch/arm/mach-bcm/bcm63xx_pmb.c val |= MEM_PWR_ON; val 189 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, val 194 arch/arm/mach-bcm/bcm63xx_pmb.c val |= MEM_PWR_OK; val 196 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, val 201 arch/arm/mach-bcm/bcm63xx_pmb.c val &= ~MEM_CLAMP_ON; val 203 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); val 112 arch/arm/mach-bcm/bcm63xx_smp.c u32 val; val 137 arch/arm/mach-bcm/bcm63xx_smp.c val = __pa_symbol(secondary_startup); val 138 arch/arm/mach-bcm/bcm63xx_smp.c writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT); val 31 arch/arm/mach-bcm/board_bcm281xx.c uint32_t val; val 48 arch/arm/mach-bcm/board_bcm281xx.c val = readl(base + SECWDOG_OFFSET); val 49 arch/arm/mach-bcm/board_bcm281xx.c val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK; val 50 arch/arm/mach-bcm/board_bcm281xx.c val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK | val 53 arch/arm/mach-bcm/board_bcm281xx.c writel(val, base + SECWDOG_OFFSET); val 73 arch/arm/mach-bcm/platsmp-brcmstb.c static void per_cpu_sw_state_wr(u32 cpu, int val) val 76 arch/arm/mach-bcm/platsmp-brcmstb.c per_cpu(per_cpu_sw_state, cpu) = val; val 80 arch/arm/mach-bcm/platsmp-brcmstb.c static inline void per_cpu_sw_state_wr(u32 cpu, int val) { } val 96 arch/arm/mach-bcm/platsmp-brcmstb.c static void pwr_ctrl_set(unsigned int cpu, u32 val, u32 mask) val 99 arch/arm/mach-bcm/platsmp-brcmstb.c writel((readl(base) & mask) | val, base); val 102 arch/arm/mach-bcm/platsmp-brcmstb.c static void pwr_ctrl_clr(unsigned int cpu, u32 val, u32 mask) val 105 arch/arm/mach-bcm/platsmp-brcmstb.c writel((readl(base) & mask) & ~val, base); val 129 arch/arm/mach-bcm/platsmp-brcmstb.c u32 val; val 130 arch/arm/mach-bcm/platsmp-brcmstb.c val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg); val 132 arch/arm/mach-bcm/platsmp-brcmstb.c val |= BIT(cpu_logical_map(cpu)); val 134 arch/arm/mach-bcm/platsmp-brcmstb.c val &= ~BIT(cpu_logical_map(cpu)); val 135 arch/arm/mach-bcm/platsmp-brcmstb.c writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg); val 35 arch/arm/mach-berlin/platsmp.c u32 val; val 37 arch/arm/mach-berlin/platsmp.c val = readl(cpu_ctrl + CPU_RESET_NON_SC); val 38 arch/arm/mach-berlin/platsmp.c val &= ~BIT(cpu_logical_map(cpu)); val 39 arch/arm/mach-berlin/platsmp.c writel(val, cpu_ctrl + CPU_RESET_NON_SC); val 40 arch/arm/mach-berlin/platsmp.c val |= BIT(cpu_logical_map(cpu)); val 41 arch/arm/mach-berlin/platsmp.c writel(val, cpu_ctrl + CPU_RESET_NON_SC); val 109 arch/arm/mach-berlin/platsmp.c u32 val; val 111 arch/arm/mach-berlin/platsmp.c val = readl(cpu_ctrl + CPU_RESET_NON_SC); val 112 arch/arm/mach-berlin/platsmp.c val &= ~BIT(cpu_logical_map(cpu)); val 113 arch/arm/mach-berlin/platsmp.c writel(val, cpu_ctrl + CPU_RESET_NON_SC); val 181 arch/arm/mach-cns3xxx/core.c u32 val; val 184 arch/arm/mach-cns3xxx/core.c val = readl(stat); val 185 arch/arm/mach-cns3xxx/core.c writel(val & ~(1 << 2), stat); val 203 arch/arm/mach-cns3xxx/core.c u32 val; val 229 arch/arm/mach-cns3xxx/core.c val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); val 230 arch/arm/mach-cns3xxx/core.c val |= (1 << 9); val 231 arch/arm/mach-cns3xxx/core.c writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); val 243 arch/arm/mach-cns3xxx/core.c val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); val 244 arch/arm/mach-cns3xxx/core.c val |= (1 << 10); val 245 arch/arm/mach-cns3xxx/core.c writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); val 265 arch/arm/mach-cns3xxx/core.c u32 val; val 279 arch/arm/mach-cns3xxx/core.c val = readl(base + L310_TAG_LATENCY_CTRL); val 280 arch/arm/mach-cns3xxx/core.c val &= 0xfffff888; val 281 arch/arm/mach-cns3xxx/core.c writel(val, base + L310_TAG_LATENCY_CTRL); val 292 arch/arm/mach-cns3xxx/core.c val = readl(base + L310_DATA_LATENCY_CTRL); val 293 arch/arm/mach-cns3xxx/core.c val &= 0xfffff888; val 294 arch/arm/mach-cns3xxx/core.c writel(val, base + L310_DATA_LATENCY_CTRL); val 87 arch/arm/mach-cns3xxx/pcie.c int where, int size, u32 *val) val 93 arch/arm/mach-cns3xxx/pcie.c ret = pci_generic_config_read(bus, devfn, where, size, val); val 102 arch/arm/mach-cns3xxx/pcie.c *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask; val 213 arch/arm/mach-cns3xxx/pcie.c int where, int size, u32 val) val 223 arch/arm/mach-cns3xxx/pcie.c v |= (val & mask) << shift; val 1102 arch/arm/mach-davinci/board-da850-evm.c u32 val; val 1111 arch/arm/mach-davinci/board-da850-evm.c val = __raw_readl(cfg_chip3_base); val 1114 arch/arm/mach-davinci/board-da850-evm.c val |= BIT(8); val 1119 arch/arm/mach-davinci/board-da850-evm.c val &= ~BIT(8); val 1130 arch/arm/mach-davinci/board-da850-evm.c __raw_writel(val, cfg_chip3_base); val 486 arch/arm/mach-davinci/board-dm646x-evm.c int val = 0; val 499 arch/arm/mach-davinci/board-dm646x-evm.c val = i2c_smbus_read_byte(cpld_client); val 500 arch/arm/mach-davinci/board-dm646x-evm.c if (val < 0) val 501 arch/arm/mach-davinci/board-dm646x-evm.c return val; val 504 arch/arm/mach-davinci/board-dm646x-evm.c val &= ~0x40; val 506 arch/arm/mach-davinci/board-dm646x-evm.c val |= 0x40; val 508 arch/arm/mach-davinci/board-dm646x-evm.c err = i2c_smbus_write_byte(cpld_client, val); val 606 arch/arm/mach-davinci/board-dm646x-evm.c int val; val 615 arch/arm/mach-davinci/board-dm646x-evm.c val = i2c_smbus_read_byte(cpld_client); val 616 arch/arm/mach-davinci/board-dm646x-evm.c if (val < 0) val 617 arch/arm/mach-davinci/board-dm646x-evm.c return val; val 621 arch/arm/mach-davinci/board-dm646x-evm.c val &= TVP5147_INPUT; val 623 arch/arm/mach-davinci/board-dm646x-evm.c val |= TVP7002_INPUT; val 625 arch/arm/mach-davinci/board-dm646x-evm.c err = i2c_smbus_write_byte(cpld_client, val); val 641 arch/arm/mach-davinci/board-dm646x-evm.c int val; val 647 arch/arm/mach-davinci/board-dm646x-evm.c val = i2c_smbus_read_byte(cpld_client); val 648 arch/arm/mach-davinci/board-dm646x-evm.c if (val < 0) val 649 arch/arm/mach-davinci/board-dm646x-evm.c return val; val 654 arch/arm/mach-davinci/board-dm646x-evm.c val &= VPIF_INPUT_TWO_CHANNEL; val 657 arch/arm/mach-davinci/board-dm646x-evm.c val |= VPIF_INPUT_ONE_CHANNEL; val 663 arch/arm/mach-davinci/board-dm646x-evm.c err = i2c_smbus_write_byte(cpld_client, val); val 524 arch/arm/mach-davinci/board-mityomapl138.c u32 val; val 530 arch/arm/mach-davinci/board-mityomapl138.c val = __raw_readl(cfg_chip3_base); val 533 arch/arm/mach-davinci/board-mityomapl138.c val |= BIT(8); val 537 arch/arm/mach-davinci/board-mityomapl138.c val &= ~BIT(8); val 548 arch/arm/mach-davinci/board-mityomapl138.c __raw_writel(val, cfg_chip3_base); val 52 arch/arm/mach-davinci/board-omapl138-hawk.c u32 val; val 55 arch/arm/mach-davinci/board-omapl138-hawk.c val = __raw_readl(cfgchip3); val 56 arch/arm/mach-davinci/board-omapl138-hawk.c val &= ~BIT(8); val 64 arch/arm/mach-davinci/board-omapl138-hawk.c __raw_writel(val, cfgchip3); val 29 arch/arm/mach-davinci/cpuidle.c u32 val; val 31 arch/arm/mach-davinci/cpuidle.c val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); val 35 arch/arm/mach-davinci/cpuidle.c val |= DDR2_SRPD_BIT; val 37 arch/arm/mach-davinci/cpuidle.c val &= ~DDR2_SRPD_BIT; val 38 arch/arm/mach-davinci/cpuidle.c val |= DDR2_LPMODEN_BIT; val 40 arch/arm/mach-davinci/cpuidle.c val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT); val 43 arch/arm/mach-davinci/cpuidle.c __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET); val 973 arch/arm/mach-davinci/dm365.c u32 val; val 979 arch/arm/mach-davinci/dm365.c val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; val 983 arch/arm/mach-davinci/dm365.c val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; val 986 arch/arm/mach-davinci/dm365.c val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE | val 993 arch/arm/mach-davinci/dm365.c writel(val, vpss_clkctl_reg); val 46 arch/arm/mach-davinci/pm.c unsigned val; val 51 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val 52 arch/arm/mach-davinci/pm.c val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); val 53 arch/arm/mach-davinci/pm.c __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); val 58 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val 59 arch/arm/mach-davinci/pm.c val |= PLLCTL_PLLPWRDN; val 60 arch/arm/mach-davinci/pm.c __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); val 64 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.deepsleep_reg); val 65 arch/arm/mach-davinci/pm.c val &= ~DEEPSLEEP_SLEEPCOUNT_MASK, val 66 arch/arm/mach-davinci/pm.c val |= pm_config.sleepcount; val 67 arch/arm/mach-davinci/pm.c __raw_writel(val, pm_config.deepsleep_reg); val 75 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val 76 arch/arm/mach-davinci/pm.c val &= ~PLLCTL_PLLRST; val 77 arch/arm/mach-davinci/pm.c __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); val 80 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val 81 arch/arm/mach-davinci/pm.c val &= ~PLLCTL_PLLPWRDN; val 82 arch/arm/mach-davinci/pm.c __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); val 88 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val 89 arch/arm/mach-davinci/pm.c val |= PLLCTL_PLLRST; val 90 arch/arm/mach-davinci/pm.c __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); val 96 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val 97 arch/arm/mach-davinci/pm.c val &= ~PLLCTL_PLLENSRC; val 98 arch/arm/mach-davinci/pm.c val |= PLLCTL_PLLEN; val 99 arch/arm/mach-davinci/pm.c __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); val 96 arch/arm/mach-dove/pcie.c int size, u32 *val) val 104 arch/arm/mach-dove/pcie.c *val = 0xffffffff; val 109 arch/arm/mach-dove/pcie.c ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); val 116 arch/arm/mach-dove/pcie.c int where, int size, u32 val) val 127 arch/arm/mach-dove/pcie.c ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); val 14 arch/arm/mach-ebsa110/include/mach/io.h void __outb8(u8 val, unsigned int port); val 17 arch/arm/mach-ebsa110/include/mach/io.h void __outb16(u8 val, unsigned int port); val 20 arch/arm/mach-ebsa110/include/mach/io.h void __outw(u16 val, unsigned int port); val 23 arch/arm/mach-ebsa110/include/mach/io.h void __outl(u32 val, unsigned int port); val 29 arch/arm/mach-ebsa110/include/mach/io.h void __writeb(u8 val, volatile void __iomem *addr); val 30 arch/arm/mach-ebsa110/include/mach/io.h void __writew(u16 val, volatile void __iomem *addr); val 31 arch/arm/mach-ebsa110/include/mach/io.h void __writel(u32 val, volatile void __iomem *addr); val 126 arch/arm/mach-ebsa110/io.c void __writeb(u8 val, volatile void __iomem *addr) val 131 arch/arm/mach-ebsa110/io.c __raw_writel(val, a); val 133 arch/arm/mach-ebsa110/io.c __raw_writeb(val, a); val 136 arch/arm/mach-ebsa110/io.c void __writew(u16 val, volatile void __iomem *addr) val 143 arch/arm/mach-ebsa110/io.c __raw_writew(val, a); val 146 arch/arm/mach-ebsa110/io.c void __writel(u32 val, volatile void __iomem *addr) val 153 arch/arm/mach-ebsa110/io.c __raw_writew(val, a); val 154 arch/arm/mach-ebsa110/io.c __raw_writew(val >> 16, a + 4); val 288 arch/arm/mach-ebsa110/io.c void __outb8(u8 val, unsigned int port) val 294 arch/arm/mach-ebsa110/io.c __raw_writeb(val, (void __iomem *)ISAIO_BASE + (port << 2)); val 302 arch/arm/mach-ebsa110/io.c __raw_writel(val, a); val 304 arch/arm/mach-ebsa110/io.c __raw_writeb(val, a); val 308 arch/arm/mach-ebsa110/io.c void __outb16(u8 val, unsigned int port) val 320 arch/arm/mach-ebsa110/io.c __raw_writeb(val, (void __iomem *)ISAIO_BASE + offset); val 323 arch/arm/mach-ebsa110/io.c void __outw(u16 val, unsigned int port) val 336 arch/arm/mach-ebsa110/io.c __raw_writew(val, (void __iomem *)ISAIO_BASE + offset); val 339 arch/arm/mach-ebsa110/io.c void __outl(u32 val, unsigned int port) val 333 arch/arm/mach-ep93xx/clock.c u32 val; val 336 arch/arm/mach-ep93xx/clock.c val = __raw_readl(clk->enable_reg); val 348 arch/arm/mach-ep93xx/clock.c val |= div_bit; val 350 arch/arm/mach-ep93xx/clock.c val &= ~div_bit; val 354 arch/arm/mach-ep93xx/clock.c ep93xx_syscon_swlocked_write(val, clk->enable_reg); val 418 arch/arm/mach-ep93xx/clock.c u32 val; val 425 arch/arm/mach-ep93xx/clock.c val = __raw_readl(clk->enable_reg); val 426 arch/arm/mach-ep93xx/clock.c val &= ~0x7fff; val 429 arch/arm/mach-ep93xx/clock.c val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) | val 432 arch/arm/mach-ep93xx/clock.c ep93xx_syscon_swlocked_write(val, clk->enable_reg); val 438 arch/arm/mach-ep93xx/clock.c unsigned val = __raw_readl(clk->enable_reg); val 441 arch/arm/mach-ep93xx/clock.c ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, val 444 arch/arm/mach-ep93xx/clock.c ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, val 455 arch/arm/mach-ep93xx/clock.c unsigned val = __raw_readl(clk->enable_reg) & val 459 arch/arm/mach-ep93xx/clock.c ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32, val 462 arch/arm/mach-ep93xx/clock.c ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64, val 465 arch/arm/mach-ep93xx/clock.c ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128, val 93 arch/arm/mach-ep93xx/core.c void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) val 100 arch/arm/mach-ep93xx/core.c __raw_writel(val, reg); val 108 arch/arm/mach-ep93xx/core.c unsigned int val; val 112 arch/arm/mach-ep93xx/core.c val = __raw_readl(EP93XX_SYSCON_DEVCFG); val 113 arch/arm/mach-ep93xx/core.c val &= ~clear_bits; val 114 arch/arm/mach-ep93xx/core.c val |= set_bits; val 116 arch/arm/mach-ep93xx/core.c __raw_writel(val, EP93XX_SYSCON_DEVCFG); val 674 arch/arm/mach-ep93xx/core.c unsigned val; val 685 arch/arm/mach-ep93xx/core.c val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); val 686 arch/arm/mach-ep93xx/core.c val &= ~EP93XX_I2SCLKDIV_MASK; val 687 arch/arm/mach-ep93xx/core.c val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; val 688 arch/arm/mach-ep93xx/core.c ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); val 198 arch/arm/mach-ep93xx/soc.h void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg); val 155 arch/arm/mach-exynos/common.h static inline void pmu_raw_writel(u32 val, u32 offset) val 157 arch/arm/mach-exynos/common.h writel_relaxed(val, pmu_base_addr + offset); val 151 arch/arm/mach-exynos/firmware.c static void exynos_l2_write_sec(unsigned long val, unsigned reg) val 157 arch/arm/mach-exynos/firmware.c if (val & L2X0_CTRL_EN) { val 169 arch/arm/mach-exynos/firmware.c exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0); val 173 arch/arm/mach-exynos/firmware.c exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0); val 100 arch/arm/mach-exynos/platsmp.c int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); val 102 arch/arm/mach-exynos/platsmp.c if (!(val & S5P_CORE_LOCAL_PWR_EN)) val 218 arch/arm/mach-exynos/platsmp.c u32 val; val 233 arch/arm/mach-exynos/platsmp.c val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id)); val 234 arch/arm/mach-exynos/platsmp.c val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG; val 235 arch/arm/mach-exynos/platsmp.c pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id)); val 247 arch/arm/mach-exynos/platsmp.c static void exynos_write_pen_release(int val) val 249 arch/arm/mach-exynos/platsmp.c exynos_pen_release = val; val 46 arch/arm/mach-footbridge/netwinder-hw.c static inline void wb977_wb(int reg, int val) val 49 arch/arm/mach-footbridge/netwinder-hw.c outb(val, 0x371); val 52 arch/arm/mach-footbridge/netwinder-hw.c static inline void wb977_ww(int reg, int val) val 55 arch/arm/mach-footbridge/netwinder-hw.c outb(val >> 8, 0x371); val 57 arch/arm/mach-footbridge/netwinder-hw.c outb(val & 255, 0x371); val 42 arch/arm/mach-highbank/highbank.c static void highbank_l2c310_write_sec(unsigned long val, unsigned reg) val 45 arch/arm/mach-highbank/highbank.c highbank_smc1(0x102, val); val 72 arch/arm/mach-highbank/highbank.c u32 val; val 99 arch/arm/mach-highbank/highbank.c val = readl(sregs_base + reg); val 100 arch/arm/mach-highbank/highbank.c writel(val | 0xff01, sregs_base + reg); val 20 arch/arm/mach-highbank/pm.c static int highbank_suspend_finish(unsigned long val) val 78 arch/arm/mach-hisi/hotplug.c u32 val = 0; val 91 arch/arm/mach-hisi/hotplug.c val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN val 93 arch/arm/mach-hisi/hotplug.c writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); val 95 arch/arm/mach-hisi/hotplug.c val |= CPU0_HPM_SRST_REQ_EN; val 96 arch/arm/mach-hisi/hotplug.c writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); val 105 arch/arm/mach-hisi/hotplug.c val = readl_relaxed(ctrl_base + SCPERCTRL0); val 106 arch/arm/mach-hisi/hotplug.c val &= ~(CPU0_WFI_MASK_CFG << cpu); val 107 arch/arm/mach-hisi/hotplug.c writel_relaxed(val, ctrl_base + SCPERCTRL0); val 110 arch/arm/mach-hisi/hotplug.c val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN val 112 arch/arm/mach-hisi/hotplug.c writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); val 115 arch/arm/mach-hisi/hotplug.c val = readl_relaxed(ctrl_base + SCPERCTRL0); val 116 arch/arm/mach-hisi/hotplug.c val |= (CPU0_WFI_MASK_CFG << cpu); val 117 arch/arm/mach-hisi/hotplug.c writel_relaxed(val, ctrl_base + SCPERCTRL0); val 130 arch/arm/mach-hisi/hotplug.c val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN val 132 arch/arm/mach-hisi/hotplug.c writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); val 193 arch/arm/mach-hisi/hotplug.c u32 val = 0; val 201 arch/arm/mach-hisi/hotplug.c val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); val 202 arch/arm/mach-hisi/hotplug.c val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN); val 203 arch/arm/mach-hisi/hotplug.c val |= PMC0_CPU1_PMC_ENABLE; val 204 arch/arm/mach-hisi/hotplug.c writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0); val 206 arch/arm/mach-hisi/hotplug.c val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); val 207 arch/arm/mach-hisi/hotplug.c val &= ~CRG20_CPU1_RESET; val 208 arch/arm/mach-hisi/hotplug.c writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); val 211 arch/arm/mach-hisi/hotplug.c val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); val 212 arch/arm/mach-hisi/hotplug.c val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN; val 213 arch/arm/mach-hisi/hotplug.c val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK; val 214 arch/arm/mach-hisi/hotplug.c writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0); val 217 arch/arm/mach-hisi/hotplug.c val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); val 218 arch/arm/mach-hisi/hotplug.c val |= CRG20_CPU1_RESET; val 219 arch/arm/mach-hisi/hotplug.c writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); val 43 arch/arm/mach-imx/anatop.c u32 reg, val; val 45 arch/arm/mach-imx/anatop.c regmap_read(anatop, ANADIG_ANA_MISC0, &val); val 49 arch/arm/mach-imx/anatop.c reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? val 23 arch/arm/mach-imx/cpu-imx27.c u32 val; val 29 arch/arm/mach-imx/cpu-imx27.c val = imx_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID)); val 31 arch/arm/mach-imx/cpu-imx27.c mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); val 33 arch/arm/mach-imx/cpu-imx27.c switch (val >> 28) { val 17 arch/arm/mach-imx/cpuidle-imx6sx.c static int imx6sx_idle_finish(unsigned long val) val 53 arch/arm/mach-imx/gpc.c u32 val; val 55 arch/arm/mach-imx/gpc.c val = readl_relaxed(gpc_base + GPC_CNTR); val 56 arch/arm/mach-imx/gpc.c val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT); val 58 arch/arm/mach-imx/gpc.c val |= 1 << GPC_CNTR_L2_PGE_SHIFT; val 59 arch/arm/mach-imx/gpc.c writel_relaxed(val, gpc_base + GPC_CNTR); val 129 arch/arm/mach-imx/gpc.c u32 val; val 132 arch/arm/mach-imx/gpc.c val = readl_relaxed(reg); val 133 arch/arm/mach-imx/gpc.c val &= ~(1 << hwirq % 32); val 134 arch/arm/mach-imx/gpc.c writel_relaxed(val, reg); val 140 arch/arm/mach-imx/gpc.c u32 val; val 143 arch/arm/mach-imx/gpc.c val = readl_relaxed(reg); val 144 arch/arm/mach-imx/gpc.c val |= 1 << (hwirq % 32); val 145 arch/arm/mach-imx/gpc.c writel_relaxed(val, reg); val 31 arch/arm/mach-imx/iomux-v1.c static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset) val 33 arch/arm/mach-imx/iomux-v1.c imx_writel(val, imx_iomuxv1_baseaddr + offset); val 56 arch/arm/mach-imx/mach-imx6q.c static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) val 61 arch/arm/mach-imx/mach-imx6q.c phy_write(dev, 0x0e, val); val 107 arch/arm/mach-imx/mach-imx6q.c u16 val; val 114 arch/arm/mach-imx/mach-imx6q.c val = phy_read(dev, 0xe); val 115 arch/arm/mach-imx/mach-imx6q.c val &= 0xffe3; val 116 arch/arm/mach-imx/mach-imx6q.c val |= 0x18; val 117 arch/arm/mach-imx/mach-imx6q.c phy_write(dev, 0xe, val); val 121 arch/arm/mach-imx/mach-imx6q.c val = phy_read(dev, 0x1e); val 122 arch/arm/mach-imx/mach-imx6q.c val |= 0x0100; val 123 arch/arm/mach-imx/mach-imx6q.c phy_write(dev, 0x1e, val); val 132 arch/arm/mach-imx/mach-imx6q.c u16 val; val 141 arch/arm/mach-imx/mach-imx6q.c val = phy_read(dev, 0xe); val 142 arch/arm/mach-imx/mach-imx6q.c phy_write(dev, 0xe, val & ~(1 << 8)); val 154 arch/arm/mach-imx/mach-imx6q.c val = phy_read(dev, 0x0); val 155 arch/arm/mach-imx/mach-imx6q.c if (val & BMCR_PDOWN) val 156 arch/arm/mach-imx/mach-imx6q.c phy_write(dev, 0x0, val & ~BMCR_PDOWN); val 20 arch/arm/mach-imx/mach-imx6sx.c u16 val; val 28 arch/arm/mach-imx/mach-imx6sx.c val = phy_read(dev, 0x1e); val 29 arch/arm/mach-imx/mach-imx6sx.c val |= 0x0100; val 30 arch/arm/mach-imx/mach-imx6sx.c phy_write(dev, 0x1e, val); val 19 arch/arm/mach-imx/mach-imx7d.c u16 val; val 29 arch/arm/mach-imx/mach-imx7d.c val = phy_read(dev, 0xe); val 30 arch/arm/mach-imx/mach-imx7d.c val &= ~(0x1 << 8); val 31 arch/arm/mach-imx/mach-imx7d.c phy_write(dev, 0xe, val); val 327 arch/arm/mach-imx/mmdc.c u32 val; val 346 arch/arm/mach-imx/mmdc.c val = event->attr.config1; val 348 arch/arm/mach-imx/mmdc.c writel(val, reg); val 351 arch/arm/mach-imx/mmdc.c val = DBG_EN; val 353 arch/arm/mach-imx/mmdc.c val |= PROFILE_SEL; val 355 arch/arm/mach-imx/mmdc.c writel(val, reg); val 540 arch/arm/mach-imx/mmdc.c u32 val; val 559 arch/arm/mach-imx/mmdc.c val = readl_relaxed(reg); val 560 arch/arm/mach-imx/mmdc.c ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >> val 566 arch/arm/mach-imx/mmdc.c val = readl_relaxed(reg); val 567 arch/arm/mach-imx/mmdc.c val &= ~(1 << BP_MMDC_MAPSR_PSD); val 568 arch/arm/mach-imx/mmdc.c writel_relaxed(val, reg); val 233 arch/arm/mach-imx/pm-imx6.c u32 val = readl_relaxed(ccm_base + CGPR); val 235 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CGPR_INT_MEM_CLK_LPM; val 237 arch/arm/mach-imx/pm-imx6.c val |= BM_CGPR_INT_MEM_CLK_LPM; val 238 arch/arm/mach-imx/pm-imx6.c writel_relaxed(val, ccm_base + CGPR); val 243 arch/arm/mach-imx/pm-imx6.c u32 val; val 252 arch/arm/mach-imx/pm-imx6.c val = readl_relaxed(ccm_base + CCR); val 253 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CCR_RBC_EN; val 254 arch/arm/mach-imx/pm-imx6.c val |= enable ? BM_CCR_RBC_EN : 0; val 255 arch/arm/mach-imx/pm-imx6.c writel_relaxed(val, ccm_base + CCR); val 258 arch/arm/mach-imx/pm-imx6.c val = readl_relaxed(ccm_base + CCR); val 259 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CCR_RBC_BYPASS_COUNT; val 260 arch/arm/mach-imx/pm-imx6.c val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; val 261 arch/arm/mach-imx/pm-imx6.c writel(val, ccm_base + CCR); val 276 arch/arm/mach-imx/pm-imx6.c u32 val; val 279 arch/arm/mach-imx/pm-imx6.c val = readl_relaxed(ccm_base + CLPCR); val 280 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CLPCR_WB_PER_AT_LPM; val 281 arch/arm/mach-imx/pm-imx6.c val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; val 282 arch/arm/mach-imx/pm-imx6.c writel_relaxed(val, ccm_base + CLPCR); val 285 arch/arm/mach-imx/pm-imx6.c val = readl_relaxed(ccm_base + CCR); val 286 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CCR_WB_COUNT; val 287 arch/arm/mach-imx/pm-imx6.c val |= enable ? BM_CCR_WB_COUNT : 0; val 288 arch/arm/mach-imx/pm-imx6.c writel_relaxed(val, ccm_base + CCR); val 293 arch/arm/mach-imx/pm-imx6.c u32 val = readl_relaxed(ccm_base + CLPCR); val 295 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CLPCR_LPM; val 300 arch/arm/mach-imx/pm-imx6.c val |= 0x1 << BP_CLPCR_LPM; val 301 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; val 304 arch/arm/mach-imx/pm-imx6.c val |= 0x2 << BP_CLPCR_LPM; val 305 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CLPCR_VSTBY; val 306 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CLPCR_SBYOS; val 308 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_BYPASS_PMIC_READY; val 311 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; val 313 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; val 316 arch/arm/mach-imx/pm-imx6.c val |= 0x1 << BP_CLPCR_LPM; val 317 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CLPCR_VSTBY; val 318 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CLPCR_SBYOS; val 321 arch/arm/mach-imx/pm-imx6.c val |= 0x2 << BP_CLPCR_LPM; val 322 arch/arm/mach-imx/pm-imx6.c val |= 0x3 << BP_CLPCR_STBY_COUNT; val 323 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_VSTBY; val 324 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_SBYOS; val 326 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_BYPASS_PMIC_READY; val 329 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; val 331 arch/arm/mach-imx/pm-imx6.c val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; val 353 arch/arm/mach-imx/pm-imx6.c writel_relaxed(val, ccm_base + CLPCR); val 360 arch/arm/mach-imx/pm-imx6.c static int imx6q_suspend_finish(unsigned long val) val 642 arch/arm/mach-imx/pm-imx6.c u32 val; val 652 arch/arm/mach-imx/pm-imx6.c val = readl_relaxed(ccm_base + CLPCR); val 653 arch/arm/mach-imx/pm-imx6.c val &= ~BM_CLPCR_LPM; val 654 arch/arm/mach-imx/pm-imx6.c writel_relaxed(val, ccm_base + CLPCR); val 32 arch/arm/mach-imx/pm-imx7ulp.c u32 val = readl_relaxed(smc1_base + SMC_PMCTRL); val 35 arch/arm/mach-imx/pm-imx7ulp.c val &= ~(BM_PMCTRL_RUNM | BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO); val 40 arch/arm/mach-imx/pm-imx7ulp.c val |= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO; val 44 arch/arm/mach-imx/pm-imx7ulp.c val |= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO; val 48 arch/arm/mach-imx/pm-imx7ulp.c val |= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO; val 54 arch/arm/mach-imx/pm-imx7ulp.c writel_relaxed(val, smc1_base + SMC_PMCTRL); val 44 arch/arm/mach-imx/src.c u32 val; val 55 arch/arm/mach-imx/src.c val = readl_relaxed(src_base + SRC_SCR); val 56 arch/arm/mach-imx/src.c val |= bit; val 57 arch/arm/mach-imx/src.c writel_relaxed(val, src_base + SRC_SCR); val 81 arch/arm/mach-imx/src.c u32 mask, val; val 86 arch/arm/mach-imx/src.c val = readl_relaxed(src_base + SRC_SCR); val 87 arch/arm/mach-imx/src.c val = enable ? val | mask : val & ~mask; val 88 arch/arm/mach-imx/src.c val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); val 89 arch/arm/mach-imx/src.c writel_relaxed(val, src_base + SRC_SCR); val 115 arch/arm/mach-imx/src.c u32 val; val 132 arch/arm/mach-imx/src.c val = readl_relaxed(src_base + SRC_SCR); val 133 arch/arm/mach-imx/src.c val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); val 134 arch/arm/mach-imx/src.c writel_relaxed(val, src_base + SRC_SCR); val 90 arch/arm/mach-imx/system.c unsigned int val; val 102 arch/arm/mach-imx/system.c val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val 103 arch/arm/mach-imx/system.c val |= L310_PREFETCH_CTRL_DBL_LINEFILL | val 108 arch/arm/mach-imx/system.c val &= ~L310_PREFETCH_CTRL_OFFSET_MASK; val 109 arch/arm/mach-imx/system.c val |= 15; val 111 arch/arm/mach-imx/system.c writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); val 52 arch/arm/mach-integrator/core.c u32 val; val 55 arch/arm/mach-integrator/core.c val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; val 56 arch/arm/mach-integrator/core.c writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); val 41 arch/arm/mach-integrator/impd1.c void impd1_tweak_control(struct device *dev, u32 mask, u32 val) val 46 arch/arm/mach-integrator/impd1.c val &= mask; val 48 arch/arm/mach-integrator/impd1.c writel(cur | val, impd1->base + IMPD1_CTRL); val 15 arch/arm/mach-integrator/impd1.h void impd1_tweak_control(struct device *dev, u32 mask, u32 val); val 84 arch/arm/mach-integrator/integrator_cp.c unsigned int val; val 87 arch/arm/mach-integrator/integrator_cp.c regmap_read(cm_map, CM_COUNTER_OFFSET, &val); val 88 arch/arm/mach-integrator/integrator_cp.c return val; val 234 arch/arm/mach-iop32x/iop3xx.h u32 val; val 235 arch/arm/mach-iop32x/iop3xx.h asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val)); val 236 arch/arm/mach-iop32x/iop3xx.h return val; val 239 arch/arm/mach-iop32x/iop3xx.h static inline void write_tmr0(u32 val) val 241 arch/arm/mach-iop32x/iop3xx.h asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); val 244 arch/arm/mach-iop32x/iop3xx.h static inline void write_tmr1(u32 val) val 246 arch/arm/mach-iop32x/iop3xx.h asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val)); val 251 arch/arm/mach-iop32x/iop3xx.h u32 val; val 252 arch/arm/mach-iop32x/iop3xx.h asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val)); val 253 arch/arm/mach-iop32x/iop3xx.h return val; val 256 arch/arm/mach-iop32x/iop3xx.h static inline void write_tcr0(u32 val) val 258 arch/arm/mach-iop32x/iop3xx.h asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val)); val 263 arch/arm/mach-iop32x/iop3xx.h u32 val; val 264 arch/arm/mach-iop32x/iop3xx.h asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val)); val 265 arch/arm/mach-iop32x/iop3xx.h return val; val 268 arch/arm/mach-iop32x/iop3xx.h static inline void write_tcr1(u32 val) val 270 arch/arm/mach-iop32x/iop3xx.h asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val)); val 273 arch/arm/mach-iop32x/iop3xx.h static inline void write_trr0(u32 val) val 275 arch/arm/mach-iop32x/iop3xx.h asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); val 278 arch/arm/mach-iop32x/iop3xx.h static inline void write_trr1(u32 val) val 280 arch/arm/mach-iop32x/iop3xx.h asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val)); val 283 arch/arm/mach-iop32x/iop3xx.h static inline void write_tisr(u32 val) val 285 arch/arm/mach-iop32x/iop3xx.h asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); val 290 arch/arm/mach-iop32x/iop3xx.h u32 val; val 291 arch/arm/mach-iop32x/iop3xx.h asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val)); val 292 arch/arm/mach-iop32x/iop3xx.h return val; val 294 arch/arm/mach-iop32x/iop3xx.h static inline void write_wdtcr(u32 val) val 296 arch/arm/mach-iop32x/iop3xx.h asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val)); val 309 arch/arm/mach-iop32x/iop3xx.h static inline void write_wdtsr(u32 val) val 22 arch/arm/mach-iop32x/irq.c static void intctl_write(u32 val) val 24 arch/arm/mach-iop32x/irq.c asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); val 27 arch/arm/mach-iop32x/irq.c static void intstr_write(u32 val) val 29 arch/arm/mach-iop32x/irq.c asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); val 90 arch/arm/mach-iop32x/pci.c u32 val; val 99 arch/arm/mach-iop32x/pci.c : "=r" (val) val 102 arch/arm/mach-iop32x/pci.c return val; val 114 arch/arm/mach-iop32x/pci.c u32 val = iop3xx_read(addr) >> ((where & 3) * 8); val 117 arch/arm/mach-iop32x/pci.c val = 0xffffffff; val 119 arch/arm/mach-iop32x/pci.c *value = val; val 129 arch/arm/mach-iop32x/pci.c u32 val; val 132 arch/arm/mach-iop32x/pci.c val = iop3xx_read(addr); val 139 arch/arm/mach-iop32x/pci.c val &= ~(0xff << where); val 141 arch/arm/mach-iop32x/pci.c val &= ~(0xffff << where); val 143 arch/arm/mach-iop32x/pci.c *IOP3XX_OCCDR = val | value << where; val 37 arch/arm/mach-ixp4xx/include/mach/cpu.h u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); val 43 arch/arm/mach-ixp4xx/include/mach/cpu.h return val & IXP42X_FEATURE_MASK; val 45 arch/arm/mach-ixp4xx/include/mach/cpu.h return val & IXP43X_FEATURE_MASK; val 46 arch/arm/mach-ixp4xx/include/mach/cpu.h return val & IXP46X_FEATURE_MASK; val 47 arch/arm/mach-meson/platsmp.c u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG); val 50 arch/arm/mach-meson/platsmp.c val |= BIT(cpu); val 52 arch/arm/mach-meson/platsmp.c val &= ~BIT(cpu); val 55 arch/arm/mach-meson/platsmp.c val |= BIT(0); val 57 arch/arm/mach-meson/platsmp.c writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG); val 214 arch/arm/mach-meson/platsmp.c u32 val; val 259 arch/arm/mach-meson/platsmp.c ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val, val 260 arch/arm/mach-meson/platsmp.c val & MESON_CPU_PWR_A9_CNTL1_ST(cpu), val 61 arch/arm/mach-mmp/pm-mmp2.c unsigned int val; val 68 arch/arm/mach-mmp/pm-mmp2.c val = __raw_readl(CIU_REG(0x1c)); val 69 arch/arm/mach-mmp/pm-mmp2.c val |= 0xf0; val 70 arch/arm/mach-mmp/pm-mmp2.c __raw_writel(val, CIU_REG(0x1c)); val 77 arch/arm/mach-mmp/pm-mmp2.c unsigned int val; val 84 arch/arm/mach-mmp/pm-mmp2.c val = __raw_readl(CIU_REG(0x1c)); val 85 arch/arm/mach-mmp/pm-mmp2.c val &= ~(0xf0); val 86 arch/arm/mach-mmp/pm-mmp2.c __raw_writel(val, CIU_REG(0x1c)); val 102 arch/arm/mach-mmp/pm-mmp2.c unsigned int val; val 105 arch/arm/mach-mmp/pm-mmp2.c val = __raw_readl(MPMU_PLL2_CTRL1); val 106 arch/arm/mach-mmp/pm-mmp2.c val |= (1 << 29); val 107 arch/arm/mach-mmp/pm-mmp2.c __raw_writel(val, MPMU_PLL2_CTRL1); val 84 arch/arm/mach-mmp/pxa168.c uint32_t val; val 88 arch/arm/mach-mmp/pxa168.c val = __raw_readl(APMU_WAKE_CLR); val 89 arch/arm/mach-mmp/pxa168.c __raw_writel(val | mask, APMU_WAKE_CLR); val 138 arch/arm/mach-mv78xx0/pcie.c int size, u32 *val) val 146 arch/arm/mach-mv78xx0/pcie.c *val = 0xffffffff; val 151 arch/arm/mach-mv78xx0/pcie.c ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); val 158 arch/arm/mach-mv78xx0/pcie.c int where, int size, u32 val) val 169 arch/arm/mach-mv78xx0/pcie.c ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); val 164 arch/arm/mach-mxs/mach-mxs.c u32 val; val 221 arch/arm/mach-mxs/mach-mxs.c val = ocotp[i]; val 222 arch/arm/mach-mxs/mach-mxs.c macaddr[3] = (val >> 16) & 0xff; val 223 arch/arm/mach-mxs/mach-mxs.c macaddr[4] = (val >> 8) & 0xff; val 224 arch/arm/mach-mxs/mach-mxs.c macaddr[5] = (val >> 0) & 0xff; val 89 arch/arm/mach-omap1/ams-delta-fiq.c unsigned long val, offset; val 158 arch/arm/mach-omap1/ams-delta-fiq.c val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); val 159 arch/arm/mach-omap1/ams-delta-fiq.c omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); val 198 arch/arm/mach-omap1/ams-delta-fiq.c val = omap_readl(OMAP_IH1_BASE + offset) | 1; val 199 arch/arm/mach-omap1/ams-delta-fiq.c omap_writel(val, OMAP_IH1_BASE + offset); val 40 arch/arm/mach-omap1/board-fsample.c #define fsample_cpld_write(val, reg) __raw_writeb(val, reg) val 43 arch/arm/mach-omap1/clock.c unsigned int val = __raw_readl(clk->enable_reg); val 44 arch/arm/mach-omap1/clock.c return val & clk->enable_bit ? 48000000 : 12000000; val 329 arch/arm/mach-omap1/clock.c unsigned int val; val 331 arch/arm/mach-omap1/clock.c val = __raw_readl(clk->enable_reg); val 333 arch/arm/mach-omap1/clock.c val &= ~(1 << clk->enable_bit); val 335 arch/arm/mach-omap1/clock.c val |= (1 << clk->enable_bit); val 338 arch/arm/mach-omap1/clock.c __raw_writel(val, clk->enable_reg); val 175 arch/arm/mach-omap1/dma.c static inline void dma_write(u32 val, int reg, int lch) val 182 arch/arm/mach-omap1/dma.c __raw_writew(val, addr); val 184 arch/arm/mach-omap1/dma.c __raw_writew(val >> 16, addr + 2); val 190 arch/arm/mach-omap1/dma.c uint32_t val; val 195 arch/arm/mach-omap1/dma.c val = __raw_readw(addr); val 197 arch/arm/mach-omap1/dma.c val |= __raw_readw(addr + 2) << 16; val 199 arch/arm/mach-omap1/dma.c return val; val 105 arch/arm/mach-omap1/irq.c unsigned long val, offset; val 110 arch/arm/mach-omap1/irq.c val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); val 112 arch/arm/mach-omap1/irq.c irq_bank_writel(val, bank, offset); val 48 arch/arm/mach-omap1/ocpi.c unsigned int val; val 54 arch/arm/mach-omap1/ocpi.c val = omap_readl(OCPI_PROT); val 55 arch/arm/mach-omap1/ocpi.c val &= ~0xff; val 57 arch/arm/mach-omap1/ocpi.c omap_writel(val, OCPI_PROT); val 59 arch/arm/mach-omap1/ocpi.c val = omap_readl(OCPI_SEC); val 60 arch/arm/mach-omap1/ocpi.c val &= ~0xff; val 61 arch/arm/mach-omap1/ocpi.c omap_writel(val, OCPI_SEC); val 89 arch/arm/mach-omap1/timer32k.c static inline void omap_32k_timer_write(int val, int reg) val 91 arch/arm/mach-omap1/timer32k.c omap_writew(val, OMAP1_32K_TIMER_BASE + reg); val 547 arch/arm/mach-omap1/usb.c unsigned int val; val 554 arch/arm/mach-omap1/usb.c val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1); val 555 arch/arm/mach-omap1/usb.c val |= (config->hmc_mode << 1); val 556 arch/arm/mach-omap1/usb.c omap_writel(val, MOD_CONF_CTRL_0); val 517 arch/arm/mach-omap2/board-n8x0.c u32 val; val 520 arch/arm/mach-omap2/board-n8x0.c val = EN_VPLL_SLEEP | EN_VMMC_SLEEP \ val 525 arch/arm/mach-omap2/board-n8x0.c ret = menelaus_set_regulator_sleep(1, val); val 55 arch/arm/mach-omap2/cm2xxx_3xxx.h static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) val 57 arch/arm/mach-omap2/cm2xxx_3xxx.h writel_relaxed(val, cm_base.va + module + idx); val 57 arch/arm/mach-omap2/cm33xx.c static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) val 59 arch/arm/mach-omap2/cm33xx.c writel_relaxed(val, cm_base.va + inst + idx); val 122 arch/arm/mach-omap2/cminst44xx.c static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) val 127 arch/arm/mach-omap2/cminst44xx.c writel_relaxed(val, _cm_bases[part].va + inst + idx); val 104 arch/arm/mach-omap2/common.h void omap4_l2c310_write_sec(unsigned long val, unsigned reg); val 146 arch/arm/mach-omap2/control.c u32 val; val 149 arch/arm/mach-omap2/control.c val = omap_ctrl_readl(offset); val 151 arch/arm/mach-omap2/control.c return (val >> (byte_offset * 8)) & 0xff; val 156 arch/arm/mach-omap2/control.c u32 val; val 159 arch/arm/mach-omap2/control.c val = omap_ctrl_readl(offset); val 161 arch/arm/mach-omap2/control.c return (val >> (byte_offset * 8)) & 0xffff; val 171 arch/arm/mach-omap2/control.c void omap_ctrl_writeb(u8 val, u16 offset) val 179 arch/arm/mach-omap2/control.c tmp |= val << (byte_offset * 8); val 184 arch/arm/mach-omap2/control.c void omap_ctrl_writew(u16 val, u16 offset) val 192 arch/arm/mach-omap2/control.c tmp |= val << (byte_offset * 8); val 197 arch/arm/mach-omap2/control.c void omap_ctrl_writel(u32 val, u16 offset) val 200 arch/arm/mach-omap2/control.c writel_relaxed(val, omap2_ctrl_base + offset); val 510 arch/arm/mach-omap2/control.h extern void omap_ctrl_writeb(u8 val, u16 offset); val 511 arch/arm/mach-omap2/control.h extern void omap_ctrl_writew(u16 val, u16 offset); val 512 arch/arm/mach-omap2/control.h extern void omap_ctrl_writel(u32 val, u16 offset); val 85 arch/arm/mach-omap2/dma.c static inline void dma_write(u32 val, int reg, int lch) val 92 arch/arm/mach-omap2/dma.c writel_relaxed(val, addr); val 52 arch/arm/mach-omap2/id.c static u32 val = OMAP2_DEVICETYPE_MASK; val 54 arch/arm/mach-omap2/id.c if (val < OMAP2_DEVICETYPE_MASK) val 55 arch/arm/mach-omap2/id.c return val; val 58 arch/arm/mach-omap2/id.c val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); val 60 arch/arm/mach-omap2/id.c val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); val 62 arch/arm/mach-omap2/id.c val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); val 64 arch/arm/mach-omap2/id.c val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); val 66 arch/arm/mach-omap2/id.c val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); val 68 arch/arm/mach-omap2/id.c val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); val 69 arch/arm/mach-omap2/id.c val &= OMAP5_DEVICETYPE_MASK; val 70 arch/arm/mach-omap2/id.c val >>= 6; val 77 arch/arm/mach-omap2/id.c val &= OMAP2_DEVICETYPE_MASK; val 78 arch/arm/mach-omap2/id.c val >>= 8; val 81 arch/arm/mach-omap2/id.c return val; val 81 arch/arm/mach-omap2/omap-wakeupgen.c static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu) val 83 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + val 87 arch/arm/mach-omap2/omap-wakeupgen.c static inline void sar_writel(u32 val, u32 offset, u8 idx) val 89 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + offset + (idx * 4)); val 106 arch/arm/mach-omap2/omap-wakeupgen.c u32 val, bit_number; val 112 arch/arm/mach-omap2/omap-wakeupgen.c val = wakeupgen_readl(i, cpu); val 113 arch/arm/mach-omap2/omap-wakeupgen.c val &= ~BIT(bit_number); val 114 arch/arm/mach-omap2/omap-wakeupgen.c wakeupgen_writel(val, i, cpu); val 119 arch/arm/mach-omap2/omap-wakeupgen.c u32 val, bit_number; val 125 arch/arm/mach-omap2/omap-wakeupgen.c val = wakeupgen_readl(i, cpu); val 126 arch/arm/mach-omap2/omap-wakeupgen.c val |= BIT(bit_number); val 127 arch/arm/mach-omap2/omap-wakeupgen.c wakeupgen_writel(val, i, cpu); val 240 arch/arm/mach-omap2/omap-wakeupgen.c u32 i, val; val 247 arch/arm/mach-omap2/omap-wakeupgen.c val = wakeupgen_readl(i, 0); val 248 arch/arm/mach-omap2/omap-wakeupgen.c sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i); val 249 arch/arm/mach-omap2/omap-wakeupgen.c val = wakeupgen_readl(i, 1); val 250 arch/arm/mach-omap2/omap-wakeupgen.c sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i); val 264 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); val 265 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET); val 266 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); val 267 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET); val 270 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); val 271 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET); val 272 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN); val 273 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET); val 276 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET); val 277 arch/arm/mach-omap2/omap-wakeupgen.c val |= SAR_BACKUP_STATUS_WAKEUPGEN; val 278 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET); val 284 arch/arm/mach-omap2/omap-wakeupgen.c u32 i, val; val 288 arch/arm/mach-omap2/omap-wakeupgen.c val = wakeupgen_readl(i, 0); val 289 arch/arm/mach-omap2/omap-wakeupgen.c sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i); val 290 arch/arm/mach-omap2/omap-wakeupgen.c val = wakeupgen_readl(i, 1); val 291 arch/arm/mach-omap2/omap-wakeupgen.c sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i); val 297 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); val 298 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); val 299 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); val 300 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); val 303 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); val 304 arch/arm/mach-omap2/omap-wakeupgen.c val |= SAR_BACKUP_STATUS_WAKEUPGEN; val 305 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); val 342 arch/arm/mach-omap2/omap-wakeupgen.c u32 val; val 351 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(sar_base + offset); val 352 arch/arm/mach-omap2/omap-wakeupgen.c val &= ~SAR_BACKUP_STATUS_WAKEUPGEN; val 353 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + offset); val 551 arch/arm/mach-omap2/omap-wakeupgen.c u32 val; val 622 arch/arm/mach-omap2/omap-wakeupgen.c val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE); val 623 arch/arm/mach-omap2/omap-wakeupgen.c val |= BIT(5); val 624 arch/arm/mach-omap2/omap-wakeupgen.c omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val); val 219 arch/arm/mach-omap2/omap4-common.c void omap4_l2c310_write_sec(unsigned long val, unsigned reg) val 249 arch/arm/mach-omap2/omap4-common.c omap_smc1(smc_op, val); val 152 arch/arm/mach-omap2/pm-debug.c static int pwrdm_suspend_get(void *data, u64 *val) val 158 arch/arm/mach-omap2/pm-debug.c *val = ret; val 162 arch/arm/mach-omap2/pm-debug.c return *val; val 165 arch/arm/mach-omap2/pm-debug.c static int pwrdm_suspend_set(void *data, u64 val) val 169 arch/arm/mach-omap2/pm-debug.c (struct powerdomain *)data, (int)val); val 199 arch/arm/mach-omap2/pm-debug.c static int option_get(void *data, u64 *val) val 203 arch/arm/mach-omap2/pm-debug.c *val = *option; val 208 arch/arm/mach-omap2/pm-debug.c static int option_set(void *data, u64 val) val 212 arch/arm/mach-omap2/pm-debug.c *option = val; val 216 arch/arm/mach-omap2/pm-debug.c omap3_pm_off_mode_enable(val); val 165 arch/arm/mach-omap2/pm34xx.c u32 val; val 168 arch/arm/mach-omap2/pm34xx.c asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); val 170 arch/arm/mach-omap2/pm34xx.c *save++ = val; val 173 arch/arm/mach-omap2/pm34xx.c asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); val 175 arch/arm/mach-omap2/pm34xx.c *save++ = val; val 33 arch/arm/mach-omap2/prcm_mpu44xx.c void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg) val 35 arch/arm/mach-omap2/prcm_mpu44xx.c writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); val 28 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); val 58 arch/arm/mach-omap2/prm2xxx_3xxx.h static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) val 60 arch/arm/mach-omap2/prm2xxx_3xxx.h writel_relaxed(val, prm_base.va + module + idx); val 37 arch/arm/mach-omap2/prm33xx.c static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) val 39 arch/arm/mach-omap2/prm33xx.c writel_relaxed(val, prm_base.va + inst + idx); val 120 arch/arm/mach-omap2/prm3xxx.c void omap3_prm_vcvp_write(u32 val, u8 offset) val 122 arch/arm/mach-omap2/prm3xxx.c omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); val 137 arch/arm/mach-omap2/prm3xxx.h extern void omap3_prm_vcvp_write(u32 val, u8 offset); val 102 arch/arm/mach-omap2/prm44xx.c static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) val 104 arch/arm/mach-omap2/prm44xx.c writel_relaxed(val, prm_base.va + inst + reg); val 179 arch/arm/mach-omap2/prm44xx.c void omap4_prm_vcvp_write(u32 val, u8 offset) val 186 arch/arm/mach-omap2/prm44xx.c omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, val 32 arch/arm/mach-omap2/prm44xx_54xx.h extern void omap4_prm_vcvp_write(u32 val, u8 offset); val 67 arch/arm/mach-omap2/prminst44xx.c void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) val 72 arch/arm/mach-omap2/prminst44xx.c writel_relaxed(val, _prm_bases[part].va + inst + idx); val 21 arch/arm/mach-omap2/prminst44xx.h extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); val 29 arch/arm/mach-omap2/sdrc.h static inline void sdrc_write_reg(u32 val, u16 reg) val 31 arch/arm/mach-omap2/sdrc.h writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); val 41 arch/arm/mach-omap2/sdrc.h static inline void sms_write_reg(u32 val, u16 reg) val 43 arch/arm/mach-omap2/sdrc.h writel_relaxed(val, OMAP_SMS_REGADDR(reg)); val 290 arch/arm/mach-omap2/vc.c u32 val; val 297 arch/arm/mach-omap2/vc.c val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET); val 298 arch/arm/mach-omap2/vc.c if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) || val 299 arch/arm/mach-omap2/vc.c (val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) { val 300 arch/arm/mach-omap2/vc.c val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL; val 301 arch/arm/mach-omap2/vc.c val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL; val 303 arch/arm/mach-omap2/vc.c val); val 304 arch/arm/mach-omap2/vc.c voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET); val 318 arch/arm/mach-omap2/vc.c val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); val 319 arch/arm/mach-omap2/vc.c if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { val 320 arch/arm/mach-omap2/vc.c val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF; val 322 arch/arm/mach-omap2/vc.c val); val 323 arch/arm/mach-omap2/vc.c voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET); val 325 arch/arm/mach-omap2/vc.c vc.voltctrl = val; val 333 arch/arm/mach-omap2/vc.c unsigned long val; val 335 arch/arm/mach-omap2/vc.c val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate; val 336 arch/arm/mach-omap2/vc.c val *= voltdm->sys_clk.rate / 8 / 1000000 + 1; val 337 arch/arm/mach-omap2/vc.c val <<= __ffs(voltdm->vfsm->voltsetup_mask); val 339 arch/arm/mach-omap2/vc.c c->voltsetup1 |= val; val 489 arch/arm/mach-omap2/vc.c u32 val; val 491 arch/arm/mach-omap2/vc.c val = omap_usec_to_32k(usec) << shift; val 494 arch/arm/mach-omap2/vc.c if (val > mask) val 495 arch/arm/mach-omap2/vc.c val = mask; val 497 arch/arm/mach-omap2/vc.c return val; val 509 arch/arm/mach-omap2/vc.c u32 val; val 527 arch/arm/mach-omap2/vc.c val = voltdm->read(offset); val 529 arch/arm/mach-omap2/vc.c val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT; val 531 arch/arm/mach-omap2/vc.c val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT; val 533 arch/arm/mach-omap2/vc.c voltdm->write(val, offset); val 537 arch/arm/mach-omap2/vc.c val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT, val 539 arch/arm/mach-omap2/vc.c val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT, val 542 arch/arm/mach-omap2/vc.c writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME); val 613 arch/arm/mach-omap2/vc.c u32 val; val 661 arch/arm/mach-omap2/vc.c val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29; val 664 arch/arm/mach-omap2/vc.c writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + val 668 arch/arm/mach-omap2/vc.c val = hsscll << OMAP4430_HSSCLL_SHIFT; val 669 arch/arm/mach-omap2/vc.c val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT); val 672 arch/arm/mach-omap2/vc.c voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); val 772 arch/arm/mach-omap2/vc.c u32 val; val 826 arch/arm/mach-omap2/vc.c val = ((on_vsel << vc->common->cmd_on_shift) | val 830 arch/arm/mach-omap2/vc.c voltdm->write(val, vc->cmdval_reg); val 75 arch/arm/mach-omap2/voltage.h void (*write) (u32 val, u8 offset); val 42 arch/arm/mach-omap2/vp.c u32 val, sys_clk_rate, timeout, waittime; val 76 arch/arm/mach-omap2/vp.c val = (voltdm->pmic->vp_erroroffset << val 79 arch/arm/mach-omap2/vp.c voltdm->write(val, vp->vpconfig); val 82 arch/arm/mach-omap2/vp.c val = (waittime << vp->common->vstepmin_smpswaittimemin_shift) | val 84 arch/arm/mach-omap2/vp.c voltdm->write(val, vp->vstepmin); val 87 arch/arm/mach-omap2/vp.c val = (vstepmax << vp->common->vstepmax_stepmax_shift) | val 89 arch/arm/mach-omap2/vp.c voltdm->write(val, vp->vstepmax); val 92 arch/arm/mach-omap2/vp.c val = (vddmax << vp->common->vlimitto_vddmax_shift) | val 95 arch/arm/mach-omap2/vp.c voltdm->write(val, vp->vlimitto); val 77 arch/arm/mach-orion5x/pci.c int size, u32 *val) val 83 arch/arm/mach-orion5x/pci.c *val = 0xffffffff; val 88 arch/arm/mach-orion5x/pci.c ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); val 95 arch/arm/mach-orion5x/pci.c int where, int size, u32 *val) val 100 arch/arm/mach-orion5x/pci.c *val = 0xffffffff; val 110 arch/arm/mach-orion5x/pci.c *val = 0xffffffff; val 115 arch/arm/mach-orion5x/pci.c bus, devfn, where, size, val); val 121 arch/arm/mach-orion5x/pci.c int where, int size, u32 val) val 130 arch/arm/mach-orion5x/pci.c ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); val 274 arch/arm/mach-orion5x/pci.c u32 where, u32 size, u32 *val) val 283 arch/arm/mach-orion5x/pci.c *val = readl(PCI_CONF_DATA); val 286 arch/arm/mach-orion5x/pci.c *val = (*val >> (8*(where & 0x3))) & 0xff; val 288 arch/arm/mach-orion5x/pci.c *val = (*val >> (8*(where & 0x3))) & 0xffff; val 296 arch/arm/mach-orion5x/pci.c u32 where, u32 size, u32 val) val 308 arch/arm/mach-orion5x/pci.c __raw_writel(val, PCI_CONF_DATA); val 310 arch/arm/mach-orion5x/pci.c __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); val 312 arch/arm/mach-orion5x/pci.c __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); val 343 arch/arm/mach-orion5x/pci.c int where, int size, u32 *val) val 346 arch/arm/mach-orion5x/pci.c *val = 0xffffffff; val 351 arch/arm/mach-orion5x/pci.c PCI_FUNC(devfn), where, size, val); val 355 arch/arm/mach-orion5x/pci.c int where, int size, u32 val) val 361 arch/arm/mach-orion5x/pci.c PCI_FUNC(devfn), where, size, val); val 397 arch/arm/mach-orion5x/pci.c u32 val; val 402 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); val 403 arch/arm/mach-orion5x/pci.c val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); val 404 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); val 429 arch/arm/mach-orion5x/pci.c u32 val; val 435 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); val 436 arch/arm/mach-orion5x/pci.c val = (cs->base & 0xfffff000) | (val & 0xfff); val 437 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); val 67 arch/arm/mach-prima2/rtciobrg.c unsigned long flags, val; val 72 arch/arm/mach-prima2/rtciobrg.c val = __sirfsoc_rtc_iobrg_readl(addr); val 76 arch/arm/mach-prima2/rtciobrg.c return val; val 80 arch/arm/mach-prima2/rtciobrg.c void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr) val 87 arch/arm/mach-prima2/rtciobrg.c writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); val 90 arch/arm/mach-prima2/rtciobrg.c void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr) val 97 arch/arm/mach-prima2/rtciobrg.c sirfsoc_rtc_iobrg_pre_writel(val, addr); val 109 arch/arm/mach-prima2/rtciobrg.c unsigned int val) val 111 arch/arm/mach-prima2/rtciobrg.c sirfsoc_rtc_iobrg_writel(val, reg); val 116 arch/arm/mach-prima2/rtciobrg.c unsigned int *val) val 118 arch/arm/mach-prima2/rtciobrg.c *val = (u32)sirfsoc_rtc_iobrg_readl(reg); val 25 arch/arm/mach-pxa/include/mach/uncompress.h static inline void uart_write(unsigned char val, int offset) val 27 arch/arm/mach-pxa/include/mach/uncompress.h *(volatile unsigned char *)(uart_base + (offset << uart_shift)) = val; val 150 arch/arm/mach-pxa/mfp-pxa3xx.h static inline void pxa3xx_mfp_write(int mfp, unsigned long val) val 152 arch/arm/mach-pxa/mfp-pxa3xx.h mfp_write(mfp, val); val 270 arch/arm/mach-pxa/pcm990-baseboard.c u8 val; val 276 arch/arm/mach-pxa/pcm990-baseboard.c val = pcm990_cpld_readb(PCM990_CTRL_INTSETCLR); val 277 arch/arm/mach-pxa/pcm990-baseboard.c val |= 1 << pcm990_irq; val 278 arch/arm/mach-pxa/pcm990-baseboard.c pcm990_cpld_writeb(val, PCM990_CTRL_INTSETCLR); val 344 arch/arm/mach-pxa/pcm990-baseboard.c u8 val; val 346 arch/arm/mach-pxa/pcm990-baseboard.c val = pcm990_cpld_readb(PCM990_CTRL_REG5); val 349 arch/arm/mach-pxa/pcm990-baseboard.c val |= PCM990_CTRL_MMC2PWR; val 351 arch/arm/mach-pxa/pcm990-baseboard.c val &= ~PCM990_CTRL_MMC2PWR; val 44 arch/arm/mach-pxa/pxa3xx-ulpi.c static inline void u2d_writel(u32 reg, u32 val) val 46 arch/arm/mach-pxa/pxa3xx-ulpi.c __raw_writel(val, u2d->mmio_base + reg); val 98 arch/arm/mach-pxa/pxa3xx-ulpi.c static int pxa310_ulpi_write(struct usb_phy *otg, u32 val, u32 reg) val 105 arch/arm/mach-pxa/pxa3xx-ulpi.c u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8)); val 279 arch/arm/mach-pxa/sharpsl_pm.c void sharpsl_pm_led(int val) val 281 arch/arm/mach-pxa/sharpsl_pm.c if (val == SHARPSL_LED_ERROR) { val 283 arch/arm/mach-pxa/sharpsl_pm.c } else if (val == SHARPSL_LED_ON) { val 462 arch/arm/mach-pxa/sharpsl_pm.c static int get_select_val(int *val) val 467 arch/arm/mach-pxa/sharpsl_pm.c temp = val[0]; val 470 arch/arm/mach-pxa/sharpsl_pm.c if (temp < val[i]) { val 471 arch/arm/mach-pxa/sharpsl_pm.c temp = val[i]; val 477 arch/arm/mach-pxa/sharpsl_pm.c temp = val[4]; val 480 arch/arm/mach-pxa/sharpsl_pm.c if (temp > val[i]) { val 481 arch/arm/mach-pxa/sharpsl_pm.c temp = val[i]; val 488 arch/arm/mach-pxa/sharpsl_pm.c sum += val[i]; val 490 arch/arm/mach-pxa/sharpsl_pm.c dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]); val 497 arch/arm/mach-pxa/sharpsl_pm.c int val, i, buff[5]; val 508 arch/arm/mach-pxa/sharpsl_pm.c val = get_select_val(buff); val 510 arch/arm/mach-pxa/sharpsl_pm.c dev_dbg(sharpsl_pm.dev, "Temperature: %d\n", val); val 511 arch/arm/mach-pxa/sharpsl_pm.c if (val > sharpsl_pm.machinfo->charge_on_temp) { val 522 arch/arm/mach-pxa/sharpsl_pm.c int val, i, buff[5]; val 543 arch/arm/mach-pxa/sharpsl_pm.c val = get_select_val(buff); val 544 arch/arm/mach-pxa/sharpsl_pm.c dev_dbg(sharpsl_pm.dev, "Battery Voltage: %d\n", val); val 546 arch/arm/mach-pxa/sharpsl_pm.c if (val < sharpsl_pm.machinfo->charge_on_volt) val 100 arch/arm/mach-pxa/sharpsl_pm.h void sharpsl_pm_led(int val); val 887 arch/arm/mach-pxa/viper.c unsigned long val, void *data) val 893 arch/arm/mach-pxa/viper.c switch (val) { val 83 arch/arm/mach-qcom/platsmp.c u32 val; val 119 arch/arm/mach-qcom/platsmp.c val = PLL_CLAMP | L2DT_SLP | CLAMP; val 120 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); val 121 arch/arm/mach-qcom/platsmp.c val &= ~L2DT_SLP; val 122 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); val 126 arch/arm/mach-qcom/platsmp.c val |= COREPOR_RST; val 127 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); val 131 arch/arm/mach-qcom/platsmp.c val &= ~CLAMP; val 132 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); val 136 arch/arm/mach-qcom/platsmp.c val &= ~COREPOR_RST; val 137 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); val 141 arch/arm/mach-qcom/platsmp.c val |= CORE_PWRD_UP; val 142 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); val 40 arch/arm/mach-rockchip/platsmp.c u32 val; val 43 arch/arm/mach-rockchip/platsmp.c ret = regmap_read(pmu, PMU_PWRDN_ST, &val); val 47 arch/arm/mach-rockchip/platsmp.c return !(val & BIT(pd)); val 66 arch/arm/mach-rockchip/platsmp.c u32 val = (on) ? 0 : BIT(pd); val 85 arch/arm/mach-rockchip/platsmp.c ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); val 57 arch/arm/mach-rpc/include/mach/hardware.h #define vidc_writel(val) __raw_writel(val, VIDC_BASE) val 35 arch/arm/mach-rpc/irq.c unsigned int val, mask = d->mask; val 37 arch/arm/mach-rpc/irq.c val = readb(base + MASK); val 38 arch/arm/mach-rpc/irq.c writeb(val & ~mask, base + MASK); val 45 arch/arm/mach-rpc/irq.c unsigned int val, mask = d->mask; val 47 arch/arm/mach-rpc/irq.c val = readb(base + MASK); val 48 arch/arm/mach-rpc/irq.c writeb(val & ~mask, base + MASK); val 54 arch/arm/mach-rpc/irq.c unsigned int val, mask = d->mask; val 56 arch/arm/mach-rpc/irq.c val = readb(base + MASK); val 57 arch/arm/mach-rpc/irq.c writeb(val | mask, base + MASK); val 37 arch/arm/mach-s3c24xx/include/mach/io.h static inline void __out##fnsuffix (unsigned int val, unsigned int port) \ val 46 arch/arm/mach-s3c24xx/include/mach/io.h : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ val 105 arch/arm/mach-s3c24xx/iotiming-s3c2410.c unsigned long val; val 112 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 0; val 115 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 1; val 118 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 2; val 122 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 3; val 128 arch/arm/mach-s3c24xx/iotiming-s3c2410.c *v |= val << shift; val 153 arch/arm/mach-s3c24xx/iotiming-s3c2410.c unsigned long val; val 164 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 0; val 171 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = div - 1; val 176 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 4; val 181 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 5; val 186 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 6; val 193 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val = 7; val 200 arch/arm/mach-s3c24xx/iotiming-s3c2410.c *v |= val << 8; val 265 arch/arm/mach-s3c24xx/iotiming-s3c2410.c unsigned long val) val 267 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val &= 7; val 268 arch/arm/mach-s3c24xx/iotiming-s3c2410.c return hclk_tns * tacc_tab[val]; val 277 arch/arm/mach-s3c24xx/iotiming-s3c2410.c unsigned long val) val 279 arch/arm/mach-s3c24xx/iotiming-s3c2410.c val &= 3; val 280 arch/arm/mach-s3c24xx/iotiming-s3c2410.c return hclk_tns * ((val == 3) ? 4 : val); val 51 arch/arm/mach-s3c24xx/mach-osiris-dvs.c unsigned long val, void *data) val 66 arch/arm/mach-s3c24xx/mach-osiris-dvs.c switch (val) { val 31 arch/arm/mach-s3c24xx/simtec-nor.c unsigned int val; val 33 arch/arm/mach-s3c24xx/simtec-nor.c val = __raw_readb(BAST_VA_CTRL3); val 38 arch/arm/mach-s3c24xx/simtec-nor.c val |= BAST_CPLD_CTRL3_ROMWEN; val 40 arch/arm/mach-s3c24xx/simtec-nor.c val &= ~BAST_CPLD_CTRL3_ROMWEN; val 42 arch/arm/mach-s3c24xx/simtec-nor.c __raw_writeb(val, BAST_VA_CTRL3); val 44 arch/arm/mach-s3c64xx/pm.c u32 val; val 48 arch/arm/mach-s3c64xx/pm.c val = __raw_readl(S3C64XX_NORMAL_CFG); val 49 arch/arm/mach-s3c64xx/pm.c val &= ~(pd->ena); val 50 arch/arm/mach-s3c64xx/pm.c __raw_writel(val, S3C64XX_NORMAL_CFG); val 58 arch/arm/mach-s3c64xx/pm.c u32 val; val 63 arch/arm/mach-s3c64xx/pm.c val = __raw_readl(S3C64XX_NORMAL_CFG); val 64 arch/arm/mach-s3c64xx/pm.c val |= pd->ena; val 65 arch/arm/mach-s3c64xx/pm.c __raw_writel(val, S3C64XX_NORMAL_CFG); val 80 arch/arm/mach-sa1100/assabet.c void ASSABET_BCR_frob(unsigned int mask, unsigned int val) val 82 arch/arm/mach-sa1100/assabet.c unsigned long m = mask, v = val; val 171 arch/arm/mach-sa1100/assabet.c static void adv7171_write(unsigned reg, unsigned val) val 189 arch/arm/mach-sa1100/assabet.c adv7171_send(val); val 123 arch/arm/mach-sa1100/neponset.c void neponset_ncr_frob(unsigned int mask, unsigned int val) val 126 arch/arm/mach-sa1100/neponset.c unsigned long m = mask, v = val; val 27 arch/arm/mach-spear/pl080.c unsigned char val; val 32 arch/arm/mach-spear/pl080.c unsigned int signal = cd->min_signal, val; val 39 arch/arm/mach-spear/pl080.c (signals[signal].val != cd->muxval)) { val 46 arch/arm/mach-spear/pl080.c val = readl(DMA_CHN_CFG); val 53 arch/arm/mach-spear/pl080.c val &= ~(0x3 << (signal * 2)); val 54 arch/arm/mach-spear/pl080.c val |= cd->muxval << (signal * 2); val 55 arch/arm/mach-spear/pl080.c writel(val, DMA_CHN_CFG); val 59 arch/arm/mach-spear/pl080.c signals[signal].val = cd->muxval; val 30 arch/arm/mach-spear/platsmp.c static void spear_write_pen_release(int val) val 32 arch/arm/mach-spear/platsmp.c spear_pen_release = val; val 75 arch/arm/mach-spear/time.c u16 val; val 86 arch/arm/mach-spear/time.c val = readw(gpt_base + CR(CLKSRC)); val 87 arch/arm/mach-spear/time.c val &= ~CTRL_ONE_SHOT; /* autoreload mode */ val 88 arch/arm/mach-spear/time.c val |= CTRL_ENABLE ; val 89 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKSRC)); val 98 arch/arm/mach-spear/time.c u16 val = readw(gpt_base + CR(CLKEVT)); val 101 arch/arm/mach-spear/time.c val &= ~CTRL_ENABLE; val 102 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKEVT)); val 114 arch/arm/mach-spear/time.c u16 val; val 119 arch/arm/mach-spear/time.c val = readw(gpt_base + CR(CLKEVT)); val 120 arch/arm/mach-spear/time.c val |= CTRL_ONE_SHOT; val 121 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKEVT)); val 129 arch/arm/mach-spear/time.c u16 val; val 138 arch/arm/mach-spear/time.c val = readw(gpt_base + CR(CLKEVT)); val 139 arch/arm/mach-spear/time.c val &= ~CTRL_ONE_SHOT; val 140 arch/arm/mach-spear/time.c val |= CTRL_ENABLE | CTRL_INT_ENABLE; val 141 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKEVT)); val 160 arch/arm/mach-spear/time.c u16 val = readw(gpt_base + CR(CLKEVT)); val 162 arch/arm/mach-spear/time.c if (val & CTRL_ENABLE) val 163 arch/arm/mach-spear/time.c writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); val 167 arch/arm/mach-spear/time.c val |= CTRL_ENABLE | CTRL_INT_ENABLE; val 168 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKEVT)); val 23 arch/arm/mach-sti/board-dt.c static void sti_l2_write_sec(unsigned long val, unsigned reg) val 7 arch/arm/mach-tango/setup.c static void tango_l2c_write(unsigned long val, unsigned int reg) val 10 arch/arm/mach-tango/setup.c tango_set_l2_control(val); val 2 arch/arm/mach-tango/smc.h extern int tango_smc(unsigned int val, unsigned int service); val 4 arch/arm/mach-tango/smc.h #define tango_set_l2_control(val) tango_smc(val, 0x102) val 5 arch/arm/mach-tango/smc.h #define tango_start_aux_core(val) tango_smc(val, 0x104) val 6 arch/arm/mach-tango/smc.h #define tango_set_aux_boot_addr(val) tango_smc(val, 0x105) val 7 arch/arm/mach-tango/smc.h #define tango_suspend(val) tango_smc(val, 0x120) val 8 arch/arm/mach-tango/smc.h #define tango_aux_core_die(val) tango_smc(val, 0x121) val 9 arch/arm/mach-tango/smc.h #define tango_aux_core_kill(val) tango_smc(val, 0x122) val 75 arch/arm/mach-tegra/sleep.h .macro mov32, reg, val val 271 arch/arm/mach-u300/core.c u16 val; val 277 arch/arm/mach-u300/core.c val = readw(syscon_base + U300_SYSCON_CIDR); val 279 arch/arm/mach-u300/core.c val = (val & 0xFFU) << 8 | (val >> 8); val 284 arch/arm/mach-u300/core.c if (chip->chipid == (val & 0xFF00U)) { val 290 arch/arm/mach-u300/core.c "(chip ID 0x%04x)\n", chipname, val); val 292 arch/arm/mach-u300/core.c if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { val 384 arch/arm/mach-u300/core.c u16 val; val 396 arch/arm/mach-u300/core.c val = readw(syscon_base + U300_SYSCON_SMCR) | val 398 arch/arm/mach-u300/core.c writew(val, syscon_base + U300_SYSCON_SMCR); val 61 arch/arm/mach-ux500/cpu-db8500.c static void ux500_l2c310_write_sec(unsigned long val, unsigned reg) val 49 arch/arm/mach-ux500/pm.c u32 val = readl(PRCM_A9_MASK_REQ); val 52 arch/arm/mach-ux500/pm.c writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, val 67 arch/arm/mach-ux500/pm.c u32 val = readl(PRCM_A9_MASK_REQ); val 70 arch/arm/mach-ux500/pm.c writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); val 111 arch/arm/mach-versatile/versatile_dt.c u32 val; val 118 arch/arm/mach-versatile/versatile_dt.c val = readl(__io_address(VERSATILE_SCTL_BASE)); val 122 arch/arm/mach-versatile/versatile_dt.c (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, val 128 arch/arm/mach-versatile/versatile_dt.c u32 val; val 137 arch/arm/mach-versatile/versatile_dt.c val = readl(versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET); val 138 arch/arm/mach-versatile/versatile_dt.c if (val & 1) { val 41 arch/arm/mach-zynq/slcr.c static int zynq_slcr_write(u32 val, u32 offset) val 43 arch/arm/mach-zynq/slcr.c return regmap_write(zynq_slcr_regmap, offset, val); val 54 arch/arm/mach-zynq/slcr.c static int zynq_slcr_read(u32 *val, u32 offset) val 56 arch/arm/mach-zynq/slcr.c return regmap_read(zynq_slcr_regmap, offset, val); val 78 arch/arm/mach-zynq/slcr.c u32 val; val 80 arch/arm/mach-zynq/slcr.c zynq_slcr_read(&val, SLCR_PSS_IDCODE); val 81 arch/arm/mach-zynq/slcr.c val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT; val 82 arch/arm/mach-zynq/slcr.c val &= SLCR_PSS_IDCODE_DEVICE_MASK; val 84 arch/arm/mach-zynq/slcr.c return val; val 196 arch/arm/mm/alignment.c #define __get8_unaligned_check(ins,val,addr,err) \ val 211 arch/arm/mm/alignment.c : "=r" (err), "=&r" (val), "=r" (addr) \ val 214 arch/arm/mm/alignment.c #define __get16_unaligned_check(ins,val,addr) \ val 218 arch/arm/mm/alignment.c val = v << ((BE) ? 8 : 0); \ val 220 arch/arm/mm/alignment.c val |= v << ((BE) ? 0 : 8); \ val 225 arch/arm/mm/alignment.c #define get16_unaligned_check(val,addr) \ val 226 arch/arm/mm/alignment.c __get16_unaligned_check("ldrb",val,addr) val 228 arch/arm/mm/alignment.c #define get16t_unaligned_check(val,addr) \ val 229 arch/arm/mm/alignment.c __get16_unaligned_check("ldrbt",val,addr) val 231 arch/arm/mm/alignment.c #define __get32_unaligned_check(ins,val,addr) \ val 235 arch/arm/mm/alignment.c val = v << ((BE) ? 24 : 0); \ val 237 arch/arm/mm/alignment.c val |= v << ((BE) ? 16 : 8); \ val 239 arch/arm/mm/alignment.c val |= v << ((BE) ? 8 : 16); \ val 241 arch/arm/mm/alignment.c val |= v << ((BE) ? 0 : 24); \ val 246 arch/arm/mm/alignment.c #define get32_unaligned_check(val,addr) \ val 247 arch/arm/mm/alignment.c __get32_unaligned_check("ldrb",val,addr) val 249 arch/arm/mm/alignment.c #define get32t_unaligned_check(val,addr) \ val 250 arch/arm/mm/alignment.c __get32_unaligned_check("ldrbt",val,addr) val 252 arch/arm/mm/alignment.c #define __put16_unaligned_check(ins,val,addr) \ val 254 arch/arm/mm/alignment.c unsigned int err = 0, v = val, a = addr; \ val 278 arch/arm/mm/alignment.c #define put16_unaligned_check(val,addr) \ val 279 arch/arm/mm/alignment.c __put16_unaligned_check("strb",val,addr) val 281 arch/arm/mm/alignment.c #define put16t_unaligned_check(val,addr) \ val 282 arch/arm/mm/alignment.c __put16_unaligned_check("strbt",val,addr) val 284 arch/arm/mm/alignment.c #define __put32_unaligned_check(ins,val,addr) \ val 286 arch/arm/mm/alignment.c unsigned int err = 0, v = val, a = addr; \ val 320 arch/arm/mm/alignment.c #define put32_unaligned_check(val,addr) \ val 321 arch/arm/mm/alignment.c __put32_unaligned_check("strb", val, addr) val 323 arch/arm/mm/alignment.c #define put32t_unaligned_check(val,addr) \ val 324 arch/arm/mm/alignment.c __put32_unaligned_check("strbt", val, addr) val 350 arch/arm/mm/alignment.c unsigned long val; val 351 arch/arm/mm/alignment.c get16_unaligned_check(val, addr); val 355 arch/arm/mm/alignment.c val = (signed long)((signed short) val); val 357 arch/arm/mm/alignment.c regs->uregs[rd] = val; val 365 arch/arm/mm/alignment.c unsigned long val; val 368 arch/arm/mm/alignment.c get16t_unaligned_check(val, addr); val 373 arch/arm/mm/alignment.c val = (signed long)((signed short) val); val 375 arch/arm/mm/alignment.c regs->uregs[rd] = val; val 412 arch/arm/mm/alignment.c unsigned long val; val 413 arch/arm/mm/alignment.c get32_unaligned_check(val, addr); val 414 arch/arm/mm/alignment.c regs->uregs[rd] = val; val 415 arch/arm/mm/alignment.c get32_unaligned_check(val, addr + 4); val 416 arch/arm/mm/alignment.c regs->uregs[rd2] = val; val 426 arch/arm/mm/alignment.c unsigned long val, val2; val 429 arch/arm/mm/alignment.c get32t_unaligned_check(val, addr); val 434 arch/arm/mm/alignment.c regs->uregs[rd] = val; val 461 arch/arm/mm/alignment.c unsigned int val; val 462 arch/arm/mm/alignment.c get32_unaligned_check(val, addr); val 463 arch/arm/mm/alignment.c regs->uregs[rd] = val; val 470 arch/arm/mm/alignment.c unsigned int val; val 472 arch/arm/mm/alignment.c get32t_unaligned_check(val, addr); val 474 arch/arm/mm/alignment.c regs->uregs[rd] = val; val 554 arch/arm/mm/alignment.c unsigned int val; val 555 arch/arm/mm/alignment.c get32t_unaligned_check(val, eaddr); val 556 arch/arm/mm/alignment.c regs->uregs[rd] = val; val 567 arch/arm/mm/alignment.c unsigned int val; val 568 arch/arm/mm/alignment.c get32_unaligned_check(val, eaddr); val 569 arch/arm/mm/alignment.c regs->uregs[rd] = val; val 64 arch/arm/mm/cache-b15-rac.c u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); val 67 arch/arm/mm/cache-b15-rac.c return val; val 94 arch/arm/mm/cache-b15-rac.c static inline void __b15_rac_enable(u32 val) val 96 arch/arm/mm/cache-b15-rac.c __raw_writel(val, b15_rac_base + RAC_CONFIG0_REG); val 105 arch/arm/mm/cache-b15-rac.c u32 val = 0; \ val 116 arch/arm/mm/cache-b15-rac.c val = b15_rac_disable_and_flush(); \ val 121 arch/arm/mm/cache-b15-rac.c __b15_rac_enable(val); \ val 64 arch/arm/mm/cache-l2x0-pmu.c static void l2x0_pmu_counter_config_write(int idx, u32 val) val 66 arch/arm/mm/cache-l2x0-pmu.c writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_CFG - 4 * idx); val 74 arch/arm/mm/cache-l2x0-pmu.c static void l2x0_pmu_counter_write(int idx, u32 val) val 76 arch/arm/mm/cache-l2x0-pmu.c writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx); val 81 arch/arm/mm/cache-l2x0-pmu.c u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL); val 82 arch/arm/mm/cache-l2x0-pmu.c val |= L2X0_EVENT_CNT_CTRL_ENABLE; val 83 arch/arm/mm/cache-l2x0-pmu.c writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL); val 88 arch/arm/mm/cache-l2x0-pmu.c u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL); val 89 arch/arm/mm/cache-l2x0-pmu.c val &= ~L2X0_EVENT_CNT_CTRL_ENABLE; val 90 arch/arm/mm/cache-l2x0-pmu.c writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL); val 179 arch/arm/mm/cache-l2x0-pmu.c u32 val; val 181 arch/arm/mm/cache-l2x0-pmu.c val = event << L2X0_EVENT_CNT_CFG_SRC_SHIFT; val 182 arch/arm/mm/cache-l2x0-pmu.c val |= L2X0_EVENT_CNT_CFG_INT_DISABLED; val 183 arch/arm/mm/cache-l2x0-pmu.c l2x0_pmu_counter_config_write(idx, val); val 205 arch/arm/mm/cache-l2x0-pmu.c u32 val; val 207 arch/arm/mm/cache-l2x0-pmu.c val = L2X0_EVENT_CNT_CFG_SRC_DISABLED << L2X0_EVENT_CNT_CFG_SRC_SHIFT; val 208 arch/arm/mm/cache-l2x0-pmu.c val |= L2X0_EVENT_CNT_CFG_INT_DISABLED; val 209 arch/arm/mm/cache-l2x0-pmu.c l2x0_pmu_counter_config_write(idx, val); val 65 arch/arm/mm/cache-l2x0.c static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) val 67 arch/arm/mm/cache-l2x0.c if (val == readl_relaxed(base + reg)) val 70 arch/arm/mm/cache-l2x0.c outer_cache.write_sec(val, reg); val 72 arch/arm/mm/cache-l2x0.c writel_relaxed(val, base + reg); val 80 arch/arm/mm/cache-l2x0.c static inline void l2c_set_debug(void __iomem *base, unsigned long val) val 82 arch/arm/mm/cache-l2x0.c l2c_write_sec(val, base, L2X0_DEBUG_CTRL); val 706 arch/arm/mm/cache-l2x0.c u32 val = l2x0_saved_regs.prefetch_ctrl; val 707 arch/arm/mm/cache-l2x0.c if (val & L310_PREFETCH_CTRL_DBL_LINEFILL) { val 708 arch/arm/mm/cache-l2x0.c val &= ~L310_PREFETCH_CTRL_DBL_LINEFILL; val 709 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.prefetch_ctrl = val; val 947 arch/arm/mm/cache-l2x0.c u32 mask = 0, val = 0; val 1017 arch/arm/mm/cache-l2x0.c val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT); val 1020 arch/arm/mm/cache-l2x0.c *aux_val |= val; val 1032 arch/arm/mm/cache-l2x0.c u32 val = 0, mask = 0; val 1039 arch/arm/mm/cache-l2x0.c val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; val 1047 arch/arm/mm/cache-l2x0.c val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | val 1054 arch/arm/mm/cache-l2x0.c val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; val 1059 arch/arm/mm/cache-l2x0.c val |= L2C_AUX_CTRL_PARITY_ENABLE; val 1066 arch/arm/mm/cache-l2x0.c val |= L2C_AUX_CTRL_SHARED_OVERRIDE; val 1078 arch/arm/mm/cache-l2x0.c val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT); val 1082 arch/arm/mm/cache-l2x0.c *aux_val |= val; val 1135 arch/arm/mm/cache-l2x0.c u32 val; val 1202 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "arm,double-linefill", &val); val 1204 arch/arm/mm/cache-l2x0.c if (val) val 1212 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "arm,double-linefill-incr", &val); val 1214 arch/arm/mm/cache-l2x0.c if (val) val 1222 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val); val 1224 arch/arm/mm/cache-l2x0.c if (!val) val 1232 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "arm,prefetch-drop", &val); val 1234 arch/arm/mm/cache-l2x0.c if (val) val 1242 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "arm,prefetch-offset", &val); val 1245 arch/arm/mm/cache-l2x0.c prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK; val 1250 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "prefetch-data", &val); val 1252 arch/arm/mm/cache-l2x0.c if (val) val 1260 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "prefetch-instr", &val); val 1262 arch/arm/mm/cache-l2x0.c if (val) val 1275 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "arm,dynamic-clock-gating", &val); val 1277 arch/arm/mm/cache-l2x0.c if (!val) val 1282 arch/arm/mm/cache-l2x0.c ret = of_property_read_u32(np, "arm,standby-mode", &val); val 1284 arch/arm/mm/cache-l2x0.c if (!val) val 1482 arch/arm/mm/cache-l2x0.c u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; val 1492 arch/arm/mm/cache-l2x0.c val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; val 1498 arch/arm/mm/cache-l2x0.c val |= AURORA_ACR_ECC_EN; val 1503 arch/arm/mm/cache-l2x0.c val |= AURORA_ACR_PARITY_EN; val 1509 arch/arm/mm/cache-l2x0.c *aux_val |= val; val 219 arch/arm/mm/cache-uniphier.c u32 val = 0; val 222 arch/arm/mm/cache-uniphier.c val = UNIPHIER_SSCC_WTG | UNIPHIER_SSCC_PRD | UNIPHIER_SSCC_ON; val 224 arch/arm/mm/cache-uniphier.c writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC); val 511 arch/arm/mm/dma-mapping.c unsigned long val; val 519 arch/arm/mm/dma-mapping.c val = gen_pool_alloc(atomic_pool, size); val 520 arch/arm/mm/dma-mapping.c if (val) { val 521 arch/arm/mm/dma-mapping.c phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); val 524 arch/arm/mm/dma-mapping.c ptr = (void *)val; val 58 arch/arm/mm/dump.c u64 val; val 68 arch/arm/mm/dump.c .val = L_PTE_USER, val 73 arch/arm/mm/dump.c .val = L_PTE_RDONLY, val 79 arch/arm/mm/dump.c .val = L_PTE_XN, val 85 arch/arm/mm/dump.c .val = L_PTE_SHARED, val 90 arch/arm/mm/dump.c .val = L_PTE_MT_UNCACHED, val 94 arch/arm/mm/dump.c .val = L_PTE_MT_BUFFERABLE, val 98 arch/arm/mm/dump.c .val = L_PTE_MT_WRITETHROUGH, val 102 arch/arm/mm/dump.c .val = L_PTE_MT_WRITEBACK, val 107 arch/arm/mm/dump.c .val = L_PTE_MT_MINICACHE, val 112 arch/arm/mm/dump.c .val = L_PTE_MT_WRITEALLOC, val 116 arch/arm/mm/dump.c .val = L_PTE_MT_DEV_SHARED, val 121 arch/arm/mm/dump.c .val = L_PTE_MT_DEV_NONSHARED, val 126 arch/arm/mm/dump.c .val = L_PTE_MT_DEV_WC, val 130 arch/arm/mm/dump.c .val = L_PTE_MT_DEV_CACHED, val 139 arch/arm/mm/dump.c .val = PMD_SECT_USER, val 143 arch/arm/mm/dump.c .val = L_PMD_SECT_RDONLY | PMD_SECT_AP2, val 150 arch/arm/mm/dump.c .val = PMD_SECT_APX | PMD_SECT_AP_WRITE, val 155 arch/arm/mm/dump.c .val = PMD_SECT_AP_WRITE, val 159 arch/arm/mm/dump.c .val = PMD_SECT_AP_READ, val 163 arch/arm/mm/dump.c .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, val 169 arch/arm/mm/dump.c .val = 0, val 174 arch/arm/mm/dump.c .val = PMD_SECT_AP_WRITE, val 178 arch/arm/mm/dump.c .val = PMD_SECT_AP_READ, val 182 arch/arm/mm/dump.c .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, val 187 arch/arm/mm/dump.c .val = PMD_SECT_XN, val 193 arch/arm/mm/dump.c .val = PMD_SECT_S, val 227 arch/arm/mm/dump.c if ((st->current_prot & bits->mask) == bits->val) val 242 arch/arm/mm/dump.c pg_level[st->level].ro_bit->val) val 245 arch/arm/mm/dump.c pg_level[st->level].nx_bit->val) val 255 arch/arm/mm/dump.c unsigned int level, u64 val, const char *domain) val 258 arch/arm/mm/dump.c u64 prot = val & pg_level[level].mask; val 215 arch/arm/mm/fault-armv.c register unsigned long zero = 0, one = 1, val; val 223 arch/arm/mm/fault-armv.c val = *p1; val 226 arch/arm/mm/fault-armv.c return val != zero; val 44 arch/arm/mm/nommu.c static inline void set_vbar(unsigned long val) val 46 arch/arm/mm/nommu.c asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); val 414 arch/arm/net/bpf_jit_32.c static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx) val 417 arch/arm/net/bpf_jit_32.c emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx); val 419 arch/arm/net/bpf_jit_32.c emit(ARM_MOVW(rd, val & 0xffff), ctx); val 420 arch/arm/net/bpf_jit_32.c if (val > 0xffff) val 421 arch/arm/net/bpf_jit_32.c emit(ARM_MOVT(rd, val >> 16), ctx); val 425 arch/arm/net/bpf_jit_32.c static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx) val 427 arch/arm/net/bpf_jit_32.c int imm12 = imm8m(val); val 432 arch/arm/net/bpf_jit_32.c emit_mov_i_no8m(rd, val, ctx); val 586 arch/arm/net/bpf_jit_32.c static inline void emit_a32_mov_i(const s8 dst, const u32 val, val 592 arch/arm/net/bpf_jit_32.c emit_mov_i(tmp[1], val, ctx); val 595 arch/arm/net/bpf_jit_32.c emit_mov_i(dst, val, ctx); val 599 arch/arm/net/bpf_jit_32.c static void emit_a32_mov_i64(const s8 dst[], u64 val, struct jit_ctx *ctx) val 604 arch/arm/net/bpf_jit_32.c emit_mov_i(rd[1], (u32)val, ctx); val 605 arch/arm/net/bpf_jit_32.c emit_mov_i(rd[0], val >> 32, ctx); val 612 arch/arm/net/bpf_jit_32.c const u32 val, struct jit_ctx *ctx) { val 613 arch/arm/net/bpf_jit_32.c u64 val64 = val; val 615 arch/arm/net/bpf_jit_32.c if (is64 && (val & (1<<31))) val 783 arch/arm/net/bpf_jit_32.c static inline void emit_a32_alu_i(const s8 dst, const u32 val, val 793 arch/arm/net/bpf_jit_32.c emit(ARM_LSL_I(rd, rd, val), ctx); val 796 arch/arm/net/bpf_jit_32.c emit(ARM_LSR_I(rd, rd, val), ctx); val 799 arch/arm/net/bpf_jit_32.c emit(ARM_RSB_I(rd, rd, val), ctx); val 897 arch/arm/net/bpf_jit_32.c const u32 val, struct jit_ctx *ctx){ val 906 arch/arm/net/bpf_jit_32.c if (val < 32) { val 907 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(tmp2[0], rd[0], SRTYPE_ASL, val), ctx); val 908 arch/arm/net/bpf_jit_32.c emit(ARM_ORR_SI(rd[0], tmp2[0], rd[1], SRTYPE_LSR, 32 - val), ctx); val 909 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(rd[1], rd[1], SRTYPE_ASL, val), ctx); val 911 arch/arm/net/bpf_jit_32.c if (val == 32) val 914 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(rd[0], rd[1], SRTYPE_ASL, val - 32), ctx); val 923 arch/arm/net/bpf_jit_32.c const u32 val, struct jit_ctx *ctx) { val 932 arch/arm/net/bpf_jit_32.c if (val == 0) { val 936 arch/arm/net/bpf_jit_32.c } else if (val < 32) { val 937 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx); val 938 arch/arm/net/bpf_jit_32.c emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx); val 939 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_LSR, val), ctx); val 940 arch/arm/net/bpf_jit_32.c } else if (val == 32) { val 944 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_LSR, val - 32), ctx); val 953 arch/arm/net/bpf_jit_32.c const u32 val, struct jit_ctx *ctx){ val 962 arch/arm/net/bpf_jit_32.c if (val == 0) { val 966 arch/arm/net/bpf_jit_32.c } else if (val < 32) { val 967 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx); val 968 arch/arm/net/bpf_jit_32.c emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx); val 969 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, val), ctx); val 970 arch/arm/net/bpf_jit_32.c } else if (val == 32) { val 974 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_ASR, val - 32), ctx); val 1591 arch/arm/net/bpf_jit_32.c u64 val = (u32)imm | (u64)insn[1].imm << 32; val 1593 arch/arm/net/bpf_jit_32.c emit_a32_mov_i64(dst, val, ctx); val 97 arch/arm/nwfpe/fpa11_cpdt.c } val; val 101 arch/arm/nwfpe/fpa11_cpdt.c val.f = float64_to_float32(roundData, fpa11->fpreg[Fn].fDouble); val 106 arch/arm/nwfpe/fpa11_cpdt.c val.f = floatx80_to_float32(roundData, fpa11->fpreg[Fn].fExtended); val 111 arch/arm/nwfpe/fpa11_cpdt.c val.f = fpa11->fpreg[Fn].fSingle; val 114 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[0], pMem); val 123 arch/arm/nwfpe/fpa11_cpdt.c } val; val 127 arch/arm/nwfpe/fpa11_cpdt.c val.f = float32_to_float64(fpa11->fpreg[Fn].fSingle); val 132 arch/arm/nwfpe/fpa11_cpdt.c val.f = floatx80_to_float64(roundData, fpa11->fpreg[Fn].fExtended); val 137 arch/arm/nwfpe/fpa11_cpdt.c val.f = fpa11->fpreg[Fn].fDouble; val 141 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[0], &pMem[0]); /* msw */ val 142 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[1], &pMem[1]); /* lsw */ val 144 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[1], &pMem[0]); /* msw */ val 145 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[0], &pMem[1]); /* lsw */ val 156 arch/arm/nwfpe/fpa11_cpdt.c } val; val 160 arch/arm/nwfpe/fpa11_cpdt.c val.f = float32_to_floatx80(fpa11->fpreg[Fn].fSingle); val 164 arch/arm/nwfpe/fpa11_cpdt.c val.f = float64_to_floatx80(fpa11->fpreg[Fn].fDouble); val 168 arch/arm/nwfpe/fpa11_cpdt.c val.f = fpa11->fpreg[Fn].fExtended; val 171 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[0], &pMem[0]); /* sign & exp */ val 173 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[1], &pMem[1]); /* msw */ val 174 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[2], &pMem[2]); val 176 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[1], &pMem[2]); val 177 arch/arm/nwfpe/fpa11_cpdt.c put_user(val.i[2], &pMem[1]); /* msw */ val 168 arch/arm/plat-omap/dma.c #define omap_writel(val, reg) do {} while (0) val 246 arch/arm/plat-omap/dma.c u32 val; val 248 arch/arm/plat-omap/dma.c val = p->dma_read(CCR, lch); val 251 arch/arm/plat-omap/dma.c val &= ~((1 << 23) | (3 << 19) | 0x1f); val 252 arch/arm/plat-omap/dma.c val |= (dma_trigger & ~0x1f) << 14; val 253 arch/arm/plat-omap/dma.c val |= dma_trigger & 0x1f; val 256 arch/arm/plat-omap/dma.c val |= 1 << 5; val 258 arch/arm/plat-omap/dma.c val &= ~(1 << 5); val 261 arch/arm/plat-omap/dma.c val |= 1 << 18; val 263 arch/arm/plat-omap/dma.c val &= ~(1 << 18); val 266 arch/arm/plat-omap/dma.c val &= ~(1 << 24); /* dest synch */ val 267 arch/arm/plat-omap/dma.c val |= (1 << 23); /* Prefetch */ val 269 arch/arm/plat-omap/dma.c val |= 1 << 24; /* source synch */ val 271 arch/arm/plat-omap/dma.c val &= ~(1 << 24); /* dest synch */ val 273 arch/arm/plat-omap/dma.c p->dma_write(val, CCR, lch); val 569 arch/arm/plat-omap/dma.c u32 val; val 579 arch/arm/plat-omap/dma.c val = p->dma_read(IRQENABLE_L0, lch); val 580 arch/arm/plat-omap/dma.c val |= 1 << lch; val 581 arch/arm/plat-omap/dma.c p->dma_write(val, IRQENABLE_L0, lch); val 587 arch/arm/plat-omap/dma.c u32 val; val 595 arch/arm/plat-omap/dma.c val = p->dma_read(IRQENABLE_L0, lch); val 596 arch/arm/plat-omap/dma.c val &= ~(1 << lch); val 597 arch/arm/plat-omap/dma.c p->dma_write(val, IRQENABLE_L0, lch); val 1211 arch/arm/plat-omap/dma.c u32 val, enable_reg; val 1214 arch/arm/plat-omap/dma.c val = p->dma_read(IRQSTATUS_L0, 0); val 1215 arch/arm/plat-omap/dma.c if (val == 0) { val 1221 arch/arm/plat-omap/dma.c val &= enable_reg; /* Dispatch only relevant interrupts */ val 1222 arch/arm/plat-omap/dma.c for (i = 0; i < dma_lch_count && val != 0; i++) { val 1223 arch/arm/plat-omap/dma.c if (val & 1) val 1225 arch/arm/plat-omap/dma.c val >>= 1; val 184 arch/arm/plat-orion/gpio.c int val; val 187 arch/arm/plat-orion/gpio.c val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); val 189 arch/arm/plat-orion/gpio.c val = readl(GPIO_OUT(ochip)); val 192 arch/arm/plat-orion/gpio.c return (val >> pin) & 1; val 25 arch/arm/plat-orion/include/plat/pcie.h u32 devfn, int where, int size, u32 *val); val 27 arch/arm/plat-orion/include/plat/pcie.h u32 devfn, int where, int size, u32 *val); val 29 arch/arm/plat-orion/include/plat/pcie.h u32 devfn, int where, int size, u32 *val); val 31 arch/arm/plat-orion/include/plat/pcie.h u32 devfn, int where, int size, u32 val); val 209 arch/arm/plat-orion/pcie.c u32 devfn, int where, int size, u32 *val) val 217 arch/arm/plat-orion/pcie.c *val = readl(base + PCIE_CONF_DATA_OFF); val 220 arch/arm/plat-orion/pcie.c *val = (*val >> (8 * (where & 3))) & 0xff; val 222 arch/arm/plat-orion/pcie.c *val = (*val >> (8 * (where & 3))) & 0xffff; val 228 arch/arm/plat-orion/pcie.c u32 devfn, int where, int size, u32 *val) val 236 arch/arm/plat-orion/pcie.c *val = readl(base + PCIE_CONF_DATA_OFF); val 240 arch/arm/plat-orion/pcie.c *val = readl(base + PCIE_HEADER_LOG_4_OFF); val 243 arch/arm/plat-orion/pcie.c *val = (*val >> (8 * (where & 3))) & 0xff; val 245 arch/arm/plat-orion/pcie.c *val = (*val >> (8 * (where & 3))) & 0xffff; val 251 arch/arm/plat-orion/pcie.c u32 devfn, int where, int size, u32 *val) val 253 arch/arm/plat-orion/pcie.c *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) | val 259 arch/arm/plat-orion/pcie.c *val = (*val >> (8 * (where & 3))) & 0xff; val 261 arch/arm/plat-orion/pcie.c *val = (*val >> (8 * (where & 3))) & 0xffff; val 267 arch/arm/plat-orion/pcie.c u32 devfn, int where, int size, u32 val) val 278 arch/arm/plat-orion/pcie.c writel(val, base + PCIE_CONF_DATA_OFF); val 280 arch/arm/plat-orion/pcie.c writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); val 282 arch/arm/plat-orion/pcie.c writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); val 132 arch/arm/plat-pxa/mfp.c #define mfpr_writel(off, val) \ val 133 arch/arm/plat-pxa/mfp.c __raw_writel(val, mfpr_mmio_base + (off)) val 206 arch/arm/plat-pxa/mfp.c unsigned long val, flags; val 211 arch/arm/plat-pxa/mfp.c val = mfpr_readl(mfp_table[mfp].mfpr_off); val 214 arch/arm/plat-pxa/mfp.c return val; val 217 arch/arm/plat-pxa/mfp.c void mfp_write(int mfp, unsigned long val) val 224 arch/arm/plat-pxa/mfp.c mfpr_writel(mfp_table[mfp].mfpr_off, val); val 676 arch/arm/plat-samsung/gpio-samsung.c unsigned long val; val 678 arch/arm/plat-samsung/gpio-samsung.c val = __raw_readl(ourchip->base + 0x04); val 679 arch/arm/plat-samsung/gpio-samsung.c val >>= offset; val 680 arch/arm/plat-samsung/gpio-samsung.c val &= 1; val 682 arch/arm/plat-samsung/gpio-samsung.c return val; val 27 arch/arm/plat-samsung/include/plat/pm-common.h unsigned long val; val 69 arch/arm/plat-samsung/pm-check.c static u32 *s3c_pm_countram(struct resource *res, u32 *val) val 79 arch/arm/plat-samsung/pm-check.c *val += size * sizeof(u32); val 80 arch/arm/plat-samsung/pm-check.c return val; val 104 arch/arm/plat-samsung/pm-check.c static u32 *s3c_pm_makecheck(struct resource *res, u32 *val) val 115 arch/arm/plat-samsung/pm-check.c *val = crc32_le(~0, phys_to_virt(addr), left); val 116 arch/arm/plat-samsung/pm-check.c val++; val 119 arch/arm/plat-samsung/pm-check.c return val; val 161 arch/arm/plat-samsung/pm-check.c static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) val 193 arch/arm/plat-samsung/pm-check.c if (calc != *val) { val 195 arch/arm/plat-samsung/pm-check.c "%08lx (%08x vs %08x)\n", addr, calc, *val); val 198 arch/arm/plat-samsung/pm-check.c addr, calc, *val); val 202 arch/arm/plat-samsung/pm-check.c val++; val 205 arch/arm/plat-samsung/pm-check.c return val; val 30 arch/arm/plat-samsung/pm-common.c ptr->val = readl_relaxed(ptr->reg); val 31 arch/arm/plat-samsung/pm-common.c S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); val 50 arch/arm/plat-samsung/pm-common.c ptr->reg, ptr->val, readl_relaxed(ptr->reg)); val 52 arch/arm/plat-samsung/pm-common.c writel_relaxed(ptr->val, ptr->reg); val 70 arch/arm/plat-samsung/pm-common.c writel_relaxed(ptr->val, ptr->reg); val 21 arch/arm/plat-samsung/wakeup-mask.c u32 val; val 23 arch/arm/plat-samsung/wakeup-mask.c val = __raw_readl(reg); val 27 arch/arm/plat-samsung/wakeup-mask.c val |= mask->bit; val 35 arch/arm/plat-samsung/wakeup-mask.c val &= ~mask->bit; val 37 arch/arm/plat-samsung/wakeup-mask.c val |= mask->bit; val 40 arch/arm/plat-samsung/wakeup-mask.c printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); val 41 arch/arm/plat-samsung/wakeup-mask.c __raw_writel(val, reg); val 38 arch/arm/plat-versatile/platsmp.c static void versatile_write_cpu_release(int val) val 40 arch/arm/plat-versatile/platsmp.c versatile_cpu_release = val; val 380 arch/arm/probes/kprobes/core.c unsigned long val, void *data) val 188 arch/arm/probes/kprobes/opt-arm.c unsigned long val; val 254 arch/arm/probes/kprobes/opt-arm.c val = (unsigned long)op; val 255 arch/arm/probes/kprobes/opt-arm.c code[TMPL_VAL_IDX] = val; val 258 arch/arm/probes/kprobes/opt-arm.c val = (unsigned long)optimized_callback; val 259 arch/arm/probes/kprobes/opt-arm.c code[TMPL_CALL_IDX] = val; val 19 arch/arm/probes/kprobes/test-arm.c #define TEST_ARM_TO_THUMB_INTERWORK_R(code1, reg, val, code2) \ val 21 arch/arm/probes/kprobes/test-arm.c TEST_ARG_REG(reg, val) \ val 34 arch/arm/probes/kprobes/test-arm.c #define TEST_ARM_TO_THUMB_INTERWORK_P(code1, reg, val, code2) \ val 36 arch/arm/probes/kprobes/test-arm.c TEST_ARG_PTR(reg, val) \ val 57 arch/arm/probes/kprobes/test-arm.c #define _DATA_PROCESSING_DNM(op,s,val) \ val 58 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "eq" s " r0, r",1, VAL1,", r",2, val, "") \ val 59 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "ne" s " r1, r",1, VAL1,", r",2, val, ", lsl #3") \ val 60 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "cs" s " r2, r",3, VAL1,", r",2, val, ", lsr #4") \ val 61 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "cc" s " r3, r",3, VAL1,", r",2, val, ", asr #5") \ val 62 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "mi" s " r4, r",5, VAL1,", r",2, N(val),", asr #6") \ val 63 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "pl" s " r5, r",5, VAL1,", r",2, val, ", ror #7") \ val 64 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "vs" s " r6, r",7, VAL1,", r",2, val, ", rrx") \ val 69 arch/arm/probes/kprobes/test-arm.c TEST_RRR( op "hi" s " r8, r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\ val 70 arch/arm/probes/kprobes/test-arm.c TEST_RRR( op "ls" s " r9, r",9, VAL1,", r",14,val, ", lsr r",7, 4,"")\ val 71 arch/arm/probes/kprobes/test-arm.c TEST_RRR( op "ge" s " r10, r",11,VAL1,", r",14,val, ", asr r",7, 5,"")\ val 72 arch/arm/probes/kprobes/test-arm.c TEST_RRR( op "lt" s " r11, r",11,VAL1,", r",14,N(val),", asr r",7, 6,"")\ val 73 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "gt" s " r12, r13" ", r",14,val, ", ror r",14,7,"")\ val 74 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "le" s " r14, r",0, val, ", r13" ", lsl r",14,8,"")\ val 80 arch/arm/probes/kprobes/test-arm.c #define DATA_PROCESSING_DNM(op,val) \ val 81 arch/arm/probes/kprobes/test-arm.c _DATA_PROCESSING_DNM(op,"",val) \ val 82 arch/arm/probes/kprobes/test-arm.c _DATA_PROCESSING_DNM(op,"s",val) val 84 arch/arm/probes/kprobes/test-arm.c #define DATA_PROCESSING_NM(op,val) \ val 85 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "ne r",1, VAL1,", r",2, val, "") \ val 86 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "eq r",1, VAL1,", r",2, val, ", lsl #3") \ val 87 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "cc r",3, VAL1,", r",2, val, ", lsr #4") \ val 88 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "cs r",3, VAL1,", r",2, val, ", asr #5") \ val 89 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "pl r",5, VAL1,", r",2, N(val),", asr #6") \ val 90 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "mi r",5, VAL1,", r",2, val, ", ror #7") \ val 91 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "vc r",7, VAL1,", r",2, val, ", rrx") \ val 96 arch/arm/probes/kprobes/test-arm.c TEST_RRR( op "ls r",9, VAL1,", r",14,val, ", lsl r",0, 3,"") \ val 97 arch/arm/probes/kprobes/test-arm.c TEST_RRR( op "hi r",9, VAL1,", r",14,val, ", lsr r",7, 4,"") \ val 98 arch/arm/probes/kprobes/test-arm.c TEST_RRR( op "lt r",11,VAL1,", r",14,val, ", asr r",7, 5,"") \ val 99 arch/arm/probes/kprobes/test-arm.c TEST_RRR( op "ge r",11,VAL1,", r",14,N(val),", asr r",7, 6,"") \ val 100 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "le r13" ", r",14,val, ", ror r",14,7,"") \ val 101 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "gt r",0, val, ", r13" ", lsl r",14,8,"") \ val 106 arch/arm/probes/kprobes/test-arm.c #define _DATA_PROCESSING_DM(op,s,val) \ val 107 arch/arm/probes/kprobes/test-arm.c TEST_R( op "eq" s " r0, r",1, val, "") \ val 108 arch/arm/probes/kprobes/test-arm.c TEST_R( op "ne" s " r1, r",1, val, ", lsl #3") \ val 109 arch/arm/probes/kprobes/test-arm.c TEST_R( op "cs" s " r2, r",3, val, ", lsr #4") \ val 110 arch/arm/probes/kprobes/test-arm.c TEST_R( op "cc" s " r3, r",3, val, ", asr #5") \ val 111 arch/arm/probes/kprobes/test-arm.c TEST_R( op "mi" s " r4, r",5, N(val),", asr #6") \ val 112 arch/arm/probes/kprobes/test-arm.c TEST_R( op "pl" s " r5, r",5, val, ", ror #7") \ val 113 arch/arm/probes/kprobes/test-arm.c TEST_R( op "vs" s " r6, r",10,val, ", rrx") \ val 116 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "vc" s " r8, r",7, val, ", lsl r",0, 3,"") \ val 117 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "hi" s " r9, r",9, val, ", lsr r",7, 4,"") \ val 118 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "ls" s " r10, r",9, val, ", asr r",7, 5,"") \ val 119 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "ge" s " r11, r",11,N(val),", asr r",7, 6,"") \ val 120 arch/arm/probes/kprobes/test-arm.c TEST_RR( op "lt" s " r12, r",11,val, ", ror r",14,7,"") \ val 127 arch/arm/probes/kprobes/test-arm.c #define DATA_PROCESSING_DM(op,val) \ val 128 arch/arm/probes/kprobes/test-arm.c _DATA_PROCESSING_DM(op,"",val) \ val 129 arch/arm/probes/kprobes/test-arm.c _DATA_PROCESSING_DM(op,"s",val) val 1100 arch/arm/probes/kprobes/test-core.c unsigned long val; val 1108 arch/arm/probes/kprobes/test-core.c val = (scenario & 1) ? VALM : ~VALM; val 1110 arch/arm/probes/kprobes/test-core.c current_stack[i] = val + (i << 8); val 1118 arch/arm/probes/kprobes/test-core.c val = (scenario & 2) ? VALR : ~VALR; val 1120 arch/arm/probes/kprobes/test-core.c regs->uregs[i] = val ^ (i << 8); val 1121 arch/arm/probes/kprobes/test-core.c regs->ARM_lr = val ^ (14 << 8); val 1132 arch/arm/probes/kprobes/test-core.c regs->uregs[arg->reg] = arg->val; val 1139 arch/arm/probes/kprobes/test-core.c (unsigned long)current_stack + arg->val; val 1152 arch/arm/probes/kprobes/test-core.c current_stack[arg->index] = arg->val; val 1229 arch/arm/probes/kprobes/test-core.c result_regs.uregs[arg->reg] &= arg->val; val 65 arch/arm/probes/kprobes/test-core.h u32 val; val 72 arch/arm/probes/kprobes/test-core.h u32 val; val 121 arch/arm/probes/kprobes/test-core.h #define TEST_ARG_REG(reg, val) \ val 125 arch/arm/probes/kprobes/test-core.h ".word "#val" \n\t" val 127 arch/arm/probes/kprobes/test-core.h #define TEST_ARG_PTR(reg, val) \ val 131 arch/arm/probes/kprobes/test-core.h ".word "#val" \n\t" val 133 arch/arm/probes/kprobes/test-core.h #define TEST_ARG_MEM(index, val) \ val 137 arch/arm/probes/kprobes/test-core.h ".word "#val" \n\t" val 139 arch/arm/probes/kprobes/test-core.h #define TEST_ARG_REG_MASKED(reg, val) \ val 143 arch/arm/probes/kprobes/test-core.h ".word "#val" \n\t" val 231 arch/arm/probes/kprobes/test-core.h #define TEST_R(code1, reg, val, code2) \ val 233 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ val 334 arch/arm/probes/kprobes/test-core.h #define TEST_BF_R(code1, reg, val, code2) \ val 336 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ val 341 arch/arm/probes/kprobes/test-core.h #define TEST_BB_R(code1, reg, val, code2) \ val 343 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ val 368 arch/arm/probes/kprobes/test-core.h #define TEST_BF_RX(code1, reg, val, code2, codex) \ val 370 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ val 383 arch/arm/probes/kprobes/test-core.h #define TEST_RX(code1, reg, val, code2, codex) \ val 385 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ val 439 arch/arm/probes/kprobes/test-core.h #define N(val) (val ^ 0xffffffff) val 41 arch/arm/probes/kprobes/test-thumb.c #define TEST_THUMB_TO_ARM_INTERWORK_P(code1, reg, val, code2) \ val 43 arch/arm/probes/kprobes/test-thumb.c TEST_ARG_PTR(reg, val) \ val 91 arch/arm/probes/kprobes/test-thumb.c #define DATA_PROCESSING16(op,val) \ val 92 arch/arm/probes/kprobes/test-thumb.c TEST_RR( op" r",0,VAL1,", r",7,val,"") \ val 93 arch/arm/probes/kprobes/test-thumb.c TEST_RR( op" r",7,VAL2,", r",0,val,"") val 478 arch/arm/probes/kprobes/test-thumb.c #define _DATA_PROCESSING32_DNM(op,s,val) \ val 479 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op s".w r0, r",1, VAL1,", r",2, val, "") \ val 480 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op s" r1, r",1, VAL1,", r",2, val, ", lsl #3") \ val 481 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op s" r2, r",3, VAL1,", r",2, val, ", lsr #4") \ val 482 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op s" r3, r",3, VAL1,", r",2, val, ", asr #5") \ val 483 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op s" r4, r",5, VAL1,", r",2, N(val),", asr #6") \ val 484 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op s" r5, r",5, VAL1,", r",2, val, ", ror #7") \ val 485 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op s" r8, r",9, VAL1,", r",10,val, ", rrx") \ val 490 arch/arm/probes/kprobes/test-thumb.c #define DATA_PROCESSING32_DNM(op,val) \ val 491 arch/arm/probes/kprobes/test-thumb.c _DATA_PROCESSING32_DNM(op,"",val) \ val 492 arch/arm/probes/kprobes/test-thumb.c _DATA_PROCESSING32_DNM(op,"s",val) val 494 arch/arm/probes/kprobes/test-thumb.c #define DATA_PROCESSING32_NM(op,val) \ val 495 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op".w r",1, VAL1,", r",2, val, "") \ val 496 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op" r",1, VAL1,", r",2, val, ", lsl #3") \ val 497 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op" r",3, VAL1,", r",2, val, ", lsr #4") \ val 498 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op" r",3, VAL1,", r",2, val, ", asr #5") \ val 499 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op" r",5, VAL1,", r",2, N(val),", asr #6") \ val 500 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op" r",5, VAL1,", r",2, val, ", ror #7") \ val 501 arch/arm/probes/kprobes/test-thumb.c TEST_RR(op" r",9, VAL1,", r",10,val, ", rrx") \ val 506 arch/arm/probes/kprobes/test-thumb.c #define _DATA_PROCESSING32_DM(op,s,val) \ val 507 arch/arm/probes/kprobes/test-thumb.c TEST_R( op s".w r0, r",14, val, "") \ val 508 arch/arm/probes/kprobes/test-thumb.c TEST_R( op s" r1, r",12, val, ", lsl #3") \ val 509 arch/arm/probes/kprobes/test-thumb.c TEST_R( op s" r2, r",11, val, ", lsr #4") \ val 510 arch/arm/probes/kprobes/test-thumb.c TEST_R( op s" r3, r",10, val, ", asr #5") \ val 511 arch/arm/probes/kprobes/test-thumb.c TEST_R( op s" r4, r",9, N(val),", asr #6") \ val 512 arch/arm/probes/kprobes/test-thumb.c TEST_R( op s" r5, r",8, val, ", ror #7") \ val 513 arch/arm/probes/kprobes/test-thumb.c TEST_R( op s" r8, r",7,val, ", rrx") \ val 519 arch/arm/probes/kprobes/test-thumb.c #define DATA_PROCESSING32_DM(op,val) \ val 520 arch/arm/probes/kprobes/test-thumb.c _DATA_PROCESSING32_DM(op,"",val) \ val 521 arch/arm/probes/kprobes/test-thumb.c _DATA_PROCESSING32_DM(op,"s",val) val 179 arch/arm/probes/uprobes/core.c unsigned long val, void *data) val 111 arch/arm/vdso/vdsomunge.c static void write_elf_word(Elf32_Word val, Elf32_Word *dst, bool swap) val 113 arch/arm/vdso/vdsomunge.c *dst = swap ? swab32(val) : val; val 9 arch/arm/vfp/vfp.h static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift) val 13 arch/arm/vfp/vfp.h val = val >> shift | ((val << (32 - shift)) != 0); val 15 arch/arm/vfp/vfp.h val = val != 0; val 17 arch/arm/vfp/vfp.h return val; val 20 arch/arm/vfp/vfp.h static inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift) val 24 arch/arm/vfp/vfp.h val = val >> shift | ((val << (64 - shift)) != 0); val 26 arch/arm/vfp/vfp.h val = val != 0; val 28 arch/arm/vfp/vfp.h return val; val 31 arch/arm/vfp/vfp.h static inline u32 vfp_hi64to32jamming(u64 val) val 39 arch/arm/vfp/vfp.h : "=r" (v) : "r" (val) : "cc"); val 156 arch/arm/vfp/vfp.h asmlinkage void vfp_put_float(s32 val, unsigned int reg); val 188 arch/arm/vfp/vfp.h static inline void vfp_single_unpack(struct vfp_single *s, s32 val) val 192 arch/arm/vfp/vfp.h s->sign = vfp_single_packed_sign(val) >> 16, val 193 arch/arm/vfp/vfp.h s->exponent = vfp_single_packed_exponent(val); val 195 arch/arm/vfp/vfp.h significand = (u32) val; val 208 arch/arm/vfp/vfp.h u32 val; val 209 arch/arm/vfp/vfp.h val = (s->sign << 16) + val 212 arch/arm/vfp/vfp.h return (s32)val; val 271 arch/arm/vfp/vfp.h asmlinkage void vfp_put_double(u64 val, unsigned int reg); val 297 arch/arm/vfp/vfp.h static inline void vfp_double_unpack(struct vfp_double *s, s64 val) val 301 arch/arm/vfp/vfp.h s->sign = vfp_double_packed_sign(val) >> 48; val 302 arch/arm/vfp/vfp.h s->exponent = vfp_double_packed_exponent(val); val 304 arch/arm/vfp/vfp.h significand = (u64) val; val 317 arch/arm/vfp/vfp.h u64 val; val 318 arch/arm/vfp/vfp.h val = ((u64)s->sign << 48) + val 321 arch/arm/vfp/vfp.h return (s64)val; val 69 arch/arm64/include/asm/arch_gicv3.h static inline void gic_write_ctlr(u32 val) val 71 arch/arm64/include/asm/arch_gicv3.h write_sysreg_s(val, SYS_ICC_CTLR_EL1); val 80 arch/arm64/include/asm/arch_gicv3.h static inline void gic_write_grpen1(u32 val) val 82 arch/arm64/include/asm/arch_gicv3.h write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1); val 86 arch/arm64/include/asm/arch_gicv3.h static inline void gic_write_sgi1r(u64 val) val 88 arch/arm64/include/asm/arch_gicv3.h write_sysreg_s(val, SYS_ICC_SGI1R_EL1); val 96 arch/arm64/include/asm/arch_gicv3.h static inline void gic_write_sre(u32 val) val 98 arch/arm64/include/asm/arch_gicv3.h write_sysreg_s(val, SYS_ICC_SRE_EL1); val 102 arch/arm64/include/asm/arch_gicv3.h static inline void gic_write_bpr1(u32 val) val 104 arch/arm64/include/asm/arch_gicv3.h write_sysreg_s(val, SYS_ICC_BPR1_EL1); val 112 arch/arm64/include/asm/arch_gicv3.h static inline void gic_write_pmr(u32 val) val 114 arch/arm64/include/asm/arch_gicv3.h write_sysreg_s(val, SYS_ICC_PMR_EL1); val 104 arch/arm64/include/asm/arch_timer.h void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) val 109 arch/arm64/include/asm/arch_timer.h write_sysreg(val, cntp_ctl_el0); val 112 arch/arm64/include/asm/arch_timer.h write_sysreg(val, cntp_tval_el0); val 118 arch/arm64/include/asm/arch_timer.h write_sysreg(val, cntv_ctl_el0); val 121 arch/arm64/include/asm/arch_timer.h write_sysreg(val, cntv_tval_el0); val 176 arch/arm64/include/asm/arch_timer.h #define arch_counter_enforce_ordering(val) do { \ val 177 arch/arm64/include/asm/arch_timer.h u64 tmp, _val = (val); \ val 38 arch/arm64/include/asm/arm_dsu_pmu.h static inline void __dsu_pmu_write_pmcr(u32 val) val 40 arch/arm64/include/asm/arm_dsu_pmu.h write_sysreg_s(val, CLUSTERPMCR_EL1); val 46 arch/arm64/include/asm/arm_dsu_pmu.h u32 val = read_sysreg_s(CLUSTERPMOVSCLR_EL1); val 48 arch/arm64/include/asm/arm_dsu_pmu.h write_sysreg_s(val, CLUSTERPMOVSCLR_EL1); val 50 arch/arm64/include/asm/arm_dsu_pmu.h return val; val 65 arch/arm64/include/asm/arm_dsu_pmu.h static inline void __dsu_pmu_write_counter(int counter, u64 val) val 68 arch/arm64/include/asm/arm_dsu_pmu.h write_sysreg_s(val, CLUSTERPMXEVCNTR_EL1); val 84 arch/arm64/include/asm/arm_dsu_pmu.h static inline void __dsu_pmu_write_pmccntr(u64 val) val 86 arch/arm64/include/asm/arm_dsu_pmu.h write_sysreg_s(val, CLUSTERPMCCNTR_EL1); val 509 arch/arm64/include/asm/assembler.h .macro mov_q, reg, val val 83 arch/arm64/include/asm/atomic_ll_sc.h int val, result; \ val 93 arch/arm64/include/asm/atomic_ll_sc.h : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \ val 181 arch/arm64/include/asm/atomic_ll_sc.h s64 result, val; \ val 192 arch/arm64/include/asm/atomic_ll_sc.h : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \ val 234 arch/arm64/include/asm/cmpxchg.h unsigned long val) \ val 247 arch/arm64/include/asm/cmpxchg.h : [val] "r" (val)); \ val 259 arch/arm64/include/asm/cmpxchg.h unsigned long val, \ val 264 arch/arm64/include/asm/cmpxchg.h return __cmpwait_case##sfx##_8(ptr, (u8)val); \ val 266 arch/arm64/include/asm/cmpxchg.h return __cmpwait_case##sfx##_16(ptr, (u16)val); \ val 268 arch/arm64/include/asm/cmpxchg.h return __cmpwait_case##sfx##_32(ptr, val); \ val 270 arch/arm64/include/asm/cmpxchg.h return __cmpwait_case##sfx##_64(ptr, val); \ val 282 arch/arm64/include/asm/cmpxchg.h #define __cmpwait_relaxed(ptr, val) \ val 283 arch/arm64/include/asm/cmpxchg.h __cmpwait((ptr), (unsigned long)(val), sizeof(*(ptr))) val 474 arch/arm64/include/asm/cpufeature.h static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val) val 476 arch/arm64/include/asm/cpufeature.h return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign); val 487 arch/arm64/include/asm/cpufeature.h u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT); val 489 arch/arm64/include/asm/cpufeature.h return val == ID_AA64PFR0_EL0_32BIT_64BIT; val 494 arch/arm64/include/asm/cpufeature.h u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT); val 496 arch/arm64/include/asm/cpufeature.h return val > 0; val 517 arch/arm64/include/asm/cpufeature.h u32 val; val 520 arch/arm64/include/asm/cpufeature.h val = cpuid_feature_extract_unsigned_field(mmfr0, val 523 arch/arm64/include/asm/cpufeature.h return val == ID_AA64MMFR0_TGRAN4_SUPPORTED; val 529 arch/arm64/include/asm/cpufeature.h u32 val; val 532 arch/arm64/include/asm/cpufeature.h val = cpuid_feature_extract_unsigned_field(mmfr0, val 535 arch/arm64/include/asm/cpufeature.h return val == ID_AA64MMFR0_TGRAN64_SUPPORTED; val 541 arch/arm64/include/asm/cpufeature.h u32 val; val 544 arch/arm64/include/asm/cpufeature.h val = cpuid_feature_extract_unsigned_field(mmfr0, val 547 arch/arm64/include/asm/cpufeature.h return val == ID_AA64MMFR0_TGRAN16_SUPPORTED; val 558 arch/arm64/include/asm/cpufeature.h u32 val; val 561 arch/arm64/include/asm/cpufeature.h val = cpuid_feature_extract_unsigned_field(mmfr0, val 564 arch/arm64/include/asm/cpufeature.h return val == 0x1; val 92 arch/arm64/include/asm/futex.h u32 val, tmp; val 119 arch/arm64/include/asm/futex.h : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp), "+r" (loops) val 125 arch/arm64/include/asm/futex.h *uval = val; val 35 arch/arm64/include/asm/hw_breakpoint.h u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) | val 39 arch/arm64/include/asm/hw_breakpoint.h val |= DBG_HMC_HYP; val 41 arch/arm64/include/asm/hw_breakpoint.h return val; val 120 arch/arm64/include/asm/hw_breakpoint.h unsigned long val, void *data); val 259 arch/arm64/include/asm/insn.h #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ val 262 arch/arm64/include/asm/insn.h BUILD_BUG_ON(~(mask) & (val)); \ val 263 arch/arm64/include/asm/insn.h return (code & (mask)) == (val); \ val 267 arch/arm64/include/asm/insn.h return (val); \ val 25 arch/arm64/include/asm/io.h static inline void __raw_writeb(u8 val, volatile void __iomem *addr) val 27 arch/arm64/include/asm/io.h asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); val 31 arch/arm64/include/asm/io.h static inline void __raw_writew(u16 val, volatile void __iomem *addr) val 33 arch/arm64/include/asm/io.h asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); val 37 arch/arm64/include/asm/io.h static inline void __raw_writel(u32 val, volatile void __iomem *addr) val 39 arch/arm64/include/asm/io.h asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); val 43 arch/arm64/include/asm/io.h static inline void __raw_writeq(u64 val, volatile void __iomem *addr) val 45 arch/arm64/include/asm/io.h asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); val 51 arch/arm64/include/asm/io.h u8 val; val 55 arch/arm64/include/asm/io.h : "=r" (val) : "r" (addr)); val 56 arch/arm64/include/asm/io.h return val; val 62 arch/arm64/include/asm/io.h u16 val; val 67 arch/arm64/include/asm/io.h : "=r" (val) : "r" (addr)); val 68 arch/arm64/include/asm/io.h return val; val 74 arch/arm64/include/asm/io.h u32 val; val 78 arch/arm64/include/asm/io.h : "=r" (val) : "r" (addr)); val 79 arch/arm64/include/asm/io.h return val; val 85 arch/arm64/include/asm/io.h u64 val; val 89 arch/arm64/include/asm/io.h : "=r" (val) : "r" (addr)); val 90 arch/arm64/include/asm/io.h return val; val 48 arch/arm64/include/asm/kprobes.h unsigned long val, void *data); val 46 arch/arm64/include/asm/kvm_asm.h void *val = &sym; \ val 48 arch/arm64/include/asm/kvm_asm.h val = lm_alias(&sym); \ val 49 arch/arm64/include/asm/kvm_asm.h val; \ val 171 arch/arm64/include/asm/kvm_emulate.h unsigned long val) val 174 arch/arm64/include/asm/kvm_emulate.h vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val; val 389 arch/arm64/include/asm/kvm_host.h void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); val 33 arch/arm64/include/asm/module.h void *loc, u64 val); val 46 arch/arm64/include/asm/percpu.h static inline void __percpu_write_##sz(void *ptr, unsigned long val) \ val 48 arch/arm64/include/asm/percpu.h WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \ val 53 arch/arm64/include/asm/percpu.h __percpu_##name##_case_##sz(void *ptr, unsigned long val) \ val 69 arch/arm64/include/asm/percpu.h : [val] "r" ((u##sz)(val))); \ val 74 arch/arm64/include/asm/percpu.h __percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \ val 91 arch/arm64/include/asm/percpu.h : [val] "r" ((u##sz)(val))); \ val 165 arch/arm64/include/asm/percpu.h #define this_cpu_write_1(pcp, val) \ val 166 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_write_8, pcp, (unsigned long)val) val 167 arch/arm64/include/asm/percpu.h #define this_cpu_write_2(pcp, val) \ val 168 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_write_16, pcp, (unsigned long)val) val 169 arch/arm64/include/asm/percpu.h #define this_cpu_write_4(pcp, val) \ val 170 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_write_32, pcp, (unsigned long)val) val 171 arch/arm64/include/asm/percpu.h #define this_cpu_write_8(pcp, val) \ val 172 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_write_64, pcp, (unsigned long)val) val 174 arch/arm64/include/asm/percpu.h #define this_cpu_add_1(pcp, val) \ val 175 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_add_case_8, pcp, val) val 176 arch/arm64/include/asm/percpu.h #define this_cpu_add_2(pcp, val) \ val 177 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_add_case_16, pcp, val) val 178 arch/arm64/include/asm/percpu.h #define this_cpu_add_4(pcp, val) \ val 179 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_add_case_32, pcp, val) val 180 arch/arm64/include/asm/percpu.h #define this_cpu_add_8(pcp, val) \ val 181 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_add_case_64, pcp, val) val 183 arch/arm64/include/asm/percpu.h #define this_cpu_add_return_1(pcp, val) \ val 184 arch/arm64/include/asm/percpu.h _pcp_protect_return(__percpu_add_return_case_8, pcp, val) val 185 arch/arm64/include/asm/percpu.h #define this_cpu_add_return_2(pcp, val) \ val 186 arch/arm64/include/asm/percpu.h _pcp_protect_return(__percpu_add_return_case_16, pcp, val) val 187 arch/arm64/include/asm/percpu.h #define this_cpu_add_return_4(pcp, val) \ val 188 arch/arm64/include/asm/percpu.h _pcp_protect_return(__percpu_add_return_case_32, pcp, val) val 189 arch/arm64/include/asm/percpu.h #define this_cpu_add_return_8(pcp, val) \ val 190 arch/arm64/include/asm/percpu.h _pcp_protect_return(__percpu_add_return_case_64, pcp, val) val 192 arch/arm64/include/asm/percpu.h #define this_cpu_and_1(pcp, val) \ val 193 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_andnot_case_8, pcp, ~val) val 194 arch/arm64/include/asm/percpu.h #define this_cpu_and_2(pcp, val) \ val 195 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_andnot_case_16, pcp, ~val) val 196 arch/arm64/include/asm/percpu.h #define this_cpu_and_4(pcp, val) \ val 197 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_andnot_case_32, pcp, ~val) val 198 arch/arm64/include/asm/percpu.h #define this_cpu_and_8(pcp, val) \ val 199 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_andnot_case_64, pcp, ~val) val 201 arch/arm64/include/asm/percpu.h #define this_cpu_or_1(pcp, val) \ val 202 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_or_case_8, pcp, val) val 203 arch/arm64/include/asm/percpu.h #define this_cpu_or_2(pcp, val) \ val 204 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_or_case_16, pcp, val) val 205 arch/arm64/include/asm/percpu.h #define this_cpu_or_4(pcp, val) \ val 206 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_or_case_32, pcp, val) val 207 arch/arm64/include/asm/percpu.h #define this_cpu_or_8(pcp, val) \ val 208 arch/arm64/include/asm/percpu.h _pcp_protect(__percpu_or_case_64, pcp, val) val 210 arch/arm64/include/asm/percpu.h #define this_cpu_xchg_1(pcp, val) \ val 211 arch/arm64/include/asm/percpu.h _pcp_protect_return(xchg_relaxed, pcp, val) val 212 arch/arm64/include/asm/percpu.h #define this_cpu_xchg_2(pcp, val) \ val 213 arch/arm64/include/asm/percpu.h _pcp_protect_return(xchg_relaxed, pcp, val) val 214 arch/arm64/include/asm/percpu.h #define this_cpu_xchg_4(pcp, val) \ val 215 arch/arm64/include/asm/percpu.h _pcp_protect_return(xchg_relaxed, pcp, val) val 216 arch/arm64/include/asm/percpu.h #define this_cpu_xchg_8(pcp, val) \ val 217 arch/arm64/include/asm/percpu.h _pcp_protect_return(xchg_relaxed, pcp, val) val 38 arch/arm64/include/asm/pgtable.h extern void __pte_error(const char *file, int line, unsigned long val); val 39 arch/arm64/include/asm/pgtable.h extern void __pmd_error(const char *file, int line, unsigned long val); val 40 arch/arm64/include/asm/pgtable.h extern void __pud_error(const char *file, int line, unsigned long val); val 41 arch/arm64/include/asm/pgtable.h extern void __pgd_error(const char *file, int line, unsigned long val); val 826 arch/arm64/include/asm/pgtable.h #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) val 827 arch/arm64/include/asm/pgtable.h #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) val 831 arch/arm64/include/asm/pgtable.h #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) val 44 arch/arm64/include/asm/preempt.h static inline void __preempt_count_add(int val) val 47 arch/arm64/include/asm/preempt.h pc += val; val 51 arch/arm64/include/asm/preempt.h static inline void __preempt_count_sub(int val) val 54 arch/arm64/include/asm/preempt.h pc -= val; val 249 arch/arm64/include/asm/ptrace.h u64 val = 0; val 256 arch/arm64/include/asm/ptrace.h val = regs->regs[offset]; val 259 arch/arm64/include/asm/ptrace.h val = regs->sp; val 262 arch/arm64/include/asm/ptrace.h val = regs->pc; val 265 arch/arm64/include/asm/ptrace.h val = regs->pstate; val 268 arch/arm64/include/asm/ptrace.h val = 0; val 271 arch/arm64/include/asm/ptrace.h return val; val 288 arch/arm64/include/asm/ptrace.h unsigned long val) val 291 arch/arm64/include/asm/ptrace.h regs->regs[r] = val; val 341 arch/arm64/include/asm/ptrace.h unsigned long val) val 343 arch/arm64/include/asm/ptrace.h regs->pc = val; val 354 arch/arm64/include/asm/ptrace.h unsigned long val) val 356 arch/arm64/include/asm/ptrace.h procedure_link_pointer(regs) = val; val 123 arch/arm64/include/asm/smp.h static inline void update_cpu_boot_status(int val) val 125 arch/arm64/include/asm/smp.h WRITE_ONCE(secondary_data.status, val); val 48 arch/arm64/include/asm/syscall.h int error, long val) val 50 arch/arm64/include/asm/syscall.h regs->regs[0] = (long) error ? error : val; val 20 arch/arm64/include/asm/xen/events.h #define xchg_xen_ulong(ptr, val) xchg((ptr), (val)) val 383 arch/arm64/kernel/cpu_errata.c s32 val; val 427 arch/arm64/kernel/cpu_errata.c val = (s32)res.a0; val 429 arch/arm64/kernel/cpu_errata.c switch (val) { val 514 arch/arm64/kernel/cpufeature.c u64 val = 0; val 528 arch/arm64/kernel/cpufeature.c val = arm64_ftr_set_value(ftrp, val, ftr_new); val 541 arch/arm64/kernel/cpufeature.c val &= valid_mask; val 543 arch/arm64/kernel/cpufeature.c reg->sys_val = val; val 647 arch/arm64/kernel/cpufeature.c static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) val 652 arch/arm64/kernel/cpufeature.c update_cpu_ftr_reg(regp, val); val 653 arch/arm64/kernel/cpufeature.c if ((boot & regp->strict_mask) == (val & regp->strict_mask)) val 656 arch/arm64/kernel/cpufeature.c regp->name, boot, cpu, val); val 862 arch/arm64/kernel/cpufeature.c int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); val 864 arch/arm64/kernel/cpufeature.c return val >= entry->min_field_value; val 870 arch/arm64/kernel/cpufeature.c u64 val; val 874 arch/arm64/kernel/cpufeature.c val = read_sanitised_ftr_reg(entry->sys_reg); val 876 arch/arm64/kernel/cpufeature.c val = __read_sysreg_by_encoding(entry->sys_reg); val 878 arch/arm64/kernel/cpufeature.c return feature_matches(val, entry); val 1173 arch/arm64/kernel/cpufeature.c u64 val = read_sysreg_s(SYS_CLIDR_EL1); val 1176 arch/arm64/kernel/cpufeature.c WARN_ON(val & (7 << 27 | 7 << 21)); val 2186 arch/arm64/kernel/cpufeature.c u64 val; val 2188 arch/arm64/kernel/cpufeature.c rc = emulate_sys_reg(sys_reg, &val); val 2190 arch/arm64/kernel/cpufeature.c pt_regs_write_reg(regs, rt, val); val 107 arch/arm64/kernel/hw_breakpoint.c u64 val = 0; val 110 arch/arm64/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); val 111 arch/arm64/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); val 112 arch/arm64/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val); val 113 arch/arm64/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val); val 118 arch/arm64/kernel/hw_breakpoint.c return val; val 122 arch/arm64/kernel/hw_breakpoint.c static void write_wb_reg(int reg, int n, u64 val) val 125 arch/arm64/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); val 126 arch/arm64/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); val 127 arch/arm64/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val); val 128 arch/arm64/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val); val 625 arch/arm64/kernel/hw_breakpoint.c u64 addr, val; val 643 arch/arm64/kernel/hw_breakpoint.c val = read_wb_reg(AARCH64_DBG_REG_BVR, i); val 644 arch/arm64/kernel/hw_breakpoint.c if (val != (addr & ~0x3)) val 712 arch/arm64/kernel/hw_breakpoint.c static u64 get_distance_from_watchpoint(unsigned long addr, u64 val, val 723 arch/arm64/kernel/hw_breakpoint.c wp_low = val + lens; val 724 arch/arm64/kernel/hw_breakpoint.c wp_high = val + lene; val 739 arch/arm64/kernel/hw_breakpoint.c u64 val; val 768 arch/arm64/kernel/hw_breakpoint.c val = read_wb_reg(AARCH64_DBG_REG_WVR, i); val 771 arch/arm64/kernel/hw_breakpoint.c dist = get_distance_from_watchpoint(addr, val, &ctrl); val 1020 arch/arm64/kernel/hw_breakpoint.c unsigned long val, void *data) val 110 arch/arm64/kernel/insn.c __le32 val; val 112 arch/arm64/kernel/insn.c ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE); val 114 arch/arm64/kernel/insn.c *insnp = le32_to_cpu(val); val 1497 arch/arm64/kernel/insn.c static bool range_of_ones(u64 val) val 1500 arch/arm64/kernel/insn.c u64 sval = val >> __ffs64(val); val 80 arch/arm64/kernel/module-plts.c u64 val = sym->st_value + rela->r_addend; val 85 arch/arm64/kernel/module-plts.c plt[i] = get_plt_entry(val, &plt[i]); val 104 arch/arm64/kernel/module-plts.c void *loc, u64 val) val 126 arch/arm64/kernel/module-plts.c plt[i] = __get_adrp_add_pair(val, (u64)&plt[i], rd); val 71 arch/arm64/kernel/module.c static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val) val 75 arch/arm64/kernel/module.c return val; val 77 arch/arm64/kernel/module.c return val - (u64)place; val 79 arch/arm64/kernel/module.c return (val & ~0xfff) - ((u64)place & ~0xfff); val 88 arch/arm64/kernel/module.c static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len) val 90 arch/arm64/kernel/module.c s64 sval = do_reloc(op, place, val); val 152 arch/arm64/kernel/module.c static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val, val 159 arch/arm64/kernel/module.c sval = do_reloc(op, place, val); val 193 arch/arm64/kernel/module.c static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val, val 201 arch/arm64/kernel/module.c sval = do_reloc(op, place, val); val 229 arch/arm64/kernel/module.c __le32 *place, u64 val) val 234 arch/arm64/kernel/module.c return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21, val 238 arch/arm64/kernel/module.c if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21, val 244 arch/arm64/kernel/module.c val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff); val 245 arch/arm64/kernel/module.c if (!val) val 247 arch/arm64/kernel/module.c insn = aarch64_insn_gen_branch_imm((u64)place, val, val 266 arch/arm64/kernel/module.c u64 val; val 279 arch/arm64/kernel/module.c val = sym->st_value + rel[i].r_addend; val 295 arch/arm64/kernel/module.c ovf = reloc_data(RELOC_OP_ABS, loc, val, 64); val 298 arch/arm64/kernel/module.c ovf = reloc_data(RELOC_OP_ABS, loc, val, 32); val 301 arch/arm64/kernel/module.c ovf = reloc_data(RELOC_OP_ABS, loc, val, 16); val 305 arch/arm64/kernel/module.c ovf = reloc_data(RELOC_OP_PREL, loc, val, 64); val 308 arch/arm64/kernel/module.c ovf = reloc_data(RELOC_OP_PREL, loc, val, 32); val 311 arch/arm64/kernel/module.c ovf = reloc_data(RELOC_OP_PREL, loc, val, 16); val 319 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, val 326 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, val 333 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, val 339 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48, val 343 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, val 347 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, val 351 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, val 356 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, val 360 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, val 365 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, val 369 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, val 374 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, val 378 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, val 384 arch/arm64/kernel/module.c ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48, val 390 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, val 394 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21, val 401 arch/arm64/kernel/module.c ovf = reloc_insn_adrp(me, sechdrs, loc, val); val 408 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12, val 413 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11, val 418 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10, val 423 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9, val 428 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8, val 432 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14, val 436 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, val 441 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26, val 446 arch/arm64/kernel/module.c val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym); val 447 arch/arm64/kernel/module.c if (!val) val 449 arch/arm64/kernel/module.c ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, val 469 arch/arm64/kernel/module.c me->name, (int)ELF64_R_TYPE(rel[i].r_info), val); val 38 arch/arm64/kernel/pci.c unsigned int devfn, int reg, int len, u32 *val) val 44 arch/arm64/kernel/pci.c return b->ops->read(b, devfn, reg, len, val); val 48 arch/arm64/kernel/pci.c unsigned int devfn, int reg, int len, u32 val) val 54 arch/arm64/kernel/pci.c return b->ops->write(b, devfn, reg, len, val); val 377 arch/arm64/kernel/perf_event.c static inline void armv8pmu_pmcr_write(u32 val) val 379 arch/arm64/kernel/perf_event.c val &= ARMV8_PMU_PMCR_MASK; val 381 arch/arm64/kernel/perf_event.c write_sysreg(val, pmcr_el0); val 416 arch/arm64/kernel/perf_event.c u64 val = 0; val 418 arch/arm64/kernel/perf_event.c val = armv8pmu_read_evcntr(idx); val 420 arch/arm64/kernel/perf_event.c val = (val << 32) | armv8pmu_read_evcntr(idx - 1); val 421 arch/arm64/kernel/perf_event.c return val; val 484 arch/arm64/kernel/perf_event.c static inline void armv8pmu_write_evtype(int idx, u32 val) val 487 arch/arm64/kernel/perf_event.c val &= ARMV8_PMU_EVTYPE_MASK; val 488 arch/arm64/kernel/perf_event.c write_sysreg(val, pmxevtyper_el0); val 31 arch/arm64/kernel/probes/simulate-insn.c static inline void set_x_reg(struct pt_regs *regs, int reg, u64 val) val 33 arch/arm64/kernel/probes/simulate-insn.c pt_regs_write_reg(regs, reg, val); val 36 arch/arm64/kernel/probes/simulate-insn.c static inline void set_w_reg(struct pt_regs *regs, int reg, u64 val) val 38 arch/arm64/kernel/probes/simulate-insn.c pt_regs_write_reg(regs, reg, lower_32_bits(val)); val 89 arch/arm64/kernel/probes/simulate-insn.c long imm, xn, val; val 95 arch/arm64/kernel/probes/simulate-insn.c val = (imm<<12) + (addr & 0xfffffffffffff000); val 97 arch/arm64/kernel/probes/simulate-insn.c val = imm + addr; val 99 arch/arm64/kernel/probes/simulate-insn.c set_x_reg(regs, xn, val); val 163 arch/arm64/kernel/probes/uprobes.c unsigned long val, void *data) val 1557 arch/arm64/kernel/ptrace.c compat_ulong_t val) val 1572 arch/arm64/kernel/ptrace.c &val); val 14 arch/arm64/kernel/reloc_test_core.c #define __SET_ABS(name, val) asm(".globl " #name "; .set "#name ", " #val) val 15 arch/arm64/kernel/reloc_test_core.c #define SET_ABS(name, val) __SET_ABS(name, val) val 33 arch/arm64/kernel/smp_spin_table.c static void write_pen_release(u64 val) val 38 arch/arm64/kernel/smp_spin_table.c secondary_holding_pen_release = val; val 17 arch/arm64/kernel/ssbd.c u64 val = is_compat_thread(task_thread_info(task)) ? val 20 arch/arm64/kernel/ssbd.c task_pt_regs(task)->pstate |= val; val 25 arch/arm64/kernel/ssbd.c u64 val = is_compat_thread(task_thread_info(task)) ? val 28 arch/arm64/kernel/ssbd.c task_pt_regs(task)->pstate &= ~val; val 69 arch/arm64/kernel/syscall.c u32 reg, val; val 79 arch/arm64/kernel/syscall.c val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE; val 80 arch/arm64/kernel/syscall.c write_sysreg(val, mdscr_el1); val 70 arch/arm64/kernel/traps.c unsigned int val, bad; val 72 arch/arm64/kernel/traps.c bad = aarch64_insn_read(&((u32 *)addr)[i], &val); val 75 arch/arm64/kernel/traps.c p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); val 471 arch/arm64/kernel/traps.c unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); val 475 arch/arm64/kernel/traps.c val &= ~BIT(CTR_DIC_SHIFT); val 478 arch/arm64/kernel/traps.c val &= ~CTR_IMINLINE_MASK; val 479 arch/arm64/kernel/traps.c val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; val 482 arch/arm64/kernel/traps.c pt_regs_write_reg(regs, rt, val); val 663 arch/arm64/kernel/traps.c u64 val = arch_timer_read_counter(); val 665 arch/arm64/kernel/traps.c pt_regs_write_reg(regs, rt, lower_32_bits(val)); val 666 arch/arm64/kernel/traps.c pt_regs_write_reg(regs, rt2, upper_32_bits(val)); val 922 arch/arm64/kernel/traps.c void __pte_error(const char *file, int line, unsigned long val) val 924 arch/arm64/kernel/traps.c pr_err("%s:%d: bad pte %016lx.\n", file, line, val); val 927 arch/arm64/kernel/traps.c void __pmd_error(const char *file, int line, unsigned long val) val 929 arch/arm64/kernel/traps.c pr_err("%s:%d: bad pmd %016lx.\n", file, line, val); val 932 arch/arm64/kernel/traps.c void __pud_error(const char *file, int line, unsigned long val) val 934 arch/arm64/kernel/traps.c pr_err("%s:%d: bad pud %016lx.\n", file, line, val); val 937 arch/arm64/kernel/traps.c void __pgd_error(const char *file, int line, unsigned long val) val 939 arch/arm64/kernel/traps.c pr_err("%s:%d: bad pgd %016lx.\n", file, line, val); val 38 arch/arm64/kvm/debug.c u64 val = vcpu_read_sys_reg(vcpu, MDSCR_EL1); val 40 arch/arm64/kvm/debug.c vcpu->arch.guest_debug_preserved.mdscr_el1 = val; val 48 arch/arm64/kvm/debug.c u64 val = vcpu->arch.guest_debug_preserved.mdscr_el1; val 50 arch/arm64/kvm/debug.c vcpu_write_sys_reg(vcpu, val, MDSCR_EL1); val 535 arch/arm64/kvm/guest.c u64 val; val 538 arch/arm64/kvm/guest.c ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id)); val 542 arch/arm64/kvm/guest.c return kvm_arm_timer_set_reg(vcpu, reg->id, val); val 548 arch/arm64/kvm/guest.c u64 val; val 550 arch/arm64/kvm/guest.c val = kvm_arm_timer_get_reg(vcpu, reg->id); val 551 arch/arm64/kvm/guest.c return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0; val 96 arch/arm64/kvm/hyp/switch.c u64 val; val 98 arch/arm64/kvm/hyp/switch.c val = read_sysreg(cpacr_el1); val 99 arch/arm64/kvm/hyp/switch.c val |= CPACR_EL1_TTA; val 100 arch/arm64/kvm/hyp/switch.c val &= ~CPACR_EL1_ZEN; val 103 arch/arm64/kvm/hyp/switch.c val |= CPACR_EL1_ZEN; val 105 arch/arm64/kvm/hyp/switch.c val &= ~CPACR_EL1_FPEN; val 109 arch/arm64/kvm/hyp/switch.c write_sysreg(val, cpacr_el1); val 117 arch/arm64/kvm/hyp/switch.c u64 val; val 121 arch/arm64/kvm/hyp/switch.c val = CPTR_EL2_DEFAULT; val 122 arch/arm64/kvm/hyp/switch.c val |= CPTR_EL2_TTA | CPTR_EL2_TZ; val 124 arch/arm64/kvm/hyp/switch.c val |= CPTR_EL2_TFP; val 128 arch/arm64/kvm/hyp/switch.c write_sysreg(val, cptr_el2); val 400 arch/arm64/kvm/hyp/switch.c u64 val = vcpu_get_reg(vcpu, rt); val 411 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_SCTLR); val 414 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_TTBR0); val 417 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_TTBR1); val 420 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_TCR); val 423 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_ESR); val 426 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_FAR); val 429 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_AFSR0); val 432 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_AFSR1); val 435 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_MAIR); val 438 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_AMAIR); val 441 arch/arm64/kvm/hyp/switch.c write_sysreg_el1(val, SYS_CONTEXTIDR); val 22 arch/arm64/kvm/hyp/tlb.c u64 val; val 36 arch/arm64/kvm/hyp/tlb.c val = cxt->tcr = read_sysreg_el1(SYS_TCR); val 37 arch/arm64/kvm/hyp/tlb.c val |= TCR_EPD1_MASK | TCR_EPD0_MASK; val 38 arch/arm64/kvm/hyp/tlb.c write_sysreg_el1(val, SYS_TCR); val 39 arch/arm64/kvm/hyp/tlb.c val = cxt->sctlr = read_sysreg_el1(SYS_SCTLR); val 40 arch/arm64/kvm/hyp/tlb.c val |= SCTLR_ELx_M; val 41 arch/arm64/kvm/hyp/tlb.c write_sysreg_el1(val, SYS_SCTLR); val 57 arch/arm64/kvm/hyp/tlb.c val = read_sysreg(hcr_el2); val 58 arch/arm64/kvm/hyp/tlb.c val &= ~HCR_TGE; val 59 arch/arm64/kvm/hyp/tlb.c write_sysreg(val, hcr_el2); val 62 arch/arm64/kvm/pmu.c write_sysreg(val, pmevtyper##idx##_el0); \ val 119 arch/arm64/kvm/pmu.c static void kvm_vcpu_pmu_write_evtype_direct(int idx, u32 val) val 124 arch/arm64/kvm/pmu.c write_sysreg(val, pmccfiltr_el0); val 112 arch/arm64/kvm/sys_regs.c void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) val 126 arch/arm64/kvm/sys_regs.c case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); return; val 127 arch/arm64/kvm/sys_regs.c case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); return; val 128 arch/arm64/kvm/sys_regs.c case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); return; val 129 arch/arm64/kvm/sys_regs.c case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); return; val 130 arch/arm64/kvm/sys_regs.c case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); return; val 131 arch/arm64/kvm/sys_regs.c case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); return; val 132 arch/arm64/kvm/sys_regs.c case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); return; val 133 arch/arm64/kvm/sys_regs.c case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); return; val 134 arch/arm64/kvm/sys_regs.c case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); return; val 135 arch/arm64/kvm/sys_regs.c case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); return; val 136 arch/arm64/kvm/sys_regs.c case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); return; val 137 arch/arm64/kvm/sys_regs.c case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); return; val 138 arch/arm64/kvm/sys_regs.c case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); return; val 139 arch/arm64/kvm/sys_regs.c case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12); return; val 140 arch/arm64/kvm/sys_regs.c case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); return; val 141 arch/arm64/kvm/sys_regs.c case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); return; val 142 arch/arm64/kvm/sys_regs.c case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); return; val 143 arch/arm64/kvm/sys_regs.c case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); return; val 144 arch/arm64/kvm/sys_regs.c case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); return; val 145 arch/arm64/kvm/sys_regs.c case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); return; val 146 arch/arm64/kvm/sys_regs.c case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); return; val 147 arch/arm64/kvm/sys_regs.c case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); return; val 148 arch/arm64/kvm/sys_regs.c case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); return; val 152 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, reg) = val; val 209 arch/arm64/kvm/sys_regs.c u64 val; val 219 arch/arm64/kvm/sys_regs.c val = p->regval; val 221 arch/arm64/kvm/sys_regs.c val = vcpu_read_sys_reg(vcpu, reg); val 223 arch/arm64/kvm/sys_regs.c val = (p->regval << 32) | (u64)lower_32_bits(val); val 225 arch/arm64/kvm/sys_regs.c val = ((u64)upper_32_bits(val) << 32) | val 228 arch/arm64/kvm/sys_regs.c vcpu_write_sys_reg(vcpu, val, reg); val 316 arch/arm64/kvm/sys_regs.c u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); val 320 arch/arm64/kvm/sys_regs.c if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { val 411 arch/arm64/kvm/sys_regs.c u64 val = p->regval; val 414 arch/arm64/kvm/sys_regs.c val &= 0xffffffffUL; val 415 arch/arm64/kvm/sys_regs.c val |= ((*dbg_reg >> 32) << 32); val 418 arch/arm64/kvm/sys_regs.c *dbg_reg = val; val 470 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; val 513 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; val 556 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; val 598 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; val 626 arch/arm64/kvm/sys_regs.c u64 pmcr, val; val 633 arch/arm64/kvm/sys_regs.c val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) val 636 arch/arm64/kvm/sys_regs.c val |= ARMV8_PMU_PMCR_LC; val 637 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, r->reg) = val; val 674 arch/arm64/kvm/sys_regs.c u64 val; val 684 arch/arm64/kvm/sys_regs.c val = __vcpu_sys_reg(vcpu, PMCR_EL0); val 685 arch/arm64/kvm/sys_regs.c val &= ~ARMV8_PMU_PMCR_MASK; val 686 arch/arm64/kvm/sys_regs.c val |= p->regval & ARMV8_PMU_PMCR_MASK; val 688 arch/arm64/kvm/sys_regs.c val |= ARMV8_PMU_PMCR_LC; val 689 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMCR_EL0) = val; val 690 arch/arm64/kvm/sys_regs.c kvm_pmu_handle_pmcr(vcpu, val); val 694 arch/arm64/kvm/sys_regs.c val = __vcpu_sys_reg(vcpu, PMCR_EL0) val 696 arch/arm64/kvm/sys_regs.c p->regval = val; val 746 arch/arm64/kvm/sys_regs.c u64 pmcr, val; val 749 arch/arm64/kvm/sys_regs.c val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; val 750 arch/arm64/kvm/sys_regs.c if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { val 858 arch/arm64/kvm/sys_regs.c u64 val, mask; val 868 arch/arm64/kvm/sys_regs.c val = p->regval & mask; val 871 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; val 872 arch/arm64/kvm/sys_regs.c kvm_pmu_enable_counter_mask(vcpu, val); val 876 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; val 877 arch/arm64/kvm/sys_regs.c kvm_pmu_disable_counter_mask(vcpu, val); val 900 arch/arm64/kvm/sys_regs.c u64 val = p->regval & mask; val 904 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; val 907 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; val 1079 arch/arm64/kvm/sys_regs.c u64 val = raz ? 0 : read_sanitised_ftr_reg(id); val 1082 arch/arm64/kvm/sys_regs.c val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); val 1084 arch/arm64/kvm/sys_regs.c val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | val 1090 arch/arm64/kvm/sys_regs.c return val; val 1121 arch/arm64/kvm/sys_regs.c static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); val 1122 arch/arm64/kvm/sys_regs.c static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); val 1169 arch/arm64/kvm/sys_regs.c u64 val; val 1174 arch/arm64/kvm/sys_regs.c val = guest_id_aa64zfr0_el1(vcpu); val 1175 arch/arm64/kvm/sys_regs.c return reg_to_user(uaddr, &val, reg->id); val 1184 arch/arm64/kvm/sys_regs.c u64 val; val 1189 arch/arm64/kvm/sys_regs.c err = reg_from_user(&val, uaddr, id); val 1194 arch/arm64/kvm/sys_regs.c if (val != guest_id_aa64zfr0_el1(vcpu)) val 1212 arch/arm64/kvm/sys_regs.c const u64 val = read_id_reg(vcpu, rd, raz); val 1214 arch/arm64/kvm/sys_regs.c return reg_to_user(uaddr, &val, id); val 1223 arch/arm64/kvm/sys_regs.c u64 val; val 1225 arch/arm64/kvm/sys_regs.c err = reg_from_user(&val, uaddr, id); val 1230 arch/arm64/kvm/sys_regs.c if (val != read_id_reg(vcpu, rd, raz)) val 1704 arch/arm64/kvm/sys_regs.c u64 val = *dbg_reg; val 1706 arch/arm64/kvm/sys_regs.c val &= 0xffffffffUL; val 1707 arch/arm64/kvm/sys_regs.c val |= p->regval << 32; val 1708 arch/arm64/kvm/sys_regs.c *dbg_reg = val; val 2396 arch/arm64/kvm/sys_regs.c ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ val 2406 arch/arm64/kvm/sys_regs.c ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); val 2418 arch/arm64/kvm/sys_regs.c static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) val 2420 arch/arm64/kvm/sys_regs.c if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) val 2425 arch/arm64/kvm/sys_regs.c static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) val 2427 arch/arm64/kvm/sys_regs.c if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) val 2442 arch/arm64/kvm/sys_regs.c return reg_to_user(uaddr, &r->val, id); val 2450 arch/arm64/kvm/sys_regs.c u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ val 2457 arch/arm64/kvm/sys_regs.c err = reg_from_user(&val, uaddr, id); val 2462 arch/arm64/kvm/sys_regs.c if (r->val != val) val 2468 arch/arm64/kvm/sys_regs.c static bool is_valid_cache(u32 val) val 2472 arch/arm64/kvm/sys_regs.c if (val >= CSSELR_MAX) val 2476 arch/arm64/kvm/sys_regs.c level = (val >> 1); val 2483 arch/arm64/kvm/sys_regs.c return (val & 1); val 2486 arch/arm64/kvm/sys_regs.c return !(val & 1); val 2496 arch/arm64/kvm/sys_regs.c u32 val; val 2508 arch/arm64/kvm/sys_regs.c val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) val 2510 arch/arm64/kvm/sys_regs.c if (!is_valid_cache(val)) val 2513 arch/arm64/kvm/sys_regs.c return put_user(get_ccsidr(val), uval); val 2521 arch/arm64/kvm/sys_regs.c u32 val, newval; val 2533 arch/arm64/kvm/sys_regs.c val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) val 2535 arch/arm64/kvm/sys_regs.c if (!is_valid_cache(val)) val 2542 arch/arm64/kvm/sys_regs.c if (newval != get_ccsidr(val)) val 2613 arch/arm64/kvm/sys_regs.c u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; val 2616 arch/arm64/kvm/sys_regs.c val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; val 2620 arch/arm64/kvm/sys_regs.c if (put_user(val | i, uindices)) val 2777 arch/arm64/kvm/sys_regs.c cache_levels = clidr.val; val 49 arch/arm64/kvm/sys_regs.h u64 val; val 98 arch/arm64/kvm/sys_regs.h __vcpu_sys_reg(vcpu, r->reg) = r->val; val 19 arch/arm64/kvm/vgic-sys-reg-v3.c u64 val; val 23 arch/arm64/kvm/vgic-sys-reg-v3.c val = p->regval; val 29 arch/arm64/kvm/vgic-sys-reg-v3.c host_pri_bits = ((val & ICC_CTLR_EL1_PRI_BITS_MASK) >> val 36 arch/arm64/kvm/vgic-sys-reg-v3.c host_id_bits = (val & ICC_CTLR_EL1_ID_BITS_MASK) >> val 45 arch/arm64/kvm/vgic-sys-reg-v3.c seis = (val & ICC_CTLR_EL1_SEIS_MASK) >> val 52 arch/arm64/kvm/vgic-sys-reg-v3.c a3v = (val & ICC_CTLR_EL1_A3V_MASK) >> ICC_CTLR_EL1_A3V_SHIFT; val 60 arch/arm64/kvm/vgic-sys-reg-v3.c vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT; val 61 arch/arm64/kvm/vgic-sys-reg-v3.c vmcr.eoim = (val & ICC_CTLR_EL1_EOImode_MASK) >> ICC_CTLR_EL1_EOImode_SHIFT; val 64 arch/arm64/kvm/vgic-sys-reg-v3.c val = 0; val 65 arch/arm64/kvm/vgic-sys-reg-v3.c val |= (vgic_v3_cpu->num_pri_bits - 1) << val 67 arch/arm64/kvm/vgic-sys-reg-v3.c val |= vgic_v3_cpu->num_id_bits << ICC_CTLR_EL1_ID_BITS_SHIFT; val 68 arch/arm64/kvm/vgic-sys-reg-v3.c val |= ((kvm_vgic_global_state.ich_vtr_el2 & val 71 arch/arm64/kvm/vgic-sys-reg-v3.c val |= ((kvm_vgic_global_state.ich_vtr_el2 & val 78 arch/arm64/kvm/vgic-sys-reg-v3.c val |= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK; val 79 arch/arm64/kvm/vgic-sys-reg-v3.c val |= (vmcr.eoim << ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK; val 81 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = val; val 90 arch/arm64/mm/dump.c u64 val; val 98 arch/arm64/mm/dump.c .val = PTE_VALID, val 103 arch/arm64/mm/dump.c .val = PTE_USER, val 108 arch/arm64/mm/dump.c .val = PTE_RDONLY, val 113 arch/arm64/mm/dump.c .val = PTE_PXN, val 118 arch/arm64/mm/dump.c .val = PTE_SHARED, val 123 arch/arm64/mm/dump.c .val = PTE_AF, val 128 arch/arm64/mm/dump.c .val = PTE_NG, val 133 arch/arm64/mm/dump.c .val = PTE_CONT, val 138 arch/arm64/mm/dump.c .val = PTE_TABLE_BIT, val 143 arch/arm64/mm/dump.c .val = PTE_UXN, val 147 arch/arm64/mm/dump.c .val = PTE_ATTRINDX(MT_DEVICE_nGnRnE), val 151 arch/arm64/mm/dump.c .val = PTE_ATTRINDX(MT_DEVICE_nGnRE), val 155 arch/arm64/mm/dump.c .val = PTE_ATTRINDX(MT_DEVICE_GRE), val 159 arch/arm64/mm/dump.c .val = PTE_ATTRINDX(MT_NORMAL_NC), val 163 arch/arm64/mm/dump.c .val = PTE_ATTRINDX(MT_NORMAL), val 204 arch/arm64/mm/dump.c if ((st->current_prot & bits->mask) == bits->val) val 244 arch/arm64/mm/dump.c u64 val) val 247 arch/arm64/mm/dump.c u64 prot = val & pg_level[level].mask; val 72 arch/arm64/net/bpf_jit_comp.c const s32 val, struct jit_ctx *ctx) val 74 arch/arm64/net/bpf_jit_comp.c u16 hi = val >> 16; val 75 arch/arm64/net/bpf_jit_comp.c u16 lo = val & 0xffff; val 92 arch/arm64/net/bpf_jit_comp.c static int i64_i16_blocks(const u64 val, bool inverse) val 94 arch/arm64/net/bpf_jit_comp.c return (((val >> 0) & 0xffff) != (inverse ? 0xffff : 0x0000)) + val 95 arch/arm64/net/bpf_jit_comp.c (((val >> 16) & 0xffff) != (inverse ? 0xffff : 0x0000)) + val 96 arch/arm64/net/bpf_jit_comp.c (((val >> 32) & 0xffff) != (inverse ? 0xffff : 0x0000)) + val 97 arch/arm64/net/bpf_jit_comp.c (((val >> 48) & 0xffff) != (inverse ? 0xffff : 0x0000)); val 100 arch/arm64/net/bpf_jit_comp.c static inline void emit_a64_mov_i64(const int reg, const u64 val, val 103 arch/arm64/net/bpf_jit_comp.c u64 nrm_tmp = val, rev_tmp = ~val; val 108 arch/arm64/net/bpf_jit_comp.c return emit_a64_mov_i(0, reg, (u32)val, ctx); val 130 arch/arm64/net/bpf_jit_comp.c static inline void emit_addr_mov_i64(const int reg, const u64 val, val 133 arch/arm64/net/bpf_jit_comp.c u64 tmp = val; val 48 arch/c6x/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 40 arch/c6x/include/asm/syscall.h int error, long val) val 42 arch/c6x/include/asm/syscall.h regs->a4 = error ?: val; val 31 arch/c6x/include/asm/unaligned.h static inline void put_unaligned_le16(u16 val, void *p) val 34 arch/c6x/include/asm/unaligned.h _p[0] = val; val 35 arch/c6x/include/asm/unaligned.h _p[1] = val >> 8; val 38 arch/c6x/include/asm/unaligned.h static inline void put_unaligned_be16(u16 val, void *p) val 41 arch/c6x/include/asm/unaligned.h _p[0] = val >> 8; val 42 arch/c6x/include/asm/unaligned.h _p[1] = val; val 47 arch/c6x/include/asm/unaligned.h u32 val = (u32) p; val 50 arch/c6x/include/asm/unaligned.h : "+a"(val)); val 51 arch/c6x/include/asm/unaligned.h return val; val 54 arch/c6x/include/asm/unaligned.h static inline void put_unaligned32(u32 val, void *p) val 57 arch/c6x/include/asm/unaligned.h : : "a"(val), "b"(p) : "memory"); val 62 arch/c6x/include/asm/unaligned.h u64 val; val 65 arch/c6x/include/asm/unaligned.h : "=a"(val) : "a"(p)); val 66 arch/c6x/include/asm/unaligned.h return val; val 69 arch/c6x/include/asm/unaligned.h static inline void put_unaligned64(u64 val, const void *p) val 72 arch/c6x/include/asm/unaligned.h : : "a"(val), "b"(p) : "memory"); val 125 arch/c6x/include/asm/unaligned.h #define __put_unaligned_le(val, ptr) ({ \ val 129 arch/c6x/include/asm/unaligned.h *(u8 *)__gu_p = (__force u8)(val); \ val 132 arch/c6x/include/asm/unaligned.h put_unaligned_le16((__force u16)(val), __gu_p); \ val 135 arch/c6x/include/asm/unaligned.h put_unaligned_le32((__force u32)(val), __gu_p); \ val 138 arch/c6x/include/asm/unaligned.h put_unaligned_le64((__force u64)(val), __gu_p); \ val 146 arch/c6x/include/asm/unaligned.h #define __put_unaligned_be(val, ptr) ({ \ val 150 arch/c6x/include/asm/unaligned.h *(u8 *)__gu_p = (__force u8)(val); \ val 153 arch/c6x/include/asm/unaligned.h put_unaligned_be16((__force u16)(val), __gu_p); \ val 156 arch/c6x/include/asm/unaligned.h put_unaligned_be32((__force u32)(val), __gu_p); \ val 159 arch/c6x/include/asm/unaligned.h put_unaligned_be64((__force u64)(val), __gu_p); \ val 13 arch/c6x/include/uapi/asm/swab.h static inline __attribute_const__ __u16 __c6x_swab16(__u16 val) val 15 arch/c6x/include/uapi/asm/swab.h asm("swap4 .l1 %0,%0\n" : "+a"(val)); val 16 arch/c6x/include/uapi/asm/swab.h return val; val 19 arch/c6x/include/uapi/asm/swab.h static inline __attribute_const__ __u32 __c6x_swab32(__u32 val) val 23 arch/c6x/include/uapi/asm/swab.h : "+a"(val)); val 24 arch/c6x/include/uapi/asm/swab.h return val; val 27 arch/c6x/include/uapi/asm/swab.h static inline __attribute_const__ __u64 __c6x_swab64(__u64 val) val 33 arch/c6x/include/uapi/asm/swab.h : "+a"(val)); val 34 arch/c6x/include/uapi/asm/swab.h return val; val 37 arch/c6x/include/uapi/asm/swab.h static inline __attribute_const__ __u32 __c6x_swahw32(__u32 val) val 39 arch/c6x/include/uapi/asm/swab.h asm("swap2 .l1 %0,%0\n" : "+a"(val)); val 40 arch/c6x/include/uapi/asm/swab.h return val; val 43 arch/c6x/include/uapi/asm/swab.h static inline __attribute_const__ __u32 __c6x_swahb32(__u32 val) val 45 arch/c6x/include/uapi/asm/swab.h asm("swap4 .l1 %0,%0\n" : "+a"(val)); val 46 arch/c6x/include/uapi/asm/swab.h return val; val 33 arch/c6x/kernel/soc.c int count, i, val; val 41 arch/c6x/kernel/soc.c for (i = 0, val = 0; i < 2; i++) { val 42 arch/c6x/kernel/soc.c val = val << 4; val 43 arch/c6x/kernel/soc.c val |= isdigit(str[i]) ? val 46 arch/c6x/kernel/soc.c cmdline_mac[count] = val; val 129 arch/c6x/platforms/dscr.c static void dscr_write_locked1(u32 reg, u32 val, val 148 arch/c6x/platforms/dscr.c : "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key) val 158 arch/c6x/platforms/dscr.c static void dscr_write_locked2(u32 reg, u32 val, val 164 arch/c6x/platforms/dscr.c soc_writel(val, dscr.base + reg); val 169 arch/c6x/platforms/dscr.c static void dscr_write(u32 reg, u32 val) val 175 arch/c6x/platforms/dscr.c dscr_write_locked1(reg, val, lock->lockreg, lock->key); val 177 arch/c6x/platforms/dscr.c dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0], val 180 arch/c6x/platforms/dscr.c soc_writel(val, dscr.base + reg); val 192 arch/c6x/platforms/dscr.c u32 ctl_val, val; val 227 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + ctl->reg); val 228 arch/c6x/platforms/dscr.c val &= ~ctl_mask; val 229 arch/c6x/platforms/dscr.c val |= ctl_val; val 231 arch/c6x/platforms/dscr.c dscr_write(ctl->reg, val); val 246 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + stat->reg); val 247 arch/c6x/platforms/dscr.c val >>= ctl_shift; val 248 arch/c6x/platforms/dscr.c val &= ((1 << stat->nbits) - 1); val 249 arch/c6x/platforms/dscr.c } while (val != ctl_val); val 260 arch/c6x/platforms/dscr.c u32 val; val 271 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + r->reg); val 273 arch/c6x/platforms/dscr.c dscr_write(r->reg, val | r->mask); val 275 arch/c6x/platforms/dscr.c dscr_write(r->reg, val & ~(r->mask)); val 284 arch/c6x/platforms/dscr.c u32 val; val 287 arch/c6x/platforms/dscr.c err = of_property_read_u32_array(node, "ti,dscr-devstat", &val, 1); val 289 arch/c6x/platforms/dscr.c c6x_devstat = soc_readl(base + val); val 46 arch/c6x/platforms/emif.c u32 val; val 58 arch/c6x/platforms/emif.c err = of_property_read_u32_array(node, "ti,dscr-dev-enable", &val, 1); val 60 arch/c6x/platforms/emif.c dscr_set_devstate(val, DSCR_DEVSTATE_ENABLED); val 72 arch/c6x/platforms/emif.c err = of_property_read_u32_array(node, "ti,emifa-burst-priority", &val, 1); val 74 arch/c6x/platforms/emif.c soc_writel(val, ®s->bprio); val 76 arch/c6x/platforms/emif.c err = of_property_read_u32_array(node, "ti,emifa-async-wait-control", &val, 1); val 78 arch/c6x/platforms/emif.c soc_writel(val, ®s->awcc); val 145 arch/c6x/platforms/megamod-pic.c u32 val; val 156 arch/c6x/platforms/megamod-pic.c val = soc_readl(&pic->regs->intmux[index]); val 157 arch/c6x/platforms/megamod-pic.c val &= ~(0xff << offset); val 158 arch/c6x/platforms/megamod-pic.c val |= src << offset; val 159 arch/c6x/platforms/megamod-pic.c soc_writel(val, &pic->regs->intmux[index]); val 181 arch/c6x/platforms/megamod-pic.c u32 val; val 190 arch/c6x/platforms/megamod-pic.c val = be32_to_cpup(map); val 191 arch/c6x/platforms/megamod-pic.c if (val && val >= 4) val 192 arch/c6x/platforms/megamod-pic.c mapping[i] = val; val 324 arch/c6x/platforms/megamod-pic.c static void assert_event(unsigned int val) val 326 arch/c6x/platforms/megamod-pic.c soc_writel(val, &mm_pic->regs->evtasrt); val 425 arch/c6x/platforms/plldata.c u32 val; val 435 arch/c6x/platforms/plldata.c err = of_property_read_u32(node, "clock-frequency", &val); val 436 arch/c6x/platforms/plldata.c if (err || val == 0) { val 438 arch/c6x/platforms/plldata.c node, (int)val / 1000000); val 439 arch/c6x/platforms/plldata.c val = 25000000; val 441 arch/c6x/platforms/plldata.c clkin1.rate = val; val 443 arch/c6x/platforms/plldata.c err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val); val 445 arch/c6x/platforms/plldata.c val = 5000; val 446 arch/c6x/platforms/plldata.c pll->bypass_delay = val; val 448 arch/c6x/platforms/plldata.c err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val); val 450 arch/c6x/platforms/plldata.c val = 30000; val 451 arch/c6x/platforms/plldata.c pll->reset_delay = val; val 453 arch/c6x/platforms/plldata.c err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val); val 455 arch/c6x/platforms/plldata.c val = 30000; val 456 arch/c6x/platforms/plldata.c pll->lock_delay = val; val 90 arch/c6x/platforms/timer64.c u32 val; val 100 arch/c6x/platforms/timer64.c val = soc_readl(&timer->tcr); val 101 arch/c6x/platforms/timer64.c soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr); val 104 arch/c6x/platforms/timer64.c val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK; val 105 arch/c6x/platforms/timer64.c soc_writel(val, &timer->tgcr); val 106 arch/c6x/platforms/timer64.c soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr); val 179 arch/c6x/platforms/timer64.c u32 val; val 183 arch/c6x/platforms/timer64.c err = of_property_read_u32(np, "ti,core-mask", &val); val 185 arch/c6x/platforms/timer64.c if (val & (1 << get_coreid())) { val 217 arch/c6x/platforms/timer64.c err = of_property_read_u32(np, "ti,dscr-dev-enable", &val); val 219 arch/c6x/platforms/timer64.c timer64_devstate_id = val; val 18 arch/csky/abiv1/alignment.c static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val) val 21 arch/csky/abiv1/alignment.c regs->lr = val; val 23 arch/csky/abiv1/alignment.c *((uint32_t *)&(regs->a0) - 2 + rx) = val; val 34 arch/csky/abiv1/alignment.c uint32_t val; val 50 arch/csky/abiv1/alignment.c : "=&r"(err), "=r"(val) val 54 arch/csky/abiv1/alignment.c *valp = val; val 65 arch/csky/abiv1/alignment.c static int stb_asm(uint32_t addr, uint32_t val) val 83 arch/csky/abiv1/alignment.c : "r"(val), "r" (addr) val 15 arch/csky/abiv1/inc/abi/reg_ops.h #define cpwcr(reg, val) \ val 17 arch/csky/abiv1/inc/abi/reg_ops.h asm volatile("cpwcr %0, "reg"\n"::"b"(val)); \ val 63 arch/csky/include/asm/pgtable.h #define __swp_type(x) (((x).val >> 4) & 0xff) val 64 arch/csky/include/asm/pgtable.h #define __swp_offset(x) ((x).val >> 12) val 68 arch/csky/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 17 arch/csky/include/asm/reg_ops.h #define mtcr(reg, val) \ val 22 arch/csky/include/asm/reg_ops.h : "r"(val) \ val 48 arch/csky/include/asm/syscall.h int error, long val) val 50 arch/csky/include/asm/syscall.h regs->a0 = (long) error ?: val; val 37 arch/csky/kernel/perf_event.c static void (*hw_raw_write_mapping[CSKY_PMU_MAX_EVENTS])(uint64_t val); val 61 arch/csky/kernel/perf_event.c #define cpwgr(reg, val) \ val 66 arch/csky/kernel/perf_event.c : "r"(val) \ val 80 arch/csky/kernel/perf_event.c #define cpwcr(reg, val) \ val 85 arch/csky/kernel/perf_event.c : "r"(val) \ val 107 arch/csky/kernel/perf_event.c static void csky_pmu_write_cc(uint64_t val) val 109 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2>", (uint32_t) val); val 110 arch/csky/kernel/perf_event.c cpwgr("<0, 0x3>", (uint32_t) (val >> 32)); val 131 arch/csky/kernel/perf_event.c static void csky_pmu_write_ic(uint64_t val) val 133 arch/csky/kernel/perf_event.c cpwgr("<0, 0x4>", (uint32_t) val); val 134 arch/csky/kernel/perf_event.c cpwgr("<0, 0x5>", (uint32_t) (val >> 32)); val 155 arch/csky/kernel/perf_event.c static void csky_pmu_write_icac(uint64_t val) val 157 arch/csky/kernel/perf_event.c cpwgr("<0, 0x6>", (uint32_t) val); val 158 arch/csky/kernel/perf_event.c cpwgr("<0, 0x7>", (uint32_t) (val >> 32)); val 179 arch/csky/kernel/perf_event.c static void csky_pmu_write_icmc(uint64_t val) val 181 arch/csky/kernel/perf_event.c cpwgr("<0, 0x8>", (uint32_t) val); val 182 arch/csky/kernel/perf_event.c cpwgr("<0, 0x9>", (uint32_t) (val >> 32)); val 203 arch/csky/kernel/perf_event.c static void csky_pmu_write_dcac(uint64_t val) val 205 arch/csky/kernel/perf_event.c cpwgr("<0, 0xa>", (uint32_t) val); val 206 arch/csky/kernel/perf_event.c cpwgr("<0, 0xb>", (uint32_t) (val >> 32)); val 227 arch/csky/kernel/perf_event.c static void csky_pmu_write_dcmc(uint64_t val) val 229 arch/csky/kernel/perf_event.c cpwgr("<0, 0xc>", (uint32_t) val); val 230 arch/csky/kernel/perf_event.c cpwgr("<0, 0xd>", (uint32_t) (val >> 32)); val 251 arch/csky/kernel/perf_event.c static void csky_pmu_write_l2ac(uint64_t val) val 253 arch/csky/kernel/perf_event.c cpwgr("<0, 0xe>", (uint32_t) val); val 254 arch/csky/kernel/perf_event.c cpwgr("<0, 0xf>", (uint32_t) (val >> 32)); val 275 arch/csky/kernel/perf_event.c static void csky_pmu_write_l2mc(uint64_t val) val 277 arch/csky/kernel/perf_event.c cpwgr("<0, 0x10>", (uint32_t) val); val 278 arch/csky/kernel/perf_event.c cpwgr("<0, 0x11>", (uint32_t) (val >> 32)); val 299 arch/csky/kernel/perf_event.c static void csky_pmu_write_iutlbmc(uint64_t val) val 301 arch/csky/kernel/perf_event.c cpwgr("<0, 0x14>", (uint32_t) val); val 302 arch/csky/kernel/perf_event.c cpwgr("<0, 0x15>", (uint32_t) (val >> 32)); val 323 arch/csky/kernel/perf_event.c static void csky_pmu_write_dutlbmc(uint64_t val) val 325 arch/csky/kernel/perf_event.c cpwgr("<0, 0x16>", (uint32_t) val); val 326 arch/csky/kernel/perf_event.c cpwgr("<0, 0x17>", (uint32_t) (val >> 32)); val 347 arch/csky/kernel/perf_event.c static void csky_pmu_write_jtlbmc(uint64_t val) val 349 arch/csky/kernel/perf_event.c cpwgr("<0, 0x18>", (uint32_t) val); val 350 arch/csky/kernel/perf_event.c cpwgr("<0, 0x19>", (uint32_t) (val >> 32)); val 371 arch/csky/kernel/perf_event.c static void csky_pmu_write_softc(uint64_t val) val 373 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1a>", (uint32_t) val); val 374 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1b>", (uint32_t) (val >> 32)); val 395 arch/csky/kernel/perf_event.c static void csky_pmu_write_cbmc(uint64_t val) val 397 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1c>", (uint32_t) val); val 398 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1d>", (uint32_t) (val >> 32)); val 419 arch/csky/kernel/perf_event.c static void csky_pmu_write_cbic(uint64_t val) val 421 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1e>", (uint32_t) val); val 422 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1f>", (uint32_t) (val >> 32)); val 443 arch/csky/kernel/perf_event.c static void csky_pmu_write_ibmc(uint64_t val) val 445 arch/csky/kernel/perf_event.c cpwgr("<0, 0x20>", (uint32_t) val); val 446 arch/csky/kernel/perf_event.c cpwgr("<0, 0x21>", (uint32_t) (val >> 32)); val 467 arch/csky/kernel/perf_event.c static void csky_pmu_write_ibic(uint64_t val) val 469 arch/csky/kernel/perf_event.c cpwgr("<0, 0x22>", (uint32_t) val); val 470 arch/csky/kernel/perf_event.c cpwgr("<0, 0x23>", (uint32_t) (val >> 32)); val 491 arch/csky/kernel/perf_event.c static void csky_pmu_write_lsfc(uint64_t val) val 493 arch/csky/kernel/perf_event.c cpwgr("<0, 0x24>", (uint32_t) val); val 494 arch/csky/kernel/perf_event.c cpwgr("<0, 0x25>", (uint32_t) (val >> 32)); val 515 arch/csky/kernel/perf_event.c static void csky_pmu_write_sic(uint64_t val) val 517 arch/csky/kernel/perf_event.c cpwgr("<0, 0x26>", (uint32_t) val); val 518 arch/csky/kernel/perf_event.c cpwgr("<0, 0x27>", (uint32_t) (val >> 32)); val 539 arch/csky/kernel/perf_event.c static void csky_pmu_write_dcrac(uint64_t val) val 541 arch/csky/kernel/perf_event.c cpwgr("<0, 0x28>", (uint32_t) val); val 542 arch/csky/kernel/perf_event.c cpwgr("<0, 0x29>", (uint32_t) (val >> 32)); val 563 arch/csky/kernel/perf_event.c static void csky_pmu_write_dcrmc(uint64_t val) val 565 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2a>", (uint32_t) val); val 566 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2b>", (uint32_t) (val >> 32)); val 587 arch/csky/kernel/perf_event.c static void csky_pmu_write_dcwac(uint64_t val) val 589 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2c>", (uint32_t) val); val 590 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2d>", (uint32_t) (val >> 32)); val 611 arch/csky/kernel/perf_event.c static void csky_pmu_write_dcwmc(uint64_t val) val 613 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2e>", (uint32_t) val); val 614 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2f>", (uint32_t) (val >> 32)); val 635 arch/csky/kernel/perf_event.c static void csky_pmu_write_l2rac(uint64_t val) val 637 arch/csky/kernel/perf_event.c cpwgr("<0, 0x30>", (uint32_t) val); val 638 arch/csky/kernel/perf_event.c cpwgr("<0, 0x31>", (uint32_t) (val >> 32)); val 659 arch/csky/kernel/perf_event.c static void csky_pmu_write_l2rmc(uint64_t val) val 661 arch/csky/kernel/perf_event.c cpwgr("<0, 0x32>", (uint32_t) val); val 662 arch/csky/kernel/perf_event.c cpwgr("<0, 0x33>", (uint32_t) (val >> 32)); val 683 arch/csky/kernel/perf_event.c static void csky_pmu_write_l2wac(uint64_t val) val 685 arch/csky/kernel/perf_event.c cpwgr("<0, 0x34>", (uint32_t) val); val 686 arch/csky/kernel/perf_event.c cpwgr("<0, 0x35>", (uint32_t) (val >> 32)); val 707 arch/csky/kernel/perf_event.c static void csky_pmu_write_l2wmc(uint64_t val) val 709 arch/csky/kernel/perf_event.c cpwgr("<0, 0x36>", (uint32_t) val); val 710 arch/csky/kernel/perf_event.c cpwgr("<0, 0x37>", (uint32_t) (val >> 32)); val 25 arch/csky/mm/cachev1.c static inline void cache_op_line(unsigned long i, unsigned int val) val 28 arch/csky/mm/cachev1.c mtcr("cr17", val); val 50 arch/csky/mm/cachev1.c unsigned int val = value | CACHE_CLR | CACHE_OMS; val 69 arch/csky/mm/cachev1.c cache_op_line(i, val); val 72 arch/csky/mm/cachev1.c mtcr("cr24", val); val 22 arch/h8300/include/asm/flat.h u32 val = get_unaligned((__force u32 *)rp); val 24 arch/h8300/include/asm/flat.h val &= 0x00ffffff; val 25 arch/h8300/include/asm/flat.h *addr = val; val 17 arch/h8300/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 121 arch/hexagon/include/asm/atomic.h int output, val; \ val 128 arch/hexagon/include/asm/atomic.h : "=&r" (output), "=&r" (val) \ val 117 arch/hexagon/include/asm/hexagon_vm.h static inline long __vmcache_fetch_cfg(unsigned long val) val 119 arch/hexagon/include/asm/hexagon_vm.h return __vmcache(hvmc_fetch_cfg, val, 0); val 86 arch/hexagon/include/asm/io.h u8 val; val 89 arch/hexagon/include/asm/io.h : "=&r" (val) val 92 arch/hexagon/include/asm/io.h return val; val 97 arch/hexagon/include/asm/io.h u16 val; val 100 arch/hexagon/include/asm/io.h : "=&r" (val) val 103 arch/hexagon/include/asm/io.h return val; val 108 arch/hexagon/include/asm/io.h u32 val; val 111 arch/hexagon/include/asm/io.h : "=&r" (val) val 114 arch/hexagon/include/asm/io.h return val; val 392 arch/hexagon/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 456 arch/hexagon/include/asm/pgtable.h #define __swp_type(swp_pte) (((swp_pte).val >> 1) & 0x1f) val 459 arch/hexagon/include/asm/pgtable.h ((((swp_pte).val >> 6) & 0xf) | (((swp_pte).val >> 9) & 0x7ffff0)) val 204 arch/hexagon/include/uapi/asm/registers.h #define pt_set_elr(regs, val) ((regs)->hvmer.vmel = (val)) val 275 arch/ia64/hp/common/sba_iommu.c #define WRITE_REG(val, addr) __raw_writeq(val, addr) val 22 arch/ia64/include/asm/acenv.h unsigned int old, new, val; val 26 arch/ia64/include/asm/acenv.h val = ia64_cmpxchg4_acq(lock, new, old); val 27 arch/ia64/include/asm/acenv.h } while (unlikely (val != old)); val 34 arch/ia64/include/asm/acenv.h unsigned int old, new, val; val 38 arch/ia64/include/asm/acenv.h val = ia64_cmpxchg4_acq(lock, new, old); val 39 arch/ia64/include/asm/acenv.h } while (unlikely (val != old)); val 24 arch/ia64/include/asm/delay.h ia64_set_itm (unsigned long val) val 26 arch/ia64/include/asm/delay.h ia64_setreg(_IA64_REG_CR_ITM, val); val 41 arch/ia64/include/asm/delay.h ia64_set_itv (unsigned long val) val 43 arch/ia64/include/asm/delay.h ia64_setreg(_IA64_REG_CR_ITV, val); val 54 arch/ia64/include/asm/delay.h ia64_set_itc (unsigned long val) val 56 arch/ia64/include/asm/delay.h ia64_setreg(_IA64_REG_AR_ITC, val); val 224 arch/ia64/include/asm/elf.h uint64_t val; val 26 arch/ia64/include/asm/futex.h int val, newval; \ val 38 arch/ia64/include/asm/futex.h : "+r" (r8), "=r" (val), "=&r" (oldval), \ val 44 arch/ia64/include/asm/futex.h } while (unlikely (val != oldval)); \ val 173 arch/ia64/include/asm/io.h static inline void outb(unsigned char val, unsigned long port) val 177 arch/ia64/include/asm/io.h *addr = val; val 182 arch/ia64/include/asm/io.h static inline void outw(unsigned short val, unsigned long port) val 186 arch/ia64/include/asm/io.h *addr = val; val 191 arch/ia64/include/asm/io.h static inline void outl(unsigned int val, unsigned long port) val 195 arch/ia64/include/asm/io.h *addr = val; val 73 arch/ia64/include/asm/iosapic.h __ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) val 76 arch/ia64/include/asm/iosapic.h writel(val, iosapic + IOSAPIC_WINDOW); val 111 arch/ia64/include/asm/kprobes.h unsigned long val, void *data); val 18 arch/ia64/include/asm/patch.h extern void ia64_patch (u64 insn_addr, u64 mask, u64 val); /* patch any insn slot */ val 19 arch/ia64/include/asm/patch.h extern void ia64_patch_imm64 (u64 insn_addr, u64 val); /* patch "movl" w/abs. value*/ val 20 arch/ia64/include/asm/patch.h extern void ia64_patch_imm60 (u64 insn_addr, u64 val); /* patch "brl" w/ip-rel value */ val 24 arch/ia64/include/asm/patch.h extern void ia64_patch_phys_stack_reg(unsigned long val); val 43 arch/ia64/include/asm/pci.h int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size); val 44 arch/ia64/include/asm/pci.h int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size); val 40 arch/ia64/include/asm/perfmon.h unsigned int val; val 476 arch/ia64/include/asm/pgtable.h #define __swp_type(entry) (((entry).val >> 1) & 0x7f) val 477 arch/ia64/include/asm/pgtable.h #define __swp_offset(entry) (((entry).val << 1) >> 9) val 480 arch/ia64/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 124 arch/ia64/include/asm/processor.h __u64 val; val 145 arch/ia64/include/asm/processor.h __u64 val; val 155 arch/ia64/include/asm/processor.h __u64 val; val 166 arch/ia64/include/asm/processor.h __u64 val; val 176 arch/ia64/include/asm/processor.h __u64 val; val 568 arch/ia64/include/asm/processor.h ia64_set_lrr0 (unsigned long val) val 570 arch/ia64/include/asm/processor.h ia64_setreg(_IA64_REG_CR_LRR0, val); val 575 arch/ia64/include/asm/processor.h ia64_set_lrr1 (unsigned long val) val 577 arch/ia64/include/asm/processor.h ia64_setreg(_IA64_REG_CR_LRR1, val); val 83 arch/ia64/include/asm/sn/sn_sal.h u64 val; val 108 arch/ia64/include/asm/sn/sn_sal.h size_blade.val, (u64)intr_mmr_offset, val 46 arch/ia64/include/asm/syscall.h int error, long val) val 53 arch/ia64/include/asm/syscall.h regs->r8 = val; val 31 arch/ia64/include/asm/tlbflush.h #define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001) val 32 arch/ia64/include/asm/tlbflush.h #define RR_VE(val) (((val) & 0x0000000000000001) << 0) val 35 arch/ia64/include/asm/tlbflush.h #define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f) val 36 arch/ia64/include/asm/tlbflush.h #define RR_PS(val) (((val) & 0x000000000000003f) << 2) val 40 arch/ia64/include/asm/tlbflush.h #define RR_TO_RID(val) ((val >> 8) & 0xffffff) val 97 arch/ia64/include/asm/uaccess.h # define __get_user_size(val, addr, n, err) \ val 106 arch/ia64/include/asm/uaccess.h (val) = __gu_r9; \ val 114 arch/ia64/include/asm/uaccess.h # define __put_user_size(val, addr, n, err) \ val 120 arch/ia64/include/asm/uaccess.h : "=r"(__pu_r8) : "m"(__m(addr)), "rO"(val), "0"(__pu_r8)); \ val 126 arch/ia64/include/asm/uaccess.h # define __get_user_size(val, addr, n, err) \ val 130 arch/ia64/include/asm/uaccess.h (val) = ia64_getreg(_IA64_REG_R9); \ val 132 arch/ia64/include/asm/uaccess.h # define __put_user_size(val, addr, n, err) \ val 135 arch/ia64/include/asm/uaccess.h (__force unsigned long) (val)); \ val 177 arch/ia64/include/asm/unwind.h unw_set_cfm (struct unw_frame_info *info, unsigned long val) val 179 arch/ia64/include/asm/unwind.h *(info)->cfm_loc = val; val 184 arch/ia64/include/asm/unwind.h unw_get_rp (struct unw_frame_info *info, unsigned long *val) val 188 arch/ia64/include/asm/unwind.h *val = *info->rp_loc; val 190 arch/ia64/include/asm/uv/uv_hub.h unsigned long val) val 192 arch/ia64/include/asm/uv/uv_hub.h *uv_global_mmr32_address(pnode, offset) = val; val 213 arch/ia64/include/asm/uv/uv_hub.h unsigned long val) val 215 arch/ia64/include/asm/uv/uv_hub.h *uv_global_mmr64_address(pnode, offset) = val; val 238 arch/ia64/include/asm/uv/uv_hub.h static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) val 240 arch/ia64/include/asm/uv/uv_hub.h *uv_local_mmr_address(offset) = val; val 34 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_native_setreg(regnum, val) \ val 38 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \ val 43 arch/ia64/include/uapi/asm/gcc_intrin.h "r"(val): "memory"); \ val 48 arch/ia64/include/uapi/asm/gcc_intrin.h "r"(val): "memory" ); \ val 52 arch/ia64/include/uapi/asm/gcc_intrin.h "r"(val): "memory"); \ val 55 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \ val 199 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_st4_rel_nta(m, val) \ val 201 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \ val 425 arch/ia64/include/uapi/asm/gcc_intrin.h #define __ia64_set_dbr(index, val) \ val 426 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory") val 428 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_set_ibr(index, val) \ val 429 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory") val 431 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_set_pkr(index, val) \ val 432 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory") val 434 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_set_pmc(index, val) \ val 435 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory") val 437 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_set_pmd(index, val) \ val 438 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory") val 440 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_native_set_rr(index, val) \ val 441 arch/ia64/include/uapi/asm/gcc_intrin.h asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory"); val 82 arch/ia64/include/uapi/asm/intel_intrin.h #define __ia64_set_dbr(index, val) \ val 83 arch/ia64/include/uapi/asm/intel_intrin.h __setIndReg(_IA64_REG_INDR_DBR, index, val) val 84 arch/ia64/include/uapi/asm/intel_intrin.h #define ia64_set_ibr(index, val) \ val 85 arch/ia64/include/uapi/asm/intel_intrin.h __setIndReg(_IA64_REG_INDR_IBR, index, val) val 86 arch/ia64/include/uapi/asm/intel_intrin.h #define ia64_set_pkr(index, val) \ val 87 arch/ia64/include/uapi/asm/intel_intrin.h __setIndReg(_IA64_REG_INDR_PKR, index, val) val 88 arch/ia64/include/uapi/asm/intel_intrin.h #define ia64_set_pmc(index, val) \ val 89 arch/ia64/include/uapi/asm/intel_intrin.h __setIndReg(_IA64_REG_INDR_PMC, index, val) val 90 arch/ia64/include/uapi/asm/intel_intrin.h #define ia64_set_pmd(index, val) \ val 91 arch/ia64/include/uapi/asm/intel_intrin.h __setIndReg(_IA64_REG_INDR_PMD, index, val) val 92 arch/ia64/include/uapi/asm/intel_intrin.h #define ia64_native_set_rr(index, val) \ val 93 arch/ia64/include/uapi/asm/intel_intrin.h __setIndReg(_IA64_REG_INDR_RR, index, val) val 156 arch/ia64/kernel/crash.c kdump_init_notifier(struct notifier_block *self, unsigned long val, void *data) val 162 arch/ia64/kernel/crash.c switch (val) { val 179 arch/ia64/kernel/crash.c if (val == DIE_INIT_MONARCH_LEAVE) val 186 arch/ia64/kernel/crash.c if (val != DIE_INIT_MONARCH_LEAVE && val 187 arch/ia64/kernel/crash.c val != DIE_INIT_MONARCH_PROCESS && val 188 arch/ia64/kernel/crash.c val != DIE_MCA_MONARCH_LEAVE) val 193 arch/ia64/kernel/crash.c switch (val) { val 150 arch/ia64/kernel/iosapic.c iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val) val 155 arch/ia64/kernel/iosapic.c __iosapic_write(iosapic->addr, reg, val); val 954 arch/ia64/kernel/kprobes.c unsigned long val, void *data) val 962 arch/ia64/kernel/kprobes.c switch(val) { val 1597 arch/ia64/kernel/mca.c default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data) val 1601 arch/ia64/kernel/mca.c if (val != DIE_INIT_MONARCH_PROCESS) val 156 arch/ia64/kernel/module.c apply_imm64 (struct module *mod, struct insn *insn, uint64_t val) val 163 arch/ia64/kernel/module.c ia64_patch_imm64((u64) insn, val); val 168 arch/ia64/kernel/module.c apply_imm60 (struct module *mod, struct insn *insn, uint64_t val) val 175 arch/ia64/kernel/module.c if (val + ((uint64_t) 1 << 59) >= (1UL << 60)) { val 177 arch/ia64/kernel/module.c mod->name, (long) val); val 180 arch/ia64/kernel/module.c ia64_patch_imm60((u64) insn, val); val 185 arch/ia64/kernel/module.c apply_imm22 (struct module *mod, struct insn *insn, uint64_t val) val 187 arch/ia64/kernel/module.c if (val + (1 << 21) >= (1 << 22)) { val 189 arch/ia64/kernel/module.c mod->name, (long)val); val 192 arch/ia64/kernel/module.c ia64_patch((u64) insn, 0x01fffcfe000UL, ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ val 193 arch/ia64/kernel/module.c | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ val 194 arch/ia64/kernel/module.c | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ val 195 arch/ia64/kernel/module.c | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); val 200 arch/ia64/kernel/module.c apply_imm21b (struct module *mod, struct insn *insn, uint64_t val) val 202 arch/ia64/kernel/module.c if (val + (1 << 20) >= (1 << 21)) { val 204 arch/ia64/kernel/module.c mod->name, (long)val); val 207 arch/ia64/kernel/module.c ia64_patch((u64) insn, 0x11ffffe000UL, ( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */ val 208 arch/ia64/kernel/module.c | ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */)); val 519 arch/ia64/kernel/module.c if (e->val == value) val 525 arch/ia64/kernel/module.c e->val = value; val 624 arch/ia64/kernel/module.c uint64_t val; val 627 arch/ia64/kernel/module.c val = sym->st_value + addend; val 634 arch/ia64/kernel/module.c case RV_GPREL: val -= mod->arch.gp; break; val 635 arch/ia64/kernel/module.c case RV_LTREL: val = get_ltoff(mod, val, &ok); break; val 636 arch/ia64/kernel/module.c case RV_PLTREL: val = get_plt(mod, location, val, &ok); break; val 637 arch/ia64/kernel/module.c case RV_FPTR: val = get_fdesc(mod, val, &ok); break; val 638 arch/ia64/kernel/module.c case RV_SECREL: val -= sec->sh_addr; break; val 639 arch/ia64/kernel/module.c case RV_LTREL_FPTR: val = get_ltoff(mod, get_fdesc(mod, val, &ok), &ok); break; val 644 arch/ia64/kernel/module.c if ((in_init(mod, val) && in_core(mod, (uint64_t)location)) || val 645 arch/ia64/kernel/module.c (in_core(mod, val) && in_init(mod, (uint64_t)location))) { val 650 arch/ia64/kernel/module.c uint64_t delta = ((int64_t)val - (int64_t)location) / 16; val 652 arch/ia64/kernel/module.c val = get_fdesc(mod, val, &ok); val 653 arch/ia64/kernel/module.c val = get_plt(mod, location, val, &ok); val 655 arch/ia64/kernel/module.c } else if (!is_internal(mod, val)) val 656 arch/ia64/kernel/module.c val = get_plt(mod, location, val, &ok); val 659 arch/ia64/kernel/module.c val -= bundle(location); val 666 arch/ia64/kernel/module.c val -= (uint64_t) location; val 680 arch/ia64/kernel/module.c val -= (uint64_t) (in_init(mod, val) ? mod->init_layout.base : mod->core_layout.base); val 690 arch/ia64/kernel/module.c if (!is_internal(mod, val)) { val 693 arch/ia64/kernel/module.c reloc_name[r_type], (unsigned long)val); val 698 arch/ia64/kernel/module.c val -= bundle(location); val 705 arch/ia64/kernel/module.c val = get_fdesc(mod, get_plt(mod, location, val, &ok), &ok); val 712 arch/ia64/kernel/module.c val = addend - sym->st_value; val 717 arch/ia64/kernel/module.c if (gp_addressable(mod, val)) val 718 arch/ia64/kernel/module.c val -= mod->arch.gp; val 720 arch/ia64/kernel/module.c val = get_ltoff(mod, val, &ok); val 725 arch/ia64/kernel/module.c if (gp_addressable(mod, val)) { val 761 arch/ia64/kernel/module.c DEBUGP("%s: [%p]<-%016lx = %s(%lx)\n", __func__, location, val, val 765 arch/ia64/kernel/module.c case RF_INSN21B: ok = apply_imm21b(mod, location, (int64_t) val / 16); break; val 766 arch/ia64/kernel/module.c case RF_INSN22: ok = apply_imm22(mod, location, val); break; val 767 arch/ia64/kernel/module.c case RF_INSN64: ok = apply_imm64(mod, location, val); break; val 768 arch/ia64/kernel/module.c case RF_INSN60: ok = apply_imm60(mod, location, (int64_t) val / 16); break; val 769 arch/ia64/kernel/module.c case RF_32LSB: put_unaligned(val, (uint32_t *) location); break; val 770 arch/ia64/kernel/module.c case RF_64LSB: put_unaligned(val, (uint64_t *) location); break; val 45 arch/ia64/kernel/patch.c ia64_patch (u64 insn_addr, u64 mask, u64 val) val 55 arch/ia64/kernel/patch.c v1 = val << (shift - 64); val 58 arch/ia64/kernel/patch.c v0 = val << shift; v1 = val >> (64 - shift); val 65 arch/ia64/kernel/patch.c ia64_patch_imm64 (u64 insn_addr, u64 val) val 72 arch/ia64/kernel/patch.c 0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ val 73 arch/ia64/kernel/patch.c | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ val 74 arch/ia64/kernel/patch.c | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ val 75 arch/ia64/kernel/patch.c | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ val 76 arch/ia64/kernel/patch.c | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */)); val 77 arch/ia64/kernel/patch.c ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22); val 81 arch/ia64/kernel/patch.c ia64_patch_imm60 (u64 insn_addr, u64 val) val 88 arch/ia64/kernel/patch.c 0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ val 89 arch/ia64/kernel/patch.c | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); val 90 arch/ia64/kernel/patch.c ia64_patch(insn_addr + 1, 0x1fffffffffcUL, val >> 18); val 219 arch/ia64/kernel/patch.c void ia64_patch_phys_stack_reg(unsigned long val) val 227 arch/ia64/kernel/patch.c imm = (((val >> 7) & 0x3f) << 27) | (val & 0x7f) << 13; val 220 arch/ia64/kernel/perfmon.c #define PFM_REG_RETFLAG_SET(flags, val) do { flags &= ~PFM_REG_RETFL_MASK; flags |= (val); } while(0) val 251 arch/ia64/kernel/perfmon.c unsigned long val; /* virtual 64bit counter value */ val 392 arch/ia64/kernel/perfmon.c typedef int (*pfm_reg_check_t)(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs); val 405 arch/ia64/kernel/perfmon.c #define PMC_PM(cnum, val) (((val) >> (pmu_conf->pmc_desc[cnum].pm_pos)) & 0x1) val 463 arch/ia64/kernel/perfmon.c unsigned long val; val 694 arch/ia64/kernel/perfmon.c pfm_set_psr_l(unsigned long val) val 696 arch/ia64/kernel/perfmon.c ia64_setreg(_IA64_REG_PSR_L, val); val 744 arch/ia64/kernel/perfmon.c return ctx->ctx_pmds[i].val + (ia64_get_pmd(i) & pmu_conf->ovfl_val); val 751 arch/ia64/kernel/perfmon.c pfm_write_soft_counter(pfm_context_t *ctx, int i, unsigned long val) val 755 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val = val & ~ovfl_val; val 760 arch/ia64/kernel/perfmon.c ia64_set_pmd(i, val & ovfl_val); val 881 arch/ia64/kernel/perfmon.c unsigned long mask, val, ovfl_mask; val 910 arch/ia64/kernel/perfmon.c val = ia64_get_pmd(i); val 916 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val += (val & ovfl_mask); val 918 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val = val; val 922 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val, val 923 arch/ia64/kernel/perfmon.c val & ovfl_mask)); val 956 arch/ia64/kernel/perfmon.c unsigned long psr, val; val 1002 arch/ia64/kernel/perfmon.c val = ctx->ctx_pmds[i].val & ovfl_mask; val 1003 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val &= ~ovfl_mask; val 1005 arch/ia64/kernel/perfmon.c val = ctx->ctx_pmds[i].val; val 1007 arch/ia64/kernel/perfmon.c ia64_set_pmd(i, val); val 1011 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val, val 1012 arch/ia64/kernel/perfmon.c val)); val 1066 arch/ia64/kernel/perfmon.c unsigned long val, ovfl_val = pmu_conf->ovfl_val; val 1070 arch/ia64/kernel/perfmon.c val = PMD_IS_COUNTING(i) ? pmds[i] & ovfl_val : pmds[i]; val 1071 arch/ia64/kernel/perfmon.c ia64_set_pmd(i, val); val 1084 arch/ia64/kernel/perfmon.c unsigned long val; val 1091 arch/ia64/kernel/perfmon.c val = ctx->ctx_pmds[i].val; val 1100 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val = val & ~ovfl_val; val 1101 arch/ia64/kernel/perfmon.c val &= ovfl_val; val 1103 arch/ia64/kernel/perfmon.c ctx->th_pmds[i] = val; val 1108 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val)); val 2662 arch/ia64/kernel/perfmon.c unsigned long val = is_long_reset ? reg->long_reset : reg->short_reset; val 2668 arch/ia64/kernel/perfmon.c val -= (old_seed & mask); /* counter values are negative numbers! */ val 2674 arch/ia64/kernel/perfmon.c reg->lval = val; val 2675 arch/ia64/kernel/perfmon.c return val; val 2683 arch/ia64/kernel/perfmon.c unsigned long val; val 2694 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val = val = pfm_new_counter_value(ctx->ctx_pmds+ i, is_long_reset); val 2697 arch/ia64/kernel/perfmon.c DPRINT_ovfl((" %s reset ctx_pmds[%d]=%lx\n", is_long_reset ? "long" : "short", i, val)); val 2707 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val = val = pfm_new_counter_value(ctx->ctx_pmds + i, is_long_reset); val 2710 arch/ia64/kernel/perfmon.c is_long_reset ? "long" : "short", i, val)); val 2719 arch/ia64/kernel/perfmon.c unsigned long val; val 2737 arch/ia64/kernel/perfmon.c val = pfm_new_counter_value(ctx->ctx_pmds+ i, is_long_reset); val 2740 arch/ia64/kernel/perfmon.c DPRINT_ovfl((" %s reset ctx_pmds[%d]=%lx\n", is_long_reset ? "long" : "short", i, val)); val 2742 arch/ia64/kernel/perfmon.c pfm_write_soft_counter(ctx, i, val); val 2752 arch/ia64/kernel/perfmon.c val = pfm_new_counter_value(ctx->ctx_pmds + i, is_long_reset); val 2755 arch/ia64/kernel/perfmon.c pfm_write_soft_counter(ctx, i, val); val 2757 arch/ia64/kernel/perfmon.c ia64_set_pmd(i, val); val 2760 arch/ia64/kernel/perfmon.c is_long_reset ? "long" : "short", i, val)); val 3111 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[cnum].val = value; val 3164 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[cnum].val, val 3205 arch/ia64/kernel/perfmon.c unsigned long val = 0UL, lval, ovfl_mask, sval; val 3271 arch/ia64/kernel/perfmon.c sval = ctx->ctx_pmds[cnum].val; val 3281 arch/ia64/kernel/perfmon.c val = ia64_get_pmd(cnum); val 3288 arch/ia64/kernel/perfmon.c val = is_loaded ? ctx->th_pmds[cnum] : 0UL; val 3296 arch/ia64/kernel/perfmon.c val &= ovfl_mask; val 3297 arch/ia64/kernel/perfmon.c val += sval; val 3304 arch/ia64/kernel/perfmon.c unsigned long v = val; val 3307 arch/ia64/kernel/perfmon.c val = v; val 3313 arch/ia64/kernel/perfmon.c DPRINT(("pmd[%u]=0x%lx\n", cnum, val)); val 3320 arch/ia64/kernel/perfmon.c req->reg_value = val; val 3740 arch/ia64/kernel/perfmon.c dbreg.val = req->dbreg_value; val 3746 arch/ia64/kernel/perfmon.c rnum, dbreg.val, mode, i, count)); val 3777 arch/ia64/kernel/perfmon.c ia64_set_ibr(rnum, dbreg.val); val 3781 arch/ia64/kernel/perfmon.c ctx->ctx_ibrs[rnum] = dbreg.val; val 3784 arch/ia64/kernel/perfmon.c rnum, dbreg.val, ctx->ctx_used_ibrs[0], is_loaded, can_access_pmu)); val 3789 arch/ia64/kernel/perfmon.c ia64_set_dbr(rnum, dbreg.val); val 3792 arch/ia64/kernel/perfmon.c ctx->ctx_dbrs[rnum] = dbreg.val; val 3795 arch/ia64/kernel/perfmon.c rnum, dbreg.val, ctx->ctx_used_dbrs[0], is_loaded, can_access_pmu)); val 5168 arch/ia64/kernel/perfmon.c old_val = new_val = ctx->ctx_pmds[i].val; val 5170 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val = new_val; val 5197 arch/ia64/kernel/perfmon.c ovfl_ctrl.val = 0; val 5224 arch/ia64/kernel/perfmon.c ovfl_arg->ovfl_ctrl.val = 0; /* module must fill in all fields */ val 5227 arch/ia64/kernel/perfmon.c ovfl_arg->pmd_value = ctx->ctx_pmds[i].val; val 6210 arch/ia64/kernel/perfmon.c unsigned long mask2, val, pmd_val, ovfl_val; val 6278 arch/ia64/kernel/perfmon.c val = pmd_val = can_access_pmu ? ia64_get_pmd(i) : ctx->th_pmds[i]; val 6284 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val, val 6285 arch/ia64/kernel/perfmon.c val & ovfl_val)); val 6290 arch/ia64/kernel/perfmon.c val = ctx->ctx_pmds[i].val + (val & ovfl_val); val 6303 arch/ia64/kernel/perfmon.c val += 1 + ovfl_val; val 6308 arch/ia64/kernel/perfmon.c DPRINT(("[%d] ctx_pmd[%d]=0x%lx pmd_val=0x%lx\n", task_pid_nr(task), i, val, pmd_val)); val 6312 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[i].val = val; val 178 arch/ia64/kernel/perfmon_default_smpl.c unsigned long *val = arg->smpl_pmds_values; val 180 arch/ia64/kernel/perfmon_default_smpl.c *e++ = *val++; val 9 arch/ia64/kernel/perfmon_itanium.h static int pfm_ita_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs); val 52 arch/ia64/kernel/perfmon_itanium.h pfm_ita_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs) val 66 arch/ia64/kernel/perfmon_itanium.h if (cnum == 13 && is_loaded && ((*val & 0x1) == 0UL) && ctx->ctx_fl_using_dbreg == 0) { val 68 arch/ia64/kernel/perfmon_itanium.h DPRINT(("pmc[%d]=0x%lx has active pmc13.ta cleared, clearing ibr\n", cnum, *val)); val 85 arch/ia64/kernel/perfmon_itanium.h if (cnum == 11 && is_loaded && ((*val >> 28)& 0x1) == 0 && ctx->ctx_fl_using_dbreg == 0) { val 87 arch/ia64/kernel/perfmon_itanium.h DPRINT(("pmc[%d]=0x%lx has active pmc11.pt cleared, clearing dbr\n", cnum, *val)); val 9 arch/ia64/kernel/perfmon_mckinley.h static int pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs); val 57 arch/ia64/kernel/perfmon_mckinley.h pfm_mck_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs) val 59 arch/ia64/kernel/perfmon_mckinley.h unsigned long tmp1, tmp2, ival = *val; val 67 arch/ia64/kernel/perfmon_mckinley.h *val = tmp1 | tmp2; val 70 arch/ia64/kernel/perfmon_mckinley.h cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val)); val 78 arch/ia64/kernel/perfmon_mckinley.h pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs) val 85 arch/ia64/kernel/perfmon_mckinley.h pfm_mck_reserved(cnum, val, regs); val 102 arch/ia64/kernel/perfmon_mckinley.h DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, *val, ctx->ctx_fl_using_dbreg, is_loaded)); val 105 arch/ia64/kernel/perfmon_mckinley.h && (*val & 0x1e00000000000UL) && (*val & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) { val 107 arch/ia64/kernel/perfmon_mckinley.h DPRINT(("pmc[%d]=0x%lx has active pmc13 settings, clearing dbr\n", cnum, *val)); val 123 arch/ia64/kernel/perfmon_mckinley.h if (cnum == 14 && is_loaded && ((*val & 0x2222UL) != 0x2222UL) && ctx->ctx_fl_using_dbreg == 0) { val 125 arch/ia64/kernel/perfmon_mckinley.h DPRINT(("pmc[%d]=0x%lx has active pmc14 settings, clearing ibr\n", cnum, *val)); val 140 arch/ia64/kernel/perfmon_mckinley.h case 4: *val |= 1UL << 23; /* force power enable bit */ val 142 arch/ia64/kernel/perfmon_mckinley.h case 8: val8 = *val; val 148 arch/ia64/kernel/perfmon_mckinley.h val13 = *val; val 154 arch/ia64/kernel/perfmon_mckinley.h val14 = *val; val 9 arch/ia64/kernel/perfmon_montecito.h static int pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs); val 135 arch/ia64/kernel/perfmon_montecito.h pfm_mont_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs) val 137 arch/ia64/kernel/perfmon_montecito.h unsigned long tmp1, tmp2, ival = *val; val 145 arch/ia64/kernel/perfmon_montecito.h *val = tmp1 | tmp2; val 148 arch/ia64/kernel/perfmon_montecito.h cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val)); val 156 arch/ia64/kernel/perfmon_montecito.h pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs) val 165 arch/ia64/kernel/perfmon_montecito.h pfm_mont_reserved(cnum, val, regs); val 167 arch/ia64/kernel/perfmon_montecito.h tmpval = *val; val 225 arch/ia64/kernel/perfmon_montecito.h case 32: val32 = *val; val 230 arch/ia64/kernel/perfmon_montecito.h case 38: val38 = *val; val 235 arch/ia64/kernel/perfmon_montecito.h case 41: val41 = *val; val 253 arch/ia64/kernel/perfmon_montecito.h *val = tmpval; val 141 arch/ia64/kernel/process.c unsigned long val, *bsp, ndirty; val 148 arch/ia64/kernel/process.c get_user(val, (unsigned long __user *) ia64_rse_skip_regs(bsp, i)); val 149 arch/ia64/kernel/process.c printk("r%-3u:%c%016lx%s", 32 + i, is_nat ? '*' : ' ', val, val 91 arch/ia64/kernel/ptrace.c unsigned long val; val 98 arch/ia64/kernel/ptrace.c val = GET_BITS( 1, 1, scratch_unat); val 99 arch/ia64/kernel/ptrace.c val |= GET_BITS( 2, 3, scratch_unat); val 100 arch/ia64/kernel/ptrace.c val |= GET_BITS(12, 13, scratch_unat); val 101 arch/ia64/kernel/ptrace.c val |= GET_BITS(14, 14, scratch_unat); val 102 arch/ia64/kernel/ptrace.c val |= GET_BITS(15, 15, scratch_unat); val 103 arch/ia64/kernel/ptrace.c val |= GET_BITS( 8, 11, scratch_unat); val 104 arch/ia64/kernel/ptrace.c val |= GET_BITS(16, 31, scratch_unat); val 105 arch/ia64/kernel/ptrace.c return val; val 406 arch/ia64/kernel/ptrace.c unsigned long user_rbs_end, unsigned long addr, long *val) val 431 arch/ia64/kernel/ptrace.c *val = ret; val 445 arch/ia64/kernel/ptrace.c *val = 0; val 455 arch/ia64/kernel/ptrace.c *val = *ia64_rse_skip_regs(krbs, regnum); val 462 arch/ia64/kernel/ptrace.c *val = ret; val 468 arch/ia64/kernel/ptrace.c unsigned long user_rbs_end, unsigned long addr, long val) val 487 arch/ia64/kernel/ptrace.c put_rnat(child, child_stack, krbs, laddr, val, val 492 arch/ia64/kernel/ptrace.c *ia64_rse_skip_regs(krbs, regnum) = val; val 495 arch/ia64/kernel/ptrace.c } else if (access_process_vm(child, addr, &val, sizeof(val), val 497 arch/ia64/kernel/ptrace.c != sizeof(val)) val 542 arch/ia64/kernel/ptrace.c unsigned long addr, val; val 547 arch/ia64/kernel/ptrace.c ret = ia64_peek(child, sw, user_rbs_end, addr, &val); val 550 arch/ia64/kernel/ptrace.c if (access_process_vm(child, addr, &val, sizeof(val), val 552 arch/ia64/kernel/ptrace.c != sizeof(val)) val 562 arch/ia64/kernel/ptrace.c unsigned long addr, val; val 567 arch/ia64/kernel/ptrace.c if (access_process_vm(child, addr, &val, sizeof(val), val 569 arch/ia64/kernel/ptrace.c != sizeof(val)) val 572 arch/ia64/kernel/ptrace.c ret = ia64_poke(child, sw, user_rbs_end, addr, val); val 830 arch/ia64/kernel/ptrace.c unsigned long psr, ec, lc, rnat, bsp, cfm, nat_bits, val; val 891 arch/ia64/kernel/ptrace.c if (unw_access_gr(&info, i, &val, &nat, 0) < 0) val 893 arch/ia64/kernel/ptrace.c retval |= __put_user(val, &ppr->gr[i]); val 917 arch/ia64/kernel/ptrace.c if (unw_access_br(&info, i, &val, 0) < 0) val 919 arch/ia64/kernel/ptrace.c __put_user(val, &ppr->br[i]); val 974 arch/ia64/kernel/ptrace.c unsigned long psr, rsc, ec, lc, rnat, bsp, cfm, nat_bits, val = 0; val 1027 arch/ia64/kernel/ptrace.c retval |= __get_user(val, &ppr->gr[i]); val 1029 arch/ia64/kernel/ptrace.c if (unw_set_gr(&info, i, val, 0) < 0) val 1054 arch/ia64/kernel/ptrace.c retval |= __get_user(val, &ppr->br[i]); val 1055 arch/ia64/kernel/ptrace.c unw_set_br(&info, i, val); val 308 arch/ia64/kernel/unaligned.c set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat) val 341 arch/ia64/kernel/unaligned.c *addr = val; val 361 arch/ia64/kernel/unaligned.c ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val); val 381 arch/ia64/kernel/unaligned.c get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int *nat) val 409 arch/ia64/kernel/unaligned.c *val = *addr; val 432 arch/ia64/kernel/unaligned.c ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val); val 446 arch/ia64/kernel/unaligned.c *val = 0; val 454 arch/ia64/kernel/unaligned.c setreg (unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs) val 465 arch/ia64/kernel/unaligned.c set_rse_reg(regs, regnum, val, nat); val 492 arch/ia64/kernel/unaligned.c *(unsigned long *)addr = val; val 499 arch/ia64/kernel/unaligned.c DPRINT("*0x%lx=0x%lx NaT=%d prev_unat @%p=%lx\n", addr, val, nat, (void *) unat, *unat); val 505 arch/ia64/kernel/unaligned.c DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat); val 628 arch/ia64/kernel/unaligned.c getreg (unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs) val 634 arch/ia64/kernel/unaligned.c get_rse_reg(regs, regnum, val, nat); val 642 arch/ia64/kernel/unaligned.c *val = 0; val 663 arch/ia64/kernel/unaligned.c *val = *(unsigned long *)addr; val 757 arch/ia64/kernel/unaligned.c unsigned long val = 0; val 777 arch/ia64/kernel/unaligned.c if (copy_from_user(&val, (void __user *) ifa, len)) val 779 arch/ia64/kernel/unaligned.c setreg(ld.r1, val, 0, regs); val 284 arch/ia64/kernel/unwind.c unw_access_gr (struct unw_frame_info *info, int regnum, unsigned long *val, char *nat, int write) val 292 arch/ia64/kernel/unwind.c *val = 0; /* read r0 always returns 0 */ val 322 arch/ia64/kernel/unwind.c *val = 0; val 390 arch/ia64/kernel/unwind.c *addr = *val; val 398 arch/ia64/kernel/unwind.c *val = *addr; val 401 arch/ia64/kernel/unwind.c *val = 0; /* if register is a NaT, *addr may contain kernel data! */ val 410 arch/ia64/kernel/unwind.c unw_access_br (struct unw_frame_info *info, int regnum, unsigned long *val, int write) val 438 arch/ia64/kernel/unwind.c *addr = *val; val 440 arch/ia64/kernel/unwind.c *val = *addr; val 446 arch/ia64/kernel/unwind.c unw_access_fr (struct unw_frame_info *info, int regnum, struct ia64_fpreg *val, int write) val 487 arch/ia64/kernel/unwind.c *addr = *val; val 489 arch/ia64/kernel/unwind.c *val = *addr; val 495 arch/ia64/kernel/unwind.c unw_access_ar (struct unw_frame_info *info, int regnum, unsigned long *val, int write) val 542 arch/ia64/kernel/unwind.c (*info->cfm_loc & ~(0x3fUL << 52)) | ((*val & 0x3f) << 52); val 544 arch/ia64/kernel/unwind.c *val = (*info->cfm_loc >> 52) & 0x3f; val 584 arch/ia64/kernel/unwind.c *addr = *val; val 586 arch/ia64/kernel/unwind.c *val = *addr; val 592 arch/ia64/kernel/unwind.c unw_access_pr (struct unw_frame_info *info, unsigned long *val, int write) val 605 arch/ia64/kernel/unwind.c *addr = *val; val 607 arch/ia64/kernel/unwind.c *val = *addr; val 707 arch/ia64/kernel/unwind.c set_reg (struct unw_reg_info *reg, enum unw_where where, int when, unsigned long val) val 709 arch/ia64/kernel/unwind.c reg->val = val; val 725 arch/ia64/kernel/unwind.c reg->val = *offp; val 760 arch/ia64/kernel/unwind.c reg->val = sr->gr_save_loc++; val 1095 arch/ia64/kernel/unwind.c r->val = 0; val 1116 arch/ia64/kernel/unwind.c r->val = (ytreg & 0x7f); val 1131 arch/ia64/kernel/unwind.c r->val = 0x10 - 4*pspoff; val 1146 arch/ia64/kernel/unwind.c r->val = 4*spoff; val 1362 arch/ia64/kernel/unwind.c unsigned long val = 0; val 1366 arch/ia64/kernel/unwind.c if (r->val >= 32) { val 1369 arch/ia64/kernel/unwind.c val = UNW_NAT_REGSTK; val 1377 arch/ia64/kernel/unwind.c val = UNW_NAT_VAL; val 1382 arch/ia64/kernel/unwind.c val = UNW_NAT_NONE; val 1397 arch/ia64/kernel/unwind.c insn.val = val; val 1406 arch/ia64/kernel/unwind.c unsigned long val, rval; val 1414 arch/ia64/kernel/unwind.c val = rval = r->val; val 1421 arch/ia64/kernel/unwind.c val = rval - 32; val 1427 arch/ia64/kernel/unwind.c val = unw.preg_index[UNW_REG_R4 + (rval - 4)]; val 1430 arch/ia64/kernel/unwind.c val = 0; val 1434 arch/ia64/kernel/unwind.c val = pt_regs_off(rval); val 1440 arch/ia64/kernel/unwind.c val = unw.preg_index[UNW_REG_F2 + (rval - 2)]; val 1442 arch/ia64/kernel/unwind.c val = unw.preg_index[UNW_REG_F16 + (rval - 16)]; val 1446 arch/ia64/kernel/unwind.c val = offsetof(struct pt_regs, f6) + 16*(rval - 6); val 1455 arch/ia64/kernel/unwind.c val = unw.preg_index[UNW_REG_B1 + (rval - 1)]; val 1459 arch/ia64/kernel/unwind.c val = offsetof(struct pt_regs, b0); val 1461 arch/ia64/kernel/unwind.c val = offsetof(struct pt_regs, b6); val 1463 arch/ia64/kernel/unwind.c val = offsetof(struct pt_regs, b7); val 1482 arch/ia64/kernel/unwind.c insn.val = val; val 1495 arch/ia64/kernel/unwind.c insn.dst = insn.val = unw.preg_index[UNW_REG_PSP]; val 1590 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].val = 0; val 1612 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_PSP].val = 0; val 1616 arch/ia64/kernel/unwind.c if ((r->where == UNW_WHERE_PSPREL && r->val <= 0x10) val 1619 arch/ia64/kernel/unwind.c r->val = 0; val 1634 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].val = sr.return_link_reg; val 1637 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].val); val 1647 arch/ia64/kernel/unwind.c case UNW_WHERE_GR: UNW_DPRINT(1, "r%lu", r->val); break; val 1648 arch/ia64/kernel/unwind.c case UNW_WHERE_FR: UNW_DPRINT(1, "f%lu", r->val); break; val 1649 arch/ia64/kernel/unwind.c case UNW_WHERE_BR: UNW_DPRINT(1, "b%lu", r->val); break; val 1650 arch/ia64/kernel/unwind.c case UNW_WHERE_SPREL: UNW_DPRINT(1, "[sp+0x%lx]", r->val); break; val 1651 arch/ia64/kernel/unwind.c case UNW_WHERE_PSPREL: UNW_DPRINT(1, "[psp+0x%lx]", r->val); break; val 1653 arch/ia64/kernel/unwind.c UNW_DPRINT(1, "%s+0x%lx", unw.preg_name[r - sr.curr.reg], r->val); val 1675 arch/ia64/kernel/unwind.c && sr.curr.reg[UNW_REG_PSP].val != 0) { val 1679 arch/ia64/kernel/unwind.c insn.val = sr.curr.reg[UNW_REG_PSP].val; /* frame size */ val 1723 arch/ia64/kernel/unwind.c unsigned long opc, dst, val, off; val 1736 arch/ia64/kernel/unwind.c val = next_insn.val; val 1742 arch/ia64/kernel/unwind.c s[dst] += val; val 1746 arch/ia64/kernel/unwind.c if (!s[val]) val 1748 arch/ia64/kernel/unwind.c s[dst+1] = s[val+1]; val 1749 arch/ia64/kernel/unwind.c s[dst] = s[val]; val 1753 arch/ia64/kernel/unwind.c if (!s[val]) val 1755 arch/ia64/kernel/unwind.c s[dst] = s[val]; val 1760 arch/ia64/kernel/unwind.c s[dst] = (unsigned long) get_scratch_regs(state) + val; val 1764 arch/ia64/kernel/unwind.c __func__, dst, val); val 1769 arch/ia64/kernel/unwind.c if (val == 0) val 1774 arch/ia64/kernel/unwind.c __func__, val); val 1781 arch/ia64/kernel/unwind.c val); val 1785 arch/ia64/kernel/unwind.c s[dst] = state->psp + val; val 1789 arch/ia64/kernel/unwind.c s[dst] = state->sp + val; val 1800 arch/ia64/kernel/unwind.c s[dst+1] = val; val 1805 arch/ia64/kernel/unwind.c if ((s[val] & (local_cpu_data->unimpl_va_mask | 0x7)) != 0 val 1806 arch/ia64/kernel/unwind.c || s[val] < TASK_SIZE) val 1809 arch/ia64/kernel/unwind.c __func__, s[val]); val 1813 arch/ia64/kernel/unwind.c s[dst] = *(unsigned long *) s[val]; val 1821 arch/ia64/kernel/unwind.c off = unw.sw_off[val]; val 1822 arch/ia64/kernel/unwind.c s[val] = (unsigned long) state->sw + off; val 1829 arch/ia64/kernel/unwind.c s[val+1] = (offsetof(struct switch_stack, ar_unat) - off) | UNW_NAT_MEMSTK; val 78 arch/ia64/kernel/unwind_i.h unsigned long val; /* save location: register number or offset */ val 143 arch/ia64/kernel/unwind_i.h signed int val : 19; val 117 arch/ia64/mm/tlb.c static inline void spinaphore_init(struct spinaphore *ss, int val) val 120 arch/ia64/mm/tlb.c ss->serve = val; val 486 arch/ia64/pci/pci.c int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) val 492 arch/ia64/pci/pci.c *val = inb(port); val 495 arch/ia64/pci/pci.c *val = inw(port); val 498 arch/ia64/pci/pci.c *val = inl(port); val 517 arch/ia64/pci/pci.c int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) val 523 arch/ia64/pci/pci.c outb(val, port); val 526 arch/ia64/pci/pci.c outw(val, port); val 529 arch/ia64/pci/pci.c outl(val, port); val 186 arch/m68k/atari/debug.c #define SCC_WRITE(reg, val) \ val 190 arch/m68k/atari/debug.c atari_scc.cha_b_ctrl = (val); \ val 141 arch/m68k/atari/nvram.c unsigned char val; val 193 arch/m68k/atari/nvram.c if (nvram[1] == boot_prefs[i].val) { val 95 arch/m68k/atari/time.c static void mste_read(struct MSTE_RTC *val) val 97 arch/m68k/atari/time.c #define COPY(v) val->v=(mste_rtc.v & 0xf) val 105 arch/m68k/atari/time.c } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); val 109 arch/m68k/atari/time.c static void mste_write(struct MSTE_RTC *val) val 111 arch/m68k/atari/time.c #define COPY(v) mste_rtc.v=val->v val 119 arch/m68k/atari/time.c } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); val 130 arch/m68k/atari/time.c #define RTC_WRITE(reg,val) \ val 133 arch/m68k/atari/time.c tt_rtc.data = (val); \ val 143 arch/m68k/atari/time.c struct MSTE_RTC val; val 152 arch/m68k/atari/time.c val.sec_ones = t->tm_sec % 10; val 153 arch/m68k/atari/time.c val.sec_tens = t->tm_sec / 10; val 154 arch/m68k/atari/time.c val.min_ones = t->tm_min % 10; val 155 arch/m68k/atari/time.c val.min_tens = t->tm_min / 10; val 163 arch/m68k/atari/time.c val.hr_ones = hour % 10; val 164 arch/m68k/atari/time.c val.hr_tens = hour / 10; val 165 arch/m68k/atari/time.c val.day_ones = t->tm_mday % 10; val 166 arch/m68k/atari/time.c val.day_tens = t->tm_mday / 10; val 167 arch/m68k/atari/time.c val.mon_ones = (t->tm_mon+1) % 10; val 168 arch/m68k/atari/time.c val.mon_tens = (t->tm_mon+1) / 10; val 170 arch/m68k/atari/time.c val.year_ones = year % 10; val 171 arch/m68k/atari/time.c val.year_tens = year / 10; val 172 arch/m68k/atari/time.c val.weekday = t->tm_wday; val 173 arch/m68k/atari/time.c mste_write(&val); val 175 arch/m68k/atari/time.c val.year_ones = (year % 4); /* leap year register */ val 179 arch/m68k/atari/time.c mste_read(&val); val 180 arch/m68k/atari/time.c t->tm_sec = val.sec_ones + val.sec_tens * 10; val 181 arch/m68k/atari/time.c t->tm_min = val.min_ones + val.min_tens * 10; val 182 arch/m68k/atari/time.c hour = val.hr_ones + val.hr_tens * 10; val 190 arch/m68k/atari/time.c t->tm_mday = val.day_ones + val.day_tens * 10; val 191 arch/m68k/atari/time.c t->tm_mon = val.mon_ones + val.mon_tens * 10 - 1; val 192 arch/m68k/atari/time.c t->tm_year = val.year_ones + val.year_tens * 10 + 80; val 193 arch/m68k/atari/time.c t->tm_wday = val.weekday; val 54 arch/m68k/coldfire/intc-2.c u32 val, imrbit; val 64 arch/m68k/coldfire/intc-2.c val = __raw_readl(imraddr); val 65 arch/m68k/coldfire/intc-2.c __raw_writel(val | imrbit, imraddr); val 72 arch/m68k/coldfire/intc-2.c u32 val, imrbit; val 86 arch/m68k/coldfire/intc-2.c val = __raw_readl(imraddr); val 87 arch/m68k/coldfire/intc-2.c __raw_writel(val & ~imrbit, imraddr); val 176 arch/m68k/hp300/config.c unsigned char val) val 186 arch/m68k/hp300/config.c rtc_write_data((val << 4) | reg); val 21 arch/m68k/include/asm/MC68328.h #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) val 22 arch/m68k/include/asm/MC68EZ328.h #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) val 24 arch/m68k/include/asm/MC68VZ328.h #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) val 14 arch/m68k/include/asm/hwtest.h extern int hwreg_write(volatile void *regp, unsigned short val); val 52 arch/m68k/include/asm/ide.h #define writeb(val, port) out_8(port, val) val 53 arch/m68k/include/asm/ide.h #define writew(val, port) out_be16(port, val) val 206 arch/m68k/include/asm/io_mm.h #define isa_outb(val,port) out_8(isa_itb(port),(val)) val 207 arch/m68k/include/asm/io_mm.h #define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val))) val 208 arch/m68k/include/asm/io_mm.h #define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val))) val 214 arch/m68k/include/asm/io_mm.h #define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val)) val 215 arch/m68k/include/asm/io_mm.h #define isa_writew(val,p) \ val 216 arch/m68k/include/asm/io_mm.h (ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \ val 217 arch/m68k/include/asm/io_mm.h : out_le16(isa_mtw((unsigned long)(p)),(val))) val 225 arch/m68k/include/asm/io_mm.h #define isa_rom_outb(val, port) rom_out_8(isa_itb(port), (val)) val 226 arch/m68k/include/asm/io_mm.h #define isa_rom_outw(val, port) \ val 227 arch/m68k/include/asm/io_mm.h (ISA_SEX ? rom_out_be16(isa_itw(port), (val)) \ val 228 arch/m68k/include/asm/io_mm.h : rom_out_le16(isa_itw(port), (val))) val 239 arch/m68k/include/asm/io_mm.h #define isa_rom_writeb(val, p) rom_out_8(isa_mtb((unsigned long)(p)), (val)) val 240 arch/m68k/include/asm/io_mm.h #define isa_rom_writew(val, p) \ val 241 arch/m68k/include/asm/io_mm.h (ISA_SEX ? rom_out_be16(isa_mtw((unsigned long)(p)), (val)) \ val 242 arch/m68k/include/asm/io_mm.h : rom_out_le16(isa_mtw((unsigned long)(p)), (val))) val 243 arch/m68k/include/asm/io_mm.h #define isa_rom_writew_swap(val, p) \ val 244 arch/m68k/include/asm/io_mm.h (ISA_SEX ? rom_out_le16(isa_mtw((unsigned long)(p)), (val)) \ val 245 arch/m68k/include/asm/io_mm.h : rom_out_be16(isa_mtw((unsigned long)(p)), (val))) val 246 arch/m68k/include/asm/io_mm.h #define isa_rom_writew_raw(val, p) rom_out_be16(isa_mtw((unsigned long)(p)), (val)) val 354 arch/m68k/include/asm/io_mm.h #define outb(val, port) ((port) < 1024 ? isa_rom_outb((val), (port)) : out_8((port), (val))) val 355 arch/m68k/include/asm/io_mm.h #define outb_p(val, port) ((port) < 1024 ? isa_rom_outb_p((val), (port)) : out_8((port), (val))) val 356 arch/m68k/include/asm/io_mm.h #define outw(val, port) ((port) < 1024 ? isa_rom_outw((val), (port)) : out_le16((port), (val))) val 357 arch/m68k/include/asm/io_mm.h #define outw_p(val, port) ((port) < 1024 ? isa_rom_outw_p((val), (port)) : out_le16((port), (val))) val 369 arch/m68k/include/asm/io_mm.h #define writeb(val, addr) out_8((addr), (val)) val 371 arch/m68k/include/asm/io_mm.h #define writew(val, addr) out_le16((addr), (val)) val 375 arch/m68k/include/asm/io_mm.h #define writel(val,addr) out_le32((addr),(val)) val 41 arch/m68k/include/asm/kmap.h static inline void memset_io(volatile void __iomem *addr, unsigned char val, val 44 arch/m68k/include/asm/kmap.h __builtin_memset((void __force *) addr, val, count); val 271 arch/m68k/include/asm/mac_via.h char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1; val 272 arch/m68k/include/asm/mac_via.h if (!rbv_present || val<0) return -1; val 273 arch/m68k/include/asm/mac_via.h via2[rMonP] = (via2[rMonP] & ~RBV_DEPTH) | val; val 21 arch/m68k/include/asm/mc146818rtc.h #define CMOS_WRITE(val, addr) ({ \ val 23 arch/m68k/include/asm/mc146818rtc.h atari_outb_p((val), ATARI_RTC_PORT(1)); \ val 392 arch/m68k/include/asm/mcf_pgtable.h #define __swp_type(x) ((x).val & 0xFF) val 393 arch/m68k/include/asm/mcf_pgtable.h #define __swp_offset(x) ((x).val >> 11) val 397 arch/m68k/include/asm/mcf_pgtable.h #define __swp_entry_to_pte(x) (__pte((x).val)) val 269 arch/m68k/include/asm/motorola_pgtable.h #define __swp_type(x) (((x).val >> 4) & 0xff) val 270 arch/m68k/include/asm/motorola_pgtable.h #define __swp_offset(x) ((x).val >> 12) val 273 arch/m68k/include/asm/motorola_pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 281 arch/m68k/include/asm/openprom.h int (*no_getprop)(int node, char *name, char *val); val 282 arch/m68k/include/asm/openprom.h int (*no_setprop)(int node, char *name, char *val, int len); val 39 arch/m68k/include/asm/pgtable_no.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 43 arch/m68k/include/asm/raw_io.h #define raw_outb(val,port) out_8((port),(val)) val 44 arch/m68k/include/asm/raw_io.h #define raw_outw(val,port) out_be16((port),(val)) val 45 arch/m68k/include/asm/raw_io.h #define raw_outl(val,port) out_be32((port),(val)) val 46 arch/m68k/include/asm/raw_io.h #define __raw_writeb(val,addr) out_8((addr),(val)) val 47 arch/m68k/include/asm/raw_io.h #define __raw_writew(val,addr) out_be16((addr),(val)) val 48 arch/m68k/include/asm/raw_io.h #define __raw_writel(val,addr) out_be32((addr),(val)) val 97 arch/m68k/include/asm/raw_io.h #define raw_rom_outb(val, port) rom_out_8((port), (val)) val 98 arch/m68k/include/asm/raw_io.h #define raw_rom_outw(val, port) rom_out_be16((port), (val)) val 41 arch/m68k/include/asm/segment.h static inline void set_fs(mm_segment_t val) val 45 arch/m68k/include/asm/segment.h : /* no outputs */ : "r" (val.seg) : "memory"); val 210 arch/m68k/include/asm/sun3_pgtable.h #define __swp_type(x) ((x).val & 0x7F) val 211 arch/m68k/include/asm/sun3_pgtable.h #define __swp_offset(x) (((x).val) >> 7) val 214 arch/m68k/include/asm/sun3_pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 168 arch/m68k/include/asm/sun3mmu.h extern int sun3_map_test(unsigned long addr, char *val); val 30 arch/m68k/include/asm/vga.h #define outb_p(port, val) do { } while (0) val 31 arch/m68k/include/asm/vga.h #define outw(port, val) do { } while (0) val 11 arch/m68k/include/uapi/asm/swab.h static inline __attribute_const__ __u32 __arch_swab32(__u32 val) val 13 arch/m68k/include/uapi/asm/swab.h __asm__("byterev %0" : "=d" (val) : "0" (val)); val 14 arch/m68k/include/uapi/asm/swab.h return val; val 20 arch/m68k/include/uapi/asm/swab.h static inline __attribute_const__ __u32 __arch_swab32(__u32 val) val 22 arch/m68k/include/uapi/asm/swab.h __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val)); val 23 arch/m68k/include/uapi/asm/swab.h return val; val 562 arch/m68k/kernel/setup_mm.c static void m68k_nvram_write_byte(unsigned char val, int addr) val 565 arch/m68k/kernel/setup_mm.c mac_pram_write_byte(val, addr); val 401 arch/m68k/mac/misc.c void mac_pram_write_byte(unsigned char val, int addr) val 407 arch/m68k/mac/misc.c via_pram_write_byte(val, addr); val 412 arch/m68k/mac/misc.c cuda_pram_write_byte(val, addr); val 417 arch/m68k/mac/misc.c pmu_pram_write_byte(val, addr); val 62 arch/m68k/mm/hwtest.c int hwreg_write(volatile void *regp, unsigned short val) val 87 arch/m68k/mm/hwtest.c : "a" (regp), "a" (tmp_vectors), "g" (val) val 136 arch/m68k/mm/sun3kmap.c int sun3_map_test(unsigned long addr, char *val) val 157 arch/m68k/mm/sun3kmap.c : "=a"(val), "=r"(ret) val 76 arch/m68k/sun3/mmu_emu.c unsigned long val = pte_val (pte); val 78 arch/m68k/sun3/mmu_emu.c val, (val & SUN3_PAGE_PGNUM_MASK) << PAGE_SHIFT); val 79 arch/m68k/sun3/mmu_emu.c if (val & SUN3_PAGE_VALID) pr_cont(" valid"); val 80 arch/m68k/sun3/mmu_emu.c if (val & SUN3_PAGE_WRITEABLE) pr_cont(" write"); val 81 arch/m68k/sun3/mmu_emu.c if (val & SUN3_PAGE_SYSTEM) pr_cont(" sys"); val 82 arch/m68k/sun3/mmu_emu.c if (val & SUN3_PAGE_NOCACHE) pr_cont(" nocache"); val 83 arch/m68k/sun3/mmu_emu.c if (val & SUN3_PAGE_ACCESSED) pr_cont(" accessed"); val 84 arch/m68k/sun3/mmu_emu.c if (val & SUN3_PAGE_MODIFIED) pr_cont(" modified"); val 85 arch/m68k/sun3/mmu_emu.c switch (val & SUN3_PAGE_TYPE_MASK) { val 94 arch/m68k/sun3/mmu_emu.c unsigned long val = pte_val (pte); val 97 arch/m68k/sun3/mmu_emu.c flags[0] = (val & SUN3_PAGE_VALID) ? 'v' : '-'; val 98 arch/m68k/sun3/mmu_emu.c flags[1] = (val & SUN3_PAGE_WRITEABLE) ? 'w' : '-'; val 99 arch/m68k/sun3/mmu_emu.c flags[2] = (val & SUN3_PAGE_SYSTEM) ? 's' : '-'; val 100 arch/m68k/sun3/mmu_emu.c flags[3] = (val & SUN3_PAGE_NOCACHE) ? 'x' : '-'; val 101 arch/m68k/sun3/mmu_emu.c flags[4] = (val & SUN3_PAGE_ACCESSED) ? 'a' : '-'; val 102 arch/m68k/sun3/mmu_emu.c flags[5] = (val & SUN3_PAGE_MODIFIED) ? 'm' : '-'; val 105 arch/m68k/sun3/mmu_emu.c switch (val & SUN3_PAGE_TYPE_MASK) { val 114 arch/m68k/sun3/mmu_emu.c val, (val & SUN3_PAGE_PGNUM_MASK) << PAGE_SHIFT, flags, type); val 101 arch/microblaze/include/asm/cpuinfo.h u32 val = 0; val 103 arch/microblaze/include/asm/cpuinfo.h of_property_read_u32(cpu, n, &val); val 105 arch/microblaze/include/asm/cpuinfo.h return val; val 109 arch/microblaze/include/asm/pci-bridge.h int dev_fn, int where, u8 *val); val 111 arch/microblaze/include/asm/pci-bridge.h int dev_fn, int where, u16 *val); val 113 arch/microblaze/include/asm/pci-bridge.h int dev_fn, int where, u32 *val); val 115 arch/microblaze/include/asm/pci-bridge.h int dev_fn, int where, u8 val); val 117 arch/microblaze/include/asm/pci-bridge.h int dev_fn, int where, u16 val); val 119 arch/microblaze/include/asm/pci-bridge.h int dev_fn, int where, u32 val); val 51 arch/microblaze/include/asm/pci.h extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, val 53 arch/microblaze/include/asm/pci.h extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, val 43 arch/microblaze/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 506 arch/microblaze/include/asm/pgtable.h #define __swp_type(entry) ((entry).val & 0x3f) val 507 arch/microblaze/include/asm/pgtable.h #define __swp_offset(entry) ((entry).val >> 6) val 511 arch/microblaze/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 }) val 37 arch/microblaze/include/asm/syscall.h int error, long val) val 42 arch/microblaze/include/asm/syscall.h regs->r3 = val; val 63 arch/microblaze/include/asm/syscall.h unsigned long val) val 67 arch/microblaze/include/asm/syscall.h regs->r10 = val; val 69 arch/microblaze/include/asm/syscall.h regs->r9 = val; val 71 arch/microblaze/include/asm/syscall.h regs->r8 = val; val 73 arch/microblaze/include/asm/syscall.h regs->r7 = val; val 75 arch/microblaze/include/asm/syscall.h regs->r6 = val; val 77 arch/microblaze/include/asm/syscall.h regs->r5 = val; val 46 arch/microblaze/include/asm/uaccess.h # define set_fs(val) (current_thread_info()->addr_limit = (val)) val 24 arch/microblaze/kernel/cpu/pvr.c #define get_single_pvr(pvrid, val) \ val 31 arch/microblaze/kernel/cpu/pvr.c val = tmp; \ val 82 arch/microblaze/kernel/ptrace.c unsigned long val = 0; val 96 arch/microblaze/kernel/ptrace.c val = child->mm->start_code; val 98 arch/microblaze/kernel/ptrace.c val = child->mm->start_data; val 100 arch/microblaze/kernel/ptrace.c val = child->mm->end_code val 108 arch/microblaze/kernel/ptrace.c val = *reg_addr; val 128 arch/microblaze/kernel/ptrace.c rval = put_user(val, (unsigned long __user *)data); val 51 arch/microblaze/kernel/timer.c static void timer_write32(u32 val, void __iomem *addr) val 53 arch/microblaze/kernel/timer.c iowrite32(val, addr); val 61 arch/microblaze/kernel/timer.c static void timer_write32_be(u32 val, void __iomem *addr) val 63 arch/microblaze/kernel/timer.c iowrite32be(val, addr); val 19 arch/microblaze/pci/indirect_pci.c int len, u32 *val) val 59 arch/microblaze/pci/indirect_pci.c *val = in_8(cfg_data); val 62 arch/microblaze/pci/indirect_pci.c *val = in_le16(cfg_data); val 65 arch/microblaze/pci/indirect_pci.c *val = in_le32(cfg_data); val 73 arch/microblaze/pci/indirect_pci.c int len, u32 val) val 110 arch/microblaze/pci/indirect_pci.c val &= 0xffffff00; val 115 arch/microblaze/pci/indirect_pci.c val = 0; val 125 arch/microblaze/pci/indirect_pci.c out_8(cfg_data, val); val 128 arch/microblaze/pci/indirect_pci.c out_le16(cfg_data, val); val 131 arch/microblaze/pci/indirect_pci.c out_le32(cfg_data, val); val 218 arch/microblaze/pci/pci-common.c int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) val 241 arch/microblaze/pci/pci-common.c *((u8 *)val) = in_8(addr); val 246 arch/microblaze/pci/pci-common.c *((u16 *)val) = in_le16(addr); val 251 arch/microblaze/pci/pci-common.c *((u32 *)val) = in_le32(addr); val 258 arch/microblaze/pci/pci-common.c int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) val 286 arch/microblaze/pci/pci-common.c out_8(addr, val >> 24); val 291 arch/microblaze/pci/pci-common.c out_le16(addr, val >> 16); val 296 arch/microblaze/pci/pci-common.c out_le32(addr, val); val 1062 arch/microblaze/pci/pci-common.c null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ val 1069 arch/microblaze/pci/pci-common.c int len, u32 *val) val 1076 arch/microblaze/pci/pci-common.c int len, u32 val) val 88 arch/microblaze/pci/xilinx_pci.c u32 val, dev, func, offset; val 99 arch/microblaze/pci/xilinx_pci.c PCI_DEVFN(dev, func), offset, &val); val 100 arch/microblaze/pci/xilinx_pci.c if (offset == 0 && val == 0xFFFFFFFF) { val 107 arch/microblaze/pci/xilinx_pci.c pr_cont("%08x ", val); val 62 arch/mips/alchemy/devboards/bcsr.c void bcsr_write(enum bcsr_id reg, unsigned short val) val 67 arch/mips/alchemy/devboards/bcsr.c __raw_writew(val, bcsr_regs[reg].raddr); val 641 arch/mips/ar7/platform.c u32 val; val 706 arch/mips/ar7/platform.c val = readl(bootcr); val 708 arch/mips/ar7/platform.c if (val & AR7_WDT_HW_ENA) { val 42 arch/mips/ath25/ar2315.c static inline void ar2315_rst_reg_write(u32 reg, u32 val) val 44 arch/mips/ath25/ar2315.c __raw_writel(val, ar2315_rst_base + reg); val 47 arch/mips/ath25/ar2315.c static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val) val 52 arch/mips/ath25/ar2315.c ret |= val; val 43 arch/mips/ath25/ar5312.c static inline void ar5312_rst_reg_write(u32 reg, u32 val) val 45 arch/mips/ath25/ar5312.c __raw_writel(val, ar5312_rst_base + reg); val 48 arch/mips/ath25/ar5312.c static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val) val 53 arch/mips/ath25/ar5312.c ret |= val; val 21 arch/mips/ath79/early_printk.c static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) val 27 arch/mips/ath79/early_printk.c if ((t & mask) == val) val 750 arch/mips/bcm63xx/boards/board_bcm963xx.c u32 val; val 757 arch/mips/bcm63xx/boards/board_bcm963xx.c val = 0x18000000; val 759 arch/mips/bcm63xx/boards/board_bcm963xx.c val = bcm_mpi_readl(MPI_CSBASE_REG(0)); val 760 arch/mips/bcm63xx/boards/board_bcm963xx.c val &= MPI_CSBASE_BASE_MASK; val 762 arch/mips/bcm63xx/boards/board_bcm963xx.c boot_addr = (u8 *)KSEG1ADDR(val); val 802 arch/mips/bcm63xx/boards/board_bcm963xx.c val = 0; val 808 arch/mips/bcm63xx/boards/board_bcm963xx.c val |= GPIO_MODE_6348_G2_PCI; val 814 arch/mips/bcm63xx/boards/board_bcm963xx.c val |= GPIO_MODE_6348_G1_MII_PCCARD; val 819 arch/mips/bcm63xx/boards/board_bcm963xx.c val |= GPIO_MODE_6348_G3_EXT_MII | val 825 arch/mips/bcm63xx/boards/board_bcm963xx.c val |= GPIO_MODE_6348_G3_EXT_MII | val 829 arch/mips/bcm63xx/boards/board_bcm963xx.c bcm_gpio_writel(val, GPIO_MODE_REG); val 259 arch/mips/bcm63xx/cpu.c u32 val; val 265 arch/mips/bcm63xx/cpu.c val = bcm_sdram_readl(SDRAM_MBASE_REG); val 266 arch/mips/bcm63xx/cpu.c return val * 8 * 1024 * 1024; val 270 arch/mips/bcm63xx/cpu.c val = bcm_sdram_readl(SDRAM_CFG_REG); val 271 arch/mips/bcm63xx/cpu.c rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; val 272 arch/mips/bcm63xx/cpu.c cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; val 273 arch/mips/bcm63xx/cpu.c is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; val 274 arch/mips/bcm63xx/cpu.c banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; val 278 arch/mips/bcm63xx/cpu.c val = bcm_memc_readl(MEMC_CFG_REG); val 279 arch/mips/bcm63xx/cpu.c rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; val 280 arch/mips/bcm63xx/cpu.c cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; val 281 arch/mips/bcm63xx/cpu.c is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1; val 38 arch/mips/bcm63xx/cs.c u32 val; val 50 arch/mips/bcm63xx/cs.c val = (base & MPI_CSBASE_BASE_MASK); val 52 arch/mips/bcm63xx/cs.c val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT; val 55 arch/mips/bcm63xx/cs.c bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); val 70 arch/mips/bcm63xx/cs.c u32 val; val 76 arch/mips/bcm63xx/cs.c val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); val 77 arch/mips/bcm63xx/cs.c val &= ~(MPI_CSCTL_WAIT_MASK); val 78 arch/mips/bcm63xx/cs.c val &= ~(MPI_CSCTL_SETUP_MASK); val 79 arch/mips/bcm63xx/cs.c val &= ~(MPI_CSCTL_HOLD_MASK); val 80 arch/mips/bcm63xx/cs.c val |= wait << MPI_CSCTL_WAIT_SHIFT; val 81 arch/mips/bcm63xx/cs.c val |= setup << MPI_CSCTL_SETUP_SHIFT; val 82 arch/mips/bcm63xx/cs.c val |= hold << MPI_CSCTL_HOLD_SHIFT; val 83 arch/mips/bcm63xx/cs.c bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); val 97 arch/mips/bcm63xx/cs.c u32 val; val 109 arch/mips/bcm63xx/cs.c val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); val 110 arch/mips/bcm63xx/cs.c val &= ~(MPI_CSCTL_DATA16_MASK); val 111 arch/mips/bcm63xx/cs.c val &= ~(MPI_CSCTL_SYNCMODE_MASK); val 112 arch/mips/bcm63xx/cs.c val &= ~(MPI_CSCTL_TSIZE_MASK); val 113 arch/mips/bcm63xx/cs.c val &= ~(MPI_CSCTL_ENDIANSWAP_MASK); val 114 arch/mips/bcm63xx/cs.c val |= params; val 115 arch/mips/bcm63xx/cs.c bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); val 129 arch/mips/bcm63xx/cs.c u32 val; val 135 arch/mips/bcm63xx/cs.c val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); val 137 arch/mips/bcm63xx/cs.c val |= MPI_CSCTL_ENABLE_MASK; val 139 arch/mips/bcm63xx/cs.c val &= ~MPI_CSCTL_ENABLE_MASK; val 140 arch/mips/bcm63xx/cs.c bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); val 60 arch/mips/bcm63xx/dev-flash.c u32 val; val 64 arch/mips/bcm63xx/dev-flash.c val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); val 65 arch/mips/bcm63xx/dev-flash.c if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) val 76 arch/mips/bcm63xx/dev-flash.c val = bcm_gpio_readl(GPIO_STRAPBUS_REG); val 77 arch/mips/bcm63xx/dev-flash.c if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) val 82 arch/mips/bcm63xx/dev-flash.c val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); val 83 arch/mips/bcm63xx/dev-flash.c if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) val 88 arch/mips/bcm63xx/dev-flash.c val = bcm_gpio_readl(GPIO_STRAPBUS_REG); val 89 arch/mips/bcm63xx/dev-flash.c switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { val 106 arch/mips/bcm63xx/dev-flash.c u32 val; val 113 arch/mips/bcm63xx/dev-flash.c val = bcm_mpi_readl(MPI_CSBASE_REG(0)); val 114 arch/mips/bcm63xx/dev-flash.c val &= MPI_CSBASE_BASE_MASK; val 116 arch/mips/bcm63xx/dev-flash.c mtd_resources[0].start = val; val 15 arch/mips/bcm63xx/early_printk.c unsigned int val; val 19 arch/mips/bcm63xx/early_printk.c val = bcm_uart0_readl(UART_IR_REG); val 20 arch/mips/bcm63xx/early_printk.c if (val & UART_IR_STAT(UART_IR_TXEMPTY)) val 39 arch/mips/bcm63xx/gpio.c unsigned gpio, int val) val 60 arch/mips/bcm63xx/gpio.c if (val) val 87 arch/mips/bcm63xx/irq.c u32 val; \ val 89 arch/mips/bcm63xx/irq.c val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \ val 90 arch/mips/bcm63xx/irq.c val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \ val 91 arch/mips/bcm63xx/irq.c pending[--tgt] = val; \ val 93 arch/mips/bcm63xx/irq.c if (val) \ val 114 arch/mips/bcm63xx/irq.c u32 val; \ val 126 arch/mips/bcm63xx/irq.c val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ val 127 arch/mips/bcm63xx/irq.c val &= ~(1 << bit); \ val 128 arch/mips/bcm63xx/irq.c bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ val 136 arch/mips/bcm63xx/irq.c u32 val; \ val 148 arch/mips/bcm63xx/irq.c val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ val 150 arch/mips/bcm63xx/irq.c val |= (1 << bit); \ val 152 arch/mips/bcm63xx/irq.c val &= ~(1 << bit); \ val 153 arch/mips/bcm63xx/irq.c bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ val 196 arch/mips/bcm63xx/reset.c u32 val; val 202 arch/mips/bcm63xx/reset.c val = bcm_perf_readl(reset_reg); val 205 arch/mips/bcm63xx/reset.c val &= ~mask; val 207 arch/mips/bcm63xx/reset.c val |= mask; val 209 arch/mips/bcm63xx/reset.c bcm_perf_writel(val, reset_reg); val 26 arch/mips/boot/compressed/dbg.c void puthex(unsigned long long val) val 32 arch/mips/boot/compressed/dbg.c buf[i] = "0123456789ABCDEF"[val & 0x0F]; val 33 arch/mips/boot/compressed/dbg.c val >>= 4; val 30 arch/mips/boot/compressed/decompress.c extern void puthex(unsigned long long val); val 33 arch/mips/boot/compressed/decompress.c #define puthex(val) do {} while (0) val 131 arch/mips/boot/tools/relocs.c #define le16_to_cpu(val) (val) val 132 arch/mips/boot/tools/relocs.c #define le32_to_cpu(val) (val) val 133 arch/mips/boot/tools/relocs.c #define le64_to_cpu(val) (val) val 134 arch/mips/boot/tools/relocs.c #define be16_to_cpu(val) bswap_16(val) val 135 arch/mips/boot/tools/relocs.c #define be32_to_cpu(val) bswap_32(val) val 136 arch/mips/boot/tools/relocs.c #define be64_to_cpu(val) bswap_64(val) val 138 arch/mips/boot/tools/relocs.c #define cpu_to_le16(val) (val) val 139 arch/mips/boot/tools/relocs.c #define cpu_to_le32(val) (val) val 140 arch/mips/boot/tools/relocs.c #define cpu_to_le64(val) (val) val 141 arch/mips/boot/tools/relocs.c #define cpu_to_be16(val) bswap_16(val) val 142 arch/mips/boot/tools/relocs.c #define cpu_to_be32(val) bswap_32(val) val 143 arch/mips/boot/tools/relocs.c #define cpu_to_be64(val) bswap_64(val) val 146 arch/mips/boot/tools/relocs.c #define le16_to_cpu(val) bswap_16(val) val 147 arch/mips/boot/tools/relocs.c #define le32_to_cpu(val) bswap_32(val) val 148 arch/mips/boot/tools/relocs.c #define le64_to_cpu(val) bswap_64(val) val 149 arch/mips/boot/tools/relocs.c #define be16_to_cpu(val) (val) val 150 arch/mips/boot/tools/relocs.c #define be32_to_cpu(val) (val) val 151 arch/mips/boot/tools/relocs.c #define be64_to_cpu(val) (val) val 153 arch/mips/boot/tools/relocs.c #define cpu_to_le16(val) bswap_16(val) val 154 arch/mips/boot/tools/relocs.c #define cpu_to_le32(val) bswap_32(val) val 155 arch/mips/boot/tools/relocs.c #define cpu_to_le64(val) bswap_64(val) val 156 arch/mips/boot/tools/relocs.c #define cpu_to_be16(val) (val) val 157 arch/mips/boot/tools/relocs.c #define cpu_to_be32(val) (val) val 158 arch/mips/boot/tools/relocs.c #define cpu_to_be64(val) (val) val 161 arch/mips/boot/tools/relocs.c static uint16_t elf16_to_cpu(uint16_t val) val 164 arch/mips/boot/tools/relocs.c return le16_to_cpu(val); val 166 arch/mips/boot/tools/relocs.c return be16_to_cpu(val); val 169 arch/mips/boot/tools/relocs.c static uint32_t elf32_to_cpu(uint32_t val) val 172 arch/mips/boot/tools/relocs.c return le32_to_cpu(val); val 174 arch/mips/boot/tools/relocs.c return be32_to_cpu(val); val 177 arch/mips/boot/tools/relocs.c static uint32_t cpu_to_elf32(uint32_t val) val 180 arch/mips/boot/tools/relocs.c return cpu_to_le32(val); val 182 arch/mips/boot/tools/relocs.c return cpu_to_be32(val); val 189 arch/mips/boot/tools/relocs.c static uint64_t elf64_to_cpu(uint64_t val) val 192 arch/mips/boot/tools/relocs.c return le64_to_cpu(val); val 194 arch/mips/boot/tools/relocs.c return be64_to_cpu(val); val 12 arch/mips/boot/tools/relocs_32.c #define ELF_R_SYM(val) ELF32_R_SYM(val) val 13 arch/mips/boot/tools/relocs_32.c #define ELF_R_TYPE(val) ELF32_R_TYPE(val) val 25 arch/mips/boot/tools/relocs_64.c #define ELF_R_SYM(val) (((Elf64_Mips_Rela *)(&val))->fields.r_sym) val 26 arch/mips/boot/tools/relocs_64.c #define ELF_R_TYPE(val) (((Elf64_Mips_Rela *)(&val))->fields.r_type) val 2269 arch/mips/cavium-octeon/octeon-irq.c u32 val; val 2303 arch/mips/cavium-octeon/octeon-irq.c r = of_property_read_u32(ciu_node, "cavium,max-bits", &val); val 2309 arch/mips/cavium-octeon/octeon-irq.c host_data->max_bits = val; val 38 arch/mips/emma/markeins/led.c void markeins_led_hex(u32 val) val 42 arch/mips/emma/markeins/led.c sprintf(str, "%08x", val); val 106 arch/mips/emma/markeins/setup.c u32 val; val 108 arch/mips/emma/markeins/setup.c val = emma2rh_in32(EMMA2RH_PBRD_INT_EN); /* open serial interrupts. */ val 109 arch/mips/emma/markeins/setup.c emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa); val 110 arch/mips/emma/markeins/setup.c val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL); /* set serial clocks. */ val 111 arch/mips/emma/markeins/setup.c emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5); /* 18MHz */ val 106 arch/mips/fw/cfe/cfe_api.c int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) val 118 arch/mips/fw/cfe/cfe_api.c xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); val 376 arch/mips/fw/cfe/cfe_api.c int cfe_setenv(char *name, char *val) val 388 arch/mips/fw/cfe/cfe_api.c xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); val 389 arch/mips/fw/cfe/cfe_api.c xiocb.plist.xiocb_envbuf.val_length = strlen(val); val 44 arch/mips/include/asm/cmpxchg.h #define __xchg_asm(ld, st, m, val) \ val 63 arch/mips/include/asm/cmpxchg.h : GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \ val 70 arch/mips/include/asm/cmpxchg.h *m = val; \ val 77 arch/mips/include/asm/cmpxchg.h extern unsigned long __xchg_small(volatile void *ptr, unsigned long val, val 27 arch/mips/include/asm/compat.h s32 val[2]; val 60 arch/mips/include/asm/cop2.h extern int cu2_notifier_call_chain(unsigned long val, void *v); val 125 arch/mips/include/asm/cpu-info.h extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v); val 118 arch/mips/include/asm/emma/emma2rh.h static inline void emma2rh_out32(u32 offset, u32 val) val 120 arch/mips/include/asm/emma/emma2rh.h *(volatile u32 *)(EMMA2RH_BASE | offset) = val; val 126 arch/mips/include/asm/emma/emma2rh.h u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); val 127 arch/mips/include/asm/emma/emma2rh.h return val; val 130 arch/mips/include/asm/emma/emma2rh.h static inline void emma2rh_out16(u32 offset, u16 val) val 132 arch/mips/include/asm/emma/emma2rh.h *(volatile u16 *)(EMMA2RH_BASE | offset) = val; val 138 arch/mips/include/asm/emma/emma2rh.h u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); val 139 arch/mips/include/asm/emma/emma2rh.h return val; val 142 arch/mips/include/asm/emma/emma2rh.h static inline void emma2rh_out8(u32 offset, u8 val) val 144 arch/mips/include/asm/emma/emma2rh.h *(volatile u8 *)(EMMA2RH_BASE | offset) = val; val 150 arch/mips/include/asm/emma/emma2rh.h u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); val 151 arch/mips/include/asm/emma/emma2rh.h return val; val 131 arch/mips/include/asm/futex.h u32 val; val 162 arch/mips/include/asm/futex.h : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr) val 193 arch/mips/include/asm/futex.h : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr) val 201 arch/mips/include/asm/futex.h *uval = val; val 87 arch/mips/include/asm/fw/cfe/cfe_api.h int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); val 104 arch/mips/include/asm/fw/cfe/cfe_api.h int cfe_setenv(char *name, char *val); val 62 arch/mips/include/asm/hugetlb.h unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL; val 63 arch/mips/include/asm/hugetlb.h return !val || (val == (unsigned long)invalid_pte_table); val 317 arch/mips/include/asm/io.h static inline void pfx##write##bwlq(type val, \ val 330 arch/mips/include/asm/io.h __val = pfx##ioswab##bwlq(__mem, val); \ val 398 arch/mips/include/asm/io.h static inline void pfx##out##bwlq##p(type val, unsigned long port) \ val 410 arch/mips/include/asm/io.h __val = pfx##ioswab##bwlq(__addr, val); \ val 503 arch/mips/include/asm/io.h #define writeb_be(val, addr) \ val 504 arch/mips/include/asm/io.h __raw_writeb((val), (__force unsigned *)(addr)) val 505 arch/mips/include/asm/io.h #define writew_be(val, addr) \ val 506 arch/mips/include/asm/io.h __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) val 507 arch/mips/include/asm/io.h #define writel_be(val, addr) \ val 508 arch/mips/include/asm/io.h __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) val 509 arch/mips/include/asm/io.h #define writeq_be(val, addr) \ val 510 arch/mips/include/asm/io.h __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) val 580 arch/mips/include/asm/io.h static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) val 582 arch/mips/include/asm/io.h memset((void __force *) addr, val, count); val 290 arch/mips/include/asm/jazz.h static inline void r4030_write_reg16(unsigned long addr, unsigned val) val 292 arch/mips/include/asm/jazz.h *((volatile unsigned short *)addr) = val; val 296 arch/mips/include/asm/jazz.h static inline void r4030_write_reg32(unsigned long addr, unsigned val) val 298 arch/mips/include/asm/jazz.h *((volatile unsigned int *)addr) = val; val 75 arch/mips/include/asm/kprobes.h unsigned long val, void *data); val 413 arch/mips/include/asm/kvm_host.h unsigned long val) val 425 arch/mips/include/asm/kvm_host.h : "r" (val)); val 430 arch/mips/include/asm/kvm_host.h unsigned long val) val 442 arch/mips/include/asm/kvm_host.h : "r" (~val)); val 448 arch/mips/include/asm/kvm_host.h unsigned long val) val 461 arch/mips/include/asm/kvm_host.h : "r" (~change), "r" (val & change)); val 481 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 483 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] = val; \ val 489 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 491 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val; \ val 494 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 496 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] &= ~val; \ val 500 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 504 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val & _mask; \ val 510 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 512 arch/mips/include/asm/kvm_host.h _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ val 515 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 517 arch/mips/include/asm/kvm_host.h _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ val 521 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 524 arch/mips/include/asm/kvm_host.h val); \ val 539 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 541 arch/mips/include/asm/kvm_host.h write_gc0_##name(val); \ val 547 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 549 arch/mips/include/asm/kvm_host.h set_gc0_##name(val); \ val 552 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 554 arch/mips/include/asm/kvm_host.h clear_gc0_##name(val); \ val 558 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 560 arch/mips/include/asm/kvm_host.h change_gc0_##name(mask, val); \ val 586 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 588 arch/mips/include/asm/kvm_host.h kvm_write_##name2(cop0, val); \ val 594 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 596 arch/mips/include/asm/kvm_host.h kvm_set_##name2(cop0, val); \ val 599 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 601 arch/mips/include/asm/kvm_host.h kvm_clear_##name2(cop0, val); \ val 605 arch/mips/include/asm/kvm_host.h __KVMT##type val) \ val 607 arch/mips/include/asm/kvm_host.h kvm_change_##name2(cop0, mask, val); \ val 123 arch/mips/include/asm/mach-ar7/ar7.h unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + val 125 arch/mips/include/asm/mach-ar7/ar7.h return ((val >> 12) & 0x0f); val 154 arch/mips/include/asm/mach-ath79/ath79.h static inline void ath79_pll_wr(unsigned reg, u32 val) val 156 arch/mips/include/asm/mach-ath79/ath79.h __raw_writel(val, ath79_pll_base + reg); val 164 arch/mips/include/asm/mach-ath79/ath79.h static inline void ath79_reset_wr(unsigned reg, u32 val) val 166 arch/mips/include/asm/mach-ath79/ath79.h __raw_writel(val, ath79_reset_base + reg); val 42 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h int phy_id, int reg, int val)); val 253 arch/mips/include/asm/mach-db1x00/bcsr.h void bcsr_write(enum bcsr_id reg, unsigned short val); val 15 arch/mips/include/asm/mach-lantiq/lantiq.h #define ltq_w32(val, reg) __raw_writel(val, reg) val 19 arch/mips/include/asm/mach-lantiq/lantiq.h #define ltq_w8(val, reg) __raw_writeb(val, reg) val 84 arch/mips/include/asm/mach-pnx833x/gpio.h static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin) val 87 arch/mips/include/asm/mach-pnx833x/gpio.h if (val) val 92 arch/mips/include/asm/mach-pnx833x/gpio.h if (val) val 20 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) val 24 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX_FIELD(cpu, val, reg, field) \ val 25 arch/mips/include/asm/mach-pnx833x/pnx833x.h (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ val 27 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) val 28 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) val 29 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) val 37 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX_WRITEFIELD(cpu, val, reg, field) \ val 39 arch/mips/include/asm/mach-pnx833x/pnx833x.h ((val) << PNX##cpu##_##reg##_##field##_SHIFT)) val 40 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX833X_WRITEFIELD(val, reg, field) \ val 41 arch/mips/include/asm/mach-pnx833x/pnx833x.h PNX_WRITEFIELD(833X, val, reg, field) val 42 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8330_WRITEFIELD(val, reg, field) \ val 43 arch/mips/include/asm/mach-pnx833x/pnx833x.h PNX_WRITEFIELD(8330, val, reg, field) val 44 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8335_WRITEFIELD(val, reg, field) \ val 45 arch/mips/include/asm/mach-pnx833x/pnx833x.h PNX_WRITEFIELD(8335, val, reg, field) val 35 arch/mips/include/asm/mach-ralink/ralink_regs.h static inline void rt_sysc_w32(u32 val, unsigned reg) val 37 arch/mips/include/asm/mach-ralink/ralink_regs.h __raw_writel(val, rt_sysc_membase + reg); val 47 arch/mips/include/asm/mach-ralink/ralink_regs.h u32 val = rt_sysc_r32(reg) & ~clr; val 49 arch/mips/include/asm/mach-ralink/ralink_regs.h __raw_writel(val | set, rt_sysc_membase + reg); val 52 arch/mips/include/asm/mach-ralink/ralink_regs.h static inline void rt_memc_w32(u32 val, unsigned reg) val 54 arch/mips/include/asm/mach-ralink/ralink_regs.h __raw_writel(val, rt_memc_membase + reg); val 46 arch/mips/include/asm/mips-cps.h static inline void write_##unit##_##name(uint##sz##_t val) \ val 50 arch/mips/include/asm/mips-cps.h __raw_writel(val, addr_##unit##_##name()); \ val 55 arch/mips/include/asm/mips-cps.h __raw_writeq(val, addr_##unit##_##name()); \ val 59 arch/mips/include/asm/mips-cps.h __raw_writel((uint64_t)val >> 32, \ val 61 arch/mips/include/asm/mips-cps.h __raw_writel(val, addr_##unit##_##name()); \ val 72 arch/mips/include/asm/mips-cps.h uint##sz##_t val) \ val 76 arch/mips/include/asm/mips-cps.h reg_val |= val; \ val 80 arch/mips/include/asm/mips-cps.h static inline void set_##unit##_##name(uint##sz##_t val) \ val 82 arch/mips/include/asm/mips-cps.h change_##unit##_##name(val, val); \ val 85 arch/mips/include/asm/mips-cps.h static inline void clear_##unit##_##name(uint##sz##_t val) \ val 87 arch/mips/include/asm/mips-cps.h change_##unit##_##name(val, 0); \ val 65 arch/mips/include/asm/mips-gic.h unsigned int val) \ val 68 arch/mips/include/asm/mips-gic.h __raw_writel(val, addr_gic_##name(intr)); \ val 95 arch/mips/include/asm/mips-gic.h unsigned int val; \ val 99 arch/mips/include/asm/mips-gic.h val = __raw_readq(addr) >> intr % 64; \ val 102 arch/mips/include/asm/mips-gic.h val = __raw_readl(addr) >> intr % 32; \ val 105 arch/mips/include/asm/mips-gic.h return val & 0x1; \ val 126 arch/mips/include/asm/mips-gic.h unsigned int val) \ val 136 arch/mips/include/asm/mips-gic.h _val |= (uint64_t)val << (intr % 64); \ val 144 arch/mips/include/asm/mips-gic.h _val |= val << (intr % 32); \ val 21 arch/mips/include/asm/mipsmtregs.h #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) val 27 arch/mips/include/asm/mipsmtregs.h #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) val 30 arch/mips/include/asm/mipsmtregs.h #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) val 33 arch/mips/include/asm/mipsmtregs.h #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) val 36 arch/mips/include/asm/mipsmtregs.h #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) val 40 arch/mips/include/asm/mipsmtregs.h #define write_c0_tchalt(val) __write_32bit_c0_register($2, 4, val) val 43 arch/mips/include/asm/mipsmtregs.h #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) val 376 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) val 378 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) val 380 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) val 382 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_count(val) mttc0(9, 0, val) val 384 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_status(val) mttc0(12, 0, val) val 386 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_cause(val) mttc0(13, 0, val) val 388 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_config(val) mttc0(16, 0, val) val 390 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_config1(val) mttc0(16, 1, val) val 392 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_config7(val) mttc0(16, 7, val) val 394 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_ebase(val) mttc0(15, 1, val) val 395 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_compare(val) mttc0(11, 0, val) val 398 arch/mips/include/asm/mipsmtregs.h #define write_vpe_c0_epc(val) mttc0(14, 0, val) val 403 arch/mips/include/asm/mipsmtregs.h #define write_tc_c0_tcstatus(val) mttc0(2, 1, val) val 405 arch/mips/include/asm/mipsmtregs.h #define write_tc_c0_tcbind(val) mttc0(2, 2, val) val 407 arch/mips/include/asm/mipsmtregs.h #define write_tc_c0_tcrestart(val) mttc0(2, 3, val) val 409 arch/mips/include/asm/mipsmtregs.h #define write_tc_c0_tchalt(val) mttc0(2, 4, val) val 411 arch/mips/include/asm/mipsmtregs.h #define write_tc_c0_tccontext(val) mttc0(2, 5, val) val 415 arch/mips/include/asm/mipsmtregs.h #define write_tc_gpr_sp(val) mttgpr(29, val) val 417 arch/mips/include/asm/mipsmtregs.h #define write_tc_gpr_gp(val) mttgpr(28, val) val 1319 arch/mips/include/asm/mipsregs.h #define write_r10k_perf_cntr(counter,val) \ val 1324 arch/mips/include/asm/mipsregs.h : "r" (val), "i" (counter)); \ val 1338 arch/mips/include/asm/mipsregs.h #define write_r10k_perf_cntl(counter,val) \ val 1343 arch/mips/include/asm/mipsregs.h : "r" (val), "i" (counter)); \ val 1445 arch/mips/include/asm/mipsregs.h #define __write_ulong_c0_register(reg, sel, val) \ val 1448 arch/mips/include/asm/mipsregs.h __write_32bit_c0_register(reg, sel, val); \ val 1450 arch/mips/include/asm/mipsregs.h __write_64bit_c0_register(reg, sel, val); \ val 1504 arch/mips/include/asm/mipsregs.h #define __write_64bit_c0_split(source, sel, val) \ val 1506 arch/mips/include/asm/mipsregs.h unsigned long long __tmp = (val); \ val 1583 arch/mips/include/asm/mipsregs.h #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) val 1586 arch/mips/include/asm/mipsregs.h #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) val 1589 arch/mips/include/asm/mipsregs.h #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) val 1592 arch/mips/include/asm/mipsregs.h #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val) val 1595 arch/mips/include/asm/mipsregs.h #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) val 1598 arch/mips/include/asm/mipsregs.h #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val) val 1601 arch/mips/include/asm/mipsregs.h #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) val 1606 arch/mips/include/asm/mipsregs.h #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) val 1609 arch/mips/include/asm/mipsregs.h #define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val) val 1612 arch/mips/include/asm/mipsregs.h #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) val 1615 arch/mips/include/asm/mipsregs.h #define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val) val 1618 arch/mips/include/asm/mipsregs.h #define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val) val 1621 arch/mips/include/asm/mipsregs.h #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) val 1624 arch/mips/include/asm/mipsregs.h #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) val 1627 arch/mips/include/asm/mipsregs.h #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) val 1632 arch/mips/include/asm/mipsregs.h #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) val 1635 arch/mips/include/asm/mipsregs.h #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) val 1641 arch/mips/include/asm/mipsregs.h #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) val 1644 arch/mips/include/asm/mipsregs.h #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) val 1647 arch/mips/include/asm/mipsregs.h #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) val 1650 arch/mips/include/asm/mipsregs.h #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) val 1653 arch/mips/include/asm/mipsregs.h #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val) val 1656 arch/mips/include/asm/mipsregs.h #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val) val 1659 arch/mips/include/asm/mipsregs.h #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val) val 1662 arch/mips/include/asm/mipsregs.h #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) val 1665 arch/mips/include/asm/mipsregs.h #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val) val 1668 arch/mips/include/asm/mipsregs.h #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) val 1671 arch/mips/include/asm/mipsregs.h #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) val 1675 arch/mips/include/asm/mipsregs.h #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) val 1678 arch/mips/include/asm/mipsregs.h #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val) val 1681 arch/mips/include/asm/mipsregs.h #define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val) val 1684 arch/mips/include/asm/mipsregs.h #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) val 1687 arch/mips/include/asm/mipsregs.h #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) val 1701 arch/mips/include/asm/mipsregs.h #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) val 1702 arch/mips/include/asm/mipsregs.h #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) val 1703 arch/mips/include/asm/mipsregs.h #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) val 1704 arch/mips/include/asm/mipsregs.h #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) val 1705 arch/mips/include/asm/mipsregs.h #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) val 1706 arch/mips/include/asm/mipsregs.h #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) val 1707 arch/mips/include/asm/mipsregs.h #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) val 1708 arch/mips/include/asm/mipsregs.h #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) val 1711 arch/mips/include/asm/mipsregs.h #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) val 1713 arch/mips/include/asm/mipsregs.h #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) val 1715 arch/mips/include/asm/mipsregs.h #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) val 1728 arch/mips/include/asm/mipsregs.h #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) val 1729 arch/mips/include/asm/mipsregs.h #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) val 1730 arch/mips/include/asm/mipsregs.h #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) val 1731 arch/mips/include/asm/mipsregs.h #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) val 1732 arch/mips/include/asm/mipsregs.h #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) val 1733 arch/mips/include/asm/mipsregs.h #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) val 1734 arch/mips/include/asm/mipsregs.h #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) val 1735 arch/mips/include/asm/mipsregs.h #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) val 1749 arch/mips/include/asm/mipsregs.h #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) val 1750 arch/mips/include/asm/mipsregs.h #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) val 1751 arch/mips/include/asm/mipsregs.h #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) val 1752 arch/mips/include/asm/mipsregs.h #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) val 1753 arch/mips/include/asm/mipsregs.h #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) val 1754 arch/mips/include/asm/mipsregs.h #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) val 1755 arch/mips/include/asm/mipsregs.h #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) val 1756 arch/mips/include/asm/mipsregs.h #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) val 1759 arch/mips/include/asm/mipsregs.h #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) val 1762 arch/mips/include/asm/mipsregs.h #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) val 1765 arch/mips/include/asm/mipsregs.h #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) val 1768 arch/mips/include/asm/mipsregs.h #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) val 1772 arch/mips/include/asm/mipsregs.h #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val) val 1775 arch/mips/include/asm/mipsregs.h #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) val 1778 arch/mips/include/asm/mipsregs.h #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) val 1781 arch/mips/include/asm/mipsregs.h #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) val 1784 arch/mips/include/asm/mipsregs.h #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) val 1787 arch/mips/include/asm/mipsregs.h #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) val 1790 arch/mips/include/asm/mipsregs.h #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) val 1793 arch/mips/include/asm/mipsregs.h #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) val 1799 arch/mips/include/asm/mipsregs.h #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) val 1801 arch/mips/include/asm/mipsregs.h #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) val 1803 arch/mips/include/asm/mipsregs.h #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) val 1805 arch/mips/include/asm/mipsregs.h #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) val 1807 arch/mips/include/asm/mipsregs.h #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) val 1809 arch/mips/include/asm/mipsregs.h #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) val 1811 arch/mips/include/asm/mipsregs.h #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) val 1813 arch/mips/include/asm/mipsregs.h #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) val 1815 arch/mips/include/asm/mipsregs.h #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) val 1817 arch/mips/include/asm/mipsregs.h #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) val 1819 arch/mips/include/asm/mipsregs.h #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) val 1821 arch/mips/include/asm/mipsregs.h #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) val 1824 arch/mips/include/asm/mipsregs.h #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) val 1827 arch/mips/include/asm/mipsregs.h #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) val 1832 arch/mips/include/asm/mipsregs.h #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) val 1835 arch/mips/include/asm/mipsregs.h #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) val 1838 arch/mips/include/asm/mipsregs.h #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) val 1841 arch/mips/include/asm/mipsregs.h #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) val 1844 arch/mips/include/asm/mipsregs.h #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) val 1847 arch/mips/include/asm/mipsregs.h #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) val 1850 arch/mips/include/asm/mipsregs.h #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) val 1854 arch/mips/include/asm/mipsregs.h #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) val 1857 arch/mips/include/asm/mipsregs.h #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) val 1860 arch/mips/include/asm/mipsregs.h #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) val 1863 arch/mips/include/asm/mipsregs.h #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) val 1866 arch/mips/include/asm/mipsregs.h #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) val 1869 arch/mips/include/asm/mipsregs.h #define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val) val 1872 arch/mips/include/asm/mipsregs.h #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) val 1876 arch/mips/include/asm/mipsregs.h #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) val 1879 arch/mips/include/asm/mipsregs.h #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) val 1882 arch/mips/include/asm/mipsregs.h #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) val 1886 arch/mips/include/asm/mipsregs.h #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) val 1889 arch/mips/include/asm/mipsregs.h #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) val 1892 arch/mips/include/asm/mipsregs.h #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) val 1895 arch/mips/include/asm/mipsregs.h #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) val 1898 arch/mips/include/asm/mipsregs.h #define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val) val 1901 arch/mips/include/asm/mipsregs.h #define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val) val 1905 arch/mips/include/asm/mipsregs.h #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) val 1908 arch/mips/include/asm/mipsregs.h #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) val 1911 arch/mips/include/asm/mipsregs.h #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) val 1914 arch/mips/include/asm/mipsregs.h #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val) val 1917 arch/mips/include/asm/mipsregs.h #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val) val 1924 arch/mips/include/asm/mipsregs.h #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) val 1927 arch/mips/include/asm/mipsregs.h #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) val 1931 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) val 1934 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) val 1937 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) val 1941 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) val 1944 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) val 1947 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) val 1950 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) val 1953 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) val 1957 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) val 1960 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) val 1963 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) val 1966 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) val 1969 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) val 1972 arch/mips/include/asm/mipsregs.h #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) val 2061 arch/mips/include/asm/mipsregs.h #define __write_ulong_gc0_register(reg, sel, val) \ val 2064 arch/mips/include/asm/mipsregs.h __write_32bit_gc0_register(reg, sel, val); \ val 2066 arch/mips/include/asm/mipsregs.h __write_64bit_gc0_register(reg, sel, val); \ val 2070 arch/mips/include/asm/mipsregs.h #define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val) val 2073 arch/mips/include/asm/mipsregs.h #define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val) val 2076 arch/mips/include/asm/mipsregs.h #define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val) val 2079 arch/mips/include/asm/mipsregs.h #define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val) val 2082 arch/mips/include/asm/mipsregs.h #define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val) val 2085 arch/mips/include/asm/mipsregs.h #define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val) val 2088 arch/mips/include/asm/mipsregs.h #define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val) val 2091 arch/mips/include/asm/mipsregs.h #define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val) val 2094 arch/mips/include/asm/mipsregs.h #define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val) val 2097 arch/mips/include/asm/mipsregs.h #define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val) val 2100 arch/mips/include/asm/mipsregs.h #define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val) val 2103 arch/mips/include/asm/mipsregs.h #define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val) val 2106 arch/mips/include/asm/mipsregs.h #define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val) val 2109 arch/mips/include/asm/mipsregs.h #define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val) val 2112 arch/mips/include/asm/mipsregs.h #define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val) val 2115 arch/mips/include/asm/mipsregs.h #define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val) val 2118 arch/mips/include/asm/mipsregs.h #define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val) val 2121 arch/mips/include/asm/mipsregs.h #define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val) val 2124 arch/mips/include/asm/mipsregs.h #define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val) val 2127 arch/mips/include/asm/mipsregs.h #define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val) val 2130 arch/mips/include/asm/mipsregs.h #define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val) val 2135 arch/mips/include/asm/mipsregs.h #define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val) val 2138 arch/mips/include/asm/mipsregs.h #define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val) val 2141 arch/mips/include/asm/mipsregs.h #define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val) val 2144 arch/mips/include/asm/mipsregs.h #define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val) val 2147 arch/mips/include/asm/mipsregs.h #define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val) val 2150 arch/mips/include/asm/mipsregs.h #define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val) val 2155 arch/mips/include/asm/mipsregs.h #define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val) val 2158 arch/mips/include/asm/mipsregs.h #define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val) val 2168 arch/mips/include/asm/mipsregs.h #define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val) val 2169 arch/mips/include/asm/mipsregs.h #define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val) val 2170 arch/mips/include/asm/mipsregs.h #define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val) val 2171 arch/mips/include/asm/mipsregs.h #define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val) val 2172 arch/mips/include/asm/mipsregs.h #define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val) val 2173 arch/mips/include/asm/mipsregs.h #define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val) val 2174 arch/mips/include/asm/mipsregs.h #define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val) val 2175 arch/mips/include/asm/mipsregs.h #define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val) val 2178 arch/mips/include/asm/mipsregs.h #define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val) val 2188 arch/mips/include/asm/mipsregs.h #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val) val 2189 arch/mips/include/asm/mipsregs.h #define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val) val 2190 arch/mips/include/asm/mipsregs.h #define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val) val 2191 arch/mips/include/asm/mipsregs.h #define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val) val 2192 arch/mips/include/asm/mipsregs.h #define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val) val 2193 arch/mips/include/asm/mipsregs.h #define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val) val 2194 arch/mips/include/asm/mipsregs.h #define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val) val 2195 arch/mips/include/asm/mipsregs.h #define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val) val 2205 arch/mips/include/asm/mipsregs.h #define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val) val 2206 arch/mips/include/asm/mipsregs.h #define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val) val 2207 arch/mips/include/asm/mipsregs.h #define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val) val 2208 arch/mips/include/asm/mipsregs.h #define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val) val 2209 arch/mips/include/asm/mipsregs.h #define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val) val 2210 arch/mips/include/asm/mipsregs.h #define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val) val 2211 arch/mips/include/asm/mipsregs.h #define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val) val 2212 arch/mips/include/asm/mipsregs.h #define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val) val 2215 arch/mips/include/asm/mipsregs.h #define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val) val 2218 arch/mips/include/asm/mipsregs.h #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val) val 2220 arch/mips/include/asm/mipsregs.h #define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val) val 2222 arch/mips/include/asm/mipsregs.h #define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val) val 2224 arch/mips/include/asm/mipsregs.h #define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val) val 2226 arch/mips/include/asm/mipsregs.h #define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val) val 2228 arch/mips/include/asm/mipsregs.h #define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val) val 2230 arch/mips/include/asm/mipsregs.h #define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val) val 2232 arch/mips/include/asm/mipsregs.h #define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val) val 2234 arch/mips/include/asm/mipsregs.h #define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val) val 2236 arch/mips/include/asm/mipsregs.h #define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val) val 2238 arch/mips/include/asm/mipsregs.h #define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val) val 2240 arch/mips/include/asm/mipsregs.h #define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val) val 2243 arch/mips/include/asm/mipsregs.h #define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val) val 2251 arch/mips/include/asm/mipsregs.h #define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val) val 2252 arch/mips/include/asm/mipsregs.h #define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val) val 2253 arch/mips/include/asm/mipsregs.h #define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val) val 2254 arch/mips/include/asm/mipsregs.h #define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val) val 2255 arch/mips/include/asm/mipsregs.h #define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val) val 2256 arch/mips/include/asm/mipsregs.h #define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val) val 2260 arch/mips/include/asm/mipsregs.h #define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val) val 2263 arch/mips/include/asm/mipsregs.h #define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val) val 2266 arch/mips/include/asm/mipsregs.h #define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val) val 2269 arch/mips/include/asm/mipsregs.h #define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val) val 2291 arch/mips/include/asm/mipsregs.h #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ val 2299 arch/mips/include/asm/mipsregs.h : : "r" (val)); \ val 2305 arch/mips/include/asm/mipsregs.h #define write_32bit_cp1_register(dest, val) \ val 2306 arch/mips/include/asm/mipsregs.h _write_32bit_cp1_register(dest, val, .set hardfloat) val 2310 arch/mips/include/asm/mipsregs.h #define write_32bit_cp1_register(dest, val) \ val 2311 arch/mips/include/asm/mipsregs.h _write_32bit_cp1_register(dest, val, ) val 2330 arch/mips/include/asm/mipsregs.h #define wrdsp(val, mask) \ val 2339 arch/mips/include/asm/mipsregs.h : "r" (val), "i" (mask)); \ val 2562 arch/mips/include/asm/mipsregs.h #define wrdsp(val, mask) \ val 2573 arch/mips/include/asm/mipsregs.h : "r" (val), "i" (mask)); \ val 2592 arch/mips/include/asm/mipsregs.h #define _dsp_mtxxx(val, ins) \ val 2602 arch/mips/include/asm/mipsregs.h : "r" (val), "i" (ins)); \ val 2610 arch/mips/include/asm/mipsregs.h #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000)) val 2611 arch/mips/include/asm/mipsregs.h #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000)) val 2618 arch/mips/include/asm/mipsregs.h #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) val 2619 arch/mips/include/asm/mipsregs.h #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) val 2798 arch/mips/include/asm/mipsregs.h change_##name(unsigned int change, unsigned int val) \ val 2804 arch/mips/include/asm/mipsregs.h new |= (val & change); \ val 190 arch/mips/include/asm/msa.h static inline void write_msa_##name(unsigned int val) \ val 197 arch/mips/include/asm/msa.h : : "r"(val)); \ val 54 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) val 58 arch/mips/include/asm/netlogic/haldefs.h *addr = val; val 75 arch/mips/include/asm/netlogic/haldefs.h uint64_t val; val 88 arch/mips/include/asm/netlogic/haldefs.h : "=r" (val) val 92 arch/mips/include/asm/netlogic/haldefs.h val = *ptr; val 94 arch/mips/include/asm/netlogic/haldefs.h return val; val 98 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) val 118 arch/mips/include/asm/netlogic/haldefs.h : "0" (val), "m" (*ptr)); val 121 arch/mips/include/asm/netlogic/haldefs.h *ptr = val; val 135 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) val 137 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg(base, reg, val); val 147 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) val 149 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64(base, reg, val); val 48 arch/mips/include/asm/netlogic/mips-extns.h #define write_c0_eimr(val) \ val 59 arch/mips/include/asm/netlogic/mips-extns.h : : "r" (val)); \ val 61 arch/mips/include/asm/netlogic/mips-extns.h __write_64bit_c0_register($9, 7, (val)); \ val 121 arch/mips/include/asm/netlogic/mips-extns.h uint64_t val; val 124 arch/mips/include/asm/netlogic/mips-extns.h val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7); val 137 arch/mips/include/asm/netlogic/mips-extns.h : "=r" (val)); val 139 arch/mips/include/asm/netlogic/mips-extns.h return val; val 203 arch/mips/include/asm/netlogic/mips-extns.h #define __write_64bit_c2_split(source, sel, val) \ val 217 arch/mips/include/asm/netlogic/mips-extns.h : : "r" (val)); \ val 227 arch/mips/include/asm/netlogic/mips-extns.h : : "r" (val)); \ val 231 arch/mips/include/asm/netlogic/xlp-hal/pic.h uint64_t val; val 233 arch/mips/include/asm/netlogic/xlp-hal/pic.h val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) | val 238 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); val 245 arch/mips/include/asm/netlogic/xlp-hal/pic.h uint64_t val; val 247 arch/mips/include/asm/netlogic/xlp-hal/pic.h val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) | val 252 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_IRT(irt_num), val); val 210 arch/mips/include/asm/nile4.h static inline void nile4_out32(u32 offset, u32 val) val 212 arch/mips/include/asm/nile4.h *(volatile u32 *)(NILE4_BASE+offset) = val; val 218 arch/mips/include/asm/nile4.h u32 val = *(volatile u32 *)(NILE4_BASE+offset); val 220 arch/mips/include/asm/nile4.h return val; val 223 arch/mips/include/asm/nile4.h static inline void nile4_out16(u32 offset, u16 val) val 225 arch/mips/include/asm/nile4.h *(volatile u16 *)(NILE4_BASE+offset) = val; val 231 arch/mips/include/asm/nile4.h u16 val = *(volatile u16 *)(NILE4_BASE+offset); val 233 arch/mips/include/asm/nile4.h return val; val 236 arch/mips/include/asm/nile4.h static inline void nile4_out8(u32 offset, u8 val) val 238 arch/mips/include/asm/nile4.h *(volatile u8 *)(NILE4_BASE+offset) = val; val 244 arch/mips/include/asm/nile4.h u8 val = *(volatile u8 *)(NILE4_BASE+offset); val 246 arch/mips/include/asm/nile4.h return val; val 2419 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t val:1; val 2423 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t val:1; val 2550 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t val:1; val 2556 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t val:1; val 117 arch/mips/include/asm/octeon/cvmx-spinlock.h [val] "+m"(lock->value), [tmp] "=&r"(tmp) val 140 arch/mips/include/asm/octeon/cvmx-spinlock.h [val] "+m"(lock->value), [tmp] "=&r"(tmp) val 177 arch/mips/include/asm/octeon/cvmx-spinlock.h [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav) val 210 arch/mips/include/asm/octeon/cvmx-spinlock.h [val] "+m"(*word), [tmp] "=&r"(tmp) val 213 arch/mips/include/asm/octeon/cvmx.h static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ val 215 arch/mips/include/asm/octeon/cvmx.h *CASTPTR(volatile TYPE##_t, addr) = val; \ val 266 arch/mips/include/asm/octeon/cvmx.h static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) val 268 arch/mips/include/asm/octeon/cvmx.h cvmx_write64(csr_addr, val); val 280 arch/mips/include/asm/octeon/cvmx.h static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val) val 282 arch/mips/include/asm/octeon/cvmx.h cvmx_write_csr((__force uint64_t)csr_addr, val); val 285 arch/mips/include/asm/octeon/cvmx.h static inline void cvmx_write_io(uint64_t io_addr, uint64_t val) val 287 arch/mips/include/asm/octeon/cvmx.h cvmx_write64(io_addr, val); val 293 arch/mips/include/asm/octeon/cvmx.h uint64_t val = cvmx_read64(csr_addr); val 294 arch/mips/include/asm/octeon/cvmx.h return val; val 368 arch/mips/include/asm/octeon/cvmx.h uint64_t val) val 375 arch/mips/include/asm/octeon/cvmx.h cvmx_write64_uint64(composite_csr_addr, val); val 397 arch/mips/include/asm/octeon/cvmx.h static inline uint32_t cvmx_pop(uint32_t val) val 400 arch/mips/include/asm/octeon/cvmx.h CVMX_POP(pop, val); val 412 arch/mips/include/asm/octeon/cvmx.h static inline int cvmx_dpop(uint64_t val) val 415 arch/mips/include/asm/octeon/cvmx.h CVMX_DPOP(pop, val); val 295 arch/mips/include/asm/octeon/octeon.h static inline void octeon_npi_write32(uint64_t address, uint32_t val) val 297 arch/mips/include/asm/octeon/octeon.h cvmx_write64_uint32(address ^ 4, val); val 817 arch/mips/include/asm/pci/bridge.h #define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg) val 818 arch/mips/include/asm/pci/bridge.h #define bridge_set(bc, reg, val) \ val 819 arch/mips/include/asm/pci/bridge.h __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg) val 820 arch/mips/include/asm/pci/bridge.h #define bridge_clr(bc, reg, val) \ val 821 arch/mips/include/asm/pci/bridge.h __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg) val 227 arch/mips/include/asm/pgtable-32.h #define __swp_type(x) (((x).val >> 10) & 0x1f) val 228 arch/mips/include/asm/pgtable-32.h #define __swp_offset(x) ((x).val >> 15) val 231 arch/mips/include/asm/pgtable-32.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 238 arch/mips/include/asm/pgtable-32.h #define __swp_type(x) (((x).val >> 4) & 0x1f) val 239 arch/mips/include/asm/pgtable-32.h #define __swp_offset(x) ((x).val >> 9) val 242 arch/mips/include/asm/pgtable-32.h #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) val 247 arch/mips/include/asm/pgtable-32.h #define __swp_type(x) (((x).val >> 2) & 0x1f) val 248 arch/mips/include/asm/pgtable-32.h #define __swp_offset(x) ((x).val >> 7) val 251 arch/mips/include/asm/pgtable-32.h #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) val 261 arch/mips/include/asm/pgtable-32.h #define __swp_type(x) (((x).val >> 8) & 0x1f) val 262 arch/mips/include/asm/pgtable-32.h #define __swp_offset(x) ((x).val >> 13) val 265 arch/mips/include/asm/pgtable-32.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 375 arch/mips/include/asm/pgtable-64.h #define __swp_type(x) (((x).val >> 16) & 0xff) val 376 arch/mips/include/asm/pgtable-64.h #define __swp_offset(x) ((x).val >> 24) val 379 arch/mips/include/asm/pgtable-64.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 108 arch/mips/include/asm/processor.h return fpr->val##width[FPR_IDX(width, idx)]; \ val 112 arch/mips/include/asm/processor.h u##width val) \ val 114 arch/mips/include/asm/processor.h fpr->val##width[FPR_IDX(width, idx)] = val; \ val 60 arch/mips/include/asm/ptrace.h unsigned long val) val 62 arch/mips/include/asm/ptrace.h regs->cp0_epc = val; val 184 arch/mips/include/asm/ptrace.h unsigned long val) val 186 arch/mips/include/asm/ptrace.h regs->regs[29] = val; val 242 arch/mips/include/asm/sibyte/sb1250_defs.h #define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) val 113 arch/mips/include/asm/syscall.h int error, long val) val 119 arch/mips/include/asm/syscall.h regs->regs[2] = val; val 89 arch/mips/include/asm/txx9/generic.h void (*putc)(unsigned int pos, unsigned char val)); val 66 arch/mips/include/asm/txx9/smsc_fdc37m81x.h void smsc_fdc37m81x_config_set(u8 reg, u8 val); val 232 arch/mips/include/asm/uaccess.h #define __get_kernel_common(val, size, ptr) __get_user_common(val, size, ptr) val 252 arch/mips/include/asm/uaccess.h #define __get_kernel_common(val, size, ptr) \ val 255 arch/mips/include/asm/uaccess.h case 1: __get_data_asm(val, _loadb, ptr); break; \ val 256 arch/mips/include/asm/uaccess.h case 2: __get_data_asm(val, _loadh, ptr); break; \ val 257 arch/mips/include/asm/uaccess.h case 4: __get_data_asm(val, _loadw, ptr); break; \ val 258 arch/mips/include/asm/uaccess.h case 8: __GET_DW(val, _loadd, ptr); break; \ val 265 arch/mips/include/asm/uaccess.h #define __GET_DW(val, insn, ptr) __get_data_asm_ll32(val, insn, ptr) val 268 arch/mips/include/asm/uaccess.h #define __GET_DW(val, insn, ptr) __get_data_asm(val, insn, ptr) val 273 arch/mips/include/asm/uaccess.h #define __get_user_common(val, size, ptr) \ val 276 arch/mips/include/asm/uaccess.h case 1: __get_data_asm(val, user_lb, ptr); break; \ val 277 arch/mips/include/asm/uaccess.h case 2: __get_data_asm(val, user_lh, ptr); break; \ val 278 arch/mips/include/asm/uaccess.h case 4: __get_data_asm(val, user_lw, ptr); break; \ val 279 arch/mips/include/asm/uaccess.h case 8: __GET_DW(val, user_ld, ptr); break; \ val 314 arch/mips/include/asm/uaccess.h #define __get_data_asm(val, insn, addr) \ val 333 arch/mips/include/asm/uaccess.h (val) = (__typeof__(*(addr))) __gu_tmp; \ val 339 arch/mips/include/asm/uaccess.h #define __get_data_asm_ll32(val, insn, addr) \ val 364 arch/mips/include/asm/uaccess.h (val) = __gu_tmp.t; \ val 198 arch/mips/include/asm/uasm.h int uasm_rel_hi(long val); val 199 arch/mips/include/asm/uasm.h int uasm_rel_lo(long val); val 211 arch/mips/include/asm/uasm.h # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val) val 227 arch/mips/include/asm/uasm.h # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val) val 35 arch/mips/include/asm/vga.h static inline void scr_writew(u16 val, volatile u16 *addr) val 37 arch/mips/include/asm/vga.h *addr = cpu_to_le16(val); val 13 arch/mips/jazz/reset.c static void jazz_write_output(unsigned char val) val 20 arch/mips/jazz/reset.c jazz_kh->data = val; val 23 arch/mips/jazz/reset.c static void jazz_write_command(unsigned char val) val 30 arch/mips/jazz/reset.c jazz_kh->command = val; val 51 arch/mips/kernel/cevt-ds1287.c u8 val; val 55 arch/mips/kernel/cevt-ds1287.c val = CMOS_READ(RTC_REG_B); val 56 arch/mips/kernel/cevt-ds1287.c val &= ~RTC_PIE; val 57 arch/mips/kernel/cevt-ds1287.c CMOS_WRITE(val, RTC_REG_B); val 65 arch/mips/kernel/cevt-ds1287.c u8 val; val 69 arch/mips/kernel/cevt-ds1287.c val = CMOS_READ(RTC_REG_B); val 70 arch/mips/kernel/cevt-ds1287.c val |= RTC_PIE; val 71 arch/mips/kernel/cevt-ds1287.c CMOS_WRITE(val, RTC_REG_B); val 10 arch/mips/kernel/cmpxchg.c unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int size) val 21 arch/mips/kernel/cmpxchg.c val &= mask; val 43 arch/mips/kernel/cmpxchg.c new32 = (load32 & ~mask) | (val << shift); val 26 arch/mips/kernel/gpio_txx9.c u32 val; val 27 arch/mips/kernel/gpio_txx9.c val = __raw_readl(&txx9_pioptr->dout); val 29 arch/mips/kernel/gpio_txx9.c val |= 1 << offset; val 31 arch/mips/kernel/gpio_txx9.c val &= ~(1 << offset); val 32 arch/mips/kernel/gpio_txx9.c __raw_writel(val, &txx9_pioptr->dout); val 423 arch/mips/kernel/kprobes.c unsigned long val, void *data) val 429 arch/mips/kernel/kprobes.c switch (val) { val 260 arch/mips/kernel/mips-cm.c u32 val; val 266 arch/mips/kernel/mips-cm.c val = core << __ffs(CM3_GCR_Cx_OTHER_CORE); val 267 arch/mips/kernel/mips-cm.c val |= vp << __ffs(CM3_GCR_Cx_OTHER_VP); val 270 arch/mips/kernel/mips-cm.c val |= CM_GCR_Cx_OTHER_CLUSTER_EN; val 271 arch/mips/kernel/mips-cm.c val |= cluster << __ffs(CM_GCR_Cx_OTHER_CLUSTER); val 272 arch/mips/kernel/mips-cm.c val |= block << __ffs(CM_GCR_Cx_OTHER_BLOCK); val 302 arch/mips/kernel/mips-cm.c val = core << __ffs(CM_GCR_Cx_OTHER_CORENUM); val 305 arch/mips/kernel/mips-cm.c write_gcr_cl_other(val); val 123 arch/mips/kernel/module.c Elf_Addr val, vallo; val 152 arch/mips/kernel/module.c val = ((insn & 0xffff) << 16) + vallo; val 153 arch/mips/kernel/module.c val += v; val 159 arch/mips/kernel/module.c val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; val 161 arch/mips/kernel/module.c insn = (insn & ~0xffff) | val; val 175 arch/mips/kernel/module.c val = v + vallo; val 176 arch/mips/kernel/module.c insnlo = (insnlo & ~0xffff) | (val & 0xffff); val 83 arch/mips/kernel/perf_event_mipsxx.c void (*write_counter)(unsigned int idx, u64 val); val 206 arch/mips/kernel/perf_event_mipsxx.c static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) val 212 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfcntr0(val); val 215 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfcntr1(val); val 218 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfcntr2(val); val 221 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfcntr3(val); val 226 arch/mips/kernel/perf_event_mipsxx.c static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val) val 232 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfcntr0_64(val); val 235 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfcntr1_64(val); val 238 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfcntr2_64(val); val 241 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfcntr3_64(val); val 265 arch/mips/kernel/perf_event_mipsxx.c static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) val 271 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfctrl0(val); val 274 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfctrl1(val); val 277 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfctrl2(val); val 280 arch/mips/kernel/perf_event_mipsxx.c write_c0_perfctrl3(val); val 31 arch/mips/kernel/proc.c int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v) val 33 arch/mips/kernel/proc.c return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v); val 166 arch/mips/kernel/signal.c uint64_t val; val 198 arch/mips/kernel/signal.c val = get_fpr64(¤t->thread.fpu.fpr[i], 1); val 199 arch/mips/kernel/signal.c err |= __put_user(val, &msa->wr[i]); val 212 arch/mips/kernel/signal.c unsigned long long val; val 244 arch/mips/kernel/signal.c err |= __get_user(val, &msa->wr[i]); val 245 arch/mips/kernel/signal.c set_fpr64(¤t->thread.fpu.fpr[i], 1, val); val 54 arch/mips/kernel/smp-bmips.c static void bmips_set_reset_vec(int cpu, u32 val); val 475 arch/mips/kernel/smp-bmips.c u32 val; val 482 arch/mips/kernel/smp-bmips.c u32 mask = ~(0xffff << shift), val = info->val >> 16; val 491 arch/mips/kernel/smp-bmips.c bmips_write_zscm_reg(0xa0, (val << 16) | val); val 495 arch/mips/kernel/smp-bmips.c (val << shift)); val 501 arch/mips/kernel/smp-bmips.c static void bmips_set_reset_vec(int cpu, u32 val) val 508 arch/mips/kernel/smp-bmips.c info.val = val; val 514 arch/mips/kernel/smp-bmips.c __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); val 518 arch/mips/kernel/smp-bmips.c __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); val 11 arch/mips/kernel/spinlock_test.c static int ss_get(void *data, u64 *val) val 33 arch/mips/kernel/spinlock_test.c *val = ktime_us_delta(finish, start); val 91 arch/mips/kernel/spinlock_test.c static int multi_get(void *data, u64 *val) val 112 arch/mips/kernel/spinlock_test.c *val = ktime_us_delta(finish, t1.start); val 1211 arch/mips/kernel/traps.c int cu2_notifier_call_chain(unsigned long val, void *v) val 1213 arch/mips/kernel/traps.c return raw_notifier_call_chain(&cu2_chain, val, v); val 155 arch/mips/kernel/uprobes.c unsigned long val, void *data) val 168 arch/mips/kernel/uprobes.c switch (val) { val 28 arch/mips/kernel/vpe-mt.c unsigned long flags, val, dmt_flag; val 35 arch/mips/kernel/vpe-mt.c val = read_c0_vpeconf0(); val 36 arch/mips/kernel/vpe-mt.c if (!(val & VPECONF0_MVP)) { val 88 arch/mips/kernel/vpe-mt.c val = read_tc_c0_tcstatus(); val 89 arch/mips/kernel/vpe-mt.c val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; val 90 arch/mips/kernel/vpe-mt.c write_tc_c0_tcstatus(val); val 331 arch/mips/kernel/vpe-mt.c unsigned long flags, val; val 385 arch/mips/kernel/vpe-mt.c val = read_c0_mvpconf0(); val 386 arch/mips/kernel/vpe-mt.c hw_tcs = (val & MVPCONF0_PTC) + 1; val 387 arch/mips/kernel/vpe-mt.c hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; val 337 arch/mips/kernel/vpe.c Elf32_Addr val, vallo; val 364 arch/mips/kernel/vpe.c val = ((insn & 0xffff) << 16) + vallo; val 365 arch/mips/kernel/vpe.c val += v; val 371 arch/mips/kernel/vpe.c val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; val 373 arch/mips/kernel/vpe.c insn = (insn & ~0xffff) | val; val 387 arch/mips/kernel/vpe.c val = v + vallo; val 388 arch/mips/kernel/vpe.c insnlo = (insnlo & ~0xffff) | (val & 0xffff); val 1387 arch/mips/kvm/emulate.c unsigned int old_val, val, change; val 1390 arch/mips/kvm/emulate.c val = vcpu->arch.gprs[rt]; val 1391 arch/mips/kvm/emulate.c change = val ^ old_val; val 1394 arch/mips/kvm/emulate.c val &= ~ST0_NMI; val 1402 arch/mips/kvm/emulate.c val &= ~(ST0_CU1 | ST0_FR); val 1409 arch/mips/kvm/emulate.c val &= ~ST0_FR; val 1431 arch/mips/kvm/emulate.c if (change & ST0_CU1 && !(val & ST0_FR) && val 1444 arch/mips/kvm/emulate.c change_c0_status(ST0_CU1, val); val 1448 arch/mips/kvm/emulate.c kvm_write_c0_guest_status(cop0, val); val 1459 arch/mips/kvm/emulate.c unsigned int old_val, val, change, wrmask; val 1462 arch/mips/kvm/emulate.c val = vcpu->arch.gprs[rt]; val 1466 arch/mips/kvm/emulate.c change = (val ^ old_val) & wrmask; val 1467 arch/mips/kvm/emulate.c val = old_val ^ change; val 1479 arch/mips/kvm/emulate.c change_c0_config5(MIPS_CONF5_FRE, val); val 1490 arch/mips/kvm/emulate.c val); val 1494 arch/mips/kvm/emulate.c kvm_write_c0_guest_config5(cop0, val); val 204 arch/mips/kvm/trace.h unsigned long val), val 205 arch/mips/kvm/trace.h TP_ARGS(vcpu, op, reg, val), val 207 arch/mips/kvm/trace.h __field(unsigned long, val) val 213 arch/mips/kvm/trace.h __entry->val = val; val 227 arch/mips/kvm/trace.h __entry->val) val 865 arch/mips/kvm/vz.c static unsigned long mips_process_maar(unsigned int op, unsigned long val) val 878 arch/mips/kvm/vz.c val &= ~MIPS_MAAR_VH; val 881 arch/mips/kvm/vz.c val &= ~MIPS_MAAR_VH; val 882 arch/mips/kvm/vz.c if (val & MIPS_MAAR_VL) val 883 arch/mips/kvm/vz.c val |= MIPS_MAAR_VH; val 886 arch/mips/kvm/vz.c return val & mask; val 889 arch/mips/kvm/vz.c static void kvm_write_maari(struct kvm_vcpu *vcpu, unsigned long val) val 893 arch/mips/kvm/vz.c val &= MIPS_MAARI_INDEX; val 894 arch/mips/kvm/vz.c if (val == MIPS_MAARI_INDEX) val 896 arch/mips/kvm/vz.c else if (val < ARRAY_SIZE(vcpu->arch.maar)) val 897 arch/mips/kvm/vz.c kvm_write_sw_gc0_maari(cop0, val); val 909 arch/mips/kvm/vz.c unsigned long val; val 941 arch/mips/kvm/vz.c val = kvm_mips_read_count(vcpu); val 944 arch/mips/kvm/vz.c val = read_gc0_compare(); val 948 arch/mips/kvm/vz.c val = read_gc0_lladdr() & val 951 arch/mips/kvm/vz.c val = 0; val 959 arch/mips/kvm/vz.c val = vcpu->arch.maar[ val 976 arch/mips/kvm/vz.c val = cop0->reg[rd][sel]; val 978 arch/mips/kvm/vz.c val = 0; val 985 arch/mips/kvm/vz.c val = (int)val; val 986 arch/mips/kvm/vz.c vcpu->arch.gprs[rt] = val; val 991 arch/mips/kvm/vz.c KVM_TRACE_COP0(rd, sel), val); val 999 arch/mips/kvm/vz.c val = vcpu->arch.gprs[rt]; val 1002 arch/mips/kvm/vz.c KVM_TRACE_COP0(rd, sel), val); val 1020 arch/mips/kvm/vz.c !(val & MIPS_LLADDR_LLB)) val 1026 arch/mips/kvm/vz.c val = mips_process_maar(inst.c0r_format.rs, val 1027 arch/mips/kvm/vz.c val); val 1033 arch/mips/kvm/vz.c val; val 1038 arch/mips/kvm/vz.c kvm_write_maari(vcpu, val); val 1234 arch/mips/kvm/vz.c unsigned int val = arch->gprs[rt]; val 1238 arch/mips/kvm/vz.c val); val 1243 arch/mips/kvm/vz.c val &= ~(ST0_CU1 | ST0_FR); val 1250 arch/mips/kvm/vz.c val &= ~ST0_FR; val 1253 arch/mips/kvm/vz.c change = val ^ old_val; val 1271 arch/mips/kvm/vz.c if (change & ST0_CU1 && !(val & ST0_FR) && val 1275 arch/mips/kvm/vz.c write_gc0_status(val); val 1278 arch/mips/kvm/vz.c u32 change = old_cause ^ val; val 1282 arch/mips/kvm/vz.c if (val & CAUSEF_DC) { val 1299 arch/mips/kvm/vz.c write_gc0_intctl(val); val 1302 arch/mips/kvm/vz.c change = val ^ old_val; val 1312 arch/mips/kvm/vz.c change_c0_config5(MIPS_CONF5_FRE, val); val 1316 arch/mips/kvm/vz.c val = old_val ^ val 1318 arch/mips/kvm/vz.c write_gc0_config5(val); val 160 arch/mips/lantiq/irq.c int val = 0; val 167 arch/mips/lantiq/irq.c val = 1; val 171 arch/mips/lantiq/irq.c val = 2; val 175 arch/mips/lantiq/irq.c val = 3; val 179 arch/mips/lantiq/irq.c val = 5; val 182 arch/mips/lantiq/irq.c val = 6; val 195 arch/mips/lantiq/irq.c (~(7 << (i * 4)))) | (val << (i * 4)), val 250 arch/mips/lantiq/xway/sysctrl.c unsigned int val = ltq_cgu_r32(ifccr); val 254 arch/mips/lantiq/xway/sysctrl.c val &= ~0x1f00000; val 256 arch/mips/lantiq/xway/sysctrl.c val |= 0xe00000; val 258 arch/mips/lantiq/xway/sysctrl.c val |= 0x700000; /* 62.5M */ val 260 arch/mips/lantiq/xway/sysctrl.c val &= ~0xf00000; val 262 arch/mips/lantiq/xway/sysctrl.c val |= 0x800000; val 264 arch/mips/lantiq/xway/sysctrl.c val |= 0x400000; /* 62.5M */ val 266 arch/mips/lantiq/xway/sysctrl.c ltq_cgu_w32(val, ifccr); val 296 arch/mips/lantiq/xway/sysctrl.c unsigned int val = ltq_cgu_r32(ifccr); val 298 arch/mips/lantiq/xway/sysctrl.c val &= ~(3 << shift); val 299 arch/mips/lantiq/xway/sysctrl.c val |= i << shift; val 300 arch/mips/lantiq/xway/sysctrl.c val |= enable; val 301 arch/mips/lantiq/xway/sysctrl.c ltq_cgu_w32(val, ifccr); val 23 arch/mips/lasat/at93c.c static void at93c_reg_write(u32 val) val 25 arch/mips/lasat/at93c.c *at93c->reg = val; val 25 arch/mips/lasat/ds1603.c static void rtc_reg_write(unsigned long val) val 27 arch/mips/lasat/ds1603.c *ds1603->reg = val; val 25 arch/mips/lasat/picvue.c static void pvc_reg_write(u32 val) val 27 arch/mips/lasat/picvue.c *picvue->reg = val; val 92 arch/mips/loongson32/common/platform.c u32 val; val 94 arch/mips/loongson32/common/platform.c val = __raw_readl(LS1X_MUX_CTRL1); val 103 arch/mips/loongson32/common/platform.c val &= ~(GMAC1_USE_TXCLK | GMAC1_USE_PWM23); val 106 arch/mips/loongson32/common/platform.c val |= (GMAC1_USE_TXCLK | GMAC1_USE_PWM23); val 113 arch/mips/loongson32/common/platform.c val &= ~GMAC1_SHUT; val 117 arch/mips/loongson32/common/platform.c val &= ~(GMAC0_USE_TXCLK | GMAC0_USE_PWM01); val 120 arch/mips/loongson32/common/platform.c val |= (GMAC0_USE_TXCLK | GMAC0_USE_PWM01); val 127 arch/mips/loongson32/common/platform.c val &= ~GMAC0_SHUT; val 129 arch/mips/loongson32/common/platform.c __raw_writel(val, LS1X_MUX_CTRL1); val 133 arch/mips/loongson32/common/platform.c val &= ~PHY_INTF_SELI; val 135 arch/mips/loongson32/common/platform.c val |= 0x4 << PHY_INTF_SELI_SHIFT; val 136 arch/mips/loongson32/common/platform.c __raw_writel(val, LS1X_MUX_CTRL1); val 138 arch/mips/loongson32/common/platform.c val = __raw_readl(LS1X_MUX_CTRL0); val 139 arch/mips/loongson32/common/platform.c __raw_writel(val & (~GMAC_SHUT), LS1X_MUX_CTRL0); val 286 arch/mips/loongson32/common/platform.c u32 val = __raw_readl(LS1X_RTC_CTRL); val 288 arch/mips/loongson32/common/platform.c if (!(val & RTC_EXTCLK_OK)) val 289 arch/mips/loongson32/common/platform.c __raw_writel(val | RTC_EXTCLK_EN, LS1X_RTC_CTRL); val 34 arch/mips/loongson64/lemote-2f/ec_kb3310b.c void ec_write(unsigned short addr, unsigned char val) val 41 arch/mips/loongson64/lemote-2f/ec_kb3310b.c outb(val, EC_IO_PORT_DATA); val 13 arch/mips/loongson64/lemote-2f/ec_kb3310b.h extern void ec_write(unsigned short addr, unsigned char val); val 53 arch/mips/loongson64/lemote-2f/reset.c u32 hi, lo, val; val 61 arch/mips/loongson64/lemote-2f/reset.c val = inl(gpio_base + GPIOL_OUT_EN); val 62 arch/mips/loongson64/lemote-2f/reset.c val &= ~(1 << (16 + 13)); val 63 arch/mips/loongson64/lemote-2f/reset.c val |= (1 << 13); val 64 arch/mips/loongson64/lemote-2f/reset.c outl(val, gpio_base + GPIOL_OUT_EN); val 67 arch/mips/loongson64/lemote-2f/reset.c val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13)); val 68 arch/mips/loongson64/lemote-2f/reset.c val |= (1 << (16 + 13)); val 69 arch/mips/loongson64/lemote-2f/reset.c outl(val, gpio_base + GPIOL_OUT_VAL); val 95 arch/mips/loongson64/lemote-2f/reset.c u8 val; val 101 arch/mips/loongson64/lemote-2f/reset.c val = inb(EC_SHUTDOWN_IO_PORT_DATA); val 102 arch/mips/loongson64/lemote-2f/reset.c outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA); val 107 arch/mips/loongson64/lemote-2f/reset.c outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA); val 455 arch/mips/loongson64/loongson-3/smp.c register int val; val 479 arch/mips/loongson64/loongson-3/smp.c : [addr] "=&r" (addr), [val] "=&r" (val) val 517 arch/mips/loongson64/loongson-3/smp.c register int val; val 561 arch/mips/loongson64/loongson-3/smp.c : [addr] "=&r" (addr), [val] "=&r" (val) val 600 arch/mips/loongson64/loongson-3/smp.c register int val; val 624 arch/mips/loongson64/loongson-3/smp.c : [addr] "=&r" (addr), [val] "=&r" (val) val 1476 arch/mips/math-emu/cp1emu.c u32 val; val 1489 arch/mips/math-emu/cp1emu.c if (__get_user(val, va)) { val 1494 arch/mips/math-emu/cp1emu.c SITOREG(val, MIPSInst_FD(ir)); val 1503 arch/mips/math-emu/cp1emu.c SIFROMREG(val, MIPSInst_FS(ir)); val 1509 arch/mips/math-emu/cp1emu.c if (put_user(val, va)) { val 1573 arch/mips/math-emu/cp1emu.c u64 val; val 1586 arch/mips/math-emu/cp1emu.c if (__get_user(val, va)) { val 1591 arch/mips/math-emu/cp1emu.c DITOREG(val, MIPSInst_FD(ir)); val 1599 arch/mips/math-emu/cp1emu.c DIFROMREG(val, MIPSInst_FS(ir)); val 1605 arch/mips/math-emu/cp1emu.c if (__put_user(val, va)) { val 14 arch/mips/math-emu/me-debugfs.c static int fpuemu_stat_get(void *data, u64 *val) val 27 arch/mips/math-emu/me-debugfs.c *val = sum; val 307 arch/mips/mm/c-octeon.c static void co_cache_error_call_notifiers(unsigned long val) val 309 arch/mips/mm/c-octeon.c int rv = raw_notifier_call_chain(&co_cache_error_chain, val, NULL); val 315 arch/mips/mm/c-octeon.c if (val) { val 64 arch/mips/mm/cerr-sb1.c static inline void breakout_errctl(unsigned int val) val 66 arch/mips/mm/cerr-sb1.c if (val & CP0_ERRCTL_RECOVERABLE) val 68 arch/mips/mm/cerr-sb1.c if (val & CP0_ERRCTL_DCACHE) val 70 arch/mips/mm/cerr-sb1.c if (val & CP0_ERRCTL_ICACHE) val 72 arch/mips/mm/cerr-sb1.c if (val & CP0_ERRCTL_MULTIBUS) val 77 arch/mips/mm/cerr-sb1.c static inline void breakout_cerri(unsigned int val) val 79 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRI_TAG_PARITY) val 81 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRI_DATA_PARITY) val 83 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRI_EXTERNAL) val 88 arch/mips/mm/cerr-sb1.c static inline void breakout_cerrd(unsigned int val) val 90 arch/mips/mm/cerr-sb1.c switch (val & CP0_CERRD_CAUSES) { val 110 arch/mips/mm/cerr-sb1.c if (!(val & CP0_CERRD_TYPES)) val 113 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRD_MULTIPLE) val 115 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRD_TAG_STATE) val 117 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRD_TAG_ADDRESS) val 119 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRD_DATA_SBE) val 121 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRD_DATA_DBE) val 123 arch/mips/mm/cerr-sb1.c if (val & CP0_CERRD_EXTERNAL) val 446 arch/mips/mm/cerr-sb1.c unsigned char val; val 467 arch/mips/mm/cerr-sb1.c while (dsc->val != 0xff) { val 468 arch/mips/mm/cerr-sb1.c if (dsc->val == state) val 427 arch/mips/mm/uasm.c static int uasm_rel_highest(long val) val 430 arch/mips/mm/uasm.c return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; val 436 arch/mips/mm/uasm.c static int uasm_rel_higher(long val) val 439 arch/mips/mm/uasm.c return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; val 445 arch/mips/mm/uasm.c int uasm_rel_hi(long val) val 447 arch/mips/mm/uasm.c return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; val 451 arch/mips/mm/uasm.c int uasm_rel_lo(long val) val 453 arch/mips/mm/uasm.c return ((val & 0xffff) ^ 0x8000) - 0x8000; val 1633 arch/mips/net/ebpf_jit.c s64 val; val 1635 arch/mips/net/ebpf_jit.c val = (s64)((u32)insn->imm | ((u64)(insn + 1)->imm << 32)); val 1636 arch/mips/net/ebpf_jit.c if (val > 0 && val <= S32_MAX) val 1638 arch/mips/net/ebpf_jit.c else if (val >= S32_MIN && val <= S32_MAX) val 194 arch/mips/netlogic/xlp/ahci-init-xlp2.c u32 val; val 199 arch/mips/netlogic/xlp/ahci-init-xlp2.c val = nlm_read_sata_reg(regbase, PHY_MEM_ACCESS); val 200 arch/mips/netlogic/xlp/ahci-init-xlp2.c return (val >> 16) & 0xff; val 206 arch/mips/netlogic/xlp/ahci-init-xlp2.c u8 val; val 218 arch/mips/netlogic/xlp/ahci-init-xlp2.c val = read_phy_reg(regbase, 0x0029, port); val 219 arch/mips/netlogic/xlp/ahci-init-xlp2.c write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1)); val 221 arch/mips/netlogic/xlp/ahci-init-xlp2.c val = read_phy_reg(regbase, 0x0056, port); val 222 arch/mips/netlogic/xlp/ahci-init-xlp2.c write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3)); val 224 arch/mips/netlogic/xlp/ahci-init-xlp2.c val = read_phy_reg(regbase, 0x0018, port); val 225 arch/mips/netlogic/xlp/ahci-init-xlp2.c write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0)); val 348 arch/mips/netlogic/xlp/ahci-init-xlp2.c u32 val; val 353 arch/mips/netlogic/xlp/ahci-init-xlp2.c val = nlm_read_sata_reg(regbase, SATA_INT); val 354 arch/mips/netlogic/xlp/ahci-init-xlp2.c sata_set_glue_reg(regbase, SATA_INT, val); val 365 arch/mips/netlogic/xlp/ahci-init-xlp2.c u32 val; val 374 arch/mips/netlogic/xlp/ahci-init-xlp2.c val = nlm_read_sata_reg(regbase, SATA_INT); val 375 arch/mips/netlogic/xlp/ahci-init-xlp2.c sata_set_glue_reg(regbase, SATA_INT, val); val 163 arch/mips/netlogic/xlp/ahci-init.c uint32_t val = 0; val 167 arch/mips/netlogic/xlp/ahci-init.c val = nlm_read_sata_reg(regbase, SATA_INT); val 168 arch/mips/netlogic/xlp/ahci-init.c sata_set_glue_reg(regbase, SATA_INT, val); val 183 arch/mips/netlogic/xlp/ahci-init.c uint32_t val; val 190 arch/mips/netlogic/xlp/ahci-init.c val = nlm_read_sata_reg(regbase, SATA_INT); val 191 arch/mips/netlogic/xlp/ahci-init.c sata_set_glue_reg(regbase, SATA_INT, val); val 185 arch/mips/netlogic/xlp/nlm_hal.c uint32_t val; val 188 arch/mips/netlogic/xlp/nlm_hal.c val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG); val 189 arch/mips/netlogic/xlp/nlm_hal.c if (val == 0xffffffff) { val 192 arch/mips/netlogic/xlp/nlm_hal.c irt = val & 0xffff; val 469 arch/mips/netlogic/xlp/nlm_hal.c uint32_t val; val 490 arch/mips/netlogic/xlp/nlm_hal.c val = nlm_read_bridge_reg(bridgebase, xlatreg); val 491 arch/mips/netlogic/xlp/nlm_hal.c n = (val >> 1) & 0x3; val 495 arch/mips/netlogic/xlp/nlm_hal.c val = nlm_read_bridge_reg(bridgebase, barreg); val 496 arch/mips/netlogic/xlp/nlm_hal.c val = (val >> 12) & 0xfffff; val 497 arch/mips/netlogic/xlp/nlm_hal.c base = (uint64_t) val << 20; val 498 arch/mips/netlogic/xlp/nlm_hal.c val = nlm_read_bridge_reg(bridgebase, limreg); val 499 arch/mips/netlogic/xlp/nlm_hal.c val = (val >> 12) & 0xfffff; val 500 arch/mips/netlogic/xlp/nlm_hal.c if (val == 0) /* BAR not used */ val 502 arch/mips/netlogic/xlp/nlm_hal.c lim = ((uint64_t)val + 1) << 20; val 145 arch/mips/netlogic/xlp/usb-init-xlp2.c u32 val; val 150 arch/mips/netlogic/xlp/usb-init-xlp2.c val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV); val 151 arch/mips/netlogic/xlp/usb-init-xlp2.c val &= ~(0x3f << XLPII_FSEL); val 152 arch/mips/netlogic/xlp/usb-init-xlp2.c val |= (0x27 << XLPII_FSEL); val 153 arch/mips/netlogic/xlp/usb-init-xlp2.c nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val); val 155 arch/mips/netlogic/xlp/usb-init-xlp2.c val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG); val 156 arch/mips/netlogic/xlp/usb-init-xlp2.c val |= (1 << XLPII_VVLD); val 157 arch/mips/netlogic/xlp/usb-init-xlp2.c nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val); val 160 arch/mips/netlogic/xlp/usb-init-xlp2.c val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST); val 161 arch/mips/netlogic/xlp/usb-init-xlp2.c val &= (XLPII_ATERESET | XLPII_LOOPEN | XLPII_TESTPDHSP val 163 arch/mips/netlogic/xlp/usb-init-xlp2.c nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val); val 166 arch/mips/netlogic/xlp/usb-init-xlp2.c val = XLPII_VAUXRST | XLPII_VCCRST | (1 << XLPII_NUM2PORT) val 169 arch/mips/netlogic/xlp/usb-init-xlp2.c nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val); val 188 arch/mips/netlogic/xlp/usb-init-xlp2.c val = readl(corebase + 0xc110); val 189 arch/mips/netlogic/xlp/usb-init-xlp2.c val &= ~(0x3 << 12); val 190 arch/mips/netlogic/xlp/usb-init-xlp2.c val |= (1 << 12); val 191 arch/mips/netlogic/xlp/usb-init-xlp2.c writel(val, corebase + 0xc110); val 195 arch/mips/netlogic/xlp/usb-init-xlp2.c val = readl(corebase + 0xc200); val 196 arch/mips/netlogic/xlp/usb-init-xlp2.c val &= ~(1 << 6); val 197 arch/mips/netlogic/xlp/usb-init-xlp2.c writel(val, corebase + 0xc200); val 201 arch/mips/netlogic/xlp/usb-init-xlp2.c val = readl(corebase + 0xc2c0); val 202 arch/mips/netlogic/xlp/usb-init-xlp2.c val &= ~(1 << 17); val 203 arch/mips/netlogic/xlp/usb-init-xlp2.c writel(val, corebase + 0xc2c0); val 72 arch/mips/netlogic/xlp/usb-init.c uint32_t val; val 76 arch/mips/netlogic/xlp/usb-init.c val = nlm_read_usb_reg(port_addr, USB_INT_EN); val 77 arch/mips/netlogic/xlp/usb-init.c val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | val 79 arch/mips/netlogic/xlp/usb-init.c nlm_write_usb_reg(port_addr, USB_INT_EN, val); val 85 arch/mips/netlogic/xlp/usb-init.c uint32_t val; val 89 arch/mips/netlogic/xlp/usb-init.c val = nlm_read_usb_reg(port_addr, USB_PHY_0); val 90 arch/mips/netlogic/xlp/usb-init.c val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1); val 91 arch/mips/netlogic/xlp/usb-init.c nlm_write_usb_reg(port_addr, USB_PHY_0, val); val 94 arch/mips/netlogic/xlp/usb-init.c val = nlm_read_usb_reg(port_addr, USB_CTL_0); val 95 arch/mips/netlogic/xlp/usb-init.c val &= ~(USB_CONTROLLER_RESET); val 96 arch/mips/netlogic/xlp/usb-init.c val |= 0x4; val 97 arch/mips/netlogic/xlp/usb-init.c nlm_write_usb_reg(port_addr, USB_CTL_0, val); val 151 arch/mips/netlogic/xlr/platform.c uint32_t val; val 167 arch/mips/netlogic/xlr/platform.c val = nlm_read_reg(gpio_mmio, 21); val 168 arch/mips/netlogic/xlr/platform.c if (((val >> 22) & 0x01) == 0) { val 32 arch/mips/oprofile/op_model_loongson2.c #define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val) val 34 arch/mips/oprofile/op_model_loongson2.c #define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val) val 33 arch/mips/oprofile/op_model_loongson3.c #define write_c0_perflo1(val) __write_64bit_c0_register($25, 0, val) val 35 arch/mips/oprofile/op_model_loongson3.c #define write_c0_perfhi1(val) __write_64bit_c0_register($25, 1, val) val 39 arch/mips/oprofile/op_model_loongson3.c #define write_c0_perflo2(val) __write_64bit_c0_register($25, 2, val) val 41 arch/mips/oprofile/op_model_loongson3.c #define write_c0_perfhi2(val) __write_64bit_c0_register($25, 3, val) val 49 arch/mips/pci/fixup-fuloong2e.c unsigned int val; val 52 arch/mips/pci/fixup-fuloong2e.c pci_read_config_dword(pdev, 0xe0, &val); val 53 arch/mips/pci/fixup-fuloong2e.c pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4); val 181 arch/mips/pci/fixup-fuloong2e.c unsigned int val; val 188 arch/mips/pci/fixup-fuloong2e.c pci_read_config_dword(pdev, 0x4, &val); val 189 arch/mips/pci/fixup-fuloong2e.c pci_write_config_dword(pdev, 0x4, val | 1); val 205 arch/mips/pci/fixup-fuloong2e.c pci_read_config_dword(pdev, 0x2c, &val); val 138 arch/mips/pci/fixup-lemote2f.c unsigned int val; val 140 arch/mips/pci/fixup-lemote2f.c pci_read_config_dword(pdev, 0xe0, &val); val 142 arch/mips/pci/fixup-lemote2f.c pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2); val 250 arch/mips/pci/msi-xlp.c u32 val; val 253 arch/mips/pci/msi-xlp.c val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0); val 254 arch/mips/pci/msi-xlp.c if ((val & 0x200) == 0) { val 255 arch/mips/pci/msi-xlp.c val |= 0x200; /* MSI Interrupt enable */ val 256 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val); val 259 arch/mips/pci/msi-xlp.c val = nlm_read_reg(lnkbase, PCIE_INT_EN0); val 260 arch/mips/pci/msi-xlp.c if ((val & 0x200) == 0) { val 261 arch/mips/pci/msi-xlp.c val |= 0x200; val 262 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_INT_EN0, val); val 266 arch/mips/pci/msi-xlp.c val = nlm_read_reg(lnkbase, 0x1); /* CMD */ val 267 arch/mips/pci/msi-xlp.c if ((val & 0x0400) == 0) { val 268 arch/mips/pci/msi-xlp.c val |= 0x0400; val 269 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, 0x1, val); val 273 arch/mips/pci/msi-xlp.c val = nlm_read_pci_reg(lnkbase, 0xf); val 274 arch/mips/pci/msi-xlp.c val &= ~0x1fu; val 275 arch/mips/pci/msi-xlp.c val |= (1 << 8) | lirq; val 276 arch/mips/pci/msi-xlp.c nlm_write_pci_reg(lnkbase, 0xf, val); val 283 arch/mips/pci/msi-xlp.c val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP); val 284 arch/mips/pci/msi-xlp.c if ((val & (1 << 16)) == 0) { val 285 arch/mips/pci/msi-xlp.c val |= 0xb << 16; /* mmc32, msi enable */ val 286 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val); val 348 arch/mips/pci/msi-xlp.c u32 val; val 350 arch/mips/pci/msi-xlp.c val = nlm_read_reg(lnkbase, 0x2C); val 351 arch/mips/pci/msi-xlp.c if ((val & 0x80000000U) == 0) { val 352 arch/mips/pci/msi-xlp.c val |= 0x80000000U; val 353 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, 0x2C, val); val 357 arch/mips/pci/msi-xlp.c val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0); val 358 arch/mips/pci/msi-xlp.c if ((val & 0x200) == 0) { val 359 arch/mips/pci/msi-xlp.c val |= 0x200; /* MSI Interrupt enable */ val 360 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val); val 363 arch/mips/pci/msi-xlp.c val = nlm_read_reg(lnkbase, PCIE_INT_EN0); val 364 arch/mips/pci/msi-xlp.c if ((val & 0x200) == 0) { val 365 arch/mips/pci/msi-xlp.c val |= 0x200; /* MSI Interrupt enable */ val 366 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, PCIE_INT_EN0, val); val 370 arch/mips/pci/msi-xlp.c val = nlm_read_reg(lnkbase, 0x1); /* CMD */ val 371 arch/mips/pci/msi-xlp.c if ((val & 0x0400) == 0) { val 372 arch/mips/pci/msi-xlp.c val |= 0x0400; val 373 arch/mips/pci/msi-xlp.c nlm_write_reg(lnkbase, 0x1, val); val 377 arch/mips/pci/msi-xlp.c val = nlm_read_pci_reg(lnkbase, 0xf); val 378 arch/mips/pci/msi-xlp.c val &= ~0x1fu; val 379 arch/mips/pci/msi-xlp.c val |= (1 << 8) | lirq; val 380 arch/mips/pci/msi-xlp.c nlm_write_pci_reg(lnkbase, 0xf, val); val 470 arch/mips/pci/msi-xlp.c int irq, i, irt, msixvec, val; val 493 arch/mips/pci/msi-xlp.c val = ((node * nlm_threads_per_node()) << 7 | val 496 arch/mips/pci/msi-xlp.c (link * XLP_MSIXVEC_PER_LINK)), val); val 39 arch/mips/pci/ops-bcm63xx.c static int preprocess_write(u32 orig_data, u32 val, int where, val 48 arch/mips/pci/ops-bcm63xx.c (val << ((where & 3) << 3)); val 52 arch/mips/pci/ops-bcm63xx.c (val << ((where & 3) << 3)); val 55 arch/mips/pci/ops-bcm63xx.c ret = val; val 68 arch/mips/pci/ops-bcm63xx.c u32 val; val 85 arch/mips/pci/ops-bcm63xx.c val = (reg << MPI_L2PCFG_REG_SHIFT); val 86 arch/mips/pci/ops-bcm63xx.c val |= (func << MPI_L2PCFG_FUNC_SHIFT); val 87 arch/mips/pci/ops-bcm63xx.c val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT); val 88 arch/mips/pci/ops-bcm63xx.c val |= MPI_L2PCFG_CFG_USEREG_MASK; val 89 arch/mips/pci/ops-bcm63xx.c val |= MPI_L2PCFG_CFG_SEL_MASK; val 93 arch/mips/pci/ops-bcm63xx.c val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT); val 95 arch/mips/pci/ops-bcm63xx.c bcm_mpi_writel(val, MPI_L2PCFG_REG); val 102 arch/mips/pci/ops-bcm63xx.c u32 *val) val 116 arch/mips/pci/ops-bcm63xx.c *val = postprocess_read(data, where, size); val 123 arch/mips/pci/ops-bcm63xx.c u32 val) val 135 arch/mips/pci/ops-bcm63xx.c data = preprocess_write(data, val, where, size); val 148 arch/mips/pci/ops-bcm63xx.c int where, int size, u32 *val) val 158 arch/mips/pci/ops-bcm63xx.c where, size, val); val 162 arch/mips/pci/ops-bcm63xx.c int where, int size, u32 val) val 172 arch/mips/pci/ops-bcm63xx.c where, size, val); val 208 arch/mips/pci/ops-bcm63xx.c static int fake_cb_bridge_read(int where, int size, u32 *val) val 284 arch/mips/pci/ops-bcm63xx.c *val = postprocess_read(data, where, size); val 291 arch/mips/pci/ops-bcm63xx.c static int fake_cb_bridge_write(int where, int size, u32 val) val 301 arch/mips/pci/ops-bcm63xx.c data = preprocess_write(data, val, where, size); val 363 arch/mips/pci/ops-bcm63xx.c int where, int size, u32 *val) val 369 arch/mips/pci/ops-bcm63xx.c return fake_cb_bridge_read(where, size, val); val 381 arch/mips/pci/ops-bcm63xx.c where, size, val); val 387 arch/mips/pci/ops-bcm63xx.c int where, int size, u32 val) val 391 arch/mips/pci/ops-bcm63xx.c return fake_cb_bridge_write(where, size, val); val 399 arch/mips/pci/ops-bcm63xx.c where, size, val); val 417 arch/mips/pci/ops-bcm63xx.c u32 val; val 455 arch/mips/pci/ops-bcm63xx.c val = bcm_mpi_readl(MPI_L2PIOREMAP_REG); val 457 arch/mips/pci/ops-bcm63xx.c val |= MPI_L2PREMAP_IS_CARDBUS_MASK; val 459 arch/mips/pci/ops-bcm63xx.c val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK; val 460 arch/mips/pci/ops-bcm63xx.c bcm_mpi_writel(val, MPI_L2PIOREMAP_REG); val 484 arch/mips/pci/ops-bcm63xx.c int where, int size, u32 *val) val 497 arch/mips/pci/ops-bcm63xx.c *val = postprocess_read(data, where, size); val 504 arch/mips/pci/ops-bcm63xx.c int where, int size, u32 val) val 518 arch/mips/pci/ops-bcm63xx.c data = preprocess_write(data, val, where, size); val 90 arch/mips/pci/ops-bonito64.c int where, int size, u32 * val) val 104 arch/mips/pci/ops-bonito64.c *val = (data >> ((where & 3) << 3)) & 0xff; val 106 arch/mips/pci/ops-bonito64.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 108 arch/mips/pci/ops-bonito64.c *val = data; val 114 arch/mips/pci/ops-bonito64.c int where, int size, u32 val) val 124 arch/mips/pci/ops-bonito64.c data = val; val 132 arch/mips/pci/ops-bonito64.c (val << ((where & 3) << 3)); val 135 arch/mips/pci/ops-bonito64.c (val << ((where & 3) << 3)); val 70 arch/mips/pci/ops-emma2rh.c int size, uint32_t * val) val 77 arch/mips/pci/ops-emma2rh.c *val = 0xffffffffU; val 93 arch/mips/pci/ops-emma2rh.c *val = (data >> ((where & 3) << 3)) & 0xffU; val 96 arch/mips/pci/ops-emma2rh.c *val = (data >> ((where & 2) << 3)) & 0xffffU; val 99 arch/mips/pci/ops-emma2rh.c *val = data; val 115 arch/mips/pci/ops-emma2rh.c int size, u32 val) val 140 arch/mips/pci/ops-emma2rh.c data |= ((val & 0xffU) << shift); val 145 arch/mips/pci/ops-emma2rh.c data |= ((val & 0xffffU) << shift); val 148 arch/mips/pci/ops-emma2rh.c data = val; val 92 arch/mips/pci/ops-gt64xxx_pci0.c int where, int size, u32 * val) val 101 arch/mips/pci/ops-gt64xxx_pci0.c *val = (data >> ((where & 3) << 3)) & 0xff; val 103 arch/mips/pci/ops-gt64xxx_pci0.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 105 arch/mips/pci/ops-gt64xxx_pci0.c *val = data; val 111 arch/mips/pci/ops-gt64xxx_pci0.c int where, int size, u32 val) val 116 arch/mips/pci/ops-gt64xxx_pci0.c data = val; val 124 arch/mips/pci/ops-gt64xxx_pci0.c (val << ((where & 3) << 3)); val 127 arch/mips/pci/ops-gt64xxx_pci0.c (val << ((where & 3) << 3)); val 72 arch/mips/pci/ops-lantiq.c int where, int size, u32 *val) val 80 arch/mips/pci/ops-lantiq.c *val = (data >> ((where & 3) << 3)) & 0xff; val 82 arch/mips/pci/ops-lantiq.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 84 arch/mips/pci/ops-lantiq.c *val = data; val 90 arch/mips/pci/ops-lantiq.c int where, int size, u32 val) val 95 arch/mips/pci/ops-lantiq.c data = val; val 103 arch/mips/pci/ops-lantiq.c (val << ((where & 3) << 3)); val 106 arch/mips/pci/ops-lantiq.c (val << ((where & 3) << 3)); val 119 arch/mips/pci/ops-loongson2.c int where, int size, u32 *val) val 133 arch/mips/pci/ops-loongson2.c *val = (data >> ((where & 3) << 3)) & 0xff; val 135 arch/mips/pci/ops-loongson2.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 137 arch/mips/pci/ops-loongson2.c *val = data; val 143 arch/mips/pci/ops-loongson2.c int where, int size, u32 val) val 153 arch/mips/pci/ops-loongson2.c data = val; val 161 arch/mips/pci/ops-loongson2.c (val << ((where & 3) << 3)); val 164 arch/mips/pci/ops-loongson2.c (val << ((where & 3) << 3)); val 66 arch/mips/pci/ops-loongson3.c int where, int size, u32 *val) val 76 arch/mips/pci/ops-loongson3.c *val = (data >> ((where & 3) << 3)) & 0xff; val 78 arch/mips/pci/ops-loongson3.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 80 arch/mips/pci/ops-loongson3.c *val = data; val 86 arch/mips/pci/ops-loongson3.c int where, int size, u32 val) val 92 arch/mips/pci/ops-loongson3.c data = val; val 101 arch/mips/pci/ops-loongson3.c (val << ((where & 3) << 3)); val 104 arch/mips/pci/ops-loongson3.c (val << ((where & 3) << 3)); val 41 arch/mips/pci/ops-mace.c int reg, int size, u32 *val) val 50 arch/mips/pci/ops-mace.c *val = mace->pci.config_data.b[(reg & 3) ^ 3]; val 53 arch/mips/pci/ops-mace.c *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1]; val 56 arch/mips/pci/ops-mace.c *val = mace->pci.config_data.l; val 68 arch/mips/pci/ops-mace.c *val |= 0x1000; val 70 arch/mips/pci/ops-mace.c DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); val 77 arch/mips/pci/ops-mace.c int reg, int size, u32 val) val 82 arch/mips/pci/ops-mace.c mace->pci.config_data.b[(reg & 3) ^ 3] = val; val 85 arch/mips/pci/ops-mace.c mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val; val 88 arch/mips/pci/ops-mace.c mace->pci.config_data.l = val; val 92 arch/mips/pci/ops-mace.c DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val); val 76 arch/mips/pci/ops-msc.c int where, int size, u32 * val) val 90 arch/mips/pci/ops-msc.c *val = (data >> ((where & 3) << 3)) & 0xff; val 92 arch/mips/pci/ops-msc.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 94 arch/mips/pci/ops-msc.c *val = data; val 100 arch/mips/pci/ops-msc.c int where, int size, u32 val) val 110 arch/mips/pci/ops-msc.c data = val; val 118 arch/mips/pci/ops-msc.c (val << ((where & 3) << 3)); val 121 arch/mips/pci/ops-msc.c (val << ((where & 3) << 3)); val 18 arch/mips/pci/ops-nile4.c struct pci_bus *bus, unsigned int devfn, int where, u32 *val) val 32 arch/mips/pci/ops-nile4.c vrc_pciregs[(0x200 + where) >> 2] = *val; val 34 arch/mips/pci/ops-nile4.c *val = vrc_pciregs[(0x200 + where) >> 2]; val 59 arch/mips/pci/ops-nile4.c *(u32 *) adr = *val; val 61 arch/mips/pci/ops-nile4.c *val = *(u32 *) adr; val 76 arch/mips/pci/ops-nile4.c int where, int size, u32 *val) val 92 arch/mips/pci/ops-nile4.c *val = (data >> ((where & 3) << 3)) & 0xff; val 94 arch/mips/pci/ops-nile4.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 96 arch/mips/pci/ops-nile4.c *val = data; val 102 arch/mips/pci/ops-nile4.c int where, int size, u32 val) val 119 arch/mips/pci/ops-nile4.c (val << ((where & 3) << 3)); val 122 arch/mips/pci/ops-nile4.c (val << ((where & 3) << 3)); val 124 arch/mips/pci/ops-nile4.c data = val; val 464 arch/mips/pci/ops-pmcmsp.c u32 *val) val 475 arch/mips/pci/ops-pmcmsp.c *val = 0xFFFFFFFF; val 479 arch/mips/pci/ops-pmcmsp.c *val = (data >> ((where & 3) << 3)) & 0x0ff; val 512 arch/mips/pci/ops-pmcmsp.c u32 *val) val 523 arch/mips/pci/ops-pmcmsp.c *val = 0xFFFFFFFF; val 534 arch/mips/pci/ops-pmcmsp.c *val = 0xFFFFFFFF; val 538 arch/mips/pci/ops-pmcmsp.c *val = (data >> ((where & 3) << 3)) & 0x0ffff; val 569 arch/mips/pci/ops-pmcmsp.c u32 *val) val 575 arch/mips/pci/ops-pmcmsp.c *val = 0xFFFFFFFF; val 586 arch/mips/pci/ops-pmcmsp.c *val = 0xFFFFFFFF; val 590 arch/mips/pci/ops-pmcmsp.c *val = data; val 622 arch/mips/pci/ops-pmcmsp.c u8 val) val 633 arch/mips/pci/ops-pmcmsp.c (val << ((where & 3) << 3)); val 671 arch/mips/pci/ops-pmcmsp.c u16 val) val 686 arch/mips/pci/ops-pmcmsp.c (val << ((where & 3) << 3)); val 723 arch/mips/pci/ops-pmcmsp.c u32 val) val 731 arch/mips/pci/ops-pmcmsp.c where, &val)) val 766 arch/mips/pci/ops-pmcmsp.c u32 *val) val 769 arch/mips/pci/ops-pmcmsp.c if (msp_pcibios_read_config_byte(bus, devfn, where, val)) { val 773 arch/mips/pci/ops-pmcmsp.c if (msp_pcibios_read_config_word(bus, devfn, where, val)) { val 777 arch/mips/pci/ops-pmcmsp.c if (msp_pcibios_read_config_dword(bus, devfn, where, val)) { val 781 arch/mips/pci/ops-pmcmsp.c *val = 0xFFFFFFFF; val 817 arch/mips/pci/ops-pmcmsp.c u32 val) val 821 arch/mips/pci/ops-pmcmsp.c where, (u8)(0xFF & val))) { val 826 arch/mips/pci/ops-pmcmsp.c where, (u16)(0xFFFF & val))) { val 830 arch/mips/pci/ops-pmcmsp.c if (msp_pcibios_write_config_dword(bus, devfn, where, val)) { val 73 arch/mips/pci/ops-rc32434.c int where, u8 *val) val 79 arch/mips/pci/ops-rc32434.c *val = (data >> ((where & 3) << 3)) & 0xff; val 84 arch/mips/pci/ops-rc32434.c int where, u16 *val) val 90 arch/mips/pci/ops-rc32434.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 95 arch/mips/pci/ops-rc32434.c int where, u32 *val) val 108 arch/mips/pci/ops-rc32434.c ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); val 130 arch/mips/pci/ops-rc32434.c u8 val) val 138 arch/mips/pci/ops-rc32434.c (val << ((where & 3) << 3)); val 149 arch/mips/pci/ops-rc32434.c u16 val) val 157 arch/mips/pci/ops-rc32434.c (val << ((where & 3) << 3)); val 169 arch/mips/pci/ops-rc32434.c u32 val) val 171 arch/mips/pci/ops-rc32434.c if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) val 178 arch/mips/pci/ops-rc32434.c int where, int size, u32 *val) val 182 arch/mips/pci/ops-rc32434.c return read_config_byte(bus, devfn, where, (u8 *) val); val 184 arch/mips/pci/ops-rc32434.c return read_config_word(bus, devfn, where, (u16 *) val); val 186 arch/mips/pci/ops-rc32434.c return read_config_dword(bus, devfn, where, val); val 191 arch/mips/pci/ops-rc32434.c int where, int size, u32 val) val 195 arch/mips/pci/ops-rc32434.c return write_config_byte(bus, devfn, where, (u8) val); val 197 arch/mips/pci/ops-rc32434.c return write_config_word(bus, devfn, where, (u16) val); val 199 arch/mips/pci/ops-rc32434.c return write_config_dword(bus, devfn, where, val); val 41 arch/mips/pci/ops-sni.c int size, u32 * val) val 50 arch/mips/pci/ops-sni.c *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); val 53 arch/mips/pci/ops-sni.c *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); val 56 arch/mips/pci/ops-sni.c *val = inl(PCIMT_CONFIG_DATA); val 64 arch/mips/pci/ops-sni.c int size, u32 val) val 73 arch/mips/pci/ops-sni.c outb(val, PCIMT_CONFIG_DATA + (reg & 3)); val 76 arch/mips/pci/ops-sni.c outw(val, PCIMT_CONFIG_DATA + (reg & 2)); val 79 arch/mips/pci/ops-sni.c outl(val, PCIMT_CONFIG_DATA); val 101 arch/mips/pci/ops-sni.c int size, u32 * val) val 125 arch/mips/pci/ops-sni.c *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); val 128 arch/mips/pci/ops-sni.c *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); val 131 arch/mips/pci/ops-sni.c *val = inl(PCIMT_CONFIG_DATA); val 138 arch/mips/pci/ops-sni.c int size, u32 val) val 147 arch/mips/pci/ops-sni.c outb(val, PCIMT_CONFIG_DATA + (reg & 3)); val 150 arch/mips/pci/ops-sni.c outw(val, PCIMT_CONFIG_DATA + (reg & 2)); val 153 arch/mips/pci/ops-sni.c outl(val, PCIMT_CONFIG_DATA); val 77 arch/mips/pci/ops-tx3927.c int where, int size, u32 * val) val 80 arch/mips/pci/ops-tx3927.c *val = 0xffffffff; val 86 arch/mips/pci/ops-tx3927.c *val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)); val 90 arch/mips/pci/ops-tx3927.c *val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3))); val 94 arch/mips/pci/ops-tx3927.c *val = le32_to_cpu(tx3927_pcicptr->icd); val 102 arch/mips/pci/ops-tx3927.c int where, int size, u32 val) val 109 arch/mips/pci/ops-tx3927.c *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val; val 114 arch/mips/pci/ops-tx3927.c cpu_to_le16(val); val 118 arch/mips/pci/ops-tx3927.c tx3927_pcicptr->icd = cpu_to_le32(val); val 112 arch/mips/pci/ops-tx4927.c static void icd_writeb(u8 val, int offset, val 118 arch/mips/pci/ops-tx4927.c __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); val 120 arch/mips/pci/ops-tx4927.c static void icd_writew(u16 val, int offset, val 126 arch/mips/pci/ops-tx4927.c __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); val 128 arch/mips/pci/ops-tx4927.c static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr) val 130 arch/mips/pci/ops-tx4927.c __raw_writel(val, &pcicptr->g2pcfgdata); val 140 arch/mips/pci/ops-tx4927.c int where, int size, u32 *val) val 145 arch/mips/pci/ops-tx4927.c *val = 0xffffffff; val 150 arch/mips/pci/ops-tx4927.c *val = icd_readb(where & 3, pcicptr); val 153 arch/mips/pci/ops-tx4927.c *val = icd_readw(where & 3, pcicptr); val 156 arch/mips/pci/ops-tx4927.c *val = icd_readl(pcicptr); val 162 arch/mips/pci/ops-tx4927.c int where, int size, u32 val) val 170 arch/mips/pci/ops-tx4927.c icd_writeb(val, where & 3, pcicptr); val 173 arch/mips/pci/ops-tx4927.c icd_writew(val, where & 3, pcicptr); val 176 arch/mips/pci/ops-tx4927.c icd_writel(val, pcicptr); val 199 arch/mips/pci/ops-tx4927.c u8 val = 0; val 200 arch/mips/pci/ops-tx4927.c if (kstrtou8(str + 7, 0, &val) == 0) val 201 arch/mips/pci/ops-tx4927.c tx4927_pci_opts.trdyto = val; val 205 arch/mips/pci/ops-tx4927.c u8 val = 0; val 206 arch/mips/pci/ops-tx4927.c if (kstrtou8(str + 8, 0, &val) == 0) val 207 arch/mips/pci/ops-tx4927.c tx4927_pci_opts.retryto = val; val 211 arch/mips/pci/ops-tx4927.c u16 val; val 212 arch/mips/pci/ops-tx4927.c if (kstrtou16(str + 5, 0, &val) == 0) val 213 arch/mips/pci/ops-tx4927.c tx4927_pci_opts.gbwc = val; val 49 arch/mips/pci/ops-vr41xx.c int size, uint32_t *val) val 53 arch/mips/pci/ops-vr41xx.c *val = 0xffffffffU; val 61 arch/mips/pci/ops-vr41xx.c *val = (data >> ((where & 3) << 3)) & 0xffU; val 64 arch/mips/pci/ops-vr41xx.c *val = (data >> ((where & 2) << 3)) & 0xffffU; val 67 arch/mips/pci/ops-vr41xx.c *val = data; val 77 arch/mips/pci/ops-vr41xx.c int size, uint32_t val) val 91 arch/mips/pci/ops-vr41xx.c data |= ((val & 0xffU) << shift); val 96 arch/mips/pci/ops-vr41xx.c data |= ((val & 0xffffU) << shift); val 99 arch/mips/pci/ops-vr41xx.c data = val; val 189 arch/mips/pci/pci-alchemy.c int where, u8 *val) val 198 arch/mips/pci/pci-alchemy.c *val = data & 0xff; val 203 arch/mips/pci/pci-alchemy.c int where, u16 *val) val 210 arch/mips/pci/pci-alchemy.c *val = data & 0xffff; val 215 arch/mips/pci/pci-alchemy.c int where, u32 *val) val 217 arch/mips/pci/pci-alchemy.c return config_access(PCI_ACCESS_READ, bus, devfn, where, val); val 221 arch/mips/pci/pci-alchemy.c int where, u8 val) val 229 arch/mips/pci/pci-alchemy.c (val << ((where & 3) << 3)); val 238 arch/mips/pci/pci-alchemy.c int where, u16 val) val 246 arch/mips/pci/pci-alchemy.c (val << ((where & 3) << 3)); val 255 arch/mips/pci/pci-alchemy.c int where, u32 val) val 257 arch/mips/pci/pci-alchemy.c return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); val 261 arch/mips/pci/pci-alchemy.c int where, int size, u32 *val) val 268 arch/mips/pci/pci-alchemy.c *val = _val; val 275 arch/mips/pci/pci-alchemy.c *val = _val; val 279 arch/mips/pci/pci-alchemy.c return read_config_dword(bus, devfn, where, val); val 284 arch/mips/pci/pci-alchemy.c int where, int size, u32 val) val 288 arch/mips/pci/pci-alchemy.c return write_config_byte(bus, devfn, where, (u8) val); val 290 arch/mips/pci/pci-alchemy.c return write_config_word(bus, devfn, where, (u16) val); val 292 arch/mips/pci/pci-alchemy.c return write_config_dword(bus, devfn, where, val); val 367 arch/mips/pci/pci-alchemy.c unsigned long val; val 435 arch/mips/pci/pci-alchemy.c val = __raw_readl(ctx->regs + PCI_REG_CONFIG); val 436 arch/mips/pci/pci-alchemy.c val |= PCI_CONFIG_NC; val 437 arch/mips/pci/pci-alchemy.c __raw_writel(val, ctx->regs + PCI_REG_CONFIG); val 473 arch/mips/pci/pci-alchemy.c val = __raw_readl(ctx->regs + PCI_REG_CONFIG); val 474 arch/mips/pci/pci-alchemy.c val &= ~pd->pci_cfg_clr; val 475 arch/mips/pci/pci-alchemy.c val |= pd->pci_cfg_set; val 476 arch/mips/pci/pci-alchemy.c val &= ~PCI_CONFIG_PD; /* clear disable bit */ val 477 arch/mips/pci/pci-alchemy.c __raw_writel(val, ctx->regs + PCI_REG_CONFIG); val 196 arch/mips/pci/pci-ar2315.c u32 val) val 198 arch/mips/pci/pci-ar2315.c __raw_writel(val, apc->mmr_mem + reg); val 202 arch/mips/pci/pci-ar2315.c u32 mask, u32 val) val 207 arch/mips/pci/pci-ar2315.c ret |= val; val 267 arch/mips/pci/pci-ar2315.c unsigned devfn, int where, u32 *val) val 269 arch/mips/pci/pci-ar2315.c return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val, val 274 arch/mips/pci/pci-ar2315.c unsigned devfn, int where, u32 val) val 276 arch/mips/pci/pci-ar2315.c return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val, val 108 arch/mips/pci/pci-bcm1480.c int where, int size, u32 * val) val 123 arch/mips/pci/pci-bcm1480.c *val = (data >> ((where & 3) << 3)) & 0xff; val 125 arch/mips/pci/pci-bcm1480.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 127 arch/mips/pci/pci-bcm1480.c *val = data; val 133 arch/mips/pci/pci-bcm1480.c int where, int size, u32 val) val 150 arch/mips/pci/pci-bcm1480.c (val << ((where & 3) << 3)); val 153 arch/mips/pci/pci-bcm1480.c (val << ((where & 3) << 3)); val 155 arch/mips/pci/pci-bcm1480.c data = val; val 97 arch/mips/pci/pci-bcm1480ht.c int where, int size, u32 * val) val 112 arch/mips/pci/pci-bcm1480ht.c *val = (data >> ((where & 3) << 3)) & 0xff; val 114 arch/mips/pci/pci-bcm1480ht.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 116 arch/mips/pci/pci-bcm1480ht.c *val = data; val 122 arch/mips/pci/pci-bcm1480ht.c int where, int size, u32 val) val 139 arch/mips/pci/pci-bcm1480ht.c (val << ((where & 3) << 3)); val 142 arch/mips/pci/pci-bcm1480ht.c (val << ((where & 3) << 3)); val 144 arch/mips/pci/pci-bcm1480ht.c data = val; val 109 arch/mips/pci/pci-bcm63xx.c static void bcm63xx_int_cfg_writel(u32 val, u32 reg) val 116 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val, MPI_PCICFGDATA_REG); val 123 arch/mips/pci/pci-bcm63xx.c u32 val; val 132 arch/mips/pci/pci-bcm63xx.c val = bcm_misc_readl(reg); val 133 arch/mips/pci/pci-bcm63xx.c val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; val 134 arch/mips/pci/pci-bcm63xx.c bcm_misc_writel(val, reg); val 152 arch/mips/pci/pci-bcm63xx.c u32 val; val 164 arch/mips/pci/pci-bcm63xx.c val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); val 165 arch/mips/pci/pci-bcm63xx.c val |= OPT1_RD_BE_OPT_EN; val 166 arch/mips/pci/pci-bcm63xx.c val |= OPT1_RD_REPLY_BE_FIX_EN; val 167 arch/mips/pci/pci-bcm63xx.c val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN; val 168 arch/mips/pci/pci-bcm63xx.c val |= OPT1_L1_INT_STATUS_MASK_POL; val 169 arch/mips/pci/pci-bcm63xx.c bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG); val 172 arch/mips/pci/pci-bcm63xx.c val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG); val 173 arch/mips/pci/pci-bcm63xx.c val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D; val 174 arch/mips/pci/pci-bcm63xx.c bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG); val 176 arch/mips/pci/pci-bcm63xx.c val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG); val 178 arch/mips/pci/pci-bcm63xx.c val |= OPT2_TX_CREDIT_CHK_EN; val 179 arch/mips/pci/pci-bcm63xx.c val |= OPT2_UBUS_UR_DECODE_DIS; val 182 arch/mips/pci/pci-bcm63xx.c val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT); val 183 arch/mips/pci/pci-bcm63xx.c val |= OPT2_CFG_TYPE1_BD_SEL; val 184 arch/mips/pci/pci-bcm63xx.c bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); val 187 arch/mips/pci/pci-bcm63xx.c val = bcm_pcie_readl(PCIE_IDVAL3_REG); val 188 arch/mips/pci/pci-bcm63xx.c val &= ~IDVAL3_CLASS_CODE_MASK; val 189 arch/mips/pci/pci-bcm63xx.c val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT); val 190 arch/mips/pci/pci-bcm63xx.c bcm_pcie_writel(val, PCIE_IDVAL3_REG); val 193 arch/mips/pci/pci-bcm63xx.c val = bcm_pcie_readl(PCIE_CONFIG2_REG); val 194 arch/mips/pci/pci-bcm63xx.c val &= ~CONFIG2_BAR1_SIZE_MASK; val 195 arch/mips/pci/pci-bcm63xx.c bcm_pcie_writel(val, PCIE_CONFIG2_REG); val 198 arch/mips/pci/pci-bcm63xx.c val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; val 199 arch/mips/pci/pci-bcm63xx.c val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; val 200 arch/mips/pci/pci-bcm63xx.c val |= BASEMASK_REMAP_EN; val 201 arch/mips/pci/pci-bcm63xx.c bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); val 203 arch/mips/pci/pci-bcm63xx.c val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; val 204 arch/mips/pci/pci-bcm63xx.c bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); val 214 arch/mips/pci/pci-bcm63xx.c u32 val; val 229 arch/mips/pci/pci-bcm63xx.c val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK; val 230 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG); val 232 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG); val 236 arch/mips/pci/pci-bcm63xx.c val = bcm_pcmcia_readl(PCMCIA_C1_REG); val 237 arch/mips/pci/pci-bcm63xx.c val &= ~PCMCIA_C1_CBIDSEL_MASK; val 238 arch/mips/pci/pci-bcm63xx.c val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT); val 239 arch/mips/pci/pci-bcm63xx.c bcm_pcmcia_writel(val, PCMCIA_C1_REG); val 243 arch/mips/pci/pci-bcm63xx.c val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK; val 244 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG); val 246 arch/mips/pci/pci-bcm63xx.c val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK; val 247 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG); val 258 arch/mips/pci/pci-bcm63xx.c val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK; val 259 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val, MPI_L2PIOBASE_REG); val 261 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG); val 270 arch/mips/pci/pci-bcm63xx.c val = MPI_SP0_REMAP_ENABLE_MASK; val 272 arch/mips/pci/pci-bcm63xx.c val = 0; val 273 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val, MPI_SP0_REMAP_REG); val 296 arch/mips/pci/pci-bcm63xx.c val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS); val 297 arch/mips/pci/pci-bcm63xx.c val &= ~REG_TIMER_RETRY_MASK; val 298 arch/mips/pci/pci-bcm63xx.c bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS); val 301 arch/mips/pci/pci-bcm63xx.c val = bcm63xx_int_cfg_readl(PCI_COMMAND); val 302 arch/mips/pci/pci-bcm63xx.c val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); val 303 arch/mips/pci/pci-bcm63xx.c bcm63xx_int_cfg_writel(val, PCI_COMMAND); val 307 arch/mips/pci/pci-bcm63xx.c val = bcm_mpi_readl(MPI_PCIMODESEL_REG); val 308 arch/mips/pci/pci-bcm63xx.c val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK; val 309 arch/mips/pci/pci-bcm63xx.c val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK; val 310 arch/mips/pci/pci-bcm63xx.c val &= ~MPI_PCIMODESEL_PREFETCH_MASK; val 311 arch/mips/pci/pci-bcm63xx.c val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT); val 312 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val, MPI_PCIMODESEL_REG); val 315 arch/mips/pci/pci-bcm63xx.c val = bcm_mpi_readl(MPI_LOCINT_REG); val 316 arch/mips/pci/pci-bcm63xx.c val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT); val 317 arch/mips/pci/pci-bcm63xx.c bcm_mpi_writel(val, MPI_LOCINT_REG); val 12 arch/mips/pci/pci-lantiq.h unsigned int devfn, int where, int size, u32 *val); val 14 arch/mips/pci/pci-lantiq.h unsigned int devfn, int where, int size, u32 val); val 79 arch/mips/pci/pci-mt7620.c static inline void bridge_w32(u32 val, unsigned reg) val 81 arch/mips/pci/pci-mt7620.c iowrite32(val, bridge_base + reg); val 89 arch/mips/pci/pci-mt7620.c static inline void pcie_w32(u32 val, unsigned reg) val 91 arch/mips/pci/pci-mt7620.c iowrite32(val, pcie_base + reg); val 101 arch/mips/pci/pci-mt7620.c u32 val = pcie_r32(reg); val 103 arch/mips/pci/pci-mt7620.c val &= ~clr; val 104 arch/mips/pci/pci-mt7620.c val |= set; val 105 arch/mips/pci/pci-mt7620.c pcie_w32(val, reg); val 127 arch/mips/pci/pci-mt7620.c static void pcie_phy(unsigned long addr, unsigned long val) val 130 arch/mips/pci/pci-mt7620.c pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), val 137 arch/mips/pci/pci-mt7620.c int size, u32 *val) val 155 arch/mips/pci/pci-mt7620.c *val = (data >> ((where & 3) << 3)) & 0xff; val 158 arch/mips/pci/pci-mt7620.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 161 arch/mips/pci/pci-mt7620.c *val = data; val 169 arch/mips/pci/pci-mt7620.c int size, u32 val) val 188 arch/mips/pci/pci-mt7620.c (val << ((where & 3) << 3)); val 192 arch/mips/pci/pci-mt7620.c (val << ((where & 3) << 3)); val 195 arch/mips/pci/pci-mt7620.c data = val; val 258 arch/mips/pci/pci-mt7620.c u32 val = 0; val 271 arch/mips/pci/pci-mt7620.c pci_config_read(NULL, 0, 0x70c, 4, &val); val 272 arch/mips/pci/pci-mt7620.c val &= ~(0xff) << 8; val 273 arch/mips/pci/pci-mt7620.c val |= 0x50 << 8; val 274 arch/mips/pci/pci-mt7620.c pci_config_write(NULL, 0, 0x70c, 4, val); val 276 arch/mips/pci/pci-mt7620.c pci_config_read(NULL, 0, 0x70c, 4, &val); val 277 arch/mips/pci/pci-mt7620.c dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val); val 288 arch/mips/pci/pci-mt7620.c u32 val = 0; val 352 arch/mips/pci/pci-mt7620.c pci_config_read(NULL, 0, 4, 4, &val); val 353 arch/mips/pci/pci-mt7620.c pci_config_write(NULL, 0, 4, 4, val | 0x7); val 364 arch/mips/pci/pci-mt7620.c u32 val; val 371 arch/mips/pci/pci-mt7620.c pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val); val 258 arch/mips/pci/pci-octeon.c int reg, int size, u32 *val) val 275 arch/mips/pci/pci-octeon.c *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); val 278 arch/mips/pci/pci-octeon.c *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64)); val 281 arch/mips/pci/pci-octeon.c *val = cvmx_read64_uint8(pci_addr.u64); val 292 arch/mips/pci/pci-octeon.c int reg, int size, u32 val) val 309 arch/mips/pci/pci-octeon.c cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val)); val 312 arch/mips/pci/pci-octeon.c cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val)); val 315 arch/mips/pci/pci-octeon.c cvmx_write64_uint8(pci_addr.u64, val); val 51 arch/mips/pci/pci-rt2880.c static void rt2880_pci_reg_write(u32 val, u32 reg) val 53 arch/mips/pci/pci-rt2880.c writel(val, rt2880_pci_base + reg); val 64 arch/mips/pci/pci-rt2880.c int where, int size, u32 *val) val 80 arch/mips/pci/pci-rt2880.c *val = (data >> ((where & 3) << 3)) & 0xff; val 83 arch/mips/pci/pci-rt2880.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 86 arch/mips/pci/pci-rt2880.c *val = data; val 94 arch/mips/pci/pci-rt2880.c int where, int size, u32 val) val 110 arch/mips/pci/pci-rt2880.c (val << ((where & 3) << 3)); val 114 arch/mips/pci/pci-rt2880.c (val << ((where & 3) << 3)); val 117 arch/mips/pci/pci-rt2880.c data = val; val 168 arch/mips/pci/pci-rt2880.c static inline void rt2880_pci_write_u32(unsigned long reg, u32 val) val 177 arch/mips/pci/pci-rt2880.c rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); val 87 arch/mips/pci/pci-rt3883.c u32 val, unsigned reg) val 89 arch/mips/pci/pci-rt3883.c iowrite32(val, rpc->base + reg); val 117 arch/mips/pci/pci-rt3883.c unsigned func, unsigned reg, u32 val) val 125 arch/mips/pci/pci-rt3883.c rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); val 229 arch/mips/pci/pci-rt3883.c int where, int size, u32 *val) val 249 arch/mips/pci/pci-rt3883.c *val = (data >> ((where & 3) << 3)) & 0xff; val 252 arch/mips/pci/pci-rt3883.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 255 arch/mips/pci/pci-rt3883.c *val = data; val 263 arch/mips/pci/pci-rt3883.c int where, int size, u32 val) val 284 arch/mips/pci/pci-rt3883.c (val << ((where & 3) << 3)); val 288 arch/mips/pci/pci-rt3883.c (val << ((where & 3) << 3)); val 291 arch/mips/pci/pci-rt3883.c data = val; val 415 arch/mips/pci/pci-rt3883.c u32 val; val 527 arch/mips/pci/pci-rt3883.c val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); val 528 arch/mips/pci/pci-rt3883.c val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; val 529 arch/mips/pci/pci-rt3883.c rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); val 532 arch/mips/pci/pci-rt3883.c val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); val 533 arch/mips/pci/pci-rt3883.c val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; val 534 arch/mips/pci/pci-rt3883.c rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); val 117 arch/mips/pci/pci-sb1250.c int where, int size, u32 * val) val 132 arch/mips/pci/pci-sb1250.c *val = (data >> ((where & 3) << 3)) & 0xff; val 134 arch/mips/pci/pci-sb1250.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 136 arch/mips/pci/pci-sb1250.c *val = data; val 142 arch/mips/pci/pci-sb1250.c int where, int size, u32 val) val 159 arch/mips/pci/pci-sb1250.c (val << ((where & 3) << 3)); val 162 arch/mips/pci/pci-sb1250.c (val << ((where & 3) << 3)); val 164 arch/mips/pci/pci-sb1250.c data = val; val 57 arch/mips/pci/pci-virtio-guest.c unsigned int devfn, int reg, int size, u32 val) val 63 arch/mips/pci/pci-virtio-guest.c outb(val, PCI_CONFIG_DATA + (reg & 3)); val 66 arch/mips/pci/pci-virtio-guest.c outw(val, PCI_CONFIG_DATA + (reg & 2)); val 69 arch/mips/pci/pci-virtio-guest.c outl(val, PCI_CONFIG_DATA); val 77 arch/mips/pci/pci-virtio-guest.c int reg, int size, u32 *val) val 83 arch/mips/pci/pci-virtio-guest.c *val = inb(PCI_CONFIG_DATA + (reg & 3)); val 86 arch/mips/pci/pci-virtio-guest.c *val = inw(PCI_CONFIG_DATA + (reg & 2)); val 89 arch/mips/pci/pci-virtio-guest.c *val = inl(PCI_CONFIG_DATA); val 105 arch/mips/pci/pci-vr41xx.c uint32_t val; val 153 arch/mips/pci/pci-vr41xx.c val = IBA(master->bus_base_address) | val 157 arch/mips/pci/pci-vr41xx.c pciu_write(PCIMMAW1REG, val); val 159 arch/mips/pci/pci-vr41xx.c val = pciu_read(PCIMMAW1REG); val 160 arch/mips/pci/pci-vr41xx.c val &= ~WINEN; val 161 arch/mips/pci/pci-vr41xx.c pciu_write(PCIMMAW1REG, val); val 166 arch/mips/pci/pci-vr41xx.c val = IBA(master->bus_base_address) | val 170 arch/mips/pci/pci-vr41xx.c pciu_write(PCIMMAW2REG, val); val 172 arch/mips/pci/pci-vr41xx.c val = pciu_read(PCIMMAW2REG); val 173 arch/mips/pci/pci-vr41xx.c val &= ~WINEN; val 174 arch/mips/pci/pci-vr41xx.c pciu_write(PCIMMAW2REG, val); val 179 arch/mips/pci/pci-vr41xx.c val = TARGET_MSK(target->address_mask) | val 182 arch/mips/pci/pci-vr41xx.c pciu_write(PCITAW1REG, val); val 184 arch/mips/pci/pci-vr41xx.c val = pciu_read(PCITAW1REG); val 185 arch/mips/pci/pci-vr41xx.c val &= ~WINEN; val 186 arch/mips/pci/pci-vr41xx.c pciu_write(PCITAW1REG, val); val 191 arch/mips/pci/pci-vr41xx.c val = TARGET_MSK(target->address_mask) | val 194 arch/mips/pci/pci-vr41xx.c pciu_write(PCITAW2REG, val); val 196 arch/mips/pci/pci-vr41xx.c val = pciu_read(PCITAW2REG); val 197 arch/mips/pci/pci-vr41xx.c val &= ~WINEN; val 198 arch/mips/pci/pci-vr41xx.c pciu_write(PCITAW2REG, val); val 203 arch/mips/pci/pci-vr41xx.c val = IBA(master->bus_base_address) | val 207 arch/mips/pci/pci-vr41xx.c pciu_write(PCIMIOAWREG, val); val 209 arch/mips/pci/pci-vr41xx.c val = pciu_read(PCIMIOAWREG); val 210 arch/mips/pci/pci-vr41xx.c val &= ~WINEN; val 211 arch/mips/pci/pci-vr41xx.c pciu_write(PCIMIOAWREG, val); val 226 arch/mips/pci/pci-vr41xx.c val = MBADD(mailbox->base_address) | TYPE_32BITSPACE | val 228 arch/mips/pci/pci-vr41xx.c pciu_write(MAILBAREG, val); val 233 arch/mips/pci/pci-vr41xx.c val = PMBA(window->base_address) | TYPE_32BITSPACE | val 235 arch/mips/pci/pci-vr41xx.c pciu_write(PCIMBA1REG, val); val 240 arch/mips/pci/pci-vr41xx.c val = PMBA(window->base_address) | TYPE_32BITSPACE | val 242 arch/mips/pci/pci-vr41xx.c pciu_write(PCIMBA2REG, val); val 245 arch/mips/pci/pci-vr41xx.c val = pciu_read(RETVALREG); val 246 arch/mips/pci/pci-vr41xx.c val &= ~RTYVAL_MASK; val 247 arch/mips/pci/pci-vr41xx.c val |= RTYVAL(setup->retry_limit); val 248 arch/mips/pci/pci-vr41xx.c pciu_write(RETVALREG, val); val 250 arch/mips/pci/pci-vr41xx.c val = pciu_read(PCIAPCNTREG); val 251 arch/mips/pci/pci-vr41xx.c val &= ~(TKYGNT | PAPC); val 255 arch/mips/pci/pci-vr41xx.c val |= PAPC_ALTERNATE_0; val 258 arch/mips/pci/pci-vr41xx.c val |= PAPC_ALTERNATE_B; val 261 arch/mips/pci/pci-vr41xx.c val |= PAPC_FAIR; val 266 arch/mips/pci/pci-vr41xx.c val |= TKYGNT_ENABLE; val 268 arch/mips/pci/pci-vr41xx.c pciu_write(PCIAPCNTREG, val); val 73 arch/mips/pci/pci-vr41xx.h #define TRDYV(val) ((uint32_t)(val) & 0xffU) val 84 arch/mips/pci/pci-vr41xx.h #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U) val 108 arch/mips/pci/pci-vr41xx.h #define RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U) val 103 arch/mips/pci/pci-xlp.c int where, int size, u32 *val) val 115 arch/mips/pci/pci-xlp.c *val = (data >> ((where & 3) << 3)) & 0xff; val 117 arch/mips/pci/pci-xlp.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 119 arch/mips/pci/pci-xlp.c *val = data; val 126 arch/mips/pci/pci-xlp.c int where, int size, u32 val) val 139 arch/mips/pci/pci-xlp.c (val << ((where & 3) << 3)); val 142 arch/mips/pci/pci-xlp.c (val << ((where & 3) << 3)); val 144 arch/mips/pci/pci-xlp.c data = val; val 85 arch/mips/pci/pci-xlr.c int where, int size, u32 *val) val 97 arch/mips/pci/pci-xlr.c *val = (data >> ((where & 3) << 3)) & 0xff; val 99 arch/mips/pci/pci-xlr.c *val = (data >> ((where & 3) << 3)) & 0xffff; val 101 arch/mips/pci/pci-xlr.c *val = data; val 108 arch/mips/pci/pci-xlr.c int where, int size, u32 val) val 121 arch/mips/pci/pci-xlr.c (val << ((where & 3) << 3)); val 124 arch/mips/pci/pci-xlr.c (val << ((where & 3) << 3)); val 126 arch/mips/pci/pci-xlr.c data = val; val 226 arch/mips/pci/pci-xlr.c u16 val; val 240 arch/mips/pci/pci-xlr.c pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val); val 241 arch/mips/pci/pci-xlr.c if ((val & PCI_MSI_FLAGS_ENABLE) == 0) { val 242 arch/mips/pci/pci-xlr.c val |= PCI_MSI_FLAGS_ENABLE; val 243 arch/mips/pci/pci-xlr.c pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val); val 200 arch/mips/pci/pcie-octeon.c uint32_t val) val 206 arch/mips/pci/pcie-octeon.c pescx_cfg_wr.s.data = val; val 212 arch/mips/pci/pcie-octeon.c pemx_cfg_wr.s.data = val; val 331 arch/mips/pci/pcie-octeon.c int reg, uint8_t val) val 336 arch/mips/pci/pcie-octeon.c cvmx_write64_uint8(address, val); val 350 arch/mips/pci/pcie-octeon.c int reg, uint16_t val) val 355 arch/mips/pci/pcie-octeon.c cvmx_write64_uint16(address, cpu_to_le16(val)); val 369 arch/mips/pci/pcie-octeon.c int reg, uint32_t val) val 374 arch/mips/pci/pcie-octeon.c cvmx_write64_uint32(address, cpu_to_le32(val)); val 1539 arch/mips/pci/pcie-octeon.c u32 *val) val 1672 arch/mips/pci/pcie-octeon.c *val = cvmx_pcie_config_read32(pcie_port, bus_number, val 1676 arch/mips/pci/pcie-octeon.c *val = cvmx_pcie_config_read16(pcie_port, bus_number, val 1680 arch/mips/pci/pcie-octeon.c *val = cvmx_pcie_config_read8(pcie_port, bus_number, val 1702 arch/mips/pci/pcie-octeon.c pr_debug("val=%08x : tries=%02d\n", *val, retry_cnt); val 1710 arch/mips/pci/pcie-octeon.c int reg, int size, u32 *val) val 1712 arch/mips/pci/pcie-octeon.c return octeon_pcie_read_config(0, bus, devfn, reg, size, val); val 1716 arch/mips/pci/pcie-octeon.c int reg, int size, u32 *val) val 1718 arch/mips/pci/pcie-octeon.c return octeon_pcie_read_config(1, bus, devfn, reg, size, val); val 1722 arch/mips/pci/pcie-octeon.c int reg, int size, u32 *val) val 1732 arch/mips/pci/pcie-octeon.c int size, u32 val) val 1743 arch/mips/pci/pcie-octeon.c reg, size, val); val 1749 arch/mips/pci/pcie-octeon.c devfn & 0x7, reg, val); val 1753 arch/mips/pci/pcie-octeon.c devfn & 0x7, reg, val); val 1757 arch/mips/pci/pcie-octeon.c devfn & 0x7, reg, val); val 1766 arch/mips/pci/pcie-octeon.c int reg, int size, u32 val) val 1768 arch/mips/pci/pcie-octeon.c return octeon_pcie_write_config(0, bus, devfn, reg, size, val); val 1772 arch/mips/pci/pcie-octeon.c int reg, int size, u32 val) val 1774 arch/mips/pci/pcie-octeon.c return octeon_pcie_write_config(1, bus, devfn, reg, size, val); val 1778 arch/mips/pci/pcie-octeon.c int reg, int size, u32 val) val 126 arch/mips/pmcs-msp71xx/msp_usb.c unsigned int val; val 139 arch/mips/pmcs-msp71xx/msp_usb.c val = 1; val 146 arch/mips/pmcs-msp71xx/msp_usb.c val = 0; val 149 arch/mips/pmcs-msp71xx/msp_usb.c if (val) { val 35 arch/mips/ralink/early_printk.c static inline void uart_w32(u32 val, unsigned reg) val 37 arch/mips/ralink/early_printk.c __raw_writel(val, uart_membase + reg); val 59 arch/mips/ralink/irq.c static inline void rt_intc_w32(u32 val, unsigned reg) val 61 arch/mips/ralink/irq.c __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]); val 578 arch/mips/ralink/mt7620.c u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); val 580 arch/mips/ralink/mt7620.c val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); val 581 arch/mips/ralink/mt7620.c val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; val 583 arch/mips/ralink/mt7620.c rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); val 28 arch/mips/ralink/reset.c u32 val; val 33 arch/mips/ralink/reset.c val = rt_sysc_r32(SYSC_REG_RESET_CTRL); val 34 arch/mips/ralink/reset.c val |= BIT(id); val 35 arch/mips/ralink/reset.c rt_sysc_w32(val, SYSC_REG_RESET_CTRL); val 43 arch/mips/ralink/reset.c u32 val; val 48 arch/mips/ralink/reset.c val = rt_sysc_r32(SYSC_REG_RESET_CTRL); val 49 arch/mips/ralink/reset.c val &= ~BIT(id); val 50 arch/mips/ralink/reset.c rt_sysc_w32(val, SYSC_REG_RESET_CTRL); val 188 arch/mips/ralink/rt305x.c u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); val 190 arch/mips/ralink/rt305x.c if (!(val & RT3352_CLKCFG0_XTAL_SEL)) val 37 arch/mips/ralink/timer.c static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val) val 39 arch/mips/ralink/timer.c __raw_writel(val, rt->membase + reg); val 64 arch/mips/rb532/gpio.c u32 val; val 68 arch/mips/rb532/gpio.c val = readl(ioaddr); val 69 arch/mips/rb532/gpio.c val &= ~(!bitval << offset); /* unset bit if bitval == 0 */ val 70 arch/mips/rb532/gpio.c val |= (!!bitval << offset); /* set bit if bitval == 1 */ val 71 arch/mips/rb532/gpio.c writel(val, ioaddr); val 79 arch/mips/rb532/irq.c #define WRITE_MASK(base, val) (*(base + 2) = (val)) val 44 arch/mips/rb532/setup.c u32 val; val 59 arch/mips/rb532/setup.c val = __raw_readl(&pci_reg->pcic); val 60 arch/mips/rb532/setup.c val &= 0xFFFFFF7; val 61 arch/mips/rb532/setup.c __raw_writel(val, (void *)&pci_reg->pcic); val 98 arch/mips/sibyte/common/sb_tbprof.c #define zclk_timer_init(val) \ val 107 arch/mips/sibyte/common/sb_tbprof.c : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \ val 113 arch/mips/sibyte/common/sb_tbprof.c #define zclk_get(val) \ val 119 arch/mips/sibyte/common/sb_tbprof.c : /* outputs */ "=r"(val) \ val 18 arch/mips/txx9/generic/7segled.c static void (*tx_7segled_putc)(unsigned int pos, unsigned char val); val 21 arch/mips/txx9/generic/7segled.c void (*putc)(unsigned int pos, unsigned char val)) val 37 arch/mips/txx9/generic/mem_tx4927.c u64 val; val 48 arch/mips/txx9/generic/mem_tx4927.c val = __raw_readq(addr); val 51 arch/mips/txx9/generic/mem_tx4927.c sdccr_ce = ((val & (1 << 10)) >> 10); val 52 arch/mips/txx9/generic/mem_tx4927.c sdccr_bs = ((val & (1 << 8)) >> 8); val 53 arch/mips/txx9/generic/mem_tx4927.c sdccr_rs = ((val & (3 << 5)) >> 5); val 54 arch/mips/txx9/generic/mem_tx4927.c sdccr_cs = ((val & (7 << 2)) >> 2); val 55 arch/mips/txx9/generic/mem_tx4927.c sdccr_mw = ((val & (1 << 0)) >> 0); val 412 arch/mips/txx9/generic/pci.c char *val = str + 4; val 414 arch/mips/txx9/generic/pci.c if (strcmp(val, "33") == 0) val 416 arch/mips/txx9/generic/pci.c else if (strcmp(val, "66") == 0) val 264 arch/mips/txx9/generic/setup.c unsigned int val; val 265 arch/mips/txx9/generic/setup.c if (kstrtouint(str + 10, 10, &val) == 0) val 266 arch/mips/txx9/generic/setup.c txx9_master_clock = val; val 88 arch/mips/txx9/generic/smsc_fdc37m81x.c u8 val = 0; val 91 arch/mips/txx9/generic/smsc_fdc37m81x.c val = smsc_fdc37m81x_rd(reg); val 93 arch/mips/txx9/generic/smsc_fdc37m81x.c return val; val 96 arch/mips/txx9/generic/smsc_fdc37m81x.c void smsc_fdc37m81x_config_set(u8 reg, u8 val) val 99 arch/mips/txx9/generic/smsc_fdc37m81x.c smsc_dc37m81x_wr(reg, val); val 247 arch/mips/txx9/rbtx4938/setup.c u8 val; val 250 arch/mips/txx9/rbtx4938/setup.c val = readb(rbtx4938_spics_addr); val 252 arch/mips/txx9/rbtx4938/setup.c val |= 1 << offset; val 254 arch/mips/txx9/rbtx4938/setup.c val &= ~(1 << offset); val 255 arch/mips/txx9/rbtx4938/setup.c writeb(val, rbtx4938_spics_addr); val 262 arch/mips/txx9/rbtx4939/setup.c static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val) val 268 arch/mips/txx9/rbtx4939/setup.c led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f); val 269 arch/mips/txx9/rbtx4939/setup.c val = led_val[pos]; val 272 arch/mips/txx9/rbtx4939/setup.c writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4)); val 275 arch/mips/txx9/rbtx4939/setup.c static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val) val 278 arch/mips/txx9/rbtx4939/setup.c val = (val & 0x88) | val 279 arch/mips/txx9/rbtx4939/setup.c ((val & 0x40) >> 6) | val 280 arch/mips/txx9/rbtx4939/setup.c ((val & 0x20) >> 4) | val 281 arch/mips/txx9/rbtx4939/setup.c ((val & 0x10) >> 2) | val 282 arch/mips/txx9/rbtx4939/setup.c ((val & 0x04) << 2) | val 283 arch/mips/txx9/rbtx4939/setup.c ((val & 0x02) << 4) | val 284 arch/mips/txx9/rbtx4939/setup.c ((val & 0x01) << 6); val 285 arch/mips/txx9/rbtx4939/setup.c __rbtx4939_7segled_putc(pos, val); val 78 arch/mips/vdso/genvdso.c static uint##bits##_t swap_uint##bits(uint##bits##_t val) \ val 80 arch/mips/vdso/genvdso.c return need_swap ? bswap_##bits(val) : val; \ val 41 arch/nds32/include/asm/futex.h u32 val, tmp, flags; val 55 arch/nds32/include/asm/futex.h :"+&r"(ret), "=&r"(val), "=&r"(tmp), "=&r"(flags) val 60 arch/nds32/include/asm/futex.h *uval = val; val 11 arch/nds32/include/asm/io.h static inline void __raw_writeb(u8 val, volatile void __iomem *addr) val 13 arch/nds32/include/asm/io.h asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr)); val 17 arch/nds32/include/asm/io.h static inline void __raw_writew(u16 val, volatile void __iomem *addr) val 19 arch/nds32/include/asm/io.h asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr)); val 23 arch/nds32/include/asm/io.h static inline void __raw_writel(u32 val, volatile void __iomem *addr) val 25 arch/nds32/include/asm/io.h asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr)); val 31 arch/nds32/include/asm/io.h u8 val; val 33 arch/nds32/include/asm/io.h asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr)); val 34 arch/nds32/include/asm/io.h return val; val 40 arch/nds32/include/asm/io.h u16 val; val 42 arch/nds32/include/asm/io.h asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr)); val 43 arch/nds32/include/asm/io.h return val; val 49 arch/nds32/include/asm/io.h u32 val; val 51 arch/nds32/include/asm/io.h asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr)); val 52 arch/nds32/include/asm/io.h return val; val 123 arch/nds32/include/asm/l2_cache.h static inline void SET_L2CC_CTRL_CPU(unsigned long cpu, unsigned long val) val 126 arch/nds32/include/asm/l2_cache.h L2C_W_REG(L2CC_CTRL_OFF, val); val 128 arch/nds32/include/asm/l2_cache.h L2C_W_REG(L2CC_CTRL_OFF + (cpu << 8), val); val 36 arch/nds32/include/asm/pgtable.h extern void __pte_error(const char *file, int line, unsigned long val); val 37 arch/nds32/include/asm/pgtable.h extern void __pmd_error(const char *file, int line, unsigned long val); val 38 arch/nds32/include/asm/pgtable.h extern void __pgd_error(const char *file, int line, unsigned long val); val 385 arch/nds32/include/asm/pgtable.h #define __swp_type(x) (((x).val >> 2) & 0x7f) val 386 arch/nds32/include/asm/pgtable.h #define __swp_offset(x) ((x).val >> 9) val 389 arch/nds32/include/asm/pgtable.h #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) val 75 arch/nds32/include/asm/pmu.h void (*write_counter)(struct perf_event *event, u32 val); val 108 arch/nds32/include/asm/syscall.h int error, long val) val 110 arch/nds32/include/asm/syscall.h regs->uregs[0] = (long)error ? error : val; val 29 arch/nds32/kernel/module.c void do_reloc16(unsigned int val, unsigned int *loc, unsigned int val_mask, val 45 arch/nds32/kernel/module.c tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask); val 47 arch/nds32/kernel/module.c tmp = tmp2 | ((val & val_mask) >> val_shift); val 58 arch/nds32/kernel/module.c void do_reloc32(unsigned int val, unsigned int *loc, unsigned int val_mask, val 75 arch/nds32/kernel/module.c tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask); val 77 arch/nds32/kernel/module.c tmp = tmp2 | ((val & val_mask) >> val_shift); val 140 arch/nds32/kernel/perf_event_cpu.c u32 val = __nds32__mfsr(NDS32_SR_PFM_CTL); val 141 arch/nds32/kernel/perf_event_cpu.c u32 old_val = val; val 146 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr(val | ov_flag, NDS32_SR_PFM_CTL); val 294 arch/nds32/kernel/perf_event_cpu.c unsigned int val = __nds32__mfsr(NDS32_SR_PFM_CTL); val 298 arch/nds32/kernel/perf_event_cpu.c val &= ~mask; val 299 arch/nds32/kernel/perf_event_cpu.c val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); val 300 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); val 344 arch/nds32/kernel/perf_event_cpu.c u32 val; val 365 arch/nds32/kernel/perf_event_cpu.c val = ori_val | (evnum << offset); val 366 arch/nds32/kernel/perf_event_cpu.c val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); val 367 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); val 372 arch/nds32/kernel/perf_event_cpu.c unsigned int val = __nds32__mfsr(NDS32_SR_PFM_CTL); val 376 arch/nds32/kernel/perf_event_cpu.c val |= mask; val 377 arch/nds32/kernel/perf_event_cpu.c val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); val 378 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); val 384 arch/nds32/kernel/perf_event_cpu.c unsigned int val = __nds32__mfsr(NDS32_SR_PFM_CTL); val 388 arch/nds32/kernel/perf_event_cpu.c val |= mask; val 389 arch/nds32/kernel/perf_event_cpu.c val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); val 390 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); val 396 arch/nds32/kernel/perf_event_cpu.c unsigned int val = __nds32__mfsr(NDS32_SR_PFM_CTL); val 400 arch/nds32/kernel/perf_event_cpu.c val &= ~mask; val 401 arch/nds32/kernel/perf_event_cpu.c val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); val 402 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); val 598 arch/nds32/kernel/perf_event_cpu.c unsigned int val; val 604 arch/nds32/kernel/perf_event_cpu.c val = __nds32__mfsr(NDS32_SR_PFM_CTL); val 605 arch/nds32/kernel/perf_event_cpu.c val |= (PFM_CTL_EN[0] | PFM_CTL_EN[1] | PFM_CTL_EN[2]); val 606 arch/nds32/kernel/perf_event_cpu.c val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); val 607 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); val 615 arch/nds32/kernel/perf_event_cpu.c unsigned int val; val 621 arch/nds32/kernel/perf_event_cpu.c val = __nds32__mfsr(NDS32_SR_PFM_CTL); val 622 arch/nds32/kernel/perf_event_cpu.c val &= ~(PFM_CTL_EN[0] | PFM_CTL_EN[1] | PFM_CTL_EN[2]); val 623 arch/nds32/kernel/perf_event_cpu.c val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); val 624 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); val 631 arch/nds32/kernel/perf_event_cpu.c u32 val = 0; val 633 arch/nds32/kernel/perf_event_cpu.c val |= (PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); val 634 arch/nds32/kernel/perf_event_cpu.c __nds32__mtsr(val, NDS32_SR_PFM_CTL); val 50 arch/nds32/kernel/traps.c unsigned long val; val 51 arch/nds32/kernel/traps.c if (__get_user(val, (unsigned long *)p) == 0) val 52 arch/nds32/kernel/traps.c sprintf(str + i * 9, " %08lx", val); val 83 arch/nds32/kernel/traps.c unsigned int val, bad; val 85 arch/nds32/kernel/traps.c bad = __get_user(val, &((u32 *) addr)[i]); val 88 arch/nds32/kernel/traps.c p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); val 213 arch/nds32/kernel/traps.c void __pte_error(const char *file, int line, unsigned long val) val 215 arch/nds32/kernel/traps.c pr_emerg("%s:%d: bad pte %08lx.\n", file, line, val); val 218 arch/nds32/kernel/traps.c void __pmd_error(const char *file, int line, unsigned long val) val 220 arch/nds32/kernel/traps.c pr_emerg("%s:%d: bad pmd %08lx.\n", file, line, val); val 223 arch/nds32/kernel/traps.c void __pgd_error(const char *file, int line, unsigned long val) val 225 arch/nds32/kernel/traps.c pr_emerg("%s:%d: bad pgd %08lx.\n", file, line, val); val 34 arch/nds32/mm/alignment.c #define __get8_data(val,addr,err) \ val 47 arch/nds32/mm/alignment.c : "=r" (err), "=&r" (val), "=r" (addr) \ val 84 arch/nds32/mm/alignment.c #define set16_data(addr, val) \ val 87 arch/nds32/mm/alignment.c val = le32_to_cpu(val); \ val 103 arch/nds32/mm/alignment.c : "=r" (err), "+r" (ptr), "+r" (val) \ val 110 arch/nds32/mm/alignment.c #define set32_data(addr, val) \ val 113 arch/nds32/mm/alignment.c val = le32_to_cpu(val); \ val 135 arch/nds32/mm/alignment.c : "=r" (err), "+r" (ptr), "+r" (val) \ val 141 arch/nds32/mm/alignment.c #define set_data(addr, val, len) \ val 143 arch/nds32/mm/alignment.c set16_data(addr, val); \ val 145 arch/nds32/mm/alignment.c set32_data(addr, val); val 173 arch/nds32/mm/alignment.c static inline unsigned long sign_extend(unsigned long val, int len) val 179 arch/nds32/mm/alignment.c val = cpu_to_le32(val); val 181 arch/nds32/mm/alignment.c s = (void *)&val; val 283 arch/nios2/include/asm/pgtable.h #define __swp_type(swp) (((swp).val >> 26) & 0x3) val 284 arch/nios2/include/asm/pgtable.h #define __swp_offset(swp) ((swp).val & 0xfffff) val 287 arch/nios2/include/asm/pgtable.h #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) val 38 arch/nios2/include/asm/syscall.h struct pt_regs *regs, int error, long val) val 45 arch/nios2/include/asm/syscall.h regs->r2 = val; val 90 arch/nios2/include/asm/uaccess.h #define __get_user_asm(val, insn, addr, err) \ val 100 arch/nios2/include/asm/uaccess.h : "=&r" (err), "=r" (val) \ val 104 arch/nios2/include/asm/uaccess.h #define __get_user_unknown(val, size, ptr, err) do { \ val 106 arch/nios2/include/asm/uaccess.h if (__copy_from_user(&(val), ptr, size)) { \ val 111 arch/nios2/include/asm/uaccess.h #define __get_user_common(val, size, ptr, err) \ val 115 arch/nios2/include/asm/uaccess.h __get_user_asm(val, "ldbu", ptr, err); \ val 118 arch/nios2/include/asm/uaccess.h __get_user_asm(val, "ldhu", ptr, err); \ val 121 arch/nios2/include/asm/uaccess.h __get_user_asm(val, "ldw", ptr, err); \ val 124 arch/nios2/include/asm/uaccess.h __get_user_unknown(val, size, ptr, err); \ val 151 arch/nios2/include/asm/uaccess.h #define __put_user_asm(val, insn, ptr, err) \ val 162 arch/nios2/include/asm/uaccess.h : "r" (val), "r" (ptr), "i" (-EFAULT)); \ val 24 arch/nios2/kernel/cpuinfo.c u32 val = 0; val 26 arch/nios2/kernel/cpuinfo.c of_property_read_u32(cpu, n, &val); val 28 arch/nios2/kernel/cpuinfo.c return val; val 57 arch/nios2/kernel/misaligned.c static inline void put_reg_val(struct pt_regs *fp, int reg, u32 val) val 60 arch/nios2/kernel/misaligned.c *(u32 *)p = val; val 68 arch/nios2/kernel/misaligned.c u32 isn, addr, val; val 100 arch/nios2/kernel/misaligned.c val = (d1 << 8) | d0; val 101 arch/nios2/kernel/misaligned.c put_reg_val(fp, b, val); val 104 arch/nios2/kernel/misaligned.c val = get_reg_val(fp, b); val 105 arch/nios2/kernel/misaligned.c d1 = val >> 8; val 106 arch/nios2/kernel/misaligned.c d0 = val >> 0; val 118 arch/nios2/kernel/misaligned.c val = (short)((d1 << 8) | d0); val 119 arch/nios2/kernel/misaligned.c put_reg_val(fp, b, val); val 122 arch/nios2/kernel/misaligned.c val = get_reg_val(fp, b); val 123 arch/nios2/kernel/misaligned.c d3 = val >> 24; val 124 arch/nios2/kernel/misaligned.c d2 = val >> 16; val 125 arch/nios2/kernel/misaligned.c d1 = val >> 8; val 126 arch/nios2/kernel/misaligned.c d0 = val >> 0; val 144 arch/nios2/kernel/misaligned.c val = (d3 << 24) | (d2 << 16) | (d1 << 8) | d0; val 145 arch/nios2/kernel/misaligned.c put_reg_val(fp, b, val); val 68 arch/nios2/kernel/time.c static void timer_writew(struct nios2_timer *timer, u16 val, u32 offs) val 70 arch/nios2/kernel/time.c writew(val, timer->base + offs); val 45 arch/openrisc/include/asm/cmpxchg.h unsigned long val) val 52 arch/openrisc/include/asm/cmpxchg.h : "=&r"(val) val 53 arch/openrisc/include/asm/cmpxchg.h : "r"(ptr), "r"(val) val 56 arch/openrisc/include/asm/cmpxchg.h return val; val 435 arch/openrisc/include/asm/pgtable.h #define __swp_type(x) (((x).val >> 5) & 0x7f) val 436 arch/openrisc/include/asm/pgtable.h #define __swp_offset(x) ((x).val >> 12) val 440 arch/openrisc/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 48 arch/openrisc/include/asm/syscall.h int error, long val) val 50 arch/openrisc/include/asm/syscall.h regs->gpr[11] = (long) error ?: val; val 267 arch/openrisc/kernel/setup.c const int *val; val 270 arch/openrisc/kernel/setup.c val = of_get_property(cpu, "clock-frequency", NULL); val 271 arch/openrisc/kernel/setup.c if (!val) val 273 arch/openrisc/kernel/setup.c loops_per_jiffy = *val / HZ; val 89 arch/parisc/include/asm/futex.h u32 val; val 108 arch/parisc/include/asm/futex.h if (unlikely(get_user(val, uaddr) != 0)) { val 113 arch/parisc/include/asm/futex.h if (val == oldval && unlikely(put_user(newval, uaddr) != 0)) { val 118 arch/parisc/include/asm/futex.h *uval = val; val 87 arch/parisc/include/asm/io.h static inline void gsc_writeb(unsigned char val, unsigned long addr) val 94 arch/parisc/include/asm/io.h : "=&r" (flags) : "r" (val), "r" (addr), "i" (PSW_SM_D) ); val 97 arch/parisc/include/asm/io.h static inline void gsc_writew(unsigned short val, unsigned long addr) val 104 arch/parisc/include/asm/io.h : "=&r" (flags) : "r" (val), "r" (addr), "i" (PSW_SM_D) ); val 107 arch/parisc/include/asm/io.h static inline void gsc_writel(unsigned int val, unsigned long addr) val 111 arch/parisc/include/asm/io.h : : "r" (val), "r" (addr) ); val 114 arch/parisc/include/asm/io.h static inline void gsc_writeq(unsigned long long val, unsigned long addr) val 119 arch/parisc/include/asm/io.h : : "r" (val), "r" (addr) ); val 122 arch/parisc/include/asm/io.h gsc_writel(val >> 32, addr); val 123 arch/parisc/include/asm/io.h gsc_writel(val, addr+4); val 232 arch/parisc/include/asm/io.h void memset_io(volatile void __iomem *addr, unsigned char val, int count); val 318 arch/parisc/include/asm/io.h extern void iowrite64(u64 val, void __iomem *addr); val 319 arch/parisc/include/asm/io.h extern void iowrite64be(u64 val, void __iomem *addr); val 376 arch/parisc/include/asm/pdcpat.h extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val); val 377 arch/parisc/include/asm/pdcpat.h extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val); val 480 arch/parisc/include/asm/pgtable.h #define __swp_type(x) ((x).val & 0x1f) val 481 arch/parisc/include/asm/pgtable.h #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \ val 482 arch/parisc/include/asm/pgtable.h (((x).val >> 8) & ~0x7) ) val 487 arch/parisc/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 29 arch/parisc/include/asm/ptrace.h unsigned long val) val 31 arch/parisc/include/asm/ptrace.h regs->iaoq[0] = val; val 32 arch/parisc/include/asm/ptrace.h regs->iaoq[1] = val + 4; val 46 arch/parisc/include/asm/special_insns.h static inline void set_eiem(unsigned long val) val 48 arch/parisc/include/asm/special_insns.h mtctl(val, 15); val 60 arch/parisc/include/asm/special_insns.h #define mtsp(val, cr) \ val 61 arch/parisc/include/asm/special_insns.h { if (__builtin_constant_p(val) && ((val) == 0)) \ val 66 arch/parisc/include/asm/special_insns.h : "r" (val), "i" (cr) : "memory"); } val 47 arch/parisc/include/asm/syscall.h int error, long val) val 49 arch/parisc/include/asm/syscall.h regs->gr[28] = error ? error : val; val 36 arch/parisc/include/asm/uaccess.h #define LDD_USER(val, ptr) __get_user_asm64(val, ptr) val 39 arch/parisc/include/asm/uaccess.h #define LDD_USER(val, ptr) __get_user_asm(val, "ldd", ptr) val 83 arch/parisc/include/asm/uaccess.h #define __get_user_internal(val, ptr) \ val 88 arch/parisc/include/asm/uaccess.h case 1: __get_user_asm(val, "ldb", ptr); break; \ val 89 arch/parisc/include/asm/uaccess.h case 2: __get_user_asm(val, "ldh", ptr); break; \ val 90 arch/parisc/include/asm/uaccess.h case 4: __get_user_asm(val, "ldw", ptr); break; \ val 91 arch/parisc/include/asm/uaccess.h case 8: LDD_USER(val, ptr); break; \ val 98 arch/parisc/include/asm/uaccess.h #define __get_user(val, ptr) \ val 101 arch/parisc/include/asm/uaccess.h __get_user_internal(val, ptr); \ val 104 arch/parisc/include/asm/uaccess.h #define __get_user_asm(val, ldx, ptr) \ val 114 arch/parisc/include/asm/uaccess.h (val) = (__force __typeof__(*(ptr))) __gu_val; \ val 119 arch/parisc/include/asm/uaccess.h #define __get_user_asm64(val, ptr) \ val 135 arch/parisc/include/asm/uaccess.h (val) = __gu_tmp.t; \ val 985 arch/parisc/kernel/firmware.c void pdc_pci_config_write(void *hpa, unsigned long cfg_addr, unsigned int val) val 994 arch/parisc/kernel/firmware.c cfg_addr&~3UL, 4UL, (unsigned long) val); val 1537 arch/parisc/kernel/firmware.c int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val) val 1544 arch/parisc/kernel/firmware.c pci_addr, pci_size, val); val 56 arch/parisc/kernel/module.c #define RELOC_REACHABLE(val, bits) \ val 57 arch/parisc/kernel/module.c (( ( !((val) & (1<<((bits)-1))) && ((val)>>(bits)) != 0 ) || \ val 58 arch/parisc/kernel/module.c ( ((val) & (1<<((bits)-1))) && ((val)>>(bits)) != (((__typeof__(val))(~0))>>((bits)+2)))) ? \ val 61 arch/parisc/kernel/module.c #define CHECK_RELOC(val, bits) \ val 62 arch/parisc/kernel/module.c if (!RELOC_REACHABLE(val, bits)) { \ val 64 arch/parisc/kernel/module.c me->name, strtab + sym->st_name, (unsigned long)val, bits); \ val 528 arch/parisc/kernel/module.c Elf32_Addr val; val 555 arch/parisc/kernel/module.c val = sym->st_value; val 562 arch/parisc/kernel/module.c (uint32_t)loc, val, addend, val 580 arch/parisc/kernel/module.c *loc = fsel(val, addend); val 584 arch/parisc/kernel/module.c *loc = fsel(val, addend); val 588 arch/parisc/kernel/module.c val = lrsel(val, addend); val 589 arch/parisc/kernel/module.c *loc = mask(*loc, 21) | reassemble_21(val); val 593 arch/parisc/kernel/module.c val = rrsel(val, addend); val 594 arch/parisc/kernel/module.c *loc = mask(*loc, 14) | reassemble_14(val); val 601 arch/parisc/kernel/module.c *loc = fsel(val, addend); val 605 arch/parisc/kernel/module.c *loc = fsel(val, addend); val 609 arch/parisc/kernel/module.c val = lrsel(val - dp, addend); val 610 arch/parisc/kernel/module.c *loc = mask(*loc, 21) | reassemble_21(val); val 614 arch/parisc/kernel/module.c val = rrsel(val - dp, addend); val 615 arch/parisc/kernel/module.c *loc = mask(*loc, 14) | reassemble_14(val); val 620 arch/parisc/kernel/module.c val += addend; val 621 arch/parisc/kernel/module.c val = (val - dot - 8)/4; val 622 arch/parisc/kernel/module.c if (!RELOC_REACHABLE(val, 17)) { val 625 arch/parisc/kernel/module.c val = get_stub(me, sym->st_value, addend, val 627 arch/parisc/kernel/module.c val = (val - dot - 8)/4; val 628 arch/parisc/kernel/module.c CHECK_RELOC(val, 17); val 630 arch/parisc/kernel/module.c *loc = (*loc & ~0x1f1ffd) | reassemble_17(val); val 635 arch/parisc/kernel/module.c val += addend; val 636 arch/parisc/kernel/module.c val = (val - dot - 8)/4; val 637 arch/parisc/kernel/module.c if (!RELOC_REACHABLE(val, 22)) { val 640 arch/parisc/kernel/module.c val = get_stub(me, sym->st_value, addend, val 642 arch/parisc/kernel/module.c val = (val - dot - 8)/4; val 643 arch/parisc/kernel/module.c CHECK_RELOC(val, 22); val 645 arch/parisc/kernel/module.c *loc = (*loc & ~0x3ff1ffd) | reassemble_22(val); val 649 arch/parisc/kernel/module.c *loc = val - dot - 8 + addend; val 674 arch/parisc/kernel/module.c Elf64_Addr val; val 700 arch/parisc/kernel/module.c val = sym->st_value; val 707 arch/parisc/kernel/module.c loc, val, addend, val 721 arch/parisc/kernel/module.c val = get_got(me, val, addend); val 724 arch/parisc/kernel/module.c loc, val); val 725 arch/parisc/kernel/module.c val = lrsel(val, 0); val 726 arch/parisc/kernel/module.c *loc = mask(*loc, 21) | reassemble_21(val); val 731 arch/parisc/kernel/module.c val = get_got(me, val, addend); val 732 arch/parisc/kernel/module.c val = rrsel(val, 0); val 735 arch/parisc/kernel/module.c loc, val); val 736 arch/parisc/kernel/module.c *loc = mask(*loc, 14) | reassemble_14(val); val 742 arch/parisc/kernel/module.c loc, val); val 743 arch/parisc/kernel/module.c val += addend; val 745 arch/parisc/kernel/module.c if (in_local(me, (void *)val)) { val 750 arch/parisc/kernel/module.c val = (val - dot - 8)/4; val 751 arch/parisc/kernel/module.c if (!RELOC_REACHABLE(val, 22)) { val 754 arch/parisc/kernel/module.c val = get_stub(me, sym->st_value, val 759 arch/parisc/kernel/module.c val = sym->st_value; val 760 arch/parisc/kernel/module.c val += addend; val 763 arch/parisc/kernel/module.c val = sym->st_value; val 766 arch/parisc/kernel/module.c val = get_stub(me, val, addend, ELF_STUB_MILLI, val 769 arch/parisc/kernel/module.c val = get_stub(me, val, addend, ELF_STUB_GOT, val 774 arch/parisc/kernel/module.c addend, val); val 775 arch/parisc/kernel/module.c val = (val - dot - 8)/4; val 776 arch/parisc/kernel/module.c CHECK_RELOC(val, 22); val 777 arch/parisc/kernel/module.c *loc = (*loc & ~0x3ff1ffd) | reassemble_22(val); val 781 arch/parisc/kernel/module.c *loc = val - dot - 8 + addend; val 785 arch/parisc/kernel/module.c *loc64 = val - dot - 8 + addend; val 789 arch/parisc/kernel/module.c *loc64 = val + addend; val 796 arch/parisc/kernel/module.c *loc = fsel(val, addend); val 800 arch/parisc/kernel/module.c *loc = fsel(val, addend); val 804 arch/parisc/kernel/module.c if(in_local(me, (void *)(val + addend))) { val 805 arch/parisc/kernel/module.c *loc64 = get_fdesc(me, val+addend); val 815 arch/parisc/kernel/module.c loc, val); val 816 arch/parisc/kernel/module.c *loc64 = val + addend; val 488 arch/parisc/kernel/ptrace.c static void set_reg(struct pt_regs *regs, int num, unsigned long val) val 498 arch/parisc/kernel/ptrace.c val &= USER_PSW_BITS; val 500 arch/parisc/kernel/ptrace.c regs->gr[0] |= val; val 503 arch/parisc/kernel/ptrace.c regs->gr[num - RI(gr[0])] = val; val 508 arch/parisc/kernel/ptrace.c regs->iaoq[num - RI(iaoq[0])] = val | 3; val 510 arch/parisc/kernel/ptrace.c case RI(sar): regs->sar = val; val 31 arch/parisc/kernel/sys_parisc.c #define SET_LAST_MMAP(filp, val) \ val 124 arch/parisc/kernel/unaligned.c unsigned long val = 0; val 143 arch/parisc/kernel/unaligned.c : "=r" (val), "=r" (ret) val 144 arch/parisc/kernel/unaligned.c : "0" (val), "r" (saddr), "r" (regs->isr) val 147 arch/parisc/kernel/unaligned.c DPRINTF("val = 0x" RFMT "\n", val); val 150 arch/parisc/kernel/unaligned.c regs->gr[toreg] = val; val 158 arch/parisc/kernel/unaligned.c unsigned long val = 0; val 181 arch/parisc/kernel/unaligned.c : "=r" (val), "=r" (ret) val 182 arch/parisc/kernel/unaligned.c : "0" (val), "r" (saddr), "r" (regs->isr) val 185 arch/parisc/kernel/unaligned.c DPRINTF("val = 0x" RFMT "\n", val); val 188 arch/parisc/kernel/unaligned.c ((__u32*)(regs->fr))[toreg] = val; val 190 arch/parisc/kernel/unaligned.c regs->gr[toreg] = val; val 197 arch/parisc/kernel/unaligned.c __u64 val = 0; val 225 arch/parisc/kernel/unaligned.c : "=r" (val), "=r" (ret) val 226 arch/parisc/kernel/unaligned.c : "0" (val), "r" (saddr), "r" (regs->isr) val 254 arch/parisc/kernel/unaligned.c val=((__u64)valh<<32)|(__u64)vall; val 258 arch/parisc/kernel/unaligned.c DPRINTF("val = 0x%llx\n", val); val 261 arch/parisc/kernel/unaligned.c regs->fr[toreg] = val; val 263 arch/parisc/kernel/unaligned.c regs->gr[toreg] = val; val 270 arch/parisc/kernel/unaligned.c unsigned long val = regs->gr[frreg]; val 274 arch/parisc/kernel/unaligned.c val = 0; val 277 arch/parisc/kernel/unaligned.c val, regs->isr, regs->ior); val 293 arch/parisc/kernel/unaligned.c : "r" (val), "r" (regs->ior), "r" (regs->isr) val 301 arch/parisc/kernel/unaligned.c unsigned long val; val 305 arch/parisc/kernel/unaligned.c val = ((__u32*)(regs->fr))[frreg]; val 307 arch/parisc/kernel/unaligned.c val = regs->gr[frreg]; val 309 arch/parisc/kernel/unaligned.c val = 0; val 312 arch/parisc/kernel/unaligned.c val, regs->isr, regs->ior); val 340 arch/parisc/kernel/unaligned.c : "r" (val), "r" (regs->ior), "r" (regs->isr) val 347 arch/parisc/kernel/unaligned.c __u64 val; val 351 arch/parisc/kernel/unaligned.c val = regs->fr[frreg]; val 353 arch/parisc/kernel/unaligned.c val = regs->gr[frreg]; val 355 arch/parisc/kernel/unaligned.c val = 0; val 358 arch/parisc/kernel/unaligned.c val, regs->isr, regs->ior); val 392 arch/parisc/kernel/unaligned.c : "r" (val), "r" (regs->ior), "r" (regs->isr) val 396 arch/parisc/kernel/unaligned.c unsigned long valh=(val>>32),vall=(val&0xffffffffl); val 106 arch/parisc/lib/io.c void memset_io(volatile void __iomem *addr, unsigned char val, int count) val 108 arch/parisc/lib/io.c u32 val32 = (val << 24) | (val << 16) | (val << 8) | val; val 110 arch/parisc/lib/io.c writeb(val, addr++); val 119 arch/parisc/lib/io.c writeb(val, addr++); val 337 arch/parisc/math-emu/cnv_float.h {unsigned int val = Sall(sgl_value) << SGL_EXP_LENGTH; \ val 340 arch/parisc/math-emu/cnv_float.h Dintp2(dresultB) = val >> (31 - exponent); \ val 343 arch/parisc/math-emu/cnv_float.h Dintp1(dresultA) = val >> (63 - exponent); \ val 344 arch/parisc/math-emu/cnv_float.h Dintp2(dresultB) = exponent <= 62 ? val << (exponent - 31) : 0; \ val 533 arch/parisc/math-emu/dbl_float.h #define Dblext_isone_lowp2(val) (Dextlowp2(val)!=0) val 534 arch/parisc/math-emu/dbl_float.h #define Dblext_isone_highp3(val) (Dexthighp3(val)!=0) val 535 arch/parisc/math-emu/dbl_float.h #define Dblext_isnotzero_low31p3(val) (Dextlow31p3(val)!=0) val 314 arch/parisc/math-emu/sgl_float.h #define Sglext_isone_lowp1(val) (Sextlowp1(val)!=0) val 315 arch/parisc/math-emu/sgl_float.h #define Sglext_isone_highp2(val) (Sexthighp2(val)!=0) val 316 arch/parisc/math-emu/sgl_float.h #define Sglext_isnotzero_low31p2(val) (Sextlow31p2(val)!=0) val 159 arch/powerpc/boot/4xx.c #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) val 172 arch/powerpc/boot/4xx.c u32 val, cs; val 189 arch/powerpc/boot/4xx.c val = SDRAM0_READ(DDR0_10); val 191 arch/powerpc/boot/4xx.c val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); val 193 arch/powerpc/boot/4xx.c while (val) { val 194 arch/powerpc/boot/4xx.c if (val & 0x1) val 196 arch/powerpc/boot/4xx.c val = val >> 1; val 203 arch/powerpc/boot/4xx.c u32 val, max_cs, max_col, max_row; val 207 arch/powerpc/boot/4xx.c val = SDRAM0_READ(DDR0_02); val 208 arch/powerpc/boot/4xx.c if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) val 212 arch/powerpc/boot/4xx.c max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); val 213 arch/powerpc/boot/4xx.c max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); val 214 arch/powerpc/boot/4xx.c max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); val 223 arch/powerpc/boot/4xx.c val = SDRAM0_READ(DDR0_14); val 225 arch/powerpc/boot/4xx.c if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) val 231 arch/powerpc/boot/4xx.c val = SDRAM0_READ(DDR0_42); val 233 arch/powerpc/boot/4xx.c row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT); val 239 arch/powerpc/boot/4xx.c val = SDRAM0_READ(DDR0_43); val 241 arch/powerpc/boot/4xx.c col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT); val 246 arch/powerpc/boot/4xx.c if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT)) val 11 arch/powerpc/boot/dcr.h #define mtdcr(rn, val) \ val 12 arch/powerpc/boot/dcr.h asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val)) val 19 arch/powerpc/boot/dcr.h #define mtdcrx(rn, val) \ val 21 arch/powerpc/boot/dcr.h asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \ val 26 arch/powerpc/boot/ep405.c u64 val; val 32 arch/powerpc/boot/ep405.c if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, &val)) { val 36 arch/powerpc/boot/ep405.c ibm405gp_fixup_clocks(val, 0xa8c000); val 40 arch/powerpc/boot/ep405.c if (!planetcore_get_decimal(table, PLANETCORE_KEY_KB_NVRAM, &val)) { val 48 arch/powerpc/boot/ep405.c reg[2] = (val << 10) & 0xffffffff; val 22 arch/powerpc/boot/ep8248e.c u64 val; val 27 arch/powerpc/boot/ep8248e.c if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, &val)) { val 32 arch/powerpc/boot/ep8248e.c pq2_fixup_clocks(val); val 20 arch/powerpc/boot/ep88xc.c u64 val; val 25 arch/powerpc/boot/ep88xc.c if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, &val)) { val 30 arch/powerpc/boot/ep88xc.c mpc885_fixup_clocks(val); val 21 arch/powerpc/boot/io.h static inline void out_8(volatile unsigned char *addr, int val) val 24 arch/powerpc/boot/io.h : "=m" (*addr) : "r" (val)); val 46 arch/powerpc/boot/io.h static inline void out_le16(volatile u16 *addr, int val) val 49 arch/powerpc/boot/io.h : "r" (val), "r" (addr)); val 52 arch/powerpc/boot/io.h static inline void out_be16(volatile u16 *addr, int val) val 55 arch/powerpc/boot/io.h : "=m" (*addr) : "r" (val)); val 76 arch/powerpc/boot/io.h static inline void out_le32(volatile unsigned *addr, int val) val 79 arch/powerpc/boot/io.h : "r" (val), "r" (addr)); val 82 arch/powerpc/boot/io.h static inline void out_be32(volatile unsigned *addr, int val) val 85 arch/powerpc/boot/io.h : "=m" (*addr) : "r" (val)); val 119 arch/powerpc/boot/libfdt-wrapper.c const char *val, val 123 arch/powerpc/boot/libfdt-wrapper.c name, val, len); val 128 arch/powerpc/boot/libfdt-wrapper.c const char *val) val 131 arch/powerpc/boot/libfdt-wrapper.c val); val 117 arch/powerpc/boot/ops.h #define setprop_val(devp, name, val) \ val 119 arch/powerpc/boot/ops.h typeof(val) x = (val); \ val 52 arch/powerpc/boot/planetcore.c int planetcore_get_decimal(const char *table, const char *key, u64 *val) val 58 arch/powerpc/boot/planetcore.c *val = strtoull(str, NULL, 10); val 62 arch/powerpc/boot/planetcore.c int planetcore_get_hex(const char *table, const char *key, u64 *val) val 68 arch/powerpc/boot/planetcore.c *val = strtoull(str, NULL, 16); val 34 arch/powerpc/boot/planetcore.h int planetcore_get_decimal(const char *table, const char *key, u64 *val); val 35 arch/powerpc/boot/planetcore.h int planetcore_get_hex(const char *table, const char *key, u64 *val); val 42 arch/powerpc/boot/xz_config.h static inline void put_unaligned_be32(u32 val, void *p) val 44 arch/powerpc/boot/xz_config.h *((u32 *)p) = cpu_to_be32(val); val 28 arch/powerpc/include/asm/archrandom.h unsigned long val; val 31 arch/powerpc/include/asm/archrandom.h rc = arch_get_random_seed_long(&val); val 33 arch/powerpc/include/asm/archrandom.h *v = val; val 375 arch/powerpc/include/asm/book3s/32/pgtable.h #define __swp_type(entry) ((entry).val & 0x1f) val 376 arch/powerpc/include/asm/book3s/32/pgtable.h #define __swp_offset(entry) ((entry).val >> 5) val 379 arch/powerpc/include/asm/book3s/32/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) val 187 arch/powerpc/include/asm/book3s/64/hash.h __be64 old, tmp, val, mask; val 192 arch/powerpc/include/asm/book3s/64/hash.h val = pte_raw(entry) & mask; val 202 arch/powerpc/include/asm/book3s/64/hash.h :"r" (val), "r" (ptep), "m" (*ptep), "r" (cpu_to_be64(H_PAGE_BUSY)) val 730 arch/powerpc/include/asm/book3s/64/pgtable.h #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ val 732 arch/powerpc/include/asm/book3s/64/pgtable.h #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) val 743 arch/powerpc/include/asm/book3s/64/pgtable.h #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) val 110 arch/powerpc/include/asm/cache.h #define _set_L2CR(val) do { } while(0) val 111 arch/powerpc/include/asm/cache.h #define _set_L3CR(val) do { } while(0) val 67 arch/powerpc/include/asm/cell-pmu.h extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val); val 69 arch/powerpc/include/asm/cell-pmu.h extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val); val 72 arch/powerpc/include/asm/cell-pmu.h extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val); val 74 arch/powerpc/include/asm/cell-pmu.h extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val); val 42 arch/powerpc/include/asm/cell-regs.h u64 val; val 47 arch/powerpc/include/asm/cell-regs.h u64 val; val 18 arch/powerpc/include/asm/cmpxchg.h static inline u32 __xchg_##type##sfx(volatile void *p, u32 val) \ val 25 arch/powerpc/include/asm/cmpxchg.h val <<= bitoff; \ val 36 arch/powerpc/include/asm/cmpxchg.h : "r" (p), "r" (val), "r" (prev_mask) \ val 89 arch/powerpc/include/asm/cmpxchg.h __xchg_u32_local(volatile void *p, unsigned long val) val 99 arch/powerpc/include/asm/cmpxchg.h : "r" (p), "r" (val) val 106 arch/powerpc/include/asm/cmpxchg.h __xchg_u32_relaxed(u32 *p, unsigned long val) val 116 arch/powerpc/include/asm/cmpxchg.h : "r" (p), "r" (val) val 124 arch/powerpc/include/asm/cmpxchg.h __xchg_u64_local(volatile void *p, unsigned long val) val 134 arch/powerpc/include/asm/cmpxchg.h : "r" (p), "r" (val) val 141 arch/powerpc/include/asm/cmpxchg.h __xchg_u64_relaxed(u64 *p, unsigned long val) val 151 arch/powerpc/include/asm/cmpxchg.h : "r" (p), "r" (val) val 33 arch/powerpc/include/asm/dcr-native.h extern void __mtdcr(unsigned int reg, unsigned int val); val 47 arch/powerpc/include/asm/dcr-native.h static inline void mtdcrx(unsigned int reg, unsigned int val) val 50 arch/powerpc/include/asm/dcr-native.h : : "r" (val), "r" (reg)); val 81 arch/powerpc/include/asm/dcr-native.h unsigned int val; val 86 arch/powerpc/include/asm/dcr-native.h val = mfdcrx(base_data); val 89 arch/powerpc/include/asm/dcr-native.h val = __mfdcr(base_data); val 92 arch/powerpc/include/asm/dcr-native.h return val; val 96 arch/powerpc/include/asm/dcr-native.h unsigned val) val 103 arch/powerpc/include/asm/dcr-native.h mtdcrx(base_data, val); val 106 arch/powerpc/include/asm/dcr-native.h __mtdcr(base_data, val); val 115 arch/powerpc/include/asm/dcr-native.h unsigned int val; val 120 arch/powerpc/include/asm/dcr-native.h val = (mfdcrx(base_data) & ~clr) | set; val 121 arch/powerpc/include/asm/dcr-native.h mtdcrx(base_data, val); val 124 arch/powerpc/include/asm/dcr-native.h val = (__mfdcr(base_data) & ~clr) | set; val 125 arch/powerpc/include/asm/dcr-native.h __mtdcr(base_data, val); val 227 arch/powerpc/include/asm/eeh.h int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val); val 228 arch/powerpc/include/asm/eeh.h int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val); val 329 arch/powerpc/include/asm/eeh.h #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) val 375 arch/powerpc/include/asm/eeh.h #define EEH_POSSIBLE_ERROR(val, type) (0) val 385 arch/powerpc/include/asm/eeh.h u8 val = in_8(addr); val 386 arch/powerpc/include/asm/eeh.h if (EEH_POSSIBLE_ERROR(val, u8)) val 388 arch/powerpc/include/asm/eeh.h return val; val 393 arch/powerpc/include/asm/eeh.h u16 val = in_le16(addr); val 394 arch/powerpc/include/asm/eeh.h if (EEH_POSSIBLE_ERROR(val, u16)) val 396 arch/powerpc/include/asm/eeh.h return val; val 401 arch/powerpc/include/asm/eeh.h u32 val = in_le32(addr); val 402 arch/powerpc/include/asm/eeh.h if (EEH_POSSIBLE_ERROR(val, u32)) val 404 arch/powerpc/include/asm/eeh.h return val; val 409 arch/powerpc/include/asm/eeh.h u64 val = in_le64(addr); val 410 arch/powerpc/include/asm/eeh.h if (EEH_POSSIBLE_ERROR(val, u64)) val 412 arch/powerpc/include/asm/eeh.h return val; val 417 arch/powerpc/include/asm/eeh.h u16 val = in_be16(addr); val 418 arch/powerpc/include/asm/eeh.h if (EEH_POSSIBLE_ERROR(val, u16)) val 420 arch/powerpc/include/asm/eeh.h return val; val 425 arch/powerpc/include/asm/eeh.h u32 val = in_be32(addr); val 426 arch/powerpc/include/asm/eeh.h if (EEH_POSSIBLE_ERROR(val, u32)) val 428 arch/powerpc/include/asm/eeh.h return val; val 433 arch/powerpc/include/asm/eeh.h u64 val = in_be64(addr); val 434 arch/powerpc/include/asm/eeh.h if (EEH_POSSIBLE_ERROR(val, u64)) val 436 arch/powerpc/include/asm/eeh.h return val; val 17 arch/powerpc/include/asm/emulated_ops.h atomic_t val; val 59 arch/powerpc/include/asm/emulated_ops.h atomic_inc(&ppc_emulated.type.val); \ val 40 arch/powerpc/include/asm/fadump-internal.h u64 val = 0; val 43 arch/powerpc/include/asm/fadump-internal.h for (i = 0; i < sizeof(val); i++) val 44 arch/powerpc/include/asm/fadump-internal.h val = (*str) ? (val << 8) | *str++ : val << 8; val 45 arch/powerpc/include/asm/fadump-internal.h return val; val 39 arch/powerpc/include/asm/feature-fixups.h #define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ val 46 arch/powerpc/include/asm/feature-fixups.h FTR_ENTRY_LONG val; \ val 61 arch/powerpc/include/asm/feature-fixups.h #define END_FTR_SECTION_NESTED(msk, val, label) \ val 63 arch/powerpc/include/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) val 65 arch/powerpc/include/asm/feature-fixups.h #define END_FTR_SECTION(msk, val) \ val 66 arch/powerpc/include/asm/feature-fixups.h END_FTR_SECTION_NESTED(msk, val, 97) val 76 arch/powerpc/include/asm/feature-fixups.h #define ALT_FTR_SECTION_END_NESTED(msk, val, label) \ val 77 arch/powerpc/include/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) val 82 arch/powerpc/include/asm/feature-fixups.h #define ALT_FTR_SECTION_END(msk, val) \ val 83 arch/powerpc/include/asm/feature-fixups.h ALT_FTR_SECTION_END_NESTED(msk, val, 97) val 93 arch/powerpc/include/asm/feature-fixups.h #define END_MMU_FTR_SECTION_NESTED(msk, val, label) \ val 95 arch/powerpc/include/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup) val 97 arch/powerpc/include/asm/feature-fixups.h #define END_MMU_FTR_SECTION(msk, val) \ val 98 arch/powerpc/include/asm/feature-fixups.h END_MMU_FTR_SECTION_NESTED(msk, val, 97) val 109 arch/powerpc/include/asm/feature-fixups.h #define ALT_MMU_FTR_SECTION_END_NESTED(msk, val, label) \ val 110 arch/powerpc/include/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup) val 115 arch/powerpc/include/asm/feature-fixups.h #define ALT_MMU_FTR_SECTION_END(msk, val) \ val 116 arch/powerpc/include/asm/feature-fixups.h ALT_MMU_FTR_SECTION_END_NESTED(msk, val, 97) val 126 arch/powerpc/include/asm/feature-fixups.h #define END_FW_FTR_SECTION_NESTED(msk, val, label) \ val 128 arch/powerpc/include/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup) val 130 arch/powerpc/include/asm/feature-fixups.h #define END_FW_FTR_SECTION(msk, val) \ val 131 arch/powerpc/include/asm/feature-fixups.h END_FW_FTR_SECTION_NESTED(msk, val, 97) val 139 arch/powerpc/include/asm/feature-fixups.h #define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label) \ val 140 arch/powerpc/include/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup) val 145 arch/powerpc/include/asm/feature-fixups.h #define ALT_FW_FTR_SECTION_END(msk, val) \ val 146 arch/powerpc/include/asm/feature-fixups.h ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97) val 154 arch/powerpc/include/asm/feature-fixups.h #define ASM_FTR_IF(section_if, section_else, msk, val) \ val 159 arch/powerpc/include/asm/feature-fixups.h stringify_in_c(ALT_FTR_SECTION_END((msk), (val))) val 167 arch/powerpc/include/asm/feature-fixups.h #define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \ val 172 arch/powerpc/include/asm/feature-fixups.h stringify_in_c(ALT_MMU_FTR_SECTION_END((msk), (val))) val 56 arch/powerpc/include/asm/hw_breakpoint.h unsigned long val, void *data); val 79 arch/powerpc/include/asm/imc-pmu.h u64 val; val 10 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr), mem, addr) val 11 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr) val 12 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr) val 13 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr) val 14 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr) val 19 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr) val 20 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr) val 26 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port), pio, port) val 27 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port), pio, port) val 28 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port), pio, port) val 114 arch/powerpc/include/asm/io.h static inline void name(volatile u##size __iomem *addr, u##size val) \ val 117 arch/powerpc/include/asm/io.h : "=Z" (*addr) : "r" (val) : "memory"); \ val 131 arch/powerpc/include/asm/io.h static inline void name(volatile u##size __iomem *addr, u##size val) \ val 134 arch/powerpc/include/asm/io.h : "=m" (*addr) : "r" (val) : "memory"); \ val 176 arch/powerpc/include/asm/io.h static inline void out_le64(volatile u64 __iomem *addr, u64 val) val 178 arch/powerpc/include/asm/io.h out_be64(addr, swab64(val)); val 190 arch/powerpc/include/asm/io.h static inline void out_be64(volatile u64 __iomem *addr, u64 val) val 192 arch/powerpc/include/asm/io.h out_le64(addr, swab64(val)); val 346 arch/powerpc/include/asm/io.h static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr) val 349 arch/powerpc/include/asm/io.h : : "r" (val), "r" (paddr) : "memory"); val 352 arch/powerpc/include/asm/io.h static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr) val 355 arch/powerpc/include/asm/io.h : : "r" (val), "r" (paddr) : "memory"); val 358 arch/powerpc/include/asm/io.h static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr) val 361 arch/powerpc/include/asm/io.h : : "r" (val), "r" (paddr) : "memory"); val 364 arch/powerpc/include/asm/io.h static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) val 367 arch/powerpc/include/asm/io.h : : "r" (val), "r" (paddr) : "memory"); val 370 arch/powerpc/include/asm/io.h static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr) val 372 arch/powerpc/include/asm/io.h __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr); val 450 arch/powerpc/include/asm/io.h static inline void name(unsigned int val, unsigned int port) \ val 459 arch/powerpc/include/asm/io.h : : "r" (val), "r" (port + _IO_BASE) \ val 487 arch/powerpc/include/asm/io.h #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) val 488 arch/powerpc/include/asm/io.h #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) val 489 arch/powerpc/include/asm/io.h #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) val 490 arch/powerpc/include/asm/io.h #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) val 491 arch/powerpc/include/asm/io.h #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) val 492 arch/powerpc/include/asm/io.h #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) val 493 arch/powerpc/include/asm/io.h #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) val 514 arch/powerpc/include/asm/io.h #define __do_outb(val, port) _rec_outb(val, port) val 515 arch/powerpc/include/asm/io.h #define __do_outw(val, port) _rec_outw(val, port) val 516 arch/powerpc/include/asm/io.h #define __do_outl(val, port) _rec_outl(val, port) val 521 arch/powerpc/include/asm/io.h #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); val 522 arch/powerpc/include/asm/io.h #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); val 523 arch/powerpc/include/asm/io.h #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); val 665 arch/powerpc/include/asm/io.h #define outb_p(val, port) (udelay(1), outb((val), (port))) val 667 arch/powerpc/include/asm/io.h #define outw_p(val, port) (udelay(1), outw((val), (port))) val 669 arch/powerpc/include/asm/io.h #define outl_p(val, port) (udelay(1), outl((val), (port))) val 751 arch/powerpc/include/asm/io.h #define mmio_write16be(val, addr) writew_be(val, addr) val 752 arch/powerpc/include/asm/io.h #define mmio_write32be(val, addr) writel_be(val, addr) val 753 arch/powerpc/include/asm/io.h #define mmio_write64be(val, addr) writeq_be(val, addr) val 88 arch/powerpc/include/asm/kprobes.h unsigned long val, void *data); val 235 arch/powerpc/include/asm/kvm_book3s.h bool upper, u32 val); val 328 arch/powerpc/include/asm/kvm_book3s.h static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) val 330 arch/powerpc/include/asm/kvm_book3s.h vcpu->arch.regs.gpr[num] = val; val 338 arch/powerpc/include/asm/kvm_book3s.h static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) val 340 arch/powerpc/include/asm/kvm_book3s.h vcpu->arch.regs.ccr = val; val 348 arch/powerpc/include/asm/kvm_book3s.h static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, ulong val) val 350 arch/powerpc/include/asm/kvm_book3s.h vcpu->arch.regs.xer = val; val 358 arch/powerpc/include/asm/kvm_book3s.h static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val) val 360 arch/powerpc/include/asm/kvm_book3s.h vcpu->arch.regs.ctr = val; val 368 arch/powerpc/include/asm/kvm_book3s.h static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val) val 370 arch/powerpc/include/asm/kvm_book3s.h vcpu->arch.regs.link = val; val 378 arch/powerpc/include/asm/kvm_book3s.h static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val) val 380 arch/powerpc/include/asm/kvm_book3s.h vcpu->arch.regs.nip = val; val 26 arch/powerpc/include/asm/kvm_booke.h static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) val 28 arch/powerpc/include/asm/kvm_booke.h vcpu->arch.regs.gpr[num] = val; val 36 arch/powerpc/include/asm/kvm_booke.h static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) val 38 arch/powerpc/include/asm/kvm_booke.h vcpu->arch.regs.ccr = val; val 46 arch/powerpc/include/asm/kvm_booke.h static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, ulong val) val 48 arch/powerpc/include/asm/kvm_booke.h vcpu->arch.regs.xer = val; val 62 arch/powerpc/include/asm/kvm_booke.h static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val) val 64 arch/powerpc/include/asm/kvm_booke.h vcpu->arch.regs.ctr = val; val 72 arch/powerpc/include/asm/kvm_booke.h static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val) val 74 arch/powerpc/include/asm/kvm_booke.h vcpu->arch.regs.link = val; val 82 arch/powerpc/include/asm/kvm_booke.h static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val) val 84 arch/powerpc/include/asm/kvm_booke.h vcpu->arch.regs.nip = val; val 80 arch/powerpc/include/asm/kvm_ppc.h u64 val, unsigned int bytes, val 269 arch/powerpc/include/asm/kvm_ppc.h union kvmppc_one_reg *val); val 271 arch/powerpc/include/asm/kvm_ppc.h union kvmppc_one_reg *val); val 406 arch/powerpc/include/asm/kvm_ppc.h #define set_reg_val(id, val) ({ \ val 409 arch/powerpc/include/asm/kvm_ppc.h case 4: __v = (val).wval; break; \ val 410 arch/powerpc/include/asm/kvm_ppc.h case 8: __v = (val).dval; break; \ val 692 arch/powerpc/include/asm/kvm_ppc.h union kvmppc_one_reg *val); val 694 arch/powerpc/include/asm/kvm_ppc.h union kvmppc_one_reg *val); val 729 arch/powerpc/include/asm/kvm_ppc.h union kvmppc_one_reg *val) val 732 arch/powerpc/include/asm/kvm_ppc.h union kvmppc_one_reg *val) val 921 arch/powerpc/include/asm/kvm_ppc.h static inline void kvmppc_set_##reg(struct kvm_vcpu *vcpu, ulong val) \ val 923 arch/powerpc/include/asm/kvm_ppc.h mtspr(bookehv_spr, val); \ val 936 arch/powerpc/include/asm/kvm_ppc.h static inline void kvmppc_set_##reg(struct kvm_vcpu *vcpu, u##size val) \ val 939 arch/powerpc/include/asm/kvm_ppc.h vcpu->arch.shared->reg = cpu_to_be##size(val); \ val 941 arch/powerpc/include/asm/kvm_ppc.h vcpu->arch.shared->reg = cpu_to_le##size(val); \ val 974 arch/powerpc/include/asm/kvm_ppc.h static inline void kvmppc_set_msr_fast(struct kvm_vcpu *vcpu, u64 val) val 977 arch/powerpc/include/asm/kvm_ppc.h vcpu->arch.shared->msr = cpu_to_be64(val); val 979 arch/powerpc/include/asm/kvm_ppc.h vcpu->arch.shared->msr = cpu_to_le64(val); val 996 arch/powerpc/include/asm/kvm_ppc.h static inline void kvmppc_set_sr(struct kvm_vcpu *vcpu, int nr, u32 val) val 999 arch/powerpc/include/asm/kvm_ppc.h vcpu->arch.shared->sr[nr] = cpu_to_be32(val); val 1001 arch/powerpc/include/asm/kvm_ppc.h vcpu->arch.shared->sr[nr] = cpu_to_le32(val); val 76 arch/powerpc/include/asm/machdep.h void (*rtc_write_val)(int addr, unsigned char val); val 86 arch/powerpc/include/asm/machdep.h void (*nvram_write_val)(int addr, unsigned char val); val 26 arch/powerpc/include/asm/mc146818rtc.h #define CMOS_WRITE(val, addr) ({ \ val 28 arch/powerpc/include/asm/mc146818rtc.h outb_p((val),RTC_PORT(1)); \ val 59 arch/powerpc/include/asm/mpc5121.h int mpc512x_cs_config(unsigned int cs, u32 val); val 389 arch/powerpc/include/asm/mpic.h #define MPIC_REGSET(val) (((val) & 0xf ) << 28) val 381 arch/powerpc/include/asm/nohash/32/pgtable.h #define __swp_type(entry) ((entry).val & 0x1f) val 382 arch/powerpc/include/asm/nohash/32/pgtable.h #define __swp_offset(entry) ((entry).val >> 5) val 385 arch/powerpc/include/asm/nohash/32/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) val 128 arch/powerpc/include/asm/nohash/64/pgtable.h static inline void pmd_set(pmd_t *pmdp, unsigned long val) val 130 arch/powerpc/include/asm/nohash/64/pgtable.h *pmdp = __pmd(val); val 150 arch/powerpc/include/asm/nohash/64/pgtable.h static inline void pud_set(pud_t *pudp, unsigned long val) val 152 arch/powerpc/include/asm/nohash/64/pgtable.h *pudp = __pud(val); val 180 arch/powerpc/include/asm/nohash/64/pgtable.h static inline void pgd_set(pgd_t *pgdp, unsigned long val) val 182 arch/powerpc/include/asm/nohash/64/pgtable.h *pgdp = __pgd(val); val 348 arch/powerpc/include/asm/nohash/64/pgtable.h #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ val 350 arch/powerpc/include/asm/nohash/64/pgtable.h #define __swp_offset(x) ((x).val >> PTE_RPN_SHIFT) val 356 arch/powerpc/include/asm/nohash/64/pgtable.h #define __swp_entry_to_pte(x) __pte((x).val) val 167 arch/powerpc/include/asm/opal.h int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val); val 168 arch/powerpc/include/asm/opal.h int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val); val 206 arch/powerpc/include/asm/opal.h int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); val 95 arch/powerpc/include/asm/oprofile_impl.h static inline void classic_ctr_write(unsigned int i, unsigned int val) val 99 arch/powerpc/include/asm/oprofile_impl.h mtspr(SPRN_PMC1, val); val 102 arch/powerpc/include/asm/oprofile_impl.h mtspr(SPRN_PMC2, val); val 105 arch/powerpc/include/asm/oprofile_impl.h mtspr(SPRN_PMC3, val); val 108 arch/powerpc/include/asm/oprofile_impl.h mtspr(SPRN_PMC4, val); val 111 arch/powerpc/include/asm/oprofile_impl.h mtspr(SPRN_PMC5, val); val 114 arch/powerpc/include/asm/oprofile_impl.h mtspr(SPRN_PMC6, val); val 120 arch/powerpc/include/asm/oprofile_impl.h mtspr(SPRN_PMC7, val); val 123 arch/powerpc/include/asm/oprofile_impl.h mtspr(SPRN_PMC8, val); val 485 arch/powerpc/include/asm/pasemi_dma.h extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val); val 488 arch/powerpc/include/asm/pasemi_dma.h extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val); val 491 arch/powerpc/include/asm/pasemi_dma.h extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val); val 135 arch/powerpc/include/asm/pci-bridge.h int dev_fn, int where, u8 *val); val 137 arch/powerpc/include/asm/pci-bridge.h int dev_fn, int where, u16 *val); val 139 arch/powerpc/include/asm/pci-bridge.h int dev_fn, int where, u32 *val); val 141 arch/powerpc/include/asm/pci-bridge.h int dev_fn, int where, u8 val); val 143 arch/powerpc/include/asm/pci-bridge.h int dev_fn, int where, u16 val); val 145 arch/powerpc/include/asm/pci-bridge.h int dev_fn, int where, u32 val); val 155 arch/powerpc/include/asm/pci-bridge.h int offset, int len, u32 *val); val 159 arch/powerpc/include/asm/pci-bridge.h int offset, int len, u32 *val); val 162 arch/powerpc/include/asm/pci-bridge.h int offset, int len, u32 val); val 80 arch/powerpc/include/asm/pci.h extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, val 82 arch/powerpc/include/asm/pci.h extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, val 54 arch/powerpc/include/asm/ppc-pci.h int rtas_write_config(struct pci_dn *, int where, int size, u32 val); val 55 arch/powerpc/include/asm/ppc-pci.h int rtas_read_config(struct pci_dn *, int where, int size, u32 *val); val 310 arch/powerpc/include/asm/processor.h #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) val 313 arch/powerpc/include/asm/processor.h extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); val 316 arch/powerpc/include/asm/processor.h #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) val 319 arch/powerpc/include/asm/processor.h extern int set_endian(struct task_struct *tsk, unsigned int val); val 322 arch/powerpc/include/asm/processor.h #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) val 325 arch/powerpc/include/asm/processor.h extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); val 495 arch/powerpc/include/asm/ps3.h void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val); val 497 arch/powerpc/include/asm/ps3.h void ps3_write_ctr(u32 cpu, u32 ctr, u32 val); val 500 arch/powerpc/include/asm/ps3.h void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val); val 502 arch/powerpc/include/asm/ps3.h void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val); val 120 arch/powerpc/include/asm/ptrace.h unsigned long val) val 122 arch/powerpc/include/asm/ptrace.h regs->nip = val; val 1356 arch/powerpc/include/asm/reg.h static inline void mtmsr_isync(unsigned long val) val 1359 arch/powerpc/include/asm/reg.h "r" (val), "i" (CPU_FTR_ARCH_206) : "memory"); val 1435 arch/powerpc/include/asm/reg.h static inline void mtsrin(u32 val, u32 idx) val 1437 arch/powerpc/include/asm/reg.h asm volatile("mtsrin %0, %1" : : "r" (val), "r" (idx)); val 13 arch/powerpc/include/asm/setjmp.h extern void longjmp(jmp_buf env, int val) __attribute__((noreturn)); val 167 arch/powerpc/include/asm/sfp-machine.h #define __FP_PACK_S(val,X) \ val 170 arch/powerpc/include/asm/sfp-machine.h _FP_PACK_RAW_1_P(S,val,X); \ val 174 arch/powerpc/include/asm/sfp-machine.h #define __FP_PACK_D(val,X) \ val 178 arch/powerpc/include/asm/sfp-machine.h _FP_PACK_RAW_2_P(D, val, X); \ val 181 arch/powerpc/include/asm/sfp-machine.h #define __FP_PACK_DS(val,X) \ val 191 arch/powerpc/include/asm/sfp-machine.h _FP_PACK_RAW_2_P(D, val, X); \ val 103 arch/powerpc/include/asm/sstep.h unsigned long val; val 56 arch/powerpc/include/asm/syscall.h int error, long val) val 69 arch/powerpc/include/asm/syscall.h regs->gpr[3] = val; val 77 arch/powerpc/include/asm/syscall.h unsigned long val, mask = -1UL; val 86 arch/powerpc/include/asm/syscall.h val = regs->orig_gpr3; val 88 arch/powerpc/include/asm/syscall.h val = regs->gpr[3 + n]; val 90 arch/powerpc/include/asm/syscall.h args[n] = val & mask; val 156 arch/powerpc/include/asm/time.h static inline void set_dec(u64 val) val 159 arch/powerpc/include/asm/time.h mtspr(SPRN_PIT, (u32) val); val 162 arch/powerpc/include/asm/time.h --val; val 164 arch/powerpc/include/asm/time.h mtspr(SPRN_DEC, val); val 84 arch/powerpc/include/asm/tsi108.h int offset, int len, u32 val); val 86 arch/powerpc/include/asm/tsi108.h int offset, int len, u32 * val); val 108 arch/powerpc/include/asm/tsi108.h static inline void tsi108_write_reg(u32 reg_offset, u32 val) val 110 arch/powerpc/include/asm/tsi108.h out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val); val 23 arch/powerpc/include/asm/ultravisor.h static inline void set_ptcr_when_no_uv(u64 val) val 26 arch/powerpc/include/asm/ultravisor.h mtspr(SPRN_PTCR, val); val 35 arch/powerpc/include/asm/vas.h #define SET_FIELD(m, v, val) \ val 36 arch/powerpc/include/asm/vas.h (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_LSH(m)) & (m))) val 27 arch/powerpc/include/asm/vga.h static inline void scr_writew(u16 val, volatile u16 *addr) val 29 arch/powerpc/include/asm/vga.h *addr = cpu_to_le16(val); val 21 arch/powerpc/include/asm/word-at-a-time.h static inline long prep_zero_mask(unsigned long val, unsigned long rhs, const struct word_at_a_time *c) val 23 arch/powerpc/include/asm/word-at-a-time.h unsigned long mask = (val & c->low_bits) + c->low_bits; val 37 arch/powerpc/include/asm/word-at-a-time.h static inline bool has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) val 39 arch/powerpc/include/asm/word-at-a-time.h unsigned long rhs = val | c->low_bits; val 41 arch/powerpc/include/asm/word-at-a-time.h return (val + c->high_bits) & ~rhs; val 73 arch/powerpc/kernel/asm-offsets.c #define STACK_PT_REGS_OFFSET(sym, val) \ val 74 arch/powerpc/kernel/asm-offsets.c DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val)) val 1797 arch/powerpc/kernel/eeh.c static int eeh_enable_dbgfs_set(void *data, u64 val) val 1799 arch/powerpc/kernel/eeh.c if (val) val 1807 arch/powerpc/kernel/eeh.c static int eeh_enable_dbgfs_get(void *data, u64 *val) val 1810 arch/powerpc/kernel/eeh.c *val = 0x1ul; val 1812 arch/powerpc/kernel/eeh.c *val = 0x0ul; val 703 arch/powerpc/kernel/eeh_pe.c uint32_t val; val 717 arch/powerpc/kernel/eeh_pe.c eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val); val 718 arch/powerpc/kernel/eeh_pe.c if (!(val & PCI_EXP_SLTSTA_PDS)) { val 719 arch/powerpc/kernel/eeh_pe.c eeh_edev_dbg(edev, "No card in the slot (0x%04x) !\n", val); val 724 arch/powerpc/kernel/eeh_pe.c eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val); val 725 arch/powerpc/kernel/eeh_pe.c if (val & PCI_EXP_SLTCAP_PCP) { val 726 arch/powerpc/kernel/eeh_pe.c eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val); val 727 arch/powerpc/kernel/eeh_pe.c if (val & PCI_EXP_SLTCTL_PCC) { val 729 arch/powerpc/kernel/eeh_pe.c val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC); val 730 arch/powerpc/kernel/eeh_pe.c val |= (0x0100 & PCI_EXP_SLTCTL_PIC); val 731 arch/powerpc/kernel/eeh_pe.c eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val); val 737 arch/powerpc/kernel/eeh_pe.c eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val); val 738 arch/powerpc/kernel/eeh_pe.c val &= ~PCI_EXP_LNKCTL_LD; val 739 arch/powerpc/kernel/eeh_pe.c eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val); val 742 arch/powerpc/kernel/eeh_pe.c eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val); val 743 arch/powerpc/kernel/eeh_pe.c if (!(val & PCI_EXP_LNKCAP_DLLLARC)) { val 744 arch/powerpc/kernel/eeh_pe.c eeh_edev_dbg(edev, "No link reporting capability (0x%08x) \n", val); val 755 arch/powerpc/kernel/eeh_pe.c eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val); val 756 arch/powerpc/kernel/eeh_pe.c if (val & PCI_EXP_LNKSTA_DLLLA) val 760 arch/powerpc/kernel/eeh_pe.c if (val & PCI_EXP_LNKSTA_DLLLA) val 762 arch/powerpc/kernel/eeh_pe.c (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB"); val 764 arch/powerpc/kernel/eeh_pe.c eeh_edev_dbg(edev, "Link not ready (0x%04x)\n", val); val 21 arch/powerpc/kernel/head_booke.h #define ALLOC_STACK_FRAME(reg, val) \ val 22 arch/powerpc/kernel/head_booke.h addi reg,reg,val val 24 arch/powerpc/kernel/head_booke.h #define ALLOC_STACK_FRAME(reg, val) \ val 25 arch/powerpc/kernel/head_booke.h addis reg,reg,val@ha; \ val 26 arch/powerpc/kernel/head_booke.h addi reg,reg,val@l val 360 arch/powerpc/kernel/hw_breakpoint.c struct notifier_block *unused, unsigned long val, void *data) val 364 arch/powerpc/kernel/hw_breakpoint.c switch (val) { val 76 arch/powerpc/kernel/iomap.c void iowrite8(u8 val, void __iomem *addr) val 78 arch/powerpc/kernel/iomap.c writeb(val, addr); val 80 arch/powerpc/kernel/iomap.c void iowrite16(u16 val, void __iomem *addr) val 82 arch/powerpc/kernel/iomap.c writew(val, addr); val 84 arch/powerpc/kernel/iomap.c void iowrite16be(u16 val, void __iomem *addr) val 86 arch/powerpc/kernel/iomap.c writew_be(val, addr); val 88 arch/powerpc/kernel/iomap.c void iowrite32(u32 val, void __iomem *addr) val 90 arch/powerpc/kernel/iomap.c writel(val, addr); val 92 arch/powerpc/kernel/iomap.c void iowrite32be(u32 val, void __iomem *addr) val 94 arch/powerpc/kernel/iomap.c writel_be(val, addr); val 102 arch/powerpc/kernel/iomap.c void iowrite64(u64 val, void __iomem *addr) val 104 arch/powerpc/kernel/iomap.c writeq(val, addr); val 106 arch/powerpc/kernel/iomap.c void iowrite64_lo_hi(u64 val, void __iomem *addr) val 108 arch/powerpc/kernel/iomap.c writeq(val, addr); val 110 arch/powerpc/kernel/iomap.c void iowrite64_hi_lo(u64 val, void __iomem *addr) val 112 arch/powerpc/kernel/iomap.c writeq(val, addr); val 114 arch/powerpc/kernel/iomap.c void iowrite64be(u64 val, void __iomem *addr) val 116 arch/powerpc/kernel/iomap.c writeq_be(val, addr); val 118 arch/powerpc/kernel/iomap.c void iowrite64be_lo_hi(u64 val, void __iomem *addr) val 120 arch/powerpc/kernel/iomap.c writeq_be(val, addr); val 122 arch/powerpc/kernel/iomap.c void iowrite64be_hi_lo(u64 val, void __iomem *addr) val 124 arch/powerpc/kernel/iomap.c writeq_be(val, addr); val 161 arch/powerpc/kernel/module_32.c static inline int entry_matches(struct ppc_plt_entry *entry, Elf32_Addr val) val 163 arch/powerpc/kernel/module_32.c if (entry->jump[0] != (PPC_INST_ADDIS | __PPC_RT(R12) | PPC_HA(val))) val 166 arch/powerpc/kernel/module_32.c PPC_LO(val))) val 173 arch/powerpc/kernel/module_32.c Elf32_Addr val, val 179 arch/powerpc/kernel/module_32.c pr_debug("Doing plt for call to 0x%x at 0x%x\n", val, (unsigned int)location); val 189 arch/powerpc/kernel/module_32.c if (entry_matches(entry, val)) return (uint32_t)entry; val 199 arch/powerpc/kernel/module_32.c entry->jump[0] = PPC_INST_ADDIS | __PPC_RT(R12) | PPC_HA(val); val 200 arch/powerpc/kernel/module_32.c entry->jump[1] = PPC_INST_ADDI | __PPC_RT(R12) | __PPC_RA(R12) | PPC_LO(val); val 204 arch/powerpc/kernel/module_32.c pr_debug("Initialized plt for 0x%x at %p\n", val, entry); val 147 arch/powerpc/kernel/optprobes.c void patch_imm32_load_insns(unsigned int val, kprobe_opcode_t *addr) val 151 arch/powerpc/kernel/optprobes.c ((val >> 16) & 0xffff)); val 156 arch/powerpc/kernel/optprobes.c ___PPC_RS(4) | (val & 0xffff)); val 163 arch/powerpc/kernel/optprobes.c void patch_imm64_load_insns(unsigned long val, kprobe_opcode_t *addr) val 167 arch/powerpc/kernel/optprobes.c ((val >> 48) & 0xffff)); val 172 arch/powerpc/kernel/optprobes.c ___PPC_RS(3) | ((val >> 32) & 0xffff)); val 182 arch/powerpc/kernel/optprobes.c ___PPC_RS(3) | ((val >> 16) & 0xffff)); val 187 arch/powerpc/kernel/optprobes.c ___PPC_RS(3) | (val & 0xffff)); val 482 arch/powerpc/kernel/pci-common.c int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) val 505 arch/powerpc/kernel/pci-common.c *((u8 *)val) = in_8(addr); val 510 arch/powerpc/kernel/pci-common.c *((u16 *)val) = in_le16(addr); val 515 arch/powerpc/kernel/pci-common.c *((u32 *)val) = in_le32(addr); val 522 arch/powerpc/kernel/pci-common.c int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) val 550 arch/powerpc/kernel/pci-common.c out_8(addr, val >> 24); val 555 arch/powerpc/kernel/pci-common.c out_le16(addr, val >> 16); val 560 arch/powerpc/kernel/pci-common.c out_le32(addr, val); val 1517 arch/powerpc/kernel/pci-common.c null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ val 1524 arch/powerpc/kernel/pci-common.c int len, u32 *val) val 1531 arch/powerpc/kernel/pci-common.c int len, u32 val) val 1332 arch/powerpc/kernel/process.c static void print_bits(unsigned long val, struct regbit *bits, const char *sep) val 1337 arch/powerpc/kernel/process.c if (val & bits->bit) { val 1351 arch/powerpc/kernel/process.c static void print_tm_bits(unsigned long val) val 1360 arch/powerpc/kernel/process.c if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { val 1362 arch/powerpc/kernel/process.c print_bits(val, msr_tm_bits, ""); val 1367 arch/powerpc/kernel/process.c static void print_tm_bits(unsigned long val) {} val 1370 arch/powerpc/kernel/process.c static void print_msr_bits(unsigned long val) val 1373 arch/powerpc/kernel/process.c print_bits(val, msr_bits, ","); val 1374 arch/powerpc/kernel/process.c print_tm_bits(val); val 1821 arch/powerpc/kernel/process.c int set_fpexc_mode(struct task_struct *tsk, unsigned int val) val 1829 arch/powerpc/kernel/process.c if (val & PR_FP_EXC_SW_ENABLE) { val 1845 arch/powerpc/kernel/process.c tsk->thread.fpexc_mode = val & val 1861 arch/powerpc/kernel/process.c if (val > PR_FP_EXC_PRECISE) val 1863 arch/powerpc/kernel/process.c tsk->thread.fpexc_mode = __pack_fe01(val); val 1872 arch/powerpc/kernel/process.c unsigned int val; val 1890 arch/powerpc/kernel/process.c val = tsk->thread.fpexc_mode; val 1897 arch/powerpc/kernel/process.c val = __unpack_fe01(tsk->thread.fpexc_mode); val 1898 arch/powerpc/kernel/process.c return put_user(val, (unsigned int __user *) adr); val 1901 arch/powerpc/kernel/process.c int set_endian(struct task_struct *tsk, unsigned int val) val 1905 arch/powerpc/kernel/process.c if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || val 1906 arch/powerpc/kernel/process.c (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) val 1912 arch/powerpc/kernel/process.c if (val == PR_ENDIAN_BIG) val 1914 arch/powerpc/kernel/process.c else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) val 1925 arch/powerpc/kernel/process.c unsigned int val; val 1936 arch/powerpc/kernel/process.c val = PR_ENDIAN_LITTLE; val 1938 arch/powerpc/kernel/process.c val = PR_ENDIAN_PPC_LITTLE; val 1940 arch/powerpc/kernel/process.c val = PR_ENDIAN_BIG; val 1942 arch/powerpc/kernel/process.c return put_user(val, (unsigned int __user *)adr); val 1945 arch/powerpc/kernel/process.c int set_unalign_ctl(struct task_struct *tsk, unsigned int val) val 1947 arch/powerpc/kernel/process.c tsk->thread.align_ctl = val; val 439 arch/powerpc/kernel/prom_init.c static void __init prom_print_hex(unsigned long val) val 441 arch/powerpc/kernel/prom_init.c int i, nibbles = sizeof(val)*2; val 442 arch/powerpc/kernel/prom_init.c char buf[sizeof(val)*2+1]; val 445 arch/powerpc/kernel/prom_init.c buf[i] = (val & 0xf) + '0'; val 448 arch/powerpc/kernel/prom_init.c val >>= 4; val 456 arch/powerpc/kernel/prom_init.c static void __init prom_print_dec(unsigned long val) val 462 arch/powerpc/kernel/prom_init.c buf[i] = (val % 10) + '0'; val 463 arch/powerpc/kernel/prom_init.c val = val/10; val 464 arch/powerpc/kernel/prom_init.c if (val == 0) val 802 arch/powerpc/kernel/prom_init.c bool val; val 804 arch/powerpc/kernel/prom_init.c if (prom_strtobool(++opt, &val)) val 807 arch/powerpc/kernel/prom_init.c prom_radix_disable = val; val 824 arch/powerpc/kernel/prom_init.c bool val; val 827 arch/powerpc/kernel/prom_init.c if (!prom_strtobool(opt, &val)) val 828 arch/powerpc/kernel/prom_init.c prom_svm_enable = val; val 911 arch/powerpc/kernel/prom_init.c struct { u32 mask, val; } pvrs[12]; val 938 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x003a0000), val 942 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x003e0000), val 946 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x003f0000), val 950 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x004b0000), val 954 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x004c0000), val 958 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x004d0000), val 962 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x004e0000), val 966 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x0f000005), val 970 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x0f000004), val 974 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x0f000003), val 978 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x0f000002), val 982 arch/powerpc/kernel/prom_init.c .val = cpu_to_be32(0x0f000001), val 1201 arch/powerpc/kernel/prom_init.c static void __init prom_parse_mmu_model(u8 val, val 1204 arch/powerpc/kernel/prom_init.c switch (val) { val 1227 arch/powerpc/kernel/prom_init.c prom_debug("Unknown mmu support option: 0x%x\n", val); val 1232 arch/powerpc/kernel/prom_init.c static void __init prom_parse_xive_model(u8 val, val 1235 arch/powerpc/kernel/prom_init.c switch (val) { val 1255 arch/powerpc/kernel/prom_init.c prom_debug("Unknown xive support option: 0x%x\n", val); val 1260 arch/powerpc/kernel/prom_init.c static void __init prom_parse_platform_support(u8 index, u8 val, val 1265 arch/powerpc/kernel/prom_init.c prom_parse_mmu_model(val & OV5_FEAT(OV5_MMU_SUPPORT), support); val 1268 arch/powerpc/kernel/prom_init.c if (val & OV5_FEAT(OV5_RADIX_GTSE)) { val 1274 arch/powerpc/kernel/prom_init.c prom_parse_xive_model(val & OV5_FEAT(OV5_XIVE_SUPPORT), val 1598 arch/powerpc/kernel/prom_init.c __be32 val; val 1606 arch/powerpc/kernel/prom_init.c val = cpu_to_be32(2); val 1607 arch/powerpc/kernel/prom_init.c prom_getprop(prom.root, "#address-cells", &val, sizeof(val)); val 1608 arch/powerpc/kernel/prom_init.c rac = be32_to_cpu(val); val 1609 arch/powerpc/kernel/prom_init.c val = cpu_to_be32(1); val 1610 arch/powerpc/kernel/prom_init.c prom_getprop(prom.root, "#size-cells", &val, sizeof(rsc)); val 1611 arch/powerpc/kernel/prom_init.c rsc = be32_to_cpu(val); val 1722 arch/powerpc/kernel/prom_init.c __be32 val; val 1725 arch/powerpc/kernel/prom_init.c if (prom_getprop(prom.chosen, "stdin", &val, sizeof(val)) > 0) { val 1726 arch/powerpc/kernel/prom_init.c stdin = be32_to_cpu(val); val 1748 arch/powerpc/kernel/prom_init.c __be32 val; val 1757 arch/powerpc/kernel/prom_init.c val = 0; val 1758 arch/powerpc/kernel/prom_init.c prom_getprop(rtas_node, "ibm,os-term", &val, sizeof(val)); val 1759 arch/powerpc/kernel/prom_init.c token = be32_to_cpu(val); val 1779 arch/powerpc/kernel/prom_init.c __be32 val; val 1789 arch/powerpc/kernel/prom_init.c val = 0; val 1790 arch/powerpc/kernel/prom_init.c prom_getprop(rtas_node, "rtas-size", &val, sizeof(size)); val 1791 arch/powerpc/kernel/prom_init.c size = be32_to_cpu(val); val 1818 arch/powerpc/kernel/prom_init.c val = cpu_to_be32(base); val 1820 arch/powerpc/kernel/prom_init.c &val, sizeof(val)); val 1821 arch/powerpc/kernel/prom_init.c val = cpu_to_be32(entry); val 1823 arch/powerpc/kernel/prom_init.c &val, sizeof(val)); val 1827 arch/powerpc/kernel/prom_init.c &val, sizeof(val)) != PROM_ERROR) val 1847 arch/powerpc/kernel/prom_init.c __be32 val; val 1863 arch/powerpc/kernel/prom_init.c &val, sizeof(val)) != PROM_ERROR) { val 2215 arch/powerpc/kernel/prom_init.c __be32 val; val 2217 arch/powerpc/kernel/prom_init.c if (prom_getprop(prom.chosen, "stdout", &val, sizeof(val)) <= 0) val 2220 arch/powerpc/kernel/prom_init.c prom.stdout = be32_to_cpu(val); val 2232 arch/powerpc/kernel/prom_init.c val = cpu_to_be32(stdout_node); val 3051 arch/powerpc/kernel/prom_init.c u32 interrupts[2], parent, rval, val = 0; val 3067 arch/powerpc/kernel/prom_init.c prom_setprop(iob, name, "interrupt-controller", &val, 0); val 3158 arch/powerpc/kernel/prom_init.c __be64 val; val 3163 arch/powerpc/kernel/prom_init.c val = cpu_to_be64(prom_initrd_start); val 3165 arch/powerpc/kernel/prom_init.c &val, sizeof(val)); val 3166 arch/powerpc/kernel/prom_init.c val = cpu_to_be64(prom_initrd_end); val 3168 arch/powerpc/kernel/prom_init.c &val, sizeof(val)); val 3412 arch/powerpc/kernel/prom_init.c __be64 val = cpu_to_be64(prom_memory_limit); val 3414 arch/powerpc/kernel/prom_init.c &val, sizeof(val)); val 259 arch/powerpc/kernel/rtas-proc.c static int parse_number(const char __user *p, size_t count, u64 *val) val 272 arch/powerpc/kernel/rtas-proc.c *val = simple_strtoull(buf, &end, 10); val 45 arch/powerpc/kernel/rtas_pci.c int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val) val 69 arch/powerpc/kernel/rtas_pci.c *val = returnval; val 79 arch/powerpc/kernel/rtas_pci.c int where, int size, u32 *val) val 84 arch/powerpc/kernel/rtas_pci.c *val = 0xFFFFFFFF; val 89 arch/powerpc/kernel/rtas_pci.c ret = rtas_read_config(pdn, where, size, val); val 90 arch/powerpc/kernel/rtas_pci.c if (*val == EEH_IO_ERROR_VALUE(size) && val 97 arch/powerpc/kernel/rtas_pci.c int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val) val 116 arch/powerpc/kernel/rtas_pci.c BUID_HI(buid), BUID_LO(buid), size, (ulong) val); val 118 arch/powerpc/kernel/rtas_pci.c ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val); val 129 arch/powerpc/kernel/rtas_pci.c int where, int size, u32 val) val 136 arch/powerpc/kernel/rtas_pci.c return rtas_write_config(pdn, where, size, val); val 158 arch/powerpc/kernel/rtas_pci.c volatile u32 val; val 175 arch/powerpc/kernel/rtas_pci.c val = in_be32(chip_regs + 0xf6030); val 176 arch/powerpc/kernel/rtas_pci.c if (val & PRG_CL_RESET_VALID) { val 178 arch/powerpc/kernel/rtas_pci.c val &= ~PRG_CL_RESET_VALID; val 179 arch/powerpc/kernel/rtas_pci.c out_be32(chip_regs + 0xf6030, val); val 184 arch/powerpc/kernel/rtas_pci.c val = in_be32(chip_regs + 0xf6030); val 185 arch/powerpc/kernel/rtas_pci.c printk("reg0: %x\n", val); val 74 arch/powerpc/kernel/security.c static int barrier_nospec_set(void *data, u64 val) val 76 arch/powerpc/kernel/security.c switch (val) { val 84 arch/powerpc/kernel/security.c if (!!val == !!barrier_nospec_enabled) val 87 arch/powerpc/kernel/security.c enable_barrier_nospec(!!val); val 92 arch/powerpc/kernel/security.c static int barrier_nospec_get(void *data, u64 *val) val 94 arch/powerpc/kernel/security.c *val = barrier_nospec_enabled ? 1 : 0; val 356 arch/powerpc/kernel/security.c static int stf_barrier_set(void *data, u64 val) val 360 arch/powerpc/kernel/security.c if (val == 1) val 362 arch/powerpc/kernel/security.c else if (val == 0) val 374 arch/powerpc/kernel/security.c static int stf_barrier_get(void *data, u64 *val) val 376 arch/powerpc/kernel/security.c *val = stf_barrier ? 1 : 0; val 469 arch/powerpc/kernel/security.c static int count_cache_flush_set(void *data, u64 val) val 473 arch/powerpc/kernel/security.c if (val == 1) val 475 arch/powerpc/kernel/security.c else if (val == 0) val 485 arch/powerpc/kernel/security.c static int count_cache_flush_get(void *data, u64 *val) val 488 arch/powerpc/kernel/security.c *val = 0; val 490 arch/powerpc/kernel/security.c *val = 1; val 103 arch/powerpc/kernel/setup_32.c unsigned long val = simple_strtoul(str, NULL, 0); val 104 arch/powerpc/kernel/setup_32.c printk(KERN_INFO "l2cr set to %lx\n", val); val 106 arch/powerpc/kernel/setup_32.c _set_L2CR(val); /* and enable it */ val 116 arch/powerpc/kernel/setup_32.c unsigned long val = simple_strtoul(str, NULL, 0); val 117 arch/powerpc/kernel/setup_32.c printk(KERN_INFO "l3cr set to %lx\n", val); val 118 arch/powerpc/kernel/setup_32.c _set_L3CR(val); /* and enable it */ val 966 arch/powerpc/kernel/setup_64.c static int rfi_flush_set(void *data, u64 val) val 970 arch/powerpc/kernel/setup_64.c if (val == 1) val 972 arch/powerpc/kernel/setup_64.c else if (val == 0) val 984 arch/powerpc/kernel/setup_64.c static int rfi_flush_get(void *data, u64 *val) val 986 arch/powerpc/kernel/setup_64.c *val = rfi_flush ? 1 : 0; val 111 arch/powerpc/kernel/sysfs.c static void do_show_pwrmgtcr0(void *val) val 113 arch/powerpc/kernel/sysfs.c u32 *value = val; val 131 arch/powerpc/kernel/sysfs.c static void do_store_pw20_state(void *val) val 133 arch/powerpc/kernel/sysfs.c u32 *value = val; val 196 arch/powerpc/kernel/sysfs.c static void set_pw20_wait_entry_bit(void *val) val 198 arch/powerpc/kernel/sysfs.c u32 *value = val; val 253 arch/powerpc/kernel/sysfs.c static void do_store_altivec_idle(void *val) val 255 arch/powerpc/kernel/sysfs.c u32 *value = val; val 318 arch/powerpc/kernel/sysfs.c static void set_altivec_idle_wait_entry_bit(void *val) val 320 arch/powerpc/kernel/sysfs.c u32 *value = val; val 411 arch/powerpc/kernel/sysfs.c static void read_##NAME(void *val) \ val 413 arch/powerpc/kernel/sysfs.c *(unsigned long *)val = mfspr(ADDRESS); \ val 415 arch/powerpc/kernel/sysfs.c static void write_##NAME(void *val) \ val 418 arch/powerpc/kernel/sysfs.c mtspr(ADDRESS, *(unsigned long *)val); \ val 427 arch/powerpc/kernel/sysfs.c unsigned long val; \ val 428 arch/powerpc/kernel/sysfs.c smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \ val 429 arch/powerpc/kernel/sysfs.c return sprintf(buf, "%lx\n", val); \ val 436 arch/powerpc/kernel/sysfs.c unsigned long val; \ val 437 arch/powerpc/kernel/sysfs.c int ret = sscanf(buf, "%lx", &val); \ val 440 arch/powerpc/kernel/sysfs.c smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \ val 519 arch/powerpc/kernel/sysfs.c static void read_dscr(void *val) val 521 arch/powerpc/kernel/sysfs.c *(unsigned long *)val = get_paca()->dscr_default; val 532 arch/powerpc/kernel/sysfs.c static void write_dscr(void *val) val 534 arch/powerpc/kernel/sysfs.c get_paca()->dscr_default = *(unsigned long *)val; val 536 arch/powerpc/kernel/sysfs.c current->thread.dscr = *(unsigned long *)val; val 537 arch/powerpc/kernel/sysfs.c mtspr(SPRN_DSCR, *(unsigned long *)val); val 576 arch/powerpc/kernel/sysfs.c unsigned long val; val 579 arch/powerpc/kernel/sysfs.c ret = sscanf(buf, "%lx", &val); val 582 arch/powerpc/kernel/sysfs.c dscr_default = val; val 584 arch/powerpc/kernel/sysfs.c on_each_cpu(write_dscr, &val, 1); val 743 arch/powerpc/kernel/time.c static int __init get_freq(char *name, int cells, unsigned long *val) val 756 arch/powerpc/kernel/time.c *val = of_read_ulong(fp, cells); val 1233 arch/powerpc/kernel/traps.c u8 val; val 1243 arch/powerpc/kernel/traps.c if (get_user(val, (u8 __user *)EA)) val 1249 arch/powerpc/kernel/traps.c regs->gpr[rT] |= val << shift; val 1253 arch/powerpc/kernel/traps.c val = regs->gpr[rT] >> shift; val 1254 arch/powerpc/kernel/traps.c if (put_user(val, (u8 __user *)EA)) val 2291 arch/powerpc/kernel/traps.c (u32 *)&entries[i].val.counter); val 217 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_maple(unsigned int reg, u8 val) val 219 arch/powerpc/kernel/udbg_16550.c real_writeb(val, UDBG_UART_MAPLE_ADDR + reg); val 240 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_pas(unsigned int reg, u8 val) val 242 arch/powerpc/kernel/udbg_16550.c real_205_writeb(val, UDBG_UART_PAS_ADDR + reg); val 263 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_44x_as1(unsigned int reg, u8 val) val 265 arch/powerpc/kernel/udbg_16550.c as1_writeb(val, (void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg); val 285 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_40x(unsigned int reg, u8 val) val 287 arch/powerpc/kernel/udbg_16550.c real_writeb(val, (void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR val 122 arch/powerpc/kernel/uprobes.c unsigned long val, void *data) val 135 arch/powerpc/kernel/uprobes.c switch (val) { val 673 arch/powerpc/kernel/vdso.c unsigned long cpu, node, val; val 685 arch/powerpc/kernel/vdso.c val = (cpu & 0xfff) | ((node & 0xffff) << 16); val 686 arch/powerpc/kernel/vdso.c mtspr(SPRN_SPRG_VDSO_WRITE, val); val 687 arch/powerpc/kernel/vdso.c get_paca()->sprg_vdso = val; val 603 arch/powerpc/kvm/book3s.c union kvmppc_one_reg *val) val 608 arch/powerpc/kvm/book3s.c r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val); val 613 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, kvmppc_get_dar(vcpu)); val 616 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, kvmppc_get_dsisr(vcpu)); val 620 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, VCPU_FPR(vcpu, i)); val 623 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, vcpu->arch.fp.fpscr); val 629 arch/powerpc/kvm/book3s.c val->vsxval[0] = vcpu->arch.fp.fpr[i][0]; val 630 arch/powerpc/kvm/book3s.c val->vsxval[1] = vcpu->arch.fp.fpr[i][1]; val 637 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, INS_TW); val 646 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, kvmppc_xive_get_icp(vcpu)); val 648 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, kvmppc_xics_get_icp(vcpu)); val 658 arch/powerpc/kvm/book3s.c r = kvmppc_xive_native_get_vp(vcpu, val); val 664 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, vcpu->arch.fscr); val 667 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, vcpu->arch.tar); val 670 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, vcpu->arch.ebbhr); val 673 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, vcpu->arch.ebbrr); val 676 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, vcpu->arch.bescr); val 679 arch/powerpc/kvm/book3s.c *val = get_reg_val(id, vcpu->arch.ic); val 691 arch/powerpc/kvm/book3s.c union kvmppc_one_reg *val) val 696 arch/powerpc/kvm/book3s.c r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val); val 701 arch/powerpc/kvm/book3s.c kvmppc_set_dar(vcpu, set_reg_val(id, *val)); val 704 arch/powerpc/kvm/book3s.c kvmppc_set_dsisr(vcpu, set_reg_val(id, *val)); val 708 arch/powerpc/kvm/book3s.c VCPU_FPR(vcpu, i) = set_reg_val(id, *val); val 711 arch/powerpc/kvm/book3s.c vcpu->arch.fp.fpscr = set_reg_val(id, *val); val 717 arch/powerpc/kvm/book3s.c vcpu->arch.fp.fpr[i][0] = val->vsxval[0]; val 718 arch/powerpc/kvm/book3s.c vcpu->arch.fp.fpr[i][1] = val->vsxval[1]; val 731 arch/powerpc/kvm/book3s.c r = kvmppc_xive_set_icp(vcpu, set_reg_val(id, *val)); val 733 arch/powerpc/kvm/book3s.c r = kvmppc_xics_set_icp(vcpu, set_reg_val(id, *val)); val 743 arch/powerpc/kvm/book3s.c r = kvmppc_xive_native_set_vp(vcpu, val); val 749 arch/powerpc/kvm/book3s.c vcpu->arch.fscr = set_reg_val(id, *val); val 752 arch/powerpc/kvm/book3s.c vcpu->arch.tar = set_reg_val(id, *val); val 755 arch/powerpc/kvm/book3s.c vcpu->arch.ebbhr = set_reg_val(id, *val); val 758 arch/powerpc/kvm/book3s.c vcpu->arch.ebbrr = set_reg_val(id, *val); val 761 arch/powerpc/kvm/book3s.c vcpu->arch.bescr = set_reg_val(id, *val); val 764 arch/powerpc/kvm/book3s.c vcpu->arch.ic = set_reg_val(id, *val); val 975 arch/powerpc/kvm/book3s.c unsigned long val = kvmppc_get_gpr(vcpu, 6); val 982 arch/powerpc/kvm/book3s.c *(u8 *)&buf = val; val 986 arch/powerpc/kvm/book3s.c *(__be16 *)&buf = cpu_to_be16(val); val 990 arch/powerpc/kvm/book3s.c *(__be32 *)&buf = cpu_to_be32(val); val 994 arch/powerpc/kvm/book3s.c *(__be64 *)&buf = cpu_to_be64(val); val 638 arch/powerpc/kvm/book3s_emulate.c u32 val) val 642 arch/powerpc/kvm/book3s_emulate.c u32 bl = (val >> 2) & 0x7ff; val 644 arch/powerpc/kvm/book3s_emulate.c bat->bepi = val & 0xfffe0000; val 645 arch/powerpc/kvm/book3s_emulate.c bat->vs = (val & 2) ? 1 : 0; val 646 arch/powerpc/kvm/book3s_emulate.c bat->vp = (val & 1) ? 1 : 0; val 647 arch/powerpc/kvm/book3s_emulate.c bat->raw = (bat->raw & 0xffffffff00000000ULL) | val; val 650 arch/powerpc/kvm/book3s_emulate.c bat->brpn = val & 0xfffe0000; val 651 arch/powerpc/kvm/book3s_emulate.c bat->wimg = (val >> 3) & 0xf; val 652 arch/powerpc/kvm/book3s_emulate.c bat->pp = val & 3; val 653 arch/powerpc/kvm/book3s_emulate.c bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32); val 1623 arch/powerpc/kvm/book3s_hv.c union kvmppc_one_reg *val) val 1630 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); val 1633 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, 0); val 1636 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.dabr); val 1639 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.dabrx); val 1642 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.dscr); val 1645 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.purr); val 1648 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.spurr); val 1651 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.amr); val 1654 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.uamor); val 1658 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.mmcr[i]); val 1662 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.pmc[i]); val 1666 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.spmc[i]); val 1669 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.siar); val 1672 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.sdar); val 1675 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.sier); val 1678 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.iamr); val 1681 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.pspb); val 1690 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.vcore->dpdes | val 1694 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.vcore->vtb); val 1697 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.dawr); val 1700 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.dawrx); val 1703 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.ciabr); val 1706 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.csigr); val 1709 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.tacr); val 1712 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.tcscr); val 1715 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.pid); val 1718 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.acop); val 1721 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.wort); val 1724 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.tid); val 1727 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.psscr); val 1731 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.vpa.next_gpa); val 1736 arch/powerpc/kvm/book3s_hv.c val->vpaval.addr = vcpu->arch.slb_shadow.next_gpa; val 1737 arch/powerpc/kvm/book3s_hv.c val->vpaval.length = vcpu->arch.slb_shadow.len; val 1742 arch/powerpc/kvm/book3s_hv.c val->vpaval.addr = vcpu->arch.dtl.next_gpa; val 1743 arch/powerpc/kvm/book3s_hv.c val->vpaval.length = vcpu->arch.dtl.len; val 1747 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.vcore->tb_offset); val 1751 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.vcore->lpcr); val 1754 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.ppr); val 1758 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.tfhar); val 1761 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.tfiar); val 1764 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.texasr); val 1768 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.gpr_tm[i]); val 1776 arch/powerpc/kvm/book3s_hv.c val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j]; val 1779 arch/powerpc/kvm/book3s_hv.c val->vval = vcpu->arch.vr_tm.vr[i-32]; val 1786 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.cr_tm); val 1789 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.xer_tm); val 1792 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.lr_tm); val 1795 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.ctr_tm); val 1798 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr); val 1801 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.amr_tm); val 1804 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.ppr_tm); val 1807 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.vrsave_tm); val 1811 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); val 1816 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.dscr_tm); val 1819 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.tar_tm); val 1823 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.vcore->arch_compat); val 1826 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.dec_expires + val 1830 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->arch.online); val 1833 arch/powerpc/kvm/book3s_hv.c *val = get_reg_val(id, vcpu->kvm->arch.l1_ptcr); val 1844 arch/powerpc/kvm/book3s_hv.c union kvmppc_one_reg *val) val 1853 arch/powerpc/kvm/book3s_hv.c if (set_reg_val(id, *val)) val 1857 arch/powerpc/kvm/book3s_hv.c vcpu->arch.dabr = set_reg_val(id, *val); val 1860 arch/powerpc/kvm/book3s_hv.c vcpu->arch.dabrx = set_reg_val(id, *val) & ~DABRX_HYP; val 1863 arch/powerpc/kvm/book3s_hv.c vcpu->arch.dscr = set_reg_val(id, *val); val 1866 arch/powerpc/kvm/book3s_hv.c vcpu->arch.purr = set_reg_val(id, *val); val 1869 arch/powerpc/kvm/book3s_hv.c vcpu->arch.spurr = set_reg_val(id, *val); val 1872 arch/powerpc/kvm/book3s_hv.c vcpu->arch.amr = set_reg_val(id, *val); val 1875 arch/powerpc/kvm/book3s_hv.c vcpu->arch.uamor = set_reg_val(id, *val); val 1879 arch/powerpc/kvm/book3s_hv.c vcpu->arch.mmcr[i] = set_reg_val(id, *val); val 1883 arch/powerpc/kvm/book3s_hv.c vcpu->arch.pmc[i] = set_reg_val(id, *val); val 1887 arch/powerpc/kvm/book3s_hv.c vcpu->arch.spmc[i] = set_reg_val(id, *val); val 1890 arch/powerpc/kvm/book3s_hv.c vcpu->arch.siar = set_reg_val(id, *val); val 1893 arch/powerpc/kvm/book3s_hv.c vcpu->arch.sdar = set_reg_val(id, *val); val 1896 arch/powerpc/kvm/book3s_hv.c vcpu->arch.sier = set_reg_val(id, *val); val 1899 arch/powerpc/kvm/book3s_hv.c vcpu->arch.iamr = set_reg_val(id, *val); val 1902 arch/powerpc/kvm/book3s_hv.c vcpu->arch.pspb = set_reg_val(id, *val); val 1905 arch/powerpc/kvm/book3s_hv.c vcpu->arch.vcore->dpdes = set_reg_val(id, *val); val 1908 arch/powerpc/kvm/book3s_hv.c vcpu->arch.vcore->vtb = set_reg_val(id, *val); val 1911 arch/powerpc/kvm/book3s_hv.c vcpu->arch.dawr = set_reg_val(id, *val); val 1914 arch/powerpc/kvm/book3s_hv.c vcpu->arch.dawrx = set_reg_val(id, *val) & ~DAWRX_HYP; val 1917 arch/powerpc/kvm/book3s_hv.c vcpu->arch.ciabr = set_reg_val(id, *val); val 1923 arch/powerpc/kvm/book3s_hv.c vcpu->arch.csigr = set_reg_val(id, *val); val 1926 arch/powerpc/kvm/book3s_hv.c vcpu->arch.tacr = set_reg_val(id, *val); val 1929 arch/powerpc/kvm/book3s_hv.c vcpu->arch.tcscr = set_reg_val(id, *val); val 1932 arch/powerpc/kvm/book3s_hv.c vcpu->arch.pid = set_reg_val(id, *val); val 1935 arch/powerpc/kvm/book3s_hv.c vcpu->arch.acop = set_reg_val(id, *val); val 1938 arch/powerpc/kvm/book3s_hv.c vcpu->arch.wort = set_reg_val(id, *val); val 1941 arch/powerpc/kvm/book3s_hv.c vcpu->arch.tid = set_reg_val(id, *val); val 1944 arch/powerpc/kvm/book3s_hv.c vcpu->arch.psscr = set_reg_val(id, *val) & PSSCR_GUEST_VIS; val 1947 arch/powerpc/kvm/book3s_hv.c addr = set_reg_val(id, *val); val 1955 arch/powerpc/kvm/book3s_hv.c addr = val->vpaval.addr; val 1956 arch/powerpc/kvm/book3s_hv.c len = val->vpaval.length; val 1963 arch/powerpc/kvm/book3s_hv.c addr = val->vpaval.addr; val 1964 arch/powerpc/kvm/book3s_hv.c len = val->vpaval.length; val 1975 arch/powerpc/kvm/book3s_hv.c ALIGN(set_reg_val(id, *val), 1UL << 24); val 1978 arch/powerpc/kvm/book3s_hv.c kvmppc_set_lpcr(vcpu, set_reg_val(id, *val), true); val 1981 arch/powerpc/kvm/book3s_hv.c kvmppc_set_lpcr(vcpu, set_reg_val(id, *val), false); val 1984 arch/powerpc/kvm/book3s_hv.c vcpu->arch.ppr = set_reg_val(id, *val); val 1988 arch/powerpc/kvm/book3s_hv.c vcpu->arch.tfhar = set_reg_val(id, *val); val 1991 arch/powerpc/kvm/book3s_hv.c vcpu->arch.tfiar = set_reg_val(id, *val); val 1994 arch/powerpc/kvm/book3s_hv.c vcpu->arch.texasr = set_reg_val(id, *val); val 1998 arch/powerpc/kvm/book3s_hv.c vcpu->arch.gpr_tm[i] = set_reg_val(id, *val); val 2006 arch/powerpc/kvm/book3s_hv.c vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j]; val 2009 arch/powerpc/kvm/book3s_hv.c vcpu->arch.vr_tm.vr[i-32] = val->vval; val 2015 arch/powerpc/kvm/book3s_hv.c vcpu->arch.cr_tm = set_reg_val(id, *val); val 2018 arch/powerpc/kvm/book3s_hv.c vcpu->arch.xer_tm = set_reg_val(id, *val); val 2021 arch/powerpc/kvm/book3s_hv.c vcpu->arch.lr_tm = set_reg_val(id, *val); val 2024 arch/powerpc/kvm/book3s_hv.c vcpu->arch.ctr_tm = set_reg_val(id, *val); val 2027 arch/powerpc/kvm/book3s_hv.c vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val); val 2030 arch/powerpc/kvm/book3s_hv.c vcpu->arch.amr_tm = set_reg_val(id, *val); val 2033 arch/powerpc/kvm/book3s_hv.c vcpu->arch.ppr_tm = set_reg_val(id, *val); val 2036 arch/powerpc/kvm/book3s_hv.c vcpu->arch.vrsave_tm = set_reg_val(id, *val); val 2040 arch/powerpc/kvm/book3s_hv.c vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val); val 2045 arch/powerpc/kvm/book3s_hv.c vcpu->arch.dscr_tm = set_reg_val(id, *val); val 2048 arch/powerpc/kvm/book3s_hv.c vcpu->arch.tar_tm = set_reg_val(id, *val); val 2052 arch/powerpc/kvm/book3s_hv.c r = kvmppc_set_arch_compat(vcpu, set_reg_val(id, *val)); val 2055 arch/powerpc/kvm/book3s_hv.c vcpu->arch.dec_expires = set_reg_val(id, *val) - val 2059 arch/powerpc/kvm/book3s_hv.c i = set_reg_val(id, *val); val 2067 arch/powerpc/kvm/book3s_hv.c vcpu->kvm->arch.l1_ptcr = set_reg_val(id, *val); val 1124 arch/powerpc/kvm/book3s_hv_rm_mmu.c unsigned long mask, val; val 1129 arch/powerpc/kvm/book3s_hv_rm_mmu.c val = 0; val 1133 arch/powerpc/kvm/book3s_hv_rm_mmu.c val |= HPTE_V_LARGE; val 1152 arch/powerpc/kvm/book3s_hv_rm_mmu.c val |= avpn; val 1164 arch/powerpc/kvm/book3s_hv_rm_mmu.c if (!(v & valid) || (v & mask) != val) val 1180 arch/powerpc/kvm/book3s_hv_rm_mmu.c if ((v & valid) && (v & mask) == val && val 1188 arch/powerpc/kvm/book3s_hv_rm_mmu.c if (val & HPTE_V_SECONDARY) val 1190 arch/powerpc/kvm/book3s_hv_rm_mmu.c val |= HPTE_V_SECONDARY; val 222 arch/powerpc/kvm/book3s_paired_singles.c u64 val; val 228 arch/powerpc/kvm/book3s_paired_singles.c val = *((u32*)tmp); val 233 arch/powerpc/kvm/book3s_paired_singles.c val = VCPU_FPR(vcpu, rs) & 0xffffffff; val 238 arch/powerpc/kvm/book3s_paired_singles.c val = VCPU_FPR(vcpu, rs); val 242 arch/powerpc/kvm/book3s_paired_singles.c val = 0; val 251 arch/powerpc/kvm/book3s_paired_singles.c emulated = kvmppc_handle_store(run, vcpu, val, len, 1); val 257 arch/powerpc/kvm/book3s_paired_singles.c val, addr, len); val 323 arch/powerpc/kvm/book3s_paired_singles.c u64 val = ((u64)tmp[0] << 32) | tmp[1]; val 324 arch/powerpc/kvm/book3s_paired_singles.c emulated = kvmppc_handle_store(run, vcpu, val, 8, 1); val 1513 arch/powerpc/kvm/book3s_pr.c union kvmppc_one_reg *val) val 1519 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); val 1522 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, to_book3s(vcpu)->hior); val 1525 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, to_book3s(vcpu)->vtb); val 1533 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, LPCR_ILE); val 1535 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, 0); val 1539 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.tfhar); val 1542 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.tfiar); val 1545 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.texasr); val 1548 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, val 1558 arch/powerpc/kvm/book3s_pr.c val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j]; val 1561 arch/powerpc/kvm/book3s_pr.c val->vval = vcpu->arch.vr_tm.vr[i-32]; val 1568 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.cr_tm); val 1571 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.xer_tm); val 1574 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.lr_tm); val 1577 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.ctr_tm); val 1580 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr); val 1583 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.amr_tm); val 1586 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.ppr_tm); val 1589 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.vrsave_tm); val 1593 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); val 1598 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.dscr_tm); val 1601 arch/powerpc/kvm/book3s_pr.c *val = get_reg_val(id, vcpu->arch.tar_tm); val 1621 arch/powerpc/kvm/book3s_pr.c union kvmppc_one_reg *val) val 1627 arch/powerpc/kvm/book3s_pr.c to_book3s(vcpu)->hior = set_reg_val(id, *val); val 1631 arch/powerpc/kvm/book3s_pr.c to_book3s(vcpu)->vtb = set_reg_val(id, *val); val 1635 arch/powerpc/kvm/book3s_pr.c kvmppc_set_lpcr_pr(vcpu, set_reg_val(id, *val)); val 1639 arch/powerpc/kvm/book3s_pr.c vcpu->arch.tfhar = set_reg_val(id, *val); val 1642 arch/powerpc/kvm/book3s_pr.c vcpu->arch.tfiar = set_reg_val(id, *val); val 1645 arch/powerpc/kvm/book3s_pr.c vcpu->arch.texasr = set_reg_val(id, *val); val 1649 arch/powerpc/kvm/book3s_pr.c set_reg_val(id, *val); val 1658 arch/powerpc/kvm/book3s_pr.c vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j]; val 1661 arch/powerpc/kvm/book3s_pr.c vcpu->arch.vr_tm.vr[i-32] = val->vval; val 1667 arch/powerpc/kvm/book3s_pr.c vcpu->arch.cr_tm = set_reg_val(id, *val); val 1670 arch/powerpc/kvm/book3s_pr.c vcpu->arch.xer_tm = set_reg_val(id, *val); val 1673 arch/powerpc/kvm/book3s_pr.c vcpu->arch.lr_tm = set_reg_val(id, *val); val 1676 arch/powerpc/kvm/book3s_pr.c vcpu->arch.ctr_tm = set_reg_val(id, *val); val 1679 arch/powerpc/kvm/book3s_pr.c vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val); val 1682 arch/powerpc/kvm/book3s_pr.c vcpu->arch.amr_tm = set_reg_val(id, *val); val 1685 arch/powerpc/kvm/book3s_pr.c vcpu->arch.ppr_tm = set_reg_val(id, *val); val 1688 arch/powerpc/kvm/book3s_pr.c vcpu->arch.vrsave_tm = set_reg_val(id, *val); val 1692 arch/powerpc/kvm/book3s_pr.c vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val); val 1697 arch/powerpc/kvm/book3s_pr.c vcpu->arch.dscr_tm = set_reg_val(id, *val); val 1700 arch/powerpc/kvm/book3s_pr.c vcpu->arch.tar_tm = set_reg_val(id, *val); val 1192 arch/powerpc/kvm/book3s_xics.c u64 val, prio; val 1204 arch/powerpc/kvm/book3s_xics.c val = irqp->server; val 1207 arch/powerpc/kvm/book3s_xics.c val |= KVM_XICS_MASKED; val 1210 arch/powerpc/kvm/book3s_xics.c val |= prio << KVM_XICS_PRIORITY_SHIFT; val 1212 arch/powerpc/kvm/book3s_xics.c val |= KVM_XICS_LEVEL_SENSITIVE; val 1214 arch/powerpc/kvm/book3s_xics.c val |= KVM_XICS_PENDING; val 1216 arch/powerpc/kvm/book3s_xics.c val |= KVM_XICS_PENDING; val 1219 arch/powerpc/kvm/book3s_xics.c val |= KVM_XICS_PRESENTED; val 1222 arch/powerpc/kvm/book3s_xics.c val |= KVM_XICS_QUEUED; val 1229 arch/powerpc/kvm/book3s_xics.c if (!ret && put_user(val, ubufp)) val 1241 arch/powerpc/kvm/book3s_xics.c u64 val; val 1256 arch/powerpc/kvm/book3s_xics.c if (get_user(val, ubufp)) val 1259 arch/powerpc/kvm/book3s_xics.c server = val & KVM_XICS_DESTINATION_MASK; val 1260 arch/powerpc/kvm/book3s_xics.c prio = val >> KVM_XICS_PRIORITY_SHIFT; val 1269 arch/powerpc/kvm/book3s_xics.c if (val & KVM_XICS_MASKED) val 1276 arch/powerpc/kvm/book3s_xics.c if (val & KVM_XICS_LEVEL_SENSITIVE) val 1279 arch/powerpc/kvm/book3s_xics.c if (val & KVM_XICS_PRESENTED || val & KVM_XICS_PENDING) val 1281 arch/powerpc/kvm/book3s_xics.c if (val & KVM_XICS_QUEUED) val 1287 arch/powerpc/kvm/book3s_xics.c if (val & KVM_XICS_PENDING) val 398 arch/powerpc/kvm/book3s_xive.c u64 val; val 443 arch/powerpc/kvm/book3s_xive.c val = xive_vm_esb_load(xd, XIVE_ESB_SET_PQ_10); val 444 arch/powerpc/kvm/book3s_xive.c state->old_p = !!(val & 2); val 445 arch/powerpc/kvm/book3s_xive.c state->old_q = !!(val & 1); val 1499 arch/powerpc/kvm/book3s_xive.c u64 val, prio; val 1534 arch/powerpc/kvm/book3s_xive.c val = state->act_server; val 1538 arch/powerpc/kvm/book3s_xive.c val |= KVM_XICS_MASKED; val 1541 arch/powerpc/kvm/book3s_xive.c val |= prio << KVM_XICS_PRIORITY_SHIFT; val 1543 arch/powerpc/kvm/book3s_xive.c val |= KVM_XICS_LEVEL_SENSITIVE; val 1545 arch/powerpc/kvm/book3s_xive.c val |= KVM_XICS_PENDING; val 1548 arch/powerpc/kvm/book3s_xive.c val |= KVM_XICS_PRESENTED; val 1551 arch/powerpc/kvm/book3s_xive.c val |= KVM_XICS_QUEUED; val 1560 arch/powerpc/kvm/book3s_xive.c val |= KVM_XICS_PENDING; val 1571 arch/powerpc/kvm/book3s_xive.c if (put_user(val, ubufp)) val 1643 arch/powerpc/kvm/book3s_xive.c u64 val; val 1666 arch/powerpc/kvm/book3s_xive.c if (get_user(val, ubufp)) { val 1671 arch/powerpc/kvm/book3s_xive.c server = val & KVM_XICS_DESTINATION_MASK; val 1672 arch/powerpc/kvm/book3s_xive.c guest_prio = val >> KVM_XICS_PRIORITY_SHIFT; val 1675 arch/powerpc/kvm/book3s_xive.c val, server, guest_prio); val 1742 arch/powerpc/kvm/book3s_xive.c val |= KVM_XICS_PENDING; val 1753 arch/powerpc/kvm/book3s_xive.c if (val & KVM_XICS_LEVEL_SENSITIVE) { val 1755 arch/powerpc/kvm/book3s_xive.c if (val & KVM_XICS_PENDING) val 1770 arch/powerpc/kvm/book3s_xive.c if (val & KVM_XICS_PRESENTED && !(val & KVM_XICS_PENDING)) val 1772 arch/powerpc/kvm/book3s_xive.c if (val & KVM_XICS_QUEUED || val & KVM_XICS_PENDING) val 1782 arch/powerpc/kvm/book3s_xive.c if (val & KVM_XICS_MASKED) { val 32 arch/powerpc/kvm/book3s_xive_native.c u64 val; val 37 arch/powerpc/kvm/book3s_xive_native.c val = in_be64(xd->eoi_mmio + offset); val 38 arch/powerpc/kvm/book3s_xive_native.c return (u8)val; val 337 arch/powerpc/kvm/book3s_xive_native.c u64 val; val 357 arch/powerpc/kvm/book3s_xive_native.c if (get_user(val, ubufp)) { val 382 arch/powerpc/kvm/book3s_xive_native.c if (val & KVM_XIVE_LEVEL_SENSITIVE) { val 384 arch/powerpc/kvm/book3s_xive_native.c if (val & KVM_XIVE_LEVEL_ASSERTED) val 1128 arch/powerpc/kvm/book3s_xive_native.c int kvmppc_xive_native_get_vp(struct kvm_vcpu *vcpu, union kvmppc_one_reg *val) val 1141 arch/powerpc/kvm/book3s_xive_native.c val->xive_timaval[0] = vcpu->arch.xive_saved_state.w01; val 1152 arch/powerpc/kvm/book3s_xive_native.c val->xive_timaval[0] |= cpu_to_be64(opal_state & TM_IPB_MASK); val 1166 arch/powerpc/kvm/book3s_xive_native.c int kvmppc_xive_native_set_vp(struct kvm_vcpu *vcpu, union kvmppc_one_reg *val) val 1172 arch/powerpc/kvm/book3s_xive_native.c val->xive_timaval[0], val->xive_timaval[1]); val 1188 arch/powerpc/kvm/book3s_xive_native.c vcpu->arch.xive_saved_state.w01 = val->xive_timaval[0]; val 59 arch/powerpc/kvm/book3s_xive_template.c u64 val; val 64 arch/powerpc/kvm/book3s_xive_template.c val =__x_readq(__x_eoi_page(xd) + offset); val 66 arch/powerpc/kvm/book3s_xive_template.c val >>= 64-8; val 68 arch/powerpc/kvm/book3s_xive_template.c return (u8)val; val 1654 arch/powerpc/kvm/booke.c union kvmppc_one_reg *val) val 1660 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.dbg_reg.iac1); val 1663 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.dbg_reg.iac2); val 1667 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.dbg_reg.iac3); val 1670 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.dbg_reg.iac4); val 1674 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.dbg_reg.dac1); val 1677 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.dbg_reg.dac2); val 1681 arch/powerpc/kvm/booke.c *val = get_reg_val(id, epr); val 1686 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.epcr); val 1690 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.tcr); val 1693 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.tsr); val 1696 arch/powerpc/kvm/booke.c *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); val 1699 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.vrsave); val 1702 arch/powerpc/kvm/booke.c r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val); val 1710 arch/powerpc/kvm/booke.c union kvmppc_one_reg *val) val 1716 arch/powerpc/kvm/booke.c vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val); val 1719 arch/powerpc/kvm/booke.c vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val); val 1723 arch/powerpc/kvm/booke.c vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val); val 1726 arch/powerpc/kvm/booke.c vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val); val 1730 arch/powerpc/kvm/booke.c vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val); val 1733 arch/powerpc/kvm/booke.c vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val); val 1736 arch/powerpc/kvm/booke.c u32 new_epr = set_reg_val(id, *val); val 1742 arch/powerpc/kvm/booke.c u32 new_epcr = set_reg_val(id, *val); val 1748 arch/powerpc/kvm/booke.c u32 tsr_bits = set_reg_val(id, *val); val 1753 arch/powerpc/kvm/booke.c u32 tsr_bits = set_reg_val(id, *val); val 1758 arch/powerpc/kvm/booke.c u32 tsr = set_reg_val(id, *val); val 1763 arch/powerpc/kvm/booke.c u32 tcr = set_reg_val(id, *val); val 1768 arch/powerpc/kvm/booke.c vcpu->arch.vrsave = set_reg_val(id, *val); val 1771 arch/powerpc/kvm/booke.c r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val); val 28 arch/powerpc/kvm/e500.c unsigned long val; val 78 arch/powerpc/kvm/e500.c entry->val = sid; val 106 arch/powerpc/kvm/e500.c if (entry && entry->val != 0 && val 107 arch/powerpc/kvm/e500.c __this_cpu_read(pcpu_sids.entry[entry->val]) == entry && val 108 arch/powerpc/kvm/e500.c entry->pentry == this_cpu_ptr(&pcpu_sids.entry[entry->val])) val 109 arch/powerpc/kvm/e500.c return entry->val; val 169 arch/powerpc/kvm/e500.c idt->id[as][pid][pr].val = 0; val 238 arch/powerpc/kvm/e500.c u32 val, eaddr; val 269 arch/powerpc/kvm/e500.c val = (pid << MAS6_SPID_SHIFT) | MAS6_SAS; val 274 arch/powerpc/kvm/e500.c mtspr(SPRN_MAS6, val); val 276 arch/powerpc/kvm/e500.c val = mfspr(SPRN_MAS1); val 277 arch/powerpc/kvm/e500.c if (val & MAS1_VALID) { val 278 arch/powerpc/kvm/e500.c mtspr(SPRN_MAS1, val & ~MAS1_VALID); val 423 arch/powerpc/kvm/e500.c union kvmppc_one_reg *val) val 425 arch/powerpc/kvm/e500.c int r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val); val 430 arch/powerpc/kvm/e500.c union kvmppc_one_reg *val) val 432 arch/powerpc/kvm/e500.c int r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val); val 139 arch/powerpc/kvm/e500.h union kvmppc_one_reg *val); val 141 arch/powerpc/kvm/e500.h union kvmppc_one_reg *val); val 602 arch/powerpc/kvm/e500_mmu.c union kvmppc_one_reg *val) val 609 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.shared->mas0); val 612 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.shared->mas1); val 615 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.shared->mas2); val 618 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.shared->mas7_3); val 621 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.shared->mas4); val 624 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.shared->mas6); val 627 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.mmucfg); val 630 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.eptcfg); val 637 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.tlbcfg[i]); val 644 arch/powerpc/kvm/e500_mmu.c *val = get_reg_val(id, vcpu->arch.tlbps[i]); val 655 arch/powerpc/kvm/e500_mmu.c union kvmppc_one_reg *val) val 662 arch/powerpc/kvm/e500_mmu.c vcpu->arch.shared->mas0 = set_reg_val(id, *val); val 665 arch/powerpc/kvm/e500_mmu.c vcpu->arch.shared->mas1 = set_reg_val(id, *val); val 668 arch/powerpc/kvm/e500_mmu.c vcpu->arch.shared->mas2 = set_reg_val(id, *val); val 671 arch/powerpc/kvm/e500_mmu.c vcpu->arch.shared->mas7_3 = set_reg_val(id, *val); val 674 arch/powerpc/kvm/e500_mmu.c vcpu->arch.shared->mas4 = set_reg_val(id, *val); val 677 arch/powerpc/kvm/e500_mmu.c vcpu->arch.shared->mas6 = set_reg_val(id, *val); val 681 arch/powerpc/kvm/e500_mmu.c u32 reg = set_reg_val(id, *val); val 687 arch/powerpc/kvm/e500_mmu.c u32 reg = set_reg_val(id, *val); val 697 arch/powerpc/kvm/e500_mmu.c u32 reg = set_reg_val(id, *val); val 707 arch/powerpc/kvm/e500_mmu.c u32 reg = set_reg_val(id, *val); val 60 arch/powerpc/kvm/e500mc.c u32 val; val 67 arch/powerpc/kvm/e500mc.c val = (tid << 16) | ts; val 72 arch/powerpc/kvm/e500mc.c mtspr(SPRN_MAS6, val); val 76 arch/powerpc/kvm/e500mc.c val = mfspr(SPRN_MAS1); val 77 arch/powerpc/kvm/e500mc.c if (val & MAS1_VALID) { val 78 arch/powerpc/kvm/e500mc.c mtspr(SPRN_MAS1, val & ~MAS1_VALID); val 273 arch/powerpc/kvm/e500mc.c union kvmppc_one_reg *val) val 279 arch/powerpc/kvm/e500mc.c *val = get_reg_val(id, vcpu->arch.sprg9); val 282 arch/powerpc/kvm/e500mc.c r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val); val 289 arch/powerpc/kvm/e500mc.c union kvmppc_one_reg *val) val 295 arch/powerpc/kvm/e500mc.c vcpu->arch.sprg9 = set_reg_val(id, *val); val 298 arch/powerpc/kvm/e500mc.c r = kvmppc_set_one_reg_e500_tlb(vcpu, id, val); val 230 arch/powerpc/kvm/emulate_loadstore.c emulated = kvmppc_handle_store(run, vcpu, op.val, val 126 arch/powerpc/kvm/mpic.c u32 val, int idx); val 130 arch/powerpc/kvm/mpic.c uint32_t val); val 581 arch/powerpc/kvm/mpic.c uint32_t val) val 595 arch/powerpc/kvm/mpic.c src->idr = val & mask; val 626 arch/powerpc/kvm/mpic.c uint32_t val) val 631 arch/powerpc/kvm/mpic.c src->output = val & ILR_INTTGT_MASK; val 640 arch/powerpc/kvm/mpic.c uint32_t val) val 652 arch/powerpc/kvm/mpic.c (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); val 674 arch/powerpc/kvm/mpic.c pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, val 678 arch/powerpc/kvm/mpic.c static void openpic_gcr_write(struct openpic *opp, uint64_t val) val 680 arch/powerpc/kvm/mpic.c if (val & GCR_RESET) { val 686 arch/powerpc/kvm/mpic.c opp->gcr |= val & opp->mpic_mode_mask; val 689 arch/powerpc/kvm/mpic.c static int openpic_gbl_write(void *opaque, gpa_t addr, u32 val) val 694 arch/powerpc/kvm/mpic.c pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val); val 709 arch/powerpc/kvm/mpic.c err = openpic_cpu_write_internal(opp, addr, val, val 715 arch/powerpc/kvm/mpic.c openpic_gcr_write(opp, val); val 732 arch/powerpc/kvm/mpic.c write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); val 736 arch/powerpc/kvm/mpic.c opp->spve = val & opp->vector_mask; val 807 arch/powerpc/kvm/mpic.c static int openpic_tmr_write(void *opaque, gpa_t addr, u32 val) val 814 arch/powerpc/kvm/mpic.c pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val); val 820 arch/powerpc/kvm/mpic.c opp->tfrr = val; val 832 arch/powerpc/kvm/mpic.c (val & TBCR_CI) == 0 && val 836 arch/powerpc/kvm/mpic.c opp->timers[idx].tbcr = val; val 839 arch/powerpc/kvm/mpic.c write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val); val 842 arch/powerpc/kvm/mpic.c write_IRQreg_idr(opp, opp->irq_tim0 + idx, val); val 887 arch/powerpc/kvm/mpic.c static int openpic_src_write(void *opaque, gpa_t addr, u32 val) val 892 arch/powerpc/kvm/mpic.c pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val); val 899 arch/powerpc/kvm/mpic.c write_IRQreg_ivpr(opp, idx, val); val 902 arch/powerpc/kvm/mpic.c write_IRQreg_idr(opp, idx, val); val 905 arch/powerpc/kvm/mpic.c write_IRQreg_ilr(opp, idx, val); val 941 arch/powerpc/kvm/mpic.c static int openpic_msi_write(void *opaque, gpa_t addr, u32 val) val 947 arch/powerpc/kvm/mpic.c pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val); val 953 arch/powerpc/kvm/mpic.c srs = val >> MSIIR_SRS_SHIFT; val 955 arch/powerpc/kvm/mpic.c ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT; val 1016 arch/powerpc/kvm/mpic.c static int openpic_summary_write(void *opaque, gpa_t addr, u32 val) val 1018 arch/powerpc/kvm/mpic.c pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val); val 1025 arch/powerpc/kvm/mpic.c u32 val, int idx) val 1033 arch/powerpc/kvm/mpic.c addr, val); val 1050 arch/powerpc/kvm/mpic.c opp->src[opp->irq_ipi0 + idx].destmask |= val; val 1055 arch/powerpc/kvm/mpic.c dst->ctpr = val & 0x0000000F; val 1119 arch/powerpc/kvm/mpic.c static int openpic_cpu_write(void *opaque, gpa_t addr, u32 val) val 1123 arch/powerpc/kvm/mpic.c return openpic_cpu_write_internal(opp, addr, val, val 1242 arch/powerpc/kvm/mpic.c int (*write)(void *opaque, gpa_t addr, u32 val); val 1356 arch/powerpc/kvm/mpic.c static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val) val 1366 arch/powerpc/kvm/mpic.c return mr->write(opp, addr - mr->start_addr, val); val 1379 arch/powerpc/kvm/mpic.c u32 val; val 1390 arch/powerpc/kvm/mpic.c ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val); val 1399 arch/powerpc/kvm/mpic.c *(u32 *)ptr = u.val; val 1401 arch/powerpc/kvm/mpic.c __func__, addr, ret, u.val); val 1497 arch/powerpc/kvm/mpic.c static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type) val 1507 arch/powerpc/kvm/mpic.c ret = kvm_mpic_write_internal(opp, addr, *val); val 1509 arch/powerpc/kvm/mpic.c ret = kvm_mpic_read_internal(opp, addr, val); val 1513 arch/powerpc/kvm/mpic.c pr_debug("%s: type %d addr %llx val %x\n", __func__, type, addr, *val); val 894 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 902 arch/powerpc/kvm/powerpc.c val.vval = VCPU_VSX_VR(vcpu, index - 32); val 903 arch/powerpc/kvm/powerpc.c val.vsxval[offset] = gpr; val 904 arch/powerpc/kvm/powerpc.c VCPU_VSX_VR(vcpu, index - 32) = val.vval; val 913 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 917 arch/powerpc/kvm/powerpc.c val.vval = VCPU_VSX_VR(vcpu, index - 32); val 918 arch/powerpc/kvm/powerpc.c val.vsxval[0] = gpr; val 919 arch/powerpc/kvm/powerpc.c val.vsxval[1] = gpr; val 920 arch/powerpc/kvm/powerpc.c VCPU_VSX_VR(vcpu, index - 32) = val.vval; val 930 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 934 arch/powerpc/kvm/powerpc.c val.vsx32val[0] = gpr; val 935 arch/powerpc/kvm/powerpc.c val.vsx32val[1] = gpr; val 936 arch/powerpc/kvm/powerpc.c val.vsx32val[2] = gpr; val 937 arch/powerpc/kvm/powerpc.c val.vsx32val[3] = gpr; val 938 arch/powerpc/kvm/powerpc.c VCPU_VSX_VR(vcpu, index - 32) = val.vval; val 940 arch/powerpc/kvm/powerpc.c val.vsx32val[0] = gpr; val 941 arch/powerpc/kvm/powerpc.c val.vsx32val[1] = gpr; val 942 arch/powerpc/kvm/powerpc.c VCPU_VSX_FPR(vcpu, index, 0) = val.vsxval[0]; val 943 arch/powerpc/kvm/powerpc.c VCPU_VSX_FPR(vcpu, index, 1) = val.vsxval[0]; val 950 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 959 arch/powerpc/kvm/powerpc.c val.vval = VCPU_VSX_VR(vcpu, index - 32); val 960 arch/powerpc/kvm/powerpc.c val.vsx32val[offset] = gpr32; val 961 arch/powerpc/kvm/powerpc.c VCPU_VSX_VR(vcpu, index - 32) = val.vval; val 965 arch/powerpc/kvm/powerpc.c val.vsxval[0] = VCPU_VSX_FPR(vcpu, index, dword_offset); val 966 arch/powerpc/kvm/powerpc.c val.vsx32val[word_offset] = gpr32; val 967 arch/powerpc/kvm/powerpc.c VCPU_VSX_FPR(vcpu, index, dword_offset) = val.vsxval[0]; val 1018 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 1026 arch/powerpc/kvm/powerpc.c val.vval = VCPU_VSX_VR(vcpu, index); val 1027 arch/powerpc/kvm/powerpc.c val.vsxval[offset] = gpr; val 1028 arch/powerpc/kvm/powerpc.c VCPU_VSX_VR(vcpu, index) = val.vval; val 1034 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 1042 arch/powerpc/kvm/powerpc.c val.vval = VCPU_VSX_VR(vcpu, index); val 1043 arch/powerpc/kvm/powerpc.c val.vsx32val[offset] = gpr32; val 1044 arch/powerpc/kvm/powerpc.c VCPU_VSX_VR(vcpu, index) = val.vval; val 1050 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 1058 arch/powerpc/kvm/powerpc.c val.vval = VCPU_VSX_VR(vcpu, index); val 1059 arch/powerpc/kvm/powerpc.c val.vsx16val[offset] = gpr16; val 1060 arch/powerpc/kvm/powerpc.c VCPU_VSX_VR(vcpu, index) = val.vval; val 1066 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 1074 arch/powerpc/kvm/powerpc.c val.vval = VCPU_VSX_VR(vcpu, index); val 1075 arch/powerpc/kvm/powerpc.c val.vsx8val[offset] = gpr8; val 1076 arch/powerpc/kvm/powerpc.c VCPU_VSX_VR(vcpu, index) = val.vval; val 1311 arch/powerpc/kvm/powerpc.c u64 val, unsigned int bytes, int is_default_endian) val 1336 arch/powerpc/kvm/powerpc.c val = dp_to_sp(val); val 1341 arch/powerpc/kvm/powerpc.c case 8: *(u64 *)data = val; break; val 1342 arch/powerpc/kvm/powerpc.c case 4: *(u32 *)data = val; break; val 1343 arch/powerpc/kvm/powerpc.c case 2: *(u16 *)data = val; break; val 1344 arch/powerpc/kvm/powerpc.c case 1: *(u8 *)data = val; break; val 1348 arch/powerpc/kvm/powerpc.c case 8: *(u64 *)data = swab64(val); break; val 1349 arch/powerpc/kvm/powerpc.c case 4: *(u32 *)data = swab32(val); break; val 1350 arch/powerpc/kvm/powerpc.c case 2: *(u16 *)data = swab16(val); break; val 1351 arch/powerpc/kvm/powerpc.c case 1: *(u8 *)data = val; break; val 1372 arch/powerpc/kvm/powerpc.c static inline int kvmppc_get_vsr_data(struct kvm_vcpu *vcpu, int rs, u64 *val) val 1391 arch/powerpc/kvm/powerpc.c *val = VCPU_VSX_FPR(vcpu, rs, vsx_offset); val 1394 arch/powerpc/kvm/powerpc.c *val = reg.vsxval[vsx_offset]; val 1411 arch/powerpc/kvm/powerpc.c *val = reg.vsx32val[word_offset]; val 1414 arch/powerpc/kvm/powerpc.c *val = reg.vsx32val[vsx_offset]; val 1429 arch/powerpc/kvm/powerpc.c u64 val; val 1439 arch/powerpc/kvm/powerpc.c if (kvmppc_get_vsr_data(vcpu, rs, &val) == -1) val 1443 arch/powerpc/kvm/powerpc.c val, bytes, is_default_endian); val 1516 arch/powerpc/kvm/powerpc.c int kvmppc_get_vmx_dword(struct kvm_vcpu *vcpu, int index, u64 *val) val 1529 arch/powerpc/kvm/powerpc.c *val = reg.vsxval[vmx_offset]; val 1534 arch/powerpc/kvm/powerpc.c int kvmppc_get_vmx_word(struct kvm_vcpu *vcpu, int index, u64 *val) val 1547 arch/powerpc/kvm/powerpc.c *val = reg.vsx32val[vmx_offset]; val 1552 arch/powerpc/kvm/powerpc.c int kvmppc_get_vmx_hword(struct kvm_vcpu *vcpu, int index, u64 *val) val 1565 arch/powerpc/kvm/powerpc.c *val = reg.vsx16val[vmx_offset]; val 1570 arch/powerpc/kvm/powerpc.c int kvmppc_get_vmx_byte(struct kvm_vcpu *vcpu, int index, u64 *val) val 1583 arch/powerpc/kvm/powerpc.c *val = reg.vsx8val[vmx_offset]; val 1591 arch/powerpc/kvm/powerpc.c u64 val = 0; val 1603 arch/powerpc/kvm/powerpc.c if (kvmppc_get_vmx_dword(vcpu, index, &val) == -1) val 1608 arch/powerpc/kvm/powerpc.c if (kvmppc_get_vmx_word(vcpu, index, &val) == -1) val 1612 arch/powerpc/kvm/powerpc.c if (kvmppc_get_vmx_hword(vcpu, index, &val) == -1) val 1616 arch/powerpc/kvm/powerpc.c if (kvmppc_get_vmx_byte(vcpu, index, &val) == -1) val 1623 arch/powerpc/kvm/powerpc.c emulated = kvmppc_handle_store(run, vcpu, val, bytes, val 1674 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 1678 arch/powerpc/kvm/powerpc.c if (size > sizeof(val)) val 1681 arch/powerpc/kvm/powerpc.c r = kvmppc_get_one_reg(vcpu, reg->id, &val); val 1691 arch/powerpc/kvm/powerpc.c val.vval = vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0]; val 1698 arch/powerpc/kvm/powerpc.c val = get_reg_val(reg->id, vcpu->arch.vr.vscr.u[3]); val 1701 arch/powerpc/kvm/powerpc.c val = get_reg_val(reg->id, vcpu->arch.vrsave); val 1713 arch/powerpc/kvm/powerpc.c if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size)) val 1722 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg val; val 1726 arch/powerpc/kvm/powerpc.c if (size > sizeof(val)) val 1729 arch/powerpc/kvm/powerpc.c if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size)) val 1732 arch/powerpc/kvm/powerpc.c r = kvmppc_set_one_reg(vcpu, reg->id, &val); val 1742 arch/powerpc/kvm/powerpc.c vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0] = val.vval; val 1749 arch/powerpc/kvm/powerpc.c vcpu->arch.vr.vscr.u[3] = set_reg_val(reg->id, val); val 1756 arch/powerpc/kvm/powerpc.c vcpu->arch.vrsave = set_reg_val(reg->id, val); val 70 arch/powerpc/lib/sstep.c unsigned long val) val 74 arch/powerpc/lib/sstep.c val &= 0xffffffffUL; val 76 arch/powerpc/lib/sstep.c return val; val 353 arch/powerpc/lib/sstep.c static nokprobe_inline int write_mem_aligned(unsigned long val, val 361 arch/powerpc/lib/sstep.c err = __put_user(val, (unsigned char __user *) ea); val 364 arch/powerpc/lib/sstep.c err = __put_user(val, (unsigned short __user *) ea); val 367 arch/powerpc/lib/sstep.c err = __put_user(val, (unsigned int __user *) ea); val 371 arch/powerpc/lib/sstep.c err = __put_user(val, (unsigned long __user *) ea); val 423 arch/powerpc/lib/sstep.c static nokprobe_inline int write_mem_unaligned(unsigned long val, val 433 arch/powerpc/lib/sstep.c u.ul = val; val 442 arch/powerpc/lib/sstep.c static int write_mem(unsigned long val, unsigned long ea, int nb, val 448 arch/powerpc/lib/sstep.c return write_mem_aligned(val, ea, nb, regs); val 449 arch/powerpc/lib/sstep.c return write_mem_unaligned(val, ea, nb, regs); val 712 arch/powerpc/lib/sstep.c u32 val = reg->w[IS_LE ? 3 : 0]; val 715 arch/powerpc/lib/sstep.c reg->w[i] = val; val 947 arch/powerpc/lib/sstep.c long val = op->val; val 953 arch/powerpc/lib/sstep.c val = (int) val; val 955 arch/powerpc/lib/sstep.c if (val < 0) val 957 arch/powerpc/lib/sstep.c else if (val > 0) val 963 arch/powerpc/lib/sstep.c static nokprobe_inline void set_ca32(struct instruction_op *op, bool val) val 966 arch/powerpc/lib/sstep.c if (val) val 978 arch/powerpc/lib/sstep.c unsigned long val = val1 + val2; val 981 arch/powerpc/lib/sstep.c ++val; val 984 arch/powerpc/lib/sstep.c op->val = val; val 987 arch/powerpc/lib/sstep.c val = (unsigned int) val; val 992 arch/powerpc/lib/sstep.c if (val < val1 || (carry_in && val == val1)) val 997 arch/powerpc/lib/sstep.c set_ca32(op, (unsigned int)val < (unsigned int)val1 || val 998 arch/powerpc/lib/sstep.c (carry_in && (unsigned int)val == (unsigned int)val1)); val 1051 arch/powerpc/lib/sstep.c op->val = out_val; val 1070 arch/powerpc/lib/sstep.c op->val = out; val 1076 arch/powerpc/lib/sstep.c op->val = out & 0x0000003f0000003fULL; val 1081 arch/powerpc/lib/sstep.c op->val = out; /* popcntd */ val 1099 arch/powerpc/lib/sstep.c op->val = perm; val 1114 arch/powerpc/lib/sstep.c op->val = res & 0x0000000100000001ULL; val 1119 arch/powerpc/lib/sstep.c op->val = res & 1; /*prtyd */ val 1170 arch/powerpc/lib/sstep.c unsigned long int val, val2; val 1183 arch/powerpc/lib/sstep.c op->val = truncate_if_32bit(regs->msr, imm); val 1204 arch/powerpc/lib/sstep.c op->val = truncate_if_32bit(regs->msr, imm); val 1216 arch/powerpc/lib/sstep.c val = (regs->ccr >> ra) & 0xf; val 1217 arch/powerpc/lib/sstep.c op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd); val 1224 arch/powerpc/lib/sstep.c op->val = truncate_if_32bit(regs->msr, imm); val 1255 arch/powerpc/lib/sstep.c val = (instr >> (6 + ra * 2 + rb)) & 1; val 1257 arch/powerpc/lib/sstep.c (val << (31 - rd)); val 1313 arch/powerpc/lib/sstep.c "=r" (op->val) : "r" (regs->gpr[ra]), val 1319 arch/powerpc/lib/sstep.c "=r" (op->val) : "r" (regs->gpr[ra]), val 1325 arch/powerpc/lib/sstep.c "=r" (op->val) : "r" (regs->gpr[ra]), val 1338 arch/powerpc/lib/sstep.c op->val = regs->gpr[ra] * (short) instr; val 1348 arch/powerpc/lib/sstep.c val = regs->gpr[ra]; val 1351 arch/powerpc/lib/sstep.c val = (unsigned int) val; val 1353 arch/powerpc/lib/sstep.c do_cmp_unsigned(regs, op, val, imm, rd >> 2); val 1358 arch/powerpc/lib/sstep.c val = regs->gpr[ra]; val 1361 arch/powerpc/lib/sstep.c val = (int) val; val 1363 arch/powerpc/lib/sstep.c do_cmp_signed(regs, op, val, imm, rd >> 2); val 1381 arch/powerpc/lib/sstep.c op->val = imm; val 1388 arch/powerpc/lib/sstep.c op->val = imm; val 1396 arch/powerpc/lib/sstep.c op->val = regs->nip + (imm << 16) + 4; val 1405 arch/powerpc/lib/sstep.c val = DATA32(regs->gpr[rd]); val 1407 arch/powerpc/lib/sstep.c op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); val 1413 arch/powerpc/lib/sstep.c val = DATA32(regs->gpr[rd]); val 1414 arch/powerpc/lib/sstep.c op->val = ROTATE(val, rb) & MASK32(mb, me); val 1421 arch/powerpc/lib/sstep.c val = DATA32(regs->gpr[rd]); val 1422 arch/powerpc/lib/sstep.c op->val = ROTATE(val, rb) & MASK32(mb, me); val 1426 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] | (unsigned short) instr; val 1431 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] | (imm << 16); val 1435 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] ^ (unsigned short) instr; val 1440 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] ^ (imm << 16); val 1444 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] & (unsigned short) instr; val 1450 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] & (imm << 16); val 1457 arch/powerpc/lib/sstep.c val = regs->gpr[rd]; val 1460 arch/powerpc/lib/sstep.c val = ROTATE(val, sh); val 1463 arch/powerpc/lib/sstep.c val &= MASK64_L(mb); val 1466 arch/powerpc/lib/sstep.c val &= MASK64_R(mb); val 1469 arch/powerpc/lib/sstep.c val &= MASK64(mb, 63 - sh); val 1473 arch/powerpc/lib/sstep.c val = (regs->gpr[ra] & ~imm) | val 1474 arch/powerpc/lib/sstep.c (val & imm); val 1476 arch/powerpc/lib/sstep.c op->val = val; val 1480 arch/powerpc/lib/sstep.c val = ROTATE(val, sh); val 1483 arch/powerpc/lib/sstep.c op->val = val & MASK64_L(mb); val 1486 arch/powerpc/lib/sstep.c op->val = val & MASK64_R(mb); val 1498 arch/powerpc/lib/sstep.c val = (regs->ccr >> (31 - mb)) & 1; val 1501 arch/powerpc/lib/sstep.c op->val = (val) ? val2 : regs->gpr[rb]; val 1529 arch/powerpc/lib/sstep.c op->val = 0xffffffff & ~(MSR_ME | MSR_LE); val 1540 arch/powerpc/lib/sstep.c op->val = imm; val 1554 arch/powerpc/lib/sstep.c op->val = regs->ccr & imm; val 1560 arch/powerpc/lib/sstep.c val = regs->gpr[rd]; val 1565 arch/powerpc/lib/sstep.c (val & imm); val 1583 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd]; val 1594 arch/powerpc/lib/sstep.c val = regs->gpr[ra]; val 1599 arch/powerpc/lib/sstep.c val = (int) val; val 1603 arch/powerpc/lib/sstep.c do_cmp_signed(regs, op, val, val2, rd >> 2); val 1607 arch/powerpc/lib/sstep.c val = regs->gpr[ra]; val 1612 arch/powerpc/lib/sstep.c val = (unsigned int) val; val 1616 arch/powerpc/lib/sstep.c do_cmp_unsigned(regs, op, val, val2, rd >> 2); val 1632 arch/powerpc/lib/sstep.c asm("mulhdu %0,%1,%2" : "=r" (op->val) : val 1642 arch/powerpc/lib/sstep.c asm("mulhwu %0,%1,%2" : "=r" (op->val) : val 1647 arch/powerpc/lib/sstep.c op->val = regs->gpr[rb] - regs->gpr[ra]; val 1651 arch/powerpc/lib/sstep.c asm("mulhd %0,%1,%2" : "=r" (op->val) : val 1656 arch/powerpc/lib/sstep.c asm("mulhw %0,%1,%2" : "=r" (op->val) : val 1661 arch/powerpc/lib/sstep.c op->val = -regs->gpr[ra]; val 1690 arch/powerpc/lib/sstep.c op->val = regs->gpr[ra] * regs->gpr[rb]; val 1699 arch/powerpc/lib/sstep.c op->val = (long)(int) regs->gpr[ra] * val 1707 arch/powerpc/lib/sstep.c op->val = regs->gpr[ra] % regs->gpr[rb]; val 1711 arch/powerpc/lib/sstep.c op->val = regs->gpr[ra] + regs->gpr[rb]; val 1717 arch/powerpc/lib/sstep.c op->val = (unsigned int) regs->gpr[ra] % val 1722 arch/powerpc/lib/sstep.c op->val = regs->gpr[ra] / regs->gpr[rb]; val 1726 arch/powerpc/lib/sstep.c op->val = (unsigned int) regs->gpr[ra] / val 1731 arch/powerpc/lib/sstep.c op->val = (long int) regs->gpr[ra] / val 1736 arch/powerpc/lib/sstep.c op->val = (int) regs->gpr[ra] / val 1746 arch/powerpc/lib/sstep.c asm volatile(PPC_DARN(%0, 0) : "=r" (op->val)); val 1751 arch/powerpc/lib/sstep.c asm volatile(PPC_DARN(%0, 1) : "=r" (op->val)); val 1756 arch/powerpc/lib/sstep.c asm volatile(PPC_DARN(%0, 2) : "=r" (op->val)); val 1765 arch/powerpc/lib/sstep.c op->val = (long int) regs->gpr[ra] % val 1772 arch/powerpc/lib/sstep.c op->val = (int) regs->gpr[ra] % val 1781 arch/powerpc/lib/sstep.c val = (unsigned int) regs->gpr[rd]; val 1782 arch/powerpc/lib/sstep.c op->val = ( val ? __builtin_clz(val) : 32 ); val 1786 arch/powerpc/lib/sstep.c val = regs->gpr[rd]; val 1787 arch/powerpc/lib/sstep.c op->val = ( val ? __builtin_clzl(val) : 64 ); val 1791 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] & regs->gpr[rb]; val 1795 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] & ~regs->gpr[rb]; val 1803 arch/powerpc/lib/sstep.c op->val = ~(regs->gpr[rd] | regs->gpr[rb]); val 1819 arch/powerpc/lib/sstep.c op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]); val 1823 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] ^ regs->gpr[rb]; val 1831 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] | ~regs->gpr[rb]; val 1835 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] | regs->gpr[rb]; val 1839 arch/powerpc/lib/sstep.c op->val = ~(regs->gpr[rd] & regs->gpr[rb]); val 1849 arch/powerpc/lib/sstep.c val = (unsigned int) regs->gpr[rd]; val 1850 arch/powerpc/lib/sstep.c op->val = (val ? __builtin_ctz(val) : 32); val 1856 arch/powerpc/lib/sstep.c val = regs->gpr[rd]; val 1857 arch/powerpc/lib/sstep.c op->val = (val ? __builtin_ctzl(val) : 64); val 1861 arch/powerpc/lib/sstep.c op->val = (signed short) regs->gpr[rd]; val 1865 arch/powerpc/lib/sstep.c op->val = (signed char) regs->gpr[rd]; val 1869 arch/powerpc/lib/sstep.c op->val = (signed int) regs->gpr[rd]; val 1879 arch/powerpc/lib/sstep.c op->val = (regs->gpr[rd] << sh) & 0xffffffffUL; val 1881 arch/powerpc/lib/sstep.c op->val = 0; val 1887 arch/powerpc/lib/sstep.c op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh; val 1889 arch/powerpc/lib/sstep.c op->val = 0; val 1896 arch/powerpc/lib/sstep.c op->val = ival >> (sh < 32 ? sh : 31); val 1909 arch/powerpc/lib/sstep.c op->val = ival >> sh; val 1922 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] << sh; val 1924 arch/powerpc/lib/sstep.c op->val = 0; val 1930 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd] >> sh; val 1932 arch/powerpc/lib/sstep.c op->val = 0; val 1939 arch/powerpc/lib/sstep.c op->val = ival >> (sh < 64 ? sh : 63); val 1953 arch/powerpc/lib/sstep.c op->val = ival >> sh; val 1968 arch/powerpc/lib/sstep.c val = (signed int) regs->gpr[rd]; val 1970 arch/powerpc/lib/sstep.c op->val = ROTATE(val, sh) & MASK64(0, 63 - sh); val 1972 arch/powerpc/lib/sstep.c op->val = val; val 2021 arch/powerpc/lib/sstep.c op->val = regs->gpr[rd]; val 2243 arch/powerpc/lib/sstep.c op->val = byterev_8(regs->gpr[rd]); val 2253 arch/powerpc/lib/sstep.c op->val = byterev_4(regs->gpr[rd]); val 2269 arch/powerpc/lib/sstep.c op->val = byterev_2(regs->gpr[rd]); val 2683 arch/powerpc/lib/sstep.c op->val = SRR1_PROGPRIV; val 2688 arch/powerpc/lib/sstep.c op->val = SRR1_PROGTRAP; val 2763 arch/powerpc/lib/sstep.c regs->gpr[op->reg] = op->val; val 2774 arch/powerpc/lib/sstep.c next_pc = op->val; val 2818 arch/powerpc/lib/sstep.c regs->xer = op->val & 0xffffffffUL; val 2821 arch/powerpc/lib/sstep.c regs->link = op->val; val 2824 arch/powerpc/lib/sstep.c regs->ctr = op->val; val 2852 arch/powerpc/lib/sstep.c unsigned long val; val 2869 arch/powerpc/lib/sstep.c val = 0; val 2873 arch/powerpc/lib/sstep.c __get_user_asmx(val, ea, err, "lbarx"); val 2876 arch/powerpc/lib/sstep.c __get_user_asmx(val, ea, err, "lharx"); val 2880 arch/powerpc/lib/sstep.c __get_user_asmx(val, ea, err, "lwarx"); val 2884 arch/powerpc/lib/sstep.c __get_user_asmx(val, ea, err, "ldarx"); val 2898 arch/powerpc/lib/sstep.c regs->gpr[op->reg] = val; val 2910 arch/powerpc/lib/sstep.c __put_user_asmx(op->val, ea, err, "stbcx.", cr); val 2913 arch/powerpc/lib/sstep.c __put_user_asmx(op->val, ea, err, "stbcx.", cr); val 2917 arch/powerpc/lib/sstep.c __put_user_asmx(op->val, ea, err, "stwcx.", cr); val 2921 arch/powerpc/lib/sstep.c __put_user_asmx(op->val, ea, err, "stdcx.", cr); val 3028 arch/powerpc/lib/sstep.c do_byterev(&op->val, size); val 3029 arch/powerpc/lib/sstep.c err = write_mem(op->val, ea, size, regs); val 3108 arch/powerpc/lib/sstep.c unsigned long val; val 3167 arch/powerpc/lib/sstep.c val = regs->gpr[op.reg]; val 3168 arch/powerpc/lib/sstep.c if ((val & MSR_RI) == 0) val 3172 arch/powerpc/lib/sstep.c regs->msr = (regs->msr & ~op.val) | (val & op.val); val 1977 arch/powerpc/mm/book3s64/hash_utils.c static int hpt_order_get(void *data, u64 *val) val 1979 arch/powerpc/mm/book3s64/hash_utils.c *val = ppc64_pft_size; val 1983 arch/powerpc/mm/book3s64/hash_utils.c static int hpt_order_set(void *data, u64 val) val 1991 arch/powerpc/mm/book3s64/hash_utils.c ret = mmu_hash_ops.resize_hpt(val); val 342 arch/powerpc/mm/init_64.c bool val; val 345 arch/powerpc/mm/init_64.c val = true; val 346 arch/powerpc/mm/init_64.c else if (kstrtobool(p, &val)) val 349 arch/powerpc/mm/init_64.c disable_radix = val; val 105 arch/powerpc/mm/nohash/40x.c unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_HWWRITE; val 108 arch/powerpc/mm/nohash/40x.c *pmdp++ = __pmd(val); val 109 arch/powerpc/mm/nohash/40x.c *pmdp++ = __pmd(val); val 110 arch/powerpc/mm/nohash/40x.c *pmdp++ = __pmd(val); val 111 arch/powerpc/mm/nohash/40x.c *pmdp++ = __pmd(val); val 120 arch/powerpc/mm/nohash/40x.c unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_HWWRITE; val 123 arch/powerpc/mm/nohash/40x.c *pmdp = __pmd(val); val 15 arch/powerpc/mm/ptdump/8xx.c .val = 0, val 20 arch/powerpc/mm/ptdump/8xx.c .val = 0, val 24 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_RO, val 28 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_NA, val 32 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_EXEC, val 37 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_PRESENT, val 42 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_GUARDED, val 47 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_DIRTY, val 52 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_ACCESSED, val 57 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_NO_CACHE, val 62 arch/powerpc/mm/ptdump/8xx.c .val = _PAGE_SPECIAL, val 15 arch/powerpc/mm/ptdump/book3s64.c .val = 0, val 20 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_READ, val 25 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_WRITE, val 30 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_EXEC, val 35 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_PTE, val 40 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_PRESENT, val 45 arch/powerpc/mm/ptdump/book3s64.c .val = 0, val 50 arch/powerpc/mm/ptdump/book3s64.c .val = H_PAGE_HASHPTE, val 55 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_DIRTY, val 60 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_ACCESSED, val 65 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_NON_IDEMPOTENT, val 70 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_TOLERANT, val 75 arch/powerpc/mm/ptdump/book3s64.c .val = H_PAGE_BUSY, val 80 arch/powerpc/mm/ptdump/book3s64.c .val = H_PAGE_COMBO, val 84 arch/powerpc/mm/ptdump/book3s64.c .val = H_PAGE_4K_PFN, val 89 arch/powerpc/mm/ptdump/book3s64.c .val = H_PAGE_F_GIX, val 95 arch/powerpc/mm/ptdump/book3s64.c .val = H_PAGE_F_SECOND, val 100 arch/powerpc/mm/ptdump/book3s64.c .val = _PAGE_SPECIAL, val 55 arch/powerpc/mm/ptdump/hashpagetable.c u64 val; val 65 arch/powerpc/mm/ptdump/hashpagetable.c .val = SLB_VSID_B_256M, val 70 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_V_SECONDARY, val 75 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_V_VALID, val 80 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_V_BOLTED, val 89 arch/powerpc/mm/ptdump/hashpagetable.c .val = PP_RWXX, val 93 arch/powerpc/mm/ptdump/hashpagetable.c .val = PP_RWRX, val 97 arch/powerpc/mm/ptdump/hashpagetable.c .val = PP_RWRW, val 101 arch/powerpc/mm/ptdump/hashpagetable.c .val = PP_RXRX, val 105 arch/powerpc/mm/ptdump/hashpagetable.c .val = PP_RXXX, val 109 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_R_KEY_HI | HPTE_R_KEY_LO, val 115 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_R_R, val 120 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_R_C, val 125 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_R_N, val 129 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_R_W, val 133 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_R_I, val 137 arch/powerpc/mm/ptdump/hashpagetable.c .val = HPTE_R_G, val 162 arch/powerpc/mm/ptdump/hashpagetable.c u64 val; val 169 arch/powerpc/mm/ptdump/hashpagetable.c val = pte & flag->val; val 171 arch/powerpc/mm/ptdump/hashpagetable.c val = val >> flag->shift; val 172 arch/powerpc/mm/ptdump/hashpagetable.c seq_printf(st->seq, " %s:%llx", flag->set, val); val 174 arch/powerpc/mm/ptdump/hashpagetable.c if ((pte & flag->mask) == flag->val) val 121 arch/powerpc/mm/ptdump/ptdump.c u64 val; val 128 arch/powerpc/mm/ptdump/ptdump.c val = pte & flag->val; val 130 arch/powerpc/mm/ptdump/ptdump.c val = val >> flag->shift; val 131 arch/powerpc/mm/ptdump/ptdump.c pt_dump_seq_printf(st->seq, " %s:%llx", flag->set, val); val 133 arch/powerpc/mm/ptdump/ptdump.c if ((pte & flag->mask) == flag->val) val 192 arch/powerpc/mm/ptdump/ptdump.c unsigned int level, u64 val, unsigned long page_size) val 194 arch/powerpc/mm/ptdump/ptdump.c u64 flag = val & pg_level[level].mask; val 195 arch/powerpc/mm/ptdump/ptdump.c u64 pa = val & PTE_RPN_MASK; val 6 arch/powerpc/mm/ptdump/ptdump.h u64 val; val 13 arch/powerpc/mm/ptdump/segment_regs.c u32 val = mfsrin(i << 28); val 16 arch/powerpc/mm/ptdump/segment_regs.c seq_printf(m, "Kern key %d ", (val >> 30) & 1); val 17 arch/powerpc/mm/ptdump/segment_regs.c seq_printf(m, "User key %d ", (val >> 29) & 1); val 18 arch/powerpc/mm/ptdump/segment_regs.c if (val & 0x80000000) { val 19 arch/powerpc/mm/ptdump/segment_regs.c seq_printf(m, "Device 0x%03x", (val >> 20) & 0x1ff); val 20 arch/powerpc/mm/ptdump/segment_regs.c seq_printf(m, "-0x%05x", val & 0xfffff); val 22 arch/powerpc/mm/ptdump/segment_regs.c if (val & 0x10000000) val 24 arch/powerpc/mm/ptdump/segment_regs.c seq_printf(m, "VSID 0x%06x", val & 0xffffff); val 15 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_USER, val 20 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_RW, val 25 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_EXEC, val 30 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_PRESENT, val 35 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_GUARDED, val 40 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_DIRTY, val 45 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_ACCESSED, val 50 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_WRITETHRU, val 55 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_NO_CACHE, val 60 arch/powerpc/mm/ptdump/shared.c .val = _PAGE_SPECIAL, val 422 arch/powerpc/oprofile/cell/spu_task_sync.c static int spu_active_notify(struct notifier_block *self, unsigned long val, val 430 arch/powerpc/oprofile/cell/spu_task_sync.c if (!val) { val 435 arch/powerpc/oprofile/cell/spu_task_sync.c retval = process_context_switch(the_spu, val); val 173 arch/powerpc/oprofile/op_model_7450.c int val; val 183 arch/powerpc/oprofile/op_model_7450.c val = classic_ctr_read(i); val 184 arch/powerpc/oprofile/op_model_7450.c if (val < 0) { val 376 arch/powerpc/oprofile/op_model_cell.c u32 val = 0; val 378 arch/powerpc/oprofile/op_model_cell.c val |= CBE_PM_ENABLE_PERF_MON; val 381 arch/powerpc/oprofile/op_model_cell.c val |= CBE_PM_STOP_AT_MAX; val 384 arch/powerpc/oprofile/op_model_cell.c val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode); val 387 arch/powerpc/oprofile/op_model_cell.c val |= CBE_PM_TRACE_BUF_OVFLW(pm_regs.pm_cntrl.trace_buf_ovflw); val 389 arch/powerpc/oprofile/op_model_cell.c val |= CBE_PM_FREEZE_ALL_CTRS; val 391 arch/powerpc/oprofile/op_model_cell.c val |= CBE_PM_SPU_ADDR_TRACE_SET(pm_regs.pm_cntrl.spu_addr_trace); val 397 arch/powerpc/oprofile/op_model_cell.c val |= CBE_PM_COUNT_MODE_SET(pm_regs.pm_cntrl.count_mode); val 398 arch/powerpc/oprofile/op_model_cell.c cbe_write_pm(cpu, pm_control, val); val 1111 arch/powerpc/oprofile/op_model_cell.c oprof_cpufreq_notify(struct notifier_block *nb, unsigned long val, void *data) val 1115 arch/powerpc/oprofile/op_model_cell.c if ((val == CPUFREQ_PRECHANGE && frq->old < frq->new) || val 1116 arch/powerpc/oprofile/op_model_cell.c (val == CPUFREQ_POSTCHANGE && frq->old > frq->new)) val 103 arch/powerpc/oprofile/op_model_fsl_emb.c static inline void ctr_write(unsigned int i, unsigned int val) val 107 arch/powerpc/oprofile/op_model_fsl_emb.c mtpmr(PMRN_PMC0, val); val 110 arch/powerpc/oprofile/op_model_fsl_emb.c mtpmr(PMRN_PMC1, val); val 113 arch/powerpc/oprofile/op_model_fsl_emb.c mtpmr(PMRN_PMC2, val); val 116 arch/powerpc/oprofile/op_model_fsl_emb.c mtpmr(PMRN_PMC3, val); val 119 arch/powerpc/oprofile/op_model_fsl_emb.c mtpmr(PMRN_PMC4, val); val 122 arch/powerpc/oprofile/op_model_fsl_emb.c mtpmr(PMRN_PMC5, val); val 345 arch/powerpc/oprofile/op_model_fsl_emb.c int val; val 352 arch/powerpc/oprofile/op_model_fsl_emb.c val = ctr_read(i); val 353 arch/powerpc/oprofile/op_model_fsl_emb.c if (val < 0) { val 50 arch/powerpc/oprofile/op_model_pa6t.c static inline void ctr_write(unsigned int i, u64 val) val 54 arch/powerpc/oprofile/op_model_pa6t.c mtspr(SPRN_PA6T_PMC0, val); val 57 arch/powerpc/oprofile/op_model_pa6t.c mtspr(SPRN_PA6T_PMC1, val); val 60 arch/powerpc/oprofile/op_model_pa6t.c mtspr(SPRN_PA6T_PMC2, val); val 63 arch/powerpc/oprofile/op_model_pa6t.c mtspr(SPRN_PA6T_PMC3, val); val 66 arch/powerpc/oprofile/op_model_pa6t.c mtspr(SPRN_PA6T_PMC4, val); val 69 arch/powerpc/oprofile/op_model_pa6t.c mtspr(SPRN_PA6T_PMC5, val); val 192 arch/powerpc/oprofile/op_model_pa6t.c u64 val; val 204 arch/powerpc/oprofile/op_model_pa6t.c val = ctr_read(i); val 205 arch/powerpc/oprofile/op_model_pa6t.c if (val & (0x1UL << 39)) { /* Overflow bit set */ val 337 arch/powerpc/oprofile/op_model_power4.c static bool pmc_overflow(unsigned long val) val 339 arch/powerpc/oprofile/op_model_power4.c if ((int)val < 0) val 353 arch/powerpc/oprofile/op_model_power4.c if (pvr_version_is(PVR_POWER7) && ((0x80000000 - val) <= 256)) val 364 arch/powerpc/oprofile/op_model_power4.c int val; val 383 arch/powerpc/oprofile/op_model_power4.c val = classic_ctr_read(i); val 384 arch/powerpc/oprofile/op_model_power4.c if (pmc_overflow(val)) { val 83 arch/powerpc/perf/8xx-pmu.c s64 val = 0; val 90 arch/powerpc/perf/8xx-pmu.c val = get_tb(); val 95 arch/powerpc/perf/8xx-pmu.c val = get_insn_ctr(); val 106 arch/powerpc/perf/8xx-pmu.c val = itlb_miss_counter; val 116 arch/powerpc/perf/8xx-pmu.c val = dtlb_miss_counter; val 119 arch/powerpc/perf/8xx-pmu.c local64_set(&event->hw.prev_count, val); val 126 arch/powerpc/perf/8xx-pmu.c s64 prev, val = 0, delta = 0; val 135 arch/powerpc/perf/8xx-pmu.c val = get_tb(); val 136 arch/powerpc/perf/8xx-pmu.c delta = 16 * (val - prev); val 139 arch/powerpc/perf/8xx-pmu.c val = get_insn_ctr(); val 140 arch/powerpc/perf/8xx-pmu.c delta = prev - val; val 145 arch/powerpc/perf/8xx-pmu.c val = itlb_miss_counter; val 146 arch/powerpc/perf/8xx-pmu.c delta = (s64)((s32)val - (s32)prev); val 149 arch/powerpc/perf/8xx-pmu.c val = dtlb_miss_counter; val 150 arch/powerpc/perf/8xx-pmu.c delta = (s64)((s32)val - (s32)prev); val 153 arch/powerpc/perf/8xx-pmu.c } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); val 449 arch/powerpc/perf/core-book3s.c u64 val; val 457 arch/powerpc/perf/core-book3s.c val = read_bhrb(r_index++); val 458 arch/powerpc/perf/core-book3s.c if (!val) val 462 arch/powerpc/perf/core-book3s.c addr = val & BHRB_EA; val 463 arch/powerpc/perf/core-book3s.c pred = val & BHRB_PREDICTION; val 497 arch/powerpc/perf/core-book3s.c if (val & BHRB_TARGET) { val 506 arch/powerpc/perf/core-book3s.c val = read_bhrb(r_index++); val 507 arch/powerpc/perf/core-book3s.c addr = val & BHRB_EA; val 508 arch/powerpc/perf/core-book3s.c if (val & BHRB_TARGET) { val 731 arch/powerpc/perf/core-book3s.c unsigned long val; val 735 arch/powerpc/perf/core-book3s.c val = mfspr(SPRN_PMC1); val 738 arch/powerpc/perf/core-book3s.c val = mfspr(SPRN_PMC2); val 741 arch/powerpc/perf/core-book3s.c val = mfspr(SPRN_PMC3); val 744 arch/powerpc/perf/core-book3s.c val = mfspr(SPRN_PMC4); val 747 arch/powerpc/perf/core-book3s.c val = mfspr(SPRN_PMC5); val 750 arch/powerpc/perf/core-book3s.c val = mfspr(SPRN_PMC6); val 754 arch/powerpc/perf/core-book3s.c val = mfspr(SPRN_PMC7); val 757 arch/powerpc/perf/core-book3s.c val = mfspr(SPRN_PMC8); val 762 arch/powerpc/perf/core-book3s.c val = 0; val 764 arch/powerpc/perf/core-book3s.c return val; val 770 arch/powerpc/perf/core-book3s.c static void write_pmc(int idx, unsigned long val) val 774 arch/powerpc/perf/core-book3s.c mtspr(SPRN_PMC1, val); val 777 arch/powerpc/perf/core-book3s.c mtspr(SPRN_PMC2, val); val 780 arch/powerpc/perf/core-book3s.c mtspr(SPRN_PMC3, val); val 783 arch/powerpc/perf/core-book3s.c mtspr(SPRN_PMC4, val); val 786 arch/powerpc/perf/core-book3s.c mtspr(SPRN_PMC5, val); val 789 arch/powerpc/perf/core-book3s.c mtspr(SPRN_PMC6, val); val 793 arch/powerpc/perf/core-book3s.c mtspr(SPRN_PMC7, val); val 796 arch/powerpc/perf/core-book3s.c mtspr(SPRN_PMC8, val); val 1034 arch/powerpc/perf/core-book3s.c static u64 check_and_compute_delta(u64 prev, u64 val) val 1036 arch/powerpc/perf/core-book3s.c u64 delta = (val - prev) & 0xfffffffful; val 1047 arch/powerpc/perf/core-book3s.c if (prev > val && (prev - val) < 256) val 1055 arch/powerpc/perf/core-book3s.c s64 val, delta, prev; val 1064 arch/powerpc/perf/core-book3s.c val = read_pmc(event->hw.idx); val 1065 arch/powerpc/perf/core-book3s.c local64_set(&event->hw.prev_count, val); val 1077 arch/powerpc/perf/core-book3s.c val = read_pmc(event->hw.idx); val 1078 arch/powerpc/perf/core-book3s.c delta = check_and_compute_delta(prev, val); val 1081 arch/powerpc/perf/core-book3s.c } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); val 1096 arch/powerpc/perf/core-book3s.c val = prev - delta; val 1097 arch/powerpc/perf/core-book3s.c if (val < 1) val 1098 arch/powerpc/perf/core-book3s.c val = 1; val 1099 arch/powerpc/perf/core-book3s.c } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); val 1117 arch/powerpc/perf/core-book3s.c u64 val, prev, delta; val 1124 arch/powerpc/perf/core-book3s.c val = (event->hw.idx == 5) ? pmc5 : pmc6; val 1127 arch/powerpc/perf/core-book3s.c delta = check_and_compute_delta(prev, val); val 1137 arch/powerpc/perf/core-book3s.c u64 val, prev; val 1143 arch/powerpc/perf/core-book3s.c val = (event->hw.idx == 5) ? pmc5 : pmc6; val 1145 arch/powerpc/perf/core-book3s.c if (check_and_compute_delta(prev, val)) val 1146 arch/powerpc/perf/core-book3s.c local64_set(&event->hw.prev_count, val); val 1204 arch/powerpc/perf/core-book3s.c unsigned long flags, mmcr0, val; val 1223 arch/powerpc/perf/core-book3s.c val = mmcr0 = mfspr(SPRN_MMCR0); val 1224 arch/powerpc/perf/core-book3s.c val |= MMCR0_FC; val 1225 arch/powerpc/perf/core-book3s.c val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | val 1233 arch/powerpc/perf/core-book3s.c write_mmcr0(cpuhw, val); val 1280 arch/powerpc/perf/core-book3s.c unsigned long val, mmcr0; val 1391 arch/powerpc/perf/core-book3s.c val = local64_read(&event->hw.prev_count); val 1393 arch/powerpc/perf/core-book3s.c val = 0; val 1397 arch/powerpc/perf/core-book3s.c val = 0x80000000L - left; val 1399 arch/powerpc/perf/core-book3s.c local64_set(&event->hw.prev_count, val); val 1404 arch/powerpc/perf/core-book3s.c val = 0; val 1405 arch/powerpc/perf/core-book3s.c write_pmc(idx, val); val 1598 arch/powerpc/perf/core-book3s.c unsigned long val; val 1615 arch/powerpc/perf/core-book3s.c val = 0; val 1617 arch/powerpc/perf/core-book3s.c val = 0x80000000L - left; val 1619 arch/powerpc/perf/core-book3s.c write_pmc(event->hw.idx, val); val 2038 arch/powerpc/perf/core-book3s.c static void record_and_restart(struct perf_event *event, unsigned long val, val 2052 arch/powerpc/perf/core-book3s.c delta = check_and_compute_delta(prev, val); val 2059 arch/powerpc/perf/core-book3s.c val = 0; val 2072 arch/powerpc/perf/core-book3s.c val = 0x80000000LL - left; val 2075 arch/powerpc/perf/core-book3s.c write_pmc(event->hw.idx, val); val 2076 arch/powerpc/perf/core-book3s.c local64_set(&event->hw.prev_count, val); val 2142 arch/powerpc/perf/core-book3s.c static bool pmc_overflow_power7(unsigned long val) val 2155 arch/powerpc/perf/core-book3s.c if ((0x80000000 - val) <= 256) val 2161 arch/powerpc/perf/core-book3s.c static bool pmc_overflow(unsigned long val) val 2163 arch/powerpc/perf/core-book3s.c if ((int)val < 0) val 2177 arch/powerpc/perf/core-book3s.c unsigned long val[8]; val 2195 arch/powerpc/perf/core-book3s.c val[i] = read_pmc(i + 1); val 2200 arch/powerpc/perf/core-book3s.c if (!pmc_overflow(val[i])) val 2215 arch/powerpc/perf/core-book3s.c record_and_restart(event, val[i], regs); val 2229 arch/powerpc/perf/core-book3s.c if (pmc_overflow_power7(val[event->hw.idx - 1])) { val 2233 arch/powerpc/perf/core-book3s.c val[event->hw.idx - 1], val 54 arch/powerpc/perf/core-fsl-emb.c unsigned long val; val 58 arch/powerpc/perf/core-fsl-emb.c val = mfpmr(PMRN_PMC0); val 61 arch/powerpc/perf/core-fsl-emb.c val = mfpmr(PMRN_PMC1); val 64 arch/powerpc/perf/core-fsl-emb.c val = mfpmr(PMRN_PMC2); val 67 arch/powerpc/perf/core-fsl-emb.c val = mfpmr(PMRN_PMC3); val 70 arch/powerpc/perf/core-fsl-emb.c val = mfpmr(PMRN_PMC4); val 73 arch/powerpc/perf/core-fsl-emb.c val = mfpmr(PMRN_PMC5); val 77 arch/powerpc/perf/core-fsl-emb.c val = 0; val 79 arch/powerpc/perf/core-fsl-emb.c return val; val 85 arch/powerpc/perf/core-fsl-emb.c static void write_pmc(int idx, unsigned long val) val 89 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMC0, val); val 92 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMC1, val); val 95 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMC2, val); val 98 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMC3, val); val 101 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMC4, val); val 104 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMC5, val); val 116 arch/powerpc/perf/core-fsl-emb.c static void write_pmlca(int idx, unsigned long val) val 120 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCA0, val); val 123 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCA1, val); val 126 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCA2, val); val 129 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCA3, val); val 132 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCA4, val); val 135 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCA5, val); val 147 arch/powerpc/perf/core-fsl-emb.c static void write_pmlcb(int idx, unsigned long val) val 151 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCB0, val); val 154 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCB1, val); val 157 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCB2, val); val 160 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCB3, val); val 163 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCB4, val); val 166 arch/powerpc/perf/core-fsl-emb.c mtpmr(PMRN_PMLCB5, val); val 177 arch/powerpc/perf/core-fsl-emb.c s64 val, delta, prev; val 190 arch/powerpc/perf/core-fsl-emb.c val = read_pmc(event->hw.idx); val 191 arch/powerpc/perf/core-fsl-emb.c } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); val 194 arch/powerpc/perf/core-fsl-emb.c delta = (val - prev) & 0xfffffffful; val 294 arch/powerpc/perf/core-fsl-emb.c u64 val; val 321 arch/powerpc/perf/core-fsl-emb.c val = 0; val 325 arch/powerpc/perf/core-fsl-emb.c val = 0x80000000L - left; val 327 arch/powerpc/perf/core-fsl-emb.c local64_set(&event->hw.prev_count, val); val 331 arch/powerpc/perf/core-fsl-emb.c val = 0; val 336 arch/powerpc/perf/core-fsl-emb.c write_pmc(i, val); val 390 arch/powerpc/perf/core-fsl-emb.c unsigned long val; val 407 arch/powerpc/perf/core-fsl-emb.c val = 0; val 409 arch/powerpc/perf/core-fsl-emb.c val = 0x80000000L - left; val 410 arch/powerpc/perf/core-fsl-emb.c write_pmc(event->hw.idx, val); val 602 arch/powerpc/perf/core-fsl-emb.c static void record_and_restart(struct perf_event *event, unsigned long val, val 616 arch/powerpc/perf/core-fsl-emb.c delta = (val - prev) & 0xfffffffful; val 623 arch/powerpc/perf/core-fsl-emb.c val = 0; val 634 arch/powerpc/perf/core-fsl-emb.c val = 0x80000000LL - left; val 637 arch/powerpc/perf/core-fsl-emb.c write_pmc(event->hw.idx, val); val 638 arch/powerpc/perf/core-fsl-emb.c local64_set(&event->hw.prev_count, val); val 660 arch/powerpc/perf/core-fsl-emb.c unsigned long val; val 673 arch/powerpc/perf/core-fsl-emb.c val = read_pmc(i); val 674 arch/powerpc/perf/core-fsl-emb.c if ((int)val < 0) { val 678 arch/powerpc/perf/core-fsl-emb.c record_and_restart(event, val, regs); val 452 arch/powerpc/perf/hv-24x7.c char *ev_name, *a_ev_name, *val; val 461 arch/powerpc/perf/hv-24x7.c val = event_fmt(event, domain); val 462 arch/powerpc/perf/hv-24x7.c if (!val) val 476 arch/powerpc/perf/hv-24x7.c attr = device_str_attr_create_(a_ev_name, val); val 484 arch/powerpc/perf/hv-24x7.c kfree(val); val 209 arch/powerpc/perf/isa207-common.c u64 val; val 213 arch/powerpc/perf/isa207-common.c dsrc->val = 0; val 218 arch/powerpc/perf/isa207-common.c val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; val 219 arch/powerpc/perf/isa207-common.c if (val == 1 || val == 2) { val 223 arch/powerpc/perf/isa207-common.c dsrc->val = isa207_find_source(idx, sub_idx); val 224 arch/powerpc/perf/isa207-common.c dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); val 234 arch/powerpc/perf/isa207-common.c u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; val 236 arch/powerpc/perf/isa207-common.c if (val == 0 || val == 7) val 369 arch/powerpc/perf/isa207-common.c unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; val 422 arch/powerpc/perf/isa207-common.c val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; val 423 arch/powerpc/perf/isa207-common.c if (val) { val 424 arch/powerpc/perf/isa207-common.c mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; val 425 arch/powerpc/perf/isa207-common.c mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; val 437 arch/powerpc/perf/isa207-common.c val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; val 438 arch/powerpc/perf/isa207-common.c mmcra |= val << MMCRA_THR_CTL_SHIFT; val 439 arch/powerpc/perf/isa207-common.c val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; val 440 arch/powerpc/perf/isa207-common.c mmcra |= val << MMCRA_THR_SEL_SHIFT; val 441 arch/powerpc/perf/isa207-common.c val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; val 442 arch/powerpc/perf/isa207-common.c mmcra |= thresh_cmp_val(val); val 446 arch/powerpc/perf/isa207-common.c val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; val 447 arch/powerpc/perf/isa207-common.c mmcra |= val << MMCRA_IFM_SHIFT; val 242 arch/powerpc/platforms/44x/fsp2.c u32 val; val 249 arch/powerpc/platforms/44x/fsp2.c val = mfdcr(DCRN_PLB6_CR0); val 250 arch/powerpc/platforms/44x/fsp2.c val |= 0x20000000; val 251 arch/powerpc/platforms/44x/fsp2.c mtdcr(DCRN_PLB6_BASE, val); val 263 arch/powerpc/platforms/44x/fsp2.c val = mfcmu(CMUN_TVS1); val 264 arch/powerpc/platforms/44x/fsp2.c val |= 0x4; val 265 arch/powerpc/platforms/44x/fsp2.c mtcmu(CMUN_TVS1, val); val 268 arch/powerpc/platforms/44x/fsp2.c val = mfcmu(CMUN_FIR0); val 269 arch/powerpc/platforms/44x/fsp2.c val |= 0x30000000; val 270 arch/powerpc/platforms/44x/fsp2.c mtcmu(CMUN_FIR0, val); val 251 arch/powerpc/platforms/44x/warp.c int val; val 253 arch/powerpc/platforms/44x/warp.c val = i2c_smbus_read_word_data(client, 0); val 254 arch/powerpc/platforms/44x/warp.c if (val < 0) val 257 arch/powerpc/platforms/44x/warp.c s16 temp = swab16(val); val 67 arch/powerpc/platforms/4xx/gpio.c __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 72 arch/powerpc/platforms/4xx/gpio.c if (val) val 79 arch/powerpc/platforms/4xx/gpio.c ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 86 arch/powerpc/platforms/4xx/gpio.c __ppc4xx_gpio_set(gc, gpio, val); val 90 arch/powerpc/platforms/4xx/gpio.c pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); val 123 arch/powerpc/platforms/4xx/gpio.c ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 133 arch/powerpc/platforms/4xx/gpio.c __ppc4xx_gpio_set(gc, gpio, val); val 152 arch/powerpc/platforms/4xx/gpio.c pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); val 39 arch/powerpc/platforms/4xx/pci.c #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) val 40 arch/powerpc/platforms/4xx/pci.c #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) val 42 arch/powerpc/platforms/4xx/pci.c #define RES_TO_U32_LOW(val) \ val 43 arch/powerpc/platforms/4xx/pci.c ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val)) val 44 arch/powerpc/platforms/4xx/pci.c #define RES_TO_U32_HIGH(val) \ val 45 arch/powerpc/platforms/4xx/pci.c ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0)) val 670 arch/powerpc/platforms/4xx/pci.c u32 val; val 673 arch/powerpc/platforms/4xx/pci.c val = mfdcri(SDR0, port->sdr_base + sdr_offset); val 674 arch/powerpc/platforms/4xx/pci.c if ((val & mask) == value) { val 676 arch/powerpc/platforms/4xx/pci.c port->index, sdr_offset, timeout_ms, val); val 845 arch/powerpc/platforms/4xx/pci.c u32 val = 1 << 24; val 848 arch/powerpc/platforms/4xx/pci.c val = PTYPE_LEGACY_ENDPOINT << 20; val 850 arch/powerpc/platforms/4xx/pci.c val = PTYPE_ROOT_PORT << 20; val 853 arch/powerpc/platforms/4xx/pci.c val |= LNKW_X8 << 12; val 855 arch/powerpc/platforms/4xx/pci.c val |= LNKW_X4 << 12; val 857 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); val 949 arch/powerpc/platforms/4xx/pci.c u32 val; val 953 arch/powerpc/platforms/4xx/pci.c val = PTYPE_LEGACY_ENDPOINT << 20; val 955 arch/powerpc/platforms/4xx/pci.c val = PTYPE_ROOT_PORT << 20; val 958 arch/powerpc/platforms/4xx/pci.c val |= LNKW_X1 << 12; val 961 arch/powerpc/platforms/4xx/pci.c val |= LNKW_X4 << 12; val 965 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); val 1060 arch/powerpc/platforms/4xx/pci.c u32 val; val 1074 arch/powerpc/platforms/4xx/pci.c val = PTYPE_LEGACY_ENDPOINT << 20; val 1076 arch/powerpc/platforms/4xx/pci.c val = PTYPE_ROOT_PORT << 20; val 1078 arch/powerpc/platforms/4xx/pci.c val |= LNKW_X1 << 12; val 1080 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); val 1097 arch/powerpc/platforms/4xx/pci.c val = PESDR0_460EX_RSTSTA - port->sdr_base; val 1098 arch/powerpc/platforms/4xx/pci.c if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) { val 1301 arch/powerpc/platforms/4xx/pci.c u32 val; val 1304 arch/powerpc/platforms/4xx/pci.c val = PTYPE_LEGACY_ENDPOINT; val 1306 arch/powerpc/platforms/4xx/pci.c val = PTYPE_ROOT_PORT; val 1309 arch/powerpc/platforms/4xx/pci.c 1 << 24 | val << 20 | LNKW_X1 << 12); val 1323 arch/powerpc/platforms/4xx/pci.c val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); val 1324 arch/powerpc/platforms/4xx/pci.c if (!(val & 0x00001000)) val 1375 arch/powerpc/platforms/4xx/pci.c u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT); val 1388 arch/powerpc/platforms/4xx/pci.c val = in_le32(mbase + PECFG_TLDLP); val 1390 arch/powerpc/platforms/4xx/pci.c if ((val & mask) == mask) val 1395 arch/powerpc/platforms/4xx/pci.c if (val & PECFG_TLDLP_PRESENT) { val 1604 arch/powerpc/platforms/4xx/pci.c int offset, int len, u32 *val) val 1632 arch/powerpc/platforms/4xx/pci.c *val = in_8((u8 *)(addr + offset)); val 1635 arch/powerpc/platforms/4xx/pci.c *val = in_le16((u16 *)(addr + offset)); val 1638 arch/powerpc/platforms/4xx/pci.c *val = in_le32((u32 *)(addr + offset)); val 1645 arch/powerpc/platforms/4xx/pci.c devfn, offset, len, addr + offset, *val); val 1652 arch/powerpc/platforms/4xx/pci.c *val = 0xffff0001; val 1661 arch/powerpc/platforms/4xx/pci.c int offset, int len, u32 val) val 1685 arch/powerpc/platforms/4xx/pci.c devfn, offset, len, addr + offset, val); val 1689 arch/powerpc/platforms/4xx/pci.c out_8((u8 *)(addr + offset), val); val 1692 arch/powerpc/platforms/4xx/pci.c out_le16((u16 *)(addr + offset), val); val 1695 arch/powerpc/platforms/4xx/pci.c out_le32((u32 *)(addr + offset), val); val 1922 arch/powerpc/platforms/4xx/pci.c u32 val; val 2029 arch/powerpc/platforms/4xx/pci.c val = *pval; val 2032 arch/powerpc/platforms/4xx/pci.c val = 0xaaa0 + port->index; val 2034 arch/powerpc/platforms/4xx/pci.c val = 0xeee0 + port->index; val 2036 arch/powerpc/platforms/4xx/pci.c out_le16(mbase + 0x200, val); val 2040 arch/powerpc/platforms/4xx/pci.c val = *pval; val 2043 arch/powerpc/platforms/4xx/pci.c val = 0xbed0 + port->index; val 2045 arch/powerpc/platforms/4xx/pci.c val = 0xfed0 + port->index; val 2047 arch/powerpc/platforms/4xx/pci.c out_le16(mbase + 0x202, val); val 288 arch/powerpc/platforms/512x/clock-commonclk.c uint32_t val; val 290 arch/powerpc/platforms/512x/clock-commonclk.c val = in_be32(reg); val 291 arch/powerpc/platforms/512x/clock-commonclk.c val >>= pos; val 292 arch/powerpc/platforms/512x/clock-commonclk.c val &= (1 << len) - 1; val 293 arch/powerpc/platforms/512x/clock-commonclk.c return val; val 366 arch/powerpc/platforms/512x/clock-commonclk.c { .val = 2, .div = 2, }, val 367 arch/powerpc/platforms/512x/clock-commonclk.c { .val = 3, .div = 3, }, val 368 arch/powerpc/platforms/512x/clock-commonclk.c { .val = 4, .div = 4, }, val 369 arch/powerpc/platforms/512x/clock-commonclk.c { .val = 6, .div = 6, }, val 375 arch/powerpc/platforms/512x/clock-commonclk.c { .val = 1, .div = 1, }, val 376 arch/powerpc/platforms/512x/clock-commonclk.c { .val = 2, .div = 2, }, val 377 arch/powerpc/platforms/512x/clock-commonclk.c { .val = 3, .div = 3, }, val 378 arch/powerpc/platforms/512x/clock-commonclk.c { .val = 4, .div = 4, }, val 386 arch/powerpc/platforms/512x/clock-commonclk.c int val; val 388 arch/powerpc/platforms/512x/clock-commonclk.c val = 0; val 393 arch/powerpc/platforms/512x/clock-commonclk.c val = *prop; val 396 arch/powerpc/platforms/512x/clock-commonclk.c return val; val 487 arch/powerpc/platforms/512x/mpc512x_shared.c int mpc512x_cs_config(unsigned int cs, u32 val) val 503 arch/powerpc/platforms/512x/mpc512x_shared.c out_be32(&lpc->cs_cfg[cs], val); val 36 arch/powerpc/platforms/52xx/efika.c int len, u32 * val) val 46 arch/powerpc/platforms/52xx/efika.c *val = ret; val 51 arch/powerpc/platforms/52xx/efika.c int offset, int len, u32 val) val 60 arch/powerpc/platforms/52xx/efika.c addr, len, val); val 50 arch/powerpc/platforms/52xx/media5200.c u32 val; val 53 arch/powerpc/platforms/52xx/media5200.c val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); val 54 arch/powerpc/platforms/52xx/media5200.c val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)); val 55 arch/powerpc/platforms/52xx/media5200.c out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); val 62 arch/powerpc/platforms/52xx/media5200.c u32 val; val 65 arch/powerpc/platforms/52xx/media5200.c val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); val 66 arch/powerpc/platforms/52xx/media5200.c val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d))); val 67 arch/powerpc/platforms/52xx/media5200.c out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); val 81 arch/powerpc/platforms/52xx/media5200.c int sub_virq, val; val 93 arch/powerpc/platforms/52xx/media5200.c val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT); val 94 arch/powerpc/platforms/52xx/media5200.c if (val) { val 95 arch/powerpc/platforms/52xx/media5200.c sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1); val 178 arch/powerpc/platforms/52xx/mpc52xx_common.c u32 val; val 198 arch/powerpc/platforms/52xx/mpc52xx_common.c val = in_be32(&mpc52xx_cdm->clk_enables); val 199 arch/powerpc/platforms/52xx/mpc52xx_common.c out_be32(&mpc52xx_cdm->clk_enables, val | mask); val 216 arch/powerpc/platforms/52xx/mpc52xx_common.c u32 val; val 229 arch/powerpc/platforms/52xx/mpc52xx_common.c val = in_be32(&mpc52xx_cdm->rstcfg); val 230 arch/powerpc/platforms/52xx/mpc52xx_common.c if (val & (1 << 5)) val 234 arch/powerpc/platforms/52xx/mpc52xx_common.c if (val & (1 << 6)) val 314 arch/powerpc/platforms/52xx/mpc52xx_gpt.c mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 316 arch/powerpc/platforms/52xx/mpc52xx_gpt.c mpc52xx_gpt_gpio_set(gc, gpio, val); val 108 arch/powerpc/platforms/52xx/mpc52xx_pci.c int offset, int len, u32 *val) val 155 arch/powerpc/platforms/52xx/mpc52xx_pci.c *val = value; val 165 arch/powerpc/platforms/52xx/mpc52xx_pci.c int offset, int len, u32 val) val 188 arch/powerpc/platforms/52xx/mpc52xx_pci.c (offset & 3), val); val 192 arch/powerpc/platforms/52xx/mpc52xx_pci.c ((offset>>1) & 1), val); val 197 arch/powerpc/platforms/52xx/mpc52xx_pci.c (u16)val); val 199 arch/powerpc/platforms/52xx/mpc52xx_pci.c (u16)(val>>16)); val 214 arch/powerpc/platforms/52xx/mpc52xx_pci.c val = value | ((val << offset) & mask); val 217 arch/powerpc/platforms/52xx/mpc52xx_pci.c out_le32(hose->cfg_data, val); val 96 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c static void mcu_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 102 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c if (val) val 111 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c static int mcu_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 113 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c mcu_gpio_set(gc, gpio, val); val 59 arch/powerpc/platforms/85xx/socrates_fpga_pic.c static inline void socrates_fpga_pic_write(int reg, uint32_t val) val 61 arch/powerpc/platforms/85xx/socrates_fpga_pic.c out_be32(socrates_fpga_pic_iobase + reg, val); val 86 arch/powerpc/platforms/85xx/tqm85xx.c unsigned int val; val 98 arch/powerpc/platforms/85xx/tqm85xx.c pci_read_config_dword(pdev, 0x80, &val); val 99 arch/powerpc/platforms/85xx/tqm85xx.c pci_write_config_dword(pdev, 0x80, val | (1 << 27)); val 160 arch/powerpc/platforms/86xx/gef_ppc9a.c unsigned int val; val 169 arch/powerpc/platforms/86xx/gef_ppc9a.c pci_read_config_dword(pdev, 0xe0, &val); val 170 arch/powerpc/platforms/86xx/gef_ppc9a.c pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5); val 147 arch/powerpc/platforms/86xx/gef_sbc310.c unsigned int val; val 156 arch/powerpc/platforms/86xx/gef_sbc310.c pci_read_config_dword(pdev, 0xe0, &val); val 157 arch/powerpc/platforms/86xx/gef_sbc310.c pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x2); val 137 arch/powerpc/platforms/86xx/gef_sbc610.c unsigned int val; val 146 arch/powerpc/platforms/86xx/gef_sbc610.c pci_read_config_dword(pdev, 0xe0, &val); val 147 arch/powerpc/platforms/86xx/gef_sbc610.c pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5); val 86 arch/powerpc/platforms/86xx/mvme7100.c unsigned int val; val 92 arch/powerpc/platforms/86xx/mvme7100.c pci_read_config_dword(pdev, 0xe0, &val); val 93 arch/powerpc/platforms/86xx/mvme7100.c pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x2); val 598 arch/powerpc/platforms/8xx/cpm1.c static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 609 arch/powerpc/platforms/8xx/cpm1.c __cpm1_gpio16_set(mm_gc, pin_mask, val); val 727 arch/powerpc/platforms/8xx/cpm1.c static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 738 arch/powerpc/platforms/8xx/cpm1.c __cpm1_gpio32_set(mm_gc, pin_mask, val); val 62 arch/powerpc/platforms/8xx/m8xx_setup.c static int __init get_freq(char *name, unsigned long *val) val 75 arch/powerpc/platforms/8xx/m8xx_setup.c *val = *fp; val 85 arch/powerpc/platforms/cell/axon_msi.c static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) val 87 arch/powerpc/platforms/cell/axon_msi.c pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); val 89 arch/powerpc/platforms/cell/axon_msi.c dcr_write(msic->dcr_host, dcr_n, val); val 449 arch/powerpc/platforms/cell/axon_msi.c static int msic_set(void *data, u64 val) val 452 arch/powerpc/platforms/cell/axon_msi.c out_le32(msic->trigger, val); val 456 arch/powerpc/platforms/cell/axon_msi.c static int msic_get(void *data, u64 *val) val 458 arch/powerpc/platforms/cell/axon_msi.c *val = 0; val 83 arch/powerpc/platforms/cell/cbe_thermal.c value.val = in_be64(®->val); val 105 arch/powerpc/platforms/cell/cbe_thermal.c value = in_be64(&pmd_regs->tm_tpr.val); val 127 arch/powerpc/platforms/cell/cbe_thermal.c reg_value = in_be64(&pmd_regs->tm_tpr.val); val 134 arch/powerpc/platforms/cell/cbe_thermal.c out_be64(&pmd_regs->tm_tpr.val, reg_value); val 322 arch/powerpc/platforms/cell/cbe_thermal.c str1.val = 0x1010101010101010ull; val 332 arch/powerpc/platforms/cell/cbe_thermal.c cr1.val = 0x0404040404040404ull; val 355 arch/powerpc/platforms/cell/cbe_thermal.c out_be64(&pmd_regs->tm_str1.val, str1.val); val 356 arch/powerpc/platforms/cell/cbe_thermal.c out_be64(&pmd_regs->tm_tpr.val, tpr.val); val 357 arch/powerpc/platforms/cell/cbe_thermal.c out_be64(&pmd_regs->tm_cr1.val, cr1.val); val 237 arch/powerpc/platforms/cell/interrupt.c const u32 *val; val 244 arch/powerpc/platforms/cell/interrupt.c val = of_get_property(ct, "#interrupt-cells", NULL); val 245 arch/powerpc/platforms/cell/interrupt.c if (val == NULL || *val != 1) val 133 arch/powerpc/platforms/cell/iommu.c u64 val; val 141 arch/powerpc/platforms/cell/iommu.c val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask) val 145 arch/powerpc/platforms/cell/iommu.c out_be64(reg, val); val 684 arch/powerpc/platforms/cell/iommu.c unsigned long base, val; val 700 arch/powerpc/platforms/cell/iommu.c val = in_be64(cregs + IOC_IOCmd_Cfg); val 701 arch/powerpc/platforms/cell/iommu.c val &= ~IOC_IOCmd_Cfg_TE; val 702 arch/powerpc/platforms/cell/iommu.c out_be64(cregs + IOC_IOCmd_Cfg, val); val 42 arch/powerpc/platforms/cell/pmu.c #define READ_SHADOW_REG(val, reg) \ val 46 arch/powerpc/platforms/cell/pmu.c (val) = shadow_regs->reg; \ val 49 arch/powerpc/platforms/cell/pmu.c #define READ_MMIO_UPPER32(val, reg) \ val 53 arch/powerpc/platforms/cell/pmu.c (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \ val 63 arch/powerpc/platforms/cell/pmu.c u32 val_in_latch, val = 0; val 70 arch/powerpc/platforms/cell/pmu.c READ_SHADOW_REG(val, pm_ctr[phys_ctr]); val 72 arch/powerpc/platforms/cell/pmu.c READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]); val 76 arch/powerpc/platforms/cell/pmu.c return val; val 80 arch/powerpc/platforms/cell/pmu.c void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val) val 90 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(pm_ctr[phys_ctr], val); val 115 arch/powerpc/platforms/cell/pmu.c u32 val; val 118 arch/powerpc/platforms/cell/pmu.c val = cbe_read_phys_ctr(cpu, phys_ctr); val 121 arch/powerpc/platforms/cell/pmu.c val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff); val 123 arch/powerpc/platforms/cell/pmu.c return val; val 127 arch/powerpc/platforms/cell/pmu.c void cbe_write_ctr(u32 cpu, u32 ctr, u32 val) val 138 arch/powerpc/platforms/cell/pmu.c val = (val << 16) | (phys_val & 0xffff); val 140 arch/powerpc/platforms/cell/pmu.c val = (val & 0xffff) | (phys_val & 0xffff0000); val 143 arch/powerpc/platforms/cell/pmu.c cbe_write_phys_ctr(cpu, phys_ctr, val); val 163 arch/powerpc/platforms/cell/pmu.c void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val) val 166 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(pm07_control[ctr], val); val 176 arch/powerpc/platforms/cell/pmu.c u32 val = 0; val 180 arch/powerpc/platforms/cell/pmu.c READ_SHADOW_REG(val, group_control); val 184 arch/powerpc/platforms/cell/pmu.c READ_SHADOW_REG(val, debug_bus_control); val 188 arch/powerpc/platforms/cell/pmu.c READ_MMIO_UPPER32(val, trace_address); val 192 arch/powerpc/platforms/cell/pmu.c READ_SHADOW_REG(val, ext_tr_timer); val 196 arch/powerpc/platforms/cell/pmu.c READ_MMIO_UPPER32(val, pm_status); val 200 arch/powerpc/platforms/cell/pmu.c READ_SHADOW_REG(val, pm_control); val 204 arch/powerpc/platforms/cell/pmu.c READ_MMIO_UPPER32(val, pm_interval); val 208 arch/powerpc/platforms/cell/pmu.c READ_SHADOW_REG(val, pm_start_stop); val 212 arch/powerpc/platforms/cell/pmu.c return val; val 216 arch/powerpc/platforms/cell/pmu.c void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val) val 220 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(group_control, val); val 224 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(debug_bus_control, val); val 228 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(trace_address, val); val 232 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(ext_tr_timer, val); val 236 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(pm_status, val); val 240 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(pm_control, val); val 244 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(pm_interval, val); val 248 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(pm_start_stop, val); val 28 arch/powerpc/platforms/cell/spider-pci.c u32 val; val 31 arch/powerpc/platforms/cell/spider-pci.c val = in_be32(priv->regs + SPIDER_PCI_DUMMY_READ); val 38 arch/powerpc/platforms/cell/spider-pci.c ret val = __do_##name(addr); \ val 40 arch/powerpc/platforms/cell/spider-pci.c return val; \ val 76 arch/powerpc/platforms/cell/spider-pci.c u32 val = in_be32(regs + SPIDER_PCI_VCI_CNTL_STAT); val 77 arch/powerpc/platforms/cell/spider-pci.c pr_debug("SPIDER_IOWA:PVCI_Control_Status was 0x%08x\n", val); val 78 arch/powerpc/platforms/cell/spider-pci.c out_be32(regs + SPIDER_PCI_VCI_CNTL_STAT, val | 0x8); val 204 arch/powerpc/platforms/cell/spufs/backing_ops.c static void spu_backing_signal1_type_set(struct spu_context *ctx, u64 val) val 210 arch/powerpc/platforms/cell/spufs/backing_ops.c if (val) val 223 arch/powerpc/platforms/cell/spufs/backing_ops.c static void spu_backing_signal2_type_set(struct spu_context *ctx, u64 val) val 229 arch/powerpc/platforms/cell/spufs/backing_ops.c if (val) val 247 arch/powerpc/platforms/cell/spufs/backing_ops.c static void spu_backing_npc_write(struct spu_context *ctx, u32 val) val 249 arch/powerpc/platforms/cell/spufs/backing_ops.c ctx->csa.prob.spu_npc_RW = val; val 262 arch/powerpc/platforms/cell/spufs/backing_ops.c static void spu_backing_privcntl_write(struct spu_context *ctx, u64 val) val 264 arch/powerpc/platforms/cell/spufs/backing_ops.c ctx->csa.priv2.spu_privcntl_RW = val; val 272 arch/powerpc/platforms/cell/spufs/backing_ops.c static void spu_backing_runcntl_write(struct spu_context *ctx, u32 val) val 275 arch/powerpc/platforms/cell/spufs/backing_ops.c ctx->csa.prob.spu_runcntl_RW = val; val 276 arch/powerpc/platforms/cell/spufs/backing_ops.c if (val & SPU_RUNCNTL_RUNNABLE) { val 87 arch/powerpc/platforms/cell/spufs/file.c u64 val; val 88 arch/powerpc/platforms/cell/spufs/file.c ret = attr->get(attr->data, &val); val 93 arch/powerpc/platforms/cell/spufs/file.c attr->fmt, (unsigned long long)val); val 106 arch/powerpc/platforms/cell/spufs/file.c u64 val; val 125 arch/powerpc/platforms/cell/spufs/file.c val = simple_strtol(attr->set_buf, NULL, 0); val 126 arch/powerpc/platforms/cell/spufs/file.c attr->set(attr->data, val); val 387 arch/powerpc/platforms/cell/spufs/file.c static int spufs_cntl_get(void *data, u64 *val) val 395 arch/powerpc/platforms/cell/spufs/file.c *val = ctx->ops->status_read(ctx); val 401 arch/powerpc/platforms/cell/spufs/file.c static int spufs_cntl_set(void *data, u64 val) val 409 arch/powerpc/platforms/cell/spufs/file.c ctx->ops->runcntl_write(ctx, val); val 1232 arch/powerpc/platforms/cell/spufs/file.c static int __##__get(void *data, u64 *val) \ val 1241 arch/powerpc/platforms/cell/spufs/file.c *val = __get(ctx); \ val 1247 arch/powerpc/platforms/cell/spufs/file.c *val = __get(ctx); \ val 1250 arch/powerpc/platforms/cell/spufs/file.c *val = __get(ctx); \ val 1256 arch/powerpc/platforms/cell/spufs/file.c static int spufs_signal1_type_set(void *data, u64 val) val 1264 arch/powerpc/platforms/cell/spufs/file.c ctx->ops->signal1_type_set(ctx, val); val 1278 arch/powerpc/platforms/cell/spufs/file.c static int spufs_signal2_type_set(void *data, u64 val) val 1286 arch/powerpc/platforms/cell/spufs/file.c ctx->ops->signal2_type_set(ctx, val); val 1763 arch/powerpc/platforms/cell/spufs/file.c static int spufs_npc_set(void *data, u64 val) val 1771 arch/powerpc/platforms/cell/spufs/file.c ctx->ops->npc_write(ctx, val); val 1784 arch/powerpc/platforms/cell/spufs/file.c static int spufs_decr_set(void *data, u64 val) val 1793 arch/powerpc/platforms/cell/spufs/file.c lscsa->decr.slot[0] = (u32) val; val 1807 arch/powerpc/platforms/cell/spufs/file.c static int spufs_decr_status_set(void *data, u64 val) val 1815 arch/powerpc/platforms/cell/spufs/file.c if (val) val 1835 arch/powerpc/platforms/cell/spufs/file.c static int spufs_event_mask_set(void *data, u64 val) val 1844 arch/powerpc/platforms/cell/spufs/file.c lscsa->event_mask.slot[0] = (u32) val; val 1872 arch/powerpc/platforms/cell/spufs/file.c static int spufs_srr0_set(void *data, u64 val) val 1881 arch/powerpc/platforms/cell/spufs/file.c lscsa->srr0.slot[0] = (u32) val; val 2372 arch/powerpc/platforms/cell/spufs/file.c (unsigned int) p->val, val 2482 arch/powerpc/platforms/cell/spufs/file.c u32 type, u32 val) val 2495 arch/powerpc/platforms/cell/spufs/file.c p->val = val; val 134 arch/powerpc/platforms/cell/spufs/hw_ops.c static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val) val 142 arch/powerpc/platforms/cell/spufs/hw_ops.c if (val) val 155 arch/powerpc/platforms/cell/spufs/hw_ops.c static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val) val 163 arch/powerpc/platforms/cell/spufs/hw_ops.c if (val) val 181 arch/powerpc/platforms/cell/spufs/hw_ops.c static void spu_hw_npc_write(struct spu_context *ctx, u32 val) val 183 arch/powerpc/platforms/cell/spufs/hw_ops.c out_be32(&ctx->spu->problem->spu_npc_RW, val); val 196 arch/powerpc/platforms/cell/spufs/hw_ops.c static void spu_hw_privcntl_write(struct spu_context *ctx, u64 val) val 198 arch/powerpc/platforms/cell/spufs/hw_ops.c out_be64(&ctx->spu->priv2->spu_privcntl_RW, val); val 206 arch/powerpc/platforms/cell/spufs/hw_ops.c static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val) val 209 arch/powerpc/platforms/cell/spufs/hw_ops.c if (val & SPU_RUNCNTL_ISOLATE) val 212 arch/powerpc/platforms/cell/spufs/hw_ops.c out_be32(&ctx->spu->problem->spu_runcntl_RW, val); val 62 arch/powerpc/platforms/cell/spufs/spufs.h u32 val; val 182 arch/powerpc/platforms/cell/spufs/spufs.h void (*signal1_type_set) (struct spu_context * ctx, u64 val); val 184 arch/powerpc/platforms/cell/spufs/spufs.h void (*signal2_type_set) (struct spu_context * ctx, u64 val); val 286 arch/powerpc/platforms/cell/spufs/spufs.h u32 type, u32 val); val 44 arch/powerpc/platforms/chrp/nvram.c static void chrp_nvram_write_val(int addr, unsigned char val) val 55 arch/powerpc/platforms/chrp/nvram.c nvram_buf[0] = val; val 58 arch/powerpc/platforms/chrp/nvram.c printk(KERN_DEBUG "rtas IO error storing 0x%02x at %d", val, addr); val 35 arch/powerpc/platforms/chrp/pci.c int len, u32 *val) val 49 arch/powerpc/platforms/chrp/pci.c *val = in_8(cfg_data); val 52 arch/powerpc/platforms/chrp/pci.c *val = in_le16(cfg_data); val 55 arch/powerpc/platforms/chrp/pci.c *val = in_le32(cfg_data); val 62 arch/powerpc/platforms/chrp/pci.c int len, u32 val) val 76 arch/powerpc/platforms/chrp/pci.c out_8(cfg_data, val); val 79 arch/powerpc/platforms/chrp/pci.c out_le16(cfg_data, val); val 82 arch/powerpc/platforms/chrp/pci.c out_le32(cfg_data, val); val 98 arch/powerpc/platforms/chrp/pci.c int len, u32 *val) val 108 arch/powerpc/platforms/chrp/pci.c *val = ret; val 113 arch/powerpc/platforms/chrp/pci.c int len, u32 val) val 122 arch/powerpc/platforms/chrp/pci.c addr, len, val); val 168 arch/powerpc/platforms/chrp/pci.c u32 val; val 179 arch/powerpc/platforms/chrp/pci.c val = in_be32(®[12]); val 180 arch/powerpc/platforms/chrp/pci.c if (val & PRG_CL_RESET_VALID) { val 181 arch/powerpc/platforms/chrp/pci.c out_be32(®[12], val & ~PRG_CL_RESET_VALID); val 111 arch/powerpc/platforms/chrp/pegasos_eth.c #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); } val 163 arch/powerpc/platforms/chrp/setup.c static inline void __init sio_write(u8 val, u8 index) val 166 arch/powerpc/platforms/chrp/setup.c outb(val, 0x15d); val 76 arch/powerpc/platforms/chrp/time.c static void chrp_cmos_clock_write(unsigned long val, int addr) val 81 arch/powerpc/platforms/chrp/time.c outb(val, nvram_data); val 94 arch/powerpc/platforms/fsl_uli1575.c u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4); val 95 arch/powerpc/platforms/fsl_uli1575.c pci_write_config_byte(dev, 0x48 + i, val); val 118 arch/powerpc/platforms/maple/pci.c int offset, int len, u32 *val) val 136 arch/powerpc/platforms/maple/pci.c *val = in_8(addr); val 139 arch/powerpc/platforms/maple/pci.c *val = in_le16(addr); val 142 arch/powerpc/platforms/maple/pci.c *val = in_le32(addr); val 149 arch/powerpc/platforms/maple/pci.c int offset, int len, u32 val) val 167 arch/powerpc/platforms/maple/pci.c out_8(addr, val); val 170 arch/powerpc/platforms/maple/pci.c out_le16(addr, val); val 173 arch/powerpc/platforms/maple/pci.c out_le32(addr, val); val 207 arch/powerpc/platforms/maple/pci.c int len, u32 *val) val 216 arch/powerpc/platforms/maple/pci.c *val = in_8(addr); val 219 arch/powerpc/platforms/maple/pci.c *val = in_be16(addr); val 222 arch/powerpc/platforms/maple/pci.c *val = in_be32(addr); val 230 arch/powerpc/platforms/maple/pci.c int len, u32 val) val 241 arch/powerpc/platforms/maple/pci.c out_8(addr, val); val 244 arch/powerpc/platforms/maple/pci.c out_be16(addr, val); val 247 arch/powerpc/platforms/maple/pci.c out_be32(addr, val); val 255 arch/powerpc/platforms/maple/pci.c int offset, int len, u32 *val) val 265 arch/powerpc/platforms/maple/pci.c return u3_ht_root_read_config(hose, offset, len, val); val 280 arch/powerpc/platforms/maple/pci.c *val = in_8(addr); val 283 arch/powerpc/platforms/maple/pci.c *val = in_le16(addr); val 286 arch/powerpc/platforms/maple/pci.c *val = in_le32(addr); val 293 arch/powerpc/platforms/maple/pci.c int offset, int len, u32 val) val 303 arch/powerpc/platforms/maple/pci.c return u3_ht_root_write_config(hose, offset, len, val); val 317 arch/powerpc/platforms/maple/pci.c out_8(addr, val); val 320 arch/powerpc/platforms/maple/pci.c out_le16(addr, val); val 323 arch/powerpc/platforms/maple/pci.c out_le32(addr, val); val 372 arch/powerpc/platforms/maple/pci.c int offset, int len, u32 *val) val 391 arch/powerpc/platforms/maple/pci.c *val = in_8(addr); val 394 arch/powerpc/platforms/maple/pci.c *val = in_le16(addr); val 397 arch/powerpc/platforms/maple/pci.c *val = in_le32(addr); val 403 arch/powerpc/platforms/maple/pci.c int offset, int len, u32 val) val 422 arch/powerpc/platforms/maple/pci.c out_8(addr, val); val 425 arch/powerpc/platforms/maple/pci.c out_le16(addr, val); val 428 arch/powerpc/platforms/maple/pci.c out_le32(addr, val); val 46 arch/powerpc/platforms/maple/time.c static void maple_clock_write(unsigned long val, int addr) val 49 arch/powerpc/platforms/maple/time.c outb_p(val, maple_rtc_addr+1); val 54 arch/powerpc/platforms/pasemi/dma_lib.c void pasemi_write_iob_reg(unsigned int reg, unsigned int val) val 56 arch/powerpc/platforms/pasemi/dma_lib.c out_le32(iob_regs+reg, val); val 75 arch/powerpc/platforms/pasemi/dma_lib.c void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val) val 77 arch/powerpc/platforms/pasemi/dma_lib.c out_le32(mac_regs[intf]+reg, val); val 94 arch/powerpc/platforms/pasemi/dma_lib.c void pasemi_write_dma_reg(unsigned int reg, unsigned int val) val 96 arch/powerpc/platforms/pasemi/dma_lib.c out_le32(dma_regs+reg, val); val 154 arch/powerpc/platforms/pasemi/gpio_mdio.c static int gpio_mdio_write(struct mii_bus *bus, int phy_id, int location, u16 val) val 160 arch/powerpc/platforms/pasemi/gpio_mdio.c u16 value = val & 0xffff; val 58 arch/powerpc/platforms/pasemi/pci.c int offset, int len, u32 *val) val 84 arch/powerpc/platforms/pasemi/pci.c *val = (tmp >> (8*byte)) & 0xff; val 88 arch/powerpc/platforms/pasemi/pci.c *val = tmp & 0xffff; val 90 arch/powerpc/platforms/pasemi/pci.c *val = (tmp >> 16) & 0xffff; val 93 arch/powerpc/platforms/pasemi/pci.c *val = tmp; val 156 arch/powerpc/platforms/pasemi/pci.c int offset, int len, u32 *val) val 168 arch/powerpc/platforms/pasemi/pci.c if (workaround_5945(bus, devfn, offset, len, val)) val 181 arch/powerpc/platforms/pasemi/pci.c *val = in_8(addr); val 184 arch/powerpc/platforms/pasemi/pci.c *val = in_le16(addr); val 187 arch/powerpc/platforms/pasemi/pci.c *val = in_le32(addr); val 195 arch/powerpc/platforms/pasemi/pci.c int offset, int len, u32 val) val 217 arch/powerpc/platforms/pasemi/pci.c out_8(addr, val); val 220 arch/powerpc/platforms/pasemi/pci.c out_le16(addr, val); val 223 arch/powerpc/platforms/pasemi/pci.c out_le32(addr, val); val 160 arch/powerpc/platforms/powermac/bootx_init.c u32 val; val 170 arch/powerpc/platforms/powermac/bootx_init.c val = ((unsigned long)bootx_info) + bootx_info->ramDisk; val 171 arch/powerpc/platforms/powermac/bootx_init.c bootx_dt_add_prop("linux,initrd-start", &val, 4, mem_end); val 172 arch/powerpc/platforms/powermac/bootx_init.c val += bootx_info->ramDiskSize; val 173 arch/powerpc/platforms/powermac/bootx_init.c bootx_dt_add_prop("linux,initrd-end", &val, 4, mem_end); val 200 arch/powerpc/platforms/powermac/low_i2c.c reg_t reg, u8 val) val 202 arch/powerpc/platforms/powermac/low_i2c.c writeb(val, host->base + (((unsigned)reg) << host->bsteps)); val 206 arch/powerpc/platforms/powermac/low_i2c.c #define kw_write_reg(reg, val) __kw_write_reg(host, reg, val) val 1297 arch/powerpc/platforms/powermac/low_i2c.c u32 len, const u8 *mask, const u8 *val) val 1303 arch/powerpc/platforms/powermac/low_i2c.c inst->scratch[i] = (inst->buffer[i] & mask[i]) | val[i]; val 1307 arch/powerpc/platforms/powermac/low_i2c.c | (val[i] & mask[i]); val 92 arch/powerpc/platforms/powermac/nvram.c static void core99_nvram_write_byte(int addr, unsigned char val) val 96 arch/powerpc/platforms/powermac/nvram.c nvram_image[addr] = val; val 156 arch/powerpc/platforms/powermac/nvram.c static void direct_nvram_write_byte(int addr, unsigned char val) val 158 arch/powerpc/platforms/powermac/nvram.c out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val); val 164 arch/powerpc/platforms/powermac/nvram.c unsigned char val; val 169 arch/powerpc/platforms/powermac/nvram.c val = in_8(&nvram_data[(addr & 0x1f) << 4]); val 172 arch/powerpc/platforms/powermac/nvram.c return val; val 175 arch/powerpc/platforms/powermac/nvram.c static void indirect_nvram_write_byte(int addr, unsigned char val) val 181 arch/powerpc/platforms/powermac/nvram.c out_8(&nvram_data[(addr & 0x1f) << 4], val); val 210 arch/powerpc/platforms/powermac/nvram.c static void pmu_nvram_write_byte(int addr, unsigned char val) val 217 arch/powerpc/platforms/powermac/nvram.c (addr >> 8) & 0xff, addr & 0xff, val)) val 283 arch/powerpc/platforms/powermac/pci.c int offset, int len, u32 *val) val 304 arch/powerpc/platforms/powermac/pci.c *val = 0xff; break; val 306 arch/powerpc/platforms/powermac/pci.c *val = 0xffff; break; val 308 arch/powerpc/platforms/powermac/pci.c *val = 0xfffffffful; break; val 321 arch/powerpc/platforms/powermac/pci.c *val = in_8(addr); val 324 arch/powerpc/platforms/powermac/pci.c *val = swap ? in_le16(addr) : in_be16(addr); val 327 arch/powerpc/platforms/powermac/pci.c *val = swap ? in_le32(addr) : in_be32(addr); val 334 arch/powerpc/platforms/powermac/pci.c int offset, int len, u32 val) val 364 arch/powerpc/platforms/powermac/pci.c out_8(addr, val); val 367 arch/powerpc/platforms/powermac/pci.c swap ? out_le16(addr, val) : out_be16(addr, val); val 370 arch/powerpc/platforms/powermac/pci.c swap ? out_le32(addr, val) : out_be32(addr, val); val 495 arch/powerpc/platforms/powermac/pci.c u16 val; val 515 arch/powerpc/platforms/powermac/pci.c PCI_BRIDGE_CONTROL, &val) < 0) { val 520 arch/powerpc/platforms/powermac/pci.c val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; val 521 arch/powerpc/platforms/powermac/pci.c early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); val 1061 arch/powerpc/platforms/powermac/pci.c u8 val; val 1063 arch/powerpc/platforms/powermac/pci.c if (pci_read_config_byte(dev, 0x91, &val) == 0) val 1064 arch/powerpc/platforms/powermac/pci.c pci_write_config_byte(dev, 0x91, val | 0x30); val 1066 arch/powerpc/platforms/powermac/pci.c if (pci_read_config_byte(dev, 0x92, &val) == 0) val 1067 arch/powerpc/platforms/powermac/pci.c pci_write_config_byte(dev, 0x92, val & ~0x06); val 1073 arch/powerpc/platforms/powermac/pci.c u8 val; val 1076 arch/powerpc/platforms/powermac/pci.c if (pci_read_config_byte(dev, 0x8c, &val) == 0) val 1077 arch/powerpc/platforms/powermac/pci.c pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); val 1079 arch/powerpc/platforms/powermac/pci.c if (pci_read_config_byte(dev, 0x92, &val) == 0) val 1080 arch/powerpc/platforms/powermac/pci.c pci_write_config_byte(dev, 0x92, val & ~0x06); val 221 arch/powerpc/platforms/powermac/pfunc_base.c u32 tmp, val; val 229 arch/powerpc/platforms/powermac/pfunc_base.c val = args->u[0].v << shift; val 230 arch/powerpc/platforms/powermac/pfunc_base.c tmp = (tmp & ~mask) | (val & mask); val 241 arch/powerpc/platforms/powermac/pfunc_base.c u32 tmp, val; val 249 arch/powerpc/platforms/powermac/pfunc_base.c val = args->u[0].v << shift; val 250 arch/powerpc/platforms/powermac/pfunc_base.c tmp = (tmp & ~mask) | (val & mask); val 28 arch/powerpc/platforms/powermac/pmac.h extern void pmac_nvram_write_byte(int addr, unsigned char val); val 160 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) val 165 arch/powerpc/platforms/powernv/eeh-powernv.c out_be64(phb->regs + offset, val); val 169 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) val 174 arch/powerpc/platforms/powernv/eeh-powernv.c *val = in_be64(phb->regs + offset); val 179 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ val 181 arch/powerpc/platforms/powernv/eeh-powernv.c return pnv_eeh_dbgfs_set(data, reg, val); \ val 184 arch/powerpc/platforms/powernv/eeh-powernv.c static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ val 186 arch/powerpc/platforms/powernv/eeh-powernv.c return pnv_eeh_dbgfs_get(data, reg, val); \ val 1274 arch/powerpc/platforms/powernv/eeh-powernv.c int where, int size, u32 *val) val 1280 arch/powerpc/platforms/powernv/eeh-powernv.c *val = 0xFFFFFFFF; val 1284 arch/powerpc/platforms/powernv/eeh-powernv.c return pnv_pci_cfg_read(pdn, where, size, val); val 1288 arch/powerpc/platforms/powernv/eeh-powernv.c int where, int size, u32 val) val 1296 arch/powerpc/platforms/powernv/eeh-powernv.c return pnv_pci_cfg_write(pdn, where, size, val); val 179 arch/powerpc/platforms/powernv/idle.c u8 val; val 181 arch/powerpc/platforms/powernv/idle.c if (kstrtou8(buf, 0, &val) || val != 1) val 269 arch/powerpc/platforms/powernv/memtrace.c static int memtrace_enable_set(void *data, u64 val) val 278 arch/powerpc/platforms/powernv/memtrace.c if (val & (bytes - 1)) { val 289 arch/powerpc/platforms/powernv/memtrace.c if (!val) val 293 arch/powerpc/platforms/powernv/memtrace.c if (memtrace_init_regions_runtime(val)) val 299 arch/powerpc/platforms/powernv/memtrace.c memtrace_size = val; val 304 arch/powerpc/platforms/powernv/memtrace.c static int memtrace_enable_get(void *data, u64 *val) val 306 arch/powerpc/platforms/powernv/memtrace.c *val = memtrace_size; val 109 arch/powerpc/platforms/powernv/ocxl.c u32 val; val 115 arch/powerpc/platforms/powernv/ocxl.c pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val); val 116 arch/powerpc/platforms/powernv/ocxl.c if (val & AFU_PRESENT) val 117 arch/powerpc/platforms/powernv/ocxl.c *afu_idx = (val & AFU_INDEX_MASK) >> AFU_INDEX_SHIFT; val 130 arch/powerpc/platforms/powernv/opal-fadump.h u64 val; val 137 arch/powerpc/platforms/powernv/opal-fadump.h val = (cpu_endian ? be64_to_cpu(reg_entry->reg_val) : val 142 arch/powerpc/platforms/powernv/opal-fadump.h val); val 25 arch/powerpc/platforms/powernv/opal-imc.c static int imc_mem_get(void *data, u64 *val) val 27 arch/powerpc/platforms/powernv/opal-imc.c *val = cpu_to_be64(*(u64 *)data); val 31 arch/powerpc/platforms/powernv/opal-imc.c static int imc_mem_set(void *data, u64 val) val 33 arch/powerpc/platforms/powernv/opal-imc.c *(u64 *)data = cpu_to_be64(val); val 73 arch/powerpc/platforms/powernv/opal-lpc.c static void opal_lpc_outb(u8 val, unsigned long port) val 77 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 1); val 80 arch/powerpc/platforms/powernv/opal-lpc.c static void __opal_lpc_outw(__le16 val, unsigned long port) val 85 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_outb(val >> 8, port); val 86 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_outb(val , port + 1); val 89 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 2); val 92 arch/powerpc/platforms/powernv/opal-lpc.c static void opal_lpc_outw(u16 val, unsigned long port) val 94 arch/powerpc/platforms/powernv/opal-lpc.c __opal_lpc_outw(cpu_to_le16(val), port); val 97 arch/powerpc/platforms/powernv/opal-lpc.c static void __opal_lpc_outl(__le32 val, unsigned long port) val 102 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_outb(val >> 24, port); val 103 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_outb(val >> 16, port + 1); val 104 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_outb(val >> 8, port + 2); val 105 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_outb(val , port + 3); val 108 arch/powerpc/platforms/powernv/opal-lpc.c opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 4); val 111 arch/powerpc/platforms/powernv/opal-lpc.c static void opal_lpc_outl(u32 val, unsigned long port) val 113 arch/powerpc/platforms/powernv/opal-lpc.c __opal_lpc_outl(cpu_to_le32(val), port); val 94 arch/powerpc/platforms/powernv/opal-xscom.c u64 reg, reg_base, reg_cnt, val; val 103 arch/powerpc/platforms/powernv/opal-xscom.c rc = opal_scom_read(ent->chip, reg_base, reg, &val); val 105 arch/powerpc/platforms/powernv/opal-xscom.c rc = put_user(val, ubuf64); val 125 arch/powerpc/platforms/powernv/opal-xscom.c u64 reg, reg_base, reg_cnt, val; val 134 arch/powerpc/platforms/powernv/opal-xscom.c rc = get_user(val, ubuf64); val 136 arch/powerpc/platforms/powernv/opal-xscom.c rc = opal_scom_write(ent->chip, reg_base, reg, val); val 1988 arch/powerpc/platforms/powernv/pci-ioda.c const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; val 1992 arch/powerpc/platforms/powernv/pci-ioda.c __raw_rm_writeq_be(val, invalidate); val 1994 arch/powerpc/platforms/powernv/pci-ioda.c __raw_writeq_be(val, invalidate); val 2001 arch/powerpc/platforms/powernv/pci-ioda.c unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); val 2004 arch/powerpc/platforms/powernv/pci-ioda.c __raw_writeq_be(val, invalidate); val 2689 arch/powerpc/platforms/powernv/pci-ioda.c u32 val; val 2703 arch/powerpc/platforms/powernv/pci-ioda.c i, &val); val 2705 arch/powerpc/platforms/powernv/pci-ioda.c mask |= 1ULL << val; val 3095 arch/powerpc/platforms/powernv/pci-ioda.c static int pnv_pci_diag_data_set(void *data, u64 val) val 3101 arch/powerpc/platforms/powernv/pci-ioda.c if (val != 1ULL) val 652 arch/powerpc/platforms/powernv/pci.c int where, int size, u32 *val) val 662 arch/powerpc/platforms/powernv/pci.c *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; val 669 arch/powerpc/platforms/powernv/pci.c *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; val 675 arch/powerpc/platforms/powernv/pci.c *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; val 683 arch/powerpc/platforms/powernv/pci.c __func__, pdn->busno, pdn->devfn, where, size, *val); val 688 arch/powerpc/platforms/powernv/pci.c int where, int size, u32 val) val 694 arch/powerpc/platforms/powernv/pci.c __func__, pdn->busno, pdn->devfn, where, size, val); val 697 arch/powerpc/platforms/powernv/pci.c opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); val 700 arch/powerpc/platforms/powernv/pci.c opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); val 703 arch/powerpc/platforms/powernv/pci.c opal_pci_config_write_word(phb->opal_id, bdfn, where, val); val 744 arch/powerpc/platforms/powernv/pci.c int where, int size, u32 *val) val 750 arch/powerpc/platforms/powernv/pci.c *val = 0xFFFFFFFF; val 758 arch/powerpc/platforms/powernv/pci.c ret = pnv_pci_cfg_read(pdn, where, size, val); val 761 arch/powerpc/platforms/powernv/pci.c if (*val == EEH_IO_ERROR_VALUE(size) && val 773 arch/powerpc/platforms/powernv/pci.c int where, int size, u32 val) val 786 arch/powerpc/platforms/powernv/pci.c ret = pnv_pci_cfg_write(pdn, where, size, val); val 852 arch/powerpc/platforms/powernv/pci.c __be64 val; val 867 arch/powerpc/platforms/powernv/pci.c rc = opal_pci_get_pbcq_tunnel_bar(phb->opal_id, &val); val 872 arch/powerpc/platforms/powernv/pci.c tunnel_bar = be64_to_cpu(val); val 179 arch/powerpc/platforms/powernv/pci.h int where, int size, u32 *val); val 181 arch/powerpc/platforms/powernv/pci.h int where, int size, u32 val); val 41 arch/powerpc/platforms/powernv/rng.c static unsigned long rng_whiten(struct powernv_rng *rng, unsigned long val) val 46 arch/powerpc/platforms/powernv/rng.c asm ("popcntd %0,%1" : "=r" (parity) : "r" (val)); val 49 arch/powerpc/platforms/powernv/rng.c val ^= rng->mask; val 54 arch/powerpc/platforms/powernv/rng.c return val; val 70 arch/powerpc/platforms/powernv/rng.c unsigned long val; val 73 arch/powerpc/platforms/powernv/rng.c asm volatile(PPC_DARN(%0, 1) : "=r"(val)); val 75 arch/powerpc/platforms/powernv/rng.c if (val == DARN_ERR) val 78 arch/powerpc/platforms/powernv/rng.c *v = val; val 85 arch/powerpc/platforms/powernv/rng.c unsigned long val; val 92 arch/powerpc/platforms/powernv/rng.c if (powernv_get_random_darn(&val)) { val 138 arch/powerpc/platforms/powernv/rng.c unsigned long val; val 157 arch/powerpc/platforms/powernv/rng.c val = in_be64(rng->regs); val 158 arch/powerpc/platforms/powernv/rng.c rng->mask = val; val 368 arch/powerpc/platforms/powernv/subcore.c unsigned long val; val 373 arch/powerpc/platforms/powernv/subcore.c rc = sscanf(buf, "%lx", &val); val 377 arch/powerpc/platforms/powernv/subcore.c switch (val) { val 381 arch/powerpc/platforms/powernv/subcore.c if (subcores_per_core == val) val 389 arch/powerpc/platforms/powernv/subcore.c rc = set_subcores_per_core(val); val 273 arch/powerpc/platforms/powernv/vas-window.c u64 lpcr, val; val 279 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 280 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_MSR_HV, val, 1); val 281 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_MSR_SF, val, 1); val 283 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_MSR_DR, val, 1); val 284 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_MSR_PR, val, 1); val 286 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(XLATE_MSR), val); val 289 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 297 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_LPCR_PAGE_SIZE, val, 5); val 298 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL); val 299 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_LPCR_TC, val, lpcr & LPCR_TC); val 300 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_LPCR_SC, val, 0); val 301 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(XLATE_LPCR), val); val 310 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 311 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_XLATE_MODE, val, radix_enabled() ? 3 : 2); val 312 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(XLATE_CTL), val); val 317 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 318 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_AMR, val, mfspr(SPRN_AMR)); val 319 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(AMR), val); val 321 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 322 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_SEIDR, val, 0); val 323 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(SEIDR), val); val 360 arch/powerpc/platforms/powernv/vas-window.c u64 val; val 365 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 366 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LPID, val, winctx->lpid); val 367 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LPID), val); val 369 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 370 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_PID_ID, val, winctx->pidr); val 371 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(PID), val); val 375 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 376 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_FAULT_TX_WIN, val, 0); val 377 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(FAULT_TX_WIN), val); val 382 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 383 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_HV_INTR_SRC_RA, val, winctx->irq_port); val 384 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), val); val 386 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 387 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_PSWID_EA_HANDLE, val, winctx->pswid); val 388 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(PSWID), val); val 403 arch/powerpc/platforms/powernv/vas-window.c val = __pa(winctx->rx_fifo); val 404 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_PAGE_MIGRATION_SELECT, val, 0); val 405 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LFIFO_BAR), val); val 407 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 408 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LDATA_STAMP, val, winctx->data_stamp); val 409 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), val); val 411 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 412 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LDMA_TYPE, val, winctx->dma_type); val 413 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LDMA_FIFO_DISABLE, val, winctx->fifo_disable); val 414 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), val); val 420 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 421 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LRX_WCRED, val, winctx->wcreds_max); val 422 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LRX_WCRED), val); val 424 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 425 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_TX_WCRED, val, winctx->wcreds_max); val 426 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(TX_WCRED), val); val 433 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 434 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LFIFO_SIZE, val, ilog2(fifo_size)); val 435 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LFIFO_SIZE), val); val 447 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 448 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LRX_WIN_ID, val, winctx->rx_win_id); val 449 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), val); val 453 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 454 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_NOTIFY_DISABLE, val, winctx->notify_disable); val 455 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_INTR_DISABLE, val, winctx->intr_disable); val 456 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_NOTIFY_EARLY, val, winctx->notify_early); val 457 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_NOTIFY_OSU_INTR, val, winctx->notify_os_intr_reg); val 458 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LNOTIFY_CTL), val); val 460 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 461 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LNOTIFY_PID, val, winctx->lnotify_pid); val 462 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LNOTIFY_PID), val); val 464 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 465 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LNOTIFY_LPID, val, winctx->lnotify_lpid); val 466 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LNOTIFY_LPID), val); val 468 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 469 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LNOTIFY_TID, val, winctx->lnotify_tid); val 470 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LNOTIFY_TID), val); val 472 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 473 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LNOTIFY_MIN_SCOPE, val, winctx->min_scope); val 474 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_LNOTIFY_MAX_SCOPE, val, winctx->max_scope); val 475 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), val); val 484 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 485 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_PUSH_TO_MEM, val, 1); val 486 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), val); val 489 arch/powerpc/platforms/powernv/vas-window.c val = 0ULL; val 490 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_REJ_NO_CREDIT, val, winctx->rej_no_credit); val 491 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_PIN, val, winctx->pin_win); val 492 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val, winctx->tx_wcred_mode); val 493 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val, winctx->rx_wcred_mode); val 494 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_TX_WORD_MODE, val, winctx->tx_word_mode); val 495 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_RX_WORD_MODE, val, winctx->rx_word_mode); val 496 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_FAULT_WIN, val, winctx->fault_win); val 497 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_NX_WIN, val, winctx->nx_win); val 498 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_OPEN, val, 1); val 499 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(WINCTL), val); val 1076 arch/powerpc/platforms/powernv/vas-window.c uint64_t val; val 1093 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(RMA_LSMP_REPORT_ENABLE, 0ULL, 1); val 1094 arch/powerpc/platforms/powernv/vas-window.c addr += val; val 1129 arch/powerpc/platforms/powernv/vas-window.c u64 val; val 1132 arch/powerpc/platforms/powernv/vas-window.c val = read_hvwc_reg(window, VREG(WINCTL)); val 1134 arch/powerpc/platforms/powernv/vas-window.c mode = GET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val); val 1136 arch/powerpc/platforms/powernv/vas-window.c mode = GET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val); val 1142 arch/powerpc/platforms/powernv/vas-window.c val = read_hvwc_reg(window, VREG(TX_WCRED)); val 1143 arch/powerpc/platforms/powernv/vas-window.c creds = GET_FIELD(VAS_TX_WCRED, val); val 1145 arch/powerpc/platforms/powernv/vas-window.c val = read_hvwc_reg(window, VREG(LRX_WCRED)); val 1146 arch/powerpc/platforms/powernv/vas-window.c creds = GET_FIELD(VAS_LRX_WCRED, val); val 1150 arch/powerpc/platforms/powernv/vas-window.c val = 0; val 1165 arch/powerpc/platforms/powernv/vas-window.c u64 val; val 1168 arch/powerpc/platforms/powernv/vas-window.c val = read_hvwc_reg(window, VREG(WIN_STATUS)); val 1169 arch/powerpc/platforms/powernv/vas-window.c busy = GET_FIELD(VAS_WIN_BUSY, val); val 1171 arch/powerpc/platforms/powernv/vas-window.c val = 0; val 1205 arch/powerpc/platforms/powernv/vas-window.c u64 val; val 1207 arch/powerpc/platforms/powernv/vas-window.c val = read_hvwc_reg(window, VREG(WINCTL)); val 1208 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_PIN, val, 0); val 1209 arch/powerpc/platforms/powernv/vas-window.c val = SET_FIELD(VAS_WINCTL_OPEN, val, 0); val 1210 arch/powerpc/platforms/powernv/vas-window.c write_hvwc_reg(window, VREG(WINCTL), val); val 411 arch/powerpc/platforms/powernv/vas.h void *regptr, u64 val) val 413 arch/powerpc/platforms/powernv/vas.h if (val) val 416 arch/powerpc/platforms/powernv/vas.h regptr, val); val 420 arch/powerpc/platforms/powernv/vas.h s32 reg, u64 val) val 425 arch/powerpc/platforms/powernv/vas.h vas_log_write(win, name, regptr, val); val 427 arch/powerpc/platforms/powernv/vas.h out_be64(regptr, val); val 431 arch/powerpc/platforms/powernv/vas.h s32 reg, u64 val) val 436 arch/powerpc/platforms/powernv/vas.h vas_log_write(win, name, regptr, val); val 438 arch/powerpc/platforms/powernv/vas.h out_be64(regptr, val); val 406 arch/powerpc/platforms/ps3/os-area.c static unsigned int db_align_up(unsigned int val, unsigned int size) val 408 arch/powerpc/platforms/ps3/os-area.c return (val + (size - 1)) & (~(size - 1)); val 389 arch/powerpc/platforms/pseries/cmm.c unsigned long val = simple_strtoul (buf, NULL, 10); val 393 arch/powerpc/platforms/pseries/cmm.c if (val != 0) val 736 arch/powerpc/platforms/pseries/cmm.c static int cmm_set_disable(const char *val, const struct kernel_param *kp) val 738 arch/powerpc/platforms/pseries/cmm.c int disable = simple_strtoul(val, NULL, 10); val 642 arch/powerpc/platforms/pseries/eeh_pseries.c static int pseries_eeh_read_config(struct pci_dn *pdn, int where, int size, u32 *val) val 644 arch/powerpc/platforms/pseries/eeh_pseries.c return rtas_read_config(pdn, where, size, val); val 656 arch/powerpc/platforms/pseries/eeh_pseries.c static int pseries_eeh_write_config(struct pci_dn *pdn, int where, int size, u32 val) val 658 arch/powerpc/platforms/pseries/eeh_pseries.c return rtas_write_config(pdn, where, size, val); val 29 arch/powerpc/platforms/pseries/firmware.c unsigned long val; val 98 arch/powerpc/platforms/pseries/firmware.c hypertas_fw_features_table[i].val; val 107 arch/powerpc/platforms/pseries/firmware.c unsigned long val; val 132 arch/powerpc/platforms/pseries/firmware.c vec5_fw_features_table[i].val; val 118 arch/powerpc/sysdev/cpm2.c u32 val; val 130 arch/powerpc/sysdev/cpm2.c val = (((clk * 2 / rate) - 1) & ~1) | CPM_BRG_EN | src; val 132 arch/powerpc/sysdev/cpm2.c val |= CPM_BRG_DIV16; val 134 arch/powerpc/sysdev/cpm2.c out_be32(bp, val); val 155 arch/powerpc/sysdev/cpm_common.c static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 166 arch/powerpc/sysdev/cpm_common.c __cpm2_gpio32_set(mm_gc, pin_mask, val); val 68 arch/powerpc/sysdev/fsl_pci.c u32 val = 0; val 73 arch/powerpc/sysdev/fsl_pci.c PCIE_LTSSM, 4, &val); val 75 arch/powerpc/sysdev/fsl_pci.c early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); val 76 arch/powerpc/sysdev/fsl_pci.c if (val < PCIE_LTSSM_L0) val 81 arch/powerpc/sysdev/fsl_pci.c val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) val 83 arch/powerpc/sysdev/fsl_pci.c if (val != PEX_CSR0_LTSSM_L0) val 91 arch/powerpc/sysdev/fsl_pci.c int offset, int len, u32 *val) val 100 arch/powerpc/sysdev/fsl_pci.c return indirect_read_config(bus, devfn, offset, len, val); val 732 arch/powerpc/sysdev/fsl_pci.c int offset, int len, u32 val) val 738 arch/powerpc/sysdev/fsl_pci.c val &= 0xffffff00; val 740 arch/powerpc/sysdev/fsl_pci.c return pci_generic_config_write(bus, devfn, offset, len, val); val 182 arch/powerpc/sysdev/fsl_rio.c u8 hopcount, u32 offset, int len, u32 *val) val 227 arch/powerpc/sysdev/fsl_rio.c *val = rval; val 247 arch/powerpc/sysdev/fsl_rio.c u8 hopcount, u32 offset, int len, u32 val) val 257 arch/powerpc/sysdev/fsl_rio.c index, destid, hopcount, offset, len, val); val 273 arch/powerpc/sysdev/fsl_rio.c out_8((u8 *) data, val); val 276 arch/powerpc/sysdev/fsl_rio.c out_be16((u16 *) data, val); val 279 arch/powerpc/sysdev/fsl_rio.c out_be32((u32 *) data, val); val 28 arch/powerpc/sysdev/grackle.c unsigned int val; val 31 arch/powerpc/sysdev/grackle.c val = in_le32(bp->cfg_data); val 32 arch/powerpc/sysdev/grackle.c val = enable? (val | GRACKLE_PICR1_STG) : val 33 arch/powerpc/sysdev/grackle.c (val & ~GRACKLE_PICR1_STG); val 35 arch/powerpc/sysdev/grackle.c out_le32(bp->cfg_data, val); val 41 arch/powerpc/sysdev/grackle.c unsigned int val; val 44 arch/powerpc/sysdev/grackle.c val = in_le32(bp->cfg_data); val 45 arch/powerpc/sysdev/grackle.c val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) : val 46 arch/powerpc/sysdev/grackle.c (val & ~GRACKLE_PICR1_LOOPSNOOP); val 48 arch/powerpc/sysdev/grackle.c out_le32(bp->cfg_data, val); val 21 arch/powerpc/sysdev/indirect_pci.c int offset, int len, u32 *val) val 64 arch/powerpc/sysdev/indirect_pci.c *val = in_8(cfg_data); val 67 arch/powerpc/sysdev/indirect_pci.c *val = in_le16(cfg_data); val 70 arch/powerpc/sysdev/indirect_pci.c *val = in_le32(cfg_data); val 77 arch/powerpc/sysdev/indirect_pci.c int offset, int len, u32 *val) val 82 arch/powerpc/sysdev/indirect_pci.c val); val 86 arch/powerpc/sysdev/indirect_pci.c int offset, int len, u32 val) val 127 arch/powerpc/sysdev/indirect_pci.c val &= 0xffffff00; val 132 arch/powerpc/sysdev/indirect_pci.c val = 0; val 142 arch/powerpc/sysdev/indirect_pci.c out_8(cfg_data, val); val 145 arch/powerpc/sysdev/indirect_pci.c out_le16(cfg_data, val); val 148 arch/powerpc/sysdev/indirect_pci.c out_le32(cfg_data, val); val 46 arch/powerpc/sysdev/mmio_nvram.c unsigned char val; val 53 arch/powerpc/sysdev/mmio_nvram.c val = ioread8(mmio_nvram_start + addr); val 57 arch/powerpc/sysdev/mmio_nvram.c return val; val 79 arch/powerpc/sysdev/mmio_nvram.c static void mmio_nvram_write_val(int addr, unsigned char val) val 86 arch/powerpc/sysdev/mmio_nvram.c iowrite8(val, mmio_nvram_start + addr); val 269 arch/powerpc/sysdev/mpic.c unsigned int val; val 271 arch/powerpc/sysdev/mpic.c val = _mpic_read(mpic->reg_type, &mpic->isus[isu], val 275 arch/powerpc/sysdev/mpic.c val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | val 278 arch/powerpc/sysdev/mpic.c return val; val 43 arch/powerpc/sysdev/simple_gpio.c static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 51 arch/powerpc/sysdev/simple_gpio.c if (val) val 66 arch/powerpc/sysdev/simple_gpio.c static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 68 arch/powerpc/sysdev/simple_gpio.c u8_gpio_set(gc, gpio, val); val 45 arch/powerpc/sysdev/tsi108_pci.c extern void tsi108_write_reg(u32 reg_offset, u32 val); val 49 arch/powerpc/sysdev/tsi108_pci.c int offset, int len, u32 val) val 66 arch/powerpc/sysdev/tsi108_pci.c printk("data = 0x%08x\n", val); val 71 arch/powerpc/sysdev/tsi108_pci.c out_8((u8 *) cfg_addr, val); val 74 arch/powerpc/sysdev/tsi108_pci.c out_le16((u16 *) cfg_addr, val); val 77 arch/powerpc/sysdev/tsi108_pci.c out_le32((u32 *) cfg_addr, val); val 133 arch/powerpc/sysdev/tsi108_pci.c int len, u32 * val) val 160 arch/powerpc/sysdev/tsi108_pci.c *val = temp; val 167 arch/powerpc/sysdev/tsi108_pci.c printk("data = 0x%x\n", *val); val 197 arch/powerpc/sysdev/xive/common.c u64 val; val 204 arch/powerpc/sysdev/xive/common.c val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0); val 206 arch/powerpc/sysdev/xive/common.c val = in_be64(xd->eoi_mmio + offset); val 208 arch/powerpc/sysdev/xive/common.c return (u8)val; val 248 arch/powerpc/sysdev/xive/common.c u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET); val 251 arch/powerpc/sysdev/xive/common.c val & XIVE_ESB_VAL_P ? 'P' : '-', val 252 arch/powerpc/sysdev/xive/common.c val & XIVE_ESB_VAL_Q ? 'Q' : '-'); val 282 arch/powerpc/sysdev/xive/common.c u64 val = xive_esb_read(xd, XIVE_ESB_GET); val 285 arch/powerpc/sysdev/xive/common.c val & XIVE_ESB_VAL_P ? 'P' : '-', val 286 arch/powerpc/sysdev/xive/common.c val & XIVE_ESB_VAL_Q ? 'Q' : '-'); val 435 arch/powerpc/sysdev/xive/common.c u64 val; val 446 arch/powerpc/sysdev/xive/common.c val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01); val 447 arch/powerpc/sysdev/xive/common.c if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P)) val 557 arch/powerpc/sysdev/xive/native.c u32 val, cpu; val 583 arch/powerpc/sysdev/xive/native.c if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0) val 584 arch/powerpc/sysdev/xive/native.c max_prio = val - 1; val 587 arch/powerpc/sysdev/xive/native.c of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) { val 588 arch/powerpc/sysdev/xive/native.c xive_queue_shift = val; val 589 arch/powerpc/sysdev/xive/native.c if (val == PAGE_SHIFT) val 753 arch/powerpc/sysdev/xive/spapr.c u8 val; val 755 arch/powerpc/sysdev/xive/spapr.c val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT); val 756 arch/powerpc/sysdev/xive/spapr.c switch (val) { val 767 arch/powerpc/sysdev/xive/spapr.c __func__, val); val 782 arch/powerpc/sysdev/xive/spapr.c u32 val; val 829 arch/powerpc/sysdev/xive/spapr.c of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) { val 830 arch/powerpc/sysdev/xive/spapr.c xive_queue_shift = val; val 831 arch/powerpc/sysdev/xive/spapr.c if (val == PAGE_SHIFT) val 2032 arch/powerpc/xmon/ppc-opc.c unsigned long val = (insn >> 16) & 0x1f; val 2036 arch/powerpc/xmon/ppc-opc.c if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) val 2037 arch/powerpc/xmon/ppc-opc.c || (val - 0x10 > 7 && (insn & 0x100) != 0) val 2038 arch/powerpc/xmon/ppc-opc.c || val <= 3 val 2039 arch/powerpc/xmon/ppc-opc.c || (val & 8) != 0) val 2041 arch/powerpc/xmon/ppc-opc.c return val & 7; val 1840 arch/powerpc/xmon/xmon.c write_spr(int n, unsigned long val) val 1851 arch/powerpc/xmon/xmon.c xmon_mtspr(n, val); val 1959 arch/powerpc/xmon/xmon.c unsigned long val; val 1961 arch/powerpc/xmon/xmon.c val = 0xdeadbeef; val 1962 arch/powerpc/xmon/xmon.c if (!read_spr(spr, &val)) { val 1967 arch/powerpc/xmon/xmon.c if (val == 0xdeadbeef) { val 1969 arch/powerpc/xmon/xmon.c val = 0x0badcafe; val 1970 arch/powerpc/xmon/xmon.c if (!read_spr(spr, &val)) { val 1975 arch/powerpc/xmon/xmon.c if (val == 0x0badcafe) { val 1982 arch/powerpc/xmon/xmon.c printf("SPR 0x%03x (%4d) = 0x%lx\n", spr, spr, val); val 2015 arch/powerpc/xmon/xmon.c unsigned long val; val 2017 arch/powerpc/xmon/xmon.c val = 0; val 2018 arch/powerpc/xmon/xmon.c read_spr(regno, &val); val 2019 arch/powerpc/xmon/xmon.c scanhex(&val); val 2020 arch/powerpc/xmon/xmon.c write_spr(regno, val); val 2150 arch/powerpc/xmon/xmon.c byterev(unsigned char *val, int size) val 2156 arch/powerpc/xmon/xmon.c SWAP(val[0], val[1], t); val 2159 arch/powerpc/xmon/xmon.c SWAP(val[0], val[3], t); val 2160 arch/powerpc/xmon/xmon.c SWAP(val[1], val[2], t); val 2163 arch/powerpc/xmon/xmon.c SWAP(val[0], val[7], t); val 2164 arch/powerpc/xmon/xmon.c SWAP(val[1], val[6], t); val 2165 arch/powerpc/xmon/xmon.c SWAP(val[2], val[5], t); val 2166 arch/powerpc/xmon/xmon.c SWAP(val[3], val[4], t); val 2216 arch/powerpc/xmon/xmon.c unsigned char val[16]; val 2244 arch/powerpc/xmon/xmon.c n = mread(adrs, val, size); val 2248 arch/powerpc/xmon/xmon.c byterev(val, size); val 2251 arch/powerpc/xmon/xmon.c printf("%.2x", val[i]); val 2261 arch/powerpc/xmon/xmon.c val[i] = n >> (i * 8); val 2263 arch/powerpc/xmon/xmon.c byterev(val, size); val 2264 arch/powerpc/xmon/xmon.c mwrite(adrs, val, size); val 2280 arch/powerpc/xmon/xmon.c val[i] = n >> (i * 8); val 2282 arch/powerpc/xmon/xmon.c byterev(val, size); val 2283 arch/powerpc/xmon/xmon.c mwrite(adrs, val, size); val 2682 arch/powerpc/xmon/xmon.c u64 val; val 2697 arch/powerpc/xmon/xmon.c case 1: val = temp[j]; break; val 2698 arch/powerpc/xmon/xmon.c case 2: val = *(u16 *)&temp[j]; break; val 2699 arch/powerpc/xmon/xmon.c case 4: val = *(u32 *)&temp[j]; break; val 2700 arch/powerpc/xmon/xmon.c case 8: val = *(u64 *)&temp[j]; break; val 2701 arch/powerpc/xmon/xmon.c default: val = 0; val 2704 arch/powerpc/xmon/xmon.c printf("%0*llx", size * 2, val); val 2845 arch/powerpc/xmon/xmon.c unsigned char val[4]; val 2849 arch/powerpc/xmon/xmon.c nr = mread(adr, val, 4); val 2857 arch/powerpc/xmon/xmon.c inst = GETWORD(val); val 3021 arch/powerpc/xmon/xmon.c unsigned char val[4]; val 3038 arch/powerpc/xmon/xmon.c if (mread(a, val, 4) == 4 val 3039 arch/powerpc/xmon/xmon.c && ((GETWORD(val) ^ mval) & mask) == 0) { val 3040 arch/powerpc/xmon/xmon.c printf("%.16x: %.16x\n", a, GETWORD(val)); val 3859 arch/powerpc/xmon/xmon.c static int xmon_dbgfs_set(void *data, u64 val) val 3861 arch/powerpc/xmon/xmon.c xmon_on = !!val; val 3875 arch/powerpc/xmon/xmon.c static int xmon_dbgfs_get(void *data, u64 *val) val 3877 arch/powerpc/xmon/xmon.c *val = xmon_on; val 94 arch/riscv/include/asm/csr.h #define csr_swap(csr, val) \ val 96 arch/riscv/include/asm/csr.h unsigned long __v = (unsigned long)(val); \ val 112 arch/riscv/include/asm/csr.h #define csr_write(csr, val) \ val 114 arch/riscv/include/asm/csr.h unsigned long __v = (unsigned long)(val); \ val 120 arch/riscv/include/asm/csr.h #define csr_read_set(csr, val) \ val 122 arch/riscv/include/asm/csr.h unsigned long __v = (unsigned long)(val); \ val 129 arch/riscv/include/asm/csr.h #define csr_set(csr, val) \ val 131 arch/riscv/include/asm/csr.h unsigned long __v = (unsigned long)(val); \ val 137 arch/riscv/include/asm/csr.h #define csr_read_clear(csr, val) \ val 139 arch/riscv/include/asm/csr.h unsigned long __v = (unsigned long)(val); \ val 146 arch/riscv/include/asm/csr.h #define csr_clear(csr, val) \ val 148 arch/riscv/include/asm/csr.h unsigned long __v = (unsigned long)(val); \ val 83 arch/riscv/include/asm/futex.h u32 val; val 106 arch/riscv/include/asm/futex.h : [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp) val 111 arch/riscv/include/asm/futex.h *uval = val; val 33 arch/riscv/include/asm/io.h static inline void __raw_writeb(u8 val, volatile void __iomem *addr) val 35 arch/riscv/include/asm/io.h asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); val 39 arch/riscv/include/asm/io.h static inline void __raw_writew(u16 val, volatile void __iomem *addr) val 41 arch/riscv/include/asm/io.h asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); val 45 arch/riscv/include/asm/io.h static inline void __raw_writel(u32 val, volatile void __iomem *addr) val 47 arch/riscv/include/asm/io.h asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); val 52 arch/riscv/include/asm/io.h static inline void __raw_writeq(u64 val, volatile void __iomem *addr) val 54 arch/riscv/include/asm/io.h asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); val 61 arch/riscv/include/asm/io.h u8 val; val 63 arch/riscv/include/asm/io.h asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr)); val 64 arch/riscv/include/asm/io.h return val; val 70 arch/riscv/include/asm/io.h u16 val; val 72 arch/riscv/include/asm/io.h asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr)); val 73 arch/riscv/include/asm/io.h return val; val 79 arch/riscv/include/asm/io.h u32 val; val 81 arch/riscv/include/asm/io.h asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr)); val 82 arch/riscv/include/asm/io.h return val; val 89 arch/riscv/include/asm/io.h u64 val; val 91 arch/riscv/include/asm/io.h asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr)); val 92 arch/riscv/include/asm/io.h return val; val 12 arch/riscv/include/asm/module.h unsigned long module_emit_got_entry(struct module *mod, unsigned long val); val 13 arch/riscv/include/asm/module.h unsigned long module_emit_plt_entry(struct module *mod, unsigned long val); val 32 arch/riscv/include/asm/module.h static inline struct got_entry emit_got_entry(unsigned long val) val 34 arch/riscv/include/asm/module.h return (struct got_entry) {val}; val 37 arch/riscv/include/asm/module.h static inline struct got_entry *get_got_entry(unsigned long val, val 43 arch/riscv/include/asm/module.h if (got[i].symbol_addr == val) val 65 arch/riscv/include/asm/module.h static inline struct plt_entry emit_plt_entry(unsigned long val, val 91 arch/riscv/include/asm/module.h static inline int get_got_plt_idx(unsigned long val, const struct mod_section *sec) val 96 arch/riscv/include/asm/module.h if (got_plt[i].symbol_addr == val) val 102 arch/riscv/include/asm/module.h static inline struct plt_entry *get_plt_entry(unsigned long val, val 107 arch/riscv/include/asm/module.h int got_plt_idx = get_got_plt_idx(val, sec_got_plt); val 425 arch/riscv/include/asm/pgtable.h #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) val 426 arch/riscv/include/asm/pgtable.h #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) val 431 arch/riscv/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 70 arch/riscv/include/asm/ptrace.h unsigned long val) val 72 arch/riscv/include/asm/ptrace.h regs->sepc = val; val 83 arch/riscv/include/asm/ptrace.h unsigned long val) val 85 arch/riscv/include/asm/ptrace.h regs->sp = val; val 94 arch/riscv/include/asm/ptrace.h unsigned long val) val 96 arch/riscv/include/asm/ptrace.h regs->s0 = val; val 60 arch/riscv/include/asm/syscall.h int error, long val) val 62 arch/riscv/include/asm/syscall.h regs->a0 = (long) error ?: val; val 20 arch/riscv/include/asm/word-at-a-time.h static inline unsigned long has_zero(unsigned long val, val 23 arch/riscv/include/asm/word-at-a-time.h unsigned long mask = ((val - c->one_bits) & ~val) & c->high_bits; val 28 arch/riscv/include/asm/word-at-a-time.h static inline unsigned long prep_zero_mask(unsigned long val, val 13 arch/riscv/kernel/module-sections.c unsigned long module_emit_got_entry(struct module *mod, unsigned long val) val 17 arch/riscv/kernel/module-sections.c struct got_entry *got = get_got_entry(val, got_sec); val 24 arch/riscv/kernel/module-sections.c got[i] = emit_got_entry(val); val 32 arch/riscv/kernel/module-sections.c unsigned long module_emit_plt_entry(struct module *mod, unsigned long val) val 37 arch/riscv/kernel/module-sections.c struct plt_entry *plt = get_plt_entry(val, plt_sec, got_plt_sec); val 45 arch/riscv/kernel/module-sections.c got_plt[i] = emit_got_entry(val); val 47 arch/riscv/kernel/module-sections.c plt[i] = emit_plt_entry(val, val 184 arch/riscv/kernel/perf_event.c u64 val = 0; val 188 arch/riscv/kernel/perf_event.c val = csr_read(CSR_CYCLE); val 191 arch/riscv/kernel/perf_event.c val = csr_read(CSR_INSTRET); val 198 arch/riscv/kernel/perf_event.c return val; val 47 arch/riscv/mm/sifive_l2_cache.c unsigned int val; val 49 arch/riscv/mm/sifive_l2_cache.c if (kstrtouint_from_user(data, count, 0, &val)) val 51 arch/riscv/mm/sifive_l2_cache.c if ((val >= 0 && val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) val 52 arch/riscv/mm/sifive_l2_cache.c writel(val, l2_base + SIFIVE_L2_ECCINJECTERR); val 75 arch/riscv/mm/sifive_l2_cache.c u32 regval, val; val 78 arch/riscv/mm/sifive_l2_cache.c val = regval & 0xFF; val 79 arch/riscv/mm/sifive_l2_cache.c pr_info("L2CACHE: No. of Banks in the cache: %d\n", val); val 80 arch/riscv/mm/sifive_l2_cache.c val = (regval & 0xFF00) >> 8; val 81 arch/riscv/mm/sifive_l2_cache.c pr_info("L2CACHE: No. of ways per bank: %d\n", val); val 82 arch/riscv/mm/sifive_l2_cache.c val = (regval & 0xFF0000) >> 16; val 83 arch/riscv/mm/sifive_l2_cache.c pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val); val 84 arch/riscv/mm/sifive_l2_cache.c val = (regval & 0xFF000000) >> 24; val 85 arch/riscv/mm/sifive_l2_cache.c pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); val 464 arch/riscv/net/bpf_jit_comp.c static bool is_12b_int(s64 val) val 466 arch/riscv/net/bpf_jit_comp.c return -(1 << 11) <= val && val < (1 << 11); val 469 arch/riscv/net/bpf_jit_comp.c static bool is_13b_int(s64 val) val 471 arch/riscv/net/bpf_jit_comp.c return -(1 << 12) <= val && val < (1 << 12); val 474 arch/riscv/net/bpf_jit_comp.c static bool is_21b_int(s64 val) val 476 arch/riscv/net/bpf_jit_comp.c return -(1L << 20) <= val && val < (1L << 20); val 479 arch/riscv/net/bpf_jit_comp.c static bool is_32b_int(s64 val) val 481 arch/riscv/net/bpf_jit_comp.c return -(1L << 31) <= val && val < (1L << 31); val 514 arch/riscv/net/bpf_jit_comp.c static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) val 526 arch/riscv/net/bpf_jit_comp.c s64 upper = (val + (1 << 11)) >> 12, lower = val & 0xfff; val 529 arch/riscv/net/bpf_jit_comp.c if (is_32b_int(val)) { val 82 arch/s390/appldata/appldata_mem.c static struct sysinfo val; val 99 arch/s390/appldata/appldata_mem.c si_meminfo(&val); val 100 arch/s390/appldata/appldata_mem.c mem_data->sharedram = val.sharedram; val 101 arch/s390/appldata/appldata_mem.c mem_data->totalram = P2K(val.totalram); val 102 arch/s390/appldata/appldata_mem.c mem_data->freeram = P2K(val.freeram); val 103 arch/s390/appldata/appldata_mem.c mem_data->totalhigh = P2K(val.totalhigh); val 104 arch/s390/appldata/appldata_mem.c mem_data->freehigh = P2K(val.freehigh); val 105 arch/s390/appldata/appldata_mem.c mem_data->bufferram = P2K(val.bufferram); val 107 arch/s390/appldata/appldata_mem.c - val.bufferram); val 109 arch/s390/appldata/appldata_mem.c si_swapinfo(&val); val 110 arch/s390/appldata/appldata_mem.c mem_data->totalswap = P2K(val.totalswap); val 111 arch/s390/appldata/appldata_mem.c mem_data->freeswap = P2K(val.freeswap); val 22 arch/s390/boot/als.c static void u16_to_hex(char *str, u16 val) val 27 arch/s390/boot/als.c num = (val >> (16 - 4 * i)) & 0xf; val 48 arch/s390/boot/als.c static void u16_to_decimal(char *str, u16 val) val 52 arch/s390/boot/als.c while (div * 10 <= val) val 55 arch/s390/boot/als.c *str++ = '0' + val / div; val 56 arch/s390/boot/als.c val %= div; val 65 arch/s390/boot/als.c unsigned long val; val 71 arch/s390/boot/als.c val = ~S390_lowcore.stfle_fac_list[i] & als[i]; val 73 arch/s390/boot/als.c if (!(val & (1UL << (BITS_PER_LONG - 1 - j)))) val 177 arch/s390/boot/ipl_parm.c unsigned long val, endval; val 187 arch/s390/boot/ipl_parm.c val = simple_strtoull(str, &endp, 0); val 197 arch/s390/boot/ipl_parm.c while (val <= endval) { val 198 arch/s390/boot/ipl_parm.c modify_facility(val, clear); val 199 arch/s390/boot/ipl_parm.c val++; val 202 arch/s390/boot/ipl_parm.c modify_facility(val, clear); val 214 arch/s390/boot/ipl_parm.c char *param, *val; val 222 arch/s390/boot/ipl_parm.c args = next_arg(args, ¶m, &val); val 224 arch/s390/boot/ipl_parm.c if (!strcmp(param, "mem") && val) { val 225 arch/s390/boot/ipl_parm.c memory_end = round_down(memparse(val, NULL), PAGE_SIZE); val 229 arch/s390/boot/ipl_parm.c if (!strcmp(param, "vmalloc") && val) val 230 arch/s390/boot/ipl_parm.c vmalloc_size = round_up(memparse(val, NULL), PAGE_SIZE); val 233 arch/s390/boot/ipl_parm.c rc = kstrtobool(val, &enabled); val 238 arch/s390/boot/ipl_parm.c if (!strcmp(param, "facilities") && val) val 239 arch/s390/boot/ipl_parm.c modify_fac_list(val); val 10 arch/s390/boot/pgm_check_info.c #define add_val_as_hex(dst, val) \ val 11 arch/s390/boot/pgm_check_info.c __add_val_as_hex(dst, (const unsigned char *)&val, sizeof(val)) val 96 arch/s390/boot/startup.c Elf64_Addr loc, val; val 104 arch/s390/boot/startup.c val = rela->r_addend; val 108 arch/s390/boot/startup.c val += dynsym[r_sym].st_value + offset; val 114 arch/s390/boot/startup.c val += offset; val 117 arch/s390/boot/startup.c rc = arch_kexec_do_relocs(r_type, (void *) loc, val, 0); val 248 arch/s390/include/asm/ap.h unsigned long val; val 279 arch/s390/include/asm/ap.h reg1.value = apinfo->val; val 286 arch/s390/include/asm/ap.h apinfo->val = reg2; val 14 arch/s390/include/asm/atomic_ops.h static inline op_type op_name(op_type val, op_type *ptr) \ val 22 arch/s390/include/asm/atomic_ops.h : [val] "d" (val) : "cc", "memory"); \ val 44 arch/s390/include/asm/atomic_ops.h static __always_inline void op_name(op_type val, op_type *ptr) \ val 49 arch/s390/include/asm/atomic_ops.h : [ptr] "+Q" (*ptr) : [val] "i" (val) : "cc", "memory");\ val 65 arch/s390/include/asm/atomic_ops.h static inline int op_name(int val, int *ptr) \ val 75 arch/s390/include/asm/atomic_ops.h : [val] "d" (val), "0" (*ptr) : "cc", "memory"); \ val 91 arch/s390/include/asm/atomic_ops.h static inline long op_name(long val, long *ptr) \ val 101 arch/s390/include/asm/atomic_ops.h : [val] "d" (val), "0" (*ptr) : "cc", "memory"); \ val 116 arch/s390/include/asm/atomic_ops.h #define __atomic_add_const(val, ptr) __atomic_add(val, ptr) val 117 arch/s390/include/asm/atomic_ops.h #define __atomic_add_const_barrier(val, ptr) __atomic_add(val, ptr) val 118 arch/s390/include/asm/atomic_ops.h #define __atomic64_add_const(val, ptr) __atomic64_add(val, ptr) val 119 arch/s390/include/asm/atomic_ops.h #define __atomic64_add_const_barrier(val, ptr) __atomic64_add(val, ptr) val 366 arch/s390/include/asm/bitops.h unsigned int val = (unsigned int)word; val 368 arch/s390/include/asm/bitops.h return (1 + (__flogr(-val & val) ^ (BITS_PER_LONG - 1))) & mask; val 206 arch/s390/include/asm/cpu_mf.h static inline int ecctr(u64 ctr, u64 *val) val 213 arch/s390/include/asm/cpu_mf.h *val = content; val 80 arch/s390/include/asm/ctl_reg.h unsigned long val; val 103 arch/s390/include/asm/ctl_reg.h unsigned long val; val 299 arch/s390/include/asm/diag.h unsigned long val; val 120 arch/s390/include/asm/gmap.h int gmap_read_table(struct gmap *gmap, unsigned long gaddr, unsigned long *val); val 61 arch/s390/include/asm/io.h #define memset_io(dst, val, count) zpci_memset_io(dst, val, count) val 74 arch/s390/include/asm/kexec.h int arch_kexec_do_relocs(int r_type, void *loc, unsigned long val, val 78 arch/s390/include/asm/kprobes.h unsigned long val, void *data); val 87 arch/s390/include/asm/kvm_host.h unsigned long val; val 36 arch/s390/include/asm/nmi.h unsigned long val; val 91 arch/s390/include/asm/pci.h u32 val; /* bar start & 3 flag bits */ val 54 arch/s390/include/asm/pci_io.h static inline void zpci_write_##VALTYPE(VALTYPE val, \ val 57 arch/s390/include/asm/pci_io.h u64 data = (VALTYPE) val; \ val 74 arch/s390/include/asm/pci_io.h u64 val; val 78 arch/s390/include/asm/pci_io.h val = (u64) *((u8 *) src); val 81 arch/s390/include/asm/pci_io.h val = (u64) *((u16 *) src); val 84 arch/s390/include/asm/pci_io.h val = (u64) *((u32 *) src); val 87 arch/s390/include/asm/pci_io.h val = (u64) *((u64 *) src); val 90 arch/s390/include/asm/pci_io.h val = 0; /* let FW report error */ val 93 arch/s390/include/asm/pci_io.h return zpci_store(dst, val, len); val 185 arch/s390/include/asm/pci_io.h unsigned char val, size_t count) val 192 arch/s390/include/asm/pci_io.h memset(src, val, count); val 27 arch/s390/include/asm/percpu.h #define arch_this_cpu_to_op_simple(pcp, val, op) \ val 37 arch/s390/include/asm/percpu.h new__ = old__ op (val); \ val 44 arch/s390/include/asm/percpu.h #define this_cpu_add_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) val 45 arch/s390/include/asm/percpu.h #define this_cpu_add_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) val 46 arch/s390/include/asm/percpu.h #define this_cpu_add_return_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) val 47 arch/s390/include/asm/percpu.h #define this_cpu_add_return_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) val 48 arch/s390/include/asm/percpu.h #define this_cpu_and_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) val 49 arch/s390/include/asm/percpu.h #define this_cpu_and_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) val 50 arch/s390/include/asm/percpu.h #define this_cpu_or_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) val 51 arch/s390/include/asm/percpu.h #define this_cpu_or_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) val 55 arch/s390/include/asm/percpu.h #define this_cpu_add_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) val 56 arch/s390/include/asm/percpu.h #define this_cpu_add_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) val 57 arch/s390/include/asm/percpu.h #define this_cpu_add_return_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) val 58 arch/s390/include/asm/percpu.h #define this_cpu_add_return_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) val 59 arch/s390/include/asm/percpu.h #define this_cpu_and_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) val 60 arch/s390/include/asm/percpu.h #define this_cpu_and_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) val 61 arch/s390/include/asm/percpu.h #define this_cpu_or_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) val 62 arch/s390/include/asm/percpu.h #define this_cpu_or_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) val 66 arch/s390/include/asm/percpu.h #define arch_this_cpu_add(pcp, val, op1, op2, szcast) \ val 69 arch/s390/include/asm/percpu.h pcp_op_T__ val__ = (val); \ val 90 arch/s390/include/asm/percpu.h #define this_cpu_add_4(pcp, val) arch_this_cpu_add(pcp, val, "laa", "asi", int) val 91 arch/s390/include/asm/percpu.h #define this_cpu_add_8(pcp, val) arch_this_cpu_add(pcp, val, "laag", "agsi", long) val 93 arch/s390/include/asm/percpu.h #define arch_this_cpu_add_return(pcp, val, op) \ val 96 arch/s390/include/asm/percpu.h pcp_op_T__ val__ = (val); \ val 109 arch/s390/include/asm/percpu.h #define this_cpu_add_return_4(pcp, val) arch_this_cpu_add_return(pcp, val, "laa") val 110 arch/s390/include/asm/percpu.h #define this_cpu_add_return_8(pcp, val) arch_this_cpu_add_return(pcp, val, "laag") val 112 arch/s390/include/asm/percpu.h #define arch_this_cpu_to_op(pcp, val, op) \ val 115 arch/s390/include/asm/percpu.h pcp_op_T__ val__ = (val); \ val 127 arch/s390/include/asm/percpu.h #define this_cpu_and_4(pcp, val) arch_this_cpu_to_op(pcp, val, "lan") val 128 arch/s390/include/asm/percpu.h #define this_cpu_and_8(pcp, val) arch_this_cpu_to_op(pcp, val, "lang") val 129 arch/s390/include/asm/percpu.h #define this_cpu_or_4(pcp, val) arch_this_cpu_to_op(pcp, val, "lao") val 130 arch/s390/include/asm/percpu.h #define this_cpu_or_8(pcp, val) arch_this_cpu_to_op(pcp, val, "laog") val 163 arch/s390/include/asm/pgalloc.h void *vmem_crst_alloc(unsigned long val); val 1664 arch/s390/include/asm/pgtable.h return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; val 1669 arch/s390/include/asm/pgtable.h return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; val 1678 arch/s390/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 53 arch/s390/include/asm/preempt.h static inline void __preempt_count_add(int val) val 55 arch/s390/include/asm/preempt.h if (__builtin_constant_p(val) && (val >= -128) && (val <= 127)) val 56 arch/s390/include/asm/preempt.h __atomic_add_const(val, &S390_lowcore.preempt_count); val 58 arch/s390/include/asm/preempt.h __atomic_add(val, &S390_lowcore.preempt_count); val 61 arch/s390/include/asm/preempt.h static inline void __preempt_count_sub(int val) val 63 arch/s390/include/asm/preempt.h __preempt_count_add(-val); val 110 arch/s390/include/asm/preempt.h static inline void __preempt_count_add(int val) val 112 arch/s390/include/asm/preempt.h S390_lowcore.preempt_count += val; val 115 arch/s390/include/asm/preempt.h static inline void __preempt_count_sub(int val) val 117 arch/s390/include/asm/preempt.h S390_lowcore.preempt_count -= val; val 233 arch/s390/include/asm/processor.h unsigned long val; val 236 arch/s390/include/asm/processor.h : "=d" (val) : "a" (asi << 8 | parm)); val 237 arch/s390/include/asm/processor.h return val; val 339 arch/s390/include/asm/processor.h #define mem_assign_absolute(dest, val) do { \ val 340 arch/s390/include/asm/processor.h __typeof__(dest) __tmp = (val); \ val 342 arch/s390/include/asm/processor.h BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ val 172 arch/s390/include/asm/ptrace.h unsigned long val) val 174 arch/s390/include/asm/ptrace.h regs->psw.addr = val; val 246 arch/s390/include/asm/qdio.h u8 val[QDIO_MAX_BUFFERS_PER_Q]; val 35 arch/s390/include/asm/smp.h extern void smp_cpu_set_polarization(int cpu, int val); val 47 arch/s390/include/asm/syscall.h int error, long val) val 49 arch/s390/include/asm/syscall.h regs->gprs[2] = error ? error : val; val 346 arch/s390/kernel/dis.c unsigned int val; val 352 arch/s390/kernel/dis.c val = 0; val 354 arch/s390/kernel/dis.c val <<= 8; val 355 arch/s390/kernel/dis.c val |= (unsigned int) *cp++; val 358 arch/s390/kernel/dis.c val >>= -bits; val 359 arch/s390/kernel/dis.c val &= ((1U << (operand->bits - 1)) << 1) - 1; val 363 arch/s390/kernel/dis.c val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; val 368 arch/s390/kernel/dis.c val |= (code[4] & 8) << 1; val 370 arch/s390/kernel/dis.c val |= (code[4] & 4) << 2; val 372 arch/s390/kernel/dis.c val |= (code[4] & 2) << 3; val 374 arch/s390/kernel/dis.c val |= (code[4] & 1) << 4; val 379 arch/s390/kernel/dis.c (val & (1U << (operand->bits - 1)))) val 380 arch/s390/kernel/dis.c val |= (-1U << (operand->bits - 1)) << 1; val 384 arch/s390/kernel/dis.c val <<= 1; val 388 arch/s390/kernel/dis.c val++; val 389 arch/s390/kernel/dis.c return val; val 611 arch/s390/kernel/kprobes.c unsigned long val, void *data) val 620 arch/s390/kernel/kprobes.c switch (val) { val 126 arch/s390/kernel/machine_kexec.c __ctl_store(cr2_old.val, 2, 2); val 129 arch/s390/kernel/machine_kexec.c __ctl_load(cr2_new.val, 2, 2); val 131 arch/s390/kernel/machine_kexec.c __ctl_load(cr2_old.val, 2, 2); val 278 arch/s390/kernel/machine_kexec_file.c unsigned long val; /* relocated symbol value */ val 298 arch/s390/kernel/machine_kexec_file.c val = sym->st_value; val 300 arch/s390/kernel/machine_kexec_file.c val += pi->sechdrs[sym->st_shndx].sh_addr; val 301 arch/s390/kernel/machine_kexec_file.c val += relas[i].r_addend; val 306 arch/s390/kernel/machine_kexec_file.c arch_kexec_do_relocs(r_type, loc, val, addr); val 5 arch/s390/kernel/machine_kexec_reloc.c int arch_kexec_do_relocs(int r_type, void *loc, unsigned long val, val 12 arch/s390/kernel/machine_kexec_reloc.c *(u8 *)loc = val; val 16 arch/s390/kernel/machine_kexec_reloc.c *(u16 *)loc |= val & 0xfff; val 19 arch/s390/kernel/machine_kexec_reloc.c *(u16 *)loc = val; val 23 arch/s390/kernel/machine_kexec_reloc.c *(u32 *)loc |= (val & 0xfff) << 16; /* DL */ val 24 arch/s390/kernel/machine_kexec_reloc.c *(u32 *)loc |= (val & 0xff000) >> 4; /* DH */ val 27 arch/s390/kernel/machine_kexec_reloc.c *(u32 *)loc = val; val 32 arch/s390/kernel/machine_kexec_reloc.c *(u64 *)loc = val; val 35 arch/s390/kernel/machine_kexec_reloc.c *(u16 *)loc = (val - addr); val 38 arch/s390/kernel/machine_kexec_reloc.c *(u16 *)loc = (val - addr) >> 1; val 41 arch/s390/kernel/machine_kexec_reloc.c *(u32 *)loc = (val - addr) >> 1; val 44 arch/s390/kernel/machine_kexec_reloc.c *(u32 *)loc = (val - addr); val 47 arch/s390/kernel/machine_kexec_reloc.c *(u64 *)loc = (val - addr); val 50 arch/s390/kernel/machine_kexec_reloc.c *(unsigned long *) loc = val; val 176 arch/s390/kernel/module.c static int apply_rela_bits(Elf_Addr loc, Elf_Addr val, val 182 arch/s390/kernel/module.c if (val & ((1UL << shift) - 1)) val 185 arch/s390/kernel/module.c val = (Elf_Addr)(((long) val) >> shift); val 188 arch/s390/kernel/module.c if ((long) val < min || (long) val > max) val 191 arch/s390/kernel/module.c val >>= shift; val 193 arch/s390/kernel/module.c if ((unsigned long) val > umax) val 198 arch/s390/kernel/module.c *(unsigned char *) loc = val; val 200 arch/s390/kernel/module.c *(unsigned short *) loc = (val & 0xfff) | val 203 arch/s390/kernel/module.c *(unsigned short *) loc = val; val 205 arch/s390/kernel/module.c *(unsigned int *) loc = (val & 0xfff) << 16 | val 206 arch/s390/kernel/module.c (val & 0xff000) >> 4 | val 209 arch/s390/kernel/module.c *(unsigned int *) loc = val; val 211 arch/s390/kernel/module.c *(unsigned long *) loc = val; val 219 arch/s390/kernel/module.c Elf_Addr loc, val; val 230 arch/s390/kernel/module.c val = symtab[r_sym].st_value; val 242 arch/s390/kernel/module.c val += rela->r_addend; val 244 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 8, 0); val 246 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 12, 0); val 248 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 16, 0); val 250 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 20, 0); val 252 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 32, 0); val 254 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 64, 0); val 261 arch/s390/kernel/module.c val += rela->r_addend - loc; val 263 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 16, 0); val 265 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 16, 1); val 267 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 32, 1); val 269 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 32, 0); val 271 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 64, 0); val 290 arch/s390/kernel/module.c *gotent = val; val 293 arch/s390/kernel/module.c val = info->got_offset + rela->r_addend; val 296 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 12, 0); val 299 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 16, 0); val 302 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 20, 0); val 305 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 32, 0); val 308 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 64, 0); val 311 arch/s390/kernel/module.c val += (Elf_Addr) me->core_layout.base - loc; val 312 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 32, 1); val 340 arch/s390/kernel/module.c ip[3] = (unsigned int) (val >> 32); val 341 arch/s390/kernel/module.c ip[4] = (unsigned int) val; val 347 arch/s390/kernel/module.c val = me->arch.plt_offset - me->arch.got_offset + val 351 arch/s390/kernel/module.c val - loc + 0xffffUL < 0x1ffffeUL) || val 353 arch/s390/kernel/module.c val - loc + 0xffffffffULL < 0x1fffffffeULL))) val 354 arch/s390/kernel/module.c val = (Elf_Addr) me->core_layout.base + val 357 arch/s390/kernel/module.c val += rela->r_addend - loc; val 360 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 16, 1); val 362 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 16, 0); val 364 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 32, 1); val 367 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 32, 0); val 370 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 64, 0); val 375 arch/s390/kernel/module.c val = val + rela->r_addend - val 378 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 16, 0); val 380 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 32, 0); val 382 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 0, 64, 0); val 386 arch/s390/kernel/module.c val = (Elf_Addr) me->core_layout.base + me->arch.got_offset + val 389 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 32, 0); val 391 arch/s390/kernel/module.c rc = apply_rela_bits(loc, val, 1, 32, 1); val 409 arch/s390/kernel/module.c r_type, (unsigned long) val); val 264 arch/s390/kernel/nmi.c cr2.val = S390_lowcore.cregs_save_area[2]; val 348 arch/s390/kernel/nmi.c mci.val = S390_lowcore.mcck_interruption_code; val 370 arch/s390/kernel/nmi.c t_mcic = mci.val; val 402 arch/s390/kernel/nmi.c mcck->mcck_code = mci.val; val 458 arch/s390/kernel/nmi.c mcck_dam_code = (mci.val & MCIC_SUBCLASS_MASK); val 2113 arch/s390/kernel/perf_cpum_sf.c static int param_set_sfb_size(const char *val, const struct kernel_param *kp) val 2120 arch/s390/kernel/perf_cpum_sf.c if (!val || !strlen(val)) val 2126 arch/s390/kernel/perf_cpum_sf.c if (strchr(val, ',')) val 2127 arch/s390/kernel/perf_cpum_sf.c rc = (sscanf(val, "%lu,%lu", &min, &max) == 2) ? 0 : -EINVAL; val 2129 arch/s390/kernel/perf_cpum_sf.c rc = kstrtoul(val, 10, &max); val 54 arch/s390/kernel/ptrace.c __ctl_store(cr0_old.val, 0, 0); val 55 arch/s390/kernel/ptrace.c __ctl_store(cr2_old.val, 2, 2); val 80 arch/s390/kernel/ptrace.c cr0_changed = cr0_new.val != cr0_old.val; val 81 arch/s390/kernel/ptrace.c cr2_changed = cr2_new.val != cr2_old.val; val 83 arch/s390/kernel/ptrace.c __ctl_load(cr0_new.val, 0, 0); val 85 arch/s390/kernel/ptrace.c __ctl_load(cr2_new.val, 2, 2); val 1052 arch/s390/kernel/setup.c asm volatile("diag %0,0,0x318\n" : : "d" (diag318_info.val)); val 699 arch/s390/kernel/smp.c void smp_cpu_set_polarization(int cpu, int val) val 701 arch/s390/kernel/smp.c pcpu_devices[cpu].polarization = val; val 1042 arch/s390/kernel/smp.c int cpu, val, rc, i; val 1045 arch/s390/kernel/smp.c if (sscanf(buf, "%d %c", &val, &delim) != 1) val 1047 arch/s390/kernel/smp.c if (val != 0 && val != 1) val 1062 arch/s390/kernel/smp.c switch (val) { val 386 arch/s390/kernel/topology.c int val, rc; val 389 arch/s390/kernel/topology.c if (sscanf(buf, "%d %c", &val, &delim) != 1) val 391 arch/s390/kernel/topology.c if (val != 0 && val != 1) val 396 arch/s390/kernel/topology.c if (cpu_management == val) val 398 arch/s390/kernel/topology.c rc = topology_set_cpu_management(val); val 401 arch/s390/kernel/topology.c cpu_management = val; val 111 arch/s390/kernel/uprobes.c int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, val 121 arch/s390/kernel/uprobes.c switch (val) { val 20 arch/s390/kvm/gaccess.c unsigned long val; val 43 arch/s390/kvm/gaccess.c unsigned long val; val 58 arch/s390/kvm/gaccess.c unsigned long val; val 102 arch/s390/kvm/gaccess.c unsigned long val; val 144 arch/s390/kvm/gaccess.c unsigned long val; val 166 arch/s390/kvm/gaccess.c unsigned long val; val 216 arch/s390/kvm/gaccess.c u32 val; val 226 arch/s390/kvm/gaccess.c u32 val; val 297 arch/s390/kvm/gaccess.c } while (cmpxchg(&ic->val, old.val, new.val) != old.val); val 317 arch/s390/kvm/gaccess.c } while (cmpxchg(&ic->val, old.val, new.val) != old.val); val 341 arch/s390/kvm/gaccess.c } while (cmpxchg(&ic->val, old.val, new.val) != old.val); val 357 arch/s390/kvm/gaccess.c } while (cmpxchg(&ic->val, old.val, new.val) != old.val); val 394 arch/s390/kvm/gaccess.c alet.val = vcpu->run->s.regs.acrs[ar]; val 396 arch/s390/kvm/gaccess.c if (ar == 0 || alet.val == 0) { val 397 arch/s390/kvm/gaccess.c asce->val = vcpu->arch.sie_block->gcr[1]; val 399 arch/s390/kvm/gaccess.c } else if (alet.val == 1) { val 400 arch/s390/kvm/gaccess.c asce->val = vcpu->arch.sie_block->gcr[7]; val 413 arch/s390/kvm/gaccess.c rc = read_guest_real(vcpu, ald_addr + 16, &ald.val, sizeof(union ald)); val 464 arch/s390/kvm/gaccess.c asce->val = aste.asce; val 561 arch/s390/kvm/gaccess.c asce->val = 0; val 571 arch/s390/kvm/gaccess.c asce->val = vcpu->arch.sie_block->gcr[1]; val 574 arch/s390/kvm/gaccess.c asce->val = vcpu->arch.sie_block->gcr[7]; val 577 arch/s390/kvm/gaccess.c asce->val = vcpu->arch.sie_block->gcr[13]; val 588 arch/s390/kvm/gaccess.c static int deref_table(struct kvm *kvm, unsigned long gpa, unsigned long *val) val 590 arch/s390/kvm/gaccess.c return kvm_read_guest(kvm, gpa, val, sizeof(*val)); val 627 arch/s390/kvm/gaccess.c ctlreg0.val = vcpu->arch.sie_block->gcr[0]; val 668 arch/s390/kvm/gaccess.c if (deref_table(vcpu->kvm, ptr, &rfte.val)) val 686 arch/s390/kvm/gaccess.c if (deref_table(vcpu->kvm, ptr, &rste.val)) val 704 arch/s390/kvm/gaccess.c if (deref_table(vcpu->kvm, ptr, &rtte.val)) val 732 arch/s390/kvm/gaccess.c if (deref_table(vcpu->kvm, ptr, &ste.val)) val 752 arch/s390/kvm/gaccess.c if (deref_table(vcpu->kvm, ptr, &pte.val)) val 787 arch/s390/kvm/gaccess.c union ctlreg0 ctlreg0 = {.val = vcpu->arch.sie_block->gcr[0]}; val 968 arch/s390/kvm/gaccess.c union ctlreg0 ctlreg0 = {.val = vcpu->arch.sie_block->gcr[0]}; val 996 arch/s390/kvm/gaccess.c asce.val = sg->orig_asce; val 1034 arch/s390/kvm/gaccess.c rfte.val = ptr; val 1037 arch/s390/kvm/gaccess.c rc = gmap_read_table(parent, ptr + vaddr.rfx * 8, &rfte.val); val 1050 arch/s390/kvm/gaccess.c rc = gmap_shadow_r2t(sg, saddr, rfte.val, *fake); val 1059 arch/s390/kvm/gaccess.c rste.val = ptr; val 1062 arch/s390/kvm/gaccess.c rc = gmap_read_table(parent, ptr + vaddr.rsx * 8, &rste.val); val 1076 arch/s390/kvm/gaccess.c rc = gmap_shadow_r3t(sg, saddr, rste.val, *fake); val 1085 arch/s390/kvm/gaccess.c rtte.val = ptr; val 1088 arch/s390/kvm/gaccess.c rc = gmap_read_table(parent, ptr + vaddr.rtx * 8, &rtte.val); val 1101 arch/s390/kvm/gaccess.c rtte.val = ptr; val 1111 arch/s390/kvm/gaccess.c rc = gmap_shadow_sgt(sg, saddr, rtte.val, *fake); val 1120 arch/s390/kvm/gaccess.c ste.val = ptr; val 1123 arch/s390/kvm/gaccess.c rc = gmap_read_table(parent, ptr + vaddr.sx * 8, &ste.val); val 1136 arch/s390/kvm/gaccess.c ste.val = ptr; val 1142 arch/s390/kvm/gaccess.c rc = gmap_shadow_pgt(sg, saddr, ste.val, *fake); val 1188 arch/s390/kvm/gaccess.c pte.val = pgt + vaddr.px * PAGE_SIZE; val 1192 arch/s390/kvm/gaccess.c rc = gmap_read_table(sg->parent, pgt + vaddr.px * 8, &pte.val); val 1200 arch/s390/kvm/gaccess.c rc = gmap_shadow_page(sg, saddr, __pte(pte.val)); val 556 arch/s390/kvm/interrupt.c mci.val = mchk->mcic; val 610 arch/s390/kvm/interrupt.c rc |= put_guest_lc(vcpu, mci.val, (u64 __user *) __LC_MCCK_CODE); val 2793 arch/s390/kvm/interrupt.c mci.val = mcck_info->mcic; val 266 arch/s390/kvm/kvm-s390.c static int kvm_clock_sync(struct notifier_block *notifier, unsigned long val, val 3245 arch/s390/kvm/kvm-s390.c __u64 val; val 3257 arch/s390/kvm/kvm-s390.c r = get_user(val, (u64 __user *)reg->addr); val 3259 arch/s390/kvm/kvm-s390.c kvm_s390_set_cpu_timer(vcpu, val); val 1096 arch/s390/kvm/vsie.c cr0.val = vcpu->arch.sie_block->gcr[0]; val 1129 arch/s390/mm/gmap.c int gmap_read_table(struct gmap *gmap, unsigned long gaddr, unsigned long *val) val 1147 arch/s390/mm/gmap.c *val = *(unsigned long *) address; val 54 arch/s390/mm/kasan_init.c static void * __init kasan_early_crst_alloc(unsigned long val) val 60 arch/s390/mm/kasan_init.c crst_table_init(table, val); val 351 arch/s390/mm/pgalloc.c static unsigned long base_crst_alloc(unsigned long val) val 357 arch/s390/mm/pgalloc.c crst_table_init((unsigned long *)table, val); val 41 arch/s390/mm/vmem.c void *vmem_crst_alloc(unsigned long val) val 47 arch/s390/mm/vmem.c crst_table_init(table, val); val 279 arch/s390/net/bpf_jit_comp.c #define EMIT_CONST_U32(val) \ val 285 arch/s390/net/bpf_jit_comp.c *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \ val 290 arch/s390/net/bpf_jit_comp.c #define EMIT_CONST_U64(val) \ val 296 arch/s390/net/bpf_jit_comp.c *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \ val 188 arch/s390/pci/pci.c static int zpci_cfg_load(struct zpci_dev *zdev, int offset, u32 *val, u8 len) val 198 arch/s390/pci/pci.c *val = (u32) data; val 200 arch/s390/pci/pci.c *val = 0xffffffff; val 204 arch/s390/pci/pci.c static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len) val 207 arch/s390/pci/pci.c u64 data = val; val 372 arch/s390/pci/pci.c int size, u32 *val) val 380 arch/s390/pci/pci.c ret = zpci_cfg_load(zdev, where, val, size); val 386 arch/s390/pci/pci.c int size, u32 val) val 394 arch/s390/pci/pci.c ret = zpci_cfg_store(zdev, where, val, size); val 527 arch/s390/pci/pci.c if (zdev->bars[i].val & 8) val 529 arch/s390/pci/pci.c if (zdev->bars[i].val & 4) val 149 arch/s390/pci/pci_clp.c zdev->bars[i].val = le32_to_cpu(response->bar[i]); val 135 arch/s390/pci/pci_debug.c unsigned long val; val 141 arch/s390/pci/pci_debug.c rc = kstrtoul_from_user(ubuf, count, 10, &val); val 146 arch/s390/pci/pci_debug.c switch (val) { val 55 arch/s390/pci/pci_mmio.c u64 val = 0; val 78 arch/s390/pci/pci_mmio.c [val] "+d" (val), [tmp] "=d" (tmp), val 206 arch/s390/pci/pci_mmio.c u64 val, tmp; val 228 arch/s390/pci/pci_mmio.c [cc] "+d" (cc), [val] "=d" (val), [len] "+d" (len), val 78 arch/sh/boards/mach-cayman/setup.c #define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \ val 80 arch/sh/boards/mach-cayman/setup.c outb((val), SMSC_DATA_PORT_ADDR); }) val 581 arch/sh/boards/mach-ecovec24/setup.c int val = 0; val 586 arch/sh/boards/mach-ecovec24/setup.c val = gpio_get_value(GPIO_PTZ0); val 591 arch/sh/boards/mach-ecovec24/setup.c return val ? 0 : 1; val 46 arch/sh/boards/mach-microdev/fdc37c93xapm.c #define SMSC_WRITE_INDEXED(val, index) ({ \ val 48 arch/sh/boards/mach-microdev/fdc37c93xapm.c outb((val), SMSC_DATA_PORT_ADDR); }) val 32 arch/sh/boards/mach-se/7206/irq.c unsigned short val; val 37 arch/sh/boards/mach-se/7206/irq.c val = __raw_readw(INTC_IPR01); val 38 arch/sh/boards/mach-se/7206/irq.c val &= mask; val 39 arch/sh/boards/mach-se/7206/irq.c __raw_writew(val, INTC_IPR01); val 63 arch/sh/boards/mach-se/7206/irq.c unsigned short val; val 68 arch/sh/boards/mach-se/7206/irq.c val = __raw_readw(INTC_IPR01); val 69 arch/sh/boards/mach-se/7206/irq.c val |= value; val 70 arch/sh/boards/mach-se/7206/irq.c __raw_writew(val, INTC_IPR01); val 46 arch/sh/drivers/pci/ops-dreamcast.c static int gapspci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) val 48 arch/sh/drivers/pci/ops-dreamcast.c *val = 0xffffffff; val 54 arch/sh/drivers/pci/ops-dreamcast.c case 1: *val = inb(GAPSPCI_BBA_CONFIG+where); break; val 55 arch/sh/drivers/pci/ops-dreamcast.c case 2: *val = inw(GAPSPCI_BBA_CONFIG+where); break; val 56 arch/sh/drivers/pci/ops-dreamcast.c case 4: *val = inl(GAPSPCI_BBA_CONFIG+where); break; val 62 arch/sh/drivers/pci/ops-dreamcast.c static int gapspci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) val 68 arch/sh/drivers/pci/ops-dreamcast.c case 1: outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break; val 69 arch/sh/drivers/pci/ops-dreamcast.c case 2: outw((u16)val, GAPSPCI_BBA_CONFIG+where); break; val 70 arch/sh/drivers/pci/ops-dreamcast.c case 4: outl((u32)val, GAPSPCI_BBA_CONFIG+where); break; val 23 arch/sh/drivers/pci/ops-sh4.c int where, int size, u32 *val) val 40 arch/sh/drivers/pci/ops-sh4.c *val = (data >> ((where & 3) << 3)) & 0xff; val 43 arch/sh/drivers/pci/ops-sh4.c *val = (data >> ((where & 2) << 3)) & 0xffff; val 46 arch/sh/drivers/pci/ops-sh4.c *val = data; val 61 arch/sh/drivers/pci/ops-sh4.c int where, int size, u32 val) val 77 arch/sh/drivers/pci/ops-sh4.c data |= ((val & 0xff) << shift); val 82 arch/sh/drivers/pci/ops-sh4.c data |= ((val & 0xffff) << shift); val 85 arch/sh/drivers/pci/ops-sh4.c data = val; val 23 arch/sh/drivers/pci/ops-sh5.c int size, u32 *val) val 29 arch/sh/drivers/pci/ops-sh5.c *val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3)); val 32 arch/sh/drivers/pci/ops-sh5.c *val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2)); val 35 arch/sh/drivers/pci/ops-sh5.c *val = SH5PCI_READ(PDR); val 43 arch/sh/drivers/pci/ops-sh5.c int size, u32 val) val 49 arch/sh/drivers/pci/ops-sh5.c SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val); val 52 arch/sh/drivers/pci/ops-sh5.c SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val); val 55 arch/sh/drivers/pci/ops-sh5.c SH5PCI_WRITE(PDR, val); val 90 arch/sh/drivers/pci/ops-sh7786.c int where, int size, u32 *val) val 105 arch/sh/drivers/pci/ops-sh7786.c *val = 0xffffffff; val 110 arch/sh/drivers/pci/ops-sh7786.c *val = (data >> ((where & 3) << 3)) & 0xff; val 112 arch/sh/drivers/pci/ops-sh7786.c *val = (data >> ((where & 2) << 3)) & 0xffff; val 114 arch/sh/drivers/pci/ops-sh7786.c *val = data; val 118 arch/sh/drivers/pci/ops-sh7786.c devfn, where, size, (unsigned long)*val); val 126 arch/sh/drivers/pci/ops-sh7786.c int where, int size, u32 val) val 145 arch/sh/drivers/pci/ops-sh7786.c devfn, where, size, (unsigned long)val); val 150 arch/sh/drivers/pci/ops-sh7786.c data |= ((val & 0xff) << shift); val 154 arch/sh/drivers/pci/ops-sh7786.c data |= ((val & 0xffff) << shift); val 156 arch/sh/drivers/pci/ops-sh7786.c data = val; val 171 arch/sh/drivers/pci/pci-sh4.h unsigned long val, unsigned long reg) val 173 arch/sh/drivers/pci/pci-sh4.h __raw_writel(val, chan->reg_base + reg); val 87 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg)) val 88 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg)) val 89 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg)) val 566 arch/sh/drivers/pci/pcie-sh7786.h pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg) val 568 arch/sh/drivers/pci/pcie-sh7786.h __raw_writel(val, chan->reg_base + reg); val 17 arch/sh/include/asm/cache_insns_32.h static inline reg_size_t register_align(void *val) val 19 arch/sh/include/asm/cache_insns_32.h return (unsigned long)(signed long)val; val 15 arch/sh/include/asm/cache_insns_64.h static inline reg_size_t register_align(void *val) val 17 arch/sh/include/asm/cache_insns_64.h return (unsigned long long)(signed long long)(signed long)val; val 15 arch/sh/include/asm/cmpxchg-cas.h static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) val 19 arch/sh/include/asm/cmpxchg-cas.h while (__cmpxchg_u32(m, old, val) != old); val 5 arch/sh/include/asm/cmpxchg-grb.h static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) val 20 arch/sh/include/asm/cmpxchg-grb.h "+r" (val) /* inhibit r15 overloading */ val 27 arch/sh/include/asm/cmpxchg-grb.h static inline unsigned long xchg_u16(volatile u16 *m, unsigned long val) val 42 arch/sh/include/asm/cmpxchg-grb.h "+r" (val) /* inhibit r15 overloading */ val 49 arch/sh/include/asm/cmpxchg-grb.h static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) val 64 arch/sh/include/asm/cmpxchg-grb.h "+r" (val) /* inhibit r15 overloading */ val 7 arch/sh/include/asm/cmpxchg-irq.h static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) val 13 arch/sh/include/asm/cmpxchg-irq.h *m = val; val 18 arch/sh/include/asm/cmpxchg-irq.h static inline unsigned long xchg_u16(volatile u16 *m, unsigned long val) val 24 arch/sh/include/asm/cmpxchg-irq.h *m = val; val 29 arch/sh/include/asm/cmpxchg-irq.h static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) val 35 arch/sh/include/asm/cmpxchg-irq.h *m = val & 0xff; val 5 arch/sh/include/asm/cmpxchg-llsc.h static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) val 19 arch/sh/include/asm/cmpxchg-llsc.h : "r" (m), "r" (val) val 40 arch/sh/include/asm/cmpxchg-xchg.h static inline unsigned long xchg_u16(volatile u16 *m, unsigned long val) val 42 arch/sh/include/asm/cmpxchg-xchg.h return __xchg_cmpxchg(m, val, sizeof *m); val 45 arch/sh/include/asm/cmpxchg-xchg.h static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) val 47 arch/sh/include/asm/cmpxchg-xchg.h return __xchg_cmpxchg(m, val, sizeof *m); val 62 arch/sh/include/asm/hw_breakpoint.h unsigned long val, void *data); val 161 arch/sh/include/asm/io.h static inline void pfx##out##bwlq##p(type val, unsigned long port) \ val 166 arch/sh/include/asm/io.h *__addr = val; \ val 240 arch/sh/include/asm/io.h unsigned long long val); val 50 arch/sh/include/asm/kprobes.h unsigned long val, void *data); val 41 arch/sh/include/asm/pgtable.h static inline unsigned long long neff_sign_extend(unsigned long val) val 43 arch/sh/include/asm/pgtable.h unsigned long long extended = val; val 461 arch/sh/include/asm/pgtable_32.h #define __swp_type(x) ((x).val & 0x1f) val 462 arch/sh/include/asm/pgtable_32.h #define __swp_offset(x) ((x).val >> 5) val 465 arch/sh/include/asm/pgtable_32.h #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val }) val 468 arch/sh/include/asm/pgtable_32.h #define __swp_type(x) ((x).val & 0xff) val 469 arch/sh/include/asm/pgtable_32.h #define __swp_offset(x) ((x).val >> 10) val 473 arch/sh/include/asm/pgtable_32.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 }) val 296 arch/sh/include/asm/pgtable_64.h #define __swp_type(x) (((x).val & 3) + (((x).val >> 1) & 0x3c)) val 297 arch/sh/include/asm/pgtable_64.h #define __swp_offset(x) ((x).val >> 8) val 300 arch/sh/include/asm/pgtable_64.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 121 arch/sh/include/asm/processor.h extern int set_unalign_ctl(struct task_struct *, unsigned int val); val 124 arch/sh/include/asm/processor.h #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) val 24 arch/sh/include/asm/ptrace.h unsigned long val) val 26 arch/sh/include/asm/ptrace.h regs->pc = val; val 40 arch/sh/include/asm/ptrace.h unsigned long val) val 42 arch/sh/include/asm/ptrace.h regs->regs[15] = val; val 41 arch/sh/include/asm/syscall_32.h int error, long val) val 46 arch/sh/include/asm/syscall_32.h regs->regs[0] = val; val 40 arch/sh/include/asm/syscall_64.h int error, long val) val 45 arch/sh/include/asm/syscall_64.h regs->regs[9] = val; val 161 arch/sh/include/asm/thread_info.h static inline void set_thread_fault_code(unsigned int val) val 165 arch/sh/include/asm/thread_info.h | (val << TI_FLAG_FAULT_CODE_SHIFT); val 127 arch/sh/include/asm/uaccess_32.h #define __put_user_u64(val,addr,retval) \ val 146 arch/sh/include/asm/uaccess_32.h : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \ val 149 arch/sh/include/asm/uaccess_32.h #define __put_user_u64(val,addr,retval) \ val 168 arch/sh/include/asm/uaccess_32.h : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \ val 94 arch/sh/include/asm/unaligned-sh4a.h static inline void nonnative_put_le16(u16 val, u8 *p) val 96 arch/sh/include/asm/unaligned-sh4a.h *p++ = val; val 97 arch/sh/include/asm/unaligned-sh4a.h *p++ = val >> 8; val 100 arch/sh/include/asm/unaligned-sh4a.h static inline void nonnative_put_le32(u32 val, u8 *p) val 102 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_le16(val, p); val 103 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_le16(val >> 16, p + 2); val 106 arch/sh/include/asm/unaligned-sh4a.h static inline void nonnative_put_le64(u64 val, u8 *p) val 108 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_le32(val, p); val 109 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_le32(val >> 32, p + 4); val 112 arch/sh/include/asm/unaligned-sh4a.h static inline void nonnative_put_be16(u16 val, u8 *p) val 114 arch/sh/include/asm/unaligned-sh4a.h *p++ = val >> 8; val 115 arch/sh/include/asm/unaligned-sh4a.h *p++ = val; val 118 arch/sh/include/asm/unaligned-sh4a.h static inline void nonnative_put_be32(u32 val, u8 *p) val 120 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_be16(val >> 16, p); val 121 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_be16(val, p + 2); val 124 arch/sh/include/asm/unaligned-sh4a.h static inline void nonnative_put_be64(u64 val, u8 *p) val 126 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_be32(val >> 32, p); val 127 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_be32(val, p + 4); val 130 arch/sh/include/asm/unaligned-sh4a.h static inline void put_unaligned_le16(u16 val, void *p) val 133 arch/sh/include/asm/unaligned-sh4a.h __put_unaligned_cpu16(val, p); val 135 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_le16(val, p); val 139 arch/sh/include/asm/unaligned-sh4a.h static inline void put_unaligned_le32(u32 val, void *p) val 142 arch/sh/include/asm/unaligned-sh4a.h __put_unaligned_cpu32(val, p); val 144 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_le32(val, p); val 148 arch/sh/include/asm/unaligned-sh4a.h static inline void put_unaligned_le64(u64 val, void *p) val 151 arch/sh/include/asm/unaligned-sh4a.h __put_unaligned_cpu64(val, p); val 153 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_le64(val, p); val 157 arch/sh/include/asm/unaligned-sh4a.h static inline void put_unaligned_be16(u16 val, void *p) val 160 arch/sh/include/asm/unaligned-sh4a.h __put_unaligned_cpu16(val, p); val 162 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_be16(val, p); val 166 arch/sh/include/asm/unaligned-sh4a.h static inline void put_unaligned_be32(u32 val, void *p) val 169 arch/sh/include/asm/unaligned-sh4a.h __put_unaligned_cpu32(val, p); val 171 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_be32(val, p); val 175 arch/sh/include/asm/unaligned-sh4a.h static inline void put_unaligned_be64(u64 val, void *p) val 178 arch/sh/include/asm/unaligned-sh4a.h __put_unaligned_cpu64(val, p); val 180 arch/sh/include/asm/unaligned-sh4a.h nonnative_put_be64(val, p); val 79 arch/sh/include/asm/watchdog.h static inline void sh_wdt_write_cnt(__u32 val) val 81 arch/sh/include/asm/watchdog.h __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT); val 91 arch/sh/include/asm/watchdog.h static inline void sh_wdt_write_bst(__u32 val) val 93 arch/sh/include/asm/watchdog.h __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST); val 112 arch/sh/include/asm/watchdog.h static inline void sh_wdt_write_csr(__u32 val) val 114 arch/sh/include/asm/watchdog.h __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR); val 133 arch/sh/include/asm/watchdog.h static inline void sh_wdt_write_cnt(__u8 val) val 135 arch/sh/include/asm/watchdog.h __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT); val 155 arch/sh/include/asm/watchdog.h static inline void sh_wdt_write_csr(__u8 val) val 157 arch/sh/include/asm/watchdog.h __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR); val 55 arch/sh/include/cpu-sh2/cpu/watchdog.h static inline void sh_wdt_write_rstcsr(__u8 val) val 62 arch/sh/include/cpu-sh2/cpu/watchdog.h __raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR); val 41 arch/sh/include/mach-common/mach/secureedge5410.h #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ val 43 arch/sh/include/mach-common/mach/secureedge5410.h ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) val 151 arch/sh/include/mach-sdk7786/mach/fpga.h static inline void fpga_write_reg(u16 val, unsigned int reg) val 153 arch/sh/include/mach-sdk7786/mach/fpga.h iowrite16(val, sdk7786_fpga_base + reg); val 47 arch/sh/include/uapi/asm/swab.h static inline __u64 __arch_swab64(__u64 val) val 53 arch/sh/include/uapi/asm/swab.h v.u = val; val 112 arch/sh/kernel/cpu/sh2/smp-j2.c unsigned long val; val 121 arch/sh/kernel/cpu/sh2/smp-j2.c val = __raw_readl(j2_ipi_trigger + cpu); val 122 arch/sh/kernel/cpu/sh2/smp-j2.c __raw_writel(val | (1U<<28), j2_ipi_trigger + cpu); val 411 arch/sh/kernel/cpu/sh4a/setup-sh7786.c u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; val 412 arch/sh/kernel/cpu/sh4a/setup-sh7786.c __raw_writel(val | EXT_CLOCK_MODE, USBCTL0); val 528 arch/sh/kernel/disassemble.c u32 val; val 531 arch/sh/kernel/disassemble.c __get_user(val, (u16 *)disp_pc_addr); val 533 arch/sh/kernel/disassemble.c __get_user(val, (u32 *)disp_pc_addr); val 535 arch/sh/kernel/disassemble.c printk(" ! %08x <%pS>", val, (void *)val); val 30 arch/sh/kernel/dumpstack.c unsigned int val; val 35 arch/sh/kernel/dumpstack.c if (__get_user(val, (unsigned int __user *)p)) { val 39 arch/sh/kernel/dumpstack.c printk("%08x ", val); val 130 arch/sh/kernel/dwarf.c u32 val = get_unaligned(src); val 131 arch/sh/kernel/dwarf.c put_unaligned(val, dst); val 223 arch/sh/kernel/dwarf.c static int dwarf_read_encoded_value(char *addr, unsigned long *val, val 248 arch/sh/kernel/dwarf.c __raw_writel(decoded_addr, val); val 370 arch/sh/kernel/hw_breakpoint.c unsigned long val, void *data) val 374 arch/sh/kernel/hw_breakpoint.c if (val != DIE_BREAKPOINT) val 41 arch/sh/kernel/iomap.c void iowrite8(u8 val, void __iomem *addr) val 43 arch/sh/kernel/iomap.c writeb(val, addr); val 47 arch/sh/kernel/iomap.c void iowrite16(u16 val, void __iomem *addr) val 49 arch/sh/kernel/iomap.c writew(val, addr); val 53 arch/sh/kernel/iomap.c void iowrite16be(u16 val, void __iomem *addr) val 55 arch/sh/kernel/iomap.c __raw_writew(cpu_to_be16(val), addr); val 59 arch/sh/kernel/iomap.c void iowrite32(u32 val, void __iomem *addr) val 61 arch/sh/kernel/iomap.c writel(val, addr); val 65 arch/sh/kernel/iomap.c void iowrite32be(u32 val, void __iomem *addr) val 67 arch/sh/kernel/iomap.c __raw_writel(cpu_to_be32(val), addr); val 479 arch/sh/kernel/kprobes.c unsigned long val, void *data) val 488 arch/sh/kernel/kprobes.c if (val == DIE_TRAP && val 22 arch/sh/kernel/nmi_debug.c unsigned long val, void *data) val 26 arch/sh/kernel/nmi_debug.c if (likely(val != DIE_NMI)) val 282 arch/sh/kernel/traps_64.c __u64 val = regs->regs[srcreg]; val 286 arch/sh/kernel/traps_64.c misaligned_kernel_word_store(address, val); val 289 arch/sh/kernel/traps_64.c asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address)); val 290 arch/sh/kernel/traps_64.c asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address)); val 293 arch/sh/kernel/traps_64.c asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address)); val 294 arch/sh/kernel/traps_64.c asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address)); val 796 arch/sh/kernel/traps_64.c u64 poke_real_address_q(u64 addr, u64 val); val 89 arch/sh/mm/alignment.c int set_unalign_ctl(struct task_struct *tsk, unsigned int val) val 92 arch/sh/mm/alignment.c (val & SH_THREAD_UAC_MASK); val 96 arch/sh/mm/tlb-debugfs.c unsigned long val; val 100 arch/sh/mm/tlb-debugfs.c val = __raw_readl(addr1 | (entry << MMU_TLB_ENTRY_SHIFT)); val 102 arch/sh/mm/tlb-debugfs.c vpn = val & 0xfffffc00; val 103 arch/sh/mm/tlb-debugfs.c valid = val & 0x100; val 105 arch/sh/mm/tlb-debugfs.c val = __raw_readl(addr2 | (entry << MMU_TLB_ENTRY_SHIFT)); val 107 arch/sh/mm/tlb-debugfs.c asid = val & MMU_CONTEXT_ASID_MASK; val 109 arch/sh/mm/tlb-debugfs.c val = __raw_readl(data1 | (entry << MMU_TLB_ENTRY_SHIFT)); val 111 arch/sh/mm/tlb-debugfs.c ppn = (val & 0x0ffffc00) << 4; val 113 arch/sh/mm/tlb-debugfs.c val = __raw_readl(data2 | (entry << MMU_TLB_ENTRY_SHIFT)); val 115 arch/sh/mm/tlb-debugfs.c size = (val & 0xf0) >> 4; val 21 arch/sparc/include/asm/cmpxchg_64.h static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) val 32 arch/sparc/include/asm/cmpxchg_64.h : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2) val 33 arch/sparc/include/asm/cmpxchg_64.h : "0" (val), "r" (m) val 35 arch/sparc/include/asm/cmpxchg_64.h return val; val 38 arch/sparc/include/asm/cmpxchg_64.h static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val) val 49 arch/sparc/include/asm/cmpxchg_64.h : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2) val 50 arch/sparc/include/asm/cmpxchg_64.h : "0" (val), "r" (m) val 52 arch/sparc/include/asm/cmpxchg_64.h return val; val 70 arch/sparc/include/asm/cmpxchg_64.h xchg16(__volatile__ unsigned short *m, unsigned short val) val 83 arch/sparc/include/asm/cmpxchg_64.h new32 = (load32 & (~mask)) | val << bit_shift; val 204 arch/sparc/include/asm/floppy_64.h u8 val; val 207 arch/sparc/include/asm/floppy_64.h val = readb(stat); val 208 arch/sparc/include/asm/floppy_64.h if (unlikely(!(val & 0x80))) { val 213 arch/sparc/include/asm/floppy_64.h if (unlikely(!(val & 0x20))) { val 219 arch/sparc/include/asm/floppy_64.h if (val & 0x40) { val 235 arch/sparc/include/asm/floppy_64.h val = readb(auxio_register); val 236 arch/sparc/include/asm/floppy_64.h val |= AUXIO_AUX1_FTCNT; val 237 arch/sparc/include/asm/floppy_64.h writeb(val, auxio_register); val 238 arch/sparc/include/asm/floppy_64.h val &= ~AUXIO_AUX1_FTCNT; val 239 arch/sparc/include/asm/floppy_64.h writeb(val, auxio_register); val 307 arch/sparc/include/asm/floppy_64.h static void sun_pci_fd_outb(unsigned char val, unsigned long port) val 310 arch/sparc/include/asm/floppy_64.h outb(val, port); val 313 arch/sparc/include/asm/floppy_64.h static void sun_pci_fd_broken_outb(unsigned char val, unsigned long port) val 324 arch/sparc/include/asm/floppy_64.h if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x20)) { val 325 arch/sparc/include/asm/floppy_64.h val |= 0x10; val 328 arch/sparc/include/asm/floppy_64.h outb(val, port); val 332 arch/sparc/include/asm/floppy_64.h static void sun_pci_fd_lde_broken_outb(unsigned char val, unsigned long port) val 343 arch/sparc/include/asm/floppy_64.h if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x10)) { val 344 arch/sparc/include/asm/floppy_64.h val &= ~(0x03); val 345 arch/sparc/include/asm/floppy_64.h val |= 0x21; val 348 arch/sparc/include/asm/floppy_64.h outb(val, port); val 446 arch/sparc/include/asm/floppy_64.h static void sun_pci_fd_out_byte(unsigned long port, unsigned char val, val 454 arch/sparc/include/asm/floppy_64.h outb(val, reg); val 29 arch/sparc/include/asm/fpumacro.h static inline void fprs_write(unsigned long val) val 31 arch/sparc/include/asm/fpumacro.h __asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val)); val 8 arch/sparc/include/asm/head_64.h #define SET_GL(val) \ val 9 arch/sparc/include/asm/head_64.h .word 0xa1902000 | val val 3235 arch/sparc/include/asm/hypervisor.h unsigned long *val); val 3237 arch/sparc/include/asm/hypervisor.h unsigned long val); val 3239 arch/sparc/include/asm/hypervisor.h unsigned long *val); val 3241 arch/sparc/include/asm/hypervisor.h unsigned long val); val 51 arch/sparc/include/asm/kprobes.h unsigned long val, void *data); val 125 arch/sparc/include/asm/leon_amba.h u32 val; val 23 arch/sparc/include/asm/mc146818rtc_32.h #define CMOS_WRITE(val, addr) ({ \ val 25 arch/sparc/include/asm/mc146818rtc_32.h outb_p((val),RTC_PORT(1)); \ val 24 arch/sparc/include/asm/mc146818rtc_64.h #define CMOS_WRITE(val, addr) ({ \ val 26 arch/sparc/include/asm/mc146818rtc_64.h outb_p((val),RTC_PORT(1)); \ val 177 arch/sparc/include/asm/openprom.h int (*no_getprop)(phandle node, const char *name, char *val); val 178 arch/sparc/include/asm/openprom.h int (*no_setprop)(phandle node, const char *name, char *val, int len); val 354 arch/sparc/include/asm/pgtable_32.h return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK; val 359 arch/sparc/include/asm/pgtable_32.h return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK; val 370 arch/sparc/include/asm/pgtable_32.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 351 arch/sparc/include/asm/pgtable_64.h unsigned long val = pgprot_val(prot); val 366 arch/sparc/include/asm/pgtable_64.h : "=r" (val) val 367 arch/sparc/include/asm/pgtable_64.h : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), val 371 arch/sparc/include/asm/pgtable_64.h return __pgprot(val); val 443 arch/sparc/include/asm/pgtable_64.h unsigned long val = pte_val(pte), tmp; val 458 arch/sparc/include/asm/pgtable_64.h : "=r" (val), "=r" (tmp) val 459 arch/sparc/include/asm/pgtable_64.h : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), val 462 arch/sparc/include/asm/pgtable_64.h return __pte(val); val 467 arch/sparc/include/asm/pgtable_64.h unsigned long val = pte_val(pte), tmp; val 482 arch/sparc/include/asm/pgtable_64.h : "=r" (val), "=r" (tmp) val 483 arch/sparc/include/asm/pgtable_64.h : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), val 486 arch/sparc/include/asm/pgtable_64.h return __pte(val); val 491 arch/sparc/include/asm/pgtable_64.h unsigned long val = pte_val(pte), mask; val 504 arch/sparc/include/asm/pgtable_64.h return __pte(val | mask); val 509 arch/sparc/include/asm/pgtable_64.h unsigned long val = pte_val(pte), tmp; val 524 arch/sparc/include/asm/pgtable_64.h : "=r" (val), "=r" (tmp) val 525 arch/sparc/include/asm/pgtable_64.h : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), val 528 arch/sparc/include/asm/pgtable_64.h return __pte(val); val 661 arch/sparc/include/asm/pgtable_64.h unsigned long val = pte_val(pte); val 669 arch/sparc/include/asm/pgtable_64.h : "=r" (val) val 670 arch/sparc/include/asm/pgtable_64.h : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); val 672 arch/sparc/include/asm/pgtable_64.h return val; val 788 arch/sparc/include/asm/pgtable_64.h unsigned long val = pmd_val(entry); val 790 arch/sparc/include/asm/pgtable_64.h return __pgprot(val); val 830 arch/sparc/include/asm/pgtable_64.h unsigned long val = __pa((unsigned long) (ptep)); val 832 arch/sparc/include/asm/pgtable_64.h pmd_val(*pmdp) = val; val 1010 arch/sparc/include/asm/pgtable_64.h #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) val 1011 arch/sparc/include/asm/pgtable_64.h #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) val 1019 arch/sparc/include/asm/pgtable_64.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 33 arch/sparc/include/asm/prom.h int of_set_property(struct device_node *node, const char *name, void *val, int len); val 66 arch/sparc/include/asm/ptrace.h #define instruction_pointer_set(regs, val) do { \ val 67 arch/sparc/include/asm/ptrace.h (regs)->tpc = (val); \ val 68 arch/sparc/include/asm/ptrace.h (regs)->tnpc = (val)+4; \ val 144 arch/sparc/include/asm/spinlock_32.h unsigned int val; val 147 arch/sparc/include/asm/spinlock_32.h : "=r" (val) val 151 arch/sparc/include/asm/spinlock_32.h if (val == 0) { val 152 arch/sparc/include/asm/spinlock_32.h val = rw->lock & ~0xff; val 153 arch/sparc/include/asm/spinlock_32.h if (val) val 159 arch/sparc/include/asm/spinlock_32.h return (val == 0); val 71 arch/sparc/include/asm/syscall.h long val = regs->u_regs[UREG_I0]; val 73 arch/sparc/include/asm/syscall.h return (syscall_has_error(regs) ? -val : 0); val 79 arch/sparc/include/asm/syscall.h long val = regs->u_regs[UREG_I0]; val 81 arch/sparc/include/asm/syscall.h return val; val 86 arch/sparc/include/asm/syscall.h int error, long val) val 93 arch/sparc/include/asm/syscall.h regs->u_regs[UREG_I0] = val; val 111 arch/sparc/include/asm/syscall.h unsigned long val = regs->u_regs[UREG_I0 + j]; val 114 arch/sparc/include/asm/syscall.h args[j] = (u32) val; val 116 arch/sparc/include/asm/syscall.h args[j] = val; val 143 arch/sparc/include/asm/thread_info_64.h #define set_thread_fault_code(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE] = (val)) val 145 arch/sparc/include/asm/thread_info_64.h #define set_thread_wstate(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE] = (val)) val 147 arch/sparc/include/asm/thread_info_64.h #define set_thread_cwp(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP] = (val)) val 149 arch/sparc/include/asm/thread_info_64.h #define set_thread_noerror(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_NOERROR] = (val)) val 151 arch/sparc/include/asm/thread_info_64.h #define set_thread_fpdepth(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH] = (val)) val 153 arch/sparc/include/asm/thread_info_64.h #define set_thread_wsaved(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED] = (val)) val 29 arch/sparc/include/asm/uaccess_32.h #define set_fs(val) ((current->thread.current_ds) = (val)) val 37 arch/sparc/include/asm/uaccess_64.h #define set_fs(val) \ val 39 arch/sparc/include/asm/uaccess_64.h current_thread_info()->current_ds = (val).seg; \ val 40 arch/sparc/include/asm/uaccess_64.h __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" ((val).seg)); \ val 44 arch/sparc/include/asm/uprobes.h extern int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data); val 23 arch/sparc/include/asm/vga.h static inline void scr_writew(u16 val, u16 *addr) val 27 arch/sparc/include/asm/vga.h *addr = val; val 215 arch/sparc/include/asm/viking.h unsigned long val; val 220 arch/sparc/include/asm/viking.h : "=r" (val) val 222 arch/sparc/include/asm/viking.h if (!val) val 227 arch/sparc/include/asm/viking.h : "=r" (val) val 229 arch/sparc/include/asm/viking.h if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) { val 232 arch/sparc/include/asm/viking.h return val | (vaddr << 8); val 237 arch/sparc/include/asm/viking.h : "=r" (val) val 239 arch/sparc/include/asm/viking.h if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) { val 242 arch/sparc/include/asm/viking.h return val | (vaddr << 8); val 247 arch/sparc/include/asm/viking.h : "=r" (val) val 249 arch/sparc/include/asm/viking.h return val; val 42 arch/sparc/kernel/adi_64.c u64 pn, *val; val 85 arch/sparc/kernel/adi_64.c val = (u64 *) mdesc_get_property(hp, pn, "adp-blksz", &len); val 86 arch/sparc/kernel/adi_64.c if (!val) val 88 arch/sparc/kernel/adi_64.c adi_state.caps.blksz = *val; val 90 arch/sparc/kernel/adi_64.c val = (u64 *) mdesc_get_property(hp, pn, "adp-nbits", &len); val 91 arch/sparc/kernel/adi_64.c if (!val) val 93 arch/sparc/kernel/adi_64.c adi_state.caps.nbits = *val; val 95 arch/sparc/kernel/adi_64.c val = (u64 *) mdesc_get_property(hp, pn, "ue-on-adp", &len); val 96 arch/sparc/kernel/adi_64.c if (!val) val 98 arch/sparc/kernel/adi_64.c adi_state.caps.ue_on_adi = *val; val 39 arch/sparc/kernel/apc.c #define apc_writeb(val, offs) (sbus_writeb(val, regs+offs)) val 615 arch/sparc/kernel/chmc.c static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val) val 619 arch/sparc/kernel/chmc.c : : "r" (val), val 623 arch/sparc/kernel/chmc.c : : "r" (val), val 630 arch/sparc/kernel/chmc.c static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val) val 636 arch/sparc/kernel/chmc.c bp->raw_reg = val; val 637 arch/sparc/kernel/chmc.c bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT; val 638 arch/sparc/kernel/chmc.c bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT; val 639 arch/sparc/kernel/chmc.c bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT; val 640 arch/sparc/kernel/chmc.c bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT; val 641 arch/sparc/kernel/chmc.c bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT; val 1169 arch/sparc/kernel/ds.c const u64 *val; val 1181 arch/sparc/kernel/ds.c val = mdesc_get_property(hp, vdev->mp, "id", NULL); val 1182 arch/sparc/kernel/ds.c if (val) val 1183 arch/sparc/kernel/ds.c dp->id = *val; val 53 arch/sparc/kernel/ebus.c u32 val = 0; val 62 arch/sparc/kernel/ebus.c val = readl(p->regs + EBDMA_CSR); val 64 arch/sparc/kernel/ebus.c if (!(val & (EBDMA_CSR_DRAIN | EBDMA_CSR_CYC_PEND))) val 85 arch/sparc/kernel/iommu.c unsigned long val = iopte_val(*iopte); val 87 arch/sparc/kernel/iommu.c val &= ~IOPTE_PAGE; val 88 arch/sparc/kernel/iommu.c val |= iommu->dummy_page_pa; val 90 arch/sparc/kernel/iommu.c iopte_val(*iopte) = val; val 329 arch/sparc/kernel/iommu.c u64 val; val 335 arch/sparc/kernel/iommu.c val = iommu_read(matchreg); val 336 arch/sparc/kernel/iommu.c val &= 0xffff; val 337 arch/sparc/kernel/iommu.c if (!val) val 340 arch/sparc/kernel/iommu.c while (val) { val 341 arch/sparc/kernel/iommu.c if (val & 0x1) val 343 arch/sparc/kernel/iommu.c val >>= 1; val 345 arch/sparc/kernel/iommu.c val = iommu_read(matchreg); val 346 arch/sparc/kernel/iommu.c if (unlikely(val)) { val 349 arch/sparc/kernel/iommu.c val, ctx); val 377 arch/sparc/kernel/irq_64.c unsigned long cpuid, imap, val; val 386 arch/sparc/kernel/irq_64.c val = upa_readq(imap); val 387 arch/sparc/kernel/irq_64.c val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | val 389 arch/sparc/kernel/irq_64.c val |= tid | IMAP_VALID; val 390 arch/sparc/kernel/irq_64.c upa_writeq(val, imap); val 402 arch/sparc/kernel/irq_64.c unsigned long cpuid, imap, val; val 410 arch/sparc/kernel/irq_64.c val = upa_readq(imap); val 411 arch/sparc/kernel/irq_64.c val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | val 413 arch/sparc/kernel/irq_64.c val |= tid | IMAP_VALID; val 414 arch/sparc/kernel/irq_64.c upa_writeq(val, imap); val 16 arch/sparc/kernel/jump_label.c u32 val; val 31 arch/sparc/kernel/jump_label.c val = 0x10680000 | (((u32) off >> 2) & 0x7ffff); val 37 arch/sparc/kernel/jump_label.c val = 0x10800000 | (((u32) off >> 2) & 0x3fffff); val 40 arch/sparc/kernel/jump_label.c val = 0x01000000; val 44 arch/sparc/kernel/jump_label.c *insn = val; val 24 arch/sparc/kernel/kernel.h unsigned long val = (unsigned long) p; val 26 arch/sparc/kernel/kernel.h return kern_base + (val - KERNBASE); val 393 arch/sparc/kernel/kprobes.c unsigned long val, void *data) val 401 arch/sparc/kernel/kprobes.c switch (val) { val 20 arch/sparc/kernel/led.c unsigned char val = get_auxio(); val 23 arch/sparc/kernel/led.c if (val & AUXIO_LED) { val 265 arch/sparc/kernel/leon_kernel.c u32 rld, val, ctrl, off; val 268 arch/sparc/kernel/leon_kernel.c val = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val); val 271 arch/sparc/kernel/leon_kernel.c val = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val); val 272 arch/sparc/kernel/leon_kernel.c off = 2 * rld - val; val 274 arch/sparc/kernel/leon_kernel.c off = rld - val; val 398 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val, 0); val 103 arch/sparc/kernel/leon_pci_grpci1.c unsigned int devfn, int where, u32 val); val 118 arch/sparc/kernel/leon_pci_grpci1.c unsigned int devfn, int where, u32 *val) val 142 arch/sparc/kernel/leon_pci_grpci1.c *val = 0xffffffff; val 148 arch/sparc/kernel/leon_pci_grpci1.c *val = swab32(tmp); val 155 arch/sparc/kernel/leon_pci_grpci1.c unsigned int devfn, int where, u32 *val) val 163 arch/sparc/kernel/leon_pci_grpci1.c *val = 0xffff & (v >> (8 * (where & 0x3))); val 168 arch/sparc/kernel/leon_pci_grpci1.c unsigned int devfn, int where, u32 *val) val 174 arch/sparc/kernel/leon_pci_grpci1.c *val = 0xff & (v >> (8 * (where & 3))); val 180 arch/sparc/kernel/leon_pci_grpci1.c unsigned int devfn, int where, u32 val) val 201 arch/sparc/kernel/leon_pci_grpci1.c LEON3_BYPASS_STORE_PA(pci_conf, swab32(val)); val 207 arch/sparc/kernel/leon_pci_grpci1.c unsigned int devfn, int where, u32 val) val 218 arch/sparc/kernel/leon_pci_grpci1.c ((0xffff & val) << (8 * (where & 0x3))); val 223 arch/sparc/kernel/leon_pci_grpci1.c unsigned int devfn, int where, u32 val) val 232 arch/sparc/kernel/leon_pci_grpci1.c ((0xff & val) << (8 * (where & 0x3))); val 240 arch/sparc/kernel/leon_pci_grpci1.c int where, int size, u32 *val) val 247 arch/sparc/kernel/leon_pci_grpci1.c *val = ~0; val 253 arch/sparc/kernel/leon_pci_grpci1.c ret = grpci1_cfg_r8(priv, busno, devfn, where, val); val 256 arch/sparc/kernel/leon_pci_grpci1.c ret = grpci1_cfg_r16(priv, busno, devfn, where, val); val 259 arch/sparc/kernel/leon_pci_grpci1.c ret = grpci1_cfg_r32(priv, busno, devfn, where, val); val 269 arch/sparc/kernel/leon_pci_grpci1.c busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *val, size); val 279 arch/sparc/kernel/leon_pci_grpci1.c int where, int size, u32 val) val 290 arch/sparc/kernel/leon_pci_grpci1.c busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); val 297 arch/sparc/kernel/leon_pci_grpci1.c return grpci1_cfg_w8(priv, busno, devfn, where, val); val 299 arch/sparc/kernel/leon_pci_grpci1.c return grpci1_cfg_w16(priv, busno, devfn, where, val); val 301 arch/sparc/kernel/leon_pci_grpci1.c return grpci1_cfg_w32(priv, busno, devfn, where, val); val 235 arch/sparc/kernel/leon_pci_grpci2.c unsigned int devfn, int where, u32 *val) val 271 arch/sparc/kernel/leon_pci_grpci2.c *val = 0xffffffff; val 274 arch/sparc/kernel/leon_pci_grpci2.c *val = swab32(tmp); val 281 arch/sparc/kernel/leon_pci_grpci2.c unsigned int devfn, int where, u32 *val) val 289 arch/sparc/kernel/leon_pci_grpci2.c *val = 0xffff & (v >> (8 * (where & 0x3))); val 294 arch/sparc/kernel/leon_pci_grpci2.c unsigned int devfn, int where, u32 *val) val 300 arch/sparc/kernel/leon_pci_grpci2.c *val = 0xff & (v >> (8 * (where & 3))); val 306 arch/sparc/kernel/leon_pci_grpci2.c unsigned int devfn, int where, u32 val) val 332 arch/sparc/kernel/leon_pci_grpci2.c LEON3_BYPASS_STORE_PA(pci_conf, swab32(val)); val 344 arch/sparc/kernel/leon_pci_grpci2.c unsigned int devfn, int where, u32 val) val 355 arch/sparc/kernel/leon_pci_grpci2.c ((0xffff & val) << (8 * (where & 0x3))); val 360 arch/sparc/kernel/leon_pci_grpci2.c unsigned int devfn, int where, u32 val) val 369 arch/sparc/kernel/leon_pci_grpci2.c ((0xff & val) << (8 * (where & 0x3))); val 377 arch/sparc/kernel/leon_pci_grpci2.c int where, int size, u32 *val) val 384 arch/sparc/kernel/leon_pci_grpci2.c *val = ~0; val 390 arch/sparc/kernel/leon_pci_grpci2.c ret = grpci2_cfg_r8(priv, busno, devfn, where, val); val 393 arch/sparc/kernel/leon_pci_grpci2.c ret = grpci2_cfg_r16(priv, busno, devfn, where, val); val 396 arch/sparc/kernel/leon_pci_grpci2.c ret = grpci2_cfg_r32(priv, busno, devfn, where, val); val 406 arch/sparc/kernel/leon_pci_grpci2.c *val, size); val 416 arch/sparc/kernel/leon_pci_grpci2.c int where, int size, u32 val) val 427 arch/sparc/kernel/leon_pci_grpci2.c where, size, val); val 434 arch/sparc/kernel/leon_pci_grpci2.c return grpci2_cfg_w8(priv, busno, devfn, where, val); val 436 arch/sparc/kernel/leon_pci_grpci2.c return grpci2_cfg_w16(priv, busno, devfn, where, val); val 438 arch/sparc/kernel/leon_pci_grpci2.c return grpci2_cfg_w32(priv, busno, devfn, where, val); val 65 arch/sparc/kernel/leon_smp.c unsigned long val) val 67 arch/sparc/kernel/leon_smp.c __asm__ __volatile__("swapa [%2] %3, %0\n\t" : "=&r"(val) val 68 arch/sparc/kernel/leon_smp.c : "0"(val), "r"(ptr), "i"(ASI_LEON_DCACHE_MISS) val 70 arch/sparc/kernel/leon_smp.c return val; val 62 arch/sparc/kernel/mdesc.c u64 val; val 641 arch/sparc/kernel/mdesc.c ret = ep[from_node].d.val; val 649 arch/sparc/kernel/mdesc.c ret = ep[ret].d.val; val 671 arch/sparc/kernel/mdesc.c void *val = NULL; val 676 arch/sparc/kernel/mdesc.c val = &ep->d.val; val 682 arch/sparc/kernel/mdesc.c val = data + ep->d.data.data_offset; val 689 arch/sparc/kernel/mdesc.c if (!val) val 695 arch/sparc/kernel/mdesc.c return val; val 735 arch/sparc/kernel/mdesc.c return ep->d.val; val 863 arch/sparc/kernel/mdesc.c u64 val, int depth) val 876 arch/sparc/kernel/mdesc.c (*func)(hp, n, val); val 878 arch/sparc/kernel/mdesc.c find_back_node_value(hp, n, srch_val, func, val, depth-1); val 1060 arch/sparc/kernel/mdesc.c u64 val; val 1064 arch/sparc/kernel/mdesc.c val = *p; val 1066 arch/sparc/kernel/mdesc.c if (!val || val >= 64) val 1069 arch/sparc/kernel/mdesc.c if (val > max) val 1070 arch/sparc/kernel/mdesc.c val = max; val 1072 arch/sparc/kernel/mdesc.c *mask = ((1U << val) * 64U) - 1U; val 1083 arch/sparc/kernel/mdesc.c const u64 *val; val 1085 arch/sparc/kernel/mdesc.c val = mdesc_get_property(hp, mp, "q-cpu-mondo-#bits", NULL); val 1086 arch/sparc/kernel/mdesc.c get_one_mondo_bits(val, &tb->cpu_mondo_qmask, 7, ilog2(max_cpus * 2)); val 1088 arch/sparc/kernel/mdesc.c val = mdesc_get_property(hp, mp, "q-dev-mondo-#bits", NULL); val 1089 arch/sparc/kernel/mdesc.c get_one_mondo_bits(val, &tb->dev_mondo_qmask, 7, 8); val 1091 arch/sparc/kernel/mdesc.c val = mdesc_get_property(hp, mp, "q-resumable-#bits", NULL); val 1092 arch/sparc/kernel/mdesc.c get_one_mondo_bits(val, &tb->resum_qmask, 6, 7); val 1094 arch/sparc/kernel/mdesc.c val = mdesc_get_property(hp, mp, "q-nonresumable-#bits", NULL); val 1095 arch/sparc/kernel/mdesc.c get_one_mondo_bits(val, &tb->nonresum_qmask, 2, 2); val 1159 arch/sparc/kernel/mdesc.c u64 val; val 1161 arch/sparc/kernel/mdesc.c val = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | val 1164 arch/sparc/kernel/mdesc.c val = *pgsz_prop; val 1167 arch/sparc/kernel/mdesc.c *pgsz_mask = val; val 1169 arch/sparc/kernel/mdesc.c *pgsz_mask &= val; val 425 arch/sparc/kernel/of_device_32.c int val = 0; val 427 arch/sparc/kernel/of_device_32.c get_option(&str, &val); val 428 arch/sparc/kernel/of_device_32.c if (val & 1) val 718 arch/sparc/kernel/of_device_64.c int val = 0; val 720 arch/sparc/kernel/of_device_64.c get_option(&str, &val); val 721 arch/sparc/kernel/of_device_64.c if (val & 1) val 723 arch/sparc/kernel/of_device_64.c if (val & 2) val 112 arch/sparc/kernel/pci.c void pci_config_write8(u8 *addr, u8 val) val 124 arch/sparc/kernel/pci.c : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) val 131 arch/sparc/kernel/pci.c void pci_config_write16(u16 *addr, u16 val) val 143 arch/sparc/kernel/pci.c : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) val 150 arch/sparc/kernel/pci.c void pci_config_write32(u32 *addr, u32 val) val 162 arch/sparc/kernel/pci.c : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) val 173 arch/sparc/kernel/pci.c int val = 0; val 175 arch/sparc/kernel/pci.c get_option(&str, &val); val 176 arch/sparc/kernel/pci.c if (val) val 966 arch/sparc/kernel/pci.c u8 val; val 980 arch/sparc/kernel/pci.c pci_read_config_byte(ali_isa_bridge, 0x7e, &val); val 982 arch/sparc/kernel/pci.c val |= 0x01; val 984 arch/sparc/kernel/pci.c val &= ~0x01; val 985 arch/sparc/kernel/pci.c pci_write_config_byte(ali_isa_bridge, 0x7e, val); val 320 arch/sparc/kernel/pci_common.c const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL); val 322 arch/sparc/kernel/pci_common.c pbm->pci_first_busno = val[0]; val 323 arch/sparc/kernel/pci_common.c pbm->pci_last_busno = val[1]; val 325 arch/sparc/kernel/pci_common.c val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL); val 326 arch/sparc/kernel/pci_common.c if (val) { val 327 arch/sparc/kernel/pci_common.c pbm->ino_bitmap = (((u64)val[1] << 32UL) | val 328 arch/sparc/kernel/pci_common.c ((u64)val[0] << 0UL)); val 202 arch/sparc/kernel/pci_fire.c u64 val; val 204 arch/sparc/kernel/pci_fire.c val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); val 205 arch/sparc/kernel/pci_fire.c val &= ~(MSI_MAP_EQNUM); val 206 arch/sparc/kernel/pci_fire.c val |= msiqid; val 207 arch/sparc/kernel/pci_fire.c upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); val 211 arch/sparc/kernel/pci_fire.c val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); val 212 arch/sparc/kernel/pci_fire.c val |= MSI_MAP_VALID; val 213 arch/sparc/kernel/pci_fire.c upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); val 220 arch/sparc/kernel/pci_fire.c u64 val; val 222 arch/sparc/kernel/pci_fire.c val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); val 224 arch/sparc/kernel/pci_fire.c val &= ~MSI_MAP_VALID; val 226 arch/sparc/kernel/pci_fire.c upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); val 283 arch/sparc/kernel/pci_fire.c u64 val; val 291 arch/sparc/kernel/pci_fire.c val = upa_readq(imap_reg); val 292 arch/sparc/kernel/pci_fire.c val |= (1UL << 63) | int_ctrlr; val 293 arch/sparc/kernel/pci_fire.c upa_writeq(val, imap_reg); val 368 arch/sparc/kernel/pci_fire.c u64 val; val 385 arch/sparc/kernel/pci_fire.c val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL); val 386 arch/sparc/kernel/pci_fire.c val |= (FIRE_TLU_CTRL_TIM | val 389 arch/sparc/kernel/pci_fire.c upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL); val 181 arch/sparc/kernel/pci_impl.h void pci_config_write8(u8 *addr, u8 val); val 182 arch/sparc/kernel/pci_impl.h void pci_config_write16(u16 *addr, u16 val); val 183 arch/sparc/kernel/pci_impl.h void pci_config_write32(u32 *addr, u32 val); val 323 arch/sparc/kernel/pci_msi.c const u32 *val; val 326 arch/sparc/kernel/pci_msi.c val = of_get_property(pbm->op->dev.of_node, "#msi-eqs", &len); val 327 arch/sparc/kernel/pci_msi.c if (!val || len != 4) val 329 arch/sparc/kernel/pci_msi.c pbm->msiq_num = *val; val 349 arch/sparc/kernel/pci_msi.c val = of_get_property(pbm->op->dev.of_node, "msi-eq-size", &len); val 350 arch/sparc/kernel/pci_msi.c if (!val || len != 4) val 353 arch/sparc/kernel/pci_msi.c pbm->msiq_ent_count = *val; val 366 arch/sparc/kernel/pci_msi.c val = of_get_property(pbm->op->dev.of_node, "#msi", &len); val 367 arch/sparc/kernel/pci_msi.c if (!val || len != 4) val 369 arch/sparc/kernel/pci_msi.c pbm->msi_num = *val; val 376 arch/sparc/kernel/pci_msi.c val = of_get_property(pbm->op->dev.of_node, "msi-data-mask", &len); val 377 arch/sparc/kernel/pci_msi.c if (!val || len != 4) val 379 arch/sparc/kernel/pci_msi.c pbm->msi_data_mask = *val; val 381 arch/sparc/kernel/pci_msi.c val = of_get_property(pbm->op->dev.of_node, "msix-data-width", &len); val 382 arch/sparc/kernel/pci_msi.c if (!val || len != 4) val 384 arch/sparc/kernel/pci_msi.c pbm->msix_data_width = *val; val 156 arch/sparc/kernel/pci_schizo.c unsigned long val; val 158 arch/sparc/kernel/pci_schizo.c val = upa_readq(err_base + (i * 8UL)); val 160 arch/sparc/kernel/pci_schizo.c stc_error_buf[i] = val; val 214 arch/sparc/kernel/pcic.c int where, int size, u32 *val) val 222 arch/sparc/kernel/pcic.c *val = 0xff & (v >> (8*(where & 3))); val 227 arch/sparc/kernel/pcic.c *val = 0xffff & (v >> (8*(where & 3))); val 231 arch/sparc/kernel/pcic.c pcic_read_config_dword(bus->number, devfn, where&~3, val); val 253 arch/sparc/kernel/pcic.c int where, int size, u32 val) val 262 arch/sparc/kernel/pcic.c ((0xff&val) << (8*(where&3))); val 268 arch/sparc/kernel/pcic.c ((0xffff&val) << (8*(where&3))); val 272 arch/sparc/kernel/pcic.c return pcic_write_config_dword(bus->number, devfn, where, val); val 57 arch/sparc/kernel/pcr.c u64 val; val 60 arch/sparc/kernel/pcr.c __asm__ __volatile__("rd %%pcr, %0" : "=r" (val)); val 61 arch/sparc/kernel/pcr.c return val; val 64 arch/sparc/kernel/pcr.c static void direct_pcr_write(unsigned long reg_num, u64 val) val 67 arch/sparc/kernel/pcr.c __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (val)); val 72 arch/sparc/kernel/pcr.c u64 val; val 75 arch/sparc/kernel/pcr.c __asm__ __volatile__("rd %%pic, %0" : "=r" (val)); val 76 arch/sparc/kernel/pcr.c return val; val 79 arch/sparc/kernel/pcr.c static void direct_pic_write(unsigned long reg_num, u64 val) val 91 arch/sparc/kernel/pcr.c "rd %%pic, %%g0" : : "r" (val)); val 111 arch/sparc/kernel/pcr.c static void n2_pcr_write(unsigned long reg_num, u64 val) val 116 arch/sparc/kernel/pcr.c if (val & PCR_N2_HTRACE) { val 117 arch/sparc/kernel/pcr.c ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val); val 119 arch/sparc/kernel/pcr.c direct_pcr_write(reg_num, val); val 121 arch/sparc/kernel/pcr.c direct_pcr_write(reg_num, val); val 146 arch/sparc/kernel/pcr.c unsigned long val; val 148 arch/sparc/kernel/pcr.c (void) sun4v_vt_get_perfreg(reg_num, &val); val 150 arch/sparc/kernel/pcr.c return val; val 153 arch/sparc/kernel/pcr.c static void n4_pcr_write(unsigned long reg_num, u64 val) val 155 arch/sparc/kernel/pcr.c (void) sun4v_vt_set_perfreg(reg_num, val); val 160 arch/sparc/kernel/pcr.c unsigned long val; val 163 arch/sparc/kernel/pcr.c : "=r" (val) val 166 arch/sparc/kernel/pcr.c return val; val 169 arch/sparc/kernel/pcr.c static void n4_pic_write(unsigned long reg_num, u64 val) val 173 arch/sparc/kernel/pcr.c : "r" (val), "r" (reg_num * 0x8UL), "i" (ASI_PIC)); val 197 arch/sparc/kernel/pcr.c unsigned long val; val 199 arch/sparc/kernel/pcr.c (void) sun4v_t5_get_perfreg(reg_num, &val); val 201 arch/sparc/kernel/pcr.c return val; val 204 arch/sparc/kernel/pcr.c static void n5_pcr_write(unsigned long reg_num, u64 val) val 206 arch/sparc/kernel/pcr.c (void) sun4v_t5_set_perfreg(reg_num, val); val 223 arch/sparc/kernel/pcr.c unsigned long val; val 225 arch/sparc/kernel/pcr.c (void) sun4v_m7_get_perfreg(reg_num, &val); val 227 arch/sparc/kernel/pcr.c return val; val 230 arch/sparc/kernel/pcr.c static void m7_pcr_write(unsigned long reg_num, u64 val) val 232 arch/sparc/kernel/pcr.c (void) sun4v_m7_set_perfreg(reg_num, val); val 137 arch/sparc/kernel/perf_event.c static u8 perf_event_get_msk(unsigned long val) val 139 arch/sparc/kernel/perf_event.c return val & 0xff; val 142 arch/sparc/kernel/perf_event.c static u64 perf_event_get_enc(unsigned long val) val 144 arch/sparc/kernel/perf_event.c return val >> 16; val 182 arch/sparc/kernel/perf_event.c u64 val; val 184 arch/sparc/kernel/perf_event.c val = pcr_ops->read_pic(0); val 186 arch/sparc/kernel/perf_event.c val >>= 32; val 188 arch/sparc/kernel/perf_event.c return val & 0xffffffff; val 191 arch/sparc/kernel/perf_event.c static void sparc_default_write_pmc(int idx, u64 val) val 200 arch/sparc/kernel/perf_event.c val <<= shift; val 204 arch/sparc/kernel/perf_event.c pic |= val; val 733 arch/sparc/kernel/perf_event.c u64 val = pcr_ops->read_pic(idx); val 735 arch/sparc/kernel/perf_event.c return val & 0xffffffff; val 738 arch/sparc/kernel/perf_event.c static void sparc_vt_write_pmc(int idx, u64 val) val 746 arch/sparc/kernel/perf_event.c pcr_ops->write_pic(idx, val & 0xffffffff); val 829 arch/sparc/kernel/perf_event.c u64 enc, val, mask = mask_for_index(idx); val 837 arch/sparc/kernel/perf_event.c val = cpuc->pcr[pcr_index]; val 838 arch/sparc/kernel/perf_event.c val &= ~mask; val 839 arch/sparc/kernel/perf_event.c val |= event_encoding(enc, idx); val 840 arch/sparc/kernel/perf_event.c cpuc->pcr[pcr_index] = val; val 850 arch/sparc/kernel/perf_event.c u64 val; val 855 arch/sparc/kernel/perf_event.c val = cpuc->pcr[pcr_index]; val 856 arch/sparc/kernel/perf_event.c val &= ~mask; val 857 arch/sparc/kernel/perf_event.c val |= nop; val 858 arch/sparc/kernel/perf_event.c cpuc->pcr[pcr_index] = val; val 1059 arch/sparc/kernel/perf_event.c u64 val = cpuc->pcr[i]; val 1061 arch/sparc/kernel/perf_event.c val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit | val 1063 arch/sparc/kernel/perf_event.c cpuc->pcr[i] = val; val 1656 arch/sparc/kernel/perf_event.c u64 val; val 1663 arch/sparc/kernel/perf_event.c val = sparc_perf_event_update(event, hwc, idx); val 1664 arch/sparc/kernel/perf_event.c if (val & (1ULL << 31)) val 38 arch/sparc/kernel/pmc.c #define pmc_writeb(val, offs) (sbus_writeb(val, regs+offs)) val 50 arch/sparc/kernel/prom_common.c int of_set_property(struct device_node *dp, const char *name, void *val, int len) val 57 arch/sparc/kernel/prom_common.c new_val = kmemdup(val, len, GFP_KERNEL); val 73 arch/sparc/kernel/prom_common.c ret = prom_setprop(dp->phandle, name, val, len); val 337 arch/sparc/kernel/prom_irqtrans.c u64 val; val 343 arch/sparc/kernel/prom_irqtrans.c val = 0; val 345 arch/sparc/kernel/prom_irqtrans.c val = schizo_read(sync_reg); val 346 arch/sparc/kernel/prom_irqtrans.c if (!(val & mask)) val 351 arch/sparc/kernel/prom_irqtrans.c val, mask); val 364 arch/sparc/kernel/prom_irqtrans.c : "=&r" (mask), "=&r" (val) val 365 arch/sparc/kernel/prom_irqtrans.c : "0" (mask), "1" (val), val 62 arch/sparc/kernel/psycho_common.c u64 val; val 64 arch/sparc/kernel/psycho_common.c val = upa_readq(err_base + (i * 8UL)); val 66 arch/sparc/kernel/psycho_common.c stc_error_buf[i] = val; val 239 arch/sparc/kernel/ptrace_32.c unsigned long val; val 241 arch/sparc/kernel/ptrace_32.c val = (1 << 8) | (8 << 16); val 243 arch/sparc/kernel/ptrace_32.c &val, val 788 arch/sparc/kernel/ptrace_64.c compat_ulong_t val; val 790 arch/sparc/kernel/ptrace_64.c val = (enabled << 8) | (8 << 16); val 792 arch/sparc/kernel/ptrace_64.c &val, val 827 arch/sparc/kernel/ptrace_64.c unsigned long val; val 834 arch/sparc/kernel/ptrace_64.c val = task_thread_info(target)->xfsr[0]; val 835 arch/sparc/kernel/ptrace_64.c val &= 0xffffffff00000000UL; val 836 arch/sparc/kernel/ptrace_64.c val |= fsr; val 837 arch/sparc/kernel/ptrace_64.c task_thread_info(target)->xfsr[0] = val; val 67 arch/sparc/kernel/sbus.c u64 val; val 105 arch/sparc/kernel/sbus.c val = upa_readq(cfg_reg); val 106 arch/sparc/kernel/sbus.c if (val & (1UL << 14UL)) { val 111 arch/sparc/kernel/sbus.c val |= (1UL << 14UL); val 114 arch/sparc/kernel/sbus.c val |= (1UL << 1UL); val 116 arch/sparc/kernel/sbus.c val |= (1UL << 2UL); val 118 arch/sparc/kernel/sbus.c val |= (1UL << 3UL); val 120 arch/sparc/kernel/sbus.c val |= (1UL << 4UL); val 121 arch/sparc/kernel/sbus.c upa_writeq(val, cfg_reg); val 33 arch/sparc/kernel/sun4d_smp.c static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val) val 36 arch/sparc/kernel/sun4d_smp.c "=&r" (val), "=&r" (ptr) : val 37 arch/sparc/kernel/sun4d_smp.c "0" (val), "1" (ptr)); val 38 arch/sparc/kernel/sun4d_smp.c return val; val 30 arch/sparc/kernel/sun4m_smp.c swap_ulong(volatile unsigned long *ptr, unsigned long val) val 33 arch/sparc/kernel/sun4m_smp.c "=&r" (val), "=&r" (ptr) : val 34 arch/sparc/kernel/sun4m_smp.c "0" (val), "1" (ptr)); val 35 arch/sparc/kernel/sun4m_smp.c return val; val 271 arch/sparc/kernel/sys_sparc_64.c unsigned long val = get_random_long(); val 273 arch/sparc/kernel/sys_sparc_64.c rnd = (val % (1UL << (23UL-PAGE_SHIFT))); val 275 arch/sparc/kernel/sys_sparc_64.c rnd = (val % (1UL << (30UL-PAGE_SHIFT))); val 113 arch/sparc/kernel/sysfs.c unsigned long ra, orig_ra, *val = data; val 115 arch/sparc/kernel/sysfs.c if (*val) val 126 arch/sparc/kernel/sysfs.c long val = work_on_cpu(s->id, read_mmustat_enable, NULL); val 128 arch/sparc/kernel/sysfs.c return sprintf(buf, "%lx\n", val); val 135 arch/sparc/kernel/sysfs.c unsigned long val; val 139 arch/sparc/kernel/sysfs.c ret = sscanf(buf, "%lu", &val); val 143 arch/sparc/kernel/sysfs.c err = work_on_cpu(s->id, write_mmustat_enable, &val); val 140 arch/sparc/kernel/time_32.c u32 val, offset; val 142 arch/sparc/kernel/time_32.c val = sbus_readl(master_l10_counter); val 143 arch/sparc/kernel/time_32.c offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK; val 146 arch/sparc/kernel/time_32.c if (val & TIMER_LIMIT_BIT) val 248 arch/sparc/kernel/time_32.c static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) val 253 arch/sparc/kernel/time_32.c writeb(val, pdata->ioaddr + ofs); val 338 arch/sparc/kernel/time_64.c static void __hbird_write_stick(unsigned long val) val 340 arch/sparc/kernel/time_64.c unsigned long low = (val & 0xffffffffUL); val 341 arch/sparc/kernel/time_64.c unsigned long high = (val >> 32UL); val 354 arch/sparc/kernel/time_64.c static void __hbird_write_compare(unsigned long val) val 356 arch/sparc/kernel/time_64.c unsigned long low = (val & 0xffffffffUL); val 357 arch/sparc/kernel/time_64.c unsigned long high = (val >> 32UL); val 394 arch/sparc/kernel/time_64.c unsigned long val; val 396 arch/sparc/kernel/time_64.c val = __hbird_read_stick() + adj; val 397 arch/sparc/kernel/time_64.c __hbird_write_stick(val); val 399 arch/sparc/kernel/time_64.c return val; val 404 arch/sparc/kernel/time_64.c unsigned long val = __hbird_read_stick(); val 407 arch/sparc/kernel/time_64.c val &= ~TICKCMP_IRQ_BIT; val 408 arch/sparc/kernel/time_64.c val += adj; val 409 arch/sparc/kernel/time_64.c __hbird_write_compare(val); val 413 arch/sparc/kernel/time_64.c return ((long)(val2 - val)) > 0L; val 535 arch/sparc/kernel/time_64.c static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) val 540 arch/sparc/kernel/time_64.c writeb(val, regs + ofs); val 652 arch/sparc/kernel/time_64.c static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val, val 667 arch/sparc/kernel/time_64.c if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || val 668 arch/sparc/kernel/time_64.c (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { val 867 arch/sparc/kernel/traps_64.c unsigned long val; val 869 arch/sparc/kernel/traps_64.c val = cpu_data(i).ecache_size; val 870 arch/sparc/kernel/traps_64.c if (!val) val 873 arch/sparc/kernel/traps_64.c if (val > largest_size) val 874 arch/sparc/kernel/traps_64.c largest_size = val; val 876 arch/sparc/kernel/traps_64.c val = cpu_data(i).ecache_line_size; val 877 arch/sparc/kernel/traps_64.c if (val < smallest_linesize) val 878 arch/sparc/kernel/traps_64.c smallest_linesize = val; val 263 arch/sparc/kernel/uprobes.c unsigned long val, void *data) val 272 arch/sparc/kernel/uprobes.c switch (val) { val 204 arch/sparc/kernel/visemul.c static void store_reg(struct pt_regs *regs, unsigned long val, unsigned long rd) val 209 arch/sparc/kernel/visemul.c *rd_kern = val; val 214 arch/sparc/kernel/visemul.c __put_user((u32)val, (u32 __user *)rd_user); val 216 arch/sparc/kernel/visemul.c __put_user(val, rd_user); val 491 arch/sparc/kernel/visemul.c unsigned int val; val 496 arch/sparc/kernel/visemul.c val = ((from_fixed < 0) ? val 501 arch/sparc/kernel/visemul.c rd_val |= (val << (8 * byte)); val 514 arch/sparc/kernel/visemul.c unsigned long val; val 519 arch/sparc/kernel/visemul.c val = ((from_fixed < 0) ? val 524 arch/sparc/kernel/visemul.c rd_val |= (val << (32 * word)); val 537 arch/sparc/kernel/visemul.c long val; val 542 arch/sparc/kernel/visemul.c val = ((from_fixed < -32768) ? val 547 arch/sparc/kernel/visemul.c rd_val |= ((val & 0xffff) << (word * 16)); val 560 arch/sparc/kernel/visemul.c unsigned long val; val 563 arch/sparc/kernel/visemul.c val = src << 4; val 565 arch/sparc/kernel/visemul.c rd_val |= (val << (byte * 16)); val 1144 arch/sparc/mm/init_64.c const u64 *val; val 1146 arch/sparc/mm/init_64.c val = mdesc_get_property(md, target, val 1148 arch/sparc/mm/init_64.c if (val && *val == cfg_handle) val 1163 arch/sparc/mm/init_64.c const u64 *val; val 1168 arch/sparc/mm/init_64.c val = mdesc_get_property(md, target, "latency", NULL); val 1169 arch/sparc/mm/init_64.c if (!val) val 1172 arch/sparc/mm/init_64.c if (*val < best_latency) { val 1174 arch/sparc/mm/init_64.c best_latency = *val; val 1277 arch/sparc/mm/init_64.c const u64 *val; val 1281 arch/sparc/mm/init_64.c val = mdesc_get_property(md, node, "latency", NULL); val 1282 arch/sparc/mm/init_64.c m->latency = *val; val 1283 arch/sparc/mm/init_64.c val = mdesc_get_property(md, node, "address-match", NULL); val 1284 arch/sparc/mm/init_64.c m->match = *val; val 1285 arch/sparc/mm/init_64.c val = mdesc_get_property(md, node, "address-mask", NULL); val 1286 arch/sparc/mm/init_64.c m->mask = *val; val 1318 arch/sparc/mm/init_64.c const u64 *val; val 1320 arch/sparc/mm/init_64.c val = mdesc_get_property(md, node, "base", NULL); val 1321 arch/sparc/mm/init_64.c m->base = *val; val 1322 arch/sparc/mm/init_64.c val = mdesc_get_property(md, node, "size", NULL); val 1323 arch/sparc/mm/init_64.c m->size = *val; val 1324 arch/sparc/mm/init_64.c val = mdesc_get_property(md, node, val 1330 arch/sparc/mm/init_64.c if (val) val 1331 arch/sparc/mm/init_64.c m->offset = *val; val 2818 arch/sparc/mm/init_64.c unsigned long val; val 2820 arch/sparc/mm/init_64.c val = (_PAGE_VALID | _PAGE_SZ4MB_4U | val 2824 arch/sparc/mm/init_64.c val = (_PAGE_VALID | _PAGE_SZ4MB_4V | val 2828 arch/sparc/mm/init_64.c return val | paddr; val 840 arch/sparc/mm/srmmu.c unsigned long *val; val 842 arch/sparc/mm/srmmu.c val = &pmdp->pmdv[x]; val 843 arch/sparc/mm/srmmu.c *(unsigned long *)__nocache_fix(val) = probed; val 23 arch/sparc/oprofile/init.c unsigned long val, void *data) val 28 arch/sparc/oprofile/init.c switch (val) { val 111 arch/sparc/vdso/vdso2c.c #define PBE(x, val, bits, ifnot) \ val 114 arch/sparc/vdso/vdso2c.c put_unaligned_be##bits((val), (x)), ifnot) val 116 arch/sparc/vdso/vdso2c.c #define LAST_PBE(x, val) \ val 117 arch/sparc/vdso/vdso2c.c __builtin_choose_expr(sizeof(*(x)) == 1, *(x) = (val), (void)(0)) val 119 arch/sparc/vdso/vdso2c.c #define PUT_BE(x, val) \ val 120 arch/sparc/vdso/vdso2c.c PBE(x, val, 64, PBE(x, val, 32, PBE(x, val, 16, LAST_PBE(x, val)))) val 58 arch/sparc/vdso/vdso2c.h typeof(dyn[i].d_un.d_val) val = GET_BE(&dyn[i].d_un.d_val); val 60 arch/sparc/vdso/vdso2c.h if ((tag == DT_RELSZ || tag == DT_RELASZ) && (val != 0)) val 449 arch/sparc/vdso/vma.c unsigned long val; val 451 arch/sparc/vdso/vma.c err = kstrtoul(s, 10, &val); val 454 arch/sparc/vdso/vma.c vdso_enabled = val; val 352 arch/um/include/asm/pgtable.h #define __swp_type(x) (((x).val >> 5) & 0x1f) val 353 arch/um/include/asm/pgtable.h #define __swp_offset(x) ((x).val >> 11) val 359 arch/um/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 46 arch/um/include/asm/syscall-generic.h int error, long val) val 48 arch/um/include/asm/syscall-generic.h PT_REGS_SET_SYSCALL_RETURN(regs, (long) error ?: val); val 11 arch/um/include/shared/longjmp.h #define UML_LONGJMP(buf, val) do { \ val 12 arch/um/include/shared/longjmp.h longjmp(*buf, val); \ val 23 arch/um/kernel/exitcode.c int val; val 29 arch/um/kernel/exitcode.c val = uml_exitcode; val 30 arch/um/kernel/exitcode.c seq_printf(m, "%d\n", val); val 30 arch/unicore32/include/asm/hwdef-copro.h unsigned int val; val 31 arch/unicore32/include/asm/hwdef-copro.h asm("movc %0, p0.c1, #0" : "=r" (val) : : "cc"); val 32 arch/unicore32/include/asm/hwdef-copro.h return val; val 35 arch/unicore32/include/asm/hwdef-copro.h static inline void set_cr(unsigned int val) val 37 arch/unicore32/include/asm/hwdef-copro.h asm volatile("movc p0.c1, %0, #0" : : "r" (val) : "cc"); val 47 arch/unicore32/include/asm/pgtable.h extern void __pte_error(const char *file, int line, unsigned long val); val 48 arch/unicore32/include/asm/pgtable.h extern void __pgd_error(const char *file, int line, unsigned long val); val 264 arch/unicore32/include/asm/pgtable.h #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) \ val 266 arch/unicore32/include/asm/pgtable.h #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) val 272 arch/unicore32/include/asm/pgtable.h #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) val 18 arch/unicore32/include/mach/bitfield.h #define FIELD(val, vmask, vshift) (((val) & ((UData(1) << (vmask)) - 1)) << (vshift)) val 77 arch/unicore32/kernel/ptrace.c unsigned long val) val 82 arch/unicore32/kernel/ptrace.c return put_user_reg(tsk, off >> 2, val); val 91 arch/unicore32/kernel/traps.c unsigned long val; val 92 arch/unicore32/kernel/traps.c if (__get_user(val, (unsigned long *)p) == 0) val 93 arch/unicore32/kernel/traps.c sprintf(str + i * 9, " %08lx", val); val 121 arch/unicore32/kernel/traps.c unsigned int val, bad; val 123 arch/unicore32/kernel/traps.c bad = __get_user(val, &((u32 *)addr)[i]); val 127 arch/unicore32/kernel/traps.c width, val); val 270 arch/unicore32/kernel/traps.c void __pte_error(const char *file, int line, unsigned long val) val 272 arch/unicore32/kernel/traps.c printk(KERN_DEFAULT "%s:%d: bad pte %08lx.\n", file, line, val); val 275 arch/unicore32/kernel/traps.c void __pmd_error(const char *file, int line, unsigned long val) val 277 arch/unicore32/kernel/traps.c printk(KERN_DEFAULT "%s:%d: bad pmd %08lx.\n", file, line, val); val 280 arch/unicore32/kernel/traps.c void __pgd_error(const char *file, int line, unsigned long val) val 282 arch/unicore32/kernel/traps.c printk(KERN_DEFAULT "%s:%d: bad pgd %08lx.\n", file, line, val); val 67 arch/unicore32/mm/alignment.c #define get8_unaligned_check(val, addr, err) \ val 80 arch/unicore32/mm/alignment.c : "=r" (err), "=&r" (val), "=r" (addr) \ val 83 arch/unicore32/mm/alignment.c #define get8t_unaligned_check(val, addr, err) \ val 96 arch/unicore32/mm/alignment.c : "=r" (err), "=&r" (val), "=r" (addr) \ val 99 arch/unicore32/mm/alignment.c #define get16_unaligned_check(val, addr) \ val 102 arch/unicore32/mm/alignment.c get8_unaligned_check(val, a, err); \ val 104 arch/unicore32/mm/alignment.c val |= v << 8; \ val 109 arch/unicore32/mm/alignment.c #define put16_unaligned_check(val, addr) \ val 111 arch/unicore32/mm/alignment.c unsigned int err = 0, v = val, a = addr; \ val 133 arch/unicore32/mm/alignment.c #define __put32_unaligned_check(ins, val, addr) \ val 135 arch/unicore32/mm/alignment.c unsigned int err = 0, v = val, a = addr; \ val 163 arch/unicore32/mm/alignment.c #define get32_unaligned_check(val, addr) \ val 166 arch/unicore32/mm/alignment.c get8_unaligned_check(val, a, err); \ val 168 arch/unicore32/mm/alignment.c val |= v << 8; \ val 170 arch/unicore32/mm/alignment.c val |= v << 16; \ val 172 arch/unicore32/mm/alignment.c val |= v << 24; \ val 177 arch/unicore32/mm/alignment.c #define put32_unaligned_check(val, addr) \ val 178 arch/unicore32/mm/alignment.c __put32_unaligned_check("stb.u", val, addr) val 180 arch/unicore32/mm/alignment.c #define get32t_unaligned_check(val, addr) \ val 183 arch/unicore32/mm/alignment.c get8t_unaligned_check(val, a, err); \ val 185 arch/unicore32/mm/alignment.c val |= v << 8; \ val 187 arch/unicore32/mm/alignment.c val |= v << 16; \ val 189 arch/unicore32/mm/alignment.c val |= v << 24; \ val 194 arch/unicore32/mm/alignment.c #define put32t_unaligned_check(val, addr) \ val 195 arch/unicore32/mm/alignment.c __put32_unaligned_check("stb.u", val, addr) val 222 arch/unicore32/mm/alignment.c unsigned long val; val 223 arch/unicore32/mm/alignment.c get16_unaligned_check(val, addr); val 227 arch/unicore32/mm/alignment.c val = (signed long)((signed short)val); val 229 arch/unicore32/mm/alignment.c regs->uregs[rd] = val; val 465 arch/unicore32/mm/alignment.c unsigned long val = 0; val 467 arch/unicore32/mm/alignment.c get32t_unaligned_check(val, addr); val 471 arch/unicore32/mm/alignment.c : : "r"(val)); \ val 487 arch/unicore32/mm/alignment.c : : "r"(val)); \ val 499 arch/unicore32/mm/alignment.c put32t_unaligned_check(val, addr); val 288 arch/x86/boot/compressed/acpi.c char val[MAX_ADDR_LEN] = { }; val 291 arch/x86/boot/compressed/acpi.c ret = cmdline_find_option("acpi_rsdp", val, MAX_ADDR_LEN); val 295 arch/x86/boot/compressed/acpi.c if (kstrtoull(val, 16, &addr)) val 216 arch/x86/boot/compressed/kaslr.c static void parse_gb_huge_pages(char *param, char *val) val 222 arch/x86/boot/compressed/kaslr.c p = val; val 235 arch/x86/boot/compressed/kaslr.c p = val; val 247 arch/x86/boot/compressed/kaslr.c char *param, *val; val 266 arch/x86/boot/compressed/kaslr.c args = next_arg(args, ¶m, &val); val 268 arch/x86/boot/compressed/kaslr.c if (!val && strcmp(param, "--") == 0) { val 274 arch/x86/boot/compressed/kaslr.c mem_avoid_memmap(val); val 276 arch/x86/boot/compressed/kaslr.c parse_gb_huge_pages(param, val); val 278 arch/x86/boot/compressed/kaslr.c char *p = val; val 269 arch/x86/boot/string.c unsigned int val; val 272 arch/x86/boot/string.c val = c - '0'; val 274 arch/x86/boot/string.c val = lc - 'a' + 10; val 278 arch/x86/boot/string.c if (val >= base) val 285 arch/x86/boot/string.c if (res > __div_u64(ULLONG_MAX - val, base)) val 288 arch/x86/boot/string.c res = res * base + val; val 131 arch/x86/entry/vdso/vdso2c.c #define PLE(x, val, bits, ifnot) \ val 134 arch/x86/entry/vdso/vdso2c.c put_unaligned_le##bits((val), (x)), ifnot) val 137 arch/x86/entry/vdso/vdso2c.c #define LAST_PLE(x, val) \ val 138 arch/x86/entry/vdso/vdso2c.c __builtin_choose_expr(sizeof(*(x)) == 1, *(x) = (val), bad_put_le()) val 140 arch/x86/entry/vdso/vdso2c.c #define PUT_LE(x, val) \ val 141 arch/x86/entry/vdso/vdso2c.c PLE(x, val, 64, PLE(x, val, 32, PLE(x, val, 16, LAST_PLE(x, val)))) val 800 arch/x86/events/amd/ibs.c u64 val; val 805 arch/x86/events/amd/ibs.c rdmsrl(MSR_AMD64_IBSCTL, val); val 806 arch/x86/events/amd/ibs.c offset = val & IBSCTL_LVT_OFFSET_MASK; val 808 arch/x86/events/amd/ibs.c if (!(val & IBSCTL_LVT_OFFSET_VALID)) { val 810 arch/x86/events/amd/ibs.c smp_processor_id(), offset, MSR_AMD64_IBSCTL, val); val 816 arch/x86/events/amd/ibs.c smp_processor_id(), offset, MSR_AMD64_IBSCTL, val); val 918 arch/x86/events/amd/ibs.c u64 val; val 920 arch/x86/events/amd/ibs.c rdmsrl(MSR_AMD64_IBSCTL, val); val 921 arch/x86/events/amd/ibs.c if (!(val & IBSCTL_LVT_OFFSET_VALID)) val 924 arch/x86/events/amd/ibs.c return val & IBSCTL_LVT_OFFSET_MASK; val 195 arch/x86/events/core.c u64 val, val_fail = -1, val_new= ~0; val 206 arch/x86/events/core.c ret = rdmsrl_safe(reg, &val); val 209 arch/x86/events/core.c if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { val 211 arch/x86/events/core.c val_fail = val; val 220 arch/x86/events/core.c ret = rdmsrl_safe(reg, &val); val 224 arch/x86/events/core.c if (val & (0x03 << i*4)) { val 226 arch/x86/events/core.c val_fail = val; val 249 arch/x86/events/core.c if (rdmsrl_safe(reg, &val)) val 251 arch/x86/events/core.c val ^= 0xffffUL; val 252 arch/x86/events/core.c ret = wrmsrl_safe(reg, val); val 254 arch/x86/events/core.c if (ret || val != val_new) val 304 arch/x86/events/core.c u64 config, val; val 323 arch/x86/events/core.c val = hw_cache_event_ids[cache_type][cache_op][cache_result]; val 325 arch/x86/events/core.c if (val == 0) val 328 arch/x86/events/core.c if (val == -1) val 331 arch/x86/events/core.c hwc->config |= val; val 333 arch/x86/events/core.c return x86_pmu_extra_regs(val, event); val 620 arch/x86/events/core.c u64 val; val 624 arch/x86/events/core.c rdmsrl(x86_pmu_config_addr(idx), val); val 625 arch/x86/events/core.c if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) val 627 arch/x86/events/core.c val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; val 628 arch/x86/events/core.c wrmsrl(x86_pmu_config_addr(idx), val); val 1497 arch/x86/events/core.c u64 val; val 1517 arch/x86/events/core.c val = x86_perf_event_update(event); val 1518 arch/x86/events/core.c if (val & (1ULL << (x86_pmu.cntval_bits - 1))) val 2182 arch/x86/events/core.c unsigned long val; val 2185 arch/x86/events/core.c ret = kstrtoul(buf, 0, &val); val 2189 arch/x86/events/core.c if (val > 2) val 2195 arch/x86/events/core.c if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { val 2201 arch/x86/events/core.c if (val == 2) val 2208 arch/x86/events/core.c x86_pmu.attr_rdpmc = val; val 2075 arch/x86/events/intel/core.c u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; val 2077 arch/x86/events/intel/core.c if (cpuc->tfa_shadow != val) { val 2078 arch/x86/events/intel/core.c cpuc->tfa_shadow = val; val 2079 arch/x86/events/intel/core.c wrmsrl(MSR_TSX_FORCE_ABORT, val); val 4314 arch/x86/events/intel/core.c unsigned long val; val 4317 arch/x86/events/intel/core.c ret = kstrtoul(buf, 0, &val); val 4321 arch/x86/events/intel/core.c if (val > 1) val 4326 arch/x86/events/intel/core.c if (x86_pmu.attr_freeze_on_smi == val) val 4329 arch/x86/events/intel/core.c x86_pmu.attr_freeze_on_smi = val; val 4332 arch/x86/events/intel/core.c on_each_cpu(flip_smm_bit, &val, 1); val 4363 arch/x86/events/intel/core.c bool val; val 4366 arch/x86/events/intel/core.c ret = kstrtobool(buf, &val); val 4371 arch/x86/events/intel/core.c if (val == allow_tsx_force_abort) val 4374 arch/x86/events/intel/core.c allow_tsx_force_abort = val; val 352 arch/x86/events/intel/cstate.c u64 val; val 354 arch/x86/events/intel/cstate.c rdmsrl(event->hw.event_base, val); val 355 arch/x86/events/intel/cstate.c return val; val 33 arch/x86/events/intel/ds.c u64 val; val 102 arch/x86/events/intel/ds.c u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); val 104 arch/x86/events/intel/ds.c dse.val = status; val 114 arch/x86/events/intel/ds.c val |= P(TLB, MISS); val 116 arch/x86/events/intel/ds.c val |= P(TLB, HIT); val 124 arch/x86/events/intel/ds.c val |= P(LVL, HIT); val 126 arch/x86/events/intel/ds.c val |= P(LVL, MISS); val 132 arch/x86/events/intel/ds.c val |= P(LOCK, LOCKED); val 134 arch/x86/events/intel/ds.c return val; val 141 arch/x86/events/intel/ds.c dse.val = PERF_MEM_NA; val 162 arch/x86/events/intel/ds.c return dse.val; val 168 arch/x86/events/intel/ds.c u64 val; val 170 arch/x86/events/intel/ds.c dse.val = status; val 175 arch/x86/events/intel/ds.c val = pebs_data_source[dse.ld_dse]; val 181 arch/x86/events/intel/ds.c val |= P(TLB, NA) | P(LOCK, NA); val 182 arch/x86/events/intel/ds.c return val; val 190 arch/x86/events/intel/ds.c val |= P(TLB, MISS) | P(TLB, L2); val 192 arch/x86/events/intel/ds.c val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); val 198 arch/x86/events/intel/ds.c val |= P(LOCK, LOCKED); val 200 arch/x86/events/intel/ds.c return val; val 1326 arch/x86/events/intel/ds.c u64 val = PERF_MEM_NA; val 1331 arch/x86/events/intel/ds.c val = load_latency_data(aux); val 1333 arch/x86/events/intel/ds.c val = precise_datala_hsw(event, aux); val 1335 arch/x86/events/intel/ds.c val = precise_store_data(aux); val 1336 arch/x86/events/intel/ds.c return val; val 1373 arch/x86/events/intel/ds.c data->data_src.val = get_data_src(event, pebs->dse); val 1579 arch/x86/events/intel/ds.c data->data_src.val = get_data_src(event, meminfo->aux); val 160 arch/x86/events/intel/knc.c u64 val; val 162 arch/x86/events/intel/knc.c rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); val 163 arch/x86/events/intel/knc.c val &= ~(KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1); val 164 arch/x86/events/intel/knc.c wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); val 169 arch/x86/events/intel/knc.c u64 val; val 171 arch/x86/events/intel/knc.c rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); val 172 arch/x86/events/intel/knc.c val |= (KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1); val 173 arch/x86/events/intel/knc.c wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); val 180 arch/x86/events/intel/knc.c u64 val; val 182 arch/x86/events/intel/knc.c val = hwc->config; val 183 arch/x86/events/intel/knc.c val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; val 185 arch/x86/events/intel/knc.c (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); val 191 arch/x86/events/intel/knc.c u64 val; val 193 arch/x86/events/intel/knc.c val = hwc->config; val 194 arch/x86/events/intel/knc.c val |= ARCH_PERFMON_EVENTSEL_ENABLE; val 196 arch/x86/events/intel/knc.c (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); val 279 arch/x86/events/intel/lbr.c inline u64 lbr_from_signext_quirk_wr(u64 val) val 291 arch/x86/events/intel/lbr.c val |= (LBR_FROM_SIGNEXT_2MSB & val) << 2; val 293 arch/x86/events/intel/lbr.c return val; val 299 arch/x86/events/intel/lbr.c static u64 lbr_from_signext_quirk_rd(u64 val) val 306 arch/x86/events/intel/lbr.c val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT); val 308 arch/x86/events/intel/lbr.c return val; val 311 arch/x86/events/intel/lbr.c static inline void wrlbr_from(unsigned int idx, u64 val) val 313 arch/x86/events/intel/lbr.c val = lbr_from_signext_quirk_wr(val); val 314 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_from + idx, val); val 317 arch/x86/events/intel/lbr.c static inline void wrlbr_to(unsigned int idx, u64 val) val 319 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_to + idx, val); val 324 arch/x86/events/intel/lbr.c u64 val; val 326 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_from + idx, val); val 328 arch/x86/events/intel/lbr.c return lbr_from_signext_quirk_rd(val); val 333 arch/x86/events/intel/lbr.c u64 val; val 335 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_to + idx, val); val 337 arch/x86/events/intel/lbr.c return val; val 1005 arch/x86/events/intel/p4.c u64 val; val 1027 arch/x86/events/intel/p4.c val = x86_perf_event_update(event); val 1028 arch/x86/events/intel/p4.c if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1)))) val 140 arch/x86/events/intel/p6.c u64 val; val 143 arch/x86/events/intel/p6.c rdmsrl(MSR_P6_EVNTSEL0, val); val 144 arch/x86/events/intel/p6.c val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; val 145 arch/x86/events/intel/p6.c wrmsrl(MSR_P6_EVNTSEL0, val); val 150 arch/x86/events/intel/p6.c unsigned long val; val 153 arch/x86/events/intel/p6.c rdmsrl(MSR_P6_EVNTSEL0, val); val 154 arch/x86/events/intel/p6.c val |= ARCH_PERFMON_EVENTSEL_ENABLE; val 155 arch/x86/events/intel/p6.c wrmsrl(MSR_P6_EVNTSEL0, val); val 162 arch/x86/events/intel/p6.c u64 val = P6_NOP_EVENT; val 164 arch/x86/events/intel/p6.c (void)wrmsrl_safe(hwc->config_base, val); val 170 arch/x86/events/intel/p6.c u64 val; val 172 arch/x86/events/intel/p6.c val = hwc->config; val 181 arch/x86/events/intel/p6.c (void)wrmsrl_safe(hwc->config_base, val); val 3765 arch/x86/events/intel/uncore_snbep.c u32 val = 0; val 3771 arch/x86/events/intel/uncore_snbep.c pci_read_config_dword(dev, SKX_CAPID6, &val); val 3772 arch/x86/events/intel/uncore_snbep.c val &= SKX_CHA_BIT_MASK; val 3775 arch/x86/events/intel/uncore_snbep.c return hweight32(val); val 1023 arch/x86/events/perf_event.h u64 lbr_from_signext_quirk_wr(u64 val); val 18 arch/x86/events/probe.c u64 val; val 32 arch/x86/events/probe.c if (rdmsrl_safe(msr[bit].msr, &val)) val 35 arch/x86/events/probe.c if (!zero && !val) val 73 arch/x86/hyperv/hv_apic.c static void hv_apic_write(u32 reg, u32 val) val 77 arch/x86/hyperv/hv_apic.c wrmsr(HV_X64_MSR_EOI, val, 0); val 80 arch/x86/hyperv/hv_apic.c wrmsr(HV_X64_MSR_TPR, val, 0); val 83 arch/x86/hyperv/hv_apic.c native_apic_mem_write(reg, val); val 87 arch/x86/hyperv/hv_apic.c static void hv_apic_eoi_write(u32 reg, u32 val) val 94 arch/x86/hyperv/hv_apic.c wrmsr(HV_X64_MSR_EOI, val, 0); val 91 arch/x86/hyperv/hv_init.c u64 val; val 93 arch/x86/hyperv/hv_init.c val = vmalloc_to_pfn(*hvp); val 94 arch/x86/hyperv/hv_init.c val = (val << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) | val 97 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, val); val 26 arch/x86/hyperv/hv_spinlock.c static void hv_qlock_wait(u8 *byte, u8 val) val 51 arch/x86/hyperv/hv_spinlock.c if (READ_ONCE(*byte) == val) val 263 arch/x86/ia32/ia32_signal.c u32 val; val 341 arch/x86/ia32/ia32_signal.c u32 val; val 254 arch/x86/include/asm/apic.h unsigned long val; val 256 arch/x86/include/asm/apic.h rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); val 257 arch/x86/include/asm/apic.h return val; val 401 arch/x86/include/asm/apic.h static inline void apic_write(u32 reg, u32 val) val 403 arch/x86/include/asm/apic.h apic->write(reg, val); val 436 arch/x86/include/asm/apic.h static inline void apic_write(u32 reg, u32 val) { } val 218 arch/x86/include/asm/atomic.h int val = arch_atomic_read(v); val 220 arch/x86/include/asm/atomic.h do { } while (!arch_atomic_try_cmpxchg(v, &val, val & i)); val 222 arch/x86/include/asm/atomic.h return val; val 235 arch/x86/include/asm/atomic.h int val = arch_atomic_read(v); val 237 arch/x86/include/asm/atomic.h do { } while (!arch_atomic_try_cmpxchg(v, &val, val | i)); val 239 arch/x86/include/asm/atomic.h return val; val 252 arch/x86/include/asm/atomic.h int val = arch_atomic_read(v); val 254 arch/x86/include/asm/atomic.h do { } while (!arch_atomic_try_cmpxchg(v, &val, val ^ i)); val 256 arch/x86/include/asm/atomic.h return val; val 15 arch/x86/include/asm/atomic64_32.h #define ATOMIC64_INIT(val) { (val) } val 204 arch/x86/include/asm/atomic64_64.h s64 val = arch_atomic64_read(v); val 207 arch/x86/include/asm/atomic64_64.h } while (!arch_atomic64_try_cmpxchg(v, &val, val & i)); val 208 arch/x86/include/asm/atomic64_64.h return val; val 221 arch/x86/include/asm/atomic64_64.h s64 val = arch_atomic64_read(v); val 224 arch/x86/include/asm/atomic64_64.h } while (!arch_atomic64_try_cmpxchg(v, &val, val | i)); val 225 arch/x86/include/asm/atomic64_64.h return val; val 238 arch/x86/include/asm/atomic64_64.h s64 val = arch_atomic64_read(v); val 241 arch/x86/include/asm/atomic64_64.h } while (!arch_atomic64_try_cmpxchg(v, &val, val ^ i)); val 242 arch/x86/include/asm/atomic64_64.h return val; val 26 arch/x86/include/asm/bug.h # define __BUG_REL(val) ".long " __stringify(val) val 28 arch/x86/include/asm/bug.h # define __BUG_REL(val) ".long " __stringify(val) " - 2b" val 5 arch/x86/include/asm/cmpxchg_64.h static inline void set_64bit(volatile u64 *ptr, u64 val) val 7 arch/x86/include/asm/cmpxchg_64.h *ptr = val; val 23 arch/x86/include/asm/debugreg.h unsigned long val = 0; /* Damn you, gcc! */ val 27 arch/x86/include/asm/debugreg.h asm("mov %%db0, %0" :"=r" (val)); val 30 arch/x86/include/asm/debugreg.h asm("mov %%db1, %0" :"=r" (val)); val 33 arch/x86/include/asm/debugreg.h asm("mov %%db2, %0" :"=r" (val)); val 36 arch/x86/include/asm/debugreg.h asm("mov %%db3, %0" :"=r" (val)); val 39 arch/x86/include/asm/debugreg.h asm("mov %%db6, %0" :"=r" (val)); val 42 arch/x86/include/asm/debugreg.h asm("mov %%db7, %0" :"=r" (val)); val 47 arch/x86/include/asm/debugreg.h return val; val 259 arch/x86/include/asm/floppy.h unsigned char val; \ val 261 arch/x86/include/asm/floppy.h val = (CMOS_READ(0x10) >> 4) & 15; \ val 263 arch/x86/include/asm/floppy.h val; \ val 269 arch/x86/include/asm/floppy.h unsigned char val; \ val 271 arch/x86/include/asm/floppy.h val = CMOS_READ(0x10) & 15; \ val 273 arch/x86/include/asm/floppy.h val; \ val 61 arch/x86/include/asm/hw_breakpoint.h unsigned long val, void *data); val 6 arch/x86/include/asm/intel_mid_vrtc.h extern void vrtc_cmos_write(unsigned char val, unsigned char reg); val 43 arch/x86/include/asm/intel_pmc_ipc.h int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val); val 84 arch/x86/include/asm/intel_pmc_ipc.h static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) val 53 arch/x86/include/asm/io.h static inline void name(type val, volatile void __iomem *addr) \ val 54 arch/x86/include/asm/io.h { asm volatile("mov" size " %0,%1": :reg (val), \ val 243 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_call_pmic_bus_access_notifier_chain(unsigned long val, void *v) val 106 arch/x86/include/asm/kprobes.h unsigned long val, void *data); val 103 arch/x86/include/asm/kvm_emulate.h void (*write_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val); val 113 arch/x86/include/asm/kvm_emulate.h unsigned long addr, void *val, val 125 arch/x86/include/asm/kvm_emulate.h void *val, unsigned int bytes); val 136 arch/x86/include/asm/kvm_emulate.h unsigned long addr, void *val, unsigned int bytes, val 146 arch/x86/include/asm/kvm_emulate.h unsigned long addr, void *val, unsigned int bytes, val 156 arch/x86/include/asm/kvm_emulate.h unsigned long addr, void *val, unsigned int bytes, val 167 arch/x86/include/asm/kvm_emulate.h unsigned long addr, const void *val, val 188 arch/x86/include/asm/kvm_emulate.h int size, unsigned short port, void *val, val 192 arch/x86/include/asm/kvm_emulate.h int size, unsigned short port, const void *val, val 206 arch/x86/include/asm/kvm_emulate.h int (*set_cr)(struct x86_emulate_ctxt *ctxt, int cr, ulong val); val 256 arch/x86/include/asm/kvm_emulate.h unsigned long val; val 309 arch/x86/include/asm/kvm_host.h unsigned long val; val 1288 arch/x86/include/asm/kvm_host.h const void *val, int bytes); val 1386 arch/x86/include/asm/kvm_host.h int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); val 1387 arch/x86/include/asm/kvm_host.h int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); val 1572 arch/x86/include/asm/kvm_host.h int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); val 1640 arch/x86/include/asm/kvm_host.h #define put_smstate(type, buf, offset, val) \ val 1641 arch/x86/include/asm/kvm_host.h *(type *)((buf) + (offset) - 0x7e00) = val val 94 arch/x86/include/asm/mc146818rtc.h #define CMOS_WRITE(val, addr) rtc_cmos_write(val, addr) val 96 arch/x86/include/asm/mc146818rtc.h void rtc_cmos_write(unsigned char val, unsigned char addr); val 5 arch/x86/include/asm/misc.h int num_digits(int val); val 17 arch/x86/include/asm/mshyperv.h #define hv_init_timer_config(timer, val) \ val 18 arch/x86/include/asm/mshyperv.h wrmsrl(HV_X64_MSR_STIMER0_CONFIG + (2*timer), val) val 20 arch/x86/include/asm/mshyperv.h #define hv_get_simp(val) rdmsrl(HV_X64_MSR_SIMP, val) val 21 arch/x86/include/asm/mshyperv.h #define hv_set_simp(val) wrmsrl(HV_X64_MSR_SIMP, val) val 23 arch/x86/include/asm/mshyperv.h #define hv_get_siefp(val) rdmsrl(HV_X64_MSR_SIEFP, val) val 24 arch/x86/include/asm/mshyperv.h #define hv_set_siefp(val) wrmsrl(HV_X64_MSR_SIEFP, val) val 26 arch/x86/include/asm/mshyperv.h #define hv_get_synic_state(val) rdmsrl(HV_X64_MSR_SCONTROL, val) val 27 arch/x86/include/asm/mshyperv.h #define hv_set_synic_state(val) wrmsrl(HV_X64_MSR_SCONTROL, val) val 33 arch/x86/include/asm/mshyperv.h #define hv_get_synint_state(int_num, val) \ val 34 arch/x86/include/asm/mshyperv.h rdmsrl(HV_X64_MSR_SINT0 + int_num, val) val 35 arch/x86/include/asm/mshyperv.h #define hv_set_synint_state(int_num, val) \ val 36 arch/x86/include/asm/mshyperv.h wrmsrl(HV_X64_MSR_SINT0 + int_num, val) val 38 arch/x86/include/asm/mshyperv.h #define hv_get_crash_ctl(val) \ val 39 arch/x86/include/asm/mshyperv.h rdmsrl(HV_X64_MSR_CRASH_CTL, val) val 41 arch/x86/include/asm/mshyperv.h #define hv_get_time_ref_count(val) \ val 42 arch/x86/include/asm/mshyperv.h rdmsrl(HV_X64_MSR_TIME_REF_COUNT, val) val 44 arch/x86/include/asm/mshyperv.h #define hv_get_reference_tsc(val) \ val 45 arch/x86/include/asm/mshyperv.h rdmsrl(HV_X64_MSR_REFERENCE_TSC, val) val 46 arch/x86/include/asm/mshyperv.h #define hv_set_reference_tsc(val) \ val 47 arch/x86/include/asm/mshyperv.h wrmsrl(HV_X64_MSR_REFERENCE_TSC, val) val 48 arch/x86/include/asm/mshyperv.h #define hv_set_clocksource_vdso(val) \ val 49 arch/x86/include/asm/mshyperv.h ((val).archdata.vclock_mode = VCLOCK_HVCLOCK) val 22 arch/x86/include/asm/msr-trace.h TP_PROTO(unsigned msr, u64 val, int failed), val 23 arch/x86/include/asm/msr-trace.h TP_ARGS(msr, val, failed), val 26 arch/x86/include/asm/msr-trace.h __field( u64, val ) val 31 arch/x86/include/asm/msr-trace.h __entry->val = val; val 36 arch/x86/include/asm/msr-trace.h __entry->val, val 41 arch/x86/include/asm/msr-trace.h TP_PROTO(unsigned msr, u64 val, int failed), val 42 arch/x86/include/asm/msr-trace.h TP_ARGS(msr, val, failed) val 46 arch/x86/include/asm/msr-trace.h TP_PROTO(unsigned msr, u64 val, int failed), val 47 arch/x86/include/asm/msr-trace.h TP_ARGS(msr, val, failed) val 51 arch/x86/include/asm/msr-trace.h TP_PROTO(unsigned msr, u64 val, int failed), val 52 arch/x86/include/asm/msr-trace.h TP_ARGS(msr, val, failed) val 54 arch/x86/include/asm/msr.h #define DECLARE_ARGS(val, low, high) unsigned long low, high val 55 arch/x86/include/asm/msr.h #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) val 56 arch/x86/include/asm/msr.h #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) val 58 arch/x86/include/asm/msr.h #define DECLARE_ARGS(val, low, high) unsigned long long val val 59 arch/x86/include/asm/msr.h #define EAX_EDX_VAL(val, low, high) (val) val 60 arch/x86/include/asm/msr.h #define EAX_EDX_RET(val, low, high) "=A" (val) val 74 arch/x86/include/asm/msr.h extern void do_trace_write_msr(unsigned int msr, u64 val, int failed); val 75 arch/x86/include/asm/msr.h extern void do_trace_read_msr(unsigned int msr, u64 val, int failed); val 76 arch/x86/include/asm/msr.h extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed); val 79 arch/x86/include/asm/msr.h static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {} val 80 arch/x86/include/asm/msr.h static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {} val 81 arch/x86/include/asm/msr.h static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {} val 93 arch/x86/include/asm/msr.h DECLARE_ARGS(val, low, high); val 98 arch/x86/include/asm/msr.h : EAX_EDX_RET(val, low, high) : "c" (msr)); val 100 arch/x86/include/asm/msr.h return EAX_EDX_VAL(val, low, high); val 121 arch/x86/include/asm/msr.h #define native_wrmsrl(msr, val) \ val 122 arch/x86/include/asm/msr.h __wrmsr((msr), (u32)((u64)(val)), \ val 123 arch/x86/include/asm/msr.h (u32)((u64)(val) >> 32)) val 127 arch/x86/include/asm/msr.h unsigned long long val; val 129 arch/x86/include/asm/msr.h val = __rdmsr(msr); val 132 arch/x86/include/asm/msr.h do_trace_read_msr(msr, val, 0); val 134 arch/x86/include/asm/msr.h return val; val 140 arch/x86/include/asm/msr.h DECLARE_ARGS(val, low, high); val 151 arch/x86/include/asm/msr.h : [err] "=r" (*err), EAX_EDX_RET(val, low, high) val 154 arch/x86/include/asm/msr.h do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err); val 155 arch/x86/include/asm/msr.h return EAX_EDX_VAL(val, low, high); val 203 arch/x86/include/asm/msr.h DECLARE_ARGS(val, low, high); val 205 arch/x86/include/asm/msr.h asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); val 207 arch/x86/include/asm/msr.h return EAX_EDX_VAL(val, low, high); val 220 arch/x86/include/asm/msr.h DECLARE_ARGS(val, low, high); val 239 arch/x86/include/asm/msr.h : EAX_EDX_RET(val, low, high) val 243 arch/x86/include/asm/msr.h return EAX_EDX_VAL(val, low, high); val 248 arch/x86/include/asm/msr.h DECLARE_ARGS(val, low, high); val 250 arch/x86/include/asm/msr.h asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); val 252 arch/x86/include/asm/msr.h do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0); val 253 arch/x86/include/asm/msr.h return EAX_EDX_VAL(val, low, high); val 278 arch/x86/include/asm/msr.h #define rdmsrl(msr, val) \ val 279 arch/x86/include/asm/msr.h ((val) = native_read_msr((msr))) val 281 arch/x86/include/asm/msr.h static inline void wrmsrl(unsigned int msr, u64 val) val 283 arch/x86/include/asm/msr.h native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32)); val 317 arch/x86/include/asm/msr.h #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) val 324 arch/x86/include/asm/msr.h static inline int wrmsrl_safe(u32 msr, u64 val) val 326 arch/x86/include/asm/msr.h return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); val 331 arch/x86/include/asm/msr.h #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) val 263 arch/x86/include/asm/nospec-branch.h void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature) val 267 arch/x86/include/asm/nospec-branch.h "a" ((u32)val), val 268 arch/x86/include/asm/nospec-branch.h "d" ((u32)(val >> 32)), val 275 arch/x86/include/asm/nospec-branch.h u64 val = PRED_CMD_IBPB; val 277 arch/x86/include/asm/nospec-branch.h alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB); val 291 arch/x86/include/asm/nospec-branch.h u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS; \ val 294 arch/x86/include/asm/nospec-branch.h alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \ val 300 arch/x86/include/asm/nospec-branch.h u64 val = x86_spec_ctrl_base; \ val 302 arch/x86/include/asm/nospec-branch.h alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \ val 50 arch/x86/include/asm/numachip/numachip_csr.h static inline void write_lcsr(unsigned long offset, unsigned int val) val 52 arch/x86/include/asm/numachip/numachip_csr.h writel(swab32(val), lcsr_address(offset)); val 83 arch/x86/include/asm/numachip/numachip_csr.h static inline void numachip2_write32_lcsr(unsigned long offset, u32 val) val 85 arch/x86/include/asm/numachip/numachip_csr.h writel(val, numachip2_lcsr_address(offset)); val 88 arch/x86/include/asm/numachip/numachip_csr.h static inline void numachip2_write64_lcsr(unsigned long offset, u64 val) val 90 arch/x86/include/asm/numachip/numachip_csr.h writeq(val, numachip2_lcsr_address(offset)); val 102 arch/x86/include/asm/paravirt.h static inline void set_debugreg(unsigned long val, int reg) val 104 arch/x86/include/asm/paravirt.h PVOP_VCALL2(cpu.set_debugreg, reg, val); val 193 arch/x86/include/asm/paravirt.h #define rdmsrl(msr, val) \ val 195 arch/x86/include/asm/paravirt.h val = paravirt_read_msr(msr); \ val 198 arch/x86/include/asm/paravirt.h static inline void wrmsrl(unsigned msr, u64 val) val 200 arch/x86/include/asm/paravirt.h wrmsr(msr, (u32)val, (u32)(val>>32)); val 235 arch/x86/include/asm/paravirt.h #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) val 362 arch/x86/include/asm/paravirt.h static inline pte_t __pte(pteval_t val) val 367 arch/x86/include/asm/paravirt.h ret = PVOP_CALLEE2(pteval_t, mmu.make_pte, val, (u64)val >> 32); val 369 arch/x86/include/asm/paravirt.h ret = PVOP_CALLEE1(pteval_t, mmu.make_pte, val); val 387 arch/x86/include/asm/paravirt.h static inline pgd_t __pgd(pgdval_t val) val 392 arch/x86/include/asm/paravirt.h ret = PVOP_CALLEE2(pgdval_t, mmu.make_pgd, val, (u64)val >> 32); val 394 arch/x86/include/asm/paravirt.h ret = PVOP_CALLEE1(pgdval_t, mmu.make_pgd, val); val 455 arch/x86/include/asm/paravirt.h pmdval_t val = native_pmd_val(pmd); val 458 arch/x86/include/asm/paravirt.h PVOP_VCALL3(mmu.set_pmd, pmdp, val, (u64)val >> 32); val 460 arch/x86/include/asm/paravirt.h PVOP_VCALL2(mmu.set_pmd, pmdp, val); val 464 arch/x86/include/asm/paravirt.h static inline pmd_t __pmd(pmdval_t val) val 469 arch/x86/include/asm/paravirt.h ret = PVOP_CALLEE2(pmdval_t, mmu.make_pmd, val, (u64)val >> 32); val 471 arch/x86/include/asm/paravirt.h ret = PVOP_CALLEE1(pmdval_t, mmu.make_pmd, val); val 491 arch/x86/include/asm/paravirt.h pudval_t val = native_pud_val(pud); val 494 arch/x86/include/asm/paravirt.h PVOP_VCALL3(mmu.set_pud, pudp, val, (u64)val >> 32); val 496 arch/x86/include/asm/paravirt.h PVOP_VCALL2(mmu.set_pud, pudp, val); val 499 arch/x86/include/asm/paravirt.h static inline pud_t __pud(pudval_t val) val 503 arch/x86/include/asm/paravirt.h ret = PVOP_CALLEE1(pudval_t, mmu.make_pud, val); val 520 arch/x86/include/asm/paravirt.h p4dval_t val = native_p4d_val(p4d); val 522 arch/x86/include/asm/paravirt.h PVOP_VCALL2(mmu.set_p4d, p4dp, val); val 527 arch/x86/include/asm/paravirt.h static inline p4d_t __p4d(p4dval_t val) val 529 arch/x86/include/asm/paravirt.h p4dval_t ret = PVOP_CALLEE1(p4dval_t, mmu.make_p4d, val); val 640 arch/x86/include/asm/paravirt.h u32 val) val 642 arch/x86/include/asm/paravirt.h PVOP_VCALL2(lock.queued_spin_lock_slowpath, lock, val); val 650 arch/x86/include/asm/paravirt.h static __always_inline void pv_wait(u8 *ptr, u8 val) val 652 arch/x86/include/asm/paravirt.h PVOP_VCALL2(lock.wait, ptr, val); val 314 arch/x86/include/asm/paravirt_types.h void (*queued_spin_lock_slowpath)(struct qspinlock *lock, u32 val); val 317 arch/x86/include/asm/paravirt_types.h void (*wait)(u8 *ptr, u8 val); val 13 arch/x86/include/asm/pci-direct.h extern void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, u32 val); val 14 arch/x86/include/asm/pci-direct.h extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val); val 15 arch/x86/include/asm/pci-direct.h extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val); val 14 arch/x86/include/asm/pci_64.h static inline void set_pci_iommu(struct pci_bus *bus, void *val) val 17 arch/x86/include/asm/pci_64.h sd->iommu = val; val 104 arch/x86/include/asm/pci_x86.h int reg, int len, u32 *val); val 106 arch/x86/include/asm/pci_x86.h int reg, int len, u32 val); val 177 arch/x86/include/asm/pci_x86.h u8 val; val 178 arch/x86/include/asm/pci_x86.h asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos)); val 179 arch/x86/include/asm/pci_x86.h return val; val 184 arch/x86/include/asm/pci_x86.h u16 val; val 185 arch/x86/include/asm/pci_x86.h asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos)); val 186 arch/x86/include/asm/pci_x86.h return val; val 191 arch/x86/include/asm/pci_x86.h u32 val; val 192 arch/x86/include/asm/pci_x86.h asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos)); val 193 arch/x86/include/asm/pci_x86.h return val; val 196 arch/x86/include/asm/pci_x86.h static inline void mmio_config_writeb(void __iomem *pos, u8 val) val 198 arch/x86/include/asm/pci_x86.h asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory"); val 201 arch/x86/include/asm/pci_x86.h static inline void mmio_config_writew(void __iomem *pos, u16 val) val 203 arch/x86/include/asm/pci_x86.h asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory"); val 206 arch/x86/include/asm/pci_x86.h static inline void mmio_config_writel(void __iomem *pos, u32 val) val 208 arch/x86/include/asm/pci_x86.h asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory"); val 90 arch/x86/include/asm/percpu.h #define percpu_to_op(qual, op, var, val) \ val 95 arch/x86/include/asm/percpu.h pto_tmp__ = (val); \ val 102 arch/x86/include/asm/percpu.h : "qi" ((pto_T__)(val))); \ val 107 arch/x86/include/asm/percpu.h : "ri" ((pto_T__)(val))); \ val 112 arch/x86/include/asm/percpu.h : "ri" ((pto_T__)(val))); \ val 117 arch/x86/include/asm/percpu.h : "re" ((pto_T__)(val))); \ val 127 arch/x86/include/asm/percpu.h #define percpu_add_op(qual, var, val) \ val 130 arch/x86/include/asm/percpu.h const int pao_ID__ = (__builtin_constant_p(val) && \ val 131 arch/x86/include/asm/percpu.h ((val) == 1 || (val) == -1)) ? \ val 132 arch/x86/include/asm/percpu.h (int)(val) : 0; \ val 135 arch/x86/include/asm/percpu.h pao_tmp__ = (val); \ val 147 arch/x86/include/asm/percpu.h : "qi" ((pao_T__)(val))); \ val 157 arch/x86/include/asm/percpu.h : "ri" ((pao_T__)(val))); \ val 167 arch/x86/include/asm/percpu.h : "ri" ((pao_T__)(val))); \ val 177 arch/x86/include/asm/percpu.h : "re" ((pao_T__)(val))); \ val 267 arch/x86/include/asm/percpu.h #define percpu_add_return_op(qual, var, val) \ val 269 arch/x86/include/asm/percpu.h typeof(var) paro_ret__ = val; \ val 293 arch/x86/include/asm/percpu.h paro_ret__ += val; \ val 398 arch/x86/include/asm/percpu.h #define raw_cpu_write_1(pcp, val) percpu_to_op(, "mov", (pcp), val) val 399 arch/x86/include/asm/percpu.h #define raw_cpu_write_2(pcp, val) percpu_to_op(, "mov", (pcp), val) val 400 arch/x86/include/asm/percpu.h #define raw_cpu_write_4(pcp, val) percpu_to_op(, "mov", (pcp), val) val 401 arch/x86/include/asm/percpu.h #define raw_cpu_add_1(pcp, val) percpu_add_op(, (pcp), val) val 402 arch/x86/include/asm/percpu.h #define raw_cpu_add_2(pcp, val) percpu_add_op(, (pcp), val) val 403 arch/x86/include/asm/percpu.h #define raw_cpu_add_4(pcp, val) percpu_add_op(, (pcp), val) val 404 arch/x86/include/asm/percpu.h #define raw_cpu_and_1(pcp, val) percpu_to_op(, "and", (pcp), val) val 405 arch/x86/include/asm/percpu.h #define raw_cpu_and_2(pcp, val) percpu_to_op(, "and", (pcp), val) val 406 arch/x86/include/asm/percpu.h #define raw_cpu_and_4(pcp, val) percpu_to_op(, "and", (pcp), val) val 407 arch/x86/include/asm/percpu.h #define raw_cpu_or_1(pcp, val) percpu_to_op(, "or", (pcp), val) val 408 arch/x86/include/asm/percpu.h #define raw_cpu_or_2(pcp, val) percpu_to_op(, "or", (pcp), val) val 409 arch/x86/include/asm/percpu.h #define raw_cpu_or_4(pcp, val) percpu_to_op(, "or", (pcp), val) val 422 arch/x86/include/asm/percpu.h #define raw_cpu_xchg_1(pcp, val) raw_percpu_xchg_op(pcp, val) val 423 arch/x86/include/asm/percpu.h #define raw_cpu_xchg_2(pcp, val) raw_percpu_xchg_op(pcp, val) val 424 arch/x86/include/asm/percpu.h #define raw_cpu_xchg_4(pcp, val) raw_percpu_xchg_op(pcp, val) val 429 arch/x86/include/asm/percpu.h #define this_cpu_write_1(pcp, val) percpu_to_op(volatile, "mov", (pcp), val) val 430 arch/x86/include/asm/percpu.h #define this_cpu_write_2(pcp, val) percpu_to_op(volatile, "mov", (pcp), val) val 431 arch/x86/include/asm/percpu.h #define this_cpu_write_4(pcp, val) percpu_to_op(volatile, "mov", (pcp), val) val 432 arch/x86/include/asm/percpu.h #define this_cpu_add_1(pcp, val) percpu_add_op(volatile, (pcp), val) val 433 arch/x86/include/asm/percpu.h #define this_cpu_add_2(pcp, val) percpu_add_op(volatile, (pcp), val) val 434 arch/x86/include/asm/percpu.h #define this_cpu_add_4(pcp, val) percpu_add_op(volatile, (pcp), val) val 435 arch/x86/include/asm/percpu.h #define this_cpu_and_1(pcp, val) percpu_to_op(volatile, "and", (pcp), val) val 436 arch/x86/include/asm/percpu.h #define this_cpu_and_2(pcp, val) percpu_to_op(volatile, "and", (pcp), val) val 437 arch/x86/include/asm/percpu.h #define this_cpu_and_4(pcp, val) percpu_to_op(volatile, "and", (pcp), val) val 438 arch/x86/include/asm/percpu.h #define this_cpu_or_1(pcp, val) percpu_to_op(volatile, "or", (pcp), val) val 439 arch/x86/include/asm/percpu.h #define this_cpu_or_2(pcp, val) percpu_to_op(volatile, "or", (pcp), val) val 440 arch/x86/include/asm/percpu.h #define this_cpu_or_4(pcp, val) percpu_to_op(volatile, "or", (pcp), val) val 445 arch/x86/include/asm/percpu.h #define raw_cpu_add_return_1(pcp, val) percpu_add_return_op(, pcp, val) val 446 arch/x86/include/asm/percpu.h #define raw_cpu_add_return_2(pcp, val) percpu_add_return_op(, pcp, val) val 447 arch/x86/include/asm/percpu.h #define raw_cpu_add_return_4(pcp, val) percpu_add_return_op(, pcp, val) val 452 arch/x86/include/asm/percpu.h #define this_cpu_add_return_1(pcp, val) percpu_add_return_op(volatile, pcp, val) val 453 arch/x86/include/asm/percpu.h #define this_cpu_add_return_2(pcp, val) percpu_add_return_op(volatile, pcp, val) val 454 arch/x86/include/asm/percpu.h #define this_cpu_add_return_4(pcp, val) percpu_add_return_op(volatile, pcp, val) val 482 arch/x86/include/asm/percpu.h #define raw_cpu_write_8(pcp, val) percpu_to_op(, "mov", (pcp), val) val 483 arch/x86/include/asm/percpu.h #define raw_cpu_add_8(pcp, val) percpu_add_op(, (pcp), val) val 484 arch/x86/include/asm/percpu.h #define raw_cpu_and_8(pcp, val) percpu_to_op(, "and", (pcp), val) val 485 arch/x86/include/asm/percpu.h #define raw_cpu_or_8(pcp, val) percpu_to_op(, "or", (pcp), val) val 486 arch/x86/include/asm/percpu.h #define raw_cpu_add_return_8(pcp, val) percpu_add_return_op(, pcp, val) val 491 arch/x86/include/asm/percpu.h #define this_cpu_write_8(pcp, val) percpu_to_op(volatile, "mov", (pcp), val) val 492 arch/x86/include/asm/percpu.h #define this_cpu_add_8(pcp, val) percpu_add_op(volatile, (pcp), val) val 493 arch/x86/include/asm/percpu.h #define this_cpu_and_8(pcp, val) percpu_to_op(volatile, "and", (pcp), val) val 494 arch/x86/include/asm/percpu.h #define this_cpu_or_8(pcp, val) percpu_to_op(volatile, "or", (pcp), val) val 495 arch/x86/include/asm/percpu.h #define this_cpu_add_return_8(pcp, val) percpu_add_return_op(volatile, pcp, val) val 89 arch/x86/include/asm/pgtable-2level.h #define __swp_type(x) (((x).val >> (_PAGE_BIT_PRESENT + 1)) \ val 91 arch/x86/include/asm/pgtable-2level.h #define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT) val 96 arch/x86/include/asm/pgtable-2level.h #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val }) val 100 arch/x86/include/asm/pgtable-2level.h static inline u64 protnone_mask(u64 val) val 105 arch/x86/include/asm/pgtable-2level.h static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask) val 107 arch/x86/include/asm/pgtable-2level.h return val; val 110 arch/x86/include/asm/pgtable-2level.h static inline bool __pte_needs_invert(u64 val) val 258 arch/x86/include/asm/pgtable-3level.h #define __swp_type(x) (((x).val) & 0x1f) val 259 arch/x86/include/asm/pgtable-3level.h #define __swp_offset(x) ((x).val >> 5) val 16 arch/x86/include/asm/pgtable-invert.h static inline bool __pte_needs_invert(u64 val) val 18 arch/x86/include/asm/pgtable-invert.h return val && !(val & _PAGE_PRESENT); val 22 arch/x86/include/asm/pgtable-invert.h static inline u64 protnone_mask(u64 val) val 24 arch/x86/include/asm/pgtable-invert.h return __pte_needs_invert(val) ? ~0ull : 0; val 27 arch/x86/include/asm/pgtable-invert.h static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask) val 34 arch/x86/include/asm/pgtable-invert.h if (__pte_needs_invert(oldval) != __pte_needs_invert(val)) val 35 arch/x86/include/asm/pgtable-invert.h val = (val & ~mask) | (~val & mask); val 36 arch/x86/include/asm/pgtable-invert.h return val; val 209 arch/x86/include/asm/pgtable.h static inline u64 protnone_mask(u64 val); val 602 arch/x86/include/asm/pgtable.h static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask); val 606 arch/x86/include/asm/pgtable.h pteval_t val = pte_val(pte), oldval = val; val 612 arch/x86/include/asm/pgtable.h val &= _PAGE_CHG_MASK; val 613 arch/x86/include/asm/pgtable.h val |= check_pgprot(newprot) & ~_PAGE_CHG_MASK; val 614 arch/x86/include/asm/pgtable.h val = flip_protnone_guard(oldval, val, PTE_PFN_MASK); val 615 arch/x86/include/asm/pgtable.h return __pte(val); val 620 arch/x86/include/asm/pgtable.h pmdval_t val = pmd_val(pmd), oldval = val; val 622 arch/x86/include/asm/pgtable.h val &= _HPAGE_CHG_MASK; val 623 arch/x86/include/asm/pgtable.h val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; val 624 arch/x86/include/asm/pgtable.h val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK); val 625 arch/x86/include/asm/pgtable.h return __pmd(val); val 792 arch/x86/include/asm/pgtable.h unsigned long val = native_pmd_val(pmd); val 793 arch/x86/include/asm/pgtable.h return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0; val 219 arch/x86/include/asm/pgtable_64.h #define __swp_type(x) ((x).val >> (64 - SWP_TYPE_BITS)) val 222 arch/x86/include/asm/pgtable_64.h #define __swp_offset(x) (~(x).val << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT) val 235 arch/x86/include/asm/pgtable_64.h #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val }) val 236 arch/x86/include/asm/pgtable_64.h #define __swp_entry_to_pmd(x) ((pmd_t) { .pmd = (x).val }) val 292 arch/x86/include/asm/pgtable_types.h static inline pgd_t native_make_pgd(pgdval_t val) val 294 arch/x86/include/asm/pgtable_types.h return (pgd_t) { val & PGD_ALLOWED_BITS }; val 310 arch/x86/include/asm/pgtable_types.h static inline p4d_t native_make_p4d(pudval_t val) val 312 arch/x86/include/asm/pgtable_types.h return (p4d_t) { val }; val 322 arch/x86/include/asm/pgtable_types.h static inline p4d_t native_make_p4d(pudval_t val) val 324 arch/x86/include/asm/pgtable_types.h return (p4d_t) { .pgd = native_make_pgd((pgdval_t)val) }; val 336 arch/x86/include/asm/pgtable_types.h static inline pud_t native_make_pud(pmdval_t val) val 338 arch/x86/include/asm/pgtable_types.h return (pud_t) { val }; val 348 arch/x86/include/asm/pgtable_types.h static inline pud_t native_make_pud(pudval_t val) val 350 arch/x86/include/asm/pgtable_types.h return (pud_t) { .p4d.pgd = native_make_pgd(val) }; val 362 arch/x86/include/asm/pgtable_types.h static inline pmd_t native_make_pmd(pmdval_t val) val 364 arch/x86/include/asm/pgtable_types.h return (pmd_t) { val }; val 374 arch/x86/include/asm/pgtable_types.h static inline pmd_t native_make_pmd(pmdval_t val) val 376 arch/x86/include/asm/pgtable_types.h return (pmd_t) { .pud.p4d.pgd = native_make_pgd(val) }; val 437 arch/x86/include/asm/pgtable_types.h static inline pte_t native_make_pte(pteval_t val) val 439 arch/x86/include/asm/pgtable_types.h return (pte_t) { .pte = val }; val 488 arch/x86/include/asm/pgtable_types.h pgprotval_t val = pgprot_val(pgprot); val 491 arch/x86/include/asm/pgtable_types.h pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) | val 492 arch/x86/include/asm/pgtable_types.h ((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT)); val 497 arch/x86/include/asm/pgtable_types.h pgprotval_t val = pgprot_val(pgprot); val 500 arch/x86/include/asm/pgtable_types.h pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) | val 501 arch/x86/include/asm/pgtable_types.h ((val & _PAGE_PAT_LARGE) >> val 77 arch/x86/include/asm/preempt.h static __always_inline void __preempt_count_add(int val) val 79 arch/x86/include/asm/preempt.h raw_cpu_add_4(__preempt_count, val); val 82 arch/x86/include/asm/preempt.h static __always_inline void __preempt_count_sub(int val) val 84 arch/x86/include/asm/preempt.h raw_cpu_add_4(__preempt_count, -val); val 911 arch/x86/include/asm/processor.h #define SET_TSC_CTL(val) set_tsc_mode((val)) val 914 arch/x86/include/asm/processor.h extern int set_tsc_mode(unsigned int val); val 178 arch/x86/include/asm/ptrace.h unsigned long val) val 180 arch/x86/include/asm/ptrace.h regs->ip = val; val 194 arch/x86/include/asm/ptrace.h unsigned long val) val 196 arch/x86/include/asm/ptrace.h regs->sp = val; val 283 arch/x86/include/asm/ptrace.h unsigned long val; val 288 arch/x86/include/asm/ptrace.h ret = probe_kernel_read(&val, addr, sizeof(val)); val 290 arch/x86/include/asm/ptrace.h return val; val 16 arch/x86/include/asm/qspinlock.h u32 val; val 23 arch/x86/include/asm/qspinlock.h val = GEN_BINARY_RMWcc(LOCK_PREFIX "btsl", lock->val.counter, c, val 25 arch/x86/include/asm/qspinlock.h val |= atomic_read(&lock->val) & ~_Q_PENDING_MASK; val 27 arch/x86/include/asm/qspinlock.h return val; val 31 arch/x86/include/asm/qspinlock.h extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); val 33 arch/x86/include/asm/qspinlock.h extern void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); val 48 arch/x86/include/asm/qspinlock.h static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) val 50 arch/x86/include/asm/qspinlock.h pv_queued_spin_lock_slowpath(lock, val); val 98 arch/x86/include/asm/qspinlock.h while (atomic_read(&lock->val) != 0) val 100 arch/x86/include/asm/qspinlock.h } while (atomic_cmpxchg(&lock->val, 0, _Q_LOCKED_VAL) != 0); val 55 arch/x86/include/asm/rmwcc.h __CLOBBERS_MEM(), [val] vcon (_val)) val 57 arch/x86/include/asm/rmwcc.h #define GEN_BINARY_RMWcc_5(op, var, cc, vcon, val) \ val 58 arch/x86/include/asm/rmwcc.h GEN_BINARY_RMWcc_6(op, var, cc, vcon, val, "%[var]") val 68 arch/x86/include/asm/rmwcc.h __CLOBBERS_MEM(clobbers), [val] vcon (_val)) val 21 arch/x86/include/asm/special_insns.h void native_write_cr0(unsigned long val); val 25 arch/x86/include/asm/special_insns.h unsigned long val; val 26 arch/x86/include/asm/special_insns.h asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order)); val 27 arch/x86/include/asm/special_insns.h return val; val 32 arch/x86/include/asm/special_insns.h unsigned long val; val 33 arch/x86/include/asm/special_insns.h asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order)); val 34 arch/x86/include/asm/special_insns.h return val; val 37 arch/x86/include/asm/special_insns.h static inline void native_write_cr2(unsigned long val) val 39 arch/x86/include/asm/special_insns.h asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order)); val 44 arch/x86/include/asm/special_insns.h unsigned long val; val 45 arch/x86/include/asm/special_insns.h asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order)); val 46 arch/x86/include/asm/special_insns.h return val; val 49 arch/x86/include/asm/special_insns.h static inline void native_write_cr3(unsigned long val) val 51 arch/x86/include/asm/special_insns.h asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order)); val 56 arch/x86/include/asm/special_insns.h unsigned long val; val 66 arch/x86/include/asm/special_insns.h : "=r" (val), "=m" (__force_order) : "0" (0)); val 69 arch/x86/include/asm/special_insns.h asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order)); val 71 arch/x86/include/asm/special_insns.h return val; val 74 arch/x86/include/asm/special_insns.h void native_write_cr4(unsigned long val); val 86 arch/x86/include/asm/syscall.h int error, long val) val 88 arch/x86/include/asm/syscall.h regs->ax = (long) error ?: val; val 69 arch/x86/include/asm/text-patching.h static inline void int3_emulate_push(struct pt_regs *regs, unsigned long val) val 78 arch/x86/include/asm/text-patching.h *(unsigned long *)regs->sp = val; val 109 arch/x86/include/asm/unwind.h unsigned long val; \ val 111 arch/x86/include/asm/unwind.h val = READ_ONCE(x); \ val 113 arch/x86/include/asm/unwind.h val = READ_ONCE_NOCHECK(x); \ val 114 arch/x86/include/asm/unwind.h val; \ val 111 arch/x86/include/asm/uv/bios.h u64 val; val 636 arch/x86/include/asm/uv/uv_hub.h static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) val 638 arch/x86/include/asm/uv/uv_hub.h writeq(val, uv_global_mmr32_address(pnode, offset)); val 656 arch/x86/include/asm/uv/uv_hub.h static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) val 658 arch/x86/include/asm/uv/uv_hub.h writeq(val, uv_global_mmr64_address(pnode, offset)); val 666 arch/x86/include/asm/uv/uv_hub.h static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) val 668 arch/x86/include/asm/uv/uv_hub.h writeb(val, uv_global_mmr64_address(pnode, offset)); val 690 arch/x86/include/asm/uv/uv_hub.h static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) val 692 arch/x86/include/asm/uv/uv_hub.h writeq(val, uv_local_mmr_address(offset)); val 700 arch/x86/include/asm/uv/uv_hub.h static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) val 702 arch/x86/include/asm/uv/uv_hub.h writeb(val, uv_local_mmr_address(offset)); val 891 arch/x86/include/asm/uv/uv_hub.h unsigned long val; val 897 arch/x86/include/asm/uv/uv_hub.h val = uv_hub_ipi_value(apicid, vector, dmode); val 898 arch/x86/include/asm/uv/uv_hub.h uv_write_global_mmr64(pnode, UVH_IPI_INT, val); val 24 arch/x86/include/asm/xen/events.h #define xchg_xen_ulong(ptr, val) xchg((ptr), (val)) val 53 arch/x86/include/asm/xen/interface.h #define set_xen_guest_handle(hnd, val) \ val 57 arch/x86/include/asm/xen/interface.h (hnd).p = val; \ val 60 arch/x86/include/asm/xen/interface.h #define set_xen_guest_handle(hnd, val) do { (hnd).p = val; } while (0) val 64 arch/x86/include/asm/xen/interface.h #define set_xen_guest_handle(hnd, val) \ val 68 arch/x86/include/asm/xen/interface.h (hnd) = val; \ val 71 arch/x86/include/asm/xen/interface.h #define set_xen_guest_handle(hnd, val) do { (hnd) = val; } while (0) val 94 arch/x86/include/asm/xen/page.h static inline int xen_safe_write_ulong(unsigned long *addr, unsigned long val) val 106 arch/x86/include/asm/xen/page.h : [val] "r" (val)); val 112 arch/x86/include/asm/xen/page.h unsigned long *val) val 126 arch/x86/include/asm/xen/page.h *val = rval; val 8 arch/x86/include/uapi/asm/swab.h static inline __attribute_const__ __u32 __arch_swab32(__u32 val) val 10 arch/x86/include/uapi/asm/swab.h asm("bswapl %0" : "=r" (val) : "0" (val)); val 11 arch/x86/include/uapi/asm/swab.h return val; val 15 arch/x86/include/uapi/asm/swab.h static inline __attribute_const__ __u64 __arch_swab64(__u64 val) val 25 arch/x86/include/uapi/asm/swab.h v.u = val; val 31 arch/x86/include/uapi/asm/swab.h asm("bswapq %0" : "=r" (val) : "0" (val)); val 32 arch/x86/include/uapi/asm/swab.h return val; val 1737 arch/x86/kernel/acpi/boot.c unsigned int old, new, val; val 1741 arch/x86/kernel/acpi/boot.c val = cmpxchg(lock, old, new); val 1742 arch/x86/kernel/acpi/boot.c } while (unlikely (val != old)); val 1748 arch/x86/kernel/acpi/boot.c unsigned int old, new, val; val 1752 arch/x86/kernel/acpi/boot.c val = cmpxchg(lock, old, new); val 1753 arch/x86/kernel/acpi/boot.c } while (unlikely (val != old)); val 17 arch/x86/kernel/acpi/cppc_msr.c int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) val 21 arch/x86/kernel/acpi/cppc_msr.c err = rdmsrl_safe_on_cpu(cpunum, reg->address, val); val 26 arch/x86/kernel/acpi/cppc_msr.c *val &= mask; val 27 arch/x86/kernel/acpi/cppc_msr.c *val >>= reg->bit_offset; val 32 arch/x86/kernel/acpi/cppc_msr.c int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) val 42 arch/x86/kernel/acpi/cppc_msr.c val <<= reg->bit_offset; val 43 arch/x86/kernel/acpi/cppc_msr.c val &= mask; val 45 arch/x86/kernel/acpi/cppc_msr.c rd_val |= val; val 649 arch/x86/kernel/alternative.c int3_exception_notify(struct notifier_block *self, unsigned long val, void *data) val 657 arch/x86/kernel/alternative.c if (val != DIE_INT3) val 673 arch/x86/kernel/alternative.c unsigned int val = 0; val 693 arch/x86/kernel/alternative.c : __ASM_SEL_RAW(a, D) (&val) val 696 arch/x86/kernel/alternative.c BUG_ON(val != 1); val 501 arch/x86/kernel/amd_nb.c u32 val; val 513 arch/x86/kernel/amd_nb.c if (pci_read_config_dword(F4, 0x164, &val)) val 516 arch/x86/kernel/amd_nb.c if (val & BIT(2)) val 40 arch/x86/kernel/apic/apic_flat_64.c unsigned long val; val 46 arch/x86/kernel/apic/apic_flat_64.c val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; val 47 arch/x86/kernel/apic/apic_flat_64.c val |= SET_APIC_LOGICAL_ID(id); val 48 arch/x86/kernel/apic/apic_flat_64.c apic_write(APIC_LDR, val); val 26 arch/x86/kernel/apic/apic_numachip.c static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly; val 75 arch/x86/kernel/apic/apic_numachip.c static void numachip1_apic_icr_write(int apicid, unsigned int val) val 77 arch/x86/kernel/apic/apic_numachip.c write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val); val 80 arch/x86/kernel/apic/apic_numachip.c static void numachip2_apic_icr_write(int apicid, unsigned int val) val 82 arch/x86/kernel/apic/apic_numachip.c numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val); val 172 arch/x86/kernel/apic/apic_numachip.c u64 val; val 179 arch/x86/kernel/apic/apic_numachip.c rdmsrl(MSR_FAM10H_NODE_ID, val); val 180 arch/x86/kernel/apic/apic_numachip.c nodes = ((val >> 3) & 7) + 1; val 44 arch/x86/kernel/apic/probe_32.c unsigned long val; val 47 arch/x86/kernel/apic/probe_32.c val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; val 48 arch/x86/kernel/apic/probe_32.c val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); val 49 arch/x86/kernel/apic/probe_32.c apic_write(APIC_LDR, val); val 70 arch/x86/kernel/apic/x2apic_uv_x.c unsigned long val, *mmr; val 73 arch/x86/kernel/apic/x2apic_uv_x.c val = *mmr; val 76 arch/x86/kernel/apic/x2apic_uv_x.c return val; val 519 arch/x86/kernel/apic/x2apic_uv_x.c unsigned long val; val 525 arch/x86/kernel/apic/x2apic_uv_x.c val = (1UL << UVH_IPI_INT_SEND_SHFT) | val 530 arch/x86/kernel/apic/x2apic_uv_x.c uv_write_global_mmr64(pnode, UVH_IPI_INT, val); val 532 arch/x86/kernel/apic/x2apic_uv_x.c val = (1UL << UVH_IPI_INT_SEND_SHFT) | val 537 arch/x86/kernel/apic/x2apic_uv_x.c uv_write_global_mmr64(pnode, UVH_IPI_INT, val); val 745 arch/x86/kernel/apm_32.c static int apm_driver_version(u_short *val) val 750 arch/x86/kernel/apm_32.c if (apm_bios_call_simple(APM_FUNC_VERSION, 0, *val, &eax, &err)) val 752 arch/x86/kernel/apm_32.c *val = eax; val 36 arch/x86/kernel/check.c unsigned long val; val 43 arch/x86/kernel/check.c ret = kstrtoul(arg, 10, &val); val 47 arch/x86/kernel/check.c memory_corruption_check = val; val 56 arch/x86/kernel/check.c unsigned long val; val 63 arch/x86/kernel/check.c ret = kstrtoul(arg, 10, &val); val 67 arch/x86/kernel/check.c corruption_check_period = val; val 59 arch/x86/kernel/cpu/amd.c static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) val 66 arch/x86/kernel/cpu/amd.c gprs[0] = (u32)val; val 68 arch/x86/kernel/cpu/amd.c gprs[2] = val >> 32; val 519 arch/x86/kernel/cpu/amd.c u64 val; val 521 arch/x86/kernel/cpu/amd.c rdmsrl(MSR_K7_HWCR, val); val 522 arch/x86/kernel/cpu/amd.c if (!(val & BIT(24))) val 676 arch/x86/kernel/cpu/amd.c unsigned int val; val 678 arch/x86/kernel/cpu/amd.c val = read_pci_config(0, 24, 0, 0x68); val 679 arch/x86/kernel/cpu/amd.c if ((val >> 17 & 0x3) == 0x3) val 181 arch/x86/kernel/cpu/cacheinfo.c unsigned val; val 191 arch/x86/kernel/cpu/cacheinfo.c unsigned val; val 202 arch/x86/kernel/cpu/cacheinfo.c unsigned val; val 245 arch/x86/kernel/cpu/cacheinfo.c cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); val 246 arch/x86/kernel/cpu/cacheinfo.c cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); val 253 arch/x86/kernel/cpu/cacheinfo.c if (!l1->val) val 261 arch/x86/kernel/cpu/cacheinfo.c if (!l2.val) val 270 arch/x86/kernel/cpu/cacheinfo.c if (!l3.val) val 310 arch/x86/kernel/cpu/cacheinfo.c u32 val = 0; val 312 arch/x86/kernel/cpu/cacheinfo.c pci_read_config_dword(nb->misc, 0x1C4, &val); val 315 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[0] = sc0 = !(val & BIT(0)); val 316 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[1] = sc1 = !(val & BIT(4)); val 319 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[0] = sc0 += !(val & BIT(1)); val 320 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[1] = sc1 += !(val & BIT(5)); val 323 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9)); val 324 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13)); val 439 arch/x86/kernel/cpu/cacheinfo.c unsigned long val = 0; val 448 arch/x86/kernel/cpu/cacheinfo.c if (kstrtoul(buf, 10, &val) < 0) val 451 arch/x86/kernel/cpu/cacheinfo.c err = amd_set_l3_disable_slot(nb, cpu, slot, val); val 488 arch/x86/kernel/cpu/cacheinfo.c unsigned long val; val 493 arch/x86/kernel/cpu/cacheinfo.c if (kstrtoul(buf, 16, &val) < 0) val 496 arch/x86/kernel/cpu/cacheinfo.c if (amd_set_subcaches(cpu, val)) val 372 arch/x86/kernel/cpu/common.c void native_write_cr0(unsigned long val) val 377 arch/x86/kernel/cpu/common.c asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); val 380 arch/x86/kernel/cpu/common.c if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { val 382 arch/x86/kernel/cpu/common.c val |= bits_missing; val 391 arch/x86/kernel/cpu/common.c void native_write_cr4(unsigned long val) val 396 arch/x86/kernel/cpu/common.c asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits)); val 399 arch/x86/kernel/cpu/common.c if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) { val 400 arch/x86/kernel/cpu/common.c bits_missing = ~val & cr4_pinned_bits; val 401 arch/x86/kernel/cpu/common.c val |= bits_missing; val 224 arch/x86/kernel/cpu/hygon.c u64 val; val 226 arch/x86/kernel/cpu/hygon.c rdmsrl(MSR_K7_HWCR, val); val 227 arch/x86/kernel/cpu/hygon.c if (!(val & BIT(24))) val 77 arch/x86/kernel/cpu/intel_epb.c u64 val = this_cpu_read(saved_epb); val 81 arch/x86/kernel/cpu/intel_epb.c if (val) { val 82 arch/x86/kernel/cpu/intel_epb.c val &= EPB_MASK; val 91 arch/x86/kernel/cpu/intel_epb.c val = epb & EPB_MASK; val 92 arch/x86/kernel/cpu/intel_epb.c if (val == ENERGY_PERF_BIAS_PERFORMANCE) { val 93 arch/x86/kernel/cpu/intel_epb.c val = ENERGY_PERF_BIAS_NORMAL; val 97 arch/x86/kernel/cpu/intel_epb.c wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); val 140 arch/x86/kernel/cpu/intel_epb.c u64 epb, val; val 146 arch/x86/kernel/cpu/intel_epb.c val = energ_perf_values[ret]; val 147 arch/x86/kernel/cpu/intel_epb.c else if (kstrtou64(buf, 0, &val) || val > MAX_EPB) val 155 arch/x86/kernel/cpu/intel_epb.c (epb & ~EPB_MASK) | val); val 1116 arch/x86/kernel/cpu/mce/amd.c #define RW_ATTR(val) \ val 1117 arch/x86/kernel/cpu/mce/amd.c static struct threshold_attr val = { \ val 1118 arch/x86/kernel/cpu/mce/amd.c .attr = {.name = __stringify(val), .mode = 0644 }, \ val 1119 arch/x86/kernel/cpu/mce/amd.c .show = show_## val, \ val 1120 arch/x86/kernel/cpu/mce/amd.c .store = store_## val, \ val 573 arch/x86/kernel/cpu/mce/core.c static int mce_first_notifier(struct notifier_block *nb, unsigned long val, val 599 arch/x86/kernel/cpu/mce/core.c static int srao_decode_notifier(struct notifier_block *nb, unsigned long val, val 621 arch/x86/kernel/cpu/mce/core.c static int mce_default_notifier(struct notifier_block *nb, unsigned long val, val 2510 arch/x86/kernel/cpu/mce/core.c static int fake_panic_get(void *data, u64 *val) val 2512 arch/x86/kernel/cpu/mce/core.c *val = fake_panic; val 2516 arch/x86/kernel/cpu/mce/core.c static int fake_panic_set(void *data, u64 val) val 2519 arch/x86/kernel/cpu/mce/core.c fake_panic = val; val 40 arch/x86/kernel/cpu/mce/dev-mcelog.c static int dev_mce_log(struct notifier_block *nb, unsigned long val, val 65 arch/x86/kernel/cpu/mce/inject.c static int inj_##reg##_set(void *data, u64 val) \ val 69 arch/x86/kernel/cpu/mce/inject.c m->reg = val; \ val 79 arch/x86/kernel/cpu/mce/inject.c static int inj_##reg##_get(void *data, u64 *val) \ val 83 arch/x86/kernel/cpu/mce/inject.c *val = m->reg; \ val 277 arch/x86/kernel/cpu/mce/inject.c static int mce_inject_raise(struct notifier_block *nb, unsigned long val, val 383 arch/x86/kernel/cpu/mce/inject.c static int inj_extcpu_set(void *data, u64 val) val 387 arch/x86/kernel/cpu/mce/inject.c if (val >= nr_cpu_ids || !cpu_online(val)) { val 388 arch/x86/kernel/cpu/mce/inject.c pr_err("%s: Invalid CPU: %llu\n", __func__, val); val 391 arch/x86/kernel/cpu/mce/inject.c m->extcpu = val; val 426 arch/x86/kernel/cpu/mce/inject.c u32 val; val 437 arch/x86/kernel/cpu/mce/inject.c err = pci_read_config_dword(F3, NBCFG, &val); val 444 arch/x86/kernel/cpu/mce/inject.c if (val & BIT(27)) val 450 arch/x86/kernel/cpu/mce/inject.c val |= BIT(27); val 451 arch/x86/kernel/cpu/mce/inject.c err = pci_write_config_dword(F3, NBCFG, val); val 561 arch/x86/kernel/cpu/mce/inject.c static int inj_bank_set(void *data, u64 val) val 571 arch/x86/kernel/cpu/mce/inject.c if (val >= n_banks) { val 572 arch/x86/kernel/cpu/mce/inject.c pr_err("MCA bank %llu non-existent on CPU%d\n", val, m->extcpu); val 576 arch/x86/kernel/cpu/mce/inject.c m->bank = val; val 156 arch/x86/kernel/cpu/mce/intel.c u64 val; val 161 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(bank), val); val 164 arch/x86/kernel/cpu/mce/intel.c val |= MCI_CTL2_CMCI_EN; val 166 arch/x86/kernel/cpu/mce/intel.c val &= ~MCI_CTL2_CMCI_EN; val 168 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCx_CTL2(bank), val); val 273 arch/x86/kernel/cpu/mce/intel.c u64 val; val 283 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(i), val); val 286 arch/x86/kernel/cpu/mce/intel.c if (val & MCI_CTL2_CMCI_EN) { val 293 arch/x86/kernel/cpu/mce/intel.c val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK; val 294 arch/x86/kernel/cpu/mce/intel.c val |= CMCI_THRESHOLD; val 295 arch/x86/kernel/cpu/mce/intel.c } else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) { val 302 arch/x86/kernel/cpu/mce/intel.c val |= CMCI_THRESHOLD; val 305 arch/x86/kernel/cpu/mce/intel.c val |= MCI_CTL2_CMCI_EN; val 306 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCx_CTL2(i), val); val 307 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(i), val); val 310 arch/x86/kernel/cpu/mce/intel.c if (val & MCI_CTL2_CMCI_EN) { val 320 arch/x86/kernel/cpu/mce/intel.c (val & MCI_CTL2_CMCI_THRESHOLD_MASK)) val 355 arch/x86/kernel/cpu/mce/intel.c u64 val; val 359 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(bank), val); val 360 arch/x86/kernel/cpu/mce/intel.c val &= ~MCI_CTL2_CMCI_EN; val 361 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCx_CTL2(bank), val); val 447 arch/x86/kernel/cpu/mce/intel.c u64 val; val 452 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCG_EXT_CTL, val); val 454 arch/x86/kernel/cpu/mce/intel.c if (!(val & MCG_EXT_CTL_LMCE_EN)) val 455 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); val 460 arch/x86/kernel/cpu/mce/intel.c u64 val; val 465 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCG_EXT_CTL, val); val 466 arch/x86/kernel/cpu/mce/intel.c val &= ~MCG_EXT_CTL_LMCE_EN; val 467 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCG_EXT_CTL, val); val 472 arch/x86/kernel/cpu/mce/intel.c unsigned long long val; val 488 arch/x86/kernel/cpu/mce/intel.c if (rdmsrl_safe(MSR_PPIN_CTL, &val)) val 491 arch/x86/kernel/cpu/mce/intel.c if ((val & 3UL) == 1UL) { val 497 arch/x86/kernel/cpu/mce/intel.c if (!(val & 2UL)) { val 498 arch/x86/kernel/cpu/mce/intel.c wrmsrl_safe(MSR_PPIN_CTL, val | 2UL); val 499 arch/x86/kernel/cpu/mce/intel.c rdmsrl_safe(MSR_PPIN_CTL, &val); val 503 arch/x86/kernel/cpu/mce/intel.c if (val & 2UL) val 619 arch/x86/kernel/cpu/microcode/core.c unsigned long val; val 622 arch/x86/kernel/cpu/microcode/core.c ret = kstrtoul(buf, 0, &val); val 626 arch/x86/kernel/cpu/microcode/core.c if (val != 1) val 390 arch/x86/kernel/cpu/microcode/intel.c unsigned int val[2]; val 407 arch/x86/kernel/cpu/microcode/intel.c native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); val 408 arch/x86/kernel/cpu/microcode/intel.c csig.pf = 1 << ((val[1] >> 18) & 7); val 766 arch/x86/kernel/cpu/microcode/intel.c unsigned int val[2]; val 774 arch/x86/kernel/cpu/microcode/intel.c rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); val 775 arch/x86/kernel/cpu/microcode/intel.c csig->pf = 1 << ((val[1] >> 18) & 7); val 179 arch/x86/kernel/cpu/mshyperv.c static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) val 133 arch/x86/kernel/cpu/resctrl/ctrlmondata.c unsigned long first_bit, zero_bit, val; val 137 arch/x86/kernel/cpu/resctrl/ctrlmondata.c ret = kstrtoul(buf, 16, &val); val 143 arch/x86/kernel/cpu/resctrl/ctrlmondata.c if (val == 0 || val > r->default_ctrl) { val 148 arch/x86/kernel/cpu/resctrl/ctrlmondata.c first_bit = find_first_bit(&val, cbm_len); val 149 arch/x86/kernel/cpu/resctrl/ctrlmondata.c zero_bit = find_next_zero_bit(&val, cbm_len, first_bit); val 151 arch/x86/kernel/cpu/resctrl/ctrlmondata.c if (find_next_bit(&val, cbm_len, zero_bit) < cbm_len) { val 152 arch/x86/kernel/cpu/resctrl/ctrlmondata.c rdt_last_cmd_printf("The mask %lx has non-consecutive 1-bits\n", val); val 162 arch/x86/kernel/cpu/resctrl/ctrlmondata.c *data = val; val 172 arch/x86/kernel/cpu/resctrl/ctrlmondata.c unsigned long val; val 175 arch/x86/kernel/cpu/resctrl/ctrlmondata.c ret = kstrtoul(buf, 16, &val); val 181 arch/x86/kernel/cpu/resctrl/ctrlmondata.c if (val > r->default_ctrl) { val 186 arch/x86/kernel/cpu/resctrl/ctrlmondata.c *data = val; val 507 arch/x86/kernel/cpu/resctrl/ctrlmondata.c rr->val = 0; val 544 arch/x86/kernel/cpu/resctrl/ctrlmondata.c if (rr.val & RMID_VAL_ERROR) val 546 arch/x86/kernel/cpu/resctrl/ctrlmondata.c else if (rr.val & RMID_VAL_UNAVAIL) val 549 arch/x86/kernel/cpu/resctrl/ctrlmondata.c seq_printf(m, "%llu\n", rr.val * r->mon_scale); val 93 arch/x86/kernel/cpu/resctrl/internal.h u64 val; val 79 arch/x86/kernel/cpu/resctrl/monitor.c u64 val; val 90 arch/x86/kernel/cpu/resctrl/monitor.c rdmsrl(MSR_IA32_QM_CTR, val); val 92 arch/x86/kernel/cpu/resctrl/monitor.c return val; val 97 arch/x86/kernel/cpu/resctrl/monitor.c u64 val = __rmid_read(entry->rmid, QOS_L3_OCCUP_EVENT_ID); val 99 arch/x86/kernel/cpu/resctrl/monitor.c return val >= resctrl_cqm_threshold; val 170 arch/x86/kernel/cpu/resctrl/monitor.c u64 val; val 178 arch/x86/kernel/cpu/resctrl/monitor.c val = __rmid_read(entry->rmid, QOS_L3_OCCUP_EVENT_ID); val 179 arch/x86/kernel/cpu/resctrl/monitor.c if (val <= resctrl_cqm_threshold) val 232 arch/x86/kernel/cpu/resctrl/monitor.c rr->val = tval; val 237 arch/x86/kernel/cpu/resctrl/monitor.c rr->val += tval; val 263 arch/x86/kernel/cpu/resctrl/monitor.c rr->val += m->chunks; val 2513 arch/x86/kernel/cpu/resctrl/rdtgroup.c unsigned long val = _val; val 2515 arch/x86/kernel/cpu/resctrl/rdtgroup.c if (!val) val 2518 arch/x86/kernel/cpu/resctrl/rdtgroup.c first_bit = find_first_bit(&val, cbm_len); val 2519 arch/x86/kernel/cpu/resctrl/rdtgroup.c zero_bit = find_next_zero_bit(&val, cbm_len, first_bit); val 2522 arch/x86/kernel/cpu/resctrl/rdtgroup.c bitmap_clear(&val, zero_bit, cbm_len - zero_bit); val 2523 arch/x86/kernel/cpu/resctrl/rdtgroup.c return (u32)val; val 617 arch/x86/kernel/early-quirks.c #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg) val 329 arch/x86/kernel/ftrace.c static int ftrace_write(unsigned long ip, const char *val, int size) val 333 arch/x86/kernel/ftrace.c if (probe_kernel_write((void *)ip, val, size)) val 86 arch/x86/kernel/head32.c #define SET_PL2(pl2, val) { (pl2).pmd = (val); } val 89 arch/x86/kernel/head32.c #define SET_PL2(pl2, val) { (pl2).pgd = (val); } val 526 arch/x86/kernel/hw_breakpoint.c struct notifier_block *unused, unsigned long val, void *data) val 528 arch/x86/kernel/hw_breakpoint.c if (val != DIE_DEBUG) val 196 arch/x86/kernel/kgdb.c int val; val 218 arch/x86/kernel/kgdb.c val = arch_install_hw_breakpoint(bp); val 219 arch/x86/kernel/kgdb.c if (!val) val 75 arch/x86/kernel/kprobes/opt.c static void synthesize_set_arg1(kprobe_opcode_t *addr, unsigned long val) val 83 arch/x86/kernel/kprobes/opt.c *(unsigned long *)addr = val; val 295 arch/x86/kernel/kvm.c static notrace void kvm_guest_apic_eoi_write(u32 reg, u32 val) val 770 arch/x86/kernel/kvm.c static void kvm_wait(u8 *ptr, u8 val) val 779 arch/x86/kernel/kvm.c if (READ_ONCE(*ptr) != val) val 60 arch/x86/kernel/mmconf-fam10h_64.c u64 val; val 99 arch/x86/kernel/mmconf-fam10h_64.c rdmsrl(address, val); val 102 arch/x86/kernel/mmconf-fam10h_64.c if (!(val & (1<<21))) { val 107 arch/x86/kernel/mmconf-fam10h_64.c rdmsrl(address, val); val 108 arch/x86/kernel/mmconf-fam10h_64.c tom2 = max(val & 0xffffff800000ULL, 1ULL << 32); val 160 arch/x86/kernel/mmconf-fam10h_64.c val = range[i].start & MMCONF_MASK; val 161 arch/x86/kernel/mmconf-fam10h_64.c if (val >= base + MMCONF_SIZE && BASE_VALID(base)) val 172 arch/x86/kernel/mmconf-fam10h_64.c u64 val; val 179 arch/x86/kernel/mmconf-fam10h_64.c rdmsrl(address, val); val 182 arch/x86/kernel/mmconf-fam10h_64.c if (val & FAM10H_MMIO_CONF_ENABLE) { val 184 arch/x86/kernel/mmconf-fam10h_64.c busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & val 189 arch/x86/kernel/mmconf-fam10h_64.c u64 base = val & MMCONF_MASK; val 210 arch/x86/kernel/mmconf-fam10h_64.c val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) | val 212 arch/x86/kernel/mmconf-fam10h_64.c val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) | val 214 arch/x86/kernel/mmconf-fam10h_64.c wrmsrl(address, val); val 139 arch/x86/kernel/module.c u64 val; val 157 arch/x86/kernel/module.c val = sym->st_value + rel[i].r_addend; val 165 arch/x86/kernel/module.c *(u64 *)loc = val; val 170 arch/x86/kernel/module.c *(u32 *)loc = val; val 171 arch/x86/kernel/module.c if (val != *(u32 *)loc) val 177 arch/x86/kernel/module.c *(s32 *)loc = val; val 178 arch/x86/kernel/module.c if ((s64)val != *(s32 *)loc) val 185 arch/x86/kernel/module.c val -= (u64)loc; val 186 arch/x86/kernel/module.c *(u32 *)loc = val; val 188 arch/x86/kernel/module.c if ((s64)val != *(s32 *)loc) val 195 arch/x86/kernel/module.c val -= (u64)loc; val 196 arch/x86/kernel/module.c *(u64 *)loc = val; val 208 arch/x86/kernel/module.c (int)ELF64_R_TYPE(rel[i].r_info), loc, val); val 213 arch/x86/kernel/module.c (int)ELF64_R_TYPE(rel[i].r_info), val); val 37 arch/x86/kernel/nmi_selftest.c static int __init nmi_unk_cb(unsigned int val, struct pt_regs *regs) val 55 arch/x86/kernel/nmi_selftest.c static int __init test_nmi_ipi_callback(unsigned int val, struct pt_regs *regs) val 529 arch/x86/kernel/pci-calgary_64.c u64 val; val 542 arch/x86/kernel/pci-calgary_64.c val = readl(target); val 547 arch/x86/kernel/pci-calgary_64.c val = readq(target); val 549 arch/x86/kernel/pci-calgary_64.c } while ((val & 0xff) != 0xff && i < 100); val 568 arch/x86/kernel/pci-calgary_64.c u32 val; val 579 arch/x86/kernel/pci-calgary_64.c val = be32_to_cpu(readl(target)); val 580 arch/x86/kernel/pci-calgary_64.c printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); val 581 arch/x86/kernel/pci-calgary_64.c val |= PMR_SOFTSTOP; val 582 arch/x86/kernel/pci-calgary_64.c printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); val 583 arch/x86/kernel/pci-calgary_64.c writel(cpu_to_be32(val), target); val 597 arch/x86/kernel/pci-calgary_64.c val = be32_to_cpu(readl(target)); val 598 arch/x86/kernel/pci-calgary_64.c printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); val 601 arch/x86/kernel/pci-calgary_64.c if (val & PMR_SOFTSTOPFAULT) { val 613 arch/x86/kernel/pci-calgary_64.c val = be32_to_cpu(readl(target)); val 614 arch/x86/kernel/pci-calgary_64.c printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); val 616 arch/x86/kernel/pci-calgary_64.c val = be32_to_cpu(readl(target)); val 617 arch/x86/kernel/pci-calgary_64.c printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); val 627 arch/x86/kernel/pci-calgary_64.c val = be32_to_cpu(readl(target)); val 628 arch/x86/kernel/pci-calgary_64.c printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); val 633 arch/x86/kernel/pci-calgary_64.c val = 0; val 634 arch/x86/kernel/pci-calgary_64.c printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); val 635 arch/x86/kernel/pci-calgary_64.c writel(cpu_to_be32(val), target); val 636 arch/x86/kernel/pci-calgary_64.c val = be32_to_cpu(readl(target)); val 637 arch/x86/kernel/pci-calgary_64.c printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); val 941 arch/x86/kernel/pci-calgary_64.c u32 val; val 947 arch/x86/kernel/pci-calgary_64.c val = cpu_to_be32(readl(target)); val 948 arch/x86/kernel/pci-calgary_64.c val |= 0x00800000; val 949 arch/x86/kernel/pci-calgary_64.c writel(cpu_to_be32(val), target); val 1071 arch/x86/kernel/pci-calgary_64.c u32 val; val 1089 arch/x86/kernel/pci-calgary_64.c val = be32_to_cpu(readl(target)); val 1091 arch/x86/kernel/pci-calgary_64.c start_bus = (u8)((val & 0x00FF0000) >> 16); val 1092 arch/x86/kernel/pci-calgary_64.c end_bus = (u8)((val & 0x0000FF00) >> 8); val 1263 arch/x86/kernel/pci-calgary_64.c u32 val; val 1274 arch/x86/kernel/pci-calgary_64.c val = read_pci_config(bus, dev, 0, 0); val 1275 arch/x86/kernel/pci-calgary_64.c if (val != 0xffffffff) val 1278 arch/x86/kernel/pci-calgary_64.c return (val != 0xffffffff); val 1312 arch/x86/kernel/pci-calgary_64.c u32 val; val 1314 arch/x86/kernel/pci-calgary_64.c val = read_pci_config(bus, 0, 0, 0); val 1315 arch/x86/kernel/pci-calgary_64.c pci_device = (val & 0xFFFF0000) >> 16; val 1413 arch/x86/kernel/pci-calgary_64.c u32 val; val 1415 arch/x86/kernel/pci-calgary_64.c val = read_pci_config(bus, 0, 0, 0); val 1416 arch/x86/kernel/pci-calgary_64.c pci_device = (val & 0xFFFF0000) >> 16; val 1467 arch/x86/kernel/pci-calgary_64.c unsigned long val; val 1500 arch/x86/kernel/pci-calgary_64.c ret = kstrtoul(p, 0, &val); val 1504 arch/x86/kernel/pci-calgary_64.c bridge = val; val 171 arch/x86/kernel/process.c unsigned int val; val 174 arch/x86/kernel/process.c val = PR_TSC_SIGSEGV; val 176 arch/x86/kernel/process.c val = PR_TSC_ENABLE; val 178 arch/x86/kernel/process.c return put_user(val, (unsigned int __user *)adr); val 181 arch/x86/kernel/process.c int set_tsc_mode(unsigned int val) val 183 arch/x86/kernel/process.c if (val == PR_TSC_SIGSEGV) val 185 arch/x86/kernel/process.c else if (val == PR_TSC_ENABLE) val 618 arch/x86/kernel/ptrace.c unsigned long val = 0; val 625 arch/x86/kernel/ptrace.c val = bp->hw.info.address; val 627 arch/x86/kernel/ptrace.c val = thread->debugreg6; val 629 arch/x86/kernel/ptrace.c val = thread->ptrace_dr7; val 631 arch/x86/kernel/ptrace.c return val; val 674 arch/x86/kernel/ptrace.c unsigned long val) val 681 arch/x86/kernel/ptrace.c rc = ptrace_set_breakpoint_addr(tsk, n, val); val 683 arch/x86/kernel/ptrace.c thread->debugreg6 = val; val 686 arch/x86/kernel/ptrace.c rc = ptrace_write_dr7(tsk, val); val 688 arch/x86/kernel/ptrace.c thread->ptrace_dr7 = val; val 930 arch/x86/kernel/ptrace.c *val = regs->q; break val 934 arch/x86/kernel/ptrace.c *val = get_segment_reg(child, \ val 938 arch/x86/kernel/ptrace.c static int getreg32(struct task_struct *child, unsigned regno, u32 *val) val 963 arch/x86/kernel/ptrace.c *val = get_flags(child); val 969 arch/x86/kernel/ptrace.c *val = ptrace_get_debugreg(child, regno / 4); val 980 arch/x86/kernel/ptrace.c *val = 0; val 1051 arch/x86/kernel/ptrace.c __u32 val; val 1055 arch/x86/kernel/ptrace.c ret = getreg32(child, addr, &val); val 1057 arch/x86/kernel/ptrace.c ret = put_user(val, (__u32 __user *)datap); val 74 arch/x86/kernel/quirks.c u32 val; val 82 arch/x86/kernel/quirks.c val = readl(rcba_base + 0x3404); val 83 arch/x86/kernel/quirks.c if (!(val & 0x80)) { val 85 arch/x86/kernel/quirks.c writel(val | 0x80, rcba_base + 0x3404); val 88 arch/x86/kernel/quirks.c val = readl(rcba_base + 0x3404); val 89 arch/x86/kernel/quirks.c if (!(val & 0x80)) val 97 arch/x86/kernel/quirks.c u32 val; val 121 arch/x86/kernel/quirks.c val = readl(rcba_base + 0x3404); val 123 arch/x86/kernel/quirks.c if (val & 0x80) { val 125 arch/x86/kernel/quirks.c val = val & 0x3; val 126 arch/x86/kernel/quirks.c force_hpet_address = 0xFED00000 | (val << 12); val 134 arch/x86/kernel/quirks.c writel(val | 0x80, rcba_base + 0x3404); val 136 arch/x86/kernel/quirks.c val = readl(rcba_base + 0x3404); val 137 arch/x86/kernel/quirks.c if (!(val & 0x80)) { val 140 arch/x86/kernel/quirks.c val = val & 0x3; val 141 arch/x86/kernel/quirks.c force_hpet_address = 0xFED00000 | (val << 12); val 187 arch/x86/kernel/quirks.c u32 val; val 199 arch/x86/kernel/quirks.c val = gen_cntl >> 15; val 200 arch/x86/kernel/quirks.c val &= 0x7; val 201 arch/x86/kernel/quirks.c if (val == 0x4) val 209 arch/x86/kernel/quirks.c u32 val; val 220 arch/x86/kernel/quirks.c val = gen_cntl >> 15; val 221 arch/x86/kernel/quirks.c val &= 0x7; val 222 arch/x86/kernel/quirks.c if (val & 0x4) { val 223 arch/x86/kernel/quirks.c val &= 0x3; val 224 arch/x86/kernel/quirks.c force_hpet_address = 0xFED00000 | (val << 12); val 240 arch/x86/kernel/quirks.c val = gen_cntl >> 15; val 241 arch/x86/kernel/quirks.c val &= 0x7; val 242 arch/x86/kernel/quirks.c if (val & 0x4) { val 244 arch/x86/kernel/quirks.c val &= 0x3; val 245 arch/x86/kernel/quirks.c force_hpet_address = 0xFED00000 | (val << 12); val 284 arch/x86/kernel/quirks.c u32 val; val 289 arch/x86/kernel/quirks.c val = 0xfed00000 | 0x80; val 290 arch/x86/kernel/quirks.c pci_write_config_dword(cached_dev, 0x68, val); val 292 arch/x86/kernel/quirks.c pci_read_config_dword(cached_dev, 0x68, &val); val 293 arch/x86/kernel/quirks.c if (val & 0x80) val 301 arch/x86/kernel/quirks.c u32 uninitialized_var(val); val 311 arch/x86/kernel/quirks.c pci_read_config_dword(dev, 0x68, &val); val 316 arch/x86/kernel/quirks.c if (val & 0x80) { val 317 arch/x86/kernel/quirks.c force_hpet_address = (val & ~0x3ff); val 327 arch/x86/kernel/quirks.c val = 0xfed00000 | 0x80; val 328 arch/x86/kernel/quirks.c pci_write_config_dword(dev, 0x68, val); val 330 arch/x86/kernel/quirks.c pci_read_config_dword(dev, 0x68, &val); val 331 arch/x86/kernel/quirks.c if (val & 0x80) { val 332 arch/x86/kernel/quirks.c force_hpet_address = (val & ~0x3ff); val 379 arch/x86/kernel/quirks.c u32 d, val; val 396 arch/x86/kernel/quirks.c pci_read_config_dword(dev, 0x14, &val); val 412 arch/x86/kernel/quirks.c force_hpet_address = val; val 432 arch/x86/kernel/quirks.c u32 uninitialized_var(val); val 443 arch/x86/kernel/quirks.c pci_read_config_dword(dev, 0x44, &val); val 444 arch/x86/kernel/quirks.c force_hpet_address = val & 0xfffffffe; val 541 arch/x86/kernel/quirks.c u32 val; val 548 arch/x86/kernel/quirks.c pci_read_config_dword(nb_ht, 0x60, &val); val 549 arch/x86/kernel/quirks.c node = pcibus_to_node(dev->bus) | (val & 7); val 605 arch/x86/kernel/quirks.c u32 val; val 611 arch/x86/kernel/quirks.c pci_read_config_dword(dev, 0x58, &val); val 612 arch/x86/kernel/quirks.c if (val & 0x1F) { val 613 arch/x86/kernel/quirks.c val &= ~(0x1F); val 614 arch/x86/kernel/quirks.c pci_write_config_dword(dev, 0x58, val); val 617 arch/x86/kernel/quirks.c pci_read_config_dword(dev, 0x5C, &val); val 618 arch/x86/kernel/quirks.c if (val & BIT(0)) { val 619 arch/x86/kernel/quirks.c val &= ~BIT(0); val 620 arch/x86/kernel/quirks.c pci_write_config_dword(dev, 0x5c, val); val 813 arch/x86/kernel/reboot.c static int crash_nmi_callback(unsigned int val, struct pt_regs *regs) val 128 arch/x86/kernel/rtc.c unsigned char val; val 132 arch/x86/kernel/rtc.c val = inb(RTC_PORT(1)); val 135 arch/x86/kernel/rtc.c return val; val 139 arch/x86/kernel/rtc.c void rtc_cmos_write(unsigned char val, unsigned char addr) val 143 arch/x86/kernel/rtc.c outb(val, RTC_PORT(1)); val 291 arch/x86/kernel/signal.c u32 val; val 301 arch/x86/kernel/signal.c u32 val; val 118 arch/x86/kernel/smp.c static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) val 482 arch/x86/kernel/tsc.c static inline int pit_verify_msb(unsigned char val) val 486 arch/x86/kernel/tsc.c return inb(0x42) == val; val 489 arch/x86/kernel/tsc.c static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) val 495 arch/x86/kernel/tsc.c if (!pit_verify_msb(val)) val 975 arch/x86/kernel/tsc.c static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, val 991 arch/x86/kernel/tsc.c if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || val 992 arch/x86/kernel/tsc.c (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { val 347 arch/x86/kernel/unwind_orc.c unsigned long *val) val 352 arch/x86/kernel/unwind_orc.c *val = READ_ONCE_NOCHECK(*(unsigned long *)addr); val 394 arch/x86/kernel/unwind_orc.c unsigned long *val) val 402 arch/x86/kernel/unwind_orc.c *val = ((unsigned long *)state->regs)[reg]; val 407 arch/x86/kernel/unwind_orc.c *val = ((unsigned long *)state->prev_regs)[reg]; val 525 arch/x86/kernel/uprobes.c static int emulate_push_stack(struct pt_regs *regs, unsigned long val) val 529 arch/x86/kernel/uprobes.c if (copy_to_user((void __user *)new_sp, &val, sizeof_long(regs))) val 997 arch/x86/kernel/uprobes.c int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data) val 1007 arch/x86/kernel/uprobes.c switch (val) { val 455 arch/x86/kernel/vm86_32.c #define val_byte(val, n) (((__u8 *)&val)[n]) val 457 arch/x86/kernel/vm86_32.c #define pushb(base, ptr, val, err_label) \ val 459 arch/x86/kernel/vm86_32.c __u8 __val = val; \ val 465 arch/x86/kernel/vm86_32.c #define pushw(base, ptr, val, err_label) \ val 467 arch/x86/kernel/vm86_32.c __u16 __val = val; \ val 476 arch/x86/kernel/vm86_32.c #define pushl(base, ptr, val, err_label) \ val 478 arch/x86/kernel/vm86_32.c __u32 __val = val; \ val 11 arch/x86/kvm/debugfs.c static int vcpu_get_timer_advance_ns(void *data, u64 *val) val 14 arch/x86/kvm/debugfs.c *val = vcpu->arch.apic->lapic_timer.timer_advance_ns; val 20 arch/x86/kvm/debugfs.c static int vcpu_get_tsc_offset(void *data, u64 *val) val 23 arch/x86/kvm/debugfs.c *val = vcpu->arch.tsc_offset; val 29 arch/x86/kvm/debugfs.c static int vcpu_get_tsc_scaling_ratio(void *data, u64 *val) val 32 arch/x86/kvm/debugfs.c *val = vcpu->arch.tsc_scaling_ratio; val 38 arch/x86/kvm/debugfs.c static int vcpu_get_tsc_scaling_frac_bits(void *data, u64 *val) val 40 arch/x86/kvm/debugfs.c *val = kvm_tsc_scaling_ratio_frac_bits; val 520 arch/x86/kvm/emulate.c static void assign_register(unsigned long *reg, u64 val, int bytes) val 525 arch/x86/kvm/emulate.c *(u8 *)reg = (u8)val; val 528 arch/x86/kvm/emulate.c *(u16 *)reg = (u16)val; val 531 arch/x86/kvm/emulate.c *reg = (u32)val; val 534 arch/x86/kvm/emulate.c *reg = val; val 1037 arch/x86/kvm/emulate.c if (ctxt->src.val == 0) val 1045 arch/x86/kvm/emulate.c if (ctxt->src.val == 0) val 1065 arch/x86/kvm/emulate.c op->val = *(u8 *)op->addr.reg; val 1068 arch/x86/kvm/emulate.c op->val = *(u16 *)op->addr.reg; val 1071 arch/x86/kvm/emulate.c op->val = *(u32 *)op->addr.reg; val 1074 arch/x86/kvm/emulate.c op->val = *(u64 *)op->addr.reg; val 1204 arch/x86/kvm/emulate.c ctxt->dst.val = fcw; val 1220 arch/x86/kvm/emulate.c ctxt->dst.val = fsw; val 1253 arch/x86/kvm/emulate.c op->orig_val = op->val; val 1428 arch/x86/kvm/emulate.c sv = (s16)ctxt->src.val & (s16)mask; val 1430 arch/x86/kvm/emulate.c sv = (s32)ctxt->src.val & (s32)mask; val 1432 arch/x86/kvm/emulate.c sv = (s64)ctxt->src.val & (s64)mask; val 1439 arch/x86/kvm/emulate.c ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; val 1836 arch/x86/kvm/emulate.c return assign_register(op->addr.reg, op->val, op->bytes); val 1850 arch/x86/kvm/emulate.c &op->val, val 1855 arch/x86/kvm/emulate.c &op->val, val 1894 arch/x86/kvm/emulate.c return push(ctxt, &ctxt->src.val, ctxt->op_bytes); val 1915 arch/x86/kvm/emulate.c return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); val 1922 arch/x86/kvm/emulate.c unsigned long val, change_mask; val 1926 arch/x86/kvm/emulate.c rc = emulate_pop(ctxt, &val, len); val 1955 arch/x86/kvm/emulate.c (ctxt->eflags & ~change_mask) | (val & change_mask); val 1965 arch/x86/kvm/emulate.c return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); val 1971 arch/x86/kvm/emulate.c unsigned frame_size = ctxt->src.val; val 1972 arch/x86/kvm/emulate.c unsigned nesting_level = ctxt->src2.val & 31; val 1999 arch/x86/kvm/emulate.c int seg = ctxt->src2.val; val 2001 arch/x86/kvm/emulate.c ctxt->src.val = get_segment_selector(ctxt, seg); val 2012 arch/x86/kvm/emulate.c int seg = ctxt->src2.val; val 2037 arch/x86/kvm/emulate.c (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); val 2051 arch/x86/kvm/emulate.c ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; val 2059 arch/x86/kvm/emulate.c u32 val; val 2067 arch/x86/kvm/emulate.c rc = emulate_pop(ctxt, &val, ctxt->op_bytes); val 2070 arch/x86/kvm/emulate.c assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); val 2086 arch/x86/kvm/emulate.c ctxt->src.val = ctxt->eflags; val 2093 arch/x86/kvm/emulate.c ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); val 2098 arch/x86/kvm/emulate.c ctxt->src.val = ctxt->_eip; val 2237 arch/x86/kvm/emulate.c rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); val 2247 arch/x86/kvm/emulate.c return assign_eip_near(ctxt, ctxt->src.val); val 2256 arch/x86/kvm/emulate.c rc = assign_eip_near(ctxt, ctxt->src.val); val 2259 arch/x86/kvm/emulate.c ctxt->src.val = old_eip; val 2333 arch/x86/kvm/emulate.c rsp_increment(ctxt, ctxt->src.val); val 2340 arch/x86/kvm/emulate.c ctxt->dst.orig_val = ctxt->dst.val; val 2341 arch/x86/kvm/emulate.c ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); val 2342 arch/x86/kvm/emulate.c ctxt->src.orig_val = ctxt->src.val; val 2343 arch/x86/kvm/emulate.c ctxt->src.val = ctxt->dst.orig_val; val 2349 arch/x86/kvm/emulate.c ctxt->dst.val = ctxt->src.orig_val; val 2354 arch/x86/kvm/emulate.c ctxt->src.val = ctxt->dst.orig_val; val 2356 arch/x86/kvm/emulate.c ctxt->dst.val = ctxt->dst.orig_val; val 2363 arch/x86/kvm/emulate.c int seg = ctxt->src2.val; val 2373 arch/x86/kvm/emulate.c ctxt->dst.val = ctxt->src.val; val 2497 arch/x86/kvm/emulate.c u32 val, cr0, cr3, cr4; val 2508 arch/x86/kvm/emulate.c val = GET_SMSTATE(u32, smstate, 0x7fcc); val 2509 arch/x86/kvm/emulate.c ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); val 2510 arch/x86/kvm/emulate.c val = GET_SMSTATE(u32, smstate, 0x7fc8); val 2511 arch/x86/kvm/emulate.c ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); val 2552 arch/x86/kvm/emulate.c u64 val, cr0, cr3, cr4; val 2563 arch/x86/kvm/emulate.c val = GET_SMSTATE(u32, smstate, 0x7f68); val 2564 arch/x86/kvm/emulate.c ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); val 2565 arch/x86/kvm/emulate.c val = GET_SMSTATE(u32, smstate, 0x7f60); val 2566 arch/x86/kvm/emulate.c ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); val 2572 arch/x86/kvm/emulate.c val = GET_SMSTATE(u64, smstate, 0x7ed0); val 2573 arch/x86/kvm/emulate.c ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA); val 3398 arch/x86/kvm/emulate.c ctxt->src.val = (unsigned long) error_code; val 3444 arch/x86/kvm/emulate.c al = ctxt->dst.val; val 3462 arch/x86/kvm/emulate.c ctxt->dst.val = al; val 3465 arch/x86/kvm/emulate.c ctxt->src.val = 0; val 3480 arch/x86/kvm/emulate.c if (ctxt->src.val == 0) val 3483 arch/x86/kvm/emulate.c al = ctxt->dst.val & 0xff; val 3484 arch/x86/kvm/emulate.c ah = al / ctxt->src.val; val 3485 arch/x86/kvm/emulate.c al %= ctxt->src.val; val 3487 arch/x86/kvm/emulate.c ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); val 3491 arch/x86/kvm/emulate.c ctxt->src.val = 0; val 3500 arch/x86/kvm/emulate.c u8 al = ctxt->dst.val & 0xff; val 3501 arch/x86/kvm/emulate.c u8 ah = (ctxt->dst.val >> 8) & 0xff; val 3503 arch/x86/kvm/emulate.c al = (al + (ah * ctxt->src.val)) & 0xff; val 3505 arch/x86/kvm/emulate.c ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; val 3509 arch/x86/kvm/emulate.c ctxt->src.val = 0; val 3519 arch/x86/kvm/emulate.c long rel = ctxt->src.val; val 3521 arch/x86/kvm/emulate.c ctxt->src.val = (unsigned long)ctxt->_eip; val 3547 arch/x86/kvm/emulate.c rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); val 3551 arch/x86/kvm/emulate.c ctxt->src.val = old_cs; val 3556 arch/x86/kvm/emulate.c ctxt->src.val = old_eip; val 3583 arch/x86/kvm/emulate.c rsp_increment(ctxt, ctxt->src.val); val 3590 arch/x86/kvm/emulate.c ctxt->src.val = ctxt->dst.val; val 3594 arch/x86/kvm/emulate.c ctxt->dst.val = ctxt->src.orig_val; val 3601 arch/x86/kvm/emulate.c ctxt->dst.val = ctxt->src2.val; val 3610 arch/x86/kvm/emulate.c ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); val 3621 arch/x86/kvm/emulate.c ctxt->dst.val = tsc_aux; val 3676 arch/x86/kvm/emulate.c tmp = (u16)ctxt->src.val; val 3677 arch/x86/kvm/emulate.c ctxt->dst.val &= ~0xffffUL; val 3678 arch/x86/kvm/emulate.c ctxt->dst.val |= (unsigned long)swab16(tmp); val 3681 arch/x86/kvm/emulate.c ctxt->dst.val = swab32((u32)ctxt->src.val); val 3684 arch/x86/kvm/emulate.c ctxt->dst.val = swab64(ctxt->src.val); val 3694 arch/x86/kvm/emulate.c if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) val 3704 arch/x86/kvm/emulate.c unsigned long val; val 3707 arch/x86/kvm/emulate.c val = ctxt->src.val & ~0ULL; val 3709 arch/x86/kvm/emulate.c val = ctxt->src.val & ~0U; val 3712 arch/x86/kvm/emulate.c if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) val 3751 arch/x86/kvm/emulate.c ctxt->dst.val = get_segment_selector(ctxt, segment); val 3767 arch/x86/kvm/emulate.c u16 sel = ctxt->src.val; val 3787 arch/x86/kvm/emulate.c u16 sel = ctxt->src.val; val 3801 arch/x86/kvm/emulate.c u16 sel = ctxt->src.val; val 3920 arch/x86/kvm/emulate.c ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); val 3927 arch/x86/kvm/emulate.c | (ctxt->src.val & 0x0f)); val 3939 arch/x86/kvm/emulate.c rc = jmp_rel(ctxt, ctxt->src.val); val 3949 arch/x86/kvm/emulate.c rc = jmp_rel(ctxt, ctxt->src.val); val 3956 arch/x86/kvm/emulate.c if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, val 3957 arch/x86/kvm/emulate.c &ctxt->dst.val)) val 3965 arch/x86/kvm/emulate.c ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, val 3966 arch/x86/kvm/emulate.c &ctxt->src.val, 1); val 4037 arch/x86/kvm/emulate.c asm("bswap %0" : "+r"(ctxt->dst.val)); val 4041 arch/x86/kvm/emulate.c asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); val 4055 arch/x86/kvm/emulate.c ctxt->dst.val = (s32) ctxt->src.val; val 4405 arch/x86/kvm/emulate.c if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) val 4414 arch/x86/kvm/emulate.c if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) val 4988 arch/x86/kvm/emulate.c op->val = insn_fetch(s8, ctxt); val 4991 arch/x86/kvm/emulate.c op->val = insn_fetch(s16, ctxt); val 4994 arch/x86/kvm/emulate.c op->val = insn_fetch(s32, ctxt); val 4997 arch/x86/kvm/emulate.c op->val = insn_fetch(s64, ctxt); val 5003 arch/x86/kvm/emulate.c op->val &= 0xff; val 5006 arch/x86/kvm/emulate.c op->val &= 0xffff; val 5009 arch/x86/kvm/emulate.c op->val &= 0xffffffff; val 5036 arch/x86/kvm/emulate.c op->orig_val = op->val; val 5046 arch/x86/kvm/emulate.c op->orig_val = op->val; val 5053 arch/x86/kvm/emulate.c op->orig_val = op->val; val 5064 arch/x86/kvm/emulate.c op->orig_val = op->val; val 5072 arch/x86/kvm/emulate.c op->val = 0; val 5084 arch/x86/kvm/emulate.c op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; val 5092 arch/x86/kvm/emulate.c op->val = 1; val 5126 arch/x86/kvm/emulate.c op->val = 0; val 5137 arch/x86/kvm/emulate.c op->val = 0; val 5150 arch/x86/kvm/emulate.c op->val = VCPU_SREG_ES; val 5154 arch/x86/kvm/emulate.c op->val = VCPU_SREG_CS; val 5158 arch/x86/kvm/emulate.c op->val = VCPU_SREG_SS; val 5162 arch/x86/kvm/emulate.c op->val = VCPU_SREG_DS; val 5166 arch/x86/kvm/emulate.c op->val = VCPU_SREG_FS; val 5170 arch/x86/kvm/emulate.c op->val = VCPU_SREG_GS; val 5533 arch/x86/kvm/emulate.c : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), val 5535 arch/x86/kvm/emulate.c : "c"(ctxt->src2.val)); val 5664 arch/x86/kvm/emulate.c &ctxt->src2.val, ctxt->src2.bytes); val 5676 arch/x86/kvm/emulate.c &ctxt->dst.val, ctxt->dst.bytes); val 5724 arch/x86/kvm/emulate.c rc = jmp_rel(ctxt, ctxt->src.val); val 5727 arch/x86/kvm/emulate.c ctxt->dst.val = ctxt->src.addr.mem.ea; val 5737 arch/x86/kvm/emulate.c case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; val 5738 arch/x86/kvm/emulate.c case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; val 5739 arch/x86/kvm/emulate.c case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; val 5746 arch/x86/kvm/emulate.c rc = emulate_int(ctxt, ctxt->src.val); val 5754 arch/x86/kvm/emulate.c rc = jmp_rel(ctxt, ctxt->src.val); val 5864 arch/x86/kvm/emulate.c ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); val 5867 arch/x86/kvm/emulate.c ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); val 5871 arch/x86/kvm/emulate.c ctxt->dst.val = ctxt->src.val; val 5877 arch/x86/kvm/emulate.c rc = jmp_rel(ctxt, ctxt->src.val); val 5880 arch/x86/kvm/emulate.c ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); val 5884 arch/x86/kvm/emulate.c ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val val 5885 arch/x86/kvm/emulate.c : (u16) ctxt->src.val; val 5889 arch/x86/kvm/emulate.c ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : val 5890 arch/x86/kvm/emulate.c (s16) ctxt->src.val; val 54 arch/x86/kvm/i8254.c static void pit_set_gate(struct kvm_pit *pit, int channel, u32 val) val 69 arch/x86/kvm/i8254.c if (c->gate < val) val 74 arch/x86/kvm/i8254.c c->gate = val; val 311 arch/x86/kvm/i8254.c static void create_pit_timer(struct kvm_pit *pit, u32 val, int is_period) val 321 arch/x86/kvm/i8254.c interval = mul_u64_u32_div(val, NSEC_PER_SEC, KVM_PIT_FREQ); val 354 arch/x86/kvm/i8254.c static void pit_load_count(struct kvm_pit *pit, int channel, u32 val) val 358 arch/x86/kvm/i8254.c pr_debug("load_count val is %d, channel is %d\n", val, channel); val 364 arch/x86/kvm/i8254.c if (val == 0) val 365 arch/x86/kvm/i8254.c val = 0x10000; val 367 arch/x86/kvm/i8254.c ps->channels[channel].count = val; val 381 arch/x86/kvm/i8254.c create_pit_timer(pit, val, 0); val 385 arch/x86/kvm/i8254.c create_pit_timer(pit, val, 1); val 392 arch/x86/kvm/i8254.c void kvm_pit_load_count(struct kvm_pit *pit, int channel, u32 val, val 404 arch/x86/kvm/i8254.c pit_load_count(pit, channel, val); val 407 arch/x86/kvm/i8254.c pit_load_count(pit, channel, val); val 435 arch/x86/kvm/i8254.c u32 val = *(u32 *) data; val 439 arch/x86/kvm/i8254.c val &= 0xff; val 444 arch/x86/kvm/i8254.c if (val != 0) val 446 arch/x86/kvm/i8254.c (unsigned int)addr, len, val); val 449 arch/x86/kvm/i8254.c channel = val >> 6; val 454 arch/x86/kvm/i8254.c if (val & (2 << channel)) { val 455 arch/x86/kvm/i8254.c if (!(val & 0x20)) val 457 arch/x86/kvm/i8254.c if (!(val & 0x10)) val 464 arch/x86/kvm/i8254.c access = (val >> 4) & KVM_PIT_CHANNEL_MASK; val 471 arch/x86/kvm/i8254.c s->mode = (val >> 1) & 7; val 474 arch/x86/kvm/i8254.c s->bcd = val & 1; val 483 arch/x86/kvm/i8254.c pit_load_count(pit, addr, val); val 486 arch/x86/kvm/i8254.c pit_load_count(pit, addr, val << 8); val 489 arch/x86/kvm/i8254.c s->write_latch = val; val 493 arch/x86/kvm/i8254.c pit_load_count(pit, addr, s->write_latch | (val << 8)); val 579 arch/x86/kvm/i8254.c u32 val = *(u32 *) data; val 584 arch/x86/kvm/i8254.c pit_state->speaker_data_on = (val >> 1) & 1; val 585 arch/x86/kvm/i8254.c pit_set_gate(pit, 2, val & 1); val 62 arch/x86/kvm/i8254.h void kvm_pit_load_count(struct kvm_pit *pit, int channel, u32 val, val 305 arch/x86/kvm/i8259.c static void pic_ioport_write(void *opaque, u32 addr, u32 val) val 312 arch/x86/kvm/i8259.c if (val & 0x10) { val 313 arch/x86/kvm/i8259.c s->init4 = val & 1; val 314 arch/x86/kvm/i8259.c if (val & 0x02) val 316 arch/x86/kvm/i8259.c if (val & 0x08) val 320 arch/x86/kvm/i8259.c } else if (val & 0x08) { val 321 arch/x86/kvm/i8259.c if (val & 0x04) val 323 arch/x86/kvm/i8259.c if (val & 0x02) val 324 arch/x86/kvm/i8259.c s->read_reg_select = val & 1; val 325 arch/x86/kvm/i8259.c if (val & 0x40) val 326 arch/x86/kvm/i8259.c s->special_mask = (val >> 5) & 1; val 328 arch/x86/kvm/i8259.c cmd = val >> 5; val 346 arch/x86/kvm/i8259.c irq = val & 7; val 351 arch/x86/kvm/i8259.c s->priority_add = (val + 1) & 7; val 355 arch/x86/kvm/i8259.c irq = val & 7; val 367 arch/x86/kvm/i8259.c u8 imr_diff = s->imr ^ val, val 369 arch/x86/kvm/i8259.c s->imr = val; val 381 arch/x86/kvm/i8259.c s->irq_base = val & 0xf8; val 391 arch/x86/kvm/i8259.c s->special_fully_nested_mode = (val >> 4) & 1; val 392 arch/x86/kvm/i8259.c s->auto_eoi = (val >> 1) & 1; val 439 arch/x86/kvm/i8259.c static void elcr_ioport_write(void *opaque, u32 addr, u32 val) val 442 arch/x86/kvm/i8259.c s->elcr = val & s->elcr_mask; val 452 arch/x86/kvm/i8259.c gpa_t addr, int len, const void *val) val 454 arch/x86/kvm/i8259.c unsigned char data = *(unsigned char *)val; val 486 arch/x86/kvm/i8259.c gpa_t addr, int len, void *val) val 488 arch/x86/kvm/i8259.c unsigned char *data = (unsigned char *)val; val 491 arch/x86/kvm/i8259.c memset(val, 0, len); val 517 arch/x86/kvm/i8259.c gpa_t addr, int len, const void *val) val 520 arch/x86/kvm/i8259.c addr, len, val); val 524 arch/x86/kvm/i8259.c gpa_t addr, int len, void *val) val 527 arch/x86/kvm/i8259.c addr, len, val); val 531 arch/x86/kvm/i8259.c gpa_t addr, int len, const void *val) val 534 arch/x86/kvm/i8259.c addr, len, val); val 538 arch/x86/kvm/i8259.c gpa_t addr, int len, void *val) val 541 arch/x86/kvm/i8259.c addr, len, val); val 545 arch/x86/kvm/i8259.c gpa_t addr, int len, const void *val) val 548 arch/x86/kvm/i8259.c addr, len, val); val 552 arch/x86/kvm/i8259.c gpa_t addr, int len, void *val) val 555 arch/x86/kvm/i8259.c addr, len, val); val 272 arch/x86/kvm/ioapic.c static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) val 285 arch/x86/kvm/ioapic.c ioapic->id = (val >> 24) & 0xf; val 304 arch/x86/kvm/ioapic.c e->bits |= (u64) val << 32; val 307 arch/x86/kvm/ioapic.c e->bits |= (u32) val; val 502 arch/x86/kvm/ioapic.c gpa_t addr, int len, void *val) val 530 arch/x86/kvm/ioapic.c *(u64 *) val = result; val 535 arch/x86/kvm/ioapic.c memcpy(val, (char *)&result, len); val 544 arch/x86/kvm/ioapic.c gpa_t addr, int len, const void *val) val 556 arch/x86/kvm/ioapic.c data = *(u32 *) val; val 559 arch/x86/kvm/ioapic.c data = *(u16 *) val; val 562 arch/x86/kvm/ioapic.c data = *(u8 *) val; val 18 arch/x86/kvm/kvm_cache_regs.h unsigned long val) \ val 20 arch/x86/kvm/kvm_cache_regs.h vcpu->arch.regs[VCPU_REGS_##uname] = val; \ val 51 arch/x86/kvm/kvm_cache_regs.h unsigned long val) val 53 arch/x86/kvm/kvm_cache_regs.h vcpu->arch.regs[reg] = val; val 63 arch/x86/kvm/kvm_cache_regs.h static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val) val 65 arch/x86/kvm/kvm_cache_regs.h kvm_register_write(vcpu, VCPU_REGS_RIP, val); val 73 arch/x86/kvm/kvm_cache_regs.h static inline void kvm_rsp_write(struct kvm_vcpu *vcpu, unsigned long val) val 75 arch/x86/kvm/kvm_cache_regs.h kvm_register_write(vcpu, VCPU_REGS_RSP, val); val 250 arch/x86/kvm/lapic.c static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) val 252 arch/x86/kvm/lapic.c bool enabled = val & APIC_SPIV_APIC_ENABLED; val 254 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_SPIV, val); val 618 arch/x86/kvm/lapic.c static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) val 621 arch/x86/kvm/lapic.c return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, val 622 arch/x86/kvm/lapic.c sizeof(val)); val 625 arch/x86/kvm/lapic.c static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) val 628 arch/x86/kvm/lapic.c return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, val 629 arch/x86/kvm/lapic.c sizeof(*val)); val 639 arch/x86/kvm/lapic.c u8 val; val 640 arch/x86/kvm/lapic.c if (pv_eoi_get_user(vcpu, &val) < 0) { val 645 arch/x86/kvm/lapic.c return val & 0x1; val 1262 arch/x86/kvm/lapic.c u32 val = 0; val 1275 arch/x86/kvm/lapic.c val = apic_get_tmcct(apic); val 1279 arch/x86/kvm/lapic.c val = kvm_lapic_get_reg(apic, offset); val 1285 arch/x86/kvm/lapic.c val = kvm_lapic_get_reg(apic, offset); val 1289 arch/x86/kvm/lapic.c return val; val 1850 arch/x86/kvm/lapic.c int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) val 1854 arch/x86/kvm/lapic.c trace_kvm_apic_write(reg, val); val 1859 arch/x86/kvm/lapic.c kvm_apic_set_xapic_id(apic, val >> 24); val 1866 arch/x86/kvm/lapic.c apic_set_tpr(apic, val & 0xff); val 1875 arch/x86/kvm/lapic.c kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); val 1882 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); val 1892 arch/x86/kvm/lapic.c apic_set_spiv(apic, val & mask); val 1893 arch/x86/kvm/lapic.c if (!(val & APIC_SPIV_APIC_ENABLED)) { val 1911 arch/x86/kvm/lapic.c val &= ~(1 << 12); val 1912 arch/x86/kvm/lapic.c apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); val 1913 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ICR, val); val 1918 arch/x86/kvm/lapic.c val &= 0xff000000; val 1919 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ICR2, val); val 1923 arch/x86/kvm/lapic.c apic_manage_nmi_watchdog(apic, val); val 1934 arch/x86/kvm/lapic.c val |= APIC_LVT_MASKED; val 1938 arch/x86/kvm/lapic.c val &= apic_lvt_mask[index]; val 1939 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, reg, val); val 1945 arch/x86/kvm/lapic.c val |= APIC_LVT_MASKED; val 1946 arch/x86/kvm/lapic.c val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); val 1947 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_LVTT, val); val 1956 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TMICT, val); val 1963 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TDCR, val); val 1974 arch/x86/kvm/lapic.c if (apic_x2apic_mode(apic) && val != 0) val 1980 arch/x86/kvm/lapic.c kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); val 1998 arch/x86/kvm/lapic.c u32 val; val 2019 arch/x86/kvm/lapic.c val = *(u32*)data; val 2021 arch/x86/kvm/lapic.c kvm_lapic_reg_write(apic, offset & 0xff0, val); val 2035 arch/x86/kvm/lapic.c u32 val = 0; val 2040 arch/x86/kvm/lapic.c kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); val 2043 arch/x86/kvm/lapic.c kvm_lapic_reg_write(vcpu->arch.apic, offset, val); val 81 arch/x86/kvm/lapic.h int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); val 157 arch/x86/kvm/lapic.h static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) val 159 arch/x86/kvm/lapic.h *((u32 *) (apic->regs + reg_off)) = val; val 61 arch/x86/kvm/mmu.c static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); val 62 arch/x86/kvm/mmu.c static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); val 1376 arch/x86/kvm/mmu.c if (!rmap_head->val) { val 1378 arch/x86/kvm/mmu.c rmap_head->val = (unsigned long)spte; val 1379 arch/x86/kvm/mmu.c } else if (!(rmap_head->val & 1)) { val 1382 arch/x86/kvm/mmu.c desc->sptes[0] = (u64 *)rmap_head->val; val 1384 arch/x86/kvm/mmu.c rmap_head->val = (unsigned long)desc | 1; val 1388 arch/x86/kvm/mmu.c desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); val 1418 arch/x86/kvm/mmu.c rmap_head->val = (unsigned long)desc->sptes[0]; val 1423 arch/x86/kvm/mmu.c rmap_head->val = (unsigned long)desc->more | 1; val 1433 arch/x86/kvm/mmu.c if (!rmap_head->val) { val 1436 arch/x86/kvm/mmu.c } else if (!(rmap_head->val & 1)) { val 1438 arch/x86/kvm/mmu.c if ((u64 *)rmap_head->val != spte) { val 1442 arch/x86/kvm/mmu.c rmap_head->val = 0; val 1445 arch/x86/kvm/mmu.c desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); val 1542 arch/x86/kvm/mmu.c if (!rmap_head->val) val 1545 arch/x86/kvm/mmu.c if (!(rmap_head->val & 1)) { val 1547 arch/x86/kvm/mmu.c sptep = (u64 *)rmap_head->val; val 1551 arch/x86/kvm/mmu.c iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); val 6271 arch/x86/kvm/mmu.c static void __set_nx_huge_pages(bool val) val 6273 arch/x86/kvm/mmu.c nx_huge_pages = itlb_multihit_kvm_mitigation = val; val 6276 arch/x86/kvm/mmu.c static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) val 6282 arch/x86/kvm/mmu.c if (sysfs_streq(val, "off")) val 6284 arch/x86/kvm/mmu.c else if (sysfs_streq(val, "force")) val 6286 arch/x86/kvm/mmu.c else if (sysfs_streq(val, "auto")) val 6288 arch/x86/kvm/mmu.c else if (strtobool(val, &new_val) < 0) val 6398 arch/x86/kvm/mmu.c static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) val 6404 arch/x86/kvm/mmu.c err = param_set_uint(val, kp); val 151 arch/x86/kvm/mmu_audit.c if (!rmap_head->val) { val 275 arch/x86/kvm/mmu_audit.c static int mmu_audit_set(const char *val, const struct kernel_param *kp) val 280 arch/x86/kvm/mmu_audit.c ret = kstrtoul(val, 10, &enable); val 66 arch/x86/kvm/page_track.c int index, val; val 70 arch/x86/kvm/page_track.c val = slot->arch.gfn_track[mode][index]; val 72 arch/x86/kvm/page_track.c if (WARN_ON(val + count < 0 || val + count > USHRT_MAX)) val 845 arch/x86/kvm/svm.c u64 val; val 851 arch/x86/kvm/svm.c val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); val 855 arch/x86/kvm/svm.c val |= (1ULL << 47); val 857 arch/x86/kvm/svm.c low = lower_32_bits(val); val 858 arch/x86/kvm/svm.c high = upper_32_bits(val); val 3153 arch/x86/kvm/svm.c u16 val, mask; val 3167 arch/x86/kvm/svm.c val = 0; val 3169 arch/x86/kvm/svm.c if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) val 3172 arch/x86/kvm/svm.c return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; val 4004 arch/x86/kvm/svm.c unsigned long val) val 4017 arch/x86/kvm/svm.c val &= ~SVM_CR0_SELECTIVE_MASK; val 4019 arch/x86/kvm/svm.c if (cr0 ^ val) { val 4032 arch/x86/kvm/svm.c unsigned long val; val 4050 arch/x86/kvm/svm.c val = kvm_register_read(&svm->vcpu, reg); val 4053 arch/x86/kvm/svm.c if (!check_selective_cr0_intercepted(svm, val)) val 4054 arch/x86/kvm/svm.c err = kvm_set_cr0(&svm->vcpu, val); val 4060 arch/x86/kvm/svm.c err = kvm_set_cr3(&svm->vcpu, val); val 4063 arch/x86/kvm/svm.c err = kvm_set_cr4(&svm->vcpu, val); val 4066 arch/x86/kvm/svm.c err = kvm_set_cr8(&svm->vcpu, val); val 4076 arch/x86/kvm/svm.c val = kvm_read_cr0(&svm->vcpu); val 4079 arch/x86/kvm/svm.c val = svm->vcpu.arch.cr2; val 4082 arch/x86/kvm/svm.c val = kvm_read_cr3(&svm->vcpu); val 4085 arch/x86/kvm/svm.c val = kvm_read_cr4(&svm->vcpu); val 4088 arch/x86/kvm/svm.c val = kvm_get_cr8(&svm->vcpu); val 4095 arch/x86/kvm/svm.c kvm_register_write(&svm->vcpu, reg, val); val 4103 arch/x86/kvm/svm.c unsigned long val; val 4125 arch/x86/kvm/svm.c val = kvm_register_read(&svm->vcpu, reg); val 4126 arch/x86/kvm/svm.c kvm_set_dr(&svm->vcpu, dr - 16, val); val 4130 arch/x86/kvm/svm.c kvm_get_dr(&svm->vcpu, dr, &val); val 4131 arch/x86/kvm/svm.c kvm_register_write(&svm->vcpu, reg, val); val 6132 arch/x86/kvm/svm.c unsigned long cr0, val; val 6148 arch/x86/kvm/svm.c val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; val 6152 arch/x86/kvm/svm.c val &= 0xfUL; val 6155 arch/x86/kvm/svm.c val |= X86_CR0_PE; val 6158 arch/x86/kvm/svm.c if (cr0 ^ val) val 110 arch/x86/kvm/trace.h __field( unsigned int, val ) val 119 arch/x86/kvm/trace.h __entry->val = *(unsigned char *)data; val 121 arch/x86/kvm/trace.h __entry->val = *(unsigned short *)data; val 123 arch/x86/kvm/trace.h __entry->val = *(unsigned int *)data; val 128 arch/x86/kvm/trace.h __entry->port, __entry->size, __entry->count, __entry->val, val 195 arch/x86/kvm/trace.h TP_PROTO(unsigned int rw, unsigned int reg, unsigned int val), val 196 arch/x86/kvm/trace.h TP_ARGS(rw, reg, val), val 201 arch/x86/kvm/trace.h __field( unsigned int, val ) val 207 arch/x86/kvm/trace.h __entry->val = val; val 213 arch/x86/kvm/trace.h __entry->val) val 216 arch/x86/kvm/trace.h #define trace_kvm_apic_read(reg, val) trace_kvm_apic(0, reg, val) val 217 arch/x86/kvm/trace.h #define trace_kvm_apic_write(reg, val) trace_kvm_apic(1, reg, val) val 362 arch/x86/kvm/trace.h TP_PROTO(unsigned int rw, unsigned int cr, unsigned long val), val 363 arch/x86/kvm/trace.h TP_ARGS(rw, cr, val), val 368 arch/x86/kvm/trace.h __field( unsigned long, val ) val 374 arch/x86/kvm/trace.h __entry->val = val; val 379 arch/x86/kvm/trace.h __entry->cr, __entry->val) val 382 arch/x86/kvm/trace.h #define trace_kvm_cr_read(cr, val) trace_kvm_cr(0, cr, val) val 383 arch/x86/kvm/trace.h #define trace_kvm_cr_write(cr, val) trace_kvm_cr(1, cr, val) val 15 arch/x86/kvm/vmx/evmcs.c #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n))))) val 75 arch/x86/kvm/vmx/evmcs.h #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n))))) val 976 arch/x86/kvm/vmx/nested.c static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) val 981 arch/x86/kvm/vmx/nested.c return (val & invalid_mask) == 0; val 1371 arch/x86/kvm/vmx/nested.c unsigned long val; val 1383 arch/x86/kvm/vmx/nested.c val = __vmcs_readl(field.encoding); val 1384 arch/x86/kvm/vmx/nested.c vmcs12_write_any(vmcs12, field.encoding, field.offset, val); val 1406 arch/x86/kvm/vmx/nested.c unsigned long val; val 1417 arch/x86/kvm/vmx/nested.c val = vmcs12_read_any(vmcs12, field.encoding, val 1419 arch/x86/kvm/vmx/nested.c __vmcs_writel(field.encoding, val); val 2023 arch/x86/kvm/vmx/nested.c vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); val 2024 arch/x86/kvm/vmx/nested.c vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); val 3949 arch/x86/kvm/vmx/nested.c if (vmx->msr_autoload.guest.val[i].index == MSR_EFER) val 3950 arch/x86/kvm/vmx/nested.c return vmx->msr_autoload.guest.val[i].value; val 5222 arch/x86/kvm/vmx/nested.c unsigned long val; val 5227 arch/x86/kvm/vmx/nested.c val = kvm_register_readl(vcpu, reg); val 5231 arch/x86/kvm/vmx/nested.c (val ^ vmcs12->cr0_read_shadow)) val 5236 arch/x86/kvm/vmx/nested.c vmcs12->cr3_target_value0 == val) || val 5238 arch/x86/kvm/vmx/nested.c vmcs12->cr3_target_value1 == val) || val 5240 arch/x86/kvm/vmx/nested.c vmcs12->cr3_target_value2 == val) || val 5242 arch/x86/kvm/vmx/nested.c vmcs12->cr3_target_value3 == val)) val 5249 arch/x86/kvm/vmx/nested.c (vmcs12->cr4_read_shadow ^ val)) val 5282 arch/x86/kvm/vmx/nested.c val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; val 5284 arch/x86/kvm/vmx/nested.c (val ^ vmcs12->cr0_read_shadow)) val 5288 arch/x86/kvm/vmx/nested.c (val & 0x1)) val 255 arch/x86/kvm/vmx/nested.h static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) val 257 arch/x86/kvm/vmx/nested.h return ((val & fixed1) | fixed0) == val; val 260 arch/x86/kvm/vmx/nested.h static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) val 271 arch/x86/kvm/vmx/nested.h return fixed_bits_valid(val, fixed0, fixed1); val 274 arch/x86/kvm/vmx/nested.h static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) val 279 arch/x86/kvm/vmx/nested.h return fixed_bits_valid(val, fixed0, fixed1); val 282 arch/x86/kvm/vmx/nested.h static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) val 287 arch/x86/kvm/vmx/nested.h return fixed_bits_valid(val, fixed0, fixed1); val 193 arch/x86/kvm/vmx/pmu_intel.c u64 val = pmc_read_counter(pmc); val 194 arch/x86/kvm/vmx/pmu_intel.c *data = val & pmu->counter_bitmask[KVM_PMC_GP]; val 197 arch/x86/kvm/vmx/pmu_intel.c u64 val = pmc_read_counter(pmc); val 198 arch/x86/kvm/vmx/pmu_intel.c *data = val & pmu->counter_bitmask[KVM_PMC_FIXED]; val 5 arch/x86/kvm/vmx/vmcs12.c #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n))))) val 375 arch/x86/kvm/vmx/vmcs12.h #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n))))) val 820 arch/x86/kvm/vmx/vmx.c if (m->val[i].index == msr) val 853 arch/x86/kvm/vmx/vmx.c m->guest.val[i] = m->guest.val[m->guest.nr]; val 862 arch/x86/kvm/vmx/vmx.c m->host.val[i] = m->host.val[m->host.nr]; val 930 arch/x86/kvm/vmx/vmx.c m->guest.val[i].index = msr; val 931 arch/x86/kvm/vmx/vmx.c m->guest.val[i].value = guest_val; val 940 arch/x86/kvm/vmx/vmx.c m->host.val[j].index = msr; val 941 arch/x86/kvm/vmx/vmx.c m->host.val[j].value = host_val; val 1724 arch/x86/kvm/vmx/vmx.c uint64_t val) val 1728 arch/x86/kvm/vmx/vmx.c return !(val & ~valid_bits); val 4203 arch/x86/kvm/vmx/vmx.c vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); val 4205 arch/x86/kvm/vmx/vmx.c vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); val 4745 arch/x86/kvm/vmx/vmx.c static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) val 4749 arch/x86/kvm/vmx/vmx.c unsigned long orig_val = val; val 4759 arch/x86/kvm/vmx/vmx.c val = (val & ~vmcs12->cr0_guest_host_mask) | val 4762 arch/x86/kvm/vmx/vmx.c if (!nested_guest_cr0_valid(vcpu, val)) val 4765 arch/x86/kvm/vmx/vmx.c if (kvm_set_cr0(vcpu, val)) val 4771 arch/x86/kvm/vmx/vmx.c !nested_host_cr0_valid(vcpu, val)) val 4774 arch/x86/kvm/vmx/vmx.c return kvm_set_cr0(vcpu, val); val 4778 arch/x86/kvm/vmx/vmx.c static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) val 4782 arch/x86/kvm/vmx/vmx.c unsigned long orig_val = val; val 4785 arch/x86/kvm/vmx/vmx.c val = (val & ~vmcs12->cr4_guest_host_mask) | val 4787 arch/x86/kvm/vmx/vmx.c if (kvm_set_cr4(vcpu, val)) val 4792 arch/x86/kvm/vmx/vmx.c return kvm_set_cr4(vcpu, val); val 4803 arch/x86/kvm/vmx/vmx.c unsigned long exit_qualification, val; val 4814 arch/x86/kvm/vmx/vmx.c val = kvm_register_readl(vcpu, reg); val 4815 arch/x86/kvm/vmx/vmx.c trace_kvm_cr_write(cr, val); val 4818 arch/x86/kvm/vmx/vmx.c err = handle_set_cr0(vcpu, val); val 4822 arch/x86/kvm/vmx/vmx.c err = kvm_set_cr3(vcpu, val); val 4825 arch/x86/kvm/vmx/vmx.c err = handle_set_cr4(vcpu, val); val 4829 arch/x86/kvm/vmx/vmx.c u8 cr8 = (u8)val; val 4855 arch/x86/kvm/vmx/vmx.c val = kvm_read_cr3(vcpu); val 4856 arch/x86/kvm/vmx/vmx.c kvm_register_write(vcpu, reg, val); val 4857 arch/x86/kvm/vmx/vmx.c trace_kvm_cr_read(cr, val); val 4860 arch/x86/kvm/vmx/vmx.c val = kvm_get_cr8(vcpu); val 4861 arch/x86/kvm/vmx/vmx.c kvm_register_write(vcpu, reg, val); val 4862 arch/x86/kvm/vmx/vmx.c trace_kvm_cr_read(cr, val); val 4867 arch/x86/kvm/vmx/vmx.c val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; val 4868 arch/x86/kvm/vmx/vmx.c trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); val 4869 arch/x86/kvm/vmx/vmx.c kvm_lmsw(vcpu, val); val 4932 arch/x86/kvm/vmx/vmx.c unsigned long val; val 4934 arch/x86/kvm/vmx/vmx.c if (kvm_get_dr(vcpu, dr, &val)) val 4936 arch/x86/kvm/vmx/vmx.c kvm_register_write(vcpu, reg, val); val 4949 arch/x86/kvm/vmx/vmx.c static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) val 4966 arch/x86/kvm/vmx/vmx.c static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) val 4968 arch/x86/kvm/vmx/vmx.c vmcs_writel(GUEST_DR7, val); val 29 arch/x86/kvm/vmx/vmx.h struct vmx_msr_entry val[NR_AUTOLOAD_MSRS]; val 406 arch/x86/kvm/vmx/vmx.h static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \ val 408 arch/x86/kvm/vmx/vmx.h if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ val 409 arch/x86/kvm/vmx/vmx.h vmcs_write32(uname, val); \ val 410 arch/x86/kvm/vmx/vmx.h vmx->loaded_vmcs->controls_shadow.lname = val; \ val 417 arch/x86/kvm/vmx/vmx.h static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \ val 419 arch/x86/kvm/vmx/vmx.h lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ val 421 arch/x86/kvm/vmx/vmx.h static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \ val 423 arch/x86/kvm/vmx/vmx.h lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ val 1108 arch/x86/kvm/x86.c static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) val 1114 arch/x86/kvm/x86.c vcpu->arch.db[array_index_nospec(dr, size)] = val; val 1116 arch/x86/kvm/x86.c vcpu->arch.eff_db[dr] = val; val 1121 arch/x86/kvm/x86.c if (val & 0xffffffff00000000ULL) val 1123 arch/x86/kvm/x86.c vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); val 1129 arch/x86/kvm/x86.c if (val & 0xffffffff00000000ULL) val 1131 arch/x86/kvm/x86.c vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; val 1139 arch/x86/kvm/x86.c int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) val 1141 arch/x86/kvm/x86.c if (__kvm_set_dr(vcpu, dr, val)) { val 1149 arch/x86/kvm/x86.c int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) val 1155 arch/x86/kvm/x86.c *val = vcpu->arch.db[array_index_nospec(dr, size)]; val 1161 arch/x86/kvm/x86.c *val = vcpu->arch.dr6; val 1163 arch/x86/kvm/x86.c *val = kvm_x86_ops->get_dr6(vcpu); val 1168 arch/x86/kvm/x86.c *val = vcpu->arch.dr7; val 3917 arch/x86/kvm/x86.c unsigned long val; val 3920 arch/x86/kvm/x86.c kvm_get_dr(vcpu, 6, &val); val 3921 arch/x86/kvm/x86.c dbgregs->dr6 = val; val 5386 arch/x86/kvm/x86.c static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, val 5390 arch/x86/kvm/x86.c void *data = val; val 5419 arch/x86/kvm/x86.c gva_t addr, void *val, unsigned int bytes, val 5436 arch/x86/kvm/x86.c ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, val 5445 arch/x86/kvm/x86.c gva_t addr, void *val, unsigned int bytes, val 5457 arch/x86/kvm/x86.c return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, val 5463 arch/x86/kvm/x86.c gva_t addr, void *val, unsigned int bytes, val 5472 arch/x86/kvm/x86.c return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); val 5476 arch/x86/kvm/x86.c unsigned long addr, void *val, unsigned int bytes) val 5479 arch/x86/kvm/x86.c int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); val 5484 arch/x86/kvm/x86.c static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, val 5488 arch/x86/kvm/x86.c void *data = val; val 5515 arch/x86/kvm/x86.c static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, val 5525 arch/x86/kvm/x86.c return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, val 5529 arch/x86/kvm/x86.c int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, val 5542 arch/x86/kvm/x86.c return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, val 5610 arch/x86/kvm/x86.c const void *val, int bytes) val 5614 arch/x86/kvm/x86.c ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); val 5617 arch/x86/kvm/x86.c kvm_page_track_write(vcpu, gpa, val, bytes); val 5622 arch/x86/kvm/x86.c int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, val 5625 arch/x86/kvm/x86.c void *val, int bytes); val 5627 arch/x86/kvm/x86.c int bytes, void *val); val 5629 arch/x86/kvm/x86.c void *val, int bytes); val 5633 arch/x86/kvm/x86.c static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) val 5637 arch/x86/kvm/x86.c vcpu->mmio_fragments[0].gpa, val); val 5646 arch/x86/kvm/x86.c void *val, int bytes) val 5648 arch/x86/kvm/x86.c return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); val 5652 arch/x86/kvm/x86.c void *val, int bytes) val 5654 arch/x86/kvm/x86.c return emulator_write_phys(vcpu, gpa, val, bytes); val 5657 arch/x86/kvm/x86.c static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) val 5659 arch/x86/kvm/x86.c trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); val 5660 arch/x86/kvm/x86.c return vcpu_mmio_write(vcpu, gpa, bytes, val); val 5664 arch/x86/kvm/x86.c void *val, int bytes) val 5671 arch/x86/kvm/x86.c void *val, int bytes) val 5693 arch/x86/kvm/x86.c static int emulator_read_write_onepage(unsigned long addr, void *val, val 5723 arch/x86/kvm/x86.c if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) val 5729 arch/x86/kvm/x86.c handled = ops->read_write_mmio(vcpu, gpa, bytes, val); val 5735 arch/x86/kvm/x86.c val += handled; val 5740 arch/x86/kvm/x86.c frag->data = val; val 5747 arch/x86/kvm/x86.c void *val, unsigned int bytes, val 5756 arch/x86/kvm/x86.c ops->read_write_prepare(vcpu, val, bytes)) val 5766 arch/x86/kvm/x86.c rc = emulator_read_write_onepage(addr, val, now, exception, val 5774 arch/x86/kvm/x86.c val += now; val 5778 arch/x86/kvm/x86.c rc = emulator_read_write_onepage(addr, val, bytes, exception, val 5796 arch/x86/kvm/x86.c return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); val 5801 arch/x86/kvm/x86.c void *val, val 5805 arch/x86/kvm/x86.c return emulator_read_write(ctxt, addr, val, bytes, val 5811 arch/x86/kvm/x86.c const void *val, val 5815 arch/x86/kvm/x86.c return emulator_read_write(ctxt, addr, (void *)val, bytes, val 5912 arch/x86/kvm/x86.c unsigned short port, void *val, val 5936 arch/x86/kvm/x86.c int size, unsigned short port, void *val, val 5947 arch/x86/kvm/x86.c ret = emulator_pio_in_out(vcpu, size, port, val, count, true); val 5950 arch/x86/kvm/x86.c memcpy(val, vcpu->arch.pio_data, size * count); val 5961 arch/x86/kvm/x86.c const void *val, unsigned int count) val 5965 arch/x86/kvm/x86.c memcpy(vcpu->arch.pio_data, val, size * count); val 5967 arch/x86/kvm/x86.c return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); val 6059 arch/x86/kvm/x86.c static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) val 6066 arch/x86/kvm/x86.c res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); val 6069 arch/x86/kvm/x86.c vcpu->arch.cr2 = val; val 6072 arch/x86/kvm/x86.c res = kvm_set_cr3(vcpu, val); val 6075 arch/x86/kvm/x86.c res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); val 6078 arch/x86/kvm/x86.c res = kvm_set_cr8(vcpu, val); val 6246 arch/x86/kvm/x86.c static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) val 6248 arch/x86/kvm/x86.c kvm_register_write(emul_to_vcpu(ctxt), reg, val); val 6887 arch/x86/kvm/x86.c unsigned long val = kvm_rax_read(vcpu); val 6889 arch/x86/kvm/x86.c size, port, &val, 1); val 6911 arch/x86/kvm/x86.c unsigned long val; val 6922 arch/x86/kvm/x86.c val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; val 6929 arch/x86/kvm/x86.c vcpu->arch.pio.port, &val, 1); val 6930 arch/x86/kvm/x86.c kvm_rax_write(vcpu, val); val 6938 arch/x86/kvm/x86.c unsigned long val; val 6942 arch/x86/kvm/x86.c val = (size < 4) ? kvm_rax_read(vcpu) : 0; val 6945 arch/x86/kvm/x86.c &val, 1); val 6947 arch/x86/kvm/x86.c kvm_rax_write(vcpu, val); val 7102 arch/x86/kvm/x86.c static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, val 7108 arch/x86/kvm/x86.c if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) val 7110 arch/x86/kvm/x86.c if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) val 7755 arch/x86/kvm/x86.c unsigned long val; val 7766 arch/x86/kvm/x86.c kvm_get_dr(vcpu, 6, &val); val 7767 arch/x86/kvm/x86.c put_smstate(u32, buf, 0x7fcc, (u32)val); val 7768 arch/x86/kvm/x86.c kvm_get_dr(vcpu, 7, &val); val 7769 arch/x86/kvm/x86.c put_smstate(u32, buf, 0x7fc8, (u32)val); val 7806 arch/x86/kvm/x86.c unsigned long val; val 7815 arch/x86/kvm/x86.c kvm_get_dr(vcpu, 6, &val); val 7816 arch/x86/kvm/x86.c put_smstate(u64, buf, 0x7f68, val); val 7817 arch/x86/kvm/x86.c kvm_get_dr(vcpu, 7, &val); val 7818 arch/x86/kvm/x86.c put_smstate(u64, buf, 0x7f60, val); val 10143 arch/x86/kvm/x86.c static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) val 10146 arch/x86/kvm/x86.c return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, val 10147 arch/x86/kvm/x86.c sizeof(val)); val 10150 arch/x86/kvm/x86.c static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) val 10153 arch/x86/kvm/x86.c return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, val 10221 arch/x86/kvm/x86.c u32 val; val 10230 arch/x86/kvm/x86.c !apf_get_user(vcpu, &val)) { val 10231 arch/x86/kvm/x86.c if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && val 17 arch/x86/kvm/x86.h static inline unsigned int __grow_ple_window(unsigned int val, val 20 arch/x86/kvm/x86.h u64 ret = val; val 33 arch/x86/kvm/x86.h static inline unsigned int __shrink_ple_window(unsigned int val, val 40 arch/x86/kvm/x86.h val /= modifier; val 42 arch/x86/kvm/x86.h val -= modifier; val 44 arch/x86/kvm/x86.h return max(val, min); val 244 arch/x86/kvm/x86.h unsigned long val = kvm_register_read(vcpu, reg); val 246 arch/x86/kvm/x86.h return is_64_bit_mode(vcpu) ? val : (u32)val; val 251 arch/x86/kvm/x86.h unsigned long val) val 254 arch/x86/kvm/x86.h val = (u32)val; val 255 arch/x86/kvm/x86.h return kvm_register_write(vcpu, reg, val); val 270 arch/x86/kvm/x86.h gva_t addr, void *val, unsigned int bytes, val 274 arch/x86/kvm/x86.h gva_t addr, void *val, unsigned int bytes, val 7 arch/x86/lib/misc.c int num_digits(int val) val 12 arch/x86/lib/misc.c if (val < 0) { val 14 arch/x86/lib/misc.c val = -val; val 17 arch/x86/lib/misc.c while (val >= m) { val 42 arch/x86/lib/msr.c u64 val; val 44 arch/x86/lib/msr.c err = rdmsrl_safe(msr, &val); val 46 arch/x86/lib/msr.c m->q = val; val 117 arch/x86/lib/msr.c void do_trace_write_msr(unsigned int msr, u64 val, int failed) val 119 arch/x86/lib/msr.c trace_write_msr(msr, val, failed); val 124 arch/x86/lib/msr.c void do_trace_read_msr(unsigned int msr, u64 val, int failed) val 126 arch/x86/lib/msr.c trace_read_msr(msr, val, failed); val 131 arch/x86/lib/msr.c void do_trace_rdpmc(unsigned counter, u64 val, int failed) val 133 arch/x86/lib/msr.c trace_rdpmc(counter, val, failed); val 250 arch/x86/mm/kasan_init_64.c unsigned long val, val 253 arch/x86/mm/kasan_init_64.c if (val == DIE_GPF) { val 586 arch/x86/mm/kmmio.c kmmio_die_notifier(struct notifier_block *nb, unsigned long val, void *args) val 591 arch/x86/mm/kmmio.c if (val == DIE_DEBUG && (*dr6_p & DR_STEP)) val 489 arch/x86/mm/pageattr.c static inline bool conflicts(pgprot_t prot, pgprotval_t val) val 491 arch/x86/mm/pageattr.c return (pgprot_val(prot) & ~val) != pgprot_val(prot); val 494 arch/x86/mm/pageattr.c static inline void check_conflict(int warnlvl, pgprot_t prot, pgprotval_t val, val 504 arch/x86/mm/pageattr.c if (warnlvl > cpa_warn_level || !conflicts(prot, val)) val 509 arch/x86/mm/pageattr.c (unsigned long long)val); val 205 arch/x86/net/bpf_jit_comp32.c static inline void emit_ia32_mov_i(const u8 dst, const u32 val, bool dstk, val 212 arch/x86/net/bpf_jit_comp32.c if (val == 0) { val 220 arch/x86/net/bpf_jit_comp32.c STACK_VAR(dst), val); val 223 arch/x86/net/bpf_jit_comp32.c if (val == 0) val 227 arch/x86/net/bpf_jit_comp32.c val); val 270 arch/x86/net/bpf_jit_comp32.c const u32 val, bool dstk, u8 **pprog) val 274 arch/x86/net/bpf_jit_comp32.c if (is64 && (val & (1<<31))) val 276 arch/x86/net/bpf_jit_comp32.c emit_ia32_mov_i(dst_lo, val, dstk, pprog); val 316 arch/x86/net/bpf_jit_comp32.c static inline void emit_ia32_to_le_r64(const u8 dst[], s32 val, val 325 arch/x86/net/bpf_jit_comp32.c if (dstk && val != 64) { val 331 arch/x86/net/bpf_jit_comp32.c switch (val) { val 353 arch/x86/net/bpf_jit_comp32.c if (dstk && val != 64) { val 364 arch/x86/net/bpf_jit_comp32.c static inline void emit_ia32_to_be_r64(const u8 dst[], s32 val, val 379 arch/x86/net/bpf_jit_comp32.c switch (val) { val 597 arch/x86/net/bpf_jit_comp32.c const u8 dst, const s32 val, bool dstk, val 609 arch/x86/net/bpf_jit_comp32.c if (!is_imm8(val)) val 611 arch/x86/net/bpf_jit_comp32.c EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EDX), val); val 617 arch/x86/net/bpf_jit_comp32.c if (is_imm8(val)) val 618 arch/x86/net/bpf_jit_comp32.c EMIT3(0x83, add_1reg(0xD0, dreg), val); val 622 arch/x86/net/bpf_jit_comp32.c if (is_imm8(val)) val 623 arch/x86/net/bpf_jit_comp32.c EMIT3(0x83, add_1reg(0xC0, dreg), val); val 631 arch/x86/net/bpf_jit_comp32.c if (is_imm8(val)) val 632 arch/x86/net/bpf_jit_comp32.c EMIT3(0x83, add_1reg(0xD8, dreg), val); val 636 arch/x86/net/bpf_jit_comp32.c if (is_imm8(val)) val 637 arch/x86/net/bpf_jit_comp32.c EMIT3(0x83, add_1reg(0xE8, dreg), val); val 644 arch/x86/net/bpf_jit_comp32.c if (is_imm8(val)) val 645 arch/x86/net/bpf_jit_comp32.c EMIT3(0x83, add_1reg(0xC8, dreg), val); val 651 arch/x86/net/bpf_jit_comp32.c if (is_imm8(val)) val 652 arch/x86/net/bpf_jit_comp32.c EMIT3(0x83, add_1reg(0xE0, dreg), val); val 658 arch/x86/net/bpf_jit_comp32.c if (is_imm8(val)) val 659 arch/x86/net/bpf_jit_comp32.c EMIT3(0x83, add_1reg(0xF0, dreg), val); val 677 arch/x86/net/bpf_jit_comp32.c const u8 dst[], const u32 val, val 684 arch/x86/net/bpf_jit_comp32.c if (is64 && (val & (1<<31))) val 687 arch/x86/net/bpf_jit_comp32.c emit_ia32_alu_i(is64, false, op, dst_lo, val, dstk, &prog); val 889 arch/x86/net/bpf_jit_comp32.c static inline void emit_ia32_lsh_i64(const u8 dst[], const u32 val, val 904 arch/x86/net/bpf_jit_comp32.c if (val < 32) { val 906 arch/x86/net/bpf_jit_comp32.c EMIT4(0x0F, 0xA4, add_2reg(0xC0, dreg_hi, dreg_lo), val); val 908 arch/x86/net/bpf_jit_comp32.c EMIT3(0xC1, add_1reg(0xE0, dreg_lo), val); val 909 arch/x86/net/bpf_jit_comp32.c } else if (val >= 32 && val < 64) { val 910 arch/x86/net/bpf_jit_comp32.c u32 value = val - 32; val 937 arch/x86/net/bpf_jit_comp32.c static inline void emit_ia32_rsh_i64(const u8 dst[], const u32 val, val 953 arch/x86/net/bpf_jit_comp32.c if (val < 32) { val 955 arch/x86/net/bpf_jit_comp32.c EMIT4(0x0F, 0xAC, add_2reg(0xC0, dreg_lo, dreg_hi), val); val 957 arch/x86/net/bpf_jit_comp32.c EMIT3(0xC1, add_1reg(0xE8, dreg_hi), val); val 958 arch/x86/net/bpf_jit_comp32.c } else if (val >= 32 && val < 64) { val 959 arch/x86/net/bpf_jit_comp32.c u32 value = val - 32; val 986 arch/x86/net/bpf_jit_comp32.c static inline void emit_ia32_arsh_i64(const u8 dst[], const u32 val, val 1001 arch/x86/net/bpf_jit_comp32.c if (val < 32) { val 1003 arch/x86/net/bpf_jit_comp32.c EMIT4(0x0F, 0xAC, add_2reg(0xC0, dreg_lo, dreg_hi), val); val 1005 arch/x86/net/bpf_jit_comp32.c EMIT3(0xC1, add_1reg(0xF8, dreg_hi), val); val 1006 arch/x86/net/bpf_jit_comp32.c } else if (val >= 32 && val < 64) { val 1007 arch/x86/net/bpf_jit_comp32.c u32 value = val - 32; val 1111 arch/x86/net/bpf_jit_comp32.c static inline void emit_ia32_mul_i64(const u8 dst[], const u32 val, val 1118 arch/x86/net/bpf_jit_comp32.c hi = val & (1<<31) ? (u32)~0 : 0; val 1120 arch/x86/net/bpf_jit_comp32.c EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val); val 1143 arch/x86/net/bpf_jit_comp32.c EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val); val 45 arch/x86/oprofile/nmi_int.c u64 val = 0; val 48 arch/x86/oprofile/nmi_int.c val |= ARCH_PERFMON_EVENTSEL_INT; val 49 arch/x86/oprofile/nmi_int.c val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; val 50 arch/x86/oprofile/nmi_int.c val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; val 51 arch/x86/oprofile/nmi_int.c val |= (counter_config->unit_mask & 0xFF) << 8; val 55 arch/x86/oprofile/nmi_int.c val |= counter_config->extra; val 57 arch/x86/oprofile/nmi_int.c val |= event & 0xFF; val 58 arch/x86/oprofile/nmi_int.c val |= (u64)(event & 0x0F00) << 24; val 60 arch/x86/oprofile/nmi_int.c return val; val 64 arch/x86/oprofile/nmi_int.c static int profile_exceptions_notify(unsigned int val, struct pt_regs *regs) val 106 arch/x86/oprofile/op_model_amd.c static inline u64 op_amd_randomize_ibs_op(u64 val) val 124 arch/x86/oprofile/op_model_amd.c val += (s8)(random >> 4); val 126 arch/x86/oprofile/op_model_amd.c val |= (u64)(random & IBS_RANDOM_MASK) << 32; val 128 arch/x86/oprofile/op_model_amd.c return val; val 135 arch/x86/oprofile/op_model_amd.c u64 val, ctl; val 144 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); val 145 arch/x86/oprofile/op_model_amd.c oprofile_write_reserve(&entry, regs, val, val 147 arch/x86/oprofile/op_model_amd.c oprofile_add_data64(&entry, val); val 149 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); val 150 arch/x86/oprofile/op_model_amd.c oprofile_add_data64(&entry, val); val 163 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPRIP, val); val 164 arch/x86/oprofile/op_model_amd.c oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE, val 166 arch/x86/oprofile/op_model_amd.c oprofile_add_data64(&entry, val); val 167 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPDATA, val); val 168 arch/x86/oprofile/op_model_amd.c oprofile_add_data64(&entry, val); val 169 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPDATA2, val); val 170 arch/x86/oprofile/op_model_amd.c oprofile_add_data64(&entry, val); val 171 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPDATA3, val); val 172 arch/x86/oprofile/op_model_amd.c oprofile_add_data64(&entry, val); val 173 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSDCLINAD, val); val 174 arch/x86/oprofile/op_model_amd.c oprofile_add_data64(&entry, val); val 175 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); val 176 arch/x86/oprofile/op_model_amd.c oprofile_add_data64(&entry, val); val 178 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSBRTARGET, val); val 179 arch/x86/oprofile/op_model_amd.c oprofile_add_data(&entry, (unsigned long)val); val 192 arch/x86/oprofile/op_model_amd.c u64 val; val 206 arch/x86/oprofile/op_model_amd.c val = ibs_config.max_cnt_fetch >> 4; val 207 arch/x86/oprofile/op_model_amd.c val = min(val, IBS_FETCH_MAX_CNT); val 208 arch/x86/oprofile/op_model_amd.c ibs_config.max_cnt_fetch = val << 4; val 209 arch/x86/oprofile/op_model_amd.c val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; val 210 arch/x86/oprofile/op_model_amd.c val |= IBS_FETCH_ENABLE; val 211 arch/x86/oprofile/op_model_amd.c wrmsrl(MSR_AMD64_IBSFETCHCTL, val); val 215 arch/x86/oprofile/op_model_amd.c val = ibs_config.max_cnt_op >> 4; val 221 arch/x86/oprofile/op_model_amd.c val = clamp(val, 0x0081ULL, 0xFF80ULL); val 222 arch/x86/oprofile/op_model_amd.c ibs_config.max_cnt_op = val << 4; val 230 arch/x86/oprofile/op_model_amd.c val += IBS_RANDOM_MAXCNT_OFFSET; val 232 arch/x86/oprofile/op_model_amd.c val = min(val, IBS_OP_MAX_CNT_EXT); val 234 arch/x86/oprofile/op_model_amd.c val = min(val, IBS_OP_MAX_CNT); val 236 arch/x86/oprofile/op_model_amd.c (val - IBS_RANDOM_MAXCNT_OFFSET) << 4; val 238 arch/x86/oprofile/op_model_amd.c val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT); val 239 arch/x86/oprofile/op_model_amd.c val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; val 240 arch/x86/oprofile/op_model_amd.c val |= IBS_OP_ENABLE; val 241 arch/x86/oprofile/op_model_amd.c ibs_state.ibs_op_ctl = val; val 247 arch/x86/oprofile/op_model_amd.c val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl); val 248 arch/x86/oprofile/op_model_amd.c wrmsrl(MSR_AMD64_IBSOPCTL, val); val 271 arch/x86/oprofile/op_model_amd.c u64 val; val 279 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); val 280 arch/x86/oprofile/op_model_amd.c val &= model->reserved; val 281 arch/x86/oprofile/op_model_amd.c val |= op_x86_get_ctrl(model, &counter_config[virt]); val 282 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); val 336 arch/x86/oprofile/op_model_amd.c u64 val; val 352 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); val 353 arch/x86/oprofile/op_model_amd.c if (val & ARCH_PERFMON_EVENTSEL_ENABLE) val 355 arch/x86/oprofile/op_model_amd.c val &= model->reserved; val 356 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); val 374 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); val 375 arch/x86/oprofile/op_model_amd.c val &= model->reserved; val 376 arch/x86/oprofile/op_model_amd.c val |= op_x86_get_ctrl(model, &counter_config[virt]); val 377 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); val 384 arch/x86/oprofile/op_model_amd.c u64 val; val 391 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->counters[i].addr, val); val 393 arch/x86/oprofile/op_model_amd.c if (val & OP_CTR_OVERFLOW) val 407 arch/x86/oprofile/op_model_amd.c u64 val; val 413 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); val 414 arch/x86/oprofile/op_model_amd.c val |= ARCH_PERFMON_EVENTSEL_ENABLE; val 415 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); val 423 arch/x86/oprofile/op_model_amd.c u64 val; val 433 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); val 434 arch/x86/oprofile/op_model_amd.c val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; val 435 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); val 75 arch/x86/oprofile/op_model_ppro.c u64 val; val 99 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->controls[i].addr, val); val 100 arch/x86/oprofile/op_model_ppro.c if (val & ARCH_PERFMON_EVENTSEL_ENABLE) val 102 arch/x86/oprofile/op_model_ppro.c val &= model->reserved; val 103 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->controls[i].addr, val); val 116 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->controls[i].addr, val); val 117 arch/x86/oprofile/op_model_ppro.c val &= model->reserved; val 118 arch/x86/oprofile/op_model_ppro.c val |= op_x86_get_ctrl(model, &counter_config[i]); val 119 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->controls[i].addr, val); val 130 arch/x86/oprofile/op_model_ppro.c u64 val; val 136 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->counters[i].addr, val); val 137 arch/x86/oprofile/op_model_ppro.c if (val & (1ULL << (counter_width - 1))) val 160 arch/x86/oprofile/op_model_ppro.c u64 val; val 165 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->controls[i].addr, val); val 166 arch/x86/oprofile/op_model_ppro.c val |= ARCH_PERFMON_EVENTSEL_ENABLE; val 167 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->controls[i].addr, val); val 175 arch/x86/oprofile/op_model_ppro.c u64 val; val 181 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->controls[i].addr, val); val 182 arch/x86/oprofile/op_model_ppro.c val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; val 183 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->controls[i].addr, val); val 74 arch/x86/pci/amd_bus.c u64 val; val 197 arch/x86/pci/amd_bus.c rdmsrl(address, val); val 198 arch/x86/pci/amd_bus.c end = (val & 0xffffff800000ULL); val 288 arch/x86/pci/amd_bus.c rdmsrl(address, val); val 290 arch/x86/pci/amd_bus.c if (val & (1<<21)) { val 293 arch/x86/pci/amd_bus.c rdmsrl(address, val); val 294 arch/x86/pci/amd_bus.c end = (val & 0xffffff800000ULL); val 355 arch/x86/pci/amd_bus.c u32 val = read_pci_config(bus, slot, 3, 0); val 357 arch/x86/pci/amd_bus.c if (!early_is_amd_nb(val)) val 360 arch/x86/pci/amd_bus.c val = read_pci_config(bus, slot, 3, 0x8c); val 361 arch/x86/pci/amd_bus.c if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) { val 362 arch/x86/pci/amd_bus.c val |= ENABLE_CF8_EXT_CFG >> 32; val 363 arch/x86/pci/amd_bus.c write_pci_config(bus, slot, 3, 0x8c, val); val 40 arch/x86/pci/common.c int reg, int len, u32 *val) val 43 arch/x86/pci/common.c return raw_pci_ops->read(domain, bus, devfn, reg, len, val); val 45 arch/x86/pci/common.c return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); val 50 arch/x86/pci/common.c int reg, int len, u32 val) val 53 arch/x86/pci/common.c return raw_pci_ops->write(domain, bus, devfn, reg, len, val); val 55 arch/x86/pci/common.c return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); val 36 arch/x86/pci/early.c u32 val) val 39 arch/x86/pci/early.c outl(val, 0xcfc); val 42 arch/x86/pci/early.c void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val) val 45 arch/x86/pci/early.c outb(val, 0xcfc + (offset&3)); val 48 arch/x86/pci/early.c void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val) val 51 arch/x86/pci/early.c outw(val, 0xcfc + (offset&2)); val 176 arch/x86/pci/fixup.c u32 val; val 186 arch/x86/pci/fixup.c pci_read_config_dword(dev, 0x6c, &val); val 191 arch/x86/pci/fixup.c if ((val & 0x00FF0000) != 0x00010000) { val 193 arch/x86/pci/fixup.c pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); val 383 arch/x86/pci/fixup.c unsigned char val; val 387 arch/x86/pci/fixup.c pci_read_config_byte(dev, 0x50, &val); val 388 arch/x86/pci/fixup.c if (val & 0x40) { val 389 arch/x86/pci/fixup.c pci_write_config_byte(dev, 0x50, val & (~0x40)); val 392 arch/x86/pci/fixup.c pci_read_config_byte(dev, 0x50, &val); val 393 arch/x86/pci/fixup.c if (val & 0x40) val 504 arch/x86/pci/fixup.c u8 val; val 513 arch/x86/pci/fixup.c pci_read_config_byte(dev, 0x08, &val); val 515 arch/x86/pci/fixup.c if (val < 0x2F) { val 517 arch/x86/pci/fixup.c val = inb(0xCD7); val 521 arch/x86/pci/fixup.c outb(val | 0x80, 0xCD7); val 95 arch/x86/pci/intel_mid_pci.c int reg, int len, u32 val, int offset) val 104 arch/x86/pci/intel_mid_pci.c if (val == ~0 && len == 4) { val 135 arch/x86/pci/intel_mid_pci.c return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val); val 157 arch/x86/pci/irq.c unsigned char val; val 165 arch/x86/pci/irq.c val = inb(port); val 166 arch/x86/pci/irq.c if (!(val & mask)) { val 168 arch/x86/pci/irq.c outb(val | mask, port); val 186 arch/x86/pci/irq.c unsigned nr, unsigned int val) val 192 arch/x86/pci/irq.c x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); val 212 arch/x86/pci/irq.c unsigned int val = irqmap[irq]; val 215 arch/x86/pci/irq.c if (val) { val 216 arch/x86/pci/irq.c write_config_nybble(router, 0x48, pirq-1, val); val 114 arch/x86/pci/numachip.c u32 val; val 118 arch/x86/pci/numachip.c ret = raw_pci_read(0, 0, PCI_DEVFN(0x18, 0), 0x60, sizeof(val), &val); val 123 arch/x86/pci/numachip.c limit = PCI_DEVFN(0x18 + ((val >> 4) & 7) + 1, 0); val 45 arch/x86/platform/intel-mid/intel_mid_vrtc.c void vrtc_cmos_write(unsigned char val, unsigned char reg) val 51 arch/x86/platform/intel-mid/intel_mid_vrtc.c __raw_writeb(val, vrtc_virt_base + (reg << 2)); val 451 arch/x86/platform/intel/iosf_mbi.c static int mcr_get(void *data, u64 *val) val 453 arch/x86/platform/intel/iosf_mbi.c *val = *(u32 *)data; val 457 arch/x86/platform/intel/iosf_mbi.c static int mcr_set(void *data, u64 val) val 459 arch/x86/platform/intel/iosf_mbi.c u8 command = ((u32)val & 0xFF000000) >> 24, val 460 arch/x86/platform/intel/iosf_mbi.c port = ((u32)val & 0x00FF0000) >> 16, val 461 arch/x86/platform/intel/iosf_mbi.c offset = ((u32)val & 0x0000FF00) >> 8; val 464 arch/x86/platform/intel/iosf_mbi.c *(u32 *)data = val; val 61 arch/x86/platform/olpc/olpc-xo15-sci.c unsigned int val; val 63 arch/x86/platform/olpc/olpc-xo15-sci.c if (sscanf(buf, "%u", &val) != 1) val 66 arch/x86/platform/olpc/olpc-xo15-sci.c set_lid_wake_behavior(!!val); val 102 arch/x86/platform/uv/bios_uv.c part.val = v0; val 1541 arch/x86/platform/uv/tlb_uv.c int val = 0; val 1546 arch/x86/platform/uv/tlb_uv.c val = 10*val+(*name-'0'); val 1549 arch/x86/platform/uv/tlb_uv.c return val; val 1564 arch/x86/platform/uv/tlb_uv.c int val; val 1584 arch/x86/platform/uv/tlb_uv.c val = local_atoi(p); val 1587 arch/x86/platform/uv/tlb_uv.c if (val == 0) { val 1592 arch/x86/platform/uv/tlb_uv.c if (val < 1 || val > bcp->cpus_in_uvhub) { val 1595 arch/x86/platform/uv/tlb_uv.c val); val 1598 arch/x86/platform/uv/tlb_uv.c max_concurr = val; val 1599 arch/x86/platform/uv/tlb_uv.c max_concurr_const = val; val 1602 arch/x86/platform/uv/tlb_uv.c if (val == 0) val 1605 arch/x86/platform/uv/tlb_uv.c *tunables[cnt].tunp = val; val 2247 arch/x86/platform/uv/tlb_uv.c unsigned long val; val 2251 arch/x86/platform/uv/tlb_uv.c val = 1L << 63; val 2252 arch/x86/platform/uv/tlb_uv.c write_gmmr_activation(pnode, val); val 101 arch/x86/platform/uv/uv_nmi.c static int param_set_local64(const char *val, const struct kernel_param *kp) val 184 arch/x86/platform/uv/uv_nmi.c static int param_set_action(const char *val, const struct kernel_param *kp) val 191 arch/x86/platform/uv/uv_nmi.c strncpy(arg, val, ACTION_LEN - 1); val 72 arch/x86/platform/uv/uv_time.c unsigned long apicid, val; val 78 arch/x86/platform/uv/uv_time.c val = (1UL << UVH_IPI_INT_SEND_SHFT) | val 82 arch/x86/platform/uv/uv_time.c uv_write_global_mmr64(pnode, UVH_IPI_INT, val); val 100 arch/x86/platform/uv/uv_time.c u64 val; val 115 arch/x86/platform/uv/uv_time.c val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) | val 119 arch/x86/platform/uv/uv_time.c uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val); val 301 arch/x86/tools/relocs.c #define le16_to_cpu(val) (val) val 302 arch/x86/tools/relocs.c #define le32_to_cpu(val) (val) val 303 arch/x86/tools/relocs.c #define le64_to_cpu(val) (val) val 306 arch/x86/tools/relocs.c #define le16_to_cpu(val) bswap_16(val) val 307 arch/x86/tools/relocs.c #define le32_to_cpu(val) bswap_32(val) val 308 arch/x86/tools/relocs.c #define le64_to_cpu(val) bswap_64(val) val 311 arch/x86/tools/relocs.c static uint16_t elf16_to_cpu(uint16_t val) val 313 arch/x86/tools/relocs.c return le16_to_cpu(val); val 316 arch/x86/tools/relocs.c static uint32_t elf32_to_cpu(uint32_t val) val 318 arch/x86/tools/relocs.c return le32_to_cpu(val); val 325 arch/x86/tools/relocs.c static uint64_t elf64_to_cpu(uint64_t val) val 327 arch/x86/tools/relocs.c return le64_to_cpu(val); val 12 arch/x86/tools/relocs_32.c #define ELF_R_SYM(val) ELF32_R_SYM(val) val 13 arch/x86/tools/relocs_32.c #define ELF_R_TYPE(val) ELF32_R_TYPE(val) val 12 arch/x86/tools/relocs_64.c #define ELF_R_SYM(val) ELF64_R_SYM(val) val 13 arch/x86/tools/relocs_64.c #define ELF_R_TYPE(val) ELF64_R_TYPE(val) val 25 arch/x86/um/os-Linux/tls.c int val[] = {GDT_ENTRY_TLS_MIN_I386, GDT_ENTRY_TLS_MIN_X86_64}; val 28 arch/x86/um/os-Linux/tls.c for (i = 0; i < ARRAY_SIZE(val); i++) { val 30 arch/x86/um/os-Linux/tls.c info.entry_number = val[i]; val 33 arch/x86/um/os-Linux/tls.c *tls_min = val[i]; val 24 arch/x86/um/user-offsets.c #define DEFINE(sym, val) \ val 25 arch/x86/um/user-offsets.c asm volatile("\n->" #sym " %0 " #val : : "i" (val)) val 27 arch/x86/um/user-offsets.c #define DEFINE_LONGS(sym, val) \ val 28 arch/x86/um/user-offsets.c asm volatile("\n->" #sym " %0 " #val : : "i" (val/sizeof(unsigned long))) val 75 arch/x86/xen/apic.c static void xen_apic_write(u32 reg, u32 val) val 83 arch/x86/xen/apic.c WARN(1,"register: %x, value: %x\n", reg, val); val 321 arch/x86/xen/enlighten_pv.c static void xen_set_debugreg(int reg, unsigned long val) val 323 arch/x86/xen/enlighten_pv.c HYPERVISOR_set_debugreg(reg, val); val 670 arch/x86/xen/enlighten_pv.c static int cvt_gate_to_trap(int vector, const gate_desc *val, val 675 arch/x86/xen/enlighten_pv.c if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) val 680 arch/x86/xen/enlighten_pv.c addr = gate_offset(val); val 682 arch/x86/xen/enlighten_pv.c if (!get_trap_addr((void **)&addr, val->bits.ist)) val 687 arch/x86/xen/enlighten_pv.c info->cs = gate_segment(val); val 688 arch/x86/xen/enlighten_pv.c info->flags = val->bits.dpl; val 690 arch/x86/xen/enlighten_pv.c if (val->bits.type == GATE_INTERRUPT) val 891 arch/x86/xen/enlighten_pv.c u64 val; val 893 arch/x86/xen/enlighten_pv.c if (pmu_msr_read(msr, &val, err)) val 894 arch/x86/xen/enlighten_pv.c return val; val 896 arch/x86/xen/enlighten_pv.c val = native_read_msr_safe(msr, err); val 899 arch/x86/xen/enlighten_pv.c val &= ~X2APIC_ENABLE; val 902 arch/x86/xen/enlighten_pv.c return val; val 219 arch/x86/xen/mmu_pv.c static void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val) val 229 arch/x86/xen/mmu_pv.c u.val = pmd_val_ma(val); val 237 arch/x86/xen/mmu_pv.c static void xen_set_pmd(pmd_t *ptr, pmd_t val) val 239 arch/x86/xen/mmu_pv.c trace_xen_mmu_set_pmd(ptr, val); val 244 arch/x86/xen/mmu_pv.c *ptr = val; val 248 arch/x86/xen/mmu_pv.c xen_set_pmd_hyper(ptr, val); val 270 arch/x86/xen/mmu_pv.c u.val = pte_val_ma(pteval); val 291 arch/x86/xen/mmu_pv.c u.val = pte_val_ma(pteval); val 326 arch/x86/xen/mmu_pv.c u.val = pte_val_ma(pte); val 333 arch/x86/xen/mmu_pv.c static pteval_t pte_mfn_to_pfn(pteval_t val) val 335 arch/x86/xen/mmu_pv.c if (val & _PAGE_PRESENT) { val 336 arch/x86/xen/mmu_pv.c unsigned long mfn = (val & XEN_PTE_MFN_MASK) >> PAGE_SHIFT; val 339 arch/x86/xen/mmu_pv.c pteval_t flags = val & PTE_FLAGS_MASK; val 341 arch/x86/xen/mmu_pv.c val = flags & ~_PAGE_PRESENT; val 343 arch/x86/xen/mmu_pv.c val = ((pteval_t)pfn << PAGE_SHIFT) | flags; val 346 arch/x86/xen/mmu_pv.c return val; val 349 arch/x86/xen/mmu_pv.c static pteval_t pte_pfn_to_mfn(pteval_t val) val 351 arch/x86/xen/mmu_pv.c if (val & _PAGE_PRESENT) { val 352 arch/x86/xen/mmu_pv.c unsigned long pfn = (val & PTE_PFN_MASK) >> PAGE_SHIFT; val 353 arch/x86/xen/mmu_pv.c pteval_t flags = val & PTE_FLAGS_MASK; val 369 arch/x86/xen/mmu_pv.c val = ((pteval_t)mfn << PAGE_SHIFT) | flags; val 372 arch/x86/xen/mmu_pv.c return val; val 410 arch/x86/xen/mmu_pv.c static void xen_set_pud_hyper(pud_t *ptr, pud_t val) val 420 arch/x86/xen/mmu_pv.c u.val = pud_val_ma(val); val 428 arch/x86/xen/mmu_pv.c static void xen_set_pud(pud_t *ptr, pud_t val) val 430 arch/x86/xen/mmu_pv.c trace_xen_mmu_set_pud(ptr, val); val 435 arch/x86/xen/mmu_pv.c *ptr = val; val 439 arch/x86/xen/mmu_pv.c xen_set_pud_hyper(ptr, val); val 500 arch/x86/xen/mmu_pv.c static void __xen_set_p4d_hyper(p4d_t *ptr, p4d_t val) val 505 arch/x86/xen/mmu_pv.c u.val = p4d_val_ma(val); val 516 arch/x86/xen/mmu_pv.c static void __init xen_set_p4d_hyper(p4d_t *ptr, p4d_t val) val 522 arch/x86/xen/mmu_pv.c __xen_set_p4d_hyper(ptr, val); val 529 arch/x86/xen/mmu_pv.c static void xen_set_p4d(p4d_t *ptr, p4d_t val) val 534 arch/x86/xen/mmu_pv.c trace_xen_mmu_set_p4d(ptr, (p4d_t *)user_ptr, val); val 539 arch/x86/xen/mmu_pv.c *ptr = val; val 542 arch/x86/xen/mmu_pv.c pgd_val.pgd = p4d_val_ma(val); val 552 arch/x86/xen/mmu_pv.c __xen_set_p4d_hyper(ptr, val); val 554 arch/x86/xen/mmu_pv.c __xen_set_p4d_hyper((p4d_t *)user_ptr, val); val 1999 arch/x86/xen/mmu_pv.c unsigned long val; val 2001 arch/x86/xen/mmu_pv.c vaddr = early_memremap_ro(addr, sizeof(val)); val 2002 arch/x86/xen/mmu_pv.c val = *vaddr; val 2003 arch/x86/xen/mmu_pv.c early_memunmap(vaddr, sizeof(val)); val 2004 arch/x86/xen/mmu_pv.c return val; val 2709 arch/x86/xen/mmu_pv.c rmd->mmu_update->val = pte_val_ma(pte); val 189 arch/x86/xen/pmu.c static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type, val 239 arch/x86/xen/pmu.c *val = *reg; val 241 arch/x86/xen/pmu.c *reg = *val; val 244 arch/x86/xen/pmu.c ctxt->global_status &= (~(*val)); val 252 arch/x86/xen/pmu.c static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read) val 284 arch/x86/xen/pmu.c *val = *reg; val 286 arch/x86/xen/pmu.c *reg = *val; val 293 arch/x86/xen/pmu.c bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err) val 297 arch/x86/xen/pmu.c if (!xen_amd_pmu_emulate(msr, val, 1)) val 298 arch/x86/xen/pmu.c *val = native_read_msr_safe(msr, err); val 305 arch/x86/xen/pmu.c if (!xen_intel_pmu_emulate(msr, val, type, index, 1)) val 306 arch/x86/xen/pmu.c *val = native_read_msr_safe(msr, err); val 316 arch/x86/xen/pmu.c uint64_t val = ((uint64_t)high << 32) | low; val 320 arch/x86/xen/pmu.c if (!xen_amd_pmu_emulate(msr, &val, 0)) val 328 arch/x86/xen/pmu.c if (!xen_intel_pmu_emulate(msr, &val, type, index, 0)) val 395 arch/x86/xen/pmu.c int pmu_apic_update(uint32_t val) val 405 arch/x86/xen/pmu.c xenpmu_data->pmu.l.lapic_lvtpc = val; val 539 arch/x86/xen/pmu.c xp.val = pfn_to_mfn(pfn); val 16 arch/x86/xen/pmu.h bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err); val 78 arch/x86/xen/setup.c bool val = false; val 87 arch/x86/xen/setup.c val = true; val 88 arch/x86/xen/setup.c else if (strtobool(arg + strlen("xen_512gb_limit="), &val)) val 91 arch/x86/xen/setup.c xen_512gb_limit = val; val 292 arch/x86/xen/setup.c .val = pfn val 37 arch/x86/xen/spinlock.c static void xen_qlock_wait(u8 *byte, u8 val) val 52 arch/x86/xen/spinlock.c } else if (READ_ONCE(*byte) == val) { val 126 arch/xtensa/include/asm/cmpxchg.h static inline unsigned long xchg_u32(volatile int * m, unsigned long val) val 138 arch/xtensa/include/asm/cmpxchg.h : "a" (val), "a" (m) val 152 arch/xtensa/include/asm/cmpxchg.h : "a" (m), "a" (val) val 165 arch/xtensa/include/asm/cmpxchg.h : "a" (m), "a" (val) val 44 arch/xtensa/include/asm/hw_breakpoint.h unsigned long val, void *data); val 57 arch/xtensa/include/asm/mmu_context.h static inline void set_rasid_register (unsigned long val) val 60 arch/xtensa/include/asm/mmu_context.h " isync\n" : : "a" (val)); val 391 arch/xtensa/include/asm/pgtable.h #define __swp_type(entry) (((entry).val >> 6) & 0x1f) val 392 arch/xtensa/include/asm/pgtable.h #define __swp_offset(entry) ((entry).val >> 11) val 397 arch/xtensa/include/asm/pgtable.h #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) val 52 arch/xtensa/include/asm/syscall.h int error, long val) val 54 arch/xtensa/include/asm/syscall.h regs->areg[2] = (long) error ? error : val; val 105 arch/xtensa/include/asm/tlbflush.h static inline void set_itlbcfg_register (unsigned long val) val 108 arch/xtensa/include/asm/tlbflush.h : : "a" (val)); val 111 arch/xtensa/include/asm/tlbflush.h static inline void set_dtlbcfg_register (unsigned long val) val 114 arch/xtensa/include/asm/tlbflush.h : : "a" (val)); val 117 arch/xtensa/include/asm/tlbflush.h static inline void set_ptevaddr_register (unsigned long val) val 120 arch/xtensa/include/asm/tlbflush.h : : "a" (val)); val 36 arch/xtensa/include/asm/uaccess.h #define set_fs(val) (current->thread.current_ds = (val)) val 86 arch/xtensa/kernel/hw_breakpoint.c unsigned long val, void *data) val 336 arch/xtensa/kernel/ptrace.c static int ptrace_pokeusr(struct task_struct *child, long regno, long val) val 343 arch/xtensa/kernel/ptrace.c regs->areg[regno - REG_AR_BASE] = val; val 347 arch/xtensa/kernel/ptrace.c regs->areg[regno - REG_A_BASE] = val; val 351 arch/xtensa/kernel/ptrace.c regs->pc = val; val 355 arch/xtensa/kernel/ptrace.c regs->syscall = val; val 53 arch/xtensa/platforms/iss/simdisk.c static int simdisk_param_set_filename(const char *val, val 57 arch/xtensa/platforms/iss/simdisk.c filename[n_files++] = val; val 44 block/bfq-cgroup.c static inline void bfq_stat_add(struct bfq_stat *stat, uint64_t val) val 46 block/bfq-cgroup.c percpu_counter_add_batch(&stat->cpu_cnt, val, BLKG_STAT_CPU_BATCH); val 938 block/bfq-cgroup.c unsigned int val = 0; val 941 block/bfq-cgroup.c val = bfqgd->weight; val 943 block/bfq-cgroup.c seq_printf(sf, "%u\n", val); val 1004 block/bfq-cgroup.c u64 val) val 1011 block/bfq-cgroup.c if (val < BFQ_MIN_WEIGHT || val > BFQ_MAX_WEIGHT) val 1016 block/bfq-cgroup.c bfqgd->weight = (unsigned short)val; val 1021 block/bfq-cgroup.c bfq_group_set_weight(bfqg, val, 0); val 463 block/blk-cgroup.c struct cftype *cftype, u64 val) val 273 block/blk-integrity.c unsigned long val = simple_strtoul(p, &p, 10); val 275 block/blk-integrity.c if (val) val 292 block/blk-integrity.c unsigned long val = simple_strtoul(p, &p, 10); val 294 block/blk-integrity.c if (val) val 750 block/blk-iolatency.c static int iolatency_set_min_lat_nsec(struct blkcg_gq *blkg, u64 val) val 755 block/blk-iolatency.c iolat->min_lat_nsec = val; val 756 block/blk-iolatency.c iolat->cur_win_nsec = max_t(u64, val << 4, BLKIOLATENCY_MIN_WIN_SIZE); val 760 block/blk-iolatency.c if (!oldval && val) val 762 block/blk-iolatency.c if (oldval && !val) { val 810 block/blk-iolatency.c char val[21]; /* 18446744073709551616 */ val 812 block/blk-iolatency.c if (sscanf(tok, "%15[^=]=%20s", key, val) != 2) val 818 block/blk-iolatency.c if (!strcmp(val, "max")) val 820 block/blk-iolatency.c else if (sscanf(val, "%llu", &v) == 1) val 264 block/blk-sysfs.c unsigned long val; \ val 266 block/blk-sysfs.c ret = queue_var_store(&val, page, count); \ val 270 block/blk-sysfs.c val = !val; \ val 272 block/blk-sysfs.c if (val) \ val 339 block/blk-sysfs.c unsigned long val; val 341 block/blk-sysfs.c ret = queue_var_store(&val, page, count); val 345 block/blk-sysfs.c if (val == 2) { val 348 block/blk-sysfs.c } else if (val == 1) { val 351 block/blk-sysfs.c } else if (val == 0) { val 361 block/blk-sysfs.c int val; val 364 block/blk-sysfs.c val = BLK_MQ_POLL_CLASSIC; val 366 block/blk-sysfs.c val = q->poll_nsec / 1000; val 368 block/blk-sysfs.c return sprintf(page, "%d\n", val); val 374 block/blk-sysfs.c int err, val; val 379 block/blk-sysfs.c err = kstrtoint(page, 10, &val); val 383 block/blk-sysfs.c if (val == BLK_MQ_POLL_CLASSIC) val 385 block/blk-sysfs.c else if (val >= 0) val 386 block/blk-sysfs.c q->poll_nsec = val * 1000; val 428 block/blk-sysfs.c unsigned int val; val 431 block/blk-sysfs.c err = kstrtou32(page, 10, &val); val 432 block/blk-sysfs.c if (err || val == 0) val 435 block/blk-sysfs.c blk_queue_rq_timeout(q, msecs_to_jiffies(val)); val 453 block/blk-sysfs.c s64 val; val 455 block/blk-sysfs.c ret = queue_var_store64(&val, page); val 458 block/blk-sysfs.c if (val < -1) val 468 block/blk-sysfs.c if (val == -1) val 469 block/blk-sysfs.c val = wbt_default_latency_nsec(q); val 470 block/blk-sysfs.c else if (val >= 0) val 471 block/blk-sysfs.c val *= 1000ULL; val 473 block/blk-sysfs.c if (wbt_get_min_lat(q) == val) val 484 block/blk-sysfs.c wbt_set_min_lat(q, val); val 1613 block/blk-throttle.c u64 val = U64_MAX; val 1625 block/blk-throttle.c if (!p || (sscanf(p, "%llu", &val) != 1 && strcmp(p, "max"))) val 1629 block/blk-throttle.c if (!val) val 1634 block/blk-throttle.c v[0] = val; val 1636 block/blk-throttle.c v[1] = val; val 1638 block/blk-throttle.c v[2] = min_t(u64, val, UINT_MAX); val 1640 block/blk-throttle.c v[3] = min_t(u64, val, UINT_MAX); val 1642 block/blk-throttle.c idle_time = val; val 1644 block/blk-throttle.c latency_time = val; val 54 block/blk-timeout.c int val; val 60 block/blk-timeout.c val = simple_strtoul(p, &p, 10); val 61 block/blk-timeout.c if (val) val 437 block/blk-wbt.c void wbt_set_min_lat(struct request_queue *q, u64 val) val 442 block/blk-wbt.c RQWB(rqos)->min_lat_nsec = val; val 96 block/blk-wbt.h void wbt_set_min_lat(struct request_queue *q, u64 val); val 127 block/blk-wbt.h static inline void wbt_set_min_lat(struct request_queue *q, u64 val) val 18 block/bsg-lib.c #define uptr64(val) ((void __user *)(uintptr_t)(val)) val 55 block/bsg.c #define uptr64(val) ((void __user *)(uintptr_t)(val)) val 15 block/compat_ioctl.c static int compat_put_ushort(unsigned long arg, unsigned short val) val 17 block/compat_ioctl.c return put_user(val, (unsigned short __user *)compat_ptr(arg)); val 20 block/compat_ioctl.c static int compat_put_int(unsigned long arg, int val) val 22 block/compat_ioctl.c return put_user(val, (compat_int_t __user *)compat_ptr(arg)); val 25 block/compat_ioctl.c static int compat_put_uint(unsigned long arg, unsigned int val) val 27 block/compat_ioctl.c return put_user(val, (compat_uint_t __user *)compat_ptr(arg)); val 30 block/compat_ioctl.c static int compat_put_long(unsigned long arg, long val) val 32 block/compat_ioctl.c return put_user(val, (compat_long_t __user *)compat_ptr(arg)); val 35 block/compat_ioctl.c static int compat_put_ulong(unsigned long arg, compat_ulong_t val) val 37 block/compat_ioctl.c return put_user(val, (compat_ulong_t __user *)compat_ptr(arg)); val 40 block/compat_ioctl.c static int compat_put_u64(unsigned long arg, u64 val) val 42 block/compat_ioctl.c return put_user(val, (compat_u64 __user *)compat_ptr(arg)); val 1983 block/genhd.c static int disk_events_set_dfl_poll_msecs(const char *val, val 1989 block/genhd.c ret = param_set_ulong(val, kp); val 268 block/ioctl.c static int put_ushort(unsigned long arg, unsigned short val) val 270 block/ioctl.c return put_user(val, (unsigned short __user *)arg); val 273 block/ioctl.c static int put_int(unsigned long arg, int val) val 275 block/ioctl.c return put_user(val, (int __user *)arg); val 278 block/ioctl.c static int put_uint(unsigned long arg, unsigned int val) val 280 block/ioctl.c return put_user(val, (unsigned int __user *)arg); val 283 block/ioctl.c static int put_long(unsigned long arg, long val) val 285 block/ioctl.c return put_user(val, (long __user *)arg); val 288 block/ioctl.c static int put_ulong(unsigned long arg, unsigned long val) val 290 block/ioctl.c return put_user(val, (unsigned long __user *)arg); val 293 block/ioctl.c static int put_u64(unsigned long arg, u64 val) val 295 block/ioctl.c return put_user(val, (u64 __user *)arg); val 82 block/scsi_ioctl.c int val = min_t(int, q->sg_reserved_size, max_sectors_bytes(q)); val 84 block/scsi_ioctl.c return put_user(val, p); val 247 crypto/api.c int crypto_probing_notify(unsigned long val, void *v) val 251 crypto/api.c ok = blocking_notifier_call_chain(&crypto_chain, val, v); val 254 crypto/api.c ok = blocking_notifier_call_chain(&crypto_chain, val, v); val 94 crypto/asymmetric_keys/public_key.c static u8 *pkey_pack_u32(u8 *dst, u32 val) val 96 crypto/asymmetric_keys/public_key.c memcpy(dst, &val, sizeof(val)); val 97 crypto/asymmetric_keys/public_key.c return dst + sizeof(val); val 36 crypto/dh.c static int _compute_val(const struct dh_ctx *ctx, MPI base, MPI val) val 39 crypto/dh.c return mpi_powm(val, base, ctx->xa, ctx->p); val 125 crypto/dh.c MPI val = mpi_alloc(0); val 128 crypto/dh.c if (!val) val 131 crypto/dh.c ret = mpi_powm(val, y, ctx->q, ctx->p); val 134 crypto/dh.c mpi_free(val); val 138 crypto/dh.c ret = mpi_cmp_ui(val, 1); val 140 crypto/dh.c mpi_free(val); val 153 crypto/dh.c MPI base, val = mpi_alloc(0); val 157 crypto/dh.c if (!val) val 178 crypto/dh.c ret = _compute_val(ctx, base, val); val 182 crypto/dh.c ret = mpi_write_to_sgl(val, req->dst, req->dst_len, &sign); val 192 crypto/dh.c mpi_free(val); val 282 crypto/drbg.c static inline void drbg_cpu_to_be32(__u32 val, unsigned char *buf) val 289 crypto/drbg.c conversion->conv = cpu_to_be32(val); val 81 crypto/internal.h int crypto_probing_notify(unsigned long val, void *v); val 125 crypto/internal.h static inline void crypto_notify(unsigned long val, void *v) val 127 crypto/internal.h blocking_notifier_call_chain(&crypto_chain, val, v); val 28 crypto/michael_mic.c static inline u32 xswap(u32 val) val 30 crypto/michael_mic.c return ((val & 0x00ff00ff) << 8) | ((val & 0xff00ff00) >> 8); val 3311 crypto/testmgr.c __le32 val; val 3340 crypto/testmgr.c err = crypto_shash_final(shash, (u8 *)&val); val 3347 crypto/testmgr.c if (val != cpu_to_le32(~420553207)) { val 3349 crypto/testmgr.c driver, le32_to_cpu(val)); val 3651 crypto/testmgr.c static u8 *test_pack_u32(u8 *dst, u32 val) val 3653 crypto/testmgr.c memcpy(dst, &val, sizeof(val)); val 3654 crypto/testmgr.c return dst + sizeof(val); val 229 drivers/accessibility/braille/braille_console.c unsigned char val = KVAL(param->value); val 232 drivers/accessibility/braille/braille_console.c switch (val) { val 129 drivers/acpi/ac.c union power_supply_propval *val) val 141 drivers/acpi/ac.c val->intval = ac->state; val 135 drivers/acpi/acpi_extlog.c static int extlog_print(struct notifier_block *nb, unsigned long val, val 129 drivers/acpi/acpi_lpss.c u32 val; val 132 drivers/acpi/acpi_lpss.c val = readl(pdata->mmio_base + offset); val 133 drivers/acpi/acpi_lpss.c writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); val 135 drivers/acpi/acpi_lpss.c val = readl(pdata->mmio_base + LPSS_UART_CPR); val 136 drivers/acpi/acpi_lpss.c if (!(val & LPSS_UART_CPR_AFCE)) { val 138 drivers/acpi/acpi_lpss.c val = readl(pdata->mmio_base + offset); val 139 drivers/acpi/acpi_lpss.c val |= LPSS_GENERAL_UART_RTS_OVRD; val 140 drivers/acpi/acpi_lpss.c writel(val, pdata->mmio_base + offset); val 147 drivers/acpi/acpi_lpss.c u32 val; val 150 drivers/acpi/acpi_lpss.c val = readl(pdata->mmio_base + offset); val 151 drivers/acpi/acpi_lpss.c val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; val 152 drivers/acpi/acpi_lpss.c writel(val, pdata->mmio_base + offset); val 720 drivers/acpi/acpi_lpss.c static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, val 723 drivers/acpi/acpi_lpss.c writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); val 726 drivers/acpi/acpi_lpss.c static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) val 747 drivers/acpi/acpi_lpss.c *val = __lpss_reg_read(pdata, reg); val 800 drivers/acpi/acpi_lpss.c static void acpi_lpss_set_ltr(struct device *dev, s32 val) val 806 drivers/acpi/acpi_lpss.c if (val < 0) { val 814 drivers/acpi/acpi_lpss.c if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { val 816 drivers/acpi/acpi_lpss.c val = LPSS_LTR_MAX_VAL; val 817 drivers/acpi/acpi_lpss.c } else if (val > LPSS_LTR_MAX_VAL) { val 819 drivers/acpi/acpi_lpss.c val >>= LPSS_LTR_SNOOP_LAT_SHIFT; val 823 drivers/acpi/acpi_lpss.c ltr_val |= val; val 141 drivers/acpi/acpi_tad.c static char *acpi_tad_rt_next_field(char *s, int *val) val 150 drivers/acpi/acpi_tad.c if (kstrtoint(s, 10, val)) val 161 drivers/acpi/acpi_tad.c int val, ret = -ENODATA; val 167 drivers/acpi/acpi_tad.c s = acpi_tad_rt_next_field(str, &val); val 171 drivers/acpi/acpi_tad.c rt.year = val; val 173 drivers/acpi/acpi_tad.c s = acpi_tad_rt_next_field(s, &val); val 177 drivers/acpi/acpi_tad.c rt.month = val; val 179 drivers/acpi/acpi_tad.c s = acpi_tad_rt_next_field(s, &val); val 183 drivers/acpi/acpi_tad.c rt.day = val; val 185 drivers/acpi/acpi_tad.c s = acpi_tad_rt_next_field(s, &val); val 189 drivers/acpi/acpi_tad.c rt.hour = val; val 191 drivers/acpi/acpi_tad.c s = acpi_tad_rt_next_field(s, &val); val 195 drivers/acpi/acpi_tad.c rt.minute = val; val 197 drivers/acpi/acpi_tad.c s = acpi_tad_rt_next_field(s, &val); val 201 drivers/acpi/acpi_tad.c rt.second = val; val 203 drivers/acpi/acpi_tad.c s = acpi_tad_rt_next_field(s, &val); val 207 drivers/acpi/acpi_tad.c rt.tz = val; val 209 drivers/acpi/acpi_tad.c if (kstrtoint(s, 10, &val)) val 212 drivers/acpi/acpi_tad.c rt.daylight = val; val 1692 drivers/acpi/acpi_video.c unsigned long val, void *ign) val 1698 drivers/acpi/acpi_video.c switch (val) { val 26 drivers/acpi/acpica/acmacros.h #define ACPI_SET8(ptr, val) (*ACPI_CAST8 (ptr) = (u8) (val)) val 27 drivers/acpi/acpica/acmacros.h #define ACPI_SET16(ptr, val) (*ACPI_CAST16 (ptr) = (u16) (val)) val 28 drivers/acpi/acpica/acmacros.h #define ACPI_SET32(ptr, val) (*ACPI_CAST32 (ptr) = (u32) (val)) val 29 drivers/acpi/acpica/acmacros.h #define ACPI_SET64(ptr, val) (*ACPI_CAST64 (ptr) = (u64) (val)) val 319 drivers/acpi/acpica/acmacros.h #define ACPI_REGISTER_PREPARE_BITS(val, pos, mask) \ val 320 drivers/acpi/acpica/acmacros.h ((val << pos) & mask) val 322 drivers/acpi/acpica/acmacros.h #define ACPI_REGISTER_INSERT_VALUE(reg, pos, mask, val) \ val 323 drivers/acpi/acpica/acmacros.h reg = (reg & (~(mask))) | ACPI_REGISTER_PREPARE_BITS(val, pos, mask) val 41 drivers/acpi/acpica/nsaccess.c acpi_string val = NULL; val 125 drivers/acpi/acpica/nsaccess.c if (init_val->val) { val 126 drivers/acpi/acpica/nsaccess.c status = acpi_os_predefined_override(init_val, &val); val 133 drivers/acpi/acpica/nsaccess.c if (!val) { val 134 drivers/acpi/acpica/nsaccess.c val = init_val->val; val 157 drivers/acpi/acpica/nsaccess.c (u8) ACPI_TO_INTEGER(val); val 177 drivers/acpi/acpica/nsaccess.c obj_desc->integer.value = ACPI_TO_INTEGER(val); val 184 drivers/acpi/acpica/nsaccess.c obj_desc->string.length = (u32)strlen(val); val 185 drivers/acpi/acpica/nsaccess.c obj_desc->string.pointer = val; val 193 drivers/acpi/acpica/nsaccess.c (u8) (ACPI_TO_INTEGER(val) - 1); val 57 drivers/acpi/apei/apei-base.c int __apei_exec_read_register(struct acpi_whea_header *entry, u64 *val) val 61 drivers/acpi/apei/apei-base.c rc = apei_read(val, &entry->register_region); val 64 drivers/acpi/apei/apei-base.c *val >>= entry->register_region.bit_offset; val 65 drivers/acpi/apei/apei-base.c *val &= entry->mask; val 74 drivers/acpi/apei/apei-base.c u64 val = 0; val 76 drivers/acpi/apei/apei-base.c rc = __apei_exec_read_register(entry, &val); val 79 drivers/acpi/apei/apei-base.c ctx->value = val; val 99 drivers/acpi/apei/apei-base.c int __apei_exec_write_register(struct acpi_whea_header *entry, u64 val) val 103 drivers/acpi/apei/apei-base.c val &= entry->mask; val 104 drivers/acpi/apei/apei-base.c val <<= entry->register_region.bit_offset; val 111 drivers/acpi/apei/apei-base.c val |= valr; val 113 drivers/acpi/apei/apei-base.c rc = apei_write(val, &entry->register_region); val 640 drivers/acpi/apei/apei-base.c int apei_read(u64 *val, struct acpi_generic_address *reg) val 651 drivers/acpi/apei/apei-base.c *val = 0; val 655 drivers/acpi/apei/apei-base.c val, access_bit_width); val 660 drivers/acpi/apei/apei-base.c status = acpi_os_read_port(address, (u32 *)val, val 674 drivers/acpi/apei/apei-base.c int apei_write(u64 val, struct acpi_generic_address *reg) val 688 drivers/acpi/apei/apei-base.c val, access_bit_width); val 693 drivers/acpi/apei/apei-base.c status = acpi_os_write_port(address, val, access_bit_width); val 80 drivers/acpi/apei/apei-internal.h int apei_read(u64 *val, struct acpi_generic_address *reg); val 81 drivers/acpi/apei/apei-internal.h int apei_write(u64 val, struct acpi_generic_address *reg); val 83 drivers/acpi/apei/apei-internal.h int __apei_exec_read_register(struct acpi_whea_header *entry, u64 *val); val 84 drivers/acpi/apei/apei-internal.h int __apei_exec_write_register(struct acpi_whea_header *entry, u64 val); val 406 drivers/acpi/apei/einj.c u64 val, trigger_paddr, timeout = FIRMWARE_TIMEOUT; val 479 drivers/acpi/apei/einj.c val = apei_exec_ctx_get_output(&ctx); val 480 drivers/acpi/apei/einj.c if (!(val & EINJ_OP_BUSY)) val 488 drivers/acpi/apei/einj.c val = apei_exec_ctx_get_output(&ctx); val 489 drivers/acpi/apei/einj.c if (val != EINJ_STATUS_SUCCESS) val 604 drivers/acpi/apei/einj.c static int error_type_get(void *data, u64 *val) val 606 drivers/acpi/apei/einj.c *val = error_type; val 611 drivers/acpi/apei/einj.c static int error_type_set(void *data, u64 val) val 621 drivers/acpi/apei/einj.c vendor = val & ACPI5_VENDOR_BIT; val 622 drivers/acpi/apei/einj.c tval = val & 0x7fffffff; val 631 drivers/acpi/apei/einj.c if (!(val & available_error_type)) val 634 drivers/acpi/apei/einj.c error_type = val; val 642 drivers/acpi/apei/einj.c static int error_inject_set(void *data, u64 val) val 148 drivers/acpi/apei/erst.c u64 val; val 150 drivers/acpi/apei/erst.c rc = __apei_exec_read_register(entry, &val); val 153 drivers/acpi/apei/erst.c val += ctx->value; val 154 drivers/acpi/apei/erst.c rc = __apei_exec_write_register(entry, val); val 162 drivers/acpi/apei/erst.c u64 val; val 164 drivers/acpi/apei/erst.c rc = __apei_exec_read_register(entry, &val); val 167 drivers/acpi/apei/erst.c val -= ctx->value; val 168 drivers/acpi/apei/erst.c rc = __apei_exec_write_register(entry, val); val 193 drivers/acpi/apei/erst.c u64 val; val 207 drivers/acpi/apei/erst.c rc = __apei_exec_read_register(entry, &val); val 210 drivers/acpi/apei/erst.c if (val != ctx->value) val 223 drivers/acpi/apei/erst.c u64 val; val 225 drivers/acpi/apei/erst.c rc = __apei_exec_read_register(entry, &val); val 228 drivers/acpi/apei/erst.c if (val == ctx->value) { val 625 drivers/acpi/apei/erst.c u64 val; val 643 drivers/acpi/apei/erst.c val = apei_exec_ctx_get_output(&ctx); val 644 drivers/acpi/apei/erst.c if (!val) val 652 drivers/acpi/apei/erst.c val = apei_exec_ctx_get_output(&ctx); val 657 drivers/acpi/apei/erst.c return erst_errno(val); val 664 drivers/acpi/apei/erst.c u64 val; val 686 drivers/acpi/apei/erst.c val = apei_exec_ctx_get_output(&ctx); val 687 drivers/acpi/apei/erst.c if (!val) val 695 drivers/acpi/apei/erst.c val = apei_exec_ctx_get_output(&ctx); val 700 drivers/acpi/apei/erst.c return erst_errno(val); val 707 drivers/acpi/apei/erst.c u64 val; val 725 drivers/acpi/apei/erst.c val = apei_exec_ctx_get_output(&ctx); val 726 drivers/acpi/apei/erst.c if (!val) val 734 drivers/acpi/apei/erst.c val = apei_exec_ctx_get_output(&ctx); val 739 drivers/acpi/apei/erst.c return erst_errno(val); val 204 drivers/acpi/apei/ghes.c u64 val = 0; val 206 drivers/acpi/apei/ghes.c rc = apei_read(&val, &gv2->read_ack_register); val 210 drivers/acpi/apei/ghes.c val &= gv2->read_ack_preserve << gv2->read_ack_register.bit_offset; val 211 drivers/acpi/apei/ghes.c val |= gv2->read_ack_write << gv2->read_ack_register.bit_offset; val 213 drivers/acpi/apei/ghes.c apei_write(val, &gv2->read_ack_register); val 218 drivers/acpi/battery.c union power_supply_propval *val) val 231 drivers/acpi/battery.c val->intval = acpi_battery_handle_discharging(battery); val 233 drivers/acpi/battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 235 drivers/acpi/battery.c val->intval = POWER_SUPPLY_STATUS_FULL; val 237 drivers/acpi/battery.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 240 drivers/acpi/battery.c val->intval = acpi_battery_present(battery); val 243 drivers/acpi/battery.c val->intval = acpi_battery_technology(battery); val 246 drivers/acpi/battery.c val->intval = battery->cycle_count; val 252 drivers/acpi/battery.c val->intval = battery->design_voltage * 1000; val 258 drivers/acpi/battery.c val->intval = battery->voltage_now * 1000; val 265 drivers/acpi/battery.c val->intval = battery->rate_now * 1000; val 272 drivers/acpi/battery.c val->intval = battery->design_capacity * 1000; val 279 drivers/acpi/battery.c val->intval = battery->full_charge_capacity * 1000; val 286 drivers/acpi/battery.c val->intval = battery->capacity_now * 1000; val 298 drivers/acpi/battery.c val->intval = battery->capacity_now * 100/ val 303 drivers/acpi/battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; val 306 drivers/acpi/battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_LOW; val 308 drivers/acpi/battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_FULL; val 310 drivers/acpi/battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; val 313 drivers/acpi/battery.c val->strval = battery->model_number; val 316 drivers/acpi/battery.c val->strval = battery->oem_info; val 319 drivers/acpi/battery.c val->strval = battery->serial_number; val 600 drivers/acpi/button.c static int param_set_lid_init_state(const char *val, val 605 drivers/acpi/button.c if (!strncmp(val, "open", sizeof("open") - 1)) { val 608 drivers/acpi/button.c } else if (!strncmp(val, "method", sizeof("method") - 1)) { val 611 drivers/acpi/button.c } else if (!strncmp(val, "ignore", sizeof("ignore") - 1)) { val 941 drivers/acpi/cppc_acpi.c int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) val 956 drivers/acpi/cppc_acpi.c int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) val 967 drivers/acpi/cppc_acpi.c static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) val 975 drivers/acpi/cppc_acpi.c *val = reg_res->cpc_entry.int_value; val 979 drivers/acpi/cppc_acpi.c *val = 0; val 985 drivers/acpi/cppc_acpi.c return cpc_read_ffh(cpu, reg, val); val 988 drivers/acpi/cppc_acpi.c val, reg->bit_width); val 992 drivers/acpi/cppc_acpi.c *val = readb_relaxed(vaddr); val 995 drivers/acpi/cppc_acpi.c *val = readw_relaxed(vaddr); val 998 drivers/acpi/cppc_acpi.c *val = readl_relaxed(vaddr); val 1001 drivers/acpi/cppc_acpi.c *val = readq_relaxed(vaddr); val 1012 drivers/acpi/cppc_acpi.c static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) val 1024 drivers/acpi/cppc_acpi.c return cpc_write_ffh(cpu, reg, val); val 1027 drivers/acpi/cppc_acpi.c val, reg->bit_width); val 1031 drivers/acpi/cppc_acpi.c writeb_relaxed(val, vaddr); val 1034 drivers/acpi/cppc_acpi.c writew_relaxed(val, vaddr); val 1037 drivers/acpi/cppc_acpi.c writel_relaxed(val, vaddr); val 1040 drivers/acpi/cppc_acpi.c writeq_relaxed(val, vaddr); val 444 drivers/acpi/device_pm.c static void acpi_pm_notify_handler(acpi_handle handle, u32 val, void *not_used) val 448 drivers/acpi/device_pm.c if (val != ACPI_NOTIFY_DEVICE_WAKE) val 26 drivers/acpi/dptf/dptf_power.c unsigned long long val;\ val 30 drivers/acpi/dptf/dptf_power.c NULL, &val);\ val 32 drivers/acpi/dptf/dptf_power.c return sprintf(buf, "%d\n", (int)val);\ val 891 drivers/acpi/ec.c int ec_read(u8 addr, u8 *val) val 902 drivers/acpi/ec.c *val = temp_data; val 909 drivers/acpi/ec.c int ec_write(u8 addr, u8 val) val 916 drivers/acpi/ec.c err = acpi_ec_write(first_ec, addr, val); val 2003 drivers/acpi/ec.c static int param_set_event_clearing(const char *val, val 2008 drivers/acpi/ec.c if (!strncmp(val, "status", sizeof("status") - 1)) { val 2011 drivers/acpi/ec.c } else if (!strncmp(val, "query", sizeof("query") - 1)) { val 2014 drivers/acpi/ec.c } else if (!strncmp(val, "event", sizeof("event") - 1)) { val 67 drivers/acpi/internal.h void acpi_scan_hotplug_enabled(struct acpi_hotplug_profile *hotplug, bool val); val 1280 drivers/acpi/nfit/core.c long val; val 1282 drivers/acpi/nfit/core.c rc = kstrtol(buf, 0, &val); val 1291 drivers/acpi/nfit/core.c switch (val) { val 1352 drivers/acpi/nfit/core.c long val; val 1354 drivers/acpi/nfit/core.c rc = kstrtol(buf, 0, &val); val 1357 drivers/acpi/nfit/core.c if (val != 1) val 13 drivers/acpi/nfit/mce.c static int nfit_handle_mce(struct notifier_block *nb, unsigned long val, val 192 drivers/acpi/numa.c u8 val = slit->entry[d*i + j]; val 194 drivers/acpi/numa.c if (val != LOCAL_DISTANCE) val 196 drivers/acpi/numa.c } else if (val <= LOCAL_DISTANCE) val 20 drivers/acpi/pmic/intel_pmic.c unsigned int val; val 226 drivers/acpi/pmic/intel_pmic.c opregion->ctx.val = *value64 & 0xff; val 231 drivers/acpi/pmic/intel_pmic.c opregion->ctx.val); val 234 drivers/acpi/pmic/intel_pmic.c &opregion->ctx.val); val 236 drivers/acpi/pmic/intel_pmic.c *value64 = opregion->ctx.val; val 288 drivers/acpi/pmic/intel_pmic_bxtwc.c u8 val, mask = bit; val 291 drivers/acpi/pmic/intel_pmic_bxtwc.c val = 0xFF; val 293 drivers/acpi/pmic/intel_pmic_bxtwc.c val = 0x0; val 295 drivers/acpi/pmic/intel_pmic_bxtwc.c return regmap_update_bits(regmap, reg, mask, val); val 300 drivers/acpi/pmic/intel_pmic_bxtwc.c unsigned int val, adc_val, reg_val; val 307 drivers/acpi/pmic/intel_pmic_bxtwc.c if (regmap_read(regmap, reg, &val)) val 309 drivers/acpi/pmic/intel_pmic_bxtwc.c temp_l = (u8) val; val 311 drivers/acpi/pmic/intel_pmic_bxtwc.c if (regmap_read(regmap, (reg - 1), &val)) val 313 drivers/acpi/pmic/intel_pmic_bxtwc.c temp_h = (u8) val; val 354 drivers/acpi/pmic/intel_pmic_bxtwc.c unsigned int val; val 356 drivers/acpi/pmic/intel_pmic_bxtwc.c if (regmap_read(regmap, reg, &val)) val 359 drivers/acpi/pmic/intel_pmic_bxtwc.c *value = (val & mask) >> bit; val 367 drivers/acpi/pmic/intel_pmic_bxtwc.c u8 mask = BIT(bit), val = enable << bit; val 369 drivers/acpi/pmic/intel_pmic_bxtwc.c return regmap_update_bits(regmap, reg, mask, val); val 792 drivers/acpi/property.c enum dev_prop_type proptype, void *val) val 797 drivers/acpi/property.c if (!val) val 809 drivers/acpi/property.c *(u8 *)val = obj->integer.value; val 814 drivers/acpi/property.c *(u16 *)val = obj->integer.value; val 819 drivers/acpi/property.c *(u32 *)val = obj->integer.value; val 822 drivers/acpi/property.c *(u64 *)val = obj->integer.value; val 830 drivers/acpi/property.c *(char **)val = obj->string.pointer; val 840 drivers/acpi/property.c enum dev_prop_type proptype, void *val) val 847 drivers/acpi/property.c ret = acpi_data_prop_read_single(&adev->data, propname, proptype, val); val 853 drivers/acpi/property.c static int acpi_copy_property_array_u8(const union acpi_object *items, u8 *val, val 864 drivers/acpi/property.c val[i] = items[i].integer.value; val 870 drivers/acpi/property.c u16 *val, size_t nval) val 880 drivers/acpi/property.c val[i] = items[i].integer.value; val 886 drivers/acpi/property.c u32 *val, size_t nval) val 896 drivers/acpi/property.c val[i] = items[i].integer.value; val 902 drivers/acpi/property.c u64 *val, size_t nval) val 910 drivers/acpi/property.c val[i] = items[i].integer.value; val 916 drivers/acpi/property.c char **val, size_t nval) val 924 drivers/acpi/property.c val[i] = items[i].string.pointer; val 932 drivers/acpi/property.c void *val, size_t nval) val 938 drivers/acpi/property.c if (val && nval == 1) { val 939 drivers/acpi/property.c ret = acpi_data_prop_read_single(data, propname, proptype, val); val 948 drivers/acpi/property.c if (!val) val 960 drivers/acpi/property.c ret = acpi_copy_property_array_u8(items, (u8 *)val, nval); val 963 drivers/acpi/property.c ret = acpi_copy_property_array_u16(items, (u16 *)val, nval); val 966 drivers/acpi/property.c ret = acpi_copy_property_array_u32(items, (u32 *)val, nval); val 969 drivers/acpi/property.c ret = acpi_copy_property_array_u64(items, (u64 *)val, nval); val 973 drivers/acpi/property.c items, (char **)val, val 984 drivers/acpi/property.c enum dev_prop_type proptype, void *val, size_t nval) val 986 drivers/acpi/property.c return adev ? acpi_data_prop_read(&adev->data, propname, proptype, val, nval) : -EINVAL; val 1003 drivers/acpi/property.c void *val, size_t nval) val 1006 drivers/acpi/property.c propname, proptype, val, nval); val 1200 drivers/acpi/property.c unsigned int val) val 1210 drivers/acpi/property.c if (val == nr) val 1276 drivers/acpi/property.c unsigned int elem_size, void *val, val 1298 drivers/acpi/property.c return acpi_node_prop_read(fwnode, propname, type, val, nval); val 1303 drivers/acpi/property.c const char *propname, const char **val, val 1307 drivers/acpi/property.c val, nval); val 136 drivers/acpi/sbs.c union power_supply_propval *val) val 141 drivers/acpi/sbs.c val->intval = sbs->charger_present; val 164 drivers/acpi/sbs.c union power_supply_propval *val) val 175 drivers/acpi/sbs.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 177 drivers/acpi/sbs.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 179 drivers/acpi/sbs.c val->intval = POWER_SUPPLY_STATUS_FULL; val 182 drivers/acpi/sbs.c val->intval = battery->present; val 185 drivers/acpi/sbs.c val->intval = acpi_battery_technology(battery); val 188 drivers/acpi/sbs.c val->intval = battery->cycle_count; val 191 drivers/acpi/sbs.c val->intval = battery->design_voltage * val 195 drivers/acpi/sbs.c val->intval = battery->voltage_now * val 200 drivers/acpi/sbs.c val->intval = abs(battery->rate_now) * val 202 drivers/acpi/sbs.c val->intval *= (acpi_battery_mode(battery)) ? val 208 drivers/acpi/sbs.c val->intval = abs(battery->rate_avg) * val 210 drivers/acpi/sbs.c val->intval *= (acpi_battery_mode(battery)) ? val 215 drivers/acpi/sbs.c val->intval = battery->state_of_charge; val 219 drivers/acpi/sbs.c val->intval = battery->design_capacity * val 224 drivers/acpi/sbs.c val->intval = battery->full_charge_capacity * val 229 drivers/acpi/sbs.c val->intval = battery->capacity_now * val 233 drivers/acpi/sbs.c val->intval = battery->temp_now - 2730; // dK -> dC val 236 drivers/acpi/sbs.c val->strval = battery->device_name; val 239 drivers/acpi/sbs.c val->strval = battery->manufacturer_name; val 249 drivers/acpi/sbshc.c unsigned long long val; val 255 drivers/acpi/sbshc.c status = acpi_evaluate_integer(device->handle, "_EC", NULL, &val); val 271 drivers/acpi/sbshc.c hc->offset = (val >> 8) & 0xff; val 272 drivers/acpi/sbshc.c hc->query_bit = val & 0xff; val 1776 drivers/acpi/scan.c void acpi_scan_hotplug_enabled(struct acpi_hotplug_profile *hotplug, bool val) val 1778 drivers/acpi/scan.c if (!!hotplug->enabled == !!val) val 1783 drivers/acpi/scan.c hotplug->enabled = val; val 172 drivers/acpi/sysfs.c static int param_set_trace_method_name(const char *val, val 178 drivers/acpi/sysfs.c if (*val != '\\') val 181 drivers/acpi/sysfs.c if ((is_abs_path && strlen(val) > 1023) || val 182 drivers/acpi/sysfs.c (!is_abs_path && strlen(val) > 1022)) { val 200 drivers/acpi/sysfs.c strcpy(trace_method_name, val); val 203 drivers/acpi/sysfs.c strcpy(trace_method_name+1, val); val 234 drivers/acpi/sysfs.c static int param_set_trace_state(const char *val, val 242 drivers/acpi/sysfs.c #define acpi_compare_param(val, key) \ val 243 drivers/acpi/sysfs.c strncmp((val), (key), sizeof(key) - 1) val 245 drivers/acpi/sysfs.c if (!acpi_compare_param(val, "enable")) { val 248 drivers/acpi/sysfs.c } else if (!acpi_compare_param(val, "disable")) val 250 drivers/acpi/sysfs.c else if (!acpi_compare_param(val, "method-once")) val 252 drivers/acpi/sysfs.c else if (!acpi_compare_param(val, "method")) val 254 drivers/acpi/sysfs.c else if (!acpi_compare_param(val, "opcode-once")) val 256 drivers/acpi/sysfs.c else if (!acpi_compare_param(val, "opcode")) val 825 drivers/acpi/sysfs.c static int __init acpi_gpe_set_masked_gpes(char *val) val 829 drivers/acpi/sysfs.c if (kstrtou8(val, 0, &gpe)) val 963 drivers/acpi/sysfs.c unsigned int val; val 965 drivers/acpi/sysfs.c if (kstrtouint(buf, 10, &val) || val > 1) val 968 drivers/acpi/sysfs.c acpi_scan_hotplug_enabled(hotplug, val); val 1018 drivers/acpi/sysfs.c bool val; val 1021 drivers/acpi/sysfs.c ret = strtobool(buf, &val); val 1025 drivers/acpi/sysfs.c if (val) { val 371 drivers/acpi/video_detect.c unsigned long val, void *bd) val 377 drivers/acpi/video_detect.c val == BACKLIGHT_REGISTERED) val 69 drivers/acpi/x86/apple.c union acpi_object *val = &props->package.elements[i * 2 + 1]; val 72 drivers/acpi/x86/apple.c (val->type != ACPI_TYPE_INTEGER && val 73 drivers/acpi/x86/apple.c val->type != ACPI_TYPE_BUFFER)) val 78 drivers/acpi/x86/apple.c if ( val->type == ACPI_TYPE_BUFFER) val 79 drivers/acpi/x86/apple.c newsize += val->buffer.length; val 104 drivers/acpi/x86/apple.c union acpi_object *val = &props->package.elements[i * 2 + 1]; val 118 drivers/acpi/x86/apple.c newprops[v].type = val->type; val 119 drivers/acpi/x86/apple.c if (val->type == ACPI_TYPE_INTEGER) { val 120 drivers/acpi/x86/apple.c newprops[v].integer.value = val->integer.value; val 122 drivers/acpi/x86/apple.c newprops[v].buffer.length = val->buffer.length; val 124 drivers/acpi/x86/apple.c memcpy(free_space, val->buffer.pointer, val 125 drivers/acpi/x86/apple.c val->buffer.length); val 126 drivers/acpi/x86/apple.c free_space += val->buffer.length; val 140 drivers/amba/tegra-ahb.c u32 val; val 147 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); val 148 drivers/amba/tegra-ahb.c val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE; val 149 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL); val 181 drivers/amba/tegra-ahb.c u32 val; val 183 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM); val 184 drivers/amba/tegra-ahb.c val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR; val 185 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM); val 187 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_GIZMO_USB); val 188 drivers/amba/tegra-ahb.c val |= IMMEDIATE; val 189 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_GIZMO_USB); val 191 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_GIZMO_USB2); val 192 drivers/amba/tegra-ahb.c val |= IMMEDIATE; val 193 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_GIZMO_USB2); val 195 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_GIZMO_USB3); val 196 drivers/amba/tegra-ahb.c val |= IMMEDIATE; val 197 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_GIZMO_USB3); val 199 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL); val 200 drivers/amba/tegra-ahb.c val |= PRIORITY_SELECT_USB | val 204 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL); val 206 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1); val 207 drivers/amba/tegra-ahb.c val &= ~MST_ID(~0); val 208 drivers/amba/tegra-ahb.c val |= PREFETCH_ENB | val 212 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1); val 214 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2); val 215 drivers/amba/tegra-ahb.c val &= ~MST_ID(~0); val 216 drivers/amba/tegra-ahb.c val |= PREFETCH_ENB | val 220 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2); val 222 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3); val 223 drivers/amba/tegra-ahb.c val &= ~MST_ID(~0); val 224 drivers/amba/tegra-ahb.c val |= PREFETCH_ENB | val 228 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3); val 230 drivers/amba/tegra-ahb.c val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4); val 231 drivers/amba/tegra-ahb.c val &= ~MST_ID(~0); val 232 drivers/amba/tegra-ahb.c val |= PREFETCH_ENB | val 236 drivers/amba/tegra-ahb.c gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4); val 129 drivers/android/binder.c static int binder_set_stop_on_user_error(const char *val, val 134 drivers/android/binder.c ret = param_set_int(val, kp); val 193 drivers/android/binder_alloc_selftest.c static bool is_dup(int *seq, int index, int val) val 198 drivers/android/binder_alloc_selftest.c if (seq[i] == val) val 771 drivers/ata/ahci.c u16 val; val 792 drivers/ata/ahci.c pci_read_config_word(pdev, 0x92, &val); val 793 drivers/ata/ahci.c val &= ~(1 << port); val 794 drivers/ata/ahci.c pci_write_config_word(pdev, 0x92, val); val 796 drivers/ata/ahci.c val |= 1 << port; val 797 drivers/ata/ahci.c pci_write_config_word(pdev, 0x92, val); val 984 drivers/ata/ahci.c u32 val; val 988 drivers/ata/ahci.c pci_read_config_dword(pdev, 0xf8, &val); val 989 drivers/ata/ahci.c val |= 1 << 0x1b; val 992 drivers/ata/ahci.c pci_write_config_dword(pdev, 0xf8, val); val 994 drivers/ata/ahci.c pci_read_config_dword(pdev, 0x54c, &val); val 995 drivers/ata/ahci.c val |= 1 << 0xc; val 996 drivers/ata/ahci.c pci_write_config_dword(pdev, 0x54c, val); val 998 drivers/ata/ahci.c pci_read_config_dword(pdev, 0x4a4, &val); val 999 drivers/ata/ahci.c val &= 0xff; val 1000 drivers/ata/ahci.c val |= 0x01060100; val 1001 drivers/ata/ahci.c pci_write_config_dword(pdev, 0x4a4, val); val 1003 drivers/ata/ahci.c pci_read_config_dword(pdev, 0x54c, &val); val 1004 drivers/ata/ahci.c val &= ~(1 << 0xc); val 1005 drivers/ata/ahci.c pci_write_config_dword(pdev, 0x54c, val); val 1007 drivers/ata/ahci.c pci_read_config_dword(pdev, 0xf8, &val); val 1008 drivers/ata/ahci.c val &= ~(1 << 0x1b); val 1009 drivers/ata/ahci.c pci_write_config_dword(pdev, 0xf8, val); val 1335 drivers/ata/ahci.c unsigned int val; val 1340 drivers/ata/ahci.c val = (unsigned long)dmi->driver_data; val 1342 drivers/ata/ahci.c return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); val 107 drivers/ata/ahci_brcm.c static inline void brcm_sata_writereg(u32 val, void __iomem *addr) val 111 drivers/ata/ahci_brcm.c __raw_writel(val, addr); val 113 drivers/ata/ahci_brcm.c writel_relaxed(val, addr); val 31 drivers/ata/ahci_da850.c unsigned int val; val 34 drivers/ata/ahci_da850.c val = readl(pwrdn_reg); val 35 drivers/ata/ahci_da850.c val &= ~BIT(0); val 36 drivers/ata/ahci_da850.c writel(val, pwrdn_reg); val 38 drivers/ata/ahci_da850.c val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) | val 41 drivers/ata/ahci_da850.c writel(val, ahci_base + SATA_P0PHYCR_REG); val 65 drivers/ata/ahci_dm816.c u32 val; val 90 drivers/ata/ahci_dm816.c val = AHCI_DM816_PHY_MPY(mpy) | AHCI_DM816_PHY_LOS(1) | val 93 drivers/ata/ahci_dm816.c writel(val, hpriv->mmio + AHCI_DM816_P0PHYCR_REG); val 96 drivers/ata/ahci_dm816.c val = AHCI_DM816_PHY_LOS(1) | AHCI_DM816_PHY_RXCDR(4) | val 98 drivers/ata/ahci_dm816.c writel(val, hpriv->mmio + AHCI_DM816_P1PHYCR_REG); val 163 drivers/ata/ahci_imx.c static int imx_phy_reg_write(u16 val, void __iomem *mmio) val 165 drivers/ata/ahci_imx.c u32 crval = val; val 181 drivers/ata/ahci_imx.c if (val & IMX_CLOCK_RESET_RESET) { val 205 drivers/ata/ahci_imx.c static int imx_phy_reg_read(u16 *val, void __iomem *mmio) val 215 drivers/ata/ahci_imx.c *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT; val 230 drivers/ata/ahci_imx.c u16 val; val 261 drivers/ata/ahci_imx.c ret = imx_phy_reg_read(&val, mmio); val 264 drivers/ata/ahci_imx.c if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE) val 447 drivers/ata/ahci_imx.c u32 val, reg; val 480 drivers/ata/ahci_imx.c IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val); val 481 drivers/ata/ahci_imx.c if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { val 501 drivers/ata/ahci_imx.c if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { val 511 drivers/ata/ahci_imx.c val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET; val 513 drivers/ata/ahci_imx.c val, val 517 drivers/ata/ahci_imx.c val, val 598 drivers/ata/ahci_imx.c regmap_read(imxpriv->gpr, reg, &val); val 599 drivers/ata/ahci_imx.c val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK; val 600 drivers/ata/ahci_imx.c if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK) val 605 drivers/ata/ahci_imx.c if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) { val 88 drivers/ata/ahci_seattle.c u32 val; val 96 drivers/ata/ahci_seattle.c val = ioread32(plat_data->sgpio_ctrl); val 98 drivers/ata/ahci_seattle.c val |= 1 << ACTIVITY_BIT_POS((ap->port_no)); val 100 drivers/ata/ahci_seattle.c val &= ~(1 << ACTIVITY_BIT_POS((ap->port_no))); val 103 drivers/ata/ahci_seattle.c val |= 1 << LOCATE_BIT_POS((ap->port_no)); val 105 drivers/ata/ahci_seattle.c val &= ~(1 << LOCATE_BIT_POS((ap->port_no))); val 108 drivers/ata/ahci_seattle.c val |= 1 << FAULT_BIT_POS((ap->port_no)); val 110 drivers/ata/ahci_seattle.c val &= ~(1 << FAULT_BIT_POS((ap->port_no))); val 112 drivers/ata/ahci_seattle.c iowrite32(val, plat_data->sgpio_ctrl); val 129 drivers/ata/ahci_seattle.c u32 val; val 140 drivers/ata/ahci_seattle.c val = ioread32(plat_data->sgpio_ctrl); val 142 drivers/ata/ahci_seattle.c if (!(val & 0xf)) val 180 drivers/ata/ahci_tegra.c u32 val; val 183 drivers/ata/ahci_tegra.c val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); val 184 drivers/ata/ahci_tegra.c val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT; val 185 drivers/ata/ahci_tegra.c writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); val 194 drivers/ata/ahci_tegra.c u32 val; val 197 drivers/ata/ahci_tegra.c ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val); val 201 drivers/ata/ahci_tegra.c calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK]; val 205 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + val 207 drivers/ata/ahci_tegra.c val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK; val 208 drivers/ata/ahci_tegra.c val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK; val 209 drivers/ata/ahci_tegra.c val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; val 210 drivers/ata/ahci_tegra.c val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; val 211 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + val 214 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + val 216 drivers/ata/ahci_tegra.c val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK; val 217 drivers/ata/ahci_tegra.c val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK; val 218 drivers/ata/ahci_tegra.c val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; val 219 drivers/ata/ahci_tegra.c val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; val 220 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + val 292 drivers/ata/ahci_tegra.c u32 val; val 305 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SATA_FPCI_BAR5); val 306 drivers/ata/ahci_tegra.c val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE); val 307 drivers/ata/ahci_tegra.c val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE; val 308 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SATA_FPCI_BAR5); val 311 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SATA_CONFIGURATION_0); val 312 drivers/ata/ahci_tegra.c val |= SATA_CONFIGURATION_0_EN_FPCI; val 313 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); val 316 drivers/ata/ahci_tegra.c val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1; val 317 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0); val 318 drivers/ata/ahci_tegra.c val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2; val 319 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0); val 320 drivers/ata/ahci_tegra.c val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1; val 321 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0); val 322 drivers/ata/ahci_tegra.c val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2; val 323 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0); val 327 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0); val 328 drivers/ata/ahci_tegra.c val |= T_SATA_CFG_PHY_0_MASK_SQUELCH; val 329 drivers/ata/ahci_tegra.c val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD; val 330 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0); val 332 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB); val 333 drivers/ata/ahci_tegra.c val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK | val 336 drivers/ata/ahci_tegra.c val |= (T_SATA0_NVOOB_COMMA_CNT | val 339 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB); val 344 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2); val 345 drivers/ata/ahci_tegra.c val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK; val 346 drivers/ata/ahci_tegra.c val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW; val 347 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2); val 356 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1); val 357 drivers/ata/ahci_tegra.c val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE | val 359 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1); val 360 drivers/ata/ahci_tegra.c val = T_SATA0_CFG_9_BASE_ADDRESS; val 361 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9); val 364 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); val 365 drivers/ata/ahci_tegra.c val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; val 366 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); val 368 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); val 369 drivers/ata/ahci_tegra.c val &= val 372 drivers/ata/ahci_tegra.c val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF; val 373 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); val 375 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); val 376 drivers/ata/ahci_tegra.c val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; val 377 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); val 380 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR); val 381 drivers/ata/ahci_tegra.c val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP | val 385 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR); val 391 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35); val 392 drivers/ata/ahci_tegra.c val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK; val 393 drivers/ata/ahci_tegra.c val |= T_SATA0_CFG_35_IDP_INDEX; val 394 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35); val 396 drivers/ata/ahci_tegra.c val = T_SATA0_AHCI_IDP1_DATA; val 397 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1); val 399 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1); val 400 drivers/ata/ahci_tegra.c val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN | val 402 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1); val 405 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SATA_CONFIGURATION_0); val 406 drivers/ata/ahci_tegra.c val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE; val 407 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); val 413 drivers/ata/ahci_tegra.c val = readl(tegra->sata_regs + SATA_INTR_MASK); val 414 drivers/ata/ahci_tegra.c val |= SATA_INTR_MASK_IP_INT_MASK; val 415 drivers/ata/ahci_tegra.c writel(val, tegra->sata_regs + SATA_INTR_MASK); val 114 drivers/ata/ahci_xgene.c int val, unsigned long interval, val 123 drivers/ata/ahci_xgene.c while (tmp != val && time_before(jiffies, deadline)) { val 270 drivers/ata/ahci_xgene.c u32 val; val 274 drivers/ata/ahci_xgene.c val = readl(mmio + PORTCFG); val 275 drivers/ata/ahci_xgene.c val = PORTADDR_SET(val, channel == 0 ? 2 : 3); val 276 drivers/ata/ahci_xgene.c writel(val, mmio + PORTCFG); val 288 drivers/ata/ahci_xgene.c val = readl(mmio + PORTPHY5CFG); val 289 drivers/ata/ahci_xgene.c val = PORTPHY5CFG_RTCHG_SET(val, 0x300); val 290 drivers/ata/ahci_xgene.c writel(val, mmio + PORTPHY5CFG); val 292 drivers/ata/ahci_xgene.c val = readl(mmio + PORTAXICFG); val 293 drivers/ata/ahci_xgene.c val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */ val 294 drivers/ata/ahci_xgene.c val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */ val 295 drivers/ata/ahci_xgene.c writel(val, mmio + PORTAXICFG); val 298 drivers/ata/ahci_xgene.c val = readl(mmio + PORTRANSCFG); val 299 drivers/ata/ahci_xgene.c val = PORTRANSCFG_RXWM_SET(val, 0x30); val 300 drivers/ata/ahci_xgene.c writel(val, mmio + PORTRANSCFG); val 363 drivers/ata/ahci_xgene.c u32 val, sstatus; val 373 drivers/ata/ahci_xgene.c val = readl(port_mmio + PORT_SCR_ERR); val 374 drivers/ata/ahci_xgene.c if (val & (SERR_DISPARITY | SERR_10B_8B_ERR)) val 384 drivers/ata/ahci_xgene.c val = readl(port_mmio + PORT_SCR_ERR); val 385 drivers/ata/ahci_xgene.c writel(val, port_mmio + PORT_SCR_ERR); val 656 drivers/ata/ahci_xgene.c u32 val; val 670 drivers/ata/ahci_xgene.c val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */ val 672 drivers/ata/ahci_xgene.c INTSTATUSMASK, val); val 686 drivers/ata/ahci_xgene.c val = readl(ctx->csr_core + BUSCTLREG); val 687 drivers/ata/ahci_xgene.c val &= ~0x00000002; /* Enable write coherency */ val 688 drivers/ata/ahci_xgene.c val &= ~0x00000001; /* Enable read coherency */ val 689 drivers/ata/ahci_xgene.c writel(val, ctx->csr_core + BUSCTLREG); val 691 drivers/ata/ahci_xgene.c val = readl(ctx->csr_core + IOFMSTRWAUX); val 692 drivers/ata/ahci_xgene.c val |= (1 << 3); /* Enable read coherency */ val 693 drivers/ata/ahci_xgene.c val |= (1 << 9); /* Enable write coherency */ val 694 drivers/ata/ahci_xgene.c writel(val, ctx->csr_core + IOFMSTRWAUX); val 695 drivers/ata/ahci_xgene.c val = readl(ctx->csr_core + IOFMSTRWAUX); val 697 drivers/ata/ahci_xgene.c IOFMSTRWAUX, val); val 704 drivers/ata/ahci_xgene.c u32 val; val 710 drivers/ata/ahci_xgene.c val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG); val 711 drivers/ata/ahci_xgene.c val &= ~CFG_SATA_ENET_SELECT_MASK; val 712 drivers/ata/ahci_xgene.c writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG); val 713 drivers/ata/ahci_xgene.c val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG); val 714 drivers/ata/ahci_xgene.c return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0; val 786 drivers/ata/ata_piix.c unsigned int reg, u32 *val) val 794 drivers/ata/ata_piix.c *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); val 799 drivers/ata/ata_piix.c unsigned int reg, u32 val) val 807 drivers/ata/ata_piix.c iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); val 55 drivers/ata/libahci.c static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); val 56 drivers/ata/libahci.c static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); val 83 drivers/ata/libahci.c enum sw_activity val); val 593 drivers/ata/libahci.c static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) val 599 drivers/ata/libahci.c *val = readl(port_mmio + offset); val 605 drivers/ata/libahci.c static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) val 611 drivers/ata/libahci.c writel(val, port_mmio + offset); val 1153 drivers/ata/libahci.c static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) val 1162 drivers/ata/libahci.c if (val == OFF) { val 1172 drivers/ata/libahci.c if (val == BLINK_OFF) { val 1180 drivers/ata/libahci.c emp->blink_policy = val; val 5518 drivers/ata/libata-core.c int sata_scr_read(struct ata_link *link, int reg, u32 *val) val 5522 drivers/ata/libata-core.c return link->ap->ops->scr_read(link, reg, val); val 5526 drivers/ata/libata-core.c return sata_pmp_scr_read(link, reg, val); val 5545 drivers/ata/libata-core.c int sata_scr_write(struct ata_link *link, int reg, u32 val) val 5549 drivers/ata/libata-core.c return link->ap->ops->scr_write(link, reg, val); val 5553 drivers/ata/libata-core.c return sata_pmp_scr_write(link, reg, val); val 5571 drivers/ata/libata-core.c int sata_scr_write_flush(struct ata_link *link, int reg, u32 val) val 5577 drivers/ata/libata-core.c rc = link->ap->ops->scr_write(link, reg, val); val 5579 drivers/ata/libata-core.c rc = link->ap->ops->scr_read(link, reg, &val); val 5585 drivers/ata/libata-core.c return sata_pmp_scr_write(link, reg, val); val 6816 drivers/ata/libata-core.c return (tmp == bits->val) ? 1 : 0; val 6955 drivers/ata/libata-core.c char *id, *val, *endp; val 6973 drivers/ata/libata-core.c val = strstrip(start); val 6979 drivers/ata/libata-core.c val = strstrip(p + 1); val 7003 drivers/ata/libata-core.c if (strncasecmp(val, fp->name, strlen(val))) val 7009 drivers/ata/libata-core.c if (strcasecmp(val, fp->name) == 0) { val 7175 drivers/ata/libata-core.c u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, u32 val, val 7189 drivers/ata/libata-core.c while ((tmp & mask) == val && time_before(jiffies, deadline)) { val 75 drivers/ata/libata-pmp.c static unsigned int sata_pmp_write(struct ata_link *link, int reg, u32 val) val 87 drivers/ata/libata-pmp.c tf.nsect = val & 0xff; val 88 drivers/ata/libata-pmp.c tf.lbal = (val >> 8) & 0xff; val 89 drivers/ata/libata-pmp.c tf.lbam = (val >> 16) & 0xff; val 90 drivers/ata/libata-pmp.c tf.lbah = (val >> 24) & 0xff; val 172 drivers/ata/libata-pmp.c int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val) val 179 drivers/ata/libata-pmp.c err_mask = sata_pmp_write(link, reg, val); val 445 drivers/ata/libata-scsi.c enum sw_activity val; val 450 drivers/ata/libata-scsi.c val = simple_strtoul(buf, NULL, 0); val 451 drivers/ata/libata-scsi.c switch (val) { val 453 drivers/ata/libata-scsi.c rc = ap->ops->sw_activity_store(atadev, val); val 767 drivers/ata/libata-scsi.c unsigned long val; val 774 drivers/ata/libata-scsi.c val = ata_ioc32(ap); val 776 drivers/ata/libata-scsi.c return put_user(val, (unsigned long __user *)arg); val 779 drivers/ata/libata-scsi.c val = (unsigned long) arg; val 783 drivers/ata/libata-scsi.c if (val) val 788 drivers/ata/libata-scsi.c if (val != ata_ioc32(ap)) val 170 drivers/ata/libata.h extern int sata_pmp_scr_read(struct ata_link *link, int reg, u32 *val); val 171 drivers/ata/libata.h extern int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val); val 176 drivers/ata/libata.h static inline int sata_pmp_scr_read(struct ata_link *link, int reg, u32 *val) val 181 drivers/ata/libata.h static inline int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val) val 256 drivers/ata/pata_arasan_cf.c u32 val = readl(acdev->vbase + IRQ_EN); val 260 drivers/ata/pata_arasan_cf.c writel(val | mask, acdev->vbase + IRQ_EN); val 262 drivers/ata/pata_arasan_cf.c writel(val & ~mask, acdev->vbase + IRQ_EN); val 267 drivers/ata/pata_arasan_cf.c u32 val = readl(acdev->vbase + OP_MODE); val 269 drivers/ata/pata_arasan_cf.c writel(val | CARD_RESET, acdev->vbase + OP_MODE); val 271 drivers/ata/pata_arasan_cf.c writel(val & ~CARD_RESET, acdev->vbase + OP_MODE); val 286 drivers/ata/pata_arasan_cf.c u32 val = readl(acdev->vbase + CFI_STS); val 289 drivers/ata/pata_arasan_cf.c if (!(val & (CARD_DETECT1 | CARD_DETECT2))) { val 725 drivers/ata/pata_arasan_cf.c u32 val; val 734 drivers/ata/pata_arasan_cf.c val = readl(acdev->vbase + OP_MODE) & val 736 drivers/ata/pata_arasan_cf.c writel(val, acdev->vbase + OP_MODE); val 737 drivers/ata/pata_arasan_cf.c val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK; val 738 drivers/ata/pata_arasan_cf.c val |= pio << TRUEIDE_PIO_TIMING_SHIFT; val 739 drivers/ata/pata_arasan_cf.c writel(val, acdev->vbase + TM_CFG); val 86 drivers/ata/pata_cs5536.c static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val) val 91 drivers/ata/pata_cs5536.c rdmsr(MSR_IDE_CFG + reg, *val, dummy); val 95 drivers/ata/pata_cs5536.c return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val); val 98 drivers/ata/pata_cs5536.c static int cs5536_write(struct pci_dev *pdev, int reg, int val) val 101 drivers/ata/pata_cs5536.c wrmsr(MSR_IDE_CFG + reg, val, 0); val 105 drivers/ata/pata_cs5536.c return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val); val 180 drivers/ata/pata_ep93xx.c int val; val 183 drivers/ata/pata_ep93xx.c val = 3; val 185 drivers/ata/pata_ep93xx.c val = 2; val 187 drivers/ata/pata_ep93xx.c val = 1; val 189 drivers/ata/pata_ep93xx.c return val << IDECFG_WST_SHIFT; val 774 drivers/ata/pata_ep93xx.c u32 val = readl(drv_data->ide_base + IDEUDMASTS); val 789 drivers/ata/pata_ep93xx.c if (val & IDEUDMASTS_NDO || val & IDEUDMASTS_NDI || val 790 drivers/ata/pata_ep93xx.c val & IDEUDMASTS_N4X || val & IDEUDMASTS_INTIDE) val 797 drivers/ata/pata_ep93xx.c if (val & IDEUDMASTS_SBUSY || val & IDEUDMASTS_DMAIDE) val 88 drivers/ata/pata_imx.c u32 val; val 92 drivers/ata/pata_imx.c val = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL); val 94 drivers/ata/pata_imx.c val |= PATA_IMX_ATA_CTRL_IORDY_EN; val 96 drivers/ata/pata_imx.c val &= ~PATA_IMX_ATA_CTRL_IORDY_EN; val 97 drivers/ata/pata_imx.c __raw_writel(val, priv->host_regs + PATA_IMX_ATA_CONTROL); val 753 drivers/ata/pata_legacy.c static void winbond_writecfg(unsigned long port, u8 reg, u8 val) val 758 drivers/ata/pata_legacy.c outb(val, port + 0x02); val 764 drivers/ata/pata_legacy.c u8 val; val 769 drivers/ata/pata_legacy.c val = inb(port + 0x02); val 772 drivers/ata/pata_legacy.c return val; val 76 drivers/ata/pata_octeon_cf.c unsigned int val; val 82 drivers/ata/pata_octeon_cf.c val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000), val 85 drivers/ata/pata_octeon_cf.c return val; val 81 drivers/ata/pata_opti.c static void opti_write_reg(struct ata_port *ap, u8 val, int reg) val 91 drivers/ata/pata_opti.c iowrite8(val, regio + reg); val 223 drivers/ata/pata_sil680.c u8 val; val 225 drivers/ata/pata_sil680.c pci_read_config_byte(pdev, addr, &val); val 227 drivers/ata/pata_sil680.c return val & 0x08; val 143 drivers/ata/pata_sl82c105.c u16 val; val 145 drivers/ata/pata_sl82c105.c pci_read_config_word(pdev, 0x7E, &val); val 146 drivers/ata/pata_sl82c105.c pci_write_config_word(pdev, 0x7E, val | 4); val 147 drivers/ata/pata_sl82c105.c pci_write_config_word(pdev, 0x7E, val & ~4); val 234 drivers/ata/pata_sl82c105.c u32 val, mask = ap->port_no ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; val 236 drivers/ata/pata_sl82c105.c pci_read_config_dword(pdev, 0x40, &val); val 238 drivers/ata/pata_sl82c105.c return val & mask; val 295 drivers/ata/pata_sl82c105.c u32 val; val 297 drivers/ata/pata_sl82c105.c pci_read_config_dword(pdev, 0x40, &val); val 298 drivers/ata/pata_sl82c105.c val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; val 299 drivers/ata/pata_sl82c105.c pci_write_config_dword(pdev, 0x40, val); val 404 drivers/ata/sata_dwc_460ex.c static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val) val 412 drivers/ata/sata_dwc_460ex.c *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4)); val 414 drivers/ata/sata_dwc_460ex.c link->ap->print_id, scr, *val); val 419 drivers/ata/sata_dwc_460ex.c static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val) val 422 drivers/ata/sata_dwc_460ex.c link->ap->print_id, scr, val); val 428 drivers/ata/sata_dwc_460ex.c sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val); val 435 drivers/ata/sata_dwc_460ex.c u32 val; val 436 drivers/ata/sata_dwc_460ex.c sata_dwc_scr_read(&ap->link, SCR_ERROR, &val); val 437 drivers/ata/sata_dwc_460ex.c sata_dwc_scr_write(&ap->link, SCR_ERROR, val); val 597 drivers/ata/sata_fsl.c unsigned int sc_reg_in, u32 val) val 616 drivers/ata/sata_fsl.c iowrite32(val, ssr_base + (sc_reg * 4)); val 621 drivers/ata/sata_fsl.c unsigned int sc_reg_in, u32 *val) val 640 drivers/ata/sata_fsl.c *val = ioread32(ssr_base + (sc_reg * 4)); val 156 drivers/ata/sata_gemini.c u32 val; val 159 drivers/ata/sata_gemini.c val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; val 162 drivers/ata/sata_gemini.c val |= GEMINI_SATA_CTRL_SLAVE_EN; val 163 drivers/ata/sata_gemini.c writel(val, sg->base + GEMINI_SATA0_CTRL); val 165 drivers/ata/sata_gemini.c val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; val 168 drivers/ata/sata_gemini.c val |= GEMINI_SATA_CTRL_SLAVE_EN; val 169 drivers/ata/sata_gemini.c writel(val, sg->base + GEMINI_SATA1_CTRL); val 180 drivers/ata/sata_gemini.c val = readl(sg->base + GEMINI_SATA0_STATUS); val 182 drivers/ata/sata_gemini.c val = readl(sg->base + GEMINI_SATA1_STATUS); val 183 drivers/ata/sata_gemini.c if (val & GEMINI_SATA_STATUS_PHY_READY) val 187 drivers/ata/sata_gemini.c bridge_online = !!(val & GEMINI_SATA_STATUS_PHY_READY); val 268 drivers/ata/sata_highbank.c static void cphy_override_tx_attenuation(u8 sata_port, u32 val) val 273 drivers/ata/sata_highbank.c if (val & 0x8) val 283 drivers/ata/sata_highbank.c tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN; val 287 drivers/ata/sata_highbank.c static void cphy_override_rx_mode(u8 sata_port, u32 val) val 299 drivers/ata/sata_highbank.c tmp |= val << CPHY_SATA_DPLL_SHIFT; val 291 drivers/ata/sata_inic162x.c static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) val 298 drivers/ata/sata_inic162x.c *val = readl(scr_addr + scr_map[sc_reg] * 4); val 302 drivers/ata/sata_inic162x.c *val &= ~SERR_PHYRDY_CHG; val 306 drivers/ata/sata_inic162x.c static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) val 313 drivers/ata/sata_inic162x.c writel(val, scr_addr + scr_map[sc_reg] * 4); val 757 drivers/ata/sata_inic162x.c u16 val; val 769 drivers/ata/sata_inic162x.c val = readw(mmio_base + HOST_CTL); val 770 drivers/ata/sata_inic162x.c if (!(val & HCTL_SOFTRST)) val 774 drivers/ata/sata_inic162x.c if (val & HCTL_SOFTRST) val 787 drivers/ata/sata_inic162x.c val = readw(mmio_base + HOST_IRQ_MASK); val 788 drivers/ata/sata_inic162x.c val &= ~(HIRQ_PORT0 | HIRQ_PORT1); val 789 drivers/ata/sata_inic162x.c writew(val, mmio_base + HOST_IRQ_MASK); val 588 drivers/ata/sata_mv.c static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); val 589 drivers/ata/sata_mv.c static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); val 590 drivers/ata/sata_mv.c static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); val 591 drivers/ata/sata_mv.c static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); val 1345 drivers/ata/sata_mv.c static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) val 1350 drivers/ata/sata_mv.c *val = readl(mv_ap_base(link->ap) + ofs); val 1356 drivers/ata/sata_mv.c static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) val 1377 drivers/ata/sata_mv.c if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) val 1378 drivers/ata/sata_mv.c val |= 0xf000; val 1391 drivers/ata/sata_mv.c if ((val & 0xf0) != 0x10) val 1399 drivers/ata/sata_mv.c writelfl(val, addr); val 3053 drivers/ata/sata_mv.c static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) val 3061 drivers/ata/sata_mv.c *val = readl(addr + ofs); val 3067 drivers/ata/sata_mv.c static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) val 3075 drivers/ata/sata_mv.c writelfl(val, addr + ofs); val 289 drivers/ata/sata_nv.c static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); val 290 drivers/ata/sata_nv.c static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); val 1508 drivers/ata/sata_nv.c static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) val 1513 drivers/ata/sata_nv.c *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg * 4)); val 1517 drivers/ata/sata_nv.c static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) val 1522 drivers/ata/sata_nv.c iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); val 137 drivers/ata/sata_promise.c static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); val 138 drivers/ata/sata_promise.c static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); val 468 drivers/ata/sata_promise.c unsigned int sc_reg, u32 *val) val 472 drivers/ata/sata_promise.c *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); val 477 drivers/ata/sata_promise.c unsigned int sc_reg, u32 val) val 481 drivers/ata/sata_promise.c writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); val 98 drivers/ata/sata_qstor.c static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); val 99 drivers/ata/sata_qstor.c static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); val 214 drivers/ata/sata_qstor.c static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) val 218 drivers/ata/sata_qstor.c *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8)); val 228 drivers/ata/sata_qstor.c static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) val 232 drivers/ata/sata_qstor.c writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8)); val 171 drivers/ata/sata_rcar.c u32 val, int group) val 181 drivers/ata/sata_rcar.c iowrite32(val, base + SATAPHYWDATA_REG); val 189 drivers/ata/sata_rcar.c val = ioread32(base + SATAPHYACK_REG); val 190 drivers/ata/sata_rcar.c if (val & SATAPHYACK_PHYACK) val 508 drivers/ata/sata_rcar.c u32 *val) val 513 drivers/ata/sata_rcar.c *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); val 518 drivers/ata/sata_rcar.c u32 val) val 523 drivers/ata/sata_rcar.c iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); val 789 drivers/ata/sata_rcar.c u32 val; val 792 drivers/ata/sata_rcar.c val = ioread32(base + ATAPI_CONTROL1_REG); val 793 drivers/ata/sata_rcar.c val |= ATAPI_CONTROL1_RESET; val 794 drivers/ata/sata_rcar.c iowrite32(val, base + ATAPI_CONTROL1_REG); val 797 drivers/ata/sata_rcar.c val = ioread32(base + ATAPI_CONTROL1_REG); val 798 drivers/ata/sata_rcar.c val |= ATAPI_CONTROL1_ISM; val 799 drivers/ata/sata_rcar.c val |= ATAPI_CONTROL1_DESE; val 800 drivers/ata/sata_rcar.c val |= ATAPI_CONTROL1_DTA32M; val 801 drivers/ata/sata_rcar.c iowrite32(val, base + ATAPI_CONTROL1_REG); val 804 drivers/ata/sata_rcar.c val = ioread32(base + ATAPI_CONTROL1_REG); val 805 drivers/ata/sata_rcar.c val &= ~ATAPI_CONTROL1_RESET; val 806 drivers/ata/sata_rcar.c iowrite32(val, base + ATAPI_CONTROL1_REG); val 103 drivers/ata/sata_sil.c static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); val 104 drivers/ata/sata_sil.c static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); val 396 drivers/ata/sata_sil.c static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) val 401 drivers/ata/sata_sil.c *val = readl(mmio); val 407 drivers/ata/sata_sil.c static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) val 412 drivers/ata/sata_sil.c writel(val, mmio); val 326 drivers/ata/sata_sil24.c static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val); val 327 drivers/ata/sata_sil24.c static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val); val 497 drivers/ata/sata_sil24.c static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) val 502 drivers/ata/sata_sil24.c *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4); val 508 drivers/ata/sata_sil24.c static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) val 513 drivers/ata/sata_sil24.c writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); val 50 drivers/ata/sata_sis.c static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); val 51 drivers/ata/sata_sis.c static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); val 129 drivers/ata/sata_sis.c unsigned int sc_reg, u32 *val) val 137 drivers/ata/sata_sis.c pci_read_config_dword(pdev, cfg_addr, val); val 142 drivers/ata/sata_sis.c unsigned int sc_reg, u32 val) val 147 drivers/ata/sata_sis.c pci_write_config_dword(pdev, cfg_addr, val); val 151 drivers/ata/sata_sis.c static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) val 160 drivers/ata/sata_sis.c return sis_scr_cfg_read(link, sc_reg, val); val 162 drivers/ata/sata_sis.c *val = ioread32(base + sc_reg * 4); val 166 drivers/ata/sata_sis.c static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) val 175 drivers/ata/sata_sis.c return sis_scr_cfg_write(link, sc_reg, val); val 177 drivers/ata/sata_sis.c iowrite32(val, base + (sc_reg * 4)); val 186 drivers/ata/sata_sis.c u32 genctl, val; val 242 drivers/ata/sata_sis.c pci_read_config_dword(pdev, 0x6C, &val); val 243 drivers/ata/sata_sis.c if (val & (1L << 31)) { val 106 drivers/ata/sata_svw.c unsigned int sc_reg, u32 *val) val 110 drivers/ata/sata_svw.c *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); val 116 drivers/ata/sata_svw.c unsigned int sc_reg, u32 val) val 120 drivers/ata/sata_svw.c writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); val 44 drivers/ata/sata_uli.c static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); val 45 drivers/ata/sata_uli.c static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); val 97 drivers/ata/sata_uli.c u32 val; val 99 drivers/ata/sata_uli.c pci_read_config_dword(pdev, cfg_addr, &val); val 100 drivers/ata/sata_uli.c return val; val 103 drivers/ata/sata_uli.c static void uli_scr_cfg_write(struct ata_link *link, unsigned int scr, u32 val) val 108 drivers/ata/sata_uli.c pci_write_config_dword(pdev, cfg_addr, val); val 111 drivers/ata/sata_uli.c static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) val 116 drivers/ata/sata_uli.c *val = uli_scr_cfg_read(link, sc_reg); val 120 drivers/ata/sata_uli.c static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) val 125 drivers/ata/sata_uli.c uli_scr_cfg_write(link, sc_reg, val); val 73 drivers/ata/sata_via.c static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); val 74 drivers/ata/sata_via.c static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); val 75 drivers/ata/sata_via.c static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val); val 76 drivers/ata/sata_via.c static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val); val 185 drivers/ata/sata_via.c static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) val 189 drivers/ata/sata_via.c *val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg)); val 193 drivers/ata/sata_via.c static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) val 197 drivers/ata/sata_via.c iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg)); val 201 drivers/ata/sata_via.c static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val) val 246 drivers/ata/sata_via.c *val = v; val 250 drivers/ata/sata_via.c static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val) val 260 drivers/ata/sata_via.c pci_write_config_dword(pdev, 0xB0 + slot * 4, val); val 265 drivers/ata/sata_via.c v |= ((val & 0x4) >> 1) | (val & 0x1); val 268 drivers/ata/sata_via.c v |= ((val >> 8) & 0x3) << 2; val 85 drivers/ata/sata_vsc.c unsigned int sc_reg, u32 *val) val 89 drivers/ata/sata_vsc.c *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); val 95 drivers/ata/sata_vsc.c unsigned int sc_reg, u32 val) val 99 drivers/ata/sata_vsc.c writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); val 240 drivers/atm/firestream.c int reg, val; val 564 drivers/atm/firestream.c static inline void write_fs (struct fs_dev *dev, int offset, u32 val) val 566 drivers/atm/firestream.c writel (val, dev->base + offset); val 1314 drivers/atm/firestream.c static void write_phy(struct fs_dev *dev, int regnum, int val) val 1317 drivers/atm/firestream.c regnum, val, 0); val 1328 drivers/atm/firestream.c for (i=0;i<reginit->val;i++) { val 1332 drivers/atm/firestream.c write_phy (dev, reginit->reg, reginit->val); val 242 drivers/atm/fore200e.c fore200e_poll(struct fore200e* fore200e, volatile u32* addr, u32 val, int msecs) val 249 drivers/atm/fore200e.c if ((ok = (*addr == val)) || (*addr & STATUS_ERROR)) val 257 drivers/atm/fore200e.c *addr, val); val 266 drivers/atm/fore200e.c fore200e_io_poll(struct fore200e* fore200e, volatile u32 __iomem *addr, u32 val, int msecs) val 272 drivers/atm/fore200e.c if ((ok = (fore200e->bus->read(addr) == val))) val 280 drivers/atm/fore200e.c fore200e->bus->read(addr), val); val 443 drivers/atm/fore200e.c static void fore200e_pca_write(u32 val, volatile u32 __iomem *addr) val 447 drivers/atm/fore200e.c writel(cpu_to_le32(val), addr); val 639 drivers/atm/fore200e.c static void fore200e_sba_write(u32 val, volatile u32 __iomem *addr) val 641 drivers/atm/fore200e.c sbus_writel(val, addr); val 176 drivers/atm/he.c #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0) val 182 drivers/atm/he.c he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr, val 185 drivers/atm/he.c he_writel(he_dev, val, CON_DAT); val 191 drivers/atm/he.c #define he_writel_rcm(dev, val, reg) \ val 192 drivers/atm/he.c he_writel_internal(dev, val, reg, CON_CTL_RCM) val 194 drivers/atm/he.c #define he_writel_tcm(dev, val, reg) \ val 195 drivers/atm/he.c he_writel_internal(dev, val, reg, CON_CTL_TCM) val 197 drivers/atm/he.c #define he_writel_mbox(dev, val, reg) \ val 198 drivers/atm/he.c he_writel_internal(dev, val, reg, CON_CTL_MBOX) val 224 drivers/atm/he.c #define he_writel_tsr0(dev, val, cid) \ val 225 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0) val 229 drivers/atm/he.c #define he_writel_tsr1(dev, val, cid) \ val 230 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1) val 232 drivers/atm/he.c #define he_writel_tsr2(dev, val, cid) \ val 233 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2) val 235 drivers/atm/he.c #define he_writel_tsr3(dev, val, cid) \ val 236 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3) val 238 drivers/atm/he.c #define he_writel_tsr4(dev, val, cid) \ val 239 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4) val 249 drivers/atm/he.c #define he_writel_tsr4_upper(dev, val, cid) \ val 250 drivers/atm/he.c he_writel_internal(dev, val, CONFIG_TSRA | (cid << 3) | 4, \ val 259 drivers/atm/he.c #define he_writel_tsr5(dev, val, cid) \ val 260 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5) val 262 drivers/atm/he.c #define he_writel_tsr6(dev, val, cid) \ val 263 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6) val 265 drivers/atm/he.c #define he_writel_tsr7(dev, val, cid) \ val 266 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7) val 269 drivers/atm/he.c #define he_writel_tsr8(dev, val, cid) \ val 270 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0) val 272 drivers/atm/he.c #define he_writel_tsr9(dev, val, cid) \ val 273 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1) val 275 drivers/atm/he.c #define he_writel_tsr10(dev, val, cid) \ val 276 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2) val 278 drivers/atm/he.c #define he_writel_tsr11(dev, val, cid) \ val 279 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3) val 282 drivers/atm/he.c #define he_writel_tsr12(dev, val, cid) \ val 283 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0) val 285 drivers/atm/he.c #define he_writel_tsr13(dev, val, cid) \ val 286 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1) val 289 drivers/atm/he.c #define he_writel_tsr14(dev, val, cid) \ val 290 drivers/atm/he.c he_writel_tcm(dev, val, CONFIG_TSRD | cid) val 292 drivers/atm/he.c #define he_writel_tsr14_upper(dev, val, cid) \ val 293 drivers/atm/he.c he_writel_internal(dev, val, CONFIG_TSRD | cid, \ val 301 drivers/atm/he.c #define he_writel_rsr0(dev, val, cid) \ val 302 drivers/atm/he.c he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0) val 306 drivers/atm/he.c #define he_writel_rsr1(dev, val, cid) \ val 307 drivers/atm/he.c he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1) val 309 drivers/atm/he.c #define he_writel_rsr2(dev, val, cid) \ val 310 drivers/atm/he.c he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2) val 312 drivers/atm/he.c #define he_writel_rsr3(dev, val, cid) \ val 313 drivers/atm/he.c he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3) val 315 drivers/atm/he.c #define he_writel_rsr4(dev, val, cid) \ val 316 drivers/atm/he.c he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4) val 318 drivers/atm/he.c #define he_writel_rsr5(dev, val, cid) \ val 319 drivers/atm/he.c he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5) val 321 drivers/atm/he.c #define he_writel_rsr6(dev, val, cid) \ val 322 drivers/atm/he.c he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6) val 324 drivers/atm/he.c #define he_writel_rsr7(dev, val, cid) \ val 325 drivers/atm/he.c he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7) val 1486 drivers/atm/he.c int val; val 1488 drivers/atm/he.c val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM); val 1489 drivers/atm/he.c val = (val & ~SUNI_TPOP_APM_S) | (SUNI_TPOP_S_SDH << SUNI_TPOP_APM_S_SHIFT); val 1490 drivers/atm/he.c he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM); val 2635 drivers/atm/he.c reg.val = he_readl(he_dev, reg.addr); val 2638 drivers/atm/he.c reg.val = val 2642 drivers/atm/he.c reg.val = val 2646 drivers/atm/he.c reg.val = val 2673 drivers/atm/he.c he_phy_put(struct atm_dev *atm_dev, unsigned char val, unsigned long addr) val 2678 drivers/atm/he.c HPRINTK("phy_put(val 0x%x, addr 0x%lx)\n", val, addr); val 2681 drivers/atm/he.c he_writel(he_dev, val, FRAMER + (addr*4)); val 2789 drivers/atm/he.c u32 val = 0, tmp_read = 0; val 2793 drivers/atm/he.c val = readl(he_dev->membase + HOST_CNTL); val 2794 drivers/atm/he.c val &= 0xFFFFE0FF; val 2797 drivers/atm/he.c val |= 0x800; val 2798 drivers/atm/he.c he_writel(he_dev, val, HOST_CNTL); val 2802 drivers/atm/he.c he_writel(he_dev, val | readtab[i], HOST_CNTL); val 2808 drivers/atm/he.c he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL); val 2810 drivers/atm/he.c he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL); val 2816 drivers/atm/he.c val &= 0xFFFFF7FF; /* Turn off write enable */ val 2817 drivers/atm/he.c he_writel(he_dev, val, HOST_CNTL); val 2821 drivers/atm/he.c he_writel(he_dev, val | clocktab[j++], HOST_CNTL); val 2826 drivers/atm/he.c he_writel(he_dev, val | clocktab[j++], HOST_CNTL); val 2830 drivers/atm/he.c he_writel(he_dev, val | ID_CS, HOST_CNTL); val 46 drivers/atm/idt77105.c #define PUT(val,reg) dev->ops->phy_put(dev,val,IDT77105_##reg) val 64 drivers/atm/idt77105.c u16 val; val 69 drivers/atm/idt77105.c val = GET(CTRLO); val 71 drivers/atm/idt77105.c val |= GET(CTRHI)<<8; val 73 drivers/atm/idt77105.c return val; val 701 drivers/atm/iphase.c static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val) val 718 drivers/atm/iphase.c NVRAM_CLKOUT (val & 0x8000); val 719 drivers/atm/iphase.c val <<= 1; val 739 drivers/atm/iphase.c u_short val; val 751 drivers/atm/iphase.c val = 0; val 754 drivers/atm/iphase.c val |= (t << i); val 758 drivers/atm/iphase.c return val; val 827 drivers/atm/iphase.c static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val) val 829 drivers/atm/iphase.c writel(val, ia->phy + (reg >> 2)); val 870 drivers/atm/iphase.c u16 val; val 877 drivers/atm/iphase.c ia_phy_write32(iadev, regs->reg, regs->val); val 1373 drivers/atm/iphase.h #define CFG_AND(val) { \ val 1376 drivers/atm/iphase.h t &= (val); \ val 1387 drivers/atm/iphase.h #define CFG_OR(val) { \ val 1390 drivers/atm/iphase.h t |= (val); \ val 484 drivers/atm/lanai.c static inline void reg_write(const struct lanai_dev *lanai, u32 val, val 488 drivers/atm/lanai.c (int) reg, val); val 489 drivers/atm/lanai.c writel(val, reg_addr(lanai, reg)); val 546 drivers/atm/lanai.c u32 val, int offset) val 548 drivers/atm/lanai.c writel(val, sram_addr(lanai, offset)); val 649 drivers/atm/lanai.c u32 val; val 651 drivers/atm/lanai.c val= readl(lvcc->vbase + offset); val 653 drivers/atm/lanai.c lvcc->vci, (int) offset, val); val 654 drivers/atm/lanai.c return val; val 658 drivers/atm/lanai.c u32 val, enum lanai_vcc_offset offset) val 661 drivers/atm/lanai.c APRINTK((val & ~0xFFFF) == 0, val 663 drivers/atm/lanai.c (unsigned int) val, lvcc->vci, (unsigned int) offset); val 665 drivers/atm/lanai.c lvcc->vci, (unsigned int) offset, (unsigned int) val); val 666 drivers/atm/lanai.c writel(val, lvcc->vbase + offset); val 1914 drivers/atm/lanai.c static int check_board_id_and_rev(const char *name, u32 val, int *revp) val 1917 drivers/atm/lanai.c (int) RESET_GET_BOARD_ID(val), val 1918 drivers/atm/lanai.c (int) RESET_GET_BOARD_REV(val)); val 1919 drivers/atm/lanai.c if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) { val 1921 drivers/atm/lanai.c "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val)); val 1925 drivers/atm/lanai.c *revp = RESET_GET_BOARD_REV(val); val 109 drivers/atm/nicstarmac.c #define NICSTAR_REG_WRITE(bs, reg, val) \ val 111 drivers/atm/nicstarmac.c writel((val),(base)+(reg)) val 124 drivers/atm/nicstarmac.c u_int32_t val; val 129 drivers/atm/nicstarmac.c val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; val 133 drivers/atm/nicstarmac.c (val | rdsrtab[i])); val 143 drivers/atm/nicstarmac.c (val | clocktab[j++])); val 147 drivers/atm/nicstarmac.c (val | clocktab[j++])); val 164 drivers/atm/nicstarmac.c u_int32_t val = 0; val 168 drivers/atm/nicstarmac.c val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; val 173 drivers/atm/nicstarmac.c (val | readtab[i])); val 180 drivers/atm/nicstarmac.c (val | clocktab[j++] | ((offset >> i) & 1))); val 183 drivers/atm/nicstarmac.c (val | clocktab[j++] | ((offset >> i) & 1))); val 192 drivers/atm/nicstarmac.c (val | clocktab[j++])); val 198 drivers/atm/nicstarmac.c (val | clocktab[j++])); val 209 drivers/atm/nicstarmac.c u_int32_t val; val 214 drivers/atm/nicstarmac.c val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; val 217 drivers/atm/nicstarmac.c (val | CS_HIGH | CLK_HIGH)); val 221 drivers/atm/nicstarmac.c (val | CS_HIGH | CLK_LOW)); val 225 drivers/atm/nicstarmac.c (val | CS_HIGH | CLK_HIGH)); val 229 drivers/atm/nicstarmac.c (val | CS_HIGH | CLK_LOW)); val 41 drivers/atm/suni.c #define PUT(val,reg) dev->ops->phy_put(dev,val,SUNI_##reg) val 37 drivers/atm/uPD98402.c #define PUT(val,reg) dev->ops->phy_put(dev,val,uPD98402_##reg) val 118 drivers/auxdisplay/arm-charlcd.c u32 val; val 126 drivers/auxdisplay/arm-charlcd.c val = 0; val 127 drivers/auxdisplay/arm-charlcd.c while (!(val & CHAR_RAW_VALID) && i < 10) { val 129 drivers/auxdisplay/arm-charlcd.c val = readl(lcd->virtbase + CHAR_RAW); val 145 drivers/auxdisplay/arm-charlcd.c val = 0; val 146 drivers/auxdisplay/arm-charlcd.c while (!(val & CHAR_RAW_VALID) && i < 10) { val 148 drivers/auxdisplay/arm-charlcd.c val = readl(lcd->virtbase + CHAR_RAW); val 62 drivers/auxdisplay/hd44780.c static void hd44780_write_gpio8(struct hd44780 *hd, u8 val, unsigned int rs) val 67 drivers/auxdisplay/hd44780.c values[0] = val; val 78 drivers/auxdisplay/hd44780.c static void hd44780_write_gpio4(struct hd44780 *hd, u8 val, unsigned int rs) val 84 drivers/auxdisplay/hd44780.c values[0] = val >> 4; val 95 drivers/auxdisplay/hd44780.c values[0] |= val & 0x0f; val 69 drivers/auxdisplay/img-ascii-lcd.c ulong val; val 72 drivers/auxdisplay/img-ascii-lcd.c val = *((u64 *)&ctx->curr[0]); val 73 drivers/auxdisplay/img-ascii-lcd.c __raw_writeq(val, ctx->base); val 75 drivers/auxdisplay/img-ascii-lcd.c val = *((u32 *)&ctx->curr[0]); val 76 drivers/auxdisplay/img-ascii-lcd.c __raw_writel(val, ctx->base); val 77 drivers/auxdisplay/img-ascii-lcd.c val = *((u32 *)&ctx->curr[4]); val 78 drivers/auxdisplay/img-ascii-lcd.c __raw_writel(val, ctx->base + 4); val 580 drivers/auxdisplay/panel.c static void lcd_get_bits(unsigned int port, int *val) val 586 drivers/auxdisplay/panel.c *val &= lcd_bits[port][bit][BIT_MSK]; val 587 drivers/auxdisplay/panel.c *val |= lcd_bits[port][bit][state]; val 594 drivers/auxdisplay/panel.c int val; val 596 drivers/auxdisplay/panel.c val = r_dtr(pprt); val 597 drivers/auxdisplay/panel.c lcd_get_bits(LCD_PORT_D, &val); val 598 drivers/auxdisplay/panel.c w_dtr(pprt, val); val 599 drivers/auxdisplay/panel.c return val; val 605 drivers/auxdisplay/panel.c int val; val 607 drivers/auxdisplay/panel.c val = r_ctr(pprt); val 608 drivers/auxdisplay/panel.c lcd_get_bits(LCD_PORT_C, &val); val 609 drivers/auxdisplay/panel.c w_ctr(pprt, val); val 610 drivers/auxdisplay/panel.c return val; val 173 drivers/base/arch_topology.c unsigned long val, val 182 drivers/base/arch_topology.c if (val != CPUFREQ_CREATE_POLICY) val 1295 drivers/base/core.c bool val; val 1298 drivers/base/core.c val = !dev->offline; val 1300 drivers/base/core.c return sprintf(buf, "%u\n", val); val 1306 drivers/base/core.c bool val; val 1309 drivers/base/core.c ret = strtobool(buf, &val); val 1317 drivers/base/core.c ret = val ? device_online(dev) : device_offline(dev); val 159 drivers/base/memory.c int memory_notify(unsigned long val, void *v) val 161 drivers/base/memory.c return blocking_notifier_call_chain(&memory_chain, val, v); val 164 drivers/base/memory.c int memory_isolate_notify(unsigned long val, void *v) val 166 drivers/base/memory.c return atomic_notifier_call_chain(&memory_isolate_chain, val, v); val 638 drivers/base/power/domain.c unsigned long val, void *ptr) val 56 drivers/base/power/qos.c s32 val; val 67 drivers/base/power/qos.c val = pqf->effective_flags & mask; val 68 drivers/base/power/qos.c if (val) val 69 drivers/base/power/qos.c return (val == mask) ? PM_QOS_FLAGS_ALL : PM_QOS_FLAGS_SOME; val 713 drivers/base/power/qos.c int dev_pm_qos_expose_flags(struct device *dev, s32 val) val 725 drivers/base/power/qos.c ret = dev_pm_qos_add_request(dev, req, DEV_PM_QOS_FLAGS, val); val 843 drivers/base/power/qos.c int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val) val 853 drivers/base/power/qos.c if (val < 0) { val 854 drivers/base/power/qos.c if (val == PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT) val 865 drivers/base/power/qos.c ret = __dev_pm_qos_add_request(dev, req, DEV_PM_QOS_LATENCY_TOLERANCE, val); val 872 drivers/base/power/qos.c if (val < 0) { val 876 drivers/base/power/qos.c ret = __dev_pm_qos_update_request(dev->power.qos->latency_tolerance_req, val); val 120 drivers/base/power/trace.c unsigned int val; val 124 drivers/base/power/trace.c val = time.tm_year; /* 100 years */ val 125 drivers/base/power/trace.c if (val > 100) val 126 drivers/base/power/trace.c val -= 100; val 127 drivers/base/power/trace.c val += time.tm_mon * 100; /* 12 months */ val 128 drivers/base/power/trace.c val += (time.tm_mday-1) * 100 * 12; /* 28 month-days */ val 129 drivers/base/power/trace.c val += time.tm_hour * 100 * 12 * 28; /* 24 hours */ val 130 drivers/base/power/trace.c val += (time.tm_min / 3) * 100 * 12 * 28 * 24; /* 20 3-minute intervals */ val 131 drivers/base/power/trace.c return val; val 277 drivers/base/power/trace.c unsigned int val = hash_value_early_read; val 280 drivers/base/power/trace.c user = val % USERHASH; val 281 drivers/base/power/trace.c val = val / USERHASH; val 282 drivers/base/power/trace.c file = val % FILEHASH; val 283 drivers/base/power/trace.c val = val / FILEHASH; val 284 drivers/base/power/trace.c dev = val /* % DEVHASH */; val 79 drivers/base/property.c u8 *val, size_t nval) val 81 drivers/base/property.c return fwnode_property_read_u8_array(dev_fwnode(dev), propname, val, nval); val 104 drivers/base/property.c u16 *val, size_t nval) val 106 drivers/base/property.c return fwnode_property_read_u16_array(dev_fwnode(dev), propname, val, nval); val 129 drivers/base/property.c u32 *val, size_t nval) val 131 drivers/base/property.c return fwnode_property_read_u32_array(dev_fwnode(dev), propname, val, nval); val 154 drivers/base/property.c u64 *val, size_t nval) val 156 drivers/base/property.c return fwnode_property_read_u64_array(dev_fwnode(dev), propname, val, nval); val 179 drivers/base/property.c const char **val, size_t nval) val 181 drivers/base/property.c return fwnode_property_read_string_array(dev_fwnode(dev), propname, val, nval); val 201 drivers/base/property.c const char **val) val 203 drivers/base/property.c return fwnode_property_read_string(dev_fwnode(dev), propname, val); val 231 drivers/base/property.c unsigned int elem_size, void *val, val 237 drivers/base/property.c elem_size, val, nval); val 242 drivers/base/property.c elem_size, val, nval); val 266 drivers/base/property.c const char *propname, u8 *val, size_t nval) val 269 drivers/base/property.c val, nval); val 292 drivers/base/property.c const char *propname, u16 *val, size_t nval) val 295 drivers/base/property.c val, nval); val 318 drivers/base/property.c const char *propname, u32 *val, size_t nval) val 321 drivers/base/property.c val, nval); val 344 drivers/base/property.c const char *propname, u64 *val, size_t nval) val 347 drivers/base/property.c val, nval); val 370 drivers/base/property.c const char *propname, const char **val, val 376 drivers/base/property.c val, nval); val 381 drivers/base/property.c val, nval); val 402 drivers/base/property.c const char *propname, const char **val) val 404 drivers/base/property.c int ret = fwnode_property_read_string_array(fwnode, propname, val, 1); val 36 drivers/base/regmap/internal.h unsigned int reg, unsigned int val); val 38 drivers/base/regmap/internal.h void (*format_val)(void *buf, unsigned int val, unsigned int shift); val 103 drivers/base/regmap/internal.h int (*reg_read)(void *context, unsigned int reg, unsigned int *val); val 104 drivers/base/regmap/internal.h int (*reg_write)(void *context, unsigned int reg, unsigned int val); val 106 drivers/base/regmap/internal.h unsigned int mask, unsigned int val); val 189 drivers/base/regmap/internal.h unsigned int val); val 258 drivers/base/regmap/internal.h unsigned int val); val 262 drivers/base/regmap/internal.h const void *val, size_t val_len); val 328 drivers/base/regmap/regcache-lzo.c unsigned int val; val 339 drivers/base/regmap/regcache-lzo.c ret = regcache_read(map, i, &val); val 345 drivers/base/regmap/regcache-lzo.c if (ret > 0 && val == map->reg_defaults[ret].def) val 349 drivers/base/regmap/regcache-lzo.c ret = _regmap_write(map, i, val); val 354 drivers/base/regmap/regcache-lzo.c i, val); val 56 drivers/base/regmap/regcache-rbtree.c unsigned int idx, unsigned int val) val 59 drivers/base/regmap/regcache-rbtree.c regcache_set_val(map, rbnode->block, idx, val); val 31 drivers/base/regmap/regcache.c unsigned int reg, val; val 88 drivers/base/regmap/regcache.c val = regcache_get_val(map, map->reg_defaults_raw, i); val 93 drivers/base/regmap/regcache.c ret = regmap_read(map, reg, &val); val 103 drivers/base/regmap/regcache.c map->reg_defaults[j].def = val; val 279 drivers/base/regmap/regcache.c unsigned int val) val 289 drivers/base/regmap/regcache.c if (ret >= 0 && val == map->reg_defaults[ret].def) val 300 drivers/base/regmap/regcache.c unsigned int val; val 307 drivers/base/regmap/regcache.c ret = regcache_read(map, reg, &val); val 311 drivers/base/regmap/regcache.c if (!regcache_reg_needs_sync(map, reg, val)) val 315 drivers/base/regmap/regcache.c ret = _regmap_write(map, reg, val); val 322 drivers/base/regmap/regcache.c dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val); val 549 drivers/base/regmap/regcache.c unsigned int val) val 551 drivers/base/regmap/regcache.c if (regcache_get_val(map, base, idx) == val) val 557 drivers/base/regmap/regcache.c val, 0); val 565 drivers/base/regmap/regcache.c cache[idx] = val; val 571 drivers/base/regmap/regcache.c cache[idx] = val; val 577 drivers/base/regmap/regcache.c cache[idx] = val; val 584 drivers/base/regmap/regcache.c cache[idx] = val; val 673 drivers/base/regmap/regcache.c unsigned int i, regtmp, val; val 683 drivers/base/regmap/regcache.c val = regcache_get_val(map, block, i); val 684 drivers/base/regmap/regcache.c if (!regcache_reg_needs_sync(map, regtmp, val)) val 689 drivers/base/regmap/regcache.c ret = _regmap_write(map, regtmp, val); val 698 drivers/base/regmap/regcache.c regtmp, val); val 737 drivers/base/regmap/regcache.c unsigned int i, val; val 755 drivers/base/regmap/regcache.c val = regcache_get_val(map, block, i); val 756 drivers/base/regmap/regcache.c if (!regcache_reg_needs_sync(map, regtmp, val)) { val 45 drivers/base/regmap/regmap-ac97.c unsigned int *val) val 49 drivers/base/regmap/regmap-ac97.c *val = ac97->bus->ops->read(ac97, reg); val 55 drivers/base/regmap/regmap-ac97.c unsigned int val) val 59 drivers/base/regmap/regmap-ac97.c ac97->bus->ops->write(ac97, reg, val); val 225 drivers/base/regmap/regmap-debugfs.c unsigned int val, start_reg; val 254 drivers/base/regmap/regmap-debugfs.c ret = regmap_read(map, i, &val); val 257 drivers/base/regmap/regmap-debugfs.c "%.*x", map->debugfs_val_len, val); val 16 drivers/base/regmap/regmap-i2c.c unsigned int *val) val 29 drivers/base/regmap/regmap-i2c.c *val = ret; val 35 drivers/base/regmap/regmap-i2c.c unsigned int val) val 40 drivers/base/regmap/regmap-i2c.c if (val > 0xff || reg > 0xff) val 43 drivers/base/regmap/regmap-i2c.c return i2c_smbus_write_byte_data(i2c, reg, val); val 52 drivers/base/regmap/regmap-i2c.c unsigned int *val) val 65 drivers/base/regmap/regmap-i2c.c *val = ret; val 71 drivers/base/regmap/regmap-i2c.c unsigned int val) val 76 drivers/base/regmap/regmap-i2c.c if (val > 0xffff || reg > 0xff) val 79 drivers/base/regmap/regmap-i2c.c return i2c_smbus_write_word_data(i2c, reg, val); val 88 drivers/base/regmap/regmap-i2c.c unsigned int *val) val 101 drivers/base/regmap/regmap-i2c.c *val = ret; val 107 drivers/base/regmap/regmap-i2c.c unsigned int val) val 112 drivers/base/regmap/regmap-i2c.c if (val > 0xffff || reg > 0xff) val 115 drivers/base/regmap/regmap-i2c.c return i2c_smbus_write_word_swapped(i2c, reg, val); val 140 drivers/base/regmap/regmap-i2c.c const void *val, size_t val_size) val 161 drivers/base/regmap/regmap-i2c.c xfer[1].buf = (void *)val; val 174 drivers/base/regmap/regmap-i2c.c void *val, size_t val_size) val 189 drivers/base/regmap/regmap-i2c.c xfer[1].buf = val; val 223 drivers/base/regmap/regmap-i2c.c size_t reg_size, void *val, val 233 drivers/base/regmap/regmap-i2c.c ret = i2c_smbus_read_i2c_block_data(i2c, ((u8 *)reg)[0], val_size, val); val 26 drivers/base/regmap/regmap-i3c.c void *val, size_t val_size) val 38 drivers/base/regmap/regmap-i3c.c xfers[1].data.in = val; val 64 drivers/base/regmap/regmap-irq.c unsigned int val) val 67 drivers/base/regmap/regmap-irq.c return regmap_write_bits(d->map, reg, mask, val); val 69 drivers/base/regmap/regmap-irq.c return regmap_update_bits(d->map, reg, mask, val); val 79 drivers/base/regmap/regmap-irq.c u32 val; val 93 drivers/base/regmap/regmap-irq.c ret = regmap_read(map, reg, &val); val 24 drivers/base/regmap/regmap-mmio.c unsigned int reg, unsigned int val); val 73 drivers/base/regmap/regmap-mmio.c unsigned int val) val 75 drivers/base/regmap/regmap-mmio.c writeb(val, ctx->regs + reg); val 80 drivers/base/regmap/regmap-mmio.c unsigned int val) val 82 drivers/base/regmap/regmap-mmio.c writew(val, ctx->regs + reg); val 87 drivers/base/regmap/regmap-mmio.c unsigned int val) val 89 drivers/base/regmap/regmap-mmio.c iowrite16be(val, ctx->regs + reg); val 94 drivers/base/regmap/regmap-mmio.c unsigned int val) val 96 drivers/base/regmap/regmap-mmio.c writel(val, ctx->regs + reg); val 101 drivers/base/regmap/regmap-mmio.c unsigned int val) val 103 drivers/base/regmap/regmap-mmio.c iowrite32be(val, ctx->regs + reg); val 109 drivers/base/regmap/regmap-mmio.c unsigned int val) val 111 drivers/base/regmap/regmap-mmio.c writeq(val, ctx->regs + reg); val 115 drivers/base/regmap/regmap-mmio.c static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val) val 126 drivers/base/regmap/regmap-mmio.c ctx->reg_write(ctx, reg, val); val 172 drivers/base/regmap/regmap-mmio.c static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val) val 183 drivers/base/regmap/regmap-mmio.c *val = ctx->reg_read(ctx, reg); val 40 drivers/base/regmap/regmap-sccb.c static int regmap_sccb_read(void *context, unsigned int reg, unsigned int *val) val 59 drivers/base/regmap/regmap-sccb.c *val = data.byte; val 75 drivers/base/regmap/regmap-sccb.c static int regmap_sccb_write(void *context, unsigned int reg, unsigned int val) val 80 drivers/base/regmap/regmap-sccb.c return i2c_smbus_write_byte_data(i2c, reg, val); val 10 drivers/base/regmap/regmap-sdw.c static int regmap_sdw_write(void *context, unsigned int reg, unsigned int val) val 15 drivers/base/regmap/regmap-sdw.c return sdw_write(slave, reg, val); val 18 drivers/base/regmap/regmap-sdw.c static int regmap_sdw_read(void *context, unsigned int reg, unsigned int *val) val 28 drivers/base/regmap/regmap-sdw.c *val = read; val 18 drivers/base/regmap/regmap-slimbus.c void *val, size_t val_size) val 22 drivers/base/regmap/regmap-slimbus.c return slim_read(sdev, *(u16 *)reg, val_size, val); val 38 drivers/base/regmap/regmap-spi.c const void *val, size_t val_len) val 44 drivers/base/regmap/regmap-spi.c { .tx_buf = val, .len = val_len, }, }; val 55 drivers/base/regmap/regmap-spi.c const void *val, size_t val_len, val 66 drivers/base/regmap/regmap-spi.c async->t[1].tx_buf = val; val 71 drivers/base/regmap/regmap-spi.c if (val) val 93 drivers/base/regmap/regmap-spi.c void *val, size_t val_size) val 98 drivers/base/regmap/regmap-spi.c return spi_write_then_read(spi, reg, reg_size, val, val_size); val 18 drivers/base/regmap/regmap-spmi.c void *val, size_t val_size) val 26 drivers/base/regmap/regmap-spmi.c err = spmi_register_read(context, addr++, val++); val 33 drivers/base/regmap/regmap-spmi.c const void *val, size_t val_size) val 35 drivers/base/regmap/regmap-spmi.c const u8 *data = val; val 107 drivers/base/regmap/regmap-spmi.c void *val, size_t val_size) val 124 drivers/base/regmap/regmap-spmi.c err = spmi_ext_register_read(context, addr, val, len); val 129 drivers/base/regmap/regmap-spmi.c val += len; val 136 drivers/base/regmap/regmap-spmi.c err = spmi_ext_register_readl(context, addr, val, len); val 141 drivers/base/regmap/regmap-spmi.c val += len; val 151 drivers/base/regmap/regmap-spmi.c const void *val, size_t val_size) val 164 drivers/base/regmap/regmap-spmi.c err = spmi_ext_register_write(context, addr, val, len); val 169 drivers/base/regmap/regmap-spmi.c val += len; val 176 drivers/base/regmap/regmap-spmi.c err = spmi_ext_register_writel(context, addr, val, len); val 181 drivers/base/regmap/regmap-spmi.c val += len; val 21 drivers/base/regmap/regmap-w1.c static int w1_reg_a8_v8_read(void *context, unsigned int reg, unsigned int *val) val 34 drivers/base/regmap/regmap-w1.c *val = w1_read_8(sl->master); val 43 drivers/base/regmap/regmap-w1.c static int w1_reg_a8_v8_write(void *context, unsigned int reg, unsigned int val) val 56 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, val); val 70 drivers/base/regmap/regmap-w1.c unsigned int *val) val 83 drivers/base/regmap/regmap-w1.c *val = w1_read_8(sl->master); val 84 drivers/base/regmap/regmap-w1.c *val |= w1_read_8(sl->master)<<8; val 94 drivers/base/regmap/regmap-w1.c unsigned int val) val 107 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, val & 0x00FF); val 108 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, val>>8 & 0x00FF); val 122 drivers/base/regmap/regmap-w1.c unsigned int *val) val 136 drivers/base/regmap/regmap-w1.c *val = w1_read_8(sl->master); val 137 drivers/base/regmap/regmap-w1.c *val |= w1_read_8(sl->master)<<8; val 147 drivers/base/regmap/regmap-w1.c unsigned int val) val 161 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, val & 0x00FF); val 162 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, val>>8 & 0x00FF); val 45 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, val 49 drivers/base/regmap/regmap.c unsigned int *val); val 51 drivers/base/regmap/regmap.c unsigned int *val); val 53 drivers/base/regmap/regmap.c unsigned int val); val 55 drivers/base/regmap/regmap.c unsigned int val); val 57 drivers/base/regmap/regmap.c unsigned int val); val 106 drivers/base/regmap/regmap.c unsigned int val; val 118 drivers/base/regmap/regmap.c ret = regcache_read(map, reg, &val); val 212 drivers/base/regmap/regmap.c unsigned int reg, unsigned int val) val 216 drivers/base/regmap/regmap.c *out = (reg << 6) | val; val 220 drivers/base/regmap/regmap.c unsigned int reg, unsigned int val) val 223 drivers/base/regmap/regmap.c *out = cpu_to_be16((reg << 12) | val); val 227 drivers/base/regmap/regmap.c unsigned int reg, unsigned int val) val 230 drivers/base/regmap/regmap.c *out = cpu_to_be16((reg << 9) | val); val 234 drivers/base/regmap/regmap.c unsigned int reg, unsigned int val) val 238 drivers/base/regmap/regmap.c out[2] = val; val 239 drivers/base/regmap/regmap.c out[1] = (val >> 8) | (reg << 6); val 243 drivers/base/regmap/regmap.c static void regmap_format_8(void *buf, unsigned int val, unsigned int shift) val 247 drivers/base/regmap/regmap.c b[0] = val << shift; val 250 drivers/base/regmap/regmap.c static void regmap_format_16_be(void *buf, unsigned int val, unsigned int shift) val 254 drivers/base/regmap/regmap.c b[0] = cpu_to_be16(val << shift); val 257 drivers/base/regmap/regmap.c static void regmap_format_16_le(void *buf, unsigned int val, unsigned int shift) val 261 drivers/base/regmap/regmap.c b[0] = cpu_to_le16(val << shift); val 264 drivers/base/regmap/regmap.c static void regmap_format_16_native(void *buf, unsigned int val, val 267 drivers/base/regmap/regmap.c *(u16 *)buf = val << shift; val 270 drivers/base/regmap/regmap.c static void regmap_format_24(void *buf, unsigned int val, unsigned int shift) val 274 drivers/base/regmap/regmap.c val <<= shift; val 276 drivers/base/regmap/regmap.c b[0] = val >> 16; val 277 drivers/base/regmap/regmap.c b[1] = val >> 8; val 278 drivers/base/regmap/regmap.c b[2] = val; val 281 drivers/base/regmap/regmap.c static void regmap_format_32_be(void *buf, unsigned int val, unsigned int shift) val 285 drivers/base/regmap/regmap.c b[0] = cpu_to_be32(val << shift); val 288 drivers/base/regmap/regmap.c static void regmap_format_32_le(void *buf, unsigned int val, unsigned int shift) val 292 drivers/base/regmap/regmap.c b[0] = cpu_to_le32(val << shift); val 295 drivers/base/regmap/regmap.c static void regmap_format_32_native(void *buf, unsigned int val, val 298 drivers/base/regmap/regmap.c *(u32 *)buf = val << shift; val 302 drivers/base/regmap/regmap.c static void regmap_format_64_be(void *buf, unsigned int val, unsigned int shift) val 306 drivers/base/regmap/regmap.c b[0] = cpu_to_be64((u64)val << shift); val 309 drivers/base/regmap/regmap.c static void regmap_format_64_le(void *buf, unsigned int val, unsigned int shift) val 313 drivers/base/regmap/regmap.c b[0] = cpu_to_le64((u64)val << shift); val 316 drivers/base/regmap/regmap.c static void regmap_format_64_native(void *buf, unsigned int val, val 319 drivers/base/regmap/regmap.c *(u64 *)buf = (u64)val << shift; val 1478 drivers/base/regmap/regmap.c const void *val, size_t val_len) val 1508 drivers/base/regmap/regmap.c ival = map->format.parse_val(val + (i * val_bytes)); val 1535 drivers/base/regmap/regmap.c ret = _regmap_raw_write_impl(map, reg, val, val 1543 drivers/base/regmap/regmap.c val += win_residue * map->format.val_bytes; val 1565 drivers/base/regmap/regmap.c if (val != work_val && val_len == map->format.val_bytes) { val 1566 drivers/base/regmap/regmap.c memcpy(work_val, val, map->format.val_bytes); val 1567 drivers/base/regmap/regmap.c val = work_val; val 1606 drivers/base/regmap/regmap.c if (val != work_val) val 1611 drivers/base/regmap/regmap.c val, val_len, async); val 1637 drivers/base/regmap/regmap.c if (val == work_val) val 1646 drivers/base/regmap/regmap.c val, val_len); val 1659 drivers/base/regmap/regmap.c val, val_len); val 1711 drivers/base/regmap/regmap.c unsigned int val) val 1726 drivers/base/regmap/regmap.c map->format.format_write(map, reg, val); val 1739 drivers/base/regmap/regmap.c unsigned int val) val 1743 drivers/base/regmap/regmap.c return map->bus->reg_write(map->bus_context, reg, val); val 1747 drivers/base/regmap/regmap.c unsigned int val) val 1754 drivers/base/regmap/regmap.c + map->format.pad_bytes, val, 0); val 1768 drivers/base/regmap/regmap.c unsigned int val) val 1777 drivers/base/regmap/regmap.c ret = regcache_write(map, reg, val); val 1787 drivers/base/regmap/regmap.c dev_info(map->dev, "%x <= %x\n", reg, val); val 1789 drivers/base/regmap/regmap.c trace_regmap_reg_write(map, reg, val); val 1791 drivers/base/regmap/regmap.c return map->reg_write(context, reg, val); val 1804 drivers/base/regmap/regmap.c int regmap_write(struct regmap *map, unsigned int reg, unsigned int val) val 1813 drivers/base/regmap/regmap.c ret = _regmap_write(map, reg, val); val 1831 drivers/base/regmap/regmap.c int regmap_write_async(struct regmap *map, unsigned int reg, unsigned int val) val 1842 drivers/base/regmap/regmap.c ret = _regmap_write(map, reg, val); val 1853 drivers/base/regmap/regmap.c const void *val, size_t val_len) val 1874 drivers/base/regmap/regmap.c ret = _regmap_raw_write_impl(map, reg, val, chunk_bytes); val 1879 drivers/base/regmap/regmap.c val += chunk_bytes; val 1885 drivers/base/regmap/regmap.c ret = _regmap_raw_write_impl(map, reg, val, val_len); val 1907 drivers/base/regmap/regmap.c const void *val, size_t val_len) val 1918 drivers/base/regmap/regmap.c ret = _regmap_raw_write(map, reg, val, val_len); val 1948 drivers/base/regmap/regmap.c const void *val, size_t val_len) val 1976 drivers/base/regmap/regmap.c ret = _regmap_raw_write(map, reg, val, write_len); val 1979 drivers/base/regmap/regmap.c val = ((u8 *)val) + write_len; val 2007 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, val 2013 drivers/base/regmap/regmap.c mask, val << field->shift, val 2034 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, val 2044 drivers/base/regmap/regmap.c mask, val << field->shift, val 2063 drivers/base/regmap/regmap.c int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val, val 2083 drivers/base/regmap/regmap.c ival = *(u8 *)(val + (i * val_bytes)); val 2086 drivers/base/regmap/regmap.c ival = *(u16 *)(val + (i * val_bytes)); val 2089 drivers/base/regmap/regmap.c ival = *(u32 *)(val + (i * val_bytes)); val 2093 drivers/base/regmap/regmap.c ival = *(u64 *)(val + (i * val_bytes)); val 2112 drivers/base/regmap/regmap.c wval = kmemdup(val, val_count * val_bytes, map->alloc_flags); val 2161 drivers/base/regmap/regmap.c unsigned int val = regs[i].def; val 2165 drivers/base/regmap/regmap.c map->format.format_val(u8, val, 0); val 2301 drivers/base/regmap/regmap.c unsigned int val = regs[i].def; val 2303 drivers/base/regmap/regmap.c ret = regcache_write(map, reg, val); val 2440 drivers/base/regmap/regmap.c const void *val, size_t val_len) val 2453 drivers/base/regmap/regmap.c ret = _regmap_raw_write(map, reg, val, val_len); val 2463 drivers/base/regmap/regmap.c static int _regmap_raw_read(struct regmap *map, unsigned int reg, void *val, val 2489 drivers/base/regmap/regmap.c val, val_len); val 2497 drivers/base/regmap/regmap.c unsigned int *val) val 2501 drivers/base/regmap/regmap.c return map->bus->reg_read(map->bus_context, reg, val); val 2505 drivers/base/regmap/regmap.c unsigned int *val) val 2517 drivers/base/regmap/regmap.c *val = map->format.parse_val(work_val); val 2523 drivers/base/regmap/regmap.c unsigned int *val) val 2529 drivers/base/regmap/regmap.c ret = regcache_read(map, reg, val); val 2540 drivers/base/regmap/regmap.c ret = map->reg_read(context, reg, val); val 2543 drivers/base/regmap/regmap.c dev_info(map->dev, "%x => %x\n", reg, *val); val 2545 drivers/base/regmap/regmap.c trace_regmap_reg_read(map, reg, *val); val 2548 drivers/base/regmap/regmap.c regcache_write(map, reg, *val); val 2564 drivers/base/regmap/regmap.c int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val) val 2573 drivers/base/regmap/regmap.c ret = _regmap_read(map, reg, val); val 2592 drivers/base/regmap/regmap.c int regmap_raw_read(struct regmap *map, unsigned int reg, void *val, val 2631 drivers/base/regmap/regmap.c ret = _regmap_raw_read(map, reg, val, chunk_bytes); val 2636 drivers/base/regmap/regmap.c val += chunk_bytes; val 2642 drivers/base/regmap/regmap.c ret = _regmap_raw_read(map, reg, val, val_len); val 2656 drivers/base/regmap/regmap.c map->format.format_val(val + (i * val_bytes), v, 0); val 2689 drivers/base/regmap/regmap.c void *val, size_t val_len) val 2717 drivers/base/regmap/regmap.c ret = _regmap_raw_read(map, reg, val, read_len); val 2720 drivers/base/regmap/regmap.c val = ((u8 *)val) + read_len; val 2739 drivers/base/regmap/regmap.c int regmap_field_read(struct regmap_field *field, unsigned int *val) val 2749 drivers/base/regmap/regmap.c *val = reg_val; val 2766 drivers/base/regmap/regmap.c unsigned int *val) val 2782 drivers/base/regmap/regmap.c *val = reg_val; val 2799 drivers/base/regmap/regmap.c int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val, val 2812 drivers/base/regmap/regmap.c ret = regmap_raw_read(map, reg, val, val_bytes * val_count); val 2817 drivers/base/regmap/regmap.c map->format.parse_inplace(val + i); val 2820 drivers/base/regmap/regmap.c u64 *u64 = val; val 2822 drivers/base/regmap/regmap.c u32 *u32 = val; val 2823 drivers/base/regmap/regmap.c u16 *u16 = val; val 2824 drivers/base/regmap/regmap.c u8 *u8 = val; val 2866 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, val 2876 drivers/base/regmap/regmap.c ret = map->reg_update_bits(map->bus_context, reg, mask, val); val 2885 drivers/base/regmap/regmap.c tmp |= val & mask; val 2920 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, val 2929 drivers/base/regmap/regmap.c ret = _regmap_update_bits(map, reg, mask, val, change, force); val 3109 drivers/base/regmap/regmap.c unsigned int *val) val 3114 drivers/base/regmap/regmap.c *val = map->format.parse_val(buf); val 19 drivers/base/regmap/trace.h unsigned int val), val 21 drivers/base/regmap/trace.h TP_ARGS(map, reg, val), val 26 drivers/base/regmap/trace.h __field( unsigned int, val ) val 32 drivers/base/regmap/trace.h __entry->val = val; val 37 drivers/base/regmap/trace.h (unsigned int)__entry->val) val 43 drivers/base/regmap/trace.h unsigned int val), val 45 drivers/base/regmap/trace.h TP_ARGS(map, reg, val) val 52 drivers/base/regmap/trace.h unsigned int val), val 54 drivers/base/regmap/trace.h TP_ARGS(map, reg, val) val 61 drivers/base/regmap/trace.h unsigned int val), val 63 drivers/base/regmap/trace.h TP_ARGS(map, reg, val) val 265 drivers/base/swnode.c unsigned int elem_size, void *val, val 268 drivers/base/swnode.c if (!val) val 273 drivers/base/swnode.c return property_entry_read_u8_array(props, name, val, nval); val 275 drivers/base/swnode.c return property_entry_read_u16_array(props, name, val, nval); val 277 drivers/base/swnode.c return property_entry_read_u32_array(props, name, val, nval); val 279 drivers/base/swnode.c return property_entry_read_u64_array(props, name, val, nval); val 499 drivers/base/swnode.c unsigned int elem_size, void *val, val 505 drivers/base/swnode.c elem_size, val, nval); val 510 drivers/base/swnode.c const char **val, size_t nval) val 515 drivers/base/swnode.c propname, val, nval); val 16 drivers/bcma/core.c u32 val; val 19 drivers/bcma/core.c val = bcma_aread32(core, reg); val 20 drivers/bcma/core.c if ((val & mask) == value) val 18 drivers/bcma/driver_chipcommon_b.c u32 val; val 21 drivers/bcma/driver_chipcommon_b.c val = readl(addr); val 22 drivers/bcma/driver_chipcommon_b.c if ((val & mask) == value) val 213 drivers/bcma/driver_chipcommon_pmu.c u32 val; val 215 drivers/bcma/driver_chipcommon_pmu.c val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL); val 217 drivers/bcma/driver_chipcommon_pmu.c val |= BCMA_CHIPCTL_4331_EXTPA_EN; val 219 drivers/bcma/driver_chipcommon_pmu.c val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; val 221 drivers/bcma/driver_chipcommon_pmu.c val |= BCMA_CHIPCTL_4331_EXTPA_EN2; val 223 drivers/bcma/driver_chipcommon_pmu.c val &= ~BCMA_CHIPCTL_4331_EXTPA_EN; val 224 drivers/bcma/driver_chipcommon_pmu.c val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2; val 225 drivers/bcma/driver_chipcommon_pmu.c val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; val 227 drivers/bcma/driver_chipcommon_pmu.c bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); val 81 drivers/bcma/driver_gpio.c u32 val = bcma_chipco_gpio_in(cc, BIT(gpio)); val 83 drivers/bcma/driver_gpio.c bcma_chipco_gpio_polarity(cc, BIT(gpio), val); val 106 drivers/bcma/driver_gpio.c u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN); val 109 drivers/bcma/driver_gpio.c unsigned long irqs = (val ^ pol) & mask; val 117 drivers/bcma/driver_gpio.c bcma_chipco_gpio_polarity(cc, irqs, val & irqs); val 22 drivers/bcma/driver_pci_host.c #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) val 89 drivers/bcma/driver_pci_host.c u32 addr, val; val 106 drivers/bcma/driver_pci_host.c val = bcma_pcie_read_config(pc, addr); val 111 drivers/bcma/driver_pci_host.c val = pcicore_read32(pc, addr); val 118 drivers/bcma/driver_pci_host.c mmio = ioremap_nocache(addr, sizeof(val)); val 122 drivers/bcma/driver_pci_host.c if (mips_busprobe32(val, mmio)) { val 123 drivers/bcma/driver_pci_host.c val = 0xFFFFFFFF; val 127 drivers/bcma/driver_pci_host.c val >>= (8 * (off & 3)); val 131 drivers/bcma/driver_pci_host.c *((u8 *)buf) = (u8)val; val 134 drivers/bcma/driver_pci_host.c *((u16 *)buf) = (u16)val; val 137 drivers/bcma/driver_pci_host.c *((u32 *)buf) = (u32)val; val 153 drivers/bcma/driver_pci_host.c u32 addr, val; val 171 drivers/bcma/driver_pci_host.c val = bcma_pcie_read_config(pc, addr); val 176 drivers/bcma/driver_pci_host.c val = pcicore_read32(pc, addr); val 183 drivers/bcma/driver_pci_host.c mmio = ioremap_nocache(addr, sizeof(val)); val 187 drivers/bcma/driver_pci_host.c if (mips_busprobe32(val, mmio)) { val 188 drivers/bcma/driver_pci_host.c val = 0xFFFFFFFF; val 195 drivers/bcma/driver_pci_host.c val &= ~(0xFF << (8 * (off & 3))); val 196 drivers/bcma/driver_pci_host.c val |= *((const u8 *)buf) << (8 * (off & 3)); val 199 drivers/bcma/driver_pci_host.c val &= ~(0xFFFF << (8 * (off & 3))); val 200 drivers/bcma/driver_pci_host.c val |= *((const u16 *)buf) << (8 * (off & 3)); val 203 drivers/bcma/driver_pci_host.c val = *((const u32 *)buf); val 211 drivers/bcma/driver_pci_host.c bcma_pcie_write_config(pc, addr, val); val 213 drivers/bcma/driver_pci_host.c pcicore_write32(pc, addr, val); val 215 drivers/bcma/driver_pci_host.c writel(val, mmio); val 232 drivers/bcma/driver_pci_host.c int reg, int size, u32 *val) val 244 drivers/bcma/driver_pci_host.c PCI_FUNC(devfn), reg, val, size); val 252 drivers/bcma/driver_pci_host.c int reg, int size, u32 val) val 264 drivers/bcma/driver_pci_host.c PCI_FUNC(devfn), reg, &val, size); val 29 drivers/bcma/driver_pcie2.c u32 val) val 32 drivers/bcma/driver_pcie2.c pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val); val 42 drivers/bcma/driver_pcie2.c u32 val; val 45 drivers/bcma/driver_pcie2.c val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL); val 46 drivers/bcma/driver_pcie2.c val |= PCIE2_CLKC_DLYPERST; val 47 drivers/bcma/driver_pcie2.c val &= ~PCIE2_CLKC_DISSPROMLD; val 49 drivers/bcma/driver_pcie2.c val &= ~PCIE2_CLKC_DLYPERST; val 50 drivers/bcma/driver_pcie2.c val |= PCIE2_CLKC_DISSPROMLD; val 52 drivers/bcma/driver_pcie2.c pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val); val 166 drivers/bcma/host_pci.c u32 val; val 188 drivers/bcma/host_pci.c pci_read_config_dword(dev, 0x40, &val); val 189 drivers/bcma/host_pci.c if ((val & 0x0000ff00) != 0) val 190 drivers/bcma/host_pci.c pci_write_config_dword(dev, 0x40, val & 0xffff00ff); val 103 drivers/bcma/main.c u32 val; val 106 drivers/bcma/main.c val = bcma_read32(core, reg); val 107 drivers/bcma/main.c if ((val & mask) == value) val 324 drivers/block/ataflop.c #define FDC_WRITE(reg,val) \ val 330 drivers/block/ataflop.c dma_wd.fdc_acces_seccount = (val); \ val 718 drivers/block/ataflop.c #define FILL(n,val) \ val 720 drivers/block/ataflop.c memset( p, val, n ); \ val 1352 drivers/block/drbd/drbd_bitmap.c unsigned long e, int val) val 1380 drivers/block/drbd/drbd_bitmap.c if (val) val 1401 drivers/block/drbd/drbd_bitmap.c const unsigned long e, int val) val 1413 drivers/block/drbd/drbd_bitmap.c if ((val ? BM_DONT_SET : BM_DONT_CLEAR) & b->bm_flags) val 1416 drivers/block/drbd/drbd_bitmap.c c = __bm_change_bits_to(device, s, e, val); val 1130 drivers/block/drbd/drbd_int.h extern void drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local); val 1131 drivers/block/drbd/drbd_int.h extern void _drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local); val 1133 drivers/block/drbd/drbd_int.h extern void drbd_uuid_set_bm(struct drbd_device *device, u64 val) __must_hold(local); val 1135 drivers/block/drbd/drbd_int.h extern void __drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local); val 1575 drivers/block/drbd/drbd_int.h int val = 1; val 1577 drivers/block/drbd/drbd_int.h (char*)&val, sizeof(val)); val 1582 drivers/block/drbd/drbd_int.h int val = 0; val 1584 drivers/block/drbd/drbd_int.h (char*)&val, sizeof(val)); val 1589 drivers/block/drbd/drbd_int.h int val = 1; val 1591 drivers/block/drbd/drbd_int.h (char*)&val, sizeof(val)); val 1596 drivers/block/drbd/drbd_int.h int val = 2; val 1598 drivers/block/drbd/drbd_int.h (char*)&val, sizeof(val)); val 2335 drivers/block/drbd/drbd_int.h static inline int drbd_set_ed_uuid(struct drbd_device *device, u64 val) val 2337 drivers/block/drbd/drbd_int.h int changed = device->ed_uuid != val; val 2338 drivers/block/drbd/drbd_int.h device->ed_uuid = val; val 1034 drivers/block/drbd/drbd_main.c int drbd_send_state_req(struct drbd_peer_device *peer_device, union drbd_state mask, union drbd_state val) val 1044 drivers/block/drbd/drbd_main.c p->val = cpu_to_be32(val.i); val 1048 drivers/block/drbd/drbd_main.c int conn_send_state_req(struct drbd_connection *connection, union drbd_state mask, union drbd_state val) val 1060 drivers/block/drbd/drbd_main.c p->val = cpu_to_be32(val.i); val 3442 drivers/block/drbd/drbd_main.c void __drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local) val 3446 drivers/block/drbd/drbd_main.c val |= 1; val 3448 drivers/block/drbd/drbd_main.c val &= ~((u64)1); val 3450 drivers/block/drbd/drbd_main.c drbd_set_ed_uuid(device, val); val 3453 drivers/block/drbd/drbd_main.c device->ldev->md.uuid[idx] = val; val 3457 drivers/block/drbd/drbd_main.c void _drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local) val 3461 drivers/block/drbd/drbd_main.c __drbd_uuid_set(device, idx, val); val 3465 drivers/block/drbd/drbd_main.c void drbd_uuid_set(struct drbd_device *device, int idx, u64 val) __must_hold(local) val 3473 drivers/block/drbd/drbd_main.c __drbd_uuid_set(device, idx, val); val 3486 drivers/block/drbd/drbd_main.c u64 val; val 3489 drivers/block/drbd/drbd_main.c get_random_bytes(&val, sizeof(u64)); val 3498 drivers/block/drbd/drbd_main.c __drbd_uuid_set(device, UI_CURRENT, val); val 3506 drivers/block/drbd/drbd_main.c void drbd_uuid_set_bm(struct drbd_device *device, u64 val) __must_hold(local) val 3509 drivers/block/drbd/drbd_main.c if (device->ldev->md.uuid[UI_BITMAP] == 0 && val == 0) val 3513 drivers/block/drbd/drbd_main.c if (val == 0) { val 3522 drivers/block/drbd/drbd_main.c device->ldev->md.uuid[UI_BITMAP] = val & ~((u64)1); val 475 drivers/block/drbd/drbd_nl.c union drbd_state val = { }; val 526 drivers/block/drbd/drbd_nl.c val.pdsk = D_INCONSISTENT; val 531 drivers/block/drbd/drbd_nl.c val.pdsk = D_OUTDATED; val 538 drivers/block/drbd/drbd_nl.c val.pdsk = D_OUTDATED; val 549 drivers/block/drbd/drbd_nl.c val.disk = D_OUTDATED; val 558 drivers/block/drbd/drbd_nl.c val.pdsk = D_OUTDATED; val 580 drivers/block/drbd/drbd_nl.c _conn_request_state(connection, mask, val, CS_VERBOSE); val 625 drivers/block/drbd/drbd_nl.c union drbd_state mask, val; val 641 drivers/block/drbd/drbd_nl.c val.i = 0; val.role = new_role; val 644 drivers/block/drbd/drbd_nl.c rv = _drbd_request_state_holding_state_mutex(device, mask, val, CS_WAIT_COMPLETE); val 649 drivers/block/drbd/drbd_nl.c val.pdsk = 0; val 658 drivers/block/drbd/drbd_nl.c val.disk = D_UP_TO_DATE; val 668 drivers/block/drbd/drbd_nl.c val.disk = D_UP_TO_DATE; val 680 drivers/block/drbd/drbd_nl.c val.pdsk = D_OUTDATED; val 700 drivers/block/drbd/drbd_nl.c rv = _drbd_request_state(device, mask, val, val 3061 drivers/block/drbd/drbd_nl.c union drbd_state mask, union drbd_state val) val 3073 drivers/block/drbd/drbd_nl.c retcode = drbd_request_state(adm_ctx.device, mask, val); val 3227 drivers/block/drbd/drbd_nl.c u64 val; val 3228 drivers/block/drbd/drbd_nl.c get_random_bytes(&val, sizeof(u64)); val 3229 drivers/block/drbd/drbd_nl.c drbd_set_ed_uuid(device, val); val 372 drivers/block/drbd/drbd_protocol.h u32 val; val 4388 drivers/block/drbd/drbd_receiver.c union drbd_state mask, val; val 4397 drivers/block/drbd/drbd_receiver.c val.i = be32_to_cpu(p->val); val 4406 drivers/block/drbd/drbd_receiver.c val = convert_state(val); val 4408 drivers/block/drbd/drbd_receiver.c rv = drbd_change_state(device, CS_VERBOSE, mask, val); val 4419 drivers/block/drbd/drbd_receiver.c union drbd_state mask, val; val 4423 drivers/block/drbd/drbd_receiver.c val.i = be32_to_cpu(p->val); val 4432 drivers/block/drbd/drbd_receiver.c val = convert_state(val); val 4434 drivers/block/drbd/drbd_receiver.c rv = conn_request_state(connection, mask, val, CS_VERBOSE | CS_LOCAL_ONLY | CS_IGN_OUTD_FAIL); val 481 drivers/block/drbd/drbd_state.c apply_mask_val(union drbd_state os, union drbd_state mask, union drbd_state val) val 484 drivers/block/drbd/drbd_state.c ns.i = (os.i & ~mask.i) | val.i; val 490 drivers/block/drbd/drbd_state.c union drbd_state mask, union drbd_state val) val 497 drivers/block/drbd/drbd_state.c ns = apply_mask_val(drbd_read_state(device), mask, val); val 511 drivers/block/drbd/drbd_state.c union drbd_state mask, union drbd_state val) val 513 drivers/block/drbd/drbd_state.c drbd_change_state(device, CS_HARD, mask, val); val 518 drivers/block/drbd/drbd_state.c union drbd_state val) val 532 drivers/block/drbd/drbd_state.c ns = sanitize_state(device, os, apply_mask_val(os, mask, val), NULL); val 564 drivers/block/drbd/drbd_state.c union drbd_state val, enum chg_state_flags f) val 581 drivers/block/drbd/drbd_state.c ns = sanitize_state(device, os, apply_mask_val(os, mask, val), NULL); val 600 drivers/block/drbd/drbd_state.c if (drbd_send_state_req(first_peer_device(device), mask, val)) { val 608 drivers/block/drbd/drbd_state.c (rv = _req_st_cond(device, mask, val))); val 616 drivers/block/drbd/drbd_state.c ns = apply_mask_val(drbd_read_state(device), mask, val); val 650 drivers/block/drbd/drbd_state.c union drbd_state val, enum chg_state_flags f) val 655 drivers/block/drbd/drbd_state.c (rv = drbd_req_state(device, mask, val, f)) != SS_IN_TRANSIENT_STATE); val 701 drivers/block/drbd/drbd_state.c union drbd_state val, enum chg_state_flags f) val 708 drivers/block/drbd/drbd_state.c (rv = drbd_req_state(device, mask, val, f)) != SS_IN_TRANSIENT_STATE, val 2151 drivers/block/drbd/drbd_state.c conn_is_valid_transition(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, val 2163 drivers/block/drbd/drbd_state.c ns = sanitize_state(device, os, apply_mask_val(os, mask, val), NULL); val 2194 drivers/block/drbd/drbd_state.c conn_set_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, val 2201 drivers/block/drbd/drbd_state.c .conn = val.conn, val 2213 drivers/block/drbd/drbd_state.c if (connection->cstate != C_WF_REPORT_PARAMS && val.conn == C_WF_REPORT_PARAMS) val 2216 drivers/block/drbd/drbd_state.c connection->cstate = val.conn; val 2224 drivers/block/drbd/drbd_state.c ns = apply_mask_val(os, mask, val); val 2251 drivers/block/drbd/drbd_state.c .conn = val.conn, val 2266 drivers/block/drbd/drbd_state.c _conn_rq_cond(struct drbd_connection *connection, union drbd_state mask, union drbd_state val) val 2276 drivers/block/drbd/drbd_state.c err = conn_is_valid_transition(connection, mask, val, 0); val 2284 drivers/block/drbd/drbd_state.c _conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, val 2295 drivers/block/drbd/drbd_state.c rv = is_valid_conn_transition(oc, val.conn); val 2300 drivers/block/drbd/drbd_state.c rv = conn_is_valid_transition(connection, mask, val, flags); val 2304 drivers/block/drbd/drbd_state.c if (oc == C_WF_REPORT_PARAMS && val.conn == C_DISCONNECTING && val 2315 drivers/block/drbd/drbd_state.c if (conn_send_state_req(connection, mask, val)) { val 2323 drivers/block/drbd/drbd_state.c if (val.conn == C_DISCONNECTING) val 2331 drivers/block/drbd/drbd_state.c (rv = _conn_rq_cond(connection, mask, val)), val 2341 drivers/block/drbd/drbd_state.c conn_set_state(connection, mask, val, &ns_min, &ns_max, flags); val 2371 drivers/block/drbd/drbd_state.c drbd_err(connection, " mask = 0x%x val = 0x%x\n", mask.i, val.i); val 2372 drivers/block/drbd/drbd_state.c drbd_err(connection, " old_conn:%s wanted_conn:%s\n", drbd_conn_str(oc), drbd_conn_str(val.conn)); val 2378 drivers/block/drbd/drbd_state.c conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, val 2384 drivers/block/drbd/drbd_state.c rv = _conn_request_state(connection, mask, val, flags); val 39 drivers/block/drbd/drbd_state.h ({ union drbd_state val; val.i = 0; val.T = (S); val; }) val 43 drivers/block/drbd/drbd_state.h ({ union drbd_state val; val.i = 0; val.T1 = (S1); \ val 44 drivers/block/drbd/drbd_state.h val.T2 = (S2); val; }) val 48 drivers/block/drbd/drbd_state.h ({ union drbd_state val; val.i = 0; val.T1 = (S1); \ val 49 drivers/block/drbd/drbd_state.h val.T2 = (S2); val.T3 = (S3); val; }) val 118 drivers/block/drbd/drbd_state.h union drbd_state val); val 137 drivers/block/drbd/drbd_state.h _conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, val 141 drivers/block/drbd/drbd_state.h conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, val 159 drivers/block/drbd/drbd_state.h union drbd_state val) val 161 drivers/block/drbd/drbd_state.h return _drbd_request_state(device, mask, val, CS_VERBOSE + CS_ORDERED); val 248 drivers/block/drbd/drbd_vli.h static inline int bitstream_put_bits(struct bitstream *bs, u64 val, const unsigned int bits) val 261 drivers/block/drbd/drbd_vli.h val &= ~0ULL >> (64 - bits); val 263 drivers/block/drbd/drbd_vli.h *b++ |= (val & 0xff) << bs->cur.bit; val 266 drivers/block/drbd/drbd_vli.h *b++ |= (val >> tmp) & 0xff; val 283 drivers/block/drbd/drbd_vli.h u64 val; val 299 drivers/block/drbd/drbd_vli.h val = 0; val 304 drivers/block/drbd/drbd_vli.h memcpy(&val, bs->cur.b+1, n - 1); val 305 drivers/block/drbd/drbd_vli.h val = le64_to_cpu(val) << (8 - bs->cur.bit); val 309 drivers/block/drbd/drbd_vli.h val |= bs->cur.b[0] >> bs->cur.bit; val 312 drivers/block/drbd/drbd_vli.h val &= ~0ULL >> (64 - bits); val 315 drivers/block/drbd/drbd_vli.h *out = val; val 108 drivers/block/null_blk_main.c static int null_param_store_val(const char *str, int *val, int min, int max) val 119 drivers/block/null_blk_main.c *val = new_val; val 207 drivers/block/null_blk_main.c static inline ssize_t nullb_device_uint_attr_show(unsigned int val, char *page) val 209 drivers/block/null_blk_main.c return snprintf(page, PAGE_SIZE, "%u\n", val); val 212 drivers/block/null_blk_main.c static inline ssize_t nullb_device_ulong_attr_show(unsigned long val, val 215 drivers/block/null_blk_main.c return snprintf(page, PAGE_SIZE, "%lu\n", val); val 218 drivers/block/null_blk_main.c static inline ssize_t nullb_device_bool_attr_show(bool val, char *page) val 220 drivers/block/null_blk_main.c return snprintf(page, PAGE_SIZE, "%u\n", val); val 223 drivers/block/null_blk_main.c static ssize_t nullb_device_uint_attr_store(unsigned int *val, val 233 drivers/block/null_blk_main.c *val = tmp; val 237 drivers/block/null_blk_main.c static ssize_t nullb_device_ulong_attr_store(unsigned long *val, val 247 drivers/block/null_blk_main.c *val = tmp; val 251 drivers/block/null_blk_main.c static ssize_t nullb_device_bool_attr_store(bool *val, const char *page, val 261 drivers/block/null_blk_main.c *val = tmp; val 38 drivers/block/paride/aten.c static void aten_write_regr( PIA *pi, int cont, int regr, int val) val 44 drivers/block/paride/aten.c w0(r); w2(0xe); w2(6); w0(val); w2(7); w2(6); w2(0xc); val 79 drivers/block/paride/bpck.c static void bpck_write_regr( PIA *pi, int cont, int regr, int val ) val 90 drivers/block/paride/bpck.c w0(val); val 97 drivers/block/paride/bpck.c w0(val); w2(1); w2(3); w2(0); val 72 drivers/block/paride/bpck6.c static void bpck6_write_regr(PIA *pi, int cont, int reg, int val) val 77 drivers/block/paride/bpck6.c ppc6_wr_port(PPCSTRUCT(pi),cont?reg|8:reg,(u8)val); val 71 drivers/block/paride/comm.c static void comm_write_regr( PIA *pi, int cont, int regr, int val ) val 80 drivers/block/paride/comm.c case 1: w0(r); P1; w0(val); P2; val 85 drivers/block/paride/comm.c case 4: w3(r); (void)r1(); w4(val); val 74 drivers/block/paride/dstr.c static void dstr_write_regr( PIA *pi, int cont, int regr, int val ) val 87 drivers/block/paride/dstr.c case 1: w0(val); w2(5); w2(7); w2(5); w2(4); val 92 drivers/block/paride/dstr.c case 4: w4(val); val 47 drivers/block/paride/epat.c static void epat_write_regr( PIA *pi, int cont, int regr, int val) val 57 drivers/block/paride/epat.c case 2: w0(0x60+r); w2(1); w0(val); w2(4); val 62 drivers/block/paride/epat.c case 5: w3(0x40+r); w4(val); val 82 drivers/block/paride/epia.c static void epia_write_regr( PIA *pi, int cont, int regr, int val) val 93 drivers/block/paride/epia.c w0(r); w2(1); w0(val); w2(3); w2(4); val 99 drivers/block/paride/epia.c w3(r); w4(val); w2(4); val 40 drivers/block/paride/fit2.c static void fit2_write_regr( PIA *pi, int cont, int regr, int val) val 43 drivers/block/paride/fit2.c w2(0xc); w0(regr); w2(4); w0(val); w2(5); w0(0); w2(4); val 42 drivers/block/paride/fit3.c static void fit3_write_regr( PIA *pi, int cont, int regr, int val) val 50 drivers/block/paride/fit3.c w0(val); w2(0xd); val 55 drivers/block/paride/fit3.c w4(val); w4(0); val 66 drivers/block/paride/friq.c static void friq_write_regr( PIA *pi, int cont, int regr, int val) val 73 drivers/block/paride/friq.c w0(val); val 63 drivers/block/paride/frpw.c static void frpw_write_regr( PIA *pi, int cont, int regr, int val) val 70 drivers/block/paride/frpw.c w0(val); val 75 drivers/block/paride/kbic.c static void kbic_write_regr( PIA *pi, int cont, int regr, int val) val 86 drivers/block/paride/kbic.c w0(val); w2(5); w2(4); val 92 drivers/block/paride/kbic.c w4(val); w4(val); val 32 drivers/block/paride/ktti.c static void ktti_write_regr( PIA *pi, int cont, int regr, int val) val 39 drivers/block/paride/ktti.c w0(val); w2(3); w0(0); w2(6); w2(0xb); val 59 drivers/block/paride/on20.c static void on20_write_regr( PIA *pi, int cont, int regr, int val ) val 66 drivers/block/paride/on20.c op(0); vl(val); val 67 drivers/block/paride/on20.c op(0); vl(val); val 76 drivers/block/paride/on26.c static void on26_write_regr( PIA *pi, int cont, int regr, int val ) val 86 drivers/block/paride/on26.c w0(val); P2; w0(val); P2; val 93 drivers/block/paride/on26.c w2(5); w4(val); w2(4); val 94 drivers/block/paride/on26.c w2(5); w4(val); w2(4); val 45 drivers/block/paride/paride.c void pi_write_regr(PIA * pi, int cont, int regr, int val) val 47 drivers/block/paride/paride.c pi->proto->write_regr(pi, cont, regr, val); val 83 drivers/block/paride/paride.h extern void pi_write_regr(PIA *pi, int cont, int regr, int val); val 372 drivers/block/paride/pcd.c static inline void write_reg(struct pcd_unit *cd, int reg, int val) val 374 drivers/block/paride/pcd.c pi_write_regr(cd->pi, 0, reg, val); val 269 drivers/block/paride/pd.c static inline void write_status(struct pd_unit *disk, int val) val 271 drivers/block/paride/pd.c pi_write_regr(disk->pi, 1, 6, val); val 274 drivers/block/paride/pd.c static inline void write_reg(struct pd_unit *disk, int reg, int val) val 276 drivers/block/paride/pd.c pi_write_regr(disk->pi, 0, reg, val); val 421 drivers/block/paride/pf.c static inline void write_reg(struct pf_unit *pf, int reg, int val) val 423 drivers/block/paride/pf.c pi_write_regr(pf->pi, 0, reg, val); val 273 drivers/block/paride/pg.c static inline void write_reg(struct pg *dev, int reg, int val) val 275 drivers/block/paride/pg.c pi_write_regr(dev->pi, 0, reg, val); val 262 drivers/block/paride/pt.c static inline void write_reg(struct pi_adapter *pi, int reg, int val) val 264 drivers/block/paride/pt.c pi_write_regr(pi, 0, reg, val); val 271 drivers/block/pktcdvd.c int val; val 281 drivers/block/pktcdvd.c && sscanf(data, "%d", &val) == 1) { val 283 drivers/block/pktcdvd.c pd->write_congestion_off = val; val 289 drivers/block/pktcdvd.c && sscanf(data, "%d", &val) == 1) { val 291 drivers/block/pktcdvd.c pd->write_congestion_on = val; val 1809 drivers/block/rbd.c static void __rbd_object_map_set(struct rbd_device *rbd_dev, u64 objno, u8 val) val 1816 drivers/block/rbd.c rbd_assert(!(val & ~OBJ_MASK)); val 1820 drivers/block/rbd.c *p = (*p & ~(OBJ_MASK << shift)) | (val << shift); val 285 drivers/block/skd_main.c u32 val = readl(skdev->mem_map[1] + offset); val 288 drivers/block/skd_main.c dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val); val 289 drivers/block/skd_main.c return val; val 292 drivers/block/skd_main.c static inline void skd_reg_write32(struct skd_device *skdev, u32 val, val 295 drivers/block/skd_main.c writel(val, skdev->mem_map[1] + offset); val 297 drivers/block/skd_main.c dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val); val 300 drivers/block/skd_main.c static inline void skd_reg_write64(struct skd_device *skdev, u64 val, val 303 drivers/block/skd_main.c writeq(val, skdev->mem_map[1] + offset); val 306 drivers/block/skd_main.c val); val 2031 drivers/block/skd_main.c u32 val; val 2034 drivers/block/skd_main.c val = FIT_ISH_FW_STATE_CHANGE + val 2039 drivers/block/skd_main.c SKD_WRITEL(skdev, ~val, FIT_INT_MASK_HOST); val 2040 drivers/block/skd_main.c dev_dbg(&skdev->pdev->dev, "interrupt mask=0x%x\n", ~val); val 2042 drivers/block/skd_main.c val = SKD_READL(skdev, FIT_CONTROL); val 2043 drivers/block/skd_main.c val |= FIT_CR_ENABLE_INTERRUPTS; val 2044 drivers/block/skd_main.c dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val); val 2045 drivers/block/skd_main.c SKD_WRITEL(skdev, val, FIT_CONTROL); val 2056 drivers/block/skd_main.c u32 val; val 2058 drivers/block/skd_main.c val = SKD_READL(skdev, FIT_CONTROL); val 2059 drivers/block/skd_main.c val |= (FIT_CR_SOFT_RESET); val 2060 drivers/block/skd_main.c dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val); val 2061 drivers/block/skd_main.c SKD_WRITEL(skdev, val, FIT_CONTROL); val 225 drivers/block/xsysace.c void (*out) (struct ace_device * ace, int reg, u16 val); val 237 drivers/block/xsysace.c static void ace_out_8(struct ace_device *ace, int reg, u16 val) val 240 drivers/block/xsysace.c out_8(r, val); val 241 drivers/block/xsysace.c out_8(r + 1, val >> 8); val 277 drivers/block/xsysace.c static void ace_out_be16(struct ace_device *ace, int reg, u16 val) val 279 drivers/block/xsysace.c out_be16(ace->baseaddr + reg, val); val 306 drivers/block/xsysace.c static void ace_out_le16(struct ace_device *ace, int reg, u16 val) val 308 drivers/block/xsysace.c out_le16(ace->baseaddr + reg, val); val 353 drivers/block/xsysace.c static inline void ace_out(struct ace_device *ace, int reg, u16 val) val 355 drivers/block/xsysace.c ace->reg_ops->out(ace, reg, val); val 358 drivers/block/xsysace.c static inline void ace_out32(struct ace_device *ace, int reg, u32 val) val 360 drivers/block/xsysace.c ace_out(ace, reg, val); val 361 drivers/block/xsysace.c ace_out(ace, reg + 2, val >> 16); val 490 drivers/block/xsysace.c u16 val; val 547 drivers/block/xsysace.c val = ace_in(ace, ACE_CTRL); val 548 drivers/block/xsysace.c ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ); val 587 drivers/block/xsysace.c val = ace_in(ace, ACE_CTRL); val 588 drivers/block/xsysace.c ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); val 690 drivers/block/xsysace.c val = ace_in(ace, ACE_CTRL); val 691 drivers/block/xsysace.c ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); val 935 drivers/block/xsysace.c u16 val; val 943 drivers/block/xsysace.c val = ace_in(ace, ACE_CTRL); val 944 drivers/block/xsysace.c ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ); val 983 drivers/block/xsysace.c u16 val; val 1072 drivers/block/xsysace.c val = ace_in(ace, ACE_CTRL); val 1073 drivers/block/xsysace.c val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ; val 1074 drivers/block/xsysace.c ace_out(ace, ACE_CTRL, val); val 212 drivers/block/zram/zram_drv.c unsigned long val; val 215 drivers/block/zram/zram_drv.c val = page[0]; val 218 drivers/block/zram/zram_drv.c if (val != page[pos]) val 222 drivers/block/zram/zram_drv.c *element = val; val 230 drivers/block/zram/zram_drv.c u32 val; val 234 drivers/block/zram/zram_drv.c val = init_done(zram); val 237 drivers/block/zram/zram_drv.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 270 drivers/block/zram/zram_drv.c unsigned long val; val 273 drivers/block/zram/zram_drv.c err = kstrtoul(buf, 10, &val); val 274 drivers/block/zram/zram_drv.c if (err || val != 0) val 325 drivers/block/zram/zram_drv.c u64 val; val 328 drivers/block/zram/zram_drv.c if (kstrtoull(buf, 10, &val)) val 333 drivers/block/zram/zram_drv.c zram->wb_limit_enable = val; val 344 drivers/block/zram/zram_drv.c bool val; val 349 drivers/block/zram/zram_drv.c val = zram->wb_limit_enable; val 353 drivers/block/zram/zram_drv.c return scnprintf(buf, PAGE_SIZE, "%d\n", val); val 360 drivers/block/zram/zram_drv.c u64 val; val 363 drivers/block/zram/zram_drv.c if (kstrtoull(buf, 10, &val)) val 368 drivers/block/zram/zram_drv.c zram->bd_wb_limit = val; val 379 drivers/block/zram/zram_drv.c u64 val; val 384 drivers/block/zram/zram_drv.c val = zram->bd_wb_limit; val 388 drivers/block/zram/zram_drv.c return scnprintf(buf, PAGE_SIZE, "%llu\n", val); val 389 drivers/bluetooth/btintel.c void *val, size_t val_size) val 445 drivers/bluetooth/btintel.c memcpy(val, rp->data, val_size); val 454 drivers/bluetooth/btintel.c const void *val, size_t val_size) val 488 drivers/bluetooth/btintel.c memcpy(&cp->data, val, val_size); val 1607 drivers/bluetooth/btusb.c u8 val = 0x00; val 1611 drivers/bluetooth/btusb.c skb = __hci_cmd_sync(hdev, 0xfc3b, 1, &val, HCI_INIT_TIMEOUT); val 2887 drivers/bluetooth/btusb.c static int btusb_mtk_reg_read(struct btusb_data *data, u32 reg, u32 *val) val 2904 drivers/bluetooth/btusb.c *val = get_unaligned_le32(buf); val 128 drivers/bus/brcmstb_gisb.c static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg) val 136 drivers/bus/brcmstb_gisb.c iowrite32be(val, gdev->base + offset); val 138 drivers/bus/brcmstb_gisb.c iowrite32(val, gdev->base + offset); val 160 drivers/bus/brcmstb_gisb.c int val, ret; val 162 drivers/bus/brcmstb_gisb.c ret = kstrtoint(buf, 10, &val); val 166 drivers/bus/brcmstb_gisb.c if (val == 0 || val >= 0xffffffff) val 170 drivers/bus/brcmstb_gisb.c gisb_write(gdev, val, ARB_TIMER); val 149 drivers/bus/da8xx-mstpri.c u32 val; val 169 drivers/bus/da8xx-mstpri.c .val = 0, val 173 drivers/bus/da8xx-mstpri.c .val = 0, val 177 drivers/bus/da8xx-mstpri.c .val = 1, val 240 drivers/bus/da8xx-mstpri.c reg |= prio->val << prio_descr->shift; val 99 drivers/bus/fsl-mc/dprc.c cmd_params->irq_val = cpu_to_le32(irq_cfg->val); val 410 drivers/bus/fsl-mc/dprc.c cmd_params->irq_val = cpu_to_le32(irq_cfg->val); val 80 drivers/bus/fsl-mc/fsl-mc-msi.c irq_cfg.val = msi_desc->msg.data; val 272 drivers/bus/fsl-mc/fsl-mc-private.h u32 val; val 241 drivers/bus/hisi_lpc.c u32 val, size_t dwidth) val 251 drivers/bus/hisi_lpc.c val = cpu_to_le32(val); val 253 drivers/bus/hisi_lpc.c buf = (const unsigned char *)&val; val 92 drivers/bus/imx-weim.c u32 val; val 102 drivers/bus/imx-weim.c of_property_for_each_u32(np, "ranges", prop, p, val) { val 104 drivers/bus/imx-weim.c cs = val; val 105 drivers/bus/imx-weim.c } else if (i % 4 == 3 && val) { val 106 drivers/bus/imx-weim.c val = (val / SZ_32M) | 1; val 107 drivers/bus/imx-weim.c gprval |= val << cs * 3; val 208 drivers/bus/moxtet.c u32 val; val 218 drivers/bus/moxtet.c ret = of_property_read_u32(nc, "reg", &val); val 225 drivers/bus/moxtet.c dev->idx = val; val 422 drivers/bus/moxtet.c int moxtet_device_write(struct device *dev, u8 val) val 433 drivers/bus/moxtet.c moxtet->tx[moxtet->count - mdev->idx] = val; val 234 drivers/bus/qcom-ebi2.c u32 val; val 239 drivers/bus/qcom-ebi2.c val = readl(ebi2_base); val 240 drivers/bus/qcom-ebi2.c val |= csd->enable_mask; val 241 drivers/bus/qcom-ebi2.c writel(val, ebi2_base); val 252 drivers/bus/qcom-ebi2.c ret = of_property_read_u32(np, xp->prop, &val); val 260 drivers/bus/qcom-ebi2.c if (xp->max == 1 && val) { val 270 drivers/bus/qcom-ebi2.c if (val > xp->max) { val 273 drivers/bus/qcom-ebi2.c xp->prop, val, xp->max); val 274 drivers/bus/qcom-ebi2.c val = xp->max; val 277 drivers/bus/qcom-ebi2.c slowcfg |= (val << xp->shift); val 279 drivers/bus/qcom-ebi2.c fastcfg |= (val << xp->shift); val 280 drivers/bus/qcom-ebi2.c dev_dbg(dev, "set %s to %u\n", xp->prop, val); val 303 drivers/bus/qcom-ebi2.c u32 val; val 346 drivers/bus/qcom-ebi2.c val = readl(ebi2_base); val 347 drivers/bus/qcom-ebi2.c val &= ~EBI2_CSN_MASK; val 348 drivers/bus/qcom-ebi2.c writel(val, ebi2_base); val 400 drivers/bus/sunxi-rsb.c unsigned int *val) val 408 drivers/bus/sunxi-rsb.c return sunxi_rsb_read(rdev->rsb, rdev->rtaddr, reg, val, ctx->size); val 412 drivers/bus/sunxi-rsb.c unsigned int val) val 417 drivers/bus/sunxi-rsb.c return sunxi_rsb_write(rdev->rsb, rdev->rtaddr, reg, &val, ctx->size); val 132 drivers/bus/ti-sysc.c u32 val; val 134 drivers/bus/ti-sysc.c val = readw_relaxed(ddata->module_va + offset); val 141 drivers/bus/ti-sysc.c val |= tmp << 16; val 144 drivers/bus/ti-sysc.c return val; val 1412 drivers/bus/ti-sysc.c u16 val; val 1414 drivers/bus/ti-sysc.c val = sysc_read(ddata, offset); val 1415 drivers/bus/ti-sysc.c val |= BIT(5); val 1416 drivers/bus/ti-sysc.c sysc_write(ddata, offset, val); val 1431 drivers/bus/ti-sysc.c u16 val; val 1440 drivers/bus/ti-sysc.c val = sysc_read(ddata, offset); val 1442 drivers/bus/ti-sysc.c val |= BIT(15); val 1444 drivers/bus/ti-sysc.c val &= ~BIT(15); val 1445 drivers/bus/ti-sysc.c sysc_write(ddata, offset, val); val 1462 drivers/bus/ti-sysc.c u32 val = BIT(31); /* THALIA_INT_BYPASS */ val 1464 drivers/bus/ti-sysc.c sysc_write(ddata, offset, val); val 1471 drivers/bus/ti-sysc.c u32 val; val 1477 drivers/bus/ti-sysc.c error = readl_poll_timeout(ddata->module_va + wps, val, val 1478 drivers/bus/ti-sysc.c !(val & 0x10), 100, val 1484 drivers/bus/ti-sysc.c error = readl_poll_timeout(ddata->module_va + wps, val, val 1485 drivers/bus/ti-sysc.c !(val & 0x10), 100, val 1739 drivers/bus/ti-sysc.c u32 val; val 1741 drivers/bus/ti-sysc.c error = of_property_read_u32(np, "ti,sysc-mask", &val); val 1745 drivers/bus/ti-sysc.c ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; val 1756 drivers/bus/ti-sysc.c u32 val; val 1758 drivers/bus/ti-sysc.c of_property_for_each_u32(np, name, prop, p, val) { val 1759 drivers/bus/ti-sysc.c if (val >= SYSC_NR_IDLEMODES) { val 1760 drivers/bus/ti-sysc.c dev_err(ddata->dev, "invalid idlemode: %i\n", val); val 1763 drivers/bus/ti-sysc.c *idlemodes |= (1 << val); val 1797 drivers/bus/ti-sysc.c u32 val; val 1799 drivers/bus/ti-sysc.c error = of_property_read_u32(np, "ti,syss-mask", &val); val 1809 drivers/bus/ti-sysc.c if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) val 1812 drivers/bus/ti-sysc.c ddata->cfg.syss_mask = val; val 2091 drivers/bus/ti-sysc.c u32 val; val 2096 drivers/bus/ti-sysc.c error = of_property_read_u32(np, "ti,sysc-delay-us", &val); val 2098 drivers/bus/ti-sysc.c if (val > 255) { val 2100 drivers/bus/ti-sysc.c val); val 2103 drivers/bus/ti-sysc.c ddata->cfg.srst_udelay = (u8)val; val 136 drivers/bus/ts-nbus.c static int ts_nbus_read_byte(struct ts_nbus *ts_nbus, u8 *val) val 141 drivers/bus/ts-nbus.c *val = 0; val 147 drivers/bus/ts-nbus.c *val |= BIT(i); val 171 drivers/bus/ts-nbus.c static int ts_nbus_read_bus(struct ts_nbus *ts_nbus, u8 *val) val 176 drivers/bus/ts-nbus.c return ts_nbus_read_byte(ts_nbus, val); val 184 drivers/bus/ts-nbus.c static void ts_nbus_write_bus(struct ts_nbus *ts_nbus, int cmd, u8 val) val 191 drivers/bus/ts-nbus.c ts_nbus_write_byte(ts_nbus, val); val 199 drivers/bus/ts-nbus.c int ts_nbus_read(struct ts_nbus *ts_nbus, u8 adr, u16 *val) val 218 drivers/bus/ts-nbus.c *val = 0; val 227 drivers/bus/ts-nbus.c *val |= byte << (i * 8); val 246 drivers/bus/ts-nbus.c int ts_nbus_write(struct ts_nbus *ts_nbus, u8 adr, u16 val) val 261 drivers/bus/ts-nbus.c ts_nbus_write_bus(ts_nbus, TS_NBUS_WRITE_VAL, (u8)(val >> (i * 8))); val 137 drivers/bus/uniphier-system-bus.c u32 base, end, mask, val; val 159 drivers/bus/uniphier-system-bus.c val = UNIPHIER_SBC_BASE_DUMMY; val 161 drivers/bus/uniphier-system-bus.c val = 0; val 165 drivers/bus/uniphier-system-bus.c val = base & 0xfffe0000; val 166 drivers/bus/uniphier-system-bus.c val |= (~mask >> 16) & 0xfffe; val 167 drivers/bus/uniphier-system-bus.c val |= UNIPHIER_SBC_BASE_BE; val 169 drivers/bus/uniphier-system-bus.c dev_dbg(priv->dev, "SBC_BASE[%d] = 0x%08x\n", i, val); val 171 drivers/bus/uniphier-system-bus.c writel(val, base_reg + UNIPHIER_SBC_STRIDE * i); val 47 drivers/bus/vexpress-config.c const char *name, u32 *val) val 50 drivers/bus/vexpress-config.c *val = 0; val 54 drivers/bus/vexpress-config.c if (of_property_read_u32(node, name, val) == 0) { val 3454 drivers/cdrom/cdrom.c static int cdrom_print_info(const char *header, int val, char *info, val 3483 drivers/cdrom/cdrom.c "\t%d", CDROM_CAN(val) != 0); val 56 drivers/char/agp/i460-agp.c #define WR_GATT(index, val) writel((val), (u32 *) i460.gatt + (index)) val 192 drivers/char/ds1620.c static int cvt_9_to_int(unsigned int val) val 194 drivers/char/ds1620.c if (val & 0x100) val 195 drivers/char/ds1620.c val |= 0xfffffe00; val 197 drivers/char/ds1620.c return val; val 623 drivers/char/dtlk.c char val = 0; val 627 drivers/char/dtlk.c val = dtlk_write_tts(*buf++); val 629 drivers/char/dtlk.c return val; val 53 drivers/char/hw_random/bcm2835-rng.c static inline void rng_writel(struct bcm2835_rng_priv *priv, u32 val, val 57 drivers/char/hw_random/bcm2835-rng.c __raw_writel(val, priv->base + offset); val 59 drivers/char/hw_random/bcm2835-rng.c writel(val, priv->base + offset); val 89 drivers/char/hw_random/bcm2835-rng.c u32 val; val 99 drivers/char/hw_random/bcm2835-rng.c val = rng_readl(priv, RNG_INT_MASK); val 100 drivers/char/hw_random/bcm2835-rng.c val |= RNG_INT_OFF; val 101 drivers/char/hw_random/bcm2835-rng.c rng_writel(priv, val, RNG_INT_MASK); val 59 drivers/char/hw_random/exynos-trng.c int val; val 66 drivers/char/hw_random/exynos-trng.c val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val, val 67 drivers/char/hw_random/exynos-trng.c val == 0, 200, 1000000); val 68 drivers/char/hw_random/exynos-trng.c if (val < 0) val 69 drivers/char/hw_random/exynos-trng.c return val; val 80 drivers/char/hw_random/exynos-trng.c u32 val; val 88 drivers/char/hw_random/exynos-trng.c val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2); val 89 drivers/char/hw_random/exynos-trng.c if (val > 0x7fff) { val 90 drivers/char/hw_random/exynos-trng.c dev_err(trng->dev, "clock divider too large: %d", val); val 93 drivers/char/hw_random/exynos-trng.c val = val << 1; val 94 drivers/char/hw_random/exynos-trng.c writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV); val 97 drivers/char/hw_random/exynos-trng.c val = EXYNOS_TRNG_CTRL_RNGEN; val 98 drivers/char/hw_random/exynos-trng.c writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL); val 37 drivers/char/hw_random/hisi-rng.c int val = RNG_EN; val 51 drivers/char/hw_random/hisi-rng.c val |= RNG_RING_EN | RNG_SEED_SEL; val 53 drivers/char/hw_random/hisi-rng.c writel_relaxed(val, hrng->base + RNG_CTRL); val 59 drivers/char/hw_random/iproc-rng200.c uint32_t val; val 62 drivers/char/hw_random/iproc-rng200.c val = ioread32(rng_base + RNG_CTRL_OFFSET); val 63 drivers/char/hw_random/iproc-rng200.c val &= ~RNG_CTRL_RNG_RBGEN_MASK; val 64 drivers/char/hw_random/iproc-rng200.c val |= RNG_CTRL_RNG_RBGEN_DISABLE; val 65 drivers/char/hw_random/iproc-rng200.c iowrite32(val, rng_base + RNG_CTRL_OFFSET); val 71 drivers/char/hw_random/iproc-rng200.c val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); val 72 drivers/char/hw_random/iproc-rng200.c val |= RBG_SOFT_RESET; val 73 drivers/char/hw_random/iproc-rng200.c iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET); val 75 drivers/char/hw_random/iproc-rng200.c val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); val 76 drivers/char/hw_random/iproc-rng200.c val |= RNG_SOFT_RESET; val 77 drivers/char/hw_random/iproc-rng200.c iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET); val 79 drivers/char/hw_random/iproc-rng200.c val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); val 80 drivers/char/hw_random/iproc-rng200.c val &= ~RNG_SOFT_RESET; val 81 drivers/char/hw_random/iproc-rng200.c iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET); val 83 drivers/char/hw_random/iproc-rng200.c val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); val 84 drivers/char/hw_random/iproc-rng200.c val &= ~RBG_SOFT_RESET; val 85 drivers/char/hw_random/iproc-rng200.c iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET); val 88 drivers/char/hw_random/iproc-rng200.c val = ioread32(rng_base + RNG_CTRL_OFFSET); val 89 drivers/char/hw_random/iproc-rng200.c val &= ~RNG_CTRL_RNG_RBGEN_MASK; val 90 drivers/char/hw_random/iproc-rng200.c val |= RNG_CTRL_RNG_RBGEN_ENABLE; val 91 drivers/char/hw_random/iproc-rng200.c iowrite32(val, rng_base + RNG_CTRL_OFFSET); val 158 drivers/char/hw_random/iproc-rng200.c uint32_t val; val 161 drivers/char/hw_random/iproc-rng200.c val = ioread32(priv->base + RNG_CTRL_OFFSET); val 162 drivers/char/hw_random/iproc-rng200.c val &= ~RNG_CTRL_RNG_RBGEN_MASK; val 163 drivers/char/hw_random/iproc-rng200.c val |= RNG_CTRL_RNG_RBGEN_ENABLE; val 164 drivers/char/hw_random/iproc-rng200.c iowrite32(val, priv->base + RNG_CTRL_OFFSET); val 172 drivers/char/hw_random/iproc-rng200.c uint32_t val; val 175 drivers/char/hw_random/iproc-rng200.c val = ioread32(priv->base + RNG_CTRL_OFFSET); val 176 drivers/char/hw_random/iproc-rng200.c val &= ~RNG_CTRL_RNG_RBGEN_MASK; val 177 drivers/char/hw_random/iproc-rng200.c val |= RNG_CTRL_RNG_RBGEN_DISABLE; val 178 drivers/char/hw_random/iproc-rng200.c iowrite32(val, priv->base + RNG_CTRL_OFFSET); val 44 drivers/char/hw_random/mtk-rng.c u32 val; val 51 drivers/char/hw_random/mtk-rng.c val = readl(priv->base + RNG_CTRL); val 52 drivers/char/hw_random/mtk-rng.c val |= RNG_EN; val 53 drivers/char/hw_random/mtk-rng.c writel(val, priv->base + RNG_CTRL); val 61 drivers/char/hw_random/mtk-rng.c u32 val; val 63 drivers/char/hw_random/mtk-rng.c val = readl(priv->base + RNG_CTRL); val 64 drivers/char/hw_random/mtk-rng.c val &= ~RNG_EN; val 65 drivers/char/hw_random/mtk-rng.c writel(val, priv->base + RNG_CTRL); val 308 drivers/char/hw_random/n2-drv.c u64 val = 0; val 311 drivers/char/hw_random/n2-drv.c val = ((2 << RNG_v1_CTL_ASEL_SHIFT) | val 317 drivers/char/hw_random/n2-drv.c val |= (1 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES1; val 320 drivers/char/hw_random/n2-drv.c val |= (2 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES2; val 323 drivers/char/hw_random/n2-drv.c val |= (3 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES3; val 326 drivers/char/hw_random/n2-drv.c val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3; val 333 drivers/char/hw_random/n2-drv.c val = ((2 << RNG_v2_CTL_ASEL_SHIFT) | val 339 drivers/char/hw_random/n2-drv.c val |= (1 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES1; val 342 drivers/char/hw_random/n2-drv.c val |= (2 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES2; val 345 drivers/char/hw_random/n2-drv.c val |= (3 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES3; val 348 drivers/char/hw_random/n2-drv.c val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3; val 355 drivers/char/hw_random/n2-drv.c return val; val 485 drivers/char/hw_random/n2-drv.c static u64 advance_polynomial(u64 poly, u64 val, int count) val 490 drivers/char/hw_random/n2-drv.c int highbit_set = ((s64)val < 0); val 492 drivers/char/hw_random/n2-drv.c val <<= 1; val 494 drivers/char/hw_random/n2-drv.c val ^= poly; val 497 drivers/char/hw_random/n2-drv.c return val; val 500 drivers/char/hw_random/n2-drv.c static int n2rng_test_buffer_find(struct n2rng *np, u64 val) val 506 drivers/char/hw_random/n2-drv.c if (np->test_buffer[i] == val) val 523 drivers/char/hw_random/n2-drv.c u64 val; val 531 drivers/char/hw_random/n2-drv.c val = RNG_v1_SELFTEST_VAL; val 534 drivers/char/hw_random/n2-drv.c val = RNG_v2_SELFTEST_VAL; val 540 drivers/char/hw_random/n2-drv.c matches += n2rng_test_buffer_find(np, val); val 543 drivers/char/hw_random/n2-drv.c val = advance_polynomial(SELFTEST_POLY, val, 1); val 169 drivers/char/hw_random/omap-rng.c u32 val) val 171 drivers/char/hw_random/omap-rng.c __raw_writel(val, priv->base + priv->pdata->regs[reg]); val 254 drivers/char/hw_random/omap-rng.c u32 val; val 265 drivers/char/hw_random/omap-rng.c val = 0x5 << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT; val 270 drivers/char/hw_random/omap-rng.c val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT; val 271 drivers/char/hw_random/omap-rng.c omap_rng_write(priv, RNG_CONFIG_REG, val); val 278 drivers/char/hw_random/omap-rng.c val = RNG_CONTROL_ENABLE_TRNG_MASK; val 279 drivers/char/hw_random/omap-rng.c omap_rng_write(priv, RNG_CONTROL_REG, val); val 286 drivers/char/hw_random/omap-rng.c u32 val; val 292 drivers/char/hw_random/omap-rng.c val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT; val 293 drivers/char/hw_random/omap-rng.c val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT; val 294 drivers/char/hw_random/omap-rng.c omap_rng_write(priv, RNG_CONFIG_REG, val); val 298 drivers/char/hw_random/omap-rng.c val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT; val 299 drivers/char/hw_random/omap-rng.c val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT; val 300 drivers/char/hw_random/omap-rng.c omap_rng_write(priv, RNG_ALARMCNT_REG, val); val 302 drivers/char/hw_random/omap-rng.c val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT; val 303 drivers/char/hw_random/omap-rng.c val |= RNG_CONTROL_ENABLE_TRNG_MASK; val 304 drivers/char/hw_random/omap-rng.c omap_rng_write(priv, RNG_CONTROL_REG, val); val 311 drivers/char/hw_random/omap-rng.c int val; val 313 drivers/char/hw_random/omap-rng.c val = omap_rng_read(priv, RNG_CONTROL_REG); val 314 drivers/char/hw_random/omap-rng.c val &= ~RNG_CONTROL_ENABLE_TRNG_MASK; val 315 drivers/char/hw_random/omap-rng.c omap_rng_write(priv, RNG_CONTROL_REG, val); val 60 drivers/char/hw_random/tx4939-rng.c static void write_rng(u64 val, void __iomem *base, unsigned int offset) val 62 drivers/char/hw_random/tx4939-rng.c return ____raw_writeq(val, base + offset); val 120 drivers/char/hw_random/xgene-rng.c u32 val; val 122 drivers/char/hw_random/xgene-rng.c val = readl(ctx->csr_base + RNG_INTR_STS_ACK); val 123 drivers/char/hw_random/xgene-rng.c if (val & MONOBIT_FAIL_MASK) val 129 drivers/char/hw_random/xgene-rng.c dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val); val 130 drivers/char/hw_random/xgene-rng.c if (val & POKER_FAIL_MASK) val 137 drivers/char/hw_random/xgene-rng.c dev_err(ctx->dev, "test poker failure error 0x%08X\n", val); val 138 drivers/char/hw_random/xgene-rng.c if (val & LONG_RUN_FAIL_MASK) val 143 drivers/char/hw_random/xgene-rng.c dev_err(ctx->dev, "test long run failure error 0x%08X\n", val); val 144 drivers/char/hw_random/xgene-rng.c if (val & RUN_FAIL_MASK) val 150 drivers/char/hw_random/xgene-rng.c dev_err(ctx->dev, "test run failure error 0x%08X\n", val); val 151 drivers/char/hw_random/xgene-rng.c if (val & NOISE_FAIL_MASK) val 153 drivers/char/hw_random/xgene-rng.c dev_err(ctx->dev, "noise failure error 0x%08X\n", val); val 154 drivers/char/hw_random/xgene-rng.c if (val & STUCK_OUT_MASK) val 159 drivers/char/hw_random/xgene-rng.c dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val); val 161 drivers/char/hw_random/xgene-rng.c if (val & SHUTDOWN_OFLO_MASK) { val 181 drivers/char/hw_random/xgene-rng.c val); val 198 drivers/char/hw_random/xgene-rng.c writel(val, ctx->csr_base + RNG_INTR_STS_ACK); val 214 drivers/char/hw_random/xgene-rng.c u32 i, val = 0; val 217 drivers/char/hw_random/xgene-rng.c val = readl(ctx->csr_base + RNG_INTR_STS_ACK); val 218 drivers/char/hw_random/xgene-rng.c if ((val & READY_MASK) || !wait) val 223 drivers/char/hw_random/xgene-rng.c return (val & READY_MASK); val 242 drivers/char/hw_random/xgene-rng.c u32 val; val 246 drivers/char/hw_random/xgene-rng.c val = MAX_REFILL_CYCLES_SET(0, 10); val 247 drivers/char/hw_random/xgene-rng.c val = MIN_REFILL_CYCLES_SET(val, 10); val 248 drivers/char/hw_random/xgene-rng.c writel(val, ctx->csr_base + RNG_CONFIG); val 250 drivers/char/hw_random/xgene-rng.c val = ALARM_THRESHOLD_SET(0, 0xFF); val 251 drivers/char/hw_random/xgene-rng.c writel(val, ctx->csr_base + RNG_ALARMCNT); val 264 drivers/char/hw_random/xgene-rng.c val = ENABLE_RNG_SET(0, 1); val 265 drivers/char/hw_random/xgene-rng.c val = MONOBIT_FAIL_MASK_SET(val, 1); val 266 drivers/char/hw_random/xgene-rng.c val = POKER_FAIL_MASK_SET(val, 1); val 267 drivers/char/hw_random/xgene-rng.c val = LONG_RUN_FAIL_MASK_SET(val, 1); val 268 drivers/char/hw_random/xgene-rng.c val = RUN_FAIL_MASK_SET(val, 1); val 269 drivers/char/hw_random/xgene-rng.c val = NOISE_FAIL_MASK_SET(val, 1); val 270 drivers/char/hw_random/xgene-rng.c val = STUCK_OUT_MASK_SET(val, 1); val 271 drivers/char/hw_random/xgene-rng.c val = SHUTDOWN_OFLO_MASK_SET(val, 1); val 272 drivers/char/hw_random/xgene-rng.c writel(val, ctx->csr_base + RNG_CONTROL); val 80 drivers/char/ipmi/bt-bmc.c uint32_t val = 0; val 83 drivers/char/ipmi/bt-bmc.c rc = regmap_read(bt_bmc->map, bt_bmc->offset + reg, &val); val 86 drivers/char/ipmi/bt-bmc.c return rc == 0 ? (u8) val : 0; val 236 drivers/char/ipmi/ipmb_dev_int.c enum i2c_slave_event event, u8 *val) val 271 drivers/char/ipmi/ipmb_dev_int.c buf[++ipmb_dev->msg_idx] = *val; val 353 drivers/char/ipmi/ipmi_devintf.c struct ipmi_cmdspec val; val 355 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 360 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_register_for_cmd(priv->user, val.netfn, val.cmd, val 367 drivers/char/ipmi/ipmi_devintf.c struct ipmi_cmdspec val; val 369 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 374 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_unregister_for_cmd(priv->user, val.netfn, val.cmd, val 381 drivers/char/ipmi/ipmi_devintf.c struct ipmi_cmdspec_chans val; val 383 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 388 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_register_for_cmd(priv->user, val.netfn, val.cmd, val 389 drivers/char/ipmi/ipmi_devintf.c val.chans); val 395 drivers/char/ipmi/ipmi_devintf.c struct ipmi_cmdspec_chans val; val 397 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 402 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_unregister_for_cmd(priv->user, val.netfn, val.cmd, val 403 drivers/char/ipmi/ipmi_devintf.c val.chans); val 409 drivers/char/ipmi/ipmi_devintf.c int val; val 411 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 416 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_set_gets_events(priv->user, val); val 423 drivers/char/ipmi/ipmi_devintf.c unsigned int val; val 425 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 430 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_set_my_address(priv->user, 0, val); val 436 drivers/char/ipmi/ipmi_devintf.c unsigned int val; val 443 drivers/char/ipmi/ipmi_devintf.c val = rval; val 445 drivers/char/ipmi/ipmi_devintf.c if (copy_to_user(arg, &val, sizeof(val))) { val 454 drivers/char/ipmi/ipmi_devintf.c unsigned int val; val 456 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 461 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_set_my_LUN(priv->user, 0, val); val 467 drivers/char/ipmi/ipmi_devintf.c unsigned int val; val 474 drivers/char/ipmi/ipmi_devintf.c val = rval; val 476 drivers/char/ipmi/ipmi_devintf.c if (copy_to_user(arg, &val, sizeof(val))) { val 485 drivers/char/ipmi/ipmi_devintf.c struct ipmi_channel_lun_address_set val; val 487 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 492 drivers/char/ipmi/ipmi_devintf.c return ipmi_set_my_address(priv->user, val.channel, val.value); val 498 drivers/char/ipmi/ipmi_devintf.c struct ipmi_channel_lun_address_set val; val 500 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 505 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_get_my_address(priv->user, val.channel, &val.value); val 509 drivers/char/ipmi/ipmi_devintf.c if (copy_to_user(arg, &val, sizeof(val))) { val 518 drivers/char/ipmi/ipmi_devintf.c struct ipmi_channel_lun_address_set val; val 520 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 525 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_set_my_LUN(priv->user, val.channel, val.value); val 531 drivers/char/ipmi/ipmi_devintf.c struct ipmi_channel_lun_address_set val; val 533 drivers/char/ipmi/ipmi_devintf.c if (copy_from_user(&val, arg, sizeof(val))) { val 538 drivers/char/ipmi/ipmi_devintf.c rv = ipmi_get_my_LUN(priv->user, val.channel, &val.value); val 542 drivers/char/ipmi/ipmi_devintf.c if (copy_to_user(arg, &val, sizeof(val))) { val 83 drivers/char/ipmi/ipmi_msghandler.c static int panic_op_write_handler(const char *val, val 89 drivers/char/ipmi/ipmi_msghandler.c strncpy(valcp, val, 15); val 1549 drivers/char/ipmi/ipmi_msghandler.c int ipmi_set_gets_events(struct ipmi_user *user, bool val) val 1564 drivers/char/ipmi/ipmi_msghandler.c if (user->gets_events == val) val 1567 drivers/char/ipmi/ipmi_msghandler.c user->gets_events = val; val 1569 drivers/char/ipmi/ipmi_msghandler.c if (val) { val 4484 drivers/char/ipmi/ipmi_msghandler.c static void smi_recv_tasklet(unsigned long val) val 4487 drivers/char/ipmi/ipmi_msghandler.c struct ipmi_smi *intf = (struct ipmi_smi *) val; val 50 drivers/char/ipmi/ipmi_poweroff.c static int set_param_ifnum(const char *val, const struct kernel_param *kp) val 52 drivers/char/ipmi/ipmi_poweroff.c int rv = param_set_int(val, kp); val 17 drivers/char/ipmi/ipmi_si_hotmod.c static int hotmod_handler(const char *val, const struct kernel_param *kp); val 37 drivers/char/ipmi/ipmi_si_hotmod.c const int val; val 59 drivers/char/ipmi/ipmi_si_hotmod.c static int parse_str(const struct hotmod_vals *v, unsigned int *val, char *name, val 74 drivers/char/ipmi/ipmi_si_hotmod.c *val = v[i].val; val 85 drivers/char/ipmi/ipmi_si_hotmod.c const char *name, unsigned int *val) val 94 drivers/char/ipmi/ipmi_si_hotmod.c *val = simple_strtoul(option, &n, 0); val 186 drivers/char/ipmi/ipmi_si_hotmod.c static int hotmod_handler(const char *val, const struct kernel_param *kp) val 188 drivers/char/ipmi/ipmi_si_hotmod.c char *str = kstrdup(val, GFP_KERNEL), *curr, *next; val 114 drivers/char/ipmi/ipmi_watchdog.c #define WDOG_SET_TIMEOUT(byte1, byte2, val) \ val 115 drivers/char/ipmi/ipmi_watchdog.c (byte1) = (((val) * 10) & 0xff), (byte2) = (((val) * 10) >> 8) val 176 drivers/char/ipmi/ipmi_watchdog.c static int set_param_timeout(const char *val, const struct kernel_param *kp) val 182 drivers/char/ipmi/ipmi_watchdog.c if (!val) val 184 drivers/char/ipmi/ipmi_watchdog.c l = simple_strtoul(val, &endp, 0); val 185 drivers/char/ipmi/ipmi_watchdog.c if (endp == val) val 208 drivers/char/ipmi/ipmi_watchdog.c static int set_param_str(const char *val, const struct kernel_param *kp) val 215 drivers/char/ipmi/ipmi_watchdog.c strncpy(valcp, val, 15); val 244 drivers/char/ipmi/ipmi_watchdog.c static int set_param_wdog_ifnum(const char *val, const struct kernel_param *kp) val 246 drivers/char/ipmi/ipmi_watchdog.c int rv = param_set_int(val, kp); val 668 drivers/char/ipmi/ipmi_watchdog.c int val; val 676 drivers/char/ipmi/ipmi_watchdog.c i = copy_from_user(&val, argp, sizeof(int)); val 679 drivers/char/ipmi/ipmi_watchdog.c timeout = val; val 689 drivers/char/ipmi/ipmi_watchdog.c i = copy_from_user(&val, argp, sizeof(int)); val 692 drivers/char/ipmi/ipmi_watchdog.c pretimeout = val; val 705 drivers/char/ipmi/ipmi_watchdog.c i = copy_from_user(&val, argp, sizeof(int)); val 708 drivers/char/ipmi/ipmi_watchdog.c if (val & WDIOS_DISABLECARD) { val 714 drivers/char/ipmi/ipmi_watchdog.c if (val & WDIOS_ENABLECARD) { val 721 drivers/char/ipmi/ipmi_watchdog.c val = 0; val 722 drivers/char/ipmi/ipmi_watchdog.c i = copy_to_user(argp, &val, sizeof(val)); val 1098 drivers/char/ipmi/ipmi_watchdog.c ipmi_nmi(unsigned int val, struct pt_regs *regs) val 68 drivers/char/ipmi/kcs_bmc.c static void update_status_bits(struct kcs_bmc *kcs_bmc, u8 mask, u8 val) val 73 drivers/char/ipmi/kcs_bmc.c tmp |= val & mask; val 72 drivers/char/ipmi/kcs_bmc_aspeed.c u32 val = 0; val 75 drivers/char/ipmi/kcs_bmc_aspeed.c rc = regmap_read(priv->map, reg, &val); val 78 drivers/char/ipmi/kcs_bmc_aspeed.c return rc == 0 ? (u8) val : 0; val 82 drivers/char/ipmi/kcs_bmc_npcm7xx.c u32 val = 0; val 85 drivers/char/ipmi/kcs_bmc_npcm7xx.c rc = regmap_read(priv->map, reg, &val); val 88 drivers/char/ipmi/kcs_bmc_npcm7xx.c return rc == 0 ? (u8)val : 0; val 76 drivers/char/mwave/3780i.c unsigned short val; val 85 drivers/char/mwave/3780i.c val = InWordDsp(DSP_MsaDataDSISHigh); val 88 drivers/char/mwave/3780i.c PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val); val 90 drivers/char/mwave/3780i.c return val; val 480 drivers/char/mwave/3780i.c unsigned short val; val 497 drivers/char/mwave/3780i.c val = InWordDsp(DSP_MsaDataDSISHigh); val 499 drivers/char/mwave/3780i.c if(put_user(val, pusBuffer++)) val 504 drivers/char/mwave/3780i.c uCount, val); val 522 drivers/char/mwave/3780i.c unsigned short val; val 539 drivers/char/mwave/3780i.c val = InWordDsp(DSP_ReadAndClear); val 541 drivers/char/mwave/3780i.c if(put_user(val, pusBuffer++)) val 546 drivers/char/mwave/3780i.c uCount, val); val 579 drivers/char/mwave/3780i.c unsigned short val; val 580 drivers/char/mwave/3780i.c if(get_user(val, pusBuffer++)) val 583 drivers/char/mwave/3780i.c OutWordDsp(DSP_MsaDataDSISHigh, val); val 588 drivers/char/mwave/3780i.c uCount, val); val 81 drivers/char/pc8736x_gpio.c static inline void superio_outb(int addr, int val) val 84 drivers/char/pc8736x_gpio.c outb_p(val, superio_cmd + 1); val 155 drivers/char/pc8736x_gpio.c int port, bit, val; val 159 drivers/char/pc8736x_gpio.c val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN); val 160 drivers/char/pc8736x_gpio.c val >>= bit; val 161 drivers/char/pc8736x_gpio.c val &= 1; val 165 drivers/char/pc8736x_gpio.c val); val 167 drivers/char/pc8736x_gpio.c return val; val 170 drivers/char/pc8736x_gpio.c static void pc8736x_gpio_set(unsigned minor, int val) val 181 drivers/char/pc8736x_gpio.c curval, bit, (curval & ~(1 << bit)), val, (val << bit)); val 183 drivers/char/pc8736x_gpio.c val = (curval & ~(1 << bit)) | (val << bit); val 186 drivers/char/pc8736x_gpio.c " %2x -> %2x\n", minor, port, bit, curval, val); val 188 drivers/char/pc8736x_gpio.c outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT); val 191 drivers/char/pc8736x_gpio.c val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN); val 193 drivers/char/pc8736x_gpio.c dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val); val 194 drivers/char/pc8736x_gpio.c pc8736x_gpio_shadow[port] = val; val 175 drivers/char/pcmcia/cm4000_cs.c static inline void xoutb(unsigned char val, unsigned short port) val 177 drivers/char/pcmcia/cm4000_cs.c pr_debug("outb(val=%.2x,port=%.4x)\n", val, port); val 178 drivers/char/pcmcia/cm4000_cs.c outb(val, port); val 182 drivers/char/pcmcia/cm4000_cs.c unsigned char val; val 184 drivers/char/pcmcia/cm4000_cs.c val = inb(port); val 185 drivers/char/pcmcia/cm4000_cs.c pr_debug("%.2x=inb(%.4x)\n", val, port); val 187 drivers/char/pcmcia/cm4000_cs.c return val; val 89 drivers/char/pcmcia/cm4040_cs.c static inline void xoutb(unsigned char val, unsigned short port) val 91 drivers/char/pcmcia/cm4040_cs.c pr_debug("outb(val=%.2x,port=%.4x)\n", val, port); val 92 drivers/char/pcmcia/cm4040_cs.c outb(val, port); val 97 drivers/char/pcmcia/cm4040_cs.c unsigned char val; val 99 drivers/char/pcmcia/cm4040_cs.c val = inb(port); val 100 drivers/char/pcmcia/cm4040_cs.c pr_debug("%.2x=inb(%.4x)\n", val, port); val 101 drivers/char/pcmcia/cm4040_cs.c return val; val 169 drivers/char/pcmcia/cm4040_cs.c static int write_sync_reg(unsigned char val, struct reader_dev *dev) val 178 drivers/char/pcmcia/cm4040_cs.c xoutb(val, iobase + REG_OFFSET_SYNC_CONTROL); val 321 drivers/char/pcmcia/synclink_cs.c #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg)) val 325 drivers/char/pcmcia/synclink_cs.c #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg)) val 1868 drivers/char/pcmcia/synclink_cs.c unsigned char val; val 1874 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, PVR) & 0x0f; val 1877 drivers/char/pcmcia/synclink_cs.c case MGSL_INTERFACE_RS232: val |= PVR_RS232; break; val 1878 drivers/char/pcmcia/synclink_cs.c case MGSL_INTERFACE_V35: val |= PVR_V35; break; val 1879 drivers/char/pcmcia/synclink_cs.c case MGSL_INTERFACE_RS422: val |= PVR_RS422; break; val 1881 drivers/char/pcmcia/synclink_cs.c write_reg(info, PVR, val); val 2872 drivers/char/pcmcia/synclink_cs.c unsigned char val; val 2897 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f; val 2898 drivers/char/pcmcia/synclink_cs.c val |= ((M << 4) & 0xc0); val 2899 drivers/char/pcmcia/synclink_cs.c write_reg(info, (unsigned char) (channel + CCR2), val); val 2907 drivers/char/pcmcia/synclink_cs.c unsigned char val; val 2921 drivers/char/pcmcia/synclink_cs.c val = 0x82; val 2925 drivers/char/pcmcia/synclink_cs.c val |= BIT2; val 2926 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHB + MODE, val); val 2994 drivers/char/pcmcia/synclink_cs.c unsigned char val; val 2997 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); val 2998 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + CCR1, val); val 3001 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); val 3002 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + CCR2, val); val 3011 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + MODE) | BIT0; val 3012 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + MODE, val); val 3017 drivers/char/pcmcia/synclink_cs.c unsigned char val; val 3062 drivers/char/pcmcia/synclink_cs.c val = 0x82; val 3064 drivers/char/pcmcia/synclink_cs.c val |= BIT0; val 3068 drivers/char/pcmcia/synclink_cs.c val |= BIT2; val 3069 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + MODE, val); val 3081 drivers/char/pcmcia/synclink_cs.c val = 0xc0; val 3085 drivers/char/pcmcia/synclink_cs.c val |= BIT3; val 3088 drivers/char/pcmcia/synclink_cs.c val |= BIT4; val 3091 drivers/char/pcmcia/synclink_cs.c val |= BIT4 | BIT2; val 3094 drivers/char/pcmcia/synclink_cs.c val |= BIT4 | BIT3; val 3097 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + CCR0, val); val 3110 drivers/char/pcmcia/synclink_cs.c val = 0x10 + clkmode; val 3111 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + CCR1, val); val 3125 drivers/char/pcmcia/synclink_cs.c val = 0x00; val 3128 drivers/char/pcmcia/synclink_cs.c val |= BIT5; val 3130 drivers/char/pcmcia/synclink_cs.c val |= BIT4; val 3132 drivers/char/pcmcia/synclink_cs.c val |= BIT1; val 3134 drivers/char/pcmcia/synclink_cs.c val |= BIT0; val 3135 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + CCR2, val); val 3149 drivers/char/pcmcia/synclink_cs.c val = 0x00; val 3151 drivers/char/pcmcia/synclink_cs.c val |= BIT2 | BIT1; val 3153 drivers/char/pcmcia/synclink_cs.c val |= BIT5; val 3157 drivers/char/pcmcia/synclink_cs.c val |= BIT6; val 3160 drivers/char/pcmcia/synclink_cs.c val |= BIT6; val 3163 drivers/char/pcmcia/synclink_cs.c val |= BIT7 | BIT6; val 3166 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + CCR3, val); val 3169 drivers/char/pcmcia/synclink_cs.c val = 0; val 3172 drivers/char/pcmcia/synclink_cs.c case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; val 3173 drivers/char/pcmcia/synclink_cs.c case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break; val 3174 drivers/char/pcmcia/synclink_cs.c case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break; val 3175 drivers/char/pcmcia/synclink_cs.c case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; val 3177 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + PRE, val); val 3190 drivers/char/pcmcia/synclink_cs.c val = 0x50; val 3191 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + CCR4, val); val 3214 drivers/char/pcmcia/synclink_cs.c val = 0x00; val 3216 drivers/char/pcmcia/synclink_cs.c val |= BIT5; val 3217 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + XBCH, val); val 3388 drivers/char/pcmcia/synclink_cs.c unsigned char val; val 3408 drivers/char/pcmcia/synclink_cs.c val = 0x06; val 3410 drivers/char/pcmcia/synclink_cs.c val |= BIT0; val 3414 drivers/char/pcmcia/synclink_cs.c val |= BIT6; val 3415 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + MODE, val); val 3486 drivers/char/pcmcia/synclink_cs.c val = 0x00; val 3488 drivers/char/pcmcia/synclink_cs.c val |= BIT0; /* 7 bits */ val 3490 drivers/char/pcmcia/synclink_cs.c val |= BIT5; val 3493 drivers/char/pcmcia/synclink_cs.c val |= BIT2; /* Parity enable */ val 3495 drivers/char/pcmcia/synclink_cs.c val |= BIT3; val 3497 drivers/char/pcmcia/synclink_cs.c val |= BIT4; val 3499 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + DAFO, val); val 3531 drivers/char/pcmcia/synclink_cs.c val = 0x00; val 3533 drivers/char/pcmcia/synclink_cs.c val |= BIT5; val 3534 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + XBCH, val); val 3592 drivers/char/pcmcia/synclink_cs.c unsigned char val; val 3594 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + MODE); val 3597 drivers/char/pcmcia/synclink_cs.c val &= ~BIT6; val 3599 drivers/char/pcmcia/synclink_cs.c val |= BIT6; val 3602 drivers/char/pcmcia/synclink_cs.c val |= BIT2; val 3604 drivers/char/pcmcia/synclink_cs.c val &= ~BIT2; val 3606 drivers/char/pcmcia/synclink_cs.c write_reg(info, CHA + MODE, val); val 635 drivers/char/rtc.c unsigned char val; val 669 drivers/char/rtc.c val = CMOS_READ(RTC_FREQ_SELECT) & 0xf0; val 670 drivers/char/rtc.c val |= (16 - tmp); val 671 drivers/char/rtc.c CMOS_WRITE(val, RTC_FREQ_SELECT); val 1282 drivers/char/rtc.c unsigned char val; val 1286 drivers/char/rtc.c val = CMOS_READ(RTC_CONTROL); val 1287 drivers/char/rtc.c val &= ~bit; val 1288 drivers/char/rtc.c CMOS_WRITE(val, RTC_CONTROL); val 1296 drivers/char/rtc.c unsigned char val; val 1300 drivers/char/rtc.c val = CMOS_READ(RTC_CONTROL); val 1301 drivers/char/rtc.c val |= bit; val 1302 drivers/char/rtc.c CMOS_WRITE(val, RTC_CONTROL); val 145 drivers/char/tlclk.c #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port) val 330 drivers/char/tlclk.c unsigned char val; val 336 drivers/char/tlclk.c val = (unsigned char)tmp; val 338 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG1, 0xef, val); val 352 drivers/char/tlclk.c unsigned char val; val 358 drivers/char/tlclk.c val = (unsigned char)tmp; val 360 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG1, 0xdf, val << 1); val 374 drivers/char/tlclk.c unsigned char val; val 380 drivers/char/tlclk.c val = (unsigned char)tmp; val 382 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7); val 396 drivers/char/tlclk.c unsigned char val; val 401 drivers/char/tlclk.c val = (unsigned char)tmp; val 403 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6); val 417 drivers/char/tlclk.c unsigned char val; val 422 drivers/char/tlclk.c val = (unsigned char)tmp; val 424 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3); val 439 drivers/char/tlclk.c unsigned char val; val 444 drivers/char/tlclk.c val = (unsigned char)tmp; val 446 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2); val 460 drivers/char/tlclk.c unsigned char val; val 465 drivers/char/tlclk.c val = (unsigned char)tmp; val 467 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1); val 481 drivers/char/tlclk.c unsigned char val; val 486 drivers/char/tlclk.c val = (unsigned char)tmp; val 488 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG2, 0xfe, val); val 502 drivers/char/tlclk.c unsigned char val; val 507 drivers/char/tlclk.c val = (unsigned char)tmp; val 509 drivers/char/tlclk.c if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) { val 511 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val); val 512 drivers/char/tlclk.c } else if (val >= CLK_8_592MHz) { val 514 drivers/char/tlclk.c switch (val) { val 529 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3); val 543 drivers/char/tlclk.c unsigned char val; val 549 drivers/char/tlclk.c val = (unsigned char)tmp; val 551 drivers/char/tlclk.c if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) { val 553 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val); val 554 drivers/char/tlclk.c } else if (val >= CLK_8_592MHz) { val 556 drivers/char/tlclk.c switch (val) { val 571 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG3, 0xf8, val); val 585 drivers/char/tlclk.c unsigned char val; val 591 drivers/char/tlclk.c val = (unsigned char)tmp; val 593 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG1, 0xfe, val); val 606 drivers/char/tlclk.c unsigned char val; val 612 drivers/char/tlclk.c val = (unsigned char)tmp; val 614 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG1, 0xfd, val); val 627 drivers/char/tlclk.c unsigned char val; val 633 drivers/char/tlclk.c val = (unsigned char)tmp; val 635 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG0, 0xfb, val); val 647 drivers/char/tlclk.c unsigned char val; val 653 drivers/char/tlclk.c val = (unsigned char)tmp; val 655 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG0, 0xbf, val); val 668 drivers/char/tlclk.c unsigned char val; val 674 drivers/char/tlclk.c val = (unsigned char)tmp; val 676 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG0, 0x7f, val); val 708 drivers/char/tlclk.c unsigned char val; val 714 drivers/char/tlclk.c val = (unsigned char)tmp; val 716 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG0, 0xcf, val); val 728 drivers/char/tlclk.c unsigned char val; val 734 drivers/char/tlclk.c val = (unsigned char)tmp; val 736 drivers/char/tlclk.c SET_PORT_BITS(TLCLK_REG4, 0xfd, val); val 32 drivers/char/tpm/tpm_atmel.h #define atmel_putb(val, priv, offset) writeb(val, priv->iobase + offset) val 84 drivers/char/tpm/tpm_atmel.h #define atmel_putb(val, chip, offset) \ val 85 drivers/char/tpm/tpm_atmel.h outb(val, atmel_get_priv(chip)->base + offset) val 70 drivers/char/tpm/tpm_nsc.c static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data) val 77 drivers/char/tpm/tpm_nsc.c if ((*data & mask) == val) val 85 drivers/char/tpm/tpm_nsc.c if ((*data & mask) == val) val 39 drivers/clk/actions/owl-divider.c unsigned long val; val 43 drivers/clk/actions/owl-divider.c val = reg >> div_hw->shift; val 44 drivers/clk/actions/owl-divider.c val &= (1 << div_hw->width) - 1; val 47 drivers/clk/actions/owl-divider.c val, div_hw->table, val 66 drivers/clk/actions/owl-divider.c unsigned long val; val 69 drivers/clk/actions/owl-divider.c val = divider_get_val(rate, parent_rate, div_hw->table, val 76 drivers/clk/actions/owl-divider.c reg | (val << div_hw->shift)); val 23 drivers/clk/actions/owl-factor.c if (clkt->val > maxval) val 24 drivers/clk/actions/owl-factor.c maxval = clkt->val; val 29 drivers/clk/actions/owl-factor.c unsigned int val, unsigned int *mul, unsigned int *div) val 34 drivers/clk/actions/owl-factor.c if (clkt->val == val) { val 48 drivers/clk/actions/owl-factor.c int val = -1; val 56 drivers/clk/actions/owl-factor.c val = clkt->val; val 61 drivers/clk/actions/owl-factor.c if (val == -1) val 62 drivers/clk/actions/owl-factor.c val = _get_table_maxval(table); val 64 drivers/clk/actions/owl-factor.c return val; val 90 drivers/clk/actions/owl-factor.c __func__, clkt->val, clkt->mul, clkt->div, val 98 drivers/clk/actions/owl-factor.c return clkt->val; val 105 drivers/clk/actions/owl-factor.c bestval = clkt->val; val 126 drivers/clk/actions/owl-factor.c unsigned int val, mul = 0, div = 1; val 128 drivers/clk/actions/owl-factor.c val = owl_clk_val_best(factor_hw, &common->hw, rate, parent_rate); val 129 drivers/clk/actions/owl-factor.c _get_table_div_mul(clkt, val, &mul, &div); val 150 drivers/clk/actions/owl-factor.c u32 reg, val, mul, div; val 157 drivers/clk/actions/owl-factor.c val = reg >> factor_hw->shift; val 158 drivers/clk/actions/owl-factor.c val &= div_mask(factor_hw); val 160 drivers/clk/actions/owl-factor.c _get_table_div_mul(clkt, val, &mul, &div); val 189 drivers/clk/actions/owl-factor.c u32 val, reg; val 191 drivers/clk/actions/owl-factor.c val = _get_table_val(factor_hw->table, rate, parent_rate); val 193 drivers/clk/actions/owl-factor.c if (val > div_mask(factor_hw)) val 194 drivers/clk/actions/owl-factor.c val = div_mask(factor_hw); val 199 drivers/clk/actions/owl-factor.c reg |= val << factor_hw->shift; val 17 drivers/clk/actions/owl-factor.h unsigned int val; val 32 drivers/clk/actions/owl-pll.c unsigned int val) val 37 drivers/clk/actions/owl-pll.c if (clkt->val == val) val 87 drivers/clk/actions/owl-pll.c u32 val; val 90 drivers/clk/actions/owl-pll.c regmap_read(common->regmap, pll_hw->reg, &val); val 92 drivers/clk/actions/owl-pll.c val = val >> pll_hw->shift; val 93 drivers/clk/actions/owl-pll.c val &= mul_mask(pll_hw); val 95 drivers/clk/actions/owl-pll.c return _get_table_rate(pll_hw->table, val); val 102 drivers/clk/actions/owl-pll.c regmap_read(common->regmap, pll_hw->reg, &val); val 104 drivers/clk/actions/owl-pll.c val = val >> pll_hw->shift; val 105 drivers/clk/actions/owl-pll.c val &= mul_mask(pll_hw); val 107 drivers/clk/actions/owl-pll.c return pll_hw->bfreq * val; val 162 drivers/clk/actions/owl-pll.c u32 val, reg; val 170 drivers/clk/actions/owl-pll.c val = clkt->val; val 172 drivers/clk/actions/owl-pll.c val = owl_pll_calculate_mul(pll_hw, rate); val 178 drivers/clk/actions/owl-pll.c reg |= val << pll_hw->shift; val 20 drivers/clk/actions/owl-pll.h unsigned int val; val 30 drivers/clk/at91/clk-i2s-mux.c u32 val; val 32 drivers/clk/at91/clk-i2s-mux.c regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val); val 34 drivers/clk/at91/clk-i2s-mux.c return (val & BIT(mux->bus_id)) >> mux->bus_id; val 73 drivers/clk/at91/clk-sam9x60-pll.c u32 val; val 78 drivers/clk/at91/clk-sam9x60-pll.c regmap_read(regmap, PMC_PLL_CTRL0, &val); val 79 drivers/clk/at91/clk-sam9x60-pll.c div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val); val 81 drivers/clk/at91/clk-sam9x60-pll.c regmap_read(regmap, PMC_PLL_CTRL1, &val); val 82 drivers/clk/at91/clk-sam9x60-pll.c mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val); val 91 drivers/clk/at91/clk-sam9x60-pll.c val = PMC_PLL_ACR_DEFAULT; val 92 drivers/clk/at91/clk-sam9x60-pll.c regmap_write(regmap, PMC_PLL_ACR, val); val 99 drivers/clk/at91/clk-sam9x60-pll.c val |= PMC_PLL_ACR_UTMIBG; val 100 drivers/clk/at91/clk-sam9x60-pll.c regmap_write(regmap, PMC_PLL_ACR, val); val 105 drivers/clk/at91/clk-sam9x60-pll.c val |= PMC_PLL_ACR_UTMIVR; val 106 drivers/clk/at91/clk-sam9x60-pll.c regmap_write(regmap, PMC_PLL_ACR, val); val 68 drivers/clk/axs10x/i2s_pll_clock.c unsigned int val) val 70 drivers/clk/axs10x/i2s_pll_clock.c writel_relaxed(val, clk->base + reg); val 84 drivers/clk/axs10x/i2s_pll_clock.c static inline unsigned int i2s_pll_get_value(unsigned int val) val 86 drivers/clk/axs10x/i2s_pll_clock.c return (val & 0x3F) + ((val >> 6) & 0x3F); val 103 drivers/clk/axs10x/pll_clock.c u32 val) val 105 drivers/clk/axs10x/pll_clock.c iowrite32(val, clk->base + reg); val 333 drivers/clk/bcm/clk-bcm2835.c static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) val 335 drivers/clk/bcm/clk-bcm2835.c writel(CM_PASSWORD | val, cprman->regs + reg); val 78 drivers/clk/bcm/clk-iproc-armpll.c u32 val; val 81 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); val 82 drivers/clk/bcm/clk-iproc-armpll.c if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT)) val 83 drivers/clk/bcm/clk-iproc-armpll.c policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK; val 90 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); val 91 drivers/clk/bcm/clk-iproc-armpll.c fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) & val 94 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); val 96 drivers/clk/bcm/clk-iproc-armpll.c (val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT); val 120 drivers/clk/bcm/clk-iproc-armpll.c u32 val; val 131 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); val 132 drivers/clk/bcm/clk-iproc-armpll.c mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK; val 138 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); val 139 drivers/clk/bcm/clk-iproc-armpll.c mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK; val 153 drivers/clk/bcm/clk-iproc-armpll.c u32 val; val 156 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); val 157 drivers/clk/bcm/clk-iproc-armpll.c if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) { val 162 drivers/clk/bcm/clk-iproc-armpll.c ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) & val 167 drivers/clk/bcm/clk-iproc-armpll.c ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK; val 170 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); val 171 drivers/clk/bcm/clk-iproc-armpll.c ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) & val 176 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET); val 177 drivers/clk/bcm/clk-iproc-armpll.c ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK; val 199 drivers/clk/bcm/clk-iproc-armpll.c u32 val; val 205 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); val 206 drivers/clk/bcm/clk-iproc-armpll.c if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) { val 212 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); val 213 drivers/clk/bcm/clk-iproc-armpll.c if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) { val 218 drivers/clk/bcm/clk-iproc-armpll.c pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) & val 50 drivers/clk/bcm/clk-iproc-asiu.c u32 val; val 56 drivers/clk/bcm/clk-iproc-asiu.c val = readl(asiu->gate_base + clk->gate.offset); val 57 drivers/clk/bcm/clk-iproc-asiu.c val |= (1 << clk->gate.en_shift); val 58 drivers/clk/bcm/clk-iproc-asiu.c writel(val, asiu->gate_base + clk->gate.offset); val 67 drivers/clk/bcm/clk-iproc-asiu.c u32 val; val 73 drivers/clk/bcm/clk-iproc-asiu.c val = readl(asiu->gate_base + clk->gate.offset); val 74 drivers/clk/bcm/clk-iproc-asiu.c val &= ~(1 << clk->gate.en_shift); val 75 drivers/clk/bcm/clk-iproc-asiu.c writel(val, asiu->gate_base + clk->gate.offset); val 83 drivers/clk/bcm/clk-iproc-asiu.c u32 val; val 92 drivers/clk/bcm/clk-iproc-asiu.c val = readl(asiu->div_base + clk->div.offset); val 93 drivers/clk/bcm/clk-iproc-asiu.c if ((val & (1 << clk->div.en_shift)) == 0) { val 99 drivers/clk/bcm/clk-iproc-asiu.c div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); val 101 drivers/clk/bcm/clk-iproc-asiu.c div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); val 135 drivers/clk/bcm/clk-iproc-asiu.c u32 val; val 142 drivers/clk/bcm/clk-iproc-asiu.c val = readl(asiu->div_base + clk->div.offset); val 143 drivers/clk/bcm/clk-iproc-asiu.c val &= ~(1 << clk->div.en_shift); val 144 drivers/clk/bcm/clk-iproc-asiu.c writel(val, asiu->div_base + clk->div.offset); val 156 drivers/clk/bcm/clk-iproc-asiu.c val = readl(asiu->div_base + clk->div.offset); val 157 drivers/clk/bcm/clk-iproc-asiu.c val |= 1 << clk->div.en_shift; val 159 drivers/clk/bcm/clk-iproc-asiu.c val &= ~(bit_mask(clk->div.high_width) val 161 drivers/clk/bcm/clk-iproc-asiu.c val |= div_h << clk->div.high_shift; val 163 drivers/clk/bcm/clk-iproc-asiu.c val &= ~(bit_mask(clk->div.high_width) val 167 drivers/clk/bcm/clk-iproc-asiu.c val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); val 168 drivers/clk/bcm/clk-iproc-asiu.c val |= div_l << clk->div.low_shift; val 170 drivers/clk/bcm/clk-iproc-asiu.c val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); val 172 drivers/clk/bcm/clk-iproc-asiu.c writel(val, asiu->div_base + clk->div.offset); val 163 drivers/clk/bcm/clk-iproc-pll.c u32 val = readl(pll->status_base + ctrl->status.offset); val 165 drivers/clk/bcm/clk-iproc-pll.c if (val & (1 << ctrl->status.shift)) val 174 drivers/clk/bcm/clk-iproc-pll.c const u32 offset, u32 val) val 178 drivers/clk/bcm/clk-iproc-pll.c writel(val, base + offset); val 182 drivers/clk/bcm/clk-iproc-pll.c val = readl(base + offset); val 188 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 191 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->asiu_base + ctrl->asiu.offset); val 192 drivers/clk/bcm/clk-iproc-pll.c val &= ~(1 << ctrl->asiu.en_shift); val 193 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); val 197 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->aon.offset); val 198 drivers/clk/bcm/clk-iproc-pll.c val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; val 199 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); val 204 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->pwr_base + ctrl->aon.offset); val 205 drivers/clk/bcm/clk-iproc-pll.c val |= 1 << ctrl->aon.iso_shift; val 206 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); val 209 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); val 210 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); val 217 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 220 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->aon.offset); val 221 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); val 222 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); val 227 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->pwr_base + ctrl->aon.offset); val 228 drivers/clk/bcm/clk-iproc-pll.c val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; val 229 drivers/clk/bcm/clk-iproc-pll.c val &= ~(1 << ctrl->aon.iso_shift); val 230 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); val 235 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->asiu_base + ctrl->asiu.offset); val 236 drivers/clk/bcm/clk-iproc-pll.c val |= (1 << ctrl->asiu.en_shift); val 237 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); val 245 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 249 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + reset->offset); val 251 drivers/clk/bcm/clk-iproc-pll.c val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift); val 253 drivers/clk/bcm/clk-iproc-pll.c val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift)); val 254 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, reset->offset, val); val 260 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 265 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + dig_filter->offset); val 266 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | val 269 drivers/clk/bcm/clk-iproc-pll.c val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | val 271 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, dig_filter->offset, val); val 273 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + reset->offset); val 275 drivers/clk/bcm/clk-iproc-pll.c val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift)); val 277 drivers/clk/bcm/clk-iproc-pll.c val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift); val 278 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, reset->offset, val); val 290 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 295 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->status_base + ctrl->status.offset); val 296 drivers/clk/bcm/clk-iproc-pll.c if ((val & (1 << ctrl->status.shift)) == 0) val 299 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_int.offset); val 300 drivers/clk/bcm/clk-iproc-pll.c ndiv_int = (val >> ctrl->ndiv_int.shift) & val 306 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->pdiv.offset); val 307 drivers/clk/bcm/clk-iproc-pll.c pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); val 322 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 367 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_frac.offset); val 368 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->ndiv_frac.width) << val 370 drivers/clk/bcm/clk-iproc-pll.c val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; val 372 drivers/clk/bcm/clk-iproc-pll.c ctrl->ndiv_frac.offset, val); val 382 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->macro_mode.offset); val 383 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->macro_mode.width) << val 385 drivers/clk/bcm/clk-iproc-pll.c val |= PLL_USER_MODE << ctrl->macro_mode.shift; val 387 drivers/clk/bcm/clk-iproc-pll.c ctrl->macro_mode.offset, val); val 392 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->vco_ctrl.l_offset); val 395 drivers/clk/bcm/clk-iproc-pll.c val |= (1 << PLL_VCO_LOW_SHIFT); val 398 drivers/clk/bcm/clk-iproc-pll.c val &= ~(1 << PLL_VCO_HIGH_SHIFT); val 400 drivers/clk/bcm/clk-iproc-pll.c val |= (1 << PLL_VCO_HIGH_SHIFT); val 402 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val); val 405 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_int.offset); val 406 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); val 407 drivers/clk/bcm/clk-iproc-pll.c val |= vco->ndiv_int << ctrl->ndiv_int.shift; val 408 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val); val 412 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_frac.offset); val 413 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->ndiv_frac.width) << val 415 drivers/clk/bcm/clk-iproc-pll.c val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; val 417 drivers/clk/bcm/clk-iproc-pll.c val); val 421 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->pdiv.offset); val 422 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); val 423 drivers/clk/bcm/clk-iproc-pll.c val |= vco->pdiv << ctrl->pdiv.shift; val 424 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val); val 463 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 472 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->status_base + ctrl->status.offset); val 473 drivers/clk/bcm/clk-iproc-pll.c if ((val & (1 << ctrl->status.shift)) == 0) val 481 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_int.offset); val 482 drivers/clk/bcm/clk-iproc-pll.c ndiv_int = (val >> ctrl->ndiv_int.shift) & val 487 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_frac.offset); val 488 drivers/clk/bcm/clk-iproc-pll.c ndiv_frac = (val >> ctrl->ndiv_frac.shift) & val 493 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->pdiv.offset); val 494 drivers/clk/bcm/clk-iproc-pll.c pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); val 590 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 593 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->enable.offset); val 594 drivers/clk/bcm/clk-iproc-pll.c val &= ~(1 << ctrl->enable.enable_shift); val 595 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); val 598 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->enable.offset); val 599 drivers/clk/bcm/clk-iproc-pll.c val &= ~(1 << ctrl->enable.hold_shift); val 600 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); val 610 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 615 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->enable.offset); val 616 drivers/clk/bcm/clk-iproc-pll.c val |= 1 << ctrl->enable.enable_shift; val 617 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); val 626 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 633 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->mdiv.offset); val 634 drivers/clk/bcm/clk-iproc-pll.c mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); val 674 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 687 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->mdiv.offset); val 689 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); val 691 drivers/clk/bcm/clk-iproc-pll.c val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); val 692 drivers/clk/bcm/clk-iproc-pll.c val |= div << ctrl->mdiv.shift; val 694 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val); val 716 drivers/clk/bcm/clk-iproc-pll.c u32 val; val 718 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->sw_ctrl.offset); val 719 drivers/clk/bcm/clk-iproc-pll.c val |= BIT(ctrl->sw_ctrl.shift); val 721 drivers/clk/bcm/clk-iproc-pll.c val); val 48 drivers/clk/bcm/clk-kona.c static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) val 52 drivers/clk/bcm/clk-kona.c return (reg_val & ~mask) | (val << shift); val 197 drivers/clk/bcm/clk-kona.c u32 val; val 200 drivers/clk/bcm/clk-kona.c val = __ccu_read(ccu, reg_offset); val 201 drivers/clk/bcm/clk-kona.c bit_val = (val & bit_mask) != 0; val 63 drivers/clk/bcm/clk-raspberrypi.c __le32 val; val 68 drivers/clk/bcm/clk-raspberrypi.c u32 clk, u32 *val) val 72 drivers/clk/bcm/clk-raspberrypi.c .val = cpu_to_le32(*val), val 81 drivers/clk/bcm/clk-raspberrypi.c *val = le32_to_cpu(msg.val); val 90 drivers/clk/bcm/clk-raspberrypi.c u32 val = 0; val 95 drivers/clk/bcm/clk-raspberrypi.c RPI_FIRMWARE_ARM_CLK_ID, &val); val 99 drivers/clk/bcm/clk-raspberrypi.c return !!(val & RPI_FIRMWARE_STATE_ENABLE_BIT); val 108 drivers/clk/bcm/clk-raspberrypi.c u32 val = 0; val 114 drivers/clk/bcm/clk-raspberrypi.c &val); val 118 drivers/clk/bcm/clk-raspberrypi.c return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE; val 46 drivers/clk/berlin/berlin2-pll.c u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; val 49 drivers/clk/berlin/berlin2-pll.c val = readl_relaxed(pll->base + SPLL_CTRL0); val 50 drivers/clk/berlin/berlin2-pll.c fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; val 51 drivers/clk/berlin/berlin2-pll.c rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK; val 57 drivers/clk/berlin/berlin2-pll.c val = readl_relaxed(pll->base + SPLL_CTRL1); val 58 drivers/clk/berlin/berlin2-pll.c vcodivsel = (val >> map->divsel_shift) & DIVSEL_MASK; val 128 drivers/clk/clk-aspeed.c static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val) val 132 drivers/clk/clk-aspeed.c if (val & AST2400_HPLL_BYPASS_EN) { val 137 drivers/clk/clk-aspeed.c u32 n = (val >> 5) & 0x3f; val 138 drivers/clk/clk-aspeed.c u32 od = (val >> 4) & 0x1; val 139 drivers/clk/clk-aspeed.c u32 d = val & 0xf; val 148 drivers/clk/clk-aspeed.c static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) val 152 drivers/clk/clk-aspeed.c if (val & AST2500_HPLL_BYPASS_EN) { val 157 drivers/clk/clk-aspeed.c u32 p = (val >> 13) & 0x3f; val 158 drivers/clk/clk-aspeed.c u32 m = (val >> 5) & 0xff; val 159 drivers/clk/clk-aspeed.c u32 n = val & 0x1f; val 324 drivers/clk/clk-aspeed.c int ret, val; val 331 drivers/clk/clk-aspeed.c ret = regmap_read(ar->map, reg, &val); val 335 drivers/clk/clk-aspeed.c return !!(val & BIT(bit)); val 388 drivers/clk/clk-aspeed.c u32 val, rate; val 421 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_MISC_CTRL, &val); val 422 drivers/clk/clk-aspeed.c if (val & UART_DIV13_EN) val 436 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_MPLL_PARAM, &val); val 437 drivers/clk/clk-aspeed.c hw = soc_data->calc_pll("mpll", val); val 561 drivers/clk/clk-aspeed.c u32 val, div, clkin, hpll; val 572 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_STRAP, &val); val 573 drivers/clk/clk-aspeed.c rate = (val >> 8) & 3; val 574 drivers/clk/clk-aspeed.c if (val & CLKIN_25MHZ_EN) { val 577 drivers/clk/clk-aspeed.c } else if (val & AST2400_CLK_SOURCE_SEL) { val 592 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_HPLL_PARAM, &val); val 593 drivers/clk/clk-aspeed.c if (val & AST2400_HPLL_PROGRAMMED) val 594 drivers/clk/clk-aspeed.c hw = aspeed_ast2400_calc_pll("hpll", val); val 608 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_STRAP, &val); val 609 drivers/clk/clk-aspeed.c val = (val >> 10) & 0x3; val 610 drivers/clk/clk-aspeed.c div = val + 1; val 629 drivers/clk/clk-aspeed.c u32 val, freq, div; val 632 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_STRAP, &val); val 633 drivers/clk/clk-aspeed.c if (val & CLKIN_25MHZ_EN) val 644 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_HPLL_PARAM, &val); val 645 drivers/clk/clk-aspeed.c aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); val 648 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_STRAP, &val); val 649 drivers/clk/clk-aspeed.c val = (val >> 9) & 0x7; val 650 drivers/clk/clk-aspeed.c WARN(val == 0, "strapping is zero: cannot determine ahb clock"); val 651 drivers/clk/clk-aspeed.c div = 2 * (val + 1); val 656 drivers/clk/clk-aspeed.c regmap_read(map, ASPEED_CLK_SELECTION, &val); val 657 drivers/clk/clk-aspeed.c val = (val >> 23) & 0x7; val 658 drivers/clk/clk-aspeed.c div = 4 * (val + 1); val 666 drivers/clk/clk-aspeed.c u32 val; val 698 drivers/clk/clk-aspeed.c ret = regmap_read(map, ASPEED_STRAP, &val); val 81 drivers/clk/clk-aspeed.h struct clk_hw *(*calc_pll)(const char *name, u32 val); val 158 drivers/clk/clk-ast2600.c static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) val 162 drivers/clk/clk-ast2600.c if (val & BIT(24)) { val 167 drivers/clk/clk-ast2600.c u32 m = val & 0x1fff; val 168 drivers/clk/clk-ast2600.c u32 n = (val >> 13) & 0x3f; val 169 drivers/clk/clk-ast2600.c u32 p = (val >> 19) & 0xf; val 177 drivers/clk/clk-ast2600.c static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) val 181 drivers/clk/clk-ast2600.c if (val & BIT(20)) { val 186 drivers/clk/clk-ast2600.c u32 m = (val >> 5) & 0x3f; val 187 drivers/clk/clk-ast2600.c u32 od = (val >> 4) & 0x1; val 188 drivers/clk/clk-ast2600.c u32 n = val & 0xf; val 338 drivers/clk/clk-ast2600.c u32 val; val 342 drivers/clk/clk-ast2600.c ret = regmap_read(ar->map, reg, &val); val 346 drivers/clk/clk-ast2600.c return !!(val & rst); val 413 drivers/clk/clk-ast2600.c u32 val, rate; val 440 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_G6_MISC_CTRL, &val); val 441 drivers/clk/clk-ast2600.c if (val & UART_DIV13_EN) val 451 drivers/clk/clk-ast2600.c regmap_read(map, 0x80, &val); val 452 drivers/clk/clk-ast2600.c if (val & BIT(31)) val 609 drivers/clk/clk-ast2600.c u32 val, div, chip_id, axi_div, ahb_div; val 617 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_HPLL_PARAM, &val); val 618 drivers/clk/clk-ast2600.c aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val); val 620 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_MPLL_PARAM, &val); val 621 drivers/clk/clk-ast2600.c aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val); val 623 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_DPLL_PARAM, &val); val 624 drivers/clk/clk-ast2600.c aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val); val 626 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_EPLL_PARAM, &val); val 627 drivers/clk/clk-ast2600.c aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val); val 629 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_APLL_PARAM, &val); val 630 drivers/clk/clk-ast2600.c aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val); val 633 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_G6_STRAP1, &val); val 634 drivers/clk/clk-ast2600.c if (val & BIT(16)) val 641 drivers/clk/clk-ast2600.c ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3]; val 643 drivers/clk/clk-ast2600.c ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3]; val 648 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val); val 649 drivers/clk/clk-ast2600.c val = (val >> 23) & 0x7; val 650 drivers/clk/clk-ast2600.c div = 4 * (val + 1); val 654 drivers/clk/clk-ast2600.c regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val); val 655 drivers/clk/clk-ast2600.c val = (val >> 9) & 0x7; val 656 drivers/clk/clk-ast2600.c div = 2 * (val + 1); val 161 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int val) val 163 drivers/clk/clk-axi-clkgen.c writel(val, axi_clkgen->base + reg); val 167 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int *val) val 169 drivers/clk/clk-axi-clkgen.c *val = readl(axi_clkgen->base + reg); val 175 drivers/clk/clk-axi-clkgen.c unsigned int val; val 178 drivers/clk/clk-axi-clkgen.c axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val); val 179 drivers/clk/clk-axi-clkgen.c } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout); val 181 drivers/clk/clk-axi-clkgen.c if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) val 184 drivers/clk/clk-axi-clkgen.c return val & 0xffff; val 188 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int *val) val 206 drivers/clk/clk-axi-clkgen.c *val = ret; val 212 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int val, unsigned int mask) val 226 drivers/clk/clk-axi-clkgen.c reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask); val 236 drivers/clk/clk-axi-clkgen.c unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE; val 239 drivers/clk/clk-axi-clkgen.c val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE; val 241 drivers/clk/clk-axi-clkgen.c axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val); val 113 drivers/clk/clk-cdce706.c unsigned *val) val 115 drivers/clk/clk-cdce706.c int rc = regmap_read(dev_data->regmap, reg | 0x80, val); val 123 drivers/clk/clk-cdce706.c unsigned val) val 125 drivers/clk/clk-cdce706.c int rc = regmap_write(dev_data->regmap, reg | 0x80, val); val 133 drivers/clk/clk-cdce706.c unsigned mask, unsigned val) val 135 drivers/clk/clk-cdce706.c int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val); val 564 drivers/clk/clk-cdce706.c unsigned val; val 566 drivers/clk/clk-cdce706.c ret = cdce706_reg_read(cdce, CDCE706_DIVIDER_PLL(i), &val); val 570 drivers/clk/clk-cdce706.c (val & CDCE706_DIVIDER_PLL_MASK(i)) >> val 573 drivers/clk/clk-cdce706.c ret = cdce706_reg_read(cdce, CDCE706_DIVIDER(i), &val); val 576 drivers/clk/clk-cdce706.c cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK; val 600 drivers/clk/clk-cdce706.c unsigned val; val 602 drivers/clk/clk-cdce706.c ret = cdce706_reg_read(cdce, CDCE706_CLKOUT(i), &val); val 605 drivers/clk/clk-cdce706.c cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK; val 551 drivers/clk/clk-cdce925.c const void *reg, size_t reg_size, void *val, size_t val_size) val 579 drivers/clk/clk-cdce925.c xfer[1].buf = val; val 584 drivers/clk/clk-cdce925.c reg_size, val_size, reg_data[0], *((u8 *)val)); val 27 drivers/clk/clk-clps711x.c { .val = 0, .div = 32, }, val 28 drivers/clk/clk-clps711x.c { .val = 1, .div = 8, }, val 29 drivers/clk/clk-clps711x.c { .val = 2, .div = 2, }, val 30 drivers/clk/clk-clps711x.c { .val = 3, .div = 1, }, val 34 drivers/clk/clk-clps711x.c { .val = 0, .div = 256, }, val 35 drivers/clk/clk-clps711x.c { .val = 1, .div = 1, }, val 99 drivers/clk/clk-cs2000-cp.c #define cs2000_write(priv, addr, val) \ val 100 drivers/clk/clk-cs2000-cp.c i2c_smbus_write_byte_data(priv_to_client(priv), addr, val) val 102 drivers/clk/clk-cs2000-cp.c static int cs2000_bset(struct cs2000_priv *priv, u8 addr, u8 mask, u8 val) val 111 drivers/clk/clk-cs2000-cp.c data |= (val & mask); val 147 drivers/clk/clk-cs2000-cp.c u32 val; val 150 drivers/clk/clk-cs2000-cp.c val = 0x0; val 152 drivers/clk/clk-cs2000-cp.c val = 0x1; val 154 drivers/clk/clk-cs2000-cp.c val = 0x2; val 160 drivers/clk/clk-cs2000-cp.c REFCLKDIV(val)); val 166 drivers/clk/clk-cs2000-cp.c s32 val; val 170 drivers/clk/clk-cs2000-cp.c val = cs2000_read(priv, DEVICE_CTRL); val 171 drivers/clk/clk-cs2000-cp.c if (val < 0) val 172 drivers/clk/clk-cs2000-cp.c return val; val 173 drivers/clk/clk-cs2000-cp.c if (!(val & PLL_UNLOCK)) val 226 drivers/clk/clk-cs2000-cp.c u32 val; val 233 drivers/clk/clk-cs2000-cp.c val = cs2000_rate_to_ratio(rate_in, rate_out); val 237 drivers/clk/clk-cs2000-cp.c Ratio_Val(val, i)); val 248 drivers/clk/clk-cs2000-cp.c u32 val; val 251 drivers/clk/clk-cs2000-cp.c val = 0; val 257 drivers/clk/clk-cs2000-cp.c val |= Val_Ratio(tmp, i); val 260 drivers/clk/clk-cs2000-cp.c return val; val 467 drivers/clk/clk-cs2000-cp.c s32 val; val 470 drivers/clk/clk-cs2000-cp.c val = cs2000_read(priv, DEVICE_ID); val 471 drivers/clk/clk-cs2000-cp.c if (val < 0) val 472 drivers/clk/clk-cs2000-cp.c return val; val 475 drivers/clk/clk-cs2000-cp.c if (val >> 3) val 478 drivers/clk/clk-cs2000-cp.c switch (val & REVISION_MASK) { val 36 drivers/clk/clk-divider.c static inline void clk_div_writel(struct clk_divider *divider, u32 val) val 39 drivers/clk/clk-divider.c iowrite32be(val, divider->reg); val 41 drivers/clk/clk-divider.c writel(val, divider->reg); val 51 drivers/clk/clk-divider.c if (clkt->div > maxdiv && clkt->val <= mask) val 80 drivers/clk/clk-divider.c unsigned int val) val 85 drivers/clk/clk-divider.c if (clkt->val == val) val 91 drivers/clk/clk-divider.c unsigned int val, unsigned long flags, u8 width) val 94 drivers/clk/clk-divider.c return val; val 96 drivers/clk/clk-divider.c return 1 << val; val 98 drivers/clk/clk-divider.c return val ? val : clk_div_mask(width) + 1; val 100 drivers/clk/clk-divider.c return _get_table_div(table, val); val 101 drivers/clk/clk-divider.c return val + 1; val 111 drivers/clk/clk-divider.c return clkt->val; val 130 drivers/clk/clk-divider.c unsigned int val, val 136 drivers/clk/clk-divider.c div = _get_div(table, val, flags, width); val 152 drivers/clk/clk-divider.c unsigned int val; val 154 drivers/clk/clk-divider.c val = clk_div_readl(divider) >> divider->shift; val 155 drivers/clk/clk-divider.c val &= clk_div_mask(divider->width); val 157 drivers/clk/clk-divider.c return divider_recalc_rate(hw, parent_rate, val, divider->table, val 361 drivers/clk/clk-divider.c unsigned long flags, unsigned int val) val 365 drivers/clk/clk-divider.c div = _get_div(table, val, flags, width); val 387 drivers/clk/clk-divider.c u32 val; val 389 drivers/clk/clk-divider.c val = clk_div_readl(divider) >> divider->shift; val 390 drivers/clk/clk-divider.c val &= clk_div_mask(divider->width); val 394 drivers/clk/clk-divider.c val); val 424 drivers/clk/clk-divider.c u32 val; val 437 drivers/clk/clk-divider.c val = clk_div_mask(divider->width) << (divider->shift + 16); val 439 drivers/clk/clk-divider.c val = clk_div_readl(divider); val 440 drivers/clk/clk-divider.c val &= ~(clk_div_mask(divider->width) << divider->shift); val 442 drivers/clk/clk-divider.c val |= (u32)value << divider->shift; val 443 drivers/clk/clk-divider.c clk_div_writel(divider, val); val 25 drivers/clk/clk-fractional-divider.c static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val) val 28 drivers/clk/clk-fractional-divider.c iowrite32be(val, fd->reg); val 30 drivers/clk/clk-fractional-divider.c writel(val, fd->reg); val 39 drivers/clk/clk-fractional-divider.c u32 val; val 47 drivers/clk/clk-fractional-divider.c val = clk_fd_readl(fd); val 54 drivers/clk/clk-fractional-divider.c m = (val & fd->mmask) >> fd->mshift; val 55 drivers/clk/clk-fractional-divider.c n = (val & fd->nmask) >> fd->nshift; val 119 drivers/clk/clk-fractional-divider.c u32 val; val 135 drivers/clk/clk-fractional-divider.c val = clk_fd_readl(fd); val 136 drivers/clk/clk-fractional-divider.c val &= ~(fd->mmask | fd->nmask); val 137 drivers/clk/clk-fractional-divider.c val |= (m << fd->mshift) | (n << fd->nshift); val 138 drivers/clk/clk-fractional-divider.c clk_fd_writel(fd, val); val 34 drivers/clk/clk-gate.c static inline void clk_gate_writel(struct clk_gate *gate, u32 val) val 37 drivers/clk/clk-gate.c iowrite32be(val, gate->reg); val 39 drivers/clk/clk-gate.c writel(val, gate->reg); val 123 drivers/clk/clk-gemini.c u32 val; val 125 drivers/clk/clk-gemini.c regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val); val 126 drivers/clk/clk-gemini.c if (val & PCI_CLK_66MHZ) val 176 drivers/clk/clk-gemini.c unsigned int val; val 178 drivers/clk/clk-gemini.c regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val); val 179 drivers/clk/clk-gemini.c return !!(val & PCI_CLKRUN_EN); val 250 drivers/clk/clk-gemini.c u32 val; val 253 drivers/clk/clk-gemini.c ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val); val 257 drivers/clk/clk-gemini.c return !!(val & BIT(id)); val 280 drivers/clk/clk-gemini.c u32 val; val 317 drivers/clk/clk-gemini.c regmap_read(map, GEMINI_GLOBAL_STATUS, &val); val 318 drivers/clk/clk-gemini.c val >>= CPU_AHB_RATIO_SHIFT; val 319 drivers/clk/clk-gemini.c val &= CPU_AHB_RATIO_MASK; val 321 drivers/clk/clk-gemini.c cpu_ahb_mult[val], val 322 drivers/clk/clk-gemini.c cpu_ahb_div[val]); val 326 drivers/clk/clk-gemini.c regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val); val 327 drivers/clk/clk-gemini.c if (val & SECURITY_CLK_SEL) { val 360 drivers/clk/clk-gemini.c div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK); val 398 drivers/clk/clk-gemini.c u32 val; val 426 drivers/clk/clk-gemini.c ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val); val 436 drivers/clk/clk-gemini.c if (val & PLL_OSC_SEL) val 444 drivers/clk/clk-gemini.c mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK); val 447 drivers/clk/clk-gemini.c if (val & PLL_OSC_SEL) val 58 drivers/clk/clk-hi655x.c uint32_t val; val 60 drivers/clk/clk-hi655x.c ret = regmap_read(hi655x->regmap, HI655X_CLK_BASE, &val); val 64 drivers/clk/clk-hi655x.c return val & HI655X_CLK_BASE; val 122 drivers/clk/clk-hsdk-pll.c static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val) val 124 drivers/clk/clk-hsdk-pll.c iowrite32(val, clk->regs + reg); val 135 drivers/clk/clk-hsdk-pll.c u32 val = 0; val 138 drivers/clk/clk-hsdk-pll.c val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT; val 139 drivers/clk/clk-hsdk-pll.c val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; val 140 drivers/clk/clk-hsdk-pll.c val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT; val 141 drivers/clk/clk-hsdk-pll.c val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT; val 143 drivers/clk/clk-hsdk-pll.c dev_dbg(clk->dev, "write configuration: %#x\n", val); val 145 drivers/clk/clk-hsdk-pll.c hsdk_pll_write(clk, CGU_PLL_CTRL, val); val 166 drivers/clk/clk-hsdk-pll.c u32 val; val 171 drivers/clk/clk-hsdk-pll.c val = hsdk_pll_read(clk, CGU_PLL_CTRL); val 173 drivers/clk/clk-hsdk-pll.c dev_dbg(clk->dev, "current configuration: %#x\n", val); val 176 drivers/clk/clk-hsdk-pll.c if (val & CGU_PLL_CTRL_PD) val 180 drivers/clk/clk-hsdk-pll.c if (val & CGU_PLL_CTRL_BYPASS) val 184 drivers/clk/clk-hsdk-pll.c idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT); val 186 drivers/clk/clk-hsdk-pll.c fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); val 188 drivers/clk/clk-hsdk-pll.c odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT); val 194 drivers/clk/clk-lochnagar.c unsigned int val; val 197 drivers/clk/clk-lochnagar.c ret = regmap_read(regmap, lclk->src_reg, &val); val 204 drivers/clk/clk-lochnagar.c val &= lclk->src_mask; val 206 drivers/clk/clk-lochnagar.c return val; val 124 drivers/clk/clk-max77686.c u32 val; val 126 drivers/clk/clk-max77686.c ret = regmap_read(max77686->regmap, max77686->clk_info->clk_reg, &val); val 131 drivers/clk/clk-max77686.c return val & max77686->clk_info->clk_enable_mask; val 152 drivers/clk/clk-max9485.c u8 val = drvdata->reg_value & MAX9485_FREQ_MASK; val 156 drivers/clk/clk-max9485.c if (val == entry->reg_value) val 101 drivers/clk/clk-milbeaut.c { .val = 0, .div = 8 }, val 102 drivers/clk/clk-milbeaut.c { .val = 1, .div = 9 }, val 103 drivers/clk/clk-milbeaut.c { .val = 2, .div = 10 }, val 104 drivers/clk/clk-milbeaut.c { .val = 3, .div = 15 }, val 109 drivers/clk/clk-milbeaut.c { .val = 1, .div = 2 }, val 110 drivers/clk/clk-milbeaut.c { .val = 3, .div = 4 }, val 115 drivers/clk/clk-milbeaut.c { .val = 3, .div = 4 }, val 116 drivers/clk/clk-milbeaut.c { .val = 7, .div = 8 }, val 121 drivers/clk/clk-milbeaut.c { .val = 1, .div = 2 }, val 122 drivers/clk/clk-milbeaut.c { .val = 3, .div = 4 }, val 127 drivers/clk/clk-milbeaut.c { .val = 0, .div = 2 }, val 128 drivers/clk/clk-milbeaut.c { .val = 1, .div = 3 }, val 133 drivers/clk/clk-milbeaut.c { .val = 3, .div = 4 }, val 134 drivers/clk/clk-milbeaut.c { .val = 7, .div = 8 }, val 139 drivers/clk/clk-milbeaut.c { .val = 3, .div = 4 }, val 140 drivers/clk/clk-milbeaut.c { .val = 4, .div = 5 }, val 141 drivers/clk/clk-milbeaut.c { .val = 5, .div = 6 }, val 142 drivers/clk/clk-milbeaut.c { .val = 7, .div = 8 }, val 147 drivers/clk/clk-milbeaut.c { .val = 7, .div = 8 }, val 148 drivers/clk/clk-milbeaut.c { .val = 15, .div = 16 }, val 153 drivers/clk/clk-milbeaut.c { .val = 3, .div = 4 }, val 154 drivers/clk/clk-milbeaut.c { .val = 7, .div = 8 }, val 159 drivers/clk/clk-milbeaut.c { .val = 15, .div = 16 }, val 160 drivers/clk/clk-milbeaut.c { .val = 31, .div = 32 }, val 165 drivers/clk/clk-milbeaut.c { .val = 0, .div = 8 }, val 166 drivers/clk/clk-milbeaut.c { .val = 1, .div = 16 }, val 167 drivers/clk/clk-milbeaut.c { .val = 2, .div = 24 }, val 168 drivers/clk/clk-milbeaut.c { .val = 3, .div = 32 }, val 173 drivers/clk/clk-milbeaut.c { .val = 0, .div = 2 }, val 174 drivers/clk/clk-milbeaut.c { .val = 1, .div = 3 }, val 175 drivers/clk/clk-milbeaut.c { .val = 2, .div = 4 }, val 176 drivers/clk/clk-milbeaut.c { .val = 3, .div = 8 }, val 177 drivers/clk/clk-milbeaut.c { .val = 4, .div = 16 }, val 182 drivers/clk/clk-milbeaut.c { .val = 0, .div = 9 }, val 183 drivers/clk/clk-milbeaut.c { .val = 1, .div = 10 }, val 184 drivers/clk/clk-milbeaut.c { .val = 2, .div = 11 }, val 185 drivers/clk/clk-milbeaut.c { .val = 3, .div = 12 }, val 186 drivers/clk/clk-milbeaut.c { .val = 4, .div = 13 }, val 187 drivers/clk/clk-milbeaut.c { .val = 5, .div = 14 }, val 188 drivers/clk/clk-milbeaut.c { .val = 6, .div = 16 }, val 189 drivers/clk/clk-milbeaut.c { .val = 7, .div = 18 }, val 283 drivers/clk/clk-milbeaut.c u32 val; val 285 drivers/clk/clk-milbeaut.c val = readl(mux->reg) >> mux->shift; val 286 drivers/clk/clk-milbeaut.c val &= mux->mask; val 288 drivers/clk/clk-milbeaut.c return clk_mux_val_to_index(hw, mux->table, mux->flags, val); val 294 drivers/clk/clk-milbeaut.c u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); val 307 drivers/clk/clk-milbeaut.c val = (val | write_en) << mux->shift; val 308 drivers/clk/clk-milbeaut.c reg |= val; val 380 drivers/clk/clk-milbeaut.c unsigned int val; val 382 drivers/clk/clk-milbeaut.c val = readl(divider->reg) >> divider->shift; val 383 drivers/clk/clk-milbeaut.c val &= clk_div_mask(divider->width); val 385 drivers/clk/clk-milbeaut.c return divider_recalc_rate(hw, parent_rate, val, divider->table, val 396 drivers/clk/clk-milbeaut.c u32 val; val 398 drivers/clk/clk-milbeaut.c val = readl(divider->reg) >> divider->shift; val 399 drivers/clk/clk-milbeaut.c val &= clk_div_mask(divider->width); val 403 drivers/clk/clk-milbeaut.c val); val 416 drivers/clk/clk-milbeaut.c u32 val; val 429 drivers/clk/clk-milbeaut.c val = readl(divider->reg); val 430 drivers/clk/clk-milbeaut.c val &= ~(clk_div_mask(divider->width) << divider->shift); val 432 drivers/clk/clk-milbeaut.c val |= ((u32)value | write_en) << divider->shift; val 433 drivers/clk/clk-milbeaut.c writel(val, divider->reg); val 437 drivers/clk/clk-milbeaut.c if (readl_poll_timeout(divider->write_valid_reg, val, val 438 drivers/clk/clk-milbeaut.c !val, M10V_UPOLL_RATE, M10V_UTIMEOUT)) val 63 drivers/clk/clk-moxart.c unsigned int div, val; val 77 drivers/clk/clk-moxart.c val = readl(base + 0xc) >> 4 & 0x7; val 80 drivers/clk/clk-moxart.c if (val > 4) val 81 drivers/clk/clk-moxart.c val = 0; val 82 drivers/clk/clk-moxart.c div = div_idx[val] * 2; val 23 drivers/clk/clk-multiplier.c static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) val 26 drivers/clk/clk-multiplier.c iowrite32be(val, mult->reg); val 28 drivers/clk/clk-multiplier.c writel(val, mult->reg); val 45 drivers/clk/clk-multiplier.c unsigned long val; val 47 drivers/clk/clk-multiplier.c val = clk_mult_readl(mult) >> mult->shift; val 48 drivers/clk/clk-multiplier.c val &= GENMASK(mult->width - 1, 0); val 50 drivers/clk/clk-multiplier.c if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS) val 51 drivers/clk/clk-multiplier.c val = 1; val 53 drivers/clk/clk-multiplier.c return parent_rate * val; val 131 drivers/clk/clk-multiplier.c unsigned long val; val 138 drivers/clk/clk-multiplier.c val = clk_mult_readl(mult); val 139 drivers/clk/clk-multiplier.c val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift); val 140 drivers/clk/clk-multiplier.c val |= factor << mult->shift; val 141 drivers/clk/clk-multiplier.c clk_mult_writel(mult, val); val 34 drivers/clk/clk-mux.c static inline void clk_mux_writel(struct clk_mux *mux, u32 val) val 37 drivers/clk/clk-mux.c iowrite32be(val, mux->reg); val 39 drivers/clk/clk-mux.c writel(val, mux->reg); val 43 drivers/clk/clk-mux.c unsigned int val) val 51 drivers/clk/clk-mux.c if (table[i] == val) val 56 drivers/clk/clk-mux.c if (val && (flags & CLK_MUX_INDEX_BIT)) val 57 drivers/clk/clk-mux.c val = ffs(val) - 1; val 59 drivers/clk/clk-mux.c if (val && (flags & CLK_MUX_INDEX_ONE)) val 60 drivers/clk/clk-mux.c val--; val 62 drivers/clk/clk-mux.c if (val >= num_parents) val 65 drivers/clk/clk-mux.c return val; val 71 drivers/clk/clk-mux.c unsigned int val = index; val 74 drivers/clk/clk-mux.c val = table[index]; val 77 drivers/clk/clk-mux.c val = 1 << index; val 80 drivers/clk/clk-mux.c val++; val 83 drivers/clk/clk-mux.c return val; val 90 drivers/clk/clk-mux.c u32 val; val 92 drivers/clk/clk-mux.c val = clk_mux_readl(mux) >> mux->shift; val 93 drivers/clk/clk-mux.c val &= mux->mask; val 95 drivers/clk/clk-mux.c return clk_mux_val_to_index(hw, mux->table, mux->flags, val); val 101 drivers/clk/clk-mux.c u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); val 116 drivers/clk/clk-mux.c val = val << mux->shift; val 117 drivers/clk/clk-mux.c reg |= val; val 68 drivers/clk/clk-nomadik.c u32 val; val 71 drivers/clk/clk-nomadik.c val = readl(src_base + SRC_XTALCR); val 72 drivers/clk/clk-nomadik.c val &= ~SRC_XTALCR_MXTALOVER; val 73 drivers/clk/clk-nomadik.c val |= SRC_XTALCR_MXTALEN; val 75 drivers/clk/clk-nomadik.c writel(val, src_base + SRC_XTALCR); val 91 drivers/clk/clk-nomadik.c u32 val; val 106 drivers/clk/clk-nomadik.c val = readl(src_base + SRC_CR); val 107 drivers/clk/clk-nomadik.c val |= SRC_CR_T0_ENSEL; val 108 drivers/clk/clk-nomadik.c val |= SRC_CR_T1_ENSEL; val 109 drivers/clk/clk-nomadik.c val |= SRC_CR_T2_ENSEL; val 110 drivers/clk/clk-nomadik.c val |= SRC_CR_T3_ENSEL; val 111 drivers/clk/clk-nomadik.c val |= SRC_CR_T4_ENSEL; val 112 drivers/clk/clk-nomadik.c val |= SRC_CR_T5_ENSEL; val 113 drivers/clk/clk-nomadik.c val |= SRC_CR_T6_ENSEL; val 114 drivers/clk/clk-nomadik.c val |= SRC_CR_T7_ENSEL; val 115 drivers/clk/clk-nomadik.c writel(val, src_base + SRC_CR); val 117 drivers/clk/clk-nomadik.c val = readl(src_base + SRC_XTALCR); val 119 drivers/clk/clk-nomadik.c (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled"); val 121 drivers/clk/clk-nomadik.c (val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled"); val 124 drivers/clk/clk-nomadik.c val |= SRC_XTALCR_SXTALDIS; val 129 drivers/clk/clk-nomadik.c val |= SRC_XTALCR_MXTALOVER; val 130 drivers/clk/clk-nomadik.c val &= ~SRC_XTALCR_MXTALEN; val 133 drivers/clk/clk-nomadik.c writel(val, src_base + SRC_XTALCR); val 167 drivers/clk/clk-nomadik.c u32 val; val 170 drivers/clk/clk-nomadik.c val = readl(src_base + SRC_PLLCR); val 172 drivers/clk/clk-nomadik.c if (val & SRC_PLLCR_PLL1OVER) { val 173 drivers/clk/clk-nomadik.c val |= SRC_PLLCR_PLL1EN; val 174 drivers/clk/clk-nomadik.c writel(val, src_base + SRC_PLLCR); val 177 drivers/clk/clk-nomadik.c val |= SRC_PLLCR_PLL2EN; val 178 drivers/clk/clk-nomadik.c writel(val, src_base + SRC_PLLCR); val 187 drivers/clk/clk-nomadik.c u32 val; val 190 drivers/clk/clk-nomadik.c val = readl(src_base + SRC_PLLCR); val 192 drivers/clk/clk-nomadik.c if (val & SRC_PLLCR_PLL1OVER) { val 193 drivers/clk/clk-nomadik.c val &= ~SRC_PLLCR_PLL1EN; val 194 drivers/clk/clk-nomadik.c writel(val, src_base + SRC_PLLCR); val 197 drivers/clk/clk-nomadik.c val &= ~SRC_PLLCR_PLL2EN; val 198 drivers/clk/clk-nomadik.c writel(val, src_base + SRC_PLLCR); val 206 drivers/clk/clk-nomadik.c u32 val; val 208 drivers/clk/clk-nomadik.c val = readl(src_base + SRC_PLLCR); val 210 drivers/clk/clk-nomadik.c if (val & SRC_PLLCR_PLL1OVER) val 211 drivers/clk/clk-nomadik.c return !!(val & SRC_PLLCR_PLL1EN); val 213 drivers/clk/clk-nomadik.c return !!(val & SRC_PLLCR_PLL2EN); val 222 drivers/clk/clk-nomadik.c u32 val; val 224 drivers/clk/clk-nomadik.c val = readl(src_base + SRC_PLLFR); val 230 drivers/clk/clk-nomadik.c mul = (val >> 8) & 0x3FU; val 232 drivers/clk/clk-nomadik.c div = val & 0x07U; val 239 drivers/clk/clk-nomadik.c mul = (val >> 24) & 0x3FU; val 329 drivers/clk/clk-nomadik.c u32 val = readl(src_base + sreg); val 331 drivers/clk/clk-nomadik.c return !!(val & sclk->clkbit); val 43 drivers/clk/clk-npcm7xx.c unsigned int val; val 51 drivers/clk/clk-npcm7xx.c val = readl_relaxed(pll->pllcon); val 53 drivers/clk/clk-npcm7xx.c indv = FIELD_GET(PLLCON_INDV, val); val 54 drivers/clk/clk-npcm7xx.c fbdv = FIELD_GET(PLLCON_FBDV, val); val 55 drivers/clk/clk-npcm7xx.c otdv1 = FIELD_GET(PLLCON_OTDV1, val); val 56 drivers/clk/clk-npcm7xx.c otdv2 = FIELD_GET(PLLCON_OTDV2, val); val 41 drivers/clk/clk-nspire.c static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk) val 43 drivers/clk/clk-nspire.c if (EXTRACT(val, FIXED_BASE)) val 46 drivers/clk/clk-nspire.c clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; val 48 drivers/clk/clk-nspire.c clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN); val 49 drivers/clk/clk-nspire.c clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); val 52 drivers/clk/clk-nspire.c static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk) val 54 drivers/clk/clk-nspire.c if (EXTRACT(val, FIXED_BASE)) val 57 drivers/clk/clk-nspire.c clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; val 59 drivers/clk/clk-nspire.c clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2; val 60 drivers/clk/clk-nspire.c clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); val 66 drivers/clk/clk-nspire.c u32 val; val 76 drivers/clk/clk-nspire.c val = readl(io); val 79 drivers/clk/clk-nspire.c get_clkinfo(val, &info); val 108 drivers/clk/clk-nspire.c u32 val; val 117 drivers/clk/clk-nspire.c val = readl(io); val 120 drivers/clk/clk-nspire.c get_clkinfo(val, &info); val 50 drivers/clk/clk-oxnas.c unsigned int val; val 52 drivers/clk/clk-oxnas.c ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val); val 56 drivers/clk/clk-oxnas.c return val & BIT(std->bit); val 103 drivers/clk/clk-palmas.c u32 val; val 109 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, &val); val 115 drivers/clk/clk-palmas.c return !!(val & cinfo->clk_desc->enable_mask); val 99 drivers/clk/clk-qoriq.c static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) val 102 drivers/clk/clk-qoriq.c iowrite32(val, reg); val 104 drivers/clk/clk-qoriq.c iowrite32be(val, reg); val 109 drivers/clk/clk-qoriq.c u32 val; val 112 drivers/clk/clk-qoriq.c val = ioread32(reg); val 114 drivers/clk/clk-qoriq.c val = ioread32be(reg); val 116 drivers/clk/clk-qoriq.c return val; val 56 drivers/clk/clk-rk808.c uint32_t val; val 58 drivers/clk/clk-rk808.c int ret = regmap_read(rk808->regmap, RK808_CLK32OUT_REG, &val); val 63 drivers/clk/clk-rk808.c return (val & CLK32KOUT2_EN) ? 1 : 0; val 119 drivers/clk/clk-rk808.c unsigned int val; val 121 drivers/clk/clk-rk808.c int ret = regmap_read(rk808->regmap, RK817_SYS_CFG(1), &val); val 126 drivers/clk/clk-rk808.c return (val & RK817_CLK32KOUT2_EN) ? 1 : 0; val 57 drivers/clk/clk-s2mps11.c u32 val; val 61 drivers/clk/clk-s2mps11.c s2mps11->reg, &val); val 65 drivers/clk/clk-s2mps11.c return val & s2mps11->mask; val 216 drivers/clk/clk-scpi.c u32 val; val 229 drivers/clk/clk-scpi.c idx, &val)) { val 234 drivers/clk/clk-scpi.c sclk->id = val; val 85 drivers/clk/clk-si514.c unsigned int val; val 88 drivers/clk/clk-si514.c err = regmap_read(data->regmap, SI514_REG_CONTROL, &val); val 92 drivers/clk/clk-si514.c return !!(val & SI514_CONTROL_OE); val 404 drivers/clk/clk-si5341.c u32 val; val 408 drivers/clk/clk-si5341.c SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val); val 412 drivers/clk/clk-si5341.c if (!(val & BIT(index))) val 415 drivers/clk/clk-si5341.c err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val); val 419 drivers/clk/clk-si5341.c if (!(val & BIT(index))) val 423 drivers/clk/clk-si5341.c err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val); val 427 drivers/clk/clk-si5341.c return !(val & BIT(index)); val 586 drivers/clk/clk-si5341.c u32 val; val 589 drivers/clk/clk-si5341.c SI5341_OUT_CONFIG(output), &val); val 594 drivers/clk/clk-si5341.c return (val & 0x03) == SI5341_OUT_CFG_OE; val 632 drivers/clk/clk-si5341.c u32 val; val 653 drivers/clk/clk-si5341.c SI5341_OUT_CONFIG(output), &val); val 657 drivers/clk/clk-si5341.c if (val & SI5341_OUT_CFG_RDIV_FORCE2) val 746 drivers/clk/clk-si5341.c u32 val; val 749 drivers/clk/clk-si5341.c SI5341_OUT_MUX_SEL(output), &val); val 751 drivers/clk/clk-si5341.c return val & 0x7; val 1030 drivers/clk/clk-si5341.c u32 val; val 1047 drivers/clk/clk-si5341.c if (!of_property_read_u32(child, "silabs,format", &val)) { val 1049 drivers/clk/clk-si5341.c switch (val) { val 1064 drivers/clk/clk-si5341.c val, num); val 1068 drivers/clk/clk-si5341.c config[num].out_format_drv_bits |= val & 0x07; val 1073 drivers/clk/clk-si5341.c if (!of_property_read_u32(child, "silabs,common-mode", &val)) { val 1074 drivers/clk/clk-si5341.c if (val > 0xf) { val 1077 drivers/clk/clk-si5341.c val); val 1081 drivers/clk/clk-si5341.c config[num].out_cm_ampl_bits |= val & 0x0f; val 1084 drivers/clk/clk-si5341.c if (!of_property_read_u32(child, "silabs,amplitude", &val)) { val 1085 drivers/clk/clk-si5341.c if (val > 0xf) { val 1088 drivers/clk/clk-si5341.c val); val 1092 drivers/clk/clk-si5341.c config[num].out_cm_ampl_bits |= (val << 4) & 0xf0; val 85 drivers/clk/clk-si5351.c u32 val; val 88 drivers/clk/clk-si5351.c ret = regmap_read(drvdata->regmap, reg, &val); val 95 drivers/clk/clk-si5351.c return (u8)val; val 105 drivers/clk/clk-si5351.c u8 reg, u8 val) val 107 drivers/clk/clk-si5351.c return regmap_write(drvdata->regmap, reg, val); val 117 drivers/clk/clk-si5351.c u8 reg, u8 mask, u8 val) val 119 drivers/clk/clk-si5351.c return regmap_update_bits(drvdata->regmap, reg, mask, val); val 390 drivers/clk/clk-si5351.c u8 val; val 392 drivers/clk/clk-si5351.c val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE); val 394 drivers/clk/clk-si5351.c return (val & mask) ? 1 : 0; val 582 drivers/clk/clk-si5351.c u8 val; val 584 drivers/clk/clk-si5351.c val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); val 586 drivers/clk/clk-si5351.c return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0; val 802 drivers/clk/clk-si5351.c u8 val; val 809 drivers/clk/clk-si5351.c val = SI5351_CLK_INPUT_MULTISYNTH_N; val 814 drivers/clk/clk-si5351.c val = SI5351_CLK_INPUT_MULTISYNTH_N; val 816 drivers/clk/clk-si5351.c val = SI5351_CLK_INPUT_MULTISYNTH_0_4; val 819 drivers/clk/clk-si5351.c val = SI5351_CLK_INPUT_XTAL; val 825 drivers/clk/clk-si5351.c val = SI5351_CLK_INPUT_CLKIN; val 832 drivers/clk/clk-si5351.c SI5351_CLK_INPUT_MASK, val); val 875 drivers/clk/clk-si5351.c u8 val; val 882 drivers/clk/clk-si5351.c val = SI5351_CLK_DISABLE_STATE_LOW; val 885 drivers/clk/clk-si5351.c val = SI5351_CLK_DISABLE_STATE_HIGH; val 888 drivers/clk/clk-si5351.c val = SI5351_CLK_DISABLE_STATE_FLOAT; val 891 drivers/clk/clk-si5351.c val = SI5351_CLK_DISABLE_STATE_NEVER; val 897 drivers/clk/clk-si5351.c si5351_set_bits(drvdata, reg, mask, val << shift); val 904 drivers/clk/clk-si5351.c u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num); val 906 drivers/clk/clk-si5351.c switch (val & SI5351_CLK_INPUT_MASK) { val 913 drivers/clk/clk-si5351.c val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B : val 918 drivers/clk/clk-si5351.c (val & SI5351_CLK_PLL_SELECT) ? 1 : 0); val 959 drivers/clk/clk-si5351.c unsigned char val; val 961 drivers/clk/clk-si5351.c val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); val 962 drivers/clk/clk-si5351.c switch (val & SI5351_CLK_INPUT_MASK) { val 1164 drivers/clk/clk-si5351.c u32 val; val 1184 drivers/clk/clk-si5351.c p = of_prop_next_u32(prop, p, &val); val 1191 drivers/clk/clk-si5351.c switch (val) { val 1199 drivers/clk/clk-si5351.c val, num); val 1206 drivers/clk/clk-si5351.c "invalid parent %d for pll %d\n", val, num); val 1226 drivers/clk/clk-si5351.c &val)) { val 1227 drivers/clk/clk-si5351.c switch (val) { val 1239 drivers/clk/clk-si5351.c val, num); val 1244 drivers/clk/clk-si5351.c if (!of_property_read_u32(child, "silabs,clock-source", &val)) { val 1245 drivers/clk/clk-si5351.c switch (val) { val 1262 drivers/clk/clk-si5351.c val, num); val 1271 drivers/clk/clk-si5351.c val, num); val 1277 drivers/clk/clk-si5351.c &val)) { val 1278 drivers/clk/clk-si5351.c switch (val) { val 1283 drivers/clk/clk-si5351.c pdata->clkout[num].drive = val; val 1288 drivers/clk/clk-si5351.c val, num); val 1294 drivers/clk/clk-si5351.c &val)) { val 1295 drivers/clk/clk-si5351.c switch (val) { val 1315 drivers/clk/clk-si5351.c val, num); val 1320 drivers/clk/clk-si5351.c if (!of_property_read_u32(child, "clock-frequency", &val)) val 1321 drivers/clk/clk-si5351.c pdata->clkout[num].rate = val; val 114 drivers/clk/clk-si544.c unsigned int val; val 117 drivers/clk/clk-si544.c err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); val 121 drivers/clk/clk-si544.c return !!(val & SI544_OE_STATE_ODC_OE); val 670 drivers/clk/clk-stm32f4.c unsigned long val; val 680 drivers/clk/clk-stm32f4.c val = readl(base + pll->offset) & ~(0x1ff << 6); val 682 drivers/clk/clk-stm32f4.c writel(val | ((n & 0x1ff) << 6), base + pll->offset); val 905 drivers/clk/clk-stm32f4.c unsigned long val; val 907 drivers/clk/clk-stm32f4.c val = readl(base + STM32F4_RCC_BDCR); val 908 drivers/clk/clk-stm32f4.c writel(val | BIT(16), base + STM32F4_RCC_BDCR); val 909 drivers/clk/clk-stm32f4.c writel(val & ~BIT(16), base + STM32F4_RCC_BDCR); val 749 drivers/clk/clk-stm32h7.c u32 val, mask; val 752 drivers/clk/clk-stm32h7.c val = readl(fd->mreg); val 754 drivers/clk/clk-stm32h7.c m = (val & mask) >> fd->mshift; val 756 drivers/clk/clk-stm32h7.c val = readl(fd->nreg); val 758 drivers/clk/clk-stm32h7.c n = ((val & mask) >> fd->nshift) + 1; val 767 drivers/clk/clk-stm32h7.c val = pll_read_frac(hw); val 768 drivers/clk/clk-stm32h7.c rate1 = (u64)parent_rate * (u64)val; val 17 drivers/clk/clk-tango4.c #define extract_pll_n(val) ((val >> 0) & ((1u << 7) - 1)) val 18 drivers/clk/clk-tango4.c #define extract_pll_k(val) ((val >> 13) & ((1u << 3) - 1)) val 19 drivers/clk/clk-tango4.c #define extract_pll_m(val) ((val >> 16) & ((1u << 3) - 1)) val 20 drivers/clk/clk-tango4.c #define extract_pll_isel(val) ((val >> 24) & ((1u << 3) - 1)) val 25 drivers/clk/clk-tango4.c u32 val, mul, div; val 28 drivers/clk/clk-tango4.c val = readl(base + idx * 8); val 29 drivers/clk/clk-tango4.c mul = extract_pll_n(val) + 1; val 30 drivers/clk/clk-tango4.c div = (extract_pll_m(val) + 1) << extract_pll_k(val); val 32 drivers/clk/clk-tango4.c if (extract_pll_isel(val) != 1) val 39 drivers/clk/clk-tango4.c u32 val, mul, div; val 42 drivers/clk/clk-tango4.c val = readl(base + idx * 8); val 44 drivers/clk/clk-tango4.c div = (2 << 27) + val; val 46 drivers/clk/clk-tango4.c if (val > 0xf0000000) val 47 drivers/clk/clk-tango4.c panic("%s: unsupported divider %x\n", name, val); val 458 drivers/clk/clk-u300.c u16 val; val 464 drivers/clk/clk-u300.c val = readw(sclk->res_reg); val 465 drivers/clk/clk-u300.c val |= BIT(sclk->res_bit); val 466 drivers/clk/clk-u300.c writew(val, sclk->res_reg); val 474 drivers/clk/clk-u300.c u16 val; val 480 drivers/clk/clk-u300.c val = readw(sclk->res_reg); val 481 drivers/clk/clk-u300.c val &= ~BIT(sclk->res_bit); val 482 drivers/clk/clk-u300.c writew(val, sclk->res_reg); val 543 drivers/clk/clk-u300.c u16 val; val 549 drivers/clk/clk-u300.c val = readw(sclk->en_reg); val 550 drivers/clk/clk-u300.c val &= BIT(sclk->en_bit); val 552 drivers/clk/clk-u300.c return val ? 1 : 0; val 557 drivers/clk/clk-u300.c u16 val; val 559 drivers/clk/clk-u300.c val = readw(syscon_vbase + U300_SYSCON_CCR); val 560 drivers/clk/clk-u300.c val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; val 561 drivers/clk/clk-u300.c return val; val 654 drivers/clk/clk-u300.c u16 val; val 661 drivers/clk/clk-u300.c val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER; val 664 drivers/clk/clk-u300.c val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE; val 667 drivers/clk/clk-u300.c val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH; val 670 drivers/clk/clk-u300.c val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST; val 675 drivers/clk/clk-u300.c val |= readw(syscon_vbase + U300_SYSCON_CCR) & val 677 drivers/clk/clk-u300.c writew(val, syscon_vbase + U300_SYSCON_CCR); val 955 drivers/clk/clk-u300.c u16 val; val 961 drivers/clk/clk-u300.c val = readw(syscon_vbase + U300_SYSCON_MMCR); val 963 drivers/clk/clk-u300.c val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE; val 965 drivers/clk/clk-u300.c val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE; val 966 drivers/clk/clk-u300.c writew(val, syscon_vbase + U300_SYSCON_MMCR); val 968 drivers/clk/clk-u300.c val = readw(syscon_vbase + U300_SYSCON_MMCR); val 970 drivers/clk/clk-u300.c val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE; val 972 drivers/clk/clk-u300.c val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE; val 973 drivers/clk/clk-u300.c writew(val, syscon_vbase + U300_SYSCON_MMCR); val 1011 drivers/clk/clk-u300.c u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) & val 1013 drivers/clk/clk-u300.c switch (val) { val 1067 drivers/clk/clk-u300.c u16 val; val 1072 drivers/clk/clk-u300.c val = 0x0054; val 1075 drivers/clk/clk-u300.c val = 0x0044; val 1078 drivers/clk/clk-u300.c val = 0x0043; val 1081 drivers/clk/clk-u300.c val = 0x0033; val 1084 drivers/clk/clk-u300.c val = 0x0032; val 1087 drivers/clk/clk-u300.c val = 0x0022; val 1090 drivers/clk/clk-u300.c val = 0x0021; val 1093 drivers/clk/clk-u300.c val = 0x0011; val 1096 drivers/clk/clk-u300.c val = 0x0000; val 1104 drivers/clk/clk-u300.c writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R); val 1181 drivers/clk/clk-u300.c u16 val; val 1186 drivers/clk/clk-u300.c val = readw(syscon_vbase + U300_SYSCON_CCR); val 1187 drivers/clk/clk-u300.c val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; val 1188 drivers/clk/clk-u300.c writew(val, syscon_vbase + U300_SYSCON_CCR); val 1194 drivers/clk/clk-u300.c val = readw(syscon_vbase + U300_SYSCON_PMCR); val 1195 drivers/clk/clk-u300.c val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE; val 1196 drivers/clk/clk-u300.c writew(val, syscon_vbase + U300_SYSCON_PMCR); val 243 drivers/clk/clk-xgene.c u32 val; val 250 drivers/clk/clk-xgene.c val = readl(fd->reg); val 259 drivers/clk/clk-xgene.c scale = (val & fd->mask) >> fd->shift; val 299 drivers/clk/clk-xgene.c u32 val; val 321 drivers/clk/clk-xgene.c val = readl(fd->reg); val 322 drivers/clk/clk-xgene.c val &= ~fd->mask; val 323 drivers/clk/clk-xgene.c val |= (scale << fd->shift); val 324 drivers/clk/clk-xgene.c writel(val, fd->reg); val 59 drivers/clk/davinci/da8xx-cfgchip.c unsigned int val; val 61 drivers/clk/davinci/da8xx-cfgchip.c regmap_read(clk->regmap, clk->reg, &val); val 63 drivers/clk/davinci/da8xx-cfgchip.c return !!(val & clk->mask); val 216 drivers/clk/davinci/da8xx-cfgchip.c unsigned int val = index ? clk->mask : 0; val 218 drivers/clk/davinci/da8xx-cfgchip.c return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val); val 224 drivers/clk/davinci/da8xx-cfgchip.c unsigned int val; val 226 drivers/clk/davinci/da8xx-cfgchip.c regmap_read(clk->regmap, clk->reg, &val); val 228 drivers/clk/davinci/da8xx-cfgchip.c return (val & clk->mask) ? 1 : 0; val 376 drivers/clk/davinci/da8xx-cfgchip.c unsigned int mask, val; val 388 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_PHY_PLLON; val 390 drivers/clk/davinci/da8xx-cfgchip.c regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); val 391 drivers/clk/davinci/da8xx-cfgchip.c ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val, val 392 drivers/clk/davinci/da8xx-cfgchip.c val & CFGCHIP2_PHYCLKGD, 0, 500000); val 402 drivers/clk/davinci/da8xx-cfgchip.c unsigned int val; val 404 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_PHYPWRDN; val 405 drivers/clk/davinci/da8xx-cfgchip.c regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val); val 411 drivers/clk/davinci/da8xx-cfgchip.c unsigned int val; val 413 drivers/clk/davinci/da8xx-cfgchip.c regmap_read(usb0->regmap, CFGCHIP(2), &val); val 415 drivers/clk/davinci/da8xx-cfgchip.c return !!(val & CFGCHIP2_PHYCLKGD); val 422 drivers/clk/davinci/da8xx-cfgchip.c unsigned int mask, val; val 428 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_12MHZ; val 431 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_13MHZ; val 434 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_19_2MHZ; val 437 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_20MHZ; val 440 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_24MHZ; val 443 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_26MHZ; val 446 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_38_4MHZ; val 449 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_40MHZ; val 452 drivers/clk/davinci/da8xx-cfgchip.c val = CFGCHIP2_REFFREQ_48MHZ; val 458 drivers/clk/davinci/da8xx-cfgchip.c regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); val 482 drivers/clk/davinci/da8xx-cfgchip.c unsigned int val; val 484 drivers/clk/davinci/da8xx-cfgchip.c regmap_read(usb0->regmap, CFGCHIP(2), &val); val 486 drivers/clk/davinci/da8xx-cfgchip.c return (val & CFGCHIP2_USB2PHYCLKMUX) ? 1 : 0; val 560 drivers/clk/davinci/da8xx-cfgchip.c unsigned int val; val 562 drivers/clk/davinci/da8xx-cfgchip.c regmap_read(usb1->regmap, CFGCHIP(2), &val); val 564 drivers/clk/davinci/da8xx-cfgchip.c return (val & CFGCHIP2_USB1PHYCLKMUX) ? 1 : 0; val 63 drivers/clk/h8300/clk-h8s2678.c unsigned char val; val 69 drivers/clk/h8300/clk-h8s2678.c val = readb(pll_clock->sckcr); val 70 drivers/clk/h8300/clk-h8s2678.c val |= 0x08; val 71 drivers/clk/h8300/clk-h8s2678.c writeb(val, pll_clock->sckcr); val 72 drivers/clk/h8300/clk-h8s2678.c val = readb(pll_clock->pllcr); val 73 drivers/clk/h8300/clk-h8s2678.c val &= ~0x03; val 74 drivers/clk/h8300/clk-h8s2678.c val |= pll; val 75 drivers/clk/h8300/clk-h8s2678.c writeb(val, pll_clock->pllcr); val 306 drivers/clk/hisilicon/clk-hi3620.c static u32 mmc_clk_delay(u32 val, u32 para, u32 off, u32 len) val 312 drivers/clk/hisilicon/clk-hi3620.c val |= 1 << (off + i); val 314 drivers/clk/hisilicon/clk-hi3620.c val &= ~(1 << (off + i)); val 318 drivers/clk/hisilicon/clk-hi3620.c return val; val 325 drivers/clk/hisilicon/clk-hi3620.c u32 sam, drv, div, val; val 360 drivers/clk/hisilicon/clk-hi3620.c val = readl_relaxed(mclk->clken_reg); val 361 drivers/clk/hisilicon/clk-hi3620.c val &= ~(1 << mclk->clken_bit); val 362 drivers/clk/hisilicon/clk-hi3620.c writel_relaxed(val, mclk->clken_reg); val 364 drivers/clk/hisilicon/clk-hi3620.c val = readl_relaxed(mclk->sam_reg); val 365 drivers/clk/hisilicon/clk-hi3620.c val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits); val 366 drivers/clk/hisilicon/clk-hi3620.c writel_relaxed(val, mclk->sam_reg); val 368 drivers/clk/hisilicon/clk-hi3620.c val = readl_relaxed(mclk->drv_reg); val 369 drivers/clk/hisilicon/clk-hi3620.c val = mmc_clk_delay(val, drv, mclk->drv_off, mclk->drv_bits); val 370 drivers/clk/hisilicon/clk-hi3620.c writel_relaxed(val, mclk->drv_reg); val 372 drivers/clk/hisilicon/clk-hi3620.c val = readl_relaxed(mclk->div_reg); val 373 drivers/clk/hisilicon/clk-hi3620.c val = mmc_clk_delay(val, div, mclk->div_off, mclk->div_bits); val 374 drivers/clk/hisilicon/clk-hi3620.c writel_relaxed(val, mclk->div_reg); val 376 drivers/clk/hisilicon/clk-hi3620.c val = readl_relaxed(mclk->clken_reg); val 377 drivers/clk/hisilicon/clk-hi3620.c val |= 1 << mclk->clken_bit; val 378 drivers/clk/hisilicon/clk-hi3620.c writel_relaxed(val, mclk->clken_reg); val 70 drivers/clk/hisilicon/clk-hisi-phase.c u32 val; val 78 drivers/clk/hisilicon/clk-hisi-phase.c val = readl(phase->reg); val 79 drivers/clk/hisilicon/clk-hisi-phase.c val &= ~phase->mask; val 80 drivers/clk/hisilicon/clk-hisi-phase.c val |= regval << phase->shift; val 81 drivers/clk/hisilicon/clk-hisi-phase.c writel(val, phase->reg); val 172 drivers/clk/hisilicon/clk-hix5hd2.c u32 val; val 174 drivers/clk/hisilicon/clk-hix5hd2.c val = readl_relaxed(clk->ctrl_reg); val 175 drivers/clk/hisilicon/clk-hix5hd2.c val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; val 176 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->ctrl_reg); val 177 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->ctrl_rst_mask); val 178 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->ctrl_reg); val 180 drivers/clk/hisilicon/clk-hix5hd2.c val = readl_relaxed(clk->phy_reg); val 181 drivers/clk/hisilicon/clk-hix5hd2.c val |= clk->phy_clk_mask; val 182 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->phy_rst_mask); val 183 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->phy_reg); val 186 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->phy_clk_mask); val 187 drivers/clk/hisilicon/clk-hix5hd2.c val |= clk->phy_rst_mask; val 188 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->phy_reg); val 191 drivers/clk/hisilicon/clk-hix5hd2.c val |= clk->phy_clk_mask; val 192 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->phy_rst_mask); val 193 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->phy_reg); val 201 drivers/clk/hisilicon/clk-hix5hd2.c u32 val; val 203 drivers/clk/hisilicon/clk-hix5hd2.c val = readl_relaxed(clk->ctrl_reg); val 204 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->ctrl_clk_mask); val 205 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->ctrl_reg); val 216 drivers/clk/hisilicon/clk-hix5hd2.c u32 val; val 218 drivers/clk/hisilicon/clk-hix5hd2.c val = readl_relaxed(clk->ctrl_reg); val 219 drivers/clk/hisilicon/clk-hix5hd2.c val |= clk->ctrl_clk_mask; val 220 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->ctrl_rst_mask); val 221 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->ctrl_reg); val 223 drivers/clk/hisilicon/clk-hix5hd2.c val = readl_relaxed(clk->phy_reg); val 224 drivers/clk/hisilicon/clk-hix5hd2.c val |= clk->phy_clk_mask; val 225 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->phy_rst_mask); val 226 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->phy_reg); val 234 drivers/clk/hisilicon/clk-hix5hd2.c u32 val; val 236 drivers/clk/hisilicon/clk-hix5hd2.c val = readl_relaxed(clk->ctrl_reg); val 237 drivers/clk/hisilicon/clk-hix5hd2.c val |= clk->ctrl_rst_mask; val 238 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->ctrl_clk_mask); val 239 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->ctrl_reg); val 241 drivers/clk/hisilicon/clk-hix5hd2.c val = readl_relaxed(clk->phy_reg); val 242 drivers/clk/hisilicon/clk-hix5hd2.c val |= clk->phy_rst_mask; val 243 drivers/clk/hisilicon/clk-hix5hd2.c val &= ~(clk->phy_clk_mask); val 244 drivers/clk/hisilicon/clk-hix5hd2.c writel_relaxed(val, clk->phy_reg); val 48 drivers/clk/hisilicon/clkdivider-hi6220.c unsigned int val; val 51 drivers/clk/hisilicon/clkdivider-hi6220.c val = readl_relaxed(dclk->reg) >> dclk->shift; val 52 drivers/clk/hisilicon/clkdivider-hi6220.c val &= div_mask(dclk->width); val 54 drivers/clk/hisilicon/clkdivider-hi6220.c return divider_recalc_rate(hw, parent_rate, val, dclk->table, val 128 drivers/clk/hisilicon/clkdivider-hi6220.c table[i].val = table[i].div - 1; val 26 drivers/clk/imgtec/clk-boston.c static u32 ext_field(u32 val, u32 mask) val 28 drivers/clk/imgtec/clk-boston.c return (val & mask) >> (ffs(mask) - 1); val 98 drivers/clk/imx/clk-composite-8m.c u32 val; val 107 drivers/clk/imx/clk-composite-8m.c val = readl(divider->reg); val 108 drivers/clk/imx/clk-composite-8m.c val &= ~((clk_div_mask(divider->width) << divider->shift) | val 111 drivers/clk/imx/clk-composite-8m.c val |= (u32)(prediv_value - 1) << divider->shift; val 112 drivers/clk/imx/clk-composite-8m.c val |= (u32)(div_value - 1) << PCG_DIV_SHIFT; val 113 drivers/clk/imx/clk-composite-8m.c writel(val, divider->reg); val 30 drivers/clk/imx/clk-divider-gate.c unsigned int val; val 32 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg) >> div->shift; val 33 drivers/clk/imx/clk-divider-gate.c val &= clk_div_mask(div->width); val 34 drivers/clk/imx/clk-divider-gate.c if (!val) val 37 drivers/clk/imx/clk-divider-gate.c return divider_recalc_rate(hw, parent_rate, val, div->table, val 47 drivers/clk/imx/clk-divider-gate.c unsigned int val; val 52 drivers/clk/imx/clk-divider-gate.c val = div_gate->cached_val; val 54 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg) >> div->shift; val 55 drivers/clk/imx/clk-divider-gate.c val &= clk_div_mask(div->width); val 60 drivers/clk/imx/clk-divider-gate.c if (!val) val 63 drivers/clk/imx/clk-divider-gate.c return divider_recalc_rate(hw, parent_rate, val, div->table, val 80 drivers/clk/imx/clk-divider-gate.c u32 val; val 90 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg); val 91 drivers/clk/imx/clk-divider-gate.c val &= ~(clk_div_mask(div->width) << div->shift); val 92 drivers/clk/imx/clk-divider-gate.c val |= (u32)value << div->shift; val 93 drivers/clk/imx/clk-divider-gate.c writel(val, div->reg); val 108 drivers/clk/imx/clk-divider-gate.c u32 val; val 117 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg); val 118 drivers/clk/imx/clk-divider-gate.c val |= div_gate->cached_val << div->shift; val 119 drivers/clk/imx/clk-divider-gate.c writel(val, div->reg); val 131 drivers/clk/imx/clk-divider-gate.c u32 val; val 136 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg) >> div->shift; val 137 drivers/clk/imx/clk-divider-gate.c val &= clk_div_mask(div->width); val 138 drivers/clk/imx/clk-divider-gate.c div_gate->cached_val = val; val 147 drivers/clk/imx/clk-divider-gate.c u32 val; val 149 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg) >> div->shift; val 150 drivers/clk/imx/clk-divider-gate.c val &= clk_div_mask(div->width); val 152 drivers/clk/imx/clk-divider-gate.c return val ? 1 : 0; val 185 drivers/clk/imx/clk-divider-gate.c u32 val; val 209 drivers/clk/imx/clk-divider-gate.c val = readl(reg) >> shift; val 210 drivers/clk/imx/clk-divider-gate.c val &= clk_div_mask(width); val 211 drivers/clk/imx/clk-divider-gate.c div_gate->cached_val = val; val 26 drivers/clk/imx/clk-fixup-div.c void (*fixup)(u32 *val); val 59 drivers/clk/imx/clk-fixup-div.c u32 val; val 71 drivers/clk/imx/clk-fixup-div.c val = readl(div->reg); val 72 drivers/clk/imx/clk-fixup-div.c val &= ~(div_mask(div) << div->shift); val 73 drivers/clk/imx/clk-fixup-div.c val |= value << div->shift; val 74 drivers/clk/imx/clk-fixup-div.c fixup_div->fixup(&val); val 75 drivers/clk/imx/clk-fixup-div.c writel(val, div->reg); val 90 drivers/clk/imx/clk-fixup-div.c void (*fixup)(u32 *val)) val 24 drivers/clk/imx/clk-fixup-mux.c void (*fixup)(u32 *val); val 46 drivers/clk/imx/clk-fixup-mux.c u32 val; val 50 drivers/clk/imx/clk-fixup-mux.c val = readl(mux->reg); val 51 drivers/clk/imx/clk-fixup-mux.c val &= ~(mux->mask << mux->shift); val 52 drivers/clk/imx/clk-fixup-mux.c val |= index << mux->shift; val 53 drivers/clk/imx/clk-fixup-mux.c fixup_mux->fixup(&val); val 54 drivers/clk/imx/clk-fixup-mux.c writel(val, mux->reg); val 68 drivers/clk/imx/clk-fixup-mux.c int num_parents, void (*fixup)(u32 *val)) val 45 drivers/clk/imx/clk-frac-pll.c u32 val; val 47 drivers/clk/imx/clk-frac-pll.c return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0, val 53 drivers/clk/imx/clk-frac-pll.c u32 val; val 60 drivers/clk/imx/clk-frac-pll.c return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0, val 67 drivers/clk/imx/clk-frac-pll.c u32 val; val 69 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 70 drivers/clk/imx/clk-frac-pll.c val &= ~PLL_PD_MASK; val 71 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); val 79 drivers/clk/imx/clk-frac-pll.c u32 val; val 81 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 82 drivers/clk/imx/clk-frac-pll.c val |= PLL_PD_MASK; val 83 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); val 89 drivers/clk/imx/clk-frac-pll.c u32 val; val 91 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 92 drivers/clk/imx/clk-frac-pll.c return (val & PLL_PD_MASK) ? 0 : 1; val 99 drivers/clk/imx/clk-frac-pll.c u32 val, divff, divfi, divq; val 103 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 104 drivers/clk/imx/clk-frac-pll.c divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2; val 105 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG1); val 106 drivers/clk/imx/clk-frac-pll.c divff = FIELD_GET(PLL_FRAC_DIV_MASK, val); val 107 drivers/clk/imx/clk-frac-pll.c divfi = FIELD_GET(PLL_INT_DIV_MASK, val); val 158 drivers/clk/imx/clk-frac-pll.c u32 val, divfi, divff; val 171 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG1); val 172 drivers/clk/imx/clk-frac-pll.c val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK); val 173 drivers/clk/imx/clk-frac-pll.c val |= (divff << 7) | (divfi - 1); val 174 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG1); val 176 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 177 drivers/clk/imx/clk-frac-pll.c val &= ~0x1f; val 178 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); val 181 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 182 drivers/clk/imx/clk-frac-pll.c val |= PLL_NEWDIV_VAL; val 183 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); val 188 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 189 drivers/clk/imx/clk-frac-pll.c val &= ~PLL_NEWDIV_VAL; val 190 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); val 34 drivers/clk/imx/clk-gate-exclusive.c u32 val = readl(gate->reg); val 36 drivers/clk/imx/clk-gate-exclusive.c if (val & exgate->exclusive_mask) val 86 drivers/clk/imx/clk-gate2.c u32 val = readl(reg); val 88 drivers/clk/imx/clk-gate2.c if (((val >> bit_idx) & 1) == 1) val 393 drivers/clk/imx/clk-imx5.c u32 val; val 483 drivers/clk/imx/clk-imx5.c val = readl(MXC_CCM_CCDR); val 484 drivers/clk/imx/clk-imx5.c val |= 1 << 18; val 485 drivers/clk/imx/clk-imx5.c writel(val, MXC_CCM_CCDR); val 487 drivers/clk/imx/clk-imx5.c val = readl(MXC_CCM_CLPCR); val 488 drivers/clk/imx/clk-imx5.c val |= 1 << 23; val 489 drivers/clk/imx/clk-imx5.c writel(val, MXC_CCM_CLPCR); val 95 drivers/clk/imx/clk-imx6q.c { .val = 0, .div = 20, }, val 96 drivers/clk/imx/clk-imx6q.c { .val = 1, .div = 10, }, val 97 drivers/clk/imx/clk-imx6q.c { .val = 2, .div = 5, }, val 98 drivers/clk/imx/clk-imx6q.c { .val = 3, .div = 4, }, val 103 drivers/clk/imx/clk-imx6q.c { .val = 2, .div = 1, }, val 104 drivers/clk/imx/clk-imx6q.c { .val = 1, .div = 2, }, val 105 drivers/clk/imx/clk-imx6q.c { .val = 0, .div = 4, }, val 110 drivers/clk/imx/clk-imx6q.c { .val = 0, .div = 1, }, val 111 drivers/clk/imx/clk-imx6q.c { .val = 1, .div = 2, }, val 112 drivers/clk/imx/clk-imx6q.c { .val = 2, .div = 1, }, val 113 drivers/clk/imx/clk-imx6q.c { .val = 3, .div = 4, }, val 71 drivers/clk/imx/clk-imx6sl.c { .val = 0, .div = 20, }, val 72 drivers/clk/imx/clk-imx6sl.c { .val = 1, .div = 10, }, val 73 drivers/clk/imx/clk-imx6sl.c { .val = 2, .div = 5, }, val 74 drivers/clk/imx/clk-imx6sl.c { .val = 3, .div = 4, }, val 79 drivers/clk/imx/clk-imx6sl.c { .val = 2, .div = 1, }, val 80 drivers/clk/imx/clk-imx6sl.c { .val = 1, .div = 2, }, val 81 drivers/clk/imx/clk-imx6sl.c { .val = 0, .div = 4, }, val 86 drivers/clk/imx/clk-imx6sl.c { .val = 0, .div = 1, }, val 87 drivers/clk/imx/clk-imx6sl.c { .val = 1, .div = 2, }, val 88 drivers/clk/imx/clk-imx6sl.c { .val = 2, .div = 1, }, val 89 drivers/clk/imx/clk-imx6sl.c { .val = 3, .div = 4, }, val 141 drivers/clk/imx/clk-imx6sl.c u32 val; val 144 drivers/clk/imx/clk-imx6sl.c saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); val 145 drivers/clk/imx/clk-imx6sl.c val |= BM_PLL_ARM_ENABLE; val 146 drivers/clk/imx/clk-imx6sl.c val &= ~BM_PLL_ARM_POWERDOWN; val 147 drivers/clk/imx/clk-imx6sl.c writel_relaxed(val, anatop_base + PLL_ARM); val 60 drivers/clk/imx/clk-imx6sll.c { .val = 2, .div = 1, }, val 61 drivers/clk/imx/clk-imx6sll.c { .val = 1, .div = 2, }, val 62 drivers/clk/imx/clk-imx6sll.c { .val = 0, .div = 4, }, val 67 drivers/clk/imx/clk-imx6sll.c { .val = 0, .div = 1, }, val 68 drivers/clk/imx/clk-imx6sll.c { .val = 1, .div = 2, }, val 69 drivers/clk/imx/clk-imx6sll.c { .val = 2, .div = 1, }, val 70 drivers/clk/imx/clk-imx6sll.c { .val = 3, .div = 4, }, val 88 drivers/clk/imx/clk-imx6sx.c { .val = 0, .div = 20, }, val 89 drivers/clk/imx/clk-imx6sx.c { .val = 1, .div = 10, }, val 90 drivers/clk/imx/clk-imx6sx.c { .val = 2, .div = 5, }, val 91 drivers/clk/imx/clk-imx6sx.c { .val = 3, .div = 4, }, val 96 drivers/clk/imx/clk-imx6sx.c { .val = 2, .div = 1, }, val 97 drivers/clk/imx/clk-imx6sx.c { .val = 1, .div = 2, }, val 98 drivers/clk/imx/clk-imx6sx.c { .val = 0, .div = 4, }, val 103 drivers/clk/imx/clk-imx6sx.c { .val = 0, .div = 1, }, val 104 drivers/clk/imx/clk-imx6sx.c { .val = 1, .div = 2, }, val 105 drivers/clk/imx/clk-imx6sx.c { .val = 2, .div = 1, }, val 106 drivers/clk/imx/clk-imx6sx.c { .val = 3, .div = 4, }, val 75 drivers/clk/imx/clk-imx6ul.c { .val = 0, .div = 20, }, val 76 drivers/clk/imx/clk-imx6ul.c { .val = 1, .div = 10, }, val 77 drivers/clk/imx/clk-imx6ul.c { .val = 2, .div = 5, }, val 78 drivers/clk/imx/clk-imx6ul.c { .val = 3, .div = 4, }, val 83 drivers/clk/imx/clk-imx6ul.c { .val = 2, .div = 1, }, val 84 drivers/clk/imx/clk-imx6ul.c { .val = 1, .div = 2, }, val 85 drivers/clk/imx/clk-imx6ul.c { .val = 0, .div = 4, }, val 90 drivers/clk/imx/clk-imx6ul.c { .val = 0, .div = 1, }, val 91 drivers/clk/imx/clk-imx6ul.c { .val = 1, .div = 2, }, val 92 drivers/clk/imx/clk-imx6ul.c { .val = 2, .div = 1, }, val 93 drivers/clk/imx/clk-imx6ul.c { .val = 3, .div = 4, }, val 28 drivers/clk/imx/clk-imx7d.c { .val = 3, .div = 1, }, val 29 drivers/clk/imx/clk-imx7d.c { .val = 2, .div = 1, }, val 30 drivers/clk/imx/clk-imx7d.c { .val = 1, .div = 2, }, val 31 drivers/clk/imx/clk-imx7d.c { .val = 0, .div = 4, }, val 36 drivers/clk/imx/clk-imx7d.c { .val = 3, .div = 4, }, val 37 drivers/clk/imx/clk-imx7d.c { .val = 2, .div = 1, }, val 38 drivers/clk/imx/clk-imx7d.c { .val = 1, .div = 2, }, val 39 drivers/clk/imx/clk-imx7d.c { .val = 0, .div = 1, }, val 36 drivers/clk/imx/clk-imx7ulp.c { .val = 1, .div = 1, }, val 37 drivers/clk/imx/clk-imx7ulp.c { .val = 2, .div = 2, }, val 38 drivers/clk/imx/clk-imx7ulp.c { .val = 3, .div = 4, }, val 39 drivers/clk/imx/clk-imx7ulp.c { .val = 4, .div = 8, }, val 40 drivers/clk/imx/clk-imx7ulp.c { .val = 5, .div = 16, }, val 41 drivers/clk/imx/clk-imx7ulp.c { .val = 6, .div = 32, }, val 42 drivers/clk/imx/clk-imx7ulp.c { .val = 7, .div = 64, }, val 44 drivers/clk/imx/clk-lpcg-scu.c u32 reg, val; val 51 drivers/clk/imx/clk-lpcg-scu.c val = CLK_GATE_SCU_LPCG_SW_SEL; val 53 drivers/clk/imx/clk-lpcg-scu.c val |= CLK_GATE_SCU_LPCG_HW_SEL; val 55 drivers/clk/imx/clk-lpcg-scu.c reg |= val << clk->bit_idx; val 45 drivers/clk/imx/clk-pfdv2.c u32 val; val 47 drivers/clk/imx/clk-pfdv2.c return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit), val 55 drivers/clk/imx/clk-pfdv2.c u32 val; val 58 drivers/clk/imx/clk-pfdv2.c val = readl_relaxed(pfd->reg); val 59 drivers/clk/imx/clk-pfdv2.c val &= ~(1 << pfd->gate_bit); val 60 drivers/clk/imx/clk-pfdv2.c writel_relaxed(val, pfd->reg); val 70 drivers/clk/imx/clk-pfdv2.c u32 val; val 73 drivers/clk/imx/clk-pfdv2.c val = readl_relaxed(pfd->reg); val 74 drivers/clk/imx/clk-pfdv2.c val |= (1 << pfd->gate_bit); val 75 drivers/clk/imx/clk-pfdv2.c writel_relaxed(val, pfd->reg); val 139 drivers/clk/imx/clk-pfdv2.c u32 val; val 151 drivers/clk/imx/clk-pfdv2.c val = readl_relaxed(pfd->reg); val 152 drivers/clk/imx/clk-pfdv2.c val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off); val 153 drivers/clk/imx/clk-pfdv2.c val |= frac << pfd->frac_off; val 154 drivers/clk/imx/clk-pfdv2.c writel_relaxed(val, pfd->reg); val 128 drivers/clk/imx/clk-pll14xx.c u32 val; val 130 drivers/clk/imx/clk-pll14xx.c return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0, val 269 drivers/clk/imx/clk-pll14xx.c u32 val; val 276 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); val 277 drivers/clk/imx/clk-pll14xx.c if (val & RST_MASK) val 279 drivers/clk/imx/clk-pll14xx.c val |= BYPASS_MASK; val 280 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); val 281 drivers/clk/imx/clk-pll14xx.c val |= RST_MASK; val 282 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); val 288 drivers/clk/imx/clk-pll14xx.c val &= ~BYPASS_MASK; val 289 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); val 297 drivers/clk/imx/clk-pll14xx.c u32 val; val 299 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); val 301 drivers/clk/imx/clk-pll14xx.c return (val & RST_MASK) ? 1 : 0; val 307 drivers/clk/imx/clk-pll14xx.c u32 val; val 313 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); val 314 drivers/clk/imx/clk-pll14xx.c val &= ~RST_MASK; val 315 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); val 347 drivers/clk/imx/clk-pll14xx.c u32 val; val 379 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); val 380 drivers/clk/imx/clk-pll14xx.c val &= ~BYPASS_MASK; val 381 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); val 57 drivers/clk/imx/clk-pllv3.c u32 val = readl_relaxed(pll->base) & pll->power_bit; val 60 drivers/clk/imx/clk-pllv3.c if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) val 78 drivers/clk/imx/clk-pllv3.c u32 val; val 80 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); val 82 drivers/clk/imx/clk-pllv3.c val |= pll->power_bit; val 84 drivers/clk/imx/clk-pllv3.c val &= ~pll->power_bit; val 85 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); val 93 drivers/clk/imx/clk-pllv3.c u32 val; val 95 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); val 97 drivers/clk/imx/clk-pllv3.c val &= ~pll->power_bit; val 99 drivers/clk/imx/clk-pllv3.c val |= pll->power_bit; val 100 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); val 135 drivers/clk/imx/clk-pllv3.c u32 val, div; val 144 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); val 145 drivers/clk/imx/clk-pllv3.c val &= ~(pll->div_mask << pll->div_shift); val 146 drivers/clk/imx/clk-pllv3.c val |= (div << pll->div_shift); val 147 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); val 193 drivers/clk/imx/clk-pllv3.c u32 val, div; val 199 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); val 200 drivers/clk/imx/clk-pllv3.c val &= ~pll->div_mask; val 201 drivers/clk/imx/clk-pllv3.c val |= div; val 202 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); val 269 drivers/clk/imx/clk-pllv3.c u32 val, div; val 286 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); val 287 drivers/clk/imx/clk-pllv3.c val &= ~pll->div_mask; val 288 drivers/clk/imx/clk-pllv3.c val |= div; val 289 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); val 374 drivers/clk/imx/clk-pllv3.c u32 val; val 376 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); val 378 drivers/clk/imx/clk-pllv3.c val &= ~pll->div_mask; /* clear bit for mfi=20 */ val 380 drivers/clk/imx/clk-pllv3.c val |= pll->div_mask; /* set bit for mfi=22 */ val 381 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); val 151 drivers/clk/imx/clk-pllv4.c u32 val, mult, mfn, mfd = DEFAULT_MFD; val 167 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base + PLL_CFG_OFFSET); val 168 drivers/clk/imx/clk-pllv4.c val &= ~BM_PLL_MULT; val 169 drivers/clk/imx/clk-pllv4.c val |= mult << BP_PLL_MULT; val 170 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base + PLL_CFG_OFFSET); val 180 drivers/clk/imx/clk-pllv4.c u32 val; val 183 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base); val 184 drivers/clk/imx/clk-pllv4.c val |= PLL_EN; val 185 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base); val 192 drivers/clk/imx/clk-pllv4.c u32 val; val 195 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base); val 196 drivers/clk/imx/clk-pllv4.c val &= ~PLL_EN; val 197 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base); val 103 drivers/clk/imx/clk-sccg-pll.c u32 val; val 105 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 108 drivers/clk/imx/clk-sccg-pll.c if (!(val & SSCG_PLL_BYPASS2_MASK)) val 109 drivers/clk/imx/clk-sccg-pll.c return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, val 309 drivers/clk/imx/clk-sccg-pll.c u32 val = readl_relaxed(pll->base + PLL_CFG0); val 311 drivers/clk/imx/clk-sccg-pll.c return (val & PLL_PD_MASK) ? 0 : 1; val 317 drivers/clk/imx/clk-sccg-pll.c u32 val; val 319 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 320 drivers/clk/imx/clk-sccg-pll.c val &= ~PLL_PD_MASK; val 321 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG0); val 329 drivers/clk/imx/clk-sccg-pll.c u32 val; val 331 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); val 332 drivers/clk/imx/clk-sccg-pll.c val |= PLL_PD_MASK; val 333 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG0); val 340 drivers/clk/imx/clk-sccg-pll.c u32 val, divr1, divf1, divr2, divf2, divq; val 343 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG2); val 344 drivers/clk/imx/clk-sccg-pll.c divr1 = FIELD_GET(PLL_DIVR1_MASK, val); val 345 drivers/clk/imx/clk-sccg-pll.c divr2 = FIELD_GET(PLL_DIVR2_MASK, val); val 346 drivers/clk/imx/clk-sccg-pll.c divf1 = FIELD_GET(PLL_DIVF1_MASK, val); val 347 drivers/clk/imx/clk-sccg-pll.c divf2 = FIELD_GET(PLL_DIVF2_MASK, val); val 348 drivers/clk/imx/clk-sccg-pll.c divq = FIELD_GET(PLL_DIVQ_MASK, val); val 352 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); val 353 drivers/clk/imx/clk-sccg-pll.c if (val & SSCG_PLL_BYPASS2_MASK) { val 355 drivers/clk/imx/clk-sccg-pll.c } else if (val & SSCG_PLL_BYPASS1_MASK) { val 372 drivers/clk/imx/clk-sccg-pll.c u32 val; val 375 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); val 376 drivers/clk/imx/clk-sccg-pll.c val &= ~SSCG_PLL_BYPASS_MASK; val 377 drivers/clk/imx/clk-sccg-pll.c val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); val 378 drivers/clk/imx/clk-sccg-pll.c writel(val, pll->base + PLL_CFG0); val 380 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG2); val 381 drivers/clk/imx/clk-sccg-pll.c val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK); val 382 drivers/clk/imx/clk-sccg-pll.c val &= ~(PLL_DIVR1_MASK | PLL_DIVR2_MASK | PLL_DIVQ_MASK); val 383 drivers/clk/imx/clk-sccg-pll.c val |= FIELD_PREP(PLL_DIVF1_MASK, setup->divf1); val 384 drivers/clk/imx/clk-sccg-pll.c val |= FIELD_PREP(PLL_DIVF2_MASK, setup->divf2); val 385 drivers/clk/imx/clk-sccg-pll.c val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1); val 386 drivers/clk/imx/clk-sccg-pll.c val |= FIELD_PREP(PLL_DIVR2_MASK, setup->divr2); val 387 drivers/clk/imx/clk-sccg-pll.c val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq); val 388 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG2); val 396 drivers/clk/imx/clk-sccg-pll.c u32 val; val 399 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); val 400 drivers/clk/imx/clk-sccg-pll.c if (val & SSCG_PLL_BYPASS2_MASK) val 402 drivers/clk/imx/clk-sccg-pll.c else if (val & SSCG_PLL_BYPASS1_MASK) val 410 drivers/clk/imx/clk-sccg-pll.c u32 val; val 412 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); val 413 drivers/clk/imx/clk-sccg-pll.c val &= ~SSCG_PLL_BYPASS_MASK; val 414 drivers/clk/imx/clk-sccg-pll.c val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); val 415 drivers/clk/imx/clk-sccg-pll.c writel(val, pll->base + PLL_CFG0); val 101 drivers/clk/imx/clk-vf610.c { .val = 0, .div = 1 }, val 102 drivers/clk/imx/clk-vf610.c { .val = 1, .div = 2 }, val 103 drivers/clk/imx/clk-vf610.c { .val = 2, .div = 6 }, val 104 drivers/clk/imx/clk-vf610.c { .val = 3, .div = 8 }, val 105 drivers/clk/imx/clk-vf610.c { .val = 4, .div = 10 }, val 106 drivers/clk/imx/clk-vf610.c { .val = 5, .div = 12 }, val 107 drivers/clk/imx/clk-vf610.c { .val = 6, .div = 14 }, val 108 drivers/clk/imx/clk-vf610.c { .val = 7, .div = 16 }, val 129 drivers/clk/imx/clk.c void imx_cscmr1_fixup(u32 *val) val 131 drivers/clk/imx/clk.c *val ^= CSCMR1_FIXUP; val 16 drivers/clk/imx/clk.h extern void imx_cscmr1_fixup(u32 *val); val 192 drivers/clk/imx/clk.h void (*fixup)(u32 *val)); val 196 drivers/clk/imx/clk.h int num_parents, void (*fixup)(u32 *val)); val 54 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_gate_info *info, bool val) val 58 drivers/clk/ingenic/cgu.c if (val ^ info->clear_to_gate) val 20 drivers/clk/ingenic/pm.c u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); val 22 drivers/clk/ingenic/pm.c writel(val | LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR); val 29 drivers/clk/ingenic/pm.c u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); val 31 drivers/clk/ingenic/pm.c writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR); val 130 drivers/clk/ingenic/tcu.c unsigned int val = 0; val 133 drivers/clk/ingenic/tcu.c ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val); val 136 drivers/clk/ingenic/tcu.c return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1; val 81 drivers/clk/keystone/pll.c u32 mult = 0, prediv, postdiv, val; val 88 drivers/clk/keystone/pll.c val = readl(pll_data->pllm); val 89 drivers/clk/keystone/pll.c mult = (val & pll_data->pllm_lower_mask); val 93 drivers/clk/keystone/pll.c val = readl(pll_data->pll_ctl0); val 94 drivers/clk/keystone/pll.c mult |= ((val & pll_data->pllm_upper_mask) val 96 drivers/clk/keystone/pll.c prediv = (val & pll_data->plld_mask); val 100 drivers/clk/keystone/pll.c postdiv = ((val & pll_data->clkod_mask) >> val 36 drivers/clk/loongson1/clk-loongson1c.c [0] = { .val = 0, .div = 2 }, val 37 drivers/clk/loongson1/clk-loongson1c.c [1] = { .val = 1, .div = 4 }, val 38 drivers/clk/loongson1/clk-loongson1c.c [2] = { .val = 2, .div = 3 }, val 39 drivers/clk/loongson1/clk-loongson1c.c [3] = { .val = 3, .div = 3 }, val 39 drivers/clk/mediatek/clk-apmixed.c u32 val; val 41 drivers/clk/mediatek/clk-apmixed.c val = readl(tx->base_addr); val 43 drivers/clk/mediatek/clk-apmixed.c val |= REF2USB_TX_EN; val 44 drivers/clk/mediatek/clk-apmixed.c writel(val, tx->base_addr); val 47 drivers/clk/mediatek/clk-apmixed.c val |= REF2USB_TX_LPF_EN; val 48 drivers/clk/mediatek/clk-apmixed.c writel(val, tx->base_addr); val 50 drivers/clk/mediatek/clk-apmixed.c val |= REF2USB_TX_OUT_EN; val 51 drivers/clk/mediatek/clk-apmixed.c writel(val, tx->base_addr); val 59 drivers/clk/mediatek/clk-apmixed.c u32 val; val 61 drivers/clk/mediatek/clk-apmixed.c val = readl(tx->base_addr); val 62 drivers/clk/mediatek/clk-apmixed.c val &= ~REF2USB_EN_MASK; val 63 drivers/clk/mediatek/clk-apmixed.c writel(val, tx->base_addr); val 22 drivers/clk/mediatek/clk-cpumux.c unsigned int val; val 24 drivers/clk/mediatek/clk-cpumux.c regmap_read(mux->regmap, mux->reg, &val); val 26 drivers/clk/mediatek/clk-cpumux.c val >>= mux->shift; val 27 drivers/clk/mediatek/clk-cpumux.c val &= mux->mask; val 29 drivers/clk/mediatek/clk-cpumux.c return val; val 35 drivers/clk/mediatek/clk-cpumux.c u32 mask, val; val 37 drivers/clk/mediatek/clk-cpumux.c val = index << mux->shift; val 40 drivers/clk/mediatek/clk-cpumux.c return regmap_update_bits(mux->regmap, mux->reg, mask, val); val 21 drivers/clk/mediatek/clk-gate.c u32 val; val 23 drivers/clk/mediatek/clk-gate.c regmap_read(cg->regmap, cg->sta_ofs, &val); val 25 drivers/clk/mediatek/clk-gate.c val &= BIT(cg->bit); val 27 drivers/clk/mediatek/clk-gate.c return val == 0; val 33 drivers/clk/mediatek/clk-gate.c u32 val; val 35 drivers/clk/mediatek/clk-gate.c regmap_read(cg->regmap, cg->sta_ofs, &val); val 37 drivers/clk/mediatek/clk-gate.c val &= BIT(cg->bit); val 39 drivers/clk/mediatek/clk-gate.c return val != 0; val 56 drivers/clk/mediatek/clk-mux.c u32 val; val 58 drivers/clk/mediatek/clk-mux.c regmap_read(mux->regmap, mux->data->mux_ofs, &val); val 60 drivers/clk/mediatek/clk-mux.c return (val & BIT(mux->data->gate_shift)) == 0; val 67 drivers/clk/mediatek/clk-mux.c u32 val; val 69 drivers/clk/mediatek/clk-mux.c regmap_read(mux->regmap, mux->data->mux_ofs, &val); val 70 drivers/clk/mediatek/clk-mux.c val = (val >> mux->data->mux_shift) & mask; val 72 drivers/clk/mediatek/clk-mux.c return val; val 101 drivers/clk/mediatek/clk-mux.c u32 val, orig; val 110 drivers/clk/mediatek/clk-mux.c val = (orig & ~(mask << mux->data->mux_shift)) val 113 drivers/clk/mediatek/clk-mux.c if (val != orig) { val 118 drivers/clk/mediatek/clk-pll.c u32 chg, val; val 124 drivers/clk/mediatek/clk-pll.c val = readl(pll->pd_addr); val 125 drivers/clk/mediatek/clk-pll.c val &= ~(POSTDIV_MASK << pll->data->pd_shift); val 126 drivers/clk/mediatek/clk-pll.c val |= (ffs(postdiv) - 1) << pll->data->pd_shift; val 130 drivers/clk/mediatek/clk-pll.c writel(val, pll->pd_addr); val 131 drivers/clk/mediatek/clk-pll.c val = readl(pll->pcw_addr); val 135 drivers/clk/mediatek/clk-pll.c val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1, val 137 drivers/clk/mediatek/clk-pll.c val |= pcw << pll->data->pcw_shift; val 138 drivers/clk/mediatek/clk-pll.c writel(val, pll->pcw_addr); val 142 drivers/clk/mediatek/clk-pll.c writel(val + 1, pll->tuner_addr); val 166 drivers/clk/mediatek/clk-pll.c u32 val; val 175 drivers/clk/mediatek/clk-pll.c for (val = 0; div_table[val + 1].freq != 0; val++) { val 176 drivers/clk/mediatek/clk-pll.c if (freq > div_table[val + 1].freq) val 179 drivers/clk/mediatek/clk-pll.c *postdiv = 1 << val; val 181 drivers/clk/mediatek/clk-pll.c for (val = 0; val < 5; val++) { val 182 drivers/clk/mediatek/clk-pll.c *postdiv = 1 << val; val 190 drivers/clk/mediatek/clk-pll.c _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); val 960 drivers/clk/meson/axg-audio.c unsigned int val, offset, bit; val 964 drivers/clk/meson/axg-audio.c regmap_read(rst->map, offset, &val); val 966 drivers/clk/meson/axg-audio.c return !!(val & BIT(bit)); val 45 drivers/clk/meson/clk-cpu-dyndiv.c unsigned int val; val 52 drivers/clk/meson/clk-cpu-dyndiv.c val = (unsigned int)ret << data->div.shift; val 61 drivers/clk/meson/clk-cpu-dyndiv.c val); val 21 drivers/clk/meson/clk-phase.c static int meson_clk_degrees_from_val(unsigned int val, unsigned int width) val 23 drivers/clk/meson/clk-phase.c return phase_step(width) * val; val 28 drivers/clk/meson/clk-phase.c unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width)); val 34 drivers/clk/meson/clk-phase.c return val % (1 << width); val 41 drivers/clk/meson/clk-phase.c unsigned int val; val 43 drivers/clk/meson/clk-phase.c val = meson_parm_read(clk->map, &phase->ph); val 45 drivers/clk/meson/clk-phase.c return meson_clk_degrees_from_val(val, phase->ph.width); val 52 drivers/clk/meson/clk-phase.c unsigned int val; val 54 drivers/clk/meson/clk-phase.c val = meson_clk_degrees_to_val(degrees, phase->ph.width); val 55 drivers/clk/meson/clk-phase.c meson_parm_write(clk->map, &phase->ph, val); val 85 drivers/clk/meson/clk-phase.c unsigned int val; val 88 drivers/clk/meson/clk-phase.c val = meson_parm_read(clk->map, &tph->ph0); val 89 drivers/clk/meson/clk-phase.c meson_parm_write(clk->map, &tph->ph1, val); val 90 drivers/clk/meson/clk-phase.c meson_parm_write(clk->map, &tph->ph2, val); val 97 drivers/clk/meson/clk-phase.c unsigned int val; val 100 drivers/clk/meson/clk-phase.c val = meson_parm_read(clk->map, &tph->ph0); val 102 drivers/clk/meson/clk-phase.c return meson_clk_degrees_from_val(val, tph->ph0.width); val 109 drivers/clk/meson/clk-phase.c unsigned int val; val 111 drivers/clk/meson/clk-phase.c val = meson_clk_degrees_to_val(degrees, tph->ph0.width); val 112 drivers/clk/meson/clk-phase.c meson_parm_write(clk->map, &tph->ph0, val); val 113 drivers/clk/meson/clk-phase.c meson_parm_write(clk->map, &tph->ph1, val); val 114 drivers/clk/meson/clk-phase.c meson_parm_write(clk->map, &tph->ph2, val); val 105 drivers/clk/meson/clk-pll.c u64 val = (u64)rate * n; val 112 drivers/clk/meson/clk-pll.c val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate); val 114 drivers/clk/meson/clk-pll.c val = div_u64(val * frac_max, parent_rate); val 116 drivers/clk/meson/clk-pll.c val -= m * frac_max; val 118 drivers/clk/meson/clk-pll.c return min((unsigned int)val, (frac_max - 1)); val 158 drivers/clk/meson/clk-pll.c u64 val = (u64)rate * n; val 161 drivers/clk/meson/clk-pll.c return DIV_ROUND_CLOSEST_ULL(val, parent_rate); val 163 drivers/clk/meson/clk-pll.c return div_u64(val, parent_rate); val 36 drivers/clk/meson/clk-regmap.c unsigned int val; val 38 drivers/clk/meson/clk-regmap.c regmap_read(clk->map, gate->offset, &val); val 40 drivers/clk/meson/clk-regmap.c val ^= BIT(gate->bit_idx); val 42 drivers/clk/meson/clk-regmap.c val &= BIT(gate->bit_idx); val 44 drivers/clk/meson/clk-regmap.c return val ? 1 : 0; val 64 drivers/clk/meson/clk-regmap.c unsigned int val; val 67 drivers/clk/meson/clk-regmap.c ret = regmap_read(clk->map, div->offset, &val); val 72 drivers/clk/meson/clk-regmap.c val >>= div->shift; val 73 drivers/clk/meson/clk-regmap.c val &= clk_div_mask(div->width); val 74 drivers/clk/meson/clk-regmap.c return divider_recalc_rate(hw, prate, val, div->table, div->flags, val 83 drivers/clk/meson/clk-regmap.c unsigned int val; val 88 drivers/clk/meson/clk-regmap.c ret = regmap_read(clk->map, div->offset, &val); val 93 drivers/clk/meson/clk-regmap.c val >>= div->shift; val 94 drivers/clk/meson/clk-regmap.c val &= clk_div_mask(div->width); val 97 drivers/clk/meson/clk-regmap.c div->width, div->flags, val); val 109 drivers/clk/meson/clk-regmap.c unsigned int val; val 117 drivers/clk/meson/clk-regmap.c val = (unsigned int)ret << div->shift; val 119 drivers/clk/meson/clk-regmap.c clk_div_mask(div->width) << div->shift, val); val 141 drivers/clk/meson/clk-regmap.c unsigned int val; val 144 drivers/clk/meson/clk-regmap.c ret = regmap_read(clk->map, mux->offset, &val); val 148 drivers/clk/meson/clk-regmap.c val >>= mux->shift; val 149 drivers/clk/meson/clk-regmap.c val &= mux->mask; val 150 drivers/clk/meson/clk-regmap.c return clk_mux_val_to_index(hw, mux->table, mux->flags, val); val 157 drivers/clk/meson/clk-regmap.c unsigned int val = clk_mux_index_to_val(mux->table, mux->flags, index); val 161 drivers/clk/meson/clk-regmap.c val << mux->shift); val 2627 drivers/clk/meson/g12a.c .val = { val 1734 drivers/clk/meson/gxbb.c .val = { val 673 drivers/clk/meson/meson8b.c { .val = 1, .div = 4 }, val 674 drivers/clk/meson/meson8b.c { .val = 2, .div = 6 }, val 675 drivers/clk/meson/meson8b.c { .val = 3, .div = 8 }, val 676 drivers/clk/meson/meson8b.c { .val = 4, .div = 10 }, val 677 drivers/clk/meson/meson8b.c { .val = 5, .div = 12 }, val 678 drivers/clk/meson/meson8b.c { .val = 6, .div = 14 }, val 679 drivers/clk/meson/meson8b.c { .val = 7, .div = 16 }, val 680 drivers/clk/meson/meson8b.c { .val = 8, .div = 18 }, val 19 drivers/clk/meson/parm.h #define PARM_SET(width, shift, reg, val) \ val 20 drivers/clk/meson/parm.h (((reg) & CLRPMASK(width, shift)) | ((val) << (shift))) val 32 drivers/clk/meson/parm.h unsigned int val; val 34 drivers/clk/meson/parm.h regmap_read(map, p->reg_off, &val); val 35 drivers/clk/meson/parm.h return PARM_GET(p->width, p->shift, val); val 39 drivers/clk/meson/parm.h unsigned int val) val 42 drivers/clk/meson/parm.h val << p->shift); val 223 drivers/clk/meson/sclk-div.c unsigned int val; val 225 drivers/clk/meson/sclk-div.c val = meson_parm_read(clk->map, &sclk->div); val 228 drivers/clk/meson/sclk-div.c if (!val) val 231 drivers/clk/meson/sclk-div.c sclk->cached_div = val + 1; val 82 drivers/clk/meson/vid-pll-div.c div = _get_table_val(meson_parm_read(clk->map, &pll_div->val), val 14 drivers/clk/meson/vid-pll-div.h struct parm val; val 56 drivers/clk/mmp/clk-frac.c unsigned int val, num, den; val 58 drivers/clk/mmp/clk-frac.c val = readl_relaxed(factor->base); val 61 drivers/clk/mmp/clk-frac.c num = (val >> masks->num_shift) & masks->num_mask; val 64 drivers/clk/mmp/clk-frac.c den = (val >> masks->den_shift) & masks->den_mask; val 80 drivers/clk/mmp/clk-frac.c unsigned long val; val 96 drivers/clk/mmp/clk-frac.c val = readl_relaxed(factor->base); val 98 drivers/clk/mmp/clk-frac.c val &= ~(masks->num_mask << masks->num_shift); val 99 drivers/clk/mmp/clk-frac.c val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; val 101 drivers/clk/mmp/clk-frac.c val &= ~(masks->den_mask << masks->den_shift); val 102 drivers/clk/mmp/clk-frac.c val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift; val 104 drivers/clk/mmp/clk-frac.c writel_relaxed(val, factor->base); val 116 drivers/clk/mmp/clk-frac.c u32 val, num, den; val 123 drivers/clk/mmp/clk-frac.c val = readl(factor->base); val 126 drivers/clk/mmp/clk-frac.c num = (val >> masks->num_shift) & masks->num_mask; val 129 drivers/clk/mmp/clk-frac.c den = (val >> masks->den_shift) & masks->den_mask; val 136 drivers/clk/mmp/clk-frac.c val &= ~(masks->num_mask << masks->num_shift); val 137 drivers/clk/mmp/clk-frac.c val |= (factor->ftbl[0].num & masks->num_mask) << val 140 drivers/clk/mmp/clk-frac.c val &= ~(masks->den_mask << masks->den_shift); val 141 drivers/clk/mmp/clk-frac.c val |= (factor->ftbl[0].den & masks->den_mask) << val 144 drivers/clk/mmp/clk-frac.c writel(val, factor->base); val 46 drivers/clk/mmp/clk-mix.c static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val) val 51 drivers/clk/mmp/clk-mix.c return val; val 53 drivers/clk/mmp/clk-mix.c return 1 << val; val 56 drivers/clk/mmp/clk-mix.c if (clkt->val == val) val 61 drivers/clk/mmp/clk-mix.c return val + 1; val 64 drivers/clk/mmp/clk-mix.c static unsigned int _get_mux(struct mmp_clk_mix *mix, unsigned int val) val 70 drivers/clk/mmp/clk-mix.c return ffs(val) - 1; val 72 drivers/clk/mmp/clk-mix.c return val - 1; val 75 drivers/clk/mmp/clk-mix.c if (mix->mux_table[i] == val) val 81 drivers/clk/mmp/clk-mix.c return val; val 94 drivers/clk/mmp/clk-mix.c return clkt->val; val 46 drivers/clk/mmp/clk.h #define MMP_CLK_BITS_SET_VAL(val, width, shift) \ val 47 drivers/clk/mmp/clk.h (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift)) val 40 drivers/clk/mmp/reset.c u32 val; val 46 drivers/clk/mmp/reset.c val = readl(cell->reg); val 47 drivers/clk/mmp/reset.c val |= cell->bits; val 48 drivers/clk/mmp/reset.c writel(val, cell->reg); val 62 drivers/clk/mmp/reset.c u32 val; val 68 drivers/clk/mmp/reset.c val = readl(cell->reg); val 69 drivers/clk/mmp/reset.c val &= ~cell->bits; val 70 drivers/clk/mmp/reset.c writel(val, cell->reg); val 104 drivers/clk/mvebu/armada-37xx-periph.c { .val = 1, .div = 1, }, val 105 drivers/clk/mvebu/armada-37xx-periph.c { .val = 2, .div = 2, }, val 106 drivers/clk/mvebu/armada-37xx-periph.c { .val = 3, .div = 3, }, val 107 drivers/clk/mvebu/armada-37xx-periph.c { .val = 4, .div = 4, }, val 108 drivers/clk/mvebu/armada-37xx-periph.c { .val = 5, .div = 5, }, val 109 drivers/clk/mvebu/armada-37xx-periph.c { .val = 6, .div = 6, }, val 110 drivers/clk/mvebu/armada-37xx-periph.c { .val = 0, .div = 0, }, /* last entry */ val 114 drivers/clk/mvebu/armada-37xx-periph.c { .val = 0, .div = 1, }, val 115 drivers/clk/mvebu/armada-37xx-periph.c { .val = 1, .div = 2, }, val 116 drivers/clk/mvebu/armada-37xx-periph.c { .val = 0, .div = 0, }, /* last entry */ val 120 drivers/clk/mvebu/armada-37xx-periph.c { .val = 0, .div = 2, }, val 121 drivers/clk/mvebu/armada-37xx-periph.c { .val = 1, .div = 4, }, val 122 drivers/clk/mvebu/armada-37xx-periph.c { .val = 0, .div = 0, }, /* last entry */ val 326 drivers/clk/mvebu/armada-37xx-periph.c u32 val; val 328 drivers/clk/mvebu/armada-37xx-periph.c val = (readl(reg) >> shift) & 0x7; val 329 drivers/clk/mvebu/armada-37xx-periph.c if (val > 6) val 331 drivers/clk/mvebu/armada-37xx-periph.c return val; val 366 drivers/clk/mvebu/armada-37xx-periph.c unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD; val 371 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); val 373 drivers/clk/mvebu/armada-37xx-periph.c return !!(val & BIT(ARMADA_37XX_NB_DFS_EN)); val 429 drivers/clk/mvebu/armada-37xx-periph.c u32 val; val 432 drivers/clk/mvebu/armada-37xx-periph.c val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base); val 434 drivers/clk/mvebu/armada-37xx-periph.c val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux; val 435 drivers/clk/mvebu/armada-37xx-periph.c val &= pm_cpu->mask_mux; val 438 drivers/clk/mvebu/armada-37xx-periph.c return val; val 456 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg, mask, val, val 461 drivers/clk/mvebu/armada-37xx-periph.c val = index << offset; val 463 drivers/clk/mvebu/armada-37xx-periph.c regmap_update_bits(base, reg, mask, val); val 493 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF; val 497 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); val 499 drivers/clk/mvebu/armada-37xx-periph.c val >>= offset; val 500 drivers/clk/mvebu/armada-37xx-periph.c val &= ARMADA_37XX_NB_TBG_DIV_MASK; val 501 drivers/clk/mvebu/armada-37xx-periph.c if (val == div) val 561 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg, mask, val, val 566 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); val 567 drivers/clk/mvebu/armada-37xx-periph.c val >>= offset; val 568 drivers/clk/mvebu/armada-37xx-periph.c val &= ARMADA_37XX_NB_TBG_DIV_MASK; val 570 drivers/clk/mvebu/armada-37xx-periph.c if (val == div) { val 56 drivers/clk/mvebu/armada-37xx-tbg.c u32 val; val 58 drivers/clk/mvebu/armada-37xx-tbg.c val = readl(reg + TBG_CTRL0); val 60 drivers/clk/mvebu/armada-37xx-tbg.c return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2; val 65 drivers/clk/mvebu/armada-37xx-tbg.c u32 val; val 68 drivers/clk/mvebu/armada-37xx-tbg.c val = readl(reg + TBG_CTRL7); val 70 drivers/clk/mvebu/armada-37xx-tbg.c div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK; val 73 drivers/clk/mvebu/armada-37xx-tbg.c val = readl(reg + ptbg->vcodiv_reg); val 75 drivers/clk/mvebu/armada-37xx-tbg.c div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK); val 142 drivers/clk/mvebu/cp110-system-controller.c u32 val; val 144 drivers/clk/mvebu/cp110-system-controller.c regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val); val 146 drivers/clk/mvebu/cp110-system-controller.c return val & BIT(gate->bit_idx); val 37 drivers/clk/mvebu/dove-divider.c static void dove_load_divider(void __iomem *base, u32 val, u32 mask, u32 load) val 44 drivers/clk/mvebu/dove-divider.c v = (readl_relaxed(base + DIV_CTRL0) & ~(mask | load)) | val; val 54 drivers/clk/mvebu/dove-divider.c u32 val; val 56 drivers/clk/mvebu/dove-divider.c val = readl_relaxed(dc->base + DIV_CTRL0); val 57 drivers/clk/mvebu/dove-divider.c val >>= dc->div_bit_start; val 59 drivers/clk/mvebu/dove-divider.c divider = val & ~(~0 << dc->div_bit_size); val 78 drivers/clk/mxs/clk-frac.c u32 div, val; val 94 drivers/clk/mxs/clk-frac.c val = readl_relaxed(frac->reg); val 95 drivers/clk/mxs/clk-frac.c val &= ~(((1 << frac->width) - 1) << frac->shift); val 96 drivers/clk/mxs/clk-frac.c val |= div << frac->shift; val 97 drivers/clk/mxs/clk-frac.c writel_relaxed(val, frac->reg); val 46 drivers/clk/mxs/clk-imx23.c u32 val; val 55 drivers/clk/mxs/clk-imx23.c val = readl_relaxed(SAIF); val 56 drivers/clk/mxs/clk-imx23.c val |= 1 << BP_SAIF_DIV_FRAC_EN; val 57 drivers/clk/mxs/clk-imx23.c writel_relaxed(val, SAIF); val 81 drivers/clk/mxs/clk-imx28.c u32 val; val 93 drivers/clk/mxs/clk-imx28.c val = readl_relaxed(SAIF0); val 94 drivers/clk/mxs/clk-imx28.c val |= 1 << BP_SAIF_DIV_FRAC_EN; val 95 drivers/clk/mxs/clk-imx28.c writel_relaxed(val, SAIF0); val 97 drivers/clk/mxs/clk-imx28.c val = readl_relaxed(SAIF1); val 98 drivers/clk/mxs/clk-imx28.c val |= 1 << BP_SAIF_DIV_FRAC_EN; val 99 drivers/clk/mxs/clk-imx28.c writel_relaxed(val, SAIF1); val 102 drivers/clk/mxs/clk-imx28.c val = readl_relaxed(ENET); val 103 drivers/clk/mxs/clk-imx28.c val &= ~(1 << BP_ENET_SLEEP); val 104 drivers/clk/mxs/clk-imx28.c writel_relaxed(val, ENET); val 116 drivers/clk/mxs/clk-imx28.c val = readl_relaxed(FRAC0); val 117 drivers/clk/mxs/clk-imx28.c val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC)); val 118 drivers/clk/mxs/clk-imx28.c val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC); val 119 drivers/clk/mxs/clk-imx28.c writel_relaxed(val, FRAC0); val 89 drivers/clk/mxs/clk-ref.c u32 val; val 103 drivers/clk/mxs/clk-ref.c val = readl_relaxed(ref->reg); val 104 drivers/clk/mxs/clk-ref.c val &= ~(0x3f << shift); val 105 drivers/clk/mxs/clk-ref.c val |= frac << shift; val 106 drivers/clk/mxs/clk-ref.c writel_relaxed(val, ref->reg); val 25 drivers/clk/mxs/clk-ssp.c u32 val; val 44 drivers/clk/mxs/clk-ssp.c val = readl(ssp->base + HW_SSP_TIMING(ssp)); val 45 drivers/clk/mxs/clk-ssp.c val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); val 46 drivers/clk/mxs/clk-ssp.c val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); val 47 drivers/clk/mxs/clk-ssp.c val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); val 48 drivers/clk/mxs/clk-ssp.c writel(val, ssp->base + HW_SSP_TIMING(ssp)); val 140 drivers/clk/nxp/clk-lpc18xx-ccu.c u32 val; val 146 drivers/clk/nxp/clk-lpc18xx-ccu.c val = readl(gate->reg); val 147 drivers/clk/nxp/clk-lpc18xx-ccu.c if (val & LPC18XX_CCU_DIVSTAT) val 148 drivers/clk/nxp/clk-lpc18xx-ccu.c val |= LPC18XX_CCU_DIV; val 151 drivers/clk/nxp/clk-lpc18xx-ccu.c val |= LPC18XX_CCU_RUN; val 158 drivers/clk/nxp/clk-lpc18xx-ccu.c val |= LPC18XX_CCU_AUTO; val 159 drivers/clk/nxp/clk-lpc18xx-ccu.c writel(val, gate->reg); val 161 drivers/clk/nxp/clk-lpc18xx-ccu.c val &= ~LPC18XX_CCU_RUN; val 164 drivers/clk/nxp/clk-lpc18xx-ccu.c writel(val, gate->reg); val 383 drivers/clk/nxp/clk-lpc32xx.c static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val) val 385 drivers/clk/nxp/clk-lpc32xx.c writel(val, usb_clk_vbase + LPC32XX_USB_CLK_CTRL); val 391 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 393 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 395 drivers/clk/nxp/clk-lpc32xx.c if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) val 413 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 415 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 417 drivers/clk/nxp/clk-lpc32xx.c return ((val & clk->enable_mask) == clk->enable); val 429 drivers/clk/nxp/clk-lpc32xx.c u32 val, count; val 434 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 435 drivers/clk/nxp/clk-lpc32xx.c if (val & PLL_CTRL_LOCK) val 439 drivers/clk/nxp/clk-lpc32xx.c if (val & PLL_CTRL_LOCK) val 455 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 457 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 459 drivers/clk/nxp/clk-lpc32xx.c val &= clk->enable | PLL_CTRL_LOCK; val 460 drivers/clk/nxp/clk-lpc32xx.c if (val == (clk->enable | PLL_CTRL_LOCK)) val 478 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 480 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 481 drivers/clk/nxp/clk-lpc32xx.c is_direct = val & PLL_CTRL_DIRECT; val 482 drivers/clk/nxp/clk-lpc32xx.c is_bypass = val & PLL_CTRL_BYPASS; val 483 drivers/clk/nxp/clk-lpc32xx.c is_feedback = val & PLL_CTRL_FEEDBACK; val 485 drivers/clk/nxp/clk-lpc32xx.c clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1; val 486 drivers/clk/nxp/clk-lpc32xx.c clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1; val 487 drivers/clk/nxp/clk-lpc32xx.c clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1; val 518 drivers/clk/nxp/clk-lpc32xx.c parent_rate, val, is_direct, is_bypass, is_feedback, val 536 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 542 drivers/clk/nxp/clk-lpc32xx.c val = PLL_CTRL_DIRECT; val 543 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->m_div - 1) << 1; val 544 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->n_div - 1) << 9; val 548 drivers/clk/nxp/clk-lpc32xx.c val = PLL_CTRL_BYPASS; val 549 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->p_div - 1) << 11; val 553 drivers/clk/nxp/clk-lpc32xx.c val = PLL_CTRL_DIRECT | PLL_CTRL_BYPASS; val 557 drivers/clk/nxp/clk-lpc32xx.c val = PLL_CTRL_FEEDBACK; val 558 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->m_div - 1) << 1; val 559 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->n_div - 1) << 9; val 560 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->p_div - 1) << 11; val 564 drivers/clk/nxp/clk-lpc32xx.c val = 0x0; val 565 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->m_div - 1) << 1; val 566 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->n_div - 1) << 9; val 567 drivers/clk/nxp/clk-lpc32xx.c val |= (clk->p_div - 1) << 11; val 579 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val); val 716 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 718 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 719 drivers/clk/nxp/clk-lpc32xx.c val &= clk->enable_mask | clk->busy_mask; val 721 drivers/clk/nxp/clk-lpc32xx.c return (val == (BIT(7) | BIT(0)) || val 722 drivers/clk/nxp/clk-lpc32xx.c val == (BIT(8) | BIT(1))); val 728 drivers/clk/nxp/clk-lpc32xx.c u32 val, hclk_div; val 730 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 731 drivers/clk/nxp/clk-lpc32xx.c hclk_div = val & clk->busy_mask; val 749 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 754 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 755 drivers/clk/nxp/clk-lpc32xx.c val &= clk->enable_mask; val 757 drivers/clk/nxp/clk-lpc32xx.c return parent_rate / (val >> 7); val 771 drivers/clk/nxp/clk-lpc32xx.c u32 val, x, y; val 773 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 774 drivers/clk/nxp/clk-lpc32xx.c x = (val & 0xFF00) >> 8; val 775 drivers/clk/nxp/clk-lpc32xx.c y = val & 0xFF; val 788 drivers/clk/nxp/clk-lpc32xx.c { .val = 0, .div = 1 }, val 789 drivers/clk/nxp/clk-lpc32xx.c { .val = 1, .div = 2 }, val 790 drivers/clk/nxp/clk-lpc32xx.c { .val = 2, .div = 4 }, val 800 drivers/clk/nxp/clk-lpc32xx.c u32 val, ctrl_val, count; val 810 drivers/clk/nxp/clk-lpc32xx.c val = lpc32xx_usb_clk_read(clk); val 811 drivers/clk/nxp/clk-lpc32xx.c if (clk->busy && (val & clk->busy) == clk->busy) { val 818 drivers/clk/nxp/clk-lpc32xx.c val |= clk->enable; val 819 drivers/clk/nxp/clk-lpc32xx.c lpc32xx_usb_clk_write(clk, val); val 822 drivers/clk/nxp/clk-lpc32xx.c val = lpc32xx_usb_clk_read(clk); val 823 drivers/clk/nxp/clk-lpc32xx.c if ((val & clk->enable) == clk->enable) val 827 drivers/clk/nxp/clk-lpc32xx.c if ((val & clk->enable) == clk->enable) val 839 drivers/clk/nxp/clk-lpc32xx.c u32 val = lpc32xx_usb_clk_read(clk); val 841 drivers/clk/nxp/clk-lpc32xx.c val &= ~clk->enable; val 842 drivers/clk/nxp/clk-lpc32xx.c lpc32xx_usb_clk_write(clk, val); val 852 drivers/clk/nxp/clk-lpc32xx.c u32 ctrl_val, val; val 860 drivers/clk/nxp/clk-lpc32xx.c val = lpc32xx_usb_clk_read(clk); val 862 drivers/clk/nxp/clk-lpc32xx.c return ((val & clk->enable) == clk->enable); val 888 drivers/clk/nxp/clk-lpc32xx.c u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask); val 890 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, clk->reg, mask, val); val 897 drivers/clk/nxp/clk-lpc32xx.c u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0); val 899 drivers/clk/nxp/clk-lpc32xx.c regmap_update_bits(clk_regmap, clk->reg, mask, val); val 905 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 908 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); val 909 drivers/clk/nxp/clk-lpc32xx.c is_set = val & BIT(clk->bit_idx); val 923 drivers/clk/nxp/clk-lpc32xx.c unsigned int val) val 928 drivers/clk/nxp/clk-lpc32xx.c if (clkt->val == val) val 934 drivers/clk/nxp/clk-lpc32xx.c unsigned int val, unsigned long flags, u8 width) val 937 drivers/clk/nxp/clk-lpc32xx.c return val; val 939 drivers/clk/nxp/clk-lpc32xx.c return _get_table_div(table, val); val 940 drivers/clk/nxp/clk-lpc32xx.c return val + 1; val 947 drivers/clk/nxp/clk-lpc32xx.c unsigned int val; val 949 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, divider->reg, &val); val 951 drivers/clk/nxp/clk-lpc32xx.c val >>= divider->shift; val 952 drivers/clk/nxp/clk-lpc32xx.c val &= div_mask(divider->width); val 954 drivers/clk/nxp/clk-lpc32xx.c return divider_recalc_rate(hw, parent_rate, val, divider->table, val 1002 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 1004 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, mux->reg, &val); val 1005 drivers/clk/nxp/clk-lpc32xx.c val >>= mux->shift; val 1006 drivers/clk/nxp/clk-lpc32xx.c val &= mux->mask; val 1012 drivers/clk/nxp/clk-lpc32xx.c if (mux->table[i] == val) val 1017 drivers/clk/nxp/clk-lpc32xx.c if (val >= num_parents) val 1020 drivers/clk/nxp/clk-lpc32xx.c return val; val 1477 drivers/clk/nxp/clk-lpc32xx.c u32 val; val 1479 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, reg, &val); val 1481 drivers/clk/nxp/clk-lpc32xx.c if (!(val & div_mask)) { val 1482 drivers/clk/nxp/clk-lpc32xx.c val &= ~gate; val 1483 drivers/clk/nxp/clk-lpc32xx.c val |= BIT(__ffs(div_mask)); val 1486 drivers/clk/nxp/clk-lpc32xx.c regmap_update_bits(clk_regmap, reg, gate | div_mask, val); val 83 drivers/clk/pistachio/clk-pll.c static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) val 85 drivers/clk/pistachio/clk-pll.c writel(val, pll->base + reg); val 108 drivers/clk/pistachio/clk-pll.c u32 val; val 110 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD; val 111 drivers/clk/pistachio/clk-pll.c return val ? PLL_MODE_INT : PLL_MODE_FRAC; val 117 drivers/clk/pistachio/clk-pll.c u32 val; val 119 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL3); val 121 drivers/clk/pistachio/clk-pll.c val |= PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD; val 123 drivers/clk/pistachio/clk-pll.c val &= ~(PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD); val 125 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL3); val 160 drivers/clk/pistachio/clk-pll.c u32 val; val 162 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL3); val 163 drivers/clk/pistachio/clk-pll.c val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD | val 165 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL3); val 167 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL4); val 168 drivers/clk/pistachio/clk-pll.c val &= ~PLL_FRAC_CTRL4_BYPASS; val 169 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL4); val 179 drivers/clk/pistachio/clk-pll.c u32 val; val 181 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL3); val 182 drivers/clk/pistachio/clk-pll.c val |= PLL_FRAC_CTRL3_PD; val 183 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL3); val 199 drivers/clk/pistachio/clk-pll.c u64 val, vco, old_postdiv1, old_postdiv2; val 218 drivers/clk/pistachio/clk-pll.c val = div64_u64(params->fref, params->refdiv); val 219 drivers/clk/pistachio/clk-pll.c if (val < MIN_PFD) val 221 drivers/clk/pistachio/clk-pll.c name, val, MIN_PFD); val 222 drivers/clk/pistachio/clk-pll.c if (val > vco / 16) val 224 drivers/clk/pistachio/clk-pll.c name, val, vco / 16); val 226 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); val 227 drivers/clk/pistachio/clk-pll.c val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) | val 229 drivers/clk/pistachio/clk-pll.c val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | val 231 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL1); val 233 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL2); val 235 drivers/clk/pistachio/clk-pll.c old_postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) & val 237 drivers/clk/pistachio/clk-pll.c old_postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & val 247 drivers/clk/pistachio/clk-pll.c val &= ~((PLL_FRAC_CTRL2_FRAC_MASK << PLL_FRAC_CTRL2_FRAC_SHIFT) | val 252 drivers/clk/pistachio/clk-pll.c val |= (params->frac << PLL_FRAC_CTRL2_FRAC_SHIFT) | val 255 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL2); val 273 drivers/clk/pistachio/clk-pll.c u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; val 275 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); val 276 drivers/clk/pistachio/clk-pll.c prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; val 277 drivers/clk/pistachio/clk-pll.c fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; val 279 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL2); val 280 drivers/clk/pistachio/clk-pll.c postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) & val 282 drivers/clk/pistachio/clk-pll.c postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & val 284 drivers/clk/pistachio/clk-pll.c frac = (val >> PLL_FRAC_CTRL2_FRAC_SHIFT) & PLL_FRAC_CTRL2_FRAC_MASK; val 317 drivers/clk/pistachio/clk-pll.c u32 val; val 319 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); val 320 drivers/clk/pistachio/clk-pll.c val &= ~(PLL_INT_CTRL1_PD | val 322 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL1); val 324 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL2); val 325 drivers/clk/pistachio/clk-pll.c val &= ~PLL_INT_CTRL2_BYPASS; val 326 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL2); val 336 drivers/clk/pistachio/clk-pll.c u32 val; val 338 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); val 339 drivers/clk/pistachio/clk-pll.c val |= PLL_INT_CTRL1_PD; val 340 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL1); val 356 drivers/clk/pistachio/clk-pll.c u32 val, vco, old_postdiv1, old_postdiv2; val 371 drivers/clk/pistachio/clk-pll.c val = div_u64(params->fref, params->refdiv); val 372 drivers/clk/pistachio/clk-pll.c if (val < MIN_PFD) val 374 drivers/clk/pistachio/clk-pll.c name, val, MIN_PFD); val 375 drivers/clk/pistachio/clk-pll.c if (val > vco / 16) val 377 drivers/clk/pistachio/clk-pll.c name, val, vco / 16); val 379 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); val 381 drivers/clk/pistachio/clk-pll.c old_postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) & val 383 drivers/clk/pistachio/clk-pll.c old_postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & val 393 drivers/clk/pistachio/clk-pll.c val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) | val 397 drivers/clk/pistachio/clk-pll.c val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | val 401 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL1); val 413 drivers/clk/pistachio/clk-pll.c u32 val, prediv, fbdiv, postdiv1, postdiv2; val 416 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); val 417 drivers/clk/pistachio/clk-pll.c prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; val 418 drivers/clk/pistachio/clk-pll.c fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; val 419 drivers/clk/pistachio/clk-pll.c postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) & val 421 drivers/clk/pistachio/clk-pll.c postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & val 162 drivers/clk/qcom/clk-alpha-pll.c u32 val; val 167 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 172 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 175 drivers/clk/qcom/clk-alpha-pll.c if (inverse && !(val & mask)) val 177 drivers/clk/qcom/clk-alpha-pll.c else if ((val & mask) == mask) val 211 drivers/clk/qcom/clk-alpha-pll.c u32 val, mask; val 224 drivers/clk/qcom/clk-alpha-pll.c val = config->main_output_mask; val 225 drivers/clk/qcom/clk-alpha-pll.c val |= config->aux_output_mask; val 226 drivers/clk/qcom/clk-alpha-pll.c val |= config->aux2_output_mask; val 227 drivers/clk/qcom/clk-alpha-pll.c val |= config->early_output_mask; val 228 drivers/clk/qcom/clk-alpha-pll.c val |= config->pre_div_val; val 229 drivers/clk/qcom/clk-alpha-pll.c val |= config->post_div_val; val 230 drivers/clk/qcom/clk-alpha-pll.c val |= config->vco_val; val 231 drivers/clk/qcom/clk-alpha-pll.c val |= config->alpha_en_mask; val 232 drivers/clk/qcom/clk-alpha-pll.c val |= config->alpha_mode_mask; val 242 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); val 253 drivers/clk/qcom/clk-alpha-pll.c u32 val; val 255 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 259 drivers/clk/qcom/clk-alpha-pll.c val |= PLL_FSM_ENA; val 262 drivers/clk/qcom/clk-alpha-pll.c val &= ~PLL_OFFLINE_REQ; val 264 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); val 278 drivers/clk/qcom/clk-alpha-pll.c u32 val; val 280 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 308 drivers/clk/qcom/clk-alpha-pll.c u32 val; val 310 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 314 drivers/clk/qcom/clk-alpha-pll.c return !!(val & mask); val 331 drivers/clk/qcom/clk-alpha-pll.c u32 val, mask; val 334 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 339 drivers/clk/qcom/clk-alpha-pll.c if (val & PLL_VOTE_FSM_ENA) { val 347 drivers/clk/qcom/clk-alpha-pll.c if ((val & mask) == mask) val 383 drivers/clk/qcom/clk-alpha-pll.c u32 val, mask; val 385 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 390 drivers/clk/qcom/clk-alpha-pll.c if (val & PLL_VOTE_FSM_ENA) { val 564 drivers/clk/qcom/clk-alpha-pll.c vco->val << PLL_VCO_SHIFT); val 782 drivers/clk/qcom/clk-alpha-pll.c u32 val; val 785 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &val); val 790 drivers/clk/qcom/clk-alpha-pll.c if (val & PLL_VOTE_FSM_ENA) { val 819 drivers/clk/qcom/clk-alpha-pll.c u32 val; val 822 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &val); val 827 drivers/clk/qcom/clk-alpha-pll.c if (val & PLL_VOTE_FSM_ENA) { val 1015 drivers/clk/qcom/clk-alpha-pll.c u32 val, mask; val 1029 drivers/clk/qcom/clk-alpha-pll.c val = config->post_div_val; val 1030 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); val 1044 drivers/clk/qcom/clk-alpha-pll.c u32 val, opmode_val; val 1047 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &val); val 1052 drivers/clk/qcom/clk-alpha-pll.c if (val & PLL_VOTE_FSM_ENA) { val 1064 drivers/clk/qcom/clk-alpha-pll.c if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL)) val 1101 drivers/clk/qcom/clk-alpha-pll.c u32 val; val 1104 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &val); val 1109 drivers/clk/qcom/clk-alpha-pll.c if (val & PLL_FSM_ENA) { val 1144 drivers/clk/qcom/clk-alpha-pll.c u32 val, l, alpha_width = pll_alpha_width(pll); val 1149 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 1193 drivers/clk/qcom/clk-alpha-pll.c u32 i, div = 1, val; val 1196 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); val 1200 drivers/clk/qcom/clk-alpha-pll.c val >>= pll->post_div_shift; val 1201 drivers/clk/qcom/clk-alpha-pll.c val &= BIT(pll->width) - 1; val 1204 drivers/clk/qcom/clk-alpha-pll.c if (pll->post_div_table[i].val == val) { val 1218 drivers/clk/qcom/clk-alpha-pll.c u32 i, div = 1, val; val 1220 drivers/clk/qcom/clk-alpha-pll.c regmap_read(regmap, PLL_USER_CTL(pll), &val); val 1222 drivers/clk/qcom/clk-alpha-pll.c val >>= pll->post_div_shift; val 1223 drivers/clk/qcom/clk-alpha-pll.c val &= PLL_POST_DIV_MASK(pll); val 1226 drivers/clk/qcom/clk-alpha-pll.c if (pll->post_div_table[i].val == val) { val 1251 drivers/clk/qcom/clk-alpha-pll.c int i, val = 0, div; val 1256 drivers/clk/qcom/clk-alpha-pll.c val = pll->post_div_table[i].val; val 1263 drivers/clk/qcom/clk-alpha-pll.c val << PLL_POST_DIV_SHIFT); val 1286 drivers/clk/qcom/clk-alpha-pll.c int i, val = 0, div, ret; val 1292 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); val 1296 drivers/clk/qcom/clk-alpha-pll.c if (val & PLL_VOTE_FSM_ENA) val 1302 drivers/clk/qcom/clk-alpha-pll.c val = pll->post_div_table[i].val; val 1309 drivers/clk/qcom/clk-alpha-pll.c val << pll->post_div_shift); val 45 drivers/clk/qcom/clk-alpha-pll.h u32 val; val 18 drivers/clk/qcom/clk-branch.c u32 val; val 23 drivers/clk/qcom/clk-branch.c regmap_read(br->clkr.regmap, br->hwcg_reg, &val); val 25 drivers/clk/qcom/clk-branch.c return !!(val & BIT(br->hwcg_bit)); val 31 drivers/clk/qcom/clk-branch.c u32 val; val 33 drivers/clk/qcom/clk-branch.c regmap_read(br->clkr.regmap, br->halt_reg, &val); val 35 drivers/clk/qcom/clk-branch.c val &= BIT(br->halt_bit); val 37 drivers/clk/qcom/clk-branch.c val = !val; val 39 drivers/clk/qcom/clk-branch.c return !!val == !enabling; val 49 drivers/clk/qcom/clk-branch.c u32 val; val 55 drivers/clk/qcom/clk-branch.c regmap_read(br->clkr.regmap, br->halt_reg, &val); val 58 drivers/clk/qcom/clk-branch.c val &= mask; val 59 drivers/clk/qcom/clk-branch.c return (val & BRANCH_CLK_OFF) == 0 || val 60 drivers/clk/qcom/clk-branch.c val == BRANCH_NOC_FSM_STATUS_ON; val 62 drivers/clk/qcom/clk-branch.c return val & BRANCH_CLK_OFF; val 58 drivers/clk/qcom/clk-hfpll.c u32 val; val 77 drivers/clk/qcom/clk-hfpll.c regmap_read(regmap, hd->status_reg, &val); val 78 drivers/clk/qcom/clk-hfpll.c } while (!(val & BIT(hd->lock_bit))); val 155 drivers/clk/qcom/clk-hfpll.c u32 l_val, val; val 168 drivers/clk/qcom/clk-hfpll.c regmap_read(regmap, hd->user_reg, &val); val 170 drivers/clk/qcom/clk-hfpll.c val &= ~hd->user_vco_mask; val 172 drivers/clk/qcom/clk-hfpll.c val |= hd->user_vco_mask; val 173 drivers/clk/qcom/clk-hfpll.c regmap_write(regmap, hd->user_reg, val); val 91 drivers/clk/qcom/clk-krait.c u32 val; val 98 drivers/clk/qcom/clk-krait.c val = krait_get_l2_indirect_reg(d->offset); val 99 drivers/clk/qcom/clk-krait.c val &= ~mask; val 100 drivers/clk/qcom/clk-krait.c krait_set_l2_indirect_reg(d->offset, val); val 28 drivers/clk/qcom/clk-pll.c u32 mask, val; val 31 drivers/clk/qcom/clk-pll.c ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); val 36 drivers/clk/qcom/clk-pll.c if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA) val 69 drivers/clk/qcom/clk-pll.c u32 val; val 71 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->mode_reg, &val); val 73 drivers/clk/qcom/clk-pll.c if (val & PLL_VOTE_FSM_ENA) val 181 drivers/clk/qcom/clk-pll.c u32 val; val 188 drivers/clk/qcom/clk-pll.c ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val); val 191 drivers/clk/qcom/clk-pll.c if (val & BIT(pll->status_bit)) val 221 drivers/clk/qcom/clk-pll.c u32 val; val 228 drivers/clk/qcom/clk-pll.c val = config->vco_val; val 229 drivers/clk/qcom/clk-pll.c val |= config->pre_div_val; val 230 drivers/clk/qcom/clk-pll.c val |= config->post_div_val; val 231 drivers/clk/qcom/clk-pll.c val |= config->mn_ena_mask; val 232 drivers/clk/qcom/clk-pll.c val |= config->main_output_mask; val 233 drivers/clk/qcom/clk-pll.c val |= config->aux_output_mask; val 242 drivers/clk/qcom/clk-pll.c regmap_update_bits(regmap, pll->config_reg, mask, val); val 156 drivers/clk/qcom/clk-rcg.c static u32 reg_to_mnctr_mode(struct mn *mn, u32 val) val 158 drivers/clk/qcom/clk-rcg.c val >>= mn->mnctr_mode_shift; val 159 drivers/clk/qcom/clk-rcg.c val &= MNCTR_MODE_MASK; val 160 drivers/clk/qcom/clk-rcg.c return val; val 182 drivers/clk/qcom/clk-rcg.c static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val) val 188 drivers/clk/qcom/clk-rcg.c val &= ~mask; val 191 drivers/clk/qcom/clk-rcg.c val |= BIT(mn->mnctr_en_bit); val 192 drivers/clk/qcom/clk-rcg.c val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift; val 195 drivers/clk/qcom/clk-rcg.c return val; val 958 drivers/clk/qcom/clk-rcg2.c u32 val, mask, cfg, mode, src; val 985 drivers/clk/qcom/clk-rcg2.c &val); val 986 drivers/clk/qcom/clk-rcg2.c val &= mask; val 987 drivers/clk/qcom/clk-rcg2.c f->m = val; val 990 drivers/clk/qcom/clk-rcg2.c &val); val 991 drivers/clk/qcom/clk-rcg2.c val = ~val; val 992 drivers/clk/qcom/clk-rcg2.c val &= mask; val 993 drivers/clk/qcom/clk-rcg2.c val += f->m; val 994 drivers/clk/qcom/clk-rcg2.c f->n = val; val 1094 drivers/clk/qcom/clk-rcg2.c u32 val; val 1097 drivers/clk/qcom/clk-rcg2.c ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val); val 1101 drivers/clk/qcom/clk-rcg2.c if (!(val & SE_CMD_DFS_EN)) val 23 drivers/clk/qcom/clk-regmap-divider.c u32 val; val 25 drivers/clk/qcom/clk-regmap-divider.c regmap_read(clkr->regmap, divider->reg, &val); val 26 drivers/clk/qcom/clk-regmap-divider.c val >>= divider->shift; val 27 drivers/clk/qcom/clk-regmap-divider.c val &= BIT(divider->width) - 1; val 30 drivers/clk/qcom/clk-regmap-divider.c CLK_DIVIDER_ROUND_CLOSEST, val); val 26 drivers/clk/qcom/clk-regmap-mux-div.c u32 val, mask; val 29 drivers/clk/qcom/clk-regmap-mux-div.c val = (div << md->hid_shift) | (src << md->src_shift); val 34 drivers/clk/qcom/clk-regmap-mux-div.c mask, val); val 46 drivers/clk/qcom/clk-regmap-mux-div.c &val); val 49 drivers/clk/qcom/clk-regmap-mux-div.c if (!(val & CMD_RCGR_UPDATE)) val 62 drivers/clk/qcom/clk-regmap-mux-div.c u32 val, d, s; val 65 drivers/clk/qcom/clk-regmap-mux-div.c regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val); val 67 drivers/clk/qcom/clk-regmap-mux-div.c if (val & CMD_RCGR_DIRTY_CFG) { val 72 drivers/clk/qcom/clk-regmap-mux-div.c regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val); val 73 drivers/clk/qcom/clk-regmap-mux-div.c s = (val >> md->src_shift); val 77 drivers/clk/qcom/clk-regmap-mux-div.c d = (val >> md->hid_shift); val 23 drivers/clk/qcom/clk-regmap-mux.c unsigned int val; val 25 drivers/clk/qcom/clk-regmap-mux.c regmap_read(clkr->regmap, mux->reg, &val); val 27 drivers/clk/qcom/clk-regmap-mux.c val >>= mux->shift; val 28 drivers/clk/qcom/clk-regmap-mux.c val &= mask; val 31 drivers/clk/qcom/clk-regmap-mux.c return qcom_find_src_index(hw, mux->parent_map, val); val 33 drivers/clk/qcom/clk-regmap-mux.c return val; val 41 drivers/clk/qcom/clk-regmap-mux.c unsigned int val; val 46 drivers/clk/qcom/clk-regmap-mux.c val = index; val 47 drivers/clk/qcom/clk-regmap-mux.c val <<= mux->shift; val 49 drivers/clk/qcom/clk-regmap-mux.c return regmap_update_bits(clkr->regmap, mux->reg, mask, val); val 25 drivers/clk/qcom/clk-regmap.c unsigned int val; val 28 drivers/clk/qcom/clk-regmap.c ret = regmap_read(rclk->regmap, rclk->enable_reg, &val); val 33 drivers/clk/qcom/clk-regmap.c return (val & rclk->enable_mask) == 0; val 35 drivers/clk/qcom/clk-regmap.c return (val & rclk->enable_mask) != 0; val 51 drivers/clk/qcom/clk-regmap.c unsigned int val; val 54 drivers/clk/qcom/clk-regmap.c val = 0; val 56 drivers/clk/qcom/clk-regmap.c val = rclk->enable_mask; val 59 drivers/clk/qcom/clk-regmap.c rclk->enable_mask, val); val 75 drivers/clk/qcom/clk-regmap.c unsigned int val; val 78 drivers/clk/qcom/clk-regmap.c val = rclk->enable_mask; val 80 drivers/clk/qcom/clk-regmap.c val = 0; val 83 drivers/clk/qcom/clk-regmap.c val); val 53 drivers/clk/qcom/clk-spmi-pmic-div.c unsigned int val = 0; val 55 drivers/clk/qcom/clk-spmi-pmic-div.c regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); val 57 drivers/clk/qcom/clk-spmi-pmic-div.c return val & REG_EN_MASK; val 91 drivers/clk/qcom/common.c u32 val; val 98 drivers/clk/qcom/common.c val = bias_count << PLL_BIAS_COUNT_SHIFT | val 102 drivers/clk/qcom/common.c regmap_update_bits(map, reg, mask, val); val 1396 drivers/clk/qcom/gcc-ipq4019.c if (clkt->val == cdiv) val 54 drivers/clk/qcom/gdsc.c u32 val; val 64 drivers/clk/qcom/gdsc.c ret = regmap_read(sc->regmap, reg, &val); val 71 drivers/clk/qcom/gdsc.c return !!(val & GDSC_POWER_UP_COMPLETE); val 73 drivers/clk/qcom/gdsc.c return !!(val & GDSC_POWER_DOWN_COMPLETE); val 79 drivers/clk/qcom/gdsc.c return !!(val & PWR_ON_MASK); val 81 drivers/clk/qcom/gdsc.c return !(val & PWR_ON_MASK); val 89 drivers/clk/qcom/gdsc.c u32 val = en ? HW_CONTROL_MASK : 0; val 91 drivers/clk/qcom/gdsc.c return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); val 113 drivers/clk/qcom/gdsc.c u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK; val 115 drivers/clk/qcom/gdsc.c ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val); val 301 drivers/clk/qcom/gdsc.c u32 mask, val; val 311 drivers/clk/qcom/gdsc.c val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; val 312 drivers/clk/qcom/gdsc.c ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); val 430 drivers/clk/qcom/lcc-ipq806x.c u32 val; val 438 drivers/clk/qcom/lcc-ipq806x.c regmap_read(regmap, 0x0, &val); val 439 drivers/clk/qcom/lcc-ipq806x.c if (!val) val 537 drivers/clk/qcom/lcc-mdm9615.c u32 val; val 545 drivers/clk/qcom/lcc-mdm9615.c regmap_read(regmap, 0x4, &val); val 546 drivers/clk/qcom/lcc-mdm9615.c if (val == 0x12) { val 536 drivers/clk/qcom/lcc-msm8960.c u32 val; val 544 drivers/clk/qcom/lcc-msm8960.c regmap_read(regmap, 0x4, &val); val 545 drivers/clk/qcom/lcc-msm8960.c if (val == 0x12) { val 530 drivers/clk/qcom/mmcc-msm8960.c u32 val; val 550 drivers/clk/qcom/mmcc-msm8960.c val = rdi->s2_mask; val 552 drivers/clk/qcom/mmcc-msm8960.c val = 0; val 553 drivers/clk/qcom/mmcc-msm8960.c regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val); val 561 drivers/clk/qcom/mmcc-msm8960.c val = rdi->s_mask; val 563 drivers/clk/qcom/mmcc-msm8960.c val = 0; val 564 drivers/clk/qcom/mmcc-msm8960.c regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val); val 582 drivers/clk/qcom/mmcc-msm8960.c u32 val; val 586 drivers/clk/qcom/mmcc-msm8960.c regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val); val 587 drivers/clk/qcom/mmcc-msm8960.c if (val & rdi->s2_mask) val 590 drivers/clk/qcom/mmcc-msm8960.c regmap_read(rdi->clkr.regmap, rdi->s_reg, &val); val 591 drivers/clk/qcom/mmcc-msm8960.c if (val & rdi->s_mask) val 51 drivers/clk/renesas/clk-div6.c u32 val; val 53 drivers/clk/renesas/clk-div6.c val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) val 55 drivers/clk/renesas/clk-div6.c writel(val, clock->reg); val 63 drivers/clk/renesas/clk-div6.c u32 val; val 65 drivers/clk/renesas/clk-div6.c val = readl(clock->reg); val 66 drivers/clk/renesas/clk-div6.c val |= CPG_DIV6_CKSTP; val 73 drivers/clk/renesas/clk-div6.c if (!(val & CPG_DIV6_DIV_MASK)) val 74 drivers/clk/renesas/clk-div6.c val |= CPG_DIV6_DIV_MASK; val 75 drivers/clk/renesas/clk-div6.c writel(val, clock->reg); val 118 drivers/clk/renesas/clk-div6.c u32 val; val 122 drivers/clk/renesas/clk-div6.c val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK; val 124 drivers/clk/renesas/clk-div6.c if (!(val & CPG_DIV6_CKSTP)) val 125 drivers/clk/renesas/clk-div6.c writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); val 69 drivers/clk/renesas/clk-mstp.c static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val, val 72 drivers/clk/renesas/clk-mstp.c group->width_8bit ? writeb(val, reg) : writel(val, reg); val 61 drivers/clk/renesas/clk-rcar-gen2.c unsigned int val; val 63 drivers/clk/renesas/clk-rcar-gen2.c val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; val 64 drivers/clk/renesas/clk-rcar-gen2.c mult = 32 - val; val 89 drivers/clk/renesas/clk-rcar-gen2.c u32 val, kick; val 98 drivers/clk/renesas/clk-rcar-gen2.c val = readl(zclk->reg); val 99 drivers/clk/renesas/clk-rcar-gen2.c val &= ~CPG_FRQCRC_ZFC_MASK; val 100 drivers/clk/renesas/clk-rcar-gen2.c val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; val 101 drivers/clk/renesas/clk-rcar-gen2.c writel(val, zclk->reg); val 54 drivers/clk/renesas/clk-rz.c u32 val; val 76 drivers/clk/renesas/clk-rz.c val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3; val 78 drivers/clk/renesas/clk-rz.c val = readl(cpg->reg + CPG_FRQCR2) & 3; val 82 drivers/clk/renesas/clk-rz.c mult = frqcr_tab[val]; val 324 drivers/clk/renesas/r9a06g032-clocks.c u32 val = readl(reg); val 326 drivers/clk/renesas/r9a06g032-clocks.c val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f)); val 327 drivers/clk/renesas/r9a06g032-clocks.c writel(val, reg); val 335 drivers/clk/renesas/r9a06g032-clocks.c u32 val = readl(reg); val 337 drivers/clk/renesas/r9a06g032-clocks.c return !!(val & (1U << (one & 0x1f))); val 58 drivers/clk/renesas/rcar-gen2-cpg.c unsigned int val; val 60 drivers/clk/renesas/rcar-gen2-cpg.c val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; val 61 drivers/clk/renesas/rcar-gen2-cpg.c mult = 32 - val; val 86 drivers/clk/renesas/rcar-gen2-cpg.c u32 val, kick; val 95 drivers/clk/renesas/rcar-gen2-cpg.c val = readl(zclk->reg); val 96 drivers/clk/renesas/rcar-gen2-cpg.c val &= ~CPG_FRQCRC_ZFC_MASK; val 97 drivers/clk/renesas/rcar-gen2-cpg.c val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; val 98 drivers/clk/renesas/rcar-gen2-cpg.c writel(val, zclk->reg); val 39 drivers/clk/renesas/rcar-gen3-cpg.c u32 val; val 42 drivers/clk/renesas/rcar-gen3-cpg.c val = readl(reg); val 43 drivers/clk/renesas/rcar-gen3-cpg.c val &= ~clear; val 44 drivers/clk/renesas/rcar-gen3-cpg.c val |= set; val 45 drivers/clk/renesas/rcar-gen3-cpg.c writel(val, reg); val 108 drivers/clk/renesas/rcar-gen3-cpg.c u32 val; val 110 drivers/clk/renesas/rcar-gen3-cpg.c val = readl(zclk->reg) & zclk->mask; val 111 drivers/clk/renesas/rcar-gen3-cpg.c mult = 32 - (val >> __ffs(zclk->mask)); val 223 drivers/clk/renesas/rcar-gen3-cpg.c .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ val 231 drivers/clk/renesas/rcar-gen3-cpg.c u32 val; val 283 drivers/clk/renesas/rcar-gen3-cpg.c clock->div_table[clock->cur_div_idx].val & val 358 drivers/clk/renesas/rcar-gen3-cpg.c clock->div_table[i].val & val 386 drivers/clk/renesas/rcar-gen3-cpg.c u32 val; val 408 drivers/clk/renesas/rcar-gen3-cpg.c val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK; val 409 drivers/clk/renesas/rcar-gen3-cpg.c val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK); val 410 drivers/clk/renesas/rcar-gen3-cpg.c writel(val, clock->csn.reg); val 39 drivers/clk/renesas/rcar-usb2-clock-sel.c u16 val = readw(priv->base + USB20_CLKSET0); val 42 drivers/clk/renesas/rcar-usb2-clock-sel.c priv->extal, priv->xtal, val); val 44 drivers/clk/renesas/rcar-usb2-clock-sel.c if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) val 142 drivers/clk/renesas/renesas-cpg-mssr.c u32 val; val 803 drivers/clk/renesas/renesas-cpg-mssr.c priv->smstpcr_saved[reg].val = val 837 drivers/clk/renesas/renesas-cpg-mssr.c newval |= priv->smstpcr_saved[reg].val & mask; val 851 drivers/clk/renesas/renesas-cpg-mssr.c mask &= ~priv->smstpcr_saved[reg].val; val 115 drivers/clk/rockchip/clk-cpu.c __func__, clksel->reg, clksel->val); val 116 drivers/clk/rockchip/clk-cpu.c writel(clksel->val, cpuclk->reg_base + clksel->reg); val 74 drivers/clk/rockchip/clk-ddr.c u32 val; val 76 drivers/clk/rockchip/clk-ddr.c val = readl(ddrclk->reg_base + val 78 drivers/clk/rockchip/clk-ddr.c val &= GENMASK(ddrclk->mux_width - 1, 0); val 80 drivers/clk/rockchip/clk-ddr.c return val; val 26 drivers/clk/rockchip/clk-half-divider.c unsigned int val; val 28 drivers/clk/rockchip/clk-half-divider.c val = readl(divider->reg) >> divider->shift; val 29 drivers/clk/rockchip/clk-half-divider.c val &= div_mask(divider->width); val 30 drivers/clk/rockchip/clk-half-divider.c val = val * 2 + 3; val 32 drivers/clk/rockchip/clk-half-divider.c return DIV_ROUND_UP_ULL(((u64)parent_rate * 2), val); val 114 drivers/clk/rockchip/clk-half-divider.c u32 val; val 126 drivers/clk/rockchip/clk-half-divider.c val = div_mask(divider->width) << (divider->shift + 16); val 128 drivers/clk/rockchip/clk-half-divider.c val = readl(divider->reg); val 129 drivers/clk/rockchip/clk-half-divider.c val &= ~(div_mask(divider->width) << divider->shift); val 131 drivers/clk/rockchip/clk-half-divider.c val |= value << divider->shift; val 132 drivers/clk/rockchip/clk-half-divider.c writel(val, divider->reg); val 28 drivers/clk/rockchip/clk-inverter.c u32 val; val 30 drivers/clk/rockchip/clk-inverter.c val = readl(inv_clock->reg) >> inv_clock->shift; val 31 drivers/clk/rockchip/clk-inverter.c val &= INVERTER_MASK; val 32 drivers/clk/rockchip/clk-inverter.c return val ? 180 : 0; val 38 drivers/clk/rockchip/clk-inverter.c u32 val; val 41 drivers/clk/rockchip/clk-inverter.c val = !!degrees; val 49 drivers/clk/rockchip/clk-inverter.c writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), val 59 drivers/clk/rockchip/clk-inverter.c reg |= val; val 25 drivers/clk/rockchip/clk-muxgrf.c unsigned int val; val 27 drivers/clk/rockchip/clk-muxgrf.c regmap_read(mux->regmap, mux->reg, &val); val 29 drivers/clk/rockchip/clk-muxgrf.c val >>= mux->shift; val 30 drivers/clk/rockchip/clk-muxgrf.c val &= mask; val 32 drivers/clk/rockchip/clk-muxgrf.c return val; val 39 drivers/clk/rockchip/clk-muxgrf.c unsigned int val; val 41 drivers/clk/rockchip/clk-muxgrf.c val = index; val 42 drivers/clk/rockchip/clk-muxgrf.c val <<= mux->shift; val 45 drivers/clk/rockchip/clk-muxgrf.c return regmap_write(mux->regmap, mux->reg, val | (mask << 16)); val 47 drivers/clk/rockchip/clk-muxgrf.c return regmap_update_bits(mux->regmap, mux->reg, mask, val); val 88 drivers/clk/rockchip/clk-pll.c unsigned int val; val 92 drivers/clk/rockchip/clk-pll.c ret = regmap_read(grf, pll->lock_offset, &val); val 99 drivers/clk/rockchip/clk-pll.c if (val & BIT(pll->lock_shift)) val 81 drivers/clk/rockchip/clk-px30.c .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \ val 86 drivers/clk/rockchip/clk-rk3036.c .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \ val 83 drivers/clk/rockchip/clk-rk3128.c .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \ val 112 drivers/clk/rockchip/clk-rk3188.c .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \ val 118 drivers/clk/rockchip/clk-rk3188.c .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \ val 163 drivers/clk/rockchip/clk-rk3188.c .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\ val 242 drivers/clk/rockchip/clk-rk3188.c { .val = 0, .div = 2 }, val 243 drivers/clk/rockchip/clk-rk3188.c { .val = 1, .div = 4 }, val 244 drivers/clk/rockchip/clk-rk3188.c { .val = 2, .div = 8 }, val 245 drivers/clk/rockchip/clk-rk3188.c { .val = 3, .div = 16 }, val 537 drivers/clk/rockchip/clk-rk3188.c { .val = 0, .div = 1 }, val 538 drivers/clk/rockchip/clk-rk3188.c { .val = 1, .div = 2 }, val 539 drivers/clk/rockchip/clk-rk3188.c { .val = 2, .div = 3 }, val 540 drivers/clk/rockchip/clk-rk3188.c { .val = 3, .div = 4 }, val 541 drivers/clk/rockchip/clk-rk3188.c { .val = 4, .div = 8 }, val 658 drivers/clk/rockchip/clk-rk3188.c { .val = 0, .div = 1 }, val 659 drivers/clk/rockchip/clk-rk3188.c { .val = 1, .div = 2 }, val 660 drivers/clk/rockchip/clk-rk3188.c { .val = 2, .div = 3 }, val 661 drivers/clk/rockchip/clk-rk3188.c { .val = 3, .div = 4 }, val 662 drivers/clk/rockchip/clk-rk3188.c { .val = 4, .div = 8 }, val 84 drivers/clk/rockchip/clk-rk3228.c .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ val 133 drivers/clk/rockchip/clk-rk3288.c .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \ val 141 drivers/clk/rockchip/clk-rk3288.c .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \ val 233 drivers/clk/rockchip/clk-rk3288.c { .val = 0, .div = 1 }, val 234 drivers/clk/rockchip/clk-rk3288.c { .val = 1, .div = 2 }, val 235 drivers/clk/rockchip/clk-rk3288.c { .val = 3, .div = 4 }, val 77 drivers/clk/rockchip/clk-rk3308.c .val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \ val 96 drivers/clk/rockchip/clk-rk3328.c .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \ val 145 drivers/clk/rockchip/clk-rk3368.c { .val = 0, .div = 1 }, val 146 drivers/clk/rockchip/clk-rk3368.c { .val = 1, .div = 2 }, val 147 drivers/clk/rockchip/clk-rk3368.c { .val = 3, .div = 4 }, val 186 drivers/clk/rockchip/clk-rk3368.c .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \ val 192 drivers/clk/rockchip/clk-rk3368.c .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \ val 321 drivers/clk/rockchip/clk-rk3399.c .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \ val 327 drivers/clk/rockchip/clk-rk3399.c .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \ val 75 drivers/clk/rockchip/clk-rv1108.c .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\ val 25 drivers/clk/rockchip/clk.h #define HIWORD_UPDATE(val, mask, shift) \ val 26 drivers/clk/rockchip/clk.h ((val) << (shift) | (mask) << ((shift) + 16)) val 322 drivers/clk/rockchip/clk.h u32 val; val 63 drivers/clk/samsung/clk-s3c2410-dclk.c u32 val; val 65 drivers/clk/samsung/clk-s3c2410-dclk.c val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift; val 66 drivers/clk/samsung/clk-s3c2410-dclk.c val >>= clkout->shift; val 67 drivers/clk/samsung/clk-s3c2410-dclk.c val &= clkout->mask; val 69 drivers/clk/samsung/clk-s3c2410-dclk.c if (val >= num_parents) val 72 drivers/clk/samsung/clk-s3c2410-dclk.c return val; val 60 drivers/clk/samsung/clk-s3c2410.c { .val = 0, .div = 1 }, val 61 drivers/clk/samsung/clk-s3c2410.c { .val = 1, .div = 2 }, val 62 drivers/clk/samsung/clk-s3c2410.c { .val = 2, .div = 4 }, val 63 drivers/clk/samsung/clk-s3c2410.c { .val = 3, .div = 6 }, val 64 drivers/clk/samsung/clk-s3c2410.c { .val = 4, .div = 8 }, val 65 drivers/clk/samsung/clk-s3c2410.c { .val = 5, .div = 10 }, val 66 drivers/clk/samsung/clk-s3c2410.c { .val = 6, .div = 12 }, val 67 drivers/clk/samsung/clk-s3c2410.c { .val = 7, .div = 14 }, val 240 drivers/clk/samsung/clk-s3c2410.c { .val = 0, .div = 4 }, val 241 drivers/clk/samsung/clk-s3c2410.c { .val = 1, .div = 8 }, val 246 drivers/clk/samsung/clk-s3c2410.c { .val = 0, .div = 3 }, val 247 drivers/clk/samsung/clk-s3c2410.c { .val = 1, .div = 6 }, val 43 drivers/clk/samsung/clk-s3c2412.c { .val = 0, .div = 1 }, val 44 drivers/clk/samsung/clk-s3c2412.c { .val = 1, .div = 2 }, val 45 drivers/clk/samsung/clk-s3c2412.c { .val = 2, .div = 4 }, val 46 drivers/clk/samsung/clk-s3c2412.c { .val = 3, .div = 6 }, val 47 drivers/clk/samsung/clk-s3c2412.c { .val = 4, .div = 8 }, val 48 drivers/clk/samsung/clk-s3c2412.c { .val = 5, .div = 10 }, val 49 drivers/clk/samsung/clk-s3c2412.c { .val = 6, .div = 12 }, val 50 drivers/clk/samsung/clk-s3c2412.c { .val = 7, .div = 14 }, val 79 drivers/clk/samsung/clk-s3c2443.c { .val = 0, .div = 1 }, val 80 drivers/clk/samsung/clk-s3c2443.c { .val = 1, .div = 2 }, val 81 drivers/clk/samsung/clk-s3c2443.c { .val = 3, .div = 4 }, val 86 drivers/clk/samsung/clk-s3c2443.c { .val = 0, .div = 1 }, val 87 drivers/clk/samsung/clk-s3c2443.c { .val = 1, .div = 3 }, val 88 drivers/clk/samsung/clk-s3c2443.c { .val = 2, .div = 5 }, val 89 drivers/clk/samsung/clk-s3c2443.c { .val = 3, .div = 7 }, val 90 drivers/clk/samsung/clk-s3c2443.c { .val = 4, .div = 9 }, val 91 drivers/clk/samsung/clk-s3c2443.c { .val = 5, .div = 11 }, val 92 drivers/clk/samsung/clk-s3c2443.c { .val = 6, .div = 13 }, val 93 drivers/clk/samsung/clk-s3c2443.c { .val = 7, .div = 15 }, val 190 drivers/clk/samsung/clk-s3c2443.c { .val = 0, .div = 1 }, val 191 drivers/clk/samsung/clk-s3c2443.c { .val = 1, .div = 2 }, val 192 drivers/clk/samsung/clk-s3c2443.c { .val = 2, .div = 3 }, val 193 drivers/clk/samsung/clk-s3c2443.c { .val = 3, .div = 4 }, val 194 drivers/clk/samsung/clk-s3c2443.c { .val = 5, .div = 6 }, val 195 drivers/clk/samsung/clk-s3c2443.c { .val = 7, .div = 8 }, val 238 drivers/clk/samsung/clk-s3c2443.c { .val = 0, .div = 1 }, val 239 drivers/clk/samsung/clk-s3c2443.c { .val = 8, .div = 2 }, val 240 drivers/clk/samsung/clk-s3c2443.c { .val = 2, .div = 3 }, val 241 drivers/clk/samsung/clk-s3c2443.c { .val = 9, .div = 4 }, val 242 drivers/clk/samsung/clk-s3c2443.c { .val = 10, .div = 6 }, val 243 drivers/clk/samsung/clk-s3c2443.c { .val = 11, .div = 8 }, val 244 drivers/clk/samsung/clk-s3c2443.c { .val = 13, .div = 12 }, val 245 drivers/clk/samsung/clk-s3c2443.c { .val = 15, .div = 16 }, val 293 drivers/clk/sirf/clk-atlas7.c { .val = 0, .div = 1 }, val 294 drivers/clk/sirf/clk-atlas7.c { .val = 1, .div = 2 }, val 295 drivers/clk/sirf/clk-atlas7.c { .val = 2, .div = 4 }, val 296 drivers/clk/sirf/clk-atlas7.c { .val = 3, .div = 8 }, val 297 drivers/clk/sirf/clk-atlas7.c { .val = 4, .div = 16 }, val 298 drivers/clk/sirf/clk-atlas7.c { .val = 5, .div = 32 }, val 341 drivers/clk/sirf/clk-atlas7.c static inline void clkc_writel(u32 val, unsigned reg) val 343 drivers/clk/sirf/clk-atlas7.c writel(val, sirfsoc_clk_vbase + reg); val 498 drivers/clk/sirf/clk-atlas7.c u32 val, reg; val 503 drivers/clk/sirf/clk-atlas7.c val = clkc_readl(reg) | BIT(0); val 504 drivers/clk/sirf/clk-atlas7.c clkc_writel(val, reg); val 510 drivers/clk/sirf/clk-atlas7.c u32 val, reg; val 515 drivers/clk/sirf/clk-atlas7.c val = clkc_readl(reg) & ~BIT(0); val 516 drivers/clk/sirf/clk-atlas7.c clkc_writel(val, reg); val 64 drivers/clk/sirf/clk-common.c static inline void clkc_writel(u32 val, unsigned reg) val 66 drivers/clk/sirf/clk-common.c writel(val, sirfsoc_clk_vbase + reg); val 650 drivers/clk/sirf/clk-common.c u32 val, reg; val 660 drivers/clk/sirf/clk-common.c val = clkc_readl(reg) | BIT(bit); val 661 drivers/clk/sirf/clk-common.c clkc_writel(val, reg); val 667 drivers/clk/sirf/clk-common.c u32 val, reg; val 677 drivers/clk/sirf/clk-common.c val = clkc_readl(reg) & ~BIT(bit); val 678 drivers/clk/sirf/clk-common.c clkc_writel(val, reg); val 25 drivers/clk/socfpga/clk-gate-a10.c u32 div = 1, val; val 30 drivers/clk/socfpga/clk-gate-a10.c val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val 31 drivers/clk/socfpga/clk-gate-a10.c val &= GENMASK(socfpgaclk->width - 1, 0); val 32 drivers/clk/socfpga/clk-gate-a10.c div = (1 << val); val 18 drivers/clk/socfpga/clk-gate-s10.c u32 div = 1, val; val 23 drivers/clk/socfpga/clk-gate-s10.c val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val 24 drivers/clk/socfpga/clk-gate-s10.c val &= GENMASK(socfpgaclk->width - 1, 0); val 25 drivers/clk/socfpga/clk-gate-s10.c div = (1 << val); val 34 drivers/clk/socfpga/clk-gate-s10.c u32 div = 1, val; val 36 drivers/clk/socfpga/clk-gate-s10.c val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val 37 drivers/clk/socfpga/clk-gate-s10.c val &= GENMASK(socfpgaclk->width - 1, 0); val 38 drivers/clk/socfpga/clk-gate-s10.c div = (1 << val); val 94 drivers/clk/socfpga/clk-gate.c u32 div = 1, val; val 99 drivers/clk/socfpga/clk-gate.c val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val 100 drivers/clk/socfpga/clk-gate.c val &= GENMASK(socfpgaclk->width - 1, 0); val 103 drivers/clk/socfpga/clk-gate.c div = val + 1; val 105 drivers/clk/socfpga/clk-gate.c div = (1 << val); val 23 drivers/clk/socfpga/clk-periph-s10.c u32 val; val 25 drivers/clk/socfpga/clk-periph-s10.c val = readl(socfpgaclk->hw.reg); val 26 drivers/clk/socfpga/clk-periph-s10.c val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0); val 27 drivers/clk/socfpga/clk-periph-s10.c parent_rate /= val; val 21 drivers/clk/socfpga/clk-periph.c u32 div, val; val 27 drivers/clk/socfpga/clk-periph.c val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val 28 drivers/clk/socfpga/clk-periph.c val &= GENMASK(socfpgaclk->width - 1, 0); val 29 drivers/clk/socfpga/clk-periph.c parent_rate /= (val + 1); val 69 drivers/clk/spear/clk-aux-synth.c unsigned int num = 1, den = 1, val, eqn; val 75 drivers/clk/spear/clk-aux-synth.c val = readl_relaxed(aux->reg); val 80 drivers/clk/spear/clk-aux-synth.c eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; val 85 drivers/clk/spear/clk-aux-synth.c num = (val >> aux->masks->xscale_sel_shift) & val 89 drivers/clk/spear/clk-aux-synth.c den *= (val >> aux->masks->yscale_sel_shift) & val 104 drivers/clk/spear/clk-aux-synth.c unsigned long val, flags = 0; val 113 drivers/clk/spear/clk-aux-synth.c val = readl_relaxed(aux->reg) & val 115 drivers/clk/spear/clk-aux-synth.c val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << val 117 drivers/clk/spear/clk-aux-synth.c val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); val 118 drivers/clk/spear/clk-aux-synth.c val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) << val 120 drivers/clk/spear/clk-aux-synth.c val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift); val 121 drivers/clk/spear/clk-aux-synth.c val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) << val 123 drivers/clk/spear/clk-aux-synth.c writel_relaxed(val, aux->reg); val 73 drivers/clk/spear/clk-frac-synth.c unsigned int div = 1, val; val 78 drivers/clk/spear/clk-frac-synth.c val = readl_relaxed(frac->reg); val 83 drivers/clk/spear/clk-frac-synth.c div = val & DIV_FACTOR_MASK; val 100 drivers/clk/spear/clk-frac-synth.c unsigned long flags = 0, val; val 109 drivers/clk/spear/clk-frac-synth.c val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK; val 110 drivers/clk/spear/clk-frac-synth.c val |= rtbl[i].div & DIV_FACTOR_MASK; val 111 drivers/clk/spear/clk-frac-synth.c writel_relaxed(val, frac->reg); val 60 drivers/clk/spear/clk-gpt-synth.c unsigned int div = 1, val; val 65 drivers/clk/spear/clk-gpt-synth.c val = readl_relaxed(gpt->reg); val 70 drivers/clk/spear/clk-gpt-synth.c div += val & GPT_MSCALE_MASK; val 71 drivers/clk/spear/clk-gpt-synth.c div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); val 85 drivers/clk/spear/clk-gpt-synth.c unsigned long flags = 0, val; val 94 drivers/clk/spear/clk-gpt-synth.c val = readl(gpt->reg) & ~GPT_MSCALE_MASK; val 95 drivers/clk/spear/clk-gpt-synth.c val &= ~(GPT_NSCALE_MASK << GPT_NSCALE_SHIFT); val 97 drivers/clk/spear/clk-gpt-synth.c val |= rtbl[i].mscale & GPT_MSCALE_MASK; val 98 drivers/clk/spear/clk-gpt-synth.c val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT; val 100 drivers/clk/spear/clk-gpt-synth.c writel_relaxed(val, gpt->reg); val 149 drivers/clk/spear/clk-vco-pll.c unsigned long flags = 0, val; val 157 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(pll->vco->cfg_reg); val 158 drivers/clk/spear/clk-vco-pll.c val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT); val 159 drivers/clk/spear/clk-vco-pll.c val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT; val 160 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, pll->vco->cfg_reg); val 197 drivers/clk/spear/clk-vco-pll.c unsigned int num = 2, den = 0, val, mode = 0; val 204 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->cfg_reg); val 209 drivers/clk/spear/clk-vco-pll.c den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK; val 214 drivers/clk/spear/clk-vco-pll.c num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK; val 217 drivers/clk/spear/clk-vco-pll.c num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK; val 235 drivers/clk/spear/clk-vco-pll.c unsigned long flags = 0, val; val 244 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->mode_reg); val 245 drivers/clk/spear/clk-vco-pll.c val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); val 246 drivers/clk/spear/clk-vco-pll.c val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT; val 247 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, vco->mode_reg); val 249 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->cfg_reg); val 250 drivers/clk/spear/clk-vco-pll.c val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT); val 251 drivers/clk/spear/clk-vco-pll.c val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT; val 253 drivers/clk/spear/clk-vco-pll.c val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT); val 255 drivers/clk/spear/clk-vco-pll.c val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) << val 258 drivers/clk/spear/clk-vco-pll.c val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) << val 261 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, vco->cfg_reg); val 35 drivers/clk/sprd/div.c unsigned long val; val 39 drivers/clk/sprd/div.c val = reg >> div->shift; val 40 drivers/clk/sprd/div.c val &= (1 << div->width) - 1; val 42 drivers/clk/sprd/div.c return divider_recalc_rate(&common->hw, parent_rate, val, NULL, 0, val 60 drivers/clk/sprd/div.c unsigned long val; val 63 drivers/clk/sprd/div.c val = divider_get_val(rate, parent_rate, NULL, val 70 drivers/clk/sprd/div.c reg | (val << div->shift)); val 42 drivers/clk/sprd/pll.c unsigned int val = 0; val 47 drivers/clk/sprd/pll.c regmap_read(common->regmap, common->reg + index * 4, &val); val 49 drivers/clk/sprd/pll.c return val; val 54 drivers/clk/sprd/pll.c u32 msk, u32 val) val 66 drivers/clk/sprd/pll.c regmap_write(common->regmap, offset, (reg & ~msk) | val); val 143 drivers/clk/sprd/pll.c #define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \ val 144 drivers/clk/sprd/pll.c (((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT)) val 175 drivers/clk/sprd/pll.c cfg[index].val |= mask; val 182 drivers/clk/sprd/pll.c cfg[index].val |= mask; val 187 drivers/clk/sprd/pll.c cfg[index].val |= mask; val 194 drivers/clk/sprd/pll.c cfg[index].val |= (nint << shift) & mask; val 204 drivers/clk/sprd/pll.c cfg[index].val |= (kint << shift) & mask; val 212 drivers/clk/sprd/pll.c cfg[index].val |= ibias_val << shift & mask; val 217 drivers/clk/sprd/pll.c sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val); val 219 drivers/clk/sprd/pll.c cfg[i].val); val 14 drivers/clk/sprd/pll.h u32 val; val 590 drivers/clk/st/clkgen-fsyn.c uint64_t val; val 592 drivers/clk/st/clkgen-fsyn.c val = (uint64_t)output << si; val 594 drivers/clk/st/clkgen-fsyn.c *p = (uint64_t)input * P20 - (32LL + (uint64_t)m) * val * (P20 / 32LL); val 596 drivers/clk/st/clkgen-fsyn.c *p = div64_u64(*p, val); val 29 drivers/clk/st/clkgen.h unsigned long val) val 32 drivers/clk/st/clkgen.h ~(field->mask << field->shift)) | (val << field->shift), val 47 drivers/clk/st/clkgen.h #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \ val 48 drivers/clk/st/clkgen.h &pll->data->field, val) val 273 drivers/clk/sunxi-ng/ccu-sun4i-a10.c { .val = 0, .div = 2 }, val 274 drivers/clk/sunxi-ng/ccu-sun4i-a10.c { .val = 1, .div = 2 }, val 275 drivers/clk/sunxi-ng/ccu-sun4i-a10.c { .val = 2, .div = 4 }, val 276 drivers/clk/sunxi-ng/ccu-sun4i-a10.c { .val = 3, .div = 8 }, val 1432 drivers/clk/sunxi-ng/ccu-sun4i-a10.c u32 val; val 1441 drivers/clk/sunxi-ng/ccu-sun4i-a10.c val = readl(reg + SUN4I_PLL_AUDIO_REG); val 1448 drivers/clk/sunxi-ng/ccu-sun4i-a10.c val &= ~GENMASK(25, 16); val 1451 drivers/clk/sunxi-ng/ccu-sun4i-a10.c val &= ~GENMASK(29, 26); val 1452 drivers/clk/sunxi-ng/ccu-sun4i-a10.c writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG); val 1463 drivers/clk/sunxi-ng/ccu-sun4i-a10.c val = readl(reg + SUN4I_AHB_REG); val 1464 drivers/clk/sunxi-ng/ccu-sun4i-a10.c val &= ~GENMASK(7, 6); val 1465 drivers/clk/sunxi-ng/ccu-sun4i-a10.c writel(val | (2 << 6), reg + SUN4I_AHB_REG); val 252 drivers/clk/sunxi-ng/ccu-sun50i-a64.c { .val = 0, .div = 2 }, val 253 drivers/clk/sunxi-ng/ccu-sun50i-a64.c { .val = 1, .div = 2 }, val 254 drivers/clk/sunxi-ng/ccu-sun50i-a64.c { .val = 2, .div = 4 }, val 255 drivers/clk/sunxi-ng/ccu-sun50i-a64.c { .val = 3, .div = 8 }, val 388 drivers/clk/sunxi-ng/ccu-sun50i-a64.c { .val = 0, .div = 1 }, val 389 drivers/clk/sunxi-ng/ccu-sun50i-a64.c { .val = 1, .div = 2 }, val 390 drivers/clk/sunxi-ng/ccu-sun50i-a64.c { .val = 2, .div = 4 }, val 391 drivers/clk/sunxi-ng/ccu-sun50i-a64.c { .val = 3, .div = 6 }, val 942 drivers/clk/sunxi-ng/ccu-sun50i-a64.c u32 val; val 951 drivers/clk/sunxi-ng/ccu-sun50i-a64.c val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); val 952 drivers/clk/sunxi-ng/ccu-sun50i-a64.c val &= ~GENMASK(19, 16); val 953 drivers/clk/sunxi-ng/ccu-sun50i-a64.c writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); val 1179 drivers/clk/sunxi-ng/ccu-sun50i-h6.c u32 val; val 1189 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + pll_regs[i]); val 1190 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val |= BIT(29); val 1191 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val, reg + pll_regs[i]); val 1200 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + pll_video_regs[i]); val 1201 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val &= ~BIT(0); val 1202 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val, reg + pll_video_regs[i]); val 1212 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + usb2_clk_regs[i]); val 1213 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val &= ~GENMASK(25, 24); val 1214 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel (val, reg + usb2_clk_regs[i]); val 1221 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + SUN50I_H6_PLL_AUDIO_REG); val 1222 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val &= ~(GENMASK(21, 16) | BIT(0)); val 1223 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); val 1230 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG); val 1231 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val |= BIT(24); val 1232 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); val 222 drivers/clk/sunxi-ng/ccu-sun5i.c { .val = 0, .div = 2 }, val 223 drivers/clk/sunxi-ng/ccu-sun5i.c { .val = 1, .div = 2 }, val 224 drivers/clk/sunxi-ng/ccu-sun5i.c { .val = 2, .div = 4 }, val 225 drivers/clk/sunxi-ng/ccu-sun5i.c { .val = 3, .div = 8 }, val 991 drivers/clk/sunxi-ng/ccu-sun5i.c u32 val; val 1000 drivers/clk/sunxi-ng/ccu-sun5i.c val = readl(reg + SUN5I_PLL_AUDIO_REG); val 1001 drivers/clk/sunxi-ng/ccu-sun5i.c val &= ~GENMASK(29, 26); val 1002 drivers/clk/sunxi-ng/ccu-sun5i.c writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG); val 1011 drivers/clk/sunxi-ng/ccu-sun5i.c val = readl(reg + SUN5I_AHB_REG); val 1012 drivers/clk/sunxi-ng/ccu-sun5i.c val &= ~GENMASK(7, 6); val 1013 drivers/clk/sunxi-ng/ccu-sun5i.c writel(val | (2 << 6), reg + SUN5I_AHB_REG); val 185 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 0, .div = 1 }, val 186 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 1, .div = 2 }, val 187 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 2, .div = 3 }, val 188 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 3, .div = 4 }, val 189 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 4, .div = 4 }, val 190 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 5, .div = 4 }, val 191 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 6, .div = 4 }, val 192 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 7, .div = 4 }, val 229 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 0, .div = 2 }, val 230 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 1, .div = 2 }, val 231 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 2, .div = 4 }, val 232 drivers/clk/sunxi-ng/ccu-sun6i-a31.c { .val = 3, .div = 8 }, val 1232 drivers/clk/sunxi-ng/ccu-sun6i-a31.c u32 val; val 1241 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val = readl(reg + SUN6I_A31_PLL_AUDIO_REG); val 1242 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val &= ~GENMASK(19, 16); val 1243 drivers/clk/sunxi-ng/ccu-sun6i-a31.c writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG); val 1246 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val = readl(reg + SUN6I_A31_PLL_MIPI_REG); val 1247 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val &= BIT(16); val 1248 drivers/clk/sunxi-ng/ccu-sun6i-a31.c writel(val, reg + SUN6I_A31_PLL_MIPI_REG); val 1251 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val = readl(reg + SUN6I_A31_AHB1_REG); val 1253 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val &= ~GENMASK(7, 6); val 1254 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val |= 0x2 << 6; val 1256 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val &= ~GENMASK(13, 12); val 1257 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val |= 0x3 << 12; val 1258 drivers/clk/sunxi-ng/ccu-sun6i-a31.c writel(val, reg + SUN6I_A31_AHB1_REG); val 202 drivers/clk/sunxi-ng/ccu-sun8i-a23.c { .val = 0, .div = 2 }, val 203 drivers/clk/sunxi-ng/ccu-sun8i-a23.c { .val = 1, .div = 2 }, val 204 drivers/clk/sunxi-ng/ccu-sun8i-a23.c { .val = 2, .div = 4 }, val 205 drivers/clk/sunxi-ng/ccu-sun8i-a23.c { .val = 3, .div = 8 }, val 730 drivers/clk/sunxi-ng/ccu-sun8i-a23.c u32 val; val 739 drivers/clk/sunxi-ng/ccu-sun8i-a23.c val = readl(reg + SUN8I_A23_PLL_AUDIO_REG); val 740 drivers/clk/sunxi-ng/ccu-sun8i-a23.c val &= ~GENMASK(19, 16); val 741 drivers/clk/sunxi-ng/ccu-sun8i-a23.c writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG); val 744 drivers/clk/sunxi-ng/ccu-sun8i-a23.c val = readl(reg + SUN8I_A23_PLL_MIPI_REG); val 745 drivers/clk/sunxi-ng/ccu-sun8i-a23.c val &= ~BIT(16); val 746 drivers/clk/sunxi-ng/ccu-sun8i-a23.c writel(val, reg + SUN8I_A23_PLL_MIPI_REG); val 212 drivers/clk/sunxi-ng/ccu-sun8i-a33.c { .val = 0, .div = 2 }, val 213 drivers/clk/sunxi-ng/ccu-sun8i-a33.c { .val = 1, .div = 2 }, val 214 drivers/clk/sunxi-ng/ccu-sun8i-a33.c { .val = 2, .div = 4 }, val 215 drivers/clk/sunxi-ng/ccu-sun8i-a33.c { .val = 3, .div = 8 }, val 790 drivers/clk/sunxi-ng/ccu-sun8i-a33.c u32 val; val 799 drivers/clk/sunxi-ng/ccu-sun8i-a33.c val = readl(reg + SUN8I_A33_PLL_AUDIO_REG); val 800 drivers/clk/sunxi-ng/ccu-sun8i-a33.c val &= ~GENMASK(19, 16); val 801 drivers/clk/sunxi-ng/ccu-sun8i-a33.c writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG); val 804 drivers/clk/sunxi-ng/ccu-sun8i-a33.c val = readl(reg + SUN8I_A33_PLL_MIPI_REG); val 805 drivers/clk/sunxi-ng/ccu-sun8i-a33.c val &= ~BIT(16); val 806 drivers/clk/sunxi-ng/ccu-sun8i-a33.c writel(val, reg + SUN8I_A33_PLL_MIPI_REG); val 864 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c u32 val = readl(reg); val 867 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c if (!(val & BIT(SUN8I_A83T_PLL_P_SHIFT))) val 878 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1, val 880 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val |= 17 << SUN8I_A83T_PLL_N_SHIFT; val 883 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val &= ~BIT(SUN8I_A83T_PLL_P_SHIFT); val 885 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c writel(val, reg); val 892 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c u32 val; val 900 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val = readl(reg + SUN8I_A83T_PLL_AUDIO_REG); val 901 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val &= ~BIT(16); val 902 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val |= BIT(18); val 903 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG); val 176 drivers/clk/sunxi-ng/ccu-sun8i-h3.c { .val = 0, .div = 2 }, val 177 drivers/clk/sunxi-ng/ccu-sun8i-h3.c { .val = 1, .div = 2 }, val 178 drivers/clk/sunxi-ng/ccu-sun8i-h3.c { .val = 2, .div = 4 }, val 179 drivers/clk/sunxi-ng/ccu-sun8i-h3.c { .val = 3, .div = 8 }, val 321 drivers/clk/sunxi-ng/ccu-sun8i-h3.c { .val = 0, .div = 1 }, val 322 drivers/clk/sunxi-ng/ccu-sun8i-h3.c { .val = 1, .div = 2 }, val 323 drivers/clk/sunxi-ng/ccu-sun8i-h3.c { .val = 2, .div = 4 }, val 324 drivers/clk/sunxi-ng/ccu-sun8i-h3.c { .val = 3, .div = 6 }, val 1143 drivers/clk/sunxi-ng/ccu-sun8i-h3.c u32 val; val 1152 drivers/clk/sunxi-ng/ccu-sun8i-h3.c val = readl(reg + SUN8I_H3_PLL_AUDIO_REG); val 1153 drivers/clk/sunxi-ng/ccu-sun8i-h3.c val &= ~GENMASK(19, 16); val 1154 drivers/clk/sunxi-ng/ccu-sun8i-h3.c writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG); val 284 drivers/clk/sunxi-ng/ccu-sun8i-r40.c { .val = 0, .div = 2 }, val 285 drivers/clk/sunxi-ng/ccu-sun8i-r40.c { .val = 1, .div = 2 }, val 286 drivers/clk/sunxi-ng/ccu-sun8i-r40.c { .val = 2, .div = 4 }, val 287 drivers/clk/sunxi-ng/ccu-sun8i-r40.c { .val = 3, .div = 8 }, val 1302 drivers/clk/sunxi-ng/ccu-sun8i-r40.c u32 val; val 1311 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); val 1312 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val &= ~GENMASK(19, 16); val 1313 drivers/clk/sunxi-ng/ccu-sun8i-r40.c writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); val 1316 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val = readl(reg + SUN8I_R40_PLL_MIPI_REG); val 1317 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val &= ~BIT(16); val 1318 drivers/clk/sunxi-ng/ccu-sun8i-r40.c writel(val, reg + SUN8I_R40_PLL_MIPI_REG); val 1321 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val = readl(reg + SUN8I_R40_USB_CLK_REG); val 1322 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val &= ~GENMASK(25, 20); val 1323 drivers/clk/sunxi-ng/ccu-sun8i-r40.c writel(val, reg + SUN8I_R40_USB_CLK_REG); val 161 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c { .val = 0, .div = 2 }, val 162 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c { .val = 1, .div = 2 }, val 163 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c { .val = 2, .div = 4 }, val 164 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c { .val = 3, .div = 8 }, val 801 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c u32 val; val 810 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG); val 811 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c val &= ~GENMASK(19, 16); val 812 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG); val 237 drivers/clk/sunxi-ng/ccu-sun9i-a80.c { .val = 0, .div = 1 }, val 238 drivers/clk/sunxi-ng/ccu-sun9i-a80.c { .val = 1, .div = 2 }, val 239 drivers/clk/sunxi-ng/ccu-sun9i-a80.c { .val = 2, .div = 3 }, val 240 drivers/clk/sunxi-ng/ccu-sun9i-a80.c { .val = 3, .div = 4 }, val 241 drivers/clk/sunxi-ng/ccu-sun9i-a80.c { .val = 4, .div = 4 }, val 242 drivers/clk/sunxi-ng/ccu-sun9i-a80.c { .val = 5, .div = 4 }, val 243 drivers/clk/sunxi-ng/ccu-sun9i-a80.c { .val = 6, .div = 4 }, val 244 drivers/clk/sunxi-ng/ccu-sun9i-a80.c { .val = 7, .div = 4 }, val 1190 drivers/clk/sunxi-ng/ccu-sun9i-a80.c u32 val = readl(reg); val 1193 drivers/clk/sunxi-ng/ccu-sun9i-a80.c if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT))) val 1204 drivers/clk/sunxi-ng/ccu-sun9i-a80.c val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1, val 1206 drivers/clk/sunxi-ng/ccu-sun9i-a80.c val |= 17 << SUN9I_A80_PLL_N_SHIFT; val 1209 drivers/clk/sunxi-ng/ccu-sun9i-a80.c val &= ~BIT(SUN9I_A80_PLL_P_SHIFT); val 1211 drivers/clk/sunxi-ng/ccu-sun9i-a80.c writel(val, reg); val 1218 drivers/clk/sunxi-ng/ccu-sun9i-a80.c u32 val; val 1226 drivers/clk/sunxi-ng/ccu-sun9i-a80.c val = readl(reg + SUN9I_A80_PLL_AUDIO_REG); val 1227 drivers/clk/sunxi-ng/ccu-sun9i-a80.c val &= ~(BIT(16) | BIT(18)); val 1228 drivers/clk/sunxi-ng/ccu-sun9i-a80.c writel(val, reg + SUN9I_A80_PLL_AUDIO_REG); val 139 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c { .val = 0, .div = 2 }, val 140 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c { .val = 1, .div = 2 }, val 141 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c { .val = 2, .div = 4 }, val 142 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c { .val = 3, .div = 8 }, val 528 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c u32 val; val 537 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c val = readl(reg + SUNIV_PLL_AUDIO_REG); val 538 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c val &= ~GENMASK(19, 16); val 539 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG); val 60 drivers/clk/sunxi-ng/ccu_div.c unsigned long val; val 64 drivers/clk/sunxi-ng/ccu_div.c val = reg >> cd->div.shift; val 65 drivers/clk/sunxi-ng/ccu_div.c val &= (1 << cd->div.width) - 1; val 70 drivers/clk/sunxi-ng/ccu_div.c val = divider_recalc_rate(hw, parent_rate, val, cd->div.table, val 74 drivers/clk/sunxi-ng/ccu_div.c val /= cd->fixed_post_div; val 76 drivers/clk/sunxi-ng/ccu_div.c return val; val 93 drivers/clk/sunxi-ng/ccu_div.c unsigned long val; val 102 drivers/clk/sunxi-ng/ccu_div.c val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, val 110 drivers/clk/sunxi-ng/ccu_div.c writel(reg | (val << cd->div.shift), val 25 drivers/clk/sunxi-ng/ccu_mmc_timing.c u32 val; val 32 drivers/clk/sunxi-ng/ccu_mmc_timing.c val = readl(cm->base + cm->reg); val 34 drivers/clk/sunxi-ng/ccu_mmc_timing.c val |= CCU_MMC_NEW_TIMING_MODE; val 36 drivers/clk/sunxi-ng/ccu_mmc_timing.c val &= ~CCU_MMC_NEW_TIMING_MODE; val 37 drivers/clk/sunxi-ng/ccu_mmc_timing.c writel(val, cm->base + cm->reg); val 271 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); val 273 drivers/clk/sunxi-ng/ccu_mp.c if (val & CCU_MMC_NEW_TIMING_MODE) val 282 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); val 286 drivers/clk/sunxi-ng/ccu_mp.c if (val & CCU_MMC_NEW_TIMING_MODE) { val 295 drivers/clk/sunxi-ng/ccu_mp.c if (val & CCU_MMC_NEW_TIMING_MODE) { val 308 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); val 310 drivers/clk/sunxi-ng/ccu_mp.c if (val & CCU_MMC_NEW_TIMING_MODE) val 78 drivers/clk/sunxi-ng/ccu_mult.c unsigned long val; val 85 drivers/clk/sunxi-ng/ccu_mult.c val = reg >> cm->mult.shift; val 86 drivers/clk/sunxi-ng/ccu_mult.c val &= (1 << cm->mult.width) - 1; val 91 drivers/clk/sunxi-ng/ccu_mult.c return parent_rate * (val + cm->mult.offset); val 47 drivers/clk/sunxi/clk-a10-pll2.c u32 val; val 115 drivers/clk/sunxi/clk-a10-pll2.c val = readl(reg); val 116 drivers/clk/sunxi/clk-a10-pll2.c val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); val 117 drivers/clk/sunxi/clk-a10-pll2.c val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; val 118 drivers/clk/sunxi/clk-a10-pll2.c writel(val, reg); val 37 drivers/clk/sunxi/clk-factors.c #define FACTOR_SET(bit, len, reg, val) \ val 38 drivers/clk/sunxi/clk-factors.c (((reg) & CLRMASK(len, bit)) | (val << (bit))) val 23 drivers/clk/sunxi/clk-sun6i-apb0.c { .val = 0, .div = 2, }, val 24 drivers/clk/sunxi/clk-sun6i-apb0.c { .val = 1, .div = 2, }, val 25 drivers/clk/sunxi/clk-sun6i-apb0.c { .val = 2, .div = 4, }, val 26 drivers/clk/sunxi/clk-sun6i-apb0.c { .val = 3, .div = 8, }, val 43 drivers/clk/sunxi/clk-sun9i-mmc.c u32 val; val 48 drivers/clk/sunxi/clk-sun9i-mmc.c val = readl(reg); val 49 drivers/clk/sunxi/clk-sun9i-mmc.c writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg); val 65 drivers/clk/sunxi/clk-sun9i-mmc.c u32 val; val 70 drivers/clk/sunxi/clk-sun9i-mmc.c val = readl(reg); val 71 drivers/clk/sunxi/clk-sun9i-mmc.c writel(val | BIT(SUN9I_MMC_RESET_BIT), reg); val 738 drivers/clk/sunxi/clk-sunxi.c { .val = 0, .div = 1 }, val 739 drivers/clk/sunxi/clk-sunxi.c { .val = 1, .div = 2 }, val 740 drivers/clk/sunxi/clk-sunxi.c { .val = 2, .div = 3 }, val 741 drivers/clk/sunxi/clk-sunxi.c { .val = 3, .div = 4 }, val 742 drivers/clk/sunxi/clk-sunxi.c { .val = 4, .div = 4 }, val 743 drivers/clk/sunxi/clk-sunxi.c { .val = 5, .div = 4 }, val 744 drivers/clk/sunxi/clk-sunxi.c { .val = 6, .div = 4 }, val 745 drivers/clk/sunxi/clk-sunxi.c { .val = 7, .div = 4 }, val 761 drivers/clk/sunxi/clk-sunxi.c { .val = 0, .div = 2 }, val 762 drivers/clk/sunxi/clk-sunxi.c { .val = 1, .div = 2 }, val 763 drivers/clk/sunxi/clk-sunxi.c { .val = 2, .div = 4 }, val 764 drivers/clk/sunxi/clk-sunxi.c { .val = 3, .div = 8 }, val 894 drivers/clk/sunxi/clk-sunxi.c { .val = 0, .div = 6, }, val 895 drivers/clk/sunxi/clk-sunxi.c { .val = 1, .div = 12, }, val 896 drivers/clk/sunxi/clk-sunxi.c { .val = 2, .div = 18, }, val 897 drivers/clk/sunxi/clk-sunxi.c { .val = 3, .div = 24, }, val 335 drivers/clk/tegra/clk-dfll.c static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs) val 338 drivers/clk/tegra/clk-dfll.c __raw_writel(val, td->base + offs); val 353 drivers/clk/tegra/clk-dfll.c static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs) val 355 drivers/clk/tegra/clk-dfll.c __raw_writel(val, td->i2c_base + offs); val 541 drivers/clk/tegra/clk-dfll.c u32 val; val 543 drivers/clk/tegra/clk-dfll.c val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG); val 546 drivers/clk/tegra/clk-dfll.c val |= DFLL_OUTPUT_CFG_I2C_ENABLE; val 548 drivers/clk/tegra/clk-dfll.c val &= ~DFLL_OUTPUT_CFG_I2C_ENABLE; val 550 drivers/clk/tegra/clk-dfll.c dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); val 573 drivers/clk/tegra/clk-dfll.c u32 val, div; val 581 drivers/clk/tegra/clk-dfll.c val = dfll_readl(td, DFLL_OUTPUT_CFG); val 582 drivers/clk/tegra/clk-dfll.c val &= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK; val 584 drivers/clk/tegra/clk-dfll.c val |= (div << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT) val 586 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_OUTPUT_CFG); val 589 drivers/clk/tegra/clk-dfll.c val |= DFLL_OUTPUT_CFG_PWM_ENABLE; val 590 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_OUTPUT_CFG); val 597 drivers/clk/tegra/clk-dfll.c val = dfll_readl(td, DFLL_OUTPUT_CFG); val 598 drivers/clk/tegra/clk-dfll.c val &= ~DFLL_OUTPUT_CFG_PWM_ENABLE; val 599 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_OUTPUT_CFG); val 616 drivers/clk/tegra/clk-dfll.c u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); val 618 drivers/clk/tegra/clk-dfll.c val = (val & DFLL_OUTPUT_FORCE_ENABLE) | (out_val & OUT_MASK); val 619 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_OUTPUT_FORCE); val 634 drivers/clk/tegra/clk-dfll.c u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); val 637 drivers/clk/tegra/clk-dfll.c val |= DFLL_OUTPUT_FORCE_ENABLE; val 639 drivers/clk/tegra/clk-dfll.c val &= ~DFLL_OUTPUT_FORCE_ENABLE; val 641 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_OUTPUT_FORCE); val 654 drivers/clk/tegra/clk-dfll.c u32 val; val 659 drivers/clk/tegra/clk-dfll.c val = dfll_set_force_output_value(td, out_sel); val 661 drivers/clk/tegra/clk-dfll.c !(val & DFLL_OUTPUT_FORCE_ENABLE)) { val 678 drivers/clk/tegra/clk-dfll.c u32 val; val 688 drivers/clk/tegra/clk-dfll.c val = regulator_list_hardware_vsel(td->vdd_reg, val 690 drivers/clk/tegra/clk-dfll.c __raw_writel(val, td->lut_base + i * 4); val 708 drivers/clk/tegra/clk-dfll.c u32 val; val 711 drivers/clk/tegra/clk-dfll.c val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT; val 712 drivers/clk/tegra/clk-dfll.c val |= DFLL_I2C_CFG_SLAVE_ADDR_10; val 714 drivers/clk/tegra/clk-dfll.c val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT; val 716 drivers/clk/tegra/clk-dfll.c val |= DFLL_I2C_CFG_SIZE_MASK; val 717 drivers/clk/tegra/clk-dfll.c val |= DFLL_I2C_CFG_ARB_ENABLE; val 718 drivers/clk/tegra/clk-dfll.c dfll_i2c_writel(td, val, DFLL_I2C_CFG); val 722 drivers/clk/tegra/clk-dfll.c val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8); val 723 drivers/clk/tegra/clk-dfll.c BUG_ON(!val || (val > DFLL_I2C_CLK_DIVISOR_MASK)); val 724 drivers/clk/tegra/clk-dfll.c val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT; val 727 drivers/clk/tegra/clk-dfll.c val |= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT; val 728 drivers/clk/tegra/clk-dfll.c __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR); val 742 drivers/clk/tegra/clk-dfll.c u32 val; val 752 drivers/clk/tegra/clk-dfll.c val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | val 755 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_OUTPUT_CFG); val 830 drivers/clk/tegra/clk-dfll.c u32 val; val 854 drivers/clk/tegra/clk-dfll.c val = DVCO_RATE_TO_MULT(rate, td->ref_rate); val 855 drivers/clk/tegra/clk-dfll.c if (val > FREQ_MAX) { val 860 drivers/clk/tegra/clk-dfll.c req->mult_bits = val; val 882 drivers/clk/tegra/clk-dfll.c u32 val = 0; val 889 drivers/clk/tegra/clk-dfll.c val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT; val 890 drivers/clk/tegra/clk-dfll.c val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT; val 891 drivers/clk/tegra/clk-dfll.c val |= ((u32)force_val << DFLL_FREQ_REQ_FORCE_SHIFT) & val 893 drivers/clk/tegra/clk-dfll.c val |= DFLL_FREQ_REQ_FREQ_VALID | DFLL_FREQ_REQ_FORCE_ENABLE; val 895 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_FREQ_REQ); val 994 drivers/clk/tegra/clk-dfll.c u32 val; val 1000 drivers/clk/tegra/clk-dfll.c val = dfll_readl(td, DFLL_FREQ_REQ); val 1001 drivers/clk/tegra/clk-dfll.c val |= DFLL_FREQ_REQ_SCALE_MASK; val 1002 drivers/clk/tegra/clk-dfll.c val &= ~DFLL_FREQ_REQ_FORCE_ENABLE; val 1003 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_FREQ_REQ); val 1273 drivers/clk/tegra/clk-dfll.c static int attr_enable_get(void *data, u64 *val) val 1277 drivers/clk/tegra/clk-dfll.c *val = dfll_is_running(td); val 1281 drivers/clk/tegra/clk-dfll.c static int attr_enable_set(void *data, u64 val) val 1285 drivers/clk/tegra/clk-dfll.c return val ? dfll_enable(td) : dfll_disable(td); val 1290 drivers/clk/tegra/clk-dfll.c static int attr_lock_get(void *data, u64 *val) val 1294 drivers/clk/tegra/clk-dfll.c *val = (td->mode == DFLL_CLOSED_LOOP); val 1298 drivers/clk/tegra/clk-dfll.c static int attr_lock_set(void *data, u64 val) val 1302 drivers/clk/tegra/clk-dfll.c return val ? dfll_lock(td) : dfll_unlock(td); val 1306 drivers/clk/tegra/clk-dfll.c static int attr_rate_get(void *data, u64 *val) val 1310 drivers/clk/tegra/clk-dfll.c *val = dfll_read_monitor_rate(td); val 1315 drivers/clk/tegra/clk-dfll.c static int attr_rate_set(void *data, u64 val) val 1319 drivers/clk/tegra/clk-dfll.c return dfll_request_rate(td, val); val 1325 drivers/clk/tegra/clk-dfll.c u32 val, offs; val 1331 drivers/clk/tegra/clk-dfll.c val = dfll_i2c_readl(td, offs); val 1333 drivers/clk/tegra/clk-dfll.c val = dfll_readl(td, offs); val 1334 drivers/clk/tegra/clk-dfll.c seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val); val 1397 drivers/clk/tegra/clk-dfll.c u32 val; val 1399 drivers/clk/tegra/clk-dfll.c val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32); val 1400 drivers/clk/tegra/clk-dfll.c BUG_ON(val > DFLL_CONFIG_DIV_MASK); val 1401 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_CONFIG); val 1403 drivers/clk/tegra/clk-dfll.c val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) | val 1408 drivers/clk/tegra/clk-dfll.c dfll_writel(td, val, DFLL_PARAMS); val 81 drivers/clk/tegra/clk-divider.c u32 val; val 90 drivers/clk/tegra/clk-divider.c val = readl_relaxed(divider->reg); val 91 drivers/clk/tegra/clk-divider.c val &= ~(div_mask(divider) << divider->shift); val 92 drivers/clk/tegra/clk-divider.c val |= div << divider->shift; val 96 drivers/clk/tegra/clk-divider.c val |= PERIPH_CLK_UART_DIV_ENB; val 98 drivers/clk/tegra/clk-divider.c val &= ~PERIPH_CLK_UART_DIV_ENB; val 102 drivers/clk/tegra/clk-divider.c val |= pll_out_override(divider); val 104 drivers/clk/tegra/clk-divider.c writel_relaxed(val, divider->reg); val 158 drivers/clk/tegra/clk-divider.c { .val = 0, .div = 2 }, val 159 drivers/clk/tegra/clk-divider.c { .val = 1, .div = 1 }, val 160 drivers/clk/tegra/clk-divider.c { .val = 0, .div = 0 }, val 91 drivers/clk/tegra/clk-emc.c u32 val, div; val 101 drivers/clk/tegra/clk-emc.c val = readl(tegra->clk_regs + CLK_SOURCE_EMC); val 102 drivers/clk/tegra/clk-emc.c div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK; val 162 drivers/clk/tegra/clk-emc.c u32 val; val 166 drivers/clk/tegra/clk-emc.c val = readl(tegra->clk_regs + CLK_SOURCE_EMC); val 168 drivers/clk/tegra/clk-emc.c return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT) val 21 drivers/clk/tegra/clk-periph-gate.c #define write_enb_set(val, gate) \ val 22 drivers/clk/tegra/clk-periph-gate.c writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg)) val 23 drivers/clk/tegra/clk-periph-gate.c #define write_enb_clr(val, gate) \ val 24 drivers/clk/tegra/clk-periph-gate.c writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg)) val 28 drivers/clk/tegra/clk-periph-gate.c #define write_rst_clr(val, gate) \ val 29 drivers/clk/tegra/clk-periph-gate.c writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) val 21 drivers/clk/tegra/clk-pll-out.c u32 val = readl_relaxed(pll_out->reg); val 24 drivers/clk/tegra/clk-pll-out.c state = (val & pll_out_enb(pll_out)) ? 1 : 0; val 25 drivers/clk/tegra/clk-pll-out.c if (!(val & (pll_out_rst(pll_out)))) val 34 drivers/clk/tegra/clk-pll-out.c u32 val; val 39 drivers/clk/tegra/clk-pll-out.c val = readl_relaxed(pll_out->reg); val 41 drivers/clk/tegra/clk-pll-out.c val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out)); val 43 drivers/clk/tegra/clk-pll-out.c writel_relaxed(val, pll_out->reg); val 56 drivers/clk/tegra/clk-pll-out.c u32 val; val 61 drivers/clk/tegra/clk-pll-out.c val = readl_relaxed(pll_out->reg); val 63 drivers/clk/tegra/clk-pll-out.c val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out)); val 65 drivers/clk/tegra/clk-pll-out.c writel_relaxed(val, pll_out->reg); val 237 drivers/clk/tegra/clk-pll.c #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) val 238 drivers/clk/tegra/clk-pll.c #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) val 239 drivers/clk/tegra/clk-pll.c #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) val 240 drivers/clk/tegra/clk-pll.c #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) val 241 drivers/clk/tegra/clk-pll.c #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p) val 242 drivers/clk/tegra/clk-pll.c #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p) val 278 drivers/clk/tegra/clk-pll.c u32 val; val 286 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 287 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->lock_enable_bit_idx); val 288 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 294 drivers/clk/tegra/clk-pll.c u32 val, lock_mask; val 311 drivers/clk/tegra/clk-pll.c val = readl_relaxed(lock_addr); val 312 drivers/clk/tegra/clk-pll.c if ((val & lock_mask) == lock_mask) { val 333 drivers/clk/tegra/clk-pll.c u32 val; val 336 drivers/clk/tegra/clk-pll.c val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); val 337 drivers/clk/tegra/clk-pll.c if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) val 338 drivers/clk/tegra/clk-pll.c return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; val 341 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 343 drivers/clk/tegra/clk-pll.c return val & PLL_BASE_ENABLE ? 1 : 0; val 349 drivers/clk/tegra/clk-pll.c u32 val; val 352 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->iddq_reg, pll); val 353 drivers/clk/tegra/clk-pll.c val &= ~BIT(pll->params->iddq_bit_idx); val 354 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->iddq_reg, pll); val 359 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->reset_reg, pll); val 360 drivers/clk/tegra/clk-pll.c val &= ~BIT(pll->params->reset_bit_idx); val 361 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->reset_reg, pll); val 366 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 368 drivers/clk/tegra/clk-pll.c val &= ~PLL_BASE_BYPASS; val 369 drivers/clk/tegra/clk-pll.c val |= PLL_BASE_ENABLE; val 370 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 373 drivers/clk/tegra/clk-pll.c val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); val 374 drivers/clk/tegra/clk-pll.c val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; val 375 drivers/clk/tegra/clk-pll.c writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); val 382 drivers/clk/tegra/clk-pll.c u32 val; val 384 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 386 drivers/clk/tegra/clk-pll.c val &= ~PLL_BASE_BYPASS; val 387 drivers/clk/tegra/clk-pll.c val &= ~PLL_BASE_ENABLE; val 388 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 391 drivers/clk/tegra/clk-pll.c val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); val 392 drivers/clk/tegra/clk-pll.c val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; val 393 drivers/clk/tegra/clk-pll.c writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); val 397 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->reset_reg, pll); val 398 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->reset_bit_idx); val 399 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->reset_reg, pll); val 403 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->iddq_reg, pll); val 404 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->iddq_bit_idx); val 405 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->iddq_reg, pll); val 413 drivers/clk/tegra/clk-pll.c u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); val 415 drivers/clk/tegra/clk-pll.c val |= pll->params->ssc_ctrl_en_mask; val 416 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->ssc_ctrl_reg, pll); val 423 drivers/clk/tegra/clk-pll.c u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); val 425 drivers/clk/tegra/clk-pll.c val &= ~pll->params->ssc_ctrl_en_mask; val 426 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->ssc_ctrl_reg, pll); val 618 drivers/clk/tegra/clk-pll.c u32 val; val 625 drivers/clk/tegra/clk-pll.c val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); val 626 drivers/clk/tegra/clk-pll.c val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); val 627 drivers/clk/tegra/clk-pll.c pll_writel_sdm_din(val, pll); val 630 drivers/clk/tegra/clk-pll.c val = pll_readl_sdm_ctrl(pll); val 631 drivers/clk/tegra/clk-pll.c enabled = (val & sdm_en_mask(pll)); val 634 drivers/clk/tegra/clk-pll.c val &= ~pll->params->sdm_ctrl_en_mask; val 637 drivers/clk/tegra/clk-pll.c val |= pll->params->sdm_ctrl_en_mask; val 639 drivers/clk/tegra/clk-pll.c pll_writel_sdm_ctrl(val, pll); val 645 drivers/clk/tegra/clk-pll.c u32 val; val 652 drivers/clk/tegra/clk-pll.c val = pll_override_readl(params->pmc_divp_reg, pll); val 653 drivers/clk/tegra/clk-pll.c val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); val 654 drivers/clk/tegra/clk-pll.c val |= cfg->p << div_nmp->override_divp_shift; val 655 drivers/clk/tegra/clk-pll.c pll_override_writel(val, params->pmc_divp_reg, pll); val 657 drivers/clk/tegra/clk-pll.c val = pll_override_readl(params->pmc_divnm_reg, pll); val 658 drivers/clk/tegra/clk-pll.c val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | val 660 drivers/clk/tegra/clk-pll.c val |= (cfg->m << div_nmp->override_divm_shift) | val 662 drivers/clk/tegra/clk-pll.c pll_override_writel(val, params->pmc_divnm_reg, pll); val 664 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 666 drivers/clk/tegra/clk-pll.c val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | val 669 drivers/clk/tegra/clk-pll.c val |= (cfg->m << divm_shift(pll)) | val 673 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 682 drivers/clk/tegra/clk-pll.c u32 val; val 691 drivers/clk/tegra/clk-pll.c val = pll_override_readl(params->pmc_divp_reg, pll); val 692 drivers/clk/tegra/clk-pll.c cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); val 694 drivers/clk/tegra/clk-pll.c val = pll_override_readl(params->pmc_divnm_reg, pll); val 695 drivers/clk/tegra/clk-pll.c cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); val 696 drivers/clk/tegra/clk-pll.c cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); val 698 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 700 drivers/clk/tegra/clk-pll.c cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); val 701 drivers/clk/tegra/clk-pll.c cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); val 702 drivers/clk/tegra/clk-pll.c cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); val 706 drivers/clk/tegra/clk-pll.c val = pll_readl_sdm_din(pll); val 707 drivers/clk/tegra/clk-pll.c val &= sdm_din_mask(pll); val 708 drivers/clk/tegra/clk-pll.c cfg->sdm_data = sdin_din_to_data(val); val 718 drivers/clk/tegra/clk-pll.c u32 val; val 720 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 722 drivers/clk/tegra/clk-pll.c val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); val 723 drivers/clk/tegra/clk-pll.c val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; val 726 drivers/clk/tegra/clk-pll.c val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); val 728 drivers/clk/tegra/clk-pll.c val |= 1 << PLL_MISC_LFCON_SHIFT; val 730 drivers/clk/tegra/clk-pll.c val &= ~(1 << PLL_MISC_DCCON_SHIFT); val 732 drivers/clk/tegra/clk-pll.c val |= 1 << PLL_MISC_DCCON_SHIFT; val 735 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 845 drivers/clk/tegra/clk-pll.c u32 val; val 849 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 851 drivers/clk/tegra/clk-pll.c if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) val 856 drivers/clk/tegra/clk-pll.c !(val & PLL_BASE_OVERRIDE)) { val 893 drivers/clk/tegra/clk-pll.c u32 val; val 903 drivers/clk/tegra/clk-pll.c val = readl(pll->pmc + PMC_SATA_PWRGT); val 904 drivers/clk/tegra/clk-pll.c val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; val 905 drivers/clk/tegra/clk-pll.c writel(val, pll->pmc + PMC_SATA_PWRGT); val 907 drivers/clk/tegra/clk-pll.c val = readl(pll->pmc + PMC_SATA_PWRGT); val 908 drivers/clk/tegra/clk-pll.c val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; val 909 drivers/clk/tegra/clk-pll.c writel(val, pll->pmc + PMC_SATA_PWRGT); val 911 drivers/clk/tegra/clk-pll.c val = readl(pll->pmc + PMC_SATA_PWRGT); val 912 drivers/clk/tegra/clk-pll.c val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; val 913 drivers/clk/tegra/clk-pll.c writel(val, pll->pmc + PMC_SATA_PWRGT); val 915 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 919 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 920 drivers/clk/tegra/clk-pll.c if (val & PLLE_MISC_READY) val 937 drivers/clk/tegra/clk-pll.c u32 val; val 950 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 951 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); val 952 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 954 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 955 drivers/clk/tegra/clk-pll.c if (!(val & PLLE_MISC_READY)) { val 963 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 964 drivers/clk/tegra/clk-pll.c val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | val 966 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); val 967 drivers/clk/tegra/clk-pll.c val |= sel.m << divm_shift(pll); val 968 drivers/clk/tegra/clk-pll.c val |= sel.n << divn_shift(pll); val 969 drivers/clk/tegra/clk-pll.c val |= sel.p << divp_shift(pll); val 970 drivers/clk/tegra/clk-pll.c val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; val 971 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 974 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 975 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_SETUP_VALUE; val 976 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_LOCK_ENABLE; val 977 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 979 drivers/clk/tegra/clk-pll.c val = readl(pll->clk_base + PLLE_SS_CTRL); val 980 drivers/clk/tegra/clk-pll.c val &= ~PLLE_SS_COEFFICIENTS_MASK; val 981 drivers/clk/tegra/clk-pll.c val |= PLLE_SS_DISABLE; val 982 drivers/clk/tegra/clk-pll.c writel(val, pll->clk_base + PLLE_SS_CTRL); val 984 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 985 drivers/clk/tegra/clk-pll.c val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); val 986 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 997 drivers/clk/tegra/clk-pll.c u32 val = pll_readl_base(pll); val 1001 drivers/clk/tegra/clk-pll.c divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); val 1002 drivers/clk/tegra/clk-pll.c divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); val 1003 drivers/clk/tegra/clk-pll.c divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); val 1225 drivers/clk/tegra/clk-pll.c u32 val; val 1250 drivers/clk/tegra/clk-pll.c val = step_a << pll_params->stepa_shift; val 1251 drivers/clk/tegra/clk-pll.c val |= step_b << pll_params->stepb_shift; val 1252 drivers/clk/tegra/clk-pll.c writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); val 1337 drivers/clk/tegra/clk-pll.c u32 val; val 1339 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 1340 drivers/clk/tegra/clk-pll.c val |= PLLCX_MISC_STROBE; val 1341 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 1344 drivers/clk/tegra/clk-pll.c val &= ~PLLCX_MISC_STROBE; val 1345 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 1351 drivers/clk/tegra/clk-pll.c u32 val; val 1364 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 1365 drivers/clk/tegra/clk-pll.c val &= ~PLLCX_MISC_RESET; val 1366 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 1382 drivers/clk/tegra/clk-pll.c u32 val; val 1386 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 1387 drivers/clk/tegra/clk-pll.c val |= PLLCX_MISC_RESET; val 1388 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 1409 drivers/clk/tegra/clk-pll.c u32 val, n_threshold; val 1431 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 1432 drivers/clk/tegra/clk-pll.c val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); val 1433 drivers/clk/tegra/clk-pll.c val |= n <= n_threshold ? val 1435 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 1567 drivers/clk/tegra/clk-pll.c u32 val; val 1583 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 1584 drivers/clk/tegra/clk-pll.c val &= ~BIT(29); /* Disable lock override */ val 1585 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 1587 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); val 1588 drivers/clk/tegra/clk-pll.c val |= PLLE_AUX_ENABLE_SWCTL; val 1589 drivers/clk/tegra/clk-pll.c val &= ~PLLE_AUX_SEQ_ENABLE; val 1590 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); val 1593 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 1594 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_LOCK_ENABLE; val 1595 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_IDDQ_SW_CTRL; val 1596 drivers/clk/tegra/clk-pll.c val &= ~PLLE_MISC_IDDQ_SW_VALUE; val 1597 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_PLLE_PTS; val 1598 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); val 1599 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 1602 drivers/clk/tegra/clk-pll.c val = pll_readl(PLLE_SS_CTRL, pll); val 1603 drivers/clk/tegra/clk-pll.c val |= PLLE_SS_DISABLE; val 1604 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); val 1606 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 1607 drivers/clk/tegra/clk-pll.c val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | val 1609 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); val 1610 drivers/clk/tegra/clk-pll.c val |= sel.m << divm_shift(pll); val 1611 drivers/clk/tegra/clk-pll.c val |= sel.n << divn_shift(pll); val 1612 drivers/clk/tegra/clk-pll.c val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; val 1613 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 1622 drivers/clk/tegra/clk-pll.c val = pll_readl(PLLE_SS_CTRL, pll); val 1623 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); val 1624 drivers/clk/tegra/clk-pll.c val &= ~PLLE_SS_COEFFICIENTS_MASK; val 1625 drivers/clk/tegra/clk-pll.c val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114; val 1626 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); val 1627 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); val 1628 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); val 1630 drivers/clk/tegra/clk-pll.c val &= ~PLLE_SS_CNTL_INTERP_RESET; val 1631 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); val 1635 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 1636 drivers/clk/tegra/clk-pll.c val &= ~PLLE_MISC_IDDQ_SW_CTRL; val 1637 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 1639 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); val 1640 drivers/clk/tegra/clk-pll.c val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); val 1641 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); val 1642 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); val 1644 drivers/clk/tegra/clk-pll.c val |= PLLE_AUX_SEQ_ENABLE; val 1645 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); val 1647 drivers/clk/tegra/clk-pll.c val = pll_readl(XUSBIO_PLL_CFG0, pll); val 1648 drivers/clk/tegra/clk-pll.c val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | val 1650 drivers/clk/tegra/clk-pll.c val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | val 1652 drivers/clk/tegra/clk-pll.c pll_writel(val, XUSBIO_PLL_CFG0, pll); val 1654 drivers/clk/tegra/clk-pll.c val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; val 1655 drivers/clk/tegra/clk-pll.c pll_writel(val, XUSBIO_PLL_CFG0, pll); val 1658 drivers/clk/tegra/clk-pll.c val = pll_readl(SATA_PLL_CFG0, pll); val 1659 drivers/clk/tegra/clk-pll.c val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; val 1660 drivers/clk/tegra/clk-pll.c val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; val 1661 drivers/clk/tegra/clk-pll.c val |= SATA_PLL_CFG0_SEQ_START_STATE; val 1662 drivers/clk/tegra/clk-pll.c pll_writel(val, SATA_PLL_CFG0, pll); val 1666 drivers/clk/tegra/clk-pll.c val = pll_readl(SATA_PLL_CFG0, pll); val 1667 drivers/clk/tegra/clk-pll.c val |= SATA_PLL_CFG0_SEQ_ENABLE; val 1668 drivers/clk/tegra/clk-pll.c pll_writel(val, SATA_PLL_CFG0, pll); val 1681 drivers/clk/tegra/clk-pll.c u32 val; val 1688 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 1689 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; val 1690 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 1989 drivers/clk/tegra/clk-pll.c u32 val, val_iddq; val 2020 drivers/clk/tegra/clk-pll.c val = readl_relaxed(clk_base + pll_params->base_reg); val 2023 drivers/clk/tegra/clk-pll.c if (val & PLL_BASE_ENABLE) val 2050 drivers/clk/tegra/clk-pll.c u32 val; val 2066 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2067 drivers/clk/tegra/clk-pll.c if (val & PLL_BASE_ENABLE) val 2074 drivers/clk/tegra/clk-pll.c val = m << divm_shift(pll); val 2075 drivers/clk/tegra/clk-pll.c val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); val 2076 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 2081 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 2082 drivers/clk/tegra/clk-pll.c val &= ~BIT(29); val 2083 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 2217 drivers/clk/tegra/clk-pll.c u32 val, val_aux; val 2225 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2228 drivers/clk/tegra/clk-pll.c if (val & PLL_BASE_ENABLE) { val 2290 drivers/clk/tegra/clk-pll.c u32 val, val_iddq; val 2307 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2308 drivers/clk/tegra/clk-pll.c val &= ~PLLSS_REF_SRC_SEL_MASK; val 2309 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 2336 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2338 drivers/clk/tegra/clk-pll.c if (val & PLL_BASE_ENABLE) { val 2349 drivers/clk/tegra/clk-pll.c val &= ~PLLSS_LOCK_OVERRIDE; val 2350 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 2393 drivers/clk/tegra/clk-pll.c u32 val; val 2395 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2397 drivers/clk/tegra/clk-pll.c return val & PLLE_BASE_ENABLE ? 1 : 0; val 2404 drivers/clk/tegra/clk-pll.c u32 val; val 2420 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); val 2421 drivers/clk/tegra/clk-pll.c if (val & PLLE_AUX_SEQ_ENABLE) val 2424 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2425 drivers/clk/tegra/clk-pll.c val &= ~BIT(30); /* Disable lock override */ val 2426 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 2428 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 2429 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_LOCK_ENABLE; val 2430 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_IDDQ_SW_CTRL; val 2431 drivers/clk/tegra/clk-pll.c val &= ~PLLE_MISC_IDDQ_SW_VALUE; val 2432 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_PLLE_PTS; val 2433 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); val 2434 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 2437 drivers/clk/tegra/clk-pll.c val = pll_readl(PLLE_SS_CTRL, pll); val 2438 drivers/clk/tegra/clk-pll.c val |= PLLE_SS_DISABLE; val 2439 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); val 2441 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2442 drivers/clk/tegra/clk-pll.c val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | val 2444 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); val 2445 drivers/clk/tegra/clk-pll.c val |= sel.m << divm_shift(pll); val 2446 drivers/clk/tegra/clk-pll.c val |= sel.n << divn_shift(pll); val 2447 drivers/clk/tegra/clk-pll.c val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; val 2448 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 2451 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2452 drivers/clk/tegra/clk-pll.c val |= PLLE_BASE_ENABLE; val 2453 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 2460 drivers/clk/tegra/clk-pll.c val = pll_readl(PLLE_SS_CTRL, pll); val 2461 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); val 2462 drivers/clk/tegra/clk-pll.c val &= ~PLLE_SS_COEFFICIENTS_MASK; val 2463 drivers/clk/tegra/clk-pll.c val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210; val 2464 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); val 2465 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); val 2466 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); val 2468 drivers/clk/tegra/clk-pll.c val &= ~PLLE_SS_CNTL_INTERP_RESET; val 2469 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); val 2472 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 2473 drivers/clk/tegra/clk-pll.c val &= ~PLLE_MISC_IDDQ_SW_CTRL; val 2474 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 2476 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); val 2477 drivers/clk/tegra/clk-pll.c val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); val 2478 drivers/clk/tegra/clk-pll.c val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); val 2479 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); val 2481 drivers/clk/tegra/clk-pll.c val |= PLLE_AUX_SEQ_ENABLE; val 2482 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); val 2495 drivers/clk/tegra/clk-pll.c u32 val; val 2501 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); val 2502 drivers/clk/tegra/clk-pll.c if (val & PLLE_AUX_SEQ_ENABLE) val 2505 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2506 drivers/clk/tegra/clk-pll.c val &= ~PLLE_BASE_ENABLE; val 2507 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); val 2509 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); val 2510 drivers/clk/tegra/clk-pll.c val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL; val 2511 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); val 2513 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); val 2514 drivers/clk/tegra/clk-pll.c val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; val 2515 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); val 2538 drivers/clk/tegra/clk-pll.c u32 val, val_aux; val 2546 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); val 2549 drivers/clk/tegra/clk-pll.c if (val & PLLE_BASE_ENABLE) { val 2619 drivers/clk/tegra/clk-pll.c u32 val; val 2631 drivers/clk/tegra/clk-pll.c val = readl_relaxed(clk_base + pll_params->base_reg); val 2632 drivers/clk/tegra/clk-pll.c if (val & PLLSS_REF_SRC_SEL_MASK) { val 26 drivers/clk/tegra/clk-sdmmc-mux.c #define get_div_field(val) ((val) & DIV_MASK) val 27 drivers/clk/tegra/clk-sdmmc-mux.c #define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT) val 45 drivers/clk/tegra/clk-sdmmc-mux.c u32 src, val; val 50 drivers/clk/tegra/clk-sdmmc-mux.c val = readl_relaxed(sdmmc_mux->reg); val 51 drivers/clk/tegra/clk-sdmmc-mux.c src = get_mux_field(val); val 52 drivers/clk/tegra/clk-sdmmc-mux.c if (get_div_field(val)) val 70 drivers/clk/tegra/clk-sdmmc-mux.c u32 val; val 73 drivers/clk/tegra/clk-sdmmc-mux.c val = readl_relaxed(sdmmc_mux->reg); val 74 drivers/clk/tegra/clk-sdmmc-mux.c if (get_div_field(val)) val 79 drivers/clk/tegra/clk-sdmmc-mux.c val &= ~MUX_MASK; val 80 drivers/clk/tegra/clk-sdmmc-mux.c val |= index << MUX_SHIFT; val 82 drivers/clk/tegra/clk-sdmmc-mux.c writel(val, sdmmc_mux->reg); val 91 drivers/clk/tegra/clk-sdmmc-mux.c u32 val; val 95 drivers/clk/tegra/clk-sdmmc-mux.c val = readl_relaxed(sdmmc_mux->reg); val 96 drivers/clk/tegra/clk-sdmmc-mux.c div = get_div_field(val); val 139 drivers/clk/tegra/clk-sdmmc-mux.c u32 val; val 155 drivers/clk/tegra/clk-sdmmc-mux.c val = src << MUX_SHIFT; val 156 drivers/clk/tegra/clk-sdmmc-mux.c val |= div; val 157 drivers/clk/tegra/clk-sdmmc-mux.c writel(val, sdmmc_mux->reg); val 34 drivers/clk/tegra/clk-super.c u32 val, state; val 37 drivers/clk/tegra/clk-super.c val = readl_relaxed(mux->reg); val 39 drivers/clk/tegra/clk-super.c state = val & SUPER_STATE_MASK; val 47 drivers/clk/tegra/clk-super.c source = (val >> shift) & super_state_to_src_mask(mux); val 53 drivers/clk/tegra/clk-super.c if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && val 63 drivers/clk/tegra/clk-super.c u32 val, state; val 71 drivers/clk/tegra/clk-super.c val = readl_relaxed(mux->reg); val 72 drivers/clk/tegra/clk-super.c state = val & SUPER_STATE_MASK; val 93 drivers/clk/tegra/clk-super.c val ^= SUPER_LP_DIV2_BYPASS; val 94 drivers/clk/tegra/clk-super.c writel_relaxed(val, mux->reg); val 100 drivers/clk/tegra/clk-super.c val &= ~((super_state_to_src_mask(mux)) << shift); val 101 drivers/clk/tegra/clk-super.c val |= (index & (super_state_to_src_mask(mux))) << shift; val 103 drivers/clk/tegra/clk-super.c writel_relaxed(val, mux->reg); val 28 drivers/clk/tegra/clk-tegra-fixed.c u32 val, pll_ref_div; val 31 drivers/clk/tegra/clk-tegra-fixed.c val = readl_relaxed(clk_base + OSC_CTRL); val 32 drivers/clk/tegra/clk-tegra-fixed.c osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; val 55 drivers/clk/tegra/clk-tegra-fixed.c val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; val 56 drivers/clk/tegra/clk-tegra-fixed.c pll_ref_div = 1 << val; val 627 drivers/clk/tegra/clk-tegra114.c { .val = 0, .div = 1 }, val 628 drivers/clk/tegra/clk-tegra114.c { .val = 1, .div = 2 }, val 629 drivers/clk/tegra/clk-tegra114.c { .val = 2, .div = 3 }, val 630 drivers/clk/tegra/clk-tegra114.c { .val = 3, .div = 4 }, val 631 drivers/clk/tegra/clk-tegra114.c { .val = 4, .div = 5 }, val 632 drivers/clk/tegra/clk-tegra114.c { .val = 5, .div = 6 }, val 633 drivers/clk/tegra/clk-tegra114.c { .val = 0, .div = 0 }, val 473 drivers/clk/tegra/clk-tegra124.c { .val = 0, .div = 1 }, val 474 drivers/clk/tegra/clk-tegra124.c { .val = 1, .div = 2 }, val 475 drivers/clk/tegra/clk-tegra124.c { .val = 2, .div = 3 }, val 476 drivers/clk/tegra/clk-tegra124.c { .val = 3, .div = 4 }, val 477 drivers/clk/tegra/clk-tegra124.c { .val = 4, .div = 5 }, val 478 drivers/clk/tegra/clk-tegra124.c { .val = 5, .div = 6 }, val 479 drivers/clk/tegra/clk-tegra124.c { .val = 0, .div = 0 }, val 489 drivers/clk/tegra/clk-tegra210.c u32 val; val 491 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); val 492 drivers/clk/tegra/clk-tegra210.c val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | val 494 drivers/clk/tegra/clk-tegra210.c val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | val 496 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); val 502 drivers/clk/tegra/clk-tegra210.c u32 val; val 504 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); val 505 drivers/clk/tegra/clk-tegra210.c val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; val 506 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); val 512 drivers/clk/tegra/clk-tegra210.c u32 val; val 514 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + SATA_PLL_CFG0); val 515 drivers/clk/tegra/clk-tegra210.c val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; val 516 drivers/clk/tegra/clk-tegra210.c val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET | val 518 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + SATA_PLL_CFG0); val 524 drivers/clk/tegra/clk-tegra210.c u32 val; val 526 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + SATA_PLL_CFG0); val 527 drivers/clk/tegra/clk-tegra210.c val |= SATA_PLL_CFG0_SEQ_ENABLE; val 528 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + SATA_PLL_CFG0); val 534 drivers/clk/tegra/clk-tegra210.c u32 val; val 536 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + SATA_PLL_CFG0); val 538 drivers/clk/tegra/clk-tegra210.c val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; val 539 drivers/clk/tegra/clk-tegra210.c val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; val 540 drivers/clk/tegra/clk-tegra210.c val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; val 541 drivers/clk/tegra/clk-tegra210.c val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; val 543 drivers/clk/tegra/clk-tegra210.c val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; val 544 drivers/clk/tegra/clk-tegra210.c val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; val 545 drivers/clk/tegra/clk-tegra210.c val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; val 546 drivers/clk/tegra/clk-tegra210.c val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; val 548 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + SATA_PLL_CFG0); val 554 drivers/clk/tegra/clk-tegra210.c u32 val; val 556 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + mbist->lvl2_offset); val 557 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); val 559 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + mbist->lvl2_offset); val 608 drivers/clk/tegra/clk-tegra210.c u32 ovre, val; val 614 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); val 615 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24), val 619 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); val 757 drivers/clk/tegra/clk-tegra210.c u32 val = readl_relaxed(clk_base + plla->params->base_reg); val 761 drivers/clk/tegra/clk-tegra210.c if (val & PLL_ENABLE) { val 766 drivers/clk/tegra/clk-tegra210.c if (val & PLLA_BASE_IDDQ) { val 773 drivers/clk/tegra/clk-tegra210.c val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */ val 775 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, plla->params, 0, val, val 778 drivers/clk/tegra/clk-tegra210.c val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */ val 779 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, plla->params, 2, val, val 783 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); val 784 drivers/clk/tegra/clk-tegra210.c val &= ~mask; val 785 drivers/clk/tegra/clk-tegra210.c val |= PLLA_MISC0_DEFAULT_VALUE & mask; val 786 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); val 793 drivers/clk/tegra/clk-tegra210.c val |= PLLA_BASE_IDDQ; val 794 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + plla->params->base_reg); val 808 drivers/clk/tegra/clk-tegra210.c u32 val; val 820 drivers/clk/tegra/clk-tegra210.c val = PLLD_MISC1_DEFAULT_VALUE; val 822 drivers/clk/tegra/clk-tegra210.c val, PLLD_MISC1_WRITE_MASK); val 825 drivers/clk/tegra/clk-tegra210.c val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ); val 828 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, plld->params, 0, val, val 836 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); val 837 drivers/clk/tegra/clk-tegra210.c val &= ~mask; val 838 drivers/clk/tegra/clk-tegra210.c val |= PLLD_MISC0_DEFAULT_VALUE & mask; val 839 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); val 845 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); val 846 drivers/clk/tegra/clk-tegra210.c val &= PLLD_MISC0_DSI_CLKENABLE; val 847 drivers/clk/tegra/clk-tegra210.c val |= PLLD_MISC0_DEFAULT_VALUE; val 849 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); val 863 drivers/clk/tegra/clk-tegra210.c u32 val = readl_relaxed(clk_base + plldss->params->base_reg); val 867 drivers/clk/tegra/clk-tegra210.c if (val & PLL_ENABLE) { val 873 drivers/clk/tegra/clk-tegra210.c if (val & PLLDSS_BASE_IDDQ) { val 911 drivers/clk/tegra/clk-tegra210.c if (val & PLLDSS_BASE_LOCK_OVERRIDE) { val 912 drivers/clk/tegra/clk-tegra210.c val &= ~PLLDSS_BASE_LOCK_OVERRIDE; val 913 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + val 917 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); val 918 drivers/clk/tegra/clk-tegra210.c val &= ~PLLDSS_MISC0_LOCK_ENABLE; val 919 drivers/clk/tegra/clk-tegra210.c val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE; val 920 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); val 927 drivers/clk/tegra/clk-tegra210.c val |= PLLDSS_BASE_IDDQ; val 928 drivers/clk/tegra/clk-tegra210.c val &= ~PLLDSS_BASE_LOCK_OVERRIDE; val 929 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + plldss->params->base_reg); val 982 drivers/clk/tegra/clk-tegra210.c u32 val = readl_relaxed(clk_base + pllre->params->base_reg); val 986 drivers/clk/tegra/clk-tegra210.c if (val & PLL_ENABLE) { val 991 drivers/clk/tegra/clk-tegra210.c val &= PLLRE_BASE_DEFAULT_MASK; val 992 drivers/clk/tegra/clk-tegra210.c if (val != PLLRE_BASE_DEFAULT_VALUE) { val 994 drivers/clk/tegra/clk-tegra210.c val, PLLRE_BASE_DEFAULT_VALUE); val 1001 drivers/clk/tegra/clk-tegra210.c val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ); val 1003 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pllre->params, 0, val, val 1007 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); val 1008 drivers/clk/tegra/clk-tegra210.c if (val & PLLRE_MISC0_IDDQ) val 1012 drivers/clk/tegra/clk-tegra210.c val &= ~mask; val 1013 drivers/clk/tegra/clk-tegra210.c val |= PLLRE_MISC0_DEFAULT_VALUE & mask; val 1014 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); val 1024 drivers/clk/tegra/clk-tegra210.c val &= ~PLLRE_BASE_DEFAULT_MASK; val 1025 drivers/clk/tegra/clk-tegra210.c val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK; val 1026 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllre->params->base_reg); val 1099 drivers/clk/tegra/clk-tegra210.c u32 val; val 1106 drivers/clk/tegra/clk-tegra210.c val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) & val 1108 drivers/clk/tegra/clk-tegra210.c val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT; val 1109 drivers/clk/tegra/clk-tegra210.c val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; val 1122 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); val 1125 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); val 1126 drivers/clk/tegra/clk-tegra210.c val &= ~PLLX_MISC0_LOCK_ENABLE; val 1127 drivers/clk/tegra/clk-tegra210.c val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE; val 1128 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); val 1143 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); val 1160 drivers/clk/tegra/clk-tegra210.c u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); val 1164 drivers/clk/tegra/clk-tegra210.c if (val & PLL_ENABLE) { val 1170 drivers/clk/tegra/clk-tegra210.c val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ); val 1172 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pllmb->params, 0, val, val 1178 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); val 1179 drivers/clk/tegra/clk-tegra210.c val &= ~mask; val 1180 drivers/clk/tegra/clk-tegra210.c val |= PLLMB_MISC1_DEFAULT_VALUE & mask; val 1181 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); val 1201 drivers/clk/tegra/clk-tegra210.c u32 val, mask; val 1204 drivers/clk/tegra/clk-tegra210.c val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ); val 1208 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 0, val, val 1212 drivers/clk/tegra/clk-tegra210.c val = PLLP_MISC1_DEFAULT_VALUE; val 1214 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 1, val, val 1221 drivers/clk/tegra/clk-tegra210.c u32 val = readl_relaxed(clk_base + pllp->params->base_reg); val 1225 drivers/clk/tegra/clk-tegra210.c if (val & PLL_ENABLE) { val 1236 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); val 1238 drivers/clk/tegra/clk-tegra210.c val &= ~mask; val 1239 drivers/clk/tegra/clk-tegra210.c val |= PLLP_MISC0_DEFAULT_VALUE & mask; val 1240 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); val 1251 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); val 1253 drivers/clk/tegra/clk-tegra210.c val &= mask; val 1254 drivers/clk/tegra/clk-tegra210.c val |= ~mask & PLLP_MISC1_DEFAULT_VALUE; val 1255 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); val 1268 drivers/clk/tegra/clk-tegra210.c u32 val, mask; val 1271 drivers/clk/tegra/clk-tegra210.c val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ); val 1273 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, params, 0, val, val 1276 drivers/clk/tegra/clk-tegra210.c val = PLLU_MISC1_DEFAULT_VALUE; val 1278 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, params, 1, val, val 1284 drivers/clk/tegra/clk-tegra210.c u32 val = readl_relaxed(clk_base + pllu->base_reg); val 1288 drivers/clk/tegra/clk-tegra210.c if (val & PLL_ENABLE) { val 1299 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); val 1300 drivers/clk/tegra/clk-tegra210.c val &= ~PLLU_MISC0_LOCK_ENABLE; val 1301 drivers/clk/tegra/clk-tegra210.c val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE; val 1302 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); val 1304 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); val 1305 drivers/clk/tegra/clk-tegra210.c val &= ~PLLU_MISC1_LOCK_OVERRIDE; val 1306 drivers/clk/tegra/clk-tegra210.c val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE; val 1307 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); val 1340 drivers/clk/tegra/clk-tegra210.c u32 val = 0; val 1344 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + reg); val 1345 drivers/clk/tegra/clk-tegra210.c if ((val & mask) == mask) { val 1356 drivers/clk/tegra/clk-tegra210.c u32 val, base, ndiv_new_mask; val 1361 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); val 1362 drivers/clk/tegra/clk-tegra210.c val &= (~ndiv_new_mask); val 1363 drivers/clk/tegra/clk-tegra210.c val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT; val 1364 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); val 1367 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); val 1368 drivers/clk/tegra/clk-tegra210.c val |= PLLX_MISC2_EN_DYNRAMP; val 1369 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); val 1381 drivers/clk/tegra/clk-tegra210.c val &= ~PLLX_MISC2_EN_DYNRAMP; val 1382 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); val 1743 drivers/clk/tegra/clk-tegra210.c { .val = 0, .div = 1 }, val 1744 drivers/clk/tegra/clk-tegra210.c { .val = 1, .div = 2 }, val 1745 drivers/clk/tegra/clk-tegra210.c { .val = 2, .div = 3 }, val 1746 drivers/clk/tegra/clk-tegra210.c { .val = 3, .div = 4 }, val 1747 drivers/clk/tegra/clk-tegra210.c { .val = 4, .div = 5 }, val 1748 drivers/clk/tegra/clk-tegra210.c { .val = 5, .div = 6 }, val 1749 drivers/clk/tegra/clk-tegra210.c { .val = 6, .div = 8 }, val 1750 drivers/clk/tegra/clk-tegra210.c { .val = 7, .div = 10 }, val 1751 drivers/clk/tegra/clk-tegra210.c { .val = 8, .div = 12 }, val 1752 drivers/clk/tegra/clk-tegra210.c { .val = 9, .div = 16 }, val 1753 drivers/clk/tegra/clk-tegra210.c { .val = 10, .div = 12 }, val 1754 drivers/clk/tegra/clk-tegra210.c { .val = 11, .div = 16 }, val 1755 drivers/clk/tegra/clk-tegra210.c { .val = 12, .div = 20 }, val 1756 drivers/clk/tegra/clk-tegra210.c { .val = 13, .div = 24 }, val 1757 drivers/clk/tegra/clk-tegra210.c { .val = 14, .div = 32 }, val 1758 drivers/clk/tegra/clk-tegra210.c { .val = 0, .div = 0 }, val 316 drivers/clk/ti/apll.c static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val) val 323 drivers/clk/ti/apll.c v |= val << __ffs(ad->autoidle_mask); val 352 drivers/clk/ti/apll.c u32 val; val 377 drivers/clk/ti/apll.c if (of_property_read_u32(node, "ti,clock-frequency", &val)) { val 381 drivers/clk/ti/apll.c clk_hw->fixed_rate = val; val 383 drivers/clk/ti/apll.c if (of_property_read_u32(node, "ti,bit-shift", &val)) { val 388 drivers/clk/ti/apll.c clk_hw->enable_bit = val; val 389 drivers/clk/ti/apll.c ad->enable_mask = 0x3 << val; val 390 drivers/clk/ti/apll.c ad->autoidle_mask = 0x3 << val; val 392 drivers/clk/ti/apll.c if (of_property_read_u32(node, "ti,idlest-shift", &val)) { val 397 drivers/clk/ti/apll.c ad->idlest_mask = 1 << val; val 117 drivers/clk/ti/autoidle.c u32 val; val 119 drivers/clk/ti/autoidle.c val = ti_clk_ll_ops->clk_readl(&clk->reg); val 122 drivers/clk/ti/autoidle.c val &= ~(1 << clk->shift); val 124 drivers/clk/ti/autoidle.c val |= (1 << clk->shift); val 126 drivers/clk/ti/autoidle.c ti_clk_ll_ops->clk_writel(val, &clk->reg); val 131 drivers/clk/ti/autoidle.c u32 val; val 133 drivers/clk/ti/autoidle.c val = ti_clk_ll_ops->clk_readl(&clk->reg); val 136 drivers/clk/ti/autoidle.c val |= (1 << clk->shift); val 138 drivers/clk/ti/autoidle.c val &= ~(1 << clk->shift); val 140 drivers/clk/ti/autoidle.c ti_clk_ll_ops->clk_writel(val, &clk->reg); val 70 drivers/clk/ti/clk-dra7-atl.c u32 val) val 72 drivers/clk/ti/clk-dra7-atl.c __raw_writel(val, cinfo->iobase + reg); val 48 drivers/clk/ti/clk.c static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg) val 53 drivers/clk/ti/clk.c writel_relaxed(val, reg->ptr); val 55 drivers/clk/ti/clk.c regmap_write(io->regmap, reg->offset, val); val 57 drivers/clk/ti/clk.c writel_relaxed(val, io->mem + reg->offset); val 60 drivers/clk/ti/clk.c static void _clk_rmw(u32 val, u32 mask, void __iomem *ptr) val 66 drivers/clk/ti/clk.c v |= val; val 70 drivers/clk/ti/clk.c static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg) val 75 drivers/clk/ti/clk.c _clk_rmw(val, mask, reg->ptr); val 77 drivers/clk/ti/clk.c regmap_update_bits(io->regmap, reg->offset, mask, val); val 79 drivers/clk/ti/clk.c _clk_rmw(val, mask, io->mem + reg->offset); val 85 drivers/clk/ti/clk.c u32 val; val 89 drivers/clk/ti/clk.c val = readl_relaxed(reg->ptr); val 91 drivers/clk/ti/clk.c regmap_read(io->regmap, reg->offset, &val); val 93 drivers/clk/ti/clk.c val = readl_relaxed(io->mem + reg->offset); val 95 drivers/clk/ti/clk.c return val; val 266 drivers/clk/ti/clk.c u32 val; val 281 drivers/clk/ti/clk.c if (of_property_read_u32_index(node, "reg", index, &val)) { val 286 drivers/clk/ti/clk.c reg->offset = val; val 69 drivers/clk/ti/clkctrl.c static u32 _omap4_idlest(u32 val) val 71 drivers/clk/ti/clkctrl.c val &= OMAP4_IDLEST_MASK; val 72 drivers/clk/ti/clkctrl.c val >>= OMAP4_IDLEST_SHIFT; val 74 drivers/clk/ti/clkctrl.c return val; val 77 drivers/clk/ti/clkctrl.c static bool _omap4_is_idle(u32 val) val 79 drivers/clk/ti/clkctrl.c val = _omap4_idlest(val); val 81 drivers/clk/ti/clkctrl.c return val == CLKCTRL_IDLEST_DISABLED; val 84 drivers/clk/ti/clkctrl.c static bool _omap4_is_ready(u32 val) val 86 drivers/clk/ti/clkctrl.c val = _omap4_idlest(val); val 88 drivers/clk/ti/clkctrl.c return val == CLKCTRL_IDLEST_FUNCTIONAL || val 89 drivers/clk/ti/clkctrl.c val == CLKCTRL_IDLEST_INTERFACE_IDLE; val 137 drivers/clk/ti/clkctrl.c u32 val; val 155 drivers/clk/ti/clkctrl.c val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); val 157 drivers/clk/ti/clkctrl.c val &= ~OMAP4_MODULEMODE_MASK; val 158 drivers/clk/ti/clkctrl.c val |= clk->enable_bit; val 160 drivers/clk/ti/clkctrl.c ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); val 179 drivers/clk/ti/clkctrl.c u32 val; val 185 drivers/clk/ti/clkctrl.c val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); val 187 drivers/clk/ti/clkctrl.c val &= ~OMAP4_MODULEMODE_MASK; val 189 drivers/clk/ti/clkctrl.c ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); val 211 drivers/clk/ti/clkctrl.c u32 val; val 213 drivers/clk/ti/clkctrl.c val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); val 215 drivers/clk/ti/clkctrl.c if (val & clk->enable_bit) val 183 drivers/clk/ti/clkt_dpll.c u8 mask, val; val 193 drivers/clk/ti/clkt_dpll.c val = __ffs(mask); val 194 drivers/clk/ti/clkt_dpll.c mask ^= (1 << val); val 195 drivers/clk/ti/clkt_dpll.c if (v == val) val 54 drivers/clk/ti/divider.c unsigned int val) val 59 drivers/clk/ti/divider.c if (clkt->val == val) val 64 drivers/clk/ti/divider.c static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) val 67 drivers/clk/ti/divider.c return val; val 69 drivers/clk/ti/divider.c return 1 << val; val 71 drivers/clk/ti/divider.c return _get_table_div(divider->table, val); val 72 drivers/clk/ti/divider.c return val + 1; val 82 drivers/clk/ti/divider.c return clkt->val; val 101 drivers/clk/ti/divider.c unsigned int div, val; val 103 drivers/clk/ti/divider.c val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; val 104 drivers/clk/ti/divider.c val &= div_mask(divider); val 106 drivers/clk/ti/divider.c div = _get_div(divider, val); val 244 drivers/clk/ti/divider.c u32 val; val 258 drivers/clk/ti/divider.c val = div_mask(divider) << (divider->shift + 16); val 260 drivers/clk/ti/divider.c val = ti_clk_ll_ops->clk_readl(÷r->reg); val 261 drivers/clk/ti/divider.c val &= ~(div_mask(divider) << divider->shift); val 263 drivers/clk/ti/divider.c val |= value << divider->shift; val 264 drivers/clk/ti/divider.c ti_clk_ll_ops->clk_writel(val, ÷r->reg); val 280 drivers/clk/ti/divider.c u32 val; val 282 drivers/clk/ti/divider.c val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; val 283 drivers/clk/ti/divider.c divider->context = val & div_mask(divider); val 297 drivers/clk/ti/divider.c u32 val; val 299 drivers/clk/ti/divider.c val = ti_clk_ll_ops->clk_readl(÷r->reg); val 300 drivers/clk/ti/divider.c val &= ~(div_mask(divider) << divider->shift); val 301 drivers/clk/ti/divider.c val |= divider->context << divider->shift; val 302 drivers/clk/ti/divider.c ti_clk_ll_ops->clk_writel(val, ÷r->reg); val 366 drivers/clk/ti/divider.c u32 val; val 373 drivers/clk/ti/divider.c val = 1; val 375 drivers/clk/ti/divider.c val = 0; val 384 drivers/clk/ti/divider.c val++; val 387 drivers/clk/ti/divider.c *width = fls(val); val 417 drivers/clk/ti/divider.c tmp[valid_div].val = i; val 433 drivers/clk/ti/divider.c u32 val; val 449 drivers/clk/ti/divider.c of_property_read_u32_index(node, "ti,dividers", i, &val); val 450 drivers/clk/ti/divider.c if (val) val 467 drivers/clk/ti/divider.c of_property_read_u32_index(node, "ti,dividers", i, &val); val 468 drivers/clk/ti/divider.c if (val) { val 469 drivers/clk/ti/divider.c table[valid_div].div = val; val 470 drivers/clk/ti/divider.c table[valid_div].val = i; val 484 drivers/clk/ti/divider.c u32 val = 0; val 499 drivers/clk/ti/divider.c val = 1; val 508 drivers/clk/ti/divider.c val++; val 514 drivers/clk/ti/divider.c val = table[div].val; val 519 drivers/clk/ti/divider.c return fls(val); val 526 drivers/clk/ti/divider.c u32 val; val 533 drivers/clk/ti/divider.c if (!of_property_read_u32(node, "ti,bit-shift", &val)) val 534 drivers/clk/ti/divider.c *shift = val; val 539 drivers/clk/ti/divider.c if (!of_property_read_u32(node, "ti,latch-bit", &val)) val 540 drivers/clk/ti/divider.c *latch = val; val 608 drivers/clk/ti/divider.c u32 val; val 614 drivers/clk/ti/divider.c if (ti_clk_divider_populate(node, &div->reg, &div->table, &val, val 142 drivers/clk/ti/gate.c u32 val; val 150 drivers/clk/ti/gate.c if (!of_property_read_u32(node, "ti,bit-shift", &val)) val 151 drivers/clk/ti/gate.c enable_bit = val; val 179 drivers/clk/ti/gate.c u32 val = 0; val 188 drivers/clk/ti/gate.c of_property_read_u32(node, "ti,bit-shift", &val); val 190 drivers/clk/ti/gate.c gate->enable_bit = val; val 75 drivers/clk/ti/interface.c u32 val; val 80 drivers/clk/ti/interface.c if (!of_property_read_u32(node, "ti,bit-shift", &val)) val 81 drivers/clk/ti/interface.c enable_bit = val; val 33 drivers/clk/ti/mux.c u32 val; val 42 drivers/clk/ti/mux.c val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; val 43 drivers/clk/ti/mux.c val &= mux->mask; val 49 drivers/clk/ti/mux.c if (mux->table[i] == val) val 54 drivers/clk/ti/mux.c if (val && (mux->flags & CLK_MUX_INDEX_BIT)) val 55 drivers/clk/ti/mux.c val = ffs(val) - 1; val 57 drivers/clk/ti/mux.c if (val && (mux->flags & CLK_MUX_INDEX_ONE)) val 58 drivers/clk/ti/mux.c val--; val 60 drivers/clk/ti/mux.c if (val >= num_parents) val 63 drivers/clk/ti/mux.c return val; val 69 drivers/clk/ti/mux.c u32 val; val 82 drivers/clk/ti/mux.c val = mux->mask << (mux->shift + 16); val 84 drivers/clk/ti/mux.c val = ti_clk_ll_ops->clk_readl(&mux->reg); val 85 drivers/clk/ti/mux.c val &= ~(mux->mask << mux->shift); val 87 drivers/clk/ti/mux.c val |= index << mux->shift; val 88 drivers/clk/ti/mux.c ti_clk_ll_ops->clk_writel(val, &mux->reg); val 261 drivers/clk/ti/mux.c u32 val; val 270 drivers/clk/ti/mux.c if (!of_property_read_u32(node, "ti,bit-shift", &val)) val 271 drivers/clk/ti/mux.c mux->shift = val; val 32 drivers/clk/uniphier/clk-uniphier-cpugear.c unsigned int val; val 49 drivers/clk/uniphier/clk-uniphier-cpugear.c val, !(val & UNIPHIER_CLK_CPUGEAR_UPD_BIT), val 58 drivers/clk/uniphier/clk-uniphier-cpugear.c unsigned int val; val 61 drivers/clk/uniphier/clk-uniphier-cpugear.c gear->regbase + UNIPHIER_CLK_CPUGEAR_STAT, &val); val 65 drivers/clk/uniphier/clk-uniphier-cpugear.c val &= gear->mask; val 67 drivers/clk/uniphier/clk-uniphier-cpugear.c return val < num_parents ? val : -EINVAL; val 45 drivers/clk/uniphier/clk-uniphier-gate.c unsigned int val; val 47 drivers/clk/uniphier/clk-uniphier-gate.c if (regmap_read(gate->regmap, gate->reg, &val) < 0) val 50 drivers/clk/uniphier/clk-uniphier-gate.c return !!(val & BIT(gate->bit)); val 36 drivers/clk/uniphier/clk-uniphier-mux.c unsigned int val; val 39 drivers/clk/uniphier/clk-uniphier-mux.c ret = regmap_read(mux->regmap, mux->reg, &val); val 44 drivers/clk/uniphier/clk-uniphier-mux.c if ((mux->masks[i] & val) == mux->vals[i]) val 76 drivers/clk/versatile/clk-icst.c u32 val; val 79 drivers/clk/versatile/clk-icst.c ret = regmap_read(icst->map, icst->vcoreg_off, &val); val 92 drivers/clk/versatile/clk-icst.c vco->v = val & INTEGRATOR_AP_CM_BITS; val 107 drivers/clk/versatile/clk-icst.c vco->v = val & INTEGRATOR_AP_SYS_BITS; val 122 drivers/clk/versatile/clk-icst.c bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ); val 139 drivers/clk/versatile/clk-icst.c vco->v = val & 0xFF; val 141 drivers/clk/versatile/clk-icst.c vco->s = (val >> 8) & 7; val 146 drivers/clk/versatile/clk-icst.c vco->v = (val >> 12) & 0xFF; val 148 drivers/clk/versatile/clk-icst.c vco->s = (val >> 20) & 7; val 152 drivers/clk/versatile/clk-icst.c vco->v = val & 0x1ff; val 153 drivers/clk/versatile/clk-icst.c vco->r = (val >> 9) & 0x7f; val 154 drivers/clk/versatile/clk-icst.c vco->s = (val >> 16) & 03; val 166 drivers/clk/versatile/clk-icst.c u32 val; val 173 drivers/clk/versatile/clk-icst.c val = vco.v & 0xFF; val 183 drivers/clk/versatile/clk-icst.c val = vco.v & 0xFF; val 193 drivers/clk/versatile/clk-icst.c val = (vco.v & 0xFF) | vco.s << 8; val 201 drivers/clk/versatile/clk-icst.c val = ((vco.v & 0xFF) << 12) | (vco.s << 20); val 210 drivers/clk/versatile/clk-icst.c val = vco.v | (vco.r << 9) | (vco.s << 16); val 214 drivers/clk/versatile/clk-icst.c pr_debug("ICST: new val = 0x%08x\n", val); val 220 drivers/clk/versatile/clk-icst.c ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val); val 306 drivers/clk/versatile/clk-icst.c unsigned int val; val 310 drivers/clk/versatile/clk-icst.c val = 0; val 312 drivers/clk/versatile/clk-icst.c val = INTEGRATOR_AP_PCI_25_33_MHZ; val 324 drivers/clk/versatile/clk-icst.c val); val 38 drivers/clk/versatile/clk-sp810.c u32 val = readl(timerclken->sp810->base + SCCTRL); val 40 drivers/clk/versatile/clk-sp810.c return !!(val & (1 << SCCTRL_TIMERENnSEL_SHIFT(timerclken->channel))); val 47 drivers/clk/versatile/clk-sp810.c u32 val, shift = SCCTRL_TIMERENnSEL_SHIFT(timerclken->channel); val 55 drivers/clk/versatile/clk-sp810.c val = readl(sp810->base + SCCTRL); val 56 drivers/clk/versatile/clk-sp810.c val &= ~(1 << shift); val 57 drivers/clk/versatile/clk-sp810.c val |= index << shift; val 58 drivers/clk/versatile/clk-sp810.c writel(val, sp810->base + SCCTRL); val 92 drivers/clk/x86/clk-pmc-atom.c static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val) val 100 drivers/clk/x86/clk-pmc-atom.c tmp = (tmp & ~mask) | (val & mask); val 62 drivers/clk/zte/clk-zx296702.c { .val = 1, .div = 2, }, val 63 drivers/clk/zte/clk-zx296702.c { .val = 3, .div = 4, }, val 68 drivers/clk/zte/clk-zx296702.c { .val = 0, .div = 1, }, val 69 drivers/clk/zte/clk-zx296702.c { .val = 1, .div = 2, }, val 70 drivers/clk/zte/clk-zx296702.c { .val = 3, .div = 4, }, val 75 drivers/clk/zte/clk-zx296702.c { .val = 0, .div = 1, }, val 76 drivers/clk/zte/clk-zx296702.c { .val = 1, .div = 2, }, val 77 drivers/clk/zte/clk-zx296702.c { .val = 3, .div = 4, }, val 78 drivers/clk/zte/clk-zx296702.c { .val = 5, .div = 6, }, val 79 drivers/clk/zte/clk-zx296702.c { .val = 7, .div = 8, }, val 452 drivers/clk/zte/clk-zx296718.c { .val = 1, .div = 2, }, val 453 drivers/clk/zte/clk-zx296718.c { .val = 3, .div = 4, }, val 641 drivers/clk/zte/clk-zx296718.c { .val = 0, .div = 1, }, val 642 drivers/clk/zte/clk-zx296718.c { .val = 1, .div = 2, }, val 643 drivers/clk/zte/clk-zx296718.c { .val = 3, .div = 4, }, val 644 drivers/clk/zte/clk-zx296718.c { .val = 5, .div = 6, }, val 645 drivers/clk/zte/clk-zx296718.c { .val = 7, .div = 8, }, val 646 drivers/clk/zte/clk-zx296718.c { .val = 9, .div = 10, }, val 647 drivers/clk/zte/clk-zx296718.c { .val = 11, .div = 12, }, val 648 drivers/clk/zte/clk-zx296718.c { .val = 13, .div = 14, }, val 649 drivers/clk/zte/clk-zx296718.c { .val = 15, .div = 16, }, val 653 drivers/clk/zte/clk-zx296718.c { .val = 0, .div = 1, }, val 654 drivers/clk/zte/clk-zx296718.c { .val = 1, .div = 2, }, val 655 drivers/clk/zte/clk-zx296718.c { .val = 2, .div = 3, }, val 656 drivers/clk/zte/clk-zx296718.c { .val = 3, .div = 4, }, val 657 drivers/clk/zte/clk-zx296718.c { .val = 4, .div = 5, }, val 658 drivers/clk/zte/clk-zx296718.c { .val = 5, .div = 6, }, val 659 drivers/clk/zte/clk-zx296718.c { .val = 6, .div = 7, }, val 660 drivers/clk/zte/clk-zx296718.c { .val = 7, .div = 8, }, val 661 drivers/clk/zte/clk-zx296718.c { .val = 8, .div = 9, }, val 662 drivers/clk/zte/clk-zx296718.c { .val = 9, .div = 10, }, val 663 drivers/clk/zte/clk-zx296718.c { .val = 10, .div = 11, }, val 664 drivers/clk/zte/clk-zx296718.c { .val = 11, .div = 12, }, val 665 drivers/clk/zte/clk-zx296718.c { .val = 12, .div = 13, }, val 666 drivers/clk/zte/clk-zx296718.c { .val = 13, .div = 14, }, val 667 drivers/clk/zte/clk-zx296718.c { .val = 14, .div = 15, }, val 668 drivers/clk/zte/clk-zx296718.c { .val = 15, .div = 16, }, val 420 drivers/clk/zte/clk.c unsigned int val; val 428 drivers/clk/zte/clk.c val = readl_relaxed(zx_audio_div->reg_base + 0x4); val 429 drivers/clk/zte/clk.c val &= ~0xffff; val 430 drivers/clk/zte/clk.c val |= divt.int_reg | CLK_AUDIO_DIV_INT_FRAC_RE; val 431 drivers/clk/zte/clk.c writel_relaxed(val, zx_audio_div->reg_base + 0x4); val 435 drivers/clk/zte/clk.c val = readl_relaxed(zx_audio_div->reg_base + 0x4); val 436 drivers/clk/zte/clk.c val &= ~CLK_AUDIO_DIV_INT_FRAC_RE; val 437 drivers/clk/zte/clk.c writel_relaxed(val, zx_audio_div->reg_base + 0x4); val 48 drivers/clk/zynqmp/clk-mux-zynqmp.c u32 val; val 52 drivers/clk/zynqmp/clk-mux-zynqmp.c ret = eemi_ops->clock_getparent(clk_id, &val); val 58 drivers/clk/zynqmp/clk-mux-zynqmp.c return val; val 88 drivers/clocksource/arm_arch_timer.c void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, val 95 drivers/clocksource/arm_arch_timer.c writel_relaxed(val, timer->base + CNTP_CTL); val 98 drivers/clocksource/arm_arch_timer.c writel_relaxed(val, timer->base + CNTP_TVAL); val 105 drivers/clocksource/arm_arch_timer.c writel_relaxed(val, timer->base + CNTV_CTL); val 108 drivers/clocksource/arm_arch_timer.c writel_relaxed(val, timer->base + CNTV_TVAL); val 112 drivers/clocksource/arm_arch_timer.c arch_timer_reg_write_cp15(access, reg, val); val 120 drivers/clocksource/arm_arch_timer.c u32 val; val 126 drivers/clocksource/arm_arch_timer.c val = readl_relaxed(timer->base + CNTP_CTL); val 129 drivers/clocksource/arm_arch_timer.c val = readl_relaxed(timer->base + CNTP_TVAL); val 136 drivers/clocksource/arm_arch_timer.c val = readl_relaxed(timer->base + CNTV_CTL); val 139 drivers/clocksource/arm_arch_timer.c val = readl_relaxed(timer->base + CNTV_TVAL); val 143 drivers/clocksource/arm_arch_timer.c val = arch_timer_reg_read_cp15(access, reg); val 146 drivers/clocksource/arm_arch_timer.c return val; val 54 drivers/clocksource/dw_apb_timer.c static inline void apbt_writel(struct dw_apb_timer *timer, u32 val, val 57 drivers/clocksource/dw_apb_timer.c writel(val, timer->base + offs); val 65 drivers/clocksource/dw_apb_timer.c static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val, val 68 drivers/clocksource/dw_apb_timer.c writel_relaxed(val, timer->base + offs); val 42 drivers/clocksource/h8300_tpu.c static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val) val 59 drivers/clocksource/h8300_tpu.c *val = v2; val 49 drivers/clocksource/mps2-timer.c static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset) val 51 drivers/clocksource/mps2-timer.c writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); val 424 drivers/clocksource/samsung_pwm_timer.c u32 val; val 431 drivers/clocksource/samsung_pwm_timer.c of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { val 432 drivers/clocksource/samsung_pwm_timer.c if (val >= SAMSUNG_PWM_NUM) { val 437 drivers/clocksource/samsung_pwm_timer.c pwm.variant.output_mask |= 1 << val; val 90 drivers/clocksource/timer-atcpit100.c u32 val; val 92 drivers/clocksource/timer-atcpit100.c val = readl(base + INT_STA); val 93 drivers/clocksource/timer-atcpit100.c writel(val | CH0INT0, base + INT_STA); val 98 drivers/clocksource/timer-atcpit100.c u32 val; val 100 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); val 101 drivers/clocksource/timer-atcpit100.c writel(val | CH1TMR0EN, base + CH_EN); val 106 drivers/clocksource/timer-atcpit100.c u32 val; val 108 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); val 109 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, base + CH_EN); val 114 drivers/clocksource/timer-atcpit100.c u32 val; val 117 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); val 118 drivers/clocksource/timer-atcpit100.c writel(val & ~CH0TMR0EN, base + CH_EN); val 124 drivers/clocksource/timer-atcpit100.c u32 val; val 127 drivers/clocksource/timer-atcpit100.c val = readl(timer_of_base(to) + CH_EN); val 128 drivers/clocksource/timer-atcpit100.c writel(val & ~CH0TMR0EN, timer_of_base(to) + CH_EN); val 130 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); val 155 drivers/clocksource/timer-atcpit100.c u32 val; val 158 drivers/clocksource/timer-atcpit100.c val = readl(timer_of_base(to) + CH_EN); val 159 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); val 224 drivers/clocksource/timer-atcpit100.c u32 val; val 256 drivers/clocksource/timer-atcpit100.c val = readl(base + INT_EN); val 257 drivers/clocksource/timer-atcpit100.c writel(val | CH0INT0EN, base + INT_EN); val 97 drivers/clocksource/timer-atmel-st.c unsigned int val; val 101 drivers/clocksource/timer-atmel-st.c regmap_read(regmap_st, AT91_ST_SR, &val); val 143 drivers/clocksource/timer-atmel-st.c unsigned int val; val 160 drivers/clocksource/timer-atmel-st.c regmap_read(regmap_st, AT91_ST_SR, &val); val 187 drivers/clocksource/timer-atmel-st.c unsigned int sclk_rate, val; val 199 drivers/clocksource/timer-atmel-st.c regmap_read(regmap_st, AT91_ST_SR, &val); val 108 drivers/clocksource/timer-cs5535.c uint16_t val = cs5535_mfgpt_read(cs5535_event_clock, MFGPT_REG_SETUP); val 111 drivers/clocksource/timer-cs5535.c if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1))) val 144 drivers/clocksource/timer-cs5535.c uint16_t val; val 168 drivers/clocksource/timer-cs5535.c val = MFGPT_SCALE | (3 << 8); val 170 drivers/clocksource/timer-cs5535.c cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, val); val 81 drivers/clocksource/timer-davinci.c unsigned int reg, unsigned int val) val 83 drivers/clocksource/timer-davinci.c writel_relaxed(val, clockevent->base + reg); val 20 drivers/clocksource/timer-efm32.c #define TIMERn_CTRL_PRESC(val) (((val) & 0xf) << 24) val 22 drivers/clocksource/timer-efm32.c #define TIMERn_CTRL_CLKSEL(val) (((val) & 0x3) << 16) val 25 drivers/clocksource/timer-efm32.c #define TIMERn_CTRL_MODE(val) (((val) & 0x3) << 0) val 40 drivers/clocksource/timer-fsl-ftm.c static inline void ftm_writel(u32 val, void __iomem *addr) val 43 drivers/clocksource/timer-fsl-ftm.c iowrite32be(val, addr); val 45 drivers/clocksource/timer-fsl-ftm.c iowrite32(val, addr); val 50 drivers/clocksource/timer-fsl-ftm.c u32 val; val 53 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); val 54 drivers/clocksource/timer-fsl-ftm.c val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK); val 55 drivers/clocksource/timer-fsl-ftm.c val |= priv->ps | FTM_SC_CLK(1); val 56 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); val 61 drivers/clocksource/timer-fsl-ftm.c u32 val; val 64 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); val 65 drivers/clocksource/timer-fsl-ftm.c val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK); val 66 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); val 71 drivers/clocksource/timer-fsl-ftm.c u32 val; val 73 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); val 74 drivers/clocksource/timer-fsl-ftm.c val &= ~FTM_SC_TOF; val 75 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); val 80 drivers/clocksource/timer-fsl-ftm.c u32 val; val 82 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); val 83 drivers/clocksource/timer-fsl-ftm.c val |= FTM_SC_TOIE; val 84 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); val 89 drivers/clocksource/timer-fsl-ftm.c u32 val; val 91 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); val 92 drivers/clocksource/timer-fsl-ftm.c val &= ~FTM_SC_TOIE; val 93 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); val 258 drivers/clocksource/timer-fttmr010.c u32 val; val 319 drivers/clocksource/timer-fttmr010.c val = TIMER_2_CR_ASPEED_ENABLE; val 321 drivers/clocksource/timer-fttmr010.c val = TIMER_2_CR_ENABLE | TIMER_1_CR_UPDOWN | val 324 drivers/clocksource/timer-fttmr010.c writel(val, fttmr010->base + TIMER_CR); val 42 drivers/clocksource/timer-imx-tpm.c unsigned int val; val 45 drivers/clocksource/timer-imx-tpm.c val = readl(timer_base + TPM_C0SC); val 46 drivers/clocksource/timer-imx-tpm.c val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE); val 47 drivers/clocksource/timer-imx-tpm.c writel(val, timer_base + TPM_C0SC); val 52 drivers/clocksource/timer-imx-tpm.c unsigned int val; val 55 drivers/clocksource/timer-imx-tpm.c val = readl(timer_base + TPM_C0SC); val 56 drivers/clocksource/timer-imx-tpm.c val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) | val 58 drivers/clocksource/timer-imx-tpm.c writel(val, timer_base + TPM_C0SC); val 111 drivers/clocksource/timer-ixp4xx.c u32 val; val 113 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); val 115 drivers/clocksource/timer-ixp4xx.c val &= IXP4XX_OST_RELOAD_MASK; val 116 drivers/clocksource/timer-ixp4xx.c __raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val, val 125 drivers/clocksource/timer-ixp4xx.c u32 val; val 127 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); val 128 drivers/clocksource/timer-ixp4xx.c val &= ~IXP4XX_OST_ENABLE; val 129 drivers/clocksource/timer-ixp4xx.c __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); val 147 drivers/clocksource/timer-ixp4xx.c u32 val; val 149 drivers/clocksource/timer-ixp4xx.c val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK; val 150 drivers/clocksource/timer-ixp4xx.c val |= IXP4XX_OST_ENABLE; val 151 drivers/clocksource/timer-ixp4xx.c __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); val 159 drivers/clocksource/timer-ixp4xx.c u32 val; val 161 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); val 162 drivers/clocksource/timer-ixp4xx.c val |= IXP4XX_OST_ENABLE; val 163 drivers/clocksource/timer-ixp4xx.c __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); val 53 drivers/clocksource/timer-keystone.c static inline void keystone_timer_writel(u32 val, unsigned long rg) val 55 drivers/clocksource/timer-keystone.c writel_relaxed(val, timer.base + rg); val 27 drivers/clocksource/timer-mediatek.c #define GPT_IRQ_ENABLE(val) BIT((val) - 1) val 29 drivers/clocksource/timer-mediatek.c #define GPT_IRQ_ACK(val) BIT((val) - 1) val 31 drivers/clocksource/timer-mediatek.c #define GPT_CTRL_REG(val) (0x10 * (val)) val 32 drivers/clocksource/timer-mediatek.c #define GPT_CTRL_OP(val) (((val) & 0x3) << 4) val 40 drivers/clocksource/timer-mediatek.c #define GPT_CLK_REG(val) (0x04 + (0x10 * (val))) val 41 drivers/clocksource/timer-mediatek.c #define GPT_CLK_SRC(val) (((val) & 0x1) << 4) val 47 drivers/clocksource/timer-mediatek.c #define GPT_CNT_REG(val) (0x08 + (0x10 * (val))) val 48 drivers/clocksource/timer-mediatek.c #define GPT_CMP_REG(val) (0x0C + (0x10 * (val))) val 137 drivers/clocksource/timer-mediatek.c u32 val; val 139 drivers/clocksource/timer-mediatek.c val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); val 140 drivers/clocksource/timer-mediatek.c writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) + val 153 drivers/clocksource/timer-mediatek.c u32 val; val 158 drivers/clocksource/timer-mediatek.c val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); val 161 drivers/clocksource/timer-mediatek.c val &= ~GPT_CTRL_OP(0x3); val 164 drivers/clocksource/timer-mediatek.c val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT); val 166 drivers/clocksource/timer-mediatek.c val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT); val 168 drivers/clocksource/timer-mediatek.c writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR, val 231 drivers/clocksource/timer-mediatek.c u32 val; val 239 drivers/clocksource/timer-mediatek.c val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); val 240 drivers/clocksource/timer-mediatek.c writel(val | GPT_IRQ_ENABLE(timer), val 77 drivers/clocksource/timer-meson6.c u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); val 79 drivers/clocksource/timer-meson6.c writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN, val 90 drivers/clocksource/timer-meson6.c u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); val 93 drivers/clocksource/timer-meson6.c val |= MESON_ISA_TIMER_MUX_TIMERA_MODE; val 95 drivers/clocksource/timer-meson6.c val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE; val 97 drivers/clocksource/timer-meson6.c writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN, val 162 drivers/clocksource/timer-meson6.c u32 val; val 178 drivers/clocksource/timer-meson6.c val = readl(timer_base + MESON_ISA_TIMER_MUX); val 179 drivers/clocksource/timer-meson6.c val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK; val 180 drivers/clocksource/timer-meson6.c val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK, val 182 drivers/clocksource/timer-meson6.c writel(val, timer_base + MESON_ISA_TIMER_MUX); val 189 drivers/clocksource/timer-meson6.c val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK; val 190 drivers/clocksource/timer-meson6.c val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK, val 192 drivers/clocksource/timer-meson6.c writel(val, timer_base + MESON_ISA_TIMER_MUX); val 53 drivers/clocksource/timer-milbeaut.c u32 val; val 55 drivers/clocksource/timer-milbeaut.c val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); val 56 drivers/clocksource/timer-milbeaut.c val &= ~MLB_TMR_TMCSR_UF; val 57 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); val 66 drivers/clocksource/timer-milbeaut.c u32 val = MLB_TMR_TMCSR_CSL_DIV2; val 68 drivers/clocksource/timer-milbeaut.c val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; val 70 drivers/clocksource/timer-milbeaut.c val |= MLB_TMR_TMCSR_RELD; val 71 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); val 76 drivers/clocksource/timer-milbeaut.c u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); val 78 drivers/clocksource/timer-milbeaut.c val &= ~MLB_TMR_TMCSR_CNTE; val 79 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); val 127 drivers/clocksource/timer-milbeaut.c u32 val = MLB_TMR_TMCSR_CSL_DIV2; val 129 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); val 132 drivers/clocksource/timer-milbeaut.c val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG; val 133 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); val 59 drivers/clocksource/timer-npcm7xx.c u32 val; val 61 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); val 62 drivers/clocksource/timer-npcm7xx.c val |= NPCM7XX_Tx_COUNTEN; val 63 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); val 71 drivers/clocksource/timer-npcm7xx.c u32 val; val 73 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); val 74 drivers/clocksource/timer-npcm7xx.c val &= ~NPCM7XX_Tx_COUNTEN; val 75 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); val 83 drivers/clocksource/timer-npcm7xx.c u32 val; val 85 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); val 86 drivers/clocksource/timer-npcm7xx.c val &= ~NPCM7XX_Tx_OPER; val 87 drivers/clocksource/timer-npcm7xx.c val |= NPCM7XX_START_ONESHOT_Tx; val 88 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); val 96 drivers/clocksource/timer-npcm7xx.c u32 val; val 100 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); val 101 drivers/clocksource/timer-npcm7xx.c val &= ~NPCM7XX_Tx_OPER; val 102 drivers/clocksource/timer-npcm7xx.c val |= NPCM7XX_START_PERIODIC_Tx; val 103 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); val 112 drivers/clocksource/timer-npcm7xx.c u32 val; val 115 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); val 116 drivers/clocksource/timer-npcm7xx.c val |= NPCM7XX_START_Tx; val 117 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); val 171 drivers/clocksource/timer-npcm7xx.c u32 val; val 178 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); val 179 drivers/clocksource/timer-npcm7xx.c val |= NPCM7XX_START_Tx; val 180 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); val 99 drivers/clocksource/timer-pistachio.c u32 val; val 101 drivers/clocksource/timer-pistachio.c val = gpt_readl(pcs->base, TIMER_CFG, timeridx); val 103 drivers/clocksource/timer-pistachio.c val |= TIMER_ME_LOCAL; val 105 drivers/clocksource/timer-pistachio.c val &= ~TIMER_ME_LOCAL; val 107 drivers/clocksource/timer-pistachio.c gpt_writel(pcs->base, val, TIMER_CFG, timeridx); val 107 drivers/clocksource/timer-prima2.c u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); val 109 drivers/clocksource/timer-prima2.c writel_relaxed(val & ~BIT(0), val 116 drivers/clocksource/timer-prima2.c u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); val 118 drivers/clocksource/timer-prima2.c writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); val 53 drivers/clocksource/timer-pxa.c #define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg)) val 36 drivers/clocksource/timer-sprd.c u32 val = readl_relaxed(base + TIMER_CTL); val 38 drivers/clocksource/timer-sprd.c val |= TIMER_CTL_ENABLE; val 40 drivers/clocksource/timer-sprd.c val |= TIMER_CTL_64BIT_WIDTH; val 42 drivers/clocksource/timer-sprd.c val &= ~TIMER_CTL_64BIT_WIDTH; val 45 drivers/clocksource/timer-sprd.c val |= TIMER_CTL_PERIOD_MODE; val 47 drivers/clocksource/timer-sprd.c val &= ~TIMER_CTL_PERIOD_MODE; val 49 drivers/clocksource/timer-sprd.c writel_relaxed(val, base + TIMER_CTL); val 54 drivers/clocksource/timer-sprd.c u32 val = readl_relaxed(base + TIMER_CTL); val 56 drivers/clocksource/timer-sprd.c val &= ~TIMER_CTL_ENABLE; val 57 drivers/clocksource/timer-sprd.c writel_relaxed(val, base + TIMER_CTL); val 73 drivers/clocksource/timer-sprd.c u32 val = readl_relaxed(base + TIMER_INT); val 75 drivers/clocksource/timer-sprd.c val |= TIMER_INT_CLR; val 76 drivers/clocksource/timer-sprd.c writel_relaxed(val, base + TIMER_INT); val 30 drivers/clocksource/timer-sun4i.c #define TIMER_IRQ_EN(val) BIT(val) val 32 drivers/clocksource/timer-sun4i.c #define TIMER_CTL_REG(val) (0x10 * val + 0x10) val 35 drivers/clocksource/timer-sun4i.c #define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2) val 37 drivers/clocksource/timer-sun4i.c #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) val 39 drivers/clocksource/timer-sun4i.c #define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14) val 40 drivers/clocksource/timer-sun4i.c #define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18) val 60 drivers/clocksource/timer-sun4i.c u32 val = readl(base + TIMER_CTL_REG(timer)); val 61 drivers/clocksource/timer-sun4i.c writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer)); val 74 drivers/clocksource/timer-sun4i.c u32 val = readl(base + TIMER_CTL_REG(timer)); val 77 drivers/clocksource/timer-sun4i.c val &= ~TIMER_CTL_ONESHOT; val 79 drivers/clocksource/timer-sun4i.c val |= TIMER_CTL_ONESHOT; val 81 drivers/clocksource/timer-sun4i.c writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, val 172 drivers/clocksource/timer-sun4i.c u32 val; val 215 drivers/clocksource/timer-sun4i.c val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG); val 216 drivers/clocksource/timer-sun4i.c writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG); val 27 drivers/clocksource/timer-sun5i.c #define TIMER_IRQ_EN(val) BIT(val) val 29 drivers/clocksource/timer-sun5i.c #define TIMER_CTL_REG(val) (0x20 * (val) + 0x10) val 32 drivers/clocksource/timer-sun5i.c #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) val 34 drivers/clocksource/timer-sun5i.c #define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14) val 35 drivers/clocksource/timer-sun5i.c #define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18) val 36 drivers/clocksource/timer-sun5i.c #define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c) val 37 drivers/clocksource/timer-sun5i.c #define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20) val 83 drivers/clocksource/timer-sun5i.c u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); val 84 drivers/clocksource/timer-sun5i.c writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); val 96 drivers/clocksource/timer-sun5i.c u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); val 99 drivers/clocksource/timer-sun5i.c val &= ~TIMER_CTL_ONESHOT; val 101 drivers/clocksource/timer-sun5i.c val |= TIMER_CTL_ONESHOT; val 103 drivers/clocksource/timer-sun5i.c writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, val 270 drivers/clocksource/timer-sun5i.c u32 val; val 313 drivers/clocksource/timer-sun5i.c val = readl(base + TIMER_IRQ_EN_REG); val 314 drivers/clocksource/timer-sun5i.c writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG); val 56 drivers/connector/cn_queue.c return ((i1->idx == i2->idx) && (i1->val == i2->val)); val 243 drivers/connector/connector.c cbq->id.id.val); val 96 drivers/counter/104-quad-8.c struct iio_chan_spec const *chan, int *val, int *val2, long mask) val 108 drivers/counter/104-quad-8.c *val = !!(inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) val 118 drivers/counter/104-quad-8.c *val = (borrow ^ carry) << 24; val 127 drivers/counter/104-quad-8.c *val |= (unsigned int)inb(base_offset) << (8 * i); val 133 drivers/counter/104-quad-8.c *val = priv->ab_enable[chan->channel]; val 136 drivers/counter/104-quad-8.c *val = 1; val 145 drivers/counter/104-quad-8.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 158 drivers/counter/104-quad-8.c if ((unsigned int)val > 0xFFFFFF) val 168 drivers/counter/104-quad-8.c outb(val >> (8 * i), base_offset); val 177 drivers/counter/104-quad-8.c val = priv->preset[chan->channel]; val 179 drivers/counter/104-quad-8.c outb(val >> (8 * i), base_offset); val 191 drivers/counter/104-quad-8.c if (val < 0 || val > 1) val 196 drivers/counter/104-quad-8.c priv->ab_enable[chan->channel] = val; val 198 drivers/counter/104-quad-8.c ior_cfg = val | priv->preset_enable[chan->channel] << 1; val 211 drivers/counter/104-quad-8.c (val2 || val != 1)) { val 217 drivers/counter/104-quad-8.c if (val == 1 && !val2) val 219 drivers/counter/104-quad-8.c else if (!val) val 617 drivers/counter/104-quad-8.c struct counter_signal *signal, struct counter_signal_read_value *val) val 632 drivers/counter/104-quad-8.c counter_signal_read_value_set(val, COUNTER_SIGNAL_LEVEL, &level); val 638 drivers/counter/104-quad-8.c struct counter_count *count, struct counter_count_read_value *val) val 664 drivers/counter/104-quad-8.c counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &position); val 672 drivers/counter/104-quad-8.c struct counter_count *count, struct counter_count_write_value *val) val 681 drivers/counter/104-quad-8.c val); val 237 drivers/counter/counter.c void counter_signal_read_value_set(struct counter_signal_read_value *const val, val 242 drivers/counter/counter.c val->len = sprintf(val->buf, "%s\n", val 245 drivers/counter/counter.c val->len = 0; val 258 drivers/counter/counter.c void counter_count_read_value_set(struct counter_count_read_value *const val, val 264 drivers/counter/counter.c val->len = sprintf(val->buf, "%lu\n", *(unsigned long *)data); val 267 drivers/counter/counter.c val->len = 0; val 287 drivers/counter/counter.c const struct counter_count_write_value *const val) val 293 drivers/counter/counter.c err = kstrtoul(val->buf, 0, data); val 380 drivers/counter/counter.c struct counter_signal_read_value val = { .buf = buf }; val 382 drivers/counter/counter.c err = counter->ops->signal_read(counter, signal, &val); val 386 drivers/counter/counter.c return val.len; val 791 drivers/counter/counter.c struct counter_count_read_value val = { .buf = buf }; val 793 drivers/counter/counter.c err = counter->ops->count_read(counter, count, &val); val 797 drivers/counter/counter.c return val.len; val 809 drivers/counter/counter.c struct counter_count_write_value val = { .buf = buf }; val 811 drivers/counter/counter.c err = counter->ops->count_write(counter, count, &val); val 18 drivers/counter/ftm-quaddec.c #define FTM_FIELD_UPDATE(ftm, offset, mask, val) \ val 23 drivers/counter/ftm-quaddec.c flags |= FIELD_PREP(mask, val); \ val 181 drivers/counter/ftm-quaddec.c struct counter_count_read_value *val) val 188 drivers/counter/ftm-quaddec.c counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &cntval); val 195 drivers/counter/ftm-quaddec.c struct counter_count_write_value *val) val 201 drivers/counter/ftm-quaddec.c err = counter_count_write_value_get(&cnt, COUNTER_COUNT_POSITION, val); val 34 drivers/counter/stm32-lptimer-cnt.c u32 val; val 37 drivers/counter/stm32-lptimer-cnt.c ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val); val 41 drivers/counter/stm32-lptimer-cnt.c return FIELD_GET(STM32_LPTIM_ENABLE, val); val 48 drivers/counter/stm32-lptimer-cnt.c u32 val; val 50 drivers/counter/stm32-lptimer-cnt.c val = FIELD_PREP(STM32_LPTIM_ENABLE, enable); val 51 drivers/counter/stm32-lptimer-cnt.c ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val); val 71 drivers/counter/stm32-lptimer-cnt.c ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, val 72 drivers/counter/stm32-lptimer-cnt.c (val & STM32_LPTIM_CMPOK_ARROK), val 98 drivers/counter/stm32-lptimer-cnt.c u32 val; val 102 drivers/counter/stm32-lptimer-cnt.c val = enable ? STM32_LPTIM_ENC : 0; val 104 drivers/counter/stm32-lptimer-cnt.c val = enable ? STM32_LPTIM_COUNTMODE : 0; val 105 drivers/counter/stm32-lptimer-cnt.c val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0); val 107 drivers/counter/stm32-lptimer-cnt.c return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val); val 112 drivers/counter/stm32-lptimer-cnt.c int val, int val2, long mask) val 119 drivers/counter/stm32-lptimer-cnt.c if (val < 0 || val > 1) val 124 drivers/counter/stm32-lptimer-cnt.c if ((ret < 0) || (!ret && !val)) val 126 drivers/counter/stm32-lptimer-cnt.c if (val && ret) val 129 drivers/counter/stm32-lptimer-cnt.c ret = stm32_lptim_setup(priv, val); val 132 drivers/counter/stm32-lptimer-cnt.c return stm32_lptim_set_enable_state(priv, val); val 141 drivers/counter/stm32-lptimer-cnt.c int *val, int *val2, long mask) val 152 drivers/counter/stm32-lptimer-cnt.c *val = dat; val 159 drivers/counter/stm32-lptimer-cnt.c *val = ret; val 164 drivers/counter/stm32-lptimer-cnt.c *val = 1; val 381 drivers/counter/stm32-lptimer-cnt.c struct counter_count_read_value *val) val 391 drivers/counter/stm32-lptimer-cnt.c counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &cnt); val 52 drivers/counter/stm32-timer-cnt.c struct counter_count_read_value *val) val 58 drivers/counter/stm32-timer-cnt.c counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &cnt); val 65 drivers/counter/stm32-timer-cnt.c struct counter_count_write_value *val) val 71 drivers/counter/stm32-timer-cnt.c err = counter_count_write_value_get(&cnt, COUNTER_COUNT_POSITION, val); val 56 drivers/cpufreq/acpi-cpufreq.c void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val); val 94 drivers/cpufreq/acpi-cpufreq.c u64 msr_mask, val; val 110 drivers/cpufreq/acpi-cpufreq.c rdmsrl(msr_addr, val); val 113 drivers/cpufreq/acpi-cpufreq.c val &= ~msr_mask; val 115 drivers/cpufreq/acpi-cpufreq.c val |= msr_mask; val 117 drivers/cpufreq/acpi-cpufreq.c wrmsrl(msr_addr, val); val 128 drivers/cpufreq/acpi-cpufreq.c static int set_boost(int val) val 131 drivers/cpufreq/acpi-cpufreq.c on_each_cpu(boost_set_msr_each, (void *)(long)val, 1); val 133 drivers/cpufreq/acpi-cpufreq.c pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); val 155 drivers/cpufreq/acpi-cpufreq.c unsigned int val = 0; val 160 drivers/cpufreq/acpi-cpufreq.c ret = kstrtouint(buf, 10, &val); val 161 drivers/cpufreq/acpi-cpufreq.c if (ret || val > 1) val 164 drivers/cpufreq/acpi-cpufreq.c set_boost(val); val 227 drivers/cpufreq/acpi-cpufreq.c static unsigned extract_freq(struct cpufreq_policy *policy, u32 val) val 234 drivers/cpufreq/acpi-cpufreq.c return extract_msr(policy, val); val 236 drivers/cpufreq/acpi-cpufreq.c return extract_io(policy, val); val 244 drivers/cpufreq/acpi-cpufreq.c u32 val, dummy; val 246 drivers/cpufreq/acpi-cpufreq.c rdmsr(MSR_IA32_PERF_CTL, val, dummy); val 247 drivers/cpufreq/acpi-cpufreq.c return val; val 250 drivers/cpufreq/acpi-cpufreq.c static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val) val 255 drivers/cpufreq/acpi-cpufreq.c lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE); val 261 drivers/cpufreq/acpi-cpufreq.c u32 val, dummy; val 263 drivers/cpufreq/acpi-cpufreq.c rdmsr(MSR_AMD_PERF_CTL, val, dummy); val 264 drivers/cpufreq/acpi-cpufreq.c return val; val 267 drivers/cpufreq/acpi-cpufreq.c static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val) val 269 drivers/cpufreq/acpi-cpufreq.c wrmsr(MSR_AMD_PERF_CTL, val, 0); val 274 drivers/cpufreq/acpi-cpufreq.c u32 val; val 276 drivers/cpufreq/acpi-cpufreq.c acpi_os_read_port(reg->address, &val, reg->bit_width); val 277 drivers/cpufreq/acpi-cpufreq.c return val; val 280 drivers/cpufreq/acpi-cpufreq.c static void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val) val 282 drivers/cpufreq/acpi-cpufreq.c acpi_os_write_port(reg->address, val, reg->bit_width); val 287 drivers/cpufreq/acpi-cpufreq.c u32 val; val 289 drivers/cpufreq/acpi-cpufreq.c void (*write)(struct acpi_pct_register *reg, u32 val); val 299 drivers/cpufreq/acpi-cpufreq.c cmd->val = cmd->func.read(cmd->reg); val 313 drivers/cpufreq/acpi-cpufreq.c return cmd.val; val 321 drivers/cpufreq/acpi-cpufreq.c cmd->func.write(cmd->reg, cmd->val); val 325 drivers/cpufreq/acpi-cpufreq.c const struct cpumask *mask, u32 val) val 330 drivers/cpufreq/acpi-cpufreq.c .val = val, val 345 drivers/cpufreq/acpi-cpufreq.c u32 val; val 350 drivers/cpufreq/acpi-cpufreq.c val = drv_read(data, mask); val 352 drivers/cpufreq/acpi-cpufreq.c pr_debug("%s = %u\n", __func__, val); val 354 drivers/cpufreq/acpi-cpufreq.c return val; val 109 drivers/cpufreq/amd_freq_sensitivity.c u64 val; val 128 drivers/cpufreq/amd_freq_sensitivity.c if (rdmsrl_safe(MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, &val)) val 131 drivers/cpufreq/amd_freq_sensitivity.c if (!(val >> CLASS_CODE_SHIFT)) val 129 drivers/cpufreq/armada-37xx-cpufreq.c unsigned int reg, mask, val, offset = 0; val 141 drivers/cpufreq/armada-37xx-cpufreq.c val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF; val 149 drivers/cpufreq/armada-37xx-cpufreq.c val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF; val 154 drivers/cpufreq/armada-37xx-cpufreq.c val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF; val 158 drivers/cpufreq/armada-37xx-cpufreq.c val <<= offset; val 161 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, val); val 303 drivers/cpufreq/armada-37xx-cpufreq.c unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD, val 307 drivers/cpufreq/armada-37xx-cpufreq.c val = ARMADA_37XX_DVFS_LOAD_0; val 308 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, val); val 205 drivers/cpufreq/brcmstb-avs-cpufreq.c u32 val; val 216 drivers/cpufreq/brcmstb-avs-cpufreq.c for (i = 0, val = 1; val != 0 && i < AVS_LOOP_LIMIT; i++) val 217 drivers/cpufreq/brcmstb-avs-cpufreq.c val = readl(base + AVS_MBOX_COMMAND); val 249 drivers/cpufreq/brcmstb-avs-cpufreq.c val = readl(base + AVS_MBOX_STATUS); val 250 drivers/cpufreq/brcmstb-avs-cpufreq.c if (time_left == 0 || val == 0 || val > AVS_STATUS_MAX) { val 254 drivers/cpufreq/brcmstb-avs-cpufreq.c jiffies_to_msecs(time_left), val); val 269 drivers/cpufreq/brcmstb-avs-cpufreq.c switch (val) { val 109 drivers/cpufreq/cppc_cpufreq.c u16 val = (u16)get_unaligned((const u16 *) val 111 drivers/cpufreq/cppc_cpufreq.c *mhz = val > *mhz ? val : *mhz; val 304 drivers/cpufreq/cpufreq.c static void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci) val 319 drivers/cpufreq/cpufreq.c if (val == CPUFREQ_POSTCHANGE && ci->old != ci->new) { val 711 drivers/cpufreq/cpufreq.c unsigned long val; \ val 714 drivers/cpufreq/cpufreq.c ret = sscanf(buf, "%lu", &val); \ val 718 drivers/cpufreq/cpufreq.c ret = freq_qos_update_request(policy->object##_freq_req, val);\ val 176 drivers/cpufreq/e_powersaver.c u64 val; val 229 drivers/cpufreq/e_powersaver.c rdmsrl(MSR_IA32_MISC_ENABLE, val); val 230 drivers/cpufreq/e_powersaver.c if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { val 231 drivers/cpufreq/e_powersaver.c val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP; val 232 drivers/cpufreq/e_powersaver.c wrmsrl(MSR_IA32_MISC_ENABLE, val); val 234 drivers/cpufreq/e_powersaver.c rdmsrl(MSR_IA32_MISC_ENABLE, val); val 235 drivers/cpufreq/e_powersaver.c if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { val 223 drivers/cpufreq/imx6q-cpufreq.c u32 val; val 243 drivers/cpufreq/imx6q-cpufreq.c val = readl_relaxed(base + OCOTP_CFG3); val 244 drivers/cpufreq/imx6q-cpufreq.c val >>= OCOTP_CFG3_SPEED_SHIFT; val 245 drivers/cpufreq/imx6q-cpufreq.c val &= 0x3; val 247 drivers/cpufreq/imx6q-cpufreq.c if (val < OCOTP_CFG3_SPEED_996MHZ) val 253 drivers/cpufreq/imx6q-cpufreq.c if (val != OCOTP_CFG3_SPEED_852MHZ) val 256 drivers/cpufreq/imx6q-cpufreq.c if (val != OCOTP_CFG3_SPEED_1P2GHZ) val 271 drivers/cpufreq/imx6q-cpufreq.c u32 val; val 275 drivers/cpufreq/imx6q-cpufreq.c ret = nvmem_cell_read_u32(dev, "speed_grade", &val); val 296 drivers/cpufreq/imx6q-cpufreq.c val = readl_relaxed(base + OCOTP_CFG3); val 308 drivers/cpufreq/imx6q-cpufreq.c val >>= OCOTP_CFG3_SPEED_SHIFT; val 309 drivers/cpufreq/imx6q-cpufreq.c val &= 0x3; val 312 drivers/cpufreq/imx6q-cpufreq.c if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) val 318 drivers/cpufreq/imx6q-cpufreq.c if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ) val 322 drivers/cpufreq/imx6q-cpufreq.c if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) val 337 drivers/cpufreq/imx6q-cpufreq.c const __be32 *val; val 436 drivers/cpufreq/imx6q-cpufreq.c val = prop->value; val 438 drivers/cpufreq/imx6q-cpufreq.c unsigned long freq = be32_to_cpup(val++); val 439 drivers/cpufreq/imx6q-cpufreq.c unsigned long volt = be32_to_cpup(val++); val 1335 drivers/cpufreq/intel_pstate.c u64 val; val 1339 drivers/cpufreq/intel_pstate.c val = (u64)pstate << 8; val 1341 drivers/cpufreq/intel_pstate.c val |= (u64)1 << 32; val 1353 drivers/cpufreq/intel_pstate.c return val | vid; val 1507 drivers/cpufreq/intel_pstate.c u64 val; val 1509 drivers/cpufreq/intel_pstate.c val = (u64)pstate << 8; val 1511 drivers/cpufreq/intel_pstate.c val |= (u64)1 << 32; val 1513 drivers/cpufreq/intel_pstate.c return val; val 139 drivers/cpufreq/longhaul.c rdmsrl(MSR_VIA_BCR2, bcr2.val); val 147 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_BCR2, bcr2.val); val 154 drivers/cpufreq/longhaul.c rdmsrl(MSR_VIA_BCR2, bcr2.val); val 156 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_BCR2, bcr2.val); val 167 drivers/cpufreq/longhaul.c rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); val 183 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); val 197 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); val 202 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); val 215 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); val 220 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); val 234 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); val 536 drivers/cpufreq/longhaul.c rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); val 17 drivers/cpufreq/longhaul.h unsigned long val; val 46 drivers/cpufreq/longhaul.h unsigned long long val; val 37 drivers/cpufreq/loongson1-cpufreq.c unsigned long val, void *data) val 39 drivers/cpufreq/loongson1-cpufreq.c if (val == CPUFREQ_POSTCHANGE) val 33 drivers/cpufreq/loongson2_cpufreq.c unsigned long val, void *data); val 40 drivers/cpufreq/loongson2_cpufreq.c unsigned long val, void *data) val 42 drivers/cpufreq/loongson2_cpufreq.c if (val == CPUFREQ_POSTCHANGE) val 299 drivers/cpufreq/pmac64-cpufreq.c u32 val = 0; val 302 drivers/cpufreq/pmac64-cpufreq.c args.u[0].p = &val; val 304 drivers/cpufreq/pmac64-cpufreq.c return val ? CPUFREQ_HIGH : CPUFREQ_LOW; val 65 drivers/cpufreq/powernow-k7.c unsigned long val; val 222 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); val 228 drivers/cpufreq/powernow-k7.c wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); val 237 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); val 243 drivers/cpufreq/powernow-k7.c wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); val 263 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); val 350 drivers/cpufreq/powernow-k7.c pc.val = (unsigned long) acpi_processor_perf->states[0].control; val 357 drivers/cpufreq/powernow-k7.c pc.val = (unsigned long) state->control; val 560 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); val 601 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); val 22 drivers/cpufreq/powernow-k7.h unsigned long long val; val 40 drivers/cpufreq/powernow-k7.h unsigned long long val; val 450 drivers/cpufreq/powernv-cpufreq.c static inline void set_pmspr(unsigned long sprn, unsigned long val) val 454 drivers/cpufreq/powernv-cpufreq.c mtspr(SPRN_PMCR, val); val 458 drivers/cpufreq/powernv-cpufreq.c mtspr(SPRN_PMICR, val); val 525 drivers/cpufreq/powernv-cpufreq.c unsigned long val; val 530 drivers/cpufreq/powernv-cpufreq.c val = get_pmspr(SPRN_PMCR); val 531 drivers/cpufreq/powernv-cpufreq.c val = val & 0x0000FFFFFFFFFFFFULL; val 537 drivers/cpufreq/powernv-cpufreq.c val = val | (gpstate_ul << 56) | (pstate_ul << 48); val 540 drivers/cpufreq/powernv-cpufreq.c raw_smp_processor_id(), val); val 541 drivers/cpufreq/powernv-cpufreq.c set_pmspr(SPRN_PMCR, val); val 674 drivers/cpufreq/powernv-cpufreq.c unsigned long val; val 697 drivers/cpufreq/powernv-cpufreq.c val = get_pmspr(SPRN_PMCR); val 698 drivers/cpufreq/powernv-cpufreq.c freq_data.gpstate_id = extract_global_pstate(val); val 699 drivers/cpufreq/powernv-cpufreq.c freq_data.pstate_id = extract_local_pstate(val); val 539 drivers/cpufreq/s3c24xx-cpufreq.c u32 val; val 546 drivers/cpufreq/s3c24xx-cpufreq.c val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; val 547 drivers/cpufreq/s3c24xx-cpufreq.c val |= calc_locktime(rate, cpu_cur.info->locktime_m); val 549 drivers/cpufreq/s3c24xx-cpufreq.c pr_info("%s: new locktime is 0x%08x\n", __func__, val); val 550 drivers/cpufreq/s3c24xx-cpufreq.c __raw_writel(val, S3C2410_LOCKTIME); val 490 drivers/cpufreq/s5pv210-cpufreq.c unsigned long val; val 492 drivers/cpufreq/s5pv210-cpufreq.c val = readl_relaxed(dmc_reg + 0x4); val 493 drivers/cpufreq/s5pv210-cpufreq.c val = (val & (0xf << 8)); val 495 drivers/cpufreq/s5pv210-cpufreq.c return val >> 8; val 61 drivers/cpufreq/sparc-us2e-cpufreq.c static void write_hbreg(unsigned long addr, unsigned long val) val 66 drivers/cpufreq/sparc-us2e-cpufreq.c : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) val 41 drivers/cpufreq/sparc-us3-cpufreq.c unsigned long ret, *val = arg; val 46 drivers/cpufreq/sparc-us3-cpufreq.c *val = ret; val 176 drivers/cpufreq/spear-cpufreq.c const __be32 *val; val 197 drivers/cpufreq/spear-cpufreq.c val = prop->value; val 206 drivers/cpufreq/spear-cpufreq.c freq_tbl[i].frequency = be32_to_cpup(val++); val 29 drivers/cpuidle/cpuidle-calxeda.c static int calxeda_idle_finish(unsigned long val) val 40 drivers/cpuidle/cpuidle-powernv.c u64 val; val 147 drivers/cpuidle/cpuidle-powernv.c power9_idle_type(stop_psscr_table[index].val, val 246 drivers/cpuidle/cpuidle-powernv.c stop_psscr_table[index].val = psscr_val; val 80 drivers/cpuidle/governors/haltpoll.c unsigned int val; val 87 drivers/cpuidle/governors/haltpoll.c val = dev->poll_limit_ns * guest_halt_poll_grow; val 89 drivers/cpuidle/governors/haltpoll.c if (val < guest_halt_poll_grow_start) val 90 drivers/cpuidle/governors/haltpoll.c val = guest_halt_poll_grow_start; val 91 drivers/cpuidle/governors/haltpoll.c if (val > guest_halt_poll_ns) val 92 drivers/cpuidle/governors/haltpoll.c val = guest_halt_poll_ns; val 94 drivers/cpuidle/governors/haltpoll.c dev->poll_limit_ns = val; val 99 drivers/cpuidle/governors/haltpoll.c val = dev->poll_limit_ns; val 101 drivers/cpuidle/governors/haltpoll.c val = 0; val 103 drivers/cpuidle/governors/haltpoll.c val /= shrink; val 104 drivers/cpuidle/governors/haltpoll.c dev->poll_limit_ns = val; val 381 drivers/cpuidle/governors/teo.c unsigned int val = cpu_data->intervals[i]; val 383 drivers/cpuidle/governors/teo.c if (val >= duration_us) val 387 drivers/cpuidle/governors/teo.c sum += val; val 1129 drivers/crypto/amcc/crypto4xx_core.c u32 val[2]; val 1142 drivers/crypto/amcc/crypto4xx_core.c val[0] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_0); val 1143 drivers/crypto/amcc/crypto4xx_core.c val[1] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_1); val 1150 drivers/crypto/amcc/crypto4xx_core.c memcpy(data, &val, 8); val 1155 drivers/crypto/amcc/crypto4xx_core.c memcpy(data, &val, max - curr); val 515 drivers/crypto/bcm/util.c void format_value_ccm(unsigned int val, u8 *buf, u8 len) val 524 drivers/crypto/bcm/util.c buf[len - i - 1] = (val >> (8 * i)) & 0xff; val 97 drivers/crypto/bcm/util.h void format_value_ccm(unsigned int val, u8 *buf, u8 len); val 355 drivers/crypto/caam/ctrl.c u32 val; val 371 drivers/crypto/caam/ctrl.c val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) val 373 drivers/crypto/caam/ctrl.c if (ent_delay <= val) val 376 drivers/crypto/caam/ctrl.c val = rd_reg32(&r4tst->rtsdctl); val 377 drivers/crypto/caam/ctrl.c val = (val & ~RTSDCTL_ENT_DLY_MASK) | val 379 drivers/crypto/caam/ctrl.c wr_reg32(&r4tst->rtsdctl, val); val 385 drivers/crypto/caam/ctrl.c val = rd_reg32(&r4tst->rtmctl); val 252 drivers/crypto/caam/desc_constr.h u32 val = caam32_to_cpu(*move_cmd); val 254 drivers/crypto/caam/desc_constr.h val &= ~MOVE_OFFSET_MASK; val 255 drivers/crypto/caam/desc_constr.h val |= (desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) & MOVE_OFFSET_MASK; val 256 drivers/crypto/caam/desc_constr.h *move_cmd = cpu_to_caam32(val); val 50 drivers/crypto/caam/dpseci_cmd.h #define dpseci_set_field(var, field, val) \ val 51 drivers/crypto/caam/dpseci_cmd.h ((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field))) val 202 drivers/crypto/caam/intern.h static int caam_debugfs_u64_get(void *data, u64 *val) val 204 drivers/crypto/caam/intern.h *val = caam64_to_cpu(*(u64 *)data); val 208 drivers/crypto/caam/intern.h static int caam_debugfs_u32_get(void *data, u64 *val) val 210 drivers/crypto/caam/intern.h *val = caam32_to_cpu(*(u32 *)data); val 653 drivers/crypto/caam/qi.c const u64 val = (u64)cpumask_weight(qman_affine_cpus()) * val 668 drivers/crypto/caam/qi.c qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1); val 677 drivers/crypto/caam/qi.c dev_dbg(qidev, "Congestion threshold set to %llu\n", val); val 77 drivers/crypto/caam/regs.h static inline u##len caam##len ## _to_cpu(u##len val) \ val 80 drivers/crypto/caam/regs.h return le##len ## _to_cpu((__force __le##len)val); \ val 82 drivers/crypto/caam/regs.h return be##len ## _to_cpu((__force __be##len)val); \ val 86 drivers/crypto/caam/regs.h static inline u##len cpu_to_caam##len(u##len val) \ val 89 drivers/crypto/caam/regs.h return (__force u##len)cpu_to_le##len(val); \ val 91 drivers/crypto/caam/regs.h return (__force u##len)cpu_to_be##len(val); \ val 260 drivers/crypto/caam/regs.h static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val) val 265 drivers/crypto/caam/regs.h inpentry[hw_idx] = val; val 269 drivers/crypto/caam/regs.h inpentry[hw_idx] = val; val 144 drivers/crypto/cavium/cpt/cpt_common.h u64 val) val 146 drivers/crypto/cavium/cpt/cpt_common.h writeq(val, hw_addr + offset); val 128 drivers/crypto/cavium/cpt/cptvf.h void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, u32 val); val 365 drivers/crypto/cavium/cpt/cptvf_main.c static void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val) val 370 drivers/crypto/cavium/cpt/cptvf_main.c vqx_ctl.s.ena = val; val 374 drivers/crypto/cavium/cpt/cptvf_main.c void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, u32 val) val 380 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */ val 385 drivers/crypto/cavium/cpt/cptvf_main.c static void cptvf_write_vq_inprog(struct cpt_vf *cptvf, u8 val) val 390 drivers/crypto/cavium/cpt/cptvf_main.c vqx_inprg.s.inflight = val; val 394 drivers/crypto/cavium/cpt/cptvf_main.c static void cptvf_write_vq_done_numwait(struct cpt_vf *cptvf, u32 val) val 400 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dwait.s.num_wait = val; val 633 drivers/crypto/cavium/cpt/cptvf_main.c static void cptvf_write_vq_saddr(struct cpt_vf *cptvf, u64 val) val 637 drivers/crypto/cavium/cpt/cptvf_main.c vqx_saddr.u = val; val 58 drivers/crypto/cavium/zip/zip_main.c void zip_reg_write(u64 val, u64 __iomem *addr) val 60 drivers/crypto/cavium/zip/zip_main.c writeq(val, addr); val 465 drivers/crypto/cavium/zip/zip_main.c u64 val = 0ull; val 482 drivers/crypto/cavium/zip/zip_main.c val = zip_reg_read((zip->reg_base + val 484 drivers/crypto/cavium/zip/zip_main.c pending += val >> 32 & 0xffffff; val 487 drivers/crypto/cavium/zip/zip_main.c val = atomic64_read(&st->comp_req_complete); val 488 drivers/crypto/cavium/zip/zip_main.c avg_chunk = (val) ? atomic64_read(&st->comp_in_bytes) / val : 0; val 490 drivers/crypto/cavium/zip/zip_main.c val = atomic64_read(&st->comp_out_bytes); val 491 drivers/crypto/cavium/zip/zip_main.c avg_cr = (val) ? atomic64_read(&st->comp_in_bytes) / val : 0; val 563 drivers/crypto/cavium/zip/zip_main.c u64 val = 0; val 576 drivers/crypto/cavium/zip/zip_main.c val = zip_reg_read((zip_dev[index]->reg_base + val 579 drivers/crypto/cavium/zip/zip_main.c zipregs[i].reg_name, val); val 115 drivers/crypto/cavium/zip/zip_main.h void zip_reg_write(u64 val, u64 __iomem *addr); val 106 drivers/crypto/ccree/cc_driver.c __le32 val; val 112 drivers/crypto/ccree/cc_driver.c return le32_to_cpu(idr.val); val 196 drivers/crypto/ccree/cc_driver.c unsigned int val; val 207 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE)); val 208 drivers/crypto/ccree/cc_driver.c if (val & CC_NVM_IS_IDLE_MASK) { val 221 drivers/crypto/ccree/cc_driver.c unsigned int val, cache_params; val 227 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); val 228 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK); val 234 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(HOST_IRR)); val 235 drivers/crypto/ccree/cc_driver.c dev_dbg(dev, "IRR=0x%08X\n", val); val 236 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(HOST_ICR), val); val 239 drivers/crypto/ccree/cc_driver.c val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK; val 242 drivers/crypto/ccree/cc_driver.c val |= CC_GPR0_IRQ_MASK; val 244 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val); val 248 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); val 251 drivers/crypto/ccree/cc_driver.c dev_dbg(dev, "Cache params previous: 0x%08X\n", val); val 254 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); val 258 drivers/crypto/ccree/cc_driver.c val, cache_params); val 269 drivers/crypto/ccree/cc_driver.c u32 val, hw_rev_pidr, sig_cidr; val 379 drivers/crypto/ccree/cc_driver.c val = cc_ioread(new_drvdata, new_drvdata->sig_offset); val 380 drivers/crypto/ccree/cc_driver.c if (val != hw_rev->sig) { val 382 drivers/crypto/ccree/cc_driver.c val, hw_rev->sig); val 386 drivers/crypto/ccree/cc_driver.c sig_cidr = val; val 390 drivers/crypto/ccree/cc_driver.c val = cc_read_idr(new_drvdata, pidr_0124_offsets); val 391 drivers/crypto/ccree/cc_driver.c if (val != hw_rev->pidr_0124) { val 393 drivers/crypto/ccree/cc_driver.c val, hw_rev->pidr_0124); val 397 drivers/crypto/ccree/cc_driver.c hw_rev_pidr = val; val 399 drivers/crypto/ccree/cc_driver.c val = cc_read_idr(new_drvdata, cidr_0123_offsets); val 400 drivers/crypto/ccree/cc_driver.c if (val != hw_rev->cidr_0123) { val 402 drivers/crypto/ccree/cc_driver.c val, hw_rev->cidr_0123); val 406 drivers/crypto/ccree/cc_driver.c sig_cidr = val; val 409 drivers/crypto/ccree/cc_driver.c val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS)); val 410 drivers/crypto/ccree/cc_driver.c switch (val) { val 427 drivers/crypto/ccree/cc_driver.c val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED)); val 428 drivers/crypto/ccree/cc_driver.c val &= CC_SECURITY_DISABLED_MASK; val 429 drivers/crypto/ccree/cc_driver.c new_drvdata->sec_disabled |= !!val; val 222 drivers/crypto/ccree/cc_driver.h static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val) val 224 drivers/crypto/ccree/cc_driver.h iowrite32(val, (drvdata->cc_base + reg)); val 42 drivers/crypto/ccree/cc_fips.c int val = CC_FIPS_SYNC_REE_STATUS; val 47 drivers/crypto/ccree/cc_fips.c val |= (status ? CC_FIPS_SYNC_MODULE_OK : CC_FIPS_SYNC_MODULE_ERROR); val 49 drivers/crypto/ccree/cc_fips.c cc_iowrite(drvdata, CC_REG(HOST_GPR0), val); val 115 drivers/crypto/ccree/cc_fips.c u32 irq, val; val 126 drivers/crypto/ccree/cc_fips.c val = (CC_REG(HOST_IMR) & ~irq); val 127 drivers/crypto/ccree/cc_fips.c cc_iowrite(drvdata, CC_REG(HOST_IMR), val); val 308 drivers/crypto/ccree/cc_hw_queue_defs.h static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) val 310 drivers/crypto/ccree/cc_hw_queue_defs.h pdesc->word[0] = val; val 407 drivers/crypto/ccree/cc_hw_queue_defs.h static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) val 409 drivers/crypto/ccree/cc_hw_queue_defs.h pdesc->word[2] = val; val 483 drivers/crypto/chelsio/chtls/chtls.h int chtls_set_tcb_tflag(struct sock *sk, unsigned int bit_pos, int val); val 25 drivers/crypto/chelsio/chtls/chtls_hw.c u64 mask, u64 val, u8 cookie, int no_reply) val 35 drivers/crypto/chelsio/chtls/chtls_hw.c req->val = cpu_to_be64(val); val 42 drivers/crypto/chelsio/chtls/chtls_hw.c u64 mask, u64 val, u8 cookie, int no_reply) val 53 drivers/crypto/chelsio/chtls/chtls_hw.c __set_tcb_field_direct(csk, req, word, mask, val, cookie, no_reply); val 61 drivers/crypto/chelsio/chtls/chtls_hw.c static int chtls_set_tcb_field(struct sock *sk, u16 word, u64 mask, u64 val) val 80 drivers/crypto/chelsio/chtls/chtls_hw.c __set_tcb_field(sk, skb, word, mask, val, 0, 1); val 94 drivers/crypto/chelsio/chtls/chtls_hw.c int chtls_set_tcb_tflag(struct sock *sk, unsigned int bit_pos, int val) val 97 drivers/crypto/chelsio/chtls/chtls_hw.c (u64)val << bit_pos); val 110 drivers/crypto/chelsio/chtls/chtls_hw.c static int chtls_set_tcb_quiesce(struct sock *sk, int val) val 113 drivers/crypto/chelsio/chtls/chtls_hw.c TF_RX_QUIESCE_V(val)); val 179 drivers/crypto/chelsio/chtls/chtls_io.c flowc->mnemval[paramidx].val = cpu_to_be32(__v); \ val 92 drivers/crypto/exynos-rng.c static void exynos_rng_writel(struct exynos_rng_dev *rng, u32 val, u32 offset) val 94 drivers/crypto/exynos-rng.c writel_relaxed(val, rng->mem + offset); val 100 drivers/crypto/exynos-rng.c u32 val; val 112 drivers/crypto/exynos-rng.c val = seed[i] << 24; val 113 drivers/crypto/exynos-rng.c val |= seed[i + 1] << 16; val 114 drivers/crypto/exynos-rng.c val |= seed[i + 2] << 8; val 115 drivers/crypto/exynos-rng.c val |= seed[i + 3] << 0; val 117 drivers/crypto/exynos-rng.c exynos_rng_writel(rng, val, EXYNOS_RNG_SEED(seed_reg)); val 120 drivers/crypto/exynos-rng.c val = exynos_rng_readl(rng, EXYNOS_RNG_STATUS); val 121 drivers/crypto/exynos-rng.c if (!(val & EXYNOS_RNG_STATUS_SEED_SETTING_DONE)) { val 638 drivers/crypto/hifn_795x.c static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) val 640 drivers/crypto/hifn_795x.c writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); val 643 drivers/crypto/hifn_795x.c static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) val 645 drivers/crypto/hifn_795x.c writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); val 321 drivers/crypto/hisilicon/qm.c u32 val; val 324 drivers/crypto/hisilicon/qm.c val, !((val >> QM_MB_BUSY_SHIFT) & val 423 drivers/crypto/hisilicon/qm.c u32 val; val 426 drivers/crypto/hisilicon/qm.c return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val, val 427 drivers/crypto/hisilicon/qm.c val & BIT(0), 10, 1000); val 703 drivers/crypto/hisilicon/qm.c unsigned int val; val 706 drivers/crypto/hisilicon/qm.c ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val, val 707 drivers/crypto/hisilicon/qm.c val & BIT(0), 10, 1000); val 720 drivers/crypto/hisilicon/qm.c return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val, val 721 drivers/crypto/hisilicon/qm.c val & BIT(0), 10, 1000); val 771 drivers/crypto/hisilicon/qm.c static int current_q_write(struct debugfs_file *file, u32 val) val 776 drivers/crypto/hisilicon/qm.c if (val >= qm->debug.curr_qm_qp_num) val 779 drivers/crypto/hisilicon/qm.c tmp = val << QM_DFX_QN_SHIFT | val 783 drivers/crypto/hisilicon/qm.c tmp = val << QM_DFX_QN_SHIFT | val 816 drivers/crypto/hisilicon/qm.c u32 val; val 822 drivers/crypto/hisilicon/qm.c val = current_q_read(file); val 825 drivers/crypto/hisilicon/qm.c val = clear_enable_read(file); val 832 drivers/crypto/hisilicon/qm.c ret = sprintf(tbuf, "%u\n", val); val 841 drivers/crypto/hisilicon/qm.c unsigned long val; val 857 drivers/crypto/hisilicon/qm.c if (kstrtoul(tbuf, 0, &val)) val 863 drivers/crypto/hisilicon/qm.c ret = current_q_write(file, val); val 868 drivers/crypto/hisilicon/qm.c ret = clear_enable_write(file, val); val 936 drivers/crypto/hisilicon/qm.c u32 val; val 944 drivers/crypto/hisilicon/qm.c val = readl(qm->io_base + regs->reg_offset); val 945 drivers/crypto/hisilicon/qm.c seq_printf(s, "%s= 0x%08x\n", regs->reg_name, val); val 1384 drivers/crypto/hisilicon/qm.c unsigned int val; val 1389 drivers/crypto/hisilicon/qm.c val, val & BIT(0), 10, 1000)) val 13 drivers/crypto/hisilicon/sgl.c static int acc_sgl_sge_set(const char *val, const struct kernel_param *kp) val 18 drivers/crypto/hisilicon/sgl.c if (!val) val 21 drivers/crypto/hisilicon/sgl.c ret = kstrtou32(val, 10, &n); val 25 drivers/crypto/hisilicon/sgl.c return param_set_int(val, kp); val 81 drivers/crypto/hisilicon/zip/zip_crypto.c u32 val; val 83 drivers/crypto/hisilicon/zip/zip_crypto.c val = (sqe->dw9) & ~HZIP_BUF_TYPE_M; val 84 drivers/crypto/hisilicon/zip/zip_crypto.c val |= FIELD_PREP(HZIP_BUF_TYPE_M, buf_type); val 85 drivers/crypto/hisilicon/zip/zip_crypto.c sqe->dw9 = val; val 222 drivers/crypto/hisilicon/zip/zip_main.c static int pf_q_num_set(const char *val, const struct kernel_param *kp) val 230 drivers/crypto/hisilicon/zip/zip_main.c if (!val) val 251 drivers/crypto/hisilicon/zip/zip_main.c ret = kstrtou32(val, 10, &n); val 255 drivers/crypto/hisilicon/zip/zip_main.c return param_set_int(val, kp); val 370 drivers/crypto/hisilicon/zip/zip_main.c static int current_qm_write(struct ctrl_debug_file *file, u32 val) val 377 drivers/crypto/hisilicon/zip/zip_main.c if (val > ctrl->num_vfs) val 381 drivers/crypto/hisilicon/zip/zip_main.c if (val == 0) { val 385 drivers/crypto/hisilicon/zip/zip_main.c if (val == ctrl->num_vfs) val 392 drivers/crypto/hisilicon/zip/zip_main.c writel(val, qm->io_base + QM_DFX_MB_CNT_VF); val 393 drivers/crypto/hisilicon/zip/zip_main.c writel(val, qm->io_base + QM_DFX_DB_CNT_VF); val 395 drivers/crypto/hisilicon/zip/zip_main.c tmp = val | val 399 drivers/crypto/hisilicon/zip/zip_main.c tmp = val | val 414 drivers/crypto/hisilicon/zip/zip_main.c static int clear_enable_write(struct ctrl_debug_file *file, u32 val) val 419 drivers/crypto/hisilicon/zip/zip_main.c if (val != 1 && val != 0) val 423 drivers/crypto/hisilicon/zip/zip_main.c ~SOFT_CTRL_CNT_CLR_CE_BIT) | val; val 434 drivers/crypto/hisilicon/zip/zip_main.c u32 val; val 440 drivers/crypto/hisilicon/zip/zip_main.c val = current_qm_read(file); val 443 drivers/crypto/hisilicon/zip/zip_main.c val = clear_enable_read(file); val 450 drivers/crypto/hisilicon/zip/zip_main.c ret = sprintf(tbuf, "%u\n", val); val 459 drivers/crypto/hisilicon/zip/zip_main.c unsigned long val; val 473 drivers/crypto/hisilicon/zip/zip_main.c if (kstrtoul(tbuf, 0, &val)) val 479 drivers/crypto/hisilicon/zip/zip_main.c ret = current_qm_write(file, val); val 484 drivers/crypto/hisilicon/zip/zip_main.c ret = clear_enable_write(file, val); val 64 drivers/crypto/inside-secure/safexcel.c u32 val; val 69 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CS_RAM_CTRL); val 70 drivers/crypto/inside-secure/safexcel.c val = (val & ~EIP197_CS_BANKSEL_MASK) | val 72 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_CS_RAM_CTRL); val 80 drivers/crypto/inside-secure/safexcel.c u32 val, addrhi, addrlo, addrmid; val 106 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CLASSIFICATION_RAMS + val 109 drivers/crypto/inside-secure/safexcel.c if (val == ((addrmid | (addrlo << 16)) & probemask)) { val 124 drivers/crypto/inside-secure/safexcel.c u32 htable_offset, val, offset; val 134 drivers/crypto/inside-secure/safexcel.c val = EIP197_CS_RC_NEXT(i + 1) | EIP197_CS_RC_PREV(i - 1); val 136 drivers/crypto/inside-secure/safexcel.c val |= EIP197_CS_RC_PREV(EIP197_RC_NULL); val 138 drivers/crypto/inside-secure/safexcel.c val |= EIP197_CS_RC_NEXT(EIP197_RC_NULL); val 139 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + offset + 4); val 155 drivers/crypto/inside-secure/safexcel.c u32 val, dsize, asize; val 167 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CS_RAM_CTRL); val 168 drivers/crypto/inside-secure/safexcel.c val &= ~EIP197_TRC_ENABLE_MASK; val 169 drivers/crypto/inside-secure/safexcel.c val |= EIP197_TRC_ENABLE_0 | EIP197_CS_BANKSEL_MASK; val 170 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_CS_RAM_CTRL); val 171 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CS_RAM_CTRL); val 172 drivers/crypto/inside-secure/safexcel.c maxbanks = ((val&EIP197_CS_BANKSEL_MASK)>>EIP197_CS_BANKSEL_OFS) + 1; val 181 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_TRC_PARAMS); val 182 drivers/crypto/inside-secure/safexcel.c val |= EIP197_TRC_PARAMS_SW_RESET | EIP197_TRC_PARAMS_DATA_ACCESS; val 183 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_PARAMS); val 193 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_TRC_PARAMS); val 195 drivers/crypto/inside-secure/safexcel.c val &= ~(EIP197_TRC_PARAMS_DATA_ACCESS | EIP197_CS_BANKSEL_MASK); val 196 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_PARAMS); val 232 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CS_RAM_CTRL); val 233 drivers/crypto/inside-secure/safexcel.c val &= ~EIP197_TRC_ENABLE_MASK; val 234 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_CS_RAM_CTRL); val 237 drivers/crypto/inside-secure/safexcel.c val = EIP197_TRC_FREECHAIN_HEAD_PTR(0) | val 239 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_FREECHAIN); val 242 drivers/crypto/inside-secure/safexcel.c val = EIP197_TRC_PARAMS2_RC_SZ_SMALL(cs_trc_rec_wc) | val 244 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_PARAMS2); val 247 drivers/crypto/inside-secure/safexcel.c val = EIP197_TRC_PARAMS_RC_SZ_LARGE(cs_trc_lg_rec_wc) | val 250 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_PARAMS); val 259 drivers/crypto/inside-secure/safexcel.c u32 val; val 267 drivers/crypto/inside-secure/safexcel.c val = readl(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe)); val 268 drivers/crypto/inside-secure/safexcel.c val |= EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER | val 272 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe)); val 348 drivers/crypto/inside-secure/safexcel.c u32 val; val 356 drivers/crypto/inside-secure/safexcel.c val = 0; val 358 drivers/crypto/inside-secure/safexcel.c val = EIP197_PE_ICE_UENG_START_OFFSET((ifppsz - 1) & val 361 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe)); val 365 drivers/crypto/inside-secure/safexcel.c val = 0; val 367 drivers/crypto/inside-secure/safexcel.c val = EIP197_PE_ICE_UENG_START_OFFSET((ipuesz - 1) & val 370 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe)); val 457 drivers/crypto/inside-secure/safexcel.c u32 cd_size_rnd, val; val 491 drivers/crypto/inside-secure/safexcel.c val = EIP197_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS); val 492 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS); val 493 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_DMA_CFG); val 505 drivers/crypto/inside-secure/safexcel.c u32 rd_size_rnd, val; val 540 drivers/crypto/inside-secure/safexcel.c val = EIP197_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS); val 541 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS); val 542 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_xDR_WR_RES_BUF | EIP197_HIA_xDR_WR_CTRL_BUF; val 543 drivers/crypto/inside-secure/safexcel.c writel(val, val 551 drivers/crypto/inside-secure/safexcel.c val = readl(EIP197_HIA_AIC_R(priv) + EIP197_HIA_AIC_R_ENABLE_CTRL(i)); val 552 drivers/crypto/inside-secure/safexcel.c val |= EIP197_RDR_IRQ(i); val 553 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_HIA_AIC_R(priv) + EIP197_HIA_AIC_R_ENABLE_CTRL(i)); val 561 drivers/crypto/inside-secure/safexcel.c u32 val; val 572 drivers/crypto/inside-secure/safexcel.c val = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); val 573 drivers/crypto/inside-secure/safexcel.c val |= EIP197_MST_CTRL_TX_MAX_CMD(5); val 574 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); val 604 drivers/crypto/inside-secure/safexcel.c val = EIP197_HIA_DFE_CFG_DIS_DEBUG; val 605 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(6) | val 607 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(6) | val 609 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS); val 610 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(RD_CACHE_3BITS); val 611 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_HIA_DFE(priv) + EIP197_HIA_DFE_CFG(pe)); val 642 drivers/crypto/inside-secure/safexcel.c val = EIP197_HIA_DSE_CFG_DIS_DEBUG; val 643 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) | val 645 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS); val 646 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE; val 651 drivers/crypto/inside-secure/safexcel.c val |= EIP197_HIA_DSE_CFG_EN_SINGLE_WR; val 652 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_HIA_DSE(priv) + EIP197_HIA_DSE_CFG(pe)); val 665 drivers/crypto/inside-secure/safexcel.c val = EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES | val 668 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_PE(priv) + EIP197_PE_EIP96_TOKEN_CTRL(pe)); val 1243 drivers/crypto/inside-secure/safexcel.c u32 val, mask = 0; val 1245 drivers/crypto/inside-secure/safexcel.c val = readl(EIP197_HIA_AIC_G(priv) + EIP197_HIA_OPTIONS); val 1255 drivers/crypto/inside-secure/safexcel.c priv->config.pes = (val >> EIP197_N_PES_OFFSET) & mask; val 1257 drivers/crypto/inside-secure/safexcel.c priv->config.rings = min_t(u32, val & GENMASK(3, 0), max_rings); val 1259 drivers/crypto/inside-secure/safexcel.c val = (val & GENMASK(27, 25)) >> 25; val 1260 drivers/crypto/inside-secure/safexcel.c mask = BIT(val) - 1; val 1312 drivers/crypto/inside-secure/safexcel.c u32 peid, version, mask, val, hiaopt; val 1362 drivers/crypto/inside-secure/safexcel.c val = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); val 1363 drivers/crypto/inside-secure/safexcel.c val = val ^ (mask >> 24); /* toggle byte swap bits */ val 1364 drivers/crypto/inside-secure/safexcel.c writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); val 1681 drivers/crypto/inside-secure/safexcel.c u32 val; val 1721 drivers/crypto/inside-secure/safexcel.c val = readl(pciebase + EIP197_XLX_IRQ_BLOCK_ID_ADDR); val 1722 drivers/crypto/inside-secure/safexcel.c if ((val >> 16) == EIP197_XLX_IRQ_BLOCK_ID_VALUE) { val 1724 drivers/crypto/inside-secure/safexcel.c (val & 0xff)); val 1741 drivers/crypto/inside-secure/safexcel.c val); val 1179 drivers/crypto/mediatek/mtk-aes.c u32 val = mtk_aes_read(cryp, RDR_STAT(aes->id)); val 1181 drivers/crypto/mediatek/mtk-aes.c mtk_aes_write(cryp, RDR_STAT(aes->id), val); val 165 drivers/crypto/mediatek/mtk-platform.c u32 val; val 168 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + DFE_THR_STAT); val 169 drivers/crypto/mediatek/mtk-platform.c if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE) { val 170 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + DSE_THR_STAT); val 171 drivers/crypto/mediatek/mtk-platform.c if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE) val 305 drivers/crypto/mediatek/mtk-platform.c u32 val; val 318 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + HIA_MST_CTRL); val 319 drivers/crypto/mediatek/mtk-platform.c val &= ~MTK_BURST_SIZE_MSK; val 320 drivers/crypto/mediatek/mtk-platform.c val |= MTK_BURST_SIZE(5); val 321 drivers/crypto/mediatek/mtk-platform.c writel(val, cryp->base + HIA_MST_CTRL); val 357 drivers/crypto/mediatek/mtk-platform.c u32 val; val 360 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + AIC_G_VERSION); val 362 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + AIC_VERSION(hw)); val 364 drivers/crypto/mediatek/mtk-platform.c val &= MTK_AIC_VER_MSK; val 365 drivers/crypto/mediatek/mtk-platform.c if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12) val 369 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + AIC_G_OPTIONS); val 371 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + AIC_OPTIONS(hw)); val 373 drivers/crypto/mediatek/mtk-platform.c val &= MTK_AIC_INT_MSK; val 374 drivers/crypto/mediatek/mtk-platform.c if (!val || val > 32) val 1189 drivers/crypto/mediatek/mtk-sha.c u32 val = mtk_sha_read(cryp, RDR_STAT(sha->id)); val 1191 drivers/crypto/mediatek/mtk-sha.c mtk_sha_write(cryp, RDR_STAT(sha->id), val); val 226 drivers/crypto/omap-aes-gcm.c int i, val; val 237 drivers/crypto/omap-aes-gcm.c val = omap_aes_read(dd, AES_REG_TAG_N(dd, i)); val 238 drivers/crypto/omap-aes-gcm.c auth_tag[i] = val ^ auth_tag[i]; val 82 drivers/crypto/omap-aes.c u32 val; val 84 drivers/crypto/omap-aes.c val = omap_aes_read(dd, offset); val 85 drivers/crypto/omap-aes.c val &= ~mask; val 86 drivers/crypto/omap-aes.c val |= value; val 87 drivers/crypto/omap-aes.c omap_aes_write(dd, offset, val); val 127 drivers/crypto/omap-aes.c u32 val; val 153 drivers/crypto/omap-aes.c val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); val 155 drivers/crypto/omap-aes.c val |= AES_REG_CTRL_CBC; val 158 drivers/crypto/omap-aes.c val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; val 161 drivers/crypto/omap-aes.c val |= AES_REG_CTRL_GCM; val 164 drivers/crypto/omap-aes.c val |= AES_REG_CTRL_DIRECTION; val 166 drivers/crypto/omap-aes.c omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); val 173 drivers/crypto/omap-aes.c u32 mask, val; val 175 drivers/crypto/omap-aes.c val = dd->pdata->dma_start; val 178 drivers/crypto/omap-aes.c val |= dd->pdata->dma_enable_out; val 180 drivers/crypto/omap-aes.c val |= dd->pdata->dma_enable_in; val 185 drivers/crypto/omap-aes.c omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); val 24 drivers/crypto/omap-aes.h #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) val 207 drivers/crypto/omap-des.c u32 val; val 209 drivers/crypto/omap-des.c val = omap_des_read(dd, offset); val 210 drivers/crypto/omap-des.c val &= ~mask; val 211 drivers/crypto/omap-des.c val |= value; val 212 drivers/crypto/omap-des.c omap_des_write(dd, offset, val); val 250 drivers/crypto/omap-des.c u32 val = 0, mask = 0; val 268 drivers/crypto/omap-des.c val |= DES_REG_CTRL_CBC; val 270 drivers/crypto/omap-des.c val |= DES_REG_CTRL_DIRECTION; val 272 drivers/crypto/omap-des.c val |= DES_REG_CTRL_TDES; val 276 drivers/crypto/omap-des.c omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask); val 283 drivers/crypto/omap-des.c u32 mask, val; val 287 drivers/crypto/omap-des.c val = dd->pdata->dma_start; val 290 drivers/crypto/omap-des.c val |= dd->pdata->dma_enable_out; val 292 drivers/crypto/omap-des.c val |= dd->pdata->dma_enable_in; val 297 drivers/crypto/omap-des.c omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask); val 261 drivers/crypto/omap-sham.c u32 val; val 263 drivers/crypto/omap-sham.c val = omap_sham_read(dd, address); val 264 drivers/crypto/omap-sham.c val &= ~mask; val 265 drivers/crypto/omap-sham.c val |= value; val 266 drivers/crypto/omap-sham.c omap_sham_write(dd, address, val); val 387 drivers/crypto/omap-sham.c u32 val = length << 5, mask; val 400 drivers/crypto/omap-sham.c val |= SHA_REG_CTRL_ALGO; val 402 drivers/crypto/omap-sham.c val |= SHA_REG_CTRL_ALGO_CONST; val 404 drivers/crypto/omap-sham.c val |= SHA_REG_CTRL_CLOSE_HASH; val 409 drivers/crypto/omap-sham.c omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); val 456 drivers/crypto/omap-sham.c u32 val, mask; val 463 drivers/crypto/omap-sham.c val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); val 470 drivers/crypto/omap-sham.c val |= SHA_REG_MODE_ALGO_CONSTANT; val 475 drivers/crypto/omap-sham.c val |= SHA_REG_MODE_HMAC_KEY_PROC; val 485 drivers/crypto/omap-sham.c val |= SHA_REG_MODE_CLOSE_HASH; val 488 drivers/crypto/omap-sham.c val |= SHA_REG_MODE_HMAC_OUTER_HASH; val 495 drivers/crypto/omap-sham.c dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); val 496 drivers/crypto/omap-sham.c omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); val 157 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c unsigned int val, i; val 161 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i)); val 162 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c val |= ADF_C3XXX_ENABLE_AE_ECC_ERR; val 163 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val); val 164 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i)); val 165 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c val |= ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR; val 166 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val); val 171 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i)); val 172 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c val |= ADF_C3XXX_ERRSSMSH_EN; val 173 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val); val 174 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i)); val 175 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c val |= ADF_C3XXX_ERRSSMSH_EN; val 176 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val); val 167 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c unsigned int val, i; val 171 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i)); val 172 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c val |= ADF_C62X_ENABLE_AE_ECC_ERR; val 173 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val); val 174 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i)); val 175 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c val |= ADF_C62X_ENABLE_AE_ECC_PARITY_CORR; val 176 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val); val 181 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i)); val 182 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c val |= ADF_C62X_ERRSSMSH_EN; val 183 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val); val 184 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i)); val 185 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c val |= ADF_C62X_ERRSSMSH_EN; val 186 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val); val 198 drivers/crypto/qat/qat_common/adf_accel_devices.h #define ADF_CSR_WR(csr_base, csr_offset, val) \ val 199 drivers/crypto/qat/qat_common/adf_accel_devices.h __raw_writel(val, csr_base + csr_offset) val 75 drivers/crypto/qat/qat_common/adf_cfg.c seq_printf(sfile, "%s = %s\n", ptr->key, ptr->val); val 249 drivers/crypto/qat/qat_common/adf_cfg.c char *val) val 257 drivers/crypto/qat/qat_common/adf_cfg.c memcpy(val, keyval->val, ADF_CFG_MAX_VAL_LEN_IN_BYTES); val 279 drivers/crypto/qat/qat_common/adf_cfg.c const char *key, const void *val, val 297 drivers/crypto/qat/qat_common/adf_cfg.c snprintf(key_val->val, ADF_CFG_MAX_VAL_LEN_IN_BYTES, val 298 drivers/crypto/qat/qat_common/adf_cfg.c "%ld", (*((long *)val))); val 300 drivers/crypto/qat/qat_common/adf_cfg.c strlcpy(key_val->val, (char *)val, sizeof(key_val->val)); val 302 drivers/crypto/qat/qat_common/adf_cfg.c snprintf(key_val->val, ADF_CFG_MAX_VAL_LEN_IN_BYTES, val 303 drivers/crypto/qat/qat_common/adf_cfg.c "0x%lx", (unsigned long)val); val 59 drivers/crypto/qat/qat_common/adf_cfg.h char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES]; val 82 drivers/crypto/qat/qat_common/adf_cfg.h const char *key, const void *val, val 55 drivers/crypto/qat/qat_common/adf_cfg_user.h char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES]; val 156 drivers/crypto/qat/qat_common/adf_ctl_drv.c long *ptr = (long *)key_val->val; val 157 drivers/crypto/qat/qat_common/adf_ctl_drv.c long val = *ptr; val 160 drivers/crypto/qat/qat_common/adf_ctl_drv.c key_val->key, (void *)val, val 168 drivers/crypto/qat/qat_common/adf_ctl_drv.c key_val->key, key_val->val, val 132 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c u32 val, pf2vf_offset, count = 0; val 160 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); val 161 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if ((val & remote_in_use_mask) == remote_in_use_pattern) { val 176 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); val 177 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if ((val & local_in_use_mask) != local_in_use_pattern) { val 195 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); val 196 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c } while ((val & int_bit) && (count++ < ADF_IOV_MSG_ACK_MAX_RETRY)); val 198 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if (val & int_bit) { val 200 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c val &= ~int_bit; val 205 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, val & ~local_in_use_mask); val 229 drivers/crypto/qat/qat_common/adf_sriov.c unsigned long val; val 258 drivers/crypto/qat/qat_common/adf_sriov.c val = 0; val 260 drivers/crypto/qat/qat_common/adf_sriov.c ADF_NUM_CY, (void *)&val, ADF_DEC)) val 239 drivers/crypto/qat/qat_common/adf_transport.c char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES]; val 257 drivers/crypto/qat/qat_common/adf_transport.c if (adf_cfg_get_param_value(accel_dev, section, ring_name, val)) { val 262 drivers/crypto/qat/qat_common/adf_transport.c if (kstrtouint(val, 10, &ring_num)) { val 52 drivers/crypto/qat/qat_common/icp_qat_fw.h #define QAT_FIELD_SET(flags, val, bitpos, mask) \ val 54 drivers/crypto/qat/qat_common/icp_qat_fw.h (((val) & (mask)) << (bitpos))) ; } val 167 drivers/crypto/qat/qat_common/icp_qat_fw.h #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \ val 168 drivers/crypto/qat/qat_common/icp_qat_fw.h icp_qat_fw_comn_req_hdr_t.service_type = val val 173 drivers/crypto/qat/qat_common/icp_qat_fw.h #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \ val 174 drivers/crypto/qat/qat_common/icp_qat_fw.h icp_qat_fw_comn_req_hdr_t.service_cmd_id = val val 179 drivers/crypto/qat/qat_common/icp_qat_fw.h #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \ val 180 drivers/crypto/qat/qat_common/icp_qat_fw.h ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) val 190 drivers/crypto/qat/qat_common/icp_qat_fw.h #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \ val 191 drivers/crypto/qat/qat_common/icp_qat_fw.h QAT_FIELD_SET((hdr_t.hdr_flags), (val), \ val 219 drivers/crypto/qat/qat_common/icp_qat_fw.h #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \ val 220 drivers/crypto/qat/qat_common/icp_qat_fw.h QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \ val 223 drivers/crypto/qat/qat_common/icp_qat_fw.h #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \ val 224 drivers/crypto/qat/qat_common/icp_qat_fw.h QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \ val 236 drivers/crypto/qat/qat_common/icp_qat_fw.h #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ val 239 drivers/crypto/qat/qat_common/icp_qat_fw.h ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ val 245 drivers/crypto/qat/qat_common/icp_qat_fw.h #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \ val 248 drivers/crypto/qat/qat_common/icp_qat_fw.h ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); } val 124 drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val) \ val 125 drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h ICP_QAT_FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val) val 186 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \ val 187 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \ val 190 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \ val 191 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \ val 194 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \ val 195 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \ val 198 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \ val 199 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \ val 202 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_PROTO_SET(flags, val) \ val 203 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \ val 206 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \ val 207 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \ val 210 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \ val 211 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \ val 214 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \ val 215 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \ val 218 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \ val 219 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \ val 222 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \ val 223 drivers/crypto/qat/qat_common/icp_qat_fw_la.h QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \ val 366 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ val 370 drivers/crypto/qat/qat_common/icp_qat_fw_la.h ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ val 377 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \ val 381 drivers/crypto/qat/qat_common/icp_qat_fw_la.h ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) } val 387 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ val 391 drivers/crypto/qat/qat_common/icp_qat_fw_la.h ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ val 398 drivers/crypto/qat/qat_common/icp_qat_fw_la.h #define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \ val 402 drivers/crypto/qat/qat_common/icp_qat_fw_la.h ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) } val 108 drivers/crypto/qat/qat_common/icp_qat_fw_pke.h #define ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(hdr_t, val) \ val 109 drivers/crypto/qat/qat_common/icp_qat_fw_pke.h QAT_FIELD_SET((hdr_t.hdr_flags), (val), \ val 134 drivers/crypto/qat/qat_common/icp_qat_hal.h #define SET_CAP_CSR(handle, csr, val) \ val 135 drivers/crypto/qat/qat_common/icp_qat_hal.h ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val) val 138 drivers/crypto/qat/qat_common/icp_qat_hal.h #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val) val 144 drivers/crypto/qat/qat_common/icp_qat_hal.h #define SET_AE_CSR(handle, ae, csr, val) \ val 145 drivers/crypto/qat/qat_common/icp_qat_hal.h ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val) val 152 drivers/crypto/qat/qat_common/icp_qat_hal.h #define SET_AE_XFER(handle, ae, reg, val) \ val 153 drivers/crypto/qat/qat_common/icp_qat_hal.h ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val) val 154 drivers/crypto/qat/qat_common/icp_qat_hal.h #define SRAM_WRITE(handle, addr, val) \ val 155 drivers/crypto/qat/qat_common/icp_qat_hal.h ADF_CSR_WR(handle->hal_sram_addr_v, addr, val) val 139 drivers/crypto/qat/qat_common/icp_qat_hw.h #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \ val 140 drivers/crypto/qat/qat_common/icp_qat_hw.h (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS) val 148 drivers/crypto/qat/qat_common/icp_qat_hw.h #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1))) val 230 drivers/crypto/qat/qat_common/icp_qat_hw.h uint32_t val; val 313 drivers/crypto/qat/qat_common/qat_algs.c cipher->aes.cipher_config.val = QAT_AES_HW_CONFIG_ENC(alg, mode); val 399 drivers/crypto/qat/qat_common/qat_algs.c cipher->aes.cipher_config.val = QAT_AES_HW_CONFIG_DEC(alg, mode); val 498 drivers/crypto/qat/qat_common/qat_algs.c enc_cd->aes.cipher_config.val = QAT_AES_HW_CONFIG_ENC(alg, mode); val 513 drivers/crypto/qat/qat_common/qat_algs.c dec_cd->aes.cipher_config.val = val 516 drivers/crypto/qat/qat_common/qat_algs.c dec_cd->aes.cipher_config.val = val 167 drivers/crypto/qat/qat_common/qat_crypto.c unsigned long val; val 174 drivers/crypto/qat/qat_common/qat_crypto.c val = i; val 177 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 183 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 187 drivers/crypto/qat/qat_common/qat_crypto.c val = 128; val 189 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 192 drivers/crypto/qat/qat_common/qat_crypto.c val = 512; val 195 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 198 drivers/crypto/qat/qat_common/qat_crypto.c val = 0; val 201 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 204 drivers/crypto/qat/qat_common/qat_crypto.c val = 2; val 207 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 210 drivers/crypto/qat/qat_common/qat_crypto.c val = 8; val 213 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 216 drivers/crypto/qat/qat_common/qat_crypto.c val = 10; val 219 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 222 drivers/crypto/qat/qat_common/qat_crypto.c val = ADF_COALESCING_DEF_TIME; val 225 drivers/crypto/qat/qat_common/qat_crypto.c key, (void *)&val, ADF_DEC)) val 229 drivers/crypto/qat/qat_common/qat_crypto.c val = i; val 231 drivers/crypto/qat/qat_common/qat_crypto.c ADF_NUM_CY, (void *)&val, ADF_DEC)) val 250 drivers/crypto/qat/qat_common/qat_crypto.c char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES]; val 254 drivers/crypto/qat/qat_common/qat_crypto.c if (adf_cfg_get_param_value(accel_dev, SEC, key, val)) val 257 drivers/crypto/qat/qat_common/qat_crypto.c if (kstrtoul(val, 0, &num_inst)) val 271 drivers/crypto/qat/qat_common/qat_crypto.c if (adf_cfg_get_param_value(accel_dev, SEC, key, val)) val 274 drivers/crypto/qat/qat_common/qat_crypto.c if (kstrtoul(val, 10, &bank)) val 277 drivers/crypto/qat/qat_common/qat_crypto.c if (adf_cfg_get_param_value(accel_dev, SEC, key, val)) val 280 drivers/crypto/qat/qat_common/qat_crypto.c if (kstrtoul(val, 10, &num_msg_sym)) val 286 drivers/crypto/qat/qat_common/qat_crypto.c if (adf_cfg_get_param_value(accel_dev, SEC, key, val)) val 289 drivers/crypto/qat/qat_common/qat_crypto.c if (kstrtoul(val, 10, &num_msg_asym)) val 1184 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int val) val 1209 drivers/crypto/qat/qat_common/qat_hal.c SET_AE_XFER(handle, ae, reg_addr, val); val 1213 drivers/crypto/qat/qat_common/qat_hal.c SET_AE_XFER(handle, ae, (reg_addr + dr_offset), val); val 1281 drivers/crypto/qat/qat_common/qat_hal.c unsigned short nn, unsigned int val) val 1290 drivers/crypto/qat/qat_common/qat_hal.c stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, ICP_NEIGH_REL, nn, val); val 168 drivers/crypto/qat/qat_common/qat_uclo.c unsigned int addr, unsigned int *val, val 172 drivers/crypto/qat/qat_common/qat_uclo.c unsigned char *ptr = (unsigned char *)val; val 185 drivers/crypto/qat/qat_common/qat_uclo.c unsigned int *val, val 189 drivers/crypto/qat/qat_common/qat_uclo.c unsigned char *ptr = (unsigned char *)val; val 179 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c unsigned int val, i; val 183 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); val 184 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR; val 185 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); val 186 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); val 187 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c val |= ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR; val 188 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); val 193 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); val 194 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c val |= ADF_DH895XCC_ERRSSMSH_EN; val 195 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); val 196 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); val 197 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c val |= ADF_DH895XCC_ERRSSMSH_EN; val 198 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); val 25 drivers/crypto/qce/common.c static inline void qce_write(struct qce_device *qce, u32 offset, u32 val) val 27 drivers/crypto/qce/common.c writel(val, qce->base + offset); val 31 drivers/crypto/qce/common.c const u32 *val, unsigned int len) val 36 drivers/crypto/qce/common.c qce_write(qce, offset + i * sizeof(u32), val[i]); val 424 drivers/crypto/qce/common.c u32 val; val 426 drivers/crypto/qce/common.c val = qce_read(qce, REG_VERSION); val 427 drivers/crypto/qce/common.c *major = (val & CORE_MAJOR_REV_MASK) >> CORE_MAJOR_REV_SHIFT; val 428 drivers/crypto/qce/common.c *minor = (val & CORE_MINOR_REV_MASK) >> CORE_MINOR_REV_SHIFT; val 429 drivers/crypto/qce/common.c *step = (val & CORE_STEP_REV_MASK) >> CORE_STEP_REV_SHIFT; val 44 drivers/crypto/qcom-rng.c u32 val; val 48 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_STATUS); val 49 drivers/crypto/qcom-rng.c if (!(val & PRNG_STATUS_DATA_AVAIL)) val 52 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_DATA_OUT); val 53 drivers/crypto/qcom-rng.c if (!val) val 57 drivers/crypto/qcom-rng.c memcpy(data, &val, WORD_SZ); val 62 drivers/crypto/qcom-rng.c memcpy(data, &val, max - currsize); val 100 drivers/crypto/qcom-rng.c u32 val; val 108 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_CONFIG); val 109 drivers/crypto/qcom-rng.c if (val & PRNG_CONFIG_HW_ENABLE) val 112 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_LFSR_CFG); val 113 drivers/crypto/qcom-rng.c val &= ~PRNG_LFSR_CFG_MASK; val 114 drivers/crypto/qcom-rng.c val |= PRNG_LFSR_CFG_CLOCKS; val 115 drivers/crypto/qcom-rng.c writel(val, rng->base + PRNG_LFSR_CFG); val 117 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_CONFIG); val 118 drivers/crypto/qcom-rng.c val |= PRNG_CONFIG_HW_ENABLE; val 119 drivers/crypto/qcom-rng.c writel(val, rng->base + PRNG_CONFIG); val 181 drivers/crypto/rockchip/rk3288_crypto.h #define CRYPTO_WRITE(dev, offset, val) \ val 182 drivers/crypto/rockchip/rk3288_crypto.h writel_relaxed((val), ((dev)->reg + (offset))) val 146 drivers/crypto/s5p-sss.c #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) val 149 drivers/crypto/s5p-sss.c #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ val 234 drivers/crypto/stm32/stm32-cryp.c static inline void stm32_cryp_write(struct stm32_cryp *cryp, u32 ofst, u32 val) val 236 drivers/crypto/stm32/stm32-cryp.c writel_relaxed(val, cryp->regs + ofst); val 113 drivers/crypto/sunxi-ss/sun4i-ss.h #define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f) val 119 drivers/crypto/sunxi-ss/sun4i-ss.h #define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f) val 78 drivers/crypto/talitos.c static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val, val 82 drivers/crypto/talitos.c ptr->j_extent = val; val 85 drivers/crypto/talitos.c static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1) val 88 drivers/crypto/talitos.c ptr->j_extent |= val; val 26 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_WRITE_BIT(reg_name, val, mask) \ val 28 drivers/crypto/ux500/cryp/cryp_p.h ((val) & (mask))), reg_name) val 30 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_TEST_BITS(reg_name, val) \ val 31 drivers/crypto/ux500/cryp/cryp_p.h (readl_relaxed(reg_name) & (val)) val 33 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_PUT_BITS(reg, val, shift, mask) \ val 35 drivers/crypto/ux500/cryp/cryp_p.h (((u32)val << shift) & (mask))), reg) val 104 drivers/crypto/ux500/hash/hash_alg.h #define HASH_PUT_BITS(reg, val, shift, mask) \ val 106 drivers/crypto/ux500/hash/hash_alg.h (((u32)val << shift) & (mask))), reg) val 108 drivers/crypto/ux500/hash/hash_alg.h #define HASH_SET_DIN(val, len) writesl(&device_data->base->din, (val), (len)) val 121 drivers/crypto/ux500/hash/hash_alg.h #define HASH_SET_NBLW(val) \ val 124 drivers/crypto/ux500/hash/hash_alg.h (u32) (val), HASH_STR_NBLW_POS, \ val 64 drivers/devfreq/event/rockchip-dfi.c u32 val; val 68 drivers/devfreq/event/rockchip-dfi.c regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); val 69 drivers/devfreq/event/rockchip-dfi.c ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & val 316 drivers/devfreq/rk3399_dmc.c u32 val; val 379 drivers/devfreq/rk3399_dmc.c regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); val 380 drivers/devfreq/rk3399_dmc.c ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & val 186 drivers/devfreq/tegra30-devfreq.c static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset) val 188 drivers/devfreq/tegra30-devfreq.c writel_relaxed(val, tegra->regs + offset); val 196 drivers/devfreq/tegra30-devfreq.c static void device_writel(struct tegra_devfreq_device *dev, u32 val, val 199 drivers/devfreq/tegra30-devfreq.c writel_relaxed(val, dev->regs + offset); val 202 drivers/devfreq/tegra30-devfreq.c static unsigned long do_percent(unsigned long val, unsigned int pct) val 204 drivers/devfreq/tegra30-devfreq.c return val * pct / 100; val 223 drivers/devfreq/tegra30-devfreq.c u32 val = tegra->cur_freq * ACTMON_SAMPLING_PERIOD; val 225 drivers/devfreq/tegra30-devfreq.c device_writel(dev, do_percent(val, dev->config->boost_up_threshold), val 228 drivers/devfreq/tegra30-devfreq.c device_writel(dev, do_percent(val, dev->config->boost_down_threshold), val 337 drivers/devfreq/tegra30-devfreq.c u32 val; val 341 drivers/devfreq/tegra30-devfreq.c val = actmon_readl(tegra, ACTMON_GLB_STATUS); val 343 drivers/devfreq/tegra30-devfreq.c if (val & tegra->devices[i].config->irq_mask) { val 386 drivers/devfreq/tegra30-devfreq.c u32 val = 0; val 399 drivers/devfreq/tegra30-devfreq.c val |= ACTMON_DEV_CTRL_ENB_PERIODIC; val 400 drivers/devfreq/tegra30-devfreq.c val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1) val 402 drivers/devfreq/tegra30-devfreq.c val |= (ACTMON_BELOW_WMARK_WINDOW - 1) val 404 drivers/devfreq/tegra30-devfreq.c val |= (ACTMON_ABOVE_WMARK_WINDOW - 1) val 406 drivers/devfreq/tegra30-devfreq.c val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN; val 407 drivers/devfreq/tegra30-devfreq.c val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN; val 408 drivers/devfreq/tegra30-devfreq.c val |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; val 409 drivers/devfreq/tegra30-devfreq.c val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; val 410 drivers/devfreq/tegra30-devfreq.c val |= ACTMON_DEV_CTRL_ENB; val 412 drivers/devfreq/tegra30-devfreq.c device_writel(dev, val, ACTMON_DEV_CTRL); val 470 drivers/dma/altera-msgdma.c u32 val; val 477 drivers/dma/altera-msgdma.c ret = readl_poll_timeout(mdev->csr + MSGDMA_CSR_STATUS, val, val 478 drivers/dma/altera-msgdma.c (val & MSGDMA_CSR_STAT_RESETTING) == 0, val 371 drivers/dma/amba-pl08x.c unsigned int val; val 375 drivers/dma/amba-pl08x.c val = readl(ch->reg_busy); val 376 drivers/dma/amba-pl08x.c return !!(val & BIT(ch->id)); val 378 drivers/dma/amba-pl08x.c val = readl(ch->reg_config); val 379 drivers/dma/amba-pl08x.c return val & PL080_CONFIG_ACTIVE; val 420 drivers/dma/amba-pl08x.c u32 val = 0; val 438 drivers/dma/amba-pl08x.c val |= FTDMAC020_CH_CSR_TC_MSK; val 439 drivers/dma/amba-pl08x.c val |= ((llictl & FTDMAC020_LLI_SRC_WIDTH_MSK) >> val 442 drivers/dma/amba-pl08x.c val |= ((llictl & FTDMAC020_LLI_DST_WIDTH_MSK) >> val 445 drivers/dma/amba-pl08x.c val |= ((llictl & FTDMAC020_LLI_SRCAD_CTL_MSK) >> val 448 drivers/dma/amba-pl08x.c val |= ((llictl & FTDMAC020_LLI_DSTAD_CTL_MSK) >> val 452 drivers/dma/amba-pl08x.c val |= FTDMAC020_CH_CSR_SRC_SEL; val 454 drivers/dma/amba-pl08x.c val |= FTDMAC020_CH_CSR_DST_SEL; val 466 drivers/dma/amba-pl08x.c val |= PL080_BSIZE_1 << val 470 drivers/dma/amba-pl08x.c val |= PL080_BSIZE_4 << val 474 drivers/dma/amba-pl08x.c val |= PL080_BSIZE_8 << val 478 drivers/dma/amba-pl08x.c val |= PL080_BSIZE_16 << val 482 drivers/dma/amba-pl08x.c val |= PL080_BSIZE_32 << val 486 drivers/dma/amba-pl08x.c val |= PL080_BSIZE_64 << val 490 drivers/dma/amba-pl08x.c val |= PL080_BSIZE_128 << val 494 drivers/dma/amba-pl08x.c val |= PL080_BSIZE_256 << val 501 drivers/dma/amba-pl08x.c val |= FTDMAC020_CH_CSR_PROT2; val 503 drivers/dma/amba-pl08x.c val |= FTDMAC020_CH_CSR_PROT3; val 505 drivers/dma/amba-pl08x.c val |= FTDMAC020_CH_CSR_PROT1; val 507 drivers/dma/amba-pl08x.c writel_relaxed(val, phychan->reg_control); val 533 drivers/dma/amba-pl08x.c u32 val; val 552 drivers/dma/amba-pl08x.c val = readl(phychan->reg_config); val 553 drivers/dma/amba-pl08x.c while (val & FTDMAC020_CH_CFG_BUSY) val 554 drivers/dma/amba-pl08x.c val = readl(phychan->reg_config); val 556 drivers/dma/amba-pl08x.c val = readl(phychan->reg_control); val 557 drivers/dma/amba-pl08x.c while (val & FTDMAC020_CH_CSR_EN) val 558 drivers/dma/amba-pl08x.c val = readl(phychan->reg_control); val 560 drivers/dma/amba-pl08x.c writel(val | FTDMAC020_CH_CSR_EN, val 563 drivers/dma/amba-pl08x.c val = readl(phychan->reg_config); val 564 drivers/dma/amba-pl08x.c while ((val & PL080_CONFIG_ACTIVE) || val 565 drivers/dma/amba-pl08x.c (val & PL080_CONFIG_ENABLE)) val 566 drivers/dma/amba-pl08x.c val = readl(phychan->reg_config); val 568 drivers/dma/amba-pl08x.c writel(val | PL080_CONFIG_ENABLE, phychan->reg_config); val 584 drivers/dma/amba-pl08x.c u32 val; val 589 drivers/dma/amba-pl08x.c val = readl(ch->reg_control); val 590 drivers/dma/amba-pl08x.c val &= ~FTDMAC020_CH_CSR_EN; val 591 drivers/dma/amba-pl08x.c writel(val, ch->reg_control); val 596 drivers/dma/amba-pl08x.c val = readl(ch->reg_config); val 597 drivers/dma/amba-pl08x.c val |= PL080_CONFIG_HALT; val 598 drivers/dma/amba-pl08x.c writel(val, ch->reg_config); val 612 drivers/dma/amba-pl08x.c u32 val; val 616 drivers/dma/amba-pl08x.c val = readl(ch->reg_control); val 617 drivers/dma/amba-pl08x.c val |= FTDMAC020_CH_CSR_EN; val 618 drivers/dma/amba-pl08x.c writel(val, ch->reg_control); val 623 drivers/dma/amba-pl08x.c val = readl(ch->reg_config); val 624 drivers/dma/amba-pl08x.c val &= ~PL080_CONFIG_HALT; val 625 drivers/dma/amba-pl08x.c writel(val, ch->reg_config); val 637 drivers/dma/amba-pl08x.c u32 val; val 642 drivers/dma/amba-pl08x.c val = readl(ch->reg_config); val 643 drivers/dma/amba-pl08x.c val |= (FTDMAC020_CH_CFG_INT_ABT_MASK | val 646 drivers/dma/amba-pl08x.c writel(val, ch->reg_config); val 649 drivers/dma/amba-pl08x.c val = readl(ch->reg_control); val 650 drivers/dma/amba-pl08x.c val &= ~FTDMAC020_CH_CSR_EN; val 651 drivers/dma/amba-pl08x.c val |= FTDMAC020_CH_CSR_ABT; val 652 drivers/dma/amba-pl08x.c writel(val, ch->reg_control); val 662 drivers/dma/amba-pl08x.c val = readl(ch->reg_config); val 663 drivers/dma/amba-pl08x.c val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | val 665 drivers/dma/amba-pl08x.c writel(val, ch->reg_config); val 673 drivers/dma/amba-pl08x.c u32 val; val 679 drivers/dma/amba-pl08x.c val = readl(ch->reg_control); val 680 drivers/dma/amba-pl08x.c val &= FTDMAC020_CH_CSR_SRC_WIDTH_MSK; val 681 drivers/dma/amba-pl08x.c val >>= FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT; val 683 drivers/dma/amba-pl08x.c val = readl(ch->base + PL080S_CH_CONTROL2); val 684 drivers/dma/amba-pl08x.c bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK; val 686 drivers/dma/amba-pl08x.c val = readl(ch->reg_control); val 687 drivers/dma/amba-pl08x.c val &= PL080_CONTROL_SWIDTH_MASK; val 688 drivers/dma/amba-pl08x.c val >>= PL080_CONTROL_SWIDTH_SHIFT; val 691 drivers/dma/amba-pl08x.c val = readl(ch->reg_control); val 692 drivers/dma/amba-pl08x.c bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK; val 694 drivers/dma/amba-pl08x.c val &= PL080_CONTROL_SWIDTH_MASK; val 695 drivers/dma/amba-pl08x.c val >>= PL080_CONTROL_SWIDTH_SHIFT; val 698 drivers/dma/amba-pl08x.c switch (val) { val 713 drivers/dma/amba-pl08x.c u32 val; val 717 drivers/dma/amba-pl08x.c val = llis_va[PL080_LLI_CCTL]; val 718 drivers/dma/amba-pl08x.c bytes = val & FTDMAC020_LLI_TRANSFER_SIZE_MASK; val 720 drivers/dma/amba-pl08x.c val = llis_va[PL080_LLI_CCTL]; val 721 drivers/dma/amba-pl08x.c val &= FTDMAC020_LLI_SRC_WIDTH_MSK; val 722 drivers/dma/amba-pl08x.c val >>= FTDMAC020_LLI_SRC_WIDTH_SHIFT; val 724 drivers/dma/amba-pl08x.c val = llis_va[PL080S_LLI_CCTL2]; val 725 drivers/dma/amba-pl08x.c bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK; val 727 drivers/dma/amba-pl08x.c val = llis_va[PL080_LLI_CCTL]; val 728 drivers/dma/amba-pl08x.c val &= PL080_CONTROL_SWIDTH_MASK; val 729 drivers/dma/amba-pl08x.c val >>= PL080_CONTROL_SWIDTH_SHIFT; val 732 drivers/dma/amba-pl08x.c val = llis_va[PL080_LLI_CCTL]; val 733 drivers/dma/amba-pl08x.c bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK; val 735 drivers/dma/amba-pl08x.c val &= PL080_CONTROL_SWIDTH_MASK; val 736 drivers/dma/amba-pl08x.c val >>= PL080_CONTROL_SWIDTH_SHIFT; val 739 drivers/dma/amba-pl08x.c switch (val) { val 971 drivers/dma/amba-pl08x.c u32 val; val 975 drivers/dma/amba-pl08x.c val = (cctl & FTDMAC020_LLI_SRC_WIDTH_MSK) >> val 978 drivers/dma/amba-pl08x.c val = (cctl & FTDMAC020_LLI_DST_WIDTH_MSK) >> val 982 drivers/dma/amba-pl08x.c val = (cctl & PL080_CONTROL_SWIDTH_MASK) >> val 985 drivers/dma/amba-pl08x.c val = (cctl & PL080_CONTROL_DWIDTH_MASK) >> val 989 drivers/dma/amba-pl08x.c switch (val) { val 2578 drivers/dma/amba-pl08x.c u32 val; val 2607 drivers/dma/amba-pl08x.c ret = of_property_read_u32(np, "memcpy-burst-size", &val); val 2610 drivers/dma/amba-pl08x.c val = 1; val 2612 drivers/dma/amba-pl08x.c switch (val) { val 2642 drivers/dma/amba-pl08x.c ret = of_property_read_u32(np, "memcpy-bus-width", &val); val 2645 drivers/dma/amba-pl08x.c val = 8; val 2647 drivers/dma/amba-pl08x.c switch (val) { val 2737 drivers/dma/amba-pl08x.c u32 val; val 2739 drivers/dma/amba-pl08x.c val = readl(pl08x->base + FTDMAC020_REVISION); val 2741 drivers/dma/amba-pl08x.c (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); val 2742 drivers/dma/amba-pl08x.c val = readl(pl08x->base + FTDMAC020_FEATURE); val 2745 drivers/dma/amba-pl08x.c (val >> 12) & 0x0f, val 2746 drivers/dma/amba-pl08x.c (val & BIT(10)) ? "no" : "has", val 2747 drivers/dma/amba-pl08x.c (val & BIT(9)) ? "AHB0 and AHB1" : "AHB0", val 2748 drivers/dma/amba-pl08x.c (val & BIT(8)) ? "supports" : "does not support"); val 2751 drivers/dma/amba-pl08x.c if (!(val & BIT(8))) val 2754 drivers/dma/amba-pl08x.c vd->channels = (val >> 12) & 0x0f; val 2755 drivers/dma/amba-pl08x.c vd->dualmaster = !!(val & BIT(9)); val 2908 drivers/dma/amba-pl08x.c u32 val; val 2910 drivers/dma/amba-pl08x.c val = readl(ch->reg_config); val 2911 drivers/dma/amba-pl08x.c if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { val 273 drivers/dma/at_hdmac_regs.h #define channel_writel(atchan, name, val) \ val 274 drivers/dma/at_hdmac_regs.h __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET) val 341 drivers/dma/at_hdmac_regs.h #define dma_writel(atdma, name, val) \ val 342 drivers/dma/at_hdmac_regs.h __raw_writel((val), (atdma)->regs + AT_DMA_##name) val 171 drivers/dma/bcm-sba-raid.c static inline u64 __pure sba_cmd_enc(u64 cmd, u32 val, u32 shift, u32 mask) val 174 drivers/dma/bcm-sba-raid.c cmd |= ((u64)(val & mask) << shift); val 1468 drivers/dma/coh901318.c u32 val; val 1474 drivers/dma/coh901318.c val = readl(virtbase + COH901318_CX_CFG + val 1478 drivers/dma/coh901318.c val |= COH901318_CX_CFG_CH_ENABLE; val 1479 drivers/dma/coh901318.c writel(val, virtbase + COH901318_CX_CFG + val 1685 drivers/dma/coh901318.c u32 val; val 1694 drivers/dma/coh901318.c val = readl(virtbase + COH901318_CX_CFG + val 1698 drivers/dma/coh901318.c if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 && val 1699 drivers/dma/coh901318.c (val & COH901318_CX_CFG_CH_ENABLE)) val 1703 drivers/dma/coh901318.c val &= ~COH901318_CX_CFG_CH_ENABLE; val 1705 drivers/dma/coh901318.c writel(val, virtbase + COH901318_CX_CFG + val 1707 drivers/dma/coh901318.c writel(val, virtbase + COH901318_CX_CFG + val 1731 drivers/dma/coh901318.c u32 val; val 1742 drivers/dma/coh901318.c val = readl(cohc->base->virtbase + COH901318_CX_CFG + val 1745 drivers/dma/coh901318.c val |= COH901318_CX_CFG_CH_ENABLE; val 1747 drivers/dma/coh901318.c writel(val, cohc->base->virtbase + COH901318_CX_CFG + val 281 drivers/dma/coh901318_lli.c u32 val; val 285 drivers/dma/coh901318_lli.c val = ctrl_chained; val 288 drivers/dma/coh901318_lli.c val = ctrl_sg; val 291 drivers/dma/coh901318_lli.c lli->control = val | elem_size; val 158 drivers/dma/dma-axi-dmac.c unsigned int val) val 160 drivers/dma/dma-axi-dmac.c writel(val, axi_dmac->base + reg); val 201 drivers/dma/dma-axi-dmac.c unsigned int val; val 203 drivers/dma/dma-axi-dmac.c val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER); val 204 drivers/dma/dma-axi-dmac.c if (val) /* Queue is full, wait for the next SOT IRQ */ val 728 drivers/dma/dma-axi-dmac.c u32 val; val 731 drivers/dma/dma-axi-dmac.c ret = of_property_read_u32(of_chan, "reg", &val); val 736 drivers/dma/dma-axi-dmac.c if (val != 0) val 739 drivers/dma/dma-axi-dmac.c ret = of_property_read_u32(of_chan, "adi,source-bus-type", &val); val 742 drivers/dma/dma-axi-dmac.c if (val > AXI_DMAC_BUS_TYPE_FIFO) val 744 drivers/dma/dma-axi-dmac.c chan->src_type = val; val 746 drivers/dma/dma-axi-dmac.c ret = of_property_read_u32(of_chan, "adi,destination-bus-type", &val); val 749 drivers/dma/dma-axi-dmac.c if (val > AXI_DMAC_BUS_TYPE_FIFO) val 751 drivers/dma/dma-axi-dmac.c chan->dest_type = val; val 753 drivers/dma/dma-axi-dmac.c ret = of_property_read_u32(of_chan, "adi,source-bus-width", &val); val 756 drivers/dma/dma-axi-dmac.c chan->src_width = val / 8; val 758 drivers/dma/dma-axi-dmac.c ret = of_property_read_u32(of_chan, "adi,destination-bus-width", &val); val 761 drivers/dma/dma-axi-dmac.c chan->dest_width = val / 8; val 189 drivers/dma/dma-jz4780.c unsigned int chn, unsigned int reg, uint32_t val) val 191 drivers/dma/dma-jz4780.c writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); val 201 drivers/dma/dma-jz4780.c unsigned int reg, uint32_t val) val 203 drivers/dma/dma-jz4780.c writel(val, jzdma->ctrl_base + reg); val 264 drivers/dma/dma-jz4780.c unsigned long val, uint32_t *shift) val 267 drivers/dma/dma-jz4780.c int ord = ffs(val) - 1; val 139 drivers/dma/dmatest.c static int dmatest_run_set(const char *val, const struct kernel_param *kp); val 140 drivers/dma/dmatest.c static int dmatest_run_get(char *val, const struct kernel_param *kp); val 149 drivers/dma/dmatest.c static int dmatest_chan_set(const char *val, const struct kernel_param *kp); val 150 drivers/dma/dmatest.c static int dmatest_chan_get(char *val, const struct kernel_param *kp); val 164 drivers/dma/dmatest.c static int dmatest_test_list_get(char *val, const struct kernel_param *kp); val 267 drivers/dma/dmatest.c static int dmatest_wait_get(char *val, const struct kernel_param *kp) val 275 drivers/dma/dmatest.c return param_get_bool(val, kp); val 311 drivers/dma/dmatest.c u8 val = is_memset ? PATTERN_MEMSET_IDX : index; val 313 drivers/dma/dmatest.c return ~val & PATTERN_COUNT_MASK; val 439 drivers/dma/dmatest.c unsigned int val = min(x, y); val 441 drivers/dma/dmatest.c return val % 2 ? val : val - 1; val 466 drivers/dma/dmatest.c static unsigned long long dmatest_persec(s64 runtime, unsigned int val) val 479 drivers/dma/dmatest.c per_sec *= val; val 1141 drivers/dma/dmatest.c static int dmatest_run_get(char *val, const struct kernel_param *kp) val 1155 drivers/dma/dmatest.c return param_get_bool(val, kp); val 1158 drivers/dma/dmatest.c static int dmatest_run_set(const char *val, const struct kernel_param *kp) val 1164 drivers/dma/dmatest.c ret = param_set_bool(val, kp); val 1183 drivers/dma/dmatest.c static int dmatest_chan_set(const char *val, const struct kernel_param *kp) val 1191 drivers/dma/dmatest.c ret = param_set_copystring(val, kp); val 1254 drivers/dma/dmatest.c static int dmatest_chan_get(char *val, const struct kernel_param *kp) val 1265 drivers/dma/dmatest.c return param_get_string(val, kp); val 1268 drivers/dma/dmatest.c static int dmatest_test_list_get(char *val, const struct kernel_param *kp) val 45 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) val 47 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(val, chip->regs + reg); val 56 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val) val 58 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(val, chan->chan_regs + reg); val 67 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) val 73 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(lower_32_bits(val), chan->chan_regs + reg); val 74 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); val 79 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 81 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chip, DMAC_CFG); val 82 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~DMAC_EN_MASK; val 83 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(chip, DMAC_CFG, val); val 88 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 90 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chip, DMAC_CFG); val 91 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= DMAC_EN_MASK; val 92 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(chip, DMAC_CFG, val); val 97 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 99 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chip, DMAC_CFG); val 100 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~INT_EN_MASK; val 101 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(chip, DMAC_CFG, val); val 106 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 108 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chip, DMAC_CFG); val 109 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= INT_EN_MASK; val 110 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(chip, DMAC_CFG, val); val 115 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 120 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA); val 121 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~irq_mask; val 122 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val); val 148 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 150 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chan->chip, DMAC_CHEN); val 151 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT); val 152 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; val 153 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); val 158 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 160 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chan->chip, DMAC_CHEN); val 161 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | val 163 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); val 168 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 170 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chan->chip, DMAC_CHEN); val 172 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT)); val 383 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 385 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = le32_to_cpu(desc->lli.ctl_hi); val 386 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= CH_CTL_H_LLI_LAST; val 387 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c desc->lli.ctl_hi = cpu_to_le32(val); val 402 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 405 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = le32_to_cpu(desc->lli.ctl_lo); val 406 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~CH_CTL_L_SRC_MAST; val 407 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c desc->lli.ctl_lo = cpu_to_le32(val); val 412 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 415 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = le32_to_cpu(desc->lli.ctl_lo); val 417 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= CH_CTL_L_DST_MAST; val 419 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~CH_CTL_L_DST_MAST; val 421 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c desc->lli.ctl_lo = cpu_to_le32(val); val 657 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 661 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chan->chip, DMAC_CHEN); val 662 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | val 664 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); val 685 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 val; val 687 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val = axi_dma_ioread32(chan->chip, DMAC_CHEN); val 688 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); val 689 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); val 690 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); val 536 drivers/dma/dw-edma/dw-edma-core.c unsigned long total, pos, val; val 550 drivers/dma/dw-edma/dw-edma-core.c val = dw_edma_v0_core_status_done_int(dw, write ? val 553 drivers/dma/dw-edma/dw-edma-core.c val &= mask; val 554 drivers/dma/dw-edma/dw-edma-core.c for_each_set_bit(pos, &val, total) { val 560 drivers/dma/dw-edma/dw-edma-core.c val = dw_edma_v0_core_status_abort_int(dw, write ? val 563 drivers/dma/dw-edma/dw-edma-core.c val &= mask; val 564 drivers/dma/dw-edma/dw-edma-core.c for_each_set_bit(pos, &val, total) { val 55 drivers/dma/dw-edma/dw-edma-v0-debugfs.c static int dw_edma_debugfs_u32_get(void *data, u64 *val) val 86 drivers/dma/dw-edma/dw-edma-v0-debugfs.c *val = readl(ptr); val 90 drivers/dma/dw-edma/dw-edma-v0-debugfs.c *val = readl(reg); val 302 drivers/dma/dw/regs.h #define channel_writel(dwc, name, val) \ val 303 drivers/dma/dw/regs.h writel((val), &(__dwc_regs(dwc)->name)) val 348 drivers/dma/dw/regs.h #define dma_writel(dw, name, val) \ val 349 drivers/dma/dw/regs.h writel((val), &(__dw_regs(dw)->name)) val 353 drivers/dma/dw/regs.h #define idma32_writeq(dw, name, val) \ val 354 drivers/dma/dw/regs.h hi_lo_writeq((val), &(__dw_regs(dw)->name)) val 96 drivers/dma/fsl-edma-common.c u32 val; val 99 drivers/dma/fsl-edma-common.c val = EDMAMUX_CHCFG_ENBL << 24 | slot; val 101 drivers/dma/fsl-edma-common.c val = EDMAMUX_CHCFG_DIS; val 103 drivers/dma/fsl-edma-common.c iowrite32(val, addr + off * 4); val 185 drivers/dma/fsl-edma-common.h u8 val, void __iomem *addr) val 189 drivers/dma/fsl-edma-common.h iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3)); val 191 drivers/dma/fsl-edma-common.h iowrite8(val, addr); val 195 drivers/dma/fsl-edma-common.h u16 val, void __iomem *addr) val 199 drivers/dma/fsl-edma-common.h iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2)); val 201 drivers/dma/fsl-edma-common.h iowrite16(val, addr); val 205 drivers/dma/fsl-edma-common.h u32 val, void __iomem *addr) val 208 drivers/dma/fsl-edma-common.h iowrite32be(val, addr); val 210 drivers/dma/fsl-edma-common.h iowrite32(val, addr); val 276 drivers/dma/fsl-qdma.c static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val, val 279 drivers/dma/fsl-qdma.c FSL_DMA_OUT(qdma, addr, val, 32); val 49 drivers/dma/fsldma.c static void set_sr(struct fsldma_chan *chan, u32 val) val 51 drivers/dma/fsldma.c FSL_DMA_OUT(chan, &chan->regs->sr, val, 32); val 59 drivers/dma/fsldma.c static void set_mr(struct fsldma_chan *chan, u32 val) val 61 drivers/dma/fsldma.c FSL_DMA_OUT(chan, &chan->regs->mr, val, 32); val 79 drivers/dma/fsldma.c static void set_bcr(struct fsldma_chan *chan, u32 val) val 81 drivers/dma/fsldma.c FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32); val 214 drivers/dma/fsldma.h static void fsl_iowrite64(u64 val, u64 __iomem *addr) val 216 drivers/dma/fsldma.h out_le32((u32 __iomem *)addr + 1, val >> 32); val 217 drivers/dma/fsldma.h out_le32((u32 __iomem *)addr, (u32)val); val 228 drivers/dma/fsldma.h static void fsl_iowrite64be(u64 val, u64 __iomem *addr) val 230 drivers/dma/fsldma.h out_be32((u32 __iomem *)addr, val >> 32); val 231 drivers/dma/fsldma.h out_be32((u32 __iomem *)addr + 1, (u32)val); val 251 drivers/dma/fsldma.h #define FSL_DMA_OUT(fsl_dma, addr, val, width) \ val 253 drivers/dma/fsldma.h fsl_iowrite##width##be(val, addr) : fsl_iowrite \ val 254 drivers/dma/fsldma.h ##width(val, addr)) val 154 drivers/dma/img-mdc-dma.c static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg) val 156 drivers/dma/img-mdc-dma.c writel(val, mdma->regs + reg); val 164 drivers/dma/img-mdc-dma.c static inline void mdc_chan_writel(struct mdc_chan *mchan, u32 val, u32 reg) val 166 drivers/dma/img-mdc-dma.c mdc_writel(mchan->mdma, val, mchan->chan_nr * 0x040 + reg); val 529 drivers/dma/img-mdc-dma.c u32 val; val 545 drivers/dma/img-mdc-dma.c val = mdc_chan_readl(mchan, MDC_GENERAL_CONFIG); val 546 drivers/dma/img-mdc-dma.c val |= MDC_GENERAL_CONFIG_LIST_IEN | MDC_GENERAL_CONFIG_IEN | val 549 drivers/dma/img-mdc-dma.c mdc_chan_writel(mchan, val, MDC_GENERAL_CONFIG); val 550 drivers/dma/img-mdc-dma.c val = (mchan->thread << MDC_READ_PORT_CONFIG_STHREAD_SHIFT) | val 553 drivers/dma/img-mdc-dma.c mdc_chan_writel(mchan, val, MDC_READ_PORT_CONFIG); val 555 drivers/dma/img-mdc-dma.c val = mdc_chan_readl(mchan, MDC_CONTROL_AND_STATUS); val 556 drivers/dma/img-mdc-dma.c val |= MDC_CONTROL_AND_STATUS_LIST_EN; val 557 drivers/dma/img-mdc-dma.c mdc_chan_writel(mchan, val, MDC_CONTROL_AND_STATUS); val 651 drivers/dma/img-mdc-dma.c u32 val, processed, done1, done2; val 654 drivers/dma/img-mdc-dma.c val = mdc_chan_readl(mchan, MDC_CMDS_PROCESSED); val 655 drivers/dma/img-mdc-dma.c processed = (val >> MDC_CMDS_PROCESSED_CMDS_PROCESSED_SHIFT) & val 663 drivers/dma/img-mdc-dma.c val = mdc_chan_readl(mchan, MDC_CMDS_PROCESSED); val 665 drivers/dma/img-mdc-dma.c done1 = (val >> MDC_CMDS_PROCESSED_CMDS_DONE_SHIFT) & val 668 drivers/dma/img-mdc-dma.c val &= ~((MDC_CMDS_PROCESSED_CMDS_PROCESSED_MASK << val 672 drivers/dma/img-mdc-dma.c val |= done1 << MDC_CMDS_PROCESSED_CMDS_PROCESSED_SHIFT; val 674 drivers/dma/img-mdc-dma.c mdc_chan_writel(mchan, val, MDC_CMDS_PROCESSED); val 676 drivers/dma/img-mdc-dma.c val = mdc_chan_readl(mchan, MDC_CMDS_PROCESSED); val 678 drivers/dma/img-mdc-dma.c done2 = (val >> MDC_CMDS_PROCESSED_CMDS_DONE_SHIFT) & val 891 drivers/dma/img-mdc-dma.c u32 val; val 921 drivers/dma/img-mdc-dma.c val = mdc_readl(mdma, MDC_GLOBAL_CONFIG_A); val 922 drivers/dma/img-mdc-dma.c mdma->nr_channels = (val >> MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_SHIFT) & val 925 drivers/dma/img-mdc-dma.c 1 << ((val >> MDC_GLOBAL_CONFIG_A_THREAD_ID_WIDTH_SHIFT) & val 928 drivers/dma/img-mdc-dma.c (1 << ((val >> MDC_GLOBAL_CONFIG_A_SYS_DAT_WIDTH_SHIFT) & val 257 drivers/dma/imx-dma.c static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, val 260 drivers/dma/imx-dma.c __raw_writel(val, imxdma->base + offset); val 726 drivers/dma/imx-sdma.c unsigned long val; val 729 drivers/dma/imx-sdma.c val = readl_relaxed(sdma->regs + chnenbl); val 730 drivers/dma/imx-sdma.c __set_bit(channel, &val); val 731 drivers/dma/imx-sdma.c writel_relaxed(val, sdma->regs + chnenbl); val 739 drivers/dma/imx-sdma.c unsigned long val; val 741 drivers/dma/imx-sdma.c val = readl_relaxed(sdma->regs + chnenbl); val 742 drivers/dma/imx-sdma.c __clear_bit(channel, &val); val 743 drivers/dma/imx-sdma.c writel_relaxed(val, sdma->regs + chnenbl); val 1795 drivers/dma/imx-sdma.c u32 reg, val, shift, num_map, i; val 1835 drivers/dma/imx-sdma.c ret = of_property_read_u32_index(np, propname, i + 2, &val); val 1842 drivers/dma/imx-sdma.c regmap_update_bits(gpr, reg, BIT(shift), val << shift); val 777 drivers/dma/iop-adma.h u32 val) val 780 drivers/dma/iop-adma.h hw_desc->src[0] = val; val 136 drivers/dma/k3dma.c u32 val = 0; val 139 drivers/dma/k3dma.c val = readl_relaxed(phy->base + CX_CFG); val 140 drivers/dma/k3dma.c val |= CX_CFG_EN; val 141 drivers/dma/k3dma.c writel_relaxed(val, phy->base + CX_CFG); val 143 drivers/dma/k3dma.c val = readl_relaxed(phy->base + CX_CFG); val 144 drivers/dma/k3dma.c val &= ~CX_CFG_EN; val 145 drivers/dma/k3dma.c writel_relaxed(val, phy->base + CX_CFG); val 151 drivers/dma/k3dma.c u32 val = 0; val 155 drivers/dma/k3dma.c val = 0x1 << phy->idx; val 156 drivers/dma/k3dma.c writel_relaxed(val, d->base + INT_TC1_RAW); val 157 drivers/dma/k3dma.c writel_relaxed(val, d->base + INT_TC2_RAW); val 158 drivers/dma/k3dma.c writel_relaxed(val, d->base + INT_ERR1_RAW); val 159 drivers/dma/k3dma.c writel_relaxed(val, d->base + INT_ERR2_RAW); val 671 drivers/dma/k3dma.c u32 maxburst = 0, val = 0; val 690 drivers/dma/k3dma.c val = __ffs(width); val 693 drivers/dma/k3dma.c val = 3; val 696 drivers/dma/k3dma.c c->ccfg |= (val << 12) | (val << 16); val 699 drivers/dma/k3dma.c val = 15; val 701 drivers/dma/k3dma.c val = maxburst - 1; val 702 drivers/dma/k3dma.c c->ccfg |= (val << 20) | (val << 24); val 174 drivers/dma/mediatek/mtk-cqdma.c static void mtk_dma_write(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) val 176 drivers/dma/mediatek/mtk-cqdma.c writel_relaxed(val, pc->base + reg); val 182 drivers/dma/mediatek/mtk-cqdma.c u32 val; val 184 drivers/dma/mediatek/mtk-cqdma.c val = mtk_dma_read(pc, reg); val 185 drivers/dma/mediatek/mtk-cqdma.c val &= ~mask; val 186 drivers/dma/mediatek/mtk-cqdma.c val |= set; val 187 drivers/dma/mediatek/mtk-cqdma.c mtk_dma_write(pc, reg, val); val 190 drivers/dma/mediatek/mtk-cqdma.c static void mtk_dma_set(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) val 192 drivers/dma/mediatek/mtk-cqdma.c mtk_dma_rmw(pc, reg, 0, val); val 195 drivers/dma/mediatek/mtk-cqdma.c static void mtk_dma_clr(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) val 197 drivers/dma/mediatek/mtk-cqdma.c mtk_dma_rmw(pc, reg, val, 0); val 274 drivers/dma/mediatek/mtk-hsdma.c static void mtk_dma_write(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) val 276 drivers/dma/mediatek/mtk-hsdma.c writel(val, hsdma->base + reg); val 282 drivers/dma/mediatek/mtk-hsdma.c u32 val; val 284 drivers/dma/mediatek/mtk-hsdma.c val = mtk_dma_read(hsdma, reg); val 285 drivers/dma/mediatek/mtk-hsdma.c val &= ~mask; val 286 drivers/dma/mediatek/mtk-hsdma.c val |= set; val 287 drivers/dma/mediatek/mtk-hsdma.c mtk_dma_write(hsdma, reg, val); val 290 drivers/dma/mediatek/mtk-hsdma.c static void mtk_dma_set(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) val 292 drivers/dma/mediatek/mtk-hsdma.c mtk_dma_rmw(hsdma, reg, 0, val); val 295 drivers/dma/mediatek/mtk-hsdma.c static void mtk_dma_clr(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) val 297 drivers/dma/mediatek/mtk-hsdma.c mtk_dma_rmw(hsdma, reg, val, 0); val 122 drivers/dma/mediatek/mtk-uart-apdma.c unsigned int reg, unsigned int val) val 124 drivers/dma/mediatek/mtk-uart-apdma.c writel(val, c->base + reg); val 34 drivers/dma/mic_x100_dma.c static inline u32 mic_dma_hw_ring_inc(u32 val) val 36 drivers/dma/mic_x100_dma.c return (val + 1) % MIC_DMA_DESC_RX_SIZE; val 39 drivers/dma/mic_x100_dma.c static inline u32 mic_dma_hw_ring_dec(u32 val) val 41 drivers/dma/mic_x100_dma.c return val ? val - 1 : MIC_DMA_DESC_RX_SIZE - 1; val 178 drivers/dma/mic_x100_dma.h static inline void mic_dma_write_reg(struct mic_dma_chan *ch, u32 reg, u32 val) val 180 drivers/dma/mic_x100_dma.h iowrite32(val, mic_dma_chan_to_mmio(ch) + MIC_DMA_SBOX_CH_BASE + val 189 drivers/dma/mic_x100_dma.h static inline void mic_dma_mmio_write(struct mic_dma_chan *ch, u32 val, val 192 drivers/dma/mic_x100_dma.h iowrite32(val, mic_dma_chan_to_mmio(ch) + offset); val 111 drivers/dma/mv_xor.c u32 val = readl_relaxed(XOR_INTR_MASK(chan)); val 112 drivers/dma/mv_xor.c val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); val 113 drivers/dma/mv_xor.c writel_relaxed(val, XOR_INTR_MASK(chan)); val 125 drivers/dma/mv_xor.c u32 val; val 127 drivers/dma/mv_xor.c val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; val 128 drivers/dma/mv_xor.c val = ~(val << (chan->idx * 16)); val 129 drivers/dma/mv_xor.c dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); val 130 drivers/dma/mv_xor.c writel_relaxed(val, XOR_INTR_CAUSE(chan)); val 135 drivers/dma/mv_xor.c u32 val = 0xFFFF0000 >> (chan->idx * 16); val 136 drivers/dma/mv_xor.c writel_relaxed(val, XOR_INTR_CAUSE(chan)); val 694 drivers/dma/mv_xor.c u32 val; val 696 drivers/dma/mv_xor.c val = readl_relaxed(XOR_CONFIG(chan)); val 697 drivers/dma/mv_xor.c dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); val 699 drivers/dma/mv_xor.c val = readl_relaxed(XOR_ACTIVATION(chan)); val 700 drivers/dma/mv_xor.c dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); val 702 drivers/dma/mv_xor.c val = readl_relaxed(XOR_INTR_CAUSE(chan)); val 703 drivers/dma/mv_xor.c dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); val 705 drivers/dma/mv_xor.c val = readl_relaxed(XOR_INTR_MASK(chan)); val 706 drivers/dma/mv_xor.c dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); val 708 drivers/dma/mv_xor.c val = readl_relaxed(XOR_ERROR_CAUSE(chan)); val 709 drivers/dma/mv_xor.c dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); val 711 drivers/dma/mv_xor.c val = readl_relaxed(XOR_ERROR_ADDR(chan)); val 712 drivers/dma/mv_xor.c dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); val 120 drivers/dma/owl-dma.c #define BIT_FIELD(val, width, shift, newshift) \ val 121 drivers/dma/owl-dma.c ((((val) >> (shift)) & ((BIT(width)) - 1)) << (newshift)) val 230 drivers/dma/owl-dma.c u32 val, bool state) val 237 drivers/dma/owl-dma.c regval |= val; val 239 drivers/dma/owl-dma.c regval &= ~val; val 241 drivers/dma/owl-dma.c writel(val, pchan->base + reg); val 254 drivers/dma/owl-dma.c static void dma_update(struct owl_dma *od, u32 reg, u32 val, bool state) val 261 drivers/dma/owl-dma.c regval |= val; val 263 drivers/dma/owl-dma.c regval &= ~val; val 265 drivers/dma/owl-dma.c writel(val, od->base + reg); val 453 drivers/dma/owl-dma.c unsigned int val; val 455 drivers/dma/owl-dma.c val = dma_readl(od, OWL_DMA_IDLE_STAT); val 457 drivers/dma/owl-dma.c return !(val & (1 << pchan->id)); val 112 drivers/dma/pch_dma.c #define channel_writel(pdc, name, val) \ val 113 drivers/dma/pch_dma.c writel((val), (pdc)->membase + PDC_##name) val 134 drivers/dma/pch_dma.c #define dma_writel(pd, name, val) \ val 135 drivers/dma/pch_dma.c writel((val), (pd)->membase + PCH_DMA_##name) val 180 drivers/dma/pch_dma.c u32 val; val 188 drivers/dma/pch_dma.c val = dma_readl(pd, CTL2); val 191 drivers/dma/pch_dma.c val |= 0x1 << pos; val 193 drivers/dma/pch_dma.c val &= ~(0x1 << pos); val 195 drivers/dma/pch_dma.c dma_writel(pd, CTL2, val); val 198 drivers/dma/pch_dma.c chan->chan_id, val); val 205 drivers/dma/pch_dma.c u32 val; val 210 drivers/dma/pch_dma.c val = dma_readl(pd, CTL0); val 216 drivers/dma/pch_dma.c val &= mask_mode; val 218 drivers/dma/pch_dma.c val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id + val 221 drivers/dma/pch_dma.c val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id + val 224 drivers/dma/pch_dma.c val |= mask_ctl; val 225 drivers/dma/pch_dma.c dma_writel(pd, CTL0, val); val 228 drivers/dma/pch_dma.c val = dma_readl(pd, CTL3); val 234 drivers/dma/pch_dma.c val &= mask_mode; val 236 drivers/dma/pch_dma.c val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch + val 239 drivers/dma/pch_dma.c val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch + val 241 drivers/dma/pch_dma.c val |= mask_ctl; val 242 drivers/dma/pch_dma.c dma_writel(pd, CTL3, val); val 246 drivers/dma/pch_dma.c chan->chan_id, val); val 252 drivers/dma/pch_dma.c u32 val; val 261 drivers/dma/pch_dma.c val = dma_readl(pd, CTL0); val 262 drivers/dma/pch_dma.c val &= mask_dir; val 263 drivers/dma/pch_dma.c val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id); val 264 drivers/dma/pch_dma.c val |= mask_ctl; val 265 drivers/dma/pch_dma.c dma_writel(pd, CTL0, val); val 272 drivers/dma/pch_dma.c val = dma_readl(pd, CTL3); val 273 drivers/dma/pch_dma.c val &= mask_dir; val 274 drivers/dma/pch_dma.c val |= mode << (DMA_CTL0_BITS_PER_CH * ch); val 275 drivers/dma/pch_dma.c val |= mask_ctl; val 276 drivers/dma/pch_dma.c dma_writel(pd, CTL3, val); val 280 drivers/dma/pch_dma.c chan->chan_id, val); val 286 drivers/dma/pch_dma.c u32 val; val 288 drivers/dma/pch_dma.c val = dma_readl(pd, STS0); val 289 drivers/dma/pch_dma.c return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS + val 296 drivers/dma/pch_dma.c u32 val; val 298 drivers/dma/pch_dma.c val = dma_readl(pd, STS2); val 299 drivers/dma/pch_dma.c return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS + val 711 drivers/dma/pl330.c enum dmamov_dst dst, u32 val) val 718 drivers/dma/pl330.c buf[2] = val; val 719 drivers/dma/pl330.c buf[3] = val >> 8; val 720 drivers/dma/pl330.c buf[4] = val >> 16; val 721 drivers/dma/pl330.c buf[5] = val >> 24; val 724 drivers/dma/pl330.c dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); val 886 drivers/dma/pl330.c u32 val; val 888 drivers/dma/pl330.c val = (insn[0] << 16) | (insn[1] << 24); val 890 drivers/dma/pl330.c val |= (1 << 0); val 891 drivers/dma/pl330.c val |= (thrd->id << 8); /* Channel Number */ val 893 drivers/dma/pl330.c writel(val, regs + DBGINST0); val 895 drivers/dma/pl330.c val = le32_to_cpu(*((__le32 *)&insn[2])); val 896 drivers/dma/pl330.c writel(val, regs + DBGINST1); val 911 drivers/dma/pl330.c u32 val; val 914 drivers/dma/pl330.c val = readl(regs + DS) & 0xf; val 916 drivers/dma/pl330.c val = readl(regs + CS(thrd->id)) & 0xf; val 918 drivers/dma/pl330.c switch (val) { val 1632 drivers/dma/pl330.c u32 val; val 1639 drivers/dma/pl330.c val = readl(regs + FSM) & 0x1; val 1640 drivers/dma/pl330.c if (val) val 1645 drivers/dma/pl330.c val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); val 1646 drivers/dma/pl330.c pl330->dmac_tbd.reset_chan |= val; val 1647 drivers/dma/pl330.c if (val) { val 1650 drivers/dma/pl330.c if (val & (1 << i)) { val 1662 drivers/dma/pl330.c val = readl(regs + ES); val 1664 drivers/dma/pl330.c && val & ~((1 << pl330->pcfg.num_events) - 1)) { val 1673 drivers/dma/pl330.c if (val & (1 << ev)) { /* Event occurred */ val 1813 drivers/dma/pl330.c u32 val; val 1815 drivers/dma/pl330.c val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; val 1816 drivers/dma/pl330.c val &= CRD_DATA_WIDTH_MASK; val 1817 drivers/dma/pl330.c pl330->pcfg.data_bus_width = 8 * (1 << val); val 1819 drivers/dma/pl330.c val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; val 1820 drivers/dma/pl330.c val &= CRD_DATA_BUFF_MASK; val 1821 drivers/dma/pl330.c pl330->pcfg.data_buf_dep = val + 1; val 1823 drivers/dma/pl330.c val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; val 1824 drivers/dma/pl330.c val &= CR0_NUM_CHANS_MASK; val 1825 drivers/dma/pl330.c val += 1; val 1826 drivers/dma/pl330.c pl330->pcfg.num_chan = val; val 1828 drivers/dma/pl330.c val = readl(regs + CR0); val 1829 drivers/dma/pl330.c if (val & CR0_PERIPH_REQ_SET) { val 1830 drivers/dma/pl330.c val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; val 1831 drivers/dma/pl330.c val += 1; val 1832 drivers/dma/pl330.c pl330->pcfg.num_peri = val; val 1838 drivers/dma/pl330.c val = readl(regs + CR0); val 1839 drivers/dma/pl330.c if (val & CR0_BOOT_MAN_NS) val 1844 drivers/dma/pl330.c val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; val 1845 drivers/dma/pl330.c val &= CR0_NUM_EVENTS_MASK; val 1846 drivers/dma/pl330.c val += 1; val 1847 drivers/dma/pl330.c pl330->pcfg.num_events = val; val 2370 drivers/dma/pl330.c u32 val, addr; val 2373 drivers/dma/pl330.c val = addr = 0; val 2375 drivers/dma/pl330.c val = readl(regs + SA(thrd->id)); val 2378 drivers/dma/pl330.c val = readl(regs + DA(thrd->id)); val 2385 drivers/dma/pl330.c if (!val) val 2388 drivers/dma/pl330.c return val - addr; val 993 drivers/dma/ppc4xx/adma.c u32 val = ioread32be(&xor_reg->ccbalr); val 995 drivers/dma/ppc4xx/adma.c iowrite32be(val, &xor_reg->cblalr); val 997 drivers/dma/ppc4xx/adma.c val = ioread32be(&xor_reg->crsr); val 998 drivers/dma/ppc4xx/adma.c iowrite32be(val | XOR_CRSR_XAE_BIT, val 4324 drivers/dma/ppc4xx/adma.c unsigned long val; val 4333 drivers/dma/ppc4xx/adma.c sscanf(buf, "%lx", &val); val 4334 drivers/dma/ppc4xx/adma.c dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_XORBA, val); val 4373 drivers/dma/ppc4xx/adma.c unsigned long reg, val; val 4384 drivers/dma/ppc4xx/adma.c sscanf(buf, "%lx", &val); val 4386 drivers/dma/ppc4xx/adma.c if (val & ~0x1FF) val 4389 drivers/dma/ppc4xx/adma.c val &= 0xFF; val 4392 drivers/dma/ppc4xx/adma.c reg |= val << MQ0_CFBHL_POLY; val 156 drivers/dma/pxa_dma.c #define phy_writel(phy, val, _reg) \ val 158 drivers/dma/pxa_dma.c writel((val), (phy)->base + _reg((phy)->idx)); \ val 161 drivers/dma/pxa_dma.c __func__, (u32)(val), #_reg); \ val 163 drivers/dma/pxa_dma.c #define phy_writel_relaxed(phy, val, _reg) \ val 165 drivers/dma/pxa_dma.c writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \ val 168 drivers/dma/pxa_dma.c __func__, (u32)(val), #_reg); \ val 453 drivers/dma/qcom/bam_dma.c u32 val; val 472 drivers/dma/qcom/bam_dma.c val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); val 473 drivers/dma/qcom/bam_dma.c val |= BIT(bchan->id); val 474 drivers/dma/qcom/bam_dma.c writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); val 480 drivers/dma/qcom/bam_dma.c val = P_EN | P_SYS_MODE; val 482 drivers/dma/qcom/bam_dma.c val |= P_DIRECTION; val 484 drivers/dma/qcom/bam_dma.c writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL)); val 538 drivers/dma/qcom/bam_dma.c u32 val; val 562 drivers/dma/qcom/bam_dma.c val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); val 563 drivers/dma/qcom/bam_dma.c val &= ~BIT(bchan->id); val 564 drivers/dma/qcom/bam_dma.c writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); val 1155 drivers/dma/qcom/bam_dma.c u32 val; val 1159 drivers/dma/qcom/bam_dma.c val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION)); val 1160 drivers/dma/qcom/bam_dma.c bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK; val 1168 drivers/dma/qcom/bam_dma.c val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES)); val 1169 drivers/dma/qcom/bam_dma.c bdev->num_channels = val & BAM_NUM_PIPES_MASK; val 1177 drivers/dma/qcom/bam_dma.c val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL)); val 1178 drivers/dma/qcom/bam_dma.c val |= BAM_SW_RST; val 1179 drivers/dma/qcom/bam_dma.c writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); val 1180 drivers/dma/qcom/bam_dma.c val &= ~BAM_SW_RST; val 1181 drivers/dma/qcom/bam_dma.c writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); val 1187 drivers/dma/qcom/bam_dma.c val |= BAM_EN; val 1188 drivers/dma/qcom/bam_dma.c writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); val 75 drivers/dma/qcom/hidma_ll.c #define HIDMA_CH_STATE(val) \ val 76 drivers/dma/qcom/hidma_ll.c ((val >> HIDMA_CH_STATE_BIT_POS) & HIDMA_CH_STATE_MASK) val 314 drivers/dma/qcom/hidma_ll.c u32 val; val 317 drivers/dma/qcom/hidma_ll.c val = readl(lldev->trca + HIDMA_TRCA_CTRLSTS_REG); val 318 drivers/dma/qcom/hidma_ll.c val &= ~(HIDMA_CH_CONTROL_MASK << 16); val 319 drivers/dma/qcom/hidma_ll.c val |= HIDMA_CH_RESET << 16; val 320 drivers/dma/qcom/hidma_ll.c writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG); val 326 drivers/dma/qcom/hidma_ll.c ret = readl_poll_timeout(lldev->trca + HIDMA_TRCA_CTRLSTS_REG, val, val 327 drivers/dma/qcom/hidma_ll.c HIDMA_CH_STATE(val) == HIDMA_CH_DISABLED, val 334 drivers/dma/qcom/hidma_ll.c val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG); val 335 drivers/dma/qcom/hidma_ll.c val &= ~(HIDMA_CH_CONTROL_MASK << 16); val 336 drivers/dma/qcom/hidma_ll.c val |= HIDMA_CH_RESET << 16; val 337 drivers/dma/qcom/hidma_ll.c writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG); val 343 drivers/dma/qcom/hidma_ll.c ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val, val 344 drivers/dma/qcom/hidma_ll.c HIDMA_CH_STATE(val) == HIDMA_CH_DISABLED, val 460 drivers/dma/qcom/hidma_ll.c u32 val; val 463 drivers/dma/qcom/hidma_ll.c val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG); val 464 drivers/dma/qcom/hidma_ll.c val &= ~(HIDMA_CH_CONTROL_MASK << 16); val 465 drivers/dma/qcom/hidma_ll.c val |= HIDMA_CH_ENABLE << 16; val 466 drivers/dma/qcom/hidma_ll.c writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG); val 468 drivers/dma/qcom/hidma_ll.c ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val, val 469 drivers/dma/qcom/hidma_ll.c hidma_is_chan_enabled(HIDMA_CH_STATE(val)), val 476 drivers/dma/qcom/hidma_ll.c val = readl(lldev->trca + HIDMA_TRCA_CTRLSTS_REG); val 477 drivers/dma/qcom/hidma_ll.c val &= ~(HIDMA_CH_CONTROL_MASK << 16); val 478 drivers/dma/qcom/hidma_ll.c val |= HIDMA_CH_ENABLE << 16; val 479 drivers/dma/qcom/hidma_ll.c writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG); val 481 drivers/dma/qcom/hidma_ll.c ret = readl_poll_timeout(lldev->trca + HIDMA_TRCA_CTRLSTS_REG, val, val 482 drivers/dma/qcom/hidma_ll.c hidma_is_chan_enabled(HIDMA_CH_STATE(val)), val 509 drivers/dma/qcom/hidma_ll.c u32 val; val 511 drivers/dma/qcom/hidma_ll.c val = readl(lldev->trca + HIDMA_TRCA_CTRLSTS_REG); val 512 drivers/dma/qcom/hidma_ll.c lldev->trch_state = HIDMA_CH_STATE(val); val 513 drivers/dma/qcom/hidma_ll.c val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG); val 514 drivers/dma/qcom/hidma_ll.c lldev->evch_state = HIDMA_CH_STATE(val); val 553 drivers/dma/qcom/hidma_ll.c u32 val; val 560 drivers/dma/qcom/hidma_ll.c val = readl(lldev->trca + HIDMA_TRCA_CTRLSTS_REG); val 561 drivers/dma/qcom/hidma_ll.c val &= ~(HIDMA_CH_CONTROL_MASK << 16); val 562 drivers/dma/qcom/hidma_ll.c val |= HIDMA_CH_SUSPEND << 16; val 563 drivers/dma/qcom/hidma_ll.c writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG); val 569 drivers/dma/qcom/hidma_ll.c ret = readl_poll_timeout(lldev->trca + HIDMA_TRCA_CTRLSTS_REG, val, val 570 drivers/dma/qcom/hidma_ll.c HIDMA_CH_STATE(val) == HIDMA_CH_SUSPENDED, val 575 drivers/dma/qcom/hidma_ll.c val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG); val 576 drivers/dma/qcom/hidma_ll.c val &= ~(HIDMA_CH_CONTROL_MASK << 16); val 577 drivers/dma/qcom/hidma_ll.c val |= HIDMA_CH_SUSPEND << 16; val 578 drivers/dma/qcom/hidma_ll.c writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG); val 584 drivers/dma/qcom/hidma_ll.c ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val, val 585 drivers/dma/qcom/hidma_ll.c HIDMA_CH_STATE(val) == HIDMA_CH_SUSPENDED, val 637 drivers/dma/qcom/hidma_ll.c u32 val; val 649 drivers/dma/qcom/hidma_ll.c val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG); val 650 drivers/dma/qcom/hidma_ll.c writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG); val 660 drivers/dma/qcom/hidma_ll.c val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG); val 661 drivers/dma/qcom/hidma_ll.c writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG); val 689 drivers/dma/qcom/hidma_ll.c u32 val; val 698 drivers/dma/qcom/hidma_ll.c val = readl(lldev->evca + HIDMA_EVCA_INTCTRL_REG); val 699 drivers/dma/qcom/hidma_ll.c val &= ~0xF; val 701 drivers/dma/qcom/hidma_ll.c val = val | 0x1; val 702 drivers/dma/qcom/hidma_ll.c writel(val, lldev->evca + HIDMA_EVCA_INTCTRL_REG); val 805 drivers/dma/qcom/hidma_ll.c u32 val; val 828 drivers/dma/qcom/hidma_ll.c val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG); val 829 drivers/dma/qcom/hidma_ll.c writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG); val 68 drivers/dma/qcom/hidma_mgmt.c u32 val; val 120 drivers/dma/qcom/hidma_mgmt.c val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET); val 121 drivers/dma/qcom/hidma_mgmt.c val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS); val 122 drivers/dma/qcom/hidma_mgmt.c val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS; val 123 drivers/dma/qcom/hidma_mgmt.c val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK; val 124 drivers/dma/qcom/hidma_mgmt.c val |= mgmtdev->max_read_request; val 125 drivers/dma/qcom/hidma_mgmt.c writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET); val 127 drivers/dma/qcom/hidma_mgmt.c val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET); val 128 drivers/dma/qcom/hidma_mgmt.c val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS); val 129 drivers/dma/qcom/hidma_mgmt.c val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS; val 130 drivers/dma/qcom/hidma_mgmt.c val &= ~HIDMA_MAX_RD_XACTIONS_MASK; val 131 drivers/dma/qcom/hidma_mgmt.c val |= mgmtdev->max_rd_xactions; val 132 drivers/dma/qcom/hidma_mgmt.c writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET); val 143 drivers/dma/qcom/hidma_mgmt.c val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i)); val 144 drivers/dma/qcom/hidma_mgmt.c val &= ~(1 << HIDMA_PRIORITY_BIT_POS); val 145 drivers/dma/qcom/hidma_mgmt.c val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS; val 146 drivers/dma/qcom/hidma_mgmt.c val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS); val 147 drivers/dma/qcom/hidma_mgmt.c val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS; val 148 drivers/dma/qcom/hidma_mgmt.c writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i)); val 151 drivers/dma/qcom/hidma_mgmt.c val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET); val 152 drivers/dma/qcom/hidma_mgmt.c val &= ~HIDMA_CHRESET_TIMEOUT_MASK; val 153 drivers/dma/qcom/hidma_mgmt.c val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK; val 154 drivers/dma/qcom/hidma_mgmt.c writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET); val 169 drivers/dma/qcom/hidma_mgmt.c u32 val; val 296 drivers/dma/qcom/hidma_mgmt.c val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET); val 297 drivers/dma/qcom/hidma_mgmt.c val |= 1; val 298 drivers/dma/qcom/hidma_mgmt.c writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET); val 23 drivers/dma/qcom/hidma_mgmt_sys.c int (*set)(struct hidma_mgmt_dev *mdev, u64 val); val 31 drivers/dma/qcom/hidma_mgmt_sys.c static int set_##name(struct hidma_mgmt_dev *mdev, u64 val) \ val 37 drivers/dma/qcom/hidma_mgmt_sys.c mdev->name = val; \ val 56 drivers/dma/qcom/hidma_mgmt_sys.c static int set_priority(struct hidma_mgmt_dev *mdev, unsigned int i, u64 val) val 65 drivers/dma/qcom/hidma_mgmt_sys.c mdev->priority[i] = val; val 72 drivers/dma/qcom/hidma_mgmt_sys.c static int set_weight(struct hidma_mgmt_dev *mdev, unsigned int i, u64 val) val 81 drivers/dma/qcom/hidma_mgmt_sys.c mdev->weight[i] = val; val 254 drivers/dma/s3c24xx-dma.c unsigned int val = readl(phy->base + S3C24XX_DSTAT); val 255 drivers/dma/s3c24xx-dma.c return val & S3C24XX_DSTAT_STAT_BUSY; val 447 drivers/dma/s3c24xx-dma.c u32 val; val 489 drivers/dma/s3c24xx-dma.c val = readl_relaxed(phy->base + S3C24XX_DMASKTRIG); val 490 drivers/dma/s3c24xx-dma.c val &= ~S3C24XX_DMASKTRIG_STOP; val 491 drivers/dma/s3c24xx-dma.c val |= S3C24XX_DMASKTRIG_ON; val 495 drivers/dma/s3c24xx-dma.c val |= S3C24XX_DMASKTRIG_SWTRIG; val 497 drivers/dma/s3c24xx-dma.c writel(val, phy->base + S3C24XX_DMASKTRIG); val 73 drivers/dma/sh/shdmac.c u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0; val 75 drivers/dma/sh/shdmac.c __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset); val 245 drivers/dma/sh/shdmac.c static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) val 251 drivers/dma/sh/shdmac.c sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); val 252 drivers/dma/sh/shdmac.c chcr_write(sh_chan, val); val 257 drivers/dma/sh/shdmac.c static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) val 276 drivers/dma/sh/shdmac.c __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), val 239 drivers/dma/sprd-dma.c u32 mask, u32 val) val 244 drivers/dma/sprd-dma.c tmp = (orig & ~mask) | val; val 249 drivers/dma/sprd-dma.c u32 mask, u32 val) val 254 drivers/dma/sprd-dma.c tmp = (orig & ~mask) | val; val 434 drivers/dma/sprd-dma.c u32 val, chn = schan->chn_num + 1; val 438 drivers/dma/sprd-dma.c val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; val 439 drivers/dma/sprd-dma.c val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; val 440 drivers/dma/sprd-dma.c val |= SPRD_DMA_GLB_2STAGE_EN; val 442 drivers/dma/sprd-dma.c val |= SPRD_DMA_GLB_SRC_INT; val 444 drivers/dma/sprd-dma.c sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); val 448 drivers/dma/sprd-dma.c val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; val 449 drivers/dma/sprd-dma.c val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; val 450 drivers/dma/sprd-dma.c val |= SPRD_DMA_GLB_2STAGE_EN; val 452 drivers/dma/sprd-dma.c val |= SPRD_DMA_GLB_SRC_INT; val 454 drivers/dma/sprd-dma.c sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); val 458 drivers/dma/sprd-dma.c val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & val 460 drivers/dma/sprd-dma.c val |= SPRD_DMA_GLB_2STAGE_EN; val 462 drivers/dma/sprd-dma.c val |= SPRD_DMA_GLB_DEST_INT; val 464 drivers/dma/sprd-dma.c sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); val 468 drivers/dma/sprd-dma.c val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & val 470 drivers/dma/sprd-dma.c val |= SPRD_DMA_GLB_2STAGE_EN; val 472 drivers/dma/sprd-dma.c val |= SPRD_DMA_GLB_DEST_INT; val 474 drivers/dma/sprd-dma.c sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); val 639 drivers/dma/st_fdma.c unsigned long val; val 647 drivers/dma/st_fdma.c val = fchan_read(fchan, FDMA_CH_CMD_OFST); val 648 drivers/dma/st_fdma.c val &= FDMA_CH_CMD_DATA_MASK; val 649 drivers/dma/st_fdma.c fchan_write(fchan, val, FDMA_CH_CMD_OFST); val 169 drivers/dma/st_fdma.h #define fdma_write(fdev, val, name) \ val 170 drivers/dma/st_fdma.h writel((val), (fdev)->slim_rproc->peri + name) val 189 drivers/dma/st_fdma.h #define fchan_write(fchan, val, name) \ val 190 drivers/dma/st_fdma.h writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \ val 196 drivers/dma/st_fdma.h #define dreq_write(fchan, val, name) \ val 197 drivers/dma/st_fdma.h writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \ val 211 drivers/dma/st_fdma.h #define fnode_write(fchan, val, name) \ val 212 drivers/dma/st_fdma.h writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \ val 281 drivers/dma/ste_dma40.c unsigned int val; val 286 drivers/dma/ste_dma40.c { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, val 289 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, val 290 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, val 291 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, val 292 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, val 293 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, val 294 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, val 295 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, val 296 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, val 297 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, val 298 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, val 299 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, val 300 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} val 304 drivers/dma/ste_dma40.c { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, val 307 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF}, val 308 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF}, val 309 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF}, val 310 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF}, val 311 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF}, val 312 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF}, val 313 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF}, val 314 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF}, val 315 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF}, val 316 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF}, val 317 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF}, val 318 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF}, val 319 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF}, val 320 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF}, val 321 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF} val 1257 drivers/dma/ste_dma40.c u32 val; val 1259 drivers/dma/ste_dma40.c val = readl(chanbase + D40_CHAN_REG_SSLNK); val 1260 drivers/dma/ste_dma40.c val |= readl(chanbase + D40_CHAN_REG_SDLNK); val 1262 drivers/dma/ste_dma40.c return val; val 1392 drivers/dma/ste_dma40.c u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); val 1393 drivers/dma/ste_dma40.c num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) val 3025 drivers/dma/ste_dma40.c u32 val[2]; val 3029 drivers/dma/ste_dma40.c val[0] = readl(base->virtbase + D40_DREG_PRSME); val 3030 drivers/dma/ste_dma40.c val[1] = readl(base->virtbase + D40_DREG_PRSMO); val 3035 drivers/dma/ste_dma40.c if (((val[i % 2] >> odd_even_bit) & 3) == 1) { val 3080 drivers/dma/ste_dma40.c val[0] = readl(base->virtbase + D40_DREG_PRTYP); val 3085 drivers/dma/ste_dma40.c (val[0] & 0x3) != 1) val 3088 drivers/dma/ste_dma40.c __func__, i, val[0] & 0x3); val 3090 drivers/dma/ste_dma40.c val[0] = val[0] >> 2; val 3331 drivers/dma/ste_dma40.c writel(dma_init_reg[i].val, val 3515 drivers/dma/ste_dma40.c u32 val; val 3558 drivers/dma/ste_dma40.c val = readl(base->virtbase + D40_DREG_LCPA); val 3559 drivers/dma/ste_dma40.c if (res->start != val && val != 0) { val 3562 drivers/dma/ste_dma40.c __func__, val, &res->start); val 241 drivers/dma/stm32-dma.c static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) val 243 drivers/dma/stm32-dma.c writel_relaxed(val, dmadev->base + reg); val 55 drivers/dma/stm32-dmamux.c static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val) val 57 drivers/dma/stm32-dmamux.c writel_relaxed(val, iomem + reg); val 316 drivers/dma/stm32-mdma.c static void stm32_mdma_write(struct stm32_mdma_device *dmadev, u32 reg, u32 val) val 318 drivers/dma/stm32-mdma.c writel_relaxed(val, dmadev->base + reg); val 232 drivers/dma/tegra20-apb-dma.c static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val) val 234 drivers/dma/tegra20-apb-dma.c writel(val, tdma->base_addr + reg); val 243 drivers/dma/tegra20-apb-dma.c u32 reg, u32 val) val 245 drivers/dma/tegra20-apb-dma.c writel(val, tdc->chan_addr + reg); val 29 drivers/dma/tegra210-adma.c #define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12) val 37 drivers/dma/tegra210-adma.c #define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28) val 38 drivers/dma/tegra210-adma.c #define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24) val 41 drivers/dma/tegra210-adma.c #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf) val 46 drivers/dma/tegra210-adma.c #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8) val 47 drivers/dma/tegra210-adma.c #define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0xf) val 48 drivers/dma/tegra210-adma.c #define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0x1f) << 8) val 49 drivers/dma/tegra210-adma.c #define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0x1f) val 70 drivers/dma/tegra210-adma.c #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift) val 170 drivers/dma/tegra210-adma.c static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val) val 172 drivers/dma/tegra210-adma.c writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); val 180 drivers/dma/tegra210-adma.c static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val) val 182 drivers/dma/tegra210-adma.c writel(val, tdc->chan_addr + reg); val 278 drivers/dma/ti/cppi41.c static void cppi_writel(u32 val, void *__iomem *mem) val 280 drivers/dma/ti/cppi41.c __raw_writel(val, mem); val 288 drivers/dma/ti/cppi41.c static u32 pd_trans_len(u32 val) val 290 drivers/dma/ti/cppi41.c return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1); val 312 drivers/dma/ti/cppi41.c u32 val; val 315 drivers/dma/ti/cppi41.c val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i)); val 316 drivers/dma/ti/cppi41.c if (i == QMGR_PENDING_SLOT_Q(first_completion_queue) && val) { val 323 drivers/dma/ti/cppi41.c val &= ~mask; val 326 drivers/dma/ti/cppi41.c if (val) val 329 drivers/dma/ti/cppi41.c while (val) { val 338 drivers/dma/ti/cppi41.c q_num = __fls(val); val 339 drivers/dma/ti/cppi41.c val &= ~(1 << q_num); val 51 drivers/dma/ti/dma-crossbar.c static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u8 val) val 59 drivers/dma/ti/dma-crossbar.c writeb_relaxed(val, iomem + (63 - event % 4)); val 61 drivers/dma/ti/dma-crossbar.c writeb_relaxed(val, iomem + event); val 220 drivers/dma/ti/dma-crossbar.c static inline void ti_dra7_xbar_write(void __iomem *iomem, int xbar, u16 val) val 222 drivers/dma/ti/dma-crossbar.c writew_relaxed(val, iomem + (xbar * 2)); val 307 drivers/dma/ti/edma.c static inline void edma_write(struct edma_cc *ecc, int offset, int val) val 309 drivers/dma/ti/edma.c __raw_writel(val, ecc->base + offset); val 315 drivers/dma/ti/edma.c unsigned val = edma_read(ecc, offset); val 317 drivers/dma/ti/edma.c val &= and; val 318 drivers/dma/ti/edma.c val |= or; val 319 drivers/dma/ti/edma.c edma_write(ecc, offset, val); val 324 drivers/dma/ti/edma.c unsigned val = edma_read(ecc, offset); val 326 drivers/dma/ti/edma.c val &= and; val 327 drivers/dma/ti/edma.c edma_write(ecc, offset, val); val 332 drivers/dma/ti/edma.c unsigned val = edma_read(ecc, offset); val 334 drivers/dma/ti/edma.c val |= or; val 335 drivers/dma/ti/edma.c edma_write(ecc, offset, val); val 345 drivers/dma/ti/edma.c unsigned val) val 347 drivers/dma/ti/edma.c edma_write(ecc, offset + (i << 2), val); val 369 drivers/dma/ti/edma.c int j, unsigned val) val 371 drivers/dma/ti/edma.c edma_write(ecc, offset + ((i * 2 + j) << 2), val); val 386 drivers/dma/ti/edma.c unsigned val) val 388 drivers/dma/ti/edma.c edma_write(ecc, EDMA_SHADOW0 + offset, val); val 392 drivers/dma/ti/edma.c int i, unsigned val) val 394 drivers/dma/ti/edma.c edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); val 404 drivers/dma/ti/edma.c int param_no, unsigned val) val 406 drivers/dma/ti/edma.c edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); val 1565 drivers/dma/ti/edma.c unsigned int val; val 1590 drivers/dma/ti/edma.c val = edma_read_array(ecc, EDMA_EMR, j); val 1591 drivers/dma/ti/edma.c if (!val) val 1594 drivers/dma/ti/edma.c dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); val 1595 drivers/dma/ti/edma.c emr = val; val 1609 drivers/dma/ti/edma.c val = edma_read(ecc, EDMA_QEMR); val 1610 drivers/dma/ti/edma.c if (val) { val 1611 drivers/dma/ti/edma.c dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); val 1613 drivers/dma/ti/edma.c edma_write(ecc, EDMA_QEMCR, val); val 1614 drivers/dma/ti/edma.c edma_shadow0_write(ecc, SH_QSECR, val); val 1617 drivers/dma/ti/edma.c val = edma_read(ecc, EDMA_CCERR); val 1618 drivers/dma/ti/edma.c if (val) { val 1619 drivers/dma/ti/edma.c dev_warn(ecc->dev, "CCERR 0x%08x\n", val); val 1621 drivers/dma/ti/edma.c edma_write(ecc, EDMA_CCERRCLR, val); val 288 drivers/dma/ti/omap-dma.c static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr) val 292 drivers/dma/ti/omap-dma.c writew_relaxed(val, addr); val 295 drivers/dma/ti/omap-dma.c writew_relaxed(val, addr); val 296 drivers/dma/ti/omap-dma.c writew_relaxed(val >> 16, addr + 2); val 299 drivers/dma/ti/omap-dma.c writel_relaxed(val, addr); val 308 drivers/dma/ti/omap-dma.c unsigned val; val 312 drivers/dma/ti/omap-dma.c val = readw_relaxed(addr); val 315 drivers/dma/ti/omap-dma.c val = readw_relaxed(addr); val 316 drivers/dma/ti/omap-dma.c val |= readw_relaxed(addr + 2) << 16; val 319 drivers/dma/ti/omap-dma.c val = readl_relaxed(addr); val 323 drivers/dma/ti/omap-dma.c val = 0; val 326 drivers/dma/ti/omap-dma.c return val; val 329 drivers/dma/ti/omap-dma.c static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val) val 335 drivers/dma/ti/omap-dma.c omap_dma_write(val, r->type, od->base + r->offset); val 347 drivers/dma/ti/omap-dma.c static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val) val 351 drivers/dma/ti/omap-dma.c omap_dma_write(val, r->type, c->channel_base + r->offset); val 371 drivers/dma/ti/omap-dma.c unsigned val = omap_dma_chan_read(c, CSR); val 374 drivers/dma/ti/omap-dma.c omap_dma_chan_write(c, CSR, val); val 376 drivers/dma/ti/omap-dma.c return val; val 430 drivers/dma/ti/omap-dma.c u32 val; val 434 drivers/dma/ti/omap-dma.c val = omap_dma_chan_read(c, CCR); val 435 drivers/dma/ti/omap-dma.c if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) val 444 drivers/dma/ti/omap-dma.c if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) val 453 drivers/dma/ti/omap-dma.c uint32_t val; val 460 drivers/dma/ti/omap-dma.c val = omap_dma_chan_read(c, CCR); val 461 drivers/dma/ti/omap-dma.c if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { val 465 drivers/dma/ti/omap-dma.c val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; val 466 drivers/dma/ti/omap-dma.c val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); val 467 drivers/dma/ti/omap-dma.c omap_dma_glbl_write(od, OCP_SYSCONFIG, val); val 469 drivers/dma/ti/omap-dma.c val = omap_dma_chan_read(c, CCR); val 470 drivers/dma/ti/omap-dma.c val &= ~CCR_ENABLE; val 471 drivers/dma/ti/omap-dma.c omap_dma_chan_write(c, CCR, val); val 478 drivers/dma/ti/omap-dma.c if (!(val & CCR_ENABLE)) val 481 drivers/dma/ti/omap-dma.c val &= ~CCR_ENABLE; val 482 drivers/dma/ti/omap-dma.c omap_dma_chan_write(c, CCR, val); val 491 drivers/dma/ti/omap-dma.c val = omap_dma_chan_read(c, CLNK_CTRL); val 494 drivers/dma/ti/omap-dma.c val |= 1 << 14; /* set the STOP_LNK bit */ val 496 drivers/dma/ti/omap-dma.c val &= ~CLNK_CTRL_ENABLE_LNK; val 498 drivers/dma/ti/omap-dma.c omap_dma_chan_write(c, CLNK_CTRL, val); val 657 drivers/dma/ti/omap-dma.c unsigned val; val 660 drivers/dma/ti/omap-dma.c val = BIT(c->dma_ch); val 661 drivers/dma/ti/omap-dma.c omap_dma_glbl_write(od, IRQSTATUS_L1, val); val 662 drivers/dma/ti/omap-dma.c od->irq_enable_mask |= val; val 665 drivers/dma/ti/omap-dma.c val = omap_dma_glbl_read(od, IRQENABLE_L0); val 666 drivers/dma/ti/omap-dma.c val &= ~BIT(c->dma_ch); val 667 drivers/dma/ti/omap-dma.c omap_dma_glbl_write(od, IRQENABLE_L0, val); val 752 drivers/dma/ti/omap-dma.c uint32_t val; val 754 drivers/dma/ti/omap-dma.c val = omap_dma_chan_read(c, reg); val 755 drivers/dma/ti/omap-dma.c if (val == 0 && od->plat->errata & DMA_ERRATA_3_3) val 756 drivers/dma/ti/omap-dma.c val = omap_dma_chan_read(c, reg); val 758 drivers/dma/ti/omap-dma.c return val; val 37 drivers/dma/txx9dmac.c #define channel64_writeq(dc, name, val) \ val 38 drivers/dma/txx9dmac.c __raw_writeq((val), &(__dma_regs(dc)->name)) val 41 drivers/dma/txx9dmac.c #define channel64_writel(dc, name, val) \ val 42 drivers/dma/txx9dmac.c __raw_writel((val), &(__dma_regs(dc)->name)) val 46 drivers/dma/txx9dmac.c #define channel32_writel(dc, name, val) \ val 47 drivers/dma/txx9dmac.c __raw_writel((val), &(__dma_regs32(dc)->name)) val 50 drivers/dma/txx9dmac.c #define channel_writeq(dc, name, val) channel64_writeq(dc, name, val) val 54 drivers/dma/txx9dmac.c #define channel_writel(dc, name, val) \ val 56 drivers/dma/txx9dmac.c channel64_writel(dc, name, val) : channel32_writel(dc, name, val)) val 66 drivers/dma/txx9dmac.c static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val) val 69 drivers/dma/txx9dmac.c channel64_writeq(dc, CHAR, val); val 71 drivers/dma/txx9dmac.c channel64_writel(dc, CHAR, val); val 92 drivers/dma/txx9dmac.c static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val) val 95 drivers/dma/txx9dmac.c channel64_write_CHAR(dc, val); val 97 drivers/dma/txx9dmac.c channel32_writel(dc, CHAR, val); val 114 drivers/dma/txx9dmac.c #define dma64_writel(ddev, name, val) \ val 115 drivers/dma/txx9dmac.c __raw_writel((val), &(__txx9dmac_regs(ddev)->name)) val 119 drivers/dma/txx9dmac.c #define dma32_writel(ddev, name, val) \ val 120 drivers/dma/txx9dmac.c __raw_writel((val), &(__txx9dmac_regs32(ddev)->name)) val 125 drivers/dma/txx9dmac.c #define dma_writel(ddev, name, val) \ val 127 drivers/dma/txx9dmac.c dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val)) val 151 drivers/dma/txx9dmac.c struct txx9dmac_desc *desc, dma_addr_t val) val 154 drivers/dma/txx9dmac.c desc->hwdesc.CHAR = val; val 156 drivers/dma/txx9dmac.c desc->hwdesc32.CHAR = val; val 159 drivers/dma/uniphier-mdmac.c u32 val; val 172 drivers/dma/uniphier-mdmac.c val, val & irq_flag, 0, 20); val 343 drivers/dma/xgene-dma.c u32 val; val 345 drivers/dma/xgene-dma.c val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW); val 346 drivers/dma/xgene-dma.c return !(val & XGENE_DMA_PQ_DISABLE_MASK); val 1013 drivers/dma/xgene-dma.c u32 val, i; val 1015 drivers/dma/xgene-dma.c val = ioread32(pdma->csr_dma + XGENE_DMA_INT); val 1018 drivers/dma/xgene-dma.c iowrite32(val, pdma->csr_dma + XGENE_DMA_INT); val 1021 drivers/dma/xgene-dma.c int_mask = val >> XGENE_DMA_INT_MASK_SHIFT; val 1024 drivers/dma/xgene-dma.c "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]); val 1050 drivers/dma/xgene-dma.c u32 i, val; val 1098 drivers/dma/xgene-dma.c val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE); val 1099 drivers/dma/xgene-dma.c XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num); val 1100 drivers/dma/xgene-dma.c iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE); val 1105 drivers/dma/xgene-dma.c u32 ring_id, val; val 1109 drivers/dma/xgene-dma.c val = ioread32(ring->pdma->csr_ring + val 1111 drivers/dma/xgene-dma.c XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num); val 1112 drivers/dma/xgene-dma.c iowrite32(val, ring->pdma->csr_ring + val 1272 drivers/dma/xgene-dma.c u32 val; val 1275 drivers/dma/xgene-dma.c val = ioread32(pdma->csr_dma + XGENE_DMA_GCR); val 1276 drivers/dma/xgene-dma.c XGENE_DMA_CH_SETUP(val); val 1277 drivers/dma/xgene-dma.c XGENE_DMA_ENABLE(val); val 1278 drivers/dma/xgene-dma.c iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR); val 1283 drivers/dma/xgene-dma.c u32 val; val 1285 drivers/dma/xgene-dma.c val = ioread32(pdma->csr_dma + XGENE_DMA_GCR); val 1286 drivers/dma/xgene-dma.c XGENE_DMA_DISABLE(val); val 1287 drivers/dma/xgene-dma.c iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR); val 1335 drivers/dma/xgene-dma.c u32 val; val 1352 drivers/dma/xgene-dma.c val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR); val 1357 drivers/dma/xgene-dma.c XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val), val 1358 drivers/dma/xgene-dma.c XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL); val 456 drivers/dma/xilinx/xilinx_dma.c #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ val 457 drivers/dma/xilinx/xilinx_dma.c readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \ val 1045 drivers/dma/xilinx/xilinx_dma.c u32 val; val 1050 drivers/dma/xilinx/xilinx_dma.c return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, val 1051 drivers/dma/xilinx/xilinx_dma.c val & XILINX_DMA_DMASR_HALTED, 0, val 1063 drivers/dma/xilinx/xilinx_dma.c u32 val; val 1065 drivers/dma/xilinx/xilinx_dma.c return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, val 1066 drivers/dma/xilinx/xilinx_dma.c val & XILINX_DMA_DMASR_IDLE, 0, val 1077 drivers/dma/xilinx/xilinx_dma.c u32 val; val 1082 drivers/dma/xilinx/xilinx_dma.c err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, val 1083 drivers/dma/xilinx/xilinx_dma.c !(val & XILINX_DMA_DMASR_HALTED), 0, val 334 drivers/dma/xilinx/zynqmp_dma.c u32 val; val 337 drivers/dma/xilinx/zynqmp_dma.c val = readl(chan->regs + ZYNQMP_DMA_ISR); val 338 drivers/dma/xilinx/zynqmp_dma.c writel(val, chan->regs + ZYNQMP_DMA_ISR); val 341 drivers/dma/xilinx/zynqmp_dma.c val = ZYNQMP_DMA_AXCOHRNT; val 342 drivers/dma/xilinx/zynqmp_dma.c val = (val & ~ZYNQMP_DMA_AXCACHE) | val 344 drivers/dma/xilinx/zynqmp_dma.c writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR); val 347 drivers/dma/xilinx/zynqmp_dma.c val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR); val 349 drivers/dma/xilinx/zynqmp_dma.c val = (val & ~ZYNQMP_DMA_ARCACHE) | val 351 drivers/dma/xilinx/zynqmp_dma.c val = (val & ~ZYNQMP_DMA_AWCACHE) | val 354 drivers/dma/xilinx/zynqmp_dma.c writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR); val 357 drivers/dma/xilinx/zynqmp_dma.c val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT); val 358 drivers/dma/xilinx/zynqmp_dma.c val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT); val 537 drivers/dma/xilinx/zynqmp_dma.c u32 val; val 539 drivers/dma/xilinx/zynqmp_dma.c val = readl(chan->regs + ZYNQMP_DMA_CTRL0); val 540 drivers/dma/xilinx/zynqmp_dma.c val |= ZYNQMP_DMA_POINT_TYPE_SG; val 541 drivers/dma/xilinx/zynqmp_dma.c writel(val, chan->regs + ZYNQMP_DMA_CTRL0); val 543 drivers/dma/xilinx/zynqmp_dma.c val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR); val 544 drivers/dma/xilinx/zynqmp_dma.c val = (val & ~ZYNQMP_DMA_ARLEN) | val 546 drivers/dma/xilinx/zynqmp_dma.c val = (val & ~ZYNQMP_DMA_AWLEN) | val 548 drivers/dma/xilinx/zynqmp_dma.c writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR); val 140 drivers/dma/zx_dma.c u32 val = 0; val 142 drivers/dma/zx_dma.c val = readl_relaxed(phy->base + REG_ZX_CTRL); val 143 drivers/dma/zx_dma.c val &= ~ZX_CH_ENABLE; val 144 drivers/dma/zx_dma.c val |= ZX_FORCE_CLOSE; val 145 drivers/dma/zx_dma.c writel_relaxed(val, phy->base + REG_ZX_CTRL); val 147 drivers/dma/zx_dma.c val = 0x1 << phy->idx; val 148 drivers/dma/zx_dma.c writel_relaxed(val, d->base + REG_ZX_TC_IRQ_RAW); val 149 drivers/dma/zx_dma.c writel_relaxed(val, d->base + REG_ZX_SRC_ERR_IRQ_RAW); val 150 drivers/dma/zx_dma.c writel_relaxed(val, d->base + REG_ZX_DST_ERR_IRQ_RAW); val 151 drivers/dma/zx_dma.c writel_relaxed(val, d->base + REG_ZX_CFG_ERR_IRQ_RAW); val 694 drivers/dma/zx_dma.c u32 val = 0; val 696 drivers/dma/zx_dma.c val = readl_relaxed(c->phy->base + REG_ZX_CTRL); val 697 drivers/dma/zx_dma.c val &= ~ZX_CH_ENABLE; val 698 drivers/dma/zx_dma.c writel_relaxed(val, c->phy->base + REG_ZX_CTRL); val 706 drivers/dma/zx_dma.c u32 val = 0; val 708 drivers/dma/zx_dma.c val = readl_relaxed(c->phy->base + REG_ZX_CTRL); val 709 drivers/dma/zx_dma.c val |= ZX_CH_ENABLE; val 710 drivers/dma/zx_dma.c writel_relaxed(val, c->phy->base + REG_ZX_CTRL); val 518 drivers/edac/altera_edac.c unsigned int val) val 523 drivers/edac/altera_edac.c arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0, val 540 drivers/edac/altera_edac.c unsigned int *val) val 548 drivers/edac/altera_edac.c *val = (unsigned int)result.a1; val 62 drivers/edac/amd64_edac.c u32 *val, const char *func) val 66 drivers/edac/amd64_edac.c err = pci_read_config_dword(pdev, offset, val); val 75 drivers/edac/amd64_edac.c u32 val, const char *func) val 79 drivers/edac/amd64_edac.c err = pci_write_config_dword(pdev, offset, val); val 115 drivers/edac/amd64_edac.c int offset, u32 *val) val 154 drivers/edac/amd64_edac.c return amd64_read_pci_cfg(pvt->F2, offset, val); val 2958 drivers/edac/amd64_edac.c u32 val; val 2963 drivers/edac/amd64_edac.c amd64_read_pci_cfg(pvt->F3, NBCFG, &val); val 2965 drivers/edac/amd64_edac.c pvt->nbcfg = val; val 2968 drivers/edac/amd64_edac.c pvt->mc_node_id, val, val 2969 drivers/edac/amd64_edac.c !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); val 486 drivers/edac/amd64_edac.h u32 *val, const char *func); val 488 drivers/edac/amd64_edac.h u32 val, const char *func); val 490 drivers/edac/amd64_edac.h #define amd64_read_pci_cfg(pdev, offset, val) \ val 491 drivers/edac/amd64_edac.h __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) val 493 drivers/edac/amd64_edac.h #define amd64_write_pci_cfg(pdev, offset, val) \ val 494 drivers/edac/amd64_edac.h __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) val 571 drivers/edac/amd8111_edac.c int val; val 579 drivers/edac/amd8111_edac.c val = pci_register_driver(&amd8111_edac_dev_driver); val 580 drivers/edac/amd8111_edac.c val |= pci_register_driver(&amd8111_edac_pci_driver); val 582 drivers/edac/amd8111_edac.c return val; val 41 drivers/edac/aspeed_edac.c static int regmap_reg_write(void *context, unsigned int reg, unsigned int val) val 48 drivers/edac/aspeed_edac.c writel(val, regs + reg); val 57 drivers/edac/aspeed_edac.c static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val) val 61 drivers/edac/aspeed_edac.c *val = readl(regs + reg); val 53 drivers/edac/edac_mc_sysfs.c static int edac_set_poll_msec(const char *val, const struct kernel_param *kp) val 58 drivers/edac/edac_mc_sysfs.c if (!val) val 61 drivers/edac/edac_mc_sysfs.c ret = kstrtouint(val, 0, &i); val 25 drivers/edac/edac_module.c unsigned long val; val 28 drivers/edac/edac_module.c ret = kstrtoul(buf, 0, &val); val 32 drivers/edac/edac_module.c if (val > 4) val 95 drivers/edac/fsl_ddr_edac.c unsigned long val; val 99 drivers/edac/fsl_ddr_edac.c rc = kstrtoul(data, 0, &val); val 103 drivers/edac/fsl_ddr_edac.c ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val); val 115 drivers/edac/fsl_ddr_edac.c unsigned long val; val 119 drivers/edac/fsl_ddr_edac.c rc = kstrtoul(data, 0, &val); val 123 drivers/edac/fsl_ddr_edac.c ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val); val 135 drivers/edac/fsl_ddr_edac.c unsigned long val; val 139 drivers/edac/fsl_ddr_edac.c rc = kstrtoul(data, 0, &val); val 143 drivers/edac/fsl_ddr_edac.c ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val); val 194 drivers/edac/i10nm_base.c static int debugfs_u64_set(void *data, u64 val) val 198 drivers/edac/i10nm_base.c pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); val 205 drivers/edac/i10nm_base.c m.addr = val; val 866 drivers/edac/i7core_edac.c static int write_and_test(struct pci_dev *dev, const int where, const u32 val) val 873 drivers/edac/i7core_edac.c where, val); val 878 drivers/edac/i7core_edac.c pci_write_config_dword(dev, where, val); val 881 drivers/edac/i7core_edac.c if (read == val) val 888 drivers/edac/i7core_edac.c where, val, read); val 1811 drivers/edac/i7core_edac.c static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val, val 1036 drivers/edac/mce_amd.c amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) val 62 drivers/edac/mv64x60_edac.c u32 val; val 64 drivers/edac/mv64x60_edac.c val = readl(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); val 65 drivers/edac/mv64x60_edac.c if (!val) val 124 drivers/edac/pnd2_edac.c #define U64_LSHIFT(val, s) ((u64)(val) << (s)) val 144 drivers/edac/pnd2_edac.c #define P2SB_WRITE(size, off, val) \ val 145 drivers/edac/pnd2_edac.c pci_bus_write_config_##size(p2sb_bus, P2SB_DEVFN, off, val) val 1392 drivers/edac/pnd2_edac.c static int pnd2_mce_check_error(struct notifier_block *nb, unsigned long val, void *data) val 1453 drivers/edac/pnd2_edac.c static int debugfs_u64_set(void *data, u64 val) val 1458 drivers/edac/pnd2_edac.c *(u64 *)data = val; val 1462 drivers/edac/pnd2_edac.c m.addr = val; val 20 drivers/edac/ppc4xx_edac.h #define PPC_REG_VAL(bit, val) ((val) << ((PPC_REG_BITS - 1) - (bit))) val 21 drivers/edac/ppc4xx_edac.h #define PPC_REG_DECODE(bit, val) ((val) >> ((PPC_REG_BITS - 1) - (bit))) val 3132 drivers/edac/sb_edac.c static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, val 547 drivers/edac/skx_base.c static int debugfs_u64_set(void *data, u64 val) val 551 drivers/edac/skx_base.c pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); val 558 drivers/edac/skx_base.c m.addr = val; val 273 drivers/edac/skx_common.c u32 val = GET_BITFIELD(reg, lobit, hibit); val 275 drivers/edac/skx_common.c if (val < minval || val > maxval) { val 276 drivers/edac/skx_common.c edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg); val 279 drivers/edac/skx_common.c return val + add; val 565 drivers/edac/skx_common.c int skx_mce_check_error(struct notifier_block *nb, unsigned long val, val 139 drivers/edac/skx_common.h int skx_mce_check_error(struct notifier_block *nb, unsigned long val, val 275 drivers/edac/thunderx_edac.c u64 val; \ val 278 drivers/edac/thunderx_edac.c res = kstrtoull_from_user(data, count, 0, &val); \ val 281 drivers/edac/thunderx_edac.c writeq(val, pdata->regs + _reg); \ val 308 drivers/edac/thunderx_edac.c u64 val; val 311 drivers/edac/thunderx_edac.c res = kstrtoull_from_user(data, count, 0, &val); val 315 drivers/edac/thunderx_edac.c writeq(val, lmc->regs + LMC_INT_W1S); val 87 drivers/edac/ti_edac.c static void ti_edac_writel(struct ti_edac *edac, u32 val, u16 offset) val 89 drivers/edac/ti_edac.c writel_relaxed(val, edac->reg + offset); val 135 drivers/edac/ti_edac.c u32 val; val 140 drivers/edac/ti_edac.c val = ti_edac_readl(edac, EMIF_SDRAM_CONFIG); val 143 drivers/edac/ti_edac.c bits = ((val & SDRAM_PAGESIZE_MASK) >> SDRAM_PAGESIZE_SHIFT) + 8; val 144 drivers/edac/ti_edac.c bits += ((val & SDRAM_ROWSIZE_MASK) >> SDRAM_ROWSIZE_SHIFT) + 9; val 145 drivers/edac/ti_edac.c bits += (val & SDRAM_IBANK_MASK) >> SDRAM_IBANK_SHIFT; val 147 drivers/edac/ti_edac.c if (val & SDRAM_NARROW_MODE_MASK) { val 156 drivers/edac/ti_edac.c bits += ((val & SDRAM_K2_PAGESIZE_MASK) >> val 158 drivers/edac/ti_edac.c bits += (val & SDRAM_K2_IBANK_MASK) >> SDRAM_K2_IBANK_SHIFT; val 159 drivers/edac/ti_edac.c bits += (val & SDRAM_K2_EBANK_MASK) >> SDRAM_K2_EBANK_SHIFT; val 161 drivers/edac/ti_edac.c val = (val & SDRAM_K2_NARROW_MODE_MASK) >> val 163 drivers/edac/ti_edac.c switch (val) { val 183 drivers/edac/ti_edac.c if ((val & SDRAM_TYPE_MASK) == SDRAM_TYPE_DDR2) val 188 drivers/edac/ti_edac.c val = ti_edac_readl(edac, EMIF_ECC_CTRL); val 189 drivers/edac/ti_edac.c if (val & ECC_ENABLED) val 66 drivers/edac/xgene_edac.c static void xgene_edac_pcp_rd(struct xgene_edac *edac, u32 reg, u32 *val) val 68 drivers/edac/xgene_edac.c *val = readl(edac->pcp_csr + reg); val 74 drivers/edac/xgene_edac.c u32 val; val 77 drivers/edac/xgene_edac.c val = readl(edac->pcp_csr + reg); val 78 drivers/edac/xgene_edac.c val &= ~bits_mask; val 79 drivers/edac/xgene_edac.c writel(val, edac->pcp_csr + reg); val 86 drivers/edac/xgene_edac.c u32 val; val 89 drivers/edac/xgene_edac.c val = readl(edac->pcp_csr + reg); val 90 drivers/edac/xgene_edac.c val |= bits_mask; val 91 drivers/edac/xgene_edac.c writel(val, edac->pcp_csr + reg); val 250 drivers/edac/xgene_edac.c unsigned int val; val 281 drivers/edac/xgene_edac.c val = readl(ctx->mcu_csr + MCUGECR); val 282 drivers/edac/xgene_edac.c val |= MCU_GECR_DEMANDUCINTREN_MASK | val 286 drivers/edac/xgene_edac.c writel(val, ctx->mcu_csr + MCUGECR); val 289 drivers/edac/xgene_edac.c val = readl(ctx->mcu_csr + MCUGECR); val 290 drivers/edac/xgene_edac.c val &= ~(MCU_GECR_DEMANDUCINTREN_MASK | val 294 drivers/edac/xgene_edac.c writel(val, ctx->mcu_csr + MCUGECR); val 524 drivers/edac/xgene_edac.c u32 val; val 528 drivers/edac/xgene_edac.c val = readl(pg_f + MEMERR_CPU_ICFESR_PAGE_OFFSET); val 529 drivers/edac/xgene_edac.c if (!val) val 533 drivers/edac/xgene_edac.c ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val, val 534 drivers/edac/xgene_edac.c MEMERR_CPU_ICFESR_ERRWAY_RD(val), val 535 drivers/edac/xgene_edac.c MEMERR_CPU_ICFESR_ERRINDEX_RD(val), val 536 drivers/edac/xgene_edac.c MEMERR_CPU_ICFESR_ERRINFO_RD(val)); val 537 drivers/edac/xgene_edac.c if (val & MEMERR_CPU_ICFESR_CERR_MASK) val 539 drivers/edac/xgene_edac.c if (val & MEMERR_CPU_ICFESR_MULTCERR_MASK) val 541 drivers/edac/xgene_edac.c switch (MEMERR_CPU_ICFESR_ERRTYPE_RD(val)) { val 561 drivers/edac/xgene_edac.c writel(val, pg_f + MEMERR_CPU_ICFESR_PAGE_OFFSET); val 563 drivers/edac/xgene_edac.c if (val & (MEMERR_CPU_ICFESR_CERR_MASK | val 568 drivers/edac/xgene_edac.c val = readl(pg_f + MEMERR_CPU_LSUESR_PAGE_OFFSET); val 569 drivers/edac/xgene_edac.c if (!val) val 573 drivers/edac/xgene_edac.c ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val, val 574 drivers/edac/xgene_edac.c MEMERR_CPU_LSUESR_ERRWAY_RD(val), val 575 drivers/edac/xgene_edac.c MEMERR_CPU_LSUESR_ERRINDEX_RD(val), val 576 drivers/edac/xgene_edac.c MEMERR_CPU_LSUESR_ERRINFO_RD(val)); val 577 drivers/edac/xgene_edac.c if (val & MEMERR_CPU_LSUESR_CERR_MASK) val 579 drivers/edac/xgene_edac.c if (val & MEMERR_CPU_LSUESR_MULTCERR_MASK) val 581 drivers/edac/xgene_edac.c switch (MEMERR_CPU_LSUESR_ERRTYPE_RD(val)) { val 605 drivers/edac/xgene_edac.c writel(val, pg_f + MEMERR_CPU_LSUESR_PAGE_OFFSET); val 607 drivers/edac/xgene_edac.c if (val & (MEMERR_CPU_LSUESR_CERR_MASK | val 612 drivers/edac/xgene_edac.c val = readl(pg_f + MEMERR_CPU_MMUESR_PAGE_OFFSET); val 613 drivers/edac/xgene_edac.c if (!val) val 617 drivers/edac/xgene_edac.c ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val, val 618 drivers/edac/xgene_edac.c MEMERR_CPU_MMUESR_ERRWAY_RD(val), val 619 drivers/edac/xgene_edac.c MEMERR_CPU_MMUESR_ERRINDEX_RD(val), val 620 drivers/edac/xgene_edac.c MEMERR_CPU_MMUESR_ERRINFO_RD(val), val 621 drivers/edac/xgene_edac.c val & MEMERR_CPU_MMUESR_ERRREQSTR_LSU_MASK ? "LSU" : "ICF"); val 622 drivers/edac/xgene_edac.c if (val & MEMERR_CPU_MMUESR_CERR_MASK) val 624 drivers/edac/xgene_edac.c if (val & MEMERR_CPU_MMUESR_MULTCERR_MASK) val 626 drivers/edac/xgene_edac.c switch (MEMERR_CPU_MMUESR_ERRTYPE_RD(val)) { val 654 drivers/edac/xgene_edac.c writel(val, pg_f + MEMERR_CPU_MMUESR_PAGE_OFFSET); val 666 drivers/edac/xgene_edac.c u32 val; val 670 drivers/edac/xgene_edac.c val = readl(pg_e + MEMERR_L2C_L2ESR_PAGE_OFFSET); val 671 drivers/edac/xgene_edac.c if (!val) val 677 drivers/edac/xgene_edac.c ctx->pmd, val, val_hi, val_lo); val 680 drivers/edac/xgene_edac.c MEMERR_L2C_L2ESR_ERRSYN_RD(val), val 681 drivers/edac/xgene_edac.c MEMERR_L2C_L2ESR_ERRWAY_RD(val), val 682 drivers/edac/xgene_edac.c MEMERR_L2C_L2ESR_ERRCPU_RD(val), val 683 drivers/edac/xgene_edac.c MEMERR_L2C_L2ESR_ERRGROUP_RD(val), val 684 drivers/edac/xgene_edac.c MEMERR_L2C_L2ESR_ERRACTION_RD(val)); val 686 drivers/edac/xgene_edac.c if (val & MEMERR_L2C_L2ESR_ERR_MASK) val 688 drivers/edac/xgene_edac.c if (val & MEMERR_L2C_L2ESR_MULTICERR_MASK) val 690 drivers/edac/xgene_edac.c if (val & MEMERR_L2C_L2ESR_UCERR_MASK) val 692 drivers/edac/xgene_edac.c if (val & MEMERR_L2C_L2ESR_MULTUCERR_MASK) val 695 drivers/edac/xgene_edac.c switch (MEMERR_L2C_L2ESR_ERRTYPE_RD(val)) { val 711 drivers/edac/xgene_edac.c writel(val, pg_e + MEMERR_L2C_L2ESR_PAGE_OFFSET); val 713 drivers/edac/xgene_edac.c if (val & (MEMERR_L2C_L2ESR_ERR_MASK | val 716 drivers/edac/xgene_edac.c if (val & (MEMERR_L2C_L2ESR_UCERR_MASK | val 723 drivers/edac/xgene_edac.c val = readl(pg_d + CPUX_L2C_L2RTOSR_PAGE_OFFSET); val 724 drivers/edac/xgene_edac.c if (val) { val 729 drivers/edac/xgene_edac.c ctx->pmd, val, val_hi, val_lo); val 730 drivers/edac/xgene_edac.c writel(val, pg_d + CPUX_L2C_L2RTOSR_PAGE_OFFSET); val 895 drivers/edac/xgene_edac.c u32 val; val 906 drivers/edac/xgene_edac.c rc = regmap_read(edac->efuse_map, 0, &val); val 909 drivers/edac/xgene_edac.c if (!xgene_edac_pmd_available(val, pmd)) { val 1117 drivers/edac/xgene_edac.c u32 val; val 1119 drivers/edac/xgene_edac.c val = readl(ctx->dev_csr + L3C_ECR); val 1120 drivers/edac/xgene_edac.c val |= L3C_UCERREN | L3C_CERREN; val 1124 drivers/edac/xgene_edac.c val |= L3C_ECR_UCINTREN | L3C_ECR_CINTREN; val 1126 drivers/edac/xgene_edac.c val &= ~(L3C_ECR_UCINTREN | L3C_ECR_CINTREN); val 1128 drivers/edac/xgene_edac.c writel(val, ctx->dev_csr + L3C_ECR); val 146 drivers/extcon/extcon-arizona.c unsigned int mask = 0, val = 0; val 160 drivers/extcon/extcon-arizona.c val = ARIZONA_HP1L_SHRTO; val 163 drivers/extcon/extcon-arizona.c val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI; val 178 drivers/extcon/extcon-arizona.c val = ARIZONA_RMV_SHRT_HP1L; val 200 drivers/extcon/extcon-arizona.c mask, val); val 206 drivers/extcon/extcon-arizona.c mask, val); val 407 drivers/extcon/extcon-arizona.c unsigned int val, range; val 410 drivers/extcon/extcon-arizona.c ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, &val); val 419 drivers/extcon/extcon-arizona.c if (!(val & ARIZONA_HP_DONE)) { val 421 drivers/extcon/extcon-arizona.c val); val 425 drivers/extcon/extcon-arizona.c val &= ARIZONA_HP_LVL_MASK; val 429 drivers/extcon/extcon-arizona.c if (!(val & ARIZONA_HP_DONE_B)) { val 431 drivers/extcon/extcon-arizona.c val); val 435 drivers/extcon/extcon-arizona.c ret = regmap_read(arizona->regmap, ARIZONA_HP_DACVAL, &val); val 448 drivers/extcon/extcon-arizona.c (val < arizona_hpdet_b_ranges[range].threshold || val 449 drivers/extcon/extcon-arizona.c val >= ARIZONA_HPDET_B_RANGE_MAX)) { val 462 drivers/extcon/extcon-arizona.c if (val < arizona_hpdet_b_ranges[range].threshold || val 463 drivers/extcon/extcon-arizona.c val >= ARIZONA_HPDET_B_RANGE_MAX) { val 469 drivers/extcon/extcon-arizona.c val, range); val 471 drivers/extcon/extcon-arizona.c val = arizona_hpdet_b_ranges[range].factor_b val 472 drivers/extcon/extcon-arizona.c / ((val * 100) - val 477 drivers/extcon/extcon-arizona.c if (!(val & ARIZONA_HP_DONE_B)) { val 479 drivers/extcon/extcon-arizona.c val); val 483 drivers/extcon/extcon-arizona.c val &= ARIZONA_HP_LVL_B_MASK; val 485 drivers/extcon/extcon-arizona.c val /= 2; val 494 drivers/extcon/extcon-arizona.c (val >= arizona_hpdet_c_ranges[range].max)) { val 507 drivers/extcon/extcon-arizona.c if (range && (val < arizona_hpdet_c_ranges[range].min)) { val 510 drivers/extcon/extcon-arizona.c val = arizona_hpdet_c_ranges[range].min; val 520 drivers/extcon/extcon-arizona.c dev_dbg(arizona->dev, "HP impedance %d ohms\n", val); val 521 drivers/extcon/extcon-arizona.c return val; val 820 drivers/extcon/extcon-arizona.c unsigned int val = 0, lvl; val 844 drivers/extcon/extcon-arizona.c ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_4, &val); val 853 drivers/extcon/extcon-arizona.c dev_dbg(arizona->dev, "MICDET_ADCVAL: %x\n", val); val 855 drivers/extcon/extcon-arizona.c val &= ARIZONA_MICDET_ADCVAL_MASK; val 856 drivers/extcon/extcon-arizona.c if (val < ARRAY_SIZE(arizona_micd_levels)) val 857 drivers/extcon/extcon-arizona.c val = arizona_micd_levels[val]; val 859 drivers/extcon/extcon-arizona.c val = INT_MAX; val 861 drivers/extcon/extcon-arizona.c if (val <= QUICK_HEADPHONE_MAX_OHM) val 862 drivers/extcon/extcon-arizona.c val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_0; val 863 drivers/extcon/extcon-arizona.c else if (val <= MICROPHONE_MIN_OHM) val 864 drivers/extcon/extcon-arizona.c val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_1; val 865 drivers/extcon/extcon-arizona.c else if (val <= MICROPHONE_MAX_OHM) val 866 drivers/extcon/extcon-arizona.c val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_8; val 868 drivers/extcon/extcon-arizona.c val = ARIZONA_MICD_LVL_8; val 871 drivers/extcon/extcon-arizona.c for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) { val 872 drivers/extcon/extcon-arizona.c ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val); val 880 drivers/extcon/extcon-arizona.c dev_dbg(arizona->dev, "MICDET: %x\n", val); val 882 drivers/extcon/extcon-arizona.c if (!(val & ARIZONA_MICD_VALID)) { val 890 drivers/extcon/extcon-arizona.c if (i == 10 && !(val & MICD_LVL_0_TO_8)) { val 897 drivers/extcon/extcon-arizona.c if (!(val & ARIZONA_MICD_STS)) { val 907 drivers/extcon/extcon-arizona.c if (info->detecting && (val & ARIZONA_MICD_LVL_8)) { val 935 drivers/extcon/extcon-arizona.c if (info->detecting && (val & MICD_LVL_1_TO_7)) { val 960 drivers/extcon/extcon-arizona.c if (val & MICD_LVL_0_TO_7) { val 964 drivers/extcon/extcon-arizona.c lvl = val & ARIZONA_MICD_LVL_MASK; val 987 drivers/extcon/extcon-arizona.c val); val 1053 drivers/extcon/extcon-arizona.c unsigned int val; val 1058 drivers/extcon/extcon-arizona.c &val); val 1067 drivers/extcon/extcon-arizona.c if (val & ARIZONA_HP_DONE) val 1071 drivers/extcon/extcon-arizona.c if (val & ARIZONA_HP_DONE_B) val 1088 drivers/extcon/extcon-arizona.c unsigned int val, present, mask; val 1110 drivers/extcon/extcon-arizona.c ret = regmap_read(arizona->regmap, ARIZONA_AOD_IRQ_RAW_STATUS, &val); val 1119 drivers/extcon/extcon-arizona.c val &= mask; val 1120 drivers/extcon/extcon-arizona.c if (val == info->last_jackdet) { val 1137 drivers/extcon/extcon-arizona.c info->last_jackdet = val; val 1294 drivers/extcon/extcon-arizona.c unsigned int val = ARIZONA_ACCDET_MODE_HPL; val 1297 drivers/extcon/extcon-arizona.c device_property_read_u32(arizona->dev, "wlf,hpdet-channel", &val); val 1298 drivers/extcon/extcon-arizona.c switch (val) { val 1301 drivers/extcon/extcon-arizona.c pdata->hpdet_channel = val; val 1305 drivers/extcon/extcon-arizona.c "Wrong wlf,hpdet-channel DT value %d\n", val); val 1352 drivers/extcon/extcon-arizona.c unsigned int val; val 1594 drivers/extcon/extcon-arizona.c val = 0xc101; val 1596 drivers/extcon/extcon-arizona.c val &= ~ARIZONA_GPN_PU; val 1599 drivers/extcon/extcon-arizona.c val); val 132 drivers/extcon/extcon-axp288.c unsigned int val, i, clear_mask = 0; val 136 drivers/extcon/extcon-axp288.c ret = regmap_read(info->regmap, AXP288_PS_BOOT_REASON_REG, &val); val 142 drivers/extcon/extcon-axp288.c bits = val & GENMASK(ARRAY_SIZE(axp288_pwr_up_down_info) - 1, 0); val 178 drivers/extcon/extcon-fsa9480.c int ret, val; val 180 drivers/extcon/extcon-fsa9480.c ret = regmap_read(usbsw->regmap, reg, &val); val 186 drivers/extcon/extcon-fsa9480.c return val; val 223 drivers/extcon/extcon-fsa9480.c u16 val; val 231 drivers/extcon/extcon-fsa9480.c val = val2 << 8 | val1; val 236 drivers/extcon/extcon-fsa9480.c fsa9480_handle_change(usbsw, usbsw->cable & ~val, false); val 239 drivers/extcon/extcon-fsa9480.c fsa9480_handle_change(usbsw, val & ~usbsw->cable, true); val 241 drivers/extcon/extcon-fsa9480.c usbsw->cable = val; val 194 drivers/extcon/extcon-intel-cht-wc.c int ret, val; val 200 drivers/extcon/extcon-intel-cht-wc.c val = CHT_WC_VBUS_GPIO_CTLO_DRV_OD | CHT_WC_VBUS_GPIO_CTLO_DIR_OUT; val 202 drivers/extcon/extcon-intel-cht-wc.c val |= CHT_WC_VBUS_GPIO_CTLO_OUTPUT; val 204 drivers/extcon/extcon-intel-cht-wc.c ret = regmap_write(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, val); val 212 drivers/extcon/extcon-intel-cht-wc.c unsigned int val = enable ? CHT_WC_CHGRCTRL1_OTGMODE : 0; val 216 drivers/extcon/extcon-intel-cht-wc.c CHT_WC_CHGRCTRL1_OTGMODE, val); val 224 drivers/extcon/extcon-intel-cht-wc.c unsigned int val = enable ? 0 : CHT_WC_CHGDISCTRL_OUT; val 228 drivers/extcon/extcon-intel-cht-wc.c CHT_WC_CHGDISCTRL_OUT, val); val 317 drivers/extcon/extcon-intel-cht-wc.c int ret, mask, val; val 319 drivers/extcon/extcon-intel-cht-wc.c val = enable ? 0 : CHT_WC_CHGDISCTRL_FN; val 321 drivers/extcon/extcon-intel-cht-wc.c CHT_WC_CHGDISCTRL_FN, val); val 328 drivers/extcon/extcon-intel-cht-wc.c val = enable ? mask : 0; val 329 drivers/extcon/extcon-intel-cht-wc.c ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val); val 195 drivers/extcon/extcon-max14577.c u8 val, bool attached) val 210 drivers/extcon/extcon-max14577.c ctrl1 = val; val 257 drivers/extcon/extcon-max77693.c u8 val, bool attached) val 263 drivers/extcon/extcon-max77693.c ctrl1 = val; val 200 drivers/extcon/extcon-max77843.c u8 val, bool attached, bool nobccomp) val 207 drivers/extcon/extcon-max77843.c ctrl1 = val; val 195 drivers/extcon/extcon-max8997.c u8 val, bool attached) val 201 drivers/extcon/extcon-max8997.c ctrl1 = val; val 34 drivers/extcon/extcon-rt8973a.c u8 val; val 80 drivers/extcon/extcon-rt8973a.c .val = RT8973A_REG_CONTROL1_ADC_EN_MASK val 526 drivers/extcon/extcon-rt8973a.c u8 val = 0; val 529 drivers/extcon/extcon-rt8973a.c val = ~info->reg_data[i].val; val 531 drivers/extcon/extcon-rt8973a.c val = info->reg_data[i].val; val 533 drivers/extcon/extcon-rt8973a.c regmap_update_bits(info->regmap, reg, mask, val); val 32 drivers/extcon/extcon-sm5502.c unsigned int val; val 69 drivers/extcon/extcon-sm5502.c .val = SM5502_REG_RESET_MASK, val 73 drivers/extcon/extcon-sm5502.c .val = SM5502_REG_CONTROL_MASK_INT_MASK, val 77 drivers/extcon/extcon-sm5502.c .val = SM5502_REG_INTM1_KP_MASK val 83 drivers/extcon/extcon-sm5502.c .val = SM5502_REG_INTM2_VBUS_DET_MASK val 538 drivers/extcon/extcon-sm5502.c unsigned int val = 0; val 541 drivers/extcon/extcon-sm5502.c val |= ~info->reg_data[i].val; val 543 drivers/extcon/extcon-sm5502.c val = info->reg_data[i].val; val 544 drivers/extcon/extcon-sm5502.c regmap_write(info->regmap, info->reg_data[i].reg, val); val 245 drivers/firewire/nosy.c set_phy_reg(struct pcilynx *lynx, int addr, int val) val 252 drivers/firewire/nosy.c if (val > 0xff) { val 254 drivers/firewire/nosy.c "PHY register value %d out of range\n", val); val 258 drivers/firewire/nosy.c LINK_PHY_ADDR(addr) | LINK_PHY_WDATA(val)); val 551 drivers/firewire/ohci.c u32 val; val 556 drivers/firewire/ohci.c val = reg_read(ohci, OHCI1394_PhyControl); val 557 drivers/firewire/ohci.c if (!~val) val 560 drivers/firewire/ohci.c if (val & OHCI1394_PhyControl_ReadDone) val 561 drivers/firewire/ohci.c return OHCI1394_PhyControl_ReadData(val); val 576 drivers/firewire/ohci.c static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) val 581 drivers/firewire/ohci.c OHCI1394_PhyControl_Write(addr, val)); val 583 drivers/firewire/ohci.c val = reg_read(ohci, OHCI1394_PhyControl); val 584 drivers/firewire/ohci.c if (!~val) val 587 drivers/firewire/ohci.c if (!(val & OHCI1394_PhyControl_WritePending)) val 593 drivers/firewire/ohci.c ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); val 2165 drivers/firewire/ohci.c u32 val; val 2170 drivers/firewire/ohci.c val = reg_read(ohci, OHCI1394_HCControlSet); val 2171 drivers/firewire/ohci.c if (!~val) val 2174 drivers/firewire/ohci.c if (!(val & OHCI1394_HCControl_softReset)) val 299 drivers/firmware/arm_scmi/perf.c u##w val = 0; \ val 302 drivers/firmware/arm_scmi/perf.c val = ioread##w(db->addr) & db->mask; \ val 303 drivers/firmware/arm_scmi/perf.c iowrite##w((u##w)db->set | val, db->addr); \ val 322 drivers/firmware/arm_scmi/perf.c u64 val = 0; val 325 drivers/firmware/arm_scmi/perf.c val = ioread64_hi_lo(db->addr) & db->mask; val 326 drivers/firmware/arm_scmi/perf.c iowrite64_hi_lo(db->set | val, db->addr); val 737 drivers/firmware/arm_scpi.c static int scpi_sensor_get_value(u16 sensor, u64 *val) val 750 drivers/firmware/arm_scpi.c *val = le32_to_cpup((__le32 *)&value); val 752 drivers/firmware/arm_scpi.c *val = le64_to_cpu(value); val 165 drivers/firmware/broadcom/bcm47xx_nvram.c int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len) val 189 drivers/firmware/broadcom/bcm47xx_nvram.c return snprintf(val, val_len, "%s", value); val 67 drivers/firmware/broadcom/bcm47xx_sprom.c type *val, type allset, bool fallback) \ val 85 drivers/firmware/broadcom/bcm47xx_sprom.c *val = var; \ val 100 drivers/firmware/broadcom/bcm47xx_sprom.c u32 val; val 105 drivers/firmware/broadcom/bcm47xx_sprom.c err = kstrtou32(strim(buf), 0, &val); val 111 drivers/firmware/broadcom/bcm47xx_sprom.c *val_lo = (val & 0x0000FFFFU); val 112 drivers/firmware/broadcom/bcm47xx_sprom.c *val_hi = (val & 0xFFFF0000U) >> 16; val 121 drivers/firmware/broadcom/bcm47xx_sprom.c u32 val; val 126 drivers/firmware/broadcom/bcm47xx_sprom.c err = kstrtou32(strim(buf), 0, &val); val 133 drivers/firmware/broadcom/bcm47xx_sprom.c if (val == 0xffff || val == 0xffffffff) val 136 drivers/firmware/broadcom/bcm47xx_sprom.c *leddc_on_time = val & 0xff; val 137 drivers/firmware/broadcom/bcm47xx_sprom.c *leddc_off_time = (val >> 16) & 0xff; val 141 drivers/firmware/broadcom/bcm47xx_sprom.c u8 val[6], bool fallback) val 151 drivers/firmware/broadcom/bcm47xx_sprom.c if (!mac_pton(buf, val)) val 156 drivers/firmware/broadcom/bcm47xx_sprom.c char val[2], bool fallback) val 170 drivers/firmware/broadcom/bcm47xx_sprom.c memcpy(val, buf, 2); val 653 drivers/firmware/dmi-sysfs.c int val; val 667 drivers/firmware/dmi-sysfs.c val = 0; val 668 drivers/firmware/dmi-sysfs.c error = dmi_walk(dmi_sysfs_register_handle, &val); val 671 drivers/firmware/dmi-sysfs.c if (val) { val 672 drivers/firmware/dmi-sysfs.c error = val; val 725 drivers/firmware/efi/efi.c u64 val; val 738 drivers/firmware/efi/efi.c val = of_read_number(prop, len / sizeof(u32)); val 741 drivers/firmware/efi/efi.c *(u32 *)dest = val; val 743 drivers/firmware/efi/efi.c *(u64 *)dest = val; val 747 drivers/firmware/efi/efi.c params[i].size * 2, val); val 41 drivers/firmware/efi/libstub/tpm.c u8 val = 1; val 55 drivers/firmware/efi/libstub/tpm.c EFI_VARIABLE_RUNTIME_ACCESS, sizeof(val), &val); val 539 drivers/firmware/google/gsmi.c unsigned long val; val 545 drivers/firmware/google/gsmi.c rc = kstrtoul(buf, 0, &val); val 553 drivers/firmware/google/gsmi.c if (val > 100) val 557 drivers/firmware/google/gsmi.c param.percentage = val; val 699 drivers/firmware/google/gsmi.c static u64 __init local_hash_64(u64 val, unsigned bits) val 701 drivers/firmware/google/gsmi.c u64 hash = val; val 17 drivers/firmware/imx/misc.c u32 val; val 37 drivers/firmware/imx/misc.c u32 val; val 52 drivers/firmware/imx/misc.c u8 ctrl, u32 val) val 63 drivers/firmware/imx/misc.c msg.val = val; val 82 drivers/firmware/imx/misc.c u8 ctrl, u32 *val) val 102 drivers/firmware/imx/misc.c if (val != NULL) val 103 drivers/firmware/imx/misc.c *val = resp->val; val 298 drivers/firmware/iscsi_ibft.c __be32 val; val 314 drivers/firmware/iscsi_ibft.c val = cpu_to_be32(~((1 << (32-nic->subnet_mask_prefix))-1)); val 315 drivers/firmware/iscsi_ibft.c str += sprintf(str, "%pI4", &val); val 601 drivers/firmware/qcom_scm-32.c unsigned int *val) val 607 drivers/firmware/qcom_scm-32.c *val = ret; val 612 drivers/firmware/qcom_scm-32.c int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) val 615 drivers/firmware/qcom_scm-32.c addr, val); val 226 drivers/firmware/qcom_scm-64.c desc.args[1] = req[0].val; val 228 drivers/firmware/qcom_scm-64.c desc.args[3] = req[1].val; val 230 drivers/firmware/qcom_scm-64.c desc.args[5] = req[2].val; val 232 drivers/firmware/qcom_scm-64.c desc.args[7] = req[3].val; val 234 drivers/firmware/qcom_scm-64.c desc.args[9] = req[4].val; val 476 drivers/firmware/qcom_scm-64.c unsigned int *val) val 488 drivers/firmware/qcom_scm-64.c *val = res.a1; val 493 drivers/firmware/qcom_scm-64.c int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) val 499 drivers/firmware/qcom_scm-64.c desc.args[1] = val; val 348 drivers/firmware/qcom_scm.c int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) val 350 drivers/firmware/qcom_scm.c return __qcom_scm_io_readl(__scm->dev, addr, val); val 354 drivers/firmware/qcom_scm.c int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) val 356 drivers/firmware/qcom_scm.c return __qcom_scm_io_writel(__scm->dev, addr, val); val 30 drivers/firmware/qcom_scm.h extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val); val 31 drivers/firmware/qcom_scm.h extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val); val 93 drivers/firmware/ti_sci.h #define TI_SCI_MSG_FLAG(val) (1 << (val)) val 96 drivers/firmware/trusted_foundations.c static void tf_cache_write_sec(unsigned long val, unsigned int reg) val 105 drivers/firmware/trusted_foundations.c if (val == L2X0_CTRL_EN) val 97 drivers/fpga/altera-cvp.c int where, u8 *val) val 100 drivers/fpga/altera-cvp.c val); val 104 drivers/fpga/altera-cvp.c int where, u32 *val) val 107 drivers/fpga/altera-cvp.c val); val 111 drivers/fpga/altera-cvp.c int where, u32 val) val 114 drivers/fpga/altera-cvp.c val); val 133 drivers/fpga/altera-cvp.c static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val) val 135 drivers/fpga/altera-cvp.c writel(val, conf->map); val 138 drivers/fpga/altera-cvp.c static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val) val 141 drivers/fpga/altera-cvp.c val); val 148 drivers/fpga/altera-cvp.c u32 val; val 151 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val); val 152 drivers/fpga/altera-cvp.c val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK; val 153 drivers/fpga/altera-cvp.c val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF; val 154 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val); val 164 drivers/fpga/altera-cvp.c u32 val; val 171 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_STATUS, &val); val 172 drivers/fpga/altera-cvp.c if ((val & status_mask) == status_val) val 185 drivers/fpga/altera-cvp.c u32 val; val 189 drivers/fpga/altera-cvp.c ret = altera_read_config_dword(conf, VSE_CVP_STATUS, &val); val 190 drivers/fpga/altera-cvp.c if (ret || (val & VSE_CVP_STATUS_CFG_ERR)) { val 206 drivers/fpga/altera-cvp.c u32 val; val 210 drivers/fpga/altera-cvp.c ret = altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val); val 217 drivers/fpga/altera-cvp.c val &= ~VSE_CVP_PROG_CTRL_MASK; val 218 drivers/fpga/altera-cvp.c ret = altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val); val 235 drivers/fpga/altera-cvp.c u8 val; val 238 drivers/fpga/altera-cvp.c ret = altera_read_config_byte(conf, VSE_CVP_TX_CREDITS, &val); val 246 drivers/fpga/altera-cvp.c if (val - (u8)conf->sent_packets) val 253 drivers/fpga/altera-cvp.c val, conf->sent_packets); val 290 drivers/fpga/altera-cvp.c u32 val; val 293 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val); val 294 drivers/fpga/altera-cvp.c val &= ~VSE_CVP_PROG_CTRL_START_XFER; val 295 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val); val 298 drivers/fpga/altera-cvp.c val &= ~VSE_CVP_PROG_CTRL_CONFIG; val 299 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val); val 323 drivers/fpga/altera-cvp.c u32 iflags, val; val 342 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_STATUS, &val); val 343 drivers/fpga/altera-cvp.c if (!(val & VSE_CVP_STATUS_CVP_EN)) { val 344 drivers/fpga/altera-cvp.c dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val); val 348 drivers/fpga/altera-cvp.c if (val & VSE_CVP_STATUS_CFG_RDY) { val 360 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val); val 361 drivers/fpga/altera-cvp.c val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL; val 362 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val); val 365 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val); val 366 drivers/fpga/altera-cvp.c val |= VSE_CVP_MODE_CTRL_CVP_MODE; val 367 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val); val 387 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val); val 389 drivers/fpga/altera-cvp.c val |= VSE_CVP_PROG_CTRL_CONFIG; val 390 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val); val 417 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val); val 418 drivers/fpga/altera-cvp.c val |= VSE_CVP_PROG_CTRL_START_XFER; val 419 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val); val 423 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val); val 424 drivers/fpga/altera-cvp.c val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK; val 425 drivers/fpga/altera-cvp.c val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF; val 426 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val); val 488 drivers/fpga/altera-cvp.c u32 mask, val; val 496 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_UNCOR_ERR_STATUS, &val); val 497 drivers/fpga/altera-cvp.c if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) { val 503 drivers/fpga/altera-cvp.c altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val); val 504 drivers/fpga/altera-cvp.c val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL; val 505 drivers/fpga/altera-cvp.c val &= ~VSE_CVP_MODE_CTRL_CVP_MODE; val 506 drivers/fpga/altera-cvp.c altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val); val 582 drivers/fpga/altera-cvp.c u16 cmd, val; val 597 drivers/fpga/altera-cvp.c pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val); val 598 drivers/fpga/altera-cvp.c if (val != VSE_PCIE_EXT_CAP_ID_VAL) { val 599 drivers/fpga/altera-cvp.c dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val); val 37 drivers/fpga/altera-pr-ip-core.c u32 val; val 39 drivers/fpga/altera-pr-ip-core.c val = readl(priv->reg_base + ALT_PR_CSR_OFST); val 41 drivers/fpga/altera-pr-ip-core.c val &= ALT_PR_CSR_STATUS_MSK; val 43 drivers/fpga/altera-pr-ip-core.c switch (val) { val 73 drivers/fpga/altera-pr-ip-core.c val, err, __func__); val 82 drivers/fpga/altera-pr-ip-core.c u32 val; val 90 drivers/fpga/altera-pr-ip-core.c val = readl(priv->reg_base + ALT_PR_CSR_OFST); val 92 drivers/fpga/altera-pr-ip-core.c if (val & ALT_PR_CSR_PR_START) { val 99 drivers/fpga/altera-pr-ip-core.c writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); val 180 drivers/fpga/altera-pr-ip-core.c u32 val; val 188 drivers/fpga/altera-pr-ip-core.c val = readl(priv->reg_base + ALT_PR_CSR_OFST); val 191 drivers/fpga/altera-pr-ip-core.c (val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT, val 192 drivers/fpga/altera-pr-ip-core.c (int)(val & ALT_PR_CSR_PR_START)); val 64 drivers/fpga/dfl-fme-error.c u64 v, val; val 66 drivers/fpga/dfl-fme-error.c if (kstrtou64(buf, 0, &val)) val 75 drivers/fpga/dfl-fme-error.c if (val == v) val 109 drivers/fpga/dfl-fme-error.c u64 v, val; val 111 drivers/fpga/dfl-fme-error.c if (kstrtou64(buf, 0, &val)) val 120 drivers/fpga/dfl-fme-error.c if (val == v) val 222 drivers/fpga/dfl-fme-error.c u64 v, val; val 225 drivers/fpga/dfl-fme-error.c if (kstrtou64(buf, 0, &val)) val 234 drivers/fpga/dfl-fme-error.c if (val == v) val 130 drivers/fpga/socfpga-a10.c u32 val; val 140 drivers/fpga/socfpga-a10.c regmap_read_poll_timeout(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, val, val 141 drivers/fpga/socfpga-a10.c val, 1, 100); val 230 drivers/fpga/socfpga-a10.c u32 val; val 232 drivers/fpga/socfpga-a10.c regmap_read(priv->regmap, A10_FPGAMGR_IMGCFG_STAT_OFST, &val); val 234 drivers/fpga/socfpga-a10.c return val; val 165 drivers/fpga/socfpga.c u32 val; val 167 drivers/fpga/socfpga.c val = socfpga_fpga_readl(priv, offset); val 168 drivers/fpga/socfpga.c val |= bits; val 169 drivers/fpga/socfpga.c socfpga_fpga_writel(priv, offset, val); val 175 drivers/fpga/socfpga.c u32 val; val 177 drivers/fpga/socfpga.c val = socfpga_fpga_readl(priv, offset); val 178 drivers/fpga/socfpga.c val &= ~bits; val 179 drivers/fpga/socfpga.c socfpga_fpga_writel(priv, offset, val); val 27 drivers/fpga/xilinx-pr-decoupler.c u32 offset, u32 val) val 29 drivers/fpga/xilinx-pr-decoupler.c writel(val, d->io_base + offset); val 138 drivers/fpga/zynq-fpga.c u32 val) val 140 drivers/fpga/zynq-fpga.c writel(val, priv->io_base + offset); val 149 drivers/fpga/zynq-fpga.c #define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \ val 150 drivers/fpga/zynq-fpga.c readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \ val 106 drivers/fsi/fsi-core.c uint8_t slave_id, uint32_t addr, void *val, size_t size); val 108 drivers/fsi/fsi-core.c uint8_t slave_id, uint32_t addr, const void *val, size_t size); val 128 drivers/fsi/fsi-core.c int fsi_device_read(struct fsi_device *dev, uint32_t addr, void *val, val 134 drivers/fsi/fsi-core.c return fsi_slave_read(dev->slave, dev->addr + addr, val, size); val 138 drivers/fsi/fsi-core.c int fsi_device_write(struct fsi_device *dev, uint32_t addr, const void *val, val 144 drivers/fsi/fsi-core.c return fsi_slave_write(dev->slave, dev->addr + addr, val, size); val 148 drivers/fsi/fsi-core.c int fsi_device_peek(struct fsi_device *dev, void *val) val 152 drivers/fsi/fsi-core.c return fsi_slave_read(dev->slave, addr, val, sizeof(uint32_t)); val 340 drivers/fsi/fsi-core.c void *val, size_t size) val 351 drivers/fsi/fsi-core.c id, addr, val, size); val 365 drivers/fsi/fsi-core.c const void *val, size_t size) val 376 drivers/fsi/fsi-core.c id, addr, val, size); val 823 drivers/fsi/fsi-core.c unsigned long val; val 826 drivers/fsi/fsi-core.c if (kstrtoul(buf, 0, &val) < 0) val 829 drivers/fsi/fsi-core.c if (val < 1 || val > 16) val 836 drivers/fsi/fsi-core.c slave->t_send_delay = val; val 837 drivers/fsi/fsi-core.c slave->t_echo_delay = val; val 1124 drivers/fsi/fsi-core.c uint8_t slave_id, uint32_t addr, void *val, size_t size) val 1132 drivers/fsi/fsi-core.c rc = master->read(master, link, slave_id, addr, val, size); val 1135 drivers/fsi/fsi-core.c false, val, rc); val 1141 drivers/fsi/fsi-core.c uint8_t slave_id, uint32_t addr, const void *val, size_t size) val 1145 drivers/fsi/fsi-core.c trace_fsi_master_write(master, link, slave_id, addr, size, val); val 1149 drivers/fsi/fsi-core.c rc = master->write(master, link, slave_id, addr, val, size); val 1152 drivers/fsi/fsi-core.c true, val, rc); val 598 drivers/fsi/fsi-master-ast-cf.c uint8_t id, uint32_t addr, void *val, val 611 drivers/fsi/fsi-master-ast-cf.c rc = fsi_master_acf_xfer(master, id, &cmd, size, val); val 622 drivers/fsi/fsi-master-ast-cf.c uint8_t id, uint32_t addr, const void *val, val 633 drivers/fsi/fsi-master-ast-cf.c build_ar_command(master, &cmd, id, addr, size, val); val 635 drivers/fsi/fsi-master-ast-cf.c id, addr, size, *(uint32_t *)val); val 905 drivers/fsi/fsi-master-ast-cf.c uint32_t val; val 913 drivers/fsi/fsi-master-ast-cf.c val = ioread32(master->cvic + CVIC_EN_REG); val 914 drivers/fsi/fsi-master-ast-cf.c if (val & 2) val 918 drivers/fsi/fsi-master-ast-cf.c if (!(val & 2)) { val 928 drivers/fsi/fsi-master-ast-cf.c uint32_t val; val 970 drivers/fsi/fsi-master-ast-cf.c val = ioread8(master->sram + CF_STARTED); val 971 drivers/fsi/fsi-master-ast-cf.c if (val) val 975 drivers/fsi/fsi-master-ast-cf.c if (!val) { val 1093 drivers/fsi/fsi-master-ast-cf.c unsigned long val; val 1097 drivers/fsi/fsi-master-ast-cf.c err = kstrtoul(buf, 0, &val); val 1101 drivers/fsi/fsi-master-ast-cf.c external_mode = !!val; val 1131 drivers/fsi/fsi-master-ast-cf.c u8 val; val 1163 drivers/fsi/fsi-master-ast-cf.c val = ioread8(master->sram + ARB_REG); val 1164 drivers/fsi/fsi-master-ast-cf.c if (val != ARB_ARM_REQ) val 1170 drivers/fsi/fsi-master-ast-cf.c if (val != ARB_ARM_ACK) val 463 drivers/fsi/fsi-master-gpio.c uint64_t val = response.msg; val 465 drivers/fsi/fsi-master-gpio.c val >>= 4; val 466 drivers/fsi/fsi-master-gpio.c val &= (1ull << (size * 8)) - 1; val 469 drivers/fsi/fsi-master-gpio.c data_byte[size-i-1] = val; val 470 drivers/fsi/fsi-master-gpio.c val >>= 8; val 562 drivers/fsi/fsi-master-gpio.c uint8_t id, uint32_t addr, void *val, size_t size) val 573 drivers/fsi/fsi-master-gpio.c rc = fsi_master_gpio_xfer(master, id, &cmd, size, val); val 581 drivers/fsi/fsi-master-gpio.c uint8_t id, uint32_t addr, const void *val, size_t size) val 591 drivers/fsi/fsi-master-gpio.c build_ar_command(master, &cmd, id, addr, size, val); val 728 drivers/fsi/fsi-master-gpio.c unsigned long val; val 732 drivers/fsi/fsi-master-gpio.c err = kstrtoul(buf, 0, &val); val 736 drivers/fsi/fsi-master-gpio.c external_mode = !!val; val 92 drivers/fsi/fsi-master-hub.c uint8_t id, uint32_t addr, void *val, size_t size) val 100 drivers/fsi/fsi-master-hub.c return fsi_slave_read(hub->upstream->slave, addr, val, size); val 104 drivers/fsi/fsi-master-hub.c uint8_t id, uint32_t addr, const void *val, size_t size) val 112 drivers/fsi/fsi-master-hub.c return fsi_slave_write(hub->upstream->slave, addr, val, size); val 57 drivers/fsi/fsi-master.h uint32_t addr, void *val, size_t size); val 59 drivers/fsi/fsi-master.h uint32_t addr, const void *val, size_t size); val 357 drivers/fsi/fsi-scom.c uint64_t val; val 367 drivers/fsi/fsi-scom.c rc = get_scom(scom, &val, *offset); val 374 drivers/fsi/fsi-scom.c rc = copy_to_user(buf, &val, len); val 387 drivers/fsi/fsi-scom.c uint64_t val; val 392 drivers/fsi/fsi-scom.c rc = copy_from_user(&val, buf, len); val 402 drivers/fsi/fsi-scom.c rc = put_scom(scom, val, *offset); val 55 drivers/gpio/gpio-74x164.c unsigned offset, int val) val 62 drivers/gpio/gpio-74x164.c if (val) val 95 drivers/gpio/gpio-74x164.c unsigned offset, int val) val 97 drivers/gpio/gpio-74x164.c gen_74x164_set_value(gc, offset, val); val 90 drivers/gpio/gpio-74xx-mmio.c static int mmio_74xx_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 95 drivers/gpio/gpio-74xx-mmio.c gc->set(gc, gpio, val); val 85 drivers/gpio/gpio-adnp.c u8 val; val 87 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); val 92 drivers/gpio/gpio-adnp.c val |= BIT(pos); val 94 drivers/gpio/gpio-adnp.c val &= ~BIT(pos); val 96 drivers/gpio/gpio-adnp.c adnp_write(adnp, GPIO_PLR(adnp) + reg, val); val 151 drivers/gpio/gpio-adnp.c u8 val; val 155 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); val 159 drivers/gpio/gpio-adnp.c val |= BIT(pos); val 161 drivers/gpio/gpio-adnp.c err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); val 165 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); val 169 drivers/gpio/gpio-adnp.c if (!(val & BIT(pos))) { val 44 drivers/gpio/gpio-adp5520.c unsigned off, int val) val 49 drivers/gpio/gpio-adp5520.c if (val) val 67 drivers/gpio/gpio-adp5520.c unsigned off, int val) val 75 drivers/gpio/gpio-adp5520.c if (val) val 55 drivers/gpio/gpio-adp5588.c static int adp5588_gpio_write(struct i2c_client *client, u8 reg, u8 val) val 57 drivers/gpio/gpio-adp5588.c int ret = i2c_smbus_write_byte_data(client, reg, val); val 70 drivers/gpio/gpio-adp5588.c int val; val 75 drivers/gpio/gpio-adp5588.c val = dev->dat_out[bank]; val 77 drivers/gpio/gpio-adp5588.c val = adp5588_gpio_read(dev->client, GPIO_DAT_STAT1 + bank); val 81 drivers/gpio/gpio-adp5588.c return !!(val & bit); val 85 drivers/gpio/gpio-adp5588.c unsigned off, int val) val 94 drivers/gpio/gpio-adp5588.c if (val) val 121 drivers/gpio/gpio-adp5588.c unsigned off, int val) val 133 drivers/gpio/gpio-adp5588.c if (val) val 27 drivers/gpio/gpio-altera-a10sr.c int ret, val; val 29 drivers/gpio/gpio-altera-a10sr.c ret = regmap_read(gpio->regmap, ALTR_A10SR_PBDSW_REG, &val); val 33 drivers/gpio/gpio-altera-a10sr.c return !!(val & BIT(offset - ALTR_A10SR_LED_VALID_SHIFT)); val 67 drivers/gpio/gpio-amd-fch.c u32 val; val 71 drivers/gpio/gpio-amd-fch.c val = readl_relaxed(ptr); val 73 drivers/gpio/gpio-amd-fch.c val |= AMD_FCH_GPIO_FLAG_WRITE; val 75 drivers/gpio/gpio-amd-fch.c val &= ~AMD_FCH_GPIO_FLAG_WRITE; val 77 drivers/gpio/gpio-amd-fch.c writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr); val 54 drivers/gpio/gpio-arizona.c unsigned int reg, val; val 58 drivers/gpio/gpio-arizona.c ret = regmap_read(arizona->regmap, reg, &val); val 63 drivers/gpio/gpio-arizona.c if (val & ARIZONA_GPN_DIR) { val 78 drivers/gpio/gpio-arizona.c ret = regmap_read(arizona->regmap, reg, &val); val 86 drivers/gpio/gpio-arizona.c if (val & ARIZONA_GPN_LVL) val 98 drivers/gpio/gpio-arizona.c unsigned int val; val 101 drivers/gpio/gpio-arizona.c ret = regmap_read(arizona->regmap, ARIZONA_GPIO1_CTRL + offset, &val); val 105 drivers/gpio/gpio-arizona.c if ((val & ARIZONA_GPN_DIR) && persistent) { val 390 drivers/gpio/gpio-aspeed.c int val) val 400 drivers/gpio/gpio-aspeed.c if (val) val 410 drivers/gpio/gpio-aspeed.c int val) val 419 drivers/gpio/gpio-aspeed.c __aspeed_gpio_set(gc, offset, val); val 454 drivers/gpio/gpio-aspeed.c unsigned int offset, int val) val 472 drivers/gpio/gpio-aspeed.c __aspeed_gpio_set(gc, offset, val); val 487 drivers/gpio/gpio-aspeed.c u32 val; val 497 drivers/gpio/gpio-aspeed.c val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); val 501 drivers/gpio/gpio-aspeed.c return !val; val 719 drivers/gpio/gpio-aspeed.c u32 val; val 726 drivers/gpio/gpio-aspeed.c val = readl(treg); val 729 drivers/gpio/gpio-aspeed.c val |= GPIO_BIT(offset); val 731 drivers/gpio/gpio-aspeed.c val &= ~GPIO_BIT(offset); val 733 drivers/gpio/gpio-aspeed.c writel(val, treg); val 830 drivers/gpio/gpio-aspeed.c u32 val; val 836 drivers/gpio/gpio-aspeed.c val = ioread32(addr); val 837 drivers/gpio/gpio-aspeed.c iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); val 840 drivers/gpio/gpio-aspeed.c val = ioread32(addr); val 841 drivers/gpio/gpio-aspeed.c iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); val 49 drivers/gpio/gpio-ath79.c unsigned reg, u32 val) val 51 drivers/gpio/gpio-ath79.c writel(val, ctrl->base + reg); val 94 drivers/gpio/gpio-bcm-kona.c u32 val; val 100 drivers/gpio/gpio-bcm-kona.c val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); val 101 drivers/gpio/gpio-bcm-kona.c val |= BIT(gpio); val 102 drivers/gpio/gpio-bcm-kona.c bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); val 110 drivers/gpio/gpio-bcm-kona.c u32 val; val 116 drivers/gpio/gpio-bcm-kona.c val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); val 117 drivers/gpio/gpio-bcm-kona.c val &= ~BIT(gpio); val 118 drivers/gpio/gpio-bcm-kona.c bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); val 127 drivers/gpio/gpio-bcm-kona.c u32 val; val 129 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; val 130 drivers/gpio/gpio-bcm-kona.c return !!val; val 139 drivers/gpio/gpio-bcm-kona.c u32 val, reg_offset; val 152 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); val 153 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); val 154 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + reg_offset); val 166 drivers/gpio/gpio-bcm-kona.c u32 val, reg_offset; val 179 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); val 184 drivers/gpio/gpio-bcm-kona.c return !!(val & BIT(bit)); val 206 drivers/gpio/gpio-bcm-kona.c u32 val; val 213 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)); val 214 drivers/gpio/gpio-bcm-kona.c val &= ~GPIO_GPCTR0_IOTR_MASK; val 215 drivers/gpio/gpio-bcm-kona.c val |= GPIO_GPCTR0_IOTR_CMD_INPUT; val 216 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_CONTROL(gpio)); val 230 drivers/gpio/gpio-bcm-kona.c u32 val, reg_offset; val 237 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)); val 238 drivers/gpio/gpio-bcm-kona.c val &= ~GPIO_GPCTR0_IOTR_MASK; val 239 drivers/gpio/gpio-bcm-kona.c val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; val 240 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_CONTROL(gpio)); val 243 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); val 244 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); val 245 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + reg_offset); val 267 drivers/gpio/gpio-bcm-kona.c u32 val, res; val 293 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)); val 294 drivers/gpio/gpio-bcm-kona.c val &= ~GPIO_GPCTR0_DBR_MASK; val 298 drivers/gpio/gpio-bcm-kona.c val &= ~GPIO_GPCTR0_DB_ENABLE_MASK; val 300 drivers/gpio/gpio-bcm-kona.c val |= GPIO_GPCTR0_DB_ENABLE_MASK | val 304 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_CONTROL(gpio)); val 345 drivers/gpio/gpio-bcm-kona.c u32 val; val 352 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_INT_STATUS(bank_id)); val 353 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); val 354 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_INT_STATUS(bank_id)); val 366 drivers/gpio/gpio-bcm-kona.c u32 val; val 373 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_INT_MASK(bank_id)); val 374 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); val 375 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_INT_MASK(bank_id)); val 388 drivers/gpio/gpio-bcm-kona.c u32 val; val 395 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_INT_MSKCLR(bank_id)); val 396 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); val 397 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); val 409 drivers/gpio/gpio-bcm-kona.c u32 val; val 438 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)); val 439 drivers/gpio/gpio-bcm-kona.c val &= ~GPIO_GPCTR0_ITR_MASK; val 440 drivers/gpio/gpio-bcm-kona.c val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT; val 441 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_CONTROL(gpio)); val 22 drivers/gpio/gpio-bd70528.c u8 val; val 26 drivers/gpio/gpio-bd70528.c val = BD70528_DEBOUNCE_DISABLE; val 29 drivers/gpio/gpio-bd70528.c val = BD70528_DEBOUNCE_15MS; val 32 drivers/gpio/gpio-bd70528.c val = BD70528_DEBOUNCE_30MS; val 35 drivers/gpio/gpio-bd70528.c val = BD70528_DEBOUNCE_50MS; val 43 drivers/gpio/gpio-bd70528.c BD70528_DEBOUNCE_MASK, val); val 49 drivers/gpio/gpio-bd70528.c int val, ret; val 52 drivers/gpio/gpio-bd70528.c ret = regmap_read(bdgpio->chip.regmap, GPIO_OUT_REG(offset), &val); val 58 drivers/gpio/gpio-bd70528.c return !(val & BD70528_GPIO_OUT_EN_MASK); val 104 drivers/gpio/gpio-bd70528.c u8 val = (value) ? BD70528_GPIO_OUT_HI : BD70528_GPIO_OUT_LO; val 107 drivers/gpio/gpio-bd70528.c BD70528_GPIO_OUT_MASK, val); val 128 drivers/gpio/gpio-bd70528.c unsigned int val; val 130 drivers/gpio/gpio-bd70528.c ret = regmap_read(bdgpio->chip.regmap, GPIO_OUT_REG(offset), &val); val 132 drivers/gpio/gpio-bd70528.c ret = !!(val & BD70528_GPIO_OUT_MASK); val 141 drivers/gpio/gpio-bd70528.c unsigned int val; val 144 drivers/gpio/gpio-bd70528.c ret = regmap_read(bdgpio->chip.regmap, BD70528_REG_GPIO_STATE, &val); val 147 drivers/gpio/gpio-bd70528.c ret = !(val & GPIO_IN_STATE_MASK(offset)); val 35 drivers/gpio/gpio-bd9571mwv.c int ret, val; val 37 drivers/gpio/gpio-bd9571mwv.c ret = regmap_read(gpio->bd->regmap, BD9571MWV_GPIO_DIR, &val); val 41 drivers/gpio/gpio-bd9571mwv.c return val & BIT(offset); val 72 drivers/gpio/gpio-bd9571mwv.c int ret, val; val 74 drivers/gpio/gpio-bd9571mwv.c ret = regmap_read(gpio->bd->regmap, BD9571MWV_GPIO_IN, &val); val 78 drivers/gpio/gpio-bd9571mwv.c return val & BIT(offset); val 94 drivers/gpio/gpio-bt8xx.c u32 val; val 97 drivers/gpio/gpio-bt8xx.c val = bgread(BT848_GPIO_DATA); val 100 drivers/gpio/gpio-bt8xx.c return !!(val & (1 << nr)); val 104 drivers/gpio/gpio-bt8xx.c unsigned nr, int val) val 117 drivers/gpio/gpio-bt8xx.c if (val) val 129 drivers/gpio/gpio-bt8xx.c unsigned nr, int val) val 138 drivers/gpio/gpio-bt8xx.c if (val) val 30 drivers/gpio/gpio-creg-snps.c static void creg_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) val 38 drivers/gpio/gpio-creg-snps.c value = val ? hcg->layout->on[offset] : hcg->layout->off[offset]; val 52 drivers/gpio/gpio-creg-snps.c static int creg_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val) val 54 drivers/gpio/gpio-creg-snps.c creg_gpio_set(gc, offset, val); val 158 drivers/gpio/gpio-crystalcove.c unsigned int val; val 164 drivers/gpio/gpio-crystalcove.c ret = regmap_read(cg->regmap, reg, &val); val 168 drivers/gpio/gpio-crystalcove.c return val & 0x1; val 60 drivers/gpio/gpio-cs5535.c static void errata_outl(struct cs5535_gpio_chip *chip, u32 val, val 75 drivers/gpio/gpio-cs5535.c if (val & 0xffff) val 76 drivers/gpio/gpio-cs5535.c val |= (inl(addr) & 0xffff); /* ignore the high bits */ val 78 drivers/gpio/gpio-cs5535.c val |= (inl(addr) ^ (val >> 16)); val 80 drivers/gpio/gpio-cs5535.c outl(val, addr); val 131 drivers/gpio/gpio-cs5535.c long val; val 136 drivers/gpio/gpio-cs5535.c val = inl(chip->base + reg); val 139 drivers/gpio/gpio-cs5535.c val = inl(chip->base + 0x80 + reg); val 144 drivers/gpio/gpio-cs5535.c return (val & (1 << offset)) ? 1 : 0; val 170 drivers/gpio/gpio-cs5535.c uint32_t val; val 182 drivers/gpio/gpio-cs5535.c val = inl(chip->base + offset); val 185 drivers/gpio/gpio-cs5535.c val &= ~(0xF << shift); val 188 drivers/gpio/gpio-cs5535.c val |= ((pair & 7) << shift); val 192 drivers/gpio/gpio-cs5535.c val |= (1 << (shift + 3)); val 194 drivers/gpio/gpio-cs5535.c outl(val, chip->base + offset); val 235 drivers/gpio/gpio-cs5535.c static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val) val 237 drivers/gpio/gpio-cs5535.c if (val) val 256 drivers/gpio/gpio-cs5535.c static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val) val 265 drivers/gpio/gpio-cs5535.c if (val) val 162 drivers/gpio/gpio-davinci.c u32 val; val 171 drivers/gpio/gpio-davinci.c ret = of_property_read_u32(dn, "ti,ngpio", &val); val 175 drivers/gpio/gpio-davinci.c pdata->ngpio = val; val 177 drivers/gpio/gpio-davinci.c ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); val 181 drivers/gpio/gpio-davinci.c pdata->gpio_unbanked = val; val 138 drivers/gpio/gpio-dwapb.c u32 val) val 143 drivers/gpio/gpio-dwapb.c gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); val 173 drivers/gpio/gpio-dwapb.c int val; val 181 drivers/gpio/gpio-dwapb.c val = gc->get(gc, offs % 32); val 182 drivers/gpio/gpio-dwapb.c if (val) val 227 drivers/gpio/gpio-dwapb.c u32 val; val 230 drivers/gpio/gpio-dwapb.c val = dwapb_read(gpio, GPIO_INTEN); val 231 drivers/gpio/gpio-dwapb.c val |= BIT(d->hwirq); val 232 drivers/gpio/gpio-dwapb.c dwapb_write(gpio, GPIO_INTEN, val); val 242 drivers/gpio/gpio-dwapb.c u32 val; val 245 drivers/gpio/gpio-dwapb.c val = dwapb_read(gpio, GPIO_INTEN); val 246 drivers/gpio/gpio-dwapb.c val &= ~BIT(d->hwirq); val 247 drivers/gpio/gpio-dwapb.c dwapb_write(gpio, GPIO_INTEN, val); val 141 drivers/gpio/gpio-eic-sprd.c u16 reg, unsigned int val) val 152 drivers/gpio/gpio-eic-sprd.c if (val) val 34 drivers/gpio/gpio-exar.c static void exar_update(struct gpio_chip *chip, unsigned int reg, int val, val 43 drivers/gpio/gpio-exar.c if (val) val 82 drivers/gpio/gpio-f7188x.c int val; val 85 drivers/gpio/gpio-f7188x.c val = inb(base + 1) << 8; val 87 drivers/gpio/gpio-f7188x.c val |= inb(base + 1); val 89 drivers/gpio/gpio-f7188x.c return val; val 92 drivers/gpio/gpio-f7188x.c static inline void superio_outb(int base, int reg, int val) val 95 drivers/gpio/gpio-f7188x.c outb(val, base + 1); val 68 drivers/gpio/gpio-ftgpio010.c u32 val; val 70 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_INT_EN); val 71 drivers/gpio/gpio-ftgpio010.c val &= ~BIT(irqd_to_hwirq(d)); val 72 drivers/gpio/gpio-ftgpio010.c writel(val, g->base + GPIO_INT_EN); val 79 drivers/gpio/gpio-ftgpio010.c u32 val; val 81 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_INT_EN); val 82 drivers/gpio/gpio-ftgpio010.c val |= BIT(irqd_to_hwirq(d)); val 83 drivers/gpio/gpio-ftgpio010.c writel(val, g->base + GPIO_INT_EN); val 166 drivers/gpio/gpio-ftgpio010.c u32 val; val 192 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_DEBOUNCE_PRESCALE); val 193 drivers/gpio/gpio-ftgpio010.c if (val == deb_div) { val 201 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_DEBOUNCE_EN); val 202 drivers/gpio/gpio-ftgpio010.c val |= BIT(offset); val 203 drivers/gpio/gpio-ftgpio010.c writel(val, g->base + GPIO_DEBOUNCE_EN); val 207 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_DEBOUNCE_EN); val 208 drivers/gpio/gpio-ftgpio010.c if (val) { val 219 drivers/gpio/gpio-ftgpio010.c val |= BIT(offset); val 220 drivers/gpio/gpio-ftgpio010.c writel(val, g->base + GPIO_DEBOUNCE_EN); val 91 drivers/gpio/gpio-grgpio.c int val) val 95 drivers/gpio/gpio-grgpio.c if (val) val 46 drivers/gpio/gpio-gw-pld.c s32 val; val 48 drivers/gpio/gpio-gw-pld.c val = i2c_smbus_read_byte(gw->client); val 50 drivers/gpio/gpio-gw-pld.c return (val < 0) ? 0 : !!(val & BIT(offset)); val 56 drivers/gpio/gpio-ich.c #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) val 103 drivers/gpio/gpio-ich.c static int ichx_write_bit(int reg, unsigned nr, int val, int verify) val 118 drivers/gpio/gpio-ich.c if (val) val 175 drivers/gpio/gpio-ich.c int val) val 182 drivers/gpio/gpio-ich.c ichx_write_bit(GPIO_LVL, nr, val, 0); val 254 drivers/gpio/gpio-ich.c static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val) val 256 drivers/gpio/gpio-ich.c ichx_write_bit(GPIO_LVL, nr, val, 0); val 111 drivers/gpio/gpio-it87.c static inline void superio_outb(int val, int reg) val 114 drivers/gpio/gpio-it87.c outb(val, VAL); val 119 drivers/gpio/gpio-it87.c int val; val 122 drivers/gpio/gpio-it87.c val = inb(VAL) << 8; val 124 drivers/gpio/gpio-it87.c val |= inb(VAL); val 125 drivers/gpio/gpio-it87.c return val; val 128 drivers/gpio/gpio-it87.c static inline void superio_outw(int val, int reg) val 131 drivers/gpio/gpio-it87.c outb(val >> 8, VAL); val 133 drivers/gpio/gpio-it87.c outb(val, VAL); val 225 drivers/gpio/gpio-it87.c unsigned gpio_num, int val) val 235 drivers/gpio/gpio-it87.c if (val) val 242 drivers/gpio/gpio-it87.c unsigned gpio_num, int val) val 260 drivers/gpio/gpio-it87.c it87_gpio_set(chip, gpio_num, val); val 90 drivers/gpio/gpio-ixp4xx.c u32 val; val 134 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + int_reg); val 135 drivers/gpio/gpio-ixp4xx.c val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); val 136 drivers/gpio/gpio-ixp4xx.c __raw_writel(val, g->base + int_reg); val 141 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + int_reg); val 142 drivers/gpio/gpio-ixp4xx.c val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); val 143 drivers/gpio/gpio-ixp4xx.c __raw_writel(val, g->base + int_reg); val 146 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + IXP4XX_REG_GPOE); val 147 drivers/gpio/gpio-ixp4xx.c val |= BIT(d->hwirq); val 148 drivers/gpio/gpio-ixp4xx.c __raw_writel(val, g->base + IXP4XX_REG_GPOE); val 108 drivers/gpio/gpio-janz-ttl.c static void ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val) val 111 drivers/gpio/gpio-janz-ttl.c iowrite16be(val, &mod->regs->control); val 35 drivers/gpio/gpio-kempld.c u8 reg, u8 bit, u8 val) val 40 drivers/gpio/gpio-kempld.c if (val) val 42 drivers/gpio/gpio-loongson.c u32 val; val 45 drivers/gpio/gpio-loongson.c val = LOONGSON_GPIODATA; val 48 drivers/gpio/gpio-loongson.c return !!(val & BIT(gpio + LOONGSON_GPIO_IN_OFFSET)); val 54 drivers/gpio/gpio-loongson.c u32 val; val 57 drivers/gpio/gpio-loongson.c val = LOONGSON_GPIODATA; val 59 drivers/gpio/gpio-loongson.c val |= BIT(gpio); val 61 drivers/gpio/gpio-loongson.c val &= ~BIT(gpio); val 62 drivers/gpio/gpio-loongson.c LOONGSON_GPIODATA = val; val 66 drivers/gpio/gpio-lp3943.c u8 val) val 72 drivers/gpio/gpio-lp3943.c val << mux[offset].shift); val 60 drivers/gpio/gpio-lp873x.c int ret, val; val 62 drivers/gpio/gpio-lp873x.c ret = regmap_read(gpio->lp873->regmap, LP873X_REG_GPO_CTRL, &val); val 66 drivers/gpio/gpio-lp873x.c return val & BIT(offset * BITS_PER_GPO); val 32 drivers/gpio/gpio-lp87565.c int ret, val; val 34 drivers/gpio/gpio-lp87565.c ret = regmap_read(gpio->map, LP87565_REG_GPIO_IN, &val); val 38 drivers/gpio/gpio-lp87565.c return !!(val & BIT(offset)); val 54 drivers/gpio/gpio-lp87565.c int ret, val; val 56 drivers/gpio/gpio-lp87565.c ret = regmap_read(gpio->map, LP87565_REG_GPIO_CONFIG, &val); val 60 drivers/gpio/gpio-lp87565.c return !(val & BIT(offset)); val 59 drivers/gpio/gpio-lpc18xx.c u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL); val 62 drivers/gpio/gpio-lpc18xx.c val &= ~BIT(pin); val 64 drivers/gpio/gpio-lpc18xx.c val |= BIT(pin); val 66 drivers/gpio/gpio-lpc18xx.c writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL); val 173 drivers/gpio/gpio-lpc32xx.c static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset) val 175 drivers/gpio/gpio-lpc32xx.c __raw_writel(val, group->reg_base + offset); val 29 drivers/gpio/gpio-madera.c unsigned int val; val 33 drivers/gpio/gpio-madera.c &val); val 37 drivers/gpio/gpio-madera.c return !!(val & MADERA_GP1_DIR_MASK); val 56 drivers/gpio/gpio-madera.c unsigned int val; val 60 drivers/gpio/gpio-madera.c &val); val 64 drivers/gpio/gpio-madera.c return !!(val & MADERA_GP1_LVL_MASK); val 127 drivers/gpio/gpio-max3191x.c int val, i, ot = 0, uv1 = 0; val 129 drivers/gpio/gpio-max3191x.c val = spi_sync(spi, &max3191x->mesg); val 130 drivers/gpio/gpio-max3191x.c if (val) { val 131 drivers/gpio/gpio-max3191x.c dev_err_ratelimited(dev, "SPI receive error %d\n", val); val 132 drivers/gpio/gpio-max3191x.c return val; val 140 drivers/gpio/gpio-max3191x.c val = (status & 0xf8) != crc8(max3191x_crc8, &in, 1, 0); val 141 drivers/gpio/gpio-max3191x.c __assign_bit(i, max3191x->crc_error, val); val 142 drivers/gpio/gpio-max3191x.c if (val) val 159 drivers/gpio/gpio-max3191x.c val = !(status & 1); val 160 drivers/gpio/gpio-max3191x.c __assign_bit(i, max3191x->undervolt2, val); val 161 drivers/gpio/gpio-max3191x.c if (val && !uv1) val 174 drivers/gpio/gpio-max3191x.c val = gpiod_get_value_cansleep(fault_pin); val 175 drivers/gpio/gpio-max3191x.c if (val < 0) { val 177 drivers/gpio/gpio-max3191x.c "GPIO read error %d\n", val); val 178 drivers/gpio/gpio-max3191x.c return val; val 180 drivers/gpio/gpio-max3191x.c __assign_bit(i, max3191x->fault, val); val 181 drivers/gpio/gpio-max3191x.c if (val && !uv1 && !ot) val 17 drivers/gpio/gpio-max7300.c unsigned int val) val 21 drivers/gpio/gpio-max7300.c return i2c_smbus_write_byte_data(client, reg, val); val 20 drivers/gpio/gpio-max7301.c unsigned int val) val 23 drivers/gpio/gpio-max7301.c u16 word = ((reg & 0x7F) << 8) | (val & 0xFF); val 158 drivers/gpio/gpio-max732x.c static int max732x_writeb(struct max732x_chip *chip, int group_a, uint8_t val) val 164 drivers/gpio/gpio-max732x.c ret = i2c_smbus_write_byte(client, val); val 173 drivers/gpio/gpio-max732x.c static int max732x_readb(struct max732x_chip *chip, int group_a, uint8_t *val) val 185 drivers/gpio/gpio-max732x.c *val = (uint8_t)ret; val 208 drivers/gpio/gpio-max732x.c int val) val 217 drivers/gpio/gpio-max732x.c reg_out = (reg_out & ~mask) | (val & mask); val 232 drivers/gpio/gpio-max732x.c static void max732x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) val 237 drivers/gpio/gpio-max732x.c max732x_gpio_set_mask(gc, base, mask, val << (off & 0x7)); val 274 drivers/gpio/gpio-max732x.c unsigned off, int val) val 285 drivers/gpio/gpio-max732x.c max732x_gpio_set_value(gc, off, val); val 290 drivers/gpio/gpio-max732x.c static int max732x_writew(struct max732x_chip *chip, uint16_t val) val 294 drivers/gpio/gpio-max732x.c val = cpu_to_le16(val); val 296 drivers/gpio/gpio-max732x.c ret = i2c_master_send(chip->client_group_a, (char *)&val, 2); val 305 drivers/gpio/gpio-max732x.c static int max732x_readw(struct max732x_chip *chip, uint16_t *val) val 309 drivers/gpio/gpio-max732x.c ret = i2c_master_recv(chip->client_group_a, (char *)val, 2); val 315 drivers/gpio/gpio-max732x.c *val = le16_to_cpu(*val); val 143 drivers/gpio/gpio-max77620.c unsigned int val; val 146 drivers/gpio/gpio-max77620.c ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val); val 152 drivers/gpio/gpio-max77620.c if (val & MAX77620_CNFG_GPIO_DIR_MASK) val 153 drivers/gpio/gpio-max77620.c return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK); val 155 drivers/gpio/gpio-max77620.c return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK); val 162 drivers/gpio/gpio-max77620.c u8 val; val 165 drivers/gpio/gpio-max77620.c val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH : val 169 drivers/gpio/gpio-max77620.c MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val); val 188 drivers/gpio/gpio-max77620.c u8 val; val 193 drivers/gpio/gpio-max77620.c val = MAX77620_CNFG_GPIO_DBNC_None; val 196 drivers/gpio/gpio-max77620.c val = MAX77620_CNFG_GPIO_DBNC_8ms; val 199 drivers/gpio/gpio-max77620.c val = MAX77620_CNFG_GPIO_DBNC_16ms; val 202 drivers/gpio/gpio-max77620.c val = MAX77620_CNFG_GPIO_DBNC_32ms; val 210 drivers/gpio/gpio-max77620.c MAX77620_CNFG_GPIO_DBNC_MASK, val); val 221 drivers/gpio/gpio-max77620.c u8 val; val 224 drivers/gpio/gpio-max77620.c val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH : val 228 drivers/gpio/gpio-max77620.c MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val); val 83 drivers/gpio/gpio-max77650.c unsigned int val; val 86 drivers/gpio/gpio-max77650.c rv = regmap_read(chip->map, MAX77650_REG_CNFG_GPIO, &val); val 90 drivers/gpio/gpio-max77650.c return MAX77650_GPIO_INVAL_BITS(val); val 97 drivers/gpio/gpio-max77650.c unsigned int val; val 100 drivers/gpio/gpio-max77650.c rv = regmap_read(chip->map, MAX77650_REG_CNFG_GPIO, &val); val 104 drivers/gpio/gpio-max77650.c return MAX77650_GPIO_DIR_BITS(val); val 47 drivers/gpio/gpio-mb86s7x.c u32 val; val 51 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + PFR(gpio)); val 52 drivers/gpio/gpio-mb86s7x.c val &= ~OFFSET(gpio); val 53 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + PFR(gpio)); val 64 drivers/gpio/gpio-mb86s7x.c u32 val; val 68 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + PFR(gpio)); val 69 drivers/gpio/gpio-mb86s7x.c val |= OFFSET(gpio); val 70 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + PFR(gpio)); val 79 drivers/gpio/gpio-mb86s7x.c unsigned char val; val 83 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + DDR(gpio)); val 84 drivers/gpio/gpio-mb86s7x.c val &= ~OFFSET(gpio); val 85 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + DDR(gpio)); val 97 drivers/gpio/gpio-mb86s7x.c unsigned char val; val 101 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + PDR(gpio)); val 103 drivers/gpio/gpio-mb86s7x.c val |= OFFSET(gpio); val 105 drivers/gpio/gpio-mb86s7x.c val &= ~OFFSET(gpio); val 106 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + PDR(gpio)); val 108 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + DDR(gpio)); val 109 drivers/gpio/gpio-mb86s7x.c val |= OFFSET(gpio); val 110 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + DDR(gpio)); val 128 drivers/gpio/gpio-mb86s7x.c unsigned char val; val 132 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + PDR(gpio)); val 134 drivers/gpio/gpio-mb86s7x.c val |= OFFSET(gpio); val 136 drivers/gpio/gpio-mb86s7x.c val &= ~OFFSET(gpio); val 137 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + PDR(gpio)); val 41 drivers/gpio/gpio-mc9s08dz60.c static int mc9s08dz60_set(struct mc9s08dz60 *mc9s, unsigned offset, int val) val 49 drivers/gpio/gpio-mc9s08dz60.c if (val) val 61 drivers/gpio/gpio-mc9s08dz60.c static void mc9s08dz60_set_value(struct gpio_chip *gc, unsigned offset, int val) val 65 drivers/gpio/gpio-mc9s08dz60.c mc9s08dz60_set(mc9s, offset, val); val 69 drivers/gpio/gpio-mc9s08dz60.c unsigned offset, int val) val 73 drivers/gpio/gpio-mc9s08dz60.c return mc9s08dz60_set(mc9s, offset, val); val 92 drivers/gpio/gpio-ml-ioh.c static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) val 100 drivers/gpio/gpio-ml-ioh.c if (val) val 117 drivers/gpio/gpio-ml-ioh.c int val) val 131 drivers/gpio/gpio-ml-ioh.c if (val) val 243 drivers/gpio/gpio-ml-ioh.c u32 val; val 263 drivers/gpio/gpio-ml-ioh.c val = IOH_EDGE_RISING; val 266 drivers/gpio/gpio-ml-ioh.c val = IOH_EDGE_FALLING; val 269 drivers/gpio/gpio-ml-ioh.c val = IOH_EDGE_BOTH; val 272 drivers/gpio/gpio-ml-ioh.c val = IOH_LEVEL_H; val 275 drivers/gpio/gpio-ml-ioh.c val = IOH_LEVEL_L; val 287 drivers/gpio/gpio-ml-ioh.c iowrite32(im | (val << (im_pos * 4)), im_reg); val 191 drivers/gpio/gpio-mmio.c unsigned long val; val 203 drivers/gpio/gpio-mmio.c val = gc->read_reg(gc->reg_dat) & readmask; val 210 drivers/gpio/gpio-mmio.c while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio) val 216 drivers/gpio/gpio-mmio.c static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) val 220 drivers/gpio/gpio-mmio.c static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 227 drivers/gpio/gpio-mmio.c if (val) val 238 drivers/gpio/gpio-mmio.c int val) val 242 drivers/gpio/gpio-mmio.c if (val) val 248 drivers/gpio/gpio-mmio.c static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) val 255 drivers/gpio/gpio-mmio.c if (val) val 339 drivers/gpio/gpio-mmio.c int val) val 345 drivers/gpio/gpio-mmio.c int val) val 347 drivers/gpio/gpio-mmio.c gc->set(gc, gpio, val); val 384 drivers/gpio/gpio-mmio.c static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 388 drivers/gpio/gpio-mmio.c gc->set(gc, gpio, val); val 96 drivers/gpio/gpio-mockup.c int val; val 99 drivers/gpio/gpio-mockup.c val = __gpio_mockup_get(chip, offset); val 102 drivers/gpio/gpio-mockup.c return val; val 109 drivers/gpio/gpio-mockup.c unsigned int bit, val; val 113 drivers/gpio/gpio-mockup.c val = __gpio_mockup_get(chip, bit); val 114 drivers/gpio/gpio-mockup.c __assign_bit(bit, bits, val); val 207 drivers/gpio/gpio-mockup.c int val, cnt; val 218 drivers/gpio/gpio-mockup.c val = gpio_mockup_get(gc, priv->offset); val 219 drivers/gpio/gpio-mockup.c cnt = snprintf(buf, sizeof(buf), "%d\n", val); val 229 drivers/gpio/gpio-mockup.c int rv, val, curr, irq, irq_type; val 239 drivers/gpio/gpio-mockup.c rv = kstrtoint_from_user(usr_buf, size, 0, &val); val 242 drivers/gpio/gpio-mockup.c if (val != 0 && val != 1) val 257 drivers/gpio/gpio-mockup.c if (curr == val) val 263 drivers/gpio/gpio-mockup.c if ((val == 1 && (irq_type & IRQ_TYPE_EDGE_RISING)) || val 264 drivers/gpio/gpio-mockup.c (val == 0 && (irq_type & IRQ_TYPE_EDGE_FALLING))) val 271 drivers/gpio/gpio-mockup.c __gpio_mockup_set(chip, priv->offset, val); val 274 drivers/gpio/gpio-mockup.c chip->lines[priv->offset].pull = val; val 56 drivers/gpio/gpio-moxtet.c int val) val 67 drivers/gpio/gpio-moxtet.c if (val) val 102 drivers/gpio/gpio-moxtet.c unsigned int offset, int val) val 107 drivers/gpio/gpio-moxtet.c moxtet_gpio_set_value(gc, offset, val); val 58 drivers/gpio/gpio-mpc5200.c __mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 64 drivers/gpio/gpio-mpc5200.c if (val) val 73 drivers/gpio/gpio-mpc5200.c mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 79 drivers/gpio/gpio-mpc5200.c __mpc52xx_wkup_gpio_set(gc, gpio, val); val 83 drivers/gpio/gpio-mpc5200.c pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); val 109 drivers/gpio/gpio-mpc5200.c mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 118 drivers/gpio/gpio-mpc5200.c __mpc52xx_wkup_gpio_set(gc, gpio, val); val 130 drivers/gpio/gpio-mpc5200.c pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); val 220 drivers/gpio/gpio-mpc5200.c __mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 226 drivers/gpio/gpio-mpc5200.c if (val) val 234 drivers/gpio/gpio-mpc5200.c mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 240 drivers/gpio/gpio-mpc5200.c __mpc52xx_simple_gpio_set(gc, gpio, val); val 244 drivers/gpio/gpio-mpc5200.c pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); val 270 drivers/gpio/gpio-mpc5200.c mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 280 drivers/gpio/gpio-mpc5200.c __mpc52xx_simple_gpio_set(gc, gpio, val); val 292 drivers/gpio/gpio-mpc5200.c pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); val 87 drivers/gpio/gpio-mpc8xxx.c u32 val; val 92 drivers/gpio/gpio-mpc8xxx.c val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; val 95 drivers/gpio/gpio-mpc8xxx.c return !!((val | out_shadow) & mpc_pin2mask(gpio)); val 99 drivers/gpio/gpio-mpc8xxx.c unsigned int gpio, int val) val 106 drivers/gpio/gpio-mpc8xxx.c return mpc8xxx_gc->direction_output(gc, gpio, val); val 110 drivers/gpio/gpio-mpc8xxx.c unsigned int gpio, int val) val 117 drivers/gpio/gpio-mpc8xxx.c return mpc8xxx_gc->direction_output(gc, gpio, val); val 67 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) val 73 drivers/gpio/gpio-mt7621.c gc->write_reg(mtk->base + offset, val); val 164 drivers/gpio/gpio-mvebu.c u32 val; val 167 drivers/gpio/gpio-mvebu.c regmap_read(map, offset, &val); val 169 drivers/gpio/gpio-mvebu.c return val; val 173 drivers/gpio/gpio-mvebu.c mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) val 179 drivers/gpio/gpio-mvebu.c regmap_write(map, offset, val); val 214 drivers/gpio/gpio-mvebu.c u32 val; val 217 drivers/gpio/gpio-mvebu.c regmap_read(map, offset, &val); val 219 drivers/gpio/gpio-mvebu.c return val; val 223 drivers/gpio/gpio-mvebu.c mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) val 229 drivers/gpio/gpio-mvebu.c regmap_write(map, offset, val); val 264 drivers/gpio/gpio-mvebu.c u32 val; val 267 drivers/gpio/gpio-mvebu.c regmap_read(map, offset, &val); val 269 drivers/gpio/gpio-mvebu.c return val; val 273 drivers/gpio/gpio-mvebu.c mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) val 279 drivers/gpio/gpio-mvebu.c regmap_write(map, offset, val); val 529 drivers/gpio/gpio-mvebu.c u32 data_in, in_pol, val; val 540 drivers/gpio/gpio-mvebu.c val = BIT(pin); /* falling */ val 542 drivers/gpio/gpio-mvebu.c val = 0; /* raising */ val 546 drivers/gpio/gpio-mvebu.c BIT(pin), val); val 654 drivers/gpio/gpio-mvebu.c unsigned long long val; val 660 drivers/gpio/gpio-mvebu.c val = (unsigned long long) val 662 drivers/gpio/gpio-mvebu.c val *= NSEC_PER_SEC; val 663 drivers/gpio/gpio-mvebu.c do_div(val, mvpwm->clk_rate); val 664 drivers/gpio/gpio-mvebu.c if (val > UINT_MAX) val 666 drivers/gpio/gpio-mvebu.c else if (val) val 667 drivers/gpio/gpio-mvebu.c state->duty_cycle = val; val 671 drivers/gpio/gpio-mvebu.c val = (unsigned long long) val 673 drivers/gpio/gpio-mvebu.c val *= NSEC_PER_SEC; val 674 drivers/gpio/gpio-mvebu.c do_div(val, mvpwm->clk_rate); val 675 drivers/gpio/gpio-mvebu.c if (val < state->duty_cycle) { val 678 drivers/gpio/gpio-mvebu.c val -= state->duty_cycle; val 679 drivers/gpio/gpio-mvebu.c if (val > UINT_MAX) val 681 drivers/gpio/gpio-mvebu.c else if (val) val 682 drivers/gpio/gpio-mvebu.c state->period = val; val 701 drivers/gpio/gpio-mvebu.c unsigned long long val; val 705 drivers/gpio/gpio-mvebu.c val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; val 706 drivers/gpio/gpio-mvebu.c do_div(val, NSEC_PER_SEC); val 707 drivers/gpio/gpio-mvebu.c if (val > UINT_MAX) val 709 drivers/gpio/gpio-mvebu.c if (val) val 710 drivers/gpio/gpio-mvebu.c on = val; val 714 drivers/gpio/gpio-mvebu.c val = (unsigned long long) mvpwm->clk_rate * val 716 drivers/gpio/gpio-mvebu.c do_div(val, NSEC_PER_SEC); val 717 drivers/gpio/gpio-mvebu.c if (val > UINT_MAX) val 719 drivers/gpio/gpio-mvebu.c if (val) val 720 drivers/gpio/gpio-mvebu.c off = val; val 175 drivers/gpio/gpio-mxc.c u32 bit, val; val 192 drivers/gpio/gpio-mxc.c val = port->gc.get(&port->gc, gpio_idx); val 193 drivers/gpio/gpio-mxc.c if (val) { val 214 drivers/gpio/gpio-mxc.c val = readl(port->base + GPIO_EDGE_SEL); val 216 drivers/gpio/gpio-mxc.c writel(val | (1 << gpio_idx), val 219 drivers/gpio/gpio-mxc.c writel(val & ~(1 << gpio_idx), val 226 drivers/gpio/gpio-mxc.c val = readl(reg) & ~(0x3 << (bit << 1)); val 227 drivers/gpio/gpio-mxc.c writel(val | (edge << (bit << 1)), reg); val 238 drivers/gpio/gpio-mxc.c u32 bit, val; val 243 drivers/gpio/gpio-mxc.c val = readl(reg); val 244 drivers/gpio/gpio-mxc.c edge = (val >> (bit << 1)) & 3; val 245 drivers/gpio/gpio-mxc.c val &= ~(0x3 << (bit << 1)); val 257 drivers/gpio/gpio-mxc.c writel(val | (edge << (bit << 1)), reg); val 72 drivers/gpio/gpio-mxs.c u32 val; val 87 drivers/gpio/gpio-mxs.c val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; val 88 drivers/gpio/gpio-mxs.c if (val) val 134 drivers/gpio/gpio-mxs.c u32 bit, val, edge; val 140 drivers/gpio/gpio-mxs.c val = readl(pin_addr); val 141 drivers/gpio/gpio-mxs.c edge = val & bit; val 94 drivers/gpio/gpio-omap.c u32 val = readl_relaxed(reg); val 97 drivers/gpio/gpio-omap.c val |= mask; val 99 drivers/gpio/gpio-omap.c val &= ~mask; val 101 drivers/gpio/gpio-omap.c writel_relaxed(val, reg); val 103 drivers/gpio/gpio-omap.c return val; val 181 drivers/gpio/gpio-omap.c u32 val; val 199 drivers/gpio/gpio-omap.c val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); val 200 drivers/gpio/gpio-omap.c bank->dbck_enable_mask = val; val 214 drivers/gpio/gpio-omap.c bank->context.debounce_en = val; val 855 drivers/gpio/gpio-omap.c u32 direction, m, val = 0; val 861 drivers/gpio/gpio-omap.c val |= readl_relaxed(base + bank->regs->datain) & m; val 865 drivers/gpio/gpio-omap.c val |= readl_relaxed(base + bank->regs->dataout) & m; val 867 drivers/gpio/gpio-omap.c *bits = val; val 31 drivers/gpio/gpio-palmas.c unsigned int val; val 39 drivers/gpio/gpio-palmas.c ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); val 45 drivers/gpio/gpio-palmas.c if (val & BIT(offset)) val 50 drivers/gpio/gpio-palmas.c ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); val 55 drivers/gpio/gpio-palmas.c return !!(val & BIT(offset)); val 336 drivers/gpio/gpio-pca953x.c static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) val 341 drivers/gpio/gpio-pca953x.c ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip)); val 350 drivers/gpio/gpio-pca953x.c static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) val 355 drivers/gpio/gpio-pca953x.c ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip)); val 379 drivers/gpio/gpio-pca953x.c unsigned off, int val) val 391 drivers/gpio/gpio-pca953x.c ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); val 425 drivers/gpio/gpio-pca953x.c static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) val 433 drivers/gpio/gpio-pca953x.c regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); val 846 drivers/gpio/gpio-pca953x.c u8 val[MAX_BANK]; val 860 drivers/gpio/gpio-pca953x.c memset(val, 0xFF, NBANK(chip)); val 862 drivers/gpio/gpio-pca953x.c memset(val, 0, NBANK(chip)); val 864 drivers/gpio/gpio-pca953x.c ret = pca953x_write_regs(chip, chip->regs->invert, val); val 872 drivers/gpio/gpio-pca953x.c u8 val[MAX_BANK]; val 879 drivers/gpio/gpio-pca953x.c memset(val, 0x02, NBANK(chip)); val 880 drivers/gpio/gpio-pca953x.c ret = pca953x_write_regs(chip, PCA957X_BKEN, val); val 97 drivers/gpio/gpio-pch.c static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) val 105 drivers/gpio/gpio-pch.c if (val) val 122 drivers/gpio/gpio-pch.c int val) val 132 drivers/gpio/gpio-pch.c if (val) val 223 drivers/gpio/gpio-pch.c u32 im, im_pos, val; val 242 drivers/gpio/gpio-pch.c val = PCH_EDGE_RISING; val 245 drivers/gpio/gpio-pch.c val = PCH_EDGE_FALLING; val 248 drivers/gpio/gpio-pch.c val = PCH_EDGE_BOTH; val 251 drivers/gpio/gpio-pch.c val = PCH_LEVEL_H; val 254 drivers/gpio/gpio-pch.c val = PCH_LEVEL_L; val 262 drivers/gpio/gpio-pch.c iowrite32(im | (val << (im_pos * 4)), im_reg); val 68 drivers/gpio/gpio-pmic-eic-sprd.c u16 reg, unsigned int val) val 74 drivers/gpio/gpio-pmic-eic-sprd.c BIT(shift), val << shift); val 268 drivers/gpio/gpio-pmic-eic-sprd.c u32 n, girq, val; val 272 drivers/gpio/gpio-pmic-eic-sprd.c &val); val 276 drivers/gpio/gpio-pmic-eic-sprd.c status = val & SPRD_PMIC_EIC_DATA_MASK; val 103 drivers/gpio/gpio-raspberrypi-exp.c static int rpi_exp_gpio_dir_out(struct gpio_chip *gc, unsigned int off, int val) val 115 drivers/gpio/gpio-raspberrypi-exp.c set_out.state = val; /* Output state */ val 175 drivers/gpio/gpio-raspberrypi-exp.c static void rpi_exp_gpio_set(struct gpio_chip *gc, unsigned int off, int val) val 184 drivers/gpio/gpio-raspberrypi-exp.c set.state = val; /* Output state */ val 28 drivers/gpio/gpio-rc5t583.c uint8_t val = 0; val 31 drivers/gpio/gpio-rc5t583.c ret = rc5t583_read(parent, RC5T583_GPIO_MON_IOIN, &val); val 35 drivers/gpio/gpio-rc5t583.c return !!(val & BIT(offset)); val 38 drivers/gpio/gpio-rc5t583.c static void rc5t583_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) val 42 drivers/gpio/gpio-rc5t583.c if (val) val 318 drivers/gpio/gpio-rcar.c u32 val, bankmask; val 328 drivers/gpio/gpio-rcar.c val = gpio_rcar_read(p, OUTDT); val 329 drivers/gpio/gpio-rcar.c val &= ~bankmask; val 330 drivers/gpio/gpio-rcar.c val |= (bankmask & bits[0]); val 331 drivers/gpio/gpio-rcar.c gpio_rcar_write(p, OUTDT, val); val 55 drivers/gpio/gpio-reg.c u32 val, mask = BIT(offset); val 58 drivers/gpio/gpio-reg.c val = r->out; val 60 drivers/gpio/gpio-reg.c val |= mask; val 62 drivers/gpio/gpio-reg.c val &= ~mask; val 63 drivers/gpio/gpio-reg.c r->out = val; val 64 drivers/gpio/gpio-reg.c writel_relaxed(val, r->reg); val 71 drivers/gpio/gpio-reg.c u32 val, mask = BIT(offset); val 79 drivers/gpio/gpio-reg.c val = readl_relaxed(r->reg); val 81 drivers/gpio/gpio-reg.c val = r->out; val 83 drivers/gpio/gpio-reg.c return !!(val & mask); val 100 drivers/gpio/gpio-sama5d2-piobu.c unsigned int val, reg; val 104 drivers/gpio/gpio-sama5d2-piobu.c ret = regmap_read(piobu->regmap, reg, &val); val 108 drivers/gpio/gpio-sama5d2-piobu.c return val & mask; val 140 drivers/gpio/gpio-sama5d2-piobu.c unsigned int val = PIOBU_OUT; val 143 drivers/gpio/gpio-sama5d2-piobu.c val |= PIOBU_HIGH; val 146 drivers/gpio/gpio-sama5d2-piobu.c val); val 63 drivers/gpio/gpio-sch.c int val) val 73 drivers/gpio/gpio-sch.c if (val) val 95 drivers/gpio/gpio-sch.c static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val) val 100 drivers/gpio/gpio-sch.c sch_gpio_reg_set(sch, gpio_num, GLV, val); val 105 drivers/gpio/gpio-sch.c int val) val 122 drivers/gpio/gpio-sch.c sch_gpio_set(gc, gpio_num, val); val 121 drivers/gpio/gpio-sch311x.c static inline void sch311x_sio_outb(int sio_config_port, int reg, int val) val 124 drivers/gpio/gpio-sch311x.c outb(val, sio_config_port + 1); val 49 drivers/gpio/gpio-sprd.c u16 reg, int val) val 60 drivers/gpio/gpio-sprd.c if (val) val 53 drivers/gpio/gpio-sta2x11.c static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) val 59 drivers/gpio/gpio-sta2x11.c if (val) val 75 drivers/gpio/gpio-sta2x11.c int val) val 83 drivers/gpio/gpio-sta2x11.c if (val) val 149 drivers/gpio/gpio-sta2x11.c u32 val; val 159 drivers/gpio/gpio-sta2x11.c val = readl(®s->afsela); val 161 drivers/gpio/gpio-sta2x11.c val |= bit; val 163 drivers/gpio/gpio-sta2x11.c val &= ~bit; val 164 drivers/gpio/gpio-sta2x11.c writel(val | bit, ®s->afsela); val 182 drivers/gpio/gpio-sta2x11.c val = readl(®s->pdis) | bit; val 183 drivers/gpio/gpio-sta2x11.c writel(val, ®s->pdis); val 187 drivers/gpio/gpio-sta2x11.c val = readl(®s->pdis) & ~bit; val 188 drivers/gpio/gpio-sta2x11.c writel(val, ®s->pdis); val 193 drivers/gpio/gpio-sta2x11.c val = readl(®s->pdis) & ~bit; val 194 drivers/gpio/gpio-sta2x11.c writel(val, ®s->pdis); val 217 drivers/gpio/gpio-sta2x11.c u32 val; val 222 drivers/gpio/gpio-sta2x11.c val = readl(®s->rimsc) & ~bit; val 223 drivers/gpio/gpio-sta2x11.c writel(val, ®s->rimsc); val 226 drivers/gpio/gpio-sta2x11.c val = readl(®s->fimsc) & ~bit; val 227 drivers/gpio/gpio-sta2x11.c writel(val, ®s->fimsc); val 240 drivers/gpio/gpio-sta2x11.c u32 val; val 247 drivers/gpio/gpio-sta2x11.c val = readl(®s->rimsc); val 249 drivers/gpio/gpio-sta2x11.c writel(val | bit, ®s->rimsc); val 251 drivers/gpio/gpio-sta2x11.c writel(val & ~bit, ®s->rimsc); val 252 drivers/gpio/gpio-sta2x11.c val = readl(®s->rimsc); val 254 drivers/gpio/gpio-sta2x11.c writel(val | bit, ®s->fimsc); val 256 drivers/gpio/gpio-sta2x11.c writel(val & ~bit, ®s->fimsc); val 56 drivers/gpio/gpio-stmpe.c static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) val 60 drivers/gpio/gpio-stmpe.c int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; val 69 drivers/gpio/gpio-stmpe.c stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); val 91 drivers/gpio/gpio-stmpe.c unsigned offset, int val) val 98 drivers/gpio/gpio-stmpe.c stmpe_gpio_set(chip, offset, val); val 254 drivers/gpio/gpio-stmpe.c bool val = !!stmpe_gpio_get(gc, offset); val 269 drivers/gpio/gpio-stmpe.c val ? "hi" : "lo"); val 338 drivers/gpio/gpio-stmpe.c val ? "hi" : "lo", val 70 drivers/gpio/gpio-stp-xway.c #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg) val 108 drivers/gpio/gpio-stp-xway.c static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val) val 112 drivers/gpio/gpio-stp-xway.c if (val) val 128 drivers/gpio/gpio-stp-xway.c static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val) val 130 drivers/gpio/gpio-stp-xway.c xway_stp_set(gc, gpio, val); val 61 drivers/gpio/gpio-syscon.c unsigned int val, offs; val 67 drivers/gpio/gpio-syscon.c (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val); val 71 drivers/gpio/gpio-syscon.c return !!(val & BIT(offs % SYSCON_REG_BITS)); val 74 drivers/gpio/gpio-syscon.c static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val) val 84 drivers/gpio/gpio-syscon.c val ? BIT(offs % SYSCON_REG_BITS) : 0); val 105 drivers/gpio/gpio-syscon.c static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val) val 121 drivers/gpio/gpio-syscon.c chip->set(chip, offset, val); val 135 drivers/gpio/gpio-syscon.c int val) val 145 drivers/gpio/gpio-syscon.c data = (val ? BIT(bit) : 0) | BIT(bit + 16); val 163 drivers/gpio/gpio-syscon.c static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val) val 171 drivers/gpio/gpio-syscon.c if (!val) val 54 drivers/gpio/gpio-tb10x.c u32 val) val 56 drivers/gpio/gpio-tb10x.c iowrite32(val, gpio->base + offs); val 60 drivers/gpio/gpio-tb10x.c u32 mask, u32 val) val 68 drivers/gpio/gpio-tb10x.c r = (r & ~mask) | (val & mask); val 52 drivers/gpio/gpio-tc3589x.c static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) val 58 drivers/gpio/gpio-tc3589x.c u8 data[] = {val ? BIT(pos) : 0, BIT(pos)}; val 64 drivers/gpio/gpio-tc3589x.c unsigned int offset, int val) val 71 drivers/gpio/gpio-tc3589x.c tc3589x_gpio_set(chip, offset, val); val 97 drivers/gpio/gpio-tegra.c u32 val, u32 reg) val 99 drivers/gpio/gpio-tegra.c __raw_writel(val, tgi->regs + reg); val 116 drivers/gpio/gpio-tegra.c u32 val; val 118 drivers/gpio/gpio-tegra.c val = 0x100 << GPIO_BIT(gpio); val 120 drivers/gpio/gpio-tegra.c val |= 1 << GPIO_BIT(gpio); val 121 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, val, reg); val 306 drivers/gpio/gpio-tegra.c u32 val; val 336 drivers/gpio/gpio-tegra.c val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); val 337 drivers/gpio/gpio-tegra.c val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); val 338 drivers/gpio/gpio-tegra.c val |= lvl_type << GPIO_BIT(gpio); val 339 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); val 77 drivers/gpio/gpio-timberdale.c unsigned nr, int val) val 83 drivers/gpio/gpio-timberdale.c unsigned nr, int val) val 85 drivers/gpio/gpio-timberdale.c timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0); val 49 drivers/gpio/gpio-tps65086.c int ret, val; val 51 drivers/gpio/gpio-tps65086.c ret = regmap_read(gpio->tps->regmap, TPS65086_GPOCTRL, &val); val 55 drivers/gpio/gpio-tps65086.c return val & BIT(4 + offset); val 27 drivers/gpio/gpio-tps65218.c unsigned int val; val 30 drivers/gpio/gpio-tps65218.c ret = regmap_read(tps65218->regmap, TPS65218_REG_ENABLE2, &val); val 34 drivers/gpio/gpio-tps65218.c return !!(val & (TPS65218_ENABLE2_GPIO1 << offset)); val 33 drivers/gpio/gpio-tps6586x.c uint8_t val; val 36 drivers/gpio/gpio-tps6586x.c ret = tps6586x_read(tps6586x_gpio->parent, TPS6586X_GPIOSET2, &val); val 40 drivers/gpio/gpio-tps6586x.c return !!(val & (1 << offset)); val 56 drivers/gpio/gpio-tps6586x.c uint8_t val, mask; val 60 drivers/gpio/gpio-tps6586x.c val = 0x1 << (offset * 2); val 64 drivers/gpio/gpio-tps6586x.c val, mask); val 29 drivers/gpio/gpio-tps65910.c unsigned int val; val 31 drivers/gpio/gpio-tps65910.c tps65910_reg_read(tps65910, TPS65910_GPIO0 + offset, &val); val 33 drivers/gpio/gpio-tps65910.c if (val & GPIO_STS_MASK) val 28 drivers/gpio/gpio-tps65912.c int ret, val; val 30 drivers/gpio/gpio-tps65912.c ret = regmap_read(gpio->tps->regmap, TPS65912_GPIO1 + offset, &val); val 34 drivers/gpio/gpio-tps65912.c if (val & GPIO_CFG_MASK) val 64 drivers/gpio/gpio-tps65912.c int ret, val; val 66 drivers/gpio/gpio-tps65912.c ret = regmap_read(gpio->tps->regmap, TPS65912_GPIO1 + offset, &val); val 70 drivers/gpio/gpio-tps65912.c if (val & GPIO_STS_MASK) val 34 drivers/gpio/gpio-tps68470.c int val, ret; val 41 drivers/gpio/gpio-tps68470.c ret = regmap_read(regmap, reg, &val); val 47 drivers/gpio/gpio-tps68470.c return !!(val & BIT(offset)); val 56 drivers/gpio/gpio-tps68470.c int val, ret; val 62 drivers/gpio/gpio-tps68470.c ret = regmap_read(regmap, TPS68470_GPIO_CTL_REG_A(offset), &val); val 69 drivers/gpio/gpio-tps68470.c val &= TPS68470_GPIO_MODE_MASK; val 70 drivers/gpio/gpio-tps68470.c return val >= TPS68470_GPIO_MODE_OUT_CMOS ? 0 : 1; val 49 drivers/gpio/gpio-tqmx86.c static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val, val 52 drivers/gpio/gpio-tqmx86.c iowrite8(val, gd->io_base + reg); val 67 drivers/gpio/gpio-tqmx86.c u8 val; val 70 drivers/gpio/gpio-tqmx86.c val = tqmx86_gpio_read(gpio, TQMX86_GPIOD); val 72 drivers/gpio/gpio-tqmx86.c val |= BIT(offset); val 74 drivers/gpio/gpio-tqmx86.c val &= ~BIT(offset); val 75 drivers/gpio/gpio-tqmx86.c tqmx86_gpio_write(gpio, val, TQMX86_GPIOD); val 186 drivers/gpio/gpio-ts5500.c u8 val = inb(addr); val 187 drivers/gpio/gpio-ts5500.c val |= mask; val 188 drivers/gpio/gpio-ts5500.c outb(val, addr); val 193 drivers/gpio/gpio-ts5500.c u8 val = inb(addr); val 194 drivers/gpio/gpio-ts5500.c val &= ~mask; val 195 drivers/gpio/gpio-ts5500.c outb(val, addr); val 225 drivers/gpio/gpio-ts5500.c static int ts5500_gpio_output(struct gpio_chip *chip, unsigned offset, int val) val 238 drivers/gpio/gpio-ts5500.c if (val) val 247 drivers/gpio/gpio-ts5500.c static void ts5500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) val 254 drivers/gpio/gpio-ts5500.c if (val) val 19 drivers/gpio/gpio-ucb1400.c static int ucb1400_gpio_dir_out(struct gpio_chip *gc, unsigned off, int val) val 24 drivers/gpio/gpio-ucb1400.c ucb1400_gpio_set_value(gpio->ac97, off, val); val 36 drivers/gpio/gpio-ucb1400.c static void ucb1400_gpio_set(struct gpio_chip *gc, unsigned off, int val) val 40 drivers/gpio/gpio-ucb1400.c ucb1400_gpio_set_value(gpio->ac97, off, val); val 63 drivers/gpio/gpio-uniphier.c unsigned int reg, u32 mask, u32 val) val 71 drivers/gpio/gpio-uniphier.c tmp |= mask & val; val 77 drivers/gpio/gpio-uniphier.c unsigned int reg, u32 mask, u32 val) val 85 drivers/gpio/gpio-uniphier.c mask, val); val 90 drivers/gpio/gpio-uniphier.c int val) val 97 drivers/gpio/gpio-uniphier.c uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0); val 128 drivers/gpio/gpio-uniphier.c unsigned int offset, int val) val 130 drivers/gpio/gpio-uniphier.c uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); val 142 drivers/gpio/gpio-uniphier.c unsigned int offset, int val) val 144 drivers/gpio/gpio-uniphier.c uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); val 208 drivers/gpio/gpio-uniphier.c u32 val = 0; val 211 drivers/gpio/gpio-uniphier.c val = mask; val 215 drivers/gpio/gpio-uniphier.c uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val); val 217 drivers/gpio/gpio-uniphier.c uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val); val 433 drivers/gpio/gpio-uniphier.c u32 *val = priv->saved_vals; val 440 drivers/gpio/gpio-uniphier.c *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); val 441 drivers/gpio/gpio-uniphier.c *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); val 444 drivers/gpio/gpio-uniphier.c *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN); val 445 drivers/gpio/gpio-uniphier.c *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE); val 446 drivers/gpio/gpio-uniphier.c *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); val 455 drivers/gpio/gpio-uniphier.c const u32 *val = priv->saved_vals; val 462 drivers/gpio/gpio-uniphier.c writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); val 463 drivers/gpio/gpio-uniphier.c writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); val 466 drivers/gpio/gpio-uniphier.c writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN); val 467 drivers/gpio/gpio-uniphier.c writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE); val 468 drivers/gpio/gpio-uniphier.c writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); val 74 drivers/gpio/gpio-vf610.c static inline void vf610_gpio_writel(u32 val, void __iomem *reg) val 76 drivers/gpio/gpio-vf610.c writel_relaxed(val, reg); val 99 drivers/gpio/gpio-vf610.c static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 103 drivers/gpio/gpio-vf610.c unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR; val 112 drivers/gpio/gpio-vf610.c u32 val; val 115 drivers/gpio/gpio-vf610.c val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); val 116 drivers/gpio/gpio-vf610.c val &= ~mask; val 117 drivers/gpio/gpio-vf610.c vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); val 58 drivers/gpio/gpio-viperboard.c u16 val; val 261 drivers/gpio/gpio-viperboard.c gbmsg->val = cpu_to_be16(dir << offset); val 279 drivers/gpio/gpio-viperboard.c u16 val; val 294 drivers/gpio/gpio-viperboard.c val = gbmsg->val; val 302 drivers/gpio/gpio-viperboard.c gpio->gpiob_val = be16_to_cpu(val); val 324 drivers/gpio/gpio-viperboard.c gbmsg->val = cpu_to_be16(value << offset); val 131 drivers/gpio/gpio-vx855.c int val) val 144 drivers/gpio/gpio-vx855.c if (val) val 149 drivers/gpio/gpio-vx855.c if (val) val 159 drivers/gpio/gpio-vx855.c unsigned int nr, int val) val 168 drivers/gpio/gpio-vx855.c vx855gpio_set(gpio, nr, val); val 169 drivers/gpio/gpio-wcove.c unsigned int val; val 175 drivers/gpio/gpio-wcove.c ret = regmap_read(wg->regmap, reg, &val); val 179 drivers/gpio/gpio-wcove.c return !(val & CTLO_DIR_OUT); val 185 drivers/gpio/gpio-wcove.c unsigned int val; val 191 drivers/gpio/gpio-wcove.c ret = regmap_read(wg->regmap, reg, &val); val 195 drivers/gpio/gpio-wcove.c return val & 0x1; val 184 drivers/gpio/gpio-winbond.c u8 val; val 186 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_read(base, reg); val 187 drivers/gpio/gpio-winbond.c val |= BIT(bit); val 188 drivers/gpio/gpio-winbond.c winbond_sio_reg_write(base, reg, val); val 193 drivers/gpio/gpio-winbond.c u8 val; val 195 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_read(base, reg); val 196 drivers/gpio/gpio-winbond.c val &= ~BIT(bit); val 197 drivers/gpio/gpio-winbond.c winbond_sio_reg_write(base, reg, val); val 387 drivers/gpio/gpio-winbond.c bool val; val 391 drivers/gpio/gpio-winbond.c val = winbond_sio_enter(*base); val 392 drivers/gpio/gpio-winbond.c if (val) val 393 drivers/gpio/gpio-winbond.c return val; val 397 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_btest(*base, info->datareg, offset); val 399 drivers/gpio/gpio-winbond.c val = !val; val 403 drivers/gpio/gpio-winbond.c return val; val 430 drivers/gpio/gpio-winbond.c int val) val 448 drivers/gpio/gpio-winbond.c val = !val; val 450 drivers/gpio/gpio-winbond.c if (val) val 461 drivers/gpio/gpio-winbond.c int val) val 475 drivers/gpio/gpio-winbond.c val = !val; val 477 drivers/gpio/gpio-winbond.c if (val) val 498 drivers/gpio/gpio-winbond.c unsigned int val; val 500 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_read(base, WB_SIO_REG_GPIO1_MF); val 501 drivers/gpio/gpio-winbond.c if ((val & WB_SIO_REG_G1MF_FS_MASK) == WB_SIO_REG_G1MF_FS_GPIO1) val 505 drivers/gpio/gpio-winbond.c val); val 507 drivers/gpio/gpio-winbond.c val &= ~WB_SIO_REG_G1MF_FS_MASK; val 508 drivers/gpio/gpio-winbond.c val |= WB_SIO_REG_G1MF_FS_GPIO1; val 510 drivers/gpio/gpio-winbond.c winbond_sio_reg_write(base, WB_SIO_REG_GPIO1_MF, val); val 33 drivers/gpio/gpio-wm831x.c int val = WM831X_GPN_DIR; val 36 drivers/gpio/gpio-wm831x.c val |= WM831X_GPN_TRI; val 40 drivers/gpio/gpio-wm831x.c WM831X_GPN_FN_MASK, val); val 73 drivers/gpio/gpio-wm831x.c int val = 0; val 77 drivers/gpio/gpio-wm831x.c val |= WM831X_GPN_TRI; val 81 drivers/gpio/gpio-wm831x.c WM831X_GPN_FN_MASK, val); val 62 drivers/gpio/gpio-xgene-sb.c void __iomem *reg, u32 gpio, int val) val 67 drivers/gpio/gpio-xgene-sb.c if (val) val 48 drivers/gpio/gpio-xgene.c static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) val 58 drivers/gpio/gpio-xgene.c if (val) val 65 drivers/gpio/gpio-xgene.c static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) val 71 drivers/gpio/gpio-xgene.c __xgene_gpio_set(gc, offset, val); val 107 drivers/gpio/gpio-xgene.c unsigned int offset, int val) val 121 drivers/gpio/gpio-xgene.c __xgene_gpio_set(gc, offset, val); val 27 drivers/gpio/gpio-xilinx.c # define xgpio_writereg(offset, val) writel(val, offset) val 30 drivers/gpio/gpio-xilinx.c # define xgpio_writereg(offset, val) __raw_writel(val, offset) val 89 drivers/gpio/gpio-xilinx.c u32 val; val 91 drivers/gpio/gpio-xilinx.c val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + val 94 drivers/gpio/gpio-xilinx.c return !!(val & BIT(xgpio_offset(chip, gpio))); val 106 drivers/gpio/gpio-xilinx.c static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 116 drivers/gpio/gpio-xilinx.c if (val) val 214 drivers/gpio/gpio-xilinx.c static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 224 drivers/gpio/gpio-xilinx.c if (val) val 79 drivers/gpio/gpio-xra1403.c unsigned int val; val 82 drivers/gpio/gpio-xra1403.c ret = regmap_read(xra->regmap, to_reg(XRA_GCR, offset), &val); val 86 drivers/gpio/gpio-xra1403.c return !!(val & BIT(offset % 8)); val 92 drivers/gpio/gpio-xra1403.c unsigned int val; val 95 drivers/gpio/gpio-xra1403.c ret = regmap_read(xra->regmap, to_reg(XRA_GSR, offset), &val); val 99 drivers/gpio/gpio-xra1403.c return !!(val & BIT(offset % 8)); val 117 drivers/gpio/gpio-xtensa.c u32 val = value ? BIT(offset) : 0; val 121 drivers/gpio/gpio-xtensa.c :: "a" (val), "a" (mask)); val 68 drivers/gpio/gpio-zevio.c unsigned port_offset, u32 val) val 71 drivers/gpio/gpio-zevio.c writel(val, IOMEM(c->chip.regs + section_offset + port_offset)); val 78 drivers/gpio/gpio-zevio.c u32 val, dir; val 83 drivers/gpio/gpio-zevio.c val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); val 85 drivers/gpio/gpio-zevio.c val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); val 88 drivers/gpio/gpio-zevio.c return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1; val 94 drivers/gpio/gpio-zevio.c u32 val; val 97 drivers/gpio/gpio-zevio.c val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); val 99 drivers/gpio/gpio-zevio.c val |= BIT(ZEVIO_GPIO_BIT(pin)); val 101 drivers/gpio/gpio-zevio.c val &= ~BIT(ZEVIO_GPIO_BIT(pin)); val 103 drivers/gpio/gpio-zevio.c zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); val 110 drivers/gpio/gpio-zevio.c u32 val; val 114 drivers/gpio/gpio-zevio.c val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); val 115 drivers/gpio/gpio-zevio.c val |= BIT(ZEVIO_GPIO_BIT(pin)); val 116 drivers/gpio/gpio-zevio.c zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); val 127 drivers/gpio/gpio-zevio.c u32 val; val 130 drivers/gpio/gpio-zevio.c val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); val 132 drivers/gpio/gpio-zevio.c val |= BIT(ZEVIO_GPIO_BIT(pin)); val 134 drivers/gpio/gpio-zevio.c val &= ~BIT(ZEVIO_GPIO_BIT(pin)); val 136 drivers/gpio/gpio-zevio.c zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); val 137 drivers/gpio/gpio-zevio.c val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); val 138 drivers/gpio/gpio-zevio.c val &= ~BIT(ZEVIO_GPIO_BIT(pin)); val 139 drivers/gpio/gpio-zevio.c zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); val 614 drivers/gpio/gpiolib.c int val = !!handlereq.default_values[i]; val 616 drivers/gpio/gpiolib.c ret = gpiod_direction_output(desc, val); val 796 drivers/gpio/gpiolib.c int val; val 800 drivers/gpio/gpiolib.c val = gpiod_get_value_cansleep(le->desc); val 801 drivers/gpio/gpiolib.c if (val < 0) val 802 drivers/gpio/gpiolib.c return val; val 803 drivers/gpio/gpiolib.c ghd.values[0] = val; val 3012 drivers/gpio/gpiolib.c int val = !!value; val 3028 drivers/gpio/gpiolib.c ret = gc->direction_output(gc, gpio_chip_hwgpio(desc), val); val 3042 drivers/gpio/gpiolib.c gc->set(gc, gpio_chip_hwgpio(desc), val); val 3047 drivers/gpio/gpiolib.c trace_gpio_value(desc_to_gpio(desc), 0, val); val 146 drivers/gpio/sgpio-aspeed.c static void sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val) val 156 drivers/gpio/sgpio-aspeed.c if (val) val 164 drivers/gpio/sgpio-aspeed.c static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val) val 171 drivers/gpio/sgpio-aspeed.c sgpio_set_value(gc, offset, val); val 188 drivers/gpio/sgpio-aspeed.c static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val) val 196 drivers/gpio/sgpio-aspeed.c sgpio_set_value(gc, offset, val); val 1089 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_P(reg, val, mask) \ val 1093 drivers/gpu/drm/amd/amdgpu/amdgpu.h tmp_ |= ((val) & ~(mask)); \ val 1098 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_PLL_P(reg, val, mask) \ val 1102 drivers/gpu/drm/amd/amdgpu/amdgpu.h tmp_ |= ((val) & ~(mask)); \ val 1119 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_FIELD(reg, field, val) \ val 1120 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) val 1122 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ val 1123 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) val 189 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c u32 val = 0; val 358 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); val 360 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val |= ACP_SOFT_RESET__SoftResetAud_MASK; val 361 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); val 365 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); val 367 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) val 377 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); val 378 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = val | ACP_CONTROL__ClkEn_MASK; val 379 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); val 384 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); val 385 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c if (val & (u32) 0x1) val 395 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); val 396 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; val 397 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); val 417 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c u32 val = 0; val 429 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); val 431 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val |= ACP_SOFT_RESET__SoftResetAud_MASK; val 432 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); val 436 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); val 438 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) val 447 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); val 448 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val &= ~ACP_CONTROL__ClkEn_MASK; val 449 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); val 454 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); val 455 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c if (val & (u32) 0x1) val 742 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c unsigned long val, val 1841 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) val 1869 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) val 1883 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) val 1887 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32(reg, val); val 1917 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) val 1921 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32_IO(reg, val); val 466 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c uint64_t val) val 488 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c new_coherent_mode = val ? true : false; val 504 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c if (amdgpu_connector->audio != val) { val 505 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector->audio = val; val 519 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c if (amdgpu_connector->dither != val) { val 520 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector->dither = val; val 533 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c if (amdgpu_encoder->underscan_type != val) { val 534 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_encoder->underscan_type = val; val 547 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c if (amdgpu_encoder->underscan_hborder != val) { val 548 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_encoder->underscan_hborder = val; val 561 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c if (amdgpu_encoder->underscan_vborder != val) { val 562 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_encoder->underscan_vborder = val; val 571 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c if (val == 0) val 587 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c switch (val) { val 1020 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c static int amdgpu_debugfs_ib_preempt(void *data, u64 val) val 1027 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c if (val >= AMDGPU_MAX_RINGS) val 1030 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c ring = adev->rings[val]; val 106 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t val; val 109 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val = RREG32(rec->y_clk_reg); val 110 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val &= rec->y_clk_mask; val 112 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c return (val != 0); val 121 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t val; val 124 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val = RREG32(rec->y_data_reg); val 125 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val &= rec->y_data_mask; val 127 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c return (val != 0); val 135 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t val; val 138 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; val 139 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val |= clock ? 0 : rec->en_clk_mask; val 140 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->en_clk_reg, val); val 148 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t val; val 151 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; val 152 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val |= data ? 0 : rec->en_data_mask; val 153 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->en_data_reg, val); val 286 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c u8 *val) val 309 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c *val = in_buf[0]; val 310 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c DRM_DEBUG("val = 0x%02x\n", *val); val 313 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c addr, *val); val 320 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c u8 val) val 331 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c out_buf[1] = val; val 335 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c addr, val); val 342 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c u8 val; val 352 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c 0x3, &val); val 353 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val &= ~amdgpu_connector->router.ddc_mux_control_pin; val 356 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c 0x3, val); val 359 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c 0x1, &val); val 360 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val &= ~amdgpu_connector->router.ddc_mux_control_pin; val 361 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val |= amdgpu_connector->router.ddc_mux_state; val 364 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c 0x1, val); val 371 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c u8 val; val 381 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c 0x3, &val); val 382 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val &= ~amdgpu_connector->router.cd_mux_control_pin; val 385 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c 0x3, val); val 388 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c 0x1, &val); val 389 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val &= ~amdgpu_connector->router.cd_mux_control_pin; val 390 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val |= amdgpu_connector->router.cd_mux_state; val 393 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c 0x1, val); val 112 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t val; val 117 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c val = RREG32(reg_index); val 119 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c if (val != reg_val) val 122 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c if ((val & mask) == reg_val) val 76 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c char val[128]; val 81 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", val 91 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c if (copy_to_user(buf, &val[*pos], s)) val 163 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); val 165 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t val, uint32_t mask); val 223 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h #define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \ val 225 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \ val 228 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h #define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \ val 230 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h (*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \ val 233 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h #define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \ val 236 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h *(val) = 0; \ val 239 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h *(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \ val 241 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h *(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \ val 179 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t idx, val = 0xCDCDCDCD, align, arg; val 192 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->card->reg_read(gctx->card, idx); val 210 drivers/gpu/drm/amd/amdgpu/atom.c val = val 221 drivers/gpu/drm/amd/amdgpu/atom.c val = get_unaligned_le32((u32 *)&ctx->ps[idx]); val 223 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG("PS[0x%02X,0x%04X]", idx, val); val 232 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->divmul[0]; val 235 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->divmul[1]; val 238 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->data_block; val 241 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->shift; val 244 drivers/gpu/drm/amd/amdgpu/atom.c val = 1 << gctx->shift; val 247 drivers/gpu/drm/amd/amdgpu/atom.c val = ~(1 << gctx->shift); val 250 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->fb_base; val 253 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->io_attr; val 256 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->reg_block; val 259 drivers/gpu/drm/amd/amdgpu/atom.c val = ctx->ws[idx]; val 271 drivers/gpu/drm/amd/amdgpu/atom.c val = U32(idx + gctx->data_block); val 279 drivers/gpu/drm/amd/amdgpu/atom.c val = 0; val 281 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->scratch[(gctx->fb_base / 4) + idx]; val 288 drivers/gpu/drm/amd/amdgpu/atom.c val = U32(*ptr); val 291 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG("IMM 0x%08X\n", val); val 292 drivers/gpu/drm/amd/amdgpu/atom.c return val; val 296 drivers/gpu/drm/amd/amdgpu/atom.c val = U16(*ptr); val 299 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG("IMM 0x%04X\n", val); val 300 drivers/gpu/drm/amd/amdgpu/atom.c return val; val 305 drivers/gpu/drm/amd/amdgpu/atom.c val = U8(*ptr); val 308 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG("IMM 0x%02X\n", val); val 309 drivers/gpu/drm/amd/amdgpu/atom.c return val; val 317 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->card->pll_read(gctx->card, idx); val 324 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->card->mc_read(gctx->card, idx); val 328 drivers/gpu/drm/amd/amdgpu/atom.c *saved = val; val 329 drivers/gpu/drm/amd/amdgpu/atom.c val &= atom_arg_mask[align]; val 330 drivers/gpu/drm/amd/amdgpu/atom.c val >>= atom_arg_shift[align]; val 334 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG(".[31:0] -> 0x%08X\n", val); val 337 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG(".[15:0] -> 0x%04X\n", val); val 340 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG(".[23:8] -> 0x%04X\n", val); val 343 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG(".[31:16] -> 0x%04X\n", val); val 346 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG(".[7:0] -> 0x%02X\n", val); val 349 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG(".[15:8] -> 0x%02X\n", val); val 352 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG(".[23:16] -> 0x%02X\n", val); val 355 drivers/gpu/drm/amd/amdgpu/atom.c DEBUG(".[31:24] -> 0x%02X\n", val); val 358 drivers/gpu/drm/amd/amdgpu/atom.c return val; val 404 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t val = 0xCDCDCDCD; val 408 drivers/gpu/drm/amd/amdgpu/atom.c val = U32(*ptr); val 414 drivers/gpu/drm/amd/amdgpu/atom.c val = U16(*ptr); val 421 drivers/gpu/drm/amd/amdgpu/atom.c val = U8(*ptr); val 425 drivers/gpu/drm/amd/amdgpu/atom.c return val; val 445 drivers/gpu/drm/amd/amdgpu/atom.c int *ptr, uint32_t val, uint32_t saved) val 449 drivers/gpu/drm/amd/amdgpu/atom.c val, idx; val 452 drivers/gpu/drm/amd/amdgpu/atom.c val <<= atom_arg_shift[align]; val 453 drivers/gpu/drm/amd/amdgpu/atom.c val &= atom_arg_mask[align]; val 455 drivers/gpu/drm/amd/amdgpu/atom.c val |= saved; val 466 drivers/gpu/drm/amd/amdgpu/atom.c val << 2); val 468 drivers/gpu/drm/amd/amdgpu/atom.c gctx->card->reg_write(gctx->card, idx, val); val 487 drivers/gpu/drm/amd/amdgpu/atom.c idx, val); val 494 drivers/gpu/drm/amd/amdgpu/atom.c ctx->ps[idx] = cpu_to_le32(val); val 502 drivers/gpu/drm/amd/amdgpu/atom.c gctx->divmul[0] = val; val 505 drivers/gpu/drm/amd/amdgpu/atom.c gctx->divmul[1] = val; val 508 drivers/gpu/drm/amd/amdgpu/atom.c gctx->data_block = val; val 511 drivers/gpu/drm/amd/amdgpu/atom.c gctx->shift = val; val 517 drivers/gpu/drm/amd/amdgpu/atom.c gctx->fb_base = val; val 520 drivers/gpu/drm/amd/amdgpu/atom.c gctx->io_attr = val; val 523 drivers/gpu/drm/amd/amdgpu/atom.c gctx->reg_block = val; val 526 drivers/gpu/drm/amd/amdgpu/atom.c ctx->ws[idx] = val; val 536 drivers/gpu/drm/amd/amdgpu/atom.c gctx->scratch[(gctx->fb_base / 4) + idx] = val; val 543 drivers/gpu/drm/amd/amdgpu/atom.c gctx->card->pll_write(gctx->card, idx, val); val 549 drivers/gpu/drm/amd/amdgpu/atom.c gctx->card->mc_write(gctx->card, idx, val); val 843 drivers/gpu/drm/amd/amdgpu/atom.c uint8_t val = U8((*ptr)++); val 844 drivers/gpu/drm/amd/amdgpu/atom.c SDEBUG("POST card output: 0x%02X\n", val); val 1004 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t src, val, target; val 1011 drivers/gpu/drm/amd/amdgpu/atom.c val = val 1015 drivers/gpu/drm/amd/amdgpu/atom.c if (val == src) { val 1056 drivers/gpu/drm/amd/amdgpu/atom.c uint8_t val = U8((*ptr)++); val 1057 drivers/gpu/drm/amd/amdgpu/atom.c SDEBUG("DEBUG output: 0x%02X\n", val); val 1062 drivers/gpu/drm/amd/amdgpu/atom.c uint16_t val = U16(*ptr); val 1063 drivers/gpu/drm/amd/amdgpu/atom.c (*ptr) += val + 2; val 1064 drivers/gpu/drm/amd/amdgpu/atom.c SDEBUG("PROCESSDS output: 0x%02X\n", val); val 1032 drivers/gpu/drm/amd/amdgpu/cik.c uint32_t val; val 1051 drivers/gpu/drm/amd/amdgpu/cik.c val = RREG32(reg_offset); val 1056 drivers/gpu/drm/amd/amdgpu/cik.c return val; val 875 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t reg, uint32_t val) val 879 drivers/gpu/drm/amd/amdgpu/cik_sdma.c amdgpu_ring_write(ring, val); val 1507 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t offset, val; val 1537 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c val = RREG32(mmHDMI_CONTROL + offset); val 1538 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; val 1539 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK; val 1551 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; val 1552 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; val 1557 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; val 1558 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; val 1564 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_CONTROL + offset, val); val 328 drivers/gpu/drm/amd/amdgpu/dce_virtual.c uint64_t val) val 401 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c bool wc, uint32_t reg, uint32_t val) val 408 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, val); val 4807 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t val) val 4826 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, val); val 4830 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t val, uint32_t mask) val 4832 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); val 2363 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t reg, uint32_t val) val 2372 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c amdgpu_ring_write(ring, val); val 3283 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t reg, uint32_t val) val 3292 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, val); val 6502 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t val) val 6522 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, val); val 806 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c bool wc, uint32_t reg, uint32_t val) val 814 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, val); val 5422 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t val) val 5441 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, val); val 5445 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t val, uint32_t mask) val 5447 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); val 40 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val) val 42 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); val 164 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c u32 req, val, size; val 186 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c val = RREG32_NO_KIQ( val 190 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c val), PAGE_SIZE); val 193 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c strcpy(buf,((char *)adev->virt.fw_reserve.p_pf2vf + val)); val 341 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val) val 347 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c TRN_MSG_VALID, val ? 1 : 0); val 187 drivers/gpu/drm/amd/amdgpu/nv.c uint32_t val; val 193 drivers/gpu/drm/amd/amdgpu/nv.c val = RREG32(reg_offset); val 198 drivers/gpu/drm/amd/amdgpu/nv.c return val; val 816 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t reg, uint32_t val) val 821 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c amdgpu_ring_write(ring, val); val 1087 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t reg, uint32_t val) val 1092 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c amdgpu_ring_write(ring, val); val 1630 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t reg, uint32_t val) val 1635 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c amdgpu_ring_write(ring, val); val 1639 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t val, uint32_t mask) val 1641 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); val 1173 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t reg, uint32_t val) val 1178 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, val); val 1182 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t val, uint32_t mask) val 1189 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, val); /* reference */ val 1022 drivers/gpu/drm/amd/amdgpu/si.c uint32_t val; val 1039 drivers/gpu/drm/amd/amdgpu/si.c val = RREG32(reg_offset); val 1044 drivers/gpu/drm/amd/amdgpu/si.c return val; val 459 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t reg, uint32_t val) val 463 drivers/gpu/drm/amd/amdgpu/si_dma.c amdgpu_ring_write(ring, val); val 374 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t val; val 380 drivers/gpu/drm/amd/amdgpu/soc15.c val = RREG32(reg_offset); val 385 drivers/gpu/drm/amd/amdgpu/soc15.c return val; val 30 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_FIELD15(ip, idx, reg, field, val) \ val 33 drivers/gpu/drm/amd/amdgpu/soc15_common.h & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) val 122 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ val 125 drivers/gpu/drm/amd/amdgpu/soc15_common.h & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) val 1032 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t reg, uint32_t val) val 1037 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, val); val 1336 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val) val 1345 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, val); val 1352 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t val, uint32_t mask) val 1361 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, val); val 1404 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val, val 1410 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, val); val 1426 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val) val 1430 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, val); val 522 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c uint32_t val = 0; val 525 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; val 527 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); val 706 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t val = 0; val 709 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; val 711 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); val 981 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t val, uint32_t mask) val 986 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c amdgpu_ring_write(ring, val); val 1002 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t reg, uint32_t val) val 1006 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c amdgpu_ring_write(ring, val); val 1014 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t val = 0; val 1018 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; val 1020 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val, val 1540 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, val 1550 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, val); val 1575 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) val 1584 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, val); val 1691 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, val 1697 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, val); val 1713 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) val 1717 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, val); val 1935 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, val 1947 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, val); val 1980 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) val 1997 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, val); val 2012 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) val 2024 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[(*ptr)++] = val; val 2031 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, reg_offset, val, mask, i; val 2036 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c val = lower_32_bits(ring->gpu_addr); val 2037 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); val 2042 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c val = upper_32_bits(ring->gpu_addr); val 2043 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); val 2054 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c val = 0x13; val 2055 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); val 2060 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c val = 0x1; val 2061 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); val 2066 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c val = 0x1; val 2072 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[ptr++] = val; val 2093 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c val = 0; val 2094 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); val 2099 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c val = 0x12; val 2100 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); val 1600 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) val 1608 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, val); val 1634 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg, uint32_t val) val 1642 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, val); val 1766 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) val 1771 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, val); val 1786 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) val 1790 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, val); val 1988 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) val 1998 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, val); val 2029 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) val 2044 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, val); val 35 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); val 39 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t reg, uint32_t val); val 47 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); val 50 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); val 59 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); val 62 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); val 556 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t val; val 575 drivers/gpu/drm/amd/amdgpu/vi.c val = RREG32(reg_offset); val 580 drivers/gpu/drm/amd/amdgpu/vi.c return val; val 80 drivers/gpu/drm/amd/amdkfd/kfd_process.c int val = 0; val 85 drivers/gpu/drm/amd/amdkfd/kfd_process.c val = p->pasid; val 91 drivers/gpu/drm/amd/amdkfd/kfd_process.c return snprintf(buffer, PAGE_SIZE, "%d\n", val); val 3837 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint64_t val) val 3851 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c switch (val) { val 3873 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm_new_state->underscan_hborder = val; val 3876 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm_new_state->underscan_vborder = val; val 3879 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm_new_state->underscan_enable = val; val 3882 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm_new_state->abm_level = val; val 3892 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint64_t *val) val 3903 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c *val = DRM_MODE_SCALE_CENTER; val 3906 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c *val = DRM_MODE_SCALE_ASPECT; val 3909 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c *val = DRM_MODE_SCALE_FULLSCREEN; val 3913 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c *val = DRM_MODE_SCALE_NONE; val 3918 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c *val = dm_state->underscan_hborder; val 3921 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c *val = dm_state->underscan_vborder; val 3924 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c *val = dm_state->underscan_enable; val 3927 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c *val = dm_state->abm_level; val 361 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h uint64_t val); val 366 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h uint64_t *val); val 164 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c int64_t val; val 183 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c val = ctm->matrix[i - (i / 4)]; val 185 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c if (val & (1ULL << 63)) val 186 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c val = -(val & ~(1ULL << 63)); val 188 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c matrix[i].value = val; val 1089 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c static int visual_confirm_set(void *data, u64 val) val 1093 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; val 1102 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c static int visual_confirm_get(void *data, u64 *val) val 1106 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c *val = adev->dm.dc->debug.visual_confirm; val 210 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c const uint16_t *val = NULL; val 216 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c val = output_csc_matrix[i].regval; val 221 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c return val; val 52 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t dcp_grph, scl, blnd, update_lock_mode, val; val 60 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val 71 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, val 76 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, val 2054 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t val = 0; val 2068 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c val, val 2075 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c val, val 2080 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERTICAL_INTERRUPT0_POSITION), val); val 48 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_UPDATE(reg, field, val) \ val 49 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) val 63 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_SET(reg, field, val) \ val 64 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val) val 1348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define HPD_REG_UPDATE(reg_name, field, val) \ val 1350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c FN(reg_name, field), val) val 1380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define AUX_REG_UPDATE(reg_name, field, val) \ val 1382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c FN(reg_name, field), val) val 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c #define AUX_REG_WRITE(reg_name, val) \ val 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c dm_write_reg(CTX, AUX_REG(reg_name), val) val 88 drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h static inline double dml_fmod(double f, int val) val 90 drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h return (double) dcn_bw_mod(f, val); val 63 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET(reg_name, initial_val, field, val) \ val 65 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, field), val) val 156 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET(reg_name, field, val) \ val 158 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, field), val) val 218 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \ val 220 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(reg_name), FN(reg_name, field), val,\ val 230 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE(reg_name, field, val) \ val 232 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, field), val) val 383 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h { uint32_t val = REG_UPDATE(reg, f1, v1); \ val 384 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET(reg, val, f2, v2); } val 387 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h { uint32_t val = REG_UPDATE(reg, f1, v1); \ val 388 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h val = REG_SET(reg, val, f2, v2); \ val 389 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET(reg, val, f3, v3); } val 131 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_WREG32_FIELD(device, reg, field, val) \ val 132 drivers/gpu/drm/amd/include/cgs_common.h cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) val 134 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ val 135 drivers/gpu/drm/amd/include/cgs_common.h cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) val 96 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c entry[i].shift, entry[i].val, entry[i].timeout)) val 45 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t val; val 1657 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t val = cgs_read_ind_register(hwmgr->device, val 1659 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP); val 1661 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL)) val 372 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t val; val 382 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); val 384 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); val 385 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); val 386 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); val 387 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); val 388 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) & val 392 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); val 429 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t val = 0; val 443 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); val 444 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); val 445 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); val 447 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); val 178 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c uint32_t val; val 188 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); val 190 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); val 191 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); val 192 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); val 193 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); val 194 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); val 196 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); val 209 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c uint32_t val = 0; val 211 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); val 212 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); val 213 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); val 215 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); val 248 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t val; val 258 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); val 260 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); val 261 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); val 262 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); val 263 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); val 264 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); val 266 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); val 279 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t val = 0; val 281 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); val 282 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); val 283 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); val 285 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); val 1139 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t val; val 1149 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); val 1150 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); val 1151 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); val 1152 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); val 1153 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); val 1154 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); val 1155 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); val 1156 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); val 1158 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); val 1166 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t val = 0; val 1168 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); val 1169 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); val 1170 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); val 1172 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); val 1648 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t val; val 1661 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); val 1662 drivers/gpu/drm/amd/powerplay/smu_v11_0.c if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) val 186 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t val; val 211 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, val 214 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ixSMC_SYSCON_MISC_CNTL, val | 1); val 80 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t val = cgs_read_register(hwmgr->device, val 83 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c __func__, msg, val); val 78 drivers/gpu/drm/arc/arcpgu_crtc.c u32 val; val 95 drivers/gpu/drm/arc/arcpgu_crtc.c val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); val 98 drivers/gpu/drm/arc/arcpgu_crtc.c val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST; val 100 drivers/gpu/drm/arc/arcpgu_crtc.c val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST); val 103 drivers/gpu/drm/arc/arcpgu_crtc.c val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST; val 105 drivers/gpu/drm/arc/arcpgu_crtc.c val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST); val 107 drivers/gpu/drm/arc/arcpgu_crtc.c arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val); val 74 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 count, u32 *val) val 82 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val[i] = malidp_read32(reg, addr); val 84 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val[i] = 0xDEADDEAD; val 608 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 val = 0; val 611 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= 0x62; val 613 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= 0x63; val 615 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= 0x64; val 617 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= 0x65; val 619 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= 0x66; val 622 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= SC_VTSEL(0x6A); val 624 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= SC_VTSEL(0x6B); val 626 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= SC_VTSEL(0x6C); val 628 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= SC_VTSEL(0x6D); val 630 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val |= SC_VTSEL(0x6E); val 632 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SC_COEFFTAB, val); val 226 drivers/gpu/drm/arm/malidp_crtc.c s64 val = ctm->matrix[i]; val 227 drivers/gpu/drm/arm/malidp_crtc.c u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) & val 237 drivers/gpu/drm/arm/malidp_crtc.c if (val & BIT_ULL(63)) val 239 drivers/gpu/drm/arm/malidp_crtc.c if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14))) val 131 drivers/gpu/drm/arm/malidp_drv.c u32 val; val 135 drivers/gpu/drm/arm/malidp_drv.c val = malidp_hw_read(hwdev, se_control); val 136 drivers/gpu/drm/arm/malidp_drv.c val &= ~MALIDP_SE_SCALING_EN; val 137 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, val, se_control); val 142 drivers/gpu/drm/arm/malidp_drv.c val = malidp_hw_read(hwdev, se_control); val 143 drivers/gpu/drm/arm/malidp_drv.c val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN; val 145 drivers/gpu/drm/arm/malidp_drv.c val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK); val 146 drivers/gpu/drm/arm/malidp_drv.c val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0; val 148 drivers/gpu/drm/arm/malidp_drv.c val |= MALIDP_SE_RGBO_IF_EN; val 149 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, val, se_control); val 152 drivers/gpu/drm/arm/malidp_drv.c val = MALIDP_SE_SET_V_SIZE(s->input_h) | val 154 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE); val 155 drivers/gpu/drm/arm/malidp_drv.c val = MALIDP_SE_SET_V_SIZE(s->output_h) | val 157 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE); val 340 drivers/gpu/drm/arm/malidp_hw.c u32 val = 0; val 346 drivers/gpu/drm/arm/malidp_hw.c val |= MALIDP500_HSYNCPOL; val 348 drivers/gpu/drm/arm/malidp_hw.c val |= MALIDP500_VSYNCPOL; val 349 drivers/gpu/drm/arm/malidp_hw.c val |= MALIDP_DE_DEFAULT_PREFETCH_START; val 350 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL); val 358 drivers/gpu/drm/arm/malidp_hw.c val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) | val 360 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR); val 363 drivers/gpu/drm/arm/malidp_hw.c val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) | val 365 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS); val 367 drivers/gpu/drm/arm/malidp_hw.c val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) | val 369 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS); val 371 drivers/gpu/drm/arm/malidp_hw.c val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) | val 373 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH); val 375 drivers/gpu/drm/arm/malidp_hw.c val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive); val 376 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE); val 652 drivers/gpu/drm/arm/malidp_hw.c u32 val = MALIDP_DE_DEFAULT_PREFETCH_START; val 656 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL); val 666 drivers/gpu/drm/arm/malidp_hw.c val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) | val 669 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR); val 671 drivers/gpu/drm/arm/malidp_hw.c val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) | val 673 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS); val 675 drivers/gpu/drm/arm/malidp_hw.c val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) | val 677 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS); val 679 drivers/gpu/drm/arm/malidp_hw.c val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) | val 682 drivers/gpu/drm/arm/malidp_hw.c val |= MALIDP550_HSYNCPOL; val 684 drivers/gpu/drm/arm/malidp_hw.c val |= MALIDP550_VSYNCPOL; val 685 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH); val 687 drivers/gpu/drm/arm/malidp_hw.c val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive); val 688 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE); val 368 drivers/gpu/drm/arm/malidp_hw.h u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) | val 376 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_write(hwdev, val, image_enh); val 592 drivers/gpu/drm/arm/malidp_planes.c int val; val 594 drivers/gpu/drm/arm/malidp_planes.c val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, val 598 drivers/gpu/drm/arm/malidp_planes.c if (val < 0) val 599 drivers/gpu/drm/arm/malidp_planes.c return val; val 601 drivers/gpu/drm/arm/malidp_planes.c ms->rotmem_size = val; val 752 drivers/gpu/drm/arm/malidp_planes.c u32 src_w, src_h, val = 0, src_x, src_y; val 772 drivers/gpu/drm/arm/malidp_planes.c val = ((fb->width - (src_x + src_w)) << MALIDP_AD_CROP_RIGHT_OFFSET) | val 774 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, val 777 drivers/gpu/drm/arm/malidp_planes.c val = ((fb->height - (src_y + src_h)) << MALIDP_AD_CROP_BOTTOM_OFFSET) | val 779 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, val 782 drivers/gpu/drm/arm/malidp_planes.c val = MALIDP_AD_EN; val 784 drivers/gpu/drm/arm/malidp_planes.c val |= MALIDP_AD_BS; val 786 drivers/gpu/drm/arm/malidp_planes.c val |= MALIDP_AD_YTR; val 788 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset); val 799 drivers/gpu/drm/arm/malidp_planes.c u32 src_w, src_h, dest_w, dest_h, val; val 821 drivers/gpu/drm/arm/malidp_planes.c val = malidp_hw_read(mp->hwdev, mp->layer->base); val 822 drivers/gpu/drm/arm/malidp_planes.c val = (val & ~LAYER_FORMAT_MASK) | ms->format; val 823 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, mp->layer->base); val 863 drivers/gpu/drm/arm/malidp_planes.c val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); val 864 drivers/gpu/drm/arm/malidp_planes.c val &= ~LAYER_ROT_MASK; val 868 drivers/gpu/drm/arm/malidp_planes.c val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << val 871 drivers/gpu/drm/arm/malidp_planes.c val |= LAYER_H_FLIP; val 873 drivers/gpu/drm/arm/malidp_planes.c val |= LAYER_V_FLIP; val 875 drivers/gpu/drm/arm/malidp_planes.c val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff)); val 878 drivers/gpu/drm/arm/malidp_planes.c val |= LAYER_COMP_PLANE; val 883 drivers/gpu/drm/arm/malidp_planes.c val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE; val 886 drivers/gpu/drm/arm/malidp_planes.c val |= LAYER_COMP_PIXEL; val 890 drivers/gpu/drm/arm/malidp_planes.c val |= LAYER_ALPHA(plane_alpha); val 892 drivers/gpu/drm/arm/malidp_planes.c val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); val 899 drivers/gpu/drm/arm/malidp_planes.c val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); val 903 drivers/gpu/drm/arm/malidp_planes.c val |= LAYER_ENABLE; val 905 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, val 86 drivers/gpu/drm/armada/armada_crtc.c uint32_t val; val 88 drivers/gpu/drm/armada/armada_crtc.c val = regs->mask; val 89 drivers/gpu/drm/armada/armada_crtc.c if (val != 0) val 90 drivers/gpu/drm/armada/armada_crtc.c val &= readl_relaxed(reg); val 91 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(val | regs->val, reg); val 262 drivers/gpu/drm/armada/armada_crtc.c uint32_t val; val 268 drivers/gpu/drm/armada/armada_crtc.c val = readl_relaxed(base + LCD_SPU_ADV_REG); val 269 drivers/gpu/drm/armada/armada_crtc.c val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN); val 270 drivers/gpu/drm/armada/armada_crtc.c val |= dcrtc->v[i].spu_adv_reg; val 271 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(val, base + LCD_SPU_ADV_REG); val 335 drivers/gpu/drm/armada/armada_crtc.c uint32_t lm, rm, tm, bm, val, sclk; val 362 drivers/gpu/drm/armada/armada_crtc.c val = adj->crtc_hsync_start; val 363 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; val 367 drivers/gpu/drm/armada/armada_crtc.c val -= adj->crtc_htotal / 2; val 368 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; val 376 drivers/gpu/drm/armada/armada_crtc.c val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; val 378 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); val 389 drivers/gpu/drm/armada/armada_crtc.c val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0; val 390 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1); val 400 drivers/gpu/drm/armada/armada_crtc.c val = 0; val 402 drivers/gpu/drm/armada/armada_crtc.c val |= CFG_INV_CSYNC; val 404 drivers/gpu/drm/armada/armada_crtc.c val |= CFG_INV_HSYNC; val 406 drivers/gpu/drm/armada/armada_crtc.c val |= CFG_INV_VSYNC; val 407 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_mod(regs, i, val, CFG_INV_CSYNC | CFG_INV_HSYNC | val 553 drivers/gpu/drm/armada/armada_crtc.c uint32_t val = *p; val 562 drivers/gpu/drm/armada/armada_crtc.c val = (val & 0xff00ff00) | val 563 drivers/gpu/drm/armada/armada_crtc.c (val & 0x000000ff) << 16 | val 564 drivers/gpu/drm/armada/armada_crtc.c (val & 0x00ff0000) >> 16; val 566 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(val, val 15 drivers/gpu/drm/armada/armada_crtc.h uint32_t val; val 23 drivers/gpu/drm/armada/armada_crtc.h __reg[_i].val = _v; \ val 55 drivers/gpu/drm/armada/armada_debugfs.c unsigned long reg, mask, val; val 71 drivers/gpu/drm/armada/armada_debugfs.c if (sscanf(buf, "%lx %lx %lx", ®, &mask, &val) != 3) val 79 drivers/gpu/drm/armada/armada_debugfs.c v |= val & mask; val 22 drivers/gpu/drm/armada/armada_drm.h armada_updatel(uint32_t val, uint32_t mask, void __iomem *ptr) val 27 drivers/gpu/drm/armada/armada_drm.h v = (v & ~mask) | val; val 75 drivers/gpu/drm/armada/armada_overlay.c u32 cfg, cfg_mask, val; val 96 drivers/gpu/drm/armada/armada_overlay.c val = armada_src_hw(state); val 97 drivers/gpu/drm/armada/armada_overlay.c if (armada_src_hw(old_state) != val) val 98 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); val 99 drivers/gpu/drm/armada/armada_overlay.c val = armada_dst_yx(state); val 100 drivers/gpu/drm/armada/armada_overlay.c if (armada_dst_yx(old_state) != val) val 101 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); val 102 drivers/gpu/drm/armada/armada_overlay.c val = armada_dst_hw(state); val 103 drivers/gpu/drm/armada/armada_overlay.c if (armada_dst_hw(old_state) != val) val 104 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); val 126 drivers/gpu/drm/armada/armada_overlay.c val = armada_pitch(state, 0) << 16 | armada_pitch(state, 0); val 127 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC); val 128 drivers/gpu/drm/armada/armada_overlay.c val = armada_pitch(state, 1) << 16 | armada_pitch(state, 2); val 129 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV); val 171 drivers/gpu/drm/armada/armada_overlay.c val = armada_spu_contrast(state); val 173 drivers/gpu/drm/armada/armada_overlay.c armada_spu_contrast(old_state) != val) val 174 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST); val 175 drivers/gpu/drm/armada/armada_overlay.c val = armada_spu_saturation(state); val 177 drivers/gpu/drm/armada/armada_overlay.c armada_spu_saturation(old_state) != val) val 178 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION); val 181 drivers/gpu/drm/armada/armada_overlay.c val = armada_csc(state); val 183 drivers/gpu/drm/armada/armada_overlay.c armada_csc(old_state) != val) val 184 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK, val 186 drivers/gpu/drm/armada/armada_overlay.c val = drm_to_overlay_state(state)->colorkey_yr; val 188 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(old_state)->colorkey_yr != val) val 189 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y); val 190 drivers/gpu/drm/armada/armada_overlay.c val = drm_to_overlay_state(state)->colorkey_ug; val 192 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(old_state)->colorkey_ug != val) val 193 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U); val 194 drivers/gpu/drm/armada/armada_overlay.c val = drm_to_overlay_state(state)->colorkey_vb; val 196 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(old_state)->colorkey_vb != val) val 197 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V); val 198 drivers/gpu/drm/armada/armada_overlay.c val = drm_to_overlay_state(state)->colorkey_mode; val 200 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(old_state)->colorkey_mode != val) val 201 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK | val 204 drivers/gpu/drm/armada/armada_overlay.c val = drm_to_overlay_state(state)->colorkey_enable; val 206 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(old_state)->colorkey_enable != val) && val 208 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY | val 345 drivers/gpu/drm/armada/armada_overlay.c uint64_t val) val 349 drivers/gpu/drm/armada/armada_overlay.c #define K2R(val) (((val) >> 0) & 0xff) val 350 drivers/gpu/drm/armada/armada_overlay.c #define K2G(val) (((val) >> 8) & 0xff) val 351 drivers/gpu/drm/armada/armada_overlay.c #define K2B(val) (((val) >> 16) & 0xff) val 354 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val)); val 355 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val)); val 356 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val)); val 360 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16; val 362 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16; val 364 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16; val 367 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24; val 369 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24; val 371 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24; val 374 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8; val 376 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8; val 378 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8; val 381 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_yr |= K2R(val); val 383 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_ug |= K2G(val); val 385 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->colorkey_vb |= K2B(val); val 387 drivers/gpu/drm/armada/armada_overlay.c if (val == CKMODE_DISABLE) { val 394 drivers/gpu/drm/armada/armada_overlay.c CFG_CKMODE(val) | val 400 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->brightness = val - 256; val 402 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->contrast = val; val 404 drivers/gpu/drm/armada/armada_overlay.c drm_to_overlay_state(state)->saturation = val; val 413 drivers/gpu/drm/armada/armada_overlay.c uint64_t *val) val 421 drivers/gpu/drm/armada/armada_overlay.c *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, val 425 drivers/gpu/drm/armada/armada_overlay.c if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, val 428 drivers/gpu/drm/armada/armada_overlay.c *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, val 433 drivers/gpu/drm/armada/armada_overlay.c *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, val 437 drivers/gpu/drm/armada/armada_overlay.c *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, val 441 drivers/gpu/drm/armada/armada_overlay.c *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, val 445 drivers/gpu/drm/armada/armada_overlay.c *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, val 449 drivers/gpu/drm/armada/armada_overlay.c *val = (drm_to_overlay_state(state)->colorkey_mode & val 452 drivers/gpu/drm/armada/armada_overlay.c *val = drm_to_overlay_state(state)->brightness + 256; val 454 drivers/gpu/drm/armada/armada_overlay.c *val = drm_to_overlay_state(state)->contrast; val 456 drivers/gpu/drm/armada/armada_overlay.c *val = drm_to_overlay_state(state)->saturation; val 164 drivers/gpu/drm/armada/armada_plane.c u32 cfg, cfg_mask, val; val 183 drivers/gpu/drm/armada/armada_plane.c val = CFG_PDWN64x66; val 185 drivers/gpu/drm/armada/armada_plane.c val |= CFG_PDWN256x24; val 186 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1); val 188 drivers/gpu/drm/armada/armada_plane.c val = armada_src_hw(state); val 189 drivers/gpu/drm/armada/armada_plane.c if (armada_src_hw(old_state) != val) val 190 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN); val 191 drivers/gpu/drm/armada/armada_plane.c val = armada_dst_yx(state); val 192 drivers/gpu/drm/armada/armada_plane.c if (armada_dst_yx(old_state) != val) val 193 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN); val 194 drivers/gpu/drm/armada/armada_plane.c val = armada_dst_hw(state); val 195 drivers/gpu/drm/armada/armada_plane.c if (armada_dst_hw(old_state) != val) val 196 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN); val 136 drivers/gpu/drm/ast/ast_drv.h u##x val = 0;\ val 137 drivers/gpu/drm/ast/ast_drv.h val = ioread##x(ast->regs + reg); \ val 138 drivers/gpu/drm/ast/ast_drv.h return val;\ val 147 drivers/gpu/drm/ast/ast_drv.h u##x val = 0;\ val 148 drivers/gpu/drm/ast/ast_drv.h val = ioread##x(ast->ioregs + reg); \ val 149 drivers/gpu/drm/ast/ast_drv.h return val;\ val 157 drivers/gpu/drm/ast/ast_drv.h static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ val 158 drivers/gpu/drm/ast/ast_drv.h iowrite##x(val, ast->regs + reg);\ val 166 drivers/gpu/drm/ast/ast_drv.h static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ val 167 drivers/gpu/drm/ast/ast_drv.h iowrite##x(val, ast->ioregs + reg);\ val 176 drivers/gpu/drm/ast/ast_drv.h uint8_t val) val 178 drivers/gpu/drm/ast/ast_drv.h ast_io_write16(ast, base, ((u16)val << 8) | index); val 183 drivers/gpu/drm/ast/ast_drv.h uint8_t mask, uint8_t val); val 42 drivers/gpu/drm/ast/ast_main.c uint8_t mask, uint8_t val) val 46 drivers/gpu/drm/ast/ast_main.c tmp = (ast_io_read8(ast, base + 1) & mask) | val; val 962 drivers/gpu/drm/ast/ast_mode.c uint32_t val, val2, count, pass; val 966 drivers/gpu/drm/ast/ast_mode.c val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; val 969 drivers/gpu/drm/ast/ast_mode.c if (val == val2) { val 973 drivers/gpu/drm/ast/ast_mode.c val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; val 977 drivers/gpu/drm/ast/ast_mode.c return val & 1 ? 1 : 0; val 984 drivers/gpu/drm/ast/ast_mode.c uint32_t val, val2, count, pass; val 988 drivers/gpu/drm/ast/ast_mode.c val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; val 991 drivers/gpu/drm/ast/ast_mode.c if (val == val2) { val 995 drivers/gpu/drm/ast/ast_mode.c val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; val 999 drivers/gpu/drm/ast/ast_mode.c return val & 1 ? 1 : 0; val 172 drivers/gpu/drm/ati_pcigart.c u32 val; val 176 drivers/gpu/drm/ati_pcigart.c val = page_base | 0xc; val 179 drivers/gpu/drm/ati_pcigart.c val = (page_base >> 8) | 0xc; val 183 drivers/gpu/drm/ati_pcigart.c val = page_base; val 188 drivers/gpu/drm/ati_pcigart.c pci_gart[gart_idx] = cpu_to_le32(val); val 191 drivers/gpu/drm/ati_pcigart.c writel(val, (void __iomem *)map->handle + offset); val 359 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h unsigned int reg, u32 val) val 361 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h regmap_write(layer->regmap, layer->desc->regs_offset + reg, val); val 367 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h u32 val; val 369 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val); val 371 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h return val; val 375 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h unsigned int cfgid, u32 val) val 379 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h (cfgid * sizeof(u32)), val); val 391 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h unsigned int c, u32 val) val 395 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h val); val 430 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c u32 val = ((lut->red << 8) & 0xff0000) | val 434 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_clut(&plane->layer, idx, val); val 13 drivers/gpu/drm/bochs/bochs_hw.c static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val) val 20 drivers/gpu/drm/bochs/bochs_hw.c writeb(val, bochs->mmio + offset); val 22 drivers/gpu/drm/bochs/bochs_hw.c outb(val, ioport); val 40 drivers/gpu/drm/bochs/bochs_hw.c static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val) val 44 drivers/gpu/drm/bochs/bochs_hw.c writew(val, bochs->mmio + offset); val 47 drivers/gpu/drm/bochs/bochs_hw.c outw(val, VBE_DISPI_IOPORT_DATA); val 39 drivers/gpu/drm/bridge/adv7511/adv7511_cec.c unsigned int val; val 42 drivers/gpu/drm/bridge/adv7511/adv7511_cec.c ADV7511_REG_CEC_TX_ENABLE + offset, &val)) val 45 drivers/gpu/drm/bridge/adv7511/adv7511_cec.c if ((val & 0x01) == 0) val 96 drivers/gpu/drm/bridge/adv7511/adv7511_cec.c unsigned int val; val 119 drivers/gpu/drm/bridge/adv7511/adv7511_cec.c i + ADV7511_REG_CEC_RX_FRAME_HDR + offset, &val); val 120 drivers/gpu/drm/bridge/adv7511/adv7511_cec.c msg.msg[i] = val; val 421 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c unsigned int val; val 424 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val); val 427 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c else if (val & ADV7511_STATUS_HPD) val 633 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c unsigned int val; val 637 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val); val 641 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c if (val & ADV7511_STATUS_HPD) val 1097 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c unsigned int val; val 1152 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c ret = regmap_read(adv7511->regmap, ADV7511_REG_CHIP_REVISION, &val); val 1155 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c dev_dbg(dev, "Rev. %d\n", val); val 1028 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c ssize_t val; val 1031 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status); val 1032 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (val < 0) { val 1033 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val); val 1034 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c return val; val 1042 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c unsigned int val; val 1047 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); val 1048 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val &= ~IF_EN; val 1049 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); val 1072 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); val 1073 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val |= REUSE_SPD_EN; val 1074 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); val 1077 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); val 1078 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = (val | IF_UP) & ~IF_EN; val 1079 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); val 1082 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); val 1083 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val |= IF_EN; val 1084 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); val 154 drivers/gpu/drm/bridge/cdns-dsi.c #define DATA_LANE_STATE(l, val) \ val 155 drivers/gpu/drm/bridge/cdns-dsi.c (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0)) val 157 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0)) val 211 drivers/gpu/drm/bridge/cdns-dsi.c #define RCVD_ACK_VAL(val) ((val) >> 16) val 212 drivers/gpu/drm/bridge/cdns-dsi.c #define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11) val 235 drivers/gpu/drm/bridge/cdns-dsi.c #define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0)) val 236 drivers/gpu/drm/bridge/cdns-dsi.c #define RD_SIZE(val) ((val) & GENMASK(15, 0)) val 324 drivers/gpu/drm/bridge/cdns-dsi.c #define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2) val 325 drivers/gpu/drm/bridge/cdns-dsi.c #define LINE_POS(val) ((val) & GENMASK(1, 0)) val 328 drivers/gpu/drm/bridge/cdns-dsi.c #define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3) val 329 drivers/gpu/drm/bridge/cdns-dsi.c #define HORIZ_POS(val) ((val) & GENMASK(2, 0)) val 700 drivers/gpu/drm/bridge/cdns-dsi.c u32 val; val 702 drivers/gpu/drm/bridge/cdns-dsi.c val = readl(dsi->regs + MCTL_MAIN_DATA_CTL); val 703 drivers/gpu/drm/bridge/cdns-dsi.c val &= ~(IF_VID_SELECT_MASK | IF_VID_MODE | VID_EN | HOST_EOT_GEN | val 705 drivers/gpu/drm/bridge/cdns-dsi.c writel(val, dsi->regs + MCTL_MAIN_DATA_CTL); val 707 drivers/gpu/drm/bridge/cdns-dsi.c val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id); val 708 drivers/gpu/drm/bridge/cdns-dsi.c writel(val, dsi->regs + MCTL_MAIN_EN); val 746 drivers/gpu/drm/bridge/cdns-dsi.c u32 val; val 752 drivers/gpu/drm/bridge/cdns-dsi.c val = 0; val 754 drivers/gpu/drm/bridge/cdns-dsi.c val |= DATA_LANE_EN(i); val 757 drivers/gpu/drm/bridge/cdns-dsi.c val |= CLK_CONTINUOUS; val 759 drivers/gpu/drm/bridge/cdns-dsi.c writel(val, dsi->regs + MCTL_MAIN_PHY_CTL); val 769 drivers/gpu/drm/bridge/cdns-dsi.c val = CLK_LANE_EN | PLL_START; val 771 drivers/gpu/drm/bridge/cdns-dsi.c val |= DATA_LANE_START(i); val 773 drivers/gpu/drm/bridge/cdns-dsi.c writel(val, dsi->regs + MCTL_MAIN_EN); val 1025 drivers/gpu/drm/bridge/cdns-dsi.c u32 cmd, sts, val, wait = WRITE_COMPLETED, ctl = 0; val 1088 drivers/gpu/drm/bridge/cdns-dsi.c val = 0; val 1090 drivers/gpu/drm/bridge/cdns-dsi.c val |= (u32)buf[i + j] << (8 * j); val 1092 drivers/gpu/drm/bridge/cdns-dsi.c writel(val, dsi->regs + DIRECT_CMD_WRDATA); val 1127 drivers/gpu/drm/bridge/cdns-dsi.c val = readl(dsi->regs + DIRECT_CMD_RDDATA); val 1129 drivers/gpu/drm/bridge/cdns-dsi.c buf[i + j] = val >> (8 * j); val 1174 drivers/gpu/drm/bridge/cdns-dsi.c u32 val; val 1214 drivers/gpu/drm/bridge/cdns-dsi.c val = readl(dsi->regs + ID_REG); val 1215 drivers/gpu/drm/bridge/cdns-dsi.c if (REV_VENDOR_ID(val) != 0xcad) { val 1221 drivers/gpu/drm/bridge/cdns-dsi.c val = readl(dsi->regs + IP_CONF); val 1222 drivers/gpu/drm/bridge/cdns-dsi.c dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2); val 1223 drivers/gpu/drm/bridge/cdns-dsi.c dsi->rx_fifo_depth = RX_FIFO_DEPTH(val); val 72 drivers/gpu/drm/bridge/nxp-ptn3460.c char val) val 78 drivers/gpu/drm/bridge/nxp-ptn3460.c buf[1] = val; val 92 drivers/gpu/drm/bridge/nxp-ptn3460.c char val; val 103 drivers/gpu/drm/bridge/nxp-ptn3460.c val = 1 << PTN3460_EDID_ENABLE_EMULATION | val 106 drivers/gpu/drm/bridge/nxp-ptn3460.c ret = ptn3460_write_byte(ptn_bridge, PTN3460_EDID_EMULATION_ADDR, val); val 72 drivers/gpu/drm/bridge/parade-ps8622.c static int ps8622_set(struct i2c_client *client, u8 page, u8 reg, u8 val) val 77 drivers/gpu/drm/bridge/parade-ps8622.c u8 data[] = {reg, val}; val 87 drivers/gpu/drm/bridge/parade-ps8622.c client->addr + page, reg, val, ret); val 182 drivers/gpu/drm/bridge/sii902x.c static int sii902x_read_unlocked(struct i2c_client *i2c, u8 reg, u8 *val) val 193 drivers/gpu/drm/bridge/sii902x.c *val = data.byte; val 197 drivers/gpu/drm/bridge/sii902x.c static int sii902x_write_unlocked(struct i2c_client *i2c, u8 reg, u8 val) val 201 drivers/gpu/drm/bridge/sii902x.c data.byte = val; val 209 drivers/gpu/drm/bridge/sii902x.c u8 val) val 218 drivers/gpu/drm/bridge/sii902x.c status |= val & mask; val 442 drivers/gpu/drm/bridge/sii902x.c unsigned int val = mute ? SII902X_TPI_AUDIO_MUTE_ENABLE : val 449 drivers/gpu/drm/bridge/sii902x.c SII902X_TPI_AUDIO_MUTE_ENABLE, val); val 481 drivers/gpu/drm/bridge/sii902x.c u8 val; val 483 drivers/gpu/drm/bridge/sii902x.c { .freq = 32000, .val = SII902X_TPI_AUDIO_FREQ_32KHZ }, val 484 drivers/gpu/drm/bridge/sii902x.c { .freq = 44000, .val = SII902X_TPI_AUDIO_FREQ_44KHZ }, val 485 drivers/gpu/drm/bridge/sii902x.c { .freq = 48000, .val = SII902X_TPI_AUDIO_FREQ_48KHZ }, val 486 drivers/gpu/drm/bridge/sii902x.c { .freq = 88000, .val = SII902X_TPI_AUDIO_FREQ_88KHZ }, val 487 drivers/gpu/drm/bridge/sii902x.c { .freq = 96000, .val = SII902X_TPI_AUDIO_FREQ_96KHZ }, val 488 drivers/gpu/drm/bridge/sii902x.c { .freq = 176000, .val = SII902X_TPI_AUDIO_FREQ_176KHZ }, val 489 drivers/gpu/drm/bridge/sii902x.c { .freq = 192000, .val = SII902X_TPI_AUDIO_FREQ_192KHZ }, val 562 drivers/gpu/drm/bridge/sii902x.c config_byte3_reg |= sii902x_sample_freq[i].val; val 255 drivers/gpu/drm/bridge/sil-sii8620.c static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) val 257 drivers/gpu/drm/bridge/sil-sii8620.c val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); val 258 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_write(ctx, addr, val); val 424 drivers/gpu/drm/bridge/sil-sii8620.c static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) val 426 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); val 988 drivers/gpu/drm/bridge/sil-sii8620.c u8 uninitialized_var(val); val 999 drivers/gpu/drm/bridge/sil-sii8620.c val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN val 1004 drivers/gpu/drm/bridge/sil-sii8620.c val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN val 1010 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_write(ctx, REG_TPI_SC, val); val 135 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c static void dw_hdmi_writel(u32 val, void __iomem *ptr) val 137 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(val, ptr); val 138 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(val >> 8, ptr + 1); val 139 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(val >> 16, ptr + 2); val 140 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(val >> 24, ptr + 3); val 19 drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); val 67 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c static void dw_hdmi_write(struct dw_hdmi_cec *cec, u8 val, int offset) val 69 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c cec->ops->write(cec->hdmi, val, offset); val 7 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.h void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); val 23 drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c u8 val, int offset) val 27 drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c audio->write(hdmi, val, offset); val 205 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) val 207 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); val 212 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c unsigned int val = 0; val 214 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); val 216 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c return val; val 844 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u8 val; val 891 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | val 894 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_TX_INVID0); val 897 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | val 900 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); val 1029 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u8 val, vp_conf; val 1075 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & val 1080 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); val 1145 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u32 val; val 1147 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { val 1152 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); val 1299 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u16 val; val 1314 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = hdmi_readb(hdmi, HDMI_PHY_STAT0); val 1315 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!(val & HDMI_PHY_TX_PHY_LOCK)) val 1321 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (val & HDMI_PHY_TX_PHY_LOCK) val 1333 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u8 val; val 1349 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; val 1350 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (val) val 1356 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!val) { val 1563 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u8 val; val 1622 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); val 1624 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; val 1626 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; val 1628 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; val 1629 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); val 1632 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = ((frame.colorimetry & 0x3) << 6) | val 1635 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); val 1638 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = ((frame.extended_colorimetry & 0x7) << 4) | val 1642 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; val 1643 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); val 1646 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = frame.video_code & 0x7f; val 1647 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); val 1650 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << val 1656 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); val 1662 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = ((frame.ycc_quantization_range & 0x3) << 2) | val 1664 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); val 1930 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u8 val; val 1968 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); val 1970 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); val 2621 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u32 val = 1; val 2660 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c of_property_read_u32(np, "reg-io-width", &val); val 2661 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c switch (val) { val 283 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) val 285 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c writel(val, dsi->base + reg); val 361 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c u32 val = 0; val 364 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= ACK_RQST_EN; val 366 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= CMD_MODE_ALL_LP; val 369 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c dsi_write(dsi, DSI_CMD_MODE_CFG, val); val 375 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c u32 val, mask; val 378 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val, !(val & GEN_CMD_FULL), 1000, val 389 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val, (val & mask) == mask, val 405 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c u32 val; val 421 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val, !(val & GEN_PLD_W_FULL), 1000, val 440 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c u32 val; val 444 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val, !(val & GEN_RD_CMD_BUSY), val 454 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val, !(val & GEN_PLD_R_EMPTY), val 461 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val = dsi_read(dsi, DSI_GEN_PLD_DATA); val 463 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c buf[i + j] = val >> (8 * j); val 515 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c u32 val; val 522 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val = ENABLE_LOW_POWER; val 525 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= VID_MODE_TYPE_BURST; val 527 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; val 529 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; val 533 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= VID_MODE_VPG_ENABLE; val 534 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0; val 538 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c dsi_write(dsi, DSI_VID_MODE_CFG, val); val 589 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c u32 val = 0, color = 0; val 607 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= VSYNC_ACTIVE_LOW; val 609 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val |= HSYNC_ACTIVE_LOW; val 613 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c dsi_write(dsi, DSI_DPI_CFG_POL, val); val 769 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c u32 val; val 775 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, val 776 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); val 781 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val, val & PHY_STOP_STATE_CLK_LANE, 1000, val 28 drivers/gpu/drm/bridge/tc358764.c #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) val 170 drivers/gpu/drm/bridge/tc358764.c static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val) val 179 drivers/gpu/drm/bridge/tc358764.c ret = mipi_dsi_generic_read(dsi, &addr, sizeof(addr), val, sizeof(*val)); val 181 drivers/gpu/drm/bridge/tc358764.c le32_to_cpus(val); val 183 drivers/gpu/drm/bridge/tc358764.c dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val); val 186 drivers/gpu/drm/bridge/tc358764.c static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val) val 197 drivers/gpu/drm/bridge/tc358764.c data[2] = val; val 198 drivers/gpu/drm/bridge/tc358764.c data[3] = val >> 8; val 199 drivers/gpu/drm/bridge/tc358764.c data[4] = val >> 16; val 200 drivers/gpu/drm/bridge/tc358764.c data[5] = val >> 24; val 288 drivers/gpu/drm/bridge/tc358767.c unsigned int val; val 290 drivers/gpu/drm/bridge/tc358767.c return regmap_read_poll_timeout(tc->regmap, addr, val, val 291 drivers/gpu/drm/bridge/tc358767.c (val & cond_mask) == cond_value, val 1355 drivers/gpu/drm/bridge/tc358767.c u32 val; val 1365 drivers/gpu/drm/bridge/tc358767.c ret = regmap_read(tc->regmap, GPIOI, &val); val 1369 drivers/gpu/drm/bridge/tc358767.c conn = val & BIT(tc->hpd_pin); val 1479 drivers/gpu/drm/bridge/tc358767.c u32 val; val 1482 drivers/gpu/drm/bridge/tc358767.c r = regmap_read(tc->regmap, INTSTS_G, &val); val 1486 drivers/gpu/drm/bridge/tc358767.c if (!val) val 1489 drivers/gpu/drm/bridge/tc358767.c if (val & INT_SYSERR) { val 1504 drivers/gpu/drm/bridge/tc358767.c bool h = val & INT_GPIO_H(tc->hpd_pin); val 1505 drivers/gpu/drm/bridge/tc358767.c bool lc = val & INT_GPIO_LC(tc->hpd_pin); val 1514 drivers/gpu/drm/bridge/tc358767.c regmap_write(tc->regmap, INTSTS_G, val); val 121 drivers/gpu/drm/bridge/ti-sn65dsi86.c unsigned int reg, u16 val) val 123 drivers/gpu/drm/bridge/ti-sn65dsi86.c regmap_write(pdata->regmap, reg, val & 0xFF); val 124 drivers/gpu/drm/bridge/ti-sn65dsi86.c regmap_write(pdata->regmap, reg + 1, val >> 8); val 164 drivers/gpu/drm/bridge/ti-sn65dsi86.c unsigned int reg, val; val 172 drivers/gpu/drm/bridge/ti-sn65dsi86.c regmap_read(pdata->regmap, reg, &val); val 173 drivers/gpu/drm/bridge/ti-sn65dsi86.c seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); val 268 drivers/gpu/drm/bridge/ti-sn65dsi86.c int ret, val; val 321 drivers/gpu/drm/bridge/ti-sn65dsi86.c regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); val 323 drivers/gpu/drm/bridge/ti-sn65dsi86.c if (!(val & DPPLL_CLK_SRC_DSICLK)) val 431 drivers/gpu/drm/bridge/ti-sn65dsi86.c unsigned int val, i; val 441 drivers/gpu/drm/bridge/ti-sn65dsi86.c val = (MIN_DSI_CLK_FREQ_MHZ / 5) + val 443 drivers/gpu/drm/bridge/ti-sn65dsi86.c regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); val 498 drivers/gpu/drm/bridge/ti-sn65dsi86.c unsigned int val; val 502 drivers/gpu/drm/bridge/ti-sn65dsi86.c val = CHA_DSI_LANES(4 - pdata->dsi->lanes); val 504 drivers/gpu/drm/bridge/ti-sn65dsi86.c CHA_DSI_LANES_MASK, val); val 507 drivers/gpu/drm/bridge/ti-sn65dsi86.c val = DP_NUM_LANES(pdata->dsi->lanes - 1); val 509 drivers/gpu/drm/bridge/ti-sn65dsi86.c val); val 517 drivers/gpu/drm/bridge/ti-sn65dsi86.c ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, val 518 drivers/gpu/drm/bridge/ti-sn65dsi86.c val & DPPLL_SRC_DP_PLL_LOCK, 1000, val 536 drivers/gpu/drm/bridge/ti-sn65dsi86.c ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, val 537 drivers/gpu/drm/bridge/ti-sn65dsi86.c val == ML_TX_MAIN_LINK_OFF || val 538 drivers/gpu/drm/bridge/ti-sn65dsi86.c val == ML_TX_NORMAL_MODE, 1000, val 543 drivers/gpu/drm/bridge/ti-sn65dsi86.c } else if (val == ML_TX_MAIN_LINK_OFF) { val 619 drivers/gpu/drm/bridge/ti-sn65dsi86.c unsigned int val; val 652 drivers/gpu/drm/bridge/ti-sn65dsi86.c ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, val 653 drivers/gpu/drm/bridge/ti-sn65dsi86.c !(val & AUX_CMD_SEND), 200, val 658 drivers/gpu/drm/bridge/ti-sn65dsi86.c ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); val 661 drivers/gpu/drm/bridge/ti-sn65dsi86.c else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL) val 662 drivers/gpu/drm/bridge/ti-sn65dsi86.c || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) val 663 drivers/gpu/drm/bridge/ti-sn65dsi86.c || (val & AUX_IRQ_STATUS_AUX_SHORT)) val 670 drivers/gpu/drm/bridge/ti-sn65dsi86.c unsigned int val; val 672 drivers/gpu/drm/bridge/ti-sn65dsi86.c &val); val 676 drivers/gpu/drm/bridge/ti-sn65dsi86.c WARN_ON(val & ~0xFF); val 677 drivers/gpu/drm/bridge/ti-sn65dsi86.c buf[i] = (u8)(val & 0xFF); val 81 drivers/gpu/drm/cirrus/cirrus.c static void wreg_seq(struct cirrus_device *cirrus, u8 reg, u8 val) val 84 drivers/gpu/drm/cirrus/cirrus.c iowrite8(val, cirrus->mmio + SEQ_DATA); val 96 drivers/gpu/drm/cirrus/cirrus.c static void wreg_crt(struct cirrus_device *cirrus, u8 reg, u8 val) val 99 drivers/gpu/drm/cirrus/cirrus.c iowrite8(val, cirrus->mmio + CRT_DATA); val 105 drivers/gpu/drm/cirrus/cirrus.c static void wreg_gfx(struct cirrus_device *cirrus, u8 reg, u8 val) val 108 drivers/gpu/drm/cirrus/cirrus.c iowrite8(val, cirrus->mmio + GFX_DATA); val 113 drivers/gpu/drm/cirrus/cirrus.c static void wreg_hdr(struct cirrus_device *cirrus, u8 val) val 119 drivers/gpu/drm/cirrus/cirrus.c iowrite8(val, cirrus->mmio + VGA_DAC_MASK); val 421 drivers/gpu/drm/drm_atomic_uapi.c uint64_t val) val 429 drivers/gpu/drm/drm_atomic_uapi.c state->active = val; val 432 drivers/gpu/drm/drm_atomic_uapi.c drm_property_lookup_blob(dev, val); val 437 drivers/gpu/drm/drm_atomic_uapi.c state->vrr_enabled = val; val 441 drivers/gpu/drm/drm_atomic_uapi.c val, val 449 drivers/gpu/drm/drm_atomic_uapi.c val, val 457 drivers/gpu/drm/drm_atomic_uapi.c val, val 463 drivers/gpu/drm/drm_atomic_uapi.c s32 __user *fence_ptr = u64_to_user_ptr(val); val 473 drivers/gpu/drm/drm_atomic_uapi.c return crtc->funcs->atomic_set_property(crtc, state, property, val); val 487 drivers/gpu/drm/drm_atomic_uapi.c struct drm_property *property, uint64_t *val) val 493 drivers/gpu/drm/drm_atomic_uapi.c *val = drm_atomic_crtc_effectively_active(state); val 495 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->mode_blob) ? state->mode_blob->base.id : 0; val 497 drivers/gpu/drm/drm_atomic_uapi.c *val = state->vrr_enabled; val 499 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; val 501 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->ctm) ? state->ctm->base.id : 0; val 503 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; val 505 drivers/gpu/drm/drm_atomic_uapi.c *val = 0; val 507 drivers/gpu/drm/drm_atomic_uapi.c return crtc->funcs->atomic_get_property(crtc, state, property, val); val 516 drivers/gpu/drm/drm_atomic_uapi.c struct drm_property *property, uint64_t val) val 525 drivers/gpu/drm/drm_atomic_uapi.c fb = drm_framebuffer_lookup(dev, file_priv, val); val 533 drivers/gpu/drm/drm_atomic_uapi.c if (U642I64(val) == -1) val 536 drivers/gpu/drm/drm_atomic_uapi.c state->fence = sync_file_get_fence(val); val 541 drivers/gpu/drm/drm_atomic_uapi.c struct drm_crtc *crtc = drm_crtc_find(dev, file_priv, val); val 542 drivers/gpu/drm/drm_atomic_uapi.c if (val && !crtc) val 546 drivers/gpu/drm/drm_atomic_uapi.c state->crtc_x = U642I64(val); val 548 drivers/gpu/drm/drm_atomic_uapi.c state->crtc_y = U642I64(val); val 550 drivers/gpu/drm/drm_atomic_uapi.c state->crtc_w = val; val 552 drivers/gpu/drm/drm_atomic_uapi.c state->crtc_h = val; val 554 drivers/gpu/drm/drm_atomic_uapi.c state->src_x = val; val 556 drivers/gpu/drm/drm_atomic_uapi.c state->src_y = val; val 558 drivers/gpu/drm/drm_atomic_uapi.c state->src_w = val; val 560 drivers/gpu/drm/drm_atomic_uapi.c state->src_h = val; val 562 drivers/gpu/drm/drm_atomic_uapi.c state->alpha = val; val 564 drivers/gpu/drm/drm_atomic_uapi.c state->pixel_blend_mode = val; val 566 drivers/gpu/drm/drm_atomic_uapi.c if (!is_power_of_2(val & DRM_MODE_ROTATE_MASK)) { val 568 drivers/gpu/drm/drm_atomic_uapi.c plane->base.id, plane->name, val); val 571 drivers/gpu/drm/drm_atomic_uapi.c state->rotation = val; val 573 drivers/gpu/drm/drm_atomic_uapi.c state->zpos = val; val 575 drivers/gpu/drm/drm_atomic_uapi.c state->color_encoding = val; val 577 drivers/gpu/drm/drm_atomic_uapi.c state->color_range = val; val 581 drivers/gpu/drm/drm_atomic_uapi.c val, val 588 drivers/gpu/drm/drm_atomic_uapi.c property, val); val 602 drivers/gpu/drm/drm_atomic_uapi.c struct drm_property *property, uint64_t *val) val 608 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->fb) ? state->fb->base.id : 0; val 610 drivers/gpu/drm/drm_atomic_uapi.c *val = -1; val 612 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->crtc) ? state->crtc->base.id : 0; val 614 drivers/gpu/drm/drm_atomic_uapi.c *val = I642U64(state->crtc_x); val 616 drivers/gpu/drm/drm_atomic_uapi.c *val = I642U64(state->crtc_y); val 618 drivers/gpu/drm/drm_atomic_uapi.c *val = state->crtc_w; val 620 drivers/gpu/drm/drm_atomic_uapi.c *val = state->crtc_h; val 622 drivers/gpu/drm/drm_atomic_uapi.c *val = state->src_x; val 624 drivers/gpu/drm/drm_atomic_uapi.c *val = state->src_y; val 626 drivers/gpu/drm/drm_atomic_uapi.c *val = state->src_w; val 628 drivers/gpu/drm/drm_atomic_uapi.c *val = state->src_h; val 630 drivers/gpu/drm/drm_atomic_uapi.c *val = state->alpha; val 632 drivers/gpu/drm/drm_atomic_uapi.c *val = state->pixel_blend_mode; val 634 drivers/gpu/drm/drm_atomic_uapi.c *val = state->rotation; val 636 drivers/gpu/drm/drm_atomic_uapi.c *val = state->zpos; val 638 drivers/gpu/drm/drm_atomic_uapi.c *val = state->color_encoding; val 640 drivers/gpu/drm/drm_atomic_uapi.c *val = state->color_range; val 642 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->fb_damage_clips) ? val 645 drivers/gpu/drm/drm_atomic_uapi.c return plane->funcs->atomic_get_property(plane, state, property, val); val 675 drivers/gpu/drm/drm_atomic_uapi.c struct drm_property *property, uint64_t val) val 683 drivers/gpu/drm/drm_atomic_uapi.c struct drm_crtc *crtc = drm_crtc_find(dev, file_priv, val); val 684 drivers/gpu/drm/drm_atomic_uapi.c if (val && !crtc) val 694 drivers/gpu/drm/drm_atomic_uapi.c state->tv.subconnector = val; val 696 drivers/gpu/drm/drm_atomic_uapi.c state->tv.margins.left = val; val 698 drivers/gpu/drm/drm_atomic_uapi.c state->tv.margins.right = val; val 700 drivers/gpu/drm/drm_atomic_uapi.c state->tv.margins.top = val; val 702 drivers/gpu/drm/drm_atomic_uapi.c state->tv.margins.bottom = val; val 704 drivers/gpu/drm/drm_atomic_uapi.c state->tv.mode = val; val 706 drivers/gpu/drm/drm_atomic_uapi.c state->tv.brightness = val; val 708 drivers/gpu/drm/drm_atomic_uapi.c state->tv.contrast = val; val 710 drivers/gpu/drm/drm_atomic_uapi.c state->tv.flicker_reduction = val; val 712 drivers/gpu/drm/drm_atomic_uapi.c state->tv.overscan = val; val 714 drivers/gpu/drm/drm_atomic_uapi.c state->tv.saturation = val; val 716 drivers/gpu/drm/drm_atomic_uapi.c state->tv.hue = val; val 730 drivers/gpu/drm/drm_atomic_uapi.c state->link_status = val; val 734 drivers/gpu/drm/drm_atomic_uapi.c val, val 739 drivers/gpu/drm/drm_atomic_uapi.c state->picture_aspect_ratio = val; val 741 drivers/gpu/drm/drm_atomic_uapi.c state->content_type = val; val 743 drivers/gpu/drm/drm_atomic_uapi.c state->scaling_mode = val; val 745 drivers/gpu/drm/drm_atomic_uapi.c if (val == DRM_MODE_CONTENT_PROTECTION_ENABLED) { val 749 drivers/gpu/drm/drm_atomic_uapi.c state->content_protection = val; val 751 drivers/gpu/drm/drm_atomic_uapi.c state->hdcp_content_type = val; val 753 drivers/gpu/drm/drm_atomic_uapi.c state->colorspace = val; val 757 drivers/gpu/drm/drm_atomic_uapi.c fb = drm_framebuffer_lookup(dev, file_priv, val); val 763 drivers/gpu/drm/drm_atomic_uapi.c s32 __user *fence_ptr = u64_to_user_ptr(val); val 768 drivers/gpu/drm/drm_atomic_uapi.c state->max_requested_bpc = val; val 771 drivers/gpu/drm/drm_atomic_uapi.c state, property, val); val 785 drivers/gpu/drm/drm_atomic_uapi.c struct drm_property *property, uint64_t *val) val 791 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->crtc) ? state->crtc->base.id : 0; val 794 drivers/gpu/drm/drm_atomic_uapi.c *val = DRM_MODE_DPMS_ON; val 796 drivers/gpu/drm/drm_atomic_uapi.c *val = connector->dpms; val 798 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.subconnector; val 800 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.margins.left; val 802 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.margins.right; val 804 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.margins.top; val 806 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.margins.bottom; val 808 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.mode; val 810 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.brightness; val 812 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.contrast; val 814 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.flicker_reduction; val 816 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.overscan; val 818 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.saturation; val 820 drivers/gpu/drm/drm_atomic_uapi.c *val = state->tv.hue; val 822 drivers/gpu/drm/drm_atomic_uapi.c *val = state->link_status; val 824 drivers/gpu/drm/drm_atomic_uapi.c *val = state->picture_aspect_ratio; val 826 drivers/gpu/drm/drm_atomic_uapi.c *val = state->content_type; val 828 drivers/gpu/drm/drm_atomic_uapi.c *val = state->colorspace; val 830 drivers/gpu/drm/drm_atomic_uapi.c *val = state->scaling_mode; val 832 drivers/gpu/drm/drm_atomic_uapi.c *val = state->hdr_output_metadata ? val 835 drivers/gpu/drm/drm_atomic_uapi.c *val = state->content_protection; val 837 drivers/gpu/drm/drm_atomic_uapi.c *val = state->hdcp_content_type; val 840 drivers/gpu/drm/drm_atomic_uapi.c *val = 0; val 842 drivers/gpu/drm/drm_atomic_uapi.c *val = 0; val 844 drivers/gpu/drm/drm_atomic_uapi.c *val = state->max_requested_bpc; val 847 drivers/gpu/drm/drm_atomic_uapi.c state, property, val); val 856 drivers/gpu/drm/drm_atomic_uapi.c struct drm_property *property, uint64_t *val) val 866 drivers/gpu/drm/drm_atomic_uapi.c connector->state, property, val); val 873 drivers/gpu/drm/drm_atomic_uapi.c crtc->state, property, val); val 880 drivers/gpu/drm/drm_atomic_uapi.c plane->state, property, val); val 122 drivers/gpu/drm/drm_color_mgmt.c uint32_t val = user_input; val 127 drivers/gpu/drm/drm_color_mgmt.c val += 1UL << (16 - bit_precision - 1); val 128 drivers/gpu/drm/drm_color_mgmt.c val >>= 16 - bit_precision; val 131 drivers/gpu/drm/drm_color_mgmt.c return clamp_val(val, 0, max); val 245 drivers/gpu/drm/drm_crtc_internal.h struct drm_property *property, uint64_t *val); val 91 drivers/gpu/drm/drm_dp_cec.c u32 val = enable ? DP_CEC_TUNNELING_ENABLE : 0; val 94 drivers/gpu/drm/drm_dp_cec.c err = drm_dp_dpcd_writeb(aux, DP_CEC_TUNNELING_CONTROL, val); val 137 drivers/gpu/drm/drm_dp_cec.c u8 val; val 142 drivers/gpu/drm/drm_dp_cec.c err = drm_dp_dpcd_readb(aux, DP_CEC_TUNNELING_CONTROL, &val); val 145 drivers/gpu/drm/drm_dp_cec.c val |= DP_CEC_SNOOPING_ENABLE; val 147 drivers/gpu/drm/drm_dp_cec.c val &= ~DP_CEC_SNOOPING_ENABLE; val 148 drivers/gpu/drm/drm_dp_cec.c err = drm_dp_dpcd_writeb(aux, DP_CEC_TUNNELING_CONTROL, val); val 76 drivers/gpu/drm/drm_flip_work.c void drm_flip_work_queue(struct drm_flip_work *work, void *val) val 80 drivers/gpu/drm/drm_flip_work.c task = drm_flip_work_allocate_task(val, val 86 drivers/gpu/drm/drm_flip_work.c work->func(work, val); val 444 drivers/gpu/drm/drm_hdcp.c u64 val) val 450 drivers/gpu/drm/drm_hdcp.c if (state->content_protection == val) val 453 drivers/gpu/drm/drm_hdcp.c state->content_protection = val; val 41 drivers/gpu/drm/drm_kms_helper_common.c static int edid_firmware_set(const char *val, const struct kernel_param *kp) val 45 drivers/gpu/drm/drm_kms_helper_common.c return __drm_set_edid_firmware_path(val); val 130 drivers/gpu/drm/drm_mipi_dbi.c int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) val 138 drivers/gpu/drm/drm_mipi_dbi.c return mipi_dbi_command_buf(dbi, cmd, val, 1); val 632 drivers/gpu/drm/drm_mipi_dbi.c u8 val; val 634 drivers/gpu/drm/drm_mipi_dbi.c if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) val 637 drivers/gpu/drm/drm_mipi_dbi.c val &= ~DCS_POWER_MODE_RESERVED_MASK; val 640 drivers/gpu/drm/drm_mipi_dbi.c if (val != (DCS_POWER_MODE_DISPLAY | val 821 drivers/gpu/drm/drm_mipi_dbi.c u8 val, carry = 0; val 828 drivers/gpu/drm/drm_mipi_dbi.c val = src[1]; val 829 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = carry | BIT(8 - i) | (val >> i); val 830 drivers/gpu/drm/drm_mipi_dbi.c carry = val << (8 - i); val 832 drivers/gpu/drm/drm_mipi_dbi.c val = src[0]; val 833 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = carry | BIT(8 - i) | (val >> i); val 834 drivers/gpu/drm/drm_mipi_dbi.c carry = val << (8 - i); val 840 drivers/gpu/drm/drm_mipi_dbi.c val = *src++; val 841 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = carry | BIT(8 - i) | (val >> i); val 842 drivers/gpu/drm/drm_mipi_dbi.c carry = val << (8 - i); val 1188 drivers/gpu/drm/drm_mipi_dbi.c u8 val, cmd = 0, parameters[64]; val 1216 drivers/gpu/drm/drm_mipi_dbi.c ret = kstrtou8(token, 16, &val); val 1221 drivers/gpu/drm/drm_mipi_dbi.c cmd = val; val 1223 drivers/gpu/drm/drm_mipi_dbi.c parameters[i++] = val; val 1245 drivers/gpu/drm/drm_mipi_dbi.c u8 cmd, val[4]; val 1273 drivers/gpu/drm/drm_mipi_dbi.c ret = mipi_dbi_command_buf(dbi, cmd, val, len); val 1278 drivers/gpu/drm/drm_mipi_dbi.c seq_printf(m, "%*phN\n", (int)len, val); val 268 drivers/gpu/drm/drm_mode_object.c struct drm_property *property, uint64_t val) val 277 drivers/gpu/drm/drm_mode_object.c obj->properties->values[i] = val; val 288 drivers/gpu/drm/drm_mode_object.c uint64_t *val) val 298 drivers/gpu/drm/drm_mode_object.c return drm_atomic_get_property(obj, property, val); val 302 drivers/gpu/drm/drm_mode_object.c *val = obj->properties->values[i]; val 329 drivers/gpu/drm/drm_mode_object.c struct drm_property *property, uint64_t *val) val 333 drivers/gpu/drm/drm_mode_object.c return __drm_object_property_get_value(obj, property, val); val 347 drivers/gpu/drm/drm_mode_object.c uint64_t val; val 353 drivers/gpu/drm/drm_mode_object.c ret = __drm_object_property_get_value(obj, prop, &val); val 360 drivers/gpu/drm/drm_mode_object.c if (put_user(val, prop_values + count)) val 13 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c #define EXTRACT(val, field) (((val) & field##__MASK) >> field##__SHIFT) val 171 drivers/gpu/drm/etnaviv/etnaviv_gpu.c #define etnaviv_field(val, field) \ val 172 drivers/gpu/drm/etnaviv/etnaviv_gpu.c (((val) & field##__MASK) >> field##__SHIFT) val 697 drivers/gpu/drm/etnaviv/etnaviv_gpu.c u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); val 698 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; val 699 drivers/gpu/drm/etnaviv/etnaviv_gpu.c gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); val 1220 drivers/gpu/drm/etnaviv/etnaviv_gpu.c u32 val; val 1223 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); val 1224 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; val 1225 drivers/gpu/drm/etnaviv/etnaviv_gpu.c gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); val 1228 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); val 1229 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; val 1230 drivers/gpu/drm/etnaviv/etnaviv_gpu.c gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); val 1240 drivers/gpu/drm/etnaviv/etnaviv_gpu.c u32 val; val 1251 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); val 1252 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; val 1253 drivers/gpu/drm/etnaviv/etnaviv_gpu.c gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); val 1256 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); val 1257 drivers/gpu/drm/etnaviv/etnaviv_gpu.c val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; val 1258 drivers/gpu/drm/etnaviv/etnaviv_gpu.c gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); val 544 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c u32 val; val 548 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c val = sig->sample(gpu, dom, sig); val 550 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c *(bo + pmr->offset) = val; val 96 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 val) val 98 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = (val & mask) | (readl(ctx->addr + reg) & ~mask); val 99 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + reg); val 105 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 val; val 107 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDINTCON0_INTEN; val 109 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= VIDINTCON0_FRAMEDONE; val 111 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP; val 113 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDINTCON0); val 200 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 val; val 214 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDOUT_LCD_ON; val 216 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= VIDOUT_INTERLACE_EN_F; val 218 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= VIDOUT_COMMAND_IF; val 220 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= VIDOUT_RGB_IF; val 223 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDOUTCON0); val 226 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) | val 229 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDTCON2_LINEVAL(m->vdisplay - 1) | val 231 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDTCON2); val 239 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1); val 240 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDTCON00); val 242 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDTCON01_VSPW_F( val 244 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDTCON01); val 246 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDTCON10_HBPD_F( val 250 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDTCON10); val 252 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDTCON11_HSPW_F( val 254 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDTCON11); val 267 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 val = 0; val 272 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A); val 273 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); val 278 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0); val 279 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); val 281 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE); val 282 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); val 286 drivers/gpu/drm/exynos/exynos5433_drm_decon.c decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val); val 293 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 val = 0; val 301 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_ALPHA_SEL_F; val 302 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BLD_PIX_F; val 303 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_ALPHA_MUL_F; val 306 drivers/gpu/drm/exynos/exynos5433_drm_decon.c decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val); val 309 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDOSD_Wx_ALPHA_R_F(win_alpha) | val 313 drivers/gpu/drm/exynos/exynos5433_drm_decon.c VIDOSDxC_ALPHA0_RGB_MASK, val); val 326 drivers/gpu/drm/exynos/exynos5433_drm_decon.c unsigned long val; val 333 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = readl(ctx->addr + DECON_WINCONx(win)); val 334 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val &= WINCONx_ENWIN_F; val 338 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BPPMODE_16BPP_I1555; val 339 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_HAWSWP_F; val 340 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 343 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BPPMODE_16BPP_565; val 344 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_HAWSWP_F; val 345 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 348 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BPPMODE_24BPP_888; val 349 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_WSWP_F; val 350 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 354 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BPPMODE_32BPP_A8888; val 355 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_WSWP_F; val 356 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 371 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val &= ~WINCONx_BURSTLEN_MASK; val 372 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val |= WINCONx_BURSTLEN_8WORD; val 374 drivers/gpu/drm/exynos/exynos5433_drm_decon.c decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val); val 410 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 val; val 413 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = COORDINATE_X(state->crtc.x) | val 415 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDOSDxA(win)); val 417 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | val 419 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDOSDxB(win)); val 421 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y); val 422 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDOSDxA(win)); val 424 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | val 426 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDOSDxB(win)); val 429 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) | val 431 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDOSDxC(win)); val 433 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | val 435 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDOSDxD(win)); val 439 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = dma_addr + pitch * state->src.h; val 440 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); val 443 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14) val 446 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15) val 448 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDW0xADD2(win)); val 486 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 val; val 490 drivers/gpu/drm/exynos/exynos5433_drm_decon.c readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, val 491 drivers/gpu/drm/exynos/exynos5433_drm_decon.c ~val & VIDCON0_STOP_STATUS, 12, 20000); val 494 drivers/gpu/drm/exynos/exynos5433_drm_decon.c ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, val 495 drivers/gpu/drm/exynos/exynos5433_drm_decon.c ~val & VIDCON0_SWRESET, 12, 20000); val 687 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 val; val 689 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = readl(ctx->addr + DECON_VIDINTCON1); val 690 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; val 692 drivers/gpu/drm/exynos/exynos5433_drm_decon.c if (val) { val 693 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + DECON_VIDINTCON1); val 695 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = readl(ctx->addr + DECON_VIDOUTCON0); val 696 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F; val 697 drivers/gpu/drm/exynos/exynos5433_drm_decon.c if (val == val 110 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 val = readl(ctx->regs + WINCON(win)); val 112 drivers/gpu/drm/exynos/exynos7_drm_decon.c if (val & WINCONx_ENWIN) { val 113 drivers/gpu/drm/exynos/exynos7_drm_decon.c val &= ~WINCONx_ENWIN; val 114 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + WINCON(win)); val 156 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 val, clkdiv; val 172 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); val 173 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDTCON0); val 175 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDTCON1_VSPW(vsync_len - 1); val 176 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDTCON1); val 184 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); val 185 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDTCON2); val 187 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDTCON3_HSPW(hsync_len - 1); val 188 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDTCON3); val 192 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | val 194 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDTCON4); val 202 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDCON0_ENVID | VIDCON0_ENVID_F; val 203 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDCON0); val 207 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); val 208 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VCLKCON1); val 209 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VCLKCON2); val 212 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + DECON_UPDATE); val 213 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= DECON_UPDATE_STANDALONE_F; val 214 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + DECON_UPDATE); val 220 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 val; val 226 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + VIDINTCON0); val 228 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= VIDINTCON0_INT_ENABLE; val 231 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= VIDINTCON0_INT_FRAME; val 232 drivers/gpu/drm/exynos/exynos7_drm_decon.c val &= ~VIDINTCON0_FRAMESEL0_MASK; val 233 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= VIDINTCON0_FRAMESEL0_VSYNC; val 236 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDINTCON0); val 245 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 val; val 251 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + VIDINTCON0); val 253 drivers/gpu/drm/exynos/exynos7_drm_decon.c val &= ~VIDINTCON0_INT_ENABLE; val 255 drivers/gpu/drm/exynos/exynos7_drm_decon.c val &= ~VIDINTCON0_INT_FRAME; val 257 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDINTCON0); val 264 drivers/gpu/drm/exynos/exynos7_drm_decon.c unsigned long val; val 267 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + WINCON(win)); val 268 drivers/gpu/drm/exynos/exynos7_drm_decon.c val &= ~WINCONx_BPPMODE_MASK; val 272 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_16BPP_565; val 273 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 276 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_24BPP_xRGB; val 277 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 280 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_24BPP_xBGR; val 281 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 284 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_24BPP_RGBx; val 285 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 288 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_24BPP_BGRx; val 289 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 292 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | val 294 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 297 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | val 299 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 302 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | val 304 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 308 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | val 310 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_16WORD; val 326 drivers/gpu/drm/exynos/exynos7_drm_decon.c val &= ~WINCONx_BURSTLEN_MASK; val 327 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_BURSTLEN_8WORD; val 330 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + WINCON(win)); val 355 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 bits, val; val 359 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + SHADOWCON); val 361 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= bits; val 363 drivers/gpu/drm/exynos/exynos7_drm_decon.c val &= ~bits; val 364 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + SHADOWCON); val 387 drivers/gpu/drm/exynos/exynos7_drm_decon.c unsigned long val, alpha; val 408 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); val 409 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDW_BUF_START(win)); val 422 drivers/gpu/drm/exynos/exynos7_drm_decon.c (unsigned long)val); val 426 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | val 428 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDOSD_A(win)); val 437 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); val 439 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDOSD_B(win)); val 464 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + WINCON(win)); val 465 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_TRIPLE_BUF_MODE; val 466 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= WINCONx_ENWIN; val 467 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + WINCON(win)); val 472 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + DECON_UPDATE); val 473 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= DECON_UPDATE_STANDALONE_F; val 474 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + DECON_UPDATE); val 482 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 val; val 491 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + WINCON(win)); val 492 drivers/gpu/drm/exynos/exynos7_drm_decon.c val &= ~WINCONx_ENWIN; val 493 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + WINCON(win)); val 495 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + DECON_UPDATE); val 496 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= DECON_UPDATE_STANDALONE_F; val 497 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + DECON_UPDATE); val 515 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 val; val 519 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VIDOUTCON0_DISP_IF_0_ON; val 521 drivers/gpu/drm/exynos/exynos7_drm_decon.c val |= VIDOUTCON0_RGBIF; val 522 drivers/gpu/drm/exynos/exynos7_drm_decon.c writel(val, ctx->regs + VIDOUTCON0); val 586 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 val, clear_bit; val 588 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = readl(ctx->regs + VIDINTCON1); val 591 drivers/gpu/drm/exynos/exynos7_drm_decon.c if (val & clear_bit) val 319 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 val) val 322 drivers/gpu/drm/exynos/exynos_drm_dsi.c writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); val 120 drivers/gpu/drm/exynos/exynos_drm_fimc.c static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg) val 122 drivers/gpu/drm/exynos/exynos_drm_fimc.c writel(val, ctx->regs + reg); val 238 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val) val 240 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = (val & mask) | (readl(ctx->regs + reg) & ~mask); val 241 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + reg); val 247 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val; val 253 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = readl(ctx->regs + VIDINTCON0); val 255 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDINTCON0_INT_ENABLE; val 258 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDINTCON0_INT_I80IFDONE; val 259 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDINTCON0_INT_SYSMAINCON; val 260 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~VIDINTCON0_INT_SYSSUBCON; val 262 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDINTCON0_INT_FRAME; val 264 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~VIDINTCON0_FRAMESEL0_MASK; val 265 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDINTCON0_FRAMESEL0_FRONTPORCH; val 266 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~VIDINTCON0_FRAMESEL1_MASK; val 267 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDINTCON0_FRAMESEL1_NONE; val 270 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDINTCON0); val 279 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val; val 285 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = readl(ctx->regs + VIDINTCON0); val 287 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~VIDINTCON0_INT_ENABLE; val 290 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~VIDINTCON0_INT_I80IFDONE; val 291 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~VIDINTCON0_INT_SYSMAINCON; val 292 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~VIDINTCON0_INT_SYSSUBCON; val 294 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~VIDINTCON0_INT_FRAME; val 296 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDINTCON0); val 322 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val = readl(ctx->regs + WINCON(win)); val 325 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_ENWIN; val 327 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~WINCONx_ENWIN; val 329 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + WINCON(win)); val 336 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val = readl(ctx->regs + SHADOWCON); val 339 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= SHADOWCON_CHx_ENABLE(win); val 341 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~SHADOWCON_CHx_ENABLE(win); val 343 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + SHADOWCON); val 359 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val = readl(ctx->regs + WINCON(win)); val 361 drivers/gpu/drm/exynos/exynos_drm_fimd.c if (val & WINCONx_ENWIN) { val 438 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val = readl(timing_base + TRIGCON); val 440 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~(TRGMODE_ENABLE); val 444 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE; val 446 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= HWTRIGEN_PER_ENABLE; val 448 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= TRGMODE_ENABLE; val 451 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, timing_base + TRIGCON); val 460 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val; val 470 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = ctx->i80ifcon | I80IFEN_ENABLE; val 471 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, timing_base + I80IFCONFAx(0)); val 503 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDTCON0_VBPD(vbpd - 1) | val 506 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); val 513 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDTCON1_HBPD(hbpd - 1) | val 516 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); val 546 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | val 550 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); val 558 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = ctx->vidcon0; val 559 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDCON0_ENVID | VIDCON0_ENVID_F; val 562 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDCON0_CLKSEL_LCD; val 565 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; val 567 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDCON0); val 574 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val = 0; val 579 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A); val 580 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); val 585 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0); val 586 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); val 588 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE); val 589 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); val 593 drivers/gpu/drm/exynos/exynos_drm_fimd.c fimd_set_bits(ctx, BLENDEQx(win), mask, val); val 601 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val = 0; val 609 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCON1_ALPHA_SEL; val 610 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCON1_BLD_PIX; val 611 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCON1_ALPHA_MUL; val 614 drivers/gpu/drm/exynos/exynos_drm_fimd.c fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); val 617 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDISD14C_ALPHA0_R(win_alpha_h) | val 623 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDOSD_C(win)); val 625 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) | val 627 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDWnALPHA0(win)); val 629 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) | val 631 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDWnALPHA1(win)); val 645 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val = WINCONx_ENWIN; val 664 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCON0_BPPMODE_8BPP_PALETTE; val 665 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_BURSTLEN_8WORD; val 666 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_BYTSWP; val 669 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCON0_BPPMODE_16BPP_1555; val 670 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_HAWSWP; val 671 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_BURSTLEN_16WORD; val 674 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCON0_BPPMODE_16BPP_565; val 675 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_HAWSWP; val 676 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_BURSTLEN_16WORD; val 679 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCON0_BPPMODE_24BPP_888; val 680 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_WSWP; val 681 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_BURSTLEN_16WORD; val 685 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCON1_BPPMODE_25BPP_A1888; val 686 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_WSWP; val 687 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_BURSTLEN_16WORD; val 700 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~WINCONx_BURSTLEN_MASK; val 701 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= WINCONx_BURSTLEN_4WORD; val 703 drivers/gpu/drm/exynos/exynos_drm_fimd.c fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); val 734 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 reg, bits, val; val 754 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = readl(ctx->regs + reg); val 756 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= bits; val 758 drivers/gpu/drm/exynos/exynos_drm_fimd.c val &= ~bits; val 759 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + reg); val 796 drivers/gpu/drm/exynos/exynos_drm_fimd.c unsigned long val, size, offset; val 810 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = (unsigned long)dma_addr; val 811 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); val 815 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = (unsigned long)(dma_addr + size); val 816 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); val 820 drivers/gpu/drm/exynos/exynos_drm_fimd.c (unsigned long)dma_addr, val, size); val 827 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | val 831 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); val 834 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | val 838 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDOSD_A(win)); val 847 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | val 850 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + VIDOSD_B(win)); val 861 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = state->crtc.w * state->crtc.h; val 862 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + offset); val 865 drivers/gpu/drm/exynos/exynos_drm_fimd.c (unsigned int)val); val 1005 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; val 1006 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + DP_MIE_CLKCON); val 1025 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val, clear_bit; val 1027 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = readl(ctx->regs + VIDINTCON1); val 1030 drivers/gpu/drm/exynos/exynos_drm_fimd.c if (val & clear_bit) val 1141 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 val; val 1155 drivers/gpu/drm/exynos/exynos_drm_fimd.c if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) val 1156 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = 0; val 1157 drivers/gpu/drm/exynos/exynos_drm_fimd.c ctx->i80ifcon = LCD_CS_SETUP(val); val 1158 drivers/gpu/drm/exynos/exynos_drm_fimd.c if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) val 1159 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = 0; val 1160 drivers/gpu/drm/exynos/exynos_drm_fimd.c ctx->i80ifcon |= LCD_WR_SETUP(val); val 1161 drivers/gpu/drm/exynos/exynos_drm_fimd.c if (of_property_read_u32(i80_if_timings, "wr-active", &val)) val 1162 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = 1; val 1163 drivers/gpu/drm/exynos/exynos_drm_fimd.c ctx->i80ifcon |= LCD_WR_ACTIVE(val); val 1164 drivers/gpu/drm/exynos/exynos_drm_fimd.c if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) val 1165 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = 0; val 1166 drivers/gpu/drm/exynos/exynos_drm_fimd.c ctx->i80ifcon |= LCD_WR_HOLD(val); val 423 drivers/gpu/drm/exynos/exynos_drm_ipp.c static inline void __limit_set_val(unsigned int *ptr, unsigned int val) val 426 drivers/gpu/drm/exynos/exynos_drm_ipp.c *ptr = val; val 453 drivers/gpu/drm/exynos/exynos_drm_ipp.c static inline bool __align_check(unsigned int val, unsigned int align) val 455 drivers/gpu/drm/exynos/exynos_drm_ipp.c if (align && (val & (align - 1))) { val 457 drivers/gpu/drm/exynos/exynos_drm_ipp.c val, align); val 463 drivers/gpu/drm/exynos/exynos_drm_ipp.c static inline bool __size_limit_check(unsigned int val, val 466 drivers/gpu/drm/exynos/exynos_drm_ipp.c if ((l->min && val < l->min) || (l->max && val > l->max)) { val 468 drivers/gpu/drm/exynos/exynos_drm_ipp.c val, l->min, l->max); val 471 drivers/gpu/drm/exynos/exynos_drm_ipp.c return __align_check(val, l->align); val 120 drivers/gpu/drm/exynos/exynos_drm_ipp.h #define IPP_SIZE_LIMIT(l, val...) \ val 122 drivers/gpu/drm/exynos/exynos_drm_ipp.h DRM_EXYNOS_IPP_LIMIT_SIZE_##l), val val 124 drivers/gpu/drm/exynos/exynos_drm_ipp.h #define IPP_SCALE_LIMIT(val...) \ val 125 drivers/gpu/drm/exynos/exynos_drm_ipp.h .type = (DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE), val val 111 drivers/gpu/drm/exynos/exynos_drm_mic.c unsigned int val; val 113 drivers/gpu/drm/exynos/exynos_drm_mic.c ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val); val 122 drivers/gpu/drm/exynos/exynos_drm_mic.c val |= MIC0_I80_MUX; val 124 drivers/gpu/drm/exynos/exynos_drm_mic.c val |= MIC0_RGB_MUX; val 126 drivers/gpu/drm/exynos/exynos_drm_mic.c val |= MIC0_ON_MUX; val 128 drivers/gpu/drm/exynos/exynos_drm_mic.c val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX); val 130 drivers/gpu/drm/exynos/exynos_drm_mic.c ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val); val 70 drivers/gpu/drm/exynos/exynos_drm_rotator.c u32 val = rot_read(ROT_CONFIG); val 73 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONFIG_IRQ; val 75 drivers/gpu/drm/exynos/exynos_drm_rotator.c val &= ~ROT_CONFIG_IRQ; val 77 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_CONFIG); val 82 drivers/gpu/drm/exynos/exynos_drm_rotator.c u32 val = rot_read(ROT_STATUS); val 84 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = ROT_STATUS_IRQ(val); val 86 drivers/gpu/drm/exynos/exynos_drm_rotator.c if (val == ROT_STATUS_IRQ_VAL_COMPLETE) val 96 drivers/gpu/drm/exynos/exynos_drm_rotator.c u32 val; val 102 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = rot_read(ROT_STATUS); val 103 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_STATUS_IRQ_PENDING((u32)irq_status); val 104 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_STATUS); val 121 drivers/gpu/drm/exynos/exynos_drm_rotator.c u32 val; val 123 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = rot_read(ROT_CONTROL); val 124 drivers/gpu/drm/exynos/exynos_drm_rotator.c val &= ~ROT_CONTROL_FMT_MASK; val 128 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONTROL_FMT_YCBCR420_2P; val 131 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONTROL_FMT_RGB888; val 135 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_CONTROL); val 141 drivers/gpu/drm/exynos/exynos_drm_rotator.c u32 val; val 144 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = ROT_SET_BUF_SIZE_H(buf->buf.height) | val 146 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_SRC_BUF_SIZE); val 149 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = ROT_CROP_POS_Y(buf->rect.y) | ROT_CROP_POS_X(buf->rect.x); val 150 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_SRC_CROP_POS); val 151 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = ROT_SRC_CROP_SIZE_H(buf->rect.h) | val 153 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_SRC_CROP_SIZE); val 163 drivers/gpu/drm/exynos/exynos_drm_rotator.c u32 val; val 166 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = rot_read(ROT_CONTROL); val 167 drivers/gpu/drm/exynos/exynos_drm_rotator.c val &= ~ROT_CONTROL_FLIP_MASK; val 170 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONTROL_FLIP_VERTICAL; val 172 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONTROL_FLIP_HORIZONTAL; val 174 drivers/gpu/drm/exynos/exynos_drm_rotator.c val &= ~ROT_CONTROL_ROT_MASK; val 177 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONTROL_ROT_90; val 179 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONTROL_ROT_180; val 181 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONTROL_ROT_270; val 183 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_CONTROL); val 189 drivers/gpu/drm/exynos/exynos_drm_rotator.c u32 val; val 192 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = ROT_SET_BUF_SIZE_H(buf->buf.height) | val 194 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_DST_BUF_SIZE); val 197 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = ROT_CROP_POS_Y(buf->rect.y) | ROT_CROP_POS_X(buf->rect.x); val 198 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_DST_CROP_POS); val 207 drivers/gpu/drm/exynos/exynos_drm_rotator.c u32 val; val 212 drivers/gpu/drm/exynos/exynos_drm_rotator.c val = rot_read(ROT_CONTROL); val 213 drivers/gpu/drm/exynos/exynos_drm_rotator.c val |= ROT_CONTROL_START; val 214 drivers/gpu/drm/exynos/exynos_drm_rotator.c rot_write(val, ROT_CONTROL); val 111 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 113 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_INT_EN_TIMEOUT | val 139 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_INT_EN); val 145 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 147 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10); val 148 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_SRC_CFG); val 168 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 170 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_SRC_SPAN_SET_Y_SPAN(src_buf->buf.pitch[0] / val 174 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_SRC_SPAN_SET_C_SPAN(src_buf->buf.pitch[1]); val 176 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_SRC_SPAN); val 183 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 185 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2); val 186 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2); val 187 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_SRC_Y_POS); val 188 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_SRC_C_POS_SET_CH_POS( val 190 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_SRC_C_POS_SET_CV_POS( val 192 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_SRC_C_POS); val 198 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 200 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_SRC_WH_SET_WIDTH(src_pos->w); val 201 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_SRC_WH_SET_HEIGHT(src_pos->h); val 202 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_SRC_WH); val 208 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 210 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_DST_CFG_SET_COLOR_FORMAT(dst_fmt); val 211 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_DST_CFG); val 231 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 233 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_DST_SPAN_SET_Y_SPAN(dst_buf->buf.pitch[0] / val 237 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_DST_SPAN_SET_C_SPAN(dst_buf->buf.pitch[1]); val 239 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_DST_SPAN); val 245 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 247 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_DST_WH_SET_WIDTH(dst_pos->w); val 248 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_DST_WH_SET_HEIGHT(dst_pos->h); val 249 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_DST_WH); val 255 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 257 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_DST_POS_SET_H_POS(dst_pos->x); val 258 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_DST_POS_SET_V_POS(dst_pos->y); val 259 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_DST_POS); val 267 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val, h_ratio, v_ratio; val 277 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_H_RATIO_SET(h_ratio); val 278 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_H_RATIO); val 280 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_V_RATIO_SET(v_ratio); val 281 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_V_RATIO); val 287 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val = 0; val 290 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_90); val 292 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_180); val 294 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_270); val 296 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_ROT_CFG_FLIP_X_EN; val 298 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_ROT_CFG_FLIP_Y_EN; val 299 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_ROT_CFG); val 343 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val; val 345 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_TIMEOUT_CTRL_TIMER_ENABLE; val 346 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(timer); val 347 drivers/gpu/drm/exynos/exynos_drm_scaler.c val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider); val 348 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_TIMEOUT_CTRL); val 414 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val = scaler_read(SCALER_INT_STATUS); val 416 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(val, SCALER_INT_STATUS); val 418 drivers/gpu/drm/exynos/exynos_drm_scaler.c return val; val 421 drivers/gpu/drm/exynos/exynos_drm_scaler.c static inline int scaler_task_done(u32 val) val 423 drivers/gpu/drm/exynos/exynos_drm_scaler.c return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL; val 430 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 val = scaler_get_int_status(scaler); val 440 drivers/gpu/drm/exynos/exynos_drm_scaler.c exynos_drm_ipp_task_done(task, scaler_task_done(val)); val 685 drivers/gpu/drm/exynos/exynos_hdmi.c int bytes, u32 val) val 690 drivers/gpu/drm/exynos/exynos_hdmi.c writel(val & 0xff, hdata->regs + reg_id); val 691 drivers/gpu/drm/exynos/exynos_hdmi.c val >>= 8; val 1048 drivers/gpu/drm/exynos/exynos_hdmi.c u32 data_num, val; val 1077 drivers/gpu/drm/exynos/exynos_hdmi.c val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01; val 1078 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val); val 1124 drivers/gpu/drm/exynos/exynos_hdmi.c u32 val = start ? HDMI_TG_EN : 0; val 1127 drivers/gpu/drm/exynos/exynos_hdmi.c val |= HDMI_FIELD_EN; val 1129 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN); val 1130 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN); val 1182 drivers/gpu/drm/exynos/exynos_hdmi.c u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS); val 1184 drivers/gpu/drm/exynos/exynos_hdmi.c if (val & HDMI_PHY_STATUS_READY) { val 1199 drivers/gpu/drm/exynos/exynos_hdmi.c unsigned int val; val 1205 drivers/gpu/drm/exynos/exynos_hdmi.c val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; val 1206 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val); val 1208 drivers/gpu/drm/exynos/exynos_hdmi.c val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0; val 1209 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val); val 1211 drivers/gpu/drm/exynos/exynos_hdmi.c val = (m->hsync_start - m->hdisplay - 2); val 1212 drivers/gpu/drm/exynos/exynos_hdmi.c val |= ((m->hsync_end - m->hdisplay - 2) << 10); val 1213 drivers/gpu/drm/exynos/exynos_hdmi.c val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20; val 1214 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val); val 1224 drivers/gpu/drm/exynos/exynos_hdmi.c val = ((m->vsync_end - m->vdisplay) / 2); val 1225 drivers/gpu/drm/exynos/exynos_hdmi.c val |= ((m->vsync_start - m->vdisplay) / 2) << 12; val 1226 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); val 1228 drivers/gpu/drm/exynos/exynos_hdmi.c val = m->vtotal / 2; val 1229 drivers/gpu/drm/exynos/exynos_hdmi.c val |= ((m->vtotal - m->vdisplay) / 2) << 11; val 1230 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); val 1232 drivers/gpu/drm/exynos/exynos_hdmi.c val = (m->vtotal + val 1234 drivers/gpu/drm/exynos/exynos_hdmi.c val |= m->vtotal << 11; val 1235 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val); val 1237 drivers/gpu/drm/exynos/exynos_hdmi.c val = ((m->vtotal / 2) + 7); val 1238 drivers/gpu/drm/exynos/exynos_hdmi.c val |= ((m->vtotal / 2) + 2) << 12; val 1239 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val); val 1241 drivers/gpu/drm/exynos/exynos_hdmi.c val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); val 1242 drivers/gpu/drm/exynos/exynos_hdmi.c val |= ((m->htotal / 2) + val 1244 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val); val 1252 drivers/gpu/drm/exynos/exynos_hdmi.c val = m->vtotal; val 1253 drivers/gpu/drm/exynos/exynos_hdmi.c val |= (m->vtotal - m->vdisplay) << 11; val 1254 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); val 1258 drivers/gpu/drm/exynos/exynos_hdmi.c val = (m->vsync_end - m->vdisplay); val 1259 drivers/gpu/drm/exynos/exynos_hdmi.c val |= ((m->vsync_start - m->vdisplay) << 12); val 1260 drivers/gpu/drm/exynos/exynos_hdmi.c hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); val 188 drivers/gpu/drm/exynos/exynos_mixer.c u32 val) val 190 drivers/gpu/drm/exynos/exynos_mixer.c writel(val, ctx->vp_regs + reg_id); val 194 drivers/gpu/drm/exynos/exynos_mixer.c u32 val, u32 mask) val 198 drivers/gpu/drm/exynos/exynos_mixer.c val = (val & mask) | (old & ~mask); val 199 drivers/gpu/drm/exynos/exynos_mixer.c writel(val, ctx->vp_regs + reg_id); val 208 drivers/gpu/drm/exynos/exynos_mixer.c u32 val) val 210 drivers/gpu/drm/exynos/exynos_mixer.c writel(val, ctx->mixer_regs + reg_id); val 214 drivers/gpu/drm/exynos/exynos_mixer.c u32 reg_id, u32 val, u32 mask) val 218 drivers/gpu/drm/exynos/exynos_mixer.c val = (val & mask) | (old & ~mask); val 219 drivers/gpu/drm/exynos/exynos_mixer.c writel(val, ctx->mixer_regs + reg_id); val 295 drivers/gpu/drm/exynos/exynos_mixer.c u32 val = (data[0] << 24) | (data[1] << 16) | val 297 drivers/gpu/drm/exynos/exynos_mixer.c vp_reg_write(ctx, reg_id, val); val 315 drivers/gpu/drm/exynos/exynos_mixer.c u32 val; val 317 drivers/gpu/drm/exynos/exynos_mixer.c val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ val 322 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_GRP_CFG_PIXEL_BLEND_EN; val 326 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_GRP_CFG_BLEND_PRE_MUL; val 327 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_GRP_CFG_PIXEL_BLEND_EN; val 332 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_GRP_CFG_WIN_BLEND_EN; val 333 drivers/gpu/drm/exynos/exynos_mixer.c val |= win_alpha; val 336 drivers/gpu/drm/exynos/exynos_mixer.c val, MXR_GRP_CFG_MISC_MASK); val 342 drivers/gpu/drm/exynos/exynos_mixer.c u32 val = 0; val 345 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_VID_CFG_BLEND_EN; val 346 drivers/gpu/drm/exynos/exynos_mixer.c val |= win_alpha; val 348 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_write(ctx, MXR_VIDEO_CFG, val); val 411 drivers/gpu/drm/exynos/exynos_mixer.c u32 val; val 414 drivers/gpu/drm/exynos/exynos_mixer.c val = test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? val 421 drivers/gpu/drm/exynos/exynos_mixer.c val |= ctx->scan_value; val 423 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_SCAN_MASK); val 429 drivers/gpu/drm/exynos/exynos_mixer.c u32 val; val 432 drivers/gpu/drm/exynos/exynos_mixer.c val = MXR_CFG_RGB601; val 434 drivers/gpu/drm/exynos/exynos_mixer.c val = MXR_CFG_RGB709; val 447 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_CFG_QUANT_RANGE_FULL; val 449 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_CFG_QUANT_RANGE_LIMITED; val 451 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); val 457 drivers/gpu/drm/exynos/exynos_mixer.c u32 val = enable ? ~0 : 0; val 461 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); val 467 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); val 475 drivers/gpu/drm/exynos/exynos_mixer.c vp_reg_writemask(ctx, VP_ENABLE, val, VP_ENABLE_ON); val 476 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_writemask(ctx, MXR_CFG, val, val 521 drivers/gpu/drm/exynos/exynos_mixer.c u32 val; val 545 drivers/gpu/drm/exynos/exynos_mixer.c val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0); val 546 drivers/gpu/drm/exynos/exynos_mixer.c vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP); val 549 drivers/gpu/drm/exynos/exynos_mixer.c val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12); val 550 drivers/gpu/drm/exynos/exynos_mixer.c val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR); val 551 drivers/gpu/drm/exynos/exynos_mixer.c vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_FMT_MASK); val 612 drivers/gpu/drm/exynos/exynos_mixer.c u32 val; val 663 drivers/gpu/drm/exynos/exynos_mixer.c val = MXR_GRP_WH_WIDTH(state->src.w); val 664 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_GRP_WH_HEIGHT(state->src.h); val 665 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_GRP_WH_H_SCALE(x_ratio); val 666 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_GRP_WH_V_SCALE(y_ratio); val 667 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_write(ctx, MXR_GRAPHIC_WH(win), val); val 670 drivers/gpu/drm/exynos/exynos_mixer.c val = MXR_GRP_DXY_DX(dst_x_offset); val 671 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_GRP_DXY_DY(dst_y_offset); val 672 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_write(ctx, MXR_GRAPHIC_DXY(win), val); val 744 drivers/gpu/drm/exynos/exynos_mixer.c u32 val; val 749 drivers/gpu/drm/exynos/exynos_mixer.c val = mixer_reg_read(ctx, MXR_INT_STATUS); val 752 drivers/gpu/drm/exynos/exynos_mixer.c if (val & MXR_INT_STATUS_VSYNC) { val 754 drivers/gpu/drm/exynos/exynos_mixer.c val |= MXR_INT_CLEAR_VSYNC; val 755 drivers/gpu/drm/exynos/exynos_mixer.c val &= ~MXR_INT_STATUS_VSYNC; val 767 drivers/gpu/drm/exynos/exynos_mixer.c mixer_reg_write(ctx, MXR_INT_STATUS, val); val 45 drivers/gpu/drm/exynos/regs-decon7.h #define VCLKCON1_CLKVAL_NUM_VCLK(val) (((val) & 0xff) << 0) val 69 drivers/gpu/drm/exynos/regs-mixer.h #define MXR_MASK_VAL(val, high_bit, low_bit) \ val 70 drivers/gpu/drm/exynos/regs-mixer.h (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit)) val 130 drivers/gpu/drm/exynos/regs-scaler.h #define SCALER_SET(val, hi_b, lo_b) \ val 131 drivers/gpu/drm/exynos/regs-scaler.h (((val) & SCALER_MASK(hi_b, lo_b)) << lo_b) val 55 drivers/gpu/drm/exynos/regs-vp.h #define VP_MASK_VAL(val, high_bit, low_bit) \ val 56 drivers/gpu/drm/exynos/regs-vp.h (((val) << (low_bit)) & VP_MASK(high_bit, low_bit)) val 98 drivers/gpu/drm/gma500/cdv_device.c u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; val 103 drivers/gpu/drm/gma500/cdv_device.c val &= ~1; val 105 drivers/gpu/drm/gma500/cdv_device.c val *= lbpc; val 107 drivers/gpu/drm/gma500/cdv_device.c return (val * 100)/cdv_get_max_backlight(dev); val 129 drivers/gpu/drm/gma500/cdv_intel_display.c int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) val 151 drivers/gpu/drm/gma500/cdv_intel_display.c *val = REG_READ(SB_DATA); val 156 drivers/gpu/drm/gma500/cdv_intel_display.c int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) val 165 drivers/gpu/drm/gma500/cdv_intel_display.c DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); val 175 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(SB_DATA, val); val 1844 drivers/gpu/drm/gma500/cdv_intel_dp.c uint64_t val) val 1851 drivers/gpu/drm/gma500/cdv_intel_dp.c ret = drm_object_property_set_value(&connector->base, property, val); val 1856 drivers/gpu/drm/gma500/cdv_intel_dp.c int i = val; val 1877 drivers/gpu/drm/gma500/cdv_intel_dp.c if (val == !!intel_dp->color_range) val 1880 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; val 56 drivers/gpu/drm/gma500/intel_gmbus.c #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg)) val 277 drivers/gpu/drm/gma500/intel_gmbus.c u32 val, loop = 0; val 285 drivers/gpu/drm/gma500/intel_gmbus.c val = GMBUS_REG_READ(GMBUS3 + reg_offset); val 287 drivers/gpu/drm/gma500/intel_gmbus.c *buf++ = val & 0xff; val 288 drivers/gpu/drm/gma500/intel_gmbus.c val >>= 8; val 292 drivers/gpu/drm/gma500/intel_gmbus.c u32 val, loop; val 294 drivers/gpu/drm/gma500/intel_gmbus.c val = loop = 0; val 296 drivers/gpu/drm/gma500/intel_gmbus.c val |= *buf++ << (8 * loop); val 299 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); val 315 drivers/gpu/drm/gma500/intel_gmbus.c val = loop = 0; val 317 drivers/gpu/drm/gma500/intel_gmbus.c val |= *buf++ << (8 * loop); val 320 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); val 27 drivers/gpu/drm/gma500/intel_i2c.c u32 val; val 29 drivers/gpu/drm/gma500/intel_i2c.c val = REG_READ(chan->reg); val 30 drivers/gpu/drm/gma500/intel_i2c.c return (val & GPIO_CLOCK_VAL_IN) != 0; val 37 drivers/gpu/drm/gma500/intel_i2c.c u32 val; val 39 drivers/gpu/drm/gma500/intel_i2c.c val = REG_READ(chan->reg); val 40 drivers/gpu/drm/gma500/intel_i2c.c return (val & GPIO_DATA_VAL_IN) != 0; val 475 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c u32 val; val 487 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c val = lane_count; val 488 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET; val 492 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c val |= DSI_DPI_COLOR_FORMAT_RGB565; val 495 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c val |= DSI_DPI_COLOR_FORMAT_RGB666; val 498 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c val |= DSI_DPI_COLOR_FORMAT_RGB888; val 504 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); val 548 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE; val 549 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); val 256 drivers/gpu/drm/gma500/mdfld_dsi_output.c uint64_t val; val 272 drivers/gpu/drm/gma500/mdfld_dsi_output.c if (drm_object_property_get_value(&connector->base, property, &val)) val 275 drivers/gpu/drm/gma500/mdfld_dsi_output.c if (val == value) val 282 drivers/gpu/drm/gma500/mdfld_dsi_output.c centerechange = (val == DRM_MODE_SCALE_NO_SCALE) || val 45 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) val 46 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) val 47 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define FLD_MOD(orig, val, start, end) \ val 48 drivers/gpu/drm/gma500/mdfld_dsi_output.h (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) val 50 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define REG_FLD_MOD(reg, val, start, end) \ val 51 drivers/gpu/drm/gma500/mdfld_dsi_output.h REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end)) val 54 drivers/gpu/drm/gma500/mdfld_dsi_output.h u32 val, int start, int end) val 58 drivers/gpu/drm/gma500/mdfld_dsi_output.h while (FLD_GET(REG_READ(reg), start, end) != val) { val 66 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define REG_FLD_WAIT(reg, val, start, end) \ val 67 drivers/gpu/drm/gma500/mdfld_dsi_output.h REGISTER_FLD_WAIT(dev, reg, val, start, end) val 69 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define REG_BIT_WAIT(reg, val, bitnum) \ val 70 drivers/gpu/drm/gma500/mdfld_dsi_output.h REGISTER_FLD_WAIT(dev, reg, val, bitnum, bitnum) val 222 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c u32 val; val 235 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c val = FLD_VAL(param, 23, 16) | FLD_VAL(cmd, 15, 8) | val 238 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c REG_WRITE(ctrl_reg, val); val 249 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c u32 val; val 299 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c val = FLD_VAL(len, 23, 8) | FLD_VAL(virtual_channel, 7, 6) | val 302 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c REG_WRITE(ctrl_reg, val); val 80 drivers/gpu/drm/gma500/mmu.c uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL); val 81 drivers/gpu/drm/gma500/mmu.c PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL); val 85 drivers/gpu/drm/gma500/mmu.c PSB_WSGX32(val & ~_PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL); val 106 drivers/gpu/drm/gma500/mmu.c uint32_t val; val 109 drivers/gpu/drm/gma500/mmu.c val = PSB_RSGX32(PSB_CR_BIF_CTRL); val 111 drivers/gpu/drm/gma500/mmu.c PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL); val 113 drivers/gpu/drm/gma500/mmu.c PSB_WSGX32(val | _PSB_CB_CTRL_FLUSH, PSB_CR_BIF_CTRL); val 118 drivers/gpu/drm/gma500/mmu.c PSB_WSGX32(val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC), val 36 drivers/gpu/drm/gma500/oaktrail_hdmi.c #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg)) val 36 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg)) val 64 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c #define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r)) val 69 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c u32 val, tmp; val 71 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = LPC_READ_REG(chan, RGIO); val 72 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val |= GPIO_CLOCK; val 73 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c LPC_WRITE_REG(chan, RGIO, val); val 75 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0; val 77 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c return val; val 83 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c u32 val, tmp; val 85 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = LPC_READ_REG(chan, RGIO); val 86 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val |= GPIO_DATA; val 87 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c LPC_WRITE_REG(chan, RGIO, val); val 89 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = (LPC_READ_REG(chan, RGLVL) & GPIO_DATA) ? 1 : 0; val 91 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c return val; val 97 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c u32 val; val 100 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = LPC_READ_REG(chan, RGIO); val 101 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val |= GPIO_CLOCK; val 102 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c LPC_WRITE_REG(chan, RGIO, val); val 104 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = LPC_READ_REG(chan, RGIO); val 105 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val &= ~GPIO_CLOCK; val 106 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c LPC_WRITE_REG(chan, RGIO, val); val 107 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = LPC_READ_REG(chan, RGLVL); val 108 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val &= ~GPIO_CLOCK; val 109 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c LPC_WRITE_REG(chan, RGLVL, val); val 116 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c u32 val; val 119 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = LPC_READ_REG(chan, RGIO); val 120 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val |= GPIO_DATA; val 121 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c LPC_WRITE_REG(chan, RGIO, val); val 123 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = LPC_READ_REG(chan, RGIO); val 124 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val &= ~GPIO_DATA; val 125 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c LPC_WRITE_REG(chan, RGIO, val); val 126 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val = LPC_READ_REG(chan, RGLVL); val 127 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c val &= ~GPIO_DATA; val 128 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c LPC_WRITE_REG(chan, RGLVL, val); val 235 drivers/gpu/drm/gma500/opregion.c unsigned long val, void *data) val 830 drivers/gpu/drm/gma500/psb_drv.h uint32_t val; val 833 drivers/gpu/drm/gma500/psb_drv.h val = REG_READ_AUX(reg); val 835 drivers/gpu/drm/gma500/psb_drv.h val = REG_READ(reg); val 837 drivers/gpu/drm/gma500/psb_drv.h return val; val 843 drivers/gpu/drm/gma500/psb_drv.h uint32_t val) val 846 drivers/gpu/drm/gma500/psb_drv.h iowrite32((val), dev_priv->vdc_reg + (reg)); val 850 drivers/gpu/drm/gma500/psb_drv.h uint32_t val) val 853 drivers/gpu/drm/gma500/psb_drv.h iowrite32((val), dev_priv->aux_reg + (reg)); val 856 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) val 857 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val)) val 860 drivers/gpu/drm/gma500/psb_drv.h uint32_t val, int aux) val 863 drivers/gpu/drm/gma500/psb_drv.h REG_WRITE_AUX(reg, val); val 865 drivers/gpu/drm/gma500/psb_drv.h REG_WRITE(reg, val); val 868 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux)) val 871 drivers/gpu/drm/gma500/psb_drv.h uint32_t reg, uint32_t val) val 874 drivers/gpu/drm/gma500/psb_drv.h iowrite16((val), dev_priv->vdc_reg + (reg)); val 877 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) val 880 drivers/gpu/drm/gma500/psb_drv.h uint32_t reg, uint32_t val) val 883 drivers/gpu/drm/gma500/psb_drv.h iowrite8((val), dev_priv->vdc_reg + (reg)); val 886 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) val 270 drivers/gpu/drm/gma500/psb_intel_drv.h extern int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val); val 271 drivers/gpu/drm/gma500/psb_intel_drv.h extern int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val); val 227 drivers/gpu/drm/gma500/psb_intel_sdvo.c static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val) val 230 drivers/gpu/drm/gma500/psb_intel_sdvo.c u32 bval = val, cval = val; val 723 drivers/gpu/drm/gma500/psb_intel_sdvo.c static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val) val 725 drivers/gpu/drm/gma500/psb_intel_sdvo.c return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); val 1667 drivers/gpu/drm/gma500/psb_intel_sdvo.c uint64_t val) val 1676 drivers/gpu/drm/gma500/psb_intel_sdvo.c ret = drm_object_property_set_value(&connector->base, property, val); val 1681 drivers/gpu/drm/gma500/psb_intel_sdvo.c int i = val; val 1702 drivers/gpu/drm/gma500/psb_intel_sdvo.c if (val == !!psb_intel_sdvo->color_range) val 1705 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; val 1719 drivers/gpu/drm/gma500/psb_intel_sdvo.c if (val >= ARRAY_SIZE(tv_format_names)) val 1723 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_connector->tv_format_supported[val]) val 1726 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val]; val 1729 drivers/gpu/drm/gma500/psb_intel_sdvo.c temp_value = val; val 1732 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_connector->right, val); val 1744 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_connector->left, val); val 1756 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_connector->bottom, val); val 1768 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_connector->top, val); val 196 drivers/gpu/drm/gma500/psb_irq.c u32 val, addr; val 200 drivers/gpu/drm/gma500/psb_irq.c val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS); val 203 drivers/gpu/drm/gma500/psb_irq.c val = PSB_RSGX32(PSB_CR_BIF_INT_STAT); val 205 drivers/gpu/drm/gma500/psb_irq.c if (val) { val 206 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_PF_N_RW) val 211 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_CACHE) val 213 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_TA) val 215 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_VDM) val 217 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_2D) val 219 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_PBE) val 221 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_TSP) val 223 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_ISP) val 225 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_USSEPDS) val 227 drivers/gpu/drm/gma500/psb_irq.c if (val & _PSB_CBI_STAT_FAULT_HOST) val 41 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) val 256 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c u32 val; val 259 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val = readl(priv->mmio + CRT_PLL1_HS); val 260 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1)); val 261 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(val, priv->mmio + CRT_PLL1_HS); val 263 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1); val 264 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(val, priv->mmio + CRT_PLL1_HS); val 270 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val = pll & ~(CRT_PLL1_HS_POWERON(1)); val 271 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(val, priv->mmio + CRT_PLL1_HS); val 275 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val &= ~(CRT_PLL1_HS_INTER_BYPASS(1)); val 276 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(val, priv->mmio + CRT_PLL1_HS); val 280 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val |= CRT_PLL1_HS_OUTER_BYPASS(1); val 281 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(val, priv->mmio + CRT_PLL1_HS); val 363 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c unsigned int val; val 387 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0); val 388 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0); val 389 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val |= HIBMC_CRT_DISP_CTL_TIMING(1); val 390 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val |= HIBMC_CRT_DISP_CTL_PLANE(1); val 392 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c display_ctrl_adjust(dev, mode, val); val 290 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 val; val 297 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = DSI_24BITS_1; val 300 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = DSI_24BITS_1; val 304 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c return val; val 310 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val) val 324 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + PHY_TST_CTRL1); val 333 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 val; val 338 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8); val 339 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + PHY_IF_CFG); val 344 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = readl(base + CLKMGR_CFG) | phy->clk_division; val 345 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + CLKMGR_CFG); val 367 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 val; val 411 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) + val 413 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_PLL_I, val); val 416 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p; val 417 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val); val 418 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) + val 420 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_PLL_V, val); val 434 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = readl(base + PHY_STATUS); val 435 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c if ((BIT(0) | BIT(2)) & val) val 457 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 val; val 460 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = dsi_get_dpi_color_coding(format); val 461 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + DPI_COLOR_CODING); val 463 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2; val 464 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1; val 465 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + DPI_CFG_POL); val 514 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 val; val 525 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = DSI_NON_BURST_SYNC_PULSES; val 527 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = DSI_NON_BURST_SYNC_EVENTS; val 529 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = DSI_BURST_SYNC_PULSES_1; val 530 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + VID_MODE_CFG); val 89 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h u32 mask, u32 val) val 95 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h tmp |= (val & mask) << bit_start; val 216 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h u32 mask, u32 val) val 222 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h tmp |= (val & mask) << bit_start; val 94 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) val 102 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c MASK(1), !!val); val 351 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 val; val 360 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = ade_read_reload_bit(base, RDMA_OFST + ch); val 361 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val); val 362 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_ctrl); val 363 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val); val 364 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_addr); val 365 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val); val 366 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_size); val 367 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val); val 368 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_stride); val 369 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val); val 370 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_space); val 371 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val); val 372 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_en); val 373 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val); val 378 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 val; val 380 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = ade_read_reload_bit(base, CLIP_OFST + ch); val 381 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val); val 382 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_CLIP_DISABLE(ch)); val 383 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val); val 384 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_CLIP_SIZE0(ch)); val 385 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val); val 386 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_CLIP_SIZE1(ch)); val 387 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val); val 393 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 val; val 395 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_XY0(ovly_ch)); val 396 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val); val 397 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_XY1(ovly_ch)); val 398 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val); val 399 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_CTL(ovly_ch)); val 400 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val); val 405 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 val; val 407 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = ade_read_reload_bit(base, OVLY_OFST + comp); val 408 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val); val 410 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val); val 411 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CTL); val 412 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val); val 671 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 val; val 683 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) | val 688 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(val, base + ADE_OVLY_CH_CTL(ovly_ch)); val 284 drivers/gpu/drm/i2c/ch7006_drv.c uint64_t val) val 296 drivers/gpu/drm/i2c/ch7006_drv.c priv->select_subconnector = val; val 303 drivers/gpu/drm/i2c/ch7006_drv.c priv->hmargin = val; val 311 drivers/gpu/drm/i2c/ch7006_drv.c priv->vmargin = val; val 322 drivers/gpu/drm/i2c/ch7006_drv.c priv->norm = val; val 327 drivers/gpu/drm/i2c/ch7006_drv.c priv->brightness = val; val 334 drivers/gpu/drm/i2c/ch7006_drv.c priv->contrast = val; val 341 drivers/gpu/drm/i2c/ch7006_drv.c priv->flicker = val; val 351 drivers/gpu/drm/i2c/ch7006_drv.c priv->scale = val; val 392 drivers/gpu/drm/i2c/ch7006_drv.c uint8_t val; val 401 drivers/gpu/drm/i2c/ch7006_drv.c ret = i2c_master_recv(client, &val, sizeof(val)); val 405 drivers/gpu/drm/i2c/ch7006_drv.c ch7006_info(client, "Detected version ID: %x\n", val); val 369 drivers/gpu/drm/i2c/ch7006_mode.c void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val) val 371 drivers/gpu/drm/i2c/ch7006_mode.c uint8_t buf[] = {addr, val}; val 382 drivers/gpu/drm/i2c/ch7006_mode.c uint8_t val; val 389 drivers/gpu/drm/i2c/ch7006_mode.c ret = i2c_master_recv(client, &val, sizeof(val)); val 393 drivers/gpu/drm/i2c/ch7006_mode.c return val; val 122 drivers/gpu/drm/i2c/ch7006_priv.h void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val); val 106 drivers/gpu/drm/i2c/sil164_drv.c sil164_write(struct i2c_client *client, uint8_t addr, uint8_t val) val 108 drivers/gpu/drm/i2c/sil164_drv.c uint8_t buf[] = {addr, val}; val 120 drivers/gpu/drm/i2c/sil164_drv.c uint8_t val; val 127 drivers/gpu/drm/i2c/sil164_drv.c ret = i2c_master_recv(client, &val, sizeof(val)); val 131 drivers/gpu/drm/i2c/sil164_drv.c return val; val 320 drivers/gpu/drm/i2c/sil164_drv.c uint64_t val) val 98 drivers/gpu/drm/i2c/tda9950.c static void tda9950_write(struct i2c_client *client, u8 addr, u8 val) val 100 drivers/gpu/drm/i2c/tda9950.c tda9950_write_range(client, addr, &val, 1); val 129 drivers/gpu/drm/i2c/tda9950.c u8 val; val 131 drivers/gpu/drm/i2c/tda9950.c ret = tda9950_read_range(client, addr, &val, 1); val 133 drivers/gpu/drm/i2c/tda9950.c val = 0; val 135 drivers/gpu/drm/i2c/tda9950.c return val; val 403 drivers/gpu/drm/i2c/tda998x_drv.c cec_write(struct tda998x_priv *priv, u16 addr, u8 val) val 405 drivers/gpu/drm/i2c/tda998x_drv.c u8 buf[] = {addr, val}; val 422 drivers/gpu/drm/i2c/tda998x_drv.c u8 val; val 432 drivers/gpu/drm/i2c/tda998x_drv.c .buf = &val, val 441 drivers/gpu/drm/i2c/tda998x_drv.c val = 0; val 444 drivers/gpu/drm/i2c/tda998x_drv.c return val; val 449 drivers/gpu/drm/i2c/tda998x_drv.c int val = cec_read(priv, REG_CEC_ENAMODS); val 451 drivers/gpu/drm/i2c/tda998x_drv.c if (val < 0) val 455 drivers/gpu/drm/i2c/tda998x_drv.c val |= mods; val 457 drivers/gpu/drm/i2c/tda998x_drv.c val &= ~mods; val 459 drivers/gpu/drm/i2c/tda998x_drv.c cec_write(priv, REG_CEC_ENAMODS, val); val 465 drivers/gpu/drm/i2c/tda998x_drv.c u8 val; val 471 drivers/gpu/drm/i2c/tda998x_drv.c val = cec_read(priv, REG_CEC_DES_FREQ2); val 472 drivers/gpu/drm/i2c/tda998x_drv.c val &= ~CEC_DES_FREQ2_DIS_AUTOCAL; val 473 drivers/gpu/drm/i2c/tda998x_drv.c cec_write(priv, REG_CEC_DES_FREQ2, val); val 638 drivers/gpu/drm/i2c/tda998x_drv.c u8 val = 0; val 641 drivers/gpu/drm/i2c/tda998x_drv.c ret = reg_read_range(priv, reg, &val, sizeof(val)); val 644 drivers/gpu/drm/i2c/tda998x_drv.c return val; val 648 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(struct tda998x_priv *priv, u16 reg, u8 val) val 651 drivers/gpu/drm/i2c/tda998x_drv.c u8 buf[] = {REG2ADDR(reg), val}; val 667 drivers/gpu/drm/i2c/tda998x_drv.c reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) val 670 drivers/gpu/drm/i2c/tda998x_drv.c u8 buf[] = {REG2ADDR(reg), val >> 8, val}; val 686 drivers/gpu/drm/i2c/tda998x_drv.c reg_set(struct tda998x_priv *priv, u16 reg, u8 val) val 692 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(priv, reg, old_val | val); val 696 drivers/gpu/drm/i2c/tda998x_drv.c reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) val 702 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(priv, reg, old_val & ~val); val 1192 drivers/gpu/drm/i2c/tda998x_drv.c u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); val 1194 drivers/gpu/drm/i2c/tda998x_drv.c return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : val 139 drivers/gpu/drm/i810/i810_drv.h #define I810_WRITE(reg, val) do { I810_DEREF(reg) = val; } while (0) val 142 drivers/gpu/drm/i810/i810_drv.h #define I810_WRITE16(reg, val) do { I810_DEREF16(reg) = val; } while (0) val 169 drivers/gpu/drm/i915/display/dvo_ch7017.c static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val) val 182 drivers/gpu/drm/i915/display/dvo_ch7017.c .buf = val, val 188 drivers/gpu/drm/i915/display/dvo_ch7017.c static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val) val 190 drivers/gpu/drm/i915/display/dvo_ch7017.c u8 buf[2] = { addr, val }; val 206 drivers/gpu/drm/i915/display/dvo_ch7017.c u8 val; val 215 drivers/gpu/drm/i915/display/dvo_ch7017.c if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val)) val 218 drivers/gpu/drm/i915/display/dvo_ch7017.c switch (val) { val 231 drivers/gpu/drm/i915/display/dvo_ch7017.c val, adapter->name, dvo->slave_addr); val 337 drivers/gpu/drm/i915/display/dvo_ch7017.c u8 val; val 339 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val); val 352 drivers/gpu/drm/i915/display/dvo_ch7017.c val & ~CH7017_LVDS_POWER_DOWN_EN); val 356 drivers/gpu/drm/i915/display/dvo_ch7017.c val | CH7017_LVDS_POWER_DOWN_EN); val 365 drivers/gpu/drm/i915/display/dvo_ch7017.c u8 val; val 367 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val); val 369 drivers/gpu/drm/i915/display/dvo_ch7017.c if (val & CH7017_LVDS_POWER_DOWN_EN) val 377 drivers/gpu/drm/i915/display/dvo_ch7017.c u8 val; val 381 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_read(dvo, reg, &val); \ val 382 drivers/gpu/drm/i915/display/dvo_ch7017.c DRM_DEBUG_KMS(#reg ": %02x\n", val); \ val 325 drivers/gpu/drm/i915/display/dvo_ch7xxx.c u8 val; val 327 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_readb(dvo, CH7xxx_PM, &val); val 329 drivers/gpu/drm/i915/display/dvo_ch7xxx.c if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP)) val 340 drivers/gpu/drm/i915/display/dvo_ch7xxx.c u8 val; val 343 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_readb(dvo, i, &val); val 344 drivers/gpu/drm/i915/display/dvo_ch7xxx.c DRM_DEBUG_KMS("%02X ", val); val 442 drivers/gpu/drm/i915/display/dvo_ivch.c u16 val; val 444 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR00, &val); val 445 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR00: 0x%04x\n", val); val 446 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR01, &val); val 447 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR01: 0x%04x\n", val); val 448 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR10, &val); val 449 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR10: 0x%04x\n", val); val 450 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR30, &val); val 451 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR30: 0x%04x\n", val); val 452 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR40, &val); val 453 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR40: 0x%04x\n", val); val 456 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR80, &val); val 457 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR80: 0x%04x\n", val); val 458 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR81, &val); val 459 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR81: 0x%04x\n", val); val 460 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR82, &val); val 461 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR82: 0x%04x\n", val); val 462 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR83, &val); val 463 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR83: 0x%04x\n", val); val 464 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR84, &val); val 465 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR84: 0x%04x\n", val); val 466 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR85, &val); val 467 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR85: 0x%04x\n", val); val 468 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR86, &val); val 469 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR86: 0x%04x\n", val); val 470 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR87, &val); val 471 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR87: 0x%04x\n", val); val 472 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR88, &val); val 473 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR88: 0x%04x\n", val); val 476 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR8E, &val); val 477 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR8E: 0x%04x\n", val); val 480 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR8F, &val); val 481 drivers/gpu/drm/i915/display/dvo_ivch.c DRM_DEBUG_KMS("VR8F: 0x%04x\n", val); val 247 drivers/gpu/drm/i915/display/dvo_sil164.c u8 val; val 249 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_FREQ_LO, &val); val 250 drivers/gpu/drm/i915/display/dvo_sil164.c DRM_DEBUG_KMS("SIL164_FREQ_LO: 0x%02x\n", val); val 251 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_FREQ_HI, &val); val 252 drivers/gpu/drm/i915/display/dvo_sil164.c DRM_DEBUG_KMS("SIL164_FREQ_HI: 0x%02x\n", val); val 253 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_REG8, &val); val 254 drivers/gpu/drm/i915/display/dvo_sil164.c DRM_DEBUG_KMS("SIL164_REG8: 0x%02x\n", val); val 255 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_REG9, &val); val 256 drivers/gpu/drm/i915/display/dvo_sil164.c DRM_DEBUG_KMS("SIL164_REG9: 0x%02x\n", val); val 257 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_REGC, &val); val 258 drivers/gpu/drm/i915/display/dvo_sil164.c DRM_DEBUG_KMS("SIL164_REGC: 0x%02x\n", val); val 268 drivers/gpu/drm/i915/display/dvo_tfp410.c u8 val, val2; val 270 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_REV, &val); val 271 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_REV: 0x%02X\n", val); val 272 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_CTL_1, &val); val 273 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_CTL1: 0x%02X\n", val); val 274 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_CTL_2, &val); val 275 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_CTL2: 0x%02X\n", val); val 276 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_CTL_3, &val); val 277 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_CTL3: 0x%02X\n", val); val 278 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_USERCFG, &val); val 279 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_USERCFG: 0x%02X\n", val); val 280 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_DLY, &val); val 281 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_DE_DLY: 0x%02X\n", val); val 282 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_CTL, &val); val 283 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_DE_CTL: 0x%02X\n", val); val 284 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_TOP, &val); val 285 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_DE_TOP: 0x%02X\n", val); val 286 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_CNT_LO, &val); val 288 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val); val 289 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_LIN_LO, &val); val 291 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val); val 292 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_H_RES_LO, &val); val 294 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val); val 295 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_V_RES_LO, &val); val 297 drivers/gpu/drm/i915/display/dvo_tfp410.c DRM_DEBUG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val); val 598 drivers/gpu/drm/i915/display/icl_dsi.c u32 val; val 602 drivers/gpu/drm/i915/display/icl_dsi.c val = I915_READ(ICL_DPCLKA_CFGCR0); val 604 drivers/gpu/drm/i915/display/icl_dsi.c val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); val 605 drivers/gpu/drm/i915/display/icl_dsi.c val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); val 607 drivers/gpu/drm/i915/display/icl_dsi.c I915_WRITE(ICL_DPCLKA_CFGCR0, val); val 611 drivers/gpu/drm/i915/display/icl_dsi.c val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); val 613 drivers/gpu/drm/i915/display/icl_dsi.c val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); val 615 drivers/gpu/drm/i915/display/icl_dsi.c I915_WRITE(ICL_DPCLKA_CFGCR0, val); val 54 drivers/gpu/drm/i915/display/intel_atomic.c u64 *val) val 62 drivers/gpu/drm/i915/display/intel_atomic.c *val = intel_conn_state->force_audio; val 64 drivers/gpu/drm/i915/display/intel_atomic.c *val = intel_conn_state->broadcast_rgb; val 86 drivers/gpu/drm/i915/display/intel_atomic.c u64 val) val 94 drivers/gpu/drm/i915/display/intel_atomic.c intel_conn_state->force_audio = val; val 99 drivers/gpu/drm/i915/display/intel_atomic.c intel_conn_state->broadcast_rgb = val; val 25 drivers/gpu/drm/i915/display/intel_atomic.h u64 *val); val 29 drivers/gpu/drm/i915/display/intel_atomic.h u64 val); val 1233 drivers/gpu/drm/i915/display/intel_bios.c static u8 translate_iboost(u8 val) val 1237 drivers/gpu/drm/i915/display/intel_bios.c if (val >= ARRAY_SIZE(mapping)) { val 1238 drivers/gpu/drm/i915/display/intel_bios.c DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); val 1241 drivers/gpu/drm/i915/display/intel_bios.c return mapping[val]; val 28 drivers/gpu/drm/i915/display/intel_bw.c u32 val = 0; val 34 drivers/gpu/drm/i915/display/intel_bw.c &val, NULL); val 38 drivers/gpu/drm/i915/display/intel_bw.c switch (val & 0xf) { val 52 drivers/gpu/drm/i915/display/intel_bw.c MISSING_CASE(val & 0xf); val 56 drivers/gpu/drm/i915/display/intel_bw.c qi->num_channels = (val & 0xf0) >> 4; val 57 drivers/gpu/drm/i915/display/intel_bw.c qi->num_points = (val & 0xf00) >> 8; val 68 drivers/gpu/drm/i915/display/intel_bw.c u32 val = 0, val2 = 0; val 74 drivers/gpu/drm/i915/display/intel_bw.c &val, &val2); val 78 drivers/gpu/drm/i915/display/intel_bw.c sp->dclk = val & 0xffff; val 79 drivers/gpu/drm/i915/display/intel_bw.c sp->t_rp = (val & 0xff0000) >> 16; val 80 drivers/gpu/drm/i915/display/intel_bw.c sp->t_rcd = (val & 0xff000000) >> 24; val 466 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 476 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); val 482 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >> val 485 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> val 530 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val, cmd = cdclk_state->voltage_level; val 558 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); val 559 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~DSPFREQGUAR_MASK; val 560 drivers/gpu/drm/i915/display/intel_cdclk.c val |= (cmd << DSPFREQGUAR_SHIFT); val 561 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); val 575 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); val 576 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~CCK_FREQUENCY_VALUES; val 577 drivers/gpu/drm/i915/display/intel_cdclk.c val |= divider; val 578 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); val 587 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); val 588 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~0x7f; val 595 drivers/gpu/drm/i915/display/intel_cdclk.c val |= 4500 / 250; /* 4.5 usec */ val 597 drivers/gpu/drm/i915/display/intel_cdclk.c val |= 3000 / 250; /* 3.0 usec */ val 598 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); val 617 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val, cmd = cdclk_state->voltage_level; val 640 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); val 641 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~DSPFREQGUAR_MASK_CHV; val 642 drivers/gpu/drm/i915/display/intel_cdclk.c val |= (cmd << DSPFREQGUAR_SHIFT_CHV); val 643 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); val 718 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 736 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); val 737 drivers/gpu/drm/i915/display/intel_cdclk.c val |= LCPLL_CD_SOURCE_FCLK; val 738 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(LCPLL_CTL, val); val 748 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); val 749 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~LCPLL_CLK_FREQ_MASK; val 756 drivers/gpu/drm/i915/display/intel_cdclk.c val |= LCPLL_CLK_FREQ_337_5_BDW; val 759 drivers/gpu/drm/i915/display/intel_cdclk.c val |= LCPLL_CLK_FREQ_450; val 762 drivers/gpu/drm/i915/display/intel_cdclk.c val |= LCPLL_CLK_FREQ_54O_BDW; val 765 drivers/gpu/drm/i915/display/intel_cdclk.c val |= LCPLL_CLK_FREQ_675_BDW; val 769 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(LCPLL_CTL, val); val 771 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); val 772 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~LCPLL_CD_SOURCE_FCLK; val 773 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(LCPLL_CTL, val); val 825 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 830 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL1_CTL); val 831 drivers/gpu/drm/i915/display/intel_cdclk.c if ((val & LCPLL_PLL_ENABLE) == 0) val 834 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) val 837 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(DPLL_CTRL1); val 839 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | val 845 drivers/gpu/drm/i915/display/intel_cdclk.c switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { val 857 drivers/gpu/drm/i915/display/intel_cdclk.c MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); val 942 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 955 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(DPLL_CTRL1); val 957 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | val 959 drivers/gpu/drm/i915/display/intel_cdclk.c val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); val 961 drivers/gpu/drm/i915/display/intel_cdclk.c val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, val 964 drivers/gpu/drm/i915/display/intel_cdclk.c val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, val 967 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(DPLL_CTRL1, val); val 1242 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 1247 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_ENABLE); val 1248 drivers/gpu/drm/i915/display/intel_cdclk.c if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) val 1251 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) val 1254 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_CTL); val 1255 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; val 1318 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 1320 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_CTL); val 1321 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~BXT_DE_PLL_RATIO_MASK; val 1322 drivers/gpu/drm/i915/display/intel_cdclk.c val |= BXT_DE_PLL_RATIO(ratio); val 1323 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(BXT_DE_PLL_CTL, val); val 1341 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val, divider; val 1386 drivers/gpu/drm/i915/display/intel_cdclk.c val = divider | skl_cdclk_decimal(cdclk); val 1388 drivers/gpu/drm/i915/display/intel_cdclk.c val |= BXT_CDCLK_CD2X_PIPE_NONE; val 1390 drivers/gpu/drm/i915/display/intel_cdclk.c val |= BXT_CDCLK_CD2X_PIPE(pipe); val 1396 drivers/gpu/drm/i915/display/intel_cdclk.c val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; val 1397 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(CDCLK_CTL, val); val 1531 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 1540 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_ENABLE); val 1541 drivers/gpu/drm/i915/display/intel_cdclk.c if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) val 1544 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) val 1547 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref; val 1590 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 1592 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_ENABLE); val 1593 drivers/gpu/drm/i915/display/intel_cdclk.c val &= ~BXT_DE_PLL_PLL_ENABLE; val 1594 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(BXT_DE_PLL_ENABLE, val); val 1606 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 1608 drivers/gpu/drm/i915/display/intel_cdclk.c val = CNL_CDCLK_PLL_RATIO(ratio); val 1609 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(BXT_DE_PLL_ENABLE, val); val 1611 drivers/gpu/drm/i915/display/intel_cdclk.c val |= BXT_DE_PLL_PLL_ENABLE; val 1612 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(BXT_DE_PLL_ENABLE, val); val 1627 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val, divider; val 1661 drivers/gpu/drm/i915/display/intel_cdclk.c val = divider | skl_cdclk_decimal(cdclk); val 1663 drivers/gpu/drm/i915/display/intel_cdclk.c val |= BXT_CDCLK_CD2X_PIPE_NONE; val 1665 drivers/gpu/drm/i915/display/intel_cdclk.c val |= BXT_CDCLK_CD2X_PIPE(pipe); val 1666 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(CDCLK_CTL, val); val 1883 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 1887 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(SKL_DSSM); val 1888 drivers/gpu/drm/i915/display/intel_cdclk.c switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) { val 1890 drivers/gpu/drm/i915/display/intel_cdclk.c MISSING_CASE(val); val 1903 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_ENABLE); val 1904 drivers/gpu/drm/i915/display/intel_cdclk.c if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || val 1905 drivers/gpu/drm/i915/display/intel_cdclk.c (val & BXT_DE_PLL_LOCK) == 0) { val 1915 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; val 1917 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(CDCLK_CTL); val 1918 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0); val 1934 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val; val 1944 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(CDCLK_CTL); val 1946 drivers/gpu/drm/i915/display/intel_cdclk.c if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0) val 1949 drivers/gpu/drm/i915/display/intel_cdclk.c if ((val & CDCLK_FREQ_DECIMAL_MASK) != val 430 drivers/gpu/drm/i915/display/intel_color.c u32 val; val 432 drivers/gpu/drm/i915/display/intel_color.c val = I915_READ(PIPECONF(pipe)); val 433 drivers/gpu/drm/i915/display/intel_color.c val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX; val 434 drivers/gpu/drm/i915/display/intel_color.c val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); val 435 drivers/gpu/drm/i915/display/intel_color.c I915_WRITE(PIPECONF(pipe), val); val 443 drivers/gpu/drm/i915/display/intel_color.c u32 val; val 445 drivers/gpu/drm/i915/display/intel_color.c val = I915_READ(PIPECONF(pipe)); val 446 drivers/gpu/drm/i915/display/intel_color.c val &= ~PIPECONF_GAMMA_MODE_MASK_ILK; val 447 drivers/gpu/drm/i915/display/intel_color.c val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); val 448 drivers/gpu/drm/i915/display/intel_color.c I915_WRITE(PIPECONF(pipe), val); val 468 drivers/gpu/drm/i915/display/intel_color.c u32 val = 0; val 476 drivers/gpu/drm/i915/display/intel_color.c val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; val 478 drivers/gpu/drm/i915/display/intel_color.c val |= SKL_BOTTOM_COLOR_CSC_ENABLE; val 479 drivers/gpu/drm/i915/display/intel_color.c I915_WRITE(SKL_BOTTOM_COLOR(pipe), val); val 49 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val; val 51 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW3(phy)); val 52 drivers/gpu/drm/i915/display/intel_combo_phy.c switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { val 54 drivers/gpu/drm/i915/display/intel_combo_phy.c MISSING_CASE(val); val 80 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val; val 84 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW1(phy)); val 85 drivers/gpu/drm/i915/display/intel_combo_phy.c val &= ~((0xff << 16) | 0xff); val 86 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= procmon->dw1; val 87 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PORT_COMP_DW1(phy), val); val 97 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val = I915_READ(reg); val 99 drivers/gpu/drm/i915/display/intel_combo_phy.c if ((val & mask) != expected_val) { val 103 drivers/gpu/drm/i915/display/intel_combo_phy.c reg.reg, val, mask, expected_val); val 152 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val; val 154 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(CHICKEN_MISC_2); val 155 drivers/gpu/drm/i915/display/intel_combo_phy.c val &= ~CNL_COMP_PWR_DOWN; val 156 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(CHICKEN_MISC_2, val); val 161 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(CNL_PORT_COMP_DW0); val 162 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= COMP_INIT; val 163 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(CNL_PORT_COMP_DW0, val); val 165 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(CNL_PORT_CL1CM_DW5); val 166 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= CL_POWER_DOWN_ENABLE; val 167 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(CNL_PORT_CL1CM_DW5, val); val 172 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val; val 177 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(CHICKEN_MISC_2); val 178 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= CNL_COMP_PWR_DOWN; val 179 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(CHICKEN_MISC_2, val); val 219 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val; val 260 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_CL_DW10(phy)); val 261 drivers/gpu/drm/i915/display/intel_combo_phy.c val &= ~PWR_DOWN_LN_MASK; val 262 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= lane_mask << PWR_DOWN_LN_SHIFT; val 263 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PORT_CL_DW10(phy), val); val 266 drivers/gpu/drm/i915/display/intel_combo_phy.c static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) val 279 drivers/gpu/drm/i915/display/intel_combo_phy.c return val | ICL_PHY_MISC_MUX_DDID; val 289 drivers/gpu/drm/i915/display/intel_combo_phy.c return val & ~ICL_PHY_MISC_MUX_DDID; val 297 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val; val 321 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PHY_MISC(phy)); val 323 drivers/gpu/drm/i915/display/intel_combo_phy.c val = ehl_combo_phy_a_mux(dev_priv, val); val 324 drivers/gpu/drm/i915/display/intel_combo_phy.c val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; val 325 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PHY_MISC(phy), val); val 331 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW8(phy)); val 332 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= IREFGEN; val 333 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PORT_COMP_DW8(phy), val); val 336 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW0(phy)); val 337 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= COMP_INIT; val 338 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PORT_COMP_DW0(phy), val); val 340 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_CL_DW5(phy)); val 341 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= CL_POWER_DOWN_ENABLE; val 342 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PORT_CL_DW5(phy), val); val 351 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val; val 366 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PHY_MISC(phy)); val 367 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; val 368 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PHY_MISC(phy), val); val 371 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW0(phy)); val 372 drivers/gpu/drm/i915/display/intel_combo_phy.c val &= ~COMP_INIT; val 373 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PORT_COMP_DW0(phy), val); val 76 drivers/gpu/drm/i915/display/intel_crt.c u32 val; val 78 drivers/gpu/drm/i915/display/intel_crt.c val = I915_READ(adpa_reg); val 82 drivers/gpu/drm/i915/display/intel_crt.c *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; val 84 drivers/gpu/drm/i915/display/intel_crt.c *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; val 86 drivers/gpu/drm/i915/display/intel_crt.c return val & ADPA_DAC_ENABLE; val 1389 drivers/gpu/drm/i915/display/intel_ddi.c u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; val 1391 drivers/gpu/drm/i915/display/intel_ddi.c switch (val) { val 1403 drivers/gpu/drm/i915/display/intel_ddi.c MISSING_CASE(val); val 1612 drivers/gpu/drm/i915/display/intel_ddi.c u32 val, pll; val 1614 drivers/gpu/drm/i915/display/intel_ddi.c val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); val 1615 drivers/gpu/drm/i915/display/intel_ddi.c switch (val & PORT_CLK_SEL_MASK) { val 1857 drivers/gpu/drm/i915/display/intel_ddi.c u32 val = I915_READ(reg); val 1860 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK | val 1863 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | val 1866 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(reg, val); val 2335 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 2350 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); val 2351 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~SCALING_MODE_SEL_MASK; val 2352 drivers/gpu/drm/i915/display/intel_ddi.c val |= SCALING_MODE_SEL(2); val 2353 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); val 2356 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); val 2357 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | val 2359 drivers/gpu/drm/i915/display/intel_ddi.c val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); val 2360 drivers/gpu/drm/i915/display/intel_ddi.c val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); val 2362 drivers/gpu/drm/i915/display/intel_ddi.c val |= RCOMP_SCALAR(0x98); val 2363 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); val 2368 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); val 2369 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | val 2371 drivers/gpu/drm/i915/display/intel_ddi.c val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); val 2372 drivers/gpu/drm/i915/display/intel_ddi.c val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); val 2373 drivers/gpu/drm/i915/display/intel_ddi.c val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); val 2374 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); val 2379 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); val 2380 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~RTERM_SELECT_MASK; val 2381 drivers/gpu/drm/i915/display/intel_ddi.c val |= RTERM_SELECT(6); val 2382 drivers/gpu/drm/i915/display/intel_ddi.c val |= TAP3_DISABLE; val 2383 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); val 2386 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); val 2387 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~N_SCALAR_MASK; val 2388 drivers/gpu/drm/i915/display/intel_ddi.c val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); val 2389 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); val 2398 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 2415 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); val 2417 drivers/gpu/drm/i915/display/intel_ddi.c val |= COMMON_KEEPER_EN; val 2419 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~COMMON_KEEPER_EN; val 2420 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); val 2430 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); val 2431 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~LOADGEN_SELECT; val 2435 drivers/gpu/drm/i915/display/intel_ddi.c val |= LOADGEN_SELECT; val 2437 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); val 2441 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_CL1CM_DW5); val 2442 drivers/gpu/drm/i915/display/intel_ddi.c val |= SUS_CLOCK_CONFIG; val 2443 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_CL1CM_DW5, val); val 2446 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); val 2447 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~TX_TRAINING_EN; val 2448 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); val 2454 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); val 2455 drivers/gpu/drm/i915/display/intel_ddi.c val |= TX_TRAINING_EN; val 2456 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); val 2464 drivers/gpu/drm/i915/display/intel_ddi.c u32 n_entries, val; val 2478 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); val 2479 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | val 2481 drivers/gpu/drm/i915/display/intel_ddi.c val |= SCALING_MODE_SEL(0x2); val 2482 drivers/gpu/drm/i915/display/intel_ddi.c val |= RTERM_SELECT(0x6); val 2483 drivers/gpu/drm/i915/display/intel_ddi.c val |= TAP3_DISABLE; val 2484 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); val 2487 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); val 2488 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | val 2490 drivers/gpu/drm/i915/display/intel_ddi.c val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); val 2491 drivers/gpu/drm/i915/display/intel_ddi.c val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); val 2493 drivers/gpu/drm/i915/display/intel_ddi.c val |= RCOMP_SCALAR(0x98); val 2494 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); val 2499 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); val 2500 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | val 2502 drivers/gpu/drm/i915/display/intel_ddi.c val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); val 2503 drivers/gpu/drm/i915/display/intel_ddi.c val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); val 2504 drivers/gpu/drm/i915/display/intel_ddi.c val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); val 2505 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); val 2509 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); val 2510 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~N_SCALAR_MASK; val 2511 drivers/gpu/drm/i915/display/intel_ddi.c val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); val 2512 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); val 2523 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 2541 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); val 2543 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~COMMON_KEEPER_EN; val 2545 drivers/gpu/drm/i915/display/intel_ddi.c val |= COMMON_KEEPER_EN; val 2546 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); val 2556 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); val 2557 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~LOADGEN_SELECT; val 2561 drivers/gpu/drm/i915/display/intel_ddi.c val |= LOADGEN_SELECT; val 2563 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); val 2567 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_CL_DW5(phy)); val 2568 drivers/gpu/drm/i915/display/intel_ddi.c val |= SUS_CLOCK_CONFIG; val 2569 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_CL_DW5(phy), val); val 2572 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); val 2573 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~TX_TRAINING_EN; val 2574 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); val 2580 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); val 2581 drivers/gpu/drm/i915/display/intel_ddi.c val |= TX_TRAINING_EN; val 2582 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); val 2592 drivers/gpu/drm/i915/display/intel_ddi.c u32 n_entries, val; val 2606 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_LINK_PARAMS(ln, port)); val 2607 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CRI_USE_FS32; val 2608 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val); val 2610 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_LINK_PARAMS(ln, port)); val 2611 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CRI_USE_FS32; val 2612 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val); val 2617 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_SWINGCTRL(ln, port)); val 2618 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val 2619 drivers/gpu/drm/i915/display/intel_ddi.c val |= CRI_TXDEEMPH_OVERRIDE_17_12( val 2621 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val); val 2623 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_SWINGCTRL(ln, port)); val 2624 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val 2625 drivers/gpu/drm/i915/display/intel_ddi.c val |= CRI_TXDEEMPH_OVERRIDE_17_12( val 2627 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val); val 2632 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_DRVCTRL(ln, port)); val 2633 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | val 2635 drivers/gpu/drm/i915/display/intel_ddi.c val |= CRI_TXDEEMPH_OVERRIDE_5_0( val 2640 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX1_DRVCTRL(ln, port), val); val 2642 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_DRVCTRL(ln, port)); val 2643 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | val 2645 drivers/gpu/drm/i915/display/intel_ddi.c val |= CRI_TXDEEMPH_OVERRIDE_5_0( val 2650 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX2_DRVCTRL(ln, port), val); val 2661 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_CLKHUB(ln, port)); val 2663 drivers/gpu/drm/i915/display/intel_ddi.c val |= CFG_LOW_RATE_LKREN_EN; val 2665 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CFG_LOW_RATE_LKREN_EN; val 2666 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_CLKHUB(ln, port), val); val 2671 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_DCC(ln, port)); val 2672 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; val 2674 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; val 2676 drivers/gpu/drm/i915/display/intel_ddi.c val |= CFG_AMI_CK_DIV_OVERRIDE_EN | val 2679 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX1_DCC(ln, port), val); val 2681 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_DCC(ln, port)); val 2682 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; val 2684 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; val 2686 drivers/gpu/drm/i915/display/intel_ddi.c val |= CFG_AMI_CK_DIV_OVERRIDE_EN | val 2689 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX2_DCC(ln, port), val); val 2694 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_PISO_READLOAD(ln, port)); val 2695 drivers/gpu/drm/i915/display/intel_ddi.c val |= CRI_CALCINIT; val 2696 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val); val 2698 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_PISO_READLOAD(ln, port)); val 2699 drivers/gpu/drm/i915/display/intel_ddi.c val |= CRI_CALCINIT; val 2700 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val); val 2795 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 2799 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_DPCLKA_CFGCR0); val 2800 drivers/gpu/drm/i915/display/intel_ddi.c WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); val 2813 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); val 2814 drivers/gpu/drm/i915/display/intel_ddi.c val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); val 2815 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_DPCLKA_CFGCR0, val); val 2819 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); val 2820 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_DPCLKA_CFGCR0, val); val 2829 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 2833 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_DPCLKA_CFGCR0); val 2834 drivers/gpu/drm/i915/display/intel_ddi.c val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); val 2835 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_DPCLKA_CFGCR0, val); val 2843 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 2893 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_DPCLKA_CFGCR0); val 2897 drivers/gpu/drm/i915/display/intel_ddi.c bool ddi_clk_ungated = !(val & val 2913 drivers/gpu/drm/i915/display/intel_ddi.c val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); val 2914 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(ICL_DPCLKA_CFGCR0, val); val 2924 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 2944 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DPCLKA_CFGCR0); val 2945 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); val 2946 drivers/gpu/drm/i915/display/intel_ddi.c val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); val 2947 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DPCLKA_CFGCR0, val); val 2954 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DPCLKA_CFGCR0); val 2955 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); val 2956 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DPCLKA_CFGCR0, val); val 2959 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DPLL_CTRL2); val 2961 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | val 2963 drivers/gpu/drm/i915/display/intel_ddi.c val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | val 2966 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DPLL_CTRL2, val); val 3001 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 3008 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_DP_MODE(ln, port)); val 3009 drivers/gpu/drm/i915/display/intel_ddi.c val |= MG_DP_MODE_CFG_TR2PWR_GATING | val 3014 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_DP_MODE(ln, port), val); val 3017 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_MISC_SUS0(tc_port)); val 3018 drivers/gpu/drm/i915/display/intel_ddi.c val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) | val 3025 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_MISC_SUS0(tc_port), val); val 3033 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 3040 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_DP_MODE(ln, port)); val 3041 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | val 3046 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_DP_MODE(ln, port), val); val 3049 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_MISC_SUS0(tc_port)); val 3050 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK | val 3057 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_MISC_SUS0(tc_port), val); val 3137 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 3142 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); val 3143 drivers/gpu/drm/i915/display/intel_ddi.c val |= DP_TP_CTL_FEC_ENABLE; val 3144 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); val 3156 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 3161 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); val 3162 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~DP_TP_CTL_FEC_ENABLE; val 3163 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); val 3328 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 3330 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DDI_BUF_CTL(port)); val 3331 drivers/gpu/drm/i915/display/intel_ddi.c if (val & DDI_BUF_CTL_ENABLE) { val 3332 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~DDI_BUF_CTL_ENABLE; val 3333 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DDI_BUF_CTL(port), val); val 3337 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); val 3338 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); val 3339 drivers/gpu/drm/i915/display/intel_ddi.c val |= DP_TP_CTL_LINK_TRAIN_PAT1; val 3340 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); val 3440 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 3448 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); val 3449 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~FDI_RX_ENABLE; val 3450 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), val); val 3455 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_MISC(PIPE_A)); val 3456 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); val 3457 drivers/gpu/drm/i915/display/intel_ddi.c val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); val 3458 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_MISC(PIPE_A), val); val 3460 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); val 3461 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~FDI_PCDCLK; val 3462 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), val); val 3464 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); val 3465 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~FDI_RX_PLL_ENABLE; val 3466 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), val); val 3533 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 3535 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(reg); val 3538 drivers/gpu/drm/i915/display/intel_ddi.c val |= DDIE_TRAINING_OVERRIDE_ENABLE | val 3541 drivers/gpu/drm/i915/display/intel_ddi.c val |= DDI_TRAINING_OVERRIDE_ENABLE | val 3544 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(reg, val); val 3550 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | val 3553 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | val 3556 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(reg, val); val 3765 drivers/gpu/drm/i915/display/intel_ddi.c u32 val; val 3769 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DDI_BUF_CTL(port)); val 3770 drivers/gpu/drm/i915/display/intel_ddi.c if (val & DDI_BUF_CTL_ENABLE) { val 3771 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~DDI_BUF_CTL_ENABLE; val 3772 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DDI_BUF_CTL(port), val); val 3776 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); val 3777 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); val 3778 drivers/gpu/drm/i915/display/intel_ddi.c val |= DP_TP_CTL_LINK_TRAIN_PAT1; val 3779 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); val 3786 drivers/gpu/drm/i915/display/intel_ddi.c val = DP_TP_CTL_ENABLE | val 3789 drivers/gpu/drm/i915/display/intel_ddi.c val |= DP_TP_CTL_MODE_MST; val 3791 drivers/gpu/drm/i915/display/intel_ddi.c val |= DP_TP_CTL_MODE_SST; val 3793 drivers/gpu/drm/i915/display/intel_ddi.c val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; val 3795 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); val 175 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 178 drivers/gpu/drm/i915/display/intel_display.c val = vlv_cck_read(dev_priv, reg); val 179 drivers/gpu/drm/i915/display/intel_display.c divider = val & CCK_FREQUENCY_VALUES; val 181 drivers/gpu/drm/i915/display/intel_display.c WARN((val & CCK_FREQUENCY_STATUS) != val 1092 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1095 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(DPLL(pipe)); val 1096 drivers/gpu/drm/i915/display/intel_display.c cur_state = !!(val & DPLL_VCO_ENABLE); val 1105 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1109 drivers/gpu/drm/i915/display/intel_display.c val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); val 1112 drivers/gpu/drm/i915/display/intel_display.c cur_state = val & DSI_PLL_VCO_EN; val 1127 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); val 1128 drivers/gpu/drm/i915/display/intel_display.c cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); val 1130 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(FDI_TX_CTL(pipe)); val 1131 drivers/gpu/drm/i915/display/intel_display.c cur_state = !!(val & FDI_TX_ENABLE); val 1143 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1146 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(FDI_RX_CTL(pipe)); val 1147 drivers/gpu/drm/i915/display/intel_display.c cur_state = !!(val & FDI_RX_ENABLE); val 1158 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1168 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(FDI_TX_CTL(pipe)); val 1169 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); val 1175 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1178 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(FDI_RX_CTL(pipe)); val 1179 drivers/gpu/drm/i915/display/intel_display.c cur_state = !!(val & FDI_RX_PLL_ENABLE); val 1188 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1232 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(pp_reg); val 1233 drivers/gpu/drm/i915/display/intel_display.c if (!(val & PANEL_POWER_ON) || val 1234 drivers/gpu/drm/i915/display/intel_display.c ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) val 1258 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(PIPECONF(cpu_transcoder)); val 1259 drivers/gpu/drm/i915/display/intel_display.c cur_state = !!(val & PIPECONF_ENABLE); val 1304 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1307 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PCH_TRANSCONF(pipe)); val 1308 drivers/gpu/drm/i915/display/intel_display.c enabled = !!(val & TRANS_ENABLE); val 1548 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1553 drivers/gpu/drm/i915/display/intel_display.c val = DPLL_INTEGRATED_REF_CLK_VLV | val 1556 drivers/gpu/drm/i915/display/intel_display.c val |= DPLL_INTEGRATED_CRI_CLK_VLV; val 1558 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), val); val 1565 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1570 drivers/gpu/drm/i915/display/intel_display.c val = DPLL_SSC_REF_CLK_CHV | val 1573 drivers/gpu/drm/i915/display/intel_display.c val |= DPLL_INTEGRATED_CRI_CLK_VLV; val 1575 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), val); val 1581 drivers/gpu/drm/i915/display/intel_display.c val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); val 1582 drivers/gpu/drm/i915/display/intel_display.c val &= ~DPIO_DCLKP_EN; val 1583 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); val 1626 drivers/gpu/drm/i915/display/intel_display.c u32 val, pipeconf_val; val 1639 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); val 1640 drivers/gpu/drm/i915/display/intel_display.c val |= TRANS_CHICKEN2_TIMING_OVERRIDE; val 1641 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val); val 1645 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); val 1654 drivers/gpu/drm/i915/display/intel_display.c val &= ~PIPECONF_BPC_MASK; val 1656 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_8BPC; val 1658 drivers/gpu/drm/i915/display/intel_display.c val |= pipeconf_val & PIPECONF_BPC_MASK; val 1661 drivers/gpu/drm/i915/display/intel_display.c val &= ~TRANS_INTERLACE_MASK; val 1665 drivers/gpu/drm/i915/display/intel_display.c val |= TRANS_LEGACY_INTERLACED_ILK; val 1667 drivers/gpu/drm/i915/display/intel_display.c val |= TRANS_INTERLACED; val 1669 drivers/gpu/drm/i915/display/intel_display.c val |= TRANS_PROGRESSIVE; val 1672 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val | TRANS_ENABLE); val 1680 drivers/gpu/drm/i915/display/intel_display.c u32 val, pipeconf_val; val 1687 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(TRANS_CHICKEN2(PIPE_A)); val 1688 drivers/gpu/drm/i915/display/intel_display.c val |= TRANS_CHICKEN2_TIMING_OVERRIDE; val 1689 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); val 1691 drivers/gpu/drm/i915/display/intel_display.c val = TRANS_ENABLE; val 1696 drivers/gpu/drm/i915/display/intel_display.c val |= TRANS_INTERLACED; val 1698 drivers/gpu/drm/i915/display/intel_display.c val |= TRANS_PROGRESSIVE; val 1700 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(LPT_TRANSCONF, val); val 1710 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1720 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); val 1721 drivers/gpu/drm/i915/display/intel_display.c val &= ~TRANS_ENABLE; val 1722 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val); val 1730 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); val 1731 drivers/gpu/drm/i915/display/intel_display.c val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; val 1732 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val); val 1738 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1740 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(LPT_TRANSCONF); val 1741 drivers/gpu/drm/i915/display/intel_display.c val &= ~TRANS_ENABLE; val 1742 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(LPT_TRANSCONF, val); val 1749 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(TRANS_CHICKEN2(PIPE_A)); val 1750 drivers/gpu/drm/i915/display/intel_display.c val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; val 1751 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); val 1800 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1830 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); val 1831 drivers/gpu/drm/i915/display/intel_display.c if (val & PIPECONF_ENABLE) { val 1837 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val | PIPECONF_ENABLE); val 1858 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 1871 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); val 1872 drivers/gpu/drm/i915/display/intel_display.c if ((val & PIPECONF_ENABLE) == 0) val 1880 drivers/gpu/drm/i915/display/intel_display.c val &= ~PIPECONF_DOUBLE_WIDE; val 1884 drivers/gpu/drm/i915/display/intel_display.c val &= ~PIPECONF_ENABLE; val 1886 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val); val 1887 drivers/gpu/drm/i915/display/intel_display.c if ((val & PIPECONF_ENABLE) == 0) val 3885 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 3897 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(DSPCNTR(i9xx_plane)); val 3899 drivers/gpu/drm/i915/display/intel_display.c ret = val & DISPLAY_PLANE_ENABLE; val 3904 drivers/gpu/drm/i915/display/intel_display.c *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> val 6409 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(CLKGATE_DIS_PSL(pipe)); val 6413 drivers/gpu/drm/i915/display/intel_display.c val |= mask; val 6415 drivers/gpu/drm/i915/display/intel_display.c val &= ~mask; val 6417 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(CLKGATE_DIS_PSL(pipe), val); val 6424 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 6426 drivers/gpu/drm/i915/display/intel_display.c val = MBUS_DBOX_A_CREDIT(2); val 6429 drivers/gpu/drm/i915/display/intel_display.c val |= MBUS_DBOX_BW_CREDIT(2); val 6430 drivers/gpu/drm/i915/display/intel_display.c val |= MBUS_DBOX_B_CREDIT(12); val 6432 drivers/gpu/drm/i915/display/intel_display.c val |= MBUS_DBOX_BW_CREDIT(1); val 6433 drivers/gpu/drm/i915/display/intel_display.c val |= MBUS_DBOX_B_CREDIT(8); val 6436 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); val 8597 drivers/gpu/drm/i915/display/intel_display.c u32 val, base, offset; val 8618 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(DSPCNTR(i9xx_plane)); val 8621 drivers/gpu/drm/i915/display/intel_display.c if (val & DISPPLANE_TILED) { val 8626 drivers/gpu/drm/i915/display/intel_display.c if (val & DISPPLANE_ROTATE_180) val 8631 drivers/gpu/drm/i915/display/intel_display.c val & DISPPLANE_MIRROR) val 8634 drivers/gpu/drm/i915/display/intel_display.c pixel_format = val & DISPPLANE_PIXFORMAT_MASK; val 8652 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PIPESRC(pipe)); val 8653 drivers/gpu/drm/i915/display/intel_display.c fb->width = ((val >> 16) & 0xfff) + 1; val 8654 drivers/gpu/drm/i915/display/intel_display.c fb->height = ((val >> 0) & 0xfff) + 1; val 8656 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(DSPSTRIDE(i9xx_plane)); val 8657 drivers/gpu/drm/i915/display/intel_display.c fb->pitches[0] = val & 0xffffffc0; val 8888 drivers/gpu/drm/i915/display/intel_display.c u32 val, final; val 8943 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PCH_DREF_CONTROL); val 8949 drivers/gpu/drm/i915/display/intel_display.c final = val; val 8978 drivers/gpu/drm/i915/display/intel_display.c if (final == val) val 8982 drivers/gpu/drm/i915/display/intel_display.c val &= ~DREF_NONSPREAD_SOURCE_MASK; val 8985 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_NONSPREAD_CK505_ENABLE; val 8987 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_NONSPREAD_SOURCE_ENABLE; val 8990 drivers/gpu/drm/i915/display/intel_display.c val &= ~DREF_SSC_SOURCE_MASK; val 8991 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_SSC_SOURCE_ENABLE; val 8996 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_SSC1_ENABLE; val 8998 drivers/gpu/drm/i915/display/intel_display.c val &= ~DREF_SSC1_ENABLE; val 9001 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PCH_DREF_CONTROL, val); val 9005 drivers/gpu/drm/i915/display/intel_display.c val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; val 9011 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; val 9013 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; val 9015 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; val 9017 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PCH_DREF_CONTROL, val); val 9023 drivers/gpu/drm/i915/display/intel_display.c val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; val 9026 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; val 9028 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PCH_DREF_CONTROL, val); val 9036 drivers/gpu/drm/i915/display/intel_display.c val &= ~DREF_SSC_SOURCE_MASK; val 9037 drivers/gpu/drm/i915/display/intel_display.c val |= DREF_SSC_SOURCE_DISABLE; val 9040 drivers/gpu/drm/i915/display/intel_display.c val &= ~DREF_SSC1_ENABLE; val 9042 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PCH_DREF_CONTROL, val); val 9048 drivers/gpu/drm/i915/display/intel_display.c BUG_ON(val != final); val 9392 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 9394 drivers/gpu/drm/i915/display/intel_display.c val = 0; val 9398 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_6BPC; val 9401 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_8BPC; val 9404 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_10BPC; val 9407 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_12BPC; val 9415 drivers/gpu/drm/i915/display/intel_display.c val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); val 9418 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_INTERLACED_ILK; val 9420 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_PROGRESSIVE; val 9423 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_COLOR_RANGE_SELECT; val 9425 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); val 9427 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPECONF(pipe), val); val 9436 drivers/gpu/drm/i915/display/intel_display.c u32 val = 0; val 9439 drivers/gpu/drm/i915/display/intel_display.c val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); val 9442 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_INTERLACED_ILK; val 9444 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_PROGRESSIVE; val 9446 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPECONF(cpu_transcoder), val); val 9454 drivers/gpu/drm/i915/display/intel_display.c u32 val = 0; val 9458 drivers/gpu/drm/i915/display/intel_display.c val |= PIPEMISC_DITHER_6_BPC; val 9461 drivers/gpu/drm/i915/display/intel_display.c val |= PIPEMISC_DITHER_8_BPC; val 9464 drivers/gpu/drm/i915/display/intel_display.c val |= PIPEMISC_DITHER_10_BPC; val 9467 drivers/gpu/drm/i915/display/intel_display.c val |= PIPEMISC_DITHER_12_BPC; val 9475 drivers/gpu/drm/i915/display/intel_display.c val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; val 9479 drivers/gpu/drm/i915/display/intel_display.c val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; val 9482 drivers/gpu/drm/i915/display/intel_display.c val |= PIPEMISC_YUV420_ENABLE | val 9488 drivers/gpu/drm/i915/display/intel_display.c val |= PIPEMISC_HDR_MODE_PRECISION; val 9490 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPEMISC(crtc->pipe), val); val 9800 drivers/gpu/drm/i915/display/intel_display.c u32 val, base, offset, stride_mult, tiling, alpha; val 9821 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PLANE_CTL(pipe, plane_id)); val 9824 drivers/gpu/drm/i915/display/intel_display.c pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK; val 9826 drivers/gpu/drm/i915/display/intel_display.c pixel_format = val & PLANE_CTL_FORMAT_MASK; val 9832 drivers/gpu/drm/i915/display/intel_display.c alpha = val & PLANE_CTL_ALPHA_MASK; val 9836 drivers/gpu/drm/i915/display/intel_display.c val & PLANE_CTL_ORDER_RGBX, alpha); val 9839 drivers/gpu/drm/i915/display/intel_display.c tiling = val & PLANE_CTL_TILED_MASK; val 9850 drivers/gpu/drm/i915/display/intel_display.c if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) val 9856 drivers/gpu/drm/i915/display/intel_display.c if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) val 9870 drivers/gpu/drm/i915/display/intel_display.c switch (val & PLANE_CTL_ROTATE_MASK) { val 9886 drivers/gpu/drm/i915/display/intel_display.c val & PLANE_CTL_FLIP_HORIZONTAL) val 9894 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PLANE_SIZE(pipe, plane_id)); val 9895 drivers/gpu/drm/i915/display/intel_display.c fb->height = ((val >> 16) & 0xfff) + 1; val 9896 drivers/gpu/drm/i915/display/intel_display.c fb->width = ((val >> 0) & 0x1fff) + 1; val 9898 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PLANE_STRIDE(pipe, plane_id)); val 9900 drivers/gpu/drm/i915/display/intel_display.c fb->pitches[0] = (val & 0x3ff) * stride_mult; val 11006 drivers/gpu/drm/i915/display/intel_display.c u32 val; val 11018 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(CURCNTR(plane->pipe)); val 11020 drivers/gpu/drm/i915/display/intel_display.c ret = val & MCURSOR_MODE; val 11025 drivers/gpu/drm/i915/display/intel_display.c *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >> val 15296 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(PP_CONTROL(pps_idx)); val 15298 drivers/gpu/drm/i915/display/intel_display.c val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; val 15299 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PP_CONTROL(pps_idx), val); val 16884 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(hdmi_reg); val 16886 drivers/gpu/drm/i915/display/intel_display.c if (val & SDVO_ENABLE || val 16887 drivers/gpu/drm/i915/display/intel_display.c (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) val 16893 drivers/gpu/drm/i915/display/intel_display.c val &= ~SDVO_PIPE_SEL_MASK; val 16894 drivers/gpu/drm/i915/display/intel_display.c val |= SDVO_PIPE_SEL(PIPE_A); val 16896 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(hdmi_reg, val); val 16902 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(dp_reg); val 16904 drivers/gpu/drm/i915/display/intel_display.c if (val & DP_PORT_EN || val 16905 drivers/gpu/drm/i915/display/intel_display.c (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) val 16911 drivers/gpu/drm/i915/display/intel_display.c val &= ~DP_PIPE_SEL_MASK; val 16912 drivers/gpu/drm/i915/display/intel_display.c val |= DP_PIPE_SEL(PIPE_A); val 16914 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(dp_reg, val); val 391 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 407 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); val 408 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); val 415 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx)); val 416 drivers/gpu/drm/i915/display/intel_display_power.c val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; val 417 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val); val 433 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 438 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); val 439 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); val 452 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 455 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); val 456 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); val 459 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(ICL_PORT_CL_DW12(phy)); val 460 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX); val 474 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); val 475 drivers/gpu/drm/i915/display/intel_display_power.c val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; val 476 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); val 487 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 490 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(ICL_PORT_CL_DW12(phy)); val 491 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX); val 494 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); val 495 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); val 586 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 590 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DP_AUX_CH_CTL(aux_ch)); val 591 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~DP_AUX_CH_CTL_TBT_IO; val 593 drivers/gpu/drm/i915/display/intel_display_power.c val |= DP_AUX_CH_CTL_TBT_IO; val 594 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DP_AUX_CH_CTL(aux_ch), val); val 621 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 623 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); val 633 drivers/gpu/drm/i915/display/intel_display_power.c val |= I915_READ(regs->bios); val 635 drivers/gpu/drm/i915/display/intel_display_power.c return (val & mask) == mask; val 729 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 731 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); val 734 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state, val); val 735 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state = val; val 763 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 769 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DC_STATE_EN); val 772 drivers/gpu/drm/i915/display/intel_display_power.c val & mask, state); val 775 drivers/gpu/drm/i915/display/intel_display_power.c if ((val & mask) != dev_priv->csr.dc_state) val 777 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state, val & mask); val 779 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~mask; val 780 drivers/gpu/drm/i915/display/intel_display_power.c val |= state; val 782 drivers/gpu/drm/i915/display/intel_display_power.c gen9_write_dc_state(dev_priv, val); val 784 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state = val & mask; val 1142 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 1150 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DSPCLK_GATE_D); val 1151 drivers/gpu/drm/i915/display/intel_display_power.c val &= DPOUNIT_CLOCK_GATE_DISABLE; val 1152 drivers/gpu/drm/i915/display/intel_display_power.c val |= VRHUNIT_CLOCK_GATE_DISABLE; val 1153 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DSPCLK_GATE_D, val); val 1181 drivers/gpu/drm/i915/display/intel_display_power.c u32 val = I915_READ(DPLL(pipe)); val 1183 drivers/gpu/drm/i915/display/intel_display_power.c val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; val 1185 drivers/gpu/drm/i915/display/intel_display_power.c val |= DPLL_INTEGRATED_CRI_CLK_VLV; val 1187 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DPLL(pipe), val); val 1286 drivers/gpu/drm/i915/display/intel_display_power.c #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) val 1489 drivers/gpu/drm/i915/display/intel_display_power.c u32 reg, val, expected, actual; val 1507 drivers/gpu/drm/i915/display/intel_display_power.c val = vlv_dpio_read(dev_priv, pipe, reg); val 1526 drivers/gpu/drm/i915/display/intel_display_power.c if (ch == DPIO_CH1 && val == 0) val 1535 drivers/gpu/drm/i915/display/intel_display_power.c actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; val 1537 drivers/gpu/drm/i915/display/intel_display_power.c actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; val 1544 drivers/gpu/drm/i915/display/intel_display_power.c reg, val); val 4111 drivers/gpu/drm/i915/display/intel_display_power.c u32 val, status; val 4113 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(reg); val 4114 drivers/gpu/drm/i915/display/intel_display_power.c val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST); val 4115 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(reg, val); val 4208 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask, val; val 4215 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(MBUS_ABOX_CTL); val 4216 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~mask; val 4217 drivers/gpu/drm/i915/display/intel_display_power.c val |= MBUS_ABOX_BT_CREDIT_POOL1(16) | val 4221 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(MBUS_ABOX_CTL, val); val 4226 drivers/gpu/drm/i915/display/intel_display_power.c u32 val = I915_READ(LCPLL_CTL); val 4234 drivers/gpu/drm/i915/display/intel_display_power.c if (val & LCPLL_CD_SOURCE_FCLK) val 4237 drivers/gpu/drm/i915/display/intel_display_power.c if (val & LCPLL_PLL_DISABLE) val 4240 drivers/gpu/drm/i915/display/intel_display_power.c if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) val 4292 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) val 4296 drivers/gpu/drm/i915/display/intel_display_power.c GEN6_PCODE_WRITE_D_COMP, val)) val 4299 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(D_COMP_BDW, val); val 4315 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 4319 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); val 4322 drivers/gpu/drm/i915/display/intel_display_power.c val |= LCPLL_CD_SOURCE_FCLK; val 4323 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); val 4329 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); val 4332 drivers/gpu/drm/i915/display/intel_display_power.c val |= LCPLL_PLL_DISABLE; val 4333 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); val 4339 drivers/gpu/drm/i915/display/intel_display_power.c val = hsw_read_dcomp(dev_priv); val 4340 drivers/gpu/drm/i915/display/intel_display_power.c val |= D_COMP_COMP_DISABLE; val 4341 drivers/gpu/drm/i915/display/intel_display_power.c hsw_write_dcomp(dev_priv, val); val 4349 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); val 4350 drivers/gpu/drm/i915/display/intel_display_power.c val |= LCPLL_POWER_DOWN_ALLOW; val 4351 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); val 4362 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 4364 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); val 4366 drivers/gpu/drm/i915/display/intel_display_power.c if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | val 4376 drivers/gpu/drm/i915/display/intel_display_power.c if (val & LCPLL_POWER_DOWN_ALLOW) { val 4377 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~LCPLL_POWER_DOWN_ALLOW; val 4378 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); val 4382 drivers/gpu/drm/i915/display/intel_display_power.c val = hsw_read_dcomp(dev_priv); val 4383 drivers/gpu/drm/i915/display/intel_display_power.c val |= D_COMP_COMP_FORCE; val 4384 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~D_COMP_COMP_DISABLE; val 4385 drivers/gpu/drm/i915/display/intel_display_power.c hsw_write_dcomp(dev_priv, val); val 4387 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); val 4388 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~LCPLL_PLL_DISABLE; val 4389 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); val 4394 drivers/gpu/drm/i915/display/intel_display_power.c if (val & LCPLL_CD_SOURCE_FCLK) { val 4395 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); val 4396 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~LCPLL_CD_SOURCE_FCLK; val 4397 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); val 4435 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 4440 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(SOUTH_DSPCLK_GATE_D); val 4441 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; val 4442 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(SOUTH_DSPCLK_GATE_D, val); val 4451 drivers/gpu/drm/i915/display/intel_display_power.c u32 val; val 4459 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(SOUTH_DSPCLK_GATE_D); val 4460 drivers/gpu/drm/i915/display/intel_display_power.c val |= PCH_LP_PARTITION_LEVEL_DISABLE; val 4461 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(SOUTH_DSPCLK_GATE_D, val); val 4469 drivers/gpu/drm/i915/display/intel_display_power.c u32 reset_bits, val; val 4479 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(reg); val 4482 drivers/gpu/drm/i915/display/intel_display_power.c val |= reset_bits; val 4484 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~reset_bits; val 4486 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(reg, val); val 3081 drivers/gpu/drm/i915/display/intel_dp.c u32 val = I915_READ(TRANS_DP_CTL(p)); val 3083 drivers/gpu/drm/i915/display/intel_dp.c if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { val 3102 drivers/gpu/drm/i915/display/intel_dp.c u32 val; val 3104 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(dp_reg); val 3106 drivers/gpu/drm/i915/display/intel_dp.c ret = val & DP_PORT_EN; val 3110 drivers/gpu/drm/i915/display/intel_dp.c *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; val 3114 drivers/gpu/drm/i915/display/intel_dp.c *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; val 3116 drivers/gpu/drm/i915/display/intel_dp.c *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; val 4037 drivers/gpu/drm/i915/display/intel_dp.c u32 val; val 4042 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(DP_TP_CTL(port)); val 4043 drivers/gpu/drm/i915/display/intel_dp.c val &= ~DP_TP_CTL_LINK_TRAIN_MASK; val 4044 drivers/gpu/drm/i915/display/intel_dp.c val |= DP_TP_CTL_LINK_TRAIN_IDLE; val 4045 drivers/gpu/drm/i915/display/intel_dp.c I915_WRITE(DP_TP_CTL(port), val); val 4272 drivers/gpu/drm/i915/display/intel_dp.c int val = le16_to_cpu(sink_rates[i]); val 4274 drivers/gpu/drm/i915/display/intel_dp.c if (val == 0) val 4283 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->sink_rates[i] = (val * 200) / 10; val 4910 drivers/gpu/drm/i915/display/intel_dp.c u8 val; val 4916 drivers/gpu/drm/i915/display/intel_dp.c DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) val 4919 drivers/gpu/drm/i915/display/intel_dp.c drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); val 4921 drivers/gpu/drm/i915/display/intel_dp.c if (val & DP_AUTOMATED_TEST_REQUEST) val 4924 drivers/gpu/drm/i915/display/intel_dp.c if (val & DP_CP_IRQ) val 4927 drivers/gpu/drm/i915/display/intel_dp.c if (val & DP_SINK_SPECIFIC_IRQ) val 6705 drivers/gpu/drm/i915/display/intel_dp.c u32 val; val 6707 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(reg); val 6710 drivers/gpu/drm/i915/display/intel_dp.c val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; val 6712 drivers/gpu/drm/i915/display/intel_dp.c val |= PIPECONF_EDP_RR_MODE_SWITCH; val 6715 drivers/gpu/drm/i915/display/intel_dp.c val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; val 6717 drivers/gpu/drm/i915/display/intel_dp.c val &= ~PIPECONF_EDP_RR_MODE_SWITCH; val 6719 drivers/gpu/drm/i915/display/intel_dp.c I915_WRITE(reg, val); val 271 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 281 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); val 282 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); val 283 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); val 285 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); val 286 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); val 287 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; val 288 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); val 290 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); val 291 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~SCALE_DCOMP_METHOD; val 293 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= SCALE_DCOMP_METHOD; val 295 drivers/gpu/drm/i915/display/intel_dpio_phy.c if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) val 298 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); val 300 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); val 301 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~DE_EMPHASIS; val 302 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= deemphasis << DEEMPH_SHIFT; val 303 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); val 305 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); val 306 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; val 307 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); val 340 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); val 342 drivers/gpu/drm/i915/display/intel_dpio_phy.c return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; val 357 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 376 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_P_CR_GT_DISP_PWRON); val 377 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= phy_info->pwron_mask; val 378 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); val 396 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); val 397 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~IREF0RC_OFFSET_MASK; val 398 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= 0xE4 << IREF0RC_OFFSET_SHIFT; val 399 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); val 401 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); val 402 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~IREF1RC_OFFSET_MASK; val 403 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= 0xE4 << IREF1RC_OFFSET_SHIFT; val 404 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); val 407 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); val 408 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | val 410 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); val 413 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_CL2CM_DW6(phy)); val 414 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DW6_OLDO_DYN_PWR_DOWN_EN; val 415 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); val 428 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, val 430 drivers/gpu/drm/i915/display/intel_dpio_phy.c grc_code = val << GRC_CODE_FAST_SHIFT | val 431 drivers/gpu/drm/i915/display/intel_dpio_phy.c val << GRC_CODE_SLOW_SHIFT | val 432 drivers/gpu/drm/i915/display/intel_dpio_phy.c val; val 435 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_REF_DW8(phy)); val 436 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= GRC_DIS | GRC_RDY_OVRD; val 437 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_REF_DW8(phy), val); val 443 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); val 444 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= COMMON_RESET_DIS; val 445 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); val 451 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 455 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); val 456 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~COMMON_RESET_DIS; val 457 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); val 459 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_P_CR_GT_DISP_PWRON); val 460 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~phy_info->pwron_mask; val 461 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); val 497 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 499 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(reg); val 500 drivers/gpu/drm/i915/display/intel_dpio_phy.c if ((val & mask) == expected) val 509 drivers/gpu/drm/i915/display/intel_dpio_phy.c phy, &vaf, reg.reg, val, (val & ~mask) | expected, val 602 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); val 608 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~LATENCY_OPTIM; val 610 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= LATENCY_OPTIM; val 612 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); val 630 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); val 632 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (val & LATENCY_OPTIM) val 649 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 655 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); val 656 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); val 657 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); val 658 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; val 659 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); val 662 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); val 663 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); val 664 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); val 665 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; val 666 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); val 669 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); val 670 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); val 671 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; val 672 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); val 675 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); val 676 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); val 677 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; val 678 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); val 683 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); val 684 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~DPIO_SWING_DEEMPH9P5_MASK; val 685 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; val 686 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); val 691 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); val 693 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~DPIO_SWING_MARGIN000_MASK; val 694 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; val 701 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); val 702 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; val 704 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); val 714 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); val 716 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; val 718 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; val 719 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); val 723 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); val 724 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; val 725 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); val 728 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); val 729 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; val 730 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); val 744 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 746 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); val 748 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); val 750 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; val 751 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); val 754 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); val 756 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); val 758 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; val 759 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); val 762 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); val 763 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_PCS_REQ_SOFTRESET_EN; val 765 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~DPIO_PCS_CLK_SOFT_RESET; val 767 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_CLK_SOFT_RESET; val 768 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); val 771 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); val 772 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_PCS_REQ_SOFTRESET_EN; val 774 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~DPIO_PCS_CLK_SOFT_RESET; val 776 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_PCS_CLK_SOFT_RESET; val 777 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); val 791 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 810 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); val 811 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); val 813 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_BUFLEFTENA1_FORCE; val 815 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_BUFRIGHTENA1_FORCE; val 816 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); val 818 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); val 819 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); val 821 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_BUFLEFTENA2_FORCE; val 823 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_BUFRIGHTENA2_FORCE; val 824 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); val 828 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); val 829 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; val 831 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~CHV_PCS_USEDCLKCHANNEL; val 833 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_PCS_USEDCLKCHANNEL; val 834 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); val 837 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); val 838 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; val 840 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~CHV_PCS_USEDCLKCHANNEL; val 842 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_PCS_USEDCLKCHANNEL; val 843 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); val 851 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); val 853 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~CHV_CMN_USEDCLKCHANNEL; val 855 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= CHV_CMN_USEDCLKCHANNEL; val 856 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); val 871 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 876 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); val 877 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~DPIO_LANEDESKEW_STRAP_OVRD; val 878 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); val 881 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); val 882 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~DPIO_LANEDESKEW_STRAP_OVRD; val 883 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); val 909 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); val 910 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_TX2_STAGGER_MASK(0x1f); val 911 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); val 914 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); val 915 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= DPIO_TX2_STAGGER_MASK(0x1f); val 916 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); val 957 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 963 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); val 964 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); val 965 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); val 967 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); val 968 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); val 969 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); val 1052 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val; val 1057 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); val 1058 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = 0; val 1060 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= (1<<21); val 1062 drivers/gpu/drm/i915/display/intel_dpio_phy.c val &= ~(1<<21); val 1063 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= 0x001000c4; val 1064 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); val 373 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 380 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(PCH_DPLL(id)); val 381 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll = val; val 387 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return val & DPLL_VCO_ENABLE; val 401 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 406 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(PCH_DREF_CONTROL); val 407 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | val 523 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 525 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(WRPLL_CTL(id)); val 526 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); val 541 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 543 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(SPLL_CTL); val 544 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); val 561 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 568 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(WRPLL_CTL(id)); val 569 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->wrpll = val; val 573 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return val & WRPLL_PLL_ENABLE; val 581 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 588 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(SPLL_CTL); val 589 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->spll = val; val 593 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return val & SPLL_PLL_ENABLE; val 819 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 824 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL | val 828 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.wrpll = val; val 988 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 990 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(DPLL_CTRL1); val 992 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~(DPLL_CTRL1_HDMI_MODE(id) | val 995 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= pll->state.hw_state.ctrl1 << (id * 6); val 997 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(DPLL_CTRL1, val); val 1049 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 1062 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(regs[id].ctl); val 1063 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!(val & LCPLL_PLL_ENABLE)) val 1066 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(DPLL_CTRL1); val 1067 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; val 1070 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (val & DPLL_CTRL1_HDMI_MODE(id)) { val 1089 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 1100 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(regs[id].ctl); val 1101 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN_ON(!(val & LCPLL_PLL_ENABLE))) val 1104 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(DPLL_CTRL1); val 1105 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; val 1655 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 1667 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(BXT_PORT_PLL_ENABLE(port)); val 1668 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!(val & PORT_PLL_ENABLE)) val 2022 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 2025 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); val 2026 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= PLL_POWER_ENABLE; val 2027 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_ENABLE(id), val); val 2038 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = pll->state.hw_state.cfgcr0; val 2039 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_CFGCR0(id), val); val 2047 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = pll->state.hw_state.cfgcr1; val 2048 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_CFGCR1(id), val); val 2063 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); val 2064 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= PLL_ENABLE; val 2065 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_ENABLE(id), val); val 2090 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 2107 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); val 2108 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~PLL_ENABLE; val 2109 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_ENABLE(id), val); val 2125 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); val 2126 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~PLL_POWER_ENABLE; val 2127 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_ENABLE(id), val); val 2141 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 2151 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); val 2152 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!(val & PLL_ENABLE)) val 2155 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_CFGCR0(id)); val 2156 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0 = val; val 2159 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (val & DPLL_CFGCR0_HDMI_MODE) { val 3050 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 3057 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_ENABLE(tc_port)); val 3058 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!(val & PLL_ENABLE)) val 3112 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 3119 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); val 3120 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!(val & PLL_ENABLE)) val 3193 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 3201 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_REFCLKIN_CTL(tc_port)); val 3202 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val 3203 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_refclkin_ctl; val 3204 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_REFCLKIN_CTL(tc_port), val); val 3206 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); val 3207 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val 3208 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_clktop2_coreclkctl1; val 3209 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val); val 3211 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); val 3212 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | val 3216 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_clktop2_hsclkctl; val 3217 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val); val 3225 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_BIAS(tc_port)); val 3226 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~hw_state->mg_pll_bias_mask; val 3227 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_pll_bias; val 3228 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_BIAS(tc_port), val); val 3230 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); val 3231 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~hw_state->mg_pll_tdc_coldst_bias_mask; val 3232 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_pll_tdc_coldst_bias; val 3233 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val); val 3242 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 3244 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); val 3245 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= PLL_POWER_ENABLE; val 3246 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(enable_reg, val); val 3260 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 3262 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); val 3263 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= PLL_ENABLE; val 3264 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(enable_reg, val); val 3347 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 val; val 3357 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); val 3358 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~PLL_ENABLE; val 3359 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(enable_reg, val); val 3367 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); val 3368 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~PLL_POWER_ENABLE; val 3369 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(enable_reg, val); val 289 drivers/gpu/drm/i915/display/intel_fbc.c u32 val = I915_READ(CHICKEN_MISC_4); val 291 drivers/gpu/drm/i915/display/intel_fbc.c val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); val 295 drivers/gpu/drm/i915/display/intel_fbc.c val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride; val 297 drivers/gpu/drm/i915/display/intel_fbc.c I915_WRITE(CHICKEN_MISC_4, val); val 153 drivers/gpu/drm/i915/display/intel_gmbus.c u32 val; val 156 drivers/gpu/drm/i915/display/intel_gmbus.c val = I915_READ(DSPCLK_GATE_D); val 158 drivers/gpu/drm/i915/display/intel_gmbus.c val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; val 160 drivers/gpu/drm/i915/display/intel_gmbus.c val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; val 161 drivers/gpu/drm/i915/display/intel_gmbus.c I915_WRITE(DSPCLK_GATE_D, val); val 167 drivers/gpu/drm/i915/display/intel_gmbus.c u32 val; val 169 drivers/gpu/drm/i915/display/intel_gmbus.c val = I915_READ(SOUTH_DSPCLK_GATE_D); val 171 drivers/gpu/drm/i915/display/intel_gmbus.c val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; val 173 drivers/gpu/drm/i915/display/intel_gmbus.c val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; val 174 drivers/gpu/drm/i915/display/intel_gmbus.c I915_WRITE(SOUTH_DSPCLK_GATE_D, val); val 180 drivers/gpu/drm/i915/display/intel_gmbus.c u32 val; val 182 drivers/gpu/drm/i915/display/intel_gmbus.c val = I915_READ(GEN9_CLKGATE_DIS_4); val 184 drivers/gpu/drm/i915/display/intel_gmbus.c val |= BXT_GMBUS_GATING_DIS; val 186 drivers/gpu/drm/i915/display/intel_gmbus.c val &= ~BXT_GMBUS_GATING_DIS; val 187 drivers/gpu/drm/i915/display/intel_gmbus.c I915_WRITE(GEN9_CLKGATE_DIS_4, val); val 418 drivers/gpu/drm/i915/display/intel_gmbus.c u32 val, loop = 0; val 424 drivers/gpu/drm/i915/display/intel_gmbus.c val = I915_READ_FW(GMBUS3); val 429 drivers/gpu/drm/i915/display/intel_gmbus.c *buf++ = val & 0xff; val 430 drivers/gpu/drm/i915/display/intel_gmbus.c val >>= 8; val 484 drivers/gpu/drm/i915/display/intel_gmbus.c u32 val, loop; val 486 drivers/gpu/drm/i915/display/intel_gmbus.c val = loop = 0; val 488 drivers/gpu/drm/i915/display/intel_gmbus.c val |= *buf++ << (8 * loop++); val 492 drivers/gpu/drm/i915/display/intel_gmbus.c I915_WRITE_FW(GMBUS3, val); val 501 drivers/gpu/drm/i915/display/intel_gmbus.c val = loop = 0; val 503 drivers/gpu/drm/i915/display/intel_gmbus.c val |= *buf++ << (8 * loop); val 506 drivers/gpu/drm/i915/display/intel_gmbus.c I915_WRITE_FW(GMBUS3, val); val 196 drivers/gpu/drm/i915/display/intel_hdcp.c u32 val; val 198 drivers/gpu/drm/i915/display/intel_hdcp.c val = I915_READ(HDCP_KEY_STATUS); val 199 drivers/gpu/drm/i915/display/intel_hdcp.c if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) val 232 drivers/gpu/drm/i915/display/intel_hdcp.c 10, 1, &val); val 235 drivers/gpu/drm/i915/display/intel_hdcp.c else if (!(val & HDCP_KEY_LOAD_STATUS)) val 211 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(VIDEO_DIP_CTL); val 214 drivers/gpu/drm/i915/display/intel_hdmi.c WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); val 216 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val 217 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_index(type); val 219 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~g4x_infoframe_enable(type); val 221 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(VIDEO_DIP_CTL, val); val 231 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_enable(type); val 232 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~VIDEO_DIP_FREQ_MASK; val 233 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_FREQ_VSYNC; val 235 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(VIDEO_DIP_CTL, val); val 245 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val, *data = frame; val 248 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(VIDEO_DIP_CTL); val 250 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val 251 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_index(type); val 253 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(VIDEO_DIP_CTL, val); val 263 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(VIDEO_DIP_CTL); val 265 drivers/gpu/drm/i915/display/intel_hdmi.c if ((val & VIDEO_DIP_ENABLE) == 0) val 268 drivers/gpu/drm/i915/display/intel_hdmi.c if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) val 271 drivers/gpu/drm/i915/display/intel_hdmi.c return val & (VIDEO_DIP_ENABLE_AVI | val 284 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 287 drivers/gpu/drm/i915/display/intel_hdmi.c WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); val 289 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val 290 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_index(type); val 292 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~g4x_infoframe_enable(type); val 294 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 304 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_enable(type); val 305 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~VIDEO_DIP_FREQ_MASK; val 306 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_FREQ_VSYNC; val 308 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 319 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val, *data = frame; val 322 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); val 324 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val 325 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_index(type); val 327 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); val 339 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 341 drivers/gpu/drm/i915/display/intel_hdmi.c if ((val & VIDEO_DIP_ENABLE) == 0) val 344 drivers/gpu/drm/i915/display/intel_hdmi.c if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) val 347 drivers/gpu/drm/i915/display/intel_hdmi.c return val & (VIDEO_DIP_ENABLE_AVI | val 361 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 364 drivers/gpu/drm/i915/display/intel_hdmi.c WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); val 366 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val 367 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_index(type); val 372 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~g4x_infoframe_enable(type); val 374 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 384 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_enable(type); val 385 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~VIDEO_DIP_FREQ_MASK; val 386 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_FREQ_VSYNC; val 388 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 399 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val, *data = frame; val 402 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); val 404 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val 405 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_index(type); val 407 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); val 418 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); val 420 drivers/gpu/drm/i915/display/intel_hdmi.c if ((val & VIDEO_DIP_ENABLE) == 0) val 423 drivers/gpu/drm/i915/display/intel_hdmi.c return val & (VIDEO_DIP_ENABLE_AVI | val 437 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 440 drivers/gpu/drm/i915/display/intel_hdmi.c WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); val 442 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val 443 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_index(type); val 445 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~g4x_infoframe_enable(type); val 447 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 457 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_enable(type); val 458 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~VIDEO_DIP_FREQ_MASK; val 459 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_FREQ_VSYNC; val 461 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 472 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val, *data = frame; val 475 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); val 477 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val 478 drivers/gpu/drm/i915/display/intel_hdmi.c val |= g4x_infoframe_index(type); val 480 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); val 491 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); val 493 drivers/gpu/drm/i915/display/intel_hdmi.c if ((val & VIDEO_DIP_ENABLE) == 0) val 496 drivers/gpu/drm/i915/display/intel_hdmi.c if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) val 499 drivers/gpu/drm/i915/display/intel_hdmi.c return val & (VIDEO_DIP_ENABLE_AVI | val 515 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(ctl_reg); val 519 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~hsw_infoframe_enable(type); val 520 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(ctl_reg, val); val 532 drivers/gpu/drm/i915/display/intel_hdmi.c val |= hsw_infoframe_enable(type); val 533 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(ctl_reg, val); val 544 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val, *data = frame; val 547 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); val 558 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); val 568 drivers/gpu/drm/i915/display/intel_hdmi.c return val & mask; val 598 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val, ret = 0; val 601 drivers/gpu/drm/i915/display/intel_hdmi.c val = dig_port->infoframes_enabled(encoder, crtc_state); val 608 drivers/gpu/drm/i915/display/intel_hdmi.c if (val & hsw_infoframe_enable(type)) val 611 drivers/gpu/drm/i915/display/intel_hdmi.c if (val & g4x_infoframe_enable(type)) val 844 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 858 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; val 861 drivers/gpu/drm/i915/display/intel_hdmi.c if (!(val & VIDEO_DIP_ENABLE)) val 863 drivers/gpu/drm/i915/display/intel_hdmi.c if (port != (val & VIDEO_DIP_PORT_MASK)) { val 865 drivers/gpu/drm/i915/display/intel_hdmi.c (val & VIDEO_DIP_PORT_MASK) >> 29); val 868 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | val 870 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 875 drivers/gpu/drm/i915/display/intel_hdmi.c if (port != (val & VIDEO_DIP_PORT_MASK)) { val 876 drivers/gpu/drm/i915/display/intel_hdmi.c if (val & VIDEO_DIP_ENABLE) { val 878 drivers/gpu/drm/i915/display/intel_hdmi.c (val & VIDEO_DIP_PORT_MASK) >> 29); val 881 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~VIDEO_DIP_PORT_MASK; val 882 drivers/gpu/drm/i915/display/intel_hdmi.c val |= port; val 885 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_ENABLE; val 886 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE_AVI | val 889 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1027 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 1033 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; val 1036 drivers/gpu/drm/i915/display/intel_hdmi.c if (!(val & VIDEO_DIP_ENABLE)) val 1038 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | val 1041 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1046 drivers/gpu/drm/i915/display/intel_hdmi.c if (port != (val & VIDEO_DIP_PORT_MASK)) { val 1047 drivers/gpu/drm/i915/display/intel_hdmi.c WARN(val & VIDEO_DIP_ENABLE, val 1049 drivers/gpu/drm/i915/display/intel_hdmi.c (val & VIDEO_DIP_PORT_MASK) >> 29); val 1050 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~VIDEO_DIP_PORT_MASK; val 1051 drivers/gpu/drm/i915/display/intel_hdmi.c val |= port; val 1054 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_ENABLE; val 1055 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE_AVI | val 1060 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_ENABLE_GCP; val 1062 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1085 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 1090 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; val 1093 drivers/gpu/drm/i915/display/intel_hdmi.c if (!(val & VIDEO_DIP_ENABLE)) val 1095 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | val 1098 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1104 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; val 1105 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | val 1109 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_ENABLE_GCP; val 1111 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1134 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 1140 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; val 1143 drivers/gpu/drm/i915/display/intel_hdmi.c if (!(val & VIDEO_DIP_ENABLE)) val 1145 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | val 1148 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1153 drivers/gpu/drm/i915/display/intel_hdmi.c if (port != (val & VIDEO_DIP_PORT_MASK)) { val 1154 drivers/gpu/drm/i915/display/intel_hdmi.c WARN(val & VIDEO_DIP_ENABLE, val 1156 drivers/gpu/drm/i915/display/intel_hdmi.c (val & VIDEO_DIP_PORT_MASK) >> 29); val 1157 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~VIDEO_DIP_PORT_MASK; val 1158 drivers/gpu/drm/i915/display/intel_hdmi.c val |= port; val 1161 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_ENABLE; val 1162 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE_AVI | val 1167 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_ENABLE_GCP; val 1169 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1190 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); val 1195 drivers/gpu/drm/i915/display/intel_hdmi.c val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | val 1201 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1207 drivers/gpu/drm/i915/display/intel_hdmi.c val |= VIDEO_DIP_ENABLE_GCP_HSW; val 1209 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); val 1360 drivers/gpu/drm/i915/display/intel_hdmi.c u8 val; val 1362 drivers/gpu/drm/i915/display/intel_hdmi.c ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); val 1367 drivers/gpu/drm/i915/display/intel_hdmi.c *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; val 1388 drivers/gpu/drm/i915/display/intel_hdmi.c u8 val; val 1390 drivers/gpu/drm/i915/display/intel_hdmi.c ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); val 1395 drivers/gpu/drm/i915/display/intel_hdmi.c *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; val 377 drivers/gpu/drm/i915/display/intel_lspcon.c u32 val = 0; val 383 drivers/gpu/drm/i915/display/intel_lspcon.c while (val < len) { val 397 drivers/gpu/drm/i915/display/intel_lspcon.c val++; reg++; data++; val 400 drivers/gpu/drm/i915/display/intel_lspcon.c val = 0; val 402 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_read(aux, reg, &val, 1); val 409 drivers/gpu/drm/i915/display/intel_lspcon.c val &= ~LSPCON_MCA_AVI_IF_HANDLED; val 410 drivers/gpu/drm/i915/display/intel_lspcon.c val |= LSPCON_MCA_AVI_IF_KICKOFF; val 412 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, &val, 1); val 418 drivers/gpu/drm/i915/display/intel_lspcon.c val = 0; val 419 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_read(aux, reg, &val, 1); val 425 drivers/gpu/drm/i915/display/intel_lspcon.c if (val == LSPCON_MCA_AVI_IF_HANDLED) val 86 drivers/gpu/drm/i915/display/intel_lvds.c u32 val; val 88 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(lvds_reg); val 92 drivers/gpu/drm/i915/display/intel_lvds.c *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; val 94 drivers/gpu/drm/i915/display/intel_lvds.c *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; val 96 drivers/gpu/drm/i915/display/intel_lvds.c return val & LVDS_PORT_EN; val 157 drivers/gpu/drm/i915/display/intel_lvds.c u32 val; val 161 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_ON_DELAYS(0)); val 162 drivers/gpu/drm/i915/display/intel_lvds.c pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); val 163 drivers/gpu/drm/i915/display/intel_lvds.c pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); val 164 drivers/gpu/drm/i915/display/intel_lvds.c pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); val 166 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_OFF_DELAYS(0)); val 167 drivers/gpu/drm/i915/display/intel_lvds.c pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); val 168 drivers/gpu/drm/i915/display/intel_lvds.c pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); val 170 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_DIVISOR(0)); val 171 drivers/gpu/drm/i915/display/intel_lvds.c pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); val 172 drivers/gpu/drm/i915/display/intel_lvds.c val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); val 178 drivers/gpu/drm/i915/display/intel_lvds.c if (val) val 179 drivers/gpu/drm/i915/display/intel_lvds.c val--; val 181 drivers/gpu/drm/i915/display/intel_lvds.c pps->t4 = val * 1000; val 204 drivers/gpu/drm/i915/display/intel_lvds.c u32 val; val 206 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_CONTROL(0)); val 207 drivers/gpu/drm/i915/display/intel_lvds.c WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); val 209 drivers/gpu/drm/i915/display/intel_lvds.c val |= PANEL_POWER_RESET; val 210 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(PP_CONTROL(0), val); val 774 drivers/gpu/drm/i915/display/intel_lvds.c unsigned int val; val 794 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(lvds_encoder->reg); val 796 drivers/gpu/drm/i915/display/intel_lvds.c val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); val 798 drivers/gpu/drm/i915/display/intel_lvds.c val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); val 799 drivers/gpu/drm/i915/display/intel_lvds.c if (val == 0) val 800 drivers/gpu/drm/i915/display/intel_lvds.c val = dev_priv->vbt.bios_lvds_val; val 802 drivers/gpu/drm/i915/display/intel_lvds.c return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; val 624 drivers/gpu/drm/i915/display/intel_opregion.c unsigned long val, void *data) val 651 drivers/gpu/drm/i915/display/intel_opregion.c static void set_did(struct intel_opregion *opregion, int i, u32 val) val 654 drivers/gpu/drm/i915/display/intel_opregion.c opregion->acpi->didl[i] = val; val 661 drivers/gpu/drm/i915/display/intel_opregion.c opregion->acpi->did2[i] = val; val 202 drivers/gpu/drm/i915/display/intel_overlay.c u8 val; val 212 drivers/gpu/drm/i915/display/intel_overlay.c PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); val 214 drivers/gpu/drm/i915/display/intel_overlay.c val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; val 216 drivers/gpu/drm/i915/display/intel_overlay.c val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; val 218 drivers/gpu/drm/i915/display/intel_overlay.c PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); val 518 drivers/gpu/drm/i915/display/intel_panel.c u32 val) val 526 drivers/gpu/drm/i915/display/intel_panel.c return val; val 530 drivers/gpu/drm/i915/display/intel_panel.c return panel->backlight.max - val + panel->backlight.min; val 533 drivers/gpu/drm/i915/display/intel_panel.c return val; val 554 drivers/gpu/drm/i915/display/intel_panel.c u32 val; val 556 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; val 558 drivers/gpu/drm/i915/display/intel_panel.c val >>= 1; val 564 drivers/gpu/drm/i915/display/intel_panel.c val *= lbpc; val 567 drivers/gpu/drm/i915/display/intel_panel.c return val; val 608 drivers/gpu/drm/i915/display/intel_panel.c u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; val 609 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_PCH_CTL2, val | level); val 804 drivers/gpu/drm/i915/display/intel_panel.c u32 tmp, val; val 813 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(UTIL_PIN_CTL); val 814 drivers/gpu/drm/i915/display/intel_panel.c val &= ~UTIL_PIN_ENABLE; val 815 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(UTIL_PIN_CTL, val); val 1081 drivers/gpu/drm/i915/display/intel_panel.c u32 pwm_ctl, val; val 1085 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(UTIL_PIN_CTL); val 1086 drivers/gpu/drm/i915/display/intel_panel.c if (val & UTIL_PIN_ENABLE) { val 1088 drivers/gpu/drm/i915/display/intel_panel.c val &= ~UTIL_PIN_ENABLE; val 1089 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(UTIL_PIN_CTL, val); val 1092 drivers/gpu/drm/i915/display/intel_panel.c val = 0; val 1094 drivers/gpu/drm/i915/display/intel_panel.c val |= UTIL_PIN_POLARITY; val 1095 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) | val 1211 drivers/gpu/drm/i915/display/intel_panel.c u32 val = 0; val 1216 drivers/gpu/drm/i915/display/intel_panel.c val = panel->backlight.get(connector); val 1217 drivers/gpu/drm/i915/display/intel_panel.c val = intel_panel_compute_brightness(connector, val); val 1222 drivers/gpu/drm/i915/display/intel_panel.c DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); val 1223 drivers/gpu/drm/i915/display/intel_panel.c return val; val 1572 drivers/gpu/drm/i915/display/intel_panel.c u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; val 1603 drivers/gpu/drm/i915/display/intel_panel.c val = pch_get_backlight(connector); val 1605 drivers/gpu/drm/i915/display/intel_panel.c val = lpt_get_backlight(connector); val 1606 drivers/gpu/drm/i915/display/intel_panel.c val = intel_panel_compute_brightness(connector, val); val 1607 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.level = clamp(val, panel->backlight.min, val 1627 drivers/gpu/drm/i915/display/intel_panel.c u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; val 1643 drivers/gpu/drm/i915/display/intel_panel.c val = pch_get_backlight(connector); val 1644 drivers/gpu/drm/i915/display/intel_panel.c val = intel_panel_compute_brightness(connector, val); val 1645 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.level = clamp(val, panel->backlight.min, val 1659 drivers/gpu/drm/i915/display/intel_panel.c u32 ctl, val; val 1684 drivers/gpu/drm/i915/display/intel_panel.c val = i9xx_get_backlight(connector); val 1685 drivers/gpu/drm/i915/display/intel_panel.c val = intel_panel_compute_brightness(connector, val); val 1686 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.level = clamp(val, panel->backlight.min, val 1689 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.enabled = val != 0; val 1698 drivers/gpu/drm/i915/display/intel_panel.c u32 ctl, ctl2, val; val 1718 drivers/gpu/drm/i915/display/intel_panel.c val = i9xx_get_backlight(connector); val 1719 drivers/gpu/drm/i915/display/intel_panel.c val = intel_panel_compute_brightness(connector, val); val 1720 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.level = clamp(val, panel->backlight.min, val 1732 drivers/gpu/drm/i915/display/intel_panel.c u32 ctl, ctl2, val; val 1751 drivers/gpu/drm/i915/display/intel_panel.c val = _vlv_get_backlight(dev_priv, pipe); val 1752 drivers/gpu/drm/i915/display/intel_panel.c val = intel_panel_compute_brightness(connector, val); val 1753 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.level = clamp(val, panel->backlight.min, val 1766 drivers/gpu/drm/i915/display/intel_panel.c u32 pwm_ctl, val; val 1774 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(UTIL_PIN_CTL); val 1776 drivers/gpu/drm/i915/display/intel_panel.c val & UTIL_PIN_POLARITY; val 1791 drivers/gpu/drm/i915/display/intel_panel.c val = bxt_get_backlight(connector); val 1792 drivers/gpu/drm/i915/display/intel_panel.c val = intel_panel_compute_brightness(connector, val); val 1793 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.level = clamp(val, panel->backlight.min, val 1806 drivers/gpu/drm/i915/display/intel_panel.c u32 pwm_ctl, val; val 1829 drivers/gpu/drm/i915/display/intel_panel.c val = bxt_get_backlight(connector); val 1830 drivers/gpu/drm/i915/display/intel_panel.c val = intel_panel_compute_brightness(connector, val); val 1831 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.level = clamp(val, panel->backlight.min, val 54 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 *val) val 61 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; val 64 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = 0; val 130 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 *val) val 142 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; val 145 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; val 149 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; val 155 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; val 159 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = 0; val 200 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 *val) val 210 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; val 215 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; val 218 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = 0; val 261 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 *val) val 268 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; val 271 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; val 274 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; val 277 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = 0; val 339 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 *val) val 346 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; val 349 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; val 352 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; val 355 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = 0; val 367 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 *val) val 374 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL; val 377 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL; val 380 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL; val 383 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL; val 386 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL; val 389 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL; val 392 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL; val 395 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL; val 398 drivers/gpu/drm/i915/display/intel_pipe_crc.c *val = 0; val 409 drivers/gpu/drm/i915/display/intel_pipe_crc.c enum intel_pipe_crc_source *source, u32 *val) val 412 drivers/gpu/drm/i915/display/intel_pipe_crc.c return i8xx_pipe_crc_ctl_reg(source, val); val 414 drivers/gpu/drm/i915/display/intel_pipe_crc.c return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); val 416 drivers/gpu/drm/i915/display/intel_pipe_crc.c return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); val 418 drivers/gpu/drm/i915/display/intel_pipe_crc.c return ilk_pipe_crc_ctl_reg(source, val); val 420 drivers/gpu/drm/i915/display/intel_pipe_crc.c return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val); val 422 drivers/gpu/drm/i915/display/intel_pipe_crc.c return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val); val 593 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 val = 0; /* shut up gcc */ val 613 drivers/gpu/drm/i915/display/intel_pipe_crc.c ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val); val 618 drivers/gpu/drm/i915/display/intel_pipe_crc.c I915_WRITE(PIPE_CRC_CTL(crtc->index), val); val 642 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 val = 0; val 647 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val) < 0) val 653 drivers/gpu/drm/i915/display/intel_pipe_crc.c I915_WRITE(PIPE_CRC_CTL(crtc->index), val); val 135 drivers/gpu/drm/i915/display/intel_psr.c static void psr_event_print(u32 val, bool psr2_enabled) val 137 drivers/gpu/drm/i915/display/intel_psr.c DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val); val 138 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) val 140 drivers/gpu/drm/i915/display/intel_psr.c if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) val 142 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) val 144 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) val 146 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_GRAPHICS_RESET) val 148 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_PCH_INTERRUPT) val 150 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_MEMORY_UP) val 152 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) val 154 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_WD_TIMER_EXPIRE) val 156 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) val 158 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_REGISTER_UPDATE) val 160 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_HDCP_ENABLE) val 162 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_KVMR_SESSION_ENABLE) val 164 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_VBI_ENABLE) val 166 drivers/gpu/drm/i915/display/intel_psr.c if (val & PSR_EVENT_LPSP_MODE_EXIT) val 168 drivers/gpu/drm/i915/display/intel_psr.c if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) val 216 drivers/gpu/drm/i915/display/intel_psr.c u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); val 219 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(PSR_EVENT(cpu_transcoder), val); val 220 drivers/gpu/drm/i915/display/intel_psr.c psr_event_print(val, psr2_enabled); val 245 drivers/gpu/drm/i915/display/intel_psr.c u8 val = 8; /* assume the worst if we can't read the value */ val 248 drivers/gpu/drm/i915/display/intel_psr.c DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) val 249 drivers/gpu/drm/i915/display/intel_psr.c val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; val 252 drivers/gpu/drm/i915/display/intel_psr.c return val; val 257 drivers/gpu/drm/i915/display/intel_psr.c u16 val; val 267 drivers/gpu/drm/i915/display/intel_psr.c r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); val 275 drivers/gpu/drm/i915/display/intel_psr.c if (r != 2 || val == 0) val 276 drivers/gpu/drm/i915/display/intel_psr.c val = 4; val 278 drivers/gpu/drm/i915/display/intel_psr.c return val; val 433 drivers/gpu/drm/i915/display/intel_psr.c u32 val = 0; val 436 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP4_TIME_0US; val 439 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP1_TIME_0us; val 441 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP1_TIME_100us; val 443 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP1_TIME_500us; val 445 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP1_TIME_2500us; val 448 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP2_TP3_TIME_0us; val 450 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP2_TP3_TIME_100us; val 452 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP2_TP3_TIME_500us; val 454 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP2_TP3_TIME_2500us; val 458 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP1_TP3_SEL; val 460 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_TP1_TP2_SEL; val 462 drivers/gpu/drm/i915/display/intel_psr.c return val; val 469 drivers/gpu/drm/i915/display/intel_psr.c u32 val = EDP_PSR_ENABLE; val 480 drivers/gpu/drm/i915/display/intel_psr.c val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; val 482 drivers/gpu/drm/i915/display/intel_psr.c val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; val 484 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; val 487 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_LINK_STANDBY; val 489 drivers/gpu/drm/i915/display/intel_psr.c val |= intel_psr1_get_tp_time(intel_dp); val 492 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR_CRC_ENABLE; val 494 drivers/gpu/drm/i915/display/intel_psr.c val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; val 495 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(EDP_PSR_CTL, val); val 501 drivers/gpu/drm/i915/display/intel_psr.c u32 val; val 509 drivers/gpu/drm/i915/display/intel_psr.c val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; val 511 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; val 513 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_Y_COORDINATE_ENABLE; val 515 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); val 519 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR2_TP2_TIME_50us; val 521 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR2_TP2_TIME_100us; val 523 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR2_TP2_TIME_500us; val 525 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR2_TP2_TIME_2500us; val 533 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(EDP_PSR2_CTL, val); val 782 drivers/gpu/drm/i915/display/intel_psr.c u32 val; val 792 drivers/gpu/drm/i915/display/intel_psr.c val = I915_READ(EDP_PSR2_CTL); val 793 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(!(val & EDP_PSR2_ENABLE)); val 794 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); val 796 drivers/gpu/drm/i915/display/intel_psr.c val = I915_READ(EDP_PSR_CTL); val 797 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(!(val & EDP_PSR_ENABLE)); val 798 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); val 1052 drivers/gpu/drm/i915/display/intel_psr.c int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) val 1054 drivers/gpu/drm/i915/display/intel_psr.c const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; val 1058 drivers/gpu/drm/i915/display/intel_psr.c if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || val 1060 drivers/gpu/drm/i915/display/intel_psr.c DRM_DEBUG_KMS("Invalid debug mask %llx\n", val); val 1069 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.debug = val; val 1211 drivers/gpu/drm/i915/display/intel_psr.c u32 val; val 1234 drivers/gpu/drm/i915/display/intel_psr.c val = I915_READ(EDP_PSR_IIR); val 1235 drivers/gpu/drm/i915/display/intel_psr.c val &= EDP_PSR_ERROR(edp_psr_shift(TRANSCODER_EDP)); val 1236 drivers/gpu/drm/i915/display/intel_psr.c if (val) { val 1257 drivers/gpu/drm/i915/display/intel_psr.c u8 val; val 1270 drivers/gpu/drm/i915/display/intel_psr.c if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) { val 1275 drivers/gpu/drm/i915/display/intel_psr.c if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) { val 1281 drivers/gpu/drm/i915/display/intel_psr.c if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) { val 1286 drivers/gpu/drm/i915/display/intel_psr.c if (val & DP_PSR_RFB_STORAGE_ERROR) val 1288 drivers/gpu/drm/i915/display/intel_psr.c if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) val 1290 drivers/gpu/drm/i915/display/intel_psr.c if (val & DP_PSR_LINK_CRC_ERROR) val 1293 drivers/gpu/drm/i915/display/intel_psr.c if (val & ~errors) val 1295 drivers/gpu/drm/i915/display/intel_psr.c val & ~errors); val 1296 drivers/gpu/drm/i915/display/intel_psr.c if (val & errors) { val 1301 drivers/gpu/drm/i915/display/intel_psr.c drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val); val 212 drivers/gpu/drm/i915/display/intel_sdvo.c static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) val 216 drivers/gpu/drm/i915/display/intel_sdvo.c u32 bval = val, cval = val; val 220 drivers/gpu/drm/i915/display/intel_sdvo.c I915_WRITE(intel_sdvo->sdvo_reg, val); val 227 drivers/gpu/drm/i915/display/intel_sdvo.c I915_WRITE(intel_sdvo->sdvo_reg, val); val 821 drivers/gpu/drm/i915/display/intel_sdvo.c static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) val 823 drivers/gpu/drm/i915/display/intel_sdvo.c return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); val 1367 drivers/gpu/drm/i915/display/intel_sdvo.c val = input; \ val 1368 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ val 1377 drivers/gpu/drm/i915/display/intel_sdvo.c u16 val; val 1565 drivers/gpu/drm/i915/display/intel_sdvo.c u32 val; val 1567 drivers/gpu/drm/i915/display/intel_sdvo.c val = I915_READ(sdvo_reg); val 1571 drivers/gpu/drm/i915/display/intel_sdvo.c *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; val 1573 drivers/gpu/drm/i915/display/intel_sdvo.c *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; val 1575 drivers/gpu/drm/i915/display/intel_sdvo.c *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; val 1577 drivers/gpu/drm/i915/display/intel_sdvo.c return val & SDVO_ENABLE; val 1605 drivers/gpu/drm/i915/display/intel_sdvo.c u8 val; val 1656 drivers/gpu/drm/i915/display/intel_sdvo.c &val, 1)) { val 1657 drivers/gpu/drm/i915/display/intel_sdvo.c switch (val) { val 1678 drivers/gpu/drm/i915/display/intel_sdvo.c &val, 1)) { val 1681 drivers/gpu/drm/i915/display/intel_sdvo.c if ((val & mask) == mask) val 1686 drivers/gpu/drm/i915/display/intel_sdvo.c &val, 1)) { val 1687 drivers/gpu/drm/i915/display/intel_sdvo.c if (val == SDVO_ENCODE_HDMI) val 2266 drivers/gpu/drm/i915/display/intel_sdvo.c u64 *val) val 2276 drivers/gpu/drm/i915/display/intel_sdvo.c *val = i; val 2282 drivers/gpu/drm/i915/display/intel_sdvo.c *val = 0; val 2285 drivers/gpu/drm/i915/display/intel_sdvo.c *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; val 2288 drivers/gpu/drm/i915/display/intel_sdvo.c *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; val 2290 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.hpos; val 2292 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.vpos; val 2294 drivers/gpu/drm/i915/display/intel_sdvo.c *val = state->tv.saturation; val 2296 drivers/gpu/drm/i915/display/intel_sdvo.c *val = state->tv.contrast; val 2298 drivers/gpu/drm/i915/display/intel_sdvo.c *val = state->tv.hue; val 2300 drivers/gpu/drm/i915/display/intel_sdvo.c *val = state->tv.brightness; val 2302 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.sharpness; val 2304 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.flicker_filter; val 2306 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.flicker_filter_2d; val 2308 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.flicker_filter_adaptive; val 2310 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.chroma_filter; val 2312 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.luma_filter; val 2314 drivers/gpu/drm/i915/display/intel_sdvo.c *val = sdvo_state->tv.dot_crawl; val 2316 drivers/gpu/drm/i915/display/intel_sdvo.c return intel_digital_connector_atomic_get_property(connector, state, property, val); val 2325 drivers/gpu/drm/i915/display/intel_sdvo.c u64 val) val 2331 drivers/gpu/drm/i915/display/intel_sdvo.c state->tv.mode = intel_sdvo_connector->tv_format_supported[val]; val 2342 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; val 2346 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; val 2348 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.hpos = val; val 2350 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.vpos = val; val 2352 drivers/gpu/drm/i915/display/intel_sdvo.c state->tv.saturation = val; val 2354 drivers/gpu/drm/i915/display/intel_sdvo.c state->tv.contrast = val; val 2356 drivers/gpu/drm/i915/display/intel_sdvo.c state->tv.hue = val; val 2358 drivers/gpu/drm/i915/display/intel_sdvo.c state->tv.brightness = val; val 2360 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.sharpness = val; val 2362 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.flicker_filter = val; val 2364 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.flicker_filter_2d = val; val 2366 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.flicker_filter_adaptive = val; val 2368 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.chroma_filter = val; val 2370 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.luma_filter = val; val 2372 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo_state->tv.dot_crawl = val; val 2374 drivers/gpu/drm/i915/display/intel_sdvo.c return intel_digital_connector_atomic_set_property(connector, state, property, val); val 101 drivers/gpu/drm/i915/display/intel_tc.c u32 val; val 105 drivers/gpu/drm/i915/display/intel_tc.c val = intel_uncore_read(uncore, val 107 drivers/gpu/drm/i915/display/intel_tc.c val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port); val 111 drivers/gpu/drm/i915/display/intel_tc.c val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) : val 115 drivers/gpu/drm/i915/display/intel_tc.c val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) : val 119 drivers/gpu/drm/i915/display/intel_tc.c val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port); val 126 drivers/gpu/drm/i915/display/intel_tc.c PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val); val 156 drivers/gpu/drm/i915/display/intel_tc.c u32 val; val 158 drivers/gpu/drm/i915/display/intel_tc.c val = intel_uncore_read(uncore, val 161 drivers/gpu/drm/i915/display/intel_tc.c if (val == 0xffffffff) { val 167 drivers/gpu/drm/i915/display/intel_tc.c if (val & TC_LIVE_STATE_TBT(tc_port)) val 169 drivers/gpu/drm/i915/display/intel_tc.c if (val & TC_LIVE_STATE_TC(tc_port)) val 187 drivers/gpu/drm/i915/display/intel_tc.c u32 val; val 189 drivers/gpu/drm/i915/display/intel_tc.c val = intel_uncore_read(uncore, val 191 drivers/gpu/drm/i915/display/intel_tc.c if (val == 0xffffffff) { val 197 drivers/gpu/drm/i915/display/intel_tc.c return val & DP_PHY_MODE_STATUS_COMPLETED(tc_port); val 206 drivers/gpu/drm/i915/display/intel_tc.c u32 val; val 208 drivers/gpu/drm/i915/display/intel_tc.c val = intel_uncore_read(uncore, val 210 drivers/gpu/drm/i915/display/intel_tc.c if (val == 0xffffffff) { val 218 drivers/gpu/drm/i915/display/intel_tc.c val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port); val 220 drivers/gpu/drm/i915/display/intel_tc.c val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port); val 223 drivers/gpu/drm/i915/display/intel_tc.c PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val); val 237 drivers/gpu/drm/i915/display/intel_tc.c u32 val; val 239 drivers/gpu/drm/i915/display/intel_tc.c val = intel_uncore_read(uncore, val 241 drivers/gpu/drm/i915/display/intel_tc.c if (val == 0xffffffff) { val 247 drivers/gpu/drm/i915/display/intel_tc.c return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)); val 99 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val = 0; val 102 drivers/gpu/drm/i915/display/vlv_dsi.c val |= *data++ << 8 * j; val 104 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(reg, val); val 115 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val = I915_READ(reg); val 118 drivers/gpu/drm/i915/display/vlv_dsi.c *data++ = val >> 8 * j; val 372 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 382 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_CTRL(PORT_A)); val 383 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); val 388 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); val 389 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~ULPS_STATE_MASK; val 390 drivers/gpu/drm/i915/display/vlv_dsi.c val |= DEVICE_READY; val 391 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DEVICE_READY(port), val); val 395 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); val 396 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~ULPS_STATE_MASK; val 397 drivers/gpu/drm/i915/display/vlv_dsi.c val |= (ULPS_STATE_ENTER | DEVICE_READY); val 398 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DEVICE_READY(port), val); val 406 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); val 407 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~ULPS_STATE_MASK; val 408 drivers/gpu/drm/i915/display/vlv_dsi.c val |= (ULPS_STATE_EXIT | DEVICE_READY); val 409 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DEVICE_READY(port), val); val 412 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); val 413 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~ULPS_STATE_MASK; val 414 drivers/gpu/drm/i915/display/vlv_dsi.c val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); val 415 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DEVICE_READY(port), val); val 417 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_CTRL(port)); val 418 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~GLK_LP_WAKE; val 419 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_CTRL(port), val); val 443 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 449 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(BXT_MIPI_PORT_CTRL(port)); val 450 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); val 456 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); val 457 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~ULPS_STATE_MASK; val 458 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DEVICE_READY(port), val); val 460 drivers/gpu/drm/i915/display/vlv_dsi.c val |= DEVICE_READY; val 461 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DEVICE_READY(port), val); val 470 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 492 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_PORT_CTRL(PORT_A)); val 493 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); val 521 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 525 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); val 526 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~ULPS_STATE_MASK; val 527 drivers/gpu/drm/i915/display/vlv_dsi.c val |= (ULPS_STATE_ENTER | DEVICE_READY); val 528 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DEVICE_READY(port), val); val 590 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 614 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(port_ctrl); val 615 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); val 754 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 775 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(BXT_P_CR_GT_DISP_PWRON); val 777 drivers/gpu/drm/i915/display/vlv_dsi.c val | MIPIO_RST_CTRL); val 785 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 788 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(DSPCLK_GATE_D); val 789 drivers/gpu/drm/i915/display/vlv_dsi.c val |= DPOUNIT_CLOCK_GATE_DISABLE; val 790 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(DSPCLK_GATE_D, val); val 891 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 922 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(BXT_P_CR_GT_DISP_PWRON); val 924 drivers/gpu/drm/i915/display/vlv_dsi.c val & ~MIPIO_RST_CTRL); val 930 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 934 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(DSPCLK_GATE_D); val 935 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~DPOUNIT_CLOCK_GATE_DISABLE; val 936 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(DSPCLK_GATE_D, val); val 1323 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val, tmp; val 1375 drivers/gpu/drm/i915/display/vlv_dsi.c val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; val 1377 drivers/gpu/drm/i915/display/vlv_dsi.c val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; val 1378 drivers/gpu/drm/i915/display/vlv_dsi.c val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ val 1380 drivers/gpu/drm/i915/display/vlv_dsi.c val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; val 1381 drivers/gpu/drm/i915/display/vlv_dsi.c val |= pixel_format_to_reg(intel_dsi->pixel_format); val 1397 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); val 1511 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 1526 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DSI_FUNC_PRG(port)); val 1527 drivers/gpu/drm/i915/display/vlv_dsi.c val &= ~VID_MODE_FORMAT_MASK; val 1528 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); val 1577 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val; val 1590 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(DSPCNTR(plane->i9xx_plane)); val 1592 drivers/gpu/drm/i915/display/vlv_dsi.c if (!(val & DISPLAY_PLANE_ENABLE)) val 1594 drivers/gpu/drm/i915/display/vlv_dsi.c else if (val & DISPPLANE_ROTATE_180) val 200 drivers/gpu/drm/i915/display/vlv_dsi_pll.c u32 val; val 204 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val = I915_READ(BXT_DSI_PLL_ENABLE); val 205 drivers/gpu/drm/i915/display/vlv_dsi_pll.c enabled = (val & mask) == mask; val 218 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val = I915_READ(BXT_DSI_PLL_CTL); val 220 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (!(val & BXT_DSIA_16X_MASK)) { val 221 drivers/gpu/drm/i915/display/vlv_dsi_pll.c DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val); val 225 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { val 226 drivers/gpu/drm/i915/display/vlv_dsi_pll.c DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val); val 237 drivers/gpu/drm/i915/display/vlv_dsi_pll.c u32 val; val 241 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val = I915_READ(BXT_DSI_PLL_ENABLE); val 242 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val &= ~BXT_DSI_PLL_DO_ENABLE; val 243 drivers/gpu/drm/i915/display/vlv_dsi_pll.c I915_WRITE(BXT_DSI_PLL_ENABLE, val); val 508 drivers/gpu/drm/i915/display/vlv_dsi_pll.c u32 val; val 525 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val = I915_READ(BXT_DSI_PLL_ENABLE); val 526 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val |= BXT_DSI_PLL_DO_ENABLE; val 527 drivers/gpu/drm/i915/display/vlv_dsi_pll.c I915_WRITE(BXT_DSI_PLL_ENABLE, val); val 886 drivers/gpu/drm/i915/gem/selftests/huge_pages.c u32 val) val 897 drivers/gpu/drm/i915/gem/selftests/huge_pages.c vma->size >> PAGE_SHIFT, val); val 900 drivers/gpu/drm/i915/gem/selftests/huge_pages.c static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val) val 916 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (ptr[dword] != val) { val 918 drivers/gpu/drm/i915/gem/selftests/huge_pages.c n, dword, ptr[dword], val); val 936 drivers/gpu/drm/i915/gem/selftests/huge_pages.c u32 dword, u32 val) val 967 drivers/gpu/drm/i915/gem/selftests/huge_pages.c err = gpu_write(vma, ctx, engine, dword, val); val 973 drivers/gpu/drm/i915/gem/selftests/huge_pages.c err = cpu_check(obj, dword, val); val 31 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c u32 val = prandom_u32_state(&prng); val 38 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c phys_sz, sz, val); val 62 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c memset32(vaddr, val ^ 0xdeadbeaf, val 70 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c val); val 81 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c if (vaddr[i] != val) { val 83 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c vaddr[i], val); val 768 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c u32 *buf, val; val 797 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c val = *buf; val 798 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c cnt = (val & s_mask) >> s_shift; val 799 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c *rpcs = val; val 37 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c u32 val = prandom_u32_state(&prng); val 44 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c phys_sz, sz, val); val 62 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c memset32(vaddr, val ^ 0xdeadbeaf, val 69 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c err = i915_gem_object_fill_blt(obj, ce, val); val 81 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c if (vaddr[i] != val) { val 83 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c vaddr[i], val); val 122 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c u32 val = prandom_u32_state(&prng); val 129 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c phys_sz, sz, val); val 143 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c memset32(vaddr, val, val 163 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c memset32(vaddr, val ^ 0xdeadbeaf, val 182 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c if (vaddr[i] != val) { val 184 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c vaddr[i], val); val 42 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c u32 val) val 70 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c *cmd++ = val; val 76 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c *cmd++ = val; val 80 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c *cmd++ = val; val 109 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c u32 val) val 121 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c batch = igt_emit_store_dw(vma, offset, count, val); val 24 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h u32 val); val 31 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h u32 val); val 907 drivers/gpu/drm/i915/gt/intel_engine_cs.c u32 mcr_mask, mcr_ss, mcr, old_mcr, val; val 933 drivers/gpu/drm/i915/gt/intel_engine_cs.c val = intel_uncore_read_fw(uncore, reg); val 943 drivers/gpu/drm/i915/gt/intel_engine_cs.c return val; val 42 drivers/gpu/drm/i915/gt/intel_lrc_reg.h #define CTX_REG(reg_state, pos, reg, val) do { \ val 46 drivers/gpu/drm/i915/gt/intel_lrc_reg.h (reg_state__)[(pos__) + 1] = (val); \ val 70 drivers/gpu/drm/i915/gt/intel_renderstate.c #define OUT_BATCH(batch, i, val) \ val 74 drivers/gpu/drm/i915/gt/intel_renderstate.c (batch)[(i)++] = (val); \ val 113 drivers/gpu/drm/i915/gt/intel_sseu.c u32 mask, val = slices; val 117 drivers/gpu/drm/i915/gt/intel_sseu.c val <<= GEN11_RPCS_S_CNT_SHIFT; val 120 drivers/gpu/drm/i915/gt/intel_sseu.c val <<= GEN8_RPCS_S_CNT_SHIFT; val 123 drivers/gpu/drm/i915/gt/intel_sseu.c GEM_BUG_ON(val & ~mask); val 124 drivers/gpu/drm/i915/gt/intel_sseu.c val &= mask; val 126 drivers/gpu/drm/i915/gt/intel_sseu.c rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val; val 130 drivers/gpu/drm/i915/gt/intel_sseu.c u32 val = subslices; val 132 drivers/gpu/drm/i915/gt/intel_sseu.c val <<= GEN8_RPCS_SS_CNT_SHIFT; val 134 drivers/gpu/drm/i915/gt/intel_sseu.c GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK); val 135 drivers/gpu/drm/i915/gt/intel_sseu.c val &= GEN8_RPCS_SS_CNT_MASK; val 137 drivers/gpu/drm/i915/gt/intel_sseu.c rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val; val 141 drivers/gpu/drm/i915/gt/intel_sseu.c u32 val; val 143 drivers/gpu/drm/i915/gt/intel_sseu.c val = ctx_sseu.min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT; val 144 drivers/gpu/drm/i915/gt/intel_sseu.c GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK); val 145 drivers/gpu/drm/i915/gt/intel_sseu.c val &= GEN8_RPCS_EU_MIN_MASK; val 147 drivers/gpu/drm/i915/gt/intel_sseu.c rpcs |= val; val 149 drivers/gpu/drm/i915/gt/intel_sseu.c val = ctx_sseu.max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT; val 150 drivers/gpu/drm/i915/gt/intel_sseu.c GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK); val 151 drivers/gpu/drm/i915/gt/intel_sseu.c val &= GEN8_RPCS_EU_MAX_MASK; val 153 drivers/gpu/drm/i915/gt/intel_sseu.c rpcs |= val; val 120 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->mask, wa_->val); val 122 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->val &= ~wa->mask; val 126 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->val |= wa->val; val 150 drivers/gpu/drm/i915/gt/intel_workarounds.c u32 val) val 155 drivers/gpu/drm/i915/gt/intel_workarounds.c .val = val, val 163 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) val 165 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val)); val 169 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val) val 171 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, reg, ~0, val); val 175 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val) val 177 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, reg, val, val); val 639 drivers/gpu/drm/i915/gt/intel_workarounds.c *cs++ = wa->val; val 953 drivers/gpu/drm/i915/gt/intel_workarounds.c if ((cur ^ wa->val) & wa->read) { val 957 drivers/gpu/drm/i915/gt/intel_workarounds.c wa->val, wa->mask); val 982 drivers/gpu/drm/i915/gt/intel_workarounds.c intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val); val 17 drivers/gpu/drm/i915/gt/intel_workarounds_types.h u32 val; val 83 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c u32 val = intel_uncore_read(uncore, GUC_STATUS); val 84 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c u32 uk_val = val & GS_UKERNEL_MASK; val 86 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c *status = val; val 88 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c ((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE)); val 139 drivers/gpu/drm/i915/gt/uc/intel_uc.c u32 val; val 143 drivers/gpu/drm/i915/gt/uc/intel_uc.c val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15)); val 144 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->mmio_msg |= val & guc->msg_enabled_mask; val 124 drivers/gpu/drm/i915/gvt/cfg_space.c u64 val; val 130 drivers/gpu/drm/i915/gvt/cfg_space.c val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2]; val 131 drivers/gpu/drm/i915/gvt/cfg_space.c if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) val 132 drivers/gpu/drm/i915/gvt/cfg_space.c val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); val 134 drivers/gpu/drm/i915/gvt/cfg_space.c val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); val 136 drivers/gpu/drm/i915/gvt/cfg_space.c first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT; val 152 drivers/gpu/drm/i915/gvt/cfg_space.c u64 val; val 158 drivers/gpu/drm/i915/gvt/cfg_space.c val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0]; val 159 drivers/gpu/drm/i915/gvt/cfg_space.c if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) val 812 drivers/gpu/drm/i915/gvt/cmd_parser.c #define patch_value(s, addr, val) do { \ val 813 drivers/gpu/drm/i915/gvt/cmd_parser.c *addr = val; \ val 1115 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 hws_pga, val; val 1145 drivers/gpu/drm/i915/gvt/cmd_parser.c val = cmd_val(s, 1) & (~(1 << 21)); val 1146 drivers/gpu/drm/i915/gvt/cmd_parser.c patch_value(s, cmd_ptr(s, 1), val); val 1644 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 hws_pga, val; val 1671 drivers/gpu/drm/i915/gvt/cmd_parser.c val = cmd_val(s, 0) & (~(1 << 21)); val 1672 drivers/gpu/drm/i915/gvt/cmd_parser.c patch_value(s, cmd_ptr(s, 0), val); val 128 drivers/gpu/drm/i915/gvt/debugfs.c vgpu_scan_nonprivbb_get(void *data, u64 *val) val 131 drivers/gpu/drm/i915/gvt/debugfs.c *val = vgpu->scan_nonprivbb; val 142 drivers/gpu/drm/i915/gvt/debugfs.c vgpu_scan_nonprivbb_set(void *data, u64 val) val 150 drivers/gpu/drm/i915/gvt/debugfs.c val &= (1 << I915_NUM_ENGINES) - 1; val 152 drivers/gpu/drm/i915/gvt/debugfs.c if (vgpu->scan_nonprivbb == val) val 155 drivers/gpu/drm/i915/gvt/debugfs.c if (!val) val 168 drivers/gpu/drm/i915/gvt/debugfs.c if (engine && (val & (1 << id))) { val 172 drivers/gpu/drm/i915/gvt/debugfs.c val &= ~(1 << id); val 175 drivers/gpu/drm/i915/gvt/debugfs.c if (val) val 181 drivers/gpu/drm/i915/gvt/debugfs.c vgpu->scan_nonprivbb = val; val 540 drivers/gpu/drm/i915/gvt/edid.c unsigned char val = edid_get_byte(vgpu); val 542 drivers/gpu/drm/i915/gvt/edid.c aux_data_for_write = (val << 16); val 123 drivers/gpu/drm/i915/gvt/execlist.h u32 val; val 205 drivers/gpu/drm/i915/gvt/fb_decoder.c u32 val, fmt; val 213 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); val 214 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); val 219 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->tiled = val & PLANE_CTL_TILED_MASK; val 221 drivers/gpu/drm/i915/gvt/fb_decoder.c val & PLANE_CTL_FORMAT_MASK, val 222 drivers/gpu/drm/i915/gvt/fb_decoder.c val & PLANE_CTL_ORDER_RGBX, val 223 drivers/gpu/drm/i915/gvt/fb_decoder.c val & PLANE_CTL_ALPHA_MASK, val 224 drivers/gpu/drm/i915/gvt/fb_decoder.c val & PLANE_CTL_YUV422_ORDER_MASK); val 234 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->tiled = val & DISPPLANE_TILED; val 235 drivers/gpu/drm/i915/gvt/fb_decoder.c fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK); val 270 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); val 271 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> val 273 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> val 335 drivers/gpu/drm/i915/gvt/fb_decoder.c u32 val, mode, index; val 344 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, CURCNTR(pipe)); val 345 drivers/gpu/drm/i915/gvt/fb_decoder.c mode = val & MCURSOR_MODE; val 362 drivers/gpu/drm/i915/gvt/fb_decoder.c alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >> val 364 drivers/gpu/drm/i915/gvt/fb_decoder.c alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >> val 381 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, CURPOS(pipe)); val 382 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; val 383 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; val 384 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; val 385 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT; val 414 drivers/gpu/drm/i915/gvt/fb_decoder.c u32 val, fmt; val 423 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, SPRCTL(pipe)); val 424 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->enabled = !!(val & SPRITE_ENABLE); val 428 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->tiled = !!(val & SPRITE_TILED); val 429 drivers/gpu/drm/i915/gvt/fb_decoder.c color_order = !!(val & SPRITE_RGB_ORDER_RGBX); val 430 drivers/gpu/drm/i915/gvt/fb_decoder.c yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >> val 433 drivers/gpu/drm/i915/gvt/fb_decoder.c fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT; val 488 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, SPRSIZE(pipe)); val 489 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> val 491 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> val 496 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, SPRPOS(pipe)); val 497 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; val 498 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; val 500 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, SPROFFSET(pipe)); val 501 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> val 503 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> val 459 drivers/gpu/drm/i915/gvt/gvt.h u32 offset, u32 val, bool low) val 472 drivers/gpu/drm/i915/gvt/gvt.h *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); val 474 drivers/gpu/drm/i915/gvt/gvt.h *pval = val; val 1301 drivers/gpu/drm/i915/gvt/handlers.c u32 val = *(u32 *)p_data; val 1305 drivers/gpu/drm/i915/gvt/handlers.c offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { val 328 drivers/gpu/drm/i915/gvt/interrupt.c u32 val = vgpu_vreg(vgpu, val 347 drivers/gpu/drm/i915/gvt/interrupt.c if (val & map->down_irq_bitmask) val 1012 drivers/gpu/drm/i915/gvt/kvmgt.c u64 val; val 1014 drivers/gpu/drm/i915/gvt/kvmgt.c ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val), val 1019 drivers/gpu/drm/i915/gvt/kvmgt.c if (copy_to_user(buf, &val, sizeof(val))) val 1024 drivers/gpu/drm/i915/gvt/kvmgt.c u32 val; val 1026 drivers/gpu/drm/i915/gvt/kvmgt.c ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val), val 1031 drivers/gpu/drm/i915/gvt/kvmgt.c if (copy_to_user(buf, &val, sizeof(val))) val 1036 drivers/gpu/drm/i915/gvt/kvmgt.c u16 val; val 1038 drivers/gpu/drm/i915/gvt/kvmgt.c ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val), val 1043 drivers/gpu/drm/i915/gvt/kvmgt.c if (copy_to_user(buf, &val, sizeof(val))) val 1048 drivers/gpu/drm/i915/gvt/kvmgt.c u8 val; val 1050 drivers/gpu/drm/i915/gvt/kvmgt.c ret = intel_vgpu_rw(mdev, &val, sizeof(val), ppos, val 1055 drivers/gpu/drm/i915/gvt/kvmgt.c if (copy_to_user(buf, &val, sizeof(val))) val 1086 drivers/gpu/drm/i915/gvt/kvmgt.c u64 val; val 1088 drivers/gpu/drm/i915/gvt/kvmgt.c if (copy_from_user(&val, buf, sizeof(val))) val 1091 drivers/gpu/drm/i915/gvt/kvmgt.c ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val), val 1098 drivers/gpu/drm/i915/gvt/kvmgt.c u32 val; val 1100 drivers/gpu/drm/i915/gvt/kvmgt.c if (copy_from_user(&val, buf, sizeof(val))) val 1103 drivers/gpu/drm/i915/gvt/kvmgt.c ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val), val 1110 drivers/gpu/drm/i915/gvt/kvmgt.c u16 val; val 1112 drivers/gpu/drm/i915/gvt/kvmgt.c if (copy_from_user(&val, buf, sizeof(val))) val 1115 drivers/gpu/drm/i915/gvt/kvmgt.c ret = intel_vgpu_rw(mdev, (char *)&val, val 1116 drivers/gpu/drm/i915/gvt/kvmgt.c sizeof(val), ppos, true); val 1122 drivers/gpu/drm/i915/gvt/kvmgt.c u8 val; val 1124 drivers/gpu/drm/i915/gvt/kvmgt.c if (copy_from_user(&val, buf, sizeof(val))) val 1127 drivers/gpu/drm/i915/gvt/kvmgt.c ret = intel_vgpu_rw(mdev, &val, sizeof(val), val 1703 drivers/gpu/drm/i915/gvt/kvmgt.c const u8 *val, int len, val 1711 drivers/gpu/drm/i915/gvt/kvmgt.c (void *)val, len); val 94 drivers/gpu/drm/i915/gvt/reg.h #define GFX_MODE_BIT_SET_IN_MASK(val, bit) \ val 95 drivers/gpu/drm/i915/gvt/reg.h ((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16)))) val 55 drivers/gpu/drm/i915/gvt/scheduler.c ring_context->pdps[i].val = pdp[7 - i]; val 145 drivers/gpu/drm/i915/gvt/scheduler.c + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) val 148 drivers/gpu/drm/i915/gvt/scheduler.c + RING_CTX_OFF(name.val),\ val 149 drivers/gpu/drm/i915/gvt/scheduler.c &shadow_ring_context->name.val, 4);\ val 150 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context->name.val |= 0xffff << 16;\ val 174 drivers/gpu/drm/i915/gvt/scheduler.c if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val)) val 538 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context->bb_per_ctx_ptr.val = val 539 drivers/gpu/drm/i915/gvt/scheduler.c (shadow_ring_context->bb_per_ctx_ptr.val & val 541 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context->rcs_indirect_ctx.val = val 542 drivers/gpu/drm/i915/gvt/scheduler.c (shadow_ring_context->rcs_indirect_ctx.val & val 860 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4); val 867 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) val 1422 drivers/gpu/drm/i915/gvt/scheduler.c gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val); val 1497 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(ring_header.val), &head, 4); val 1500 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(ring_tail.val), &tail, 4); val 1527 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(rb_start.val), &start, 4); val 1529 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(rb_ctrl.val), &ctl, 4); val 1531 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4); val 1554 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4); val 1556 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4); val 1346 drivers/gpu/drm/i915/i915_debugfs.c static int i915_fbc_false_color_get(void *data, u64 *val) val 1353 drivers/gpu/drm/i915/i915_debugfs.c *val = dev_priv->fbc.false_color; val 1358 drivers/gpu/drm/i915/i915_debugfs.c static int i915_fbc_false_color_set(void *data, u64 val) val 1369 drivers/gpu/drm/i915/i915_debugfs.c dev_priv->fbc.false_color = val; val 1371 drivers/gpu/drm/i915/i915_debugfs.c I915_WRITE(ILK_DPFC_CONTROL, val ? val 2004 drivers/gpu/drm/i915/i915_debugfs.c static int i915_guc_log_level_get(void *data, u64 *val) val 2011 drivers/gpu/drm/i915/i915_debugfs.c *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log); val 2016 drivers/gpu/drm/i915/i915_debugfs.c static int i915_guc_log_level_set(void *data, u64 val) val 2023 drivers/gpu/drm/i915/i915_debugfs.c return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val); val 2074 drivers/gpu/drm/i915/i915_debugfs.c u8 val; val 2099 drivers/gpu/drm/i915/i915_debugfs.c ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val); val 2104 drivers/gpu/drm/i915/i915_debugfs.c val &= DP_PSR_SINK_STATE_MASK; val 2105 drivers/gpu/drm/i915/i915_debugfs.c if (val < ARRAY_SIZE(sink_status)) val 2106 drivers/gpu/drm/i915/i915_debugfs.c str = sink_status[val]; val 2107 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str); val 2119 drivers/gpu/drm/i915/i915_debugfs.c u32 val, status_val; val 2136 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR2_STATUS); val 2137 drivers/gpu/drm/i915/i915_debugfs.c status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >> val 2152 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR_STATUS); val 2153 drivers/gpu/drm/i915/i915_debugfs.c status_val = (val & EDP_PSR_STATUS_STATE_MASK) >> val 2159 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val); val 2169 drivers/gpu/drm/i915/i915_debugfs.c u32 val; val 2195 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR2_CTL); val 2196 drivers/gpu/drm/i915/i915_debugfs.c enabled = val & EDP_PSR2_ENABLE; val 2198 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR_CTL); val 2199 drivers/gpu/drm/i915/i915_debugfs.c enabled = val & EDP_PSR_ENABLE; val 2202 drivers/gpu/drm/i915/i915_debugfs.c enableddisabled(enabled), val); val 2211 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR_PERF_CNT) & EDP_PSR_PERF_CNT_MASK; val 2212 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Performance counter: %u\n", val); val 2252 drivers/gpu/drm/i915/i915_debugfs.c i915_edp_psr_debug_set(void *data, u64 val) val 2261 drivers/gpu/drm/i915/i915_debugfs.c DRM_DEBUG_KMS("Setting PSR debug to %llx\n", val); val 2265 drivers/gpu/drm/i915/i915_debugfs.c ret = intel_psr_debug_set(dev_priv, val); val 2273 drivers/gpu/drm/i915/i915_debugfs.c i915_edp_psr_debug_get(void *data, u64 *val) val 2280 drivers/gpu/drm/i915/i915_debugfs.c *val = READ_ONCE(dev_priv->psr.debug); val 2893 drivers/gpu/drm/i915/i915_debugfs.c wa->val, wa->mask); val 3132 drivers/gpu/drm/i915/i915_debugfs.c int val = 0; val 3159 drivers/gpu/drm/i915/i915_debugfs.c status = kstrtoint(input_buffer, 10, &val); val 3162 drivers/gpu/drm/i915/i915_debugfs.c DRM_DEBUG_DRIVER("Got %d for test active\n", val); val 3166 drivers/gpu/drm/i915/i915_debugfs.c if (val == 1) val 3541 drivers/gpu/drm/i915/i915_debugfs.c i915_wedged_get(void *data, u64 *val) val 3548 drivers/gpu/drm/i915/i915_debugfs.c *val = 1; val 3551 drivers/gpu/drm/i915/i915_debugfs.c *val = 0; val 3559 drivers/gpu/drm/i915/i915_debugfs.c i915_wedged_set(void *data, u64 val) val 3567 drivers/gpu/drm/i915/i915_debugfs.c intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE, val 3568 drivers/gpu/drm/i915/i915_debugfs.c "Manually set wedged engine mask = %llx", val); val 3595 drivers/gpu/drm/i915/i915_debugfs.c i915_drop_caches_get(void *data, u64 *val) val 3597 drivers/gpu/drm/i915/i915_debugfs.c *val = DROP_ALL; val 3603 drivers/gpu/drm/i915/i915_debugfs.c i915_drop_caches_set(void *data, u64 val) val 3608 drivers/gpu/drm/i915/i915_debugfs.c val, val & DROP_ALL); val 3610 drivers/gpu/drm/i915/i915_debugfs.c if (val & DROP_RESET_ACTIVE && val 3617 drivers/gpu/drm/i915/i915_debugfs.c if (val & (DROP_ACTIVE | DROP_IDLE | DROP_RETIRE | DROP_RESET_SEQNO)) { val 3630 drivers/gpu/drm/i915/i915_debugfs.c if (ret == 0 && val & (DROP_IDLE | DROP_ACTIVE)) val 3636 drivers/gpu/drm/i915/i915_debugfs.c if (ret == 0 && val & DROP_IDLE) val 3642 drivers/gpu/drm/i915/i915_debugfs.c if (val & DROP_RETIRE) val 3647 drivers/gpu/drm/i915/i915_debugfs.c if (ret == 0 && val & DROP_IDLE) val 3651 drivers/gpu/drm/i915/i915_debugfs.c if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(&i915->gt)) val 3655 drivers/gpu/drm/i915/i915_debugfs.c if (val & DROP_BOUND) val 3658 drivers/gpu/drm/i915/i915_debugfs.c if (val & DROP_UNBOUND) val 3661 drivers/gpu/drm/i915/i915_debugfs.c if (val & DROP_SHRINK_ALL) val 3665 drivers/gpu/drm/i915/i915_debugfs.c if (val & DROP_IDLE) { val 3670 drivers/gpu/drm/i915/i915_debugfs.c if (val & DROP_FREED) val 3681 drivers/gpu/drm/i915/i915_debugfs.c i915_cache_sharing_get(void *data, u64 *val) val 3693 drivers/gpu/drm/i915/i915_debugfs.c *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; val 3699 drivers/gpu/drm/i915/i915_debugfs.c i915_cache_sharing_set(void *data, u64 val) val 3707 drivers/gpu/drm/i915/i915_debugfs.c if (val > 3) val 3710 drivers/gpu/drm/i915/i915_debugfs.c DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); val 3717 drivers/gpu/drm/i915/i915_debugfs.c snpcr |= val << GEN6_MBC_SNPCR_SHIFT; val 4162 drivers/gpu/drm/i915/i915_debugfs.c static int i915_drrs_ctl_set(void *data, u64 val) val 4209 drivers/gpu/drm/i915/i915_debugfs.c val ? "en" : "dis", val); val 4212 drivers/gpu/drm/i915/i915_debugfs.c if (val) val 743 drivers/gpu/drm/i915/i915_drv.c static int skl_get_dimm_size(u16 val) val 745 drivers/gpu/drm/i915/i915_drv.c return val & SKL_DRAM_SIZE_MASK; val 748 drivers/gpu/drm/i915/i915_drv.c static int skl_get_dimm_width(u16 val) val 750 drivers/gpu/drm/i915/i915_drv.c if (skl_get_dimm_size(val) == 0) val 753 drivers/gpu/drm/i915/i915_drv.c switch (val & SKL_DRAM_WIDTH_MASK) { val 757 drivers/gpu/drm/i915/i915_drv.c val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT; val 758 drivers/gpu/drm/i915/i915_drv.c return 8 << val; val 760 drivers/gpu/drm/i915/i915_drv.c MISSING_CASE(val); val 765 drivers/gpu/drm/i915/i915_drv.c static int skl_get_dimm_ranks(u16 val) val 767 drivers/gpu/drm/i915/i915_drv.c if (skl_get_dimm_size(val) == 0) val 770 drivers/gpu/drm/i915/i915_drv.c val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT; val 772 drivers/gpu/drm/i915/i915_drv.c return val + 1; val 776 drivers/gpu/drm/i915/i915_drv.c static int cnl_get_dimm_size(u16 val) val 778 drivers/gpu/drm/i915/i915_drv.c return (val & CNL_DRAM_SIZE_MASK) / 2; val 781 drivers/gpu/drm/i915/i915_drv.c static int cnl_get_dimm_width(u16 val) val 783 drivers/gpu/drm/i915/i915_drv.c if (cnl_get_dimm_size(val) == 0) val 786 drivers/gpu/drm/i915/i915_drv.c switch (val & CNL_DRAM_WIDTH_MASK) { val 790 drivers/gpu/drm/i915/i915_drv.c val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT; val 791 drivers/gpu/drm/i915/i915_drv.c return 8 << val; val 793 drivers/gpu/drm/i915/i915_drv.c MISSING_CASE(val); val 798 drivers/gpu/drm/i915/i915_drv.c static int cnl_get_dimm_ranks(u16 val) val 800 drivers/gpu/drm/i915/i915_drv.c if (cnl_get_dimm_size(val) == 0) val 803 drivers/gpu/drm/i915/i915_drv.c val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT; val 805 drivers/gpu/drm/i915/i915_drv.c return val + 1; val 818 drivers/gpu/drm/i915/i915_drv.c int channel, char dimm_name, u16 val) val 821 drivers/gpu/drm/i915/i915_drv.c dimm->size = cnl_get_dimm_size(val); val 822 drivers/gpu/drm/i915/i915_drv.c dimm->width = cnl_get_dimm_width(val); val 823 drivers/gpu/drm/i915/i915_drv.c dimm->ranks = cnl_get_dimm_ranks(val); val 825 drivers/gpu/drm/i915/i915_drv.c dimm->size = skl_get_dimm_size(val); val 826 drivers/gpu/drm/i915/i915_drv.c dimm->width = skl_get_dimm_width(val); val 827 drivers/gpu/drm/i915/i915_drv.c dimm->ranks = skl_get_dimm_ranks(val); val 838 drivers/gpu/drm/i915/i915_drv.c int channel, u32 val) val 841 drivers/gpu/drm/i915/i915_drv.c channel, 'L', val & 0xffff); val 843 drivers/gpu/drm/i915/i915_drv.c channel, 'S', val >> 16); val 881 drivers/gpu/drm/i915/i915_drv.c u32 val; val 884 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); val 885 drivers/gpu/drm/i915/i915_drv.c ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val); val 889 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); val 890 drivers/gpu/drm/i915/i915_drv.c ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val); val 926 drivers/gpu/drm/i915/i915_drv.c u32 val; val 928 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); val 930 drivers/gpu/drm/i915/i915_drv.c switch (val & SKL_DRAM_DDR_TYPE_MASK) { val 940 drivers/gpu/drm/i915/i915_drv.c MISSING_CASE(val); val 949 drivers/gpu/drm/i915/i915_drv.c u32 mem_freq_khz, val; val 959 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); val 960 drivers/gpu/drm/i915/i915_drv.c mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) * val 976 drivers/gpu/drm/i915/i915_drv.c static int bxt_get_dimm_size(u32 val) val 978 drivers/gpu/drm/i915/i915_drv.c switch (val & BXT_DRAM_SIZE_MASK) { val 990 drivers/gpu/drm/i915/i915_drv.c MISSING_CASE(val); val 995 drivers/gpu/drm/i915/i915_drv.c static int bxt_get_dimm_width(u32 val) val 997 drivers/gpu/drm/i915/i915_drv.c if (!bxt_get_dimm_size(val)) val 1000 drivers/gpu/drm/i915/i915_drv.c val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT; val 1002 drivers/gpu/drm/i915/i915_drv.c return 8 << val; val 1005 drivers/gpu/drm/i915/i915_drv.c static int bxt_get_dimm_ranks(u32 val) val 1007 drivers/gpu/drm/i915/i915_drv.c if (!bxt_get_dimm_size(val)) val 1010 drivers/gpu/drm/i915/i915_drv.c switch (val & BXT_DRAM_RANK_MASK) { val 1016 drivers/gpu/drm/i915/i915_drv.c MISSING_CASE(val); val 1021 drivers/gpu/drm/i915/i915_drv.c static enum intel_dram_type bxt_get_dimm_type(u32 val) val 1023 drivers/gpu/drm/i915/i915_drv.c if (!bxt_get_dimm_size(val)) val 1026 drivers/gpu/drm/i915/i915_drv.c switch (val & BXT_DRAM_TYPE_MASK) { val 1036 drivers/gpu/drm/i915/i915_drv.c MISSING_CASE(val); val 1042 drivers/gpu/drm/i915/i915_drv.c u32 val) val 1044 drivers/gpu/drm/i915/i915_drv.c dimm->width = bxt_get_dimm_width(val); val 1045 drivers/gpu/drm/i915/i915_drv.c dimm->ranks = bxt_get_dimm_ranks(val); val 1051 drivers/gpu/drm/i915/i915_drv.c dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8; val 1059 drivers/gpu/drm/i915/i915_drv.c u32 mem_freq_khz, val; val 1063 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0); val 1064 drivers/gpu/drm/i915/i915_drv.c mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) * val 1067 drivers/gpu/drm/i915/i915_drv.c dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK; val 1085 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(BXT_D_CR_DRP0_DUNIT(i)); val 1086 drivers/gpu/drm/i915/i915_drv.c if (val == 0xFFFFFFFF) val 1091 drivers/gpu/drm/i915/i915_drv.c bxt_get_dimm_info(&dimm, val); val 1092 drivers/gpu/drm/i915/i915_drv.c type = bxt_get_dimm_type(val); val 2329 drivers/gpu/drm/i915/i915_drv.c u32 val; val 2397 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(VLV_GTLC_WAKE_CTRL); val 2398 drivers/gpu/drm/i915/i915_drv.c val &= VLV_GTLC_ALLOWWAKEREQ; val 2399 drivers/gpu/drm/i915/i915_drv.c val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; val 2400 drivers/gpu/drm/i915/i915_drv.c I915_WRITE(VLV_GTLC_WAKE_CTRL, val); val 2402 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); val 2403 drivers/gpu/drm/i915/i915_drv.c val &= VLV_GFX_CLK_FORCE_ON_BIT; val 2404 drivers/gpu/drm/i915/i915_drv.c val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; val 2405 drivers/gpu/drm/i915/i915_drv.c I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); val 2417 drivers/gpu/drm/i915/i915_drv.c u32 mask, u32 val) val 2432 drivers/gpu/drm/i915/i915_drv.c == val, 3); val 2442 drivers/gpu/drm/i915/i915_drv.c u32 val; val 2445 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); val 2446 drivers/gpu/drm/i915/i915_drv.c val &= ~VLV_GFX_CLK_FORCE_ON_BIT; val 2448 drivers/gpu/drm/i915/i915_drv.c val |= VLV_GFX_CLK_FORCE_ON_BIT; val 2449 drivers/gpu/drm/i915/i915_drv.c I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); val 2469 drivers/gpu/drm/i915/i915_drv.c u32 val; val 2472 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(VLV_GTLC_WAKE_CTRL); val 2473 drivers/gpu/drm/i915/i915_drv.c val &= ~VLV_GTLC_ALLOWWAKEREQ; val 2475 drivers/gpu/drm/i915/i915_drv.c val |= VLV_GTLC_ALLOWWAKEREQ; val 2476 drivers/gpu/drm/i915/i915_drv.c I915_WRITE(VLV_GTLC_WAKE_CTRL, val); val 2480 drivers/gpu/drm/i915/i915_drv.c val = allow ? mask : 0; val 2482 drivers/gpu/drm/i915/i915_drv.c err = vlv_wait_for_pw_status(dev_priv, mask, val); val 2493 drivers/gpu/drm/i915/i915_drv.c u32 val; val 2496 drivers/gpu/drm/i915/i915_drv.c val = wait_for_on ? mask : 0; val 2505 drivers/gpu/drm/i915/i915_drv.c if (vlv_wait_for_pw_status(dev_priv, mask, val)) val 15 drivers/gpu/drm/i915/i915_fixed.h u32 val; val 18 drivers/gpu/drm/i915/i915_fixed.h #define FP_16_16_MAX ((uint_fixed_16_16_t){ .val = UINT_MAX }) val 20 drivers/gpu/drm/i915/i915_fixed.h static inline bool is_fixed16_zero(uint_fixed_16_16_t val) val 22 drivers/gpu/drm/i915/i915_fixed.h return val.val == 0; val 25 drivers/gpu/drm/i915/i915_fixed.h static inline uint_fixed_16_16_t u32_to_fixed16(u32 val) val 27 drivers/gpu/drm/i915/i915_fixed.h uint_fixed_16_16_t fp = { .val = val << 16 }; val 29 drivers/gpu/drm/i915/i915_fixed.h WARN_ON(val > U16_MAX); val 36 drivers/gpu/drm/i915/i915_fixed.h return DIV_ROUND_UP(fp.val, 1 << 16); val 41 drivers/gpu/drm/i915/i915_fixed.h return fp.val >> 16; val 47 drivers/gpu/drm/i915/i915_fixed.h uint_fixed_16_16_t min = { .val = min(min1.val, min2.val) }; val 55 drivers/gpu/drm/i915/i915_fixed.h uint_fixed_16_16_t max = { .val = max(max1.val, max2.val) }; val 60 drivers/gpu/drm/i915/i915_fixed.h static inline uint_fixed_16_16_t clamp_u64_to_fixed16(u64 val) val 62 drivers/gpu/drm/i915/i915_fixed.h uint_fixed_16_16_t fp = { .val = (u32)val }; val 64 drivers/gpu/drm/i915/i915_fixed.h WARN_ON(val > U32_MAX); val 69 drivers/gpu/drm/i915/i915_fixed.h static inline u32 div_round_up_fixed16(uint_fixed_16_16_t val, val 72 drivers/gpu/drm/i915/i915_fixed.h return DIV_ROUND_UP(val.val, d.val); val 75 drivers/gpu/drm/i915/i915_fixed.h static inline u32 mul_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t mul) val 79 drivers/gpu/drm/i915/i915_fixed.h tmp = mul_u32_u32(val, mul.val); val 86 drivers/gpu/drm/i915/i915_fixed.h static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, val 91 drivers/gpu/drm/i915/i915_fixed.h tmp = mul_u32_u32(val.val, mul.val); val 97 drivers/gpu/drm/i915/i915_fixed.h static inline uint_fixed_16_16_t div_fixed16(u32 val, u32 d) val 101 drivers/gpu/drm/i915/i915_fixed.h tmp = (u64)val << 16; val 107 drivers/gpu/drm/i915/i915_fixed.h static inline u32 div_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t d) val 111 drivers/gpu/drm/i915/i915_fixed.h tmp = (u64)val << 16; val 112 drivers/gpu/drm/i915/i915_fixed.h tmp = DIV_ROUND_UP_ULL(tmp, d.val); val 118 drivers/gpu/drm/i915/i915_fixed.h static inline uint_fixed_16_16_t mul_u32_fixed16(u32 val, uint_fixed_16_16_t mul) val 122 drivers/gpu/drm/i915/i915_fixed.h tmp = mul_u32_u32(val, mul.val); val 132 drivers/gpu/drm/i915/i915_fixed.h tmp = (u64)add1.val + add2.val; val 143 drivers/gpu/drm/i915/i915_fixed.h tmp = (u64)add1.val + tmp_add2.val; val 67 drivers/gpu/drm/i915/i915_gem_fence_reg.c u64 val; val 80 drivers/gpu/drm/i915/i915_gem_fence_reg.c val = 0; val 89 drivers/gpu/drm/i915/i915_gem_fence_reg.c val = (vma->node.start + vma->fence_size - I965_FENCE_PAGE) << 32; val 90 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= vma->node.start; val 91 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= (u64)((stride / 128) - 1) << fence_pitch_shift; val 93 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= BIT(I965_FENCE_TILING_Y_SHIFT); val 94 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= I965_FENCE_REG_VALID; val 113 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val)); val 114 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val)); val 122 drivers/gpu/drm/i915/i915_gem_fence_reg.c u32 val; val 124 drivers/gpu/drm/i915/i915_gem_fence_reg.c val = 0; val 141 drivers/gpu/drm/i915/i915_gem_fence_reg.c val = vma->node.start; val 143 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= BIT(I830_FENCE_TILING_Y_SHIFT); val 144 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= I915_FENCE_SIZE_BITS(vma->fence_size); val 145 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT; val 147 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= I830_FENCE_REG_VALID; val 154 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_write_fw(uncore, reg, val); val 162 drivers/gpu/drm/i915/i915_gem_fence_reg.c u32 val; val 164 drivers/gpu/drm/i915/i915_gem_fence_reg.c val = 0; val 174 drivers/gpu/drm/i915/i915_gem_fence_reg.c val = vma->node.start; val 176 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= BIT(I830_FENCE_TILING_Y_SHIFT); val 177 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= I830_FENCE_SIZE_BITS(vma->fence_size); val 178 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT; val 179 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= I830_FENCE_REG_VALID; val 186 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_write_fw(uncore, reg, val); val 606 drivers/gpu/drm/i915/i915_gem_gtt.c fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count) val 608 drivers/gpu/drm/i915/i915_gem_gtt.c kunmap_atomic(memset64(kmap_atomic(p->page), val, count)); val 63 drivers/gpu/drm/i915/i915_irq.c typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val); val 212 drivers/gpu/drm/i915/i915_irq.c u32 val = intel_uncore_read(uncore, reg); val 214 drivers/gpu/drm/i915/i915_irq.c if (val == 0) val 218 drivers/gpu/drm/i915/i915_irq.c i915_mmio_reg_offset(reg), val); val 227 drivers/gpu/drm/i915/i915_irq.c u16 val = intel_uncore_read16(uncore, GEN2_IIR); val 229 drivers/gpu/drm/i915/i915_irq.c if (val == 0) val 233 drivers/gpu/drm/i915/i915_irq.c i915_mmio_reg_offset(GEN2_IIR), val); val 268 drivers/gpu/drm/i915/i915_irq.c u32 val; val 273 drivers/gpu/drm/i915/i915_irq.c val = I915_READ(PORT_HOTPLUG_EN); val 274 drivers/gpu/drm/i915/i915_irq.c val &= ~mask; val 275 drivers/gpu/drm/i915/i915_irq.c val |= bits; val 276 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(PORT_HOTPLUG_EN, val); val 1350 drivers/gpu/drm/i915/i915_irq.c static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1354 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1); val 1356 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2); val 1358 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3); val 1360 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4); val 1366 drivers/gpu/drm/i915/i915_irq.c static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1370 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1); val 1372 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2); val 1374 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3); val 1376 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4); val 1378 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5); val 1380 drivers/gpu/drm/i915/i915_irq.c return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6); val 1386 drivers/gpu/drm/i915/i915_irq.c static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1390 drivers/gpu/drm/i915/i915_irq.c return val & PORTA_HOTPLUG_LONG_DETECT; val 1392 drivers/gpu/drm/i915/i915_irq.c return val & PORTB_HOTPLUG_LONG_DETECT; val 1394 drivers/gpu/drm/i915/i915_irq.c return val & PORTC_HOTPLUG_LONG_DETECT; val 1400 drivers/gpu/drm/i915/i915_irq.c static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1404 drivers/gpu/drm/i915/i915_irq.c return val & ICP_DDIA_HPD_LONG_DETECT; val 1406 drivers/gpu/drm/i915/i915_irq.c return val & ICP_DDIB_HPD_LONG_DETECT; val 1408 drivers/gpu/drm/i915/i915_irq.c return val & TGP_DDIC_HPD_LONG_DETECT; val 1414 drivers/gpu/drm/i915/i915_irq.c static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1418 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); val 1420 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); val 1422 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); val 1424 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); val 1430 drivers/gpu/drm/i915/i915_irq.c static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1434 drivers/gpu/drm/i915/i915_irq.c return val & ICP_DDIA_HPD_LONG_DETECT; val 1436 drivers/gpu/drm/i915/i915_irq.c return val & ICP_DDIB_HPD_LONG_DETECT; val 1438 drivers/gpu/drm/i915/i915_irq.c return val & TGP_DDIC_HPD_LONG_DETECT; val 1444 drivers/gpu/drm/i915/i915_irq.c static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1448 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); val 1450 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); val 1452 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); val 1454 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); val 1456 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5); val 1458 drivers/gpu/drm/i915/i915_irq.c return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6); val 1464 drivers/gpu/drm/i915/i915_irq.c static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) val 1468 drivers/gpu/drm/i915/i915_irq.c return val & PORTE_HOTPLUG_LONG_DETECT; val 1474 drivers/gpu/drm/i915/i915_irq.c static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1478 drivers/gpu/drm/i915/i915_irq.c return val & PORTA_HOTPLUG_LONG_DETECT; val 1480 drivers/gpu/drm/i915/i915_irq.c return val & PORTB_HOTPLUG_LONG_DETECT; val 1482 drivers/gpu/drm/i915/i915_irq.c return val & PORTC_HOTPLUG_LONG_DETECT; val 1484 drivers/gpu/drm/i915/i915_irq.c return val & PORTD_HOTPLUG_LONG_DETECT; val 1490 drivers/gpu/drm/i915/i915_irq.c static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1494 drivers/gpu/drm/i915/i915_irq.c return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; val 1500 drivers/gpu/drm/i915/i915_irq.c static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1504 drivers/gpu/drm/i915/i915_irq.c return val & PORTB_HOTPLUG_LONG_DETECT; val 1506 drivers/gpu/drm/i915/i915_irq.c return val & PORTC_HOTPLUG_LONG_DETECT; val 1508 drivers/gpu/drm/i915/i915_irq.c return val & PORTD_HOTPLUG_LONG_DETECT; val 1514 drivers/gpu/drm/i915/i915_irq.c static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val) val 1518 drivers/gpu/drm/i915/i915_irq.c return val & PORTB_HOTPLUG_INT_LONG_PULSE; val 1520 drivers/gpu/drm/i915/i915_irq.c return val & PORTC_HOTPLUG_INT_LONG_PULSE; val 1522 drivers/gpu/drm/i915/i915_irq.c return val & PORTD_HOTPLUG_INT_LONG_PULSE; val 1539 drivers/gpu/drm/i915/i915_irq.c bool long_pulse_detect(enum hpd_pin pin, u32 val)) val 3495 drivers/gpu/drm/i915/i915_irq.c u32 val; val 3501 drivers/gpu/drm/i915/i915_irq.c val = I915_READ(GEN11_DE_HPD_IMR); val 3502 drivers/gpu/drm/i915/i915_irq.c val &= ~hotplug_irqs; val 3503 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(GEN11_DE_HPD_IMR, val); val 3516 drivers/gpu/drm/i915/i915_irq.c u32 val, hotplug; val 3520 drivers/gpu/drm/i915/i915_irq.c val = I915_READ(SOUTH_CHICKEN1); val 3521 drivers/gpu/drm/i915/i915_irq.c val &= ~CHASSIS_CLK_REQ_DURATION_MASK; val 3522 drivers/gpu/drm/i915/i915_irq.c val |= CHASSIS_CLK_REQ_DURATION(0xf); val 3523 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(SOUTH_CHICKEN1, val); val 917 drivers/gpu/drm/i915/i915_pci.c u16 val; val 919 drivers/gpu/drm/i915/i915_pci.c if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { val 3198 drivers/gpu/drm/i915/i915_perf.c static u32 mask_reg_value(u32 reg, u32 val) val 3205 drivers/gpu/drm/i915/i915_perf.c val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); val 3212 drivers/gpu/drm/i915/i915_perf.c val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); val 3214 drivers/gpu/drm/i915/i915_perf.c return val; val 162 drivers/gpu/drm/i915/i915_pmu.c add_sample(struct i915_pmu_sample *sample, u32 val) val 164 drivers/gpu/drm/i915/i915_pmu.c sample->cur += val; val 181 drivers/gpu/drm/i915/i915_pmu.c u32 val; val 188 drivers/gpu/drm/i915/i915_pmu.c val = ENGINE_READ_FW(engine, RING_CTL); val 189 drivers/gpu/drm/i915/i915_pmu.c if (val == 0) /* powerwell off => engine idle */ val 192 drivers/gpu/drm/i915/i915_pmu.c if (val & RING_WAIT) val 194 drivers/gpu/drm/i915/i915_pmu.c if (val & RING_WAIT_SEMAPHORE) val 204 drivers/gpu/drm/i915/i915_pmu.c busy = val & (RING_WAIT_SEMAPHORE | RING_WAIT); val 206 drivers/gpu/drm/i915/i915_pmu.c val = ENGINE_READ_FW(engine, RING_MI_MODE); val 207 drivers/gpu/drm/i915/i915_pmu.c busy = !(val & MODE_IDLE); val 219 drivers/gpu/drm/i915/i915_pmu.c add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul) val 221 drivers/gpu/drm/i915/i915_pmu.c sample->cur += mul_u32_u32(val, mul); val 232 drivers/gpu/drm/i915/i915_pmu.c u32 val; val 234 drivers/gpu/drm/i915/i915_pmu.c val = i915->gt_pm.rps.cur_freq; val 236 drivers/gpu/drm/i915/i915_pmu.c val = intel_uncore_read_notrace(uncore, GEN6_RPSTAT1); val 237 drivers/gpu/drm/i915/i915_pmu.c val = intel_get_cagf(i915, val); val 242 drivers/gpu/drm/i915/i915_pmu.c intel_gpu_freq(i915, val), val 432 drivers/gpu/drm/i915/i915_pmu.c u64 val; val 434 drivers/gpu/drm/i915/i915_pmu.c val = intel_rc6_residency_ns(i915, val 440 drivers/gpu/drm/i915/i915_pmu.c val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); val 443 drivers/gpu/drm/i915/i915_pmu.c val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); val 445 drivers/gpu/drm/i915/i915_pmu.c return val; val 456 drivers/gpu/drm/i915/i915_pmu.c u64 val; val 460 drivers/gpu/drm/i915/i915_pmu.c val = __get_rc6(gt); val 471 drivers/gpu/drm/i915/i915_pmu.c if (val >= pmu->sample[__I915_SAMPLE_RC6_ESTIMATED].cur) { val 473 drivers/gpu/drm/i915/i915_pmu.c pmu->sample[__I915_SAMPLE_RC6].cur = val; val 475 drivers/gpu/drm/i915/i915_pmu.c val = pmu->sample[__I915_SAMPLE_RC6_ESTIMATED].cur; val 503 drivers/gpu/drm/i915/i915_pmu.c val = pm_runtime_suspended_time(kdev); val 506 drivers/gpu/drm/i915/i915_pmu.c pmu->suspended_time_last = val; val 508 drivers/gpu/drm/i915/i915_pmu.c val -= pmu->suspended_time_last; val 509 drivers/gpu/drm/i915/i915_pmu.c val += pmu->sample[__I915_SAMPLE_RC6].cur; val 511 drivers/gpu/drm/i915/i915_pmu.c pmu->sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val; val 513 drivers/gpu/drm/i915/i915_pmu.c val = pmu->sample[__I915_SAMPLE_RC6_ESTIMATED].cur; val 515 drivers/gpu/drm/i915/i915_pmu.c val = pmu->sample[__I915_SAMPLE_RC6].cur; val 521 drivers/gpu/drm/i915/i915_pmu.c return val; val 532 drivers/gpu/drm/i915/i915_pmu.c u64 val = 0; val 546 drivers/gpu/drm/i915/i915_pmu.c val = ktime_to_ns(intel_engine_get_busy_time(engine)); val 548 drivers/gpu/drm/i915/i915_pmu.c val = engine->pmu.sample[sample].cur; val 553 drivers/gpu/drm/i915/i915_pmu.c val = val 558 drivers/gpu/drm/i915/i915_pmu.c val = val 563 drivers/gpu/drm/i915/i915_pmu.c val = count_interrupts(i915); val 566 drivers/gpu/drm/i915/i915_pmu.c val = get_rc6(&i915->gt); val 571 drivers/gpu/drm/i915/i915_pmu.c return val; val 756 drivers/gpu/drm/i915/i915_pmu.c unsigned long val; val 765 drivers/gpu/drm/i915/i915_pmu.c return sprintf(buf, "config=0x%lx\n", eattr->val); val 819 drivers/gpu/drm/i915/i915_pmu.c attr->val = config; val 1096 drivers/gpu/drm/i915/i915_reg.h #define _SSPM0_SSC(val) ((val) << 0) val 1102 drivers/gpu/drm/i915/i915_reg.h #define _SSPM0_SSS(val) ((val) << 24) val 1132 drivers/gpu/drm/i915/i915_reg.h #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) val 1138 drivers/gpu/drm/i915/i915_reg.h #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) val 2673 drivers/gpu/drm/i915/i915_reg.h #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) val 6296 drivers/gpu/drm/i915/i915_reg.h #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) val 6297 drivers/gpu/drm/i915/i915_reg.h #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) val 9391 drivers/gpu/drm/i915/i915_reg.h #define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT) val 9392 drivers/gpu/drm/i915/i915_reg.h #define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1) val 10384 drivers/gpu/drm/i915/i915_reg.h #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ val 10385 drivers/gpu/drm/i915/i915_reg.h (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) val 10397 drivers/gpu/drm/i915/i915_reg.h #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ val 10398 drivers/gpu/drm/i915/i915_reg.h (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) val 10410 drivers/gpu/drm/i915/i915_reg.h #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ val 10411 drivers/gpu/drm/i915/i915_reg.h (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) val 10423 drivers/gpu/drm/i915/i915_reg.h #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ val 10424 drivers/gpu/drm/i915/i915_reg.h (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) val 311 drivers/gpu/drm/i915/i915_sysfs.c u32 val; val 313 drivers/gpu/drm/i915/i915_sysfs.c ret = kstrtou32(buf, 0, &val); val 318 drivers/gpu/drm/i915/i915_sysfs.c val = intel_freq_opcode(dev_priv, val); val 319 drivers/gpu/drm/i915/i915_sysfs.c if (val < rps->min_freq || val > rps->max_freq) val 323 drivers/gpu/drm/i915/i915_sysfs.c if (val != rps->boost_freq) { val 324 drivers/gpu/drm/i915/i915_sysfs.c rps->boost_freq = val; val 360 drivers/gpu/drm/i915/i915_sysfs.c u32 val; val 363 drivers/gpu/drm/i915/i915_sysfs.c ret = kstrtou32(buf, 0, &val); val 370 drivers/gpu/drm/i915/i915_sysfs.c val = intel_freq_opcode(dev_priv, val); val 371 drivers/gpu/drm/i915/i915_sysfs.c if (val < rps->min_freq || val 372 drivers/gpu/drm/i915/i915_sysfs.c val > rps->max_freq || val 373 drivers/gpu/drm/i915/i915_sysfs.c val < rps->min_freq_softlimit) { val 378 drivers/gpu/drm/i915/i915_sysfs.c if (val > rps->rp0_freq) val 380 drivers/gpu/drm/i915/i915_sysfs.c intel_gpu_freq(dev_priv, val)); val 382 drivers/gpu/drm/i915/i915_sysfs.c rps->max_freq_softlimit = val; val 384 drivers/gpu/drm/i915/i915_sysfs.c val = clamp_t(int, rps->cur_freq, val 391 drivers/gpu/drm/i915/i915_sysfs.c ret = intel_set_rps(dev_priv, val); val 416 drivers/gpu/drm/i915/i915_sysfs.c u32 val; val 419 drivers/gpu/drm/i915/i915_sysfs.c ret = kstrtou32(buf, 0, &val); val 426 drivers/gpu/drm/i915/i915_sysfs.c val = intel_freq_opcode(dev_priv, val); val 427 drivers/gpu/drm/i915/i915_sysfs.c if (val < rps->min_freq || val 428 drivers/gpu/drm/i915/i915_sysfs.c val > rps->max_freq || val 429 drivers/gpu/drm/i915/i915_sysfs.c val > rps->max_freq_softlimit) { val 434 drivers/gpu/drm/i915/i915_sysfs.c rps->min_freq_softlimit = val; val 436 drivers/gpu/drm/i915/i915_sysfs.c val = clamp_t(int, rps->cur_freq, val 443 drivers/gpu/drm/i915/i915_sysfs.c ret = intel_set_rps(dev_priv, val); val 470 drivers/gpu/drm/i915/i915_sysfs.c u32 val; val 473 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->rp0_freq); val 475 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->rp1_freq); val 477 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->min_freq); val 481 drivers/gpu/drm/i915/i915_sysfs.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 868 drivers/gpu/drm/i915/i915_trace.h TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace), val 870 drivers/gpu/drm/i915/i915_trace.h TP_ARGS(write, reg, val, len, trace), val 875 drivers/gpu/drm/i915/i915_trace.h __field(u64, val) val 882 drivers/gpu/drm/i915/i915_trace.h __entry->val = (u64)val; val 891 drivers/gpu/drm/i915/i915_trace.h (u32)(__entry->val & 0xffffffff), val 892 drivers/gpu/drm/i915/i915_trace.h (u32)(__entry->val >> 32)) val 271 drivers/gpu/drm/i915/intel_csr.c u32 val, mask; val 279 drivers/gpu/drm/i915/intel_csr.c val = I915_READ(DC_STATE_DEBUG); val 280 drivers/gpu/drm/i915/intel_csr.c if ((val & mask) != mask) { val 281 drivers/gpu/drm/i915/intel_csr.c val |= mask; val 282 drivers/gpu/drm/i915/intel_csr.c I915_WRITE(DC_STATE_DEBUG, val); val 153 drivers/gpu/drm/i915/intel_pm.c u32 val = I915_READ(CHICKEN_MISC_2); val 154 drivers/gpu/drm/i915/intel_pm.c val &= ~(GLK_CL0_PWR_DOWN | val 157 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CHICKEN_MISC_2, val); val 331 drivers/gpu/drm/i915/intel_pm.c u32 val; val 335 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); val 337 drivers/gpu/drm/i915/intel_pm.c val &= ~FORCE_DDR_HIGH_FREQ; val 339 drivers/gpu/drm/i915/intel_pm.c val |= FORCE_DDR_HIGH_FREQ; val 340 drivers/gpu/drm/i915/intel_pm.c val &= ~FORCE_DDR_LOW_FREQ; val 341 drivers/gpu/drm/i915/intel_pm.c val |= FORCE_DDR_FREQ_REQ_ACK; val 342 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); val 353 drivers/gpu/drm/i915/intel_pm.c u32 val; val 357 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); val 359 drivers/gpu/drm/i915/intel_pm.c val |= DSP_MAXFIFO_PM5_ENABLE; val 361 drivers/gpu/drm/i915/intel_pm.c val &= ~DSP_MAXFIFO_PM5_ENABLE; val 362 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); val 373 drivers/gpu/drm/i915/intel_pm.c u32 val; val 384 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(DSPFW3); val 385 drivers/gpu/drm/i915/intel_pm.c was_enabled = val & PINEVIEW_SELF_REFRESH_EN; val 387 drivers/gpu/drm/i915/intel_pm.c val |= PINEVIEW_SELF_REFRESH_EN; val 389 drivers/gpu/drm/i915/intel_pm.c val &= ~PINEVIEW_SELF_REFRESH_EN; val 390 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DSPFW3, val); val 394 drivers/gpu/drm/i915/intel_pm.c val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : val 396 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(FW_BLC_SELF, val); val 405 drivers/gpu/drm/i915/intel_pm.c val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : val 407 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(INSTPM, val); val 2830 drivers/gpu/drm/i915/intel_pm.c u32 val; val 2835 drivers/gpu/drm/i915/intel_pm.c val = 0; /* data0 to be programmed to 0 for first set */ val 2838 drivers/gpu/drm/i915/intel_pm.c &val, NULL); val 2845 drivers/gpu/drm/i915/intel_pm.c wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; val 2846 drivers/gpu/drm/i915/intel_pm.c wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & val 2848 drivers/gpu/drm/i915/intel_pm.c wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & val 2850 drivers/gpu/drm/i915/intel_pm.c wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & val 2854 drivers/gpu/drm/i915/intel_pm.c val = 1; /* data0 to be programmed to 1 for second set */ val 2857 drivers/gpu/drm/i915/intel_pm.c &val, NULL); val 2863 drivers/gpu/drm/i915/intel_pm.c wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; val 2864 drivers/gpu/drm/i915/intel_pm.c wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & val 2866 drivers/gpu/drm/i915/intel_pm.c wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & val 2868 drivers/gpu/drm/i915/intel_pm.c wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & val 3554 drivers/gpu/drm/i915/intel_pm.c u32 val; val 3578 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(WM_MISC); val 3580 drivers/gpu/drm/i915/intel_pm.c val &= ~WM_MISC_DATA_PARTITION_5_6; val 3582 drivers/gpu/drm/i915/intel_pm.c val |= WM_MISC_DATA_PARTITION_5_6; val 3583 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(WM_MISC, val); val 3585 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(DISP_ARB_CTL2); val 3587 drivers/gpu/drm/i915/intel_pm.c val &= ~DISP_DATA_PARTITION_5_6; val 3589 drivers/gpu/drm/i915/intel_pm.c val |= DISP_DATA_PARTITION_5_6; val 3590 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DISP_ARB_CTL2, val); val 3595 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(DISP_ARB_CTL); val 3597 drivers/gpu/drm/i915/intel_pm.c val &= ~DISP_FBC_WM_DIS; val 3599 drivers/gpu/drm/i915/intel_pm.c val |= DISP_FBC_WM_DIS; val 3600 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DISP_ARB_CTL, val); val 3991 drivers/gpu/drm/i915/intel_pm.c u32 val, val2; val 3996 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(CUR_BUF_CFG(pipe)); val 3997 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); val 4001 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_CTL(pipe, plane_id)); val 4004 drivers/gpu/drm/i915/intel_pm.c if (val & PLANE_CTL_ENABLE) val 4005 drivers/gpu/drm/i915/intel_pm.c fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK, val 4006 drivers/gpu/drm/i915/intel_pm.c val & PLANE_CTL_ORDER_RGBX, val 4007 drivers/gpu/drm/i915/intel_pm.c val & PLANE_CTL_ALPHA_MASK); val 4010 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); val 4011 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); val 4013 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); val 4017 drivers/gpu/drm/i915/intel_pm.c swap(val, val2); val 4019 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); val 5135 drivers/gpu/drm/i915/intel_pm.c u32 val = 0; val 5138 drivers/gpu/drm/i915/intel_pm.c val |= PLANE_WM_EN; val 5140 drivers/gpu/drm/i915/intel_pm.c val |= PLANE_WM_IGNORE_LINES; val 5141 drivers/gpu/drm/i915/intel_pm.c val |= level->plane_res_b; val 5142 drivers/gpu/drm/i915/intel_pm.c val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; val 5144 drivers/gpu/drm/i915/intel_pm.c I915_WRITE_FW(reg, val); val 5758 drivers/gpu/drm/i915/intel_pm.c static inline void skl_wm_level_from_reg_val(u32 val, val 5761 drivers/gpu/drm/i915/intel_pm.c level->plane_en = val & PLANE_WM_EN; val 5762 drivers/gpu/drm/i915/intel_pm.c level->ignore_lines = val & PLANE_WM_IGNORE_LINES; val 5763 drivers/gpu/drm/i915/intel_pm.c level->plane_res_b = val & PLANE_WM_BLOCKS_MASK; val 5764 drivers/gpu/drm/i915/intel_pm.c level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) & val 5775 drivers/gpu/drm/i915/intel_pm.c u32 val; val 5784 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_WM(pipe, plane_id, level)); val 5786 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(CUR_WM(pipe, level)); val 5788 drivers/gpu/drm/i915/intel_pm.c skl_wm_level_from_reg_val(val, &wm->wm[level]); val 5792 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); val 5794 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(CUR_WM_TRANS(pipe)); val 5796 drivers/gpu/drm/i915/intel_pm.c skl_wm_level_from_reg_val(val, &wm->trans_wm); val 6130 drivers/gpu/drm/i915/intel_pm.c u32 val; val 6140 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); val 6141 drivers/gpu/drm/i915/intel_pm.c if (val & DSP_MAXFIFO_PM5_ENABLE) val 6153 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); val 6154 drivers/gpu/drm/i915/intel_pm.c val |= FORCE_DDR_FREQ_REQ_ACK; val 6155 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); val 6163 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); val 6164 drivers/gpu/drm/i915/intel_pm.c if ((val & FORCE_DDR_HIGH_FREQ) == 0) val 6362 drivers/gpu/drm/i915/intel_pm.c u32 val; val 6367 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(DISP_ARB_CTL2); val 6370 drivers/gpu/drm/i915/intel_pm.c val |= DISP_IPC_ENABLE; val 6372 drivers/gpu/drm/i915/intel_pm.c val &= ~DISP_IPC_ENABLE; val 6374 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DISP_ARB_CTL2, val); val 6405 drivers/gpu/drm/i915/intel_pm.c bool ironlake_set_drps(struct drm_i915_private *i915, u8 val) val 6419 drivers/gpu/drm/i915/intel_pm.c (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; val 6542 drivers/gpu/drm/i915/intel_pm.c static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) val 6555 drivers/gpu/drm/i915/intel_pm.c if (val <= rps->min_freq_softlimit) val 6559 drivers/gpu/drm/i915/intel_pm.c if (val <= rps->min_freq_softlimit) val 6642 drivers/gpu/drm/i915/intel_pm.c static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) val 6650 drivers/gpu/drm/i915/intel_pm.c if (val > rps->efficient_freq + 1 && val 6651 drivers/gpu/drm/i915/intel_pm.c val > rps->cur_freq) val 6656 drivers/gpu/drm/i915/intel_pm.c if (val <= rps->efficient_freq && val 6657 drivers/gpu/drm/i915/intel_pm.c val < rps->cur_freq) val 6659 drivers/gpu/drm/i915/intel_pm.c else if (val >= rps->rp0_freq && val 6660 drivers/gpu/drm/i915/intel_pm.c val > rps->cur_freq) val 6665 drivers/gpu/drm/i915/intel_pm.c if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 && val 6666 drivers/gpu/drm/i915/intel_pm.c val < rps->cur_freq) val 6671 drivers/gpu/drm/i915/intel_pm.c if (val <= rps->min_freq_softlimit) val 6673 drivers/gpu/drm/i915/intel_pm.c if (val >= rps->max_freq_softlimit) val 6701 drivers/gpu/drm/i915/intel_pm.c static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) val 6707 drivers/gpu/drm/i915/intel_pm.c if (val > rps->min_freq_softlimit) val 6709 drivers/gpu/drm/i915/intel_pm.c if (val < rps->max_freq_softlimit) val 6720 drivers/gpu/drm/i915/intel_pm.c static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) val 6727 drivers/gpu/drm/i915/intel_pm.c if (val != rps->cur_freq) { val 6728 drivers/gpu/drm/i915/intel_pm.c gen6_set_rps_thresholds(dev_priv, val); val 6732 drivers/gpu/drm/i915/intel_pm.c GEN9_FREQUENCY(val)); val 6735 drivers/gpu/drm/i915/intel_pm.c HSW_FREQUENCY(val)); val 6738 drivers/gpu/drm/i915/intel_pm.c GEN6_FREQUENCY(val) | val 6746 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); val 6747 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); val 6749 drivers/gpu/drm/i915/intel_pm.c rps->cur_freq = val; val 6750 drivers/gpu/drm/i915/intel_pm.c trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); val 6755 drivers/gpu/drm/i915/intel_pm.c static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val) val 6759 drivers/gpu/drm/i915/intel_pm.c if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1), val 6761 drivers/gpu/drm/i915/intel_pm.c val &= ~1; val 6763 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); val 6765 drivers/gpu/drm/i915/intel_pm.c if (val != dev_priv->gt_pm.rps.cur_freq) { val 6767 drivers/gpu/drm/i915/intel_pm.c err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); val 6772 drivers/gpu/drm/i915/intel_pm.c gen6_set_rps_thresholds(dev_priv, val); val 6775 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.cur_freq = val; val 6776 drivers/gpu/drm/i915/intel_pm.c trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); val 6791 drivers/gpu/drm/i915/intel_pm.c u32 val = rps->idle_freq; val 6794 drivers/gpu/drm/i915/intel_pm.c if (rps->cur_freq <= val) val 6810 drivers/gpu/drm/i915/intel_pm.c err = valleyview_set_rps(dev_priv, val); val 6904 drivers/gpu/drm/i915/intel_pm.c int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) val 6910 drivers/gpu/drm/i915/intel_pm.c GEM_BUG_ON(val > rps->max_freq); val 6911 drivers/gpu/drm/i915/intel_pm.c GEM_BUG_ON(val < rps->min_freq); val 6914 drivers/gpu/drm/i915/intel_pm.c rps->cur_freq = val; val 6919 drivers/gpu/drm/i915/intel_pm.c err = valleyview_set_rps(dev_priv, val); val 6921 drivers/gpu/drm/i915/intel_pm.c err = gen6_set_rps(dev_priv, val); val 7562 drivers/gpu/drm/i915/intel_pm.c u32 val, rp0; val 7564 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); val 7569 drivers/gpu/drm/i915/intel_pm.c rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); val 7573 drivers/gpu/drm/i915/intel_pm.c rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); val 7579 drivers/gpu/drm/i915/intel_pm.c rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); val 7590 drivers/gpu/drm/i915/intel_pm.c u32 val, rpe; val 7592 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); val 7593 drivers/gpu/drm/i915/intel_pm.c rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; val 7600 drivers/gpu/drm/i915/intel_pm.c u32 val, rp1; val 7602 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); val 7603 drivers/gpu/drm/i915/intel_pm.c rp1 = (val & FB_GFX_FREQ_FUSE_MASK); val 7610 drivers/gpu/drm/i915/intel_pm.c u32 val, rpn; val 7612 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); val 7613 drivers/gpu/drm/i915/intel_pm.c rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & val 7621 drivers/gpu/drm/i915/intel_pm.c u32 val, rp1; val 7623 drivers/gpu/drm/i915/intel_pm.c val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); val 7625 drivers/gpu/drm/i915/intel_pm.c rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; val 7632 drivers/gpu/drm/i915/intel_pm.c u32 val, rp0; val 7634 drivers/gpu/drm/i915/intel_pm.c val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); val 7636 drivers/gpu/drm/i915/intel_pm.c rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; val 7645 drivers/gpu/drm/i915/intel_pm.c u32 val, rpe; val 7647 drivers/gpu/drm/i915/intel_pm.c val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); val 7648 drivers/gpu/drm/i915/intel_pm.c rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; val 7649 drivers/gpu/drm/i915/intel_pm.c val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); val 7650 drivers/gpu/drm/i915/intel_pm.c rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; val 7657 drivers/gpu/drm/i915/intel_pm.c u32 val; val 7659 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; val 7667 drivers/gpu/drm/i915/intel_pm.c return max_t(u32, val, 0xc0); val 7778 drivers/gpu/drm/i915/intel_pm.c u32 val; val 7789 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); val 7790 drivers/gpu/drm/i915/intel_pm.c switch ((val >> 6) & 3) { val 7834 drivers/gpu/drm/i915/intel_pm.c u32 val; val 7845 drivers/gpu/drm/i915/intel_pm.c val = vlv_cck_read(dev_priv, CCK_FUSE_REG); val 7847 drivers/gpu/drm/i915/intel_pm.c switch ((val >> 2) & 0x7) { val 7948 drivers/gpu/drm/i915/intel_pm.c u32 val; val 7972 drivers/gpu/drm/i915/intel_pm.c val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50; val 7973 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); val 7975 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); val 7980 drivers/gpu/drm/i915/intel_pm.c WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); val 7982 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); val 7983 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); val 8035 drivers/gpu/drm/i915/intel_pm.c u32 val; val 8058 drivers/gpu/drm/i915/intel_pm.c val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875; val 8059 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); val 8061 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); val 8066 drivers/gpu/drm/i915/intel_pm.c WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); val 8068 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); val 8069 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); val 8162 drivers/gpu/drm/i915/intel_pm.c unsigned long val = 0; val 8169 drivers/gpu/drm/i915/intel_pm.c val = __i915_chipset_val(dev_priv); val 8173 drivers/gpu/drm/i915/intel_pm.c return val; val 8300 drivers/gpu/drm/i915/intel_pm.c unsigned long val = 0; val 8307 drivers/gpu/drm/i915/intel_pm.c val = __i915_gfx_val(dev_priv); val 8311 drivers/gpu/drm/i915/intel_pm.c return val; val 8512 drivers/gpu/drm/i915/intel_pm.c unsigned long val; val 8514 drivers/gpu/drm/i915/intel_pm.c val = vid * vid; val 8515 drivers/gpu/drm/i915/intel_pm.c val *= (freq / 1000); val 8516 drivers/gpu/drm/i915/intel_pm.c val *= 255; val 8517 drivers/gpu/drm/i915/intel_pm.c val /= (127*127*900); val 8518 drivers/gpu/drm/i915/intel_pm.c if (val > 0xff) val 8519 drivers/gpu/drm/i915/intel_pm.c DRM_ERROR("bad pxval: %ld\n", val); val 8520 drivers/gpu/drm/i915/intel_pm.c pxw[i] = val; val 8527 drivers/gpu/drm/i915/intel_pm.c u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | val 8529 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(PXW(i), val); val 8980 drivers/gpu/drm/i915/intel_pm.c u32 val; val 8996 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(TRANS_CHICKEN2(pipe)); val 8997 drivers/gpu/drm/i915/intel_pm.c val |= TRANS_CHICKEN2_TIMING_OVERRIDE; val 8998 drivers/gpu/drm/i915/intel_pm.c val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; val 9000 drivers/gpu/drm/i915/intel_pm.c val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; val 9001 drivers/gpu/drm/i915/intel_pm.c val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; val 9002 drivers/gpu/drm/i915/intel_pm.c val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; val 9003 drivers/gpu/drm/i915/intel_pm.c val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; val 9004 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(TRANS_CHICKEN2(pipe), val); val 9155 drivers/gpu/drm/i915/intel_pm.c u32 val = I915_READ(SOUTH_DSPCLK_GATE_D); val 9157 drivers/gpu/drm/i915/intel_pm.c val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; val 9158 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(SOUTH_DSPCLK_GATE_D, val); val 9167 drivers/gpu/drm/i915/intel_pm.c u32 val; val 9173 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(GEN8_L3SQCREG1); val 9174 drivers/gpu/drm/i915/intel_pm.c val &= ~L3_PRIO_CREDITS_MASK; val 9175 drivers/gpu/drm/i915/intel_pm.c val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits); val 9176 drivers/gpu/drm/i915/intel_pm.c val |= L3_HIGH_PRIO_CREDITS(high_prio_credits); val 9177 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN8_L3SQCREG1, val); val 9222 drivers/gpu/drm/i915/intel_pm.c u32 val; val 9237 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE); val 9239 drivers/gpu/drm/i915/intel_pm.c val |= RCCUNIT_CLKGATE_DIS; val 9242 drivers/gpu/drm/i915/intel_pm.c val |= SARBUNIT_CLKGATE_DIS; val 9243 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val); val 9246 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE); val 9247 drivers/gpu/drm/i915/intel_pm.c val |= GWUNIT_CLKGATE_DIS; val 9248 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val); val 9252 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE); val 9253 drivers/gpu/drm/i915/intel_pm.c val |= VFUNIT_CLKGATE_DIS; val 9254 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val); val 9856 drivers/gpu/drm/i915/intel_pm.c static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) val 9864 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000); val 9867 drivers/gpu/drm/i915/intel_pm.c static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) val 9871 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7; val 9874 drivers/gpu/drm/i915/intel_pm.c static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) val 9882 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000); val 9885 drivers/gpu/drm/i915/intel_pm.c static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) val 9890 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2; val 9893 drivers/gpu/drm/i915/intel_pm.c int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) val 9896 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, val 9899 drivers/gpu/drm/i915/intel_pm.c return chv_gpu_freq(dev_priv, val); val 9901 drivers/gpu/drm/i915/intel_pm.c return byt_gpu_freq(dev_priv, val); val 9903 drivers/gpu/drm/i915/intel_pm.c return val * GT_FREQUENCY_MULTIPLIER; val 9906 drivers/gpu/drm/i915/intel_pm.c int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) val 9909 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, val 9912 drivers/gpu/drm/i915/intel_pm.c return chv_freq_opcode(dev_priv, val); val 9914 drivers/gpu/drm/i915/intel_pm.c return byt_freq_opcode(dev_priv, val); val 9916 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); val 76 drivers/gpu/drm/i915/intel_pm.h int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); val 77 drivers/gpu/drm/i915/intel_pm.h int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); val 88 drivers/gpu/drm/i915/intel_pm.h bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); val 89 drivers/gpu/drm/i915/intel_pm.h int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); val 94 drivers/gpu/drm/i915/intel_sideband.c u32 addr, u32 *val) val 116 drivers/gpu/drm/i915/intel_sideband.c intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val); val 129 drivers/gpu/drm/i915/intel_sideband.c *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA); val 144 drivers/gpu/drm/i915/intel_sideband.c u32 val = 0; val 147 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, addr, &val); val 149 drivers/gpu/drm/i915/intel_sideband.c return val; val 152 drivers/gpu/drm/i915/intel_sideband.c int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val) val 155 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, addr, &val); val 160 drivers/gpu/drm/i915/intel_sideband.c u32 val = 0; val 163 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, reg, &val); val 165 drivers/gpu/drm/i915/intel_sideband.c return val; val 168 drivers/gpu/drm/i915/intel_sideband.c void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val) val 171 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, reg, &val); val 176 drivers/gpu/drm/i915/intel_sideband.c u32 val = 0; val 179 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, addr, &val); val 181 drivers/gpu/drm/i915/intel_sideband.c return val; val 186 drivers/gpu/drm/i915/intel_sideband.c u32 val = 0; val 189 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, reg, &val); val 191 drivers/gpu/drm/i915/intel_sideband.c return val; val 195 drivers/gpu/drm/i915/intel_sideband.c u8 port, u32 reg, u32 val) val 198 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, reg, &val); val 203 drivers/gpu/drm/i915/intel_sideband.c u32 val = 0; val 206 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, reg, &val); val 208 drivers/gpu/drm/i915/intel_sideband.c return val; val 211 drivers/gpu/drm/i915/intel_sideband.c void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val) val 214 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, reg, &val); val 219 drivers/gpu/drm/i915/intel_sideband.c u32 val = 0; val 222 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, reg, &val); val 224 drivers/gpu/drm/i915/intel_sideband.c return val; val 227 drivers/gpu/drm/i915/intel_sideband.c void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val) val 230 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, reg, &val); val 236 drivers/gpu/drm/i915/intel_sideband.c u32 val = 0; val 238 drivers/gpu/drm/i915/intel_sideband.c vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val); val 244 drivers/gpu/drm/i915/intel_sideband.c WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n", val 245 drivers/gpu/drm/i915/intel_sideband.c pipe_name(pipe), reg, val); val 247 drivers/gpu/drm/i915/intel_sideband.c return val; val 251 drivers/gpu/drm/i915/intel_sideband.c enum pipe pipe, int reg, u32 val) val 255 drivers/gpu/drm/i915/intel_sideband.c vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val); val 260 drivers/gpu/drm/i915/intel_sideband.c u32 val = 0; val 263 drivers/gpu/drm/i915/intel_sideband.c reg, &val); val 264 drivers/gpu/drm/i915/intel_sideband.c return val; val 267 drivers/gpu/drm/i915/intel_sideband.c void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val) val 270 drivers/gpu/drm/i915/intel_sideband.c reg, &val); val 276 drivers/gpu/drm/i915/intel_sideband.c u32 *val, bool is_read) val 291 drivers/gpu/drm/i915/intel_sideband.c intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val); val 314 drivers/gpu/drm/i915/intel_sideband.c *val = intel_uncore_read_fw(uncore, SBI_DATA); val 375 drivers/gpu/drm/i915/intel_sideband.c u32 mbox, u32 *val, u32 *val1, val 393 drivers/gpu/drm/i915/intel_sideband.c intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val); val 407 drivers/gpu/drm/i915/intel_sideband.c *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA); val 418 drivers/gpu/drm/i915/intel_sideband.c u32 *val, u32 *val1) val 423 drivers/gpu/drm/i915/intel_sideband.c err = __sandybridge_pcode_rw(i915, mbox, val, val1, val 437 drivers/gpu/drm/i915/intel_sideband.c u32 mbox, u32 val, val 444 drivers/gpu/drm/i915/intel_sideband.c err = __sandybridge_pcode_rw(i915, mbox, &val, NULL, val 451 drivers/gpu/drm/i915/intel_sideband.c val, mbox, __builtin_return_address(0), err); val 31 drivers/gpu/drm/i915/intel_sideband.h u8 port, u32 reg, u32 val); val 40 drivers/gpu/drm/i915/intel_sideband.h void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val); val 53 drivers/gpu/drm/i915/intel_sideband.h void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val); val 66 drivers/gpu/drm/i915/intel_sideband.h void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val); val 80 drivers/gpu/drm/i915/intel_sideband.h enum pipe pipe, int reg, u32 val); val 93 drivers/gpu/drm/i915/intel_sideband.h void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val); val 118 drivers/gpu/drm/i915/intel_sideband.h int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val); val 131 drivers/gpu/drm/i915/intel_sideband.h u32 *val, u32 *val1); val 133 drivers/gpu/drm/i915/intel_sideband.h u32 val, int fast_timeout_us, val 135 drivers/gpu/drm/i915/intel_sideband.h #define sandybridge_pcode_write(i915, mbox, val) \ val 136 drivers/gpu/drm/i915/intel_sideband.h sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0) val 89 drivers/gpu/drm/i915/intel_uncore.c #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) val 90 drivers/gpu/drm/i915/intel_uncore.c #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) val 313 drivers/gpu/drm/i915/intel_uncore.c u32 val; val 315 drivers/gpu/drm/i915/intel_uncore.c val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); val 316 drivers/gpu/drm/i915/intel_uncore.c val &= GEN6_GT_THREAD_STATUS_CORE_MASK; val 318 drivers/gpu/drm/i915/intel_uncore.c return val; val 1128 drivers/gpu/drm/i915/intel_uncore.c u##x val = 0; \ val 1132 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ val 1133 drivers/gpu/drm/i915/intel_uncore.c return val val 1139 drivers/gpu/drm/i915/intel_uncore.c val = __raw_uncore_read##x(uncore, reg); \ val 1148 drivers/gpu/drm/i915/intel_uncore.c val = __raw_uncore_read##x(uncore, reg); \ val 1170 drivers/gpu/drm/i915/intel_uncore.c u##x val = 0; \ val 1178 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ val 1179 drivers/gpu/drm/i915/intel_uncore.c return val val 1216 drivers/gpu/drm/i915/intel_uncore.c val = __raw_uncore_read##x(uncore, reg); \ val 1240 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ val 1247 drivers/gpu/drm/i915/intel_uncore.c gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ val 1249 drivers/gpu/drm/i915/intel_uncore.c __raw_uncore_write##x(uncore, reg, val); \ val 1255 drivers/gpu/drm/i915/intel_uncore.c gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ val 1258 drivers/gpu/drm/i915/intel_uncore.c __raw_uncore_write##x(uncore, reg, val); \ val 1278 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ val 1289 drivers/gpu/drm/i915/intel_uncore.c gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ val 1293 drivers/gpu/drm/i915/intel_uncore.c __raw_uncore_write##x(uncore, reg, val); \ val 1302 drivers/gpu/drm/i915/intel_uncore.c func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ val 1308 drivers/gpu/drm/i915/intel_uncore.c __raw_uncore_write##x(uncore, reg, val); \ val 1849 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read64_2x32(uncore, val 1853 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read64(uncore, val 1856 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read(uncore, entry->offset_ldw); val 1858 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read16(uncore, val 1861 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read8(uncore, val 95 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, u8 val, bool trace); val 97 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, u16 val, bool trace); val 99 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, u32 val, bool trace); val 269 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u##x__ val) \ val 271 drivers/gpu/drm/i915/intel_uncore.h write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \ val 295 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u##x__ val) \ val 297 drivers/gpu/drm/i915/intel_uncore.h uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \ val 381 drivers/gpu/drm/i915/intel_uncore.h u32 val; val 383 drivers/gpu/drm/i915/intel_uncore.h val = intel_uncore_read(uncore, reg); val 384 drivers/gpu/drm/i915/intel_uncore.h val &= ~clear; val 385 drivers/gpu/drm/i915/intel_uncore.h val |= set; val 386 drivers/gpu/drm/i915/intel_uncore.h intel_uncore_write(uncore, reg, val); val 392 drivers/gpu/drm/i915/intel_uncore.h u32 val; val 394 drivers/gpu/drm/i915/intel_uncore.h val = intel_uncore_read_fw(uncore, reg); val 395 drivers/gpu/drm/i915/intel_uncore.h val &= ~clear; val 396 drivers/gpu/drm/i915/intel_uncore.h val |= set; val 397 drivers/gpu/drm/i915/intel_uncore.h intel_uncore_write_fw(uncore, reg, val); val 401 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u32 val, val 406 drivers/gpu/drm/i915/intel_uncore.h intel_uncore_write(uncore, reg, val); val 1202 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c u32 val; val 1205 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c val = ioread32(vaddr + n); val 1208 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (val != n) { val 1210 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c val, n); val 921 drivers/gpu/drm/i915/selftests/i915_vma.c u32 val = y << 16 | x; val 928 drivers/gpu/drm/i915/selftests/i915_vma.c iowrite32(val, &map[offset / sizeof(*map)]); val 953 drivers/gpu/drm/i915/selftests/i915_vma.c u32 val; val 961 drivers/gpu/drm/i915/selftests/i915_vma.c val = ioread32(&map[offset / sizeof(*map)]); val 962 drivers/gpu/drm/i915/selftests/i915_vma.c if (val != exp) { val 965 drivers/gpu/drm/i915/selftests/i915_vma.c val, exp); val 193 drivers/gpu/drm/i915/selftests/intel_uncore.c u32 val; val 214 drivers/gpu/drm/i915/selftests/intel_uncore.c val = readl(reg); val 233 drivers/gpu/drm/i915/selftests/intel_uncore.c if (!val) { val 29 drivers/gpu/drm/i915/selftests/mock_uncore.c nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { } val 186 drivers/gpu/drm/imx/imx-tve.c unsigned int val; val 207 drivers/gpu/drm/imx/imx-tve.c val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444; val 209 drivers/gpu/drm/imx/imx-tve.c val |= TVE_TV_STAND_HD_1080P30 | 0; val 211 drivers/gpu/drm/imx/imx-tve.c val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; val 212 drivers/gpu/drm/imx/imx-tve.c ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); val 365 drivers/gpu/drm/imx/imx-tve.c unsigned int val; val 367 drivers/gpu/drm/imx/imx-tve.c regmap_read(tve->regmap, TVE_STAT_REG, &val); val 379 drivers/gpu/drm/imx/imx-tve.c unsigned int val; val 382 drivers/gpu/drm/imx/imx-tve.c ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); val 386 drivers/gpu/drm/imx/imx-tve.c switch (val & TVE_DAC_SAMP_RATE_MASK) { val 417 drivers/gpu/drm/imx/imx-tve.c u32 val; val 422 drivers/gpu/drm/imx/imx-tve.c val = TVE_DAC_DIV4_RATE; val 424 drivers/gpu/drm/imx/imx-tve.c val = TVE_DAC_DIV2_RATE; val 426 drivers/gpu/drm/imx/imx-tve.c val = TVE_DAC_FULL_RATE; val 429 drivers/gpu/drm/imx/imx-tve.c TVE_DAC_SAMP_RATE_MASK, val); val 545 drivers/gpu/drm/imx/imx-tve.c unsigned int val; val 642 drivers/gpu/drm/imx/imx-tve.c ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); val 648 drivers/gpu/drm/imx/imx-tve.c if (val != 0x00100000) { val 17 drivers/gpu/drm/lima/lima_mmu.c #define lima_mmu_send_command(cmd, addr, val, cond) \ val 22 drivers/gpu/drm/lima/lima_mmu.c __ret = readl_poll_timeout(ip->iomem + (addr), val, \ val 84 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 97 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + MCDE_CRA0); val 98 drivers/gpu/drm/mcde/mcde_display.c val &= ~MCDE_CRX0_FLOEN; val 99 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + MCDE_CRA0); val 190 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 242 drivers/gpu/drm/mcde/mcde_display.c val = 0 << MCDE_EXTSRCXCONF_BUF_ID_SHIFT; val 243 drivers/gpu/drm/mcde/mcde_display.c val |= 1 << MCDE_EXTSRCXCONF_BUF_NB_SHIFT; val 244 drivers/gpu/drm/mcde/mcde_display.c val |= 0 << MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT; val 251 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 << val 253 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BGR; val 256 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 << val 260 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 << val 262 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BGR; val 265 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 << val 269 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_RGB888 << val 271 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BGR; val 274 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_RGB888 << val 278 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 << val 280 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BGR; val 283 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 << val 287 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_RGB444 << val 289 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BGR; val 292 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_RGB444 << val 296 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 << val 298 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BGR; val 301 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 << val 305 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_RGB565 << val 307 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BGR; val 310 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_RGB565 << val 314 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCONF_BPP_YCBCR422 << val 322 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf); val 325 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL; val 326 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY; val 327 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr); val 338 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 397 drivers/gpu/drm/mcde/mcde_display.c val = mode->hdisplay << MCDE_OVLXCONF_PPL_SHIFT; val 398 drivers/gpu/drm/mcde/mcde_display.c val |= mode->vdisplay << MCDE_OVLXCONF_LPF_SHIFT; val 400 drivers/gpu/drm/mcde/mcde_display.c val |= src << MCDE_OVLXCONF_EXTSRC_ID_SHIFT; val 401 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf1); val 403 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA; val 404 drivers/gpu/drm/mcde/mcde_display.c val |= 0xff << MCDE_OVLXCONF2_ALPHAVALUE_SHIFT; val 422 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_OVLXCONF2_OPQ; val 430 drivers/gpu/drm/mcde/mcde_display.c val |= 48 << MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT; val 431 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf2); val 439 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_OVLXCR_OVLEN; val 440 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_OVLXCR_COLCCTRL_DISABLED; val 441 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_OVLXCR_BURSTSIZE_8W << val 443 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_OVLXCR_MAXOUTSTANDING_8_REQ << val 446 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_OVLXCR_ROTBURSTSIZE_8W << val 448 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr); val 454 drivers/gpu/drm/mcde/mcde_display.c val = ch << MCDE_OVLXCOMP_CH_ID_SHIFT; val 455 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + comp); val 462 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 505 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE val 507 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0 val 514 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE val 516 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER val 519 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + sync); val 522 drivers/gpu/drm/mcde/mcde_display.c val = (mode->hdisplay - 1) << MCDE_CHNLXCONF_PPL_SHIFT; val 523 drivers/gpu/drm/mcde/mcde_display.c val |= (mode->vdisplay - 1) << MCDE_CHNLXCONF_LPF_SHIFT; val 524 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf); val 530 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_CHNLXSTAT_CHNLBLBCKGND_EN | val 532 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + stat); val 552 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 569 drivers/gpu/drm/mcde/mcde_display.c val = fifo_wtrmrk << MCDE_CTRLX_FIFOWTRMRK_SHIFT; val 571 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_CTRLX_FORMTYPE_DSI << val 575 drivers/gpu/drm/mcde/mcde_display.c val |= fmt << MCDE_CTRLX_FORMID_SHIFT; val 576 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + ctrl); val 579 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_CRX0_BLENDEN | val 581 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr0); val 586 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_CRX1_CLKSEL_MCDECLK << MCDE_CRX1_CLKSEL_SHIFT; val 589 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr1); val 597 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 639 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_DSICONF0_CMD8 | MCDE_DSICONF0_DCSVID_NOTGEN; val 641 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_DSICONF0_VID_MODE_VID; val 644 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_DSICONF0_PACKING_RGB888 << val 648 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_DSICONF0_PACKING_RGB666 << val 652 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_DSICONF0_PACKING_RGB666_PACKED << val 656 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_DSICONF0_PACKING_RGB565 << val 663 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf0); val 669 drivers/gpu/drm/mcde/mcde_display.c val = MIPI_DCS_WRITE_MEMORY_CONTINUE << val 671 drivers/gpu/drm/mcde/mcde_display.c val |= MIPI_DCS_WRITE_MEMORY_START << val 673 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cmdw); val 685 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 702 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + cr); val 703 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_CRX0_FLOEN; val 704 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr); val 713 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 730 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + cr); val 731 drivers/gpu/drm/mcde/mcde_display.c val &= ~MCDE_CRX0_FLOEN; val 732 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr); val 757 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 785 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + ctrl); val 786 drivers/gpu/drm/mcde/mcde_display.c if (!(val & MCDE_CTRLX_FIFOEMPTY)) { val 831 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 929 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_VSCRC_VSPOL; val 931 drivers/gpu/drm/mcde/mcde_display.c val = 0; val 932 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + MCDE_VSCRC0); val 934 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + MCDE_CRC); val 935 drivers/gpu/drm/mcde/mcde_display.c val |= MCDE_CRC_SYCEN0; val 936 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + MCDE_CRC); val 1069 drivers/gpu/drm/mcde/mcde_display.c u32 val; val 1072 drivers/gpu/drm/mcde/mcde_display.c val = MCDE_PP_VCMPA | val 1078 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + MCDE_IMSCPP); val 149 drivers/gpu/drm/mcde/mcde_drv.c u32 val; val 151 drivers/gpu/drm/mcde/mcde_drv.c val = readl(mcde->regs + MCDE_MISERR); val 155 drivers/gpu/drm/mcde/mcde_drv.c if (val) val 157 drivers/gpu/drm/mcde/mcde_drv.c writel(val, mcde->regs + MCDE_RISERR); val 323 drivers/gpu/drm/mcde/mcde_drv.c u32 val; val 446 drivers/gpu/drm/mcde/mcde_drv.c val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT; val 448 drivers/gpu/drm/mcde/mcde_drv.c val |= 3 << MCDE_CONF0_OUTMUX0_SHIFT; val 450 drivers/gpu/drm/mcde/mcde_drv.c val |= 3 << MCDE_CONF0_OUTMUX1_SHIFT; val 452 drivers/gpu/drm/mcde/mcde_drv.c val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT; val 454 drivers/gpu/drm/mcde/mcde_drv.c val |= 4 << MCDE_CONF0_OUTMUX3_SHIFT; val 456 drivers/gpu/drm/mcde/mcde_drv.c val |= 5 << MCDE_CONF0_OUTMUX4_SHIFT; val 458 drivers/gpu/drm/mcde/mcde_drv.c writel(val, mcde->regs + MCDE_CONF0); val 461 drivers/gpu/drm/mcde/mcde_drv.c val = readl(mcde->regs + MCDE_CR); val 462 drivers/gpu/drm/mcde/mcde_drv.c val |= MCDE_CR_MCDEEN | MCDE_CR_AUTOCLKG_EN; val 463 drivers/gpu/drm/mcde/mcde_drv.c writel(val, mcde->regs + MCDE_CR); val 75 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 82 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); val 83 drivers/gpu/drm/mcde/mcde_dsi.c if (val) val 84 drivers/gpu/drm/mcde/mcde_dsi.c dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); val 85 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED) val 87 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) { val 91 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) val 93 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) val 96 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR); val 98 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_CMD_MODE_STS_FLAG); val 99 drivers/gpu/drm/mcde/mcde_dsi.c if (val) val 100 drivers/gpu/drm/mcde/mcde_dsi.c dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val); val 101 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_CMD_MODE_STS_ERR_NO_TE) val 104 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_CMD_MODE_STS_ERR_TE_MISS) val 107 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN) val 109 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN) val 111 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD) val 113 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_CMD_MODE_STS_CLR); val 115 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG); val 116 drivers/gpu/drm/mcde/mcde_dsi.c if (val) val 117 drivers/gpu/drm/mcde/mcde_dsi.c dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val); val 118 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR); val 120 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_TG_STS_FLAG); val 121 drivers/gpu/drm/mcde/mcde_dsi.c if (val) val 122 drivers/gpu/drm/mcde/mcde_dsi.c dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val); val 123 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_TG_STS_CLR); val 125 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_VID_MODE_STS_FLAG); val 126 drivers/gpu/drm/mcde/mcde_dsi.c if (val) val 128 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_MODE_STS_CLR); val 183 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 205 drivers/gpu/drm/mcde/mcde_dsi.c val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ; val 207 drivers/gpu/drm/mcde/mcde_dsi.c val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE; val 215 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT; val 216 drivers/gpu/drm/mcde/mcde_dsi.c val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; val 217 drivers/gpu/drm/mcde/mcde_dsi.c val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; val 218 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; val 219 drivers/gpu/drm/mcde/mcde_dsi.c val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; val 220 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); val 224 drivers/gpu/drm/mcde/mcde_dsi.c val = 0; val 226 drivers/gpu/drm/mcde/mcde_dsi.c val |= tx[i] << (i & 3) * 8; val 228 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0); val 230 drivers/gpu/drm/mcde/mcde_dsi.c val = 0; val 232 drivers/gpu/drm/mcde/mcde_dsi.c val |= tx[i + 4] << (i & 3) * 8; val 233 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1); val 236 drivers/gpu/drm/mcde/mcde_dsi.c val = 0; val 238 drivers/gpu/drm/mcde/mcde_dsi.c val |= tx[i + 8] << (i & 3) * 8; val 239 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2); val 242 drivers/gpu/drm/mcde/mcde_dsi.c val = 0; val 244 drivers/gpu/drm/mcde/mcde_dsi.c val |= tx[i + 12] << (i & 3) * 8; val 245 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3); val 278 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_DIRECT_CMD_STS); val 279 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) { val 284 drivers/gpu/drm/mcde/mcde_dsi.c if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) { val 285 drivers/gpu/drm/mcde/mcde_dsi.c val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT; val 287 drivers/gpu/drm/mcde/mcde_dsi.c val); val 330 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 335 drivers/gpu/drm/mcde/mcde_dsi.c val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ; val 336 drivers/gpu/drm/mcde/mcde_dsi.c val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; val 337 drivers/gpu/drm/mcde/mcde_dsi.c val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; val 338 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; val 339 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_1 << val 341 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); val 347 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL); val 348 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN; val 349 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN; val 350 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL); val 356 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_CMD_MODE_STS_CTL); val 357 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN; val 358 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN; val 359 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_CMD_MODE_STS_CTL); val 375 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 377 drivers/gpu/drm/mcde/mcde_dsi.c val = 0; val 379 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_BURST_MODE; val 381 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE; val 382 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL; val 387 drivers/gpu/drm/mcde/mcde_dsi.c val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 << val 389 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS; val 392 drivers/gpu/drm/mcde/mcde_dsi.c val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 << val 394 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS; val 397 drivers/gpu/drm/mcde/mcde_dsi.c val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18 val 399 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE; val 402 drivers/gpu/drm/mcde/mcde_dsi.c val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 << val 404 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS; val 414 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0; val 416 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0; val 418 drivers/gpu/drm/mcde/mcde_dsi.c val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT; val 420 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_MAIN_CTL); val 423 drivers/gpu/drm/mcde/mcde_dsi.c val = mode->vdisplay << DSI_VID_VSIZE_VSA_LENGTH_SHIFT; val 425 drivers/gpu/drm/mcde/mcde_dsi.c val |= (mode->vsync_start - mode->vdisplay) val 428 drivers/gpu/drm/mcde/mcde_dsi.c val |= (mode->vsync_end - mode->vsync_start) val 431 drivers/gpu/drm/mcde/mcde_dsi.c val |= (mode->vtotal - mode->vsync_end) val 433 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_VSIZE); val 470 drivers/gpu/drm/mcde/mcde_dsi.c val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT; val 472 drivers/gpu/drm/mcde/mcde_dsi.c val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT; val 474 drivers/gpu/drm/mcde/mcde_dsi.c val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT; val 475 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_HSIZE1); val 478 drivers/gpu/drm/mcde/mcde_dsi.c val = mode->hdisplay * (bpp / 8); val 479 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_HSIZE2); val 501 drivers/gpu/drm/mcde/mcde_dsi.c val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT; val 502 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_BLKSIZE2); val 505 drivers/gpu/drm/mcde/mcde_dsi.c val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT; val 506 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_BLKSIZE1); val 511 drivers/gpu/drm/mcde/mcde_dsi.c val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT; val 516 drivers/gpu/drm/mcde/mcde_dsi.c val |= 0 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT; val 517 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_DPHY_TIME); val 527 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_VID_BLKSIZE1); val 528 drivers/gpu/drm/mcde/mcde_dsi.c val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT; val 529 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_BLKSIZE1); val 537 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_VID_VCA_SETTING2); val 538 drivers/gpu/drm/mcde/mcde_dsi.c val |= blkline_pck << val 540 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_VCA_SETTING2); val 543 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); val 544 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE; val 545 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); val 548 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_CMD_MODE_CTL); val 549 drivers/gpu/drm/mcde/mcde_dsi.c val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN; val 550 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_CMD_MODE_CTL); val 553 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_VID_MODE_STS_CTL); val 554 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC; val 555 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA; val 556 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_VID_MODE_STS_CTL); val 559 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); val 560 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; val 561 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); val 567 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 574 drivers/gpu/drm/mcde/mcde_dsi.c val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN | val 579 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN; val 580 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); val 583 drivers/gpu/drm/mcde/mcde_dsi.c val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT; val 584 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_CMD_MODE_CTL); val 593 drivers/gpu/drm/mcde/mcde_dsi.c val = 4000 / hs_freq; val 594 drivers/gpu/drm/mcde/mcde_dsi.c dev_dbg(d->dev, "UI value: %d\n", val); val 595 drivers/gpu/drm/mcde/mcde_dsi.c val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT; val 596 drivers/gpu/drm/mcde/mcde_dsi.c val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK; val 597 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_DPHY_STATIC); val 605 drivers/gpu/drm/mcde/mcde_dsi.c val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT; val 607 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN; val 609 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS; val 610 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN | val 613 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL); val 615 drivers/gpu/drm/mcde/mcde_dsi.c val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) | val 617 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_ULPOUT_TIME); val 623 drivers/gpu/drm/mcde/mcde_dsi.c val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) | val 626 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT); val 628 drivers/gpu/drm/mcde/mcde_dsi.c val = DSI_MCTL_MAIN_EN_PLL_START | val 633 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_MCTL_MAIN_EN_DAT2_EN; val 634 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_MAIN_EN); val 638 drivers/gpu/drm/mcde/mcde_dsi.c val = DSI_MCTL_MAIN_STS_PLL_LOCK | val 642 drivers/gpu/drm/mcde/mcde_dsi.c val |= DSI_MCTL_MAIN_STS_DAT2_READY; val 643 drivers/gpu/drm/mcde/mcde_dsi.c while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) { val 655 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_CMD_MODE_CTL); val 661 drivers/gpu/drm/mcde/mcde_dsi.c val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; val 662 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_CMD_MODE_CTL); val 684 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 738 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_CMD_MODE_CTL); val 744 drivers/gpu/drm/mcde/mcde_dsi.c val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; val 745 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_CMD_MODE_CTL); val 751 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 759 drivers/gpu/drm/mcde/mcde_dsi.c val = DSI_CMD_MODE_STS_CSM_RUNNING; val 760 drivers/gpu/drm/mcde/mcde_dsi.c while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) { val 773 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 778 drivers/gpu/drm/mcde/mcde_dsi.c val = DSI_VID_MODE_STS_VSG_RUNNING; val 779 drivers/gpu/drm/mcde/mcde_dsi.c while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) { val 793 drivers/gpu/drm/mcde/mcde_dsi.c u32 val; val 800 drivers/gpu/drm/mcde/mcde_dsi.c val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); val 801 drivers/gpu/drm/mcde/mcde_dsi.c val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN; val 802 drivers/gpu/drm/mcde/mcde_dsi.c writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); val 82 drivers/gpu/drm/mediatek/mtk_cec.c unsigned int val, unsigned int mask) val 86 drivers/gpu/drm/mediatek/mtk_cec.c tmp |= val & mask; val 87 drivers/gpu/drm/mediatek/mtk_cec.c writel(val, cec->regs + offset); val 89 drivers/gpu/drm/mediatek/mtk_disp_rdma.c unsigned int mask, unsigned int val) val 93 drivers/gpu/drm/mediatek/mtk_disp_rdma.c tmp = (tmp & ~mask) | (val & mask); val 116 drivers/gpu/drm/mediatek/mtk_dpi.c static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) val 120 drivers/gpu/drm/mediatek/mtk_dpi.c tmp |= (val & mask); val 240 drivers/gpu/drm/mediatek/mtk_dpi.c u32 val; val 244 drivers/gpu/drm/mediatek/mtk_dpi.c val = OUT_BIT_8; val 247 drivers/gpu/drm/mediatek/mtk_dpi.c val = OUT_BIT_10; val 250 drivers/gpu/drm/mediatek/mtk_dpi.c val = OUT_BIT_12; val 253 drivers/gpu/drm/mediatek/mtk_dpi.c val = OUT_BIT_16; val 256 drivers/gpu/drm/mediatek/mtk_dpi.c val = OUT_BIT_8; val 259 drivers/gpu/drm/mediatek/mtk_dpi.c mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT, val 266 drivers/gpu/drm/mediatek/mtk_dpi.c u32 val; val 270 drivers/gpu/drm/mediatek/mtk_dpi.c val = YC_MAP_RGB; val 273 drivers/gpu/drm/mediatek/mtk_dpi.c val = YC_MAP_CYCY; val 276 drivers/gpu/drm/mediatek/mtk_dpi.c val = YC_MAP_YCYC; val 279 drivers/gpu/drm/mediatek/mtk_dpi.c val = YC_MAP_CY; val 282 drivers/gpu/drm/mediatek/mtk_dpi.c val = YC_MAP_YC; val 285 drivers/gpu/drm/mediatek/mtk_dpi.c val = YC_MAP_RGB; val 289 drivers/gpu/drm/mediatek/mtk_dpi.c mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); val 295 drivers/gpu/drm/mediatek/mtk_dpi.c u32 val; val 299 drivers/gpu/drm/mediatek/mtk_dpi.c val = SWAP_RGB; val 302 drivers/gpu/drm/mediatek/mtk_dpi.c val = SWAP_GBR; val 305 drivers/gpu/drm/mediatek/mtk_dpi.c val = SWAP_BRG; val 308 drivers/gpu/drm/mediatek/mtk_dpi.c val = SWAP_RBG; val 311 drivers/gpu/drm/mediatek/mtk_dpi.c val = SWAP_GRB; val 314 drivers/gpu/drm/mediatek/mtk_dpi.c val = SWAP_BGR; val 317 drivers/gpu/drm/mediatek/mtk_dpi.c val = SWAP_RGB; val 321 drivers/gpu/drm/mediatek/mtk_dpi.c mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); val 901 drivers/gpu/drm/mediatek/mtk_dsi.c u32 val; val 903 drivers/gpu/drm/mediatek/mtk_dsi.c ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY), val 188 drivers/gpu/drm/mediatek/mtk_hdmi.c static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) val 190 drivers/gpu/drm/mediatek/mtk_hdmi.c writel(val, hdmi->regs + offset); val 213 drivers/gpu/drm/mediatek/mtk_hdmi.c static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) val 219 drivers/gpu/drm/mediatek/mtk_hdmi.c tmp = (tmp & ~mask) | (val & mask); val 451 drivers/gpu/drm/mediatek/mtk_hdmi.c u32 val; val 455 drivers/gpu/drm/mediatek/mtk_hdmi.c val = AOUT_16BIT; val 458 drivers/gpu/drm/mediatek/mtk_hdmi.c val = AOUT_20BIT; val 462 drivers/gpu/drm/mediatek/mtk_hdmi.c val = AOUT_24BIT; val 466 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK); val 472 drivers/gpu/drm/mediatek/mtk_hdmi.c u32 val; val 474 drivers/gpu/drm/mediatek/mtk_hdmi.c val = mtk_hdmi_read(hdmi, GRL_CFG0); val 475 drivers/gpu/drm/mediatek/mtk_hdmi.c val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); val 479 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; val 482 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; val 486 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; val 489 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; val 492 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; val 495 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; val 498 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_write(hdmi, GRL_CFG0, val); val 504 drivers/gpu/drm/mediatek/mtk_hdmi.c u8 val; val 510 drivers/gpu/drm/mediatek/mtk_hdmi.c val = DST_NORMAL_DOUBLE | SACD_DST; val 512 drivers/gpu/drm/mediatek/mtk_hdmi.c val = 0; val 514 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); val 564 drivers/gpu/drm/mediatek/mtk_hdmi.c u32 val; val 566 drivers/gpu/drm/mediatek/mtk_hdmi.c val = mtk_hdmi_read(hdmi, GRL_CFG1); val 568 drivers/gpu/drm/mediatek/mtk_hdmi.c (val & CFG1_SPDIF) == CFG1_SPDIF) { val 569 drivers/gpu/drm/mediatek/mtk_hdmi.c val &= ~CFG1_SPDIF; val 571 drivers/gpu/drm/mediatek/mtk_hdmi.c (val & CFG1_SPDIF) == 0) { val 572 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG1_SPDIF; val 574 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_write(hdmi, GRL_CFG1, val); val 595 drivers/gpu/drm/mediatek/mtk_hdmi.c u32 val; val 597 drivers/gpu/drm/mediatek/mtk_hdmi.c val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); val 598 drivers/gpu/drm/mediatek/mtk_hdmi.c if (val & MIX_CTRL_SRC_EN) { val 599 drivers/gpu/drm/mediatek/mtk_hdmi.c val &= ~MIX_CTRL_SRC_EN; val 600 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); val 602 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= MIX_CTRL_SRC_EN; val 603 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); val 609 drivers/gpu/drm/mediatek/mtk_hdmi.c u32 val; val 611 drivers/gpu/drm/mediatek/mtk_hdmi.c val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); val 612 drivers/gpu/drm/mediatek/mtk_hdmi.c val &= ~MIX_CTRL_SRC_EN; val 613 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); val 620 drivers/gpu/drm/mediatek/mtk_hdmi.c u32 val; val 622 drivers/gpu/drm/mediatek/mtk_hdmi.c val = mtk_hdmi_read(hdmi, GRL_CFG5); val 623 drivers/gpu/drm/mediatek/mtk_hdmi.c val &= CFG5_CD_RATIO_MASK; val 627 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG5_FS128; val 630 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG5_FS256; val 633 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG5_FS384; val 636 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG5_FS512; val 639 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG5_FS768; val 642 drivers/gpu/drm/mediatek/mtk_hdmi.c val |= CFG5_FS256; val 645 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_write(hdmi, GRL_CFG5, val); val 726 drivers/gpu/drm/mediatek/mtk_hdmi.c unsigned char val[NCTS_BYTES]; val 732 drivers/gpu/drm/mediatek/mtk_hdmi.c memset(val, 0, sizeof(val)); val 734 drivers/gpu/drm/mediatek/mtk_hdmi.c val[0] = (cts >> 24) & 0xff; val 735 drivers/gpu/drm/mediatek/mtk_hdmi.c val[1] = (cts >> 16) & 0xff; val 736 drivers/gpu/drm/mediatek/mtk_hdmi.c val[2] = (cts >> 8) & 0xff; val 737 drivers/gpu/drm/mediatek/mtk_hdmi.c val[3] = cts & 0xff; val 739 drivers/gpu/drm/mediatek/mtk_hdmi.c val[4] = (n >> 16) & 0xff; val 740 drivers/gpu/drm/mediatek/mtk_hdmi.c val[5] = (n >> 8) & 0xff; val 741 drivers/gpu/drm/mediatek/mtk_hdmi.c val[6] = n & 0xff; val 744 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_write(hdmi, GRL_NCTS, val[i]); val 63 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c unsigned int val) val 65 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c writel(readl(ddc->regs + offset) | val, ddc->regs + offset); val 69 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c unsigned int val) val 71 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); val 75 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c unsigned int val) val 77 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c return (readl(ddc->regs + offset) & val) == val; val 82 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c unsigned int val) val 88 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c tmp |= (val << shift) & mask; val 101 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c u32 val; val 106 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val, val 107 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c (val & DDCM_TRI) != DDCM_TRI, 4, 20000); val 41 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c u32 val, u32 mask) val 47 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c tmp = (tmp & ~mask) | (val & mask); val 50 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h u32 val, u32 mask); val 166 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c unsigned long out_rate, val; val 168 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c val = (readl(hdmi_phy->regs + HDMI_CON6) val 170 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c switch (val) { val 182 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c val = (readl(hdmi_phy->regs + HDMI_CON6) val 184 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c out_rate *= (val + 1) * 2; val 185 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c val = (readl(hdmi_phy->regs + HDMI_CON2) val 187 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c out_rate >>= (val >> RG_HDMITX_TX_POSDIV); val 217 drivers/gpu/drm/meson/meson_dw_hdmi.c unsigned int val) val 222 drivers/gpu/drm/meson/meson_dw_hdmi.c data |= val; val 281 drivers/gpu/drm/meson/meson_dw_hdmi.c unsigned int val) val 286 drivers/gpu/drm/meson/meson_dw_hdmi.c data |= val; val 751 drivers/gpu/drm/meson/meson_dw_hdmi.c unsigned int val) val 755 drivers/gpu/drm/meson/meson_dw_hdmi.c dw_hdmi->data->dwc_write(dw_hdmi, reg, val); val 29 drivers/gpu/drm/meson/meson_overlay.c #define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val) val 14 drivers/gpu/drm/meson/meson_registers.h #define writel_bits_relaxed(mask, val, addr) \ val 15 drivers/gpu/drm/meson/meson_registers.h writel_relaxed((readl_relaxed(addr) & ~(mask)) | ((val) & (mask)), addr) val 245 drivers/gpu/drm/meson/meson_registers.h #define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12) val 892 drivers/gpu/drm/meson/meson_registers.h #define ENCI_VIDEO_MODE_ADV_DMXMD(val) (val & 0x3) val 968 drivers/gpu/drm/meson/meson_registers.h #define ENCI_MACV_MAX_AMP_VAL(val) (val & 0x83ff) val 1008 drivers/gpu/drm/meson/meson_registers.h #define ENCI_VFIFO2VD_CTL_VD_SEL(val) ((val & 0xff) << 8) val 1678 drivers/gpu/drm/meson/meson_registers.h #define DOLBY_BYPASS_EN(val) (val & 0xf) val 242 drivers/gpu/drm/meson/meson_vclk.c unsigned int val; val 255 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, val 256 drivers/gpu/drm/meson/meson_vclk.c (val & HDMI_PLL_LOCK), 10, 0); val 273 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, val 274 drivers/gpu/drm/meson/meson_vclk.c (val & HDMI_PLL_LOCK), 10, 0); val 287 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, val 288 drivers/gpu/drm/meson/meson_vclk.c ((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A), val 456 drivers/gpu/drm/meson/meson_vclk.c unsigned int val; val 477 drivers/gpu/drm/meson/meson_vclk.c val, (val & HDMI_PLL_LOCK), 10, 0); val 494 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, val 495 drivers/gpu/drm/meson/meson_vclk.c (val & HDMI_PLL_LOCK), 10, 0); val 540 drivers/gpu/drm/meson/meson_vclk.c HHI_HDMI_PLL_CNTL, val, val 541 drivers/gpu/drm/meson/meson_vclk.c ((val & HDMI_PLL_LOCK_G12A) val 340 drivers/gpu/drm/meson/meson_viu.c uint32_t val = (((length & 0x80) % 24) / 12); val 342 drivers/gpu/drm/meson/meson_viu.c return (((val & 0x3) << 10) | (((val & 0x4) >> 2) << 31)); val 219 drivers/gpu/drm/mga/mga_drv.h #define MGA_WRITE8(reg, val) \ val 220 drivers/gpu/drm/mga/mga_drv.h writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) val 221 drivers/gpu/drm/mga/mga_drv.h #define MGA_WRITE(reg, val) \ val 222 drivers/gpu/drm/mga/mga_drv.h writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) val 332 drivers/gpu/drm/mga/mga_drv.h #define DMA_WRITE(offset, val) \ val 336 drivers/gpu/drm/mga/mga_drv.h (u32)(val), write + (offset) * sizeof(u32)); \ val 337 drivers/gpu/drm/mga/mga_drv.h *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ val 43 drivers/gpu/drm/mgag200/mgag200_i2c.c static void mga_i2c_set_gpio(struct mga_device *mdev, int mask, int val) val 48 drivers/gpu/drm/mgag200/mgag200_i2c.c tmp = (RREG8(DAC_DATA) & mask) | val; val 316 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 318 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; val 322 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 324 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; val 328 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 330 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; val 334 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 336 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; val 340 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 342 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; val 346 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 348 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; val 352 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 354 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; val 358 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 360 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; val 364 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 366 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; val 370 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 372 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; val 376 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) val 378 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; val 384 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) val 386 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; val 390 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) val 392 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; val 491 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) val 493 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; val 518 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) val 520 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; val 528 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) val 530 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; val 537 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) val 539 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; val 563 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) val 565 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; val 569 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) val 571 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; val 599 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) val 601 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; val 608 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) val 610 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; val 614 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) val 616 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; val 624 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) val 626 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; val 630 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) val 632 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; val 692 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) val 694 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; val 703 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) val 705 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; val 713 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) val 715 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; val 720 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) val 722 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; val 726 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) val 728 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; val 743 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) val 745 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; val 749 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) val 751 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; val 757 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) val 759 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; val 763 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) val 765 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; val 770 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) val 772 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; val 776 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) val 778 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; val 782 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) val 784 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; val 790 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) val 792 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; val 796 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) val 798 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; val 809 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) val 811 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; val 815 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) val 817 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; val 824 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) val 826 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; val 830 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) val 832 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; val 838 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) val 840 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; val 844 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) val 846 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; val 854 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) val 856 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; val 860 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) val 862 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; val 869 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) val 871 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; val 875 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) val 877 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; val 907 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) val 909 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; val 913 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) val 915 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; val 919 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) val 921 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; val 927 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) val 929 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; val 933 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) val 935 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; val 939 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) val 941 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; val 947 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) val 949 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; val 953 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) val 955 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; val 959 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) val 961 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; val 969 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) val 971 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; val 977 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) val 979 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; val 985 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) val 987 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; val 993 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) val 995 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; val 1001 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) val 1003 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; val 1009 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) val 1011 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; val 1017 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) val 1019 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; val 1023 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) val 1025 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; val 1033 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) val 1035 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; val 1039 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) val 1041 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; val 1045 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) val 1047 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; val 1056 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) val 1058 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; val 1062 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) val 1064 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; val 1073 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) val 1075 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; val 1079 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) val 1081 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; val 1087 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) val 1089 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; val 1093 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) val 1095 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; val 1099 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) val 1101 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; val 1105 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) val 1107 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; val 1111 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) val 1113 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; val 1117 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) val 1119 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; val 1123 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) val 1125 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; val 1129 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) val 1131 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; val 1137 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) val 1139 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; val 1143 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) val 1145 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; val 1149 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) val 1151 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; val 1155 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) val 1157 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; val 1161 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) val 1163 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; val 1167 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) val 1169 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; val 1173 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) val 1175 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; val 1179 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) val 1181 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; val 1187 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) val 1189 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; val 1193 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) val 1195 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; val 1201 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) val 1203 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; val 1207 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) val 1209 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; val 1217 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) val 1219 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; val 1223 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) val 1225 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; val 1229 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) val 1231 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; val 1235 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) val 1237 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; val 1244 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) val 1246 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; val 1258 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) val 1260 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; val 1265 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) val 1267 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; val 1271 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) val 1273 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; val 1277 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) val 1279 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; val 1283 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) val 1285 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; val 1289 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) val 1291 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; val 1295 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) val 1297 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; val 1301 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) val 1303 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; val 1307 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) val 1309 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; val 1315 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) val 1317 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; val 1321 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) val 1323 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; val 1327 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) val 1329 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; val 1333 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) val 1335 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; val 1339 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) val 1341 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; val 1345 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) val 1347 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; val 1355 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) val 1357 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; val 1366 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) val 1368 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; val 1372 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) val 1374 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; val 1378 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) val 1380 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; val 1385 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) val 1387 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; val 1391 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) val 1393 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; val 1397 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) val 1399 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; val 1403 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) val 1405 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; val 1411 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) val 1413 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; val 1417 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) val 1419 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; val 1423 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) val 1425 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; val 1433 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) val 1435 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; val 1449 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) val 1451 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; val 1455 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) val 1457 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; val 1461 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) val 1463 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; val 1497 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) val 1499 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; val 1503 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) val 1505 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; val 1509 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) val 1511 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; val 1517 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) val 1519 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; val 1529 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) val 1531 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; val 1535 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) val 1537 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; val 1541 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) val 1543 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; val 1547 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) val 1549 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; val 1557 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) val 1559 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; val 1563 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) val 1565 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; val 1571 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) val 1573 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; val 1577 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) val 1579 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; val 1585 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) val 1587 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; val 1593 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) val 1595 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; val 1599 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) val 1601 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; val 1605 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) val 1607 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; val 1611 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) val 1613 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; val 1620 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) val 1622 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; val 1631 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) val 1633 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; val 1642 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) val 1644 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; val 1648 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) val 1650 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; val 1656 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) val 1658 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; val 1662 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) val 1664 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; val 1668 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) val 1670 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; val 1676 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) val 1678 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; val 1684 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) val 1686 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; val 1692 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) val 1694 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; val 1700 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) val 1702 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; val 1708 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) val 1710 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; val 1714 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) val 1716 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; val 1722 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) val 1724 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; val 1728 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) val 1730 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; val 1742 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) val 1744 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; val 1750 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) val 1752 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; val 1758 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) val 1760 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; val 1765 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) val 1767 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; val 1775 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) val 1777 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; val 1783 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) val 1785 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; val 1790 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) val 1792 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; val 1796 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) val 1798 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; val 1802 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) val 1804 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; val 1808 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) val 1810 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; val 1820 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) val 1822 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; val 1826 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) val 1828 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; val 1864 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) val 1866 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; val 1870 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) val 1872 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; val 1876 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) val 1878 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; val 1882 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) val 1884 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; val 1888 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) val 1890 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; val 1894 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) val 1896 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; val 1900 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) val 1902 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; val 1906 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) val 1908 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; val 1912 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) val 1914 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; val 1921 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) val 1923 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; val 1927 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) val 1929 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; val 1933 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) val 1935 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; val 1940 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) val 1942 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; val 1946 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) val 1948 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; val 1954 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) val 1956 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; val 1960 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) val 1962 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; val 1966 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) val 1968 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; val 1974 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) val 1976 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; val 1980 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) val 1982 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; val 1986 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) val 1988 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; val 1992 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) val 1994 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; val 1998 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) val 2000 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; val 2004 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val) val 2006 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; val 2010 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) val 2012 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; val 2016 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) val 2018 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; val 2022 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) val 2024 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; val 2028 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) val 2030 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; val 2034 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) val 2036 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; val 2042 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) val 2044 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; val 2048 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) val 2050 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; val 2054 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) val 2056 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; val 2060 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) val 2062 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; val 2068 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) val 2070 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; val 2074 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) val 2076 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; val 2080 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) val 2082 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; val 2088 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) val 2090 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; val 2095 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) val 2097 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; val 2101 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) val 2103 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; val 2107 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) val 2109 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; val 2114 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) val 2116 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; val 946 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) val 948 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; val 954 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) val 956 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; val 960 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) val 962 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; val 968 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) val 970 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; val 976 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) val 978 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; val 984 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) val 986 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; val 992 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) val 994 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; val 1000 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) val 1002 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; val 1008 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) val 1010 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; val 1016 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) val 1018 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; val 1022 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) val 1024 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; val 1030 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) val 1032 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; val 1038 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) val 1040 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; val 1046 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) val 1048 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; val 1057 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) val 1059 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; val 1066 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) val 1068 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; val 1072 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) val 1074 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; val 1078 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) val 1080 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; val 1087 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) val 1089 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; val 1093 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) val 1095 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; val 1102 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) val 1104 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; val 1108 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) val 1110 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; val 1117 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) val 1119 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; val 1123 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) val 1125 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; val 1132 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) val 1134 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; val 1138 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) val 1140 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; val 1147 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) val 1149 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; val 1153 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) val 1155 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK; val 1167 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) val 1169 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; val 1182 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) val 1184 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; val 1193 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) val 1195 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; val 1199 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) val 1201 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; val 1207 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) val 1209 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; val 1213 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) val 1215 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; val 1226 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) val 1228 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; val 1232 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) val 1234 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; val 1238 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) val 1240 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; val 1246 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) val 1248 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; val 1252 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) val 1254 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; val 1258 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 1260 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; val 1265 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) val 1267 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; val 1273 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) val 1275 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; val 1281 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) val 1283 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; val 1287 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) val 1289 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; val 1293 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) val 1295 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; val 1299 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) val 1301 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; val 1305 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) val 1307 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; val 1311 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) val 1313 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; val 1320 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) val 1322 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; val 1326 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) val 1328 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; val 1334 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) val 1336 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; val 1340 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) val 1342 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; val 1348 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) val 1350 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; val 1354 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) val 1356 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; val 1362 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) val 1364 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; val 1368 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) val 1370 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; val 1384 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) val 1386 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; val 1391 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) val 1393 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; val 1398 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) val 1400 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; val 1405 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) val 1407 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; val 1413 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) val 1415 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; val 1421 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) val 1423 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; val 1429 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) val 1431 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; val 1435 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) val 1437 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; val 1441 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) val 1443 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; val 1447 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) val 1449 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; val 1453 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) val 1455 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; val 1459 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) val 1461 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; val 1471 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) val 1473 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; val 1483 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) val 1485 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; val 1489 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) val 1491 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; val 1497 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) val 1499 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; val 1508 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) val 1510 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; val 1514 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) val 1516 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; val 1520 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) val 1522 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; val 1526 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) val 1528 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; val 1532 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) val 1534 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; val 1538 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) val 1540 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; val 1544 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) val 1546 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; val 1550 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) val 1552 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; val 1560 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) val 1562 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; val 1568 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) val 1570 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; val 1576 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) val 1578 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; val 1582 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) val 1584 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; val 1588 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) val 1590 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; val 1596 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) val 1598 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; val 1602 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) val 1604 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; val 1608 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) val 1610 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; val 1619 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) val 1621 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; val 1625 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) val 1627 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; val 1647 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) val 1649 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; val 1653 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) val 1655 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; val 1663 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) val 1665 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; val 1669 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) val 1671 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; val 1675 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) val 1677 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; val 1689 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) val 1691 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; val 1699 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) val 1701 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK; val 1707 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) val 1709 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; val 1719 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) val 1721 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; val 1726 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) val 1728 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK; val 1732 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) val 1734 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK; val 1740 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) val 1742 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK; val 1746 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) val 1748 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK; val 1752 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) val 1754 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; val 1760 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) val 1762 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; val 1768 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) val 1770 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; val 1774 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) val 1776 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; val 1780 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) val 1782 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; val 1788 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) val 1790 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; val 1794 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) val 1796 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; val 1800 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) val 1802 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; val 1808 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) val 1810 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; val 1814 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) val 1816 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; val 1822 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) val 1824 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; val 1828 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) val 1830 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; val 1836 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) val 1838 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; val 1842 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) val 1844 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; val 1848 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) val 1850 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; val 1854 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) val 1856 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; val 1884 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) val 1886 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; val 1890 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) val 1892 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; val 1896 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) val 1898 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; val 1902 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) val 1904 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; val 1910 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) val 1912 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; val 1916 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) val 1918 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK; val 1922 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) val 1924 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK; val 1928 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) val 1930 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; val 1934 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) val 1936 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; val 1954 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) val 1956 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; val 1960 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) val 1962 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; val 1968 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) val 1970 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; val 1974 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) val 1976 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; val 1986 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) val 1988 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; val 1993 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) val 1995 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; val 1999 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) val 2001 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; val 2006 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) val 2008 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; val 2012 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) val 2014 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; val 2022 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) val 2024 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; val 2028 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) val 2030 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; val 2036 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) val 2038 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; val 2043 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) val 2045 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; val 2049 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) val 2051 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; val 2057 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) val 2059 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; val 2063 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) val 2065 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; val 2073 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) val 2075 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; val 2079 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) val 2081 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; val 2085 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) val 2087 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; val 2091 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) val 2093 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; val 2097 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) val 2099 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; val 2103 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) val 2105 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; val 2109 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) val 2111 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; val 2115 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) val 2117 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; val 2121 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) val 2123 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; val 2127 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) val 2129 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; val 2133 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) val 2135 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; val 2139 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) val 2141 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; val 2145 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) val 2147 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; val 2151 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) val 2153 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; val 2157 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) val 2159 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; val 2163 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) val 2165 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; val 2173 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) val 2175 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK; val 2179 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) val 2181 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK; val 2185 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) val 2187 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK; val 2191 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) val 2193 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK; val 2197 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) val 2199 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK; val 2203 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) val 2205 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK; val 2209 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) val 2211 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK; val 2215 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) val 2217 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK; val 2221 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) val 2223 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK; val 2227 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) val 2229 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK; val 2233 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) val 2235 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK; val 2239 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) val 2241 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK; val 2245 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) val 2247 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK; val 2251 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) val 2253 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK; val 2257 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) val 2259 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK; val 2263 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) val 2265 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK; val 2276 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) val 2278 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; val 2283 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) val 2285 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; val 2289 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) val 2291 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; val 2297 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) val 2299 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; val 2303 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) val 2305 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; val 2311 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 2313 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 2317 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 2319 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 2323 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 2325 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; val 2330 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) val 2332 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; val 2338 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) val 2340 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; val 2344 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) val 2346 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; val 2350 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) val 2352 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; val 2358 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) val 2360 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; val 2364 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) val 2366 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; val 2371 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) val 2373 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; val 2381 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) val 2383 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; val 2388 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) val 2390 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; val 2394 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) val 2396 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; val 2401 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) val 2403 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; val 2411 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) val 2413 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; val 2417 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) val 2419 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; val 2423 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) val 2425 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; val 2429 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) val 2431 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; val 2437 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) val 2439 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; val 2443 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) val 2445 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; val 2449 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) val 2451 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; val 2459 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) val 2461 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; val 2465 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) val 2467 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; val 2471 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) val 2473 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; val 2479 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) val 2481 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; val 2485 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) val 2487 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; val 2495 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) val 2497 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; val 2503 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) val 2505 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; val 2509 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) val 2511 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; val 2517 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 2519 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 2523 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 2525 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 2532 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 2534 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; val 2541 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) val 2543 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; val 2549 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) val 2551 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; val 2555 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) val 2557 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; val 2561 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) val 2563 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; val 2567 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) val 2569 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; val 2575 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) val 2577 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; val 2581 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) val 2583 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; val 2587 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) val 2589 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; val 2597 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) val 2599 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; val 2603 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) val 2605 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; val 2609 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) val 2611 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; val 2617 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) val 2619 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; val 2623 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) val 2625 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; val 2637 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) val 2639 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK; val 2644 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) val 2646 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; val 2654 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) val 2656 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; val 2667 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) val 2669 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; val 2675 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) val 2677 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; val 2685 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) val 2687 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; val 2691 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) val 2693 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; val 2697 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) val 2699 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; val 2707 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) val 2709 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; val 2713 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) val 2715 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; val 2719 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) val 2721 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; val 2803 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) val 2805 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; val 2809 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) val 2811 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; val 2821 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) val 2823 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; val 2827 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) val 2829 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; val 2833 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) val 2835 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; val 2839 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) val 2841 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; val 2892 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) val 2894 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; val 2898 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) val 2900 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; val 2946 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) val 2948 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; val 2954 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) val 2956 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; val 2960 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) val 2962 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; val 3007 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) val 3009 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; val 3013 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) val 3015 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; val 3019 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) val 3021 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; val 3025 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) val 3027 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; val 3034 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) val 3036 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; val 3046 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) val 3048 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; val 3052 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) val 3054 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; val 3058 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) val 3060 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; val 3064 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) val 3066 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; val 3070 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) val 3072 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; val 3076 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) val 3078 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; val 3082 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) val 3084 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; val 3092 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) val 3094 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; val 3098 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) val 3100 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; val 3104 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) val 3106 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; val 3114 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) val 3116 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; val 3120 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) val 3122 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; val 3126 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) val 3128 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; val 3132 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) val 3134 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; val 3138 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) val 3140 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; val 3144 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) val 3146 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK; val 3150 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) val 3152 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; val 3157 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) val 3159 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; val 3165 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) val 3167 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; val 3171 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) val 3173 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; val 3177 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) val 3179 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; val 3185 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) val 3187 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; val 3191 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) val 3193 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; val 3197 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) val 3199 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; val 3205 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) val 3207 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; val 3211 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) val 3213 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; val 3217 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) val 3219 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; val 847 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) val 849 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; val 904 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) val 906 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; val 910 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) val 912 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; val 926 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) val 928 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; val 932 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) val 934 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; val 946 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) val 948 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; val 961 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) val 963 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; val 977 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) val 979 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; val 983 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) val 985 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; val 991 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) val 993 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; val 997 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) val 999 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; val 1003 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) val 1005 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; val 1009 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 1011 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; val 1016 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) val 1018 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; val 1026 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) val 1028 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; val 1034 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) val 1036 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; val 1040 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) val 1042 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; val 1046 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) val 1048 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; val 1052 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) val 1054 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; val 1058 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) val 1060 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; val 1064 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) val 1066 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; val 1072 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) val 1074 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; val 1078 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) val 1080 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; val 1084 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) val 1086 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; val 1092 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) val 1094 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; val 1100 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) val 1102 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; val 1106 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) val 1108 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; val 1112 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) val 1114 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; val 1120 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) val 1122 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; val 1128 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) val 1130 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; val 1134 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) val 1136 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; val 1140 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) val 1142 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; val 1148 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) val 1150 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; val 1156 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) val 1158 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; val 1162 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) val 1164 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; val 1168 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) val 1170 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; val 1176 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) val 1178 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; val 1184 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) val 1186 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; val 1191 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) val 1193 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; val 1199 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) val 1201 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; val 1206 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) val 1208 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; val 1215 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) val 1217 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; val 1223 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) val 1225 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; val 1229 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) val 1231 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; val 1235 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) val 1237 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; val 1241 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) val 1243 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; val 1247 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) val 1249 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; val 1253 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) val 1255 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; val 1259 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) val 1261 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; val 1265 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) val 1267 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; val 1273 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) val 1275 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; val 1279 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) val 1281 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; val 1285 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) val 1287 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; val 1291 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) val 1293 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; val 1299 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) val 1301 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; val 1307 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) val 1309 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; val 1315 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) val 1317 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; val 1321 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) val 1323 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; val 1327 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) val 1329 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; val 1333 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) val 1335 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; val 1339 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) val 1341 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; val 1345 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) val 1347 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; val 1353 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) val 1355 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; val 1365 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) val 1367 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; val 1379 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) val 1381 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; val 1385 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) val 1387 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; val 1393 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) val 1395 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; val 1401 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) val 1403 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; val 1412 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) val 1414 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; val 1418 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) val 1420 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; val 1424 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) val 1426 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; val 1430 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) val 1432 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; val 1436 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) val 1438 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; val 1442 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) val 1444 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; val 1448 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) val 1450 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; val 1454 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) val 1456 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; val 1466 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) val 1468 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; val 1474 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) val 1476 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; val 1482 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) val 1484 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; val 1488 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) val 1490 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; val 1494 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) val 1496 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; val 1502 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) val 1504 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; val 1508 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) val 1510 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; val 1514 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) val 1516 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; val 1523 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) val 1525 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; val 1529 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) val 1531 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; val 2203 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) val 2205 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; val 2209 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) val 2211 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; val 2293 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) val 2295 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; val 2301 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 2303 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 2307 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 2309 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 2313 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) val 2315 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; val 2319 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 2321 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; val 2329 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) val 2331 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; val 2335 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) val 2337 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; val 2343 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) val 2345 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; val 2349 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) val 2351 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; val 2355 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) val 2357 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; val 2365 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) val 2367 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; val 2371 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) val 2373 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; val 2377 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) val 2379 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; val 2383 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) val 2385 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; val 2393 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) val 2395 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; val 2399 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) val 2401 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; val 2405 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) val 2407 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; val 2411 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) val 2413 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; val 2419 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) val 2421 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; val 2425 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) val 2427 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; val 2441 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) val 2443 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; val 2449 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 2451 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 2455 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 2457 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 2461 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) val 2463 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; val 2467 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 2469 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; val 2477 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) val 2479 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; val 2488 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) val 2490 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; val 2494 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) val 2496 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; val 2510 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) val 2512 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; val 2517 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) val 2519 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; val 2523 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) val 2525 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; val 2533 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) val 2535 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; val 2540 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) val 2542 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; val 2563 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) val 2565 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; val 2569 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) val 2571 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; val 2585 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) val 2587 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; val 2591 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) val 2593 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; val 2601 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) val 2603 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; val 2607 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) val 2609 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; val 2613 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) val 2615 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; val 2619 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) val 2621 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; val 2629 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) val 2631 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; val 2635 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) val 2637 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; val 2641 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) val 2643 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; val 2647 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) val 2649 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; val 2655 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) val 2657 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; val 2661 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) val 2663 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; val 2677 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) val 2679 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; val 2683 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) val 2685 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; val 2689 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) val 2691 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; val 2699 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) val 2701 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; val 2705 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) val 2707 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; val 2711 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) val 2713 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; val 2717 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) val 2719 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; val 2727 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) val 2729 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; val 2733 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) val 2735 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; val 2739 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) val 2741 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; val 2745 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) val 2747 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; val 2753 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) val 2755 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; val 2759 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) val 2761 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; val 2789 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) val 2791 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; val 2796 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) val 2798 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; val 2805 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) val 2807 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; val 2811 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) val 2813 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; val 2817 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) val 2819 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; val 2835 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) val 2837 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; val 2841 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) val 2843 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; val 2857 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) val 2859 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; val 2863 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) val 2865 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; val 2869 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) val 2871 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; val 2875 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) val 2877 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; val 2919 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) val 2921 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; val 2925 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) val 2927 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; val 2931 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) val 2933 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; val 2937 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) val 2939 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; val 2945 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) val 2947 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; val 2951 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) val 2953 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; val 2957 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) val 2959 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; val 2967 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) val 2969 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; val 2973 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) val 2975 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; val 2979 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) val 2981 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; val 2993 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) val 2995 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; val 2999 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) val 3001 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; val 3011 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) val 3013 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; val 3019 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) val 3021 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; val 3029 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) val 3031 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; val 3036 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) val 3038 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; val 3042 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) val 3044 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; val 3049 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) val 3051 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; val 3055 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) val 3057 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; val 3087 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) val 3089 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; val 3093 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) val 3095 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; val 3099 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) val 3101 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; val 3105 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) val 3107 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; val 3160 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) val 3162 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; val 3166 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) val 3168 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; val 3174 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) val 3176 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; val 3182 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) val 3184 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; val 3190 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) val 3192 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; val 3198 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) val 3200 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; val 3206 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) val 3208 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; val 3214 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) val 3216 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; val 3222 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) val 3224 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; val 3228 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) val 3230 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; val 3236 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) val 3238 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; val 3248 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) val 3250 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; val 3256 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) val 3258 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; val 3264 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) val 3266 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; val 3272 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) val 3274 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; val 3283 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) val 3285 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; val 3294 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) val 3296 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; val 3300 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) val 3302 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; val 3307 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) val 3309 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; val 3316 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) val 3318 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; val 3322 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) val 3324 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; val 3331 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) val 3333 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; val 3337 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) val 3339 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; val 3346 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) val 3348 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; val 3352 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) val 3354 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; val 3361 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) val 3363 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; val 3367 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) val 3369 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; val 3376 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) val 3378 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; val 3382 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) val 3384 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; val 3391 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) val 3393 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; val 3397 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) val 3399 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; val 3459 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) val 3461 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; val 3469 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) val 3471 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; val 3481 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) val 3483 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; val 3489 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) val 3491 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; val 3495 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) val 3497 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; val 3503 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) val 3505 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; val 3509 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) val 3511 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; val 3515 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) val 3517 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; val 3521 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) val 3523 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; val 3529 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) val 3531 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; val 3539 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) val 3541 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; val 3545 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) val 3547 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; val 3553 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) val 3555 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; val 3559 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) val 3561 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; val 3567 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) val 3569 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; val 3573 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) val 3575 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; val 3581 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) val 3583 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; val 3587 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) val 3589 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; val 3595 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) val 3597 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; val 3601 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) val 3603 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; val 3609 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) val 3611 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; val 3615 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) val 3617 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; val 3623 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) val 3625 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; val 3629 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) val 3631 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; val 3637 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) val 3639 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; val 3643 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) val 3645 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; val 3651 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) val 3653 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; val 3657 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) val 3659 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; val 3665 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) val 3667 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; val 3671 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) val 3673 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; val 3679 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val) val 3681 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK; val 3685 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) val 3687 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; val 3693 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) val 3695 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK; val 3699 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val) val 3701 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK; val 3707 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val) val 3709 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK; val 3713 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val) val 3715 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK; val 3719 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val) val 3721 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK; val 3725 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val) val 3727 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK; val 3733 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val) val 3735 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK; val 3743 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val) val 3745 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK; val 3753 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val) val 3755 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK; val 3763 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val) val 3765 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK; val 3769 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val) val 3771 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK; val 3816 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) val 3818 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; val 3822 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) val 3824 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; val 3830 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) val 3832 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; val 3841 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) val 3843 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK; val 3847 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) val 3849 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK; val 3858 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) val 3860 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; val 3864 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) val 3866 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; val 3870 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) val 3872 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; val 3879 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) val 3881 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; val 3885 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) val 3887 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; val 3993 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) val 3995 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; val 3999 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) val 4001 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; val 4005 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) val 4007 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; val 4011 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) val 4013 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; val 4017 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) val 4019 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; val 4023 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) val 4025 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; val 4029 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) val 4031 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK; val 4037 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) val 4039 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; val 4046 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) val 4048 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; val 4052 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) val 4054 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; val 4062 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) val 4064 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; val 4068 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) val 4070 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; val 4074 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) val 4076 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; val 4080 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) val 4082 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; val 4086 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) val 4088 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; val 4092 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) val 4094 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; val 4098 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) val 4100 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; val 4106 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) val 4108 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; val 4112 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) val 4114 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; val 4120 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) val 4122 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; val 4126 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) val 4128 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; val 4132 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) val 4134 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; val 4140 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) val 4142 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; val 4146 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) val 4148 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; val 4154 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) val 4156 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; val 4160 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) val 4162 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; val 4174 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val) val 4176 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK; val 4182 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val) val 4184 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK; val 4190 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) val 4192 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK; val 4198 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val) val 4200 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK; val 4206 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val) val 4208 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK; val 4212 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val) val 4214 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK; val 4218 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val) val 4220 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK; val 4226 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val) val 4228 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK; val 4232 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val) val 4234 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK; val 227 drivers/gpu/drm/msm/adreno/a4xx_gpu.c unsigned int val; val 228 drivers/gpu/drm/msm/adreno/a4xx_gpu.c val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); val 229 drivers/gpu/drm/msm/adreno/a4xx_gpu.c val &= ~A4XX_CGC_HLSQ_EARLY_CYC__MASK; val 230 drivers/gpu/drm/msm/adreno/a4xx_gpu.c val |= 2 << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT; val 231 drivers/gpu/drm/msm/adreno/a4xx_gpu.c gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, val); val 1045 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) val 1047 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; val 1051 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) val 1053 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; val 1958 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) val 1960 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; val 1964 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) val 1966 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; val 1982 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) val 1984 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK; val 1988 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) val 1990 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK; val 1994 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) val 1996 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK; val 2000 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) val 2002 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK; val 2023 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) val 2025 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK; val 2029 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) val 2031 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK; val 2672 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) val 2674 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; val 2678 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) val 2680 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; val 2686 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) val 2688 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK; val 2694 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) val 2696 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK; val 2702 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) val 2704 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK; val 2710 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) val 2712 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK; val 2718 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) val 2720 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; val 2726 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) val 2728 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK; val 2737 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) val 2739 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; val 2747 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) val 2749 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; val 2753 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) val 2755 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; val 2761 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) val 2763 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK; val 2775 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) val 2777 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; val 2783 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) val 2785 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; val 2791 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) val 2793 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; val 2799 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) val 2801 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; val 2815 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 2817 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK; val 2823 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 2825 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK; val 2835 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) val 2837 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; val 2841 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) val 2843 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; val 2850 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) val 2852 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; val 2856 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) val 2858 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; val 2865 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) val 2867 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; val 2871 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) val 2873 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; val 2880 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) val 2882 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; val 2886 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) val 2888 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; val 2895 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) val 2897 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; val 2901 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) val 2903 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; val 2910 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) val 2912 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; val 2916 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) val 2918 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; val 2933 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) val 2935 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK; val 2945 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) val 2947 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; val 2951 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) val 2953 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; val 2965 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) val 2967 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; val 2971 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) val 2973 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK; val 2979 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 2981 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; val 2987 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 2989 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; val 3009 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) val 3011 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK; val 3018 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) val 3020 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK; val 3024 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) val 3026 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK; val 3030 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) val 3032 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK; val 3036 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) val 3038 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK; val 3042 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) val 3044 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK; val 3048 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) val 3050 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK; val 3054 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) val 3056 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK; val 3060 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) val 3062 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK; val 3073 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) val 3075 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK; val 3079 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) val 3081 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; val 3087 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) val 3089 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; val 3093 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) val 3095 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; val 3099 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) val 3101 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; val 3105 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) val 3107 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; val 3111 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) val 3113 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; val 3117 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) val 3119 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; val 3125 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) val 3127 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; val 3131 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) val 3133 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; val 3137 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) val 3139 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; val 3143 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 3145 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; val 3152 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) val 3154 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; val 3160 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) val 3162 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; val 3172 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) val 3174 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK; val 3178 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) val 3180 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK; val 3184 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) val 3186 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; val 3192 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) val 3194 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK; val 3200 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) val 3202 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK; val 3206 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) val 3208 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK; val 3212 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) val 3214 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; val 3220 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) val 3222 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK; val 3228 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) val 3230 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK; val 3234 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) val 3236 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK; val 3240 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) val 3242 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; val 3248 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) val 3250 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK; val 3256 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) val 3258 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK; val 3262 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) val 3264 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK; val 3268 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) val 3270 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; val 3276 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) val 3278 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK; val 3284 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) val 3286 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; val 3291 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) val 3293 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; val 3299 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) val 3301 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; val 3307 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) val 3309 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; val 3321 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) val 3323 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK; val 3330 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) val 3332 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; val 3342 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) val 3344 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; val 3350 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) val 3352 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; val 3361 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) val 3363 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK; val 3367 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) val 3369 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK; val 3373 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) val 3375 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK; val 3379 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) val 3381 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK; val 3385 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) val 3387 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; val 3391 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) val 3393 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; val 3397 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) val 3399 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; val 3403 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) val 3405 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; val 3418 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) val 3420 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; val 3426 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) val 3428 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; val 3434 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) val 3436 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK; val 3440 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) val 3442 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK; val 3446 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) val 3448 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; val 3454 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) val 3456 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; val 3460 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) val 3462 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; val 3466 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) val 3468 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; val 3475 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) val 3477 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK; val 3481 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) val 3483 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK; val 3492 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) val 3494 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK; val 3501 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) val 3503 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK; val 3507 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) val 3509 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK; val 3516 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) val 3518 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK; val 3522 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) val 3524 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK; val 3537 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) val 3539 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; val 3545 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) val 3547 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; val 3563 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) val 3565 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK; val 3583 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) val 3585 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; val 3591 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) val 3593 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; val 3603 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) val 3605 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; val 3611 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) val 3613 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; val 3623 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) val 3625 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK; val 3652 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) val 3654 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK; val 3658 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val) val 3660 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK; val 3681 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val) val 3683 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK; val 3687 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val) val 3689 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK; val 3694 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val) val 3696 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK; val 3700 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val) val 3702 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK; val 3725 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) val 3727 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; val 3739 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) val 3741 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK; val 3745 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) val 3747 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK; val 3760 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) val 3762 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK; val 3766 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) val 3768 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK; val 3772 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) val 3774 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK; val 3780 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) val 3782 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK; val 3786 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) val 3788 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK; val 3798 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) val 3800 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK; val 3806 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) val 3808 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK; val 3812 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) val 3814 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK; val 3818 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) val 3820 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK; val 3826 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) val 3828 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK; val 3834 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) val 3836 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK; val 3840 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) val 3842 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK; val 3846 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) val 3848 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK; val 3874 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) val 3876 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK; val 3881 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) val 3883 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK; val 3887 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) val 3889 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK; val 3901 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) val 3903 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; val 3907 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) val 3909 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK; val 3920 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 3922 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK; val 3926 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 3928 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK; val 3935 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 3937 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK; val 3941 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 3943 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK; val 3950 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 3952 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK; val 3956 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 3958 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK; val 3965 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 3967 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK; val 3971 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 3973 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK; val 3980 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 3982 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK; val 3986 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 3988 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK; val 3995 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 3997 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK; val 4001 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 4003 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK; val 4013 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4015 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; val 4019 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4021 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4025 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4027 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4033 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4035 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; val 4041 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) val 4043 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; val 4051 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) val 4053 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK; val 4057 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) val 4059 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK; val 4063 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) val 4065 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK; val 4069 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) val 4071 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; val 4079 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) val 4081 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; val 4085 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) val 4087 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; val 4091 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) val 4093 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; val 4097 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) val 4099 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; val 4111 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4113 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; val 4117 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4119 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4123 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4125 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4131 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4133 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; val 4150 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) val 4152 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK; val 4156 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) val 4158 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK; val 4162 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) val 4164 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; val 4172 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) val 4174 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK; val 4183 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) val 4185 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; val 4196 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4198 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; val 4202 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4204 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4208 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4210 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4216 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4218 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; val 4230 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4232 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; val 4236 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4238 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4242 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4244 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4250 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4252 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; val 4264 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4266 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; val 4270 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4272 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4276 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4278 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4284 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4286 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; val 4298 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4300 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; val 4304 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4306 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4310 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4312 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4318 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4320 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; val 4332 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 4334 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK; val 4340 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 4342 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK; val 4415 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) val 4417 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; val 4421 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val) val 4423 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK; val 4429 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) val 4431 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; val 4437 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) val 4439 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; val 4443 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) val 4445 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; val 4449 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) val 4451 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; val 4457 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) val 4459 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; val 4465 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) val 4467 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; val 4471 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) val 4473 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; val 4482 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 4484 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK; val 4488 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 4490 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK; val 4497 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 4499 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK; val 4503 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 4505 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK; val 4512 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 4514 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK; val 4518 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 4520 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK; val 4527 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 4529 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK; val 4533 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 4535 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK; val 4542 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 4544 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK; val 4548 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 4550 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK; val 4557 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) val 4559 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK; val 4563 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) val 4565 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK; val 4572 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) val 4574 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK; val 4581 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) val 4583 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK; val 4590 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) val 4592 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK; val 4599 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) val 4601 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK; val 4608 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) val 4610 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK; val 4617 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) val 4619 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK; val 4631 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) val 4633 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; val 4637 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) val 4639 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; val 4643 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) val 4645 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; val 4649 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) val 4651 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; val 4657 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) val 4659 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; val 4665 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) val 4667 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; val 4673 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) val 4675 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; val 4681 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) val 4683 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; val 4689 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) val 4691 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; val 4697 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) val 4699 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; val 4705 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) val 4707 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; val 4711 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) val 4713 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK; val 4717 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) val 4719 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK; val 4723 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) val 4725 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; val 4779 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) val 4781 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK; val 4785 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) val 4787 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK; val 4791 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 4793 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK; val 4804 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) val 4806 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK; val 4810 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) val 4812 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK; val 4818 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) val 4820 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; val 4824 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) val 4826 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK; val 4830 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 4832 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; val 4843 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) val 4845 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK; val 4849 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) val 4851 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK; val 4867 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) val 4869 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK; val 4873 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) val 4875 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK; val 4879 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 4881 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK; val 4888 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) val 4890 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK; val 4894 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) val 4896 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK; val 4900 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 4902 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK; val 4916 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) val 4918 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK; val 4922 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) val 4924 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK; val 4928 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) val 4930 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK; val 4934 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) val 4936 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK; val 4940 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) val 4942 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK; val 4946 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) val 4948 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK; val 4952 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) val 4954 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK; val 4960 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) val 4962 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK; val 4969 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) val 4971 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; val 4975 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) val 4977 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; val 4983 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) val 4985 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; val 4993 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) val 4995 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK; val 5000 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) val 5002 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK; val 5006 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) val 5008 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK; val 5012 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) val 5014 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK; val 5018 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) val 5020 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK; val 5024 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val) val 5026 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK; val 5030 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) val 5032 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK; val 5036 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) val 5038 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK; val 5042 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) val 5044 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK; val 5050 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) val 5052 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK; val 5056 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) val 5058 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK; val 5064 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val) val 5066 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK; val 5070 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) val 5072 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK; val 5076 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) val 5078 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; val 5084 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) val 5086 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; val 5093 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) val 5095 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; val 5101 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) val 5103 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK; val 5107 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) val 5109 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK; val 5127 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val) val 5129 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK; val 5135 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val) val 5137 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK; val 5143 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) val 5145 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK; val 5151 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val) val 5153 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK; val 5159 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val) val 5161 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK; val 5165 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val) val 5167 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK; val 5173 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val) val 5175 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK; val 5179 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val) val 5181 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK; val 5187 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val) val 5189 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK; val 5195 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val) val 5197 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK; val 67 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c uint32_t val[4]; val 70 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); val 72 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c val[0], val[1], val[2], val[3]); val 100 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c reset_set(void *data, u64 val) val 855 drivers/gpu/drm/msm/adreno/a5xx_gpu.c u32 val; val 865 drivers/gpu/drm/msm/adreno/a5xx_gpu.c val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); val 868 drivers/gpu/drm/msm/adreno/a5xx_gpu.c val); val 879 drivers/gpu/drm/msm/adreno/a5xx_gpu.c u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS); val 883 drivers/gpu/drm/msm/adreno/a5xx_gpu.c val & (1 << 24) ? "WRITE" : "READ", val 884 drivers/gpu/drm/msm/adreno/a5xx_gpu.c (val & 0xFFFFF) >> 2, val); val 904 drivers/gpu/drm/msm/adreno/a5xx_gpu.c u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS); val 908 drivers/gpu/drm/msm/adreno/a5xx_gpu.c val & (1 << 28) ? "WRITE" : "READ", val 909 drivers/gpu/drm/msm/adreno/a5xx_gpu.c (val & 0xFFFFF) >> 2, (val >> 20) & 0x3, val 910 drivers/gpu/drm/msm/adreno/a5xx_gpu.c (val >> 24) & 0xF); val 1162 drivers/gpu/drm/msm/adreno/a5xx_gpu.c u32 val; val 1172 drivers/gpu/drm/msm/adreno/a5xx_gpu.c return gpu_poll_timeout(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, val, val 1173 drivers/gpu/drm/msm/adreno/a5xx_gpu.c val & 0x04, 100, 10000); val 1404 drivers/gpu/drm/msm/adreno/a5xx_gpu.c u32 bin, val; val 1415 drivers/gpu/drm/msm/adreno/a5xx_gpu.c val = (1 << bin); val 1417 drivers/gpu/drm/msm/adreno/a5xx_gpu.c dev_pm_opp_set_supported_hw(dev, &val, 1); val 267 drivers/gpu/drm/msm/adreno/a5xx_power.c u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1); val 269 drivers/gpu/drm/msm/adreno/a5xx_power.c if (val) val 271 drivers/gpu/drm/msm/adreno/a5xx_power.c gpu->name, val); val 1073 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) val 1075 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; val 1079 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) val 1081 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; val 2004 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) val 2006 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; val 2010 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) val 2012 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; val 2018 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) val 2020 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; val 2024 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) val 2026 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; val 2030 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) val 2032 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; val 2038 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) val 2040 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; val 2062 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) val 2064 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; val 2068 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) val 2070 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; val 2074 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) val 2076 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; val 2080 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) val 2082 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; val 2086 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) val 2088 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; val 2092 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) val 2094 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; val 2098 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) val 2100 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; val 2104 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) val 2106 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; val 2112 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) val 2114 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; val 2118 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) val 2120 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; val 2124 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) val 2126 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; val 2130 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) val 2132 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; val 2136 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) val 2138 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; val 2142 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) val 2144 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; val 2148 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) val 2150 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; val 2154 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) val 2156 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; val 2336 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) val 2338 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; val 2463 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) val 2465 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; val 2473 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) val 2475 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; val 2526 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) val 2528 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; val 2532 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) val 2534 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; val 2541 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) val 2543 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; val 2547 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) val 2549 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; val 2556 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) val 2558 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; val 2562 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) val 2564 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; val 2570 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) val 2572 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; val 2576 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) val 2578 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; val 2586 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) val 2588 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; val 2592 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) val 2594 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; val 2600 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) val 2602 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; val 2606 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) val 2608 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; val 2618 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) val 2620 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; val 2624 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) val 2626 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; val 2634 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) val 2636 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; val 2640 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) val 2642 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; val 2646 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) val 2648 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; val 2652 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) val 2654 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; val 2666 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val) val 2668 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK; val 2680 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val) val 2682 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK; val 2708 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) val 2710 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; val 2714 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) val 2716 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; val 2722 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val) val 2724 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK; val 2730 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val) val 2732 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK; val 2738 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val) val 2740 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK; val 2746 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val) val 2748 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK; val 2754 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val) val 2756 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; val 2762 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val) val 2764 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK; val 2773 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) val 2775 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; val 2783 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) val 2785 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; val 2789 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) val 2791 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; val 2797 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) val 2799 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; val 2808 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) val 2810 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; val 2816 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) val 2818 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; val 2824 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) val 2826 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; val 2832 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) val 2834 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; val 2846 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 2848 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; val 2854 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 2856 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; val 2872 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) val 2874 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; val 2878 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) val 2880 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; val 2887 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) val 2889 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; val 2893 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) val 2895 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; val 2902 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) val 2904 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; val 2908 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) val 2910 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; val 2917 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) val 2919 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; val 2923 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) val 2925 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; val 2932 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) val 2934 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; val 2938 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) val 2940 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; val 2947 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) val 2949 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; val 2953 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) val 2955 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; val 2970 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) val 2972 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK; val 2982 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) val 2984 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; val 2988 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) val 2990 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; val 3004 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) val 3006 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; val 3013 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val) val 3015 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK; val 3021 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val) val 3023 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK; val 3029 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val) val 3031 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK; val 3037 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val) val 3039 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK; val 3046 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) val 3048 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; val 3052 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) val 3054 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; val 3061 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) val 3063 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; val 3067 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) val 3069 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; val 3076 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val) val 3078 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK; val 3082 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val) val 3084 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK; val 3091 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val) val 3093 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK; val 3097 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val) val 3099 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK; val 3107 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) val 3109 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; val 3113 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) val 3115 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; val 3126 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) val 3128 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; val 3134 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 3136 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; val 3142 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 3144 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; val 3174 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) val 3176 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; val 3182 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) val 3184 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; val 3188 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) val 3190 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; val 3194 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) val 3196 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; val 3200 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) val 3202 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; val 3206 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) val 3208 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; val 3212 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) val 3214 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; val 3218 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) val 3220 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; val 3224 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) val 3226 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; val 3232 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) val 3234 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; val 3238 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) val 3240 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; val 3244 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) val 3246 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; val 3250 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) val 3252 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; val 3256 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) val 3258 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; val 3262 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) val 3264 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; val 3268 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) val 3270 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; val 3274 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) val 3276 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; val 3315 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) val 3317 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; val 3321 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) val 3323 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; val 3329 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) val 3331 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; val 3335 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) val 3337 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; val 3341 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) val 3343 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; val 3347 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) val 3349 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; val 3353 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) val 3355 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; val 3359 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) val 3361 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; val 3367 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) val 3369 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; val 3373 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) val 3375 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; val 3379 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 3381 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; val 3387 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) val 3389 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; val 3395 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) val 3397 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; val 3409 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) val 3411 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; val 3417 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) val 3419 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; val 3425 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) val 3427 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; val 3433 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) val 3435 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; val 3441 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) val 3443 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; val 3448 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) val 3450 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; val 3456 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) val 3458 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; val 3464 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) val 3466 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; val 3477 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) val 3479 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; val 3486 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) val 3488 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; val 3494 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) val 3496 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; val 3502 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) val 3504 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; val 3523 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) val 3525 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; val 3529 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) val 3531 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; val 3535 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) val 3537 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; val 3541 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) val 3543 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; val 3547 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) val 3549 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; val 3553 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) val 3555 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; val 3559 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) val 3561 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; val 3565 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) val 3567 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; val 3576 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) val 3578 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; val 3584 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) val 3586 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; val 3598 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) val 3600 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; val 3604 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) val 3606 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; val 3612 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) val 3614 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; val 3618 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) val 3620 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; val 3626 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) val 3628 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; val 3632 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) val 3634 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; val 3641 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) val 3643 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; val 3647 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) val 3649 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; val 3664 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) val 3666 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; val 3670 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) val 3672 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; val 3679 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) val 3681 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; val 3685 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) val 3687 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; val 3693 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 3695 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; val 3703 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) val 3705 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; val 3710 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) val 3712 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; val 3716 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) val 3718 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; val 3722 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 3724 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; val 3734 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) val 3736 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; val 3742 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) val 3744 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; val 3766 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) val 3768 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; val 3788 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) val 3790 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; val 3794 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) val 3796 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; val 3806 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) val 3808 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; val 3817 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) val 3819 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; val 3823 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) val 3825 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; val 3829 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 3831 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; val 3842 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val) val 3844 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK; val 3895 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) val 3897 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; val 3901 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) val 3903 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; val 3908 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) val 3910 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; val 3914 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) val 3916 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; val 3943 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val) val 3945 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK; val 3949 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) val 3951 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK; val 3955 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val) val 3957 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK; val 3963 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) val 3965 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; val 4006 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val) val 4008 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK; val 4025 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val) val 4027 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK; val 4033 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) val 4035 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; val 4039 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) val 4041 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; val 4045 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) val 4047 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; val 4053 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) val 4055 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK; val 4061 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) val 4063 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK; val 4067 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) val 4069 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; val 4073 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) val 4075 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; val 4110 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) val 4112 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; val 4117 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val) val 4119 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; val 4123 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) val 4125 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; val 4137 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) val 4139 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; val 4143 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) val 4145 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; val 4153 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) val 4155 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; val 4163 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) val 4165 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; val 4169 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) val 4171 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; val 4175 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) val 4177 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; val 4181 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) val 4183 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; val 4191 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) val 4193 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; val 4197 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) val 4199 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; val 4203 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) val 4205 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; val 4209 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) val 4211 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; val 4217 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4219 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4223 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4225 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4229 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4231 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; val 4235 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4237 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; val 4255 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) val 4257 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; val 4261 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) val 4263 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; val 4271 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4273 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4277 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4279 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4283 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4285 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; val 4289 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4291 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; val 4309 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) val 4311 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; val 4315 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) val 4317 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; val 4325 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4327 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4331 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4333 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4337 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4339 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; val 4343 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4345 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; val 4361 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) val 4363 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; val 4367 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) val 4369 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; val 4377 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4379 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4383 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4385 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4389 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4391 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; val 4395 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4397 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; val 4415 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) val 4417 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; val 4421 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) val 4423 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; val 4463 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4465 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4469 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4471 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4475 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4477 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; val 4481 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4483 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; val 4513 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) val 4515 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; val 4519 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) val 4521 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; val 4525 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) val 4527 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; val 4531 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) val 4533 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; val 4537 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) val 4539 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; val 4543 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) val 4545 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; val 4549 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) val 4551 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; val 4555 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) val 4557 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; val 4563 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) val 4565 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; val 4571 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) val 4573 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; val 4581 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val) val 4583 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; val 4615 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) val 4617 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; val 4624 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) val 4626 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; val 4630 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) val 4632 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; val 4636 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) val 4638 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; val 4642 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) val 4644 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; val 4662 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) val 4664 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; val 4668 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) val 4670 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; val 4694 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 4696 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; val 4702 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) val 4704 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; val 4719 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) val 4721 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; val 4725 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) val 4727 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; val 4731 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) val 4733 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; val 4741 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) val 4743 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; val 4747 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) val 4749 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; val 4759 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) val 4761 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; val 4775 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) val 4777 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; val 4783 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) val 4785 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; val 4791 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) val 4793 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; val 4799 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) val 4801 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; val 4811 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) val 4813 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; val 4817 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) val 4819 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; val 4823 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) val 4825 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; val 4831 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) val 4833 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; val 4839 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) val 4841 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; val 4845 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) val 4847 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; val 4855 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) val 4857 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; val 4861 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) val 4863 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; val 4867 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) val 4869 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; val 4873 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) val 4875 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; val 4881 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) val 4883 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; val 4889 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) val 4891 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; val 4897 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) val 4899 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; val 4905 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) val 4907 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; val 4913 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) val 4915 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; val 4921 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) val 4923 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; val 4929 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) val 4931 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; val 4935 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) val 4937 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK; val 4941 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) val 4943 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK; val 4947 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) val 4949 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; val 4963 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) val 4965 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; val 4980 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) val 4982 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; val 4986 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) val 4988 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; val 4992 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) val 4994 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; val 4998 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) val 5000 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; val 5004 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) val 5006 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; val 5010 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) val 5012 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; val 5016 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) val 5018 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; val 5024 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) val 5026 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; val 5033 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) val 5035 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; val 5039 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) val 5041 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; val 5047 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) val 5049 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; val 5057 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) val 5059 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; val 5064 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) val 5066 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; val 5070 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) val 5072 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; val 5076 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) val 5078 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; val 5082 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) val 5084 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; val 5088 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) val 5090 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; val 5094 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) val 5096 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; val 5100 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val) val 5102 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; val 5106 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) val 5108 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; val 5114 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) val 5116 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; val 5120 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) val 5122 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; val 5128 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val) val 5130 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK; val 5134 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) val 5136 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; val 5140 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) val 5142 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; val 5148 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) val 5150 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; val 5157 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) val 5159 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; val 5165 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) val 5167 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; val 5171 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) val 5173 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; val 5181 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) val 5183 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; val 5189 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) val 5191 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; val 5265 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) val 5267 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; val 5271 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) val 5273 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; val 5285 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) val 5287 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; val 5291 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) val 5293 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; val 5297 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) val 5299 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; val 5305 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) val 5307 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; val 5329 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) val 5331 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; val 5335 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) val 5337 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; val 5341 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) val 5343 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; val 5347 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) val 5349 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; val 5353 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) val 5355 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; val 5359 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) val 5361 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; val 5365 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) val 5367 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; val 5371 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) val 5373 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; val 5379 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) val 5381 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; val 5385 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) val 5387 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; val 5391 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) val 5393 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; val 5397 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) val 5399 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; val 5403 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) val 5405 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; val 5409 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) val 5411 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; val 5415 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) val 5417 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; val 5421 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) val 5423 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; val 74 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 80 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); val 82 drivers/gpu/drm/msm/adreno/a6xx_gmu.c return !(val & val 90 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 96 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); val 98 drivers/gpu/drm/msm/adreno/a6xx_gmu.c return !(val & val 166 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 173 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); val 175 drivers/gpu/drm/msm/adreno/a6xx_gmu.c if (val == local) { val 193 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 198 drivers/gpu/drm/msm/adreno/a6xx_gmu.c ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, val 199 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val == 0xbabeface, 100, 10000); val 209 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 214 drivers/gpu/drm/msm/adreno/a6xx_gmu.c ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, val 215 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val & 1, 100, 10000); val 226 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 254 drivers/gpu/drm/msm/adreno/a6xx_gmu.c ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, val 255 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val & (1 << ack), 100, 10000); val 292 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 296 drivers/gpu/drm/msm/adreno/a6xx_gmu.c ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, val 297 drivers/gpu/drm/msm/adreno/a6xx_gmu.c (val & 0x38) == 0x28, 1, 100); val 310 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 318 drivers/gpu/drm/msm/adreno/a6xx_gmu.c ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, val 319 drivers/gpu/drm/msm/adreno/a6xx_gmu.c (val & 0x04), 100, 10000); val 379 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 385 drivers/gpu/drm/msm/adreno/a6xx_gmu.c ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, val 386 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val & (1 << 1), 100, 10000); val 392 drivers/gpu/drm/msm/adreno/a6xx_gmu.c ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, val 393 drivers/gpu/drm/msm/adreno/a6xx_gmu.c !val, 100, 10000); val 414 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 419 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val, val & (1 << 16), 100, 10000); val 664 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 667 drivers/gpu/drm/msm/adreno/a6xx_gmu.c gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, val 668 drivers/gpu/drm/msm/adreno/a6xx_gmu.c (val & 1), 100, 10000); val 669 drivers/gpu/drm/msm/adreno/a6xx_gmu.c gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, val 670 drivers/gpu/drm/msm/adreno/a6xx_gmu.c (val & 1), 100, 10000); val 671 drivers/gpu/drm/msm/adreno/a6xx_gmu.c gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, val 672 drivers/gpu/drm/msm/adreno/a6xx_gmu.c (val & 1), 100, 10000); val 673 drivers/gpu/drm/msm/adreno/a6xx_gmu.c gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, val 674 drivers/gpu/drm/msm/adreno/a6xx_gmu.c (val & 1), 100, 1000); val 787 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 val; val 793 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); val 795 drivers/gpu/drm/msm/adreno/a6xx_gmu.c if (val != 0xf) { val 814 drivers/gpu/drm/msm/adreno/a6xx_gmu.c REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, val 815 drivers/gpu/drm/msm/adreno/a6xx_gmu.c !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), val 997 drivers/gpu/drm/msm/adreno/a6xx_gmu.c unsigned int val; val 1006 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val = dev_pm_opp_get_level(opp); val 1010 drivers/gpu/drm/msm/adreno/a6xx_gmu.c return val; val 94 drivers/gpu/drm/msm/adreno/a6xx_gmu.h u32 val = gmu_read(gmu, reg); val 96 drivers/gpu/drm/msm/adreno/a6xx_gmu.h val &= ~mask; val 98 drivers/gpu/drm/msm/adreno/a6xx_gmu.h gmu_write(gmu, reg, val | or); val 103 drivers/gpu/drm/msm/adreno/a6xx_gmu.h u64 val; val 105 drivers/gpu/drm/msm/adreno/a6xx_gmu.h val = (u64) msm_readl(gmu->mmio + (lo << 2)); val 106 drivers/gpu/drm/msm/adreno/a6xx_gmu.h val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32); val 108 drivers/gpu/drm/msm/adreno/a6xx_gmu.h return val; val 111 drivers/gpu/drm/msm/adreno/a6xx_gmu.h #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ val 112 drivers/gpu/drm/msm/adreno/a6xx_gmu.h readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ val 69 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) val 71 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK; val 75 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) val 77 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK; val 152 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val) val 154 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK; val 158 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val) val 160 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK; val 181 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) val 183 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK; val 271 drivers/gpu/drm/msm/adreno/a6xx_gpu.c u32 val; val 273 drivers/gpu/drm/msm/adreno/a6xx_gpu.c val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); val 276 drivers/gpu/drm/msm/adreno/a6xx_gpu.c if ((!state && !val) || (state && (val == 0x8aa8aa02))) val 624 drivers/gpu/drm/msm/adreno/a6xx_gpu.c u32 val; val 627 drivers/gpu/drm/msm/adreno/a6xx_gpu.c val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); val 630 drivers/gpu/drm/msm/adreno/a6xx_gpu.c val); val 642 drivers/gpu/drm/msm/adreno/a6xx_gpu.c u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); val 646 drivers/gpu/drm/msm/adreno/a6xx_gpu.c val & (1 << 20) ? "READ" : "WRITE", val 647 drivers/gpu/drm/msm/adreno/a6xx_gpu.c (val & 0x3ffff), val); val 48 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static inline int CRASHDUMP_WRITE(u64 *in, u32 reg, u32 val) val 50 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c in[0] = val; val 130 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c u32 val; val 147 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, val 148 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c val & 0x02, 100, 10000); val 176 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c #define cxdbg_write(ptr, offset, val) \ val 177 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c msm_writel((val), (ptr) + ((offset) << 2)) val 11 drivers/gpu/drm/msm/adreno/a6xx_hfi.c #define HFI_MSG_ID(val) [val] = #val val 86 drivers/gpu/drm/msm/adreno/a6xx_hfi.c u32 val; val 90 drivers/gpu/drm/msm/adreno/a6xx_hfi.c ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, val 91 drivers/gpu/drm/msm/adreno/a6xx_hfi.c val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 5000); val 205 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) val 207 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; val 211 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) val 213 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; val 217 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) val 219 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; val 228 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) val 230 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; val 234 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) val 236 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; val 252 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) val 254 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; val 258 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) val 260 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; val 264 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) val 266 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; val 272 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) val 274 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; val 278 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) val 280 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; val 286 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) val 288 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; val 292 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) val 294 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; val 298 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) val 300 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; val 306 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) val 308 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; val 314 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) val 316 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; val 322 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) val 324 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; val 328 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) val 330 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; val 381 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) val 383 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; val 387 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) val 389 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; val 395 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) val 397 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; val 401 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) val 403 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; val 409 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) val 411 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; val 415 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) val 417 drivers/gpu/drm/msm/adreno/adreno_common.xml.h return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; val 796 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t val = gpu_read(gpu, addr); val 797 drivers/gpu/drm/msm/adreno/adreno_gpu.c printk("IO:R %08x %08x\n", addr<<2, val); val 833 drivers/gpu/drm/msm/adreno/adreno_gpu.c unsigned int val; val 835 drivers/gpu/drm/msm/adreno/adreno_gpu.c ret = of_property_read_u32(child, "qcom,gpu-freq", &val); val 843 drivers/gpu/drm/msm/adreno/adreno_gpu.c if (val != 27000000) val 844 drivers/gpu/drm/msm/adreno/adreno_gpu.c dev_pm_opp_add(dev, val, 0); val 280 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline u32 PM4_PARITY(u32 val) val 282 drivers/gpu/drm/msm/adreno/adreno_gpu.h return (0x9669 >> (0xF & (val ^ val 283 drivers/gpu/drm/msm/adreno/adreno_gpu.h (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ val 284 drivers/gpu/drm/msm/adreno/adreno_gpu.h (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ val 285 drivers/gpu/drm/msm/adreno/adreno_gpu.h (val >> 28)))) & 1; val 339 drivers/gpu/drm/msm/adreno/adreno_gpu.h u32 val = 0; val 341 drivers/gpu/drm/msm/adreno/adreno_gpu.h val = gpu_read(&gpu->base, reg - 1); val 342 drivers/gpu/drm/msm/adreno/adreno_gpu.h return val; val 396 drivers/gpu/drm/msm/adreno/adreno_gpu.h #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \ val 397 drivers/gpu/drm/msm/adreno/adreno_gpu.h readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \ val 380 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) val 382 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; val 386 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) val 388 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; val 392 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) val 394 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; val 398 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) val 400 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; val 406 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) val 408 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; val 412 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) val 414 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; val 420 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) val 422 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK; val 426 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) val 428 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK; val 432 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) val 434 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK; val 438 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) val 440 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK; val 446 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) val 448 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK; val 452 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) val 454 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; val 460 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) val 462 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK; val 468 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val) val 470 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK; val 474 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) val 476 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK; val 480 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) val 482 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK; val 486 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) val 488 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK; val 492 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) val 494 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK; val 500 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) val 502 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; val 508 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) val 510 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK; val 516 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) val 518 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; val 524 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) val 526 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; val 530 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) val 532 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; val 536 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) val 538 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; val 542 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) val 544 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; val 551 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) val 553 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; val 559 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) val 561 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; val 567 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) val 569 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; val 575 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) val 577 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; val 583 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) val 585 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; val 591 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) val 593 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; val 597 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) val 599 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; val 603 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) val 605 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; val 609 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) val 611 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; val 618 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) val 620 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; val 626 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) val 628 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; val 634 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) val 636 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; val 640 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) val 642 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; val 646 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) val 648 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; val 652 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) val 654 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; val 658 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val) val 660 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK; val 666 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) val 668 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; val 674 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) val 676 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; val 684 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) val 686 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; val 692 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) val 694 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; val 700 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) val 702 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; val 706 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) val 708 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; val 712 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) val 714 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK; val 718 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) val 720 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; val 724 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val) val 726 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK; val 732 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) val 734 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; val 741 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) val 743 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; val 749 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) val 751 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; val 755 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) val 757 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; val 761 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) val 763 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; val 767 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) val 769 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; val 773 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val) val 775 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK; val 782 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) val 784 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK; val 790 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) val 792 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK; val 798 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) val 800 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; val 807 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) val 809 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; val 815 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) val 817 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; val 823 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) val 825 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; val 831 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) val 833 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; val 839 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) val 841 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; val 849 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) val 851 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; val 859 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val) val 861 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK; val 865 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) val 867 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; val 873 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) val 875 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; val 881 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) val 883 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; val 891 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) val 893 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; val 897 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) val 899 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; val 905 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) val 907 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; val 911 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) val 913 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; val 919 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) val 921 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; val 927 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) val 929 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; val 935 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) val 937 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK; val 941 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) val 943 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK; val 949 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) val 951 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK; val 957 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) val 959 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK; val 965 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) val 967 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK; val 973 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) val 975 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK; val 981 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val) val 983 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK; val 989 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val) val 991 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK; val 997 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) val 999 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; val 1003 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) val 1005 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; val 1013 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) val 1015 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; val 1021 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val) val 1023 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK; val 1029 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val) val 1031 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK; val 1035 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val) val 1037 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK; val 1045 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val) val 1047 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK; val 1053 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val) val 1055 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK; val 1067 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) val 1069 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK; val 1077 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val) val 1079 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK; val 1085 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val) val 1087 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK; val 1093 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val) val 1095 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK; val 1101 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) val 1103 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK; val 1109 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val) val 1111 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK; val 1117 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) val 1119 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; val 1127 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) val 1129 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK; val 1135 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) val 1137 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK; val 1143 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val) val 1145 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK; val 1151 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val) val 1153 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK; val 1159 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) val 1161 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK; val 1167 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) val 1169 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK; val 1175 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) val 1177 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK; val 1185 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) val 1187 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; val 1193 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) val 1195 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; val 1201 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) val 1203 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; val 1209 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) val 1211 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; val 1217 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) val 1219 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; val 1225 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) val 1227 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; val 1239 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) val 1241 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; val 1247 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) val 1249 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; val 1255 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) val 1257 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; val 1263 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) val 1265 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK; val 1271 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) val 1273 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK; val 1281 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) val 1283 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK; val 1291 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) val 1293 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK; val 1299 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) val 1301 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK; val 1311 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) val 1313 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK; val 1319 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) val 1321 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK; val 1327 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) val 1329 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; val 1336 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) val 1338 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; val 1344 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) val 1346 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; val 1354 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) val 1356 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; val 1362 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) val 1364 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; val 1368 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) val 1370 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; val 1376 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) val 1378 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; val 1382 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) val 1384 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; val 1390 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) val 1392 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; val 1396 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) val 1398 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; val 1404 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) val 1406 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; val 1410 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) val 1412 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; val 1420 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val) val 1422 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK; val 1428 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) val 1430 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK; val 1436 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) val 1438 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK; val 1447 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) val 1449 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK; val 1455 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) val 1457 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK; val 1461 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) val 1463 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK; val 1467 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) val 1469 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; val 1476 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) val 1478 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; val 1484 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) val 1486 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; val 1492 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) val 1494 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; val 1498 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) val 1500 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; val 1504 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) val 1506 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; val 1512 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val) val 1514 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK; val 1518 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val) val 1520 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK; val 1529 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) val 1531 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK; val 1537 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) val 1539 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK; val 1545 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) val 1547 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK; val 1553 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val) val 1555 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK; val 1559 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val) val 1561 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK; val 86 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c u32 val; val 94 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c val, (val & 0xffff) >= 1, 10, timeout_us); val 138 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c u32 val; val 144 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL); val 145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c info->rd_ptr_init_val = val & 0xffff; val 147 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c val = DPU_REG_READ(c, PP_INT_COUNT_VAL); val 148 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; val 149 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c info->rd_ptr_line_count = val & 0xffff; val 151 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c val = DPU_REG_READ(c, PP_LINE_COUNT); val 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c info->wr_ptr_line_count = val & 0xffff; val 64 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c u32 val, val 70 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c name, c->blk_off + reg_off, val); val 71 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c writel_relaxed(val, c->base_off + c->blk_off + reg_off); val 314 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c u32 val; val 317 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = ((data->csc_mv[0] >> matrix_shift) & 0x1FFF) | val 319 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off, val); val 320 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = ((data->csc_mv[2] >> matrix_shift) & 0x1FFF) | val 322 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x4, val); val 323 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = ((data->csc_mv[4] >> matrix_shift) & 0x1FFF) | val 325 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x8, val); val 326 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = ((data->csc_mv[6] >> matrix_shift) & 0x1FFF) | val 328 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0xc, val); val 329 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = (data->csc_mv[8] >> matrix_shift) & 0x1FFF; val 330 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x10, val); val 333 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = (data->csc_pre_lv[0] << clamp_shift) | data->csc_pre_lv[1]; val 334 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x14, val); val 335 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = (data->csc_pre_lv[2] << clamp_shift) | data->csc_pre_lv[3]; val 336 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x18, val); val 337 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = (data->csc_pre_lv[4] << clamp_shift) | data->csc_pre_lv[5]; val 338 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x1c, val); val 341 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = (data->csc_post_lv[0] << clamp_shift) | data->csc_post_lv[1]; val 342 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x20, val); val 343 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = (data->csc_post_lv[2] << clamp_shift) | data->csc_post_lv[3]; val 344 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x24, val); val 345 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c val = (data->csc_post_lv[4] << clamp_shift) | data->csc_post_lv[5]; val 346 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x28, val); val 302 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h u32 val, val 306 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) val 308 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, int val), val 309 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_ARGS(drm_id, val), val 312 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( int, val ) val 316 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __entry->val = val; val 318 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val) val 106 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c u32 val; val 129 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c val = vbif->ops.get_limit_conf(vbif, val 131 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c if (val == ot_lim) val 113 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) val 115 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; val 119 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) val 121 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; val 141 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) val 143 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; val 147 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) val 149 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; val 153 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) val 155 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; val 183 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) val 185 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; val 190 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) val 192 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; val 197 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) val 199 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; val 204 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) val 206 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; val 211 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) val 213 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; val 218 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) val 220 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; val 225 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) val 227 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; val 232 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) val 234 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; val 243 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) val 245 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; val 250 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) val 252 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; val 257 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) val 259 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; val 264 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) val 266 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; val 271 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) val 273 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; val 278 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) val 280 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; val 285 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) val 287 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; val 292 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) val 294 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; val 326 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) val 328 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK; val 332 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) val 334 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK; val 358 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) val 360 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; val 366 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) val 368 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; val 461 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) val 463 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; val 467 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) val 469 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; val 473 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) val 475 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; val 480 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) val 482 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK; val 490 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) val 492 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK; val 496 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) val 498 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK; val 508 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) val 510 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK; val 514 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) val 516 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK; val 522 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) val 524 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK; val 528 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) val 530 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK; val 538 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) val 540 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK; val 544 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) val 546 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK; val 553 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) val 555 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK; val 595 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) val 597 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK; val 601 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) val 603 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK; val 609 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) val 611 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK; val 615 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) val 617 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK; val 623 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) val 625 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK; val 629 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) val 631 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK; val 637 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) val 639 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK; val 643 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) val 645 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK; val 659 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) val 661 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK; val 665 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) val 667 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK; val 673 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) val 675 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK; val 679 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) val 681 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; val 687 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) val 689 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK; val 693 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) val 695 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK; val 701 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) val 703 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; val 707 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) val 709 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; val 713 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) val 715 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; val 719 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) val 721 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; val 726 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) val 728 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK; val 733 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) val 735 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; val 741 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) val 743 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK; val 748 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) val 750 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; val 754 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) val 756 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK; val 762 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) val 764 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK; val 768 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) val 770 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK; val 774 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) val 776 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK; val 780 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) val 782 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK; val 790 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) val 792 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK; val 796 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) val 798 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK; val 848 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) val 850 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK; val 854 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) val 856 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK; val 866 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) val 868 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK; val 872 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) val 874 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK; val 884 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) val 886 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK; val 890 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) val 892 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK; val 905 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) val 907 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK; val 943 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) val 945 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK; val 949 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) val 951 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK; val 955 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) val 957 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK; val 961 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) val 963 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK; val 969 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) val 971 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK; val 975 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) val 977 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK; val 981 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) val 983 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK; val 1022 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) val 1024 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK; val 1028 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) val 1030 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK; val 1040 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) val 1042 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK; val 1046 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) val 1048 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK; val 1058 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) val 1060 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK; val 1064 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) val 1066 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK; val 1079 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) val 1081 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK; val 1101 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) val 1103 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK; val 1107 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) val 1109 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK; val 1119 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) val 1121 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK; val 1125 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) val 1127 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK; val 1137 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) val 1139 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK; val 1143 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) val 1145 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK; val 1158 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) val 1160 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK; val 114 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c static void unref_cursor_worker(struct drm_flip_work *work, void *val) val 121 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c msm_gem_unpin_iova(val, kms->aspace); val 122 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c drm_gem_object_put_unlocked(val); val 28 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c uint32_t val; val 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); val 76 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct drm_property *property, uint64_t val) val 180 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) val 182 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK; val 186 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) val 188 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK; val 192 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) val 194 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK; val 207 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) val 209 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK; val 213 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) val 215 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK; val 219 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) val 221 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK; val 227 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) val 229 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK; val 233 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) val 235 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK; val 239 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) val 241 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK; val 245 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) val 247 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK; val 270 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val) val 272 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK; val 276 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val) val 278 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK; val 282 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val) val 284 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK; val 292 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val) val 294 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK; val 298 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val) val 300 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK; val 304 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val) val 306 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK; val 326 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val) val 328 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK; val 379 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val) val 381 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK; val 385 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val) val 387 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK; val 391 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val) val 393 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK; val 397 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val) val 399 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK; val 403 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val) val 405 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK; val 409 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val) val 411 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK; val 415 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val) val 417 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK; val 421 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val) val 423 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK; val 429 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val) val 431 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK; val 435 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val) val 437 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK; val 443 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val) val 445 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK; val 449 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val) val 451 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK; val 457 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val) val 459 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK; val 524 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val) val 526 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK; val 530 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val) val 532 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK; val 559 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val) val 561 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK; val 565 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val) val 567 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK; val 580 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val) val 582 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK; val 586 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val) val 588 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK; val 594 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val) val 596 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK; val 600 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val) val 602 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK; val 608 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val) val 610 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK; val 614 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val) val 616 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK; val 622 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val) val 624 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK; val 628 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val) val 630 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK; val 636 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val) val 638 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK; val 646 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val) val 648 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK; val 652 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val) val 654 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK; val 662 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val) val 664 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK; val 668 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val) val 670 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK; val 678 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val) val 680 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK; val 688 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val) val 690 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK; val 696 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val) val 698 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK; val 702 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val) val 704 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK; val 710 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val) val 712 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK; val 716 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val) val 718 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK; val 724 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val) val 726 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK; val 730 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val) val 732 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK; val 738 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val) val 740 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK; val 744 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val) val 746 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK; val 752 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val) val 754 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK; val 758 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val) val 760 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK; val 774 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val) val 776 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK; val 780 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val) val 782 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK; val 788 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val) val 790 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK; val 794 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val) val 796 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK; val 804 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) val 806 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK; val 810 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) val 812 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK; val 816 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) val 818 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK; val 822 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) val 824 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK; val 829 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val) val 831 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK; val 836 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) val 838 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; val 844 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val) val 846 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK; val 850 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) val 852 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; val 858 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val) val 860 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK; val 864 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val) val 866 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK; val 870 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val) val 872 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK; val 876 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val) val 878 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK; val 885 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val) val 887 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK; val 923 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val) val 925 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK; val 929 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val) val 931 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK; val 948 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val) val 950 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK; val 954 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val) val 956 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK; val 960 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val) val 962 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK; val 966 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val) val 968 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK; val 974 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val) val 976 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK; val 980 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val) val 982 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK; val 986 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val) val 988 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK; val 992 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val) val 994 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK; val 1000 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val) val 1002 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK; val 1006 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val) val 1008 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK; val 1016 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val) val 1018 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK; val 1022 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val) val 1024 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK; val 1028 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val) val 1030 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK; val 1034 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val) val 1036 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK; val 1040 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val) val 1042 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK; val 1046 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val) val 1048 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK; val 1090 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val) val 1092 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK; val 1096 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val) val 1098 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK; val 1123 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val) val 1125 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK; val 1133 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val) val 1135 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK; val 1165 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val) val 1167 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK; val 1171 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val) val 1173 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK; val 1179 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val) val 1181 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK; val 1185 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val) val 1187 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK; val 1193 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val) val 1195 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK; val 1199 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val) val 1201 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK; val 1207 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val) val 1209 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK; val 1215 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val) val 1217 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK; val 1225 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val) val 1227 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK; val 1231 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val) val 1233 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK; val 1240 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val) val 1242 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK; val 1274 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val) val 1276 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK; val 1320 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val) val 1322 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK; val 1332 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val) val 1334 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK; val 1338 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val) val 1340 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK; val 1348 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val) val 1350 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK; val 1354 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val) val 1356 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK; val 1362 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val) val 1364 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK; val 1368 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val) val 1370 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK; val 1409 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val) val 1411 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK; val 1415 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val) val 1417 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK; val 1421 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val) val 1423 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK; val 1427 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val) val 1429 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK; val 1434 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val) val 1436 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK; val 1440 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val) val 1442 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK; val 1449 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val) val 1451 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK; val 1456 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val) val 1458 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK; val 1462 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val) val 1464 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK; val 1468 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val) val 1470 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK; val 1477 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val) val 1479 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK; val 1483 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val) val 1485 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK; val 1489 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val) val 1491 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK; val 1497 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val) val 1499 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK; val 1503 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val) val 1505 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK; val 1510 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val) val 1512 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK; val 1516 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val) val 1518 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK; val 1522 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val) val 1524 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK; val 1530 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val) val 1532 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK; val 1536 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val) val 1538 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK; val 1542 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val) val 1544 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK; val 1548 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val) val 1550 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK; val 1564 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val) val 1566 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK; val 1570 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val) val 1572 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK; val 1578 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val) val 1580 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK; val 1584 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val) val 1586 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK; val 1614 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val) val 1616 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK; val 1620 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val) val 1622 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK; val 1630 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val) val 1632 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK; val 1636 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val) val 1638 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK; val 1644 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val) val 1646 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK; val 1650 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val) val 1652 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK; val 1658 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val) val 1660 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK; val 1664 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val) val 1666 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK; val 1672 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val) val 1674 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK; val 1678 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val) val 1680 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK; val 1686 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val) val 1688 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK; val 1696 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val) val 1698 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK; val 1702 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val) val 1704 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK; val 1712 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val) val 1714 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK; val 1718 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val) val 1720 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK; val 1728 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val) val 1730 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK; val 1738 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val) val 1740 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK; val 1763 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val) val 1765 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK; val 1769 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val) val 1771 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK; val 1793 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val) val 1795 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK; val 1802 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val) val 1804 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK; val 1814 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val) val 1816 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK; val 1820 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val) val 1822 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK; val 1828 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val) val 1830 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK; val 1834 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val) val 1836 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK; val 161 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c static void unref_cursor_worker(struct drm_flip_work *work, void *val) val 168 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c msm_gem_unpin_iova(val, kms->aspace); val 169 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c drm_gem_object_put_unlocked(val); val 232 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c u32 val; val 347 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); val 349 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val | mixer_op_mode); val 351 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); val 353 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val | mixer_op_mode); val 370 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c u32 mixer_width, val; val 391 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); val 392 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; val 393 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val); val 403 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); val 404 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; val 405 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val); val 101 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint64_t val) val 112 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c pstate->name = (type)val; \ val 113 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c DBG("Set property %s %d", #name, (type)val); \ val 129 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct drm_property *property, uint64_t *val) val 140 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c *val = pstate->name; \ val 141 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c DBG("Get property %s %lld", #name, *val); \ val 100 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c u32 val; val 103 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c val = (nblks * smp_entries_per_blk) / 4; val 105 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c smp->pipe_reqprio_fifo_wm0[pipe] = val * 1; val 106 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c smp->pipe_reqprio_fifo_wm1[pipe] = val * 2; val 107 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c smp->pipe_reqprio_fifo_wm2[pipe] = val * 3; val 225 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c u32 blk, val; val 231 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c val = smp->alloc_w[idx]; val 235 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK; val 236 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c val |= MDP5_SMP_ALLOC_W_REG_CLIENT0(cid); val 239 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK; val 240 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c val |= MDP5_SMP_ALLOC_W_REG_CLIENT1(cid); val 243 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK; val 244 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c val |= MDP5_SMP_ALLOC_W_REG_CLIENT2(cid); val 248 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c smp->alloc_w[idx] = val; val 249 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c smp->alloc_r[idx] = val; val 113 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) val 115 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; val 119 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) val 121 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; val 125 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) val 127 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; val 156 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) val 158 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; val 162 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) val 164 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; val 168 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) val 170 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; val 185 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) val 187 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; val 193 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) val 195 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; val 199 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) val 201 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; val 207 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) val 209 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; val 213 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) val 215 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; val 221 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) val 223 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; val 227 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) val 229 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; val 235 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) val 237 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; val 241 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) val 243 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; val 249 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) val 251 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; val 255 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) val 257 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; val 263 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) val 265 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; val 269 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) val 271 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; val 282 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) val 284 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; val 291 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) val 293 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; val 297 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) val 299 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; val 305 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) val 307 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; val 311 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) val 313 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; val 324 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) val 326 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK; val 330 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) val 332 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK; val 336 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) val 338 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK; val 344 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) val 346 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; val 350 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) val 352 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; val 364 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) val 366 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; val 370 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) val 372 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; val 376 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) val 378 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; val 397 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) val 399 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; val 403 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) val 405 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; val 418 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) val 420 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; val 450 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) val 452 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; val 459 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) val 461 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; val 600 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) val 602 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; val 608 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) val 610 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; val 616 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) val 618 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; val 626 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) val 628 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; val 634 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) val 636 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; val 642 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) val 644 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; val 650 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) val 652 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; val 658 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) val 660 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; val 666 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) val 668 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; val 672 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) val 674 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; val 680 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) val 682 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; val 688 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) val 690 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; val 841 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) val 843 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; val 849 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) val 851 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; val 857 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) val 859 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; val 868 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) val 870 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; val 876 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) val 878 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; val 884 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) val 886 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; val 892 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) val 894 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; val 900 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) val 902 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; val 908 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) val 910 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; val 914 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) val 916 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; val 922 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) val 924 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; val 930 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) val 932 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; val 1017 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) val 1019 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; val 1026 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) val 1028 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; val 1032 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) val 1034 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; val 1040 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) val 1042 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; val 1048 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) val 1050 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; val 1168 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) val 1170 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; val 1176 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) val 1178 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; val 1184 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) val 1186 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; val 1195 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) val 1197 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; val 1203 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) val 1205 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; val 1211 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) val 1213 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; val 1219 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) val 1221 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; val 1227 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) val 1229 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; val 1235 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) val 1237 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; val 1241 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) val 1243 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; val 1249 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) val 1251 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK; val 1257 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) val 1259 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; val 1318 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) val 1320 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK; val 1324 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) val 1326 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK; val 1363 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) val 1365 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK; val 1373 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) val 1375 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK; val 1392 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) val 1394 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK; val 1400 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) val 1402 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK; val 1408 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) val 1410 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK; val 1416 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) val 1418 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK; val 1424 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) val 1426 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK; val 1432 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) val 1434 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK; val 1438 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) val 1440 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK; val 1446 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) val 1448 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK; val 1454 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) val 1456 drivers/gpu/drm/msm/dsi/dsi.xml.h return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK; val 72 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val) val 74 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK; val 78 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val) val 80 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK; val 86 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val) val 88 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK; val 92 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val) val 94 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK; val 100 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val) val 102 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK; val 106 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val) val 108 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK; val 112 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val) val 114 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK; val 158 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c s32 val, val_ckln; val 173 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c val = (hb_en << 2) + (pd << 1); val 196 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8); val 198 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = (85 * coeff + 6 * ui - val * ui) / ui_x8; val 202 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui; val 373 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c u32 val; val 378 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c val = dsi_phy_read(phy->base + reg); val 381 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_phy_write(phy->base + reg, val | bit_mask); val 383 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_phy_write(phy->base + reg, val & (~bit_mask)); val 561 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c u32 val; val 563 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); val 564 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val &= ~0x3; val 565 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val |= cached->pll_out_div; val 566 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); val 571 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); val 572 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val &= ~0x3; val 573 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val |= cached->pll_mux; val 574 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); val 181 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u32 tries, val; val 185 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + val 187 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_locked = !!(val & BIT(5)); val 198 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + val 200 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_locked = !!(val & BIT(0)); val 685 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u32 val; val 689 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; val 690 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val &= div_mask(width); val 692 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c return divider_recalc_rate(hw, parent_rate, val, NULL, val 721 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u32 val; val 731 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); val 732 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val &= ~(div_mask(width) << shift); val 734 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val |= value << shift; val 735 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); val 744 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); val 95 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c u32 val; val 98 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); val 99 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY); val 320 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c u32 val; val 331 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; val 332 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); val 334 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; val 335 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); val 337 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; val 338 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val 340 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; val 341 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); val 361 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; val 362 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); val 364 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; val 365 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); val 367 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; val 368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); val 370 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; val 371 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); val 373 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; val 374 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val 376 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; val 377 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); val 395 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c u32 val; val 407 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; val 408 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val 410 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; val 411 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val 413 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B | val 415 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val 90 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c u32 val; val 93 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); val 94 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY); val 115 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c u32 val, temp, fb_divider; val 120 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = VCO_REF_CLK_RATE / 10; val 121 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; val 126 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); val 128 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val |= (fb_divider >> 8) & 0x07; val 131 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val); val 133 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); val 135 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f; val 138 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val); val 143 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); val 144 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val |= 0x7 << 4; val 146 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val); val 265 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c u32 val; val 270 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(bytediv->reg); val 271 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val |= (factor - 1) & 0xff; val 272 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(bytediv->reg, val); val 295 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c u32 val; val 306 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); val 307 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c byte_div = val + 1; val 310 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); val 311 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val &= ~0xf; val 312 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val |= (bit_div - 1); val 313 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); val 57 drivers/gpu/drm/msm/dsi/sfpb.xml.h static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val) val 59 drivers/gpu/drm/msm/dsi/sfpb.xml.h return ((val) << SFPB_GPREG_MASTER_PORT_EN__SHIFT) & SFPB_GPREG_MASTER_PORT_EN__MASK; val 83 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_CONFIGURATION_CTRL_LANES(uint32_t val) val 85 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_CONFIGURATION_CTRL_LANES__SHIFT) & EDP_CONFIGURATION_CTRL_LANES__MASK; val 90 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val) val 92 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_CONFIGURATION_CTRL_COLOR__SHIFT) & EDP_CONFIGURATION_CTRL_COLOR__MASK; val 102 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_TOTAL_HOR_VER_HORIZ(uint32_t val) val 104 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_TOTAL_HOR_VER_HORIZ__SHIFT) & EDP_TOTAL_HOR_VER_HORIZ__MASK; val 108 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_TOTAL_HOR_VER_VERT(uint32_t val) val 110 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_TOTAL_HOR_VER_VERT__SHIFT) & EDP_TOTAL_HOR_VER_VERT__MASK; val 116 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val) val 118 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK; val 122 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_VERT(uint32_t val) val 124 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_VERT__MASK; val 130 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ(uint32_t val) val 132 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK; val 137 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT(uint32_t val) val 139 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK; val 146 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_ACTIVE_HOR_VER_HORIZ(uint32_t val) val 148 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_ACTIVE_HOR_VER_HORIZ__SHIFT) & EDP_ACTIVE_HOR_VER_HORIZ__MASK; val 152 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_ACTIVE_HOR_VER_VERT(uint32_t val) val 154 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_ACTIVE_HOR_VER_VERT__SHIFT) & EDP_ACTIVE_HOR_VER_VERT__MASK; val 160 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_MISC0(uint32_t val) val 162 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_MISC1_MISC0_MISC0__SHIFT) & EDP_MISC1_MISC0_MISC0__MASK; val 167 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_COMPONENT_FORMAT(enum edp_component_format val) val 169 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT) & EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK; val 175 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_COLOR(enum edp_color_depth val) val 177 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_MISC1_MISC0_COLOR__SHIFT) & EDP_MISC1_MISC0_COLOR__MASK; val 181 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_MISC1(uint32_t val) val 183 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_MISC1_MISC0_MISC1__SHIFT) & EDP_MISC1_MISC0_MISC1__MASK; val 188 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_STEREO(uint32_t val) val 190 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_MISC1_MISC0_STEREO__SHIFT) & EDP_MISC1_MISC0_STEREO__MASK; val 258 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val) val 260 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_AUX_DATA_DATA__SHIFT) & EDP_AUX_DATA_DATA__MASK; val 264 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val) val 266 drivers/gpu/drm/msm/edp/edp.xml.h return ((val) << EDP_AUX_DATA_INDEX__SHIFT) & EDP_AUX_DATA_INDEX__MASK; val 85 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) val 87 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK; val 92 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) val 94 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK; val 117 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val) val 119 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK; val 123 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val) val 125 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK; val 129 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val) val 131 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK; val 135 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val) val 137 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK; val 145 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) val 147 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK; val 153 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) val 155 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK; val 159 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) val 161 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK; val 186 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) val 188 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK; val 194 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACR_1_N(uint32_t val) val 196 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK; val 202 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) val 204 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK; val 208 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) val 210 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK; val 216 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) val 218 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK; val 222 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) val 224 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK; val 257 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) val 259 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK; val 330 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) val 332 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK; val 344 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) val 346 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK; val 369 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) val 371 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK; val 375 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) val 377 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK; val 383 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) val 385 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK; val 393 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) val 395 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK; val 402 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) val 404 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK; val 410 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) val 412 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK; val 416 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) val 418 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK; val 422 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) val 424 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK; val 452 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) val 454 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK; val 462 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) val 464 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; val 494 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) val 496 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK; val 500 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) val 502 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK; val 508 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) val 510 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK; val 514 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) val 516 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK; val 522 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) val 524 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK; val 528 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) val 530 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK; val 536 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) val 538 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK; val 542 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) val 544 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK; val 550 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) val 552 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK; val 592 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) val 594 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK; val 600 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) val 602 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK; val 606 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) val 608 drivers/gpu/drm/msm/hdmi/hdmi.xml.h return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK; val 92 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c u32 val; val 138 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1); val 139 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK; val 140 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c val |= HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER); val 141 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val); val 23 drivers/gpu/drm/msm/hdmi/hdmi_connector.c unsigned int val; val 25 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); val 27 drivers/gpu/drm/msm/hdmi/hdmi_connector.c if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { val 30 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val & ~HDMI_PHY_CTRL_SW_RESET); val 34 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val | HDMI_PHY_CTRL_SW_RESET); val 37 drivers/gpu/drm/msm/hdmi/hdmi_connector.c if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { val 40 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val & ~HDMI_PHY_CTRL_SW_RESET_PLL); val 44 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val | HDMI_PHY_CTRL_SW_RESET_PLL); val 49 drivers/gpu/drm/msm/hdmi/hdmi_connector.c if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { val 52 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val | HDMI_PHY_CTRL_SW_RESET); val 56 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val & ~HDMI_PHY_CTRL_SW_RESET); val 59 drivers/gpu/drm/msm/hdmi/hdmi_connector.c if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { val 62 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val | HDMI_PHY_CTRL_SW_RESET_PLL); val 66 drivers/gpu/drm/msm/hdmi/hdmi_connector.c val & ~HDMI_PHY_CTRL_SW_RESET_PLL); val 174 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c scm_buf[i].val = pdata[idx]; val 34 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c u32 val; val 257 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c unsigned int val; val 276 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12); val 277 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val |= HDMI_8960_PHY_REG12_SW_RESET; val 279 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val); val 280 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val &= ~HDMI_8960_PHY_REG12_SW_RESET; val 288 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val); val 291 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12); val 292 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val |= HDMI_8960_PHY_REG12_PWRDN_B; val 293 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val); val 298 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); val 299 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val |= HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B; val 300 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val &= ~HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL; val 301 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); val 307 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_STATUS0); val 308 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c if (val & HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK) val 341 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c unsigned int val; val 345 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12); val 346 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val &= ~HDMI_8960_PHY_REG12_PWRDN_B; val 347 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val); val 349 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); val 350 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val |= HDMI_8960_PHY_REG12_SW_RESET; val 351 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val &= ~HDMI_8960_PHY_REG12_PWRDN_B; val 352 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); val 394 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); val 162 drivers/gpu/drm/msm/msm_drv.c u32 val = readl(addr); val 164 drivers/gpu/drm/msm/msm_drv.c pr_err("IO:R %p %08x\n", addr, val); val 165 drivers/gpu/drm/msm/msm_drv.c return val; val 443 drivers/gpu/drm/msm/msm_drv.h #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) val 446 drivers/gpu/drm/msm/msm_drv.h #define COND(bool, val) ((bool) ? (val) : 0) val 226 drivers/gpu/drm/msm/msm_gpu.h uint32_t val = gpu_read(gpu, reg); val 228 drivers/gpu/drm/msm/msm_gpu.h val &= ~mask; val 229 drivers/gpu/drm/msm/msm_gpu.h gpu_write(gpu, reg, val | or); val 234 drivers/gpu/drm/msm/msm_gpu.h u64 val; val 250 drivers/gpu/drm/msm/msm_gpu.h val = (u64) msm_readl(gpu->mmio + (lo << 2)); val 251 drivers/gpu/drm/msm/msm_gpu.h val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); val 253 drivers/gpu/drm/msm/msm_gpu.h return val; val 256 drivers/gpu/drm/msm/msm_gpu.h static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) val 259 drivers/gpu/drm/msm/msm_gpu.h msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2)); val 260 drivers/gpu/drm/msm/msm_gpu.h msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); val 82 drivers/gpu/drm/msm/msm_perf.c uint32_t val; val 95 drivers/gpu/drm/msm/msm_perf.c val = totaltime ? 1000 * activetime / totaltime : 0; val 96 drivers/gpu/drm/msm/msm_perf.c n = snprintf(ptr, rem, "%3d.%d%%", val / 10, val % 10); val 102 drivers/gpu/drm/msm/msm_perf.c val = cntrs[i] / 10000; val 104 drivers/gpu/drm/msm/msm_perf.c val / 100, val % 100); val 180 drivers/gpu/drm/msm/msm_rd.c uint64_t val; val 197 drivers/gpu/drm/msm/msm_rd.c gpu->funcs->get_param(gpu, MSM_PARAM_GPU_ID, &val); val 198 drivers/gpu/drm/msm/msm_rd.c gpu_id = val; val 39 drivers/gpu/drm/mxsfb/mxsfb_crtc.c static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val) val 41 drivers/gpu/drm/mxsfb/mxsfb_crtc.c return (val & mxsfb->devdata->hs_wdth_mask) << val 63 drivers/gpu/drm/nouveau/dispnv04/hw.h uint32_t val; val 66 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd32(device, reg); val 67 drivers/gpu/drm/nouveau/dispnv04/hw.h return val; val 71 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg, uint32_t val) val 76 drivers/gpu/drm/nouveau/dispnv04/hw.h nvif_wr32(device, reg, val); val 83 drivers/gpu/drm/nouveau/dispnv04/hw.h uint32_t val; val 86 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd32(device, reg); val 87 drivers/gpu/drm/nouveau/dispnv04/hw.h return val; val 91 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg, uint32_t val) val 96 drivers/gpu/drm/nouveau/dispnv04/hw.h nvif_wr32(device, reg, val); val 131 drivers/gpu/drm/nouveau/dispnv04/hw.h uint8_t val; val 133 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); val 134 drivers/gpu/drm/nouveau/dispnv04/hw.h return val; val 169 drivers/gpu/drm/nouveau/dispnv04/hw.h uint8_t val; val 176 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd08(device, reg); val 177 drivers/gpu/drm/nouveau/dispnv04/hw.h return val; val 226 drivers/gpu/drm/nouveau/dispnv04/hw.h uint8_t val; val 234 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE); val 235 drivers/gpu/drm/nouveau/dispnv04/hw.h return val; val 689 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c uint64_t val) val 698 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->overscan = val; val 710 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->saturation = val; val 717 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->hue = val; val 724 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->flicker = val; val 732 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->tv_norm = val; val 740 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->select_subconnector = val; val 131 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t val) val 134 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h nvif_wr32(&device->object, reg, val); val 144 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint8_t val) val 147 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h nv_write_ptv(dev, NV_PTV_TV_DATA, val); val 112 drivers/gpu/drm/nouveau/dispnv50/base907c.c u32 *val = &asyw->csc.matrix[j * 4 + i]; val 116 drivers/gpu/drm/nouveau/dispnv50/base907c.c *val = 0; val 118 drivers/gpu/drm/nouveau/dispnv50/base907c.c *val = csc_drm_to_base(ctm->matrix[j * 3 + i]); val 106 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val) val 110 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h return nvkm_mask(device, falcon->addr + addr, mask, val); val 100 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h u8 val; val 103 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = &val }, val 110 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h return val; val 116 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h u8 val[2]; val 119 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h { .addr = addr, .flags = I2C_M_RD, .len = 2, .buf = val }, val 126 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h return val[0] << 8 | val[1]; val 130 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h nvkm_wri2cr(struct i2c_adapter *adap, u8 addr, u8 reg, u8 val) val 132 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h u8 buf[2] = { reg, val }; val 145 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h nv_wr16i2cr(struct i2c_adapter *adap, u8 addr, u8 reg, u16 val) val 147 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h u8 buf[3] = { reg, val >> 8, val & 0xff}; val 71 drivers/gpu/drm/nouveau/nouveau_backlight.c int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & val 74 drivers/gpu/drm/nouveau/nouveau_backlight.c return val; val 83 drivers/gpu/drm/nouveau/nouveau_backlight.c int val = bd->props.brightness; val 87 drivers/gpu/drm/nouveau/nouveau_backlight.c (val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK)); val 123 drivers/gpu/drm/nouveau/nouveau_backlight.c u32 val; val 125 drivers/gpu/drm/nouveau/nouveau_backlight.c val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); val 126 drivers/gpu/drm/nouveau/nouveau_backlight.c val &= NV50_PDISP_SOR_PWM_CTL_VAL; val 127 drivers/gpu/drm/nouveau/nouveau_backlight.c return ((val * 100) + (div / 2)) / div; val 138 drivers/gpu/drm/nouveau/nouveau_backlight.c u32 val = (bd->props.brightness * div) / 100; val 141 drivers/gpu/drm/nouveau/nouveau_backlight.c NV50_PDISP_SOR_PWM_CTL_NEW | val); val 158 drivers/gpu/drm/nouveau/nouveau_backlight.c u32 div, val; val 161 drivers/gpu/drm/nouveau/nouveau_backlight.c val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); val 162 drivers/gpu/drm/nouveau/nouveau_backlight.c val &= NVA3_PDISP_SOR_PWM_CTL_VAL; val 163 drivers/gpu/drm/nouveau/nouveau_backlight.c if (div && div >= val) val 164 drivers/gpu/drm/nouveau/nouveau_backlight.c return ((val * 100) + (div / 2)) / div; val 176 drivers/gpu/drm/nouveau/nouveau_backlight.c u32 div, val; val 179 drivers/gpu/drm/nouveau/nouveau_backlight.c val = (bd->props.brightness * div) / 100; val 182 drivers/gpu/drm/nouveau/nouveau_backlight.c val | val 594 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) val 602 drivers/gpu/drm/nouveau/nouveau_bo.c iowrite16_native(val, (void __force __iomem *)mem); val 604 drivers/gpu/drm/nouveau/nouveau_bo.c *mem = val; val 622 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) val 630 drivers/gpu/drm/nouveau/nouveau_bo.c iowrite32_native(val, (void __force __iomem *)mem); val 632 drivers/gpu/drm/nouveau/nouveau_bo.c *mem = val; val 87 drivers/gpu/drm/nouveau/nouveau_bo.h void nouveau_bo_wr16(struct nouveau_bo *, unsigned index, u16 val); val 89 drivers/gpu/drm/nouveau/nouveau_bo.h void nouveau_bo_wr32(struct nouveau_bo *, unsigned index, u32 val); val 100 drivers/gpu/drm/nouveau/nouveau_connector.c struct drm_property *property, u64 *val) val 107 drivers/gpu/drm/nouveau/nouveau_connector.c *val = asyc->scaler.mode; val 109 drivers/gpu/drm/nouveau/nouveau_connector.c *val = asyc->scaler.underscan.mode; val 111 drivers/gpu/drm/nouveau/nouveau_connector.c *val = asyc->scaler.underscan.hborder; val 113 drivers/gpu/drm/nouveau/nouveau_connector.c *val = asyc->scaler.underscan.vborder; val 115 drivers/gpu/drm/nouveau/nouveau_connector.c *val = asyc->dither.mode; val 117 drivers/gpu/drm/nouveau/nouveau_connector.c *val = asyc->dither.depth; val 119 drivers/gpu/drm/nouveau/nouveau_connector.c *val = asyc->procamp.vibrant_hue; val 121 drivers/gpu/drm/nouveau/nouveau_connector.c *val = asyc->procamp.color_vibrance; val 131 drivers/gpu/drm/nouveau/nouveau_connector.c struct drm_property *property, u64 val) val 138 drivers/gpu/drm/nouveau/nouveau_connector.c switch (val) { val 168 drivers/gpu/drm/nouveau/nouveau_connector.c if (asyc->scaler.mode != val) { val 169 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->scaler.mode = val; val 174 drivers/gpu/drm/nouveau/nouveau_connector.c if (asyc->scaler.underscan.mode != val) { val 175 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->scaler.underscan.mode = val; val 180 drivers/gpu/drm/nouveau/nouveau_connector.c if (asyc->scaler.underscan.hborder != val) { val 181 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->scaler.underscan.hborder = val; val 186 drivers/gpu/drm/nouveau/nouveau_connector.c if (asyc->scaler.underscan.vborder != val) { val 187 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->scaler.underscan.vborder = val; val 192 drivers/gpu/drm/nouveau/nouveau_connector.c if (asyc->dither.mode != val) { val 193 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->dither.mode = val; val 198 drivers/gpu/drm/nouveau/nouveau_connector.c if (asyc->dither.mode != val) { val 199 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->dither.depth = val; val 204 drivers/gpu/drm/nouveau/nouveau_connector.c if (asyc->procamp.vibrant_hue != val) { val 205 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->procamp.vibrant_hue = val; val 210 drivers/gpu/drm/nouveau/nouveau_connector.c if (asyc->procamp.color_vibrance != val) { val 211 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->procamp.color_vibrance = val; val 364 drivers/gpu/drm/nouveau/nouveau_display.c nouveau_display_acpi_ntfy(struct notifier_block *nb, unsigned long val, val 56 drivers/gpu/drm/nouveau/nouveau_dma.c uint64_t val; val 58 drivers/gpu/drm/nouveau/nouveau_dma.c val = nvif_rd32(&chan->user, chan->user_get); val 60 drivers/gpu/drm/nouveau/nouveau_dma.c val |= (uint64_t)nvif_rd32(&chan->user, chan->user_get_hi) << 32; val 66 drivers/gpu/drm/nouveau/nouveau_dma.c if (val != *prev_get) { val 67 drivers/gpu/drm/nouveau/nouveau_dma.c *prev_get = val; val 77 drivers/gpu/drm/nouveau/nouveau_dma.c if (val < chan->push.addr || val 78 drivers/gpu/drm/nouveau/nouveau_dma.c val > chan->push.addr + (chan->dma.max << 2)) val 81 drivers/gpu/drm/nouveau/nouveau_dma.c return (val - chan->push.addr) >> 2; val 138 drivers/gpu/drm/nouveau/nouveau_dma.h #define WRITE_PUT(val) do { \ val 141 drivers/gpu/drm/nouveau/nouveau_dma.h nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.addr);\ val 403 drivers/gpu/drm/nouveau/nouveau_hwmon.c nouveau_chip_read(struct device *dev, u32 attr, int channel, long *val) val 407 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = 1000; val 417 drivers/gpu/drm/nouveau/nouveau_hwmon.c nouveau_temp_read(struct device *dev, u32 attr, int channel, long *val) val 432 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = ret < 0 ? ret : (ret * 1000); val 435 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK) val 439 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST) val 443 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL) val 447 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST) val 451 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN) val 455 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST) val 466 drivers/gpu/drm/nouveau/nouveau_hwmon.c nouveau_fan_read(struct device *dev, u32 attr, int channel, long *val) val 479 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = nvkm_therm_fan_sense(therm); val 489 drivers/gpu/drm/nouveau/nouveau_hwmon.c nouveau_in_read(struct device *dev, u32 attr, int channel, long *val) val 504 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = ret < 0 ? ret : (ret / 1000); val 507 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = volt->min_uv > 0 ? (volt->min_uv / 1000) : -ENODEV; val 510 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = volt->max_uv > 0 ? (volt->max_uv / 1000) : -ENODEV; val 520 drivers/gpu/drm/nouveau/nouveau_hwmon.c nouveau_pwm_read(struct device *dev, u32 attr, int channel, long *val) val 531 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MODE); val 536 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = therm->fan_get(therm); val 546 drivers/gpu/drm/nouveau/nouveau_hwmon.c nouveau_power_read(struct device *dev, u32 attr, int channel, long *val) val 559 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = nvkm_iccsense_read_all(iccsense); val 562 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = iccsense->power_w_max; val 565 drivers/gpu/drm/nouveau/nouveau_hwmon.c *val = iccsense->power_w_crit; val 575 drivers/gpu/drm/nouveau/nouveau_hwmon.c nouveau_temp_write(struct device *dev, u32 attr, int channel, long val) val 587 drivers/gpu/drm/nouveau/nouveau_hwmon.c val / 1000); val 590 drivers/gpu/drm/nouveau/nouveau_hwmon.c val / 1000); val 593 drivers/gpu/drm/nouveau/nouveau_hwmon.c val / 1000); val 596 drivers/gpu/drm/nouveau/nouveau_hwmon.c val / 1000); val 599 drivers/gpu/drm/nouveau/nouveau_hwmon.c val / 1000); val 602 drivers/gpu/drm/nouveau/nouveau_hwmon.c val / 1000); val 609 drivers/gpu/drm/nouveau/nouveau_hwmon.c nouveau_pwm_write(struct device *dev, u32 attr, int channel, long val) val 620 drivers/gpu/drm/nouveau/nouveau_hwmon.c return therm->fan_set(therm, val); val 622 drivers/gpu/drm/nouveau/nouveau_hwmon.c return therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MODE, val); val 666 drivers/gpu/drm/nouveau/nouveau_hwmon.c int channel, long *val) val 670 drivers/gpu/drm/nouveau/nouveau_hwmon.c return nouveau_chip_read(dev, attr, channel, val); val 672 drivers/gpu/drm/nouveau/nouveau_hwmon.c return nouveau_temp_read(dev, attr, channel, val); val 674 drivers/gpu/drm/nouveau/nouveau_hwmon.c return nouveau_fan_read(dev, attr, channel, val); val 676 drivers/gpu/drm/nouveau/nouveau_hwmon.c return nouveau_in_read(dev, attr, channel, val); val 678 drivers/gpu/drm/nouveau/nouveau_hwmon.c return nouveau_pwm_read(dev, attr, channel, val); val 680 drivers/gpu/drm/nouveau/nouveau_hwmon.c return nouveau_power_read(dev, attr, channel, val); val 688 drivers/gpu/drm/nouveau/nouveau_hwmon.c int channel, long val) val 692 drivers/gpu/drm/nouveau/nouveau_hwmon.c return nouveau_temp_write(dev, attr, channel, val); val 694 drivers/gpu/drm/nouveau/nouveau_hwmon.c return nouveau_pwm_write(dev, attr, channel, val); val 30 drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) val 37 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h cp_lsr(struct nvkm_grctx *ctx, u32 val) val 39 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h cp_out(ctx, CP_LOAD_SR | val); val 121 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val) val 129 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h nvkm_wo32(ctx->data, reg * 4, val); val 785 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c dd_emit(struct nvkm_grctx *ctx, int num, u32 val) { val 787 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c if (val && ctx->mode == NVKM_GRCTX_VALS) { val 789 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); val 1158 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c xf_emit(struct nvkm_grctx *ctx, int num, u32 val) { val 1160 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c if (val && ctx->mode == NVKM_GRCTX_VALS) { val 1162 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); val 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c u32 val; val 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c val = nvkm_rd32(device, 0x100c80); val 45 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c val &= 0xf000187f; val 46 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c nvkm_wr32(device, 0x418880, val); val 989 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c #define NV_WRITE_CTX(reg, val) do { \ val 992 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chan->nv10[offset] = val; \ val 995 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c #define NV17_WRITE_CTX(reg, val) do { \ val 998 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chan->nv17[offset] = val; \ val 218 drivers/gpu/drm/nouveau/nvkm/falcon/base.c u32 val = nvkm_falcon_rd32(falcon, debug_reg); val 219 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->debug = (val >> 20) & 0x1; val 192 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(struct nvbios_init *init, u32 reg, u32 val) val 197 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c nvkm_wr32(device, reg, val); val 201 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) val 207 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c nvkm_wr32(device, reg, (tmp & ~mask) | val); val 294 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) val 298 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return nvkm_wri2cr(adap, addr, reg, val); val 486 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 val = nvbios_rd32(bios, table + (cond * 12) + 8); val 488 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c cond, reg, msk, val); val 489 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return (init_rd32(init, reg) & msk) == val; val 1016 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c int val; val 1021 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c val = init_rdi2cr(init, index, addr, reg); val 1022 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (val < 0) val 1024 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wri2cr(init, index, addr, reg, (val & mask) | data); val 1182 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 val; val 1187 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c val = init_rdvgai(init, 0x03d4, addr) & mask; val 1188 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wrvgai(init, 0x03d4, addr, val | data); val 68 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c u32 val; val 70 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val = nvkm_rd32(device, GPCPLL_COEFF); val 71 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); val 72 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); val 73 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); val 80 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c u32 val; val 82 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; val 83 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; val 84 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; val 85 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_wr32(device, GPCPLL_COEFF, val); val 259 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c u32 val; val 265 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val = nvkm_rd32(device, GPCPLL_CFG); val 266 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c if (val & GPCPLL_CFG_LOCK_DET_OFF) { val 267 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val &= ~GPCPLL_CFG_LOCK_DET_OFF; val 268 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_wr32(device, GPCPLL_CFG, val); val 136 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h u32 val; val 138 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h val = nvkm_rd32(device, GPCPLL_CFG); val 139 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h return val & GPCPLL_CFG_ENABLE; val 164 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c u32 val; val 167 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c val = nvkm_rd32(device, GPCPLL_CFG2); val 168 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) & val 534 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c u32 val; val 540 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c val = nvkm_rd32(device, GPCPLL_DVFS1); val 541 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (!(val & BIT(25))) { val 543 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c val |= BIT(25) | BIT(16); val 544 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_wr32(device, GPCPLL_DVFS1, val); val 948 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c u32 val = 0; val 952 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c tegra_fuse_readl(FUSE_RESERVED_CALIB0, &val); val 953 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c rev = (val >> FUSE_RESERVED_CALIB0_FUSE_REV_SHIFT) & val 962 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c clk->uvdet_slope = ((val >> FUSE_RESERVED_CALIB0_SLOPE_INT_SHIFT) & val 964 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c ((val >> FUSE_RESERVED_CALIB0_SLOPE_FRAC_SHIFT) & val 968 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c clk->uvdet_offs = ((val >> FUSE_RESERVED_CALIB0_INTERCEPT_INT_SHIFT) & val 970 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c ((val >> FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_SHIFT) & val 64 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h u32 val = ioread32(p + (off & ~PAGE_MASK)); val 66 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h return val; val 70 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h fbmem_poke(struct io_mapping *fb, u32 off, u32 val) val 73 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h iowrite32(val, p + (off & ~PAGE_MASK)); val 79 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h fbmem_readback(struct io_mapping *fb, u32 off, u32 val) val 81 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h fbmem_poke(fb, off, val); val 82 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h return val == fbmem_peek(fb, off); val 466 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gt215_ram_gpio(struct gt215_ramfuc *fuc, u8 tag, u32 val) val 473 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) { val 482 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c val = !val; val 484 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c val = !val; val 486 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_mask(fuc, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); val 192 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_gpio(struct nv50_ramseq *hwsq, u8 tag, u32 val) val 199 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) { val 209 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c val = !val; val 211 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c val = !val; val 213 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); val 31 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c u32 fuse_enable, unk, val; val 37 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c val = nvkm_rd32(device, 0x021100 + addr); val 41 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c return val; val 31 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c u32 fuse_enable, val; val 36 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c val = nvkm_rd32(device, 0x021000 + addr); val 39 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c return val; val 43 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c u32 val = (unk1 << 16) | unk0; val 53 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c nvkm_mask(device, reg, 0x00010001 << lsh, val << lsh); val 40 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c u8 val = nvkm_rdvgac(device, 0, bus->drive); val 41 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c if (state) val |= 0x20; val 42 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c else val &= 0xdf; val 43 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c nvkm_wrvgac(device, 0, bus->drive, val | 0x01); val 51 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c u8 val = nvkm_rdvgac(device, 0, bus->drive); val 52 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c if (state) val |= 0x10; val 53 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c else val &= 0xef; val 54 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c nvkm_wrvgac(device, 0, bus->drive, val | 0x01); val 53 drivers/gpu/drm/omapdrm/dss/dispc.c #define REG_FLD_MOD(dispc, idx, val, start, end) \ val 55 drivers/gpu/drm/omapdrm/dss/dispc.c FLD_MOD(dispc_read_reg(dispc, idx), val, start, end)) val 358 drivers/gpu/drm/omapdrm/dss/dispc.c static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) val 360 drivers/gpu/drm/omapdrm/dss/dispc.c __raw_writel(val, dispc->base + idx); val 377 drivers/gpu/drm/omapdrm/dss/dispc.c enum mgr_reg_fields regfld, int val) val 385 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); val 388 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); val 962 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 967 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); val 969 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); val 976 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); val 979 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); val 981 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); val 988 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 992 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); val 995 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); val 997 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); val 1150 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1167 drivers/gpu/drm/omapdrm/dss/dispc.c val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); val 1200 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_MOD(val, chan, shift, shift); val 1201 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_MOD(val, chan2, 31, 30); val 1203 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_MOD(val, channel, shift, shift); val 1205 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); val 1212 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1228 drivers/gpu/drm/omapdrm/dss/dispc.c val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); val 1230 drivers/gpu/drm/omapdrm/dss/dispc.c if (FLD_GET(val, shift, shift) == 1) val 1236 drivers/gpu/drm/omapdrm/dss/dispc.c switch (FLD_GET(val, 31, 30)) { val 1335 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1339 drivers/gpu/drm/omapdrm/dss/dispc.c val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); val 1340 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_MOD(val, enable, 9, 9); val 1341 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); val 1362 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1364 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | val 1367 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); val 1643 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1652 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(vinc, vinc_start, vinc_end) | val 1655 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); val 1657 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); val 1658 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); val 1666 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1674 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(vaccu, vert_start, vert_end) | val 1677 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); val 1684 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1692 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(vaccu, vert_start, vert_end) | val 1695 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); val 1702 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1704 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); val 1705 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); val 1712 drivers/gpu/drm/omapdrm/dss/dispc.c u32 val; val 1714 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); val 1715 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); val 2149 drivers/gpu/drm/omapdrm/dss/dispc.c u64 val, blank; val 2175 drivers/gpu/drm/omapdrm/dss/dispc.c val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); val 2177 drivers/gpu/drm/omapdrm/dss/dispc.c val, max(0, ds - 2) * width); val 2178 drivers/gpu/drm/omapdrm/dss/dispc.c if (val < max(0, ds - 2) * width) val 2186 drivers/gpu/drm/omapdrm/dss/dispc.c val = div_u64((u64)nonactive * lclk, pclk); val 2188 drivers/gpu/drm/omapdrm/dss/dispc.c val, max(0, ds - 1) * width); val 2189 drivers/gpu/drm/omapdrm/dss/dispc.c if (val < max(0, ds - 1) * width) val 3186 drivers/gpu/drm/omapdrm/dss/dispc.c u32 mask, val; val 3189 drivers/gpu/drm/omapdrm/dss/dispc.c val = (rf << 0) | (ipc << 3) | (onoff << 6); val 3192 drivers/gpu/drm/omapdrm/dss/dispc.c val <<= 16 + shifts[channel]; val 3195 drivers/gpu/drm/omapdrm/dss/dispc.c mask, val); val 114 drivers/gpu/drm/omapdrm/dss/dsi.c #define REG_FLD_MOD(dsi, idx, val, start, end) \ val 115 drivers/gpu/drm/omapdrm/dss/dsi.c dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end)) val 436 drivers/gpu/drm/omapdrm/dss/dsi.c const struct dsi_reg idx, u32 val) val 447 drivers/gpu/drm/omapdrm/dss/dsi.c __raw_writel(val, base + idx.idx); val 1649 drivers/gpu/drm/omapdrm/dss/dsi.c int val; val 1658 drivers/gpu/drm/omapdrm/dss/dsi.c val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ val 1660 drivers/gpu/drm/omapdrm/dss/dsi.c switch (val) { val 2448 drivers/gpu/drm/omapdrm/dss/dsi.c u32 val; val 2449 drivers/gpu/drm/omapdrm/dss/dsi.c val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); val 2451 drivers/gpu/drm/omapdrm/dss/dsi.c (val >> 0) & 0xff, val 2452 drivers/gpu/drm/omapdrm/dss/dsi.c (val >> 8) & 0xff, val 2453 drivers/gpu/drm/omapdrm/dss/dsi.c (val >> 16) & 0xff, val 2454 drivers/gpu/drm/omapdrm/dss/dsi.c (val >> 24) & 0xff); val 2499 drivers/gpu/drm/omapdrm/dss/dsi.c u32 val; val 2501 drivers/gpu/drm/omapdrm/dss/dsi.c val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); val 2502 drivers/gpu/drm/omapdrm/dss/dsi.c DSSERR("\trawval %#08x\n", val); val 2503 drivers/gpu/drm/omapdrm/dss/dsi.c dt = FLD_GET(val, 5, 0); val 2505 drivers/gpu/drm/omapdrm/dss/dsi.c u16 err = FLD_GET(val, 23, 8); val 2509 drivers/gpu/drm/omapdrm/dss/dsi.c FLD_GET(val, 23, 8)); val 2512 drivers/gpu/drm/omapdrm/dss/dsi.c FLD_GET(val, 23, 8)); val 2515 drivers/gpu/drm/omapdrm/dss/dsi.c FLD_GET(val, 23, 8)); val 2592 drivers/gpu/drm/omapdrm/dss/dsi.c u32 val; val 2599 drivers/gpu/drm/omapdrm/dss/dsi.c val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | val 2602 drivers/gpu/drm/omapdrm/dss/dsi.c dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val); val 2608 drivers/gpu/drm/omapdrm/dss/dsi.c u32 val; val 2610 drivers/gpu/drm/omapdrm/dss/dsi.c val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; val 2615 drivers/gpu/drm/omapdrm/dss/dsi.c dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); val 2865 drivers/gpu/drm/omapdrm/dss/dsi.c u32 val; val 2876 drivers/gpu/drm/omapdrm/dss/dsi.c val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); val 2878 drivers/gpu/drm/omapdrm/dss/dsi.c DSSDBG("\theader: %08x\n", val); val 2879 drivers/gpu/drm/omapdrm/dss/dsi.c dt = FLD_GET(val, 5, 0); val 2881 drivers/gpu/drm/omapdrm/dss/dsi.c u16 err = FLD_GET(val, 23, 8); val 2889 drivers/gpu/drm/omapdrm/dss/dsi.c u8 data = FLD_GET(val, 15, 8); val 2906 drivers/gpu/drm/omapdrm/dss/dsi.c u16 data = FLD_GET(val, 23, 8); val 2925 drivers/gpu/drm/omapdrm/dss/dsi.c int len = FLD_GET(val, 23, 8); val 2939 drivers/gpu/drm/omapdrm/dss/dsi.c val = dsi_read_reg(dsi, val 2943 drivers/gpu/drm/omapdrm/dss/dsi.c (val >> 0) & 0xff, val 2944 drivers/gpu/drm/omapdrm/dss/dsi.c (val >> 8) & 0xff, val 2945 drivers/gpu/drm/omapdrm/dss/dsi.c (val >> 16) & 0xff, val 2946 drivers/gpu/drm/omapdrm/dss/dsi.c (val >> 24) & 0xff); val 2950 drivers/gpu/drm/omapdrm/dss/dsi.c buf[w] = (val >> (b * 8)) & 0xff; val 57 drivers/gpu/drm/omapdrm/dss/dss.c #define REG_FLD_MOD(dss, idx, val, start, end) \ val 59 drivers/gpu/drm/omapdrm/dss/dss.c FLD_MOD(dss_read_reg(dss, idx), val, start, end)) val 95 drivers/gpu/drm/omapdrm/dss/dss.c const struct dss_reg idx, u32 val) val 97 drivers/gpu/drm/omapdrm/dss/dss.c __raw_writel(val, dss->base + idx.idx); val 149 drivers/gpu/drm/omapdrm/dss/dss.c unsigned int val; val 154 drivers/gpu/drm/omapdrm/dss/dss.c val = !enable; val 173 drivers/gpu/drm/omapdrm/dss/dss.c 1 << shift, val << shift); val 180 drivers/gpu/drm/omapdrm/dss/dss.c unsigned int shift, val; val 191 drivers/gpu/drm/omapdrm/dss/dss.c val = 0; break; val 193 drivers/gpu/drm/omapdrm/dss/dss.c val = 1; break; val 205 drivers/gpu/drm/omapdrm/dss/dss.c val = 0; break; val 207 drivers/gpu/drm/omapdrm/dss/dss.c val = 1; break; val 209 drivers/gpu/drm/omapdrm/dss/dss.c val = 2; break; val 221 drivers/gpu/drm/omapdrm/dss/dss.c val = 0; break; val 223 drivers/gpu/drm/omapdrm/dss/dss.c val = 1; break; val 225 drivers/gpu/drm/omapdrm/dss/dss.c val = 2; break; val 238 drivers/gpu/drm/omapdrm/dss/dss.c 0x3 << shift, val << shift); val 748 drivers/gpu/drm/omapdrm/dss/dss.c int val; val 752 drivers/gpu/drm/omapdrm/dss/dss.c val = 0; val 755 drivers/gpu/drm/omapdrm/dss/dss.c val = 1; val 761 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17); val 769 drivers/gpu/drm/omapdrm/dss/dss.c int val; val 773 drivers/gpu/drm/omapdrm/dss/dss.c val = 1; val 776 drivers/gpu/drm/omapdrm/dss/dss.c val = 2; val 779 drivers/gpu/drm/omapdrm/dss/dss.c val = 3; val 782 drivers/gpu/drm/omapdrm/dss/dss.c val = 0; val 788 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16); val 65 drivers/gpu/drm/omapdrm/dss/dss.h #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) val 66 drivers/gpu/drm/omapdrm/dss/dss.h #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) val 67 drivers/gpu/drm/omapdrm/dss/dss.h #define FLD_MOD(orig, val, start, end) \ val 68 drivers/gpu/drm/omapdrm/dss/dss.h (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) val 266 drivers/gpu/drm/omapdrm/dss/hdmi.h u32 val) val 268 drivers/gpu/drm/omapdrm/dss/hdmi.h __raw_writel(val, base_addr + idx); val 276 drivers/gpu/drm/omapdrm/dss/hdmi.h #define REG_FLD_MOD(base, idx, val, start, end) \ val 278 drivers/gpu/drm/omapdrm/dss/hdmi.h val, start, end)) val 283 drivers/gpu/drm/omapdrm/dss/hdmi.h const u32 idx, int b2, int b1, u32 val) val 286 drivers/gpu/drm/omapdrm/dss/hdmi.h while (val != (v = REG_GET(base_addr, idx, b2, b1))) { val 302 drivers/gpu/drm/omapdrm/dss/hdmi.h int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); val 303 drivers/gpu/drm/omapdrm/dss/hdmi.h int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); val 646 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c u8 val; val 677 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c val = 1; val 679 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c val = 0; val 682 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); val 683 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); val 684 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); val 685 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); val 688 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c val = 1; val 689 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); val 690 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); val 698 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA; val 699 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); val 702 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c val = (cfg->iec60958_cfg->status[0] & val 704 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); val 711 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6; val 712 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); val 715 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE; val 716 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); val 67 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val) val 70 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) val 74 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); val 77 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) val 78 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c != val) { val 79 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c DSSERR("Failed to set PHY power mode to %d\n", val); val 87 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val) val 90 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); val 93 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) val 94 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c != val) { val 310 drivers/gpu/drm/omapdrm/dss/venc.c static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val) val 312 drivers/gpu/drm/omapdrm/dss/venc.c __raw_writel(val, venc->base + idx); val 25 drivers/gpu/drm/omapdrm/dss/video-pll.c #define REG_MOD(reg, val, start, end) \ val 26 drivers/gpu/drm/omapdrm/dss/video-pll.c writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg) val 655 drivers/gpu/drm/omapdrm/omap_crtc.c u64 val) val 671 drivers/gpu/drm/omapdrm/omap_crtc.c plane_state->rotation = val; val 673 drivers/gpu/drm/omapdrm/omap_crtc.c plane_state->zpos = val; val 683 drivers/gpu/drm/omapdrm/omap_crtc.c u64 *val) val 689 drivers/gpu/drm/omapdrm/omap_crtc.c *val = omap_state->rotation; val 691 drivers/gpu/drm/omapdrm/omap_crtc.c *val = omap_state->zpos; val 134 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static void dmm_write_wa(struct dmm *dmm, u32 val, u32 reg) val 139 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c writel(val, dmm->wa_dma_data); val 154 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c writel(val, dmm->base + reg); val 174 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static void dmm_write(struct dmm *dmm, u32 val, u32 reg) val 180 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dmm_write_wa(dmm, val, reg); val 183 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c writel(val, dmm->base + reg); val 197 drivers/gpu/drm/omapdrm/omap_plane.c u64 val) val 202 drivers/gpu/drm/omapdrm/omap_plane.c state->zpos = val; val 212 drivers/gpu/drm/omapdrm/omap_plane.c u64 *val) val 217 drivers/gpu/drm/omapdrm/omap_plane.c *val = state->zpos; val 297 drivers/gpu/drm/panel/panel-arm-versatile.c u32 val; val 315 drivers/gpu/drm/panel/panel-arm-versatile.c ret = regmap_read(map, SYS_CLCD, &val); val 321 drivers/gpu/drm/panel/panel-arm-versatile.c val &= SYS_CLCD_CLCDID_MASK; val 327 drivers/gpu/drm/panel/panel-arm-versatile.c if (pt->magic == val) { val 306 drivers/gpu/drm/panel/panel-ilitek-ili9322.c size_t reg_size, void *val, size_t val_size) val 318 drivers/gpu/drm/panel/panel-ilitek-ili9322.c return spi_write_then_read(spi, buf, 1, val, 1); val 733 drivers/gpu/drm/panel/panel-ilitek-ili9322.c u32 val; val 755 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val = ili->conf->vreg1out_mv; val 756 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (!val) { val 760 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val < 3600) { val 764 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val > 6000) { val 768 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if ((val % 100) != 0) { val 772 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val -= 3600; val 773 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val /= 100; val 774 drivers/gpu/drm/panel/panel-ilitek-ili9322.c dev_dbg(dev, "VREG1OUT = 0x%02x\n", val); val 775 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ili->vreg1out = val; val 778 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val = ili->conf->vcom_high_percent; val 779 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (!val) { val 783 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val < 37) { val 787 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val > 100) { val 791 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val -= 37; val 792 drivers/gpu/drm/panel/panel-ilitek-ili9322.c dev_dbg(dev, "VCOM high = 0x%02x\n", val); val 793 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ili->vcom_high = val; val 796 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val = ili->conf->vcom_amplitude_percent; val 797 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (!val) { val 801 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val < 70) { val 805 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val > 132) { val 809 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val -= 70; val 810 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val >>= 1; /* Increments of 2% */ val 811 drivers/gpu/drm/panel/panel-ilitek-ili9322.c dev_dbg(dev, "VCOM amplitude = 0x%02x\n", val); val 812 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ili->vcom_amplitude = val; val 816 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val = ili->conf->gamma_corr_neg[i]; val 817 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val > 15) { val 818 drivers/gpu/drm/panel/panel-ilitek-ili9322.c dev_err(dev, "negative gamma %u > 15, capping\n", val); val 819 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val = 15; val 821 drivers/gpu/drm/panel/panel-ilitek-ili9322.c gamma = val << 4; val 822 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val = ili->conf->gamma_corr_pos[i]; val 823 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val > 15) { val 824 drivers/gpu/drm/panel/panel-ilitek-ili9322.c dev_err(dev, "positive gamma %u > 15, capping\n", val); val 825 drivers/gpu/drm/panel/panel-ilitek-ili9322.c val = 15; val 827 drivers/gpu/drm/panel/panel-ilitek-ili9322.c gamma |= val; val 872 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ret = regmap_read(ili->regmap, ILI9322_CHIP_ID, &val); val 877 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (val != ILI9322_CHIP_ID_MAGIC) { val 878 drivers/gpu/drm/panel/panel-ilitek-ili9322.c dev_err(dev, "chip ID 0x%0x2, expected 0x%02x\n", val, val 885 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ret = regmap_read(ili->regmap, ILI9322_ENTRY, &val); val 891 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ili->input = (val >> 4) & 0x0f; val 32 drivers/gpu/drm/panel/panel-lg-lb035q02.c static int lb035q02_write(struct lb035q02_device *lcd, u16 reg, u16 val) val 55 drivers/gpu/drm/panel/panel-lg-lb035q02.c buffer[5] = val >> 8; val 56 drivers/gpu/drm/panel/panel-lg-lb035q02.c buffer[6] = val; val 229 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c u8 reg, u8 val) val 233 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c ret = i2c_smbus_write_byte_data(ts->i2c, reg, val); val 238 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c static int rpi_touchscreen_write(struct rpi_touchscreen *ts, u16 reg, u32 val) val 243 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c val, val 244 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c val >> 8, val 245 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c val >> 16, val 246 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c val >> 24, val 264 drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c static int allpixelson_set(void *data, u64 val) val 271 drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c msleep(val * 1000); val 109 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_TEST(val, func) \ val 111 drivers/gpu/drm/panel/panel-sitronix-st7789v.c if ((val = (func))) \ val 112 drivers/gpu/drm/panel/panel-sitronix-st7789v.c return val; \ val 103 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c u8 val; val 106 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c for (val = i = 0; i < 4; i++) val 107 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c val |= (gamma[i] & 0x300) >> ((i + 1) * 2); val 108 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c td043mtea1_write(lcd, 0x11, val); val 110 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c for (val = i = 0; i < 4; i++) val 111 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c val |= (gamma[i + 4] & 0x300) >> ((i + 1) * 2); val 112 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c td043mtea1_write(lcd, 0x12, val); val 114 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c for (val = i = 0; i < 4; i++) val 115 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c val |= (gamma[i + 8] & 0x300) >> ((i + 1) * 2); val 116 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c td043mtea1_write(lcd, 0x13, val); val 196 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c int val; val 199 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c ret = kstrtoint(buf, 0, &val); val 203 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c lcd->vmirror = !!val; val 224 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c long val; val 227 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c ret = kstrtol(buf, 0, &val); val 228 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c if (ret != 0 || val & ~7) val 231 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c lcd->mode = val; val 233 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c val |= TPO_R02_NCLK_RISING; val 234 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c td043mtea1_write(lcd, 2, val); val 271 drivers/gpu/drm/panel/panel-tpo-tpg110.c u8 val; val 281 drivers/gpu/drm/panel/panel-tpo-tpg110.c val = tpg110_read_reg(tpg, TPG110_TEST); val 282 drivers/gpu/drm/panel/panel-tpo-tpg110.c if (val != 0x55) { val 287 drivers/gpu/drm/panel/panel-tpo-tpg110.c val = tpg110_read_reg(tpg, TPG110_CHIPID); val 289 drivers/gpu/drm/panel/panel-tpo-tpg110.c val >> 4, val & 0x0f); val 292 drivers/gpu/drm/panel/panel-tpo-tpg110.c val = tpg110_read_reg(tpg, TPG110_CTRL1); val 293 drivers/gpu/drm/panel/panel-tpo-tpg110.c val &= TPG110_RES_MASK; val 294 drivers/gpu/drm/panel/panel-tpo-tpg110.c switch (val) { val 316 drivers/gpu/drm/panel/panel-tpo-tpg110.c DRM_DEV_ERROR(tpg->dev, "ILLEGAL RESOLUTION 0x%02x\n", val); val 321 drivers/gpu/drm/panel/panel-tpo-tpg110.c if (val == TPG110_RES_480X272_D) val 322 drivers/gpu/drm/panel/panel-tpo-tpg110.c val = TPG110_RES_480X272; val 328 drivers/gpu/drm/panel/panel-tpo-tpg110.c if (pm->magic == val) { val 335 drivers/gpu/drm/panel/panel-tpo-tpg110.c val); val 339 drivers/gpu/drm/panel/panel-tpo-tpg110.c val = tpg110_read_reg(tpg, TPG110_CTRL2); val 341 drivers/gpu/drm/panel/panel-tpo-tpg110.c (val & TPG110_CTRL2_RES_PM_CTRL) ? "software" : "hardware"); val 343 drivers/gpu/drm/panel/panel-tpo-tpg110.c val |= TPG110_CTRL2_RES_PM_CTRL; val 344 drivers/gpu/drm/panel/panel-tpo-tpg110.c tpg110_write_reg(tpg, TPG110_CTRL2, val); val 352 drivers/gpu/drm/panel/panel-tpo-tpg110.c u8 val; val 355 drivers/gpu/drm/panel/panel-tpo-tpg110.c val = tpg110_read_reg(tpg, TPG110_CTRL2_PM); val 356 drivers/gpu/drm/panel/panel-tpo-tpg110.c val &= ~TPG110_CTRL2_PM; val 357 drivers/gpu/drm/panel/panel-tpo-tpg110.c tpg110_write_reg(tpg, TPG110_CTRL2_PM, val); val 367 drivers/gpu/drm/panel/panel-tpo-tpg110.c u8 val; val 372 drivers/gpu/drm/panel/panel-tpo-tpg110.c val = tpg110_read_reg(tpg, TPG110_CTRL2_PM); val 373 drivers/gpu/drm/panel/panel-tpo-tpg110.c val |= TPG110_CTRL2_PM; val 374 drivers/gpu/drm/panel/panel-tpo-tpg110.c tpg110_write_reg(tpg, TPG110_CTRL2_PM, val); val 58 drivers/gpu/drm/panfrost/panfrost_gpu.c u32 val; val 65 drivers/gpu/drm/panfrost/panfrost_gpu.c val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); val 305 drivers/gpu/drm/panfrost/panfrost_gpu.c u32 val; val 310 drivers/gpu/drm/panfrost/panfrost_gpu.c val, val == pfdev->features.l2_present, 100, 1000); val 314 drivers/gpu/drm/panfrost/panfrost_gpu.c val, val == pfdev->features.stack_present, 100, 1000); val 318 drivers/gpu/drm/panfrost/panfrost_gpu.c val, val == pfdev->features.shader_present, 100, 1000); val 322 drivers/gpu/drm/panfrost/panfrost_gpu.c val, val == pfdev->features.tiler_present, 100, 1000); val 29 drivers/gpu/drm/panfrost/panfrost_mmu.c u32 val; val 34 drivers/gpu/drm/panfrost/panfrost_mmu.c val, !(val & AS_STATUS_AS_ACTIVE), 10, 1000); val 97 drivers/gpu/drm/pl111/pl111_versatile.c u32 val; val 102 drivers/gpu/drm/pl111/pl111_versatile.c val = INTEGRATOR_CLCD_LCD_STATIC1 | INTEGRATOR_CLCD_LCD_STATIC2 | val 109 drivers/gpu/drm/pl111/pl111_versatile.c val |= INTEGRATOR_CLCD_LCDMUX_VGA24; val 114 drivers/gpu/drm/pl111/pl111_versatile.c val |= INTEGRATOR_CLCD_LCDMUX_VGA555; val 125 drivers/gpu/drm/pl111/pl111_versatile.c val); val 156 drivers/gpu/drm/pl111/pl111_versatile.c u32 val = 0; val 165 drivers/gpu/drm/pl111/pl111_versatile.c val |= SYS_CLCD_MODE_888; val 168 drivers/gpu/drm/pl111/pl111_versatile.c val |= SYS_CLCD_MODE_565_R_LSB; val 171 drivers/gpu/drm/pl111/pl111_versatile.c val |= SYS_CLCD_MODE_565_B_LSB; val 177 drivers/gpu/drm/pl111/pl111_versatile.c val |= SYS_CLCD_MODE_5551; val 189 drivers/gpu/drm/pl111/pl111_versatile.c val); val 35 drivers/gpu/drm/pl111/pl111_vexpress.c u32 val; val 78 drivers/gpu/drm/pl111/pl111_vexpress.c val = VEXPRESS_FPGAMUX_MOTHERBOARD; val 82 drivers/gpu/drm/pl111/pl111_vexpress.c val = VEXPRESS_FPGAMUX_DAUGHTERBOARD_1; val 89 drivers/gpu/drm/pl111/pl111_vexpress.c ret = regmap_write(map, 0, val); val 287 drivers/gpu/drm/qxl/qxl_cmd.c static int wait_for_io_cmd_user(struct qxl_device *qdev, uint8_t val, long port, bool intr) val 307 drivers/gpu/drm/qxl/qxl_cmd.c outb(val, addr); val 322 drivers/gpu/drm/qxl/qxl_cmd.c static void wait_for_io_cmd(struct qxl_device *qdev, uint8_t val, long port) val 327 drivers/gpu/drm/qxl/qxl_cmd.c ret = wait_for_io_cmd_user(qdev, val, port, false); val 407 drivers/gpu/drm/r128/r128_drv.h #define R128_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) val 409 drivers/gpu/drm/r128/r128_drv.h #define R128_WRITE8(reg, val) writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) val 411 drivers/gpu/drm/r128/r128_drv.h #define R128_WRITE_PLL(addr, val) \ val 415 drivers/gpu/drm/r128/r128_drv.h R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ val 185 drivers/gpu/drm/radeon/atom.c uint32_t idx, val = 0xCDCDCDCD, align, arg; val 198 drivers/gpu/drm/radeon/atom.c val = gctx->card->reg_read(gctx->card, idx); val 216 drivers/gpu/drm/radeon/atom.c val = val 227 drivers/gpu/drm/radeon/atom.c val = get_unaligned_le32((u32 *)&ctx->ps[idx]); val 229 drivers/gpu/drm/radeon/atom.c DEBUG("PS[0x%02X,0x%04X]", idx, val); val 238 drivers/gpu/drm/radeon/atom.c val = gctx->divmul[0]; val 241 drivers/gpu/drm/radeon/atom.c val = gctx->divmul[1]; val 244 drivers/gpu/drm/radeon/atom.c val = gctx->data_block; val 247 drivers/gpu/drm/radeon/atom.c val = gctx->shift; val 250 drivers/gpu/drm/radeon/atom.c val = 1 << gctx->shift; val 253 drivers/gpu/drm/radeon/atom.c val = ~(1 << gctx->shift); val 256 drivers/gpu/drm/radeon/atom.c val = gctx->fb_base; val 259 drivers/gpu/drm/radeon/atom.c val = gctx->io_attr; val 262 drivers/gpu/drm/radeon/atom.c val = gctx->reg_block; val 265 drivers/gpu/drm/radeon/atom.c val = ctx->ws[idx]; val 277 drivers/gpu/drm/radeon/atom.c val = U32(idx + gctx->data_block); val 285 drivers/gpu/drm/radeon/atom.c val = 0; val 287 drivers/gpu/drm/radeon/atom.c val = gctx->scratch[(gctx->fb_base / 4) + idx]; val 294 drivers/gpu/drm/radeon/atom.c val = U32(*ptr); val 297 drivers/gpu/drm/radeon/atom.c DEBUG("IMM 0x%08X\n", val); val 298 drivers/gpu/drm/radeon/atom.c return val; val 302 drivers/gpu/drm/radeon/atom.c val = U16(*ptr); val 305 drivers/gpu/drm/radeon/atom.c DEBUG("IMM 0x%04X\n", val); val 306 drivers/gpu/drm/radeon/atom.c return val; val 311 drivers/gpu/drm/radeon/atom.c val = U8(*ptr); val 314 drivers/gpu/drm/radeon/atom.c DEBUG("IMM 0x%02X\n", val); val 315 drivers/gpu/drm/radeon/atom.c return val; val 323 drivers/gpu/drm/radeon/atom.c val = gctx->card->pll_read(gctx->card, idx); val 330 drivers/gpu/drm/radeon/atom.c val = gctx->card->mc_read(gctx->card, idx); val 334 drivers/gpu/drm/radeon/atom.c *saved = val; val 335 drivers/gpu/drm/radeon/atom.c val &= atom_arg_mask[align]; val 336 drivers/gpu/drm/radeon/atom.c val >>= atom_arg_shift[align]; val 340 drivers/gpu/drm/radeon/atom.c DEBUG(".[31:0] -> 0x%08X\n", val); val 343 drivers/gpu/drm/radeon/atom.c DEBUG(".[15:0] -> 0x%04X\n", val); val 346 drivers/gpu/drm/radeon/atom.c DEBUG(".[23:8] -> 0x%04X\n", val); val 349 drivers/gpu/drm/radeon/atom.c DEBUG(".[31:16] -> 0x%04X\n", val); val 352 drivers/gpu/drm/radeon/atom.c DEBUG(".[7:0] -> 0x%02X\n", val); val 355 drivers/gpu/drm/radeon/atom.c DEBUG(".[15:8] -> 0x%02X\n", val); val 358 drivers/gpu/drm/radeon/atom.c DEBUG(".[23:16] -> 0x%02X\n", val); val 361 drivers/gpu/drm/radeon/atom.c DEBUG(".[31:24] -> 0x%02X\n", val); val 364 drivers/gpu/drm/radeon/atom.c return val; val 410 drivers/gpu/drm/radeon/atom.c uint32_t val = 0xCDCDCDCD; val 414 drivers/gpu/drm/radeon/atom.c val = U32(*ptr); val 420 drivers/gpu/drm/radeon/atom.c val = U16(*ptr); val 427 drivers/gpu/drm/radeon/atom.c val = U8(*ptr); val 431 drivers/gpu/drm/radeon/atom.c return val; val 451 drivers/gpu/drm/radeon/atom.c int *ptr, uint32_t val, uint32_t saved) val 455 drivers/gpu/drm/radeon/atom.c val, idx; val 458 drivers/gpu/drm/radeon/atom.c val <<= atom_arg_shift[align]; val 459 drivers/gpu/drm/radeon/atom.c val &= atom_arg_mask[align]; val 461 drivers/gpu/drm/radeon/atom.c val |= saved; val 472 drivers/gpu/drm/radeon/atom.c val << 2); val 474 drivers/gpu/drm/radeon/atom.c gctx->card->reg_write(gctx->card, idx, val); val 493 drivers/gpu/drm/radeon/atom.c idx, val); val 500 drivers/gpu/drm/radeon/atom.c ctx->ps[idx] = cpu_to_le32(val); val 508 drivers/gpu/drm/radeon/atom.c gctx->divmul[0] = val; val 511 drivers/gpu/drm/radeon/atom.c gctx->divmul[1] = val; val 514 drivers/gpu/drm/radeon/atom.c gctx->data_block = val; val 517 drivers/gpu/drm/radeon/atom.c gctx->shift = val; val 523 drivers/gpu/drm/radeon/atom.c gctx->fb_base = val; val 526 drivers/gpu/drm/radeon/atom.c gctx->io_attr = val; val 529 drivers/gpu/drm/radeon/atom.c gctx->reg_block = val; val 532 drivers/gpu/drm/radeon/atom.c ctx->ws[idx] = val; val 542 drivers/gpu/drm/radeon/atom.c gctx->scratch[(gctx->fb_base / 4) + idx] = val; val 549 drivers/gpu/drm/radeon/atom.c gctx->card->pll_write(gctx->card, idx, val); val 555 drivers/gpu/drm/radeon/atom.c gctx->card->mc_write(gctx->card, idx, val); val 814 drivers/gpu/drm/radeon/atom.c uint8_t val = U8((*ptr)++); val 815 drivers/gpu/drm/radeon/atom.c SDEBUG("POST card output: 0x%02X\n", val); val 975 drivers/gpu/drm/radeon/atom.c uint32_t src, val, target; val 982 drivers/gpu/drm/radeon/atom.c val = val 986 drivers/gpu/drm/radeon/atom.c if (val == src) { val 1770 drivers/gpu/drm/radeon/btc_dpm.c u32 val; val 1775 drivers/gpu/drm/radeon/btc_dpm.c val = (arb_registers->mc_arb_rfsh_rate & POWERMODE0_MASK) >> val 1777 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK); val 1779 drivers/gpu/drm/radeon/btc_dpm.c val = (arb_registers->mc_arb_burst_time & STATE0_MASK) >> val 1781 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK); val 1813 drivers/gpu/drm/radeon/btc_dpm.c u32 val; val 1821 drivers/gpu/drm/radeon/btc_dpm.c val = rv770_calculate_memory_refresh_rate(rdev, ulv_pl->sclk); val 1822 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK); val 1824 drivers/gpu/drm/radeon/btc_dpm.c val = cypress_calculate_burst_time(rdev, ulv_pl->sclk, ulv_pl->mclk); val 1825 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK); val 163 drivers/gpu/drm/radeon/cik.c u32 reg, u32 *val) val 178 drivers/gpu/drm/radeon/cik.c *val = RREG32(reg); val 1097 drivers/gpu/drm/radeon/evergreen.c u32 reg, u32 *val) val 1107 drivers/gpu/drm/radeon/evergreen.c *val = RREG32(reg); val 322 drivers/gpu/drm/radeon/evergreen_hdmi.c uint32_t val; val 324 drivers/gpu/drm/radeon/evergreen_hdmi.c val = RREG32(HDMI_CONTROL + offset); val 325 drivers/gpu/drm/radeon/evergreen_hdmi.c val &= ~HDMI_DEEP_COLOR_ENABLE; val 326 drivers/gpu/drm/radeon/evergreen_hdmi.c val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; val 338 drivers/gpu/drm/radeon/evergreen_hdmi.c val |= HDMI_DEEP_COLOR_ENABLE; val 339 drivers/gpu/drm/radeon/evergreen_hdmi.c val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); val 344 drivers/gpu/drm/radeon/evergreen_hdmi.c val |= HDMI_DEEP_COLOR_ENABLE; val 345 drivers/gpu/drm/radeon/evergreen_hdmi.c val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); val 351 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_CONTROL + offset, val); val 456 drivers/gpu/drm/radeon/evergreen_hdmi.c uint32_t val; val 466 drivers/gpu/drm/radeon/evergreen_hdmi.c val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); val 467 drivers/gpu/drm/radeon/evergreen_hdmi.c val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); val 470 drivers/gpu/drm/radeon/evergreen_hdmi.c val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); val 472 drivers/gpu/drm/radeon/evergreen_hdmi.c val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); val 474 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); val 862 drivers/gpu/drm/radeon/ni.c u32 reg, u32 *val) val 873 drivers/gpu/drm/radeon/ni.c *val = RREG32(reg); val 175 drivers/gpu/drm/radeon/r600.c u32 reg, u32 *val) val 183 drivers/gpu/drm/radeon/r600.c *val = RREG32(reg); val 1985 drivers/gpu/drm/radeon/r600.c int r600_count_pipe_bits(uint32_t val) val 1987 drivers/gpu/drm/radeon/r600.c return hweight32(val); val 1401 drivers/gpu/drm/radeon/r600_cs.c unsigned val; val 1403 drivers/gpu/drm/radeon/r600_cs.c val = max(1U, size >> level); val 1405 drivers/gpu/drm/radeon/r600_cs.c val = roundup_pow_of_two(val); val 1406 drivers/gpu/drm/radeon/r600_cs.c return val; val 1859 drivers/gpu/drm/radeon/radeon.h int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); val 2542 drivers/gpu/drm/radeon/radeon.h #define WREG32_P(reg, val, mask) \ val 2546 drivers/gpu/drm/radeon/radeon.h tmp_ |= ((val) & ~(mask)); \ val 2551 drivers/gpu/drm/radeon/radeon.h #define WREG32_PLL_P(reg, val, mask) \ val 2555 drivers/gpu/drm/radeon/radeon.h tmp_ |= ((val) & ~(mask)); \ val 2558 drivers/gpu/drm/radeon/radeon.h #define WREG32_SMC_P(reg, val, mask) \ val 2562 drivers/gpu/drm/radeon/radeon.h tmp_ |= ((val) & ~(mask)); \ val 681 drivers/gpu/drm/radeon/radeon_acpi.c unsigned long val, val 141 drivers/gpu/drm/radeon/radeon_asic.c u32 reg, u32 *val) val 376 drivers/gpu/drm/radeon/radeon_asic.h int r600_count_pipe_bits(uint32_t val); val 388 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); val 553 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); val 656 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); val 753 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); val 872 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); val 107 drivers/gpu/drm/radeon/radeon_clocks.c const u32 *val; val 115 drivers/gpu/drm/radeon/radeon_clocks.c val = of_get_property(dp, "ATY,RefCLK", NULL); val 116 drivers/gpu/drm/radeon/radeon_clocks.c if (!val || !*val) { val 120 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_freq = p2pll->reference_freq = (*val) / 10; val 154 drivers/gpu/drm/radeon/radeon_clocks.c val = of_get_property(dp, "ATY,SCLK", NULL); val 155 drivers/gpu/drm/radeon/radeon_clocks.c if (val && *val) val 156 drivers/gpu/drm/radeon/radeon_clocks.c rdev->clock.default_sclk = (*val) / 10; val 161 drivers/gpu/drm/radeon/radeon_clocks.c val = of_get_property(dp, "ATY,MCLK", NULL); val 162 drivers/gpu/drm/radeon/radeon_clocks.c if (val && *val) val 163 drivers/gpu/drm/radeon/radeon_clocks.c rdev->clock.default_mclk = (*val) / 10; val 2892 drivers/gpu/drm/radeon/radeon_combios.c uint32_t reg, val, and_mask, or_mask; val 2912 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS32(index); val 2914 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); val 2922 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32(reg); val 2923 drivers/gpu/drm/radeon/radeon_combios.c val = (val & and_mask) | or_mask; val 2924 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); val 2927 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS16(index); val 2929 drivers/gpu/drm/radeon/radeon_combios.c udelay(val); val 2932 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS16(index); val 2934 drivers/gpu/drm/radeon/radeon_combios.c mdelay(val); val 2942 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS8(index); val 2946 drivers/gpu/drm/radeon/radeon_combios.c reg, val); val 2967 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS32(index); val 2968 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); val 2976 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32(reg); val 2977 drivers/gpu/drm/radeon/radeon_combios.c val = (val & and_mask) | or_mask; val 2978 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); val 2981 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS16(index); val 2983 drivers/gpu/drm/radeon/radeon_combios.c udelay(val); val 2991 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32_PLL(reg); val 2992 drivers/gpu/drm/radeon/radeon_combios.c val = (val & and_mask) | or_mask; val 2993 drivers/gpu/drm/radeon/radeon_combios.c WREG32_PLL(reg, val); val 2997 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS8(index); val 3001 drivers/gpu/drm/radeon/radeon_combios.c reg, val); val 3023 drivers/gpu/drm/radeon/radeon_combios.c uint32_t val, and_mask, or_mask; val 3029 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS32(offset); val 3031 drivers/gpu/drm/radeon/radeon_combios.c WREG32(addr, val); val 3034 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS32(offset); val 3036 drivers/gpu/drm/radeon/radeon_combios.c WREG32(addr, val); val 3059 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS16(offset); val 3061 drivers/gpu/drm/radeon/radeon_combios.c udelay(val); val 3064 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS16(offset); val 3068 drivers/gpu/drm/radeon/radeon_combios.c while (val--) { val 3077 drivers/gpu/drm/radeon/radeon_combios.c while (val--) { val 3102 drivers/gpu/drm/radeon/radeon_combios.c uint32_t val, shift, tmp; val 3108 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS32(offset); val 3110 drivers/gpu/drm/radeon/radeon_combios.c WREG32_PLL(addr, val); val 3191 drivers/gpu/drm/radeon/radeon_combios.c uint8_t val = RBIOS8(offset); val 3192 drivers/gpu/drm/radeon/radeon_combios.c while (val != 0xff) { val 3195 drivers/gpu/drm/radeon/radeon_combios.c if (val == 0x0f) { val 3220 drivers/gpu/drm/radeon/radeon_combios.c or_mask = val << 24; val 3226 drivers/gpu/drm/radeon/radeon_combios.c val = RBIOS8(offset); val 552 drivers/gpu/drm/radeon/radeon_connectors.c uint64_t val) val 574 drivers/gpu/drm/radeon/radeon_connectors.c new_coherent_mode = val ? true : false; val 590 drivers/gpu/drm/radeon/radeon_connectors.c if (radeon_connector->audio != val) { val 591 drivers/gpu/drm/radeon/radeon_connectors.c radeon_connector->audio = val; val 605 drivers/gpu/drm/radeon/radeon_connectors.c if (radeon_connector->dither != val) { val 606 drivers/gpu/drm/radeon/radeon_connectors.c radeon_connector->dither = val; val 619 drivers/gpu/drm/radeon/radeon_connectors.c if (radeon_encoder->underscan_type != val) { val 620 drivers/gpu/drm/radeon/radeon_connectors.c radeon_encoder->underscan_type = val; val 633 drivers/gpu/drm/radeon/radeon_connectors.c if (radeon_encoder->underscan_hborder != val) { val 634 drivers/gpu/drm/radeon/radeon_connectors.c radeon_encoder->underscan_hborder = val; val 647 drivers/gpu/drm/radeon/radeon_connectors.c if (radeon_encoder->underscan_vborder != val) { val 648 drivers/gpu/drm/radeon/radeon_connectors.c radeon_encoder->underscan_vborder = val; val 668 drivers/gpu/drm/radeon/radeon_connectors.c dac_int->tv_std = val; val 672 drivers/gpu/drm/radeon/radeon_connectors.c dac_int->tv_std = val; val 681 drivers/gpu/drm/radeon/radeon_connectors.c if (val == 0) val 701 drivers/gpu/drm/radeon/radeon_connectors.c if (val == 0) { val 707 drivers/gpu/drm/radeon/radeon_connectors.c if (val == 1 || ret == false) { val 723 drivers/gpu/drm/radeon/radeon_connectors.c switch (val) { val 750 drivers/gpu/drm/radeon/radeon_connectors.c if (radeon_encoder->output_csc == val) val 753 drivers/gpu/drm/radeon/radeon_connectors.c radeon_encoder->output_csc = val; val 854 drivers/gpu/drm/radeon/radeon_device.c static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) val 858 drivers/gpu/drm/radeon/radeon_device.c rdev->pll_wreg(rdev, reg, val); val 888 drivers/gpu/drm/radeon/radeon_device.c static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) val 892 drivers/gpu/drm/radeon/radeon_device.c rdev->mc_wreg(rdev, reg, val); val 904 drivers/gpu/drm/radeon/radeon_device.c static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) val 908 drivers/gpu/drm/radeon/radeon_device.c WREG32(reg*4, val); val 938 drivers/gpu/drm/radeon/radeon_device.c static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) val 942 drivers/gpu/drm/radeon/radeon_device.c WREG32_IO(reg*4, val); val 72 drivers/gpu/drm/radeon/radeon_dp_mst.c u32 temp, val; val 81 drivers/gpu/drm/radeon/radeon_dp_mst.c val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe); val 83 drivers/gpu/drm/radeon/radeon_dp_mst.c val <<= (16 * satidx); val 87 drivers/gpu/drm/radeon/radeon_dp_mst.c temp |= val; val 169 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t val, temp; val 175 drivers/gpu/drm/radeon/radeon_dp_mst.c val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y); val 177 drivers/gpu/drm/radeon/radeon_dp_mst.c WREG32(NI_DP_MSE_RATE_CNTL + offset, val); val 187 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t val; val 190 drivers/gpu/drm/radeon/radeon_i2c.c val = RREG32(rec->y_clk_reg); val 191 drivers/gpu/drm/radeon/radeon_i2c.c val &= rec->y_clk_mask; val 193 drivers/gpu/drm/radeon/radeon_i2c.c return (val != 0); val 202 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t val; val 205 drivers/gpu/drm/radeon/radeon_i2c.c val = RREG32(rec->y_data_reg); val 206 drivers/gpu/drm/radeon/radeon_i2c.c val &= rec->y_data_mask; val 208 drivers/gpu/drm/radeon/radeon_i2c.c return (val != 0); val 216 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t val; val 219 drivers/gpu/drm/radeon/radeon_i2c.c val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; val 220 drivers/gpu/drm/radeon/radeon_i2c.c val |= clock ? 0 : rec->en_clk_mask; val 221 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->en_clk_reg, val); val 229 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t val; val 232 drivers/gpu/drm/radeon/radeon_i2c.c val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; val 233 drivers/gpu/drm/radeon/radeon_i2c.c val |= data ? 0 : rec->en_data_mask; val 234 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->en_data_reg, val); val 1052 drivers/gpu/drm/radeon/radeon_i2c.c u8 *val) val 1075 drivers/gpu/drm/radeon/radeon_i2c.c *val = in_buf[0]; val 1076 drivers/gpu/drm/radeon/radeon_i2c.c DRM_DEBUG("val = 0x%02x\n", *val); val 1079 drivers/gpu/drm/radeon/radeon_i2c.c addr, *val); val 1086 drivers/gpu/drm/radeon/radeon_i2c.c u8 val) val 1097 drivers/gpu/drm/radeon/radeon_i2c.c out_buf[1] = val; val 1101 drivers/gpu/drm/radeon/radeon_i2c.c addr, val); val 1107 drivers/gpu/drm/radeon/radeon_i2c.c u8 val; val 1117 drivers/gpu/drm/radeon/radeon_i2c.c 0x3, &val); val 1118 drivers/gpu/drm/radeon/radeon_i2c.c val &= ~radeon_connector->router.ddc_mux_control_pin; val 1121 drivers/gpu/drm/radeon/radeon_i2c.c 0x3, val); val 1124 drivers/gpu/drm/radeon/radeon_i2c.c 0x1, &val); val 1125 drivers/gpu/drm/radeon/radeon_i2c.c val &= ~radeon_connector->router.ddc_mux_control_pin; val 1126 drivers/gpu/drm/radeon/radeon_i2c.c val |= radeon_connector->router.ddc_mux_state; val 1129 drivers/gpu/drm/radeon/radeon_i2c.c 0x1, val); val 1135 drivers/gpu/drm/radeon/radeon_i2c.c u8 val; val 1145 drivers/gpu/drm/radeon/radeon_i2c.c 0x3, &val); val 1146 drivers/gpu/drm/radeon/radeon_i2c.c val &= ~radeon_connector->router.cd_mux_control_pin; val 1149 drivers/gpu/drm/radeon/radeon_i2c.c 0x3, val); val 1152 drivers/gpu/drm/radeon/radeon_i2c.c 0x1, &val); val 1153 drivers/gpu/drm/radeon/radeon_i2c.c val &= ~radeon_connector->router.cd_mux_control_pin; val 1154 drivers/gpu/drm/radeon/radeon_i2c.c val |= radeon_connector->router.cd_mux_state; val 1157 drivers/gpu/drm/radeon/radeon_i2c.c 0x1, val); val 797 drivers/gpu/drm/radeon/radeon_mode.h u8 *val); val 801 drivers/gpu/drm/radeon/radeon_mode.h u8 val); val 1313 drivers/gpu/drm/radeon/si.c u32 reg, u32 *val) val 1325 drivers/gpu/drm/radeon/si.c *val = RREG32(reg); val 887 drivers/gpu/drm/radeon/trinity_dpm.c u32 val; val 892 drivers/gpu/drm/radeon/trinity_dpm.c val = (p + tp - 1) / tp; val 894 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_UVD_DPM_CNTL, val); val 48 drivers/gpu/drm/radeon/vce_v1_0.c } val[8]; val 182 drivers/gpu/drm/radeon/vce_v1_0.c if (le32_to_cpu(sign->val[i].chip_id) == chip_id) val 190 drivers/gpu/drm/radeon/vce_v1_0.c data[0] = sign->val[i].nonce[0]; val 191 drivers/gpu/drm/radeon/vce_v1_0.c data[1] = sign->val[i].nonce[1]; val 192 drivers/gpu/drm/radeon/vce_v1_0.c data[2] = sign->val[i].nonce[2]; val 193 drivers/gpu/drm/radeon/vce_v1_0.c data[3] = sign->val[i].nonce[3]; val 200 drivers/gpu/drm/radeon/vce_v1_0.c data[0] = sign->val[i].sigval[0]; val 201 drivers/gpu/drm/radeon/vce_v1_0.c data[1] = sign->val[i].sigval[1]; val 202 drivers/gpu/drm/radeon/vce_v1_0.c data[2] = sign->val[i].sigval[2]; val 203 drivers/gpu/drm/radeon/vce_v1_0.c data[3] = sign->val[i].sigval[3]; val 205 drivers/gpu/drm/radeon/vce_v1_0.c rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); val 700 drivers/gpu/drm/rcar-du/rcar_du_plane.c uint64_t val) val 706 drivers/gpu/drm/rcar-du/rcar_du_plane.c rstate->colorkey = val; val 715 drivers/gpu/drm/rcar-du/rcar_du_plane.c uint64_t *val) val 722 drivers/gpu/drm/rcar-du/rcar_du_plane.c *val = rstate->colorkey; val 151 drivers/gpu/drm/rcar-du/rcar_lvds.c u32 val; val 154 drivers/gpu/drm/rcar-du/rcar_lvds.c val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M; val 156 drivers/gpu/drm/rcar-du/rcar_lvds.c val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M; val 158 drivers/gpu/drm/rcar-du/rcar_lvds.c val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M; val 160 drivers/gpu/drm/rcar-du/rcar_lvds.c val = LVDPLLCR_PLLDLYCNT_150M; val 162 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDPLLCR, val); val 167 drivers/gpu/drm/rcar-du/rcar_lvds.c u32 val; val 170 drivers/gpu/drm/rcar-du/rcar_lvds.c val = LVDPLLCR_PLLDIVCNT_42M; val 172 drivers/gpu/drm/rcar-du/rcar_lvds.c val = LVDPLLCR_PLLDIVCNT_85M; val 174 drivers/gpu/drm/rcar-du/rcar_lvds.c val = LVDPLLCR_PLLDIVCNT_128M; val 176 drivers/gpu/drm/rcar-du/rcar_lvds.c val = LVDPLLCR_PLLDIVCNT_148M; val 178 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDPLLCR, val); val 38 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) val 172 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c u32 val; val 188 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c val = dp->data->lcdsel_lit; val 190 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c val = dp->data->lcdsel_big; val 200 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); val 62 drivers/gpu/drm/rockchip/cdn-dp-core.c unsigned int reg, unsigned int val) val 72 drivers/gpu/drm/rockchip/cdn-dp-core.c ret = regmap_write(dp->grf, reg, val); val 589 drivers/gpu/drm/rockchip/cdn-dp-core.c int ret, val; val 600 drivers/gpu/drm/rockchip/cdn-dp-core.c val = DP_SEL_VOP_LIT | (DP_SEL_VOP_LIT << 16); val 602 drivers/gpu/drm/rockchip/cdn-dp-core.c val = DP_SEL_VOP_LIT << 16; val 604 drivers/gpu/drm/rockchip/cdn-dp-core.c ret = cdn_dp_grf_write(dp, GRF_SOC_CON9, val); val 31 drivers/gpu/drm/rockchip/cdn-dp-reg.c u32 val; val 33 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = DPTX_FRMR_DATA_CLK_RSTN_EN | val 45 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SOURCE_DPTX_CAR); val 47 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN; val 48 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SOURCE_PHY_CAR); val 50 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SOURCE_PKT_SYS_RSTN_EN | val 54 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SOURCE_PKT_CAR); val 56 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SPDIF_CDR_CLK_RSTN_EN | val 62 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SOURCE_AIF_CAR); val 64 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN | val 68 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SOURCE_CIPHER_CAR); val 70 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN | val 72 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SOURCE_CRYPTO_CAR); val 80 drivers/gpu/drm/rockchip/cdn-dp-reg.c int val, ret; val 83 drivers/gpu/drm/rockchip/cdn-dp-reg.c val, !val, MAILBOX_RETRY_US, val 91 drivers/gpu/drm/rockchip/cdn-dp-reg.c static int cdp_dp_mailbox_write(struct cdn_dp_device *dp, u8 val) val 101 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + MAILBOX0_WR_DATA); val 184 drivers/gpu/drm/rockchip/cdn-dp-reg.c static int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val) val 190 drivers/gpu/drm/rockchip/cdn-dp-reg.c msg[2] = (val >> 24) & 0xff; val 191 drivers/gpu/drm/rockchip/cdn-dp-reg.c msg[3] = (val >> 16) & 0xff; val 192 drivers/gpu/drm/rockchip/cdn-dp-reg.c msg[4] = (val >> 8) & 0xff; val 193 drivers/gpu/drm/rockchip/cdn-dp-reg.c msg[5] = val & 0xff; val 199 drivers/gpu/drm/rockchip/cdn-dp-reg.c u8 start_bit, u8 bits_no, u32 val) val 207 drivers/gpu/drm/rockchip/cdn-dp-reg.c field[4] = (val >> 24) & 0xff; val 208 drivers/gpu/drm/rockchip/cdn-dp-reg.c field[5] = (val >> 16) & 0xff; val 209 drivers/gpu/drm/rockchip/cdn-dp-reg.c field[6] = (val >> 8) & 0xff; val 210 drivers/gpu/drm/rockchip/cdn-dp-reg.c field[7] = val & 0xff; val 587 drivers/gpu/drm/rockchip/cdn-dp-reg.c u8 val[2] = {0}; val 592 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[0] = 0; val 596 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[0] = 6 + BT_601 * 8; val 599 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[0] = 5 + BT_601 * 8; val 602 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[0] = 5; val 608 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[1] = 0; val 611 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[1] = 1; val 614 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[1] = 2; val 617 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[1] = 3; val 620 drivers/gpu/drm/rockchip/cdn-dp-reg.c val[1] = 4; val 624 drivers/gpu/drm/rockchip/cdn-dp-reg.c msa_misc = 2 * val[0] + 32 * val[1] + val 635 drivers/gpu/drm/rockchip/cdn-dp-reg.c u32 val, link_rate, rem; val 675 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = symbol + (tu_size_reg << 8); val 676 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= TU_CNT_RST_EN; val 677 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_FRAMER_TU, val); val 682 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; val 683 drivers/gpu/drm/rockchip/cdn-dp-reg.c val /= (dp->link.num_lanes * link_rate); val 684 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = div_u64(8 * (symbol + 1), bit_per_pix) - val; val 685 drivers/gpu/drm/rockchip/cdn-dp-reg.c val += 2; val 686 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_VC_TABLE(15), val); val 690 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = BCS_6; val 693 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = BCS_8; val 696 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = BCS_10; val 699 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = BCS_12; val 702 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = BCS_16; val 706 drivers/gpu/drm/rockchip/cdn-dp-reg.c val += video->color_fmt << 8; val 707 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_FRAMER_PXL_REPR, val); val 711 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0; val 712 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0; val 713 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_FRAMER_SP, val); val 717 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = (mode->hsync_start - mode->hdisplay) << 16; val 718 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= mode->htotal - mode->hsync_end; val 719 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_FRONT_BACK_PORCH, val); val 723 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = mode->hdisplay * bit_per_pix / 8; val 724 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_BYTE_COUNT, val); val 728 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16); val 729 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, MSA_HORIZONTAL_0, val); val 733 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = mode->hsync_end - mode->hsync_start; val 734 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15); val 735 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, MSA_HORIZONTAL_1, val); val 739 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = mode->vtotal; val 740 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= (mode->vtotal - mode->vsync_start) << 16; val 741 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, MSA_VERTICAL_0, val); val 745 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = mode->vsync_end - mode->vsync_start; val 746 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15); val 747 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, MSA_VERTICAL_1, val); val 751 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = cdn_dp_get_msa_misc(video, mode); val 752 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, MSA_MISC, val); val 760 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = mode->hsync_end - mode->hsync_start; val 761 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= mode->hdisplay << 16; val 762 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_HORIZONTAL, val); val 766 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = mode->vdisplay; val 767 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= (mode->vtotal - mode->vsync_start) << 16; val 768 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_VERTICAL_0, val); val 772 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = mode->vtotal; val 773 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_reg_write(dp, DP_VERTICAL_1, val); val 833 drivers/gpu/drm/rockchip/cdn-dp-reg.c u32 val; val 850 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = MAX_NUM_CH(audio->channels); val 851 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= NUM_OF_I2S_PORTS(audio->channels); val 852 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= AUDIO_TYPE_LPCM; val 853 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= CFG_SUB_PCKT_NUM(sub_pckt_num); val 854 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SMPL2PKT_CNFG); val 857 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = 0; val 859 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = 1 << 9; val 861 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = 2 << 9; val 863 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= AUDIO_CH_NUM(audio->channels); val 864 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= I2S_DEC_PORT_EN(i2s_port_en_val); val 865 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= TRANS_SMPL_WIDTH_32; val 866 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + AUDIO_SRC_CNFG); val 870 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = (0x02 << 8) | (0x02 << 20); val 872 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = (0x0b << 8) | (0x0b << 20); val 874 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= ((2 * i) << 4) | ((2 * i + 1) << 16); val 875 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + STTS_BIT_CH(i)); val 880 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SAMPLING_FREQ(3) | val 884 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SAMPLING_FREQ(0) | val 888 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SAMPLING_FREQ(2) | val 892 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SAMPLING_FREQ(8) | val 896 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SAMPLING_FREQ(0xa) | val 900 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SAMPLING_FREQ(0xc) | val 904 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SAMPLING_FREQ(0xe) | val 908 drivers/gpu/drm/rockchip/cdn-dp-reg.c val |= 4; val 909 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + COM_CH_STTS_BITS); val 917 drivers/gpu/drm/rockchip/cdn-dp-reg.c u32 val; val 921 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4); val 922 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SMPL2PKT_CNFG); val 925 drivers/gpu/drm/rockchip/cdn-dp-reg.c val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS; val 926 drivers/gpu/drm/rockchip/cdn-dp-reg.c writel(val, dp->regs + SPDIF_CTRL_ADDR); val 66 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) val 77 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define CP_CURRENT_SEL(val) ((val) & 0xf) val 86 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) val 88 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) val 90 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) val 93 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) val 94 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) val 111 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define BIASEXTR_SEL(val) ((val) & 0x7) val 112 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define BANDGAP_SEL(val) ((val) & 0x7) val 167 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) val 298 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) val 300 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c writel(val, dsi->base + reg); val 314 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c u32 mask, u32 val) val 316 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); val 52 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) val 268 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c u32 val; val 276 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c val = hdmi->chip_data->lcdsel_lit; val 278 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c val = hdmi->chip_data->lcdsel_big; val 286 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val); val 153 drivers/gpu/drm/rockchip/inno_hdmi.c static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) val 155 drivers/gpu/drm/rockchip/inno_hdmi.c writel_relaxed(val, hdmi->regs + (offset) * 0x04); val 159 drivers/gpu/drm/rockchip/inno_hdmi.c u32 msk, u32 val) val 163 drivers/gpu/drm/rockchip/inno_hdmi.c temp |= val & msk; val 224 drivers/gpu/drm/rockchip/inno_hdmi.c u32 val; val 234 drivers/gpu/drm/rockchip/inno_hdmi.c val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH; val 235 drivers/gpu/drm/rockchip/inno_hdmi.c hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val); val 67 drivers/gpu/drm/rockchip/rk3066_hdmi.c static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) val 69 drivers/gpu/drm/rockchip/rk3066_hdmi.c writel_relaxed(val, hdmi->regs + offset); val 73 drivers/gpu/drm/rockchip/rk3066_hdmi.c u32 msk, u32 val) val 77 drivers/gpu/drm/rockchip/rk3066_hdmi.c temp |= val & msk; val 391 drivers/gpu/drm/rockchip/rk3066_hdmi.c int mux, val; val 395 drivers/gpu/drm/rockchip/rk3066_hdmi.c val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL; val 397 drivers/gpu/drm/rockchip/rk3066_hdmi.c val = HDMI_VIDEO_SEL << 16; val 399 drivers/gpu/drm/rockchip/rk3066_hdmi.c regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val); val 280 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; val 287 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = GET_SCL_FT_BIC(src, dst); val 289 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = GET_SCL_FT_BILI_DN(src, dst); val 293 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = GET_SCL_FT_BILI_UP(src, dst); val 295 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = GET_SCL_FT_BIC(src, dst); val 299 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = scl_get_bili_dn_vskip(src, dst, val 302 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = GET_SCL_FT_BILI_DN(src, dst); val 307 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return val; val 322 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t val; val 381 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, val 383 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_yrgb_x, val); val 384 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, val 386 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_yrgb_y, val); val 397 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, val 399 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_cbcr_x, val); val 400 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, val 402 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_cbcr_y, val); val 798 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t val; val 902 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | val 907 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, src_alpha_ctl, val); val 1099 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t pin_pol, val; val 1180 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = hact_st << 16; val 1181 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val |= hact_end; val 1182 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, hact_st_end, val); val 1183 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, hpost_st_end, val); val 1186 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val = vact_st << 16; val 1187 drivers/gpu/drm/rockchip/rockchip_drm_vop.c val |= vact_end; val 1188 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, vact_st_end, val); val 1189 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, vpost_st_end, val); val 1397 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) val 1400 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_framebuffer *fb = val; val 69 drivers/gpu/drm/rockchip/rockchip_lvds.c static inline void lvds_writel(struct rockchip_lvds *lvds, u32 offset, u32 val) val 71 drivers/gpu/drm/rockchip/rockchip_lvds.c writel_relaxed(val, lvds->regs + offset); val 74 drivers/gpu/drm/rockchip/rockchip_lvds.c writel_relaxed(val, lvds->regs + offset + lvds->soc_data->ch1_offset); val 104 drivers/gpu/drm/rockchip/rockchip_lvds.c u32 val; val 117 drivers/gpu/drm/rockchip/rockchip_lvds.c val = RK3288_LVDS_CH0_REG0_LANE4_EN | RK3288_LVDS_CH0_REG0_LANE3_EN | val 121 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= RK3288_LVDS_CH0_REG0_TTL_EN | val 123 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG0, val); val 141 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= RK3288_LVDS_CH0_REG0_LVDS_EN | val 143 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG0, val); val 176 drivers/gpu/drm/rockchip/rockchip_lvds.c u32 val; val 180 drivers/gpu/drm/rockchip/rockchip_lvds.c val = LVDS_DUAL | LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN | LVDS_PWRDN; val 181 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= val << 16; val 182 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val); val 217 drivers/gpu/drm/rockchip/rockchip_lvds.c u32 val; val 225 drivers/gpu/drm/rockchip/rockchip_lvds.c val = lvds->format | LVDS_CH0_EN; val 227 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= LVDS_TTL_EN | LVDS_CH1_EN; val 229 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= LVDS_DUAL | LVDS_CH1_EN; val 232 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= LVDS_START_PHASE_RST_1; val 234 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= (pin_dclk << 8) | (pin_hsync << 9); val 235 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= (0xffff << 16); val 236 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val); val 246 drivers/gpu/drm/rockchip/rockchip_lvds.c u32 val; val 256 drivers/gpu/drm/rockchip/rockchip_lvds.c val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16; val 258 drivers/gpu/drm/rockchip/rockchip_lvds.c val |= RK3288_LVDS_SOC_CON6_SEL_VOP_LIT; val 260 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con6, val); val 494 drivers/gpu/drm/savage/savage_drv.h writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) val 508 drivers/gpu/drm/savage/savage_drv.h #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) val 533 drivers/gpu/drm/savage/savage_drv.h #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) val 52 drivers/gpu/drm/sis/sis_drv.h #define SIS_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) val 124 drivers/gpu/drm/sti/sti_awg_utils.c long int val; val 129 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; val 130 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr(RPLSET, val, 0, 0, fwparams); val 132 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->trailing_pixels - 1 + AWG_DELAY; val 133 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr(SKIP, val, 0, 0, fwparams); val 137 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; val 139 drivers/gpu/drm/sti/sti_awg_utils.c val, 0, 1, fwparams); val 143 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->active_pixels - 1; val 144 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr(SKIP, val, 0, 1, fwparams); val 147 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; val 148 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr(SET, val, 0, 0, fwparams); val 158 drivers/gpu/drm/sti/sti_awg_utils.c long int val, tmp_val; val 163 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; val 164 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr(RPLSET, val, 0, 0, fwparams); val 166 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->trailing_lines - 1; val 167 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr(REPLAY, val, 0, 0, fwparams); val 184 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; val 185 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr(RPLSET, val, 0, 0, fwparams); val 187 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_lines - 1; val 188 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr(REPLAY, val, 0, 0, fwparams); val 237 drivers/gpu/drm/sti/sti_crtc.c uint64_t val) val 82 drivers/gpu/drm/sti/sti_cursor.c static void cursor_dbg_vpo(struct seq_file *s, u32 val) val 84 drivers/gpu/drm/sti/sti_cursor.c seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF); val 87 drivers/gpu/drm/sti/sti_cursor.c static void cursor_dbg_size(struct seq_file *s, u32 val) val 89 drivers/gpu/drm/sti/sti_cursor.c seq_printf(s, "\t%d x %d", val & 0x07FF, (val >> 16) & 0x07FF); val 93 drivers/gpu/drm/sti/sti_cursor.c struct sti_cursor *cursor, u32 val) val 95 drivers/gpu/drm/sti/sti_cursor.c if (cursor->pixmap.paddr == val) val 100 drivers/gpu/drm/sti/sti_cursor.c struct sti_cursor *cursor, u32 val) val 102 drivers/gpu/drm/sti/sti_cursor.c if (cursor->clut_paddr == val) val 266 drivers/gpu/drm/sti/sti_cursor.c u32 val; val 283 drivers/gpu/drm/sti/sti_cursor.c val = y << 16 | x; val 284 drivers/gpu/drm/sti/sti_cursor.c writel(val, cursor->regs + CUR_AWS); val 287 drivers/gpu/drm/sti/sti_cursor.c val = y << 16 | x; val 288 drivers/gpu/drm/sti/sti_cursor.c writel(val, cursor->regs + CUR_AWE); val 37 drivers/gpu/drm/sti/sti_drv.c static int sti_drm_fps_get(void *data, u64 *val) val 43 drivers/gpu/drm/sti/sti_drv.c *val = 0; val 47 drivers/gpu/drm/sti/sti_drv.c *val |= plane->fps_info.output << i; val 54 drivers/gpu/drm/sti/sti_drv.c static int sti_drm_fps_set(void *data, u64 val) val 64 drivers/gpu/drm/sti/sti_drv.c plane->fps_info.output = (val >> i) & 1; val 237 drivers/gpu/drm/sti/sti_dvo.c u32 val; val 272 drivers/gpu/drm/sti/sti_dvo.c val = (config->flags | DVO_DOF_EN); val 273 drivers/gpu/drm/sti/sti_dvo.c writel(val, dvo->regs + DVO_DOF_CFG); val 149 drivers/gpu/drm/sti/sti_gdp.c static void gdp_dbg_ctl(struct seq_file *s, int val) val 155 drivers/gpu/drm/sti/sti_gdp.c if (gdp_format_to_str[i].format == (val & 0x1F)) { val 163 drivers/gpu/drm/sti/sti_gdp.c seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); val 166 drivers/gpu/drm/sti/sti_gdp.c static void gdp_dbg_vpo(struct seq_file *s, int val) val 168 drivers/gpu/drm/sti/sti_gdp.c seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); val 171 drivers/gpu/drm/sti/sti_gdp.c static void gdp_dbg_vps(struct seq_file *s, int val) val 173 drivers/gpu/drm/sti/sti_gdp.c seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); val 176 drivers/gpu/drm/sti/sti_gdp.c static void gdp_dbg_size(struct seq_file *s, int val) val 178 drivers/gpu/drm/sti/sti_gdp.c seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); val 181 drivers/gpu/drm/sti/sti_gdp.c static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) val 187 drivers/gpu/drm/sti/sti_gdp.c if (gdp->node_list[i].top_field_paddr == val) { val 191 drivers/gpu/drm/sti/sti_gdp.c if (gdp->node_list[i].btm_field_paddr == val) { val 201 drivers/gpu/drm/sti/sti_gdp.c static void gdp_dbg_ppt(struct seq_file *s, int val) val 203 drivers/gpu/drm/sti/sti_gdp.c if (val & GAM_GDP_PPT_IGNORE) val 207 drivers/gpu/drm/sti/sti_gdp.c static void gdp_dbg_mst(struct seq_file *s, int val) val 209 drivers/gpu/drm/sti/sti_gdp.c if (val & 1) val 268 drivers/gpu/drm/sti/sti_hda.c static void hda_write(struct sti_hda *hda, u32 val, int offset) val 270 drivers/gpu/drm/sti/sti_hda.c writel(val, hda->regs + offset); val 302 drivers/gpu/drm/sti/sti_hda.c u32 val; val 304 drivers/gpu/drm/sti/sti_hda.c val = readl(hda->video_dacs_ctrl); val 306 drivers/gpu/drm/sti/sti_hda.c val &= ~DAC_CFG_HD_HZUVW_OFF_MASK; val 308 drivers/gpu/drm/sti/sti_hda.c val |= DAC_CFG_HD_HZUVW_OFF_MASK; val 310 drivers/gpu/drm/sti/sti_hda.c writel(val, hda->video_dacs_ctrl); val 317 drivers/gpu/drm/sti/sti_hda.c static void hda_dbg_cfg(struct seq_file *s, int val) val 320 drivers/gpu/drm/sti/sti_hda.c seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled"); val 337 drivers/gpu/drm/sti/sti_hda.c u32 val = readl(reg); val 339 drivers/gpu/drm/sti/sti_hda.c seq_printf(s, "\n\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); val 341 drivers/gpu/drm/sti/sti_hda.c seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled"); val 403 drivers/gpu/drm/sti/sti_hda.c u32 val; val 411 drivers/gpu/drm/sti/sti_hda.c val = hda_read(hda, HDA_ANA_CFG); val 412 drivers/gpu/drm/sti/sti_hda.c val &= ~CFG_AWG_ASYNC_EN; val 413 drivers/gpu/drm/sti/sti_hda.c hda_write(hda, val, HDA_ANA_CFG); val 428 drivers/gpu/drm/sti/sti_hda.c u32 val, i, mode_idx; val 495 drivers/gpu/drm/sti/sti_hda.c val = 0; val 496 drivers/gpu/drm/sti/sti_hda.c val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ? val 498 drivers/gpu/drm/sti/sti_hda.c val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT); val 499 drivers/gpu/drm/sti/sti_hda.c val |= filter_mode; val 500 drivers/gpu/drm/sti/sti_hda.c hda_write(hda, val, HDA_ANA_CFG); val 507 drivers/gpu/drm/sti/sti_hda.c val = hda_read(hda, HDA_ANA_CFG); val 508 drivers/gpu/drm/sti/sti_hda.c val |= CFG_AWG_ASYNC_EN; val 509 drivers/gpu/drm/sti/sti_hda.c hda_write(hda, val, HDA_ANA_CFG); val 174 drivers/gpu/drm/sti/sti_hdmi.c void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset) val 176 drivers/gpu/drm/sti/sti_hdmi.c writel(val, hdmi->regs + offset); val 300 drivers/gpu/drm/sti/sti_hdmi.c u32 val, i; val 322 drivers/gpu/drm/sti/sti_hdmi.c val = hdmi_read(hdmi, HDMI_SW_DI_CFG); val 323 drivers/gpu/drm/sti/sti_hdmi.c val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); val 324 drivers/gpu/drm/sti/sti_hdmi.c hdmi_write(hdmi, val, HDMI_SW_DI_CFG); val 362 drivers/gpu/drm/sti/sti_hdmi.c u32 val, slot, mode, i; val 390 drivers/gpu/drm/sti/sti_hdmi.c val = hdmi_read(hdmi, HDMI_SW_DI_CFG); val 391 drivers/gpu/drm/sti/sti_hdmi.c val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); val 392 drivers/gpu/drm/sti/sti_hdmi.c hdmi_write(hdmi, val, HDMI_SW_DI_CFG); val 394 drivers/gpu/drm/sti/sti_hdmi.c val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++); val 395 drivers/gpu/drm/sti/sti_hdmi.c val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++); val 396 drivers/gpu/drm/sti/sti_hdmi.c val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++); val 397 drivers/gpu/drm/sti/sti_hdmi.c writel(val, hdmi->regs + head_offset); val 409 drivers/gpu/drm/sti/sti_hdmi.c val = hdmi_infoframe_subpack(ptr, num); val 411 drivers/gpu/drm/sti/sti_hdmi.c writel(val, hdmi->regs + pack_offset + i); val 415 drivers/gpu/drm/sti/sti_hdmi.c val = hdmi_read(hdmi, HDMI_SW_DI_CFG); val 416 drivers/gpu/drm/sti/sti_hdmi.c val |= HDMI_IFRAME_CFG_DI_N(mode, slot); val 417 drivers/gpu/drm/sti/sti_hdmi.c hdmi_write(hdmi, val, HDMI_SW_DI_CFG); val 478 drivers/gpu/drm/sti/sti_hdmi.c int ret, val; val 493 drivers/gpu/drm/sti/sti_hdmi.c val = hdmi_read(hdmi, HDMI_SW_DI_CFG); val 494 drivers/gpu/drm/sti/sti_hdmi.c val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, val 496 drivers/gpu/drm/sti/sti_hdmi.c hdmi_write(hdmi, val, HDMI_SW_DI_CFG); val 555 drivers/gpu/drm/sti/sti_hdmi.c u32 val; val 566 drivers/gpu/drm/sti/sti_hdmi.c val = hdmi_read(hdmi, HDMI_CFG); val 567 drivers/gpu/drm/sti/sti_hdmi.c val |= HDMI_CFG_SW_RST_EN; val 568 drivers/gpu/drm/sti/sti_hdmi.c hdmi_write(hdmi, val, HDMI_CFG); val 583 drivers/gpu/drm/sti/sti_hdmi.c val = hdmi_read(hdmi, HDMI_CFG); val 584 drivers/gpu/drm/sti/sti_hdmi.c val &= ~HDMI_CFG_SW_RST_EN; val 585 drivers/gpu/drm/sti/sti_hdmi.c hdmi_write(hdmi, val, HDMI_CFG); val 597 drivers/gpu/drm/sti/sti_hdmi.c static void hdmi_dbg_cfg(struct seq_file *s, int val) val 602 drivers/gpu/drm/sti/sti_hdmi.c tmp = val & HDMI_CFG_HDMI_NOT_DVI; val 605 drivers/gpu/drm/sti/sti_hdmi.c tmp = val & HDMI_CFG_HDCP_EN; val 608 drivers/gpu/drm/sti/sti_hdmi.c tmp = val & HDMI_CFG_ESS_NOT_OESS; val 611 drivers/gpu/drm/sti/sti_hdmi.c tmp = val & HDMI_CFG_H_SYNC_POL_NEG; val 614 drivers/gpu/drm/sti/sti_hdmi.c tmp = val & HDMI_CFG_V_SYNC_POL_NEG; val 617 drivers/gpu/drm/sti/sti_hdmi.c tmp = val & HDMI_CFG_422_EN; val 621 drivers/gpu/drm/sti/sti_hdmi.c static void hdmi_dbg_sta(struct seq_file *s, int val) val 626 drivers/gpu/drm/sti/sti_hdmi.c tmp = (val & HDMI_STA_DLL_LCK); val 629 drivers/gpu/drm/sti/sti_hdmi.c tmp = (val & HDMI_STA_HOT_PLUG); val 633 drivers/gpu/drm/sti/sti_hdmi.c static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val) val 642 drivers/gpu/drm/sti/sti_hdmi.c tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1)); val 645 drivers/gpu/drm/sti/sti_hdmi.c tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4; val 648 drivers/gpu/drm/sti/sti_hdmi.c tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8; val 651 drivers/gpu/drm/sti/sti_hdmi.c tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12; val 654 drivers/gpu/drm/sti/sti_hdmi.c tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16; val 657 drivers/gpu/drm/sti/sti_hdmi.c tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20; val 745 drivers/gpu/drm/sti/sti_hdmi.c u32 val = hdmi_read(hdmi, HDMI_CFG); val 753 drivers/gpu/drm/sti/sti_hdmi.c val &= ~HDMI_CFG_DEVICE_EN; val 754 drivers/gpu/drm/sti/sti_hdmi.c hdmi_write(hdmi, val, HDMI_CFG); val 1075 drivers/gpu/drm/sti/sti_hdmi.c uint64_t val) val 1082 drivers/gpu/drm/sti/sti_hdmi.c hdmi->colorspace = val; val 1094 drivers/gpu/drm/sti/sti_hdmi.c uint64_t *val) val 1101 drivers/gpu/drm/sti/sti_hdmi.c *val = hdmi->colorspace; val 100 drivers/gpu/drm/sti/sti_hdmi.h void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset); val 79 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c u32 val, tmdsck, idf, odf, pllctrl = 0; val 133 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c val = (HDMI_SRZ_CFG_EN | val 139 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c val |= HDMI_SRZ_CFG_EN_SRC_TERMINATION; val 149 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c val |= (hdmiphy_config[i].config[0] val 151 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c hdmi_write(hdmi, val, HDMI_SRZ_CFG); val 153 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c val = hdmiphy_config[i].config[1]; val 154 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c hdmi_write(hdmi, val, HDMI_SRZ_ICNTL); val 156 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c val = hdmiphy_config[i].config[2]; val 157 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c hdmi_write(hdmi, val, HDMI_SRZ_CALCODE_EXT); val 171 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c hdmi_write(hdmi, val, HDMI_SRZ_CFG); val 188 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c int val = 0; val 194 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c val = HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION; val 195 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c val |= HDMI_SRZ_CFG_EN_BIASRES_DETECTION; val 197 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c hdmi_write(hdmi, val, HDMI_SRZ_CFG); val 72 drivers/gpu/drm/sti/sti_mixer.c u32 reg_id, u32 val) val 74 drivers/gpu/drm/sti/sti_mixer.c writel(val, mixer->regs + reg_id); val 80 drivers/gpu/drm/sti/sti_mixer.c static void mixer_dbg_ctl(struct seq_file *s, int val) val 89 drivers/gpu/drm/sti/sti_mixer.c if (val & 1) { val 93 drivers/gpu/drm/sti/sti_mixer.c val = val >> 1; val 96 drivers/gpu/drm/sti/sti_mixer.c val = val >> 2; val 97 drivers/gpu/drm/sti/sti_mixer.c if (val & 1) { val 105 drivers/gpu/drm/sti/sti_mixer.c static void mixer_dbg_crb(struct seq_file *s, int val) val 111 drivers/gpu/drm/sti/sti_mixer.c switch (val & GAM_DEPTH_MASK_ID) { val 136 drivers/gpu/drm/sti/sti_mixer.c val = val >> 3; val 210 drivers/gpu/drm/sti/sti_mixer.c u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL); val 212 drivers/gpu/drm/sti/sti_mixer.c val &= ~GAM_CTL_BACK_MASK; val 213 drivers/gpu/drm/sti/sti_mixer.c val |= enable; val 214 drivers/gpu/drm/sti/sti_mixer.c sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); val 241 drivers/gpu/drm/sti/sti_mixer.c u32 mask, val; val 268 drivers/gpu/drm/sti/sti_mixer.c val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB); val 271 drivers/gpu/drm/sti/sti_mixer.c if ((val & mask) == plane_id << (3 * i)) val 283 drivers/gpu/drm/sti/sti_mixer.c val &= ~mask; val 284 drivers/gpu/drm/sti/sti_mixer.c val |= plane_id; val 285 drivers/gpu/drm/sti/sti_mixer.c sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val); val 339 drivers/gpu/drm/sti/sti_mixer.c u32 mask, val; val 350 drivers/gpu/drm/sti/sti_mixer.c val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL); val 351 drivers/gpu/drm/sti/sti_mixer.c val &= ~mask; val 352 drivers/gpu/drm/sti/sti_mixer.c val |= status ? mask : 0; val 353 drivers/gpu/drm/sti/sti_mixer.c sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); val 150 drivers/gpu/drm/sti/sti_tvout.c static void tvout_write(struct sti_tvout *tvout, u32 val, int offset) val 152 drivers/gpu/drm/sti/sti_tvout.c writel(val, tvout->regs + offset); val 167 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); val 169 drivers/gpu/drm/sti/sti_tvout.c val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT); val 170 drivers/gpu/drm/sti/sti_tvout.c val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT); val 171 drivers/gpu/drm/sti/sti_tvout.c val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT); val 172 drivers/gpu/drm/sti/sti_tvout.c val |= cr_r << TVO_VIP_REORDER_R_SHIFT; val 173 drivers/gpu/drm/sti/sti_tvout.c val |= y_g << TVO_VIP_REORDER_G_SHIFT; val 174 drivers/gpu/drm/sti/sti_tvout.c val |= cb_b << TVO_VIP_REORDER_B_SHIFT; val 176 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); val 188 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); val 190 drivers/gpu/drm/sti/sti_tvout.c val &= ~(TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT); val 191 drivers/gpu/drm/sti/sti_tvout.c val |= range << TVO_VIP_CLIP_SHIFT; val 192 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); val 204 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); val 206 drivers/gpu/drm/sti/sti_tvout.c val &= ~(TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT); val 207 drivers/gpu/drm/sti/sti_tvout.c val |= rnd << TVO_VIP_RND_SHIFT; val 208 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); val 225 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); val 244 drivers/gpu/drm/sti/sti_tvout.c val &= ~TVO_VIP_SEL_INPUT_MASK; val 245 drivers/gpu/drm/sti/sti_tvout.c val |= sel_input; val 246 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); val 259 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); val 261 drivers/gpu/drm/sti/sti_tvout.c val &= ~TVO_IN_FMT_SIGNED; val 262 drivers/gpu/drm/sti/sti_tvout.c val |= in_vid_fmt; val 263 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); val 301 drivers/gpu/drm/sti/sti_tvout.c int val, tmp; val 309 drivers/gpu/drm/sti/sti_tvout.c val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT; val 310 drivers/gpu/drm/sti/sti_tvout.c val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT; val 311 drivers/gpu/drm/sti/sti_tvout.c val |= tmp; val 312 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, TVO_DVO_SYNC_SEL); val 318 drivers/gpu/drm/sti/sti_tvout.c val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT; val 319 drivers/gpu/drm/sti/sti_tvout.c val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT; val 320 drivers/gpu/drm/sti/sti_tvout.c val |= tmp; val 321 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, TVO_DVO_SYNC_SEL); val 404 drivers/gpu/drm/sti/sti_tvout.c int val; val 411 drivers/gpu/drm/sti/sti_tvout.c val = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDDCS; val 412 drivers/gpu/drm/sti/sti_tvout.c val = val << TVO_SYNC_HD_DCS_SHIFT; val 413 drivers/gpu/drm/sti/sti_tvout.c val |= TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDF; val 414 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, TVO_HD_SYNC_SEL); val 419 drivers/gpu/drm/sti/sti_tvout.c val = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDDCS; val 420 drivers/gpu/drm/sti/sti_tvout.c val = val << TVO_SYNC_HD_DCS_SHIFT; val 421 drivers/gpu/drm/sti/sti_tvout.c val |= TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDF; val 422 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, TVO_HD_SYNC_SEL); val 452 drivers/gpu/drm/sti/sti_tvout.c static void tvout_dbg_vip(struct seq_file *s, int val) val 468 drivers/gpu/drm/sti/sti_tvout.c r = (val & mask) >> TVO_VIP_REORDER_R_SHIFT; val 470 drivers/gpu/drm/sti/sti_tvout.c g = (val & mask) >> TVO_VIP_REORDER_G_SHIFT; val 472 drivers/gpu/drm/sti/sti_tvout.c b = (val & mask) >> TVO_VIP_REORDER_B_SHIFT; val 479 drivers/gpu/drm/sti/sti_tvout.c tmp = (val & mask) >> TVO_VIP_CLIP_SHIFT; val 483 drivers/gpu/drm/sti/sti_tvout.c tmp = (val & mask) >> TVO_VIP_RND_SHIFT; val 487 drivers/gpu/drm/sti/sti_tvout.c tmp = (val & TVO_VIP_SEL_INPUT_MASK); val 491 drivers/gpu/drm/sti/sti_tvout.c static void tvout_dbg_hd_dac_cfg(struct seq_file *s, int val) val 494 drivers/gpu/drm/sti/sti_tvout.c val & 1 ? "disabled" : "enabled"); val 63 drivers/gpu/drm/sti/sti_vid.c static void vid_dbg_ctl(struct seq_file *s, int val) val 65 drivers/gpu/drm/sti/sti_vid.c val = val >> 30; val 68 drivers/gpu/drm/sti/sti_vid.c if (!(val & 1)) val 72 drivers/gpu/drm/sti/sti_vid.c if (!(val & 2)) val 77 drivers/gpu/drm/sti/sti_vid.c static void vid_dbg_vpo(struct seq_file *s, int val) val 79 drivers/gpu/drm/sti/sti_vid.c seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF); val 82 drivers/gpu/drm/sti/sti_vid.c static void vid_dbg_vps(struct seq_file *s, int val) val 84 drivers/gpu/drm/sti/sti_vid.c seq_printf(s, "\txds:%4d\tyds:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF); val 87 drivers/gpu/drm/sti/sti_vid.c static void vid_dbg_mst(struct seq_file *s, int val) val 89 drivers/gpu/drm/sti/sti_vid.c if (val & 1) val 149 drivers/gpu/drm/sti/sti_vid.c u32 val, ydo, xdo, yds, xds; val 157 drivers/gpu/drm/sti/sti_vid.c val = readl(vid->regs + VID_CTL); val 158 drivers/gpu/drm/sti/sti_vid.c val &= ~VID_CTL_IGNORE; val 159 drivers/gpu/drm/sti/sti_vid.c writel(val, vid->regs + VID_CTL); val 185 drivers/gpu/drm/sti/sti_vid.c u32 val; val 188 drivers/gpu/drm/sti/sti_vid.c val = readl(vid->regs + VID_CTL); val 189 drivers/gpu/drm/sti/sti_vid.c val |= VID_CTL_IGNORE; val 190 drivers/gpu/drm/sti/sti_vid.c writel(val, vid->regs + VID_CTL); val 87 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) val 89 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c writel(val, dsi->base + reg); val 108 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c u32 mask, u32 val) val 110 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); val 200 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c u32 val; val 205 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, val 212 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, val 248 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c u32 val; val 291 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c val = 4000000 / pll_out_khz; val 292 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val); val 247 drivers/gpu/drm/stm/ltdc.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) val 249 drivers/gpu/drm/stm/ltdc.c writel_relaxed(val, base + reg); val 263 drivers/gpu/drm/stm/ltdc.c u32 val) val 265 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); val 408 drivers/gpu/drm/stm/ltdc.c u32 val; val 417 drivers/gpu/drm/stm/ltdc.c val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | val 419 drivers/gpu/drm/stm/ltdc.c reg_write(ldev->regs, LTDC_L1CLUTWR, val); val 552 drivers/gpu/drm/stm/ltdc.c u32 val; val 582 drivers/gpu/drm/stm/ltdc.c val = 0; val 585 drivers/gpu/drm/stm/ltdc.c val |= GCR_HSPOL; val 588 drivers/gpu/drm/stm/ltdc.c val |= GCR_VSPOL; val 591 drivers/gpu/drm/stm/ltdc.c val |= GCR_DEPOL; val 594 drivers/gpu/drm/stm/ltdc.c val |= GCR_PCPOL; val 597 drivers/gpu/drm/stm/ltdc.c GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); val 600 drivers/gpu/drm/stm/ltdc.c val = (hsync << 16) | vsync; val 601 drivers/gpu/drm/stm/ltdc.c reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); val 604 drivers/gpu/drm/stm/ltdc.c val = (accum_hbp << 16) | accum_vbp; val 605 drivers/gpu/drm/stm/ltdc.c reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); val 608 drivers/gpu/drm/stm/ltdc.c val = (accum_act_w << 16) | accum_act_h; val 609 drivers/gpu/drm/stm/ltdc.c reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); val 612 drivers/gpu/drm/stm/ltdc.c val = (total_width << 16) | total_height; val 613 drivers/gpu/drm/stm/ltdc.c reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); val 770 drivers/gpu/drm/stm/ltdc.c u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; val 795 drivers/gpu/drm/stm/ltdc.c val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); val 797 drivers/gpu/drm/stm/ltdc.c LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); val 800 drivers/gpu/drm/stm/ltdc.c val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); val 802 drivers/gpu/drm/stm/ltdc.c LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); val 806 drivers/gpu/drm/stm/ltdc.c for (val = 0; val < NB_PF; val++) val 807 drivers/gpu/drm/stm/ltdc.c if (ldev->caps.pix_fmt_hw[val] == pf) val 810 drivers/gpu/drm/stm/ltdc.c if (val == NB_PF) { val 813 drivers/gpu/drm/stm/ltdc.c val = 0; /* set by default ARGB 32 bits */ val 815 drivers/gpu/drm/stm/ltdc.c reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); val 821 drivers/gpu/drm/stm/ltdc.c val = ((pitch_in_bytes << 16) | line_length); val 823 drivers/gpu/drm/stm/ltdc.c LXCFBLR_CFBLL | LXCFBLR_CFBP, val); val 826 drivers/gpu/drm/stm/ltdc.c val = CONSTA_MAX; val 827 drivers/gpu/drm/stm/ltdc.c reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); val 830 drivers/gpu/drm/stm/ltdc.c val = BF1_PAXCA | BF2_1PAXCA; val 832 drivers/gpu/drm/stm/ltdc.c val = BF1_CA | BF2_1CA; val 837 drivers/gpu/drm/stm/ltdc.c val = BF1_PAXCA | BF2_1PAXCA; val 840 drivers/gpu/drm/stm/ltdc.c LXBFCR_BF2 | LXBFCR_BF1, val); val 843 drivers/gpu/drm/stm/ltdc.c val = y1 - y0 + 1; val 844 drivers/gpu/drm/stm/ltdc.c reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); val 853 drivers/gpu/drm/stm/ltdc.c val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; val 854 drivers/gpu/drm/stm/ltdc.c val |= LXCR_LEN; val 856 drivers/gpu/drm/stm/ltdc.c LXCR_LEN | LXCR_CLUTEN, val); val 82 drivers/gpu/drm/sun4i/sun4i_backend.c u32 val; val 88 drivers/gpu/drm/sun4i/sun4i_backend.c val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); val 90 drivers/gpu/drm/sun4i/sun4i_backend.c val = 0; val 93 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_MODCTL_LAY_EN(layer), val); val 206 drivers/gpu/drm/sun4i/sun4i_backend.c u32 val = SUN4I_BACKEND_IYUVCTL_EN; val 225 drivers/gpu/drm/sun4i/sun4i_backend.c val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422; val 235 drivers/gpu/drm/sun4i/sun4i_backend.c val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY; val 238 drivers/gpu/drm/sun4i/sun4i_backend.c val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY; val 241 drivers/gpu/drm/sun4i/sun4i_backend.c val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU; val 244 drivers/gpu/drm/sun4i/sun4i_backend.c val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV; val 251 drivers/gpu/drm/sun4i/sun4i_backend.c regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val); val 262 drivers/gpu/drm/sun4i/sun4i_backend.c u32 val; val 280 drivers/gpu/drm/sun4i/sun4i_backend.c val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8); val 282 drivers/gpu/drm/sun4i/sun4i_backend.c val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN; val 287 drivers/gpu/drm/sun4i/sun4i_backend.c val); val 292 drivers/gpu/drm/sun4i/sun4i_backend.c ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val); val 300 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); val 308 drivers/gpu/drm/sun4i/sun4i_backend.c u32 val; val 311 drivers/gpu/drm/sun4i/sun4i_backend.c ret = sun4i_backend_drm_format_to_layer(fmt, &val); val 324 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); val 477 drivers/gpu/drm/sun4i/sun4i_backend.c u32 val; val 481 drivers/gpu/drm/sun4i/sun4i_backend.c val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL), val 57 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_LAYFB_H4ADD(l, val) ((val) << ((l) * 8)) val 46 drivers/gpu/drm/sun4i/sun4i_dotclock.c u32 val; val 48 drivers/gpu/drm/sun4i/sun4i_dotclock.c regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); val 50 drivers/gpu/drm/sun4i/sun4i_dotclock.c return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT); val 57 drivers/gpu/drm/sun4i/sun4i_dotclock.c u32 val; val 59 drivers/gpu/drm/sun4i/sun4i_dotclock.c regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); val 61 drivers/gpu/drm/sun4i/sun4i_dotclock.c val >>= SUN4I_TCON0_DCLK_DIV_SHIFT; val 62 drivers/gpu/drm/sun4i/sun4i_dotclock.c val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1; val 64 drivers/gpu/drm/sun4i/sun4i_dotclock.c if (!val) val 65 drivers/gpu/drm/sun4i/sun4i_dotclock.c val = 1; val 67 drivers/gpu/drm/sun4i/sun4i_dotclock.c return parent_rate / val; val 128 drivers/gpu/drm/sun4i/sun4i_dotclock.c u32 val; val 130 drivers/gpu/drm/sun4i/sun4i_dotclock.c regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val); val 132 drivers/gpu/drm/sun4i/sun4i_dotclock.c val >>= 28; val 133 drivers/gpu/drm/sun4i/sun4i_dotclock.c val &= 3; val 135 drivers/gpu/drm/sun4i/sun4i_dotclock.c return val * 120; val 141 drivers/gpu/drm/sun4i/sun4i_dotclock.c u32 val = degrees / 120; val 143 drivers/gpu/drm/sun4i/sun4i_dotclock.c val <<= 28; val 147 drivers/gpu/drm/sun4i/sun4i_dotclock.c val); val 249 drivers/gpu/drm/sun4i/sun4i_frontend.c u32 *val) val 252 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_RGB; val 254 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV411; val 256 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV420; val 258 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV422; val 260 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV444; val 269 drivers/gpu/drm/sun4i/sun4i_frontend.c uint64_t modifier, u32 *val) val 275 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED; val 279 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR val 284 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR val 295 drivers/gpu/drm/sun4i/sun4i_frontend.c u32 *val) val 299 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = 0; val 305 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_BGRX; val 309 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV; val 313 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV; val 317 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU; val 321 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU; val 325 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UYVY; val 329 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VYUY; val 333 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_XRGB; val 337 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YUYV; val 341 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YVYU; val 349 drivers/gpu/drm/sun4i/sun4i_frontend.c static int sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt, u32 *val) val 353 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_BGRX8888; val 357 drivers/gpu/drm/sun4i/sun4i_frontend.c *val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_XRGB8888; val 86 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c u32 val; val 90 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); val 91 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; val 92 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); val 101 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c u32 val = 0; val 108 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); val 109 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); val 110 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); val 112 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val = SUN4I_HDMI_VID_CTRL_ENABLE; val 114 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; val 116 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); val 125 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c u32 val; val 144 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); val 145 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; val 146 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val |= hdmi->variant->pad_ctrl1_init_val; val 147 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); val 148 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); val 170 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; val 172 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; val 175 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; val 177 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); val 121 drivers/gpu/drm/sun4i/sun4i_tcon.c u8 val; val 149 drivers/gpu/drm/sun4i/sun4i_tcon.c val = 7; val 151 drivers/gpu/drm/sun4i/sun4i_tcon.c val = 0xf; val 155 drivers/gpu/drm/sun4i/sun4i_tcon.c SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); val 201 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 mask, val = 0; val 210 drivers/gpu/drm/sun4i/sun4i_tcon.c val = mask; val 212 drivers/gpu/drm/sun4i/sun4i_tcon.c regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); val 283 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 val = 0; val 308 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_FRM_CTL_EN; val 317 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_FRM_CTL_MODE_R; val 318 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_FRM_CTL_MODE_B; val 323 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_FRM_CTL_EN; val 328 drivers/gpu/drm/sun4i/sun4i_tcon.c regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); val 408 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 reg, val = 0; val 463 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; val 466 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; val 468 drivers/gpu/drm/sun4i/sun4i_tcon.c regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); val 487 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 val = 0; val 540 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; val 543 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; val 546 drivers/gpu/drm/sun4i/sun4i_tcon.c val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; val 573 drivers/gpu/drm/sun4i/sun4i_tcon.c val); val 589 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 val; val 604 drivers/gpu/drm/sun4i/sun4i_tcon.c val = SUN4I_TCON1_CTL_INTERLACE_ENABLE; val 606 drivers/gpu/drm/sun4i/sun4i_tcon.c val = 0; val 609 drivers/gpu/drm/sun4i/sun4i_tcon.c val); val 1346 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 val; val 1349 drivers/gpu/drm/sun4i/sun4i_tcon.c val = 1; val 1351 drivers/gpu/drm/sun4i/sun4i_tcon.c val = 0; val 1356 drivers/gpu/drm/sun4i/sun4i_tcon.c return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); val 233 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c u8 val = 0; val 241 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val = (BIT(j) & data) ? 1 : 0; val 244 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val ^= (BIT(j) & data) ? 1 : 0; val 248 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c ecc |= val << i; val 268 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c u32 val = dt & 0x3f; val 270 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val |= (vc & 3) << 6; val 271 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val |= (d0 & 0xff) << 8; val 272 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val |= (d1 & 0xff) << 16; val 273 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val |= sun6i_dsi_ecc_compute(val) << 24; val 275 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c return val; val 286 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c u32 val = SUN6I_DSI_BLK_PD(pd); val 288 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat(pd, buffer, len)); val 306 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c u32 val; val 309 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val, val 310 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c !(val & SUN6I_DSI_BASIC_CTL0_INST_ST), val 422 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c u32 val = 0; val 439 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val = SUN6I_DSI_TCON_DRQ_ENABLE_MODE; val 447 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE | val 451 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val); val 483 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel); val 511 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val |= SUN6I_DSI_PIXEL_PH_DT(dt); val 514 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val |= SUN6I_DSI_PIXEL_PH_WC(wc); val 515 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val)); val 517 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val); val 904 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c u32 val; val 926 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val); val 927 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW) val 930 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val); val 931 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c byte0 = val & 0xff; val 935 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c ((u8 *)msg->rx_buf)[0] = (val >> 8); val 203 drivers/gpu/drm/sun4i/sun8i_csc.c u32 val; val 206 drivers/gpu/drm/sun4i/sun8i_csc.c val = SUN8I_CSC_CTRL_EN; val 208 drivers/gpu/drm/sun4i/sun8i_csc.c val = 0; val 210 drivers/gpu/drm/sun4i/sun8i_csc.c regmap_update_bits(map, SUN8I_CSC_CTRL(base), SUN8I_CSC_CTRL_EN, val); val 215 drivers/gpu/drm/sun4i/sun8i_csc.c u32 val, mask; val 220 drivers/gpu/drm/sun4i/sun8i_csc.c val = mask; val 222 drivers/gpu/drm/sun4i/sun8i_csc.c val = 0; val 225 drivers/gpu/drm/sun4i/sun8i_csc.c mask, val); val 205 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c u32 val; val 322 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); val 323 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c val = (val & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK) >> val 325 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c val = min(val + b_offset, (u32)0x3f); val 334 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c val << SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT); val 347 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c u32 val = 0; val 350 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC; val 353 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC; val 356 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val); val 439 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c unsigned int val; val 479 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val, val 480 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c (val & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D), val 511 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); val 512 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2; val 32 drivers/gpu/drm/sun4i/sun8i_tcon_top.c u32 val; val 46 drivers/gpu/drm/sun4i/sun8i_tcon_top.c val = readl(tcon_top->regs + TCON_TOP_GATE_SRC_REG); val 47 drivers/gpu/drm/sun4i/sun8i_tcon_top.c val &= ~TCON_TOP_HDMI_SRC_MSK; val 48 drivers/gpu/drm/sun4i/sun8i_tcon_top.c val |= FIELD_PREP(TCON_TOP_HDMI_SRC_MSK, tcon - 1); val 49 drivers/gpu/drm/sun4i/sun8i_tcon_top.c writel(val, tcon_top->regs + TCON_TOP_GATE_SRC_REG); val 30 drivers/gpu/drm/sun4i/sun8i_ui_layer.c u32 val, bld_base, ch_base; val 39 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN; val 41 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val = 0; val 45 drivers/gpu/drm/sun4i/sun8i_ui_layer.c SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val); val 60 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); val 64 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val, val); val 66 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); val 71 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val); val 104 drivers/gpu/drm/sun4i/sun8i_ui_layer.c u32 val; val 119 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; val 121 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val = 0; val 126 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val); val 178 drivers/gpu/drm/sun4i/sun8i_ui_layer.c u32 val, ch_base; val 188 drivers/gpu/drm/sun4i/sun8i_ui_layer.c val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET; val 191 drivers/gpu/drm/sun4i/sun8i_ui_layer.c SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val); val 132 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c u32 val, base; val 140 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c val = SUN8I_SCALER_GSU_CTRL_EN | val 143 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c val = 0; val 145 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val); val 23 drivers/gpu/drm/sun4i/sun8i_vi_layer.c u32 val, bld_base, ch_base; val 32 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN; val 34 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val = 0; val 38 drivers/gpu/drm/sun4i/sun8i_vi_layer.c SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val); val 53 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); val 57 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val, val); val 59 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); val 64 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val); val 218 drivers/gpu/drm/sun4i/sun8i_vi_layer.c u32 val, ch_base; val 228 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET; val 231 drivers/gpu/drm/sun4i/sun8i_vi_layer.c SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val); val 243 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE; val 245 drivers/gpu/drm/sun4i/sun8i_vi_layer.c val = 0; val 249 drivers/gpu/drm/sun4i/sun8i_vi_layer.c SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val); val 912 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c u32 val, base; val 917 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c val = SUN8I_SCALER_VSU_CTRL_EN | val 920 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c val = 0; val 923 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_CTRL(base), val); val 960 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c u32 val; val 963 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c val = SUN50I_SCALER_VSU_SCALE_MODE_UI; val 965 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c val = SUN50I_SCALER_VSU_SCALE_MODE_NORMAL; val 968 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN50I_SCALER_VSU_SCALE_MODE(base), val); val 21 drivers/gpu/drm/tegra/vic.h #define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0) val 23 drivers/gpu/drm/tegra/vic.h #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16) val 167 drivers/gpu/drm/tilcdc/tilcdc_drv.c unsigned long val, void *data) val 172 drivers/gpu/drm/tilcdc/tilcdc_drv.c if (val == CPUFREQ_POSTCHANGE) val 141 drivers/gpu/drm/tilcdc/tilcdc_regs.h u32 val, u32 mask) val 143 drivers/gpu/drm/tilcdc/tilcdc_regs.h tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask)); val 162 drivers/gpu/drm/tiny/repaper.c static int repaper_write_val(struct spi_device *spi, u8 reg, u8 val) val 164 drivers/gpu/drm/tiny/repaper.c return repaper_write_buf(spi, reg, &val, 1); val 170 drivers/gpu/drm/tiny/repaper.c u8 val; val 176 drivers/gpu/drm/tiny/repaper.c ret = repaper_spi_transfer(spi, 0x73, NULL, &val, 1); val 178 drivers/gpu/drm/tiny/repaper.c return ret ? ret : val; val 70 drivers/gpu/drm/tiny/st7586.c u8 *src, *buf, val; val 81 drivers/gpu/drm/tiny/st7586.c val = st7586_lookup[*src++ >> 6] << 5; val 82 drivers/gpu/drm/tiny/st7586.c val |= st7586_lookup[*src++ >> 6] << 2; val 83 drivers/gpu/drm/tiny/st7586.c val |= st7586_lookup[*src++ >> 6] >> 1; val 84 drivers/gpu/drm/tiny/st7586.c *dst++ = val; val 95 drivers/gpu/drm/ttm/ttm_memory.c uint64_t val = 0; val 99 drivers/gpu/drm/ttm/ttm_memory.c val = zone->zone_mem; val 101 drivers/gpu/drm/ttm/ttm_memory.c val = zone->emer_mem; val 103 drivers/gpu/drm/ttm/ttm_memory.c val = zone->max_mem; val 105 drivers/gpu/drm/ttm/ttm_memory.c val = zone->swap_limit; val 107 drivers/gpu/drm/ttm/ttm_memory.c val = zone->used_mem; val 111 drivers/gpu/drm/ttm/ttm_memory.c (unsigned long long) val >> 10); val 124 drivers/gpu/drm/ttm/ttm_memory.c unsigned long val; val 127 drivers/gpu/drm/ttm/ttm_memory.c chars = sscanf(buffer, "%lu", &val); val 131 drivers/gpu/drm/ttm/ttm_memory.c val64 = val; val 185 drivers/gpu/drm/ttm/ttm_memory.c uint64_t val = 0; val 188 drivers/gpu/drm/ttm/ttm_memory.c val = glob->lower_mem_limit; val 191 drivers/gpu/drm/ttm/ttm_memory.c val <<= (PAGE_SHIFT - 10); val 193 drivers/gpu/drm/ttm/ttm_memory.c (unsigned long long) val); val 203 drivers/gpu/drm/ttm/ttm_memory.c unsigned long val; val 207 drivers/gpu/drm/ttm/ttm_memory.c chars = sscanf(buffer, "%lu", &val); val 211 drivers/gpu/drm/ttm/ttm_memory.c val64 = val; val 159 drivers/gpu/drm/ttm/ttm_page_alloc.c unsigned val; val 160 drivers/gpu/drm/ttm/ttm_page_alloc.c chars = sscanf(buffer, "%u", &val); val 165 drivers/gpu/drm/ttm/ttm_page_alloc.c val = val / (PAGE_SIZE >> 10); val 168 drivers/gpu/drm/ttm/ttm_page_alloc.c m->options.max_size = val; val 170 drivers/gpu/drm/ttm/ttm_page_alloc.c m->options.small = val; val 172 drivers/gpu/drm/ttm/ttm_page_alloc.c if (val > NUM_PAGES_TO_ALLOC*8) { val 177 drivers/gpu/drm/ttm/ttm_page_alloc.c } else if (val > NUM_PAGES_TO_ALLOC) { val 181 drivers/gpu/drm/ttm/ttm_page_alloc.c m->options.alloc_size = val; val 192 drivers/gpu/drm/ttm/ttm_page_alloc.c unsigned val = 0; val 195 drivers/gpu/drm/ttm/ttm_page_alloc.c val = m->options.max_size; val 197 drivers/gpu/drm/ttm/ttm_page_alloc.c val = m->options.small; val 199 drivers/gpu/drm/ttm/ttm_page_alloc.c val = m->options.alloc_size; val 201 drivers/gpu/drm/ttm/ttm_page_alloc.c val = val * (PAGE_SIZE >> 10); val 203 drivers/gpu/drm/ttm/ttm_page_alloc.c return snprintf(buffer, PAGE_SIZE, "%u\n", val); val 207 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c unsigned val; val 209 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c chars = sscanf(buffer, "%u", &val); val 214 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c val = val / (PAGE_SIZE >> 10); val 217 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c m->options.max_size = val; val 219 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c m->options.small = val; val 221 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c if (val > NUM_PAGES_TO_ALLOC*8) { val 226 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c } else if (val > NUM_PAGES_TO_ALLOC) { val 230 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c m->options.alloc_size = val; val 241 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c unsigned val = 0; val 244 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c val = m->options.max_size; val 246 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c val = m->options.small; val 248 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c val = m->options.alloc_size; val 250 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c val = val * (PAGE_SIZE >> 10); val 252 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c return snprintf(buffer, PAGE_SIZE, "%u\n", val); val 31 drivers/gpu/drm/tve200/tve200_display.c u32 val; val 50 drivers/gpu/drm/tve200/tve200_display.c val = readl(priv->regs + TVE200_CTRL); val 52 drivers/gpu/drm/tve200/tve200_display.c if (!(val & TVE200_VSTSTYPE_BITS)) { val 55 drivers/gpu/drm/tve200/tve200_display.c val |= TVE200_VSTSTYPE_VAI; val 58 drivers/gpu/drm/tve200/tve200_display.c val &= ~TVE200_VSTSTYPE_BITS; val 60 drivers/gpu/drm/tve200/tve200_display.c writel(val, priv->regs + TVE200_CTRL); val 102 drivers/gpu/drm/udl/udl_connector.c uint64_t val) val 22 drivers/gpu/drm/udl/udl_modeset.c static char *udl_set_register(char *buf, u8 reg, u8 val) val 27 drivers/gpu/drm/udl/udl_modeset.c *buf++ = val; val 172 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) val 175 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) val 178 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) val 181 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) val 68 drivers/gpu/drm/vc4/vc4_crtc.c #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) val 95 drivers/gpu/drm/vc4/vc4_crtc.c u32 val; val 110 drivers/gpu/drm/vc4/vc4_crtc.c val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel)); val 119 drivers/gpu/drm/vc4/vc4_crtc.c *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); val 126 drivers/gpu/drm/vc4/vc4_crtc.c if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) val 98 drivers/gpu/drm/vc4/vc4_dpi.c #define DPI_WRITE(offset, val) writel(val, dpi->regs + (offset)) val 479 drivers/gpu/drm/vc4/vc4_drv.h #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) val 481 drivers/gpu/drm/vc4/vc4_drv.h #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) val 548 drivers/gpu/drm/vc4/vc4_dsi.c dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) val 557 drivers/gpu/drm/vc4/vc4_dsi.c writel(val, dsi->regs + offset); val 561 drivers/gpu/drm/vc4/vc4_dsi.c *dsi->reg_dma_mem = val; val 584 drivers/gpu/drm/vc4/vc4_dsi.c #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val) val 587 drivers/gpu/drm/vc4/vc4_dsi.c #define DSI_PORT_WRITE(offset, val) \ val 588 drivers/gpu/drm/vc4/vc4_dsi.c DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val) val 98 drivers/gpu/drm/vc4/vc4_hdmi.c #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) val 100 drivers/gpu/drm/vc4/vc4_hdmi.c #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) val 1176 drivers/gpu/drm/vc4/vc4_hdmi.c u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); val 1178 drivers/gpu/drm/vc4/vc4_hdmi.c msg->msg[i] = val & 0xff; val 1179 drivers/gpu/drm/vc4/vc4_hdmi.c msg->msg[i + 1] = (val >> 8) & 0xff; val 1180 drivers/gpu/drm/vc4/vc4_hdmi.c msg->msg[i + 2] = (val >> 16) & 0xff; val 1181 drivers/gpu/drm/vc4/vc4_hdmi.c msg->msg[i + 3] = (val >> 24) & 0xff; val 1218 drivers/gpu/drm/vc4/vc4_hdmi.c u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); val 1220 drivers/gpu/drm/vc4/vc4_hdmi.c val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | val 1223 drivers/gpu/drm/vc4/vc4_hdmi.c val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | val 1227 drivers/gpu/drm/vc4/vc4_hdmi.c HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | val 1229 drivers/gpu/drm/vc4/vc4_hdmi.c HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); val 1250 drivers/gpu/drm/vc4/vc4_hdmi.c HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | val 1270 drivers/gpu/drm/vc4/vc4_hdmi.c u32 val; val 1280 drivers/gpu/drm/vc4/vc4_hdmi.c val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); val 1281 drivers/gpu/drm/vc4/vc4_hdmi.c val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; val 1282 drivers/gpu/drm/vc4/vc4_hdmi.c HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); val 1283 drivers/gpu/drm/vc4/vc4_hdmi.c val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; val 1284 drivers/gpu/drm/vc4/vc4_hdmi.c val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; val 1285 drivers/gpu/drm/vc4/vc4_hdmi.c val |= VC4_HDMI_CEC_START_XMIT_BEGIN; val 1287 drivers/gpu/drm/vc4/vc4_hdmi.c HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); val 394 drivers/gpu/drm/vc4/vc4_kms.c u64 val = ctm->matrix[i]; val 396 drivers/gpu/drm/vc4/vc4_kms.c val &= ~BIT_ULL(63); val 397 drivers/gpu/drm/vc4/vc4_kms.c if (val > BIT_ULL(32)) val 208 drivers/gpu/drm/vc4/vc4_plane.c static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val) val 223 drivers/gpu/drm/vc4/vc4_plane.c vc4_state->dlist[vc4_state->dlist_count++] = val; val 56 drivers/gpu/drm/vc4/vc4_render_cl.c static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val) val 58 drivers/gpu/drm/vc4/vc4_render_cl.c *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val; val 62 drivers/gpu/drm/vc4/vc4_render_cl.c static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val) val 64 drivers/gpu/drm/vc4/vc4_render_cl.c *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val; val 68 drivers/gpu/drm/vc4/vc4_render_cl.c static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val) val 70 drivers/gpu/drm/vc4/vc4_render_cl.c *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val; val 145 drivers/gpu/drm/vc4/vc4_txp.c #define TXP_WRITE(offset, val) writel(val, txp->regs + (offset)) val 173 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset)) val 130 drivers/gpu/drm/via/via_drv.h u32 val) val 132 drivers/gpu/drm/via/via_drv.h writel(val, (void __iomem *)(dev_priv->mmio->handle + reg)); val 136 drivers/gpu/drm/via/via_drv.h u32 val) val 138 drivers/gpu/drm/via/via_drv.h writeb(val, (void __iomem *)(dev_priv->mmio->handle + reg)); val 142 drivers/gpu/drm/via/via_drv.h u32 reg, u32 mask, u32 val) val 147 drivers/gpu/drm/via/via_drv.h tmp = (tmp & ~mask) | (val & mask); val 87 drivers/gpu/drm/via/via_video.c (fx->ms / 10) * (HZ / 100), *lock != fx->val); val 304 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c u32 val; val 306 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c val = upper_32_bits(header->handle); val 307 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val); val 309 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c val = lower_32_bits(header->handle); val 310 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c val |= header->cb_context & SVGA_CB_CONTEXT_MASK; val 311 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val); val 262 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, val 1214 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, val 1220 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c switch (val) { val 644 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h u32 val; val 648 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h val = inl(dev_priv->io_start + VMWGFX_VALUE_PORT); val 651 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h return val; val 748 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_ctx_validation_info *val; val 751 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c list_for_each_entry(val, &sw_context->ctx_list, head) { val 752 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_binding_rebind_all(val->cur); val 759 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_rebind_all_dx_query(val->ctx); val 398 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint64_t val); val 402 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint64_t val); val 407 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint64_t *val); val 482 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c static void vmw_mob_assign_ppn(u32 **addr, dma_addr_t val) val 484 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c *((u64 *) *addr) = val >> PAGE_SHIFT; val 488 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c static void vmw_mob_assign_ppn(u32 **addr, dma_addr_t val) val 490 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c *(*addr)++ = val >> PAGE_SHIFT; val 389 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_validation_res_node *val; val 394 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val = container_of(val_private, typeof(*val), private); val 395 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->dirty_set = 1; val 397 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->dirty = (dirty & VMW_RES_DIRTY_SET) ? 1 : 0; val 416 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_validation_res_node *val; val 418 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val = container_of(val_private, typeof(*val), private); val 420 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->switching_backup = 1; val 421 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c if (val->first_usage) val 422 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->no_buffer_needed = 1; val 424 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->new_backup = vbo; val 425 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->new_backup_offset = backup_offset; val 440 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_validation_res_node *val; val 445 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(val, &ctx->resource_list, head) { val 446 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_resource *res = val->res; val 448 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c ret = vmw_resource_reserve(res, intr, val->no_buffer_needed); val 452 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->reserved = 1; val 481 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_validation_res_node *val; val 485 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(val, &ctx->resource_list, head) { val 486 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c if (val->reserved) val 487 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c vmw_resource_unreserve(val->res, val 492 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(val, &ctx->resource_list, head) { val 493 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c if (val->reserved) val 494 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c vmw_resource_unreserve(val->res, val 495 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->dirty_set, val 496 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->dirty, val 497 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->switching_backup, val 498 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->new_backup, val 499 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val->new_backup_offset); val 597 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_validation_res_node *val; val 600 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(val, &ctx->resource_list, head) { val 601 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_resource *res = val->res; val 640 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_validation_res_node *val; val 648 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(val, &ctx->resource_list, head) val 649 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c (void) drm_ht_remove_item(ctx->ht, &val->hash); val 651 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(val, &ctx->resource_ctx_list, head) val 652 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c (void) drm_ht_remove_item(ctx->ht, &val->hash); val 668 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct vmw_validation_res_node *val; val 676 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(val, &ctx->resource_list, head) val 677 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c vmw_resource_unreference(&val->res); val 229 drivers/gpu/drm/vmwgfx/vmwgfx_validation.h static inline unsigned int vmw_validation_align(unsigned int val) val 231 drivers/gpu/drm/vmwgfx/vmwgfx_validation.h return ALIGN(val, sizeof(long)); val 20 drivers/gpu/drm/zte/zx_drm_drv.h static inline void zx_writel(void __iomem *reg, u32 val) val 22 drivers/gpu/drm/zte/zx_drm_drv.h writel_relaxed(val, reg); val 25 drivers/gpu/drm/zte/zx_drm_drv.h static inline void zx_writel_mask(void __iomem *reg, u32 mask, u32 val) val 30 drivers/gpu/drm/zte/zx_drm_drv.h tmp = (tmp & ~mask) | (val & mask); val 59 drivers/gpu/drm/zte/zx_hdmi.c static inline void hdmi_writeb(struct zx_hdmi *hdmi, u16 offset, u8 val) val 61 drivers/gpu/drm/zte/zx_hdmi.c writel_relaxed(val, hdmi->mmio + offset * 4); val 65 drivers/gpu/drm/zte/zx_hdmi.c u8 mask, u8 val) val 70 drivers/gpu/drm/zte/zx_hdmi.c tmp = (tmp & ~mask) | (val & mask); val 134 drivers/gpu/drm/zte/zx_plane.c u32 val = 0; val 137 drivers/gpu/drm/zte/zx_plane.c val = 0; val 139 drivers/gpu/drm/zte/zx_plane.c val = RSZ_PARA_STEP((src << 16) / dst); val 141 drivers/gpu/drm/zte/zx_plane.c val = RSZ_DATA_STEP(src / dst) | val 144 drivers/gpu/drm/zte/zx_plane.c return val; val 339 drivers/gpu/drm/zte/zx_vou.c cfg->val << shift); val 364 drivers/gpu/drm/zte/zx_vou.c u32 val; val 370 drivers/gpu/drm/zte/zx_vou.c val = V_ACTIVE((interlaced ? vm.vactive / 2 : vm.vactive) - 1); val 371 drivers/gpu/drm/zte/zx_vou.c val |= H_ACTIVE(vm.hactive - 1); val 372 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_active, val); val 374 drivers/gpu/drm/zte/zx_vou.c val = SYNC_WIDE(vm.hsync_len - 1); val 375 drivers/gpu/drm/zte/zx_vou.c val |= BACK_PORCH(vm.hback_porch - 1); val 376 drivers/gpu/drm/zte/zx_vou.c val |= FRONT_PORCH(vm.hfront_porch - 1); val 377 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_htiming, val); val 379 drivers/gpu/drm/zte/zx_vou.c val = SYNC_WIDE(vm.vsync_len - 1); val 380 drivers/gpu/drm/zte/zx_vou.c val |= BACK_PORCH(vm.vback_porch - 1); val 381 drivers/gpu/drm/zte/zx_vou.c val |= FRONT_PORCH(vm.vfront_porch - 1); val 382 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_vtiming, val); val 388 drivers/gpu/drm/zte/zx_vou.c val = zx_readl(vou->timing + SEC_V_ACTIVE); val 389 drivers/gpu/drm/zte/zx_vou.c val &= ~mask; val 390 drivers/gpu/drm/zte/zx_vou.c val |= ((vm.vactive / 2 - 1) << shift) & mask; val 391 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + SEC_V_ACTIVE, val); val 393 drivers/gpu/drm/zte/zx_vou.c val = SYNC_WIDE(vm.vsync_len - 1); val 398 drivers/gpu/drm/zte/zx_vou.c val |= BACK_PORCH(vm.vback_porch); val 399 drivers/gpu/drm/zte/zx_vou.c val |= FRONT_PORCH(vm.vfront_porch - 1); val 400 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->sec_vtiming, val); val 413 drivers/gpu/drm/zte/zx_vou.c val = H_SHIFT_VAL; val 415 drivers/gpu/drm/zte/zx_vou.c val |= V_SHIFT_VAL << 16; val 416 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->timing_shift, val); val 54 drivers/gpu/drm/zte/zx_vou.h enum vou_div_val val; val 213 drivers/gpu/host1x/hw/channel_hw.c u32 val; val 218 drivers/gpu/host1x/hw/channel_hw.c val = host1x_hypervisor_readl( val 220 drivers/gpu/host1x/hw/channel_hw.c val |= BIT(ch->id % 32); val 222 drivers/gpu/host1x/hw/channel_hw.c host, val, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32)); val 41 drivers/gpu/host1x/hw/debug_hw.c static unsigned int show_channel_command(struct output *o, u32 val, val 46 drivers/gpu/host1x/hw/debug_hw.c opcode = val >> 28; val 50 drivers/gpu/host1x/hw/debug_hw.c mask = val & 0x3f; val 53 drivers/gpu/host1x/hw/debug_hw.c val >> 6 & 0x3ff, val 54 drivers/gpu/host1x/hw/debug_hw.c val >> 16 & 0xfff, mask); val 58 drivers/gpu/host1x/hw/debug_hw.c host1x_debug_cont(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff); val 62 drivers/gpu/host1x/hw/debug_hw.c num = val & 0xffff; val 64 drivers/gpu/host1x/hw/debug_hw.c val >> 16 & 0xfff); val 71 drivers/gpu/host1x/hw/debug_hw.c num = val & 0xffff; val 73 drivers/gpu/host1x/hw/debug_hw.c val >> 16 & 0xfff); val 80 drivers/gpu/host1x/hw/debug_hw.c mask = val & 0xffff; val 82 drivers/gpu/host1x/hw/debug_hw.c val >> 16 & 0xfff, mask); val 90 drivers/gpu/host1x/hw/debug_hw.c val >> 16 & 0xfff, val & 0xffff); val 94 drivers/gpu/host1x/hw/debug_hw.c host1x_debug_cont(o, "RESTART(offset=%08x)\n", val << 4); val 99 drivers/gpu/host1x/hw/debug_hw.c val >> 16 & 0xfff, val >> 15 & 0x1, val 100 drivers/gpu/host1x/hw/debug_hw.c val >> 14 & 0x1, val & 0x3fff); val 106 drivers/gpu/host1x/hw/debug_hw.c val & 0x3fffff); val 110 drivers/gpu/host1x/hw/debug_hw.c host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff); val 114 drivers/gpu/host1x/hw/debug_hw.c *payload = val & 0xffff; val 123 drivers/gpu/host1x/hw/debug_hw.c val & 0x3fffff); val 137 drivers/gpu/host1x/hw/debug_hw.c val & 0x3fff); val 142 drivers/gpu/host1x/hw/debug_hw.c subop = val >> 24 & 0xf; val 145 drivers/gpu/host1x/hw/debug_hw.c val & 0xff); val 148 drivers/gpu/host1x/hw/debug_hw.c val & 0xff); val 150 drivers/gpu/host1x/hw/debug_hw.c host1x_debug_cont(o, "EXTEND_UNKNOWN(%08x)\n", val); val 180 drivers/gpu/host1x/hw/debug_hw.c u32 val = *(map_addr + offset / 4 + i); val 183 drivers/gpu/host1x/hw/debug_hw.c host1x_debug_output(o, "%08x: %08x: ", addr, val); val 184 drivers/gpu/host1x/hw/debug_hw.c data_count = show_channel_command(o, val, &payload); val 186 drivers/gpu/host1x/hw/debug_hw.c host1x_debug_cont(o, "%08x%s", val, val 21 drivers/gpu/host1x/hw/debug_hw_1x01.c u32 val, base, baseval; val 49 drivers/gpu/host1x/hw/debug_hw_1x01.c val = cbread & 0xffff; val 51 drivers/gpu/host1x/hw/debug_hw_1x01.c cbread >> 24, baseval + val, base, val 52 drivers/gpu/host1x/hw/debug_hw_1x01.c baseval, val); val 71 drivers/gpu/host1x/hw/debug_hw_1x01.c u32 val, rd_ptr, wr_ptr, start, end; val 76 drivers/gpu/host1x/hw/debug_hw_1x01.c val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT); val 77 drivers/gpu/host1x/hw/debug_hw_1x01.c host1x_debug_output(o, "FIFOSTAT %08x\n", val); val 78 drivers/gpu/host1x/hw/debug_hw_1x01.c if (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) { val 88 drivers/gpu/host1x/hw/debug_hw_1x01.c val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS); val 89 drivers/gpu/host1x/hw/debug_hw_1x01.c rd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val); val 90 drivers/gpu/host1x/hw/debug_hw_1x01.c wr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val); val 92 drivers/gpu/host1x/hw/debug_hw_1x01.c val = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id)); val 93 drivers/gpu/host1x/hw/debug_hw_1x01.c start = HOST1X_SYNC_CF_SETUP_BASE_V(val); val 94 drivers/gpu/host1x/hw/debug_hw_1x01.c end = HOST1X_SYNC_CF_SETUP_LIMIT_V(val); val 102 drivers/gpu/host1x/hw/debug_hw_1x01.c val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ); val 105 drivers/gpu/host1x/hw/debug_hw_1x01.c host1x_debug_output(o, "%08x: ", val); val 106 drivers/gpu/host1x/hw/debug_hw_1x01.c data_count = show_channel_command(o, val, NULL); val 108 drivers/gpu/host1x/hw/debug_hw_1x01.c host1x_debug_cont(o, "%08x%s", val, val 61 drivers/gpu/host1x/hw/debug_hw_1x06.c u32 val; val 65 drivers/gpu/host1x/hw/debug_hw_1x06.c val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT); val 66 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_debug_output(o, "CMDFIFO_STAT %08x\n", val); val 67 drivers/gpu/host1x/hw/debug_hw_1x06.c if (val & HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY) { val 72 drivers/gpu/host1x/hw/debug_hw_1x06.c val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA); val 73 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_debug_output(o, "CMDFIFO_RDATA %08x\n", val); val 79 drivers/gpu/host1x/hw/debug_hw_1x06.c val = 0; val 80 drivers/gpu/host1x/hw/debug_hw_1x06.c val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE; val 81 drivers/gpu/host1x/hw/debug_hw_1x06.c val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id); val 82 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTRL); val 84 drivers/gpu/host1x/hw/debug_hw_1x06.c val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_PEEK_PTRS); val 85 drivers/gpu/host1x/hw/debug_hw_1x06.c rd_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(val); val 86 drivers/gpu/host1x/hw/debug_hw_1x06.c wr_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(val); val 88 drivers/gpu/host1x/hw/debug_hw_1x06.c val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_SETUP(ch->id)); val 89 drivers/gpu/host1x/hw/debug_hw_1x06.c start = HOST1X_HV_CMDFIFO_SETUP_BASE_V(val); val 90 drivers/gpu/host1x/hw/debug_hw_1x06.c end = HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(val); val 93 drivers/gpu/host1x/hw/debug_hw_1x06.c val = 0; val 94 drivers/gpu/host1x/hw/debug_hw_1x06.c val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE; val 95 drivers/gpu/host1x/hw/debug_hw_1x06.c val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id); val 96 drivers/gpu/host1x/hw/debug_hw_1x06.c val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(rd_ptr); val 97 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_hypervisor_writel(host, val, val 100 drivers/gpu/host1x/hw/debug_hw_1x06.c val = host1x_hypervisor_readl(host, val 105 drivers/gpu/host1x/hw/debug_hw_1x06.c rd_ptr - start, val); val 106 drivers/gpu/host1x/hw/debug_hw_1x06.c data_count = show_channel_command(o, val, &payload); val 108 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_debug_cont(o, "%08x%s", val, val 159 drivers/gpu/host1x/syncpt.c u32 val; val 161 drivers/gpu/host1x/syncpt.c val = host1x_hw_syncpt_load(sp->host, sp); val 162 drivers/gpu/host1x/syncpt.c trace_host1x_syncpt_load_min(sp->id, val); val 164 drivers/gpu/host1x/syncpt.c return val; val 212 drivers/gpu/host1x/syncpt.c u32 val; val 226 drivers/gpu/host1x/syncpt.c val = host1x_hw_syncpt_load(sp->host, sp); val 229 drivers/gpu/host1x/syncpt.c *value = val; val 47 drivers/gpu/ipu-v3/ipu-common.c u32 val; val 49 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_SRM_PRI2); val 50 drivers/gpu/ipu-v3/ipu-common.c val &= ~DP_S_SRM_MODE_MASK; val 51 drivers/gpu/ipu-v3/ipu-common.c val |= sync ? DP_S_SRM_MODE_NEXT_FRAME : val 53 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_SRM_PRI2); val 438 drivers/gpu/ipu-v3/ipu-common.c u32 val; val 442 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_DISP_GEN); val 445 drivers/gpu/ipu-v3/ipu-common.c val |= IPU_DI0_COUNTER_RELEASE; val 447 drivers/gpu/ipu-v3/ipu-common.c val |= IPU_DI1_COUNTER_RELEASE; val 449 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_DISP_GEN); val 451 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CONF); val 452 drivers/gpu/ipu-v3/ipu-common.c val |= mask; val 453 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CONF); val 464 drivers/gpu/ipu-v3/ipu-common.c u32 val; val 468 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CONF); val 469 drivers/gpu/ipu-v3/ipu-common.c val &= ~mask; val 470 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CONF); val 472 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_DISP_GEN); val 475 drivers/gpu/ipu-v3/ipu-common.c val &= ~IPU_DI0_COUNTER_RELEASE; val 477 drivers/gpu/ipu-v3/ipu-common.c val &= ~IPU_DI1_COUNTER_RELEASE; val 479 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_DISP_GEN); val 569 drivers/gpu/ipu-v3/ipu-common.c u32 val; val 574 drivers/gpu/ipu-v3/ipu-common.c val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); val 575 drivers/gpu/ipu-v3/ipu-common.c val |= idma_mask(channel->num); val 576 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); val 610 drivers/gpu/ipu-v3/ipu-common.c u32 val; val 616 drivers/gpu/ipu-v3/ipu-common.c val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); val 617 drivers/gpu/ipu-v3/ipu-common.c val &= ~idma_mask(channel->num); val 618 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); val 640 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); val 641 drivers/gpu/ipu-v3/ipu-common.c val &= ~idma_mask(channel->num); val 642 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); val 660 drivers/gpu/ipu-v3/ipu-common.c u32 val; val 664 drivers/gpu/ipu-v3/ipu-common.c val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); val 666 drivers/gpu/ipu-v3/ipu-common.c val |= 1 << (channel->num % 32); val 668 drivers/gpu/ipu-v3/ipu-common.c val &= ~(1 << (channel->num % 32)); val 669 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); val 698 drivers/gpu/ipu-v3/ipu-common.c u32 val, mask; val 705 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CONF); val 707 drivers/gpu/ipu-v3/ipu-common.c val |= mask; val 709 drivers/gpu/ipu-v3/ipu-common.c val &= ~mask; val 710 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CONF); val 722 drivers/gpu/ipu-v3/ipu-common.c u32 val; val 726 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CONF); val 728 drivers/gpu/ipu-v3/ipu-common.c val |= IPU_CONF_IC_INPUT; val 730 drivers/gpu/ipu-v3/ipu-common.c val &= ~IPU_CONF_IC_INPUT; val 733 drivers/gpu/ipu-v3/ipu-common.c val |= IPU_CONF_CSI_SEL; val 735 drivers/gpu/ipu-v3/ipu-common.c val &= ~IPU_CONF_CSI_SEL; val 737 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CONF); val 750 drivers/gpu/ipu-v3/ipu-common.c u32 val; val 812 drivers/gpu/ipu-v3/ipu-common.c src_reg |= link->src.val; val 819 drivers/gpu/ipu-v3/ipu-common.c sink_reg |= link->sink.val; val 109 drivers/gpu/ipu-v3/ipu-cpmem.c u32 val; val 113 drivers/gpu/ipu-v3/ipu-cpmem.c val = readl(&base->word[word].data[i]); val 114 drivers/gpu/ipu-v3/ipu-cpmem.c val &= ~(mask << ofs); val 115 drivers/gpu/ipu-v3/ipu-cpmem.c val |= v << ofs; val 116 drivers/gpu/ipu-v3/ipu-cpmem.c writel(val, &base->word[word].data[i]); val 119 drivers/gpu/ipu-v3/ipu-cpmem.c val = readl(&base->word[word].data[i + 1]); val 120 drivers/gpu/ipu-v3/ipu-cpmem.c val &= ~(mask >> (ofs ? (32 - ofs) : 0)); val 121 drivers/gpu/ipu-v3/ipu-cpmem.c val |= v >> (ofs ? (32 - ofs) : 0); val 122 drivers/gpu/ipu-v3/ipu-cpmem.c writel(val, &base->word[word].data[i + 1]); val 135 drivers/gpu/ipu-v3/ipu-cpmem.c u32 val = 0; val 139 drivers/gpu/ipu-v3/ipu-cpmem.c val = (readl(&base->word[word].data[i]) >> ofs) & mask; val 146 drivers/gpu/ipu-v3/ipu-cpmem.c val |= tmp << (ofs ? (32 - ofs) : 0); val 149 drivers/gpu/ipu-v3/ipu-cpmem.c return val; val 261 drivers/gpu/ipu-v3/ipu-cpmem.c u32 val; val 266 drivers/gpu/ipu-v3/ipu-cpmem.c val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num)); val 267 drivers/gpu/ipu-v3/ipu-cpmem.c val |= 1 << (ch->num % 32); val 268 drivers/gpu/ipu-v3/ipu-cpmem.c ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num)); val 626 drivers/gpu/ipu-v3/ipu-cpmem.c u32 val; val 636 drivers/gpu/ipu-v3/ipu-cpmem.c val = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA); val 637 drivers/gpu/ipu-v3/ipu-cpmem.c val |= BIT(ch->num); val 638 drivers/gpu/ipu-v3/ipu-cpmem.c ipu_idmac_write(ipu, val, IDMAC_SEP_ALPHA); val 253 drivers/gpu/ipu-v3/ipu-dc.c u32 val; val 255 drivers/gpu/ipu-v3/ipu-dc.c val = readl(dc->base + DC_WR_CH_CONF); val 256 drivers/gpu/ipu-v3/ipu-dc.c val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; val 257 drivers/gpu/ipu-v3/ipu-dc.c writel(val, dc->base + DC_WR_CH_CONF); val 398 drivers/gpu/ipu-v3/ipu-di.c uint32_t val; val 492 drivers/gpu/ipu-v3/ipu-di.c val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT; val 494 drivers/gpu/ipu-v3/ipu-di.c val |= DI_GEN_DI_CLK_EXT; val 495 drivers/gpu/ipu-v3/ipu-di.c ipu_di_write(di, val, DI_GENERAL); val 139 drivers/gpu/ipu-v3/ipu-pre.c u32 val; val 148 drivers/gpu/ipu-v3/ipu-pre.c val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN | val 152 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_CTRL); val 171 drivers/gpu/ipu-v3/ipu-pre.c u32 val; val 183 drivers/gpu/ipu-v3/ipu-pre.c val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) | val 188 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL); val 190 drivers/gpu/ipu-v3/ipu-pre.c val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) | val 192 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE); val 194 drivers/gpu/ipu-v3/ipu-pre.c val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride); val 195 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH); val 197 drivers/gpu/ipu-v3/ipu-pre.c val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) | val 200 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL); val 202 drivers/gpu/ipu-v3/ipu-pre.c val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) | val 204 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE); val 206 drivers/gpu/ipu-v3/ipu-pre.c val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride); val 207 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH); val 211 drivers/gpu/ipu-v3/ipu-pre.c val = readl(pre->regs + IPU_PRE_TPR_CTRL); val 212 drivers/gpu/ipu-v3/ipu-pre.c val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK; val 215 drivers/gpu/ipu-v3/ipu-pre.c val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF; val 217 drivers/gpu/ipu-v3/ipu-pre.c val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED; val 219 drivers/gpu/ipu-v3/ipu-pre.c val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT; val 221 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_TPR_CTRL); val 223 drivers/gpu/ipu-v3/ipu-pre.c val = readl(pre->regs + IPU_PRE_CTRL); val 224 drivers/gpu/ipu-v3/ipu-pre.c val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE | val 227 drivers/gpu/ipu-v3/ipu-pre.c val &= ~IPU_PRE_CTRL_BLOCK_EN; val 229 drivers/gpu/ipu-v3/ipu-pre.c val |= IPU_PRE_CTRL_BLOCK_EN; val 230 drivers/gpu/ipu-v3/ipu-pre.c writel(val, pre->regs + IPU_PRE_CTRL); val 237 drivers/gpu/ipu-v3/ipu-pre.c u32 val; val 251 drivers/gpu/ipu-v3/ipu-pre.c val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS); val 253 drivers/gpu/ipu-v3/ipu-pre.c (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) & val 205 drivers/gpu/ipu-v3/ipu-prg.c u32 val, mux; val 218 drivers/gpu/ipu-v3/ipu-prg.c regmap_read(prg->iomuxc_gpr, IOMUXC_GPR5, &val); val 219 drivers/gpu/ipu-v3/ipu-prg.c if (((val >> shift) & 0x3) == mux) { val 247 drivers/gpu/ipu-v3/ipu-prg.c u32 val; val 258 drivers/gpu/ipu-v3/ipu-prg.c val = readl(prg->regs + IPU_PRG_CTL); val 259 drivers/gpu/ipu-v3/ipu-prg.c val |= IPU_PRG_CTL_BYPASS(prg_chan); val 260 drivers/gpu/ipu-v3/ipu-prg.c writel(val, prg->regs + IPU_PRG_CTL); val 262 drivers/gpu/ipu-v3/ipu-prg.c val = IPU_PRG_REG_UPDATE_REG_UPDATE; val 263 drivers/gpu/ipu-v3/ipu-prg.c writel(val, prg->regs + IPU_PRG_REG_UPDATE); val 281 drivers/gpu/ipu-v3/ipu-prg.c u32 val; val 304 drivers/gpu/ipu-v3/ipu-prg.c val = (stride - 1) & IPU_PRG_STRIDE_STRIDE_MASK; val 305 drivers/gpu/ipu-v3/ipu-prg.c writel(val, prg->regs + IPU_PRG_STRIDE(prg_chan)); val 307 drivers/gpu/ipu-v3/ipu-prg.c val = ((height & IPU_PRG_HEIGHT_PRE_HEIGHT_MASK) << val 311 drivers/gpu/ipu-v3/ipu-prg.c writel(val, prg->regs + IPU_PRG_HEIGHT(prg_chan)); val 313 drivers/gpu/ipu-v3/ipu-prg.c val = ipu_pre_get_baddr(prg->pres[chan->used_pre]); val 314 drivers/gpu/ipu-v3/ipu-prg.c *eba = val; val 315 drivers/gpu/ipu-v3/ipu-prg.c writel(val, prg->regs + IPU_PRG_BADDR(prg_chan)); val 317 drivers/gpu/ipu-v3/ipu-prg.c val = readl(prg->regs + IPU_PRG_CTL); val 319 drivers/gpu/ipu-v3/ipu-prg.c val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK << val 321 drivers/gpu/ipu-v3/ipu-prg.c val |= IPU_PRG_CTL_SOFT_ARID(prg_chan, axi_id); val 323 drivers/gpu/ipu-v3/ipu-prg.c val &= ~IPU_PRG_CTL_BYPASS(prg_chan); val 324 drivers/gpu/ipu-v3/ipu-prg.c writel(val, prg->regs + IPU_PRG_CTL); val 326 drivers/gpu/ipu-v3/ipu-prg.c val = IPU_PRG_REG_UPDATE_REG_UPDATE; val 327 drivers/gpu/ipu-v3/ipu-prg.c writel(val, prg->regs + IPU_PRG_REG_UPDATE); val 330 drivers/gpu/ipu-v3/ipu-prg.c readl_poll_timeout(prg->regs + IPU_PRG_STATUS, val, val 331 drivers/gpu/ipu-v3/ipu-prg.c (val & IPU_PRG_STATUS_BUFFER0_READY(prg_chan)) && val 332 drivers/gpu/ipu-v3/ipu-prg.c (val & IPU_PRG_STATUS_BUFFER1_READY(prg_chan)), val 363 drivers/gpu/ipu-v3/ipu-prg.c u32 val; val 406 drivers/gpu/ipu-v3/ipu-prg.c val = readl(prg->regs + IPU_PRG_CTL); val 407 drivers/gpu/ipu-v3/ipu-prg.c val |= IPU_PRG_CTL_SHADOW_EN; val 408 drivers/gpu/ipu-v3/ipu-prg.c writel(val, prg->regs + IPU_PRG_CTL); val 40 drivers/gpu/ipu-v3/ipu-smfc.c u32 val, shift; val 45 drivers/gpu/ipu-v3/ipu-smfc.c val = readl(priv->base + SMFC_BS); val 46 drivers/gpu/ipu-v3/ipu-smfc.c val &= ~(0xf << shift); val 47 drivers/gpu/ipu-v3/ipu-smfc.c val |= burstsize << shift; val 48 drivers/gpu/ipu-v3/ipu-smfc.c writel(val, priv->base + SMFC_BS); val 60 drivers/gpu/ipu-v3/ipu-smfc.c u32 val, shift; val 65 drivers/gpu/ipu-v3/ipu-smfc.c val = readl(priv->base + SMFC_MAP); val 66 drivers/gpu/ipu-v3/ipu-smfc.c val &= ~(0x7 << shift); val 67 drivers/gpu/ipu-v3/ipu-smfc.c val |= ((csi_id << 2) | mipi_id) << shift; val 68 drivers/gpu/ipu-v3/ipu-smfc.c writel(val, priv->base + SMFC_MAP); val 80 drivers/gpu/ipu-v3/ipu-smfc.c u32 val, shift; val 85 drivers/gpu/ipu-v3/ipu-smfc.c val = readl(priv->base + SMFC_WMC); val 86 drivers/gpu/ipu-v3/ipu-smfc.c val &= ~(0x3f << shift); val 87 drivers/gpu/ipu-v3/ipu-smfc.c val |= ((clr_level << 3) | set_level) << shift; val 88 drivers/gpu/ipu-v3/ipu-smfc.c writel(val, priv->base + SMFC_WMC); val 49 drivers/greybus/interface.c u16 attr, u32 *val) val 52 drivers/greybus/interface.c attr, DME_SELECTOR_INDEX_NULL, val); val 19 drivers/greybus/module.c long val; val 22 drivers/greybus/module.c ret = kstrtol(buf, 0, &val); val 26 drivers/greybus/module.c if (!val) val 463 drivers/hid/hid-asus.c int val; val 472 drivers/hid/hid-asus.c val = POWER_SUPPLY_STATUS_CHARGING; val 475 drivers/hid/hid-asus.c val = POWER_SUPPLY_STATUS_FULL; val 479 drivers/hid/hid-asus.c val = POWER_SUPPLY_STATUS_DISCHARGING; val 482 drivers/hid/hid-asus.c drvdata->battery_stat = val; val 533 drivers/hid/hid-asus.c union power_supply_propval *val) val 549 drivers/hid/hid-asus.c val->intval = drvdata->battery_stat; val 551 drivers/hid/hid-asus.c val->intval = drvdata->battery_capacity; val 554 drivers/hid/hid-asus.c val->intval = 1; val 557 drivers/hid/hid-asus.c val->intval = POWER_SUPPLY_SCOPE_DEVICE; val 560 drivers/hid/hid-asus.c val->strval = drvdata->hdev->name; val 304 drivers/hid/hid-cougar.c static int cougar_param_set_g6_is_space(const char *val, val 309 drivers/hid/hid-cougar.c ret = param_set_bool(val, kp); val 591 drivers/hid/hid-debug.c int val = nibble & 0x7; val 593 drivers/hid/hid-debug.c val = -((0x7 & ~val) +1); val 594 drivers/hid/hid-debug.c seq_printf(f, "^%d", val); val 109 drivers/hid/hid-elan.c static unsigned int elan_convert_res(char val) val 115 drivers/hid/hid-elan.c return (val * 10 + 790) * 10 / 254; val 83 drivers/hid/hid-input.c unsigned int cur_idx, unsigned int val); val 371 drivers/hid/hid-input.c union power_supply_propval *val) val 380 drivers/hid/hid-input.c val->intval = 1; val 393 drivers/hid/hid-input.c val->intval = value; val 397 drivers/hid/hid-input.c val->strval = dev->name; val 412 drivers/hid/hid-input.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 414 drivers/hid/hid-input.c val->intval = POWER_SUPPLY_STATUS_FULL; val 416 drivers/hid/hid-input.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 420 drivers/hid/hid-input.c val->intval = POWER_SUPPLY_SCOPE_DEVICE; val 1238 drivers/hid/hid-logitech-hidpp.c union power_supply_propval *val) val 1245 drivers/hid/hid-logitech-hidpp.c val->intval = hidpp->battery.status; val 1248 drivers/hid/hid-logitech-hidpp.c val->intval = hidpp->battery.capacity; val 1251 drivers/hid/hid-logitech-hidpp.c val->intval = hidpp->battery.level; val 1254 drivers/hid/hid-logitech-hidpp.c val->intval = POWER_SUPPLY_SCOPE_DEVICE; val 1257 drivers/hid/hid-logitech-hidpp.c val->intval = hidpp->battery.online; val 1261 drivers/hid/hid-logitech-hidpp.c val->strval = hidpp->name + 9; val 1263 drivers/hid/hid-logitech-hidpp.c val->strval = hidpp->name; val 1266 drivers/hid/hid-logitech-hidpp.c val->strval = "Logitech"; val 1269 drivers/hid/hid-logitech-hidpp.c val->strval = hidpp->hid_dev->uniq; val 34 drivers/hid/hid-magicmouse.c static int param_set_scroll_speed(const char *val, val 37 drivers/hid/hid-magicmouse.c if (!val || kstrtoul(val, 0, &speed) || speed > 63) val 398 drivers/hid/hid-multitouch.c unsigned long val; val 400 drivers/hid/hid-multitouch.c if (kstrtoul(buf, 0, &val)) val 403 drivers/hid/hid-multitouch.c td->mtclass.quirks = val; val 406 drivers/hid/hid-multitouch.c application->quirks = val; val 235 drivers/hid/hid-ntrig.c unsigned long val; val 237 drivers/hid/hid-ntrig.c if (kstrtoul(buf, 0, &val)) val 240 drivers/hid/hid-ntrig.c if (val > nd->sensor_physical_width) val 243 drivers/hid/hid-ntrig.c nd->min_width = val * nd->sensor_logical_width / val 270 drivers/hid/hid-ntrig.c unsigned long val; val 272 drivers/hid/hid-ntrig.c if (kstrtoul(buf, 0, &val)) val 275 drivers/hid/hid-ntrig.c if (val > nd->sensor_physical_height) val 278 drivers/hid/hid-ntrig.c nd->min_height = val * nd->sensor_logical_height / val 304 drivers/hid/hid-ntrig.c unsigned long val; val 306 drivers/hid/hid-ntrig.c if (kstrtoul(buf, 0, &val)) val 309 drivers/hid/hid-ntrig.c if (val > 0x7f) val 312 drivers/hid/hid-ntrig.c nd->activate_slack = val; val 339 drivers/hid/hid-ntrig.c unsigned long val; val 341 drivers/hid/hid-ntrig.c if (kstrtoul(buf, 0, &val)) val 344 drivers/hid/hid-ntrig.c if (val > nd->sensor_physical_width) val 347 drivers/hid/hid-ntrig.c nd->activation_width = val * nd->sensor_logical_width / val 375 drivers/hid/hid-ntrig.c unsigned long val; val 377 drivers/hid/hid-ntrig.c if (kstrtoul(buf, 0, &val)) val 380 drivers/hid/hid-ntrig.c if (val > nd->sensor_physical_height) val 383 drivers/hid/hid-ntrig.c nd->activation_height = val * nd->sensor_logical_height / val 409 drivers/hid/hid-ntrig.c unsigned long val; val 411 drivers/hid/hid-ntrig.c if (kstrtoul(buf, 0, &val)) val 419 drivers/hid/hid-ntrig.c if (val > 7) val 422 drivers/hid/hid-ntrig.c nd->deactivate_slack = -val; val 923 drivers/hid/hid-sony.c int val; val 926 drivers/hid/hid-sony.c val = ((rd[offset+1] << 8) | rd[offset]) - 511; val 927 drivers/hid/hid-sony.c input_report_abs(sc->sensor_dev, ABS_X, val); val 930 drivers/hid/hid-sony.c val = 511 - ((rd[offset+5] << 8) | rd[offset+4]); val 931 drivers/hid/hid-sony.c input_report_abs(sc->sensor_dev, ABS_Y, val); val 933 drivers/hid/hid-sony.c val = 511 - ((rd[offset+3] << 8) | rd[offset+2]); val 934 drivers/hid/hid-sony.c input_report_abs(sc->sensor_dev, ABS_Z, val); val 2298 drivers/hid/hid-sony.c union power_supply_propval *val) val 2313 drivers/hid/hid-sony.c val->intval = 1; val 2316 drivers/hid/hid-sony.c val->intval = POWER_SUPPLY_SCOPE_DEVICE; val 2319 drivers/hid/hid-sony.c val->intval = battery_capacity; val 2323 drivers/hid/hid-sony.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 2326 drivers/hid/hid-sony.c val->intval = POWER_SUPPLY_STATUS_FULL; val 2328 drivers/hid/hid-sony.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 210 drivers/hid/hid-steam.c u16 val; val 219 drivers/hid/hid-steam.c val = va_arg(args, int); val 221 drivers/hid/hid-steam.c cmd[cmd[1] + 3] = val & 0xff; val 222 drivers/hid/hid-steam.c cmd[cmd[1] + 4] = val >> 8; val 313 drivers/hid/hid-steam.c union power_supply_propval *val) val 328 drivers/hid/hid-steam.c val->intval = 1; val 331 drivers/hid/hid-steam.c val->intval = POWER_SUPPLY_SCOPE_DEVICE; val 334 drivers/hid/hid-steam.c val->intval = volts * 1000; /* mV -> uV */ val 337 drivers/hid/hid-steam.c val->intval = batt; val 1092 drivers/hid/hid-steam.c static int steam_param_set_lizard_mode(const char *val, val 1098 drivers/hid/hid-steam.c ret = param_set_bool(val, kp); val 201 drivers/hid/hid-wiimote-modules.c union power_supply_propval *val) val 208 drivers/hid/hid-wiimote-modules.c val->intval = POWER_SUPPLY_SCOPE_DEVICE; val 230 drivers/hid/hid-wiimote-modules.c val->intval = state * 100 / 255; val 1300 drivers/hid/hid-wiimote-modules.c __s32 val[4], tmp, div; val 1328 drivers/hid/hid-wiimote-modules.c val[0] = ext[0]; val 1329 drivers/hid/hid-wiimote-modules.c val[0] <<= 8; val 1330 drivers/hid/hid-wiimote-modules.c val[0] |= ext[1]; val 1332 drivers/hid/hid-wiimote-modules.c val[1] = ext[2]; val 1333 drivers/hid/hid-wiimote-modules.c val[1] <<= 8; val 1334 drivers/hid/hid-wiimote-modules.c val[1] |= ext[3]; val 1336 drivers/hid/hid-wiimote-modules.c val[2] = ext[4]; val 1337 drivers/hid/hid-wiimote-modules.c val[2] <<= 8; val 1338 drivers/hid/hid-wiimote-modules.c val[2] |= ext[5]; val 1340 drivers/hid/hid-wiimote-modules.c val[3] = ext[6]; val 1341 drivers/hid/hid-wiimote-modules.c val[3] <<= 8; val 1342 drivers/hid/hid-wiimote-modules.c val[3] |= ext[7]; val 1346 drivers/hid/hid-wiimote-modules.c if (val[i] <= s->calib_bboard[i][0]) { val 1348 drivers/hid/hid-wiimote-modules.c } else if (val[i] < s->calib_bboard[i][1]) { val 1349 drivers/hid/hid-wiimote-modules.c tmp = val[i] - s->calib_bboard[i][0]; val 1354 drivers/hid/hid-wiimote-modules.c tmp = val[i] - s->calib_bboard[i][1]; val 1360 drivers/hid/hid-wiimote-modules.c val[i] = tmp; val 1363 drivers/hid/hid-wiimote-modules.c input_report_abs(wdata->extension.input, ABS_HAT0X, val[0]); val 1364 drivers/hid/hid-wiimote-modules.c input_report_abs(wdata->extension.input, ABS_HAT0Y, val[1]); val 1365 drivers/hid/hid-wiimote-modules.c input_report_abs(wdata->extension.input, ABS_HAT1X, val[2]); val 1366 drivers/hid/hid-wiimote-modules.c input_report_abs(wdata->extension.input, ABS_HAT1Y, val[3]); val 1400 drivers/hid/hid-wiimote-modules.c __u16 val; val 1435 drivers/hid/hid-wiimote-modules.c val = wdata->state.calib_bboard[j][i]; val 1437 drivers/hid/hid-wiimote-modules.c ret += sprintf(&out[ret], "%04x\n", val); val 1439 drivers/hid/hid-wiimote-modules.c ret += sprintf(&out[ret], "%04x:", val); val 957 drivers/hid/i2c-hid/i2c-hid-core.c u32 val; val 960 drivers/hid/i2c-hid/i2c-hid-core.c ret = of_property_read_u32(dev->of_node, "hid-descr-addr", &val); val 965 drivers/hid/i2c-hid/i2c-hid-core.c if (val >> 16) { val 967 drivers/hid/i2c-hid/i2c-hid-core.c val); val 970 drivers/hid/i2c-hid/i2c-hid-core.c pdata->hid_descriptor_address = val; val 991 drivers/hid/i2c-hid/i2c-hid-core.c u32 val; val 994 drivers/hid/i2c-hid/i2c-hid-core.c &val)) val 995 drivers/hid/i2c-hid/i2c-hid-core.c pdata->post_power_delay_ms = val; val 254 drivers/hid/intel-ish-hid/ishtp-fw-loader.c const char *val; val 257 drivers/hid/intel-ish-hid/ishtp-fw-loader.c rv = device_property_read_string(devc, "firmware-name", &val); val 263 drivers/hid/intel-ish-hid/ishtp-fw-loader.c return snprintf(filename, FILENAME_SIZE, "intel/%s", val); val 1689 drivers/hid/wacom_sys.c union power_supply_propval *val) val 1696 drivers/hid/wacom_sys.c val->strval = battery->wacom->wacom_wac.name; val 1699 drivers/hid/wacom_sys.c val->intval = battery->bat_connected; val 1702 drivers/hid/wacom_sys.c val->intval = POWER_SUPPLY_SCOPE_DEVICE; val 1705 drivers/hid/wacom_sys.c val->intval = battery->battery_capacity; val 1709 drivers/hid/wacom_sys.c val->intval = battery->bat_status; val 1711 drivers/hid/wacom_sys.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 1714 drivers/hid/wacom_sys.c val->intval = POWER_SUPPLY_STATUS_FULL; val 1716 drivers/hid/wacom_sys.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 1718 drivers/hid/wacom_sys.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 175 drivers/hsi/controllers/omap_ssi_core.c u32 val; val 179 drivers/hsi/controllers/omap_ssi_core.c val = readl(omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); val 180 drivers/hsi/controllers/omap_ssi_core.c val &= ~SSI_GDD_LCH(lch); val 181 drivers/hsi/controllers/omap_ssi_core.c writel_relaxed(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); val 185 drivers/hsi/controllers/omap_ssi_core.c val = SSI_DATAAVAILABLE(msg->channel); val 189 drivers/hsi/controllers/omap_ssi_core.c val = SSI_DATAACCEPT(msg->channel); val 210 drivers/hsi/controllers/omap_ssi_core.c val |= readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); val 211 drivers/hsi/controllers/omap_ssi_core.c writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); val 124 drivers/hsi/controllers/omap_ssi_port.c static int ssi_div_get(void *data, u64 *val) val 130 drivers/hsi/controllers/omap_ssi_port.c *val = readl(omap_port->sst_base + SSI_SST_DIVISOR_REG); val 136 drivers/hsi/controllers/omap_ssi_port.c static int ssi_div_set(void *data, u64 val) val 141 drivers/hsi/controllers/omap_ssi_port.c if (val > 127) val 145 drivers/hsi/controllers/omap_ssi_port.c writel(val, omap_port->sst_base + SSI_SST_DIVISOR_REG); val 146 drivers/hsi/controllers/omap_ssi_port.c omap_port->sst.divisor = val; val 292 drivers/hsi/controllers/omap_ssi_port.c u32 val; val 303 drivers/hsi/controllers/omap_ssi_port.c val = SSI_DATAACCEPT(msg->channel); val 307 drivers/hsi/controllers/omap_ssi_port.c val = SSI_DATAAVAILABLE(msg->channel) | SSI_ERROROCCURED; val 311 drivers/hsi/controllers/omap_ssi_port.c val |= readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); val 312 drivers/hsi/controllers/omap_ssi_port.c writel(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); val 463 drivers/hsi/controllers/omap_ssi_port.c u32 val; val 481 drivers/hsi/controllers/omap_ssi_port.c val = readl(ssr + SSI_SSR_MODE_REG); val 734 drivers/hsi/controllers/omap_ssi_port.c u32 val = 0; val 742 drivers/hsi/controllers/omap_ssi_port.c val |= (1 << i); val 754 drivers/hsi/controllers/omap_ssi_port.c tmp &= ~val; val 756 drivers/hsi/controllers/omap_ssi_port.c writel(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_STATUS_REG); val 813 drivers/hsi/controllers/omap_ssi_port.c u32 val; val 825 drivers/hsi/controllers/omap_ssi_port.c for (i = 0, val = 0; i < SSI_MAX_GDD_LCH; i++) { val 829 drivers/hsi/controllers/omap_ssi_port.c val |= (1 << i); val 834 drivers/hsi/controllers/omap_ssi_port.c tmp &= ~val; val 870 drivers/hsi/controllers/omap_ssi_port.c u32 val; val 875 drivers/hsi/controllers/omap_ssi_port.c val = readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); val 876 drivers/hsi/controllers/omap_ssi_port.c val &= ~SSI_BREAKDETECTED; val 877 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); val 901 drivers/hsi/controllers/omap_ssi_port.c u32 val; val 910 drivers/hsi/controllers/omap_ssi_port.c val = SSI_DATAACCEPT(msg->channel); val 912 drivers/hsi/controllers/omap_ssi_port.c val = SSI_DATAAVAILABLE(msg->channel); val 933 drivers/hsi/controllers/omap_ssi_port.c writel(val, omap_ssi->sys + val 948 drivers/hsi/controllers/omap_ssi_port.c reg &= ~val; val 950 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(val, omap_ssi->sys + SSI_MPU_STATUS_REG(port->num, 0)); val 626 drivers/hv/hv_balloon.c static int hv_memory_notifier(struct notifier_block *nb, unsigned long val, val 632 drivers/hv/hv_balloon.c switch (val) { val 291 drivers/hv/hv_fcopy.c int *val = (int *)msg; val 297 drivers/hv/hv_fcopy.c return fcopy_handle_handshake(*val); val 308 drivers/hv/hv_fcopy.c fcopy_respond_to_host(*val); val 191 drivers/hv/hv_utils_transport.c hvt->cn_id.val == msg->id.val) { val 231 drivers/hv/hv_utils_transport.c cn_msg->id.val = hvt->cn_id.val; val 282 drivers/hv/hv_utils_transport.c hvt->cn_id.val = cn_val; val 311 drivers/hv/hv_utils_transport.c if (hvt->cn_id.idx > 0 && hvt->cn_id.val > 0 && val 343 drivers/hv/hv_utils_transport.c if (hvt->cn_id.idx > 0 && hvt->cn_id.val > 0) val 64 drivers/hv/vmbus_drv.c static int hyperv_panic_event(struct notifier_block *nb, unsigned long val, val 79 drivers/hv/vmbus_drv.c hyperv_report_panic(regs, val, false); val 84 drivers/hv/vmbus_drv.c static int hyperv_die_event(struct notifier_block *nb, unsigned long val, val 96 drivers/hv/vmbus_drv.c hyperv_report_panic(regs, val, true); val 475 drivers/hwmon/abituguru.c u8 val, test_flag, buf[3]; val 488 drivers/hwmon/abituguru.c if (abituguru_read(data, ABIT_UGURU_SENSOR_BANK1, sensor_addr, &val, val 493 drivers/hwmon/abituguru.c if ((val < 10u) || (val > 250u)) { val 496 drivers/hwmon/abituguru.c (int)sensor_addr, (int)val); val 511 drivers/hwmon/abituguru.c if (val <= 240u) { val 834 drivers/hwmon/abituguru.c unsigned long val; val 837 drivers/hwmon/abituguru.c ret = kstrtoul(buf, 10, &val); val 842 drivers/hwmon/abituguru.c val = (val * 255 + data->bank1_max_value[attr->index] / 2) / val 844 drivers/hwmon/abituguru.c if (val > 255) val 848 drivers/hwmon/abituguru.c if (data->bank1_settings[attr->index][attr->nr] != val) { val 850 drivers/hwmon/abituguru.c data->bank1_settings[attr->index][attr->nr] = val; val 867 drivers/hwmon/abituguru.c unsigned long val; val 870 drivers/hwmon/abituguru.c ret = kstrtoul(buf, 10, &val); val 875 drivers/hwmon/abituguru.c val = (val * 255 + ABIT_UGURU_FAN_MAX / 2) / ABIT_UGURU_FAN_MAX; val 878 drivers/hwmon/abituguru.c if (val < abituguru_bank2_min_threshold || val 879 drivers/hwmon/abituguru.c val > abituguru_bank2_max_threshold) val 883 drivers/hwmon/abituguru.c if (data->bank2_settings[attr->index][attr->nr] != val) { val 885 drivers/hwmon/abituguru.c data->bank2_settings[attr->index][attr->nr] = val; val 1035 drivers/hwmon/abituguru.c unsigned long val; val 1038 drivers/hwmon/abituguru.c ret = kstrtoul(buf, 10, &val); val 1043 drivers/hwmon/abituguru.c val = (val + abituguru_pwm_settings_multiplier[attr->nr] / 2) / val 1053 drivers/hwmon/abituguru.c if (val < min || val > abituguru_pwm_max[attr->nr]) val 1059 drivers/hwmon/abituguru.c (val >= data->pwm_settings[attr->index][attr->nr + 1])) val 1062 drivers/hwmon/abituguru.c (val <= data->pwm_settings[attr->index][attr->nr - 1])) val 1064 drivers/hwmon/abituguru.c else if (data->pwm_settings[attr->index][attr->nr] != val) { val 1066 drivers/hwmon/abituguru.c data->pwm_settings[attr->index][attr->nr] = val; val 1103 drivers/hwmon/abituguru.c unsigned long val; val 1107 drivers/hwmon/abituguru.c ret = kstrtoul(buf, 10, &val); val 1111 drivers/hwmon/abituguru.c if (val == 0 || val > data->bank1_sensors[ABIT_UGURU_TEMP_SENSOR]) val 1114 drivers/hwmon/abituguru.c val -= 1; val 1118 drivers/hwmon/abituguru.c address = data->bank1_address[ABIT_UGURU_TEMP_SENSOR][val]; val 159 drivers/hwmon/abx500.c unsigned long val; val 162 drivers/hwmon/abx500.c int res = kstrtol(buf, 10, &val); val 166 drivers/hwmon/abx500.c val = clamp_val(val, 0, DEFAULT_MAX_TEMP); val 169 drivers/hwmon/abx500.c data->min[attr->index] = val; val 179 drivers/hwmon/abx500.c unsigned long val; val 182 drivers/hwmon/abx500.c int res = kstrtol(buf, 10, &val); val 186 drivers/hwmon/abx500.c val = clamp_val(val, 0, DEFAULT_MAX_TEMP); val 189 drivers/hwmon/abx500.c data->max[attr->index] = val; val 200 drivers/hwmon/abx500.c unsigned long val; val 203 drivers/hwmon/abx500.c int res = kstrtoul(buf, 10, &val); val 207 drivers/hwmon/abx500.c val = clamp_val(val, 0, DEFAULT_MAX_TEMP); val 210 drivers/hwmon/abx500.c data->max_hyst[attr->index] = val; val 357 drivers/hwmon/acpi_power_meter.c acpi_string val; val 361 drivers/hwmon/acpi_power_meter.c val = resource->model_number; val 364 drivers/hwmon/acpi_power_meter.c val = resource->serial_number; val 367 drivers/hwmon/acpi_power_meter.c val = resource->oem_info; val 372 drivers/hwmon/acpi_power_meter.c val = ""; val 376 drivers/hwmon/acpi_power_meter.c return sprintf(buf, "%s\n", val); val 386 drivers/hwmon/acpi_power_meter.c u64 val = 0; val 390 drivers/hwmon/acpi_power_meter.c val = resource->caps.min_avg_interval; val 393 drivers/hwmon/acpi_power_meter.c val = resource->caps.max_avg_interval; val 396 drivers/hwmon/acpi_power_meter.c val = resource->caps.min_cap * 1000; val 399 drivers/hwmon/acpi_power_meter.c val = resource->caps.max_cap * 1000; val 405 drivers/hwmon/acpi_power_meter.c val = resource->caps.hysteresis * 1000; val 409 drivers/hwmon/acpi_power_meter.c val = 1; val 411 drivers/hwmon/acpi_power_meter.c val = 0; val 415 drivers/hwmon/acpi_power_meter.c val = 1; val 417 drivers/hwmon/acpi_power_meter.c val = 0; val 424 drivers/hwmon/acpi_power_meter.c val = resource->trip[attr->index - 7] * 1000; val 432 drivers/hwmon/acpi_power_meter.c return sprintf(buf, "%llu\n", val); val 59 drivers/hwmon/ad7418.c s32 val; val 69 drivers/hwmon/ad7418.c val = i2c_smbus_read_byte_data(client, AD7418_REG_CONF); val 70 drivers/hwmon/ad7418.c if (val < 0) val 73 drivers/hwmon/ad7418.c cfg = val; val 76 drivers/hwmon/ad7418.c val = i2c_smbus_write_byte_data(client, AD7418_REG_CONF, val 78 drivers/hwmon/ad7418.c if (val < 0) val 84 drivers/hwmon/ad7418.c val = i2c_smbus_read_word_swapped(client, val 86 drivers/hwmon/ad7418.c if (val < 0) val 89 drivers/hwmon/ad7418.c data->temp[i] = val; val 93 drivers/hwmon/ad7418.c val = i2c_smbus_write_byte_data(client, AD7418_REG_CONF, val 95 drivers/hwmon/ad7418.c if (val < 0) val 99 drivers/hwmon/ad7418.c val = i2c_smbus_read_word_swapped(client, val 101 drivers/hwmon/ad7418.c if (val < 0) val 104 drivers/hwmon/ad7418.c data->in[data->adc_max - 1 - i] = val; val 108 drivers/hwmon/ad7418.c val = i2c_smbus_write_word_swapped(client, AD7418_REG_CONF, val 110 drivers/hwmon/ad7418.c if (val < 0) val 123 drivers/hwmon/ad7418.c return val; val 153 drivers/hwmon/adc128d818.c int val; val 158 drivers/hwmon/adc128d818.c val = DIV_ROUND_CLOSEST(data->in[index][nr] * data->vref, 4095); val 159 drivers/hwmon/adc128d818.c return sprintf(buf, "%d\n", val); val 170 drivers/hwmon/adc128d818.c long val; val 173 drivers/hwmon/adc128d818.c err = kstrtol(buf, 10, &val); val 179 drivers/hwmon/adc128d818.c regval = clamp_val(DIV_ROUND_CLOSEST(val, 10), 0, 255); val 208 drivers/hwmon/adc128d818.c long val; val 212 drivers/hwmon/adc128d818.c err = kstrtol(buf, 10, &val); val 217 drivers/hwmon/adc128d818.c regval = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127); val 255 drivers/hwmon/adm1021.c unsigned long val; val 258 drivers/hwmon/adm1021.c err = kstrtoul(buf, 10, &val); val 261 drivers/hwmon/adm1021.c low_power = val != 0; val 82 drivers/hwmon/adm1025.c #define IN_TO_REG(val, scale) ((val) <= 0 ? 0 : \ val 83 drivers/hwmon/adm1025.c (val) >= (scale) * 255 / 192 ? 255 : \ val 84 drivers/hwmon/adm1025.c ((val) * 192 + (scale) / 2) / (scale)) val 87 drivers/hwmon/adm1025.c #define TEMP_TO_REG(val) ((val) <= -127500 ? -128 : \ val 88 drivers/hwmon/adm1025.c (val) >= 126500 ? 127 : \ val 89 drivers/hwmon/adm1025.c (((val) < 0 ? (val) - 500 : \ val 90 drivers/hwmon/adm1025.c (val) + 500) / 1000)) val 220 drivers/hwmon/adm1025.c long val; val 223 drivers/hwmon/adm1025.c err = kstrtol(buf, 10, &val); val 228 drivers/hwmon/adm1025.c data->in_min[index] = IN_TO_REG(val, in_scale[index]); val 241 drivers/hwmon/adm1025.c long val; val 244 drivers/hwmon/adm1025.c err = kstrtol(buf, 10, &val); val 249 drivers/hwmon/adm1025.c data->in_max[index] = IN_TO_REG(val, in_scale[index]); val 282 drivers/hwmon/adm1025.c long val; val 285 drivers/hwmon/adm1025.c err = kstrtol(buf, 10, &val); val 290 drivers/hwmon/adm1025.c data->temp_min[index] = TEMP_TO_REG(val); val 304 drivers/hwmon/adm1025.c long val; val 307 drivers/hwmon/adm1025.c err = kstrtol(buf, 10, &val); val 312 drivers/hwmon/adm1025.c data->temp_max[index] = TEMP_TO_REG(val); val 369 drivers/hwmon/adm1025.c unsigned long val; val 372 drivers/hwmon/adm1025.c err = kstrtoul(buf, 10, &val); val 376 drivers/hwmon/adm1025.c if (val > 255) val 379 drivers/hwmon/adm1025.c data->vrm = val; val 186 drivers/hwmon/adm1026.c #define SCALE(val, from, to) (((val)*(to) + ((from)/2))/(from)) val 187 drivers/hwmon/adm1026.c #define INS_TO_REG(n, val) \ val 188 drivers/hwmon/adm1026.c SCALE(clamp_val(val, 0, 255 * adm1026_scaling[n] / 192), \ val 190 drivers/hwmon/adm1026.c #define INS_FROM_REG(n, val) (SCALE(val, 192, adm1026_scaling[n])) val 197 drivers/hwmon/adm1026.c #define FAN_TO_REG(val, div) ((val) <= 0 ? 0xff : \ val 198 drivers/hwmon/adm1026.c clamp_val(1350000 / ((val) * (div)), \ val 200 drivers/hwmon/adm1026.c #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 0xff ? 0 : \ val 201 drivers/hwmon/adm1026.c 1350000 / ((val) * (div))) val 202 drivers/hwmon/adm1026.c #define DIV_FROM_REG(val) (1 << (val)) val 203 drivers/hwmon/adm1026.c #define DIV_TO_REG(val) ((val) >= 8 ? 3 : (val) >= 4 ? 2 : (val) >= 2 ? 1 : 0) val 206 drivers/hwmon/adm1026.c #define TEMP_TO_REG(val) DIV_ROUND_CLOSEST(clamp_val(val, -128000, 127000), \ val 208 drivers/hwmon/adm1026.c #define TEMP_FROM_REG(val) ((val) * 1000) val 209 drivers/hwmon/adm1026.c #define OFFSET_TO_REG(val) DIV_ROUND_CLOSEST(clamp_val(val, -128000, 127000), \ val 211 drivers/hwmon/adm1026.c #define OFFSET_FROM_REG(val) ((val) * 1000) val 213 drivers/hwmon/adm1026.c #define PWM_TO_REG(val) (clamp_val(val, 0, 255)) val 214 drivers/hwmon/adm1026.c #define PWM_FROM_REG(val) (val) val 216 drivers/hwmon/adm1026.c #define PWM_MIN_TO_REG(val) ((val) & 0xf0) val 217 drivers/hwmon/adm1026.c #define PWM_MIN_FROM_REG(val) (((val) & 0xf0) + ((val) >> 4)) val 224 drivers/hwmon/adm1026.c #define DAC_TO_REG(val) DIV_ROUND_CLOSEST(clamp_val(val, 0, 2500) * 255, \ val 226 drivers/hwmon/adm1026.c #define DAC_FROM_REG(val) (((val) * 2500) / 255) val 490 drivers/hwmon/adm1026.c long val; val 493 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 498 drivers/hwmon/adm1026.c data->in_min[nr] = INS_TO_REG(nr, val); val 518 drivers/hwmon/adm1026.c long val; val 521 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 526 drivers/hwmon/adm1026.c data->in_max[nr] = INS_TO_REG(nr, val); val 601 drivers/hwmon/adm1026.c long val; val 604 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 610 drivers/hwmon/adm1026.c clamp_val(val, INT_MIN, val 630 drivers/hwmon/adm1026.c long val; val 633 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 639 drivers/hwmon/adm1026.c clamp_val(val, INT_MIN, val 679 drivers/hwmon/adm1026.c long val; val 682 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 687 drivers/hwmon/adm1026.c data->fan_min[nr] = FAN_TO_REG(val, data->fan_div[nr]); val 746 drivers/hwmon/adm1026.c long val; val 750 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 754 drivers/hwmon/adm1026.c new_div = DIV_TO_REG(val); val 815 drivers/hwmon/adm1026.c long val; val 818 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 823 drivers/hwmon/adm1026.c data->temp_min[nr] = TEMP_TO_REG(val); val 845 drivers/hwmon/adm1026.c long val; val 848 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 853 drivers/hwmon/adm1026.c data->temp_max[nr] = TEMP_TO_REG(val); val 886 drivers/hwmon/adm1026.c long val; val 889 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 894 drivers/hwmon/adm1026.c data->temp_offset[nr] = TEMP_TO_REG(val); val 942 drivers/hwmon/adm1026.c long val; val 945 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 950 drivers/hwmon/adm1026.c data->temp_tmin[nr] = TEMP_TO_REG(val); val 981 drivers/hwmon/adm1026.c unsigned long val; val 984 drivers/hwmon/adm1026.c err = kstrtoul(buf, 10, &val); val 988 drivers/hwmon/adm1026.c if (val > 1) val 992 drivers/hwmon/adm1026.c data->config1 = (data->config1 & ~CFG1_THERM_HOT) | (val << 4); val 1022 drivers/hwmon/adm1026.c long val; val 1025 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 1030 drivers/hwmon/adm1026.c data->temp_crit[nr] = TEMP_TO_REG(val); val 1053 drivers/hwmon/adm1026.c long val; val 1056 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 1061 drivers/hwmon/adm1026.c data->analog_out = DAC_TO_REG(val); val 1092 drivers/hwmon/adm1026.c unsigned long val; val 1095 drivers/hwmon/adm1026.c err = kstrtoul(buf, 10, &val); val 1099 drivers/hwmon/adm1026.c if (val > 255) val 1102 drivers/hwmon/adm1026.c data->vrm = val; val 1167 drivers/hwmon/adm1026.c long val; val 1170 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 1175 drivers/hwmon/adm1026.c data->alarm_mask = val & 0x7fffffff; val 1207 drivers/hwmon/adm1026.c long val; val 1210 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 1215 drivers/hwmon/adm1026.c data->gpio = val & 0x1ffff; val 1242 drivers/hwmon/adm1026.c long val; val 1245 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 1250 drivers/hwmon/adm1026.c data->gpio_mask = val & 0x1ffff; val 1277 drivers/hwmon/adm1026.c long val; val 1280 drivers/hwmon/adm1026.c err = kstrtol(buf, 10, &val); val 1285 drivers/hwmon/adm1026.c data->pwm1.pwm = PWM_TO_REG(val); val 1306 drivers/hwmon/adm1026.c unsigned long val; val 1309 drivers/hwmon/adm1026.c err = kstrtoul(buf, 10, &val); val 1314 drivers/hwmon/adm1026.c data->pwm1.auto_pwm_min = clamp_val(val, 0, 255); val 1345 drivers/hwmon/adm1026.c unsigned long val; val 1348 drivers/hwmon/adm1026.c err = kstrtoul(buf, 10, &val); val 1352 drivers/hwmon/adm1026.c if (val >= 3) val 1357 drivers/hwmon/adm1026.c data->pwm1.enable = val; val 1359 drivers/hwmon/adm1026.c | ((val == 2) ? CFG1_PWM_AFC : 0); val 1361 drivers/hwmon/adm1026.c if (val == 2) { /* apply pwm1_auto_pwm_min to pwm1 */ val 1365 drivers/hwmon/adm1026.c } else if (!((old_enable == 1) && (val == 1))) { val 66 drivers/hwmon/adm1029.c #define TEMP_FROM_REG(val) ((val) * 1000) val 68 drivers/hwmon/adm1029.c #define DIV_FROM_REG(val) (1 << (((val) >> 6) - 1)) val 172 drivers/hwmon/adm1029.c u16 val; val 180 drivers/hwmon/adm1029.c val = 1880 * 120 / DIV_FROM_REG(data->fan_div[attr->index]) val 182 drivers/hwmon/adm1029.c return sprintf(buf, "%d\n", val); val 204 drivers/hwmon/adm1029.c long val; val 205 drivers/hwmon/adm1029.c int ret = kstrtol(buf, 10, &val); val 216 drivers/hwmon/adm1029.c switch (val) { val 218 drivers/hwmon/adm1029.c val = 1; val 221 drivers/hwmon/adm1029.c val = 2; val 224 drivers/hwmon/adm1029.c val = 3; val 230 drivers/hwmon/adm1029.c val); val 234 drivers/hwmon/adm1029.c reg = (reg & 0x3F) | (val << 6); val 198 drivers/hwmon/adm1031.c #define TEMP_TO_REG(val) (((val) < 0 ? ((val - 500) / 1000) : \ val 199 drivers/hwmon/adm1031.c ((val + 500) / 1000))) val 201 drivers/hwmon/adm1031.c #define TEMP_FROM_REG(val) ((val) * 1000) val 203 drivers/hwmon/adm1031.c #define TEMP_FROM_REG_EXT(val, ext) (TEMP_FROM_REG(val) + (ext) * 125) val 205 drivers/hwmon/adm1031.c #define TEMP_OFFSET_TO_REG(val) (TEMP_TO_REG(val) & 0x8f) val 206 drivers/hwmon/adm1031.c #define TEMP_OFFSET_FROM_REG(val) TEMP_FROM_REG((val) < 0 ? \ val 207 drivers/hwmon/adm1031.c (val) | 0x70 : (val)) val 221 drivers/hwmon/adm1031.c #define PWM_TO_REG(val) (clamp_val((val), 0, 255) >> 4) val 222 drivers/hwmon/adm1031.c #define PWM_FROM_REG(val) ((val) << 4) val 225 drivers/hwmon/adm1031.c #define FAN_CHAN_TO_REG(val, reg) \ val 226 drivers/hwmon/adm1031.c (((reg) & 0x1F) | (((val) << 5) & 0xe0)) val 228 drivers/hwmon/adm1031.c #define AUTO_TEMP_MIN_TO_REG(val, reg) \ val 229 drivers/hwmon/adm1031.c ((((val) / 500) & 0xf8) | ((reg) & 0x7)) val 242 drivers/hwmon/adm1031.c static int AUTO_TEMP_MAX_TO_REG(int val, int reg, int pwm) val 245 drivers/hwmon/adm1031.c int range = val - AUTO_TEMP_MIN_FROM_REG(reg); val 247 drivers/hwmon/adm1031.c range = ((val - AUTO_TEMP_MIN_FROM_REG(reg))*10)/(16 - pwm); val 286 drivers/hwmon/adm1031.c get_fan_auto_nearest(struct adm1031_data *data, int chan, u8 val, u8 reg) val 293 drivers/hwmon/adm1031.c if (val == 0) val 297 drivers/hwmon/adm1031.c if ((val == (*data->chan_select_table)[i][chan]) && val 303 drivers/hwmon/adm1031.c } else if (val == (*data->chan_select_table)[i][chan] && val 336 drivers/hwmon/adm1031.c long val; val 341 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 349 drivers/hwmon/adm1031.c ret = get_fan_auto_nearest(data, nr, val, data->conf1); val 409 drivers/hwmon/adm1031.c long val; val 412 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 416 drivers/hwmon/adm1031.c val = clamp_val(val, 0, 127000); val 418 drivers/hwmon/adm1031.c data->auto_temp[nr] = AUTO_TEMP_MIN_TO_REG(val, data->auto_temp[nr]); val 439 drivers/hwmon/adm1031.c long val; val 442 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 446 drivers/hwmon/adm1031.c val = clamp_val(val, 0, 127000); val 448 drivers/hwmon/adm1031.c data->temp_max[nr] = AUTO_TEMP_MAX_TO_REG(val, data->auto_temp[nr], val 480 drivers/hwmon/adm1031.c long val; val 483 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 489 drivers/hwmon/adm1031.c (((val>>4) & 0xf) != 5)) { val 494 drivers/hwmon/adm1031.c data->pwm[nr] = PWM_TO_REG(val); val 591 drivers/hwmon/adm1031.c long val; val 594 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 599 drivers/hwmon/adm1031.c if (val) { val 601 drivers/hwmon/adm1031.c FAN_TO_REG(val, FAN_DIV_FROM_REG(data->fan_div[nr])); val 616 drivers/hwmon/adm1031.c long val; val 622 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 626 drivers/hwmon/adm1031.c tmp = val == 8 ? 0xc0 : val 627 drivers/hwmon/adm1031.c val == 4 ? 0x80 : val 628 drivers/hwmon/adm1031.c val == 2 ? 0x40 : val 629 drivers/hwmon/adm1031.c val == 1 ? 0x00 : val 644 drivers/hwmon/adm1031.c new_min = data->fan_min[nr] * old_div / val; val 713 drivers/hwmon/adm1031.c long val; val 716 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 720 drivers/hwmon/adm1031.c val = clamp_val(val, -15000, 15000); val 722 drivers/hwmon/adm1031.c data->temp_offset[nr] = TEMP_OFFSET_TO_REG(val); val 735 drivers/hwmon/adm1031.c long val; val 738 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 742 drivers/hwmon/adm1031.c val = clamp_val(val, -55000, 127000); val 744 drivers/hwmon/adm1031.c data->temp_min[nr] = TEMP_TO_REG(val); val 757 drivers/hwmon/adm1031.c long val; val 760 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 764 drivers/hwmon/adm1031.c val = clamp_val(val, -55000, 127000); val 766 drivers/hwmon/adm1031.c data->temp_max[nr] = TEMP_TO_REG(val); val 779 drivers/hwmon/adm1031.c long val; val 782 drivers/hwmon/adm1031.c ret = kstrtol(buf, 10, &val); val 786 drivers/hwmon/adm1031.c val = clamp_val(val, -55000, 127000); val 788 drivers/hwmon/adm1031.c data->temp_crit[nr] = TEMP_TO_REG(val); val 864 drivers/hwmon/adm1031.c unsigned long val; val 868 drivers/hwmon/adm1031.c err = kstrtoul(buf, 10, &val); val 877 drivers/hwmon/adm1031.c if (val >= update_intervals[i]) val 70 drivers/hwmon/adm9240.c static inline int SCALE(long val, int mul, int div) val 72 drivers/hwmon/adm9240.c if (val < 0) val 73 drivers/hwmon/adm9240.c return (val * mul - div / 2) / div; val 75 drivers/hwmon/adm9240.c return (val * mul + div / 2) / div; val 86 drivers/hwmon/adm9240.c static inline u8 IN_TO_REG(unsigned long val, int n) val 88 drivers/hwmon/adm9240.c val = clamp_val(val, 0, nom_mv[n] * 255 / 192); val 89 drivers/hwmon/adm9240.c return SCALE(val, 192, nom_mv[n]); val 93 drivers/hwmon/adm9240.c static inline s8 TEMP_TO_REG(long val) val 95 drivers/hwmon/adm9240.c val = clamp_val(val, -40000, 127000); val 96 drivers/hwmon/adm9240.c return SCALE(val, 1, 1000); val 112 drivers/hwmon/adm9240.c static inline u8 AOUT_TO_REG(unsigned long val) val 114 drivers/hwmon/adm9240.c val = clamp_val(val, 0, 1250); val 115 drivers/hwmon/adm9240.c return SCALE(val, 255, 1250); val 273 drivers/hwmon/adm9240.c long val; val 276 drivers/hwmon/adm9240.c err = kstrtol(buf, 10, &val); val 281 drivers/hwmon/adm9240.c data->temp_max[attr->index] = TEMP_TO_REG(val); val 327 drivers/hwmon/adm9240.c unsigned long val; val 330 drivers/hwmon/adm9240.c err = kstrtoul(buf, 10, &val); val 335 drivers/hwmon/adm9240.c data->in_min[attr->index] = IN_TO_REG(val, attr->index); val 349 drivers/hwmon/adm9240.c unsigned long val; val 352 drivers/hwmon/adm9240.c err = kstrtoul(buf, 10, &val); val 357 drivers/hwmon/adm9240.c data->in_max[attr->index] = IN_TO_REG(val, attr->index); val 430 drivers/hwmon/adm9240.c unsigned long val; val 433 drivers/hwmon/adm9240.c err = kstrtoul(buf, 10, &val); val 439 drivers/hwmon/adm9240.c if (!val) { val 446 drivers/hwmon/adm9240.c } else if (val < 1350000 / (8 * 254)) { val 454 drivers/hwmon/adm9240.c unsigned int new_min = 1350000 / val; val 537 drivers/hwmon/adm9240.c long val; val 540 drivers/hwmon/adm9240.c err = kstrtol(buf, 10, &val); val 545 drivers/hwmon/adm9240.c data->aout = AOUT_TO_REG(val); val 557 drivers/hwmon/adm9240.c unsigned long val; val 559 drivers/hwmon/adm9240.c if (kstrtoul(buf, 10, &val) || val != 0) val 85 drivers/hwmon/ads7871.c static int ads7871_write_reg8(struct spi_device *spi, int reg, u8 val) val 87 drivers/hwmon/ads7871.c u8 tmp[2] = {reg, val}; val 97 drivers/hwmon/ads7871.c int ret, val, i = 0; val 124 drivers/hwmon/ads7871.c val = ads7871_read_reg16(spi, REG_LS_BYTE); val 126 drivers/hwmon/ads7871.c val = ((val >> 2) * 25000) / 8192; val 127 drivers/hwmon/ads7871.c return sprintf(buf, "%d\n", val); val 160 drivers/hwmon/ads7871.c uint8_t val; val 172 drivers/hwmon/ads7871.c val = (OSC_OSCR_BM | OSC_OSCE_BM | OSC_REFE_BM | OSC_BUFE_BM); val 173 drivers/hwmon/ads7871.c ads7871_write_reg8(spi, REG_OSC_CONTROL, val); val 176 drivers/hwmon/ads7871.c dev_dbg(dev, "REG_OSC_CONTROL write:%x, read:%x\n", val, ret); val 181 drivers/hwmon/ads7871.c if (val != ret) val 120 drivers/hwmon/adt7411.c int val, tmp; val 124 drivers/hwmon/adt7411.c val = i2c_smbus_read_byte_data(client, lsb_reg); val 125 drivers/hwmon/adt7411.c if (val < 0) val 128 drivers/hwmon/adt7411.c tmp = (val >> lsb_shift) & 3; val 129 drivers/hwmon/adt7411.c val = i2c_smbus_read_byte_data(client, msb_reg); val 131 drivers/hwmon/adt7411.c if (val >= 0) val 132 drivers/hwmon/adt7411.c val = (val << 2) | tmp; val 137 drivers/hwmon/adt7411.c return val; val 144 drivers/hwmon/adt7411.c int ret, val; val 153 drivers/hwmon/adt7411.c val = ret | bit; val 155 drivers/hwmon/adt7411.c val = ret & ~bit; val 157 drivers/hwmon/adt7411.c ret = i2c_smbus_write_byte_data(client, reg, val); val 215 drivers/hwmon/adt7411.c static int adt7411_read_in_alarm(struct device *dev, int channel, long *val) val 224 drivers/hwmon/adt7411.c *val = !!(ret & adt7411_in_alarm_bits[channel]); val 228 drivers/hwmon/adt7411.c static int adt7411_read_in_vdd(struct device *dev, u32 attr, long *val) val 240 drivers/hwmon/adt7411.c *val = ret * 7000 / 1024; val 246 drivers/hwmon/adt7411.c *val = ret * 7000 / 256; val 252 drivers/hwmon/adt7411.c *val = ret * 7000 / 256; val 255 drivers/hwmon/adt7411.c return adt7411_read_in_alarm(dev, 0, val); val 265 drivers/hwmon/adt7411.c int val; val 268 drivers/hwmon/adt7411.c val = i2c_smbus_read_byte_data(client, ADT7411_REG_CFG3); val 269 drivers/hwmon/adt7411.c if (val < 0) val 270 drivers/hwmon/adt7411.c return val; val 272 drivers/hwmon/adt7411.c if (val & ADT7411_CFG3_REF_VDD) { val 273 drivers/hwmon/adt7411.c val = adt7411_read_in_vdd(dev, hwmon_in_input, val 275 drivers/hwmon/adt7411.c if (val < 0) val 276 drivers/hwmon/adt7411.c return val; val 288 drivers/hwmon/adt7411.c long *val) val 311 drivers/hwmon/adt7411.c *val = ret * data->vref_cached / 1024; val 322 drivers/hwmon/adt7411.c *val = ret * data->vref_cached / 256; val 326 drivers/hwmon/adt7411.c ret = adt7411_read_in_alarm(dev, channel, val); val 338 drivers/hwmon/adt7411.c long *val) val 341 drivers/hwmon/adt7411.c return adt7411_read_in_vdd(dev, attr, val); val 343 drivers/hwmon/adt7411.c return adt7411_read_in_chan(dev, attr, channel, val); val 348 drivers/hwmon/adt7411.c long *val) val 374 drivers/hwmon/adt7411.c *val = !!(ret & bit); val 379 drivers/hwmon/adt7411.c long *val) val 395 drivers/hwmon/adt7411.c *val = ret * 250; val 406 drivers/hwmon/adt7411.c *val = ret * 1000; val 411 drivers/hwmon/adt7411.c return adt7411_read_temp_alarm(dev, attr, channel, val); val 418 drivers/hwmon/adt7411.c u32 attr, int channel, long *val) val 422 drivers/hwmon/adt7411.c return adt7411_read_in(dev, attr, channel, val); val 424 drivers/hwmon/adt7411.c return adt7411_read_temp(dev, attr, channel, val); val 430 drivers/hwmon/adt7411.c static int adt7411_write_in_vdd(struct device *dev, u32 attr, long val) val 436 drivers/hwmon/adt7411.c val = clamp_val(val, 0, 255 * 7000 / 256); val 437 drivers/hwmon/adt7411.c val = DIV_ROUND_CLOSEST(val * 256, 7000); val 450 drivers/hwmon/adt7411.c return i2c_smbus_write_byte_data(client, reg, val); val 454 drivers/hwmon/adt7411.c long val) val 464 drivers/hwmon/adt7411.c val = clamp_val(val, 0, 255 * data->vref_cached / 256); val 465 drivers/hwmon/adt7411.c val = DIV_ROUND_CLOSEST(val * 256, data->vref_cached); val 479 drivers/hwmon/adt7411.c ret = i2c_smbus_write_byte_data(client, reg, val); val 486 drivers/hwmon/adt7411.c long val) val 489 drivers/hwmon/adt7411.c return adt7411_write_in_vdd(dev, attr, val); val 491 drivers/hwmon/adt7411.c return adt7411_write_in_chan(dev, attr, channel, val); val 495 drivers/hwmon/adt7411.c long val) val 501 drivers/hwmon/adt7411.c val = clamp_val(val, -128000, 127000); val 502 drivers/hwmon/adt7411.c val = DIV_ROUND_CLOSEST(val, 1000); val 515 drivers/hwmon/adt7411.c return i2c_smbus_write_byte_data(client, reg, val); val 519 drivers/hwmon/adt7411.c u32 attr, int channel, long val) val 523 drivers/hwmon/adt7411.c return adt7411_write_in(dev, attr, channel, val); val 525 drivers/hwmon/adt7411.c return adt7411_write_temp(dev, attr, channel, val); val 572 drivers/hwmon/adt7411.c int val; val 577 drivers/hwmon/adt7411.c val = i2c_smbus_read_byte_data(client, ADT7411_REG_MANUFACTURER_ID); val 578 drivers/hwmon/adt7411.c if (val < 0 || val != ADT7411_MANUFACTURER_ID) { val 581 drivers/hwmon/adt7411.c val, ADT7411_MANUFACTURER_ID); val 585 drivers/hwmon/adt7411.c val = i2c_smbus_read_byte_data(client, ADT7411_REG_DEVICE_ID); val 586 drivers/hwmon/adt7411.c if (val < 0 || val != ADT7411_DEVICE_ID) { val 589 drivers/hwmon/adt7411.c val, ADT7411_DEVICE_ID); val 601 drivers/hwmon/adt7411.c u8 val; val 611 drivers/hwmon/adt7411.c val = ret; val 612 drivers/hwmon/adt7411.c val &= ~(ADT7411_CFG3_RESERVED_BIT1 | ADT7411_CFG3_RESERVED_BIT2); val 613 drivers/hwmon/adt7411.c val |= ADT7411_CFG3_RESERVED_BIT3; val 615 drivers/hwmon/adt7411.c ret = i2c_smbus_write_byte_data(data->client, ADT7411_REG_CFG3, val); val 629 drivers/hwmon/adt7411.c val = ret; val 630 drivers/hwmon/adt7411.c val &= ~ADT7411_CFG1_RESERVED_BIT1; val 631 drivers/hwmon/adt7411.c val |= ADT7411_CFG1_RESERVED_BIT3; val 634 drivers/hwmon/adt7411.c val |= ADT7411_CFG1_START_MONITOR; val 636 drivers/hwmon/adt7411.c return i2c_smbus_write_byte_data(data->client, ADT7411_REG_CFG1, val); val 733 drivers/hwmon/adt7470.c unsigned char val; val 749 drivers/hwmon/adt7470.c val = i2c_smbus_read_byte_data(client, ADT7470_REG_CFG); val 751 drivers/hwmon/adt7470.c (val & ~ADT7470_CFG_LF) | low_freq); val 753 drivers/hwmon/adt7470.c val = i2c_smbus_read_byte_data(client, ADT7470_REG_CFG_2); val 755 drivers/hwmon/adt7470.c (val & ~ADT7470_FREQ_MASK) | (index << ADT7470_FREQ_SHIFT)); val 225 drivers/hwmon/adt7475.c static inline u16 temp2reg(struct adt7475_data *data, long val) val 230 drivers/hwmon/adt7475.c val = clamp_val(val, -64000, 191000); val 231 drivers/hwmon/adt7475.c ret = (val + 64500) / 1000; val 233 drivers/hwmon/adt7475.c val = clamp_val(val, -128000, 127000); val 234 drivers/hwmon/adt7475.c if (val < -500) val 235 drivers/hwmon/adt7475.c ret = (256500 + val) / 1000; val 237 drivers/hwmon/adt7475.c ret = (val + 500) / 1000; val 318 drivers/hwmon/adt7475.c static void adt7475_write_word(struct i2c_client *client, int reg, u16 val) val 320 drivers/hwmon/adt7475.c i2c_smbus_write_byte_data(client, reg + 1, val >> 8); val 321 drivers/hwmon/adt7475.c i2c_smbus_write_byte_data(client, reg, val & 0xFF); val 329 drivers/hwmon/adt7475.c unsigned short val; val 339 drivers/hwmon/adt7475.c val = data->voltage[sattr->nr][sattr->index]; val 341 drivers/hwmon/adt7475.c reg2volt(sattr->index, val, data->bypass_attn)); val 354 drivers/hwmon/adt7475.c long val; val 356 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 362 drivers/hwmon/adt7475.c volt2reg(sattr->index, val, data->bypass_attn); val 450 drivers/hwmon/adt7475.c long val; val 452 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 463 drivers/hwmon/adt7475.c val = clamp_val(val, -63000, 127000); val 464 drivers/hwmon/adt7475.c out = data->temp[OFFSET][sattr->index] = val / 1000; val 466 drivers/hwmon/adt7475.c val = clamp_val(val, -63000, 64000); val 467 drivers/hwmon/adt7475.c out = data->temp[OFFSET][sattr->index] = val / 500; val 483 drivers/hwmon/adt7475.c val = clamp_val(val, temp - 15000, temp); val 484 drivers/hwmon/adt7475.c val = (temp - val) / 1000; val 488 drivers/hwmon/adt7475.c data->temp[HYSTERSIS][sattr->index] |= (val & 0xF) << 4; val 491 drivers/hwmon/adt7475.c data->temp[HYSTERSIS][sattr->index] |= (val & 0xF); val 498 drivers/hwmon/adt7475.c data->temp[sattr->nr][sattr->index] = temp2reg(data, val); val 548 drivers/hwmon/adt7475.c long val; val 552 drivers/hwmon/adt7475.c val = data->enh_acoustics[0] & 0xf; val 555 drivers/hwmon/adt7475.c val = (data->enh_acoustics[1] >> 4) & 0xf; val 559 drivers/hwmon/adt7475.c val = data->enh_acoustics[1] & 0xf; val 563 drivers/hwmon/adt7475.c if (val & 0x8) val 564 drivers/hwmon/adt7475.c return sprintf(buf, "%d\n", ad7475_st_map[val & 0x7]); val 578 drivers/hwmon/adt7475.c ulong val; val 580 drivers/hwmon/adt7475.c if (kstrtoul(buf, 10, &val)) val 602 drivers/hwmon/adt7475.c if (val > 0) { val 603 drivers/hwmon/adt7475.c val = find_closest_descending(val, ad7475_st_map, val 605 drivers/hwmon/adt7475.c val |= 0x8; val 611 drivers/hwmon/adt7475.c data->enh_acoustics[idx] |= (val << shift); val 635 drivers/hwmon/adt7475.c int out, val; val 642 drivers/hwmon/adt7475.c val = reg2temp(data, data->temp[AUTOMIN][sattr->index]); val 645 drivers/hwmon/adt7475.c return sprintf(buf, "%d\n", val + autorange_table[out]); val 655 drivers/hwmon/adt7475.c long val; val 657 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 674 drivers/hwmon/adt7475.c val = clamp_val(val, temp + autorange_table[0], val 676 drivers/hwmon/adt7475.c val -= temp; val 679 drivers/hwmon/adt7475.c val = find_closest(val, autorange_table, ARRAY_SIZE(autorange_table)); val 682 drivers/hwmon/adt7475.c data->range[sattr->index] |= val << 4; val 716 drivers/hwmon/adt7475.c unsigned long val; val 718 drivers/hwmon/adt7475.c if (kstrtoul(buf, 10, &val)) val 723 drivers/hwmon/adt7475.c data->tach[MIN][sattr->index] = rpm2tach(val); val 776 drivers/hwmon/adt7475.c long val; val 778 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 810 drivers/hwmon/adt7475.c data->pwm[sattr->nr][sattr->index] = clamp_val(val, 0, 0xFF); val 836 drivers/hwmon/adt7475.c long val; val 839 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 845 drivers/hwmon/adt7475.c if (val) val 862 drivers/hwmon/adt7475.c long val = 0; val 866 drivers/hwmon/adt7475.c val = 0x03; /* Run at full speed */ val 869 drivers/hwmon/adt7475.c val = 0x07; /* Manual mode */ val 875 drivers/hwmon/adt7475.c val = 0x00; val 879 drivers/hwmon/adt7475.c val = 0x01; val 883 drivers/hwmon/adt7475.c val = 0x02; val 887 drivers/hwmon/adt7475.c val = 0x05; val 891 drivers/hwmon/adt7475.c val = 0x06; val 905 drivers/hwmon/adt7475.c data->pwm[CONTROL][index] |= (val & 7) << 5; val 921 drivers/hwmon/adt7475.c long val; val 923 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 929 drivers/hwmon/adt7475.c r = hw_set_pwm(client, sattr->index, data->pwmctl[sattr->index], val); val 945 drivers/hwmon/adt7475.c long val; val 947 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 953 drivers/hwmon/adt7475.c r = hw_set_pwm(client, sattr->index, val, data->pwmchan[sattr->index]); val 989 drivers/hwmon/adt7475.c long val; val 991 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 994 drivers/hwmon/adt7475.c out = find_closest(val, pwmfreq_table, ARRAY_SIZE(pwmfreq_table)); val 1028 drivers/hwmon/adt7475.c long val; val 1030 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 1032 drivers/hwmon/adt7475.c if (val != 0 && val != 1) val 1037 drivers/hwmon/adt7475.c if (val) val 1058 drivers/hwmon/adt7475.c long val; val 1060 drivers/hwmon/adt7475.c if (kstrtol(buf, 10, &val)) val 1062 drivers/hwmon/adt7475.c if (val < 0 || val > 255) val 1064 drivers/hwmon/adt7475.c data->vrm = val; val 282 drivers/hwmon/amc6821.c long val; val 284 drivers/hwmon/amc6821.c int ret = kstrtol(buf, 10, &val); val 287 drivers/hwmon/amc6821.c val = clamp_val(val / 1000, -128, 127); val 290 drivers/hwmon/amc6821.c data->temp[ix] = val; val 358 drivers/hwmon/amc6821.c long val; val 359 drivers/hwmon/amc6821.c int ret = kstrtol(buf, 10, &val); val 364 drivers/hwmon/amc6821.c data->pwm1 = clamp_val(val , 0, 255); val 383 drivers/hwmon/amc6821.c long val; val 384 drivers/hwmon/amc6821.c int config = kstrtol(buf, 10, &val); val 397 drivers/hwmon/amc6821.c switch (val) { val 494 drivers/hwmon/amc6821.c long val; val 495 drivers/hwmon/amc6821.c int ret = kstrtol(buf, 10, &val); val 518 drivers/hwmon/amc6821.c ptemp[0] = clamp_val(val / 1000, 0, val 533 drivers/hwmon/amc6821.c ptemp[1] = clamp_val(val / 1000, (ptemp[0] & 0x7C) + 4, 124); val 538 drivers/hwmon/amc6821.c ptemp[2] = clamp_val(val / 1000, ptemp[1]+1, 255); val 561 drivers/hwmon/amc6821.c long val; val 562 drivers/hwmon/amc6821.c int ret = kstrtol(buf, 10, &val); val 567 drivers/hwmon/amc6821.c data->pwm1_auto_point_pwm[1] = clamp_val(val, 0, 254); val 617 drivers/hwmon/amc6821.c long val; val 619 drivers/hwmon/amc6821.c int ret = kstrtol(buf, 10, &val); val 622 drivers/hwmon/amc6821.c val = 1 > val ? 0xFFFF : 6000000/val; val 625 drivers/hwmon/amc6821.c data->fan[ix] = (u16) clamp_val(val, 1, 0xFFFF); val 655 drivers/hwmon/amc6821.c long val; val 656 drivers/hwmon/amc6821.c int config = kstrtol(buf, 10, &val); val 668 drivers/hwmon/amc6821.c switch (val) { val 864 drivers/hwmon/applesmc.c u16 val; val 870 drivers/hwmon/applesmc.c val = (buffer[0] << 8 | buffer[1]); val 875 drivers/hwmon/applesmc.c val = val | (0x01 << to_index(attr)); val 877 drivers/hwmon/applesmc.c val = val & ~(0x01 << to_index(attr)); val 879 drivers/hwmon/applesmc.c buffer[0] = (val >> 8) & 0xFF; val 880 drivers/hwmon/applesmc.c buffer[1] = val & 0xFF; val 33 drivers/hwmon/as370-hwmon.c u32 val; val 36 drivers/hwmon/as370-hwmon.c val = PD; val 37 drivers/hwmon/as370-hwmon.c writel_relaxed(val, addr); val 38 drivers/hwmon/as370-hwmon.c val |= T_SEL; val 39 drivers/hwmon/as370-hwmon.c writel_relaxed(val, addr); val 40 drivers/hwmon/as370-hwmon.c val |= EN; val 41 drivers/hwmon/as370-hwmon.c writel_relaxed(val, addr); val 42 drivers/hwmon/as370-hwmon.c val &= ~PD; val 43 drivers/hwmon/as370-hwmon.c writel_relaxed(val, addr); val 49 drivers/hwmon/as370-hwmon.c int val; val 54 drivers/hwmon/as370-hwmon.c val = readl_relaxed(hwmon->base + STS) & BN_MASK; val 55 drivers/hwmon/as370-hwmon.c *temp = DIV_ROUND_CLOSEST(val * 251802, 4096) - 85525; val 102 drivers/hwmon/asb100.c static u8 IN_TO_REG(unsigned val) val 104 drivers/hwmon/asb100.c unsigned nval = clamp_val(val, ASB100_IN_MIN, ASB100_IN_MAX); val 123 drivers/hwmon/asb100.c static int FAN_FROM_REG(u8 val, int div) val 125 drivers/hwmon/asb100.c return val == 0 ? -1 : val == 255 ? 0 : 1350000 / (val * div); val 163 drivers/hwmon/asb100.c #define DIV_FROM_REG(val) (1 << (val)) val 169 drivers/hwmon/asb100.c static u8 DIV_TO_REG(long val) val 171 drivers/hwmon/asb100.c return val == 8 ? 3 : val == 4 ? 2 : val == 1 ? 0 : 1; val 206 drivers/hwmon/asb100.c static void asb100_write_value(struct i2c_client *client, u16 reg, u16 val); val 255 drivers/hwmon/asb100.c unsigned long val; \ val 256 drivers/hwmon/asb100.c int err = kstrtoul(buf, 10, &val); \ val 260 drivers/hwmon/asb100.c data->in_##reg[nr] = IN_TO_REG(val); \ val 319 drivers/hwmon/asb100.c unsigned long val; val 322 drivers/hwmon/asb100.c err = kstrtoul(buf, 10, &val); val 327 drivers/hwmon/asb100.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 347 drivers/hwmon/asb100.c unsigned long val; val 350 drivers/hwmon/asb100.c err = kstrtoul(buf, 10, &val); val 358 drivers/hwmon/asb100.c data->fan_div[nr] = DIV_TO_REG(val); val 437 drivers/hwmon/asb100.c long val; \ val 438 drivers/hwmon/asb100.c int err = kstrtol(buf, 10, &val); \ val 444 drivers/hwmon/asb100.c data->reg[nr] = LM75_TEMP_TO_REG(val); \ val 447 drivers/hwmon/asb100.c data->reg[nr] = TEMP_TO_REG(val); \ val 494 drivers/hwmon/asb100.c unsigned long val; val 497 drivers/hwmon/asb100.c err = kstrtoul(buf, 10, &val); val 501 drivers/hwmon/asb100.c if (val > 255) val 504 drivers/hwmon/asb100.c data->vrm = val; val 552 drivers/hwmon/asb100.c unsigned long val; val 555 drivers/hwmon/asb100.c err = kstrtoul(buf, 10, &val); val 561 drivers/hwmon/asb100.c data->pwm |= (0x0f & ASB100_PWM_TO_REG(val)); val 580 drivers/hwmon/asb100.c unsigned long val; val 583 drivers/hwmon/asb100.c err = kstrtoul(buf, 10, &val); val 589 drivers/hwmon/asb100.c data->pwm |= (val ? 0x80 : 0x00); val 696 drivers/hwmon/asb100.c int val = asb100_read_value(client, ASB100_REG_I2C_SUBADDR); val 697 drivers/hwmon/asb100.c sc_addr[0] = 0x48 + (val & 0x07); val 698 drivers/hwmon/asb100.c sc_addr[1] = 0x48 + ((val >> 4) & 0x07); val 560 drivers/hwmon/asc7621.c u8 config, altbit, minoff, val, newval; val 568 drivers/hwmon/asc7621.c val = config | (altbit << 3); val 570 drivers/hwmon/asc7621.c if (val == 3 || val >= 10) val 572 drivers/hwmon/asc7621.c else if (val == 4) val 574 drivers/hwmon/asc7621.c else if (val == 7) val 347 drivers/hwmon/aspeed-pwm-tacho.c unsigned int val) val 351 drivers/hwmon/aspeed-pwm-tacho.c writel(val, regs + reg); val 356 drivers/hwmon/aspeed-pwm-tacho.c unsigned int *val) val 360 drivers/hwmon/aspeed-pwm-tacho.c *val = readl(regs + reg); val 374 drivers/hwmon/aspeed-pwm-tacho.c static void aspeed_set_clock_enable(struct regmap *regmap, bool val) val 378 drivers/hwmon/aspeed-pwm-tacho.c val ? ASPEED_PTCR_CTRL_CLK_EN : 0); val 381 drivers/hwmon/aspeed-pwm-tacho.c static void aspeed_set_clock_source(struct regmap *regmap, int val) val 385 drivers/hwmon/aspeed-pwm-tacho.c val ? ASPEED_PTCR_CTRL_CLK_SRC : 0); val 527 drivers/hwmon/aspeed-pwm-tacho.c u32 raw_data, tach_div, clk_source, msec, usec, val; val 543 drivers/hwmon/aspeed-pwm-tacho.c val, val 544 drivers/hwmon/aspeed-pwm-tacho.c (val & RESULT_STATUS_MASK), val 552 drivers/hwmon/aspeed-pwm-tacho.c raw_data = val & RESULT_VALUE_MASK; val 746 drivers/hwmon/aspeed-pwm-tacho.c u8 val, index; val 748 drivers/hwmon/aspeed-pwm-tacho.c for (val = 0; val < count; val++) { val 749 drivers/hwmon/aspeed-pwm-tacho.c index = fan_tach_ch[val]; val 657 drivers/hwmon/asus_atk0110.c static int atk_debugfs_gitm_get(void *p, u64 *val) val 676 drivers/hwmon/asus_atk0110.c *val = buf->value; val 345 drivers/hwmon/coretemp.c u32 val; val 356 drivers/hwmon/coretemp.c val = (eax >> 16) & 0xff; val 361 drivers/hwmon/coretemp.c if (val) { val 362 drivers/hwmon/coretemp.c dev_dbg(dev, "TjMax is %d degrees C\n", val); val 363 drivers/hwmon/coretemp.c return val * 1000; val 169 drivers/hwmon/da9052-hwmon.c u8 val = DA9052_TSICONTB_TSIMAN; val 173 drivers/hwmon/da9052-hwmon.c val |= DA9052_TSICONTB_TSIMUX_XP; val 176 drivers/hwmon/da9052-hwmon.c val |= DA9052_TSICONTB_TSIMUX_YP; val 179 drivers/hwmon/da9052-hwmon.c val |= DA9052_TSICONTB_TSIMUX_XN; val 182 drivers/hwmon/da9052-hwmon.c val |= DA9052_TSICONTB_TSIMUX_YN; val 186 drivers/hwmon/da9052-hwmon.c return da9052_reg_write(hwmon->da9052, DA9052_TSI_CONT_B_REG, val); val 429 drivers/hwmon/dell-smm-hwmon.c int val = 0; val 443 drivers/hwmon/dell-smm-hwmon.c val = (bios_version[0] << 16) | val 456 drivers/hwmon/dell-smm-hwmon.c val = i8k_get_fn_status(); val 460 drivers/hwmon/dell-smm-hwmon.c val = i8k_get_power_status(); val 464 drivers/hwmon/dell-smm-hwmon.c val = i8k_get_temp(0); val 468 drivers/hwmon/dell-smm-hwmon.c if (copy_from_user(&val, argp, sizeof(int))) val 471 drivers/hwmon/dell-smm-hwmon.c val = i8k_get_fan_speed(val); val 475 drivers/hwmon/dell-smm-hwmon.c if (copy_from_user(&val, argp, sizeof(int))) val 478 drivers/hwmon/dell-smm-hwmon.c val = i8k_get_fan_status(val); val 485 drivers/hwmon/dell-smm-hwmon.c if (copy_from_user(&val, argp, sizeof(int))) val 491 drivers/hwmon/dell-smm-hwmon.c val = i8k_set_fan(val, speed); val 498 drivers/hwmon/dell-smm-hwmon.c if (val < 0) val 499 drivers/hwmon/dell-smm-hwmon.c return val; val 503 drivers/hwmon/dell-smm-hwmon.c if (copy_to_user(argp, &val, 4)) val 513 drivers/hwmon/dell-smm-hwmon.c if (copy_to_user(argp, &val, sizeof(int))) val 714 drivers/hwmon/dell-smm-hwmon.c unsigned long val; val 717 drivers/hwmon/dell-smm-hwmon.c err = kstrtoul(buf, 10, &val); val 720 drivers/hwmon/dell-smm-hwmon.c val = clamp_val(DIV_ROUND_CLOSEST(val, i8k_pwm_mult), 0, i8k_fan_max); val 723 drivers/hwmon/dell-smm-hwmon.c err = i8k_set_fan(index, val); val 267 drivers/hwmon/dme1737.c static inline int IN_TO_REG(long val, int nominal) val 269 drivers/hwmon/dme1737.c val = clamp_val(val, 0, 255 * nominal / 192); val 270 drivers/hwmon/dme1737.c return DIV_ROUND_CLOSEST(val * 192, nominal); val 284 drivers/hwmon/dme1737.c static inline int TEMP_TO_REG(long val) val 286 drivers/hwmon/dme1737.c val = clamp_val(val, -128000, 127000); val 287 drivers/hwmon/dme1737.c return DIV_ROUND_CLOSEST(val, 1000); val 300 drivers/hwmon/dme1737.c static int TEMP_RANGE_TO_REG(long val, int reg) val 305 drivers/hwmon/dme1737.c if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) val 340 drivers/hwmon/dme1737.c static inline int FAN_TO_REG(long val, int tpc) val 343 drivers/hwmon/dme1737.c return clamp_val(val / tpc, 0, 0xffff); val 345 drivers/hwmon/dme1737.c return (val <= 0) ? 0xffff : val 346 drivers/hwmon/dme1737.c clamp_val(90000 * 60 / val, 0, 0xfffe); val 372 drivers/hwmon/dme1737.c static inline int FAN_TYPE_TO_REG(long val, int reg) val 374 drivers/hwmon/dme1737.c int edge = (val == 4) ? 3 : val; val 395 drivers/hwmon/dme1737.c static int FAN_MAX_TO_REG(long val) val 400 drivers/hwmon/dme1737.c if (val > (1000 + (i - 1) * 500)) val 426 drivers/hwmon/dme1737.c static inline int PWM_EN_TO_REG(int val, int reg) val 428 drivers/hwmon/dme1737.c int en = (val == 1) ? 7 : 3; val 453 drivers/hwmon/dme1737.c static inline int PWM_ACZ_TO_REG(long val, int reg) val 455 drivers/hwmon/dme1737.c int acz = (val == 4) ? 2 : val - 1; val 469 drivers/hwmon/dme1737.c static int PWM_FREQ_TO_REG(long val, int reg) val 474 drivers/hwmon/dme1737.c if (val > 27500) { val 476 drivers/hwmon/dme1737.c } else if (val > 22500) { val 480 drivers/hwmon/dme1737.c if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) val 503 drivers/hwmon/dme1737.c static int PWM_RR_TO_REG(long val, int ix, int reg) val 508 drivers/hwmon/dme1737.c if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) val 521 drivers/hwmon/dme1737.c static inline int PWM_RR_EN_TO_REG(long val, int ix, int reg) val 525 drivers/hwmon/dme1737.c return val ? reg | en : reg & ~en; val 538 drivers/hwmon/dme1737.c static inline int PWM_OFF_TO_REG(int val, int ix, int reg) val 540 drivers/hwmon/dme1737.c return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5)); val 555 drivers/hwmon/dme1737.c s32 val; val 558 drivers/hwmon/dme1737.c val = i2c_smbus_read_byte_data(client, reg); val 560 drivers/hwmon/dme1737.c if (val < 0) { val 567 drivers/hwmon/dme1737.c val = inb(data->addr + 1); val 570 drivers/hwmon/dme1737.c return val; val 573 drivers/hwmon/dme1737.c static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val) val 579 drivers/hwmon/dme1737.c res = i2c_smbus_write_byte_data(client, reg, val); val 588 drivers/hwmon/dme1737.c outb(val, data->addr + 1); val 838 drivers/hwmon/dme1737.c long val; val 841 drivers/hwmon/dme1737.c err = kstrtol(buf, 10, &val); val 848 drivers/hwmon/dme1737.c data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]); val 853 drivers/hwmon/dme1737.c data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]); val 922 drivers/hwmon/dme1737.c long val; val 925 drivers/hwmon/dme1737.c err = kstrtol(buf, 10, &val); val 932 drivers/hwmon/dme1737.c data->temp_min[ix] = TEMP_TO_REG(val); val 937 drivers/hwmon/dme1737.c data->temp_max[ix] = TEMP_TO_REG(val); val 942 drivers/hwmon/dme1737.c data->temp_offset[ix] = TEMP_TO_REG(val); val 1014 drivers/hwmon/dme1737.c long val; val 1019 drivers/hwmon/dme1737.c err = kstrtol(buf, 10, &val); val 1032 drivers/hwmon/dme1737.c data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(temp, val, ix, reg); val 1037 drivers/hwmon/dme1737.c data->zone_low[ix] = TEMP_TO_REG(val); val 1050 drivers/hwmon/dme1737.c val = clamp_val(val, temp, temp + 80000); val 1052 drivers/hwmon/dme1737.c data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - temp, reg); val 1057 drivers/hwmon/dme1737.c data->zone_abs[ix] = TEMP_TO_REG(val); val 1128 drivers/hwmon/dme1737.c long val; val 1131 drivers/hwmon/dme1737.c err = kstrtol(buf, 10, &val); val 1139 drivers/hwmon/dme1737.c data->fan_min[ix] = FAN_TO_REG(val, 0); val 1145 drivers/hwmon/dme1737.c data->fan_min[ix] = FAN_TO_REG(val, val 1155 drivers/hwmon/dme1737.c data->fan_max[ix - 4] = FAN_MAX_TO_REG(val); val 1161 drivers/hwmon/dme1737.c if (!(val == 1 || val == 2 || val == 4)) { val 1165 drivers/hwmon/dme1737.c val); val 1168 drivers/hwmon/dme1737.c data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data, val 1267 drivers/hwmon/dme1737.c long val; val 1270 drivers/hwmon/dme1737.c err = kstrtol(buf, 10, &val); val 1277 drivers/hwmon/dme1737.c data->pwm[ix] = clamp_val(val, 0, 255); val 1281 drivers/hwmon/dme1737.c data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data, val 1288 drivers/hwmon/dme1737.c if (val < 0 || val > 2) { val 1292 drivers/hwmon/dme1737.c val); val 1298 drivers/hwmon/dme1737.c if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) { val 1321 drivers/hwmon/dme1737.c switch (val) { val 1375 drivers/hwmon/dme1737.c if (val > 0) { val 1376 drivers/hwmon/dme1737.c data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix, val 1384 drivers/hwmon/dme1737.c data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix, val 1392 drivers/hwmon/dme1737.c if (!(val == 1 || val == 2 || val == 4 || val 1393 drivers/hwmon/dme1737.c val == 6 || val == 7)) { val 1397 drivers/hwmon/dme1737.c "or 7.\n", val); val 1408 drivers/hwmon/dme1737.c data->pwm_config[ix] = PWM_ACZ_TO_REG(val, val 1417 drivers/hwmon/dme1737.c data->pwm_acz[ix] = val; val 1431 drivers/hwmon/dme1737.c if (val > ((data->pwm_min[ix] + 1) / 2)) { val 1445 drivers/hwmon/dme1737.c data->pwm_min[ix] = clamp_val(val, 0, 255); val 1475 drivers/hwmon/dme1737.c unsigned long val; val 1478 drivers/hwmon/dme1737.c err = kstrtoul(buf, 10, &val); val 1482 drivers/hwmon/dme1737.c if (val > 255) val 1485 drivers/hwmon/dme1737.c data->vrm = val; val 2031 drivers/hwmon/dme1737.c static inline void dme1737_sio_outb(int sio_cip, int reg, int val) val 2034 drivers/hwmon/dme1737.c outb(val, sio_cip + 1); val 105 drivers/hwmon/ds1621.c #define ALARMS_FROM_REG(val) ((val) & \ val 238 drivers/hwmon/ds1621.c long val; val 241 drivers/hwmon/ds1621.c err = kstrtol(buf, 10, &val); val 246 drivers/hwmon/ds1621.c data->temp[attr->index] = DS1621_TEMP_TO_REG(val, data->zbits); val 145 drivers/hwmon/ds620.c long val; val 151 drivers/hwmon/ds620.c res = kstrtol(buf, 10, &val); val 156 drivers/hwmon/ds620.c val = (clamp_val(val, -128000, 128000) * 10 / 625) * 8; val 159 drivers/hwmon/ds620.c data->temp[attr->index] = val; val 40 drivers/hwmon/emc1403.c unsigned int val; val 43 drivers/hwmon/emc1403.c retval = regmap_read(data->regmap, sda->index, &val); val 46 drivers/hwmon/emc1403.c return sprintf(buf, "%d000\n", val); val 54 drivers/hwmon/emc1403.c unsigned int val; val 57 drivers/hwmon/emc1403.c retval = regmap_read(data->regmap, sda->nr, &val); val 60 drivers/hwmon/emc1403.c return sprintf(buf, "%d\n", !!(val & sda->index)); val 68 drivers/hwmon/emc1403.c unsigned long val; val 71 drivers/hwmon/emc1403.c if (kstrtoul(buf, 10, &val)) val 74 drivers/hwmon/emc1403.c DIV_ROUND_CLOSEST(val, 1000)); val 85 drivers/hwmon/emc1403.c unsigned long val; val 88 drivers/hwmon/emc1403.c if (kstrtoul(buf, 10, &val)) val 92 drivers/hwmon/emc1403.c val ? sda->index : 0); val 141 drivers/hwmon/emc1403.c unsigned long val; val 143 drivers/hwmon/emc1403.c if (kstrtoul(buf, 10, &val)) val 151 drivers/hwmon/emc1403.c hyst = limit * 1000 - val; val 237 drivers/hwmon/emc2103.c long val; val 239 drivers/hwmon/emc2103.c int result = kstrtol(buf, 10, &val); val 243 drivers/hwmon/emc2103.c val = DIV_ROUND_CLOSEST(clamp_val(val, -63000, 127000), 1000); val 246 drivers/hwmon/emc2103.c data->temp_min[nr] = val; val 247 drivers/hwmon/emc2103.c i2c_smbus_write_byte_data(client, REG_TEMP_MIN[nr], val); val 259 drivers/hwmon/emc2103.c long val; val 261 drivers/hwmon/emc2103.c int result = kstrtol(buf, 10, &val); val 265 drivers/hwmon/emc2103.c val = DIV_ROUND_CLOSEST(clamp_val(val, -63000, 127000), 1000); val 268 drivers/hwmon/emc2103.c data->temp_max[nr] = val; val 269 drivers/hwmon/emc2103.c i2c_smbus_write_byte_data(client, REG_TEMP_MAX[nr], val); val 80 drivers/hwmon/emc6w201.c static int emc6w201_write16(struct i2c_client *client, u8 reg, u16 val) val 84 drivers/hwmon/emc6w201.c err = i2c_smbus_write_byte_data(client, reg, val & 0xff); val 86 drivers/hwmon/emc6w201.c err = i2c_smbus_write_byte_data(client, reg + 1, val >> 8); val 97 drivers/hwmon/emc6w201.c int val; val 99 drivers/hwmon/emc6w201.c val = i2c_smbus_read_byte_data(client, reg); val 100 drivers/hwmon/emc6w201.c if (unlikely(val < 0)) { val 106 drivers/hwmon/emc6w201.c return val; val 110 drivers/hwmon/emc6w201.c static int emc6w201_write8(struct i2c_client *client, u8 reg, u8 val) val 114 drivers/hwmon/emc6w201.c err = i2c_smbus_write_byte_data(client, reg, val); val 198 drivers/hwmon/emc6w201.c long val; val 201 drivers/hwmon/emc6w201.c err = kstrtol(buf, 10, &val); val 205 drivers/hwmon/emc6w201.c val = clamp_val(val, 0, 255 * nominal_mv[nr] / 192); val 206 drivers/hwmon/emc6w201.c val = DIV_ROUND_CLOSEST(val * 192, nominal_mv[nr]); val 211 drivers/hwmon/emc6w201.c data->in[sf][nr] = val; val 237 drivers/hwmon/emc6w201.c long val; val 240 drivers/hwmon/emc6w201.c err = kstrtol(buf, 10, &val); val 244 drivers/hwmon/emc6w201.c val = clamp_val(val, -127000, 127000); val 245 drivers/hwmon/emc6w201.c val = DIV_ROUND_CLOSEST(val, 1000); val 250 drivers/hwmon/emc6w201.c data->temp[sf][nr] = val; val 281 drivers/hwmon/emc6w201.c unsigned long val; val 283 drivers/hwmon/emc6w201.c err = kstrtoul(buf, 10, &val); val 287 drivers/hwmon/emc6w201.c if (val == 0) { val 288 drivers/hwmon/emc6w201.c val = 0xFFFF; val 290 drivers/hwmon/emc6w201.c val = DIV_ROUND_CLOSEST(5400000U, val); val 291 drivers/hwmon/emc6w201.c val = clamp_val(val, 0, 0xFFFE); val 295 drivers/hwmon/emc6w201.c data->fan[sf][nr] = val; val 71 drivers/hwmon/f71805f.c int val; val 73 drivers/hwmon/f71805f.c val = inb(base + 1) << 8; val 75 drivers/hwmon/f71805f.c val |= inb(base + 1); val 76 drivers/hwmon/f71805f.c return val; val 202 drivers/hwmon/f71805f.c static inline u8 in_to_reg(long val) val 204 drivers/hwmon/f71805f.c if (val <= 0) val 206 drivers/hwmon/f71805f.c if (val >= 2016) val 208 drivers/hwmon/f71805f.c return ((val + 16) / 32) << 2; val 217 drivers/hwmon/f71805f.c static inline u8 in0_to_reg(long val) val 219 drivers/hwmon/f71805f.c if (val <= 0) val 221 drivers/hwmon/f71805f.c if (val >= 4032) val 223 drivers/hwmon/f71805f.c return ((val + 32) / 64) << 2; val 257 drivers/hwmon/f71805f.c static inline u8 pwm_freq_to_reg(unsigned long val) val 259 drivers/hwmon/f71805f.c if (val >= 187500) /* The highest we can do */ val 261 drivers/hwmon/f71805f.c if (val >= 1475) /* Use 48 MHz clock */ val 262 drivers/hwmon/f71805f.c return 0x80 | (48000000UL / (val << 8)); val 263 drivers/hwmon/f71805f.c if (val < 31) /* The lowest we can do */ val 266 drivers/hwmon/f71805f.c return 1000000UL / (val << 8); val 279 drivers/hwmon/f71805f.c static inline u8 temp_to_reg(long val) val 281 drivers/hwmon/f71805f.c if (val <= 0) val 283 drivers/hwmon/f71805f.c if (val >= 1000 * 0xff) val 285 drivers/hwmon/f71805f.c return (val + 500) / 1000; val 300 drivers/hwmon/f71805f.c static void f71805f_write8(struct f71805f_data *data, u8 reg, u8 val) val 303 drivers/hwmon/f71805f.c outb(val, data->addr + DATA_REG_OFFSET); val 313 drivers/hwmon/f71805f.c u16 val; val 316 drivers/hwmon/f71805f.c val = inb(data->addr + DATA_REG_OFFSET) << 8; val 318 drivers/hwmon/f71805f.c val |= inb(data->addr + DATA_REG_OFFSET); val 320 drivers/hwmon/f71805f.c return val; val 324 drivers/hwmon/f71805f.c static void f71805f_write16(struct f71805f_data *data, u8 reg, u16 val) val 327 drivers/hwmon/f71805f.c outb(val >> 8, data->addr + DATA_REG_OFFSET); val 329 drivers/hwmon/f71805f.c outb(val & 0xff, data->addr + DATA_REG_OFFSET); val 455 drivers/hwmon/f71805f.c long val; val 458 drivers/hwmon/f71805f.c err = kstrtol(buf, 10, &val); val 463 drivers/hwmon/f71805f.c data->in_high[nr] = in0_to_reg(val); val 476 drivers/hwmon/f71805f.c long val; val 479 drivers/hwmon/f71805f.c err = kstrtol(buf, 10, &val); val 484 drivers/hwmon/f71805f.c data->in_low[nr] = in0_to_reg(val); val 527 drivers/hwmon/f71805f.c long val; val 530 drivers/hwmon/f71805f.c err = kstrtol(buf, 10, &val); val 535 drivers/hwmon/f71805f.c data->in_high[nr] = in_to_reg(val); val 548 drivers/hwmon/f71805f.c long val; val 551 drivers/hwmon/f71805f.c err = kstrtol(buf, 10, &val); val 556 drivers/hwmon/f71805f.c data->in_low[nr] = in_to_reg(val); val 599 drivers/hwmon/f71805f.c long val; val 602 drivers/hwmon/f71805f.c err = kstrtol(buf, 10, &val); val 607 drivers/hwmon/f71805f.c data->fan_low[nr] = fan_to_reg(val); val 620 drivers/hwmon/f71805f.c long val; val 623 drivers/hwmon/f71805f.c err = kstrtol(buf, 10, &val); val 628 drivers/hwmon/f71805f.c data->fan_target[nr] = fan_to_reg(val); val 694 drivers/hwmon/f71805f.c unsigned long val; val 697 drivers/hwmon/f71805f.c err = kstrtoul(buf, 10, &val); val 701 drivers/hwmon/f71805f.c if (val > 255) val 705 drivers/hwmon/f71805f.c data->pwm[nr] = val; val 721 drivers/hwmon/f71805f.c unsigned long val; val 724 drivers/hwmon/f71805f.c err = kstrtoul(buf, 10, &val); val 728 drivers/hwmon/f71805f.c if (val < 1 || val > 3) val 731 drivers/hwmon/f71805f.c if (val > 1) { /* Automatic mode, user can't set PWM value */ val 740 drivers/hwmon/f71805f.c switch (val) { val 755 drivers/hwmon/f71805f.c if (val == 1) { /* Manual mode, user can set PWM value */ val 770 drivers/hwmon/f71805f.c unsigned long val; val 773 drivers/hwmon/f71805f.c err = kstrtoul(buf, 10, &val); val 778 drivers/hwmon/f71805f.c data->pwm_freq[nr] = pwm_freq_to_reg(val); val 806 drivers/hwmon/f71805f.c unsigned long val; val 809 drivers/hwmon/f71805f.c err = kstrtoul(buf, 10, &val); val 814 drivers/hwmon/f71805f.c data->auto_points[pwmnr].temp[apnr] = temp_to_reg(val); val 843 drivers/hwmon/f71805f.c unsigned long val; val 846 drivers/hwmon/f71805f.c err = kstrtoul(buf, 10, &val); val 851 drivers/hwmon/f71805f.c data->auto_points[pwmnr].fan[apnr] = fan_to_reg(val); val 906 drivers/hwmon/f71805f.c long val; val 909 drivers/hwmon/f71805f.c err = kstrtol(buf, 10, &val); val 914 drivers/hwmon/f71805f.c data->temp_high[nr] = temp_to_reg(val); val 927 drivers/hwmon/f71805f.c long val; val 930 drivers/hwmon/f71805f.c err = kstrtol(buf, 10, &val); val 935 drivers/hwmon/f71805f.c data->temp_hyst[nr] = temp_to_reg(val); val 1112 drivers/hwmon/f71882fg.c int val; val 1113 drivers/hwmon/f71882fg.c val = superio_inb(base, reg) << 8; val 1114 drivers/hwmon/f71882fg.c val |= superio_inb(base, reg + 1); val 1115 drivers/hwmon/f71882fg.c return val; val 1157 drivers/hwmon/f71882fg.c u8 val; val 1160 drivers/hwmon/f71882fg.c val = inb(data->addr + DATA_REG_OFFSET); val 1162 drivers/hwmon/f71882fg.c return val; val 1167 drivers/hwmon/f71882fg.c u16 val; val 1169 drivers/hwmon/f71882fg.c val = f71882fg_read8(data, reg) << 8; val 1170 drivers/hwmon/f71882fg.c val |= f71882fg_read8(data, reg + 1); val 1172 drivers/hwmon/f71882fg.c return val; val 1175 drivers/hwmon/f71882fg.c static void f71882fg_write8(struct f71882fg_data *data, u8 reg, u8 val) val 1178 drivers/hwmon/f71882fg.c outb(val, data->addr + DATA_REG_OFFSET); val 1181 drivers/hwmon/f71882fg.c static void f71882fg_write16(struct f71882fg_data *data, u8 reg, u16 val) val 1183 drivers/hwmon/f71882fg.c f71882fg_write8(data, reg, val >> 8); val 1184 drivers/hwmon/f71882fg.c f71882fg_write8(data, reg + 1, val & 0xff); val 1399 drivers/hwmon/f71882fg.c long val; val 1401 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1405 drivers/hwmon/f71882fg.c val = clamp_val(val, 23, 1500000); val 1406 drivers/hwmon/f71882fg.c val = fan_to_reg(val); val 1409 drivers/hwmon/f71882fg.c f71882fg_write16(data, F71882FG_REG_FAN_FULL_SPEED(nr), val); val 1410 drivers/hwmon/f71882fg.c data->fan_full_speed[nr] = val; val 1433 drivers/hwmon/f71882fg.c unsigned long val; val 1435 drivers/hwmon/f71882fg.c err = kstrtoul(buf, 10, &val); val 1441 drivers/hwmon/f71882fg.c if (val) val 1486 drivers/hwmon/f71882fg.c long val; val 1488 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1492 drivers/hwmon/f71882fg.c val /= 8; val 1493 drivers/hwmon/f71882fg.c val = clamp_val(val, 0, 255); val 1497 drivers/hwmon/f71882fg.c f71882fg_write8(data, F81866_REG_IN1_HIGH, val); val 1499 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_IN1_HIGH, val); val 1500 drivers/hwmon/f71882fg.c data->in1_max = val; val 1523 drivers/hwmon/f71882fg.c unsigned long val; val 1525 drivers/hwmon/f71882fg.c err = kstrtoul(buf, 10, &val); val 1535 drivers/hwmon/f71882fg.c if (val) val 1600 drivers/hwmon/f71882fg.c long val; val 1602 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1606 drivers/hwmon/f71882fg.c val /= 1000; val 1607 drivers/hwmon/f71882fg.c val = clamp_val(val, 0, 255); val 1610 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_TEMP_HIGH(nr), val); val 1611 drivers/hwmon/f71882fg.c data->temp_high[nr] = val; val 1642 drivers/hwmon/f71882fg.c long val; val 1644 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1648 drivers/hwmon/f71882fg.c val /= 1000; val 1654 drivers/hwmon/f71882fg.c val = clamp_val(val, data->temp_high[nr] - 15, data->temp_high[nr]); val 1655 drivers/hwmon/f71882fg.c val = data->temp_high[nr] - val; val 1660 drivers/hwmon/f71882fg.c reg = (reg & 0x0f) | (val << 4); val 1662 drivers/hwmon/f71882fg.c reg = (reg & 0xf0) | val; val 1684 drivers/hwmon/f71882fg.c long val; val 1686 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1690 drivers/hwmon/f71882fg.c val /= 1000; val 1691 drivers/hwmon/f71882fg.c val = clamp_val(val, 0, 255); val 1694 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_TEMP_OVT(nr), val); val 1695 drivers/hwmon/f71882fg.c data->temp_ovt[nr] = val; val 1745 drivers/hwmon/f71882fg.c unsigned long val; val 1747 drivers/hwmon/f71882fg.c err = kstrtoul(buf, 10, &val); val 1753 drivers/hwmon/f71882fg.c if (val) val 1792 drivers/hwmon/f71882fg.c int val, nr = to_sensor_dev_attr_2(devattr)->index; val 1796 drivers/hwmon/f71882fg.c val = data->pwm[nr]; val 1799 drivers/hwmon/f71882fg.c val = 255 * fan_from_reg(data->fan_target[nr]) val 1803 drivers/hwmon/f71882fg.c return sprintf(buf, "%d\n", val); val 1812 drivers/hwmon/f71882fg.c long val; val 1814 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1818 drivers/hwmon/f71882fg.c val = clamp_val(val, 0, 255); val 1829 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_PWM(nr), val); val 1830 drivers/hwmon/f71882fg.c data->pwm[nr] = val; val 1836 drivers/hwmon/f71882fg.c target = fan_to_reg(val * fan_from_reg(full_speed) / 255); val 1851 drivers/hwmon/f71882fg.c int val, nr = to_sensor_dev_attr_2(devattr)->index; val 1853 drivers/hwmon/f71882fg.c val = data->pwm[nr]; val 1854 drivers/hwmon/f71882fg.c return sprintf(buf, "%d\n", val); val 1863 drivers/hwmon/f71882fg.c long val; val 1865 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1869 drivers/hwmon/f71882fg.c val = clamp_val(val, 0, 255); val 1872 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_PWM(nr), val); val 1873 drivers/hwmon/f71882fg.c data->pwm[nr] = val; val 1910 drivers/hwmon/f71882fg.c long val; val 1912 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1917 drivers/hwmon/f71882fg.c if (data->type == f8000 && nr == 2 && val != 2) val 1924 drivers/hwmon/f71882fg.c switch (val) { val 1936 drivers/hwmon/f71882fg.c switch (val) { val 1990 drivers/hwmon/f71882fg.c long val; val 1992 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 1996 drivers/hwmon/f71882fg.c val = clamp_val(val, 0, 255); val 2004 drivers/hwmon/f71882fg.c if (val < 29) /* Prevent negative numbers */ val 2005 drivers/hwmon/f71882fg.c val = 255; val 2007 drivers/hwmon/f71882fg.c val = (255 - val) * 32 / val; val 2009 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_POINT_PWM(pwm, point), val); val 2010 drivers/hwmon/f71882fg.c data->pwm_auto_point_pwm[pwm][point] = val; val 2044 drivers/hwmon/f71882fg.c long val; val 2046 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 2050 drivers/hwmon/f71882fg.c val /= 1000; val 2055 drivers/hwmon/f71882fg.c val = clamp_val(val, data->pwm_auto_point_temp[nr][point] - 15, val 2057 drivers/hwmon/f71882fg.c val = data->pwm_auto_point_temp[nr][point] - val; val 2061 drivers/hwmon/f71882fg.c reg = (reg & 0x0f) | (val << 4); val 2063 drivers/hwmon/f71882fg.c reg = (reg & 0xf0) | val; val 2090 drivers/hwmon/f71882fg.c unsigned long val; val 2092 drivers/hwmon/f71882fg.c err = kstrtoul(buf, 10, &val); val 2099 drivers/hwmon/f71882fg.c if (val) val 2100 drivers/hwmon/f71882fg.c val = data->pwm_auto_point_mapping[nr] | (1 << 4); val 2102 drivers/hwmon/f71882fg.c val = data->pwm_auto_point_mapping[nr] & (~(1 << 4)); val 2103 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_POINT_MAPPING(nr), val); val 2104 drivers/hwmon/f71882fg.c data->pwm_auto_point_mapping[nr] = val; val 2130 drivers/hwmon/f71882fg.c long val; val 2132 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 2136 drivers/hwmon/f71882fg.c switch (val) { val 2138 drivers/hwmon/f71882fg.c val = 0; val 2141 drivers/hwmon/f71882fg.c val = 1; val 2144 drivers/hwmon/f71882fg.c val = 2; val 2149 drivers/hwmon/f71882fg.c val += data->temp_start; val 2153 drivers/hwmon/f71882fg.c val = (data->pwm_auto_point_mapping[nr] & 0xfc) | val; val 2154 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_POINT_MAPPING(nr), val); val 2155 drivers/hwmon/f71882fg.c data->pwm_auto_point_mapping[nr] = val; val 2181 drivers/hwmon/f71882fg.c long val; val 2183 drivers/hwmon/f71882fg.c err = kstrtol(buf, 10, &val); val 2187 drivers/hwmon/f71882fg.c val /= 1000; val 2190 drivers/hwmon/f71882fg.c val = clamp_val(val, -128, 127); val 2192 drivers/hwmon/f71882fg.c val = clamp_val(val, 0, 127); val 2195 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_POINT_TEMP(pwm, point), val); val 2196 drivers/hwmon/f71882fg.c data->pwm_auto_point_temp[pwm][point] = val; val 291 drivers/hwmon/f75375s.c unsigned long val; val 294 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 299 drivers/hwmon/f75375s.c data->fan_min[nr] = rpm_to_reg(val); val 311 drivers/hwmon/f75375s.c unsigned long val; val 314 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 324 drivers/hwmon/f75375s.c data->fan_target[nr] = rpm_to_reg(val); val 336 drivers/hwmon/f75375s.c unsigned long val; val 339 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 348 drivers/hwmon/f75375s.c data->pwm[nr] = clamp_val(val, 0, 255); val 362 drivers/hwmon/f75375s.c static int set_pwm_enable_direct(struct i2c_client *client, int nr, int val) val 367 drivers/hwmon/f75375s.c if (val < 0 || val > 4) val 374 drivers/hwmon/f75375s.c duty_mode_enabled(val)) val 379 drivers/hwmon/f75375s.c switch (val) { val 401 drivers/hwmon/f75375s.c switch (val) { val 420 drivers/hwmon/f75375s.c data->pwm_enable[nr] = val; val 421 drivers/hwmon/f75375s.c if (val == 0) val 432 drivers/hwmon/f75375s.c unsigned long val; val 435 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 440 drivers/hwmon/f75375s.c err = set_pwm_enable_direct(client, nr, val); val 451 drivers/hwmon/f75375s.c unsigned long val; val 456 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 460 drivers/hwmon/f75375s.c if (!(val == 0 || val == 1)) val 464 drivers/hwmon/f75375s.c if (data->kind == f75373 && val == 0) val 480 drivers/hwmon/f75375s.c if (val == 0) val 484 drivers/hwmon/f75375s.c data->pwm_mode[nr] = val; val 505 drivers/hwmon/f75375s.c #define VOLT_FROM_REG(val) ((val) * 8) val 506 drivers/hwmon/f75375s.c #define VOLT_TO_REG(val) ((val) / 8) val 538 drivers/hwmon/f75375s.c unsigned long val; val 541 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 545 drivers/hwmon/f75375s.c val = clamp_val(VOLT_TO_REG(val), 0, 0xff); val 547 drivers/hwmon/f75375s.c data->in_max[nr] = val; val 559 drivers/hwmon/f75375s.c unsigned long val; val 562 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 566 drivers/hwmon/f75375s.c val = clamp_val(VOLT_TO_REG(val), 0, 0xff); val 568 drivers/hwmon/f75375s.c data->in_min[nr] = val; val 573 drivers/hwmon/f75375s.c #define TEMP_FROM_REG(val) ((val) * 1000) val 574 drivers/hwmon/f75375s.c #define TEMP_TO_REG(val) ((val) / 1000) val 607 drivers/hwmon/f75375s.c unsigned long val; val 610 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 614 drivers/hwmon/f75375s.c val = clamp_val(TEMP_TO_REG(val), 0, 127); val 616 drivers/hwmon/f75375s.c data->temp_high[nr] = val; val 628 drivers/hwmon/f75375s.c unsigned long val; val 631 drivers/hwmon/f75375s.c err = kstrtoul(buf, 10, &val); val 635 drivers/hwmon/f75375s.c val = clamp_val(TEMP_TO_REG(val), 0, 127); val 637 drivers/hwmon/f75375s.c data->temp_max_hyst[nr] = val; val 77 drivers/hwmon/fam15h_power.c u32 val, tdp_limit, running_avg_range; val 84 drivers/hwmon/fam15h_power.c REG_TDP_RUNNING_AVERAGE, &val); val 91 drivers/hwmon/fam15h_power.c running_avg_capture = val >> 4; val 94 drivers/hwmon/fam15h_power.c running_avg_capture = (val >> 4) & 0x3fffff; val 98 drivers/hwmon/fam15h_power.c running_avg_range = (val & 0xf) + 1; val 101 drivers/hwmon/fam15h_power.c REG_TDP_LIMIT3, &val); val 108 drivers/hwmon/fam15h_power.c tdp_limit = val >> 16; val 110 drivers/hwmon/fam15h_power.c tdp_limit = (val >> 16) & 0x1fff; val 335 drivers/hwmon/fam15h_power.c u32 val; val 338 drivers/hwmon/fam15h_power.c REG_NORTHBRIDGE_CAP, &val); val 339 drivers/hwmon/fam15h_power.c if ((val & BIT(29)) && ((val >> 30) & 3)) val 358 drivers/hwmon/fam15h_power.c u32 val; val 369 drivers/hwmon/fam15h_power.c REG_TDP_RUNNING_AVERAGE, &val); val 370 drivers/hwmon/fam15h_power.c if ((val & 0xf) != 0xe) val 373 drivers/hwmon/fam15h_power.c val &= ~0xf; val 374 drivers/hwmon/fam15h_power.c val |= 0x9; val 377 drivers/hwmon/fam15h_power.c REG_TDP_RUNNING_AVERAGE, val); val 393 drivers/hwmon/fam15h_power.c u32 val; val 397 drivers/hwmon/fam15h_power.c pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val); val 398 drivers/hwmon/fam15h_power.c data->base_tdp = val >> 16; val 399 drivers/hwmon/fam15h_power.c tmp = val & 0xffff; val 402 drivers/hwmon/fam15h_power.c REG_TDP_LIMIT3, &val); val 404 drivers/hwmon/fam15h_power.c data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f); val 337 drivers/hwmon/fschmd.c #define TEMP_FROM_REG(val) (((val) - 128) * 1000) val 408 drivers/hwmon/fschmd.c #define RPM_FROM_REG(val) ((val) * 60) val 511 drivers/hwmon/fschmd.c int val = data->fan_min[index]; val 514 drivers/hwmon/fschmd.c if (val || data->kind == fscsyl) val 515 drivers/hwmon/fschmd.c val = val / 2 + 128; val 517 drivers/hwmon/fschmd.c return sprintf(buf, "%d\n", val); val 714 drivers/hwmon/ftsteutates.c int val; val 717 drivers/hwmon/ftsteutates.c val = i2c_smbus_read_byte_data(client, FTS_DEVICE_REVISION_REG); val 718 drivers/hwmon/ftsteutates.c if (val < 0x2b) val 722 drivers/hwmon/ftsteutates.c val = i2c_smbus_read_byte_data(client, FTS_DEVICE_DETECT_REG_1); val 723 drivers/hwmon/ftsteutates.c if (val != 0x17) val 726 drivers/hwmon/ftsteutates.c val = i2c_smbus_read_byte_data(client, FTS_DEVICE_DETECT_REG_2); val 727 drivers/hwmon/ftsteutates.c if (val != 0x34) val 730 drivers/hwmon/ftsteutates.c val = i2c_smbus_read_byte_data(client, FTS_DEVICE_DETECT_REG_3); val 731 drivers/hwmon/ftsteutates.c if (val != 0x54) val 738 drivers/hwmon/ftsteutates.c val = i2c_smbus_read_byte_data(client, FTS_DEVICE_ID_REG); val 739 drivers/hwmon/ftsteutates.c if (val != 0x11) val 61 drivers/hwmon/g760a.c static inline unsigned int rpm_from_cnt(u8 val, u32 clk, u16 div) val 63 drivers/hwmon/g760a.c return ((val == 0x00) ? 0 : ((clk*30)/(val*div))); val 143 drivers/hwmon/g760a.c unsigned long val; val 145 drivers/hwmon/g760a.c if (kstrtoul(buf, 10, &val)) val 149 drivers/hwmon/g760a.c data->set_cnt = PWM_TO_CNT(clamp_val(val, 0, 255)); val 256 drivers/hwmon/g762.c static int do_set_clk_freq(struct device *dev, unsigned long val) val 260 drivers/hwmon/g762.c if (val > 0xffffff) val 262 drivers/hwmon/g762.c if (!val) val 263 drivers/hwmon/g762.c val = 32768; val 265 drivers/hwmon/g762.c data->clk_freq = val; val 271 drivers/hwmon/g762.c static int do_set_pwm_mode(struct device *dev, unsigned long val) val 280 drivers/hwmon/g762.c switch (val) { val 301 drivers/hwmon/g762.c static int do_set_fan_div(struct device *dev, unsigned long val) val 310 drivers/hwmon/g762.c switch (val) { val 341 drivers/hwmon/g762.c static int do_set_fan_gear_mode(struct device *dev, unsigned long val) val 350 drivers/hwmon/g762.c switch (val) { val 377 drivers/hwmon/g762.c static int do_set_fan_pulses(struct device *dev, unsigned long val) val 386 drivers/hwmon/g762.c switch (val) { val 407 drivers/hwmon/g762.c static int do_set_pwm_enable(struct device *dev, unsigned long val) val 416 drivers/hwmon/g762.c switch (val) { val 448 drivers/hwmon/g762.c static int do_set_pwm_polarity(struct device *dev, unsigned long val) val 457 drivers/hwmon/g762.c switch (val) { val 481 drivers/hwmon/g762.c static int do_set_pwm(struct device *dev, unsigned long val) val 487 drivers/hwmon/g762.c if (val > 255) val 491 drivers/hwmon/g762.c ret = i2c_smbus_write_byte_data(client, G762_REG_SET_OUT, val); val 502 drivers/hwmon/g762.c static int do_set_fan_target(struct device *dev, unsigned long val) val 511 drivers/hwmon/g762.c data->set_cnt = cnt_from_rpm(val, data->clk_freq, val 524 drivers/hwmon/g762.c static int do_set_fan_startv(struct device *dev, unsigned long val) val 533 drivers/hwmon/g762.c switch (val) { val 638 drivers/hwmon/g762.c unsigned long val)) val 765 drivers/hwmon/g762.c unsigned long val; val 768 drivers/hwmon/g762.c if (kstrtoul(buf, 10, &val)) val 771 drivers/hwmon/g762.c ret = do_set_pwm_mode(dev, val); val 796 drivers/hwmon/g762.c unsigned long val; val 799 drivers/hwmon/g762.c if (kstrtoul(buf, 10, &val)) val 802 drivers/hwmon/g762.c ret = do_set_fan_div(dev, val); val 828 drivers/hwmon/g762.c unsigned long val; val 831 drivers/hwmon/g762.c if (kstrtoul(buf, 10, &val)) val 834 drivers/hwmon/g762.c ret = do_set_fan_pulses(dev, val); val 871 drivers/hwmon/g762.c unsigned long val; val 874 drivers/hwmon/g762.c if (kstrtoul(buf, 10, &val)) val 877 drivers/hwmon/g762.c ret = do_set_pwm_enable(dev, val); val 903 drivers/hwmon/g762.c unsigned long val; val 906 drivers/hwmon/g762.c if (kstrtoul(buf, 10, &val)) val 909 drivers/hwmon/g762.c ret = do_set_pwm(dev, val); val 950 drivers/hwmon/g762.c unsigned long val; val 953 drivers/hwmon/g762.c if (kstrtoul(buf, 10, &val)) val 956 drivers/hwmon/g762.c ret = do_set_fan_target(dev, val); val 71 drivers/hwmon/gl518sm.c #define RAW_FROM_REG(val) val val 73 drivers/hwmon/gl518sm.c #define BOOL_FROM_REG(val) ((val) ? 0 : 1) val 74 drivers/hwmon/gl518sm.c #define BOOL_TO_REG(val) ((val) ? 0 : 1) val 76 drivers/hwmon/gl518sm.c #define TEMP_CLAMP(val) clamp_val(val, -119000, 136000) val 77 drivers/hwmon/gl518sm.c #define TEMP_TO_REG(val) (DIV_ROUND_CLOSEST(TEMP_CLAMP(val), 1000) + 119) val 78 drivers/hwmon/gl518sm.c #define TEMP_FROM_REG(val) (((val) - 119) * 1000) val 88 drivers/hwmon/gl518sm.c #define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : (480000 / ((val) * (div)))) val 90 drivers/hwmon/gl518sm.c #define IN_CLAMP(val) clamp_val(val, 0, 255 * 19) val 91 drivers/hwmon/gl518sm.c #define IN_TO_REG(val) DIV_ROUND_CLOSEST(IN_CLAMP(val), 19) val 92 drivers/hwmon/gl518sm.c #define IN_FROM_REG(val) ((val) * 19) val 94 drivers/hwmon/gl518sm.c #define VDD_CLAMP(val) clamp_val(val, 0, 255 * 95 / 4) val 95 drivers/hwmon/gl518sm.c #define VDD_TO_REG(val) DIV_ROUND_CLOSEST(VDD_CLAMP(val) * 4, 95) val 96 drivers/hwmon/gl518sm.c #define VDD_FROM_REG(val) DIV_ROUND_CLOSEST((val) * 95, 4) val 98 drivers/hwmon/gl518sm.c #define DIV_FROM_REG(val) (1 << (val)) val 100 drivers/hwmon/gl518sm.c #define BEEP_MASK_TO_REG(val) ((val) & 0x7f & data->alarm_mask) val 101 drivers/hwmon/gl518sm.c #define BEEP_MASK_FROM_REG(val) ((val) & 0x7f) val 154 drivers/hwmon/gl518sm.c int val; val 165 drivers/hwmon/gl518sm.c val = gl518_read_value(client, GL518_REG_VDD_LIMIT); val 166 drivers/hwmon/gl518sm.c data->voltage_min[0] = val & 0xff; val 167 drivers/hwmon/gl518sm.c data->voltage_max[0] = (val >> 8) & 0xff; val 168 drivers/hwmon/gl518sm.c val = gl518_read_value(client, GL518_REG_VIN1_LIMIT); val 169 drivers/hwmon/gl518sm.c data->voltage_min[1] = val & 0xff; val 170 drivers/hwmon/gl518sm.c data->voltage_max[1] = (val >> 8) & 0xff; val 171 drivers/hwmon/gl518sm.c val = gl518_read_value(client, GL518_REG_VIN2_LIMIT); val 172 drivers/hwmon/gl518sm.c data->voltage_min[2] = val & 0xff; val 173 drivers/hwmon/gl518sm.c data->voltage_max[2] = (val >> 8) & 0xff; val 174 drivers/hwmon/gl518sm.c val = gl518_read_value(client, GL518_REG_VIN3_LIMIT); val 175 drivers/hwmon/gl518sm.c data->voltage_min[3] = val & 0xff; val 176 drivers/hwmon/gl518sm.c data->voltage_max[3] = (val >> 8) & 0xff; val 178 drivers/hwmon/gl518sm.c val = gl518_read_value(client, GL518_REG_FAN_COUNT); val 179 drivers/hwmon/gl518sm.c data->fan_in[0] = (val >> 8) & 0xff; val 180 drivers/hwmon/gl518sm.c data->fan_in[1] = val & 0xff; val 182 drivers/hwmon/gl518sm.c val = gl518_read_value(client, GL518_REG_FAN_LIMIT); val 183 drivers/hwmon/gl518sm.c data->fan_min[0] = (val >> 8) & 0xff; val 184 drivers/hwmon/gl518sm.c data->fan_min[1] = val & 0xff; val 192 drivers/hwmon/gl518sm.c val = gl518_read_value(client, GL518_REG_MISC); val 193 drivers/hwmon/gl518sm.c data->fan_div[0] = (val >> 6) & 0x03; val 194 drivers/hwmon/gl518sm.c data->fan_div[1] = (val >> 4) & 0x03; val 195 drivers/hwmon/gl518sm.c data->fan_auto1 = (val >> 3) & 0x01; val 199 drivers/hwmon/gl518sm.c val = gl518_read_value(client, GL518_REG_CONF); val 200 drivers/hwmon/gl518sm.c data->beep_enable = (val >> 2) & 1; val 287 drivers/hwmon/gl518sm.c long val; \ val 288 drivers/hwmon/gl518sm.c int err = kstrtol(buf, 10, &val); \ val 293 drivers/hwmon/gl518sm.c data->value = type##_TO_REG(val); \ val 307 drivers/hwmon/gl518sm.c unsigned long val; \ val 308 drivers/hwmon/gl518sm.c int err = kstrtoul(buf, 10, &val); \ val 314 drivers/hwmon/gl518sm.c data->value = type##_TO_REG(val); \ val 348 drivers/hwmon/gl518sm.c unsigned long val; val 351 drivers/hwmon/gl518sm.c err = kstrtoul(buf, 10, &val); val 357 drivers/hwmon/gl518sm.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 382 drivers/hwmon/gl518sm.c unsigned long val; val 385 drivers/hwmon/gl518sm.c err = kstrtoul(buf, 10, &val); val 389 drivers/hwmon/gl518sm.c switch (val) { val 391 drivers/hwmon/gl518sm.c val = 0; val 394 drivers/hwmon/gl518sm.c val = 1; val 397 drivers/hwmon/gl518sm.c val = 2; val 400 drivers/hwmon/gl518sm.c val = 3; val 405 drivers/hwmon/gl518sm.c val); val 411 drivers/hwmon/gl518sm.c data->fan_div[nr] = val; val 113 drivers/hwmon/gl520sm.c int val, i; val 129 drivers/hwmon/gl520sm.c val = gl520_read_value(client, GL520_REG_IN_LIMIT[i]); val 130 drivers/hwmon/gl520sm.c data->in_min[i] = val & 0xff; val 131 drivers/hwmon/gl520sm.c data->in_max[i] = (val >> 8) & 0xff; val 134 drivers/hwmon/gl520sm.c val = gl520_read_value(client, GL520_REG_FAN_INPUT); val 135 drivers/hwmon/gl520sm.c data->fan_input[0] = (val >> 8) & 0xff; val 136 drivers/hwmon/gl520sm.c data->fan_input[1] = val & 0xff; val 138 drivers/hwmon/gl520sm.c val = gl520_read_value(client, GL520_REG_FAN_MIN); val 139 drivers/hwmon/gl520sm.c data->fan_min[0] = (val >> 8) & 0xff; val 140 drivers/hwmon/gl520sm.c data->fan_min[1] = val & 0xff; val 149 drivers/hwmon/gl520sm.c val = gl520_read_value(client, GL520_REG_FAN_DIV); val 150 drivers/hwmon/gl520sm.c data->fan_div[0] = (val >> 6) & 0x03; val 151 drivers/hwmon/gl520sm.c data->fan_div[1] = (val >> 4) & 0x03; val 152 drivers/hwmon/gl520sm.c data->fan_off = (val >> 2) & 0x01; val 156 drivers/hwmon/gl520sm.c val = gl520_read_value(client, GL520_REG_CONF); val 157 drivers/hwmon/gl520sm.c data->beep_enable = !((val >> 2) & 1); val 197 drivers/hwmon/gl520sm.c #define VDD_FROM_REG(val) DIV_ROUND_CLOSEST((val) * 95, 4) val 198 drivers/hwmon/gl520sm.c #define VDD_CLAMP(val) clamp_val(val, 0, 255 * 95 / 4) val 199 drivers/hwmon/gl520sm.c #define VDD_TO_REG(val) DIV_ROUND_CLOSEST(VDD_CLAMP(val) * 4, 95) val 201 drivers/hwmon/gl520sm.c #define IN_FROM_REG(val) ((val) * 19) val 202 drivers/hwmon/gl520sm.c #define IN_CLAMP(val) clamp_val(val, 0, 255 * 19) val 203 drivers/hwmon/gl520sm.c #define IN_TO_REG(val) DIV_ROUND_CLOSEST(IN_CLAMP(val), 19) val 328 drivers/hwmon/gl520sm.c #define DIV_FROM_REG(val) (1 << (val)) val 329 drivers/hwmon/gl520sm.c #define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : (480000 / ((val) << (div)))) val 332 drivers/hwmon/gl520sm.c #define FAN_CLAMP(val, div) clamp_val(val, FAN_BASE(div) / 255, \ val 334 drivers/hwmon/gl520sm.c #define FAN_TO_REG(val, div) ((val) == 0 ? 0 : \ val 336 drivers/hwmon/gl520sm.c FAN_CLAMP(val, div) << (div))) val 497 drivers/hwmon/gl520sm.c #define TEMP_FROM_REG(val) (((val) - 130) * 1000) val 498 drivers/hwmon/gl520sm.c #define TEMP_CLAMP(val) clamp_val(val, -130000, 125000) val 499 drivers/hwmon/gl520sm.c #define TEMP_TO_REG(val) (DIV_ROUND_CLOSEST(TEMP_CLAMP(val), 1000) + 130) val 214 drivers/hwmon/gpio-fan.c unsigned long val; val 216 drivers/hwmon/gpio-fan.c if (kstrtoul(buf, 10, &val) || val > 1) val 219 drivers/hwmon/gpio-fan.c if (fan_data->pwm_enable == val) val 224 drivers/hwmon/gpio-fan.c fan_data->pwm_enable = val; val 227 drivers/hwmon/gpio-fan.c if (val == 0) val 69 drivers/hwmon/hwmon-vid.c int vid_from_reg(int val, u8 vrm) val 77 drivers/hwmon/hwmon-vid.c val &= 0x3f; val 78 drivers/hwmon/hwmon-vid.c if ((val & 0x1f) == 0x1f) val 80 drivers/hwmon/hwmon-vid.c if ((val & 0x1f) <= 0x09 || val == 0x0a) val 81 drivers/hwmon/hwmon-vid.c vid = 1087500 - (val & 0x1f) * 25000; val 83 drivers/hwmon/hwmon-vid.c vid = 1862500 - (val & 0x1f) * 25000; val 84 drivers/hwmon/hwmon-vid.c if (val & 0x20) val 90 drivers/hwmon/hwmon-vid.c val &= 0xff; val 91 drivers/hwmon/hwmon-vid.c if (val < 0x02 || val > 0xb2) val 93 drivers/hwmon/hwmon-vid.c return (1600000 - (val - 2) * 6250 + 500) / 1000; val 96 drivers/hwmon/hwmon-vid.c val &= 0x1f; val 97 drivers/hwmon/hwmon-vid.c if (val == 0x1f) val 101 drivers/hwmon/hwmon-vid.c val &= 0x3f; val 102 drivers/hwmon/hwmon-vid.c return (val < 32) ? 1550 - 25 * val val 103 drivers/hwmon/hwmon-vid.c : 775 - (25 * (val - 31)) / 2; val 106 drivers/hwmon/hwmon-vid.c val &= 0x7f; val 107 drivers/hwmon/hwmon-vid.c if (val >= 0x7c) val 109 drivers/hwmon/hwmon-vid.c return DIV_ROUND_CLOSEST(15500 - 125 * val, 10); val 113 drivers/hwmon/hwmon-vid.c val &= 0x1f; val 114 drivers/hwmon/hwmon-vid.c return val == 0x1f ? 0 : val 115 drivers/hwmon/hwmon-vid.c 1850 - val * 25; val 118 drivers/hwmon/hwmon-vid.c val &= 0x1f; val 119 drivers/hwmon/hwmon-vid.c return (val & 0x10 ? 25 : 0) + val 120 drivers/hwmon/hwmon-vid.c ((val & 0x0f) > 0x04 ? 2050 : 1250) - val 121 drivers/hwmon/hwmon-vid.c ((val & 0x0f) * 50); val 124 drivers/hwmon/hwmon-vid.c val &= 0x0f; val 127 drivers/hwmon/hwmon-vid.c val &= 0x1f; val 128 drivers/hwmon/hwmon-vid.c return val == 0x1f ? 0 : val 129 drivers/hwmon/hwmon-vid.c val & 0x10 ? 5100 - (val) * 100 : val 130 drivers/hwmon/hwmon-vid.c 2050 - (val) * 50; val 132 drivers/hwmon/hwmon-vid.c val &= 0x1f; val 133 drivers/hwmon/hwmon-vid.c return val & 0x10 ? 975 - (val & 0xF) * 25 : val 134 drivers/hwmon/hwmon-vid.c 1750 - val * 50; val 137 drivers/hwmon/hwmon-vid.c val &= 0x3f; val 139 drivers/hwmon/hwmon-vid.c if (vrm == 131 && val == 0x3f) val 140 drivers/hwmon/hwmon-vid.c val++; val 141 drivers/hwmon/hwmon-vid.c return 1708 - val * 16; val 144 drivers/hwmon/hwmon-vid.c val &= 0x7f; val 145 drivers/hwmon/hwmon-vid.c return val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000; val 202 drivers/hwmon/hwmon.c long val; val 206 drivers/hwmon/hwmon.c &val); val 211 drivers/hwmon/hwmon.c hattr->name, val); val 213 drivers/hwmon/hwmon.c return sprintf(buf, "%ld\n", val); val 241 drivers/hwmon/hwmon.c long val; val 244 drivers/hwmon/hwmon.c ret = kstrtol(buf, 10, &val); val 249 drivers/hwmon/hwmon.c val); val 254 drivers/hwmon/hwmon.c hattr->name, val); val 121 drivers/hwmon/i5k_amb.c u8 val) val 123 drivers/hwmon/i5k_amb.c iowrite8(val, data->amb_mmio + offset); val 81 drivers/hwmon/ina209.c s32 val; val 89 drivers/hwmon/ina209.c val = i2c_smbus_read_word_swapped(client, i); val 90 drivers/hwmon/ina209.c if (val < 0) { val 91 drivers/hwmon/ina209.c ret = ERR_PTR(val); val 94 drivers/hwmon/ina209.c data->regs[i] = val; val 108 drivers/hwmon/ina209.c static long ina209_from_reg(const u8 reg, const u16 val) val 117 drivers/hwmon/ina209.c return DIV_ROUND_CLOSEST((s16)val, 100); val 127 drivers/hwmon/ina209.c return (val >> 3) * 4; val 131 drivers/hwmon/ina209.c return val >> 8; val 135 drivers/hwmon/ina209.c return -1 * (val >> 8); val 142 drivers/hwmon/ina209.c return val * 20 * 1000L; val 146 drivers/hwmon/ina209.c return (s16)val; val 158 drivers/hwmon/ina209.c static int ina209_to_reg(u8 reg, u16 old, long val) val 164 drivers/hwmon/ina209.c return clamp_val(val, -320, 320) * 100; val 176 drivers/hwmon/ina209.c return (DIV_ROUND_CLOSEST(clamp_val(val, 0, 32000), 4) << 3) val 187 drivers/hwmon/ina209.c return (clamp_val(-val, 0, 255) << 8) | (old & 0xff); val 196 drivers/hwmon/ina209.c return (clamp_val(val, 0, 255) << 8) | (old & 0xff); val 201 drivers/hwmon/ina209.c return DIV_ROUND_CLOSEST(val, 20 * 1000); val 235 drivers/hwmon/ina209.c long val; val 242 drivers/hwmon/ina209.c ret = kstrtol(buf, 10, &val); val 248 drivers/hwmon/ina209.c val); val 287 drivers/hwmon/ina209.c long val; val 290 drivers/hwmon/ina209.c ret = kstrtol(buf, 10, &val); val 312 drivers/hwmon/ina209.c long val; val 318 drivers/hwmon/ina209.c ret = kstrtol(buf, 10, &val); val 323 drivers/hwmon/ina209.c ret = ina209_to_reg(reg, data->regs[reg], val); val 340 drivers/hwmon/ina209.c long val; val 345 drivers/hwmon/ina209.c val = ina209_from_reg(attr->index, data->regs[attr->index]); val 346 drivers/hwmon/ina209.c return snprintf(buf, PAGE_SIZE, "%ld\n", val); val 75 drivers/hwmon/ina2xx.c #define INA226_SHIFT_AVG(val) ((val) << 9) val 257 drivers/hwmon/ina2xx.c int val; val 262 drivers/hwmon/ina2xx.c val = DIV_ROUND_CLOSEST((s16)regval, data->config->shunt_div); val 265 drivers/hwmon/ina2xx.c val = (regval >> data->config->bus_voltage_shift) val 267 drivers/hwmon/ina2xx.c val = DIV_ROUND_CLOSEST(val, 1000); val 270 drivers/hwmon/ina2xx.c val = regval * data->power_lsb_uW; val 274 drivers/hwmon/ina2xx.c val = (s16)regval * data->current_lsb_uA; val 275 drivers/hwmon/ina2xx.c val = DIV_ROUND_CLOSEST(val, 1000); val 278 drivers/hwmon/ina2xx.c val = regval; val 283 drivers/hwmon/ina2xx.c val = 0; val 287 drivers/hwmon/ina2xx.c return val; val 312 drivers/hwmon/ina2xx.c static int ina2xx_set_shunt(struct ina2xx_data *data, long val) val 316 drivers/hwmon/ina2xx.c if (val <= 0 || val > dividend) val 320 drivers/hwmon/ina2xx.c data->rshunt = val; val 321 drivers/hwmon/ina2xx.c data->current_lsb_uA = DIV_ROUND_CLOSEST(dividend, val); val 341 drivers/hwmon/ina2xx.c unsigned long val; val 345 drivers/hwmon/ina2xx.c status = kstrtoul(buf, 10, &val); val 349 drivers/hwmon/ina2xx.c status = ina2xx_set_shunt(data, val); val 360 drivers/hwmon/ina2xx.c unsigned long val; val 363 drivers/hwmon/ina2xx.c status = kstrtoul(buf, 10, &val); val 367 drivers/hwmon/ina2xx.c if (val > INT_MAX || val == 0) val 372 drivers/hwmon/ina2xx.c ina226_interval_to_reg(val)); val 440 drivers/hwmon/ina2xx.c u32 val; val 457 drivers/hwmon/ina2xx.c if (of_property_read_u32(dev->of_node, "shunt-resistor", &val) < 0) { val 461 drivers/hwmon/ina2xx.c val = pdata->shunt_uohms; val 463 drivers/hwmon/ina2xx.c val = INA2XX_RSHUNT_DEFAULT; val 466 drivers/hwmon/ina2xx.c ina2xx_set_shunt(data, val); val 177 drivers/hwmon/ina3221.c int *val) val 186 drivers/hwmon/ina3221.c *val = sign_extend32(regval >> 3, 12); val 200 drivers/hwmon/ina3221.c static int ina3221_read_chip(struct device *dev, u32 attr, long *val) val 208 drivers/hwmon/ina3221.c *val = ina3221_avg_samples[regval]; val 212 drivers/hwmon/ina3221.c *val = ina3221_reg_to_interval_us(ina->reg_config); val 213 drivers/hwmon/ina3221.c *val = DIV_ROUND_CLOSEST(*val, 1000); val 220 drivers/hwmon/ina3221.c static int ina3221_read_in(struct device *dev, u32 attr, int channel, long *val) val 252 drivers/hwmon/ina3221.c *val = regval * (is_shunt ? 40 : 8); val 255 drivers/hwmon/ina3221.c *val = ina3221_is_enabled(ina, channel); val 271 drivers/hwmon/ina3221.c int channel, long *val) val 303 drivers/hwmon/ina3221.c *val = DIV_ROUND_CLOSEST(voltage_nv, resistance_uo); val 310 drivers/hwmon/ina3221.c *val = 0; val 316 drivers/hwmon/ina3221.c *val = regval; val 323 drivers/hwmon/ina3221.c static int ina3221_write_chip(struct device *dev, u32 attr, long val) val 331 drivers/hwmon/ina3221.c idx = find_closest(val, ina3221_avg_samples, val 344 drivers/hwmon/ina3221.c tmp = ina3221_interval_ms_to_conv_time(ina->reg_config, val); val 366 drivers/hwmon/ina3221.c int channel, long val) val 375 drivers/hwmon/ina3221.c current_ma = clamp_val(val, val 439 drivers/hwmon/ina3221.c u32 attr, int channel, long *val) val 448 drivers/hwmon/ina3221.c ret = ina3221_read_chip(dev, attr, val); val 452 drivers/hwmon/ina3221.c ret = ina3221_read_in(dev, attr, channel - 1, val); val 455 drivers/hwmon/ina3221.c ret = ina3221_read_curr(dev, attr, channel, val); val 468 drivers/hwmon/ina3221.c u32 attr, int channel, long val) val 477 drivers/hwmon/ina3221.c ret = ina3221_write_chip(dev, attr, val); val 481 drivers/hwmon/ina3221.c ret = ina3221_write_enable(dev, channel - 1, val); val 484 drivers/hwmon/ina3221.c ret = ina3221_write_curr(dev, attr, channel, val); val 616 drivers/hwmon/ina3221.c int val; val 619 drivers/hwmon/ina3221.c ret = kstrtoint(buf, 0, &val); val 623 drivers/hwmon/ina3221.c val = clamp_val(val, 1, INT_MAX); val 625 drivers/hwmon/ina3221.c input->shunt_resistor = val; val 666 drivers/hwmon/ina3221.c u32 val; val 669 drivers/hwmon/ina3221.c ret = of_property_read_u32(child, "reg", &val); val 673 drivers/hwmon/ina3221.c } else if (val > INA3221_CHANNEL3) { val 674 drivers/hwmon/ina3221.c dev_err(dev, "invalid reg %d of %pOFn\n", val, child); val 678 drivers/hwmon/ina3221.c input = &ina->inputs[val]; val 690 drivers/hwmon/ina3221.c if (!of_property_read_u32(child, "shunt-resistor-micro-ohms", &val)) { val 691 drivers/hwmon/ina3221.c if (val < 1 || val > INT_MAX) { val 693 drivers/hwmon/ina3221.c val, child); val 696 drivers/hwmon/ina3221.c input->shunt_resistor = val; val 92 drivers/hwmon/it87.c static inline void superio_outb(int ioreg, int reg, int val) val 95 drivers/hwmon/it87.c outb(val, ioreg + 1); val 100 drivers/hwmon/it87.c int val; val 103 drivers/hwmon/it87.c val = inb(ioreg + 1) << 8; val 105 drivers/hwmon/it87.c val |= inb(ioreg + 1); val 106 drivers/hwmon/it87.c return val; val 581 drivers/hwmon/it87.c static u8 in_to_reg(const struct it87_data *data, int nr, long val) val 583 drivers/hwmon/it87.c val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); val 584 drivers/hwmon/it87.c return clamp_val(val, 0, 255); val 587 drivers/hwmon/it87.c static int in_from_reg(const struct it87_data *data, int nr, int val) val 589 drivers/hwmon/it87.c return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); val 607 drivers/hwmon/it87.c #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ val 608 drivers/hwmon/it87.c 1350000 / ((val) * (div))) val 610 drivers/hwmon/it87.c #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ val 611 drivers/hwmon/it87.c 1350000 / ((val) * 2)) val 613 drivers/hwmon/it87.c #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ val 614 drivers/hwmon/it87.c ((val) + 500) / 1000), -128, 127)) val 615 drivers/hwmon/it87.c #define TEMP_FROM_REG(val) ((val) * 1000) val 617 drivers/hwmon/it87.c static u8 pwm_to_reg(const struct it87_data *data, long val) val 620 drivers/hwmon/it87.c return val; val 622 drivers/hwmon/it87.c return val >> 1; val 633 drivers/hwmon/it87.c static int DIV_TO_REG(int val) val 637 drivers/hwmon/it87.c while (answer < 7 && (val >>= 1)) val 642 drivers/hwmon/it87.c #define DIV_FROM_REG(val) BIT(val) val 873 drivers/hwmon/it87.c unsigned long val; val 875 drivers/hwmon/it87.c if (kstrtoul(buf, 10, &val) < 0) val 879 drivers/hwmon/it87.c data->in[nr][index] = in_to_reg(data, nr, val); val 961 drivers/hwmon/it87.c long val; val 964 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0) val 988 drivers/hwmon/it87.c data->temp[nr][index] = TEMP_TO_REG(val); val 1045 drivers/hwmon/it87.c long val; val 1048 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0) val 1054 drivers/hwmon/it87.c if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) val 1057 drivers/hwmon/it87.c if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) val 1059 drivers/hwmon/it87.c if (val == 2) { /* backwards compatibility */ val 1062 drivers/hwmon/it87.c val = 4; val 1065 drivers/hwmon/it87.c if (val == 3) val 1067 drivers/hwmon/it87.c else if (val == 4) val 1069 drivers/hwmon/it87.c else if (has_temp_peci(data, nr) && val == 6) val 1071 drivers/hwmon/it87.c else if (has_temp_old_peci(data, nr) && val == 6) val 1073 drivers/hwmon/it87.c else if (val != 0) val 1183 drivers/hwmon/it87.c long val; val 1186 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0) val 1192 drivers/hwmon/it87.c data->fan[nr][index] = FAN16_TO_REG(val); val 1211 drivers/hwmon/it87.c FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 1226 drivers/hwmon/it87.c unsigned long val; val 1230 drivers/hwmon/it87.c if (kstrtoul(buf, 10, &val) < 0) val 1242 drivers/hwmon/it87.c data->fan_div[nr] = DIV_TO_REG(val); val 1245 drivers/hwmon/it87.c if (val < 8) val 1250 drivers/hwmon/it87.c val = old & 0x80; val 1251 drivers/hwmon/it87.c val |= (data->fan_div[0] & 0x07); val 1252 drivers/hwmon/it87.c val |= (data->fan_div[1] & 0x07) << 3; val 1254 drivers/hwmon/it87.c val |= 0x1 << 6; val 1255 drivers/hwmon/it87.c it87_write_value(data, IT87_REG_FAN_DIV, val); val 1301 drivers/hwmon/it87.c long val; val 1303 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) val 1307 drivers/hwmon/it87.c if (val == 2) { val 1314 drivers/hwmon/it87.c if (val == 0) { val 1347 drivers/hwmon/it87.c if (val != 1) val 1350 drivers/hwmon/it87.c ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80); val 1373 drivers/hwmon/it87.c long val; val 1375 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) val 1389 drivers/hwmon/it87.c data->pwm_duty[nr] = pwm_to_reg(data, val); val 1393 drivers/hwmon/it87.c data->pwm_duty[nr] = pwm_to_reg(data, val); val 1414 drivers/hwmon/it87.c unsigned long val; val 1417 drivers/hwmon/it87.c if (kstrtoul(buf, 10, &val) < 0) val 1420 drivers/hwmon/it87.c val = clamp_val(val, 0, 1000000); val 1421 drivers/hwmon/it87.c val *= has_newer_autopwm(data) ? 256 : 128; val 1425 drivers/hwmon/it87.c if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) val 1468 drivers/hwmon/it87.c long val; val 1471 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0) val 1475 drivers/hwmon/it87.c val -= 3; val 1477 drivers/hwmon/it87.c switch (val) { val 1529 drivers/hwmon/it87.c long val; val 1531 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) val 1535 drivers/hwmon/it87.c data->auto_pwm[nr][point] = pwm_to_reg(data, val); val 1562 drivers/hwmon/it87.c unsigned long val; val 1564 drivers/hwmon/it87.c if (kstrtoul(buf, 10, &val) < 0 || val > 127) val 1568 drivers/hwmon/it87.c data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; val 1601 drivers/hwmon/it87.c long val; val 1604 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) val 1609 drivers/hwmon/it87.c reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); val 1614 drivers/hwmon/it87.c reg = TEMP_TO_REG(val); val 1824 drivers/hwmon/it87.c long val; val 1826 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0 || val != 0) val 1878 drivers/hwmon/it87.c long val; val 1880 drivers/hwmon/it87.c if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) val 1885 drivers/hwmon/it87.c if (val) val 1927 drivers/hwmon/it87.c unsigned long val; val 1929 drivers/hwmon/it87.c if (kstrtoul(buf, 10, &val) < 0) val 1932 drivers/hwmon/it87.c data->vrm = val; val 246 drivers/hwmon/jc42.c int i, val; val 252 drivers/hwmon/jc42.c val = i2c_smbus_read_word_swapped(client, temp_regs[i]); val 253 drivers/hwmon/jc42.c if (val < 0) { val 254 drivers/hwmon/jc42.c ret = ERR_PTR(val); val 257 drivers/hwmon/jc42.c data->temp[i] = val; val 268 drivers/hwmon/jc42.c u32 attr, int channel, long *val) val 278 drivers/hwmon/jc42.c *val = jc42_temp_from_reg(data->temp[t_input]); val 281 drivers/hwmon/jc42.c *val = jc42_temp_from_reg(data->temp[t_min]); val 284 drivers/hwmon/jc42.c *val = jc42_temp_from_reg(data->temp[t_max]); val 287 drivers/hwmon/jc42.c *val = jc42_temp_from_reg(data->temp[t_crit]); val 293 drivers/hwmon/jc42.c *val = temp - hyst; val 299 drivers/hwmon/jc42.c *val = temp - hyst; val 302 drivers/hwmon/jc42.c *val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1; val 305 drivers/hwmon/jc42.c *val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1; val 308 drivers/hwmon/jc42.c *val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1; val 316 drivers/hwmon/jc42.c u32 attr, int channel, long val) val 327 drivers/hwmon/jc42.c data->temp[t_min] = jc42_temp_to_reg(val, data->extended); val 332 drivers/hwmon/jc42.c data->temp[t_max] = jc42_temp_to_reg(val, data->extended); val 337 drivers/hwmon/jc42.c data->temp[t_crit] = jc42_temp_to_reg(val, data->extended); val 346 drivers/hwmon/jc42.c val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED val 349 drivers/hwmon/jc42.c diff = jc42_temp_from_reg(data->temp[t_crit]) - val; val 98 drivers/hwmon/k10temp.c unsigned int base, int offset, u32 *val) val 104 drivers/hwmon/k10temp.c base + 4, val); val 19 drivers/hwmon/k8temp.c #define TEMP_FROM_REG(val) (((((val) >> 16) & 0xff) - 49) * 1000) val 87 drivers/hwmon/k8temp.c u32 attr, int channel, long *val) val 111 drivers/hwmon/k8temp.c *val = TEMP_FROM_REG(temp) + data->temp_offset; val 203 drivers/hwmon/lineage-pem.c long val; val 207 drivers/hwmon/lineage-pem.c val = (data[index] + (data[index+1] << 8)) * 5 / 2; val 210 drivers/hwmon/lineage-pem.c val = data[index] * 200; val 213 drivers/hwmon/lineage-pem.c val = data[index] * 1000; val 216 drivers/hwmon/lineage-pem.c val = 97 * 1000; /* 97 degrees C per datasheet */ val 219 drivers/hwmon/lineage-pem.c val = 107 * 1000; /* 107 degrees C per datasheet */ val 223 drivers/hwmon/lineage-pem.c val = 0; val 225 drivers/hwmon/lineage-pem.c return val; val 230 drivers/hwmon/lineage-pem.c long val; val 235 drivers/hwmon/lineage-pem.c val = (data[index] + (data[index+1] << 8) - 75) * 1000; val 237 drivers/hwmon/lineage-pem.c val = (data[index] - 75) * 1000; val 242 drivers/hwmon/lineage-pem.c val = (data[index] + (data[index+1] << 8)) * 1000000L; val 246 drivers/hwmon/lineage-pem.c val = 0; val 248 drivers/hwmon/lineage-pem.c return val; val 253 drivers/hwmon/lineage-pem.c long val; val 259 drivers/hwmon/lineage-pem.c val = data[index] * 100; val 263 drivers/hwmon/lineage-pem.c val = 0; val 265 drivers/hwmon/lineage-pem.c return val; val 114 drivers/hwmon/lm63.c #define FAN_TO_REG(val) ((val) <= 82 ? 0xFFFC : \ val 115 drivers/hwmon/lm63.c (5400000 / (val)) & 0xFFFC) val 117 drivers/hwmon/lm63.c #define TEMP8_TO_REG(val) DIV_ROUND_CLOSEST(clamp_val((val), -128000, \ val 119 drivers/hwmon/lm63.c #define TEMP8U_TO_REG(val) DIV_ROUND_CLOSEST(clamp_val((val), 0, \ val 122 drivers/hwmon/lm63.c #define TEMP11_TO_REG(val) (DIV_ROUND_CLOSEST(clamp_val((val), -128000, \ val 124 drivers/hwmon/lm63.c #define TEMP11U_TO_REG(val) (DIV_ROUND_CLOSEST(clamp_val((val), 0, \ val 126 drivers/hwmon/lm63.c #define HYST_TO_REG(val) DIV_ROUND_CLOSEST(clamp_val((val), 0, 127000), \ val 190 drivers/hwmon/lm63.c static inline int lut_temp_to_reg(struct lm63_data *data, long val) val 192 drivers/hwmon/lm63.c val -= data->temp2_offset; val 194 drivers/hwmon/lm63.c return DIV_ROUND_CLOSEST(clamp_val(val, 0, 127500), 500); val 196 drivers/hwmon/lm63.c return DIV_ROUND_CLOSEST(clamp_val(val, 0, 127000), 1000); val 344 drivers/hwmon/lm63.c unsigned long val; val 347 drivers/hwmon/lm63.c err = kstrtoul(buf, 10, &val); val 352 drivers/hwmon/lm63.c data->fan[1] = FAN_TO_REG(val); val 386 drivers/hwmon/lm63.c unsigned long val; val 393 drivers/hwmon/lm63.c err = kstrtoul(buf, 10, &val); val 398 drivers/hwmon/lm63.c val = clamp_val(val, 0, 255); val 401 drivers/hwmon/lm63.c data->pwm1[nr] = data->pwm_highres ? val : val 402 drivers/hwmon/lm63.c (val * data->pwm1_freq * 2 + 127) / 255; val 421 drivers/hwmon/lm63.c unsigned long val; val 424 drivers/hwmon/lm63.c err = kstrtoul(buf, 10, &val); val 427 drivers/hwmon/lm63.c if (val < 1 || val > 2) val 434 drivers/hwmon/lm63.c if (val == 2 && lm63_lut_looks_bad(dev, data)) val 440 drivers/hwmon/lm63.c if (val == 1) val 492 drivers/hwmon/lm63.c long val; val 497 drivers/hwmon/lm63.c err = kstrtol(buf, 10, &val); val 506 drivers/hwmon/lm63.c temp = TEMP8U_TO_REG(val - data->temp2_offset); val 508 drivers/hwmon/lm63.c temp = TEMP8_TO_REG(val - data->temp2_offset); val 512 drivers/hwmon/lm63.c temp = TEMP8_TO_REG(val); val 516 drivers/hwmon/lm63.c temp = lut_temp_to_reg(data, val); val 565 drivers/hwmon/lm63.c long val; val 569 drivers/hwmon/lm63.c err = kstrtol(buf, 10, &val); val 575 drivers/hwmon/lm63.c data->temp11[nr] = TEMP11U_TO_REG(val - data->temp2_offset); val 577 drivers/hwmon/lm63.c data->temp11[nr] = TEMP11_TO_REG(val - data->temp2_offset); val 621 drivers/hwmon/lm63.c long val; val 625 drivers/hwmon/lm63.c err = kstrtol(buf, 10, &val); val 630 drivers/hwmon/lm63.c hyst = temp8_from_reg(data, 2) + data->temp2_offset - val; val 674 drivers/hwmon/lm63.c unsigned long val; val 677 drivers/hwmon/lm63.c err = kstrtoul(buf, 10, &val); val 682 drivers/hwmon/lm63.c lm63_set_convrate(data, clamp_val(val, 0, 100000)); val 702 drivers/hwmon/lm63.c unsigned long val; val 706 drivers/hwmon/lm63.c ret = kstrtoul(buf, 10, &val); val 709 drivers/hwmon/lm63.c if (val != 1 && val != 2) val 713 drivers/hwmon/lm63.c data->trutherm = val == 1; val 50 drivers/hwmon/lm70.c int status, val = 0; val 93 drivers/hwmon/lm70.c val = ((int)raw / 32) * 250; val 99 drivers/hwmon/lm70.c val = ((int)raw / 8) * 625 / 10; val 103 drivers/hwmon/lm70.c val = ((int)raw / 4) * 3125 / 100; val 107 drivers/hwmon/lm70.c status = sprintf(buf, "%d\n", val); /* millidegrees Celsius */ val 324 drivers/hwmon/lm75.c u32 attr, int channel, long *val) val 334 drivers/hwmon/lm75.c *val = data->sample_time; val 358 drivers/hwmon/lm75.c *val = lm75_reg_to_mc(regval, data->resolution); val 399 drivers/hwmon/lm75.c static int lm75_update_interval(struct device *dev, long val) val 406 drivers/hwmon/lm75.c index = find_closest(val, data->params->sample_times, val 442 drivers/hwmon/lm75.c static int lm75_write_chip(struct device *dev, u32 attr, long val) val 446 drivers/hwmon/lm75.c return lm75_update_interval(dev, val); val 454 drivers/hwmon/lm75.c u32 attr, int channel, long val) val 458 drivers/hwmon/lm75.c return lm75_write_chip(dev, attr, val); val 460 drivers/hwmon/lm75.c return lm75_write_temp(dev, attr, val); val 162 drivers/hwmon/lm77.c long val; val 165 drivers/hwmon/lm77.c err = kstrtol(buf, 10, &val); val 169 drivers/hwmon/lm77.c val = clamp_val(val, LM77_TEMP_MIN, LM77_TEMP_MAX); val 171 drivers/hwmon/lm77.c data->temp[nr] = val; val 172 drivers/hwmon/lm77.c lm77_write_value(client, temp_regs[nr], LM77_TEMP_TO_REG(val)); val 187 drivers/hwmon/lm77.c long val; val 190 drivers/hwmon/lm77.c err = kstrtol(buf, 10, &val); val 195 drivers/hwmon/lm77.c val = clamp_val(data->temp[t_crit] - val, LM77_TEMP_MIN, LM77_TEMP_MAX); val 196 drivers/hwmon/lm77.c data->temp[t_hyst] = val; val 72 drivers/hwmon/lm78.c static inline u8 IN_TO_REG(unsigned long val) val 74 drivers/hwmon/lm78.c unsigned long nval = clamp_val(val, 0, 4080); val 77 drivers/hwmon/lm78.c #define IN_FROM_REG(val) ((val) * 16) val 88 drivers/hwmon/lm78.c static inline int FAN_FROM_REG(u8 val, int div) val 90 drivers/hwmon/lm78.c return val == 0 ? -1 : val == 255 ? 0 : 1350000 / (val * div); val 97 drivers/hwmon/lm78.c static inline s8 TEMP_TO_REG(long val) val 99 drivers/hwmon/lm78.c int nval = clamp_val(val, -128000, 127000) ; val 103 drivers/hwmon/lm78.c static inline int TEMP_FROM_REG(s8 val) val 105 drivers/hwmon/lm78.c return val * 1000; val 108 drivers/hwmon/lm78.c #define DIV_FROM_REG(val) (1 << (val)) val 172 drivers/hwmon/lm78.c unsigned long val; val 175 drivers/hwmon/lm78.c err = kstrtoul(buf, 10, &val); val 180 drivers/hwmon/lm78.c data->in_min[nr] = IN_TO_REG(val); val 192 drivers/hwmon/lm78.c unsigned long val; val 195 drivers/hwmon/lm78.c err = kstrtoul(buf, 10, &val); val 200 drivers/hwmon/lm78.c data->in_max[nr] = IN_TO_REG(val); val 248 drivers/hwmon/lm78.c long val; val 251 drivers/hwmon/lm78.c err = kstrtol(buf, 10, &val); val 256 drivers/hwmon/lm78.c data->temp_over = TEMP_TO_REG(val); val 274 drivers/hwmon/lm78.c long val; val 277 drivers/hwmon/lm78.c err = kstrtol(buf, 10, &val); val 282 drivers/hwmon/lm78.c data->temp_hyst = TEMP_TO_REG(val); val 319 drivers/hwmon/lm78.c unsigned long val; val 322 drivers/hwmon/lm78.c err = kstrtoul(buf, 10, &val); val 327 drivers/hwmon/lm78.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 355 drivers/hwmon/lm78.c unsigned long val; val 358 drivers/hwmon/lm78.c err = kstrtoul(buf, 10, &val); val 366 drivers/hwmon/lm78.c switch (val) { val 382 drivers/hwmon/lm78.c val); val 832 drivers/hwmon/lm78.c int val, save, found = 0; val 852 drivers/hwmon/lm78.c val = inb_p(address + 1); val 853 drivers/hwmon/lm78.c if (inb_p(address + 2) != val val 854 drivers/hwmon/lm78.c || inb_p(address + 3) != val val 855 drivers/hwmon/lm78.c || inb_p(address + 7) != val) val 866 drivers/hwmon/lm78.c val = ~save & 0x7f; val 867 drivers/hwmon/lm78.c outb_p(val, address + LM78_ADDR_REG_OFFSET); val 868 drivers/hwmon/lm78.c if (inb_p(address + LM78_ADDR_REG_OFFSET) != (val | 0x80)) { val 875 drivers/hwmon/lm78.c val = inb_p(address + LM78_DATA_REG_OFFSET); val 876 drivers/hwmon/lm78.c if (val & 0x80) val 879 drivers/hwmon/lm78.c val = inb_p(address + LM78_DATA_REG_OFFSET); val 880 drivers/hwmon/lm78.c if (val < 0x03 || val > 0x77) /* Not a valid I2C address */ val 889 drivers/hwmon/lm78.c val = inb_p(address + LM78_DATA_REG_OFFSET); val 890 drivers/hwmon/lm78.c if (val == 0xa3 || val == 0x5c) val 895 drivers/hwmon/lm78.c val = inb_p(address + LM78_DATA_REG_OFFSET); val 896 drivers/hwmon/lm78.c if (val == 0x90) val 901 drivers/hwmon/lm78.c val = inb_p(address + LM78_DATA_REG_OFFSET); val 902 drivers/hwmon/lm78.c if (val == 0x00 || val == 0x20 /* LM78 */ val 903 drivers/hwmon/lm78.c || val == 0x40 /* LM78-J */ val 904 drivers/hwmon/lm78.c || (val & 0xfe) == 0xc0) /* LM79 */ val 909 drivers/hwmon/lm78.c val & 0x80 ? "LM79" : "LM78", (int)address); val 62 drivers/hwmon/lm80.c #define IN_TO_REG(val) (clamp_val(((val) + 5) / 10, 0, 255)) val 63 drivers/hwmon/lm80.c #define IN_FROM_REG(val) ((val) * 10) val 73 drivers/hwmon/lm80.c #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : \ val 74 drivers/hwmon/lm80.c (val) == 255 ? 0 : 1350000/((div) * (val))) val 80 drivers/hwmon/lm80.c #define DIV_FROM_REG(val) (1 << (val)) val 278 drivers/hwmon/lm80.c long val; val 280 drivers/hwmon/lm80.c int err = kstrtol(buf, 10, &val); val 287 drivers/hwmon/lm80.c data->in[nr][index] = IN_TO_REG(val); val 322 drivers/hwmon/lm80.c unsigned long val; val 323 drivers/hwmon/lm80.c int err = kstrtoul(buf, 10, &val); val 328 drivers/hwmon/lm80.c data->fan[nr][index] = FAN_TO_REG(val, val 349 drivers/hwmon/lm80.c unsigned long min, val; val 353 drivers/hwmon/lm80.c rv = kstrtoul(buf, 10, &val); val 362 drivers/hwmon/lm80.c switch (val) { val 378 drivers/hwmon/lm80.c val); val 419 drivers/hwmon/lm80.c long val; val 420 drivers/hwmon/lm80.c int err = kstrtol(buf, 10, &val); val 425 drivers/hwmon/lm80.c data->temp[nr] = TEMP_TO_REG(val); val 74 drivers/hwmon/lm83.c #define TEMP_FROM_REG(val) ((val) * 1000) val 75 drivers/hwmon/lm83.c #define TEMP_TO_REG(val) ((val) <= -128000 ? -128 : \ val 76 drivers/hwmon/lm83.c (val) >= 127000 ? 127 : \ val 77 drivers/hwmon/lm83.c (val) < 0 ? ((val) - 500) / 1000 : \ val 78 drivers/hwmon/lm83.c ((val) + 500) / 1000) val 167 drivers/hwmon/lm83.c long val; val 171 drivers/hwmon/lm83.c err = kstrtol(buf, 10, &val); val 176 drivers/hwmon/lm83.c data->temp[nr] = TEMP_TO_REG(val); val 124 drivers/hwmon/lm85.c #define SCALE(val, from, to) (((val) * (to) + ((from) / 2)) / (from)) val 126 drivers/hwmon/lm85.c #define INS_TO_REG(n, val) \ val 127 drivers/hwmon/lm85.c SCALE(clamp_val(val, 0, 255 * lm85_scaling[n] / 192), \ val 130 drivers/hwmon/lm85.c #define INSEXT_FROM_REG(n, val, ext) \ val 131 drivers/hwmon/lm85.c SCALE(((val) << 4) + (ext), 192 << 4, lm85_scaling[n]) val 133 drivers/hwmon/lm85.c #define INS_FROM_REG(n, val) SCALE((val), 192, lm85_scaling[n]) val 136 drivers/hwmon/lm85.c static inline u16 FAN_TO_REG(unsigned long val) val 138 drivers/hwmon/lm85.c if (!val) val 140 drivers/hwmon/lm85.c return clamp_val(5400000 / val, 1, 0xfffe); val 142 drivers/hwmon/lm85.c #define FAN_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ val 143 drivers/hwmon/lm85.c 5400000 / (val)) val 146 drivers/hwmon/lm85.c #define TEMP_TO_REG(val) \ val 147 drivers/hwmon/lm85.c DIV_ROUND_CLOSEST(clamp_val((val), -127000, 127000), 1000) val 148 drivers/hwmon/lm85.c #define TEMPEXT_FROM_REG(val, ext) \ val 149 drivers/hwmon/lm85.c SCALE(((val) << 4) + (ext), 16, 1000) val 150 drivers/hwmon/lm85.c #define TEMP_FROM_REG(val) ((val) * 1000) val 152 drivers/hwmon/lm85.c #define PWM_TO_REG(val) clamp_val(val, 0, 255) val 153 drivers/hwmon/lm85.c #define PWM_FROM_REG(val) (val) val 184 drivers/hwmon/lm85.c #define RANGE_FROM_REG(val) lm85_range_map[(val) & 0x0f] val 225 drivers/hwmon/lm85.c #define ZONE_FROM_REG(val) lm85_zone_map[(val) >> 5] val 239 drivers/hwmon/lm85.c #define HYST_TO_REG(val) clamp_val(((val) + 500) / 1000, 0, 15) val 240 drivers/hwmon/lm85.c #define HYST_FROM_REG(val) ((val) * 1000) val 393 drivers/hwmon/lm85.c int val = (ext1 << 8) + ext2; val 397 drivers/hwmon/lm85.c ((val >> (i * 2)) & 0x03) << 2; val 401 drivers/hwmon/lm85.c (val >> ((i + 4) * 2)) & 0x0c; val 500 drivers/hwmon/lm85.c int val; val 509 drivers/hwmon/lm85.c val = lm85_read_value(client, LM85_REG_AFAN_RANGE(i)); val 510 drivers/hwmon/lm85.c data->pwm_freq[i] = val % data->freq_map_size; val 511 drivers/hwmon/lm85.c data->zone[i].range = val >> 4; val 575 drivers/hwmon/lm85.c unsigned long val; val 578 drivers/hwmon/lm85.c err = kstrtoul(buf, 10, &val); val 583 drivers/hwmon/lm85.c data->fan_min[nr] = FAN_TO_REG(val); val 630 drivers/hwmon/lm85.c unsigned long val; val 633 drivers/hwmon/lm85.c err = kstrtoul(buf, 10, &val); val 637 drivers/hwmon/lm85.c if (val > 255) val 640 drivers/hwmon/lm85.c data->vrm = val; val 697 drivers/hwmon/lm85.c unsigned long val; val 700 drivers/hwmon/lm85.c err = kstrtoul(buf, 10, &val); val 705 drivers/hwmon/lm85.c data->pwm[nr] = PWM_TO_REG(val); val 741 drivers/hwmon/lm85.c unsigned long val; val 744 drivers/hwmon/lm85.c err = kstrtoul(buf, 10, &val); val 748 drivers/hwmon/lm85.c switch (val) { val 800 drivers/hwmon/lm85.c unsigned long val; val 803 drivers/hwmon/lm85.c err = kstrtoul(buf, 10, &val); val 813 drivers/hwmon/lm85.c if (data->type == adt7468 && val >= 11300) { /* High freq. mode */ val 818 drivers/hwmon/lm85.c data->freq_map_size, val); val 866 drivers/hwmon/lm85.c long val; val 869 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 874 drivers/hwmon/lm85.c data->in_min[nr] = INS_TO_REG(nr, val); val 894 drivers/hwmon/lm85.c long val; val 897 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 902 drivers/hwmon/lm85.c data->in_max[nr] = INS_TO_REG(nr, val); val 959 drivers/hwmon/lm85.c long val; val 962 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 967 drivers/hwmon/lm85.c val += 64; val 970 drivers/hwmon/lm85.c data->temp_min[nr] = TEMP_TO_REG(val); val 991 drivers/hwmon/lm85.c long val; val 994 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 999 drivers/hwmon/lm85.c val += 64; val 1002 drivers/hwmon/lm85.c data->temp_max[nr] = TEMP_TO_REG(val); val 1036 drivers/hwmon/lm85.c long val; val 1039 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 1045 drivers/hwmon/lm85.c | ZONE_TO_REG(val); val 1067 drivers/hwmon/lm85.c unsigned long val; val 1070 drivers/hwmon/lm85.c err = kstrtoul(buf, 10, &val); val 1075 drivers/hwmon/lm85.c data->autofan[nr].min_pwm = PWM_TO_REG(val); val 1099 drivers/hwmon/lm85.c long val; val 1102 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 1107 drivers/hwmon/lm85.c data->autofan[nr].min_off = val; val 1147 drivers/hwmon/lm85.c long val; val 1150 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 1156 drivers/hwmon/lm85.c data->zone[nr].hyst = HYST_TO_REG(min - val); val 1185 drivers/hwmon/lm85.c long val; val 1188 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 1193 drivers/hwmon/lm85.c data->zone[nr].limit = TEMP_TO_REG(val); val 1227 drivers/hwmon/lm85.c long val; val 1230 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 1236 drivers/hwmon/lm85.c data->zone[nr].max_desired = TEMP_TO_REG(val); val 1238 drivers/hwmon/lm85.c val - min); val 1262 drivers/hwmon/lm85.c long val; val 1265 drivers/hwmon/lm85.c err = kstrtol(buf, 10, &val); val 1270 drivers/hwmon/lm85.c data->zone[nr].critical = TEMP_TO_REG(val); val 109 drivers/hwmon/lm87.c #define IN_TO_REG(val, scale) ((val) <= 0 ? 0 : \ val 110 drivers/hwmon/lm87.c (val) >= (scale) * 255 / 192 ? 255 : \ val 111 drivers/hwmon/lm87.c ((val) * 192 + (scale) / 2) / (scale)) val 114 drivers/hwmon/lm87.c #define TEMP_TO_REG(val) ((val) <= -127500 ? -128 : \ val 115 drivers/hwmon/lm87.c (val) >= 126500 ? 127 : \ val 116 drivers/hwmon/lm87.c (((val) < 0 ? (val) - 500 : \ val 117 drivers/hwmon/lm87.c (val) + 500) / 1000)) val 121 drivers/hwmon/lm87.c #define FAN_TO_REG(val, div) ((val) * (div) * 255 <= 1350000 ? 255 : \ val 122 drivers/hwmon/lm87.c (1350000 + (val)*(div) / 2) / ((val) * (div))) val 128 drivers/hwmon/lm87.c #define AOUT_TO_REG(val) ((val) <= 0 ? 0 : \ val 129 drivers/hwmon/lm87.c (val) >= 2500 ? 255 : \ val 130 drivers/hwmon/lm87.c ((val) * 10 + 49) / 98) val 302 drivers/hwmon/lm87.c long val; val 305 drivers/hwmon/lm87.c err = kstrtol(buf, 10, &val); val 310 drivers/hwmon/lm87.c data->in_min[nr] = IN_TO_REG(val, data->in_scale[nr]); val 323 drivers/hwmon/lm87.c long val; val 326 drivers/hwmon/lm87.c err = kstrtol(buf, 10, &val); val 331 drivers/hwmon/lm87.c data->in_max[nr] = IN_TO_REG(val, data->in_scale[nr]); val 399 drivers/hwmon/lm87.c long val; val 402 drivers/hwmon/lm87.c err = kstrtol(buf, 10, &val); val 407 drivers/hwmon/lm87.c data->temp_low[nr] = TEMP_TO_REG(val); val 420 drivers/hwmon/lm87.c long val; val 423 drivers/hwmon/lm87.c err = kstrtol(buf, 10, &val); val 428 drivers/hwmon/lm87.c data->temp_high[nr] = TEMP_TO_REG(val); val 499 drivers/hwmon/lm87.c long val; val 502 drivers/hwmon/lm87.c err = kstrtol(buf, 10, &val); val 507 drivers/hwmon/lm87.c data->fan_min[nr] = FAN_TO_REG(val, val 527 drivers/hwmon/lm87.c long val; val 532 drivers/hwmon/lm87.c err = kstrtol(buf, 10, &val); val 540 drivers/hwmon/lm87.c switch (val) { val 569 drivers/hwmon/lm87.c data->fan_min[nr] = FAN_TO_REG(min, val); val 610 drivers/hwmon/lm87.c unsigned long val; val 613 drivers/hwmon/lm87.c err = kstrtoul(buf, 10, &val); val 617 drivers/hwmon/lm87.c if (val > 255) val 620 drivers/hwmon/lm87.c data->vrm = val; val 637 drivers/hwmon/lm87.c long val; val 640 drivers/hwmon/lm87.c err = kstrtol(buf, 10, &val); val 645 drivers/hwmon/lm87.c data->aout = AOUT_TO_REG(val); val 854 drivers/hwmon/lm87.c u8 val = 0; val 859 drivers/hwmon/lm87.c val |= CHAN_TEMP3; val 861 drivers/hwmon/lm87.c val |= CHAN_NO_FAN(0); val 863 drivers/hwmon/lm87.c val |= CHAN_NO_FAN(1); val 867 drivers/hwmon/lm87.c val |= CHAN_VCC_5V; val 869 drivers/hwmon/lm87.c data->channel = val; val 583 drivers/hwmon/lm90.c static int lm90_write_convrate(struct lm90_data *data, int val) val 596 drivers/hwmon/lm90.c err = i2c_smbus_write_byte_data(data->client, LM90_REG_W_CONVRATE, val); val 633 drivers/hwmon/lm90.c int val; val 635 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_LOCAL_CRIT); val 636 drivers/hwmon/lm90.c if (val < 0) val 637 drivers/hwmon/lm90.c return val; val 638 drivers/hwmon/lm90.c data->temp8[LOCAL_CRIT] = val; val 640 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_REMOTE_CRIT); val 641 drivers/hwmon/lm90.c if (val < 0) val 642 drivers/hwmon/lm90.c return val; val 643 drivers/hwmon/lm90.c data->temp8[REMOTE_CRIT] = val; val 645 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_TCRIT_HYST); val 646 drivers/hwmon/lm90.c if (val < 0) val 647 drivers/hwmon/lm90.c return val; val 648 drivers/hwmon/lm90.c data->temp_hyst = val; val 650 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_REMOTE_LOWH); val 651 drivers/hwmon/lm90.c if (val < 0) val 652 drivers/hwmon/lm90.c return val; val 653 drivers/hwmon/lm90.c data->temp11[REMOTE_LOW] = val << 8; val 656 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_REMOTE_LOWL); val 657 drivers/hwmon/lm90.c if (val < 0) val 658 drivers/hwmon/lm90.c return val; val 659 drivers/hwmon/lm90.c data->temp11[REMOTE_LOW] |= val; val 662 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_REMOTE_HIGHH); val 663 drivers/hwmon/lm90.c if (val < 0) val 664 drivers/hwmon/lm90.c return val; val 665 drivers/hwmon/lm90.c data->temp11[REMOTE_HIGH] = val << 8; val 668 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_REMOTE_HIGHL); val 669 drivers/hwmon/lm90.c if (val < 0) val 670 drivers/hwmon/lm90.c return val; val 671 drivers/hwmon/lm90.c data->temp11[REMOTE_HIGH] |= val; val 675 drivers/hwmon/lm90.c val = lm90_read16(client, LM90_REG_R_REMOTE_OFFSH, val 677 drivers/hwmon/lm90.c if (val < 0) val 678 drivers/hwmon/lm90.c return val; val 679 drivers/hwmon/lm90.c data->temp11[REMOTE_OFFSET] = val; val 683 drivers/hwmon/lm90.c val = lm90_read_reg(client, MAX6659_REG_R_LOCAL_EMERG); val 684 drivers/hwmon/lm90.c if (val < 0) val 685 drivers/hwmon/lm90.c return val; val 686 drivers/hwmon/lm90.c data->temp8[LOCAL_EMERG] = val; val 688 drivers/hwmon/lm90.c val = lm90_read_reg(client, MAX6659_REG_R_REMOTE_EMERG); val 689 drivers/hwmon/lm90.c if (val < 0) val 690 drivers/hwmon/lm90.c return val; val 691 drivers/hwmon/lm90.c data->temp8[REMOTE_EMERG] = val; val 695 drivers/hwmon/lm90.c val = lm90_select_remote_channel(data, 1); val 696 drivers/hwmon/lm90.c if (val < 0) val 697 drivers/hwmon/lm90.c return val; val 699 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_REMOTE_CRIT); val 700 drivers/hwmon/lm90.c if (val < 0) val 701 drivers/hwmon/lm90.c return val; val 702 drivers/hwmon/lm90.c data->temp8[REMOTE2_CRIT] = val; val 704 drivers/hwmon/lm90.c val = lm90_read_reg(client, MAX6659_REG_R_REMOTE_EMERG); val 705 drivers/hwmon/lm90.c if (val < 0) val 706 drivers/hwmon/lm90.c return val; val 707 drivers/hwmon/lm90.c data->temp8[REMOTE2_EMERG] = val; val 709 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_REMOTE_LOWH); val 710 drivers/hwmon/lm90.c if (val < 0) val 711 drivers/hwmon/lm90.c return val; val 712 drivers/hwmon/lm90.c data->temp11[REMOTE2_LOW] = val << 8; val 714 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_REMOTE_HIGHH); val 715 drivers/hwmon/lm90.c if (val < 0) val 716 drivers/hwmon/lm90.c return val; val 717 drivers/hwmon/lm90.c data->temp11[REMOTE2_HIGH] = val << 8; val 730 drivers/hwmon/lm90.c int val; val 733 drivers/hwmon/lm90.c val = lm90_update_limits(dev); val 734 drivers/hwmon/lm90.c if (val < 0) val 735 drivers/hwmon/lm90.c return val; val 745 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_LOCAL_LOW); val 746 drivers/hwmon/lm90.c if (val < 0) val 747 drivers/hwmon/lm90.c return val; val 748 drivers/hwmon/lm90.c data->temp8[LOCAL_LOW] = val; val 750 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_LOCAL_HIGH); val 751 drivers/hwmon/lm90.c if (val < 0) val 752 drivers/hwmon/lm90.c return val; val 753 drivers/hwmon/lm90.c data->temp8[LOCAL_HIGH] = val; val 756 drivers/hwmon/lm90.c val = lm90_read16(client, LM90_REG_R_LOCAL_TEMP, val 758 drivers/hwmon/lm90.c if (val < 0) val 759 drivers/hwmon/lm90.c return val; val 760 drivers/hwmon/lm90.c data->temp11[LOCAL_TEMP] = val; val 762 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_LOCAL_TEMP); val 763 drivers/hwmon/lm90.c if (val < 0) val 764 drivers/hwmon/lm90.c return val; val 765 drivers/hwmon/lm90.c data->temp11[LOCAL_TEMP] = val << 8; val 767 drivers/hwmon/lm90.c val = lm90_read16(client, LM90_REG_R_REMOTE_TEMPH, val 769 drivers/hwmon/lm90.c if (val < 0) val 770 drivers/hwmon/lm90.c return val; val 771 drivers/hwmon/lm90.c data->temp11[REMOTE_TEMP] = val; val 773 drivers/hwmon/lm90.c val = lm90_read_reg(client, LM90_REG_R_STATUS); val 774 drivers/hwmon/lm90.c if (val < 0) val 775 drivers/hwmon/lm90.c return val; val 776 drivers/hwmon/lm90.c data->alarms = val; /* lower 8 bit of alarms */ val 779 drivers/hwmon/lm90.c val = lm90_select_remote_channel(data, 1); val 780 drivers/hwmon/lm90.c if (val < 0) val 781 drivers/hwmon/lm90.c return val; val 783 drivers/hwmon/lm90.c val = lm90_read16(client, LM90_REG_R_REMOTE_TEMPH, val 785 drivers/hwmon/lm90.c if (val < 0) { val 787 drivers/hwmon/lm90.c return val; val 789 drivers/hwmon/lm90.c data->temp11[REMOTE2_TEMP] = val; val 793 drivers/hwmon/lm90.c val = lm90_read_reg(client, MAX6696_REG_R_STATUS2); val 794 drivers/hwmon/lm90.c if (val < 0) val 795 drivers/hwmon/lm90.c return val; val 796 drivers/hwmon/lm90.c data->alarms |= val << 8; val 827 drivers/hwmon/lm90.c static inline int temp_from_s8(s8 val) val 829 drivers/hwmon/lm90.c return val * 1000; val 832 drivers/hwmon/lm90.c static inline int temp_from_u8(u8 val) val 834 drivers/hwmon/lm90.c return val * 1000; val 837 drivers/hwmon/lm90.c static inline int temp_from_s16(s16 val) val 839 drivers/hwmon/lm90.c return val / 32 * 125; val 842 drivers/hwmon/lm90.c static inline int temp_from_u16(u16 val) val 844 drivers/hwmon/lm90.c return val / 32 * 125; val 847 drivers/hwmon/lm90.c static s8 temp_to_s8(long val) val 849 drivers/hwmon/lm90.c if (val <= -128000) val 851 drivers/hwmon/lm90.c if (val >= 127000) val 853 drivers/hwmon/lm90.c if (val < 0) val 854 drivers/hwmon/lm90.c return (val - 500) / 1000; val 855 drivers/hwmon/lm90.c return (val + 500) / 1000; val 858 drivers/hwmon/lm90.c static u8 temp_to_u8(long val) val 860 drivers/hwmon/lm90.c if (val <= 0) val 862 drivers/hwmon/lm90.c if (val >= 255000) val 864 drivers/hwmon/lm90.c return (val + 500) / 1000; val 867 drivers/hwmon/lm90.c static s16 temp_to_s16(long val) val 869 drivers/hwmon/lm90.c if (val <= -128000) val 871 drivers/hwmon/lm90.c if (val >= 127875) val 873 drivers/hwmon/lm90.c if (val < 0) val 874 drivers/hwmon/lm90.c return (val - 62) / 125 * 32; val 875 drivers/hwmon/lm90.c return (val + 62) / 125 * 32; val 878 drivers/hwmon/lm90.c static u8 hyst_to_reg(long val) val 880 drivers/hwmon/lm90.c if (val <= 0) val 882 drivers/hwmon/lm90.c if (val >= 30500) val 884 drivers/hwmon/lm90.c return (val + 500) / 1000; val 895 drivers/hwmon/lm90.c static inline int temp_from_u8_adt7461(struct lm90_data *data, u8 val) val 898 drivers/hwmon/lm90.c return (val - 64) * 1000; val 899 drivers/hwmon/lm90.c return temp_from_s8(val); val 902 drivers/hwmon/lm90.c static inline int temp_from_u16_adt7461(struct lm90_data *data, u16 val) val 905 drivers/hwmon/lm90.c return (val - 0x4000) / 64 * 250; val 906 drivers/hwmon/lm90.c return temp_from_s16(val); val 909 drivers/hwmon/lm90.c static u8 temp_to_u8_adt7461(struct lm90_data *data, long val) val 912 drivers/hwmon/lm90.c if (val <= -64000) val 914 drivers/hwmon/lm90.c if (val >= 191000) val 916 drivers/hwmon/lm90.c return (val + 500 + 64000) / 1000; val 918 drivers/hwmon/lm90.c if (val <= 0) val 920 drivers/hwmon/lm90.c if (val >= 127000) val 922 drivers/hwmon/lm90.c return (val + 500) / 1000; val 925 drivers/hwmon/lm90.c static u16 temp_to_u16_adt7461(struct lm90_data *data, long val) val 928 drivers/hwmon/lm90.c if (val <= -64000) val 930 drivers/hwmon/lm90.c if (val >= 191750) val 932 drivers/hwmon/lm90.c return (val + 64000 + 125) / 250 * 64; val 934 drivers/hwmon/lm90.c if (val <= 0) val 936 drivers/hwmon/lm90.c if (val >= 127750) val 938 drivers/hwmon/lm90.c return (val + 125) / 250 * 64; val 954 drivers/hwmon/lm90.c long val; val 957 drivers/hwmon/lm90.c err = kstrtol(buf, 10, &val); val 961 drivers/hwmon/lm90.c switch (val) { val 996 drivers/hwmon/lm90.c static int lm90_set_temp11(struct lm90_data *data, int index, long val) val 1014 drivers/hwmon/lm90.c val -= 16000; val 1017 drivers/hwmon/lm90.c data->temp11[index] = temp_to_u16_adt7461(data, val); val 1019 drivers/hwmon/lm90.c data->temp11[index] = temp_to_u8(val) << 8; val 1021 drivers/hwmon/lm90.c data->temp11[index] = temp_to_s16(val); val 1023 drivers/hwmon/lm90.c data->temp11[index] = temp_to_s8(val) << 8; val 1057 drivers/hwmon/lm90.c static int lm90_set_temp8(struct lm90_data *data, int index, long val) val 1074 drivers/hwmon/lm90.c val -= 16000; val 1077 drivers/hwmon/lm90.c data->temp8[index] = temp_to_u8_adt7461(data, val); val 1079 drivers/hwmon/lm90.c data->temp8[index] = temp_to_u8(val); val 1081 drivers/hwmon/lm90.c data->temp8[index] = temp_to_s8(val); val 1108 drivers/hwmon/lm90.c static int lm90_set_temphyst(struct lm90_data *data, long val) val 1121 drivers/hwmon/lm90.c data->temp_hyst = hyst_to_reg(temp - val); val 1153 drivers/hwmon/lm90.c static int lm90_temp_read(struct device *dev, u32 attr, int channel, long *val) val 1166 drivers/hwmon/lm90.c *val = lm90_get_temp11(data, lm90_temp_index[channel]); val 1169 drivers/hwmon/lm90.c *val = (data->alarms >> lm90_min_alarm_bits[channel]) & 1; val 1172 drivers/hwmon/lm90.c *val = (data->alarms >> lm90_max_alarm_bits[channel]) & 1; val 1175 drivers/hwmon/lm90.c *val = (data->alarms >> lm90_crit_alarm_bits[channel]) & 1; val 1178 drivers/hwmon/lm90.c *val = (data->alarms >> lm90_emergency_alarm_bits[channel]) & 1; val 1181 drivers/hwmon/lm90.c *val = (data->alarms >> lm90_fault_bits[channel]) & 1; val 1185 drivers/hwmon/lm90.c *val = lm90_get_temp8(data, val 1188 drivers/hwmon/lm90.c *val = lm90_get_temp11(data, val 1193 drivers/hwmon/lm90.c *val = lm90_get_temp8(data, val 1196 drivers/hwmon/lm90.c *val = lm90_get_temp11(data, val 1200 drivers/hwmon/lm90.c *val = lm90_get_temp8(data, lm90_temp_crit_index[channel]); val 1203 drivers/hwmon/lm90.c *val = lm90_get_temphyst(data, lm90_temp_crit_index[channel]); val 1206 drivers/hwmon/lm90.c *val = lm90_get_temp8(data, lm90_temp_emerg_index[channel]); val 1209 drivers/hwmon/lm90.c *val = lm90_get_temphyst(data, lm90_temp_emerg_index[channel]); val 1212 drivers/hwmon/lm90.c *val = lm90_get_temp11(data, REMOTE_OFFSET); val 1220 drivers/hwmon/lm90.c static int lm90_temp_write(struct device *dev, u32 attr, int channel, long val) val 1236 drivers/hwmon/lm90.c val); val 1240 drivers/hwmon/lm90.c val); val 1246 drivers/hwmon/lm90.c val); val 1250 drivers/hwmon/lm90.c val); val 1253 drivers/hwmon/lm90.c err = lm90_set_temp8(data, lm90_temp_crit_index[channel], val); val 1256 drivers/hwmon/lm90.c err = lm90_set_temphyst(data, val); val 1259 drivers/hwmon/lm90.c err = lm90_set_temp8(data, lm90_temp_emerg_index[channel], val); val 1262 drivers/hwmon/lm90.c err = lm90_set_temp11(data, REMOTE_OFFSET, val); val 1300 drivers/hwmon/lm90.c static int lm90_chip_read(struct device *dev, u32 attr, int channel, long *val) val 1313 drivers/hwmon/lm90.c *val = data->update_interval; val 1316 drivers/hwmon/lm90.c *val = data->alarms; val 1325 drivers/hwmon/lm90.c static int lm90_chip_write(struct device *dev, u32 attr, int channel, long val) val 1340 drivers/hwmon/lm90.c clamp_val(val, 0, 100000)); val 1365 drivers/hwmon/lm90.c u32 attr, int channel, long *val) val 1369 drivers/hwmon/lm90.c return lm90_chip_read(dev, attr, channel, val); val 1371 drivers/hwmon/lm90.c return lm90_temp_read(dev, attr, channel, val); val 1378 drivers/hwmon/lm90.c u32 attr, int channel, long val) val 1382 drivers/hwmon/lm90.c return lm90_chip_write(dev, attr, channel, val); val 1384 drivers/hwmon/lm90.c return lm90_temp_write(dev, attr, channel, val); val 69 drivers/hwmon/lm92.c static inline s16 TEMP_TO_REG(long val) val 71 drivers/hwmon/lm92.c val = clamp_val(val, -60000, 160000); val 72 drivers/hwmon/lm92.c return val * 10 / 625 * 8; val 154 drivers/hwmon/lm92.c long val; val 157 drivers/hwmon/lm92.c err = kstrtol(buf, 10, &val); val 162 drivers/hwmon/lm92.c data->temp[nr] = TEMP_TO_REG(val); val 194 drivers/hwmon/lm92.c long val; val 197 drivers/hwmon/lm92.c err = kstrtol(buf, 10, &val); val 201 drivers/hwmon/lm92.c val = clamp_val(val, -120000, 220000); val 204 drivers/hwmon/lm92.c TEMP_TO_REG(TEMP_FROM_REG(data->temp[attr->index]) - val); val 358 drivers/hwmon/lm93.c static u8 LM93_IN_TO_REG(int nr, unsigned val) val 361 drivers/hwmon/lm93.c const long mv = clamp_val(val, val 397 drivers/hwmon/lm93.c static u8 LM93_IN_REL_TO_REG(unsigned val, int upper, int vid) val 399 drivers/hwmon/lm93.c long uv_offset = vid * 1000 - val * 10000; val 1152 drivers/hwmon/lm93.c unsigned long val; val 1155 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1163 drivers/hwmon/lm93.c LM93_IN_REL_TO_REG(val, 0, vid); val 1167 drivers/hwmon/lm93.c data->block7[nr].min = LM93_IN_TO_REG(nr, val); val 1217 drivers/hwmon/lm93.c unsigned long val; val 1220 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1228 drivers/hwmon/lm93.c LM93_IN_REL_TO_REG(val, 1, vid); val 1232 drivers/hwmon/lm93.c data->block7[nr].max = LM93_IN_TO_REG(nr, val); val 1284 drivers/hwmon/lm93.c long val; val 1287 drivers/hwmon/lm93.c err = kstrtol(buf, 10, &val); val 1292 drivers/hwmon/lm93.c data->temp_lim[nr].min = LM93_TEMP_TO_REG(val); val 1317 drivers/hwmon/lm93.c long val; val 1320 drivers/hwmon/lm93.c err = kstrtol(buf, 10, &val); val 1325 drivers/hwmon/lm93.c data->temp_lim[nr].max = LM93_TEMP_TO_REG(val); val 1350 drivers/hwmon/lm93.c long val; val 1353 drivers/hwmon/lm93.c err = kstrtol(buf, 10, &val); val 1358 drivers/hwmon/lm93.c data->block10.base[nr] = LM93_TEMP_TO_REG(val); val 1383 drivers/hwmon/lm93.c long val; val 1386 drivers/hwmon/lm93.c err = kstrtol(buf, 10, &val); val 1391 drivers/hwmon/lm93.c data->boost[nr] = LM93_TEMP_TO_REG(val); val 1419 drivers/hwmon/lm93.c unsigned long val; val 1422 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1431 drivers/hwmon/lm93.c data->boost_hyst[nr/2] = LM93_AUTO_BOOST_HYST_TO_REG(data, val, nr, 1); val 1464 drivers/hwmon/lm93.c unsigned long val; val 1467 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1477 drivers/hwmon/lm93.c data->block10.offset[ofs], val, nr, 1); val 1542 drivers/hwmon/lm93.c unsigned long val; val 1545 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1553 drivers/hwmon/lm93.c LM93_PWM_TO_REG(val, (ctl4 & 0x07) ? val 1585 drivers/hwmon/lm93.c unsigned long val; val 1588 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1598 drivers/hwmon/lm93.c reg = (reg & 0xf0) | (LM93_TEMP_OFFSET_TO_REG(val, 1) & 0x0f); val 1640 drivers/hwmon/lm93.c unsigned long val; val 1643 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1648 drivers/hwmon/lm93.c data->block8[nr] = LM93_FAN_TO_REG(val); val 1719 drivers/hwmon/lm93.c unsigned long val; val 1722 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1728 drivers/hwmon/lm93.c if (val <= 2) { val 1730 drivers/hwmon/lm93.c if (val) { val 1732 drivers/hwmon/lm93.c LM93_REG_PWM_CTL(val - 1, LM93_PWM_CTL4)); val 1734 drivers/hwmon/lm93.c val = 0; val 1736 drivers/hwmon/lm93.c lm93_write_fan_smart_tach(client, data, nr, val); val 1772 drivers/hwmon/lm93.c unsigned long val; val 1775 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1782 drivers/hwmon/lm93.c ctl2 = (ctl2 & 0x0f) | LM93_PWM_TO_REG(val, (ctl4 & 0x07) ? val 1820 drivers/hwmon/lm93.c unsigned long val; val 1823 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1830 drivers/hwmon/lm93.c switch (val) { val 1896 drivers/hwmon/lm93.c unsigned long val; val 1899 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1905 drivers/hwmon/lm93.c ctl4 = (ctl4 & 0xf8) | LM93_PWM_FREQ_TO_REG(val); val 1934 drivers/hwmon/lm93.c unsigned long val; val 1937 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1942 drivers/hwmon/lm93.c data->block9[nr][LM93_PWM_CTL1] = clamp_val(val, 0, 255); val 1975 drivers/hwmon/lm93.c unsigned long val; val 1978 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 1985 drivers/hwmon/lm93.c ctl3 = (ctl3 & 0xf0) | LM93_PWM_TO_REG(val, (ctl4 & 0x07) ? val 2015 drivers/hwmon/lm93.c unsigned long val; val 2018 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 2024 drivers/hwmon/lm93.c ctl3 = (ctl3 & 0x1f) | (LM93_SPINUP_TIME_TO_REG(val) << 5 & 0xe0); val 2049 drivers/hwmon/lm93.c unsigned long val; val 2052 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 2058 drivers/hwmon/lm93.c ramp = (ramp & 0x0f) | (LM93_RAMP_TO_REG(val) << 4 & 0xf0); val 2081 drivers/hwmon/lm93.c unsigned long val; val 2084 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 2090 drivers/hwmon/lm93.c ramp = (ramp & 0xf0) | (LM93_RAMP_TO_REG(val) & 0x0f); val 2146 drivers/hwmon/lm93.c unsigned long val; val 2149 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 2154 drivers/hwmon/lm93.c data->prochot_max[nr] = LM93_PROCHOT_TO_REG(val); val 2182 drivers/hwmon/lm93.c unsigned long val; val 2185 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 2190 drivers/hwmon/lm93.c if (val) val 2224 drivers/hwmon/lm93.c unsigned long val; val 2227 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 2234 drivers/hwmon/lm93.c tmp = (tmp & 0x0f) | (LM93_INTERVAL_TO_REG(val) << 4); val 2236 drivers/hwmon/lm93.c tmp = (tmp & 0xf0) | LM93_INTERVAL_TO_REG(val); val 2260 drivers/hwmon/lm93.c unsigned long val; val 2263 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 2269 drivers/hwmon/lm93.c clamp_val(val, 0, 15); val 2291 drivers/hwmon/lm93.c unsigned long val; val 2294 drivers/hwmon/lm93.c err = kstrtoul(buf, 10, &val); val 2299 drivers/hwmon/lm93.c if (val) val 73 drivers/hwmon/lm95234.c int val; val 77 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, val 79 drivers/hwmon/lm95234.c if (val < 0) val 80 drivers/hwmon/lm95234.c return val; val 81 drivers/hwmon/lm95234.c temp = val << 8; val 82 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, val 84 drivers/hwmon/lm95234.c if (val < 0) val 85 drivers/hwmon/lm95234.c return val; val 86 drivers/hwmon/lm95234.c temp |= val; val 94 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, val 96 drivers/hwmon/lm95234.c if (val < 0) val 97 drivers/hwmon/lm95234.c return val; val 98 drivers/hwmon/lm95234.c temp = val << 8; val 99 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, val 101 drivers/hwmon/lm95234.c if (val < 0) val 102 drivers/hwmon/lm95234.c return val; val 103 drivers/hwmon/lm95234.c temp |= val; val 249 drivers/hwmon/lm95234.c unsigned long val; val 256 drivers/hwmon/lm95234.c ret = kstrtoul(buf, 10, &val); val 260 drivers/hwmon/lm95234.c if (val != 1 && val != 2) val 264 drivers/hwmon/lm95234.c if (val == 1) val 294 drivers/hwmon/lm95234.c long val; val 300 drivers/hwmon/lm95234.c ret = kstrtol(buf, 10, &val); val 304 drivers/hwmon/lm95234.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, index ? 255 : 127); val 307 drivers/hwmon/lm95234.c data->tcrit2[index] = val; val 308 drivers/hwmon/lm95234.c i2c_smbus_write_byte_data(data->client, LM95234_REG_TCRIT2(index), val); val 344 drivers/hwmon/lm95234.c long val; val 349 drivers/hwmon/lm95234.c ret = kstrtol(buf, 10, &val); val 353 drivers/hwmon/lm95234.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255); val 356 drivers/hwmon/lm95234.c data->tcrit1[index] = val; val 357 drivers/hwmon/lm95234.c i2c_smbus_write_byte_data(data->client, LM95234_REG_TCRIT1(index), val); val 385 drivers/hwmon/lm95234.c long val; val 390 drivers/hwmon/lm95234.c ret = kstrtol(buf, 10, &val); val 394 drivers/hwmon/lm95234.c val = DIV_ROUND_CLOSEST(val, 1000); val 395 drivers/hwmon/lm95234.c val = clamp_val((int)data->tcrit1[index] - val, 0, 31); val 398 drivers/hwmon/lm95234.c data->thyst = val; val 399 drivers/hwmon/lm95234.c i2c_smbus_write_byte_data(data->client, LM95234_REG_TCRIT_HYST, val); val 424 drivers/hwmon/lm95234.c long val; val 429 drivers/hwmon/lm95234.c ret = kstrtol(buf, 10, &val); val 434 drivers/hwmon/lm95234.c val = clamp_val(DIV_ROUND_CLOSEST(val, 500), -128, 127); val 437 drivers/hwmon/lm95234.c data->toffset[index] = val; val 438 drivers/hwmon/lm95234.c i2c_smbus_write_byte_data(data->client, LM95234_REG_OFFSET(index), val); val 463 drivers/hwmon/lm95234.c unsigned long val; val 469 drivers/hwmon/lm95234.c ret = kstrtoul(buf, 10, &val); val 474 drivers/hwmon/lm95234.c if (val <= update_intervals[regval]) val 597 drivers/hwmon/lm95234.c int mfg_id, chip_id, val; val 627 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, LM95234_REG_STATUS); val 628 drivers/hwmon/lm95234.c if (val & 0x30) val 631 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, LM95234_REG_CONFIG); val 632 drivers/hwmon/lm95234.c if (val & config_mask) val 635 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, LM95234_REG_CONVRATE); val 636 drivers/hwmon/lm95234.c if (val & 0xfc) val 639 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, LM95234_REG_REM_MODEL); val 640 drivers/hwmon/lm95234.c if (val & model_mask) val 643 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, LM95234_REG_REM_MODEL_STS); val 644 drivers/hwmon/lm95234.c if (val & model_mask) val 653 drivers/hwmon/lm95234.c int val, model; val 656 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, LM95234_REG_CONFIG); val 657 drivers/hwmon/lm95234.c if (val < 0) val 658 drivers/hwmon/lm95234.c return val; val 659 drivers/hwmon/lm95234.c if (val & 0x40) val 661 drivers/hwmon/lm95234.c val & ~0x40); val 664 drivers/hwmon/lm95234.c val = i2c_smbus_read_byte_data(client, LM95234_REG_REM_MODEL_STS); val 665 drivers/hwmon/lm95234.c if (val < 0) val 666 drivers/hwmon/lm95234.c return val; val 670 drivers/hwmon/lm95234.c if (model & val) { val 673 drivers/hwmon/lm95234.c val); val 675 drivers/hwmon/lm95234.c model & ~val); val 130 drivers/hwmon/lm95241.c long *val) val 136 drivers/hwmon/lm95241.c *val = data->interval; val 144 drivers/hwmon/lm95241.c long *val) val 151 drivers/hwmon/lm95241.c *val = temp_from_reg_signed(data->temp[channel * 2], val 154 drivers/hwmon/lm95241.c *val = temp_from_reg_unsigned(data->temp[channel * 2], val 159 drivers/hwmon/lm95241.c *val = (data->config & R1DF_MASK) ? -128000 : 0; val 161 drivers/hwmon/lm95241.c *val = (data->config & R2DF_MASK) ? -128000 : 0; val 165 drivers/hwmon/lm95241.c *val = (data->config & R1DF_MASK) ? 127875 : 255875; val 167 drivers/hwmon/lm95241.c *val = (data->config & R2DF_MASK) ? 127875 : 255875; val 171 drivers/hwmon/lm95241.c *val = (data->model & R1MS_MASK) ? 1 : 2; val 173 drivers/hwmon/lm95241.c *val = (data->model & R2MS_MASK) ? 1 : 2; val 177 drivers/hwmon/lm95241.c *val = !!(data->status & R1DM); val 179 drivers/hwmon/lm95241.c *val = !!(data->status & R2DM); val 187 drivers/hwmon/lm95241.c u32 attr, int channel, long *val) val 191 drivers/hwmon/lm95241.c return lm95241_read_chip(dev, attr, channel, val); val 193 drivers/hwmon/lm95241.c return lm95241_read_temp(dev, attr, channel, val); val 200 drivers/hwmon/lm95241.c long val) val 212 drivers/hwmon/lm95241.c if (val < 130) { val 215 drivers/hwmon/lm95241.c } else if (val < 590) { val 218 drivers/hwmon/lm95241.c } else if (val < 1850) { val 239 drivers/hwmon/lm95241.c long val) val 250 drivers/hwmon/lm95241.c if (val < 0) val 255 drivers/hwmon/lm95241.c if (val < 0) val 266 drivers/hwmon/lm95241.c if (val <= 127875) val 271 drivers/hwmon/lm95241.c if (val <= 127875) val 281 drivers/hwmon/lm95241.c if (val != 1 && val != 2) { val 287 drivers/hwmon/lm95241.c if (val == 1) { val 296 drivers/hwmon/lm95241.c if (val == 1) { val 323 drivers/hwmon/lm95241.c u32 attr, int channel, long val) val 327 drivers/hwmon/lm95241.c return lm95241_write_chip(dev, attr, channel, val); val 329 drivers/hwmon/lm95241.c return lm95241_write_temp(dev, attr, channel, val); val 160 drivers/hwmon/lm95245.c long *val) val 185 drivers/hwmon/lm95245.c *val = temp_from_reg_signed(regvalh, regvall); val 196 drivers/hwmon/lm95245.c *val = temp_from_reg_unsigned(regvalh, regvall); val 203 drivers/hwmon/lm95245.c *val = regvalh * 1000; val 211 drivers/hwmon/lm95245.c *val = regvalh * 1000; val 222 drivers/hwmon/lm95245.c *val = (regvalh - regvall) * 1000; val 234 drivers/hwmon/lm95245.c *val = (regvalh - regvall) * 1000; val 240 drivers/hwmon/lm95245.c *val = (regvalh & CFG2_REMOTE_TT) ? 1 : 2; val 251 drivers/hwmon/lm95245.c *val = temp_from_reg_signed(regvalh, regvall); val 257 drivers/hwmon/lm95245.c *val = !!(regvalh & STATUS1_ROS); val 263 drivers/hwmon/lm95245.c *val = !!(regvalh & (channel ? STATUS1_RTCRIT : STATUS1_LOC)); val 269 drivers/hwmon/lm95245.c *val = !!(regvalh & STATUS1_DIODE_FAULT); val 277 drivers/hwmon/lm95245.c long val) val 286 drivers/hwmon/lm95245.c val = clamp_val(val / 1000, 0, 255); val 287 drivers/hwmon/lm95245.c ret = regmap_write(regmap, LM95245_REG_RW_REMOTE_OS_LIMIT, val); val 292 drivers/hwmon/lm95245.c val = clamp_val(val / 1000, 0, channel ? 255 : 127); val 293 drivers/hwmon/lm95245.c ret = regmap_write(regmap, reg, val); val 304 drivers/hwmon/lm95245.c val = clamp_val(val, -1000000, 1000000); val 305 drivers/hwmon/lm95245.c val = regval - val / 1000; val 306 drivers/hwmon/lm95245.c val = clamp_val(val, 0, 31); val 308 drivers/hwmon/lm95245.c val); val 312 drivers/hwmon/lm95245.c val = clamp_val(val, -128000, 127875); val 313 drivers/hwmon/lm95245.c val = val * 256 / 1000; val 316 drivers/hwmon/lm95245.c val & 0xe0); val 322 drivers/hwmon/lm95245.c (val >> 8) & 0xff); val 326 drivers/hwmon/lm95245.c if (val != 1 && val != 2) val 330 drivers/hwmon/lm95245.c val == 1 ? CFG2_REMOTE_TT : 0); val 338 drivers/hwmon/lm95245.c long *val) val 344 drivers/hwmon/lm95245.c *val = data->interval; val 352 drivers/hwmon/lm95245.c long val) val 360 drivers/hwmon/lm95245.c ret = lm95245_set_conversion_rate(data, val); val 369 drivers/hwmon/lm95245.c u32 attr, int channel, long *val) val 373 drivers/hwmon/lm95245.c return lm95245_read_chip(dev, attr, channel, val); val 375 drivers/hwmon/lm95245.c return lm95245_read_temp(dev, attr, channel, val); val 382 drivers/hwmon/lm95245.c u32 attr, int channel, long val) val 386 drivers/hwmon/lm95245.c return lm95245_write_chip(dev, attr, channel, val); val 388 drivers/hwmon/lm95245.c return lm95245_write_temp(dev, attr, channel, val); val 94 drivers/hwmon/lochnagar-hwmon.c unsigned int val; val 113 drivers/hwmon/lochnagar-hwmon.c ret = regmap_read_poll_timeout(regmap, LOCHNAGAR2_IMON_CTRL3, val, val 114 drivers/hwmon/lochnagar-hwmon.c val & LOCHNAGAR2_IMON_DONE_MASK, val 133 drivers/hwmon/lochnagar-hwmon.c ret = regmap_read_poll_timeout(regmap, LOCHNAGAR2_IMON_CTRL3, val, val 134 drivers/hwmon/lochnagar-hwmon.c val & LOCHNAGAR2_IMON_DONE_MASK, val 144 drivers/hwmon/lochnagar-hwmon.c unsigned int val; val 153 drivers/hwmon/lochnagar-hwmon.c ret = regmap_read_poll_timeout(regmap, LOCHNAGAR2_IMON_CTRL4, val, val 154 drivers/hwmon/lochnagar-hwmon.c val & LOCHNAGAR2_IMON_DATA_RDY_MASK, val 159 drivers/hwmon/lochnagar-hwmon.c ret = regmap_read(regmap, LOCHNAGAR2_IMON_DATA1, &val); val 163 drivers/hwmon/lochnagar-hwmon.c *data = val << 16; val 165 drivers/hwmon/lochnagar-hwmon.c ret = regmap_read(regmap, LOCHNAGAR2_IMON_DATA2, &val); val 169 drivers/hwmon/lochnagar-hwmon.c *data |= val; val 176 drivers/hwmon/lochnagar-hwmon.c unsigned int precision, long *val) val 197 drivers/hwmon/lochnagar-hwmon.c *val = float_to_long(data, precision); val 205 drivers/hwmon/lochnagar-hwmon.c static int read_power(struct device *dev, int chan, long *val) val 215 drivers/hwmon/lochnagar-hwmon.c ret = read_sensor(dev, chan, LN2_VOLT, 1, LN2_PWR_UNITS, val); val 219 drivers/hwmon/lochnagar-hwmon.c power = abs(*val); val 222 drivers/hwmon/lochnagar-hwmon.c ret = read_sensor(dev, chan, LN2_CURR, nsamples, LN2_PWR_UNITS, val); val 226 drivers/hwmon/lochnagar-hwmon.c power *= abs(*val); val 230 drivers/hwmon/lochnagar-hwmon.c *val = LONG_MAX; val 232 drivers/hwmon/lochnagar-hwmon.c *val = power; val 258 drivers/hwmon/lochnagar-hwmon.c u32 attr, int chan, long *val) val 265 drivers/hwmon/lochnagar-hwmon.c return read_sensor(dev, chan, LN2_VOLT, 1, LN2_VOLT_UNITS, val); val 267 drivers/hwmon/lochnagar-hwmon.c return read_sensor(dev, chan, LN2_CURR, 1, LN2_CURR_UNITS, val); val 269 drivers/hwmon/lochnagar-hwmon.c return read_sensor(dev, chan, LN2_TEMP, 1, LN2_TEMP_UNITS, val); val 273 drivers/hwmon/lochnagar-hwmon.c return read_power(dev, chan, val); val 276 drivers/hwmon/lochnagar-hwmon.c *val = DIV_ROUND_CLOSEST(interval, 1000); val 302 drivers/hwmon/lochnagar-hwmon.c u32 attr, int chan, long val) val 309 drivers/hwmon/lochnagar-hwmon.c val = clamp_t(long, val, 1, (LN2_MAX_NSAMPLE * LN2_SAMPLE_US) / 1000); val 310 drivers/hwmon/lochnagar-hwmon.c val = DIV_ROUND_CLOSEST(val * 1000, LN2_SAMPLE_US); val 312 drivers/hwmon/lochnagar-hwmon.c priv->power_nsamples[chan] = val; val 72 drivers/hwmon/ltc2945.c long long val; val 82 drivers/hwmon/ltc2945.c val = (buf[0] << 16) + (buf[1] << 8) + buf[2]; val 85 drivers/hwmon/ltc2945.c val = (buf[0] << 4) + (buf[1] >> 4); val 106 drivers/hwmon/ltc2945.c val *= 625LL; val 109 drivers/hwmon/ltc2945.c val = (val * 25LL) >> 1; val 118 drivers/hwmon/ltc2945.c val *= 25; val 126 drivers/hwmon/ltc2945.c val = val >> 1; val 140 drivers/hwmon/ltc2945.c val *= 25; val 145 drivers/hwmon/ltc2945.c return val; val 149 drivers/hwmon/ltc2945.c unsigned long val) val 174 drivers/hwmon/ltc2945.c val = DIV_ROUND_CLOSEST(val, 625); val 181 drivers/hwmon/ltc2945.c val = DIV_ROUND_CLOSEST(val, 25) * 2; val 190 drivers/hwmon/ltc2945.c val /= 25; val 198 drivers/hwmon/ltc2945.c val *= 2; val 212 drivers/hwmon/ltc2945.c val = DIV_ROUND_CLOSEST(val, 25); val 217 drivers/hwmon/ltc2945.c return val; val 239 drivers/hwmon/ltc2945.c unsigned long val; val 245 drivers/hwmon/ltc2945.c ret = kstrtoul(buf, 10, &val); val 250 drivers/hwmon/ltc2945.c regval = ltc2945_val_to_reg(dev, reg, val); val 277 drivers/hwmon/ltc2945.c unsigned long val; val 280 drivers/hwmon/ltc2945.c ret = kstrtoul(buf, 10, &val); val 283 drivers/hwmon/ltc2945.c if (val != 1) val 74 drivers/hwmon/ltc2990.c int val; val 104 drivers/hwmon/ltc2990.c val = i2c_smbus_read_word_swapped(i2c, reg); val 105 drivers/hwmon/ltc2990.c if (unlikely(val < 0)) val 106 drivers/hwmon/ltc2990.c return val; val 113 drivers/hwmon/ltc2990.c *result = sign_extend32(val, 12) * 1000 / 16; val 118 drivers/hwmon/ltc2990.c *result = sign_extend32(val, 14) * 1942 / 100; val 122 drivers/hwmon/ltc2990.c *result = sign_extend32(val, 14) * 30518 / (100 * 1000) + 2500; val 129 drivers/hwmon/ltc2990.c *result = sign_extend32(val, 14) * 30518 / (100 * 1000); val 67 drivers/hwmon/ltc4151.c int val; val 69 drivers/hwmon/ltc4151.c val = i2c_smbus_read_byte_data(client, i); val 70 drivers/hwmon/ltc4151.c if (unlikely(val < 0)) { val 73 drivers/hwmon/ltc4151.c val); val 74 drivers/hwmon/ltc4151.c ret = ERR_PTR(val); val 77 drivers/hwmon/ltc4151.c data->regs[i] = val; val 90 drivers/hwmon/ltc4151.c u32 val; val 92 drivers/hwmon/ltc4151.c val = (data->regs[reg] << 4) + (data->regs[reg + 1] >> 4); val 97 drivers/hwmon/ltc4151.c val = val * 500 / 1000; val 104 drivers/hwmon/ltc4151.c val = val * 20 * 1000 / data->shunt; val 108 drivers/hwmon/ltc4151.c val = val * 25; val 113 drivers/hwmon/ltc4151.c val = 0; val 117 drivers/hwmon/ltc4151.c return val; val 47 drivers/hwmon/ltc4215.c s32 val; val 59 drivers/hwmon/ltc4215.c val = i2c_smbus_read_byte_data(client, i); val 60 drivers/hwmon/ltc4215.c if (unlikely(val < 0)) val 63 drivers/hwmon/ltc4215.c data->regs[i] = val; val 50 drivers/hwmon/ltc4222.c unsigned int val; val 58 drivers/hwmon/ltc4222.c val = ((buf[0] << 8) + buf[1]) >> 6; val 64 drivers/hwmon/ltc4222.c val = DIV_ROUND_CLOSEST(val * 5, 4); val 69 drivers/hwmon/ltc4222.c val = DIV_ROUND_CLOSEST(val * 125, 4); val 80 drivers/hwmon/ltc4222.c val = DIV_ROUND_CLOSEST(val * 125, 2); val 85 drivers/hwmon/ltc4222.c return val; val 132 drivers/hwmon/ltc4245.c s32 val; val 141 drivers/hwmon/ltc4245.c val = i2c_smbus_read_byte_data(client, i); val 142 drivers/hwmon/ltc4245.c if (unlikely(val < 0)) val 145 drivers/hwmon/ltc4245.c data->cregs[i] = val; val 150 drivers/hwmon/ltc4245.c val = i2c_smbus_read_byte_data(client, i+0x10); val 151 drivers/hwmon/ltc4245.c if (unlikely(val < 0)) val 154 drivers/hwmon/ltc4245.c data->vregs[i] = val; val 269 drivers/hwmon/ltc4245.c long *val) val 275 drivers/hwmon/ltc4245.c *val = ltc4245_get_current(dev, ltc4245_curr_regs[channel]); val 278 drivers/hwmon/ltc4245.c *val = !!(data->cregs[LTC4245_FAULT1] & BIT(channel + 4)); val 285 drivers/hwmon/ltc4245.c static int ltc4245_read_in(struct device *dev, u32 attr, int channel, long *val) val 292 drivers/hwmon/ltc4245.c *val = ltc4245_get_voltage(dev, val 299 drivers/hwmon/ltc4245.c *val = regval * 10; val 304 drivers/hwmon/ltc4245.c *val = !!(data->cregs[LTC4245_FAULT1] & BIT(channel)); val 306 drivers/hwmon/ltc4245.c *val = !!(data->cregs[LTC4245_FAULT2] & val 315 drivers/hwmon/ltc4245.c long *val) val 325 drivers/hwmon/ltc4245.c *val = abs(curr * voltage); val 333 drivers/hwmon/ltc4245.c u32 attr, int channel, long *val) val 338 drivers/hwmon/ltc4245.c return ltc4245_read_curr(dev, attr, channel, val); val 340 drivers/hwmon/ltc4245.c return ltc4245_read_power(dev, attr, channel, val); val 342 drivers/hwmon/ltc4245.c return ltc4245_read_in(dev, attr, channel - 1, val); val 40 drivers/hwmon/ltc4260.c unsigned int val; val 43 drivers/hwmon/ltc4260.c ret = regmap_read(regmap, reg, &val); val 50 drivers/hwmon/ltc4260.c val = val * 10; val 54 drivers/hwmon/ltc4260.c val = val * 400; val 64 drivers/hwmon/ltc4260.c val = val * 300; val 70 drivers/hwmon/ltc4260.c return val; val 68 drivers/hwmon/ltc4261.c int val; val 70 drivers/hwmon/ltc4261.c val = i2c_smbus_read_byte_data(client, i); val 71 drivers/hwmon/ltc4261.c if (unlikely(val < 0)) { val 74 drivers/hwmon/ltc4261.c val); val 75 drivers/hwmon/ltc4261.c ret = ERR_PTR(val); val 79 drivers/hwmon/ltc4261.c data->regs[i] = val; val 92 drivers/hwmon/ltc4261.c u32 val; val 94 drivers/hwmon/ltc4261.c val = (data->regs[reg] << 2) + (data->regs[reg + 1] >> 6); val 100 drivers/hwmon/ltc4261.c val = val * 25 / 10; val 110 drivers/hwmon/ltc4261.c val = val * 625 / 10; val 115 drivers/hwmon/ltc4261.c val = 0; val 119 drivers/hwmon/ltc4261.c return val; val 180 drivers/hwmon/max16065.c int val = data->fault[attr2->nr]; val 182 drivers/hwmon/max16065.c if (val < 0) val 183 drivers/hwmon/max16065.c return val; val 185 drivers/hwmon/max16065.c val &= (1 << attr2->index); val 186 drivers/hwmon/max16065.c if (val) val 188 drivers/hwmon/max16065.c MAX16065_FAULT(attr2->nr), val); val 190 drivers/hwmon/max16065.c return snprintf(buf, PAGE_SIZE, "%d\n", !!val); val 225 drivers/hwmon/max16065.c unsigned long val; val 229 drivers/hwmon/max16065.c err = kstrtoul(buf, 10, &val); val 233 drivers/hwmon/max16065.c limit = MV_TO_LIMIT(val, data->range[attr2->index]); val 503 drivers/hwmon/max16065.c int i, j, val; val 524 drivers/hwmon/max16065.c val = i2c_smbus_read_byte_data(client, MAX16065_SW_ENABLE); val 525 drivers/hwmon/max16065.c if (unlikely(val < 0)) val 526 drivers/hwmon/max16065.c return val; val 527 drivers/hwmon/max16065.c secondary_is_max = val & MAX16065_WARNING_OV; val 532 drivers/hwmon/max16065.c val = i2c_smbus_read_byte_data(client, MAX16065_SCALE(i)); val 533 drivers/hwmon/max16065.c if (unlikely(val < 0)) val 534 drivers/hwmon/max16065.c return val; val 537 drivers/hwmon/max16065.c max16065_adc_range[(val >> (j * 2)) & 0x3]; val 547 drivers/hwmon/max16065.c val = i2c_smbus_read_byte_data(client, val 549 drivers/hwmon/max16065.c if (unlikely(val < 0)) val 550 drivers/hwmon/max16065.c return val; val 551 drivers/hwmon/max16065.c data->limit[i][j] = LIMIT_TO_MV(val, data->range[j]); val 562 drivers/hwmon/max16065.c val = i2c_smbus_read_byte_data(client, MAX16065_CURR_CONTROL); val 563 drivers/hwmon/max16065.c if (unlikely(val < 0)) val 564 drivers/hwmon/max16065.c return val; val 565 drivers/hwmon/max16065.c if (val & MAX16065_CURR_ENABLE) { val 570 drivers/hwmon/max16065.c data->curr_gain = 6 << ((val >> 2) & 0x03); val 572 drivers/hwmon/max16065.c = max16065_csp_adc_range[(val >> 1) & 0x01]; val 55 drivers/hwmon/max1619.c static int temp_from_reg(int val) val 57 drivers/hwmon/max1619.c return (val & 0x80 ? val-0x100 : val) * 1000; val 60 drivers/hwmon/max1619.c static int temp_to_reg(int val) val 62 drivers/hwmon/max1619.c return (val < 0 ? val+0x100*1000 : val) / 1000; val 155 drivers/hwmon/max1619.c long val; val 156 drivers/hwmon/max1619.c int err = kstrtol(buf, 10, &val); val 161 drivers/hwmon/max1619.c data->temp[attr->index] = temp_to_reg(val); val 76 drivers/hwmon/max1668.c s32 val; val 86 drivers/hwmon/max1668.c val = i2c_smbus_read_byte_data(client, MAX1668_REG_TEMP(i)); val 87 drivers/hwmon/max1668.c if (unlikely(val < 0)) { val 88 drivers/hwmon/max1668.c ret = ERR_PTR(val); val 91 drivers/hwmon/max1668.c data->temp[i] = (s8) val; val 93 drivers/hwmon/max1668.c val = i2c_smbus_read_byte_data(client, MAX1668_REG_LIMH_RD(i)); val 94 drivers/hwmon/max1668.c if (unlikely(val < 0)) { val 95 drivers/hwmon/max1668.c ret = ERR_PTR(val); val 98 drivers/hwmon/max1668.c data->temp_max[i] = (s8) val; val 100 drivers/hwmon/max1668.c val = i2c_smbus_read_byte_data(client, MAX1668_REG_LIML_RD(i)); val 101 drivers/hwmon/max1668.c if (unlikely(val < 0)) { val 102 drivers/hwmon/max1668.c ret = ERR_PTR(val); val 105 drivers/hwmon/max1668.c data->temp_min[i] = (s8) val; val 108 drivers/hwmon/max1668.c val = i2c_smbus_read_byte_data(client, MAX1668_REG_STAT1); val 109 drivers/hwmon/max1668.c if (unlikely(val < 0)) { val 110 drivers/hwmon/max1668.c ret = ERR_PTR(val); val 113 drivers/hwmon/max1668.c data->alarms = val << 8; val 115 drivers/hwmon/max1668.c val = i2c_smbus_read_byte_data(client, MAX1668_REG_STAT2); val 116 drivers/hwmon/max1668.c if (unlikely(val < 0)) { val 117 drivers/hwmon/max1668.c ret = ERR_PTR(val); val 120 drivers/hwmon/max1668.c data->alarms |= val; val 163 drivers/hwmon/max31790.c long *val) val 175 drivers/hwmon/max31790.c *val = rpm; val 180 drivers/hwmon/max31790.c *val = rpm; val 183 drivers/hwmon/max31790.c *val = !!(data->fault_status & (1 << channel)); val 191 drivers/hwmon/max31790.c long val) val 204 drivers/hwmon/max31790.c val = clamp_val(val, FAN_RPM_MIN, FAN_RPM_MAX); val 205 drivers/hwmon/max31790.c bits = bits_for_tach_period(val); val 217 drivers/hwmon/max31790.c target_count = RPM_TO_REG(val, sr); val 259 drivers/hwmon/max31790.c long *val) val 271 drivers/hwmon/max31790.c *val = data->pwm[channel] >> 8; val 275 drivers/hwmon/max31790.c *val = 2; val 277 drivers/hwmon/max31790.c *val = 1; val 279 drivers/hwmon/max31790.c *val = 0; val 287 drivers/hwmon/max31790.c long val) val 298 drivers/hwmon/max31790.c if (val < 0 || val > 255) { val 302 drivers/hwmon/max31790.c data->pwm[channel] = val << 8; val 309 drivers/hwmon/max31790.c if (val == 0) { val 312 drivers/hwmon/max31790.c } else if (val == 1) { val 316 drivers/hwmon/max31790.c } else if (val == 2) { val 355 drivers/hwmon/max31790.c u32 attr, int channel, long *val) val 359 drivers/hwmon/max31790.c return max31790_read_fan(dev, attr, channel, val); val 361 drivers/hwmon/max31790.c return max31790_read_pwm(dev, attr, channel, val); val 368 drivers/hwmon/max31790.c u32 attr, int channel, long val) val 372 drivers/hwmon/max31790.c return max31790_write_fan(dev, attr, channel, val); val 374 drivers/hwmon/max31790.c return max31790_write_pwm(dev, attr, channel, val); val 133 drivers/hwmon/max6621.c static long max6621_temp_mc2reg(long val) val 135 drivers/hwmon/max6621.c return (val / 1000L) << MAX6621_REG_TEMP_SHIFT; val 202 drivers/hwmon/max6621.c int channel, long *val) val 229 drivers/hwmon/max6621.c *val = temp * 1000L; val 242 drivers/hwmon/max6621.c *val = (regval >> MAX6621_REG_TEMP_SHIFT) * val 257 drivers/hwmon/max6621.c *val = regval * 1000L; val 267 drivers/hwmon/max6621.c *val = 0; val 294 drivers/hwmon/max6621.c *val = !!regval; val 311 drivers/hwmon/max6621.c int channel, long val) val 321 drivers/hwmon/max6621.c val = clamp_val(val, MAX6621_TEMP_INPUT_MIN, val 323 drivers/hwmon/max6621.c val = max6621_temp_mc2reg(val); val 326 drivers/hwmon/max6621.c MAX6621_CONFIG2_REG, val); val 331 drivers/hwmon/max6621.c val = clamp_val(val, MAX6621_TEMP_INPUT_MIN, val 333 drivers/hwmon/max6621.c val = val / 1000L; val 335 drivers/hwmon/max6621.c return regmap_write(data->regmap, reg, val); val 62 drivers/hwmon/max6639.c #define FAN_FROM_REG(val, rpm_range) ((val) == 0 || (val) == 255 ? \ val 63 drivers/hwmon/max6639.c 0 : (rpm_ranges[rpm_range] * 30) / (val)) val 64 drivers/hwmon/max6639.c #define TEMP_LIMIT_TO_REG(val) clamp_val((val) / 1000, 0, 255) val 194 drivers/hwmon/max6639.c unsigned long val; val 197 drivers/hwmon/max6639.c res = kstrtoul(buf, 10, &val); val 202 drivers/hwmon/max6639.c data->temp_therm[attr->index] = TEMP_LIMIT_TO_REG(val); val 226 drivers/hwmon/max6639.c unsigned long val; val 229 drivers/hwmon/max6639.c res = kstrtoul(buf, 10, &val); val 234 drivers/hwmon/max6639.c data->temp_alert[attr->index] = TEMP_LIMIT_TO_REG(val); val 259 drivers/hwmon/max6639.c unsigned long val; val 262 drivers/hwmon/max6639.c res = kstrtoul(buf, 10, &val); val 267 drivers/hwmon/max6639.c data->temp_ot[attr->index] = TEMP_LIMIT_TO_REG(val); val 291 drivers/hwmon/max6639.c unsigned long val; val 294 drivers/hwmon/max6639.c res = kstrtoul(buf, 10, &val); val 298 drivers/hwmon/max6639.c val = clamp_val(val, 0, 255); val 301 drivers/hwmon/max6639.c data->pwm[attr->index] = (u8)(val * 120 / 255); val 57 drivers/hwmon/max6642.c static int temp_from_reg10(int val) val 59 drivers/hwmon/max6642.c return val * 250; val 62 drivers/hwmon/max6642.c static int temp_from_reg(int val) val 64 drivers/hwmon/max6642.c return val * 1000; val 67 drivers/hwmon/max6642.c static int temp_to_reg(int val) val 69 drivers/hwmon/max6642.c return val / 1000; val 160 drivers/hwmon/max6642.c u16 val, tmp; val 166 drivers/hwmon/max6642.c val = i2c_smbus_read_byte_data(client, val 168 drivers/hwmon/max6642.c tmp = (val >> 6) & 3; val 169 drivers/hwmon/max6642.c val = i2c_smbus_read_byte_data(client, val 171 drivers/hwmon/max6642.c val = (val << 2) | tmp; val 172 drivers/hwmon/max6642.c data->temp_input[0] = val; val 173 drivers/hwmon/max6642.c val = i2c_smbus_read_byte_data(client, val 175 drivers/hwmon/max6642.c tmp = (val >> 6) & 3; val 176 drivers/hwmon/max6642.c val = i2c_smbus_read_byte_data(client, val 178 drivers/hwmon/max6642.c val = (val << 2) | tmp; val 179 drivers/hwmon/max6642.c data->temp_input[1] = val; val 221 drivers/hwmon/max6642.c unsigned long val; val 224 drivers/hwmon/max6642.c err = kstrtoul(buf, 10, &val); val 229 drivers/hwmon/max6642.c data->temp_high[attr2->nr] = clamp_val(temp_to_reg(val), 0, 255); val 520 drivers/hwmon/max6650.c u32 attr, int channel, long *val) val 532 drivers/hwmon/max6650.c *val = dac_to_pwm(data->dac, val 546 drivers/hwmon/max6650.c *val = (4 - mode) & 3; /* {0 1 2 3} -> {0 3 2 1} */ val 563 drivers/hwmon/max6650.c *val = DIV_ROUND_CLOSEST(data->tach[channel] * 120, val 567 drivers/hwmon/max6650.c *val = DIV_FROM_REG(data->count); val 575 drivers/hwmon/max6650.c *val = 60 * DIV_FROM_REG(data->config) * clock / val 579 drivers/hwmon/max6650.c *val = !!(data->alarm & MAX6650_ALRM_MIN); val 584 drivers/hwmon/max6650.c *val = !!(data->alarm & MAX6650_ALRM_MAX); val 589 drivers/hwmon/max6650.c *val = !!(data->alarm & MAX6650_ALRM_TACH); val 611 drivers/hwmon/max6650.c u32 attr, int channel, long val) val 623 drivers/hwmon/max6650.c reg = pwm_to_dac(clamp_val(val, 0, 255), val 632 drivers/hwmon/max6650.c if (val < 0 || val >= ARRAY_SIZE(max6650_pwm_modes)) { val 637 drivers/hwmon/max6650.c max6650_pwm_modes[val]); val 647 drivers/hwmon/max6650.c switch (val) { val 671 drivers/hwmon/max6650.c if (val < 0) { val 675 drivers/hwmon/max6650.c ret = max6650_set_target(data, val); val 179 drivers/hwmon/max6697.c int val; val 192 drivers/hwmon/max6697.c val = i2c_smbus_read_byte_data(client, val 194 drivers/hwmon/max6697.c if (unlikely(val < 0)) { val 195 drivers/hwmon/max6697.c ret = ERR_PTR(val); val 198 drivers/hwmon/max6697.c data->temp[i][MAX6697_TEMP_EXT] = val; val 201 drivers/hwmon/max6697.c val = i2c_smbus_read_byte_data(client, MAX6697_REG_TEMP[i]); val 202 drivers/hwmon/max6697.c if (unlikely(val < 0)) { val 203 drivers/hwmon/max6697.c ret = ERR_PTR(val); val 206 drivers/hwmon/max6697.c data->temp[i][MAX6697_TEMP_INPUT] = val; val 208 drivers/hwmon/max6697.c val = i2c_smbus_read_byte_data(client, MAX6697_REG_MAX[i]); val 209 drivers/hwmon/max6697.c if (unlikely(val < 0)) { val 210 drivers/hwmon/max6697.c ret = ERR_PTR(val); val 213 drivers/hwmon/max6697.c data->temp[i][MAX6697_TEMP_MAX] = val; val 216 drivers/hwmon/max6697.c val = i2c_smbus_read_byte_data(client, val 218 drivers/hwmon/max6697.c if (unlikely(val < 0)) { val 219 drivers/hwmon/max6697.c ret = ERR_PTR(val); val 222 drivers/hwmon/max6697.c data->temp[i][MAX6697_TEMP_CRIT] = val; val 228 drivers/hwmon/max6697.c val = i2c_smbus_read_byte_data(client, MAX6697_REG_STAT(i)); val 229 drivers/hwmon/max6697.c if (unlikely(val < 0)) { val 230 drivers/hwmon/max6697.c ret = ERR_PTR(val); val 233 drivers/hwmon/max6697.c alarms = (alarms << 8) | val; val 41 drivers/hwmon/mc13783-adc.c struct device_attribute *devattr, unsigned int *val) val 61 drivers/hwmon/mc13783-adc.c *val = (sample[channel % 4] >> (channel > 3 ? 14 : 2)) & 0x3ff; val 70 drivers/hwmon/mc13783-adc.c unsigned val; val 73 drivers/hwmon/mc13783-adc.c int ret = mc13783_adc_read(dev, devattr, &val); val 79 drivers/hwmon/mc13783-adc.c val = DIV_ROUND_CLOSEST(val * 9, 2); val 85 drivers/hwmon/mc13783-adc.c val = DIV_ROUND_CLOSEST(val * 9, 4) + 2400; val 87 drivers/hwmon/mc13783-adc.c return sprintf(buf, "%u\n", val); val 94 drivers/hwmon/mc13783-adc.c unsigned val; val 95 drivers/hwmon/mc13783-adc.c int ret = mc13783_adc_read(dev, devattr, &val); val 104 drivers/hwmon/mc13783-adc.c val = DIV_ROUND_CLOSEST(val * 9, 4); val 106 drivers/hwmon/mc13783-adc.c return sprintf(buf, "%u\n", val); val 113 drivers/hwmon/mc13783-adc.c unsigned int val; val 116 drivers/hwmon/mc13783-adc.c int ret = mc13783_adc_read(dev, devattr, &val); val 123 drivers/hwmon/mc13783-adc.c val = DIV_ROUND_CLOSEST(val * 4800, 1024); val 126 drivers/hwmon/mc13783-adc.c val = DIV_ROUND_CLOSEST(val * 2555, 1024); val 128 drivers/hwmon/mc13783-adc.c return sprintf(buf, "%u\n", val); val 135 drivers/hwmon/mc13783-adc.c unsigned int val; val 138 drivers/hwmon/mc13783-adc.c int ret = mc13783_adc_read(dev, devattr, &val); val 149 drivers/hwmon/mc13783-adc.c ret = DIV_ROUND_CLOSEST(-2635920 + val * 4244, 10); val 156 drivers/hwmon/mc13783-adc.c ret = 346480 - 1140 * val; val 80 drivers/hwmon/mcp3021.c static inline u16 volts_from_reg(struct mcp3021_data *data, u16 val) val 82 drivers/hwmon/mcp3021.c return DIV_ROUND_CLOSEST(data->vdd * val, 1 << data->output_res); val 55 drivers/hwmon/menf21bmc_hwmon.c int val; val 62 drivers/hwmon/menf21bmc_hwmon.c val = i2c_smbus_read_word_data(drv_data->i2c_client, val 64 drivers/hwmon/menf21bmc_hwmon.c if (val < 0) { val 65 drivers/hwmon/menf21bmc_hwmon.c data_ret = ERR_PTR(val); val 68 drivers/hwmon/menf21bmc_hwmon.c drv_data->in_val[i] = val; val 79 drivers/hwmon/menf21bmc_hwmon.c int i, val; val 82 drivers/hwmon/menf21bmc_hwmon.c val = i2c_smbus_read_word_data(drv_data->i2c_client, val 84 drivers/hwmon/menf21bmc_hwmon.c if (val < 0) val 85 drivers/hwmon/menf21bmc_hwmon.c return val; val 87 drivers/hwmon/menf21bmc_hwmon.c drv_data->in_min[i] = val; val 89 drivers/hwmon/menf21bmc_hwmon.c val = i2c_smbus_read_word_data(drv_data->i2c_client, val 91 drivers/hwmon/menf21bmc_hwmon.c if (val < 0) val 92 drivers/hwmon/menf21bmc_hwmon.c return val; val 94 drivers/hwmon/menf21bmc_hwmon.c drv_data->in_max[i] = val; val 56 drivers/hwmon/mlxreg-fan.c #define MLXREG_FAN_GET_FAULT(val, mask) ((val) == (mask)) val 114 drivers/hwmon/mlxreg-fan.c int channel, long *val) val 130 drivers/hwmon/mlxreg-fan.c *val = MLXREG_FAN_GET_RPM(regval, fan->divider, val 139 drivers/hwmon/mlxreg-fan.c *val = MLXREG_FAN_GET_FAULT(regval, tacho->mask); val 154 drivers/hwmon/mlxreg-fan.c *val = regval; val 171 drivers/hwmon/mlxreg-fan.c int channel, long val) val 179 drivers/hwmon/mlxreg-fan.c if (val < MLXREG_FAN_MIN_DUTY || val 180 drivers/hwmon/mlxreg-fan.c val > MLXREG_FAN_MAX_DUTY) val 182 drivers/hwmon/mlxreg-fan.c return regmap_write(fan->regmap, fan->pwm.reg, val); val 69 drivers/hwmon/nct6683.c superio_outb(int ioreg, int reg, int val) val 72 drivers/hwmon/nct6683.c outb(val, ioreg + 1); val 485 drivers/hwmon/nct6683.c static inline u16 in_to_reg(u32 val, u8 src) val 493 drivers/hwmon/nct6683.c return clamp_val(DIV_ROUND_CLOSEST(val, scale), 0, 127); val 927 drivers/hwmon/nct6683.c unsigned long val; val 929 drivers/hwmon/nct6683.c if (kstrtoul(buf, 10, &val) || val > 255) val 935 drivers/hwmon/nct6683.c nct6683_write(data, NCT6683_REG_PWM_WRITE(index), val); val 1002 drivers/hwmon/nct6683.c unsigned long val; val 1006 drivers/hwmon/nct6683.c if (kstrtoul(buf, 10, &val) || (val != 0 && val != 1)) val 1019 drivers/hwmon/nct6683.c if (val) val 1063 drivers/hwmon/nct6683.c unsigned long val; val 1067 drivers/hwmon/nct6683.c if (kstrtoul(buf, 10, &val) || val != 0) val 1341 drivers/hwmon/nct6683.c u16 val; val 1348 drivers/hwmon/nct6683.c val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) val 1351 drivers/hwmon/nct6683.c switch (val & SIO_ID_MASK) { val 1356 drivers/hwmon/nct6683.c if (val != 0xffff) val 1357 drivers/hwmon/nct6683.c pr_debug("unsupported chip ID: 0x%04x\n", val); val 1363 drivers/hwmon/nct6683.c val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8) val 1365 drivers/hwmon/nct6683.c addr = val & IOREGION_ALIGNMENT; val 1372 drivers/hwmon/nct6683.c val = superio_inb(sioaddr, SIO_REG_ENABLE); val 1373 drivers/hwmon/nct6683.c if (!(val & 0x01)) { val 1375 drivers/hwmon/nct6683.c superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01); val 137 drivers/hwmon/nct6775.c superio_outb(int ioreg, int reg, int val) val 140 drivers/hwmon/nct6775.c outb(val, ioreg + 1); val 1060 drivers/hwmon/nct6775.c static inline u8 in_to_reg(u32 val, u8 nr) val 1062 drivers/hwmon/nct6775.c return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255); val 1889 drivers/hwmon/nct6775.c unsigned long val; val 1892 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 1896 drivers/hwmon/nct6775.c data->in[nr][index] = in_to_reg(val, nr); val 1970 drivers/hwmon/nct6775.c unsigned long val; val 1973 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 1976 drivers/hwmon/nct6775.c if (val > 1) val 1980 drivers/hwmon/nct6775.c if (val) val 2019 drivers/hwmon/nct6775.c unsigned long val; val 2022 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2025 drivers/hwmon/nct6775.c if (val > 1) val 2036 drivers/hwmon/nct6775.c if (val) val 2127 drivers/hwmon/nct6775.c unsigned long val; val 2132 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2139 drivers/hwmon/nct6775.c if (!val) { val 2140 drivers/hwmon/nct6775.c val = 0xff1f; val 2142 drivers/hwmon/nct6775.c if (val > 1350000U) val 2143 drivers/hwmon/nct6775.c val = 135000U; val 2144 drivers/hwmon/nct6775.c val = 1350000U / val; val 2145 drivers/hwmon/nct6775.c val = (val & 0x1f) | ((val << 3) & 0xff00); val 2147 drivers/hwmon/nct6775.c data->fan_min[nr] = val; val 2150 drivers/hwmon/nct6775.c if (!val) { val 2157 drivers/hwmon/nct6775.c reg = 1350000U / val; val 2167 drivers/hwmon/nct6775.c nr + 1, val, data->fan_from_reg_min(254, 7)); val 2177 drivers/hwmon/nct6775.c nr + 1, val, data->fan_from_reg_min(1, 0)); val 2231 drivers/hwmon/nct6775.c unsigned long val; val 2235 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2239 drivers/hwmon/nct6775.c if (val > 4) val 2243 drivers/hwmon/nct6775.c data->fan_pulses[nr] = val & 3; val 2246 drivers/hwmon/nct6775.c reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr]; val 2340 drivers/hwmon/nct6775.c long val; val 2342 drivers/hwmon/nct6775.c err = kstrtol(buf, 10, &val); val 2347 drivers/hwmon/nct6775.c data->temp[index][nr] = LM75_TEMP_TO_REG(val); val 2370 drivers/hwmon/nct6775.c long val; val 2373 drivers/hwmon/nct6775.c err = kstrtol(buf, 10, &val); val 2377 drivers/hwmon/nct6775.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127); val 2380 drivers/hwmon/nct6775.c data->temp_offset[nr] = val; val 2381 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val); val 2404 drivers/hwmon/nct6775.c unsigned long val; val 2408 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2412 drivers/hwmon/nct6775.c if (val != 1 && val != 3 && val != 4) val 2417 drivers/hwmon/nct6775.c data->temp_type[nr] = val; val 2422 drivers/hwmon/nct6775.c switch (val) { val 2538 drivers/hwmon/nct6775.c unsigned long val; val 2542 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2546 drivers/hwmon/nct6775.c if (val > 1) val 2551 drivers/hwmon/nct6775.c if (!val) val 2557 drivers/hwmon/nct6775.c data->pwm_mode[nr] = val; val 2560 drivers/hwmon/nct6775.c if (!val) val 2596 drivers/hwmon/nct6775.c unsigned long val; val 2603 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2606 drivers/hwmon/nct6775.c val = clamp_val(val, minval[index], maxval[index]); val 2609 drivers/hwmon/nct6775.c data->pwm[index][nr] = val; val 2610 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_PWM[index][nr], val); val 2614 drivers/hwmon/nct6775.c if (val) val 2698 drivers/hwmon/nct6775.c unsigned long val; val 2702 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2706 drivers/hwmon/nct6775.c if (val > sf4) val 2709 drivers/hwmon/nct6775.c if (val == sf3 && data->kind != nct6775) val 2712 drivers/hwmon/nct6775.c if (val == sf4 && check_trip_points(data, nr)) { val 2719 drivers/hwmon/nct6775.c data->pwm_enable[nr] = val; val 2720 drivers/hwmon/nct6775.c if (val == off) { val 2730 drivers/hwmon/nct6775.c reg |= pwm_enable_to_reg(val) << 4; val 2770 drivers/hwmon/nct6775.c unsigned long val; val 2773 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2776 drivers/hwmon/nct6775.c if (val == 0 || val > NUM_TEMP) val 2778 drivers/hwmon/nct6775.c if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1]) val 2782 drivers/hwmon/nct6775.c src = data->temp_src[val - 1]; val 2812 drivers/hwmon/nct6775.c unsigned long val; val 2815 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2818 drivers/hwmon/nct6775.c if (val > NUM_TEMP) val 2820 drivers/hwmon/nct6775.c val = array_index_nospec(val, NUM_TEMP + 1); val 2821 drivers/hwmon/nct6775.c if (val && (!(data->have_temp & BIT(val - 1)) || val 2822 drivers/hwmon/nct6775.c !data->temp_src[val - 1])) val 2826 drivers/hwmon/nct6775.c if (val) { val 2827 drivers/hwmon/nct6775.c src = data->temp_src[val - 1]; val 2860 drivers/hwmon/nct6775.c unsigned long val; val 2863 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2867 drivers/hwmon/nct6775.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, val 2871 drivers/hwmon/nct6775.c data->target_temp[nr] = val; val 2896 drivers/hwmon/nct6775.c unsigned long val; val 2900 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2904 drivers/hwmon/nct6775.c val = clamp_val(val, 0, 1350000U); val 2905 drivers/hwmon/nct6775.c speed = fan_to_reg(val, data->fan_div[nr]); val 2934 drivers/hwmon/nct6775.c unsigned long val; val 2937 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 2942 drivers/hwmon/nct6775.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask); val 2945 drivers/hwmon/nct6775.c data->temp_tolerance[index][nr] = val; val 2951 drivers/hwmon/nct6775.c val); val 2998 drivers/hwmon/nct6775.c unsigned long val; val 3002 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 3007 drivers/hwmon/nct6775.c data->fan_div[nr]) + val; val 3009 drivers/hwmon/nct6775.c data->fan_div[nr]) - val; val 3015 drivers/hwmon/nct6775.c val = (fan_to_reg(low, data->fan_div[nr]) - val 3019 drivers/hwmon/nct6775.c val = clamp_val(val, 0, data->speed_tolerance_limit); val 3022 drivers/hwmon/nct6775.c data->target_speed_tolerance[nr] = val; val 3063 drivers/hwmon/nct6775.c unsigned long val; val 3066 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 3070 drivers/hwmon/nct6775.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255); val 3073 drivers/hwmon/nct6775.c data->weight_temp[index][nr] = val; val 3074 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val); val 3113 drivers/hwmon/nct6775.c unsigned long val; val 3116 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 3120 drivers/hwmon/nct6775.c val = step_time_to_reg(val, data->pwm_mode[nr]); val 3122 drivers/hwmon/nct6775.c data->fan_time[index][nr] = val; val 3123 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val); val 3145 drivers/hwmon/nct6775.c unsigned long val; val 3149 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 3152 drivers/hwmon/nct6775.c if (val > 255) val 3156 drivers/hwmon/nct6775.c if (data->kind != nct6775 && !val) val 3158 drivers/hwmon/nct6775.c if (data->kind != nct6779 && val) val 3159 drivers/hwmon/nct6775.c val = 0xff; val 3163 drivers/hwmon/nct6775.c data->auto_pwm[nr][point] = val; val 3174 drivers/hwmon/nct6775.c if (val) val 3194 drivers/hwmon/nct6775.c val); val 3197 drivers/hwmon/nct6775.c if (val == 255) val 3234 drivers/hwmon/nct6775.c unsigned long val; val 3237 drivers/hwmon/nct6775.c err = kstrtoul(buf, 10, &val); val 3240 drivers/hwmon/nct6775.c if (val > 255000) val 3244 drivers/hwmon/nct6775.c data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000); val 3414 drivers/hwmon/nct6775.c unsigned long val; val 3418 drivers/hwmon/nct6775.c if (kstrtoul(buf, 10, &val) || val != 0) val 4618 drivers/hwmon/nct6775.c int val; val 4620 drivers/hwmon/nct6775.c val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE); val 4621 drivers/hwmon/nct6775.c if (val & 0x10) { val 4624 drivers/hwmon/nct6775.c val & ~0x10); val 4727 drivers/hwmon/nct6775.c u16 val; val 4735 drivers/hwmon/nct6775.c val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) | val 4737 drivers/hwmon/nct6775.c if (force_id && val != 0xffff) val 4738 drivers/hwmon/nct6775.c val = force_id; val 4740 drivers/hwmon/nct6775.c switch (val & SIO_ID_MASK) { val 4778 drivers/hwmon/nct6775.c if (val != 0xffff) val 4779 drivers/hwmon/nct6775.c pr_debug("unsupported chip ID: 0x%04x\n", val); val 4786 drivers/hwmon/nct6775.c val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8) val 4788 drivers/hwmon/nct6775.c addr = val & IOREGION_ALIGNMENT; val 4796 drivers/hwmon/nct6775.c val = superio_inb(sioaddr, SIO_REG_ENABLE); val 4797 drivers/hwmon/nct6775.c if (!(val & 0x01)) { val 4799 drivers/hwmon/nct6775.c superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01); val 124 drivers/hwmon/nct7802.c unsigned int val; val 130 drivers/hwmon/nct7802.c ret = regmap_read(data->regmap, attr->index, &val); val 134 drivers/hwmon/nct7802.c return sprintf(buf, "%d\n", val); val 143 drivers/hwmon/nct7802.c u8 val; val 145 drivers/hwmon/nct7802.c err = kstrtou8(buf, 0, &val); val 149 drivers/hwmon/nct7802.c err = regmap_write(data->regmap, attr->index, val); val 174 drivers/hwmon/nct7802.c u8 val; val 177 drivers/hwmon/nct7802.c ret = kstrtou8(buf, 0, &val); val 180 drivers/hwmon/nct7802.c if (val < 1 || val > 2) val 184 drivers/hwmon/nct7802.c (val - 1) << SMARTFAN_EN_SHIFT(sattr->index)); val 362 drivers/hwmon/nct7802.c unsigned long val; val 365 drivers/hwmon/nct7802.c err = kstrtoul(buf, 10, &val); val 369 drivers/hwmon/nct7802.c err = nct7802_write_voltage(data, nr, index, val); val 379 drivers/hwmon/nct7802.c unsigned int val; val 395 drivers/hwmon/nct7802.c ret = regmap_read(data->regmap, 0x1e, &val); /* SMI Voltage status */ val 400 drivers/hwmon/nct7802.c data->in_status &= ~((val & 0x0f) << 4); val 453 drivers/hwmon/nct7802.c long val; val 456 drivers/hwmon/nct7802.c err = kstrtol(buf, 10, &val); val 460 drivers/hwmon/nct7802.c val = DIV_ROUND_CLOSEST(clamp_val(val, -128000, 127000), 1000); val 462 drivers/hwmon/nct7802.c err = regmap_write(data->regmap, nr, val & 0xff); val 500 drivers/hwmon/nct7802.c unsigned long val; val 503 drivers/hwmon/nct7802.c err = kstrtoul(buf, 10, &val); val 507 drivers/hwmon/nct7802.c err = nct7802_write_fan_min(data, sattr->nr, sattr->index, val); val 517 drivers/hwmon/nct7802.c unsigned int val; val 520 drivers/hwmon/nct7802.c ret = regmap_read(data->regmap, sattr->nr, &val); val 524 drivers/hwmon/nct7802.c return sprintf(buf, "%u\n", !!(val & (1 << bit))); val 548 drivers/hwmon/nct7802.c unsigned long val; val 551 drivers/hwmon/nct7802.c err = kstrtoul(buf, 10, &val); val 554 drivers/hwmon/nct7802.c if (val > 1) val 558 drivers/hwmon/nct7802.c val ? 1 << sattr->index : 0); val 173 drivers/hwmon/nct7904.c unsigned int bank, unsigned int reg, u8 val) val 180 drivers/hwmon/nct7904.c ret = i2c_smbus_write_byte_data(client, reg, val); val 187 drivers/hwmon/nct7904.c long *val) val 204 drivers/hwmon/nct7904.c *val = rpm; val 216 drivers/hwmon/nct7904.c *val = rpm; val 228 drivers/hwmon/nct7904.c *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1; val 230 drivers/hwmon/nct7904.c if (*val) val 266 drivers/hwmon/nct7904.c long *val) val 284 drivers/hwmon/nct7904.c *val = volt; val 296 drivers/hwmon/nct7904.c *val = volt; val 308 drivers/hwmon/nct7904.c *val = volt; val 320 drivers/hwmon/nct7904.c *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1; val 322 drivers/hwmon/nct7904.c if (*val) val 354 drivers/hwmon/nct7904.c long *val) val 375 drivers/hwmon/nct7904.c *val = sign_extend32(temp, 10) * 125; val 383 drivers/hwmon/nct7904.c *val = (ret >> 1) & 1; val 389 drivers/hwmon/nct7904.c *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1; val 397 drivers/hwmon/nct7904.c *val = (ret >> ((channel - 5) & 0x07)) & 1; val 404 drivers/hwmon/nct7904.c *val = (ret >> (((channel - 5) & 0x07) - 4)) val 413 drivers/hwmon/nct7904.c *val = 3; /* TD */ val 415 drivers/hwmon/nct7904.c *val = 4; /* TR */ val 417 drivers/hwmon/nct7904.c *val = 0; val 422 drivers/hwmon/nct7904.c *val = 5; /* TSI */ val 424 drivers/hwmon/nct7904.c *val = 6; /* PECI */ val 426 drivers/hwmon/nct7904.c *val = 0; val 466 drivers/hwmon/nct7904.c *val = temps * 1000; val 506 drivers/hwmon/nct7904.c long *val) val 516 drivers/hwmon/nct7904.c *val = ret; val 523 drivers/hwmon/nct7904.c *val = ret ? 2 : 1; val 531 drivers/hwmon/nct7904.c long val) val 537 drivers/hwmon/nct7904.c val = clamp_val(val / 1000, -128, 127); val 564 drivers/hwmon/nct7904.c ret = nct7904_write_reg(data, BANK_1, reg1, val); val 567 drivers/hwmon/nct7904.c reg2 + channel * 8, val); val 570 drivers/hwmon/nct7904.c reg3 + (channel - 5) * 4, val); val 576 drivers/hwmon/nct7904.c long val) val 584 drivers/hwmon/nct7904.c if (val <= 0) val 587 drivers/hwmon/nct7904.c val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff); val 588 drivers/hwmon/nct7904.c tmp = (val >> 5) & 0xff; val 593 drivers/hwmon/nct7904.c tmp = val & 0x1f; val 603 drivers/hwmon/nct7904.c long val) val 611 drivers/hwmon/nct7904.c val = val / 2; /* 0.002V scale */ val 613 drivers/hwmon/nct7904.c val = val / 6; /* 0.006V scale */ val 615 drivers/hwmon/nct7904.c val = clamp_val(val, 0, 0x7ff); val 624 drivers/hwmon/nct7904.c tmp |= val & 0x7; val 633 drivers/hwmon/nct7904.c tmp = (val >> 3) & 0xff; val 643 drivers/hwmon/nct7904.c tmp |= val & 0x7; val 652 drivers/hwmon/nct7904.c tmp = (val >> 3) & 0xff; val 662 drivers/hwmon/nct7904.c long val) val 669 drivers/hwmon/nct7904.c if (val < 0 || val > 255) val 672 drivers/hwmon/nct7904.c val); val 675 drivers/hwmon/nct7904.c if (val < 1 || val > 2 || val 676 drivers/hwmon/nct7904.c (val == 2 && !data->fan_mode[channel])) val 679 drivers/hwmon/nct7904.c val == 2 ? data->fan_mode[channel] : 0); val 698 drivers/hwmon/nct7904.c u32 attr, int channel, long *val) val 702 drivers/hwmon/nct7904.c return nct7904_read_in(dev, attr, channel, val); val 704 drivers/hwmon/nct7904.c return nct7904_read_fan(dev, attr, channel, val); val 706 drivers/hwmon/nct7904.c return nct7904_read_pwm(dev, attr, channel, val); val 708 drivers/hwmon/nct7904.c return nct7904_read_temp(dev, attr, channel, val); val 715 drivers/hwmon/nct7904.c u32 attr, int channel, long val) val 719 drivers/hwmon/nct7904.c return nct7904_write_in(dev, attr, channel, val); val 721 drivers/hwmon/nct7904.c return nct7904_write_fan(dev, attr, channel, val); val 723 drivers/hwmon/nct7904.c return nct7904_write_pwm(dev, attr, channel, val); val 725 drivers/hwmon/nct7904.c return nct7904_write_temp(dev, attr, channel, val); val 881 drivers/hwmon/nct7904.c u8 val, bit; val 942 drivers/hwmon/nct7904.c val = (ret >> (i * 2)) & 0x03; val 944 drivers/hwmon/nct7904.c if (val == VOLT_MONITOR_MODE) { val 946 drivers/hwmon/nct7904.c } else if (val == THERMAL_DIODE_MODE && i < 2) { val 949 drivers/hwmon/nct7904.c } else if (val == THERMISTOR_MODE) { val 211 drivers/hwmon/npcm750-pwm-fan.c int channel, u16 val) val 223 drivers/hwmon/npcm750-pwm-fan.c iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch)); val 248 drivers/hwmon/npcm750-pwm-fan.c if (val == 0) { val 505 drivers/hwmon/npcm750-pwm-fan.c long *val) val 513 drivers/hwmon/npcm750-pwm-fan.c *val = ioread32 val 522 drivers/hwmon/npcm750-pwm-fan.c long val) val 529 drivers/hwmon/npcm750-pwm-fan.c if (val < 0 || val > NPCM7XX_PWM_CMR_MAX) val 531 drivers/hwmon/npcm750-pwm-fan.c err = npcm7xx_pwm_config_set(data, channel, (u16)val); val 557 drivers/hwmon/npcm750-pwm-fan.c long *val) val 563 drivers/hwmon/npcm750-pwm-fan.c *val = 0; val 570 drivers/hwmon/npcm750-pwm-fan.c *val = ((data->input_clk_freq * 60) / val 595 drivers/hwmon/npcm750-pwm-fan.c u32 attr, int channel, long *val) val 599 drivers/hwmon/npcm750-pwm-fan.c return npcm7xx_read_pwm(dev, attr, channel, val); val 601 drivers/hwmon/npcm750-pwm-fan.c return npcm7xx_read_fan(dev, attr, channel, val); val 608 drivers/hwmon/npcm750-pwm-fan.c u32 attr, int channel, long val) val 612 drivers/hwmon/npcm750-pwm-fan.c return npcm7xx_write_pwm(dev, attr, channel, val); val 576 drivers/hwmon/ntc_thermistor.c u32 attr, int channel, long *val) val 588 drivers/hwmon/ntc_thermistor.c *val = get_temp_mc(data, ohm); val 591 drivers/hwmon/ntc_thermistor.c *val = 4; val 227 drivers/hwmon/occ/common.c u32 val = 0; val 241 drivers/hwmon/occ/common.c val = get_unaligned_be16(&temp->sensor_id); val 250 drivers/hwmon/occ/common.c val = get_unaligned_be16(&temp->value) * 1000; val 256 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%u\n", val); val 263 drivers/hwmon/occ/common.c u32 val = 0; val 277 drivers/hwmon/occ/common.c val = get_unaligned_be32(&temp->sensor_id); val 280 drivers/hwmon/occ/common.c val = temp->value; val 281 drivers/hwmon/occ/common.c if (val == OCC_TEMP_SENSOR_FAULT) val 291 drivers/hwmon/occ/common.c if (val == 0) val 294 drivers/hwmon/occ/common.c val *= 1000; val 298 drivers/hwmon/occ/common.c val = temp->fru_type; val 301 drivers/hwmon/occ/common.c val = temp->value == OCC_TEMP_SENSOR_FAULT; val 307 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%u\n", val); val 314 drivers/hwmon/occ/common.c u16 val = 0; val 328 drivers/hwmon/occ/common.c val = get_unaligned_be16(&freq->sensor_id); val 331 drivers/hwmon/occ/common.c val = get_unaligned_be16(&freq->value); val 337 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%u\n", val); val 344 drivers/hwmon/occ/common.c u32 val = 0; val 358 drivers/hwmon/occ/common.c val = get_unaligned_be32(&freq->sensor_id); val 361 drivers/hwmon/occ/common.c val = get_unaligned_be16(&freq->value); val 367 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%u\n", val); val 374 drivers/hwmon/occ/common.c u64 val = 0; val 388 drivers/hwmon/occ/common.c val = get_unaligned_be16(&power->sensor_id); val 391 drivers/hwmon/occ/common.c val = get_unaligned_be32(&power->accumulator) / val 393 drivers/hwmon/occ/common.c val *= 1000000ULL; val 396 drivers/hwmon/occ/common.c val = (u64)get_unaligned_be32(&power->update_tag) * val 400 drivers/hwmon/occ/common.c val = get_unaligned_be16(&power->value) * 1000000ULL; val 406 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%llu\n", val); val 421 drivers/hwmon/occ/common.c u64 val = 0; val 439 drivers/hwmon/occ/common.c val = occ_get_powr_avg(&power->accumulator, val 443 drivers/hwmon/occ/common.c val = (u64)get_unaligned_be32(&power->update_tag) * val 447 drivers/hwmon/occ/common.c val = get_unaligned_be16(&power->value) * 1000000ULL; val 453 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%llu\n", val); val 460 drivers/hwmon/occ/common.c u64 val = 0; val 477 drivers/hwmon/occ/common.c val = occ_get_powr_avg(&power->system.accumulator, val 481 drivers/hwmon/occ/common.c val = (u64)get_unaligned_be32(&power->system.update_tag) * val 485 drivers/hwmon/occ/common.c val = get_unaligned_be16(&power->system.value) * 1000000ULL; val 491 drivers/hwmon/occ/common.c val = occ_get_powr_avg(&power->proc.accumulator, val 495 drivers/hwmon/occ/common.c val = (u64)get_unaligned_be32(&power->proc.update_tag) * val 499 drivers/hwmon/occ/common.c val = get_unaligned_be16(&power->proc.value) * 1000000ULL; val 505 drivers/hwmon/occ/common.c val = occ_get_powr_avg(&power->vdd.accumulator, val 509 drivers/hwmon/occ/common.c val = (u64)get_unaligned_be32(&power->vdd.update_tag) * val 513 drivers/hwmon/occ/common.c val = get_unaligned_be16(&power->vdd.value) * 1000000ULL; val 519 drivers/hwmon/occ/common.c val = occ_get_powr_avg(&power->vdn.accumulator, val 523 drivers/hwmon/occ/common.c val = (u64)get_unaligned_be32(&power->vdn.update_tag) * val 527 drivers/hwmon/occ/common.c val = get_unaligned_be16(&power->vdn.value) * 1000000ULL; val 533 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%llu\n", val); val 540 drivers/hwmon/occ/common.c u64 val = 0; val 556 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->cap) * 1000000ULL; val 559 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->system_power) * 1000000ULL; val 562 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->n_cap) * 1000000ULL; val 565 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->max) * 1000000ULL; val 568 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->min) * 1000000ULL; val 571 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->user) * 1000000ULL; val 577 drivers/hwmon/occ/common.c val = caps->user_source; val 583 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%llu\n", val); val 590 drivers/hwmon/occ/common.c u64 val = 0; val 606 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->cap) * 1000000ULL; val 609 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->system_power) * 1000000ULL; val 612 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->n_cap) * 1000000ULL; val 615 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->max) * 1000000ULL; val 618 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->hard_min) * 1000000ULL; val 621 drivers/hwmon/occ/common.c val = get_unaligned_be16(&caps->user) * 1000000ULL; val 624 drivers/hwmon/occ/common.c val = caps->user_source; val 630 drivers/hwmon/occ/common.c return snprintf(buf, PAGE_SIZE - 1, "%llu\n", val); val 27 drivers/hwmon/occ/sysfs.c int val = 0; val 40 drivers/hwmon/occ/sysfs.c val = !!(header->status & OCC_STAT_MASTER); val 43 drivers/hwmon/occ/sysfs.c val = !!(header->status & OCC_STAT_ACTIVE); val 46 drivers/hwmon/occ/sysfs.c val = !!(header->ext_status & OCC_EXT_STAT_DVFS_OT); val 49 drivers/hwmon/occ/sysfs.c val = !!(header->ext_status & OCC_EXT_STAT_DVFS_POWER); val 52 drivers/hwmon/occ/sysfs.c val = !!(header->ext_status & OCC_EXT_STAT_MEM_THROTTLE); val 55 drivers/hwmon/occ/sysfs.c val = !!(header->ext_status & OCC_EXT_STAT_QUICK_DROP); val 58 drivers/hwmon/occ/sysfs.c val = header->occ_state; val 62 drivers/hwmon/occ/sysfs.c val = hweight8(header->occs_present); val 64 drivers/hwmon/occ/sysfs.c val = 1; val 70 drivers/hwmon/occ/sysfs.c return snprintf(buf, PAGE_SIZE - 1, "%d\n", val); val 75 drivers/hwmon/pc87360.c static inline void superio_outb(int sioaddr, int reg, int val) val 78 drivers/hwmon/pc87360.c outb(val, sioaddr + 1); val 112 drivers/hwmon/pc87360.c #define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : \ val 113 drivers/hwmon/pc87360.c 480000 / ((val) * (div))) val 114 drivers/hwmon/pc87360.c #define FAN_TO_REG(val, div) ((val) <= 100 ? 0 : \ val 115 drivers/hwmon/pc87360.c 480000 / ((val) * (div))) val 116 drivers/hwmon/pc87360.c #define FAN_DIV_FROM_REG(val) (1 << (((val) >> 5) & 0x03)) val 117 drivers/hwmon/pc87360.c #define FAN_STATUS_FROM_REG(val) ((val) & 0x07) val 119 drivers/hwmon/pc87360.c #define FAN_CONFIG_MONITOR(val, nr) (((val) >> (2 + (nr) * 3)) & 1) val 120 drivers/hwmon/pc87360.c #define FAN_CONFIG_CONTROL(val, nr) (((val) >> (3 + (nr) * 3)) & 1) val 121 drivers/hwmon/pc87360.c #define FAN_CONFIG_INVERT(val, nr) (((val) >> (4 + (nr) * 3)) & 1) val 123 drivers/hwmon/pc87360.c #define PWM_FROM_REG(val, inv) ((inv) ? 255 - (val) : (val)) val 124 drivers/hwmon/pc87360.c static inline u8 PWM_TO_REG(int val, int inv) val 127 drivers/hwmon/pc87360.c val = 255 - val; val 128 drivers/hwmon/pc87360.c if (val < 0) val 130 drivers/hwmon/pc87360.c if (val > 255) val 132 drivers/hwmon/pc87360.c return val; val 149 drivers/hwmon/pc87360.c #define IN_FROM_REG(val, ref) (((val) * (ref) + 128) / 256) val 150 drivers/hwmon/pc87360.c #define IN_TO_REG(val, ref) ((val) < 0 ? 0 : \ val 151 drivers/hwmon/pc87360.c (val) * 256 >= (ref) * 255 ? 255 : \ val 152 drivers/hwmon/pc87360.c ((val) * 256 + (ref) / 2) / (ref)) val 166 drivers/hwmon/pc87360.c #define TEMP_FROM_REG(val) ((val) * 1000) val 167 drivers/hwmon/pc87360.c #define TEMP_TO_REG(val) ((val) < -55000 ? -55 : \ val 168 drivers/hwmon/pc87360.c (val) > 127000 ? 127 : \ val 169 drivers/hwmon/pc87360.c (val) < 0 ? ((val) - 500) / 1000 : \ val 170 drivers/hwmon/pc87360.c ((val) + 500) / 1000) val 358 drivers/hwmon/pc87360.c long val; val 361 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 366 drivers/hwmon/pc87360.c data->pwm[attr->index] = PWM_TO_REG(val, val 429 drivers/hwmon/pc87360.c long val; val 432 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 437 drivers/hwmon/pc87360.c data->in_min[attr->index] = IN_TO_REG(val, data->in_vref); val 449 drivers/hwmon/pc87360.c long val; val 452 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 457 drivers/hwmon/pc87360.c data->in_max[attr->index] = IN_TO_REG(val, val 599 drivers/hwmon/pc87360.c unsigned long val; val 602 drivers/hwmon/pc87360.c err = kstrtoul(buf, 10, &val); val 606 drivers/hwmon/pc87360.c if (val > 255) val 609 drivers/hwmon/pc87360.c data->vrm = val; val 689 drivers/hwmon/pc87360.c long val; val 692 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 697 drivers/hwmon/pc87360.c data->in_min[attr->index] = IN_TO_REG(val, data->in_vref); val 710 drivers/hwmon/pc87360.c long val; val 713 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 718 drivers/hwmon/pc87360.c data->in_max[attr->index] = IN_TO_REG(val, data->in_vref); val 730 drivers/hwmon/pc87360.c long val; val 733 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 738 drivers/hwmon/pc87360.c data->in_crit[attr->index-11] = IN_TO_REG(val, data->in_vref); val 891 drivers/hwmon/pc87360.c long val; val 894 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 899 drivers/hwmon/pc87360.c data->temp_min[attr->index] = TEMP_TO_REG(val); val 912 drivers/hwmon/pc87360.c long val; val 915 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 920 drivers/hwmon/pc87360.c data->temp_max[attr->index] = TEMP_TO_REG(val); val 933 drivers/hwmon/pc87360.c long val; val 936 drivers/hwmon/pc87360.c err = kstrtol(buf, 10, &val); val 941 drivers/hwmon/pc87360.c data->temp_crit[attr->index] = TEMP_TO_REG(val); val 1093 drivers/hwmon/pc87360.c u16 val; val 1100 drivers/hwmon/pc87360.c val = force_id ? force_id : superio_inb(sioaddr, DEVID); val 1101 drivers/hwmon/pc87360.c switch (val) { val 1116 drivers/hwmon/pc87360.c *devid = val; val 1122 drivers/hwmon/pc87360.c val = superio_inb(sioaddr, ACT); val 1123 drivers/hwmon/pc87360.c if (!(val & 0x01)) { val 1128 drivers/hwmon/pc87360.c val = (superio_inb(sioaddr, BASE) << 8) val 1130 drivers/hwmon/pc87360.c if (!val) { val 1136 drivers/hwmon/pc87360.c addresses[i] = val; val 108 drivers/hwmon/pc87427.c static inline void superio_outb(int sioaddr, int reg, int val) val 111 drivers/hwmon/pc87427.c outb(val, sioaddr + 1); val 209 drivers/hwmon/pc87427.c static inline u16 fan_to_reg(unsigned long val) val 211 drivers/hwmon/pc87427.c if (val < 83UL) val 213 drivers/hwmon/pc87427.c if (val >= 1350000UL) val 215 drivers/hwmon/pc87427.c return ((1350000UL + val / 2) / val) << 2; val 263 drivers/hwmon/pc87427.c static inline u8 pwm_enable_to_reg(unsigned long val, u8 pwmval) val 265 drivers/hwmon/pc87427.c switch (val) { val 431 drivers/hwmon/pc87427.c unsigned long val; val 434 drivers/hwmon/pc87427.c if (kstrtoul(buf, 10, &val) < 0) val 445 drivers/hwmon/pc87427.c data->fan_min[nr] = fan_to_reg(val); val 583 drivers/hwmon/pc87427.c unsigned long val; val 585 drivers/hwmon/pc87427.c if (kstrtoul(buf, 10, &val) < 0 || val > 2) val 588 drivers/hwmon/pc87427.c if (val == 2 && !(data->pwm_auto_ok & (1 << nr))) val 593 drivers/hwmon/pc87427.c update_pwm_enable(data, nr, pwm_enable_to_reg(val, data->pwm[nr])); val 613 drivers/hwmon/pc87427.c unsigned long val; val 617 drivers/hwmon/pc87427.c if (kstrtoul(buf, 10, &val) < 0 || val > 0xff) val 632 drivers/hwmon/pc87427.c if (mode == PWM_MODE_MANUAL && val == 0) { val 638 drivers/hwmon/pc87427.c } else if (mode == PWM_MODE_OFF && val != 0) { val 646 drivers/hwmon/pc87427.c data->pwm[nr] = val; val 648 drivers/hwmon/pc87427.c outb(val, iobase + PC87427_REG_PWM_DUTY); val 1196 drivers/hwmon/pc87427.c u16 val; val 1205 drivers/hwmon/pc87427.c val = force_id ? force_id : superio_inb(sioaddr, SIOREG_DEVID); val 1206 drivers/hwmon/pc87427.c if (val != 0xf2) { /* PC87427 */ val 1216 drivers/hwmon/pc87427.c val = superio_inb(sioaddr, SIOREG_ACT); val 1217 drivers/hwmon/pc87427.c if (!(val & 0x01)) { val 1223 drivers/hwmon/pc87427.c val = superio_inb(sioaddr, SIOREG_MAP); val 1224 drivers/hwmon/pc87427.c if (val & 0x01) { val 1230 drivers/hwmon/pc87427.c val = (superio_inb(sioaddr, SIOREG_IOBASE) << 8) val 1232 drivers/hwmon/pc87427.c if (!val) { val 1237 drivers/hwmon/pc87427.c sio_data->address[i] = val; val 104 drivers/hwmon/pcf8591.c unsigned long val; val 109 drivers/hwmon/pcf8591.c err = kstrtoul(buf, 10, &val); val 113 drivers/hwmon/pcf8591.c val /= 10; val 114 drivers/hwmon/pcf8591.c if (val > 255) val 117 drivers/hwmon/pcf8591.c data->aout = val; val 137 drivers/hwmon/pcf8591.c unsigned long val; val 140 drivers/hwmon/pcf8591.c err = kstrtoul(buf, 10, &val); val 145 drivers/hwmon/pcf8591.c if (val) val 25 drivers/hwmon/pmbus/isl68137.c int val = pmbus_read_byte_data(client, page, PMBUS_OPERATION); val 28 drivers/hwmon/pmbus/isl68137.c (val & ISL68137_VOUT_AVS) == ISL68137_VOUT_AVS ? 1 : 0); val 131 drivers/hwmon/pmbus/max31785.c u32 val; val 140 drivers/hwmon/pmbus/max31785.c reg, &val); val 144 drivers/hwmon/pmbus/max31785.c rv = (val >> 16) & 0xffff; val 617 drivers/hwmon/pmbus/pmbus_core.c long val; val 627 drivers/hwmon/pmbus/pmbus_core.c val = mantissa; val 631 drivers/hwmon/pmbus/pmbus_core.c val = val * 1000L; val 635 drivers/hwmon/pmbus/pmbus_core.c val = val * 1000L; val 638 drivers/hwmon/pmbus/pmbus_core.c val <<= exponent; val 640 drivers/hwmon/pmbus/pmbus_core.c val >>= -exponent; val 642 drivers/hwmon/pmbus/pmbus_core.c return val; val 652 drivers/hwmon/pmbus/pmbus_core.c s64 b, val = (s16)sensor->data; val 677 drivers/hwmon/pmbus/pmbus_core.c val *= 10; val 681 drivers/hwmon/pmbus/pmbus_core.c val = div_s64(val + 5LL, 10L); /* round closest */ val 685 drivers/hwmon/pmbus/pmbus_core.c val = div_s64(val - b, m); val 686 drivers/hwmon/pmbus/pmbus_core.c return clamp_val(val, LONG_MIN, LONG_MAX); val 696 drivers/hwmon/pmbus/pmbus_core.c long val = sensor->data; val 701 drivers/hwmon/pmbus/pmbus_core.c if (val >= 0x02 && val <= 0xb2) val 702 drivers/hwmon/pmbus/pmbus_core.c rv = DIV_ROUND_CLOSEST(160000 - (val - 2) * 625, 100); val 705 drivers/hwmon/pmbus/pmbus_core.c if (val >= 0x01) val 706 drivers/hwmon/pmbus/pmbus_core.c rv = 250 + (val - 1) * 5; val 709 drivers/hwmon/pmbus/pmbus_core.c if (val >= 0x01) val 710 drivers/hwmon/pmbus/pmbus_core.c rv = 500 + (val - 1) * 10; val 718 drivers/hwmon/pmbus/pmbus_core.c long val; val 725 drivers/hwmon/pmbus/pmbus_core.c val = pmbus_reg2data_direct(data, sensor); val 728 drivers/hwmon/pmbus/pmbus_core.c val = pmbus_reg2data_vid(data, sensor); val 732 drivers/hwmon/pmbus/pmbus_core.c val = pmbus_reg2data_linear(data, sensor); val 735 drivers/hwmon/pmbus/pmbus_core.c return val; val 742 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_sensor *sensor, long val) val 748 drivers/hwmon/pmbus/pmbus_core.c if (val == 0) val 753 drivers/hwmon/pmbus/pmbus_core.c if (val < 0) val 761 drivers/hwmon/pmbus/pmbus_core.c val <<= -data->exponent[sensor->page]; val 763 drivers/hwmon/pmbus/pmbus_core.c val >>= data->exponent[sensor->page]; val 764 drivers/hwmon/pmbus/pmbus_core.c val = DIV_ROUND_CLOSEST(val, 1000); val 765 drivers/hwmon/pmbus/pmbus_core.c return val & 0xffff; val 768 drivers/hwmon/pmbus/pmbus_core.c if (val < 0) { val 770 drivers/hwmon/pmbus/pmbus_core.c val = -val; val 775 drivers/hwmon/pmbus/pmbus_core.c val = DIV_ROUND_CLOSEST(val, 1000L); val 782 drivers/hwmon/pmbus/pmbus_core.c val = val * 1000; val 785 drivers/hwmon/pmbus/pmbus_core.c while (val >= MAX_MANTISSA && exponent < 15) { val 787 drivers/hwmon/pmbus/pmbus_core.c val >>= 1; val 790 drivers/hwmon/pmbus/pmbus_core.c while (val < MIN_MANTISSA && exponent > -15) { val 792 drivers/hwmon/pmbus/pmbus_core.c val <<= 1; val 796 drivers/hwmon/pmbus/pmbus_core.c mantissa = DIV_ROUND_CLOSEST(val, 1000); val 811 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_sensor *sensor, long val) val 813 drivers/hwmon/pmbus/pmbus_core.c s64 b, val64 = val; val 846 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_sensor *sensor, long val) val 848 drivers/hwmon/pmbus/pmbus_core.c val = clamp_val(val, 500, 1600); val 850 drivers/hwmon/pmbus/pmbus_core.c return 2 + DIV_ROUND_CLOSEST((1600 - val) * 100, 625); val 854 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_sensor *sensor, long val) val 859 drivers/hwmon/pmbus/pmbus_core.c return val; val 863 drivers/hwmon/pmbus/pmbus_core.c regval = pmbus_data2reg_direct(data, sensor, val); val 866 drivers/hwmon/pmbus/pmbus_core.c regval = pmbus_data2reg_vid(data, sensor, val); val 870 drivers/hwmon/pmbus/pmbus_core.c regval = pmbus_data2reg_linear(data, sensor, val); val 940 drivers/hwmon/pmbus/pmbus_core.c int val; val 942 drivers/hwmon/pmbus/pmbus_core.c val = pmbus_get_boolean(data, boolean, attr->index); val 943 drivers/hwmon/pmbus/pmbus_core.c if (val < 0) val 944 drivers/hwmon/pmbus/pmbus_core.c return val; val 945 drivers/hwmon/pmbus/pmbus_core.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 968 drivers/hwmon/pmbus/pmbus_core.c long val = 0; val 972 drivers/hwmon/pmbus/pmbus_core.c if (kstrtol(buf, 10, &val) < 0) val 976 drivers/hwmon/pmbus/pmbus_core.c regval = pmbus_data2reg(data, sensor, val); val 1952 drivers/hwmon/pmbus/pmbus_core.c int val; val 1956 drivers/hwmon/pmbus/pmbus_core.c val = _pmbus_read_word_data(client, reg->page, reg->attr->reg); val 1957 drivers/hwmon/pmbus/pmbus_core.c if (val < 0) val 1958 drivers/hwmon/pmbus/pmbus_core.c return val; val 1960 drivers/hwmon/pmbus/pmbus_core.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 1968 drivers/hwmon/pmbus/pmbus_core.c long val; val 1973 drivers/hwmon/pmbus/pmbus_core.c if (kstrtol(buf, 0, &val) < 0) val 1977 drivers/hwmon/pmbus/pmbus_core.c ret = _pmbus_write_word_data(client, reg->page, reg->attr->reg, val); val 2253 drivers/hwmon/pmbus/pmbus_core.c static int pmbus_debugfs_get(void *data, u64 *val) val 2262 drivers/hwmon/pmbus/pmbus_core.c *val = rc; val 2269 drivers/hwmon/pmbus/pmbus_core.c static int pmbus_debugfs_get_status(void *data, u64 *val) val 2279 drivers/hwmon/pmbus/pmbus_core.c *val = rc; val 304 drivers/hwmon/pmbus/ucd9000.c unsigned int offset, int val) val 307 drivers/hwmon/pmbus/ucd9000.c val); val 370 drivers/hwmon/pmbus/ucd9000.c static int ucd9000_debugfs_show_mfr_status_bit(void *data, u64 *val) val 385 drivers/hwmon/pmbus/ucd9000.c *val = !!(buffer[1] & BIT(entry->index)); val 57 drivers/hwmon/pmbus/zl6100.c long val; val 62 drivers/hwmon/pmbus/zl6100.c val = mantissa; val 65 drivers/hwmon/pmbus/zl6100.c val = val * 1000L; val 68 drivers/hwmon/pmbus/zl6100.c val <<= exponent; val 70 drivers/hwmon/pmbus/zl6100.c val >>= -exponent; val 72 drivers/hwmon/pmbus/zl6100.c return val; val 78 drivers/hwmon/pmbus/zl6100.c static u16 zl6100_d2l(long val) val 84 drivers/hwmon/pmbus/zl6100.c if (val == 0) val 87 drivers/hwmon/pmbus/zl6100.c if (val < 0) { val 89 drivers/hwmon/pmbus/zl6100.c val = -val; val 93 drivers/hwmon/pmbus/zl6100.c while (val >= MAX_MANTISSA && exponent < 15) { val 95 drivers/hwmon/pmbus/zl6100.c val >>= 1; val 98 drivers/hwmon/pmbus/zl6100.c while (val < MIN_MANTISSA && exponent > -15) { val 100 drivers/hwmon/pmbus/zl6100.c val <<= 1; val 104 drivers/hwmon/pmbus/zl6100.c mantissa = DIV_ROUND_CLOSEST(val, 1000); val 75 drivers/hwmon/raspberrypi-hwmon.c u32 attr, int channel, long *val) val 79 drivers/hwmon/raspberrypi-hwmon.c *val = !!(data->last_throttled & UNDERVOLTAGE_STICKY_BIT); val 88 drivers/hwmon/sch5627.c int i, val; val 102 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg12(data->addr, val 106 drivers/hwmon/sch5627.c if (unlikely(val < 0)) { val 107 drivers/hwmon/sch5627.c ret = ERR_PTR(val); val 110 drivers/hwmon/sch5627.c data->temp[i] = val; val 114 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg16(data->addr, val 116 drivers/hwmon/sch5627.c if (unlikely(val < 0)) { val 117 drivers/hwmon/sch5627.c ret = ERR_PTR(val); val 120 drivers/hwmon/sch5627.c data->fan[i] = val; val 124 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg12(data->addr, val 128 drivers/hwmon/sch5627.c if (unlikely(val < 0)) { val 129 drivers/hwmon/sch5627.c ret = ERR_PTR(val); val 132 drivers/hwmon/sch5627.c data->in[i] = val; val 145 drivers/hwmon/sch5627.c int i, val; val 152 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg(data->addr, val 154 drivers/hwmon/sch5627.c if (val < 0) val 155 drivers/hwmon/sch5627.c return val; val 156 drivers/hwmon/sch5627.c data->temp_max[i] = val; val 158 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg(data->addr, val 160 drivers/hwmon/sch5627.c if (val < 0) val 161 drivers/hwmon/sch5627.c return val; val 162 drivers/hwmon/sch5627.c data->temp_crit[i] = val; val 165 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg16(data->addr, val 167 drivers/hwmon/sch5627.c if (val < 0) val 168 drivers/hwmon/sch5627.c return val; val 169 drivers/hwmon/sch5627.c data->fan_min[i] = val; val 206 drivers/hwmon/sch5627.c int val; val 211 drivers/hwmon/sch5627.c val = reg_to_temp(data->temp[attr->index]); val 212 drivers/hwmon/sch5627.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 232 drivers/hwmon/sch5627.c int val; val 234 drivers/hwmon/sch5627.c val = reg_to_temp_limit(data->temp_max[attr->index]); val 235 drivers/hwmon/sch5627.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 243 drivers/hwmon/sch5627.c int val; val 245 drivers/hwmon/sch5627.c val = reg_to_temp_limit(data->temp_crit[attr->index]); val 246 drivers/hwmon/sch5627.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 254 drivers/hwmon/sch5627.c int val; val 259 drivers/hwmon/sch5627.c val = reg_to_rpm(data->fan[attr->index]); val 260 drivers/hwmon/sch5627.c if (val < 0) val 261 drivers/hwmon/sch5627.c return val; val 263 drivers/hwmon/sch5627.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 284 drivers/hwmon/sch5627.c int val = reg_to_rpm(data->fan_min[attr->index]); val 285 drivers/hwmon/sch5627.c if (val < 0) val 286 drivers/hwmon/sch5627.c return val; val 288 drivers/hwmon/sch5627.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 296 drivers/hwmon/sch5627.c int val; val 301 drivers/hwmon/sch5627.c val = DIV_ROUND_CLOSEST( val 304 drivers/hwmon/sch5627.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 458 drivers/hwmon/sch5627.c int err, build_code, build_id, hwmon_rev, val; val 469 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_HWMON_ID); val 470 drivers/hwmon/sch5627.c if (val < 0) { val 471 drivers/hwmon/sch5627.c err = val; val 474 drivers/hwmon/sch5627.c if (val != SCH5627_HWMON_ID) { val 476 drivers/hwmon/sch5627.c val, SCH5627_HWMON_ID); val 481 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_COMPANY_ID); val 482 drivers/hwmon/sch5627.c if (val < 0) { val 483 drivers/hwmon/sch5627.c err = val; val 486 drivers/hwmon/sch5627.c if (val != SCH5627_COMPANY_ID) { val 488 drivers/hwmon/sch5627.c val, SCH5627_COMPANY_ID); val 493 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_PRIMARY_ID); val 494 drivers/hwmon/sch5627.c if (val < 0) { val 495 drivers/hwmon/sch5627.c err = val; val 498 drivers/hwmon/sch5627.c if (val != SCH5627_PRIMARY_ID) { val 500 drivers/hwmon/sch5627.c val, SCH5627_PRIMARY_ID); val 526 drivers/hwmon/sch5627.c val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_CTRL); val 527 drivers/hwmon/sch5627.c if (val < 0) { val 528 drivers/hwmon/sch5627.c err = val; val 531 drivers/hwmon/sch5627.c data->control = val; val 73 drivers/hwmon/sch5636.c int i, val; val 82 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg(data->addr, val 84 drivers/hwmon/sch5636.c if (unlikely(val < 0)) { val 85 drivers/hwmon/sch5636.c ret = ERR_PTR(val); val 88 drivers/hwmon/sch5636.c data->in[i] = val; val 95 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg(data->addr, val 97 drivers/hwmon/sch5636.c if (unlikely(val < 0)) { val 98 drivers/hwmon/sch5636.c ret = ERR_PTR(val); val 101 drivers/hwmon/sch5636.c data->temp_val[i] = val; val 103 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg(data->addr, val 105 drivers/hwmon/sch5636.c if (unlikely(val < 0)) { val 106 drivers/hwmon/sch5636.c ret = ERR_PTR(val); val 109 drivers/hwmon/sch5636.c data->temp_ctrl[i] = val; val 111 drivers/hwmon/sch5636.c if (val & SCH5636_TEMP_ALARM) { val 113 drivers/hwmon/sch5636.c SCH5636_REG_TEMP_CTRL(i), val); val 121 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg16(data->addr, val 123 drivers/hwmon/sch5636.c if (unlikely(val < 0)) { val 124 drivers/hwmon/sch5636.c ret = ERR_PTR(val); val 127 drivers/hwmon/sch5636.c data->fan_val[i] = val; val 129 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg(data->addr, val 131 drivers/hwmon/sch5636.c if (unlikely(val < 0)) { val 132 drivers/hwmon/sch5636.c ret = ERR_PTR(val); val 135 drivers/hwmon/sch5636.c data->fan_ctrl[i] = val; val 137 drivers/hwmon/sch5636.c if (val & SCH5636_FAN_ALARM) { val 139 drivers/hwmon/sch5636.c SCH5636_REG_FAN_CTRL(i), val); val 171 drivers/hwmon/sch5636.c int val; val 176 drivers/hwmon/sch5636.c val = DIV_ROUND_CLOSEST( val 179 drivers/hwmon/sch5636.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 196 drivers/hwmon/sch5636.c int val; val 201 drivers/hwmon/sch5636.c val = (data->temp_val[attr->index] - 64) * 1000; val 202 drivers/hwmon/sch5636.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 210 drivers/hwmon/sch5636.c int val; val 215 drivers/hwmon/sch5636.c val = (data->temp_ctrl[attr->index] & SCH5636_TEMP_WORKING) ? 0 : 1; val 216 drivers/hwmon/sch5636.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 224 drivers/hwmon/sch5636.c int val; val 229 drivers/hwmon/sch5636.c val = (data->temp_ctrl[attr->index] & SCH5636_TEMP_ALARM) ? 1 : 0; val 230 drivers/hwmon/sch5636.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 238 drivers/hwmon/sch5636.c int val; val 243 drivers/hwmon/sch5636.c val = reg_to_rpm(data->fan_val[attr->index]); val 244 drivers/hwmon/sch5636.c if (val < 0) val 245 drivers/hwmon/sch5636.c return val; val 247 drivers/hwmon/sch5636.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 255 drivers/hwmon/sch5636.c int val; val 260 drivers/hwmon/sch5636.c val = (data->fan_ctrl[attr->index] & SCH5636_FAN_NOT_PRESENT) ? 1 : 0; val 261 drivers/hwmon/sch5636.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 269 drivers/hwmon/sch5636.c int val; val 274 drivers/hwmon/sch5636.c val = (data->fan_ctrl[attr->index] & SCH5636_FAN_ALARM) ? 1 : 0; val 275 drivers/hwmon/sch5636.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 398 drivers/hwmon/sch5636.c int i, err, val, revision[2]; val 411 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg(data->addr, val 413 drivers/hwmon/sch5636.c if (val < 0) { val 416 drivers/hwmon/sch5636.c err = val; val 419 drivers/hwmon/sch5636.c id[i] = val; val 431 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg(data->addr, val 433 drivers/hwmon/sch5636.c if (val < 0) { val 434 drivers/hwmon/sch5636.c err = val; val 437 drivers/hwmon/sch5636.c revision[i] = val; val 444 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg(data->addr, val 446 drivers/hwmon/sch5636.c if (unlikely(val < 0)) { val 447 drivers/hwmon/sch5636.c err = val; val 450 drivers/hwmon/sch5636.c data->temp_ctrl[i] = val; val 454 drivers/hwmon/sch5636.c val = sch56xx_read_virtual_reg(data->addr, val 456 drivers/hwmon/sch5636.c if (unlikely(val < 0)) { val 457 drivers/hwmon/sch5636.c err = val; val 460 drivers/hwmon/sch5636.c data->fan_ctrl[i] = val; val 98 drivers/hwmon/sch56xx-common.c u8 val; val 111 drivers/hwmon/sch56xx-common.c val = inb(addr + 1); val 112 drivers/hwmon/sch56xx-common.c outb(val, addr + 1); val 139 drivers/hwmon/sch56xx-common.c val = inb(addr + 8); val 141 drivers/hwmon/sch56xx-common.c if (val) val 142 drivers/hwmon/sch56xx-common.c outb(val, addr + 8); val 144 drivers/hwmon/sch56xx-common.c if (val & 0x01) val 159 drivers/hwmon/sch56xx-common.c val = inb(addr + 1); val 161 drivers/hwmon/sch56xx-common.c if (val == 0x01) val 166 drivers/hwmon/sch56xx-common.c (unsigned int)val, reg); val 197 drivers/hwmon/sch56xx-common.c int sch56xx_write_virtual_reg(u16 addr, u16 reg, u8 val) val 199 drivers/hwmon/sch56xx-common.c return sch56xx_send_cmd(addr, SCH56XX_CMD_WRITE, reg, val); val 293 drivers/hwmon/sch56xx-common.c u8 val; val 323 drivers/hwmon/sch56xx-common.c val = data->watchdog_output_enable | SCH56XX_WDOG_OUTPUT_ENABLE; val 325 drivers/hwmon/sch56xx-common.c SCH56XX_REG_WDOG_OUTPUT_ENABLE, val); val 329 drivers/hwmon/sch56xx-common.c data->watchdog_output_enable = val; val 332 drivers/hwmon/sch56xx-common.c val = inb(data->addr + 9); val 333 drivers/hwmon/sch56xx-common.c if (val & 0x01) val 359 drivers/hwmon/sch56xx-common.c u8 val; val 361 drivers/hwmon/sch56xx-common.c val = data->watchdog_output_enable & ~SCH56XX_WDOG_OUTPUT_ENABLE; val 364 drivers/hwmon/sch56xx-common.c SCH56XX_REG_WDOG_OUTPUT_ENABLE, val); val 369 drivers/hwmon/sch56xx-common.c data->watchdog_output_enable = val; val 12 drivers/hwmon/sch56xx-common.h int sch56xx_write_virtual_reg(u16 addr, u16 reg, u8 val); val 66 drivers/hwmon/scmi-hwmon.c u32 attr, int channel, long *val) val 81 drivers/hwmon/scmi-hwmon.c *val = value; val 227 drivers/hwmon/sht15.c static inline void sht15_send_bit(struct sht15_data *data, int val) val 229 drivers/hwmon/sht15.c gpiod_set_value(data->data, val); val 814 drivers/hwmon/sht15.c uint16_t val = 0; val 836 drivers/hwmon/sht15.c val = sht15_read_byte(data); val 837 drivers/hwmon/sht15.c val <<= 8; val 840 drivers/hwmon/sht15.c val |= sht15_read_byte(data); val 852 drivers/hwmon/sht15.c checksum_vals[1] = (u8) (val >> 8); val 853 drivers/hwmon/sht15.c checksum_vals[2] = (u8) val; val 864 drivers/hwmon/sht15.c data->val_temp = val; val 867 drivers/hwmon/sht15.c data->val_humid = val; val 226 drivers/hwmon/sht3x.c u16 val; val 244 drivers/hwmon/sht3x.c val = be16_to_cpup((__be16 *)buf); val 245 drivers/hwmon/sht3x.c data->temperature = sht3x_extract_temperature(val); val 246 drivers/hwmon/sht3x.c val = be16_to_cpup((__be16 *)(buf + 3)); val 247 drivers/hwmon/sht3x.c data->humidity = sht3x_extract_humidity(val); val 105 drivers/hwmon/shtc1.c int val; val 122 drivers/hwmon/shtc1.c val = be16_to_cpup((__be16 *)buf); val 123 drivers/hwmon/shtc1.c data->temperature = ((21875 * val) >> 13) - 45000; val 124 drivers/hwmon/shtc1.c val = be16_to_cpup((__be16 *)(buf + 3)); val 125 drivers/hwmon/shtc1.c data->humidity = ((12500 * val) >> 13); val 119 drivers/hwmon/sis5595.c static inline u8 IN_TO_REG(unsigned long val) val 121 drivers/hwmon/sis5595.c unsigned long nval = clamp_val(val, 0, 4080); val 124 drivers/hwmon/sis5595.c #define IN_FROM_REG(val) ((val) * 16) val 135 drivers/hwmon/sis5595.c static inline int FAN_FROM_REG(u8 val, int div) val 137 drivers/hwmon/sis5595.c return val == 0 ? -1 : val == 255 ? 0 : 1350000 / (val * div); val 144 drivers/hwmon/sis5595.c static inline int TEMP_FROM_REG(s8 val) val 146 drivers/hwmon/sis5595.c return val * 830 + 52120; val 148 drivers/hwmon/sis5595.c static inline s8 TEMP_TO_REG(long val) val 150 drivers/hwmon/sis5595.c int nval = clamp_val(val, -54120, 157530) ; val 158 drivers/hwmon/sis5595.c static inline u8 DIV_TO_REG(int val) val 160 drivers/hwmon/sis5595.c return val == 8 ? 3 : val == 4 ? 2 : val == 1 ? 0 : 1; val 162 drivers/hwmon/sis5595.c #define DIV_FROM_REG(val) (1 << (val)) val 244 drivers/hwmon/sis5595.c unsigned long val; val 247 drivers/hwmon/sis5595.c err = kstrtoul(buf, 10, &val); val 252 drivers/hwmon/sis5595.c data->in_min[nr] = IN_TO_REG(val); val 264 drivers/hwmon/sis5595.c unsigned long val; val 267 drivers/hwmon/sis5595.c err = kstrtoul(buf, 10, &val); val 272 drivers/hwmon/sis5595.c data->in_max[nr] = IN_TO_REG(val); val 314 drivers/hwmon/sis5595.c long val; val 317 drivers/hwmon/sis5595.c err = kstrtol(buf, 10, &val); val 322 drivers/hwmon/sis5595.c data->temp_over = TEMP_TO_REG(val); val 340 drivers/hwmon/sis5595.c long val; val 343 drivers/hwmon/sis5595.c err = kstrtol(buf, 10, &val); val 348 drivers/hwmon/sis5595.c data->temp_hyst = TEMP_TO_REG(val); val 385 drivers/hwmon/sis5595.c unsigned long val; val 388 drivers/hwmon/sis5595.c err = kstrtoul(buf, 10, &val); val 393 drivers/hwmon/sis5595.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 422 drivers/hwmon/sis5595.c unsigned long val; val 425 drivers/hwmon/sis5595.c err = kstrtoul(buf, 10, &val); val 434 drivers/hwmon/sis5595.c switch (val) { val 450 drivers/hwmon/sis5595.c val); val 578 drivers/hwmon/sis5595.c char val; val 604 drivers/hwmon/sis5595.c pci_read_config_byte(s_bridge, SIS5595_PIN_REG, &val); val 605 drivers/hwmon/sis5595.c if (!(val & 0x80)) val 161 drivers/hwmon/smm665.c int rv, val; val 166 drivers/hwmon/smm665.c val = rv << 8; val 170 drivers/hwmon/smm665.c val |= rv; val 171 drivers/hwmon/smm665.c return val; val 246 drivers/hwmon/smm665.c int i, val; val 251 drivers/hwmon/smm665.c val = smm665_read16(client, SMM665_MISC8_STATUS1); val 252 drivers/hwmon/smm665.c if (unlikely(val < 0)) { val 253 drivers/hwmon/smm665.c ret = ERR_PTR(val); val 256 drivers/hwmon/smm665.c data->faults = val; val 260 drivers/hwmon/smm665.c val = smm665_read_adc(data, i); val 261 drivers/hwmon/smm665.c if (unlikely(val < 0)) { val 262 drivers/hwmon/smm665.c ret = ERR_PTR(val); val 265 drivers/hwmon/smm665.c data->adc[i] = val; val 278 drivers/hwmon/smm665.c int val = 0; val 282 drivers/hwmon/smm665.c val = SMM665_12VIN_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK); val 292 drivers/hwmon/smm665.c val = SMM665_VMON_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK); val 297 drivers/hwmon/smm665.c val = SMM665_AIN_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK); val 301 drivers/hwmon/smm665.c val = SMM665_TEMP_ADC_TO_CELSIUS(adcval & SMM665_ADC_MASK); val 310 drivers/hwmon/smm665.c return val; val 346 drivers/hwmon/smm665.c int val = 0; val 352 drivers/hwmon/smm665.c val = 1; val 354 drivers/hwmon/smm665.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 363 drivers/hwmon/smm665.c int val; val 368 drivers/hwmon/smm665.c val = smm665_convert(data->adc[adc], adc); val 369 drivers/hwmon/smm665.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 377 drivers/hwmon/smm665.c const int val = smm665_get_##what(dev, attr->index); \ val 378 drivers/hwmon/smm665.c return snprintf(buf, PAGE_SIZE, "%d\n", val); \ val 630 drivers/hwmon/smm665.c int val; val 632 drivers/hwmon/smm665.c val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8); val 633 drivers/hwmon/smm665.c if (unlikely(val < 0)) val 636 drivers/hwmon/smm665.c = smm665_convert(val, i); val 637 drivers/hwmon/smm665.c val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 2); val 638 drivers/hwmon/smm665.c if (unlikely(val < 0)) val 640 drivers/hwmon/smm665.c if (smm665_is_critical(val)) val 641 drivers/hwmon/smm665.c data->critical_min_limit[i] = smm665_convert(val, i); val 643 drivers/hwmon/smm665.c data->alarm_min_limit[i] = smm665_convert(val, i); val 644 drivers/hwmon/smm665.c val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 4); val 645 drivers/hwmon/smm665.c if (unlikely(val < 0)) val 648 drivers/hwmon/smm665.c = smm665_convert(val, i); val 649 drivers/hwmon/smm665.c val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 6); val 650 drivers/hwmon/smm665.c if (unlikely(val < 0)) val 652 drivers/hwmon/smm665.c if (smm665_is_critical(val)) val 653 drivers/hwmon/smm665.c data->critical_max_limit[i] = smm665_convert(val, i); val 655 drivers/hwmon/smm665.c data->alarm_max_limit[i] = smm665_convert(val, i); val 44 drivers/hwmon/smsc47b397.c static inline void superio_outb(int reg, int val) val 47 drivers/hwmon/smsc47b397.c outb(val, VAL); val 47 drivers/hwmon/smsc47m1.c superio_outb(int reg, int val) val 50 drivers/hwmon/smsc47m1.c outb(val, VAL); val 274 drivers/hwmon/smsc47m1.c long val; val 277 drivers/hwmon/smsc47m1.c err = kstrtol(buf, 10, &val); val 282 drivers/hwmon/smsc47m1.c rpmdiv = val * DIV_FROM_REG(data->fan_div[nr]); val 375 drivers/hwmon/smsc47m1.c long val; val 378 drivers/hwmon/smsc47m1.c err = kstrtol(buf, 10, &val); val 382 drivers/hwmon/smsc47m1.c if (val < 0 || val > 255) val 387 drivers/hwmon/smsc47m1.c data->pwm[nr] |= PWM_TO_REG(val); val 402 drivers/hwmon/smsc47m1.c unsigned long val; val 405 drivers/hwmon/smsc47m1.c err = kstrtoul(buf, 10, &val); val 409 drivers/hwmon/smsc47m1.c if (val > 1) val 414 drivers/hwmon/smsc47m1.c data->pwm[nr] |= !val; val 530 drivers/hwmon/smsc47m1.c u8 val; val 538 drivers/hwmon/smsc47m1.c val = force_id ? force_id : superio_inb(SUPERIO_REG_DEVID); val 554 drivers/hwmon/smsc47m1.c switch (val) { val 47 drivers/hwmon/smsc47m192.c static inline int SCALE(long val, int mul, int div) val 49 drivers/hwmon/smsc47m192.c if (val < 0) val 50 drivers/hwmon/smsc47m192.c return (val * mul - div / 2) / div; val 52 drivers/hwmon/smsc47m192.c return (val * mul + div / 2) / div; val 65 drivers/hwmon/smsc47m192.c static inline u8 IN_TO_REG(unsigned long val, int n) val 67 drivers/hwmon/smsc47m192.c val = clamp_val(val, 0, nom_mv[n] * 255 / 192); val 68 drivers/hwmon/smsc47m192.c return SCALE(val, 192, nom_mv[n]); val 75 drivers/hwmon/smsc47m192.c static inline s8 TEMP_TO_REG(long val) val 77 drivers/hwmon/smsc47m192.c return SCALE(clamp_val(val, -128000, 127000), 1, 1000); val 80 drivers/hwmon/smsc47m192.c static inline int TEMP_FROM_REG(s8 val) val 82 drivers/hwmon/smsc47m192.c return val * 1000; val 203 drivers/hwmon/smsc47m192.c unsigned long val; val 206 drivers/hwmon/smsc47m192.c err = kstrtoul(buf, 10, &val); val 211 drivers/hwmon/smsc47m192.c data->in_min[nr] = IN_TO_REG(val, nr); val 225 drivers/hwmon/smsc47m192.c unsigned long val; val 228 drivers/hwmon/smsc47m192.c err = kstrtoul(buf, 10, &val); val 233 drivers/hwmon/smsc47m192.c data->in_max[nr] = IN_TO_REG(val, nr); val 301 drivers/hwmon/smsc47m192.c long val; val 304 drivers/hwmon/smsc47m192.c err = kstrtol(buf, 10, &val); val 309 drivers/hwmon/smsc47m192.c data->temp_min[nr] = TEMP_TO_REG(val); val 324 drivers/hwmon/smsc47m192.c long val; val 327 drivers/hwmon/smsc47m192.c err = kstrtol(buf, 10, &val); val 332 drivers/hwmon/smsc47m192.c data->temp_max[nr] = TEMP_TO_REG(val); val 357 drivers/hwmon/smsc47m192.c long val; val 360 drivers/hwmon/smsc47m192.c err = kstrtol(buf, 10, &val); val 365 drivers/hwmon/smsc47m192.c data->temp_offset[nr] = TEMP_TO_REG(val); val 419 drivers/hwmon/smsc47m192.c unsigned long val; val 422 drivers/hwmon/smsc47m192.c err = kstrtoul(buf, 10, &val); val 425 drivers/hwmon/smsc47m192.c if (val > 255) val 428 drivers/hwmon/smsc47m192.c data->vrm = val; val 112 drivers/hwmon/stts751.c static s32 stts751_to_hw(int val) val 114 drivers/hwmon/stts751.c return DIV_ROUND_CLOSEST(val, 125) * 32; val 596 drivers/hwmon/stts751.c unsigned long val; val 601 drivers/hwmon/stts751.c if (kstrtoul(buf, 10, &val) < 0) val 604 drivers/hwmon/stts751.c idx = find_closest_descending(val, stts751_intervals, val 608 drivers/hwmon/stts751.c val, idx, stts751_intervals[idx]); val 50 drivers/hwmon/tc654.c #define TC654_FAN_FAULT_FROM_REG(val) ((val) * 50) /* 50 RPM resolution */ val 53 drivers/hwmon/tc654.c #define TC654_FAN_FAULT_TO_REG(val) (((val) / 50) & 0xff) val 199 drivers/hwmon/tc654.c int val; val 205 drivers/hwmon/tc654.c val = data->rpm_output[nr] * TC654_HIGH_RPM_RESOLUTION; val 207 drivers/hwmon/tc654.c val = data->rpm_output[nr] * TC654_LOW_RPM_RESOLUTION; val 209 drivers/hwmon/tc654.c return sprintf(buf, "%d\n", val); val 231 drivers/hwmon/tc654.c unsigned long val; val 234 drivers/hwmon/tc654.c if (kstrtoul(buf, 10, &val)) val 237 drivers/hwmon/tc654.c val = clamp_val(val, 0, 12750); val 241 drivers/hwmon/tc654.c data->fan_fault[nr] = TC654_FAN_FAULT_TO_REG(val); val 254 drivers/hwmon/tc654.c int val; val 260 drivers/hwmon/tc654.c val = !!(data->status & TC654_REG_STATUS_F1F); val 262 drivers/hwmon/tc654.c val = !!(data->status & TC654_REG_STATUS_F2F); val 264 drivers/hwmon/tc654.c return sprintf(buf, "%d\n", val); val 274 drivers/hwmon/tc654.c u8 val; val 279 drivers/hwmon/tc654.c val = BIT((data->config >> TC654_FAN_PULSE_SHIFT[nr]) & 0x03); val 280 drivers/hwmon/tc654.c return sprintf(buf, "%d\n", val); val 291 drivers/hwmon/tc654.c unsigned long val; val 294 drivers/hwmon/tc654.c if (kstrtoul(buf, 10, &val)) val 297 drivers/hwmon/tc654.c switch (val) { val 340 drivers/hwmon/tc654.c unsigned long val; val 343 drivers/hwmon/tc654.c if (kstrtoul(buf, 10, &val)) val 346 drivers/hwmon/tc654.c if (val != 0 && val != 1) val 351 drivers/hwmon/tc654.c if (val) val 387 drivers/hwmon/tc654.c unsigned long val; val 390 drivers/hwmon/tc654.c if (kstrtoul(buf, 10, &val)) val 392 drivers/hwmon/tc654.c if (val > 255) val 397 drivers/hwmon/tc654.c if (val == 0) val 402 drivers/hwmon/tc654.c data->duty_cycle = find_closest(val, tc654_pwm_map, val 186 drivers/hwmon/thmc50.c long val; val 189 drivers/hwmon/thmc50.c err = kstrtol(buf, 10, &val); val 194 drivers/hwmon/thmc50.c data->temp_min[nr] = clamp_val(val / 1000, -128, 127); val 216 drivers/hwmon/thmc50.c long val; val 219 drivers/hwmon/thmc50.c err = kstrtol(buf, 10, &val); val 224 drivers/hwmon/thmc50.c data->temp_max[nr] = clamp_val(val / 1000, -128, 127); val 61 drivers/hwmon/tmp102.c static inline int tmp102_reg_to_mC(s16 val) val 63 drivers/hwmon/tmp102.c return ((val & ~0x01) * 1000) / 128; val 67 drivers/hwmon/tmp102.c static inline u16 tmp102_mC_to_reg(int val) val 69 drivers/hwmon/tmp102.c return (val * 128) / 1000; val 44 drivers/hwmon/tmp103.c static inline int tmp103_reg_to_mc(s8 val) val 46 drivers/hwmon/tmp103.c return val * 1000; val 49 drivers/hwmon/tmp103.c static inline u8 tmp103_mc_to_reg(int val) val 51 drivers/hwmon/tmp103.c return DIV_ROUND_CLOSEST(val, 1000); val 75 drivers/hwmon/tmp103.c long val; val 78 drivers/hwmon/tmp103.c if (kstrtol(buf, 10, &val) < 0) val 81 drivers/hwmon/tmp103.c val = clamp_val(val, -55000, 127000); val 82 drivers/hwmon/tmp103.c ret = regmap_write(regmap, sda->index, tmp103_mc_to_reg(val)); val 80 drivers/hwmon/tmp108.c static inline int tmp108_temp_reg_to_mC(s16 val) val 82 drivers/hwmon/tmp108.c return (val & ~0x0f) * 1000 / 256; val 86 drivers/hwmon/tmp108.c static inline u16 tmp108_mC_to_temp_reg(int val) val 88 drivers/hwmon/tmp108.c return (val * 256) / 1000; val 180 drivers/hwmon/tmp401.c int i, j, val; val 192 drivers/hwmon/tmp401.c val = i2c_smbus_read_byte_data(client, regaddr); val 194 drivers/hwmon/tmp401.c val = i2c_smbus_read_word_swapped(client, val 197 drivers/hwmon/tmp401.c if (val < 0) val 198 drivers/hwmon/tmp401.c return val; val 200 drivers/hwmon/tmp401.c data->temp[j][i] = j == 3 ? val << 8 : val; val 211 drivers/hwmon/tmp401.c int i, val; val 224 drivers/hwmon/tmp401.c val = i2c_smbus_read_byte_data(client, TMP401_STATUS); val 225 drivers/hwmon/tmp401.c if (val < 0) { val 226 drivers/hwmon/tmp401.c ret = ERR_PTR(val); val 230 drivers/hwmon/tmp401.c (val & TMP401_STATUS_REMOTE_OPEN) >> 1; val 232 drivers/hwmon/tmp401.c ((val & TMP401_STATUS_REMOTE_LOW) >> 2) | val 233 drivers/hwmon/tmp401.c ((val & TMP401_STATUS_LOCAL_LOW) >> 5); val 235 drivers/hwmon/tmp401.c ((val & TMP401_STATUS_REMOTE_HIGH) >> 3) | val 236 drivers/hwmon/tmp401.c ((val & TMP401_STATUS_LOCAL_HIGH) >> 6); val 237 drivers/hwmon/tmp401.c data->status[3] = val & (TMP401_STATUS_LOCAL_CRIT val 241 drivers/hwmon/tmp401.c val = i2c_smbus_read_byte_data(client, val 243 drivers/hwmon/tmp401.c if (val < 0) { val 244 drivers/hwmon/tmp401.c ret = ERR_PTR(val); val 247 drivers/hwmon/tmp401.c data->status[i] = val; val 251 drivers/hwmon/tmp401.c val = i2c_smbus_read_byte_data(client, TMP401_CONFIG_READ); val 252 drivers/hwmon/tmp401.c if (val < 0) { val 253 drivers/hwmon/tmp401.c ret = ERR_PTR(val); val 256 drivers/hwmon/tmp401.c data->config = val; val 257 drivers/hwmon/tmp401.c val = tmp401_update_device_reg16(client, data); val 258 drivers/hwmon/tmp401.c if (val < 0) { val 259 drivers/hwmon/tmp401.c ret = ERR_PTR(val); val 262 drivers/hwmon/tmp401.c val = i2c_smbus_read_byte_data(client, TMP401_TEMP_CRIT_HYST); val 263 drivers/hwmon/tmp401.c if (val < 0) { val 264 drivers/hwmon/tmp401.c ret = ERR_PTR(val); val 267 drivers/hwmon/tmp401.c data->temp_crit_hyst = val; val 331 drivers/hwmon/tmp401.c long val; val 335 drivers/hwmon/tmp401.c if (kstrtol(buf, 10, &val)) val 338 drivers/hwmon/tmp401.c reg = tmp401_temp_to_register(val, data->config, nr == 3 ? 8 : 4); val 363 drivers/hwmon/tmp401.c long val; val 369 drivers/hwmon/tmp401.c if (kstrtol(buf, 10, &val)) val 373 drivers/hwmon/tmp401.c val = clamp_val(val, -64000, 191000); val 375 drivers/hwmon/tmp401.c val = clamp_val(val, 0, 127000); val 379 drivers/hwmon/tmp401.c val = clamp_val(val, temp - 255000, temp); val 380 drivers/hwmon/tmp401.c reg = ((temp - val) + 500) / 1000; val 403 drivers/hwmon/tmp401.c long val; val 405 drivers/hwmon/tmp401.c if (kstrtol(buf, 10, &val)) val 408 drivers/hwmon/tmp401.c if (val != 1) { val 411 drivers/hwmon/tmp401.c val); val 415 drivers/hwmon/tmp401.c i2c_smbus_write_byte_data(client, TMP401_TEMP_MSB_WRITE[5][0], val); val 436 drivers/hwmon/tmp401.c unsigned long val; val 439 drivers/hwmon/tmp401.c err = kstrtoul(buf, 10, &val); val 451 drivers/hwmon/tmp401.c val = clamp_val(val, 125, 16000); val 452 drivers/hwmon/tmp401.c rate = 7 - __fls(val * 4 / (125 * 3)); val 150 drivers/hwmon/tmp421.c u32 attr, int channel, long *val) val 157 drivers/hwmon/tmp421.c *val = temp_from_u16(tmp421->temp[channel]); val 159 drivers/hwmon/tmp421.c *val = temp_from_s16(tmp421->temp[channel]); val 166 drivers/hwmon/tmp421.c *val = tmp421->temp[channel] & 0x01; val 80 drivers/hwmon/ultra45_env.c static void env_write(struct env *p, u8 ireg, u8 val) val 84 drivers/hwmon/ultra45_env.c writeb(val, p->regs + REG_DATA); val 103 drivers/hwmon/ultra45_env.c u8 val; val 105 drivers/hwmon/ultra45_env.c val = env_read(p, IREG_FAN0 + fan_nr); val 106 drivers/hwmon/ultra45_env.c period = (int) val << 8; val 122 drivers/hwmon/ultra45_env.c u8 val; val 133 drivers/hwmon/ultra45_env.c val = period >> 8; val 134 drivers/hwmon/ultra45_env.c env_write(p, IREG_FAN0 + fan_nr, val); val 144 drivers/hwmon/ultra45_env.c u8 val = env_read(p, IREG_FAN_STAT); val 145 drivers/hwmon/ultra45_env.c return sprintf(buf, "%d\n", (val & (1 << fan_nr)) ? 1 : 0); val 167 drivers/hwmon/ultra45_env.c s8 val; val 169 drivers/hwmon/ultra45_env.c val = env_read(p, IREG_LCL_TEMP + temp_nr); val 170 drivers/hwmon/ultra45_env.c return sprintf(buf, "%d\n", ((int) val) - 64); val 188 drivers/hwmon/ultra45_env.c u8 val; val 190 drivers/hwmon/ultra45_env.c val = readb(p->regs + REG_STAT); val 191 drivers/hwmon/ultra45_env.c return sprintf(buf, "%d\n", (val & (1 << index)) ? 1 : 0); val 204 drivers/hwmon/ultra45_env.c u8 val; val 206 drivers/hwmon/ultra45_env.c val = readb(p->regs + REG_STAT); val 207 drivers/hwmon/ultra45_env.c return sprintf(buf, "%d\n", val >> 4); val 114 drivers/hwmon/via686a.c static inline u8 IN_TO_REG(long val, int in_num) val 124 drivers/hwmon/via686a.c return (u8) clamp_val((val * 21024 - 1205000) / 250000, 0, 255); val 126 drivers/hwmon/via686a.c return (u8) clamp_val((val * 15737 - 1205000) / 250000, 0, 255); val 128 drivers/hwmon/via686a.c return (u8) clamp_val((val * 10108 - 1205000) / 250000, 0, 255); val 130 drivers/hwmon/via686a.c return (u8) clamp_val((val * 41714 - 12050000) / 2500000, 0, val 134 drivers/hwmon/via686a.c static inline long IN_FROM_REG(u8 val, int in_num) val 142 drivers/hwmon/via686a.c return (long) ((250000 * val + 1330000 + 21024 / 2) / 21024); val 144 drivers/hwmon/via686a.c return (long) ((250000 * val + 1330000 + 15737 / 2) / 15737); val 146 drivers/hwmon/via686a.c return (long) ((250000 * val + 1330000 + 10108 / 2) / 10108); val 148 drivers/hwmon/via686a.c return (long) ((2500000 * val + 13300000 + 41714 / 2) / 41714); val 165 drivers/hwmon/via686a.c #define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : (val) == 255 ? 0 : 1350000 / \ val 166 drivers/hwmon/via686a.c ((val) * (div))) val 271 drivers/hwmon/via686a.c static inline u8 TEMP_TO_REG(long val) val 273 drivers/hwmon/via686a.c return via_lut[val <= -50000 ? 0 : val >= 110000 ? 160 : val 274 drivers/hwmon/via686a.c (val < 0 ? val - 500 : val + 500) / 1000 + 50]; val 278 drivers/hwmon/via686a.c #define TEMP_FROM_REG(val) ((long)temp_lut[val] * 100) val 281 drivers/hwmon/via686a.c static inline long TEMP_FROM_REG10(u16 val) val 283 drivers/hwmon/via686a.c u16 eight_bits = val >> 2; val 284 drivers/hwmon/via686a.c u16 two_bits = val & 3; val 295 drivers/hwmon/via686a.c #define DIV_FROM_REG(val) (1 << (val)) val 296 drivers/hwmon/via686a.c #define DIV_TO_REG(val) ((val) == 8 ? 3 : (val) == 4 ? 2 : (val) == 1 ? 0 : 1) val 373 drivers/hwmon/via686a.c unsigned long val; val 376 drivers/hwmon/via686a.c err = kstrtoul(buf, 10, &val); val 381 drivers/hwmon/via686a.c data->in_min[nr] = IN_TO_REG(val, nr); val 392 drivers/hwmon/via686a.c unsigned long val; val 395 drivers/hwmon/via686a.c err = kstrtoul(buf, 10, &val); val 400 drivers/hwmon/via686a.c data->in_max[nr] = IN_TO_REG(val, nr); val 451 drivers/hwmon/via686a.c long val; val 454 drivers/hwmon/via686a.c err = kstrtol(buf, 10, &val); val 459 drivers/hwmon/via686a.c data->temp_over[nr] = TEMP_TO_REG(val); val 471 drivers/hwmon/via686a.c long val; val 474 drivers/hwmon/via686a.c err = kstrtol(buf, 10, &val); val 479 drivers/hwmon/via686a.c data->temp_hyst[nr] = TEMP_TO_REG(val); val 526 drivers/hwmon/via686a.c unsigned long val; val 529 drivers/hwmon/via686a.c err = kstrtoul(buf, 10, &val); val 534 drivers/hwmon/via686a.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 545 drivers/hwmon/via686a.c unsigned long val; val 548 drivers/hwmon/via686a.c err = kstrtoul(buf, 10, &val); val 554 drivers/hwmon/via686a.c data->fan_div[nr] = DIV_TO_REG(val); val 861 drivers/hwmon/via686a.c u16 address, val; val 871 drivers/hwmon/via686a.c pci_read_config_word(dev, VIA686A_BASE_REG, &val)) val 874 drivers/hwmon/via686a.c address = val & ~(VIA686A_EXTENT - 1); val 882 drivers/hwmon/via686a.c pci_read_config_word(dev, VIA686A_ENABLE_REG, &val)) val 884 drivers/hwmon/via686a.c if (!(val & 0x0001)) { val 895 drivers/hwmon/via686a.c val | 0x0001)) val 148 drivers/hwmon/vt1211.c #define IN_TO_REG(ix, val) (clamp_val((ix) == 5 ? \ val 149 drivers/hwmon/vt1211.c ((val) * 958 + 7941) / 15882 + 3 : \ val 150 drivers/hwmon/vt1211.c ((val) * 958 + 5000) / 10000 + 3, 0, 255)) val 163 drivers/hwmon/vt1211.c #define TEMP_TO_REG(ix, val) clamp_val( \ val 164 drivers/hwmon/vt1211.c ((ix) == 0 ? ((val) + 500) / 1000 : \ val 165 drivers/hwmon/vt1211.c (ix) == 1 ? ((val) + 500) / 1000 + 51 : \ val 166 drivers/hwmon/vt1211.c 253 - ((val) * 210 + 1100) / 2200), 0, 255) val 172 drivers/hwmon/vt1211.c #define RPM_TO_REG(val, div) ((val) == 0 ? 255 : \ val 173 drivers/hwmon/vt1211.c clamp_val((1310720 / (val) / \ val 198 drivers/hwmon/vt1211.c static inline void superio_outb(int sio_cip, int reg, int val) val 201 drivers/hwmon/vt1211.c outb(val, sio_cip + 1); val 242 drivers/hwmon/vt1211.c static inline void vt1211_write8(struct vt1211_data *data, u8 reg, u8 val) val 244 drivers/hwmon/vt1211.c outb(val, data->addr + reg); val 250 drivers/hwmon/vt1211.c int ix, val; val 292 drivers/hwmon/vt1211.c val = vt1211_read8(data, VT1211_REG_FAN_DIV); val 293 drivers/hwmon/vt1211.c data->fan_div[0] = (val >> 4) & 3; val 294 drivers/hwmon/vt1211.c data->fan_div[1] = (val >> 6) & 3; val 295 drivers/hwmon/vt1211.c data->fan_ctl = val & 0xf; val 297 drivers/hwmon/vt1211.c val = vt1211_read8(data, VT1211_REG_PWM_CTL); val 298 drivers/hwmon/vt1211.c data->pwm_ctl[0] = val & 0xf; val 299 drivers/hwmon/vt1211.c data->pwm_ctl[1] = (val >> 4) & 0xf; val 379 drivers/hwmon/vt1211.c long val; val 382 drivers/hwmon/vt1211.c err = kstrtol(buf, 10, &val); val 389 drivers/hwmon/vt1211.c data->in_min[ix] = IN_TO_REG(ix, val); val 393 drivers/hwmon/vt1211.c data->in_max[ix] = IN_TO_REG(ix, val); val 453 drivers/hwmon/vt1211.c long val; val 456 drivers/hwmon/vt1211.c err = kstrtol(buf, 10, &val); val 463 drivers/hwmon/vt1211.c data->temp_max[ix] = TEMP_TO_REG(ix, val); val 468 drivers/hwmon/vt1211.c data->temp_hyst[ix] = TEMP_TO_REG(ix, val); val 530 drivers/hwmon/vt1211.c unsigned long val; val 533 drivers/hwmon/vt1211.c err = kstrtoul(buf, 10, &val); val 547 drivers/hwmon/vt1211.c data->fan_min[ix] = RPM_TO_REG(val, data->fan_div[ix]); val 552 drivers/hwmon/vt1211.c switch (val) { val 569 drivers/hwmon/vt1211.c val); val 636 drivers/hwmon/vt1211.c unsigned long val; val 639 drivers/hwmon/vt1211.c err = kstrtoul(buf, 10, &val); val 655 drivers/hwmon/vt1211.c switch (val) { val 673 drivers/hwmon/vt1211.c val); val 685 drivers/hwmon/vt1211.c val = 135000 / clamp_val(val, 135000 >> 7, 135000); val 688 drivers/hwmon/vt1211.c for (val >>= 1; val > 0; val >>= 1) val 696 drivers/hwmon/vt1211.c if (val < 1 || val > 7) { val 700 drivers/hwmon/vt1211.c val); val 703 drivers/hwmon/vt1211.c if (!ISTEMP(val - 1, data->uch_config)) { val 706 drivers/hwmon/vt1211.c val); val 713 drivers/hwmon/vt1211.c data->pwm_ctl[ix] = (data->pwm_ctl[ix] & 8) | (val - 1); val 774 drivers/hwmon/vt1211.c long val; val 777 drivers/hwmon/vt1211.c err = kstrtol(buf, 10, &val); val 789 drivers/hwmon/vt1211.c data->pwm_auto_temp[ap] = TEMP_TO_REG(data->pwm_ctl[ix] & 7, val); val 836 drivers/hwmon/vt1211.c unsigned long val; val 839 drivers/hwmon/vt1211.c err = kstrtoul(buf, 10, &val); val 844 drivers/hwmon/vt1211.c data->pwm_auto_pwm[ix][ap] = clamp_val(val, 0, 255); val 868 drivers/hwmon/vt1211.c unsigned long val; val 871 drivers/hwmon/vt1211.c err = kstrtoul(buf, 10, &val); val 875 drivers/hwmon/vt1211.c if (val > 255) val 878 drivers/hwmon/vt1211.c data->vrm = val; val 91 drivers/hwmon/vt8231.c #define TEMP_MAXMIN_TO_REG(val) (253 - ((val) * 210 + 1100) / 2200) val 111 drivers/hwmon/vt8231.c #define DIV_FROM_REG(val) (1 << (val)) val 140 drivers/hwmon/vt8231.c #define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : 1310720 / ((val) * (div))) val 218 drivers/hwmon/vt8231.c unsigned long val; val 221 drivers/hwmon/vt8231.c err = kstrtoul(buf, 10, &val); val 226 drivers/hwmon/vt8231.c data->in_min[nr] = clamp_val(((val * 958) / 10000) + 3, 0, 255); val 238 drivers/hwmon/vt8231.c unsigned long val; val 241 drivers/hwmon/vt8231.c err = kstrtoul(buf, 10, &val); val 246 drivers/hwmon/vt8231.c data->in_max[nr] = clamp_val(((val * 958) / 10000) + 3, 0, 255); val 285 drivers/hwmon/vt8231.c unsigned long val; val 288 drivers/hwmon/vt8231.c err = kstrtoul(buf, 10, &val); val 293 drivers/hwmon/vt8231.c data->in_min[5] = clamp_val(((val * 958 * 34) / (10000 * 54)) + 3, val 305 drivers/hwmon/vt8231.c unsigned long val; val 308 drivers/hwmon/vt8231.c err = kstrtoul(buf, 10, &val); val 313 drivers/hwmon/vt8231.c data->in_max[5] = clamp_val(((val * 958 * 34) / (10000 * 54)) + 3, val 367 drivers/hwmon/vt8231.c long val; val 370 drivers/hwmon/vt8231.c err = kstrtol(buf, 10, &val); val 375 drivers/hwmon/vt8231.c data->temp_max[0] = clamp_val((val + 500) / 1000, 0, 255); val 385 drivers/hwmon/vt8231.c long val; val 388 drivers/hwmon/vt8231.c err = kstrtol(buf, 10, &val); val 393 drivers/hwmon/vt8231.c data->temp_min[0] = clamp_val((val + 500) / 1000, 0, 255); val 433 drivers/hwmon/vt8231.c long val; val 436 drivers/hwmon/vt8231.c err = kstrtol(buf, 10, &val); val 441 drivers/hwmon/vt8231.c data->temp_max[nr] = clamp_val(TEMP_MAXMIN_TO_REG(val), 0, 255); val 453 drivers/hwmon/vt8231.c long val; val 456 drivers/hwmon/vt8231.c err = kstrtol(buf, 10, &val); val 461 drivers/hwmon/vt8231.c data->temp_min[nr] = clamp_val(TEMP_MAXMIN_TO_REG(val), 0, 255); val 529 drivers/hwmon/vt8231.c unsigned long val; val 532 drivers/hwmon/vt8231.c err = kstrtoul(buf, 10, &val); val 537 drivers/hwmon/vt8231.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 549 drivers/hwmon/vt8231.c unsigned long val; val 556 drivers/hwmon/vt8231.c err = kstrtoul(buf, 10, &val); val 561 drivers/hwmon/vt8231.c switch (val) { val 577 drivers/hwmon/vt8231.c val); val 984 drivers/hwmon/vt8231.c u16 address, val; val 996 drivers/hwmon/vt8231.c &val)) val 999 drivers/hwmon/vt8231.c address = val & ~(VT8231_EXTENT - 1); val 1006 drivers/hwmon/vt8231.c &val)) val 1009 drivers/hwmon/vt8231.c if (!(val & 0x0001)) { val 1013 drivers/hwmon/vt8231.c val | 0x0001)) val 105 drivers/hwmon/w83627ehf.c superio_outb(int ioreg, int reg, int val) val 108 drivers/hwmon/w83627ehf.c outb(val, ioreg + 1); val 408 drivers/hwmon/w83627ehf.c static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in) val 410 drivers/hwmon/w83627ehf.c return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255); val 954 drivers/hwmon/w83627ehf.c unsigned long val; \ val 956 drivers/hwmon/w83627ehf.c err = kstrtoul(buf, 10, &val); \ val 960 drivers/hwmon/w83627ehf.c data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \ val 1068 drivers/hwmon/w83627ehf.c unsigned long val; val 1073 drivers/hwmon/w83627ehf.c err = kstrtoul(buf, 10, &val); val 1083 drivers/hwmon/w83627ehf.c if (!val) { val 1084 drivers/hwmon/w83627ehf.c val = 0xff1f; val 1086 drivers/hwmon/w83627ehf.c if (val > 1350000U) val 1087 drivers/hwmon/w83627ehf.c val = 135000U; val 1088 drivers/hwmon/w83627ehf.c val = 1350000U / val; val 1089 drivers/hwmon/w83627ehf.c val = (val & 0x1f) | ((val << 3) & 0xff00); val 1091 drivers/hwmon/w83627ehf.c data->fan_min[nr] = val; val 1094 drivers/hwmon/w83627ehf.c if (!val) { val 1099 drivers/hwmon/w83627ehf.c } else if ((reg = 1350000U / val) >= 128 * 255) { val 1108 drivers/hwmon/w83627ehf.c nr + 1, val, data->fan_from_reg_min(254, 7)); val 1118 drivers/hwmon/w83627ehf.c nr + 1, val, data->fan_from_reg_min(1, 0)); val 1225 drivers/hwmon/w83627ehf.c long val; \ val 1226 drivers/hwmon/w83627ehf.c err = kstrtol(buf, 10, &val); \ val 1230 drivers/hwmon/w83627ehf.c data->reg[nr] = LM75_TEMP_TO_REG(val); \ val 1255 drivers/hwmon/w83627ehf.c long val; val 1258 drivers/hwmon/w83627ehf.c err = kstrtol(buf, 10, &val); val 1262 drivers/hwmon/w83627ehf.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127); val 1265 drivers/hwmon/w83627ehf.c data->temp_offset[nr] = val; val 1266 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[nr], val); val 1390 drivers/hwmon/w83627ehf.c unsigned long val; val 1394 drivers/hwmon/w83627ehf.c err = kstrtoul(buf, 10, &val); val 1398 drivers/hwmon/w83627ehf.c if (val > 1) val 1402 drivers/hwmon/w83627ehf.c if (sio_data->kind == nct6776 && nr && val != 1) val 1407 drivers/hwmon/w83627ehf.c data->pwm_mode[nr] = val; val 1409 drivers/hwmon/w83627ehf.c if (!val) val 1423 drivers/hwmon/w83627ehf.c unsigned long val; val 1426 drivers/hwmon/w83627ehf.c err = kstrtoul(buf, 10, &val); val 1430 drivers/hwmon/w83627ehf.c val = clamp_val(val, 0, 255); val 1433 drivers/hwmon/w83627ehf.c data->pwm[nr] = val; val 1434 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, data->REG_PWM[nr], val); val 1447 drivers/hwmon/w83627ehf.c unsigned long val; val 1451 drivers/hwmon/w83627ehf.c err = kstrtoul(buf, 10, &val); val 1455 drivers/hwmon/w83627ehf.c if (!val || (val > 4 && val != data->pwm_enable_orig[nr])) val 1458 drivers/hwmon/w83627ehf.c if (sio_data->kind == nct6776 && val == 4) val 1462 drivers/hwmon/w83627ehf.c data->pwm_enable[nr] = val; val 1467 drivers/hwmon/w83627ehf.c reg |= (val - 1) << 4; val 1473 drivers/hwmon/w83627ehf.c reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr]; val 1502 drivers/hwmon/w83627ehf.c long val; val 1505 drivers/hwmon/w83627ehf.c err = kstrtol(buf, 10, &val); val 1509 drivers/hwmon/w83627ehf.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127); val 1512 drivers/hwmon/w83627ehf.c data->target_temp[nr] = val; val 1513 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, data->REG_TARGET[nr], val); val 1527 drivers/hwmon/w83627ehf.c long val; val 1530 drivers/hwmon/w83627ehf.c err = kstrtol(buf, 10, &val); val 1535 drivers/hwmon/w83627ehf.c val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15); val 1540 drivers/hwmon/w83627ehf.c if (sio_data->kind == nct6776 && val > 7) val 1541 drivers/hwmon/w83627ehf.c val = 7; val 1543 drivers/hwmon/w83627ehf.c reg = (reg & 0xf0) | val; val 1548 drivers/hwmon/w83627ehf.c reg = (reg & 0x0f) | (val << 4); val 1550 drivers/hwmon/w83627ehf.c reg = (reg & 0xf0) | val; val 1553 drivers/hwmon/w83627ehf.c data->tolerance[nr] = val; val 1629 drivers/hwmon/w83627ehf.c unsigned long val; \ val 1631 drivers/hwmon/w83627ehf.c err = kstrtoul(buf, 10, &val); \ val 1634 drivers/hwmon/w83627ehf.c val = clamp_val(val, 1, 255); \ val 1636 drivers/hwmon/w83627ehf.c data->reg[nr] = val; \ val 1637 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, data->REG_##REG[nr], val); \ val 1668 drivers/hwmon/w83627ehf.c unsigned long val; \ val 1670 drivers/hwmon/w83627ehf.c err = kstrtoul(buf, 10, &val); \ val 1673 drivers/hwmon/w83627ehf.c val = step_time_to_reg(val, data->pwm_mode[nr]); \ val 1675 drivers/hwmon/w83627ehf.c data->reg[nr] = val; \ val 1676 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, data->REG_##REG[nr], val); \ val 1774 drivers/hwmon/w83627ehf.c unsigned long val; val 1777 drivers/hwmon/w83627ehf.c if (kstrtoul(buf, 10, &val) || val != 0) val 2710 drivers/hwmon/w83627ehf.c u16 val; val 2719 drivers/hwmon/w83627ehf.c val = force_id; val 2721 drivers/hwmon/w83627ehf.c val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) val 2723 drivers/hwmon/w83627ehf.c switch (val & SIO_ID_MASK) { val 2761 drivers/hwmon/w83627ehf.c if (val != 0xffff) val 2762 drivers/hwmon/w83627ehf.c pr_debug("unsupported chip ID: 0x%04x\n", val); val 2769 drivers/hwmon/w83627ehf.c val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8) val 2771 drivers/hwmon/w83627ehf.c *addr = val & IOREGION_ALIGNMENT; val 2779 drivers/hwmon/w83627ehf.c val = superio_inb(sioaddr, SIO_REG_ENABLE); val 2780 drivers/hwmon/w83627ehf.c if (!(val & 0x01)) { val 2782 drivers/hwmon/w83627ehf.c superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01); val 100 drivers/hwmon/w83627hf.c superio_outb(struct w83627hf_sio_data *sio, int reg, int val) val 103 drivers/hwmon/w83627hf.c outb(val, sio->sioaddr + 1); val 250 drivers/hwmon/w83627hf.c #define IN_TO_REG(val) (clamp_val((((val) + 8) / 16), 0, 255)) val 251 drivers/hwmon/w83627hf.c #define IN_FROM_REG(val) ((val) * 16) val 280 drivers/hwmon/w83627hf.c #define FAN_FROM_REG(val,div) ((val)==0?-1:(val)==255?0:1350000/((val)*(div))) val 282 drivers/hwmon/w83627hf.c #define PWM_TO_REG(val) (clamp_val((val), 0, 255)) val 290 drivers/hwmon/w83627hf.c static inline u8 pwm_freq_to_reg_627hf(unsigned long val) val 298 drivers/hwmon/w83627hf.c if (val > (((W83627HF_BASE_PWM_FREQ >> i) + val 316 drivers/hwmon/w83627hf.c static inline u8 pwm_freq_to_reg(unsigned long val) val 319 drivers/hwmon/w83627hf.c if (val >= 93750) /* The highest we can do */ val 321 drivers/hwmon/w83627hf.c if (val >= 720) /* Use 24 MHz clock */ val 322 drivers/hwmon/w83627hf.c return 24000000UL / (val << 8); val 323 drivers/hwmon/w83627hf.c if (val < 6) /* The lowest we can do */ val 326 drivers/hwmon/w83627hf.c return 0x80 | (180000UL / (val << 8)); val 329 drivers/hwmon/w83627hf.c #define BEEP_MASK_FROM_REG(val) ((val) & 0xff7fff) val 330 drivers/hwmon/w83627hf.c #define BEEP_MASK_TO_REG(val) ((val) & 0xff7fff) val 332 drivers/hwmon/w83627hf.c #define DIV_FROM_REG(val) (1 << (val)) val 334 drivers/hwmon/w83627hf.c static inline u8 DIV_TO_REG(long val) val 337 drivers/hwmon/w83627hf.c val = clamp_val(val, 1, 128) >> 1; val 339 drivers/hwmon/w83627hf.c if (val == 0) val 341 drivers/hwmon/w83627hf.c val >>= 1; val 503 drivers/hwmon/w83627hf.c long val; val 506 drivers/hwmon/w83627hf.c err = kstrtol(buf, 10, &val); val 511 drivers/hwmon/w83627hf.c data->in_min[nr] = IN_TO_REG(val); val 522 drivers/hwmon/w83627hf.c long val; val 525 drivers/hwmon/w83627hf.c err = kstrtol(buf, 10, &val); val 530 drivers/hwmon/w83627hf.c data->in_max[nr] = IN_TO_REG(val); val 605 drivers/hwmon/w83627hf.c unsigned long val; val 608 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 620 drivers/hwmon/w83627hf.c clamp_val(((val * 100) - 70000 + 244) / 488, 0, 255); val 623 drivers/hwmon/w83627hf.c data->in_min[0] = IN_TO_REG(val); val 635 drivers/hwmon/w83627hf.c unsigned long val; val 638 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 650 drivers/hwmon/w83627hf.c clamp_val(((val * 100) - 70000 + 244) / 488, 0, 255); val 653 drivers/hwmon/w83627hf.c data->in_max[0] = IN_TO_REG(val); val 687 drivers/hwmon/w83627hf.c unsigned long val; val 690 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 695 drivers/hwmon/w83627hf.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 751 drivers/hwmon/w83627hf.c long val; val 754 drivers/hwmon/w83627hf.c err = kstrtol(buf, 10, &val); val 758 drivers/hwmon/w83627hf.c tmp = (nr) ? LM75_TEMP_TO_REG(val) : TEMP_TO_REG(val); val 773 drivers/hwmon/w83627hf.c long val; val 776 drivers/hwmon/w83627hf.c err = kstrtol(buf, 10, &val); val 780 drivers/hwmon/w83627hf.c tmp = (nr) ? LM75_TEMP_TO_REG(val) : TEMP_TO_REG(val); val 817 drivers/hwmon/w83627hf.c unsigned long val; val 820 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 824 drivers/hwmon/w83627hf.c if (val > 255) val 826 drivers/hwmon/w83627hf.c data->vrm = val; val 876 drivers/hwmon/w83627hf.c unsigned long val; val 879 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 887 drivers/hwmon/w83627hf.c | BEEP_MASK_TO_REG(val); val 998 drivers/hwmon/w83627hf.c unsigned long val; val 1001 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 1011 drivers/hwmon/w83627hf.c data->fan_div[nr] = DIV_TO_REG(val); val 1049 drivers/hwmon/w83627hf.c unsigned long val; val 1052 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 1060 drivers/hwmon/w83627hf.c data->pwm[nr] = PWM_TO_REG(val) & 0xf0; val 1067 drivers/hwmon/w83627hf.c data->pwm[nr] = PWM_TO_REG(val); val 1097 drivers/hwmon/w83627hf.c unsigned long val; val 1100 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 1104 drivers/hwmon/w83627hf.c if (!val || val > 3) /* modes 1, 2 and 3 are supported */ val 1107 drivers/hwmon/w83627hf.c data->pwm_enable[nr] = val; val 1110 drivers/hwmon/w83627hf.c reg |= (val - 1) << W83627THF_PWM_ENABLE_SHIFT[nr]; val 1140 drivers/hwmon/w83627hf.c unsigned long val; val 1143 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 1150 drivers/hwmon/w83627hf.c data->pwm_freq[nr] = pwm_freq_to_reg_627hf(val); val 1156 drivers/hwmon/w83627hf.c data->pwm_freq[nr] = pwm_freq_to_reg(val); val 1184 drivers/hwmon/w83627hf.c unsigned long val; val 1188 drivers/hwmon/w83627hf.c err = kstrtoul(buf, 10, &val); val 1194 drivers/hwmon/w83627hf.c switch (val) { val 1202 drivers/hwmon/w83627hf.c data->sens[nr] = val; val 1211 drivers/hwmon/w83627hf.c data->sens[nr] = val; val 1221 drivers/hwmon/w83627hf.c data->sens[nr] = val; val 1226 drivers/hwmon/w83627hf.c (long) val); val 1251 drivers/hwmon/w83627hf.c u16 val; val 1267 drivers/hwmon/w83627hf.c val = force_id ? force_id : superio_inb(sio_data, DEVID); val 1268 drivers/hwmon/w83627hf.c switch (val) { val 1287 drivers/hwmon/w83627hf.c pr_debug(DRVNAME ": Unsupported chip (DEVID=0x%02x)\n", val); val 1292 drivers/hwmon/w83627hf.c val = (superio_inb(sio_data, WINB_BASE_REG) << 8) | val 1294 drivers/hwmon/w83627hf.c *addr = val & WINB_ALIGNMENT; val 1300 drivers/hwmon/w83627hf.c val = superio_inb(sio_data, WINB_ACT_REG); val 1301 drivers/hwmon/w83627hf.c if (!(val & 0x01)) { val 1303 drivers/hwmon/w83627hf.c superio_outb(sio_data, WINB_ACT_REG, val | 0x01); val 61 drivers/hwmon/w83773g.c static int get_local_temp(struct regmap *regmap, long *val) val 70 drivers/hwmon/w83773g.c *val = temp_of_local(regval); val 74 drivers/hwmon/w83773g.c static int get_remote_temp(struct regmap *regmap, int index, long *val) val 88 drivers/hwmon/w83773g.c *val = temp_of_remote(regval_high, regval_low); val 92 drivers/hwmon/w83773g.c static int get_fault(struct regmap *regmap, int index, long *val) val 101 drivers/hwmon/w83773g.c *val = (regval & 0x04) >> 2; val 105 drivers/hwmon/w83773g.c static int get_offset(struct regmap *regmap, int index, long *val) val 119 drivers/hwmon/w83773g.c *val = temp_of_remote(regval_high, regval_low); val 123 drivers/hwmon/w83773g.c static int set_offset(struct regmap *regmap, int index, long val) val 129 drivers/hwmon/w83773g.c val = clamp_val(val, -127825, 127825); val 131 drivers/hwmon/w83773g.c val /= 125; val 132 drivers/hwmon/w83773g.c high_byte = val >> 3; val 133 drivers/hwmon/w83773g.c low_byte = (val & 0x07) << 5; val 142 drivers/hwmon/w83773g.c static int get_update_interval(struct regmap *regmap, long *val) val 151 drivers/hwmon/w83773g.c *val = 16000 >> regval; val 155 drivers/hwmon/w83773g.c static int set_update_interval(struct regmap *regmap, long val) val 167 drivers/hwmon/w83773g.c val = clamp_val(val, 62, 16000) * 10; val 168 drivers/hwmon/w83773g.c rate = 8 - __fls((val * 8 / (625 * 7))); val 173 drivers/hwmon/w83773g.c u32 attr, int channel, long *val) val 179 drivers/hwmon/w83773g.c return get_update_interval(regmap, val); val 186 drivers/hwmon/w83773g.c return get_local_temp(regmap, val); val 187 drivers/hwmon/w83773g.c return get_remote_temp(regmap, channel - 1, val); val 189 drivers/hwmon/w83773g.c return get_fault(regmap, channel - 1, val); val 191 drivers/hwmon/w83773g.c return get_offset(regmap, channel - 1, val); val 198 drivers/hwmon/w83773g.c u32 attr, int channel, long val) val 203 drivers/hwmon/w83773g.c return set_update_interval(regmap, val); val 206 drivers/hwmon/w83773g.c return set_offset(regmap, channel - 1, val); val 149 drivers/hwmon/w83781d.c #define IN_TO_REG(val) clamp_val(((val) + 8) / 16, 0, 255) val 150 drivers/hwmon/w83781d.c #define IN_FROM_REG(val) ((val) * 16) val 162 drivers/hwmon/w83781d.c FAN_FROM_REG(u8 val, int div) val 164 drivers/hwmon/w83781d.c if (val == 0) val 166 drivers/hwmon/w83781d.c if (val == 255) val 168 drivers/hwmon/w83781d.c return 1350000 / (val * div); val 171 drivers/hwmon/w83781d.c #define TEMP_TO_REG(val) clamp_val((val) / 1000, -127, 128) val 172 drivers/hwmon/w83781d.c #define TEMP_FROM_REG(val) ((val) * 1000) val 174 drivers/hwmon/w83781d.c #define BEEP_MASK_FROM_REG(val, type) ((type) == as99127f ? \ val 175 drivers/hwmon/w83781d.c (~(val)) & 0x7fff : (val) & 0xff7fff) val 176 drivers/hwmon/w83781d.c #define BEEP_MASK_TO_REG(val, type) ((type) == as99127f ? \ val 177 drivers/hwmon/w83781d.c (~(val)) & 0x7fff : (val) & 0xff7fff) val 179 drivers/hwmon/w83781d.c #define DIV_FROM_REG(val) (1 << (val)) val 182 drivers/hwmon/w83781d.c DIV_TO_REG(long val, enum chips type) val 185 drivers/hwmon/w83781d.c val = clamp_val(val, 1, val 188 drivers/hwmon/w83781d.c if (val == 0) val 190 drivers/hwmon/w83781d.c val >>= 1; val 266 drivers/hwmon/w83781d.c unsigned long val; \ val 267 drivers/hwmon/w83781d.c int err = kstrtoul(buf, 10, &val); \ val 271 drivers/hwmon/w83781d.c data->in_##reg[nr] = IN_TO_REG(val); \ val 319 drivers/hwmon/w83781d.c unsigned long val; val 322 drivers/hwmon/w83781d.c err = kstrtoul(buf, 10, &val); val 328 drivers/hwmon/w83781d.c FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 371 drivers/hwmon/w83781d.c long val; \ val 372 drivers/hwmon/w83781d.c int err = kstrtol(buf, 10, &val); \ val 378 drivers/hwmon/w83781d.c data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \ val 382 drivers/hwmon/w83781d.c data->temp_##reg = TEMP_TO_REG(val); \ val 426 drivers/hwmon/w83781d.c unsigned long val; val 429 drivers/hwmon/w83781d.c err = kstrtoul(buf, 10, &val); val 432 drivers/hwmon/w83781d.c data->vrm = clamp_val(val, 0, 255); val 494 drivers/hwmon/w83781d.c unsigned long val; val 497 drivers/hwmon/w83781d.c err = kstrtoul(buf, 10, &val); val 503 drivers/hwmon/w83781d.c data->beep_mask |= BEEP_MASK_TO_REG(val, data->type); val 643 drivers/hwmon/w83781d.c unsigned long val; val 646 drivers/hwmon/w83781d.c err = kstrtoul(buf, 10, &val); val 656 drivers/hwmon/w83781d.c data->fan_div[nr] = DIV_TO_REG(val, data->type); val 710 drivers/hwmon/w83781d.c unsigned long val; val 713 drivers/hwmon/w83781d.c err = kstrtoul(buf, 10, &val); val 718 drivers/hwmon/w83781d.c data->pwm[nr] = clamp_val(val, 0, 255); val 729 drivers/hwmon/w83781d.c unsigned long val; val 733 drivers/hwmon/w83781d.c err = kstrtoul(buf, 10, &val); val 739 drivers/hwmon/w83781d.c switch (val) { val 744 drivers/hwmon/w83781d.c (reg & 0xf7) | (val << 3)); val 748 drivers/hwmon/w83781d.c (reg & 0xef) | (!val << 4)); val 750 drivers/hwmon/w83781d.c data->pwm2_enable = val; val 784 drivers/hwmon/w83781d.c unsigned long val; val 788 drivers/hwmon/w83781d.c err = kstrtoul(buf, 10, &val); val 794 drivers/hwmon/w83781d.c switch (val) { val 802 drivers/hwmon/w83781d.c data->sens[nr] = val; val 811 drivers/hwmon/w83781d.c data->sens[nr] = val; val 822 drivers/hwmon/w83781d.c data->sens[nr] = val; val 826 drivers/hwmon/w83781d.c (long) val); val 1833 drivers/hwmon/w83781d.c int val, save, found = 0; val 1853 drivers/hwmon/w83781d.c val = inb_p(address + 1); val 1854 drivers/hwmon/w83781d.c if (inb_p(address + 2) != val val 1855 drivers/hwmon/w83781d.c || inb_p(address + 3) != val val 1856 drivers/hwmon/w83781d.c || inb_p(address + 7) != val) { val 1871 drivers/hwmon/w83781d.c val = ~save & 0x7f; val 1872 drivers/hwmon/w83781d.c outb_p(val, address + W83781D_ADDR_REG_OFFSET); val 1873 drivers/hwmon/w83781d.c if (inb_p(address + W83781D_ADDR_REG_OFFSET) != (val | 0x80)) { val 1881 drivers/hwmon/w83781d.c val = inb_p(address + W83781D_DATA_REG_OFFSET); val 1882 drivers/hwmon/w83781d.c if (val & 0x80) { val 1889 drivers/hwmon/w83781d.c val = inb_p(address + W83781D_DATA_REG_OFFSET); val 1890 drivers/hwmon/w83781d.c if ((!(save & 0x80) && (val != 0xa3)) val 1891 drivers/hwmon/w83781d.c || ((save & 0x80) && (val != 0x5c))) { val 1896 drivers/hwmon/w83781d.c val = inb_p(address + W83781D_DATA_REG_OFFSET); val 1897 drivers/hwmon/w83781d.c if (val < 0x03 || val > 0x77) { /* Not a valid I2C address */ val 1913 drivers/hwmon/w83781d.c val = inb_p(address + W83781D_DATA_REG_OFFSET); val 1914 drivers/hwmon/w83781d.c if ((val & 0xfe) == 0x10 /* W83781D */ val 1915 drivers/hwmon/w83781d.c || val == 0x30) /* W83782D */ val 1920 drivers/hwmon/w83781d.c val == 0x30 ? "W83782D" : "W83781D", (int)address); val 210 drivers/hwmon/w83791d.c #define IN_TO_REG(val) (clamp_val((((val) + 8) / 16), 0, 255)) val 211 drivers/hwmon/w83791d.c #define IN_FROM_REG(val) ((val) * 16) val 221 drivers/hwmon/w83791d.c #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : \ val 222 drivers/hwmon/w83791d.c ((val) == 255 ? 0 : \ val 223 drivers/hwmon/w83791d.c 1350000 / ((val) * (div)))) val 226 drivers/hwmon/w83791d.c #define TEMP1_FROM_REG(val) ((val) * 1000) val 227 drivers/hwmon/w83791d.c #define TEMP1_TO_REG(val) ((val) <= -128000 ? -128 : \ val 228 drivers/hwmon/w83791d.c (val) >= 127000 ? 127 : \ val 229 drivers/hwmon/w83791d.c (val) < 0 ? ((val) - 500) / 1000 : \ val 230 drivers/hwmon/w83791d.c ((val) + 500) / 1000) val 238 drivers/hwmon/w83791d.c #define TEMP23_FROM_REG(val) ((val) / 128 * 500) val 239 drivers/hwmon/w83791d.c #define TEMP23_TO_REG(val) (DIV_ROUND_CLOSEST(clamp_val((val), -128000, \ val 243 drivers/hwmon/w83791d.c #define TARGET_TEMP_TO_REG(val) DIV_ROUND_CLOSEST(clamp_val((val), 0, 127000), \ val 247 drivers/hwmon/w83791d.c #define TOL_TEMP_TO_REG(val) DIV_ROUND_CLOSEST(clamp_val((val), 0, 15000), \ val 250 drivers/hwmon/w83791d.c #define BEEP_MASK_TO_REG(val) ((val) & 0xffffff) val 251 drivers/hwmon/w83791d.c #define BEEP_MASK_FROM_REG(val) ((val) & 0xffffff) val 253 drivers/hwmon/w83791d.c #define DIV_FROM_REG(val) (1 << (val)) val 255 drivers/hwmon/w83791d.c static u8 div_to_reg(int nr, long val) val 260 drivers/hwmon/w83791d.c val = clamp_val(val, 1, 128) >> 1; val 262 drivers/hwmon/w83791d.c if (val == 0) val 264 drivers/hwmon/w83791d.c val >>= 1; val 378 drivers/hwmon/w83791d.c unsigned long val; \ val 379 drivers/hwmon/w83791d.c int err = kstrtoul(buf, 10, &val); \ val 383 drivers/hwmon/w83791d.c data->in_##reg[nr] = IN_TO_REG(val); \ val 452 drivers/hwmon/w83791d.c unsigned long val; val 455 drivers/hwmon/w83791d.c err = kstrtoul(buf, 10, &val); val 459 drivers/hwmon/w83791d.c val = val ? 1 : 0; val 468 drivers/hwmon/w83791d.c data->beep_mask |= val << bitnr; val 541 drivers/hwmon/w83791d.c unsigned long val; val 544 drivers/hwmon/w83791d.c err = kstrtoul(buf, 10, &val); val 549 drivers/hwmon/w83791d.c data->fan_min[nr] = fan_to_reg(val, DIV_FROM_REG(data->fan_div[nr])); val 585 drivers/hwmon/w83791d.c unsigned long val; val 588 drivers/hwmon/w83791d.c err = kstrtoul(buf, 10, &val); val 596 drivers/hwmon/w83791d.c data->fan_div[nr] = div_to_reg(nr, val); val 728 drivers/hwmon/w83791d.c unsigned long val; val 730 drivers/hwmon/w83791d.c if (kstrtoul(buf, 10, &val)) val 734 drivers/hwmon/w83791d.c data->pwm[nr] = clamp_val(val, 0, 255); val 769 drivers/hwmon/w83791d.c unsigned long val; val 775 drivers/hwmon/w83791d.c int ret = kstrtoul(buf, 10, &val); val 777 drivers/hwmon/w83791d.c if (ret || val < 1 || val > 3) val 781 drivers/hwmon/w83791d.c data->pwm_enable[nr] = val - 1; val 835 drivers/hwmon/w83791d.c long val; val 838 drivers/hwmon/w83791d.c if (kstrtol(buf, 10, &val)) val 842 drivers/hwmon/w83791d.c data->temp_target[nr] = TARGET_TEMP_TO_REG(val); val 876 drivers/hwmon/w83791d.c unsigned long val; val 882 drivers/hwmon/w83791d.c if (kstrtoul(buf, 10, &val)) val 904 drivers/hwmon/w83791d.c data->temp_tolerance[nr] = TOL_TEMP_TO_REG(val); val 938 drivers/hwmon/w83791d.c long val; val 941 drivers/hwmon/w83791d.c err = kstrtol(buf, 10, &val); val 946 drivers/hwmon/w83791d.c data->temp1[nr] = TEMP1_TO_REG(val); val 970 drivers/hwmon/w83791d.c long val; val 975 drivers/hwmon/w83791d.c err = kstrtol(buf, 10, &val); val 980 drivers/hwmon/w83791d.c data->temp_add[nr][index] = TEMP23_TO_REG(val); val 1067 drivers/hwmon/w83791d.c long val; val 1070 drivers/hwmon/w83791d.c err = kstrtol(buf, 10, &val); val 1080 drivers/hwmon/w83791d.c data->beep_mask = BEEP_MASK_TO_REG(val) & ~GLOBAL_BEEP_ENABLE_MASK; val 1083 drivers/hwmon/w83791d.c val = data->beep_mask; val 1086 drivers/hwmon/w83791d.c w83791d_write(client, W83791D_REG_BEEP_CTRL[i], (val & 0xff)); val 1087 drivers/hwmon/w83791d.c val >>= 8; val 1101 drivers/hwmon/w83791d.c long val; val 1104 drivers/hwmon/w83791d.c err = kstrtol(buf, 10, &val); val 1110 drivers/hwmon/w83791d.c data->beep_enable = val ? 1 : 0; val 1120 drivers/hwmon/w83791d.c val = (data->beep_mask >> 8) & 0xff; val 1122 drivers/hwmon/w83791d.c w83791d_write(client, W83791D_REG_BEEP_CTRL[1], val); val 1157 drivers/hwmon/w83791d.c unsigned long val; val 1166 drivers/hwmon/w83791d.c err = kstrtoul(buf, 10, &val); val 1170 drivers/hwmon/w83791d.c if (val > 255) val 1173 drivers/hwmon/w83791d.c data->vrm = val; val 1264 drivers/hwmon/w83791d.c u8 val; val 1283 drivers/hwmon/w83791d.c val = w83791d_read(client, W83791D_REG_I2C_SUBADDR); val 1284 drivers/hwmon/w83791d.c if (!(val & 0x08)) val 1286 drivers/hwmon/w83791d.c 0x48 + (val & 0x7)); val 1287 drivers/hwmon/w83791d.c if (!(val & 0x80)) { val 1289 drivers/hwmon/w83791d.c ((val & 0x7) == ((val >> 4) & 0x7))) { val 1297 drivers/hwmon/w83791d.c 0x48 + ((val >> 4) & 0x7)); val 215 drivers/hwmon/w83792d.c #define IN_FROM_REG(nr, val) (((nr) <= 1) ? ((val) * 2) : \ val 216 drivers/hwmon/w83792d.c ((((nr) == 6) || ((nr) == 7)) ? ((val) * 6) : ((val) * 4))) val 217 drivers/hwmon/w83792d.c #define IN_TO_REG(nr, val) (((nr) <= 1) ? ((val) / 2) : \ val 218 drivers/hwmon/w83792d.c ((((nr) == 6) || ((nr) == 7)) ? ((val) / 6) : ((val) / 4))) val 229 drivers/hwmon/w83792d.c #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : \ val 230 drivers/hwmon/w83792d.c ((val) == 255 ? 0 : \ val 231 drivers/hwmon/w83792d.c 1350000 / ((val) * (div)))) val 234 drivers/hwmon/w83792d.c #define TEMP1_TO_REG(val) (clamp_val(((val) < 0 ? (val) + 0x100 * 1000 \ val 235 drivers/hwmon/w83792d.c : (val)) / 1000, 0, 0xff)) val 236 drivers/hwmon/w83792d.c #define TEMP1_FROM_REG(val) (((val) & 0x80 ? (val)-0x100 : (val)) * 1000) val 241 drivers/hwmon/w83792d.c #define TEMP_ADD_TO_REG_HIGH(val) \ val 242 drivers/hwmon/w83792d.c (clamp_val(((val) < 0 ? (val) + 0x100 * 1000 : (val)) / 1000, 0, 0xff)) val 243 drivers/hwmon/w83792d.c #define TEMP_ADD_TO_REG_LOW(val) ((val%1000) ? 0x80 : 0x00) val 245 drivers/hwmon/w83792d.c #define DIV_FROM_REG(val) (1 << (val)) val 248 drivers/hwmon/w83792d.c DIV_TO_REG(long val) val 251 drivers/hwmon/w83792d.c val = clamp_val(val, 1, 128) >> 1; val 253 drivers/hwmon/w83792d.c if (val == 0) val 255 drivers/hwmon/w83792d.c val >>= 1; val 378 drivers/hwmon/w83792d.c unsigned long val; \ val 379 drivers/hwmon/w83792d.c int err = kstrtoul(buf, 10, &val); \ val 383 drivers/hwmon/w83792d.c data->in_##reg[nr] = clamp_val(IN_TO_REG(nr, val) / 4, 0, 255); \ val 416 drivers/hwmon/w83792d.c unsigned long val; val 419 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 424 drivers/hwmon/w83792d.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 460 drivers/hwmon/w83792d.c unsigned long val; val 463 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 472 drivers/hwmon/w83792d.c data->fan_div[nr] = DIV_TO_REG(val); val 507 drivers/hwmon/w83792d.c long val; val 510 drivers/hwmon/w83792d.c err = kstrtol(buf, 10, &val); val 515 drivers/hwmon/w83792d.c data->temp1[nr] = TEMP1_TO_REG(val); val 547 drivers/hwmon/w83792d.c long val; val 550 drivers/hwmon/w83792d.c err = kstrtol(buf, 10, &val); val 555 drivers/hwmon/w83792d.c data->temp_add[nr][index] = TEMP_ADD_TO_REG_HIGH(val); val 556 drivers/hwmon/w83792d.c data->temp_add[nr][index+1] = TEMP_ADD_TO_REG_LOW(val); val 625 drivers/hwmon/w83792d.c unsigned long val; val 628 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 631 drivers/hwmon/w83792d.c val = clamp_val(val, 0, 255) >> 4; val 634 drivers/hwmon/w83792d.c val |= w83792d_read_value(client, W83792D_REG_PWM[nr]) & 0xf0; val 635 drivers/hwmon/w83792d.c data->pwm[nr] = val; val 651 drivers/hwmon/w83792d.c unsigned long val; val 654 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 658 drivers/hwmon/w83792d.c if (val < 1 || val > 3) val 662 drivers/hwmon/w83792d.c switch (val) { val 702 drivers/hwmon/w83792d.c unsigned long val; val 705 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 708 drivers/hwmon/w83792d.c if (val > 1) val 713 drivers/hwmon/w83792d.c if (val) { /* PWM mode */ val 738 drivers/hwmon/w83792d.c unsigned long val; val 741 drivers/hwmon/w83792d.c if (kstrtoul(buf, 10, &val) || val != 0) val 773 drivers/hwmon/w83792d.c unsigned long val; val 776 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 780 drivers/hwmon/w83792d.c target_tmp = val; val 813 drivers/hwmon/w83792d.c unsigned long val; val 816 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 823 drivers/hwmon/w83792d.c tol_tmp = clamp_val(val, 0, 15); val 859 drivers/hwmon/w83792d.c unsigned long val; val 862 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 867 drivers/hwmon/w83792d.c data->sf2_points[index][nr] = clamp_val(val, 0, 127); val 901 drivers/hwmon/w83792d.c unsigned long val; val 904 drivers/hwmon/w83792d.c err = kstrtoul(buf, 10, &val); val 909 drivers/hwmon/w83792d.c data->sf2_levels[index][nr] = clamp_val((val * 15) / 100, 0, 15); val 929 drivers/hwmon/w83792d.c u8 val; val 949 drivers/hwmon/w83792d.c val = w83792d_read_value(new_client, W83792D_REG_I2C_SUBADDR); val 950 drivers/hwmon/w83792d.c if (!(val & 0x08)) val 952 drivers/hwmon/w83792d.c 0x48 + (val & 0x7)); val 953 drivers/hwmon/w83792d.c if (!(val & 0x80)) { val 955 drivers/hwmon/w83792d.c ((val & 0x7) == ((val >> 4) & 0x7))) { val 962 drivers/hwmon/w83792d.c 0x48 + ((val >> 4) & 0x7)); val 170 drivers/hwmon/w83793.c static inline unsigned long FAN_FROM_REG(u16 val) val 172 drivers/hwmon/w83793.c if ((val >= 0xfff) || (val == 0)) val 174 drivers/hwmon/w83793.c return 1350000UL / val; val 189 drivers/hwmon/w83793.c static inline u8 TIME_TO_REG(unsigned long val) val 191 drivers/hwmon/w83793.c return clamp_val((val + 50) / 100, 0, 0xff); val 199 drivers/hwmon/w83793.c static inline s8 TEMP_TO_REG(long val, s8 min, s8 max) val 201 drivers/hwmon/w83793.c return clamp_val((val + (val < 0 ? -500 : 500)) / 1000, min, max); val 336 drivers/hwmon/w83793.c unsigned long val; val 339 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 343 drivers/hwmon/w83793.c if (val > 255) val 346 drivers/hwmon/w83793.c data->vrm = val; val 361 drivers/hwmon/w83793.c u8 val; val 364 drivers/hwmon/w83793.c val = (data->alarms[index] >> (bit)) & 1; val 366 drivers/hwmon/w83793.c val = (data->beeps[index] >> (bit)) & 1; val 369 drivers/hwmon/w83793.c return sprintf(buf, "%u\n", val); val 383 drivers/hwmon/w83793.c unsigned long val; val 386 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 390 drivers/hwmon/w83793.c if (val > 1) val 396 drivers/hwmon/w83793.c data->beeps[index] |= val << shift; val 416 drivers/hwmon/w83793.c unsigned long val; val 419 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 423 drivers/hwmon/w83793.c if (val > 1) val 429 drivers/hwmon/w83793.c data->beep_enable |= val << 1; val 444 drivers/hwmon/w83793.c unsigned long val; val 448 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 451 drivers/hwmon/w83793.c if (val) val 472 drivers/hwmon/w83793.c u16 val; val 475 drivers/hwmon/w83793.c val = data->fan[index] & 0x0fff; val 477 drivers/hwmon/w83793.c val = data->fan_min[index] & 0x0fff; val 479 drivers/hwmon/w83793.c return sprintf(buf, "%lu\n", FAN_FROM_REG(val)); val 491 drivers/hwmon/w83793.c unsigned long val; val 494 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 497 drivers/hwmon/w83793.c val = FAN_TO_REG(val); val 500 drivers/hwmon/w83793.c data->fan_min[index] = val; val 502 drivers/hwmon/w83793.c (val >> 8) & 0xff); val 503 drivers/hwmon/w83793.c w83793_write_value(client, W83793_REG_FAN_MIN(index) + 1, val & 0xff); val 515 drivers/hwmon/w83793.c u16 val; val 520 drivers/hwmon/w83793.c val = TIME_FROM_REG(data->pwm_stop_time[index]); val 522 drivers/hwmon/w83793.c val = (data->pwm[index][nr] & 0x3f) << 2; val 524 drivers/hwmon/w83793.c return sprintf(buf, "%d\n", val); val 537 drivers/hwmon/w83793.c unsigned long val; val 540 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 546 drivers/hwmon/w83793.c val = TIME_TO_REG(val); val 547 drivers/hwmon/w83793.c data->pwm_stop_time[index] = val; val 549 drivers/hwmon/w83793.c val); val 551 drivers/hwmon/w83793.c val = clamp_val(val, 0, 0xff) >> 2; val 554 drivers/hwmon/w83793.c data->pwm[index][nr] |= val; val 656 drivers/hwmon/w83793.c unsigned long val; val 659 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 664 drivers/hwmon/w83793.c if ((val == 6) && (index < 4)) { val 665 drivers/hwmon/w83793.c val -= 3; val 666 drivers/hwmon/w83793.c } else if ((val == 3 && index < 4) val 667 drivers/hwmon/w83793.c || (val == 4 && index >= 4)) { val 669 drivers/hwmon/w83793.c val = !!val; val 679 drivers/hwmon/w83793.c data->temp_mode[index] |= val << shift; val 698 drivers/hwmon/w83793.c u32 val = 0; val 701 drivers/hwmon/w83793.c val = (data->pwm_default & 0x3f) << 2; val 703 drivers/hwmon/w83793.c val = TIME_FROM_REG(data->pwm_uptime); val 705 drivers/hwmon/w83793.c val = TIME_FROM_REG(data->pwm_downtime); val 707 drivers/hwmon/w83793.c val = TEMP_FROM_REG(data->temp_critical & 0x7f); val 709 drivers/hwmon/w83793.c return sprintf(buf, "%d\n", val); val 721 drivers/hwmon/w83793.c long val; val 724 drivers/hwmon/w83793.c err = kstrtol(buf, 10, &val); val 732 drivers/hwmon/w83793.c data->pwm_default |= clamp_val(val, 0, 0xff) >> 2; val 736 drivers/hwmon/w83793.c data->pwm_uptime = TIME_TO_REG(val); val 741 drivers/hwmon/w83793.c data->pwm_downtime = TIME_TO_REG(val); val 748 drivers/hwmon/w83793.c data->temp_critical |= TEMP_TO_REG(val, 0, 0x7f); val 796 drivers/hwmon/w83793.c u32 val; val 799 drivers/hwmon/w83793.c val = data->temp_fan_map[index]; val 802 drivers/hwmon/w83793.c val = ((data->pwm_enable >> index) & 0x01) + 2; val 804 drivers/hwmon/w83793.c val = TEMP_FROM_REG(data->temp_cruise[index] & 0x7f); val 806 drivers/hwmon/w83793.c val = data->tolerance[index >> 1] >> ((index & 0x01) ? 4 : 0); val 807 drivers/hwmon/w83793.c val = TEMP_FROM_REG(val & 0x0f); val 809 drivers/hwmon/w83793.c return sprintf(buf, "%d\n", val); val 822 drivers/hwmon/w83793.c long val; val 825 drivers/hwmon/w83793.c err = kstrtol(buf, 10, &val); val 831 drivers/hwmon/w83793.c val = clamp_val(val, 0, 255); val 832 drivers/hwmon/w83793.c w83793_write_value(client, W83793_REG_TEMP_FAN_MAP(index), val); val 833 drivers/hwmon/w83793.c data->temp_fan_map[index] = val; val 835 drivers/hwmon/w83793.c if (val == 2 || val == 3) { val 838 drivers/hwmon/w83793.c if (val - 2) val 852 drivers/hwmon/w83793.c data->temp_cruise[index] |= TEMP_TO_REG(val, 0, 0x7f); val 863 drivers/hwmon/w83793.c data->tolerance[i] |= TEMP_TO_REG(val, 0, 0x0f) << shift; val 894 drivers/hwmon/w83793.c unsigned long val; val 897 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 900 drivers/hwmon/w83793.c val = clamp_val(val, 0, 0xff) >> 2; val 905 drivers/hwmon/w83793.c data->sf2_pwm[index][nr] |= val; val 935 drivers/hwmon/w83793.c long val; val 938 drivers/hwmon/w83793.c err = kstrtol(buf, 10, &val); val 941 drivers/hwmon/w83793.c val = TEMP_TO_REG(val, 0, 0x7f); val 946 drivers/hwmon/w83793.c data->sf2_temp[index][nr] |= val; val 962 drivers/hwmon/w83793.c u16 val = data->in[index][nr]; val 965 drivers/hwmon/w83793.c val <<= 2; val 966 drivers/hwmon/w83793.c val += (data->in_low_bits[nr] >> (index * 2)) & 0x3; val 969 drivers/hwmon/w83793.c val = val * scale_in[index] + scale_in_add[index]; val 970 drivers/hwmon/w83793.c return sprintf(buf, "%d\n", val); val 983 drivers/hwmon/w83793.c unsigned long val; val 986 drivers/hwmon/w83793.c err = kstrtoul(buf, 10, &val); val 989 drivers/hwmon/w83793.c val = (val + scale_in[index] / 2) / scale_in[index]; val 995 drivers/hwmon/w83793.c val -= scale_in_add[index] / scale_in[index]; val 996 drivers/hwmon/w83793.c val = clamp_val(val, 0, 255); val 998 drivers/hwmon/w83793.c val = clamp_val(val, 0, 0x3FF); val 1002 drivers/hwmon/w83793.c data->in_low_bits[nr] |= (val & 0x03) << (2 * index); val 1005 drivers/hwmon/w83793.c val >>= 2; val 1007 drivers/hwmon/w83793.c data->in[index][nr] = val; val 1395 drivers/hwmon/w83793.c int val, ret = 0; val 1407 drivers/hwmon/w83793.c val = data->watchdog_caused_reboot ? WDIOF_CARDRESET : 0; val 1408 drivers/hwmon/w83793.c ret = put_user(val, (int __user *)arg); val 1420 drivers/hwmon/w83793.c val = watchdog_get_timeout(data); val 1421 drivers/hwmon/w83793.c ret = put_user(val, (int __user *)arg); val 1425 drivers/hwmon/w83793.c if (get_user(val, (int __user *)arg)) { val 1429 drivers/hwmon/w83793.c ret = watchdog_set_timeout(data, val); val 1435 drivers/hwmon/w83793.c if (get_user(val, (int __user *)arg)) { val 1440 drivers/hwmon/w83793.c if (val & WDIOS_DISABLECARD) val 1442 drivers/hwmon/w83793.c else if (val & WDIOS_ENABLECARD) val 1656 drivers/hwmon/w83793.c int i, tmp, val, err; val 1695 drivers/hwmon/w83793.c val = w83793_read_value(client, W83793_REG_FANIN_CTRL); val 1702 drivers/hwmon/w83793.c if (val & 0x01) { /* fan 6 */ val 1706 drivers/hwmon/w83793.c if (val & 0x02) { /* fan 7 */ val 1710 drivers/hwmon/w83793.c if (!(tmp & 0x40) && (val & 0x04)) { /* fan 8 */ val 1720 drivers/hwmon/w83793.c if (val & 0x08) /* fan 9 */ val 1722 drivers/hwmon/w83793.c if (val & 0x10) /* fan 10 */ val 1726 drivers/hwmon/w83793.c if (val & 0x20) /* fan 11 */ val 1728 drivers/hwmon/w83793.c if (val & 0x40) /* fan 12 */ val 1732 drivers/hwmon/w83793.c if ((tmp & 0x01) && (val & 0x04)) { /* fan 8, second location */ val 1738 drivers/hwmon/w83793.c if ((tmp & 0x01) && (val & 0x08)) { /* fan 9, second location */ val 1741 drivers/hwmon/w83793.c if ((tmp & 0x02) && (val & 0x10)) { /* fan 10, second location */ val 1744 drivers/hwmon/w83793.c if ((tmp & 0x04) && (val & 0x20)) { /* fan 11, second location */ val 1747 drivers/hwmon/w83793.c if ((tmp & 0x08) && (val & 0x40)) { /* fan 12, second location */ val 225 drivers/hwmon/w83795.c static inline u16 in_from_reg(u8 index, u16 val) val 229 drivers/hwmon/w83795.c return val * 6; val 231 drivers/hwmon/w83795.c return val * 2; val 234 drivers/hwmon/w83795.c static inline u16 in_to_reg(u8 index, u16 val) val 237 drivers/hwmon/w83795.c return val / 6; val 239 drivers/hwmon/w83795.c return val / 2; val 242 drivers/hwmon/w83795.c static inline unsigned long fan_from_reg(u16 val) val 244 drivers/hwmon/w83795.c if ((val == 0xfff) || (val == 0)) val 246 drivers/hwmon/w83795.c return 1350000UL / val; val 261 drivers/hwmon/w83795.c static inline u8 time_to_reg(unsigned long val) val 263 drivers/hwmon/w83795.c return clamp_val((val + 50) / 100, 0, 0xff); val 271 drivers/hwmon/w83795.c static inline s8 temp_to_reg(long val, s8 min, s8 max) val 273 drivers/hwmon/w83795.c return clamp_val(val / 1000, min, max); val 292 drivers/hwmon/w83795.c static u8 pwm_freq_to_reg(unsigned long val, u16 clkin) val 299 drivers/hwmon/w83795.c reg0 = find_closest_descending(val, pwm_freq_cksel0, val 301 drivers/hwmon/w83795.c if (val < 375) /* cksel = 1 can't beat this */ val 307 drivers/hwmon/w83795.c reg1 = clamp_val(DIV_ROUND_CLOSEST(base_clock, val), 1, 128); val 312 drivers/hwmon/w83795.c if (abs(val - best0) > abs(val - best1)) val 709 drivers/hwmon/w83795.c u8 val; val 712 drivers/hwmon/w83795.c val = (data->alarms[index] >> bit) & 1; val 714 drivers/hwmon/w83795.c val = (data->beeps[index] >> bit) & 1; val 716 drivers/hwmon/w83795.c return sprintf(buf, "%u\n", val); val 730 drivers/hwmon/w83795.c unsigned long val; val 732 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 734 drivers/hwmon/w83795.c if (val != 0 && val != 1) val 740 drivers/hwmon/w83795.c data->beeps[index] |= val << shift; val 755 drivers/hwmon/w83795.c unsigned long val; val 757 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0 || val != 0) val 761 drivers/hwmon/w83795.c val = w83795_read(client, W83795_REG_CLR_CHASSIS); val 762 drivers/hwmon/w83795.c val |= 0x80; val 763 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_CLR_CHASSIS, val); val 782 drivers/hwmon/w83795.c u16 val; val 785 drivers/hwmon/w83795.c val = data->fan[index] & 0x0fff; val 787 drivers/hwmon/w83795.c val = data->fan_min[index] & 0x0fff; val 789 drivers/hwmon/w83795.c return sprintf(buf, "%lu\n", fan_from_reg(val)); val 801 drivers/hwmon/w83795.c unsigned long val; val 803 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val)) val 805 drivers/hwmon/w83795.c val = fan_to_reg(val); val 808 drivers/hwmon/w83795.c data->fan_min[index] = val; val 809 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_FAN_MIN_HL(index), (val >> 4) & 0xff); val 810 drivers/hwmon/w83795.c val &= 0x0f; val 812 drivers/hwmon/w83795.c val <<= 4; val 813 drivers/hwmon/w83795.c val |= w83795_read(client, W83795_REG_FAN_MIN_LSB(index)) val 816 drivers/hwmon/w83795.c val |= w83795_read(client, W83795_REG_FAN_MIN_LSB(index)) val 819 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_FAN_MIN_LSB(index), val & 0xff); val 833 drivers/hwmon/w83795.c unsigned int val; val 840 drivers/hwmon/w83795.c val = time_from_reg(data->pwm[index][nr]); val 843 drivers/hwmon/w83795.c val = pwm_freq_from_reg(data->pwm[index][nr], data->clkin); val 846 drivers/hwmon/w83795.c val = data->pwm[index][nr]; val 850 drivers/hwmon/w83795.c return sprintf(buf, "%u\n", val); val 863 drivers/hwmon/w83795.c unsigned long val; val 865 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 871 drivers/hwmon/w83795.c val = time_to_reg(val); val 874 drivers/hwmon/w83795.c val = pwm_freq_to_reg(val, data->clkin); val 877 drivers/hwmon/w83795.c val = clamp_val(val, 0, 0xff); val 880 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_PWM(index, nr), val); val 881 drivers/hwmon/w83795.c data->pwm[index][nr] = val; val 923 drivers/hwmon/w83795.c unsigned long val; val 926 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 928 drivers/hwmon/w83795.c if (val < 1 || val > 2) val 932 drivers/hwmon/w83795.c if (val > 1) { val 940 drivers/hwmon/w83795.c switch (val) { val 1029 drivers/hwmon/w83795.c u8 val = index / 2; val 1046 drivers/hwmon/w83795.c data->temp_src[val] &= 0x0f; val 1048 drivers/hwmon/w83795.c data->temp_src[val] &= 0xf0; val 1050 drivers/hwmon/w83795.c data->temp_src[val] |= tmp; val 1051 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_TSS(val), data->temp_src[val]); val 1157 drivers/hwmon/w83795.c unsigned long val; val 1159 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 1165 drivers/hwmon/w83795.c val = fan_to_reg(clamp_val(val, 0, 0xfff)); val 1166 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_FTSH(index), val >> 4); val 1167 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_FTSL(index), (val << 4) & 0xf0); val 1168 drivers/hwmon/w83795.c data->target_speed[index] = val; val 1171 drivers/hwmon/w83795.c val = clamp_val(val, 0, 0x3f); val 1172 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_TFTS, val); val 1173 drivers/hwmon/w83795.c data->tol_speed = val; val 1205 drivers/hwmon/w83795.c unsigned long val; val 1208 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 1210 drivers/hwmon/w83795.c val /= 1000; val 1215 drivers/hwmon/w83795.c val = clamp_val(val, 0, 0x7f); val 1216 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_TTTI(index), val); val 1219 drivers/hwmon/w83795.c val = clamp_val(val, 0, 0x7f); val 1220 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_CTFS(index), val); val 1223 drivers/hwmon/w83795.c val = clamp_val(val, 0, 0x0f); val 1226 drivers/hwmon/w83795.c tmp |= (val << 4) & 0xf0; val 1230 drivers/hwmon/w83795.c val = clamp_val(val, 0, 0x0f); val 1233 drivers/hwmon/w83795.c tmp |= val & 0x0f; val 1237 drivers/hwmon/w83795.c data->pwm_temp[index][nr] = val; val 1265 drivers/hwmon/w83795.c unsigned long val; val 1267 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 1271 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_SF4_PWM(index, nr), val); val 1272 drivers/hwmon/w83795.c data->sf4_reg[index][SF4_PWM][nr] = val; val 1301 drivers/hwmon/w83795.c unsigned long val; val 1303 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 1305 drivers/hwmon/w83795.c val /= 1000; val 1308 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_SF4_TEMP(index, nr), val); val 1309 drivers/hwmon/w83795.c data->sf4_reg[index][SF4_TEMP][nr] = val; val 1443 drivers/hwmon/w83795.c unsigned long val; val 1446 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 1448 drivers/hwmon/w83795.c if ((val != 4) && (val != 3)) val 1452 drivers/hwmon/w83795.c if (val == 3) { val 1454 drivers/hwmon/w83795.c val = 0x01; val 1456 drivers/hwmon/w83795.c } else if (val == 4) { val 1458 drivers/hwmon/w83795.c val = 0x03; val 1465 drivers/hwmon/w83795.c tmp |= val << reg_shift; val 1482 drivers/hwmon/w83795.c u16 val = data->in[index][nr]; val 1490 drivers/hwmon/w83795.c val *= 8; val 1495 drivers/hwmon/w83795.c val <<= 2; val 1496 drivers/hwmon/w83795.c val |= (data->in_lsb[lsb_idx][nr] >> val 1500 drivers/hwmon/w83795.c val *= 8; val 1503 drivers/hwmon/w83795.c val = in_from_reg(index, val); val 1505 drivers/hwmon/w83795.c return sprintf(buf, "%d\n", val); val 1518 drivers/hwmon/w83795.c unsigned long val; val 1522 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 1524 drivers/hwmon/w83795.c val = in_to_reg(index, val); val 1528 drivers/hwmon/w83795.c val /= 8; val 1529 drivers/hwmon/w83795.c val = clamp_val(val, 0, 0x3FF); val 1535 drivers/hwmon/w83795.c tmp |= (val & 0x03) << IN_LSB_SHIFT_IDX[index][IN_LSB_SHIFT]; val 1539 drivers/hwmon/w83795.c tmp = (val >> 2) & 0xff; val 1556 drivers/hwmon/w83795.c u16 val = data->setup_pwm[nr]; val 1561 drivers/hwmon/w83795.c val = time_from_reg(val); val 1565 drivers/hwmon/w83795.c return sprintf(buf, "%d\n", val); val 1577 drivers/hwmon/w83795.c unsigned long val; val 1579 drivers/hwmon/w83795.c if (kstrtoul(buf, 10, &val) < 0) val 1584 drivers/hwmon/w83795.c val = clamp_val(val, 0, 0xff); val 1588 drivers/hwmon/w83795.c val = time_to_reg(val); val 1589 drivers/hwmon/w83795.c if (val == 0) val 1595 drivers/hwmon/w83795.c data->setup_pwm[nr] = val; val 1596 drivers/hwmon/w83795.c w83795_write(client, W83795_REG_SETUP_PWM(nr), val); val 59 drivers/hwmon/w83l785ts.c #define TEMP_FROM_REG(val) ((val) * 1000) val 80 drivers/hwmon/w83l786ng.c #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : \ val 81 drivers/hwmon/w83l786ng.c ((val) == 255 ? 0 : \ val 82 drivers/hwmon/w83l786ng.c 1350000 / ((val) * (div)))) val 85 drivers/hwmon/w83l786ng.c #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (val) + 0x100 * 1000 \ val 86 drivers/hwmon/w83l786ng.c : (val)) / 1000, 0, 0xff)) val 87 drivers/hwmon/w83l786ng.c #define TEMP_FROM_REG(val) (((val) & 0x80 ? \ val 88 drivers/hwmon/w83l786ng.c (val) - 0x100 : (val)) * 1000) val 95 drivers/hwmon/w83l786ng.c #define IN_TO_REG(val) (clamp_val((((val) + 4) / 8), 0, 255)) val 96 drivers/hwmon/w83l786ng.c #define IN_FROM_REG(val) ((val) * 8) val 98 drivers/hwmon/w83l786ng.c #define DIV_FROM_REG(val) (1 << (val)) val 101 drivers/hwmon/w83l786ng.c DIV_TO_REG(long val) val 104 drivers/hwmon/w83l786ng.c val = clamp_val(val, 1, 128) >> 1; val 106 drivers/hwmon/w83l786ng.c if (val == 0) val 108 drivers/hwmon/w83l786ng.c val >>= 1; val 244 drivers/hwmon/w83l786ng.c unsigned long val; \ val 245 drivers/hwmon/w83l786ng.c int err = kstrtoul(buf, 10, &val); \ val 249 drivers/hwmon/w83l786ng.c data->in_##reg[nr] = IN_TO_REG(val); \ val 297 drivers/hwmon/w83l786ng.c unsigned long val; val 300 drivers/hwmon/w83l786ng.c err = kstrtoul(buf, 10, &val); val 305 drivers/hwmon/w83l786ng.c data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); val 342 drivers/hwmon/w83l786ng.c unsigned long val; val 345 drivers/hwmon/w83l786ng.c err = kstrtoul(buf, 10, &val); val 353 drivers/hwmon/w83l786ng.c data->fan_div[nr] = DIV_TO_REG(val); val 426 drivers/hwmon/w83l786ng.c long val; val 429 drivers/hwmon/w83l786ng.c err = kstrtol(buf, 10, &val); val 434 drivers/hwmon/w83l786ng.c data->temp[nr][index] = TEMP_TO_REG(val); val 482 drivers/hwmon/w83l786ng.c unsigned long val; val 485 drivers/hwmon/w83l786ng.c err = kstrtoul(buf, 10, &val); val 489 drivers/hwmon/w83l786ng.c if (val > 1) val 492 drivers/hwmon/w83l786ng.c data->pwm_mode[nr] = val; val 495 drivers/hwmon/w83l786ng.c if (!val) val 509 drivers/hwmon/w83l786ng.c unsigned long val; val 512 drivers/hwmon/w83l786ng.c err = kstrtoul(buf, 10, &val); val 515 drivers/hwmon/w83l786ng.c val = clamp_val(val, 0, 255); val 516 drivers/hwmon/w83l786ng.c val = DIV_ROUND_CLOSEST(val, 0x11); val 519 drivers/hwmon/w83l786ng.c data->pwm[nr] = val * 0x11; val 520 drivers/hwmon/w83l786ng.c val |= w83l786ng_read_value(client, W83L786NG_REG_PWM[nr]) & 0xf0; val 521 drivers/hwmon/w83l786ng.c w83l786ng_write_value(client, W83L786NG_REG_PWM[nr], val); val 534 drivers/hwmon/w83l786ng.c unsigned long val; val 537 drivers/hwmon/w83l786ng.c err = kstrtoul(buf, 10, &val); val 541 drivers/hwmon/w83l786ng.c if (!val || val > 2) /* only modes 1 and 2 are supported */ val 546 drivers/hwmon/w83l786ng.c data->pwm_enable[nr] = val; val 548 drivers/hwmon/w83l786ng.c reg |= (val - 1) << W83L786NG_PWM_ENABLE_SHIFT[nr]; val 590 drivers/hwmon/w83l786ng.c unsigned long val; val 593 drivers/hwmon/w83l786ng.c err = kstrtoul(buf, 10, &val); val 600 drivers/hwmon/w83l786ng.c tol_tmp = clamp_val(val, 0, 15); val 30 drivers/hwmon/wm8350-hwmon.c int val; val 32 drivers/hwmon/wm8350-hwmon.c val = wm8350_read_auxadc(wm8350, channel, 0, 0) * WM8350_AUX_COEFF; val 33 drivers/hwmon/wm8350-hwmon.c val = DIV_ROUND_CLOSEST(val, 1000); val 35 drivers/hwmon/wm8350-hwmon.c return sprintf(buf, "%d\n", val); val 121 drivers/hwmon/xgene-hwmon.c u16 ret, val; val 123 drivers/hwmon/xgene-hwmon.c val = le16_to_cpu(READ_ONCE(*addr)); val 124 drivers/hwmon/xgene-hwmon.c ret = val & mask; val 125 drivers/hwmon/xgene-hwmon.c val &= ~mask; val 126 drivers/hwmon/xgene-hwmon.c WRITE_ONCE(*addr, cpu_to_le16(val)); val 136 drivers/hwmon/xgene-hwmon.c u16 val; val 151 drivers/hwmon/xgene-hwmon.c val = le16_to_cpu(READ_ONCE(generic_comm_base->status)); val 152 drivers/hwmon/xgene-hwmon.c val &= ~PCCS_CMD_COMPLETE; val 153 drivers/hwmon/xgene-hwmon.c WRITE_ONCE(generic_comm_base->status, cpu_to_le16(val)); val 276 drivers/hwmon/xgene-hwmon.c static int xgene_hwmon_get_cpu_pwr(struct xgene_hwmon_dev *ctx, u32 *val) val 289 drivers/hwmon/xgene-hwmon.c *val = WATT_TO_mWATT(watt) + mwatt; val 293 drivers/hwmon/xgene-hwmon.c static int xgene_hwmon_get_io_pwr(struct xgene_hwmon_dev *ctx, u32 *val) val 306 drivers/hwmon/xgene-hwmon.c *val = WATT_TO_mWATT(watt) + mwatt; val 310 drivers/hwmon/xgene-hwmon.c static int xgene_hwmon_get_temp(struct xgene_hwmon_dev *ctx, u32 *val) val 312 drivers/hwmon/xgene-hwmon.c return xgene_hwmon_reg_map_rd(ctx, SOC_TEMP_REG, val); val 324 drivers/hwmon/xgene-hwmon.c u32 val; val 326 drivers/hwmon/xgene-hwmon.c rc = xgene_hwmon_get_temp(ctx, &val); val 330 drivers/hwmon/xgene-hwmon.c temp = sign_extend32(val, TEMP_NEGATIVE_BIT); val 370 drivers/hwmon/xgene-hwmon.c u32 val; val 373 drivers/hwmon/xgene-hwmon.c rc = xgene_hwmon_get_cpu_pwr(ctx, &val); val 377 drivers/hwmon/xgene-hwmon.c return snprintf(buf, PAGE_SIZE, "%u\n", mWATT_TO_uWATT(val)); val 385 drivers/hwmon/xgene-hwmon.c u32 val; val 388 drivers/hwmon/xgene-hwmon.c rc = xgene_hwmon_get_io_pwr(ctx, &val); val 392 drivers/hwmon/xgene-hwmon.c return snprintf(buf, PAGE_SIZE, "%u\n", mWATT_TO_uWATT(val)); val 94 drivers/hwspinlock/u8500_hsem.c ulong val; val 108 drivers/hwspinlock/u8500_hsem.c val = readl(io_base + HSEM_CTRL_REG); val 109 drivers/hwspinlock/u8500_hsem.c writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); val 76 drivers/hwtracing/coresight/coresight-catu.h catu_write_##name(struct catu_drvdata *drvdata, u32 val) \ val 78 drivers/hwtracing/coresight/coresight-catu.h coresight_write_reg_pair(drvdata->base, val, offset, -1); \ val 88 drivers/hwtracing/coresight/coresight-catu.h catu_write_##name(struct catu_drvdata *drvdata, u64 val) \ val 90 drivers/hwtracing/coresight/coresight-catu.h coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ val 475 drivers/hwtracing/coresight/coresight-cpu-debug.c u8 val; val 478 drivers/hwtracing/coresight/coresight-cpu-debug.c ret = kstrtou8_from_user(buf, count, 2, &val); val 484 drivers/hwtracing/coresight/coresight-cpu-debug.c if (val == debug_enable) val 487 drivers/hwtracing/coresight/coresight-cpu-debug.c if (val) val 494 drivers/hwtracing/coresight/coresight-cpu-debug.c __func__, val ? "enable" : "disable", ret); val 498 drivers/hwtracing/coresight/coresight-cpu-debug.c debug_enable = val; val 684 drivers/hwtracing/coresight/coresight-etb10.c unsigned long val = drvdata->trigger_cntr; val 686 drivers/hwtracing/coresight/coresight-etb10.c return sprintf(buf, "%#lx\n", val); val 694 drivers/hwtracing/coresight/coresight-etb10.c unsigned long val; val 697 drivers/hwtracing/coresight/coresight-etb10.c ret = kstrtoul(buf, 16, &val); val 701 drivers/hwtracing/coresight/coresight-etb10.c drvdata->trigger_cntr = val; val 15 drivers/hwtracing/coresight/coresight-etm-cp14.c int etm_readl_cp14(u32 reg, unsigned int *val) val 19 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCR); val 22 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCCR); val 25 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMTRIGGER); val 28 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSR); val 31 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSCR); val 34 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMTSSCR); val 37 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMTEEVR); val 40 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMTECR1); val 43 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMFFLR); val 46 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR0); val 49 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR1); val 52 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR2); val 55 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR3); val 58 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR4); val 61 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR5); val 64 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR6); val 67 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR7); val 70 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR8); val 73 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR9); val 76 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR10); val 79 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR11); val 82 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR12); val 85 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR13); val 88 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR14); val 91 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACVR15); val 94 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR0); val 97 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR1); val 100 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR2); val 103 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR3); val 106 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR4); val 109 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR5); val 112 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR6); val 115 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR7); val 118 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR8); val 121 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR9); val 124 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR10); val 127 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR11); val 130 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR12); val 133 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR13); val 136 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR14); val 139 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMACTR15); val 142 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTRLDVR0); val 145 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTRLDVR1); val 148 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTRLDVR2); val 151 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTRLDVR3); val 154 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTENR0); val 157 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTENR1); val 160 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTENR2); val 163 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTENR3); val 166 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTRLDEVR0); val 169 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTRLDEVR1); val 172 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTRLDEVR2); val 175 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTRLDEVR3); val 178 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTVR0); val 181 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTVR1); val 184 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTVR2); val 187 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCNTVR3); val 190 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSQ12EVR); val 193 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSQ21EVR); val 196 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSQ23EVR); val 199 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSQ31EVR); val 202 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSQ32EVR); val 205 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSQ13EVR); val 208 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSQR); val 211 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMEXTOUTEVR0); val 214 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMEXTOUTEVR1); val 217 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMEXTOUTEVR2); val 220 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMEXTOUTEVR3); val 223 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCIDCVR0); val 226 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCIDCVR1); val 229 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCIDCVR2); val 232 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCIDCMR); val 235 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIMPSPEC0); val 238 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIMPSPEC1); val 241 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIMPSPEC2); val 244 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIMPSPEC3); val 247 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIMPSPEC4); val 250 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIMPSPEC5); val 253 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIMPSPEC6); val 256 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIMPSPEC7); val 259 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMSYNCFR); val 262 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMIDR); val 265 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMCCER); val 268 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMEXTINSELR); val 271 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMTESSEICR); val 274 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMEIBCR); val 277 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMTSEVR); val 280 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMAUXCR); val 283 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMTRACEIDR); val 286 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMVMIDCVR); val 289 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMOSLSR); val 292 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMOSSRR); val 295 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMPDCR); val 298 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = etm_read(ETMPDSR); val 301 drivers/hwtracing/coresight/coresight-etm-cp14.c *val = 0; val 306 drivers/hwtracing/coresight/coresight-etm-cp14.c int etm_writel_cp14(u32 reg, u32 val) val 310 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCR); val 313 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMTRIGGER); val 316 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSR); val 319 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMTSSCR); val 322 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMTEEVR); val 325 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMTECR1); val 328 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMFFLR); val 331 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR0); val 334 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR1); val 337 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR2); val 340 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR3); val 343 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR4); val 346 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR5); val 349 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR6); val 352 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR7); val 355 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR8); val 358 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR9); val 361 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR10); val 364 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR11); val 367 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR12); val 370 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR13); val 373 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR14); val 376 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACVR15); val 379 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR0); val 382 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR1); val 385 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR2); val 388 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR3); val 391 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR4); val 394 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR5); val 397 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR6); val 400 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR7); val 403 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR8); val 406 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR9); val 409 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR10); val 412 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR11); val 415 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR12); val 418 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR13); val 421 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR14); val 424 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMACTR15); val 427 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTRLDVR0); val 430 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTRLDVR1); val 433 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTRLDVR2); val 436 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTRLDVR3); val 439 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTENR0); val 442 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTENR1); val 445 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTENR2); val 448 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTENR3); val 451 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTRLDEVR0); val 454 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTRLDEVR1); val 457 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTRLDEVR2); val 460 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTRLDEVR3); val 463 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTVR0); val 466 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTVR1); val 469 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTVR2); val 472 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCNTVR3); val 475 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSQ12EVR); val 478 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSQ21EVR); val 481 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSQ23EVR); val 484 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSQ31EVR); val 487 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSQ32EVR); val 490 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSQ13EVR); val 493 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSQR); val 496 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMEXTOUTEVR0); val 499 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMEXTOUTEVR1); val 502 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMEXTOUTEVR2); val 505 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMEXTOUTEVR3); val 508 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCIDCVR0); val 511 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCIDCVR1); val 514 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCIDCVR2); val 517 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMCIDCMR); val 520 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMIMPSPEC0); val 523 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMIMPSPEC1); val 526 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMIMPSPEC2); val 529 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMIMPSPEC3); val 532 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMIMPSPEC4); val 535 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMIMPSPEC5); val 538 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMIMPSPEC6); val 541 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMIMPSPEC7); val 544 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMSYNCFR); val 547 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMEXTINSELR); val 550 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMTESSEICR); val 553 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMEIBCR); val 556 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMTSEVR); val 559 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMAUXCR); val 562 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMTRACEIDR); val 565 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMVMIDCVR); val 568 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMOSLAR); val 571 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMOSSRR); val 574 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMPDCR); val 577 drivers/hwtracing/coresight/coresight-etm-cp14.c etm_write(val, ETMPDSR); val 257 drivers/hwtracing/coresight/coresight-etm.h u32 val, u32 off) val 260 drivers/hwtracing/coresight/coresight-etm.h if (etm_writel_cp14(off, val)) { val 265 drivers/hwtracing/coresight/coresight-etm.h writel_relaxed(val, drvdata->base + off); val 271 drivers/hwtracing/coresight/coresight-etm.h u32 val; val 274 drivers/hwtracing/coresight/coresight-etm.h if (etm_readl_cp14(off, &val)) { val 279 drivers/hwtracing/coresight/coresight-etm.h val = readl_relaxed(drvdata->base + off); val 282 drivers/hwtracing/coresight/coresight-etm.h return val; val 16 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 19 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = drvdata->nr_addr_cmp; val 20 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 26 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c { unsigned long val; val 29 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = drvdata->nr_cntr; val 30 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 37 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 40 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = drvdata->nr_ctxid_cmp; val 41 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 48 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long flags, val; val 55 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = etm_readl(drvdata, ETMSR); val 61 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 70 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 74 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 78 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c if (val) { val 98 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 102 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->mode; val 103 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 111 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 115 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 120 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->mode = val & ETM_MODE_ALL; val 183 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 187 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->trigger_event; val 188 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 196 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 200 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 204 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->trigger_event = val & ETM_EVENT_MASK; val 213 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 217 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->enable_event; val 218 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 226 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 230 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 234 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->enable_event = val & ETM_EVENT_MASK; val 243 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 247 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->fifofull_level; val 248 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 256 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 260 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 264 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->fifofull_level = val; val 273 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 277 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->addr_idx; val 278 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 286 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 290 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 294 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c if (val >= drvdata->nr_addr_cmp) val 302 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->addr_idx = val; val 313 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 325 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->addr_val[idx]; val 328 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 337 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 341 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 353 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->addr_val[idx] = val; val 434 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 446 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->addr_val[idx]; val 449 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 458 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 462 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 474 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->addr_val[idx] = val; val 488 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 500 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->addr_val[idx]; val 503 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 512 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 516 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 528 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->addr_val[idx] = val; val 541 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 546 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->addr_acctype[config->addr_idx]; val 549 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 557 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 561 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 566 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->addr_acctype[config->addr_idx] = val; val 576 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 580 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->cntr_idx; val 581 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 589 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 593 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 597 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c if (val >= drvdata->nr_cntr) val 604 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->cntr_idx = val; val 614 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 619 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->cntr_rld_val[config->cntr_idx]; val 622 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 630 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 634 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 639 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->cntr_rld_val[config->cntr_idx] = val; val 649 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 654 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->cntr_event[config->cntr_idx]; val 657 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 665 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 669 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 674 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->cntr_event[config->cntr_idx] = val & ETM_EVENT_MASK; val 684 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 689 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->cntr_rld_event[config->cntr_idx]; val 692 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 700 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 704 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 709 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->cntr_rld_event[config->cntr_idx] = val & ETM_EVENT_MASK; val 720 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c u32 val; val 734 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = etm_readl(drvdata, ETMCNTVRn(i)); val 735 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret += sprintf(buf, "counter %d: %x\n", i, val); val 746 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 750 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 755 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->cntr_val[config->cntr_idx] = val; val 765 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 769 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->seq_12_event; val 770 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 778 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 782 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 786 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->seq_12_event = val & ETM_EVENT_MASK; val 794 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 798 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->seq_21_event; val 799 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 807 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 811 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 815 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->seq_21_event = val & ETM_EVENT_MASK; val 823 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 827 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->seq_23_event; val 828 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 836 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 840 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 844 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->seq_23_event = val & ETM_EVENT_MASK; val 852 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 856 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->seq_31_event; val 857 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 865 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 869 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 873 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->seq_31_event = val & ETM_EVENT_MASK; val 881 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 885 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->seq_32_event; val 886 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 894 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 898 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 902 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->seq_32_event = val & ETM_EVENT_MASK; val 910 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 914 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->seq_13_event; val 915 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 923 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 927 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 931 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->seq_13_event = val & ETM_EVENT_MASK; val 939 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val, flags; val 944 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->seq_curr_state; val 952 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK); val 958 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 966 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 970 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 974 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c if (val > ETM_SEQ_STATE_MAX_VAL) val 977 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->seq_curr_state = val; val 986 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 990 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->ctxid_idx; val 991 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 999 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1003 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 1007 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c if (val >= drvdata->nr_ctxid_cmp) val 1015 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->ctxid_idx = val; val 1025 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1037 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->ctxid_pid[config->ctxid_idx]; val 1040 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 1079 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1090 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->ctxid_mask; val 1091 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 1099 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1110 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 1114 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->ctxid_mask = val; val 1122 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1126 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->sync_freq; val 1127 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 1135 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1139 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 1143 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->sync_freq = val & ETM_SYNC_MASK; val 1151 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1155 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = config->timestamp_event; val 1156 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 1164 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1168 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 1172 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->timestamp_event = val & ETM_EVENT_MASK; val 1180 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c int val; val 1183 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = drvdata->cpu; val 1184 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%d\n", val); val 1192 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1195 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c val = etm_get_trace_id(drvdata); val 1197 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c return sprintf(buf, "%#lx\n", val); val 1205 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c unsigned long val; val 1208 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c ret = kstrtoul(buf, 16, &val); val 1212 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c drvdata->traceid = val & ETM_TRACEID_MASK; val 128 drivers/hwtracing/coresight/coresight-etm3x.c u32 val; val 131 drivers/hwtracing/coresight/coresight-etm3x.c val = etm_readl(drvdata, offset); val 134 drivers/hwtracing/coresight/coresight-etm3x.c if (val & BIT(position)) val 138 drivers/hwtracing/coresight/coresight-etm3x.c if (!(val & BIT(position))) val 539 drivers/hwtracing/coresight/coresight-etm3x.c u32 val; val 542 drivers/hwtracing/coresight/coresight-etm3x.c val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); val 545 drivers/hwtracing/coresight/coresight-etm3x.c if (val) val 60 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 63 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->nr_pe_cmp; val 64 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 72 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 75 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->nr_addr_cmp; val 76 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 84 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 87 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->nr_cntr; val 88 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 96 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 99 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->nr_ext_inp; val 100 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 108 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 111 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->numcidc; val 112 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 120 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 123 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->numvmidc; val 124 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 132 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 135 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->nrseqstate; val 136 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 144 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 147 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->nr_resource; val 148 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 156 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 159 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->nr_ss_cmp; val 160 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 169 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 173 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 177 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val) val 278 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 282 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->mode; val 283 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 290 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val, mode; val 294 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 298 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->mode = val & ETMv4_MODE_ALL; val 442 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 446 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->pe_sel; val 447 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 454 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 458 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 462 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val > drvdata->nr_pe) { val 467 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->pe_sel = val; val 477 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 481 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->eventctrl0; val 482 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 489 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 493 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 500 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl0 = val & 0xFF; val 504 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl0 = val & 0xFFFF; val 508 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl0 = val & 0xFFFFFF; val 512 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl0 = val; val 526 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 530 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = BMVAL(config->eventctrl1, 0, 3); val 531 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 538 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 542 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 551 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= val & BIT(1); val 555 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= val & (BIT(0) | BIT(1)); val 559 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2)); val 563 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= val & 0xF; val 577 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 581 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->ts_ctrl; val 582 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 589 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 593 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 598 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->ts_ctrl = val & ETMv4_EVENT_MASK; val 607 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 611 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->syncfreq; val 612 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 619 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 623 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 628 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->syncfreq = val & ETMv4_SYNC_MASK; val 637 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 641 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->ccctlr; val 642 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 649 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 653 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 657 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val &= ETM_CYC_THRESHOLD_MASK; val 658 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val < drvdata->ccitmin) val 661 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->ccctlr = val; val 670 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 674 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->bb_ctrl; val 675 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 682 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 686 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 698 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0)) val 701 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->bb_ctrl = val & GENMASK(8, 0); val 710 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 714 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->vinst_ctrl & ETMv4_EVENT_MASK; val 715 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 722 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 726 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 730 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val &= ETMv4_EVENT_MASK; val 732 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= val; val 742 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 746 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = BMVAL(config->vinst_ctrl, 16, 19); val 747 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 754 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 758 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 765 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val &= drvdata->s_ex_level; val 766 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= (val << 16); val 776 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 781 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = BMVAL(config->vinst_ctrl, 20, 23); val 782 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 789 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 793 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 800 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val &= drvdata->ns_ex_level; val 801 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= (val << 20); val 811 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 815 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->addr_idx; val 816 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 823 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 827 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 829 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val >= drvdata->nr_addr_cmp * 2) val 837 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_idx = val; val 848 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c u8 val, idx; val 854 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = BMVAL(config->addr_acc[idx], 0, 1); val 856 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val == ETM_INSTR_ADDR ? "instr" : val 857 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c (val == ETM_DATA_LOAD_ADDR ? "data_load" : val 858 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c (val == ETM_DATA_STORE_ADDR ? "data_store" : val 894 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 905 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = (unsigned long)config->addr_val[idx]; val 907 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 915 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 919 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 930 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_val[idx] = (u64)val; val 1017 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1030 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = (unsigned long)config->addr_val[idx]; val 1032 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1040 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1044 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1059 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_val[idx] = (u64)val; val 1074 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1087 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = (unsigned long)config->addr_val[idx]; val 1089 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1097 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1101 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1116 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_val[idx] = (u64)val; val 1131 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c u8 idx, val; val 1138 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = BMVAL(config->addr_acc[idx], 2, 3); val 1139 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c len = scnprintf(buf, PAGE_SIZE, "%s\n", val == ETM_CTX_NONE ? "none" : val 1140 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c (val == ETM_CTX_CTXID ? "ctxid" : val 1141 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c (val == ETM_CTX_VMID ? "vmid" : "all"))); val 1197 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1204 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = BMVAL(config->addr_acc[idx], 4, 6); val 1206 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1214 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1218 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1222 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val >= (drvdata->numcidc >= drvdata->numvmidc ? val 1230 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] |= (val << 4); val 1240 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1244 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->seq_idx; val 1245 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1252 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1256 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1258 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val >= drvdata->nrseqstate - 1) val 1266 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->seq_idx = val; val 1276 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1280 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->seq_state; val 1281 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1288 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1292 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1294 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val >= drvdata->nrseqstate) val 1297 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->seq_state = val; val 1307 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1313 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->seq_ctrl[idx]; val 1315 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1323 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1327 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1333 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->seq_ctrl[idx] = val & 0xFFFF; val 1343 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1347 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->seq_rst; val 1348 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1355 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1359 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1364 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->seq_rst = val & ETMv4_EVENT_MASK; val 1373 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1377 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->cntr_idx; val 1378 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1385 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1389 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1391 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val >= drvdata->nr_cntr) val 1399 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cntr_idx = val; val 1410 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1416 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->cntrldvr[idx]; val 1418 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1426 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1430 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1432 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val > ETM_CNTR_MAX_VAL) val 1437 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cntrldvr[idx] = val; val 1448 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1454 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->cntr_val[idx]; val 1456 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1464 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1468 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1470 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val > ETM_CNTR_MAX_VAL) val 1475 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cntr_val[idx] = val; val 1486 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1492 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->cntr_ctrl[idx]; val 1494 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1502 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1506 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1511 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cntr_ctrl[idx] = val; val 1521 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1525 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->res_idx; val 1526 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1533 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1537 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1540 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if ((val == 0) || (val >= drvdata->nr_resource)) val 1548 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->res_idx = val; val 1559 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1565 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->res_ctrl[idx]; val 1567 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1575 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1579 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1587 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val &= ~BIT(21); val 1588 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->res_ctrl[idx] = val & GENMASK(21, 0); val 1598 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1602 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->ctxid_idx; val 1603 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1610 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1614 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1616 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val >= drvdata->numcidc) val 1624 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->ctxid_idx = val; val 1635 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1648 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = (unsigned long)config->ctxid_pid[idx]; val 1650 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1821 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1825 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = config->vmid_idx; val 1826 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1833 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1837 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1839 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (val >= drvdata->numvmidc) val 1847 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vmid_idx = val; val 1857 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1861 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = (unsigned long)config->vmid_val[config->vmid_idx]; val 1862 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 1869 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val; val 1879 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if (kstrtoul(buf, 16, &val)) val 1883 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vmid_val[config->vmid_idx] = (u64)val; val 2002 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c int val; val 2005 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val = drvdata->cpu; val 2006 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return scnprintf(buf, PAGE_SIZE, "%d\n", val); val 233 drivers/hwtracing/coresight/coresight-etm4x.c u32 val = 0; val 280 drivers/hwtracing/coresight/coresight-etm4x.c val = 0x1 << 16 | /* Bit 16, reload counter automatically */ val 284 drivers/hwtracing/coresight/coresight-etm4x.c config->cntr_ctrl[ctridx] = val; val 286 drivers/hwtracing/coresight/coresight-etm4x.c val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */ val 289 drivers/hwtracing/coresight/coresight-etm4x.c config->res_ctrl[rselector] = val; val 291 drivers/hwtracing/coresight/coresight-etm4x.c val = 0x0 << 7 | /* Select single resource selector */ val 294 drivers/hwtracing/coresight/coresight-etm4x.c config->ts_ctrl = val; val 420 drivers/hwtracing/coresight/coresight-etm4x.c u32 val; val 423 drivers/hwtracing/coresight/coresight-etm4x.c val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); val 426 drivers/hwtracing/coresight/coresight-etm4x.c if (val) val 156 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_COND(val) BMVAL(val, 8, 10) val 159 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) val 150 drivers/hwtracing/coresight/coresight-funnel.c unsigned long val = drvdata->priority; val 152 drivers/hwtracing/coresight/coresight-funnel.c return sprintf(buf, "%#lx\n", val); val 160 drivers/hwtracing/coresight/coresight-funnel.c unsigned long val; val 163 drivers/hwtracing/coresight/coresight-funnel.c ret = kstrtoul(buf, 16, &val); val 167 drivers/hwtracing/coresight/coresight-funnel.c drvdata->priority = val; val 186 drivers/hwtracing/coresight/coresight-funnel.c u32 val; val 191 drivers/hwtracing/coresight/coresight-funnel.c val = get_funnel_ctrl_hw(drvdata); val 195 drivers/hwtracing/coresight/coresight-funnel.c return sprintf(buf, "%#x\n", val); val 37 drivers/hwtracing/coresight/coresight-priv.h #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) val 49 drivers/hwtracing/coresight/coresight-priv.h u64 val; \ val 52 drivers/hwtracing/coresight/coresight-priv.h val = (u64)fn(_dev->parent, lo_off); \ val 54 drivers/hwtracing/coresight/coresight-priv.h val = coresight_read_reg_pair(drvdata->base, \ val 57 drivers/hwtracing/coresight/coresight-priv.h return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val); \ val 131 drivers/hwtracing/coresight/coresight-priv.h u64 val; val 133 drivers/hwtracing/coresight/coresight-priv.h val = readl_relaxed(addr + lo_offset); val 134 drivers/hwtracing/coresight/coresight-priv.h val |= (hi_offset < 0) ? 0 : val 136 drivers/hwtracing/coresight/coresight-priv.h return val; val 139 drivers/hwtracing/coresight/coresight-priv.h static inline void coresight_write_reg_pair(void __iomem *addr, u64 val, val 142 drivers/hwtracing/coresight/coresight-priv.h writel_relaxed((u32)val, addr + lo_offset); val 144 drivers/hwtracing/coresight/coresight-priv.h writel_relaxed((u32)(val >> 32), addr + hi_offset); val 157 drivers/hwtracing/coresight/coresight-priv.h extern int etm_readl_cp14(u32 off, unsigned int *val); val 158 drivers/hwtracing/coresight/coresight-priv.h extern int etm_writel_cp14(u32 off, u32 val); val 160 drivers/hwtracing/coresight/coresight-priv.h static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } val 161 drivers/hwtracing/coresight/coresight-priv.h static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } val 197 drivers/hwtracing/coresight/coresight-stm.c u32 val; val 203 drivers/hwtracing/coresight/coresight-stm.c val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); val 206 drivers/hwtracing/coresight/coresight-stm.c if (val) val 242 drivers/hwtracing/coresight/coresight-stm.c u32 val; val 246 drivers/hwtracing/coresight/coresight-stm.c val = readl_relaxed(drvdata->base + STMTCSR); val 247 drivers/hwtracing/coresight/coresight-stm.c val &= ~0x1; /* clear global STM enable [0] */ val 248 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(val, drvdata->base + STMTCSR); val 463 drivers/hwtracing/coresight/coresight-stm.c unsigned long val = drvdata->stmheer; val 465 drivers/hwtracing/coresight/coresight-stm.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 473 drivers/hwtracing/coresight/coresight-stm.c unsigned long val; val 476 drivers/hwtracing/coresight/coresight-stm.c ret = kstrtoul(buf, 16, &val); val 480 drivers/hwtracing/coresight/coresight-stm.c drvdata->stmheer = val; val 482 drivers/hwtracing/coresight/coresight-stm.c drvdata->stmheter = val; val 492 drivers/hwtracing/coresight/coresight-stm.c unsigned long val = drvdata->stmhebsr; val 494 drivers/hwtracing/coresight/coresight-stm.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 502 drivers/hwtracing/coresight/coresight-stm.c unsigned long val; val 505 drivers/hwtracing/coresight/coresight-stm.c ret = kstrtoul(buf, 16, &val); val 509 drivers/hwtracing/coresight/coresight-stm.c drvdata->stmhebsr = val; val 519 drivers/hwtracing/coresight/coresight-stm.c unsigned long val; val 522 drivers/hwtracing/coresight/coresight-stm.c val = drvdata->stmspscr; val 525 drivers/hwtracing/coresight/coresight-stm.c val = readl_relaxed(drvdata->base + STMSPSCR); val 529 drivers/hwtracing/coresight/coresight-stm.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 537 drivers/hwtracing/coresight/coresight-stm.c unsigned long val, stmsper; val 540 drivers/hwtracing/coresight/coresight-stm.c ret = kstrtoul(buf, 16, &val); val 545 drivers/hwtracing/coresight/coresight-stm.c drvdata->stmspscr = val; val 566 drivers/hwtracing/coresight/coresight-stm.c unsigned long val; val 569 drivers/hwtracing/coresight/coresight-stm.c val = drvdata->stmsper; val 572 drivers/hwtracing/coresight/coresight-stm.c val = readl_relaxed(drvdata->base + STMSPER); val 576 drivers/hwtracing/coresight/coresight-stm.c return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); val 584 drivers/hwtracing/coresight/coresight-stm.c unsigned long val; val 587 drivers/hwtracing/coresight/coresight-stm.c ret = kstrtoul(buf, 16, &val); val 592 drivers/hwtracing/coresight/coresight-stm.c drvdata->stmsper = val; val 608 drivers/hwtracing/coresight/coresight-stm.c unsigned long val; val 611 drivers/hwtracing/coresight/coresight-stm.c val = drvdata->traceid; val 612 drivers/hwtracing/coresight/coresight-stm.c return sprintf(buf, "%#lx\n", val); val 620 drivers/hwtracing/coresight/coresight-stm.c unsigned long val; val 623 drivers/hwtracing/coresight/coresight-stm.c ret = kstrtoul(buf, 16, &val); val 628 drivers/hwtracing/coresight/coresight-stm.c drvdata->traceid = val & 0x7f; val 295 drivers/hwtracing/coresight/coresight-tmc.c unsigned long val = drvdata->trigger_cntr; val 297 drivers/hwtracing/coresight/coresight-tmc.c return sprintf(buf, "%#lx\n", val); val 305 drivers/hwtracing/coresight/coresight-tmc.c unsigned long val; val 308 drivers/hwtracing/coresight/coresight-tmc.c ret = kstrtoul(buf, 16, &val); val 312 drivers/hwtracing/coresight/coresight-tmc.c drvdata->trigger_cntr = val; val 330 drivers/hwtracing/coresight/coresight-tmc.c unsigned long val; val 337 drivers/hwtracing/coresight/coresight-tmc.c ret = kstrtoul(buf, 0, &val); val 341 drivers/hwtracing/coresight/coresight-tmc.c if (val & (PAGE_SIZE - 1)) val 343 drivers/hwtracing/coresight/coresight-tmc.c drvdata->size = val; val 283 drivers/hwtracing/coresight/coresight-tmc.h tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ val 285 drivers/hwtracing/coresight/coresight-tmc.h coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ val 875 drivers/hwtracing/coresight/coresight.c unsigned long val; val 878 drivers/hwtracing/coresight/coresight.c ret = kstrtoul(buf, 10, &val); val 882 drivers/hwtracing/coresight/coresight.c if (val) val 905 drivers/hwtracing/coresight/coresight.c unsigned long val; val 908 drivers/hwtracing/coresight/coresight.c ret = kstrtoul(buf, 10, &val); val 912 drivers/hwtracing/coresight/coresight.c if (val) { val 1119 drivers/hwtracing/coresight/coresight.c u32 val; val 1122 drivers/hwtracing/coresight/coresight.c val = __raw_readl(addr + offset); val 1125 drivers/hwtracing/coresight/coresight.c if (val & BIT(position)) val 1129 drivers/hwtracing/coresight/coresight.c if (!(val & BIT(position))) val 292 drivers/hwtracing/intel_th/core.c unsigned long val; val 295 drivers/hwtracing/intel_th/core.c ret = kstrtoul(buf, 10, &val); val 299 drivers/hwtracing/intel_th/core.c if (!!val != thdev->output.active) { val 300 drivers/hwtracing/intel_th/core.c if (val) val 65 drivers/hwtracing/intel_th/gth.c u32 val; val 68 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); val 69 drivers/hwtracing/intel_th/gth.c val &= ~(0xff << shift); val 70 drivers/hwtracing/intel_th/gth.c val |= config << shift; val 71 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); val 77 drivers/hwtracing/intel_th/gth.c u32 val; val 80 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); val 81 drivers/hwtracing/intel_th/gth.c val &= 0xff << shift; val 82 drivers/hwtracing/intel_th/gth.c val >>= shift; val 84 drivers/hwtracing/intel_th/gth.c return val; val 92 drivers/hwtracing/intel_th/gth.c u32 val; val 94 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); val 95 drivers/hwtracing/intel_th/gth.c val &= ~(0xffff << shift); val 96 drivers/hwtracing/intel_th/gth.c val |= freq << shift; val 97 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); val 104 drivers/hwtracing/intel_th/gth.c u32 val; val 106 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); val 107 drivers/hwtracing/intel_th/gth.c val &= 0xffff << shift; val 108 drivers/hwtracing/intel_th/gth.c val >>= shift; val 110 drivers/hwtracing/intel_th/gth.c return val; val 128 drivers/hwtracing/intel_th/gth.c u32 val; val 135 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); val 136 drivers/hwtracing/intel_th/gth.c val &= ~(0xf << shift); val 138 drivers/hwtracing/intel_th/gth.c val |= (0x8 | port) << shift; val 139 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); val 237 drivers/hwtracing/intel_th/gth.c unsigned int val); val 252 drivers/hwtracing/intel_th/gth.c unsigned int val) val 259 drivers/hwtracing/intel_th/gth.c config |= (val << shift) & mask; val 1796 drivers/hwtracing/intel_th/msu.c unsigned long val; val 1799 drivers/hwtracing/intel_th/msu.c ret = kstrtoul(buf, 10, &val); val 1803 drivers/hwtracing/intel_th/msu.c msc->wrap = !!val; val 1952 drivers/hwtracing/intel_th/msu.c unsigned long val, *win = NULL, *rewin; val 1978 drivers/hwtracing/intel_th/msu.c ret = kstrtoul(s, 10, &val); val 1981 drivers/hwtracing/intel_th/msu.c if (ret || !val) val 1997 drivers/hwtracing/intel_th/msu.c win[nr_wins - 1] = val; val 2024 drivers/hwtracing/intel_th/msu.c unsigned long val; val 2027 drivers/hwtracing/intel_th/msu.c ret = kstrtoul(buf, 10, &val); val 2031 drivers/hwtracing/intel_th/msu.c if (val != 1) val 61 drivers/hwtracing/intel_th/pti.c unsigned long val; val 64 drivers/hwtracing/intel_th/pti.c ret = kstrtoul(buf, 10, &val); val 68 drivers/hwtracing/intel_th/pti.c ret = pti_width_mode(val); val 93 drivers/hwtracing/intel_th/pti.c unsigned long val; val 96 drivers/hwtracing/intel_th/pti.c ret = kstrtoul(buf, 10, &val); val 100 drivers/hwtracing/intel_th/pti.c pti->freeclk = !!val; val 121 drivers/hwtracing/intel_th/pti.c unsigned long val; val 124 drivers/hwtracing/intel_th/pti.c ret = kstrtoul(buf, 10, &val); val 128 drivers/hwtracing/intel_th/pti.c if (!is_power_of_2(val) || val > 8 || !val) val 131 drivers/hwtracing/intel_th/pti.c pti->clkdiv = val; val 48 drivers/i2c/algos/i2c-algo-bit.c #define setsda(adap, val) adap->setsda(adap->data, val) val 49 drivers/i2c/algos/i2c-algo-bit.c #define setscl(adap, val) adap->setscl(adap->data, val) val 26 drivers/i2c/algos/i2c-algo-pca.c #define pca_outw(adap, reg, val) adap->write_byte(adap->data, reg, val) val 31 drivers/i2c/algos/i2c-algo-pca.c #define pca_set_con(adap, val) pca_outw(adap, I2C_PCA_CON, val) val 38 drivers/i2c/algos/i2c-algo-pcf.c #define set_pcf(adap, ctl, val) adap->setpcf(adap->data, ctl, val) val 42 drivers/i2c/algos/i2c-algo-pcf.c #define i2c_outb(adap, val) adap->setpcf(adap->data, 0, val) val 212 drivers/i2c/busses/i2c-amd-mp2-pci.c u32 val; val 224 drivers/i2c/busses/i2c-amd-mp2-pci.c val = readl(reg); val 225 drivers/i2c/busses/i2c-amd-mp2-pci.c if (val != 0) { val 228 drivers/i2c/busses/i2c-amd-mp2-pci.c i2c_common->eventval.ul = val; val 236 drivers/i2c/busses/i2c-amd-mp2-pci.c val = readl(privdata->mmio + AMD_P2C_MSG_INTEN); val 237 drivers/i2c/busses/i2c-amd-mp2-pci.c if (val != 0) { val 34 drivers/i2c/busses/i2c-at91-core.c void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val) val 36 drivers/i2c/busses/i2c-at91-core.c writel_relaxed(val, dev->base + reg); val 151 drivers/i2c/busses/i2c-at91.h void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val); val 318 drivers/i2c/busses/i2c-axxia.c u8 val; val 325 drivers/i2c/busses/i2c-axxia.c I2C_SLAVE_WRITE_REQUESTED, &val); val 327 drivers/i2c/busses/i2c-axxia.c val = readl(idev->base + SLV_DATA); val 328 drivers/i2c/busses/i2c-axxia.c i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val); val 332 drivers/i2c/busses/i2c-axxia.c i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val); val 341 drivers/i2c/busses/i2c-axxia.c u8 val; val 348 drivers/i2c/busses/i2c-axxia.c i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val); val 349 drivers/i2c/busses/i2c-axxia.c writel(val, idev->base + SLV_DATA); val 352 drivers/i2c/busses/i2c-axxia.c i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val); val 353 drivers/i2c/busses/i2c-axxia.c writel(val, idev->base + SLV_DATA); val 356 drivers/i2c/busses/i2c-axxia.c i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val); val 641 drivers/i2c/busses/i2c-axxia.c static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val) val 648 drivers/i2c/busses/i2c-axxia.c if (!val) val 226 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 232 drivers/i2c/busses/i2c-bcm-iproc.c val = readl(iproc_i2c->base + offset); val 235 drivers/i2c/busses/i2c-bcm-iproc.c val = readl(iproc_i2c->base + offset); val 238 drivers/i2c/busses/i2c-bcm-iproc.c return val; val 242 drivers/i2c/busses/i2c-bcm-iproc.c u32 offset, u32 val) val 248 drivers/i2c/busses/i2c-bcm-iproc.c writel(val, iproc_i2c->base + offset); val 251 drivers/i2c/busses/i2c-bcm-iproc.c writel(val, iproc_i2c->base + offset); val 258 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 262 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); val 263 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(CFG_RESET_SHIFT); val 264 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); val 270 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(BIT(CFG_RESET_SHIFT)); val 271 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); val 275 drivers/i2c/busses/i2c-bcm-iproc.c val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); val 276 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); val 279 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); val 280 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT); val 281 drivers/i2c/busses/i2c-bcm-iproc.c val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT); val 282 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); val 285 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); val 286 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); val 287 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT); val 288 drivers/i2c/busses/i2c-bcm-iproc.c val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT); val 289 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val); val 295 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(IE_S_RX_EVENT_SHIFT); val 297 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(IE_S_START_BUSY_SHIFT); val 298 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); val 304 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 306 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET); val 308 drivers/i2c/busses/i2c-bcm-iproc.c if (val & BIT(S_CMD_START_BUSY_SHIFT)) val 311 drivers/i2c/busses/i2c-bcm-iproc.c val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK; val 312 drivers/i2c/busses/i2c-bcm-iproc.c if (val == S_CMD_STATUS_TIMEOUT) { val 325 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 330 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); val 331 drivers/i2c/busses/i2c-bcm-iproc.c rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; val 337 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); val 338 drivers/i2c/busses/i2c-bcm-iproc.c value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); val 347 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(S_CMD_START_BUSY_SHIFT); val 348 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); val 354 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); val 355 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(IE_S_TX_UNDERRUN_SHIFT); val 356 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); val 359 drivers/i2c/busses/i2c-bcm-iproc.c value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); val 372 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(S_CMD_START_BUSY_SHIFT); val 373 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); val 383 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); val 384 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT); val 385 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); val 398 drivers/i2c/busses/i2c-bcm-iproc.c uint32_t val; val 402 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET); val 405 drivers/i2c/busses/i2c-bcm-iproc.c if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK)) val 409 drivers/i2c/busses/i2c-bcm-iproc.c (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK; val 419 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 427 drivers/i2c/busses/i2c-bcm-iproc.c val = msg->buf[idx]; val 431 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(M_TX_WR_STATUS_SHIFT); val 448 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); val 458 drivers/i2c/busses/i2c-bcm-iproc.c u32 bytes_left, val; val 465 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); val 466 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(IS_M_RX_THLD_SHIFT); val 467 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); val 471 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); val 472 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); val 473 drivers/i2c/busses/i2c-bcm-iproc.c val |= (bytes_left << M_FIFO_RX_THLD_SHIFT); val 474 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); val 531 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 534 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); val 535 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(CFG_RESET_SHIFT); val 536 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(BIT(CFG_EN_SHIFT)); val 537 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); val 543 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(BIT(CFG_RESET_SHIFT)); val 544 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); val 547 drivers/i2c/busses/i2c-bcm-iproc.c val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); val 548 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); val 550 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); val 551 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(IE_M_ALL_INTERRUPT_MASK << val 553 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); val 564 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 566 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); val 568 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(CFG_EN_SHIFT); val 570 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(CFG_EN_SHIFT); val 571 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); val 577 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 579 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET); val 580 drivers/i2c/busses/i2c-bcm-iproc.c val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; val 582 drivers/i2c/busses/i2c-bcm-iproc.c switch (val) { val 611 drivers/i2c/busses/i2c-bcm-iproc.c dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val); val 627 drivers/i2c/busses/i2c-bcm-iproc.c u32 val, status; val 665 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); val 666 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); val 673 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); val 674 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); val 686 drivers/i2c/busses/i2c-bcm-iproc.c u32 val, tmp, val_intr_en; val 710 drivers/i2c/busses/i2c-bcm-iproc.c val = msg->buf[i]; val 714 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(M_TX_WR_STATUS_SHIFT); val 716 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); val 747 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(M_CMD_START_BUSY_SHIFT); val 764 drivers/i2c/busses/i2c-bcm-iproc.c val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) | val 767 drivers/i2c/busses/i2c-bcm-iproc.c val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); val 773 drivers/i2c/busses/i2c-bcm-iproc.c return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val); val 796 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 799 drivers/i2c/busses/i2c-bcm-iproc.c val = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); val 802 drivers/i2c/busses/i2c-bcm-iproc.c val |= I2C_FUNC_SLAVE; val 804 drivers/i2c/busses/i2c-bcm-iproc.c return val; val 821 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 843 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); val 844 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(TIM_CFG_MODE_400_SHIFT); val 845 drivers/i2c/busses/i2c-bcm-iproc.c val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; val 846 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); val 985 drivers/i2c/busses/i2c-bcm-iproc.c u32 val; val 996 drivers/i2c/busses/i2c-bcm-iproc.c val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); val 997 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(TIM_CFG_MODE_400_SHIFT); val 998 drivers/i2c/busses/i2c-bcm-iproc.c val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; val 999 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); val 69 drivers/i2c/busses/i2c-bcm2835.c u32 reg, u32 val) val 71 drivers/i2c/busses/i2c-bcm2835.c writel(val, i2c_dev->regs + reg); val 190 drivers/i2c/busses/i2c-bcm2835.c u32 val; val 193 drivers/i2c/busses/i2c-bcm2835.c val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); val 194 drivers/i2c/busses/i2c-bcm2835.c if (!(val & BCM2835_I2C_S_TXD)) val 205 drivers/i2c/busses/i2c-bcm2835.c u32 val; val 208 drivers/i2c/busses/i2c-bcm2835.c val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); val 209 drivers/i2c/busses/i2c-bcm2835.c if (!(val & BCM2835_I2C_S_RXD)) val 278 drivers/i2c/busses/i2c-bcm2835.c u32 val, err; val 280 drivers/i2c/busses/i2c-bcm2835.c val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); val 282 drivers/i2c/busses/i2c-bcm2835.c err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR); val 288 drivers/i2c/busses/i2c-bcm2835.c if (val & BCM2835_I2C_S_DONE) { val 293 drivers/i2c/busses/i2c-bcm2835.c val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); val 296 drivers/i2c/busses/i2c-bcm2835.c if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining) val 303 drivers/i2c/busses/i2c-bcm2835.c if (val & BCM2835_I2C_S_TXW) { val 305 drivers/i2c/busses/i2c-bcm2835.c i2c_dev->msg_err = val | BCM2835_I2C_S_LEN; val 319 drivers/i2c/busses/i2c-bcm2835.c if (val & BCM2835_I2C_S_RXR) { val 321 drivers/i2c/busses/i2c-bcm2835.c i2c_dev->msg_err = val | BCM2835_I2C_S_LEN; val 118 drivers/i2c/busses/i2c-cadence.c #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) val 145 drivers/i2c/busses/i2c-davinci.c int reg, u16 val) val 147 drivers/i2c/busses/i2c-davinci.c writew_relaxed(val, i2c_dev->base + reg); val 156 drivers/i2c/busses/i2c-davinci.c int val) val 161 drivers/i2c/busses/i2c-davinci.c if (!val) /* put I2C into reset */ val 318 drivers/i2c/busses/i2c-davinci.c static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val) val 322 drivers/i2c/busses/i2c-davinci.c if (val) val 333 drivers/i2c/busses/i2c-davinci.c int val; val 336 drivers/i2c/busses/i2c-davinci.c val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG); val 337 drivers/i2c/busses/i2c-davinci.c return val & DAVINCI_I2C_DIN_PDIN0; val 343 drivers/i2c/busses/i2c-davinci.c int val; val 346 drivers/i2c/busses/i2c-davinci.c val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG); val 347 drivers/i2c/busses/i2c-davinci.c return val & DAVINCI_I2C_DIN_PDIN1; val 706 drivers/i2c/busses/i2c-davinci.c unsigned long val, void *data) val 713 drivers/i2c/busses/i2c-davinci.c if (val == CPUFREQ_PRECHANGE) { val 715 drivers/i2c/busses/i2c-davinci.c } else if (val == CPUFREQ_POSTCHANGE) { val 159 drivers/i2c/busses/i2c-designware-slave.c u8 val, slave_activity; val 175 drivers/i2c/busses/i2c-designware-slave.c i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, &val); val 180 drivers/i2c/busses/i2c-designware-slave.c val = dw_readl(dev, DW_IC_DATA_CMD); val 184 drivers/i2c/busses/i2c-designware-slave.c &val)) { val 186 drivers/i2c/busses/i2c-designware-slave.c val); val 197 drivers/i2c/busses/i2c-designware-slave.c &val)) val 198 drivers/i2c/busses/i2c-designware-slave.c dw_writel(dev, val, DW_IC_DATA_CMD); val 204 drivers/i2c/busses/i2c-designware-slave.c &val)) val 207 drivers/i2c/busses/i2c-designware-slave.c i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val); val 213 drivers/i2c/busses/i2c-designware-slave.c val = dw_readl(dev, DW_IC_DATA_CMD); val 215 drivers/i2c/busses/i2c-designware-slave.c &val)) val 216 drivers/i2c/busses/i2c-designware-slave.c dev_vdbg(dev->dev, "Byte %X acked!", val); val 218 drivers/i2c/busses/i2c-designware-slave.c i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val); val 15 drivers/i2c/busses/i2c-efm32.c #define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask) val 188 drivers/i2c/busses/i2c-eg20t.c u32 val; val 189 drivers/i2c/busses/i2c-eg20t.c val = ioread32(addr + offset); val 190 drivers/i2c/busses/i2c-eg20t.c val |= bitmask; val 191 drivers/i2c/busses/i2c-eg20t.c iowrite32(val, addr + offset); val 196 drivers/i2c/busses/i2c-eg20t.c u32 val; val 197 drivers/i2c/busses/i2c-eg20t.c val = ioread32(addr + offset); val 198 drivers/i2c/busses/i2c-eg20t.c val &= (~bitmask); val 199 drivers/i2c/busses/i2c-eg20t.c iowrite32(val, addr + offset); val 58 drivers/i2c/busses/i2c-elektor.c static void pcf_isa_setbyte(void *data, int ctl, int val) val 63 drivers/i2c/busses/i2c-elektor.c if (ctl && irq && (val & I2C_PCF_ESO)) { val 64 drivers/i2c/busses/i2c-elektor.c val |= I2C_PCF_ENI; val 67 drivers/i2c/busses/i2c-elektor.c pr_debug("%s: Write %p 0x%02X\n", pcf_isa_ops.name, address, val); val 68 drivers/i2c/busses/i2c-elektor.c iowrite8(val, address); val 71 drivers/i2c/busses/i2c-elektor.c iowrite8(val, address); val 78 drivers/i2c/busses/i2c-elektor.c int val = ioread8(address); val 80 drivers/i2c/busses/i2c-elektor.c pr_debug("%s: Read %p 0x%02X\n", pcf_isa_ops.name, address, val); val 81 drivers/i2c/busses/i2c-elektor.c return (val); val 549 drivers/i2c/busses/i2c-exynos5.c u32 val; val 551 drivers/i2c/busses/i2c-exynos5.c val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON; val 552 drivers/i2c/busses/i2c-exynos5.c writel(val, i2c->regs + HSI2C_CTL); val 553 drivers/i2c/busses/i2c-exynos5.c val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE; val 554 drivers/i2c/busses/i2c-exynos5.c writel(val, i2c->regs + HSI2C_CONF); val 566 drivers/i2c/busses/i2c-exynos5.c val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON; val 567 drivers/i2c/busses/i2c-exynos5.c writel(val, i2c->regs + HSI2C_CTL); val 568 drivers/i2c/busses/i2c-exynos5.c val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE; val 569 drivers/i2c/busses/i2c-exynos5.c writel(val, i2c->regs + HSI2C_CONF); val 340 drivers/i2c/busses/i2c-fsi.c static void fsi_i2c_set_scl(struct i2c_adapter *adap, int val) val 346 drivers/i2c/busses/i2c-fsi.c if (val) val 363 drivers/i2c/busses/i2c-fsi.c static void fsi_i2c_set_sda(struct i2c_adapter *adap, int val) val 369 drivers/i2c/busses/i2c-fsi.c if (val) val 77 drivers/i2c/busses/i2c-gpio.c #define setsda(bd, val) ((bd)->setsda((bd)->data, val)) val 78 drivers/i2c/busses/i2c-gpio.c #define setscl(bd, val) ((bd)->setscl((bd)->data, val)) val 83 drivers/i2c/busses/i2c-gpio.c static int fops_##wire##_get(void *data, u64 *val) \ val 88 drivers/i2c/busses/i2c-gpio.c *val = get##wire(&priv->bit_data); \ val 92 drivers/i2c/busses/i2c-gpio.c static int fops_##wire##_set(void *data, u64 val) \ val 97 drivers/i2c/busses/i2c-gpio.c set##wire(&priv->bit_data, val); \ val 99 drivers/i2c/busses/i2c-hix5hd2.c u32 val = readl_relaxed(priv->regs + HIX5I2C_SR); val 101 drivers/i2c/busses/i2c-hix5hd2.c writel_relaxed(val, priv->regs + HIX5I2C_ICR); val 103 drivers/i2c/busses/i2c-hix5hd2.c return val; val 124 drivers/i2c/busses/i2c-hix5hd2.c u32 rate, val; val 128 drivers/i2c/busses/i2c-hix5hd2.c val = readl_relaxed(priv->regs + HIX5I2C_CTRL); val 129 drivers/i2c/busses/i2c-hix5hd2.c writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); val 138 drivers/i2c/busses/i2c-hix5hd2.c writel_relaxed(val, priv->regs + HIX5I2C_CTRL); val 32 drivers/i2c/busses/i2c-hydra.c static inline void pdregw(void *data, u32 val) val 35 drivers/i2c/busses/i2c-hydra.c writel(val, &hydra->CachePD); val 46 drivers/i2c/busses/i2c-hydra.c u32 val = pdregr(data); val 48 drivers/i2c/busses/i2c-hydra.c val &= ~HYDRA_SCLK_OE; val 50 drivers/i2c/busses/i2c-hydra.c val &= ~HYDRA_SCLK; val 51 drivers/i2c/busses/i2c-hydra.c val |= HYDRA_SCLK_OE; val 53 drivers/i2c/busses/i2c-hydra.c pdregw(data, val); val 58 drivers/i2c/busses/i2c-hydra.c u32 val = pdregr(data); val 60 drivers/i2c/busses/i2c-hydra.c val &= ~HYDRA_SDAT_OE; val 62 drivers/i2c/busses/i2c-hydra.c val &= ~HYDRA_SDAT; val 63 drivers/i2c/busses/i2c-hydra.c val |= HYDRA_SDAT_OE; val 65 drivers/i2c/busses/i2c-hydra.c pdregw(data, val); val 63 drivers/i2c/busses/i2c-icy.c static void icy_pcf_setpcf(void *data, int ctl, int val) val 69 drivers/i2c/busses/i2c-icy.c z_writeb(val, address); val 532 drivers/i2c/busses/i2c-img-scb.c u32 val; val 537 drivers/i2c/busses/i2c-img-scb.c val = img_i2c_readl(i2c, SCB_CONTROL_REG); val 539 drivers/i2c/busses/i2c-img-scb.c val |= SCB_CONTROL_TRANSACTION_HALT; val 541 drivers/i2c/busses/i2c-img-scb.c val &= ~SCB_CONTROL_TRANSACTION_HALT; val 542 drivers/i2c/busses/i2c-img-scb.c img_i2c_writel(i2c, SCB_CONTROL_REG, val); val 1335 drivers/i2c/busses/i2c-img-scb.c u32 val; val 1375 drivers/i2c/busses/i2c-img-scb.c if (!of_property_read_u32(node, "clock-frequency", &val)) val 1376 drivers/i2c/busses/i2c-img-scb.c i2c->bitrate = val; val 122 drivers/i2c/busses/i2c-imx.c u16 val; val 270 drivers/i2c/busses/i2c-imx.c static inline void imx_i2c_write_reg(unsigned int val, val 273 drivers/i2c/busses/i2c-imx.c writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); val 500 drivers/i2c/busses/i2c-imx.c i2c_imx->ifdr = i2c_clk_div[i].val; val 515 drivers/i2c/busses/i2c-imx.c i2c_clk_div[i].val, i2c_clk_div[i].div); val 294 drivers/i2c/busses/i2c-ismt.c uint val; val 302 drivers/i2c/busses/i2c-ismt.c val = readl(priv->smba + ISMT_MSTR_MCTRL); val 303 drivers/i2c/busses/i2c-ismt.c writel((val & ~ISMT_MCTRL_FMHP) | fmhp, val 307 drivers/i2c/busses/i2c-ismt.c val = readl(priv->smba + ISMT_MSTR_MCTRL); val 308 drivers/i2c/busses/i2c-ismt.c writel(val | ISMT_MCTRL_SS, val 660 drivers/i2c/busses/i2c-ismt.c u32 val; val 667 drivers/i2c/busses/i2c-ismt.c val = readl(priv->smba + ISMT_MSTR_MSTS); val 669 drivers/i2c/busses/i2c-ismt.c if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) val 672 drivers/i2c/busses/i2c-ismt.c writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, val 694 drivers/i2c/busses/i2c-ismt.c u32 val; val 707 drivers/i2c/busses/i2c-ismt.c val = readl(priv->smba + ISMT_MSTR_MDS); val 708 drivers/i2c/busses/i2c-ismt.c writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), val 715 drivers/i2c/busses/i2c-ismt.c val = readl(priv->smba + ISMT_SPGT); val 723 drivers/i2c/busses/i2c-ismt.c writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), val 729 drivers/i2c/busses/i2c-ismt.c writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), val 735 drivers/i2c/busses/i2c-ismt.c writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), val 741 drivers/i2c/busses/i2c-ismt.c writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), val 750 drivers/i2c/busses/i2c-ismt.c val = readl(priv->smba + ISMT_SPGT); val 752 drivers/i2c/busses/i2c-ismt.c switch (val & ISMT_SPGT_SPD_MASK) { val 158 drivers/i2c/busses/i2c-jz4780.c unsigned long offset, unsigned short val) val 160 drivers/i2c/busses/i2c-jz4780.c writew(val, i2c->iomem + offset); val 103 drivers/i2c/busses/i2c-meson.c u32 val) val 109 drivers/i2c/busses/i2c-meson.c data |= val & mask; val 205 drivers/i2c/busses/i2c-mlxcpld.c u8 val; val 207 drivers/i2c/busses/i2c-mlxcpld.c mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1); val 209 drivers/i2c/busses/i2c-mlxcpld.c if (val & MLXCPLD_LPCI2C_TRANS_END) { val 210 drivers/i2c/busses/i2c-mlxcpld.c if (val & MLXCPLD_LPCI2C_STATUS_NACK) val 253 drivers/i2c/busses/i2c-mlxcpld.c u8 val; val 257 drivers/i2c/busses/i2c-mlxcpld.c mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1); val 258 drivers/i2c/busses/i2c-mlxcpld.c val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK; val 259 drivers/i2c/busses/i2c-mlxcpld.c mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1); val 267 drivers/i2c/busses/i2c-mlxcpld.c u8 val; val 269 drivers/i2c/busses/i2c-mlxcpld.c mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1); val 271 drivers/i2c/busses/i2c-mlxcpld.c if (val & MLXCPLD_LPCI2C_TRANS_END) val 302 drivers/i2c/busses/i2c-mlxcpld.c u8 datalen, val; val 335 drivers/i2c/busses/i2c-mlxcpld.c mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, val 337 drivers/i2c/busses/i2c-mlxcpld.c if (priv->smbus_block && (val & MLXCPLD_I2C_SMBUS_BLK_BIT)) { val 364 drivers/i2c/busses/i2c-mlxcpld.c u8 cmd, val; val 369 drivers/i2c/busses/i2c-mlxcpld.c val = priv->xfer.addr_width; val 375 drivers/i2c/busses/i2c-mlxcpld.c val |= MLXCPLD_I2C_SMBUS_BLK_BIT; val 377 drivers/i2c/busses/i2c-mlxcpld.c mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, 1); val 496 drivers/i2c/busses/i2c-mlxcpld.c u8 val; val 511 drivers/i2c/busses/i2c-mlxcpld.c mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CPBLTY_REG, &val, 1); val 513 drivers/i2c/busses/i2c-mlxcpld.c if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT) val 516 drivers/i2c/busses/i2c-mlxcpld.c if (val & MLXCPLD_I2C_SMBUS_BLK_BIT) val 325 drivers/i2c/busses/i2c-mpc.c u32 val = 0; val 344 drivers/i2c/busses/i2c-mpc.c val = in_be32(reg) & 0x00000020; /* sec-cfg */ val 350 drivers/i2c/busses/i2c-mpc.c return val; val 333 drivers/i2c/busses/i2c-mt65xx.c static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, val 336 drivers/i2c/busses/i2c-mt65xx.c writew(val, i2c->base + i2c->dev_comp->regs[reg]); val 72 drivers/i2c/busses/i2c-mt7621.c u32 val; val 75 drivers/i2c/busses/i2c-mt7621.c val, !(val & SM0CTL1_TRI), val 29 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1) val 30 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) val 31 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3) val 92 drivers/i2c/busses/i2c-nomadik.c #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) val 60 drivers/i2c/busses/i2c-nvidia-gpu.c u32 val; val 63 drivers/i2c/busses/i2c-nvidia-gpu.c val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL); val 64 drivers/i2c/busses/i2c-nvidia-gpu.c val |= I2C_MST_HYBRID_PADCTL_MODE_I2C | val 67 drivers/i2c/busses/i2c-nvidia-gpu.c writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL); val 70 drivers/i2c/busses/i2c-nvidia-gpu.c val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ; val 71 drivers/i2c/busses/i2c-nvidia-gpu.c val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX val 73 drivers/i2c/busses/i2c-nvidia-gpu.c val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK; val 74 drivers/i2c/busses/i2c-nvidia-gpu.c writel(val, i2cd->regs + I2C_MST_I2C0_TIMING); val 79 drivers/i2c/busses/i2c-nvidia-gpu.c u32 val; val 82 drivers/i2c/busses/i2c-nvidia-gpu.c ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val, val 83 drivers/i2c/busses/i2c-nvidia-gpu.c !(val & I2C_MST_CNTL_CYCLE_TRIGGER) || val 84 drivers/i2c/busses/i2c-nvidia-gpu.c (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY, val 88 drivers/i2c/busses/i2c-nvidia-gpu.c dev_err(i2cd->dev, "i2c timeout error %x\n", val); val 92 drivers/i2c/busses/i2c-nvidia-gpu.c val = readl(i2cd->regs + I2C_MST_CNTL); val 93 drivers/i2c/busses/i2c-nvidia-gpu.c switch (val & I2C_MST_CNTL_STATUS) { val 108 drivers/i2c/busses/i2c-nvidia-gpu.c u32 val; val 110 drivers/i2c/busses/i2c-nvidia-gpu.c val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ | val 113 drivers/i2c/busses/i2c-nvidia-gpu.c writel(val, i2cd->regs + I2C_MST_CNTL); val 119 drivers/i2c/busses/i2c-nvidia-gpu.c val = readl(i2cd->regs + I2C_MST_DATA); val 122 drivers/i2c/busses/i2c-nvidia-gpu.c data[0] = val; val 125 drivers/i2c/busses/i2c-nvidia-gpu.c put_unaligned_be16(val, data); val 128 drivers/i2c/busses/i2c-nvidia-gpu.c put_unaligned_be16(val >> 8, data); val 129 drivers/i2c/busses/i2c-nvidia-gpu.c data[2] = val; val 132 drivers/i2c/busses/i2c-nvidia-gpu.c put_unaligned_be32(val, data); val 154 drivers/i2c/busses/i2c-nvidia-gpu.c u32 val; val 158 drivers/i2c/busses/i2c-nvidia-gpu.c val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT); val 159 drivers/i2c/busses/i2c-nvidia-gpu.c writel(val, i2cd->regs + I2C_MST_CNTL); val 281 drivers/i2c/busses/i2c-ocores.c int reg, u8 mask, u8 val, val 290 drivers/i2c/busses/i2c-ocores.c if ((status & mask) == val) val 533 drivers/i2c/busses/i2c-ocores.c u32 val; val 539 drivers/i2c/busses/i2c-ocores.c if (!of_property_read_u32(np, "regstep", &val)) { val 540 drivers/i2c/busses/i2c-ocores.c if (!is_power_of_2(val)) { val 542 drivers/i2c/busses/i2c-ocores.c val); val 545 drivers/i2c/busses/i2c-ocores.c i2c->reg_shift = ilog2(val); val 572 drivers/i2c/busses/i2c-ocores.c &val)) { val 583 drivers/i2c/busses/i2c-ocores.c i2c->ip_clock_khz = val / 1000; val 98 drivers/i2c/busses/i2c-octeon-core.c u64 val; val 105 drivers/i2c/busses/i2c-octeon-core.c val = octeon_i2c_ctl_read(i2c); val 106 drivers/i2c/busses/i2c-octeon-core.c if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP))) val 110 drivers/i2c/busses/i2c-octeon-core.c if (val & TWSI_CTL_IFLG) val 735 drivers/i2c/busses/i2c-octeon-core.c static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val) val 739 drivers/i2c/busses/i2c-octeon-core.c octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR); val 125 drivers/i2c/busses/i2c-octeon-core.h static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr) val 127 drivers/i2c/busses/i2c-octeon-core.h __raw_writeq(val, addr); val 152 drivers/i2c/busses/i2c-octeon-core.h #define octeon_i2c_ctl_write(i2c, val) \ val 153 drivers/i2c/busses/i2c-octeon-core.h octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val) val 154 drivers/i2c/busses/i2c-octeon-core.h #define octeon_i2c_data_write(i2c, val) \ val 155 drivers/i2c/busses/i2c-octeon-core.h octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val) val 266 drivers/i2c/busses/i2c-omap.c int reg, u16 val) val 268 drivers/i2c/busses/i2c-omap.c writew_relaxed(val, omap->base + val 1300 drivers/i2c/busses/i2c-omap.c static void omap_i2c_set_scl(struct i2c_adapter *adap, int val) val 1306 drivers/i2c/busses/i2c-omap.c if (val) val 106 drivers/i2c/busses/i2c-owl.c static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) val 113 drivers/i2c/busses/i2c-owl.c regval |= val; val 115 drivers/i2c/busses/i2c-owl.c regval &= ~val; val 134 drivers/i2c/busses/i2c-owl.c unsigned int val, timeout = 0; val 143 drivers/i2c/busses/i2c-owl.c val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); val 144 drivers/i2c/busses/i2c-owl.c if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) val 159 drivers/i2c/busses/i2c-owl.c unsigned int val; val 161 drivers/i2c/busses/i2c-owl.c val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16); val 164 drivers/i2c/busses/i2c-owl.c writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); val 247 drivers/i2c/busses/i2c-owl.c unsigned int i2c_cmd, val; val 278 drivers/i2c/busses/i2c-owl.c val = readl(i2c_dev->base + OWL_I2C_REG_STAT); val 279 drivers/i2c/busses/i2c-owl.c if (val & OWL_I2C_STAT_LAB) { val 280 drivers/i2c/busses/i2c-owl.c val &= ~OWL_I2C_STAT_LAB; val 281 drivers/i2c/busses/i2c-owl.c writel(val, i2c_dev->base + OWL_I2C_REG_STAT); val 60 drivers/i2c/busses/i2c-parport-light.c port_write(op->port, oldval | op->val); val 62 drivers/i2c/busses/i2c-parport-light.c port_write(op->port, oldval & ~op->val); val 69 drivers/i2c/busses/i2c-parport-light.c return ((op->inverted && (oldval & op->val) != op->val) val 70 drivers/i2c/busses/i2c-parport-light.c || (!op->inverted && (oldval & op->val) == op->val)); val 121 drivers/i2c/busses/i2c-parport-light.c .val = (1 << 4), val 133 drivers/i2c/busses/i2c-parport-light.c if (adapter_parm[type].init.val) { val 169 drivers/i2c/busses/i2c-parport-light.c if (adapter_parm[type].init.val) val 234 drivers/i2c/busses/i2c-parport-light.c if (!adapter_parm[type].getscl.val) val 95 drivers/i2c/busses/i2c-parport.c port_write[op->port](data, oldval | op->val); val 97 drivers/i2c/busses/i2c-parport.c port_write[op->port](data, oldval & ~op->val); val 105 drivers/i2c/busses/i2c-parport.c return ((op->inverted && (oldval & op->val) != op->val) val 106 drivers/i2c/busses/i2c-parport.c || (!op->inverted && (oldval & op->val) == op->val)); val 201 drivers/i2c/busses/i2c-parport.c if (!adapter_parm[type].getscl.val) { val 219 drivers/i2c/busses/i2c-parport.c if (adapter_parm[type].init.val) { val 269 drivers/i2c/busses/i2c-parport.c if (adapter_parm[type].init.val) val 14 drivers/i2c/busses/i2c-parport.h u8 val; val 52 drivers/i2c/busses/i2c-pasemi.c static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) val 55 drivers/i2c/busses/i2c-pasemi.c smbus->base + reg, val); val 56 drivers/i2c/busses/i2c-pasemi.c outl(val, smbus->base + reg); val 37 drivers/i2c/busses/i2c-pca-isa.c static void pca_isa_writebyte(void *pd, int reg, int val) val 42 drivers/i2c/busses/i2c-pca-isa.c base+reg, val); val 44 drivers/i2c/busses/i2c-pca-isa.c outb(val, base+reg); val 60 drivers/i2c/busses/i2c-pca-platform.c static void i2c_pca_pf_writebyte8(void *pd, int reg, int val) val 63 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg); val 66 drivers/i2c/busses/i2c-pca-platform.c static void i2c_pca_pf_writebyte16(void *pd, int reg, int val) val 69 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg * 2); val 72 drivers/i2c/busses/i2c-pca-platform.c static void i2c_pca_pf_writebyte32(void *pd, int reg, int val) val 75 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg * 4); val 385 drivers/i2c/busses/i2c-pmcmsp.c u32 val = pmcmsptwi_readl(data->iobase + val 387 drivers/i2c/busses/i2c-pmcmsp.c if (val == 0) { val 232 drivers/i2c/busses/i2c-pnx.c u32 val; val 239 drivers/i2c/busses/i2c-pnx.c val = *alg_data->mif.buf++; val 242 drivers/i2c/busses/i2c-pnx.c val |= stop_bit; val 245 drivers/i2c/busses/i2c-pnx.c iowrite32(val, I2C_REG_TX(alg_data)); val 248 drivers/i2c/busses/i2c-pnx.c __func__, val, alg_data->mif.len + 1); val 302 drivers/i2c/busses/i2c-pnx.c unsigned int val = 0; val 323 drivers/i2c/busses/i2c-pnx.c val |= stop_bit; val 340 drivers/i2c/busses/i2c-pnx.c iowrite32(val, I2C_REG_TX(alg_data)); val 348 drivers/i2c/busses/i2c-pnx.c val = ioread32(I2C_REG_RX(alg_data)); val 349 drivers/i2c/busses/i2c-pnx.c *alg_data->mif.buf++ = (u8) (val & 0xff); val 351 drivers/i2c/busses/i2c-pnx.c __func__, val, alg_data->mif.len); val 236 drivers/i2c/busses/i2c-pxa.c decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) val 238 drivers/i2c/busses/i2c-pxa.c printk("%s %08x: ", prefix, val); val 240 drivers/i2c/busses/i2c-pxa.c const char *str = val & bits->mask ? bits->set : bits->unset; val 261 drivers/i2c/busses/i2c-pxa.c static void decode_ISR(unsigned int val) val 263 drivers/i2c/busses/i2c-pxa.c decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); val 286 drivers/i2c/busses/i2c-pxa.c static void decode_ICR(unsigned int val) val 288 drivers/i2c/busses/i2c-pxa.c decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); val 327 drivers/i2c/busses/i2c-pxa.c #define decode_ISR(val) do { } while (0) val 328 drivers/i2c/busses/i2c-pxa.c #define decode_ICR(val) do { } while (0) val 153 drivers/i2c/busses/i2c-qcom-geni.c u32 val; val 157 drivers/i2c/busses/i2c-qcom-geni.c val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; val 158 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); val 160 drivers/i2c/busses/i2c-qcom-geni.c val = itr->t_high_cnt << HIGH_COUNTER_SHFT; val 161 drivers/i2c/busses/i2c-qcom-geni.c val |= itr->t_low_cnt << LOW_COUNTER_SHFT; val 162 drivers/i2c/busses/i2c-qcom-geni.c val |= itr->t_cycle_cnt; val 163 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); val 212 drivers/i2c/busses/i2c-qcom-geni.c u32 val; val 254 drivers/i2c/busses/i2c-qcom-geni.c val = readl_relaxed(base + SE_GENI_RX_FIFOn); val 255 drivers/i2c/busses/i2c-qcom-geni.c while (gi2c->cur_rd < cur->len && p < sizeof(val)) { val 256 drivers/i2c/busses/i2c-qcom-geni.c cur->buf[gi2c->cur_rd++] = val & 0xff; val 257 drivers/i2c/busses/i2c-qcom-geni.c val >>= 8; val 268 drivers/i2c/busses/i2c-qcom-geni.c val = 0; val 270 drivers/i2c/busses/i2c-qcom-geni.c while (gi2c->cur_wr < cur->len && p < sizeof(val)) { val 272 drivers/i2c/busses/i2c-qcom-geni.c val |= temp << (p * 8); val 275 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(val, base + SE_GENI_TX_FIFOn); val 305 drivers/i2c/busses/i2c-qcom-geni.c u32 val; val 316 drivers/i2c/busses/i2c-qcom-geni.c val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); val 317 drivers/i2c/busses/i2c-qcom-geni.c } while (!(val & M_CMD_ABORT_EN) && time_left); val 319 drivers/i2c/busses/i2c-qcom-geni.c if (!(val & M_CMD_ABORT_EN)) val 325 drivers/i2c/busses/i2c-qcom-geni.c u32 val; val 331 drivers/i2c/busses/i2c-qcom-geni.c val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); val 332 drivers/i2c/busses/i2c-qcom-geni.c } while (!(val & RX_RESET_DONE) && time_left); val 334 drivers/i2c/busses/i2c-qcom-geni.c if (!(val & RX_RESET_DONE)) val 340 drivers/i2c/busses/i2c-qcom-geni.c u32 val; val 346 drivers/i2c/busses/i2c-qcom-geni.c val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); val 347 drivers/i2c/busses/i2c-qcom-geni.c } while (!(val & TX_RESET_DONE) && time_left); val 349 drivers/i2c/busses/i2c-qcom-geni.c if (!(val & TX_RESET_DONE)) val 411 drivers/i2c/busses/i2c-qup.c u32 val = readl(qup->base + QUP_STATE); val 413 drivers/i2c/busses/i2c-qup.c val |= QUP_I2C_FLUSH; val 414 drivers/i2c/busses/i2c-qup.c writel(val, qup->base + QUP_STATE); val 468 drivers/i2c/busses/i2c-qup.c u32 val; val 471 drivers/i2c/busses/i2c-qup.c val = QUP_TAG_START | addr; val 475 drivers/i2c/busses/i2c-qup.c val = 0; val 486 drivers/i2c/busses/i2c-qup.c val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; val 488 drivers/i2c/busses/i2c-qup.c val = qup_tag | msg->buf[qup->pos]; val 492 drivers/i2c/busses/i2c-qup.c writel(val, qup->base + QUP_OUT_FIFO_BASE); val 925 drivers/i2c/busses/i2c-qup.c u32 val = 0; val 931 drivers/i2c/busses/i2c-qup.c val = readl(qup->base + QUP_IN_FIFO_BASE); val 932 drivers/i2c/busses/i2c-qup.c msg->buf[qup->pos++] = val & 0xFF; val 934 drivers/i2c/busses/i2c-qup.c msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; val 947 drivers/i2c/busses/i2c-qup.c u32 addr, len, val; val 954 drivers/i2c/busses/i2c-qup.c val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr; val 955 drivers/i2c/busses/i2c-qup.c writel(val, qup->base + QUP_OUT_FIFO_BASE); val 151 drivers/i2c/busses/i2c-rcar.c static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) val 153 drivers/i2c/busses/i2c-rcar.c writel(val, priv->io + reg); val 169 drivers/i2c/busses/i2c-rcar.c static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) val 173 drivers/i2c/busses/i2c-rcar.c if (val) val 181 drivers/i2c/busses/i2c-rcar.c static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) val 185 drivers/i2c/busses/i2c-rcar.c if (val) val 626 drivers/i2c/busses/i2c-rcar.c u32 msr, val; val 630 drivers/i2c/busses/i2c-rcar.c val = rcar_i2c_read(priv, ICMCR); val 631 drivers/i2c/busses/i2c-rcar.c rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); val 160 drivers/i2c/busses/i2c-riic.c u8 val; val 173 drivers/i2c/busses/i2c-riic.c val = i2c_8bit_addr_from_msg(riic->msg); val 175 drivers/i2c/busses/i2c-riic.c val = *riic->buf; val 193 drivers/i2c/busses/i2c-riic.c writeb(val, riic->base + RIIC_ICDRT); val 245 drivers/i2c/busses/i2c-rk3x.c u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; val 250 drivers/i2c/busses/i2c-rk3x.c val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START; val 254 drivers/i2c/busses/i2c-rk3x.c val |= REG_CON_ACTACK; val 256 drivers/i2c/busses/i2c-rk3x.c i2c_writel(i2c, val, REG_CON); val 337 drivers/i2c/busses/i2c-rk3x.c u32 val; val 341 drivers/i2c/busses/i2c-rk3x.c val = 0; val 351 drivers/i2c/busses/i2c-rk3x.c val |= byte << (j * 8); val 355 drivers/i2c/busses/i2c-rk3x.c i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i); val 418 drivers/i2c/busses/i2c-rk3x.c u32 uninitialized_var(val); val 435 drivers/i2c/busses/i2c-rk3x.c val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4); val 437 drivers/i2c/busses/i2c-rk3x.c byte = (val >> ((i % 4) * 8)) & 0xff; val 877 drivers/i2c/busses/i2c-rk3x.c u32 val; val 886 drivers/i2c/busses/i2c-rk3x.c val = i2c_readl(i2c, REG_CON); val 887 drivers/i2c/busses/i2c-rk3x.c val &= ~REG_CON_TUNING_MASK; val 888 drivers/i2c/busses/i2c-rk3x.c val |= calc.tuning; val 889 drivers/i2c/busses/i2c-rk3x.c i2c_writel(i2c, val, REG_CON); val 1048 drivers/i2c/busses/i2c-rk3x.c u32 val; val 1089 drivers/i2c/busses/i2c-rk3x.c val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK; val 1090 drivers/i2c/busses/i2c-rk3x.c val |= REG_CON_EN | REG_CON_STOP; val 1091 drivers/i2c/busses/i2c-rk3x.c i2c_writel(i2c, val, REG_CON); val 894 drivers/i2c/busses/i2c-s3c2410.c unsigned long val, void *data) val 908 drivers/i2c/busses/i2c-s3c2410.c if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || val 909 drivers/i2c/busses/i2c-s3c2410.c (val == CPUFREQ_PRECHANGE && delta_f > 0)) { val 102 drivers/i2c/busses/i2c-sh7760.c static inline void OUT32(struct cami2c *cam, int reg, unsigned long val) val 104 drivers/i2c/busses/i2c-sh7760.c __raw_writel(val, (unsigned long)cam->iobase + reg); val 603 drivers/i2c/busses/i2c-sh_mobile.c u_int8_t val = iic_rd(pd, ICSR); val 605 drivers/i2c/busses/i2c-sh_mobile.c if (val & ICSR_DTE) val 608 drivers/i2c/busses/i2c-sh_mobile.c if (val & ICSR_TACK) val 622 drivers/i2c/busses/i2c-sh_mobile.c u_int8_t val = iic_rd(pd, ICSR); val 624 drivers/i2c/busses/i2c-sh_mobile.c dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); val 630 drivers/i2c/busses/i2c-sh_mobile.c if (!(val & ICSR_BUSY)) { val 632 drivers/i2c/busses/i2c-sh_mobile.c val |= pd->sr; val 633 drivers/i2c/busses/i2c-sh_mobile.c if (val & ICSR_TACK) val 635 drivers/i2c/busses/i2c-sh_mobile.c if (val & ICSR_AL) val 136 drivers/i2c/busses/i2c-sis5595.c u8 val; val 191 drivers/i2c/busses/i2c-sis5595.c if (pci_read_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, &val) val 194 drivers/i2c/busses/i2c-sis5595.c if ((val & 0x80) == 0) { val 196 drivers/i2c/busses/i2c-sis5595.c if (pci_write_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, val | 0x80) val 199 drivers/i2c/busses/i2c-sis5595.c if (pci_read_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, &val) val 202 drivers/i2c/busses/i2c-sis5595.c if ((val & 0x80) == 0) { val 273 drivers/i2c/busses/i2c-st.c u32 val, ns_per_clk; val 278 drivers/i2c/busses/i2c-st.c val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL | val 280 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_CLR); val 283 drivers/i2c/busses/i2c-st.c val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9; val 284 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_CTL); val 290 drivers/i2c/busses/i2c-st.c val = rate / (2 * t->rate); val 291 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_BRG); val 300 drivers/i2c/busses/i2c-st.c val = t->rep_start_hold / ns_per_clk; val 301 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); val 304 drivers/i2c/busses/i2c-st.c val = t->rep_start_setup / ns_per_clk; val 305 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); val 308 drivers/i2c/busses/i2c-st.c val = t->start_hold / ns_per_clk; val 309 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); val 312 drivers/i2c/busses/i2c-st.c val = t->data_setup_time / ns_per_clk; val 313 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP); val 316 drivers/i2c/busses/i2c-st.c val = t->stop_setup_time / ns_per_clk; val 317 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP); val 320 drivers/i2c/busses/i2c-st.c val = t->bus_free_time / ns_per_clk; val 321 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE); val 324 drivers/i2c/busses/i2c-st.c val = rate / 10000000; val 325 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_PRSCALER); val 326 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT); val 329 drivers/i2c/busses/i2c-st.c val = i2c_dev->scl_min_width_us * rate / 100000000; val 330 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH); val 333 drivers/i2c/busses/i2c-st.c val = i2c_dev->sda_min_width_us * rate / 100000000; val 334 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT); val 227 drivers/i2c/busses/i2c-stm32f4.c u32 val; val 246 drivers/i2c/busses/i2c-stm32f4.c val = i2c_dev->parent_rate / (100000 << 1); val 266 drivers/i2c/busses/i2c-stm32f4.c val = DIV_ROUND_UP(i2c_dev->parent_rate, 400000 * 3); val 272 drivers/i2c/busses/i2c-stm32f4.c ccr |= STM32F4_I2C_CCR_CCR(val); val 714 drivers/i2c/busses/i2c-stm32f7.c u8 *val; val 725 drivers/i2c/busses/i2c-stm32f7.c val = f7_msg->buf - sizeof(u8); val 726 drivers/i2c/busses/i2c-stm32f7.c f7_msg->count = *val; val 1313 drivers/i2c/busses/i2c-stm32f7.c u8 val; val 1322 drivers/i2c/busses/i2c-stm32f7.c &val); val 1325 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(val, base + STM32F7_I2C_TXDR); val 1334 drivers/i2c/busses/i2c-stm32f7.c val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); val 1337 drivers/i2c/busses/i2c-stm32f7.c &val); val 1372 drivers/i2c/busses/i2c-stm32f7.c i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); val 192 drivers/i2c/busses/i2c-stu300.c u32 val; val 193 drivers/i2c/busses/i2c-stu300.c val = stu300_r8(dev->virtbase + I2C_CR); val 194 drivers/i2c/busses/i2c-stu300.c val |= I2C_CR_INTERRUPT_ENABLE; val 196 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, dev->virtbase + I2C_CR); val 197 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, dev->virtbase + I2C_CR); val 202 drivers/i2c/busses/i2c-stu300.c u32 val; val 203 drivers/i2c/busses/i2c-stu300.c val = stu300_r8(dev->virtbase + I2C_CR); val 204 drivers/i2c/busses/i2c-stu300.c val &= ~I2C_CR_INTERRUPT_ENABLE; val 206 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, dev->virtbase + I2C_CR); val 207 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, dev->virtbase + I2C_CR); val 480 drivers/i2c/busses/i2c-stu300.c u32 val; val 502 drivers/i2c/busses/i2c-stu300.c val = ((clkrate/dev->speed) - 9)/3 + 1; val 505 drivers/i2c/busses/i2c-stu300.c val = ((clkrate/dev->speed) - 7)/2 + 1; val 508 drivers/i2c/busses/i2c-stu300.c if (val < 0x002) { val 515 drivers/i2c/busses/i2c-stu300.c if (val & 0xFFFFF000U) { val 523 drivers/i2c/busses/i2c-stu300.c stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM, val 526 drivers/i2c/busses/i2c-stu300.c "Fast Mode I2C\n", val); val 529 drivers/i2c/busses/i2c-stu300.c stu300_wr8((val & I2C_CCR_CC_MASK), val 532 drivers/i2c/busses/i2c-stu300.c "0x%08x, Standard Mode I2C\n", val); val 536 drivers/i2c/busses/i2c-stu300.c stu300_wr8(((val >> 7) & 0x1F), val 589 drivers/i2c/busses/i2c-stu300.c u32 val; val 594 drivers/i2c/busses/i2c-stu300.c val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) & val 598 drivers/i2c/busses/i2c-stu300.c val |= 0x01; val 600 drivers/i2c/busses/i2c-stu300.c val = i2c_8bit_addr_from_msg(msg); val 610 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, dev->virtbase + I2C_DR); val 619 drivers/i2c/busses/i2c-stu300.c val = msg->addr & I2C_DR_D_MASK; val 621 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, dev->virtbase + I2C_DR); val 637 drivers/i2c/busses/i2c-stu300.c val = stu300_r8(dev->virtbase + I2C_CR); val 638 drivers/i2c/busses/i2c-stu300.c val |= I2C_CR_PERIPHERAL_ENABLE; val 639 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, dev->virtbase + I2C_CR); val 648 drivers/i2c/busses/i2c-stu300.c u32 val; val 738 drivers/i2c/busses/i2c-stu300.c val = I2C_CR_PERIPHERAL_ENABLE; val 741 drivers/i2c/busses/i2c-stu300.c val |= I2C_CR_STOP_ENABLE; val 743 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, val 780 drivers/i2c/busses/i2c-stu300.c val = I2C_CR_PERIPHERAL_ENABLE; val 781 drivers/i2c/busses/i2c-stu300.c val |= I2C_CR_STOP_ENABLE; val 782 drivers/i2c/busses/i2c-stu300.c stu300_wr8(val, dev->virtbase + I2C_CR); val 795 drivers/i2c/busses/i2c-stu300.c val = stu300_r8(dev->virtbase + I2C_SR2); val 796 drivers/i2c/busses/i2c-stu300.c val = stu300_r8(dev->virtbase + I2C_SR1); val 284 drivers/i2c/busses/i2c-tegra.c static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, val 287 drivers/i2c/busses/i2c-tegra.c writel(val, i2c_dev->base + reg); val 307 drivers/i2c/busses/i2c-tegra.c static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, val 310 drivers/i2c/busses/i2c-tegra.c writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); val 459 drivers/i2c/busses/i2c-tegra.c u32 mask, val; val 471 drivers/i2c/busses/i2c-tegra.c val = i2c_readl(i2c_dev, offset); val 472 drivers/i2c/busses/i2c-tegra.c val |= mask; val 473 drivers/i2c/busses/i2c-tegra.c i2c_writel(i2c_dev, val, offset); val 487 drivers/i2c/busses/i2c-tegra.c u32 val; val 501 drivers/i2c/busses/i2c-tegra.c val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); val 502 drivers/i2c/busses/i2c-tegra.c rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >> val 505 drivers/i2c/busses/i2c-tegra.c val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); val 506 drivers/i2c/busses/i2c-tegra.c rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> val 531 drivers/i2c/busses/i2c-tegra.c val = i2c_readl(i2c_dev, I2C_RX_FIFO); val 532 drivers/i2c/busses/i2c-tegra.c val = cpu_to_le32(val); val 533 drivers/i2c/busses/i2c-tegra.c memcpy(buf, &val, buf_remaining); val 550 drivers/i2c/busses/i2c-tegra.c u32 val; val 557 drivers/i2c/busses/i2c-tegra.c val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); val 558 drivers/i2c/busses/i2c-tegra.c tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >> val 561 drivers/i2c/busses/i2c-tegra.c val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); val 562 drivers/i2c/busses/i2c-tegra.c tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> val 604 drivers/i2c/busses/i2c-tegra.c memcpy(&val, buf, buf_remaining); val 605 drivers/i2c/busses/i2c-tegra.c val = le32_to_cpu(val); val 612 drivers/i2c/busses/i2c-tegra.c i2c_writel(i2c_dev, val, I2C_TX_FIFO); val 627 drivers/i2c/busses/i2c-tegra.c u32 val; val 629 drivers/i2c/busses/i2c-tegra.c val = dvc_readl(i2c_dev, DVC_CTRL_REG3); val 630 drivers/i2c/busses/i2c-tegra.c val |= DVC_CTRL_REG3_SW_PROG; val 631 drivers/i2c/busses/i2c-tegra.c val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; val 632 drivers/i2c/busses/i2c-tegra.c dvc_writel(i2c_dev, val, DVC_CTRL_REG3); val 634 drivers/i2c/busses/i2c-tegra.c val = dvc_readl(i2c_dev, DVC_CTRL_REG1); val 635 drivers/i2c/busses/i2c-tegra.c val |= DVC_CTRL_REG1_INTR_EN; val 636 drivers/i2c/busses/i2c-tegra.c dvc_writel(i2c_dev, val, DVC_CTRL_REG1); val 683 drivers/i2c/busses/i2c-tegra.c u32 val; val 691 drivers/i2c/busses/i2c-tegra.c err = readl_poll_timeout_atomic(addr, val, val == 0, val 695 drivers/i2c/busses/i2c-tegra.c err = readl_poll_timeout(addr, val, val == 0, 1000, val 710 drivers/i2c/busses/i2c-tegra.c u32 val; val 723 drivers/i2c/busses/i2c-tegra.c val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | val 727 drivers/i2c/busses/i2c-tegra.c val |= I2C_CNFG_MULTI_MASTER_MODE; val 729 drivers/i2c/busses/i2c-tegra.c i2c_writel(i2c_dev, val, I2C_CNFG); val 750 drivers/i2c/busses/i2c-tegra.c val = (thigh << I2C_THIGH_SHIFT) | tlow; val 751 drivers/i2c/busses/i2c-tegra.c i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); val 935 drivers/i2c/busses/i2c-tegra.c u32 val, reg; val 963 drivers/i2c/busses/i2c-tegra.c val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); val 965 drivers/i2c/busses/i2c-tegra.c val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); val 974 drivers/i2c/busses/i2c-tegra.c val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); val 976 drivers/i2c/busses/i2c-tegra.c val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); val 993 drivers/i2c/busses/i2c-tegra.c val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | val 996 drivers/i2c/busses/i2c-tegra.c val = I2C_FIFO_CONTROL_TX_TRIG(8) | val 999 drivers/i2c/busses/i2c-tegra.c i2c_writel(i2c_dev, val, reg); val 452 drivers/i2c/busses/i2c-uniphier-f.c static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val) val 456 drivers/i2c/busses/i2c-uniphier-f.c writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0, val 253 drivers/i2c/busses/i2c-uniphier.c u32 val = UNIPHIER_I2C_BRST_RSCL; val 255 drivers/i2c/busses/i2c-uniphier.c val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN; val 256 drivers/i2c/busses/i2c-uniphier.c writel(val, priv->membase + UNIPHIER_I2C_BRST); val 267 drivers/i2c/busses/i2c-uniphier.c static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val) val 271 drivers/i2c/busses/i2c-uniphier.c writel(val ? UNIPHIER_I2C_BRST_RSCL : 0, val 126 drivers/i2c/busses/i2c-wmt.c u16 val, tcr_val; val 149 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 150 drivers/i2c/busses/i2c-wmt.c val &= ~CR_TX_END; val 151 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 153 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 154 drivers/i2c/busses/i2c-wmt.c val |= CR_CPU_RDY; val 155 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 170 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 171 drivers/i2c/busses/i2c-wmt.c val |= CR_CPU_RDY; val 172 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 188 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CSR); val 189 drivers/i2c/busses/i2c-wmt.c if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) { val 195 drivers/i2c/busses/i2c-wmt.c val = CR_TX_END | CR_CPU_RDY | CR_ENABLE; val 196 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 217 drivers/i2c/busses/i2c-wmt.c u16 val, tcr_val; val 228 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 229 drivers/i2c/busses/i2c-wmt.c val &= ~CR_TX_END; val 230 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 232 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 233 drivers/i2c/busses/i2c-wmt.c val &= ~CR_TX_NEXT_NO_ACK; val 234 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 237 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 238 drivers/i2c/busses/i2c-wmt.c val |= CR_CPU_RDY; val 239 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 243 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 244 drivers/i2c/busses/i2c-wmt.c val |= CR_TX_NEXT_NO_ACK; val 245 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 260 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 261 drivers/i2c/busses/i2c-wmt.c val |= CR_CPU_RDY; val 262 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 280 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 281 drivers/i2c/busses/i2c-wmt.c val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY); val 282 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 284 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); val 285 drivers/i2c/busses/i2c-wmt.c val |= CR_CPU_RDY; val 286 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); val 129 drivers/i2c/busses/i2c-xgene-slimpro.c u16 ret, val; val 131 drivers/i2c/busses/i2c-xgene-slimpro.c val = le16_to_cpu(READ_ONCE(*addr)); val 132 drivers/i2c/busses/i2c-xgene-slimpro.c ret = val & mask; val 133 drivers/i2c/busses/i2c-xgene-slimpro.c val &= ~mask; val 134 drivers/i2c/busses/i2c-xgene-slimpro.c WRITE_ONCE(*addr, cpu_to_le16(val)); val 343 drivers/i2c/busses/i2c-xgene-slimpro.c u32 val; val 350 drivers/i2c/busses/i2c-xgene-slimpro.c BYTE_DATA, &val); val 351 drivers/i2c/busses/i2c-xgene-slimpro.c data->byte = val; val 362 drivers/i2c/busses/i2c-xgene-slimpro.c BYTE_DATA, &val); val 363 drivers/i2c/busses/i2c-xgene-slimpro.c data->byte = val; val 365 drivers/i2c/busses/i2c-xgene-slimpro.c val = data->byte; val 368 drivers/i2c/busses/i2c-xgene-slimpro.c BYTE_DATA, val); val 375 drivers/i2c/busses/i2c-xgene-slimpro.c WORD_DATA, &val); val 376 drivers/i2c/busses/i2c-xgene-slimpro.c data->word = val; val 378 drivers/i2c/busses/i2c-xgene-slimpro.c val = data->word; val 381 drivers/i2c/busses/i2c-xgene-slimpro.c WORD_DATA, val); val 104 drivers/i2c/busses/i2c-xlp9xx.c unsigned long reg, u32 val) val 106 drivers/i2c/busses/i2c-xlp9xx.c writel(val, priv->base + reg); val 163 drivers/i2c/busses/i2c-xlp9xx.c u32 val, len; val 171 drivers/i2c/busses/i2c-xlp9xx.c val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL); val 177 drivers/i2c/busses/i2c-xlp9xx.c val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) | val 179 drivers/i2c/busses/i2c-xlp9xx.c xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val); val 329 drivers/i2c/busses/i2c-xlp9xx.c u32 intr_mask, cmd, val, len; val 347 drivers/i2c/busses/i2c-xlp9xx.c val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL); val 349 drivers/i2c/busses/i2c-xlp9xx.c val &= ~XLP9XX_I2C_CTRL_FIFORD; val 351 drivers/i2c/busses/i2c-xlp9xx.c val |= XLP9XX_I2C_CTRL_FIFORD; /* read */ val 354 drivers/i2c/busses/i2c-xlp9xx.c val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/ val 356 drivers/i2c/busses/i2c-xlp9xx.c val &= ~XLP9XX_I2C_CTRL_ADDMODE; val 367 drivers/i2c/busses/i2c-xlp9xx.c val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) | val 369 drivers/i2c/busses/i2c-xlp9xx.c xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val); val 64 drivers/i2c/busses/i2c-xlr.c static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val) val 66 drivers/i2c/busses/i2c-xlr.c __raw_writel(val, base + reg); val 70 drivers/i2c/busses/i2c-zx2967.c u32 val, unsigned long reg) val 72 drivers/i2c/busses/i2c-zx2967.c writel_relaxed(val, i2c->reg_base + reg); val 114 drivers/i2c/busses/i2c-zx2967.c u32 val; val 118 drivers/i2c/busses/i2c-zx2967.c val = I2C_RFIFO_RESET; val 121 drivers/i2c/busses/i2c-zx2967.c val = I2C_WFIFO_RESET; val 124 drivers/i2c/busses/i2c-zx2967.c val |= zx2967_i2c_readl(i2c, offset); val 125 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, offset); val 130 drivers/i2c/busses/i2c-zx2967.c u8 val[I2C_FIFO_MAX] = {0}; val 139 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_readsb(i2c, val, REG_DATA, size); val 141 drivers/i2c/busses/i2c-zx2967.c *i2c->cur_trans++ = val[i]; val 179 drivers/i2c/busses/i2c-zx2967.c u32 val; val 182 drivers/i2c/busses/i2c-zx2967.c val = I2C_MASTER | I2C_IRQ_MSK_ENABLE; val 183 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_CMD); val 231 drivers/i2c/busses/i2c-zx2967.c u16 val; val 233 drivers/i2c/busses/i2c-zx2967.c val = (addr >> I2C_ADDR_LOW_SHIFT) & I2C_ADDR_LOW_MASK; val 234 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_DEVADDR_L); val 236 drivers/i2c/busses/i2c-zx2967.c val = (addr >> I2C_ADDR_HI_SHIFT) & I2C_ADDR_HI_MASK; val 237 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_DEVADDR_H); val 238 drivers/i2c/busses/i2c-zx2967.c if (val) val 239 drivers/i2c/busses/i2c-zx2967.c val = zx2967_i2c_readl(i2c, REG_CMD) | I2C_ADDR_MODE_TEN; val 241 drivers/i2c/busses/i2c-zx2967.c val = zx2967_i2c_readl(i2c, REG_CMD) & ~I2C_ADDR_MODE_TEN; val 242 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_CMD); val 328 drivers/i2c/busses/i2c-zx2967.c u32 val; val 330 drivers/i2c/busses/i2c-zx2967.c val = zx2967_i2c_readl(i2c, REG_RDCONF); val 331 drivers/i2c/busses/i2c-zx2967.c val |= I2C_RFIFO_RESET; val 332 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_RDCONF); val 334 drivers/i2c/busses/i2c-zx2967.c val = zx2967_i2c_readl(i2c, REG_CMD); val 335 drivers/i2c/busses/i2c-zx2967.c val &= ~I2C_RW_READ; val 336 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_CMD); val 363 drivers/i2c/busses/i2c-zx2967.c u32 val; val 367 drivers/i2c/busses/i2c-zx2967.c val = zx2967_i2c_readl(i2c, REG_CMD); val 368 drivers/i2c/busses/i2c-zx2967.c val |= I2C_CMB_RW_EN; val 369 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_CMD); val 371 drivers/i2c/busses/i2c-zx2967.c val = zx2967_i2c_readl(i2c, REG_CMD); val 372 drivers/i2c/busses/i2c-zx2967.c val |= I2C_START; val 373 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_CMD); val 386 drivers/i2c/busses/i2c-zx2967.c val = zx2967_i2c_readl(i2c, REG_DATA); val 387 drivers/i2c/busses/i2c-zx2967.c data->byte = val; val 405 drivers/i2c/busses/i2c-zx2967.c u32 val; val 408 drivers/i2c/busses/i2c-zx2967.c val = zx2967_i2c_readl(i2c, REG_CMD); val 409 drivers/i2c/busses/i2c-zx2967.c val |= I2C_START; val 410 drivers/i2c/busses/i2c-zx2967.c zx2967_i2c_writel(i2c, val, REG_CMD); val 382 drivers/i2c/busses/scx200_acb.c u8 val; val 395 drivers/i2c/busses/scx200_acb.c val = inb(ACBCTL1); val 396 drivers/i2c/busses/scx200_acb.c if (val) { val 397 drivers/i2c/busses/scx200_acb.c pr_debug("disabled, but ACBCTL1=0x%02x\n", val); val 405 drivers/i2c/busses/scx200_acb.c val = inb(ACBCTL1); val 406 drivers/i2c/busses/scx200_acb.c if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) { val 408 drivers/i2c/busses/scx200_acb.c val); val 138 drivers/i2c/i2c-core-base.c static void set_scl_gpio_value(struct i2c_adapter *adap, int val) val 140 drivers/i2c/i2c-core-base.c gpiod_set_value_cansleep(adap->bus_recovery_info->scl_gpiod, val); val 148 drivers/i2c/i2c-core-base.c static void set_sda_gpio_value(struct i2c_adapter *adap, int val) val 150 drivers/i2c/i2c-core-base.c gpiod_set_value_cansleep(adap->bus_recovery_info->sda_gpiod, val); val 1890 drivers/i2c/i2c-core-base.c #define i2c_quirk_exceeded(val, quirk) ((quirk) && ((val) > (quirk))) val 46 drivers/i2c/i2c-slave-eeprom.c enum i2c_slave_event event, u8 *val) val 55 drivers/i2c/i2c-slave-eeprom.c eeprom->buffer_idx = *val | (eeprom->buffer_idx << 8); val 60 drivers/i2c/i2c-slave-eeprom.c eeprom->buffer[eeprom->buffer_idx++ & eeprom->address_mask] = *val; val 72 drivers/i2c/i2c-slave-eeprom.c *val = eeprom->buffer[eeprom->buffer_idx & eeprom->address_mask]; val 192 drivers/i2c/muxes/i2c-demux-pinctrl.c unsigned int val; val 195 drivers/i2c/muxes/i2c-demux-pinctrl.c ret = kstrtouint(buf, 0, &val); val 199 drivers/i2c/muxes/i2c-demux-pinctrl.c if (val >= priv->num_chan) val 202 drivers/i2c/muxes/i2c-demux-pinctrl.c ret = i2c_demux_change_master(priv, val); val 25 drivers/i2c/muxes/i2c-mux-gpio.c static void i2c_mux_gpio_set(const struct gpiomux *mux, unsigned val) val 27 drivers/i2c/muxes/i2c-mux-gpio.c DECLARE_BITMAP(values, BITS_PER_TYPE(val)); val 29 drivers/i2c/muxes/i2c-mux-gpio.c values[0] = val; val 79 drivers/i2c/muxes/i2c-mux-ltc4306.c unsigned int val; val 82 drivers/i2c/muxes/i2c-mux-ltc4306.c ret = regmap_read(data->regmap, LTC_REG_CONFIG, &val); val 86 drivers/i2c/muxes/i2c-mux-ltc4306.c return !!(val & BIT(1 - offset)); val 102 drivers/i2c/muxes/i2c-mux-ltc4306.c unsigned int val; val 105 drivers/i2c/muxes/i2c-mux-ltc4306.c ret = regmap_read(data->regmap, LTC_REG_MODE, &val); val 109 drivers/i2c/muxes/i2c-mux-ltc4306.c return !!(val & BIT(7 - offset)); val 135 drivers/i2c/muxes/i2c-mux-ltc4306.c unsigned int val; val 139 drivers/i2c/muxes/i2c-mux-ltc4306.c val = 0; val 142 drivers/i2c/muxes/i2c-mux-ltc4306.c val = BIT(4 - offset); val 149 drivers/i2c/muxes/i2c-mux-ltc4306.c BIT(4 - offset), val); val 216 drivers/i2c/muxes/i2c-mux-ltc4306.c unsigned int val = 0; val 268 drivers/i2c/muxes/i2c-mux-ltc4306.c val |= LTC_DOWNSTREAM_ACCL_EN; val 272 drivers/i2c/muxes/i2c-mux-ltc4306.c val |= LTC_UPSTREAM_ACCL_EN; val 274 drivers/i2c/muxes/i2c-mux-ltc4306.c if (regmap_write(data->regmap, LTC_REG_CONFIG, val) < 0) val 94 drivers/i2c/muxes/i2c-mux-mlxcpld.c struct i2c_client *client, u8 val) val 97 drivers/i2c/muxes/i2c-mux-mlxcpld.c union i2c_smbus_data data = { .byte = val }; val 98 drivers/i2c/muxes/i2c-mux-pca9541.c static int pca9541_reg_write(struct i2c_client *client, u8 command, u8 val) val 101 drivers/i2c/muxes/i2c-mux-pca9541.c union i2c_smbus_data data = { .byte = val }; val 223 drivers/i2c/muxes/i2c-mux-pca954x.c struct i2c_client *client, u8 val) val 228 drivers/i2c/muxes/i2c-mux-pca954x.c I2C_SMBUS_WRITE, val, val 296 drivers/i2c/muxes/i2c-mux-pca954x.c int val; val 299 drivers/i2c/muxes/i2c-mux-pca954x.c ret = kstrtoint(buf, 0, &val); val 303 drivers/i2c/muxes/i2c-mux-pca954x.c if (val != MUX_IDLE_AS_IS && val != MUX_IDLE_DISCONNECT && val 304 drivers/i2c/muxes/i2c-mux-pca954x.c (val < 0 || val >= data->chip->nchans)) val 309 drivers/i2c/muxes/i2c-mux-pca954x.c WRITE_ONCE(data->idle_state, val); val 314 drivers/i2c/muxes/i2c-mux-pca954x.c if (data->last_chan || val != MUX_IDLE_DISCONNECT) val 2048 drivers/i3c/master.c u32 val; val 2066 drivers/i3c/master.c if (!of_property_read_u32(i3cbus_np, "i2c-scl-hz", &val)) val 2067 drivers/i3c/master.c master->bus.scl_rate.i2c = val; val 2069 drivers/i3c/master.c if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val)) val 2070 drivers/i3c/master.c master->bus.scl_rate.i3c = val; val 316 drivers/i3c/master/i3c-master-cdns.c #define GPI_REG(val, id) \ val 317 drivers/i3c/master/i3c-master-cdns.c (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0)) val 320 drivers/i3c/master/i3c-master-cdns.c #define GPO_REG(val, id) \ val 321 drivers/i3c/master/i3c-master-cdns.c (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0)) val 1529 drivers/i3c/master/i3c-master-cdns.c u32 val; val 1578 drivers/i3c/master/i3c-master-cdns.c val = readl(master->regs + CONF_STATUS0); val 1581 drivers/i3c/master/i3c-master-cdns.c master->maxdevs = CONF_STATUS0_DEVS_NUM(val); val 1584 drivers/i3c/master/i3c-master-cdns.c val = readl(master->regs + CONF_STATUS1); val 1585 drivers/i3c/master/i3c-master-cdns.c master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val); val 1586 drivers/i3c/master/i3c-master-cdns.c master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val); val 1587 drivers/i3c/master/i3c-master-cdns.c master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val); val 1588 drivers/i3c/master/i3c-master-cdns.c master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val); val 1589 drivers/i3c/master/i3c-master-cdns.c master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val); val 1592 drivers/i3c/master/i3c-master-cdns.c master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val); val 189 drivers/ide/cmd640.c static void (*__put_cmd640_reg)(u16 reg, u8 val); val 205 drivers/ide/cmd640.c static void put_cmd640_reg_pci1(u16 reg, u8 val) val 208 drivers/ide/cmd640.c outb_p(val, (reg & 3) | 0xcfc); val 219 drivers/ide/cmd640.c static void put_cmd640_reg_pci2(u16 reg, u8 val) val 222 drivers/ide/cmd640.c outb_p(val, cmd640_key + reg); val 238 drivers/ide/cmd640.c static void put_cmd640_reg_vlb(u16 reg, u8 val) val 241 drivers/ide/cmd640.c outb_p(val, cmd640_key + 4); val 261 drivers/ide/cmd640.c static void put_cmd640_reg(u16 reg, u8 val) val 266 drivers/ide/cmd640.c __put_cmd640_reg(reg, val); val 58 drivers/ide/cs5536.c static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val) val 63 drivers/ide/cs5536.c rdmsr(MSR_IDE_CFG + reg, *val, dummy); val 67 drivers/ide/cs5536.c return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val); val 70 drivers/ide/cs5536.c static int cs5536_write(struct pci_dev *pdev, int reg, int val) val 73 drivers/ide/cs5536.c wrmsr(MSR_IDE_CFG + reg, val, 0); val 77 drivers/ide/cs5536.c return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val); val 74 drivers/ide/ide-disk_proc.c __le16 *val = (__le16 *)buf; val 78 drivers/ide/ide-disk_proc.c seq_printf(m, "%04x%c", le16_to_cpu(val[i]), val 65 drivers/ide/ide-dma-sff.c static void ide_dma_sff_write_status(ide_hwif_t *hwif, u8 val) val 70 drivers/ide/ide-dma-sff.c writeb(val, (void __iomem *)addr); val 72 drivers/ide/ide-dma-sff.c outb(val, addr); val 47 drivers/ide/ide-generic.c u16 val; val 64 drivers/ide/ide-generic.c pci_read_config_word(p, 0x6C, &val); val 65 drivers/ide/ide-generic.c if (val & 0x8000) { val 67 drivers/ide/ide-generic.c if (val & 0x4000) val 23 drivers/ide/ide-io-std.c static void ide_outb(u8 val, unsigned long port) val 25 drivers/ide/ide-io-std.c outb(val, port); val 93 drivers/ide/ide-proc.c __le16 *val = (__le16 *)buf; val 97 drivers/ide/ide-proc.c seq_printf(m, "%04x%c", le16_to_cpu(val[i]), val 145 drivers/ide/ide-proc.c int val = -EINVAL; val 148 drivers/ide/ide-proc.c val = ds->get(drive); val 150 drivers/ide/ide-proc.c return val; val 172 drivers/ide/ide-proc.c const struct ide_proc_devset *setting, int val) val 181 drivers/ide/ide-proc.c && (val < setting->min || val > setting->max)) val 183 drivers/ide/ide-proc.c return ide_devset_execute(drive, ds, val); val 327 drivers/ide/ide-proc.c unsigned val; val 347 drivers/ide/ide-proc.c val = simple_strtoul(p, &q, 10); val 371 drivers/ide/ide-proc.c ide_write_setting(drive, setting, val * div_factor / mul_factor); val 470 drivers/ide/setup-pci.c (tmp & e->mask) != e->val)) { val 155 drivers/ide/siimage.c static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr) val 160 drivers/ide/siimage.c writeb(val, (void __iomem *)addr); val 162 drivers/ide/siimage.c pci_write_config_byte(dev, addr, val); val 165 drivers/ide/siimage.c static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr) val 170 drivers/ide/siimage.c writew(val, (void __iomem *)addr); val 172 drivers/ide/siimage.c pci_write_config_word(dev, addr, val); val 175 drivers/ide/siimage.c static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr) val 180 drivers/ide/siimage.c writel(val, (void __iomem *)addr); val 182 drivers/ide/siimage.c pci_write_config_dword(dev, addr, val); val 345 drivers/ide/siimage.c u8 val = sil_ioread8(dev, addr); val 348 drivers/ide/siimage.c return (val & 8) ? 1 : 0; val 117 drivers/ide/sl82c105.c u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; val 119 drivers/ide/sl82c105.c pci_read_config_dword(dev, 0x40, &val); val 121 drivers/ide/sl82c105.c return (val & mask) ? 1 : 0; val 134 drivers/ide/sl82c105.c u16 val; val 136 drivers/ide/sl82c105.c pci_read_config_word(dev, 0x7e, &val); val 137 drivers/ide/sl82c105.c pci_write_config_word(dev, 0x7e, val | (1 << 2)); val 138 drivers/ide/sl82c105.c pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); val 152 drivers/ide/sl82c105.c u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; val 160 drivers/ide/sl82c105.c pci_read_config_dword(dev, 0x40, &val); val 161 drivers/ide/sl82c105.c if (val & mask) val 225 drivers/ide/sl82c105.c u32 val; val 227 drivers/ide/sl82c105.c pci_read_config_dword(dev, 0x40, &val); val 228 drivers/ide/sl82c105.c val |= (CTRL_P1F16 | CTRL_P0F16); val 229 drivers/ide/sl82c105.c pci_write_config_dword(dev, 0x40, val); val 276 drivers/ide/sl82c105.c u32 val; val 278 drivers/ide/sl82c105.c pci_read_config_dword(dev, 0x40, &val); val 279 drivers/ide/sl82c105.c val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; val 280 drivers/ide/sl82c105.c pci_write_config_dword(dev, 0x40, val); val 92 drivers/ide/tx4939ide.c static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) val 94 drivers/ide/tx4939ide.c __raw_writel(val, base + tx4939ide_swizzlel(reg)); val 96 drivers/ide/tx4939ide.c static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) val 98 drivers/ide/tx4939ide.c __raw_writew(val, base + tx4939ide_swizzlew(reg)); val 100 drivers/ide/tx4939ide.c static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) val 102 drivers/ide/tx4939ide.c __raw_writeb(val, base + tx4939ide_swizzleb(reg)); val 110 drivers/ide/tx4939ide.c u32 mask, val; val 123 drivers/ide/tx4939ide.c val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0); val 124 drivers/ide/tx4939ide.c hwif->select_data = (hwif->select_data & ~mask) | val; val 130 drivers/ide/tx4939ide.c u32 mask, val; val 135 drivers/ide/tx4939ide.c val = mode - XFER_UDMA_0 + 8; val 137 drivers/ide/tx4939ide.c val = mode - XFER_MW_DMA_0 + 5; val 140 drivers/ide/tx4939ide.c val <<= 20; val 143 drivers/ide/tx4939ide.c val <<= 4; val 145 drivers/ide/tx4939ide.c hwif->select_data = (hwif->select_data & ~mask) | val; val 102 drivers/iio/accel/adis16201.c int *val, int *val2, val 114 drivers/iio/accel/adis16201.c ADIS16201_ERROR_ACTIVE, val); val 120 drivers/iio/accel/adis16201.c *val = 1; val 124 drivers/iio/accel/adis16201.c *val = 0; val 129 drivers/iio/accel/adis16201.c *val = -470; val 138 drivers/iio/accel/adis16201.c *val = 0; val 142 drivers/iio/accel/adis16201.c *val = 0; val 155 drivers/iio/accel/adis16201.c *val = 25000 / -470 - 1278; val 173 drivers/iio/accel/adis16201.c *val = sign_extend32(val16, bits - 1); val 182 drivers/iio/accel/adis16201.c int val, val 204 drivers/iio/accel/adis16201.c val & m); val 109 drivers/iio/accel/adis16209.c int val, val 129 drivers/iio/accel/adis16209.c val & m); val 134 drivers/iio/accel/adis16209.c int *val, int *val2, val 146 drivers/iio/accel/adis16209.c ADIS16209_ERROR_ACTIVE, val); val 150 drivers/iio/accel/adis16209.c *val = 0; val 163 drivers/iio/accel/adis16209.c *val = -470; val 172 drivers/iio/accel/adis16209.c *val = 0; val 181 drivers/iio/accel/adis16209.c *val = 0; val 194 drivers/iio/accel/adis16209.c *val = 25000 / -470 - 0x4FE; val 209 drivers/iio/accel/adis16209.c *val = sign_extend32(val16, bits - 1); val 87 drivers/iio/accel/adxl345_core.c int *val, int *val2, long mask) val 108 drivers/iio/accel/adxl345_core.c *val = sign_extend32(le16_to_cpu(accel), 12); val 111 drivers/iio/accel/adxl345_core.c *val = 0; val 131 drivers/iio/accel/adxl345_core.c *val = sign_extend32(regval, 7) * 4; val 141 drivers/iio/accel/adxl345_core.c *val = div_s64_rem(samp_freq_nhz, NHZ_PER_HZ, val2); val 151 drivers/iio/accel/adxl345_core.c int val, int val2, long mask) val 164 drivers/iio/accel/adxl345_core.c val / 4); val 166 drivers/iio/accel/adxl345_core.c n = div_s64(val * NHZ_PER_HZ + val2, ADXL345_BASE_RATE_NANO_HZ); val 324 drivers/iio/accel/adxl372.c unsigned int size, int val) val 329 drivers/iio/accel/adxl372.c if (val <= array[i]) val 504 drivers/iio/accel/adxl372.c u32 val; val 513 drivers/iio/accel/adxl372.c val = be32_to_cpu(buf); val 515 drivers/iio/accel/adxl372.c *status1 = (val >> 24) & 0x0F; val 516 drivers/iio/accel/adxl372.c *status2 = (val >> 16) & 0x0F; val 521 drivers/iio/accel/adxl372.c *fifo_entries = val & 0x3FF; val 645 drivers/iio/accel/adxl372.c int *val, int *val2, long info) val 661 drivers/iio/accel/adxl372.c *val = sign_extend32(ret >> chan->scan_type.shift, val 665 drivers/iio/accel/adxl372.c *val = 0; val 669 drivers/iio/accel/adxl372.c *val = adxl372_samp_freq_tbl[st->odr]; val 672 drivers/iio/accel/adxl372.c *val = adxl372_bw_freq_tbl[st->bw]; val 681 drivers/iio/accel/adxl372.c int val, int val2, long info) val 690 drivers/iio/accel/adxl372.c val); val 719 drivers/iio/accel/adxl372.c val); val 780 drivers/iio/accel/adxl372.c static int adxl372_set_watermark(struct iio_dev *indio_dev, unsigned int val) val 784 drivers/iio/accel/adxl372.c if (val > ADXL372_FIFO_SIZE) val 785 drivers/iio/accel/adxl372.c val = ADXL372_FIFO_SIZE; val 787 drivers/iio/accel/adxl372.c st->watermark = val; val 164 drivers/iio/accel/bma180.c static int bma180_set_bits(struct bma180_data *data, u8 reg, u8 mask, u8 val) val 167 drivers/iio/accel/bma180.c u8 reg_val = (ret & ~mask) | (val << (ffs(mask) - 1)); val 230 drivers/iio/accel/bma180.c static int bma180_set_bw(struct bma180_data *data, int val) val 238 drivers/iio/accel/bma180.c if (data->part_info->bw_table[i] == val) { val 246 drivers/iio/accel/bma180.c data->bw = val; val 254 drivers/iio/accel/bma180.c static int bma180_set_scale(struct bma180_data *data, int val) val 262 drivers/iio/accel/bma180.c if (data->part_info->scale_table[i] == val) { val 270 drivers/iio/accel/bma180.c data->scale = val; val 463 drivers/iio/accel/bma180.c struct iio_chan_spec const *chan, int *val, int *val2, val 481 drivers/iio/accel/bma180.c *val = sign_extend32(ret >> chan->scan_type.shift, val 485 drivers/iio/accel/bma180.c *val = data->bw; val 490 drivers/iio/accel/bma180.c *val = 0; val 494 drivers/iio/accel/bma180.c *val = 500; val 500 drivers/iio/accel/bma180.c *val = 48; /* 0 LSB @ 24 degree C */ val 508 drivers/iio/accel/bma180.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 515 drivers/iio/accel/bma180.c if (val) val 525 drivers/iio/accel/bma180.c ret = bma180_set_bw(data, val); val 123 drivers/iio/accel/bma220_spi.c int *val, int *val2, long mask) val 134 drivers/iio/accel/bma220_spi.c *val = sign_extend32(ret >> BMA220_DATA_SHIFT, 5); val 141 drivers/iio/accel/bma220_spi.c *val = bma220_scale_table[range_idx][0]; val 151 drivers/iio/accel/bma220_spi.c int val, int val2, long mask) val 161 drivers/iio/accel/bma220_spi.c if (val == bma220_scale_table[i][0] && val 203 drivers/iio/accel/bmc150-accel-core.c int val; val 289 drivers/iio/accel/bmc150-accel-core.c static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, val 296 drivers/iio/accel/bmc150-accel-core.c if (bmc150_accel_samp_freq_table[i].val == val && val 346 drivers/iio/accel/bmc150-accel-core.c static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, val 353 drivers/iio/accel/bmc150-accel-core.c *val = bmc150_accel_samp_freq_table[i].val; val 494 drivers/iio/accel/bmc150-accel-core.c static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) val 500 drivers/iio/accel/bmc150-accel-core.c if (data->chip_info->scale_table[i].scale == val) { val 517 drivers/iio/accel/bmc150-accel-core.c static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) val 531 drivers/iio/accel/bmc150-accel-core.c *val = sign_extend32(value, 7); val 540 drivers/iio/accel/bmc150-accel-core.c int *val) val 562 drivers/iio/accel/bmc150-accel-core.c *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift, val 574 drivers/iio/accel/bmc150-accel-core.c int *val, int *val2, long mask) val 583 drivers/iio/accel/bmc150-accel-core.c return bmc150_accel_get_temp(data, val); val 588 drivers/iio/accel/bmc150-accel-core.c return bmc150_accel_get_axis(data, chan, val); val 594 drivers/iio/accel/bmc150-accel-core.c *val = BMC150_ACCEL_TEMP_CENTER_VAL; val 600 drivers/iio/accel/bmc150-accel-core.c *val = 0; val 625 drivers/iio/accel/bmc150-accel-core.c ret = bmc150_accel_get_bw(data, val, val2); val 635 drivers/iio/accel/bmc150-accel-core.c int val, int val2, long mask) val 643 drivers/iio/accel/bmc150-accel-core.c ret = bmc150_accel_set_bw(data, val, val2); val 647 drivers/iio/accel/bmc150-accel-core.c if (val) val 666 drivers/iio/accel/bmc150-accel-core.c int *val, int *val2) val 673 drivers/iio/accel/bmc150-accel-core.c *val = data->slope_thres; val 676 drivers/iio/accel/bmc150-accel-core.c *val = data->slope_dur; val 690 drivers/iio/accel/bmc150-accel-core.c int val, int val2) val 699 drivers/iio/accel/bmc150-accel-core.c data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; val 702 drivers/iio/accel/bmc150-accel-core.c data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; val 822 drivers/iio/accel/bmc150-accel-core.c static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) val 826 drivers/iio/accel/bmc150-accel-core.c if (val > BMC150_ACCEL_FIFO_LENGTH) val 827 drivers/iio/accel/bmc150-accel-core.c val = BMC150_ACCEL_FIFO_LENGTH; val 830 drivers/iio/accel/bmc150-accel-core.c data->watermark = val; val 867 drivers/iio/accel/bmc150-accel-core.c unsigned int val; val 869 drivers/iio/accel/bmc150-accel-core.c ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val); val 875 drivers/iio/accel/bmc150-accel-core.c count = val & 0x7F; val 1199 drivers/iio/accel/bmc150-accel-core.c unsigned int val; val 1201 drivers/iio/accel/bmc150-accel-core.c ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val); val 1207 drivers/iio/accel/bmc150-accel-core.c if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) val 1212 drivers/iio/accel/bmc150-accel-core.c if (val & BMC150_ACCEL_ANY_MOTION_BIT_X) val 1221 drivers/iio/accel/bmc150-accel-core.c if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y) val 1230 drivers/iio/accel/bmc150-accel-core.c if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z) val 1482 drivers/iio/accel/bmc150-accel-core.c unsigned int val; val 1492 drivers/iio/accel/bmc150-accel-core.c ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val); val 1498 drivers/iio/accel/bmc150-accel-core.c dev_dbg(dev, "Chip Id %x\n", val); val 1500 drivers/iio/accel/bmc150-accel-core.c if (bmc150_accel_chip_info_tbl[i].chip_id == val) { val 1507 drivers/iio/accel/bmc150-accel-core.c dev_err(dev, "Invalid chip %x\n", val); val 72 drivers/iio/accel/cros_ec_accel_legacy.c int *val, int *val2, long mask) val 87 drivers/iio/accel/cros_ec_accel_legacy.c *val = data; val 91 drivers/iio/accel/cros_ec_accel_legacy.c *val = 0; val 97 drivers/iio/accel/cros_ec_accel_legacy.c *val = 0; val 101 drivers/iio/accel/cros_ec_accel_legacy.c ret = cros_ec_sensors_core_read(st, chan, val, val2, val 112 drivers/iio/accel/cros_ec_accel_legacy.c int val, int val2, long mask) val 63 drivers/iio/accel/da280.c int *val, int *val2, long mask) val 77 drivers/iio/accel/da280.c *val = (short)ret >> 2; val 80 drivers/iio/accel/da280.c *val = 0; val 186 drivers/iio/accel/da311.c int *val, int *val2, long mask) val 200 drivers/iio/accel/da311.c *val = (short)ret >> 4; val 203 drivers/iio/accel/da311.c *val = 0; val 68 drivers/iio/accel/dmard06.c int *val, int *val2, long mask) val 83 drivers/iio/accel/dmard06.c *val = sign_extend32(ret, DMARD06_SIGN_BIT); val 86 drivers/iio/accel/dmard06.c *val = *val >> 1; val 93 drivers/iio/accel/dmard06.c *val = *val / 2; val 101 drivers/iio/accel/dmard06.c *val = DMARD06_TEMP_CENTER_VAL; val 109 drivers/iio/accel/dmard06.c *val = 0; val 51 drivers/iio/accel/dmard09.c int *val, int *val2, long mask) val 79 drivers/iio/accel/dmard09.c *val = accel; val 140 drivers/iio/accel/dmard10.c int *val, int *val2, long mask) val 158 drivers/iio/accel/dmard10.c *val = sign_extend32(ret, 12); val 161 drivers/iio/accel/dmard10.c *val = 0; val 132 drivers/iio/accel/hid-sensor-accel-3d.c int *val, int *val2, val 143 drivers/iio/accel/hid-sensor-accel-3d.c *val = 0; val 152 drivers/iio/accel/hid-sensor-accel-3d.c *val = sensor_hub_input_attr_get_raw_value( val 158 drivers/iio/accel/hid-sensor-accel-3d.c *val = 0; val 167 drivers/iio/accel/hid-sensor-accel-3d.c *val = accel_state->scale_pre_decml; val 172 drivers/iio/accel/hid-sensor-accel-3d.c *val = accel_state->value_offset; val 177 drivers/iio/accel/hid-sensor-accel-3d.c &accel_state->common_attributes, val, val2); val 181 drivers/iio/accel/hid-sensor-accel-3d.c &accel_state->common_attributes, val, val2); val 194 drivers/iio/accel/hid-sensor-accel-3d.c int val, val 204 drivers/iio/accel/hid-sensor-accel-3d.c &accel_state->common_attributes, val, val2); val 208 drivers/iio/accel/hid-sensor-accel-3d.c &accel_state->common_attributes, val, val2); val 167 drivers/iio/accel/kxcjk-1013.c int val; val 606 drivers/iio/accel/kxcjk-1013.c const struct kx_odr_map *map, size_t map_size, int val, int val2) val 611 drivers/iio/accel/kxcjk-1013.c if (map[i].val == val && map[i].val2 == val2) val 620 drivers/iio/accel/kxcjk-1013.c int *val, int *val2) val 626 drivers/iio/accel/kxcjk-1013.c *val = map[i].val; val 635 drivers/iio/accel/kxcjk-1013.c static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2) val 648 drivers/iio/accel/kxcjk-1013.c val, val2); val 652 drivers/iio/accel/kxcjk-1013.c val, val2); val 687 drivers/iio/accel/kxcjk-1013.c static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2) val 692 drivers/iio/accel/kxcjk-1013.c data->odr_bits, val, val2); val 696 drivers/iio/accel/kxcjk-1013.c data->odr_bits, val, val2); val 714 drivers/iio/accel/kxcjk-1013.c static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val) val 720 drivers/iio/accel/kxcjk-1013.c if (KXCJK1013_scale_table[i].scale == val) { val 747 drivers/iio/accel/kxcjk-1013.c struct iio_chan_spec const *chan, int *val, val 770 drivers/iio/accel/kxcjk-1013.c *val = sign_extend32(ret >> 4, 11); val 781 drivers/iio/accel/kxcjk-1013.c *val = 0; val 787 drivers/iio/accel/kxcjk-1013.c ret = kxcjk1013_get_odr(data, val, val2); val 797 drivers/iio/accel/kxcjk-1013.c struct iio_chan_spec const *chan, int val, val 806 drivers/iio/accel/kxcjk-1013.c ret = kxcjk1013_set_odr(data, val, val2); val 810 drivers/iio/accel/kxcjk-1013.c if (val) val 829 drivers/iio/accel/kxcjk-1013.c int *val, int *val2) val 836 drivers/iio/accel/kxcjk-1013.c *val = data->wake_thres; val 839 drivers/iio/accel/kxcjk-1013.c *val = data->wake_dur; val 853 drivers/iio/accel/kxcjk-1013.c int val, int val2) val 862 drivers/iio/accel/kxcjk-1013.c data->wake_thres = val; val 865 drivers/iio/accel/kxcjk-1013.c data->wake_dur = val; val 137 drivers/iio/accel/kxsd9.c int val, val 148 drivers/iio/accel/kxsd9.c if (val) val 161 drivers/iio/accel/kxsd9.c int *val, int *val2, long mask) val 180 drivers/iio/accel/kxsd9.c *val = nval; val 185 drivers/iio/accel/kxsd9.c *val = KXSD9_ZERO_G_OFFSET; val 194 drivers/iio/accel/kxsd9.c *val = 0; val 84 drivers/iio/accel/mc3230.c int *val, int *val2, long mask) val 94 drivers/iio/accel/mc3230.c *val = sign_extend32(ret, 7); val 97 drivers/iio/accel/mc3230.c *val = 0; val 108 drivers/iio/accel/mma7455_core.c int *val, int *val2, long mask) val 129 drivers/iio/accel/mma7455_core.c *val = sign_extend32(le16_to_cpu(data), 9); val 134 drivers/iio/accel/mma7455_core.c *val = 0; val 145 drivers/iio/accel/mma7455_core.c *val = 250; val 147 drivers/iio/accel/mma7455_core.c *val = 125; val 157 drivers/iio/accel/mma7455_core.c int val, int val2, long mask) val 164 drivers/iio/accel/mma7455_core.c if (val == 250 && val2 == 0) val 166 drivers/iio/accel/mma7455_core.c else if (val == 125 && val2 == 0) val 176 drivers/iio/accel/mma7455_core.c if (val == 0 && val2 == MMA7455_10BIT_SCALE) val 142 drivers/iio/accel/mma7660.c int *val, int *val2, long mask) val 154 drivers/iio/accel/mma7660.c *val = sign_extend32(ret, 5); val 157 drivers/iio/accel/mma7660.c *val = 0; val 272 drivers/iio/accel/mma8452.c int val, int val2) val 275 drivers/iio/accel/mma8452.c if (val == vals[n][0] && val2 == vals[n][1]) val 410 drivers/iio/accel/mma8452.c u16 val = 0; val 414 drivers/iio/accel/mma8452.c if (val == mma8452_os_ratio[j][i]) val 417 drivers/iio/accel/mma8452.c val = mma8452_os_ratio[j][i]; val 419 drivers/iio/accel/mma8452.c len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); val 435 drivers/iio/accel/mma8452.c int val, int val2) val 439 drivers/iio/accel/mma8452.c val, val2); val 442 drivers/iio/accel/mma8452.c static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) val 445 drivers/iio/accel/mma8452.c ARRAY_SIZE(data->chip_info->mma_scales), val, val2); val 449 drivers/iio/accel/mma8452.c int val, int val2) val 459 drivers/iio/accel/mma8452.c ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); val 484 drivers/iio/accel/mma8452.c int *val, int *val2, long mask) val 503 drivers/iio/accel/mma8452.c *val = sign_extend32(be16_to_cpu( val 510 drivers/iio/accel/mma8452.c *val = data->chip_info->mma_scales[i][0]; val 516 drivers/iio/accel/mma8452.c *val = mma8452_samp_freq[i][0]; val 527 drivers/iio/accel/mma8452.c *val = sign_extend32(ret, 7); val 532 drivers/iio/accel/mma8452.c ret = mma8452_read_hp_filter(data, val, val2); val 536 drivers/iio/accel/mma8452.c *val = 0; val 548 drivers/iio/accel/mma8452.c *val = mma8452_os_ratio[ret][i]; val 591 drivers/iio/accel/mma8452.c static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) val 611 drivers/iio/accel/mma8452.c ret = i2c_smbus_write_byte_data(data->client, reg, val); val 646 drivers/iio/accel/mma8452.c int val; val 648 drivers/iio/accel/mma8452.c val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); val 649 drivers/iio/accel/mma8452.c if (val < 0) val 650 drivers/iio/accel/mma8452.c return val; val 652 drivers/iio/accel/mma8452.c return !(val & MMA8452_FF_MT_CFG_OAE); val 657 drivers/iio/accel/mma8452.c int val; val 663 drivers/iio/accel/mma8452.c val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); val 664 drivers/iio/accel/mma8452.c if (val < 0) val 665 drivers/iio/accel/mma8452.c return val; val 668 drivers/iio/accel/mma8452.c val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); val 669 drivers/iio/accel/mma8452.c val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); val 670 drivers/iio/accel/mma8452.c val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); val 671 drivers/iio/accel/mma8452.c val &= ~MMA8452_FF_MT_CFG_OAE; val 673 drivers/iio/accel/mma8452.c val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); val 674 drivers/iio/accel/mma8452.c val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); val 675 drivers/iio/accel/mma8452.c val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); val 676 drivers/iio/accel/mma8452.c val |= MMA8452_FF_MT_CFG_OAE; val 679 drivers/iio/accel/mma8452.c return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); val 683 drivers/iio/accel/mma8452.c int val, int val2) val 687 drivers/iio/accel/mma8452.c i = mma8452_get_hp_filter_index(data, val, val2); val 704 drivers/iio/accel/mma8452.c int val, int val2, long mask) val 715 drivers/iio/accel/mma8452.c i = mma8452_get_samp_freq_index(data, val, val2); val 729 drivers/iio/accel/mma8452.c i = mma8452_get_scale_index(data, val, val2); val 742 drivers/iio/accel/mma8452.c if (val < -128 || val > 127) { val 749 drivers/iio/accel/mma8452.c val); val 753 drivers/iio/accel/mma8452.c if (val == 0 && val2 == 0) { val 757 drivers/iio/accel/mma8452.c ret = mma8452_set_hp_filter_frequency(data, val, val2); val 770 drivers/iio/accel/mma8452.c if (mma8452_os_ratio[i][ret] == val) { val 820 drivers/iio/accel/mma8452.c int *val, int *val2) val 836 drivers/iio/accel/mma8452.c *val = ret & ev_regs->ev_ths_mask; val 851 drivers/iio/accel/mma8452.c *val = us / USEC_PER_SEC; val 863 drivers/iio/accel/mma8452.c *val = 0; val 866 drivers/iio/accel/mma8452.c ret = mma8452_read_hp_filter(data, val, val2); val 883 drivers/iio/accel/mma8452.c int val, int val2) val 895 drivers/iio/accel/mma8452.c if (val < 0 || val > ev_regs->ev_ths_mask) val 898 drivers/iio/accel/mma8452.c return mma8452_change_config(data, ev_regs->ev_ths, val); val 905 drivers/iio/accel/mma8452.c steps = (val * USEC_PER_SEC + val2) / val 920 drivers/iio/accel/mma8452.c if (val == 0 && val2 == 0) { val 924 drivers/iio/accel/mma8452.c ret = mma8452_set_hp_filter_frequency(data, val, val2); val 972 drivers/iio/accel/mma8452.c int val, ret; val 987 drivers/iio/accel/mma8452.c val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); val 988 drivers/iio/accel/mma8452.c if (val < 0) val 989 drivers/iio/accel/mma8452.c return val; val 993 drivers/iio/accel/mma8452.c val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); val 994 drivers/iio/accel/mma8452.c val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); val 995 drivers/iio/accel/mma8452.c val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); val 996 drivers/iio/accel/mma8452.c val |= MMA8452_FF_MT_CFG_OAE; val 998 drivers/iio/accel/mma8452.c val |= BIT(chan->scan_index + val 1004 drivers/iio/accel/mma8452.c val &= ~BIT(chan->scan_index + val 1008 drivers/iio/accel/mma8452.c val |= ev_regs->ev_cfg_ele; val 1010 drivers/iio/accel/mma8452.c return mma8452_change_config(data, ev_regs->ev_cfg, val); val 54 drivers/iio/accel/mma9551.c int *val) val 95 drivers/iio/accel/mma9551.c *val = 90 * (quadrant + 1) - angle; val 97 drivers/iio/accel/mma9551.c *val = angle + 90 * quadrant; val 108 drivers/iio/accel/mma9551.c int *val, int *val2, long mask) val 118 drivers/iio/accel/mma9551.c ret = mma9551_read_incli_chan(data->client, chan, val); val 129 drivers/iio/accel/mma9551.c chan, val, val2); val 138 drivers/iio/accel/mma9551.c return mma9551_read_accel_scale(val, val2); val 250 drivers/iio/accel/mma9551.c int val, int val2) val 257 drivers/iio/accel/mma9551.c if (val2 != 0 || val < 1 || val > 10) val 264 drivers/iio/accel/mma9551.c val); val 277 drivers/iio/accel/mma9551.c int *val, int *val2) val 292 drivers/iio/accel/mma9551.c *val = tmp & MMA9551_TILT_ANG_THRESH_MASK; val 340 drivers/iio/accel/mma9551.c u8 val; val 374 drivers/iio/accel/mma9551.c reg, &val); val 217 drivers/iio/accel/mma9551_core.c u16 reg, u8 *val) val 220 drivers/iio/accel/mma9551_core.c reg, NULL, 0, val, 1); val 242 drivers/iio/accel/mma9551_core.c u16 reg, u8 val) val 245 drivers/iio/accel/mma9551_core.c &val, 1, NULL, 0); val 267 drivers/iio/accel/mma9551_core.c u16 reg, u8 *val) val 270 drivers/iio/accel/mma9551_core.c reg, NULL, 0, val, 1); val 292 drivers/iio/accel/mma9551_core.c u16 reg, u16 *val) val 299 drivers/iio/accel/mma9551_core.c *val = be16_to_cpu(v); val 323 drivers/iio/accel/mma9551_core.c u16 reg, u16 val) val 325 drivers/iio/accel/mma9551_core.c __be16 v = cpu_to_be16(val); val 350 drivers/iio/accel/mma9551_core.c u16 reg, u16 *val) val 357 drivers/iio/accel/mma9551_core.c *val = be16_to_cpu(v); val 493 drivers/iio/accel/mma9551_core.c u16 reg, u8 mask, u8 val) val 503 drivers/iio/accel/mma9551_core.c tmp |= val & mask; val 723 drivers/iio/accel/mma9551_core.c int *val, int *val2) val 752 drivers/iio/accel/mma9551_core.c *val = raw_accel; val 771 drivers/iio/accel/mma9551_core.c int mma9551_read_accel_scale(int *val, int *val2) val 773 drivers/iio/accel/mma9551_core.c *val = 0; val 42 drivers/iio/accel/mma9551_core.h u16 reg, u8 *val); val 44 drivers/iio/accel/mma9551_core.h u16 reg, u8 val); val 46 drivers/iio/accel/mma9551_core.h u16 reg, u8 *val); val 48 drivers/iio/accel/mma9551_core.h u16 reg, u16 *val); val 50 drivers/iio/accel/mma9551_core.h u16 reg, u16 val); val 52 drivers/iio/accel/mma9551_core.h u16 reg, u16 *val); val 60 drivers/iio/accel/mma9551_core.h u16 reg, u8 mask, u8 val); val 69 drivers/iio/accel/mma9551_core.h int *val, int *val2); val 70 drivers/iio/accel/mma9551_core.h int mma9551_read_accel_scale(int *val, int *val2); val 194 drivers/iio/accel/mma9553.c static u8 mma9553_get_bits(u16 val, u16 mask) val 196 drivers/iio/accel/mma9553.c return (val & mask) >> (ffs(mask) - 1); val 199 drivers/iio/accel/mma9553.c static u16 mma9553_set_bits(u16 current_val, u16 val, u16 mask) val 201 drivers/iio/accel/mma9553.c return (current_val & ~mask) | (val << (ffs(mask) - 1)); val 264 drivers/iio/accel/mma9553.c u16 *p_reg_val, u16 val, u16 mask) val 270 drivers/iio/accel/mma9553.c if (val == mma9553_get_bits(reg_val, mask)) val 273 drivers/iio/accel/mma9553.c reg_val = mma9553_set_bits(reg_val, val, mask); val 464 drivers/iio/accel/mma9553.c int *val, int *val2, long mask) val 480 drivers/iio/accel/mma9553.c *val = tmp; val 488 drivers/iio/accel/mma9553.c *val = tmp; val 506 drivers/iio/accel/mma9553.c *val = 100; val 508 drivers/iio/accel/mma9553.c *val = 0; val 523 drivers/iio/accel/mma9553.c *val = tmp; val 531 drivers/iio/accel/mma9553.c *val = tmp; val 536 drivers/iio/accel/mma9553.c chan, val, val2); val 547 drivers/iio/accel/mma9553.c *val = 0; val 551 drivers/iio/accel/mma9553.c *val = 4184; val 554 drivers/iio/accel/mma9553.c return mma9551_read_accel_scale(val, val2); val 559 drivers/iio/accel/mma9553.c *val = data->stepcnt_enabled; val 564 drivers/iio/accel/mma9553.c *val = tmp / 100; /* cm to m */ val 568 drivers/iio/accel/mma9553.c *val = mma9553_get_bits(data->conf.height_weight, val 574 drivers/iio/accel/mma9553.c *val = mma9553_get_bits(data->conf.filter, val 583 drivers/iio/accel/mma9553.c *val = mma9553_get_bits(data->conf.filter, val 594 drivers/iio/accel/mma9553.c *val = mma9553_get_bits(data->conf.speed_step, val 607 drivers/iio/accel/mma9553.c int val, int val2, long mask) val 614 drivers/iio/accel/mma9553.c if (data->stepcnt_enabled == !!val) val 617 drivers/iio/accel/mma9553.c ret = mma9551_set_power_state(data->client, val); val 622 drivers/iio/accel/mma9553.c data->stepcnt_enabled = val; val 627 drivers/iio/accel/mma9553.c tmp = val * 100 + val2 / 10000; val 638 drivers/iio/accel/mma9553.c if (val < 0 || val > 255) val 644 drivers/iio/accel/mma9553.c val, MMA9553_MASK_CONF_WEIGHT); val 654 drivers/iio/accel/mma9553.c if (val < 0) val 656 drivers/iio/accel/mma9553.c if (val > 6) val 657 drivers/iio/accel/mma9553.c val = 6; val 660 drivers/iio/accel/mma9553.c &data->conf.filter, val, val 670 drivers/iio/accel/mma9553.c if (val < 0 || val > 127) val 674 drivers/iio/accel/mma9553.c &data->conf.filter, val, val 691 drivers/iio/accel/mma9553.c if (val < 2) val 693 drivers/iio/accel/mma9553.c if (val > 5) val 694 drivers/iio/accel/mma9553.c val = 5; val 698 drivers/iio/accel/mma9553.c &data->conf.speed_step, val, val 771 drivers/iio/accel/mma9553.c int *val, int *val2) val 780 drivers/iio/accel/mma9553.c *val = mma9553_get_bits(data->conf.speed_step, val 788 drivers/iio/accel/mma9553.c *val = 50; val 796 drivers/iio/accel/mma9553.c *val = MMA9553_ACTIVITY_THD_TO_SEC(data->conf.actthd); val 811 drivers/iio/accel/mma9553.c int val, int val2) val 820 drivers/iio/accel/mma9553.c if (val < 0 || val > 255) val 825 drivers/iio/accel/mma9553.c &data->conf.speed_step, val, val 835 drivers/iio/accel/mma9553.c if (val < 0 || val > MMA9553_ACTIVITY_THD_TO_SEC( val 842 drivers/iio/accel/mma9553.c (val), MMA9553_MASK_CONF_WORD); val 182 drivers/iio/accel/mxc4005.c static int mxc4005_set_scale(struct mxc4005_data *data, int val) val 189 drivers/iio/accel/mxc4005.c if (mxc4005_scale_table[i].scale == val) { val 207 drivers/iio/accel/mxc4005.c int *val, int *val2, long mask) val 222 drivers/iio/accel/mxc4005.c *val = sign_extend32(ret >> chan->scan_type.shift, val 233 drivers/iio/accel/mxc4005.c *val = 0; val 243 drivers/iio/accel/mxc4005.c int val, int val2, long mask) val 249 drivers/iio/accel/mxc4005.c if (val != 0) val 51 drivers/iio/accel/mxc6255.c int *val, int *val2, long mask) val 66 drivers/iio/accel/mxc6255.c *val = sign_extend32(reg, 7); val 69 drivers/iio/accel/mxc6255.c *val = 0; val 277 drivers/iio/accel/sca3000.c static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val) val 280 drivers/iio/accel/sca3000.c st->tx[1] = val; val 366 drivers/iio/accel/sca3000.c uint8_t val) val 385 drivers/iio/accel/sca3000.c ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val); val 598 drivers/iio/accel/sca3000.c static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val) val 602 drivers/iio/accel/sca3000.c ret = __sca3000_get_base_freq(st, st->info, val); val 610 drivers/iio/accel/sca3000.c if (*val > 0) { val 614 drivers/iio/accel/sca3000.c *val /= 2; val 617 drivers/iio/accel/sca3000.c *val /= 4; val 632 drivers/iio/accel/sca3000.c static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val) val 646 drivers/iio/accel/sca3000.c if (val == base_freq / 2) val 648 drivers/iio/accel/sca3000.c if (val == base_freq / 4) val 650 drivers/iio/accel/sca3000.c else if (val != base_freq) val 657 drivers/iio/accel/sca3000.c static int sca3000_read_3db_freq(struct sca3000_state *st, int *val) val 669 drivers/iio/accel/sca3000.c *val = st->info->measurement_mode_3db_freq; val 674 drivers/iio/accel/sca3000.c *val = st->info->option_mode_1_3db_freq; val 677 drivers/iio/accel/sca3000.c *val = st->info->option_mode_2_3db_freq; val 684 drivers/iio/accel/sca3000.c static int sca3000_write_3db_freq(struct sca3000_state *st, int val) val 689 drivers/iio/accel/sca3000.c if (val == st->info->measurement_mode_3db_freq) val 692 drivers/iio/accel/sca3000.c (val == st->info->option_mode_1_3db_freq)) val 695 drivers/iio/accel/sca3000.c (val == st->info->option_mode_2_3db_freq)) val 711 drivers/iio/accel/sca3000.c int *val, val 733 drivers/iio/accel/sca3000.c *val = (be16_to_cpup((__be16 *)st->rx) >> 3) & 0x1FFF; val 734 drivers/iio/accel/sca3000.c *val = ((*val) << (sizeof(*val) * 8 - 13)) >> val 735 drivers/iio/accel/sca3000.c (sizeof(*val) * 8 - 13); val 745 drivers/iio/accel/sca3000.c *val = ((st->rx[0] & 0x3F) << 3) | val 751 drivers/iio/accel/sca3000.c *val = 0; val 758 drivers/iio/accel/sca3000.c *val = -214; val 763 drivers/iio/accel/sca3000.c ret = sca3000_read_raw_samp_freq(st, val); val 768 drivers/iio/accel/sca3000.c ret = sca3000_read_3db_freq(st, val); val 778 drivers/iio/accel/sca3000.c int val, int val2, long mask) val 788 drivers/iio/accel/sca3000.c ret = sca3000_write_raw_samp_freq(st, val); val 795 drivers/iio/accel/sca3000.c ret = sca3000_write_3db_freq(st, val); val 822 drivers/iio/accel/sca3000.c int len = 0, ret, val; val 826 drivers/iio/accel/sca3000.c val = st->rx[0]; val 831 drivers/iio/accel/sca3000.c switch (val & SCA3000_REG_MODE_MODE_MASK) { val 870 drivers/iio/accel/sca3000.c int *val, int *val2) val 884 drivers/iio/accel/sca3000.c *val = 0; val 888 drivers/iio/accel/sca3000.c *val += st->info->mot_det_mult_y[i]; val 892 drivers/iio/accel/sca3000.c *val += st->info->mot_det_mult_xz[i]; val 896 drivers/iio/accel/sca3000.c *val = 0; val 922 drivers/iio/accel/sca3000.c int val, int val2) val 932 drivers/iio/accel/sca3000.c if (val >= st->info->mot_det_mult_y[--i]) { val 934 drivers/iio/accel/sca3000.c val -= st->info->mot_det_mult_y[i]; val 939 drivers/iio/accel/sca3000.c if (val >= st->info->mot_det_mult_xz[--i]) { val 941 drivers/iio/accel/sca3000.c val -= st->info->mot_det_mult_xz[i]; val 995 drivers/iio/accel/sca3000.c static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev) val 1002 drivers/iio/accel/sca3000.c if (val & SCA3000_REG_INT_STATUS_HALF) { val 1047 drivers/iio/accel/sca3000.c int ret, val; val 1056 drivers/iio/accel/sca3000.c val = st->rx[0]; val 1061 drivers/iio/accel/sca3000.c sca3000_ring_int_process(val, indio_dev); val 1063 drivers/iio/accel/sca3000.c if (val & SCA3000_INT_STATUS_FREE_FALL) val 1072 drivers/iio/accel/sca3000.c if (val & SCA3000_INT_STATUS_Y_TRIGGER) val 1081 drivers/iio/accel/sca3000.c if (val & SCA3000_INT_STATUS_X_TRIGGER) val 1090 drivers/iio/accel/sca3000.c if (val & SCA3000_INT_STATUS_Z_TRIGGER) val 28 drivers/iio/accel/ssp_accel_sensor.c struct iio_chan_spec const *chan, int *val, val 37 drivers/iio/accel/ssp_accel_sensor.c ssp_convert_to_freq(t, val, val2); val 47 drivers/iio/accel/ssp_accel_sensor.c struct iio_chan_spec const *chan, int val, val 55 drivers/iio/accel/ssp_accel_sensor.c ret = ssp_convert_to_time(val, val2); val 911 drivers/iio/accel/st_accel_core.c struct iio_chan_spec const *ch, int *val, val 919 drivers/iio/accel/st_accel_core.c err = st_sensors_read_info_raw(indio_dev, ch, val); val 925 drivers/iio/accel/st_accel_core.c *val = adata->current_fullscale->gain / 1000000; val 929 drivers/iio/accel/st_accel_core.c *val = adata->odr; val 940 drivers/iio/accel/st_accel_core.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 948 drivers/iio/accel/st_accel_core.c gain = val * 1000000 + val2; val 956 drivers/iio/accel/st_accel_core.c err = st_sensors_set_odr(indio_dev, val); val 1024 drivers/iio/accel/st_accel_core.c unsigned int val; val 1068 drivers/iio/accel/st_accel_core.c val = elements[i].integer.value; val 1069 drivers/iio/accel/st_accel_core.c if (val > 2) val 1076 drivers/iio/accel/st_accel_core.c final_ont[0][i] = default_ont[0][val]; val 1077 drivers/iio/accel/st_accel_core.c final_ont[1][i] = default_ont[1][val]; val 1078 drivers/iio/accel/st_accel_core.c final_ont[2][i] = default_ont[2][val]; val 1091 drivers/iio/accel/st_accel_core.c val = elements[i].integer.value; val 1092 drivers/iio/accel/st_accel_core.c if (val != 0 && val != 1) val 1094 drivers/iio/accel/st_accel_core.c if (!val) val 67 drivers/iio/accel/stk8312.c int val; val 333 drivers/iio/accel/stk8312.c int *val, int *val2, long mask) val 355 drivers/iio/accel/stk8312.c *val = sign_extend32(ret, 7); val 363 drivers/iio/accel/stk8312.c *val = stk8312_scale_table[data->range - 1][0]; val 367 drivers/iio/accel/stk8312.c *val = stk8312_samp_freq_table[data->sample_rate_idx].val; val 377 drivers/iio/accel/stk8312.c int val, int val2, long mask) val 387 drivers/iio/accel/stk8312.c if (val == stk8312_scale_table[i][0] && val 402 drivers/iio/accel/stk8312.c if (val == stk8312_samp_freq_table[i].val && val 210 drivers/iio/accel/stk8ba50.c int *val, int *val2, long mask) val 231 drivers/iio/accel/stk8ba50.c *val = sign_extend32(ret >> STK8BA50_DATA_SHIFT, 9); val 236 drivers/iio/accel/stk8ba50.c *val = 0; val 240 drivers/iio/accel/stk8ba50.c *val = stk8ba50_samp_freq_table val 251 drivers/iio/accel/stk8ba50.c int val, int val2, long mask) val 260 drivers/iio/accel/stk8ba50.c if (val != 0) val 283 drivers/iio/accel/stk8ba50.c if (val == stk8ba50_samp_freq_table[i].samp_freq) { val 160 drivers/iio/adc/ad7124.c unsigned int size, int val) val 169 drivers/iio/adc/ad7124.c diff_new = abs(val - array[i]); val 182 drivers/iio/adc/ad7124.c unsigned int val, val 193 drivers/iio/adc/ad7124.c readval |= val; val 212 drivers/iio/adc/ad7124.c unsigned int val; val 214 drivers/iio/adc/ad7124.c val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) | val 217 drivers/iio/adc/ad7124.c return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val); val 284 drivers/iio/adc/ad7124.c int *val, int *val2, long info) val 291 drivers/iio/adc/ad7124.c ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); val 306 drivers/iio/adc/ad7124.c *val = st->channel_config[chan->address].vref_mv; val 315 drivers/iio/adc/ad7124.c *val = -(1 << (chan->scan_type.realbits - 1)); val 317 drivers/iio/adc/ad7124.c *val = 0; val 321 drivers/iio/adc/ad7124.c *val = st->channel_config[chan->address].odr; val 331 drivers/iio/adc/ad7124.c int val, int val2, long info) val 341 drivers/iio/adc/ad7124.c return ad7124_set_channel_odr(st, chan->address, val); val 343 drivers/iio/adc/ad7124.c if (val != 0) val 513 drivers/iio/adc/ad7124.c unsigned int val, fclk, power_mode; val 538 drivers/iio/adc/ad7124.c val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i); val 539 drivers/iio/adc/ad7124.c ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val); val 550 drivers/iio/adc/ad7124.c val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) | val 553 drivers/iio/adc/ad7124.c ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val); val 134 drivers/iio/adc/ad7266.c static int ad7266_read_single(struct ad7266_state *st, int *val, val 142 drivers/iio/adc/ad7266.c *val = be16_to_cpu(st->data.sample[address % 2]); val 148 drivers/iio/adc/ad7266.c struct iio_chan_spec const *chan, int *val, int *val2, long m) val 159 drivers/iio/adc/ad7266.c ret = ad7266_read_single(st, val, chan->address); val 162 drivers/iio/adc/ad7266.c *val = (*val >> 2) & 0xfff; val 164 drivers/iio/adc/ad7266.c *val = sign_extend32(*val, 11); val 174 drivers/iio/adc/ad7266.c *val = scale_mv; val 180 drivers/iio/adc/ad7266.c *val = 2048; val 182 drivers/iio/adc/ad7266.c *val = 0; val 206 drivers/iio/adc/ad7291.c int *val, int *val2) val 218 drivers/iio/adc/ad7291.c *val = uval & AD7291_VALUE_MASK; val 221 drivers/iio/adc/ad7291.c *val = sign_extend32(uval, 11); val 231 drivers/iio/adc/ad7291.c int val, int val2) val 236 drivers/iio/adc/ad7291.c if (val > AD7291_VALUE_MASK || val < 0) val 239 drivers/iio/adc/ad7291.c if (val > 2047 || val < -2048) val 244 drivers/iio/adc/ad7291.c val); val 322 drivers/iio/adc/ad7291.c int *val, val 355 drivers/iio/adc/ad7291.c *val = ret & AD7291_VALUE_MASK; val 364 drivers/iio/adc/ad7291.c *val = sign_extend32(ret, 11); val 374 drivers/iio/adc/ad7291.c *val = sign_extend32(ret, 11); val 385 drivers/iio/adc/ad7291.c *val = vref / 1000; val 387 drivers/iio/adc/ad7291.c *val = 2500; val 397 drivers/iio/adc/ad7291.c *val = 250; val 186 drivers/iio/adc/ad7298.c static int ad7298_scan_temp(struct ad7298_state *st, int *val) val 210 drivers/iio/adc/ad7298.c *val = sign_extend32(be16_to_cpu(buf), 11); val 232 drivers/iio/adc/ad7298.c int *val, val 246 drivers/iio/adc/ad7298.c ret = ad7298_scan_temp(st, val); val 256 drivers/iio/adc/ad7298.c *val = ret & GENMASK(chan->scan_type.realbits - 1, 0); val 262 drivers/iio/adc/ad7298.c *val = ad7298_get_ref_voltage(st); val 266 drivers/iio/adc/ad7298.c *val = ad7298_get_ref_voltage(st); val 273 drivers/iio/adc/ad7298.c *val = 1093 - 2732500 / ad7298_get_ref_voltage(st); val 105 drivers/iio/adc/ad7476.c int *val, val 123 drivers/iio/adc/ad7476.c *val = (ret >> st->chip_info->channel[0].scan_type.shift) & val 134 drivers/iio/adc/ad7476.c *val = scale_uv / 1000; val 167 drivers/iio/adc/ad7606.c int *val, val 185 drivers/iio/adc/ad7606.c *val = (short)ret; val 190 drivers/iio/adc/ad7606.c *val = 0; val 194 drivers/iio/adc/ad7606.c *val = st->oversampling; val 227 drivers/iio/adc/ad7606.c static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val) val 231 drivers/iio/adc/ad7606.c gpiod_set_value(st->gpio_range, val); val 236 drivers/iio/adc/ad7606.c static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val) val 241 drivers/iio/adc/ad7606.c values[0] = val; val 255 drivers/iio/adc/ad7606.c int val, val 280 drivers/iio/adc/ad7606.c i = find_closest(val, st->oversampling_avail, val 105 drivers/iio/adc/ad7606.h int (*write_scale)(struct iio_dev *indio_dev, int ch, int val); val 106 drivers/iio/adc/ad7606.h int (*write_os)(struct iio_dev *indio_dev, int val); val 144 drivers/iio/adc/ad7606.h unsigned int val); val 148 drivers/iio/adc/ad7606.h unsigned int val); val 149 drivers/iio/adc/ad7606_spi.c unsigned int val) val 154 drivers/iio/adc/ad7606_spi.c (val & 0x1FF)); val 162 drivers/iio/adc/ad7606_spi.c unsigned int val) val 171 drivers/iio/adc/ad7606_spi.c readval |= val; val 176 drivers/iio/adc/ad7606_spi.c static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) val 199 drivers/iio/adc/ad7606_spi.c mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); val 204 drivers/iio/adc/ad7606_spi.c static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) val 209 drivers/iio/adc/ad7606_spi.c AD7616_OS_MASK, val << 2); val 212 drivers/iio/adc/ad7606_spi.c static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) val 219 drivers/iio/adc/ad7606_spi.c AD7606_RANGE_CH_MODE(ch, val)); val 222 drivers/iio/adc/ad7606_spi.c static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val) val 226 drivers/iio/adc/ad7606_spi.c return ad7606_spi_reg_write(st, AD7606_OS_MODE, val); val 129 drivers/iio/adc/ad7766.c const struct iio_chan_spec *chan, int *val, int *val2, long info) val 140 drivers/iio/adc/ad7766.c *val = scale_uv / 1000; val 144 drivers/iio/adc/ad7766.c *val = clk_get_rate(ad7766->mclk) / val 193 drivers/iio/adc/ad7768-1.c unsigned int val) val 196 drivers/iio/adc/ad7768-1.c st->data.d8[1] = val & 0xFF; val 356 drivers/iio/adc/ad7768-1.c int *val, int *val2, long info) val 369 drivers/iio/adc/ad7768-1.c *val = ret; val 382 drivers/iio/adc/ad7768-1.c *val = (scale_uv * 2) / 1000; val 388 drivers/iio/adc/ad7768-1.c *val = st->samp_freq; val 398 drivers/iio/adc/ad7768-1.c int val, int val2, long info) val 404 drivers/iio/adc/ad7768-1.c return ad7768_set_freq(st, val); val 88 drivers/iio/adc/ad7780.c unsigned int val; val 93 drivers/iio/adc/ad7780.c val = 1; val 96 drivers/iio/adc/ad7780.c val = 0; val 100 drivers/iio/adc/ad7780.c gpiod_set_value(st->powerdown_gpio, val); val 107 drivers/iio/adc/ad7780.c int *val, val 116 drivers/iio/adc/ad7780.c return ad_sigma_delta_single_conversion(indio_dev, chan, val); val 122 drivers/iio/adc/ad7780.c *val = voltage_uv * st->gain; val 127 drivers/iio/adc/ad7780.c *val = -(1 << (chan->scan_type.realbits - 1)); val 130 drivers/iio/adc/ad7780.c *val = st->odr; val 141 drivers/iio/adc/ad7780.c int val, val 155 drivers/iio/adc/ad7780.c if (val != 0) val 170 drivers/iio/adc/ad7780.c if (1000*val + val2/1000 < AD7780_FILTER_MIDPOINT) val 171 drivers/iio/adc/ad7780.c val = 0; val 173 drivers/iio/adc/ad7780.c val = 1; val 174 drivers/iio/adc/ad7780.c st->odr = ad778x_odr_avail[val]; val 175 drivers/iio/adc/ad7780.c gpiod_set_value(st->filter_gpio, val); val 211 drivers/iio/adc/ad7791.c const struct iio_chan_spec *chan, int *val, int *val2, long info) val 219 drivers/iio/adc/ad7791.c return ad_sigma_delta_single_conversion(indio_dev, chan, val); val 226 drivers/iio/adc/ad7791.c *val = 0; val 228 drivers/iio/adc/ad7791.c *val = -(1 << (chan->scan_type.realbits - 1)); val 237 drivers/iio/adc/ad7791.c *val = 1170 * 5; val 245 drivers/iio/adc/ad7791.c *val = voltage_uv / 1000; val 255 drivers/iio/adc/ad7791.c *val = ad7791_sample_freq_avail[rate][0]; val 264 drivers/iio/adc/ad7791.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 276 drivers/iio/adc/ad7791.c if (ad7791_sample_freq_avail[i][0] == val && val 397 drivers/iio/adc/ad7793.c int *val, val 408 drivers/iio/adc/ad7793.c ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); val 418 drivers/iio/adc/ad7793.c *val = st-> val 436 drivers/iio/adc/ad7793.c *val = 0; val 441 drivers/iio/adc/ad7793.c *val = -(1 << (chan->scan_type.realbits - 1)); val 443 drivers/iio/adc/ad7793.c *val = 0; val 453 drivers/iio/adc/ad7793.c *val -= offset; val 457 drivers/iio/adc/ad7793.c *val = st->chip_info val 466 drivers/iio/adc/ad7793.c int val, val 498 drivers/iio/adc/ad7793.c if (!val) { val 504 drivers/iio/adc/ad7793.c if (val == st->chip_info->sample_freq_avail[i]) val 149 drivers/iio/adc/ad7887.c int *val, val 166 drivers/iio/adc/ad7887.c *val = ret >> chan->scan_type.shift; val 167 drivers/iio/adc/ad7887.c *val &= GENMASK(chan->scan_type.realbits - 1, 0); val 171 drivers/iio/adc/ad7887.c *val = regulator_get_voltage(st->reg); val 172 drivers/iio/adc/ad7887.c if (*val < 0) val 173 drivers/iio/adc/ad7887.c return *val; val 174 drivers/iio/adc/ad7887.c *val /= 1000; val 176 drivers/iio/adc/ad7887.c *val = st->chip_info->int_vref_mv; val 51 drivers/iio/adc/ad7923.c #define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1)) val 226 drivers/iio/adc/ad7923.c int *val, val 245 drivers/iio/adc/ad7923.c *val = EXTRACT(ret, 0, 12); val 254 drivers/iio/adc/ad7923.c *val = ret; val 60 drivers/iio/adc/ad7949.c static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val, val 75 drivers/iio/adc/ad7949.c ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask); val 88 drivers/iio/adc/ad7949.c static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, val 135 drivers/iio/adc/ad7949.c *val = ad7949_adc->buffer & mask; val 161 drivers/iio/adc/ad7949.c int *val, int *val2, long mask) val 166 drivers/iio/adc/ad7949.c if (!val) val 172 drivers/iio/adc/ad7949.c ret = ad7949_spi_read_channel(ad7949_adc, val, chan->channel); val 185 drivers/iio/adc/ad7949.c *val = ret / 5000; val 216 drivers/iio/adc/ad7949.c int val; val 226 drivers/iio/adc/ad7949.c ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel); val 227 drivers/iio/adc/ad7949.c ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel); val 135 drivers/iio/adc/ad799x.c static int ad799x_write_config(struct ad799x_state *st, u16 val) val 141 drivers/iio/adc/ad799x.c val); val 146 drivers/iio/adc/ad799x.c val); val 149 drivers/iio/adc/ad799x.c st->config = val; val 272 drivers/iio/adc/ad799x.c int *val, val 289 drivers/iio/adc/ad799x.c *val = (ret >> chan->scan_type.shift) & val 296 drivers/iio/adc/ad799x.c *val = ret / 1000; val 334 drivers/iio/adc/ad799x.c long val; val 337 drivers/iio/adc/ad799x.c ret = kstrtol(buf, 10, &val); val 349 drivers/iio/adc/ad799x.c if (val == ad7998_frequencies[i]) val 436 drivers/iio/adc/ad799x.c int val, int val2) val 441 drivers/iio/adc/ad799x.c if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0)) val 447 drivers/iio/adc/ad799x.c val << chan->scan_type.shift); val 458 drivers/iio/adc/ad799x.c int *val, int *val2) val 469 drivers/iio/adc/ad799x.c *val = (ret >> chan->scan_type.shift) & val 58 drivers/iio/adc/ad_sigma_delta.c unsigned int size, unsigned int val) val 73 drivers/iio/adc/ad_sigma_delta.c data[1] = val >> 16; val 74 drivers/iio/adc/ad_sigma_delta.c data[2] = val >> 8; val 75 drivers/iio/adc/ad_sigma_delta.c data[3] = val; val 78 drivers/iio/adc/ad_sigma_delta.c put_unaligned_be16(val, &data[1]); val 81 drivers/iio/adc/ad_sigma_delta.c data[1] = val; val 102 drivers/iio/adc/ad_sigma_delta.c unsigned int reg, unsigned int size, uint8_t *val) val 111 drivers/iio/adc/ad_sigma_delta.c .rx_buf = val, val 147 drivers/iio/adc/ad_sigma_delta.c unsigned int reg, unsigned int size, unsigned int *val) val 157 drivers/iio/adc/ad_sigma_delta.c *val = get_unaligned_be32(sigma_delta->data); val 160 drivers/iio/adc/ad_sigma_delta.c *val = (sigma_delta->data[0] << 16) | val 165 drivers/iio/adc/ad_sigma_delta.c *val = get_unaligned_be16(sigma_delta->data); val 168 drivers/iio/adc/ad_sigma_delta.c *val = sigma_delta->data[0]; val 279 drivers/iio/adc/ad_sigma_delta.c const struct iio_chan_spec *chan, int *val) val 335 drivers/iio/adc/ad_sigma_delta.c *val = sample; val 92 drivers/iio/adc/aspeed_adc.c int *val, int *val2, long mask) val 100 drivers/iio/adc/aspeed_adc.c *val = readw(data->base + chan->address); val 104 drivers/iio/adc/aspeed_adc.c *val = model_data->vref_voltage; val 109 drivers/iio/adc/aspeed_adc.c *val = clk_get_rate(data->clk_scaler->clk) / val 120 drivers/iio/adc/aspeed_adc.c int val, int val2, long mask) val 128 drivers/iio/adc/aspeed_adc.c if (val < model_data->min_sampling_rate || val 129 drivers/iio/adc/aspeed_adc.c val > model_data->max_sampling_rate) val 133 drivers/iio/adc/aspeed_adc.c val * ASPEED_CLOCKS_PER_SAMPLE); val 331 drivers/iio/adc/at91-sama5d2_adc.c #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) val 519 drivers/iio/adc/at91-sama5d2_adc.c static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) val 526 drivers/iio/adc/at91-sama5d2_adc.c *val <<= 2; val 532 drivers/iio/adc/at91-sama5d2_adc.c *val <<= 1; val 541 drivers/iio/adc/at91-sama5d2_adc.c int i = 0, val; val 553 drivers/iio/adc/at91-sama5d2_adc.c val = buf_u16[i]; val 554 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_adjust_val_osr(st, &val); val 555 drivers/iio/adc/at91-sama5d2_adc.c buf_u16[i] = val; val 616 drivers/iio/adc/at91-sama5d2_adc.c u32 val; val 625 drivers/iio/adc/at91-sama5d2_adc.c val = at91_adc_readl(st, reg); val 626 drivers/iio/adc/at91-sama5d2_adc.c if (!val) val 629 drivers/iio/adc/at91-sama5d2_adc.c pos = val & AT91_SAMA5D2_XYZ_MASK; val 631 drivers/iio/adc/at91-sama5d2_adc.c scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; val 654 drivers/iio/adc/at91-sama5d2_adc.c u32 val; val 661 drivers/iio/adc/at91-sama5d2_adc.c val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); val 662 drivers/iio/adc/at91-sama5d2_adc.c z1 = val & AT91_SAMA5D2_XYZ_MASK; val 663 drivers/iio/adc/at91-sama5d2_adc.c z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; val 680 drivers/iio/adc/at91-sama5d2_adc.c static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val) val 682 drivers/iio/adc/at91-sama5d2_adc.c *val = 0; val 686 drivers/iio/adc/at91-sama5d2_adc.c *val = at91_adc_touch_x_pos(st); val 688 drivers/iio/adc/at91-sama5d2_adc.c *val = at91_adc_touch_y_pos(st); val 695 drivers/iio/adc/at91-sama5d2_adc.c static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) val 697 drivers/iio/adc/at91-sama5d2_adc.c *val = 0; val 701 drivers/iio/adc/at91-sama5d2_adc.c *val = at91_adc_touch_pressure(st); val 1016 drivers/iio/adc/at91-sama5d2_adc.c int val; val 1037 drivers/iio/adc/at91-sama5d2_adc.c val = at91_adc_readl(st, chan->address); val 1038 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_adjust_val_osr(st, &val); val 1039 drivers/iio/adc/at91-sama5d2_adc.c st->buffer[i] = val; val 1188 drivers/iio/adc/at91-sama5d2_adc.c u16 val; val 1197 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_read_position(st, chan->channel, &val); val 1199 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_read_pressure(st, chan->channel, &val); val 1202 drivers/iio/adc/at91-sama5d2_adc.c st->buffer[i] = val; val 1302 drivers/iio/adc/at91-sama5d2_adc.c struct iio_chan_spec const *chan, int *val) val 1321 drivers/iio/adc/at91-sama5d2_adc.c *val = tmp_val; val 1325 drivers/iio/adc/at91-sama5d2_adc.c return at91_adc_adjust_val_osr(st, val); val 1335 drivers/iio/adc/at91-sama5d2_adc.c *val = tmp_val; val 1339 drivers/iio/adc/at91-sama5d2_adc.c return at91_adc_adjust_val_osr(st, val); val 1367 drivers/iio/adc/at91-sama5d2_adc.c *val = st->conversion_value; val 1368 drivers/iio/adc/at91-sama5d2_adc.c ret = at91_adc_adjust_val_osr(st, val); val 1370 drivers/iio/adc/at91-sama5d2_adc.c *val = sign_extend32(*val, 11); val 1388 drivers/iio/adc/at91-sama5d2_adc.c int *val, int *val2, long mask) val 1394 drivers/iio/adc/at91-sama5d2_adc.c return at91_adc_read_info_raw(indio_dev, chan, val); val 1396 drivers/iio/adc/at91-sama5d2_adc.c *val = st->vref_uv / 1000; val 1398 drivers/iio/adc/at91-sama5d2_adc.c *val *= 2; val 1403 drivers/iio/adc/at91-sama5d2_adc.c *val = at91_adc_get_sample_freq(st); val 1407 drivers/iio/adc/at91-sama5d2_adc.c *val = st->oversampling_ratio; val 1417 drivers/iio/adc/at91-sama5d2_adc.c int val, int val2, long mask) val 1423 drivers/iio/adc/at91-sama5d2_adc.c if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) && val 1424 drivers/iio/adc/at91-sama5d2_adc.c (val != AT91_OSR_16SAMPLES)) val 1427 drivers/iio/adc/at91-sama5d2_adc.c if (val == st->oversampling_ratio) val 1429 drivers/iio/adc/at91-sama5d2_adc.c st->oversampling_ratio = val; val 1434 drivers/iio/adc/at91-sama5d2_adc.c if (val < st->soc_info.min_sample_rate || val 1435 drivers/iio/adc/at91-sama5d2_adc.c val > st->soc_info.max_sample_rate) val 1438 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_setup_samp_freq(st, val); val 1529 drivers/iio/adc/at91-sama5d2_adc.c static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) val 1533 drivers/iio/adc/at91-sama5d2_adc.c if (val > AT91_HWFIFO_MAX_SIZE) val 1541 drivers/iio/adc/at91-sama5d2_adc.c dev_dbg(&indio_dev->dev, "new watermark is %u\n", val); val 1542 drivers/iio/adc/at91-sama5d2_adc.c st->dma_st.watermark = val; val 1550 drivers/iio/adc/at91-sama5d2_adc.c if (val == 1) val 1552 drivers/iio/adc/at91-sama5d2_adc.c else if (val > 1) val 142 drivers/iio/adc/at91_adc.c #define at91_adc_writel(st, reg, val) \ val 143 drivers/iio/adc/at91_adc.c (writel_relaxed(val, st->reg_base + reg)) val 688 drivers/iio/adc/at91_adc.c int *val, int *val2, long mask) val 716 drivers/iio/adc/at91_adc.c *val = st->last_value; val 731 drivers/iio/adc/at91_adc.c *val = st->vref_mv; val 228 drivers/iio/adc/axp20x_adc.c struct iio_chan_spec const *chan, int *val) val 243 drivers/iio/adc/axp20x_adc.c *val = axp20x_read_variable_width(info->regmap, chan->address, size); val 244 drivers/iio/adc/axp20x_adc.c if (*val < 0) val 245 drivers/iio/adc/axp20x_adc.c return *val; val 251 drivers/iio/adc/axp20x_adc.c struct iio_chan_spec const *chan, int *val) val 266 drivers/iio/adc/axp20x_adc.c *val = axp20x_read_variable_width(info->regmap, chan->address, size); val 267 drivers/iio/adc/axp20x_adc.c if (*val < 0) val 268 drivers/iio/adc/axp20x_adc.c return *val; val 274 drivers/iio/adc/axp20x_adc.c struct iio_chan_spec const *chan, int *val) val 278 drivers/iio/adc/axp20x_adc.c *val = axp20x_read_variable_width(info->regmap, chan->address, 12); val 279 drivers/iio/adc/axp20x_adc.c if (*val < 0) val 280 drivers/iio/adc/axp20x_adc.c return *val; val 285 drivers/iio/adc/axp20x_adc.c static int axp20x_adc_scale_voltage(int channel, int *val, int *val2) val 290 drivers/iio/adc/axp20x_adc.c *val = 1; val 296 drivers/iio/adc/axp20x_adc.c *val = 0; val 301 drivers/iio/adc/axp20x_adc.c *val = 1; val 306 drivers/iio/adc/axp20x_adc.c *val = 1; val 315 drivers/iio/adc/axp20x_adc.c static int axp813_adc_scale_voltage(int channel, int *val, int *val2) val 319 drivers/iio/adc/axp20x_adc.c *val = 0; val 324 drivers/iio/adc/axp20x_adc.c *val = 1; val 333 drivers/iio/adc/axp20x_adc.c static int axp20x_adc_scale_current(int channel, int *val, int *val2) val 337 drivers/iio/adc/axp20x_adc.c *val = 0; val 342 drivers/iio/adc/axp20x_adc.c *val = 0; val 348 drivers/iio/adc/axp20x_adc.c *val = 0; val 357 drivers/iio/adc/axp20x_adc.c static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val, val 362 drivers/iio/adc/axp20x_adc.c return axp20x_adc_scale_voltage(chan->channel, val, val2); val 365 drivers/iio/adc/axp20x_adc.c return axp20x_adc_scale_current(chan->channel, val, val2); val 368 drivers/iio/adc/axp20x_adc.c *val = 100; val 376 drivers/iio/adc/axp20x_adc.c static int axp22x_adc_scale(struct iio_chan_spec const *chan, int *val, val 384 drivers/iio/adc/axp20x_adc.c *val = 1; val 389 drivers/iio/adc/axp20x_adc.c *val = 0; val 394 drivers/iio/adc/axp20x_adc.c *val = 100; val 402 drivers/iio/adc/axp20x_adc.c static int axp813_adc_scale(struct iio_chan_spec const *chan, int *val, val 407 drivers/iio/adc/axp20x_adc.c return axp813_adc_scale_voltage(chan->channel, val, val2); val 410 drivers/iio/adc/axp20x_adc.c *val = 1; val 414 drivers/iio/adc/axp20x_adc.c *val = 100; val 423 drivers/iio/adc/axp20x_adc.c int *val) val 428 drivers/iio/adc/axp20x_adc.c ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, val); val 434 drivers/iio/adc/axp20x_adc.c *val &= AXP20X_GPIO10_IN_RANGE_GPIO0; val 438 drivers/iio/adc/axp20x_adc.c *val &= AXP20X_GPIO10_IN_RANGE_GPIO1; val 445 drivers/iio/adc/axp20x_adc.c *val = *val ? 700000 : 0; val 451 drivers/iio/adc/axp20x_adc.c struct iio_chan_spec const *chan, int *val) val 455 drivers/iio/adc/axp20x_adc.c return axp20x_adc_offset_voltage(indio_dev, chan->channel, val); val 458 drivers/iio/adc/axp20x_adc.c *val = -1447; val 467 drivers/iio/adc/axp20x_adc.c struct iio_chan_spec const *chan, int *val, val 472 drivers/iio/adc/axp20x_adc.c return axp20x_adc_offset(indio_dev, chan, val); val 475 drivers/iio/adc/axp20x_adc.c return axp20x_adc_scale(chan, val, val2); val 478 drivers/iio/adc/axp20x_adc.c return axp20x_adc_raw(indio_dev, chan, val); val 486 drivers/iio/adc/axp20x_adc.c struct iio_chan_spec const *chan, int *val, val 491 drivers/iio/adc/axp20x_adc.c *val = -2677; val 495 drivers/iio/adc/axp20x_adc.c return axp22x_adc_scale(chan, val, val2); val 498 drivers/iio/adc/axp20x_adc.c return axp22x_adc_raw(indio_dev, chan, val); val 506 drivers/iio/adc/axp20x_adc.c struct iio_chan_spec const *chan, int *val, val 511 drivers/iio/adc/axp20x_adc.c *val = -2667; val 515 drivers/iio/adc/axp20x_adc.c return axp813_adc_scale(chan, val, val2); val 518 drivers/iio/adc/axp20x_adc.c return axp813_adc_raw(indio_dev, chan, val); val 526 drivers/iio/adc/axp20x_adc.c struct iio_chan_spec const *chan, int val, int val2, val 539 drivers/iio/adc/axp20x_adc.c if (val != 0 && val != 700000) val 542 drivers/iio/adc/axp20x_adc.c val = val ? 1 : 0; val 547 drivers/iio/adc/axp20x_adc.c regval = AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(val); val 552 drivers/iio/adc/axp20x_adc.c regval = AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(val); val 113 drivers/iio/adc/axp288_adc.c static int axp288_adc_read_channel(int *val, unsigned long address, val 120 drivers/iio/adc/axp288_adc.c *val = (buf[0] << 4) + ((buf[1] >> 4) & 0x0F); val 159 drivers/iio/adc/axp288_adc.c int *val, int *val2, long mask) val 173 drivers/iio/adc/axp288_adc.c ret = axp288_adc_read_channel(val, chan->address, info->regmap); val 103 drivers/iio/adc/bcm_iproc_adc.c u32 val; \ val 104 drivers/iio/adc/bcm_iproc_adc.c regmap_read(priv->regmap, reg, &val); \ val 105 drivers/iio/adc/bcm_iproc_adc.c dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \ val 229 drivers/iio/adc/bcm_iproc_adc.c u32 val; val 252 drivers/iio/adc/bcm_iproc_adc.c val = (BIT(IPROC_ADC_CHANNEL_ROUNDS) | val 260 drivers/iio/adc/bcm_iproc_adc.c mask, val); val 274 drivers/iio/adc/bcm_iproc_adc.c regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val); val 277 drivers/iio/adc/bcm_iproc_adc.c val |= (BIT(channel) << IPROC_ADC_INTR); val 278 drivers/iio/adc/bcm_iproc_adc.c regmap_write(adc_priv->regmap, IPROC_INTERRUPT_MASK, val); val 288 drivers/iio/adc/bcm_iproc_adc.c while (val_check != val) { val 354 drivers/iio/adc/bcm_iproc_adc.c u32 val; val 373 drivers/iio/adc/bcm_iproc_adc.c ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); val 380 drivers/iio/adc/bcm_iproc_adc.c val &= ~(IPROC_ADC_PWR_LDO | IPROC_ADC_PWR_ADC | IPROC_ADC_PWR_BG); val 382 drivers/iio/adc/bcm_iproc_adc.c ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); val 389 drivers/iio/adc/bcm_iproc_adc.c ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); val 396 drivers/iio/adc/bcm_iproc_adc.c val |= IPROC_ADC_CONTROLLER_EN; val 397 drivers/iio/adc/bcm_iproc_adc.c ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); val 432 drivers/iio/adc/bcm_iproc_adc.c u32 val; val 436 drivers/iio/adc/bcm_iproc_adc.c ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); val 443 drivers/iio/adc/bcm_iproc_adc.c val &= ~IPROC_ADC_CONTROLLER_EN; val 444 drivers/iio/adc/bcm_iproc_adc.c ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); val 454 drivers/iio/adc/bcm_iproc_adc.c int *val, val 466 drivers/iio/adc/bcm_iproc_adc.c *val = adc_data; val 471 drivers/iio/adc/bcm_iproc_adc.c *val = 1800; val 203 drivers/iio/adc/berlin2-adc.c struct iio_chan_spec const *chan, int *val, val 213 drivers/iio/adc/berlin2-adc.c *val = berlin2_adc_read(indio_dev, chan->channel); val 214 drivers/iio/adc/berlin2-adc.c if (*val < 0) val 215 drivers/iio/adc/berlin2-adc.c return *val; val 230 drivers/iio/adc/berlin2-adc.c *val = ((temp * 100000) / 264 - 270000); val 242 drivers/iio/adc/berlin2-adc.c unsigned val; val 244 drivers/iio/adc/berlin2-adc.c regmap_read(priv->regmap, BERLIN2_SM_ADC_STATUS, &val); val 245 drivers/iio/adc/berlin2-adc.c if (val & BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK) { val 249 drivers/iio/adc/berlin2-adc.c val &= ~BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK; val 250 drivers/iio/adc/berlin2-adc.c regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS, val); val 262 drivers/iio/adc/berlin2-adc.c unsigned val; val 264 drivers/iio/adc/berlin2-adc.c regmap_read(priv->regmap, BERLIN2_SM_TSEN_STATUS, &val); val 265 drivers/iio/adc/berlin2-adc.c if (val & BERLIN2_SM_TSEN_STATUS_DATA_RDY) { val 269 drivers/iio/adc/berlin2-adc.c val &= ~BERLIN2_SM_TSEN_STATUS_DATA_RDY; val 270 drivers/iio/adc/berlin2-adc.c regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS, val); val 68 drivers/iio/adc/cc10001_adc.c u32 reg, u32 val) val 70 drivers/iio/adc/cc10001_adc.c writel(val, adc_dev->reg_base + reg); val 94 drivers/iio/adc/cc10001_adc.c u32 val; val 97 drivers/iio/adc/cc10001_adc.c val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV; val 98 drivers/iio/adc/cc10001_adc.c cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val); val 101 drivers/iio/adc/cc10001_adc.c val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG); val 102 drivers/iio/adc/cc10001_adc.c val = val | CC10001_ADC_START_CONV; val 103 drivers/iio/adc/cc10001_adc.c cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val); val 196 drivers/iio/adc/cc10001_adc.c u16 val; val 206 drivers/iio/adc/cc10001_adc.c val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns); val 211 drivers/iio/adc/cc10001_adc.c return val; val 216 drivers/iio/adc/cc10001_adc.c int *val, int *val2, long mask) val 226 drivers/iio/adc/cc10001_adc.c *val = cc10001_adc_read_raw_voltage(indio_dev, chan); val 229 drivers/iio/adc/cc10001_adc.c if (*val == CC10001_INVALID_SAMPLED) val 238 drivers/iio/adc/cc10001_adc.c *val = ret / 1000; val 848 drivers/iio/adc/cpcap-adc.c int addr, int *val) val 852 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, addr, val); val 856 drivers/iio/adc/cpcap-adc.c *val -= 282; val 857 drivers/iio/adc/cpcap-adc.c *val *= 114; val 858 drivers/iio/adc/cpcap-adc.c *val += 25000; val 865 drivers/iio/adc/cpcap-adc.c int *val, int *val2, long mask) val 881 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, chan->address, val); val 910 drivers/iio/adc/cpcap-adc.c *val = req.result; val 157 drivers/iio/adc/da9150-gpadc.c int hw_chan, int *val) val 170 drivers/iio/adc/da9150-gpadc.c *val = da9150_gpadc_gpio_6v_voltage_now(raw_val); val 173 drivers/iio/adc/da9150-gpadc.c *val = da9150_gpadc_ibus_current_avg(raw_val); val 176 drivers/iio/adc/da9150-gpadc.c *val = da9150_gpadc_vbus_21v_voltage_now(raw_val); val 179 drivers/iio/adc/da9150-gpadc.c *val = da9150_gpadc_vsys_6v_voltage_now(raw_val); val 183 drivers/iio/adc/da9150-gpadc.c *val = raw_val; val 190 drivers/iio/adc/da9150-gpadc.c static int da9150_gpadc_read_scale(int channel, int *val, int *val2) val 194 drivers/iio/adc/da9150-gpadc.c *val = 2932; val 199 drivers/iio/adc/da9150-gpadc.c *val = 1000000; val 207 drivers/iio/adc/da9150-gpadc.c static int da9150_gpadc_read_offset(int channel, int *val) val 211 drivers/iio/adc/da9150-gpadc.c *val = 1500000 / 2932; val 215 drivers/iio/adc/da9150-gpadc.c *val = -144; val 224 drivers/iio/adc/da9150-gpadc.c int *val, int *val2, long mask) val 236 drivers/iio/adc/da9150-gpadc.c chan->address, val); val 238 drivers/iio/adc/da9150-gpadc.c return da9150_gpadc_read_scale(chan->channel, val, val2); val 240 drivers/iio/adc/da9150-gpadc.c return da9150_gpadc_read_offset(chan->channel, val); val 330 drivers/iio/adc/dln2-adc.c int *val, val 347 drivers/iio/adc/dln2-adc.c *val = ret; val 355 drivers/iio/adc/dln2-adc.c *val = 0; val 362 drivers/iio/adc/dln2-adc.c *val = microhertz / 1000000; val 365 drivers/iio/adc/dln2-adc.c *val = 0; val 378 drivers/iio/adc/dln2-adc.c int val, val 388 drivers/iio/adc/dln2-adc.c microhertz = 1000000 * val + val2; val 189 drivers/iio/adc/envelope-detector.c int *val, int *val2, long mask) val 215 drivers/iio/adc/envelope-detector.c *val = env->invert ? env->dac_max - env->level : env->level; val 221 drivers/iio/adc/envelope-detector.c return iio_read_channel_scale(env->dac, val, val2); val 526 drivers/iio/adc/exynos_adc.c int *val, val 552 drivers/iio/adc/exynos_adc.c *val = info->value; val 99 drivers/iio/adc/fsl-imx25-gcq.c int *val) val 126 drivers/iio/adc/fsl-imx25-gcq.c *val = MX25_ADCQ_FIFO_DATA(data); val 132 drivers/iio/adc/fsl-imx25-gcq.c struct iio_chan_spec const *chan, int *val, val 141 drivers/iio/adc/fsl-imx25-gcq.c ret = mx25_gcq_get_raw_value(&indio_dev->dev, chan, priv, val); val 146 drivers/iio/adc/fsl-imx25-gcq.c *val = priv->channel_vref_mv[chan->channel]; val 57 drivers/iio/adc/hi8435.c static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) val 60 drivers/iio/adc/hi8435.c return spi_write_then_read(priv->spi, ®, 1, val, 1); val 63 drivers/iio/adc/hi8435.c static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val) val 70 drivers/iio/adc/hi8435.c *val = be16_to_cpu(be_val); val 75 drivers/iio/adc/hi8435.c static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val) val 82 drivers/iio/adc/hi8435.c *val = be32_to_cpu(be_val); val 87 drivers/iio/adc/hi8435.c static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val) val 90 drivers/iio/adc/hi8435.c priv->reg_buffer[1] = val; val 95 drivers/iio/adc/hi8435.c static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val) val 98 drivers/iio/adc/hi8435.c priv->reg_buffer[1] = (val >> 8) & 0xff; val 99 drivers/iio/adc/hi8435.c priv->reg_buffer[2] = val & 0xff; val 106 drivers/iio/adc/hi8435.c int *val, int *val2, long mask) val 117 drivers/iio/adc/hi8435.c *val = !!(tmp & BIT(chan->channel)); val 164 drivers/iio/adc/hi8435.c int *val, int *val2) val 184 drivers/iio/adc/hi8435.c *val = ((reg & 0xff) - (reg >> 8)) / 2; val 186 drivers/iio/adc/hi8435.c *val = ((reg & 0xff) + (reg >> 8)) / 2; val 196 drivers/iio/adc/hi8435.c int val, int val2) val 217 drivers/iio/adc/hi8435.c if (val < 2 || val > 21 || (val + 2) > priv->threshold_hi[mode]) val 220 drivers/iio/adc/hi8435.c if (val == priv->threshold_lo[mode]) val 223 drivers/iio/adc/hi8435.c priv->threshold_lo[mode] = val; val 230 drivers/iio/adc/hi8435.c if (val < 3 || val > 22 || val < (priv->threshold_lo[mode] + 2)) val 233 drivers/iio/adc/hi8435.c if (val == priv->threshold_hi[mode]) val 236 drivers/iio/adc/hi8435.c priv->threshold_hi[mode] = val; val 273 drivers/iio/adc/hi8435.c u8 val; val 276 drivers/iio/adc/hi8435.c ret = hi8435_readb(priv, reg, &val); val 277 drivers/iio/adc/hi8435.c *readval = val; val 279 drivers/iio/adc/hi8435.c val = (u8)writeval; val 280 drivers/iio/adc/hi8435.c ret = hi8435_writeb(priv, reg, val); val 415 drivers/iio/adc/hi8435.c static void hi8435_iio_push_event(struct iio_dev *idev, unsigned int val) val 420 drivers/iio/adc/hi8435.c unsigned int status = priv->event_prev_val ^ val; val 427 drivers/iio/adc/hi8435.c dir = val & BIT(i) ? IIO_EV_DIR_RISING : val 436 drivers/iio/adc/hi8435.c priv->event_prev_val = val; val 444 drivers/iio/adc/hi8435.c u32 val; val 447 drivers/iio/adc/hi8435.c ret = hi8435_readl(priv, HI8435_SO31_0_REG, &val); val 451 drivers/iio/adc/hi8435.c hi8435_iio_push_event(idev, val); val 143 drivers/iio/adc/hx711.c int val = gpiod_get_value(hx711_data->gpiod_dout); val 146 drivers/iio/adc/hx711.c if (val) val 166 drivers/iio/adc/hx711.c int i, val; val 174 drivers/iio/adc/hx711.c val = gpiod_get_value(hx711_data->gpiod_dout); val 175 drivers/iio/adc/hx711.c if (!val) val 180 drivers/iio/adc/hx711.c if (val) val 189 drivers/iio/adc/hx711.c int val = gpiod_get_value(hx711_data->gpiod_dout); val 191 drivers/iio/adc/hx711.c if (val) { val 220 drivers/iio/adc/hx711.c val = hx711_wait_for_ready(hx711_data); val 223 drivers/iio/adc/hx711.c return val; val 262 drivers/iio/adc/hx711.c int val; val 277 drivers/iio/adc/hx711.c val = hx711_read(hx711_data); val 279 drivers/iio/adc/hx711.c return val; val 284 drivers/iio/adc/hx711.c int *val, int *val2, long mask) val 292 drivers/iio/adc/hx711.c *val = hx711_reset_read(hx711_data, chan->channel); val 296 drivers/iio/adc/hx711.c if (*val < 0) val 297 drivers/iio/adc/hx711.c return *val; val 300 drivers/iio/adc/hx711.c *val = 0; val 315 drivers/iio/adc/hx711.c int val, val 329 drivers/iio/adc/hx711.c if (val != 0) val 284 drivers/iio/adc/imx7d_adc.c int *val, val 313 drivers/iio/adc/imx7d_adc.c *val = info->value; val 319 drivers/iio/adc/imx7d_adc.c *val = info->vref_uv / 1000; val 324 drivers/iio/adc/imx7d_adc.c *val = imx7d_adc_get_sample_rate(info); val 70 drivers/iio/adc/ina2xx-adc.c #define INA219_SHIFT_PGA(val) ((val) << 11) val 74 drivers/iio/adc/ina2xx-adc.c #define INA219_SHIFT_BRNG(val) ((val) << 13) val 78 drivers/iio/adc/ina2xx-adc.c #define INA226_SHIFT_AVG(val) ((val) << 9) val 82 drivers/iio/adc/ina2xx-adc.c #define INA219_SHIFT_ITB(val) ((val) << 7) val 84 drivers/iio/adc/ina2xx-adc.c #define INA226_SHIFT_ITB(val) ((val) << 6) val 88 drivers/iio/adc/ina2xx-adc.c #define INA219_SHIFT_ITS(val) ((val) << 3) val 90 drivers/iio/adc/ina2xx-adc.c #define INA226_SHIFT_ITS(val) ((val) << 3) val 174 drivers/iio/adc/ina2xx-adc.c int *val, int *val2, long mask) val 187 drivers/iio/adc/ina2xx-adc.c *val = (s16) regval; val 189 drivers/iio/adc/ina2xx-adc.c *val = regval; val 192 drivers/iio/adc/ina2xx-adc.c *val >>= chip->config->bus_voltage_shift; val 197 drivers/iio/adc/ina2xx-adc.c *val = chip->avg; val 201 drivers/iio/adc/ina2xx-adc.c *val = 0; val 214 drivers/iio/adc/ina2xx-adc.c *val = DIV_ROUND_CLOSEST(1000000, SAMPLING_PERIOD(chip)); val 222 drivers/iio/adc/ina2xx-adc.c *val = chip->config->shunt_voltage_lsb; val 228 drivers/iio/adc/ina2xx-adc.c *val = chip->config->bus_voltage_lsb; val 238 drivers/iio/adc/ina2xx-adc.c *val = chip->config->shunt_voltage_lsb; val 248 drivers/iio/adc/ina2xx-adc.c *val = chip->config->power_lsb_factor * val 258 drivers/iio/adc/ina2xx-adc.c *val = chip->pga_gain_vshunt; val 263 drivers/iio/adc/ina2xx-adc.c *val = chip->range_vbus == 32 ? 1 : 2; val 280 drivers/iio/adc/ina2xx-adc.c static int ina226_set_average(struct ina2xx_chip_info *chip, unsigned int val, val 285 drivers/iio/adc/ina2xx-adc.c if (val > 1024 || val < 1) val 288 drivers/iio/adc/ina2xx-adc.c bits = find_closest(val, ina226_avg_tab, val 471 drivers/iio/adc/ina2xx-adc.c int val, int val2, long mask) val 490 drivers/iio/adc/ina2xx-adc.c ret = ina226_set_average(chip, val, &tmp); val 513 drivers/iio/adc/ina2xx-adc.c ret = ina219_set_vshunt_pga_gain(chip, val * 1000 + val 516 drivers/iio/adc/ina2xx-adc.c ret = ina219_set_vbus_range_denom(chip, val, &tmp); val 545 drivers/iio/adc/ina2xx-adc.c bool val; val 548 drivers/iio/adc/ina2xx-adc.c ret = strtobool((const char *) buf, &val); val 552 drivers/iio/adc/ina2xx-adc.c chip->allow_async_readout = val; val 570 drivers/iio/adc/ina2xx-adc.c static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val) val 572 drivers/iio/adc/ina2xx-adc.c if (val == 0 || val > INT_MAX) val 575 drivers/iio/adc/ina2xx-adc.c chip->shunt_resistor_uohm = val; val 595 drivers/iio/adc/ina2xx-adc.c int val, val_fract, ret; val 597 drivers/iio/adc/ina2xx-adc.c ret = iio_str_to_fixpoint(buf, 100000, &val, &val_fract); val 601 drivers/iio/adc/ina2xx-adc.c ret = set_shunt_resistor(chip, val * 1000000 + val_fract); val 754 drivers/iio/adc/ina2xx-adc.c unsigned int val; val 757 drivers/iio/adc/ina2xx-adc.c INA2XX_SHUNT_VOLTAGE + bit, &val); val 761 drivers/iio/adc/ina2xx-adc.c data[i++] = val; val 954 drivers/iio/adc/ina2xx-adc.c unsigned int val; val 982 drivers/iio/adc/ina2xx-adc.c "shunt-resistor", &val) < 0) { val 987 drivers/iio/adc/ina2xx-adc.c val = pdata->shunt_uohms; val 989 drivers/iio/adc/ina2xx-adc.c val = INA2XX_RSHUNT_DEFAULT; val 992 drivers/iio/adc/ina2xx-adc.c ret = set_shunt_resistor(chip, val); val 997 drivers/iio/adc/ina2xx-adc.c val = chip->config->config_default; val 1000 drivers/iio/adc/ina2xx-adc.c ina226_set_average(chip, INA226_DEFAULT_AVG, &val); val 1001 drivers/iio/adc/ina2xx-adc.c ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val); val 1002 drivers/iio/adc/ina2xx-adc.c ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val); val 1005 drivers/iio/adc/ina2xx-adc.c ina219_set_int_time_vbus(chip, INA219_DEFAULT_IT, &val); val 1006 drivers/iio/adc/ina2xx-adc.c ina219_set_int_time_vshunt(chip, INA219_DEFAULT_IT, &val); val 1007 drivers/iio/adc/ina2xx-adc.c ina219_set_vbus_range_denom(chip, INA219_DEFAULT_BRNG, &val); val 1008 drivers/iio/adc/ina2xx-adc.c ina219_set_vshunt_pga_gain(chip, INA219_DEFAULT_PGA, &val); val 1011 drivers/iio/adc/ina2xx-adc.c ret = ina2xx_init(chip, val); val 63 drivers/iio/adc/ingenic-adc.c uint32_t val) val 71 drivers/iio/adc/ingenic-adc.c cfg |= val; val 82 drivers/iio/adc/ingenic-adc.c u8 val; val 85 drivers/iio/adc/ingenic-adc.c val = readb(adc->base + JZ_ADC_REG_ENABLE); val 88 drivers/iio/adc/ingenic-adc.c val |= BIT(engine); val 90 drivers/iio/adc/ingenic-adc.c val &= ~BIT(engine); val 92 drivers/iio/adc/ingenic-adc.c writeb(val, adc->base + JZ_ADC_REG_ENABLE); val 99 drivers/iio/adc/ingenic-adc.c u8 val; val 103 drivers/iio/adc/ingenic-adc.c ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val, val 104 drivers/iio/adc/ingenic-adc.c !(val & BIT(engine)), 250, 1000); val 113 drivers/iio/adc/ingenic-adc.c int val, val 123 drivers/iio/adc/ingenic-adc.c if (val > JZ_ADC_BATTERY_LOW_VREF) { val 244 drivers/iio/adc/ingenic-adc.c int *val, val 262 drivers/iio/adc/ingenic-adc.c *val = readw(adc->base + JZ_ADC_REG_ADSDAT); val 265 drivers/iio/adc/ingenic-adc.c *val = readw(adc->base + JZ_ADC_REG_ADBDAT); val 275 drivers/iio/adc/ingenic-adc.c *val = JZ_ADC_AUX_VREF; val 280 drivers/iio/adc/ingenic-adc.c *val = JZ_ADC_BATTERY_LOW_VREF; val 283 drivers/iio/adc/ingenic-adc.c *val = adc->soc_data->battery_high_vref; val 49 drivers/iio/adc/lp8788_adc.c int *val) val 86 drivers/iio/adc/lp8788_adc.c *val = result; val 96 drivers/iio/adc/lp8788_adc.c int *val, int *val2, long mask) val 106 drivers/iio/adc/lp8788_adc.c ret = lp8788_get_adc_result(adc, id, val) ? -EIO : IIO_VAL_INT; val 109 drivers/iio/adc/lp8788_adc.c *val = lp8788_scale[id] / 1000000; val 90 drivers/iio/adc/lpc18xx_adc.c int *val, int *val2, long mask) val 97 drivers/iio/adc/lpc18xx_adc.c *val = lpc18xx_adc_read_chan(adc, chan->channel); val 99 drivers/iio/adc/lpc18xx_adc.c if (*val < 0) val 100 drivers/iio/adc/lpc18xx_adc.c return *val; val 105 drivers/iio/adc/lpc18xx_adc.c *val = regulator_get_voltage(adc->vref) / 1000; val 57 drivers/iio/adc/lpc32xx_adc.c int *val, val 81 drivers/iio/adc/lpc32xx_adc.c *val = st->value; val 87 drivers/iio/adc/lpc32xx_adc.c *val = regulator_get_voltage(st->vref) / 1000; val 47 drivers/iio/adc/ltc2471.c int *val, int *val2, long info) val 57 drivers/iio/adc/ltc2471.c *val = ret; val 63 drivers/iio/adc/ltc2471.c *val = 2 * LTC2471_VREF; val 66 drivers/iio/adc/ltc2471.c *val = LTC2471_VREF; val 72 drivers/iio/adc/ltc2471.c *val = -LTC2471_VREF; val 37 drivers/iio/adc/ltc2485.c static int ltc2485_read(struct ltc2485_data *data, int *val) val 51 drivers/iio/adc/ltc2485.c *val = sign_extend32(be32_to_cpu(buf) >> 6, 24); val 58 drivers/iio/adc/ltc2485.c int *val, int *val2, long mask) val 64 drivers/iio/adc/ltc2485.c ret = ltc2485_read(data, val); val 71 drivers/iio/adc/ltc2485.c *val = 5000; /* on board vref millivolts */ val 65 drivers/iio/adc/ltc2497.c static int ltc2497_read(struct ltc2497_st *st, u8 address, int *val) val 93 drivers/iio/adc/ltc2497.c *val = (be32_to_cpu(st->buf) >> 14) - (1 << 17); val 100 drivers/iio/adc/ltc2497.c int *val, int *val2, long mask) val 108 drivers/iio/adc/ltc2497.c ret = ltc2497_read(st, chan->address, val); val 120 drivers/iio/adc/ltc2497.c *val = ret / 1000; val 217 drivers/iio/adc/max1027.c int *val) val 260 drivers/iio/adc/max1027.c *val = be16_to_cpu(st->buffer[0]); val 267 drivers/iio/adc/max1027.c int *val, int *val2, long mask) val 276 drivers/iio/adc/max1027.c ret = max1027_read_single_value(indio_dev, chan, val); val 281 drivers/iio/adc/max1027.c *val = 1; val 286 drivers/iio/adc/max1027.c *val = 2500; val 310 drivers/iio/adc/max1027.c u8 *val = (u8 *)st->buffer; val 315 drivers/iio/adc/max1027.c *val = (u8)writeval; val 316 drivers/iio/adc/max1027.c return spi_write(st->spi, val, 1); val 48 drivers/iio/adc/max11100.c static int max11100_read_single(struct iio_dev *indio_dev, int *val) val 65 drivers/iio/adc/max11100.c *val = (state->buffer[1] << 8) | state->buffer[2]; val 72 drivers/iio/adc/max11100.c int *val, int *val2, long info) val 79 drivers/iio/adc/max11100.c ret = max11100_read_single(indio_dev, val); val 91 drivers/iio/adc/max11100.c *val = vref_uv / 1000; val 128 drivers/iio/adc/max1118.c int *val, int *val2, long mask) val 135 drivers/iio/adc/max1118.c *val = max1118_read(adc->spi, chan->channel); val 137 drivers/iio/adc/max1118.c if (*val < 0) val 138 drivers/iio/adc/max1118.c return *val; val 142 drivers/iio/adc/max1118.c *val = max1118_get_vref_mV(adc->spi); val 143 drivers/iio/adc/max1118.c if (*val < 0) val 144 drivers/iio/adc/max1118.c return *val; val 358 drivers/iio/adc/max1363.c int *val, val 406 drivers/iio/adc/max1363.c *val = data; val 415 drivers/iio/adc/max1363.c int *val, val 424 drivers/iio/adc/max1363.c ret = max1363_read_single_chan(indio_dev, chan, val, m); val 429 drivers/iio/adc/max1363.c *val = st->vref_uv / 1000; val 694 drivers/iio/adc/max1363.c unsigned long val; val 697 drivers/iio/adc/max1363.c ret = kstrtoul(buf, 10, &val); val 701 drivers/iio/adc/max1363.c if (val == max1363_monitor_speeds[i]) { val 724 drivers/iio/adc/max1363.c enum iio_event_direction dir, enum iio_event_info info, int *val, val 729 drivers/iio/adc/max1363.c *val = st->thresh_low[chan->channel]; val 731 drivers/iio/adc/max1363.c *val = st->thresh_high[chan->channel]; val 737 drivers/iio/adc/max1363.c enum iio_event_direction dir, enum iio_event_info info, int val, val 744 drivers/iio/adc/max1363.c if (val > 0x3FF) val 748 drivers/iio/adc/max1363.c if (val > 0xFFF) val 755 drivers/iio/adc/max1363.c st->thresh_low[chan->channel] = val; val 758 drivers/iio/adc/max1363.c st->thresh_high[chan->channel] = val; val 810 drivers/iio/adc/max1363.c int val; val 815 drivers/iio/adc/max1363.c val = (1 << number) & st->mask_low; val 817 drivers/iio/adc/max1363.c val = (1 << number) & st->mask_high; val 820 drivers/iio/adc/max1363.c return val; val 303 drivers/iio/adc/max9611.c int *val, int *val2, long mask) val 321 drivers/iio/adc/max9611.c *val = MAX9611_TEMP_RAW(adc_data); val 330 drivers/iio/adc/max9611.c *val = MAX9611_VOLTAGE_RAW(adc_data); val 338 drivers/iio/adc/max9611.c *val = MAX9611_CIM_OFFSET_RAW; val 346 drivers/iio/adc/max9611.c *val = MAX9611_TEMP_SCALE_NUM; val 352 drivers/iio/adc/max9611.c *val = MAX9611_CIM_LSB_mV; val 377 drivers/iio/adc/max9611.c *val = MAX9611_VOLTAGE_RAW(adc_data) * val 393 drivers/iio/adc/max9611.c *val = MAX9611_VOLTAGE_RAW(adc_data) * val 410 drivers/iio/adc/max9611.c *val = MAX9611_VOLTAGE_RAW(adc_data) * val 422 drivers/iio/adc/max9611.c *val *= MAX9611_VOLTAGE_RAW(adc_data) * val 120 drivers/iio/adc/mcp320x.c bool differential, int device_index, int *val) val 144 drivers/iio/adc/mcp320x.c *val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3); val 149 drivers/iio/adc/mcp320x.c *val = (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6); val 152 drivers/iio/adc/mcp320x.c *val = (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1); val 157 drivers/iio/adc/mcp320x.c *val = (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4); val 160 drivers/iio/adc/mcp320x.c *val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8 val 185 drivers/iio/adc/mcp320x.c *val = (s32)raw; val 194 drivers/iio/adc/mcp320x.c struct iio_chan_spec const *channel, int *val, val 208 drivers/iio/adc/mcp320x.c channel->differential, device_index, val); val 221 drivers/iio/adc/mcp320x.c *val = ret / 1000; val 57 drivers/iio/adc/mcp3911.c static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) val 62 drivers/iio/adc/mcp3911.c ret = spi_write_then_read(adc->spi, ®, 1, val, len); val 66 drivers/iio/adc/mcp3911.c be32_to_cpus(val); val 67 drivers/iio/adc/mcp3911.c *val >>= ((4 - len) * 8); val 68 drivers/iio/adc/mcp3911.c dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%x\n", *val, val 73 drivers/iio/adc/mcp3911.c static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) val 75 drivers/iio/adc/mcp3911.c dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); val 77 drivers/iio/adc/mcp3911.c val <<= (3 - len) * 8; val 78 drivers/iio/adc/mcp3911.c cpu_to_be32s(&val); val 79 drivers/iio/adc/mcp3911.c val |= MCP3911_REG_WRITE(reg, adc->dev_addr); val 81 drivers/iio/adc/mcp3911.c return spi_write(adc->spi, &val, len + 1); val 85 drivers/iio/adc/mcp3911.c u32 val, u8 len) val 94 drivers/iio/adc/mcp3911.c val &= mask; val 95 drivers/iio/adc/mcp3911.c val |= tmp & ~mask; val 96 drivers/iio/adc/mcp3911.c return mcp3911_write(adc, reg, val, len); val 100 drivers/iio/adc/mcp3911.c struct iio_chan_spec const *channel, int *val, val 110 drivers/iio/adc/mcp3911.c MCP3911_CHANNEL(channel->channel), val, 3); val 119 drivers/iio/adc/mcp3911.c MCP3911_OFFCAL(channel->channel), val, 3); val 136 drivers/iio/adc/mcp3911.c *val = ret / 1000; val 138 drivers/iio/adc/mcp3911.c *val = MCP3911_INT_VREF_UV; val 152 drivers/iio/adc/mcp3911.c struct iio_chan_spec const *channel, int val, val 167 drivers/iio/adc/mcp3911.c ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val, val 49 drivers/iio/adc/men_z188_adc.c int *val, val 67 drivers/iio/adc/men_z188_adc.c *val = ADC_DATA(tmp); val 311 drivers/iio/adc/meson_saradc.c static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val) val 317 drivers/iio/adc/meson_saradc.c tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; val 345 drivers/iio/adc/meson_saradc.c int *val) val 372 drivers/iio/adc/meson_saradc.c *val = meson_sar_adc_calib_val(indio_dev, fifo_val); val 383 drivers/iio/adc/meson_saradc.c int val, address = chan->address; val 385 drivers/iio/adc/meson_saradc.c val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address); val 388 drivers/iio/adc/meson_saradc.c val); val 390 drivers/iio/adc/meson_saradc.c val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address); val 392 drivers/iio/adc/meson_saradc.c MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val); val 493 drivers/iio/adc/meson_saradc.c int val, timeout = 10000; val 509 drivers/iio/adc/meson_saradc.c regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); val 510 drivers/iio/adc/meson_saradc.c } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); val 550 drivers/iio/adc/meson_saradc.c int *val) val 570 drivers/iio/adc/meson_saradc.c ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val); val 587 drivers/iio/adc/meson_saradc.c int *val, int *val2, long mask) val 595 drivers/iio/adc/meson_saradc.c ONE_SAMPLE, val); val 601 drivers/iio/adc/meson_saradc.c val); val 614 drivers/iio/adc/meson_saradc.c *val = ret / 1000; val 619 drivers/iio/adc/meson_saradc.c *val = priv->param->temperature_multiplier; val 623 drivers/iio/adc/meson_saradc.c *val *= 1000; val 631 drivers/iio/adc/meson_saradc.c *val = priv->calibbias; val 635 drivers/iio/adc/meson_saradc.c *val = priv->calibscale / MILLION; val 640 drivers/iio/adc/meson_saradc.c *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET * val 643 drivers/iio/adc/meson_saradc.c *val -= priv->temperature_sensor_adc_val; val 93 drivers/iio/adc/mt6577_auxadc.c u32 val; val 95 drivers/iio/adc/mt6577_auxadc.c val = readl(reg); val 96 drivers/iio/adc/mt6577_auxadc.c val |= or_mask; val 97 drivers/iio/adc/mt6577_auxadc.c val &= ~and_mask; val 98 drivers/iio/adc/mt6577_auxadc.c writel(val, reg); val 104 drivers/iio/adc/mt6577_auxadc.c u32 val; val 118 drivers/iio/adc/mt6577_auxadc.c ret = readl_poll_timeout(reg_channel, val, val 119 drivers/iio/adc/mt6577_auxadc.c ((val & MT6577_AUXADC_RDY0) == 0), val 139 drivers/iio/adc/mt6577_auxadc.c val, ((val & MT6577_AUXADC_STA) == 0), val 150 drivers/iio/adc/mt6577_auxadc.c ret = readl_poll_timeout(reg_channel, val, val 151 drivers/iio/adc/mt6577_auxadc.c ((val & MT6577_AUXADC_RDY0) != 0), val 162 drivers/iio/adc/mt6577_auxadc.c val = readl(reg_channel) & MT6577_AUXADC_DAT_MASK; val 166 drivers/iio/adc/mt6577_auxadc.c return val; val 177 drivers/iio/adc/mt6577_auxadc.c int *val, val 185 drivers/iio/adc/mt6577_auxadc.c *val = mt6577_auxadc_read(indio_dev, chan); val 186 drivers/iio/adc/mt6577_auxadc.c if (*val < 0) { val 190 drivers/iio/adc/mt6577_auxadc.c return *val; val 193 drivers/iio/adc/mt6577_auxadc.c *val = mt_auxadc_get_cali_data(*val, true); val 131 drivers/iio/adc/mxs-lradc-adc.c int *val) val 187 drivers/iio/adc/mxs-lradc-adc.c *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; val 199 drivers/iio/adc/mxs-lradc-adc.c static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val) val 211 drivers/iio/adc/mxs-lradc-adc.c *val = max - min; val 218 drivers/iio/adc/mxs-lradc-adc.c int *val, int *val2, long m) val 225 drivers/iio/adc/mxs-lradc-adc.c return mxs_lradc_adc_read_temp(iio_dev, val); val 227 drivers/iio/adc/mxs-lradc-adc.c return mxs_lradc_adc_read_single(iio_dev, chan->channel, val); val 235 drivers/iio/adc/mxs-lradc-adc.c *val = 0; val 240 drivers/iio/adc/mxs-lradc-adc.c *val = adc->vref_mv[chan->channel]; val 253 drivers/iio/adc/mxs-lradc-adc.c *val = -1079; val 270 drivers/iio/adc/mxs-lradc-adc.c int val, int val2, long m) val 284 drivers/iio/adc/mxs-lradc-adc.c if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer && val 289 drivers/iio/adc/mxs-lradc-adc.c } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer && val 206 drivers/iio/adc/nau7802.c int *val) val 232 drivers/iio/adc/nau7802.c *val = st->last_value; val 244 drivers/iio/adc/nau7802.c int *val) val 284 drivers/iio/adc/nau7802.c *val = st->last_value; val 291 drivers/iio/adc/nau7802.c int *val, int *val2, long mask) val 326 drivers/iio/adc/nau7802.c ret = nau7802_read_irq(indio_dev, chan, val); val 328 drivers/iio/adc/nau7802.c ret = nau7802_read_poll(indio_dev, chan, val); val 342 drivers/iio/adc/nau7802.c *val = st->vref_mv; val 348 drivers/iio/adc/nau7802.c *val = nau7802_sample_freq_avail[st->sample_rate]; val 361 drivers/iio/adc/nau7802.c int val, int val2, long mask) val 376 drivers/iio/adc/nau7802.c if (val == nau7802_sample_freq_avail[i]) { val 93 drivers/iio/adc/npcm_adc.c static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel) val 128 drivers/iio/adc/npcm_adc.c *val = NPCM_ADC_DATA_MASK(ioread32(info->regs + NPCM_ADCDATA)); val 134 drivers/iio/adc/npcm_adc.c struct iio_chan_spec const *chan, int *val, val 144 drivers/iio/adc/npcm_adc.c ret = npcm_adc_read(info, val, chan->channel); val 154 drivers/iio/adc/npcm_adc.c *val = vref_uv / 1000; val 156 drivers/iio/adc/npcm_adc.c *val = NPCM_INT_VREF_MV; val 161 drivers/iio/adc/npcm_adc.c *val = info->adc_sample_hz; val 216 drivers/iio/adc/palmas_gpadc.c unsigned int mask, val; val 220 drivers/iio/adc/palmas_gpadc.c val = (adc->extended_delay val 224 drivers/iio/adc/palmas_gpadc.c PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val); val 233 drivers/iio/adc/palmas_gpadc.c val = (adc->ch0_current val 235 drivers/iio/adc/palmas_gpadc.c val |= (adc->ch3_current val 237 drivers/iio/adc/palmas_gpadc.c val |= PALMAS_GPADC_CTRL1_GPADC_FORCE; val 239 drivers/iio/adc/palmas_gpadc.c PALMAS_GPADC_CTRL1, mask, val); val 248 drivers/iio/adc/palmas_gpadc.c val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN); val 250 drivers/iio/adc/palmas_gpadc.c PALMAS_GPADC_SW_SELECT, mask, val); val 333 drivers/iio/adc/palmas_gpadc.c unsigned int val; val 354 drivers/iio/adc/palmas_gpadc.c PALMAS_GPADC_SW_CONV0_LSB, &val, 2); val 360 drivers/iio/adc/palmas_gpadc.c ret = val & 0xFFF; val 366 drivers/iio/adc/palmas_gpadc.c int adc_chan, int val) val 369 drivers/iio/adc/palmas_gpadc.c val = (val*1000 - adc->adc_info[adc_chan].offset) / val 372 drivers/iio/adc/palmas_gpadc.c if (val < 0) { val 377 drivers/iio/adc/palmas_gpadc.c val = (val * adc->adc_info[adc_chan].gain) / 1000; val 379 drivers/iio/adc/palmas_gpadc.c return val; val 383 drivers/iio/adc/palmas_gpadc.c struct iio_chan_spec const *chan, int *val, int *val2, long mask) val 412 drivers/iio/adc/palmas_gpadc.c *val = ret; val 443 drivers/iio/adc/qcom-pm8xxx-xoadc.c unsigned int val; val 453 drivers/iio/adc/qcom-pm8xxx-xoadc.c val = ch->hwchan->amux_channel << ADC_AMUX_SEL_SHIFT; val 454 drivers/iio/adc/qcom-pm8xxx-xoadc.c val |= ch->hwchan->pre_scale_mux << ADC_AMUX_PREMUX_SHIFT; val 455 drivers/iio/adc/qcom-pm8xxx-xoadc.c ret = regmap_write(adc->map, ADC_ARB_USRP_AMUX_CNTRL, val); val 545 drivers/iio/adc/qcom-pm8xxx-xoadc.c ret = regmap_read(adc->map, ADC_ARB_USRP_DATA0, &val); val 548 drivers/iio/adc/qcom-pm8xxx-xoadc.c lsb = val; val 549 drivers/iio/adc/qcom-pm8xxx-xoadc.c ret = regmap_read(adc->map, ADC_ARB_USRP_DATA1, &val); val 552 drivers/iio/adc/qcom-pm8xxx-xoadc.c msb = val; val 649 drivers/iio/adc/qcom-pm8xxx-xoadc.c int *val, int *val2, long mask) val 672 drivers/iio/adc/qcom-pm8xxx-xoadc.c adc_code, val); val 688 drivers/iio/adc/qcom-pm8xxx-xoadc.c *val = (int)adc_code; val 381 drivers/iio/adc/qcom-spmi-adc5.c struct iio_chan_spec const *chan, int *val, int *val2, val 401 drivers/iio/adc/qcom-spmi-adc5.c adc_code_volt, val); val 120 drivers/iio/adc/qcom-spmi-iadc.c unsigned int val; val 123 drivers/iio/adc/qcom-spmi-iadc.c ret = regmap_read(iadc->regmap, iadc->base + offset, &val); val 127 drivers/iio/adc/qcom-spmi-iadc.c *data = val; val 312 drivers/iio/adc/qcom-spmi-iadc.c int *val, int *val2, long mask) val 338 drivers/iio/adc/qcom-spmi-iadc.c *val = isense_ua; val 341 drivers/iio/adc/qcom-spmi-iadc.c *val = 0; val 397 drivers/iio/adc/qcom-spmi-iadc.c u8 val; val 400 drivers/iio/adc/qcom-spmi-iadc.c ret = iadc_read(iadc, IADC_PERPH_TYPE, &val); val 404 drivers/iio/adc/qcom-spmi-iadc.c if (val < IADC_PERPH_TYPE_ADC) { val 405 drivers/iio/adc/qcom-spmi-iadc.c dev_err(iadc->dev, "%d is not ADC\n", val); val 409 drivers/iio/adc/qcom-spmi-iadc.c ret = iadc_read(iadc, IADC_PERPH_SUBTYPE, &val); val 413 drivers/iio/adc/qcom-spmi-iadc.c if (val < IADC_PERPH_SUBTYPE_IADC) { val 414 drivers/iio/adc/qcom-spmi-iadc.c dev_err(iadc->dev, "%d is not IADC\n", val); val 418 drivers/iio/adc/qcom-spmi-iadc.c ret = iadc_read(iadc, IADC_REVISION2, &val); val 422 drivers/iio/adc/qcom-spmi-iadc.c if (val < IADC_REVISION2_SUPPORTED_IADC) { val 423 drivers/iio/adc/qcom-spmi-iadc.c dev_err(iadc->dev, "revision %d not supported\n", val); val 445 drivers/iio/adc/qcom-spmi-vadc.c struct iio_chan_spec const *chan, int *val, int *val2, val 464 drivers/iio/adc/qcom-spmi-vadc.c adc_code, val); val 475 drivers/iio/adc/qcom-spmi-vadc.c *val = (int)adc_code; val 817 drivers/iio/adc/qcom-spmi-vadc.c u8 val; val 820 drivers/iio/adc/qcom-spmi-vadc.c ret = vadc_read(vadc, VADC_PERPH_TYPE, &val); val 824 drivers/iio/adc/qcom-spmi-vadc.c if (val < VADC_PERPH_TYPE_ADC) { val 825 drivers/iio/adc/qcom-spmi-vadc.c dev_err(vadc->dev, "%d is not ADC\n", val); val 829 drivers/iio/adc/qcom-spmi-vadc.c ret = vadc_read(vadc, VADC_PERPH_SUBTYPE, &val); val 833 drivers/iio/adc/qcom-spmi-vadc.c if (val < VADC_PERPH_SUBTYPE_VADC) { val 834 drivers/iio/adc/qcom-spmi-vadc.c dev_err(vadc->dev, "%d is not VADC\n", val); val 838 drivers/iio/adc/qcom-spmi-vadc.c ret = vadc_read(vadc, VADC_REVISION2, &val); val 842 drivers/iio/adc/qcom-spmi-vadc.c if (val < VADC_REVISION2_SUPPORTED_VADC) { val 843 drivers/iio/adc/qcom-spmi-vadc.c dev_err(vadc->dev, "revision %d not supported\n", val); val 181 drivers/iio/adc/rcar-gyroadc.c int *val, int *val2, long mask) val 217 drivers/iio/adc/rcar-gyroadc.c *val = readl(priv->regs + datareg); val 218 drivers/iio/adc/rcar-gyroadc.c *val &= BIT(priv->sample_width) - 1; val 232 drivers/iio/adc/rcar-gyroadc.c *val = vref / 1000; val 237 drivers/iio/adc/rcar-gyroadc.c *val = RCAR_GYROADC_SAMPLE_RATE; val 56 drivers/iio/adc/rockchip_saradc.c int *val, int *val2, long mask) val 83 drivers/iio/adc/rockchip_saradc.c *val = info->last_val; val 93 drivers/iio/adc/rockchip_saradc.c *val = ret / 1000; val 189 drivers/iio/adc/sc27xx_adc.c int scale, int *val) val 256 drivers/iio/adc/sc27xx_adc.c *val = value; val 314 drivers/iio/adc/sc27xx_adc.c int channel, int scale, int *val) val 322 drivers/iio/adc/sc27xx_adc.c *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc); val 328 drivers/iio/adc/sc27xx_adc.c int *val, int *val2, long mask) val 343 drivers/iio/adc/sc27xx_adc.c *val = tmp; val 355 drivers/iio/adc/sc27xx_adc.c *val = tmp; val 359 drivers/iio/adc/sc27xx_adc.c *val = scale; val 369 drivers/iio/adc/sc27xx_adc.c int val, int val2, long mask) val 375 drivers/iio/adc/sc27xx_adc.c data->channel_scale[chan->channel] = val; val 90 drivers/iio/adc/spear_adc.c static void spear_adc_set_status(struct spear_adc_state *st, u32 val) val 92 drivers/iio/adc/spear_adc.c __raw_writel(val, &st->adc_base_spear6xx->status); val 95 drivers/iio/adc/spear_adc.c static void spear_adc_set_clk(struct spear_adc_state *st, u32 val) val 100 drivers/iio/adc/spear_adc.c count = DIV_ROUND_UP(apb_clk, val); val 110 drivers/iio/adc/spear_adc.c u32 val) val 112 drivers/iio/adc/spear_adc.c __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]); val 140 drivers/iio/adc/spear_adc.c int *val, val 160 drivers/iio/adc/spear_adc.c *val = st->value; val 167 drivers/iio/adc/spear_adc.c *val = st->vref_external; val 171 drivers/iio/adc/spear_adc.c *val = st->current_clk; val 180 drivers/iio/adc/spear_adc.c int val, val 192 drivers/iio/adc/spear_adc.c if ((val < SPEAR_ADC_CLK_MIN) || val 193 drivers/iio/adc/spear_adc.c (val > SPEAR_ADC_CLK_MAX) || val 199 drivers/iio/adc/spear_adc.c spear_adc_set_clk(st, val); val 129 drivers/iio/adc/stm32-adc-core.c u32 val; val 154 drivers/iio/adc/stm32-adc-core.c val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); val 155 drivers/iio/adc/stm32-adc-core.c val &= ~STM32F4_ADC_ADCPRE_MASK; val 156 drivers/iio/adc/stm32-adc-core.c val |= i << STM32F4_ADC_ADCPRE_SHIFT; val 157 drivers/iio/adc/stm32-adc-core.c writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); val 200 drivers/iio/adc/stm32-adc-core.c u32 ckmode, presc, val; val 266 drivers/iio/adc/stm32-adc-core.c val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); val 267 drivers/iio/adc/stm32-adc-core.c val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); val 268 drivers/iio/adc/stm32-adc-core.c val |= ckmode << STM32H7_CKMODE_SHIFT; val 269 drivers/iio/adc/stm32-adc-core.c val |= presc << STM32H7_PRESC_SHIFT; val 270 drivers/iio/adc/stm32-adc-core.c writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); val 457 drivers/iio/adc/stm32-adc.c #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ val 458 drivers/iio/adc/stm32-adc.c readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ val 466 drivers/iio/adc/stm32-adc.c static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) val 468 drivers/iio/adc/stm32-adc.c writel_relaxed(val, adc->common->base + adc->offset + reg); val 512 drivers/iio/adc/stm32-adc.c u32 val; val 514 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, res->reg); val 515 drivers/iio/adc/stm32-adc.c val = (val & ~res->mask) | (adc->res << res->shift); val 516 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, res->reg, val); val 602 drivers/iio/adc/stm32-adc.c u32 val; val 610 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); val 611 drivers/iio/adc/stm32-adc.c val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); val 612 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); val 622 drivers/iio/adc/stm32-adc.c u32 val; val 626 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, val 627 drivers/iio/adc/stm32-adc.c !(val & (STM32H7_ADSTART)), val 639 drivers/iio/adc/stm32-adc.c u32 val; val 654 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, val 655 drivers/iio/adc/stm32-adc.c val & STM32MP1_VREGREADY, 100, val 677 drivers/iio/adc/stm32-adc.c u32 val; val 682 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, val 683 drivers/iio/adc/stm32-adc.c val & STM32H7_ADRDY, val 700 drivers/iio/adc/stm32-adc.c u32 val; val 704 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, val 705 drivers/iio/adc/stm32-adc.c !(val & STM32H7_ADEN), 100, val 720 drivers/iio/adc/stm32-adc.c u32 lincalrdyw_mask, val; val 729 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, val 730 drivers/iio/adc/stm32-adc.c !(val & lincalrdyw_mask), val 737 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); val 738 drivers/iio/adc/stm32-adc.c adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); val 745 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); val 746 drivers/iio/adc/stm32-adc.c adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); val 748 drivers/iio/adc/stm32-adc.c adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); val 764 drivers/iio/adc/stm32-adc.c u32 lincalrdyw_mask, val; val 766 drivers/iio/adc/stm32-adc.c val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | val 768 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); val 777 drivers/iio/adc/stm32-adc.c val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; val 778 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); val 780 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, val 781 drivers/iio/adc/stm32-adc.c val & lincalrdyw_mask, val 796 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, val 797 drivers/iio/adc/stm32-adc.c !(val & lincalrdyw_mask), val 803 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); val 804 drivers/iio/adc/stm32-adc.c if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { val 837 drivers/iio/adc/stm32-adc.c u32 val; val 852 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, val 853 drivers/iio/adc/stm32-adc.c !(val & STM32H7_ADCAL), 100, val 869 drivers/iio/adc/stm32-adc.c ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, val 870 drivers/iio/adc/stm32-adc.c !(val & STM32H7_ADCAL), 100, val 957 drivers/iio/adc/stm32-adc.c u32 val, bit; val 977 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, sqr[i].reg); val 978 drivers/iio/adc/stm32-adc.c val &= ~sqr[i].mask; val 979 drivers/iio/adc/stm32-adc.c val |= chan->channel << sqr[i].shift; val 980 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, sqr[i].reg, val); val 987 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, sqr[0].reg); val 988 drivers/iio/adc/stm32-adc.c val &= ~sqr[0].mask; val 989 drivers/iio/adc/stm32-adc.c val |= ((i - 1) << sqr[0].shift); val 990 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, sqr[0].reg, val); val 1036 drivers/iio/adc/stm32-adc.c u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; val 1051 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); val 1052 drivers/iio/adc/stm32-adc.c val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); val 1053 drivers/iio/adc/stm32-adc.c val |= exten << adc->cfg->regs->exten.shift; val 1054 drivers/iio/adc/stm32-adc.c val |= extsel << adc->cfg->regs->extsel.shift; val 1055 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); val 1111 drivers/iio/adc/stm32-adc.c u32 val; val 1129 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, regs->sqr[1].reg); val 1130 drivers/iio/adc/stm32-adc.c val &= ~regs->sqr[1].mask; val 1131 drivers/iio/adc/stm32-adc.c val |= chan->channel << regs->sqr[1].shift; val 1132 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, regs->sqr[1].reg, val); val 1167 drivers/iio/adc/stm32-adc.c int *val, int *val2, long mask) val 1178 drivers/iio/adc/stm32-adc.c ret = stm32_adc_single_conv(indio_dev, chan, val); val 1186 drivers/iio/adc/stm32-adc.c *val = adc->common->vref_mv * 2; val 1189 drivers/iio/adc/stm32-adc.c *val = adc->common->vref_mv; val 1197 drivers/iio/adc/stm32-adc.c *val = -((1 << chan->scan_type.realbits) / 2); val 1199 drivers/iio/adc/stm32-adc.c *val = 0; val 1246 drivers/iio/adc/stm32-adc.c static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) val 1258 drivers/iio/adc/stm32-adc.c watermark = min(watermark, val * (unsigned)(sizeof(u16))); val 1666 drivers/iio/adc/stm32-adc.c u32 val, smp = 0; val 1709 drivers/iio/adc/stm32-adc.c of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { val 1710 drivers/iio/adc/stm32-adc.c if (val >= adc_info->max_channels) { val 1711 drivers/iio/adc/stm32-adc.c dev_err(&indio_dev->dev, "Invalid channel %d\n", val); val 1717 drivers/iio/adc/stm32-adc.c if (val == diff[i].vinp) { val 1719 drivers/iio/adc/stm32-adc.c "channel %d miss-configured\n", val); val 1723 drivers/iio/adc/stm32-adc.c stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, val 99 drivers/iio/adc/stm32-dfsdm-adc.c unsigned int val; val 131 drivers/iio/adc/stm32-dfsdm-adc.c return p->val; val 601 drivers/iio/adc/stm32-dfsdm-adc.c int ret, val; val 636 drivers/iio/adc/stm32-dfsdm-adc.c val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type); val 637 drivers/iio/adc/stm32-dfsdm-adc.c if (val < 0) val 638 drivers/iio/adc/stm32-dfsdm-adc.c return val; val 640 drivers/iio/adc/stm32-dfsdm-adc.c val = 0; val 642 drivers/iio/adc/stm32-dfsdm-adc.c df_ch->type = val; val 648 drivers/iio/adc/stm32-dfsdm-adc.c val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src); val 649 drivers/iio/adc/stm32-dfsdm-adc.c if (val < 0) val 650 drivers/iio/adc/stm32-dfsdm-adc.c return val; val 652 drivers/iio/adc/stm32-dfsdm-adc.c val = 0; val 654 drivers/iio/adc/stm32-dfsdm-adc.c df_ch->src = val; val 778 drivers/iio/adc/stm32-dfsdm-adc.c unsigned int val) val 790 drivers/iio/adc/stm32-dfsdm-adc.c watermark = min(watermark, val * (unsigned int)(sizeof(u32))); val 1195 drivers/iio/adc/stm32-dfsdm-adc.c int val, int val2, long mask) val 1207 drivers/iio/adc/stm32-dfsdm-adc.c ret = stm32_dfsdm_compute_all_osrs(indio_dev, val); val 1209 drivers/iio/adc/stm32-dfsdm-adc.c adc->oversamp = val; val 1214 drivers/iio/adc/stm32-dfsdm-adc.c if (!val) val 1233 drivers/iio/adc/stm32-dfsdm-adc.c ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq); val 1242 drivers/iio/adc/stm32-dfsdm-adc.c struct iio_chan_spec const *chan, int *val, val 1261 drivers/iio/adc/stm32-dfsdm-adc.c ret = stm32_dfsdm_single_conv(indio_dev, chan, val); val 1274 drivers/iio/adc/stm32-dfsdm-adc.c *val = adc->oversamp; val 1279 drivers/iio/adc/stm32-dfsdm-adc.c *val = adc->sample_freq; val 1556 drivers/iio/adc/stm32-dfsdm-adc.c int ret, irq, val; val 1607 drivers/iio/adc/stm32-dfsdm-adc.c ret = of_property_read_u32(dev->of_node, "st,filter-order", &val); val 1613 drivers/iio/adc/stm32-dfsdm-adc.c adc->dfsdm->fl_list[adc->fl_id].ford = val; val 1615 drivers/iio/adc/stm32-dfsdm-adc.c ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val); val 1617 drivers/iio/adc/stm32-dfsdm-adc.c adc->dfsdm->fl_list[adc->fl_id].sync_mode = val; val 62 drivers/iio/adc/stmpe-adc.c struct iio_chan_spec const *chan, int *val) val 89 drivers/iio/adc/stmpe-adc.c *val = info->value; val 97 drivers/iio/adc/stmpe-adc.c struct iio_chan_spec const *chan, int *val) val 126 drivers/iio/adc/stmpe-adc.c *val = ((449960l * info->value) / 1024l) - 273150; val 135 drivers/iio/adc/stmpe-adc.c int *val, val 148 drivers/iio/adc/stmpe-adc.c ret = stmpe_read_voltage(info, chan, val); val 152 drivers/iio/adc/stmpe-adc.c ret = stmpe_read_temp(info, chan, val); val 164 drivers/iio/adc/stmpe-adc.c *val = 3300; val 72 drivers/iio/adc/stx104.c struct iio_chan_spec const *chan, int *val, int *val2, long mask) val 85 drivers/iio/adc/stx104.c *val = 1 << gain; val 89 drivers/iio/adc/stx104.c *val = priv->chan_out_states[chan->channel]; val 100 drivers/iio/adc/stx104.c *val = inw(priv->base); val 107 drivers/iio/adc/stx104.c *val = -32768 * adbu; val 115 drivers/iio/adc/stx104.c *val = 5; val 124 drivers/iio/adc/stx104.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 131 drivers/iio/adc/stx104.c switch (val) { val 152 drivers/iio/adc/stx104.c if ((unsigned int)val > 65535) val 155 drivers/iio/adc/stx104.c priv->chan_out_states[chan->channel] = val; val 156 drivers/iio/adc/stx104.c outw(val, priv->base + 4 + 2 * chan->channel); val 220 drivers/iio/adc/sun4i-gpadc-iio.c static int sun4i_gpadc_read(struct iio_dev *indio_dev, int channel, int *val, val 247 drivers/iio/adc/sun4i-gpadc-iio.c *val = info->adc_data; val 249 drivers/iio/adc/sun4i-gpadc-iio.c *val = info->temp_data; val 263 drivers/iio/adc/sun4i-gpadc-iio.c int *val) val 267 drivers/iio/adc/sun4i-gpadc-iio.c return sun4i_gpadc_read(indio_dev, channel, val, info->fifo_data_irq); val 270 drivers/iio/adc/sun4i-gpadc-iio.c static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val) val 277 drivers/iio/adc/sun4i-gpadc-iio.c regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val); val 285 drivers/iio/adc/sun4i-gpadc-iio.c return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq); val 288 drivers/iio/adc/sun4i-gpadc-iio.c static int sun4i_gpadc_temp_offset(struct iio_dev *indio_dev, int *val) val 292 drivers/iio/adc/sun4i-gpadc-iio.c *val = info->data->temp_offset; val 297 drivers/iio/adc/sun4i-gpadc-iio.c static int sun4i_gpadc_temp_scale(struct iio_dev *indio_dev, int *val) val 301 drivers/iio/adc/sun4i-gpadc-iio.c *val = info->data->temp_scale; val 307 drivers/iio/adc/sun4i-gpadc-iio.c struct iio_chan_spec const *chan, int *val, val 314 drivers/iio/adc/sun4i-gpadc-iio.c ret = sun4i_gpadc_temp_offset(indio_dev, val); val 322 drivers/iio/adc/sun4i-gpadc-iio.c val); val 324 drivers/iio/adc/sun4i-gpadc-iio.c ret = sun4i_gpadc_temp_read(indio_dev, val); val 333 drivers/iio/adc/sun4i-gpadc-iio.c *val = 0; val 338 drivers/iio/adc/sun4i-gpadc-iio.c ret = sun4i_gpadc_temp_scale(indio_dev, val); val 418 drivers/iio/adc/sun4i-gpadc-iio.c int val, scale, offset; val 420 drivers/iio/adc/sun4i-gpadc-iio.c if (sun4i_gpadc_temp_read(info->indio_dev, &val)) val 426 drivers/iio/adc/sun4i-gpadc-iio.c *temp = (val + offset) * scale; val 85 drivers/iio/adc/ti-adc084s021.c struct iio_chan_spec const *channel, int *val, val 104 drivers/iio/adc/ti-adc084s021.c ret = adc084s021_adc_conversion(adc, val); val 110 drivers/iio/adc/ti-adc084s021.c *val = be16_to_cpu(*val); val 111 drivers/iio/adc/ti-adc084s021.c *val = (*val >> channel->scan_type.shift) & 0xff; val 124 drivers/iio/adc/ti-adc084s021.c *val = ret / 1000; val 176 drivers/iio/adc/ti-adc108s102.c int *val, int *val2, long m) val 194 drivers/iio/adc/ti-adc108s102.c *val = ADC108S102_RES_DATA(ret); val 201 drivers/iio/adc/ti-adc108s102.c *val = st->va_millivolt; val 60 drivers/iio/adc/ti-adc128s052.c struct iio_chan_spec const *channel, int *val, val 73 drivers/iio/adc/ti-adc128s052.c *val = ret; val 82 drivers/iio/adc/ti-adc128s052.c *val = ret / 1000; val 77 drivers/iio/adc/ti-adc161s626.c struct iio_chan_spec const *chan, int *val) val 89 drivers/iio/adc/ti-adc161s626.c *val = be16_to_cpu(buf); val 99 drivers/iio/adc/ti-adc161s626.c *val = be32_to_cpu(buf) >> 8; val 106 drivers/iio/adc/ti-adc161s626.c *val = sign_extend32(*val >> data->shift, chan->scan_type.realbits - 1); val 132 drivers/iio/adc/ti-adc161s626.c int *val, int *val2, long mask) val 143 drivers/iio/adc/ti-adc161s626.c ret = ti_adc_read_measurement(data, chan, val); val 155 drivers/iio/adc/ti-adc161s626.c *val = ret / 1000; val 160 drivers/iio/adc/ti-adc161s626.c *val = 1 << (chan->scan_type.realbits - 1); val 330 drivers/iio/adc/ti-ads1015.c int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) val 373 drivers/iio/adc/ti-ads1015.c return regmap_read(data->regmap, ADS1015_CONV_REG, val); val 440 drivers/iio/adc/ti-ads1015.c struct iio_chan_spec const *chan, int *val, val 465 drivers/iio/adc/ti-ads1015.c ret = ads1015_get_adc_result(data, chan->address, val); val 471 drivers/iio/adc/ti-ads1015.c *val = sign_extend32(*val >> shift, 15 - shift); val 484 drivers/iio/adc/ti-ads1015.c *val = ads1015_fullscale_range[idx]; val 490 drivers/iio/adc/ti-ads1015.c *val = data->data_rate[idx]; val 503 drivers/iio/adc/ti-ads1015.c struct iio_chan_spec const *chan, int val, val 512 drivers/iio/adc/ti-ads1015.c ret = ads1015_set_scale(data, chan, val, val2); val 515 drivers/iio/adc/ti-ads1015.c ret = ads1015_set_data_rate(data, chan->address, val); val 528 drivers/iio/adc/ti-ads1015.c enum iio_event_direction dir, enum iio_event_info info, int *val, val 541 drivers/iio/adc/ti-ads1015.c *val = (dir == IIO_EV_DIR_RISING) ? val 552 drivers/iio/adc/ti-ads1015.c *val = period / USEC_PER_SEC; val 568 drivers/iio/adc/ti-ads1015.c enum iio_event_direction dir, enum iio_event_info info, int val, val 582 drivers/iio/adc/ti-ads1015.c if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) { val 587 drivers/iio/adc/ti-ads1015.c data->thresh_data[chan->address].high_thresh = val; val 589 drivers/iio/adc/ti-ads1015.c data->thresh_data[chan->address].low_thresh = val; val 593 drivers/iio/adc/ti-ads1015.c period = val * USEC_PER_SEC + val2; val 644 drivers/iio/adc/ti-ads1015.c unsigned int val; val 675 drivers/iio/adc/ti-ads1015.c ret = ads1015_get_adc_result(data, chan->address, &val); val 744 drivers/iio/adc/ti-ads1015.c int val; val 748 drivers/iio/adc/ti-ads1015.c ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val); val 218 drivers/iio/adc/ti-ads124s08.c int *val, int *val2, long m) val 245 drivers/iio/adc/ti-ads124s08.c *val = ret; val 53 drivers/iio/adc/ti-ads7950.c #define TI_ADS7950_EXTRACT(val, dec, bits) \ val 54 drivers/iio/adc/ti-ads7950.c (((val) >> (dec)) & ((1 << (bits)) - 1)) val 369 drivers/iio/adc/ti-ads7950.c int *val, int *val2, long m) val 383 drivers/iio/adc/ti-ads7950.c *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift, val 392 drivers/iio/adc/ti-ads7950.c *val = ret; val 187 drivers/iio/adc/ti-ads8688.c unsigned int val) val 192 drivers/iio/adc/ti-ads8688.c tmp = ADS8688_PROG_REG(addr) | ADS8688_PROG_WR_BIT | val; val 245 drivers/iio/adc/ti-ads8688.c int *val, int *val2, long m) val 259 drivers/iio/adc/ti-ads8688.c *val = ret; val 264 drivers/iio/adc/ti-ads8688.c *val = 0; val 270 drivers/iio/adc/ti-ads8688.c *val = offset; val 294 drivers/iio/adc/ti-ads8688.c int val, int val2, long mask) val 324 drivers/iio/adc/ti-ads8688.c if (!(ads8688_range_def[0].offset == val || val 325 drivers/iio/adc/ti-ads8688.c ads8688_range_def[3].offset == val)) { val 334 drivers/iio/adc/ti-ads8688.c if (val == 0 && val 344 drivers/iio/adc/ti-ads8688.c if (val == ads8688_range_def[i].offset && val 124 drivers/iio/adc/ti-tlc4541.c int *val, val 140 drivers/iio/adc/ti-tlc4541.c *val = be16_to_cpu(st->rx_buf[0]); val 141 drivers/iio/adc/ti-tlc4541.c *val = *val >> chan->scan_type.shift; val 142 drivers/iio/adc/ti-tlc4541.c *val &= GENMASK(chan->scan_type.realbits - 1, 0); val 148 drivers/iio/adc/ti-tlc4541.c *val = ret; val 68 drivers/iio/adc/ti_am335x_adc.c unsigned int val) val 70 drivers/iio/adc/ti_am335x_adc.c writel(val, adc->mfd_tscadc->tscadc_base + reg); val 469 drivers/iio/adc/ti_am335x_adc.c int *val, int *val2, long mask) val 524 drivers/iio/adc/ti_am335x_adc.c *val = (u16) read; val 583 drivers/iio/adc/ti_am335x_adc.c u32 val; val 585 drivers/iio/adc/ti_am335x_adc.c of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { val 586 drivers/iio/adc/ti_am335x_adc.c adc_dev->channel_line[channels] = val; val 176 drivers/iio/adc/twl4030-madc.c int *val, int *val2, long mask) val 194 drivers/iio/adc/twl4030-madc.c *val = req.rbuf[chan->channel]; val 310 drivers/iio/adc/twl4030-madc.c u16 val; val 316 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_read_u16(TWL4030_MODULE_MADC, &val, reg); val 322 drivers/iio/adc/twl4030-madc.c return (int)(val >> 6); val 331 drivers/iio/adc/twl4030-madc.c u8 val; val 336 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, &val, val 341 drivers/iio/adc/twl4030-madc.c curr = ((val & TWL4030_BCI_ITHSENS) + 1) * 10; val 357 drivers/iio/adc/twl4030-madc.c u8 val; val 359 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, &val, val 363 drivers/iio/adc/twl4030-madc.c if (val & TWL4030_BCI_CGAIN) /* slope of 0.44 mV/mA */ val 450 drivers/iio/adc/twl4030-madc.c u8 val; val 453 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &val, madc->imr); val 459 drivers/iio/adc/twl4030-madc.c val |= (1 << id); val 460 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, val, madc->imr); val 340 drivers/iio/adc/twl6030-gpadc.c static inline int twl6030_gpadc_write(u8 reg, u8 val) val 342 drivers/iio/adc/twl6030-gpadc.c return twl_i2c_write_u8(TWL6030_MODULE_GPADC, val, reg); val 345 drivers/iio/adc/twl6030-gpadc.c static inline int twl6030_gpadc_read(u8 reg, u8 *val) val 348 drivers/iio/adc/twl6030-gpadc.c return twl_i2c_read(TWL6030_MODULE_GPADC, val, reg, 2); val 454 drivers/iio/adc/twl6030-gpadc.c __le16 val; val 458 drivers/iio/adc/twl6030-gpadc.c ret = twl6030_gpadc_read(reg, (u8 *)&val); val 464 drivers/iio/adc/twl6030-gpadc.c raw_code = le16_to_cpu(val); val 476 drivers/iio/adc/twl6030-gpadc.c int channel, int *val) val 498 drivers/iio/adc/twl6030-gpadc.c *val = channel_value; val 505 drivers/iio/adc/twl6030-gpadc.c int *val, int *val2, long mask) val 531 drivers/iio/adc/twl6030-gpadc.c ret = twl6030_gpadc_get_raw(gpadc, chan->channel, val); val 536 drivers/iio/adc/twl6030-gpadc.c ret = twl6030_gpadc_get_processed(gpadc, chan->channel, val); val 685 drivers/iio/adc/twl6030-gpadc.c int val; val 687 drivers/iio/adc/twl6030-gpadc.c val = (trim_regs[reg0] & mask0) << shift0; val 688 drivers/iio/adc/twl6030-gpadc.c val |= (trim_regs[reg1] & mask1) >> 1; val 690 drivers/iio/adc/twl6030-gpadc.c val = -val; val 692 drivers/iio/adc/twl6030-gpadc.c return val; val 624 drivers/iio/adc/vf610_adc.c int *val, val 658 drivers/iio/adc/vf610_adc.c *val = info->value; val 666 drivers/iio/adc/vf610_adc.c *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) * val 679 drivers/iio/adc/vf610_adc.c *val = info->vref_uv / 1000; val 684 drivers/iio/adc/vf610_adc.c *val = info->sample_freq_avail[info->adc_feature.sample_rate]; val 697 drivers/iio/adc/vf610_adc.c int val, val 709 drivers/iio/adc/vf610_adc.c if (val == info->sample_freq_avail[i]) { val 728 drivers/iio/adc/vf610_adc.c int val; val 734 drivers/iio/adc/vf610_adc.c val = readl(info->regs + VF610_REG_ADC_GC); val 735 drivers/iio/adc/vf610_adc.c val |= VF610_ADC_ADCON; val 736 drivers/iio/adc/vf610_adc.c writel(val, info->regs + VF610_REG_ADC_GC); val 741 drivers/iio/adc/vf610_adc.c val = VF610_ADC_ADCHC(channel); val 742 drivers/iio/adc/vf610_adc.c val |= VF610_ADC_AIEN; val 744 drivers/iio/adc/vf610_adc.c writel(val, info->regs + VF610_REG_ADC_HC0); val 753 drivers/iio/adc/vf610_adc.c int val; val 755 drivers/iio/adc/vf610_adc.c val = readl(info->regs + VF610_REG_ADC_GC); val 756 drivers/iio/adc/vf610_adc.c val &= ~VF610_ADC_ADCON; val 757 drivers/iio/adc/vf610_adc.c writel(val, info->regs + VF610_REG_ADC_GC); val 28 drivers/iio/adc/viperboard_adc.c u8 val; val 51 drivers/iio/adc/viperboard_adc.c int *val, val 66 drivers/iio/adc/viperboard_adc.c admsg->val = 0x00; val 82 drivers/iio/adc/viperboard_adc.c *val = admsg->val; val 116 drivers/iio/adc/xilinx-xadc-core.c uint32_t val) val 118 drivers/iio/adc/xilinx-xadc-core.c writel(val, xadc->base + reg); val 122 drivers/iio/adc/xilinx-xadc-core.c uint32_t *val) val 124 drivers/iio/adc/xilinx-xadc-core.c *val = readl(xadc->base + reg); val 159 drivers/iio/adc/xilinx-xadc-core.c unsigned int val) val 162 drivers/iio/adc/xilinx-xadc-core.c xadc->zynq_intmask |= val; val 169 drivers/iio/adc/xilinx-xadc-core.c uint16_t val) val 181 drivers/iio/adc/xilinx-xadc-core.c cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val); val 203 drivers/iio/adc/xilinx-xadc-core.c uint16_t *val) val 235 drivers/iio/adc/xilinx-xadc-core.c *val = resp & 0xffff; val 401 drivers/iio/adc/xilinx-xadc-core.c uint32_t val; val 403 drivers/iio/adc/xilinx-xadc-core.c xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val); val 405 drivers/iio/adc/xilinx-xadc-core.c switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) { val 453 drivers/iio/adc/xilinx-xadc-core.c uint16_t *val) val 458 drivers/iio/adc/xilinx-xadc-core.c *val = val32 & 0xffff; val 464 drivers/iio/adc/xilinx-xadc-core.c uint16_t val) val 466 drivers/iio/adc/xilinx-xadc-core.c xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val); val 519 drivers/iio/adc/xilinx-xadc-core.c uint32_t val; val 532 drivers/iio/adc/xilinx-xadc-core.c xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val); val 533 drivers/iio/adc/xilinx-xadc-core.c val &= ~XADC_AXI_INT_ALARM_MASK; val 534 drivers/iio/adc/xilinx-xadc-core.c val |= alarm; val 535 drivers/iio/adc/xilinx-xadc-core.c xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val); val 555 drivers/iio/adc/xilinx-xadc-core.c uint16_t mask, uint16_t val) val 564 drivers/iio/adc/xilinx-xadc-core.c return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val); val 568 drivers/iio/adc/xilinx-xadc-core.c uint16_t mask, uint16_t val) val 573 drivers/iio/adc/xilinx-xadc-core.c ret = _xadc_update_adc_reg(xadc, reg, mask, val); val 660 drivers/iio/adc/xilinx-xadc-core.c unsigned int val; val 686 drivers/iio/adc/xilinx-xadc-core.c xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val); val 689 drivers/iio/adc/xilinx-xadc-core.c val |= XADC_AXI_INT_EOS; val 691 drivers/iio/adc/xilinx-xadc-core.c val &= ~XADC_AXI_INT_EOS; val 692 drivers/iio/adc/xilinx-xadc-core.c xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val); val 733 drivers/iio/adc/xilinx-xadc-core.c uint16_t val; val 739 drivers/iio/adc/xilinx-xadc-core.c val = 0; val 742 drivers/iio/adc/xilinx-xadc-core.c val = XADC_CONF2_PD_ADC_B; val 747 drivers/iio/adc/xilinx-xadc-core.c val); val 865 drivers/iio/adc/xilinx-xadc-core.c struct iio_chan_spec const *chan, int *val, int *val2, long info) val 881 drivers/iio/adc/xilinx-xadc-core.c *val = val16; val 883 drivers/iio/adc/xilinx-xadc-core.c *val = sign_extend32(val16, 11); val 899 drivers/iio/adc/xilinx-xadc-core.c *val = 3000; val 902 drivers/iio/adc/xilinx-xadc-core.c *val = 1000; val 909 drivers/iio/adc/xilinx-xadc-core.c *val = 503975; val 917 drivers/iio/adc/xilinx-xadc-core.c *val = -((273150 << 12) / 503975); val 924 drivers/iio/adc/xilinx-xadc-core.c *val = ret; val 931 drivers/iio/adc/xilinx-xadc-core.c static int xadc_write_samplerate(struct xadc *xadc, int val) val 939 drivers/iio/adc/xilinx-xadc-core.c if (val <= 0) val 943 drivers/iio/adc/xilinx-xadc-core.c if (val > XADC_MAX_SAMPLERATE) val 944 drivers/iio/adc/xilinx-xadc-core.c val = XADC_MAX_SAMPLERATE; val 946 drivers/iio/adc/xilinx-xadc-core.c val *= 26; val 949 drivers/iio/adc/xilinx-xadc-core.c if (val < 1000000) val 950 drivers/iio/adc/xilinx-xadc-core.c val = 1000000; val 956 drivers/iio/adc/xilinx-xadc-core.c div = clk_rate / val; val 969 drivers/iio/adc/xilinx-xadc-core.c struct iio_chan_spec const *chan, int val, int val2, long info) val 976 drivers/iio/adc/xilinx-xadc-core.c return xadc_write_samplerate(xadc, val); val 164 drivers/iio/adc/xilinx-xadc-events.c int *val, int *val2) val 171 drivers/iio/adc/xilinx-xadc-events.c *val = xadc->threshold[offset]; val 174 drivers/iio/adc/xilinx-xadc-events.c *val = xadc->temp_hysteresis; val 180 drivers/iio/adc/xilinx-xadc-events.c *val >>= XADC_THRESHOLD_VALUE_SHIFT; val 188 drivers/iio/adc/xilinx-xadc-events.c int val, int val2) val 194 drivers/iio/adc/xilinx-xadc-events.c val <<= XADC_THRESHOLD_VALUE_SHIFT; val 196 drivers/iio/adc/xilinx-xadc-events.c if (val < 0 || val > 0xffff) val 203 drivers/iio/adc/xilinx-xadc-events.c xadc->threshold[offset] = val; val 206 drivers/iio/adc/xilinx-xadc-events.c xadc->temp_hysteresis = val; val 219 drivers/iio/adc/xilinx-xadc-events.c val |= 0x3; val 239 drivers/iio/adc/xilinx-xadc-events.c ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset), val); val 32 drivers/iio/adc/xilinx-xadc.h int *val, int *val2); val 36 drivers/iio/adc/xilinx-xadc.h int val, int val2); val 74 drivers/iio/adc/xilinx-xadc.h int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val); val 75 drivers/iio/adc/xilinx-xadc.h int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val); val 86 drivers/iio/adc/xilinx-xadc.h uint16_t *val) val 89 drivers/iio/adc/xilinx-xadc.h return xadc->ops->read(xadc, reg, val); val 93 drivers/iio/adc/xilinx-xadc.h uint16_t val) val 96 drivers/iio/adc/xilinx-xadc.h return xadc->ops->write(xadc, reg, val); val 100 drivers/iio/adc/xilinx-xadc.h uint16_t *val) val 105 drivers/iio/adc/xilinx-xadc.h ret = _xadc_read_adc_reg(xadc, reg, val); val 111 drivers/iio/adc/xilinx-xadc.h uint16_t val) val 116 drivers/iio/adc/xilinx-xadc.h ret = _xadc_write_adc_reg(xadc, reg, val); val 38 drivers/iio/afe/iio-rescale.c int *val, int *val2, long mask) val 46 drivers/iio/afe/iio-rescale.c return iio_read_channel_raw(rescale->source, val); val 49 drivers/iio/afe/iio-rescale.c ret = iio_read_channel_scale(rescale->source, val, val2); val 52 drivers/iio/afe/iio-rescale.c *val *= rescale->numerator; val 56 drivers/iio/afe/iio-rescale.c *val *= rescale->numerator; val 62 drivers/iio/afe/iio-rescale.c tmp = *val * 1000000000LL; val 66 drivers/iio/afe/iio-rescale.c *val = tmp; val 98 drivers/iio/amplifiers/ad8366.c int *val, val 124 drivers/iio/amplifiers/ad8366.c *val = gain / 1000; val 139 drivers/iio/amplifiers/ad8366.c int val, val 149 drivers/iio/amplifiers/ad8366.c if (val < 0) val 150 drivers/iio/amplifiers/ad8366.c gain = (val * 1000) - (val2 / 1000); val 152 drivers/iio/amplifiers/ad8366.c gain = (val * 1000) + (val2 / 1000); val 93 drivers/iio/chemical/ams-iaq-core.c struct iio_chan_spec const *chan, int *val, val 110 drivers/iio/chemical/ams-iaq-core.c *val = 0; val 115 drivers/iio/chemical/ams-iaq-core.c *val = be32_to_cpu(data->buffer.resistance); val 119 drivers/iio/chemical/ams-iaq-core.c *val = 0; val 180 drivers/iio/chemical/atlas-ph-sensor.c unsigned int val; val 182 drivers/iio/chemical/atlas-ph-sensor.c ret = regmap_read(data->regmap, ATLAS_REG_PH_CALIB_STATUS, &val); val 186 drivers/iio/chemical/atlas-ph-sensor.c if (!(val & ATLAS_REG_PH_CALIB_STATUS_MASK)) { val 191 drivers/iio/chemical/atlas-ph-sensor.c if (!(val & ATLAS_REG_PH_CALIB_STATUS_LOW)) val 194 drivers/iio/chemical/atlas-ph-sensor.c if (!(val & ATLAS_REG_PH_CALIB_STATUS_MID)) val 197 drivers/iio/chemical/atlas-ph-sensor.c if (!(val & ATLAS_REG_PH_CALIB_STATUS_HIGH)) val 207 drivers/iio/chemical/atlas-ph-sensor.c unsigned int val; val 214 drivers/iio/chemical/atlas-ph-sensor.c val = be16_to_cpu(rval); val 215 drivers/iio/chemical/atlas-ph-sensor.c dev_info(dev, "probe set to K = %d.%.2d", val / 100, val % 100); val 217 drivers/iio/chemical/atlas-ph-sensor.c ret = regmap_read(data->regmap, ATLAS_REG_EC_CALIB_STATUS, &val); val 221 drivers/iio/chemical/atlas-ph-sensor.c if (!(val & ATLAS_REG_EC_CALIB_STATUS_MASK)) { val 226 drivers/iio/chemical/atlas-ph-sensor.c if (!(val & ATLAS_REG_EC_CALIB_STATUS_DRY)) val 229 drivers/iio/chemical/atlas-ph-sensor.c if (val & ATLAS_REG_EC_CALIB_STATUS_SINGLE) { val 232 drivers/iio/chemical/atlas-ph-sensor.c if (!(val & ATLAS_REG_EC_CALIB_STATUS_LOW)) val 235 drivers/iio/chemical/atlas-ph-sensor.c if (!(val & ATLAS_REG_EC_CALIB_STATUS_HIGH)) val 246 drivers/iio/chemical/atlas-ph-sensor.c unsigned int val; val 248 drivers/iio/chemical/atlas-ph-sensor.c ret = regmap_read(data->regmap, ATLAS_REG_ORP_CALIB_STATUS, &val); val 252 drivers/iio/chemical/atlas-ph-sensor.c if (!val) val 383 drivers/iio/chemical/atlas-ph-sensor.c static int atlas_read_measurement(struct atlas_data *data, int reg, __be32 *val) val 398 drivers/iio/chemical/atlas-ph-sensor.c ret = regmap_bulk_read(data->regmap, reg, (u8 *) val, sizeof(*val)); val 408 drivers/iio/chemical/atlas-ph-sensor.c int *val, int *val2, long mask) val 439 drivers/iio/chemical/atlas-ph-sensor.c *val = be32_to_cpu(reg); val 447 drivers/iio/chemical/atlas-ph-sensor.c *val = 10; val 450 drivers/iio/chemical/atlas-ph-sensor.c *val = 1; /* 0.001 */ val 454 drivers/iio/chemical/atlas-ph-sensor.c *val = 1; /* 0.00001 */ val 458 drivers/iio/chemical/atlas-ph-sensor.c *val = 0; /* 0.000000001 */ val 462 drivers/iio/chemical/atlas-ph-sensor.c *val = 1; /* 0.1 */ val 476 drivers/iio/chemical/atlas-ph-sensor.c int val, int val2, long mask) val 479 drivers/iio/chemical/atlas-ph-sensor.c __be32 reg = cpu_to_be32(val / 10); val 481 drivers/iio/chemical/atlas-ph-sensor.c if (val2 != 0 || val < 0 || val > 20000) val 522 drivers/iio/chemical/bme680_core.c static u8 bme680_oversampling_to_reg(u8 val) val 524 drivers/iio/chemical/bme680_core.c return ilog2(val) + 1; val 604 drivers/iio/chemical/bme680_core.c static int bme680_read_temp(struct bme680_data *data, int *val) val 637 drivers/iio/chemical/bme680_core.c if (val) { val 638 drivers/iio/chemical/bme680_core.c *val = comp_temp * 10; /* Centidegrees to millidegrees */ val 646 drivers/iio/chemical/bme680_core.c int *val, int *val2) val 672 drivers/iio/chemical/bme680_core.c *val = bme680_compensate_press(data, adc_press); val 678 drivers/iio/chemical/bme680_core.c int *val, int *val2) val 706 drivers/iio/chemical/bme680_core.c *val = comp_humidity; val 712 drivers/iio/chemical/bme680_core.c int *val) val 766 drivers/iio/chemical/bme680_core.c *val = bme680_compensate_gas(data, adc_gas_res, gas_range); val 772 drivers/iio/chemical/bme680_core.c int *val, int *val2, long mask) val 780 drivers/iio/chemical/bme680_core.c return bme680_read_temp(data, val); val 782 drivers/iio/chemical/bme680_core.c return bme680_read_press(data, val, val2); val 784 drivers/iio/chemical/bme680_core.c return bme680_read_humid(data, val, val2); val 786 drivers/iio/chemical/bme680_core.c return bme680_read_gas(data, val); val 793 drivers/iio/chemical/bme680_core.c *val = data->oversampling_temp; val 796 drivers/iio/chemical/bme680_core.c *val = data->oversampling_press; val 799 drivers/iio/chemical/bme680_core.c *val = data->oversampling_humid; val 816 drivers/iio/chemical/bme680_core.c int val, int val2, long mask) val 826 drivers/iio/chemical/bme680_core.c if (!bme680_is_valid_oversampling(val)) val 831 drivers/iio/chemical/bme680_core.c data->oversampling_temp = val; val 834 drivers/iio/chemical/bme680_core.c data->oversampling_press = val; val 837 drivers/iio/chemical/bme680_core.c data->oversampling_humid = val; val 886 drivers/iio/chemical/bme680_core.c unsigned int val; val 896 drivers/iio/chemical/bme680_core.c ret = regmap_read(regmap, BME680_REG_CHIP_ID, &val); val 902 drivers/iio/chemical/bme680_core.c if (val != BME680_CHIP_ID_VAL) { val 904 drivers/iio/chemical/bme680_core.c val, BME680_CHIP_ID_VAL); val 88 drivers/iio/chemical/bme680_spi.c size_t reg_size, void *val, size_t val_size) val 101 drivers/iio/chemical/bme680_spi.c return spi_write_then_read(spi, &addr, 1, val, val_size); val 193 drivers/iio/chemical/ccs811.c int *val, int *val2, long mask) val 213 drivers/iio/chemical/ccs811.c *val = be16_to_cpu(data->buffer.raw_data) & val 218 drivers/iio/chemical/ccs811.c *val = be16_to_cpu(data->buffer.raw_data) >> 10; val 224 drivers/iio/chemical/ccs811.c *val = be16_to_cpu(data->buffer.co2); val 228 drivers/iio/chemical/ccs811.c *val = be16_to_cpu(data->buffer.voc); val 246 drivers/iio/chemical/ccs811.c *val = 1; val 250 drivers/iio/chemical/ccs811.c *val = 0; val 256 drivers/iio/chemical/ccs811.c *val = 0; val 260 drivers/iio/chemical/ccs811.c *val = 0; val 139 drivers/iio/chemical/pms7003.c int *val, int *val2, long mask) val 156 drivers/iio/chemical/pms7003.c *val = pms7003_get_pm(frame->data + chan->address); val 334 drivers/iio/chemical/sgp30.c struct iio_chan_spec const *chan, int *val, val 352 drivers/iio/chemical/sgp30.c *val = 0; val 357 drivers/iio/chemical/sgp30.c *val = 0; val 388 drivers/iio/chemical/sgp30.c *val = be16_to_cpu(words[1].value); val 393 drivers/iio/chemical/sgp30.c *val = be16_to_cpu(words[0].value); val 162 drivers/iio/chemical/sps30.c int val = get_unaligned_be32(fp); val 163 drivers/iio/chemical/sps30.c int mantissa = val & GENMASK(22, 0); val 165 drivers/iio/chemical/sps30.c int exp = val >> 23; val 180 drivers/iio/chemical/sps30.c val = (1 << exp) + (mantissa >> shift); val 181 drivers/iio/chemical/sps30.c if (val >= SPS30_MAX_PM) val 186 drivers/iio/chemical/sps30.c return val * 100 + ((fraction * 100) >> shift); val 254 drivers/iio/chemical/sps30.c int *val, int *val2, long mask) val 283 drivers/iio/chemical/sps30.c *val = data[chan->address] / 100; val 298 drivers/iio/chemical/sps30.c *val = 0; val 337 drivers/iio/chemical/sps30.c int val, ret; val 339 drivers/iio/chemical/sps30.c if (kstrtoint(buf, 0, &val) || val != 1) val 375 drivers/iio/chemical/sps30.c int val, ret; val 378 drivers/iio/chemical/sps30.c if (kstrtoint(buf, 0, &val)) val 381 drivers/iio/chemical/sps30.c if ((val < SPS30_AUTO_CLEANING_PERIOD_MIN) || val 382 drivers/iio/chemical/sps30.c (val > SPS30_AUTO_CLEANING_PERIOD_MAX)) val 385 drivers/iio/chemical/sps30.c put_unaligned_be32(val, tmp); val 244 drivers/iio/chemical/vz89x.c int *val) val 250 drivers/iio/chemical/vz89x.c *val = le32_to_cpup((__le32 *) tmp) & GENMASK(23, 0); val 253 drivers/iio/chemical/vz89x.c *val = be32_to_cpup((__be32 *) tmp) >> 8; val 263 drivers/iio/chemical/vz89x.c struct iio_chan_spec const *chan, int *val, val 280 drivers/iio/chemical/vz89x.c *val = data->buffer[chan->address]; val 283 drivers/iio/chemical/vz89x.c ret = vz89x_get_resistance_reading(data, chan, val); val 294 drivers/iio/chemical/vz89x.c *val = 10; val 303 drivers/iio/chemical/vz89x.c *val = 44; val 307 drivers/iio/chemical/vz89x.c *val = -13; val 69 drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c int *val, int *val2, long mask) val 78 drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c *val = data; val 38 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c int *val, int *val2, long mask) val 55 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c *val = data; val 70 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c *val = st->core.calib[idx].offset; val 79 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c *val = 1; val 92 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c *val = st->core.calib[idx].scale >> 15; val 112 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c *val = div_s64(val64 * 980665, 10); val 122 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c *val = 0; val 132 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c *val = val64; val 141 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c ret = cros_ec_sensors_core_read(&st->core, chan, val, val2, val 152 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c int val, int val2, long mask) val 163 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c st->core.calib[idx].offset = val; val 178 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c st->core.calib[idx].scale = val; val 198 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c st->core.param.sensor_range.data = val; val 207 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c &st->core, chan, val, val2, mask); val 484 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c int *val, int *val2, long mask) val 498 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c *val = st->resp->ec_rate.ret; val 510 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c *val = st->resp->sensor_odr.ret; val 545 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c int val, int val2, long mask) val 552 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c st->param.sensor_odr.data = val; val 561 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c st->param.ec_rate.data = val; val 566 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c st->curr_sampl_freq = val; val 117 drivers/iio/common/hid-sensors/hid-sensor-trigger.c int val; val 119 drivers/iio/common/hid-sensors/hid-sensor-trigger.c val = atomic_dec_if_positive(&st->data_ready); val 120 drivers/iio/common/hid-sensors/hid-sensor-trigger.c if (val < 0) val 373 drivers/iio/common/ms_sensors/ms_sensors_i2c.c u8 val, config_reg; val 376 drivers/iio/common/ms_sensors/ms_sensors_i2c.c ret = kstrtou8(buf, 10, &val); val 380 drivers/iio/common/ms_sensors/ms_sensors_i2c.c if (val > 1) val 391 drivers/iio/common/ms_sensors/ms_sensors_i2c.c config_reg |= val << 2; val 123 drivers/iio/common/ssp_sensors/ssp_spi.c #define SSP_SET_BUFFER_AT_INDEX(m, index, val) \ val 124 drivers/iio/common/ssp_sensors/ssp_spi.c (m->buffer[SSP_HEADER_SIZE_ALIGNED + index] = val) val 328 drivers/iio/common/st_sensors/st_sensors_core.c u32 val; val 334 drivers/iio/common/st_sensors/st_sensors_core.c if (!of_property_read_u32(np, "st,drdy-int-pin", &val) && (val <= 2)) val 335 drivers/iio/common/st_sensors/st_sensors_core.c pdata->drdy_int_pin = (u8) val; val 568 drivers/iio/common/st_sensors/st_sensors_core.c struct iio_chan_spec const *ch, int *val) val 583 drivers/iio/common/st_sensors/st_sensors_core.c err = st_sensors_read_axis_data(indio_dev, ch, val); val 587 drivers/iio/common/st_sensors/st_sensors_core.c *val = *val >> ch->scan_type.shift; val 88 drivers/iio/dac/ad5064.c unsigned int addr, unsigned int val); val 193 drivers/iio/dac/ad5064.c unsigned int addr, unsigned int val, unsigned int shift) val 195 drivers/iio/dac/ad5064.c val <<= shift; val 197 drivers/iio/dac/ad5064.c return st->write(st, cmd, addr, val); val 203 drivers/iio/dac/ad5064.c unsigned int val, address; val 208 drivers/iio/dac/ad5064.c val = 0; val 216 drivers/iio/dac/ad5064.c val = (0x1 << chan->address); val 220 drivers/iio/dac/ad5064.c val |= st->pwr_down_mode[chan->channel] << shift; val 223 drivers/iio/dac/ad5064.c ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, address, val, 0); val 317 drivers/iio/dac/ad5064.c int *val, val 326 drivers/iio/dac/ad5064.c *val = st->dac_cache[chan->channel]; val 333 drivers/iio/dac/ad5064.c *val = scale_uv / 1000; val 343 drivers/iio/dac/ad5064.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 350 drivers/iio/dac/ad5064.c if (val >= (1 << chan->scan_type.realbits) || val < 0) val 355 drivers/iio/dac/ad5064.c chan->address, val, chan->scan_type.shift); val 357 drivers/iio/dac/ad5064.c st->dac_cache[chan->channel] = val; val 796 drivers/iio/dac/ad5064.c static int ad5064_set_config(struct ad5064_state *st, unsigned int val) val 809 drivers/iio/dac/ad5064.c return ad5064_write(st, cmd, 0, val, 0); val 920 drivers/iio/dac/ad5064.c unsigned int addr, unsigned int val) val 924 drivers/iio/dac/ad5064.c st->data.spi = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val); val 991 drivers/iio/dac/ad5064.c unsigned int addr, unsigned int val) val 1007 drivers/iio/dac/ad5064.c put_unaligned_be16(val, &st->data.i2c[1]); val 192 drivers/iio/dac/ad5360.c unsigned int cmd, unsigned int addr, unsigned int val, val 197 drivers/iio/dac/ad5360.c val <<= shift; val 198 drivers/iio/dac/ad5360.c val |= AD5360_CMD(cmd) | AD5360_ADDR(addr); val 199 drivers/iio/dac/ad5360.c st->data[0].d32 = cpu_to_be32(val); val 205 drivers/iio/dac/ad5360.c unsigned int addr, unsigned int val, unsigned int shift) val 210 drivers/iio/dac/ad5360.c ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift); val 312 drivers/iio/dac/ad5360.c int val, val 322 drivers/iio/dac/ad5360.c if (val >= max_val || val < 0) val 326 drivers/iio/dac/ad5360.c chan->address, val, chan->scan_type.shift); val 329 drivers/iio/dac/ad5360.c if (val >= max_val || val < 0) val 333 drivers/iio/dac/ad5360.c chan->address, val, chan->scan_type.shift); val 336 drivers/iio/dac/ad5360.c if (val >= max_val || val < 0) val 340 drivers/iio/dac/ad5360.c chan->address, val, chan->scan_type.shift); val 343 drivers/iio/dac/ad5360.c if (val <= -max_val || val > 0) val 346 drivers/iio/dac/ad5360.c val = -val; val 351 drivers/iio/dac/ad5360.c val >>= (chan->scan_type.realbits - 14); val 358 drivers/iio/dac/ad5360.c AD5360_REG_SF_OFS(ofs_index), val, 0); val 368 drivers/iio/dac/ad5360.c int *val, val 383 drivers/iio/dac/ad5360.c *val = ret >> chan->scan_type.shift; val 391 drivers/iio/dac/ad5360.c *val = scale_uv * 4 / 1000; val 399 drivers/iio/dac/ad5360.c *val = ret; val 406 drivers/iio/dac/ad5360.c *val = ret; val 416 drivers/iio/dac/ad5360.c *val = -ret; val 174 drivers/iio/dac/ad5380.c struct iio_chan_spec const *chan, int val, int val2, long info) val 182 drivers/iio/dac/ad5380.c if (val >= max_val || val < 0) val 187 drivers/iio/dac/ad5380.c val << chan->scan_type.shift); val 189 drivers/iio/dac/ad5380.c val += (1 << chan->scan_type.realbits) / 2; val 190 drivers/iio/dac/ad5380.c if (val >= max_val || val < 0) val 195 drivers/iio/dac/ad5380.c val << chan->scan_type.shift); val 203 drivers/iio/dac/ad5380.c struct iio_chan_spec const *chan, int *val, int *val2, long info) val 212 drivers/iio/dac/ad5380.c val); val 215 drivers/iio/dac/ad5380.c *val >>= chan->scan_type.shift; val 219 drivers/iio/dac/ad5380.c val); val 222 drivers/iio/dac/ad5380.c *val >>= chan->scan_type.shift; val 223 drivers/iio/dac/ad5380.c *val -= (1 << chan->scan_type.realbits) / 2; val 226 drivers/iio/dac/ad5380.c *val = 2 * st->vref; val 133 drivers/iio/dac/ad5421.c unsigned int reg, unsigned int val) val 137 drivers/iio/dac/ad5421.c st->data[0].d32 = cpu_to_be32((reg << 16) | val); val 143 drivers/iio/dac/ad5421.c unsigned int val) val 148 drivers/iio/dac/ad5421.c ret = ad5421_write_unlocked(indio_dev, reg, val); val 312 drivers/iio/dac/ad5421.c struct iio_chan_spec const *chan, int *val, int *val2, long m) val 326 drivers/iio/dac/ad5421.c *val = ret; val 330 drivers/iio/dac/ad5421.c *val = max - min; val 334 drivers/iio/dac/ad5421.c *val = ad5421_get_offset(st); val 340 drivers/iio/dac/ad5421.c *val = ret - 32768; val 346 drivers/iio/dac/ad5421.c *val = ret; val 354 drivers/iio/dac/ad5421.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 360 drivers/iio/dac/ad5421.c if (val >= max_val || val < 0) val 363 drivers/iio/dac/ad5421.c return ad5421_write(indio_dev, AD5421_REG_DAC_DATA, val); val 365 drivers/iio/dac/ad5421.c val += 32768; val 366 drivers/iio/dac/ad5421.c if (val >= max_val || val < 0) val 369 drivers/iio/dac/ad5421.c return ad5421_write(indio_dev, AD5421_REG_OFFSET, val); val 371 drivers/iio/dac/ad5421.c if (val >= max_val || val < 0) val 374 drivers/iio/dac/ad5421.c return ad5421_write(indio_dev, AD5421_REG_GAIN, val); val 439 drivers/iio/dac/ad5421.c enum iio_event_direction dir, enum iio_event_info info, int *val, val 449 drivers/iio/dac/ad5421.c *val = ret; val 452 drivers/iio/dac/ad5421.c *val = 140000; val 56 drivers/iio/dac/ad5446.c int (*write)(struct ad5446_state *st, unsigned val); val 105 drivers/iio/dac/ad5446.c unsigned int val; val 118 drivers/iio/dac/ad5446.c val = st->pwr_down_mode << shift; val 120 drivers/iio/dac/ad5446.c val = st->cached_val; val 123 drivers/iio/dac/ad5446.c ret = st->chip_info->write(st, val); val 165 drivers/iio/dac/ad5446.c int *val, val 173 drivers/iio/dac/ad5446.c *val = st->cached_val; val 176 drivers/iio/dac/ad5446.c *val = st->vref_mv; val 185 drivers/iio/dac/ad5446.c int val, val 194 drivers/iio/dac/ad5446.c if (val >= (1 << chan->scan_type.realbits) || val < 0) val 197 drivers/iio/dac/ad5446.c val <<= chan->scan_type.shift; val 199 drivers/iio/dac/ad5446.c st->cached_val = val; val 201 drivers/iio/dac/ad5446.c ret = st->chip_info->write(st, val); val 292 drivers/iio/dac/ad5446.c static int ad5446_write(struct ad5446_state *st, unsigned val) val 295 drivers/iio/dac/ad5446.c __be16 data = cpu_to_be16(val); val 300 drivers/iio/dac/ad5446.c static int ad5660_write(struct ad5446_state *st, unsigned val) val 305 drivers/iio/dac/ad5446.c data[0] = (val >> 16) & 0xFF; val 306 drivers/iio/dac/ad5446.c data[1] = (val >> 8) & 0xFF; val 307 drivers/iio/dac/ad5446.c data[2] = val & 0xFF; val 526 drivers/iio/dac/ad5446.c static int ad5622_write(struct ad5446_state *st, unsigned val) val 529 drivers/iio/dac/ad5446.c __be16 data = cpu_to_be16(val); val 85 drivers/iio/dac/ad5449.c unsigned int val) val 91 drivers/iio/dac/ad5449.c st->data[0] = cpu_to_be16((addr << 12) | val); val 99 drivers/iio/dac/ad5449.c unsigned int *val) val 123 drivers/iio/dac/ad5449.c *val = be16_to_cpu(st->data[1]); val 131 drivers/iio/dac/ad5449.c struct iio_chan_spec const *chan, int *val, int *val2, long info) val 142 drivers/iio/dac/ad5449.c AD5449_CMD_READ(chan->address), val); val 145 drivers/iio/dac/ad5449.c *val &= 0xfff; val 147 drivers/iio/dac/ad5449.c *val = st->dac_cache[chan->address]; val 157 drivers/iio/dac/ad5449.c *val = scale_uv / 1000; val 169 drivers/iio/dac/ad5449.c struct iio_chan_spec const *chan, int val, int val2, long info) val 176 drivers/iio/dac/ad5449.c if (val < 0 || val >= (1 << chan->scan_type.realbits)) val 181 drivers/iio/dac/ad5449.c val << chan->scan_type.shift); val 183 drivers/iio/dac/ad5449.c st->dac_cache[chan->address] = val; val 69 drivers/iio/dac/ad5504.c static int ad5504_spi_write(struct ad5504_state *st, u8 addr, u16 val) val 72 drivers/iio/dac/ad5504.c (val & AD5504_RES_MASK)); val 96 drivers/iio/dac/ad5504.c int *val, val 109 drivers/iio/dac/ad5504.c *val = ret; val 113 drivers/iio/dac/ad5504.c *val = st->vref_mv; val 122 drivers/iio/dac/ad5504.c int val, val 130 drivers/iio/dac/ad5504.c if (val >= (1 << chan->scan_type.realbits) || val < 0) val 133 drivers/iio/dac/ad5504.c return ad5504_spi_write(st, chan->address, val); val 29 drivers/iio/dac/ad5592r-base.c u8 val; val 34 drivers/iio/dac/ad5592r-base.c val = st->gpio_val; val 36 drivers/iio/dac/ad5592r-base.c ret = st->ops->gpio_read(st, &val); val 43 drivers/iio/dac/ad5592r-base.c return !!(val & BIT(offset)); val 304 drivers/iio/dac/ad5592r-base.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 312 drivers/iio/dac/ad5592r-base.c if (val >= (1 << chan->scan_type.realbits) || val < 0) val 319 drivers/iio/dac/ad5592r-base.c ret = st->ops->write_dac(st, chan->channel, val); val 321 drivers/iio/dac/ad5592r-base.c st->cached_dac[chan->channel] = val; val 328 drivers/iio/dac/ad5592r-base.c if (val == st->scale_avail[0][0] && val 331 drivers/iio/dac/ad5592r-base.c else if (val == st->scale_avail[1][0] && val 378 drivers/iio/dac/ad5592r-base.c int *val, int *val2, long m) val 409 drivers/iio/dac/ad5592r-base.c *val = (int) read_val; val 413 drivers/iio/dac/ad5592r-base.c *val = ad5592r_get_vref(st); val 416 drivers/iio/dac/ad5592r-base.c s64 tmp = *val * (3767897513LL / 25LL); val 417 drivers/iio/dac/ad5592r-base.c *val = div_s64_rem(tmp, 1000000000LL, val2); val 432 drivers/iio/dac/ad5592r-base.c *val *= ++mult; val 444 drivers/iio/dac/ad5592r-base.c *val = (-34365 * 25) / ret; val 446 drivers/iio/dac/ad5592r-base.c *val = (-75365 * 25) / ret; val 35 drivers/iio/dac/ad5593r.c s32 val; val 37 drivers/iio/dac/ad5593r.c val = i2c_smbus_write_word_swapped(i2c, val 39 drivers/iio/dac/ad5593r.c if (val < 0) val 40 drivers/iio/dac/ad5593r.c return (int) val; val 42 drivers/iio/dac/ad5593r.c val = i2c_smbus_read_word_swapped(i2c, AD5593R_MODE_ADC_READBACK); val 43 drivers/iio/dac/ad5593r.c if (val < 0) val 44 drivers/iio/dac/ad5593r.c return (int) val; val 46 drivers/iio/dac/ad5593r.c *value = (u16) val; val 62 drivers/iio/dac/ad5593r.c s32 val; val 64 drivers/iio/dac/ad5593r.c val = i2c_smbus_read_word_swapped(i2c, AD5593R_MODE_REG_READBACK | reg); val 65 drivers/iio/dac/ad5593r.c if (val < 0) val 66 drivers/iio/dac/ad5593r.c return (int) val; val 68 drivers/iio/dac/ad5593r.c *value = (u16) val; val 76 drivers/iio/dac/ad5593r.c s32 val; val 78 drivers/iio/dac/ad5593r.c val = i2c_smbus_read_word_swapped(i2c, AD5593R_MODE_GPIO_READBACK); val 79 drivers/iio/dac/ad5593r.c if (val < 0) val 80 drivers/iio/dac/ad5593r.c return (int) val; val 82 drivers/iio/dac/ad5593r.c *value = (u8) val; val 24 drivers/iio/dac/ad5624r_spi.c u8 cmd, u8 addr, u16 val, u8 shift) val 37 drivers/iio/dac/ad5624r_spi.c data = (0 << 22) | (cmd << 19) | (addr << 16) | (val << shift); val 47 drivers/iio/dac/ad5624r_spi.c int *val, val 55 drivers/iio/dac/ad5624r_spi.c *val = st->vref_mv; val 64 drivers/iio/dac/ad5624r_spi.c int val, val 72 drivers/iio/dac/ad5624r_spi.c if (val >= (1 << chan->scan_type.realbits) || val < 0) val 77 drivers/iio/dac/ad5624r_spi.c chan->address, val, val 17 drivers/iio/dac/ad5686-spi.c u8 cmd, u8 addr, u16 val) val 25 drivers/iio/dac/ad5686-spi.c val); val 31 drivers/iio/dac/ad5686-spi.c AD5683_DATA(val)); val 38 drivers/iio/dac/ad5686-spi.c val); val 73 drivers/iio/dac/ad5686.c unsigned int val, ref_bit_msk; val 109 drivers/iio/dac/ad5686.c val = ((st->pwr_down_mask & st->pwr_down_mode) << shift); val 111 drivers/iio/dac/ad5686.c val |= ref_bit_msk; val 114 drivers/iio/dac/ad5686.c address, val >> (address * 2)); val 121 drivers/iio/dac/ad5686.c int *val, val 135 drivers/iio/dac/ad5686.c *val = (ret >> chan->scan_type.shift) & val 139 drivers/iio/dac/ad5686.c *val = st->vref_mv; val 148 drivers/iio/dac/ad5686.c int val, val 157 drivers/iio/dac/ad5686.c if (val > (1 << chan->scan_type.realbits) || val < 0) val 164 drivers/iio/dac/ad5686.c val << chan->scan_type.shift); val 425 drivers/iio/dac/ad5686.c unsigned int val, ref_bit_msk; val 496 drivers/iio/dac/ad5686.c val = (voltage_uv | ref_bit_msk); val 498 drivers/iio/dac/ad5686.c ret = st->write(st, cmd, 0, !!val); val 92 drivers/iio/dac/ad5686.h u8 cmd, u8 addr, u16 val); val 46 drivers/iio/dac/ad5696-i2c.c u8 cmd, u8 addr, u16 val) val 52 drivers/iio/dac/ad5696-i2c.c | val); val 158 drivers/iio/dac/ad5755.c unsigned int reg, unsigned int val) val 162 drivers/iio/dac/ad5755.c st->data[0].d32 = cpu_to_be32((reg << 16) | val); val 168 drivers/iio/dac/ad5755.c unsigned int channel, unsigned int reg, unsigned int val) val 171 drivers/iio/dac/ad5755.c AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val); val 175 drivers/iio/dac/ad5755.c unsigned int val) val 180 drivers/iio/dac/ad5755.c ret = ad5755_write_unlocked(indio_dev, reg, val); val 187 drivers/iio/dac/ad5755.c unsigned int reg, unsigned int val) val 192 drivers/iio/dac/ad5755.c ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val); val 338 drivers/iio/dac/ad5755.c const struct iio_chan_spec *chan, int *val, int *val2, long info) val 348 drivers/iio/dac/ad5755.c *val = max - min; val 352 drivers/iio/dac/ad5755.c *val = ad5755_get_offset(st, chan); val 364 drivers/iio/dac/ad5755.c *val = (ret - offset) >> shift; val 373 drivers/iio/dac/ad5755.c const struct iio_chan_spec *chan, int val, int val2, long info) val 384 drivers/iio/dac/ad5755.c val <<= shift; val 385 drivers/iio/dac/ad5755.c val += offset; val 387 drivers/iio/dac/ad5755.c if (val < 0 || val > 0xffff) val 390 drivers/iio/dac/ad5755.c return ad5755_write(indio_dev, reg, val); val 492 drivers/iio/dac/ad5755.c unsigned int val; val 501 drivers/iio/dac/ad5755.c val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV; val 502 drivers/iio/dac/ad5755.c val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT; val 503 drivers/iio/dac/ad5755.c val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT; val 505 drivers/iio/dac/ad5755.c val |= AD5755_EXT_DC_DC_COMP_RES; val 507 drivers/iio/dac/ad5755.c ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val); val 512 drivers/iio/dac/ad5755.c val = pdata->dac[i].slew.step_size << val 514 drivers/iio/dac/ad5755.c val |= pdata->dac[i].slew.rate << val 517 drivers/iio/dac/ad5755.c val |= AD5755_SLEW_ENABLE; val 520 drivers/iio/dac/ad5755.c AD5755_CTRL_REG_SLEW, val); val 529 drivers/iio/dac/ad5755.c val = 0; val 531 drivers/iio/dac/ad5755.c val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR; val 533 drivers/iio/dac/ad5755.c val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN; val 534 drivers/iio/dac/ad5755.c val |= pdata->dac[i].mode; val 536 drivers/iio/dac/ad5755.c ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0); val 216 drivers/iio/dac/ad5758.c unsigned int val) val 219 drivers/iio/dac/ad5758.c ((val & 0xFFFF) << 8)); val 227 drivers/iio/dac/ad5758.c unsigned int val) val 236 drivers/iio/dac/ad5758.c regval |= val; val 247 drivers/iio/dac/ad5758.c unsigned int size, int val) val 252 drivers/iio/dac/ad5758.c if (val <= array[i]) val 521 drivers/iio/dac/ad5758.c int *val, int *val2, long info) val 534 drivers/iio/dac/ad5758.c *val = ret; val 539 drivers/iio/dac/ad5758.c *val = (max - min) / 1000; val 545 drivers/iio/dac/ad5758.c *val = ((min * (1 << 16)) / (max - min)) / 1000; val 554 drivers/iio/dac/ad5758.c int val, int val2, long info) val 562 drivers/iio/dac/ad5758.c ret = ad5758_spi_reg_write(st, AD5758_DAC_INPUT, val); val 587 drivers/iio/dac/ad5758.c unsigned int dac_config_mode, val; val 597 drivers/iio/dac/ad5758.c val = 0; val 599 drivers/iio/dac/ad5758.c val = 1; val 601 drivers/iio/dac/ad5758.c dac_config_mode = AD5758_DAC_CONFIG_OUT_EN_MODE(val) | val 602 drivers/iio/dac/ad5758.c AD5758_DAC_CONFIG_INT_EN_MODE(val); val 115 drivers/iio/dac/ad5761.c static int _ad5761_spi_write(struct ad5761_state *st, u8 addr, u16 val) val 117 drivers/iio/dac/ad5761.c st->data[0].d32 = cpu_to_be32(AD5761_ADDR(addr) | val); val 122 drivers/iio/dac/ad5761.c static int ad5761_spi_write(struct iio_dev *indio_dev, u8 addr, u16 val) val 128 drivers/iio/dac/ad5761.c ret = _ad5761_spi_write(st, addr, val); val 134 drivers/iio/dac/ad5761.c static int _ad5761_spi_read(struct ad5761_state *st, u8 addr, u16 *val) val 156 drivers/iio/dac/ad5761.c *val = be32_to_cpu(st->data[2].d32); val 161 drivers/iio/dac/ad5761.c static int ad5761_spi_read(struct iio_dev *indio_dev, u8 addr, u16 *val) val 167 drivers/iio/dac/ad5761.c ret = _ad5761_spi_read(st, addr, val); val 199 drivers/iio/dac/ad5761.c int *val, val 212 drivers/iio/dac/ad5761.c *val = aux >> chan->scan_type.shift; val 216 drivers/iio/dac/ad5761.c *val = st->vref * ad5761_range_params[st->range].m; val 217 drivers/iio/dac/ad5761.c *val /= 10; val 222 drivers/iio/dac/ad5761.c *val = -(1 << chan->scan_type.realbits); val 223 drivers/iio/dac/ad5761.c *val *= ad5761_range_params[st->range].c; val 224 drivers/iio/dac/ad5761.c *val /= ad5761_range_params[st->range].m; val 233 drivers/iio/dac/ad5761.c int val, val 242 drivers/iio/dac/ad5761.c if (val2 || (val << chan->scan_type.shift) > 0xffff || val < 0) val 245 drivers/iio/dac/ad5761.c aux = val << chan->scan_type.shift; val 124 drivers/iio/dac/ad5764.c unsigned int val) val 130 drivers/iio/dac/ad5764.c st->data[0].d32 = cpu_to_be32((reg << 16) | val); val 139 drivers/iio/dac/ad5764.c unsigned int *val) val 160 drivers/iio/dac/ad5764.c *val = be32_to_cpu(st->data[1].d32) & 0xffff; val 184 drivers/iio/dac/ad5764.c struct iio_chan_spec const *chan, int val, int val2, long info) val 191 drivers/iio/dac/ad5764.c if (val >= max_val || val < 0) val 193 drivers/iio/dac/ad5764.c val <<= chan->scan_type.shift; val 196 drivers/iio/dac/ad5764.c if (val >= 128 || val < -128) val 200 drivers/iio/dac/ad5764.c if (val >= 32 || val < -32) val 208 drivers/iio/dac/ad5764.c return ad5764_write(indio_dev, reg, (u16)val); val 221 drivers/iio/dac/ad5764.c struct iio_chan_spec const *chan, int *val, int *val2, long info) val 231 drivers/iio/dac/ad5764.c ret = ad5764_read(indio_dev, reg, val); val 234 drivers/iio/dac/ad5764.c *val >>= chan->scan_type.shift; val 238 drivers/iio/dac/ad5764.c ret = ad5764_read(indio_dev, reg, val); val 241 drivers/iio/dac/ad5764.c *val = sign_extend32(*val, 7); val 245 drivers/iio/dac/ad5764.c ret = ad5764_read(indio_dev, reg, val); val 248 drivers/iio/dac/ad5764.c *val = sign_extend32(*val, 5); val 256 drivers/iio/dac/ad5764.c *val = vref * 4 / 1000; val 260 drivers/iio/dac/ad5764.c *val = -(1 << chan->scan_type.realbits) / 2; val 110 drivers/iio/dac/ad5791.c static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val) val 114 drivers/iio/dac/ad5791.c (val & AD5791_DAC_MASK)); val 119 drivers/iio/dac/ad5791.c static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val) val 142 drivers/iio/dac/ad5791.c *val = be32_to_cpu(st->data[2].d32); val 250 drivers/iio/dac/ad5791.c int *val, val 260 drivers/iio/dac/ad5791.c ret = ad5791_spi_read(st, chan->address, val); val 263 drivers/iio/dac/ad5791.c *val &= AD5791_DAC_MASK; val 264 drivers/iio/dac/ad5791.c *val >>= chan->scan_type.shift; val 267 drivers/iio/dac/ad5791.c *val = st->vref_mv; val 273 drivers/iio/dac/ad5791.c *val = -val64; val 321 drivers/iio/dac/ad5791.c int val, val 329 drivers/iio/dac/ad5791.c val &= GENMASK(chan->scan_type.realbits - 1, 0); val 330 drivers/iio/dac/ad5791.c val <<= chan->scan_type.shift; val 332 drivers/iio/dac/ad5791.c return ad5791_spi_write(st, chan->address, val); val 52 drivers/iio/dac/ad7303.c uint8_t val) val 56 drivers/iio/dac/ad7303.c st->config | val); val 112 drivers/iio/dac/ad7303.c struct iio_chan_spec const *chan, int *val, int *val2, long info) val 119 drivers/iio/dac/ad7303.c *val = st->dac_cache[chan->channel]; val 126 drivers/iio/dac/ad7303.c *val = 2 * vref_uv / 1000; val 137 drivers/iio/dac/ad7303.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 144 drivers/iio/dac/ad7303.c if (val >= (1 << chan->scan_type.realbits) || val < 0) val 148 drivers/iio/dac/ad7303.c ret = ad7303_write(st, chan->address, val); val 150 drivers/iio/dac/ad7303.c st->dac_cache[chan->channel] = val; val 40 drivers/iio/dac/ad8801.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 47 drivers/iio/dac/ad8801.c if (val >= 256 || val < 0) val 50 drivers/iio/dac/ad8801.c ret = ad8801_spi_write(state, chan->channel, val); val 52 drivers/iio/dac/ad8801.c state->dac_cache[chan->channel] = val; val 62 drivers/iio/dac/ad8801.c struct iio_chan_spec const *chan, int *val, int *val2, long info) val 68 drivers/iio/dac/ad8801.c *val = state->dac_cache[chan->channel]; val 71 drivers/iio/dac/ad8801.c *val = state->vrefh_mv - state->vrefl_mv; val 75 drivers/iio/dac/ad8801.c *val = state->vrefl_mv; val 48 drivers/iio/dac/cio-dac.c struct iio_chan_spec const *chan, int *val, int *val2, long mask) val 55 drivers/iio/dac/cio-dac.c *val = priv->chan_out_states[chan->channel]; val 61 drivers/iio/dac/cio-dac.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 70 drivers/iio/dac/cio-dac.c if ((unsigned int)val > 65535) val 73 drivers/iio/dac/cio-dac.c priv->chan_out_states[chan->channel] = val; val 74 drivers/iio/dac/cio-dac.c outw(val, priv->base + chan_addr_offset); val 54 drivers/iio/dac/dpot-dac.c int *val, int *val2, long mask) val 62 drivers/iio/dac/dpot-dac.c return iio_read_channel_raw(dac->dpot, val); val 65 drivers/iio/dac/dpot-dac.c ret = iio_read_channel_scale(dac->dpot, val, val2); val 68 drivers/iio/dac/dpot-dac.c tmp = *val * 1000000000LL; val 72 drivers/iio/dac/dpot-dac.c *val = tmp; val 83 drivers/iio/dac/dpot-dac.c *val *= regulator_get_voltage(dac->vref) / 1000; val 112 drivers/iio/dac/dpot-dac.c int val, int val2, long mask) val 118 drivers/iio/dac/dpot-dac.c return iio_write_channel_raw(dac->dpot, val); val 136 drivers/iio/dac/dpot-dac.c int val; val 146 drivers/iio/dac/dpot-dac.c switch (iio_read_channel_scale(dac->dpot, &val, &val2)) { val 148 drivers/iio/dac/dpot-dac.c return max * val; val 150 drivers/iio/dac/dpot-dac.c tmp = (unsigned long long)max * val; val 154 drivers/iio/dac/dpot-dac.c tmp = val * 1000000000LL * max >> val2; val 71 drivers/iio/dac/ds4424.c int *val, int channel) val 81 drivers/iio/dac/ds4424.c *val = ret; val 89 drivers/iio/dac/ds4424.c int val, struct iio_chan_spec const *chan) val 96 drivers/iio/dac/ds4424.c DS4424_DAC_ADDR(chan->channel), val); val 100 drivers/iio/dac/ds4424.c data->raw[chan->channel] = val; val 109 drivers/iio/dac/ds4424.c int *val, int *val2, long mask) val 116 drivers/iio/dac/ds4424.c ret = ds4424_get_value(indio_dev, val, chan->channel); val 122 drivers/iio/dac/ds4424.c raw.bits = *val; val 123 drivers/iio/dac/ds4424.c *val = raw.dx; val 125 drivers/iio/dac/ds4424.c *val = -*val; val 135 drivers/iio/dac/ds4424.c int val, int val2, long mask) val 144 drivers/iio/dac/ds4424.c if (val < S8_MIN || val > S8_MAX) val 147 drivers/iio/dac/ds4424.c if (val > 0) { val 149 drivers/iio/dac/ds4424.c raw.dx = val; val 152 drivers/iio/dac/ds4424.c raw.dx = -val; val 164 drivers/iio/dac/ds4424.c int ret, val; val 166 drivers/iio/dac/ds4424.c ret = ds4424_get_value(indio_dev, &val, 0); val 51 drivers/iio/dac/lpc18xx_dac.c int *val, int *val2, long mask) val 59 drivers/iio/dac/lpc18xx_dac.c *val = reg >> LPC18XX_DAC_CR_VALUE_SHIFT; val 60 drivers/iio/dac/lpc18xx_dac.c *val &= LPC18XX_DAC_CR_VALUE_MASK; val 65 drivers/iio/dac/lpc18xx_dac.c *val = regulator_get_voltage(dac->vref) / 1000; val 76 drivers/iio/dac/lpc18xx_dac.c int val, int val2, long mask) val 83 drivers/iio/dac/lpc18xx_dac.c if (val < 0 || val > LPC18XX_DAC_CR_VALUE_MASK) val 87 drivers/iio/dac/lpc18xx_dac.c reg |= val << LPC18XX_DAC_CR_VALUE_SHIFT; val 49 drivers/iio/dac/ltc1660.c int *val, val 57 drivers/iio/dac/ltc1660.c *val = priv->value[chan->channel]; val 60 drivers/iio/dac/ltc1660.c *val = regulator_get_voltage(priv->vref_reg); val 61 drivers/iio/dac/ltc1660.c if (*val < 0) { val 63 drivers/iio/dac/ltc1660.c *val); val 64 drivers/iio/dac/ltc1660.c return *val; val 68 drivers/iio/dac/ltc1660.c *val /= 1000; val 78 drivers/iio/dac/ltc1660.c int val, val 90 drivers/iio/dac/ltc1660.c if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0)) val 94 drivers/iio/dac/ltc1660.c (val << chan->scan_type.shift)); val 96 drivers/iio/dac/ltc1660.c priv->value[chan->channel] = val; val 63 drivers/iio/dac/ltc2632.c u8 cmd, u8 addr, u16 val, u8 shift) val 75 drivers/iio/dac/ltc2632.c data = (cmd << 20) | (addr << 16) | (val << shift); val 85 drivers/iio/dac/ltc2632.c int *val, val 93 drivers/iio/dac/ltc2632.c *val = st->vref_mv; val 102 drivers/iio/dac/ltc2632.c int val, val 110 drivers/iio/dac/ltc2632.c if (val >= (1 << chan->scan_type.realbits) || val < 0) val 115 drivers/iio/dac/ltc2632.c chan->address, val, val 33 drivers/iio/dac/m62332.c static int m62332_set_value(struct iio_dev *indio_dev, u8 val, int channel) val 40 drivers/iio/dac/m62332.c if (val == data->raw[channel]) val 44 drivers/iio/dac/m62332.c outbuf[1] = val; val 48 drivers/iio/dac/m62332.c if (val) { val 60 drivers/iio/dac/m62332.c data->raw[channel] = val; val 62 drivers/iio/dac/m62332.c if (!val) val 77 drivers/iio/dac/m62332.c int *val, val 91 drivers/iio/dac/m62332.c *val = ret / 1000; /* mV */ val 96 drivers/iio/dac/m62332.c *val = data->raw[chan->channel]; val 100 drivers/iio/dac/m62332.c *val = 1; val 111 drivers/iio/dac/m62332.c struct iio_chan_spec const *chan, int val, int val2, val 116 drivers/iio/dac/m62332.c if (val < 0 || val > 255) val 119 drivers/iio/dac/m62332.c return m62332_set_value(indio_dev, val, chan->channel); val 44 drivers/iio/dac/max517.c long val, int channel) val 51 drivers/iio/dac/max517.c if (val < 0 || val > 255) val 55 drivers/iio/dac/max517.c outbuf[1] = val; val 68 drivers/iio/dac/max517.c int *val, val 77 drivers/iio/dac/max517.c *val = data->vref_mv[chan->channel]; val 87 drivers/iio/dac/max517.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 93 drivers/iio/dac/max517.c ret = max517_set_value(indio_dev, val, chan->channel); val 170 drivers/iio/dac/max5821.c int *val, int channel) val 205 drivers/iio/dac/max5821.c *val = ((inbuf[0] & 0x0f) << 6) | (inbuf[1] >> 2); val 211 drivers/iio/dac/max5821.c int val, int channel) val 218 drivers/iio/dac/max5821.c if ((val < 0) || (val > 1023)) val 225 drivers/iio/dac/max5821.c outbuf[0] |= val >> 6; val 226 drivers/iio/dac/max5821.c outbuf[1] = (val & 0x3f) << 2; val 239 drivers/iio/dac/max5821.c int *val, int *val2, long mask) val 245 drivers/iio/dac/max5821.c return max5821_get_value(indio_dev, val, chan->channel); val 247 drivers/iio/dac/max5821.c *val = data->vref_mv; val 257 drivers/iio/dac/max5821.c int val, int val2, long mask) val 264 drivers/iio/dac/max5821.c return max5821_set_value(indio_dev, val, chan->channel); val 264 drivers/iio/dac/mcp4725.c static int mcp4725_set_value(struct iio_dev *indio_dev, int val) val 270 drivers/iio/dac/mcp4725.c if (val >= (1 << 12) || val < 0) val 273 drivers/iio/dac/mcp4725.c outbuf[0] = (val >> 8) & 0xf; val 274 drivers/iio/dac/mcp4725.c outbuf[1] = val & 0xff; val 309 drivers/iio/dac/mcp4725.c int *val, int *val2, long mask) val 316 drivers/iio/dac/mcp4725.c *val = data->dac_value; val 327 drivers/iio/dac/mcp4725.c *val = ret / 1000; val 336 drivers/iio/dac/mcp4725.c int val, int val2, long mask) val 343 drivers/iio/dac/mcp4725.c ret = mcp4725_set_value(indio_dev, val); val 344 drivers/iio/dac/mcp4725.c data->dac_value = val; val 50 drivers/iio/dac/mcp4922.c static int mcp4922_spi_write(struct mcp4922_state *state, u8 addr, u32 val) val 52 drivers/iio/dac/mcp4922.c state->mosi[1] = val & 0xff; val 54 drivers/iio/dac/mcp4922.c state->mosi[0] |= 0x30 | ((val >> 8) & 0x0f); val 61 drivers/iio/dac/mcp4922.c int *val, val 69 drivers/iio/dac/mcp4922.c *val = state->value[chan->channel]; val 72 drivers/iio/dac/mcp4922.c *val = state->vref_mv; val 82 drivers/iio/dac/mcp4922.c int val, val 94 drivers/iio/dac/mcp4922.c if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0)) val 96 drivers/iio/dac/mcp4922.c val <<= chan->scan_type.shift; val 98 drivers/iio/dac/mcp4922.c ret = mcp4922_spi_write(state, chan->channel, val); val 100 drivers/iio/dac/mcp4922.c state->value[chan->channel] = val; val 34 drivers/iio/dac/stm32-dac.c u32 en, val; val 37 drivers/iio/dac/stm32-dac.c ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val); val 41 drivers/iio/dac/stm32-dac.c en = FIELD_GET(STM32_DAC_CR_EN1, val); val 43 drivers/iio/dac/stm32-dac.c en = FIELD_GET(STM32_DAC_CR_EN2, val); val 74 drivers/iio/dac/stm32-dac.c static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val) val 79 drivers/iio/dac/stm32-dac.c ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val); val 81 drivers/iio/dac/stm32-dac.c ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val); val 86 drivers/iio/dac/stm32-dac.c static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val) val 91 drivers/iio/dac/stm32-dac.c ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val); val 93 drivers/iio/dac/stm32-dac.c ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val); val 100 drivers/iio/dac/stm32-dac.c int *val, int *val2, long mask) val 106 drivers/iio/dac/stm32-dac.c return stm32_dac_get_value(dac, chan->channel, val); val 108 drivers/iio/dac/stm32-dac.c *val = dac->common->vref_mv; val 118 drivers/iio/dac/stm32-dac.c int val, int val2, long mask) val 124 drivers/iio/dac/stm32-dac.c return stm32_dac_set_value(dac, chan->channel, val); val 53 drivers/iio/dac/ti-dac082s085.c u16 val[4]; val 65 drivers/iio/dac/ti-dac082s085.c static int ti_dac_cmd(struct ti_dac_chip *ti_dac, u8 cmd, u16 val) val 69 drivers/iio/dac/ti-dac082s085.c ti_dac->buf[0] = cmd | (val >> (8 - shift)); val 70 drivers/iio/dac/ti-dac082s085.c ti_dac->buf[1] = (val << shift) & 0xff; val 146 drivers/iio/dac/ti-dac082s085.c ret = ti_dac_cmd(ti_dac, WRITE_AND_UPDATE(0), ti_dac->val[0]); val 187 drivers/iio/dac/ti-dac082s085.c int *val, int *val2, long mask) val 194 drivers/iio/dac/ti-dac082s085.c *val = ti_dac->val[chan->channel]; val 203 drivers/iio/dac/ti-dac082s085.c *val = ret / 1000; val 217 drivers/iio/dac/ti-dac082s085.c int val, int val2, long mask) val 224 drivers/iio/dac/ti-dac082s085.c if (ti_dac->val[chan->channel] == val) val 227 drivers/iio/dac/ti-dac082s085.c if (val >= (1 << ti_dac->resolution) || val < 0) val 234 drivers/iio/dac/ti-dac082s085.c ret = ti_dac_cmd(ti_dac, WRITE_AND_UPDATE(chan->channel), val); val 236 drivers/iio/dac/ti-dac082s085.c ti_dac->val[chan->channel] = val; val 49 drivers/iio/dac/ti-dac5571.c u16 val[4]; val 53 drivers/iio/dac/ti-dac5571.c int (*dac5571_cmd)(struct dac5571_data *data, int channel, u16 val); val 65 drivers/iio/dac/ti-dac5571.c static int dac5571_cmd_single(struct dac5571_data *data, int channel, u16 val) val 70 drivers/iio/dac/ti-dac5571.c data->buf[1] = val << shift; val 71 drivers/iio/dac/ti-dac5571.c data->buf[0] = val >> (8 - shift); val 79 drivers/iio/dac/ti-dac5571.c static int dac5571_cmd_quad(struct dac5571_data *data, int channel, u16 val) val 84 drivers/iio/dac/ti-dac5571.c data->buf[2] = val << shift; val 85 drivers/iio/dac/ti-dac5571.c data->buf[1] = (val >> (8 - shift)); val 194 drivers/iio/dac/ti-dac5571.c ret = data->dac5571_cmd(data, chan->channel, data->val[0]); val 240 drivers/iio/dac/ti-dac5571.c int *val, int *val2, long mask) val 247 drivers/iio/dac/ti-dac5571.c *val = data->val[chan->channel]; val 255 drivers/iio/dac/ti-dac5571.c *val = ret / 1000; val 266 drivers/iio/dac/ti-dac5571.c int val, int val2, long mask) val 273 drivers/iio/dac/ti-dac5571.c if (data->val[chan->channel] == val) val 276 drivers/iio/dac/ti-dac5571.c if (val >= (1 << data->spec->resolution) || val < 0) val 283 drivers/iio/dac/ti-dac5571.c ret = data->dac5571_cmd(data, chan->channel, val); val 285 drivers/iio/dac/ti-dac5571.c data->val[chan->channel] = val; val 51 drivers/iio/dac/ti-dac7311.c u16 val; val 66 drivers/iio/dac/ti-dac7311.c static int ti_dac_cmd(struct ti_dac_chip *ti_dac, u8 power, u16 val) val 70 drivers/iio/dac/ti-dac7311.c ti_dac->buf[0] = (val << shift) & 0xFF; val 71 drivers/iio/dac/ti-dac7311.c ti_dac->buf[1] = (power << 6) | (val >> (8 - shift)); val 168 drivers/iio/dac/ti-dac7311.c int *val, int *val2, long mask) val 175 drivers/iio/dac/ti-dac7311.c *val = ti_dac->val; val 183 drivers/iio/dac/ti-dac7311.c *val = ret / 1000; val 193 drivers/iio/dac/ti-dac7311.c int val, int val2, long mask) val 201 drivers/iio/dac/ti-dac7311.c if (ti_dac->val == val) val 204 drivers/iio/dac/ti-dac7311.c if (val >= (1 << ti_dac->resolution) || val < 0) val 211 drivers/iio/dac/ti-dac7311.c ret = ti_dac_cmd(ti_dac, power, val); val 213 drivers/iio/dac/ti-dac7311.c ti_dac->val = val; val 32 drivers/iio/dac/ti-dac7612.c static int dac7612_cmd_single(struct dac7612 *priv, int channel, u16 val) val 37 drivers/iio/dac/ti-dac7612.c priv->data[0] |= val >> 8; val 38 drivers/iio/dac/ti-dac7612.c priv->data[1] = val & 0xff; val 40 drivers/iio/dac/ti-dac7612.c priv->cache[channel] = val; val 69 drivers/iio/dac/ti-dac7612.c int *val, int *val2, long mask) val 76 drivers/iio/dac/ti-dac7612.c *val = priv->cache[chan->channel]; val 80 drivers/iio/dac/ti-dac7612.c *val = 1; val 90 drivers/iio/dac/ti-dac7612.c int val, int val2, long mask) val 98 drivers/iio/dac/ti-dac7612.c if ((val >= BIT(DAC7612_RESOLUTION)) || val < 0 || val2) val 101 drivers/iio/dac/ti-dac7612.c if (val == priv->cache[chan->channel]) val 105 drivers/iio/dac/ti-dac7612.c ret = dac7612_cmd_single(priv, chan->channel, val); val 43 drivers/iio/dac/vf610_dac.c int val; val 46 drivers/iio/dac/vf610_dac.c val = VF610_DAC_DACEN | VF610_DAC_DACRFS | val 48 drivers/iio/dac/vf610_dac.c writel(val, info->regs + VF610_DACx_STATCTRL); val 53 drivers/iio/dac/vf610_dac.c int val; val 55 drivers/iio/dac/vf610_dac.c val = readl(info->regs + VF610_DACx_STATCTRL); val 56 drivers/iio/dac/vf610_dac.c val &= ~VF610_DAC_DACEN; val 57 drivers/iio/dac/vf610_dac.c writel(val, info->regs + VF610_DACx_STATCTRL); val 65 drivers/iio/dac/vf610_dac.c int val; val 69 drivers/iio/dac/vf610_dac.c val = readl(info->regs + VF610_DACx_STATCTRL); val 71 drivers/iio/dac/vf610_dac.c val |= VF610_DAC_LPEN; val 73 drivers/iio/dac/vf610_dac.c val &= ~VF610_DAC_LPEN; val 74 drivers/iio/dac/vf610_dac.c writel(val, info->regs + VF610_DACx_STATCTRL); val 117 drivers/iio/dac/vf610_dac.c int *val, int *val2, val 124 drivers/iio/dac/vf610_dac.c *val = VF610_DAC_DAT0(readl(info->regs)); val 132 drivers/iio/dac/vf610_dac.c *val = 3300 /* mV */; val 143 drivers/iio/dac/vf610_dac.c int val, int val2, val 151 drivers/iio/dac/vf610_dac.c writel(VF610_DAC_DAT0(val), info->regs); val 37 drivers/iio/dummy/iio_simple_dummy.c int val; val 281 drivers/iio/dummy/iio_simple_dummy.c int *val, val 295 drivers/iio/dummy/iio_simple_dummy.c *val = st->dac_val; val 299 drivers/iio/dummy/iio_simple_dummy.c *val = st->differential_adc_val[0]; val 301 drivers/iio/dummy/iio_simple_dummy.c *val = st->differential_adc_val[1]; val 304 drivers/iio/dummy/iio_simple_dummy.c *val = st->single_ended_adc_val; val 309 drivers/iio/dummy/iio_simple_dummy.c *val = st->accel_val; val 319 drivers/iio/dummy/iio_simple_dummy.c *val = st->steps; val 325 drivers/iio/dummy/iio_simple_dummy.c *val = st->activity_running; val 329 drivers/iio/dummy/iio_simple_dummy.c *val = st->activity_walking; val 342 drivers/iio/dummy/iio_simple_dummy.c *val = 7; val 351 drivers/iio/dummy/iio_simple_dummy.c *val = 0; val 357 drivers/iio/dummy/iio_simple_dummy.c *val = 0; val 368 drivers/iio/dummy/iio_simple_dummy.c *val = st->accel_calibbias; val 372 drivers/iio/dummy/iio_simple_dummy.c *val = st->accel_calibscale->val; val 377 drivers/iio/dummy/iio_simple_dummy.c *val = 3; val 384 drivers/iio/dummy/iio_simple_dummy.c *val = st->steps_enabled; val 394 drivers/iio/dummy/iio_simple_dummy.c *val = st->height; val 424 drivers/iio/dummy/iio_simple_dummy.c int val, val 441 drivers/iio/dummy/iio_simple_dummy.c st->dac_val = val; val 451 drivers/iio/dummy/iio_simple_dummy.c st->steps = val; val 455 drivers/iio/dummy/iio_simple_dummy.c if (val < 0) val 456 drivers/iio/dummy/iio_simple_dummy.c val = 0; val 457 drivers/iio/dummy/iio_simple_dummy.c if (val > 100) val 458 drivers/iio/dummy/iio_simple_dummy.c val = 100; val 461 drivers/iio/dummy/iio_simple_dummy.c st->activity_running = val; val 464 drivers/iio/dummy/iio_simple_dummy.c st->activity_walking = val; val 477 drivers/iio/dummy/iio_simple_dummy.c if (val == dummy_scales[i].val && val 488 drivers/iio/dummy/iio_simple_dummy.c st->accel_calibbias = val; val 495 drivers/iio/dummy/iio_simple_dummy.c st->steps_enabled = val; val 504 drivers/iio/dummy/iio_simple_dummy.c st->height = val; val 69 drivers/iio/dummy/iio_simple_dummy.h enum iio_event_info info, int *val, val 76 drivers/iio/dummy/iio_simple_dummy.h enum iio_event_info info, int val, val 122 drivers/iio/dummy/iio_simple_dummy_events.c int *val, int *val2) val 126 drivers/iio/dummy/iio_simple_dummy_events.c *val = st->event_val; val 145 drivers/iio/dummy/iio_simple_dummy_events.c int val, int val2) val 149 drivers/iio/dummy/iio_simple_dummy_events.c st->event_val = val; val 334 drivers/iio/frequency/ad9523.c unsigned int addr, unsigned int val) val 351 drivers/iio/frequency/ad9523.c st->data[1].d32 = cpu_to_be32(val); val 632 drivers/iio/frequency/ad9523.c int *val, val 649 drivers/iio/frequency/ad9523.c *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN); val 652 drivers/iio/frequency/ad9523.c *val = st->vco_out_freq[st->vco_out_map[chan->channel]] / val 658 drivers/iio/frequency/ad9523.c *val = code / 1000000; val 668 drivers/iio/frequency/ad9523.c int val, val 685 drivers/iio/frequency/ad9523.c if (val) val 691 drivers/iio/frequency/ad9523.c if (val <= 0) { val 695 drivers/iio/frequency/ad9523.c ret = ad9523_set_clock_provider(indio_dev, chan->channel, val); val 698 drivers/iio/frequency/ad9523.c tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val; val 704 drivers/iio/frequency/ad9523.c code = val * 1000000 + val2 % 1000000; val 54 drivers/iio/frequency/adf4350.c __be32 val ____cacheline_aligned; val 81 drivers/iio/frequency/adf4350.c st->val = cpu_to_be32(st->regs[i] | i); val 82 drivers/iio/frequency/adf4350.c ret = spi_write(st->spi, &st->val, 4); val 310 drivers/iio/frequency/adf4350.c unsigned long long val; val 316 drivers/iio/frequency/adf4350.c val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * val 318 drivers/iio/frequency/adf4350.c do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); val 330 drivers/iio/frequency/adf4350.c val = st->clkin; val 333 drivers/iio/frequency/adf4350.c val = st->chspc; val 336 drivers/iio/frequency/adf4350.c val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); val 340 drivers/iio/frequency/adf4350.c val = 0; val 344 drivers/iio/frequency/adf4350.c return ret < 0 ? ret : sprintf(buf, "%llu\n", val); val 184 drivers/iio/frequency/adf4371.c unsigned long long val, tmp; val 187 drivers/iio/frequency/adf4371.c val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd; val 190 drivers/iio/frequency/adf4371.c val += tmp + ADF4371_MODULUS1 / 2; val 197 drivers/iio/frequency/adf4371.c do_div(val, ADF4371_MODULUS1 * (1 << ref_div_sel)); val 200 drivers/iio/frequency/adf4371.c val <<= 1; val 202 drivers/iio/frequency/adf4371.c val <<= 2; val 204 drivers/iio/frequency/adf4371.c return val; val 330 drivers/iio/frequency/adf4371.c unsigned long long val = 0; val 336 drivers/iio/frequency/adf4371.c val = adf4371_pll_fract_n_get_rate(st, chan->channel); val 354 drivers/iio/frequency/adf4371.c val = !(readval & BIT(bit)); val 360 drivers/iio/frequency/adf4371.c val = 0; val 364 drivers/iio/frequency/adf4371.c return ret < 0 ? ret : sprintf(buf, "%llu\n", val); val 50 drivers/iio/gyro/adis16080.c u16 addr, int *val) val 69 drivers/iio/gyro/adis16080.c *val = sign_extend32(be16_to_cpu(st->buf), 11); val 76 drivers/iio/gyro/adis16080.c int *val, val 86 drivers/iio/gyro/adis16080.c ret = adis16080_read_sample(indio_dev, chan->address, val); val 92 drivers/iio/gyro/adis16080.c *val = st->info->scale_val; val 97 drivers/iio/gyro/adis16080.c *val = 5000; val 102 drivers/iio/gyro/adis16080.c *val = 85000 - 25000; val 112 drivers/iio/gyro/adis16080.c *val = 2048; val 116 drivers/iio/gyro/adis16080.c *val = DIV_ROUND_CLOSEST(25 * 585, 85 - 25); val 45 drivers/iio/gyro/adis16130.c static int adis16130_spi_read(struct iio_dev *indio_dev, u8 reg_addr, u32 *val) val 62 drivers/iio/gyro/adis16130.c *val = (st->buf[1] << 16) | (st->buf[2] << 8) | st->buf[3]; val 70 drivers/iio/gyro/adis16130.c int *val, int *val2, val 84 drivers/iio/gyro/adis16130.c *val = temp; val 90 drivers/iio/gyro/adis16130.c *val = 250; val 95 drivers/iio/gyro/adis16130.c *val = 105000; val 104 drivers/iio/gyro/adis16130.c *val = -8388608; val 107 drivers/iio/gyro/adis16130.c *val = -8036283; val 111 drivers/iio/gyro/adis16136.c static int adis16136_show_product_id(void *arg, u64 *val) val 122 drivers/iio/gyro/adis16136.c *val = prod_id; val 129 drivers/iio/gyro/adis16136.c static int adis16136_show_flash_count(void *arg, u64 *val) val 140 drivers/iio/gyro/adis16136.c *val = flash_count; val 207 drivers/iio/gyro/adis16136.c unsigned int val; val 210 drivers/iio/gyro/adis16136.c ret = kstrtouint(buf, 10, &val); val 214 drivers/iio/gyro/adis16136.c if (val == 0) val 217 drivers/iio/gyro/adis16136.c ret = adis16136_set_freq(adis16136, val); val 252 drivers/iio/gyro/adis16136.c static int adis16136_set_filter(struct iio_dev *indio_dev, int val) val 263 drivers/iio/gyro/adis16136.c if (freq / adis16136_3db_divisors[i] >= val) val 270 drivers/iio/gyro/adis16136.c static int adis16136_get_filter(struct iio_dev *indio_dev, int *val) val 287 drivers/iio/gyro/adis16136.c *val = freq / adis16136_3db_divisors[val16 & 0x07]; val 296 drivers/iio/gyro/adis16136.c const struct iio_chan_spec *chan, int *val, int *val2, long info) val 304 drivers/iio/gyro/adis16136.c return adis_single_conversion(indio_dev, chan, 0, val); val 308 drivers/iio/gyro/adis16136.c *val = adis16136->chip_info->precision; val 312 drivers/iio/gyro/adis16136.c *val = 10; val 324 drivers/iio/gyro/adis16136.c *val = sign_extend32(val32, 31); val 328 drivers/iio/gyro/adis16136.c return adis16136_get_filter(indio_dev, val); val 335 drivers/iio/gyro/adis16136.c const struct iio_chan_spec *chan, int val, int val2, long info) val 342 drivers/iio/gyro/adis16136.c ADIS16136_REG_GYRO_OFF2, val); val 344 drivers/iio/gyro/adis16136.c return adis16136_set_filter(indio_dev, val); val 178 drivers/iio/gyro/adis16260.c u16 val = ADIS16260_SLP_CNT_POWER_OFF; val 180 drivers/iio/gyro/adis16260.c ret = adis_write_reg_16(&adis16260->adis, ADIS16260_SLP_CNT, val); val 193 drivers/iio/gyro/adis16260.c int *val, int *val2, val 206 drivers/iio/gyro/adis16260.c ADIS16260_ERROR_ACTIVE, val); val 210 drivers/iio/gyro/adis16260.c *val = info->gyro_max_scale; val 214 drivers/iio/gyro/adis16260.c *val = 0; val 219 drivers/iio/gyro/adis16260.c *val = 1; val 222 drivers/iio/gyro/adis16260.c *val = 0; val 227 drivers/iio/gyro/adis16260.c *val = 145; val 234 drivers/iio/gyro/adis16260.c *val = 250000 / 1453; /* 25 C = 0x00 */ val 242 drivers/iio/gyro/adis16260.c *val = sign_extend32(val16, 11); val 250 drivers/iio/gyro/adis16260.c *val = val16; val 259 drivers/iio/gyro/adis16260.c *val = (val16 & ADIS16260_SMPL_PRD_TIME_BASE) ? val 262 drivers/iio/gyro/adis16260.c *val = (val16 & ADIS16260_SMPL_PRD_TIME_BASE) ? val 264 drivers/iio/gyro/adis16260.c *val /= (val16 & ADIS16260_SMPL_PRD_DIV_MASK) + 1; val 272 drivers/iio/gyro/adis16260.c int val, val 284 drivers/iio/gyro/adis16260.c if (val < -2048 || val >= 2048) val 288 drivers/iio/gyro/adis16260.c return adis_write_reg_16(adis, addr, val); val 290 drivers/iio/gyro/adis16260.c if (val < 0 || val >= 4096) val 294 drivers/iio/gyro/adis16260.c return adis_write_reg_16(adis, addr, val); val 298 drivers/iio/gyro/adis16260.c t = 256 / val; val 300 drivers/iio/gyro/adis16260.c t = 2048 / val; val 90 drivers/iio/gyro/adxrs450.c u16 *val) val 122 drivers/iio/gyro/adxrs450.c *val = (be32_to_cpu(st->rx) >> 5) & 0xFFFF; val 138 drivers/iio/gyro/adxrs450.c u16 val) val 145 drivers/iio/gyro/adxrs450.c tx = ADXRS450_WRITE_DATA | (reg_address << 17) | (val << 1); val 165 drivers/iio/gyro/adxrs450.c static int adxrs450_spi_sensor_data(struct iio_dev *indio_dev, s16 *val) val 191 drivers/iio/gyro/adxrs450.c *val = (be32_to_cpu(st->rx) >> 10) & 0xFFFF; val 205 drivers/iio/gyro/adxrs450.c u32 *val, char chk) val 227 drivers/iio/gyro/adxrs450.c *val = be32_to_cpu(st->rx); val 284 drivers/iio/gyro/adxrs450.c int val, val 291 drivers/iio/gyro/adxrs450.c if (val < -0x400 || val >= 0x400) val 294 drivers/iio/gyro/adxrs450.c ADXRS450_DNC1, val); val 305 drivers/iio/gyro/adxrs450.c int *val, val 319 drivers/iio/gyro/adxrs450.c *val = t; val 327 drivers/iio/gyro/adxrs450.c *val = (t >> 6) + 225; val 338 drivers/iio/gyro/adxrs450.c *val = 0; val 342 drivers/iio/gyro/adxrs450.c *val = 200; val 352 drivers/iio/gyro/adxrs450.c *val = t; val 359 drivers/iio/gyro/adxrs450.c *val = sign_extend32(t, 9); val 150 drivers/iio/gyro/bmg160_core.c static int bmg160_convert_freq_to_bit(int val) val 155 drivers/iio/gyro/bmg160_core.c if (bmg160_samp_freq_table[i].odr == val) val 162 drivers/iio/gyro/bmg160_core.c static int bmg160_set_bw(struct bmg160_data *data, int val) val 168 drivers/iio/gyro/bmg160_core.c bw_bits = bmg160_convert_freq_to_bit(val); val 181 drivers/iio/gyro/bmg160_core.c static int bmg160_get_filter(struct bmg160_data *data, int *val) val 202 drivers/iio/gyro/bmg160_core.c *val = bmg160_samp_freq_table[i].filter; val 208 drivers/iio/gyro/bmg160_core.c static int bmg160_set_filter(struct bmg160_data *data, int val) val 215 drivers/iio/gyro/bmg160_core.c if (bmg160_samp_freq_table[i].filter == val) val 233 drivers/iio/gyro/bmg160_core.c unsigned int val; val 243 drivers/iio/gyro/bmg160_core.c ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); val 249 drivers/iio/gyro/bmg160_core.c dev_dbg(dev, "Chip Id %x\n", val); val 250 drivers/iio/gyro/bmg160_core.c if (val != BMG160_CHIP_ID_VAL) { val 251 drivers/iio/gyro/bmg160_core.c dev_err(dev, "invalid chip %x\n", val); val 275 drivers/iio/gyro/bmg160_core.c ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); val 280 drivers/iio/gyro/bmg160_core.c data->slope_thres = val; val 440 drivers/iio/gyro/bmg160_core.c static int bmg160_get_bw(struct bmg160_data *data, int *val) val 458 drivers/iio/gyro/bmg160_core.c *val = bmg160_samp_freq_table[i].odr; val 466 drivers/iio/gyro/bmg160_core.c static int bmg160_set_scale(struct bmg160_data *data, int val) val 472 drivers/iio/gyro/bmg160_core.c if (bmg160_scale_table[i].scale == val) { val 487 drivers/iio/gyro/bmg160_core.c static int bmg160_get_temp(struct bmg160_data *data, int *val) val 508 drivers/iio/gyro/bmg160_core.c *val = sign_extend32(raw_val, 7); val 517 drivers/iio/gyro/bmg160_core.c static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) val 539 drivers/iio/gyro/bmg160_core.c *val = sign_extend32(le16_to_cpu(raw_val), 15); val 550 drivers/iio/gyro/bmg160_core.c int *val, int *val2, long mask) val 559 drivers/iio/gyro/bmg160_core.c return bmg160_get_temp(data, val); val 565 drivers/iio/gyro/bmg160_core.c val); val 571 drivers/iio/gyro/bmg160_core.c *val = BMG160_TEMP_CENTER_VAL; val 576 drivers/iio/gyro/bmg160_core.c return bmg160_get_filter(data, val); val 580 drivers/iio/gyro/bmg160_core.c *val = 500; val 589 drivers/iio/gyro/bmg160_core.c *val = 0; val 602 drivers/iio/gyro/bmg160_core.c ret = bmg160_get_bw(data, val); val 612 drivers/iio/gyro/bmg160_core.c int val, int val2, long mask) val 632 drivers/iio/gyro/bmg160_core.c ret = bmg160_set_bw(data, val); val 652 drivers/iio/gyro/bmg160_core.c ret = bmg160_set_filter(data, val); val 662 drivers/iio/gyro/bmg160_core.c if (val) val 693 drivers/iio/gyro/bmg160_core.c int *val, int *val2) val 700 drivers/iio/gyro/bmg160_core.c *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; val 714 drivers/iio/gyro/bmg160_core.c int val, int val2) val 723 drivers/iio/gyro/bmg160_core.c data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); val 974 drivers/iio/gyro/bmg160_core.c unsigned int val; val 976 drivers/iio/gyro/bmg160_core.c ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); val 982 drivers/iio/gyro/bmg160_core.c if (val & 0x08) val 987 drivers/iio/gyro/bmg160_core.c if (val & BMG160_ANY_MOTION_BIT_X) val 994 drivers/iio/gyro/bmg160_core.c if (val & BMG160_ANY_MOTION_BIT_Y) val 1001 drivers/iio/gyro/bmg160_core.c if (val & BMG160_ANY_MOTION_BIT_Z) val 322 drivers/iio/gyro/fxas21002c_core.c static int fxas21002c_temp_get(struct fxas21002c_data *data, int *val) val 339 drivers/iio/gyro/fxas21002c_core.c *val = sign_extend32(temp, 7); val 354 drivers/iio/gyro/fxas21002c_core.c int index, int *val) val 372 drivers/iio/gyro/fxas21002c_core.c *val = sign_extend32(be16_to_cpu(axis_be), 15); val 492 drivers/iio/gyro/fxas21002c_core.c static int fxas21002c_scale_get(struct fxas21002c_data *data, int *val) val 509 drivers/iio/gyro/fxas21002c_core.c *val = scale; val 529 drivers/iio/gyro/fxas21002c_core.c struct iio_chan_spec const *chan, int *val, val 539 drivers/iio/gyro/fxas21002c_core.c return fxas21002c_temp_get(data, val); val 541 drivers/iio/gyro/fxas21002c_core.c return fxas21002c_axis_get(data, chan->scan_index, val); val 549 drivers/iio/gyro/fxas21002c_core.c ret = fxas21002c_scale_get(data, val); val 558 drivers/iio/gyro/fxas21002c_core.c *val = 0; val 561 drivers/iio/gyro/fxas21002c_core.c *val = 0; val 565 drivers/iio/gyro/fxas21002c_core.c return fxas21002c_odr_get(data, val); val 572 drivers/iio/gyro/fxas21002c_core.c struct iio_chan_spec const *chan, int val, val 583 drivers/iio/gyro/fxas21002c_core.c return fxas21002c_odr_set(data, val); val 585 drivers/iio/gyro/fxas21002c_core.c if (val) val 593 drivers/iio/gyro/fxas21002c_core.c range = (((val * 1000 + val2 / 1000) * val 94 drivers/iio/gyro/hid-sensor-gyro-3d.c int *val, int *val2, val 103 drivers/iio/gyro/hid-sensor-gyro-3d.c *val = 0; val 112 drivers/iio/gyro/hid-sensor-gyro-3d.c *val = sensor_hub_input_attr_get_raw_value( val 119 drivers/iio/gyro/hid-sensor-gyro-3d.c *val = 0; val 128 drivers/iio/gyro/hid-sensor-gyro-3d.c *val = gyro_state->scale_pre_decml; val 133 drivers/iio/gyro/hid-sensor-gyro-3d.c *val = gyro_state->value_offset; val 138 drivers/iio/gyro/hid-sensor-gyro-3d.c &gyro_state->common_attributes, val, val2); val 142 drivers/iio/gyro/hid-sensor-gyro-3d.c &gyro_state->common_attributes, val, val2); val 155 drivers/iio/gyro/hid-sensor-gyro-3d.c int val, val 165 drivers/iio/gyro/hid-sensor-gyro-3d.c &gyro_state->common_attributes, val, val2); val 169 drivers/iio/gyro/hid-sensor-gyro-3d.c &gyro_state->common_attributes, val, val2); val 33 drivers/iio/gyro/itg3200_core.c u8 reg_address, u8 val) val 37 drivers/iio/gyro/itg3200_core.c return i2c_smbus_write_byte_data(st->i2c, 0x80 | reg_address, val); val 41 drivers/iio/gyro/itg3200_core.c u8 reg_address, u8 *val) val 49 drivers/iio/gyro/itg3200_core.c *val = ret; val 54 drivers/iio/gyro/itg3200_core.c int *val) val 79 drivers/iio/gyro/itg3200_core.c *val = out; val 86 drivers/iio/gyro/itg3200_core.c int *val, int *val2, long info) val 95 drivers/iio/gyro/itg3200_core.c ret = itg3200_read_reg_s16(indio_dev, reg, val); val 98 drivers/iio/gyro/itg3200_core.c *val = 0; val 106 drivers/iio/gyro/itg3200_core.c *val = 23000; val 113 drivers/iio/gyro/itg3200_core.c *val = (regval & ITG3200_DLPF_CFG_MASK) ? 1000 : 8000; val 121 drivers/iio/gyro/itg3200_core.c *val /= regval + 1; val 131 drivers/iio/gyro/itg3200_core.c int val, val 140 drivers/iio/gyro/itg3200_core.c if (val == 0 || val2 != 0) val 150 drivers/iio/gyro/itg3200_core.c t = ((t & ITG3200_DLPF_CFG_MASK) ? 1000u : 8000u) / val - 1; val 203 drivers/iio/gyro/itg3200_core.c u8 val; val 206 drivers/iio/gyro/itg3200_core.c ret = itg3200_read_reg_8(indio_dev, ITG3200_REG_DLPF, &val); val 210 drivers/iio/gyro/itg3200_core.c val |= ITG3200_DLPF_FS_SEL_2000; val 211 drivers/iio/gyro/itg3200_core.c return itg3200_write_reg_8(indio_dev, ITG3200_REG_DLPF, val); val 221 drivers/iio/gyro/itg3200_core.c u8 val; val 227 drivers/iio/gyro/itg3200_core.c ret = itg3200_read_reg_8(indio_dev, ITG3200_REG_ADDRESS, &val); val 231 drivers/iio/gyro/itg3200_core.c if (((val >> 1) & 0x3f) != 0x34) { val 232 drivers/iio/gyro/itg3200_core.c dev_err(&st->i2c->dev, "invalid reg value 0x%02x", val); val 263 drivers/iio/gyro/mpu3050-core.c int *val, int *val2, val 275 drivers/iio/gyro/mpu3050-core.c *val = 23000; val 283 drivers/iio/gyro/mpu3050-core.c *val = mpu3050->calibration[chan->scan_index-1]; val 289 drivers/iio/gyro/mpu3050-core.c *val = mpu3050_get_freq(mpu3050); val 295 drivers/iio/gyro/mpu3050-core.c *val = 1000; val 306 drivers/iio/gyro/mpu3050-core.c *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; val 331 drivers/iio/gyro/mpu3050-core.c *val = be16_to_cpu(raw_val); val 346 drivers/iio/gyro/mpu3050-core.c *val = be16_to_cpu(raw_val); val 370 drivers/iio/gyro/mpu3050-core.c int val, int val2, long mask) val 393 drivers/iio/gyro/mpu3050-core.c mpu3050->calibration[chan->scan_index-1] = val; val 400 drivers/iio/gyro/mpu3050-core.c if (val < 4 || val > 8000) val 407 drivers/iio/gyro/mpu3050-core.c if (val > 1000) { val 409 drivers/iio/gyro/mpu3050-core.c mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; val 414 drivers/iio/gyro/mpu3050-core.c mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; val 428 drivers/iio/gyro/mpu3050-core.c if (val != 0) { val 917 drivers/iio/gyro/mpu3050-core.c unsigned int val; val 921 drivers/iio/gyro/mpu3050-core.c ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); val 926 drivers/iio/gyro/mpu3050-core.c if (!(val & MPU3050_INT_STATUS_RAW_RDY)) val 944 drivers/iio/gyro/mpu3050-core.c unsigned int val; val 957 drivers/iio/gyro/mpu3050-core.c ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); val 1013 drivers/iio/gyro/mpu3050-core.c ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); val 1018 drivers/iio/gyro/mpu3050-core.c val = MPU3050_INT_RAW_RDY_EN; val 1021 drivers/iio/gyro/mpu3050-core.c val |= MPU3050_INT_ACTL; val 1023 drivers/iio/gyro/mpu3050-core.c val |= MPU3050_INT_LATCH_EN; val 1025 drivers/iio/gyro/mpu3050-core.c val |= MPU3050_INT_OPEN; val 1027 drivers/iio/gyro/mpu3050-core.c ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); val 1136 drivers/iio/gyro/mpu3050-core.c unsigned int val; val 1172 drivers/iio/gyro/mpu3050-core.c ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); val 1180 drivers/iio/gyro/mpu3050-core.c if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { val 1182 drivers/iio/gyro/mpu3050-core.c (u8)(val & MPU3050_CHIP_ID_MASK)); val 1187 drivers/iio/gyro/mpu3050-core.c ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); val 1195 drivers/iio/gyro/mpu3050-core.c ((val >> 4) & 0xf), (val & 0xf)); val 28 drivers/iio/gyro/ssp_gyro_sensor.c struct iio_chan_spec const *chan, int *val, val 37 drivers/iio/gyro/ssp_gyro_sensor.c ssp_convert_to_freq(t, val, val2); val 47 drivers/iio/gyro/ssp_gyro_sensor.c struct iio_chan_spec const *chan, int val, val 55 drivers/iio/gyro/ssp_gyro_sensor.c ret = ssp_convert_to_time(val, val2); val 362 drivers/iio/gyro/st_gyro_core.c struct iio_chan_spec const *ch, int *val, val 370 drivers/iio/gyro/st_gyro_core.c err = st_sensors_read_info_raw(indio_dev, ch, val); val 376 drivers/iio/gyro/st_gyro_core.c *val = 0; val 380 drivers/iio/gyro/st_gyro_core.c *val = gdata->odr; val 391 drivers/iio/gyro/st_gyro_core.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 403 drivers/iio/gyro/st_gyro_core.c err = st_sensors_set_odr(indio_dev, val); val 162 drivers/iio/health/afe4403.c int val, integer, fract, ret; val 168 drivers/iio/health/afe4403.c for (val = 0; val < afe440x_attr->table_size; val++) val 169 drivers/iio/health/afe4403.c if (afe440x_attr->val_table[val].integer == integer && val 170 drivers/iio/health/afe4403.c afe440x_attr->val_table[val].fract == fract) val 172 drivers/iio/health/afe4403.c if (val == afe440x_attr->table_size) val 175 drivers/iio/health/afe4403.c ret = regmap_field_write(afe->fields[afe440x_attr->field], val); val 212 drivers/iio/health/afe4403.c static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val) val 227 drivers/iio/health/afe4403.c *val = (rx[0] << 16) | val 242 drivers/iio/health/afe4403.c int *val, int *val2, long mask) val 253 drivers/iio/health/afe4403.c ret = afe4403_read(afe, reg, val); val 262 drivers/iio/health/afe4403.c ret = regmap_field_read(afe->fields[field], val); val 267 drivers/iio/health/afe4403.c *val = 0; val 281 drivers/iio/health/afe4403.c int val, int val2, long mask) val 290 drivers/iio/health/afe4403.c return regmap_field_write(afe->fields[field], val); val 196 drivers/iio/health/afe4404.c int val, integer, fract, ret; val 202 drivers/iio/health/afe4404.c for (val = 0; val < afe440x_attr->table_size; val++) val 203 drivers/iio/health/afe4404.c if (afe440x_attr->val_table[val].integer == integer && val 204 drivers/iio/health/afe4404.c afe440x_attr->val_table[val].fract == fract) val 206 drivers/iio/health/afe4404.c if (val == afe440x_attr->table_size) val 209 drivers/iio/health/afe4404.c ret = regmap_field_write(afe->fields[afe440x_attr->field], val); val 248 drivers/iio/health/afe4404.c int *val, int *val2, long mask) val 260 drivers/iio/health/afe4404.c ret = regmap_read(afe->regmap, value_reg, val); val 265 drivers/iio/health/afe4404.c ret = regmap_field_read(afe->fields[offdac_field], val); val 274 drivers/iio/health/afe4404.c ret = regmap_field_read(afe->fields[led_field], val); val 279 drivers/iio/health/afe4404.c *val = 0; val 293 drivers/iio/health/afe4404.c int val, int val2, long mask) val 303 drivers/iio/health/afe4404.c return regmap_field_write(afe->fields[offdac_field], val); val 309 drivers/iio/health/afe4404.c return regmap_field_write(afe->fields[led_field], val); val 199 drivers/iio/health/max30100.c unsigned int val; val 202 drivers/iio/health/max30100.c ret = regmap_read(data->regmap, MAX30100_REG_INT_STATUS, &val); val 207 drivers/iio/health/max30100.c if (val & MAX30100_REG_INT_STATUS_FIFO_RDY) val 247 drivers/iio/health/max30100.c static int max30100_get_current_idx(unsigned int val, int *reg) val 252 drivers/iio/health/max30100.c if (val == 0) { val 258 drivers/iio/health/max30100.c if (max30100_led_current_mapping[idx] == val) { val 271 drivers/iio/health/max30100.c unsigned int val[2]; val 275 drivers/iio/health/max30100.c (unsigned int *) &val, 2); val 287 drivers/iio/health/max30100.c ret = max30100_get_current_idx(val[0], ®); val 289 drivers/iio/health/max30100.c dev_err(dev, "invalid RED current setting %d", val[0]); val 301 drivers/iio/health/max30100.c ret = max30100_get_current_idx(val[1], ®); val 303 drivers/iio/health/max30100.c dev_err(dev, "invalid IR current setting %d", val[1]); val 342 drivers/iio/health/max30100.c static int max30100_read_temp(struct max30100_data *data, int *val) val 350 drivers/iio/health/max30100.c *val = reg << 4; val 356 drivers/iio/health/max30100.c *val |= reg & 0xf; val 357 drivers/iio/health/max30100.c *val = sign_extend32(*val, 11); val 362 drivers/iio/health/max30100.c static int max30100_get_temp(struct max30100_data *data, int *val) val 375 drivers/iio/health/max30100.c return max30100_read_temp(data, val); val 380 drivers/iio/health/max30100.c int *val, int *val2, long mask) val 396 drivers/iio/health/max30100.c ret = max30100_get_temp(data, val); val 405 drivers/iio/health/max30100.c *val = 1; /* 0.0625 */ val 242 drivers/iio/health/max30102.c unsigned int val; val 245 drivers/iio/health/max30102.c ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val); val 250 drivers/iio/health/max30102.c if (val & MAX30102_REG_INT_STATUS_FIFO_RDY) val 315 drivers/iio/health/max30102.c static int max30102_get_current_idx(unsigned int val, int *reg) val 318 drivers/iio/health/max30102.c *reg = val / 200; val 327 drivers/iio/health/max30102.c unsigned int val; val 330 drivers/iio/health/max30102.c ret = of_property_read_u32(np, "maxim,red-led-current-microamp", &val); val 335 drivers/iio/health/max30102.c val = 7000; val 338 drivers/iio/health/max30102.c ret = max30102_get_current_idx(val, ®); val 340 drivers/iio/health/max30102.c dev_err(dev, "invalid RED LED current setting %d\n", val); val 350 drivers/iio/health/max30102.c "maxim,green-led-current-microamp", &val); val 355 drivers/iio/health/max30102.c val = 7000; val 358 drivers/iio/health/max30102.c ret = max30102_get_current_idx(val, ®); val 361 drivers/iio/health/max30102.c val); val 371 drivers/iio/health/max30102.c ret = of_property_read_u32(np, "maxim,ir-led-current-microamp", &val); val 376 drivers/iio/health/max30102.c val = 7000; val 379 drivers/iio/health/max30102.c ret = max30102_get_current_idx(val, ®); val 381 drivers/iio/health/max30102.c dev_err(dev, "invalid IR LED current setting %d\n", val); val 421 drivers/iio/health/max30102.c static int max30102_read_temp(struct max30102_data *data, int *val) val 429 drivers/iio/health/max30102.c *val = reg << 4; val 435 drivers/iio/health/max30102.c *val |= reg & 0xf; val 436 drivers/iio/health/max30102.c *val = sign_extend32(*val, 11); val 441 drivers/iio/health/max30102.c static int max30102_get_temp(struct max30102_data *data, int *val, bool en) val 459 drivers/iio/health/max30102.c ret = max30102_read_temp(data, val); val 470 drivers/iio/health/max30102.c int *val, int *val2, long mask) val 483 drivers/iio/health/max30102.c ret = max30102_get_temp(data, val, true); val 485 drivers/iio/health/max30102.c ret = max30102_get_temp(data, val, false); val 493 drivers/iio/health/max30102.c *val = 1000; /* 62.5 */ val 192 drivers/iio/humidity/am2315.c int *val, int *val2, long mask) val 203 drivers/iio/humidity/am2315.c *val = (chan->type == IIO_HUMIDITYRELATIVE) ? val 207 drivers/iio/humidity/am2315.c *val = 100; val 192 drivers/iio/humidity/dht11.c int *val, int *val2, long m) val 265 drivers/iio/humidity/dht11.c *val = dht11->temperature; val 267 drivers/iio/humidity/dht11.c *val = dht11->humidity; val 126 drivers/iio/humidity/hdc100x.c static int hdc100x_update_config(struct hdc100x_data *data, int mask, int val) val 128 drivers/iio/humidity/hdc100x.c int tmp = (~mask & data->config) | val; val 165 drivers/iio/humidity/hdc100x.c __be16 val; val 178 drivers/iio/humidity/hdc100x.c ret = i2c_master_recv(data->client, (char *)&val, sizeof(val)); val 183 drivers/iio/humidity/hdc100x.c return be16_to_cpu(val); val 192 drivers/iio/humidity/hdc100x.c struct iio_chan_spec const *chan, int *val, val 203 drivers/iio/humidity/hdc100x.c *val = hdc100x_get_heater_status(data); val 215 drivers/iio/humidity/hdc100x.c *val = ret; val 223 drivers/iio/humidity/hdc100x.c *val = 0; val 228 drivers/iio/humidity/hdc100x.c *val = 165000; val 232 drivers/iio/humidity/hdc100x.c *val = 100000; val 238 drivers/iio/humidity/hdc100x.c *val = -15887; val 248 drivers/iio/humidity/hdc100x.c int val, int val2, long mask) val 255 drivers/iio/humidity/hdc100x.c if (val != 0) val 268 drivers/iio/humidity/hdc100x.c val ? HDC100X_REG_CONFIG_HEATER_EN : 0); val 53 drivers/iio/humidity/hid-sensor-humidity.c int *val, int *val2, long mask) val 62 drivers/iio/humidity/hid-sensor-humidity.c *val = sensor_hub_input_attr_get_raw_value( val 74 drivers/iio/humidity/hid-sensor-humidity.c *val = humid_st->scale_pre_decml; val 80 drivers/iio/humidity/hid-sensor-humidity.c *val = humid_st->value_offset; val 86 drivers/iio/humidity/hid-sensor-humidity.c &humid_st->common_attributes, val, val2); val 90 drivers/iio/humidity/hid-sensor-humidity.c &humid_st->common_attributes, val, val2); val 99 drivers/iio/humidity/hid-sensor-humidity.c int val, int val2, long mask) val 106 drivers/iio/humidity/hid-sensor-humidity.c &humid_st->common_attributes, val, val2); val 110 drivers/iio/humidity/hid-sensor-humidity.c &humid_st->common_attributes, val, val2); val 51 drivers/iio/humidity/hts221_core.c u8 val; val 167 drivers/iio/humidity/hts221_core.c hts221_odr_table[i].val)); val 178 drivers/iio/humidity/hts221_core.c u16 val) val 184 drivers/iio/humidity/hts221_core.c if (avg->avg_avl[i] == val) val 269 drivers/iio/humidity/hts221_core.c __le16 val; val 286 drivers/iio/humidity/hts221_core.c &val, sizeof(val)); val 289 drivers/iio/humidity/hts221_core.c cal_x0 = le16_to_cpu(val); val 292 drivers/iio/humidity/hts221_core.c &val, sizeof(val)); val 295 drivers/iio/humidity/hts221_core.c cal_x1 = le16_to_cpu(val); val 312 drivers/iio/humidity/hts221_core.c __le16 val; val 325 drivers/iio/humidity/hts221_core.c &val, sizeof(val)); val 328 drivers/iio/humidity/hts221_core.c cal_x0 = le16_to_cpu(val); val 331 drivers/iio/humidity/hts221_core.c &val, sizeof(val)); val 334 drivers/iio/humidity/hts221_core.c cal_x1 = le16_to_cpu(val); val 349 drivers/iio/humidity/hts221_core.c int *val, int *val2) val 370 drivers/iio/humidity/hts221_core.c *val = tmp; val 378 drivers/iio/humidity/hts221_core.c int *val, int *val2) val 399 drivers/iio/humidity/hts221_core.c *val = tmp; val 405 drivers/iio/humidity/hts221_core.c static int hts221_read_oneshot(struct hts221_hw *hw, u8 addr, int *val) val 422 drivers/iio/humidity/hts221_core.c *val = (s16)le16_to_cpu(data); val 429 drivers/iio/humidity/hts221_core.c int *val, int *val2, long mask) val 440 drivers/iio/humidity/hts221_core.c ret = hts221_read_oneshot(hw, ch->address, val); val 443 drivers/iio/humidity/hts221_core.c ret = hts221_get_sensor_scale(hw, ch->type, val, val2); val 446 drivers/iio/humidity/hts221_core.c ret = hts221_get_sensor_offset(hw, ch->type, val, val2); val 449 drivers/iio/humidity/hts221_core.c *val = hw->odr; val 460 drivers/iio/humidity/hts221_core.c *val = avg->avg_avl[idx]; val 466 drivers/iio/humidity/hts221_core.c *val = avg->avg_avl[idx]; val 487 drivers/iio/humidity/hts221_core.c int val, int val2, long mask) val 498 drivers/iio/humidity/hts221_core.c ret = hts221_update_odr(hw, val); val 503 drivers/iio/humidity/hts221_core.c ret = hts221_update_avg(hw, HTS221_SENSOR_H, val); val 506 drivers/iio/humidity/hts221_core.c ret = hts221_update_avg(hw, HTS221_SENSOR_T, val); val 39 drivers/iio/humidity/htu21.c struct iio_chan_spec const *channel, int *val, val 54 drivers/iio/humidity/htu21.c *val = temperature; val 62 drivers/iio/humidity/htu21.c *val = humidity; val 69 drivers/iio/humidity/htu21.c *val = htu21_samp_freq[dev_data->res_index]; val 79 drivers/iio/humidity/htu21.c int val, int val2, long mask) val 88 drivers/iio/humidity/htu21.c if (val == htu21_samp_freq[i]) val 74 drivers/iio/humidity/si7005.c struct iio_chan_spec const *chan, int *val, val 85 drivers/iio/humidity/si7005.c *val = ret; val 89 drivers/iio/humidity/si7005.c *val = 7; val 92 drivers/iio/humidity/si7005.c *val = 3; val 98 drivers/iio/humidity/si7005.c *val = -50 * 32 * 4; val 100 drivers/iio/humidity/si7005.c *val = -24 * 16 * 16; val 37 drivers/iio/humidity/si7020.c struct iio_chan_spec const *chan, int *val, val 51 drivers/iio/humidity/si7020.c *val = ret >> 2; val 57 drivers/iio/humidity/si7020.c *val = clamp_val(*val, 786, 13893); val 61 drivers/iio/humidity/si7020.c *val = 175720; /* = 175.72 * 1000 */ val 63 drivers/iio/humidity/si7020.c *val = 125 * 1000; val 77 drivers/iio/humidity/si7020.c *val = -4368; /* = -46.85 * (65536 >> 2) / 175.72 */ val 79 drivers/iio/humidity/si7020.c *val = -786; /* = -6 * (65536 >> 2) / 125 */ val 130 drivers/iio/imu/adis.c unsigned int *val, unsigned int size) val 206 drivers/iio/imu/adis.c *val = get_unaligned_be32(adis->rx); val 209 drivers/iio/imu/adis.c *val = get_unaligned_be16(adis->rx + 2); val 394 drivers/iio/imu/adis.c const struct iio_chan_spec *chan, unsigned int error_mask, int *val) val 414 drivers/iio/imu/adis.c *val = sign_extend32(uval, chan->scan_type.realbits - 1); val 416 drivers/iio/imu/adis.c *val = uval & ((1 << chan->scan_type.realbits) - 1); val 245 drivers/iio/imu/adis16400.c static int adis16400_show_product_id(void *arg, u64 *val) val 255 drivers/iio/imu/adis16400.c *val = prod_id; val 262 drivers/iio/imu/adis16400.c static int adis16400_show_flash_count(void *arg, u64 *val) val 272 drivers/iio/imu/adis16400.c *val = flash_count; val 374 drivers/iio/imu/adis16400.c uint8_t val = 0; val 378 drivers/iio/imu/adis16400.c val |= ADIS16400_SMPL_PRD_TIME_BASE; val 386 drivers/iio/imu/adis16400.c val |= t; val 388 drivers/iio/imu/adis16400.c if (t >= 0x0A || (val & ADIS16400_SMPL_PRD_TIME_BASE)) val 393 drivers/iio/imu/adis16400.c return adis_write_reg_8(&st->adis, ADIS16400_SMPL_PRD, val); val 407 drivers/iio/imu/adis16400.c static int adis16400_set_filter(struct iio_dev *indio_dev, int sps, int val) val 414 drivers/iio/imu/adis16400.c if (sps / adis16400_3db_divisors[i] >= val) val 507 drivers/iio/imu/adis16400.c struct iio_chan_spec const *chan, int val, int val2, long info) val 516 drivers/iio/imu/adis16400.c adis16400_addresses[chan->scan_index], val); val 525 drivers/iio/imu/adis16400.c st->filt_int = val; val 534 drivers/iio/imu/adis16400.c val * 1000 + val2 / 1000); val 538 drivers/iio/imu/adis16400.c sps = val * 1000 + val2 / 1000; val 553 drivers/iio/imu/adis16400.c struct iio_chan_spec const *chan, int *val, int *val2, long info) val 561 drivers/iio/imu/adis16400.c return adis_single_conversion(indio_dev, chan, 0, val); val 565 drivers/iio/imu/adis16400.c *val = 0; val 569 drivers/iio/imu/adis16400.c *val = 0; val 571 drivers/iio/imu/adis16400.c *val = 2; val 574 drivers/iio/imu/adis16400.c *val = 0; val 579 drivers/iio/imu/adis16400.c *val = 0; val 583 drivers/iio/imu/adis16400.c *val = 0; val 587 drivers/iio/imu/adis16400.c *val = st->variant->temp_scale_nano / 1000000; val 592 drivers/iio/imu/adis16400.c *val = 0; val 606 drivers/iio/imu/adis16400.c *val = val16; val 610 drivers/iio/imu/adis16400.c *val = st->variant->temp_offset; val 625 drivers/iio/imu/adis16400.c *val = ret / 1000; val 636 drivers/iio/imu/adis16400.c *val = ret / 1000; val 75 drivers/iio/imu/adis16460.c static int adis16460_show_serial_number(void *arg, u64 *val) val 86 drivers/iio/imu/adis16460.c *val = serial; val 93 drivers/iio/imu/adis16460.c static int adis16460_show_product_id(void *arg, u64 *val) val 104 drivers/iio/imu/adis16460.c *val = prod_id; val 111 drivers/iio/imu/adis16460.c static int adis16460_show_flash_count(void *arg, u64 *val) val 122 drivers/iio/imu/adis16460.c *val = flash_count; val 152 drivers/iio/imu/adis16460.c static int adis16460_set_freq(struct iio_dev *indio_dev, int val, int val2) val 157 drivers/iio/imu/adis16460.c t = val * 1000 + val2 / 1000; val 171 drivers/iio/imu/adis16460.c static int adis16460_get_freq(struct iio_dev *indio_dev, int *val, int *val2) val 183 drivers/iio/imu/adis16460.c *val = freq / 1000; val 190 drivers/iio/imu/adis16460.c const struct iio_chan_spec *chan, int *val, int *val2, long info) val 196 drivers/iio/imu/adis16460.c return adis_single_conversion(indio_dev, chan, 0, val); val 200 drivers/iio/imu/adis16460.c *val = st->chip_info->gyro_max_scale; val 204 drivers/iio/imu/adis16460.c *val = st->chip_info->accel_max_scale; val 208 drivers/iio/imu/adis16460.c *val = 50; /* 50 milli degrees Celsius/LSB */ val 214 drivers/iio/imu/adis16460.c *val = 500; /* 25 degrees Celsius = 0x0000 */ val 217 drivers/iio/imu/adis16460.c return adis16460_get_freq(indio_dev, val, val2); val 224 drivers/iio/imu/adis16460.c const struct iio_chan_spec *chan, int val, int val2, long info) val 228 drivers/iio/imu/adis16460.c return adis16460_set_freq(indio_dev, val, val2); val 229 drivers/iio/imu/adis16480.c static int adis16480_show_serial_number(void *arg, u64 *val) val 240 drivers/iio/imu/adis16480.c *val = serial; val 247 drivers/iio/imu/adis16480.c static int adis16480_show_product_id(void *arg, u64 *val) val 258 drivers/iio/imu/adis16480.c *val = prod_id; val 265 drivers/iio/imu/adis16480.c static int adis16480_show_flash_count(void *arg, u64 *val) val 276 drivers/iio/imu/adis16480.c *val = flash_count; val 315 drivers/iio/imu/adis16480.c static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) val 320 drivers/iio/imu/adis16480.c if (val < 0 || val2 < 0) val 323 drivers/iio/imu/adis16480.c t = val * 1000 + val2 / 1000; val 351 drivers/iio/imu/adis16480.c static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) val 380 drivers/iio/imu/adis16480.c *val = freq / 1000; val 535 drivers/iio/imu/adis16480.c uint16_t val; val 542 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(&st->adis, reg, &val); val 546 drivers/iio/imu/adis16480.c if (!(val & enable_mask)) val 549 drivers/iio/imu/adis16480.c *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; val 561 drivers/iio/imu/adis16480.c uint16_t val; val 568 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(&st->adis, reg, &val); val 573 drivers/iio/imu/adis16480.c val &= ~enable_mask; val 587 drivers/iio/imu/adis16480.c val &= ~(0x3 << offset); val 588 drivers/iio/imu/adis16480.c val |= best_freq << offset; val 589 drivers/iio/imu/adis16480.c val |= enable_mask; val 592 drivers/iio/imu/adis16480.c return adis_write_reg_16(&st->adis, reg, val); val 596 drivers/iio/imu/adis16480.c const struct iio_chan_spec *chan, int *val, int *val2, long info) val 603 drivers/iio/imu/adis16480.c return adis_single_conversion(indio_dev, chan, 0, val); val 607 drivers/iio/imu/adis16480.c *val = st->chip_info->gyro_max_scale; val 611 drivers/iio/imu/adis16480.c *val = st->chip_info->accel_max_scale; val 615 drivers/iio/imu/adis16480.c *val = 0; val 624 drivers/iio/imu/adis16480.c *val = st->chip_info->temp_scale / 1000; val 632 drivers/iio/imu/adis16480.c *val = 131; /* 1310mbar = 131 kPa */ val 641 drivers/iio/imu/adis16480.c *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); val 644 drivers/iio/imu/adis16480.c return adis16480_get_calibbias(indio_dev, chan, val); val 646 drivers/iio/imu/adis16480.c return adis16480_get_calibscale(indio_dev, chan, val); val 648 drivers/iio/imu/adis16480.c return adis16480_get_filter_freq(indio_dev, chan, val); val 650 drivers/iio/imu/adis16480.c return adis16480_get_freq(indio_dev, val, val2); val 657 drivers/iio/imu/adis16480.c const struct iio_chan_spec *chan, int val, int val2, long info) val 661 drivers/iio/imu/adis16480.c return adis16480_set_calibbias(indio_dev, chan, val); val 663 drivers/iio/imu/adis16480.c return adis16480_set_calibscale(indio_dev, chan, val); val 665 drivers/iio/imu/adis16480.c return adis16480_set_filter_freq(indio_dev, chan, val); val 667 drivers/iio/imu/adis16480.c return adis16480_set_freq(indio_dev, val, val2); val 947 drivers/iio/imu/adis16480.c uint16_t val; val 950 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); val 954 drivers/iio/imu/adis16480.c val &= ~ADIS16480_DRDY_EN_MSK; val 955 drivers/iio/imu/adis16480.c val |= ADIS16480_DRDY_EN(enable); val 957 drivers/iio/imu/adis16480.c return adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); val 1047 drivers/iio/imu/adis16480.c uint16_t val; val 1057 drivers/iio/imu/adis16480.c val = ADIS16480_DRDY_EN(0); val 1076 drivers/iio/imu/adis16480.c val |= ADIS16480_DRDY_SEL(pin); val 1085 drivers/iio/imu/adis16480.c val |= ADIS16480_DRDY_POL(1); val 1087 drivers/iio/imu/adis16480.c val |= ADIS16480_DRDY_POL(0); val 1094 drivers/iio/imu/adis16480.c return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); val 1125 drivers/iio/imu/adis16480.c uint16_t val; val 1128 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); val 1138 drivers/iio/imu/adis16480.c if (pin == ADIS16480_DRDY_SEL(val)) val 1151 drivers/iio/imu/adis16480.c val &= ~mask; val 1152 drivers/iio/imu/adis16480.c val |= mode; val 1154 drivers/iio/imu/adis16480.c ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); val 331 drivers/iio/imu/bmi160/bmi160_core.c int i, ret, val; val 333 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_read(data->regmap, bmi160_regs[t].range, &val); val 338 drivers/iio/imu/bmi160/bmi160_core.c if (bmi160_scale_table[t].tbl[i].bits == val) { val 347 drivers/iio/imu/bmi160/bmi160_core.c int axis, int *val) val 360 drivers/iio/imu/bmi160/bmi160_core.c *val = sign_extend32(le16_to_cpu(sample), 15); val 388 drivers/iio/imu/bmi160/bmi160_core.c int i, val, ret; val 390 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_read(data->regmap, bmi160_regs[t].config, &val); val 394 drivers/iio/imu/bmi160/bmi160_core.c val &= bmi160_regs[t].config_odr_mask; val 397 drivers/iio/imu/bmi160/bmi160_core.c if (val == bmi160_odr_table[t].tbl[i].bits) val 436 drivers/iio/imu/bmi160/bmi160_core.c int *val, int *val2, long mask) val 443 drivers/iio/imu/bmi160/bmi160_core.c ret = bmi160_get_data(data, chan->type, chan->channel2, val); val 448 drivers/iio/imu/bmi160/bmi160_core.c *val = 0; val 454 drivers/iio/imu/bmi160/bmi160_core.c val, val2); val 465 drivers/iio/imu/bmi160/bmi160_core.c int val, int val2, long mask) val 476 drivers/iio/imu/bmi160/bmi160_core.c val, val2); val 531 drivers/iio/imu/bmi160/bmi160_core.c unsigned int val; val 533 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_read(regmap, reg, &val); val 537 drivers/iio/imu/bmi160/bmi160_core.c val = (val & ~mask) | bits; val 539 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_write(regmap, reg, val); val 709 drivers/iio/imu/bmi160/bmi160_core.c unsigned int val; val 723 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_read(data->regmap, BMI160_REG_DUMMY, &val); val 728 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_read(data->regmap, BMI160_REG_CHIP_ID, &val); val 733 drivers/iio/imu/bmi160/bmi160_core.c if (val != BMI160_CHIP_ID_VAL) { val 735 drivers/iio/imu/bmi160/bmi160_core.c val, BMI160_CHIP_ID_VAL); val 278 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c enum inv_mpu6050_filter_e val) val 282 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->lpf, val); val 295 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->accel_lpf, val); val 361 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c int axis, int val) val 364 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c __be16 d = cpu_to_be16(val); val 375 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c int axis, int *val) val 384 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c *val = (short)be16_to_cpup(&d); val 391 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c int *val) val 408 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c chan->channel2, val); val 420 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c chan->channel2, val); val 430 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c IIO_MOD_X, val); val 451 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c int *val, int *val2, long mask) val 462 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c ret = inv_mpu6050_read_channel_data(indio_dev, chan, val); val 470 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c *val = 0; val 477 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c *val = 0; val 483 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c *val = st->hw->temp.scale / 1000000; val 492 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c *val = st->hw->temp.offset; val 502 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c chan->channel2, val); val 508 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c chan->channel2, val); val 520 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val) val 526 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c if (gyro_scale_6050[i] == val) { val 558 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val) val 564 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c if (accel_scale[i] == val) { val 580 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c int val, int val2, long mask) val 617 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c chan->channel2, val); val 622 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c chan->channel2, val); val 348 drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); val 164 drivers/iio/imu/kmx61.c int val; val 180 drivers/iio/imu/kmx61.c int val; val 291 drivers/iio/imu/kmx61.c static int kmx61_convert_freq_to_bit(int val, int val2) val 296 drivers/iio/imu/kmx61.c if (val == kmx61_samp_freq_table[i].val && val 302 drivers/iio/imu/kmx61.c static int kmx61_convert_wake_up_odr_to_bit(int val, int val2) val 307 drivers/iio/imu/kmx61.c if (kmx61_wake_up_odr_table[i].val == val && val 401 drivers/iio/imu/kmx61.c static int kmx61_set_wake_up_odr(struct kmx61_data *data, int val, int val2) val 405 drivers/iio/imu/kmx61.c odr_bits = kmx61_convert_wake_up_odr_to_bit(val, val2); val 416 drivers/iio/imu/kmx61.c static int kmx61_set_odr(struct kmx61_data *data, int val, int val2, u8 device) val 426 drivers/iio/imu/kmx61.c lodr_bits = kmx61_convert_freq_to_bit(val, val2); val 450 drivers/iio/imu/kmx61.c ret = kmx61_set_wake_up_odr(data, val, val2); val 458 drivers/iio/imu/kmx61.c static int kmx61_get_odr(struct kmx61_data *data, int *val, int *val2, val 475 drivers/iio/imu/kmx61.c *val = kmx61_samp_freq_table[lodr_bits].val; val 535 drivers/iio/imu/kmx61.c int ret, val, val2; val 566 drivers/iio/imu/kmx61.c ret = kmx61_get_odr(data, &val, &val2, KMX61_ACC); val 570 drivers/iio/imu/kmx61.c ret = kmx61_set_wake_up_odr(data, val, val2); val 784 drivers/iio/imu/kmx61.c struct iio_chan_spec const *chan, int *val, val 817 drivers/iio/imu/kmx61.c *val = sign_extend32(ret >> chan->scan_type.shift, val 828 drivers/iio/imu/kmx61.c *val = 0; val 833 drivers/iio/imu/kmx61.c *val = 0; val 844 drivers/iio/imu/kmx61.c ret = kmx61_get_odr(data, val, val2, chan->address); val 854 drivers/iio/imu/kmx61.c struct iio_chan_spec const *chan, int val, val 866 drivers/iio/imu/kmx61.c ret = kmx61_set_odr(data, val, val2, chan->address); val 872 drivers/iio/imu/kmx61.c if (val != 0) val 891 drivers/iio/imu/kmx61.c int *val, int *val2) val 898 drivers/iio/imu/kmx61.c *val = data->wake_thresh; val 901 drivers/iio/imu/kmx61.c *val = data->wake_duration; val 913 drivers/iio/imu/kmx61.c int val, int val2) val 922 drivers/iio/imu/kmx61.c data->wake_thresh = val; val 925 drivers/iio/imu/kmx61.c data->wake_duration = val; val 55 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h #define ST_LSM6DSX_SHIFT_VAL(val, mask) (((val) << __ffs(mask)) & (mask)) val 85 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h u8 val; val 96 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h u8 val; val 188 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h u8 val; val 340 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val); val 349 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u16 odr, u8 *val); val 356 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h unsigned int mask, unsigned int val) val 361 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h err = regmap_update_bits(hw->regmap, addr, mask, val); val 369 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h void *val, unsigned int len) val 374 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h err = regmap_bulk_read(hw->regmap, addr, val, len); val 382 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h unsigned int val) val 387 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h err = regmap_write(hw->regmap, addr, val); val 64 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c u8 val; val 88 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c static int st_lsm6dsx_get_decimator_val(u8 val) val 94 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c if (st_lsm6dsx_decimator_table[i].decimator == val) val 97 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c return i == max_size ? 0 : st_lsm6dsx_decimator_table[i].val; val 152 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c int val = ST_LSM6DSX_SHIFT_VAL(data, dec_reg->mask); val 156 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c val); val 172 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c int val, ts_dec = !!hw->ts_sip; val 174 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c val = ST_LSM6DSX_SHIFT_VAL(ts_dec, ts_dec_reg->mask); val 176 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c ts_dec_reg->mask, val); val 207 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c int val; val 219 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c val = ST_LSM6DSX_SHIFT_VAL(data, batch_reg->mask); val 221 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c batch_reg->mask, val); val 960 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val, val 972 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u16 odr, u8 *val) val 989 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c *val = odr_table->odr_avl[i].val; val 1014 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c u8 val = 0; val 1048 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val); val 1054 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); val 1078 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c u8 addr, int *val) val 1097 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c *val = (s16)le16_to_cpu(data); val 1104 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c int *val, int *val2, long mask) val 1115 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val); val 1119 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c *val = sensor->odr; val 1123 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c *val = 0; val 1137 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c int val, int val2, long mask) val 1153 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c val = st_lsm6dsx_check_odr(sensor, val, &data); val 1154 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c if (val < 0) val 1155 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c err = val; val 1157 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c sensor->odr = val; val 1170 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) val 1176 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c if (val < 1 || val > hw->settings->max_fifo_size) val 1181 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c err = st_lsm6dsx_update_watermark(sensor, val); val 1188 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c sensor->watermark = val; val 1355 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c int err, val; val 1360 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); val 1363 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c ts_settings->timer_en.mask, val); val 1370 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); val 1373 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c ts_settings->hr_timer.mask, val); val 1380 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); val 1383 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c ts_settings->fifo_en.mask, val); val 46 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .val = 0x40, val 62 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .val = 0x0, val 154 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c u8 mask, u8 val) val 163 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c err = regmap_update_bits(hw->regmap, addr, mask, val); val 304 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c u8 addr, u8 mask, u8 val) val 313 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c data = ((data & ~mask) | (val << __ffs(mask) & mask)); val 320 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c u16 odr, u16 *val) val 333 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c *val = settings->odr_table.odr_avl[i].val; val 341 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c u16 val; val 344 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c err = st_lsm6dsx_shub_get_odr_val(sensor, odr, &val); val 352 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c val); val 417 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c u8 val; val 419 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c val = enable ? settings->pwr_table.on_val val 423 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->pwr_table.reg.mask, val); val 434 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c int *val) val 456 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c *val = (s16)le16_to_cpu(*((__le16 *)data)); val 468 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c int *val, int *val2, long mask) val 479 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c ret = st_lsm6dsx_shub_read_oneshot(sensor, ch, val); val 483 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c *val = sensor->odr; val 487 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c *val = 0; val 502 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c int val, int val2, long mask) val 515 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c err = st_lsm6dsx_shub_get_odr_val(sensor, val, &data); val 517 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c sensor->odr = val; val 541 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c u16 val = settings->odr_table.odr_avl[i].hz; val 543 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c if (val > 0) val 545 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c val); val 726 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c if (data != settings->wai.val) val 511 drivers/iio/industrialio-buffer.c unsigned int val; val 514 drivers/iio/industrialio-buffer.c ret = kstrtouint(buf, 10, &val); val 518 drivers/iio/industrialio-buffer.c if (val == buffer->length) val 525 drivers/iio/industrialio-buffer.c buffer->access->set_length(buffer, val); val 1171 drivers/iio/industrialio-buffer.c unsigned int val; val 1174 drivers/iio/industrialio-buffer.c ret = kstrtouint(buf, 10, &val); val 1177 drivers/iio/industrialio-buffer.c if (!val) val 1182 drivers/iio/industrialio-buffer.c if (val > buffer->length) { val 1192 drivers/iio/industrialio-buffer.c buffer->watermark = val; val 304 drivers/iio/industrialio-core.c unsigned val = 0; val 310 drivers/iio/industrialio-core.c 0, &val); val 316 drivers/iio/industrialio-core.c len = snprintf(buf, sizeof(buf), "0x%X\n", val); val 325 drivers/iio/industrialio-core.c unsigned reg, val; val 335 drivers/iio/industrialio-core.c ret = sscanf(buf, "%i %i", ®, &val); val 344 drivers/iio/industrialio-core.c val, NULL); val 265 drivers/iio/industrialio-event.c bool val; val 267 drivers/iio/industrialio-event.c ret = strtobool(buf, &val); val 273 drivers/iio/industrialio-event.c iio_ev_attr_dir(this_attr), val); val 284 drivers/iio/industrialio-event.c int val; val 286 drivers/iio/industrialio-event.c val = indio_dev->info->read_event_config(indio_dev, val 289 drivers/iio/industrialio-event.c if (val < 0) val 290 drivers/iio/industrialio-event.c return val; val 292 drivers/iio/industrialio-event.c return sprintf(buf, "%d\n", val); val 301 drivers/iio/industrialio-event.c int val, val2, val_arr[2]; val 307 drivers/iio/industrialio-event.c &val, &val2); val 310 drivers/iio/industrialio-event.c val_arr[0] = val; val 322 drivers/iio/industrialio-event.c int val, val2; val 328 drivers/iio/industrialio-event.c ret = iio_str_to_fixpoint(buf, 100000, &val, &val2); val 334 drivers/iio/industrialio-event.c val, val2); val 525 drivers/iio/inkern.c static int iio_channel_read(struct iio_channel *chan, int *val, int *val2, val 543 drivers/iio/inkern.c *val = vals[0]; val 547 drivers/iio/inkern.c chan->channel, val, val2, info); val 552 drivers/iio/inkern.c int iio_read_channel_raw(struct iio_channel *chan, int *val) val 562 drivers/iio/inkern.c ret = iio_channel_read(chan, val, NULL, IIO_CHAN_INFO_RAW); val 570 drivers/iio/inkern.c int iio_read_channel_average_raw(struct iio_channel *chan, int *val) val 580 drivers/iio/inkern.c ret = iio_channel_read(chan, val, NULL, IIO_CHAN_INFO_AVERAGE_RAW); val 664 drivers/iio/inkern.c int iio_read_channel_attribute(struct iio_channel *chan, int *val, int *val2, val 675 drivers/iio/inkern.c ret = iio_channel_read(chan, val, val2, attribute); val 683 drivers/iio/inkern.c int iio_read_channel_offset(struct iio_channel *chan, int *val, int *val2) val 685 drivers/iio/inkern.c return iio_read_channel_attribute(chan, val, val2, IIO_CHAN_INFO_OFFSET); val 689 drivers/iio/inkern.c int iio_read_channel_processed(struct iio_channel *chan, int *val) val 700 drivers/iio/inkern.c ret = iio_channel_read(chan, val, NULL, val 703 drivers/iio/inkern.c ret = iio_channel_read(chan, val, NULL, IIO_CHAN_INFO_RAW); val 706 drivers/iio/inkern.c ret = iio_convert_raw_to_processed_unlocked(chan, *val, val, 1); val 716 drivers/iio/inkern.c int iio_read_channel_scale(struct iio_channel *chan, int *val, int *val2) val 718 drivers/iio/inkern.c return iio_read_channel_attribute(chan, val, val2, IIO_CHAN_INFO_SCALE); val 771 drivers/iio/inkern.c int *val, int *val2, int *type, val 787 drivers/iio/inkern.c *val = vals[2]; val 790 drivers/iio/inkern.c *val = vals[4]; val 800 drivers/iio/inkern.c *val = vals[--length]; val 802 drivers/iio/inkern.c if (vals[--length] > *val) val 803 drivers/iio/inkern.c *val = vals[length]; val 817 drivers/iio/inkern.c int iio_read_max_channel_raw(struct iio_channel *chan, int *val) val 828 drivers/iio/inkern.c ret = iio_channel_read_max(chan, val, NULL, &type, IIO_CHAN_INFO_RAW); val 855 drivers/iio/inkern.c static int iio_channel_write(struct iio_channel *chan, int val, int val2, val 859 drivers/iio/inkern.c chan->channel, val, val2, info); val 862 drivers/iio/inkern.c int iio_write_channel_attribute(struct iio_channel *chan, int val, int val2, val 873 drivers/iio/inkern.c ret = iio_channel_write(chan, val, val2, attribute); val 881 drivers/iio/inkern.c int iio_write_channel_raw(struct iio_channel *chan, int val) val 883 drivers/iio/inkern.c return iio_write_channel_attribute(chan, val, 0, IIO_CHAN_INFO_RAW); val 85 drivers/iio/light/acpi-als.c static int acpi_als_read_value(struct acpi_als *als, char *prop, s32 *val) val 98 drivers/iio/light/acpi-als.c *val = temp_val; val 109 drivers/iio/light/acpi-als.c s32 val; val 118 drivers/iio/light/acpi-als.c ret = acpi_als_read_value(als, ACPI_ALS_ILLUMINANCE, &val); val 121 drivers/iio/light/acpi-als.c *buffer++ = val; val 137 drivers/iio/light/acpi-als.c struct iio_chan_spec const *chan, int *val, val 155 drivers/iio/light/acpi-als.c *val = temp_val; val 96 drivers/iio/light/adjd_s311.c static int adjd_s311_read_data(struct iio_dev *indio_dev, u8 reg, int *val) val 108 drivers/iio/light/adjd_s311.c *val = ret & ADJD_S311_DATA_MASK; val 170 drivers/iio/light/adjd_s311.c int *val, int *val2, long mask) val 178 drivers/iio/light/adjd_s311.c ADJD_S311_DATA_REG(chan->address), val); val 187 drivers/iio/light/adjd_s311.c *val = ret & ADJD_S311_CAP_MASK; val 194 drivers/iio/light/adjd_s311.c *val = 0; val 207 drivers/iio/light/adjd_s311.c int val, int val2, long mask) val 213 drivers/iio/light/adjd_s311.c if (val < 0 || val > ADJD_S311_CAP_MASK) val 217 drivers/iio/light/adjd_s311.c ADJD_S311_CAP_REG(chan->address), val); val 219 drivers/iio/light/adjd_s311.c if (val != 0 || val2 < 0 || val2 > ADJD_S311_INT_MASK) val 111 drivers/iio/light/al3320a.c struct iio_chan_spec const *chan, int *val, val 128 drivers/iio/light/al3320a.c *val = ret; val 137 drivers/iio/light/al3320a.c *val = al3320a_scales[ret][0]; val 146 drivers/iio/light/al3320a.c struct iio_chan_spec const *chan, int val, val 155 drivers/iio/light/al3320a.c if (val == al3320a_scales[i][0] && val 236 drivers/iio/light/apds9300.c struct iio_chan_spec const *chan, int *val, int *val2, val 255 drivers/iio/light/apds9300.c *val = apds9300_calculate_lux(ch0, ch1); val 262 drivers/iio/light/apds9300.c *val = ret; val 276 drivers/iio/light/apds9300.c int *val, int *val2) val 282 drivers/iio/light/apds9300.c *val = data->thresh_hi; val 285 drivers/iio/light/apds9300.c *val = data->thresh_low; val 296 drivers/iio/light/apds9300.c enum iio_event_direction dir, enum iio_event_info info, int val, val 304 drivers/iio/light/apds9300.c ret = apds9300_set_thresh_hi(data, val); val 306 drivers/iio/light/apds9300.c ret = apds9300_set_thresh_low(data, val); val 381 drivers/iio/light/apds9960.c static int apds9960_set_pxs_gain(struct apds9960_data *data, int val) val 387 drivers/iio/light/apds9960.c if (apds9960_pxs_gain_map[idx] == val) { val 413 drivers/iio/light/apds9960.c static int apds9960_set_als_gain(struct apds9960_data *data, int val) val 419 drivers/iio/light/apds9960.c if (apds9960_als_gain_map[idx] == val) { val 470 drivers/iio/light/apds9960.c int *val, int *val2, long mask) val 484 drivers/iio/light/apds9960.c ret = regmap_read(data->regmap, chan->address, val); val 493 drivers/iio/light/apds9960.c *val = le16_to_cpu(buf); val 506 drivers/iio/light/apds9960.c *val = 0; val 519 drivers/iio/light/apds9960.c *val = apds9960_pxs_gain_map[data->pxs_gain]; val 523 drivers/iio/light/apds9960.c *val = apds9960_als_gain_map[data->als_gain]; val 538 drivers/iio/light/apds9960.c int val, int val2, long mask) val 547 drivers/iio/light/apds9960.c if (val != 0) val 558 drivers/iio/light/apds9960.c return apds9960_set_pxs_gain(data, val); val 560 drivers/iio/light/apds9960.c return apds9960_set_als_gain(data, val); val 612 drivers/iio/light/apds9960.c int *val, int *val2) val 627 drivers/iio/light/apds9960.c ret = regmap_read(data->regmap, reg, val); val 634 drivers/iio/light/apds9960.c *val = le16_to_cpu(buf); val 648 drivers/iio/light/apds9960.c int val, int val2) val 663 drivers/iio/light/apds9960.c if (val < 0 || val > APDS9960_MAX_PXS_THRES_VAL) val 665 drivers/iio/light/apds9960.c ret = regmap_write(data->regmap, reg, val); val 669 drivers/iio/light/apds9960.c if (val < 0 || val > APDS9960_MAX_ALS_THRES_VAL) val 671 drivers/iio/light/apds9960.c buf = cpu_to_le16(val); val 73 drivers/iio/light/bh1750.c u16 val; val 80 drivers/iio/light/bh1750.c val = usec / chip_info->mtreg_to_usec; val 81 drivers/iio/light/bh1750.c if (val < chip_info->mtreg_min || val > chip_info->mtreg_max) val 88 drivers/iio/light/bh1750.c regval = (val & chip_info->int_time_high_mask) >> 5; val 94 drivers/iio/light/bh1750.c regval = val & chip_info->int_time_low_mask; val 100 drivers/iio/light/bh1750.c data->mtreg = val; val 105 drivers/iio/light/bh1750.c static int bh1750_read(struct bh1750_data *data, int *val) val 126 drivers/iio/light/bh1750.c *val = be16_to_cpu(result); val 133 drivers/iio/light/bh1750.c int *val, int *val2, long mask) val 144 drivers/iio/light/bh1750.c ret = bh1750_read(data, val); val 155 drivers/iio/light/bh1750.c *val = tmp / 1000000; val 159 drivers/iio/light/bh1750.c *val = 0; val 169 drivers/iio/light/bh1750.c int val, int val2, long mask) val 176 drivers/iio/light/bh1750.c if (val != 0) val 43 drivers/iio/light/bh1780.c static int bh1780_write(struct bh1780_data *bh1780, u8 reg, u8 val) val 47 drivers/iio/light/bh1780.c val); val 101 drivers/iio/light/bh1780.c int *val, int *val2, long mask) val 116 drivers/iio/light/bh1780.c *val = value; val 123 drivers/iio/light/bh1780.c *val = 0; val 136 drivers/iio/light/cm32181.c static int cm32181_write_als_it(struct cm32181_chip *cm32181, int val) val 144 drivers/iio/light/cm32181.c if (val <= als_it_value[i]) val 205 drivers/iio/light/cm32181.c int *val, int *val2, long mask) val 215 drivers/iio/light/cm32181.c *val = ret; val 218 drivers/iio/light/cm32181.c *val = cm32181->calibscale; val 221 drivers/iio/light/cm32181.c *val = 0; val 231 drivers/iio/light/cm32181.c int val, int val2, long mask) val 238 drivers/iio/light/cm32181.c cm32181->calibscale = val; val 239 drivers/iio/light/cm32181.c return val; val 41 drivers/iio/light/cm3232.c int val; val 132 drivers/iio/light/cm3232.c static int cm3232_read_als_it(struct cm3232_chip *chip, int *val, int *val2) val 142 drivers/iio/light/cm3232.c *val = cm3232_als_it_scales[i].val; val 161 drivers/iio/light/cm3232.c static int cm3232_write_als_it(struct cm3232_chip *chip, int val, int val2) val 169 drivers/iio/light/cm3232.c if (val == cm3232_als_it_scales[i].val && val 203 drivers/iio/light/cm3232.c int val, val2; val 208 drivers/iio/light/cm3232.c ret = cm3232_read_als_it(chip, &val, &val2); val 211 drivers/iio/light/cm3232.c als_it = val * 1000000 + val2; val 236 drivers/iio/light/cm3232.c int *val, int *val2, long mask) val 247 drivers/iio/light/cm3232.c *val = ret; val 250 drivers/iio/light/cm3232.c *val = als_info->calibscale; val 253 drivers/iio/light/cm3232.c return cm3232_read_als_it(chip, val, val2); val 261 drivers/iio/light/cm3232.c int val, int val2, long mask) val 268 drivers/iio/light/cm3232.c als_info->calibscale = val; val 271 drivers/iio/light/cm3232.c return cm3232_write_als_it(chip, val, val2); val 294 drivers/iio/light/cm3232.c cm3232_als_it_scales[i].val, val 35 drivers/iio/light/cm3323.c int val; val 116 drivers/iio/light/cm3323.c static int cm3323_set_it_bits(struct cm3323_data *data, int val, int val2) val 122 drivers/iio/light/cm3323.c if (val == cm3323_int_time[i].val && val 156 drivers/iio/light/cm3323.c struct iio_chan_spec const *chan, int *val, val 170 drivers/iio/light/cm3323.c *val = ret; val 182 drivers/iio/light/cm3323.c *val = cm3323_int_time[ret].val; val 193 drivers/iio/light/cm3323.c struct iio_chan_spec const *chan, int val, val 202 drivers/iio/light/cm3323.c ret = cm3323_set_it_bits(data, val, val2); val 107 drivers/iio/light/cm3605.c int *val, int *val2, long mask) val 119 drivers/iio/light/cm3605.c *val = ret; val 191 drivers/iio/light/cm36651.c struct iio_chan_spec const *chan, int *val) val 198 drivers/iio/light/cm36651.c *val = i2c_smbus_read_word_data(client, chan->address); val 199 drivers/iio/light/cm36651.c if (*val < 0) val 210 drivers/iio/light/cm36651.c *val = i2c_smbus_read_byte(cm36651->ps_client); val 211 drivers/iio/light/cm36651.c if (*val < 0) val 327 drivers/iio/light/cm36651.c struct iio_chan_spec const *chan, int *val) val 346 drivers/iio/light/cm36651.c ret = cm36651_read_output(cm36651, chan, val); val 391 drivers/iio/light/cm36651.c struct iio_chan_spec const *chan, int val) val 399 drivers/iio/light/cm36651.c if (val == 80000) val 401 drivers/iio/light/cm36651.c else if (val == 160000) val 403 drivers/iio/light/cm36651.c else if (val == 320000) val 405 drivers/iio/light/cm36651.c else if (val == 640000) val 419 drivers/iio/light/cm36651.c if (val == 320) val 421 drivers/iio/light/cm36651.c else if (val == 420) val 423 drivers/iio/light/cm36651.c else if (val == 520) val 425 drivers/iio/light/cm36651.c else if (val == 640) val 447 drivers/iio/light/cm36651.c int *val, int *val2, long mask) val 456 drivers/iio/light/cm36651.c ret = cm36651_read_channel(cm36651, chan, val); val 459 drivers/iio/light/cm36651.c *val = 0; val 473 drivers/iio/light/cm36651.c int val, int val2, long mask) val 493 drivers/iio/light/cm36651.c int *val, int *val2) val 497 drivers/iio/light/cm36651.c *val = cm36651->ps_ctrl_regs[CM36651_PS_THD]; val 507 drivers/iio/light/cm36651.c int val, int val2) val 513 drivers/iio/light/cm36651.c if (val < 3 || val > 255) val 516 drivers/iio/light/cm36651.c cm36651->ps_ctrl_regs[CM36651_PS_THD] = val; val 41 drivers/iio/light/cros_ec_light_prox.c int *val, int *val2, long mask) val 58 drivers/iio/light/cros_ec_light_prox.c *val = data; val 75 drivers/iio/light/cros_ec_light_prox.c *val = data; val 93 drivers/iio/light/cros_ec_light_prox.c *val = st->core.calib[idx].offset; val 110 drivers/iio/light/cros_ec_light_prox.c *val = val64 >> 16; val 115 drivers/iio/light/cros_ec_light_prox.c ret = cros_ec_sensors_core_read(&st->core, chan, val, val2, val 127 drivers/iio/light/cros_ec_light_prox.c int val, int val2, long mask) val 137 drivers/iio/light/cros_ec_light_prox.c st->core.calib[idx].offset = val; val 149 drivers/iio/light/cros_ec_light_prox.c st->core.param.sensor_range.data = (val << 16) | (val2 / 100); val 153 drivers/iio/light/cros_ec_light_prox.c ret = cros_ec_sensors_core_write(&st->core, chan, val, val2, val 699 drivers/iio/light/gp2ap020a00f.c unsigned int output_reg, int *val) val 712 drivers/iio/light/gp2ap020a00f.c *val = le16_to_cpup((__le16 *)reg_buf); val 1023 drivers/iio/light/gp2ap020a00f.c int val, int val2) val 1051 drivers/iio/light/gp2ap020a00f.c if (val == 0) { val 1059 drivers/iio/light/gp2ap020a00f.c if (val == 0) { val 1068 drivers/iio/light/gp2ap020a00f.c data->thresh_val[thresh_val_id] = val; val 1082 drivers/iio/light/gp2ap020a00f.c int *val, int *val2) val 1097 drivers/iio/light/gp2ap020a00f.c *val = data->thresh_val[GP2AP020A00F_THRESH_VAL_ID(thresh_reg_l)]; val 1234 drivers/iio/light/gp2ap020a00f.c struct iio_chan_spec const *chan, int *val) val 1260 drivers/iio/light/gp2ap020a00f.c err = gp2ap020a00f_read_output(data, chan->address, val); val 1273 drivers/iio/light/gp2ap020a00f.c gp2ap020a00f_output_to_lux(data, val); val 1281 drivers/iio/light/gp2ap020a00f.c int *val, int *val2, val 1292 drivers/iio/light/gp2ap020a00f.c err = gp2ap020a00f_read_channel(data, chan, val); val 76 drivers/iio/light/hid-sensor-als.c int *val, int *val2, val 85 drivers/iio/light/hid-sensor-als.c *val = 0; val 103 drivers/iio/light/hid-sensor-als.c *val = sensor_hub_input_attr_get_raw_value( val 112 drivers/iio/light/hid-sensor-als.c *val = 0; val 118 drivers/iio/light/hid-sensor-als.c *val = als_state->scale_pre_decml; val 123 drivers/iio/light/hid-sensor-als.c *val = als_state->value_offset; val 128 drivers/iio/light/hid-sensor-als.c &als_state->common_attributes, val, val2); val 132 drivers/iio/light/hid-sensor-als.c &als_state->common_attributes, val, val2); val 145 drivers/iio/light/hid-sensor-als.c int val, val 155 drivers/iio/light/hid-sensor-als.c &als_state->common_attributes, val, val2); val 159 drivers/iio/light/hid-sensor-als.c &als_state->common_attributes, val, val2); val 57 drivers/iio/light/hid-sensor-prox.c int *val, int *val2, val 66 drivers/iio/light/hid-sensor-prox.c *val = 0; val 83 drivers/iio/light/hid-sensor-prox.c *val = sensor_hub_input_attr_get_raw_value( val 92 drivers/iio/light/hid-sensor-prox.c *val = 0; val 98 drivers/iio/light/hid-sensor-prox.c *val = prox_state->prox_attr.units; val 102 drivers/iio/light/hid-sensor-prox.c *val = hid_sensor_convert_exponent( val 108 drivers/iio/light/hid-sensor-prox.c &prox_state->common_attributes, val, val2); val 112 drivers/iio/light/hid-sensor-prox.c &prox_state->common_attributes, val, val2); val 125 drivers/iio/light/hid-sensor-prox.c int val, val 135 drivers/iio/light/hid-sensor-prox.c &prox_state->common_attributes, val, val2); val 139 drivers/iio/light/hid-sensor-prox.c &prox_state->common_attributes, val, val2); val 341 drivers/iio/light/isl29018.c int val; val 343 drivers/iio/light/isl29018.c if (kstrtoint(buf, 10, &val)) val 345 drivers/iio/light/isl29018.c if (!(val == 0 || val == 1)) val 353 drivers/iio/light/isl29018.c chip->prox_scheme = val; val 361 drivers/iio/light/isl29018.c int val, val 376 drivers/iio/light/isl29018.c chip->calibscale = val; val 382 drivers/iio/light/isl29018.c if (chan->type == IIO_LIGHT && !val) val 387 drivers/iio/light/isl29018.c ret = isl29018_set_scale(chip, val, val2); val 401 drivers/iio/light/isl29018.c int *val, val 418 drivers/iio/light/isl29018.c ret = isl29018_read_lux(chip, val); val 421 drivers/iio/light/isl29018.c ret = isl29018_read_ir(chip, val); val 426 drivers/iio/light/isl29018.c val); val 436 drivers/iio/light/isl29018.c *val = 0; val 443 drivers/iio/light/isl29018.c *val = chip->scale.scale; val 450 drivers/iio/light/isl29018.c *val = chip->calibscale; val 165 drivers/iio/light/isl29028.c int val = (lux_scale == 2000) ? ISL29028_CONF_ALS_RANGE_HIGH_LUX : val 170 drivers/iio/light/isl29028.c ISL29028_CONF_ALS_RANGE_MASK, val); val 356 drivers/iio/light/isl29028.c int val, int val2, long mask) val 378 drivers/iio/light/isl29028.c if (val < 1 || val > 100) { val 381 drivers/iio/light/isl29028.c __func__, val); val 385 drivers/iio/light/isl29028.c ret = isl29028_set_proxim_sampling(chip, val, val2); val 395 drivers/iio/light/isl29028.c if (val != 125 && val != 2000) { val 398 drivers/iio/light/isl29028.c __func__, val); val 402 drivers/iio/light/isl29028.c ret = isl29028_set_als_scale(chip, val); val 424 drivers/iio/light/isl29028.c int *val, int *val2, long mask) val 442 drivers/iio/light/isl29028.c ret = isl29028_als_get(chip, val); val 445 drivers/iio/light/isl29028.c ret = isl29028_ir_get(chip, val); val 448 drivers/iio/light/isl29028.c ret = isl29028_read_proxim(chip, val); val 463 drivers/iio/light/isl29028.c *val = chip->prox_sampling_int; val 470 drivers/iio/light/isl29028.c *val = chip->lux_scale; val 123 drivers/iio/light/isl29125.c int *val, int *val2, long mask) val 137 drivers/iio/light/isl29125.c *val = ret; val 140 drivers/iio/light/isl29125.c *val = 0; val 152 drivers/iio/light/isl29125.c int val, int val2, long mask) val 158 drivers/iio/light/isl29125.c if (val != 0) val 162 drivers/iio/light/jsa1212.c unsigned int *val) val 181 drivers/iio/light/jsa1212.c *val = le16_to_cpu(als_data); val 188 drivers/iio/light/jsa1212.c unsigned int *val) val 207 drivers/iio/light/jsa1212.c *val = pxs_data & JSA1212_PXS_DATA_MASK; val 215 drivers/iio/light/jsa1212.c int *val, int *val2, long mask) val 225 drivers/iio/light/jsa1212.c ret = jsa1212_read_als_data(data, val); val 228 drivers/iio/light/jsa1212.c ret = jsa1212_read_pxs_data(data, val); val 239 drivers/iio/light/jsa1212.c *val = jsa1212_als_range_val[data->als_rng_idx]; val 67 drivers/iio/light/lm3533-als.c u8 val; val 75 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, reg, &val); val 81 drivers/iio/light/lm3533-als.c *adc = val; val 89 drivers/iio/light/lm3533-als.c u8 val; val 92 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, LM3533_REG_ALS_ZONE_INFO, &val); val 98 drivers/iio/light/lm3533-als.c val = (val & LM3533_ALS_ZONE_MASK) >> LM3533_ALS_ZONE_SHIFT; val 99 drivers/iio/light/lm3533-als.c *zone = min_t(u8, val, LM3533_ALS_ZONE_MAX); val 130 drivers/iio/light/lm3533-als.c unsigned zone, u8 *val) val 143 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, reg, val); val 151 drivers/iio/light/lm3533-als.c unsigned zone, u8 val) val 164 drivers/iio/light/lm3533-als.c ret = lm3533_write(als->lm3533, reg, val); val 172 drivers/iio/light/lm3533-als.c int *val) val 186 drivers/iio/light/lm3533-als.c *val = target; val 193 drivers/iio/light/lm3533-als.c int *val, int *val2, long mask) val 201 drivers/iio/light/lm3533-als.c ret = lm3533_als_get_adc(indio_dev, false, val); val 205 drivers/iio/light/lm3533-als.c val); val 212 drivers/iio/light/lm3533-als.c ret = lm3533_als_get_adc(indio_dev, true, val); val 275 drivers/iio/light/lm3533-als.c u8 val; val 279 drivers/iio/light/lm3533-als.c val = mask; val 281 drivers/iio/light/lm3533-als.c val = 0; val 283 drivers/iio/light/lm3533-als.c ret = lm3533_update(als->lm3533, LM3533_REG_ALS_ZONE_INFO, val, mask); val 297 drivers/iio/light/lm3533-als.c u8 val; val 300 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, LM3533_REG_ALS_ZONE_INFO, &val); val 306 drivers/iio/light/lm3533-als.c *enable = !!(val & mask); val 319 drivers/iio/light/lm3533-als.c bool raising, u8 *val) val 329 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, reg, val); val 337 drivers/iio/light/lm3533-als.c bool raising, u8 val) val 361 drivers/iio/light/lm3533-als.c if ((raising && (val < val2)) || (!raising && (val > val2))) { val 366 drivers/iio/light/lm3533-als.c ret = lm3533_write(als->lm3533, reg, val); val 378 drivers/iio/light/lm3533-als.c u8 *val) val 396 drivers/iio/light/lm3533-als.c *val = raising - falling; val 506 drivers/iio/light/lm3533-als.c u8 val; val 512 drivers/iio/light/lm3533-als.c &val); val 516 drivers/iio/light/lm3533-als.c als_attr->val2, &val); val 520 drivers/iio/light/lm3533-als.c false, &val); val 524 drivers/iio/light/lm3533-als.c true, &val); val 533 drivers/iio/light/lm3533-als.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 542 drivers/iio/light/lm3533-als.c u8 val; val 545 drivers/iio/light/lm3533-als.c if (kstrtou8(buf, 0, &val)) val 551 drivers/iio/light/lm3533-als.c als_attr->val2, val); val 555 drivers/iio/light/lm3533-als.c false, val); val 559 drivers/iio/light/lm3533-als.c true, val); val 720 drivers/iio/light/lm3533-als.c u8 val; val 724 drivers/iio/light/lm3533-als.c val = mask; /* pwm input */ val 726 drivers/iio/light/lm3533-als.c val = 0; /* analog input */ val 728 drivers/iio/light/lm3533-als.c ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, val, mask); val 738 drivers/iio/light/lm3533-als.c static int lm3533_als_set_resistor(struct lm3533_als *als, u8 val) val 742 drivers/iio/light/lm3533-als.c if (val < LM3533_ALS_RESISTOR_MIN || val > LM3533_ALS_RESISTOR_MAX) { val 747 drivers/iio/light/lm3533-als.c ret = lm3533_write(als->lm3533, LM3533_REG_ALS_RESISTOR_SELECT, val); val 181 drivers/iio/light/ltr501.c int len, int val, int val2) val 185 drivers/iio/light/ltr501.c freq = val * 1000000 + val2; val 196 drivers/iio/light/ltr501.c int *val, int *val2) val 207 drivers/iio/light/ltr501.c *val = ltr501_als_samp_table[i].freq_val / 1000000; val 214 drivers/iio/light/ltr501.c int *val, int *val2) val 225 drivers/iio/light/ltr501.c *val = ltr501_ps_samp_table[i].freq_val / 1000000; val 232 drivers/iio/light/ltr501.c int val, int val2) val 238 drivers/iio/light/ltr501.c val, val2); val 251 drivers/iio/light/ltr501.c int val, int val2) val 257 drivers/iio/light/ltr501.c val, val2); val 269 drivers/iio/light/ltr501.c static int ltr501_als_read_samp_period(struct ltr501_data *data, int *val) val 280 drivers/iio/light/ltr501.c *val = ltr501_als_samp_table[i].time_val; val 285 drivers/iio/light/ltr501.c static int ltr501_ps_read_samp_period(struct ltr501_data *data, int *val) val 296 drivers/iio/light/ltr501.c *val = ltr501_ps_samp_table[i].time_val; val 376 drivers/iio/light/ltr501.c static int ltr501_read_it_time(struct ltr501_data *data, int *val, int *val2) val 389 drivers/iio/light/ltr501.c *val = 0; val 461 drivers/iio/light/ltr501.c int val, int val2) val 466 drivers/iio/light/ltr501.c if (val < 0 || val2 < 0) val 470 drivers/iio/light/ltr501.c period = ((val * 1000000) + val2); val 623 drivers/iio/light/ltr501.c int *val, int *val2, long mask) val 643 drivers/iio/light/ltr501.c *val = ltr501_calculate_lux(le16_to_cpu(buf[1]), val 661 drivers/iio/light/ltr501.c *val = le16_to_cpu(chan->address == LTR501_ALS_DATA1 ? val 671 drivers/iio/light/ltr501.c *val = ret & LTR501_PS_DATA_MASK; val 687 drivers/iio/light/ltr501.c *val = data->chip_info->als_gain[i].scale; val 693 drivers/iio/light/ltr501.c *val = data->chip_info->ps_gain[i].scale; val 702 drivers/iio/light/ltr501.c return ltr501_read_it_time(data, val, val2); val 709 drivers/iio/light/ltr501.c return ltr501_als_read_samp_freq(data, val, val2); val 711 drivers/iio/light/ltr501.c return ltr501_ps_read_samp_freq(data, val, val2); val 720 drivers/iio/light/ltr501.c int val, int val2) val 725 drivers/iio/light/ltr501.c if (val == gain[i].scale && val2 == gain[i].uscale) val 733 drivers/iio/light/ltr501.c int val, int val2, long mask) val 749 drivers/iio/light/ltr501.c val, val2); val 764 drivers/iio/light/ltr501.c val, val2); val 784 drivers/iio/light/ltr501.c if (val != 0) { val 806 drivers/iio/light/ltr501.c ret = ltr501_als_write_samp_freq(data, val, val2); val 824 drivers/iio/light/ltr501.c ret = ltr501_ps_write_samp_freq(data, val, val2); val 856 drivers/iio/light/ltr501.c int *val, int *val2) val 870 drivers/iio/light/ltr501.c *val = thresh_data & LTR501_ALS_THRESH_MASK; val 878 drivers/iio/light/ltr501.c *val = thresh_data & LTR501_ALS_THRESH_MASK; val 891 drivers/iio/light/ltr501.c *val = thresh_data & LTR501_PS_THRESH_MASK; val 899 drivers/iio/light/ltr501.c *val = thresh_data & LTR501_PS_THRESH_MASK; val 916 drivers/iio/light/ltr501.c int val, int val2) val 921 drivers/iio/light/ltr501.c if (val < 0) val 926 drivers/iio/light/ltr501.c if (val > LTR501_ALS_THRESH_MASK) val 933 drivers/iio/light/ltr501.c &val, 2); val 940 drivers/iio/light/ltr501.c &val, 2); val 947 drivers/iio/light/ltr501.c if (val > LTR501_PS_THRESH_MASK) val 954 drivers/iio/light/ltr501.c &val, 2); val 961 drivers/iio/light/ltr501.c &val, 2); val 979 drivers/iio/light/ltr501.c int *val, int *val2) val 986 drivers/iio/light/ltr501.c info, val, val2); val 990 drivers/iio/light/ltr501.c *val = *val2 / 1000000; val 1005 drivers/iio/light/ltr501.c int val, int val2) val 1012 drivers/iio/light/ltr501.c info, val, val2); val 1015 drivers/iio/light/ltr501.c val, val2); val 47 drivers/iio/light/lv0104cs.c int val; val 161 drivers/iio/light/lv0104cs.c int *val, int *val2) val 202 drivers/iio/light/lv0104cs.c *val = adc_output * 4; val 207 drivers/iio/light/lv0104cs.c *val = adc_output; val 212 drivers/iio/light/lv0104cs.c *val = adc_output / 2; val 217 drivers/iio/light/lv0104cs.c *val = adc_output / 8; val 228 drivers/iio/light/lv0104cs.c int *val, int *val2, long mask) val 240 drivers/iio/light/lv0104cs.c ret = lv0104cs_get_lux(lv0104cs, val, val2); val 247 drivers/iio/light/lv0104cs.c *val = lv0104cs_calibscales[lv0104cs->calibscale].val; val 253 drivers/iio/light/lv0104cs.c *val = lv0104cs_scales[lv0104cs->scale].val; val 259 drivers/iio/light/lv0104cs.c *val = lv0104cs_int_times[lv0104cs->int_time].val; val 275 drivers/iio/light/lv0104cs.c int val, int val2) val 277 drivers/iio/light/lv0104cs.c int calibscale = val * 1000000 + val2; val 283 drivers/iio/light/lv0104cs.c floor = lv0104cs_calibscales[i].val * 1000000 val 285 drivers/iio/light/lv0104cs.c ceil = lv0104cs_calibscales[i + 1].val * 1000000 val 322 drivers/iio/light/lv0104cs.c int val, int val2) val 328 drivers/iio/light/lv0104cs.c if (val != lv0104cs_scales[i].val) val 346 drivers/iio/light/lv0104cs.c int val, int val2) val 352 drivers/iio/light/lv0104cs.c if (val != lv0104cs_int_times[i].val) val 371 drivers/iio/light/lv0104cs.c int val, int val2, long mask) val 380 drivers/iio/light/lv0104cs.c return lv0104cs_set_calibscale(lv0104cs, val, val2); val 383 drivers/iio/light/lv0104cs.c return lv0104cs_set_scale(lv0104cs, val, val2); val 386 drivers/iio/light/lv0104cs.c return lv0104cs_set_int_time(lv0104cs, val, val2); val 401 drivers/iio/light/lv0104cs.c lv0104cs_calibscales[i].val, val 418 drivers/iio/light/lv0104cs.c lv0104cs_scales[i].val, val 435 drivers/iio/light/lv0104cs.c lv0104cs_int_times[i].val, val 166 drivers/iio/light/max44000.c unsigned int val; val 169 drivers/iio/light/max44000.c ret = regmap_read(data->regmap, MAX44000_REG_CFG_RX, &val); val 172 drivers/iio/light/max44000.c return (val & MAX44000_CFG_RX_ALSTIM_MASK) >> MAX44000_CFG_RX_ALSTIM_SHIFT; val 175 drivers/iio/light/max44000.c static int max44000_write_alstim(struct max44000_data *data, int val) val 179 drivers/iio/light/max44000.c val << MAX44000_CFG_RX_ALSTIM_SHIFT); val 184 drivers/iio/light/max44000.c unsigned int val; val 187 drivers/iio/light/max44000.c ret = regmap_read(data->regmap, MAX44000_REG_CFG_RX, &val); val 190 drivers/iio/light/max44000.c return (val & MAX44000_CFG_RX_ALSPGA_MASK) >> MAX44000_CFG_RX_ALSPGA_SHIFT; val 193 drivers/iio/light/max44000.c static int max44000_write_alspga(struct max44000_data *data, int val) val 197 drivers/iio/light/max44000.c val << MAX44000_CFG_RX_ALSPGA_SHIFT); val 203 drivers/iio/light/max44000.c __be16 val; val 207 drivers/iio/light/max44000.c &val, sizeof(val)); val 214 drivers/iio/light/max44000.c regval = be16_to_cpu(val); val 231 drivers/iio/light/max44000.c static int max44000_write_led_current_raw(struct max44000_data *data, int val) val 234 drivers/iio/light/max44000.c if (val < 0 || val > MAX44000_LED_CURRENT_MAX) val 236 drivers/iio/light/max44000.c if (val >= 8) val 237 drivers/iio/light/max44000.c val += 4; val 239 drivers/iio/light/max44000.c MAX44000_LED_CURRENT_MASK, val); val 258 drivers/iio/light/max44000.c int *val, int *val2, long mask) val 274 drivers/iio/light/max44000.c *val = ret; val 283 drivers/iio/light/max44000.c *val = regval; val 292 drivers/iio/light/max44000.c *val = ret; val 303 drivers/iio/light/max44000.c *val = 10; val 314 drivers/iio/light/max44000.c *val = (1 << MAX44000_ALSPGA_MAX_SHIFT); val 331 drivers/iio/light/max44000.c *val = 0; val 342 drivers/iio/light/max44000.c int val, int val2, long mask) val 349 drivers/iio/light/max44000.c ret = max44000_write_led_current_raw(data, val); val 353 drivers/iio/light/max44000.c s64 valns = val * NSEC_PER_SEC + val2; val 362 drivers/iio/light/max44000.c s64 valus = val * USEC_PER_SEC + val2; val 121 drivers/iio/light/max44009.c int val, int val2) val 127 drivers/iio/light/max44009.c ns = val * NSEC_PER_SEC + val2; val 150 drivers/iio/light/max44009.c struct iio_chan_spec const *chan, int val, val 158 drivers/iio/light/max44009.c ret = max44009_write_int_time(data, val, val2); val 247 drivers/iio/light/max44009.c struct iio_chan_spec const *chan, int *val, val 263 drivers/iio/light/max44009.c *val = lux_raw * MAX44009_SCALE_NUMERATOR; val 277 drivers/iio/light/max44009.c *val = 0; val 343 drivers/iio/light/max44009.c int val, int val2) val 351 drivers/iio/light/max44009.c threshold = max44009_threshold_byte_from_fraction(val, val2); val 402 drivers/iio/light/max44009.c int *val, int *val2) val 415 drivers/iio/light/max44009.c *val = threshold * MAX44009_SCALE_NUMERATOR; val 65 drivers/iio/light/noa1305.c static int noa1305_scale(struct noa1305_priv *priv, int *val, int *val2) val 82 drivers/iio/light/noa1305.c *val = 100; val 86 drivers/iio/light/noa1305.c *val = 100; val 90 drivers/iio/light/noa1305.c *val = 100; val 94 drivers/iio/light/noa1305.c *val = 100; val 98 drivers/iio/light/noa1305.c *val = 1000; val 102 drivers/iio/light/noa1305.c *val = 10000; val 106 drivers/iio/light/noa1305.c *val = 100000; val 110 drivers/iio/light/noa1305.c *val = 1000000; val 130 drivers/iio/light/noa1305.c int *val, int *val2, long mask) val 142 drivers/iio/light/noa1305.c *val = ret; val 151 drivers/iio/light/noa1305.c return noa1305_scale(priv, val, val2); val 95 drivers/iio/light/opt3001.c int val; val 101 drivers/iio/light/opt3001.c .val = 40, val 105 drivers/iio/light/opt3001.c .val = 81, val 109 drivers/iio/light/opt3001.c .val = 163, val 113 drivers/iio/light/opt3001.c .val = 327, val 117 drivers/iio/light/opt3001.c .val = 655, val 121 drivers/iio/light/opt3001.c .val = 1310, val 125 drivers/iio/light/opt3001.c .val = 2620, val 129 drivers/iio/light/opt3001.c .val = 5241, val 133 drivers/iio/light/opt3001.c .val = 10483, val 137 drivers/iio/light/opt3001.c .val = 20966, val 141 drivers/iio/light/opt3001.c .val = 83865, val 146 drivers/iio/light/opt3001.c static int opt3001_find_scale(const struct opt3001 *opt, int val, val 159 drivers/iio/light/opt3001.c if ((val * 1000 + val2 / 1000) <= val 160 drivers/iio/light/opt3001.c (scale->val * 1000 + scale->val2 / 1000)) { val 170 drivers/iio/light/opt3001.c u16 mantissa, int *val, int *val2) val 175 drivers/iio/light/opt3001.c *val = lux / 1000; val 176 drivers/iio/light/opt3001.c *val2 = (lux - (*val * 1000)) * 1000; val 223 drivers/iio/light/opt3001.c static int opt3001_get_lux(struct opt3001 *opt, int *val, int *val2) val 341 drivers/iio/light/opt3001.c opt3001_to_iio_ret(opt, exponent, mantissa, val, val2); val 346 drivers/iio/light/opt3001.c static int opt3001_get_int_time(struct opt3001 *opt, int *val, int *val2) val 348 drivers/iio/light/opt3001.c *val = 0; val 386 drivers/iio/light/opt3001.c struct iio_chan_spec const *chan, int *val, int *val2, val 402 drivers/iio/light/opt3001.c ret = opt3001_get_lux(opt, val, val2); val 405 drivers/iio/light/opt3001.c ret = opt3001_get_int_time(opt, val, val2); val 417 drivers/iio/light/opt3001.c struct iio_chan_spec const *chan, int val, int val2, val 432 drivers/iio/light/opt3001.c if (val != 0) val 445 drivers/iio/light/opt3001.c int *val, int *val2) val 455 drivers/iio/light/opt3001.c opt->high_thresh_mantissa, val, val2); val 459 drivers/iio/light/opt3001.c opt->low_thresh_mantissa, val, val2); val 473 drivers/iio/light/opt3001.c int val, int val2) val 484 drivers/iio/light/opt3001.c if (val < 0) val 489 drivers/iio/light/opt3001.c ret = opt3001_find_scale(opt, val, val2, &exponent); val 491 drivers/iio/light/opt3001.c dev_err(opt->dev, "can't find scale for %d.%06u\n", val, val2); val 495 drivers/iio/light/opt3001.c mantissa = (((val * 1000) + (val2 / 1000)) / 10) >> exponent; val 78 drivers/iio/light/pa12203001.c u8 val; val 209 drivers/iio/light/pa12203001.c struct iio_chan_spec const *chan, int *val, val 235 drivers/iio/light/pa12203001.c *val = le16_to_cpu(reg_word); val 250 drivers/iio/light/pa12203001.c *val = reg_byte; val 263 drivers/iio/light/pa12203001.c *val = 0; val 277 drivers/iio/light/pa12203001.c struct iio_chan_spec const *chan, int val, val 287 drivers/iio/light/pa12203001.c if (val != 0 || ret < 0) val 318 drivers/iio/light/pa12203001.c ret = regmap_write(data->map, regvals[i].reg, regvals[i].val); val 579 drivers/iio/light/rpr0521.c int *val, int *val2) val 588 drivers/iio/light/rpr0521.c *val = rpr0521_gain[chan].gain[idx].scale; val 595 drivers/iio/light/rpr0521.c int val, int val2) val 601 drivers/iio/light/rpr0521.c if (val == rpr0521_gain[chan].gain[i].scale && val 617 drivers/iio/light/rpr0521.c int *val, int *val2) val 631 drivers/iio/light/rpr0521.c *val = rpr0521_samp_freq_i[reg].als_hz; val 636 drivers/iio/light/rpr0521.c *val = rpr0521_samp_freq_i[reg].pxs_hz; val 647 drivers/iio/light/rpr0521.c int val, int val2) val 655 drivers/iio/light/rpr0521.c switch (val) { val 716 drivers/iio/light/rpr0521.c struct iio_chan_spec const *chan, int *val, val 757 drivers/iio/light/rpr0521.c *val = le16_to_cpu(raw_data); val 763 drivers/iio/light/rpr0521.c ret = rpr0521_get_gain(data, chan->address, val, val2); val 772 drivers/iio/light/rpr0521.c ret = rpr0521_read_samp_freq(data, chan->type, val, val2); val 781 drivers/iio/light/rpr0521.c ret = rpr0521_read_ps_offset(data, val); val 794 drivers/iio/light/rpr0521.c struct iio_chan_spec const *chan, int val, val 803 drivers/iio/light/rpr0521.c ret = rpr0521_set_gain(data, chan->address, val, val2); val 811 drivers/iio/light/rpr0521.c val, val2); val 818 drivers/iio/light/rpr0521.c ret = rpr0521_write_ps_offset(data, val); val 616 drivers/iio/light/si1133.c int *val) val 636 drivers/iio/light/si1133.c *val = sign_extend32((buffer[0] << 16) | (buffer[1] << 8) | buffer[2], val 707 drivers/iio/light/si1133.c static int si1133_get_lux(struct si1133_data *data, int *val) val 748 drivers/iio/light/si1133.c *val = lux >> SI1133_LUX_OUTPUT_FRACTION; val 755 drivers/iio/light/si1133.c int *val, int *val2, long mask) val 765 drivers/iio/light/si1133.c err = si1133_get_lux(data, val); val 777 drivers/iio/light/si1133.c err = si1133_measure(data, chan, val); val 791 drivers/iio/light/si1133.c *val = si1133_int_time_table[adc_sens][0]; val 804 drivers/iio/light/si1133.c *val = BIT(adc_sens); val 816 drivers/iio/light/si1133.c *val = adc_sens; val 829 drivers/iio/light/si1133.c int val, int val2, long mask) val 838 drivers/iio/light/si1133.c val = si1133_scale_to_swgain(val, val2); val 839 drivers/iio/light/si1133.c if (val < 0) val 840 drivers/iio/light/si1133.c return val; val 845 drivers/iio/light/si1133.c val); val 850 drivers/iio/light/si1133.c return si1133_set_integration_time(data, 0, val, val2); val 855 drivers/iio/light/si1133.c if (val != 0 && val != 1) val 861 drivers/iio/light/si1133.c val); val 402 drivers/iio/light/si1145.c static int si1145_read_samp_freq(struct si1145_data *data, int *val, int *val2) val 404 drivers/iio/light/si1145.c *val = 32000; val 413 drivers/iio/light/si1145.c static int si1145_store_samp_freq(struct si1145_data *data, int val) val 418 drivers/iio/light/si1145.c if (val <= 0 || val > 32000) val 420 drivers/iio/light/si1145.c meas_rate = 32000 / val; val 600 drivers/iio/light/si1145.c static int si1145_proximity_adcgain_from_scale(int val, int val2) val 602 drivers/iio/light/si1145.c val = find_closest_descending(val, si1145_proximity_scale_available, val 604 drivers/iio/light/si1145.c if (val < 0 || val > 5 || val2 != 0) val 607 drivers/iio/light/si1145.c return val; val 610 drivers/iio/light/si1145.c static int si1145_intensity_adcgain_from_scale(int val, int val2) val 612 drivers/iio/light/si1145.c val = find_closest_descending(val, si1145_intensity_scale_available, val 614 drivers/iio/light/si1145.c if (val < 0 || val > 7 || val2 != 0) val 617 drivers/iio/light/si1145.c return val; val 622 drivers/iio/light/si1145.c int *val, int *val2, long mask) val 645 drivers/iio/light/si1145.c *val = ret; val 654 drivers/iio/light/si1145.c *val = (ret >> SI1145_PS_LED_SHIFT(chan->channel)) val 673 drivers/iio/light/si1145.c *val = 28; val 677 drivers/iio/light/si1145.c *val = 0; val 688 drivers/iio/light/si1145.c *val = si1145_scale_from_adcgain(ret & 0x07); val 698 drivers/iio/light/si1145.c *val = -256 - 11136 + 25 * 35; val 709 drivers/iio/light/si1145.c *val = -si1145_uncompress(ret); val 713 drivers/iio/light/si1145.c return si1145_read_samp_freq(data, val, val2); val 721 drivers/iio/light/si1145.c int val, int val2, long mask) val 731 drivers/iio/light/si1145.c val = si1145_proximity_adcgain_from_scale(val, val2); val 732 drivers/iio/light/si1145.c if (val < 0) val 733 drivers/iio/light/si1145.c return val; val 738 drivers/iio/light/si1145.c val = si1145_intensity_adcgain_from_scale(val, val2); val 739 drivers/iio/light/si1145.c if (val < 0) val 740 drivers/iio/light/si1145.c return val; val 757 drivers/iio/light/si1145.c ret = si1145_param_set(data, reg1, val); val 763 drivers/iio/light/si1145.c ret = si1145_param_set(data, reg2, (~val & 0x07) << 4); val 770 drivers/iio/light/si1145.c if (val < 0 || val > 15 || val2 != 0) val 787 drivers/iio/light/si1145.c ((val & 0x0f) << shift)); val 791 drivers/iio/light/si1145.c return si1145_store_samp_freq(data, val); val 89 drivers/iio/light/st_uvis25_core.c static int st_uvis25_read_oneshot(struct st_uvis25_hw *hw, u8 addr, int *val) val 109 drivers/iio/light/st_uvis25_core.c err = regmap_read(hw->regmap, addr, val); val 116 drivers/iio/light/st_uvis25_core.c int *val, int *val2, long mask) val 137 drivers/iio/light/st_uvis25_core.c ret = st_uvis25_read_oneshot(hw, ch->address, val); val 179 drivers/iio/light/stk3310.c int val, int val2) val 184 drivers/iio/light/stk3310.c if (val == table[i][0] && val2 == table[i][1]) val 196 drivers/iio/light/stk3310.c int *val, int *val2) val 221 drivers/iio/light/stk3310.c *val = be16_to_cpu(buf); val 231 drivers/iio/light/stk3310.c int val, int val2) val 244 drivers/iio/light/stk3310.c if (val < 0 || val > stk3310_ps_max[index]) val 254 drivers/iio/light/stk3310.c buf = cpu_to_be16(val); val 303 drivers/iio/light/stk3310.c int *val, int *val2, long mask) val 329 drivers/iio/light/stk3310.c *val = be16_to_cpu(buf); val 340 drivers/iio/light/stk3310.c *val = stk3310_it_table[index][0]; val 351 drivers/iio/light/stk3310.c *val = stk3310_scale_table[index][0]; val 361 drivers/iio/light/stk3310.c int val, int val2, long mask) val 374 drivers/iio/light/stk3310.c val, val2); val 391 drivers/iio/light/stk3310.c val, val2); val 126 drivers/iio/light/tcs3414.c int *val, int *val2, long mask) val 145 drivers/iio/light/tcs3414.c *val = ret; val 149 drivers/iio/light/tcs3414.c *val = tcs3414_scales[i][0]; val 153 drivers/iio/light/tcs3414.c *val = 0; val 162 drivers/iio/light/tcs3414.c int val, int val2, long mask) val 170 drivers/iio/light/tcs3414.c if (val == tcs3414_scales[i][0] && val 181 drivers/iio/light/tcs3414.c if (val != 0) val 140 drivers/iio/light/tcs3472.c int *val, int *val2, long mask) val 159 drivers/iio/light/tcs3472.c *val = ret; val 162 drivers/iio/light/tcs3472.c *val = tcs3472_agains[data->control & val 166 drivers/iio/light/tcs3472.c *val = 0; val 175 drivers/iio/light/tcs3472.c int val, int val2, long mask) val 185 drivers/iio/light/tcs3472.c if (val == tcs3472_agains[i]) { val 195 drivers/iio/light/tcs3472.c if (val != 0) val 221 drivers/iio/light/tcs3472.c enum iio_event_direction dir, enum iio_event_info info, int *val, val 232 drivers/iio/light/tcs3472.c *val = (dir == IIO_EV_DIR_RISING) ? val 239 drivers/iio/light/tcs3472.c *val = period / USEC_PER_SEC; val 255 drivers/iio/light/tcs3472.c enum iio_event_direction dir, enum iio_event_info info, int val, val 278 drivers/iio/light/tcs3472.c ret = i2c_smbus_write_word_data(data->client, command, val); val 283 drivers/iio/light/tcs3472.c data->high_thresh = val; val 285 drivers/iio/light/tcs3472.c data->low_thresh = val; val 288 drivers/iio/light/tcs3472.c period = val * USEC_PER_SEC + val2; val 444 drivers/iio/light/tsl2563.c int val, val 453 drivers/iio/light/tsl2563.c chip->calib0 = tsl2563_calib_from_sysfs(val); val 455 drivers/iio/light/tsl2563.c chip->calib1 = tsl2563_calib_from_sysfs(val); val 464 drivers/iio/light/tsl2563.c int *val, val 485 drivers/iio/light/tsl2563.c *val = tsl2563_adc_to_lux(calib0, calib1); val 493 drivers/iio/light/tsl2563.c *val = chip->data0; val 495 drivers/iio/light/tsl2563.c *val = chip->data1; val 505 drivers/iio/light/tsl2563.c *val = tsl2563_calib_to_sysfs(chip->calib0); val 507 drivers/iio/light/tsl2563.c *val = tsl2563_calib_to_sysfs(chip->calib1); val 559 drivers/iio/light/tsl2563.c enum iio_event_direction dir, enum iio_event_info info, int *val, val 566 drivers/iio/light/tsl2563.c *val = chip->high_thres; val 569 drivers/iio/light/tsl2563.c *val = chip->low_thres; val 580 drivers/iio/light/tsl2563.c enum iio_event_direction dir, enum iio_event_info info, int val, val 593 drivers/iio/light/tsl2563.c val & 0xFF); val 598 drivers/iio/light/tsl2563.c (val >> 8) & 0xFF); val 600 drivers/iio/light/tsl2563.c chip->high_thres = val; val 602 drivers/iio/light/tsl2563.c chip->low_thres = val; val 361 drivers/iio/light/tsl2583.c u8 val; val 371 drivers/iio/light/tsl2583.c val = 256 - als_count; val 374 drivers/iio/light/tsl2583.c val); val 377 drivers/iio/light/tsl2583.c __func__, val); val 652 drivers/iio/light/tsl2583.c int *val, int *val2, long mask) val 681 drivers/iio/light/tsl2583.c *val = chip->als_cur_info.als_ch0; val 683 drivers/iio/light/tsl2583.c *val = chip->als_cur_info.als_ch1; val 694 drivers/iio/light/tsl2583.c *val = ret; val 700 drivers/iio/light/tsl2583.c *val = chip->als_settings.als_gain_trim; val 706 drivers/iio/light/tsl2583.c *val = gainadj[chip->als_settings.als_gain].mean; val 712 drivers/iio/light/tsl2583.c *val = 0; val 741 drivers/iio/light/tsl2583.c int val, int val2, long mask) val 756 drivers/iio/light/tsl2583.c chip->als_settings.als_gain_trim = val; val 765 drivers/iio/light/tsl2583.c if (gainadj[i].mean == val) { val 774 drivers/iio/light/tsl2583.c if (chan->type == IIO_LIGHT && !val && val2 >= 50 && val 1088 drivers/iio/light/tsl2772.c int val) val 1093 drivers/iio/light/tsl2772.c chip->settings.als_interrupt_en = val ? true : false; val 1095 drivers/iio/light/tsl2772.c chip->settings.prox_interrupt_en = val ? true : false; val 1105 drivers/iio/light/tsl2772.c int val, int val2) val 1116 drivers/iio/light/tsl2772.c chip->settings.als_thresh_high = val; val 1120 drivers/iio/light/tsl2772.c chip->settings.als_thresh_low = val; val 1129 drivers/iio/light/tsl2772.c chip->settings.prox_thres_high = val; val 1133 drivers/iio/light/tsl2772.c chip->settings.prox_thres_low = val; val 1148 drivers/iio/light/tsl2772.c persistence = ((val * 1000000) + val2) / val 1178 drivers/iio/light/tsl2772.c int *val, int *val2) val 1189 drivers/iio/light/tsl2772.c *val = chip->settings.als_thresh_high; val 1192 drivers/iio/light/tsl2772.c *val = chip->settings.als_thresh_low; val 1200 drivers/iio/light/tsl2772.c *val = chip->settings.prox_thres_high; val 1203 drivers/iio/light/tsl2772.c *val = chip->settings.prox_thres_low; val 1226 drivers/iio/light/tsl2772.c *val = filter_delay / 1000000; val 1236 drivers/iio/light/tsl2772.c int *val, val 1247 drivers/iio/light/tsl2772.c *val = chip->als_cur_info.lux; val 1257 drivers/iio/light/tsl2772.c *val = chip->als_cur_info.als_ch0; val 1259 drivers/iio/light/tsl2772.c *val = chip->als_cur_info.als_ch1; val 1263 drivers/iio/light/tsl2772.c *val = chip->prox_data; val 1271 drivers/iio/light/tsl2772.c *val = tsl2772_als_gain[chip->settings.als_gain]; val 1273 drivers/iio/light/tsl2772.c *val = tsl2772_prox_gain[chip->settings.prox_gain]; val 1276 drivers/iio/light/tsl2772.c *val = chip->settings.als_gain_trim; val 1279 drivers/iio/light/tsl2772.c *val = 0; val 1290 drivers/iio/light/tsl2772.c int val, val 1299 drivers/iio/light/tsl2772.c switch (val) { val 1316 drivers/iio/light/tsl2772.c switch (val) { val 1335 drivers/iio/light/tsl2772.c if (val < TSL2772_ALS_GAIN_TRIM_MIN || val 1336 drivers/iio/light/tsl2772.c val > TSL2772_ALS_GAIN_TRIM_MAX) val 1339 drivers/iio/light/tsl2772.c chip->settings.als_gain_trim = val; val 1342 drivers/iio/light/tsl2772.c if (val != 0 || val2 < tsl2772_int_time_avail[chip->id][1] || val 76 drivers/iio/light/tsl4531.c int *val, int *val2, long mask) val 87 drivers/iio/light/tsl4531.c *val = ret; val 91 drivers/iio/light/tsl4531.c *val = 1 << data->int_time; val 102 drivers/iio/light/tsl4531.c *val = 0; val 111 drivers/iio/light/tsl4531.c int val, int val2, long mask) val 118 drivers/iio/light/tsl4531.c if (val != 0) val 158 drivers/iio/light/us5182d.c u8 val; val 422 drivers/iio/light/us5182d.c struct iio_chan_spec const *chan, int *val, val 433 drivers/iio/light/us5182d.c *val = ret; val 439 drivers/iio/light/us5182d.c *val = 0; val 497 drivers/iio/light/us5182d.c struct iio_chan_spec const *chan, int val, val 505 drivers/iio/light/us5182d.c if (val != 0) val 523 drivers/iio/light/us5182d.c enum iio_event_direction dir, u16 val) val 529 drivers/iio/light/us5182d.c US5182D_REG_PXL_TH, val); val 532 drivers/iio/light/us5182d.c US5182D_REG_PXH_TH, val); val 539 drivers/iio/light/us5182d.c enum iio_event_direction dir, enum iio_event_info info, int *val, val 547 drivers/iio/light/us5182d.c *val = data->px_high_th; val 552 drivers/iio/light/us5182d.c *val = data->px_low_th; val 564 drivers/iio/light/us5182d.c enum iio_event_direction dir, enum iio_event_info info, int val, val 570 drivers/iio/light/us5182d.c if (val < 0 || val > USHRT_MAX || val2 != 0) val 577 drivers/iio/light/us5182d.c ret = us5182d_setup_prox(indio_dev, dir, val); val 581 drivers/iio/light/us5182d.c data->px_high_th = val; val 587 drivers/iio/light/us5182d.c ret = us5182d_setup_prox(indio_dev, dir, val); val 591 drivers/iio/light/us5182d.c data->px_low_th = val; val 743 drivers/iio/light/us5182d.c us5182d_regvals[i].val); val 88 drivers/iio/light/vcnl4000.c int (*measure_light)(struct vcnl4000_data *data, int *val); val 89 drivers/iio/light/vcnl4000.c int (*measure_proximity)(struct vcnl4000_data *data, int *val); val 193 drivers/iio/light/vcnl4000.c u8 rdy_mask, u8 data_reg, int *val) val 227 drivers/iio/light/vcnl4000.c *val = ret; val 237 drivers/iio/light/vcnl4000.c struct vcnl4200_channel *chan, int *val) val 258 drivers/iio/light/vcnl4000.c *val = ret; val 263 drivers/iio/light/vcnl4000.c static int vcnl4000_measure_light(struct vcnl4000_data *data, int *val) val 267 drivers/iio/light/vcnl4000.c VCNL4000_AL_RESULT_HI, val); val 270 drivers/iio/light/vcnl4000.c static int vcnl4200_measure_light(struct vcnl4000_data *data, int *val) val 272 drivers/iio/light/vcnl4000.c return vcnl4200_measure(data, &data->vcnl4200_al, val); val 275 drivers/iio/light/vcnl4000.c static int vcnl4000_measure_proximity(struct vcnl4000_data *data, int *val) val 279 drivers/iio/light/vcnl4000.c VCNL4000_PS_RESULT_HI, val); val 282 drivers/iio/light/vcnl4000.c static int vcnl4200_measure_proximity(struct vcnl4000_data *data, int *val) val 284 drivers/iio/light/vcnl4000.c return vcnl4200_measure(data, &data->vcnl4200_ps, val); val 327 drivers/iio/light/vcnl4000.c int *val, int *val2, long mask) val 336 drivers/iio/light/vcnl4000.c ret = data->chip_spec->measure_light(data, val); val 341 drivers/iio/light/vcnl4000.c ret = data->chip_spec->measure_proximity(data, val); val 352 drivers/iio/light/vcnl4000.c *val = 0; val 128 drivers/iio/light/vcnl4035.c int val = enable_drdy ? VCNL4035_MODE_ALS_INT_ENABLE : val 133 drivers/iio/light/vcnl4035.c val); val 172 drivers/iio/light/vcnl4035.c struct iio_chan_spec const *chan, int *val, val 195 drivers/iio/light/vcnl4035.c *val = raw_data; val 202 drivers/iio/light/vcnl4035.c *val = 50; val 204 drivers/iio/light/vcnl4035.c *val = data->als_it_val * 100; val 207 drivers/iio/light/vcnl4035.c *val = 64; val 220 drivers/iio/light/vcnl4035.c int val, int val2, long mask) val 227 drivers/iio/light/vcnl4035.c if (val <= 0 || val > 800) val 236 drivers/iio/light/vcnl4035.c val / 100); val 238 drivers/iio/light/vcnl4035.c data->als_it_val = val / 100; val 251 drivers/iio/light/vcnl4035.c int *val, int *val2) val 259 drivers/iio/light/vcnl4035.c *val = data->als_thresh_high; val 262 drivers/iio/light/vcnl4035.c *val = data->als_thresh_low; val 269 drivers/iio/light/vcnl4035.c *val = data->als_persistence; val 279 drivers/iio/light/vcnl4035.c enum iio_event_direction dir, enum iio_event_info info, int val, val 288 drivers/iio/light/vcnl4035.c if (val < 0 || val > 65535) val 291 drivers/iio/light/vcnl4035.c if (val < data->als_thresh_low) val 294 drivers/iio/light/vcnl4035.c val); val 297 drivers/iio/light/vcnl4035.c data->als_thresh_high = val; val 299 drivers/iio/light/vcnl4035.c if (val > data->als_thresh_high) val 302 drivers/iio/light/vcnl4035.c val); val 305 drivers/iio/light/vcnl4035.c data->als_thresh_low = val; val 310 drivers/iio/light/vcnl4035.c if (val < 0 || val > 8 || hweight8(val) != 1) val 313 drivers/iio/light/vcnl4035.c VCNL4035_ALS_PERS_MASK, val); val 315 drivers/iio/light/vcnl4035.c data->als_persistence = val; val 90 drivers/iio/light/veml6070.c static int veml6070_to_uv_index(unsigned val) val 105 drivers/iio/light/veml6070.c if (val <= uvi[i]) val 113 drivers/iio/light/veml6070.c int *val, int *val2, long mask) val 125 drivers/iio/light/veml6070.c *val = veml6070_to_uv_index(ret); val 127 drivers/iio/light/veml6070.c *val = ret; val 168 drivers/iio/light/vl6180.c static int vl6180_write_byte(struct i2c_client *client, u16 cmd, u8 val) val 177 drivers/iio/light/vl6180.c buf[2] = val; val 188 drivers/iio/light/vl6180.c static int vl6180_write_word(struct i2c_client *client, u16 cmd, u16 val) val 196 drivers/iio/light/vl6180.c buf[1] = cpu_to_be16(val); val 293 drivers/iio/light/vl6180.c int *val, int *val2, long mask) val 303 drivers/iio/light/vl6180.c *val = ret; val 307 drivers/iio/light/vl6180.c *val = data->als_it_ms; val 316 drivers/iio/light/vl6180.c *val = 32000; /* 0.32 * 1000 * 100 */ val 322 drivers/iio/light/vl6180.c *val = 0; /* sensor reports mm, scale to meter */ val 331 drivers/iio/light/vl6180.c *val = data->als_gain_milli; val 359 drivers/iio/light/vl6180.c static int vl6180_set_als_gain(struct vl6180_data *data, int val, int val2) val 363 drivers/iio/light/vl6180.c if (val < 1 || val > 40) val 366 drivers/iio/light/vl6180.c gain = (val * 1000000 + val2) / 1000; val 390 drivers/iio/light/vl6180.c static int vl6180_set_it(struct vl6180_data *data, int val, int val2) val 395 drivers/iio/light/vl6180.c if (val != 0 || it_ms < 1 || it_ms > 512) val 417 drivers/iio/light/vl6180.c int val, int val2, long mask) val 423 drivers/iio/light/vl6180.c return vl6180_set_it(data, val, val2); val 429 drivers/iio/light/vl6180.c return vl6180_set_als_gain(data, val, val2); val 254 drivers/iio/light/zopt2201.c int *val, int *val2, long mask) val 265 drivers/iio/light/zopt2201.c *val = ret; val 271 drivers/iio/light/zopt2201.c *val = ret * 18 * val 278 drivers/iio/light/zopt2201.c *val = zopt2201_gain_als[data->gain].scale; val 281 drivers/iio/light/zopt2201.c *val = zopt2201_gain_uvb[data->gain].scale; val 289 drivers/iio/light/zopt2201.c tmp = div_s64(*val * 1000000ULL, *val2); val 290 drivers/iio/light/zopt2201.c *val = div_s64_rem(tmp, 1000000, val2); val 294 drivers/iio/light/zopt2201.c *val = 0; val 318 drivers/iio/light/zopt2201.c int val, int val2) val 322 drivers/iio/light/zopt2201.c if (val != 0) val 366 drivers/iio/light/zopt2201.c int val, int val2) val 371 drivers/iio/light/zopt2201.c if (val == zopt2201_scale_als[i].scale && val 396 drivers/iio/light/zopt2201.c int val, int val2) val 401 drivers/iio/light/zopt2201.c if (val == zopt2201_scale_uvb[i].scale && val 410 drivers/iio/light/zopt2201.c int val, int val2, long mask) val 416 drivers/iio/light/zopt2201.c return zopt2201_write_resolution(data, val, val2); val 420 drivers/iio/light/zopt2201.c return zopt2201_write_scale_als(data, val, val2); val 422 drivers/iio/light/zopt2201.c return zopt2201_write_scale_uvb(data, val, val2); val 193 drivers/iio/magnetometer/ak8974.c static int ak8974_get_u16_val(struct ak8974 *ak8974, u8 reg, u16 *val) val 201 drivers/iio/magnetometer/ak8974.c *val = le16_to_cpu(bulk); val 206 drivers/iio/magnetometer/ak8974.c static int ak8974_set_u16_val(struct ak8974 *ak8974, u8 reg, u16 val) val 208 drivers/iio/magnetometer/ak8974.c __le16 bulk = cpu_to_le16(val); val 216 drivers/iio/magnetometer/ak8974.c u8 val; val 218 drivers/iio/magnetometer/ak8974.c val = mode ? AK8974_CTRL1_POWER : 0; val 219 drivers/iio/magnetometer/ak8974.c val |= AK8974_CTRL1_FORCE_EN; val 220 drivers/iio/magnetometer/ak8974.c ret = regmap_write(ak8974->map, AK8974_CTRL1, val); val 281 drivers/iio/magnetometer/ak8974.c u8 val; val 294 drivers/iio/magnetometer/ak8974.c val = AK8974_CTRL2_DRDY_EN; val 297 drivers/iio/magnetometer/ak8974.c val |= AK8974_CTRL2_DRDY_POL; val 301 drivers/iio/magnetometer/ak8974.c mask, val); val 316 drivers/iio/magnetometer/ak8974.c unsigned int val; val 333 drivers/iio/magnetometer/ak8974.c ret = regmap_read(ak8974->map, AK8974_STATUS, &val); val 336 drivers/iio/magnetometer/ak8974.c if (val & AK8974_STATUS_DRDY) val 384 drivers/iio/magnetometer/ak8974.c unsigned int val; val 388 drivers/iio/magnetometer/ak8974.c ret = regmap_read(ak8974->map, AK8974_STATUS, &val); val 393 drivers/iio/magnetometer/ak8974.c if (val & AK8974_STATUS_DRDY) { val 406 drivers/iio/magnetometer/ak8974.c unsigned int val; val 409 drivers/iio/magnetometer/ak8974.c ret = regmap_read(ak8974->map, AK8974_SELFTEST, &val); val 412 drivers/iio/magnetometer/ak8974.c if (val != AK8974_SELFTEST_IDLE) { val 429 drivers/iio/magnetometer/ak8974.c ret = regmap_read(ak8974->map, AK8974_SELFTEST, &val); val 432 drivers/iio/magnetometer/ak8974.c if (val != AK8974_SELFTEST_OK) { val 433 drivers/iio/magnetometer/ak8974.c dev_err(dev, "selftest result NOT OK (%02x)\n", val); val 437 drivers/iio/magnetometer/ak8974.c ret = regmap_read(ak8974->map, AK8974_SELFTEST, &val); val 440 drivers/iio/magnetometer/ak8974.c if (val != AK8974_SELFTEST_IDLE) { val 441 drivers/iio/magnetometer/ak8974.c dev_err(dev, "selftest not idle after test (%02x)\n", val); val 539 drivers/iio/magnetometer/ak8974.c int *val, int *val2, val 567 drivers/iio/magnetometer/ak8974.c *val = (s16)le16_to_cpu(hw_values[chan->address]); val 675 drivers/iio/magnetometer/ak8975.c static int ak8975_read_axis(struct iio_dev *indio_dev, int index, int *val) val 705 drivers/iio/magnetometer/ak8975.c *val = clamp_t(s16, buff, -def->range, def->range); val 716 drivers/iio/magnetometer/ak8975.c int *val, int *val2, val 723 drivers/iio/magnetometer/ak8975.c return ak8975_read_axis(indio_dev, chan->address, val); val 725 drivers/iio/magnetometer/ak8975.c *val = 0; val 282 drivers/iio/magnetometer/bmc150_magn.c static int bmc150_magn_get_odr(struct bmc150_magn_data *data, int *val) val 294 drivers/iio/magnetometer/bmc150_magn.c *val = bmc150_magn_samp_freq_table[i].freq; val 301 drivers/iio/magnetometer/bmc150_magn.c static int bmc150_magn_set_odr(struct bmc150_magn_data *data, int val) val 307 drivers/iio/magnetometer/bmc150_magn.c if (bmc150_magn_samp_freq_table[i].freq == val) { val 363 drivers/iio/magnetometer/bmc150_magn.c s16 val; val 372 drivers/iio/magnetometer/bmc150_magn.c val = ((s16)(((u16)((((s32)xyz1) << 14) / rhall)) - ((u16)0x4000))); val 373 drivers/iio/magnetometer/bmc150_magn.c val = ((s16)((((s32)x) * ((((((((s32)tregs->xy2) * ((((s32)val) * val 374 drivers/iio/magnetometer/bmc150_magn.c ((s32)val)) >> 7)) + (((s32)val) * val 379 drivers/iio/magnetometer/bmc150_magn.c return (s32)val; val 385 drivers/iio/magnetometer/bmc150_magn.c s16 val; val 394 drivers/iio/magnetometer/bmc150_magn.c val = ((s16)(((u16)((((s32)xyz1) << 14) / rhall)) - ((u16)0x4000))); val 395 drivers/iio/magnetometer/bmc150_magn.c val = ((s16)((((s32)y) * ((((((((s32)tregs->xy2) * ((((s32)val) * val 396 drivers/iio/magnetometer/bmc150_magn.c ((s32)val)) >> 7)) + (((s32)val) * val 401 drivers/iio/magnetometer/bmc150_magn.c return (s32)val; val 407 drivers/iio/magnetometer/bmc150_magn.c s32 val; val 417 drivers/iio/magnetometer/bmc150_magn.c val = (((((s32)(z - z4)) << 15) - ((((s32)z3) * ((s32)(((s16)rhall) - val 421 drivers/iio/magnetometer/bmc150_magn.c return val; val 456 drivers/iio/magnetometer/bmc150_magn.c int *val, int *val2, long mask) val 480 drivers/iio/magnetometer/bmc150_magn.c *val = values[chan->scan_index]; val 496 drivers/iio/magnetometer/bmc150_magn.c *val = 0; val 500 drivers/iio/magnetometer/bmc150_magn.c ret = bmc150_magn_get_odr(data, val); val 512 drivers/iio/magnetometer/bmc150_magn.c *val = BMC150_MAGN_REGVAL_TO_REPXY(tmp); val 519 drivers/iio/magnetometer/bmc150_magn.c *val = BMC150_MAGN_REGVAL_TO_REPZ(tmp); val 531 drivers/iio/magnetometer/bmc150_magn.c int val, int val2, long mask) val 538 drivers/iio/magnetometer/bmc150_magn.c if (val > data->max_odr) val 541 drivers/iio/magnetometer/bmc150_magn.c ret = bmc150_magn_set_odr(data, val); val 548 drivers/iio/magnetometer/bmc150_magn.c if (val < 1 || val > 511) val 551 drivers/iio/magnetometer/bmc150_magn.c ret = bmc150_magn_set_max_odr(data, val, 0, 0); val 560 drivers/iio/magnetometer/bmc150_magn.c (val)); val 564 drivers/iio/magnetometer/bmc150_magn.c if (val < 1 || val > 256) val 567 drivers/iio/magnetometer/bmc150_magn.c ret = bmc150_magn_set_max_odr(data, 0, val, 0); val 576 drivers/iio/magnetometer/bmc150_magn.c (val)); val 146 drivers/iio/magnetometer/hid-sensor-magn-3d.c int *val, int *val2, val 155 drivers/iio/magnetometer/hid-sensor-magn-3d.c *val = 0; val 164 drivers/iio/magnetometer/hid-sensor-magn-3d.c *val = sensor_hub_input_attr_get_raw_value( val 171 drivers/iio/magnetometer/hid-sensor-magn-3d.c *val = 0; val 184 drivers/iio/magnetometer/hid-sensor-magn-3d.c *val = magn_state->magn_flux_attr.scale_pre_decml; val 189 drivers/iio/magnetometer/hid-sensor-magn-3d.c *val = magn_state->rot_attr.scale_pre_decml; val 200 drivers/iio/magnetometer/hid-sensor-magn-3d.c *val = magn_state->magn_flux_attr.value_offset; val 204 drivers/iio/magnetometer/hid-sensor-magn-3d.c *val = magn_state->rot_attr.value_offset; val 213 drivers/iio/magnetometer/hid-sensor-magn-3d.c &magn_state->magn_flux_attributes, val, val2); val 219 drivers/iio/magnetometer/hid-sensor-magn-3d.c &magn_state->magn_flux_attributes, val, val2); val 223 drivers/iio/magnetometer/hid-sensor-magn-3d.c &magn_state->rot_attributes, val, val2); val 240 drivers/iio/magnetometer/hid-sensor-magn-3d.c int val, val 250 drivers/iio/magnetometer/hid-sensor-magn-3d.c &magn_state->magn_flux_attributes, val, val2); val 256 drivers/iio/magnetometer/hid-sensor-magn-3d.c &magn_state->magn_flux_attributes, val, val2); val 260 drivers/iio/magnetometer/hid-sensor-magn-3d.c &magn_state->rot_attributes, val, val2); val 151 drivers/iio/magnetometer/hmc5843_core.c unsigned int val; val 155 drivers/iio/magnetometer/hmc5843_core.c ret = regmap_read(data->regmap, HMC5843_STATUS_REG, &val); val 158 drivers/iio/magnetometer/hmc5843_core.c if (val & HMC5843_DATA_READY) val 173 drivers/iio/magnetometer/hmc5843_core.c int idx, int *val) val 190 drivers/iio/magnetometer/hmc5843_core.c *val = sign_extend32(be16_to_cpu(values[idx]), 15); val 211 drivers/iio/magnetometer/hmc5843_core.c unsigned int val; val 214 drivers/iio/magnetometer/hmc5843_core.c ret = regmap_read(data->regmap, HMC5843_CONFIG_REG_A, &val); val 218 drivers/iio/magnetometer/hmc5843_core.c return val & HMC5843_MEAS_CONF_MASK; val 303 drivers/iio/magnetometer/hmc5843_core.c int val, int val2) val 308 drivers/iio/magnetometer/hmc5843_core.c if (val == data->variant->regval_to_samp_freq[i][0] && val 350 drivers/iio/magnetometer/hmc5843_core.c static int hmc5843_get_scale_index(struct hmc5843_data *data, int val, int val2) val 354 drivers/iio/magnetometer/hmc5843_core.c if (val) val 366 drivers/iio/magnetometer/hmc5843_core.c int *val, int *val2, long mask) val 374 drivers/iio/magnetometer/hmc5843_core.c return hmc5843_read_measurement(data, chan->scan_index, val); val 380 drivers/iio/magnetometer/hmc5843_core.c *val = 0; val 388 drivers/iio/magnetometer/hmc5843_core.c *val = data->variant->regval_to_samp_freq[rval][0]; val 397 drivers/iio/magnetometer/hmc5843_core.c int val, int val2, long mask) val 404 drivers/iio/magnetometer/hmc5843_core.c rate = hmc5843_get_samp_freq_index(data, val, val2); val 410 drivers/iio/magnetometer/hmc5843_core.c range = hmc5843_get_scale_index(data, val, val2); val 128 drivers/iio/magnetometer/mag3110.c int val, int val2) val 131 drivers/iio/magnetometer/mag3110.c if (val == vals[n][0] && val2 == vals[n][1]) val 151 drivers/iio/magnetometer/mag3110.c int val, int val2) val 153 drivers/iio/magnetometer/mag3110.c return mag3110_get_int_plus_micros_index(mag3110_samp_freq, 8, val, val 223 drivers/iio/magnetometer/mag3110.c static int mag3110_change_config(struct mag3110_data *data, u8 reg, u8 val) val 251 drivers/iio/magnetometer/mag3110.c ret = i2c_smbus_write_byte_data(data->client, reg, val); val 270 drivers/iio/magnetometer/mag3110.c int *val, int *val2, long mask) val 287 drivers/iio/magnetometer/mag3110.c *val = sign_extend32( val 303 drivers/iio/magnetometer/mag3110.c *val = sign_extend32(ret, 7); val 316 drivers/iio/magnetometer/mag3110.c *val = 0; val 320 drivers/iio/magnetometer/mag3110.c *val = 1000; val 327 drivers/iio/magnetometer/mag3110.c *val = mag3110_samp_freq[i][0]; val 335 drivers/iio/magnetometer/mag3110.c *val = sign_extend32(ret >> 1, 14); val 343 drivers/iio/magnetometer/mag3110.c int val, int val2, long mask) val 354 drivers/iio/magnetometer/mag3110.c rate = mag3110_get_samp_freq_index(data, val, val2); val 370 drivers/iio/magnetometer/mag3110.c if (val < -10000 || val > 10000) { val 375 drivers/iio/magnetometer/mag3110.c MAG3110_OFF_X + 2 * chan->scan_index, val << 1); val 134 drivers/iio/magnetometer/mmc35240.c int val; val 169 drivers/iio/magnetometer/mmc35240.c int val, int val2) val 174 drivers/iio/magnetometer/mmc35240.c if (mmc35240_samp_freq[i].val == val && val 314 drivers/iio/magnetometer/mmc35240.c __le16 buf[], int *val) val 332 drivers/iio/magnetometer/mmc35240.c *val = (raw[AXIS_X] - nfo) * 1000 / sens[AXIS_X]; val 335 drivers/iio/magnetometer/mmc35240.c *val = (raw[AXIS_Y] - nfo) * 1000 / sens[AXIS_Y] - val 339 drivers/iio/magnetometer/mmc35240.c *val = (raw[AXIS_Y] - nfo) * 1000 / sens[AXIS_Y] + val 346 drivers/iio/magnetometer/mmc35240.c *val = (*val) * data->axis_coef[index] / data->axis_scale[index]; val 352 drivers/iio/magnetometer/mmc35240.c struct iio_chan_spec const *chan, int *val, val 367 drivers/iio/magnetometer/mmc35240.c ret = mmc35240_raw_to_mgauss(data, chan->address, buf, val); val 372 drivers/iio/magnetometer/mmc35240.c *val = 0; val 386 drivers/iio/magnetometer/mmc35240.c *val = mmc35240_samp_freq[i].val; val 395 drivers/iio/magnetometer/mmc35240.c struct iio_chan_spec const *chan, int val, val 403 drivers/iio/magnetometer/mmc35240.c i = mmc35240_get_samp_freq_index(data, val, val2); val 160 drivers/iio/magnetometer/rm3100-core.c unsigned int val; val 177 drivers/iio/magnetometer/rm3100-core.c ret = regmap_read(regmap, RM3100_REG_STATUS, &val); val 181 drivers/iio/magnetometer/rm3100-core.c if ((val & RM3100_STATUS_DRDY) != RM3100_STATUS_DRDY) { val 192 drivers/iio/magnetometer/rm3100-core.c &val); val 196 drivers/iio/magnetometer/rm3100-core.c if (val & RM3100_STATUS_DRDY) val 206 drivers/iio/magnetometer/rm3100-core.c static int rm3100_read_mag(struct rm3100_data *data, int idx, int *val) val 226 drivers/iio/magnetometer/rm3100-core.c *val = sign_extend32((buffer[0] << 16) | (buffer[1] << 8) | buffer[2], val 288 drivers/iio/magnetometer/rm3100-core.c static int rm3100_get_samp_freq(struct rm3100_data *data, int *val, int *val2) val 298 drivers/iio/magnetometer/rm3100-core.c *val = rm3100_samp_rates[tmp - RM3100_TMRC_OFFSET][0]; val 304 drivers/iio/magnetometer/rm3100-core.c static int rm3100_set_cycle_count(struct rm3100_data *data, int val) val 310 drivers/iio/magnetometer/rm3100-core.c ret = regmap_write(data->regmap, RM3100_REG_CC_X + 2 * i, val); val 320 drivers/iio/magnetometer/rm3100-core.c switch (val) { val 339 drivers/iio/magnetometer/rm3100-core.c static int rm3100_set_samp_freq(struct iio_dev *indio_dev, int val, int val2) val 354 drivers/iio/magnetometer/rm3100-core.c if (val == rm3100_samp_rates[i][0] && val 368 drivers/iio/magnetometer/rm3100-core.c if (val == 600 && cycle_count == 200) { val 372 drivers/iio/magnetometer/rm3100-core.c } else if (val != 600 && cycle_count == 100) { val 401 drivers/iio/magnetometer/rm3100-core.c int *val, int *val2, long mask) val 412 drivers/iio/magnetometer/rm3100-core.c ret = rm3100_read_mag(data, chan->scan_index, val); val 417 drivers/iio/magnetometer/rm3100-core.c *val = 0; val 422 drivers/iio/magnetometer/rm3100-core.c return rm3100_get_samp_freq(data, val, val2); val 430 drivers/iio/magnetometer/rm3100-core.c int val, int val2, long mask) val 434 drivers/iio/magnetometer/rm3100-core.c return rm3100_set_samp_freq(indio_dev, val, val2); val 387 drivers/iio/magnetometer/st_magn_core.c struct iio_chan_spec const *ch, int *val, val 395 drivers/iio/magnetometer/st_magn_core.c err = st_sensors_read_info_raw(indio_dev, ch, val); val 401 drivers/iio/magnetometer/st_magn_core.c *val = 0; val 409 drivers/iio/magnetometer/st_magn_core.c *val = mdata->odr; val 420 drivers/iio/magnetometer/st_magn_core.c struct iio_chan_spec const *chan, int val, int val2, long mask) val 432 drivers/iio/magnetometer/st_magn_core.c err = st_sensors_set_odr(indio_dev, val); val 87 drivers/iio/multiplexer/iio-mux.c int *val, int *val2, long mask) val 99 drivers/iio/multiplexer/iio-mux.c ret = iio_read_channel_raw(mux->parent, val); val 103 drivers/iio/multiplexer/iio-mux.c ret = iio_read_channel_scale(mux->parent, val, val2); val 145 drivers/iio/multiplexer/iio-mux.c int val, int val2, long mask) val 157 drivers/iio/multiplexer/iio-mux.c ret = iio_write_channel_raw(mux->parent, val); val 95 drivers/iio/orientation/hid-sensor-incl-3d.c int *val, int *val2, val 104 drivers/iio/orientation/hid-sensor-incl-3d.c *val = 0; val 113 drivers/iio/orientation/hid-sensor-incl-3d.c *val = sensor_hub_input_attr_get_raw_value( val 128 drivers/iio/orientation/hid-sensor-incl-3d.c *val = incl_state->scale_pre_decml; val 133 drivers/iio/orientation/hid-sensor-incl-3d.c *val = incl_state->value_offset; val 138 drivers/iio/orientation/hid-sensor-incl-3d.c &incl_state->common_attributes, val, val2); val 142 drivers/iio/orientation/hid-sensor-incl-3d.c &incl_state->common_attributes, val, val2); val 155 drivers/iio/orientation/hid-sensor-incl-3d.c int val, val 165 drivers/iio/orientation/hid-sensor-incl-3d.c &incl_state->common_attributes, val, val2); val 169 drivers/iio/orientation/hid-sensor-incl-3d.c &incl_state->common_attributes, val, val2); val 109 drivers/iio/orientation/hid-sensor-rotation.c int val, val 119 drivers/iio/orientation/hid-sensor-rotation.c &rot_state->common_attributes, val, val2); val 123 drivers/iio/orientation/hid-sensor-rotation.c &rot_state->common_attributes, val, val2); val 62 drivers/iio/potentiometer/ad5272.c static int ad5272_write(struct ad5272_data *data, int reg, int val) val 66 drivers/iio/potentiometer/ad5272.c data->buf[0] = (reg << 2) | ((val >> 8) & 0x3); val 67 drivers/iio/potentiometer/ad5272.c data->buf[1] = (u8)val; val 75 drivers/iio/potentiometer/ad5272.c static int ad5272_read(struct ad5272_data *data, int reg, int *val) val 91 drivers/iio/potentiometer/ad5272.c *val = ((data->buf[0] & 0x3) << 8) | data->buf[1]; val 100 drivers/iio/potentiometer/ad5272.c int *val, int *val2, long mask) val 107 drivers/iio/potentiometer/ad5272.c ret = ad5272_read(data, AD5272_RDAC_RD, val); val 108 drivers/iio/potentiometer/ad5272.c *val = *val >> data->cfg->shift; val 112 drivers/iio/potentiometer/ad5272.c *val = 1000 * data->cfg->kohms; val 122 drivers/iio/potentiometer/ad5272.c int val, int val2, long mask) val 129 drivers/iio/potentiometer/ad5272.c if (val >= data->cfg->max_pos || val < 0 || val2) val 132 drivers/iio/potentiometer/ad5272.c return ad5272_write(data, AD5272_RDAC_WR, val << data->cfg->shift); val 59 drivers/iio/potentiometer/ds1803.c int *val, int *val2, long mask) val 73 drivers/iio/potentiometer/ds1803.c *val = result[pot]; val 77 drivers/iio/potentiometer/ds1803.c *val = 1000 * data->cfg->kohms; val 87 drivers/iio/potentiometer/ds1803.c int val, int val2, long mask) val 97 drivers/iio/potentiometer/ds1803.c if (val > DS1803_MAX_POS || val < 0) val 104 drivers/iio/potentiometer/ds1803.c return i2c_smbus_write_byte_data(data->client, DS1803_WRITE(pot), val); val 45 drivers/iio/potentiometer/max5432.c int *val, int *val2, long mask) val 55 drivers/iio/potentiometer/max5432.c *val = data->ohm; val 63 drivers/iio/potentiometer/max5432.c int val, int val2, long mask) val 71 drivers/iio/potentiometer/max5432.c if (val < 0 || val > MAX5432_MAX_POS) val 78 drivers/iio/potentiometer/max5432.c data_byte = val << 3; val 64 drivers/iio/potentiometer/max5481.c static int max5481_write_cmd(struct max5481_data *data, u8 cmd, u16 val) val 72 drivers/iio/potentiometer/max5481.c data->msg[1] = val >> 2; val 73 drivers/iio/potentiometer/max5481.c data->msg[2] = (val & 0x3) << 6; val 87 drivers/iio/potentiometer/max5481.c int *val, int *val2, long mask) val 94 drivers/iio/potentiometer/max5481.c *val = 1000 * data->cfg->kohms; val 102 drivers/iio/potentiometer/max5481.c int val, int val2, long mask) val 109 drivers/iio/potentiometer/max5481.c if (val < 0 || val > MAX5481_MAX_POS) val 112 drivers/iio/potentiometer/max5481.c return max5481_write_cmd(data, MAX5481_WRITE_WIPER, val); val 51 drivers/iio/potentiometer/max5487.c int *val, int *val2, long mask) val 58 drivers/iio/potentiometer/max5487.c *val = 1000 * data->kohms; val 66 drivers/iio/potentiometer/max5487.c int val, int val2, long mask) val 73 drivers/iio/potentiometer/max5487.c if (val < 0 || val > MAX5487_MAX_POS) val 76 drivers/iio/potentiometer/max5487.c return max5487_write_cmd(data->spi, chan->address | val); val 58 drivers/iio/potentiometer/mcp4018.c int *val, int *val2, long mask) val 68 drivers/iio/potentiometer/mcp4018.c *val = ret; val 71 drivers/iio/potentiometer/mcp4018.c *val = 1000 * data->cfg->kohms; val 81 drivers/iio/potentiometer/mcp4018.c int val, int val2, long mask) val 87 drivers/iio/potentiometer/mcp4018.c if (val > MCP4018_WIPER_MAX || val < 0) val 94 drivers/iio/potentiometer/mcp4018.c return i2c_smbus_write_byte(data->client, val); val 82 drivers/iio/potentiometer/mcp41010.c int *val, int *val2, long mask) val 89 drivers/iio/potentiometer/mcp41010.c *val = data->value[channel]; val 93 drivers/iio/potentiometer/mcp41010.c *val = 1000 * data->cfg->kohms; val 103 drivers/iio/potentiometer/mcp41010.c int val, int val2, long mask) val 112 drivers/iio/potentiometer/mcp41010.c if (val > MCP41010_WIPER_MAX || val < 0) val 119 drivers/iio/potentiometer/mcp41010.c data->buf[1] = val & 0xff; val 123 drivers/iio/potentiometer/mcp41010.c data->value[channel] = val; val 166 drivers/iio/potentiometer/mcp4131.c int *val, int *val2, long mask) val 191 drivers/iio/potentiometer/mcp4131.c *val = MCP4131_RAW(data->buf); val 197 drivers/iio/potentiometer/mcp4131.c *val = 1000 * data->cfg->kohms; val 207 drivers/iio/potentiometer/mcp4131.c int val, int val2, long mask) val 215 drivers/iio/potentiometer/mcp4131.c if (val > data->cfg->max_pos || val < 0) val 226 drivers/iio/potentiometer/mcp4131.c data->buf[0] |= MCP4131_WRITE | (val >> 8); val 227 drivers/iio/potentiometer/mcp4131.c data->buf[1] = val & 0xFF; /* 8 bits here */ val 141 drivers/iio/potentiometer/mcp4531.c int *val, int *val2, long mask) val 153 drivers/iio/potentiometer/mcp4531.c *val = ret; val 156 drivers/iio/potentiometer/mcp4531.c *val = 1000 * data->cfg->kohms; val 184 drivers/iio/potentiometer/mcp4531.c int val, int val2, long mask) val 191 drivers/iio/potentiometer/mcp4531.c if (val > data->cfg->avail[2] || val < 0) val 199 drivers/iio/potentiometer/mcp4531.c MCP4531_WRITE | address | (val >> 8), val 200 drivers/iio/potentiometer/mcp4531.c val & 0xff); val 65 drivers/iio/potentiometer/tpl0102.c int *val, int *val2, long mask) val 71 drivers/iio/potentiometer/tpl0102.c int ret = regmap_read(data->regmap, chan->channel, val); val 76 drivers/iio/potentiometer/tpl0102.c *val = 1000 * data->cfg->kohms; val 104 drivers/iio/potentiometer/tpl0102.c int val, int val2, long mask) val 111 drivers/iio/potentiometer/tpl0102.c if (val > data->cfg->avail[2] || val < 0) val 114 drivers/iio/potentiometer/tpl0102.c return regmap_write(data->regmap, chan->channel, val); val 103 drivers/iio/potentiostat/lmp91000.c static int lmp91000_read(struct lmp91000_data *data, int channel, int *val) val 129 drivers/iio/potentiostat/lmp91000.c *val = data->buffer[data->chan_select]; val 139 drivers/iio/potentiostat/lmp91000.c int ret, val; val 143 drivers/iio/potentiostat/lmp91000.c ret = lmp91000_read(data, LMP91000_REG_MODECN_3LEAD, &val); val 145 drivers/iio/potentiostat/lmp91000.c data->buffer[0] = val; val 157 drivers/iio/potentiostat/lmp91000.c int *val, int *val2, long mask) val 169 drivers/iio/potentiostat/lmp91000.c ret = lmp91000_read(data, chan->address, val); val 180 drivers/iio/potentiostat/lmp91000.c *val, &tmp, 1); val 188 drivers/iio/potentiostat/lmp91000.c *val = (LMP91000_TEMP_BASE + i) * 1000; val 193 drivers/iio/potentiostat/lmp91000.c return iio_read_channel_offset(data->adc_chan, val, val2); val 195 drivers/iio/potentiostat/lmp91000.c return iio_read_channel_scale(data->adc_chan, val, val2); val 209 drivers/iio/potentiostat/lmp91000.c unsigned int reg, val; val 212 drivers/iio/potentiostat/lmp91000.c ret = of_property_read_u32(np, "ti,tia-gain-ohm", &val); val 218 drivers/iio/potentiostat/lmp91000.c val = 0; val 223 drivers/iio/potentiostat/lmp91000.c if (lmp91000_tia_gain[i] == val) { val 231 drivers/iio/potentiostat/lmp91000.c dev_err(dev, "invalid ti,tia-gain-ohm %d\n", val); val 235 drivers/iio/potentiostat/lmp91000.c ret = of_property_read_u32(np, "ti,rload-ohm", &val); val 237 drivers/iio/potentiostat/lmp91000.c val = 100; val 238 drivers/iio/potentiostat/lmp91000.c dev_info(dev, "no ti,rload-ohm defined, default to %d\n", val); val 243 drivers/iio/potentiostat/lmp91000.c if (lmp91000_rload[i] == val) { val 251 drivers/iio/potentiostat/lmp91000.c dev_err(dev, "invalid ti,rload-ohm %d\n", val); val 264 drivers/iio/potentiostat/lmp91000.c static int lmp91000_buffer_cb(const void *val, void *private) val 269 drivers/iio/potentiostat/lmp91000.c data->buffer[data->chan_select] = *((int *)val); val 100 drivers/iio/pressure/abp060mg.c static int abp060mg_get_measurement(struct abp_state *state, int *val) val 125 drivers/iio/pressure/abp060mg.c *val = pressure; val 131 drivers/iio/pressure/abp060mg.c struct iio_chan_spec const *chan, int *val, val 141 drivers/iio/pressure/abp060mg.c ret = abp060mg_get_measurement(state, val); val 144 drivers/iio/pressure/abp060mg.c *val = state->offset; val 148 drivers/iio/pressure/abp060mg.c *val = state->scale; val 327 drivers/iio/pressure/bmp280-core.c int *val) val 352 drivers/iio/pressure/bmp280-core.c if (val) { val 353 drivers/iio/pressure/bmp280-core.c *val = comp_temp * 10; val 361 drivers/iio/pressure/bmp280-core.c int *val, int *val2) val 388 drivers/iio/pressure/bmp280-core.c *val = comp_press; val 394 drivers/iio/pressure/bmp280-core.c static int bmp280_read_humid(struct bmp280_data *data, int *val, int *val2) val 421 drivers/iio/pressure/bmp280-core.c *val = comp_humidity * 1000 / 1024; val 428 drivers/iio/pressure/bmp280-core.c int *val, int *val2, long mask) val 440 drivers/iio/pressure/bmp280-core.c ret = data->chip_info->read_humid(data, val, val2); val 443 drivers/iio/pressure/bmp280-core.c ret = data->chip_info->read_press(data, val, val2); val 446 drivers/iio/pressure/bmp280-core.c ret = data->chip_info->read_temp(data, val); val 456 drivers/iio/pressure/bmp280-core.c *val = 1 << data->oversampling_humid; val 460 drivers/iio/pressure/bmp280-core.c *val = 1 << data->oversampling_press; val 464 drivers/iio/pressure/bmp280-core.c *val = 1 << data->oversampling_temp; val 485 drivers/iio/pressure/bmp280-core.c int val) val 492 drivers/iio/pressure/bmp280-core.c if (avail[i] == val) { val 493 drivers/iio/pressure/bmp280-core.c data->oversampling_humid = ilog2(val); val 502 drivers/iio/pressure/bmp280-core.c int val) val 509 drivers/iio/pressure/bmp280-core.c if (avail[i] == val) { val 510 drivers/iio/pressure/bmp280-core.c data->oversampling_temp = ilog2(val); val 519 drivers/iio/pressure/bmp280-core.c int val) val 526 drivers/iio/pressure/bmp280-core.c if (avail[i] == val) { val 527 drivers/iio/pressure/bmp280-core.c data->oversampling_press = ilog2(val); val 537 drivers/iio/pressure/bmp280-core.c int val, int val2, long mask) val 548 drivers/iio/pressure/bmp280-core.c ret = bmp280_write_oversampling_ratio_humid(data, val); val 551 drivers/iio/pressure/bmp280-core.c ret = bmp280_write_oversampling_ratio_press(data, val); val 554 drivers/iio/pressure/bmp280-core.c ret = bmp280_write_oversampling_ratio_temp(data, val); val 746 drivers/iio/pressure/bmp280-core.c static int bmp180_read_adc_temp(struct bmp280_data *data, int *val) val 759 drivers/iio/pressure/bmp280-core.c *val = be16_to_cpu(tmp); val 819 drivers/iio/pressure/bmp280-core.c static int bmp180_read_temp(struct bmp280_data *data, int *val) val 834 drivers/iio/pressure/bmp280-core.c if (val) { val 835 drivers/iio/pressure/bmp280-core.c *val = comp_temp * 100; val 842 drivers/iio/pressure/bmp280-core.c static int bmp180_read_adc_press(struct bmp280_data *data, int *val) val 856 drivers/iio/pressure/bmp280-core.c *val = (be32_to_cpu(tmp) >> 8) >> (8 - oss); val 897 drivers/iio/pressure/bmp280-core.c int *val, int *val2) val 914 drivers/iio/pressure/bmp280-core.c *val = comp_press; val 32 drivers/iio/pressure/bmp280-spi.c size_t reg_size, void *val, size_t val_size) val 37 drivers/iio/pressure/bmp280-spi.c return spi_write_then_read(spi, reg, reg_size, val, val_size); val 39 drivers/iio/pressure/cros_ec_baro.c int *val, int *val2, long mask) val 55 drivers/iio/pressure/cros_ec_baro.c *val = data; val 66 drivers/iio/pressure/cros_ec_baro.c *val = st->core.resp->sensor_range.ret; val 73 drivers/iio/pressure/cros_ec_baro.c ret = cros_ec_sensors_core_read(&st->core, chan, val, val2, val 85 drivers/iio/pressure/cros_ec_baro.c int val, int val2, long mask) val 95 drivers/iio/pressure/cros_ec_baro.c st->core.param.sensor_range.data = val; val 104 drivers/iio/pressure/cros_ec_baro.c ret = cros_ec_sensors_core_write(&st->core, chan, val, val2, val 165 drivers/iio/pressure/dps310.c int val; val 167 drivers/iio/pressure/dps310.c rc = regmap_read(data->regmap, DPS310_PRS_CFG, &val); val 171 drivers/iio/pressure/dps310.c return BIT(val & GENMASK(2, 0)); val 177 drivers/iio/pressure/dps310.c int val; val 179 drivers/iio/pressure/dps310.c rc = regmap_read(data->regmap, DPS310_TMP_CFG, &val); val 187 drivers/iio/pressure/dps310.c return BIT(val & GENMASK(2, 0)); val 191 drivers/iio/pressure/dps310.c static int dps310_set_pres_precision(struct dps310_data *data, int val) val 196 drivers/iio/pressure/dps310.c if (val < 0 || val > 128) val 199 drivers/iio/pressure/dps310.c shift_en = val >= 16 ? DPS310_PRS_SHIFT_EN : 0; val 206 drivers/iio/pressure/dps310.c DPS310_PRS_PRC_BITS, ilog2(val)); val 210 drivers/iio/pressure/dps310.c static int dps310_set_temp_precision(struct dps310_data *data, int val) val 215 drivers/iio/pressure/dps310.c if (val < 0 || val > 128) val 218 drivers/iio/pressure/dps310.c shift_en = val >= 16 ? DPS310_TMP_SHIFT_EN : 0; val 225 drivers/iio/pressure/dps310.c DPS310_TMP_PRC_BITS, ilog2(val)); val 231 drivers/iio/pressure/dps310.c u8 val; val 236 drivers/iio/pressure/dps310.c val = ilog2(freq) << 4; val 239 drivers/iio/pressure/dps310.c DPS310_PRS_RATE_BITS, val); val 245 drivers/iio/pressure/dps310.c u8 val; val 250 drivers/iio/pressure/dps310.c val = ilog2(freq) << 4; val 253 drivers/iio/pressure/dps310.c DPS310_TMP_RATE_BITS, val); val 259 drivers/iio/pressure/dps310.c int val; val 261 drivers/iio/pressure/dps310.c rc = regmap_read(data->regmap, DPS310_PRS_CFG, &val); val 265 drivers/iio/pressure/dps310.c return BIT((val & DPS310_PRS_RATE_BITS) >> 4); val 271 drivers/iio/pressure/dps310.c int val; val 273 drivers/iio/pressure/dps310.c rc = regmap_read(data->regmap, DPS310_TMP_CFG, &val); val 277 drivers/iio/pressure/dps310.c return BIT((val & DPS310_TMP_RATE_BITS) >> 4); val 307 drivers/iio/pressure/dps310.c u8 val[3]; val 322 drivers/iio/pressure/dps310.c rc = regmap_bulk_read(data->regmap, DPS310_PRS_BASE, val, sizeof(val)); val 326 drivers/iio/pressure/dps310.c raw = (val[0] << 16) | (val[1] << 8) | val[2]; val 338 drivers/iio/pressure/dps310.c u8 val[3]; val 341 drivers/iio/pressure/dps310.c rc = regmap_bulk_read(data->regmap, DPS310_TMP_BASE, val, sizeof(val)); val 345 drivers/iio/pressure/dps310.c raw = (val[0] << 16) | (val[1] << 8) | val[2]; val 414 drivers/iio/pressure/dps310.c struct iio_chan_spec const *chan, int val, val 427 drivers/iio/pressure/dps310.c rc = dps310_set_pres_samp_freq(data, val); val 431 drivers/iio/pressure/dps310.c rc = dps310_set_temp_samp_freq(data, val); val 443 drivers/iio/pressure/dps310.c rc = dps310_set_pres_precision(data, val); val 447 drivers/iio/pressure/dps310.c rc = dps310_set_temp_precision(data, val); val 543 drivers/iio/pressure/dps310.c static int dps310_read_pressure(struct dps310_data *data, int *val, int *val2, val 554 drivers/iio/pressure/dps310.c *val = rc; val 566 drivers/iio/pressure/dps310.c *val = rc; val 575 drivers/iio/pressure/dps310.c *val = rc; val 602 drivers/iio/pressure/dps310.c static int dps310_read_temp(struct dps310_data *data, int *val, int *val2, val 613 drivers/iio/pressure/dps310.c *val = rc; val 625 drivers/iio/pressure/dps310.c *val = rc; val 633 drivers/iio/pressure/dps310.c *val = rc; val 643 drivers/iio/pressure/dps310.c int *val, int *val2, long mask) val 649 drivers/iio/pressure/dps310.c return dps310_read_pressure(data, val, val2, mask); val 652 drivers/iio/pressure/dps310.c return dps310_read_temp(data, val, val2, mask); val 61 drivers/iio/pressure/hid-sensor-press.c int *val, int *val2, val 70 drivers/iio/pressure/hid-sensor-press.c *val = 0; val 87 drivers/iio/pressure/hid-sensor-press.c *val = sensor_hub_input_attr_get_raw_value( val 96 drivers/iio/pressure/hid-sensor-press.c *val = 0; val 102 drivers/iio/pressure/hid-sensor-press.c *val = press_state->scale_pre_decml; val 107 drivers/iio/pressure/hid-sensor-press.c *val = press_state->value_offset; val 112 drivers/iio/pressure/hid-sensor-press.c &press_state->common_attributes, val, val2); val 116 drivers/iio/pressure/hid-sensor-press.c &press_state->common_attributes, val, val2); val 129 drivers/iio/pressure/hid-sensor-press.c int val, val 139 drivers/iio/pressure/hid-sensor-press.c &press_state->common_attributes, val, val2); val 143 drivers/iio/pressure/hid-sensor-press.c &press_state->common_attributes, val, val2); val 162 drivers/iio/pressure/hp03.c int *val, int *val2, long mask) val 178 drivers/iio/pressure/hp03.c *val = priv->pressure; val 181 drivers/iio/pressure/hp03.c *val = priv->temp; val 190 drivers/iio/pressure/hp03.c *val = 0; val 194 drivers/iio/pressure/hp03.c *val = 10; val 85 drivers/iio/pressure/hp206c.c static inline int hp206c_write_reg(struct i2c_client *client, u8 reg, u8 val) val 88 drivers/iio/pressure/hp206c.c HP206C_CMD_WRITE_REG | reg, val); val 127 drivers/iio/pressure/hp206c.c int val; val 129 drivers/iio/pressure/hp206c.c val = hp206c_read_reg(client, HP206C_REG_PARA); val 130 drivers/iio/pressure/hp206c.c if (val < 0) val 131 drivers/iio/pressure/hp206c.c return val; val 133 drivers/iio/pressure/hp206c.c val |= HP206C_FLAG_CMPS_EN; val 135 drivers/iio/pressure/hp206c.c val &= ~HP206C_FLAG_CMPS_EN; val 137 drivers/iio/pressure/hp206c.c return hp206c_write_reg(client, HP206C_REG_PARA, val); val 203 drivers/iio/pressure/hp206c.c struct iio_chan_spec const *chan, int *val, val 217 drivers/iio/pressure/hp206c.c *val = hp206c_osr_rates[data->temp_osr_index]; val 222 drivers/iio/pressure/hp206c.c *val = hp206c_osr_rates[data->pres_osr_index]; val 245 drivers/iio/pressure/hp206c.c *val = sign_extend32(ret, 19); val 260 drivers/iio/pressure/hp206c.c *val = ret; val 272 drivers/iio/pressure/hp206c.c *val = 0; val 278 drivers/iio/pressure/hp206c.c *val = 0; val 297 drivers/iio/pressure/hp206c.c int val, int val2, long mask) val 307 drivers/iio/pressure/hp206c.c data->temp_osr_index = find_closest_descending(val, val 311 drivers/iio/pressure/hp206c.c data->pres_osr_index = find_closest_descending(val, val 45 drivers/iio/pressure/mpl115.c static int mpl115_comp_pressure(struct mpl115_data *data, int *val, int *val2) val 75 drivers/iio/pressure/mpl115.c *val = kpa >> 4; val 98 drivers/iio/pressure/mpl115.c int *val, int *val2, long mask) val 105 drivers/iio/pressure/mpl115.c ret = mpl115_comp_pressure(data, val, val2); val 114 drivers/iio/pressure/mpl115.c *val = ret >> 6; val 117 drivers/iio/pressure/mpl115.c *val = -605; val 121 drivers/iio/pressure/mpl115.c *val = -186; val 74 drivers/iio/pressure/mpl3115.c int *val, int *val2, long mask) val 99 drivers/iio/pressure/mpl3115.c *val = be32_to_cpu(tmp) >> 12; val 114 drivers/iio/pressure/mpl3115.c *val = sign_extend32(be32_to_cpu(tmp) >> 20, 11); val 128 drivers/iio/pressure/mpl3115.c *val = 0; val 132 drivers/iio/pressure/mpl3115.c *val = 0; val 235 drivers/iio/pressure/ms5611_core.c int *val, int *val2, long mask) val 252 drivers/iio/pressure/ms5611_core.c *val = temp * 10; val 255 drivers/iio/pressure/ms5611_core.c *val = pressure / 1000; val 264 drivers/iio/pressure/ms5611_core.c *val = 10; val 267 drivers/iio/pressure/ms5611_core.c *val = 0; val 278 drivers/iio/pressure/ms5611_core.c *val = (int)st->temp_osr->rate; val 280 drivers/iio/pressure/ms5611_core.c *val = (int)st->pressure_osr->rate; val 304 drivers/iio/pressure/ms5611_core.c int val, int val2, long mask) val 314 drivers/iio/pressure/ms5611_core.c osr = ms5611_find_osr(val, ms5611_avail_temp_osr, val 317 drivers/iio/pressure/ms5611_core.c osr = ms5611_find_osr(val, ms5611_avail_pressure_osr, val 43 drivers/iio/pressure/ms5611_i2c.c static int ms5611_i2c_read_adc(struct ms5611_state *st, s32 *val) val 53 drivers/iio/pressure/ms5611_i2c.c *val = (buf[0] << 16) | (buf[1] << 8) | buf[2]; val 38 drivers/iio/pressure/ms5611_spi.c static int ms5611_spi_read_adc(struct device *dev, s32 *val) val 48 drivers/iio/pressure/ms5611_spi.c *val = (buf[0] << 16) | (buf[1] << 8) | buf[2]; val 37 drivers/iio/pressure/ms5637.c struct iio_chan_spec const *channel, int *val, val 55 drivers/iio/pressure/ms5637.c *val = temperature; val 59 drivers/iio/pressure/ms5637.c *val = pressure / 1000; val 67 drivers/iio/pressure/ms5637.c *val = ms5637_samp_freq[dev_data->res_index]; val 77 drivers/iio/pressure/ms5637.c int val, int val2, long mask) val 86 drivers/iio/pressure/ms5637.c if (val == ms5637_samp_freq[i]) val 566 drivers/iio/pressure/st_pressure_core.c int val, val 577 drivers/iio/pressure/st_pressure_core.c err = st_sensors_set_odr(indio_dev, val); val 586 drivers/iio/pressure/st_pressure_core.c struct iio_chan_spec const *ch, int *val, val 594 drivers/iio/pressure/st_pressure_core.c err = st_sensors_read_info_raw(indio_dev, ch, val); val 602 drivers/iio/pressure/st_pressure_core.c *val = 0; val 606 drivers/iio/pressure/st_pressure_core.c *val = MCELSIUS_PER_CELSIUS; val 617 drivers/iio/pressure/st_pressure_core.c *val = ST_PRESS_MILLI_CELSIUS_OFFSET * val 628 drivers/iio/pressure/st_pressure_core.c *val = press_data->odr; val 65 drivers/iio/pressure/t5403.c static int t5403_comp_pressure(struct t5403_data *data, int *val, int *val2) val 98 drivers/iio/pressure/t5403.c *val = X / 1000; val 106 drivers/iio/pressure/t5403.c static int t5403_comp_temp(struct t5403_data *data, int *val) val 118 drivers/iio/pressure/t5403.c *val = ((s32) T5403_C_U16(1) * t_r / 0x100 + val 128 drivers/iio/pressure/t5403.c int *val, int *val2, long mask) val 137 drivers/iio/pressure/t5403.c ret = t5403_comp_pressure(data, val, val2); val 142 drivers/iio/pressure/t5403.c ret = t5403_comp_temp(data, val); val 150 drivers/iio/pressure/t5403.c *val = 0; val 160 drivers/iio/pressure/t5403.c int val, int val2, long mask) val 167 drivers/iio/pressure/t5403.c if (val != 0) val 449 drivers/iio/pressure/zpa2326.c unsigned int val; val 456 drivers/iio/pressure/zpa2326.c err = regmap_read(regs, ZPA2326_STATUS_REG, &val); val 461 drivers/iio/pressure/zpa2326.c if (val & ZPA2326_STATUS_FIFO_E) val 472 drivers/iio/pressure/zpa2326.c err = regmap_read(regs, ZPA2326_PRESS_OUT_H_REG, &val); val 485 drivers/iio/pressure/zpa2326.c err = regmap_read(regs, ZPA2326_STATUS_REG, &val); val 489 drivers/iio/pressure/zpa2326.c } while (!(val & ZPA2326_STATUS_FIFO_E)); val 516 drivers/iio/pressure/zpa2326.c unsigned int val; val 520 drivers/iio/pressure/zpa2326.c err = regmap_read(regs, ZPA2326_STATUS_REG, &val); val 526 drivers/iio/pressure/zpa2326.c if (val & ZPA2326_STATUS_P_OR) { val 554 drivers/iio/pressure/zpa2326.c err = regmap_read(regs, ZPA2326_STATUS_REG, &val); val 559 drivers/iio/pressure/zpa2326.c } while (!(val & ZPA2326_STATUS_FIFO_E)); val 787 drivers/iio/pressure/zpa2326.c unsigned int val; val 802 drivers/iio/pressure/zpa2326.c priv->result = regmap_read(priv->regmap, ZPA2326_INT_SOURCE_REG, &val); val 811 drivers/iio/pressure/zpa2326.c if (!(val & ZPA2326_INT_SOURCE_DATA_READY)) { val 819 drivers/iio/pressure/zpa2326.c val); val 860 drivers/iio/pressure/zpa2326.c unsigned int val; val 875 drivers/iio/pressure/zpa2326.c regmap_read(private->regmap, ZPA2326_INT_SOURCE_REG, &val); val 938 drivers/iio/pressure/zpa2326.c unsigned int val; val 952 drivers/iio/pressure/zpa2326.c err = regmap_read(regs, ZPA2326_CTRL_REG0_REG, &val); val 956 drivers/iio/pressure/zpa2326.c if (!(val & ZPA2326_CTRL_REG0_ONE_SHOT)) val 974 drivers/iio/pressure/zpa2326.c err = regmap_read(regs, ZPA2326_STATUS_REG, &val); val 978 drivers/iio/pressure/zpa2326.c if (!(val & ZPA2326_STATUS_P_DA)) { val 1318 drivers/iio/pressure/zpa2326.c unsigned int val; val 1343 drivers/iio/pressure/zpa2326.c err = regmap_read(priv->regmap, ZPA2326_INT_SOURCE_REG, &val); val 1478 drivers/iio/pressure/zpa2326.c int *val, val 1484 drivers/iio/pressure/zpa2326.c return zpa2326_sample_oneshot(indio_dev, chan->type, val); val 1493 drivers/iio/pressure/zpa2326.c *val = 1; val 1512 drivers/iio/pressure/zpa2326.c *val = 6; val 1523 drivers/iio/pressure/zpa2326.c *val = -17683000; val 1532 drivers/iio/pressure/zpa2326.c *val = zpa2326_get_frequency(indio_dev); val 1542 drivers/iio/pressure/zpa2326.c int val, val 1549 drivers/iio/pressure/zpa2326.c return zpa2326_set_frequency(indio_dev, val); val 85 drivers/iio/proximity/as3935.c static int as3935_read(struct as3935_state *st, unsigned int reg, int *val) val 94 drivers/iio/proximity/as3935.c *val = ret; val 101 drivers/iio/proximity/as3935.c unsigned int val) val 106 drivers/iio/proximity/as3935.c buf[1] = val; val 116 drivers/iio/proximity/as3935.c int val, ret; val 118 drivers/iio/proximity/as3935.c ret = as3935_read(st, AS3935_AFE_GAIN, &val); val 121 drivers/iio/proximity/as3935.c val = (val & AS3935_AFE_MASK) >> 1; val 123 drivers/iio/proximity/as3935.c return sprintf(buf, "%d\n", val); val 131 drivers/iio/proximity/as3935.c unsigned long val; val 134 drivers/iio/proximity/as3935.c ret = kstrtoul((const char *) buf, 10, &val); val 138 drivers/iio/proximity/as3935.c if (val > AS3935_AFE_GAIN_MAX) val 141 drivers/iio/proximity/as3935.c as3935_write(st, AS3935_AFE_GAIN, val << 1); val 178 drivers/iio/proximity/as3935.c int *val, val 190 drivers/iio/proximity/as3935.c ret = as3935_read(st, AS3935_DATA, val); val 195 drivers/iio/proximity/as3935.c if (*val == AS3935_DATA_MASK) val 202 drivers/iio/proximity/as3935.c *val *= 1000; val 205 drivers/iio/proximity/as3935.c *val = 1000; val 224 drivers/iio/proximity/as3935.c int val, ret; val 226 drivers/iio/proximity/as3935.c ret = as3935_read(st, AS3935_DATA, &val); val 230 drivers/iio/proximity/as3935.c st->buffer[0] = val & AS3935_DATA_MASK; val 245 drivers/iio/proximity/as3935.c int val; val 250 drivers/iio/proximity/as3935.c ret = as3935_read(st, AS3935_INT, &val); val 256 drivers/iio/proximity/as3935.c val &= AS3935_INT_MASK; val 258 drivers/iio/proximity/as3935.c switch (val) { val 304 drivers/iio/proximity/as3935.c int val, ret; val 307 drivers/iio/proximity/as3935.c ret = as3935_read(st, AS3935_AFE_GAIN, &val); val 310 drivers/iio/proximity/as3935.c val |= AS3935_AFE_PWR_BIT; val 312 drivers/iio/proximity/as3935.c ret = as3935_write(st, AS3935_AFE_GAIN, val); val 324 drivers/iio/proximity/as3935.c int val, ret; val 327 drivers/iio/proximity/as3935.c ret = as3935_read(st, AS3935_AFE_GAIN, &val); val 330 drivers/iio/proximity/as3935.c val &= ~AS3935_AFE_PWR_BIT; val 331 drivers/iio/proximity/as3935.c ret = as3935_write(st, AS3935_AFE_GAIN, val); val 199 drivers/iio/proximity/isl29501.c u32 *val) val 221 drivers/iio/proximity/isl29501.c *val = (msb << 8) + lsb; val 300 drivers/iio/proximity/isl29501.c unsigned int val) val 320 drivers/iio/proximity/isl29501.c isl29501->shadow_coeffs[coeff] = val; val 327 drivers/iio/proximity/isl29501.c int val) val 348 drivers/iio/proximity/isl29501.c return isl29501_register_write(isl29501, reg, val); val 351 drivers/iio/proximity/isl29501.c static unsigned int isl29501_find_corr_exp(unsigned int val, val 367 drivers/iio/proximity/isl29501.c if (val <= max_mantissa) val 370 drivers/iio/proximity/isl29501.c while ((val >> exp) > max_mantissa) { val 387 drivers/iio/proximity/isl29501.c unsigned int val; val 392 drivers/iio/proximity/isl29501.c ret = kstrtouint(buf, 10, &val); val 398 drivers/iio/proximity/isl29501.c if (val > U16_MAX) val 401 drivers/iio/proximity/isl29501.c ret = isl29501_register_write(isl29501, reg, val); val 411 drivers/iio/proximity/isl29501.c if (val > (U8_MAX << ISL29501_MAX_EXP_VAL)) val 415 drivers/iio/proximity/isl29501.c ret = isl29501_set_shadow_coeff(isl29501, reg, val); val 658 drivers/iio/proximity/isl29501.c int *val, int *val2) val 666 drivers/iio/proximity/isl29501.c *val = 3331; val 672 drivers/iio/proximity/isl29501.c *val = 0; val 678 drivers/iio/proximity/isl29501.c *val = 35; val 693 drivers/iio/proximity/isl29501.c *val = 0; val 698 drivers/iio/proximity/isl29501.c *val = isl29501_current_scale_table[current_scale - 1][0]; val 704 drivers/iio/proximity/isl29501.c *val = 125; val 732 drivers/iio/proximity/isl29501.c int *val, int *val2) val 744 drivers/iio/proximity/isl29501.c *val = isl29501_int_time[inttime][0]; val 751 drivers/iio/proximity/isl29501.c int *val, int *val2) val 768 drivers/iio/proximity/isl29501.c *val = freq; val 775 drivers/iio/proximity/isl29501.c struct iio_chan_spec const *chan, int *val, val 782 drivers/iio/proximity/isl29501.c return isl29501_get_raw(isl29501, chan, val); val 784 drivers/iio/proximity/isl29501.c return isl29501_get_scale(isl29501, chan, val, val2); val 786 drivers/iio/proximity/isl29501.c return isl29501_get_inttime(isl29501, val, val2); val 788 drivers/iio/proximity/isl29501.c return isl29501_get_freq(isl29501, val, val2); val 790 drivers/iio/proximity/isl29501.c return isl29501_get_calibbias(isl29501, chan, val); val 809 drivers/iio/proximity/isl29501.c int val, int val2) val 814 drivers/iio/proximity/isl29501.c if (isl29501_int_time[i][0] == val && val 827 drivers/iio/proximity/isl29501.c int val, int val2) val 835 drivers/iio/proximity/isl29501.c if (isl29501_current_scale_table[i][0] == val && val 865 drivers/iio/proximity/isl29501.c int val, int val2) val 871 drivers/iio/proximity/isl29501.c freq = val * 1000000 + val2 % 1000000; val 885 drivers/iio/proximity/isl29501.c int val, int val2, long mask) val 891 drivers/iio/proximity/isl29501.c return isl29501_set_raw(isl29501, chan, val); val 893 drivers/iio/proximity/isl29501.c return isl29501_set_inttime(isl29501, val, val2); val 895 drivers/iio/proximity/isl29501.c return isl29501_set_freq(isl29501, val, val2); val 897 drivers/iio/proximity/isl29501.c return isl29501_set_scale(isl29501, chan, val, val2); val 899 drivers/iio/proximity/isl29501.c return isl29501_set_calibbias(isl29501, chan, val); val 134 drivers/iio/proximity/mb1232.c struct iio_chan_spec const *channel, int *val, val 148 drivers/iio/proximity/mb1232.c *val = ret; val 152 drivers/iio/proximity/mb1232.c *val = 0; val 43 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c int (*xfer)(struct lidar_data *data, u8 reg, u8 *val, int len); val 64 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static int lidar_i2c_xfer(struct lidar_data *data, u8 reg, u8 *val, int len) val 78 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c msg[1].buf = (char *) val; val 85 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static int lidar_smbus_xfer(struct lidar_data *data, u8 reg, u8 *val, int len) val 108 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c *(val++) = ret; val 117 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c u8 val; val 119 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c ret = data->xfer(data, reg, &val, 1); val 123 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c return val; val 126 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static inline int lidar_write_control(struct lidar_data *data, int val) val 128 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c return i2c_smbus_write_byte_data(data->client, LIDAR_REG_CONTROL, val); val 131 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static inline int lidar_write_power(struct lidar_data *data, int val) val 134 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c LIDAR_REG_PWR_CONTROL, val); val 193 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c int *val, int *val2, long mask) val 207 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c *val = reg; val 214 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c *val = 0; val 69 drivers/iio/proximity/rfd77402.c u16 val; val 163 drivers/iio/proximity/rfd77402.c int *val, int *val2, long mask) val 175 drivers/iio/proximity/rfd77402.c *val = ret; val 179 drivers/iio/proximity/rfd77402.c *val = 0; val 238 drivers/iio/proximity/rfd77402.c rf77402_tof_config[i].val); val 182 drivers/iio/proximity/srf04.c struct iio_chan_spec const *channel, int *val, val 196 drivers/iio/proximity/srf04.c *val = ret; val 203 drivers/iio/proximity/srf04.c *val = 0; val 204 drivers/iio/proximity/srf08.c struct iio_chan_spec const *channel, int *val, val 218 drivers/iio/proximity/srf08.c *val = ret; val 222 drivers/iio/proximity/srf08.c *val = 0; val 260 drivers/iio/proximity/srf08.c static ssize_t srf08_write_range_mm(struct srf08_data *data, unsigned int val) val 267 drivers/iio/proximity/srf08.c ret = val / 43 - 1; val 268 drivers/iio/proximity/srf08.c mod = val % 43; val 284 drivers/iio/proximity/srf08.c data->range_mm = val; val 347 drivers/iio/proximity/srf08.c unsigned int val) val 353 drivers/iio/proximity/srf08.c if (!val) val 357 drivers/iio/proximity/srf08.c if (val && (val == data->chip_info->sensitivity_avail[i])) { val 374 drivers/iio/proximity/srf08.c data->sensitivity = val; val 388 drivers/iio/proximity/srf08.c unsigned int val; val 390 drivers/iio/proximity/srf08.c ret = kstrtouint(buf, 10, &val); val 394 drivers/iio/proximity/srf08.c ret = srf08_write_sensitivity(data, val); val 135 drivers/iio/proximity/sx9500.c int val; val 266 drivers/iio/proximity/sx9500.c int *val) val 279 drivers/iio/proximity/sx9500.c *val = be16_to_cpu(regval); val 291 drivers/iio/proximity/sx9500.c unsigned int val; val 293 drivers/iio/proximity/sx9500.c ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0, &val); val 297 drivers/iio/proximity/sx9500.c val = (val & SX9500_SCAN_PERIOD_MASK) >> SX9500_SCAN_PERIOD_SHIFT; val 299 drivers/iio/proximity/sx9500.c msleep(sx9500_scan_period_table[val]); val 306 drivers/iio/proximity/sx9500.c int *val) val 332 drivers/iio/proximity/sx9500.c ret = sx9500_read_prox_data(data, chan, val); val 360 drivers/iio/proximity/sx9500.c int *val, int *val2) val 373 drivers/iio/proximity/sx9500.c *val = sx9500_samp_freq_table[regval].val; val 381 drivers/iio/proximity/sx9500.c int *val, int *val2, long mask) val 393 drivers/iio/proximity/sx9500.c ret = sx9500_read_proximity(data, chan, val); val 397 drivers/iio/proximity/sx9500.c return sx9500_read_samp_freq(data, val, val2); val 407 drivers/iio/proximity/sx9500.c int val, int val2) val 412 drivers/iio/proximity/sx9500.c if (val == sx9500_samp_freq_table[i].val && val 432 drivers/iio/proximity/sx9500.c int val, int val2, long mask) val 440 drivers/iio/proximity/sx9500.c return sx9500_set_samp_freq(data, val, val2); val 469 drivers/iio/proximity/sx9500.c unsigned int val, chan; val 472 drivers/iio/proximity/sx9500.c ret = regmap_read(data->regmap, SX9500_REG_STAT, &val); val 478 drivers/iio/proximity/sx9500.c val >>= SX9500_PROXSTAT_SHIFT; val 482 drivers/iio/proximity/sx9500.c bool new_prox = val & BIT(chan); val 503 drivers/iio/proximity/sx9500.c unsigned int val; val 507 drivers/iio/proximity/sx9500.c ret = regmap_read(data->regmap, SX9500_REG_IRQ_SRC, &val); val 513 drivers/iio/proximity/sx9500.c if (val & (SX9500_CLOSE_IRQ | SX9500_FAR_IRQ)) val 516 drivers/iio/proximity/sx9500.c if (val & SX9500_CONVDONE_IRQ) val 653 drivers/iio/proximity/sx9500.c int val, bit, ret, i = 0; val 660 drivers/iio/proximity/sx9500.c &val); val 664 drivers/iio/proximity/sx9500.c data->buffer[i++] = val; val 799 drivers/iio/proximity/sx9500.c unsigned int val; val 808 drivers/iio/proximity/sx9500.c ret = regmap_read(data->regmap, SX9500_REG_STAT, &val); val 811 drivers/iio/proximity/sx9500.c if (!(val & SX9500_COMPSTAT_MASK)) val 830 drivers/iio/proximity/sx9500.c unsigned int val; val 848 drivers/iio/proximity/sx9500.c ret = regmap_read(data->regmap, SX9500_REG_IRQ_SRC, &val); val 42 drivers/iio/proximity/vl53l0x-i2c.c int *val) val 75 drivers/iio/proximity/vl53l0x-i2c.c *val = (buffer[10] << 8) + buffer[11]; val 90 drivers/iio/proximity/vl53l0x-i2c.c int *val, int *val2, long mask) val 100 drivers/iio/proximity/vl53l0x-i2c.c ret = vl53l0x_read_proximity(data, chan, val); val 106 drivers/iio/proximity/vl53l0x-i2c.c *val = 0; val 49 drivers/iio/resolver/ad2s1200.c int *val, val 61 drivers/iio/resolver/ad2s1200.c *val = 0; val 66 drivers/iio/resolver/ad2s1200.c *val = 6; val 90 drivers/iio/resolver/ad2s1200.c *val = be16_to_cpup(&st->rx) >> 4; val 93 drivers/iio/resolver/ad2s1200.c *val = sign_extend32(be16_to_cpup(&st->rx) >> 4, 11); val 32 drivers/iio/resolver/ad2s90.c int *val, val 45 drivers/iio/resolver/ad2s90.c *val = 6283; /* mV */ val 55 drivers/iio/resolver/ad2s90.c *val = (((u16)(st->rx[0])) << 4) | ((st->rx[1] & 0xF0) >> 4); val 53 drivers/iio/temperature/hid-sensor-temperature.c int *val, int *val2, long mask) val 63 drivers/iio/temperature/hid-sensor-temperature.c *val = sensor_hub_input_attr_get_raw_value( val 77 drivers/iio/temperature/hid-sensor-temperature.c *val = temp_st->scale_pre_decml; val 82 drivers/iio/temperature/hid-sensor-temperature.c *val = temp_st->value_offset; val 87 drivers/iio/temperature/hid-sensor-temperature.c &temp_st->common_attributes, val, val2); val 91 drivers/iio/temperature/hid-sensor-temperature.c &temp_st->common_attributes, val, val2); val 99 drivers/iio/temperature/hid-sensor-temperature.c int val, int val2, long mask) val 106 drivers/iio/temperature/hid-sensor-temperature.c &temp_st->common_attributes, val, val2); val 109 drivers/iio/temperature/hid-sensor-temperature.c &temp_st->common_attributes, val, val2); val 69 drivers/iio/temperature/max31856.c u8 val[], unsigned int read_size) val 71 drivers/iio/temperature/max31856.c return spi_write_then_read(data->spi, ®, 1, val, read_size); val 75 drivers/iio/temperature/max31856.c unsigned int val) val 80 drivers/iio/temperature/max31856.c buf[1] = val; val 131 drivers/iio/temperature/max31856.c int *val) val 146 drivers/iio/temperature/max31856.c *val = (reg_val[0] << 16 | reg_val[1] << 8 | reg_val[2]) >> 5; val 149 drivers/iio/temperature/max31856.c *val -= 0x80000; val 163 drivers/iio/temperature/max31856.c *val = (reg_val[1] << 8 | reg_val[2]) >> 2; val 165 drivers/iio/temperature/max31856.c *val += offset_cjto; val 168 drivers/iio/temperature/max31856.c *val -= 0x4000; val 187 drivers/iio/temperature/max31856.c int *val, int *val2, long mask) val 194 drivers/iio/temperature/max31856.c ret = max31856_thermocouple_read(data, chan, val); val 202 drivers/iio/temperature/max31856.c *val = 15; val 208 drivers/iio/temperature/max31856.c *val = 7; val 116 drivers/iio/temperature/maxim_thermocouple.c struct iio_chan_spec const *chan, int *val) val 127 drivers/iio/temperature/maxim_thermocouple.c *val = be16_to_cpu(buf16); val 131 drivers/iio/temperature/maxim_thermocouple.c *val = be32_to_cpu(buf32); val 141 drivers/iio/temperature/maxim_thermocouple.c if (*val & data->chip->status_bit) val 144 drivers/iio/temperature/maxim_thermocouple.c *val = sign_extend32(*val >> shift, chan->scan_type.realbits - 1); val 169 drivers/iio/temperature/maxim_thermocouple.c int *val, int *val2, long mask) val 180 drivers/iio/temperature/maxim_thermocouple.c ret = maxim_thermocouple_read(data, chan, val); val 190 drivers/iio/temperature/maxim_thermocouple.c *val = 62; val 195 drivers/iio/temperature/maxim_thermocouple.c *val = 250; /* 1000 * 0.25 */ val 218 drivers/iio/temperature/mlx90614.c struct iio_chan_spec const *channel, int *val, val 260 drivers/iio/temperature/mlx90614.c *val = ret; val 263 drivers/iio/temperature/mlx90614.c *val = MLX90614_CONST_OFFSET_DEC; val 267 drivers/iio/temperature/mlx90614.c *val = MLX90614_CONST_SCALE; val 281 drivers/iio/temperature/mlx90614.c *val = 1; val 284 drivers/iio/temperature/mlx90614.c *val = 0; val 299 drivers/iio/temperature/mlx90614.c *val = mlx90614_iir_values[ret & MLX90614_CONFIG_IIR_MASK] / 100; val 309 drivers/iio/temperature/mlx90614.c struct iio_chan_spec const *channel, int val, val 317 drivers/iio/temperature/mlx90614.c if (val < 0 || val2 < 0 || val > 1 || (val == 1 && val2 != 0)) val 319 drivers/iio/temperature/mlx90614.c val = val * MLX90614_CONST_RAW_EMISSIVITY_MAX + val 325 drivers/iio/temperature/mlx90614.c val); val 331 drivers/iio/temperature/mlx90614.c if (val < 0 || val2 < 0) val 337 drivers/iio/temperature/mlx90614.c val * 100 + val2 / 10000); val 426 drivers/iio/temperature/mlx90632.c static int mlx90632_calc_object_dsp105(struct mlx90632_data *data, int *val) val 480 drivers/iio/temperature/mlx90632.c *val = mlx90632_calc_temp_object(object, ambient, Ea, Eb, Fa, Fb, Ga, val 485 drivers/iio/temperature/mlx90632.c static int mlx90632_calc_ambient_dsp105(struct mlx90632_data *data, int *val) val 514 drivers/iio/temperature/mlx90632.c *val = mlx90632_calc_temp_ambient(ambient_new_raw, ambient_old_raw, val 520 drivers/iio/temperature/mlx90632.c struct iio_chan_spec const *channel, int *val, val 530 drivers/iio/temperature/mlx90632.c ret = mlx90632_calc_ambient_dsp105(data, val); val 535 drivers/iio/temperature/mlx90632.c ret = mlx90632_calc_object_dsp105(data, val); val 544 drivers/iio/temperature/mlx90632.c *val = 1; val 547 drivers/iio/temperature/mlx90632.c *val = 0; val 558 drivers/iio/temperature/mlx90632.c struct iio_chan_spec const *channel, int val, val 566 drivers/iio/temperature/mlx90632.c if (val < 0 || val2 < 0 || val > 1 || val 567 drivers/iio/temperature/mlx90632.c (val == 1 && val2 != 0)) val 569 drivers/iio/temperature/mlx90632.c data->emissivity = val * 1000 + val2 / 1000; val 74 drivers/iio/temperature/tmp006.c struct iio_chan_spec const *channel, int *val, val 88 drivers/iio/temperature/tmp006.c *val = sign_extend32(ret, 15); val 94 drivers/iio/temperature/tmp006.c *val = sign_extend32(ret, 15) >> TMP006_TAMBIENT_SHIFT; val 101 drivers/iio/temperature/tmp006.c *val = 0; val 104 drivers/iio/temperature/tmp006.c *val = 31; val 113 drivers/iio/temperature/tmp006.c *val = tmp006_freqs[cr][0]; val 125 drivers/iio/temperature/tmp006.c int val, val 136 drivers/iio/temperature/tmp006.c if ((val == tmp006_freqs[i][0]) && val 102 drivers/iio/temperature/tmp007.c struct iio_chan_spec const *channel, int *val, val 126 drivers/iio/temperature/tmp007.c *val = sign_extend32(ret, 15) >> TMP007_TEMP_SHIFT; val 130 drivers/iio/temperature/tmp007.c *val = 31; val 137 drivers/iio/temperature/tmp007.c *val = tmp007_avgs[conv_rate][0]; val 147 drivers/iio/temperature/tmp007.c struct iio_chan_spec const *channel, int val, val 156 drivers/iio/temperature/tmp007.c if ((val == tmp007_avgs[i][0]) && val 287 drivers/iio/temperature/tmp007.c int *val, int *val2) val 315 drivers/iio/temperature/tmp007.c *val = sign_extend32(ret, 15) >> 7; val 323 drivers/iio/temperature/tmp007.c int val, int val2) val 346 drivers/iio/temperature/tmp007.c if (val < -256 || val > 255) val 350 drivers/iio/temperature/tmp007.c return i2c_smbus_write_word_swapped(data->client, reg, (val << 7)); val 80 drivers/iio/temperature/tsys01.c struct iio_chan_spec const *channel, int *val, val 93 drivers/iio/temperature/tsys01.c *val = temperature; val 30 drivers/iio/temperature/tsys02d.c struct iio_chan_spec const *channel, int *val, val 45 drivers/iio/temperature/tsys02d.c *val = temperature; val 52 drivers/iio/temperature/tsys02d.c *val = tsys02d_samp_freq[dev_data->res_index]; val 62 drivers/iio/temperature/tsys02d.c int val, int val2, long mask) val 71 drivers/iio/temperature/tsys02d.c if (val == tsys02d_samp_freq[i]) val 51 drivers/iio/trigger/iio-trig-hrtimer.c unsigned long val; val 54 drivers/iio/trigger/iio-trig-hrtimer.c ret = kstrtoul(buf, 10, &val); val 58 drivers/iio/trigger/iio-trig-hrtimer.c if (!val || val > NSEC_PER_SEC) val 61 drivers/iio/trigger/iio-trig-hrtimer.c info->sampling_frequency = val; val 62 drivers/iio/trigger/iio-trig-hrtimer.c info->period = NSEC_PER_SEC / val; val 409 drivers/iio/trigger/stm32-timer-trigger.c int *val, int *val2, long mask) val 417 drivers/iio/trigger/stm32-timer-trigger.c *val = dat; val 422 drivers/iio/trigger/stm32-timer-trigger.c *val = (dat & TIM_CR1_CEN) ? 1 : 0; val 429 drivers/iio/trigger/stm32-timer-trigger.c *val = 1; val 444 drivers/iio/trigger/stm32-timer-trigger.c int val, int val2, long mask) val 451 drivers/iio/trigger/stm32-timer-trigger.c return regmap_write(priv->regmap, TIM_CNT, val); val 458 drivers/iio/trigger/stm32-timer-trigger.c if (val) { val 566 drivers/iio/trigger/stm32-timer-trigger.c u32 val; val 575 drivers/iio/trigger/stm32-timer-trigger.c regmap_read(priv->regmap, TIM_CR1, &val); val 576 drivers/iio/trigger/stm32-timer-trigger.c if (!(val & TIM_CR1_CEN)) val 715 drivers/iio/trigger/stm32-timer-trigger.c u32 val; val 722 drivers/iio/trigger/stm32-timer-trigger.c regmap_read(priv->regmap, TIM_CR2, &val); val 724 drivers/iio/trigger/stm32-timer-trigger.c priv->has_trgo2 = !!val; val 463 drivers/infiniband/core/cache.c const struct ib_gid_attr *val, bool default_gid, val 512 drivers/infiniband/core/cache.c attr->gid_type != val->gid_type) val 520 drivers/infiniband/core/cache.c attr->ndev != val->ndev) val 689 drivers/infiniband/core/cache.c struct ib_gid_attr val = {.ndev = ndev, .gid_type = gid_type}; val 702 drivers/infiniband/core/cache.c local_index = find_gid(table, gid, &val, false, mask, NULL); val 72 drivers/infiniband/core/packer.c u32 val; val 78 drivers/infiniband/core/packer.c val = value_read(desc[i].struct_offset_bytes, val 82 drivers/infiniband/core/packer.c val = 0; val 86 drivers/infiniband/core/packer.c *addr = (*addr & ~mask) | (cpu_to_be32(val) & mask); val 89 drivers/infiniband/core/packer.c u64 val; val 95 drivers/infiniband/core/packer.c val = value_read(desc[i].struct_offset_bytes, val 99 drivers/infiniband/core/packer.c val = 0; val 103 drivers/infiniband/core/packer.c *addr = (*addr & ~mask) | (cpu_to_be64(val) & mask); val 126 drivers/infiniband/core/packer.c static void value_write(int offset, int size, u64 val, void *structure) val 129 drivers/infiniband/core/packer.c case 8: *( u8 *) (structure + offset) = val; break; val 130 drivers/infiniband/core/packer.c case 16: *(__be16 *) (structure + offset) = cpu_to_be16(val); break; val 131 drivers/infiniband/core/packer.c case 32: *(__be32 *) (structure + offset) = cpu_to_be32(val); break; val 132 drivers/infiniband/core/packer.c case 64: *(__be64 *) (structure + offset) = cpu_to_be64(val); break; val 161 drivers/infiniband/core/packer.c u32 val; val 168 drivers/infiniband/core/packer.c val = (be32_to_cpup(addr) & mask) >> shift; val 171 drivers/infiniband/core/packer.c val, val 175 drivers/infiniband/core/packer.c u64 val; val 182 drivers/infiniband/core/packer.c val = (be64_to_cpup(addr) & mask) >> shift; val 185 drivers/infiniband/core/packer.c val, val 146 drivers/infiniband/core/uverbs_cmd.c static int uverbs_request_next(struct uverbs_req_iter *iter, void *val, val 152 drivers/infiniband/core/uverbs_cmd.c if (copy_from_user(val, iter->cur, len)) val 2756 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->eth.val, kern_spec_val, actual_filter_sz); val 2767 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->ipv4.val, kern_spec_val, actual_filter_sz); val 2778 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->ipv6.val, kern_spec_val, actual_filter_sz); val 2782 drivers/infiniband/core/uverbs_cmd.c (ntohl(ib_spec->ipv6.val.flow_label)) >= BIT(20)) val 2794 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->tcp_udp.val, kern_spec_val, actual_filter_sz); val 2805 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->tunnel.val, kern_spec_val, actual_filter_sz); val 2809 drivers/infiniband/core/uverbs_cmd.c (ntohl(ib_spec->tunnel.val.tunnel_id)) >= BIT(24)) val 2820 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->esp.val, kern_spec_val, actual_filter_sz); val 2831 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->gre.val, kern_spec_val, actual_filter_sz); val 2842 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->mpls.val, kern_spec_val, actual_filter_sz); val 497 drivers/infiniband/hw/bnxt_re/qplib_fp.c u64 val = 0; val 504 drivers/infiniband/hw/bnxt_re/qplib_fp.c val = ((srq->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | arm_type; val 505 drivers/infiniband/hw/bnxt_re/qplib_fp.c val <<= 32; val 506 drivers/infiniband/hw/bnxt_re/qplib_fp.c val |= (sw_prod << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK; val 507 drivers/infiniband/hw/bnxt_re/qplib_fp.c writeq(val, db); val 1510 drivers/infiniband/hw/bnxt_re/qplib_fp.c u64 val = 0; val 1512 drivers/infiniband/hw/bnxt_re/qplib_fp.c val = (((qp->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | val 1514 drivers/infiniband/hw/bnxt_re/qplib_fp.c val <<= 32; val 1516 drivers/infiniband/hw/bnxt_re/qplib_fp.c val |= (sw_prod << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK; val 1518 drivers/infiniband/hw/bnxt_re/qplib_fp.c writeq(val, qp->dpi->dbr); val 1811 drivers/infiniband/hw/bnxt_re/qplib_fp.c u64 val = 0; val 1813 drivers/infiniband/hw/bnxt_re/qplib_fp.c val = (((qp->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | val 1815 drivers/infiniband/hw/bnxt_re/qplib_fp.c val <<= 32; val 1817 drivers/infiniband/hw/bnxt_re/qplib_fp.c val |= (sw_prod << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK; val 1819 drivers/infiniband/hw/bnxt_re/qplib_fp.c writeq(val, qp->dpi->dbr); val 1903 drivers/infiniband/hw/bnxt_re/qplib_fp.c u64 val = 0; val 1905 drivers/infiniband/hw/bnxt_re/qplib_fp.c val = ((cq->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | val 1907 drivers/infiniband/hw/bnxt_re/qplib_fp.c val <<= 32; val 1909 drivers/infiniband/hw/bnxt_re/qplib_fp.c writeq(val, cq->dbr_base); val 1916 drivers/infiniband/hw/bnxt_re/qplib_fp.c u64 val = 0; val 1919 drivers/infiniband/hw/bnxt_re/qplib_fp.c val = ((cq->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | arm_type; val 1920 drivers/infiniband/hw/bnxt_re/qplib_fp.c val <<= 32; val 1922 drivers/infiniband/hw/bnxt_re/qplib_fp.c val |= (sw_cons << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK; val 1924 drivers/infiniband/hw/bnxt_re/qplib_fp.c writeq(val, cq->dpi->dbr); val 73 drivers/infiniband/hw/bnxt_re/qplib_fp.h static inline u32 get_sqe_pg(u32 val) val 75 drivers/infiniband/hw/bnxt_re/qplib_fp.h return ((val & ~SQE_MAX_IDX_PER_PG) / SQE_CNT_PER_PG); val 78 drivers/infiniband/hw/bnxt_re/qplib_fp.h static inline u32 get_sqe_idx(u32 val) val 80 drivers/infiniband/hw/bnxt_re/qplib_fp.h return (val & SQE_MAX_IDX_PER_PG); val 88 drivers/infiniband/hw/bnxt_re/qplib_fp.h static inline u32 get_psne_pg(u32 val) val 90 drivers/infiniband/hw/bnxt_re/qplib_fp.h return ((val & ~PSNE_MAX_IDX_PER_PG) / PSNE_CNT_PER_PG); val 93 drivers/infiniband/hw/bnxt_re/qplib_fp.h static inline u32 get_psne_idx(u32 val) val 95 drivers/infiniband/hw/bnxt_re/qplib_fp.h return (val & PSNE_MAX_IDX_PER_PG); val 439 drivers/infiniband/hw/bnxt_re/qplib_fp.h u64 val; val 441 drivers/infiniband/hw/bnxt_re/qplib_fp.h val = xid & DBC_DBC_XID_MASK; val 442 drivers/infiniband/hw/bnxt_re/qplib_fp.h val |= DBC_DBC_PATH_ROCE; val 443 drivers/infiniband/hw/bnxt_re/qplib_fp.h val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; val 444 drivers/infiniband/hw/bnxt_re/qplib_fp.h val <<= 32; val 445 drivers/infiniband/hw/bnxt_re/qplib_fp.h val |= index & DBC_DBC_INDEX_MASK; val 446 drivers/infiniband/hw/bnxt_re/qplib_fp.h writeq(val, db); val 116 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h static inline u32 get_cmdq_pg(u32 val, u32 depth) val 118 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h return (val & ~(bnxt_qplib_max_cmdq_idx_per_pg(depth))) / val 122 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h static inline u32 get_cmdq_idx(u32 val, u32 depth) val 124 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h return val & (bnxt_qplib_max_cmdq_idx_per_pg(depth)); val 141 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h static inline u32 get_creq_pg(u32 val) val 143 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG; val 146 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h static inline u32 get_creq_idx(u32 val) val 148 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h return val & MAX_CREQ_IDX_PER_PG; val 169 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h u64 val = 0; val 171 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h val = xid & DBC_DBC_XID_MASK; val 172 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h val |= DBC_DBC_PATH_ROCE; val 173 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; val 174 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h val <<= 32; val 175 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h val |= index & DBC_DBC_INDEX_MASK; val 177 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h writeq(val, db); val 199 drivers/infiniband/hw/cxgb3/iwch_cm.c req->val = cpu_to_be64(1 << S_TCB_RX_QUIESCE); val 220 drivers/infiniband/hw/cxgb3/iwch_cm.c req->val = 0; val 617 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[0].val = cpu_to_be32(FW_PFVF_CMD_PFN_V val 620 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[1].val = cpu_to_be32(ep->tx_chan); val 622 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[2].val = cpu_to_be32(ep->tx_chan); val 624 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[3].val = cpu_to_be32(ep->rss_qid); val 626 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[4].val = cpu_to_be32(ep->snd_seq); val 628 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[5].val = cpu_to_be32(ep->rcv_seq); val 630 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[6].val = cpu_to_be32(ep->snd_win); val 632 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[7].val = cpu_to_be32(ep->emss); val 634 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[8].val = cpu_to_be32(ep->snd_wscale); val 639 drivers/infiniband/hw/cxgb4/cm.c flowc->mnemval[9].val = cpu_to_be32(pri); val 718 drivers/infiniband/hw/cxgb4/t4.h static inline void write_gts(struct t4_cq *cq, u32 val) val 721 drivers/infiniband/hw/cxgb4/t4.h writel(val | INGRESSQID_V(cq->bar2_qid), val 724 drivers/infiniband/hw/cxgb4/t4.h writel(val | INGRESSQID_V(cq->cqid), cq->gts); val 734 drivers/infiniband/hw/cxgb4/t4.h u32 val; val 738 drivers/infiniband/hw/cxgb4/t4.h val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7); val 739 drivers/infiniband/hw/cxgb4/t4.h write_gts(cq, val); val 742 drivers/infiniband/hw/cxgb4/t4.h val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6); val 743 drivers/infiniband/hw/cxgb4/t4.h write_gts(cq, val); val 773 drivers/infiniband/hw/cxgb4/t4.h u32 val; val 775 drivers/infiniband/hw/cxgb4/t4.h val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7); val 776 drivers/infiniband/hw/cxgb4/t4.h write_gts(cq, val); val 1023 drivers/infiniband/hw/efa/efa_com.c u32 val, i; val 1026 drivers/infiniband/hw/efa/efa_com.c val = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF); val 1028 drivers/infiniband/hw/efa/efa_com.c if ((val & EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == val 1032 drivers/infiniband/hw/efa/efa_com.c ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val); val 1456 drivers/infiniband/hw/hfi1/chip.c u64 val = 0; val 1468 drivers/infiniband/hw/hfi1/chip.c val = read_write_csr(dd, csr, mode, data); val 1469 drivers/infiniband/hw/hfi1/chip.c return val; val 1510 drivers/infiniband/hw/hfi1/chip.c u64 val; val 1521 drivers/infiniband/hw/hfi1/chip.c val = read_write_csr(ppd->dd, csr, mode, data); val 1522 drivers/infiniband/hw/hfi1/chip.c return val; val 4057 drivers/infiniband/hw/hfi1/chip.c u64 val = 0; val 4060 drivers/infiniband/hw/hfi1/chip.c val = read_write_csr(dd, csr, mode, data); val 4062 drivers/infiniband/hw/hfi1/chip.c val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ? val 4063 drivers/infiniband/hw/hfi1/chip.c CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors; val 4070 drivers/infiniband/hw/hfi1/chip.c return val; val 8560 drivers/infiniband/hw/hfi1/chip.c u64 val; val 8573 drivers/infiniband/hw/hfi1/chip.c u64 val; val 8576 drivers/infiniband/hw/hfi1/chip.c ret = read_lcb_csr(dd, lcb_cache[i].off, &val); val 8580 drivers/infiniband/hw/hfi1/chip.c lcb_cache[i].val = val; val 8584 drivers/infiniband/hw/hfi1/chip.c static int read_lcb_cache(u32 off, u64 *val) val 8590 drivers/infiniband/hw/hfi1/chip.c *val = lcb_cache[i].val; val 9981 drivers/infiniband/hw/hfi1/chip.c int val = 0; val 9985 drivers/infiniband/hw/hfi1/chip.c val = ppd->link_width_enabled; val 9988 drivers/infiniband/hw/hfi1/chip.c val = ppd->link_width_active; val 9991 drivers/infiniband/hw/hfi1/chip.c val = ppd->link_speed_enabled; val 9994 drivers/infiniband/hw/hfi1/chip.c val = ppd->link_speed_active; val 10003 drivers/infiniband/hw/hfi1/chip.c val = ppd->actual_vls_operational; val 10006 drivers/infiniband/hw/hfi1/chip.c val = VL_ARB_HIGH_PRIO_TABLE_SIZE; val 10009 drivers/infiniband/hw/hfi1/chip.c val = VL_ARB_LOW_PRIO_TABLE_SIZE; val 10012 drivers/infiniband/hw/hfi1/chip.c val = ppd->overrun_threshold; val 10015 drivers/infiniband/hw/hfi1/chip.c val = ppd->phy_error_threshold; val 10018 drivers/infiniband/hw/hfi1/chip.c val = HLS_DEFAULT; val 10034 drivers/infiniband/hw/hfi1/chip.c return val; val 10929 drivers/infiniband/hw/hfi1/chip.c int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val) val 10943 drivers/infiniband/hw/hfi1/chip.c val *= 4096 / 64; val 10944 drivers/infiniband/hw/hfi1/chip.c reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK) val 10950 drivers/infiniband/hw/hfi1/chip.c if (val != HLS_DN_POLL) val 10954 drivers/infiniband/hw/hfi1/chip.c if (ppd->vls_operational != val) { val 10955 drivers/infiniband/hw/hfi1/chip.c ppd->vls_operational = val; val 10969 drivers/infiniband/hw/hfi1/chip.c ppd->link_width_enabled = val & ppd->link_width_supported; val 10973 drivers/infiniband/hw/hfi1/chip.c val & ppd->link_width_downgrade_supported; val 10976 drivers/infiniband/hw/hfi1/chip.c ppd->link_speed_enabled = val & ppd->link_speed_supported; val 10983 drivers/infiniband/hw/hfi1/chip.c ppd->overrun_threshold = val; val 10990 drivers/infiniband/hw/hfi1/chip.c ppd->phy_error_threshold = val; val 11006 drivers/infiniband/hw/hfi1/chip.c __func__, ib_cfg_name(which), val); val 12070 drivers/infiniband/hw/hfi1/chip.c u64 val = 0; val 12097 drivers/infiniband/hw/hfi1/chip.c val = entry->rw_cntr(entry, val 12104 drivers/infiniband/hw/hfi1/chip.c val, j); val 12106 drivers/infiniband/hw/hfi1/chip.c val; val 12113 drivers/infiniband/hw/hfi1/chip.c val = val 12118 drivers/infiniband/hw/hfi1/chip.c val, j); val 12120 drivers/infiniband/hw/hfi1/chip.c val; val 12123 drivers/infiniband/hw/hfi1/chip.c val = entry->rw_cntr(entry, dd, val 12126 drivers/infiniband/hw/hfi1/chip.c dd->cntrs[entry->offset] = val; val 12127 drivers/infiniband/hw/hfi1/chip.c hfi1_cdbg(CNTR, "\tRead 0x%llx", val); val 12141 drivers/infiniband/hw/hfi1/chip.c u64 val = 0; val 12165 drivers/infiniband/hw/hfi1/chip.c val = entry->rw_cntr(entry, ppd, j, val 12171 drivers/infiniband/hw/hfi1/chip.c val, j); val 12172 drivers/infiniband/hw/hfi1/chip.c ppd->cntrs[entry->offset + j] = val; val 12175 drivers/infiniband/hw/hfi1/chip.c val = entry->rw_cntr(entry, ppd, val 12179 drivers/infiniband/hw/hfi1/chip.c ppd->cntrs[entry->offset] = val; val 12180 drivers/infiniband/hw/hfi1/chip.c hfi1_cdbg(CNTR, "\tRead 0x%llx", val); val 12224 drivers/infiniband/hw/hfi1/chip.c u64 val; val 12234 drivers/infiniband/hw/hfi1/chip.c val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0); val 12248 drivers/infiniband/hw/hfi1/chip.c if (lower > val) { /* hw wrapped */ val 12250 drivers/infiniband/hw/hfi1/chip.c val = CNTR_MAX; val 12255 drivers/infiniband/hw/hfi1/chip.c if (val != CNTR_MAX) val 12256 drivers/infiniband/hw/hfi1/chip.c val = (upper << 32) | val; val 12260 drivers/infiniband/hw/hfi1/chip.c if ((val < sval) || (val > CNTR_MAX)) val 12261 drivers/infiniband/hw/hfi1/chip.c val = CNTR_MAX; val 12265 drivers/infiniband/hw/hfi1/chip.c *psval = val; val 12267 drivers/infiniband/hw/hfi1/chip.c hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); val 12269 drivers/infiniband/hw/hfi1/chip.c return val; val 12276 drivers/infiniband/hw/hfi1/chip.c u64 val; val 12288 drivers/infiniband/hw/hfi1/chip.c val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, val 12290 drivers/infiniband/hw/hfi1/chip.c val = data; /* return the full 64bit value */ val 12292 drivers/infiniband/hw/hfi1/chip.c val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, val 12296 drivers/infiniband/hw/hfi1/chip.c val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data); val 12299 drivers/infiniband/hw/hfi1/chip.c *psval = val; val 12301 drivers/infiniband/hw/hfi1/chip.c hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); val 12303 drivers/infiniband/hw/hfi1/chip.c return val; val 14471 drivers/infiniband/hw/hfi1/chip.c u64 val; val 14501 drivers/infiniband/hw/hfi1/chip.c val = read_csr(dd, RCV_BYPASS); val 14502 drivers/infiniband/hw/hfi1/chip.c val &= ~RCV_BYPASS_HDR_SIZE_SMASK; val 14503 drivers/infiniband/hw/hfi1/chip.c val |= ((4ull & RCV_BYPASS_HDR_SIZE_MASK) << val 14505 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_BYPASS, val); val 1429 drivers/infiniband/hw/hfi1/chip.h int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val); val 87 drivers/infiniband/hw/hfi1/driver.c static int hfi1_caps_set(const char *val, const struct kernel_param *kp); val 112 drivers/infiniband/hw/hfi1/driver.c static int hfi1_caps_set(const char *val, const struct kernel_param *kp) val 120 drivers/infiniband/hw/hfi1/driver.c ret = kstrtoul(val, 0, &value); val 100 drivers/infiniband/hw/hfi1/exp_rcv.h #define KDETH_GET(val, field) \ val 101 drivers/infiniband/hw/hfi1/exp_rcv.h (((le32_to_cpu((val))) >> KDETH_##field##_SHIFT) & KDETH_##field##_MASK) val 102 drivers/infiniband/hw/hfi1/exp_rcv.h #define KDETH_SET(dw, field, val) do { \ val 105 drivers/infiniband/hw/hfi1/exp_rcv.h dwval |= (((val) & KDETH_##field##_MASK) << \ val 110 drivers/infiniband/hw/hfi1/exp_rcv.h #define KDETH_RESET(dw, field, val) ({ dw = 0; KDETH_SET(dw, field, val); }) val 167 drivers/infiniband/hw/hfi1/file_ops.c #define HFI1_MMAP_TOKEN_SET(field, val) \ val 168 drivers/infiniband/hw/hfi1/file_ops.c (((val) & HFI1_MMAP_##field##_MASK) << HFI1_MMAP_##field##_SHIFT) val 749 drivers/infiniband/hw/hfi1/mad.c u64 val; val 756 drivers/infiniband/hw/hfi1/mad.c static int write_lcb_cache(u32 off, u64 val) val 762 drivers/infiniband/hw/hfi1/mad.c lcb_cache[i].val = val; val 771 drivers/infiniband/hw/hfi1/mad.c static int read_lcb_cache(u32 off, u64 *val) val 777 drivers/infiniband/hw/hfi1/mad.c *val = lcb_cache[i].val; val 1800 drivers/infiniband/hw/hfi1/mad.c u64 *val = data; val 1804 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, SEND_SC2VLT0, *val++); val 1805 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, SEND_SC2VLT1, *val++); val 1806 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, SEND_SC2VLT2, *val++); val 1807 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, SEND_SC2VLT3, *val++); val 1816 drivers/infiniband/hw/hfi1/mad.c u64 *val = (u64 *)data; val 1818 drivers/infiniband/hw/hfi1/mad.c *val++ = read_csr(dd, SEND_SC2VLT0); val 1819 drivers/infiniband/hw/hfi1/mad.c *val++ = read_csr(dd, SEND_SC2VLT1); val 1820 drivers/infiniband/hw/hfi1/mad.c *val++ = read_csr(dd, SEND_SC2VLT2); val 1821 drivers/infiniband/hw/hfi1/mad.c *val++ = read_csr(dd, SEND_SC2VLT3); val 147 drivers/infiniband/hw/hfi1/pio_copy.c union mix val; val 149 drivers/infiniband/hw/hfi1/pio_copy.c val.val64 = 0; val 150 drivers/infiniband/hw/hfi1/pio_copy.c val.val32[0] = *(u32 *)from; val 151 drivers/infiniband/hw/hfi1/pio_copy.c writeq(val.val64, dest); val 205 drivers/infiniband/hw/hfi1/qp.c int val; val 210 drivers/infiniband/hw/hfi1/qp.c val = opa_mtu_enum_to_int((int)mtu); val 211 drivers/infiniband/hw/hfi1/qp.c if (val > 0) val 212 drivers/infiniband/hw/hfi1/qp.c return val; val 2008 drivers/infiniband/hw/hfi1/rc.c u64 val, struct hfi1_ctxtdata *rcd) val 2077 drivers/infiniband/hw/hfi1/rc.c *vaddr = val; val 2080 drivers/infiniband/hw/hfi1/rc.c opfn_conn_reply(qp, val); val 2357 drivers/infiniband/hw/hfi1/rc.c u64 val; val 2406 drivers/infiniband/hw/hfi1/rc.c val = ib_u64_get(&ohdr->u.at.atomic_ack_eth); val 2408 drivers/infiniband/hw/hfi1/rc.c val = 0; val 2409 drivers/infiniband/hw/hfi1/rc.c if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) || val 54 drivers/infiniband/hw/hfi1/rc.h int do_rc_ack(struct rvt_qp *qp, u32 aeth, u32 psn, int opcode, u64 val, val 13 drivers/infiniband/hw/hfi1/tid_rdma.h #define CIRC_ADD(val, add, size) (((val) + (add)) & ((size) - 1)) val 14 drivers/infiniband/hw/hfi1/tid_rdma.h #define CIRC_NEXT(val, size) CIRC_ADD(val, 1, size) val 15 drivers/infiniband/hw/hfi1/tid_rdma.h #define CIRC_PREV(val, size) CIRC_ADD(val, -1, size) val 1144 drivers/infiniband/hw/hfi1/user_sdma.c u32 val = be32_to_cpu(bthpsn), val 1147 drivers/infiniband/hw/hfi1/user_sdma.c psn = val & mask; val 1321 drivers/infiniband/hw/hfi1/user_sdma.c __le16 val; val 1354 drivers/infiniband/hw/hfi1/user_sdma.c val = cpu_to_le16(((EXP_TID_GET(tidval, CTRL) & 0x3) << 10) | val 1358 drivers/infiniband/hw/hfi1/user_sdma.c val |= cpu_to_le16((KDETH_GET(hdr->kdeth.ver_tid_offset, val 1362 drivers/infiniband/hw/hfi1/user_sdma.c val |= KDETH_GET(hdr->kdeth.ver_tid_offset, SH) ? val 1370 drivers/infiniband/hw/hfi1/user_sdma.c 7, 16, 14, (__force u16)val); val 40 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg)) val 51 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_set_field(origin, mask, shift, val) \ val 54 drivers/infiniband/hw/hns/hns_roce_common.h (origin) |= cpu_to_le32(((u32)(val) << (shift)) & (mask)); \ val 57 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_set_bit(origin, shift, val) \ val 58 drivers/infiniband/hw/hns/hns_roce_common.h roce_set_field((origin), (1ul << (shift)), (shift), (val)) val 1099 drivers/infiniband/hw/hns/hns_roce_device.h static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) val 1101 drivers/infiniband/hw/hns/hns_roce_device.h __raw_writeq(*(u64 *) val, dest); val 449 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 451 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); val 452 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 455 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 456 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); val 463 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 466 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); val 467 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 470 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 471 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); val 478 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 481 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG); val 482 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 487 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 488 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val); val 495 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 498 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG); val 499 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 504 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 505 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val); val 516 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 530 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG); val 531 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 542 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 543 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val); val 558 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 572 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG); val 573 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 580 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 581 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val); val 1198 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 1226 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG); val 1227 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1238 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1239 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val); val 1240 drivers/infiniband/hw/hns/hns_roce_hw_v1.c dev_dbg(dev, "Configure raq_shift 0x%x.\n", val); val 1243 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_RAQ_WL_REG); val 1244 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1248 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1249 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_RAQ_WL_REG, val); val 1250 drivers/infiniband/hw/hns/hns_roce_hw_v1.c dev_dbg(dev, "Configure raq_wl 0x%x.\n", val); val 1253 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG); val 1254 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1266 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1267 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val); val 1268 drivers/infiniband/hw/hns/hns_roce_hw_v1.c dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val); val 1271 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); val 1272 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1274 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1275 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); val 1276 drivers/infiniband/hw/hns/hns_roce_hw_v1.c dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val); val 1302 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 1305 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); val 1307 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1311 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1312 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); val 1314 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); val 1316 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1319 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1320 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); val 1584 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 1589 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG); val 1590 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1596 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1597 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val); val 1599 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG); val 1600 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1678 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val = 0; val 1691 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1701 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1708 drivers/infiniband/hw/hns/hns_roce_hw_v1.c writel(val, hcr + 5); val 1780 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 1800 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, val 1802 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1807 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1809 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val); val 1818 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 1820 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = roce_read(hr_dev, val 1822 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 1825 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 1827 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val); val 4200 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 val; val 4202 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = readl(eqc); val 4203 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(val); val 4216 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = le32_to_cpu(tmp); val 4217 drivers/infiniband/hw/hns/hns_roce_hw_v1.c writel(val, eqc); val 1827 drivers/infiniband/hw/hns/hns_roce_hw_v2.h static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2], val 1835 drivers/infiniband/hw/hns/hns_roce_hw_v2.h hns_roce_write64_k(val, dest); val 76 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 *val, val 81 drivers/infiniband/hw/i40iw/i40iw_ctrl.c *val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPTAIL); val 82 drivers/infiniband/hw/i40iw/i40iw_ctrl.c *tail = RS_32(*val, I40E_PFPE_CQPTAIL_WQTAIL); val 83 drivers/infiniband/hw/i40iw/i40iw_ctrl.c *error = RS_32(*val, I40E_PFPE_CQPTAIL_CQP_OP_ERR); val 85 drivers/infiniband/hw/i40iw/i40iw_ctrl.c *val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPTAIL1); val 86 drivers/infiniband/hw/i40iw/i40iw_ctrl.c *tail = RS_32(*val, I40E_VFPE_CQPTAIL_WQTAIL); val 87 drivers/infiniband/hw/i40iw/i40iw_ctrl.c *error = RS_32(*val, I40E_VFPE_CQPTAIL_CQP_OP_ERR); val 103 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 newtail, error, val; val 107 drivers/infiniband/hw/i40iw/i40iw_ctrl.c i40iw_get_cqp_reg_info(cqp, &val, &newtail, &error); val 508 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 cnt = 0, p1, p2, val = 0, err_code; val 567 drivers/infiniband/hw/i40iw/i40iw_ctrl.c val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CCQPSTATUS); val 569 drivers/infiniband/hw/i40iw/i40iw_ctrl.c val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CCQPSTATUS1); val 570 drivers/infiniband/hw/i40iw/i40iw_ctrl.c } while (!val); val 652 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 cnt = 0, val = 1; val 671 drivers/infiniband/hw/i40iw/i40iw_ctrl.c val = i40iw_rd32(cqp->dev->hw, cqpstat_addr); val 672 drivers/infiniband/hw/i40iw/i40iw_ctrl.c } while (val); val 917 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 val, tail, error; val 936 drivers/infiniband/hw/i40iw/i40iw_ctrl.c i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); val 990 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 tail, val, error; val 1008 drivers/infiniband/hw/i40iw/i40iw_ctrl.c i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); val 1052 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 tail, val, error; val 1071 drivers/infiniband/hw/i40iw/i40iw_ctrl.c i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); val 2066 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 tail, val, error; val 2090 drivers/infiniband/hw/i40iw/i40iw_ctrl.c i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); val 3729 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 error, val, tail; val 3736 drivers/infiniband/hw/i40iw/i40iw_ctrl.c i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); val 3825 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 tail, val, error; val 3842 drivers/infiniband/hw/i40iw/i40iw_ctrl.c i40iw_get_cqp_reg_info(cqp, &val, &tail, &error); val 5120 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 val; val 5145 drivers/infiniband/hw/i40iw/i40iw_ctrl.c val = i40iw_rd32(dev->hw, I40E_GLPCI_DREVID); val 5146 drivers/infiniband/hw/i40iw/i40iw_ctrl.c dev->hw_rev = (u8)RS_32(val, I40E_GLPCI_DREVID_DEFAULT_REVID); val 5148 drivers/infiniband/hw/i40iw/i40iw_ctrl.c val = i40iw_rd32(dev->hw, I40E_GLPCI_LBARCTRL); val 5149 drivers/infiniband/hw/i40iw/i40iw_ctrl.c db_size = (u8)RS_32(val, I40E_GLPCI_LBARCTRL_PE_DB_SIZE); val 5154 drivers/infiniband/hw/i40iw/i40iw_ctrl.c __func__, val); val 80 drivers/infiniband/hw/i40iw/i40iw_d.h #define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits) val 81 drivers/infiniband/hw/i40iw/i40iw_d.h #define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits) val 82 drivers/infiniband/hw/i40iw/i40iw_d.h #define LS_32_1(val, bits) (u32)(val << bits) val 83 drivers/infiniband/hw/i40iw/i40iw_d.h #define RS_32_1(val, bits) (u32)(val >> bits) val 88 drivers/infiniband/hw/i40iw/i40iw_d.h #define LS_64(val, field) (((u64)val << field ## _SHIFT) & (field ## _MASK)) val 90 drivers/infiniband/hw/i40iw/i40iw_d.h #define RS_64(val, field) ((u64)(val & field ## _MASK) >> field ## _SHIFT) val 91 drivers/infiniband/hw/i40iw/i40iw_d.h #define LS_32(val, field) ((val << field ## _SHIFT) & (field ## _MASK)) val 92 drivers/infiniband/hw/i40iw/i40iw_d.h #define RS_32(val, field) ((val & field ## _MASK) >> field ## _SHIFT) val 180 drivers/infiniband/hw/i40iw/i40iw_main.c u32 val; val 182 drivers/infiniband/hw/i40iw/i40iw_main.c val = I40E_PFINT_DYN_CTLN_INTENA_MASK | val 186 drivers/infiniband/hw/i40iw/i40iw_main.c i40iw_wr32(dev->hw, I40E_PFINT_DYN_CTLN(msix_id - 1), val); val 188 drivers/infiniband/hw/i40iw/i40iw_main.c i40iw_wr32(dev->hw, I40E_VFINT_DYN_CTLN1(msix_id - 1), val); val 1362 drivers/infiniband/hw/mlx4/main.c memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, val 1366 drivers/infiniband/hw/mlx4/main.c mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; val 1386 drivers/infiniband/hw/mlx4/main.c mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; val 1388 drivers/infiniband/hw/mlx4/main.c mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; val 1400 drivers/infiniband/hw/mlx4/main.c mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; val 1402 drivers/infiniband/hw/mlx4/main.c mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; val 1648 drivers/infiniband/hw/mlx4/main.c err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, val 1695 drivers/infiniband/hw/mlx4/main.c if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) val 2539 drivers/infiniband/hw/mlx5/main.c static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) val 2554 drivers/infiniband/hw/mlx5/main.c MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); val 2558 drivers/infiniband/hw/mlx5/main.c if (mask != entry_mask || val != entry_val) val 2564 drivers/infiniband/hw/mlx5/main.c static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, val 2571 drivers/infiniband/hw/mlx5/main.c misc_v, inner_ipv6_flow_label, val); val 2576 drivers/infiniband/hw/mlx5/main.c misc_v, outer_ipv6_flow_label, val); val 2580 drivers/infiniband/hw/mlx5/main.c static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) val 2583 drivers/infiniband/hw/mlx5/main.c MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); val 2585 drivers/infiniband/hw/mlx5/main.c MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); val 2725 drivers/infiniband/hw/mlx5/main.c ib_spec->eth.val.dst_mac); val 2732 drivers/infiniband/hw/mlx5/main.c ib_spec->eth.val.src_mac); val 2743 drivers/infiniband/hw/mlx5/main.c first_vid, ntohs(ib_spec->eth.val.vlan_tag)); val 2750 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->eth.val.vlan_tag) >> 12); val 2757 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->eth.val.vlan_tag) >> 13); val 2762 drivers/infiniband/hw/mlx5/main.c ethertype, ntohs(ib_spec->eth.val.ether_type)); val 2786 drivers/infiniband/hw/mlx5/main.c &ib_spec->ipv4.val.src_ip, val 2787 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->ipv4.val.src_ip)); val 2794 drivers/infiniband/hw/mlx5/main.c &ib_spec->ipv4.val.dst_ip, val 2795 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->ipv4.val.dst_ip)); val 2798 drivers/infiniband/hw/mlx5/main.c ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); val 2802 drivers/infiniband/hw/mlx5/main.c ib_spec->ipv4.val.proto)) val 2827 drivers/infiniband/hw/mlx5/main.c &ib_spec->ipv6.val.src_ip, val 2828 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->ipv6.val.src_ip)); val 2835 drivers/infiniband/hw/mlx5/main.c &ib_spec->ipv6.val.dst_ip, val 2836 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->ipv6.val.dst_ip)); val 2840 drivers/infiniband/hw/mlx5/main.c ib_spec->ipv6.val.traffic_class); val 2844 drivers/infiniband/hw/mlx5/main.c ib_spec->ipv6.val.next_hdr)) val 2849 drivers/infiniband/hw/mlx5/main.c ntohl(ib_spec->ipv6.val.flow_label), val 2859 drivers/infiniband/hw/mlx5/main.c ntohl(ib_spec->esp.val.spi)); val 2872 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->tcp_udp.val.src_port)); val 2877 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->tcp_udp.val.dst_port)); val 2890 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->tcp_udp.val.src_port)); val 2895 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->tcp_udp.val.dst_port)); val 2912 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->gre.val.protocol)); val 2920 drivers/infiniband/hw/mlx5/main.c &ib_spec->gre.val.key, val 2921 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->gre.val.key)); val 2933 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.val.tag, val 2934 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->mpls.val.tag)); val 2948 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.val.tag, val 2949 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->mpls.val.tag)); val 2964 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.val.tag, val 2965 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->mpls.val.tag)); val 2978 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.val.tag, val 2979 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->mpls.val.tag)); val 2995 drivers/infiniband/hw/mlx5/main.c ntohl(ib_spec->tunnel.val.tunnel_id)); val 3055 drivers/infiniband/hw/mlx5/main.c if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) val 3066 drivers/infiniband/hw/mlx5/main.c is_multicast_ether_addr(eth_spec->val.dst_mac); val 3139 drivers/infiniband/hw/mlx5/main.c eth_type = ntohs(ib_spec->eth.val.ether_type); val 3707 drivers/infiniband/hw/mlx5/main.c .val = {.dst_mac = {0x1} } val 3719 drivers/infiniband/hw/mlx5/main.c .val = {.dst_mac = {} } val 5531 drivers/infiniband/hw/mlx5/main.c __be32 val; val 5543 drivers/infiniband/hw/mlx5/main.c val = *(__be32 *)(out + cnts->offsets[i]); val 5544 drivers/infiniband/hw/mlx5/main.c stats->value[i] = (u64)be32_to_cpu(val); val 1904 drivers/infiniband/hw/mthca/mthca_cmd.c u8 val; val 1911 drivers/infiniband/hw/mthca/mthca_cmd.c val = in_wc->sl << 4; val 1912 drivers/infiniband/hw/mthca/mthca_cmd.c MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET); val 1914 drivers/infiniband/hw/mthca/mthca_cmd.c val = in_wc->dlid_path_bits | val 1916 drivers/infiniband/hw/mthca/mthca_cmd.c MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET); val 54 drivers/infiniband/hw/mthca/mthca_doorbell.h static inline void mthca_write64_raw(__be64 val, void __iomem *dest) val 56 drivers/infiniband/hw/mthca/mthca_doorbell.h __raw_writeq((__force u64) val, dest); val 65 drivers/infiniband/hw/mthca/mthca_doorbell.h static inline void mthca_write_db_rec(__be32 val[2], __be32 *db) val 67 drivers/infiniband/hw/mthca/mthca_doorbell.h *(u64 *) db = *(u64 *) val; val 82 drivers/infiniband/hw/mthca/mthca_doorbell.h static inline void mthca_write64_raw(__be64 val, void __iomem *dest) val 84 drivers/infiniband/hw/mthca/mthca_doorbell.h __raw_writel(((__force u32 *) &val)[0], dest); val 85 drivers/infiniband/hw/mthca/mthca_doorbell.h __raw_writel(((__force u32 *) &val)[1], dest + 4); val 102 drivers/infiniband/hw/mthca/mthca_doorbell.h static inline void mthca_write_db_rec(__be32 val[2], __be32 *db) val 104 drivers/infiniband/hw/mthca/mthca_doorbell.h db[0] = val[0]; val 106 drivers/infiniband/hw/mthca/mthca_doorbell.h db[1] = val[1]; val 308 drivers/infiniband/hw/ocrdma/ocrdma_hw.c u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK; val 310 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) << val 314 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT); val 316 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT); val 317 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT); val 318 drivers/infiniband/hw/ocrdma/ocrdma_hw.c iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET); val 323 drivers/infiniband/hw/ocrdma/ocrdma_hw.c u32 val = 0; val 325 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK; val 326 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT; val 327 drivers/infiniband/hw/ocrdma/ocrdma_hw.c iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET); val 333 drivers/infiniband/hw/ocrdma/ocrdma_hw.c u32 val = 0; val 335 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= eq_id & OCRDMA_EQ_ID_MASK; val 336 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT); val 338 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= (1 << OCRDMA_REARM_SHIFT); val 340 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= (1 << OCRDMA_EQ_CLR_SHIFT); val 341 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= (1 << OCRDMA_EQ_TYPE_SHIFT); val 342 drivers/infiniband/hw/ocrdma/ocrdma_hw.c val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT); val 343 drivers/infiniband/hw/ocrdma/ocrdma_hw.c iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET); val 2096 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c u32 val = qp->sq.dbid | (1 << OCRDMA_DB_SQ_SHIFT); val 2098 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c iowrite32(val, qp->sq_db); val 2208 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c u32 val = qp->rq.dbid | (1 << OCRDMA_DB_RQ_SHIFT); val 2210 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c iowrite32(val, qp->rq_db); val 2299 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c u32 val = srq->rq.dbid | (1 << 16); val 2301 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c iowrite32(val, srq->db + OCRDMA_DB_GEN2_SRQ_OFFSET); val 1292 drivers/infiniband/hw/qib/qib.h void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val); val 727 drivers/infiniband/hw/qib/qib_common.h __u32 val; val 689 drivers/infiniband/hw/qib/qib_driver.c void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val) val 699 drivers/infiniband/hw/qib/qib_driver.c freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT; val 703 drivers/infiniband/hw/qib/qib_driver.c ppd->led_override_vals[0] = val & 0xF; val 704 drivers/infiniband/hw/qib/qib_driver.c ppd->led_override_vals[1] = (val >> 4) & 0xF; val 708 drivers/infiniband/hw/qib/qib_driver.c ppd->led_override_vals[0] = val & 0xF; val 709 drivers/infiniband/hw/qib/qib_driver.c ppd->led_override_vals[1] = val & 0xF; val 1912 drivers/infiniband/hw/qib/qib_file_ops.c const u32 val = qib_user_sdma_inflight_counter(pq); val 1914 drivers/infiniband/hw/qib/qib_file_ops.c if (put_user(val, inflightp)) val 1924 drivers/infiniband/hw/qib/qib_file_ops.c u32 val; val 1934 drivers/infiniband/hw/qib/qib_file_ops.c val = qib_user_sdma_complete_counter(pq); val 1935 drivers/infiniband/hw/qib/qib_file_ops.c if (put_user(val, completep)) val 1130 drivers/infiniband/hw/qib/qib_iba6120.c u64 val; val 1139 drivers/infiniband/hw/qib/qib_iba6120.c val = ~0ULL; val 1145 drivers/infiniband/hw/qib/qib_iba6120.c val &= ~QLOGIC_IB_HWE_PCIEBUSPARITYRADM; val 1148 drivers/infiniband/hw/qib/qib_iba6120.c val &= ~TXEMEMPARITYERR_PIOBUF; val 1150 drivers/infiniband/hw/qib/qib_iba6120.c dd->cspec->hwerrmask = val; val 1231 drivers/infiniband/hw/qib/qib_iba6120.c u64 val, config1, prev_val, hwstat, ibc; val 1264 drivers/infiniband/hw/qib/qib_iba6120.c val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << val 1266 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_kreg(dd, kr_ibcctrl, val); val 1268 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_kreg64(dd, kr_serdes_cfg0); val 1277 drivers/infiniband/hw/qib/qib_iba6120.c val |= SYM_MASK(SerdesCfg0, ResetPLL) | val 1283 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_kreg(dd, kr_serdes_cfg0, val); val 1292 drivers/infiniband/hw/qib/qib_iba6120.c val &= ~(SYM_MASK(SerdesCfg0, RxDetEnX) | val 1298 drivers/infiniband/hw/qib/qib_iba6120.c val |= (SYM_MASK(SerdesCfg0, ResetA) | val 1303 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_kreg(dd, kr_serdes_cfg0, val); val 1309 drivers/infiniband/hw/qib/qib_iba6120.c val &= ~((SYM_MASK(SerdesCfg0, ResetA) | val 1315 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_kreg(dd, kr_serdes_cfg0, val); val 1319 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_kreg64(dd, kr_xgxs_cfg); val 1320 drivers/infiniband/hw/qib/qib_iba6120.c prev_val = val; val 1321 drivers/infiniband/hw/qib/qib_iba6120.c if (val & QLOGIC_IB_XGXS_RESET) val 1322 drivers/infiniband/hw/qib/qib_iba6120.c val &= ~QLOGIC_IB_XGXS_RESET; val 1323 drivers/infiniband/hw/qib/qib_iba6120.c if (SYM_FIELD(val, XGXSCfg, polarity_inv) != ppd->rx_pol_inv) { val 1325 drivers/infiniband/hw/qib/qib_iba6120.c val &= ~SYM_MASK(XGXSCfg, polarity_inv); val 1326 drivers/infiniband/hw/qib/qib_iba6120.c val |= (u64)ppd->rx_pol_inv << SYM_LSB(XGXSCfg, polarity_inv); val 1328 drivers/infiniband/hw/qib/qib_iba6120.c if (val != prev_val) val 1329 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_kreg(dd, kr_xgxs_cfg, val); val 1331 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_kreg64(dd, kr_serdes_cfg0); val 1371 drivers/infiniband/hw/qib/qib_iba6120.c u64 val; val 1390 drivers/infiniband/hw/qib/qib_iba6120.c val = read_6120_creg32(dd, cr_ibsymbolerr); val 1392 drivers/infiniband/hw/qib/qib_iba6120.c val -= val - dd->cspec->ibsymsnap; val 1393 drivers/infiniband/hw/qib/qib_iba6120.c val -= dd->cspec->ibsymdelta; val 1394 drivers/infiniband/hw/qib/qib_iba6120.c write_6120_creg(dd, cr_ibsymbolerr, val); val 1397 drivers/infiniband/hw/qib/qib_iba6120.c val = read_6120_creg32(dd, cr_iblinkerrrecov); val 1399 drivers/infiniband/hw/qib/qib_iba6120.c val -= val - dd->cspec->iblnkerrsnap; val 1400 drivers/infiniband/hw/qib/qib_iba6120.c val -= dd->cspec->iblnkerrdelta; val 1401 drivers/infiniband/hw/qib/qib_iba6120.c write_6120_creg(dd, cr_iblinkerrrecov, val); val 1408 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_kreg64(dd, kr_serdes_cfg0); val 1409 drivers/infiniband/hw/qib/qib_iba6120.c val |= SYM_MASK(SerdesCfg0, TxIdeEnX); val 1410 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_kreg(dd, kr_serdes_cfg0, val); val 1438 drivers/infiniband/hw/qib/qib_iba6120.c u64 extctl, val, lst, ltst; val 1456 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_kreg64(dd, kr_ibcstatus); val 1457 drivers/infiniband/hw/qib/qib_iba6120.c ltst = qib_6120_phys_portstate(val); val 1458 drivers/infiniband/hw/qib/qib_iba6120.c lst = qib_6120_iblink_state(val); val 1755 drivers/infiniband/hw/qib/qib_iba6120.c u64 val; val 1781 drivers/infiniband/hw/qib/qib_iba6120.c val = dd->control | QLOGIC_IB_C_RESET; val 1782 drivers/infiniband/hw/qib/qib_iba6120.c writeq(val, &dd->kregbase[kr_control]); val 1799 drivers/infiniband/hw/qib/qib_iba6120.c val = readq(&dd->kregbase[kr_revision]); val 1800 drivers/infiniband/hw/qib/qib_iba6120.c if (val == dd->revision) { val 2098 drivers/infiniband/hw/qib/qib_iba6120.c u64 mask, val; val 2138 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) | val 2140 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); val 2149 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); val 2150 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); val 2152 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); val 2153 drivers/infiniband/hw/qib/qib_iba6120.c dd->rcd[ctxt]->head = val; val 2156 drivers/infiniband/hw/qib/qib_iba6120.c val |= dd->rhdrhead_intr_off; val 2157 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); val 2666 drivers/infiniband/hw/qib/qib_iba6120.c u64 val, prev_val; val 2670 drivers/infiniband/hw/qib/qib_iba6120.c val = prev_val | QLOGIC_IB_XGXS_RESET; val 2674 drivers/infiniband/hw/qib/qib_iba6120.c qib_write_kreg(dd, kr_xgxs_cfg, val); val 2748 drivers/infiniband/hw/qib/qib_iba6120.c static int qib_6120_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) val 2757 drivers/infiniband/hw/qib/qib_iba6120.c ppd->link_width_enabled = val; val 2761 drivers/infiniband/hw/qib/qib_iba6120.c ppd->link_speed_enabled = val; val 2767 drivers/infiniband/hw/qib/qib_iba6120.c if (val64 != val) { val 2770 drivers/infiniband/hw/qib/qib_iba6120.c dd->cspec->ibcctrl |= (u64) val << val 2780 drivers/infiniband/hw/qib/qib_iba6120.c if (val64 != val) { val 2783 drivers/infiniband/hw/qib/qib_iba6120.c dd->cspec->ibcctrl |= (u64) val << val 2799 drivers/infiniband/hw/qib/qib_iba6120.c if (val == IB_LINKINITCMD_POLL) val 2817 drivers/infiniband/hw/qib/qib_iba6120.c val = (ppd->ibmaxlen >> 2) + 1; val 2819 drivers/infiniband/hw/qib/qib_iba6120.c dd->cspec->ibcctrl |= (u64)val << val 2826 drivers/infiniband/hw/qib/qib_iba6120.c switch (val & 0xffff0000) { val 2848 drivers/infiniband/hw/qib/qib_iba6120.c qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); val 2851 drivers/infiniband/hw/qib/qib_iba6120.c switch (val & 0xffff) { val 2871 drivers/infiniband/hw/qib/qib_iba6120.c val & 0xffff); val 3076 drivers/infiniband/hw/qib/qib_iba6120.c u64 val; val 3091 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_kreg64(dd, kr_sendpiosize); val 3092 drivers/infiniband/hw/qib/qib_iba6120.c dd->piosize2k = val & ~0U; val 3093 drivers/infiniband/hw/qib/qib_iba6120.c dd->piosize4k = val >> 32; val 3100 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_kreg64(dd, kr_sendpiobufcnt); val 3101 drivers/infiniband/hw/qib/qib_iba6120.c dd->piobcnt2k = val & ~0U; val 3102 drivers/infiniband/hw/qib/qib_iba6120.c dd->piobcnt4k = val >> 32; val 3150 drivers/infiniband/hw/qib/qib_iba6120.c u64 val; val 3156 drivers/infiniband/hw/qib/qib_iba6120.c val = qib_read_kreg64(dd, kr_sendpioavailaddr); val 3157 drivers/infiniband/hw/qib/qib_iba6120.c if (val != dd->pioavailregs_phys) { val 3161 drivers/infiniband/hw/qib/qib_iba6120.c (unsigned long long) val); val 3398 drivers/infiniband/hw/qib/qib_iba6120.c static void writescratch(struct qib_devdata *dd, u32 val) val 3400 drivers/infiniband/hw/qib/qib_iba6120.c (void) qib_write_kreg(dd, kr_scratch, val); val 1436 drivers/infiniband/hw/qib/qib_iba7220.c u64 val; val 1447 drivers/infiniband/hw/qib/qib_iba7220.c val = ~0ULL; /* default to all hwerrors become interrupts, */ val 1449 drivers/infiniband/hw/qib/qib_iba7220.c val &= ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR; val 1450 drivers/infiniband/hw/qib/qib_iba7220.c dd->cspec->hwerrmask = val; val 1533 drivers/infiniband/hw/qib/qib_iba7220.c u64 val, prev_val, guid, ibc; val 1569 drivers/infiniband/hw/qib/qib_iba7220.c val = ppd->cpspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << val 1571 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_kreg(dd, kr_ibcctrl, val); val 1614 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_kreg64(dd, kr_xgxs_cfg); val 1615 drivers/infiniband/hw/qib/qib_iba7220.c prev_val = val; val 1616 drivers/infiniband/hw/qib/qib_iba7220.c val |= QLOGIC_IB_XGXS_FC_SAFE; val 1617 drivers/infiniband/hw/qib/qib_iba7220.c if (val != prev_val) { val 1618 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_kreg(dd, kr_xgxs_cfg, val); val 1621 drivers/infiniband/hw/qib/qib_iba7220.c if (val & QLOGIC_IB_XGXS_RESET) val 1622 drivers/infiniband/hw/qib/qib_iba7220.c val &= ~QLOGIC_IB_XGXS_RESET; val 1623 drivers/infiniband/hw/qib/qib_iba7220.c if (val != prev_val) val 1624 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_kreg(dd, kr_xgxs_cfg, val); val 1648 drivers/infiniband/hw/qib/qib_iba7220.c u64 val; val 1671 drivers/infiniband/hw/qib/qib_iba7220.c val = read_7220_creg32(dd, cr_ibsymbolerr); val 1673 drivers/infiniband/hw/qib/qib_iba7220.c val -= val - ppd->cpspec->ibsymsnap; val 1674 drivers/infiniband/hw/qib/qib_iba7220.c val -= ppd->cpspec->ibsymdelta; val 1675 drivers/infiniband/hw/qib/qib_iba7220.c write_7220_creg(dd, cr_ibsymbolerr, val); val 1678 drivers/infiniband/hw/qib/qib_iba7220.c val = read_7220_creg32(dd, cr_iblinkerrrecov); val 1680 drivers/infiniband/hw/qib/qib_iba7220.c val -= val - ppd->cpspec->iblnkerrsnap; val 1681 drivers/infiniband/hw/qib/qib_iba7220.c val -= ppd->cpspec->iblnkerrdelta; val 1682 drivers/infiniband/hw/qib/qib_iba7220.c write_7220_creg(dd, cr_iblinkerrrecov, val); val 1697 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_kreg64(ppd->dd, kr_xgxs_cfg); val 1698 drivers/infiniband/hw/qib/qib_iba7220.c val |= QLOGIC_IB_XGXS_RESET; val 1699 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_kreg(ppd->dd, kr_xgxs_cfg, val); val 1728 drivers/infiniband/hw/qib/qib_iba7220.c u64 extctl, ledblink = 0, val, lst, ltst; val 1744 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_kreg64(dd, kr_ibcstatus); val 1745 drivers/infiniband/hw/qib/qib_iba7220.c ltst = qib_7220_phys_portstate(val); val 1746 drivers/infiniband/hw/qib/qib_iba7220.c lst = qib_7220_iblink_state(val); val 2067 drivers/infiniband/hw/qib/qib_iba7220.c u64 val; val 2094 drivers/infiniband/hw/qib/qib_iba7220.c val = dd->control | QLOGIC_IB_C_RESET; val 2095 drivers/infiniband/hw/qib/qib_iba7220.c writeq(val, &dd->kregbase[kr_control]); val 2112 drivers/infiniband/hw/qib/qib_iba7220.c val = readq(&dd->kregbase[kr_revision]); val 2113 drivers/infiniband/hw/qib/qib_iba7220.c if (val == dd->revision) { val 2406 drivers/infiniband/hw/qib/qib_iba7220.c static int qib_7220_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) val 2431 drivers/infiniband/hw/qib/qib_iba7220.c ppd->link_width_enabled = val; val 2443 drivers/infiniband/hw/qib/qib_iba7220.c val--; /* convert from IB to chip */ val 2459 drivers/infiniband/hw/qib/qib_iba7220.c ppd->link_speed_enabled = val; val 2461 drivers/infiniband/hw/qib/qib_iba7220.c !(val & (val - 1))) val 2474 drivers/infiniband/hw/qib/qib_iba7220.c if (val == (QIB_IB_SDR | QIB_IB_DDR)) { val 2475 drivers/infiniband/hw/qib/qib_iba7220.c val = IBA7220_IBC_SPEED_AUTONEG_MASK | val 2481 drivers/infiniband/hw/qib/qib_iba7220.c val = val == QIB_IB_DDR ? val 2503 drivers/infiniband/hw/qib/qib_iba7220.c if (maskr != val) { val 2506 drivers/infiniband/hw/qib/qib_iba7220.c ppd->cpspec->ibcctrl |= (u64) val << val 2516 drivers/infiniband/hw/qib/qib_iba7220.c if (maskr != val) { val 2519 drivers/infiniband/hw/qib/qib_iba7220.c ppd->cpspec->ibcctrl |= (u64) val << val 2535 drivers/infiniband/hw/qib/qib_iba7220.c if (val == IB_LINKINITCMD_POLL) val 2553 drivers/infiniband/hw/qib/qib_iba7220.c val = (ppd->ibmaxlen >> 2) + 1; val 2555 drivers/infiniband/hw/qib/qib_iba7220.c ppd->cpspec->ibcctrl |= (u64)val << SYM_LSB(IBCCtrl, MaxPktLen); val 2561 drivers/infiniband/hw/qib/qib_iba7220.c switch (val & 0xffff0000) { val 2584 drivers/infiniband/hw/qib/qib_iba7220.c qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); val 2587 drivers/infiniband/hw/qib/qib_iba7220.c switch (val & 0xffff) { val 2616 drivers/infiniband/hw/qib/qib_iba7220.c val & 0xffff); val 2645 drivers/infiniband/hw/qib/qib_iba7220.c if (val > IBA7220_IBC_HRTBT_MASK) { val 2658 drivers/infiniband/hw/qib/qib_iba7220.c ppd->cpspec->ibcddrctrl |= (((u64) val & maskr) << lsb); val 2673 drivers/infiniband/hw/qib/qib_iba7220.c u64 val, ddr; val 2677 drivers/infiniband/hw/qib/qib_iba7220.c val = 0; /* disable heart beat, so link will come up */ val 2683 drivers/infiniband/hw/qib/qib_iba7220.c val = IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT; val 2693 drivers/infiniband/hw/qib/qib_iba7220.c ppd->cpspec->ibcddrctrl = ddr | val; val 2732 drivers/infiniband/hw/qib/qib_iba7220.c u64 mask, val; val 2769 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) | val 2771 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); val 2780 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); val 2781 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); val 2783 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); val 2784 drivers/infiniband/hw/qib/qib_iba7220.c dd->rcd[ctxt]->head = val; val 2787 drivers/infiniband/hw/qib/qib_iba7220.c val |= dd->rhdrhead_intr_off; val 2788 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); val 3298 drivers/infiniband/hw/qib/qib_iba7220.c u64 val, prev_val; val 3302 drivers/infiniband/hw/qib/qib_iba7220.c val = prev_val | QLOGIC_IB_XGXS_RESET; val 3306 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_kreg(dd, kr_xgxs_cfg, val); val 3787 drivers/infiniband/hw/qib/qib_iba7220.c u64 val; val 3800 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_kreg64(dd, kr_sendpiosize); val 3801 drivers/infiniband/hw/qib/qib_iba7220.c dd->piosize2k = val & ~0U; val 3802 drivers/infiniband/hw/qib/qib_iba7220.c dd->piosize4k = val >> 32; val 3809 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_kreg64(dd, kr_sendpiobufcnt); val 3810 drivers/infiniband/hw/qib/qib_iba7220.c dd->piobcnt2k = val & ~0U; val 3811 drivers/infiniband/hw/qib/qib_iba7220.c dd->piobcnt4k = val >> 32; val 3937 drivers/infiniband/hw/qib/qib_iba7220.c u64 val; val 3943 drivers/infiniband/hw/qib/qib_iba7220.c val = qib_read_kreg64(dd, kr_sendpioavailaddr); val 3944 drivers/infiniband/hw/qib/qib_iba7220.c if (val != dd->pioavailregs_phys) { val 3948 drivers/infiniband/hw/qib/qib_iba7220.c (unsigned long long) val); val 4407 drivers/infiniband/hw/qib/qib_iba7220.c static void writescratch(struct qib_devdata *dd, u32 val) val 4409 drivers/infiniband/hw/qib/qib_iba7220.c qib_write_kreg(dd, kr_scratch, val); val 2023 drivers/infiniband/hw/qib/qib_iba7322.c u64 val = qib_read_kreg64(dd, kr_intgranted); val 2025 drivers/infiniband/hw/qib/qib_iba7322.c if (val) val 2026 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg(dd, kr_intgranted, val); val 2320 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 2344 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); val 2345 drivers/infiniband/hw/qib/qib_iba7322.c val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); val 2346 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); val 2348 drivers/infiniband/hw/qib/qib_iba7322.c val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); val 2349 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); val 2352 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i); val 2353 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg_port(ppd, krp_rxcreditvl15); val 2376 drivers/infiniband/hw/qib/qib_iba7322.c u64 val, guid, ibc; val 2471 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg_port(ppd, krp_ibcctrl_c); val 2472 drivers/infiniband/hw/qib/qib_iba7322.c val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH); val 2473 drivers/infiniband/hw/qib/qib_iba7322.c val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH); val 2474 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_ibcctrl_c, val); val 2494 drivers/infiniband/hw/qib/qib_iba7322.c val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << val 2496 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_ibcctrl_a, val); val 2499 drivers/infiniband/hw/qib/qib_iba7322.c ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd); val 2508 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg_port(ppd, krp_errmask); val 2510 drivers/infiniband/hw/qib/qib_iba7322.c val | ERR_MASK_N(IBStatusChanged)); val 2523 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 2565 drivers/infiniband/hw/qib/qib_iba7322.c val = read_7322_creg32_port(ppd, crp_ibsymbolerr); val 2567 drivers/infiniband/hw/qib/qib_iba7322.c val -= val - ppd->cpspec->ibsymsnap; val 2568 drivers/infiniband/hw/qib/qib_iba7322.c val -= ppd->cpspec->ibsymdelta; val 2569 drivers/infiniband/hw/qib/qib_iba7322.c write_7322_creg_port(ppd, crp_ibsymbolerr, val); val 2572 drivers/infiniband/hw/qib/qib_iba7322.c val = read_7322_creg32_port(ppd, crp_iblinkerrrecov); val 2574 drivers/infiniband/hw/qib/qib_iba7322.c val -= val - ppd->cpspec->iblnkerrsnap; val 2575 drivers/infiniband/hw/qib/qib_iba7322.c val -= ppd->cpspec->iblnkerrdelta; val 2576 drivers/infiniband/hw/qib/qib_iba7322.c write_7322_creg_port(ppd, crp_iblinkerrrecov, val); val 2579 drivers/infiniband/hw/qib/qib_iba7322.c val = read_7322_creg32_port(ppd, crp_iblinkdown); val 2580 drivers/infiniband/hw/qib/qib_iba7322.c val += ppd->cpspec->iblnkdowndelta; val 2581 drivers/infiniband/hw/qib/qib_iba7322.c write_7322_creg_port(ppd, crp_iblinkdown, val); val 2618 drivers/infiniband/hw/qib/qib_iba7322.c u64 extctl, ledblink = 0, val; val 2634 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg_port(ppd, krp_ibcstatus_a); val 2635 drivers/infiniband/hw/qib/qib_iba7322.c grn = qib_7322_phys_portstate(val) == val 2637 drivers/infiniband/hw/qib/qib_iba7322.c yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE; val 3629 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 3690 drivers/infiniband/hw/qib/qib_iba7322.c val = dd->control | QLOGIC_IB_C_RESET; val 3691 drivers/infiniband/hw/qib/qib_iba7322.c writeq(val, &dd->kregbase[kr_control]); val 3707 drivers/infiniband/hw/qib/qib_iba7322.c val = readq(&dd->kregbase[kr_revision]); val 3708 drivers/infiniband/hw/qib/qib_iba7322.c if (val == dd->revision) val 4066 drivers/infiniband/hw/qib/qib_iba7322.c static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) val 4090 drivers/infiniband/hw/qib/qib_iba7322.c val & (val >> 16) & SendIBSLIDAssignMask); val 4092 drivers/infiniband/hw/qib/qib_iba7322.c (val >> 16) & SendIBSLMCMask); val 4096 drivers/infiniband/hw/qib/qib_iba7322.c ppd->link_width_enabled = val; val 4098 drivers/infiniband/hw/qib/qib_iba7322.c if (val == IB_WIDTH_1X) val 4099 drivers/infiniband/hw/qib/qib_iba7322.c val = 0; val 4100 drivers/infiniband/hw/qib/qib_iba7322.c else if (val == IB_WIDTH_4X) val 4101 drivers/infiniband/hw/qib/qib_iba7322.c val = 1; val 4103 drivers/infiniband/hw/qib/qib_iba7322.c val = 3; val 4116 drivers/infiniband/hw/qib/qib_iba7322.c ppd->link_speed_enabled = val; val 4117 drivers/infiniband/hw/qib/qib_iba7322.c val <<= IBA7322_IBC_SPEED_LSB; val 4120 drivers/infiniband/hw/qib/qib_iba7322.c if (val & (val - 1)) { val 4122 drivers/infiniband/hw/qib/qib_iba7322.c val |= IBA7322_IBC_IBTA_1_2_MASK | val 4127 drivers/infiniband/hw/qib/qib_iba7322.c } else if (val & IBA7322_IBC_SPEED_QDR) val 4128 drivers/infiniband/hw/qib/qib_iba7322.c val |= IBA7322_IBC_IBTA_1_2_MASK; val 4146 drivers/infiniband/hw/qib/qib_iba7322.c if (maskr != val) { val 4149 drivers/infiniband/hw/qib/qib_iba7322.c ppd->cpspec->ibcctrl_a |= (u64) val << val 4160 drivers/infiniband/hw/qib/qib_iba7322.c if (maskr != val) { val 4163 drivers/infiniband/hw/qib/qib_iba7322.c ppd->cpspec->ibcctrl_a |= (u64) val << val 4180 drivers/infiniband/hw/qib/qib_iba7322.c if (val == IB_LINKINITCMD_POLL) val 4198 drivers/infiniband/hw/qib/qib_iba7322.c val = (ppd->ibmaxlen >> 2) + 1; val 4200 drivers/infiniband/hw/qib/qib_iba7322.c ppd->cpspec->ibcctrl_a |= (u64)val << val 4208 drivers/infiniband/hw/qib/qib_iba7322.c switch (val & 0xffff0000) { val 4243 drivers/infiniband/hw/qib/qib_iba7322.c qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); val 4246 drivers/infiniband/hw/qib/qib_iba7322.c switch (val & 0xffff) { val 4275 drivers/infiniband/hw/qib/qib_iba7322.c val & 0xffff); val 4282 drivers/infiniband/hw/qib/qib_iba7322.c if (ppd->vls_operational != val) { val 4283 drivers/infiniband/hw/qib/qib_iba7322.c ppd->vls_operational = val; val 4289 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_highprio_limit, val); val 4293 drivers/infiniband/hw/qib/qib_iba7322.c if (val > 3) { val 4314 drivers/infiniband/hw/qib/qib_iba7322.c ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb); val 4324 drivers/infiniband/hw/qib/qib_iba7322.c u64 val, ctrlb; val 4330 drivers/infiniband/hw/qib/qib_iba7322.c val = 0; /* disable heart beat, so link will come up */ val 4337 drivers/infiniband/hw/qib/qib_iba7322.c val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB; val 4348 drivers/infiniband/hw/qib/qib_iba7322.c ppd->cpspec->ibcctrl_b = ctrlb | val; val 4362 drivers/infiniband/hw/qib/qib_iba7322.c u32 val = qib_read_kreg_port(ppd, regno); val 4364 drivers/infiniband/hw/qib/qib_iba7322.c vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) & val 4366 drivers/infiniband/hw/qib/qib_iba7322.c vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) & val 4377 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 4379 drivers/infiniband/hw/qib/qib_iba7322.c val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) << val 4383 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, regno, val); val 4486 drivers/infiniband/hw/qib/qib_iba7322.c u64 mask, val; val 4551 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); val 4552 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); val 4556 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); val 4557 drivers/infiniband/hw/qib/qib_iba7322.c dd->rcd[ctxt]->head = val; val 4560 drivers/infiniband/hw/qib/qib_iba7322.c val |= dd->rhdrhead_intr_off; val 4561 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); val 4565 drivers/infiniband/hw/qib/qib_iba7322.c val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; val 4566 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); val 5187 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 5193 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg_port(ppd, krp_ib_pcsconfig); val 5200 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits); val 5202 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits); val 5747 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 5761 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg64(dd, kr_sendpiobufcnt); val 5762 drivers/infiniband/hw/qib/qib_iba7322.c dd->piobcnt2k = val & ~0U; val 5763 drivers/infiniband/hw/qib/qib_iba7322.c dd->piobcnt4k = val >> 32; val 5764 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg64(dd, kr_sendpiosize); val 5765 drivers/infiniband/hw/qib/qib_iba7322.c dd->piosize2k = val & ~0U; val 5766 drivers/infiniband/hw/qib/qib_iba7322.c dd->piosize4k = val >> 32; val 6053 drivers/infiniband/hw/qib/qib_iba7322.c unsigned long val; val 6084 drivers/infiniband/hw/qib/qib_iba7322.c val = simple_strtoul(str, &nxt, 0); val 6090 drivers/infiniband/hw/qib/qib_iba7322.c if (val >= txdds_size) val 6109 drivers/infiniband/hw/qib/qib_iba7322.c ppd->cpspec->no_eep = val; val 6140 drivers/infiniband/hw/qib/qib_iba7322.c unsigned long index, val; val 6147 drivers/infiniband/hw/qib/qib_iba7322.c val = simple_strtoul(str, &n, 0); val 6148 drivers/infiniband/hw/qib/qib_iba7322.c if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + val 6170 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 6176 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg64(dd, kr_sendpioavailaddr); val 6177 drivers/infiniband/hw/qib/qib_iba7322.c if (val != dd->pioavailregs_phys) { val 6181 drivers/infiniband/hw/qib/qib_iba7322.c (unsigned long long) val); val 6233 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 6249 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); val 6250 drivers/infiniband/hw/qib/qib_iba7322.c val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP); val 6251 drivers/infiniband/hw/qib/qib_iba7322.c val |= (u64)(ppd->vls_supported - 1) << val 6253 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); val 6287 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 6309 drivers/infiniband/hw/qib/qib_iba7322.c val = 0; val 6323 drivers/infiniband/hw/qib/qib_iba7322.c val |= ctxt << (5 * (i % 6)); val 6326 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, regno, val); val 6327 drivers/infiniband/hw/qib/qib_iba7322.c val = 0; val 6331 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, regno, val); val 6350 drivers/infiniband/hw/qib/qib_iba7322.c val = TIDFLOW_ERRBITS; /* these are W1C */ val 6355 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_ureg(dd, ur_rcvflowtable+flow, val, i); val 7167 drivers/infiniband/hw/qib/qib_iba7322.c static void writescratch(struct qib_devdata *dd, u32 val) val 7169 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg(dd, kr_scratch, val); val 8258 drivers/infiniband/hw/qib/qib_iba7322.c u64 val = SJA_EN; val 8260 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg(dd, kr_r_access, val); val 8270 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 8274 drivers/infiniband/hw/qib/qib_iba7322.c val = qib_read_kreg32(dd, kr_r_access); val 8275 drivers/infiniband/hw/qib/qib_iba7322.c if (val & R_RDY) val 8276 drivers/infiniband/hw/qib/qib_iba7322.c return (val >> R_TDO_LSB) & 1; val 8284 drivers/infiniband/hw/qib/qib_iba7322.c u64 valbase, val; val 8293 drivers/infiniband/hw/qib/qib_iba7322.c val = valbase; val 8301 drivers/infiniband/hw/qib/qib_iba7322.c val |= ((tdi & 1) << R_TDI_LSB); val 8303 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg(dd, kr_r_access, val); val 8310 drivers/infiniband/hw/qib/qib_iba7322.c val = SJA_EN | (bisten << BISTEN_LSB); val 8311 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg(dd, kr_r_access, val); val 8323 drivers/infiniband/hw/qib/qib_iba7322.c u64 val; val 8326 drivers/infiniband/hw/qib/qib_iba7322.c val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB); val 8329 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg(dd, kr_r_access, val); val 402 drivers/infiniband/hw/qib/qib_pcie.c u32 mask, bits, val; val 451 drivers/infiniband/hw/qib/qib_pcie.c pci_read_config_dword(parent, 0x48, &val); val 452 drivers/infiniband/hw/qib/qib_pcie.c val &= ~mask; val 453 drivers/infiniband/hw/qib/qib_pcie.c val |= bits; val 454 drivers/infiniband/hw/qib/qib_pcie.c pci_write_config_dword(parent, 0x48, val); val 1007 drivers/infiniband/hw/qib/qib_rc.c u64 val, struct qib_ctxtdata *rcd) val 1079 drivers/infiniband/hw/qib/qib_rc.c *vaddr = val; val 1282 drivers/infiniband/hw/qib/qib_rc.c u64 val; val 1348 drivers/infiniband/hw/qib/qib_rc.c val = ib_u64_get(&ohdr->u.at.atomic_ack_eth); val 1350 drivers/infiniband/hw/qib/qib_rc.c val = 0; val 1351 drivers/infiniband/hw/qib/qib_rc.c if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) || val 100 drivers/infiniband/hw/qib/qib_sd7220.c static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val, val 109 drivers/infiniband/hw/qib/qib_sd7220.c static int qib_sd_trimself(struct qib_devdata *dd, int val); val 261 drivers/infiniband/hw/qib/qib_sd7220.c u64 val; val 289 drivers/infiniband/hw/qib/qib_sd7220.c val = qib_read_kreg64(dd, kr_hwerrstatus); val 290 drivers/infiniband/hw/qib/qib_sd7220.c if (val & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR) { val 307 drivers/infiniband/hw/qib/qib_sd7220.c u64 val; val 325 drivers/infiniband/hw/qib/qib_sd7220.c val = qib_read_kreg64(dd, kr_ibcstatus); val 326 drivers/infiniband/hw/qib/qib_sd7220.c if (!(val & (1ULL << 11))) val 932 drivers/infiniband/hw/qib/qib_sd7220.c uint64_t val; val 940 drivers/infiniband/hw/qib/qib_sd7220.c val = qib_read_kreg64(dd, kr_ibcstatus); val 941 drivers/infiniband/hw/qib/qib_sd7220.c if (val & IB_SERDES_TRIM_DONE) { val 1007 drivers/infiniband/hw/qib/qib_sd7220.c #define RXEQ_VAL_ALL(elt, adr, val) \ val 1008 drivers/infiniband/hw/qib/qib_sd7220.c {RXEQ_INIT_RDESC((elt), (adr)), {(val), (val), (val), (val)} } val 1127 drivers/infiniband/hw/qib/qib_sd7220.c static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val, val 1154 drivers/infiniband/hw/qib/qib_sd7220.c val = (ret & ~mask) | (val & mask); val 1157 drivers/infiniband/hw/qib/qib_sd7220.c ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF); val 1163 drivers/infiniband/hw/qib/qib_sd7220.c (sloc & 0xF), (sloc >> 9) & 0x3f, val); val 1173 drivers/infiniband/hw/qib/qib_sd7220.c ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask); val 1180 drivers/infiniband/hw/qib/qib_sd7220.c val & 0xFF, mask & 0xFF); val 1221 drivers/infiniband/hw/qib/qib_sd7220.c int elt, reg, val, loc; val 1226 drivers/infiniband/hw/qib/qib_sd7220.c val = rxeq_init_vals[ridx].rdata[vsel]; val 1228 drivers/infiniband/hw/qib/qib_sd7220.c ret = ibsd_mod_allchnls(dd, loc, val, 0xFF); val 1280 drivers/infiniband/hw/qib/qib_sd7220.c static int qib_sd_trimself(struct qib_devdata *dd, int val) val 1284 drivers/infiniband/hw/qib/qib_sd7220.c return qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF); val 58 drivers/infiniband/hw/qib/qib_sysfs.c u16 val; val 60 drivers/infiniband/hw/qib/qib_sysfs.c ret = kstrtou16(buf, 0, &val); val 73 drivers/infiniband/hw/qib/qib_sysfs.c ret = dd->f_set_ib_cfg(ppd, QIB_IB_CFG_HRTBT, val); val 95 drivers/infiniband/hw/qib/qib_sysfs.c u16 val; val 97 drivers/infiniband/hw/qib/qib_sysfs.c ret = kstrtou16(buf, 0, &val); val 103 drivers/infiniband/hw/qib/qib_sysfs.c qib_set_led_override(ppd, val); val 525 drivers/infiniband/hw/qib/qib_sysfs.c u32 val; val 528 drivers/infiniband/hw/qib/qib_sysfs.c ret = kstrtou32(buf, 0, &val); val 533 drivers/infiniband/hw/qib/qib_sysfs.c write_per_cpu_rc_acks(ppd, val); val 535 drivers/infiniband/hw/qib/qib_sysfs.c write_per_cpu_rc_qacks(ppd, val); val 537 drivers/infiniband/hw/qib/qib_sysfs.c write_per_cpu_rc_delayed_comp(ppd, val); val 539 drivers/infiniband/hw/qib/qib_sysfs.c *(u32 *)((char *)qibp + dattr->counter) = val; val 516 drivers/infiniband/hw/qib/qib_user_sdma.c seqnum.val = be32_to_cpu(hdr->bth[2]); val 521 drivers/infiniband/hw/qib/qib_user_sdma.c hdr->bth[2] = cpu_to_be32(seqnum.val); val 188 drivers/infiniband/hw/usnic/usnic_fwd.c *((struct filter *)&tlv->val) = *filter; val 194 drivers/infiniband/hw/usnic/usnic_fwd.c *((struct filter_action *)&tlv->val) = *action; val 51 drivers/infiniband/hw/usnic/usnic_vnic.c #define DEFINE_USNIC_VNIC_RES_AT(usnic_vnic_res_t, vnic_res_type, desc, val) \ val 68 drivers/infiniband/hw/usnic/usnic_vnic.c #define DEFINE_USNIC_VNIC_RES_AT(usnic_vnic_res_t, vnic_res_type, desc, val) \ val 50 drivers/infiniband/hw/usnic/usnic_vnic.h #define DEFINE_USNIC_VNIC_RES_AT(usnic_vnic_res_t, vnic_res_type, desc, val) \ val 51 drivers/infiniband/hw/usnic/usnic_vnic.h USNIC_VNIC_RES_TYPE_##usnic_vnic_res_t = val, val 299 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h static inline void pvrdma_write_reg(struct pvrdma_dev *dev, u32 reg, u32 val) val 301 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h writel(cpu_to_le32(val), dev->regs + reg); val 309 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h static inline void pvrdma_write_uar_cq(struct pvrdma_dev *dev, u32 val) val 311 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h writel(cpu_to_le32(val), dev->driver_uar.map + PVRDMA_UAR_CQ_OFFSET); val 314 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h static inline void pvrdma_write_uar_qp(struct pvrdma_dev *dev, u32 val) val 316 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h writel(cpu_to_le32(val), dev->driver_uar.map + PVRDMA_UAR_QP_OFFSET); val 68 drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c u32 val = cq->cq_handle; val 72 drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c val |= (notify_flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? val 77 drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c pvrdma_write_uar_cq(dev, val); val 38 drivers/infiniband/sw/rxe/rxe_sysfs.c static int sanitize_arg(const char *val, char *intf, int intf_len) val 42 drivers/infiniband/sw/rxe/rxe_sysfs.c if (!val) val 46 drivers/infiniband/sw/rxe/rxe_sysfs.c for (len = 0; len < intf_len - 1 && val[len] && val[len] != '\n'; len++) val 47 drivers/infiniband/sw/rxe/rxe_sysfs.c intf[len] = val[len]; val 50 drivers/infiniband/sw/rxe/rxe_sysfs.c if (len == 0 || (val[len] != 0 && val[len] != '\n')) val 56 drivers/infiniband/sw/rxe/rxe_sysfs.c static int rxe_param_set_add(const char *val, const struct kernel_param *kp) val 64 drivers/infiniband/sw/rxe/rxe_sysfs.c len = sanitize_arg(val, intf, sizeof(intf)); val 95 drivers/infiniband/sw/rxe/rxe_sysfs.c static int rxe_param_set_remove(const char *val, const struct kernel_param *kp) val 101 drivers/infiniband/sw/rxe/rxe_sysfs.c len = sanitize_arg(val, intf, sizeof(intf)); val 951 drivers/infiniband/sw/siw/siw_cm.c int val = 1; val 954 drivers/infiniband/sw/siw/siw_cm.c (char *)&val, sizeof(val)); val 1407 drivers/infiniband/sw/siw/siw_cm.c int val = 1; val 1409 drivers/infiniband/sw/siw/siw_cm.c rv = kernel_setsockopt(s, SOL_TCP, TCP_NODELAY, (char *)&val, val 1410 drivers/infiniband/sw/siw/siw_cm.c sizeof(val)); val 48 drivers/infiniband/ulp/ipoib/ipoib_netlink.c u16 val; val 53 drivers/infiniband/ulp/ipoib/ipoib_netlink.c val = test_bit(IPOIB_FLAG_ADMIN_CM, &priv->flags); val 54 drivers/infiniband/ulp/ipoib/ipoib_netlink.c if (nla_put_u16(skb, IFLA_IPOIB_MODE, val)) val 57 drivers/infiniband/ulp/ipoib/ipoib_netlink.c val = test_bit(IPOIB_FLAG_UMCAST, &priv->flags); val 58 drivers/infiniband/ulp/ipoib/ipoib_netlink.c if (nla_put_u16(skb, IFLA_IPOIB_UMCAST, val)) val 182 drivers/infiniband/ulp/srp/ib_srp.c static int srp_tmo_set(const char *val, const struct kernel_param *kp) val 186 drivers/infiniband/ulp/srp/ib_srp.c res = srp_parse_tmo(&tmo, val); val 3455 drivers/infiniband/ulp/srpt/ib_srpt.c unsigned long val; val 3458 drivers/infiniband/ulp/srpt/ib_srpt.c ret = kstrtoul(page, 0, &val); val 3463 drivers/infiniband/ulp/srpt/ib_srpt.c if (val > MAX_SRPT_RDMA_SIZE) { val 3464 drivers/infiniband/ulp/srpt/ib_srpt.c pr_err("val: %lu exceeds MAX_SRPT_RDMA_SIZE: %d\n", val, val 3468 drivers/infiniband/ulp/srpt/ib_srpt.c if (val < DEFAULT_MAX_RDMA_SIZE) { val 3470 drivers/infiniband/ulp/srpt/ib_srpt.c val, DEFAULT_MAX_RDMA_SIZE); val 3473 drivers/infiniband/ulp/srpt/ib_srpt.c sport->port_attrib.srp_max_rdma_size = val; val 3492 drivers/infiniband/ulp/srpt/ib_srpt.c unsigned long val; val 3495 drivers/infiniband/ulp/srpt/ib_srpt.c ret = kstrtoul(page, 0, &val); val 3500 drivers/infiniband/ulp/srpt/ib_srpt.c if (val > MAX_SRPT_RSP_SIZE) { val 3501 drivers/infiniband/ulp/srpt/ib_srpt.c pr_err("val: %lu exceeds MAX_SRPT_RSP_SIZE: %d\n", val, val 3505 drivers/infiniband/ulp/srpt/ib_srpt.c if (val < MIN_MAX_RSP_SIZE) { val 3506 drivers/infiniband/ulp/srpt/ib_srpt.c pr_err("val: %lu smaller than MIN_MAX_RSP_SIZE: %d\n", val, val 3510 drivers/infiniband/ulp/srpt/ib_srpt.c sport->port_attrib.srp_max_rsp_size = val; val 3529 drivers/infiniband/ulp/srpt/ib_srpt.c unsigned long val; val 3532 drivers/infiniband/ulp/srpt/ib_srpt.c ret = kstrtoul(page, 0, &val); val 3537 drivers/infiniband/ulp/srpt/ib_srpt.c if (val > MAX_SRPT_SRQ_SIZE) { val 3538 drivers/infiniband/ulp/srpt/ib_srpt.c pr_err("val: %lu exceeds MAX_SRPT_SRQ_SIZE: %d\n", val, val 3542 drivers/infiniband/ulp/srpt/ib_srpt.c if (val < MIN_SRPT_SRQ_SIZE) { val 3543 drivers/infiniband/ulp/srpt/ib_srpt.c pr_err("val: %lu smaller than MIN_SRPT_SRQ_SIZE: %d\n", val, val 3547 drivers/infiniband/ulp/srpt/ib_srpt.c sport->port_attrib.srp_sq_size = val; val 3567 drivers/infiniband/ulp/srpt/ib_srpt.c unsigned long val; val 3571 drivers/infiniband/ulp/srpt/ib_srpt.c ret = kstrtoul(page, 0, &val); val 3574 drivers/infiniband/ulp/srpt/ib_srpt.c if (val != !!val) val 3586 drivers/infiniband/ulp/srpt/ib_srpt.c sport->port_attrib.use_srq = val; val 3657 drivers/infiniband/ulp/srpt/ib_srpt.c u16 val; val 3660 drivers/infiniband/ulp/srpt/ib_srpt.c ret = kstrtou16(page, 0, &val); val 3664 drivers/infiniband/ulp/srpt/ib_srpt.c if (rdma_cm_port == val) val 3667 drivers/infiniband/ulp/srpt/ib_srpt.c if (val) { val 3668 drivers/infiniband/ulp/srpt/ib_srpt.c addr6.sin6_port = cpu_to_be16(val); val 3671 drivers/infiniband/ulp/srpt/ib_srpt.c addr4.sin_port = cpu_to_be16(val); val 3681 drivers/infiniband/ulp/srpt/ib_srpt.c rdma_cm_port = val; val 1594 drivers/input/input.c #define INPUT_ADD_HOTPLUG_VAR(fmt, val...) \ val 1596 drivers/input/input.c int err = add_uevent_var(env, fmt, val); \ val 189 drivers/input/joydev.c int i, val; val 192 drivers/input/joydev.c val = input_abs_get_val(dev, joydev->abspam[i]); val 193 drivers/input/joydev.c joydev->abs[i] = joydev_correct(val, &joydev->corr[i]); val 548 drivers/input/joydev.c int val = input_abs_get_val(dev, joydev->abspam[i]); val 549 drivers/input/joydev.c joydev->abs[i] = joydev_correct(val, &joydev->corr[i]); val 117 drivers/input/joystick/as5011.c int val = gpio_get_value_cansleep(as5011->button_gpio); val 119 drivers/input/joystick/as5011.c input_report_key(as5011->input_dev, BTN_JOYSTICK, !val); val 68 drivers/input/keyboard/adp5588-keys.c static int adp5588_write(struct i2c_client *client, u8 reg, u8 val) val 70 drivers/input/keyboard/adp5588-keys.c return i2c_smbus_write_byte_data(client, reg, val); val 79 drivers/input/keyboard/adp5588-keys.c int val; val 84 drivers/input/keyboard/adp5588-keys.c val = kpad->dat_out[bank]; val 86 drivers/input/keyboard/adp5588-keys.c val = adp5588_read(kpad->client, GPIO_DAT_STAT1 + bank); val 90 drivers/input/keyboard/adp5588-keys.c return !!(val & bit); val 94 drivers/input/keyboard/adp5588-keys.c unsigned off, int val) val 102 drivers/input/keyboard/adp5588-keys.c if (val) val 131 drivers/input/keyboard/adp5588-keys.c unsigned off, int val) val 142 drivers/input/keyboard/adp5588-keys.c if (val) val 382 drivers/input/keyboard/adp5589-keys.c static int adp5589_write(struct i2c_client *client, u8 reg, u8 val) val 384 drivers/input/keyboard/adp5589-keys.c return i2c_smbus_write_byte_data(client, reg, val); val 400 drivers/input/keyboard/adp5589-keys.c unsigned off, int val) val 408 drivers/input/keyboard/adp5589-keys.c if (val) val 439 drivers/input/keyboard/adp5589-keys.c unsigned off, int val) val 450 drivers/input/keyboard/adp5589-keys.c if (val) val 718 drivers/input/keyboard/adp5589-keys.c unsigned val = 0, bit = (1 << i); val 720 drivers/input/keyboard/adp5589-keys.c val = 0; val 722 drivers/input/keyboard/adp5589-keys.c val = 1; val 724 drivers/input/keyboard/adp5589-keys.c val = 2; val 726 drivers/input/keyboard/adp5589-keys.c val = 3; val 728 drivers/input/keyboard/adp5589-keys.c pull_mask |= val << (2 * (i & 0x3)); val 738 drivers/input/keyboard/adp5589-keys.c unsigned val = 0, bit = 1 << (i + kpad->var->col_shift); val 740 drivers/input/keyboard/adp5589-keys.c val = 0; val 742 drivers/input/keyboard/adp5589-keys.c val = 1; val 744 drivers/input/keyboard/adp5589-keys.c val = 2; val 746 drivers/input/keyboard/adp5589-keys.c val = 3; val 748 drivers/input/keyboard/adp5589-keys.c pull_mask |= val << (2 * (i & 0x3)); val 176 drivers/input/keyboard/bcm-keypad.c u32 val; val 178 drivers/input/keyboard/bcm-keypad.c val = readl(kp->base + KPCR_OFFSET); val 179 drivers/input/keyboard/bcm-keypad.c val &= ~KPCR_ENABLE; val 329 drivers/input/keyboard/cap11xx.c unsigned int val, rev; val 353 drivers/input/keyboard/cap11xx.c error = regmap_read(priv->regmap, CAP11XX_REG_PRODUCT_ID, &val); val 357 drivers/input/keyboard/cap11xx.c if (val != cap->product_id) { val 359 drivers/input/keyboard/cap11xx.c val, cap->product_id); val 363 drivers/input/keyboard/cap11xx.c error = regmap_read(priv->regmap, CAP11XX_REG_MANUFACTURER_ID, &val); val 367 drivers/input/keyboard/cap11xx.c if (val != CAP11XX_MANUFACTURER_ID) { val 369 drivers/input/keyboard/cap11xx.c val, CAP11XX_MANUFACTURER_ID); val 231 drivers/input/keyboard/cros_ec_keyb.c u32 val; val 260 drivers/input/keyboard/cros_ec_keyb.c val = get_unaligned_le32(&ckdev->ec->event_data.data.sysrq); val 261 drivers/input/keyboard/cros_ec_keyb.c dev_dbg(ckdev->dev, "sysrq code from EC: %#x\n", val); val 262 drivers/input/keyboard/cros_ec_keyb.c handle_sysrq(val); val 270 drivers/input/keyboard/cros_ec_keyb.c val = get_unaligned_le32( val 274 drivers/input/keyboard/cros_ec_keyb.c val = get_unaligned_le32( val 278 drivers/input/keyboard/cros_ec_keyb.c cros_ec_keyb_report_bs(ckdev, ev_type, val); val 134 drivers/input/keyboard/ep93xx_keypad.c unsigned int val = 0; val 139 drivers/input/keyboard/ep93xx_keypad.c val |= KEY_INIT_DIS3KY; val 141 drivers/input/keyboard/ep93xx_keypad.c val |= KEY_INIT_DIAG; val 143 drivers/input/keyboard/ep93xx_keypad.c val |= KEY_INIT_BACK; val 145 drivers/input/keyboard/ep93xx_keypad.c val |= KEY_INIT_T2; val 147 drivers/input/keyboard/ep93xx_keypad.c val |= ((pdata->debounce << KEY_INIT_DBNC_SHIFT) & KEY_INIT_DBNC_MASK); val 149 drivers/input/keyboard/ep93xx_keypad.c val |= ((pdata->prescale << KEY_INIT_PRSCL_SHIFT) & KEY_INIT_PRSCL_MASK); val 151 drivers/input/keyboard/ep93xx_keypad.c __raw_writel(val, keypad->mmio_base + KEY_INIT); val 56 drivers/input/keyboard/goldfish_events.c uint8_t val; val 66 drivers/input/keyboard/goldfish_events.c val = __raw_readb(addr++); val 68 drivers/input/keyboard/goldfish_events.c if (val & 1 << j) val 77 drivers/input/keyboard/goldfish_events.c u32 val[4]; val 83 drivers/input/keyboard/goldfish_events.c count = __raw_readl(addr + REG_LEN) / sizeof(val); val 91 drivers/input/keyboard/goldfish_events.c for (j = 0; j < ARRAY_SIZE(val); j++) { val 92 drivers/input/keyboard/goldfish_events.c int offset = (i * ARRAY_SIZE(val) + j) * sizeof(u32); val 94 drivers/input/keyboard/goldfish_events.c val[j] = __raw_readl(edev->addr + REG_DATA + offset); val 98 drivers/input/keyboard/goldfish_events.c val[0], val[1], val[2], val[3]); val 226 drivers/input/keyboard/hil_kbd.c unsigned int lo, hi, val; val 232 drivers/input/keyboard/hil_kbd.c val = lo + (hi << 8); val 234 drivers/input/keyboard/hil_kbd.c if (val < input_abs_get_min(dev, ABS_X + i)) val 235 drivers/input/keyboard/hil_kbd.c input_abs_set_min(dev, ABS_X + i, val); val 236 drivers/input/keyboard/hil_kbd.c if (val > input_abs_get_max(dev, ABS_X + i)) val 237 drivers/input/keyboard/hil_kbd.c input_abs_set_max(dev, ABS_X + i, val); val 240 drivers/input/keyboard/hil_kbd.c val = input_abs_get_max(dev, ABS_X + i) - val; val 241 drivers/input/keyboard/hil_kbd.c input_report_abs(dev, ABS_X + i, val); val 243 drivers/input/keyboard/hil_kbd.c val = (int) (((int8_t) lo) | ((int8_t) hi << 8)); val 245 drivers/input/keyboard/hil_kbd.c val *= -1; val 246 drivers/input/keyboard/hil_kbd.c input_report_rel(dev, REL_X + i, val); val 53 drivers/input/keyboard/lm8333.c int lm8333_write8(struct lm8333 *lm8333, u8 cmd, u8 val) val 58 drivers/input/keyboard/lm8333.c ret = i2c_smbus_write_byte_data(lm8333->client, cmd, val); val 64 drivers/input/keyboard/max7359_keypad.c static int max7359_write_reg(struct i2c_client *client, u8 reg, u8 val) val 66 drivers/input/keyboard/max7359_keypad.c int ret = i2c_smbus_write_byte_data(client, reg, val); val 70 drivers/input/keyboard/max7359_keypad.c __func__, reg, val, ret); val 89 drivers/input/keyboard/max7359_keypad.c int val, row, col, release, code; val 91 drivers/input/keyboard/max7359_keypad.c val = max7359_read_reg(keypad->client, MAX7359_REG_KEYFIFO); val 92 drivers/input/keyboard/max7359_keypad.c row = val & 0x7; val 93 drivers/input/keyboard/max7359_keypad.c col = (val >> 3) & 0x7; val 94 drivers/input/keyboard/max7359_keypad.c release = val & 0x40; val 62 drivers/input/keyboard/mcs_touchkey.c int val; val 64 drivers/input/keyboard/mcs_touchkey.c val = i2c_smbus_read_byte_data(client, chip->status_reg); val 65 drivers/input/keyboard/mcs_touchkey.c if (val < 0) { val 66 drivers/input/keyboard/mcs_touchkey.c dev_err(&client->dev, "i2c read error [%d]\n", val); val 70 drivers/input/keyboard/mcs_touchkey.c pressed = (val & (1 << chip->pressbit)) >> chip->pressbit; val 76 drivers/input/keyboard/mcs_touchkey.c key_val = val & (0xff >> (8 - chip->pressbit)); val 156 drivers/input/keyboard/mcs_touchkey.c unsigned int val = MCS_KEY_VAL(pdata->keymap[i]); val 159 drivers/input/keyboard/mcs_touchkey.c data->keycodes[val] = code; val 67 drivers/input/keyboard/mpr121_touchkey.c u8 val; val 185 drivers/input/keyboard/mpr121_touchkey.c ret = i2c_smbus_write_byte_data(client, reg->addr, reg->val); val 98 drivers/input/keyboard/nspire-keypad.c unsigned long val = 0, cycles_per_us, delay_cycles, row_delay_cycles; val 112 drivers/input/keyboard/nspire-keypad.c val |= 3 << 0; /* Set scan mode to 3 (continuous scan) */ val 113 drivers/input/keyboard/nspire-keypad.c val |= row_delay_cycles << 2; /* Delay between scanning each row */ val 114 drivers/input/keyboard/nspire-keypad.c val |= delay_cycles << 16; /* Delay between scans */ val 115 drivers/input/keyboard/nspire-keypad.c writel(val, keypad->reg_base + KEYPAD_SCAN_MODE); val 117 drivers/input/keyboard/nspire-keypad.c val = (KEYPAD_BITMASK_ROWS & 0xff) | (KEYPAD_BITMASK_COLS & 0xff)<<8; val 118 drivers/input/keyboard/nspire-keypad.c writel(val, keypad->reg_base + KEYPAD_CNTL); val 158 drivers/input/keyboard/pmic8xxx-keypad.c unsigned int val; val 161 drivers/input/keyboard/pmic8xxx-keypad.c rc = regmap_read(kp->regmap, data_reg, &val); val 164 drivers/input/keyboard/pmic8xxx-keypad.c dev_dbg(kp->dev, "%d = %d\n", row, val); val 165 drivers/input/keyboard/pmic8xxx-keypad.c state[row] = pmic8xxx_col_state(kp, val); val 225 drivers/input/keyboard/qt1050.c unsigned int val; val 229 drivers/input/keyboard/qt1050.c regmap_read(ts->regmap, QT1050_CHIP_ID, &val); val 230 drivers/input/keyboard/qt1050.c if (val != QT1050_CHIP_ID_VER) { val 231 drivers/input/keyboard/qt1050.c dev_err(&ts->client->dev, "ID %d not supported\n", val); val 236 drivers/input/keyboard/qt1050.c err = regmap_read(ts->regmap, QT1050_FW_VERSION, &val); val 243 drivers/input/keyboard/qt1050.c val >> 4, val & 0xf); val 253 drivers/input/keyboard/qt1050.c unsigned int val; val 257 drivers/input/keyboard/qt1050.c err = regmap_read(ts->regmap, QT1050_DET_STATUS, &val); val 265 drivers/input/keyboard/qt1050.c err = regmap_read(ts->regmap, QT1050_KEY_STATUS, &val); val 271 drivers/input/keyboard/qt1050.c new_keys = (val & 0x70) >> 2 | (val & 0x6) >> 1; val 83 drivers/input/keyboard/samsung-keypad.c unsigned int val; val 87 drivers/input/keyboard/samsung-keypad.c val = S5PV210_KEYIFCOLEN_MASK; val 88 drivers/input/keyboard/samsung-keypad.c val &= ~(1 << col) << 8; val 90 drivers/input/keyboard/samsung-keypad.c val = SAMSUNG_KEYIFCOL_MASK; val 91 drivers/input/keyboard/samsung-keypad.c val &= ~(1 << col); val 94 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCOL); val 97 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFROW); val 98 drivers/input/keyboard/samsung-keypad.c row_state[col] = ~val & ((1 << keypad->rows) - 1); val 112 drivers/input/keyboard/samsung-keypad.c unsigned int val; val 131 drivers/input/keyboard/samsung-keypad.c val = MATRIX_SCAN_CODE(row, col, keypad->row_shift); val 133 drivers/input/keyboard/samsung-keypad.c input_event(input_dev, EV_MSC, MSC_SCAN, val); val 135 drivers/input/keyboard/samsung-keypad.c keypad->keycodes[val], pressed); val 149 drivers/input/keyboard/samsung-keypad.c unsigned int val; val 155 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR); val 175 drivers/input/keyboard/samsung-keypad.c unsigned int val; val 185 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); val 186 drivers/input/keyboard/samsung-keypad.c val |= SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN; val 187 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); val 197 drivers/input/keyboard/samsung-keypad.c unsigned int val; val 210 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); val 211 drivers/input/keyboard/samsung-keypad.c val &= ~(SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN); val 212 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); val 467 drivers/input/keyboard/samsung-keypad.c unsigned int val; val 478 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); val 479 drivers/input/keyboard/samsung-keypad.c val |= SAMSUNG_KEYIFCON_WAKEUPEN; val 480 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); val 491 drivers/input/keyboard/samsung-keypad.c unsigned int val; val 498 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); val 499 drivers/input/keyboard/samsung-keypad.c val &= ~SAMSUNG_KEYIFCON_WAKEUPEN; val 500 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); val 513 drivers/input/keyboard/samsung-keypad.c unsigned int val; val 517 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); val 519 drivers/input/keyboard/samsung-keypad.c val |= SAMSUNG_KEYIFCON_WAKEUPEN; val 523 drivers/input/keyboard/samsung-keypad.c val &= ~SAMSUNG_KEYIFCON_WAKEUPEN; val 527 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); val 74 drivers/input/keyboard/spear-keyboard.c u32 sts, val; val 86 drivers/input/keyboard/spear-keyboard.c val = readl_relaxed(kbd->io_base + DATA_REG) & val 88 drivers/input/keyboard/spear-keyboard.c key = kbd->keycodes[val]; val 90 drivers/input/keyboard/spear-keyboard.c input_event(input, EV_MSC, MSC_SCAN, val); val 106 drivers/input/keyboard/spear-keyboard.c u32 val; val 115 drivers/input/keyboard/spear-keyboard.c val = clk_get_rate(kbd->clk) / 1000000 - 1; val 116 drivers/input/keyboard/spear-keyboard.c val = (val & MODE_CTL_PCLK_FREQ_MSK) << MODE_CTL_PCLK_FREQ_SHIFT; val 119 drivers/input/keyboard/spear-keyboard.c val = MODE_CTL_SCAN_RATE_80 | MODE_CTL_KEYBOARD | val | val 121 drivers/input/keyboard/spear-keyboard.c writel_relaxed(val, kbd->io_base + MODE_CTL_REG); val 125 drivers/input/keyboard/spear-keyboard.c val = readl_relaxed(kbd->io_base + MODE_CTL_REG); val 126 drivers/input/keyboard/spear-keyboard.c val |= MODE_CTL_START_SCAN; val 127 drivers/input/keyboard/spear-keyboard.c writel_relaxed(val, kbd->io_base + MODE_CTL_REG); val 135 drivers/input/keyboard/spear-keyboard.c u32 val; val 138 drivers/input/keyboard/spear-keyboard.c val = readl_relaxed(kbd->io_base + MODE_CTL_REG); val 139 drivers/input/keyboard/spear-keyboard.c val &= ~MODE_CTL_START_SCAN; val 140 drivers/input/keyboard/spear-keyboard.c writel_relaxed(val, kbd->io_base + MODE_CTL_REG); val 153 drivers/input/keyboard/spear-keyboard.c u32 val, suspended_rate; val 166 drivers/input/keyboard/spear-keyboard.c error = of_property_read_u32(np, "st,mode", &val); val 172 drivers/input/keyboard/spear-keyboard.c kbd->mode = val; val 292 drivers/input/keyboard/spear-keyboard.c unsigned int rate = 0, mode_ctl_reg, val; val 314 drivers/input/keyboard/spear-keyboard.c val = mode_ctl_reg & val 316 drivers/input/keyboard/spear-keyboard.c val |= (rate & MODE_CTL_PCLK_FREQ_MSK) val 318 drivers/input/keyboard/spear-keyboard.c writel_relaxed(val, kbd->io_base + MODE_CTL_REG); val 248 drivers/input/keyboard/stmpe-keypad.c u8 val; val 255 drivers/input/keyboard/stmpe-keypad.c val = ret & ~pu_pins; val 256 drivers/input/keyboard/stmpe-keypad.c val |= pu_pins; val 258 drivers/input/keyboard/stmpe-keypad.c ret = stmpe_reg_write(stmpe, pureg, val); val 97 drivers/input/keyboard/sun4i-lradc-keys.c u32 i, ints, val, voltage, diff, keycode = 0, closest = 0xffffffff; val 112 drivers/input/keyboard/sun4i-lradc-keys.c val = readl(lradc->base + LRADC_DATA0) & 0x3f; val 113 drivers/input/keyboard/sun4i-lradc-keys.c voltage = val * lradc->vref / 63; val 54 drivers/input/keyboard/tca6416-keypad.c static int tca6416_write_reg(struct tca6416_keypad_chip *chip, int reg, u16 val) val 59 drivers/input/keyboard/tca6416-keypad.c i2c_smbus_write_word_data(chip->client, reg << 1, val) : val 60 drivers/input/keyboard/tca6416-keypad.c i2c_smbus_write_byte_data(chip->client, reg, val); val 64 drivers/input/keyboard/tca6416-keypad.c __func__, reg, val, error); val 71 drivers/input/keyboard/tca6416-keypad.c static int tca6416_read_reg(struct tca6416_keypad_chip *chip, int reg, u16 *val) val 84 drivers/input/keyboard/tca6416-keypad.c *val = (u16)retval; val 91 drivers/input/keyboard/tca6416-keypad.c u16 reg_val, val; val 101 drivers/input/keyboard/tca6416-keypad.c val = reg_val ^ chip->reg_input; val 105 drivers/input/keyboard/tca6416-keypad.c if (val & (1 << i)) { val 123 drivers/input/keyboard/tca8418_keypad.c int reg, u8 val) val 127 drivers/input/keyboard/tca8418_keypad.c error = i2c_smbus_write_byte_data(keypad_data->client, reg, val); val 131 drivers/input/keyboard/tca8418_keypad.c __func__, reg, val, error); val 142 drivers/input/keyboard/tca8418_keypad.c int reg, u8 *val) val 154 drivers/input/keyboard/tca8418_keypad.c *val = (u8)error; val 147 drivers/input/keyboard/tegra-kbc.c u32 val = 0; val 156 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); val 158 drivers/input/keyboard/tegra-kbc.c if (val & 0x80) { val 159 drivers/input/keyboard/tegra-kbc.c unsigned int col = val & 0x07; val 160 drivers/input/keyboard/tegra-kbc.c unsigned int row = (val >> 3) & 0x0f; val 173 drivers/input/keyboard/tegra-kbc.c val >>= 8; val 231 drivers/input/keyboard/tegra-kbc.c u32 val; val 233 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_CONTROL_0); val 235 drivers/input/keyboard/tegra-kbc.c val |= KBC_CONTROL_FIFO_CNT_INT_EN; val 237 drivers/input/keyboard/tegra-kbc.c val &= ~KBC_CONTROL_FIFO_CNT_INT_EN; val 238 drivers/input/keyboard/tegra-kbc.c writel(val, kbc->mmio + KBC_CONTROL_0); val 245 drivers/input/keyboard/tegra-kbc.c u32 val; val 250 drivers/input/keyboard/tegra-kbc.c val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; val 251 drivers/input/keyboard/tegra-kbc.c if (val) { val 260 drivers/input/keyboard/tegra-kbc.c dly = (val == 1) ? kbc->repoll_dly : 1; val 281 drivers/input/keyboard/tegra-kbc.c u32 val; val 289 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_INT_0); val 290 drivers/input/keyboard/tegra-kbc.c writel(val, kbc->mmio + KBC_INT_0); val 292 drivers/input/keyboard/tegra-kbc.c if (val & KBC_INT_FIFO_CNT_INT_STATUS) { val 299 drivers/input/keyboard/tegra-kbc.c } else if (val & KBC_INT_KEYPRESS_INT_STATUS) { val 359 drivers/input/keyboard/tegra-kbc.c u32 val = 0; val 379 drivers/input/keyboard/tegra-kbc.c val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt); val 380 drivers/input/keyboard/tegra-kbc.c val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */ val 381 drivers/input/keyboard/tegra-kbc.c val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */ val 382 drivers/input/keyboard/tegra-kbc.c val |= KBC_CONTROL_KBC_EN; /* enable */ val 383 drivers/input/keyboard/tegra-kbc.c writel(val, kbc->mmio + KBC_CONTROL_0); val 389 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_INIT_DLY_0); val 390 drivers/input/keyboard/tegra-kbc.c kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32); val 399 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_INT_0); val 400 drivers/input/keyboard/tegra-kbc.c val >>= 4; val 401 drivers/input/keyboard/tegra-kbc.c if (!val) val 404 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_KP_ENT0_0); val 405 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_KP_ENT1_0); val 417 drivers/input/keyboard/tegra-kbc.c u32 val; val 420 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_CONTROL_0); val 421 drivers/input/keyboard/tegra-kbc.c val &= ~1; val 422 drivers/input/keyboard/tegra-kbc.c writel(val, kbc->mmio + KBC_CONTROL_0); val 720 drivers/input/keyboard/tegra-kbc.c u32 val; val 722 drivers/input/keyboard/tegra-kbc.c val = readl(kbc->mmio + KBC_CONTROL_0); val 724 drivers/input/keyboard/tegra-kbc.c val |= KBC_CONTROL_KEYPRESS_INT_EN; val 726 drivers/input/keyboard/tegra-kbc.c val &= ~KBC_CONTROL_KEYPRESS_INT_EN; val 727 drivers/input/keyboard/tegra-kbc.c writel(val, kbc->mmio + KBC_CONTROL_0); val 47 drivers/input/misc/88pm80x_onkey.c unsigned int val; val 49 drivers/input/misc/88pm80x_onkey.c ret = regmap_read(info->map, PM800_STATUS_1, &val); val 54 drivers/input/misc/88pm80x_onkey.c val &= PM800_ONKEY_STS1; val 56 drivers/input/misc/88pm80x_onkey.c input_report_key(info->idev, KEY_POWER, val); val 26 drivers/input/misc/adxl34x-i2c.c unsigned char reg, unsigned char val) val 30 drivers/input/misc/adxl34x-i2c.c return i2c_smbus_write_byte_data(client, reg, val); val 37 drivers/input/misc/adxl34x-spi.c unsigned char reg, unsigned char val) val 43 drivers/input/misc/adxl34x-spi.c buf[1] = val; val 182 drivers/input/misc/adxl34x.c #define AC_WRITE(ac, reg, val) ((ac)->bops->write((ac)->dev, reg, val)) val 454 drivers/input/misc/adxl34x.c unsigned int val; val 457 drivers/input/misc/adxl34x.c error = kstrtouint(buf, 10, &val); val 464 drivers/input/misc/adxl34x.c if (val) { val 473 drivers/input/misc/adxl34x.c ac->disabled = !!val; val 543 drivers/input/misc/adxl34x.c unsigned char val; val 546 drivers/input/misc/adxl34x.c error = kstrtou8(buf, 10, &val); val 552 drivers/input/misc/adxl34x.c ac->pdata.data_rate = RATE(val); val 578 drivers/input/misc/adxl34x.c unsigned int val; val 581 drivers/input/misc/adxl34x.c error = kstrtouint(buf, 10, &val); val 587 drivers/input/misc/adxl34x.c if (val) val 625 drivers/input/misc/adxl34x.c unsigned int val; val 631 drivers/input/misc/adxl34x.c error = kstrtouint(buf, 16, &val); val 636 drivers/input/misc/adxl34x.c AC_WRITE(ac, val >> 8, val & 0xFF); val 36 drivers/input/misc/ati_remote2.c static int ati_remote2_set_mask(const char *val, val 43 drivers/input/misc/ati_remote2.c if (!val) val 46 drivers/input/misc/ati_remote2.c ret = kstrtouint(val, 0, &mask); val 58 drivers/input/misc/ati_remote2.c static int ati_remote2_set_channel_mask(const char *val, val 63 drivers/input/misc/ati_remote2.c return ati_remote2_set_mask(val, kp, ATI_REMOTE2_MAX_CHANNEL_MASK); val 74 drivers/input/misc/ati_remote2.c static int ati_remote2_set_mode_mask(const char *val, val 79 drivers/input/misc/ati_remote2.c return ati_remote2_set_mask(val, kp, ATI_REMOTE2_MAX_MODE_MASK); val 92 drivers/input/misc/axp20x-pek.c unsigned int val; val 95 drivers/input/misc/axp20x-pek.c ret = regmap_read(axp20x_pek->axp20x->regmap, AXP20X_PEK_KEY, &val); val 99 drivers/input/misc/axp20x-pek.c val &= mask; val 100 drivers/input/misc/axp20x-pek.c val >>= ffs(mask) - 1; val 103 drivers/input/misc/axp20x-pek.c if (val == time[i].idx) val 104 drivers/input/misc/axp20x-pek.c val = time[i].time; val 106 drivers/input/misc/axp20x-pek.c return sprintf(buf, "%u\n", val); val 138 drivers/input/misc/axp20x-pek.c unsigned int val, idx = 0; val 148 drivers/input/misc/axp20x-pek.c ret = kstrtouint(val_str, 10, &val); val 155 drivers/input/misc/axp20x-pek.c err = abs(time[i].time - val); val 152 drivers/input/misc/bma150.c static int bma150_write_byte(struct i2c_client *client, u8 reg, u8 val) val 160 drivers/input/misc/bma150.c ret = i2c_smbus_write_byte_data(client, reg, val); val 169 drivers/input/misc/bma150.c int val, int shift, u8 mask, u8 reg) val 177 drivers/input/misc/bma150.c data = (data & ~mask) | ((val << shift) & mask); val 75 drivers/input/misc/cma3000_d0x.c #define CMA3000_SET(data, reg, val, msg) \ val 76 drivers/input/misc/cma3000_d0x.c ((data)->bus_ops->write(data->dev, reg, val, msg)) val 149 drivers/input/misc/cma3000_d0x.c int val; val 159 drivers/input/misc/cma3000_d0x.c val = CMA3000_READ(data, CMA3000_STATUS, "Status"); val 160 drivers/input/misc/cma3000_d0x.c if (val < 0) { val 162 drivers/input/misc/cma3000_d0x.c return val; val 165 drivers/input/misc/cma3000_d0x.c if (val & CMA3000_STATUS_PERR) { val 15 drivers/input/misc/cma3000_d0x_i2c.c u8 reg, u8 val, char *msg) val 20 drivers/input/misc/cma3000_d0x_i2c.c ret = i2c_smbus_write_byte_data(client, reg, val); val 39 drivers/input/misc/cpcap-pwrbutton.c int val; val 41 drivers/input/misc/cpcap-pwrbutton.c val = cpcap_sense_virq(button->regmap, irq); val 42 drivers/input/misc/cpcap-pwrbutton.c if (val < 0) { val 43 drivers/input/misc/cpcap-pwrbutton.c dev_err(button->dev, "irq read failed: %d", val); val 48 drivers/input/misc/cpcap-pwrbutton.c input_report_key(button->idev, KEY_POWER, val); val 88 drivers/input/misc/da9063_onkey.c unsigned int val; val 96 drivers/input/misc/da9063_onkey.c &val); val 103 drivers/input/misc/da9063_onkey.c if (!(val & config->onkey_nonkey_mask)) { val 163 drivers/input/misc/da9063_onkey.c unsigned int val; val 168 drivers/input/misc/da9063_onkey.c &val); val 169 drivers/input/misc/da9063_onkey.c if (onkey->key_power && !error && (val & config->onkey_nonkey_mask)) { val 38 drivers/input/misc/gpio_decoder.c int i, val; val 41 drivers/input/misc/gpio_decoder.c val = gpiod_get_value_cansleep(gpios->desc[i]); val 42 drivers/input/misc/gpio_decoder.c if (val < 0) { val 45 drivers/input/misc/gpio_decoder.c desc_to_gpio(gpios->desc[i]), val); val 46 drivers/input/misc/gpio_decoder.c return val; val 49 drivers/input/misc/gpio_decoder.c val = !!val; val 50 drivers/input/misc/gpio_decoder.c ret = (ret << 1) | val; val 58 drivers/input/misc/mc13783-pwrbutton.c int val; val 61 drivers/input/misc/mc13783-pwrbutton.c mc13xxx_reg_read(priv->mc13783, MC13783_REG_INTERRUPT_SENSE_1, &val); val 65 drivers/input/misc/mc13783-pwrbutton.c val = val & MC13783_IRQSENSE1_ONOFD1S ? 1 : 0; val 67 drivers/input/misc/mc13783-pwrbutton.c val ^= 1; val 68 drivers/input/misc/mc13783-pwrbutton.c input_report_key(priv->pwr, priv->keymap[0], val); val 72 drivers/input/misc/mc13783-pwrbutton.c val = val & MC13783_IRQSENSE1_ONOFD2S ? 1 : 0; val 74 drivers/input/misc/mc13783-pwrbutton.c val ^= 1; val 75 drivers/input/misc/mc13783-pwrbutton.c input_report_key(priv->pwr, priv->keymap[1], val); val 79 drivers/input/misc/mc13783-pwrbutton.c val = val & MC13783_IRQSENSE1_ONOFD3S ? 1 : 0; val 81 drivers/input/misc/mc13783-pwrbutton.c val ^= 1; val 82 drivers/input/misc/mc13783-pwrbutton.c input_report_key(priv->pwr, priv->keymap[2], val); val 116 drivers/input/misc/palmas-pwrbutton.c u32 val; val 130 drivers/input/misc/palmas-pwrbutton.c error = of_property_read_u32(np, "ti,palmas-long-press-seconds", &val); val 133 drivers/input/misc/palmas-pwrbutton.c if (val <= lpk_times[i]) { val 142 drivers/input/misc/palmas-pwrbutton.c &val); val 145 drivers/input/misc/palmas-pwrbutton.c if (val <= pwr_on_deb_ms[i]) { val 169 drivers/input/misc/palmas-pwrbutton.c int val; val 195 drivers/input/misc/palmas-pwrbutton.c val = config.long_press_time_val << __ffs(PALMAS_LPK_TIME_MASK); val 196 drivers/input/misc/palmas-pwrbutton.c val |= config.pwron_debounce_val << __ffs(PALMAS_PWRON_DEBOUNCE_MASK); val 201 drivers/input/misc/palmas-pwrbutton.c val); val 77 drivers/input/misc/pm8xxx-vibrator.c unsigned int val = vib->reg_vib_drv; val 81 drivers/input/misc/pm8xxx-vibrator.c val |= (vib->level << regs->drv_shift) & regs->drv_mask; val 83 drivers/input/misc/pm8xxx-vibrator.c val &= ~regs->drv_mask; val 85 drivers/input/misc/pm8xxx-vibrator.c rc = regmap_write(vib->regmap, regs->drv_addr, val); val 89 drivers/input/misc/pm8xxx-vibrator.c vib->reg_vib_drv = val; val 107 drivers/input/misc/pm8xxx-vibrator.c unsigned int val; val 109 drivers/input/misc/pm8xxx-vibrator.c rc = regmap_read(vib->regmap, regs->drv_addr, &val); val 172 drivers/input/misc/pm8xxx-vibrator.c unsigned int val; val 193 drivers/input/misc/pm8xxx-vibrator.c error = regmap_read(vib->regmap, regs->drv_addr, &val); val 197 drivers/input/misc/pm8xxx-vibrator.c val &= regs->drv_en_manual_mask; val 198 drivers/input/misc/pm8xxx-vibrator.c error = regmap_write(vib->regmap, regs->drv_addr, val); val 203 drivers/input/misc/pm8xxx-vibrator.c vib->reg_vib_drv = val; val 130 drivers/input/misc/pmic8xxx-pwrkey.c u8 mask, val; val 146 drivers/input/misc/pmic8xxx-pwrkey.c val = mask; val 148 drivers/input/misc/pmic8xxx-pwrkey.c val &= ~PON_CNTL_1_WD_EN_RESET; val 150 drivers/input/misc/pmic8xxx-pwrkey.c regmap_update_bits(pwrkey->regmap, PON_CNTL_1, mask, val); val 284 drivers/input/misc/pmic8xxx-pwrkey.c u8 mask, val; val 314 drivers/input/misc/pmic8xxx-pwrkey.c val = 0; val 316 drivers/input/misc/pmic8xxx-pwrkey.c val = mask; val 317 drivers/input/misc/pmic8xxx-pwrkey.c return regmap_update_bits(regmap, PM8058_SLEEP_CTRL, mask, val); val 324 drivers/input/misc/pmic8xxx-pwrkey.c u8 val = 0; val 328 drivers/input/misc/pmic8xxx-pwrkey.c val = mask; val 329 drivers/input/misc/pmic8xxx-pwrkey.c return regmap_update_bits(regmap, PM8921_SLEEP_CTRL, mask, val); val 36 drivers/input/misc/rb532_button.c int val; val 41 drivers/input/misc/rb532_button.c val = gpio_get_value(GPIO_BTN_S1); val 46 drivers/input/misc/rb532_button.c return !val; val 62 drivers/input/misc/rotary_encoder.c int val = gpiod_get_value_cansleep(encoder->gpios->desc[i]); val 66 drivers/input/misc/rotary_encoder.c val = !val; val 68 drivers/input/misc/rotary_encoder.c ret = ret << 1 | val; val 44 drivers/input/misc/sparcspkr.c u32 val, clock_freq = info->clock_freq; val 56 drivers/input/misc/sparcspkr.c val = 1 << 18; val 58 drivers/input/misc/sparcspkr.c val >>= 1; val 63 drivers/input/misc/sparcspkr.c return val; val 56 drivers/input/misc/stpmic1_onkey.c unsigned int val, reg = 0; val 71 drivers/input/misc/stpmic1_onkey.c if (!device_property_read_u32(dev, "power-off-time-sec", &val)) { val 72 drivers/input/misc/stpmic1_onkey.c if (val > 0 && val <= 16) { val 73 drivers/input/misc/stpmic1_onkey.c dev_dbg(dev, "power-off-time=%d seconds\n", val); val 75 drivers/input/misc/stpmic1_onkey.c reg |= ((16 - val) & PONKEY_TURNOFF_TIMER_MASK); val 1149 drivers/input/misc/wistron_btns.c u16 val; val 1155 drivers/input/misc/wistron_btns.c val = bios_pop_queue(); val 1156 drivers/input/misc/wistron_btns.c if (val != 0 && !discard) val 1157 drivers/input/misc/wistron_btns.c handle_key((u8)val); val 131 drivers/input/misc/yealink.c int i, a, m, val; val 151 drivers/input/misc/yealink.c val = map_to_seg7(&map_seg7, chr); val 159 drivers/input/misc/yealink.c if (val & 1) val 163 drivers/input/misc/yealink.c val = val >> 1; val 316 drivers/input/misc/yealink.c u8 val; val 334 drivers/input/misc/yealink.c val = yld->master.b[ix]; val 335 drivers/input/misc/yealink.c if (val != yld->copy.b[ix]) val 349 drivers/input/misc/yealink.c yld->copy.b[ix] = val; val 350 drivers/input/misc/yealink.c yld->ctl_data->data[0] = val; val 355 drivers/input/misc/yealink.c yld->ctl_data->sum = -1 - CMD_LED - val; val 359 drivers/input/misc/yealink.c yld->ctl_data->sum = -1 - CMD_DIALTONE - val; val 363 drivers/input/misc/yealink.c yld->ctl_data->sum = -1 - CMD_RINGTONE - val; val 366 drivers/input/misc/yealink.c val--; val 367 drivers/input/misc/yealink.c val &= 0x1f; val 369 drivers/input/misc/yealink.c yld->ctl_data->offset = cpu_to_be16(val); val 371 drivers/input/misc/yealink.c yld->ctl_data->sum = -1 - CMD_SCANCODE - val; val 383 drivers/input/misc/yealink.c yld->ctl_data->sum = -CMD_LCD - ix - val - len; val 386 drivers/input/misc/yealink.c val = yld->master.b[ix]; val 387 drivers/input/misc/yealink.c yld->copy.b[ix] = val; val 388 drivers/input/misc/yealink.c yld->ctl_data->data[i] = val; val 389 drivers/input/misc/yealink.c yld->ctl_data->sum -= val; val 53 drivers/input/mouse/elan_i2c.h int (*calibrate_result)(struct i2c_client *client, u8 *val); val 354 drivers/input/mouse/elan_i2c_core.c static unsigned int elan_convert_resolution(u8 val) val 363 drivers/input/mouse/elan_i2c_core.c return ((int)(char)val * 10 + 790) * 10 / 254; val 650 drivers/input/mouse/elan_i2c_core.c u8 val[ETP_CALIBRATE_MAX_LEN]; val 673 drivers/input/mouse/elan_i2c_core.c val[0] = 0xff; val 678 drivers/input/mouse/elan_i2c_core.c retval = data->ops->calibrate_result(client, val); val 682 drivers/input/mouse/elan_i2c_core.c else if (val[0] == 0) val 68 drivers/input/mouse/elan_i2c_i2c.c u16 reg, u8 *val, u16 len) val 84 drivers/input/mouse/elan_i2c_i2c.c .buf = val, val 93 drivers/input/mouse/elan_i2c_i2c.c static int elan_i2c_read_cmd(struct i2c_client *client, u16 reg, u8 *val) val 97 drivers/input/mouse/elan_i2c_i2c.c retval = elan_i2c_read_block(client, reg, val, ETP_I2C_INF_LENGTH); val 136 drivers/input/mouse/elan_i2c_i2c.c u8 val[256]; val 148 drivers/input/mouse/elan_i2c_i2c.c error = i2c_master_recv(client, val, ETP_I2C_INF_LENGTH); val 155 drivers/input/mouse/elan_i2c_i2c.c val, ETP_I2C_DESC_LENGTH); val 162 drivers/input/mouse/elan_i2c_i2c.c val, ETP_I2C_REPORT_DESC_LENGTH); val 179 drivers/input/mouse/elan_i2c_i2c.c u8 val[2]; val 183 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_POWER_CMD, val); val 191 drivers/input/mouse/elan_i2c_i2c.c reg = le16_to_cpup((__le16 *)val); val 219 drivers/input/mouse/elan_i2c_i2c.c static int elan_i2c_calibrate_result(struct i2c_client *client, u8 *val) val 221 drivers/input/mouse/elan_i2c_i2c.c return elan_i2c_read_block(client, ETP_I2C_CALIBRATE_CMD, val, 1); val 228 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 233 drivers/input/mouse/elan_i2c_i2c.c val); val 237 drivers/input/mouse/elan_i2c_i2c.c *value = le16_to_cpup((__le16 *)val); val 245 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 247 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_PATTERN_CMD, val); val 252 drivers/input/mouse/elan_i2c_i2c.c *pattern = val[1]; val 262 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 273 drivers/input/mouse/elan_i2c_i2c.c val); val 281 drivers/input/mouse/elan_i2c_i2c.c *version = iap ? val[1] : val[0]; val 283 drivers/input/mouse/elan_i2c_i2c.c *version = val[0]; val 293 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 302 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_IC_TYPE_CMD, val); val 308 drivers/input/mouse/elan_i2c_i2c.c *ic_type = be16_to_cpup((__be16 *)val); val 311 drivers/input/mouse/elan_i2c_i2c.c val); val 317 drivers/input/mouse/elan_i2c_i2c.c *version = val[1]; val 318 drivers/input/mouse/elan_i2c_i2c.c *clickpad = val[0] & 0x10; val 320 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_OSM_VERSION_CMD, val); val 326 drivers/input/mouse/elan_i2c_i2c.c *version = val[0]; val 327 drivers/input/mouse/elan_i2c_i2c.c *ic_type = val[1]; val 330 drivers/input/mouse/elan_i2c_i2c.c val); val 336 drivers/input/mouse/elan_i2c_i2c.c *clickpad = val[0] & 0x10; val 345 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 347 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_UNIQUEID_CMD, val); val 353 drivers/input/mouse/elan_i2c_i2c.c *id = le16_to_cpup((__le16 *)val); val 361 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 366 drivers/input/mouse/elan_i2c_i2c.c val); val 373 drivers/input/mouse/elan_i2c_i2c.c *csum = le16_to_cpup((__le16 *)val); val 381 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 383 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_MAX_X_AXIS_CMD, val); val 389 drivers/input/mouse/elan_i2c_i2c.c *max_x = le16_to_cpup((__le16 *)val) & 0x0fff; val 391 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_MAX_Y_AXIS_CMD, val); val 397 drivers/input/mouse/elan_i2c_i2c.c *max_y = le16_to_cpup((__le16 *)val) & 0x0fff; val 406 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 408 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_RESOLUTION_CMD, val); val 414 drivers/input/mouse/elan_i2c_i2c.c *hw_res_x = val[0]; val 415 drivers/input/mouse/elan_i2c_i2c.c *hw_res_y = val[1]; val 425 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 427 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_XY_TRACENUM_CMD, val); val 433 drivers/input/mouse/elan_i2c_i2c.c *x_traces = val[0]; val 434 drivers/input/mouse/elan_i2c_i2c.c *y_traces = val[1]; val 443 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 445 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_PRESSURE_CMD, val); val 452 drivers/input/mouse/elan_i2c_i2c.c if ((val[0] >> 4) & 0x1) val 464 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 466 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_IAP_CTRL_CMD, val); val 474 drivers/input/mouse/elan_i2c_i2c.c constant = le16_to_cpup((__le16 *)val); val 515 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 559 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_IAP_CMD, val); val 566 drivers/input/mouse/elan_i2c_i2c.c password = le16_to_cpup((__le16 *)val); val 580 drivers/input/mouse/elan_i2c_i2c.c u8 val[3]; val 600 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_read_cmd(client, ETP_I2C_IAP_CTRL_CMD, val); val 606 drivers/input/mouse/elan_i2c_i2c.c result = le16_to_cpup((__le16 *)val); val 114 drivers/input/mouse/elan_i2c_smbus.c static int elan_smbus_calibrate_result(struct i2c_client *client, u8 *val) val 126 drivers/input/mouse/elan_i2c_smbus.c memcpy(val, buf, ETP_CALIBRATE_MAX_LEN); val 134 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 140 drivers/input/mouse/elan_i2c_smbus.c val); val 144 drivers/input/mouse/elan_i2c_smbus.c *value = be16_to_cpup((__be16 *)val); val 153 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 158 drivers/input/mouse/elan_i2c_smbus.c val); val 165 drivers/input/mouse/elan_i2c_smbus.c *version = val[2]; val 174 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 177 drivers/input/mouse/elan_i2c_smbus.c ETP_SMBUS_SM_VERSION_CMD, val); val 183 drivers/input/mouse/elan_i2c_smbus.c *version = val[0]; val 184 drivers/input/mouse/elan_i2c_smbus.c *ic_type = val[1]; val 185 drivers/input/mouse/elan_i2c_smbus.c *clickpad = val[0] & 0x10; val 192 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 195 drivers/input/mouse/elan_i2c_smbus.c ETP_SMBUS_UNIQUEID_CMD, val); val 201 drivers/input/mouse/elan_i2c_smbus.c *id = be16_to_cpup((__be16 *)val); val 209 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 214 drivers/input/mouse/elan_i2c_smbus.c val); val 221 drivers/input/mouse/elan_i2c_smbus.c *csum = be16_to_cpup((__be16 *)val); val 230 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 232 drivers/input/mouse/elan_i2c_smbus.c ret = i2c_smbus_read_block_data(client, ETP_SMBUS_RANGE_CMD, val); val 239 drivers/input/mouse/elan_i2c_smbus.c *max_x = (0x0f & val[0]) << 8 | val[1]; val 240 drivers/input/mouse/elan_i2c_smbus.c *max_y = (0xf0 & val[0]) << 4 | val[2]; val 250 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 252 drivers/input/mouse/elan_i2c_smbus.c ret = i2c_smbus_read_block_data(client, ETP_SMBUS_RESOLUTION_CMD, val); val 259 drivers/input/mouse/elan_i2c_smbus.c *hw_res_x = val[1] & 0x0F; val 260 drivers/input/mouse/elan_i2c_smbus.c *hw_res_y = (val[1] & 0xF0) >> 4; val 271 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 273 drivers/input/mouse/elan_i2c_smbus.c ret = i2c_smbus_read_block_data(client, ETP_SMBUS_XY_TRACENUM_CMD, val); val 280 drivers/input/mouse/elan_i2c_smbus.c *x_traces = val[1]; val 281 drivers/input/mouse/elan_i2c_smbus.c *y_traces = val[2]; val 298 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 300 drivers/input/mouse/elan_i2c_smbus.c error = i2c_smbus_read_block_data(client, ETP_SMBUS_IAP_CTRL_CMD, val); val 307 drivers/input/mouse/elan_i2c_smbus.c constant = be16_to_cpup((__be16 *)val); val 349 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 386 drivers/input/mouse/elan_i2c_smbus.c val); val 394 drivers/input/mouse/elan_i2c_smbus.c password = be16_to_cpup((__be16 *)val); val 423 drivers/input/mouse/elan_i2c_smbus.c u8 val[I2C_SMBUS_BLOCK_MAX] = {0}; val 455 drivers/input/mouse/elan_i2c_smbus.c ETP_SMBUS_IAP_CTRL_CMD, val); val 462 drivers/input/mouse/elan_i2c_smbus.c result = be16_to_cpup((__be16 *)val); val 96 drivers/input/mouse/elantech.c unsigned char *val) val 141 drivers/input/mouse/elantech.c *val = param[0]; val 143 drivers/input/mouse/elantech.c *val = param[1]; val 152 drivers/input/mouse/elantech.c unsigned char val) val 167 drivers/input/mouse/elantech.c ps2_sliced_command(&psmouse->ps2dev, val) || val 179 drivers/input/mouse/elantech.c elantech_ps2_command(psmouse, NULL, val) || val 191 drivers/input/mouse/elantech.c elantech_ps2_command(psmouse, NULL, val) || val 205 drivers/input/mouse/elantech.c elantech_ps2_command(psmouse, NULL, val) || val 215 drivers/input/mouse/elantech.c reg, val); val 961 drivers/input/mouse/elantech.c unsigned char val; val 1014 drivers/input/mouse/elantech.c rc = elantech_read_reg(psmouse, 0x10, &val); val 1026 drivers/input/mouse/elantech.c !(val & ETP_R10_ABSOLUTE_MODE)) { val 1044 drivers/input/mouse/elantech.c static unsigned int elantech_convert_res(unsigned int val) val 1046 drivers/input/mouse/elantech.c return (val * 10 + 790) * 10 / 254; val 47 drivers/input/mouse/psmouse-base.c static int psmouse_set_maxproto(const char *val, const struct kernel_param *); val 2024 drivers/input/mouse/psmouse-base.c static int psmouse_set_maxproto(const char *val, const struct kernel_param *kp) val 2028 drivers/input/mouse/psmouse-base.c if (!val) val 2031 drivers/input/mouse/psmouse-base.c proto = psmouse_protocol_by_name(val, strlen(val)); val 322 drivers/input/mouse/sentelic.c int val; val 324 drivers/input/mouse/sentelic.c if (fsp_reg_read(psmouse, FSP_REG_TMOD_STATUS, &val) == -1) val 327 drivers/input/mouse/sentelic.c *btn = buttons[(val & 0x30) >> 4]; val 365 drivers/input/mouse/sentelic.c int val; val 367 drivers/input/mouse/sentelic.c if (fsp_reg_read(psmouse, FSP_REG_ONPAD_CTL, &val)) val 373 drivers/input/mouse/sentelic.c val |= (FSP_BIT_FIX_VSCR | FSP_BIT_ONPAD_ENABLE); val 375 drivers/input/mouse/sentelic.c val &= ~FSP_BIT_FIX_VSCR; val 377 drivers/input/mouse/sentelic.c if (fsp_reg_write(psmouse, FSP_REG_ONPAD_CTL, val)) val 386 drivers/input/mouse/sentelic.c int val, v2; val 388 drivers/input/mouse/sentelic.c if (fsp_reg_read(psmouse, FSP_REG_ONPAD_CTL, &val)) val 397 drivers/input/mouse/sentelic.c val |= (FSP_BIT_FIX_HSCR | FSP_BIT_ONPAD_ENABLE); val 400 drivers/input/mouse/sentelic.c val &= ~FSP_BIT_FIX_HSCR; val 404 drivers/input/mouse/sentelic.c if (fsp_reg_write(psmouse, FSP_REG_ONPAD_CTL, val)) val 422 drivers/input/mouse/sentelic.c unsigned int reg, val; val 430 drivers/input/mouse/sentelic.c retval = kstrtouint(rest + 1, 16, &val); val 434 drivers/input/mouse/sentelic.c if (val > 0xff) val 440 drivers/input/mouse/sentelic.c retval = fsp_reg_write(psmouse, reg, val) < 0 ? -EIO : count; val 466 drivers/input/mouse/sentelic.c unsigned int reg, val; val 476 drivers/input/mouse/sentelic.c if (fsp_reg_read(psmouse, reg, &val)) val 480 drivers/input/mouse/sentelic.c pad->last_val = val; val 491 drivers/input/mouse/sentelic.c int val = 0; val 493 drivers/input/mouse/sentelic.c if (fsp_page_reg_read(psmouse, &val)) val 496 drivers/input/mouse/sentelic.c return sprintf(buf, "%02x\n", val); val 502 drivers/input/mouse/sentelic.c unsigned int val; val 505 drivers/input/mouse/sentelic.c err = kstrtouint(buf, 16, &val); val 509 drivers/input/mouse/sentelic.c if (val > 0xff) val 512 drivers/input/mouse/sentelic.c if (fsp_page_reg_write(psmouse, val)) val 532 drivers/input/mouse/sentelic.c unsigned int val; val 535 drivers/input/mouse/sentelic.c err = kstrtouint(buf, 10, &val); val 539 drivers/input/mouse/sentelic.c if (val > 1) val 542 drivers/input/mouse/sentelic.c fsp_onpad_vscr(psmouse, val); val 561 drivers/input/mouse/sentelic.c unsigned int val; val 564 drivers/input/mouse/sentelic.c err = kstrtouint(buf, 10, &val); val 568 drivers/input/mouse/sentelic.c if (val > 1) val 571 drivers/input/mouse/sentelic.c fsp_onpad_hscr(psmouse, val); val 843 drivers/input/mouse/sentelic.c int val; val 865 drivers/input/mouse/sentelic.c if (fsp_reg_read(psmouse, FSP_REG_SYSCTL5, &val)) { val 877 drivers/input/mouse/sentelic.c val &= ~(FSP_BIT_EN_MSID7 | FSP_BIT_EN_MSID8 | FSP_BIT_EN_AUTO_MSID8); val 879 drivers/input/mouse/sentelic.c val &= ~FSP_BIT_EN_PKT_G0; val 882 drivers/input/mouse/sentelic.c val |= FSP_BIT_EN_MSID6; val 885 drivers/input/mouse/sentelic.c if (fsp_reg_write(psmouse, FSP_REG_SYSCTL5, val)) { val 218 drivers/input/mouse/synaptics.c static int synaptics_query_int(struct psmouse *psmouse, u8 query_cmd, u32 *val) val 230 drivers/input/mouse/synaptics.c *val = be32_to_cpu(resp.be_val); val 252 drivers/input/mouse/synaptics_i2c.c static s32 synaptics_i2c_reg_set(struct i2c_client *client, u16 reg, u8 val) val 258 drivers/input/mouse/synaptics_i2c.c ret = i2c_smbus_write_byte_data(client, reg & 0xff, val); val 57 drivers/input/mouse/trackpoint.c static int trackpoint_write(struct ps2dev *ps2dev, u8 loc, u8 val) val 59 drivers/input/mouse/trackpoint.c u8 param[3] = { TP_WRITE_MEM, loc, val }; val 229 drivers/input/rmi4/rmi_2d_sensor.c u32 val; val 240 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,clip-x-low", 1); val 244 drivers/input/rmi4/rmi_2d_sensor.c pdata->axis_align.clip_x_low = val; val 246 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,clip-y-low", 1); val 250 drivers/input/rmi4/rmi_2d_sensor.c pdata->axis_align.clip_y_low = val; val 252 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,clip-x-high", 1); val 256 drivers/input/rmi4/rmi_2d_sensor.c pdata->axis_align.clip_x_high = val; val 258 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,clip-y-high", 1); val 262 drivers/input/rmi4/rmi_2d_sensor.c pdata->axis_align.clip_y_high = val; val 264 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,offset-x", 1); val 268 drivers/input/rmi4/rmi_2d_sensor.c pdata->axis_align.offset_x = val; val 270 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,offset-y", 1); val 274 drivers/input/rmi4/rmi_2d_sensor.c pdata->axis_align.offset_y = val; val 276 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,delta-x-threshold", val 281 drivers/input/rmi4/rmi_2d_sensor.c pdata->axis_align.delta_x_threshold = val; val 283 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,delta-y-threshold", val 288 drivers/input/rmi4/rmi_2d_sensor.c pdata->axis_align.delta_y_threshold = val; val 295 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "touchscreen-x-mm", 1); val 299 drivers/input/rmi4/rmi_2d_sensor.c pdata->x_mm = val; val 301 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "touchscreen-y-mm", 1); val 305 drivers/input/rmi4/rmi_2d_sensor.c pdata->y_mm = val; val 307 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, val 312 drivers/input/rmi4/rmi_2d_sensor.c pdata->disable_report_mask = val; val 314 drivers/input/rmi4/rmi_2d_sensor.c retval = rmi_of_property_read_u32(dev, &val, "syna,rezero-wait-ms", val 319 drivers/input/rmi4/rmi_2d_sensor.c pdata->rezero_wait = val; val 414 drivers/input/rmi4/rmi_bus.c u32 val = 0; val 416 drivers/input/rmi4/rmi_bus.c retval = of_property_read_u32(dev->of_node, prop, &val); val 422 drivers/input/rmi4/rmi_bus.c *result = val; val 343 drivers/input/rmi4/rmi_f01.c u32 val; val 351 drivers/input/rmi4/rmi_f01.c retval = rmi_of_property_read_u32(dev, &val, val 356 drivers/input/rmi4/rmi_f01.c pdata->power_management.wakeup_threshold = val; val 358 drivers/input/rmi4/rmi_f01.c retval = rmi_of_property_read_u32(dev, &val, val 363 drivers/input/rmi4/rmi_f01.c pdata->power_management.doze_holdoff = val * 100; val 365 drivers/input/rmi4/rmi_f01.c retval = rmi_of_property_read_u32(dev, &val, val 370 drivers/input/rmi4/rmi_f01.c pdata->power_management.doze_interval = val / 10; val 74 drivers/input/rmi4/rmi_f03.c static int rmi_f03_pt_write(struct serio *id, unsigned char val) val 81 drivers/input/rmi4/rmi_f03.c __func__, val); val 83 drivers/input/rmi4/rmi_f03.c error = rmi_write(f03->fn->rmi_dev, f03->fn->fd.data_base_addr, val); val 48 drivers/input/serio/altera_ps2.c static int altera_ps2_write(struct serio *io, unsigned char val) val 52 drivers/input/serio/altera_ps2.c writel(val, ps2if->base); val 50 drivers/input/serio/ambakmi.c static int amba_kmi_write(struct serio *io, unsigned char val) val 59 drivers/input/serio/ambakmi.c writeb(val, KMIDATA); val 82 drivers/input/serio/apbps2.c static int apbps2_write(struct serio *io, unsigned char val) val 92 drivers/input/serio/apbps2.c iowrite32be(val, &priv->regs->data); val 87 drivers/input/serio/arc_ps2.c static int arc_ps2_write(struct serio *io, unsigned char val) val 98 drivers/input/serio/arc_ps2.c iowrite32(val & 0xff, port->data_addr); val 140 drivers/input/serio/arc_ps2.c u32 val; val 145 drivers/input/serio/arc_ps2.c val = ioread32(addr); val 146 drivers/input/serio/arc_ps2.c val &= ~(PS2_STAT_RX_INT_EN | PS2_STAT_TX_INT_EN); val 147 drivers/input/serio/arc_ps2.c iowrite32(val, addr); val 87 drivers/input/serio/hil_mlc.c static void hil_mlc_clear_di_map(hil_mlc *mlc, int val) val 91 drivers/input/serio/hil_mlc.c for (j = val; j < 7 ; j++) val 294 drivers/input/serio/hil_mlc.c static int hilse_set_lcv(hil_mlc *mlc, int val) val 296 drivers/input/serio/hil_mlc.c mlc->lcv = val; val 303 drivers/input/serio/hil_mlc.c static int hilse_set_ddi(hil_mlc *mlc, int val) val 305 drivers/input/serio/hil_mlc.c mlc->ddi = val; val 306 drivers/input/serio/hil_mlc.c hil_mlc_clear_di_map(mlc, val + 1); val 133 drivers/input/serio/hp_sdc.c static inline void hp_sdc_status_out8(uint8_t val) val 139 drivers/input/serio/hp_sdc.c if ((val & 0xf0) == 0xe0) val 141 drivers/input/serio/hp_sdc.c sdc_writeb(val, hp_sdc.status_io); val 145 drivers/input/serio/hp_sdc.c static inline void hp_sdc_data_out8(uint8_t val) val 151 drivers/input/serio/hp_sdc.c sdc_writeb(val, hp_sdc.data_io); val 55 drivers/input/serio/i8042-io.h static inline void i8042_write_data(int val) val 57 drivers/input/serio/i8042-io.h outb(val, I8042_DATA_REG); val 60 drivers/input/serio/i8042-io.h static inline void i8042_write_command(int val) val 62 drivers/input/serio/i8042-io.h outb(val, I8042_COMMAND_REG); val 42 drivers/input/serio/i8042-ip22io.h static inline void i8042_write_data(int val) val 44 drivers/input/serio/i8042-ip22io.h sgioc->kbdmouse.data = val; val 47 drivers/input/serio/i8042-ip22io.h static inline void i8042_write_command(int val) val 49 drivers/input/serio/i8042-ip22io.h sgioc->kbdmouse.command = val; val 37 drivers/input/serio/i8042-jazzio.h static inline void i8042_write_data(int val) val 39 drivers/input/serio/i8042-jazzio.h jazz_kh->data = val; val 42 drivers/input/serio/i8042-jazzio.h static inline void i8042_write_command(int val) val 44 drivers/input/serio/i8042-jazzio.h jazz_kh->command = val; val 31 drivers/input/serio/i8042-ppcio.h static inline void i8042_write_data(int val) val 33 drivers/input/serio/i8042-ppcio.h writeb(val, kb_data); val 36 drivers/input/serio/i8042-ppcio.h static inline void i8042_write_command(int val) val 38 drivers/input/serio/i8042-ppcio.h writeb(val, kb_cs); val 39 drivers/input/serio/i8042-snirm.h static inline void i8042_write_data(int val) val 41 drivers/input/serio/i8042-snirm.h writeb(val, kbd_iobase + 0x60UL); val 44 drivers/input/serio/i8042-snirm.h static inline void i8042_write_command(int val) val 46 drivers/input/serio/i8042-snirm.h writeb(val, kbd_iobase + 0x64UL); val 35 drivers/input/serio/i8042-sparcio.h static inline void i8042_write_data(int val) val 37 drivers/input/serio/i8042-sparcio.h writeb(val, kbd_iobase + 0x60UL); val 40 drivers/input/serio/i8042-sparcio.h static inline void i8042_write_command(int val) val 42 drivers/input/serio/i8042-sparcio.h writeb(val, kbd_iobase + 0x64UL); val 46 drivers/input/serio/i8042-unicore32io.h static inline void i8042_write_data(int val) val 48 drivers/input/serio/i8042-unicore32io.h writeb(val, I8042_DATA_REG); val 51 drivers/input/serio/i8042-unicore32io.h static inline void i8042_write_command(int val) val 53 drivers/input/serio/i8042-unicore32io.h writeb(val, I8042_COMMAND_REG); val 56 drivers/input/serio/i8042-x86ia64io.h static inline void i8042_write_data(int val) val 58 drivers/input/serio/i8042-x86ia64io.h outb(val, I8042_DATA_REG); val 61 drivers/input/serio/i8042-x86ia64io.h static inline void i8042_write_command(int val) val 63 drivers/input/serio/i8042-x86ia64io.h outb(val, I8042_COMMAND_REG); val 54 drivers/input/serio/i8042.c static int i8042_set_reset(const char *val, const struct kernel_param *kp) val 60 drivers/input/serio/i8042.c if (val) { val 61 drivers/input/serio/i8042.c error = kstrtobool(val, &reset); val 667 drivers/input/serio/i8042.c unsigned char param, val; val 679 drivers/input/serio/i8042.c param = val = 0xf0; val 680 drivers/input/serio/i8042.c if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) val 682 drivers/input/serio/i8042.c param = val = multiplex ? 0x56 : 0xf6; val 683 drivers/input/serio/i8042.c if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) val 685 drivers/input/serio/i8042.c param = val = multiplex ? 0xa4 : 0xa5; val 686 drivers/input/serio/i8042.c if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) val 55 drivers/input/serio/maceps2.c static int maceps2_write(struct serio *dev, unsigned char val) val 62 drivers/input/serio/maceps2.c port->tx = val; val 72 drivers/input/serio/olpc_apsp.c static int olpc_apsp_write(struct serio *port, unsigned char val) val 83 drivers/input/serio/olpc_apsp.c dev_dbg(priv->dev, "olpc_apsp_write which=%x val=%x\n", which, val); val 87 drivers/input/serio/olpc_apsp.c writel(which | val, val 43 drivers/input/serio/pcips2.c static int pcips2_write(struct serio *io, unsigned char val) val 53 drivers/input/serio/pcips2.c outb(val, ps2if->base + PS2_DATA); val 102 drivers/input/serio/pcips2.c int ret, val = 0; val 110 drivers/input/serio/pcips2.c val = PS2_CTRL_ENABLE | PS2_CTRL_RXIRQ; val 112 drivers/input/serio/pcips2.c outb(val, ps2if->base); val 80 drivers/input/serio/ps2-gpio.c static int __ps2_gpio_write(struct serio *serio, unsigned char val) val 88 drivers/input/serio/ps2-gpio.c drvdata->tx_byte = val; val 95 drivers/input/serio/ps2-gpio.c static int ps2_gpio_write(struct serio *serio, unsigned char val) val 102 drivers/input/serio/ps2-gpio.c __ps2_gpio_write(serio, val); val 108 drivers/input/serio/ps2-gpio.c __ps2_gpio_write(serio, val); val 35 drivers/input/serio/rpckbd.c static int rpckbd_write(struct serio *port, unsigned char val) val 40 drivers/input/serio/rpckbd.c iomd_writeb(val, IOMD_KARTTX); val 113 drivers/input/serio/sa1111ps2.c static int ps2_write(struct serio *io, unsigned char val) val 125 drivers/input/serio/sa1111ps2.c writel_relaxed(val, ps2if->base + PS2DATA); val 131 drivers/input/serio/sa1111ps2.c ps2if->buf[ps2if->head] = val; val 208 drivers/input/serio/sa1111ps2.c unsigned int val; val 214 drivers/input/serio/sa1111ps2.c val = readl_relaxed(ps2if->base + PS2STAT); val 215 drivers/input/serio/sa1111ps2.c return val & (PS2STAT_KBC | PS2STAT_KBD); val 895 drivers/input/serio/serio.c #define SERIO_ADD_UEVENT_VAR(fmt, val...) \ val 897 drivers/input/serio/serio.c int err = add_uevent_var(env, fmt, val); \ val 193 drivers/input/serio/sun4i-ps2.c static int sun4i_ps2_write(struct serio *serio, unsigned char val) val 200 drivers/input/serio/sun4i-ps2.c writel(val, drvdata->reg_base + PS2_REG_DATA); val 55 drivers/input/serio/userio.c static int userio_device_write(struct serio *id, unsigned char val) val 62 drivers/input/serio/userio.c userio->buf[userio->head] = val; val 367 drivers/input/tablet/aiptek.c static const char *map_val_to_str(const struct aiptek_map *map, int val) val 372 drivers/input/tablet/aiptek.c if (val == p->value) val 632 drivers/input/tablet/gtco.c u32 val = 0; val 672 drivers/input/tablet/gtco.c val = ((u16)(device->buffer[8]) << 1); val 673 drivers/input/tablet/gtco.c val |= (u16)(device->buffer[7] >> 7); val 693 drivers/input/tablet/gtco.c val = (device->buffer[5]) & MASK_BUTTON; val 697 drivers/input/tablet/gtco.c input_event(inputdev, EV_MSC, MSC_SERIAL, val); val 702 drivers/input/tablet/gtco.c val = get_unaligned_le16(&device->buffer[1]); val 703 drivers/input/tablet/gtco.c input_report_abs(inputdev, ABS_X, val); val 705 drivers/input/tablet/gtco.c val = get_unaligned_le16(&device->buffer[3]); val 706 drivers/input/tablet/gtco.c input_report_abs(inputdev, ABS_Y, val); val 709 drivers/input/tablet/gtco.c val = device->buffer[5] & MASK_INRANGE ? 1 : 0; val 710 drivers/input/tablet/gtco.c input_report_abs(inputdev, ABS_DISTANCE, val); val 721 drivers/input/tablet/gtco.c val = device->buffer[5] & MASK_BUTTON; val 724 drivers/input/tablet/gtco.c val, val); val 730 drivers/input/tablet/gtco.c input_event(inputdev, EV_MSC, MSC_SERIAL, val); val 759 drivers/input/tablet/gtco.c val = (u16)(((u16)(device->buffer[2] << 8)) | (u8)device->buffer[1]); val 760 drivers/input/tablet/gtco.c val |= (u32)(((u8)device->buffer[3] & 0x1) << 16); val 762 drivers/input/tablet/gtco.c input_report_abs(inputdev, ABS_X, val); val 770 drivers/input/tablet/gtco.c val = get_unaligned_le16(le_buffer); val 771 drivers/input/tablet/gtco.c input_report_abs(inputdev, ABS_Y, val); val 780 drivers/input/tablet/gtco.c val = get_unaligned_le16(&device->buffer[1]); val 781 drivers/input/tablet/gtco.c input_report_abs(inputdev, ABS_X, val); val 783 drivers/input/tablet/gtco.c val = get_unaligned_le16(&device->buffer[3]); val 784 drivers/input/tablet/gtco.c input_report_abs(inputdev, ABS_Y, val); val 790 drivers/input/tablet/gtco.c val = buttonbyte & MASK_INRANGE ? 1 : 0; val 791 drivers/input/tablet/gtco.c input_report_abs(inputdev, ABS_DISTANCE, val); val 794 drivers/input/tablet/gtco.c val = buttonbyte & 0x0F; val 797 drivers/input/tablet/gtco.c input_report_key(inputdev, BTN_DIGI + i, val & (1 << i)); val 800 drivers/input/tablet/gtco.c input_event(inputdev, EV_MSC, MSC_SERIAL, val); val 230 drivers/input/touchscreen/ad7877.c static int ad7877_write(struct spi_device *spi, u16 reg, u16 val) val 241 drivers/input/touchscreen/ad7877.c req->command = (u16) (AD7877_WRITEADD(reg) | (val & MAX_12BIT)); val 473 drivers/input/touchscreen/ad7877.c unsigned int val; val 476 drivers/input/touchscreen/ad7877.c error = kstrtouint(buf, 10, &val); val 480 drivers/input/touchscreen/ad7877.c if (val) val 503 drivers/input/touchscreen/ad7877.c unsigned int val; val 506 drivers/input/touchscreen/ad7877.c error = kstrtouint(buf, 10, &val); val 511 drivers/input/touchscreen/ad7877.c ts->dac = val & 0xFF; val 533 drivers/input/touchscreen/ad7877.c unsigned int val; val 536 drivers/input/touchscreen/ad7877.c error = kstrtouint(buf, 10, &val); val 541 drivers/input/touchscreen/ad7877.c ts->gpio3 = !!val; val 564 drivers/input/touchscreen/ad7877.c unsigned int val; val 567 drivers/input/touchscreen/ad7877.c error = kstrtouint(buf, 10, &val); val 572 drivers/input/touchscreen/ad7877.c ts->gpio4 = !!val; val 137 drivers/input/touchscreen/ad7879.c unsigned int val; val 140 drivers/input/touchscreen/ad7879.c error = regmap_read(ts->regmap, reg, &val); val 147 drivers/input/touchscreen/ad7879.c return val; val 150 drivers/input/touchscreen/ad7879.c static int ad7879_write(struct ad7879 *ts, u8 reg, u16 val) val 154 drivers/input/touchscreen/ad7879.c error = regmap_write(ts->regmap, reg, val); val 158 drivers/input/touchscreen/ad7879.c val, reg, error); val 371 drivers/input/touchscreen/ad7879.c unsigned int val; val 374 drivers/input/touchscreen/ad7879.c error = kstrtouint(buf, 10, &val); val 378 drivers/input/touchscreen/ad7879.c ad7879_toggle(ts, val); val 432 drivers/input/touchscreen/ad7879.c u16 val; val 435 drivers/input/touchscreen/ad7879.c val = ad7879_read(ts, AD7879_REG_CTRL2); val 438 drivers/input/touchscreen/ad7879.c return !!(val & AD7879_GPIO_DATA); val 140 drivers/input/touchscreen/ads7846.c int (*filter)(void *data, int data_idx, int *val); val 620 drivers/input/touchscreen/ads7846.c static int ads7846_debounce_filter(void *ads, int data_idx, int *val) val 624 drivers/input/touchscreen/ads7846.c if (!ts->read_cnt || (abs(ts->last_read - *val) > ts->debounce_tol)) { val 632 drivers/input/touchscreen/ads7846.c ts->last_read = *val; val 662 drivers/input/touchscreen/ads7846.c static int ads7846_no_filter(void *ads, int data_idx, int *val) val 687 drivers/input/touchscreen/ads7846.c static void ads7846_update_value(struct spi_message *m, int val) val 692 drivers/input/touchscreen/ads7846.c *(u16 *)t->rx_buf = val; val 700 drivers/input/touchscreen/ads7846.c int val; val 722 drivers/input/touchscreen/ads7846.c val = ads7846_get_value(ts, m); val 724 drivers/input/touchscreen/ads7846.c action = ts->filter(ts->filter_data, msg_idx, &val); val 735 drivers/input/touchscreen/ads7846.c ads7846_update_value(m, val); val 416 drivers/input/touchscreen/atmel_mxt_ts.c u8 *val, unsigned int count) val 425 drivers/input/touchscreen/atmel_mxt_ts.c msg.buf = val; val 440 drivers/input/touchscreen/atmel_mxt_ts.c const u8 * const val, unsigned int count) val 448 drivers/input/touchscreen/atmel_mxt_ts.c msg.buf = (u8 *)val; val 499 drivers/input/touchscreen/atmel_mxt_ts.c u8 val; val 506 drivers/input/touchscreen/atmel_mxt_ts.c error = mxt_bootloader_read(data, &val, 1); val 511 drivers/input/touchscreen/atmel_mxt_ts.c crc_failure = (val & ~MXT_BOOT_STATUS_MASK) == MXT_APP_CRC_FAIL; val 514 drivers/input/touchscreen/atmel_mxt_ts.c val, crc_failure ? ", APP_CRC_FAIL" : ""); val 519 drivers/input/touchscreen/atmel_mxt_ts.c static u8 mxt_get_bootloader_version(struct mxt_data *data, u8 val) val 524 drivers/input/touchscreen/atmel_mxt_ts.c if (val & MXT_BOOT_EXTENDED_ID) { val 527 drivers/input/touchscreen/atmel_mxt_ts.c return val; val 534 drivers/input/touchscreen/atmel_mxt_ts.c dev_dbg(dev, "Bootloader ID:%d\n", val & MXT_BOOT_ID_MASK); val 536 drivers/input/touchscreen/atmel_mxt_ts.c return val; val 544 drivers/input/touchscreen/atmel_mxt_ts.c u8 val; val 569 drivers/input/touchscreen/atmel_mxt_ts.c ret = mxt_bootloader_read(data, &val, 1); val 574 drivers/input/touchscreen/atmel_mxt_ts.c val = mxt_get_bootloader_version(data, val); val 580 drivers/input/touchscreen/atmel_mxt_ts.c val &= ~MXT_BOOT_STATUS_MASK; val 583 drivers/input/touchscreen/atmel_mxt_ts.c if (val == MXT_FRAME_CRC_CHECK) { val 585 drivers/input/touchscreen/atmel_mxt_ts.c } else if (val == MXT_FRAME_CRC_FAIL) { val 594 drivers/input/touchscreen/atmel_mxt_ts.c if (val != state) { val 596 drivers/input/touchscreen/atmel_mxt_ts.c val, state); val 624 drivers/input/touchscreen/atmel_mxt_ts.c u16 reg, u16 len, void *val) val 643 drivers/input/touchscreen/atmel_mxt_ts.c xfer[1].buf = val; val 659 drivers/input/touchscreen/atmel_mxt_ts.c const void *val) val 672 drivers/input/touchscreen/atmel_mxt_ts.c memcpy(&buf[2], val, len); val 688 drivers/input/touchscreen/atmel_mxt_ts.c static int mxt_write_reg(struct i2c_client *client, u16 reg, u8 val) val 690 drivers/input/touchscreen/atmel_mxt_ts.c return __mxt_write_reg(client, reg, 1, &val); val 743 drivers/input/touchscreen/atmel_mxt_ts.c u8 type, u8 offset, u8 val) val 753 drivers/input/touchscreen/atmel_mxt_ts.c return mxt_write_reg(data->client, reg + offset, val); val 1295 drivers/input/touchscreen/atmel_mxt_ts.c u8 val; val 1315 drivers/input/touchscreen/atmel_mxt_ts.c &val, &offset); val 1357 drivers/input/touchscreen/atmel_mxt_ts.c &val, val 1372 drivers/input/touchscreen/atmel_mxt_ts.c *(cfg->mem + byte_offset) = val; val 2688 drivers/input/touchscreen/atmel_mxt_ts.c const u8 *val) val 2698 drivers/input/touchscreen/atmel_mxt_ts.c "\t[%2u]: %02x (%d)\n", i, val[i], val[i]); val 94 drivers/input/touchscreen/bcm_iproc_tsc.c u32 val; \ val 95 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_read(priv->regmap, reg, &val); \ val 96 drivers/input/touchscreen/bcm_iproc_tsc.c dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \ val 271 drivers/input/touchscreen/bcm_iproc_tsc.c u32 val; val 288 drivers/input/touchscreen/bcm_iproc_tsc.c val = TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK; val 289 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_update_bits(priv->regmap, INTERRUPT_MASK, val, val); val 291 drivers/input/touchscreen/bcm_iproc_tsc.c val = priv->cfg_params.fifo_threshold; val 292 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_write(priv->regmap, INTERRUPT_THRES, val); val 295 drivers/input/touchscreen/bcm_iproc_tsc.c val = 0; val 296 drivers/input/touchscreen/bcm_iproc_tsc.c val |= priv->cfg_params.scanning_period << SCANNING_PERIOD_SHIFT; val 297 drivers/input/touchscreen/bcm_iproc_tsc.c val |= priv->cfg_params.debounce_timeout << DEBOUNCE_TIMEOUT_SHIFT; val 298 drivers/input/touchscreen/bcm_iproc_tsc.c val |= priv->cfg_params.settling_timeout << SETTLING_TIMEOUT_SHIFT; val 299 drivers/input/touchscreen/bcm_iproc_tsc.c val |= priv->cfg_params.touch_timeout << TOUCH_TIMEOUT_SHIFT; val 300 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_write(priv->regmap, REGCTL1, val); val 303 drivers/input/touchscreen/bcm_iproc_tsc.c val = TS_FIFO_INTR_MASK | TS_PEN_INTR_MASK; val 304 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_update_bits(priv->regmap, INTERRUPT_STATUS, val, val); val 307 drivers/input/touchscreen/bcm_iproc_tsc.c val = TS_CONTROLLER_EN_BIT | TS_WIRE_MODE_BIT; val 308 drivers/input/touchscreen/bcm_iproc_tsc.c val |= priv->cfg_params.average_data << TS_CONTROLLER_AVGDATA_SHIFT; val 315 drivers/input/touchscreen/bcm_iproc_tsc.c mask |= val; val 316 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_update_bits(priv->regmap, REGCTL2, mask, val); val 325 drivers/input/touchscreen/bcm_iproc_tsc.c u32 val; val 333 drivers/input/touchscreen/bcm_iproc_tsc.c val = TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK; val 334 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_update_bits(priv->regmap, INTERRUPT_MASK, val, 0); val 337 drivers/input/touchscreen/bcm_iproc_tsc.c val = TS_CONTROLLER_PWR_TS; val 338 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_update_bits(priv->regmap, REGCTL2, val, val); val 346 drivers/input/touchscreen/bcm_iproc_tsc.c u32 val; val 353 drivers/input/touchscreen/bcm_iproc_tsc.c if (of_property_read_u32(np, "scanning_period", &val) >= 0) { val 354 drivers/input/touchscreen/bcm_iproc_tsc.c if (val < 1 || val > 256) { val 356 drivers/input/touchscreen/bcm_iproc_tsc.c val); val 359 drivers/input/touchscreen/bcm_iproc_tsc.c priv->cfg_params.scanning_period = val; val 362 drivers/input/touchscreen/bcm_iproc_tsc.c if (of_property_read_u32(np, "debounce_timeout", &val) >= 0) { val 363 drivers/input/touchscreen/bcm_iproc_tsc.c if (val > 255) { val 365 drivers/input/touchscreen/bcm_iproc_tsc.c val); val 368 drivers/input/touchscreen/bcm_iproc_tsc.c priv->cfg_params.debounce_timeout = val; val 371 drivers/input/touchscreen/bcm_iproc_tsc.c if (of_property_read_u32(np, "settling_timeout", &val) >= 0) { val 372 drivers/input/touchscreen/bcm_iproc_tsc.c if (val > 11) { val 374 drivers/input/touchscreen/bcm_iproc_tsc.c val); val 377 drivers/input/touchscreen/bcm_iproc_tsc.c priv->cfg_params.settling_timeout = val; val 380 drivers/input/touchscreen/bcm_iproc_tsc.c if (of_property_read_u32(np, "touch_timeout", &val) >= 0) { val 381 drivers/input/touchscreen/bcm_iproc_tsc.c if (val > 255) { val 383 drivers/input/touchscreen/bcm_iproc_tsc.c val); val 386 drivers/input/touchscreen/bcm_iproc_tsc.c priv->cfg_params.touch_timeout = val; val 389 drivers/input/touchscreen/bcm_iproc_tsc.c if (of_property_read_u32(np, "average_data", &val) >= 0) { val 390 drivers/input/touchscreen/bcm_iproc_tsc.c if (val > 8) { val 391 drivers/input/touchscreen/bcm_iproc_tsc.c dev_err(dev, "average_data (%u) must be [0-8]\n", val); val 394 drivers/input/touchscreen/bcm_iproc_tsc.c priv->cfg_params.average_data = val; val 397 drivers/input/touchscreen/bcm_iproc_tsc.c if (of_property_read_u32(np, "fifo_threshold", &val) >= 0) { val 398 drivers/input/touchscreen/bcm_iproc_tsc.c if (val > 31) { val 400 drivers/input/touchscreen/bcm_iproc_tsc.c val); val 403 drivers/input/touchscreen/bcm_iproc_tsc.c priv->cfg_params.fifo_threshold = val; val 167 drivers/input/touchscreen/chipone_icn8505.c static int icn8505_write_reg(struct icn8505_data *icn8505, int reg, u8 val) val 170 drivers/input/touchscreen/chipone_icn8505.c ICN8505_REG_ADDR_WIDTH, &val, 1, false); val 187 drivers/input/touchscreen/chipone_icn8505.c static int icn8505_write_prog_reg(struct icn8505_data *icn8505, int reg, u8 val) val 190 drivers/input/touchscreen/chipone_icn8505.c ICN8505_PROG_REG_ADDR_WIDTH, &val, 1, false); val 56 drivers/input/touchscreen/colibri-vf50-ts.c int i, value = 0, val = 0; val 65 drivers/input/touchscreen/colibri-vf50-ts.c error = iio_read_channel_raw(channel, &val); val 71 drivers/input/touchscreen/colibri-vf50-ts.c value += val; val 371 drivers/input/touchscreen/edt-ft5x06.c int val; val 404 drivers/input/touchscreen/edt-ft5x06.c val = edt_ft5x06_register_read(tsdata, addr); val 405 drivers/input/touchscreen/edt-ft5x06.c if (val < 0) { val 406 drivers/input/touchscreen/edt-ft5x06.c error = val; val 413 drivers/input/touchscreen/edt-ft5x06.c val = *field; val 416 drivers/input/touchscreen/edt-ft5x06.c if (val != *field) { val 419 drivers/input/touchscreen/edt-ft5x06.c dattr->attr.name, val, *field); val 420 drivers/input/touchscreen/edt-ft5x06.c *field = val; val 423 drivers/input/touchscreen/edt-ft5x06.c count = scnprintf(buf, PAGE_SIZE, "%d\n", val); val 438 drivers/input/touchscreen/edt-ft5x06.c unsigned int val; val 449 drivers/input/touchscreen/edt-ft5x06.c error = kstrtouint(buf, 0, &val); val 453 drivers/input/touchscreen/edt-ft5x06.c if (val < attr->limit_low || val > attr->limit_high) { val 479 drivers/input/touchscreen/edt-ft5x06.c error = edt_ft5x06_register_write(tsdata, addr, val); val 487 drivers/input/touchscreen/edt-ft5x06.c *field = val; val 685 drivers/input/touchscreen/edt-ft5x06.c int val, i, error; val 710 drivers/input/touchscreen/edt-ft5x06.c val = edt_ft5x06_register_read(tsdata, 0x08); val 711 drivers/input/touchscreen/edt-ft5x06.c if (val < 1) val 715 drivers/input/touchscreen/edt-ft5x06.c if (val < 0) { val 716 drivers/input/touchscreen/edt-ft5x06.c error = val; val 921 drivers/input/touchscreen/edt-ft5x06.c u32 val; val 924 drivers/input/touchscreen/edt-ft5x06.c error = device_property_read_u32(dev, "threshold", &val); val 926 drivers/input/touchscreen/edt-ft5x06.c edt_ft5x06_register_write(tsdata, reg_addr->reg_threshold, val); val 927 drivers/input/touchscreen/edt-ft5x06.c tsdata->threshold = val; val 930 drivers/input/touchscreen/edt-ft5x06.c error = device_property_read_u32(dev, "gain", &val); val 932 drivers/input/touchscreen/edt-ft5x06.c edt_ft5x06_register_write(tsdata, reg_addr->reg_gain, val); val 933 drivers/input/touchscreen/edt-ft5x06.c tsdata->gain = val; val 936 drivers/input/touchscreen/edt-ft5x06.c error = device_property_read_u32(dev, "offset", &val); val 938 drivers/input/touchscreen/edt-ft5x06.c edt_ft5x06_register_write(tsdata, reg_addr->reg_offset, val); val 939 drivers/input/touchscreen/edt-ft5x06.c tsdata->offset = val; val 942 drivers/input/touchscreen/edt-ft5x06.c error = device_property_read_u32(dev, "offset-x", &val); val 944 drivers/input/touchscreen/edt-ft5x06.c edt_ft5x06_register_write(tsdata, reg_addr->reg_offset_x, val); val 945 drivers/input/touchscreen/edt-ft5x06.c tsdata->offset_x = val; val 948 drivers/input/touchscreen/edt-ft5x06.c error = device_property_read_u32(dev, "offset-y", &val); val 950 drivers/input/touchscreen/edt-ft5x06.c edt_ft5x06_register_write(tsdata, reg_addr->reg_offset_y, val); val 951 drivers/input/touchscreen/edt-ft5x06.c tsdata->offset_y = val; val 1031 drivers/input/touchscreen/elants_i2c.c unsigned int val; val 1034 drivers/input/touchscreen/elants_i2c.c val = *field; val 1037 drivers/input/touchscreen/elants_i2c.c val = *(u16 *)field; val 1041 drivers/input/touchscreen/elants_i2c.c return sprintf(buf, "%0*x\n", fmt_size, val); val 248 drivers/input/touchscreen/fsl-imx25-tcq.c unsigned int val = MX25_ADCQ_FIFO_DATA(sample_buf[i]); val 252 drivers/input/touchscreen/fsl-imx25-tcq.c touch_pre = val; val 255 drivers/input/touchscreen/fsl-imx25-tcq.c x_pos = val; val 258 drivers/input/touchscreen/fsl-imx25-tcq.c y_pos = val; val 261 drivers/input/touchscreen/fsl-imx25-tcq.c touch_post = val; val 239 drivers/input/touchscreen/hideep.c static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val) val 252 drivers/input/touchscreen/hideep.c *val = be32_to_cpu(data); val 256 drivers/input/touchscreen/hideep.c static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val) val 258 drivers/input/touchscreen/hideep.c __be32 data = cpu_to_be32(val); val 265 drivers/input/touchscreen/hideep.c addr, val, error); val 409 drivers/input/touchscreen/hideep.c u32 val; val 433 drivers/input/touchscreen/hideep.c val = be32_to_cpu(ucode[0]); val 434 drivers/input/touchscreen/hideep.c SET_PIO_SIG(HIDEEP_WRONLY | addr, val); val 439 drivers/input/touchscreen/hideep.c val = be32_to_cpu(ucode[xfer_count - 1]); val 440 drivers/input/touchscreen/hideep.c SET_PIO_SIG(124, val); val 763 drivers/input/touchscreen/hideep.c __le16 val[2]; val 766 drivers/input/touchscreen/hideep.c error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val)); val 770 drivers/input/touchscreen/hideep.c ts->prop.max_x = le16_to_cpup(val); val 771 drivers/input/touchscreen/hideep.c ts->prop.max_y = le16_to_cpup(val + 1); val 130 drivers/input/touchscreen/iqs5xx.c u16 reg, void *val, u16 len) val 145 drivers/input/touchscreen/iqs5xx.c .buf = (u8 *)val, val 171 drivers/input/touchscreen/iqs5xx.c static int iqs5xx_read_word(struct i2c_client *client, u16 reg, u16 *val) val 180 drivers/input/touchscreen/iqs5xx.c *val = be16_to_cpu(val_buf); val 185 drivers/input/touchscreen/iqs5xx.c static int iqs5xx_read_byte(struct i2c_client *client, u16 reg, u8 *val) val 187 drivers/input/touchscreen/iqs5xx.c return iqs5xx_read_burst(client, reg, val, sizeof(*val)); val 191 drivers/input/touchscreen/iqs5xx.c u16 reg, const void *val, u16 len) val 201 drivers/input/touchscreen/iqs5xx.c memcpy(mbuf + sizeof(reg), val, len); val 225 drivers/input/touchscreen/iqs5xx.c static int iqs5xx_write_word(struct i2c_client *client, u16 reg, u16 val) val 227 drivers/input/touchscreen/iqs5xx.c __be16 val_buf = cpu_to_be16(val); val 232 drivers/input/touchscreen/iqs5xx.c static int iqs5xx_write_byte(struct i2c_client *client, u16 reg, u8 val) val 234 drivers/input/touchscreen/iqs5xx.c return iqs5xx_write_burst(client, reg, &val, sizeof(val)); val 489 drivers/input/touchscreen/iqs5xx.c u8 val; val 511 drivers/input/touchscreen/iqs5xx.c error = iqs5xx_read_byte(client, IQS5XX_TOTAL_RX, &val); val 514 drivers/input/touchscreen/iqs5xx.c max_x_hw = (val - 1) * IQS5XX_NUM_POINTS; val 516 drivers/input/touchscreen/iqs5xx.c error = iqs5xx_read_byte(client, IQS5XX_TOTAL_TX, &val); val 519 drivers/input/touchscreen/iqs5xx.c max_y_hw = (val - 1) * IQS5XX_NUM_POINTS; val 521 drivers/input/touchscreen/iqs5xx.c error = iqs5xx_read_byte(client, IQS5XX_XY_CFG0, &val); val 525 drivers/input/touchscreen/iqs5xx.c if (val & IQS5XX_SWITCH_XY_AXIS) val 529 drivers/input/touchscreen/iqs5xx.c val ^= IQS5XX_SWITCH_XY_AXIS; val 532 drivers/input/touchscreen/iqs5xx.c val ^= prop.swap_x_y ? IQS5XX_FLIP_Y : IQS5XX_FLIP_X; val 535 drivers/input/touchscreen/iqs5xx.c val ^= prop.swap_x_y ? IQS5XX_FLIP_X : IQS5XX_FLIP_Y; val 537 drivers/input/touchscreen/iqs5xx.c error = iqs5xx_write_byte(client, IQS5XX_XY_CFG0, val); val 606 drivers/input/touchscreen/iqs5xx.c u8 val; val 669 drivers/input/touchscreen/iqs5xx.c error = iqs5xx_read_byte(client, IQS5XX_SYS_CFG0, &val); val 673 drivers/input/touchscreen/iqs5xx.c val |= IQS5XX_SETUP_COMPLETE; val 674 drivers/input/touchscreen/iqs5xx.c val &= ~IQS5XX_SW_INPUT_EVENT; val 675 drivers/input/touchscreen/iqs5xx.c error = iqs5xx_write_byte(client, IQS5XX_SYS_CFG0, val); val 679 drivers/input/touchscreen/iqs5xx.c val = IQS5XX_TP_EVENT | IQS5XX_EVENT_MODE; val 680 drivers/input/touchscreen/iqs5xx.c error = iqs5xx_write_byte(client, IQS5XX_SYS_CFG1, val); val 61 drivers/input/touchscreen/lpc32xx_ts.c #define tsc_writel(dev, reg, val) \ val 62 drivers/input/touchscreen/lpc32xx_ts.c __raw_writel((val), (dev)->tsc_base + (reg)) val 84 drivers/input/touchscreen/mms114.c unsigned int len, u8 *val) val 104 drivers/input/touchscreen/mms114.c xfer[1].buf = val; val 119 drivers/input/touchscreen/mms114.c u8 val; val 125 drivers/input/touchscreen/mms114.c error = __mms114_read_reg(data, reg, 1, &val); val 126 drivers/input/touchscreen/mms114.c return error < 0 ? error : val; val 130 drivers/input/touchscreen/mms114.c unsigned int val) val 137 drivers/input/touchscreen/mms114.c buf[1] = val & 0xff; val 148 drivers/input/touchscreen/mms114.c data->cache_mode_control = val; val 230 drivers/input/touchscreen/mms114.c int val; val 232 drivers/input/touchscreen/mms114.c val = mms114_read_reg(data, MMS114_MODE_CONTROL); val 233 drivers/input/touchscreen/mms114.c if (val < 0) val 234 drivers/input/touchscreen/mms114.c return val; val 236 drivers/input/touchscreen/mms114.c val &= ~MMS114_OPERATION_MODE_MASK; val 240 drivers/input/touchscreen/mms114.c val |= MMS114_ACTIVE; val 242 drivers/input/touchscreen/mms114.c return mms114_write_reg(data, MMS114_MODE_CONTROL, val); val 283 drivers/input/touchscreen/mms114.c int val; val 298 drivers/input/touchscreen/mms114.c val = (props->max_x >> 8) & 0xf; val 299 drivers/input/touchscreen/mms114.c val |= ((props->max_y >> 8) & 0xf) << 4; val 300 drivers/input/touchscreen/mms114.c error = mms114_write_reg(data, MMS114_XY_RESOLUTION_H, val); val 304 drivers/input/touchscreen/mms114.c val = props->max_x & 0xff; val 305 drivers/input/touchscreen/mms114.c error = mms114_write_reg(data, MMS114_X_RESOLUTION, val); val 309 drivers/input/touchscreen/mms114.c val = props->max_x & 0xff; val 310 drivers/input/touchscreen/mms114.c error = mms114_write_reg(data, MMS114_Y_RESOLUTION, val); val 212 drivers/input/touchscreen/mxs-lradc-ts.c unsigned int num_samples, val; val 220 drivers/input/touchscreen/mxs-lradc-ts.c val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET; val 221 drivers/input/touchscreen/mxs-lradc-ts.c return val / num_samples; val 19 drivers/input/touchscreen/of_touchscreen.c u32 val; val 22 drivers/input/touchscreen/of_touchscreen.c error = device_property_read_u32(dev, property, &val); val 28 drivers/input/touchscreen/of_touchscreen.c *value = val; val 326 drivers/input/touchscreen/rohm_bu21023.c s32 val; val 454 drivers/input/touchscreen/rohm_bu21023.c val = i2c_smbus_read_byte_data(client, TOUCH_GESTURE); val 455 drivers/input/touchscreen/rohm_bu21023.c if (!(val & CALIBRATION_MASK)) { val 458 drivers/input/touchscreen/rohm_bu21023.c } else if (val < 0) { val 459 drivers/input/touchscreen/rohm_bu21023.c error = val; val 465 drivers/input/touchscreen/rohm_bu21023.c val = i2c_smbus_read_byte_data(client, INT_STATUS); val 466 drivers/input/touchscreen/rohm_bu21023.c if (val == CALIBRATION_DONE) { val 469 drivers/input/touchscreen/rohm_bu21023.c } else if (val < 0) { val 470 drivers/input/touchscreen/rohm_bu21023.c error = val; val 744 drivers/input/touchscreen/rohm_bu21023.c unsigned int val; val 747 drivers/input/touchscreen/rohm_bu21023.c error = kstrtouint(buf, 0, &val); val 755 drivers/input/touchscreen/rohm_bu21023.c if (val) val 783 drivers/input/touchscreen/rohm_bu21023.c unsigned int val; val 786 drivers/input/touchscreen/rohm_bu21023.c error = kstrtouint(buf, 0, &val); val 794 drivers/input/touchscreen/rohm_bu21023.c if (val) val 822 drivers/input/touchscreen/rohm_bu21023.c unsigned int val; val 825 drivers/input/touchscreen/rohm_bu21023.c error = kstrtouint(buf, 0, &val); val 833 drivers/input/touchscreen/rohm_bu21023.c if (val) val 81 drivers/input/touchscreen/silead.c u32 val; val 304 drivers/input/touchscreen/silead.c (u8 *)&fw_data[i].val); val 261 drivers/input/touchscreen/stmpe-ts.c u32 val; val 264 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,sample-time", &val)) val 265 drivers/input/touchscreen/stmpe-ts.c ts->stmpe->sample_time = val; val 266 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,mod-12b", &val)) val 267 drivers/input/touchscreen/stmpe-ts.c ts->stmpe->mod_12b = val; val 268 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,ref-sel", &val)) val 269 drivers/input/touchscreen/stmpe-ts.c ts->stmpe->ref_sel = val; val 270 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,adc-freq", &val)) val 271 drivers/input/touchscreen/stmpe-ts.c ts->stmpe->adc_freq = val; val 272 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,ave-ctrl", &val)) val 273 drivers/input/touchscreen/stmpe-ts.c ts->ave_ctrl = val; val 274 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,touch-det-delay", &val)) val 275 drivers/input/touchscreen/stmpe-ts.c ts->touch_det_delay = val; val 276 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,settling", &val)) val 277 drivers/input/touchscreen/stmpe-ts.c ts->settling = val; val 278 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,fraction-z", &val)) val 279 drivers/input/touchscreen/stmpe-ts.c ts->fraction_z = val; val 280 drivers/input/touchscreen/stmpe-ts.c if (!of_property_read_u32(np, "st,i-drive", &val)) val 281 drivers/input/touchscreen/stmpe-ts.c ts->i_drive = val; val 1010 drivers/input/touchscreen/sur40.c sur40_set_irlevel(sur40, ctrl->val); val 1013 drivers/input/touchscreen/sur40.c value = (value & 0x0f) | (ctrl->val << 4); val 1017 drivers/input/touchscreen/sur40.c value = (value & 0xf0) | (ctrl->val); val 1021 drivers/input/touchscreen/sur40.c sur40_set_preprocessor(sur40, ctrl->val); val 69 drivers/input/touchscreen/ti_am335x_tsc.c unsigned int val) val 71 drivers/input/touchscreen/ti_am335x_tsc.c writel(val, tsc->mfd_tscadc->tscadc_base + reg); val 124 drivers/input/touchscreen/tps6507x-ts.c u8 val; val 136 drivers/input/touchscreen/tps6507x-ts.c ret = tps6507x_read_u8(tsc, TPS6507X_REG_INT, &val); val 140 drivers/input/touchscreen/tps6507x-ts.c while (val & TPS6507X_REG_TSC_INT) { val 142 drivers/input/touchscreen/tps6507x-ts.c ret = tps6507x_read_u8(tsc, TPS6507X_REG_INT, &val); val 33 drivers/input/touchscreen/tsc2007_core.c u16 val; val 45 drivers/input/touchscreen/tsc2007_core.c val = swab16(data) >> 4; val 47 drivers/input/touchscreen/tsc2007_core.c dev_dbg(&tsc->client->dev, "data: 0x%x, val: 0x%x\n", data, val); val 49 drivers/input/touchscreen/tsc2007_core.c return val; val 39 drivers/input/touchscreen/tsc2007_iio.c int *val, int *val2, long mask) val 56 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_xfer(tsc, READ_X); val 59 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_xfer(tsc, READ_Y); val 62 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_xfer(tsc, READ_Z1); val 65 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_xfer(tsc, READ_Z2); val 68 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_xfer(tsc, (ADC_ON_12BIT | TSC2007_MEASURE_AUX)); val 76 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_calculate_resistance(tsc, &tc); val 80 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_is_pen_down(tsc); val 83 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_xfer(tsc, val 87 drivers/input/touchscreen/tsc2007_iio.c *val = tsc2007_xfer(tsc, val 130 drivers/input/touchscreen/ucb1400_ts.c unsigned short val = ucb1400_reg_read(ucb->ac97, UCB_TS_CR); val 132 drivers/input/touchscreen/ucb1400_ts.c return val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW); val 216 drivers/input/touchscreen/wm9713.c u16 val; val 219 drivers/input/touchscreen/wm9713.c val = wm97xx_reg_read(wm, AC97_EXTENDED_MID); val 220 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, val & 0x7fff); val 227 drivers/input/touchscreen/wm9713.c val = wm97xx_reg_read(wm, AC97_EXTENDED_MID); val 228 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, val | 0x8000); val 326 drivers/input/touchscreen/wm9713.c u16 val = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); val 327 drivers/input/touchscreen/wm9713.c if (!(val & WM97XX_PEN_DOWN)) val 93 drivers/input/touchscreen/wm97xx-core.c void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val) val 97 drivers/input/touchscreen/wm97xx-core.c wm->dig[(reg - AC97_WM9713_DIG1) >> 1] = val; val 101 drivers/input/touchscreen/wm97xx-core.c wm->gpio[(reg - AC97_GPIO_CFG) >> 1] = val; val 105 drivers/input/touchscreen/wm97xx-core.c wm->misc = val; val 108 drivers/input/touchscreen/wm97xx-core.c wm->ac97->bus->ops->write(wm->ac97, reg, val); val 34 drivers/interconnect/qcom/smd-rpm.c int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val) val 39 drivers/interconnect/qcom/smd-rpm.c .value = cpu_to_le32(val), val 13 drivers/interconnect/qcom/smd-rpm.h int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); val 2795 drivers/iommu/amd_iommu.c struct iova *val; val 2803 drivers/iommu/amd_iommu.c val = reserve_iova(&reserved_iova_ranges, val 2805 drivers/iommu/amd_iommu.c if (!val) { val 2811 drivers/iommu/amd_iommu.c val = reserve_iova(&reserved_iova_ranges, val 2813 drivers/iommu/amd_iommu.c if (!val) { val 2831 drivers/iommu/amd_iommu.c val = reserve_iova(&reserved_iova_ranges, val 2834 drivers/iommu/amd_iommu.c if (!val) { val 3894 drivers/iommu/amd_iommu.c entry->hi.val = irte->hi.val; val 3895 drivers/iommu/amd_iommu.c entry->lo.val = irte->lo.val; val 3923 drivers/iommu/amd_iommu.c table->table[index] = irte->val; val 3960 drivers/iommu/amd_iommu.c irte->val = 0; val 3974 drivers/iommu/amd_iommu.c irte->lo.val = 0; val 3975 drivers/iommu/amd_iommu.c irte->hi.val = 0; val 4052 drivers/iommu/amd_iommu.c memset(&irte->lo.val, 0, sizeof(u64)); val 4053 drivers/iommu/amd_iommu.c memset(&irte->hi.val, 0, sizeof(u64)); val 4062 drivers/iommu/amd_iommu.c return irte->val != 0; val 4083 drivers/iommu/amd_iommu.c memset(&irte->lo.val, 0, sizeof(u64)); val 4084 drivers/iommu/amd_iommu.c memset(&irte->hi.val, 0, sizeof(u64)); val 4415 drivers/iommu/amd_iommu.c entry->lo.val = 0; val 4416 drivers/iommu/amd_iommu.c entry->hi.val = 0; val 4439 drivers/iommu/amd_iommu.c entry->lo.val = 0; val 4440 drivers/iommu/amd_iommu.c entry->hi.val = 0; val 302 drivers/iommu/amd_iommu_init.c u32 val; val 305 drivers/iommu/amd_iommu_init.c pci_read_config_dword(iommu->dev, 0xfc, &val); val 306 drivers/iommu/amd_iommu_init.c return val; val 309 drivers/iommu/amd_iommu_init.c static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) val 312 drivers/iommu/amd_iommu_init.c pci_write_config_dword(iommu->dev, 0xfc, val); val 318 drivers/iommu/amd_iommu_init.c u32 val; val 321 drivers/iommu/amd_iommu_init.c pci_read_config_dword(iommu->dev, 0xf4, &val); val 322 drivers/iommu/amd_iommu_init.c return val; val 325 drivers/iommu/amd_iommu_init.c static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) val 328 drivers/iommu/amd_iommu_init.c pci_write_config_dword(iommu->dev, 0xf4, val); val 1664 drivers/iommu/amd_iommu_init.c u64 val = 0xabcd, val2 = 0, save_reg = 0; val 1676 drivers/iommu/amd_iommu_init.c if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) || val 1678 drivers/iommu/amd_iommu_init.c (val != val2)) val 1687 drivers/iommu/amd_iommu_init.c val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); val 1688 drivers/iommu/amd_iommu_init.c iommu->max_banks = (u8) ((val >> 12) & 0x3f); val 1689 drivers/iommu/amd_iommu_init.c iommu->max_counters = (u8) ((val >> 7) & 0xf); val 1958 drivers/iommu/amd_iommu_init.c u64 val; val 1968 drivers/iommu/amd_iommu_init.c val = XT_INT_VEC(data & 0xFF) | val 1977 drivers/iommu/amd_iommu_init.c writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); val 1978 drivers/iommu/amd_iommu_init.c writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); val 1979 drivers/iommu/amd_iommu_init.c writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); val 3156 drivers/iommu/amd_iommu_init.c u64 val = *value & GENMASK_ULL(47, 0); val 3158 drivers/iommu/amd_iommu_init.c writel((u32)val, iommu->mmio_base + offset); val 3159 drivers/iommu/amd_iommu_init.c writel((val >> 32), iommu->mmio_base + offset + 4); val 802 drivers/iommu/amd_iommu_types.h u32 val; val 820 drivers/iommu/amd_iommu_types.h u64 val; val 852 drivers/iommu/amd_iommu_types.h u64 val; val 37 drivers/iommu/arm-smmu-impl.c int offset, u32 val) val 41 drivers/iommu/arm-smmu-impl.c writel_relaxed(val, arm_smmu_page(smmu, page) + offset); val 491 drivers/iommu/arm-smmu-v3.c u64 val; val 1008 drivers/iommu/arm-smmu-v3.c int val; val 1020 drivers/iommu/arm-smmu-v3.c val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); val 1021 drivers/iommu/arm-smmu-v3.c } while (atomic_cmpxchg_relaxed(&cmdq->lock, val, val + 1) != val); val 1170 drivers/iommu/arm-smmu-v3.c llq->val = READ_ONCE(cmdq->q.llq.val); val 1176 drivers/iommu/arm-smmu-v3.c llq->val = READ_ONCE(smmu->cmdq.q.llq.val); val 1223 drivers/iommu/arm-smmu-v3.c llq->val = READ_ONCE(smmu->cmdq.q.llq.val); val 1322 drivers/iommu/arm-smmu-v3.c llq.val = READ_ONCE(cmdq->q.llq.val); val 1337 drivers/iommu/arm-smmu-v3.c old = cmpxchg_relaxed(&cmdq->q.llq.val, llq.val, head.val); val 1338 drivers/iommu/arm-smmu-v3.c if (old == llq.val) val 1341 drivers/iommu/arm-smmu-v3.c llq.val = old; val 1449 drivers/iommu/arm-smmu-v3.c u64 val = 0; val 1452 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, T0SZ); val 1453 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, TG0); val 1454 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, IRGN0); val 1455 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, ORGN0); val 1456 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, SH0); val 1457 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, EPD0); val 1458 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, EPD1); val 1459 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, IPS); val 1461 drivers/iommu/arm-smmu-v3.c return val; val 1467 drivers/iommu/arm-smmu-v3.c u64 val; val 1473 drivers/iommu/arm-smmu-v3.c val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) | val 1483 drivers/iommu/arm-smmu-v3.c val |= CTXDESC_CD_0_S; val 1485 drivers/iommu/arm-smmu-v3.c cfg->cdptr[0] = cpu_to_le64(val); val 1487 drivers/iommu/arm-smmu-v3.c val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK; val 1488 drivers/iommu/arm-smmu-v3.c cfg->cdptr[1] = cpu_to_le64(val); val 1497 drivers/iommu/arm-smmu-v3.c u64 val = 0; val 1499 drivers/iommu/arm-smmu-v3.c val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span); val 1500 drivers/iommu/arm-smmu-v3.c val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK; val 1502 drivers/iommu/arm-smmu-v3.c *dst = cpu_to_le64(val); val 1538 drivers/iommu/arm-smmu-v3.c u64 val = le64_to_cpu(dst[0]); val 1570 drivers/iommu/arm-smmu-v3.c if (val & STRTAB_STE_0_V) { val 1571 drivers/iommu/arm-smmu-v3.c switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { val 1587 drivers/iommu/arm-smmu-v3.c val = STRTAB_STE_0_V; val 1592 drivers/iommu/arm-smmu-v3.c val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); val 1594 drivers/iommu/arm-smmu-v3.c val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); val 1596 drivers/iommu/arm-smmu-v3.c dst[0] = cpu_to_le64(val); val 1621 drivers/iommu/arm-smmu-v3.c val |= (s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | val 1638 drivers/iommu/arm-smmu-v3.c val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); val 1647 drivers/iommu/arm-smmu-v3.c WRITE_ONCE(dst[0], cpu_to_le64(val)); val 2968 drivers/iommu/arm-smmu-v3.c static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val, val 2973 drivers/iommu/arm-smmu-v3.c writel_relaxed(val, smmu->base + reg_off); val 2974 drivers/iommu/arm-smmu-v3.c return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, val 331 drivers/iommu/arm-smmu.h u32 val); val 334 drivers/iommu/arm-smmu.h u64 val); val 353 drivers/iommu/arm-smmu.h int offset, u32 val) val 356 drivers/iommu/arm-smmu.h smmu->impl->write_reg(smmu, page, offset, val); val 358 drivers/iommu/arm-smmu.h writel_relaxed(val, arm_smmu_page(smmu, page) + offset); val 369 drivers/iommu/arm-smmu.h int offset, u64 val) val 372 drivers/iommu/arm-smmu.h smmu->impl->write_reg64(smmu, page, offset, val); val 374 drivers/iommu/arm-smmu.h writeq_relaxed(val, arm_smmu_page(smmu, page) + offset); val 1423 drivers/iommu/dmar.c u64 val = virt_to_phys(qi->desc); val 1433 drivers/iommu/dmar.c val |= (1 << 11) | 1; val 1440 drivers/iommu/dmar.c dmar_writeq(iommu->reg + DMAR_IQA_REG, val); val 146 drivers/iommu/exynos-iommu.c #define MMU_MAJ_VER(val) ((val) >> 7) val 147 drivers/iommu/exynos-iommu.c #define MMU_MIN_VER(val) ((val) & 0x7F) val 724 drivers/iommu/exynos-iommu.c static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) val 728 drivers/iommu/exynos-iommu.c *ent = cpu_to_le32(val); val 189 drivers/iommu/fsl_pamu_domain.c u32 val) val 203 drivers/iommu/fsl_pamu_domain.c ret = pamu_update_paace_stash(liodn, i, val); val 448 drivers/iommu/fsl_pamu_domain.c static int update_domain_stash(struct fsl_dma_domain *dma_domain, u32 val) val 454 drivers/iommu/fsl_pamu_domain.c ret = update_liodn_stash(info->liodn, dma_domain, val); val 175 drivers/iommu/intel-iommu-debugfs.c tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2], val 176 drivers/iommu/intel-iommu-debugfs.c tbl_wlk->pasid_tbl_entry->val[1], val 177 drivers/iommu/intel-iommu-debugfs.c tbl_wlk->pasid_tbl_entry->val[0]); val 916 drivers/iommu/intel-iommu.c if (cmpxchg64(&pte->val, 0ULL, pteval)) val 1235 drivers/iommu/intel-iommu.c u32 val; val 1246 drivers/iommu/intel-iommu.c readl, (!(val & DMA_GSTS_WBFS)), val); val 1256 drivers/iommu/intel-iommu.c u64 val = 0; val 1261 drivers/iommu/intel-iommu.c val = DMA_CCMD_GLOBAL_INVL; val 1264 drivers/iommu/intel-iommu.c val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); val 1267 drivers/iommu/intel-iommu.c val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) val 1273 drivers/iommu/intel-iommu.c val |= DMA_CCMD_ICC; val 1276 drivers/iommu/intel-iommu.c dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); val 1280 drivers/iommu/intel-iommu.c dmar_readq, (!(val & DMA_CCMD_ICC)), val); val 1290 drivers/iommu/intel-iommu.c u64 val = 0, val_iva = 0; val 1296 drivers/iommu/intel-iommu.c val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; val 1299 drivers/iommu/intel-iommu.c val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); val 1302 drivers/iommu/intel-iommu.c val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); val 1316 drivers/iommu/intel-iommu.c val |= DMA_TLB_READ_DRAIN; val 1319 drivers/iommu/intel-iommu.c val |= DMA_TLB_WRITE_DRAIN; val 1325 drivers/iommu/intel-iommu.c dmar_writeq(iommu->reg + tlb_offset + 8, val); val 1329 drivers/iommu/intel-iommu.c dmar_readq, (!(val & DMA_TLB_IVT)), val); val 1334 drivers/iommu/intel-iommu.c if (DMA_TLB_IAIG(val) == 0) val 1336 drivers/iommu/intel-iommu.c if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) val 1339 drivers/iommu/intel-iommu.c (unsigned long long)DMA_TLB_IAIG(val)); val 2290 drivers/iommu/intel-iommu.c tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); val 3146 drivers/iommu/intel-iommu.c u64 val; val 3149 drivers/iommu/intel-iommu.c val = virt_to_phys(ctxt_tbls[idx]) | 1; val 3150 drivers/iommu/intel-iommu.c iommu->root_entry[bus].lo = val; val 3156 drivers/iommu/intel-iommu.c val = virt_to_phys(ctxt_tbls[idx + 1]) | 1; val 3157 drivers/iommu/intel-iommu.c iommu->root_entry[bus].hi = val; val 4650 drivers/iommu/intel-iommu.c unsigned long val, void *v) val 4656 drivers/iommu/intel-iommu.c switch (val) { val 251 drivers/iommu/intel-pasid.c WRITE_ONCE(dir[dir_index].val, val 264 drivers/iommu/intel-pasid.c WRITE_ONCE(pe->val[0], 0); val 265 drivers/iommu/intel-pasid.c WRITE_ONCE(pe->val[1], 0); val 266 drivers/iommu/intel-pasid.c WRITE_ONCE(pe->val[2], 0); val 267 drivers/iommu/intel-pasid.c WRITE_ONCE(pe->val[3], 0); val 268 drivers/iommu/intel-pasid.c WRITE_ONCE(pe->val[4], 0); val 269 drivers/iommu/intel-pasid.c WRITE_ONCE(pe->val[5], 0); val 270 drivers/iommu/intel-pasid.c WRITE_ONCE(pe->val[6], 0); val 271 drivers/iommu/intel-pasid.c WRITE_ONCE(pe->val[7], 0); val 300 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value); val 309 drivers/iommu/intel-pasid.c return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0)); val 319 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value); val 329 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2); val 339 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6); val 348 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[0], 1 << 1, 0); val 357 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[2], 1 << 0, 1); val 366 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[0], 1 << 0, 1); val 375 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[1], 1 << 23, value << 23); val 385 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value); val 395 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2); val 41 drivers/iommu/intel-pasid.h u64 val; val 45 drivers/iommu/intel-pasid.h u64 val[8]; val 59 drivers/iommu/intel-pasid.h return READ_ONCE(pde->val) & PASID_PTE_PRESENT; val 69 drivers/iommu/intel-pasid.h return phys_to_virt(READ_ONCE(pde->val) & PDE_PFN_MASK); val 75 drivers/iommu/intel-pasid.h return READ_ONCE(pte->val[0]) & PASID_PTE_PRESENT; val 113 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) val 723 drivers/iommu/msm_iommu.c int ret, par, val; val 773 drivers/iommu/msm_iommu.c ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val); val 778 drivers/iommu/msm_iommu.c iommu->ncb = val; val 14 drivers/iommu/msm_iommu_hw-8xxx.h #define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg))) val 16 drivers/iommu/msm_iommu_hw-8xxx.h #define SET_CTX_REG(reg, base, ctx, val) \ val 17 drivers/iommu/msm_iommu_hw-8xxx.h writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT))) val 138 drivers/iommu/omap-iommu.c u32 val, mask; val 144 drivers/iommu/omap-iommu.c val = enable ? mask : 0; val 145 drivers/iommu/omap-iommu.c regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val); val 264 drivers/iommu/omap-iommu.c u32 val; val 266 drivers/iommu/omap-iommu.c val = iommu_read_reg(obj, MMU_LOCK); val 268 drivers/iommu/omap-iommu.c l->base = MMU_LOCK_BASE(val); val 269 drivers/iommu/omap-iommu.c l->vict = MMU_LOCK_VICT(val); val 274 drivers/iommu/omap-iommu.c u32 val; val 276 drivers/iommu/omap-iommu.c val = (l->base << MMU_LOCK_BASE_SHIFT); val 277 drivers/iommu/omap-iommu.c val |= (l->vict << MMU_LOCK_VICT_SHIFT); val 279 drivers/iommu/omap-iommu.c iommu_write_reg(obj, val, MMU_LOCK); val 261 drivers/iommu/omap-iommu.h static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) val 263 drivers/iommu/omap-iommu.h __raw_writel(val, obj->regbase + offs); val 93 drivers/iommu/qcom_iommu.c iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val) val 95 drivers/iommu/qcom_iommu.c writel_relaxed(val, ctx->base + reg); val 99 drivers/iommu/qcom_iommu.c iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val) val 101 drivers/iommu/qcom_iommu.c writeq_relaxed(val, ctx->base + reg); val 123 drivers/iommu/qcom_iommu.c unsigned int val, ret; val 127 drivers/iommu/qcom_iommu.c ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val, val 128 drivers/iommu/qcom_iommu.c (val & 0x1) == 0, 0, 5000000); val 352 drivers/iommu/rockchip-iommu.c bool val; val 363 drivers/iommu/rockchip-iommu.c ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, val 364 drivers/iommu/rockchip-iommu.c val, RK_MMU_POLL_PERIOD_US, val 377 drivers/iommu/rockchip-iommu.c bool val; val 384 drivers/iommu/rockchip-iommu.c ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, val 385 drivers/iommu/rockchip-iommu.c !val, RK_MMU_POLL_PERIOD_US, val 398 drivers/iommu/rockchip-iommu.c bool val; val 405 drivers/iommu/rockchip-iommu.c ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, val 406 drivers/iommu/rockchip-iommu.c val, RK_MMU_POLL_PERIOD_US, val 419 drivers/iommu/rockchip-iommu.c bool val; val 426 drivers/iommu/rockchip-iommu.c ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, val 427 drivers/iommu/rockchip-iommu.c !val, RK_MMU_POLL_PERIOD_US, val 441 drivers/iommu/rockchip-iommu.c bool val; val 462 drivers/iommu/rockchip-iommu.c ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val, val 463 drivers/iommu/rockchip-iommu.c val, RK_MMU_FORCE_RESET_TIMEOUT_US, val 639 drivers/iommu/tegra-smmu.c u32 *pte, dma_addr_t pte_dma, u32 val) val 644 drivers/iommu/tegra-smmu.c *pte = val; val 48 drivers/irqchip/irq-atmel-aic-common.c int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val) val 77 drivers/irqchip/irq-atmel-aic-common.c *val &= ~AT91_AIC_SRCTYPE; val 78 drivers/irqchip/irq-atmel-aic-common.c *val |= aic_type; val 83 drivers/irqchip/irq-atmel-aic-common.c void aic_common_set_priority(int priority, unsigned *val) val 85 drivers/irqchip/irq-atmel-aic-common.c *val &= ~AT91_AIC_PRIOR; val 86 drivers/irqchip/irq-atmel-aic-common.c *val |= priority; val 20 drivers/irqchip/irq-atmel-aic-common.h int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val); val 22 drivers/irqchip/irq-atmel-aic-common.h void aic_common_set_priority(int priority, unsigned *val); val 106 drivers/irqchip/irq-bcm7038-l1.c static inline void l1_writel(u32 val, void __iomem *reg) val 109 drivers/irqchip/irq-bcm7038-l1.c iowrite32be(val, reg); val 111 drivers/irqchip/irq-bcm7038-l1.c writel(val, reg); val 59 drivers/irqchip/irq-gic-common.c u32 val, oldval; val 68 drivers/irqchip/irq-gic-common.c val = oldval = readl_relaxed(base + confoff); val 70 drivers/irqchip/irq-gic-common.c val &= ~confmask; val 72 drivers/irqchip/irq-gic-common.c val |= confmask; val 75 drivers/irqchip/irq-gic-common.c if (val == oldval) { val 88 drivers/irqchip/irq-gic-common.c writel_relaxed(val, base + confoff); val 89 drivers/irqchip/irq-gic-common.c if (readl_relaxed(base + confoff) != val) val 77 drivers/irqchip/irq-gic-v3-its.c u64 val; val 322 drivers/irqchip/irq-gic-v3-its.c static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) val 326 drivers/irqchip/irq-gic-v3-its.c *raw_cmd |= (val << l) & mask; val 1694 drivers/irqchip/irq-gic-v3-its.c u64 val; val 1696 drivers/irqchip/irq-gic-v3-its.c val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); val 1697 drivers/irqchip/irq-gic-v3-its.c lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1; val 1699 drivers/irqchip/irq-gic-v3-its.c gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); val 1746 drivers/irqchip/irq-gic-v3-its.c u64 val) val 1750 drivers/irqchip/irq-gic-v3-its.c gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); val 1751 drivers/irqchip/irq-gic-v3-its.c baser->val = its_read_baser(its, baser); val 1758 drivers/irqchip/irq-gic-v3-its.c u64 val = its_read_baser(its, baser); val 1759 drivers/irqchip/irq-gic-v3-its.c u64 esz = GITS_BASER_ENTRY_SIZE(val); val 1760 drivers/irqchip/irq-gic-v3-its.c u64 type = GITS_BASER_TYPE(val); val 1798 drivers/irqchip/irq-gic-v3-its.c val = (baser_phys | val 1806 drivers/irqchip/irq-gic-v3-its.c val |= indirect ? GITS_BASER_INDIRECT : 0x0; val 1810 drivers/irqchip/irq-gic-v3-its.c val |= GITS_BASER_PAGE_SIZE_4K; val 1813 drivers/irqchip/irq-gic-v3-its.c val |= GITS_BASER_PAGE_SIZE_16K; val 1816 drivers/irqchip/irq-gic-v3-its.c val |= GITS_BASER_PAGE_SIZE_64K; val 1820 drivers/irqchip/irq-gic-v3-its.c its_write_baser(its, baser, val); val 1821 drivers/irqchip/irq-gic-v3-its.c tmp = baser->val; val 1823 drivers/irqchip/irq-gic-v3-its.c if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { val 1839 drivers/irqchip/irq-gic-v3-its.c if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { val 1858 drivers/irqchip/irq-gic-v3-its.c if (val != tmp) { val 1861 drivers/irqchip/irq-gic-v3-its.c val, tmp); val 1888 drivers/irqchip/irq-gic-v3-its.c u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; val 1898 drivers/irqchip/irq-gic-v3-its.c its_write_baser(its, baser, val | GITS_BASER_INDIRECT); val 1899 drivers/irqchip/irq-gic-v3-its.c indirect = !!(baser->val & GITS_BASER_INDIRECT); val 1961 drivers/irqchip/irq-gic-v3-its.c u64 val = its_read_baser(its, baser); val 1962 drivers/irqchip/irq-gic-v3-its.c u64 type = GITS_BASER_TYPE(val); val 1991 drivers/irqchip/irq-gic-v3-its.c cache = baser->val & GITS_BASER_CACHEABILITY_MASK; val 1992 drivers/irqchip/irq-gic-v3-its.c shr = baser->val & GITS_BASER_SHAREABILITY_MASK; val 2040 drivers/irqchip/irq-gic-v3-its.c u64 val; val 2043 drivers/irqchip/irq-gic-v3-its.c val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); val 2044 drivers/irqchip/irq-gic-v3-its.c addr = val & GENMASK_ULL(51, 12); val 2051 drivers/irqchip/irq-gic-v3-its.c u64 val; val 2058 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR); val 2059 drivers/irqchip/irq-gic-v3-its.c if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) { val 2093 drivers/irqchip/irq-gic-v3-its.c u64 val; val 2095 drivers/irqchip/irq-gic-v3-its.c val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); val 2096 drivers/irqchip/irq-gic-v3-its.c val &= ~GICR_VPENDBASER_Valid; val 2097 drivers/irqchip/irq-gic-v3-its.c gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); val 2100 drivers/irqchip/irq-gic-v3-its.c val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); val 2101 drivers/irqchip/irq-gic-v3-its.c clean = !(val & GICR_VPENDBASER_Dirty); val 2109 drivers/irqchip/irq-gic-v3-its.c return val; val 2117 drivers/irqchip/irq-gic-v3-its.c u64 val, tmp; val 2122 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(rbase + GICR_CTLR); val 2124 drivers/irqchip/irq-gic-v3-its.c (val & GICR_CTLR_ENABLE_LPIS)) { val 2149 drivers/irqchip/irq-gic-v3-its.c val = (gic_rdists->prop_table_pa | val 2154 drivers/irqchip/irq-gic-v3-its.c gicr_write_propbaser(val, rbase + GICR_PROPBASER); val 2157 drivers/irqchip/irq-gic-v3-its.c if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { val 2164 drivers/irqchip/irq-gic-v3-its.c val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | val 2166 drivers/irqchip/irq-gic-v3-its.c val |= GICR_PROPBASER_nC; val 2167 drivers/irqchip/irq-gic-v3-its.c gicr_write_propbaser(val, rbase + GICR_PROPBASER); val 2174 drivers/irqchip/irq-gic-v3-its.c val = (page_to_phys(pend_page) | val 2178 drivers/irqchip/irq-gic-v3-its.c gicr_write_pendbaser(val, rbase + GICR_PENDBASER); val 2186 drivers/irqchip/irq-gic-v3-its.c val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | val 2188 drivers/irqchip/irq-gic-v3-its.c val |= GICR_PENDBASER_nC; val 2189 drivers/irqchip/irq-gic-v3-its.c gicr_write_pendbaser(val, rbase + GICR_PENDBASER); val 2193 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(rbase + GICR_CTLR); val 2194 drivers/irqchip/irq-gic-v3-its.c val |= GICR_CTLR_ENABLE_LPIS; val 2195 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(val, rbase + GICR_CTLR); val 2207 drivers/irqchip/irq-gic-v3-its.c val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; val 2209 drivers/irqchip/irq-gic-v3-its.c smp_processor_id(), val); val 2210 drivers/irqchip/irq-gic-v3-its.c gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); val 2217 drivers/irqchip/irq-gic-v3-its.c val = its_clear_vpend_valid(vlpi_base); val 2218 drivers/irqchip/irq-gic-v3-its.c WARN_ON(val & GICR_VPENDBASER_Dirty); val 2306 drivers/irqchip/irq-gic-v3-its.c if (GITS_BASER_TYPE(its->tables[i].val) == type) val 2321 drivers/irqchip/irq-gic-v3-its.c esz = GITS_BASER_ENTRY_SIZE(baser->val); val 2322 drivers/irqchip/irq-gic-v3-its.c if (!(baser->val & GITS_BASER_INDIRECT)) val 2340 drivers/irqchip/irq-gic-v3-its.c if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) val 2346 drivers/irqchip/irq-gic-v3-its.c if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) val 2821 drivers/irqchip/irq-gic-v3-its.c u64 val; val 2824 drivers/irqchip/irq-gic-v3-its.c val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & val 2826 drivers/irqchip/irq-gic-v3-its.c val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; val 2827 drivers/irqchip/irq-gic-v3-its.c val |= GICR_VPROPBASER_RaWb; val 2828 drivers/irqchip/irq-gic-v3-its.c val |= GICR_VPROPBASER_InnerShareable; val 2829 drivers/irqchip/irq-gic-v3-its.c gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); val 2831 drivers/irqchip/irq-gic-v3-its.c val = virt_to_phys(page_address(vpe->vpt_page)) & val 2833 drivers/irqchip/irq-gic-v3-its.c val |= GICR_VPENDBASER_RaWaWb; val 2834 drivers/irqchip/irq-gic-v3-its.c val |= GICR_VPENDBASER_NonShareable; val 2844 drivers/irqchip/irq-gic-v3-its.c val |= GICR_VPENDBASER_PendingLast; val 2845 drivers/irqchip/irq-gic-v3-its.c val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; val 2846 drivers/irqchip/irq-gic-v3-its.c val |= GICR_VPENDBASER_Valid; val 2847 drivers/irqchip/irq-gic-v3-its.c gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); val 2853 drivers/irqchip/irq-gic-v3-its.c u64 val; val 2855 drivers/irqchip/irq-gic-v3-its.c val = its_clear_vpend_valid(vlpi_base); val 2857 drivers/irqchip/irq-gic-v3-its.c if (unlikely(val & GICR_VPENDBASER_Dirty)) { val 2862 drivers/irqchip/irq-gic-v3-its.c vpe->idai = !!(val & GICR_VPENDBASER_IDAI); val 2863 drivers/irqchip/irq-gic-v3-its.c vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); val 3190 drivers/irqchip/irq-gic-v3-its.c u32 val; val 3192 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(base + GITS_CTLR); val 3198 drivers/irqchip/irq-gic-v3-its.c if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) val 3202 drivers/irqchip/irq-gic-v3-its.c val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe); val 3203 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(val, base + GITS_CTLR); val 3207 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(base + GITS_CTLR); val 3208 drivers/irqchip/irq-gic-v3-its.c if (val & GITS_CTLR_QUIESCENT) val 3441 drivers/irqchip/irq-gic-v3-its.c if (!(baser->val & GITS_BASER_VALID)) val 3444 drivers/irqchip/irq-gic-v3-its.c its_write_baser(its, baser, baser->val); val 3574 drivers/irqchip/irq-gic-v3-its.c u32 val, ctlr; val 3585 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; val 3586 drivers/irqchip/irq-gic-v3-its.c if (val != 0x30 && val != 0x40) { val 3721 drivers/irqchip/irq-gic-v3-its.c u64 val; val 3728 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(rbase + GICR_CTLR); val 3729 drivers/irqchip/irq-gic-v3-its.c if (!(val & GICR_CTLR_ENABLE_LPIS)) val 3751 drivers/irqchip/irq-gic-v3-its.c val &= ~GICR_CTLR_ENABLE_LPIS; val 3752 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(val, rbase + GICR_CTLR); val 207 drivers/irqchip/irq-gic-v3.c u32 val; val 214 drivers/irqchip/irq-gic-v3.c val = readl_relaxed(rbase + GICR_WAKER); val 217 drivers/irqchip/irq-gic-v3.c val &= ~GICR_WAKER_ProcessorSleep; val 219 drivers/irqchip/irq-gic-v3.c val |= GICR_WAKER_ProcessorSleep; val 220 drivers/irqchip/irq-gic-v3.c writel_relaxed(val, rbase + GICR_WAKER); val 223 drivers/irqchip/irq-gic-v3.c val = readl_relaxed(rbase + GICR_WAKER); val 224 drivers/irqchip/irq-gic-v3.c if (!(val & GICR_WAKER_ProcessorSleep)) val 229 drivers/irqchip/irq-gic-v3.c val = readl_relaxed(rbase + GICR_WAKER); val 230 drivers/irqchip/irq-gic-v3.c if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) val 361 drivers/irqchip/irq-gic-v3.c enum irqchip_irq_state which, bool val) val 370 drivers/irqchip/irq-gic-v3.c reg = val ? GICD_ISPENDR : GICD_ICPENDR; val 374 drivers/irqchip/irq-gic-v3.c reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; val 378 drivers/irqchip/irq-gic-v3.c reg = val ? GICD_ICENABLER : GICD_ISENABLER; val 390 drivers/irqchip/irq-gic-v3.c enum irqchip_irq_state which, bool *val) val 397 drivers/irqchip/irq-gic-v3.c *val = gic_peek_irq(d, GICD_ISPENDR); val 401 drivers/irqchip/irq-gic-v3.c *val = gic_peek_irq(d, GICD_ISACTIVER); val 405 drivers/irqchip/irq-gic-v3.c *val = !gic_peek_irq(d, GICD_ISENABLER); val 688 drivers/irqchip/irq-gic-v3.c u32 val; val 705 drivers/irqchip/irq-gic-v3.c val = gic_read_pmr(); val 709 drivers/irqchip/irq-gic-v3.c return val != 0; val 1082 drivers/irqchip/irq-gic-v3.c u64 val; val 1084 drivers/irqchip/irq-gic-v3.c val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | val 1091 drivers/irqchip/irq-gic-v3.c pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); val 1092 drivers/irqchip/irq-gic-v3.c gic_write_sgi1r(val); val 1135 drivers/irqchip/irq-gic-v3.c u64 val; val 1155 drivers/irqchip/irq-gic-v3.c val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); val 1157 drivers/irqchip/irq-gic-v3.c gic_write_irouter(val, reg); val 242 drivers/irqchip/irq-gic.c enum irqchip_irq_state which, bool val) val 248 drivers/irqchip/irq-gic.c reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; val 252 drivers/irqchip/irq-gic.c reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; val 256 drivers/irqchip/irq-gic.c reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; val 268 drivers/irqchip/irq-gic.c enum irqchip_irq_state which, bool *val) val 272 drivers/irqchip/irq-gic.c *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); val 276 drivers/irqchip/irq-gic.c *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); val 280 drivers/irqchip/irq-gic.c *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); val 334 drivers/irqchip/irq-gic.c u32 val, mask, bit; val 348 drivers/irqchip/irq-gic.c val = readl_relaxed(reg) & ~mask; val 349 drivers/irqchip/irq-gic.c writel_relaxed(val | bit, reg); val 463 drivers/irqchip/irq-gic.c u32 val = readl_relaxed(base + GIC_CPU_IDENT); val 464 drivers/irqchip/irq-gic.c return (val & 0xff0fff) == 0x02043B; val 557 drivers/irqchip/irq-gic.c u32 val = 0; val 563 drivers/irqchip/irq-gic.c val = readl(cpu_base + GIC_CPU_CTRL); val 564 drivers/irqchip/irq-gic.c val &= ~GICC_ENABLE; val 565 drivers/irqchip/irq-gic.c writel_relaxed(val, cpu_base + GIC_CPU_CTRL); val 888 drivers/irqchip/irq-gic.c u32 val, cur_target_mask, active_mask; val 912 drivers/irqchip/irq-gic.c val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); val 913 drivers/irqchip/irq-gic.c active_mask = val & cur_target_mask; val 915 drivers/irqchip/irq-gic.c val &= ~active_mask; val 916 drivers/irqchip/irq-gic.c val |= ror32(active_mask, ror_val); val 917 drivers/irqchip/irq-gic.c writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); val 935 drivers/irqchip/irq-gic.c val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); val 936 drivers/irqchip/irq-gic.c if (!val) val 938 drivers/irqchip/irq-gic.c writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); val 940 drivers/irqchip/irq-gic.c if (val & 0xff) val 943 drivers/irqchip/irq-gic.c val >>= 8; val 152 drivers/irqchip/irq-hip04.c u32 val, mask, bit; val 166 drivers/irqchip/irq-hip04.c val = readl_relaxed(reg) & ~mask; val 167 drivers/irqchip/irq-hip04.c writel_relaxed(val | bit, reg); val 305 drivers/irqchip/irq-imgpdc.c u32 val; val 333 drivers/irqchip/irq-imgpdc.c ret = of_property_read_u32(node, "num-perips", &val); val 338 drivers/irqchip/irq-imgpdc.c if (val > SYS0_HWIRQ) { val 339 drivers/irqchip/irq-imgpdc.c dev_err(&pdev->dev, "num-perips (%u) out of range\n", val); val 342 drivers/irqchip/irq-imgpdc.c priv->nr_perips = val; val 345 drivers/irqchip/irq-imgpdc.c ret = of_property_read_u32(node, "num-syswakes", &val); val 350 drivers/irqchip/irq-imgpdc.c if (val > SYS0_HWIRQ) { val 351 drivers/irqchip/irq-imgpdc.c dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val); val 354 drivers/irqchip/irq-imgpdc.c priv->nr_syswakes = val; val 78 drivers/irqchip/irq-imx-gpcv2.c u32 mask, val; val 82 drivers/irqchip/irq-imx-gpcv2.c val = cd->wakeup_sources[idx]; val 84 drivers/irqchip/irq-imx-gpcv2.c cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask); val 99 drivers/irqchip/irq-imx-gpcv2.c u32 val; val 103 drivers/irqchip/irq-imx-gpcv2.c val = readl_relaxed(reg); val 104 drivers/irqchip/irq-imx-gpcv2.c val &= ~BIT(d->hwirq % 32); val 105 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(val, reg); val 115 drivers/irqchip/irq-imx-gpcv2.c u32 val; val 119 drivers/irqchip/irq-imx-gpcv2.c val = readl_relaxed(reg); val 120 drivers/irqchip/irq-imx-gpcv2.c val |= BIT(d->hwirq % 32); val 121 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(val, reg); val 50 drivers/irqchip/irq-imx-irqsteer.c u32 val; val 53 drivers/irqchip/irq-imx-irqsteer.c val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); val 54 drivers/irqchip/irq-imx-irqsteer.c val |= BIT(d->hwirq % 32); val 55 drivers/irqchip/irq-imx-irqsteer.c writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); val 64 drivers/irqchip/irq-imx-irqsteer.c u32 val; val 67 drivers/irqchip/irq-imx-irqsteer.c val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); val 68 drivers/irqchip/irq-imx-irqsteer.c val &= ~BIT(d->hwirq % 32); val 69 drivers/irqchip/irq-imx-irqsteer.c writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); val 76 drivers/irqchip/irq-ixp4xx.c u32 val; val 79 drivers/irqchip/irq-ixp4xx.c val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2); val 80 drivers/irqchip/irq-ixp4xx.c val &= ~BIT(d->hwirq - 32); val 81 drivers/irqchip/irq-ixp4xx.c __raw_writel(val, ixi->irqbase + IXP4XX_ICMR2); val 83 drivers/irqchip/irq-ixp4xx.c val = __raw_readl(ixi->irqbase + IXP4XX_ICMR); val 84 drivers/irqchip/irq-ixp4xx.c val &= ~BIT(d->hwirq); val 85 drivers/irqchip/irq-ixp4xx.c __raw_writel(val, ixi->irqbase + IXP4XX_ICMR); val 96 drivers/irqchip/irq-ixp4xx.c u32 val; val 99 drivers/irqchip/irq-ixp4xx.c val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2); val 100 drivers/irqchip/irq-ixp4xx.c val |= BIT(d->hwirq - 32); val 101 drivers/irqchip/irq-ixp4xx.c __raw_writel(val, ixi->irqbase + IXP4XX_ICMR2); val 103 drivers/irqchip/irq-ixp4xx.c val = __raw_readl(ixi->irqbase + IXP4XX_ICMR); val 104 drivers/irqchip/irq-ixp4xx.c val |= BIT(d->hwirq); val 105 drivers/irqchip/irq-ixp4xx.c __raw_writel(val, ixi->irqbase + IXP4XX_ICMR); val 48 drivers/irqchip/irq-keystone.c u32 val = 0; val 50 drivers/irqchip/irq-keystone.c ret = regmap_read(kirq->devctrl_regs, kirq->devctrl_offset, &val); val 53 drivers/irqchip/irq-keystone.c return val; val 40 drivers/irqchip/irq-lpc32xx.c u32 reg, u32 val) val 42 drivers/irqchip/irq-lpc32xx.c writel_relaxed(val, ic->base + reg); val 48 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); val 50 drivers/irqchip/irq-lpc32xx.c val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) & ~mask; val 51 drivers/irqchip/irq-lpc32xx.c lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val); val 57 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); val 59 drivers/irqchip/irq-lpc32xx.c val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) | mask; val 60 drivers/irqchip/irq-lpc32xx.c lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val); val 74 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); val 101 drivers/irqchip/irq-lpc32xx.c val = lpc32xx_ic_read(ic, LPC32XX_INTC_POL); val 103 drivers/irqchip/irq-lpc32xx.c val |= mask; val 105 drivers/irqchip/irq-lpc32xx.c val &= ~mask; val 106 drivers/irqchip/irq-lpc32xx.c lpc32xx_ic_write(ic, LPC32XX_INTC_POL, val); val 108 drivers/irqchip/irq-lpc32xx.c val = lpc32xx_ic_read(ic, LPC32XX_INTC_TYPE); val 110 drivers/irqchip/irq-lpc32xx.c val |= mask; val 113 drivers/irqchip/irq-lpc32xx.c val &= ~mask; val 116 drivers/irqchip/irq-lpc32xx.c lpc32xx_ic_write(ic, LPC32XX_INTC_TYPE, val); val 196 drivers/irqchip/irq-ls-scfg-msi.c unsigned long val; val 201 drivers/irqchip/irq-ls-scfg-msi.c val = ioread32be(msir->reg); val 206 drivers/irqchip/irq-ls-scfg-msi.c for_each_set_bit_from(pos, &val, size) { val 119 drivers/irqchip/irq-mbigen.c u32 mask, addr, val; val 126 drivers/irqchip/irq-mbigen.c val = readl_relaxed(base + addr); val 129 drivers/irqchip/irq-mbigen.c val |= mask; val 131 drivers/irqchip/irq-mbigen.c val &= ~mask; val 133 drivers/irqchip/irq-mbigen.c writel_relaxed(val, base + addr); val 151 drivers/irqchip/irq-mbigen.c u32 val; val 157 drivers/irqchip/irq-mbigen.c val = readl_relaxed(base); val 159 drivers/irqchip/irq-mbigen.c val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); val 160 drivers/irqchip/irq-mbigen.c val |= (msg->data << IRQ_EVENT_ID_SHIFT); val 165 drivers/irqchip/irq-mbigen.c writel_relaxed(val, base); val 93 drivers/irqchip/irq-meson-gpio.c unsigned int reg, u32 mask, u32 val) val 99 drivers/irqchip/irq-meson-gpio.c tmp |= val; val 174 drivers/irqchip/irq-meson-gpio.c u32 val = 0; val 196 drivers/irqchip/irq-meson-gpio.c val |= REG_BOTH_EDGE(idx); val 199 drivers/irqchip/irq-meson-gpio.c val |= REG_EDGE_POL_EDGE(idx); val 202 drivers/irqchip/irq-meson-gpio.c val |= REG_EDGE_POL_LOW(idx); val 208 drivers/irqchip/irq-meson-gpio.c REG_EDGE_POL_MASK(idx), val); val 29 drivers/irqchip/irq-mscc-ocelot.c u32 val; val 32 drivers/irqchip/irq-mscc-ocelot.c val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) | val 34 drivers/irqchip/irq-mscc-ocelot.c if (!(val & mask)) val 72 drivers/irqchip/irq-omap-intc.c static void intc_writel(u32 reg, u32 val) val 74 drivers/irqchip/irq-omap-intc.c writel_relaxed(val, omap_irq_base + reg); val 55 drivers/irqchip/irq-partition-percpu.c bool val) val 63 drivers/irqchip/irq-partition-percpu.c return chip->irq_set_irqchip_state(data, which, val); val 70 drivers/irqchip/irq-partition-percpu.c bool *val) val 78 drivers/irqchip/irq-partition-percpu.c return chip->irq_get_irqchip_state(data, which, val); val 51 drivers/irqchip/irq-sni-exiu.c u32 val; val 53 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); val 54 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EIMASK); val 61 drivers/irqchip/irq-sni-exiu.c u32 val; val 63 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); val 64 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EIMASK); val 71 drivers/irqchip/irq-sni-exiu.c u32 val; val 76 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); val 77 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EIMASK); val 84 drivers/irqchip/irq-sni-exiu.c u32 val; val 86 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EILVL); val 88 drivers/irqchip/irq-sni-exiu.c val |= BIT(d->hwirq); val 90 drivers/irqchip/irq-sni-exiu.c val &= ~BIT(d->hwirq); val 91 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EILVL); val 93 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIEDG); val 95 drivers/irqchip/irq-sni-exiu.c val &= ~BIT(d->hwirq); val 97 drivers/irqchip/irq-sni-exiu.c val |= BIT(d->hwirq); val 98 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EIEDG); val 438 drivers/irqchip/irq-stm32-exti.c u32 val; val 440 drivers/irqchip/irq-stm32-exti.c val = readl_relaxed(base + reg); val 441 drivers/irqchip/irq-stm32-exti.c val |= BIT(d->hwirq % IRQS_PER_BANK); val 442 drivers/irqchip/irq-stm32-exti.c writel_relaxed(val, base + reg); val 444 drivers/irqchip/irq-stm32-exti.c return val; val 451 drivers/irqchip/irq-stm32-exti.c u32 val; val 453 drivers/irqchip/irq-stm32-exti.c val = readl_relaxed(base + reg); val 454 drivers/irqchip/irq-stm32-exti.c val &= ~BIT(d->hwirq % IRQS_PER_BANK); val 455 drivers/irqchip/irq-stm32-exti.c writel_relaxed(val, base + reg); val 457 drivers/irqchip/irq-stm32-exti.c return val; val 64 drivers/irqchip/irq-sun4i.c u32 val; val 66 drivers/irqchip/irq-sun4i.c val = readl(irq_ic_data->irq_base + val 68 drivers/irqchip/irq-sun4i.c writel(val & ~(1 << irq_off), val 77 drivers/irqchip/irq-sun4i.c u32 val; val 79 drivers/irqchip/irq-sun4i.c val = readl(irq_ic_data->irq_base + val 81 drivers/irqchip/irq-sun4i.c writel(val | (1 << irq_off), val 89 drivers/irqchip/irq-sunxi-nmi.c u32 val) val 91 drivers/irqchip/irq-sunxi-nmi.c irq_reg_writel(gc, val, off); val 50 drivers/irqchip/irq-tango.c static inline void intc_writel(struct tangox_irq_chip *chip, int reg, u32 val) val 52 drivers/irqchip/irq-tango.c writel_relaxed(val, chip->base + reg); val 32 drivers/irqchip/irq-tb10x.c u32 val) val 34 drivers/irqchip/irq-tb10x.c irq_reg_writel(gc, val, reg); val 111 drivers/irqchip/irq-ti-sci-inta.c unsigned long val; val 119 drivers/irqchip/irq-ti-sci-inta.c val = readq_relaxed(inta->base + vint_desc->vint_id * 0x1000 + val 122 drivers/irqchip/irq-ti-sci-inta.c for_each_set_bit(bit, &val, MAX_EVENTS_PER_VINT) { val 32 drivers/irqchip/irq-uniphier-aidet.c unsigned int reg, u32 mask, u32 val) val 40 drivers/irqchip/irq-uniphier-aidet.c tmp |= mask & val; val 46 drivers/irqchip/irq-uniphier-aidet.c unsigned long index, unsigned int val) val 54 drivers/irqchip/irq-uniphier-aidet.c uniphier_aidet_reg_update(priv, reg, mask, val ? mask : 0); val 60 drivers/irqchip/irq-uniphier-aidet.c unsigned int val; val 66 drivers/irqchip/irq-uniphier-aidet.c val = 0; val 69 drivers/irqchip/irq-uniphier-aidet.c val = 1; val 73 drivers/irqchip/irq-uniphier-aidet.c val = 1; val 80 drivers/irqchip/irq-uniphier-aidet.c uniphier_aidet_detconf_update(priv, data->hwirq, val); val 40 drivers/irqchip/qcom-pdc.c static void pdc_reg_write(int reg, u32 i, u32 val) val 42 drivers/irqchip/qcom-pdc.c writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); val 61 drivers/irqchip/spear-shirq.c u32 val, shift = d->irq - shirq->virq_base + shirq->offset; val 65 drivers/irqchip/spear-shirq.c val = readl(reg) & ~(0x1 << shift); val 66 drivers/irqchip/spear-shirq.c writel(val, reg); val 73 drivers/irqchip/spear-shirq.c u32 val, shift = d->irq - shirq->virq_base + shirq->offset; val 77 drivers/irqchip/spear-shirq.c val = readl(reg) | (0x1 << shift); val 78 drivers/irqchip/spear-shirq.c writel(val, reg); val 255 drivers/isdn/capi/kcapi.c notify_handler(struct notifier_block *nb, unsigned long val, void *v) val 259 drivers/isdn/capi/kcapi.c switch (val) { val 146 drivers/isdn/hardware/mISDN/avmfritz.c set_debug(const char *val, const struct kernel_param *kp) val 151 drivers/isdn/hardware/mISDN/avmfritz.c ret = param_set_uint(val, kp); val 394 drivers/isdn/hardware/mISDN/avmfritz.c u32 val, addr; val 421 drivers/isdn/hardware/mISDN/avmfritz.c val = le32_to_cpu(inl(addr)); val 423 drivers/isdn/hardware/mISDN/avmfritz.c put_unaligned(val, ptr); val 443 drivers/isdn/hardware/mISDN/avmfritz.c u32 *ptr, val, addr; val 493 drivers/isdn/hardware/mISDN/avmfritz.c val = get_unaligned(ptr); val 494 drivers/isdn/hardware/mISDN/avmfritz.c outl(cpu_to_le32(val), addr); val 623 drivers/isdn/hardware/mISDN/avmfritz.c u8 val; val 637 drivers/isdn/hardware/mISDN/avmfritz.c val = ReadISAC_V1(fc, ISAC_ISTA); val 638 drivers/isdn/hardware/mISDN/avmfritz.c mISDNisac_irq(&fc->isac, val); val 650 drivers/isdn/hardware/mISDN/avmfritz.c u8 val; val 666 drivers/isdn/hardware/mISDN/avmfritz.c val = ReadISAC_V2(fc, ISACX_ISTA); val 667 drivers/isdn/hardware/mISDN/avmfritz.c mISDNisac_irq(&fc->isac, val); val 734 drivers/isdn/hardware/mISDN/avmfritz.c u32 val; val 736 drivers/isdn/hardware/mISDN/avmfritz.c val = read_status(fc, 1); val 737 drivers/isdn/hardware/mISDN/avmfritz.c pr_debug("%s: HDLC 1 STA %x\n", fc->name, val); val 738 drivers/isdn/hardware/mISDN/avmfritz.c val = read_status(fc, 2); val 739 drivers/isdn/hardware/mISDN/avmfritz.c pr_debug("%s: HDLC 2 STA %x\n", fc->name, val); val 955 drivers/isdn/hardware/mISDN/avmfritz.c u32 val, ver; val 964 drivers/isdn/hardware/mISDN/avmfritz.c val = inl(fc->addr); val 968 drivers/isdn/hardware/mISDN/avmfritz.c pr_notice("%s: PCI stat %#x\n", fc->name, val); val 970 drivers/isdn/hardware/mISDN/avmfritz.c val & 0xff, (val >> 8) & 0xff); val 977 drivers/isdn/hardware/mISDN/avmfritz.c val = inl(fc->addr); val 980 drivers/isdn/hardware/mISDN/avmfritz.c pr_notice("%s: PCI V2 stat %#x\n", fc->name, val); val 982 drivers/isdn/hardware/mISDN/avmfritz.c val & 0xff, (val >> 8) & 0xff); val 152 drivers/isdn/hardware/mISDN/hfc_multi.h u_char val, const char *function, int line); val 154 drivers/isdn/hardware/mISDN/hfc_multi.h u_char val, const char *function, int line); val 169 drivers/isdn/hardware/mISDN/hfc_multi.h u_char val); val 171 drivers/isdn/hardware/mISDN/hfc_multi.h u_char val); val 19 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h HFC_outb_embsd(struct hfc_multi *hc, u_char reg, u_char val, val 22 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h HFC_outb_embsd(struct hfc_multi *hc, u_char reg, u_char val) val 28 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h writeb(val, hc->xhfc_memdata); val 241 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_outb(hc, reg, val) \ val 242 drivers/isdn/hardware/mISDN/hfcmulti.c (hc->HFC_outb(hc, reg, val, __func__, __LINE__)) val 243 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_outb_nodebug(hc, reg, val) \ val 244 drivers/isdn/hardware/mISDN/hfcmulti.c (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__)) val 258 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val)) val 259 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val)) val 275 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, val 278 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) val 281 drivers/isdn/hardware/mISDN/hfcmulti.c writeb(val, hc->pci_membase + reg); val 315 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, val 318 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) val 322 drivers/isdn/hardware/mISDN/hfcmulti.c outb(val, hc->pci_iobase); val 358 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, val 372 drivers/isdn/hardware/mISDN/hfcmulti.c bits[7] = '0' + (!!(val & 1)); val 373 drivers/isdn/hardware/mISDN/hfcmulti.c bits[6] = '0' + (!!(val & 2)); val 374 drivers/isdn/hardware/mISDN/hfcmulti.c bits[5] = '0' + (!!(val & 4)); val 375 drivers/isdn/hardware/mISDN/hfcmulti.c bits[4] = '0' + (!!(val & 8)); val 376 drivers/isdn/hardware/mISDN/hfcmulti.c bits[3] = '0' + (!!(val & 16)); val 377 drivers/isdn/hardware/mISDN/hfcmulti.c bits[2] = '0' + (!!(val & 32)); val 378 drivers/isdn/hardware/mISDN/hfcmulti.c bits[1] = '0' + (!!(val & 64)); val 379 drivers/isdn/hardware/mISDN/hfcmulti.c bits[0] = '0' + (!!(val & 128)); val 382 drivers/isdn/hardware/mISDN/hfcmulti.c hc->id, reg, regname, val, bits, function, line); val 383 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_nodebug(hc, reg, val); val 389 drivers/isdn/hardware/mISDN/hfcmulti.c u_char val = HFC_inb_nodebug(hc, reg); val 402 drivers/isdn/hardware/mISDN/hfcmulti.c bits[7] = '0' + (!!(val & 1)); val 403 drivers/isdn/hardware/mISDN/hfcmulti.c bits[6] = '0' + (!!(val & 2)); val 404 drivers/isdn/hardware/mISDN/hfcmulti.c bits[5] = '0' + (!!(val & 4)); val 405 drivers/isdn/hardware/mISDN/hfcmulti.c bits[4] = '0' + (!!(val & 8)); val 406 drivers/isdn/hardware/mISDN/hfcmulti.c bits[3] = '0' + (!!(val & 16)); val 407 drivers/isdn/hardware/mISDN/hfcmulti.c bits[2] = '0' + (!!(val & 32)); val 408 drivers/isdn/hardware/mISDN/hfcmulti.c bits[1] = '0' + (!!(val & 64)); val 409 drivers/isdn/hardware/mISDN/hfcmulti.c bits[0] = '0' + (!!(val & 128)); val 412 drivers/isdn/hardware/mISDN/hfcmulti.c hc->id, reg, regname, val, bits, function, line); val 413 drivers/isdn/hardware/mISDN/hfcmulti.c return val; val 419 drivers/isdn/hardware/mISDN/hfcmulti.c u_short val = HFC_inw_nodebug(hc, reg); val 434 drivers/isdn/hardware/mISDN/hfcmulti.c hc->id, reg, regname, val, function, line); val 435 drivers/isdn/hardware/mISDN/hfcmulti.c return val; val 631 drivers/isdn/hardware/mISDN/hfcmulti.c cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) val 636 drivers/isdn/hardware/mISDN/hfcmulti.c writepcibridge(hc, 1, val); val 1110 drivers/isdn/hardware/mISDN/hfcmulti.c u_long flags, val, val2 = 0, rev; val 1126 drivers/isdn/hardware/mISDN/hfcmulti.c val = HFC_inb(hc, R_CHIP_ID); val 1127 drivers/isdn/hardware/mISDN/hfcmulti.c if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe && val 1128 drivers/isdn/hardware/mISDN/hfcmulti.c (val >> 1) != 0x31) { val 1129 drivers/isdn/hardware/mISDN/hfcmulti.c printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val); val 1136 drivers/isdn/hardware/mISDN/hfcmulti.c val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ? val 1360 drivers/isdn/hardware/mISDN/hfcmulti.c val = HFC_inb(hc, R_F0_CNTL); val 1361 drivers/isdn/hardware/mISDN/hfcmulti.c val += HFC_inb(hc, R_F0_CNTH) << 8; val 1364 drivers/isdn/hardware/mISDN/hfcmulti.c "HFC_multi F0_CNT %ld after reset\n", val); val 1375 drivers/isdn/hardware/mISDN/hfcmulti.c if (val2 >= val + 8) { /* 1 ms */ val 1433 drivers/isdn/hardware/mISDN/hfcmulti.c if (val2 >= val + 8) { /* 1 ms */ val 194 drivers/isdn/hardware/mISDN/hfcpci.c u_char val; val 198 drivers/isdn/hardware/mISDN/hfcpci.c val = Read_hfc(hc, HFCPCI_CHIP_ID); val 199 drivers/isdn/hardware/mISDN/hfcpci.c printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val); val 206 drivers/isdn/hardware/mISDN/hfcpci.c val = Read_hfc(hc, HFCPCI_STATUS); val 207 drivers/isdn/hardware/mISDN/hfcpci.c printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val); val 214 drivers/isdn/hardware/mISDN/hfcpci.c val = Read_hfc(hc, HFCPCI_STATUS); val 215 drivers/isdn/hardware/mISDN/hfcpci.c printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val); val 219 drivers/isdn/hardware/mISDN/hfcpci.c val = Read_hfc(hc, HFCPCI_STATUS); val 220 drivers/isdn/hardware/mISDN/hfcpci.c if (!(val & 2)) val 223 drivers/isdn/hardware/mISDN/hfcpci.c printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt); val 248 drivers/isdn/hardware/mISDN/hfcpci.c val = Read_hfc(hc, HFCPCI_INT_S1); val 283 drivers/isdn/hardware/mISDN/hfcpci.c val = Read_hfc(hc, HFCPCI_INT_S2); val 1146 drivers/isdn/hardware/mISDN/hfcpci.c u_char val, stat; val 1155 drivers/isdn/hardware/mISDN/hfcpci.c val = Read_hfc(hc, HFCPCI_INT_S1); val 1158 drivers/isdn/hardware/mISDN/hfcpci.c "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val); val 1167 drivers/isdn/hardware/mISDN/hfcpci.c printk(KERN_DEBUG "HFC-PCI irq %x\n", val); val 1168 drivers/isdn/hardware/mISDN/hfcpci.c val &= hc->hw.int_m1; val 1169 drivers/isdn/hardware/mISDN/hfcpci.c if (val & 0x40) { /* state machine irq */ val 1176 drivers/isdn/hardware/mISDN/hfcpci.c val &= ~0x40; val 1178 drivers/isdn/hardware/mISDN/hfcpci.c if (val & 0x80) { /* timer irq */ val 1183 drivers/isdn/hardware/mISDN/hfcpci.c val &= ~0x80; val 1186 drivers/isdn/hardware/mISDN/hfcpci.c if (val & 0x08) { /* B1 rx */ val 1193 drivers/isdn/hardware/mISDN/hfcpci.c if (val & 0x10) { /* B2 rx */ val 1200 drivers/isdn/hardware/mISDN/hfcpci.c if (val & 0x01) { /* B1 tx */ val 1207 drivers/isdn/hardware/mISDN/hfcpci.c if (val & 0x02) { /* B2 tx */ val 1214 drivers/isdn/hardware/mISDN/hfcpci.c if (val & 0x20) /* D rx */ val 1216 drivers/isdn/hardware/mISDN/hfcpci.c if (val & 0x04) { /* D tx */ val 76 drivers/isdn/hardware/mISDN/hfcsusb.c static int write_reg(struct hfcsusb *hw, __u8 reg, __u8 val) val 82 drivers/isdn/hardware/mISDN/hfcsusb.c hw->name, __func__, reg, val); val 91 drivers/isdn/hardware/mISDN/hfcsusb.c buf->reg_val = val; val 30 drivers/isdn/hardware/mISDN/iohelper.h static void Write##name##_IO(void *p, u8 off, u8 val) { \ val 32 drivers/isdn/hardware/mISDN/iohelper.h outb(val, hw->ap.port + off); \ val 49 drivers/isdn/hardware/mISDN/iohelper.h static void Write##name##_IND(void *p, u8 off, u8 val) { \ val 52 drivers/isdn/hardware/mISDN/iohelper.h outb(val, hw->ap.port); \ val 70 drivers/isdn/hardware/mISDN/iohelper.h static void Write##name##_MIO(void *p, u8 off, u8 val) { \ val 72 drivers/isdn/hardware/mISDN/iohelper.h writeb(val, ((typ *)hw->adr) + off); \ val 232 drivers/isdn/hardware/mISDN/mISDNinfineon.c set_debug(const char *val, const struct kernel_param *kp) val 237 drivers/isdn/hardware/mISDN/mISDNinfineon.c ret = param_set_uint(val, kp); val 268 drivers/isdn/hardware/mISDN/mISDNinfineon.c u8 val; val 271 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL); val 272 drivers/isdn/hardware/mISDN/mISDNinfineon.c if (!(val & DIVA_IRQ_BIT)) { /* for us or shared ? */ val 286 drivers/isdn/hardware/mISDN/mISDNinfineon.c u8 val; val 289 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = readb(hw->cfg.p); val 290 drivers/isdn/hardware/mISDN/mISDNinfineon.c if (!(val & PITA_INT0_STATUS)) { /* for us or shared ? */ val 305 drivers/isdn/hardware/mISDN/mISDNinfineon.c u8 val; val 308 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS); val 309 drivers/isdn/hardware/mISDN/mISDNinfineon.c if (val & TIGER_IRQ_BIT) { /* for us or shared ? */ val 323 drivers/isdn/hardware/mISDN/mISDNinfineon.c u8 val; val 326 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR); val 327 drivers/isdn/hardware/mISDN/mISDNinfineon.c if (!(val & ELSA_IRQ_MASK)) { val 341 drivers/isdn/hardware/mISDN/mISDNinfineon.c u32 val; val 344 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); val 345 drivers/isdn/hardware/mISDN/mISDNinfineon.c if (!(val & NICCY_IRQ_BIT)) { /* for us or shared ? */ val 349 drivers/isdn/hardware/mISDN/mISDNinfineon.c outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); val 372 drivers/isdn/hardware/mISDN/mISDNinfineon.c u8 val; val 375 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = hw->ipac.read_reg(hw, IPAC_ISTA); val 376 drivers/isdn/hardware/mISDN/mISDNinfineon.c if (!(val & 0x3f)) { val 390 drivers/isdn/hardware/mISDN/mISDNinfineon.c u32 val; val 408 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); val 409 drivers/isdn/hardware/mISDN/mISDNinfineon.c val |= NICCY_IRQ_ENABLE; val 410 drivers/isdn/hardware/mISDN/mISDNinfineon.c outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); val 434 drivers/isdn/hardware/mISDN/mISDNinfineon.c u32 val; val 452 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); val 453 drivers/isdn/hardware/mISDN/mISDNinfineon.c val &= NICCY_IRQ_DISABLE; val 454 drivers/isdn/hardware/mISDN/mISDNinfineon.c outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); val 485 drivers/isdn/hardware/mISDN/mISDNinfineon.c u32 val; val 543 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = inl((u32)hw->cfg.start + GAZEL_CNTRL); val 544 drivers/isdn/hardware/mISDN/mISDNinfineon.c val |= (GAZEL_RESET_9050 + GAZEL_RESET); val 545 drivers/isdn/hardware/mISDN/mISDNinfineon.c outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); val 546 drivers/isdn/hardware/mISDN/mISDNinfineon.c val &= ~(GAZEL_RESET_9050 + GAZEL_RESET); val 548 drivers/isdn/hardware/mISDN/mISDNinfineon.c outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); val 555 drivers/isdn/hardware/mISDN/mISDNinfineon.c val = inl((u32)hw->cfg.start + GAZEL_CNTRL); val 556 drivers/isdn/hardware/mISDN/mISDNinfineon.c val |= (GAZEL_RESET_9050 + GAZEL_RESET); val 557 drivers/isdn/hardware/mISDN/mISDNinfineon.c outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); val 558 drivers/isdn/hardware/mISDN/mISDNinfineon.c val &= ~(GAZEL_RESET_9050 + GAZEL_RESET); val 560 drivers/isdn/hardware/mISDN/mISDNinfineon.c outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); val 176 drivers/isdn/hardware/mISDN/mISDNipac.c u8 val, count; val 178 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_RSTA); val 179 drivers/isdn/hardware/mISDN/mISDNipac.c if ((val & 0x70) != 0x20) { val 180 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x40) { val 186 drivers/isdn/hardware/mISDN/mISDNipac.c if (!(val & 0x20)) { val 242 drivers/isdn/hardware/mISDN/mISDNipac.c u8 val; val 245 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_MOSR); val 246 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC MOSR %02x\n", isac->name, val); val 248 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x08) { val 278 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x80) { val 306 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x04) { val 324 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x40) { val 342 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x02) { val 344 drivers/isdn/hardware/mISDN/mISDNipac.c (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) { val 375 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x20) { val 377 drivers/isdn/hardware/mISDN/mISDNipac.c (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) { val 408 drivers/isdn/hardware/mISDN/mISDNipac.c val = 0; /* dummy to avoid warning */ val 414 drivers/isdn/hardware/mISDN/mISDNipac.c u8 val; val 416 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_CIR0); val 417 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val); val 418 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 2) { val 420 drivers/isdn/hardware/mISDN/mISDNipac.c isac->state, (val >> 2) & 0xf); val 421 drivers/isdn/hardware/mISDN/mISDNipac.c isac->state = (val >> 2) & 0xf; val 424 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 1) { val 425 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_CIR1); val 426 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val); val 433 drivers/isdn/hardware/mISDN/mISDNipac.c u8 val; val 435 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISACX_CIR0); val 436 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val); val 437 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX_CIR0_CIC0) { val 439 drivers/isdn/hardware/mISDN/mISDNipac.c isac->state, val >> 4); val 440 drivers/isdn/hardware/mISDN/mISDNipac.c isac->state = val >> 4; val 449 drivers/isdn/hardware/mISDN/mISDNipac.c u8 val; val 451 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISACX_RSTAD); val 452 drivers/isdn/hardware/mISDN/mISDNipac.c if ((val & (ISACX_RSTAD_VFR | val 457 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val); val 459 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX_RSTAD_CRC) val 482 drivers/isdn/hardware/mISDN/mISDNipac.c mISDNisac_irq(struct isac_hw *isac, u8 val) val 484 drivers/isdn/hardware/mISDN/mISDNipac.c if (unlikely(!val)) val 486 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC interrupt %02x\n", isac->name, val); val 488 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX__CIC) val 490 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX__ICD) { val 491 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISACX_ISTAD); val 492 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISTAD %02x\n", isac->name, val); val 493 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX_D_XDU) { val 500 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX_D_XMR) { val 507 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX_D_XPR) val 509 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX_D_RFO) { val 513 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX_D_RME) val 515 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & ISACX_D_RPF) val 519 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x80) /* RME */ val 521 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x40) /* RPF */ val 523 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x10) /* XPR */ val 525 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x04) /* CISQ */ val 527 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x20) /* RSC - never */ val 529 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x02) /* SIN - never */ val 531 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x01) { /* EXI */ val 532 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_EXIR); val 533 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC EXIR %02x\n", isac->name, val); val 534 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x80) /* XMR */ val 536 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x40) { /* XDU */ val 543 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x04) /* MOS */ val 773 drivers/isdn/hardware/mISDN/mISDNipac.c u8 val; val 788 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISACX_STARD); val 789 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISACX STARD %x\n", isac->name, val); val 790 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISACX_ISTAD); val 791 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISACX ISTAD %x\n", isac->name, val); val 792 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISACX_ISTA); val 793 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISACX ISTA %x\n", isac->name, val); val 801 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISACX_ID); val 804 drivers/isdn/hardware/mISDN/mISDNipac.c isac->name, val & 0x3f); val 805 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISACX_CIR0); val 806 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val); val 807 drivers/isdn/hardware/mISDN/mISDNipac.c isac->state = val >> 4; val 814 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_STAR); val 815 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC STAR %x\n", isac->name, val); val 816 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_MODE); val 817 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC MODE %x\n", isac->name, val); val 818 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_ADF2); val 819 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC ADF2 %x\n", isac->name, val); val 820 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_ISTA); val 821 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC ISTA %x\n", isac->name, val); val 822 drivers/isdn/hardware/mISDN/mISDNipac.c if (val & 0x01) { val 823 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_EXIR); val 824 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC EXIR %x\n", isac->name, val); val 826 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_RBCH); val 829 drivers/isdn/hardware/mISDN/mISDNipac.c val, ISACVer[(val >> 5) & 3]); val 830 drivers/isdn/hardware/mISDN/mISDNipac.c isac->type |= ((val >> 5) & 3); val 846 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadISAC(isac, ISAC_CIR0); val 847 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: ISAC CIR0 %x\n", isac->name, val); val 848 drivers/isdn/hardware/mISDN/mISDNipac.c isac->state = (val >> 2) & 0xf; val 1432 drivers/isdn/hardware/mISDN/mISDNipac.c u8 val; val 1440 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadHSCX(hx, HSCX_VSTR); val 1441 drivers/isdn/hardware/mISDN/mISDNipac.c pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val); val 1444 drivers/isdn/hardware/mISDN/mISDNipac.c HSCXVer[val & 0x0f]); val 1455 drivers/isdn/hardware/mISDN/mISDNipac.c u8 val; val 1460 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadIPAC(ipac, IPAC_ID); val 1465 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadIPAC(ipac, IPAC_CONF); val 1468 drivers/isdn/hardware/mISDN/mISDNipac.c val, ipac->conf); val 1470 drivers/isdn/hardware/mISDN/mISDNipac.c val = ReadIPAC(ipac, IPAC_ID); val 1472 drivers/isdn/hardware/mISDN/mISDNipac.c pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val); val 41 drivers/isdn/hardware/mISDN/mISDNisar.c u8 val = isar->read_reg(isar->hw, ISAR_HIA); val 43 drivers/isdn/hardware/mISDN/mISDNisar.c while ((val & 1) && t) { val 46 drivers/isdn/hardware/mISDN/mISDNisar.c val = isar->read_reg(isar->hw, ISAR_HIA); val 178 drivers/isdn/hardware/mISDN/mISDNisar.c u16 left, val, *sp = (u16 *)buf; val 253 drivers/isdn/hardware/mISDN/mISDNisar.c val = le16_to_cpu(*sp++); val 254 drivers/isdn/hardware/mISDN/mISDNisar.c *mp++ = val >> 8; val 255 drivers/isdn/hardware/mISDN/mISDNisar.c *mp++ = val & 0xFF; val 1473 drivers/isdn/hardware/mISDN/mISDNisar.c u32 id, *val; val 1507 drivers/isdn/hardware/mISDN/mISDNisar.c val = (u32 *)skb->data; val 1509 drivers/isdn/hardware/mISDN/mISDNisar.c hh->id, *val); val 1510 drivers/isdn/hardware/mISDN/mISDNisar.c if ((hh->id == 0) && ((*val & ~DTMF_TONE_MASK) == val 1513 drivers/isdn/hardware/mISDN/mISDNisar.c char tt = *val & DTMF_TONE_MASK; val 1533 drivers/isdn/hardware/mISDN/mISDNisar.c if (faxmodulation[id] == *val) val 1538 drivers/isdn/hardware/mISDN/mISDNisar.c isar_pump_cmd(ich, hh->id, *val); val 101 drivers/isdn/hardware/mISDN/netjet.c set_debug(const char *val, const struct kernel_param *kp) val 106 drivers/isdn/hardware/mISDN/netjet.c ret = param_set_uint(val, kp); val 178 drivers/isdn/hardware/mISDN/netjet.c u32 mask = 0xff, val; val 188 drivers/isdn/hardware/mISDN/netjet.c val = card->send.start[idx]; val 189 drivers/isdn/hardware/mISDN/netjet.c val &= mask; val 190 drivers/isdn/hardware/mISDN/netjet.c val |= fill; val 191 drivers/isdn/hardware/mISDN/netjet.c card->send.start[idx++] = val; val 367 drivers/isdn/hardware/mISDN/netjet.c u32 val; val 393 drivers/isdn/hardware/mISDN/netjet.c val = card->recv.start[idx++]; val 395 drivers/isdn/hardware/mISDN/netjet.c val >>= 8; val 398 drivers/isdn/hardware/mISDN/netjet.c p[i] = val & 0xff; val 678 drivers/isdn/hardware/mISDN/netjet.c u8 val, s1val, s0val; val 691 drivers/isdn/hardware/mISDN/netjet.c val = ReadISAC_nj(card, ISAC_ISTA); val 692 drivers/isdn/hardware/mISDN/netjet.c if (val) val 693 drivers/isdn/hardware/mISDN/netjet.c mISDNisac_irq(&card->isac, val); val 84 drivers/isdn/hardware/mISDN/speedfax.c set_debug(const char *val, const struct kernel_param *kp) val 89 drivers/isdn/hardware/mISDN/speedfax.c ret = param_set_uint(val, kp); val 115 drivers/isdn/hardware/mISDN/speedfax.c u8 val; val 119 drivers/isdn/hardware/mISDN/speedfax.c val = inb(sf->cfg + TIGER_AUX_STATUS); val 120 drivers/isdn/hardware/mISDN/speedfax.c if (val & SFAX_TIGER_IRQ_BIT) { /* for us or shared ? */ val 125 drivers/isdn/hardware/mISDN/speedfax.c val = ReadISAR_IND(sf, ISAR_IRQBIT); val 127 drivers/isdn/hardware/mISDN/speedfax.c if (val & ISAR_IRQSTA) val 129 drivers/isdn/hardware/mISDN/speedfax.c val = ReadISAC_IND(sf, ISAC_ISTA); val 130 drivers/isdn/hardware/mISDN/speedfax.c if (val) val 131 drivers/isdn/hardware/mISDN/speedfax.c mISDNisac_irq(&sf->isac, val); val 132 drivers/isdn/hardware/mISDN/speedfax.c val = ReadISAR_IND(sf, ISAR_IRQBIT); val 133 drivers/isdn/hardware/mISDN/speedfax.c if ((val & ISAR_IRQSTA) && cnt--) val 88 drivers/isdn/hardware/mISDN/w6692.c set_debug(const char *val, const struct kernel_param *kp) val 93 drivers/isdn/hardware/mISDN/w6692.c ret = param_set_uint(val, kp); val 154 drivers/isdn/hardware/mISDN/w6692.c int val; val 156 drivers/isdn/hardware/mISDN/w6692.c val = ReadW6692(card, W_D_RBCH); val 158 drivers/isdn/hardware/mISDN/w6692.c W6692Ver[(val >> 6) & 3]); val 533 drivers/isdn/hardware/mISDN/w6692.c u8 val; val 542 drivers/isdn/hardware/mISDN/w6692.c val = *vol & 7; val 543 drivers/isdn/hardware/mISDN/w6692.c val = 7 - val; val 545 drivers/isdn/hardware/mISDN/w6692.c val <<= 3; val 550 drivers/isdn/hardware/mISDN/w6692.c card->xaddr |= val; val 834 drivers/isdn/hardware/mISDN/w6692.c u8 val; val 879 drivers/isdn/hardware/mISDN/w6692.c val = ReadW6692(card, W_XADDR); val 882 drivers/isdn/hardware/mISDN/w6692.c card->name, val); val 1215 drivers/isdn/hardware/mISDN/w6692.c u32 val; val 1225 drivers/isdn/hardware/mISDN/w6692.c val = ReadW6692(card, W_ISTA); val 1227 drivers/isdn/hardware/mISDN/w6692.c pr_notice("%s ISTA=%02x\n", card->name, val); val 1228 drivers/isdn/hardware/mISDN/w6692.c val = ReadW6692(card, W_IMASK); val 1230 drivers/isdn/hardware/mISDN/w6692.c pr_notice("%s IMASK=%02x\n", card->name, val); val 1231 drivers/isdn/hardware/mISDN/w6692.c val = ReadW6692(card, W_D_EXIR); val 1233 drivers/isdn/hardware/mISDN/w6692.c pr_notice("%s D_EXIR=%02x\n", card->name, val); val 1234 drivers/isdn/hardware/mISDN/w6692.c val = ReadW6692(card, W_D_EXIM); val 1236 drivers/isdn/hardware/mISDN/w6692.c pr_notice("%s D_EXIM=%02x\n", card->name, val); val 1237 drivers/isdn/hardware/mISDN/w6692.c val = ReadW6692(card, W_D_RSTA); val 1239 drivers/isdn/hardware/mISDN/w6692.c pr_notice("%s D_RSTA=%02x\n", card->name, val); val 54 drivers/isdn/mISDN/dsp_hwec.c char *dup, *tok, *name, *val; val 65 drivers/isdn/mISDN/dsp_hwec.c val = tok; val 67 drivers/isdn/mISDN/dsp_hwec.c if (!val) val 71 drivers/isdn/mISDN/dsp_hwec.c if (sscanf(val, "%d", &tmp) == 1) val 355 drivers/isdn/mISDN/layer1.c int val = event & HW_TIMER3_VMASK; val 357 drivers/isdn/mISDN/layer1.c if (val < 5) val 358 drivers/isdn/mISDN/layer1.c val = 5; val 359 drivers/isdn/mISDN/layer1.c if (val > 30) val 360 drivers/isdn/mISDN/layer1.c val = 30; val 361 drivers/isdn/mISDN/layer1.c l1->t3_value = val; val 282 drivers/isdn/mISDN/socket.c int err = -EINVAL, val[2]; val 318 drivers/isdn/mISDN/socket.c val[0] = cmd; val 319 drivers/isdn/mISDN/socket.c if (get_user(val[1], (int __user *)p)) { val 324 drivers/isdn/mISDN/socket.c CONTROL_CHANNEL, val); val 332 drivers/isdn/mISDN/socket.c val[0] = cmd; val 333 drivers/isdn/mISDN/socket.c if (get_user(val[1], (int __user *)p)) { val 338 drivers/isdn/mISDN/socket.c CONTROL_CHANNEL, val); val 1174 drivers/isdn/mISDN/tei.c unsigned int *val = (unsigned int *)arg; val 1176 drivers/isdn/mISDN/tei.c switch (val[0]) { val 1178 drivers/isdn/mISDN/tei.c if (val[1]) val 1184 drivers/isdn/mISDN/tei.c if (val[1]) val 75 drivers/leds/led-class-flash.c return sprintf(buf, "%u\n", fled_cdev->brightness.val); val 174 drivers/leds/led-class-flash.c return sprintf(buf, "%u\n", fled_cdev->timeout.val); val 259 drivers/leds/led-class-flash.c fled_cdev->brightness.val); val 260 drivers/leds/led-class-flash.c call_flash_op(fled_cdev, timeout_set, fled_cdev->timeout.val); val 334 drivers/leds/led-class-flash.c v = s->val + s->step / 2; val 338 drivers/leds/led-class-flash.c s->val = s->min + offset; val 346 drivers/leds/led-class-flash.c s->val = timeout; val 350 drivers/leds/led-class-flash.c return call_flash_op(fled_cdev, timeout_set, s->val); val 368 drivers/leds/led-class-flash.c s->val = brightness; val 372 drivers/leds/led-class-flash.c return call_flash_op(fled_cdev, flash_brightness_set, s->val); val 389 drivers/leds/led-class-flash.c s->val = brightness; val 182 drivers/leds/leds-aat1290.c aat1290_set_flash_safety_timer(led, timeout->val); val 369 drivers/leds/leds-aat1290.c setting->val = setting->max; val 435 drivers/leds/leds-aat1290.c s->val = s->max; val 156 drivers/leds/leds-as3645a.c static int as3645a_write(struct as3645a *flash, u8 addr, u8 val) val 161 drivers/leds/leds-as3645a.c rval = i2c_smbus_write_byte_data(client, addr, val); val 163 drivers/leds/leds-as3645a.c dev_dbg(&client->dev, "Write Addr:%02X Val:%02X %s\n", addr, val, val 199 drivers/leds/leds-as3645a.c u8 val; val 201 drivers/leds/leds-as3645a.c val = (flash->flash_current << AS_CURRENT_FLASH_CURRENT_SHIFT) val 205 drivers/leds/leds-as3645a.c return as3645a_write(flash, AS_CURRENT_SET_REG, val); val 210 drivers/leds/leds-as3645a.c u8 val; val 212 drivers/leds/leds-as3645a.c val = flash->timeout << AS_INDICATOR_AND_TIMER_TIMEOUT_SHIFT; val 214 drivers/leds/leds-as3645a.c val |= (flash->cfg.voltage_reference val 219 drivers/leds/leds-as3645a.c return as3645a_write(flash, AS_INDICATOR_AND_TIMER_REG, val); val 287 drivers/leds/leds-as3645a.c unsigned int val) val 289 drivers/leds/leds-as3645a.c if (val < min) val 290 drivers/leds/leds-as3645a.c val = min; val 292 drivers/leds/leds-as3645a.c if (val > max) val 293 drivers/leds/leds-as3645a.c val = max; val 295 drivers/leds/leds-as3645a.c return (val - min) / step; val 595 drivers/leds/leds-as3645a.c cfg->val = flash->cfg.flash_max_ua; val 601 drivers/leds/leds-as3645a.c cfg->val = flash->cfg.flash_timeout_us; val 640 drivers/leds/leds-as3645a.c .val = flash->cfg.assist_max_ua, val 648 drivers/leds/leds-as3645a.c .val = flash->cfg.indicator_max_ua, val 108 drivers/leds/leds-bcm6328.c unsigned long val, shift; val 116 drivers/leds/leds-bcm6328.c val = bcm6328_led_read(mode); val 117 drivers/leds/leds-bcm6328.c val &= ~(BCM6328_LED_MODE_MASK << BCM6328_LED_SHIFT(shift % 16)); val 118 drivers/leds/leds-bcm6328.c val |= (value << BCM6328_LED_SHIFT(shift % 16)); val 119 drivers/leds/leds-bcm6328.c bcm6328_led_write(mode, val); val 182 drivers/leds/leds-bcm6328.c unsigned long val; val 187 drivers/leds/leds-bcm6328.c val = bcm6328_led_read(led->mem + BCM6328_REG_INIT); val 188 drivers/leds/leds-bcm6328.c val &= ~BCM6328_LED_FAST_INTV_MASK; val 189 drivers/leds/leds-bcm6328.c val |= (delay << BCM6328_LED_FAST_INTV_SHIFT); val 190 drivers/leds/leds-bcm6328.c bcm6328_led_write(led->mem + BCM6328_REG_INIT, val); val 208 drivers/leds/leds-bcm6328.c unsigned long flags, val; val 211 drivers/leds/leds-bcm6328.c val = bcm6328_led_read(mem + BCM6328_REG_HWDIS); val 212 drivers/leds/leds-bcm6328.c val &= ~BIT(reg); val 213 drivers/leds/leds-bcm6328.c bcm6328_led_write(mem + BCM6328_REG_HWDIS, val); val 240 drivers/leds/leds-bcm6328.c val = bcm6328_led_read(addr); val 241 drivers/leds/leds-bcm6328.c val |= (BIT(reg % 4) << (((sel % 4) * 4) + 16)); val 242 drivers/leds/leds-bcm6328.c bcm6328_led_write(addr, val); val 267 drivers/leds/leds-bcm6328.c val = bcm6328_led_read(addr); val 268 drivers/leds/leds-bcm6328.c val |= (BIT(reg % 4) << ((sel % 4) * 4)); val 269 drivers/leds/leds-bcm6328.c bcm6328_led_write(addr, val); val 307 drivers/leds/leds-bcm6328.c unsigned long val, shift; val 315 drivers/leds/leds-bcm6328.c val = bcm6328_led_read(mode) >> val 317 drivers/leds/leds-bcm6328.c val &= BCM6328_LED_MODE_MASK; val 318 drivers/leds/leds-bcm6328.c if ((led->active_low && val == BCM6328_LED_MODE_OFF) || val 319 drivers/leds/leds-bcm6328.c (!led->active_low && val == BCM6328_LED_MODE_ON)) val 352 drivers/leds/leds-bcm6328.c unsigned long val, *blink_leds, *blink_delay; val 380 drivers/leds/leds-bcm6328.c val = bcm6328_led_read(mem + BCM6328_REG_INIT); val 381 drivers/leds/leds-bcm6328.c val &= ~(BCM6328_INIT_MASK); val 383 drivers/leds/leds-bcm6328.c val |= BCM6328_SERIAL_LED_EN; val 385 drivers/leds/leds-bcm6328.c val |= BCM6328_SERIAL_LED_MUX; val 387 drivers/leds/leds-bcm6328.c val |= BCM6328_SERIAL_LED_CLK_NPOL; val 389 drivers/leds/leds-bcm6328.c val |= BCM6328_SERIAL_LED_DATA_PPOL; val 391 drivers/leds/leds-bcm6328.c val |= BCM6328_SERIAL_LED_SHIFT_DIR; val 392 drivers/leds/leds-bcm6328.c bcm6328_led_write(mem + BCM6328_REG_INIT, val); val 66 drivers/leds/leds-bcm6358.c unsigned long val; val 68 drivers/leds/leds-bcm6358.c while ((val = bcm6358_led_read(mem + BCM6358_REG_CTRL)) & val 72 drivers/leds/leds-bcm6358.c return val; val 80 drivers/leds/leds-bcm6358.c unsigned long flags, val; val 84 drivers/leds/leds-bcm6358.c val = bcm6358_led_read(led->mem + BCM6358_REG_MODE); val 87 drivers/leds/leds-bcm6358.c val |= BIT(led->pin); val 89 drivers/leds/leds-bcm6358.c val &= ~(BIT(led->pin)); val 90 drivers/leds/leds-bcm6358.c bcm6358_led_write(led->mem + BCM6358_REG_MODE, val); val 121 drivers/leds/leds-bcm6358.c unsigned long val; val 122 drivers/leds/leds-bcm6358.c val = bcm6358_led_read(led->mem + BCM6358_REG_MODE); val 123 drivers/leds/leds-bcm6358.c val &= BIT(led->pin); val 124 drivers/leds/leds-bcm6358.c if ((led->active_low && !val) || val 125 drivers/leds/leds-bcm6358.c (!led->active_low && val)) val 157 drivers/leds/leds-bcm6358.c unsigned long val; val 174 drivers/leds/leds-bcm6358.c val = bcm6358_led_busy(mem); val 175 drivers/leds/leds-bcm6358.c val &= ~(BCM6358_SLED_POLARITY | BCM6358_SLED_CLKDIV_MASK); val 177 drivers/leds/leds-bcm6358.c val |= BCM6358_SLED_POLARITY; val 181 drivers/leds/leds-bcm6358.c val |= BCM6358_SLED_CLKDIV_8; val 184 drivers/leds/leds-bcm6358.c val |= BCM6358_SLED_CLKDIV_4; val 187 drivers/leds/leds-bcm6358.c val |= BCM6358_SLED_CLKDIV_2; val 190 drivers/leds/leds-bcm6358.c val |= BCM6358_SLED_CLKDIV_1; val 193 drivers/leds/leds-bcm6358.c bcm6358_led_write(mem + BCM6358_REG_CTRL, val); val 158 drivers/leds/leds-bd2802.c static int bd2802_write_byte(struct i2c_client *client, u8 reg, u8 val) val 160 drivers/leds/leds-bd2802.c int ret = i2c_smbus_write_byte_data(client, reg, val); val 165 drivers/leds/leds-bd2802.c __func__, reg, val, ret); val 322 drivers/leds/leds-bd2802.c unsigned long val; \ val 326 drivers/leds/leds-bd2802.c ret = kstrtoul(buf, 16, &val); \ val 330 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg_addr, (u8) val); \ val 486 drivers/leds/leds-bd2802.c unsigned long val; \ val 490 drivers/leds/leds-bd2802.c ret = kstrtoul(buf, 16, &val); \ val 494 drivers/leds/leds-bd2802.c led->attr_name = val; \ val 45 drivers/leds/leds-da903x.c uint8_t val; val 55 drivers/leds/leds-da903x.c val = led->flags & ~0x87; val 56 drivers/leds/leds-da903x.c val |= value ? 0x80 : 0; /* EN bit */ val 57 drivers/leds/leds-da903x.c val |= (0x7 - (value >> 5)) & 0x7; /* PWM<2:0> */ val 59 drivers/leds/leds-da903x.c val); val 62 drivers/leds/leds-da903x.c val = led->flags & ~0x80; val 63 drivers/leds/leds-da903x.c val |= value ? 0x80 : 0; /* EN bit */ val 64 drivers/leds/leds-da903x.c ret = da903x_write(led->master, DA9030_MISC_CONTROL_A, val); val 69 drivers/leds/leds-da903x.c val = (value * 0x5f / LED_FULL) & 0x7f; val 70 drivers/leds/leds-da903x.c val |= (led->flags & DA9034_LED_RAMP) ? 0x80 : 0; val 72 drivers/leds/leds-da903x.c val); val 75 drivers/leds/leds-da903x.c val = value & 0xfe; val 76 drivers/leds/leds-da903x.c ret = da903x_write(led->master, DA9034_VIBRA, val); val 42 drivers/leds/leds-da9052.c u8 val; val 45 drivers/leds/leds-da9052.c val = (brightness & 0x7f) | DA9052_LED_CONT_DIM; val 47 drivers/leds/leds-da9052.c error = da9052_reg_write(led->da9052, led_reg[led->led_index], val); val 137 drivers/leds/leds-is31fl32xx.c static int is31fl32xx_write(struct is31fl32xx_priv *priv, u8 reg, u8 val) val 141 drivers/leds/leds-is31fl32xx.c dev_dbg(&priv->client->dev, "writing register 0x%02X=0x%02X", reg, val); val 143 drivers/leds/leds-is31fl32xx.c ret = i2c_smbus_write_byte_data(priv->client, reg, val); val 189 drivers/leds/leds-ktd2692.c flash_tm_reg = GET_TIMEOUT_OFFSET(timeout->val, timeout->step); val 244 drivers/leds/leds-ktd2692.c setting->val = cfg->flash_max_timeout; val 83 drivers/leds/leds-lm3533.c u8 val; val 100 drivers/leds/leds-lm3533.c val = mask; val 102 drivers/leds/leds-lm3533.c val = 0; val 104 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, LM3533_REG_PATTERN_ENABLE, val, mask); val 134 drivers/leds/leds-lm3533.c u8 val; val 137 drivers/leds/leds-lm3533.c ret = lm3533_ctrlbank_get_brightness(&led->cb, &val); val 141 drivers/leds/leds-lm3533.c dev_dbg(led->cdev.dev, "%s - %u\n", __func__, val); val 143 drivers/leds/leds-lm3533.c return val; val 185 drivers/leds/leds-lm3533.c unsigned val; val 187 drivers/leds/leds-lm3533.c val = (*t + t_step / 2 - t_min) / t_step + v_min; val 189 drivers/leds/leds-lm3533.c *t = t_step * (val - v_min) + t_min; val 191 drivers/leds/leds-lm3533.c return (u8)val; val 210 drivers/leds/leds-lm3533.c u8 val; val 216 drivers/leds/leds-lm3533.c val = time_to_val(&t, LM3533_LED_DELAY3_TMIN, val 222 drivers/leds/leds-lm3533.c val = time_to_val(&t, LM3533_LED_DELAY2_TMIN, val 228 drivers/leds/leds-lm3533.c val = time_to_val(&t, LM3533_LED_DELAY1_TMIN, val 236 drivers/leds/leds-lm3533.c return val; val 247 drivers/leds/leds-lm3533.c u8 val; val 257 drivers/leds/leds-lm3533.c val = lm3533_led_get_hw_delay(&t); val 260 drivers/leds/leds-lm3533.c *delay, t, val); val 262 drivers/leds/leds-lm3533.c ret = lm3533_write(led->lm3533, reg, val); val 340 drivers/leds/leds-lm3533.c u8 val; val 343 drivers/leds/leds-lm3533.c ret = lm3533_read(led->lm3533, reg, &val); val 347 drivers/leds/leds-lm3533.c return scnprintf(buf, PAGE_SIZE, "%x\n", val); val 370 drivers/leds/leds-lm3533.c u8 val; val 374 drivers/leds/leds-lm3533.c if (kstrtou8(buf, 0, &val) || val > LM3533_RISEFALLTIME_MAX) val 378 drivers/leds/leds-lm3533.c ret = lm3533_write(led->lm3533, reg, val); val 408 drivers/leds/leds-lm3533.c u8 val; val 412 drivers/leds/leds-lm3533.c ret = lm3533_read(led->lm3533, reg, &val); val 416 drivers/leds/leds-lm3533.c channel = (val & LM3533_REG_CTRLBANK_BCONF_ALS_CHANNEL_MASK) + 1; val 429 drivers/leds/leds-lm3533.c u8 val; val 442 drivers/leds/leds-lm3533.c val = channel - 1; val 444 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); val 458 drivers/leds/leds-lm3533.c u8 val; val 462 drivers/leds/leds-lm3533.c ret = lm3533_read(led->lm3533, reg, &val); val 466 drivers/leds/leds-lm3533.c enable = val & LM3533_REG_CTRLBANK_BCONF_ALS_EN_MASK; val 480 drivers/leds/leds-lm3533.c u8 val; val 490 drivers/leds/leds-lm3533.c val = mask; val 492 drivers/leds/leds-lm3533.c val = 0; val 494 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); val 507 drivers/leds/leds-lm3533.c u8 val; val 512 drivers/leds/leds-lm3533.c ret = lm3533_read(led->lm3533, reg, &val); val 516 drivers/leds/leds-lm3533.c if (val & LM3533_REG_CTRLBANK_BCONF_MAPPING_MASK) val 533 drivers/leds/leds-lm3533.c u8 val; val 543 drivers/leds/leds-lm3533.c val = mask; val 545 drivers/leds/leds-lm3533.c val = 0; val 547 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); val 560 drivers/leds/leds-lm3533.c u8 val; val 563 drivers/leds/leds-lm3533.c ret = lm3533_ctrlbank_get_pwm(&led->cb, &val); val 567 drivers/leds/leds-lm3533.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 576 drivers/leds/leds-lm3533.c u8 val; val 579 drivers/leds/leds-lm3533.c if (kstrtou8(buf, 0, &val)) val 582 drivers/leds/leds-lm3533.c ret = lm3533_ctrlbank_set_pwm(&led->cb, val); val 335 drivers/leds/leds-lm3601x.c setting->val = led->max_flash_timeout; val 341 drivers/leds/leds-lm3601x.c setting->val = led->flash_current_max; val 171 drivers/leds/leds-lp3944.c u8 val = 0; val 208 drivers/leds/leds-lp3944.c lp3944_reg_read(led->client, reg, &val); val 210 drivers/leds/leds-lp3944.c val &= ~(LP3944_LED_STATUS_MASK << (id << 1)); val 211 drivers/leds/leds-lp3944.c val |= (status << (id << 1)); val 214 drivers/leds/leds-lp3944.c __func__, led->ldev.name, reg, id, status, val); val 217 drivers/leds/leds-lp3944.c err = lp3944_reg_write(led->client, reg, val); val 23 drivers/leds/leds-lp3952.c static int lp3952_register_write(struct i2c_client *client, u8 reg, u8 val) val 28 drivers/leds/leds-lp3952.c ret = regmap_write(priv->regmap, reg, val); val 32 drivers/leds/leds-lp3952.c __func__, reg, val, ret); val 39 drivers/leds/leds-lp3952.c int ret, val; val 43 drivers/leds/leds-lp3952.c val = 1 << led_id; val 45 drivers/leds/leds-lp3952.c val = LP3952_LED_MASK_ALL; val 47 drivers/leds/leds-lp3952.c ret = regmap_update_bits(priv->regmap, LP3952_REG_LED_CTRL, val, val 48 drivers/leds/leds-lp3952.c on ? val : 0); val 130 drivers/leds/leds-lp5521.c static const u8 val[] = { val 136 drivers/leds/leds-lp5521.c lp55xx_update_bits(chip, LP5521_REG_OP_MODE, mask[idx], val[idx]); val 283 drivers/leds/leds-lp5521.c u8 val; val 291 drivers/leds/leds-lp5521.c ret = lp55xx_read(chip, LP5521_REG_R_CURRENT, &val); val 296 drivers/leds/leds-lp5521.c if (val != LP5521_REG_R_CURR_DEFAULT) { val 299 drivers/leds/leds-lp5521.c LP5521_REG_R_CURR_DEFAULT, val); val 309 drivers/leds/leds-lp5521.c val = LP5521_DEFAULT_CFG; val 311 drivers/leds/leds-lp5521.c val |= LP5521_CLK_INT; val 313 drivers/leds/leds-lp5521.c ret = lp55xx_write(chip, LP5521_REG_CONFIG, val); val 484 drivers/leds/leds-lp5521.c .val = LP5521_RESET, val 488 drivers/leds/leds-lp5521.c .val = LP5521_ENABLE_DEFAULT, val 164 drivers/leds/leds-lp5523.c static const u8 val[] = { val 170 drivers/leds/leds-lp5523.c lp55xx_update_bits(chip, LP5523_REG_OP_MODE, mask[idx], val[idx]); val 686 drivers/leds/leds-lp5523.c u8 val; val 689 drivers/leds/leds-lp5523.c ret = lp55xx_read(chip, LP5523_REG_MASTER_FADER_BASE + nr - 1, &val); val 693 drivers/leds/leds-lp5523.c ret = sprintf(buf, "%u\n", val); val 708 drivers/leds/leds-lp5523.c unsigned long val; val 710 drivers/leds/leds-lp5523.c if (kstrtoul(buf, 0, &val)) val 713 drivers/leds/leds-lp5523.c if (val > 0xff) val 718 drivers/leds/leds-lp5523.c (u8)val); val 737 drivers/leds/leds-lp5523.c u8 val; val 742 drivers/leds/leds-lp5523.c ret = lp55xx_read(chip, LP5523_REG_LED_CTRL_BASE + i, &val); val 746 drivers/leds/leds-lp5523.c val = (val & LP5523_FADER_MAPPING_MASK) val 748 drivers/leds/leds-lp5523.c if (val > 3) { val 752 drivers/leds/leds-lp5523.c buf[pos++] = val + '0'; val 768 drivers/leds/leds-lp5523.c u8 val; val 776 drivers/leds/leds-lp5523.c val = (buf[i] - '0') << LP5523_FADER_MAPPING_SHIFT; val 780 drivers/leds/leds-lp5523.c val); val 851 drivers/leds/leds-lp5523.c .val = LP5523_RESET, val 855 drivers/leds/leds-lp5523.c .val = LP5523_ENABLE, val 136 drivers/leds/leds-lp5562.c static const u8 val[] = { val 142 drivers/leds/leds-lp5562.c lp55xx_update_bits(chip, LP5562_REG_OP_MODE, mask[idx], val[idx]); val 440 drivers/leds/leds-lp5562.c u8 val; val 451 drivers/leds/leds-lp5562.c val = LP5562_ENG_SEL_RGB; val 458 drivers/leds/leds-lp5562.c val = LP5562_ENG1_FOR_W; val 461 drivers/leds/leds-lp5562.c val = LP5562_ENG2_FOR_W; val 464 drivers/leds/leds-lp5562.c val = LP5562_ENG3_FOR_W; val 476 drivers/leds/leds-lp5562.c lp55xx_update_bits(chip, LP5562_REG_ENG_SEL, mask, val); val 500 drivers/leds/leds-lp5562.c .val = LP5562_RESET, val 504 drivers/leds/leds-lp5562.c .val = LP5562_ENABLE_DEFAULT, val 42 drivers/leds/leds-lp55xx-common.c u8 val = cfg->reset.val; val 45 drivers/leds/leds-lp55xx-common.c lp55xx_write(chip, addr, val); val 52 drivers/leds/leds-lp55xx-common.c u8 val = cfg->enable.val; val 55 drivers/leds/leds-lp55xx-common.c ret = lp55xx_write(chip, addr, val); val 61 drivers/leds/leds-lp55xx-common.c ret = lp55xx_read(chip, addr, &val); val 65 drivers/leds/leds-lp55xx-common.c if (val != cfg->enable.val) val 244 drivers/leds/leds-lp55xx-common.c unsigned long val; val 247 drivers/leds/leds-lp55xx-common.c if (kstrtoul(buf, 0, &val)) val 252 drivers/leds/leds-lp55xx-common.c switch (val) { val 257 drivers/leds/leds-lp55xx-common.c chip->engine_idx = val; val 262 drivers/leds/leds-lp55xx-common.c dev_err(dev, "%lu: invalid engine index. (1, 2, 3)\n", val); val 286 drivers/leds/leds-lp55xx-common.c unsigned long val; val 288 drivers/leds/leds-lp55xx-common.c if (kstrtoul(buf, 0, &val)) val 293 drivers/leds/leds-lp55xx-common.c if (val <= 0) { val 319 drivers/leds/leds-lp55xx-common.c int lp55xx_write(struct lp55xx_chip *chip, u8 reg, u8 val) val 321 drivers/leds/leds-lp55xx-common.c return i2c_smbus_write_byte_data(chip->cl, reg, val); val 325 drivers/leds/leds-lp55xx-common.c int lp55xx_read(struct lp55xx_chip *chip, u8 reg, u8 *val) val 333 drivers/leds/leds-lp55xx-common.c *val = ret; val 338 drivers/leds/leds-lp55xx-common.c int lp55xx_update_bits(struct lp55xx_chip *chip, u8 reg, u8 mask, u8 val) val 348 drivers/leds/leds-lp55xx-common.c tmp |= val & mask; val 86 drivers/leds/leds-lp55xx-common.h u8 val; val 177 drivers/leds/leds-lp55xx-common.h extern int lp55xx_write(struct lp55xx_chip *chip, u8 reg, u8 val); val 178 drivers/leds/leds-lp55xx-common.h extern int lp55xx_read(struct lp55xx_chip *chip, u8 reg, u8 *val); val 180 drivers/leds/leds-lp55xx-common.h u8 mask, u8 val); val 93 drivers/leds/leds-lp8501.c u8 val = LP8501_DEFAULT_CFG; val 103 drivers/leds/leds-lp8501.c val |= LP8501_INT_CLK; val 105 drivers/leds/leds-lp8501.c ret = lp55xx_write(chip, LP8501_REG_CONFIG, val); val 123 drivers/leds/leds-lp8501.c static const u8 val[] = { val 135 drivers/leds/leds-lp8501.c lp55xx_update_bits(chip, LP8501_REG_OP_MODE, mask[idx], val[idx]); val 288 drivers/leds/leds-lp8501.c .val = LP8501_RESET, val 292 drivers/leds/leds-lp8501.c .val = LP8501_ENABLE, val 46 drivers/leds/leds-lp8788.c u8 addr, mask, val; val 60 drivers/leds/leds-lp8788.c val = cfg->scale << (cfg->num + LP8788_ISINK_SCALE_OFFSET); val 61 drivers/leds/leds-lp8788.c ret = lp8788_update_bits(led->lp, addr, mask, val); val 68 drivers/leds/leds-lp8788.c val = cfg->iout; val 70 drivers/leds/leds-lp8788.c return lp8788_update_bits(led->lp, addr, mask, val); val 79 drivers/leds/leds-lp8788.c u8 val = on << num; val 81 drivers/leds/leds-lp8788.c ret = lp8788_update_bits(led->lp, LP8788_ISINK_CTRL, mask, val); val 89 drivers/leds/leds-lp8788.c enum led_brightness val) val 103 drivers/leds/leds-lp8788.c ret = lp8788_write_byte(led->lp, lp8788_pwm_addr[num], val); val 112 drivers/leds/leds-lp8788.c enable = (val > 0) ? 1 : 0; val 51 drivers/leds/leds-max77650.c int val, mask; val 56 drivers/leds/leds-max77650.c val = MAX77650_LED_DISABLE; val 58 drivers/leds/leds-max77650.c val = MAX77650_LED_ENABLE | brightness; val 60 drivers/leds/leds-max77650.c return regmap_update_bits(led->map, led->regA, mask, val); val 808 drivers/leds/leds-max77693.c setting->val = setting->max; val 815 drivers/leds/leds-max77693.c setting->val = setting->max; val 860 drivers/leds/leds-max77693.c s->val = s->max; val 909 drivers/leds/leds-max77693.c sub_led->flash_timeout = fled_cdev->timeout.val; val 52 drivers/leds/leds-max8997.c u8 mask = 0, val; val 57 drivers/leds/leds-max8997.c val = led->id ? val 63 drivers/leds/leds-max8997.c val = led->id ? val 70 drivers/leds/leds-max8997.c val = led->id ? val 77 drivers/leds/leds-max8997.c val = led->id ? val 87 drivers/leds/leds-max8997.c ret = max8997_update_reg(client, MAX8997_REG_LEN_CNTL, val, val 101 drivers/leds/leds-max8997.c u8 val = 0, mask = MAX8997_LED_BOOST_ENABLE_MASK; val 106 drivers/leds/leds-max8997.c val = enable ? MAX8997_LED_BOOST_ENABLE_MASK : 0; val 108 drivers/leds/leds-max8997.c ret = max8997_update_reg(client, MAX8997_REG_BOOST_CNTL, val, mask); val 121 drivers/leds/leds-max8997.c u8 val = 0, mask = 0, reg = 0; val 126 drivers/leds/leds-max8997.c val = value << MAX8997_LED_FLASH_SHIFT; val 132 drivers/leds/leds-max8997.c val = value << MAX8997_LED_MOVIE_SHIFT; val 141 drivers/leds/leds-max8997.c ret = max8997_update_reg(client, reg, val, mask); val 260 drivers/leds/leds-mlxcpld.c u8 nib, val; val 274 drivers/leds/leds-mlxcpld.c &val); val 276 drivers/leds/leds-mlxcpld.c val = (val & mask) | nib; val 278 drivers/leds/leds-mlxcpld.c &val); val 526 drivers/leds/leds-netxbig.c int val; val 531 drivers/leds/leds-netxbig.c "mode-val", 2 * i + 1, &val); val 536 drivers/leds/leds-netxbig.c mode_val[mode] = val; val 96 drivers/leds/leds-ot200.c u8 *val; val 102 drivers/leds/leds-ot200.c val = &leds_front; val 104 drivers/leds/leds-ot200.c val = &leds_back; val 109 drivers/leds/leds-ot200.c *val &= ~led->mask; val 111 drivers/leds/leds-ot200.c *val |= led->mask; val 113 drivers/leds/leds-ot200.c outb(*val, led->port); val 280 drivers/leds/leds-pca9532.c static void pca9532_gpio_set_value(struct gpio_chip *gc, unsigned offset, int val) val 285 drivers/leds/leds-pca9532.c if (val) val 311 drivers/leds/leds-pca9532.c static int pca9532_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int val) val 313 drivers/leds/leds-pca9532.c pca9532_gpio_set_value(gc, offset, val); val 159 drivers/leds/leds-pca955x.c static int pca955x_write_psc(struct i2c_client *client, int n, u8 val) val 166 drivers/leds/leds-pca955x.c val); val 169 drivers/leds/leds-pca955x.c __func__, n, val, ret); val 180 drivers/leds/leds-pca955x.c static int pca955x_write_pwm(struct i2c_client *client, int n, u8 val) val 187 drivers/leds/leds-pca955x.c val); val 190 drivers/leds/leds-pca955x.c __func__, n, val, ret); val 198 drivers/leds/leds-pca955x.c static int pca955x_write_ls(struct i2c_client *client, int n, u8 val) val 205 drivers/leds/leds-pca955x.c val); val 208 drivers/leds/leds-pca955x.c __func__, n, val, ret); val 216 drivers/leds/leds-pca955x.c static int pca955x_read_ls(struct i2c_client *client, int n, u8 *val) val 228 drivers/leds/leds-pca955x.c *val = (u8)ret; val 291 drivers/leds/leds-pca955x.c static int pca955x_read_input(struct i2c_client *client, int n, u8 *val) val 300 drivers/leds/leds-pca955x.c *val = (u8)ret; val 317 drivers/leds/leds-pca955x.c int val) val 322 drivers/leds/leds-pca955x.c if (val) val 329 drivers/leds/leds-pca955x.c int val) val 331 drivers/leds/leds-pca955x.c pca955x_set_value(gc, offset, val); val 357 drivers/leds/leds-pca955x.c unsigned int offset, int val) val 359 drivers/leds/leds-pca955x.c return pca955x_set_value(gc, offset, val); val 220 drivers/leds/leds-pca963x.c unsigned int val) val 224 drivers/leds/leds-pca963x.c return scaling ? DIV_ROUND_CLOSEST(val * scaling, 1000) : val; val 34 drivers/leds/leds-pm8058.c unsigned int val = 0; val 40 drivers/leds/leds-pm8058.c val = value << PM8058_LED_TYPE_COMMON_SHIFT; val 45 drivers/leds/leds-pm8058.c val = value << PM8058_LED_TYPE_KEYPAD_SHIFT; val 51 drivers/leds/leds-pm8058.c ret = regmap_update_bits(led->map, led->reg, mask, val); val 60 drivers/leds/leds-pm8058.c unsigned int val; val 64 drivers/leds/leds-pm8058.c ret = regmap_read(led->map, led->reg, &val); val 72 drivers/leds/leds-pm8058.c val &= PM8058_LED_TYPE_COMMON_MASK; val 73 drivers/leds/leds-pm8058.c val >>= PM8058_LED_TYPE_COMMON_SHIFT; val 77 drivers/leds/leds-pm8058.c val &= PM8058_LED_TYPE_KEYPAD_MASK; val 78 drivers/leds/leds-pm8058.c val >>= PM8058_LED_TYPE_KEYPAD_SHIFT; val 81 drivers/leds/leds-pm8058.c val = LED_OFF; val 85 drivers/leds/leds-pm8058.c return val; val 40 drivers/leds/leds-syscon.c u32 val; val 44 drivers/leds/leds-syscon.c val = 0; val 47 drivers/leds/leds-syscon.c val = sled->mask; val 51 drivers/leds/leds-syscon.c ret = regmap_update_bits(sled->map, sled->offset, sled->mask, val); val 95 drivers/leds/leds-syscon.c u32 val; val 97 drivers/leds/leds-syscon.c ret = regmap_read(map, sled->offset, &val); val 100 drivers/leds/leds-syscon.c sled->state = !!(val & sled->mask); val 273 drivers/leds/leds-tca6507.c static void set_select(struct tca6507_chip *tca, int led, int val) val 280 drivers/leds/leds-tca6507.c if (val & (1 << bit)) val 607 drivers/leds/leds-tca6507.c unsigned offset, int val) val 618 drivers/leds/leds-tca6507.c val ? TCA6507_LS_LED_OFF : TCA6507_LS_LED_ON); val 625 drivers/leds/leds-tca6507.c unsigned offset, int val) val 627 drivers/leds/leds-tca6507.c tca6507_gpio_set_value(gc, offset, val); val 23 drivers/leds/leds-ti-lmu-common.c u8 reg, val; val 41 drivers/leds/leds-ti-lmu-common.c val = brightness >> LMU_11BIT_MSB_SHIFT; val 43 drivers/leds/leds-ti-lmu-common.c val = brightness; val 48 drivers/leds/leds-ti-lmu-common.c return regmap_write(regmap, reg, val); val 75 drivers/leds/leds-tlc591xx.c u8 val; val 81 drivers/leds/leds-tlc591xx.c val = MODE2_OCH_STOP | mode; val 83 drivers/leds/leds-tlc591xx.c return regmap_write(regmap, TLC591XX_REG_MODE2, val); val 88 drivers/leds/leds-tlc591xx.c u8 val) val 94 drivers/leds/leds-tlc591xx.c val = val << i; val 96 drivers/leds/leds-tlc591xx.c return regmap_update_bits(priv->regmap, addr, mask, val); val 110 drivers/macintosh/ams/ams-i2c.c u8 val = ams_i2c_read(AMS_CTRLX); val 112 drivers/macintosh/ams/ams-i2c.c val |= 0x80; val 114 drivers/macintosh/ams/ams-i2c.c val &= ~0x80; val 115 drivers/macintosh/ams/ams-i2c.c ams_i2c_write(AMS_CTRLX, val); val 119 drivers/macintosh/ams/ams-i2c.c u8 val = ams_i2c_read(AMS_CTRLY); val 121 drivers/macintosh/ams/ams-i2c.c val |= 0x80; val 123 drivers/macintosh/ams/ams-i2c.c val &= ~0x80; val 124 drivers/macintosh/ams/ams-i2c.c ams_i2c_write(AMS_CTRLY, val); val 128 drivers/macintosh/ams/ams-i2c.c u8 val = ams_i2c_read(AMS_CTRLZ); val 130 drivers/macintosh/ams/ams-i2c.c val |= 0x80; val 132 drivers/macintosh/ams/ams-i2c.c val &= ~0x80; val 133 drivers/macintosh/ams/ams-i2c.c ams_i2c_write(AMS_CTRLZ, val); val 82 drivers/macintosh/ams/ams-pmu.c u8 val = ams_pmu_get_register(AMS_FF_ENABLE); val 84 drivers/macintosh/ams/ams-pmu.c val |= 0x80; val 86 drivers/macintosh/ams/ams-pmu.c val &= ~0x80; val 87 drivers/macintosh/ams/ams-pmu.c ams_pmu_set_register(AMS_FF_ENABLE, val); val 91 drivers/macintosh/ams/ams-pmu.c u8 val = ams_pmu_get_register(AMS_SHOCK_ENABLE); val 93 drivers/macintosh/ams/ams-pmu.c val |= 0x80; val 95 drivers/macintosh/ams/ams-pmu.c val &= ~0x80; val 96 drivers/macintosh/ams/ams-pmu.c ams_pmu_set_register(AMS_SHOCK_ENABLE, val); val 100 drivers/macintosh/ams/ams-pmu.c u8 val = ams_pmu_get_register(AMS_CONTROL); val 102 drivers/macintosh/ams/ams-pmu.c val |= 0x80; val 104 drivers/macintosh/ams/ams-pmu.c val &= ~0x80; val 105 drivers/macintosh/ams/ams-pmu.c ams_pmu_set_register(AMS_CONTROL, val); val 353 drivers/macintosh/therm_adt746x.c int val; \ val 355 drivers/macintosh/therm_adt746x.c val = simple_strtol(buf, NULL, 10); \ val 356 drivers/macintosh/therm_adt746x.c printk(KERN_INFO "Adjusting limits by %d degrees\n", val); \ val 357 drivers/macintosh/therm_adt746x.c limit_adjust = val; \ val 366 drivers/macintosh/therm_adt746x.c int val; \ val 367 drivers/macintosh/therm_adt746x.c val = simple_strtol(buf, NULL, 10); \ val 368 drivers/macintosh/therm_adt746x.c if (val < 0 || val > 255) \ val 370 drivers/macintosh/therm_adt746x.c printk(KERN_INFO "Setting specified fan speed to %d\n", val); \ val 371 drivers/macintosh/therm_adt746x.c data = val; \ val 155 drivers/macintosh/therm_windtunnel.c int val = (fan_setting << 3) | 7; val 158 drivers/macintosh/therm_windtunnel.c write_reg( x.fan, 0x25, val, 1 ); val 211 drivers/macintosh/therm_windtunnel.c int val; val 222 drivers/macintosh/therm_windtunnel.c if( (val=read_reg(x.thermostat, 1, 1)) >= 0 ) { val 223 drivers/macintosh/therm_windtunnel.c val |= 0x60; val 224 drivers/macintosh/therm_windtunnel.c if( write_reg( x.thermostat, 1, val, 1 ) ) val 937 drivers/macintosh/via-pmu.c char *label, *val; val 951 drivers/macintosh/via-pmu.c val = label; val 952 drivers/macintosh/via-pmu.c while(*val && (*val != '=')) { val 953 drivers/macintosh/via-pmu.c if (*val == ' ') val 954 drivers/macintosh/via-pmu.c *val = 0; val 955 drivers/macintosh/via-pmu.c val++; val 957 drivers/macintosh/via-pmu.c if ((*val) == 0) val 959 drivers/macintosh/via-pmu.c *(val++) = 0; val 960 drivers/macintosh/via-pmu.c while(*val == ' ') val 961 drivers/macintosh/via-pmu.c val++; val 966 drivers/macintosh/via-pmu.c option_lid_wakeup = ((*val) == '1'); val 970 drivers/macintosh/via-pmu.c new_value = ((*val) == '1'); val 28 drivers/macintosh/windfarm.h int (*set_value)(struct wf_control *ct, s32 val); val 29 drivers/macintosh/windfarm.h int (*get_value)(struct wf_control *ct, s32 *val); val 73 drivers/macintosh/windfarm.h static inline int wf_control_set(struct wf_control *ct, s32 val) val 75 drivers/macintosh/windfarm.h return ct->ops->set_value(ct, val); val 78 drivers/macintosh/windfarm.h static inline int wf_control_get(struct wf_control *ct, s32 *val) val 80 drivers/macintosh/windfarm.h return ct->ops->get_value(ct, val); val 100 drivers/macintosh/windfarm.h int (*get_value)(struct wf_sensor *sr, s32 *val); val 120 drivers/macintosh/windfarm.h static inline int wf_sensor_get(struct wf_sensor *sr, s32 *val) val 122 drivers/macintosh/windfarm.h return sr->ops->get_value(sr, val); val 166 drivers/macintosh/windfarm_core.c s32 val = 0; val 169 drivers/macintosh/windfarm_core.c err = ctrl->ops->get_value(ctrl, &val); val 185 drivers/macintosh/windfarm_core.c return sprintf(buf, "%d%s\n", val, typestr); val 194 drivers/macintosh/windfarm_core.c int val; val 198 drivers/macintosh/windfarm_core.c val = simple_strtoul(buf, &endp, 0); val 203 drivers/macintosh/windfarm_core.c err = ctrl->ops->set_value(ctrl, val); val 295 drivers/macintosh/windfarm_core.c s32 val = 0; val 298 drivers/macintosh/windfarm_core.c err = sens->ops->get_value(sens, &val); val 301 drivers/macintosh/windfarm_core.c return sprintf(buf, "%d.%03d\n", FIX32TOPRINT(val)); val 140 drivers/macintosh/windfarm_smu_sat.c s32 val; val 153 drivers/macintosh/windfarm_smu_sat.c val = ((sat->cache[i] << 8) + sat->cache[i+1]) << sens->shift; val 157 drivers/macintosh/windfarm_smu_sat.c val = (val * ((sat->cache[i] << 8) + sat->cache[i+1])) >> 4; val 160 drivers/macintosh/windfarm_smu_sat.c *value = val; val 91 drivers/macintosh/windfarm_smu_sensors.c s32 val; val 94 drivers/macintosh/windfarm_smu_sensors.c rc = smu_read_adc(ads->reg, &val); val 102 drivers/macintosh/windfarm_smu_sensors.c scaled = (s64)(((u64)val) * (u64)cpudiode->m_value); val 113 drivers/macintosh/windfarm_smu_sensors.c s32 val, scaled; val 116 drivers/macintosh/windfarm_smu_sensors.c rc = smu_read_adc(ads->reg, &val); val 124 drivers/macintosh/windfarm_smu_sensors.c scaled = (s32)(val * (u32)cpuvcp->curr_scale); val 134 drivers/macintosh/windfarm_smu_sensors.c s32 val, scaled; val 137 drivers/macintosh/windfarm_smu_sensors.c rc = smu_read_adc(ads->reg, &val); val 145 drivers/macintosh/windfarm_smu_sensors.c scaled = (s32)(val * (u32)cpuvcp->volt_scale); val 155 drivers/macintosh/windfarm_smu_sensors.c s32 val, scaled; val 158 drivers/macintosh/windfarm_smu_sensors.c rc = smu_read_adc(ads->reg, &val); val 166 drivers/macintosh/windfarm_smu_sensors.c scaled = (s32)(val * (u32)slotspow->pow_scale); val 44 drivers/mailbox/arm_mhu.c u32 val; val 46 drivers/mailbox/arm_mhu.c val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS); val 47 drivers/mailbox/arm_mhu.c if (!val) val 50 drivers/mailbox/arm_mhu.c mbox_chan_received_data(chan, (void *)&val); val 52 drivers/mailbox/arm_mhu.c writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS); val 60 drivers/mailbox/arm_mhu.c u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); val 62 drivers/mailbox/arm_mhu.c return (val == 0); val 78 drivers/mailbox/arm_mhu.c u32 val; val 81 drivers/mailbox/arm_mhu.c val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); val 82 drivers/mailbox/arm_mhu.c writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS); val 103 drivers/mailbox/bcm-flexrm-mailbox.c #define BD_START_ADDR_DECODE(val) \ val 104 drivers/mailbox/bcm-flexrm-mailbox.c ((dma_addr_t)((val) & 0x0fffffff) << RING_BD_ALIGN_ORDER) val 961 drivers/mailbox/bcm-flexrm-mailbox.c u32 val, bd_read_offset; val 971 drivers/mailbox/bcm-flexrm-mailbox.c val = readl_relaxed(ring->regs + RING_BD_START_ADDR); val 973 drivers/mailbox/bcm-flexrm-mailbox.c bd_read_offset += (u32)(BD_START_ADDR_DECODE(val) - val 991 drivers/mailbox/bcm-flexrm-mailbox.c u32 val, count, nhcnt; val 1022 drivers/mailbox/bcm-flexrm-mailbox.c val = readl_relaxed(ring->regs + RING_BD_START_ADDR); val 1024 drivers/mailbox/bcm-flexrm-mailbox.c read_offset += (u32)(BD_START_ADDR_DECODE(val) - ring->bd_dma_base); val 1236 drivers/mailbox/bcm-flexrm-mailbox.c u32 val, off; val 1297 drivers/mailbox/bcm-flexrm-mailbox.c val = ring->mbox->num_rings; val 1298 drivers/mailbox/bcm-flexrm-mailbox.c val = (num_online_cpus() < val) ? val / num_online_cpus() : 1; val 1299 drivers/mailbox/bcm-flexrm-mailbox.c cpumask_set_cpu((ring->num / val) % num_online_cpus(), val 1313 drivers/mailbox/bcm-flexrm-mailbox.c val = BD_START_ADDR_VALUE(ring->bd_dma_base); val 1314 drivers/mailbox/bcm-flexrm-mailbox.c writel_relaxed(val, ring->regs + RING_BD_START_ADDR); val 1322 drivers/mailbox/bcm-flexrm-mailbox.c val = CMPL_START_ADDR_VALUE(ring->cmpl_dma_base); val 1323 drivers/mailbox/bcm-flexrm-mailbox.c writel_relaxed(val, ring->regs + RING_CMPL_START_ADDR); val 1338 drivers/mailbox/bcm-flexrm-mailbox.c val = 0; val 1339 drivers/mailbox/bcm-flexrm-mailbox.c val |= (ring->msi_timer_val << MSI_TIMER_VAL_SHIFT); val 1340 drivers/mailbox/bcm-flexrm-mailbox.c val |= BIT(MSI_ENABLE_SHIFT); val 1341 drivers/mailbox/bcm-flexrm-mailbox.c val |= (ring->msi_count_threshold & MSI_COUNT_MASK) << MSI_COUNT_SHIFT; val 1342 drivers/mailbox/bcm-flexrm-mailbox.c writel_relaxed(val, ring->regs + RING_MSI_CONTROL); val 1345 drivers/mailbox/bcm-flexrm-mailbox.c val = BIT(CONTROL_ACTIVE_SHIFT); val 1346 drivers/mailbox/bcm-flexrm-mailbox.c writel_relaxed(val, ring->regs + RING_CONTROL); val 92 drivers/mailbox/hi3660-mailbox.c unsigned long val; val 101 drivers/mailbox/hi3660-mailbox.c val, (val & MBOX_STATE_ACK), 1000, 300000); val 116 drivers/mailbox/hi3660-mailbox.c unsigned int val, retry = 3; val 121 drivers/mailbox/hi3660-mailbox.c val = readl(mbox->base + MBOX_IPC_LOCK_REG); val 122 drivers/mailbox/hi3660-mailbox.c if (!val) val 128 drivers/mailbox/hi3660-mailbox.c if (val) val 131 drivers/mailbox/hi3660-mailbox.c return (!val) ? 0 : -ETIMEDOUT; val 140 drivers/mailbox/hi3660-mailbox.c unsigned int val, retry; val 148 drivers/mailbox/hi3660-mailbox.c val = readl(base + MBOX_SRC_REG); val 149 drivers/mailbox/hi3660-mailbox.c if (val & BIT(mchan->ack_irq)) val 90 drivers/mailbox/hi6220-mailbox.c unsigned int slot, u32 val) val 95 drivers/mailbox/hi6220-mailbox.c status = (status & ~MBOX_STATE_MASK) | val; val 100 drivers/mailbox/hi6220-mailbox.c unsigned int slot, u32 val) val 105 drivers/mailbox/hi6220-mailbox.c mode = (mode & ~MBOX_ACK_CONFIG_MASK) | val; val 75 drivers/mailbox/imx-mailbox.c static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) val 77 drivers/mailbox/imx-mailbox.c iowrite32(val, priv->base + offs); val 88 drivers/mailbox/imx-mailbox.c u32 val; val 91 drivers/mailbox/imx-mailbox.c val = imx_mu_read(priv, IMX_MU_xCR); val 92 drivers/mailbox/imx-mailbox.c val &= ~clr; val 93 drivers/mailbox/imx-mailbox.c val |= set; val 94 drivers/mailbox/imx-mailbox.c imx_mu_write(priv, val, IMX_MU_xCR); val 97 drivers/mailbox/imx-mailbox.c return val; val 112 drivers/mailbox/imx-mailbox.c u32 val, ctrl, dat; val 115 drivers/mailbox/imx-mailbox.c val = imx_mu_read(priv, IMX_MU_xSR); val 119 drivers/mailbox/imx-mailbox.c val &= IMX_MU_xSR_TEn(cp->idx) & val 123 drivers/mailbox/imx-mailbox.c val &= IMX_MU_xSR_RFn(cp->idx) & val 127 drivers/mailbox/imx-mailbox.c val &= IMX_MU_xSR_GIPn(cp->idx) & val 134 drivers/mailbox/imx-mailbox.c if (!val) val 137 drivers/mailbox/imx-mailbox.c if (val == IMX_MU_xSR_TEn(cp->idx)) { val 140 drivers/mailbox/imx-mailbox.c } else if (val == IMX_MU_xSR_RFn(cp->idx)) { val 143 drivers/mailbox/imx-mailbox.c } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { val 84 drivers/mailbox/mailbox-xgene-slimpro.c u32 val = readl(mb_chan->reg + REG_DB_STAT); val 86 drivers/mailbox/mailbox-xgene-slimpro.c if (val & MBOX_STATUS_ACK_MASK) { val 95 drivers/mailbox/mailbox-xgene-slimpro.c u32 val = readl(mb_chan->reg + REG_DB_STAT); val 97 drivers/mailbox/mailbox-xgene-slimpro.c if (val & MBOX_STATUS_AVAIL_MASK) { val 130 drivers/mailbox/mailbox-xgene-slimpro.c u32 val; val 144 drivers/mailbox/mailbox-xgene-slimpro.c val = readl(mb_chan->reg + REG_DB_STATMASK); val 145 drivers/mailbox/mailbox-xgene-slimpro.c val &= ~(MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK); val 146 drivers/mailbox/mailbox-xgene-slimpro.c writel(val, mb_chan->reg + REG_DB_STATMASK); val 154 drivers/mailbox/mailbox-xgene-slimpro.c u32 val; val 157 drivers/mailbox/mailbox-xgene-slimpro.c val = readl(mb_chan->reg + REG_DB_STATMASK); val 158 drivers/mailbox/mailbox-xgene-slimpro.c val |= (MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK); val 159 drivers/mailbox/mailbox-xgene-slimpro.c writel(val, mb_chan->reg + REG_DB_STATMASK); val 138 drivers/mailbox/omap-mailbox.c void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) val 140 drivers/mailbox/omap-mailbox.c __raw_writel(val, mdev->mbox_base + ofs); val 99 drivers/mailbox/pcc.c static int read_register(void __iomem *vaddr, u64 *val, unsigned int bit_width) val 105 drivers/mailbox/pcc.c *val = readb(vaddr); val 108 drivers/mailbox/pcc.c *val = readw(vaddr); val 111 drivers/mailbox/pcc.c *val = readl(vaddr); val 114 drivers/mailbox/pcc.c *val = readq(vaddr); val 125 drivers/mailbox/pcc.c static int write_register(void __iomem *vaddr, u64 val, unsigned int bit_width) val 131 drivers/mailbox/pcc.c writeb(val, vaddr); val 134 drivers/mailbox/pcc.c writew(val, vaddr); val 137 drivers/mailbox/pcc.c writel(val, vaddr); val 140 drivers/mailbox/pcc.c writeq(val, vaddr); val 50 drivers/mailbox/platform_mhu.c u32 val; val 52 drivers/mailbox/platform_mhu.c val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS); val 53 drivers/mailbox/platform_mhu.c if (!val) val 56 drivers/mailbox/platform_mhu.c mbox_chan_received_data(chan, (void *)&val); val 58 drivers/mailbox/platform_mhu.c writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS); val 66 drivers/mailbox/platform_mhu.c u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); val 68 drivers/mailbox/platform_mhu.c return (val == 0); val 84 drivers/mailbox/platform_mhu.c u32 val; val 87 drivers/mailbox/platform_mhu.c val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); val 88 drivers/mailbox/platform_mhu.c writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS); val 155 drivers/mailbox/ti-msgmgr.c u32 val; val 162 drivers/mailbox/ti-msgmgr.c val = readl(qinst->queue_state) & status_cnt_mask; val 163 drivers/mailbox/ti-msgmgr.c val >>= __ffs(status_cnt_mask); val 165 drivers/mailbox/ti-msgmgr.c return val; val 178 drivers/mailbox/ti-msgmgr.c u32 val; val 188 drivers/mailbox/ti-msgmgr.c val = readl(qinst->queue_state) & d->status_err_mask; val 190 drivers/mailbox/ti-msgmgr.c return val ? true : false; val 63 drivers/md/bcache/sysfs.h #define sysfs_hprint(file, val) \ val 66 drivers/md/bcache/sysfs.h ssize_t ret = bch_hprint(buf, val); \ val 429 drivers/md/bcache/util.h #define ewma_add(ewma, val, weight, factor) \ val 432 drivers/md/bcache/util.h (ewma) += (val) << factor; \ val 368 drivers/md/dm-crypt.c __be64 val; val 372 drivers/md/dm-crypt.c val = cpu_to_be64(((u64)dmreq->iv_sector << cc->iv_gen_private.benbi.shift) + 1); val 373 drivers/md/dm-crypt.c put_unaligned(val, (__be64 *)(iv + cc->iv_size - sizeof(u64))); val 2488 drivers/md/dm-crypt.c unsigned int opt_params, val; val 2516 drivers/md/dm-crypt.c else if (sscanf(opt_string, "integrity:%u:", &val) == 1) { val 2517 drivers/md/dm-crypt.c if (val == 0 || val > MAX_TAG_SIZE) { val 2521 drivers/md/dm-crypt.c cc->on_disk_tag_size = val; val 3657 drivers/md/dm-integrity.c unsigned val; val 3665 drivers/md/dm-integrity.c if (sscanf(opt_string, "journal_sectors:%u%c", &val, &dummy) == 1) val 3666 drivers/md/dm-integrity.c journal_sectors = val ? val : 1; val 3667 drivers/md/dm-integrity.c else if (sscanf(opt_string, "interleave_sectors:%u%c", &val, &dummy) == 1) val 3668 drivers/md/dm-integrity.c interleave_sectors = val; val 3669 drivers/md/dm-integrity.c else if (sscanf(opt_string, "buffer_sectors:%u%c", &val, &dummy) == 1) val 3670 drivers/md/dm-integrity.c buffer_sectors = val; val 3671 drivers/md/dm-integrity.c else if (sscanf(opt_string, "journal_watermark:%u%c", &val, &dummy) == 1 && val <= 100) val 3672 drivers/md/dm-integrity.c journal_watermark = val; val 3673 drivers/md/dm-integrity.c else if (sscanf(opt_string, "commit_time:%u%c", &val, &dummy) == 1) val 3674 drivers/md/dm-integrity.c sync_msec = val; val 3686 drivers/md/dm-integrity.c } else if (sscanf(opt_string, "block_size:%u%c", &val, &dummy) == 1) { val 3687 drivers/md/dm-integrity.c if (val < 1 << SECTOR_SHIFT || val 3688 drivers/md/dm-integrity.c val > MAX_SECTORS_PER_BLOCK << SECTOR_SHIFT || val 3689 drivers/md/dm-integrity.c (val & (val -1))) { val 3694 drivers/md/dm-integrity.c ic->sectors_per_block = val >> SECTOR_SHIFT; val 3697 drivers/md/dm-integrity.c } else if (sscanf(opt_string, "bitmap_flush_interval:%u%c", &val, &dummy) == 1) { val 3698 drivers/md/dm-integrity.c if (val >= (uint64_t)UINT_MAX * 1000 / HZ) { val 3702 drivers/md/dm-integrity.c ic->bitmap_flush_interval = msecs_to_jiffies(val); val 104 drivers/md/dm-io.c unsigned long val = (unsigned long)bio->bi_private; val 106 drivers/md/dm-io.c *io = (void *)(val & -(unsigned long)DM_IO_MAX_REGIONS); val 107 drivers/md/dm-io.c *region = val & (DM_IO_MAX_REGIONS - 1); val 480 drivers/md/dm-ioctl.c static inline size_t align_val(size_t val) val 482 drivers/md/dm-ioctl.c return (val + ALIGN_MASK) & ~ALIGN_MASK; val 37 drivers/md/dm-log-userspace-transfer.c .val = CN_VAL_DM_USERSPACE_LOG val 64 drivers/md/dm-log-userspace-transfer.c msg->id.val = ulog_cn_id.val; val 281 drivers/md/dm-writecache.c pfn.val++; val 5549 drivers/md/md.c static int add_named_array(const char *val, const struct kernel_param *kp) val 5558 drivers/md/md.c int len = strlen(val); val 5562 drivers/md/md.c while (len && val[len-1] == '\n') val 5566 drivers/md/md.c strlcpy(buf, val, len+1); val 9646 drivers/md/md.c static int set_ro(const char *val, const struct kernel_param *kp) val 9648 drivers/md/md.c return kstrtouint(val, 10, (unsigned int *)&start_readonly); val 627 drivers/md/persistent-data/dm-btree.c __le64 val; val 677 drivers/md/persistent-data/dm-btree.c val = cpu_to_le64(dm_block_location(left)); val 678 drivers/md/persistent-data/dm-btree.c __dm_bless_for_disk(&val); val 680 drivers/md/persistent-data/dm-btree.c memcpy_disk(value_ptr(pn, 0), &val, sizeof(__le64)); val 682 drivers/md/persistent-data/dm-btree.c val = cpu_to_le64(dm_block_location(right)); val 683 drivers/md/persistent-data/dm-btree.c __dm_bless_for_disk(&val); val 685 drivers/md/persistent-data/dm-btree.c memcpy_disk(value_ptr(pn, 1), &val, sizeof(__le64)); val 150 drivers/md/persistent-data/dm-space-map-common.c static void sm_set_bitmap(void *addr, unsigned b, unsigned val) val 157 drivers/md/persistent-data/dm-space-map-common.c if (val & 2) val 162 drivers/md/persistent-data/dm-space-map-common.c if (val & 1) val 500 drivers/media/cec/cec-pin.c u8 val = idx; val 503 drivers/media/cec/cec-pin.c val = pin->tx_msg.msg[idx]; val 504 drivers/media/cec/cec-pin.c v = val & (1 << (7 - (pin->tx_bit % 10))); val 162 drivers/media/common/b2c2/flexcop-reg.h #define flexcop_set_ibi_value(reg,attr,val) { \ val 164 drivers/media/common/b2c2/flexcop-reg.h v.reg.attr = val; \ val 1318 drivers/media/common/cx2341x.c return ctrl && ctrl->val != ctrl->cur.val; val 1324 drivers/media/common/cx2341x.c s32 val = ctrl->val; val 1329 drivers/media/common/cx2341x.c int b = val + 1; val 1330 drivers/media/common/cx2341x.c int gop = hdl->video_gop_size->val; val 1337 drivers/media/common/cx2341x.c hdl->video_gop_size->val = gop; val 1343 drivers/media/common/cx2341x.c hdl->video_encoding->val = val 1344 drivers/media/common/cx2341x.c (hdl->stream_type->val == V4L2_MPEG_STREAM_TYPE_MPEG1_SS || val 1345 drivers/media/common/cx2341x.c hdl->stream_type->val == V4L2_MPEG_STREAM_TYPE_MPEG1_VCD) ? val 1348 drivers/media/common/cx2341x.c if (hdl->video_encoding->val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1) val 1350 drivers/media/common/cx2341x.c hdl->video_bitrate_mode->val = val 1353 drivers/media/common/cx2341x.c if (hdl->video_bitrate_mode->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR && val 1354 drivers/media/common/cx2341x.c hdl->video_bitrate_peak->val < hdl->video_bitrate->val) val 1355 drivers/media/common/cx2341x.c hdl->video_bitrate_peak->val = hdl->video_bitrate->val; val 1372 drivers/media/common/cx2341x.c s32 val = ctrl->val; val 1379 drivers/media/common/cx2341x.c return hdl->ops->s_stream_vbi_fmt(hdl, val); val 1384 drivers/media/common/cx2341x.c CX2341X_ENC_SET_ASPECT_RATIO, 1, val + 1); val 1387 drivers/media/common/cx2341x.c return cx2341x_hdl_api(hdl, CX2341X_ENC_SET_GOP_CLOSURE, 1, val); val 1390 drivers/media/common/cx2341x.c return cx2341x_hdl_api(hdl, CX2341X_ENC_MUTE_AUDIO, 1, val); val 1394 drivers/media/common/cx2341x.c CX2341X_ENC_SET_FRAME_DROP_RATE, 1, val); val 1397 drivers/media/common/cx2341x.c return cx2341x_hdl_api(hdl, CX2341X_ENC_MISC, 2, 7, val); val 1401 drivers/media/common/cx2341x.c props = (hdl->audio_sampling_freq->val << 0) | val 1402 drivers/media/common/cx2341x.c (hdl->audio_mode->val << 8) | val 1403 drivers/media/common/cx2341x.c (hdl->audio_mode_extension->val << 10) | val 1404 drivers/media/common/cx2341x.c (hdl->audio_crc->val << 14); val 1405 drivers/media/common/cx2341x.c if (hdl->audio_emphasis->val == V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17) val 1408 drivers/media/common/cx2341x.c props |= hdl->audio_emphasis->val << 12; val 1410 drivers/media/common/cx2341x.c if (hdl->audio_encoding->val == V4L2_MPEG_AUDIO_ENCODING_AC3) { val 1416 drivers/media/common/cx2341x.c (hdl->audio_ac3_bitrate->val << 4) | val 1421 drivers/media/common/cx2341x.c ((3 - hdl->audio_encoding->val) << 2) | val 1422 drivers/media/common/cx2341x.c ((1 + hdl->audio_l2_bitrate->val) << 4); val 1431 drivers/media/common/cx2341x.c int is_ac3 = hdl->audio_encoding->val == val 1438 drivers/media/common/cx2341x.c hdl->audio_mode->val == V4L2_MPEG_AUDIO_MODE_JOINT_STEREO); val 1441 drivers/media/common/cx2341x.c return hdl->ops->s_audio_sampling_freq(hdl, hdl->audio_sampling_freq->val); val 1444 drivers/media/common/cx2341x.c return hdl->ops->s_audio_mode(hdl, hdl->audio_mode->val); val 1450 drivers/media/common/cx2341x.c hdl->video_gop_size->val, val 1451 drivers/media/common/cx2341x.c hdl->video_b_frames->val + 1); val 1456 drivers/media/common/cx2341x.c CX2341X_ENC_SET_STREAM_TYPE, 1, mpeg_stream_type[val]); val 1461 drivers/media/common/cx2341x.c hdl->video_bitrate_mode->val, val 1462 drivers/media/common/cx2341x.c hdl->video_bitrate->val, val 1463 drivers/media/common/cx2341x.c hdl->video_bitrate_peak->val / 400, 0, 0); val 1468 drivers/media/common/cx2341x.c hdl->video_encoding->val != V4L2_MPEG_VIDEO_ENCODING_MPEG_1); val 1470 drivers/media/common/cx2341x.c hdl->video_bitrate_mode->val != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR); val 1473 drivers/media/common/cx2341x.c return hdl->ops->s_video_encoding(hdl, hdl->video_encoding->val); val 1479 drivers/media/common/cx2341x.c hdl->video_mute->val | val 1480 drivers/media/common/cx2341x.c (hdl->video_mute_yuv->val << 8)); val 1487 drivers/media/common/cx2341x.c hdl->video_spatial_filter_mode->val | val 1488 drivers/media/common/cx2341x.c (hdl->video_temporal_filter_mode->val << 1), val 1489 drivers/media/common/cx2341x.c hdl->video_median_filter_type->val); val 1493 drivers/media/common/cx2341x.c active_filter = hdl->video_spatial_filter_mode->val != val 1498 drivers/media/common/cx2341x.c active_filter = hdl->video_temporal_filter_mode->val != val 1501 drivers/media/common/cx2341x.c active_filter = hdl->video_median_filter_type->val != val 1514 drivers/media/common/cx2341x.c hdl->video_luma_spatial_filter_type->val, val 1515 drivers/media/common/cx2341x.c hdl->video_chroma_spatial_filter_type->val); val 1520 drivers/media/common/cx2341x.c hdl->video_spatial_filter->val, val 1521 drivers/media/common/cx2341x.c hdl->video_temporal_filter->val); val 1526 drivers/media/common/cx2341x.c hdl->video_luma_median_filter_bottom->val, val 1527 drivers/media/common/cx2341x.c hdl->video_luma_median_filter_top->val, val 1528 drivers/media/common/cx2341x.c hdl->video_chroma_median_filter_bottom->val, val 1529 drivers/media/common/cx2341x.c hdl->video_chroma_median_filter_top->val); val 517 drivers/media/common/saa7146/saa7146_video.c u32 val; val 521 drivers/media/common/saa7146/saa7146_video.c val = saa7146_read(dev, BCS_CTRL); val 522 drivers/media/common/saa7146/saa7146_video.c val &= 0x00ffffff; val 523 drivers/media/common/saa7146/saa7146_video.c val |= (ctrl->val << 24); val 524 drivers/media/common/saa7146/saa7146_video.c saa7146_write(dev, BCS_CTRL, val); val 529 drivers/media/common/saa7146/saa7146_video.c val = saa7146_read(dev, BCS_CTRL); val 530 drivers/media/common/saa7146/saa7146_video.c val &= 0xff00ffff; val 531 drivers/media/common/saa7146/saa7146_video.c val |= (ctrl->val << 16); val 532 drivers/media/common/saa7146/saa7146_video.c saa7146_write(dev, BCS_CTRL, val); val 537 drivers/media/common/saa7146/saa7146_video.c val = saa7146_read(dev, BCS_CTRL); val 538 drivers/media/common/saa7146/saa7146_video.c val &= 0xffffff00; val 539 drivers/media/common/saa7146/saa7146_video.c val |= (ctrl->val << 0); val 540 drivers/media/common/saa7146/saa7146_video.c saa7146_write(dev, BCS_CTRL, val); val 548 drivers/media/common/saa7146/saa7146_video.c vv->hflip = ctrl->val; val 554 drivers/media/common/saa7146/saa7146_video.c vv->vflip = ctrl->val; val 140 drivers/media/dvb-frontends/af9013.c ret = regmap_bulk_write(state->regmap, 0xae00, coeff_lut[i].val, val 141 drivers/media/dvb-frontends/af9013.c sizeof(coeff_lut[i].val)); val 897 drivers/media/dvb-frontends/af9013.c tab[i].val); val 950 drivers/media/dvb-frontends/af9013.c tab[i].val); val 1280 drivers/media/dvb-frontends/af9013.c const u8 *val, int len, u8 lock) val 1301 drivers/media/dvb-frontends/af9013.c memcpy(&buf[3], val, len); val 1322 drivers/media/dvb-frontends/af9013.c u8 *val, int len, u8 lock) val 1336 drivers/media/dvb-frontends/af9013.c .buf = val, val 1370 drivers/media/dvb-frontends/af9013.c u8 *val = &((u8 *)data)[3]; val 1375 drivers/media/dvb-frontends/af9013.c ret = af9013_wregs(client, cmd, reg, val, len, lock); val 1381 drivers/media/dvb-frontends/af9013.c ret = af9013_wregs(client, cmd, reg, val, len, lock); val 1387 drivers/media/dvb-frontends/af9013.c ret = af9013_wregs(client, cmd, reg + i, val + i, 1, val 1409 drivers/media/dvb-frontends/af9013.c u8 *val = &((u8 *)val_buf)[0]; val 1420 drivers/media/dvb-frontends/af9013.c ret = af9013_rregs(client, cmd, reg + i, val + i, 1, val 27 drivers/media/dvb-frontends/af9013_priv.h u8 val; val 33 drivers/media/dvb-frontends/af9013_priv.h u8 val[24]; val 48 drivers/media/dvb-frontends/af9033.c buf[j] = tab[i].val; val 145 drivers/media/dvb-frontends/af9033.c tab[i].val); val 404 drivers/media/dvb-frontends/af9033.c ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val, val 405 drivers/media/dvb-frontends/af9033.c sizeof(coeff_lut[i].val)); val 21 drivers/media/dvb-frontends/af9033_priv.h u8 val; val 26 drivers/media/dvb-frontends/af9033_priv.h u8 val; val 33 drivers/media/dvb-frontends/af9033_priv.h u8 val[36]; val 42 drivers/media/dvb-frontends/af9033_priv.h u32 val; val 147 drivers/media/dvb-frontends/ascot2e.c static int ascot2e_write_reg(struct ascot2e_priv *priv, u8 reg, u8 val) val 149 drivers/media/dvb-frontends/ascot2e.c u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ val 155 drivers/media/dvb-frontends/ascot2e.c u8 reg, u8 *val, u32 len) val 168 drivers/media/dvb-frontends/ascot2e.c .buf = val, val 190 drivers/media/dvb-frontends/ascot2e.c ascot2e_i2c_debug(priv, reg, 0, val, len); val 194 drivers/media/dvb-frontends/ascot2e.c static int ascot2e_read_reg(struct ascot2e_priv *priv, u8 reg, u8 *val) val 196 drivers/media/dvb-frontends/ascot2e.c return ascot2e_read_regs(priv, reg, val, 1); val 90 drivers/media/dvb-frontends/atbm8830.c u32 val; val 96 drivers/media/dvb-frontends/atbm8830.c val = t; val 98 drivers/media/dvb-frontends/atbm8830.c atbm8830_write_reg(priv, REG_OSC_CLK, val); val 99 drivers/media/dvb-frontends/atbm8830.c atbm8830_write_reg(priv, REG_OSC_CLK + 1, val >> 8); val 100 drivers/media/dvb-frontends/atbm8830.c atbm8830_write_reg(priv, REG_OSC_CLK + 2, val >> 16); val 110 drivers/media/dvb-frontends/atbm8830.c u32 val; val 119 drivers/media/dvb-frontends/atbm8830.c val = t; val 122 drivers/media/dvb-frontends/atbm8830.c atbm8830_write_reg(priv, REG_IF_FREQ, val); val 123 drivers/media/dvb-frontends/atbm8830.c atbm8830_write_reg(priv, REG_IF_FREQ+1, val >> 8); val 124 drivers/media/dvb-frontends/atbm8830.c atbm8830_write_reg(priv, REG_IF_FREQ+2, val >> 16); val 132 drivers/media/dvb-frontends/au8522_common.c u8 val; val 139 drivers/media/dvb-frontends/au8522_common.c val = au8522_readreg(state, 0x4000 | val 143 drivers/media/dvb-frontends/au8522_common.c val &= ~((led_config->gpio_output_enable >> 8) & 0xff); val 144 drivers/media/dvb-frontends/au8522_common.c val |= (led_config->gpio_output_enable & 0xff); val 147 drivers/media/dvb-frontends/au8522_common.c val &= ~((led_config->gpio_output_disable >> 8) & 0xff); val 148 drivers/media/dvb-frontends/au8522_common.c val |= (led_config->gpio_output_disable & 0xff); val 151 drivers/media/dvb-frontends/au8522_common.c (led_config->gpio_output & ~0xc000), val); val 179 drivers/media/dvb-frontends/au8522_common.c u8 val; val 185 drivers/media/dvb-frontends/au8522_common.c val = au8522_readreg(state, 0x4000 | val 190 drivers/media/dvb-frontends/au8522_common.c val &= ~led_config->led_states[i]; val 194 drivers/media/dvb-frontends/au8522_common.c val |= led_config->led_states[led]; val 196 drivers/media/dvb-frontends/au8522_common.c val |= val 200 drivers/media/dvb-frontends/au8522_common.c (led_config->gpio_leds & ~0xc000), val); val 444 drivers/media/dvb-frontends/au8522_decoder.c ctrl->val - 128); val 448 drivers/media/dvb-frontends/au8522_decoder.c ctrl->val); val 452 drivers/media/dvb-frontends/au8522_decoder.c ctrl->val); val 454 drivers/media/dvb-frontends/au8522_decoder.c ctrl->val); val 458 drivers/media/dvb-frontends/au8522_decoder.c ctrl->val >> 8); val 460 drivers/media/dvb-frontends/au8522_decoder.c ctrl->val & 0xFF); val 477 drivers/media/dvb-frontends/au8522_decoder.c reg->val = au8522_readreg(state, reg->reg & 0xffff); val 486 drivers/media/dvb-frontends/au8522_decoder.c au8522_writereg(state, reg->reg, reg->val & 0xff); val 612 drivers/media/dvb-frontends/au8522_decoder.c int val = 0; val 629 drivers/media/dvb-frontends/au8522_decoder.c val = V4L2_TUNER_SUB_MONO; val 630 drivers/media/dvb-frontends/au8522_decoder.c vt->rxsubchans = val; val 28 drivers/media/dvb-frontends/au8522_dig.c u16 val; val 222 drivers/media/dvb-frontends/au8522_dig.c if (mse < tab[i].val) { val 94 drivers/media/dvb-frontends/cx22700.c u8 val; val 102 drivers/media/dvb-frontends/cx22700.c val = cx22700_readreg (state, 0x09); val 103 drivers/media/dvb-frontends/cx22700.c return cx22700_writereg (state, 0x09, val | 0x01); val 105 drivers/media/dvb-frontends/cx22700.c val = cx22700_readreg (state, 0x09); val 106 drivers/media/dvb-frontends/cx22700.c return cx22700_writereg (state, 0x09, val & 0xfe); val 117 drivers/media/dvb-frontends/cx22700.c u8 val; val 155 drivers/media/dvb-frontends/cx22700.c val = qam_tab[p->modulation - QPSK]; val 156 drivers/media/dvb-frontends/cx22700.c val |= p->hierarchy - HIERARCHY_NONE; val 158 drivers/media/dvb-frontends/cx22700.c cx22700_writereg (state, 0x04, val); val 163 drivers/media/dvb-frontends/cx22700.c val = fec_tab[p->code_rate_HP - FEC_1_2] << 3; val 164 drivers/media/dvb-frontends/cx22700.c val |= fec_tab[p->code_rate_LP - FEC_1_2]; val 166 drivers/media/dvb-frontends/cx22700.c cx22700_writereg (state, 0x05, val); val 168 drivers/media/dvb-frontends/cx22700.c val = (p->guard_interval - GUARD_INTERVAL_1_32) << 2; val 169 drivers/media/dvb-frontends/cx22700.c val |= p->transmission_mode - TRANSMISSION_MODE_2K; val 171 drivers/media/dvb-frontends/cx22700.c cx22700_writereg (state, 0x06, val); val 186 drivers/media/dvb-frontends/cx22700.c u8 val; val 193 drivers/media/dvb-frontends/cx22700.c val = cx22700_readreg (state, 0x01); val 195 drivers/media/dvb-frontends/cx22700.c if ((val & 0x7) > 4) val 198 drivers/media/dvb-frontends/cx22700.c p->hierarchy = HIERARCHY_NONE + (val & 0x7); val 200 drivers/media/dvb-frontends/cx22700.c if (((val >> 3) & 0x3) > 2) val 203 drivers/media/dvb-frontends/cx22700.c p->modulation = qam_tab[(val >> 3) & 0x3]; val 205 drivers/media/dvb-frontends/cx22700.c val = cx22700_readreg (state, 0x02); val 207 drivers/media/dvb-frontends/cx22700.c if (((val >> 3) & 0x07) > 4) val 210 drivers/media/dvb-frontends/cx22700.c p->code_rate_HP = fec_tab[(val >> 3) & 0x07]; val 212 drivers/media/dvb-frontends/cx22700.c if ((val & 0x07) > 4) val 215 drivers/media/dvb-frontends/cx22700.c p->code_rate_LP = fec_tab[val & 0x07]; val 217 drivers/media/dvb-frontends/cx22700.c val = cx22700_readreg (state, 0x03); val 219 drivers/media/dvb-frontends/cx22700.c p->guard_interval = GUARD_INTERVAL_1_32 + ((val >> 6) & 0x3); val 220 drivers/media/dvb-frontends/cx22700.c p->transmission_mode = TRANSMISSION_MODE_2K + ((val >> 5) & 0x1); val 117 drivers/media/dvb-frontends/cx22702.c u8 val; val 119 drivers/media/dvb-frontends/cx22702.c val = cx22702_readreg(state, 0x0C); val 124 drivers/media/dvb-frontends/cx22702.c val |= 0x01; val 127 drivers/media/dvb-frontends/cx22702.c val &= 0xfe; val 132 drivers/media/dvb-frontends/cx22702.c return cx22702_writereg(state, 0x0C, val); val 139 drivers/media/dvb-frontends/cx22702.c u8 val; val 145 drivers/media/dvb-frontends/cx22702.c val = cx22702_readreg(state, 0x01); val 146 drivers/media/dvb-frontends/cx22702.c switch ((val & 0x18) >> 3) { val 157 drivers/media/dvb-frontends/cx22702.c switch (val & 0x07) { val 173 drivers/media/dvb-frontends/cx22702.c val = cx22702_readreg(state, 0x02); val 174 drivers/media/dvb-frontends/cx22702.c switch ((val & 0x38) >> 3) { val 191 drivers/media/dvb-frontends/cx22702.c switch (val & 0x07) { val 209 drivers/media/dvb-frontends/cx22702.c val = cx22702_readreg(state, 0x03); val 210 drivers/media/dvb-frontends/cx22702.c switch ((val & 0x0c) >> 2) { val 224 drivers/media/dvb-frontends/cx22702.c switch (val & 0x03) { val 239 drivers/media/dvb-frontends/cx22702.c u8 val; val 242 drivers/media/dvb-frontends/cx22702.c val = cx22702_readreg(state, 0x0D); val 244 drivers/media/dvb-frontends/cx22702.c val &= 0xfe; val 246 drivers/media/dvb-frontends/cx22702.c val |= 0x01; val 247 drivers/media/dvb-frontends/cx22702.c return cx22702_writereg(state, 0x0D, val); val 254 drivers/media/dvb-frontends/cx22702.c u8 val; val 267 drivers/media/dvb-frontends/cx22702.c val = cx22702_readreg(state, 0x0C) & 0xcf; val 270 drivers/media/dvb-frontends/cx22702.c val |= 0x20; val 273 drivers/media/dvb-frontends/cx22702.c val |= 0x10; val 281 drivers/media/dvb-frontends/cx22702.c cx22702_writereg(state, 0x0C, val); val 309 drivers/media/dvb-frontends/cx22702.c val = 0x00; val 312 drivers/media/dvb-frontends/cx22702.c val = 0x08; val 315 drivers/media/dvb-frontends/cx22702.c val = 0x10; val 325 drivers/media/dvb-frontends/cx22702.c val |= 0x01; val 328 drivers/media/dvb-frontends/cx22702.c val |= 0x02; val 331 drivers/media/dvb-frontends/cx22702.c val |= 0x03; val 337 drivers/media/dvb-frontends/cx22702.c cx22702_writereg(state, 0x06, val); val 342 drivers/media/dvb-frontends/cx22702.c val = 0x00; val 345 drivers/media/dvb-frontends/cx22702.c val = 0x08; val 348 drivers/media/dvb-frontends/cx22702.c val = 0x10; val 351 drivers/media/dvb-frontends/cx22702.c val = 0x18; val 354 drivers/media/dvb-frontends/cx22702.c val = 0x20; val 365 drivers/media/dvb-frontends/cx22702.c val |= 0x01; val 368 drivers/media/dvb-frontends/cx22702.c val |= 0x02; val 371 drivers/media/dvb-frontends/cx22702.c val |= 0x03; val 374 drivers/media/dvb-frontends/cx22702.c val |= 0x04; val 380 drivers/media/dvb-frontends/cx22702.c cx22702_writereg(state, 0x07, val); val 384 drivers/media/dvb-frontends/cx22702.c val = 0x00; val 387 drivers/media/dvb-frontends/cx22702.c val = 0x04; val 390 drivers/media/dvb-frontends/cx22702.c val = 0x08; val 393 drivers/media/dvb-frontends/cx22702.c val = 0x0c; val 403 drivers/media/dvb-frontends/cx22702.c val |= 0x1; val 409 drivers/media/dvb-frontends/cx22702.c cx22702_writereg(state, 0x08, val); val 23 drivers/media/dvb-frontends/cx24110.h static inline int cx24110_pll_write(struct dvb_frontend *fe, u32 val) val 26 drivers/media/dvb-frontends/cx24110.h (u8)((val >> 24) & 0xff), val 27 drivers/media/dvb-frontends/cx24110.h (u8)((val >> 16) & 0xff), val 28 drivers/media/dvb-frontends/cx24110.h (u8)((val >> 8) & 0xff) val 364 drivers/media/dvb-frontends/cx24116.c u8 val; /* Passed to the firmware to indicate mode selection */ val 435 drivers/media/dvb-frontends/cx24116.c state->dnxt.fec_val = CX24116_MODFEC_MODES[ret].val; val 215 drivers/media/dvb-frontends/cx24117.c u8 val; /* Passed to the firmware to indicate mode selection */ val 414 drivers/media/dvb-frontends/cx24117.c state->dnxt.fec_val = cx24117_modfec_modes[ret].val; val 878 drivers/media/dvb-frontends/cx24117.c u8 val, reg = (state->demod == 0) ? CX24117_REG_QSTATUS0 : val 886 drivers/media/dvb-frontends/cx24117.c val = cx24117_readreg(state, reg) & 0x01; val 887 drivers/media/dvb-frontends/cx24117.c if (val != 0) val 763 drivers/media/dvb-frontends/cx24120.c u8 val; val 810 drivers/media/dvb-frontends/cx24120.c if (modfec_lookup_table[idx].val != fec) val 1011 drivers/media/dvb-frontends/cx24120.c u8 val; val 1061 drivers/media/dvb-frontends/cx24120.c state->dnxt.fec_val = modfec_table[idx].val; val 276 drivers/media/dvb-frontends/cx24123.c #define cx24123_writereg(state, reg, val) \ val 277 drivers/media/dvb-frontends/cx24123.c cx24123_i2c_writereg(state, state->config->demod_address, reg, val) val 310 drivers/media/dvb-frontends/cx24123.c u8 val; val 312 drivers/media/dvb-frontends/cx24123.c val = cx24123_readreg(state, 0x1b) >> 7; val 314 drivers/media/dvb-frontends/cx24123.c if (val == 0) { val 638 drivers/media/dvb-frontends/cx24123.c u8 val; val 656 drivers/media/dvb-frontends/cx24123.c val = cx24123_readreg(state, 0x28) & ~0x3; val 658 drivers/media/dvb-frontends/cx24123.c cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); val 713 drivers/media/dvb-frontends/cx24123.c u8 val; val 715 drivers/media/dvb-frontends/cx24123.c val = cx24123_readreg(state, 0x29) & ~0x40; val 720 drivers/media/dvb-frontends/cx24123.c return cx24123_writereg(state, 0x29, val & 0x7f); val 723 drivers/media/dvb-frontends/cx24123.c return cx24123_writereg(state, 0x29, val | 0x80); val 752 drivers/media/dvb-frontends/cx24123.c int i, val, tone; val 770 drivers/media/dvb-frontends/cx24123.c val = cx24123_readreg(state, 0x29); val 771 drivers/media/dvb-frontends/cx24123.c cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | val 788 drivers/media/dvb-frontends/cx24123.c int val, tone; val 803 drivers/media/dvb-frontends/cx24123.c val = cx24123_readreg(state, 0x29); val 805 drivers/media/dvb-frontends/cx24123.c cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); val 807 drivers/media/dvb-frontends/cx24123.c cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); val 959 drivers/media/dvb-frontends/cx24123.c u8 val; val 964 drivers/media/dvb-frontends/cx24123.c val = cx24123_readreg(state, 0x29) & ~0x40; val 969 drivers/media/dvb-frontends/cx24123.c return cx24123_writereg(state, 0x29, val | 0x10); val 972 drivers/media/dvb-frontends/cx24123.c return cx24123_writereg(state, 0x29, val & 0xef); val 86 drivers/media/dvb-frontends/cxd2099.c static int read_reg(struct cxd *ci, u8 reg, u8 *val) val 88 drivers/media/dvb-frontends/cxd2099.c return read_block(ci, reg, val, 1); val 117 drivers/media/dvb-frontends/cxd2099.c static int read_io(struct cxd *ci, u16 address, unsigned int *val) val 124 drivers/media/dvb-frontends/cxd2099.c status = regmap_read(ci->regmap, 3, val); val 128 drivers/media/dvb-frontends/cxd2099.c static int write_io(struct cxd *ci, u16 address, u8 val) val 135 drivers/media/dvb-frontends/cxd2099.c status = regmap_write(ci->regmap, 3, val); val 139 drivers/media/dvb-frontends/cxd2099.c static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask) val 151 drivers/media/dvb-frontends/cxd2099.c ci->regs[reg] = (ci->regs[reg] & (~mask)) | val; val 159 drivers/media/dvb-frontends/cxd2099.c static int write_reg(struct cxd *ci, u8 reg, u8 val) val 161 drivers/media/dvb-frontends/cxd2099.c return write_regm(ci, reg, val, 0xff); val 389 drivers/media/dvb-frontends/cxd2099.c u8 val; val 393 drivers/media/dvb-frontends/cxd2099.c read_pccard(ci, address, &val, 1); val 395 drivers/media/dvb-frontends/cxd2099.c return val; val 414 drivers/media/dvb-frontends/cxd2099.c unsigned int val; val 418 drivers/media/dvb-frontends/cxd2099.c read_io(ci, address, &val); val 420 drivers/media/dvb-frontends/cxd2099.c return val; val 619 drivers/media/dvb-frontends/cxd2099.c unsigned int val; val 637 drivers/media/dvb-frontends/cxd2099.c ret = regmap_read(ci->regmap, 0x00, &val); val 17 drivers/media/dvb-frontends/cxd2820r_core.c unsigned int i, reg, mask, val; val 29 drivers/media/dvb-frontends/cxd2820r_core.c val = tab[i].val; val 33 drivers/media/dvb-frontends/cxd2820r_core.c ret = regmap_write(regmap, reg, val); val 35 drivers/media/dvb-frontends/cxd2820r_core.c ret = regmap_write_bits(regmap, reg, mask, val); val 422 drivers/media/dvb-frontends/cxd2820r_core.c int val) val 428 drivers/media/dvb-frontends/cxd2820r_core.c dev_dbg(&client->dev, "nr=%u val=%d\n", nr, val); val 431 drivers/media/dvb-frontends/cxd2820r_core.c gpio[nr] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | (val << 2); val 436 drivers/media/dvb-frontends/cxd2820r_core.c static void cxd2820r_gpio_set(struct gpio_chip *chip, unsigned nr, int val) val 442 drivers/media/dvb-frontends/cxd2820r_core.c dev_dbg(&client->dev, "nr=%u val=%d\n", nr, val); val 445 drivers/media/dvb-frontends/cxd2820r_core.c gpio[nr] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | (val << 2); val 22 drivers/media/dvb-frontends/cxd2820r_priv.h u8 val; val 62 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, val 65 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, val 68 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, val 71 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, val 74 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val); val 76 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val); val 250 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 val) val 252 drivers/media/dvb-frontends/cxd2841er.c u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ val 258 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 *val, u32 len) val 273 drivers/media/dvb-frontends/cxd2841er.c .buf = val, val 286 drivers/media/dvb-frontends/cxd2841er.c cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len); val 291 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 *val) val 293 drivers/media/dvb-frontends/cxd2841er.c return cxd2841er_read_regs(priv, addr, reg, val, 1); val 101 drivers/media/dvb-frontends/dib0070.c static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val) val 110 drivers/media/dvb-frontends/dib0070.c state->i2c_write_buffer[1] = val >> 8; val 111 drivers/media/dvb-frontends/dib0070.c state->i2c_write_buffer[2] = val & 0xff; val 232 drivers/media/dvb-frontends/dib0090.c static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) val 242 drivers/media/dvb-frontends/dib0090.c state->i2c_write_buffer[1] = val >> 8; val 243 drivers/media/dvb-frontends/dib0090.c state->i2c_write_buffer[2] = val & 0xff; val 288 drivers/media/dvb-frontends/dib0090.c static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val) val 297 drivers/media/dvb-frontends/dib0090.c state->i2c_write_buffer[0] = val >> 8; val 298 drivers/media/dvb-frontends/dib0090.c state->i2c_write_buffer[1] = val & 0xff; val 860 drivers/media/dvb-frontends/dib0090.c static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val) val 866 drivers/media/dvb-frontends/dib0090.c if (val > slopes[i].range) val 869 drivers/media/dvb-frontends/dib0090.c rest = val; val 871 drivers/media/dvb-frontends/dib0090.c val -= rest; val 1657 drivers/media/dvb-frontends/dib0090.c u16 *val; val 1660 drivers/media/dvb-frontends/dib0090.c val = &state->bb7; val 1662 drivers/media/dvb-frontends/dib0090.c val = &state->bb6; val 1664 drivers/media/dvb-frontends/dib0090.c *val &= ~(0x1f << state->dc->offset); val 1665 drivers/media/dvb-frontends/dib0090.c *val |= state->step << state->dc->offset; val 1667 drivers/media/dvb-frontends/dib0090.c dib0090_write_reg(state, state->dc->addr, *val); val 2181 drivers/media/dvb-frontends/dib0090.c s16 val; val 2202 drivers/media/dvb-frontends/dib0090.c val = dib0090_get_slow_adc_val(state); val 2203 drivers/media/dvb-frontends/dib0090.c state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55; val 69 drivers/media/dvb-frontends/dib3000mb.c static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val) val 73 drivers/media/dvb-frontends/dib3000mb.c (val >> 8) & 0xff, val & 0xff, val 78 drivers/media/dvb-frontends/dib3000mb.c deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val); val 16 drivers/media/dvb-frontends/dib3000mb_priv.h #define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \ val 17 drivers/media/dvb-frontends/dib3000mb_priv.h { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; } val 26 drivers/media/dvb-frontends/dib3000mb_priv.h #define set_or(reg,val) wr(reg,rd(reg) | val) val 28 drivers/media/dvb-frontends/dib3000mb_priv.h #define set_and(reg,val) wr(reg,rd(reg) & val) val 83 drivers/media/dvb-frontends/dib3000mc.c static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val) val 97 drivers/media/dvb-frontends/dib3000mc.c b[2] = val >> 8; val 98 drivers/media/dvb-frontends/dib3000mc.c b[3] = val; val 808 drivers/media/dvb-frontends/dib3000mc.c u16 val = dib3000mc_read_word(state, 392); val 809 drivers/media/dvb-frontends/dib3000mc.c *strength = 65535 - val; val 107 drivers/media/dvb-frontends/dib7000m.c static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val) val 118 drivers/media/dvb-frontends/dib7000m.c state->i2c_write_buffer[2] = (val >> 8) & 0xff; val 119 drivers/media/dvb-frontends/dib7000m.c state->i2c_write_buffer[3] = val & 0xff; val 1301 drivers/media/dvb-frontends/dib7000m.c u16 val = dib7000m_read_word(state, 390); val 1302 drivers/media/dvb-frontends/dib7000m.c *strength = 65535 - val; val 1335 drivers/media/dvb-frontends/dib7000m.c u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef; val 1336 drivers/media/dvb-frontends/dib7000m.c val |= (onoff & 0x1) << 4; val 1338 drivers/media/dvb-frontends/dib7000m.c return dib7000m_write_word(state, 294 + state->reg_offs, val); val 130 drivers/media/dvb-frontends/dib7000p.c static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val) val 141 drivers/media/dvb-frontends/dib7000p.c state->i2c_write_buffer[2] = (val >> 8) & 0xff; val 142 drivers/media/dvb-frontends/dib7000p.c state->i2c_write_buffer[3] = val & 0xff; val 541 drivers/media/dvb-frontends/dib7000p.c static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val) val 550 drivers/media/dvb-frontends/dib7000p.c st->gpio_val |= (val & 0x01) << num; /* set the new value */ val 556 drivers/media/dvb-frontends/dib7000p.c static int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val) val 559 drivers/media/dvb-frontends/dib7000p.c return dib7000p_cfg_gpio(state, num, dir, val); val 1616 drivers/media/dvb-frontends/dib7000p.c u16 val = dib7000p_read_word(state, 394); val 1617 drivers/media/dvb-frontends/dib7000p.c *strength = 65535 - val; val 1624 drivers/media/dvb-frontends/dib7000p.c u16 val; val 1628 drivers/media/dvb-frontends/dib7000p.c val = dib7000p_read_word(state, 479); val 1629 drivers/media/dvb-frontends/dib7000p.c noise_mant = (val >> 4) & 0xff; val 1630 drivers/media/dvb-frontends/dib7000p.c noise_exp = ((val & 0xf) << 2); val 1631 drivers/media/dvb-frontends/dib7000p.c val = dib7000p_read_word(state, 480); val 1632 drivers/media/dvb-frontends/dib7000p.c noise_exp += ((val >> 14) & 0x3); val 1636 drivers/media/dvb-frontends/dib7000p.c signal_mant = (val >> 6) & 0xFF; val 1637 drivers/media/dvb-frontends/dib7000p.c signal_exp = (val & 0x3F); val 1901 drivers/media/dvb-frontends/dib7000p.c u32 time_us = 0, val, snr; val 1908 drivers/media/dvb-frontends/dib7000p.c val = strength; val 1909 drivers/media/dvb-frontends/dib7000p.c db = interpolate_value(val, val 1943 drivers/media/dvb-frontends/dib7000p.c dib7000p_read_unc_blocks(demod, &val); val 1944 drivers/media/dvb-frontends/dib7000p.c ucb = val - state->old_ucb; val 1945 drivers/media/dvb-frontends/dib7000p.c if (val < state->old_ucb) val 1972 drivers/media/dvb-frontends/dib7000p.c dib7000p_read_ber(demod, &val); val 1974 drivers/media/dvb-frontends/dib7000p.c c->post_bit_error.stat[0].uvalue += val; val 1982 drivers/media/dvb-frontends/dib7000p.c dib7000p_read_unc_blocks(demod, &val); val 1985 drivers/media/dvb-frontends/dib7000p.c c->block_error.stat[0].uvalue += val; val 2070 drivers/media/dvb-frontends/dib7000p.c u16 val = dib7000p_read_word(state, 235) & 0xffef; val 2071 drivers/media/dvb-frontends/dib7000p.c val |= (onoff & 0x1) << 4; val 2073 drivers/media/dvb-frontends/dib7000p.c return dib7000p_write_word(state, 235, val); val 54 drivers/media/dvb-frontends/dib7000p.h int (*set_gpio)(struct dvb_frontend *demod, u8 num, u8 dir, u8 val); val 229 drivers/media/dvb-frontends/dib8000.c static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) val 242 drivers/media/dvb-frontends/dib8000.c msg.buf[2] = (val >> 8) & 0xff; val 243 drivers/media/dvb-frontends/dib8000.c msg.buf[3] = val & 0xff; val 251 drivers/media/dvb-frontends/dib8000.c static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) val 262 drivers/media/dvb-frontends/dib8000.c state->i2c_write_buffer[2] = (val >> 8) & 0xff; val 263 drivers/media/dvb-frontends/dib8000.c state->i2c_write_buffer[3] = val & 0xff; val 836 drivers/media/dvb-frontends/dib8000.c static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val) val 845 drivers/media/dvb-frontends/dib8000.c st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */ val 853 drivers/media/dvb-frontends/dib8000.c static int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val) val 856 drivers/media/dvb-frontends/dib8000.c return dib8000_cfg_gpio(state, num, dir, val); val 1925 drivers/media/dvb-frontends/dib8000.c s32 val; val 1927 drivers/media/dvb-frontends/dib8000.c val = dib8000_read32(state, 384); val 1929 drivers/media/dvb-frontends/dib8000.c tmp_val = val; val 1932 drivers/media/dvb-frontends/dib8000.c mant = (val * 1000 / (1<<exp)); val 1934 drivers/media/dvb-frontends/dib8000.c val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); val 1935 drivers/media/dvb-frontends/dib8000.c val = (val*256)/1000; val 1937 drivers/media/dvb-frontends/dib8000.c return val; val 1943 drivers/media/dvb-frontends/dib8000.c int val = 0; val 1947 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 403); val 1950 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 404); val 1953 drivers/media/dvb-frontends/dib8000.c if (val & 0x200) val 1954 drivers/media/dvb-frontends/dib8000.c val -= 1024; val 1956 drivers/media/dvb-frontends/dib8000.c return val; val 3393 drivers/media/dvb-frontends/dib8000.c u16 i, val = 0; val 3437 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 572); val 3439 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 570); val 3440 drivers/media/dvb-frontends/dib8000.c c->inversion = (val & 0x40) >> 6; val 3441 drivers/media/dvb-frontends/dib8000.c switch ((val & 0x30) >> 4) { val 3457 drivers/media/dvb-frontends/dib8000.c switch (val & 0x3) { val 3476 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 505); val 3477 drivers/media/dvb-frontends/dib8000.c c->isdbt_partial_reception = val & 1; val 3483 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 493 + i) & 0x0f; val 3484 drivers/media/dvb-frontends/dib8000.c c->layer[i].segment_count = val; val 3486 drivers/media/dvb-frontends/dib8000.c if (val == 0 || val > 13) val 3495 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 499 + i) & 0x3; val 3497 drivers/media/dvb-frontends/dib8000.c if (val == 3) val 3498 drivers/media/dvb-frontends/dib8000.c val = 4; val 3499 drivers/media/dvb-frontends/dib8000.c c->layer[i].interleaving = val; val 3504 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 481 + i); val 3505 drivers/media/dvb-frontends/dib8000.c switch (val & 0x7) { val 3533 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 487 + i); val 3534 drivers/media/dvb-frontends/dib8000.c switch (val & 0x3) { val 3815 drivers/media/dvb-frontends/dib8000.c u16 val; val 3819 drivers/media/dvb-frontends/dib8000.c state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); val 3820 drivers/media/dvb-frontends/dib8000.c if (val > 65535 - *strength) val 3823 drivers/media/dvb-frontends/dib8000.c *strength += val; val 3826 drivers/media/dvb-frontends/dib8000.c val = 65535 - dib8000_read_word(state, 390); val 3827 drivers/media/dvb-frontends/dib8000.c if (val > 65535 - *strength) val 3830 drivers/media/dvb-frontends/dib8000.c *strength += val; val 3838 drivers/media/dvb-frontends/dib8000.c u16 val; val 3841 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 542); val 3843 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 544); val 3844 drivers/media/dvb-frontends/dib8000.c n = (val >> 6) & 0xff; val 3845 drivers/media/dvb-frontends/dib8000.c exp = (val & 0x3f); val 3851 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 543); val 3853 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, 545); val 3854 drivers/media/dvb-frontends/dib8000.c s = (val >> 6) & 0xff; val 3855 drivers/media/dvb-frontends/dib8000.c exp = (val & 0x3f); val 4103 drivers/media/dvb-frontends/dib8000.c u32 time_us = 0, snr, val; val 4110 drivers/media/dvb-frontends/dib8000.c val = strength; val 4111 drivers/media/dvb-frontends/dib8000.c db = interpolate_value(val, val 4153 drivers/media/dvb-frontends/dib8000.c dib8000_read_unc_blocks(fe, &val); val 4154 drivers/media/dvb-frontends/dib8000.c if (val < state->init_ucb) val 4158 drivers/media/dvb-frontends/dib8000.c c->block_error.stat[0].uvalue = val + state->init_ucb; val 4181 drivers/media/dvb-frontends/dib8000.c dib8000_read_ber(fe, &val); val 4183 drivers/media/dvb-frontends/dib8000.c c->post_bit_error.stat[0].uvalue += val; val 4211 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, per_layer_regs[i].ber); val 4213 drivers/media/dvb-frontends/dib8000.c c->post_bit_error.stat[1 + i].uvalue += val; val 4220 drivers/media/dvb-frontends/dib8000.c val = dib8000_read_word(state, per_layer_regs[i].per); val 4223 drivers/media/dvb-frontends/dib8000.c c->block_error.stat[1 + i].uvalue += val; val 4372 drivers/media/dvb-frontends/dib8000.c u16 val = dib8000_read_word(st, 299) & 0xffef; val 4373 drivers/media/dvb-frontends/dib8000.c val |= (onoff & 0x1) << 4; val 4376 drivers/media/dvb-frontends/dib8000.c return dib8000_write_word(st, 299, val); val 47 drivers/media/dvb-frontends/dib8000.h int (*set_gpio)(struct dvb_frontend *fe, u8 num, u8 dir, u8 val); val 361 drivers/media/dvb-frontends/dib9000.c static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) val 370 drivers/media/dvb-frontends/dib9000.c i2c->i2c_write_buffer[2] = (val >> 8) & 0xff; val 371 drivers/media/dvb-frontends/dib9000.c i2c->i2c_write_buffer[3] = val & 0xff; val 376 drivers/media/dvb-frontends/dib9000.c static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val) val 378 drivers/media/dvb-frontends/dib9000.c u8 b[2] = { val >> 8, val & 0xff }; val 382 drivers/media/dvb-frontends/dib9000.c static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute) val 384 drivers/media/dvb-frontends/dib9000.c u8 b[2] = { val >> 8, val & 0xff }; val 1754 drivers/media/dvb-frontends/dib9000.c static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val) val 1763 drivers/media/dvb-frontends/dib9000.c st->gpio_val |= (val & 0x01) << num; /* set the new value */ val 1771 drivers/media/dvb-frontends/dib9000.c int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val) val 1774 drivers/media/dvb-frontends/dib9000.c return dib9000_cfg_gpio(state, num, dir, val); val 1781 drivers/media/dvb-frontends/dib9000.c u16 val; val 1798 drivers/media/dvb-frontends/dib9000.c val = dib9000_read_word(state, 294 + 1) & 0xffef; val 1799 drivers/media/dvb-frontends/dib9000.c val |= (onoff & 0x1) << 4; val 1802 drivers/media/dvb-frontends/dib9000.c ret = dib9000_write_word(state, 294 + 1, val); val 2240 drivers/media/dvb-frontends/dib9000.c u16 val; val 2249 drivers/media/dvb-frontends/dib9000.c state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); val 2250 drivers/media/dvb-frontends/dib9000.c if (val > 65535 - *strength) val 2253 drivers/media/dvb-frontends/dib9000.c *strength += val; val 2269 drivers/media/dvb-frontends/dib9000.c val = 65535 - c[4]; val 2270 drivers/media/dvb-frontends/dib9000.c if (val > 65535 - *strength) val 2273 drivers/media/dvb-frontends/dib9000.c *strength += val; val 2285 drivers/media/dvb-frontends/dib9000.c u16 val; val 2298 drivers/media/dvb-frontends/dib9000.c val = c[7]; val 2299 drivers/media/dvb-frontends/dib9000.c n = (val >> 4) & 0xff; val 2300 drivers/media/dvb-frontends/dib9000.c exp = ((val & 0xf) << 2); val 2301 drivers/media/dvb-frontends/dib9000.c val = c[8]; val 2302 drivers/media/dvb-frontends/dib9000.c exp += ((val >> 14) & 0x3); val 2307 drivers/media/dvb-frontends/dib9000.c s = (val >> 6) & 0xFF; val 2308 drivers/media/dvb-frontends/dib9000.c exp = (val & 0x3F); val 36 drivers/media/dvb-frontends/dib9000.h extern int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val); val 70 drivers/media/dvb-frontends/dib9000.h static inline int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val) val 20 drivers/media/dvb-frontends/dibx000_common.c static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val) val 31 drivers/media/dvb-frontends/dibx000_common.c mst->i2c_write_buffer[2] = (val >> 8) & 0xff; val 32 drivers/media/dvb-frontends/dibx000_common.c mst->i2c_write_buffer[3] = val & 0xff; val 266 drivers/media/dvb-frontends/dibx000_common.c u16 val; val 270 drivers/media/dvb-frontends/dibx000_common.c val = addr << 8; // bit 7 = use master or not, if 0, the gate is open val 272 drivers/media/dvb-frontends/dibx000_common.c val = 1 << 7; val 275 drivers/media/dvb-frontends/dibx000_common.c val <<= 1; val 279 drivers/media/dvb-frontends/dibx000_common.c tx[2] = val >> 8; val 280 drivers/media/dvb-frontends/dibx000_common.c tx[3] = val & 0xff; val 228 drivers/media/dvb-frontends/drxk_hard.c static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) val 231 drivers/media/dvb-frontends/drxk_hard.c .buf = val, .len = 1} val 20 drivers/media/dvb-frontends/ec100.c static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val) val 23 drivers/media/dvb-frontends/ec100.c u8 buf[2] = {reg, val}; val 46 drivers/media/dvb-frontends/ec100.c static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val) val 59 drivers/media/dvb-frontends/ec100.c .buf = val val 323 drivers/media/dvb-frontends/helene.c static int helene_write_reg(struct helene_priv *priv, u8 reg, u8 val) val 325 drivers/media/dvb-frontends/helene.c u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ val 331 drivers/media/dvb-frontends/helene.c u8 reg, u8 *val, u32 len) val 344 drivers/media/dvb-frontends/helene.c .buf = val, val 366 drivers/media/dvb-frontends/helene.c helene_i2c_debug(priv, reg, 0, val, len); val 370 drivers/media/dvb-frontends/helene.c static int helene_read_reg(struct helene_priv *priv, u8 reg, u8 *val) val 372 drivers/media/dvb-frontends/helene.c return helene_read_regs(priv, reg, val, 1); val 81 drivers/media/dvb-frontends/horus3a.c static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val) val 83 drivers/media/dvb-frontends/horus3a.c u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ val 339 drivers/media/dvb-frontends/horus3a.c u8 buf[3], val; val 367 drivers/media/dvb-frontends/horus3a.c val = 0x1f; val 370 drivers/media/dvb-frontends/horus3a.c val = 0x10; val 373 drivers/media/dvb-frontends/horus3a.c val = 0xc; val 376 drivers/media/dvb-frontends/horus3a.c val = 0; val 382 drivers/media/dvb-frontends/horus3a.c val <<= 2; val 383 drivers/media/dvb-frontends/horus3a.c horus3a_write_reg(priv, 0x0e, val); val 70 drivers/media/dvb-frontends/itd1000.c u8 val; val 73 drivers/media/dvb-frontends/itd1000.c { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 }, val 83 drivers/media/dvb-frontends/itd1000.c return val; val 53 drivers/media/dvb-frontends/lg2160.c static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val) val 56 drivers/media/dvb-frontends/lg2160.c u8 buf[] = { reg >> 8, reg & 0xff, val }; val 62 drivers/media/dvb-frontends/lg2160.c lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); val 77 drivers/media/dvb-frontends/lg2160.c static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val) val 85 drivers/media/dvb-frontends/lg2160.c .flags = I2C_M_RD, .buf = val, .len = 1 }, val 105 drivers/media/dvb-frontends/lg2160.c u8 val; val 116 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, regs[i].reg, regs[i].val); val 126 drivers/media/dvb-frontends/lg2160.c u8 val; val 131 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, reg, &val); val 135 drivers/media/dvb-frontends/lg2160.c val &= ~(1 << bit); val 136 drivers/media/dvb-frontends/lg2160.c val |= (onoff & 1) << bit; val 138 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, reg, val); val 189 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0015, .val = 0xe6 }, val 191 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0015, .val = 0xf7 }, val 192 drivers/media/dvb-frontends/lg2160.c { .reg = 0x001b, .val = 0x52 }, val 193 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0208, .val = 0x00 }, val 194 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0209, .val = 0x82 }, val 195 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0210, .val = 0xf9 }, val 196 drivers/media/dvb-frontends/lg2160.c { .reg = 0x020a, .val = 0x00 }, val 197 drivers/media/dvb-frontends/lg2160.c { .reg = 0x020b, .val = 0x82 }, val 198 drivers/media/dvb-frontends/lg2160.c { .reg = 0x020d, .val = 0x28 }, val 199 drivers/media/dvb-frontends/lg2160.c { .reg = 0x020f, .val = 0x14 }, val 204 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0000, .val = 0x41 }, val 205 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0001, .val = 0xfb }, val 206 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0216, .val = 0x00 }, val 207 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0219, .val = 0x00 }, val 208 drivers/media/dvb-frontends/lg2160.c { .reg = 0x021b, .val = 0x55 }, val 209 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0606, .val = 0x0a }, val 238 drivers/media/dvb-frontends/lg2160.c u8 val; val 243 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0132, &val); val 247 drivers/media/dvb-frontends/lg2160.c val &= 0xfb; val 248 drivers/media/dvb-frontends/lg2160.c val |= (0 == state->cfg->if_khz) ? 0x04 : 0x00; val 250 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0132, val); val 263 drivers/media/dvb-frontends/lg2160.c u8 val; val 266 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0100, &val); val 270 drivers/media/dvb-frontends/lg2160.c val &= 0xf3; val 271 drivers/media/dvb-frontends/lg2160.c val |= (if_agc_fix) ? 0x08 : 0x00; val 272 drivers/media/dvb-frontends/lg2160.c val |= (rf_agc_fix) ? 0x04 : 0x00; val 274 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0100, val); val 284 drivers/media/dvb-frontends/lg2160.c u8 val; val 287 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0100, &val); val 291 drivers/media/dvb-frontends/lg2160.c val &= 0xcf; val 292 drivers/media/dvb-frontends/lg2160.c val |= (if_agc_freeze) ? 0x20 : 0x00; val 293 drivers/media/dvb-frontends/lg2160.c val |= (rf_agc_freeze) ? 0x10 : 0x00; val 295 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0100, val); val 305 drivers/media/dvb-frontends/lg2160.c u8 val; val 308 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0100, &val); val 312 drivers/media/dvb-frontends/lg2160.c val &= 0xfc; val 313 drivers/media/dvb-frontends/lg2160.c val |= (if_agc_polarity) ? 0x02 : 0x00; val 314 drivers/media/dvb-frontends/lg2160.c val |= (rf_agc_polarity) ? 0x01 : 0x00; val 316 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0100, val); val 325 drivers/media/dvb-frontends/lg2160.c u8 val; val 328 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0008, &val); val 332 drivers/media/dvb-frontends/lg2160.c val &= 0xfe; val 333 drivers/media/dvb-frontends/lg2160.c val |= (polarity) ? 0x01 : 0x00; val 335 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0008, val); val 344 drivers/media/dvb-frontends/lg2160.c u8 val; val 347 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0132, &val); val 351 drivers/media/dvb-frontends/lg2160.c val &= 0xfd; val 352 drivers/media/dvb-frontends/lg2160.c val |= (inverted) ? 0x02 : 0x00; val 354 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0132, val); val 362 drivers/media/dvb-frontends/lg2160.c u8 val; val 365 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0007, &val); val 369 drivers/media/dvb-frontends/lg2160.c val &= 0xbf; val 370 drivers/media/dvb-frontends/lg2160.c val |= (onoff) ? 0x40 : 0x00; val 372 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0007, val); val 395 drivers/media/dvb-frontends/lg2160.c u8 val; val 407 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, reg, &val); val 411 drivers/media/dvb-frontends/lg2160.c val &= 0xfe; val 412 drivers/media/dvb-frontends/lg2160.c val |= (id) ? 0x01 : 0x00; val 414 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, reg, val); val 422 drivers/media/dvb-frontends/lg2160.c u8 val; val 425 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0014, &val); val 429 drivers/media/dvb-frontends/lg2160.c val &= 0xf3; val 430 drivers/media/dvb-frontends/lg2160.c val |= (state->cfg->spi_clock << 2); val 432 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0014, val); val 440 drivers/media/dvb-frontends/lg2160.c u8 val; val 443 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0014, &val); val 447 drivers/media/dvb-frontends/lg2160.c val &= ~0x07; val 448 drivers/media/dvb-frontends/lg2160.c val |= state->cfg->output_if; /* FIXME: needs sanity check */ val 450 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, 0x0014, val); val 496 drivers/media/dvb-frontends/lg2160.c u8 val; val 501 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0128, &val); val 505 drivers/media/dvb-frontends/lg2160.c *ficver = (val >> 3) & 0x1f; val 513 drivers/media/dvb-frontends/lg2160.c u8 val; val 518 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0123, &val); val 522 drivers/media/dvb-frontends/lg2160.c *id = val & 0x7f; val 530 drivers/media/dvb-frontends/lg2160.c u8 val; val 535 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0124, &val); val 539 drivers/media/dvb-frontends/lg2160.c *nog = ((val >> 4) & 0x07) + 1; val 546 drivers/media/dvb-frontends/lg2160.c u8 val; val 551 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0125, &val); val 555 drivers/media/dvb-frontends/lg2160.c *tnog = val & 0x1f; val 562 drivers/media/dvb-frontends/lg2160.c u8 val; val 567 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0124, &val); val 571 drivers/media/dvb-frontends/lg2160.c *sgn = val & 0x0f; val 578 drivers/media/dvb-frontends/lg2160.c u8 val; val 583 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0125, &val); val 587 drivers/media/dvb-frontends/lg2160.c *prc = ((val >> 5) & 0x07) + 1; val 597 drivers/media/dvb-frontends/lg2160.c u8 val; val 602 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0410, &val); val 605 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0513, &val); val 613 drivers/media/dvb-frontends/lg2160.c switch ((val >> 4) & 0x03) { val 637 drivers/media/dvb-frontends/lg2160.c u8 val; val 642 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0400, &val); val 645 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0500, &val); val 653 drivers/media/dvb-frontends/lg2160.c val &= 0x01; val 654 drivers/media/dvb-frontends/lg2160.c *rs_frame_ens = (enum atscmh_rs_frame_ensemble) val; val 663 drivers/media/dvb-frontends/lg2160.c u8 val; val 668 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0410, &val); val 671 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0513, &val); val 679 drivers/media/dvb-frontends/lg2160.c *rs_code_pri = (enum atscmh_rs_code_mode) ((val >> 2) & 0x03); val 680 drivers/media/dvb-frontends/lg2160.c *rs_code_sec = (enum atscmh_rs_code_mode) (val & 0x03); val 688 drivers/media/dvb-frontends/lg2160.c u8 val; val 693 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0315, &val); val 696 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0511, &val); val 704 drivers/media/dvb-frontends/lg2160.c switch (val & 0x03) { val 725 drivers/media/dvb-frontends/lg2160.c u8 val; val 730 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0316, &val); val 733 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0512, &val); val 741 drivers/media/dvb-frontends/lg2160.c switch ((val >> 6) & 0x03) { val 753 drivers/media/dvb-frontends/lg2160.c switch ((val >> 4) & 0x03) { val 765 drivers/media/dvb-frontends/lg2160.c switch ((val >> 2) & 0x03) { val 777 drivers/media/dvb-frontends/lg2160.c switch (val & 0x03) { val 1122 drivers/media/dvb-frontends/lg2160.c u8 val; val 1128 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x011b, &val); val 1132 drivers/media/dvb-frontends/lg2160.c *sync_lock = (val & 0x20) ? 0 : 1; val 1133 drivers/media/dvb-frontends/lg2160.c *acq_lock = (val & 0x40) ? 0 : 1; val 1142 drivers/media/dvb-frontends/lg2160.c u8 val; val 1148 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x0304, &val); val 1152 drivers/media/dvb-frontends/lg2160.c *sync_lock = (val & 0x80) ? 0 : 1; val 1154 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, 0x011b, &val); val 1158 drivers/media/dvb-frontends/lg2160.c *acq_lock = (val & 0x40) ? 0 : 1; val 101 drivers/media/dvb-frontends/lgdt3305.c static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val) val 104 drivers/media/dvb-frontends/lgdt3305.c u8 buf[] = { reg >> 8, reg & 0xff, val }; val 110 drivers/media/dvb-frontends/lgdt3305.c lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); val 125 drivers/media/dvb-frontends/lgdt3305.c static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val) val 133 drivers/media/dvb-frontends/lgdt3305.c .flags = I2C_M_RD, .buf = val, .len = 1 }, val 163 drivers/media/dvb-frontends/lgdt3305.c u8 val; val 168 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_read_reg(state, reg, &val); val 172 drivers/media/dvb-frontends/lgdt3305.c val &= ~(1 << bit); val 173 drivers/media/dvb-frontends/lgdt3305.c val |= (onoff & 1) << bit; val 175 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_write_reg(state, reg, val); val 182 drivers/media/dvb-frontends/lgdt3305.c u8 val; val 193 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val); val 227 drivers/media/dvb-frontends/lgdt3305.c u8 val; val 235 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val); val 239 drivers/media/dvb-frontends/lgdt3305.c val &= ~0x09; val 242 drivers/media/dvb-frontends/lgdt3305.c val |= 0x08; val 244 drivers/media/dvb-frontends/lgdt3305.c val |= 0x40; val 246 drivers/media/dvb-frontends/lgdt3305.c val |= 0x01; val 248 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val); val 292 drivers/media/dvb-frontends/lgdt3305.c int val; val 296 drivers/media/dvb-frontends/lgdt3305.c val = 0; val 300 drivers/media/dvb-frontends/lgdt3305.c val = 1; val 305 drivers/media/dvb-frontends/lgdt3305.c lg_dbg("val = %d\n", val); val 307 drivers/media/dvb-frontends/lgdt3305.c return lgdt3305_set_reg_bit(state, 0x043f, 2, val); val 589 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, val 590 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x000d, .val = 0x02, }, val 591 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x000e, .val = 0x02, }, val 592 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, val 593 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, val 594 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, val 595 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, val 596 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, val 597 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, val 598 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, }, val 599 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0112, .val = 0x17, }, val 600 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0113, .val = 0x15, }, val 601 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0114, .val = 0x18, }, val 602 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0115, .val = 0xff, }, val 603 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0116, .val = 0x3c, }, val 604 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0214, .val = 0x67, }, val 605 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0424, .val = 0x8d, }, val 606 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0427, .val = 0x12, }, val 607 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0428, .val = 0x4f, }, val 608 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_IFBW_1, .val = 0x80, }, val 609 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_IFBW_2, .val = 0x00, }, val 610 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x030a, .val = 0x08, }, val 611 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x030b, .val = 0x9b, }, val 612 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x030d, .val = 0x00, }, val 613 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x030e, .val = 0x1c, }, val 614 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0314, .val = 0xe1, }, val 615 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x000d, .val = 0x82, }, val 616 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, val 617 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, val 621 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, val 622 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, }, val 623 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, }, val 624 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, }, val 625 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, }, val 626 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, val 627 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, val 628 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, val 629 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, val 630 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, val 631 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, val 632 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, }, val 633 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, }, val 634 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, }, val 635 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, }, val 636 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, }, val 637 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, }, val 638 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, }, val 639 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_IFBW_1, .val = 0x80, }, val 640 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_IFBW_2, .val = 0x00, }, val 641 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, }, val 642 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, }, val 643 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, }, val 644 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, }, val 818 drivers/media/dvb-frontends/lgdt3305.c u8 val; val 824 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val); val 831 drivers/media/dvb-frontends/lgdt3305.c if (val & (1 << 1)) val 834 drivers/media/dvb-frontends/lgdt3305.c switch (val & 0x07) { val 853 drivers/media/dvb-frontends/lgdt3305.c if (val & (1 << 7)) { val 869 drivers/media/dvb-frontends/lgdt3305.c u8 val; val 878 drivers/media/dvb-frontends/lgdt3305.c LGDT3305_FEC_LOCK_STATUS, &val); val 882 drivers/media/dvb-frontends/lgdt3305.c mpeg_lock = (val & (1 << 0)) ? 1 : 0; val 883 drivers/media/dvb-frontends/lgdt3305.c fec_lock = (val & (1 << 2)) ? 1 : 0; val 884 drivers/media/dvb-frontends/lgdt3305.c viterbi_lock = (val & (1 << 3)) ? 1 : 0; val 904 drivers/media/dvb-frontends/lgdt3305.c u8 val; val 910 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val); val 914 drivers/media/dvb-frontends/lgdt3305.c signal = (val & (1 << 4)) ? 1 : 0; val 915 drivers/media/dvb-frontends/lgdt3305.c inlock = (val & (1 << 3)) ? 0 : 1; val 916 drivers/media/dvb-frontends/lgdt3305.c sync_lock = (val & (1 << 2)) ? 1 : 0; val 917 drivers/media/dvb-frontends/lgdt3305.c nofecerr = (val & (1 << 1)) ? 1 : 0; val 918 drivers/media/dvb-frontends/lgdt3305.c snrgood = (val & (1 << 0)) ? 1 : 0; val 1100 drivers/media/dvb-frontends/lgdt3305.c u8 val; val 1128 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val); val 1129 drivers/media/dvb-frontends/lgdt3305.c if ((lg_fail(ret)) | (val == 0)) val 1134 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_read_reg(state, 0x0808, &val); val 1135 drivers/media/dvb-frontends/lgdt3305.c if ((lg_fail(ret)) | (val != 0x80)) val 123 drivers/media/dvb-frontends/lgdt3306a.c static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) val 126 drivers/media/dvb-frontends/lgdt3306a.c u8 buf[] = { reg >> 8, reg & 0xff, val }; val 132 drivers/media/dvb-frontends/lgdt3306a.c dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); val 147 drivers/media/dvb-frontends/lgdt3306a.c static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) val 155 drivers/media/dvb-frontends/lgdt3306a.c .flags = I2C_M_RD, .buf = val, .len = 1 }, val 168 drivers/media/dvb-frontends/lgdt3306a.c dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); val 185 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 190 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, reg, &val); val 194 drivers/media/dvb-frontends/lgdt3306a.c val &= ~(1 << bit); val 195 drivers/media/dvb-frontends/lgdt3306a.c val |= (onoff & 1) << bit; val 197 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, reg, val); val 226 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 244 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0070, &val); val 248 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x10; /* TPCLKSUPB=0x10 */ val 251 drivers/media/dvb-frontends/lgdt3306a.c val &= ~0x10; val 253 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0070, val); val 264 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 269 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0070, &val); val 273 drivers/media/dvb-frontends/lgdt3306a.c val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */ val 276 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x04; val 278 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x02; val 280 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0070, val); val 290 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 296 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0070, &val); val 303 drivers/media/dvb-frontends/lgdt3306a.c val &= ~0xa8; val 304 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0070, val); val 319 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0070, &val); val 323 drivers/media/dvb-frontends/lgdt3306a.c val |= 0xa8; /* enable bus */ val 324 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0070, val); val 383 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 389 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0002, &val); val 390 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xf7; /* SPECINVAUTO Off */ val 391 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x04; /* SPECINV On */ val 392 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0002, val); val 402 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0009, &val); val 403 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xe3; val 404 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */ val 405 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0009, val); val 410 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0009, &val); val 411 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */ val 412 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0009, val); val 417 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x000d, &val); val 418 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xbf; /* SAMPLING4XFEN=0 */ val 419 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x000d, val); val 479 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x001e, &val); val 480 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x0f; val 481 drivers/media/dvb-frontends/lgdt3306a.c val |= 0xa0; val 482 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x001e, val); val 488 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x211f, &val); val 489 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xef; val 490 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x211f, val); val 494 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x1061, &val); val 495 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xf8; val 496 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x04; val 497 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x1061, val); val 499 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x103d, &val); val 500 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xcf; val 501 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x103d, val); val 505 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2141, &val); val 506 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x3f; val 507 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2141, val); val 509 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2135, &val); val 510 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x0f; val 511 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x70; val 512 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2135, val); val 514 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0003, &val); val 515 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xf7; val 516 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0003, val); val 518 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x001c, &val); val 519 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x7f; val 520 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x001c, val); val 523 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2179, &val); val 524 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xf8; val 525 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2179, val); val 527 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x217a, &val); val 528 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xf8; val 529 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x217a, val); val 543 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 554 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0002, &val); val 555 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xfb; /* SPECINV Off */ val 556 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x08; /* SPECINVAUTO On */ val 557 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0002, val); val 562 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0009, &val); val 563 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */ val 564 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0009, val); val 569 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0009, &val); val 570 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xfc; val 573 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */ val 575 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */ val 577 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0009, val); val 582 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x101a, &val); val 583 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xf8; val 585 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */ val 587 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */ val 589 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x101a, val); val 594 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x000d, &val); val 595 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xbf; val 596 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x40; /* SAMPLING4XFEN=1 */ val 597 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x000d, val); val 602 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0024, &val); val 603 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x00; val 604 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0024, val); val 609 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x000a, &val); val 610 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xfd; val 611 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x02; val 612 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x000a, val); val 617 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2849, &val); val 618 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xdf; val 619 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2849, val); val 624 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x302b, &val); val 625 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x7f; /* SELFSYNCFINDEN_CQS=0; disable auto reset */ val 626 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x302b, val); val 849 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 899 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0005, &val); val 902 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xc0; val 903 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x25; val 904 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0005, val); val 912 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x000d, &val); val 915 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xc0; val 916 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x18; val 917 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x000d, val); val 923 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0005, &val); val 926 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xc0; val 927 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x25; val 928 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0005, val); val 936 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x000d, &val); val 939 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xc0; val 940 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x19; val 941 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x000d, val); val 960 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x103c, &val); val 961 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x0f; val 962 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */ val 963 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x103c, val); val 966 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x103d, &val); val 967 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xfc; val 968 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x03; val 969 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x103d, val); val 972 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x1036, &val); val 973 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xf0; val 974 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x0c; val 975 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x1036, val); val 978 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x211f, &val); val 979 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xef; /* do not use imaginary of CIR */ val 980 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x211f, val); val 983 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2849, &val); val 984 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */ val 985 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2849, val); val 1103 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 1108 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x21a1, &val); val 1111 drivers/media/dvb-frontends/lgdt3306a.c snrRef = val & 0x3f; val 1117 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2191, &val); val 1120 drivers/media/dvb-frontends/lgdt3306a.c nCombDet = (val & 0x80) >> 7; val 1122 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2180, &val); val 1125 drivers/media/dvb-frontends/lgdt3306a.c fbDlyCir = (val & 0x03) << 8; val 1127 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2181, &val); val 1130 drivers/media/dvb-frontends/lgdt3306a.c fbDlyCir |= val; val 1136 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x1061, &val); val 1139 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xf8; val 1144 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x00; /* final bandwidth = 0 */ val 1146 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x04; /* final bandwidth = 4 */ val 1148 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x1061, val); val 1153 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0024, &val); val 1156 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x0f; val 1158 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x50; val 1160 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x0024, val); val 1165 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x103d, &val); val 1168 drivers/media/dvb-frontends/lgdt3306a.c val &= 0xcf; val 1169 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x20; val 1170 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x103d, val); val 1178 drivers/media/dvb-frontends/lgdt3306a.c u8 val = 0; val 1181 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0081, &val); val 1185 drivers/media/dvb-frontends/lgdt3306a.c if (val & 0x80) { val 1189 drivers/media/dvb-frontends/lgdt3306a.c if (val & 0x08) { val 1190 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x00a6, &val); val 1193 drivers/media/dvb-frontends/lgdt3306a.c val = val >> 2; val 1194 drivers/media/dvb-frontends/lgdt3306a.c if (val & 0x01) { val 1210 drivers/media/dvb-frontends/lgdt3306a.c u8 val = 0; val 1220 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x00a6, &val); val 1224 drivers/media/dvb-frontends/lgdt3306a.c if ((val & 0x80) == 0x80) val 1234 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0080, &val); val 1238 drivers/media/dvb-frontends/lgdt3306a.c if ((val & 0x40) == 0x40) val 1250 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x1094, &val); val 1254 drivers/media/dvb-frontends/lgdt3306a.c if ((val & 0x80) == 0x80) val 1268 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0080, &val); val 1272 drivers/media/dvb-frontends/lgdt3306a.c if ((val & 0x10) == 0x10) val 1295 drivers/media/dvb-frontends/lgdt3306a.c u8 val = 0; val 1299 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0080, &val); val 1302 drivers/media/dvb-frontends/lgdt3306a.c lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03); val 1311 drivers/media/dvb-frontends/lgdt3306a.c u8 val = 0; val 1321 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x21a1, &val); val 1324 drivers/media/dvb-frontends/lgdt3306a.c snrRef = val & 0x3f; val 1327 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2199, &val); val 1330 drivers/media/dvb-frontends/lgdt3306a.c mainStrong = (val & 0x40) >> 6; val 1332 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0090, &val); val 1335 drivers/media/dvb-frontends/lgdt3306a.c aiccrejStatus = (val & 0xf0) >> 4; val 1345 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2135, &val); val 1348 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x0f; val 1349 drivers/media/dvb-frontends/lgdt3306a.c val |= 0xa0; val 1350 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2135, val); val 1354 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2141, &val); val 1357 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x3f; val 1358 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x80; val 1359 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2141, val); val 1367 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2135, &val); val 1370 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x0f; val 1371 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x70; val 1372 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2135, val); val 1376 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x2141, &val); val 1379 drivers/media/dvb-frontends/lgdt3306a.c val &= 0x3f; val 1380 drivers/media/dvb-frontends/lgdt3306a.c val |= 0x40; val 1381 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, 0x2141, val); val 1456 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 1459 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x00fa, &val); val 1463 drivers/media/dvb-frontends/lgdt3306a.c return val; val 1663 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 1679 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x00a6, &val); val 1683 drivers/media/dvb-frontends/lgdt3306a.c if(val & 0x04) val 1821 drivers/media/dvb-frontends/lgdt3306a.c u8 val; val 1841 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0000, &val); val 1844 drivers/media/dvb-frontends/lgdt3306a.c if ((val & 0x74) != 0x74) { val 1845 drivers/media/dvb-frontends/lgdt3306a.c pr_warn("expected 0x74, got 0x%x\n", (val & 0x74)); val 1851 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0001, &val); val 1854 drivers/media/dvb-frontends/lgdt3306a.c if ((val & 0xf6) != 0xc6) { val 1855 drivers/media/dvb-frontends/lgdt3306a.c pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6)); val 1861 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, 0x0002, &val); val 1864 drivers/media/dvb-frontends/lgdt3306a.c if ((val & 0x73) != 0x03) { val 1865 drivers/media/dvb-frontends/lgdt3306a.c pr_warn("expected 0x03, got 0x%x\n", (val & 0x73)); val 156 drivers/media/dvb-frontends/lgs8gl5.c u8 val; val 160 drivers/media/dvb-frontends/lgs8gl5.c val = lgs8gl5_read_reg(state, REG_RESET); val 161 drivers/media/dvb-frontends/lgs8gl5.c lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF); val 162 drivers/media/dvb-frontends/lgs8gl5.c lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF); val 171 drivers/media/dvb-frontends/lgs8gl5.c u8 val; val 194 drivers/media/dvb-frontends/lgs8gl5.c val = lgs8gl5_read_reg(state, REG_STRENGTH); val 195 drivers/media/dvb-frontends/lgs8gl5.c dprintk("Wait for carrier[%d] 0x%02X\n", n, val); val 196 drivers/media/dvb-frontends/lgs8gl5.c if (val & REG_STRENGTH_CARRIER) val 200 drivers/media/dvb-frontends/lgs8gl5.c if (!(val & REG_STRENGTH_CARRIER)) val 205 drivers/media/dvb-frontends/lgs8gl5.c val = lgs8gl5_read_reg(state, REG_STATUS); val 206 drivers/media/dvb-frontends/lgs8gl5.c dprintk("Wait for lock[%d] 0x%02X\n", n, val); val 207 drivers/media/dvb-frontends/lgs8gl5.c if (val & REG_STATUS_LOCK) val 211 drivers/media/dvb-frontends/lgs8gl5.c if (!(val & REG_STATUS_LOCK)) val 102 drivers/media/dvb-frontends/lgs8gxx.c u8 val, u8 delay, u8 tries) val 110 drivers/media/dvb-frontends/lgs8gxx.c if ((t & mask) == val) val 144 drivers/media/dvb-frontends/lgs8gxx.c u64 val; val 150 drivers/media/dvb-frontends/lgs8gxx.c val = freq; val 152 drivers/media/dvb-frontends/lgs8gxx.c val <<= 32; val 154 drivers/media/dvb-frontends/lgs8gxx.c do_div(val, if_clk); val 155 drivers/media/dvb-frontends/lgs8gxx.c v32 = val & 0xFFFFFFFF; val 180 drivers/media/dvb-frontends/lgs8gxx.c u64 val; val 197 drivers/media/dvb-frontends/lgs8gxx.c val = v32; val 198 drivers/media/dvb-frontends/lgs8gxx.c val *= priv->config->if_clk_freq; val 199 drivers/media/dvb-frontends/lgs8gxx.c val >>= 32; val 200 drivers/media/dvb-frontends/lgs8gxx.c dprintk("AFC = %u kHz\n", (u32)val); val 318 drivers/media/dvb-frontends/lgs8gxx.c u8 reg, mask, val; val 323 drivers/media/dvb-frontends/lgs8gxx.c val = 0x80; val 327 drivers/media/dvb-frontends/lgs8gxx.c val = 0xC0; val 330 drivers/media/dvb-frontends/lgs8gxx.c ret = wait_reg_mask(priv, reg, mask, val, 50, 40); val 340 drivers/media/dvb-frontends/lgs8gxx.c u8 reg, mask, val; val 345 drivers/media/dvb-frontends/lgs8gxx.c val = 0x80; val 349 drivers/media/dvb-frontends/lgs8gxx.c val = 0x01; val 352 drivers/media/dvb-frontends/lgs8gxx.c ret = wait_reg_mask(priv, reg, mask, val, 10, 20); val 14 drivers/media/dvb-frontends/m88ds3103.c u8 reg, u8 mask, u8 val) val 25 drivers/media/dvb-frontends/m88ds3103.c val &= mask; val 27 drivers/media/dvb-frontends/m88ds3103.c val |= tmp; val 30 drivers/media/dvb-frontends/m88ds3103.c return regmap_bulk_write(dev->regmap, reg, &val, 1); val 49 drivers/media/dvb-frontends/m88ds3103.c buf[j] = tab[i].val; val 46 drivers/media/dvb-frontends/m88ds3103_priv.h u8 val; val 286 drivers/media/dvb-frontends/m88rs2000.c u8 val; val 384 drivers/media/dvb-frontends/m88rs2000.c tab[i].val); val 391 drivers/media/dvb-frontends/m88rs2000.c if (tab[i].reg == 0xaa && tab[i].val == 0xff) val 62 drivers/media/dvb-frontends/mb86a16.c static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) val 65 drivers/media/dvb-frontends/mb86a16.c u8 buf[] = { reg, val }; val 83 drivers/media/dvb-frontends/mb86a16.c static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) val 111 drivers/media/dvb-frontends/mb86a16.c *val = b1[0]; val 121 drivers/media/dvb-frontends/mb86a16.c unsigned char val; val 123 drivers/media/dvb-frontends/mb86a16.c val = (timint1 << 4) | (timint2 << 2) | cnext; val 124 drivers/media/dvb-frontends/mb86a16.c if (mb86a16_write(state, MB86A16_CNTMR, val) < 0) val 290 drivers/media/dvb-frontends/mb86a16.c unsigned char val; val 292 drivers/media/dvb-frontends/mb86a16.c val = 0x7a | (cren << 7) | (afcen << 2); val 293 drivers/media/dvb-frontends/mb86a16.c if (mb86a16_write(state, 0x49, val) < 0) val 611 drivers/media/dvb-frontends/mb86a16.c unsigned char val; val 614 drivers/media/dvb-frontends/mb86a16.c if (mb86a16_read(state, 0x0d, &val) != 2) val 617 drivers/media/dvb-frontends/mb86a16.c dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val); val 618 drivers/media/dvb-frontends/mb86a16.c sync = val & 0x01; val 619 drivers/media/dvb-frontends/mb86a16.c *VIRM = (val & 0x1c) >> 2; val 249 drivers/media/dvb-frontends/mb86a20s.c u8 val; val 253 drivers/media/dvb-frontends/mb86a20s.c { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } val 264 drivers/media/dvb-frontends/mb86a20s.c return val; val 269 drivers/media/dvb-frontends/mb86a20s.c #define mb86a20s_writereg(state, reg, val) \ val 270 drivers/media/dvb-frontends/mb86a20s.c mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) val 284 drivers/media/dvb-frontends/mb86a20s.c int val; val 288 drivers/media/dvb-frontends/mb86a20s.c val = mb86a20s_readreg(state, 0x0a); val 289 drivers/media/dvb-frontends/mb86a20s.c if (val < 0) val 290 drivers/media/dvb-frontends/mb86a20s.c return val; val 292 drivers/media/dvb-frontends/mb86a20s.c val &= 0xf; val 293 drivers/media/dvb-frontends/mb86a20s.c if (val >= 2) val 296 drivers/media/dvb-frontends/mb86a20s.c if (val >= 4) val 299 drivers/media/dvb-frontends/mb86a20s.c if (val >= 5) val 302 drivers/media/dvb-frontends/mb86a20s.c if (val >= 7) val 309 drivers/media/dvb-frontends/mb86a20s.c if (val >= 9) val 313 drivers/media/dvb-frontends/mb86a20s.c __func__, *status, val); val 315 drivers/media/dvb-frontends/mb86a20s.c return val; val 740 drivers/media/dvb-frontends/mb86a20s.c int rc, val; val 768 drivers/media/dvb-frontends/mb86a20s.c val = rc; val 769 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x45, val | 0x10); val 772 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x45, val & 0x6f); val 783 drivers/media/dvb-frontends/mb86a20s.c val = rc; val 784 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x51, val | 0x01); val 787 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x51, val & 0x06); val 805 drivers/media/dvb-frontends/mb86a20s.c int rc, val; val 923 drivers/media/dvb-frontends/mb86a20s.c val = rc; val 924 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); val 927 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); val 939 drivers/media/dvb-frontends/mb86a20s.c int rc, val; val 1052 drivers/media/dvb-frontends/mb86a20s.c val = rc; val 1053 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); val 1056 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); val 1066 drivers/media/dvb-frontends/mb86a20s.c int rc, val; val 1199 drivers/media/dvb-frontends/mb86a20s.c val = rc; val 1200 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); val 1203 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); val 1388 drivers/media/dvb-frontends/mb86a20s.c int rc, val; val 1400 drivers/media/dvb-frontends/mb86a20s.c val = rc; val 1422 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x45, val | 0x10); val 1425 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x45, val & 0x6f); val 1435 drivers/media/dvb-frontends/mb86a20s.c int rc, val, layer; val 1520 drivers/media/dvb-frontends/mb86a20s.c val = rc; val 1522 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x51, val | 0x01); val 1525 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x51, val & 0x06); val 124 drivers/media/dvb-frontends/mt312.c const enum mt312_reg_addr reg, u8 *val) val 126 drivers/media/dvb-frontends/mt312.c return mt312_read(state, reg, val, 1); val 130 drivers/media/dvb-frontends/mt312.c const enum mt312_reg_addr reg, const u8 val) val 132 drivers/media/dvb-frontends/mt312.c u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ val 426 drivers/media/dvb-frontends/mt312.c u8 val; val 431 drivers/media/dvb-frontends/mt312.c val = volt_tab[v]; val 433 drivers/media/dvb-frontends/mt312.c val ^= 0x40; val 435 drivers/media/dvb-frontends/mt312.c return mt312_writereg(state, DISEQC_MODE, val); val 667 drivers/media/dvb-frontends/mt312.c u8 val = 0x00; val 672 drivers/media/dvb-frontends/mt312.c ret = mt312_readreg(state, GPP_CTRL, &val); val 677 drivers/media/dvb-frontends/mt312.c val &= 0x80; val 682 drivers/media/dvb-frontends/mt312.c val |= 0x40; val 684 drivers/media/dvb-frontends/mt312.c val &= ~0x40; val 686 drivers/media/dvb-frontends/mt312.c ret = mt312_writereg(state, GPP_CTRL, val); val 44 drivers/media/dvb-frontends/mt352.c static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val) val 47 drivers/media/dvb-frontends/mt352.c u8 buf[2] = { reg, val }; val 158 drivers/media/dvb-frontends/mxl5xx.c static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val) val 172 drivers/media/dvb-frontends/mxl5xx.c stat = i2cread(state, (u8 *) val, val 174 drivers/media/dvb-frontends/mxl5xx.c le32_to_cpus(val); val 186 drivers/media/dvb-frontends/mxl5xx.c u32 val, count = 10; val 190 drivers/media/dvb-frontends/mxl5xx.c read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val); val 191 drivers/media/dvb-frontends/mxl5xx.c if (DMA_INTR_PROT_WR_CMP & val) val 193 drivers/media/dvb-frontends/mxl5xx.c while ((DMA_INTR_PROT_WR_CMP & val) && --count) { val 198 drivers/media/dvb-frontends/mxl5xx.c &val); val 211 drivers/media/dvb-frontends/mxl5xx.c static int write_register(struct mxl *state, u32 reg, u32 val) val 217 drivers/media/dvb-frontends/mxl5xx.c BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val), val 250 drivers/media/dvb-frontends/mxl5xx.c static int read_register(struct mxl *state, u32 reg, u32 *val) val 265 drivers/media/dvb-frontends/mxl5xx.c stat = i2cread(state, (u8 *) val, val 268 drivers/media/dvb-frontends/mxl5xx.c le32_to_cpus(val); val 298 drivers/media/dvb-frontends/mxl5xx.c u32 reg, u8 lsbloc, u8 numofbits, u32 *val) val 309 drivers/media/dvb-frontends/mxl5xx.c *val = data; val 315 drivers/media/dvb-frontends/mxl5xx.c u32 reg, u8 lsbloc, u8 numofbits, u32 val) val 324 drivers/media/dvb-frontends/mxl5xx.c data = (data & ~mask) | ((val << lsbloc) & mask); val 1328 drivers/media/dvb-frontends/mxl5xx.c u32 val; val 1330 drivers/media/dvb-frontends/mxl5xx.c read_register(state, 0x90000194, &val); val 1331 drivers/media/dvb-frontends/mxl5xx.c dev_info(state->i2cdev, "DIGIO = %08x\n", val); val 1362 drivers/media/dvb-frontends/mxl5xx.c u32 val, count = 10; val 1372 drivers/media/dvb-frontends/mxl5xx.c read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); val 1373 drivers/media/dvb-frontends/mxl5xx.c while (--count && ((val >> tuner) & 1) != enable) { val 1375 drivers/media/dvb-frontends/mxl5xx.c read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); val 1379 drivers/media/dvb-frontends/mxl5xx.c read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); val 1381 drivers/media/dvb-frontends/mxl5xx.c tuner, (val >> tuner) & 1); val 1666 drivers/media/dvb-frontends/mxl5xx.c u32 val = 0; val 1668 drivers/media/dvb-frontends/mxl5xx.c status = read_by_mnemonic(state, 0x90000190, 0, 3, &val); val 1671 drivers/media/dvb-frontends/mxl5xx.c dev_info(state->i2cdev, "chipID=%08x\n", val); val 1673 drivers/media/dvb-frontends/mxl5xx.c status = read_by_mnemonic(state, 0x80030004, 8, 8, &val); val 1676 drivers/media/dvb-frontends/mxl5xx.c dev_info(state->i2cdev, "chipVer=%08x\n", val); val 1678 drivers/media/dvb-frontends/mxl5xx.c status = read_register(state, HYDRA_FIRMWARE_VERSION, &val); val 1681 drivers/media/dvb-frontends/mxl5xx.c dev_info(state->i2cdev, "FWVer=%08x\n", val); val 1683 drivers/media/dvb-frontends/mxl5xx.c state->base->fwversion = val; val 70 drivers/media/dvb-frontends/nxt6000.c u8 val; val 72 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, OFDM_COR_CTL); val 74 drivers/media/dvb-frontends/nxt6000.c nxt6000_writereg(state, OFDM_COR_CTL, val & ~COREACT); val 75 drivers/media/dvb-frontends/nxt6000.c nxt6000_writereg(state, OFDM_COR_CTL, val | COREACT); val 210 drivers/media/dvb-frontends/nxt6000.c u8 val; val 236 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, RS_COR_STAT); val 238 drivers/media/dvb-frontends/nxt6000.c pr_cont(" DATA DESCR LOCK: %d,", val & 0x01); val 239 drivers/media/dvb-frontends/nxt6000.c pr_cont(" DATA SYNC LOCK: %d,", (val >> 1) & 0x01); val 241 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, VIT_SYNC_STATUS); val 243 drivers/media/dvb-frontends/nxt6000.c pr_cont(" VITERBI LOCK: %d,", (val >> 7) & 0x01); val 245 drivers/media/dvb-frontends/nxt6000.c switch ((val >> 4) & 0x07) { val 272 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, OFDM_COR_STAT); val 274 drivers/media/dvb-frontends/nxt6000.c pr_cont(" CHCTrack: %d,", (val >> 7) & 0x01); val 275 drivers/media/dvb-frontends/nxt6000.c pr_cont(" TPSLock: %d,", (val >> 6) & 0x01); val 276 drivers/media/dvb-frontends/nxt6000.c pr_cont(" SYRLock: %d,", (val >> 5) & 0x01); val 277 drivers/media/dvb-frontends/nxt6000.c pr_cont(" AGCLock: %d,", (val >> 4) & 0x01); val 279 drivers/media/dvb-frontends/nxt6000.c switch (val & 0x0F) { val 314 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, OFDM_SYR_STAT); val 316 drivers/media/dvb-frontends/nxt6000.c pr_cont(" SYRLock: %d,", (val >> 4) & 0x01); val 317 drivers/media/dvb-frontends/nxt6000.c pr_cont(" SYRMode: %s,", (val >> 2) & 0x01 ? "8K" : "2K"); val 319 drivers/media/dvb-frontends/nxt6000.c switch ((val >> 4) & 0x03) { val 338 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, OFDM_TPS_RCVD_3); val 340 drivers/media/dvb-frontends/nxt6000.c switch ((val >> 4) & 0x07) { val 367 drivers/media/dvb-frontends/nxt6000.c switch (val & 0x07) { val 394 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, OFDM_TPS_RCVD_4); val 396 drivers/media/dvb-frontends/nxt6000.c pr_cont(" TPSMode: %s,", val & 0x01 ? "8K" : "2K"); val 398 drivers/media/dvb-frontends/nxt6000.c switch ((val >> 4) & 0x03) { val 420 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, RF_AGC_STATUS); val 421 drivers/media/dvb-frontends/nxt6000.c val = nxt6000_readreg(state, RF_AGC_STATUS); val 423 drivers/media/dvb-frontends/nxt6000.c pr_cont(" RF AGC LOCK: %d,", (val >> 4) & 0x01); val 12 drivers/media/dvb-frontends/rtl2830.c const void *val, size_t val_count) val 18 drivers/media/dvb-frontends/rtl2830.c ret = regmap_bulk_write(dev->regmap, reg, val, val_count); val 24 drivers/media/dvb-frontends/rtl2830.c unsigned int mask, unsigned int val) val 30 drivers/media/dvb-frontends/rtl2830.c ret = regmap_update_bits(dev->regmap, reg, mask, val); val 36 drivers/media/dvb-frontends/rtl2830.c void *val, size_t val_count) val 42 drivers/media/dvb-frontends/rtl2830.c ret = regmap_bulk_read(dev->regmap, reg, val, val_count); val 94 drivers/media/dvb-frontends/rtl2830.c tab[i].val); val 743 drivers/media/dvb-frontends/rtl2830.c size_t reg_len, const void *val, val 759 drivers/media/dvb-frontends/rtl2830.c memcpy(&buf[1], val, val_len); val 35 drivers/media/dvb-frontends/rtl2830_priv.h u8 val; val 143 drivers/media/dvb-frontends/rtl2832.c static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val) val 165 drivers/media/dvb-frontends/rtl2832.c *val = (reading_tmp >> lsb) & mask; val 173 drivers/media/dvb-frontends/rtl2832.c static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val) val 196 drivers/media/dvb-frontends/rtl2832.c writing_tmp |= ((val & mask) << lsb); val 1255 drivers/media/dvb-frontends/rtl2832_sdr.c ctrl->id, ctrl->name, ctrl->val, ctrl->minimum, ctrl->maximum, val 1262 drivers/media/dvb-frontends/rtl2832_sdr.c if (dev->bandwidth_auto->val) { val 1264 drivers/media/dvb-frontends/rtl2832_sdr.c s32 val = dev->f_adc + div_u64(dev->bandwidth->step, 2); val 1267 drivers/media/dvb-frontends/rtl2832_sdr.c val = clamp_t(s32, val, dev->bandwidth->minimum, val 1269 drivers/media/dvb-frontends/rtl2832_sdr.c offset = val - dev->bandwidth->minimum; val 1272 drivers/media/dvb-frontends/rtl2832_sdr.c dev->bandwidth->val = dev->bandwidth->minimum + offset; val 1274 drivers/media/dvb-frontends/rtl2832_sdr.c c->bandwidth_hz = dev->bandwidth->val; val 106 drivers/media/dvb-frontends/s5h1409.c u16 val; val 153 drivers/media/dvb-frontends/s5h1409.c u16 val; val 225 drivers/media/dvb-frontends/s5h1409.c u16 val; val 667 drivers/media/dvb-frontends/s5h1409.c u16 val; val 671 drivers/media/dvb-frontends/s5h1409.c val = s5h1409_readreg(state, 0xac) & 0xcfff; val 674 drivers/media/dvb-frontends/s5h1409.c val |= 0x0000; val 678 drivers/media/dvb-frontends/s5h1409.c val |= 0x1000; val 681 drivers/media/dvb-frontends/s5h1409.c val |= 0x2000; val 684 drivers/media/dvb-frontends/s5h1409.c val |= 0x3000; val 691 drivers/media/dvb-frontends/s5h1409.c return s5h1409_writereg(state, 0xac, val); val 804 drivers/media/dvb-frontends/s5h1409.c if (v < qam256_snr_tab[i].val) { val 819 drivers/media/dvb-frontends/s5h1409.c if (v < qam64_snr_tab[i].val) { val 834 drivers/media/dvb-frontends/s5h1409.c if (v > vsb_snr_tab[i].val) { val 134 drivers/media/dvb-frontends/s5h1411.c u16 val; val 179 drivers/media/dvb-frontends/s5h1411.c u16 val; val 252 drivers/media/dvb-frontends/s5h1411.c u16 val; val 418 drivers/media/dvb-frontends/s5h1411.c u16 val; val 422 drivers/media/dvb-frontends/s5h1411.c val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff; val 425 drivers/media/dvb-frontends/s5h1411.c val |= 0x0000; val 429 drivers/media/dvb-frontends/s5h1411.c val |= 0x1000; val 432 drivers/media/dvb-frontends/s5h1411.c val |= 0x2000; val 435 drivers/media/dvb-frontends/s5h1411.c val |= 0x3000; val 442 drivers/media/dvb-frontends/s5h1411.c return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val); val 448 drivers/media/dvb-frontends/s5h1411.c u16 val; val 451 drivers/media/dvb-frontends/s5h1411.c val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000; val 454 drivers/media/dvb-frontends/s5h1411.c val |= 0x1000; /* Inverted */ val 457 drivers/media/dvb-frontends/s5h1411.c return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val); val 463 drivers/media/dvb-frontends/s5h1411.c u16 val; val 466 drivers/media/dvb-frontends/s5h1411.c val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100; val 469 drivers/media/dvb-frontends/s5h1411.c val |= 0x100; val 471 drivers/media/dvb-frontends/s5h1411.c return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val); val 532 drivers/media/dvb-frontends/s5h1411.c u16 val; val 536 drivers/media/dvb-frontends/s5h1411.c val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02; val 540 drivers/media/dvb-frontends/s5h1411.c val | 0x02); val 542 drivers/media/dvb-frontends/s5h1411.c return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val); val 718 drivers/media/dvb-frontends/s5h1411.c if (v < qam256_snr_tab[i].val) { val 733 drivers/media/dvb-frontends/s5h1411.c if (v < qam64_snr_tab[i].val) { val 748 drivers/media/dvb-frontends/s5h1411.c if (v > vsb_snr_tab[i].val) { val 165 drivers/media/dvb-frontends/s5h1420.c u8 val; val 175 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, 0x3b); val 200 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, 0x3b, val); val 210 drivers/media/dvb-frontends/s5h1420.c u8 val; val 217 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, 0x3b); val 256 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, 0x3b, val); val 265 drivers/media/dvb-frontends/s5h1420.c u8 val; val 270 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, 0x3b); val 294 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, 0x3b, val); val 301 drivers/media/dvb-frontends/s5h1420.c u8 val; val 304 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, 0x14); val 305 drivers/media/dvb-frontends/s5h1420.c if (val & 0x02) val 307 drivers/media/dvb-frontends/s5h1420.c if (val & 0x01) val 309 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, 0x36); val 310 drivers/media/dvb-frontends/s5h1420.c if (val & 0x01) val 312 drivers/media/dvb-frontends/s5h1420.c if (val & 0x20) val 324 drivers/media/dvb-frontends/s5h1420.c u8 val; val 337 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, Vit10); val 338 drivers/media/dvb-frontends/s5h1420.c if ((val & 0x07) == 0x03) { val 339 drivers/media/dvb-frontends/s5h1420.c if (val & 0x08) val 373 drivers/media/dvb-frontends/s5h1420.c val = 0x00; val 375 drivers/media/dvb-frontends/s5h1420.c val = 0x01; val 377 drivers/media/dvb-frontends/s5h1420.c val = 0x02; val 379 drivers/media/dvb-frontends/s5h1420.c val = 0x03; val 381 drivers/media/dvb-frontends/s5h1420.c val = 0x04; val 383 drivers/media/dvb-frontends/s5h1420.c val = 0x05; val 385 drivers/media/dvb-frontends/s5h1420.c val = 0x06; val 387 drivers/media/dvb-frontends/s5h1420.c val = 0x07; val 388 drivers/media/dvb-frontends/s5h1420.c dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val); val 392 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, FEC01, val); val 395 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, Mpeg02); val 396 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, Mpeg02, val | (1 << 6)); val 399 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, QPSK01) & 0x7f; val 400 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, QPSK01, val); val 437 drivers/media/dvb-frontends/s5h1420.c u8 val = s5h1420_readreg(state, 0x15); val 439 drivers/media/dvb-frontends/s5h1420.c *strength = (u16) ((val << 8) | val); val 468 drivers/media/dvb-frontends/s5h1420.c u64 val; val 472 drivers/media/dvb-frontends/s5h1420.c val = ((u64) p->symbol_rate / 1000ULL) * (1ULL<<24); val 474 drivers/media/dvb-frontends/s5h1420.c val *= 2; val 475 drivers/media/dvb-frontends/s5h1420.c do_div(val, (state->fclk / 1000)); val 477 drivers/media/dvb-frontends/s5h1420.c dprintk("symbol rate register: %06llx\n", (unsigned long long)val); val 481 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, Tnco01, val >> 16); val 482 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, Tnco02, val >> 8); val 483 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, Tnco03, val & 0xff); val 495 drivers/media/dvb-frontends/s5h1420.c int val; val 502 drivers/media/dvb-frontends/s5h1420.c val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); val 504 drivers/media/dvb-frontends/s5h1420.c dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val); val 508 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, Pnco01, val >> 16); val 509 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, Pnco02, val >> 8); val 510 drivers/media/dvb-frontends/s5h1420.c s5h1420_writereg(state, Pnco03, val & 0xff); val 517 drivers/media/dvb-frontends/s5h1420.c int val; val 520 drivers/media/dvb-frontends/s5h1420.c val = s5h1420_readreg(state, 0x0e) << 16; val 521 drivers/media/dvb-frontends/s5h1420.c val |= s5h1420_readreg(state, 0x0f) << 8; val 522 drivers/media/dvb-frontends/s5h1420.c val |= s5h1420_readreg(state, 0x10); val 525 drivers/media/dvb-frontends/s5h1420.c if (val & 0x800000) val 526 drivers/media/dvb-frontends/s5h1420.c val |= 0xff000000; val 530 drivers/media/dvb-frontends/s5h1420.c val = (((-val) * (state->fclk/1000000)) / (1<<24)); val 532 drivers/media/dvb-frontends/s5h1420.c return val; val 232 drivers/media/dvb-frontends/s921.c u8 val; val 236 drivers/media/dvb-frontends/s921.c { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } val 246 drivers/media/dvb-frontends/s921.c return val; val 251 drivers/media/dvb-frontends/s921.c #define s921_writereg(state, reg, val) \ val 252 drivers/media/dvb-frontends/s921.c s921_i2c_writereg(state, state->config->demod_address, reg, val) val 76 drivers/media/dvb-frontends/si2165.c const u16 reg, u8 *val, const int count) val 78 drivers/media/dvb-frontends/si2165.c int ret = regmap_bulk_read(state->regmap, reg, val, count); val 87 drivers/media/dvb-frontends/si2165.c reg, count, val); val 93 drivers/media/dvb-frontends/si2165.c const u16 reg, u8 *val) val 97 drivers/media/dvb-frontends/si2165.c *val = (u8)val_tmp; val 98 drivers/media/dvb-frontends/si2165.c dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val); val 103 drivers/media/dvb-frontends/si2165.c const u16 reg, u16 *val) val 108 drivers/media/dvb-frontends/si2165.c *val = buf[0] | buf[1] << 8; val 109 drivers/media/dvb-frontends/si2165.c dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val); val 114 drivers/media/dvb-frontends/si2165.c const u16 reg, u32 *val) val 119 drivers/media/dvb-frontends/si2165.c *val = buf[0] | buf[1] << 8 | buf[2] << 16; val 120 drivers/media/dvb-frontends/si2165.c dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val); val 124 drivers/media/dvb-frontends/si2165.c static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val) val 126 drivers/media/dvb-frontends/si2165.c return regmap_write(state->regmap, reg, val); val 129 drivers/media/dvb-frontends/si2165.c static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val) val 131 drivers/media/dvb-frontends/si2165.c u8 buf[2] = { val & 0xff, (val >> 8) & 0xff }; val 136 drivers/media/dvb-frontends/si2165.c static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val) val 138 drivers/media/dvb-frontends/si2165.c u8 buf[3] = { val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff }; val 143 drivers/media/dvb-frontends/si2165.c static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val) val 146 drivers/media/dvb-frontends/si2165.c val & 0xff, val 147 drivers/media/dvb-frontends/si2165.c (val >> 8) & 0xff, val 148 drivers/media/dvb-frontends/si2165.c (val >> 16) & 0xff, val 149 drivers/media/dvb-frontends/si2165.c (val >> 24) & 0xff val 155 drivers/media/dvb-frontends/si2165.c u8 val, u8 mask) val 164 drivers/media/dvb-frontends/si2165.c val &= mask; val 166 drivers/media/dvb-frontends/si2165.c val |= tmp; val 168 drivers/media/dvb-frontends/si2165.c return si2165_writereg8(state, reg, val); val 171 drivers/media/dvb-frontends/si2165.c #define REG16(reg, val) \ val 172 drivers/media/dvb-frontends/si2165.c { (reg), (val) & 0xff }, \ val 173 drivers/media/dvb-frontends/si2165.c { (reg) + 1, (val) >> 8 & 0xff } val 176 drivers/media/dvb-frontends/si2165.c u8 val; val 187 drivers/media/dvb-frontends/si2165.c ret = si2165_writereg8(state, regs[i].reg, regs[i].val); val 270 drivers/media/dvb-frontends/si2165.c u8 val = 0; val 274 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_INIT_DONE, &val); val 277 drivers/media/dvb-frontends/si2165.c if (val == 0x01) val 364 drivers/media/dvb-frontends/si2165.c u8 val[3]; val 434 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); val 439 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_EN_RST_ERROR, val); val 442 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_EN_RST_ERROR, val); val 529 drivers/media/dvb-frontends/si2165.c u8 val; val 543 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_CHIP_MODE, &val); val 546 drivers/media/dvb-frontends/si2165.c if (val != state->config.chip_mode) { val 612 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val); val 1039 drivers/media/dvb-frontends/si2165.c u8 val[3]; val 1075 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); val 1102 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); val 1154 drivers/media/dvb-frontends/si2165.c u8 val; val 1204 drivers/media/dvb-frontends/si2165.c ret = si2165_readreg8(state, REG_CHIP_MODE, &val); val 1207 drivers/media/dvb-frontends/si2165.c if (val != state->config.chip_mode) val 411 drivers/media/dvb-frontends/si21xx.c u8 val; val 418 drivers/media/dvb-frontends/si21xx.c val = (0x80 | si21_readreg(state, 0xc1)); val 420 drivers/media/dvb-frontends/si21xx.c burst == SEC_MINI_A ? (val & ~0x10) : (val | 0x10))) val 426 drivers/media/dvb-frontends/si21xx.c if (si21_writereg(state, LNB_CTRL_REG_1, val)) val 435 drivers/media/dvb-frontends/si21xx.c u8 val; val 438 drivers/media/dvb-frontends/si21xx.c val = (0x80 | si21_readreg(state, LNB_CTRL_REG_1)); val 442 drivers/media/dvb-frontends/si21xx.c return si21_writereg(state, LNB_CTRL_REG_1, val | 0x20); val 445 drivers/media/dvb-frontends/si21xx.c return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x20)); val 456 drivers/media/dvb-frontends/si21xx.c u8 val; val 462 drivers/media/dvb-frontends/si21xx.c val = (0x80 | si21_readreg(state, LNB_CTRL_REG_1)); val 466 drivers/media/dvb-frontends/si21xx.c return si21_writereg(state, LNB_CTRL_REG_1, val | 0x40); val 469 drivers/media/dvb-frontends/si21xx.c return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x40)); val 482 drivers/media/dvb-frontends/si21xx.c u8 val; val 489 drivers/media/dvb-frontends/si21xx.c val = serit_sp1511lhb_inittab[i+1]; val 490 drivers/media/dvb-frontends/si21xx.c if (reg1 == 0xff && val == 0xff) val 492 drivers/media/dvb-frontends/si21xx.c si21_writeregs(state, reg1, &val, 1); val 28 drivers/media/dvb-frontends/si21xx.h static inline int si21xx_writeregister(struct dvb_frontend *fe, u8 reg, u8 val) val 31 drivers/media/dvb-frontends/si21xx.h u8 buf[] = {reg, val}; val 355 drivers/media/dvb-frontends/sp887x.c u16 val, reg0xc05; val 386 drivers/media/dvb-frontends/sp887x.c val = 2; val 388 drivers/media/dvb-frontends/sp887x.c val = 1; val 390 drivers/media/dvb-frontends/sp887x.c val = 0; val 392 drivers/media/dvb-frontends/sp887x.c sp887x_writereg(state, 0x311, val); val 403 drivers/media/dvb-frontends/sp887x.c val = 2 << 3; val 405 drivers/media/dvb-frontends/sp887x.c val = 3 << 3; val 407 drivers/media/dvb-frontends/sp887x.c val = 0 << 3; val 412 drivers/media/dvb-frontends/sp887x.c sp887x_writereg(state, 0xf14, 0x160 | val); val 922 drivers/media/dvb-frontends/stb0899_drv.c static int stb0899_table_lookup(const struct stb0899_tab *tab, int max, int val) val 927 drivers/media/dvb-frontends/stb0899_drv.c if (val < tab[min].read) val 929 drivers/media/dvb-frontends/stb0899_drv.c else if (val >= tab[max].read) val 934 drivers/media/dvb-frontends/stb0899_drv.c if (val >= tab[min].read && val < tab[med].read) val 939 drivers/media/dvb-frontends/stb0899_drv.c res = ((val - tab[min].read) * val 953 drivers/media/dvb-frontends/stb0899_drv.c int val; val 964 drivers/media/dvb-frontends/stb0899_drv.c val = (s32)(s8)STB0899_GETFIELD(AGCIQVALUE, reg); val 966 drivers/media/dvb-frontends/stb0899_drv.c *strength = stb0899_table_lookup(stb0899_dvbsrf_tab, ARRAY_SIZE(stb0899_dvbsrf_tab) - 1, val); val 969 drivers/media/dvb-frontends/stb0899_drv.c val & 0xff, *strength); val 976 drivers/media/dvb-frontends/stb0899_drv.c val = STB0899_GETFIELD(IF_AGC_GAIN, reg); val 978 drivers/media/dvb-frontends/stb0899_drv.c *strength = stb0899_table_lookup(stb0899_dvbs2rf_tab, ARRAY_SIZE(stb0899_dvbs2rf_tab) - 1, val); val 981 drivers/media/dvb-frontends/stb0899_drv.c val & 0x3fff, *strength); val 997 drivers/media/dvb-frontends/stb0899_drv.c unsigned int val, quant, quantn = -1, est, estn = -1; val 1010 drivers/media/dvb-frontends/stb0899_drv.c val = MAKEWORD16(buf[0], buf[1]); val 1012 drivers/media/dvb-frontends/stb0899_drv.c *snr = stb0899_table_lookup(stb0899_cn_tab, ARRAY_SIZE(stb0899_cn_tab) - 1, val); val 1014 drivers/media/dvb-frontends/stb0899_drv.c buf[0], buf[1], val, *snr); val 1025 drivers/media/dvb-frontends/stb0899_drv.c val = 301; /* C/N = 30.1 dB */ val 1027 drivers/media/dvb-frontends/stb0899_drv.c val = 270; /* C/N = 27.0 dB */ val 1034 drivers/media/dvb-frontends/stb0899_drv.c val = (quantn - estn) / 10; val 1036 drivers/media/dvb-frontends/stb0899_drv.c *snr = val; val 1038 drivers/media/dvb-frontends/stb0899_drv.c quant, quantn, est, estn, val); val 38 drivers/media/dvb-frontends/stb0899_priv.h #define INRANGE(val, x, y) (((x <= val) && (val <= y)) || \ val 39 drivers/media/dvb-frontends/stb0899_priv.h ((y <= val) && (val <= x)) ? 1 : 0) val 54 drivers/media/dvb-frontends/stb0899_priv.h #define STB0899_GETFIELD(bitf, val) ((val >> STB0899_OFFST_##bitf) & ((1 << STB0899_WIDTH_##bitf) - 1)) val 57 drivers/media/dvb-frontends/stb0899_priv.h #define STB0899_SETFIELD(mask, val, width, offset) (mask & (~(((1 << width) - 1) << \ val 58 drivers/media/dvb-frontends/stb0899_priv.h offset))) | ((val & \ val 61 drivers/media/dvb-frontends/stb0899_priv.h #define STB0899_SETFIELD_VAL(bitf, mask, val) (mask = (mask & (~(((1 << STB0899_WIDTH_##bitf) - 1) <<\ val 63 drivers/media/dvb-frontends/stb0899_priv.h (val << STB0899_OFFST_##bitf)) val 61 drivers/media/dvb-frontends/stb6100.h #define INRANGE(val, x, y) (((x <= val) && (val <= y)) || \ val 62 drivers/media/dvb-frontends/stb6100.h ((y <= val) && (val <= x)) ? 1 : 0) val 64 drivers/media/dvb-frontends/stb6100.h #define CHKRANGE(val, x, y) (((val >= x) && (val < y)) ? 1 : 0) val 329 drivers/media/dvb-frontends/stv0288.c u8 val; val 344 drivers/media/dvb-frontends/stv0288.c val = state->config->inittab[i+1]; val 345 drivers/media/dvb-frontends/stv0288.c if (reg == 0xff && val == 0xff) val 347 drivers/media/dvb-frontends/stv0288.c stv0288_writeregI(state, reg, val); val 45 drivers/media/dvb-frontends/stv0288.h static inline int stv0288_writereg(struct dvb_frontend *fe, u8 reg, u8 val) val 48 drivers/media/dvb-frontends/stv0288.h u8 buf[] = { reg, val }; val 85 drivers/media/dvb-frontends/stv0297.c int val; val 87 drivers/media/dvb-frontends/stv0297.c val = stv0297_readreg(state, reg); val 88 drivers/media/dvb-frontends/stv0297.c val &= ~mask; val 89 drivers/media/dvb-frontends/stv0297.c val |= (data & mask); val 90 drivers/media/dvb-frontends/stv0297.c stv0297_writereg(state, reg, val); val 227 drivers/media/dvb-frontends/stv0297.c int val = 0; val 231 drivers/media/dvb-frontends/stv0297.c val = 0; val 235 drivers/media/dvb-frontends/stv0297.c val = 1; val 239 drivers/media/dvb-frontends/stv0297.c val = 4; val 243 drivers/media/dvb-frontends/stv0297.c val = 2; val 247 drivers/media/dvb-frontends/stv0297.c val = 3; val 254 drivers/media/dvb-frontends/stv0297.c stv0297_writereg_mask(state, 0x00, 0x70, val << 4); val 262 drivers/media/dvb-frontends/stv0297.c int val = 0; val 266 drivers/media/dvb-frontends/stv0297.c val = 0; val 270 drivers/media/dvb-frontends/stv0297.c val = 1; val 277 drivers/media/dvb-frontends/stv0297.c stv0297_writereg_mask(state, 0x83, 0x08, val << 3); val 267 drivers/media/dvb-frontends/stv0299.c u8 val; val 275 drivers/media/dvb-frontends/stv0299.c val = stv0299_readreg (state, 0x08); val 277 drivers/media/dvb-frontends/stv0299.c if (stv0299_writeregI (state, 0x08, (val & ~0x7) | 0x6)) /* DiSEqC mode */ val 298 drivers/media/dvb-frontends/stv0299.c u8 val; val 305 drivers/media/dvb-frontends/stv0299.c val = stv0299_readreg (state, 0x08); val 307 drivers/media/dvb-frontends/stv0299.c if (stv0299_writeregI (state, 0x08, (val & ~0x7) | 0x2)) /* burst mode */ val 316 drivers/media/dvb-frontends/stv0299.c if (stv0299_writeregI (state, 0x08, val)) val 326 drivers/media/dvb-frontends/stv0299.c u8 val; val 331 drivers/media/dvb-frontends/stv0299.c val = stv0299_readreg (state, 0x08); val 335 drivers/media/dvb-frontends/stv0299.c return stv0299_writeregI (state, 0x08, val | 0x3); val 338 drivers/media/dvb-frontends/stv0299.c return stv0299_writeregI (state, 0x08, (val & ~0x3) | 0x02); val 450 drivers/media/dvb-frontends/stv0299.c u8 val; val 459 drivers/media/dvb-frontends/stv0299.c val = state->config->inittab[i+1]; val 460 drivers/media/dvb-frontends/stv0299.c if (reg == 0xff && val == 0xff) val 463 drivers/media/dvb-frontends/stv0299.c val &= ~0x10; val 465 drivers/media/dvb-frontends/stv0299.c state->mcr_reg = val & 0xf; val 466 drivers/media/dvb-frontends/stv0299.c stv0299_writeregI(state, reg, val); val 98 drivers/media/dvb-frontends/stv0299.h static inline int stv0299_writereg(struct dvb_frontend *fe, u8 reg, u8 val) { val 100 drivers/media/dvb-frontends/stv0299.h u8 buf[] = {reg, val}; val 212 drivers/media/dvb-frontends/stv0367.c static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val) val 219 drivers/media/dvb-frontends/stv0367.c val = mask & (val << pos); val 221 drivers/media/dvb-frontends/stv0367.c reg = (reg & (~mask)) | val; val 226 drivers/media/dvb-frontends/stv0367.c static void stv0367_setbits(u8 *reg, u32 label, u8 val) val 232 drivers/media/dvb-frontends/stv0367.c val = mask & (val << pos); val 234 drivers/media/dvb-frontends/stv0367.c (*reg) = ((*reg) & (~mask)) | val; val 239 drivers/media/dvb-frontends/stv0367.c u8 val = 0xff; val 244 drivers/media/dvb-frontends/stv0367.c val = stv0367_readreg(state, label >> 16); val 245 drivers/media/dvb-frontends/stv0367.c val = (val & mask) >> pos; val 247 drivers/media/dvb-frontends/stv0367.c return val; val 20 drivers/media/dvb-frontends/stv0900.h u8 val; val 180 drivers/media/dvb-frontends/stv0900_core.c void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val) val 187 drivers/media/dvb-frontends/stv0900_core.c val = mask & (val << pos); val 189 drivers/media/dvb-frontends/stv0900_core.c reg = (reg & (~mask)) | val; val 196 drivers/media/dvb-frontends/stv0900_core.c u8 val = 0xff; val 201 drivers/media/dvb-frontends/stv0900_core.c val = stv0900_read_reg(intp, label >> 16); val 202 drivers/media/dvb-frontends/stv0900_core.c val = (val & mask) >> pos; val 204 drivers/media/dvb-frontends/stv0900_core.c return val; val 1406 drivers/media/dvb-frontends/stv0900_core.c intp->ts_config[i].val); val 346 drivers/media/dvb-frontends/stv0900_priv.h u32 label, u8 val); val 3615 drivers/media/dvb-frontends/stv090x.c static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) val 3620 drivers/media/dvb-frontends/stv090x.c if ((val >= tab[min].read && val < tab[max].read) || val 3621 drivers/media/dvb-frontends/stv090x.c (val >= tab[max].read && val < tab[min].read)) { val 3624 drivers/media/dvb-frontends/stv090x.c if ((val >= tab[min].read && val < tab[med].read) || val 3625 drivers/media/dvb-frontends/stv090x.c (val >= tab[med].read && val < tab[min].read)) val 3630 drivers/media/dvb-frontends/stv090x.c res = ((val - tab[min].read) * val 3636 drivers/media/dvb-frontends/stv090x.c if (val < tab[min].read) val 3638 drivers/media/dvb-frontends/stv090x.c else if (val >= tab[max].read) val 3641 drivers/media/dvb-frontends/stv090x.c if (val >= tab[min].read) val 3643 drivers/media/dvb-frontends/stv090x.c else if (val < tab[max].read) val 3679 drivers/media/dvb-frontends/stv090x.c s32 val_0, val_1, val = 0; val 3695 drivers/media/dvb-frontends/stv090x.c val += MAKEWORD16(val_1, val_0); val 3698 drivers/media/dvb-frontends/stv090x.c val /= 16; val 3702 drivers/media/dvb-frontends/stv090x.c val = stv090x_table_lookup(stv090x_s2cn_tab, last, val); val 3703 drivers/media/dvb-frontends/stv090x.c if (val < 0) val 3704 drivers/media/dvb-frontends/stv090x.c val = 0; val 3705 drivers/media/dvb-frontends/stv090x.c *cnr = val * 0xFFFF / div; val 3720 drivers/media/dvb-frontends/stv090x.c val += MAKEWORD16(val_1, val_0); val 3723 drivers/media/dvb-frontends/stv090x.c val /= 16; val 3727 drivers/media/dvb-frontends/stv090x.c val = stv090x_table_lookup(stv090x_s1cn_tab, last, val); val 3728 drivers/media/dvb-frontends/stv090x.c *cnr = val * 0xFFFF / div; val 53 drivers/media/dvb-frontends/stv090x_priv.h #define STV090x_SETFIELD(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_##bitf) - 1) <<\ val 55 drivers/media/dvb-frontends/stv090x_priv.h (val << STV090x_OFFST_##bitf)) val 57 drivers/media/dvb-frontends/stv090x_priv.h #define STV090x_GETFIELD(val, bitf) ((val >> STV090x_OFFST_##bitf) & ((1 << STV090x_WIDTH_##bitf) - 1)) val 60 drivers/media/dvb-frontends/stv090x_priv.h #define STV090x_SETFIELD_Px(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_Px_##bitf) - 1) <<\ val 62 drivers/media/dvb-frontends/stv090x_priv.h (val << STV090x_OFFST_Px_##bitf)) val 64 drivers/media/dvb-frontends/stv090x_priv.h #define STV090x_GETFIELD_Px(val, bitf) ((val >> STV090x_OFFST_Px_##bitf) & ((1 << STV090x_WIDTH_Px_##bitf) - 1)) val 141 drivers/media/dvb-frontends/stv0910.c static int write_reg(struct stv *state, u16 reg, u8 val) val 144 drivers/media/dvb-frontends/stv0910.c u8 data[3] = {reg >> 8, reg & 0xff, val}; val 150 drivers/media/dvb-frontends/stv0910.c state->base->adr, reg, val); val 157 drivers/media/dvb-frontends/stv0910.c u16 reg, u8 *val, int count) val 163 drivers/media/dvb-frontends/stv0910.c .buf = val, .len = count } }; val 173 drivers/media/dvb-frontends/stv0910.c static int read_reg(struct stv *state, u16 reg, u8 *val) val 176 drivers/media/dvb-frontends/stv0910.c reg, val, 1); val 179 drivers/media/dvb-frontends/stv0910.c static int read_regs(struct stv *state, u16 reg, u8 *val, int len) val 182 drivers/media/dvb-frontends/stv0910.c reg, val, len); val 185 drivers/media/dvb-frontends/stv0910.c static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val) val 193 drivers/media/dvb-frontends/stv0910.c status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); val 198 drivers/media/dvb-frontends/stv0910.c static int write_field(struct stv *state, u32 field, u8 val) val 208 drivers/media/dvb-frontends/stv0910.c new = ((val << shift) & mask) | (old & ~mask); val 943 drivers/media/dvb-frontends/stv0910.c u8 val; val 947 drivers/media/dvb-frontends/stv0910.c val = 0x01; val 950 drivers/media/dvb-frontends/stv0910.c val = 0x02; val 953 drivers/media/dvb-frontends/stv0910.c val = 0x04; val 956 drivers/media/dvb-frontends/stv0910.c val = 0x08; val 959 drivers/media/dvb-frontends/stv0910.c val = 0x20; val 963 drivers/media/dvb-frontends/stv0910.c val = 0x2f; val 967 drivers/media/dvb-frontends/stv0910.c return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); val 1662 drivers/media/dvb-frontends/stv0910.c static int wait_dis(struct stv *state, u8 flag, u8 val) val 1670 drivers/media/dvb-frontends/stv0910.c if ((stat & flag) == val) val 37 drivers/media/dvb-frontends/stv6110x_priv.h #define STV6110x_SETFIELD(mask, bitf, val) \ val 40 drivers/media/dvb-frontends/stv6110x_priv.h (val << STV6110x_OFFST_##bitf)) val 42 drivers/media/dvb-frontends/stv6110x_priv.h #define STV6110x_GETFIELD(bitf, val) \ val 43 drivers/media/dvb-frontends/stv6110x_priv.h ((val >> STV6110x_OFFST_##bitf) & \ val 339 drivers/media/dvb-frontends/stv6111.c static int write_reg(struct stv *state, u8 reg, u8 val) val 341 drivers/media/dvb-frontends/stv6111.c u8 d[2] = {reg, val}; val 346 drivers/media/dvb-frontends/stv6111.c static int read_reg(struct stv *state, u8 reg, u8 *val) val 348 drivers/media/dvb-frontends/stv6111.c return i2c_read(state->i2c, state->adr, ®, 1, val, 1); val 42 drivers/media/dvb-frontends/tc90522.c u8 val; val 66 drivers/media/dvb-frontends/tc90522.c static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len) val 78 drivers/media/dvb-frontends/tc90522.c .buf = val, val 105 drivers/media/dvb-frontends/tc90522.c set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8; val 106 drivers/media/dvb-frontends/tc90522.c set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff; val 118 drivers/media/dvb-frontends/tc90522.c rv.val = laysel; val 202 drivers/media/dvb-frontends/tc90522.c u8 val[10]; val 210 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0xe6, val, 5); val 214 drivers/media/dvb-frontends/tc90522.c c->stream_id = val[0] << 8 | val[1]; val 217 drivers/media/dvb-frontends/tc90522.c v = (val[2] & 0x70) >> 4; val 222 drivers/media/dvb-frontends/tc90522.c c->layer[0].segment_count = val[3] & 0x3f; /* slots */ val 225 drivers/media/dvb-frontends/tc90522.c v = (val[2] & 0x07); val 230 drivers/media/dvb-frontends/tc90522.c c->layer[1].segment_count = val[4] & 0x3f; /* slots */ val 254 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0xbc, val, 2); val 256 drivers/media/dvb-frontends/tc90522.c cndat = val[0] << 8 | val[1]; val 285 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0xeb, val, 10); val 292 drivers/media/dvb-frontends/tc90522.c stats->stat[i].uvalue = val[i * 5] << 16 val 293 drivers/media/dvb-frontends/tc90522.c | val[i * 5 + 1] << 8 | val[i * 5 + 2]; val 306 drivers/media/dvb-frontends/tc90522.c val[i * 5 + 3] << 8 | val[i * 5 + 4]; val 337 drivers/media/dvb-frontends/tc90522.c u8 val[15], mode; val 344 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0xb0, val, 1); val 346 drivers/media/dvb-frontends/tc90522.c mode = (val[0] & 0xc0) >> 6; val 348 drivers/media/dvb-frontends/tc90522.c c->guard_interval = (val[0] & 0x30) >> 4; val 351 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0xb2, val, 6); val 356 drivers/media/dvb-frontends/tc90522.c c->isdbt_partial_reception = val[0] & 0x01; val 357 drivers/media/dvb-frontends/tc90522.c c->isdbt_sb_mode = (val[0] & 0xc0) == 0x40; val 360 drivers/media/dvb-frontends/tc90522.c v = (val[2] & 0x78) >> 3; val 366 drivers/media/dvb-frontends/tc90522.c c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2]; val 367 drivers/media/dvb-frontends/tc90522.c c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5]; val 368 drivers/media/dvb-frontends/tc90522.c v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7; val 373 drivers/media/dvb-frontends/tc90522.c v = (val[3] & 0x03) << 2 | (val[4] & 0xc0) >> 6; val 379 drivers/media/dvb-frontends/tc90522.c c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5]; val 380 drivers/media/dvb-frontends/tc90522.c c->layer[1].modulation = mod_conv[(val[2] & 0x07)]; val 381 drivers/media/dvb-frontends/tc90522.c c->layer[1].interleaving = (val[3] & 0x1c) >> 2; val 385 drivers/media/dvb-frontends/tc90522.c v = (val[5] & 0x1e) >> 1; val 391 drivers/media/dvb-frontends/tc90522.c c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)]; val 392 drivers/media/dvb-frontends/tc90522.c c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3]; val 393 drivers/media/dvb-frontends/tc90522.c c->layer[2].interleaving = (val[5] & 0xe0) >> 5; val 412 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0x8b, val, 3); val 414 drivers/media/dvb-frontends/tc90522.c cndat = val[0] << 16 | val[1] << 8 | val[2]; val 445 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0x9d, val, 15); val 452 drivers/media/dvb-frontends/tc90522.c stats->stat[i].uvalue = val[i * 3] << 16 val 453 drivers/media/dvb-frontends/tc90522.c | val[i * 3 + 1] << 8 | val[i * 3 + 2]; val 466 drivers/media/dvb-frontends/tc90522.c val[9 + i * 2] << 8 | val[9 + i * 2 + 1]; val 547 drivers/media/dvb-frontends/tc90522.c agc_sat[0].val = on ? 0xff : 0x00; val 548 drivers/media/dvb-frontends/tc90522.c agc_sat[1].val |= 0x80; val 549 drivers/media/dvb-frontends/tc90522.c agc_sat[1].val |= on ? 0x01 : 0x00; val 550 drivers/media/dvb-frontends/tc90522.c agc_sat[2].val |= on ? 0x40 : 0x00; val 554 drivers/media/dvb-frontends/tc90522.c agc_ter[0].val = on ? 0x40 : 0x00; val 555 drivers/media/dvb-frontends/tc90522.c agc_ter[1].val |= on ? 0x00 : 0x01; val 90 drivers/media/dvb-frontends/tda10023.c u8 val; val 91 drivers/media/dvb-frontends/tda10023.c val=tda10023_readreg(state,reg); val 92 drivers/media/dvb-frontends/tda10023.c val&=~mask; val 93 drivers/media/dvb-frontends/tda10023.c val|=(data&mask); val 94 drivers/media/dvb-frontends/tda10023.c return tda10023_writereg(state, reg, val); val 580 drivers/media/dvb-frontends/tda10048.c u8 val; val 586 drivers/media/dvb-frontends/tda10048.c val = tda10048_readreg(state, TDA10048_OUT_CONF2); val 587 drivers/media/dvb-frontends/tda10048.c switch ((val & 0x60) >> 5) { val 598 drivers/media/dvb-frontends/tda10048.c switch ((val & 0x18) >> 3) { val 612 drivers/media/dvb-frontends/tda10048.c switch (val & 0x07) { val 630 drivers/media/dvb-frontends/tda10048.c val = tda10048_readreg(state, TDA10048_OUT_CONF3); val 631 drivers/media/dvb-frontends/tda10048.c switch (val & 0x07) { val 649 drivers/media/dvb-frontends/tda10048.c val = tda10048_readreg(state, TDA10048_OUT_CONF1); val 650 drivers/media/dvb-frontends/tda10048.c switch ((val & 0x0c) >> 2) { val 664 drivers/media/dvb-frontends/tda10048.c switch (val & 0x03) { val 856 drivers/media/dvb-frontends/tda10048.c u8 val; val 994 drivers/media/dvb-frontends/tda10048.c if (v <= snr_tab[i].val) { val 162 drivers/media/dvb-frontends/tda1004x.c int val; val 167 drivers/media/dvb-frontends/tda1004x.c val = tda1004x_read_byte(state, reg); val 168 drivers/media/dvb-frontends/tda1004x.c if (val < 0) val 169 drivers/media/dvb-frontends/tda1004x.c return val; val 172 drivers/media/dvb-frontends/tda1004x.c val = val & ~mask; val 173 drivers/media/dvb-frontends/tda1004x.c val |= data & 0xff; val 176 drivers/media/dvb-frontends/tda1004x.c return tda1004x_write_byteI(state, reg, val); val 128 drivers/media/dvb-frontends/tda1004x.h static inline int tda1004x_writereg(struct dvb_frontend *fe, u8 reg, u8 val) { val 130 drivers/media/dvb-frontends/tda1004x.h u8 buf[] = {reg, val}; val 19 drivers/media/dvb-frontends/tda10071.c u8 reg, u8 val, u8 mask) val 30 drivers/media/dvb-frontends/tda10071.c val &= mask; val 32 drivers/media/dvb-frontends/tda10071.c val |= tmp; val 35 drivers/media/dvb-frontends/tda10071.c return regmap_bulk_write(dev->regmap, reg, &val, 1); val 638 drivers/media/dvb-frontends/tda10071.c mode = TDA10071_MODCOD[i].val; val 710 drivers/media/dvb-frontends/tda10071.c if (tmp == TDA10071_MODCOD[i].val) { val 823 drivers/media/dvb-frontends/tda10071.c tab[i].val, tab[i].mask); val 850 drivers/media/dvb-frontends/tda10071.c tab2[i].val, tab2[i].mask); val 1070 drivers/media/dvb-frontends/tda10071.c ret = tda10071_wr_reg_mask(dev, tab[i].reg, tab[i].val, val 41 drivers/media/dvb-frontends/tda10071_priv.h u8 val; val 72 drivers/media/dvb-frontends/tda10071_priv.h u8 val; val 78 drivers/media/dvb-frontends/tda10086.c int val; val 81 drivers/media/dvb-frontends/tda10086.c val = tda10086_read_byte(state, reg); val 82 drivers/media/dvb-frontends/tda10086.c if (val < 0) val 83 drivers/media/dvb-frontends/tda10086.c return val; val 86 drivers/media/dvb-frontends/tda10086.c val = val & ~mask; val 87 drivers/media/dvb-frontends/tda10086.c val |= data & 0xff; val 90 drivers/media/dvb-frontends/tda10086.c return tda10086_write_byte(state, reg, val); val 453 drivers/media/dvb-frontends/tda10086.c u8 val; val 473 drivers/media/dvb-frontends/tda10086.c val = tda10086_read_byte(state, 0x0c); val 474 drivers/media/dvb-frontends/tda10086.c if (val & 0x80) { val 475 drivers/media/dvb-frontends/tda10086.c switch(val & 0x40) { val 489 drivers/media/dvb-frontends/tda10086.c switch(val & 0x02) { val 512 drivers/media/dvb-frontends/tda10086.c val = (tda10086_read_byte(state, 0x0d) & 0x70) >> 4; val 513 drivers/media/dvb-frontends/tda10086.c switch(val) { val 547 drivers/media/dvb-frontends/tda10086.c u8 val; val 551 drivers/media/dvb-frontends/tda10086.c val = tda10086_read_byte(state, 0x0e); val 553 drivers/media/dvb-frontends/tda10086.c if (val & 0x01) val 555 drivers/media/dvb-frontends/tda10086.c if (val & 0x02) val 557 drivers/media/dvb-frontends/tda10086.c if (val & 0x04) val 559 drivers/media/dvb-frontends/tda10086.c if (val & 0x08) val 561 drivers/media/dvb-frontends/tda10086.c if (val & 0x10) { val 81 drivers/media/dvb-frontends/tda8083.c u8 val; val 83 drivers/media/dvb-frontends/tda8083.c tda8083_readregs (state, reg, &val, 1); val 85 drivers/media/dvb-frontends/tda8083.c return val; val 42 drivers/media/dvb-frontends/ts2020.c u8 val; val 139 drivers/media/dvb-frontends/ts2020.c reg_vals[i].val); val 123 drivers/media/dvb-frontends/ves1x93.c u8 val; val 132 drivers/media/dvb-frontends/ves1x93.c val = 0xc0; val 135 drivers/media/dvb-frontends/ves1x93.c val = 0x80; val 138 drivers/media/dvb-frontends/ves1x93.c val = 0x00; val 144 drivers/media/dvb-frontends/ves1x93.c return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val); val 256 drivers/media/dvb-frontends/ves1x93.c int val; val 262 drivers/media/dvb-frontends/ves1x93.c val = state->init_1x93_tab[i]; val 264 drivers/media/dvb-frontends/ves1x93.c if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */ val 265 drivers/media/dvb-frontends/ves1x93.c ves1x93_writereg (state, i, val); val 21 drivers/media/dvb-frontends/zd1301_demod.c static int zd1301_demod_wreg(struct zd1301_demod_dev *dev, u16 reg, u8 val) val 26 drivers/media/dvb-frontends/zd1301_demod.c return pdata->reg_write(pdata->reg_priv, reg, val); val 29 drivers/media/dvb-frontends/zd1301_demod.c static int zd1301_demod_rreg(struct zd1301_demod_dev *dev, u16 reg, u8 *val) val 34 drivers/media/dvb-frontends/zd1301_demod.c return pdata->reg_read(pdata->reg_priv, reg, val); val 118 drivers/media/dvb-frontends/zl10039.c const enum zl10039_reg_addr reg, u8 *val) val 120 drivers/media/dvb-frontends/zl10039.c return zl10039_read(state, reg, val, 1); val 125 drivers/media/dvb-frontends/zl10039.c const u8 val) val 127 drivers/media/dvb-frontends/zl10039.c const u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ val 39 drivers/media/dvb-frontends/zl10353.c static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val) val 42 drivers/media/dvb-frontends/zl10353.c u8 buf[2] = { reg, val }; val 572 drivers/media/dvb-frontends/zl10353.c u8 val = 0x0a; val 581 drivers/media/dvb-frontends/zl10353.c val |= 0x10; val 583 drivers/media/dvb-frontends/zl10353.c return zl10353_single_write(fe, 0x62, val); val 157 drivers/media/i2c/ad5820.c coil->focus_absolute = ctrl->val; val 117 drivers/media/i2c/ad9389b.c static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val) val 124 drivers/media/i2c/ad9389b.c ret = i2c_smbus_write_byte_data(client, reg, val); val 128 drivers/media/i2c/ad9389b.c v4l2_err(sd, "%s: failed reg 0x%x, val 0x%x\n", __func__, reg, val); val 242 drivers/media/i2c/ad9389b.c switch (ctrl->val) { val 306 drivers/media/i2c/ad9389b.c "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val); val 311 drivers/media/i2c/ad9389b.c ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00); val 328 drivers/media/i2c/ad9389b.c reg->val = ad9389b_rd(sd, reg->reg & 0xff); val 335 drivers/media/i2c/ad9389b.c ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff); val 46 drivers/media/i2c/adp1653.c flash->indicator_intensity->val) val 49 drivers/media/i2c/adp1653.c switch (flash->led_mode->val) { val 55 drivers/media/i2c/adp1653.c config |= TIMEOUT_US_TO_CODE(flash->flash_timeout->val) val 61 drivers/media/i2c/adp1653.c flash->torch_intensity->val) val 97 drivers/media/i2c/adp1653.c flash->led_mode->val = V4L2_FLASH_LED_MODE_NONE; val 110 drivers/media/i2c/adp1653.c flash->indicator_intensity->val) val 114 drivers/media/i2c/adp1653.c if (flash->led_mode->val != V4L2_FLASH_LED_MODE_FLASH) val 122 drivers/media/i2c/adp1653.c flash->flash_intensity->val) val 150 drivers/media/i2c/adp1653.c ctrl->cur.val = 0; val 153 drivers/media/i2c/adp1653.c ctrl->cur.val |= V4L2_FLASH_FAULT_SHORT_CIRCUIT; val 155 drivers/media/i2c/adp1653.c ctrl->cur.val |= V4L2_FLASH_FAULT_OVER_TEMPERATURE; val 157 drivers/media/i2c/adp1653.c ctrl->cur.val |= V4L2_FLASH_FAULT_TIMEOUT; val 159 drivers/media/i2c/adp1653.c ctrl->cur.val |= V4L2_FLASH_FAULT_OVER_VOLTAGE; val 268 drivers/media/i2c/adv7170.c u8 val = adv7170_read(sd, 0x7); val 273 drivers/media/i2c/adv7170.c if ((val & 0x40) == (1 << 6)) val 291 drivers/media/i2c/adv7170.c u8 val = adv7170_read(sd, 0x7); val 298 drivers/media/i2c/adv7170.c val &= ~0x40; val 302 drivers/media/i2c/adv7170.c val |= 0x40; val 312 drivers/media/i2c/adv7170.c return adv7170_write(sd, 0x7, val); val 183 drivers/media/i2c/adv7175.c static int adv7175_init(struct v4l2_subdev *sd, u32 val) val 306 drivers/media/i2c/adv7175.c u8 val = adv7175_read(sd, 0x7); val 311 drivers/media/i2c/adv7175.c if ((val & 0x40) == (1 << 6)) val 329 drivers/media/i2c/adv7175.c u8 val = adv7175_read(sd, 0x7); val 337 drivers/media/i2c/adv7175.c val &= ~0x40; val 341 drivers/media/i2c/adv7175.c val |= 0x40; val 351 drivers/media/i2c/adv7175.c ret = adv7175_write(sd, 0x7, val); val 489 drivers/media/i2c/adv7180.c u8 val; val 493 drivers/media/i2c/adv7180.c val = ADV7180_PWR_MAN_ON; val 495 drivers/media/i2c/adv7180.c val = ADV7180_PWR_MAN_OFF; val 497 drivers/media/i2c/adv7180.c ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); val 541 drivers/media/i2c/adv7180.c int val; val 545 drivers/media/i2c/adv7180.c val = ctrl->val; val 548 drivers/media/i2c/adv7180.c ret = adv7180_write(state, ADV7180_REG_BRI, val); val 552 drivers/media/i2c/adv7180.c ret = adv7180_write(state, ADV7180_REG_HUE, -val); val 555 drivers/media/i2c/adv7180.c ret = adv7180_write(state, ADV7180_REG_CON, val); val 562 drivers/media/i2c/adv7180.c ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); val 565 drivers/media/i2c/adv7180.c ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); val 568 drivers/media/i2c/adv7180.c if (ctrl->val) { val 228 drivers/media/i2c/adv7183.c static int adv7183_reset(struct v4l2_subdev *sd, u32 val) val 323 drivers/media/i2c/adv7183.c int val = ctrl->val; val 327 drivers/media/i2c/adv7183.c if (val < 0) val 328 drivers/media/i2c/adv7183.c val = 127 - val; val 329 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_BRIGHTNESS, val); val 332 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_CONTRAST, val); val 335 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_SD_SATURATION_CB, val >> 8); val 336 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_SD_SATURATION_CR, (val & 0xFF)); val 339 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_SD_OFFSET_CB, val >> 8); val 340 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_SD_OFFSET_CR, (val & 0xFF)); val 478 drivers/media/i2c/adv7183.c reg->val = adv7183_read(sd, reg->reg & 0xff); val 485 drivers/media/i2c/adv7183.c adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff); val 138 drivers/media/i2c/adv7343.c u8 reg, val; val 158 drivers/media/i2c/adv7343.c val = state->reg80 & (~(SD_STD_MASK)); val 159 drivers/media/i2c/adv7343.c val |= std_info[i].standard_val3; val 160 drivers/media/i2c/adv7343.c err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val); val 164 drivers/media/i2c/adv7343.c state->reg80 = val; val 167 drivers/media/i2c/adv7343.c val = state->reg01 & (~((u8) INPUT_MODE_MASK)); val 168 drivers/media/i2c/adv7343.c val |= SD_INPUT_MODE; val 169 drivers/media/i2c/adv7343.c err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val); val 173 drivers/media/i2c/adv7343.c state->reg01 = val; val 184 drivers/media/i2c/adv7343.c val = state->reg80; val 188 drivers/media/i2c/adv7343.c val &= 0x03; val 190 drivers/media/i2c/adv7343.c val |= 0x04; val 192 drivers/media/i2c/adv7343.c err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val); val 196 drivers/media/i2c/adv7343.c state->reg80 = val; val 208 drivers/media/i2c/adv7343.c unsigned char val; val 219 drivers/media/i2c/adv7343.c val = state->reg00 & 0x03; val 224 drivers/media/i2c/adv7343.c val |= ADV7343_COMPOSITE_POWER_VALUE; val 226 drivers/media/i2c/adv7343.c val |= ADV7343_COMPONENT_POWER_VALUE; val 228 drivers/media/i2c/adv7343.c val |= ADV7343_SVIDEO_POWER_VALUE; val 230 drivers/media/i2c/adv7343.c val = state->pdata->mode_config.sleep_mode << 0 | val 239 drivers/media/i2c/adv7343.c err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val); val 243 drivers/media/i2c/adv7343.c state->reg00 = val; val 246 drivers/media/i2c/adv7343.c val = state->reg02 | YUV_OUTPUT_SELECT; val 247 drivers/media/i2c/adv7343.c err = adv7343_write(sd, ADV7343_MODE_REG0, val); val 251 drivers/media/i2c/adv7343.c state->reg02 = val; val 254 drivers/media/i2c/adv7343.c val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI); val 257 drivers/media/i2c/adv7343.c val = val | (state->pdata->sd_config.sd_dac_out[0] << 1); val 259 drivers/media/i2c/adv7343.c val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1); val 262 drivers/media/i2c/adv7343.c val = val | (state->pdata->sd_config.sd_dac_out[1] << 2); val 264 drivers/media/i2c/adv7343.c val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2); val 266 drivers/media/i2c/adv7343.c err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val); val 270 drivers/media/i2c/adv7343.c state->reg82 = val; val 274 drivers/media/i2c/adv7343.c val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI); val 275 drivers/media/i2c/adv7343.c err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val); val 279 drivers/media/i2c/adv7343.c state->reg35 = val; val 305 drivers/media/i2c/adv7343.c ctrl->val); val 308 drivers/media/i2c/adv7343.c return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val); val 311 drivers/media/i2c/adv7343.c return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val); val 141 drivers/media/i2c/adv7393.c u32 val; val 162 drivers/media/i2c/adv7393.c val = state->reg80 & ~SD_STD_MASK; val 163 drivers/media/i2c/adv7393.c val |= std_info->standard_val3; val 164 drivers/media/i2c/adv7393.c err = adv7393_write(sd, ADV7393_SD_MODE_REG1, val); val 168 drivers/media/i2c/adv7393.c state->reg80 = val; val 171 drivers/media/i2c/adv7393.c val = state->reg01 & ~INPUT_MODE_MASK; val 172 drivers/media/i2c/adv7393.c val |= SD_INPUT_MODE; val 173 drivers/media/i2c/adv7393.c err = adv7393_write(sd, ADV7393_MODE_SELECT_REG, val); val 177 drivers/media/i2c/adv7393.c state->reg01 = val; val 180 drivers/media/i2c/adv7393.c val = std_info->fsc_val; val 182 drivers/media/i2c/adv7393.c err = adv7393_write(sd, reg, val); val 185 drivers/media/i2c/adv7393.c val >>= 8; val 188 drivers/media/i2c/adv7393.c val = state->reg82; val 192 drivers/media/i2c/adv7393.c val |= SD_PEDESTAL_EN; val 194 drivers/media/i2c/adv7393.c val &= SD_PEDESTAL_DI; val 196 drivers/media/i2c/adv7393.c err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val); val 200 drivers/media/i2c/adv7393.c state->reg82 = val; val 212 drivers/media/i2c/adv7393.c u8 val; val 223 drivers/media/i2c/adv7393.c val = state->reg00 & 0x03; val 226 drivers/media/i2c/adv7393.c val |= ADV7393_COMPOSITE_POWER_VALUE; val 228 drivers/media/i2c/adv7393.c val |= ADV7393_COMPONENT_POWER_VALUE; val 230 drivers/media/i2c/adv7393.c val |= ADV7393_SVIDEO_POWER_VALUE; val 232 drivers/media/i2c/adv7393.c err = adv7393_write(sd, ADV7393_POWER_MODE_REG, val); val 236 drivers/media/i2c/adv7393.c state->reg00 = val; val 239 drivers/media/i2c/adv7393.c val = state->reg02 | YUV_OUTPUT_SELECT; val 240 drivers/media/i2c/adv7393.c err = adv7393_write(sd, ADV7393_MODE_REG0, val); val 244 drivers/media/i2c/adv7393.c state->reg02 = val; val 247 drivers/media/i2c/adv7393.c val = state->reg82; val 249 drivers/media/i2c/adv7393.c val &= SD_DAC_OUT1_DI; val 251 drivers/media/i2c/adv7393.c val |= SD_DAC_OUT1_EN; val 252 drivers/media/i2c/adv7393.c err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val); val 256 drivers/media/i2c/adv7393.c state->reg82 = val; val 259 drivers/media/i2c/adv7393.c val = state->reg35 & HD_DAC_SWAP_DI; val 260 drivers/media/i2c/adv7393.c err = adv7393_write(sd, ADV7393_HD_MODE_REG6, val); val 264 drivers/media/i2c/adv7393.c state->reg35 = val; val 290 drivers/media/i2c/adv7393.c ctrl->val & SD_BRIGHTNESS_VALUE_MASK); val 294 drivers/media/i2c/adv7393.c ctrl->val - ADV7393_HUE_MIN); val 298 drivers/media/i2c/adv7393.c ctrl->val); val 428 drivers/media/i2c/adv748x/adv748x-afe.c ret = sdp_write(state, ADV748X_SDP_BRI, ctrl->val); val 432 drivers/media/i2c/adv748x/adv748x-afe.c ret = sdp_write(state, ADV748X_SDP_HUE, -ctrl->val); val 435 drivers/media/i2c/adv748x/adv748x-afe.c ret = sdp_write(state, ADV748X_SDP_CON, ctrl->val); val 438 drivers/media/i2c/adv748x/adv748x-afe.c ret = sdp_write(state, ADV748X_SDP_SD_SAT_U, ctrl->val); val 441 drivers/media/i2c/adv748x/adv748x-afe.c ret = sdp_write(state, ADV748X_SDP_SD_SAT_V, ctrl->val); val 444 drivers/media/i2c/adv748x/adv748x-afe.c enable = !!ctrl->val; val 452 drivers/media/i2c/adv748x/adv748x-afe.c enable ? ctrl->val - 1 : 0); val 105 drivers/media/i2c/adv748x/adv748x-core.c unsigned int val; val 107 drivers/media/i2c/adv748x/adv748x-core.c err = regmap_read(state->regmap[client_page], reg, &val); val 115 drivers/media/i2c/adv748x/adv748x-core.c return val; val 145 drivers/media/i2c/adv748x/adv748x-core.c unsigned int init_reg, const void *val, val 153 drivers/media/i2c/adv748x/adv748x-core.c return regmap_raw_write(regmap, init_reg, val, val_len); val 308 drivers/media/i2c/adv748x/adv748x-core.c int val; val 313 drivers/media/i2c/adv748x/adv748x-core.c val = tx_read(tx, ADV748X_CSI_FS_AS_LS); val 314 drivers/media/i2c/adv748x/adv748x-core.c if (val < 0) val 315 drivers/media/i2c/adv748x/adv748x-core.c return val; val 322 drivers/media/i2c/adv748x/adv748x-core.c WARN_ONCE((on && val & ADV748X_CSI_FS_AS_LS_UNKNOWN), val 117 drivers/media/i2c/adv748x/adv748x-hdmi.c int val; val 120 drivers/media/i2c/adv748x/adv748x-hdmi.c val = hdmi_read(state, ADV748X_HDMI_LW1); val 121 drivers/media/i2c/adv748x/adv748x-hdmi.c return (val & ADV748X_HDMI_LW1_VERT_FILTER) && val 122 drivers/media/i2c/adv748x/adv748x-hdmi.c (val & ADV748X_HDMI_LW1_DE_REGEN); val 489 drivers/media/i2c/adv748x/adv748x-hdmi.c unsigned int total_len, const u8 *val) val 505 drivers/media/i2c/adv748x/adv748x-hdmi.c i, val + i, len); val 645 drivers/media/i2c/adv748x/adv748x-hdmi.c ret = cp_write(state, ADV748X_CP_BRI, ctrl->val); val 648 drivers/media/i2c/adv748x/adv748x-hdmi.c ret = cp_write(state, ADV748X_CP_HUE, ctrl->val); val 651 drivers/media/i2c/adv748x/adv748x-hdmi.c ret = cp_write(state, ADV748X_CP_CON, ctrl->val); val 654 drivers/media/i2c/adv748x/adv748x-hdmi.c ret = cp_write(state, ADV748X_CP_SAT, ctrl->val); val 657 drivers/media/i2c/adv748x/adv748x-hdmi.c pattern = ctrl->val; val 392 drivers/media/i2c/adv748x/adv748x.h unsigned int init_reg, const void *val, val 195 drivers/media/i2c/adv7511-v4l2.c static int adv7511_wr(struct v4l2_subdev *sd, u8 reg, u8 val) val 202 drivers/media/i2c/adv7511-v4l2.c ret = i2c_smbus_write_byte_data(client, reg, val); val 256 drivers/media/i2c/adv7511-v4l2.c static int adv7511_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 263 drivers/media/i2c/adv7511-v4l2.c ret = i2c_smbus_write_byte_data(state->i2c_cec, reg, val); val 272 drivers/media/i2c/adv7511-v4l2.c u8 val) val 274 drivers/media/i2c/adv7511-v4l2.c return adv7511_cec_write(sd, reg, (adv7511_cec_read(sd, reg) & mask) | val); val 284 drivers/media/i2c/adv7511-v4l2.c static int adv7511_pktmem_wr(struct v4l2_subdev *sd, u8 reg, u8 val) val 291 drivers/media/i2c/adv7511-v4l2.c ret = i2c_smbus_write_byte_data(state->i2c_pktmem, reg, val); val 389 drivers/media/i2c/adv7511-v4l2.c switch (ctrl->val) { val 418 drivers/media/i2c/adv7511-v4l2.c v4l2_dbg(1, debug, sd, "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val); val 422 drivers/media/i2c/adv7511-v4l2.c adv7511_wr_and_or(sd, 0xaf, 0xfd, ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00); val 432 drivers/media/i2c/adv7511-v4l2.c state->content_type = ctrl->val; val 466 drivers/media/i2c/adv7511-v4l2.c reg->val = adv7511_rd(sd, reg->reg & 0xff); val 470 drivers/media/i2c/adv7511-v4l2.c reg->val = adv7511_cec_read(sd, reg->reg & 0xff); val 488 drivers/media/i2c/adv7511-v4l2.c adv7511_wr(sd, reg->reg & 0xff, reg->val & 0xff); val 492 drivers/media/i2c/adv7511-v4l2.c adv7511_cec_write(sd, reg->reg & 0xff, reg->val & 0xff); val 84 drivers/media/i2c/adv7604.c u8 val; val 342 drivers/media/i2c/adv7604.c unsigned int val; val 344 drivers/media/i2c/adv7604.c err = regmap_read(state->regmap[client_page], reg, &val); val 351 drivers/media/i2c/adv7604.c return val; val 361 drivers/media/i2c/adv7604.c unsigned int init_reg, const void *val, val 369 drivers/media/i2c/adv7604.c return regmap_raw_write(regmap, init_reg, val, val_len); val 381 drivers/media/i2c/adv7604.c static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 385 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); val 389 drivers/media/i2c/adv7604.c u8 val) val 391 drivers/media/i2c/adv7604.c return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); val 401 drivers/media/i2c/adv7604.c static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 405 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); val 415 drivers/media/i2c/adv7604.c static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 419 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); val 423 drivers/media/i2c/adv7604.c u8 val) val 425 drivers/media/i2c/adv7604.c return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); val 435 drivers/media/i2c/adv7604.c static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 439 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); val 449 drivers/media/i2c/adv7604.c static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 453 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); val 463 drivers/media/i2c/adv7604.c static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 467 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); val 470 drivers/media/i2c/adv7604.c static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 472 drivers/media/i2c/adv7604.c return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); val 482 drivers/media/i2c/adv7604.c static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 486 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); val 490 drivers/media/i2c/adv7604.c unsigned int total_len, const u8 *val) val 506 drivers/media/i2c/adv7604.c i, val + i, len); val 547 drivers/media/i2c/adv7604.c static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 551 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); val 554 drivers/media/i2c/adv7604.c static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 556 drivers/media/i2c/adv7604.c return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); val 559 drivers/media/i2c/adv7604.c static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 563 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); val 578 drivers/media/i2c/adv7604.c static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 582 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); val 585 drivers/media/i2c/adv7604.c static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 587 drivers/media/i2c/adv7604.c return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); val 597 drivers/media/i2c/adv7604.c static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 601 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); val 612 drivers/media/i2c/adv7604.c unsigned int val; val 619 drivers/media/i2c/adv7604.c err = regmap_read(state->regmap[page], reg, &val); val 621 drivers/media/i2c/adv7604.c return err ? err : val; val 625 drivers/media/i2c/adv7604.c static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) val 635 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[page], reg, val); val 644 drivers/media/i2c/adv7604.c adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); val 854 drivers/media/i2c/adv7604.c reg->val = ret; val 864 drivers/media/i2c/adv7604.c ret = adv76xx_write_reg(sd, reg->reg, reg->val); val 1204 drivers/media/i2c/adv7604.c cp_write(sd, 0x3c, ctrl->val); val 1207 drivers/media/i2c/adv7604.c cp_write(sd, 0x3a, ctrl->val); val 1210 drivers/media/i2c/adv7604.c cp_write(sd, 0x3b, ctrl->val); val 1213 drivers/media/i2c/adv7604.c cp_write(sd, 0x3d, ctrl->val); val 1216 drivers/media/i2c/adv7604.c state->rgb_quantization_range = ctrl->val; val 1226 drivers/media/i2c/adv7604.c afe_write(sd, 0xc8, ctrl->val); val 1231 drivers/media/i2c/adv7604.c cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); val 1234 drivers/media/i2c/adv7604.c cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); val 1235 drivers/media/i2c/adv7604.c cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); val 1236 drivers/media/i2c/adv7604.c cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); val 1248 drivers/media/i2c/adv7604.c ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; val 1250 drivers/media/i2c/adv7604.c ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; val 3349 drivers/media/i2c/adv7604.c unsigned int val, val2; val 3433 drivers/media/i2c/adv7604.c err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); val 3438 drivers/media/i2c/adv7604.c if (val != 0x68) { val 3448 drivers/media/i2c/adv7604.c &val); val 3453 drivers/media/i2c/adv7604.c val2 = val << 8; val 3456 drivers/media/i2c/adv7604.c &val); val 3461 drivers/media/i2c/adv7604.c val |= val2; val 3462 drivers/media/i2c/adv7604.c if ((state->info->type == ADV7611 && val != 0x2051) || val 3463 drivers/media/i2c/adv7604.c (state->info->type == ADV7612 && val != 0x2041)) { val 369 drivers/media/i2c/adv7842.c static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 373 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(client, reg, val); val 376 drivers/media/i2c/adv7842.c static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 378 drivers/media/i2c/adv7842.c return io_write(sd, reg, (io_read(sd, reg) & mask) | val); val 382 drivers/media/i2c/adv7842.c u8 reg, u8 mask, u8 val) val 384 drivers/media/i2c/adv7842.c return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); val 394 drivers/media/i2c/adv7842.c static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 398 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); val 408 drivers/media/i2c/adv7842.c static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 412 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_cec, reg, val); val 415 drivers/media/i2c/adv7842.c static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 417 drivers/media/i2c/adv7842.c return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); val 427 drivers/media/i2c/adv7842.c static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 431 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); val 441 drivers/media/i2c/adv7842.c static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 445 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); val 448 drivers/media/i2c/adv7842.c static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 450 drivers/media/i2c/adv7842.c return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); val 460 drivers/media/i2c/adv7842.c static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 464 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); val 467 drivers/media/i2c/adv7842.c static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 469 drivers/media/i2c/adv7842.c return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); val 479 drivers/media/i2c/adv7842.c static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 483 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_afe, reg, val); val 486 drivers/media/i2c/adv7842.c static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 488 drivers/media/i2c/adv7842.c return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); val 498 drivers/media/i2c/adv7842.c static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 502 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); val 505 drivers/media/i2c/adv7842.c static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 507 drivers/media/i2c/adv7842.c return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); val 517 drivers/media/i2c/adv7842.c static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 521 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_edid, reg, val); val 531 drivers/media/i2c/adv7842.c static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 535 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); val 538 drivers/media/i2c/adv7842.c static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 540 drivers/media/i2c/adv7842.c return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); val 550 drivers/media/i2c/adv7842.c static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 554 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_cp, reg, val); val 557 drivers/media/i2c/adv7842.c static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) val 559 drivers/media/i2c/adv7842.c return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); val 569 drivers/media/i2c/adv7842.c static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 573 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); val 696 drivers/media/i2c/adv7842.c u16 val = 0; val 699 drivers/media/i2c/adv7842.c val |= 1; /* port A */ val 701 drivers/media/i2c/adv7842.c val |= 2; /* port B */ val 702 drivers/media/i2c/adv7842.c return val; val 728 drivers/media/i2c/adv7842.c const u8 *val = state->vga_edid.edid; val 745 drivers/media/i2c/adv7842.c I2C_SMBUS_BLOCK_MAX, val + i); val 873 drivers/media/i2c/adv7842.c reg->val = io_read(sd, reg->reg & 0xff); val 876 drivers/media/i2c/adv7842.c reg->val = avlink_read(sd, reg->reg & 0xff); val 879 drivers/media/i2c/adv7842.c reg->val = cec_read(sd, reg->reg & 0xff); val 882 drivers/media/i2c/adv7842.c reg->val = infoframe_read(sd, reg->reg & 0xff); val 885 drivers/media/i2c/adv7842.c reg->val = sdp_io_read(sd, reg->reg & 0xff); val 888 drivers/media/i2c/adv7842.c reg->val = sdp_read(sd, reg->reg & 0xff); val 891 drivers/media/i2c/adv7842.c reg->val = afe_read(sd, reg->reg & 0xff); val 894 drivers/media/i2c/adv7842.c reg->val = rep_read(sd, reg->reg & 0xff); val 897 drivers/media/i2c/adv7842.c reg->val = edid_read(sd, reg->reg & 0xff); val 900 drivers/media/i2c/adv7842.c reg->val = hdmi_read(sd, reg->reg & 0xff); val 903 drivers/media/i2c/adv7842.c reg->val = cp_read(sd, reg->reg & 0xff); val 906 drivers/media/i2c/adv7842.c reg->val = vdp_read(sd, reg->reg & 0xff); val 919 drivers/media/i2c/adv7842.c u8 val = reg->val & 0xff; val 923 drivers/media/i2c/adv7842.c io_write(sd, reg->reg & 0xff, val); val 926 drivers/media/i2c/adv7842.c avlink_write(sd, reg->reg & 0xff, val); val 929 drivers/media/i2c/adv7842.c cec_write(sd, reg->reg & 0xff, val); val 932 drivers/media/i2c/adv7842.c infoframe_write(sd, reg->reg & 0xff, val); val 935 drivers/media/i2c/adv7842.c sdp_io_write(sd, reg->reg & 0xff, val); val 938 drivers/media/i2c/adv7842.c sdp_write(sd, reg->reg & 0xff, val); val 941 drivers/media/i2c/adv7842.c afe_write(sd, reg->reg & 0xff, val); val 944 drivers/media/i2c/adv7842.c rep_write(sd, reg->reg & 0xff, val); val 947 drivers/media/i2c/adv7842.c edid_write(sd, reg->reg & 0xff, val); val 950 drivers/media/i2c/adv7842.c hdmi_write(sd, reg->reg & 0xff, val); val 953 drivers/media/i2c/adv7842.c cp_write(sd, reg->reg & 0xff, val); val 956 drivers/media/i2c/adv7842.c vdp_write(sd, reg->reg & 0xff, val); val 1283 drivers/media/i2c/adv7842.c cp_write(sd, 0x3c, ctrl->val); val 1284 drivers/media/i2c/adv7842.c sdp_write(sd, 0x14, ctrl->val); val 1288 drivers/media/i2c/adv7842.c cp_write(sd, 0x3a, ctrl->val); val 1289 drivers/media/i2c/adv7842.c sdp_write(sd, 0x13, ctrl->val); val 1293 drivers/media/i2c/adv7842.c cp_write(sd, 0x3b, ctrl->val); val 1294 drivers/media/i2c/adv7842.c sdp_write(sd, 0x15, ctrl->val); val 1298 drivers/media/i2c/adv7842.c cp_write(sd, 0x3d, ctrl->val); val 1299 drivers/media/i2c/adv7842.c sdp_write(sd, 0x16, ctrl->val); val 1304 drivers/media/i2c/adv7842.c afe_write(sd, 0xc8, ctrl->val); val 1307 drivers/media/i2c/adv7842.c cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); val 1308 drivers/media/i2c/adv7842.c sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); val 1311 drivers/media/i2c/adv7842.c u8 R = (ctrl->val & 0xff0000) >> 16; val 1312 drivers/media/i2c/adv7842.c u8 G = (ctrl->val & 0x00ff00) >> 8; val 1313 drivers/media/i2c/adv7842.c u8 B = (ctrl->val & 0x0000ff); val 1341 drivers/media/i2c/adv7842.c state->rgb_quantization_range = ctrl->val; val 1353 drivers/media/i2c/adv7842.c ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; val 1355 drivers/media/i2c/adv7842.c ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; val 79 drivers/media/i2c/ak7375.c ctrl->val << 4, 2); val 203 drivers/media/i2c/ak7375.c int ret, val; val 208 drivers/media/i2c/ak7375.c for (val = ak7375_dev->focus->val & ~(AK7375_CTRL_STEPS - 1); val 209 drivers/media/i2c/ak7375.c val >= 0; val -= AK7375_CTRL_STEPS) { val 211 drivers/media/i2c/ak7375.c val << 4, 2); val 239 drivers/media/i2c/ak7375.c int ret, val; val 251 drivers/media/i2c/ak7375.c for (val = ak7375_dev->focus->val % AK7375_CTRL_STEPS; val 252 drivers/media/i2c/ak7375.c val <= ak7375_dev->focus->val; val 253 drivers/media/i2c/ak7375.c val += AK7375_CTRL_STEPS) { val 255 drivers/media/i2c/ak7375.c val << 4, 2); val 70 drivers/media/i2c/ak881x.c reg->val = reg_read(client, reg->reg); val 72 drivers/media/i2c/ak881x.c if (reg->val > 0xffff) val 86 drivers/media/i2c/ak881x.c if (reg_write(client, reg->reg, reg->val) < 0) val 334 drivers/media/i2c/bt819.c bt819_write(decoder, 0x0a, ctrl->val); val 338 drivers/media/i2c/bt819.c bt819_write(decoder, 0x0c, ctrl->val & 0xff); val 339 drivers/media/i2c/bt819.c bt819_setbit(decoder, 0x0b, 2, ((ctrl->val >> 8) & 0x01)); val 343 drivers/media/i2c/bt819.c bt819_write(decoder, 0x0d, (ctrl->val >> 7) & 0xff); val 344 drivers/media/i2c/bt819.c bt819_setbit(decoder, 0x0b, 1, ((ctrl->val >> 15) & 0x01)); val 348 drivers/media/i2c/bt819.c temp = (ctrl->val * 180) / 254; val 354 drivers/media/i2c/bt819.c bt819_write(decoder, 0x0f, ctrl->val); val 119 drivers/media/i2c/bt866.c u8 val; val 125 drivers/media/i2c/bt866.c val = encoder->reg[0xdc]; val 128 drivers/media/i2c/bt866.c val |= 0x40; /* CBSWAP */ val 130 drivers/media/i2c/bt866.c val &= ~0x40; /* !CBSWAP */ val 132 drivers/media/i2c/bt866.c bt866_write(encoder, 0xdc, val); val 134 drivers/media/i2c/bt866.c val = encoder->reg[0xcc]; val 136 drivers/media/i2c/bt866.c val |= 0x01; /* OSDBAR */ val 138 drivers/media/i2c/bt866.c val &= ~0x01; /* !OSDBAR */ val 139 drivers/media/i2c/bt866.c bt866_write(encoder, 0xcc, val); val 157 drivers/media/i2c/bt866.c val = encoder->reg[0xdc]; val 159 drivers/media/i2c/bt866.c val |= 1; /* SQUARE */ val 161 drivers/media/i2c/bt866.c val &= ~1; /* !SQUARE */ val 162 drivers/media/i2c/bt866.c bt866_write(client, 0xdc, val); val 40 drivers/media/i2c/cs3308.c reg->val = cs3308_read(sd, reg->reg & 0xffff); val 47 drivers/media/i2c/cs3308.c cs3308_write(sd, reg->reg & 0xffff, reg->val & 0xff); val 75 drivers/media/i2c/cs5345.c cs5345_write(sd, 0x04, ctrl->val ? 0x80 : 0); val 78 drivers/media/i2c/cs5345.c cs5345_write(sd, 0x07, ((u8)ctrl->val) & 0x3f); val 79 drivers/media/i2c/cs5345.c cs5345_write(sd, 0x08, ((u8)ctrl->val) & 0x3f); val 89 drivers/media/i2c/cs5345.c reg->val = cs5345_read(sd, reg->reg & 0x1f); val 95 drivers/media/i2c/cs5345.c cs5345_write(sd, reg->reg & 0x1f, reg->val & 0xff); val 83 drivers/media/i2c/cs53l32a.c cs53l32a_write(sd, 0x03, ctrl->val ? 0xf0 : 0x30); val 86 drivers/media/i2c/cs53l32a.c cs53l32a_write(sd, 0x04, (u8)ctrl->val); val 87 drivers/media/i2c/cs53l32a.c cs53l32a_write(sd, 0x05, (u8)ctrl->val); val 532 drivers/media/i2c/cx25840/cx25840-audio.c if (state->mute->val) val 535 drivers/media/i2c/cx25840/cx25840-audio.c set_volume(client, state->volume->val); val 540 drivers/media/i2c/cx25840/cx25840-audio.c 48 - (ctrl->val * 48 / 0xffff)); val 545 drivers/media/i2c/cx25840/cx25840-audio.c 48 - (ctrl->val * 48 / 0xffff)); val 548 drivers/media/i2c/cx25840/cx25840-audio.c set_balance(client, ctrl->val); val 1379 drivers/media/i2c/cx25840/cx25840-core.c u32 val; val 1554 drivers/media/i2c/cx25840/cx25840-core.c val = cx25840_read4(client, MODE_CTRL); val 1555 drivers/media/i2c/cx25840/cx25840-core.c val &= 0xFFFFF9FF; val 1558 drivers/media/i2c/cx25840/cx25840-core.c val |= 0x00000200; val 1559 drivers/media/i2c/cx25840/cx25840-core.c val &= ~0x2000; val 1560 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write4(client, MODE_CTRL, val); val 1562 drivers/media/i2c/cx25840/cx25840-core.c val = cx25840_read4(client, AFE_CTRL); val 1565 drivers/media/i2c/cx25840/cx25840-core.c val |= 0x00001000; val 1566 drivers/media/i2c/cx25840/cx25840-core.c val &= 0xfffffe7f; val 1571 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write4(client, AFE_CTRL, val); val 1715 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x414, ctrl->val - 128); val 1719 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x415, ctrl->val << 1); val 1724 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x418, ctrl->val << 1); val 1725 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x419, ctrl->val << 1); val 1727 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x420, ctrl->val << 1); val 1728 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x421, ctrl->val << 1); val 1734 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x41a, ctrl->val); val 1736 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x422, ctrl->val); val 2263 drivers/media/i2c/cx25840/cx25840-core.c static int cx25840_init(struct v4l2_subdev *sd, u32 val) val 2285 drivers/media/i2c/cx25840/cx25840-core.c cx25840_vconfig_add(state, val); val 2294 drivers/media/i2c/cx25840/cx25840-core.c static int cx25840_reset(struct v4l2_subdev *sd, u32 val) val 2345 drivers/media/i2c/cx25840/cx25840-core.c reg->val = cx25840_read(client, reg->reg & 0x0fff); val 2354 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff); val 2542 drivers/media/i2c/cx25840/cx25840-core.c int val = 0; val 2558 drivers/media/i2c/cx25840/cx25840-core.c val |= V4L2_TUNER_SUB_STEREO; val 2560 drivers/media/i2c/cx25840/cx25840-core.c val |= V4L2_TUNER_SUB_MONO; val 2563 drivers/media/i2c/cx25840/cx25840-core.c val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; val 2566 drivers/media/i2c/cx25840/cx25840-core.c val |= V4L2_TUNER_SUB_SAP; val 2568 drivers/media/i2c/cx25840/cx25840-core.c vt->rxsubchans = val; val 53 drivers/media/i2c/dw9714.c __be16 val = cpu_to_be16(data); val 55 drivers/media/i2c/dw9714.c ret = i2c_master_send(client, (const char *)&val, sizeof(val)); val 56 drivers/media/i2c/dw9714.c if (ret != sizeof(val)) { val 63 drivers/media/i2c/dw9714.c static int dw9714_t_focus_vcm(struct dw9714_device *dw9714_dev, u16 val) val 67 drivers/media/i2c/dw9714.c dw9714_dev->current_val = val; val 69 drivers/media/i2c/dw9714.c return dw9714_i2c_write(client, DW9714_VAL(val, DW9714_DEFAULT_S)); val 77 drivers/media/i2c/dw9714.c return dw9714_t_focus_vcm(dev_vcm, ctrl->val); val 199 drivers/media/i2c/dw9714.c int ret, val; val 201 drivers/media/i2c/dw9714.c for (val = dw9714_dev->current_val & ~(DW9714_CTRL_STEPS - 1); val 202 drivers/media/i2c/dw9714.c val >= 0; val -= DW9714_CTRL_STEPS) { val 204 drivers/media/i2c/dw9714.c DW9714_VAL(val, DW9714_DEFAULT_S)); val 223 drivers/media/i2c/dw9714.c int ret, val; val 225 drivers/media/i2c/dw9714.c for (val = dw9714_dev->current_val % DW9714_CTRL_STEPS; val 226 drivers/media/i2c/dw9714.c val < dw9714_dev->current_val + DW9714_CTRL_STEPS - 1; val 227 drivers/media/i2c/dw9714.c val += DW9714_CTRL_STEPS) { val 229 drivers/media/i2c/dw9714.c DW9714_VAL(val, DW9714_DEFAULT_S)); val 81 drivers/media/i2c/dw9807-vcm.c int val, ret; val 88 drivers/media/i2c/dw9807-vcm.c ret = readx_poll_timeout(dw9807_i2c_check, client, val, val <= 0, val 91 drivers/media/i2c/dw9807-vcm.c if (ret || val < 0) { val 97 drivers/media/i2c/dw9807-vcm.c return ret ? -EBUSY : val; val 120 drivers/media/i2c/dw9807-vcm.c dev_vcm->current_val = ctrl->val; val 121 drivers/media/i2c/dw9807-vcm.c return dw9807_set_dac(client, ctrl->val); val 250 drivers/media/i2c/dw9807-vcm.c int ret, val; val 252 drivers/media/i2c/dw9807-vcm.c for (val = dw9807_dev->current_val & ~(DW9807_CTRL_STEPS - 1); val 253 drivers/media/i2c/dw9807-vcm.c val >= 0; val -= DW9807_CTRL_STEPS) { val 254 drivers/media/i2c/dw9807-vcm.c ret = dw9807_set_dac(client, val); val 282 drivers/media/i2c/dw9807-vcm.c int ret, val; val 291 drivers/media/i2c/dw9807-vcm.c for (val = dw9807_dev->current_val % DW9807_CTRL_STEPS; val 292 drivers/media/i2c/dw9807-vcm.c val < dw9807_dev->current_val + DW9807_CTRL_STEPS - 1; val 293 drivers/media/i2c/dw9807-vcm.c val += DW9807_CTRL_STEPS) { val 294 drivers/media/i2c/dw9807-vcm.c ret = dw9807_set_dac(client, val); val 142 drivers/media/i2c/et8ek8/et8ek8_driver.c u16 reg, u32 *val) val 171 drivers/media/i2c/et8ek8/et8ek8_driver.c *val = 0; val 174 drivers/media/i2c/et8ek8/et8ek8_driver.c *val = data[0]; val 176 drivers/media/i2c/et8ek8/et8ek8_driver.c *val = (data[1] << 8) + data[0]; val 187 drivers/media/i2c/et8ek8/et8ek8_driver.c u32 val, struct i2c_msg *msg, val 201 drivers/media/i2c/et8ek8/et8ek8_driver.c buf[2] = (u8) (val) & 0xff; val 204 drivers/media/i2c/et8ek8/et8ek8_driver.c buf[2] = (u8) (val) & 0xff; val 205 drivers/media/i2c/et8ek8/et8ek8_driver.c buf[3] = (u8) (val >> 8) & 0xff; val 226 drivers/media/i2c/et8ek8/et8ek8_driver.c u32 val; val 233 drivers/media/i2c/et8ek8/et8ek8_driver.c val = wnext->val; val 237 drivers/media/i2c/et8ek8/et8ek8_driver.c val, &msg[wcnt], &data[wcnt][0]); val 317 drivers/media/i2c/et8ek8/et8ek8_driver.c msleep(next->val); val 336 drivers/media/i2c/et8ek8/et8ek8_driver.c u16 reg, u32 val) val 347 drivers/media/i2c/et8ek8/et8ek8_driver.c et8ek8_i2c_create_msg(client, data_length, reg, val, &msg, data); val 352 drivers/media/i2c/et8ek8/et8ek8_driver.c "wrote 0x%x to offset 0x%x error %d\n", val, reg, r); val 643 drivers/media/i2c/et8ek8/et8ek8_driver.c return et8ek8_set_gain(sensor, ctrl->val); val 651 drivers/media/i2c/et8ek8/et8ek8_driver.c ctrl->val); val 655 drivers/media/i2c/et8ek8/et8ek8_driver.c return et8ek8_set_test_pattern(sensor, ctrl->val); val 820 drivers/media/i2c/et8ek8/et8ek8_driver.c int val, rval; val 860 drivers/media/i2c/et8ek8/et8ek8_driver.c rval = et8ek8_i2c_read_reg(client, ET8EK8_REG_8BIT, 0x1263, &val); val 864 drivers/media/i2c/et8ek8/et8ek8_driver.c val |= BIT(4); val 866 drivers/media/i2c/et8ek8/et8ek8_driver.c val &= ~BIT(4); val 868 drivers/media/i2c/et8ek8/et8ek8_driver.c rval = et8ek8_i2c_write_reg(client, ET8EK8_REG_8BIT, 0x1263, val); val 54 drivers/media/i2c/et8ek8/et8ek8_reg.h u32 val; /* 8/16/32-bit value */ val 66 drivers/media/i2c/imx214.c u8 val; val 509 drivers/media/i2c/imx214.c return regmap_write(imx214->regmap, reg->reg, reg->val); val 521 drivers/media/i2c/imx214.c reg->val = aux; val 664 drivers/media/i2c/imx214.c vals[1] = ctrl->val; val 665 drivers/media/i2c/imx214.c vals[0] = ctrl->val >> 8; val 695 drivers/media/i2c/imx214.c usleep_range(table->val * 1000, val 696 drivers/media/i2c/imx214.c table->val * 1000 + 500); val 703 drivers/media/i2c/imx214.c vals[i] = table[i].val; val 73 drivers/media/i2c/imx258.c u8 val; val 621 drivers/media/i2c/imx258.c static int imx258_read_reg(struct imx258 *imx258, u16 reg, u32 len, u32 *val) val 648 drivers/media/i2c/imx258.c *val = get_unaligned_be32(data_buf); val 654 drivers/media/i2c/imx258.c static int imx258_write_reg(struct imx258 *imx258, u16 reg, u32 len, u32 val) val 663 drivers/media/i2c/imx258.c put_unaligned_be32(val << (8 * (4 - len)), buf + 2); val 680 drivers/media/i2c/imx258.c regs[i].val); val 709 drivers/media/i2c/imx258.c static int imx258_update_digital_gain(struct imx258 *imx258, u32 len, u32 val) val 715 drivers/media/i2c/imx258.c val); val 720 drivers/media/i2c/imx258.c val); val 725 drivers/media/i2c/imx258.c val); val 730 drivers/media/i2c/imx258.c val); val 754 drivers/media/i2c/imx258.c ctrl->val); val 759 drivers/media/i2c/imx258.c ctrl->val); val 763 drivers/media/i2c/imx258.c ctrl->val); val 768 drivers/media/i2c/imx258.c ctrl->val); val 771 drivers/media/i2c/imx258.c !ctrl->val ? REG_CONFIG_MIRROR_FLIP : val 777 drivers/media/i2c/imx258.c ctrl->id, ctrl->val); val 1057 drivers/media/i2c/imx258.c u32 val; val 1060 drivers/media/i2c/imx258.c IMX258_REG_VALUE_16BIT, &val); val 1067 drivers/media/i2c/imx258.c if (val != IMX258_CHIP_ID) { val 1069 drivers/media/i2c/imx258.c IMX258_CHIP_ID, val); val 1202 drivers/media/i2c/imx258.c u32 val = 0; val 1204 drivers/media/i2c/imx258.c device_property_read_u32(&client->dev, "clock-frequency", &val); val 1205 drivers/media/i2c/imx258.c if (val != 19200000) val 1212 drivers/media/i2c/imx258.c ret = device_property_read_u32(&client->dev, "rotation", &val); val 1213 drivers/media/i2c/imx258.c if (ret || val != 180) val 139 drivers/media/i2c/imx274.c u8 val; val 532 drivers/media/i2c/imx274.c static int imx274_set_exposure(struct stimx274 *priv, int val); val 533 drivers/media/i2c/imx274.c static int imx274_set_vflip(struct stimx274 *priv, int val); val 534 drivers/media/i2c/imx274.c static int imx274_set_test_pattern(struct stimx274 *priv, int val); val 572 drivers/media/i2c/imx274.c u8 val; val 605 drivers/media/i2c/imx274.c msleep_range(next->val); val 610 drivers/media/i2c/imx274.c val = next->val; val 615 drivers/media/i2c/imx274.c range_vals[range_count++] = val; val 620 drivers/media/i2c/imx274.c static inline int imx274_write_reg(struct stimx274 *priv, u16 addr, u8 val) val 624 drivers/media/i2c/imx274.c err = regmap_write(priv->regmap, addr, val); val 628 drivers/media/i2c/imx274.c addr, val); val 632 drivers/media/i2c/imx274.c addr, val); val 650 drivers/media/i2c/imx274.c static int imx274_read_mbreg(struct stimx274 *priv, u16 addr, u32 *val, val 662 drivers/media/i2c/imx274.c *val = le32_to_cpu(val_le); val 665 drivers/media/i2c/imx274.c __func__, addr, *val, nbytes); val 682 drivers/media/i2c/imx274.c static int imx274_write_mbreg(struct stimx274 *priv, u16 addr, u32 val, val 685 drivers/media/i2c/imx274.c __le32 val_le = cpu_to_le32(val); val 692 drivers/media/i2c/imx274.c __func__, addr, val, nbytes); val 696 drivers/media/i2c/imx274.c __func__, addr, val, nbytes); val 786 drivers/media/i2c/imx274.c ctrl->name, ctrl->val); val 792 drivers/media/i2c/imx274.c ret = imx274_set_exposure(imx274, ctrl->val); val 804 drivers/media/i2c/imx274.c ret = imx274_set_vflip(imx274, ctrl->val); val 810 drivers/media/i2c/imx274.c ret = imx274_set_test_pattern(imx274, ctrl->val); val 823 drivers/media/i2c/imx274.c int val = 0; val 827 drivers/media/i2c/imx274.c val -= goodness; val 829 drivers/media/i2c/imx274.c val -= goodness; val 834 drivers/media/i2c/imx274.c val -= goodness; val 836 drivers/media/i2c/imx274.c val -= goodness; val 839 drivers/media/i2c/imx274.c val -= abs(w - ask_w); val 840 drivers/media/i2c/imx274.c val -= abs(h - ask_h); val 843 drivers/media/i2c/imx274.c __func__, ask_w, ask_h, w, h, val); val 845 drivers/media/i2c/imx274.c return val; val 1162 drivers/media/i2c/imx274.c v_pos = imx274->ctrls.vflip->cur.val ? val 1253 drivers/media/i2c/imx274.c imx274_set_exposure(imx274, ctrl->val); val 1279 drivers/media/i2c/imx274.c priv->ctrls.exposure->val = 1000000 / IMX274_DEF_FRAME_RATE; val 1280 drivers/media/i2c/imx274.c priv->ctrls.gain->val = IMX274_DEF_GAIN; val 1281 drivers/media/i2c/imx274.c priv->ctrls.vflip->val = 0; val 1282 drivers/media/i2c/imx274.c priv->ctrls.test_pattern->val = TEST_PATTERN_DISABLED; val 1291 drivers/media/i2c/imx274.c ret = v4l2_ctrl_s_ctrl(priv->ctrls.exposure, priv->ctrls.exposure->val); val 1296 drivers/media/i2c/imx274.c ret = v4l2_ctrl_s_ctrl(priv->ctrls.gain, priv->ctrls.gain->val); val 1301 drivers/media/i2c/imx274.c ret = v4l2_ctrl_s_ctrl(priv->ctrls.vflip, priv->ctrls.vflip->val); val 1352 drivers/media/i2c/imx274.c imx274->ctrls.exposure->val); val 1386 drivers/media/i2c/imx274.c static int imx274_get_frame_length(struct stimx274 *priv, u32 *val) val 1400 drivers/media/i2c/imx274.c *val = vmax * (svr + 1); val 1409 drivers/media/i2c/imx274.c static int imx274_clamp_coarse_time(struct stimx274 *priv, u32 *val, val 1421 drivers/media/i2c/imx274.c *val = *frame_length - *val; /* convert to raw shr */ val 1422 drivers/media/i2c/imx274.c if (*val > *frame_length - IMX274_SHR_LIMIT_CONST) val 1423 drivers/media/i2c/imx274.c *val = *frame_length - IMX274_SHR_LIMIT_CONST; val 1424 drivers/media/i2c/imx274.c else if (*val < priv->mode->min_SHR) val 1425 drivers/media/i2c/imx274.c *val = priv->mode->min_SHR; val 1470 drivers/media/i2c/imx274.c gain = (u32)(ctrl->val); val 1520 drivers/media/i2c/imx274.c ctrl->val = (IMX274_GAIN_CONST << IMX274_GAIN_SHIFT) val 1525 drivers/media/i2c/imx274.c __func__, gain_reg, ctrl->val); val 1543 drivers/media/i2c/imx274.c static int imx274_set_coarse_time(struct stimx274 *priv, u32 *val) val 1548 drivers/media/i2c/imx274.c coarse_time = *val; val 1559 drivers/media/i2c/imx274.c *val = frame_length - coarse_time; val 1577 drivers/media/i2c/imx274.c static int imx274_set_exposure(struct stimx274 *priv, int val) val 1584 drivers/media/i2c/imx274.c "%s : EXPOSURE control input = %d\n", __func__, val); val 1597 drivers/media/i2c/imx274.c coarse_time = (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2 * val val 1607 drivers/media/i2c/imx274.c priv->ctrls.exposure->val = val 1633 drivers/media/i2c/imx274.c static int imx274_set_vflip(struct stimx274 *priv, int val) val 1637 drivers/media/i2c/imx274.c err = imx274_write_reg(priv, IMX274_VFLIP_REG, val); val 1658 drivers/media/i2c/imx274.c static int imx274_set_test_pattern(struct stimx274 *priv, int val) val 1662 drivers/media/i2c/imx274.c if (val == TEST_PATTERN_DISABLED) { val 1664 drivers/media/i2c/imx274.c } else if (val <= TEST_PATTERN_V_COLOR_BARS) { val 1665 drivers/media/i2c/imx274.c err = imx274_write_reg(priv, IMX274_TEST_PATTERN_REG, val - 1); val 1690 drivers/media/i2c/imx274.c static int imx274_set_frame_length(struct stimx274 *priv, u32 val) val 1696 drivers/media/i2c/imx274.c __func__, val); val 1698 drivers/media/i2c/imx274.c frame_length = (u32)val; val 79 drivers/media/i2c/imx319.c u8 val; val 1781 drivers/media/i2c/imx319.c code = codes[imx319->vflip->val][imx319->hflip->val]; val 1787 drivers/media/i2c/imx319.c static int imx319_read_reg(struct imx319 *imx319, u16 reg, u32 len, u32 *val) val 1815 drivers/media/i2c/imx319.c *val = get_unaligned_be32(data_buf); val 1821 drivers/media/i2c/imx319.c static int imx319_write_reg(struct imx319 *imx319, u16 reg, u32 len, u32 val) val 1830 drivers/media/i2c/imx319.c put_unaligned_be32(val << (8 * (4 - len)), buf + 2); val 1846 drivers/media/i2c/imx319.c ret = imx319_write_reg(imx319, regs[i].address, 1, regs[i].val); val 1890 drivers/media/i2c/imx319.c max = imx319->cur_mode->height + ctrl->val - 18; val 1908 drivers/media/i2c/imx319.c ctrl->val); val 1912 drivers/media/i2c/imx319.c ctrl->val); val 1916 drivers/media/i2c/imx319.c ctrl->val); val 1921 drivers/media/i2c/imx319.c imx319->cur_mode->height + ctrl->val); val 1925 drivers/media/i2c/imx319.c 2, ctrl->val); val 1930 drivers/media/i2c/imx319.c imx319->hflip->val | val 1931 drivers/media/i2c/imx319.c imx319->vflip->val << 1); val 1936 drivers/media/i2c/imx319.c ctrl->id, ctrl->val); val 2218 drivers/media/i2c/imx319.c u32 val; val 2220 drivers/media/i2c/imx319.c ret = imx319_read_reg(imx319, IMX319_REG_CHIP_ID, 2, &val); val 2224 drivers/media/i2c/imx319.c if (val != IMX319_CHIP_ID) { val 2226 drivers/media/i2c/imx319.c IMX319_CHIP_ID, val); val 65 drivers/media/i2c/imx355.c u8 val; val 1081 drivers/media/i2c/imx355.c code = codes[imx355->vflip->val][imx355->hflip->val]; val 1087 drivers/media/i2c/imx355.c static int imx355_read_reg(struct imx355 *imx355, u16 reg, u32 len, u32 *val) val 1115 drivers/media/i2c/imx355.c *val = get_unaligned_be32(data_buf); val 1121 drivers/media/i2c/imx355.c static int imx355_write_reg(struct imx355 *imx355, u16 reg, u32 len, u32 val) val 1130 drivers/media/i2c/imx355.c put_unaligned_be32(val << (8 * (4 - len)), buf + 2); val 1146 drivers/media/i2c/imx355.c ret = imx355_write_reg(imx355, regs[i].address, 1, regs[i].val); val 1191 drivers/media/i2c/imx355.c max = imx355->cur_mode->height + ctrl->val - 10; val 1209 drivers/media/i2c/imx355.c ctrl->val); val 1213 drivers/media/i2c/imx355.c ctrl->val); val 1217 drivers/media/i2c/imx355.c ctrl->val); val 1222 drivers/media/i2c/imx355.c imx355->cur_mode->height + ctrl->val); val 1226 drivers/media/i2c/imx355.c 2, ctrl->val); val 1231 drivers/media/i2c/imx355.c imx355->hflip->val | val 1232 drivers/media/i2c/imx355.c imx355->vflip->val << 1); val 1237 drivers/media/i2c/imx355.c ctrl->id, ctrl->val); val 1519 drivers/media/i2c/imx355.c u32 val; val 1521 drivers/media/i2c/imx355.c ret = imx355_read_reg(imx355, IMX355_REG_CHIP_ID, 2, &val); val 1525 drivers/media/i2c/imx355.c if (val != IMX355_CHIP_ID) { val 1527 drivers/media/i2c/imx355.c IMX355_CHIP_ID, val); val 480 drivers/media/i2c/ir-kbd-i2c.c static int find_slot(u16 *array, unsigned int size, u16 val) val 485 drivers/media/i2c/ir-kbd-i2c.c if (get_unaligned_be16(&array[i]) == val) { val 488 drivers/media/i2c/ir-kbd-i2c.c put_unaligned_be16(val, &array[i]); val 305 drivers/media/i2c/ks0127.c char val = 0; val 315 drivers/media/i2c/ks0127.c .len = sizeof(val), val 316 drivers/media/i2c/ks0127.c .buf = &val val 325 drivers/media/i2c/ks0127.c return val; val 329 drivers/media/i2c/ks0127.c static void ks0127_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 333 drivers/media/i2c/ks0127.c char msg[] = { reg, val }; val 338 drivers/media/i2c/ks0127.c ks->regs[reg] = val; val 347 drivers/media/i2c/ks0127.c u8 val = ks->regs[reg]; val 348 drivers/media/i2c/ks0127.c val = (val & and_v) | or_v; val 349 drivers/media/i2c/ks0127.c ks0127_write(sd, reg, val); val 179 drivers/media/i2c/lm3560.c ctrl->cur.val = fault; val 197 drivers/media/i2c/lm3560.c flash->led_mode = ctrl->val; val 204 drivers/media/i2c/lm3560.c REG_CONFIG1, 0x04, (ctrl->val) << 2); val 228 drivers/media/i2c/lm3560.c tout_bits = LM3560_FLASH_TOUT_ms_TO_REG(ctrl->val); val 234 drivers/media/i2c/lm3560.c rval = lm3560_flash_brt_ctrl(flash, led_no, ctrl->val); val 238 drivers/media/i2c/lm3560.c rval = lm3560_torch_brt_ctrl(flash, led_no, ctrl->val); val 112 drivers/media/i2c/lm3646.c ctrl->val = 0; val 114 drivers/media/i2c/lm3646.c ctrl->val |= V4L2_FLASH_FAULT_TIMEOUT; val 116 drivers/media/i2c/lm3646.c ctrl->val |= V4L2_FLASH_FAULT_SHORT_CIRCUIT; val 118 drivers/media/i2c/lm3646.c ctrl->val |= V4L2_FLASH_FAULT_UNDER_VOLTAGE; val 120 drivers/media/i2c/lm3646.c ctrl->val |= V4L2_FLASH_FAULT_INPUT_VOLTAGE; val 122 drivers/media/i2c/lm3646.c ctrl->val |= V4L2_FLASH_FAULT_OVER_CURRENT; val 124 drivers/media/i2c/lm3646.c ctrl->val |= V4L2_FLASH_FAULT_OVER_TEMPERATURE; val 126 drivers/media/i2c/lm3646.c ctrl->val |= V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE; val 128 drivers/media/i2c/lm3646.c ctrl->val |= V4L2_FLASH_FAULT_OVER_VOLTAGE; val 142 drivers/media/i2c/lm3646.c if (ctrl->val != V4L2_FLASH_LED_MODE_FLASH) val 143 drivers/media/i2c/lm3646.c return lm3646_mode_ctrl(flash, ctrl->val); val 150 drivers/media/i2c/lm3646.c (ctrl->val) << 7); val 180 drivers/media/i2c/lm3646.c (ctrl->val)); val 186 drivers/media/i2c/lm3646.c (ctrl->val)); val 192 drivers/media/i2c/lm3646.c (ctrl->val) << 4); val 76 drivers/media/i2c/m52790.c reg->val = state->input | state->output; val 86 drivers/media/i2c/m52790.c state->input = reg->val & 0x0303; val 87 drivers/media/i2c/m52790.c state->output = reg->val & ~0x0303; val 272 drivers/media/i2c/m5mols/m5mols.h int m5mols_read_u8(struct v4l2_subdev *sd, u32 reg_comb, u8 *val); val 273 drivers/media/i2c/m5mols/m5mols.h int m5mols_read_u16(struct v4l2_subdev *sd, u32 reg_comb, u16 *val); val 274 drivers/media/i2c/m5mols/m5mols.h int m5mols_read_u32(struct v4l2_subdev *sd, u32 reg_comb, u32 *val); val 275 drivers/media/i2c/m5mols/m5mols.h int m5mols_write(struct v4l2_subdev *sd, u32 reg_comb, u32 val); val 41 drivers/media/i2c/m5mols/m5mols_capture.c u32 addr_den, u32 *val) val 50 drivers/media/i2c/m5mols/m5mols_capture.c *val = den == 0 ? 0 : num / den; val 188 drivers/media/i2c/m5mols/m5mols_controls.c bool af_lock = ctrl->val & V4L2_LOCK_FOCUS; val 191 drivers/media/i2c/m5mols/m5mols_controls.c if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE) { val 192 drivers/media/i2c/m5mols/m5mols_controls.c bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; val 200 drivers/media/i2c/m5mols/m5mols_controls.c if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE) val 201 drivers/media/i2c/m5mols/m5mols_controls.c && info->auto_wb->val) { val 202 drivers/media/i2c/m5mols/m5mols_controls.c bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; val 213 drivers/media/i2c/m5mols/m5mols_controls.c if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_FOCUS) val 245 drivers/media/i2c/m5mols/m5mols_controls.c info->lock_3a->val &= ~V4L2_LOCK_EXPOSURE; val 248 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_set_metering_mode(info, info->metering->val); val 254 drivers/media/i2c/m5mols/m5mols_controls.c __func__, info->exposure_bias->val, val 255 drivers/media/i2c/m5mols/m5mols_controls.c info->metering->val); val 257 drivers/media/i2c/m5mols/m5mols_controls.c return m5mols_write(sd, AE_INDEX, info->exposure_bias->val); val 264 drivers/media/i2c/m5mols/m5mols_controls.c info->exposure->val); val 267 drivers/media/i2c/m5mols/m5mols_controls.c info->exposure->val); val 270 drivers/media/i2c/m5mols/m5mols_controls.c __func__, info->exposure->val); val 276 drivers/media/i2c/m5mols/m5mols_controls.c static int m5mols_set_white_balance(struct m5mols_info *info, int val) val 295 drivers/media/i2c/m5mols/m5mols_controls.c if (wb[i][0] != val) val 314 drivers/media/i2c/m5mols/m5mols_controls.c static int m5mols_set_saturation(struct m5mols_info *info, int val) val 316 drivers/media/i2c/m5mols/m5mols_controls.c int ret = m5mols_write(&info->sd, MON_CHROMA_LVL, val); val 323 drivers/media/i2c/m5mols/m5mols_controls.c static int m5mols_set_color_effect(struct m5mols_info *info, int val) val 331 drivers/media/i2c/m5mols/m5mols_controls.c switch (val) { val 367 drivers/media/i2c/m5mols/m5mols_controls.c u32 iso = auto_iso ? 0 : info->iso->val + 1; val 387 drivers/media/i2c/m5mols/m5mols_controls.c static int m5mols_set_stabilization(struct m5mols_info *info, int val) val 390 drivers/media/i2c/m5mols/m5mols_controls.c unsigned int evp = val ? 0xe : 0x0; val 417 drivers/media/i2c/m5mols/m5mols_controls.c ctrl->val = !status; val 419 drivers/media/i2c/m5mols/m5mols_controls.c info->iso->val = status - 1; val 423 drivers/media/i2c/m5mols/m5mols_controls.c ctrl->val &= ~0x7; val 429 drivers/media/i2c/m5mols/m5mols_controls.c info->lock_3a->val |= V4L2_LOCK_EXPOSURE; val 435 drivers/media/i2c/m5mols/m5mols_controls.c info->lock_3a->val |= V4L2_LOCK_EXPOSURE; val 439 drivers/media/i2c/m5mols/m5mols_controls.c info->lock_3a->val |= V4L2_LOCK_EXPOSURE; val 464 drivers/media/i2c/m5mols/m5mols_controls.c __func__, ctrl->name, ctrl->val, ctrl->priv); val 478 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_write(sd, MON_ZOOM, ctrl->val); val 482 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_set_exposure(info, ctrl->val); val 486 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_set_iso(info, ctrl->val); val 490 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_set_white_balance(info, ctrl->val); val 494 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_set_saturation(info, ctrl->val); val 498 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_set_color_effect(info, ctrl->val); val 502 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_set_wdr(info, ctrl->val); val 506 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_set_stabilization(info, ctrl->val); val 510 drivers/media/i2c/m5mols/m5mols_controls.c ret = m5mols_write(sd, CAPP_JPEG_RATIO, ctrl->val); val 139 drivers/media/i2c/m5mols/m5mols_core.c static int m5mols_read(struct v4l2_subdev *sd, u32 size, u32 reg, u32 *val) val 174 drivers/media/i2c/m5mols/m5mols_core.c *val = m5mols_swap_byte(&rbuf[1], size); val 185 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_read_u8(struct v4l2_subdev *sd, u32 reg, u8 *val) val 199 drivers/media/i2c/m5mols/m5mols_core.c *val = (u8)val_32; val 203 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_read_u16(struct v4l2_subdev *sd, u32 reg, u16 *val) val 217 drivers/media/i2c/m5mols/m5mols_core.c *val = (u16)val_32; val 221 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_read_u32(struct v4l2_subdev *sd, u32 reg, u32 *val) val 228 drivers/media/i2c/m5mols/m5mols_core.c return m5mols_read(sd, I2C_SIZE(reg), reg, val); val 239 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_write(struct v4l2_subdev *sd, u32 reg, u32 val) val 268 drivers/media/i2c/m5mols/m5mols_core.c *buf = m5mols_swap_byte((u8 *)&val, size); val 43 drivers/media/i2c/max2175.c u8 val; /* Register value */ val 310 drivers/media/i2c/max2175.c static inline u8 max2175_get_bitval(u8 val, u8 msb, u8 lsb) val 312 drivers/media/i2c/max2175.c return (val & GENMASK(msb, lsb)) >> lsb; val 316 drivers/media/i2c/max2175.c static int max2175_read(struct max2175 *ctx, u8 idx, u8 *val) val 325 drivers/media/i2c/max2175.c *val = regval; val 330 drivers/media/i2c/max2175.c static int max2175_write(struct max2175 *ctx, u8 idx, u8 val) val 334 drivers/media/i2c/max2175.c ret = regmap_write(ctx->regmap, idx, val); val 337 drivers/media/i2c/max2175.c ret, idx, val); val 344 drivers/media/i2c/max2175.c u8 val; val 346 drivers/media/i2c/max2175.c if (max2175_read(ctx, idx, &val)) val 349 drivers/media/i2c/max2175.c return max2175_get_bitval(val, msb, lsb); val 373 drivers/media/i2c/max2175.c unsigned int val; val 375 drivers/media/i2c/max2175.c return regmap_read_poll_timeout(ctx->regmap, idx, val, val 376 drivers/media/i2c/max2175.c (max2175_get_bitval(val, msb, lsb) == exp_bitval), val 453 drivers/media/i2c/max2175.c max2175_write(ctx, fmeu1p2_map[i].idx, fmeu1p2_map[i].val); val 468 drivers/media/i2c/max2175.c max2175_write(ctx, dab12_map[i].idx, dab12_map[i].val); val 481 drivers/media/i2c/max2175.c max2175_write(ctx, fmna1p0_map[i].idx, fmna1p0_map[i].val); val 489 drivers/media/i2c/max2175.c max2175_write(ctx, fmna2p0_map[i].idx, fmna2p0_map[i].val); val 791 drivers/media/i2c/max2175.c max2175_set_hsls(ctx, ctx->hsls->cur.val); val 794 drivers/media/i2c/max2175.c max2175_i2s_enable(ctx, ctx->i2s_en->cur.val); val 1012 drivers/media/i2c/max2175.c max2175_tune_rf_freq(ctx, ctx->freq, ctx->hsls->cur.val); val 1016 drivers/media/i2c/max2175.c ctx->hsls->cur.val); val 1023 drivers/media/i2c/max2175.c mxm_dbg(ctx, "s_ctrl: id 0x%x, val %u\n", ctrl->id, ctrl->val); val 1026 drivers/media/i2c/max2175.c max2175_i2s_enable(ctx, ctrl->val); val 1029 drivers/media/i2c/max2175.c max2175_set_hsls(ctx, ctrl->val); val 1032 drivers/media/i2c/max2175.c max2175_s_ctrl_rx_mode(ctx, ctrl->val); val 1061 drivers/media/i2c/max2175.c ctrl->val = max2175_get_lna_gain(ctx); val 1064 drivers/media/i2c/max2175.c ctrl->val = max2175_read_bits(ctx, 49, 4, 0); val 1067 drivers/media/i2c/max2175.c ctrl->val = (max2175_read_bits(ctx, 60, 7, 6) == 3); val 1088 drivers/media/i2c/max2175.c ctx->rx_mode->cur.val = rx_mode; val 1091 drivers/media/i2c/max2175.c return max2175_tune_rf_freq(ctx, freq, ctx->hsls->cur.val); val 1112 drivers/media/i2c/max2175.c max2175_freq_rx_mode_valid(ctx, ctx->rx_mode->cur.val, freq)) val 1113 drivers/media/i2c/max2175.c ret = max2175_tune_rf_freq(ctx, freq, ctx->hsls->cur.val); val 1119 drivers/media/i2c/max2175.c ret, ctx->freq, ctx->mode_resolved, ctx->rx_mode->cur.val); val 104 drivers/media/i2c/ml86v7667.c int val = i2c_smbus_read_byte_data(client, reg); val 105 drivers/media/i2c/ml86v7667.c if (val < 0) val 106 drivers/media/i2c/ml86v7667.c return val; val 108 drivers/media/i2c/ml86v7667.c val = (val & ~mask) | (data & mask); val 109 drivers/media/i2c/ml86v7667.c return i2c_smbus_write_byte_data(client, reg, val); val 121 drivers/media/i2c/ml86v7667.c SSEPL_LUMINANCE_MASK, ctrl->val); val 125 drivers/media/i2c/ml86v7667.c CLC_CONTRAST_MASK, ctrl->val); val 129 drivers/media/i2c/ml86v7667.c ctrl->val << ACCRC_CHROMA_SHIFT); val 132 drivers/media/i2c/ml86v7667.c ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val); val 137 drivers/media/i2c/ml86v7667.c ctrl->val << ACCC_CHROMA_CR_SHIFT); val 142 drivers/media/i2c/ml86v7667.c ctrl->val << ACCC_CHROMA_CB_SHIFT); val 147 drivers/media/i2c/ml86v7667.c ctrl->val << LUMC_ONOFF_SHIFT); val 152 drivers/media/i2c/ml86v7667.c ctrl->val << CHRCA_MODE_SHIFT); val 270 drivers/media/i2c/ml86v7667.c reg->val = ret; val 281 drivers/media/i2c/ml86v7667.c return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val); val 319 drivers/media/i2c/ml86v7667.c int val; val 347 drivers/media/i2c/ml86v7667.c val = i2c_smbus_read_byte_data(client, STATUS_REG); val 348 drivers/media/i2c/ml86v7667.c if (val < 0) val 349 drivers/media/i2c/ml86v7667.c return val; val 351 drivers/media/i2c/ml86v7667.c priv->std = val & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60; val 354 drivers/media/i2c/ml86v7667.c val = priv->std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601; val 355 drivers/media/i2c/ml86v7667.c ret |= ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, val); val 196 drivers/media/i2c/msp3400-driver.c static int msp_write(struct i2c_client *client, int dev, int addr, int val) val 204 drivers/media/i2c/msp3400-driver.c buffer[3] = val >> 8; val 205 drivers/media/i2c/msp3400-driver.c buffer[4] = val & 0xff; val 208 drivers/media/i2c/msp3400-driver.c dev, addr, val); val 224 drivers/media/i2c/msp3400-driver.c int msp_write_dem(struct i2c_client *client, int addr, int val) val 226 drivers/media/i2c/msp3400-driver.c return msp_write(client, I2C_MSP_DEM, addr, val); val 229 drivers/media/i2c/msp3400-driver.c int msp_write_dsp(struct i2c_client *client, int addr, int val) val 231 drivers/media/i2c/msp3400-driver.c return msp_write(client, I2C_MSP_DSP, addr, val); val 338 drivers/media/i2c/msp3400-driver.c int val = ctrl->val; val 343 drivers/media/i2c/msp3400-driver.c int reallymuted = state->muted->val | state->scan_in_progress; val 346 drivers/media/i2c/msp3400-driver.c val = (val * 0x7f / 65535) << 8; val 349 drivers/media/i2c/msp3400-driver.c state->muted->val ? "on" : "off", val 351 drivers/media/i2c/msp3400-driver.c state->volume->val); val 353 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0000, val); val 354 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0007, reallymuted ? 0x1 : (val | 0x1)); val 356 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0040, reallymuted ? 0x1 : (val | 0x1)); val 358 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0006, val); val 363 drivers/media/i2c/msp3400-driver.c val = ((val - 32768) * 0x60 / 65535) << 8; val 364 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0002, val); val 366 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0031, val); val 370 drivers/media/i2c/msp3400-driver.c val = ((val - 32768) * 0x60 / 65535) << 8; val 371 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0003, val); val 373 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0032, val); val 377 drivers/media/i2c/msp3400-driver.c val = val ? ((5 * 4) << 8) : 0; val 378 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0004, val); val 380 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0033, val); val 384 drivers/media/i2c/msp3400-driver.c val = (u8)((val / 256) - 128); val 385 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0001, val << 8); val 387 drivers/media/i2c/msp3400-driver.c msp_write_dsp(client, 0x0030, val << 8); val 400 drivers/media/i2c/msp3400-driver.c state->volume->val = state->volume->cur.val; val 401 drivers/media/i2c/msp3400-driver.c state->muted->val = state->muted->cur.val; val 479 drivers/media/i2c/msp3400-driver.c u16 val, reg; val 499 drivers/media/i2c/msp3400-driver.c val = msp_read_dem(client, reg); val 500 drivers/media/i2c/msp3400-driver.c msp_write_dem(client, reg, (val & ~0x100) | (tuner << 8)); val 130 drivers/media/i2c/msp3400-driver.h int msp_write_dem(struct i2c_client *client, int addr, int val); val 131 drivers/media/i2c/msp3400-driver.h int msp_write_dsp(struct i2c_client *client, int addr, int val); val 404 drivers/media/i2c/msp3400-kthreads.c int val; val 411 drivers/media/i2c/msp3400-kthreads.c val = msp_read_dsp(client, 0x18); val 412 drivers/media/i2c/msp3400-kthreads.c if (val > 32767) val 413 drivers/media/i2c/msp3400-kthreads.c val -= 65536; val 415 drivers/media/i2c/msp3400-kthreads.c "stereo detect register: %d\n", val); val 416 drivers/media/i2c/msp3400-kthreads.c if (val > 8192) { val 418 drivers/media/i2c/msp3400-kthreads.c } else if (val < -4096) { val 428 drivers/media/i2c/msp3400-kthreads.c val = msp_read_dem(client, 0x23); val 430 drivers/media/i2c/msp3400-kthreads.c val & 1, (val & 0x1e) >> 1); val 432 drivers/media/i2c/msp3400-kthreads.c if (val & 1) { val 434 drivers/media/i2c/msp3400-kthreads.c switch ((val & 0x1e) >> 1) { val 495 drivers/media/i2c/msp3400-kthreads.c int count, max1, max2, val1, val2, val, i; val 549 drivers/media/i2c/msp3400-kthreads.c val = msp_read_dsp(client, 0x1b); val 550 drivers/media/i2c/msp3400-kthreads.c if (val > 32767) val 551 drivers/media/i2c/msp3400-kthreads.c val -= 65536; val 552 drivers/media/i2c/msp3400-kthreads.c if (val1 < val) val 553 drivers/media/i2c/msp3400-kthreads.c val1 = val, max1 = i; val 555 drivers/media/i2c/msp3400-kthreads.c "carrier1 val: %5d / %s\n", val, cd[i].name); val 586 drivers/media/i2c/msp3400-kthreads.c val = msp_read_dsp(client, 0x1b); val 587 drivers/media/i2c/msp3400-kthreads.c if (val > 32767) val 588 drivers/media/i2c/msp3400-kthreads.c val -= 65536; val 589 drivers/media/i2c/msp3400-kthreads.c if (val2 < val) val 590 drivers/media/i2c/msp3400-kthreads.c val2 = val, max2 = i; val 592 drivers/media/i2c/msp3400-kthreads.c "carrier2 val: %5d / %s\n", val, cd[i].name); val 686 drivers/media/i2c/msp3400-kthreads.c int val, i, std, count; val 736 drivers/media/i2c/msp3400-kthreads.c val = std; val 745 drivers/media/i2c/msp3400-kthreads.c val = msp_read_dem(client, 0x7e); val 746 drivers/media/i2c/msp3400-kthreads.c if (val < 0x07ff) val 753 drivers/media/i2c/msp3400-kthreads.c if (msp_stdlist[i].retval == val) val 756 drivers/media/i2c/msp3400-kthreads.c msp_standard_std_name(val), val); val 759 drivers/media/i2c/msp3400-kthreads.c state->std = val; val 763 drivers/media/i2c/msp3400-kthreads.c (state->v4l2_std & V4L2_STD_SECAM) && (val != 0x0009)) { val 767 drivers/media/i2c/msp3400-kthreads.c msp_stdlist[8].name : "unknown", val); val 768 drivers/media/i2c/msp3400-kthreads.c state->std = val = 0x0009; val 769 drivers/media/i2c/msp3400-kthreads.c msp_write_dem(client, 0x20, val); val 775 drivers/media/i2c/msp3400-kthreads.c switch (val) { val 779 drivers/media/i2c/msp3400-kthreads.c if (val == 0x000a) val 983 drivers/media/i2c/msp3400-kthreads.c int val, i; val 1025 drivers/media/i2c/msp3400-kthreads.c val = msp_read_dem(client, 0x7e); val 1026 drivers/media/i2c/msp3400-kthreads.c if (val < 0x07ff) { val 1027 drivers/media/i2c/msp3400-kthreads.c state->std = val; val 427 drivers/media/i2c/mt9m001.c reg->val = reg_read(client, reg->reg); val 429 drivers/media/i2c/mt9m001.c if (reg->val > 0xffff) val 443 drivers/media/i2c/mt9m001.c if (reg_write(client, reg->reg, reg->val) < 0) val 496 drivers/media/i2c/mt9m001.c mt9m001->exposure->val = val 518 drivers/media/i2c/mt9m001.c if (ctrl->val) val 526 drivers/media/i2c/mt9m001.c if (ctrl->val <= ctrl->default_value) { val 529 drivers/media/i2c/mt9m001.c data = ((ctrl->val - (s32)ctrl->minimum) * 8 + range / 2) / range; val 537 drivers/media/i2c/mt9m001.c unsigned long gain = ((ctrl->val - (s32)ctrl->default_value - 1) * val 554 drivers/media/i2c/mt9m001.c if (ctrl->val == V4L2_EXPOSURE_MANUAL) { val 556 drivers/media/i2c/mt9m001.c unsigned long shutter = ((exp->val - (s32)exp->minimum) * 1048 + val 550 drivers/media/i2c/mt9m032.c int val; val 555 drivers/media/i2c/mt9m032.c val = mt9m032_read(client, reg->reg); val 556 drivers/media/i2c/mt9m032.c if (val < 0) val 560 drivers/media/i2c/mt9m032.c reg->val = val; val 574 drivers/media/i2c/mt9m032.c return mt9m032_write(client, reg->reg, reg->val); val 593 drivers/media/i2c/mt9m032.c static int mt9m032_set_gain(struct mt9m032 *sensor, s32 val) val 603 drivers/media/i2c/mt9m032.c if (val < 63) { val 605 drivers/media/i2c/mt9m032.c analog_gain_val = val; val 608 drivers/media/i2c/mt9m032.c analog_gain_val = val / 2; val 624 drivers/media/i2c/mt9m032.c if (ctrl->id == V4L2_CID_GAIN && ctrl->val >= 63) { val 626 drivers/media/i2c/mt9m032.c ctrl->val &= ~1; val 641 drivers/media/i2c/mt9m032.c return mt9m032_set_gain(sensor, ctrl->val); val 645 drivers/media/i2c/mt9m032.c return update_read_mode2(sensor, sensor->vflip->val, val 646 drivers/media/i2c/mt9m032.c sensor->hflip->val); val 650 drivers/media/i2c/mt9m032.c (ctrl->val >> 16) & 0xffff); val 655 drivers/media/i2c/mt9m032.c ctrl->val & 0xffff); val 140 drivers/media/i2c/mt9m111.c #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) val 141 drivers/media/i2c/mt9m111.c #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) val 142 drivers/media/i2c/mt9m111.c #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) val 143 drivers/media/i2c/mt9m111.c #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ val 144 drivers/media/i2c/mt9m111.c (val), (mask)) val 757 drivers/media/i2c/mt9m111.c int val; val 762 drivers/media/i2c/mt9m111.c val = mt9m111_reg_read(client, reg->reg); val 764 drivers/media/i2c/mt9m111.c reg->val = (u64)val; val 766 drivers/media/i2c/mt9m111.c if (reg->val > 0xffff) val 780 drivers/media/i2c/mt9m111.c if (mt9m111_reg_write(client, reg->reg, reg->val) < 0) val 815 drivers/media/i2c/mt9m111.c u16 val; val 821 drivers/media/i2c/mt9m111.c val = (1 << 10) | (1 << 9) | (gain / 4); val 823 drivers/media/i2c/mt9m111.c val = (1 << 9) | (gain / 2); val 825 drivers/media/i2c/mt9m111.c val = gain; val 827 drivers/media/i2c/mt9m111.c return reg_write(GLOBAL_GAIN, val); val 830 drivers/media/i2c/mt9m111.c static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val) val 834 drivers/media/i2c/mt9m111.c if (val == V4L2_EXPOSURE_AUTO) val 859 drivers/media/i2c/mt9m111.c static int mt9m111_set_test_pattern(struct mt9m111 *mt9m111, int val) val 863 drivers/media/i2c/mt9m111.c return mt9m111_reg_mask(client, MT9M111_TPG_CTRL, val, val 867 drivers/media/i2c/mt9m111.c static int mt9m111_set_colorfx(struct mt9m111 *mt9m111, int val) val 880 drivers/media/i2c/mt9m111.c if (colorfx[i].id == val) { val 897 drivers/media/i2c/mt9m111.c return mt9m111_set_flip(mt9m111, ctrl->val, val 900 drivers/media/i2c/mt9m111.c return mt9m111_set_flip(mt9m111, ctrl->val, val 903 drivers/media/i2c/mt9m111.c return mt9m111_set_global_gain(mt9m111, ctrl->val); val 905 drivers/media/i2c/mt9m111.c return mt9m111_set_autoexposure(mt9m111, ctrl->val); val 907 drivers/media/i2c/mt9m111.c return mt9m111_set_autowhitebalance(mt9m111, ctrl->val); val 909 drivers/media/i2c/mt9m111.c return mt9m111_set_test_pattern(mt9m111, ctrl->val); val 911 drivers/media/i2c/mt9m111.c return mt9m111_set_colorfx(mt9m111, ctrl->val); val 657 drivers/media/i2c/mt9p031.c if (mt9p031->blc_auto->cur.val != 0) { val 664 drivers/media/i2c/mt9p031.c if (mt9p031->blc_offset->cur.val != 0) { val 666 drivers/media/i2c/mt9p031.c mt9p031->blc_offset->cur.val); val 688 drivers/media/i2c/mt9p031.c (ctrl->val >> 16) & 0xffff); val 693 drivers/media/i2c/mt9p031.c ctrl->val & 0xffff); val 710 drivers/media/i2c/mt9p031.c if (ctrl->val <= 32) { val 711 drivers/media/i2c/mt9p031.c data = ctrl->val; val 712 drivers/media/i2c/mt9p031.c } else if (ctrl->val <= 64) { val 713 drivers/media/i2c/mt9p031.c ctrl->val &= ~1; val 714 drivers/media/i2c/mt9p031.c data = (1 << 6) | (ctrl->val >> 1); val 716 drivers/media/i2c/mt9p031.c ctrl->val &= ~7; val 717 drivers/media/i2c/mt9p031.c data = ((ctrl->val - 64) << 5) | (1 << 6) | 32; val 723 drivers/media/i2c/mt9p031.c if (ctrl->val) val 731 drivers/media/i2c/mt9p031.c if (ctrl->val) val 744 drivers/media/i2c/mt9p031.c v4l2_ctrl_activate(mt9p031->blc_auto, ctrl->val == 0); val 745 drivers/media/i2c/mt9p031.c v4l2_ctrl_activate(mt9p031->blc_offset, ctrl->val == 0); val 747 drivers/media/i2c/mt9p031.c if (!ctrl->val) { val 778 drivers/media/i2c/mt9p031.c ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT) val 783 drivers/media/i2c/mt9p031.c ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC, val 784 drivers/media/i2c/mt9p031.c ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0); val 789 drivers/media/i2c/mt9p031.c ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC); val 793 drivers/media/i2c/mt9p031.c ctrl->val); val 796 drivers/media/i2c/mt9p031.c data = ctrl->val & ((1 << 9) - 1); val 811 drivers/media/i2c/mt9p031.c ctrl->val & ((1 << 12) - 1)); val 552 drivers/media/i2c/mt9t001.c if (gain->val != gain->cur.val) val 566 drivers/media/i2c/mt9t001.c if (gain->val == gain->cur.val) val 569 drivers/media/i2c/mt9t001.c value = mt9t001_gain_value(&gain->val); val 588 drivers/media/i2c/mt9t001.c ctrl->val & 0xffff); val 593 drivers/media/i2c/mt9t001.c ctrl->val >> 16); val 597 drivers/media/i2c/mt9t001.c ctrl->val ? 0 : MT9T001_OUTPUT_CONTROL_TEST_DATA, val 598 drivers/media/i2c/mt9t001.c ctrl->val ? MT9T001_OUTPUT_CONTROL_TEST_DATA : 0); val 601 drivers/media/i2c/mt9t001.c return mt9t001_write(client, MT9T001_TEST_DATA, ctrl->val << 2); val 604 drivers/media/i2c/mt9t001.c value = ctrl->val ? 0 : MT9T001_BLACK_LEVEL_OVERRIDE; val 614 drivers/media/i2c/mt9t001.c ret = mt9t001_write(client, MT9T001_GREEN1_OFFSET, ctrl->val); val 618 drivers/media/i2c/mt9t001.c ret = mt9t001_write(client, MT9T001_GREEN2_OFFSET, ctrl->val); val 622 drivers/media/i2c/mt9t001.c ret = mt9t001_write(client, MT9T001_RED_OFFSET, ctrl->val); val 626 drivers/media/i2c/mt9t001.c return mt9t001_write(client, MT9T001_BLUE_OFFSET, ctrl->val); val 211 drivers/media/i2c/mt9t112.c int val = __mt9t112_reg_read(client, command); val 213 drivers/media/i2c/mt9t112.c if (val < 0) val 214 drivers/media/i2c/mt9t112.c return val; val 216 drivers/media/i2c/mt9t112.c val &= ~mask; val 217 drivers/media/i2c/mt9t112.c val |= set & mask; val 219 drivers/media/i2c/mt9t112.c return __mt9t112_reg_write(client, command, val); val 249 drivers/media/i2c/mt9t112.c int val = __mt9t112_mcu_read(client, command); val 251 drivers/media/i2c/mt9t112.c if (val < 0) val 252 drivers/media/i2c/mt9t112.c return val; val 254 drivers/media/i2c/mt9t112.c val &= ~mask; val 255 drivers/media/i2c/mt9t112.c val |= set & mask; val 257 drivers/media/i2c/mt9t112.c return __mt9t112_mcu_write(client, command, val); val 375 drivers/media/i2c/mt9t112.c u16 val; val 378 drivers/media/i2c/mt9t112.c val = (n << 8) | (m << 0); val 379 drivers/media/i2c/mt9t112.c mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val); val 382 drivers/media/i2c/mt9t112.c val = ((p3 & 0x0F) << 8) | ((p2 & 0x0F) << 4) | ((p1 & 0x0F) << 0); val 383 drivers/media/i2c/mt9t112.c mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val); val 386 drivers/media/i2c/mt9t112.c val = (0x7 << 12) | ((p6 & 0x0F) << 8) | ((p5 & 0x0F) << 4) | val 388 drivers/media/i2c/mt9t112.c mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val); val 391 drivers/media/i2c/mt9t112.c val = (0x1 << 12) | ((p7 & 0x0F) << 0); val 392 drivers/media/i2c/mt9t112.c mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val); val 730 drivers/media/i2c/mt9t112.c reg->val = (__u64)ret; val 741 drivers/media/i2c/mt9t112.c mt9t112_reg_write(ret, client, reg->reg, reg->val); val 74 drivers/media/i2c/mt9v011.c int rc, val; val 88 drivers/media/i2c/mt9v011.c val = be16_to_cpu(buffer); val 90 drivers/media/i2c/mt9v011.c v4l2_dbg(2, debug, sd, "mt9v011: read 0x%02x = 0x%04x\n", addr, val); val 92 drivers/media/i2c/mt9v011.c return val; val 314 drivers/media/i2c/mt9v011.c static int mt9v011_reset(struct v4l2_subdev *sd, u32 val) val 398 drivers/media/i2c/mt9v011.c reg->val = mt9v011_read(sd, reg->reg & 0xff); val 407 drivers/media/i2c/mt9v011.c mt9v011_write(sd, reg->reg & 0xff, reg->val & 0xffff); val 421 drivers/media/i2c/mt9v011.c core->global_gain = ctrl->val; val 424 drivers/media/i2c/mt9v011.c core->exposure = ctrl->val; val 427 drivers/media/i2c/mt9v011.c core->red_bal = ctrl->val; val 430 drivers/media/i2c/mt9v011.c core->blue_bal = ctrl->val; val 433 drivers/media/i2c/mt9v011.c core->hflip = ctrl->val; val 437 drivers/media/i2c/mt9v011.c core->vflip = ctrl->val; val 652 drivers/media/i2c/mt9v032.c ctrl->val); val 655 drivers/media/i2c/mt9v032.c return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val); val 659 drivers/media/i2c/mt9v032.c !ctrl->val); val 663 drivers/media/i2c/mt9v032.c ctrl->val); val 666 drivers/media/i2c/mt9v032.c mt9v032->hblank = ctrl->val; val 671 drivers/media/i2c/mt9v032.c ctrl->val); val 678 drivers/media/i2c/mt9v032.c freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val]; val 684 drivers/media/i2c/mt9v032.c switch (mt9v032->test_pattern->val) { val 701 drivers/media/i2c/mt9v032.c data = (mt9v032->test_pattern_color->val << val 711 drivers/media/i2c/mt9v032.c return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val); val 714 drivers/media/i2c/mt9v032.c return regmap_write(map, MT9V032_AEC_LPF, ctrl->val); val 717 drivers/media/i2c/mt9v032.c return regmap_write(map, MT9V032_AGC_LPF, ctrl->val); val 721 drivers/media/i2c/mt9v032.c ctrl->val); val 725 drivers/media/i2c/mt9v032.c ctrl->val); val 730 drivers/media/i2c/mt9v032.c ctrl->val); val 220 drivers/media/i2c/mt9v111.c static int __mt9v111_read(struct i2c_client *c, u8 reg, u16 *val) val 242 drivers/media/i2c/mt9v111.c *val = be16_to_cpu(buf); val 244 drivers/media/i2c/mt9v111.c dev_dbg(&c->dev, "%s: %x=%x\n", __func__, reg, *val); val 249 drivers/media/i2c/mt9v111.c static int __mt9v111_write(struct i2c_client *c, u8 reg, u16 val) val 256 drivers/media/i2c/mt9v111.c buf[1] = val >> 8; val 257 drivers/media/i2c/mt9v111.c buf[2] = val & 0xff; val 279 drivers/media/i2c/mt9v111.c u16 val; val 290 drivers/media/i2c/mt9v111.c ret = __mt9v111_read(c, MT9V111_R01_ADDR_SPACE, &val); val 294 drivers/media/i2c/mt9v111.c if (val != addr_space) val 302 drivers/media/i2c/mt9v111.c static int mt9v111_read(struct i2c_client *c, u8 addr_space, u8 reg, u16 *val) val 311 drivers/media/i2c/mt9v111.c ret = __mt9v111_read(c, reg, val); val 318 drivers/media/i2c/mt9v111.c static int mt9v111_write(struct i2c_client *c, u8 addr_space, u8 reg, u16 val) val 327 drivers/media/i2c/mt9v111.c ret = __mt9v111_write(c, reg, val); val 335 drivers/media/i2c/mt9v111.c u16 mask, u16 val) val 351 drivers/media/i2c/mt9v111.c current_val |= (val & mask); val 1023 drivers/media/i2c/mt9v111.c if (mt9v111->auto_exp->val == V4L2_EXPOSURE_MANUAL && val 1024 drivers/media/i2c/mt9v111.c mt9v111->auto_awb->val == V4L2_WHITE_BALANCE_MANUAL) val 1044 drivers/media/i2c/mt9v111.c ctrl->val == V4L2_WHITE_BALANCE_AUTO ? val 1051 drivers/media/i2c/mt9v111.c ctrl->val == V4L2_EXPOSURE_AUTO ? val 1058 drivers/media/i2c/mt9v111.c mt9v111->hblank->val); val 1064 drivers/media/i2c/mt9v111.c mt9v111->vblank->val); val 1078 drivers/media/i2c/mt9v111.c u16 val; val 1085 drivers/media/i2c/mt9v111.c MT9V111_CORE_RFF_CHIP_VER, &val); val 1089 drivers/media/i2c/mt9v111.c if ((val >> 8) != MT9V111_CHIP_ID_HIGH && val 1090 drivers/media/i2c/mt9v111.c (val & 0xff) != MT9V111_CHIP_ID_LOW) { val 1093 drivers/media/i2c/mt9v111.c val >> 8, val & 0xff); val 1099 drivers/media/i2c/mt9v111.c val >> 8, val & 0xff); val 151 drivers/media/i2c/noon010pc30.c u16 val; val 266 drivers/media/i2c/noon010pc30.c static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val) val 274 drivers/media/i2c/noon010pc30.c return i2c_smbus_write_byte_data(client, reg_addr & 0xFF, val); val 281 drivers/media/i2c/noon010pc30.c int ret = cam_i2c_write(sd, msg->addr, msg->val); val 461 drivers/media/i2c/noon010pc30.c __func__, ctrl->id, ctrl->val); val 474 drivers/media/i2c/noon010pc30.c ret = noon010_enable_autowhitebalance(sd, ctrl->val); val 477 drivers/media/i2c/noon010pc30.c ret = cam_i2c_write(sd, MWB_BGAIN_REG, ctrl->val); val 480 drivers/media/i2c/noon010pc30.c ret = cam_i2c_write(sd, MWB_RGAIN_REG, ctrl->val); val 86 drivers/media/i2c/ov13858.c u8 val; val 1054 drivers/media/i2c/ov13858.c u32 *val) val 1083 drivers/media/i2c/ov13858.c *val = be32_to_cpu(data_be); val 1095 drivers/media/i2c/ov13858.c __be32 val; val 1103 drivers/media/i2c/ov13858.c val = cpu_to_be32(__val); val 1104 drivers/media/i2c/ov13858.c val_p = (u8 *)&val; val 1127 drivers/media/i2c/ov13858.c regs[i].val); val 1192 drivers/media/i2c/ov13858.c u32 val; val 1195 drivers/media/i2c/ov13858.c OV13858_REG_VALUE_08BIT, &val); val 1200 drivers/media/i2c/ov13858.c val &= OV13858_TEST_PATTERN_MASK; val 1201 drivers/media/i2c/ov13858.c val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE; val 1203 drivers/media/i2c/ov13858.c val &= ~OV13858_TEST_PATTERN_ENABLE; val 1207 drivers/media/i2c/ov13858.c OV13858_REG_VALUE_08BIT, val); val 1222 drivers/media/i2c/ov13858.c max = ov13858->cur_mode->height + ctrl->val - 8; val 1240 drivers/media/i2c/ov13858.c OV13858_REG_VALUE_16BIT, ctrl->val); val 1243 drivers/media/i2c/ov13858.c ret = ov13858_update_digital_gain(ov13858, ctrl->val); val 1248 drivers/media/i2c/ov13858.c ctrl->val << 4); val 1255 drivers/media/i2c/ov13858.c + ctrl->val); val 1258 drivers/media/i2c/ov13858.c ret = ov13858_enable_test_pattern(ov13858, ctrl->val); val 1263 drivers/media/i2c/ov13858.c ctrl->id, ctrl->val); val 1543 drivers/media/i2c/ov13858.c u32 val; val 1546 drivers/media/i2c/ov13858.c OV13858_REG_VALUE_24BIT, &val); val 1550 drivers/media/i2c/ov13858.c if (val != OV13858_CHIP_ID) { val 1552 drivers/media/i2c/ov13858.c OV13858_CHIP_ID, val); val 1691 drivers/media/i2c/ov13858.c u32 val = 0; val 1693 drivers/media/i2c/ov13858.c device_property_read_u32(&client->dev, "clock-frequency", &val); val 1694 drivers/media/i2c/ov13858.c if (val != 19200000) val 675 drivers/media/i2c/ov2640.c s32 val = i2c_smbus_read_byte_data(client, reg); val 676 drivers/media/i2c/ov2640.c if (val < 0) val 677 drivers/media/i2c/ov2640.c return val; val 679 drivers/media/i2c/ov2640.c val &= ~mask; val 680 drivers/media/i2c/ov2640.c val |= set & mask; val 682 drivers/media/i2c/ov2640.c dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); val 684 drivers/media/i2c/ov2640.c return i2c_smbus_write_byte_data(client, reg, val); val 720 drivers/media/i2c/ov2640.c u8 val; val 739 drivers/media/i2c/ov2640.c val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00; val 741 drivers/media/i2c/ov2640.c REG04_VFLIP_IMG | REG04_VREF_EN, val); val 744 drivers/media/i2c/ov2640.c val = ctrl->val ? REG04_HFLIP_IMG : 0x00; val 745 drivers/media/i2c/ov2640.c return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val); val 747 drivers/media/i2c/ov2640.c val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00; val 748 drivers/media/i2c/ov2640.c return ov2640_mask_set(client, COM7, COM7_COLOR_BAR_TEST, val); val 769 drivers/media/i2c/ov2640.c reg->val = ret; val 780 drivers/media/i2c/ov2640.c reg->val > 0xff) val 783 drivers/media/i2c/ov2640.c return i2c_smbus_write_byte_data(client, reg->reg, reg->val); val 839 drivers/media/i2c/ov2640.c u8 val; val 900 drivers/media/i2c/ov2640.c val = (code == MEDIA_BUS_FMT_YVYU8_2X8) val 902 drivers/media/i2c/ov2640.c ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val); val 842 drivers/media/i2c/ov2659.c static int ov2659_write(struct i2c_client *client, u16 reg, u8 val) val 850 drivers/media/i2c/ov2659.c buf[2] = val; val 862 drivers/media/i2c/ov2659.c "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val); val 868 drivers/media/i2c/ov2659.c static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val) val 889 drivers/media/i2c/ov2659.c *val = buf[0]; val 894 drivers/media/i2c/ov2659.c "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val); val 990 drivers/media/i2c/ov2659.c static int ov2659_init(struct v4l2_subdev *sd, u32 val) val 1140 drivers/media/i2c/ov2659.c s64 val; val 1153 drivers/media/i2c/ov2659.c val = ov2659->pdata->link_frequency / 2; val 1155 drivers/media/i2c/ov2659.c val = ov2659->pdata->link_frequency; val 1157 drivers/media/i2c/ov2659.c ret = v4l2_ctrl_s_ctrl_int64(ov2659->link_frequency, val); val 1227 drivers/media/i2c/ov2659.c u8 val; val 1229 drivers/media/i2c/ov2659.c ret = ov2659_read(client, REG_PRE_ISP_CTRL00, &val); val 1235 drivers/media/i2c/ov2659.c val &= ~TEST_PATTERN_ENABLE; val 1238 drivers/media/i2c/ov2659.c val &= VERTICAL_COLOR_BAR_MASK; val 1239 drivers/media/i2c/ov2659.c val |= TEST_PATTERN_ENABLE; val 1243 drivers/media/i2c/ov2659.c return ov2659_write(client, REG_PRE_ISP_CTRL00, val); val 1253 drivers/media/i2c/ov2659.c return ov2659_set_test_pattern(ov2659, ctrl->val); val 66 drivers/media/i2c/ov2680.c u8 val; val 198 drivers/media/i2c/ov2680.c unsigned int len, u32 val) val 208 drivers/media/i2c/ov2680.c put_unaligned_be32(val << (8 * (4 - len)), buf + 2); val 228 drivers/media/i2c/ov2680.c unsigned int len, u32 *val) val 255 drivers/media/i2c/ov2680.c *val = get_unaligned_be32(data_buf); val 269 drivers/media/i2c/ov2680.c static int ov2680_mod_reg(struct ov2680_dev *sensor, u16 reg, u8 mask, u8 val) val 279 drivers/media/i2c/ov2680.c val &= mask; val 280 drivers/media/i2c/ov2680.c val |= readval; val 282 drivers/media/i2c/ov2680.c return ov2680_write_reg(sensor, reg, val); val 292 drivers/media/i2c/ov2680.c u8 val; val 296 drivers/media/i2c/ov2680.c val = regs->val; val 298 drivers/media/i2c/ov2680.c ret = ov2680_write_reg(sensor, reg_addr, val); val 422 drivers/media/i2c/ov2680.c gain = ctrls->gain->val; val 455 drivers/media/i2c/ov2680.c exp = (u32)ctrls->exposure->val; val 500 drivers/media/i2c/ov2680.c if (ctrls->auto_gain->val) { val 506 drivers/media/i2c/ov2680.c if (ctrls->auto_exp->val == V4L2_EXPOSURE_AUTO) { val 801 drivers/media/i2c/ov2680.c int val; val 808 drivers/media/i2c/ov2680.c val = ov2680_gain_get(sensor); val 809 drivers/media/i2c/ov2680.c if (val < 0) val 810 drivers/media/i2c/ov2680.c return val; val 811 drivers/media/i2c/ov2680.c ctrls->gain->val = val; val 814 drivers/media/i2c/ov2680.c val = ov2680_exposure_get(sensor); val 815 drivers/media/i2c/ov2680.c if (val < 0) val 816 drivers/media/i2c/ov2680.c return val; val 817 drivers/media/i2c/ov2680.c ctrls->exposure->val = val; val 835 drivers/media/i2c/ov2680.c return ov2680_gain_set(sensor, !!ctrl->val); val 837 drivers/media/i2c/ov2680.c return ov2680_gain_set(sensor, !!ctrls->auto_gain->val); val 839 drivers/media/i2c/ov2680.c return ov2680_exposure_set(sensor, !!ctrl->val); val 841 drivers/media/i2c/ov2680.c return ov2680_exposure_set(sensor, !!ctrls->auto_exp->val); val 845 drivers/media/i2c/ov2680.c if (ctrl->val) val 852 drivers/media/i2c/ov2680.c if (ctrl->val) val 857 drivers/media/i2c/ov2680.c return ov2680_test_pattern_set(sensor, ctrl->val); val 71 drivers/media/i2c/ov2685.c u8 val; val 246 drivers/media/i2c/ov2685.c u32 len, u32 val) val 259 drivers/media/i2c/ov2685.c val_be = cpu_to_be32(val); val 281 drivers/media/i2c/ov2685.c OV2685_REG_VALUE_08BIT, regs[i].val); val 288 drivers/media/i2c/ov2685.c u32 len, u32 *val) val 316 drivers/media/i2c/ov2685.c *val = be32_to_cpu(data_be); val 544 drivers/media/i2c/ov2685.c max_expo = ov2685->cur_mode->height + ctrl->val - 4; val 558 drivers/media/i2c/ov2685.c OV2685_REG_VALUE_24BIT, ctrl->val << 4); val 562 drivers/media/i2c/ov2685.c OV2685_REG_VALUE_16BIT, ctrl->val); val 567 drivers/media/i2c/ov2685.c ctrl->val + ov2685->cur_mode->height); val 572 drivers/media/i2c/ov2685.c ov2685_test_pattern_val[ctrl->val]); val 576 drivers/media/i2c/ov2685.c __func__, ctrl->id, ctrl->val); val 178 drivers/media/i2c/ov5640.c u8 val; val 617 drivers/media/i2c/ov5640.c static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val) val 626 drivers/media/i2c/ov5640.c buf[2] = val; val 636 drivers/media/i2c/ov5640.c __func__, reg, val); val 643 drivers/media/i2c/ov5640.c static int ov5640_read_reg(struct ov5640_dev *sensor, u16 reg, u8 *val) val 670 drivers/media/i2c/ov5640.c *val = buf[0]; val 674 drivers/media/i2c/ov5640.c static int ov5640_read_reg16(struct ov5640_dev *sensor, u16 reg, u16 *val) val 686 drivers/media/i2c/ov5640.c *val = ((u16)hi << 8) | (u16)lo; val 690 drivers/media/i2c/ov5640.c static int ov5640_write_reg16(struct ov5640_dev *sensor, u16 reg, u16 val) val 694 drivers/media/i2c/ov5640.c ret = ov5640_write_reg(sensor, reg, val >> 8); val 698 drivers/media/i2c/ov5640.c return ov5640_write_reg(sensor, reg + 1, val & 0xff); val 702 drivers/media/i2c/ov5640.c u8 mask, u8 val) val 712 drivers/media/i2c/ov5640.c val &= mask; val 713 drivers/media/i2c/ov5640.c val |= readval; val 715 drivers/media/i2c/ov5640.c return ov5640_write_reg(sensor, reg, val); val 1103 drivers/media/i2c/ov5640.c u8 mask, val; val 1109 drivers/media/i2c/ov5640.c val = regs->val; val 1113 drivers/media/i2c/ov5640.c ret = ov5640_mod_reg(sensor, reg_addr, mask, val); val 1115 drivers/media/i2c/ov5640.c ret = ov5640_write_reg(sensor, reg_addr, val); val 1801 drivers/media/i2c/ov5640.c bool auto_gain = sensor->ctrls.auto_gain->val == 1; val 1802 drivers/media/i2c/ov5640.c bool auto_exp = sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO; val 2416 drivers/media/i2c/ov5640.c u16 red = (u16)sensor->ctrls.red_balance->val; val 2417 drivers/media/i2c/ov5640.c u16 blue = (u16)sensor->ctrls.blue_balance->val; val 2454 drivers/media/i2c/ov5640.c if (ctrls->exposure->val < max_exp) val 2455 drivers/media/i2c/ov5640.c ret = ov5640_set_exposure(sensor, ctrls->exposure->val); val 2473 drivers/media/i2c/ov5640.c ret = ov5640_set_gain(sensor, ctrls->gain->val); val 2571 drivers/media/i2c/ov5640.c int val; val 2577 drivers/media/i2c/ov5640.c val = ov5640_get_gain(sensor); val 2578 drivers/media/i2c/ov5640.c if (val < 0) val 2579 drivers/media/i2c/ov5640.c return val; val 2580 drivers/media/i2c/ov5640.c sensor->ctrls.gain->val = val; val 2583 drivers/media/i2c/ov5640.c val = ov5640_get_exposure(sensor); val 2584 drivers/media/i2c/ov5640.c if (val < 0) val 2585 drivers/media/i2c/ov5640.c return val; val 2586 drivers/media/i2c/ov5640.c sensor->ctrls.exposure->val = val; val 2611 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_gain(sensor, ctrl->val); val 2614 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_exposure(sensor, ctrl->val); val 2617 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_white_balance(sensor, ctrl->val); val 2620 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_hue(sensor, ctrl->val); val 2623 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_contrast(sensor, ctrl->val); val 2626 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_saturation(sensor, ctrl->val); val 2629 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_test_pattern(sensor, ctrl->val); val 2632 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_light_freq(sensor, ctrl->val); val 2635 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_hflip(sensor, ctrl->val); val 2638 drivers/media/i2c/ov5640.c ret = ov5640_set_ctrl_vflip(sensor, ctrl->val); val 75 drivers/media/i2c/ov5645.c u8 val; val 544 drivers/media/i2c/ov5645.c static int ov5645_write_reg(struct ov5645 *ov5645, u16 reg, u8 val) val 551 drivers/media/i2c/ov5645.c regbuf[2] = val; val 556 drivers/media/i2c/ov5645.c __func__, ret, reg, val); val 563 drivers/media/i2c/ov5645.c static int ov5645_read_reg(struct ov5645 *ov5645, u16 reg, u8 *val) val 578 drivers/media/i2c/ov5645.c ret = i2c_master_recv(ov5645->i2c_client, val, 1); val 590 drivers/media/i2c/ov5645.c u8 val = ov5645->aec_pk_manual; val 594 drivers/media/i2c/ov5645.c val &= ~OV5645_AEC_MANUAL_ENABLE; val 596 drivers/media/i2c/ov5645.c val |= OV5645_AEC_MANUAL_ENABLE; val 598 drivers/media/i2c/ov5645.c ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val); val 600 drivers/media/i2c/ov5645.c ov5645->aec_pk_manual = val; val 607 drivers/media/i2c/ov5645.c u8 val = ov5645->aec_pk_manual; val 611 drivers/media/i2c/ov5645.c val &= ~OV5645_AGC_MANUAL_ENABLE; val 613 drivers/media/i2c/ov5645.c val |= OV5645_AGC_MANUAL_ENABLE; val 615 drivers/media/i2c/ov5645.c ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val); val 617 drivers/media/i2c/ov5645.c ov5645->aec_pk_manual = val; val 630 drivers/media/i2c/ov5645.c ret = ov5645_write_reg(ov5645, settings->reg, settings->val); val 729 drivers/media/i2c/ov5645.c u8 val = ov5645->timing_tc_reg21; val 733 drivers/media/i2c/ov5645.c val &= ~(OV5645_SENSOR_MIRROR); val 735 drivers/media/i2c/ov5645.c val |= (OV5645_SENSOR_MIRROR); val 737 drivers/media/i2c/ov5645.c ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG21, val); val 739 drivers/media/i2c/ov5645.c ov5645->timing_tc_reg21 = val; val 746 drivers/media/i2c/ov5645.c u8 val = ov5645->timing_tc_reg20; val 750 drivers/media/i2c/ov5645.c val |= (OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP); val 752 drivers/media/i2c/ov5645.c val &= ~(OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP); val 754 drivers/media/i2c/ov5645.c ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG20, val); val 756 drivers/media/i2c/ov5645.c ov5645->timing_tc_reg20 = val; val 763 drivers/media/i2c/ov5645.c u8 val = 0; val 766 drivers/media/i2c/ov5645.c val = OV5645_SET_TEST_PATTERN(value - 1); val 767 drivers/media/i2c/ov5645.c val |= OV5645_TEST_PATTERN_ENABLE; val 770 drivers/media/i2c/ov5645.c return ov5645_write_reg(ov5645, OV5645_PRE_ISP_TEST_SETTING_1, val); val 783 drivers/media/i2c/ov5645.c u8 val = 0; val 786 drivers/media/i2c/ov5645.c val = OV5645_AWB_MANUAL_ENABLE; val 788 drivers/media/i2c/ov5645.c return ov5645_write_reg(ov5645, OV5645_AWB_MANUAL_CONTROL, val); val 805 drivers/media/i2c/ov5645.c ret = ov5645_set_saturation(ov5645, ctrl->val); val 808 drivers/media/i2c/ov5645.c ret = ov5645_set_awb(ov5645, ctrl->val); val 811 drivers/media/i2c/ov5645.c ret = ov5645_set_agc_mode(ov5645, ctrl->val); val 814 drivers/media/i2c/ov5645.c ret = ov5645_set_aec_mode(ov5645, ctrl->val); val 817 drivers/media/i2c/ov5645.c ret = ov5645_set_test_pattern(ov5645, ctrl->val); val 820 drivers/media/i2c/ov5645.c ret = ov5645_set_hflip(ov5645, ctrl->val); val 823 drivers/media/i2c/ov5645.c ret = ov5645_set_vflip(ov5645, ctrl->val); val 199 drivers/media/i2c/ov5647.c static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val) val 202 drivers/media/i2c/ov5647.c unsigned char data[3] = { reg >> 8, reg & 0xff, val}; val 213 drivers/media/i2c/ov5647.c static int ov5647_read(struct v4l2_subdev *sd, u16 reg, u8 *val) val 226 drivers/media/i2c/ov5647.c ret = i2c_master_recv(client, val, 1); val 411 drivers/media/i2c/ov5647.c u8 val; val 414 drivers/media/i2c/ov5647.c ret = ov5647_read(sd, reg->reg & 0xff, &val); val 418 drivers/media/i2c/ov5647.c reg->val = val; val 427 drivers/media/i2c/ov5647.c return ov5647_write(sd, reg->reg & 0xff, reg->val & 0xff); val 71 drivers/media/i2c/ov5670.c u8 val; val 1840 drivers/media/i2c/ov5670.c u32 *val) val 1869 drivers/media/i2c/ov5670.c *val = be32_to_cpu(data_be); val 1876 drivers/media/i2c/ov5670.c u32 val) val 1891 drivers/media/i2c/ov5670.c tmp = cpu_to_be32(val); val 1914 drivers/media/i2c/ov5670.c ret = ov5670_write_reg(ov5670, regs[i].address, 1, regs[i].val); val 1975 drivers/media/i2c/ov5670.c u32 val; val 1985 drivers/media/i2c/ov5670.c OV5670_REG_VALUE_08BIT, &val); val 1990 drivers/media/i2c/ov5670.c val |= OV5670_TEST_PATTERN_ENABLE; val 1992 drivers/media/i2c/ov5670.c val &= ~OV5670_TEST_PATTERN_ENABLE; val 1995 drivers/media/i2c/ov5670.c OV5670_REG_VALUE_08BIT, val); val 2011 drivers/media/i2c/ov5670.c max = ov5670->cur_mode->height + ctrl->val - 8; val 2025 drivers/media/i2c/ov5670.c OV5670_REG_VALUE_16BIT, ctrl->val); val 2028 drivers/media/i2c/ov5670.c ret = ov5670_update_digital_gain(ov5670, ctrl->val); val 2033 drivers/media/i2c/ov5670.c OV5670_REG_VALUE_24BIT, ctrl->val << 4); val 2039 drivers/media/i2c/ov5670.c ov5670->cur_mode->height + ctrl->val); val 2042 drivers/media/i2c/ov5670.c ret = ov5670_enable_test_pattern(ov5670, ctrl->val); val 2046 drivers/media/i2c/ov5670.c __func__, ctrl->id, ctrl->val); val 2397 drivers/media/i2c/ov5670.c u32 val; val 2400 drivers/media/i2c/ov5670.c OV5670_REG_VALUE_24BIT, &val); val 2404 drivers/media/i2c/ov5670.c if (val != OV5670_CHIP_ID) { val 2406 drivers/media/i2c/ov5670.c OV5670_CHIP_ID, val); val 74 drivers/media/i2c/ov5675.c u8 val; val 512 drivers/media/i2c/ov5675.c static int ov5675_read_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 *val) val 537 drivers/media/i2c/ov5675.c *val = get_unaligned_be32(data_buf); val 542 drivers/media/i2c/ov5675.c static int ov5675_write_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 val) val 551 drivers/media/i2c/ov5675.c put_unaligned_be32(val << 8 * (4 - len), buf + 2); val 567 drivers/media/i2c/ov5675.c r_list->regs[i].val); val 618 drivers/media/i2c/ov5675.c exposure_max = (ov5675->cur_mode->height + ctrl->val - val 633 drivers/media/i2c/ov5675.c OV5675_REG_VALUE_16BIT, ctrl->val); val 637 drivers/media/i2c/ov5675.c ret = ov5675_update_digital_gain(ov5675, ctrl->val); val 643 drivers/media/i2c/ov5675.c OV5675_REG_VALUE_24BIT, ctrl->val << 3); val 649 drivers/media/i2c/ov5675.c ov5675->cur_mode->height + ctrl->val + val 654 drivers/media/i2c/ov5675.c ret = ov5675_test_pattern(ov5675, ctrl->val); val 988 drivers/media/i2c/ov5675.c u32 val; val 991 drivers/media/i2c/ov5675.c OV5675_REG_VALUE_24BIT, &val); val 995 drivers/media/i2c/ov5675.c if (val != OV5675_CHIP_ID) { val 997 drivers/media/i2c/ov5675.c OV5675_CHIP_ID, val); val 82 drivers/media/i2c/ov5695.c u8 val; val 706 drivers/media/i2c/ov5695.c u32 len, u32 val) val 719 drivers/media/i2c/ov5695.c val_be = cpu_to_be32(val); val 741 drivers/media/i2c/ov5695.c OV5695_REG_VALUE_08BIT, regs[i].val); val 748 drivers/media/i2c/ov5695.c u32 *val) val 776 drivers/media/i2c/ov5695.c *val = be32_to_cpu(data_be); val 900 drivers/media/i2c/ov5695.c u32 val; val 903 drivers/media/i2c/ov5695.c val = (pattern - 1) | OV5695_TEST_PATTERN_ENABLE; val 905 drivers/media/i2c/ov5695.c val = OV5695_TEST_PATTERN_DISABLE; val 908 drivers/media/i2c/ov5695.c OV5695_REG_VALUE_08BIT, val); val 1115 drivers/media/i2c/ov5695.c max = ov5695->cur_mode->height + ctrl->val - 4; val 1130 drivers/media/i2c/ov5695.c OV5695_REG_VALUE_24BIT, ctrl->val << 4); val 1134 drivers/media/i2c/ov5695.c OV5695_REG_VALUE_08BIT, ctrl->val); val 1139 drivers/media/i2c/ov5695.c ctrl->val & OV5695_DIGI_GAIN_L_MASK); val 1142 drivers/media/i2c/ov5695.c ctrl->val >> OV5695_DIGI_GAIN_H_SHIFT); val 1147 drivers/media/i2c/ov5695.c ctrl->val + ov5695->cur_mode->height); val 1150 drivers/media/i2c/ov5695.c ret = ov5695_enable_test_pattern(ov5695, ctrl->val); val 1154 drivers/media/i2c/ov5695.c __func__, ctrl->id, ctrl->val); val 175 drivers/media/i2c/ov6650.c u8 val; val 228 drivers/media/i2c/ov6650.c static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val) val 248 drivers/media/i2c/ov6650.c *val = data; val 257 drivers/media/i2c/ov6650.c static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val) val 260 drivers/media/i2c/ov6650.c unsigned char data[2] = { reg, val }; val 282 drivers/media/i2c/ov6650.c u8 val; val 285 drivers/media/i2c/ov6650.c ret = ov6650_reg_read(client, reg, &val); val 293 drivers/media/i2c/ov6650.c val &= ~mask; val 294 drivers/media/i2c/ov6650.c val |= set; val 296 drivers/media/i2c/ov6650.c ret = ov6650_reg_write(client, reg, val); val 329 drivers/media/i2c/ov6650.c priv->gain->val = reg; val 336 drivers/media/i2c/ov6650.c priv->blue->val = reg; val 337 drivers/media/i2c/ov6650.c priv->red->val = reg2; val 343 drivers/media/i2c/ov6650.c priv->exposure->val = reg; val 360 drivers/media/i2c/ov6650.c ctrl->val ? COMB_AGC : 0, COMB_AGC); val 361 drivers/media/i2c/ov6650.c if (!ret && !ctrl->val) val 362 drivers/media/i2c/ov6650.c ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val); val 366 drivers/media/i2c/ov6650.c ctrl->val ? COMB_AWB : 0, COMB_AWB); val 367 drivers/media/i2c/ov6650.c if (!ret && !ctrl->val) { val 368 drivers/media/i2c/ov6650.c ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val); val 371 drivers/media/i2c/ov6650.c priv->red->val); val 375 drivers/media/i2c/ov6650.c return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val), val 378 drivers/media/i2c/ov6650.c return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val), val 381 drivers/media/i2c/ov6650.c return ov6650_reg_write(client, REG_BRT, ctrl->val); val 383 drivers/media/i2c/ov6650.c ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val == val 385 drivers/media/i2c/ov6650.c if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL) val 387 drivers/media/i2c/ov6650.c priv->exposure->val); val 390 drivers/media/i2c/ov6650.c return ov6650_reg_write(client, REG_GAM1, ctrl->val); val 393 drivers/media/i2c/ov6650.c ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V); val 396 drivers/media/i2c/ov6650.c ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H); val 408 drivers/media/i2c/ov6650.c u8 val; val 415 drivers/media/i2c/ov6650.c ret = ov6650_reg_read(client, reg->reg, &val); val 417 drivers/media/i2c/ov6650.c reg->val = (__u64)val; val 427 drivers/media/i2c/ov6650.c if (reg->reg & ~0xff || reg->val & ~0xff) val 430 drivers/media/i2c/ov6650.c return ov6650_reg_write(client, reg->reg, reg->val); val 47 drivers/media/i2c/ov7251.c u8 val; val 624 drivers/media/i2c/ov7251.c static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val) val 631 drivers/media/i2c/ov7251.c regbuf[2] = val; val 636 drivers/media/i2c/ov7251.c __func__, ret, reg, val); val 643 drivers/media/i2c/ov7251.c static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val, val 647 drivers/media/i2c/ov7251.c u8 nregbuf = sizeof(reg) + num * sizeof(*val); val 656 drivers/media/i2c/ov7251.c memcpy(regbuf + 2, val, num); val 669 drivers/media/i2c/ov7251.c static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val) val 684 drivers/media/i2c/ov7251.c ret = i2c_master_recv(ov7251->i2c_client, val, 1); val 697 drivers/media/i2c/ov7251.c u8 val[3]; val 700 drivers/media/i2c/ov7251.c val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */ val 701 drivers/media/i2c/ov7251.c val[1] = (exposure & 0x0ff0) >> 4; /* goes to OV7251_AEC_EXPO_1 */ val 702 drivers/media/i2c/ov7251.c val[2] = (exposure & 0x000f) << 4; /* goes to OV7251_AEC_EXPO_2 */ val 704 drivers/media/i2c/ov7251.c return ov7251_write_seq_regs(ov7251, reg, val, 3); val 710 drivers/media/i2c/ov7251.c u8 val[2]; val 713 drivers/media/i2c/ov7251.c val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */ val 714 drivers/media/i2c/ov7251.c val[1] = gain & 0xff; /* goes to OV7251_AEC_AGC_ADJ_1 */ val 716 drivers/media/i2c/ov7251.c return ov7251_write_seq_regs(ov7251, reg, val, 2); val 727 drivers/media/i2c/ov7251.c ret = ov7251_write_reg(ov7251, settings->reg, settings->val); val 807 drivers/media/i2c/ov7251.c u8 val = ov7251->timing_format2; val 811 drivers/media/i2c/ov7251.c val |= OV7251_TIMING_FORMAT2_MIRROR; val 813 drivers/media/i2c/ov7251.c val &= ~OV7251_TIMING_FORMAT2_MIRROR; val 815 drivers/media/i2c/ov7251.c ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val); val 817 drivers/media/i2c/ov7251.c ov7251->timing_format2 = val; val 824 drivers/media/i2c/ov7251.c u8 val = ov7251->timing_format1; val 828 drivers/media/i2c/ov7251.c val |= OV7251_TIMING_FORMAT1_VFLIP; val 830 drivers/media/i2c/ov7251.c val &= ~OV7251_TIMING_FORMAT1_VFLIP; val 832 drivers/media/i2c/ov7251.c ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val); val 834 drivers/media/i2c/ov7251.c ov7251->timing_format1 = val; val 841 drivers/media/i2c/ov7251.c u8 val = ov7251->pre_isp_00; val 845 drivers/media/i2c/ov7251.c val |= OV7251_PRE_ISP_00_TEST_PATTERN; val 847 drivers/media/i2c/ov7251.c val &= ~OV7251_PRE_ISP_00_TEST_PATTERN; val 849 drivers/media/i2c/ov7251.c ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val); val 851 drivers/media/i2c/ov7251.c ov7251->pre_isp_00 = val; val 874 drivers/media/i2c/ov7251.c ret = ov7251_set_exposure(ov7251, ctrl->val); val 877 drivers/media/i2c/ov7251.c ret = ov7251_set_gain(ov7251, ctrl->val); val 880 drivers/media/i2c/ov7251.c ret = ov7251_set_test_pattern(ov7251, ctrl->val); val 883 drivers/media/i2c/ov7251.c ret = ov7251_set_hflip(ov7251, ctrl->val); val 886 drivers/media/i2c/ov7251.c ret = ov7251_set_vflip(ov7251, ctrl->val); val 611 drivers/media/i2c/ov7670.c static int ov7670_reset(struct v4l2_subdev *sd, u32 val) val 619 drivers/media/i2c/ov7670.c static int ov7670_init(struct v4l2_subdev *sd, u32 val) val 1570 drivers/media/i2c/ov7670.c return ov7670_g_gain(sd, &info->gain->val); val 1582 drivers/media/i2c/ov7670.c return ov7670_s_brightness(sd, ctrl->val); val 1584 drivers/media/i2c/ov7670.c return ov7670_s_contrast(sd, ctrl->val); val 1587 drivers/media/i2c/ov7670.c info->saturation->val, info->hue->val); val 1589 drivers/media/i2c/ov7670.c return ov7670_s_vflip(sd, ctrl->val); val 1591 drivers/media/i2c/ov7670.c return ov7670_s_hflip(sd, ctrl->val); val 1595 drivers/media/i2c/ov7670.c if (!ctrl->val) { val 1597 drivers/media/i2c/ov7670.c return ov7670_s_gain(sd, info->gain->val); val 1599 drivers/media/i2c/ov7670.c return ov7670_s_autogain(sd, ctrl->val); val 1603 drivers/media/i2c/ov7670.c if (ctrl->val == V4L2_EXPOSURE_MANUAL) { val 1605 drivers/media/i2c/ov7670.c return ov7670_s_exp(sd, info->exposure->val); val 1607 drivers/media/i2c/ov7670.c return ov7670_s_autoexp(sd, ctrl->val); val 1609 drivers/media/i2c/ov7670.c return ov7670_s_test_pattern(sd, ctrl->val); val 1622 drivers/media/i2c/ov7670.c unsigned char val = 0; val 1625 drivers/media/i2c/ov7670.c ret = ov7670_read(sd, reg->reg & 0xff, &val); val 1626 drivers/media/i2c/ov7670.c reg->val = val; val 1633 drivers/media/i2c/ov7670.c ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); val 762 drivers/media/i2c/ov772x.c u8 val; val 776 drivers/media/i2c/ov772x.c val = ctrl->val ? VFLIP_IMG : 0x00; val 778 drivers/media/i2c/ov772x.c val ^= VFLIP_IMG; val 779 drivers/media/i2c/ov772x.c return regmap_update_bits(regmap, COM3, VFLIP_IMG, val); val 781 drivers/media/i2c/ov772x.c val = ctrl->val ? HFLIP_IMG : 0x00; val 783 drivers/media/i2c/ov772x.c val ^= HFLIP_IMG; val 784 drivers/media/i2c/ov772x.c return regmap_update_bits(regmap, COM3, HFLIP_IMG, val); val 786 drivers/media/i2c/ov772x.c if (!ctrl->val) { val 794 drivers/media/i2c/ov772x.c val = 256 - ctrl->val; val 799 drivers/media/i2c/ov772x.c 0xff, val); val 814 drivers/media/i2c/ov772x.c unsigned int val; val 820 drivers/media/i2c/ov772x.c ret = regmap_read(priv->regmap, reg->reg, &val); val 824 drivers/media/i2c/ov772x.c reg->val = (__u64)val; val 835 drivers/media/i2c/ov772x.c reg->val > 0xff) val 838 drivers/media/i2c/ov772x.c return regmap_write(priv->regmap, reg->reg, reg->val); val 1034 drivers/media/i2c/ov772x.c u8 val; val 1077 drivers/media/i2c/ov772x.c val = cfmt->dsp3; val 1078 drivers/media/i2c/ov772x.c if (val) { val 1079 drivers/media/i2c/ov772x.c ret = regmap_update_bits(priv->regmap, DSP_CTRL3, UV_MASK, val); val 1092 drivers/media/i2c/ov772x.c val = cfmt->com3; val 1094 drivers/media/i2c/ov772x.c val |= VFLIP_IMG; val 1096 drivers/media/i2c/ov772x.c val |= HFLIP_IMG; val 1097 drivers/media/i2c/ov772x.c if (priv->vflip_ctrl->val) val 1098 drivers/media/i2c/ov772x.c val ^= VFLIP_IMG; val 1099 drivers/media/i2c/ov772x.c if (priv->hflip_ctrl->val) val 1100 drivers/media/i2c/ov772x.c val ^= HFLIP_IMG; val 1102 drivers/media/i2c/ov772x.c ret = regmap_update_bits(priv->regmap, COM3, SWAP_MASK | IMG_MASK, val); val 1117 drivers/media/i2c/ov772x.c if (priv->band_filter_ctrl->val) { val 1118 drivers/media/i2c/ov772x.c unsigned short band_filter = priv->band_filter_ctrl->val; val 275 drivers/media/i2c/ov7740.c unsigned int val = 0; val 278 drivers/media/i2c/ov7740.c ret = regmap_read(regmap, reg->reg & 0xff, &val); val 279 drivers/media/i2c/ov7740.c reg->val = val; val 291 drivers/media/i2c/ov7740.c regmap_write(regmap, reg->reg & 0xff, reg->val & 0xff); val 354 drivers/media/i2c/ov7740.c ov7740->blue_balance->val); val 358 drivers/media/i2c/ov7740.c ret = regmap_write(regmap, REG_RGAIN, ov7740->red_balance->val); val 436 drivers/media/i2c/ov7740.c if (!ctrl->val) val 446 drivers/media/i2c/ov7740.c ov7740->gain->val = (value1 << 8) | (value0 & 0xff); val 457 drivers/media/i2c/ov7740.c if (ctrl->val == V4L2_EXPOSURE_MANUAL) val 467 drivers/media/i2c/ov7740.c ov7740->exposure->val = (value1 << 8) | (value0 & 0xff); val 535 drivers/media/i2c/ov7740.c u8 val; val 542 drivers/media/i2c/ov7740.c ret = ov7740_set_white_balance(ov7740, ctrl->val); val 545 drivers/media/i2c/ov7740.c ret = ov7740_set_saturation(regmap, ctrl->val); val 548 drivers/media/i2c/ov7740.c ret = ov7740_set_brightness(regmap, ctrl->val); val 551 drivers/media/i2c/ov7740.c ret = ov7740_set_contrast(regmap, ctrl->val); val 554 drivers/media/i2c/ov7740.c val = ctrl->val ? REG0C_IMG_FLIP : 0x00; val 556 drivers/media/i2c/ov7740.c REG0C_IMG_FLIP, val); val 559 drivers/media/i2c/ov7740.c val = ctrl->val ? REG0C_IMG_MIRROR : 0x00; val 561 drivers/media/i2c/ov7740.c REG0C_IMG_MIRROR, val); val 564 drivers/media/i2c/ov7740.c if (!ctrl->val) val 565 drivers/media/i2c/ov7740.c ret = ov7740_set_gain(regmap, ov7740->gain->val); val 567 drivers/media/i2c/ov7740.c ret = ov7740_set_autogain(regmap, ctrl->val); val 571 drivers/media/i2c/ov7740.c if (ctrl->val == V4L2_EXPOSURE_MANUAL) val 572 drivers/media/i2c/ov7740.c ret = ov7740_set_exp(regmap, ov7740->exposure->val); val 574 drivers/media/i2c/ov7740.c ret = ov7740_set_autoexp(regmap, ctrl->val); val 74 drivers/media/i2c/ov8856.c u8 val; val 604 drivers/media/i2c/ov8856.c static int ov8856_read_reg(struct ov8856 *ov8856, u16 reg, u16 len, u32 *val) val 629 drivers/media/i2c/ov8856.c *val = get_unaligned_be32(data_buf); val 634 drivers/media/i2c/ov8856.c static int ov8856_write_reg(struct ov8856 *ov8856, u16 reg, u16 len, u32 val) val 643 drivers/media/i2c/ov8856.c put_unaligned_be32(val << 8 * (4 - len), buf + 2); val 659 drivers/media/i2c/ov8856.c r_list->regs[i].val); val 710 drivers/media/i2c/ov8856.c exposure_max = ov8856->cur_mode->height + ctrl->val - val 725 drivers/media/i2c/ov8856.c OV8856_REG_VALUE_16BIT, ctrl->val); val 729 drivers/media/i2c/ov8856.c ret = ov8856_update_digital_gain(ov8856, ctrl->val); val 735 drivers/media/i2c/ov8856.c OV8856_REG_VALUE_24BIT, ctrl->val << 4); val 741 drivers/media/i2c/ov8856.c ov8856->cur_mode->height + ctrl->val); val 745 drivers/media/i2c/ov8856.c ret = ov8856_test_pattern(ov8856, ctrl->val); val 1079 drivers/media/i2c/ov8856.c u32 val; val 1082 drivers/media/i2c/ov8856.c OV8856_REG_VALUE_24BIT, &val); val 1086 drivers/media/i2c/ov8856.c if (val != OV8856_CHIP_ID) { val 1088 drivers/media/i2c/ov8856.c OV8856_CHIP_ID, val); val 171 drivers/media/i2c/ov9640.c static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val) val 191 drivers/media/i2c/ov9640.c *val = data; val 200 drivers/media/i2c/ov9640.c static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val) val 204 drivers/media/i2c/ov9640.c unsigned char data[2] = { reg, val }; val 231 drivers/media/i2c/ov9640.c u8 val; val 234 drivers/media/i2c/ov9640.c ret = ov9640_reg_read(client, reg, &val); val 241 drivers/media/i2c/ov9640.c val |= set; val 242 drivers/media/i2c/ov9640.c val &= ~unset; val 244 drivers/media/i2c/ov9640.c ret = ov9640_reg_write(client, reg, val); val 280 drivers/media/i2c/ov9640.c if (ctrl->val) val 285 drivers/media/i2c/ov9640.c if (ctrl->val) val 300 drivers/media/i2c/ov9640.c u8 val; val 307 drivers/media/i2c/ov9640.c ret = ov9640_reg_read(client, reg->reg, &val); val 311 drivers/media/i2c/ov9640.c reg->val = (__u64)val; val 321 drivers/media/i2c/ov9640.c if (reg->reg & ~0xff || reg->val & ~0xff) val 324 drivers/media/i2c/ov9640.c return ov9640_reg_write(client, reg->reg, reg->val); val 402 drivers/media/i2c/ov9640.c u8 val; val 450 drivers/media/i2c/ov9640.c val = ov9640_regs[i].val; val 454 drivers/media/i2c/ov9640.c val |= alts->com7; val 457 drivers/media/i2c/ov9640.c val |= alts->com12; val 460 drivers/media/i2c/ov9640.c val |= alts->com13; val 463 drivers/media/i2c/ov9640.c val |= alts->com15; val 467 drivers/media/i2c/ov9640.c ret = ov9640_reg_write(client, ov9640_regs[i].reg, val); val 475 drivers/media/i2c/ov9640.c matrix_regs[i].val); val 491 drivers/media/i2c/ov9640.c ov9640_regs_dflt[i].val); val 193 drivers/media/i2c/ov9640.h u8 val; val 425 drivers/media/i2c/ov9650.c static int ov965x_read(struct ov965x *ov965x, u8 addr, u8 *val) val 432 drivers/media/i2c/ov9650.c *val = buf; val 434 drivers/media/i2c/ov9650.c *val = -1; val 437 drivers/media/i2c/ov9650.c __func__, *val, addr, ret); val 442 drivers/media/i2c/ov9650.c static int ov965x_write(struct ov965x *ov965x, u8 addr, u8 val) val 446 drivers/media/i2c/ov9650.c ret = regmap_write(ov965x->regmap, addr, val); val 449 drivers/media/i2c/ov9650.c __func__, val, addr, ret); val 637 drivers/media/i2c/ov9650.c ov965x->ctrls.blue_balance->val); val 641 drivers/media/i2c/ov9650.c ov965x->ctrls.red_balance->val); val 649 drivers/media/i2c/ov9650.c static int ov965x_set_brightness(struct ov965x *ov965x, int val) val 663 drivers/media/i2c/ov9650.c val += (NUM_BR_LEVELS / 2 + 1); val 664 drivers/media/i2c/ov9650.c if (val > NUM_BR_LEVELS) val 669 drivers/media/i2c/ov9650.c regs[val][i]); val 686 drivers/media/i2c/ov9650.c if (ctrls->auto_gain->val) val 696 drivers/media/i2c/ov9650.c unsigned int gain = ctrls->gain->val; val 726 drivers/media/i2c/ov9650.c ctrls->gain->val = (1 << m) * (16 + (rgain & 0xf)); val 782 drivers/media/i2c/ov9650.c unsigned int exposure = (ctrls->exposure->val * 100) val 796 drivers/media/i2c/ov9650.c ctrls->exposure->val = ((exposure * ov965x->exp_row_interval) val 810 drivers/media/i2c/ov9650.c if (ov965x->ctrls.hflip->val) val 813 drivers/media/i2c/ov9650.c if (ov965x->ctrls.vflip->val) val 822 drivers/media/i2c/ov9650.c static int ov965x_set_saturation(struct ov965x *ov965x, int val) val 835 drivers/media/i2c/ov9650.c val += (NUM_SAT_LEVELS / 2); val 836 drivers/media/i2c/ov9650.c if (val >= NUM_SAT_LEVELS) val 840 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, addr + i, regs[val][i]); val 868 drivers/media/i2c/ov9650.c if (!ctrl->val) val 878 drivers/media/i2c/ov9650.c ov965x->ctrls.gain->val = m * (16 + (gain & 0xf)); val 882 drivers/media/i2c/ov9650.c if (ctrl->val == V4L2_EXPOSURE_MANUAL) val 895 drivers/media/i2c/ov9650.c ov965x->ctrls.exposure->val = ((exposure * val 924 drivers/media/i2c/ov9650.c ctrl->name, ctrl->val, ov965x->power); val 938 drivers/media/i2c/ov9650.c ret = ov965x_set_white_balance(ov965x, ctrl->val); val 942 drivers/media/i2c/ov9650.c ret = ov965x_set_brightness(ov965x, ctrl->val); val 946 drivers/media/i2c/ov9650.c ret = ov965x_set_exposure(ov965x, ctrl->val); val 950 drivers/media/i2c/ov9650.c ret = ov965x_set_gain(ov965x, ctrl->val); val 958 drivers/media/i2c/ov9650.c ret = ov965x_set_banding_filter(ov965x, ctrl->val); val 962 drivers/media/i2c/ov9650.c ret = ov965x_set_saturation(ov965x, ctrl->val); val 966 drivers/media/i2c/ov9650.c ret = ov965x_set_sharpness(ov965x, ctrl->val); val 970 drivers/media/i2c/ov9650.c ret = ov965x_set_test_pattern(ov965x, ctrl->val); val 1320 drivers/media/i2c/ov9650.c return ov965x_set_banding_filter(ov965x, ctrls->light_freq->val); val 171 drivers/media/i2c/rj54n1cb0c.c u8 val; val 481 drivers/media/i2c/rj54n1cb0c.c ret = reg_write(client, rv->reg, rv->val); val 1139 drivers/media/i2c/rj54n1cb0c.c reg->val = reg_read(client, reg->reg); val 1141 drivers/media/i2c/rj54n1cb0c.c if (reg->val > 0xff) val 1156 drivers/media/i2c/rj54n1cb0c.c if (reg_write(client, reg->reg, reg->val) < 0) val 1198 drivers/media/i2c/rj54n1cb0c.c if (ctrl->val) val 1206 drivers/media/i2c/rj54n1cb0c.c if (ctrl->val) val 1214 drivers/media/i2c/rj54n1cb0c.c if (reg_write(client, RJ54N1_Y_GAIN, ctrl->val * 2) < 0) val 1219 drivers/media/i2c/rj54n1cb0c.c if (reg_set(client, RJ54N1_WB_SEL_WEIGHT_I, ctrl->val << 7, val 1222 drivers/media/i2c/rj54n1cb0c.c rj54n1->auto_wb = ctrl->val; val 400 drivers/media/i2c/s5c73m3/s5c73m3-core.c if (state->ctrls.stabilization->val) val 1347 drivers/media/i2c/s5c73m3/s5c73m3-core.c static int s5c73m3_gpio_set_value(struct s5c73m3 *priv, int id, u32 val) val 1351 drivers/media/i2c/s5c73m3/s5c73m3-core.c gpio_set_value(priv->gpio[id].gpio, !!val); val 41 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ctrl->val = V4L2_AUTO_FOCUS_STATUS_BUSY; val 45 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ctrl->val = V4L2_AUTO_FOCUS_STATUS_REACHED; val 53 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ctrl->val = V4L2_AUTO_FOCUS_STATUS_FAILED; val 80 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_colorfx(struct s5c73m3 *state, int val) val 92 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c if (colorfx[i][0] != val) val 115 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c switch (ctrls->exposure_metering->val) { val 131 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 exp_bias = ctrls->exposure_bias->val; val 137 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ctrls->exposure_bias->val, ctrls->exposure_metering->val, ret); val 142 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_white_balance(struct s5c73m3 *state, int val) val 155 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c if (wb[i][0] != val) val 176 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c if (c->focus_auto->val) val 185 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; val 186 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; val 187 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c bool af_lock = ctrl->val & V4L2_LOCK_FOCUS; val 190 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE) { val 197 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE) val 198 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c && state->ctrls.auto_wb->val) { val 205 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_FOCUS) val 217 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 mode = (c->af_distance->val == V4L2_AUTO_FOCUS_RANGE_MACRO) val 224 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c if (!ret || (c->focus_auto->is_new && c->focus_auto->val) || val 227 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c else if ((c->focus_auto->is_new && !c->focus_auto->val) || val 236 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_contrast(struct s5c73m3 *state, int val) val 238 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 reg = (val < 0) ? -val + 2 : val; val 242 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_saturation(struct s5c73m3 *state, int val) val 244 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 reg = (val < 0) ? -val + 2 : val; val 248 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_sharpness(struct s5c73m3 *state, int val) val 250 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 reg = (val < 0) ? -val + 2 : val; val 254 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_iso(struct s5c73m3 *state, int val) val 258 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c if (val == V4L2_ISO_SENSITIVITY_MANUAL) val 259 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c iso = state->ctrls.iso->val + 1; val 266 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_stabilization(struct s5c73m3 *state, int val) val 270 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c v4l2_dbg(1, s5c73m3_dbg, sd, "Image stabilization: %d\n", val); val 272 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c return s5c73m3_isp_command(state, COMM_FRAME_RATE, val ? val 290 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_scene_program(struct s5c73m3 *state, int val) val 310 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c v4l2_ctrl_get_menu(state->ctrls.scene_mode->id)[val]); val 312 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c return s5c73m3_isp_command(state, COMM_SCENE_MODE, scene_lookup[val]); val 315 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c static int s5c73m3_set_power_line_freq(struct s5c73m3 *state, int val) val 319 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c switch (val) { val 344 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ctrl->name, ctrl->val); val 366 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_white_balance(state, ctrl->val); val 370 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_contrast(state, ctrl->val); val 374 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_colorfx(state, ctrl->val); val 378 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_exposure(state, ctrl->val); val 382 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_auto_focus(state, ctrl->val); val 386 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_stabilization(state, ctrl->val); val 390 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_iso(state, ctrl->val); val 394 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_jpeg_quality(state, ctrl->val); val 398 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_power_line_freq(state, ctrl->val); val 402 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_saturation(state, ctrl->val); val 406 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_scene_program(state, ctrl->val); val 410 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_set_sharpness(state, ctrl->val); val 414 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_isp_command(state, COMM_WDR, !!ctrl->val); val 418 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c ret = s5c73m3_isp_command(state, COMM_ZOOM_STEP, ctrl->val); val 124 drivers/media/i2c/s5k4ecgx.c u16 val; val 201 drivers/media/i2c/s5k4ecgx.c static int s5k4ecgx_i2c_read(struct i2c_client *client, u16 addr, u16 *val) val 219 drivers/media/i2c/s5k4ecgx.c *val = be16_to_cpu(*((__be16 *)rbuf)); val 221 drivers/media/i2c/s5k4ecgx.c v4l2_dbg(4, debug, client, "i2c_read: 0x%04X : 0x%04x\n", addr, *val); val 226 drivers/media/i2c/s5k4ecgx.c static int s5k4ecgx_i2c_write(struct i2c_client *client, u16 addr, u16 val) val 228 drivers/media/i2c/s5k4ecgx.c u8 buf[4] = { addr >> 8, addr & 0xff, val >> 8, val & 0xff }; val 231 drivers/media/i2c/s5k4ecgx.c v4l2_dbg(4, debug, client, "i2c_write: 0x%04x : 0x%04x\n", addr, val); val 236 drivers/media/i2c/s5k4ecgx.c static int s5k4ecgx_write(struct i2c_client *client, u32 addr, u16 val) val 241 drivers/media/i2c/s5k4ecgx.c v4l2_dbg(3, debug, client, "write: 0x%08x : 0x%04x\n", addr, val); val 247 drivers/media/i2c/s5k4ecgx.c ret = s5k4ecgx_i2c_write(client, REG_CMDBUF0_ADDR, val); val 252 drivers/media/i2c/s5k4ecgx.c static int s5k4ecgx_read(struct i2c_client *client, u32 addr, u16 *val) val 261 drivers/media/i2c/s5k4ecgx.c ret = s5k4ecgx_i2c_read(client, REG_CMDBUF0_ADDR, val); val 331 drivers/media/i2c/s5k4ecgx.c u16 val; val 359 drivers/media/i2c/s5k4ecgx.c val = get_unaligned_le16(ptr); val 362 drivers/media/i2c/s5k4ecgx.c err = s5k4ecgx_write(client, addr, val); val 364 drivers/media/i2c/s5k4ecgx.c err = s5k4ecgx_i2c_write(client, REG_CMDBUF0_ADDR, val); val 457 drivers/media/i2c/s5k4ecgx.c static int s5k4ecgx_gpio_set_value(struct s5k4ecgx *priv, int id, u32 val) val 461 drivers/media/i2c/s5k4ecgx.c gpio_set_value(priv->gpio[id].gpio, val); val 631 drivers/media/i2c/s5k4ecgx.c v4l2_dbg(1, debug, sd, "ctrl: 0x%x, value: %d\n", ctrl->id, ctrl->val); val 636 drivers/media/i2c/s5k4ecgx.c err = s5k4ecgx_write(client, REG_USER_CONTRAST, ctrl->val); val 640 drivers/media/i2c/s5k4ecgx.c err = s5k4ecgx_write(client, REG_USER_SATURATION, ctrl->val); val 647 drivers/media/i2c/s5k4ecgx.c ctrl->val * SHARPNESS_DIV); val 651 drivers/media/i2c/s5k4ecgx.c err = s5k4ecgx_write(client, REG_USER_BRIGHTNESS, ctrl->val); val 842 drivers/media/i2c/s5k4ecgx.c static int s5k4ecgx_config_gpio(int nr, int val, const char *name) val 844 drivers/media/i2c/s5k4ecgx.c unsigned long flags = val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; val 448 drivers/media/i2c/s5k5baf.c static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val) val 450 drivers/media/i2c/s5k5baf.c u8 buf[4] = { addr >> 8, addr & 0xFF, val >> 8, val & 0xFF }; val 458 drivers/media/i2c/s5k5baf.c v4l2_dbg(3, debug, c, "i2c_write: 0x%04x : 0x%04x\n", addr, val); val 472 drivers/media/i2c/s5k5baf.c static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val) val 475 drivers/media/i2c/s5k5baf.c s5k5baf_i2c_write(state, REG_CMD_BUF, val); val 642 drivers/media/i2c/s5k5baf.c u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1); val 677 drivers/media/i2c/s5k5baf.c ctrls->gain_red->val, 1, val 679 drivers/media/i2c/s5k5baf.c ctrls->gain_blue->val, 1, val 705 drivers/media/i2c/s5k5baf.c unsigned int exp_time = state->ctrls.exposure->val; val 708 drivers/media/i2c/s5k5baf.c s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val); val 725 drivers/media/i2c/s5k5baf.c static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val) val 736 drivers/media/i2c/s5k5baf.c s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]); val 1554 drivers/media/i2c/s5k5baf.c v4l2_dbg(1, debug, sd, "ctrl: %s, value: %d\n", ctrl->name, ctrl->val); val 1563 drivers/media/i2c/s5k5baf.c s5k5baf_hw_set_awb(state, ctrl->val); val 1567 drivers/media/i2c/s5k5baf.c s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val); val 1571 drivers/media/i2c/s5k5baf.c s5k5baf_hw_set_colorfx(state, ctrl->val); val 1575 drivers/media/i2c/s5k5baf.c s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val); val 1579 drivers/media/i2c/s5k5baf.c s5k5baf_hw_set_auto_exposure(state, ctrl->val); val 1587 drivers/media/i2c/s5k5baf.c s5k5baf_hw_set_anti_flicker(state, ctrl->val); val 1591 drivers/media/i2c/s5k5baf.c s5k5baf_write(state, REG_USER_SATURATION, ctrl->val); val 1595 drivers/media/i2c/s5k5baf.c s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val); val 1599 drivers/media/i2c/s5k5baf.c s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val); val 1605 drivers/media/i2c/s5k5baf.c s5k5baf_hw_set_test_pattern(state, ctrl->val); val 186 drivers/media/i2c/s5k6aa.c u16 val; val 329 drivers/media/i2c/s5k6aa.c static int s5k6aa_i2c_read(struct i2c_client *client, u16 addr, u16 *val) val 347 drivers/media/i2c/s5k6aa.c *val = be16_to_cpu(*((__be16 *)rbuf)); val 349 drivers/media/i2c/s5k6aa.c v4l2_dbg(3, debug, client, "i2c_read: 0x%04X : 0x%04x\n", addr, *val); val 354 drivers/media/i2c/s5k6aa.c static int s5k6aa_i2c_write(struct i2c_client *client, u16 addr, u16 val) val 356 drivers/media/i2c/s5k6aa.c u8 buf[4] = {addr >> 8, addr & 0xFF, val >> 8, val & 0xFF}; val 359 drivers/media/i2c/s5k6aa.c v4l2_dbg(3, debug, client, "i2c_write: 0x%04X : 0x%04x\n", addr, val); val 365 drivers/media/i2c/s5k6aa.c static int s5k6aa_write(struct i2c_client *c, u16 addr, u16 val) val 370 drivers/media/i2c/s5k6aa.c return s5k6aa_i2c_write(c, REG_CMDBUF0_ADDR, val); val 374 drivers/media/i2c/s5k6aa.c static int s5k6aa_read(struct i2c_client *client, u16 addr, u16 *val) val 379 drivers/media/i2c/s5k6aa.c return s5k6aa_i2c_read(client, REG_CMDBUF0_ADDR, val); val 395 drivers/media/i2c/s5k6aa.c ret = s5k6aa_i2c_write(client, REG_CMDBUF0_ADDR, msg->val); val 469 drivers/media/i2c/s5k6aa.c unsigned int vflip = s5k6aa->ctrls.vflip->val ^ s5k6aa->inv_vflip; val 485 drivers/media/i2c/s5k6aa.c ret = s5k6aa_write(c, REG_SF_RGAIN, ctrls->gain_red->val); val 491 drivers/media/i2c/s5k6aa.c ret = s5k6aa_write(c, REG_SF_GGAIN, ctrls->gain_green->val); val 497 drivers/media/i2c/s5k6aa.c ret = s5k6aa_write(c, REG_SF_BGAIN, ctrls->gain_blue->val); val 534 drivers/media/i2c/s5k6aa.c unsigned int exp_time = s5k6aa->ctrls.exposure->val; val 550 drivers/media/i2c/s5k6aa.c ret = s5k6aa_set_user_gain(c, s5k6aa->ctrls.gain->val); val 586 drivers/media/i2c/s5k6aa.c static int s5k6aa_set_colorfx(struct s5k6aa *s5k6aa, int val) val 600 drivers/media/i2c/s5k6aa.c if (colorfx[i].id == val) val 812 drivers/media/i2c/s5k6aa.c static int s5k6aa_gpio_set_value(struct s5k6aa *priv, int id, u32 val) val 816 drivers/media/i2c/s5k6aa.c gpio_set_value(priv->gpio[id].gpio, !!val); val 1257 drivers/media/i2c/s5k6aa.c v4l2_dbg(1, debug, sd, "ctrl: 0x%x, value: %d\n", ctrl->id, ctrl->val); val 1271 drivers/media/i2c/s5k6aa.c err = s5k6aa_set_awb(s5k6aa, ctrl->val); val 1275 drivers/media/i2c/s5k6aa.c err = s5k6aa_write(client, REG_USER_BRIGHTNESS, ctrl->val); val 1279 drivers/media/i2c/s5k6aa.c err = s5k6aa_set_colorfx(s5k6aa, ctrl->val); val 1283 drivers/media/i2c/s5k6aa.c err = s5k6aa_write(client, REG_USER_CONTRAST, ctrl->val); val 1287 drivers/media/i2c/s5k6aa.c err = s5k6aa_set_auto_exposure(s5k6aa, ctrl->val); val 1291 drivers/media/i2c/s5k6aa.c err = s5k6aa_set_mirror(s5k6aa, ctrl->val); val 1298 drivers/media/i2c/s5k6aa.c err = s5k6aa_set_anti_flicker(s5k6aa, ctrl->val); val 1302 drivers/media/i2c/s5k6aa.c err = s5k6aa_write(client, REG_USER_SATURATION, ctrl->val); val 1306 drivers/media/i2c/s5k6aa.c err = s5k6aa_write(client, REG_USER_SHARPBLUR, ctrl->val); val 1310 drivers/media/i2c/s5k6aa.c err = s5k6aa_write(client, REG_P_COLORTEMP(idx), ctrl->val); val 289 drivers/media/i2c/saa6752hs.c static inline void set_reg8(struct i2c_client *client, uint8_t reg, uint8_t val) val 294 drivers/media/i2c/saa6752hs.c buf[1] = val; val 298 drivers/media/i2c/saa6752hs.c static inline void set_reg16(struct i2c_client *client, uint8_t reg, uint16_t val) val 303 drivers/media/i2c/saa6752hs.c buf[1] = val >> 8; val 304 drivers/media/i2c/saa6752hs.c buf[2] = val & 0xff; val 366 drivers/media/i2c/saa6752hs.c if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR && val 367 drivers/media/i2c/saa6752hs.c h->video_bitrate_peak->val < h->video_bitrate->val) val 368 drivers/media/i2c/saa6752hs.c h->video_bitrate_peak->val = h->video_bitrate->val; val 384 drivers/media/i2c/saa6752hs.c params->ts_pid_pmt = ctrl->val; val 387 drivers/media/i2c/saa6752hs.c params->ts_pid_audio = ctrl->val; val 390 drivers/media/i2c/saa6752hs.c params->ts_pid_video = ctrl->val; val 393 drivers/media/i2c/saa6752hs.c params->ts_pid_pcr = ctrl->val; val 396 drivers/media/i2c/saa6752hs.c params->au_encoding = ctrl->val; val 399 drivers/media/i2c/saa6752hs.c params->au_l2_bitrate = ctrl->val; val 402 drivers/media/i2c/saa6752hs.c params->au_ac3_bitrate = ctrl->val; val 409 drivers/media/i2c/saa6752hs.c params->vi_aspect = ctrl->val; val 412 drivers/media/i2c/saa6752hs.c params->vi_bitrate_mode = ctrl->val; val 413 drivers/media/i2c/saa6752hs.c params->vi_bitrate = h->video_bitrate->val / 1000; val 414 drivers/media/i2c/saa6752hs.c params->vi_bitrate_peak = h->video_bitrate_peak->val / 1000; val 416 drivers/media/i2c/saa6752hs.c ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR); val 324 drivers/media/i2c/saa7110.c saa7110_write(sd, 0x19, ctrl->val); val 327 drivers/media/i2c/saa7110.c saa7110_write(sd, 0x13, ctrl->val); val 330 drivers/media/i2c/saa7110.c saa7110_write(sd, 0x12, ctrl->val); val 333 drivers/media/i2c/saa7110.c saa7110_write(sd, 0x07, ctrl->val); val 819 drivers/media/i2c/saa7115.c if (state->agc->val) val 820 drivers/media/i2c/saa7115.c state->gain->val = val 834 drivers/media/i2c/saa7115.c saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val); val 838 drivers/media/i2c/saa7115.c saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val); val 842 drivers/media/i2c/saa7115.c saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val); val 846 drivers/media/i2c/saa7115.c saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val); val 851 drivers/media/i2c/saa7115.c if (state->agc->val) val 852 drivers/media/i2c/saa7115.c saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val); val 854 drivers/media/i2c/saa7115.c saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80); val 1350 drivers/media/i2c/saa7115.c static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val) val 1357 drivers/media/i2c/saa7115.c (val ? 0x80 : 0)); val 1392 drivers/media/i2c/saa7115.c static int saa711x_reset(struct v4l2_subdev *sd, u32 val) val 1509 drivers/media/i2c/saa7115.c reg->val = saa711x_read(sd, reg->reg & 0xff); val 1516 drivers/media/i2c/saa7115.c saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff); val 311 drivers/media/i2c/saa7127.c static int saa7127_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 317 drivers/media/i2c/saa7127.c if (i2c_smbus_write_byte_data(client, reg, val) == 0) val 655 drivers/media/i2c/saa7127.c reg->val = saa7127_read(sd, reg->reg & 0xff); val 662 drivers/media/i2c/saa7127.c saa7127_write(sd, reg->reg & 0xff, reg->val & 0xff); val 771 drivers/media/i2c/saa717x.c u32 val; val 790 drivers/media/i2c/saa717x.c val = mute | (mute << 8); val 792 drivers/media/i2c/saa717x.c val = (u8)decoder->audio_main_vol_l | val 796 drivers/media/i2c/saa717x.c saa717x_write(sd, 0x480, val); val 799 drivers/media/i2c/saa717x.c val = decoder->audio_main_bass & 0x1f; val 800 drivers/media/i2c/saa717x.c val |= (decoder->audio_main_treble & 0x1f) << 5; val 801 drivers/media/i2c/saa717x.c saa717x_write(sd, 0x488, val); val 869 drivers/media/i2c/saa717x.c saa717x_write(sd, 0x10a, ctrl->val); val 873 drivers/media/i2c/saa717x.c saa717x_write(sd, 0x10b, ctrl->val); val 877 drivers/media/i2c/saa717x.c saa717x_write(sd, 0x10c, ctrl->val); val 881 drivers/media/i2c/saa717x.c saa717x_write(sd, 0x10d, ctrl->val); val 885 drivers/media/i2c/saa717x.c state->audio_main_mute = ctrl->val; val 889 drivers/media/i2c/saa717x.c state->audio_main_volume = ctrl->val; val 893 drivers/media/i2c/saa717x.c state->audio_main_balance = ctrl->val; val 897 drivers/media/i2c/saa717x.c state->audio_main_treble = ctrl->val; val 901 drivers/media/i2c/saa717x.c state->audio_main_bass = ctrl->val; val 967 drivers/media/i2c/saa717x.c reg->val = saa717x_read(sd, reg->reg); val 975 drivers/media/i2c/saa717x.c u8 val = reg->val & 0xff; val 977 drivers/media/i2c/saa717x.c saa717x_write(sd, addr, val); val 207 drivers/media/i2c/saa7185.c static int saa7185_init(struct v4l2_subdev *sd, u32 val) val 42 drivers/media/i2c/smiapp-pll.c static int bounds_check(struct device *dev, uint32_t val, val 45 drivers/media/i2c/smiapp-pll.c if (val >= min && val <= max) val 48 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max); val 285 drivers/media/i2c/smiapp/smiapp-core.c sensor->link_freq->qmenu_int[sensor->link_freq->val]; val 313 drivers/media/i2c/smiapp/smiapp-core.c + sensor->vblank->val val 366 drivers/media/i2c/smiapp/smiapp-core.c if (sensor->hflip->val) val 369 drivers/media/i2c/smiapp/smiapp-core.c if (sensor->vflip->val) val 424 drivers/media/i2c/smiapp/smiapp-core.c SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL, ctrl->val); val 429 drivers/media/i2c/smiapp/smiapp-core.c SMIAPP_REG_U16_COARSE_INTEGRATION_TIME, ctrl->val); val 436 drivers/media/i2c/smiapp/smiapp-core.c if (sensor->hflip->val) val 439 drivers/media/i2c/smiapp/smiapp-core.c if (sensor->vflip->val) val 453 drivers/media/i2c/smiapp/smiapp-core.c exposure = sensor->exposure->val; val 458 drivers/media/i2c/smiapp/smiapp-core.c sensor->exposure->val = sensor->exposure->maximum; val 467 drivers/media/i2c/smiapp/smiapp-core.c + ctrl->val); val 473 drivers/media/i2c/smiapp/smiapp-core.c + ctrl->val); val 487 drivers/media/i2c/smiapp/smiapp-core.c ctrl->val == val 491 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_TEST_PATTERN_MODE, ctrl->val); val 496 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_TEST_DATA_RED, ctrl->val); val 500 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_TEST_DATA_GREENR, ctrl->val); val 504 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_TEST_DATA_BLUE, ctrl->val); val 508 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_TEST_DATA_GREENB, ctrl->val); val 651 drivers/media/i2c/smiapp/smiapp-core.c u32 val; val 656 drivers/media/i2c/smiapp/smiapp-core.c sensor, smiapp_reg_limits[limit[i]].addr, &val); val 659 drivers/media/i2c/smiapp/smiapp-core.c sensor->limits[limit[i]] = val; val 662 drivers/media/i2c/smiapp/smiapp-core.c smiapp_reg_limits[limit[i]].what, val, val); val 955 drivers/media/i2c/smiapp/smiapp-core.c dev_dbg(&client->dev, "vblank\t\t%d\n", sensor->vblank->val); val 956 drivers/media/i2c/smiapp/smiapp-core.c dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val); val 961 drivers/media/i2c/smiapp/smiapp-core.c + sensor->hblank->val) * val 963 drivers/media/i2c/smiapp/smiapp-core.c + sensor->vblank->val) / 100)); val 1040 drivers/media/i2c/smiapp/smiapp-core.c u32 val; val 1053 drivers/media/i2c/smiapp/smiapp-core.c rval = smiapp_read(sensor, SMIAPP_REG_U8_CCI_ADDRESS_CONTROL, &val); val 1057 drivers/media/i2c/smiapp/smiapp-core.c if (val != sensor->hwcfg->i2c_addr_alt << 1) val 1857 drivers/media/i2c/smiapp/smiapp-core.c int val = 0; val 1866 drivers/media/i2c/smiapp/smiapp-core.c val -= SCALING_GOODNESS; val 1868 drivers/media/i2c/smiapp/smiapp-core.c val -= SCALING_GOODNESS; val 1873 drivers/media/i2c/smiapp/smiapp-core.c val -= SCALING_GOODNESS; val 1875 drivers/media/i2c/smiapp/smiapp-core.c val -= SCALING_GOODNESS; val 1878 drivers/media/i2c/smiapp/smiapp-core.c val -= abs(w - ask_w); val 1879 drivers/media/i2c/smiapp/smiapp-core.c val -= abs(h - ask_h); val 1882 drivers/media/i2c/smiapp/smiapp-core.c val -= SCALING_GOODNESS_EXTREME; val 1885 drivers/media/i2c/smiapp/smiapp-core.c w, ask_w, h, ask_h, val); val 1887 drivers/media/i2c/smiapp/smiapp-core.c return val; val 2972 drivers/media/i2c/smiapp/smiapp-core.c u32 val; val 2975 drivers/media/i2c/smiapp/smiapp-core.c SMIAPP_REG_U8_BINNING_SUBTYPES, &val); val 2980 drivers/media/i2c/smiapp/smiapp-core.c sensor->nbinning_subtypes = min_t(u8, val, val 2985 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val); val 2991 drivers/media/i2c/smiapp/smiapp-core.c *(struct smiapp_binning_subtype *)&val; val 15 drivers/media/i2c/smiapp/smiapp-quirk.c static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val) val 17 drivers/media/i2c/smiapp/smiapp-quirk.c return smiapp_write(sensor, SMIAPP_REG_MK_U8(reg), val); val 27 drivers/media/i2c/smiapp/smiapp-quirk.c rval = smiapp_write_8(sensor, regs->reg, regs->val); val 31 drivers/media/i2c/smiapp/smiapp-quirk.c rval, regs->reg, regs->val); val 40 drivers/media/i2c/smiapp/smiapp-quirk.c u32 limit, u32 val) val 46 drivers/media/i2c/smiapp/smiapp-quirk.c smiapp_reg_limits[limit].what, val, val); val 47 drivers/media/i2c/smiapp/smiapp-quirk.c sensor->limits[limit] = val; val 47 drivers/media/i2c/smiapp/smiapp-quirk.h u32 *val); val 55 drivers/media/i2c/smiapp/smiapp-quirk.h u8 val; val 59 drivers/media/i2c/smiapp/smiapp-quirk.h u32 limit, u32 val); val 64 drivers/media/i2c/smiapp/smiapp-quirk.h .val = _val, \ val 68 drivers/media/i2c/smiapp/smiapp-regs.c u16 len, u32 *val) val 100 drivers/media/i2c/smiapp/smiapp-regs.c *val = 0; val 104 drivers/media/i2c/smiapp/smiapp-regs.c *val = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + val 108 drivers/media/i2c/smiapp/smiapp-regs.c *val = (data[0] << 8) + data[1]; val 111 drivers/media/i2c/smiapp/smiapp-regs.c *val = data[0]; val 127 drivers/media/i2c/smiapp/smiapp-regs.c u16 len, u32 *val) val 132 drivers/media/i2c/smiapp/smiapp-regs.c *val = 0; val 140 drivers/media/i2c/smiapp/smiapp-regs.c *val |= val8 << ((len - i - 1) << 3); val 150 drivers/media/i2c/smiapp/smiapp-regs.c static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, val 162 drivers/media/i2c/smiapp/smiapp-regs.c rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val); val 165 drivers/media/i2c/smiapp/smiapp-regs.c val); val 170 drivers/media/i2c/smiapp/smiapp-regs.c *val = float_to_u32_mul_1000000(client, *val); val 175 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val) val 178 drivers/media/i2c/smiapp/smiapp-regs.c sensor, reg, val, val 183 drivers/media/i2c/smiapp/smiapp-regs.c static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val, val 188 drivers/media/i2c/smiapp/smiapp-regs.c *val = 0; val 189 drivers/media/i2c/smiapp/smiapp-regs.c rval = smiapp_call_quirk(sensor, reg_access, false, ®, val); val 196 drivers/media/i2c/smiapp/smiapp-regs.c return __smiapp_read(sensor, reg, val, true); val 198 drivers/media/i2c/smiapp/smiapp-regs.c return smiapp_read_no_quirk(sensor, reg, val); val 201 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val) val 203 drivers/media/i2c/smiapp/smiapp-regs.c return smiapp_read_quirk(sensor, reg, val, false); val 206 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val) val 208 drivers/media/i2c/smiapp/smiapp-regs.c return smiapp_read_quirk(sensor, reg, val, true); val 211 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) val 240 drivers/media/i2c/smiapp/smiapp-regs.c data[2] = val; val 243 drivers/media/i2c/smiapp/smiapp-regs.c data[2] = val >> 8; val 244 drivers/media/i2c/smiapp/smiapp-regs.c data[3] = val; val 247 drivers/media/i2c/smiapp/smiapp-regs.c data[2] = val >> 24; val 248 drivers/media/i2c/smiapp/smiapp-regs.c data[3] = val >> 16; val 249 drivers/media/i2c/smiapp/smiapp-regs.c data[4] = val >> 8; val 250 drivers/media/i2c/smiapp/smiapp-regs.c data[5] = val; val 275 drivers/media/i2c/smiapp/smiapp-regs.c "wrote 0x%x to offset 0x%x error %d\n", val, offset, r); val 284 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val) val 288 drivers/media/i2c/smiapp/smiapp-regs.c rval = smiapp_call_quirk(sensor, reg_access, true, ®, &val); val 294 drivers/media/i2c/smiapp/smiapp-regs.c return smiapp_write_no_quirk(sensor, reg, val); val 30 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val); val 31 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val); val 32 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val); val 33 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val); val 34 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val); val 47 drivers/media/i2c/sony-btf-mpx.c static int mpx_write(struct i2c_client *client, int dev, int addr, int val) val 55 drivers/media/i2c/sony-btf-mpx.c buffer[3] = val >> 8; val 56 drivers/media/i2c/sony-btf-mpx.c buffer[4] = val & 0xff; val 177 drivers/media/i2c/sr030pc30.c u16 val; val 310 drivers/media/i2c/sr030pc30.c static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val) val 318 drivers/media/i2c/sr030pc30.c client, reg_addr & 0xFF, val); val 326 drivers/media/i2c/sr030pc30.c int ret = cam_i2c_write(sd, msg->addr, msg->val); val 425 drivers/media/i2c/sr030pc30.c __func__, ctrl->id, ctrl->val); val 431 drivers/media/i2c/sr030pc30.c ctrl->val ? 0x2E : 0x2F); val 434 drivers/media/i2c/sr030pc30.c ctrl->val ? 0xFB : 0x7B); val 437 drivers/media/i2c/sr030pc30.c ret = cam_i2c_write(sd, MWB_BGAIN_REG, info->blue->val); val 439 drivers/media/i2c/sr030pc30.c ret = cam_i2c_write(sd, MWB_RGAIN_REG, info->red->val); val 446 drivers/media/i2c/sr030pc30.c ctrl->val == V4L2_EXPOSURE_AUTO ? 0xDC : 0x0C); val 448 drivers/media/i2c/sr030pc30.c unsigned long expos = info->exp->val; val 218 drivers/media/i2c/st-mipid02.c static int mipid02_read_reg(struct mipid02_dev *bridge, u16 reg, u8 *val) val 235 drivers/media/i2c/st-mipid02.c msg[1].buf = val; val 248 drivers/media/i2c/st-mipid02.c static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val) val 257 drivers/media/i2c/st-mipid02.c buf[2] = val; val 197 drivers/media/i2c/tc358743.c __le32 val = 0; val 199 drivers/media/i2c/tc358743.c i2c_rd(sd, reg, (u8 __force *)&val, n); val 201 drivers/media/i2c/tc358743.c return le32_to_cpu(val); val 204 drivers/media/i2c/tc358743.c static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) val 206 drivers/media/i2c/tc358743.c __le32 raw = cpu_to_le32(val); val 216 drivers/media/i2c/tc358743.c static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) val 218 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, val, 1); val 222 drivers/media/i2c/tc358743.c u8 mask, u8 val) val 224 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1); val 232 drivers/media/i2c/tc358743.c static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) val 234 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, val, 2); val 237 drivers/media/i2c/tc358743.c static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) val 239 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); val 247 drivers/media/i2c/tc358743.c static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) val 249 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, val, 4); val 1375 drivers/media/i2c/tc358743.c reg->val = i2c_rdreg(sd, reg->reg, reg->size); val 1401 drivers/media/i2c/tc358743.c i2c_wrreg(sd, (u16)reg->reg, reg->val, val 309 drivers/media/i2c/tda1997x.c int val; val 311 drivers/media/i2c/tda1997x.c val = i2c_smbus_read_byte_data(state->client_cec, reg); val 312 drivers/media/i2c/tda1997x.c if (val < 0) { val 314 drivers/media/i2c/tda1997x.c val = -1; val 317 drivers/media/i2c/tda1997x.c return val; val 320 drivers/media/i2c/tda1997x.c static int tda1997x_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 325 drivers/media/i2c/tda1997x.c ret = i2c_smbus_write_byte_data(state->client_cec, reg, val); val 328 drivers/media/i2c/tda1997x.c reg, val); val 361 drivers/media/i2c/tda1997x.c int val; val 365 drivers/media/i2c/tda1997x.c val = -1; val 369 drivers/media/i2c/tda1997x.c val = i2c_smbus_read_byte_data(state->client, reg&0xff); val 370 drivers/media/i2c/tda1997x.c if (val < 0) { val 372 drivers/media/i2c/tda1997x.c val = -1; val 378 drivers/media/i2c/tda1997x.c return val; val 383 drivers/media/i2c/tda1997x.c int val; val 386 drivers/media/i2c/tda1997x.c val = io_read(sd, reg); val 387 drivers/media/i2c/tda1997x.c if (val < 0) val 388 drivers/media/i2c/tda1997x.c return val; val 389 drivers/media/i2c/tda1997x.c lval |= (val << 8); val 390 drivers/media/i2c/tda1997x.c val = io_read(sd, reg + 1); val 391 drivers/media/i2c/tda1997x.c if (val < 0) val 392 drivers/media/i2c/tda1997x.c return val; val 393 drivers/media/i2c/tda1997x.c lval |= val; val 400 drivers/media/i2c/tda1997x.c int val; val 403 drivers/media/i2c/tda1997x.c val = io_read(sd, reg); val 404 drivers/media/i2c/tda1997x.c if (val < 0) val 405 drivers/media/i2c/tda1997x.c return val; val 406 drivers/media/i2c/tda1997x.c lval |= (val << 16); val 407 drivers/media/i2c/tda1997x.c val = io_read(sd, reg + 1); val 408 drivers/media/i2c/tda1997x.c if (val < 0) val 409 drivers/media/i2c/tda1997x.c return val; val 410 drivers/media/i2c/tda1997x.c lval |= (val << 8); val 411 drivers/media/i2c/tda1997x.c val = io_read(sd, reg + 2); val 412 drivers/media/i2c/tda1997x.c if (val < 0) val 413 drivers/media/i2c/tda1997x.c return val; val 414 drivers/media/i2c/tda1997x.c lval |= val; val 423 drivers/media/i2c/tda1997x.c int val; val 426 drivers/media/i2c/tda1997x.c val = io_read(sd, reg + i); val 427 drivers/media/i2c/tda1997x.c if (val < 0) val 429 drivers/media/i2c/tda1997x.c data[i] = val; val 436 drivers/media/i2c/tda1997x.c static int io_write(struct v4l2_subdev *sd, u16 reg, u8 val) val 447 drivers/media/i2c/tda1997x.c ret = i2c_smbus_write_byte_data(state->client, reg & 0xff, val); val 450 drivers/media/i2c/tda1997x.c reg&0xff, val); val 460 drivers/media/i2c/tda1997x.c static int io_write16(struct v4l2_subdev *sd, u16 reg, u16 val) val 464 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg, (val >> 8) & 0xff); val 467 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg + 1, val & 0xff); val 473 drivers/media/i2c/tda1997x.c static int io_write24(struct v4l2_subdev *sd, u16 reg, u32 val) val 477 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg, (val >> 16) & 0xff); val 480 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg + 1, (val >> 8) & 0xff); val 483 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg + 2, val & 0xff); val 2045 drivers/media/i2c/tda1997x.c state->rgb_quantization_range = ctrl->val; val 2060 drivers/media/i2c/tda1997x.c ctrl->val = state->avi_infoframe.content_type; val 2317 drivers/media/i2c/tda1997x.c u32 reg, val, i; val 2323 drivers/media/i2c/tda1997x.c i * 2 + 1, &val); val 2325 drivers/media/i2c/tda1997x.c pdata->vidout_port_cfg[reg] = val; val 220 drivers/media/i2c/tda7432.c static int tda7432_write(struct v4l2_subdev *sd, int subaddr, int val) val 226 drivers/media/i2c/tda7432.c v4l2_dbg(1, debug, sd, "Writing %d 0x%x\n", subaddr, val); val 228 drivers/media/i2c/tda7432.c buffer[1] = val; val 231 drivers/media/i2c/tda7432.c subaddr, val); val 280 drivers/media/i2c/tda7432.c if (t->balance->val < 0) { val 282 drivers/media/i2c/tda7432.c rr = rf = -t->balance->val; val 284 drivers/media/i2c/tda7432.c } else if (t->balance->val > 0) { val 287 drivers/media/i2c/tda7432.c lr = lf = t->balance->val; val 293 drivers/media/i2c/tda7432.c if (t->mute->val) { val 306 drivers/media/i2c/tda7432.c volume = 0x6f - ctrl->val; val 313 drivers/media/i2c/tda7432.c bass = t->bass->val; val 314 drivers/media/i2c/tda7432.c treble = t->treble->val; val 47 drivers/media/i2c/tda9840.c static void tda9840_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 51 drivers/media/i2c/tda9840.c if (i2c_smbus_write_byte_data(client, reg, val)) val 53 drivers/media/i2c/tda9840.c val, reg); val 67 drivers/media/i2c/ths7303.c static int ths7303_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 74 drivers/media/i2c/ths7303.c ret = i2c_smbus_write_byte_data(client, reg, val); val 88 drivers/media/i2c/ths7303.c u8 val, sel = 0; val 112 drivers/media/i2c/ths7303.c val = (sel << 6) | (sel << 3); val 114 drivers/media/i2c/ths7303.c val |= (pdata->ch_1 & 0x27); val 115 drivers/media/i2c/ths7303.c err = ths7303_write(sd, THS7303_CHANNEL_1, val); val 119 drivers/media/i2c/ths7303.c val = (sel << 6) | (sel << 3); val 121 drivers/media/i2c/ths7303.c val |= (pdata->ch_2 & 0x27); val 122 drivers/media/i2c/ths7303.c err = ths7303_write(sd, THS7303_CHANNEL_2, val); val 126 drivers/media/i2c/ths7303.c val = (sel << 6) | (sel << 3); val 128 drivers/media/i2c/ths7303.c val |= (pdata->ch_3 & 0x27); val 129 drivers/media/i2c/ths7303.c err = ths7303_write(sd, THS7303_CHANNEL_3, val); val 222 drivers/media/i2c/ths7303.c reg->val = ths7303_read(sd, reg->reg); val 229 drivers/media/i2c/ths7303.c ths7303_write(sd, reg->reg, reg->val); val 266 drivers/media/i2c/ths7303.c u8 val = ths7303_read(sd, reg); val 268 drivers/media/i2c/ths7303.c if ((val & 0x7) == 0) { val 274 drivers/media/i2c/ths7303.c v4l2_info(sd, " value 0x%x\n", val); val 275 drivers/media/i2c/ths7303.c v4l2_info(sd, " %s\n", stc_lpf_sel_txt[(val >> 6) & 0x3]); val 276 drivers/media/i2c/ths7303.c v4l2_info(sd, " %s\n", in_mux_sel_txt[(val >> 5) & 0x1]); val 277 drivers/media/i2c/ths7303.c v4l2_info(sd, " %s\n", lpf_freq_sel_txt[(val >> 3) & 0x3]); val 278 drivers/media/i2c/ths7303.c v4l2_info(sd, " %s\n", in_bias_sel_dis_cont_txt[(val >> 0) & 0x7]); val 78 drivers/media/i2c/ths8200.c static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 85 drivers/media/i2c/ths8200.c ret = i2c_smbus_write_byte_data(client, reg, val); val 108 drivers/media/i2c/ths8200.c reg->val = ths8200_read(sd, reg->reg & 0xff); val 117 drivers/media/i2c/ths8200.c ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff); val 45 drivers/media/i2c/tlv320aic23b.c static int tlv320aic23b_write(struct v4l2_subdev *sd, int reg, u16 val) val 57 drivers/media/i2c/tlv320aic23b.c (reg << 1) | (val >> 8), val & 0xff) == 0) val 59 drivers/media/i2c/tlv320aic23b.c v4l2_err(sd, "I2C: cannot write %03x to register R%d\n", val, reg); val 89 drivers/media/i2c/tlv320aic23b.c if (!ctrl->val) val 154 drivers/media/i2c/tvaudio.c static int chip_write(struct CHIPSTATE *chip, int subaddr, int val) val 162 drivers/media/i2c/tvaudio.c v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val); val 163 drivers/media/i2c/tvaudio.c chip->shadow.bytes[1] = val; val 164 drivers/media/i2c/tvaudio.c buffer[0] = val; val 167 drivers/media/i2c/tvaudio.c v4l2_warn(sd, "I/O error (write 0x%x)\n", val); val 181 drivers/media/i2c/tvaudio.c subaddr, val); val 182 drivers/media/i2c/tvaudio.c chip->shadow.bytes[subaddr+1] = val; val 184 drivers/media/i2c/tvaudio.c buffer[1] = val; val 188 drivers/media/i2c/tvaudio.c subaddr, val); val 198 drivers/media/i2c/tvaudio.c int subaddr, int val, int mask) val 204 drivers/media/i2c/tvaudio.c val = (chip->shadow.bytes[1] & ~mask) | (val & mask); val 213 drivers/media/i2c/tvaudio.c val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask); val 216 drivers/media/i2c/tvaudio.c return chip_write(chip, subaddr, val); val 419 drivers/media/i2c/tvaudio.c int val, mode; val 423 drivers/media/i2c/tvaudio.c val = chip_read(chip); val 424 drivers/media/i2c/tvaudio.c if (val < 0) val 427 drivers/media/i2c/tvaudio.c if (val & TDA9840_DS_DUAL) val 429 drivers/media/i2c/tvaudio.c if (val & TDA9840_ST_STEREO) val 434 drivers/media/i2c/tvaudio.c val, mode); val 581 drivers/media/i2c/tvaudio.c static int tda9855_volume(int val) { return val/0x2e8+0x27; } val 582 drivers/media/i2c/tvaudio.c static int tda9855_bass(int val) { return val/0xccc+0x06; } val 583 drivers/media/i2c/tvaudio.c static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; } val 587 drivers/media/i2c/tvaudio.c int mode, val; val 592 drivers/media/i2c/tvaudio.c val = chip_read(chip); val 593 drivers/media/i2c/tvaudio.c if (val < 0) val 596 drivers/media/i2c/tvaudio.c if (val & TDA985x_STP) val 598 drivers/media/i2c/tvaudio.c if (val & TDA985x_SAPP) val 751 drivers/media/i2c/tvaudio.c int val,mode; val 755 drivers/media/i2c/tvaudio.c val = chip_read(chip); val 756 drivers/media/i2c/tvaudio.c if (val < 0) val 759 drivers/media/i2c/tvaudio.c if (val & TDA9873_STEREO) val 761 drivers/media/i2c/tvaudio.c if (val & TDA9873_DUAL) val 765 drivers/media/i2c/tvaudio.c val, mode); val 1227 drivers/media/i2c/tvaudio.c static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); } val 1228 drivers/media/i2c/tvaudio.c static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); } val 1229 drivers/media/i2c/tvaudio.c static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); } val 1295 drivers/media/i2c/tvaudio.c static int tea6300_shift10(int val) { return val >> 10; } val 1296 drivers/media/i2c/tvaudio.c static int tea6300_shift12(int val) { return val >> 12; } val 1300 drivers/media/i2c/tvaudio.c static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; } val 1301 drivers/media/i2c/tvaudio.c static int tea6320_shift11(int val) { return val >> 11; } val 1338 drivers/media/i2c/tvaudio.c static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; } val 1339 drivers/media/i2c/tvaudio.c static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; } val 1422 drivers/media/i2c/tvaudio.c int val, mode; val 1426 drivers/media/i2c/tvaudio.c val = chip_read(chip); val 1427 drivers/media/i2c/tvaudio.c if (val < 0) val 1430 drivers/media/i2c/tvaudio.c if (val & TA8874Z_B1){ val 1432 drivers/media/i2c/tvaudio.c }else if (!(val & TA8874Z_B0)){ val 1751 drivers/media/i2c/tvaudio.c chip->muted = ctrl->val; val 1762 drivers/media/i2c/tvaudio.c volume = chip->volume->val; val 1763 drivers/media/i2c/tvaudio.c balance = chip->balance->val; val 1772 drivers/media/i2c/tvaudio.c chip_write(chip, desc->bassreg, desc->bassfunc(ctrl->val)); val 1775 drivers/media/i2c/tvaudio.c chip_write(chip, desc->treblereg, desc->treblefunc(ctrl->val)); val 306 drivers/media/i2c/tvp514x.c u32 val; val 308 drivers/media/i2c/tvp514x.c val = tvp514x_read_reg(sd, reg); val 309 drivers/media/i2c/tvp514x.c v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val); val 321 drivers/media/i2c/tvp514x.c static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val) val 328 drivers/media/i2c/tvp514x.c err = i2c_smbus_write_byte_data(client, reg, val); val 361 drivers/media/i2c/tvp514x.c msleep(next->val); val 368 drivers/media/i2c/tvp514x.c err = tvp514x_write_reg(sd, next->reg, (u8) next->val); val 632 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_VIDEO_STD].val = val 678 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel; val 679 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel; val 701 drivers/media/i2c/tvp514x.c value = ctrl->val; val 707 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_BRIGHTNESS].val = value; val 712 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_CONTRAST].val = value; val 717 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_SATURATION].val = value; val 726 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_HUE].val = value; val 731 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val = value; val 736 drivers/media/i2c/tvp514x.c ctrl->id, ctrl->val); val 1062 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_OUTPUT_FORMATTER2].val |= val 1064 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_SYNC_CONTROL].val |= val 1068 drivers/media/i2c/tvp514x.c decoder->tvp514x_regs[REG_VIDEO_STD].val = val 271 drivers/media/i2c/tvp514x_regs.h u32 val; val 91 drivers/media/i2c/tvp5150.c int ret, val; val 93 drivers/media/i2c/tvp5150.c ret = regmap_read(decoder->regmap, addr, &val); val 97 drivers/media/i2c/tvp5150.c return val; val 263 drivers/media/i2c/tvp5150.c unsigned int mask, val; val 301 drivers/media/i2c/tvp5150.c val = TVP5150_MISC_CTL_HVLK; val 303 drivers/media/i2c/tvp5150.c val = TVP5150_MISC_CTL_GPCL; val 304 drivers/media/i2c/tvp5150.c regmap_update_bits(decoder->regmap, TVP5150_MISC_CTL, mask, val); val 793 drivers/media/i2c/tvp5150.c int val = tvp5150_read(sd, TVP5150_STATUS_REG_5); val 795 drivers/media/i2c/tvp5150.c switch (val & 0x0F) { val 876 drivers/media/i2c/tvp5150.c static int tvp5150_reset(struct v4l2_subdev *sd, u32 val) val 957 drivers/media/i2c/tvp5150.c regmap_write(decoder->regmap, TVP5150_BRIGHT_CTL, ctrl->val); val 960 drivers/media/i2c/tvp5150.c regmap_write(decoder->regmap, TVP5150_CONTRAST_CTL, ctrl->val); val 964 drivers/media/i2c/tvp5150.c ctrl->val); val 967 drivers/media/i2c/tvp5150.c regmap_write(decoder->regmap, TVP5150_HUE_CTL, ctrl->val); val 970 drivers/media/i2c/tvp5150.c decoder->enable = ctrl->val ? false : true; val 1213 drivers/media/i2c/tvp5150.c unsigned int mask, val = 0, int_val = 0; val 1223 drivers/media/i2c/tvp5150.c val = decoder->lock ? decoder->oe : 0; val 1225 drivers/media/i2c/tvp5150.c val = decoder->oe; val 1230 drivers/media/i2c/tvp5150.c regmap_update_bits(decoder->regmap, TVP5150_MISC_CTL, mask, val); val 1332 drivers/media/i2c/tvp5150.c reg->val = res; val 1341 drivers/media/i2c/tvp5150.c return regmap_write(decoder->regmap, reg->reg & 0xff, reg->val & 0xff); val 520 drivers/media/i2c/tvp7002.c u8 val, int *err) val 523 drivers/media/i2c/tvp7002.c *err = tvp7002_write(sd, reg, val); val 592 drivers/media/i2c/tvp7002.c tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error); val 593 drivers/media/i2c/tvp7002.c tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error); val 594 drivers/media/i2c/tvp7002.c tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error); val 687 drivers/media/i2c/tvp7002.c u8 val; val 690 drivers/media/i2c/tvp7002.c ret = tvp7002_read(sd, reg->reg & 0xff, &val); val 691 drivers/media/i2c/tvp7002.c reg->val = val; val 707 drivers/media/i2c/tvp7002.c return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff); val 171 drivers/media/i2c/tw2804.c ctrl->val = read_reg(client, TW2804_REG_GAIN, 0); val 175 drivers/media/i2c/tw2804.c ctrl->val = read_reg(client, TW2804_REG_CHROMA_GAIN, 0); val 179 drivers/media/i2c/tw2804.c ctrl->val = read_reg(client, TW2804_REG_BLUE_BALANCE, 0); val 183 drivers/media/i2c/tw2804.c ctrl->val = read_reg(client, TW2804_REG_RED_BALANCE, 0); val 202 drivers/media/i2c/tw2804.c if (ctrl->val == 0) val 213 drivers/media/i2c/tw2804.c reg = (reg & ~(0x03)) | (ctrl->val == 0 ? 0x02 : 0x03); val 217 drivers/media/i2c/tw2804.c return write_reg(client, TW2804_REG_GAIN, ctrl->val, 0); val 220 drivers/media/i2c/tw2804.c return write_reg(client, TW2804_REG_CHROMA_GAIN, ctrl->val, 0); val 223 drivers/media/i2c/tw2804.c return write_reg(client, TW2804_REG_BLUE_BALANCE, ctrl->val, 0); val 226 drivers/media/i2c/tw2804.c return write_reg(client, TW2804_REG_RED_BALANCE, ctrl->val, 0); val 230 drivers/media/i2c/tw2804.c ctrl->val, state->channel); val 234 drivers/media/i2c/tw2804.c ctrl->val, state->channel); val 238 drivers/media/i2c/tw2804.c ctrl->val, state->channel); val 242 drivers/media/i2c/tw2804.c ctrl->val, state->channel); val 146 drivers/media/i2c/tw9903.c write_reg(sd, 0x10, ctrl->val); val 149 drivers/media/i2c/tw9903.c write_reg(sd, 0x11, ctrl->val); val 152 drivers/media/i2c/tw9903.c write_reg(sd, 0x15, ctrl->val); val 116 drivers/media/i2c/tw9906.c write_reg(sd, 0x10, ctrl->val); val 119 drivers/media/i2c/tw9906.c write_reg(sd, 0x11, ctrl->val); val 122 drivers/media/i2c/tw9906.c write_reg(sd, 0x15, ctrl->val); val 32 drivers/media/i2c/tw9910.c #define GET_ID(val) ((val & 0xF8) >> 3) val 33 drivers/media/i2c/tw9910.c #define GET_REV(val) (val & 0x07) val 341 drivers/media/i2c/tw9910.c s32 val = i2c_smbus_read_byte_data(client, command); val 343 drivers/media/i2c/tw9910.c if (val < 0) val 344 drivers/media/i2c/tw9910.c return val; val 346 drivers/media/i2c/tw9910.c val &= ~mask; val 347 drivers/media/i2c/tw9910.c val |= set & mask; val 349 drivers/media/i2c/tw9910.c return i2c_smbus_write_byte_data(client, command, val); val 465 drivers/media/i2c/tw9910.c u8 val; val 471 drivers/media/i2c/tw9910.c val = OEN_TRI_SEL_ALL_OFF_r0; val 474 drivers/media/i2c/tw9910.c val = OEN_TRI_SEL_ALL_OFF_r1; val 481 drivers/media/i2c/tw9910.c val = OEN_TRI_SEL_ALL_ON; val 494 drivers/media/i2c/tw9910.c ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val); val 569 drivers/media/i2c/tw9910.c reg->val = (__u64)ret; val 580 drivers/media/i2c/tw9910.c reg->val > 0xff) val 583 drivers/media/i2c/tw9910.c return i2c_smbus_write_byte_data(client, reg->reg, reg->val); val 654 drivers/media/i2c/tw9910.c u8 val; val 665 drivers/media/i2c/tw9910.c val = 0x00; val 667 drivers/media/i2c/tw9910.c val = LEN; val 669 drivers/media/i2c/tw9910.c ret = tw9910_mask_set(client, OPFORM, LEN, val); val 676 drivers/media/i2c/tw9910.c val = RTSEL_VLOSS; break; val 678 drivers/media/i2c/tw9910.c val = RTSEL_HLOCK; break; val 680 drivers/media/i2c/tw9910.c val = RTSEL_SLOCK; break; val 682 drivers/media/i2c/tw9910.c val = RTSEL_VLOCK; break; val 684 drivers/media/i2c/tw9910.c val = RTSEL_MONO; break; val 686 drivers/media/i2c/tw9910.c val = RTSEL_DET50; break; val 688 drivers/media/i2c/tw9910.c val = RTSEL_FIELD; break; val 690 drivers/media/i2c/tw9910.c val = RTSEL_RTCO; break; val 692 drivers/media/i2c/tw9910.c val = 0; val 695 drivers/media/i2c/tw9910.c ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val); val 85 drivers/media/i2c/upd64031a.c static void upd64031a_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 91 drivers/media/i2c/upd64031a.c buf[1] = val; val 92 drivers/media/i2c/upd64031a.c v4l2_dbg(1, debug, sd, "write reg: %02X val: %02X\n", reg, val); val 94 drivers/media/i2c/upd64031a.c v4l2_err(sd, "I/O error write 0x%02x/0x%02x\n", reg, val); val 146 drivers/media/i2c/upd64031a.c reg->val = upd64031a_read(sd, reg->reg & 0xff); val 153 drivers/media/i2c/upd64031a.c upd64031a_write(sd, reg->reg & 0xff, reg->val & 0xff); val 61 drivers/media/i2c/upd64083.c static void upd64083_write(struct v4l2_subdev *sd, u8 reg, u8 val) val 67 drivers/media/i2c/upd64083.c buf[1] = val; val 68 drivers/media/i2c/upd64083.c v4l2_dbg(1, debug, sd, "write reg: %02x val: %02x\n", reg, val); val 70 drivers/media/i2c/upd64083.c v4l2_err(sd, "I/O error write 0x%02x/0x%02x\n", reg, val); val 110 drivers/media/i2c/upd64083.c reg->val = upd64083_read(sd, reg->reg & 0xff); val 117 drivers/media/i2c/upd64083.c upd64083_write(sd, reg->reg & 0xff, reg->val & 0xff); val 122 drivers/media/i2c/video-i2c.c static int mlx90640_nvram_read(void *priv, unsigned int offset, void *val, val 127 drivers/media/i2c/video-i2c.c return regmap_bulk_read(data->regmap, 0x2400 + offset, val, bytes); val 178 drivers/media/i2c/video-i2c.c unsigned int val; val 181 drivers/media/i2c/video-i2c.c val = mask; val 183 drivers/media/i2c/video-i2c.c val = 0; val 185 drivers/media/i2c/video-i2c.c return regmap_update_bits(data->regmap, AMG88XX_REG_FPSC, mask, val); val 283 drivers/media/i2c/video-i2c.c u32 attr, int channel, long *val) val 311 drivers/media/i2c/video-i2c.c *val = (tmp * 625) / 10; val 265 drivers/media/i2c/vpx3220.c static int vpx3220_init(struct v4l2_subdev *sd, u32 val) val 416 drivers/media/i2c/vpx3220.c vpx3220_write(sd, 0xe6, ctrl->val); val 420 drivers/media/i2c/vpx3220.c vpx3220_write(sd, 0xe7, ctrl->val + 192); val 423 drivers/media/i2c/vpx3220.c vpx3220_fp_write(sd, 0xa0, ctrl->val); val 426 drivers/media/i2c/vpx3220.c vpx3220_fp_write(sd, 0x1c, ctrl->val); val 530 drivers/media/i2c/vs6624.c vs6624_write(sd, VS6624_CONTRAST0, ctrl->val); val 533 drivers/media/i2c/vs6624.c vs6624_write(sd, VS6624_SATURATION0, ctrl->val); val 536 drivers/media/i2c/vs6624.c vs6624_write(sd, VS6624_HMIRROR0, ctrl->val); val 539 drivers/media/i2c/vs6624.c vs6624_write(sd, VS6624_VFLIP0, ctrl->val); val 700 drivers/media/i2c/vs6624.c reg->val = vs6624_read(sd, reg->reg & 0xffff); val 707 drivers/media/i2c/vs6624.c vs6624_write(sd, reg->reg & 0xffff, reg->val & 0xff); val 64 drivers/media/i2c/wm8739.c static int wm8739_write(struct v4l2_subdev *sd, int reg, u16 val) val 74 drivers/media/i2c/wm8739.c v4l2_dbg(1, debug, sd, "write: %02x %02x\n", reg, val); val 78 drivers/media/i2c/wm8739.c (reg << 1) | (val >> 8), val & 0xff) == 0) val 80 drivers/media/i2c/wm8739.c v4l2_err(sd, "I2C: cannot write %03x to register R%d\n", val, reg); val 102 drivers/media/i2c/wm8739.c work_l = (min(65536 - state->balance->val, 32768) * state->volume->val) / 32768; val 103 drivers/media/i2c/wm8739.c work_r = (min(state->balance->val, 32768) * state->volume->val) / 32768; val 109 drivers/media/i2c/wm8739.c mute = state->mute->val ? 0x80 : 0; val 63 drivers/media/i2c/wm8775.c static int wm8775_write(struct v4l2_subdev *sd, int reg, u16 val) val 75 drivers/media/i2c/wm8775.c (reg << 1) | (val >> 8), val & 0xff) == 0) val 77 drivers/media/i2c/wm8775.c v4l2_err(sd, "I2C: cannot write %03x to register R%d\n", val, reg); val 85 drivers/media/i2c/wm8775.c int muted = 0 != state->mute->val; val 86 drivers/media/i2c/wm8775.c u16 volume = (u16)state->vol->val; val 87 drivers/media/i2c/wm8775.c u16 balance = (u16)state->bal->val; val 139 drivers/media/i2c/wm8775.c wm8775_write(sd, R17, (ctrl->val ? ALC_EN : 0) | ALC_HOLD); val 263 drivers/media/i2c/wm8775.c wm8775_write(sd, R17, (state->loud->val ? ALC_EN : 0) | ALC_HOLD); val 88 drivers/media/pci/bt8xx/bttv-audio-hook.c unsigned int val, con; val 93 drivers/media/pci/bt8xx/bttv-audio-hook.c val = gpio_read(); val 106 drivers/media/pci/bt8xx/bttv-audio-hook.c if (con != (val & 0x300)) { val 112 drivers/media/pci/bt8xx/bttv-audio-hook.c switch (val & 0x70) { val 159 drivers/media/pci/bt8xx/bttv-audio-hook.c int val; val 174 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x02; val 177 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x01; val 182 drivers/media/pci/bt8xx/bttv-audio-hook.c gpio_bits(0x03, val); val 190 drivers/media/pci/bt8xx/bttv-audio-hook.c int val = 0; val 205 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x01; val 208 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x02; val 211 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0; val 214 drivers/media/pci/bt8xx/bttv-audio-hook.c btaor(val, ~0x03, BT848_GPIO_DATA); val 223 drivers/media/pci/bt8xx/bttv-audio-hook.c int val = 0; val 243 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x0080; val 246 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x0880; val 249 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0; val 253 drivers/media/pci/bt8xx/bttv-audio-hook.c gpio_bits(0x0880, val); val 294 drivers/media/pci/bt8xx/bttv-audio-hook.c unsigned long val; val 311 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x420000; val 314 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x410000; val 317 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x020000; val 323 drivers/media/pci/bt8xx/bttv-audio-hook.c gpio_bits(0x430000, val); val 338 drivers/media/pci/bt8xx/bttv-audio-hook.c unsigned int val = 0; val 356 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x01; val 361 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x02; val 367 drivers/media/pci/bt8xx/bttv-audio-hook.c gpio_bits(0x03, val); val 379 drivers/media/pci/bt8xx/bttv-audio-hook.c unsigned int val; val 397 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x0000; val 402 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x1080; /*-dk-???: 0x0880, 0x0080, 0x1800 ... */ val 407 drivers/media/pci/bt8xx/bttv-audio-hook.c gpio_bits(0x1800, val); val 418 drivers/media/pci/bt8xx/bttv-audio-hook.c unsigned long val; val 433 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x040000; val 436 drivers/media/pci/bt8xx/bttv-audio-hook.c val = 0x100000; val 442 drivers/media/pci/bt8xx/bttv-audio-hook.c gpio_bits(0x140000, val); val 3745 drivers/media/pci/bt8xx/bttv-cards.c u16 val = 0; val 3747 drivers/media/pci/bt8xx/bttv-cards.c val |= (pins & TEA575X_DATA) ? (1 << gpio.data) : 0; val 3748 drivers/media/pci/bt8xx/bttv-cards.c val |= (pins & TEA575X_CLK) ? (1 << gpio.clk) : 0; val 3749 drivers/media/pci/bt8xx/bttv-cards.c val |= (pins & TEA575X_WREN) ? (1 << gpio.wren) : 0; val 3751 drivers/media/pci/bt8xx/bttv-cards.c gpio_bits((1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren), val); val 3767 drivers/media/pci/bt8xx/bttv-cards.c u16 val; val 3774 drivers/media/pci/bt8xx/bttv-cards.c val = gpio_read(); val 3781 drivers/media/pci/bt8xx/bttv-cards.c if (val & (1 << gpio.data)) val 3783 drivers/media/pci/bt8xx/bttv-cards.c if (val & (1 << gpio.most)) val 4143 drivers/media/pci/bt8xx/bttv-cards.c u32 val; val 4179 drivers/media/pci/bt8xx/bttv-cards.c val = btread(BT848_GPIO_DMA_CTL); val 4180 drivers/media/pci/bt8xx/bttv-cards.c val |= BT848_GPIO_DMA_CTL_GPCLKMODE; val 4181 drivers/media/pci/bt8xx/bttv-cards.c btwrite(val, BT848_GPIO_DMA_CTL); val 1255 drivers/media/pci/bt8xx/bttv-driver.c int val; val 1259 drivers/media/pci/bt8xx/bttv-driver.c bt848_bright(btv, c->val); val 1262 drivers/media/pci/bt8xx/bttv-driver.c bt848_hue(btv, c->val); val 1265 drivers/media/pci/bt8xx/bttv-driver.c bt848_contrast(btv, c->val); val 1268 drivers/media/pci/bt8xx/bttv-driver.c bt848_sat(btv, c->val); val 1271 drivers/media/pci/bt8xx/bttv-driver.c if (c->val) { val 1280 drivers/media/pci/bt8xx/bttv-driver.c audio_mute(btv, c->val); val 1281 drivers/media/pci/bt8xx/bttv-driver.c btv->mute = c->val; val 1284 drivers/media/pci/bt8xx/bttv-driver.c btv->volume_gpio(btv, c->val); val 1288 drivers/media/pci/bt8xx/bttv-driver.c val = c->val ? BT848_SCLOOP_CAGC : 0; val 1289 drivers/media/pci/bt8xx/bttv-driver.c btwrite(val, BT848_E_SCLOOP); val 1290 drivers/media/pci/bt8xx/bttv-driver.c btwrite(val, BT848_O_SCLOOP); val 1293 drivers/media/pci/bt8xx/bttv-driver.c btv->opt_combfilter = c->val; val 1296 drivers/media/pci/bt8xx/bttv-driver.c if (c->val) { val 1305 drivers/media/pci/bt8xx/bttv-driver.c btv->opt_automute = c->val; val 1309 drivers/media/pci/bt8xx/bttv-driver.c (c->val ? BT848_ADC_CRUSH : 0), val 1313 drivers/media/pci/bt8xx/bttv-driver.c btv->opt_vcr_hack = c->val; val 1316 drivers/media/pci/bt8xx/bttv-driver.c btwrite(c->val, BT848_WC_UP); val 1319 drivers/media/pci/bt8xx/bttv-driver.c btwrite(c->val, BT848_WC_DOWN); val 1322 drivers/media/pci/bt8xx/bttv-driver.c btv->opt_uv_ratio = c->val; val 1326 drivers/media/pci/bt8xx/bttv-driver.c btaor((c->val << 7), ~BT848_OFORM_RANGE, BT848_OFORM); val 1329 drivers/media/pci/bt8xx/bttv-driver.c btaor((c->val << 5), ~BT848_OFORM_CORE32, BT848_OFORM); val 1875 drivers/media/pci/bt8xx/bttv-driver.c reg->val = btread(reg->reg); val 1888 drivers/media/pci/bt8xx/bttv-driver.c btwrite(reg->val, reg->reg & 0xfff); val 519 drivers/media/pci/bt8xx/dst.c u8 val = 0; val 523 drivers/media/pci/bt8xx/dst.c val += buf[i]; val 525 drivers/media/pci/bt8xx/dst.c return ((~val) + 1); val 83 drivers/media/pci/cobalt/cobalt-alsa-pcm.c u32 val = src[offset + 1] + (src[offset + 2] << 8) + val 88 drivers/media/pci/cobalt/cobalt-alsa-pcm.c *dst++ = val & 0xff; val 90 drivers/media/pci/cobalt/cobalt-alsa-pcm.c *dst++ = (val >> 8) & 0xff; val 91 drivers/media/pci/cobalt/cobalt-alsa-pcm.c *dst++ = (val >> 16) & 0xff; val 20 drivers/media/pci/cobalt/cobalt-cpld.c static void cpld_write(struct cobalt *cobalt, u32 offset, u16 val) val 22 drivers/media/pci/cobalt/cobalt-cpld.c return cobalt_bus_write32(cobalt->bar1, ADRS(offset), val); val 295 drivers/media/pci/cobalt/cobalt-driver.h static inline void cobalt_write_bar0(struct cobalt *cobalt, u32 reg, u32 val) val 297 drivers/media/pci/cobalt/cobalt-driver.h iowrite32(val, cobalt->bar0 + reg); val 305 drivers/media/pci/cobalt/cobalt-driver.h static inline void cobalt_write_bar1(struct cobalt *cobalt, u32 reg, u32 val) val 307 drivers/media/pci/cobalt/cobalt-driver.h iowrite32(val, cobalt->bar1 + reg); val 321 drivers/media/pci/cobalt/cobalt-driver.h int bit, int val) val 326 drivers/media/pci/cobalt/cobalt-driver.h (ctrl & ~(1UL << bit)) | (val << bit)); val 450 drivers/media/pci/cobalt/cobalt-v4l2.c iowrite32(regs->val, adrs); val 452 drivers/media/pci/cobalt/cobalt-v4l2.c regs->val = ioread32(adrs); val 435 drivers/media/pci/cx18/cx18-av-audio.c set_volume(cx, ctrl->val); val 438 drivers/media/pci/cx18/cx18-av-audio.c set_bass(cx, ctrl->val); val 441 drivers/media/pci/cx18/cx18-av-audio.c set_treble(cx, ctrl->val); val 444 drivers/media/pci/cx18/cx18-av-audio.c set_balance(cx, ctrl->val); val 447 drivers/media/pci/cx18/cx18-av-audio.c set_mute(cx, ctrl->val); val 251 drivers/media/pci/cx18/cx18-av-core.c state->volume->cur.val = state->volume->default_value = default_volume; val 255 drivers/media/pci/cx18/cx18-av-core.c static int cx18_av_reset(struct v4l2_subdev *sd, u32 val) val 764 drivers/media/pci/cx18/cx18-av-core.c int val = 0; val 780 drivers/media/pci/cx18/cx18-av-core.c val |= V4L2_TUNER_SUB_STEREO; val 782 drivers/media/pci/cx18/cx18-av-core.c val |= V4L2_TUNER_SUB_MONO; val 785 drivers/media/pci/cx18/cx18-av-core.c val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; val 788 drivers/media/pci/cx18/cx18-av-core.c val |= V4L2_TUNER_SUB_SAP; val 790 drivers/media/pci/cx18/cx18-av-core.c vt->rxsubchans = val; val 910 drivers/media/pci/cx18/cx18-av-core.c cx18_av_write(cx, 0x414, ctrl->val - 128); val 914 drivers/media/pci/cx18/cx18-av-core.c cx18_av_write(cx, 0x415, ctrl->val << 1); val 918 drivers/media/pci/cx18/cx18-av-core.c cx18_av_write(cx, 0x420, ctrl->val << 1); val 919 drivers/media/pci/cx18/cx18-av-core.c cx18_av_write(cx, 0x421, ctrl->val << 1); val 923 drivers/media/pci/cx18/cx18-av-core.c cx18_av_write(cx, 0x422, ctrl->val); val 1231 drivers/media/pci/cx18/cx18-av-core.c reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc); val 1242 drivers/media/pci/cx18/cx18-av-core.c cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val); val 22 drivers/media/pci/cx18/cx18-controls.c int type = cxhdl->stream_type->val; val 75 drivers/media/pci/cx18/cx18-controls.c static int cx18_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val) val 78 drivers/media/pci/cx18/cx18-controls.c int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1; val 104 drivers/media/pci/cx18/cx18-controls.c static int cx18_s_audio_mode(struct cx2341x_handler *cxhdl, u32 val) val 108 drivers/media/pci/cx18/cx18-controls.c cx->dualwatch_stereo_mode = val; val 745 drivers/media/pci/cx18/cx18-driver.c cx->temporal_strength = cx->cxhdl.video_temporal_filter->cur.val; val 746 drivers/media/pci/cx18/cx18-driver.c cx->spatial_strength = cx->cxhdl.video_spatial_filter->cur.val; val 747 drivers/media/pci/cx18/cx18-driver.c cx->filter_mode = cx->cxhdl.video_spatial_filter_mode->cur.val | val 748 drivers/media/pci/cx18/cx18-driver.c (cx->cxhdl.video_temporal_filter_mode->cur.val << 1) | val 749 drivers/media/pci/cx18/cx18-driver.c (cx->cxhdl.video_median_filter_type->cur.val << 2); val 204 drivers/media/pci/cx18/cx18-gpio.c static int resetctrl_reset(struct v4l2_subdev *sd, u32 val) val 210 drivers/media/pci/cx18/cx18-gpio.c switch (val) { val 13 drivers/media/pci/cx18/cx18-io.c void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) val 16 drivers/media/pci/cx18/cx18-io.c u16 val2 = val | (val << 8); val 21 drivers/media/pci/cx18/cx18-io.c cx18_writeb(cx, (u8) val, dst); val 41 drivers/media/pci/cx18/cx18-io.c cx18_writeb(cx, (u8) val, dst); val 44 drivers/media/pci/cx18/cx18-io.c void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) val 46 drivers/media/pci/cx18/cx18-io.c cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val); val 47 drivers/media/pci/cx18/cx18-io.c cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val; val 51 drivers/media/pci/cx18/cx18-io.c void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) val 53 drivers/media/pci/cx18/cx18-io.c cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val; val 57 drivers/media/pci/cx18/cx18-io.c void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) val 59 drivers/media/pci/cx18/cx18-io.c cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val); val 60 drivers/media/pci/cx18/cx18-io.c cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val; val 64 drivers/media/pci/cx18/cx18-io.c void cx18_sw2_irq_disable(struct cx18 *cx, u32 val) val 66 drivers/media/pci/cx18/cx18-io.c cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val; val 70 drivers/media/pci/cx18/cx18-io.c void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val) val 74 drivers/media/pci/cx18/cx18-io.c cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU); val 79 drivers/media/pci/cx18/cx18-io.c u32 val; val 80 drivers/media/pci/cx18/cx18-io.c val = cx18_read_reg(cx, 0xD000F8); val 81 drivers/media/pci/cx18/cx18-io.c val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00); val 82 drivers/media/pci/cx18/cx18-io.c cx18_write_reg(cx, val, 0xD000F8); val 30 drivers/media/pci/cx18/cx18-io.h void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) val 32 drivers/media/pci/cx18/cx18-io.h __raw_writel(val, addr); val 35 drivers/media/pci/cx18/cx18-io.h static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) val 39 drivers/media/pci/cx18/cx18-io.h cx18_raw_writel_noretry(cx, val, addr); val 40 drivers/media/pci/cx18/cx18-io.h if (val == cx18_raw_readl(cx, addr)) val 52 drivers/media/pci/cx18/cx18-io.h void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) val 54 drivers/media/pci/cx18/cx18-io.h writel(val, addr); val 57 drivers/media/pci/cx18/cx18-io.h static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) val 61 drivers/media/pci/cx18/cx18-io.h cx18_writel_noretry(cx, val, addr); val 62 drivers/media/pci/cx18/cx18-io.h if (val == cx18_readl(cx, addr)) val 68 drivers/media/pci/cx18/cx18-io.h void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, val 75 drivers/media/pci/cx18/cx18-io.h cx18_writel_noretry(cx, val, addr); val 90 drivers/media/pci/cx18/cx18-io.h void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) val 92 drivers/media/pci/cx18/cx18-io.h writew(val, addr); val 95 drivers/media/pci/cx18/cx18-io.h static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) val 99 drivers/media/pci/cx18/cx18-io.h cx18_writew_noretry(cx, val, addr); val 100 drivers/media/pci/cx18/cx18-io.h if (val == cx18_readw(cx, addr)) val 111 drivers/media/pci/cx18/cx18-io.h void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) val 113 drivers/media/pci/cx18/cx18-io.h writeb(val, addr); val 116 drivers/media/pci/cx18/cx18-io.h static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) val 120 drivers/media/pci/cx18/cx18-io.h cx18_writeb_noretry(cx, val, addr); val 121 drivers/media/pci/cx18/cx18-io.h if (val == cx18_readb(cx, addr)) val 133 drivers/media/pci/cx18/cx18-io.h void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count); val 137 drivers/media/pci/cx18/cx18-io.h static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) val 139 drivers/media/pci/cx18/cx18-io.h cx18_writel_noretry(cx, val, cx->reg_mem + reg); val 142 drivers/media/pci/cx18/cx18-io.h static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) val 144 drivers/media/pci/cx18/cx18-io.h cx18_writel(cx, val, cx->reg_mem + reg); val 147 drivers/media/pci/cx18/cx18-io.h static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, val 150 drivers/media/pci/cx18/cx18-io.h cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask); val 160 drivers/media/pci/cx18/cx18-io.h static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr) val 162 drivers/media/pci/cx18/cx18-io.h cx18_writel(cx, val, cx->enc_mem + addr); val 170 drivers/media/pci/cx18/cx18-io.h void cx18_sw1_irq_enable(struct cx18 *cx, u32 val); val 171 drivers/media/pci/cx18/cx18-io.h void cx18_sw1_irq_disable(struct cx18 *cx, u32 val); val 172 drivers/media/pci/cx18/cx18-io.h void cx18_sw2_irq_enable(struct cx18 *cx, u32 val); val 173 drivers/media/pci/cx18/cx18-io.h void cx18_sw2_irq_disable(struct cx18 *cx, u32 val); val 174 drivers/media/pci/cx18/cx18-io.h void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val); val 366 drivers/media/pci/cx18/cx18-ioctl.c reg->val = cx18_read_enc(cx, reg->reg); val 379 drivers/media/pci/cx18/cx18-ioctl.c cx18_write_enc(cx, reg->val, reg->reg); val 1051 drivers/media/pci/cx18/cx18-ioctl.c u32 val = *(u32 *)arg; val 1053 drivers/media/pci/cx18/cx18-ioctl.c if ((val == 0) || (val & 0x01)) val 250 drivers/media/pci/cx23885/altera-ci.c u8 val, u8 read) val 253 drivers/media/pci/cx23885/altera-ci.c return inter->fpga_rw(inter->dev, 0, val, read); val 258 drivers/media/pci/cx23885/altera-ci.c u8 flag, u8 read, int addr, u8 val) val 280 drivers/media/pci/cx23885/altera-ci.c mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read); val 287 drivers/media/pci/cx23885/altera-ci.c (read) ? mem : val); val 27 drivers/media/pci/cx23885/altera-ci.h int (*fpga_rw) (void *dev, int ad_rg, int val, int rw); val 623 drivers/media/pci/cx23885/cx23885-417.c u32 val; val 626 drivers/media/pci/cx23885/cx23885-417.c mc417_register_read(dev, 0x900C, &val); val 627 drivers/media/pci/cx23885/cx23885-417.c val |= (mask & 0x000ffff); val 628 drivers/media/pci/cx23885/cx23885-417.c mc417_register_write(dev, 0x900C, val); val 633 drivers/media/pci/cx23885/cx23885-417.c u32 val; val 636 drivers/media/pci/cx23885/cx23885-417.c mc417_register_read(dev, 0x900C, &val); val 637 drivers/media/pci/cx23885/cx23885-417.c val &= ~(mask & 0x0000ffff); val 638 drivers/media/pci/cx23885/cx23885-417.c mc417_register_write(dev, 0x900C, val); val 643 drivers/media/pci/cx23885/cx23885-417.c u32 val; val 646 drivers/media/pci/cx23885/cx23885-417.c mc417_register_read(dev, 0x9020, &val); val 648 drivers/media/pci/cx23885/cx23885-417.c val |= (mask & 0x0000ffff); val 650 drivers/media/pci/cx23885/cx23885-417.c val &= ~(mask & 0x0000ffff); val 652 drivers/media/pci/cx23885/cx23885-417.c mc417_register_write(dev, 0x9020, val); val 46 drivers/media/pci/cx23885/cx23885-ioctl.c reg->val = value; val 64 drivers/media/pci/cx23885/cx23885-ioctl.c reg->val = cx_read(reg->reg); val 77 drivers/media/pci/cx23885/cx23885-ioctl.c if (mc417_register_write(dev, (u16) reg->reg, (u32) reg->val)) val 95 drivers/media/pci/cx23885/cx23885-ioctl.c cx_write(reg->reg, reg->val); val 205 drivers/media/pci/cx23885/cx23885-video.c u8 val; val 209 drivers/media/pci/cx23885/cx23885-video.c val = cx23885_flatiron_read(dev, CH_PWR_CTRL1) & ~FLD_CH_SEL; val 211 drivers/media/pci/cx23885/cx23885-video.c val = cx23885_flatiron_read(dev, CH_PWR_CTRL1) | FLD_CH_SEL; val 215 drivers/media/pci/cx23885/cx23885-video.c val |= 0x20; /* Enable clock to delta-sigma and dec filter */ val 217 drivers/media/pci/cx23885/cx23885-video.c cx23885_flatiron_write(dev, CH_PWR_CTRL1, val); val 1081 drivers/media/pci/cx23885/cx23888-ir.c reg->val = cx23888_ir_read4(state->dev, addr); val 1095 drivers/media/pci/cx23885/cx23888-ir.c cx23888_ir_write4(state->dev, addr, reg->val); val 15 drivers/media/pci/cx23885/netup-init.c static void i2c_av_write(struct i2c_adapter *i2c, u16 reg, u8 val) val 28 drivers/media/pci/cx23885/netup-init.c buf[2] = val; val 36 drivers/media/pci/cx23885/netup-init.c static void i2c_av_write4(struct i2c_adapter *i2c, u16 reg, u32 val) val 49 drivers/media/pci/cx23885/netup-init.c buf[2] = val & 0xff; val 50 drivers/media/pci/cx23885/netup-init.c buf[3] = (val >> 8) & 0xff; val 51 drivers/media/pci/cx23885/netup-init.c buf[4] = (val >> 16) & 0xff; val 52 drivers/media/pci/cx23885/netup-init.c buf[5] = val >> 24; val 555 drivers/media/pci/cx25821/cx25821-medusa-video.c u32 val = 0, tmp = 0; val 564 drivers/media/pci/cx25821/cx25821-medusa-video.c val = cx25821_i2c_read(&dev->i2c_bus[0], val 566 drivers/media/pci/cx25821/cx25821-medusa-video.c val &= 0xFFFFFF00; val 568 drivers/media/pci/cx25821/cx25821-medusa-video.c VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value); val 576 drivers/media/pci/cx25821/cx25821-medusa-video.c u32 val = 0, tmp = 0; val 584 drivers/media/pci/cx25821/cx25821-medusa-video.c val = cx25821_i2c_read(&dev->i2c_bus[0], val 586 drivers/media/pci/cx25821/cx25821-medusa-video.c val &= 0xFFFFFF00; val 588 drivers/media/pci/cx25821/cx25821-medusa-video.c VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value); val 597 drivers/media/pci/cx25821/cx25821-medusa-video.c u32 val = 0, tmp = 0; val 607 drivers/media/pci/cx25821/cx25821-medusa-video.c val = cx25821_i2c_read(&dev->i2c_bus[0], val 609 drivers/media/pci/cx25821/cx25821-medusa-video.c val &= 0xFFFFFF00; val 612 drivers/media/pci/cx25821/cx25821-medusa-video.c VDEC_A_HUE_CTRL + (0x200 * decoder), val | value); val 621 drivers/media/pci/cx25821/cx25821-medusa-video.c u32 val = 0, tmp = 0; val 631 drivers/media/pci/cx25821/cx25821-medusa-video.c val = cx25821_i2c_read(&dev->i2c_bus[0], val 633 drivers/media/pci/cx25821/cx25821-medusa-video.c val &= 0xFFFFFF00; val 635 drivers/media/pci/cx25821/cx25821-medusa-video.c VDEC_A_USAT_CTRL + (0x200 * decoder), val | value); val 637 drivers/media/pci/cx25821/cx25821-medusa-video.c val = cx25821_i2c_read(&dev->i2c_bus[0], val 639 drivers/media/pci/cx25821/cx25821-medusa-video.c val &= 0xFFFFFF00; val 641 drivers/media/pci/cx25821/cx25821-medusa-video.c VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value); val 493 drivers/media/pci/cx25821/cx25821-video.c medusa_set_brightness(dev, ctrl->val, chan->id); val 496 drivers/media/pci/cx25821/cx25821-video.c medusa_set_hue(dev, ctrl->val, chan->id); val 499 drivers/media/pci/cx25821/cx25821-video.c medusa_set_contrast(dev, ctrl->val, chan->id); val 502 drivers/media/pci/cx25821/cx25821-video.c medusa_set_saturation(dev, ctrl->val, chan->id); val 775 drivers/media/pci/cx88/cx88-alsa.c s32 val; val 777 drivers/media/pci/cx88/cx88-alsa.c val = wm8775_g_ctrl(core, V4L2_CID_AUDIO_LOUDNESS); val 778 drivers/media/pci/cx88/cx88-alsa.c value->value.integer.value[0] = val ? 1 : 0; val 258 drivers/media/pci/cx88/cx88-blackbird.c u32 val; val 269 drivers/media/pci/cx88/cx88-blackbird.c val = (unsigned char)cx_read(P1_MDATA3) << 24; val 271 drivers/media/pci/cx88/cx88-blackbird.c val |= (unsigned char)cx_read(P1_MDATA2) << 16; val 273 drivers/media/pci/cx88/cx88-blackbird.c val |= (unsigned char)cx_read(P1_MDATA1) << 8; val 275 drivers/media/pci/cx88/cx88-blackbird.c val |= (unsigned char)cx_read(P1_MDATA0); val 277 drivers/media/pci/cx88/cx88-blackbird.c *value = val; val 299 drivers/media/pci/cx88/cx88-blackbird.c u32 val; val 307 drivers/media/pci/cx88/cx88-blackbird.c val = (unsigned char)cx_read(P1_RDATA0); val 308 drivers/media/pci/cx88/cx88-blackbird.c val |= (unsigned char)cx_read(P1_RDATA1) << 8; val 309 drivers/media/pci/cx88/cx88-blackbird.c val |= (unsigned char)cx_read(P1_RDATA2) << 16; val 310 drivers/media/pci/cx88/cx88-blackbird.c val |= (unsigned char)cx_read(P1_RDATA3) << 24; val 312 drivers/media/pci/cx88/cx88-blackbird.c *value = val; val 89 drivers/media/pci/cx88/cx88-tvaudio.c u32 val; val 104 drivers/media/pci/cx88/cx88-tvaudio.c cx_writeb(l[i].reg, l[i].val); val 107 drivers/media/pci/cx88/cx88-tvaudio.c cx_write(l[i].reg, l[i].val); val 619 drivers/media/pci/cx88/cx88-video.c value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; val 632 drivers/media/pci/cx88/cx88-video.c value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7)); val 637 drivers/media/pci/cx88/cx88-video.c value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; val 640 drivers/media/pci/cx88/cx88-video.c value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; val 645 drivers/media/pci/cx88/cx88-video.c ctrl->id, ctrl->name, ctrl->val, cc->reg, value, val 665 drivers/media/pci/cx88/cx88-video.c wm8775_s_ctrl(core, ctrl->id, ctrl->val); val 668 drivers/media/pci/cx88/cx88-video.c wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ? val 669 drivers/media/pci/cx88/cx88-video.c (0x90 + ctrl->val) << 8 : 0); val 672 drivers/media/pci/cx88/cx88-video.c wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9); val 682 drivers/media/pci/cx88/cx88-video.c value = (ctrl->val < 0x40) ? val 683 drivers/media/pci/cx88/cx88-video.c (0x7f - ctrl->val) : (ctrl->val - 0x40); val 686 drivers/media/pci/cx88/cx88-video.c value = 0x3f - (ctrl->val & 0x3f); val 689 drivers/media/pci/cx88/cx88-video.c value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; val 694 drivers/media/pci/cx88/cx88-video.c ctrl->id, ctrl->name, ctrl->val, cc->reg, value, val 1004 drivers/media/pci/cx88/cx88-video.c reg->val = cx_read(reg->reg & 0xfffffc); val 1015 drivers/media/pci/cx88/cx88-video.c cx_write(reg->reg & 0xfffffc, reg->val); val 432 drivers/media/pci/cx88/cx88.h #define wm8775_s_ctrl(core, id, val) \ val 439 drivers/media/pci/cx88/cx88.h v4l2_ctrl_s_ctrl(ctrl_, val); \ val 449 drivers/media/pci/cx88/cx88.h s32 val = 0; \ val 453 drivers/media/pci/cx88/cx88.h val = v4l2_ctrl_g_ctrl(ctrl_); \ val 457 drivers/media/pci/cx88/cx88.h val; \ val 49 drivers/media/pci/ddbridge/ddbridge-ci.c u32 val, off = (address >> 1) & (CI_BUFFER_SIZE - 1); val 56 drivers/media/pci/ddbridge/ddbridge-ci.c val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off); val 57 drivers/media/pci/ddbridge/ddbridge-ci.c return val; val 132 drivers/media/pci/ddbridge/ddbridge-ci.c u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); val 134 drivers/media/pci/ddbridge/ddbridge-ci.c ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE, val 142 drivers/media/pci/ddbridge/ddbridge-ci.c u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); val 145 drivers/media/pci/ddbridge/ddbridge-ci.c if (val & CI_CAM_DETECT) val 147 drivers/media/pci/ddbridge/ddbridge-ci.c if (val & CI_CAM_READY) val 196 drivers/media/pci/ddbridge/ddbridge-ci.c u8 val; val 198 drivers/media/pci/ddbridge/ddbridge-ci.c res = i2c_read_reg16(i2c, adr, 0x8000 | address, &val); val 199 drivers/media/pci/ddbridge/ddbridge-ci.c return res ? res : val; val 218 drivers/media/pci/ddbridge/ddbridge-ci.c u8 val; val 221 drivers/media/pci/ddbridge/ddbridge-ci.c res = i2c_read_reg(i2c, adr, 0x20 | (address & 3), &val); val 222 drivers/media/pci/ddbridge/ddbridge-ci.c return res ? res : val; val 273 drivers/media/pci/ddbridge/ddbridge-ci.c u8 val = 0; val 276 drivers/media/pci/ddbridge/ddbridge-ci.c i2c_read_reg(i2c, adr, 0x01, &val); val 278 drivers/media/pci/ddbridge/ddbridge-ci.c if (val & 2) val 280 drivers/media/pci/ddbridge/ddbridge-ci.c if (val & 1) val 1192 drivers/media/pci/ddbridge/ddbridge-core.c u8 val; val 1194 drivers/media/pci/ddbridge/ddbridge-core.c return i2c_read_reg(i2c, adr, 0, &val) ? 0 : 1; val 1639 drivers/media/pci/ddbridge/ddbridge-core.c u8 val; val 1640 drivers/media/pci/ddbridge/ddbridge-core.c int ret = i2c_read_reg(&port->i2c->adap, 0x20, 0, &val); val 1643 drivers/media/pci/ddbridge/ddbridge-core.c dev_info(dev, "[0x20]=0x%02x\n", val); val 1649 drivers/media/pci/ddbridge/ddbridge-core.c u8 val; val 1655 drivers/media/pci/ddbridge/ddbridge-core.c val = i2c_transfer(&port->i2c->adap, msgs, 2); val 1656 drivers/media/pci/ddbridge/ddbridge-core.c if (val != 2) val 1687 drivers/media/pci/ddbridge/ddbridge-core.c u8 val; val 1689 drivers/media/pci/ddbridge/ddbridge-core.c if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) val 1703 drivers/media/pci/ddbridge/ddbridge-core.c u8 val; val 1705 drivers/media/pci/ddbridge/ddbridge-core.c if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) val 1707 drivers/media/pci/ddbridge/ddbridge-core.c if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) val 1714 drivers/media/pci/ddbridge/ddbridge-core.c u8 val; val 1716 drivers/media/pci/ddbridge/ddbridge-core.c if (i2c_read_reg16(&port->i2c->adap, 0x1e, 0xf000, &val) < 0) val 1718 drivers/media/pci/ddbridge/ddbridge-core.c if (val != 0x60) val 1720 drivers/media/pci/ddbridge/ddbridge-core.c if (i2c_read_reg16(&port->i2c->adap, 0x1f, 0xf000, &val) < 0) val 1722 drivers/media/pci/ddbridge/ddbridge-core.c if (val != 0x60) val 1731 drivers/media/pci/ddbridge/ddbridge-core.c u8 val, data[2]; val 1743 drivers/media/pci/ddbridge/ddbridge-core.c i2c_read_reg(i2c, 0x10, 0x08, &val); val 1744 drivers/media/pci/ddbridge/ddbridge-core.c if (val != 0) { val 1777 drivers/media/pci/ddbridge/ddbridge-core.c u8 val, data[2]; val 1792 drivers/media/pci/ddbridge/ddbridge-core.c i2c_read_reg(i2c, 0x10, 0x08, &val); val 1793 drivers/media/pci/ddbridge/ddbridge-core.c if (val != 0) { val 2772 drivers/media/pci/ddbridge/ddbridge-core.c u32 val; val 2774 drivers/media/pci/ddbridge/ddbridge-core.c val = ddbreadl(dev, GPIO_OUTPUT) & 1; val 2775 drivers/media/pci/ddbridge/ddbridge-core.c return sprintf(buf, "%d\n", val); val 2782 drivers/media/pci/ddbridge/ddbridge-core.c u32 val; val 2784 drivers/media/pci/ddbridge/ddbridge-core.c if (sscanf(buf, "%u\n", &val) != 1) val 2787 drivers/media/pci/ddbridge/ddbridge-core.c ddbwritel(dev, val & 1, GPIO_OUTPUT); val 2857 drivers/media/pci/ddbridge/ddbridge-core.c static void ddb_set_led(struct ddb *dev, int num, int val) val 2866 drivers/media/pci/ddbridge/ddbridge-core.c 0x69, 0xf14c, val ? 2 : 0); val 2872 drivers/media/pci/ddbridge/ddbridge-core.c 0x1f, 0xf00f, val ? 1 : 0); val 2879 drivers/media/pci/ddbridge/ddbridge-core.c v = (v & ~0x10) | (val ? 0x10 : 0); val 2896 drivers/media/pci/ddbridge/ddbridge-core.c u32 val; val 2898 drivers/media/pci/ddbridge/ddbridge-core.c if (sscanf(buf, "%u\n", &val) != 1) val 2900 drivers/media/pci/ddbridge/ddbridge-core.c if (val) val 2904 drivers/media/pci/ddbridge/ddbridge-core.c ddb_set_led(dev, num, val); val 2995 drivers/media/pci/ddbridge/ddbridge-core.c unsigned int val; val 2997 drivers/media/pci/ddbridge/ddbridge-core.c if (sscanf(buf, "%u\n", &val) != 1) val 2999 drivers/media/pci/ddbridge/ddbridge-core.c if (val > 128) val 3001 drivers/media/pci/ddbridge/ddbridge-core.c if (val == 128) val 3002 drivers/media/pci/ddbridge/ddbridge-core.c val = 0xffffffff; val 3003 drivers/media/pci/ddbridge/ddbridge-core.c dev->port[num].gap = val; val 3055 drivers/media/pci/ddbridge/ddbridge-core.c unsigned int val; val 3057 drivers/media/pci/ddbridge/ddbridge-core.c if (sscanf(buf, "%u\n", &val) != 1) val 3059 drivers/media/pci/ddbridge/ddbridge-core.c if (val > 3) val 3061 drivers/media/pci/ddbridge/ddbridge-core.c ddb_lnb_init_fmode(dev, &dev->link[num], val); val 44 drivers/media/pci/ddbridge/ddbridge-i2c.c u32 val; val 48 drivers/media/pci/ddbridge/ddbridge-i2c.c val = ddbreadl(dev, i2c->regs + I2C_COMMAND); val 71 drivers/media/pci/ddbridge/ddbridge-i2c.c val, mon); val 76 drivers/media/pci/ddbridge/ddbridge-i2c.c val &= 0x70000; val 77 drivers/media/pci/ddbridge/ddbridge-i2c.c if (val == 0x20000) val 79 drivers/media/pci/ddbridge/ddbridge-i2c.c if (val) val 53 drivers/media/pci/ddbridge/ddbridge-i2c.h static int __maybe_unused i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) val 56 drivers/media/pci/ddbridge/ddbridge-i2c.h .buf = val, .len = 1 } }; val 62 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u8 reg, u8 *val, u8 len) val 67 drivers/media/pci/ddbridge/ddbridge-i2c.h .buf = val, .len = len } }; val 73 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u16 reg, u8 *val, u8 len) val 79 drivers/media/pci/ddbridge/ddbridge-i2c.h .buf = val, .len = len } }; val 85 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u16 reg, u8 val) val 87 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 msg[3] = { reg >> 8, reg & 0xff, val }; val 93 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u8 reg, u8 val) val 95 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 msg[2] = { reg, val }; val 101 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u16 reg, u8 *val) val 103 drivers/media/pci/ddbridge/ddbridge-i2c.h return i2c_read_regs16(adapter, adr, reg, val, 1); val 107 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u8 reg, u8 *val) val 109 drivers/media/pci/ddbridge/ddbridge-i2c.h return i2c_read_regs(adapter, adr, reg, val, 1); val 33 drivers/media/pci/ddbridge/ddbridge-io.h static inline void ddblwritel(struct ddb_link *link, u32 val, u32 adr) val 35 drivers/media/pci/ddbridge/ddbridge-io.h writel(val, link->dev->regs + adr); val 43 drivers/media/pci/ddbridge/ddbridge-io.h static inline void ddbwritel(struct ddb *dev, u32 val, u32 adr) val 45 drivers/media/pci/ddbridge/ddbridge-io.h writel(val, dev->regs + adr); val 60 drivers/media/pci/ddbridge/ddbridge-io.h u32 val = ddbreadl(dev, adr); val 63 drivers/media/pci/ddbridge/ddbridge-io.h if (val == ~0) { val 68 drivers/media/pci/ddbridge/ddbridge-io.h return val; val 66 drivers/media/pci/ddbridge/ddbridge-mci.c u32 i, val; val 69 drivers/media/pci/ddbridge/ddbridge-mci.c val = ddblreadl(link, MCI_CONTROL); val 70 drivers/media/pci/ddbridge/ddbridge-mci.c if (val & (MCI_CONTROL_RESET | MCI_CONTROL_START_COMMAND)) val 75 drivers/media/pci/ddbridge/ddbridge-mci.c val |= (MCI_CONTROL_START_COMMAND | MCI_CONTROL_ENABLE_DONE_INTERRUPT); val 76 drivers/media/pci/ddbridge/ddbridge-mci.c ddblwritel(link, val, MCI_CONTROL); val 401 drivers/media/pci/dm1105/dm1105.c static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val) val 407 drivers/media/pci/dm1105/dm1105.c dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val); val 51 drivers/media/pci/ivtv/ivtv-controls.c static int ivtv_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val) val 54 drivers/media/pci/ivtv/ivtv-controls.c int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1; val 79 drivers/media/pci/ivtv/ivtv-controls.c static int ivtv_s_audio_mode(struct cx2341x_handler *cxhdl, u32 val) val 83 drivers/media/pci/ivtv/ivtv-controls.c itv->dualwatch_stereo_mode = val; val 142 drivers/media/pci/ivtv/ivtv-controls.c itv->audio_stereo_mode = itv->ctrl_audio_playback->val - 1; val 143 drivers/media/pci/ivtv/ivtv-controls.c itv->audio_bilingual_mode = itv->ctrl_audio_multilingual_playback->val - 1; val 811 drivers/media/pci/ivtv/ivtv-driver.h #define write_sync(val, reg) \ val 812 drivers/media/pci/ivtv/ivtv-driver.h do { writel(val, reg); readl(reg); } while (0) val 815 drivers/media/pci/ivtv/ivtv-driver.h #define write_reg(val, reg) writel(val, itv->reg_mem + (reg)) val 816 drivers/media/pci/ivtv/ivtv-driver.h #define write_reg_sync(val, reg) \ val 817 drivers/media/pci/ivtv/ivtv-driver.h do { write_reg(val, reg); read_reg(reg); } while (0) val 820 drivers/media/pci/ivtv/ivtv-driver.h #define write_enc(val, addr) writel(val, itv->enc_mem + (u32)(addr)) val 821 drivers/media/pci/ivtv/ivtv-driver.h #define write_enc_sync(val, addr) \ val 822 drivers/media/pci/ivtv/ivtv-driver.h do { write_enc(val, addr); read_enc(addr); } while (0) val 825 drivers/media/pci/ivtv/ivtv-driver.h #define write_dec(val, addr) writel(val, itv->dec_mem + (u32)(addr)) val 826 drivers/media/pci/ivtv/ivtv-driver.h #define write_dec_sync(val, addr) \ val 827 drivers/media/pci/ivtv/ivtv-driver.h do { write_dec(val, addr); read_dec(addr); } while (0) val 257 drivers/media/pci/ivtv/ivtv-gpio.c data = ctrl->val ? itv->card->gpio_audio_mute.mute : 0; val 351 drivers/media/pci/ivtv/ivtv-i2c.c static int ivtv_waitscl(struct ivtv *itv, int val) val 357 drivers/media/pci/ivtv/ivtv-i2c.c if (ivtv_getscl(itv) == val) val 364 drivers/media/pci/ivtv/ivtv-i2c.c static int ivtv_waitsda(struct ivtv *itv, int val) val 370 drivers/media/pci/ivtv/ivtv-i2c.c if (ivtv_getsda(itv) == val) val 693 drivers/media/pci/ivtv/ivtv-ioctl.c static int ivtv_itvc(struct ivtv *itv, bool get, u64 reg, u64 *val) val 710 drivers/media/pci/ivtv/ivtv-ioctl.c *val = readl(reg + reg_start); val 712 drivers/media/pci/ivtv/ivtv-ioctl.c writel(*val, reg + reg_start); val 721 drivers/media/pci/ivtv/ivtv-ioctl.c return ivtv_itvc(itv, true, reg->reg, ®->val); val 727 drivers/media/pci/ivtv/ivtv-ioctl.c u64 val = reg->val; val 729 drivers/media/pci/ivtv/ivtv-ioctl.c return ivtv_itvc(itv, false, reg->reg, &val); val 1864 drivers/media/pci/ivtv/ivtv-ioctl.c u32 val = *(u32 *)arg; val 1866 drivers/media/pci/ivtv/ivtv-ioctl.c if ((val == 0 && itv->options.newi2c) || (val & 0x01)) val 1868 drivers/media/pci/ivtv/ivtv-ioctl.c if (val & 0x02) val 1050 drivers/media/pci/meye/meye.c SONY_PIC_COMMAND_SETCAMERABRIGHTNESS, ctrl->val); val 1051 drivers/media/pci/meye/meye.c meye.brightness = ctrl->val << 10; val 1055 drivers/media/pci/meye/meye.c SONY_PIC_COMMAND_SETCAMERAHUE, ctrl->val); val 1056 drivers/media/pci/meye/meye.c meye.hue = ctrl->val << 10; val 1060 drivers/media/pci/meye/meye.c SONY_PIC_COMMAND_SETCAMERACONTRAST, ctrl->val); val 1061 drivers/media/pci/meye/meye.c meye.contrast = ctrl->val << 10; val 1065 drivers/media/pci/meye/meye.c SONY_PIC_COMMAND_SETCAMERACOLOR, ctrl->val); val 1066 drivers/media/pci/meye/meye.c meye.colour = ctrl->val << 10; val 1070 drivers/media/pci/meye/meye.c SONY_PIC_COMMAND_SETCAMERAAGC, ctrl->val); val 1071 drivers/media/pci/meye/meye.c meye.params.agc = ctrl->val; val 1075 drivers/media/pci/meye/meye.c SONY_PIC_COMMAND_SETCAMERASHARPNESS, ctrl->val); val 1076 drivers/media/pci/meye/meye.c meye.params.sharpness = ctrl->val; val 1080 drivers/media/pci/meye/meye.c SONY_PIC_COMMAND_SETCAMERAPICTURE, ctrl->val); val 1081 drivers/media/pci/meye/meye.c meye.params.picture = ctrl->val; val 1084 drivers/media/pci/meye/meye.c meye.params.quality = ctrl->val; val 1087 drivers/media/pci/meye/meye.c meye.params.framerate = ctrl->val; val 141 drivers/media/pci/netup_unidvb/netup_unidvb_ci.c u8 val = *((u8 __force *)state->membase8_config + addr); val 144 drivers/media/pci/netup_unidvb/netup_unidvb_ci.c "%s(): addr=0x%x val=0x%x\n", __func__, addr, val); val 145 drivers/media/pci/netup_unidvb/netup_unidvb_ci.c return val; val 165 drivers/media/pci/netup_unidvb/netup_unidvb_ci.c u8 val = *((u8 __force *)state->membase8_io + addr); val 168 drivers/media/pci/netup_unidvb/netup_unidvb_ci.c "%s(): addr=0x%x val=0x%x\n", __func__, addr, val); val 169 drivers/media/pci/netup_unidvb/netup_unidvb_ci.c return val; val 63 drivers/media/pci/ngene/ngene-cards.c u8 reg, u8 val) val 65 drivers/media/pci/ngene/ngene-cards.c u8 msg[2] = {reg, val}; val 70 drivers/media/pci/ngene/ngene-cards.c static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) val 73 drivers/media/pci/ngene/ngene-cards.c .buf = val, .len = 1 } }; val 78 drivers/media/pci/ngene/ngene-cards.c u16 reg, u8 *val) val 84 drivers/media/pci/ngene/ngene-cards.c .buf = val, .len = 1} }; val 89 drivers/media/pci/ngene/ngene-cards.c u8 adr, u8 reg, u8 *val, u8 len) val 94 drivers/media/pci/ngene/ngene-cards.c .buf = val, .len = len} }; val 99 drivers/media/pci/ngene/ngene-cards.c static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) val 101 drivers/media/pci/ngene/ngene-cards.c return i2c_read_regs(adapter, adr, reg, val, 1); val 438 drivers/media/pci/ngene/ngene-cards.c u8 val; val 439 drivers/media/pci/ngene/ngene-cards.c if (i2c_read_reg16(i2c, 0x68+port/2, 0xf100, &val) < 0) val 446 drivers/media/pci/ngene/ngene-cards.c u8 val; val 448 drivers/media/pci/ngene/ngene-cards.c if (i2c_read(i2c, 0x29+port, &val) < 0) val 455 drivers/media/pci/ngene/ngene-cards.c u8 val; val 457 drivers/media/pci/ngene/ngene-cards.c if (i2c_read_reg16(i2c, 0x1e, 0xf000, &val) < 0) val 459 drivers/media/pci/ngene/ngene-cards.c if (val != 0x60) val 461 drivers/media/pci/ngene/ngene-cards.c if (i2c_read_reg16(i2c, 0x1f, 0xf000, &val) < 0) val 463 drivers/media/pci/ngene/ngene-cards.c if (val != 0x60) val 470 drivers/media/pci/ngene/ngene-cards.c u8 val; val 476 drivers/media/pci/ngene/ngene-cards.c val = i2c_transfer(i2c, msgs, 2); val 477 drivers/media/pci/ngene/ngene-cards.c if (val != 2) val 526 drivers/media/pci/ngene/ngene-cards.c u8 val, data[2]; val 538 drivers/media/pci/ngene/ngene-cards.c i2c_read_reg(i2c, addr, 0x08, &val); val 539 drivers/media/pci/ngene/ngene-cards.c if (val != 0) { val 499 drivers/media/pci/ngene/ngene-core.c u8 val; val 504 drivers/media/pci/ngene/ngene-core.c val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; val 506 drivers/media/pci/ngene/ngene-core.c } while (val); val 130 drivers/media/pci/pluto2/pluto2.c static inline void pluto_writereg(struct pluto *pluto, u32 reg, u32 val) val 132 drivers/media/pci/pluto2/pluto2.c writel(val, &pluto->io_mem[reg]); val 137 drivers/media/pci/pluto2/pluto2.c u32 val = readl(&pluto->io_mem[reg]); val 138 drivers/media/pci/pluto2/pluto2.c val &= ~mask; val 139 drivers/media/pci/pluto2/pluto2.c val |= bits; val 140 drivers/media/pci/pluto2/pluto2.c writel(val, &pluto->io_mem[reg]); val 143 drivers/media/pci/pluto2/pluto2.c static void pluto_write_tscr(struct pluto *pluto, u32 val) val 146 drivers/media/pci/pluto2/pluto2.c val &= ~TSCR_ADEF; val 147 drivers/media/pci/pluto2/pluto2.c val |= TS_DMA_PACKETS / 2; val 149 drivers/media/pci/pluto2/pluto2.c pluto_writereg(pluto, REG_TSCR, val); val 198 drivers/media/pci/pluto2/pluto2.c u32 val = pluto_readreg(pluto, REG_MISC); val 200 drivers/media/pci/pluto2/pluto2.c if (val & MISC_FRST) { val 201 drivers/media/pci/pluto2/pluto2.c val &= ~MISC_FRST; val 202 drivers/media/pci/pluto2/pluto2.c pluto_writereg(pluto, REG_MISC, val); val 205 drivers/media/pci/pluto2/pluto2.c val |= MISC_FRST; val 206 drivers/media/pci/pluto2/pluto2.c pluto_writereg(pluto, REG_MISC, val); val 212 drivers/media/pci/pluto2/pluto2.c u32 val = pluto_readreg(pluto, REG_TSCR); val 214 drivers/media/pci/pluto2/pluto2.c if (val & TSCR_RSTN) { val 215 drivers/media/pci/pluto2/pluto2.c val &= ~TSCR_RSTN; val 216 drivers/media/pci/pluto2/pluto2.c pluto_write_tscr(pluto, val); val 219 drivers/media/pci/pluto2/pluto2.c val |= TSCR_RSTN; val 220 drivers/media/pci/pluto2/pluto2.c pluto_write_tscr(pluto, val); val 359 drivers/media/pci/pluto2/pluto2.c u32 val = pluto_readreg(pluto, REG_TSCR); val 362 drivers/media/pci/pluto2/pluto2.c val |= (TSCR_MSKA | TSCR_MSKL); val 364 drivers/media/pci/pluto2/pluto2.c val &= ~(TSCR_DEM | TSCR_MSKO); val 366 drivers/media/pci/pluto2/pluto2.c val |= TSCR_IACK; val 368 drivers/media/pci/pluto2/pluto2.c pluto_write_tscr(pluto, val); val 373 drivers/media/pci/pluto2/pluto2.c u32 val = pluto_readreg(pluto, REG_TSCR); val 376 drivers/media/pci/pluto2/pluto2.c val |= (TSCR_DEM | TSCR_MSKO | TSCR_MSKA | TSCR_MSKL); val 378 drivers/media/pci/pluto2/pluto2.c val |= TSCR_IACK; val 380 drivers/media/pci/pluto2/pluto2.c pluto_write_tscr(pluto, val); val 527 drivers/media/pci/pluto2/pluto2.c u32 val = pluto_readreg(pluto, REG_MISC) & MISC_DVR; val 529 drivers/media/pci/pluto2/pluto2.c (val >> 12) & 0x0f, (val >> 4) & 0xff); val 534 drivers/media/pci/pluto2/pluto2.c u32 val = pluto_readreg(pluto, REG_MMAC); val 535 drivers/media/pci/pluto2/pluto2.c mac[0] = (val >> 8) & 0xff; val 536 drivers/media/pci/pluto2/pluto2.c mac[1] = (val >> 0) & 0xff; val 538 drivers/media/pci/pluto2/pluto2.c val = pluto_readreg(pluto, REG_IMAC); val 539 drivers/media/pci/pluto2/pluto2.c mac[2] = (val >> 8) & 0xff; val 540 drivers/media/pci/pluto2/pluto2.c mac[3] = (val >> 0) & 0xff; val 542 drivers/media/pci/pluto2/pluto2.c val = pluto_readreg(pluto, REG_LMAC); val 543 drivers/media/pci/pluto2/pluto2.c mac[4] = (val >> 8) & 0xff; val 544 drivers/media/pci/pluto2/pluto2.c mac[5] = (val >> 0) & 0xff; val 562 drivers/media/pci/pluto2/pluto2.c u32 val = readl(&cis[i]); val 564 drivers/media/pci/pluto2/pluto2.c if ((val & 0xff) == 0xff) val 566 drivers/media/pci/pluto2/pluto2.c printk(KERN_CONT "%c", val & 0xff); val 567 drivers/media/pci/pluto2/pluto2.c val >>= 8; val 88 drivers/media/pci/pt3/pt3.c u8 val; val 142 drivers/media/pci/pt3/pt3.c rv.val |= 0x40; val 144 drivers/media/pci/pt3/pt3.c rv.val |= 0x04; val 152 drivers/media/pci/pt3/pt3.c u32 val; val 158 drivers/media/pci/pt3/pt3.c val = fe->dtv_property_cache.lna; val 159 drivers/media/pci/pt3/pt3.c if (val == LNA_AUTO || val == adap->cur_lna) val 165 drivers/media/pci/pt3/pt3.c if (val) val 170 drivers/media/pci/pt3/pt3.c if (val && pt3->lna_on_cnt <= 1) { val 173 drivers/media/pci/pt3/pt3.c } else if (!val && pt3->lna_on_cnt <= 0) { val 179 drivers/media/pci/pt3/pt3.c adap->cur_lna = (val != 0); val 75 drivers/media/pci/pt3/pt3_i2c.c static void put_byte_write(struct pt3_i2cbuf *cbuf, u8 val) val 80 drivers/media/pci/pt3/pt3_i2c.c cmdbuf_add(cbuf, (val & mask) ? I_DATA_H_NOP : I_DATA_L_NOP); val 501 drivers/media/pci/saa7134/saa7134-video.c int val,mirror; val 515 drivers/media/pci/saa7134/saa7134-video.c val = 0x40 * 1024 / yscale; val 516 drivers/media/pci/saa7134/saa7134-video.c video_dbg("yscale ACM yscale=%d val=0x%x\n", yscale, val); val 518 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(SAA7134_LUMA_CONTRAST(task), val); val 519 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(SAA7134_CHROMA_SATURATION(task), val); val 606 drivers/media/pci/saa7134/saa7134-video.c static int clip_range(int val) val 608 drivers/media/pci/saa7134/saa7134-video.c if (val < 0) val 609 drivers/media/pci/saa7134/saa7134-video.c val = 0; val 610 drivers/media/pci/saa7134/saa7134-video.c return val; val 1051 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_bright = ctrl->val; val 1052 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(SAA7134_DEC_LUMA_BRIGHT, ctrl->val); val 1055 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_hue = ctrl->val; val 1056 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(SAA7134_DEC_CHROMA_HUE, ctrl->val); val 1059 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_contrast = ctrl->val; val 1064 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_saturation = ctrl->val; val 1069 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_mute = ctrl->val; val 1073 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_volume = ctrl->val; val 1077 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_invert = ctrl->val; val 1084 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_mirror = ctrl->val; val 1088 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_y_even = ctrl->val; val 1092 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_y_odd = ctrl->val; val 1102 drivers/media/pci/saa7134/saa7134-video.c dev->ctl_automute = ctrl->val; val 1860 drivers/media/pci/saa7134/saa7134-video.c reg->val = saa_readb(reg->reg & 0xffffff); val 1870 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg->reg & 0xffffff, reg->val); val 204 drivers/media/pci/saa7146/mxb.c mxb->cur_mute = ctrl->val; val 206 drivers/media/pci/saa7146/mxb.c tea6420_route(mxb, ctrl->val ? 6 : val 663 drivers/media/pci/saa7146/mxb.c reg->val = saa7146_read(dev, reg->reg); val 674 drivers/media/pci/saa7146/mxb.c saa7146_write(dev, reg->reg, reg->val); val 358 drivers/media/pci/saa7164/saa7164-api.c u16 val; val 361 drivers/media/pci/saa7164/saa7164-api.c val = port->ctl_brightness; val 364 drivers/media/pci/saa7164/saa7164-api.c val = port->ctl_contrast; val 367 drivers/media/pci/saa7164/saa7164-api.c val = port->ctl_hue; val 370 drivers/media/pci/saa7164/saa7164-api.c val = port->ctl_saturation; val 373 drivers/media/pci/saa7164/saa7164-api.c val = port->ctl_sharpness; val 378 drivers/media/pci/saa7164/saa7164-api.c __func__, port->encunit.vsourceid, ctl, val); val 381 drivers/media/pci/saa7164/saa7164-api.c ctl, sizeof(u16), &val); val 392 drivers/media/pci/saa7164/saa7164-api.c u16 val; val 395 drivers/media/pci/saa7164/saa7164-api.c ctl, sizeof(u16), &val); val 402 drivers/media/pci/saa7164/saa7164-api.c __func__, ctl, val); val 405 drivers/media/pci/saa7164/saa7164-api.c port->ctl_brightness = val; val 408 drivers/media/pci/saa7164/saa7164-api.c port->ctl_contrast = val; val 411 drivers/media/pci/saa7164/saa7164-api.c port->ctl_hue = val; val 414 drivers/media/pci/saa7164/saa7164-api.c port->ctl_saturation = val; val 417 drivers/media/pci/saa7164/saa7164-api.c port->ctl_sharpness = val; val 608 drivers/media/pci/saa7164/saa7164-api.c static int saa7164_api_set_dif(struct saa7164_port *port, u8 reg, u8 val) val 618 drivers/media/pci/saa7164/saa7164-api.c port->nr, port->type, val); val 642 drivers/media/pci/saa7164/saa7164-api.c buf[0x0c] = val; val 176 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[0 + i].val = i; val 180 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[30 + i].val = 30 + (i * 10); val 184 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[48 + i].val = 200 + (i * 200); val 187 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[55].val = 2000; val 190 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[56].val = 4000; val 193 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[57].val = 8000; val 196 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[58].val = 15000; val 199 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[59].val = 30000; val 202 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[60].val = 60000; val 205 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[61].val = 300000; val 208 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[62].val = 900000; val 211 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[63].val = 3600000; val 214 drivers/media/pci/saa7164/saa7164-core.c void saa7164_histogram_update(struct saa7164_histogram *hg, u32 val) val 218 drivers/media/pci/saa7164/saa7164-core.c if (val <= hg->counter1[i].val) { val 238 drivers/media/pci/saa7164/saa7164-core.c hg->counter1[i].val, val 417 drivers/media/pci/saa7164/saa7164-encoder.c port->ctl_brightness = ctrl->val; val 421 drivers/media/pci/saa7164/saa7164-encoder.c port->ctl_contrast = ctrl->val; val 425 drivers/media/pci/saa7164/saa7164-encoder.c port->ctl_saturation = ctrl->val; val 429 drivers/media/pci/saa7164/saa7164-encoder.c port->ctl_hue = ctrl->val; val 433 drivers/media/pci/saa7164/saa7164-encoder.c port->ctl_sharpness = ctrl->val; val 437 drivers/media/pci/saa7164/saa7164-encoder.c port->ctl_volume = ctrl->val; val 441 drivers/media/pci/saa7164/saa7164-encoder.c params->bitrate = ctrl->val; val 444 drivers/media/pci/saa7164/saa7164-encoder.c params->stream_type = ctrl->val; val 447 drivers/media/pci/saa7164/saa7164-encoder.c params->ctl_mute = ctrl->val; val 456 drivers/media/pci/saa7164/saa7164-encoder.c params->ctl_aspect = ctrl->val; val 465 drivers/media/pci/saa7164/saa7164-encoder.c params->bitrate_mode = ctrl->val; val 468 drivers/media/pci/saa7164/saa7164-encoder.c params->refdist = ctrl->val; val 471 drivers/media/pci/saa7164/saa7164-encoder.c params->bitrate_peak = ctrl->val; val 474 drivers/media/pci/saa7164/saa7164-encoder.c params->gop_size = ctrl->val; val 190 drivers/media/pci/saa7164/saa7164.h u32 val; val 486 drivers/media/pci/saa7164/saa7164.h void saa7164_histogram_update(struct saa7164_histogram *hg, u32 val); val 243 drivers/media/pci/solo6x10/solo6x10-core.c unsigned int val; val 246 drivers/media/pci/solo6x10/solo6x10-core.c val = solo_reg_read(solo_dev, SOLO_VI_CH_SWITCH_0); val 247 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 0 => Input %d\n", val & 0x1f); val 248 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 1 => Input %d\n", (val >> 5) & 0x1f); val 249 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 2 => Input %d\n", (val >> 10) & 0x1f); val 250 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 3 => Input %d\n", (val >> 15) & 0x1f); val 251 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 4 => Input %d\n", (val >> 20) & 0x1f); val 252 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 5 => Input %d\n", (val >> 25) & 0x1f); val 254 drivers/media/pci/solo6x10/solo6x10-core.c val = solo_reg_read(solo_dev, SOLO_VI_CH_SWITCH_1); val 255 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 6 => Input %d\n", val & 0x1f); val 256 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 7 => Input %d\n", (val >> 5) & 0x1f); val 257 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 8 => Input %d\n", (val >> 10) & 0x1f); val 258 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 9 => Input %d\n", (val >> 15) & 0x1f); val 259 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 10 => Input %d\n", (val >> 20) & 0x1f); val 260 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 11 => Input %d\n", (val >> 25) & 0x1f); val 262 drivers/media/pci/solo6x10/solo6x10-core.c val = solo_reg_read(solo_dev, SOLO_VI_CH_SWITCH_2); val 263 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 12 => Input %d\n", val & 0x1f); val 264 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 13 => Input %d\n", (val >> 5) & 0x1f); val 265 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 14 => Input %d\n", (val >> 10) & 0x1f); val 266 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Channel 15 => Input %d\n", (val >> 15) & 0x1f); val 267 drivers/media/pci/solo6x10/solo6x10-core.c out += sprintf(out, "Spot Output => Input %d\n", (val >> 20) & 0x1f); val 164 drivers/media/pci/solo6x10/solo6x10-disp.c u16 val, int reg_size) val 175 drivers/media/pci/solo6x10/solo6x10-disp.c buf[i] = cpu_to_le16(val); val 190 drivers/media/pci/solo6x10/solo6x10-disp.c int solo_set_motion_threshold(struct solo_dev *solo_dev, u8 ch, u16 val) val 197 drivers/media/pci/solo6x10/solo6x10-disp.c val, SOLO_MOT_THRESH_SIZE); val 185 drivers/media/pci/solo6x10/solo6x10-tw28.c u8 tw6x_off, u8 tw_off, u8 val) val 190 drivers/media/pci/solo6x10/solo6x10-tw28.c tw6x_off, val); val 194 drivers/media/pci/solo6x10/solo6x10-tw28.c tw_off, val); val 198 drivers/media/pci/solo6x10/solo6x10-tw28.c u8 val) val 205 drivers/media/pci/solo6x10/solo6x10-tw28.c if (rval == val) val 208 drivers/media/pci/solo6x10/solo6x10-tw28.c solo_i2c_writebyte(solo_dev, SOLO_I2C_TW, addr, off, val); val 643 drivers/media/pci/solo6x10/solo6x10-tw28.c u8 val, chip_num; val 649 drivers/media/pci/solo6x10/solo6x10-tw28.c val = tw_readbyte(solo_dev, chip_num, TW286x_AV_STAT_ADDR, val 652 drivers/media/pci/solo6x10/solo6x10-tw28.c return val & (1 << ch) ? 1 : 0; val 660 drivers/media/pci/solo6x10/solo6x10-tw28.c u8 val; val 665 drivers/media/pci/solo6x10/solo6x10-tw28.c val = (tw_readbyte(solo_dev, i, TW286x_AV_STAT_ADDR, val 667 drivers/media/pci/solo6x10/solo6x10-tw28.c status |= val << (i * 4); val 680 drivers/media/pci/solo6x10/solo6x10-tw28.c s32 val) val 689 drivers/media/pci/solo6x10/solo6x10-tw28.c if (val > 255 || val < 0) val 700 drivers/media/pci/solo6x10/solo6x10-tw28.c v |= val; val 711 drivers/media/pci/solo6x10/solo6x10-tw28.c sval = val - 128; val 713 drivers/media/pci/solo6x10/solo6x10-tw28.c sval = (char)val; val 724 drivers/media/pci/solo6x10/solo6x10-tw28.c TW286x_SATURATIONU_ADDR(ch), val); val 727 drivers/media/pci/solo6x10/solo6x10-tw28.c TW_SATURATION_ADDR(ch), val); val 733 drivers/media/pci/solo6x10/solo6x10-tw28.c TW_CONTRAST_ADDR(ch), val); val 738 drivers/media/pci/solo6x10/solo6x10-tw28.c sval = val - 128; val 740 drivers/media/pci/solo6x10/solo6x10-tw28.c sval = (char)val; val 753 drivers/media/pci/solo6x10/solo6x10-tw28.c s32 *val) val 768 drivers/media/pci/solo6x10/solo6x10-tw28.c *val = rval & 0x0f; val 770 drivers/media/pci/solo6x10/solo6x10-tw28.c *val = 0; val 776 drivers/media/pci/solo6x10/solo6x10-tw28.c *val = (s32)((char)rval) + 128; val 778 drivers/media/pci/solo6x10/solo6x10-tw28.c *val = rval; val 781 drivers/media/pci/solo6x10/solo6x10-tw28.c *val = tw_readbyte(solo_dev, chip_num, val 786 drivers/media/pci/solo6x10/solo6x10-tw28.c *val = tw_readbyte(solo_dev, chip_num, val 795 drivers/media/pci/solo6x10/solo6x10-tw28.c *val = (s32)((char)rval) + 128; val 797 drivers/media/pci/solo6x10/solo6x10-tw28.c *val = rval; val 814 drivers/media/pci/solo6x10/solo6x10-tw28.c unsigned int val; val 819 drivers/media/pci/solo6x10/solo6x10-tw28.c val = tw_readbyte(solo_dev, chip_num, TW286x_AUDIO_OUTPUT_VOL_ADDR, val 822 drivers/media/pci/solo6x10/solo6x10-tw28.c u_val = (val & 0x0f) | (u_val << 4); val 831 drivers/media/pci/solo6x10/solo6x10-tw28.c u8 val; val 838 drivers/media/pci/solo6x10/solo6x10-tw28.c val = tw_readbyte(solo_dev, chip_num, val 842 drivers/media/pci/solo6x10/solo6x10-tw28.c return (ch % 2) ? (val >> 4) : (val & 0x0f); val 845 drivers/media/pci/solo6x10/solo6x10-tw28.c void tw28_set_audio_gain(struct solo_dev *solo_dev, u8 ch, u8 val) val 858 drivers/media/pci/solo6x10/solo6x10-tw28.c val = (old_val & ((ch % 2) ? 0x0f : 0xf0)) | val 859 drivers/media/pci/solo6x10/solo6x10-tw28.c ((ch % 2) ? (val << 4) : val); val 862 drivers/media/pci/solo6x10/solo6x10-tw28.c TW_AUDIO_INPUT_GAIN_ADDR(ch), val); val 43 drivers/media/pci/solo6x10/solo6x10-tw28.h int tw28_set_ctrl_val(struct solo_dev *solo_dev, u32 ctrl, u8 ch, s32 val); val 44 drivers/media/pci/solo6x10/solo6x10-tw28.h int tw28_get_ctrl_val(struct solo_dev *solo_dev, u32 ctrl, u8 ch, s32 *val); val 48 drivers/media/pci/solo6x10/solo6x10-tw28.h void tw28_set_audio_gain(struct solo_dev *solo_dev, u8 ch, u8 val); val 1071 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c ctrl->val); val 1073 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_enc->gop = ctrl->val; val 1078 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_enc->qp = ctrl->val; val 1083 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_enc->motion_thresh = ctrl->val << 8; val 1089 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_enc->motion_global = ctrl->val == V4L2_DETECT_MD_MODE_GLOBAL; val 1090 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_enc->motion_enabled = ctrl->val > V4L2_DETECT_MD_MODE_DISABLED; val 1091 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c if (ctrl->val) { val 1101 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_motion_toggle(solo_enc, ctrl->val); val 559 drivers/media/pci/solo6x10/solo6x10-v4l2.c if (ctrl->val) { val 283 drivers/media/pci/solo6x10/solo6x10.h u16 val; val 286 drivers/media/pci/solo6x10/solo6x10.h pci_read_config_word(solo_dev->pdev, PCI_STATUS, &val); val 359 drivers/media/pci/solo6x10/solo6x10.h int solo_set_motion_threshold(struct solo_dev *solo_dev, u8 ch, u16 val); val 203 drivers/media/pci/sta2x11/sta2x11_vip.c static inline void reg_write(struct sta2x11_vip *vip, unsigned int reg, u32 val) val 205 drivers/media/pci/sta2x11/sta2x11_vip.c iowrite32((val), (vip->iomem)+(reg)); val 1405 drivers/media/pci/ttpci/av7110.c int i2c_writereg(struct av7110 *av7110, u8 id, u8 reg, u8 val) val 1407 drivers/media/pci/ttpci/av7110.c u8 msg[2] = { reg, val }; val 306 drivers/media/pci/ttpci/av7110.h extern int i2c_writereg(struct av7110 *av7110, u8 id, u8 reg, u8 val); val 308 drivers/media/pci/ttpci/av7110.h extern int msp_writereg(struct av7110 *av7110, u8 dev, u16 reg, u16 val); val 269 drivers/media/pci/ttpci/av7110_av.c unsigned int vol, val, balance = 0; val 298 drivers/media/pci/ttpci/av7110_av.c val = (vol * 0x73 / 255) << 8; val 302 drivers/media/pci/ttpci/av7110_av.c msp_writereg(av7110, MSP_WR_DSP, 0x0000, val); /* loudspeaker */ val 303 drivers/media/pci/ttpci/av7110_av.c msp_writereg(av7110, MSP_WR_DSP, 0x0006, val); /* headphonesr */ val 308 drivers/media/pci/ttpci/av7110_av.c val = (vol * 0x73 / 255) << 8; val 312 drivers/media/pci/ttpci/av7110_av.c msp_writereg(av7110, MSP_WR_DSP, 0x0000, val); /* loudspeaker */ val 44 drivers/media/pci/ttpci/av7110_hw.c int addr, u32 val, unsigned int count) val 58 drivers/media/pci/ttpci/av7110_hw.c saa7146_write(dev, DEBI_AD, val); val 1196 drivers/media/pci/ttpci/av7110_hw.c cap->val = 1000000; val 1198 drivers/media/pci/ttpci/av7110_hw.c cap->val = 92000; val 381 drivers/media/pci/ttpci/av7110_hw.h int addr, u32 val, unsigned int count); val 388 drivers/media/pci/ttpci/av7110_hw.h static inline void iwdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) val 390 drivers/media/pci/ttpci/av7110_hw.h av7110_debiwrite(av7110, config, addr, val, count); val 395 drivers/media/pci/ttpci/av7110_hw.h const u8 *val, int count) val 397 drivers/media/pci/ttpci/av7110_hw.h memcpy(av7110->debi_virt, val, count); val 401 drivers/media/pci/ttpci/av7110_hw.h static inline u32 irdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) val 412 drivers/media/pci/ttpci/av7110_hw.h static inline void wdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) val 417 drivers/media/pci/ttpci/av7110_hw.h av7110_debiwrite(av7110, config, addr, val, count); val 421 drivers/media/pci/ttpci/av7110_hw.h static inline u32 rdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) val 27 drivers/media/pci/ttpci/av7110_v4l.c int msp_writereg(struct av7110 *av7110, u8 dev, u16 reg, u16 val) val 29 drivers/media/pci/ttpci/av7110_v4l.c u8 msg[5] = { dev, reg >> 8, reg & 0xff, val >> 8 , val & 0xff }; val 45 drivers/media/pci/ttpci/av7110_v4l.c av7110->dvb_adapter.num, reg, val); val 51 drivers/media/pci/ttpci/av7110_v4l.c static int msp_readreg(struct av7110 *av7110, u8 dev, u16 reg, u16 *val) val 78 drivers/media/pci/ttpci/av7110_v4l.c *val = (msg2[0] << 8) | msg2[1]; val 111 drivers/media/pci/ttpci/budget-av.c static int i2c_writereg(struct i2c_adapter *i2c, u8 id, u8 reg, u8 val) val 113 drivers/media/pci/ttpci/budget-av.c u8 msg[2] = { reg, val }; val 416 drivers/media/pci/ttpci/budget.c u8 val; val 419 drivers/media/pci/ttpci/budget.c { .addr = adr, .flags = I2C_M_RD, .buf = &val, .len = 1 } val 422 drivers/media/pci/ttpci/budget.c return (i2c_transfer(i2c, msg, 2) != 2) ? -EIO : val; val 77 drivers/media/pci/tw5864/tw5864-h264.c static void bs_write_ue(struct bs *s, u32 val) val 79 drivers/media/pci/tw5864/tw5864-h264.c if (val == 0) { val 82 drivers/media/pci/tw5864/tw5864-h264.c val++; val 83 drivers/media/pci/tw5864/tw5864-h264.c bs_write(s, 2 * fls(val) - 1, val); val 87 drivers/media/pci/tw5864/tw5864-h264.c static void bs_write_se(struct bs *s, int val) val 89 drivers/media/pci/tw5864/tw5864-h264.c bs_write_ue(s, val <= 0 ? -val * 2 : val * 2 - 1); val 487 drivers/media/pci/tw5864/tw5864-video.c (u8)ctrl->val); val 491 drivers/media/pci/tw5864/tw5864-video.c (u8)ctrl->val); val 495 drivers/media/pci/tw5864/tw5864-video.c (u8)ctrl->val); val 499 drivers/media/pci/tw5864/tw5864-video.c (u8)ctrl->val); val 501 drivers/media/pci/tw5864/tw5864-video.c (u8)ctrl->val); val 504 drivers/media/pci/tw5864/tw5864-video.c input->gop = ctrl->val; val 508 drivers/media/pci/tw5864/tw5864-video.c input->qp = ctrl->val; val 515 drivers/media/pci/tw5864/tw5864-video.c memset(input->md_threshold_grid_values, ctrl->val, val 851 drivers/media/pci/tw5864/tw5864-video.c reg->val = tw_readl(reg->reg); val 858 drivers/media/pci/tw5864/tw5864-video.c reg->val = tw_indir_readb(reg->reg); val 872 drivers/media/pci/tw5864/tw5864-video.c tw_writel(reg->reg, reg->val); val 878 drivers/media/pci/tw5864/tw5864-video.c tw_indir_writeb(reg->reg, reg->val); val 1348 drivers/media/pci/tw5864/tw5864-video.c u32 val, count_len = len; val 1350 drivers/media/pci/tw5864/tw5864-video.c val = *data++; val 1352 drivers/media/pci/tw5864/tw5864-video.c val ^= *data++; val 1355 drivers/media/pci/tw5864/tw5864-video.c val ^= htonl((len >> 2)); val 1356 drivers/media/pci/tw5864/tw5864-video.c return val; val 537 drivers/media/pci/tw68/tw68-video.c tw_writeb(TW68_BRIGHT, ctrl->val); val 540 drivers/media/pci/tw68/tw68-video.c tw_writeb(TW68_HUE, ctrl->val); val 543 drivers/media/pci/tw68/tw68-video.c tw_writeb(TW68_CONTRAST, ctrl->val); val 546 drivers/media/pci/tw68/tw68-video.c tw_writeb(TW68_SAT_U, ctrl->val); val 547 drivers/media/pci/tw68/tw68-video.c tw_writeb(TW68_SAT_V, ctrl->val); val 550 drivers/media/pci/tw68/tw68-video.c if (ctrl->val) val 556 drivers/media/pci/tw68/tw68-video.c if (ctrl->val) val 830 drivers/media/pci/tw68/tw68-video.c reg->val = tw_readb(reg->reg); val 832 drivers/media/pci/tw68/tw68-video.c reg->val = tw_readl(reg->reg); val 842 drivers/media/pci/tw68/tw68-video.c tw_writeb(reg->reg, reg->val); val 844 drivers/media/pci/tw68/tw68-video.c tw_writel(reg->reg & 0xffff, reg->val); val 77 drivers/media/pci/tw686x/tw686x-core.c static int tw686x_dma_mode_set(const char *val, const struct kernel_param *kp) val 79 drivers/media/pci/tw686x/tw686x-core.c if (!strcasecmp(val, dma_mode_name(TW686X_DMA_MODE_MEMCPY))) val 81 drivers/media/pci/tw686x/tw686x-core.c else if (!strcasecmp(val, dma_mode_name(TW686X_DMA_MODE_CONTIG))) val 83 drivers/media/pci/tw686x/tw686x-core.c else if (!strcasecmp(val, dma_mode_name(TW686X_DMA_MODE_SG))) val 599 drivers/media/pci/tw686x/tw686x-video.c reg_write(dev, BRIGHT[ch], ctrl->val & 0xff); val 603 drivers/media/pci/tw686x/tw686x-video.c reg_write(dev, CONTRAST[ch], ctrl->val); val 607 drivers/media/pci/tw686x/tw686x-video.c reg_write(dev, SAT_U[ch], ctrl->val); val 608 drivers/media/pci/tw686x/tw686x-video.c reg_write(dev, SAT_V[ch], ctrl->val); val 612 drivers/media/pci/tw686x/tw686x-video.c reg_write(dev, HUE[ch], ctrl->val & 0xff); val 676 drivers/media/pci/tw686x/tw686x-video.c u32 val, dma_width, dma_height, dma_line_width; val 698 drivers/media/pci/tw686x/tw686x-video.c val = reg_read(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch]); val 701 drivers/media/pci/tw686x/tw686x-video.c val |= BIT(23); val 703 drivers/media/pci/tw686x/tw686x-video.c val &= ~BIT(23); val 706 drivers/media/pci/tw686x/tw686x-video.c val |= BIT(24); val 708 drivers/media/pci/tw686x/tw686x-video.c val &= ~BIT(24); val 710 drivers/media/pci/tw686x/tw686x-video.c val &= ~0x7ffff; val 720 drivers/media/pci/tw686x/tw686x-video.c val |= (end_idx << 10) | start_idx; val 723 drivers/media/pci/tw686x/tw686x-video.c val &= ~(0x7 << 20); val 724 drivers/media/pci/tw686x/tw686x-video.c val |= vc->format->mode << 20; val 725 drivers/media/pci/tw686x/tw686x-video.c reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val); val 731 drivers/media/pci/tw686x/tw686x-video.c val = (dma_height << 22) | (dma_line_width << 11) | dma_width; val 732 drivers/media/pci/tw686x/tw686x-video.c reg_write(vc->dev, VDMA_WHP[vc->ch], val); val 773 drivers/media/pci/tw686x/tw686x-video.c u32 val; val 776 drivers/media/pci/tw686x/tw686x-video.c val = 0; val 778 drivers/media/pci/tw686x/tw686x-video.c val = 1; val 780 drivers/media/pci/tw686x/tw686x-video.c val = 2; val 782 drivers/media/pci/tw686x/tw686x-video.c val = 3; val 784 drivers/media/pci/tw686x/tw686x-video.c val = 4; val 786 drivers/media/pci/tw686x/tw686x-video.c val = 5; val 788 drivers/media/pci/tw686x/tw686x-video.c val = 6; val 793 drivers/media/pci/tw686x/tw686x-video.c reg_write(vc->dev, SDT[vc->ch], val); val 795 drivers/media/pci/tw686x/tw686x-video.c val = reg_read(vc->dev, VIDEO_CONTROL1); val 797 drivers/media/pci/tw686x/tw686x-video.c val &= ~(1 << (SYS_MODE_DMA_SHIFT + vc->ch)); val 799 drivers/media/pci/tw686x/tw686x-video.c val |= (1 << (SYS_MODE_DMA_SHIFT + vc->ch)); val 800 drivers/media/pci/tw686x/tw686x-video.c reg_write(vc->dev, VIDEO_CONTROL1, val); val 983 drivers/media/pci/tw686x/tw686x-video.c u32 val; val 987 drivers/media/pci/tw686x/tw686x-video.c val = reg_read(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch]); val 988 drivers/media/pci/tw686x/tw686x-video.c val &= ~(0x3 << 30); val 989 drivers/media/pci/tw686x/tw686x-video.c val |= i << 30; val 990 drivers/media/pci/tw686x/tw686x-video.c reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val); val 1164 drivers/media/pci/tw686x/tw686x-video.c unsigned int ch, val; val 1291 drivers/media/pci/tw686x/tw686x-video.c val = TW686X_DEF_PHASE_REF; val 1293 drivers/media/pci/tw686x/tw686x-video.c val |= dev->dma_ops->hw_dma_mode << (16 + ch * 2); val 1294 drivers/media/pci/tw686x/tw686x-video.c reg_write(dev, PHASE_REF, val); val 289 drivers/media/platform/am437x/am437x-vpfe.c static inline void vpfe_reg_write(struct vpfe_ccdc *ccdc, u32 val, u32 offset) val 291 drivers/media/platform/am437x/am437x-vpfe.c iowrite32(val, ccdc->ccdc_cfg.base_addr + offset); val 331 drivers/media/platform/am437x/am437x-vpfe.c int val, mid_img; val 351 drivers/media/platform/am437x/am437x-vpfe.c val = (vert_start << VPFE_VDINT_VDINT0_SHIFT); val 361 drivers/media/platform/am437x/am437x-vpfe.c val = (vert_start << VPFE_VDINT_VDINT0_SHIFT) | val 365 drivers/media/platform/am437x/am437x-vpfe.c vpfe_reg_write(ccdc, val, VPFE_VDINT); val 598 drivers/media/platform/am437x/am437x-vpfe.c u32 val; val 602 drivers/media/platform/am437x/am437x-vpfe.c val = (bclamp->dc_sub) & VPFE_BLK_DC_SUB_MASK; val 603 drivers/media/platform/am437x/am437x-vpfe.c vpfe_reg_write(ccdc, val, VPFE_DCSUB); val 611 drivers/media/platform/am437x/am437x-vpfe.c val = ((bclamp->sgain & VPFE_BLK_SGAIN_MASK) | val 618 drivers/media/platform/am437x/am437x-vpfe.c vpfe_reg_write(ccdc, val, VPFE_CLAMP); val 627 drivers/media/platform/am437x/am437x-vpfe.c u32 val; val 629 drivers/media/platform/am437x/am437x-vpfe.c val = ((bcomp->b & VPFE_BLK_COMP_MASK) | val 636 drivers/media/platform/am437x/am437x-vpfe.c vpfe_reg_write(ccdc, val, VPFE_BLKCMP); val 650 drivers/media/platform/am437x/am437x-vpfe.c unsigned int val; val 679 drivers/media/platform/am437x/am437x-vpfe.c val = ((config_params->alaw.gamma_wd & val 681 drivers/media/platform/am437x/am437x-vpfe.c vpfe_reg_write(ccdc, val, VPFE_ALAW); val 682 drivers/media/platform/am437x/am437x-vpfe.c vpfe_dbg(3, vpfe, "\nWriting 0x%x to ALAW...\n", val); val 423 drivers/media/platform/aspeed-video.c static void aspeed_video_write(struct aspeed_video *video, u32 reg, u32 val) val 425 drivers/media/platform/aspeed-video.c writel(val, video->base + reg); val 1290 drivers/media/platform/aspeed-video.c video->jpeg_quality = ctrl->val; val 1294 drivers/media/platform/aspeed-video.c if (ctrl->val == V4L2_JPEG_CHROMA_SUBSAMPLING_420) { val 637 drivers/media/platform/atmel/atmel-isc-base.c u32 val, bay_cfg; val 643 drivers/media/platform/atmel/atmel-isc-base.c val = pipeline & BIT(i) ? 1 : 0; val 644 drivers/media/platform/atmel/atmel-isc-base.c regmap_field_write(isc->pipeline[i], val); val 1812 drivers/media/platform/atmel/atmel-isc-base.c ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK; val 1815 drivers/media/platform/atmel/atmel-isc-base.c ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK; val 1818 drivers/media/platform/atmel/atmel-isc-base.c ctrls->gamma_index = ctrl->val; val 1821 drivers/media/platform/atmel/atmel-isc-base.c if (ctrl->val == 1) val 136 drivers/media/platform/atmel/atmel-isi.c static void isi_writel(struct atmel_isi *isi, u32 reg, u32 val) val 138 drivers/media/platform/atmel/atmel-isi.c writel(val, isi->regs + reg); val 1839 drivers/media/platform/coda/coda-bit.c u32 val; val 1873 drivers/media/platform/coda/coda-bit.c val = 0; val 1875 drivers/media/platform/coda/coda-bit.c val |= CODA_REORDER_ENABLE; val 1877 drivers/media/platform/coda/coda-bit.c val |= CODA_NO_INT_ENABLE; val 1878 drivers/media/platform/coda/coda-bit.c coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION); val 1928 drivers/media/platform/coda/coda-bit.c val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE); val 1930 drivers/media/platform/coda/coda-bit.c width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK; val 1931 drivers/media/platform/coda/coda-bit.c height = val & CODADX6_PICHEIGHT_MASK; val 1933 drivers/media/platform/coda/coda-bit.c width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK; val 1934 drivers/media/platform/coda/coda-bit.c height = val & CODA7_PICHEIGHT_MASK; val 1984 drivers/media/platform/coda/coda-bit.c val = coda_read(dev, CODA7_RET_DEC_SEQ_HEADER_REPORT); val 1985 drivers/media/platform/coda/coda-bit.c profile = val & 0xff; val 1986 drivers/media/platform/coda/coda-bit.c level = (val >> 8) & 0x7f; val 2267 drivers/media/platform/coda/coda-bit.c u32 val; val 2285 drivers/media/platform/coda/coda-bit.c val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS); val 2286 drivers/media/platform/coda/coda-bit.c if (val != 1) val 2287 drivers/media/platform/coda/coda-bit.c pr_err("DEC_PIC_SUCCESS = %d\n", val); val 2289 drivers/media/platform/coda/coda-bit.c success = val & 0x1; val 2294 drivers/media/platform/coda/coda-bit.c if (val & (1 << 3)) val 2298 drivers/media/platform/coda/coda-bit.c if (val & (1 << 2)) val 2304 drivers/media/platform/coda/coda-bit.c val = coda_read(dev, CODA_RET_DEC_PIC_SIZE); val 2305 drivers/media/platform/coda/coda-bit.c width = (val >> 16) & 0xffff; val 2306 drivers/media/platform/coda/coda-bit.c height = val & 0xffff; val 2341 drivers/media/platform/coda/coda-bit.c val = coda_read(dev, CODA_RET_DEC_PIC_OPTION); val 2342 drivers/media/platform/coda/coda-bit.c if (val == 0) { val 2344 drivers/media/platform/coda/coda-bit.c coda_dbg(1, ctx, "prescan failed: %d\n", val); val 2393 drivers/media/platform/coda/coda-bit.c val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM); val 2395 drivers/media/platform/coda/coda-bit.c ctx->sequence_offset = val; val 2396 drivers/media/platform/coda/coda-bit.c val -= ctx->sequence_offset; val 2411 drivers/media/platform/coda/coda-bit.c if ((val & 0xffff) != (meta->sequence & 0xffff)) { val 2414 drivers/media/platform/coda/coda-bit.c val, ctx->sequence_offset, val 2424 drivers/media/platform/coda/coda-bit.c decoded_frame->meta.sequence = val; val 2431 drivers/media/platform/coda/coda-bit.c val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7; val 2432 drivers/media/platform/coda/coda-bit.c decoded_frame->type = (val == 0) ? V4L2_BUF_FLAG_KEYFRAME : val 2433 drivers/media/platform/coda/coda-bit.c (val == 1) ? V4L2_BUF_FLAG_PFRAME : val 2014 drivers/media/platform/coda/coda-common.c ctrl->id, ctrl->name, ctrl->val, val_names[ctrl->val]); val 2017 drivers/media/platform/coda/coda-common.c ctrl->id, ctrl->name, ctrl->val); val 2021 drivers/media/platform/coda/coda-common.c if (ctrl->val) val 2027 drivers/media/platform/coda/coda-common.c if (ctrl->val) val 2033 drivers/media/platform/coda/coda-common.c ctx->params.bitrate = ctrl->val / 1000; val 2037 drivers/media/platform/coda/coda-common.c ctx->params.gop_size = ctrl->val; val 2040 drivers/media/platform/coda/coda-common.c ctx->params.h264_intra_qp = ctrl->val; val 2044 drivers/media/platform/coda/coda-common.c ctx->params.h264_inter_qp = ctrl->val; val 2047 drivers/media/platform/coda/coda-common.c ctx->params.h264_min_qp = ctrl->val; val 2050 drivers/media/platform/coda/coda-common.c ctx->params.h264_max_qp = ctrl->val; val 2053 drivers/media/platform/coda/coda-common.c ctx->params.h264_slice_alpha_c0_offset_div2 = ctrl->val; val 2056 drivers/media/platform/coda/coda-common.c ctx->params.h264_slice_beta_offset_div2 = ctrl->val; val 2059 drivers/media/platform/coda/coda-common.c ctx->params.h264_disable_deblocking_filter_idc = ctrl->val; val 2062 drivers/media/platform/coda/coda-common.c ctx->params.h264_constrained_intra_pred_flag = ctrl->val; val 2065 drivers/media/platform/coda/coda-common.c ctx->params.h264_chroma_qp_index_offset = ctrl->val; val 2076 drivers/media/platform/coda/coda-common.c ctx->params.mpeg4_intra_qp = ctrl->val; val 2079 drivers/media/platform/coda/coda-common.c ctx->params.mpeg4_inter_qp = ctrl->val; val 2088 drivers/media/platform/coda/coda-common.c ctx->params.slice_mode = ctrl->val; val 2092 drivers/media/platform/coda/coda-common.c ctx->params.slice_max_mb = ctrl->val; val 2096 drivers/media/platform/coda/coda-common.c ctx->params.slice_max_bits = ctrl->val * 8; val 2102 drivers/media/platform/coda/coda-common.c ctx->params.intra_refresh = ctrl->val; val 2109 drivers/media/platform/coda/coda-common.c coda_set_jpeg_compression_quality(ctx, ctrl->val); val 2112 drivers/media/platform/coda/coda-common.c ctx->params.jpeg_restart_interval = ctrl->val; val 2115 drivers/media/platform/coda/coda-common.c ctx->params.vbv_delay = ctrl->val; val 2118 drivers/media/platform/coda/coda-common.c ctx->params.vbv_size = min(ctrl->val * 8192, 0x7fffffff); val 2122 drivers/media/platform/coda/coda-common.c ctrl->id, ctrl->val); val 20 drivers/media/platform/coda/coda-h264.c u32 val = 0xffffffff; val 23 drivers/media/platform/coda/coda-h264.c val = val << 8 | *buf++; val 26 drivers/media/platform/coda/coda-h264.c } while (val != 0x00000001); val 146 drivers/media/platform/coda/coda-h264.c static inline int rbsp_read_bits(struct rbsp *rbsp, int num, int *val) val 161 drivers/media/platform/coda/coda-h264.c if (val) val 162 drivers/media/platform/coda/coda-h264.c *val = tmp; val 180 drivers/media/platform/coda/coda-h264.c static int rbsp_read_uev(struct rbsp *rbsp, unsigned int *val) val 197 drivers/media/platform/coda/coda-h264.c if (val) val 198 drivers/media/platform/coda/coda-h264.c *val = (1 << leading_zero_bits) - 1 + tmp; val 219 drivers/media/platform/coda/coda-h264.c static int rbsp_read_sev(struct rbsp *rbsp, int *val) val 228 drivers/media/platform/coda/coda-h264.c if (val) { val 230 drivers/media/platform/coda/coda-h264.c *val = (tmp + 1) / 2; val 232 drivers/media/platform/coda/coda-h264.c *val = -(tmp / 2); val 104 drivers/media/platform/coda/imx-vdoa.c u32 val; val 116 drivers/media/platform/coda/imx-vdoa.c val = readl(vdoa->regs + VDOAIST); val 117 drivers/media/platform/coda/imx-vdoa.c writel(val, vdoa->regs + VDOAIST); val 118 drivers/media/platform/coda/imx-vdoa.c if (val & VDOAIST_TERR) { val 119 drivers/media/platform/coda/imx-vdoa.c val = readl(vdoa->regs + VDOASR) & VDOASR_ERRW; val 120 drivers/media/platform/coda/imx-vdoa.c dev_err(vdoa->dev, "AXI %s error\n", val ? "write" : "read"); val 121 drivers/media/platform/coda/imx-vdoa.c } else if (!(val & VDOAIST_EOT)) { val 152 drivers/media/platform/coda/imx-vdoa.c u32 val; val 167 drivers/media/platform/coda/imx-vdoa.c val = VDOAC_PFS; val 169 drivers/media/platform/coda/imx-vdoa.c val = 0; val 170 drivers/media/platform/coda/imx-vdoa.c writel(val, vdoa->regs + VDOAC); val 175 drivers/media/platform/coda/imx-vdoa.c val = dst; val 176 drivers/media/platform/coda/imx-vdoa.c writel(val, vdoa->regs + VDOAIEBA00); val 183 drivers/media/platform/coda/imx-vdoa.c val = dst_q_data->bytesperline * dst_q_data->height; val 185 drivers/media/platform/coda/imx-vdoa.c val = 0; val 186 drivers/media/platform/coda/imx-vdoa.c writel(val, vdoa->regs + VDOAIUBO); val 188 drivers/media/platform/coda/imx-vdoa.c val = src; val 189 drivers/media/platform/coda/imx-vdoa.c writel(val, vdoa->regs + VDOAVEBA0); val 190 drivers/media/platform/coda/imx-vdoa.c val = round_up(src_q_data->bytesperline * src_q_data->height, 4096); val 191 drivers/media/platform/coda/imx-vdoa.c writel(val, vdoa->regs + VDOAVUBO); val 106 drivers/media/platform/cros-ec-cec/cros-ec-cec.c msg.data.val = logical_addr; val 156 drivers/media/platform/cros-ec-cec/cros-ec-cec.c msg.data.val = enable; val 114 drivers/media/platform/davinci/dm355_ccdc.c static inline void regw(u32 val, u32 offset) val 116 drivers/media/platform/davinci/dm355_ccdc.c __raw_writel(val, ccdc_cfg.base_addr + offset); val 317 drivers/media/platform/davinci/dm355_ccdc.c u32 val; val 326 drivers/media/platform/davinci/dm355_ccdc.c val = (bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) | val 329 drivers/media/platform/davinci/dm355_ccdc.c regw(val, CLAMP); val 332 drivers/media/platform/davinci/dm355_ccdc.c val = (bclamp->sample_ln & CCDC_NUM_LINE_CALC_MASK) val 334 drivers/media/platform/davinci/dm355_ccdc.c regw(val, DCSUB); val 343 drivers/media/platform/davinci/dm355_ccdc.c u32 val; val 345 drivers/media/platform/davinci/dm355_ccdc.c val = (bcomp->b & CCDC_BLK_COMP_MASK) | val 348 drivers/media/platform/davinci/dm355_ccdc.c regw(val, BLKCMP1); val 350 drivers/media/platform/davinci/dm355_ccdc.c val = ((bcomp->gr & CCDC_BLK_COMP_MASK) << val 354 drivers/media/platform/davinci/dm355_ccdc.c regw(val, BLKCMP0); val 365 drivers/media/platform/davinci/dm355_ccdc.c u32 val, count = DFC_WRITE_WAIT_COUNT; val 373 drivers/media/platform/davinci/dm355_ccdc.c val = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK; val 374 drivers/media/platform/davinci/dm355_ccdc.c regw(val, DFCMEMCTL); val 400 drivers/media/platform/davinci/dm355_ccdc.c u32 val; val 404 drivers/media/platform/davinci/dm355_ccdc.c val = dfc->gen_dft_en & CCDC_DFCCTL_GDFCEN_MASK; val 409 drivers/media/platform/davinci/dm355_ccdc.c regw(val, DFCCTL); val 416 drivers/media/platform/davinci/dm355_ccdc.c val |= CCDC_DFCCTL_VDFC_DISABLE; val 417 drivers/media/platform/davinci/dm355_ccdc.c val |= (dfc->dft_corr_ctl.vdfcsl & CCDC_DFCCTL_VDFCSL_MASK) << val 419 drivers/media/platform/davinci/dm355_ccdc.c val |= (dfc->dft_corr_ctl.vdfcuda & CCDC_DFCCTL_VDFCUDA_MASK) << val 421 drivers/media/platform/davinci/dm355_ccdc.c val |= (dfc->dft_corr_ctl.vdflsft & CCDC_DFCCTL_VDFLSFT_MASK) << val 423 drivers/media/platform/davinci/dm355_ccdc.c regw(val , DFCCTL); val 426 drivers/media/platform/davinci/dm355_ccdc.c val = CCDC_DFCMEMCTL_DFCMARST_MASK << CCDC_DFCMEMCTL_DFCMARST_SHIFT; val 432 drivers/media/platform/davinci/dm355_ccdc.c val = CCDC_DFCMEMCTL_INC_ADDR; val 433 drivers/media/platform/davinci/dm355_ccdc.c regw(val, DFCMEMCTL); val 440 drivers/media/platform/davinci/dm355_ccdc.c val = regr(DFCCTL) | (CCDC_DFCCTL_VDFCEN_MASK << val 442 drivers/media/platform/davinci/dm355_ccdc.c regw(val, DFCCTL); val 499 drivers/media/platform/davinci/dm355_ccdc.c u32 val; val 501 drivers/media/platform/davinci/dm355_ccdc.c val = (pat0->olop | (pat0->olep << 2) | (pat0->elop << 4) | val 504 drivers/media/platform/davinci/dm355_ccdc.c regw(val, COLPTN); val 513 drivers/media/platform/davinci/dm355_ccdc.c unsigned int val; val 536 drivers/media/platform/davinci/dm355_ccdc.c val = (CCDC_VDHDOUT_INPUT | CCDC_RAW_IP_MODE | CCDC_DATAPOL_NORMAL | val 544 drivers/media/platform/davinci/dm355_ccdc.c val |= (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) | val 553 drivers/media/platform/davinci/dm355_ccdc.c val |= CCDC_DATA_PACK_ENABLE; val 557 drivers/media/platform/davinci/dm355_ccdc.c val |= (config_params->lpf_enable & CCDC_LPF_MASK) << val 561 drivers/media/platform/davinci/dm355_ccdc.c val |= (config_params->datasft & CCDC_DATASFT_MASK) << val 563 drivers/media/platform/davinci/dm355_ccdc.c regw(val , MODESET); val 564 drivers/media/platform/davinci/dm355_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to MODESET...\n", val); val 570 drivers/media/platform/davinci/dm355_ccdc.c val = CCDC_GAMMA_BITS_11_2 << CCDC_GAMMAWD_INPUT_SHIFT | val 575 drivers/media/platform/davinci/dm355_ccdc.c val |= (CCDC_ALAW_ENABLE | val 582 drivers/media/platform/davinci/dm355_ccdc.c val |= ((config_params->mfilt1 << CCDC_MFILT1_SHIFT) | val 585 drivers/media/platform/davinci/dm355_ccdc.c regw(val, GAMMAWD); val 586 drivers/media/platform/davinci/dm355_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to GAMMAWD...\n", val); val 611 drivers/media/platform/davinci/dm355_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting %x to COLPTN...\n", val); val 614 drivers/media/platform/davinci/dm355_ccdc.c val = (config_params->data_offset.horz_offset & CCDC_DATAOFST_MASK) << val 616 drivers/media/platform/davinci/dm355_ccdc.c val |= (config_params->data_offset.vert_offset & CCDC_DATAOFST_MASK) << val 618 drivers/media/platform/davinci/dm355_ccdc.c regw(val, DATAOFST); val 621 drivers/media/platform/davinci/dm355_ccdc.c val = (params->horz_flip_enable & CCDC_HSIZE_FLIP_MASK) << val 627 drivers/media/platform/davinci/dm355_ccdc.c val |= (((params->win.width) + 31) >> 5) & val 636 drivers/media/platform/davinci/dm355_ccdc.c val |= (((params->win.width * 2) + 31) >> 5) & val 643 drivers/media/platform/davinci/dm355_ccdc.c regw(val, HSIZE); val 92 drivers/media/platform/davinci/dm644x_ccdc.c static inline void regw(u32 val, u32 offset) val 94 drivers/media/platform/davinci/dm644x_ccdc.c __raw_writel(val, ccdc_cfg.base_addr + offset); val 122 drivers/media/platform/davinci/dm644x_ccdc.c int val = 0, mid_img = 0; val 143 drivers/media/platform/davinci/dm644x_ccdc.c val = (vert_start << CCDC_VDINT_VDINT0_SHIFT); val 144 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_VDINT); val 155 drivers/media/platform/davinci/dm644x_ccdc.c val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) | val 157 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_VDINT); val 168 drivers/media/platform/davinci/dm644x_ccdc.c unsigned int val = 0; val 170 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_ALAW); val 171 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to ALAW...\n", val); val 172 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_CLAMP); val 173 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to CLAMP...\n", val); val 174 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_DCSUB); val 175 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to DCSUB...\n", val); val 176 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_BLKCMP); val 177 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to BLKCMP...\n", val); val 178 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FPC_ADDR); val 179 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC_ADDR...\n", val); val 180 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FPC); val 181 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC...\n", val); val 182 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FMTCFG); val 183 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMTCFG...\n", val); val 184 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_COLPTN); val 185 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to COLPTN...\n", val); val 186 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FMT_HORZ); val 187 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_HORZ...\n", val); val 188 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FMT_VERT); val 189 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_VERT...\n", val); val 190 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_HSIZE_OFF); val 191 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HSIZE_OFF...\n", val); val 192 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_SDOFST); val 193 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SDOFST...\n", val); val 194 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_VP_OUT); val 195 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VP_OUT...\n", val); val 196 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_SYN_MODE); val 197 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SYN_MODE...\n", val); val 198 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_HORZ_INFO); val 199 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HORZ_INFO...\n", val); val 200 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_VERT_START); val 201 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_START...\n", val); val 202 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_VERT_LINES); val 203 drivers/media/platform/davinci/dm644x_ccdc.c dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_LINES...\n", val); val 325 drivers/media/platform/davinci/dm644x_ccdc.c u32 val; val 329 drivers/media/platform/davinci/dm644x_ccdc.c val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK; val 330 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_DCSUB); val 331 drivers/media/platform/davinci/dm644x_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to DCSUB...\n", val); val 340 drivers/media/platform/davinci/dm644x_ccdc.c val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) | val 347 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_CLAMP); val 348 drivers/media/platform/davinci/dm644x_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to CLAMP...\n", val); val 356 drivers/media/platform/davinci/dm644x_ccdc.c u32 val; val 358 drivers/media/platform/davinci/dm644x_ccdc.c val = ((bcomp->b & CCDC_BLK_COMP_MASK) | val 365 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_BLKCMP); val 378 drivers/media/platform/davinci/dm644x_ccdc.c unsigned int val; val 407 drivers/media/platform/davinci/dm644x_ccdc.c val = ((config_params->alaw.gamma_wd & val 409 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_ALAW); val 410 drivers/media/platform/davinci/dm644x_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to ALAW...\n", val); val 428 drivers/media/platform/davinci/dm644x_ccdc.c val = CCDC_DISABLE_VIDEO_PORT; val 431 drivers/media/platform/davinci/dm644x_ccdc.c val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK) val 434 drivers/media/platform/davinci/dm644x_ccdc.c val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK) val 437 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_FMTCFG); val 439 drivers/media/platform/davinci/dm644x_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMTCFG...\n", val); val 448 drivers/media/platform/davinci/dm644x_ccdc.c val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) << val 451 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_FMT_HORZ); val 453 drivers/media/platform/davinci/dm644x_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_HORZ...\n", val); val 454 drivers/media/platform/davinci/dm644x_ccdc.c val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK) val 457 drivers/media/platform/davinci/dm644x_ccdc.c val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK; val 459 drivers/media/platform/davinci/dm644x_ccdc.c val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK; val 463 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_FMT_VERT); val 465 drivers/media/platform/davinci/dm644x_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_VERT...\n", val); val 506 drivers/media/platform/davinci/dm644x_ccdc.c val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK)) val 509 drivers/media/platform/davinci/dm644x_ccdc.c val = val 514 drivers/media/platform/davinci/dm644x_ccdc.c val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK) val 516 drivers/media/platform/davinci/dm644x_ccdc.c val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK; val 517 drivers/media/platform/davinci/dm644x_ccdc.c regw(val, CCDC_VP_OUT); val 519 drivers/media/platform/davinci/dm644x_ccdc.c dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to VP_OUT...\n", val); val 141 drivers/media/platform/davinci/isif.c static inline void regw(u32 val, u32 offset) val 143 drivers/media/platform/davinci/isif.c __raw_writel(val, isif_cfg.base_addr + offset); val 147 drivers/media/platform/davinci/isif.c static inline u32 reg_modify(u32 mask, u32 val, u32 offset) val 149 drivers/media/platform/davinci/isif.c u32 new_val = (regr(offset) & ~mask) | (val & mask); val 155 drivers/media/platform/davinci/isif.c static inline void regw_lin_tbl(u32 val, u32 offset, int i) val 158 drivers/media/platform/davinci/isif.c __raw_writel(val, isif_cfg.linear_tbl0_addr + offset); val 160 drivers/media/platform/davinci/isif.c __raw_writel(val, isif_cfg.linear_tbl1_addr + offset); val 197 drivers/media/platform/davinci/isif.c u32 val; val 200 drivers/media/platform/davinci/isif.c val = (cul->hcpat_even << CULL_PAT_EVEN_LINE_SHIFT) | cul->hcpat_odd; val 201 drivers/media/platform/davinci/isif.c regw(val, CULH); val 215 drivers/media/platform/davinci/isif.c u32 val; val 217 drivers/media/platform/davinci/isif.c val = (!!gain_off_p->gain_sdram_en << GAIN_SDRAM_EN_SHIFT) | val 224 drivers/media/platform/davinci/isif.c reg_modify(GAIN_OFFSET_EN_MASK, val, CGAMMAWD); val 226 drivers/media/platform/davinci/isif.c val = (gain_off_p->gain.r_ye.integer << GAIN_INTEGER_SHIFT) | val 228 drivers/media/platform/davinci/isif.c regw(val, CRGAIN); val 230 drivers/media/platform/davinci/isif.c val = (gain_off_p->gain.gr_cy.integer << GAIN_INTEGER_SHIFT) | val 232 drivers/media/platform/davinci/isif.c regw(val, CGRGAIN); val 234 drivers/media/platform/davinci/isif.c val = (gain_off_p->gain.gb_g.integer << GAIN_INTEGER_SHIFT) | val 236 drivers/media/platform/davinci/isif.c regw(val, CGBGAIN); val 238 drivers/media/platform/davinci/isif.c val = (gain_off_p->gain.b_mg.integer << GAIN_INTEGER_SHIFT) | val 240 drivers/media/platform/davinci/isif.c regw(val, CBGAIN); val 311 drivers/media/platform/davinci/isif.c u32 val; val 320 drivers/media/platform/davinci/isif.c val = bc->bc_mode_color << ISIF_BC_MODE_COLOR_SHIFT; val 323 drivers/media/platform/davinci/isif.c val = val | 1 | (bc->horz.mode << ISIF_HORZ_BC_MODE_SHIFT); val 325 drivers/media/platform/davinci/isif.c regw(val, CLAMPCFG); val 337 drivers/media/platform/davinci/isif.c val = bc->horz.win_count_calc | val 346 drivers/media/platform/davinci/isif.c regw(val, CLHWIN0); val 355 drivers/media/platform/davinci/isif.c val |= val 358 drivers/media/platform/davinci/isif.c regw(val, CLVWIN0); val 373 drivers/media/platform/davinci/isif.c u32 val, i; val 381 drivers/media/platform/davinci/isif.c val = (linearize->corr_shft << ISIF_LIN_CORRSFT_SHIFT) | 1; val 382 drivers/media/platform/davinci/isif.c regw(val, LINCFG0); val 385 drivers/media/platform/davinci/isif.c val = ((!!linearize->scale_fact.integer) << val 388 drivers/media/platform/davinci/isif.c regw(val, LINCFG1); val 401 drivers/media/platform/davinci/isif.c u32 val, count, retries = loops_per_jiffy / (4000/HZ); val 408 drivers/media/platform/davinci/isif.c val = (vdfc->corr_mode << ISIF_VDFC_CORR_MOD_SHIFT); val 412 drivers/media/platform/davinci/isif.c val |= 1 << ISIF_VDFC_CORR_WHOLE_LN_SHIFT; val 415 drivers/media/platform/davinci/isif.c val |= vdfc->def_level_shift << ISIF_VDFC_LEVEL_SHFT_SHIFT; val 417 drivers/media/platform/davinci/isif.c regw(val, DFCCTL); val 432 drivers/media/platform/davinci/isif.c val = regr(DFCMEMCTL) | (1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT) | 1; val 433 drivers/media/platform/davinci/isif.c regw(val, DFCMEMCTL); val 453 drivers/media/platform/davinci/isif.c val = regr(DFCMEMCTL); val 455 drivers/media/platform/davinci/isif.c val &= ~BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT); val 456 drivers/media/platform/davinci/isif.c val |= 1; val 457 drivers/media/platform/davinci/isif.c regw(val, DFCMEMCTL); val 535 drivers/media/platform/davinci/isif.c u32 val; val 549 drivers/media/platform/davinci/isif.c val = ISIF_YCINSWP_RAW | ISIF_CCDCFG_FIDMD_LATCH_VSYNC | val 553 drivers/media/platform/davinci/isif.c dev_dbg(isif_cfg.dev, "Writing 0x%x to ...CCDCFG \n", val); val 554 drivers/media/platform/davinci/isif.c regw(val, CCDCFG); val 567 drivers/media/platform/davinci/isif.c val = ISIF_VDHDOUT_INPUT | (params->vd_pol << ISIF_VD_POL_SHIFT) | val 576 drivers/media/platform/davinci/isif.c regw(val, MODESET); val 577 drivers/media/platform/davinci/isif.c dev_dbg(isif_cfg.dev, "Writing 0x%x to MODESET...\n", val); val 583 drivers/media/platform/davinci/isif.c val = params->cfa_pat << ISIF_GAMMAWD_CFA_SHIFT; val 587 drivers/media/platform/davinci/isif.c val |= ISIF_ALAW_ENABLE; val 589 drivers/media/platform/davinci/isif.c val |= (params->data_msb << ISIF_ALAW_GAMMA_WD_SHIFT); val 590 drivers/media/platform/davinci/isif.c regw(val, CGAMMAWD); val 594 drivers/media/platform/davinci/isif.c val = BIT(ISIF_DPCM_EN_SHIFT) | val 599 drivers/media/platform/davinci/isif.c regw(val, MISC); val 605 drivers/media/platform/davinci/isif.c val = (params->config_params.col_pat_field0.olop) | val 613 drivers/media/platform/davinci/isif.c regw(val, CCOLP); val 614 drivers/media/platform/davinci/isif.c dev_dbg(isif_cfg.dev, "Writing %x to CCOLP ...\n", val); val 617 drivers/media/platform/davinci/isif.c val = (!!params->horz_flip_en) << ISIF_HSIZE_FLIP_SHIFT; val 621 drivers/media/platform/davinci/isif.c val |= ((params->win.width + 31) >> 5); val 623 drivers/media/platform/davinci/isif.c val |= (((params->win.width + val 626 drivers/media/platform/davinci/isif.c val |= (((params->win.width * 2) + 31) >> 5); val 627 drivers/media/platform/davinci/isif.c regw(val, HSIZE); val 47 drivers/media/platform/davinci/vpbe_display.c int ret, val; val 53 drivers/media/platform/davinci/vpbe_display.c &val); val 59 drivers/media/platform/davinci/vpbe_display.c return val; val 55 drivers/media/platform/davinci/vpbe_osd.c static inline u32 osd_write(struct osd_state *sd, u32 val, u32 offset) val 59 drivers/media/platform/davinci/vpbe_osd.c writel(val, osd->osd_base + offset); val 61 drivers/media/platform/davinci/vpbe_osd.c return val; val 69 drivers/media/platform/davinci/vpbe_osd.c u32 val = readl(addr) | mask; val 71 drivers/media/platform/davinci/vpbe_osd.c writel(val, addr); val 73 drivers/media/platform/davinci/vpbe_osd.c return val; val 81 drivers/media/platform/davinci/vpbe_osd.c u32 val = readl(addr) & ~mask; val 83 drivers/media/platform/davinci/vpbe_osd.c writel(val, addr); val 85 drivers/media/platform/davinci/vpbe_osd.c return val; val 88 drivers/media/platform/davinci/vpbe_osd.c static inline u32 osd_modify(struct osd_state *sd, u32 mask, u32 val, val 94 drivers/media/platform/davinci/vpbe_osd.c u32 new_val = (readl(addr) & ~mask) | (val & mask); val 1480 drivers/media/platform/davinci/vpbe_osd.c static void osd_set_left_margin(struct osd_state *sd, u32 val) val 1482 drivers/media/platform/davinci/vpbe_osd.c osd_write(sd, val, OSD_BASEPX); val 1485 drivers/media/platform/davinci/vpbe_osd.c static void osd_set_top_margin(struct osd_state *sd, u32 val) val 1487 drivers/media/platform/davinci/vpbe_osd.c osd_write(sd, val, OSD_BASEPY); val 77 drivers/media/platform/davinci/vpbe_venc.c static inline u32 venc_write(struct v4l2_subdev *sd, u32 offset, u32 val) val 81 drivers/media/platform/davinci/vpbe_venc.c writel(val, (venc->venc_base + offset)); val 83 drivers/media/platform/davinci/vpbe_venc.c return val; val 87 drivers/media/platform/davinci/vpbe_venc.c u32 val, u32 mask) val 89 drivers/media/platform/davinci/vpbe_venc.c u32 new_val = (venc_read(sd, offset) & ~mask) | (val & mask); val 96 drivers/media/platform/davinci/vpbe_venc.c static inline u32 vdaccfg_write(struct v4l2_subdev *sd, u32 val) val 100 drivers/media/platform/davinci/vpbe_venc.c writel(val, venc->vdaccfg_reg); val 102 drivers/media/platform/davinci/vpbe_venc.c val = readl(venc->vdaccfg_reg); val 104 drivers/media/platform/davinci/vpbe_venc.c return val; val 528 drivers/media/platform/davinci/vpbe_venc.c u32 val; val 532 drivers/media/platform/davinci/vpbe_venc.c val = venc_read(sd, VENC_VSTAT); val 533 drivers/media/platform/davinci/vpbe_venc.c *((int *)arg) = ((val & VENC_VSTAT_FIDST) == val 230 drivers/media/platform/davinci/vpif.c static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val) val 232 drivers/media/platform/davinci/vpif.c if (val) val 124 drivers/media/platform/davinci/vpss.c static inline void bl_regw(u32 val, u32 offset) val 126 drivers/media/platform/davinci/vpss.c __raw_writel(val, oper_cfg.vpss_regs_base0 + offset); val 134 drivers/media/platform/davinci/vpss.c static inline void vpss_regw(u32 val, u32 offset) val 136 drivers/media/platform/davinci/vpss.c __raw_writel(val, oper_cfg.vpss_regs_base1 + offset); val 146 drivers/media/platform/davinci/vpss.c static inline void isp5_write(u32 val, u32 offset) val 148 drivers/media/platform/davinci/vpss.c __raw_writel(val, oper_cfg.vpss_regs_base0 + offset); val 188 drivers/media/platform/davinci/vpss.c u32 mask = 1, val; val 196 drivers/media/platform/davinci/vpss.c val = bl_regr(DM644X_SBL_PCR_VPSS) & mask; val 197 drivers/media/platform/davinci/vpss.c bl_regw(val, DM644X_SBL_PCR_VPSS); val 273 drivers/media/platform/davinci/vpss.c void(*write)(u32 val, u32 offset) = isp5_write; val 365 drivers/media/platform/davinci/vpss.c int val = 0; val 366 drivers/media/platform/davinci/vpss.c val = isp5_read(DM365_ISP5_CCDCMUX); val 368 drivers/media/platform/davinci/vpss.c val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT); val 369 drivers/media/platform/davinci/vpss.c val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT); val 371 drivers/media/platform/davinci/vpss.c isp5_write(val, DM365_ISP5_CCDCMUX); val 560 drivers/media/platform/exynos-gsc/gsc-core.c if (ctx->gsc_ctrls.rotate->val == 90 || val 561 drivers/media/platform/exynos-gsc/gsc-core.c ctx->gsc_ctrls.rotate->val == 270) { val 581 drivers/media/platform/exynos-gsc/gsc-core.c (ctx->gsc_ctrls.rotate->val == 90 || val 582 drivers/media/platform/exynos-gsc/gsc-core.c ctx->gsc_ctrls.rotate->val == 270)) val 646 drivers/media/platform/exynos-gsc/gsc-core.c ctx->gsc_ctrls.rotate->val, ctx->out_path); val 652 drivers/media/platform/exynos-gsc/gsc-core.c if (ctx->gsc_ctrls.rotate->val == 90 || val 653 drivers/media/platform/exynos-gsc/gsc-core.c ctx->gsc_ctrls.rotate->val == 270) { val 711 drivers/media/platform/exynos-gsc/gsc-core.c ctx->hflip = ctrl->val; val 715 drivers/media/platform/exynos-gsc/gsc-core.c ctx->vflip = ctrl->val; val 725 drivers/media/platform/exynos-gsc/gsc-core.c ctx->gsc_ctrls.rotate->val, val 732 drivers/media/platform/exynos-gsc/gsc-core.c ctx->rotation = ctrl->val; val 736 drivers/media/platform/exynos-gsc/gsc-core.c ctx->d_frame.alpha = ctrl->val; val 536 drivers/media/platform/exynos-gsc/gsc-m2m.c ctx->gsc_ctrls.rotate->val, ctx->out_path); val 541 drivers/media/platform/exynos-gsc/gsc-m2m.c sel.r.height, ctx->gsc_ctrls.rotate->val, val 251 drivers/media/platform/exynos-gsc/gsc-regs.c if (ctx->gsc_ctrls.rotate->val == 90 || val 252 drivers/media/platform/exynos-gsc/gsc-regs.c ctx->gsc_ctrls.rotate->val == 270) { val 375 drivers/media/platform/exynos-gsc/gsc-regs.c switch (ctx->gsc_ctrls.rotate->val) { val 383 drivers/media/platform/exynos-gsc/gsc-regs.c if (ctx->gsc_ctrls.hflip->val) val 385 drivers/media/platform/exynos-gsc/gsc-regs.c else if (ctx->gsc_ctrls.vflip->val) val 391 drivers/media/platform/exynos-gsc/gsc-regs.c if (ctx->gsc_ctrls.hflip->val) val 393 drivers/media/platform/exynos-gsc/gsc-regs.c else if (ctx->gsc_ctrls.vflip->val) val 414 drivers/media/platform/exynos-gsc/gsc-regs.c cfg |= GSC_OUT_GLOBAL_ALPHA(ctx->gsc_ctrls.global_alpha->val); val 491 drivers/media/platform/exynos4-is/fimc-core.c effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8; val 492 drivers/media/platform/exynos4-is/fimc-core.c effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff; val 518 drivers/media/platform/exynos4-is/fimc-core.c ctx->hflip = ctrl->val; val 522 drivers/media/platform/exynos4-is/fimc-core.c ctx->vflip = ctrl->val; val 529 drivers/media/platform/exynos4-is/fimc-core.c ctx->d_frame.height, ctrl->val); val 533 drivers/media/platform/exynos4-is/fimc-core.c if ((ctrl->val == 90 || ctrl->val == 270) && val 537 drivers/media/platform/exynos4-is/fimc-core.c ctx->rotation = ctrl->val; val 541 drivers/media/platform/exynos4-is/fimc-core.c ctx->d_frame.alpha = ctrl->val; val 545 drivers/media/platform/exynos4-is/fimc-core.c ret = fimc_set_color_effect(ctx, ctrl->val); val 643 drivers/media/platform/exynos4-is/fimc-core.c fimc_set_color_effect(ctx, ctrls->colorfx->cur.val); val 644 drivers/media/platform/exynos4-is/fimc-core.c ctx->rotation = ctrls->rotate->val; val 645 drivers/media/platform/exynos4-is/fimc-core.c ctx->hflip = ctrls->hflip->val; val 646 drivers/media/platform/exynos4-is/fimc-core.c ctx->vflip = ctrls->vflip->val; val 668 drivers/media/platform/exynos4-is/fimc-core.c if (ctrl->cur.val > ctrl->maximum) val 669 drivers/media/platform/exynos4-is/fimc-core.c ctrl->cur.val = ctrl->maximum; val 320 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val) val 328 drivers/media/platform/exynos4-is/fimc-is-param.c isp->awb.illumination = val; val 347 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val) val 355 drivers/media/platform/exynos4-is/fimc-is-param.c isp->iso.value = val; val 361 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val) val 372 drivers/media/platform/exynos4-is/fimc-is-param.c isp->adjust.contrast = val; val 375 drivers/media/platform/exynos4-is/fimc-is-param.c isp->adjust.saturation = val; val 378 drivers/media/platform/exynos4-is/fimc-is-param.c isp->adjust.sharpness = val; val 381 drivers/media/platform/exynos4-is/fimc-is-param.c isp->adjust.exposure = val; val 384 drivers/media/platform/exynos4-is/fimc-is-param.c isp->adjust.brightness = val; val 387 drivers/media/platform/exynos4-is/fimc-is-param.c isp->adjust.hue = val; val 408 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val) val 419 drivers/media/platform/exynos4-is/fimc-is-param.c isp->metering.cmd = val; val 422 drivers/media/platform/exynos4-is/fimc-is-param.c isp->metering.win_pos_x = val; val 425 drivers/media/platform/exynos4-is/fimc-is-param.c isp->metering.win_pos_y = val; val 428 drivers/media/platform/exynos4-is/fimc-is-param.c isp->metering.win_width = val; val 431 drivers/media/platform/exynos4-is/fimc-is-param.c isp->metering.win_height = val; val 443 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val) val 451 drivers/media/platform/exynos4-is/fimc-is-param.c isp->afc.manual = val; val 457 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_drc_control(struct fimc_is *is, u32 val) val 464 drivers/media/platform/exynos4-is/fimc-is-param.c drc->control.bypass = val; val 469 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_control(struct fimc_is *is, u32 val) val 478 drivers/media/platform/exynos4-is/fimc-is-param.c fd->control.cmd = val; val 484 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_maxface(struct fimc_is *is, u32 val) val 493 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.max_number = val; val 504 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val) val 513 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.roll_angle = val; val 524 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val) val 533 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.yaw_angle = val; val 544 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val) val 553 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.smile_mode = val; val 564 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val) val 573 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.blink_mode = val; val 584 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val) val 593 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.eye_detect = val; val 604 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val) val 613 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.mouth_detect = val; val 624 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_orientation(struct fimc_is *is, u32 val) val 633 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.orientation = val; val 644 drivers/media/platform/exynos4-is/fimc-is-param.c void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val) val 653 drivers/media/platform/exynos4-is/fimc-is-param.c fd->config.orientation_value = val; val 1002 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val); val 1004 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val); val 1005 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val); val 1006 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val); val 1007 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val); val 1008 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_drc_control(struct fimc_is *is, u32 val); val 1009 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_control(struct fimc_is *is, u32 val); val 1010 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_maxface(struct fimc_is *is, u32 val); val 1011 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val); val 1012 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val); val 1013 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val); val 1014 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val); val 1015 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val); val 1016 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val); val 1017 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_orientation(struct fimc_is *is, u32 val); val 1018 drivers/media/platform/exynos4-is/fimc-is-param.h void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val); val 468 drivers/media/platform/exynos4-is/fimc-isp.c bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; val 469 drivers/media/platform/exynos4-is/fimc-isp.c bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; val 507 drivers/media/platform/exynos4-is/fimc-isp.c idx = is->isp.ctrls.iso->val; val 518 drivers/media/platform/exynos4-is/fimc-isp.c unsigned int val; val 522 drivers/media/platform/exynos4-is/fimc-isp.c val = ISP_METERING_COMMAND_AVERAGE; val 525 drivers/media/platform/exynos4-is/fimc-isp.c val = ISP_METERING_COMMAND_CENTER; val 528 drivers/media/platform/exynos4-is/fimc-isp.c val = ISP_METERING_COMMAND_SPOT; val 531 drivers/media/platform/exynos4-is/fimc-isp.c val = ISP_METERING_COMMAND_MATRIX; val 537 drivers/media/platform/exynos4-is/fimc-isp.c __is_set_isp_metering(is, IS_METERING_CONFIG_CMD, val); val 595 drivers/media/platform/exynos4-is/fimc-isp.c ctrl->val); val 600 drivers/media/platform/exynos4-is/fimc-isp.c ctrl->val); val 605 drivers/media/platform/exynos4-is/fimc-isp.c ctrl->val); val 610 drivers/media/platform/exynos4-is/fimc-isp.c ctrl->val); val 615 drivers/media/platform/exynos4-is/fimc-isp.c ctrl->val); val 620 drivers/media/platform/exynos4-is/fimc-isp.c ctrl->val); val 624 drivers/media/platform/exynos4-is/fimc-isp.c ret = __ctrl_set_metering(is, ctrl->val); val 628 drivers/media/platform/exynos4-is/fimc-isp.c ret = __ctrl_set_white_balance(is, ctrl->val); val 637 drivers/media/platform/exynos4-is/fimc-isp.c ret = __ctrl_set_iso(is, ctrl->val); val 641 drivers/media/platform/exynos4-is/fimc-isp.c ret = __ctrl_set_afc(is, ctrl->val); val 645 drivers/media/platform/exynos4-is/fimc-isp.c __ctrl_set_image_effect(is, ctrl->val); val 655 drivers/media/platform/exynos4-is/fimc-isp.c ctrl->name, ctrl->val); val 156 drivers/media/platform/exynos4-is/fimc-lite.c flite_hw_set_test_pattern(fimc, fimc->test_pattern->val); val 238 drivers/media/platform/exynos4-is/fimc-lite.c flite_hw_set_test_pattern(fimc, fimc->test_pattern->val); val 804 drivers/media/platform/exynos4-is/fimc-reg.c unsigned int mask, val, camblk_cfg; val 815 drivers/media/platform/exynos4-is/fimc-reg.c val = 0x1 << (fimc->id + 20); val 817 drivers/media/platform/exynos4-is/fimc-reg.c val = 0; val 820 drivers/media/platform/exynos4-is/fimc-reg.c ret = regmap_update_bits(map, SYSREG_CAMBLK, mask, val); val 826 drivers/media/platform/exynos4-is/fimc-reg.c val |= SYSREG_CAMBLK_FIFORST_ISP; val 827 drivers/media/platform/exynos4-is/fimc-reg.c ret = regmap_update_bits(map, SYSREG_CAMBLK, mask, val); val 292 drivers/media/platform/exynos4-is/mipi-csis.c u32 val = s5pcsis_read(state, S5PCSIS_INTMSK); val 294 drivers/media/platform/exynos4-is/mipi-csis.c val |= state->interrupt_mask; val 296 drivers/media/platform/exynos4-is/mipi-csis.c val &= ~state->interrupt_mask; val 297 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_INTMSK, val); val 302 drivers/media/platform/exynos4-is/mipi-csis.c u32 val = s5pcsis_read(state, S5PCSIS_CTRL); val 304 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET); val 310 drivers/media/platform/exynos4-is/mipi-csis.c u32 val, mask; val 312 drivers/media/platform/exynos4-is/mipi-csis.c val = s5pcsis_read(state, S5PCSIS_CTRL); val 314 drivers/media/platform/exynos4-is/mipi-csis.c val |= S5PCSIS_CTRL_ENABLE; val 316 drivers/media/platform/exynos4-is/mipi-csis.c val &= ~S5PCSIS_CTRL_ENABLE; val 317 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_CTRL, val); val 319 drivers/media/platform/exynos4-is/mipi-csis.c val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); val 320 drivers/media/platform/exynos4-is/mipi-csis.c val &= ~S5PCSIS_DPHYCTRL_ENABLE; val 323 drivers/media/platform/exynos4-is/mipi-csis.c val |= (mask & S5PCSIS_DPHYCTRL_ENABLE); val 325 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); val 332 drivers/media/platform/exynos4-is/mipi-csis.c u32 val; val 338 drivers/media/platform/exynos4-is/mipi-csis.c val = s5pcsis_read(state, S5PCSIS_CONFIG); val 339 drivers/media/platform/exynos4-is/mipi-csis.c val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg; val 340 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_CONFIG, val); val 343 drivers/media/platform/exynos4-is/mipi-csis.c val = (mf->width << 16) | mf->height; val 344 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_RESOL, val); val 349 drivers/media/platform/exynos4-is/mipi-csis.c u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); val 351 drivers/media/platform/exynos4-is/mipi-csis.c val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27); val 352 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); val 357 drivers/media/platform/exynos4-is/mipi-csis.c u32 val; val 359 drivers/media/platform/exynos4-is/mipi-csis.c val = s5pcsis_read(state, S5PCSIS_CONFIG); val 360 drivers/media/platform/exynos4-is/mipi-csis.c val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1); val 361 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_CONFIG, val); val 366 drivers/media/platform/exynos4-is/mipi-csis.c val = s5pcsis_read(state, S5PCSIS_CTRL); val 368 drivers/media/platform/exynos4-is/mipi-csis.c val |= S5PCSIS_CTRL_ALIGN_32BIT; val 370 drivers/media/platform/exynos4-is/mipi-csis.c val &= ~S5PCSIS_CTRL_ALIGN_32BIT; val 372 drivers/media/platform/exynos4-is/mipi-csis.c val &= ~S5PCSIS_CTRL_WCLK_EXTCLK; val 374 drivers/media/platform/exynos4-is/mipi-csis.c val |= S5PCSIS_CTRL_WCLK_EXTCLK; val 375 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_CTRL, val); val 378 drivers/media/platform/exynos4-is/mipi-csis.c val = s5pcsis_read(state, S5PCSIS_CTRL); val 379 drivers/media/platform/exynos4-is/mipi-csis.c s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW); val 1307 drivers/media/platform/imx-pxp.c if (ctrl->val) val 1314 drivers/media/platform/imx-pxp.c if (ctrl->val) val 1321 drivers/media/platform/imx-pxp.c ctx->alpha_component = ctrl->val; val 1618 drivers/media/platform/imx-pxp.c u32 val; val 1625 drivers/media/platform/imx-pxp.c ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val, val 1626 drivers/media/platform/imx-pxp.c val & BM_PXP_CTRL_CLKGATE, 0, 100); val 1573 drivers/media/platform/marvell-ccic/mcam-core.c reg->val = mcam_reg_read(cam, reg->reg); val 1585 drivers/media/platform/marvell-ccic/mcam-core.c mcam_reg_write(cam, reg->reg, reg->val); val 200 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int val) val 202 drivers/media/platform/marvell-ccic/mcam-core.h iowrite32(val, cam->regs + reg); val 213 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int val, unsigned int mask) val 217 drivers/media/platform/marvell-ccic/mcam-core.h v = (v & ~mask) | (val & mask); val 222 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int reg, unsigned int val) val 224 drivers/media/platform/marvell-ccic/mcam-core.h mcam_reg_write_mask(cam, reg, 0, val); val 228 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int reg, unsigned int val) val 230 drivers/media/platform/marvell-ccic/mcam-core.h mcam_reg_write_mask(cam, reg, val, val); val 319 drivers/media/platform/meson/ao-cec-g12a.c int val; val 321 drivers/media/platform/meson/ao-cec-g12a.c regmap_read(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0, &val); val 323 drivers/media/platform/meson/ao-cec-g12a.c return !!(val & (CECB_CLK_CNTL_INPUT_EN | CECB_CLK_CNTL_OUTPUT_EN)); val 430 drivers/media/platform/meson/ao-cec-g12a.c u32 val; val 432 drivers/media/platform/meson/ao-cec-g12a.c ret = regmap_read(ao_cec->regmap_cec, CECB_RX_CNT, &val); val 434 drivers/media/platform/meson/ao-cec-g12a.c ao_cec->rx_msg.len = val; val 440 drivers/media/platform/meson/ao-cec-g12a.c CECB_RX_DATA00 + i, &val); val 442 drivers/media/platform/meson/ao-cec-g12a.c ao_cec->rx_msg.msg[i] = val & 0xff; val 535 drivers/media/platform/meson/ao-cec-g12a.c u32 val; val 539 drivers/media/platform/meson/ao-cec-g12a.c ret = regmap_read(ao_cec->regmap_cec, CECB_LOCK_BUF, &val); val 542 drivers/media/platform/meson/ao-cec-g12a.c if (val & CECB_LOCK_BUF_EN) val 546 drivers/media/platform/meson/ao-cec-g12a.c ret = regmap_read(ao_cec->regmap_cec, CECB_CTRL, &val); val 549 drivers/media/platform/meson/ao-cec-g12a.c if (val & CECB_CTRL_SEND) val 228 drivers/media/platform/meson/ao-cec.c #define writel_bits_relaxed(mask, val, addr) \ val 229 drivers/media/platform/meson/ao-cec.c writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) val 14 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c #define MTK_JPEG_DUNUM_MASK(val) (((val) - 1) & 0x3) val 26 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg) val 28 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c if (val & (align - 1)) { val 246 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c u32 val; val 248 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c val = (uvscale_h << 12) | (uvscale_w << 8) | val 250 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_BRZ_FACTOR); val 313 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c u32 val; val 315 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c val = ((id_y & 0x00FF) << 24) | ((id_u & 0x00FF) << 16) | val 317 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_COMP_ID); val 342 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c u32 val; val 344 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c val = ((id0 & 0x0f) << 8) | ((id1 & 0x0f) << 4) | ((id2 & 0x0f) << 0); val 345 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_QT_ID); val 351 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c u32 val; val 353 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c val = (((mcu_group - 1) & 0x00FF) << 16) | val 356 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_WDMA_CTRL); val 363 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c u32 val; val 369 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c val = 0; val 371 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c val = (y_wh << 8) | (u_wh << 4) | v_wh; val 372 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_DU_NUM); val 57 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h static inline u32 mtk_jpeg_align(u32 val, u32 align) val 59 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h return (val + align - 1) & ~(align - 1); val 310 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c if (ctx->ctrls.rotate->val == 90 || val 311 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ctx->ctrls.rotate->val == 270) { val 331 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c (ctx->ctrls.rotate->val == 90 || val 332 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ctx->ctrls.rotate->val == 270)) val 907 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ctx->ctrls.rotate->val); val 912 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c new_r.height, ctx->ctrls.rotate->val); val 1000 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ctx->hflip = ctrl->val; val 1003 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ctx->vflip = ctrl->val; val 1012 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ctx->ctrls.rotate->val); val 1018 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ctx->rotation = ctrl->val; val 1021 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ctx->d_frame.alpha = ctrl->val; val 138 drivers/media/platform/mtk-mdp/mtk_mdp_regs.c misc->orientation = ctx->ctrls.rotate->val; val 139 drivers/media/platform/mtk-mdp/mtk_mdp_regs.c misc->hflip = ctx->ctrls.hflip->val; val 140 drivers/media/platform/mtk-mdp/mtk_mdp_regs.c misc->vflip = ctx->ctrls.vflip->val; val 147 drivers/media/platform/mtk-mdp/mtk_mdp_regs.c misc->alpha = ctx->ctrls.global_alpha->val; val 1383 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c ctrl->val = ctx->dpb_size; val 1386 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c ctrl->val = 0; val 91 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 92 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->bitrate = ctrl->val; val 97 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 98 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->num_b_frame = ctrl->val; val 102 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 103 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->rc_frame = ctrl->val; val 107 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 108 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->h264_max_qp = ctrl->val; val 112 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 113 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->seq_hdr_mode = ctrl->val; val 117 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 118 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->rc_mb = ctrl->val; val 122 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 123 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->h264_profile = ctrl->val; val 127 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 128 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->h264_level = ctrl->val; val 132 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 133 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->intra_period = ctrl->val; val 138 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c ctrl->val); val 139 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c p->gop_size = ctrl->val; val 183 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c u32 val; val 191 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c val = (1 << 16) + ((seg_id_addr + i) << 2) + j; val 192 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c writel(val, cm + VP8_HW_VLD_ADDR); val 194 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c val = vsi->segment_buf[i][j]; val 195 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c writel(val, cm + VP8_HW_VLD_VALUE); val 204 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c u32 val; val 212 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c val = ((seg_id_addr + i) << 2) + j; val 213 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c writel(val, cm + VP8_HW_VLD_ADDR); val 215 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c val = readl(cm + VP8_HW_VLD_VALUE); val 216 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c vsi->segment_buf[i][j] = val; val 224 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c u32 val = 0; val 236 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c val = readl(misc + VP8_RW_MISC_SRST); val 237 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c writel((val & 0xFFFFFFFE), misc + VP8_RW_MISC_SRST); val 252 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c u32 addr = 0, val = 0; val 259 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c val = *p++; val 260 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c writel(val, hwd + VP8_BSDSET); val 218 drivers/media/platform/mtk-vpu/mtk_vpu.c static inline void vpu_cfg_writel(struct mtk_vpu *vpu, u32 val, u32 offset) val 220 drivers/media/platform/mtk-vpu/mtk_vpu.c writel(val, vpu->reg.cfg + offset); val 869 drivers/media/platform/omap/omap_vout.c int rotation = ctrl->val; val 893 drivers/media/platform/omap/omap_vout.c unsigned int color = ctrl->val; val 914 drivers/media/platform/omap/omap_vout.c unsigned int mirror = ctrl->val; val 1063 drivers/media/platform/omap3isp/isp.c next->val = isp_reg_readl(isp, next->mmio_range, next->reg); val 1078 drivers/media/platform/omap3isp/isp.c isp_reg_writel(isp, next->val, next->mmio_range, next->reg); val 117 drivers/media/platform/omap3isp/isp.h u32 val; val 55 drivers/media/platform/omap3isp/ispccp2.c #define BIT_SET(var, shift, mask, val) \ val 58 drivers/media/platform/omap3isp/ispccp2.c | ((val) << (shift)); \ val 211 drivers/media/platform/omap3isp/ispccp2.c u32 val; val 213 drivers/media/platform/omap3isp/ispccp2.c val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) | val 216 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK, val 218 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_CTRL_IO_OUT_SEL_SHIFT, val 220 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK, val 222 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_CTRL_VP_CLK_POL_SHIFT, val 224 drivers/media/platform/omap3isp/ispccp2.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL); val 226 drivers/media/platform/omap3isp/ispccp2.c val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL); val 227 drivers/media/platform/omap3isp/ispccp2.c if (!(val & ISPCCP2_CTRL_MODE)) { val 256 drivers/media/platform/omap3isp/ispccp2.c u32 val; val 259 drivers/media/platform/omap3isp/ispccp2.c val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL); val 260 drivers/media/platform/omap3isp/ispccp2.c val |= ISPCCP2_CTRL_VP_ONLY_EN; /* Disable the memory write port */ val 265 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_CTRL_VPCLK_DIV_SHIFT, val 269 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT, val 273 drivers/media/platform/omap3isp/ispccp2.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL); val 289 drivers/media/platform/omap3isp/ispccp2.c u32 val, format; val 301 drivers/media/platform/omap3isp/ispccp2.c val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0)) val 306 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0, val 310 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0, val 313 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT, val 317 drivers/media/platform/omap3isp/ispccp2.c BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT, val 320 drivers/media/platform/omap3isp/ispccp2.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0)); val 331 drivers/media/platform/omap3isp/ispccp2.c val = ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ | val 338 drivers/media/platform/omap3isp/ispccp2.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQSTATUS); val 339 drivers/media/platform/omap3isp/ispccp2.c isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQENABLE, val); val 439 drivers/media/platform/omap3isp/ispccp2.c u32 val, hwords; val 465 drivers/media/platform/omap3isp/ispccp2.c val = ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 << val 470 drivers/media/platform/omap3isp/ispccp2.c val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 << val 474 drivers/media/platform/omap3isp/ispccp2.c val |= ISPCCP2_LCM_CTRL_SRC_DPCM_PRED; val 477 drivers/media/platform/omap3isp/ispccp2.c val |= ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 << val 481 drivers/media/platform/omap3isp/ispccp2.c val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 << val 486 drivers/media/platform/omap3isp/ispccp2.c val |= ISPCCP2_LCM_CTRL_BURST_SIZE_32X << val 489 drivers/media/platform/omap3isp/ispccp2.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL); val 308 drivers/media/platform/omap3isp/isppreview.c u32 val; val 312 drivers/media/platform/omap3isp/isppreview.c val = wbal->coef0 << ISPPRV_WBGAIN_COEF0_SHIFT; val 313 drivers/media/platform/omap3isp/isppreview.c val |= wbal->coef1 << ISPPRV_WBGAIN_COEF1_SHIFT; val 314 drivers/media/platform/omap3isp/isppreview.c val |= wbal->coef2 << ISPPRV_WBGAIN_COEF2_SHIFT; val 315 drivers/media/platform/omap3isp/isppreview.c val |= wbal->coef3 << ISPPRV_WBGAIN_COEF3_SHIFT; val 316 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN); val 363 drivers/media/platform/omap3isp/isppreview.c u32 val; val 365 drivers/media/platform/omap3isp/isppreview.c val = (rgbrgb->matrix[0][0] & 0xfff) << ISPPRV_RGB_MAT1_MTX_RR_SHIFT; val 366 drivers/media/platform/omap3isp/isppreview.c val |= (rgbrgb->matrix[0][1] & 0xfff) << ISPPRV_RGB_MAT1_MTX_GR_SHIFT; val 367 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT1); val 369 drivers/media/platform/omap3isp/isppreview.c val = (rgbrgb->matrix[0][2] & 0xfff) << ISPPRV_RGB_MAT2_MTX_BR_SHIFT; val 370 drivers/media/platform/omap3isp/isppreview.c val |= (rgbrgb->matrix[1][0] & 0xfff) << ISPPRV_RGB_MAT2_MTX_RG_SHIFT; val 371 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT2); val 373 drivers/media/platform/omap3isp/isppreview.c val = (rgbrgb->matrix[1][1] & 0xfff) << ISPPRV_RGB_MAT3_MTX_GG_SHIFT; val 374 drivers/media/platform/omap3isp/isppreview.c val |= (rgbrgb->matrix[1][2] & 0xfff) << ISPPRV_RGB_MAT3_MTX_BG_SHIFT; val 375 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT3); val 377 drivers/media/platform/omap3isp/isppreview.c val = (rgbrgb->matrix[2][0] & 0xfff) << ISPPRV_RGB_MAT4_MTX_RB_SHIFT; val 378 drivers/media/platform/omap3isp/isppreview.c val |= (rgbrgb->matrix[2][1] & 0xfff) << ISPPRV_RGB_MAT4_MTX_GB_SHIFT; val 379 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT4); val 381 drivers/media/platform/omap3isp/isppreview.c val = (rgbrgb->matrix[2][2] & 0xfff) << ISPPRV_RGB_MAT5_MTX_BB_SHIFT; val 382 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT5); val 384 drivers/media/platform/omap3isp/isppreview.c val = (rgbrgb->offset[0] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT; val 385 drivers/media/platform/omap3isp/isppreview.c val |= (rgbrgb->offset[1] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT; val 386 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF1); val 388 drivers/media/platform/omap3isp/isppreview.c val = (rgbrgb->offset[2] & 0x3ff) << ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT; val 389 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF2); val 401 drivers/media/platform/omap3isp/isppreview.c u32 val; val 403 drivers/media/platform/omap3isp/isppreview.c val = (csc->matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT; val 404 drivers/media/platform/omap3isp/isppreview.c val |= (csc->matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT; val 405 drivers/media/platform/omap3isp/isppreview.c val |= (csc->matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT; val 406 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC0); val 408 drivers/media/platform/omap3isp/isppreview.c val = (csc->matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT; val 409 drivers/media/platform/omap3isp/isppreview.c val |= (csc->matrix[1][1] & 0x3ff) << ISPPRV_CSC1_GCB_SHIFT; val 410 drivers/media/platform/omap3isp/isppreview.c val |= (csc->matrix[1][2] & 0x3ff) << ISPPRV_CSC1_BCB_SHIFT; val 411 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC1); val 413 drivers/media/platform/omap3isp/isppreview.c val = (csc->matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT; val 414 drivers/media/platform/omap3isp/isppreview.c val |= (csc->matrix[2][1] & 0x3ff) << ISPPRV_CSC2_GCR_SHIFT; val 415 drivers/media/platform/omap3isp/isppreview.c val |= (csc->matrix[2][2] & 0x3ff) << ISPPRV_CSC2_BCR_SHIFT; val 416 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC2); val 418 drivers/media/platform/omap3isp/isppreview.c val = (csc->offset[0] & 0xff) << ISPPRV_CSC_OFFSET_Y_SHIFT; val 419 drivers/media/platform/omap3isp/isppreview.c val |= (csc->offset[1] & 0xff) << ISPPRV_CSC_OFFSET_CB_SHIFT; val 420 drivers/media/platform/omap3isp/isppreview.c val |= (csc->offset[2] & 0xff) << ISPPRV_CSC_OFFSET_CR_SHIFT; val 421 drivers/media/platform/omap3isp/isppreview.c isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC_OFFSET); val 1588 drivers/media/platform/omap3isp/isppreview.c preview_update_brightness(prev, ctrl->val); val 1591 drivers/media/platform/omap3isp/isppreview.c preview_update_contrast(prev, ctrl->val); val 1823 drivers/media/platform/pxa_camera.c reg->val = __raw_readl(pcdev->base + reg->reg); val 1837 drivers/media/platform/pxa_camera.c __raw_writel(reg->val, pcdev->base + reg->reg); val 625 drivers/media/platform/qcom/camss/camss-csid.c u32 val; val 656 drivers/media/platform/qcom/camss/camss-csid.c val = ((CAMSS_CSID_TG_VC_CFG_V_BLANKING & 0xff) << 24) | val 658 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + val 662 drivers/media/platform/qcom/camss/camss-csid.c val = ((num_bytes_per_line & 0x1fff) << 16) | val 664 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + val 670 drivers/media/platform/qcom/camss/camss-csid.c val = dt; val 671 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + val 675 drivers/media/platform/qcom/camss/camss-csid.c val = tg->payload_mode; val 676 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + val 687 drivers/media/platform/qcom/camss/camss-csid.c val = phy->lane_cnt - 1; val 688 drivers/media/platform/qcom/camss/camss-csid.c val |= phy->lane_assign << 4; val 690 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, val 693 drivers/media/platform/qcom/camss/camss-csid.c val = phy->csiphy_id << 17; val 694 drivers/media/platform/qcom/camss/camss-csid.c val |= 0x9; val 696 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, val 707 drivers/media/platform/qcom/camss/camss-csid.c val = readl_relaxed(csid->base + val 709 drivers/media/platform/qcom/camss/camss-csid.c val &= ~(0xff << dt_shift); val 710 drivers/media/platform/qcom/camss/camss-csid.c val |= dt << dt_shift; val 711 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + val 714 drivers/media/platform/qcom/camss/camss-csid.c val = CAMSS_CSID_CID_n_CFG_ISPIF_EN; val 715 drivers/media/platform/qcom/camss/camss-csid.c val |= CAMSS_CSID_CID_n_CFG_RDI_EN; val 716 drivers/media/platform/qcom/camss/camss-csid.c val |= df << CAMSS_CSID_CID_n_CFG_DECODE_FORMAT_SHIFT; val 717 drivers/media/platform/qcom/camss/camss-csid.c val |= CAMSS_CSID_CID_n_CFG_RDI_MODE_RAW_DUMP; val 727 drivers/media/platform/qcom/camss/camss-csid.c val |= CAMSS_CSID_CID_n_CFG_RDI_MODE_PLAIN_PACKING; val 728 drivers/media/platform/qcom/camss/camss-csid.c val |= CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_16; val 729 drivers/media/platform/qcom/camss/camss-csid.c val |= CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_LSB; val 733 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + val 737 drivers/media/platform/qcom/camss/camss-csid.c val = CAMSS_CSID_TG_CTRL_ENABLE; val 738 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + val 743 drivers/media/platform/qcom/camss/camss-csid.c val = CAMSS_CSID_TG_CTRL_DISABLE; val 744 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + val 810 drivers/media/platform/qcom/camss/camss-csid.c if (csid->testgen_mode->cur.val == 0) { val 860 drivers/media/platform/qcom/camss/camss-csid.c if (csid->testgen_mode->cur.val == 0) { val 1064 drivers/media/platform/qcom/camss/camss-csid.c ret = csid_set_test_pattern(csid, ctrl->val); val 1250 drivers/media/platform/qcom/camss/camss-csid.c if (csid->testgen_mode->cur.val != 0) val 90 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c u8 val, l = 0; val 101 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c val = 0x1; val 102 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c val |= lane_mask << 1; val 103 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG); val 105 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c val = cfg->combo_mode << 4; val 106 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); val 158 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c u8 val = readl_relaxed(csiphy->base + val 160 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(val, csiphy->base + val 86 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c u8 val = readl_relaxed(csiphy->base + val 89 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + val 142 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c u8 val, l = 0; val 148 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = BIT(c->clk.pos); val 150 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val |= BIT(c->data[i].pos * 2); val 152 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); val 154 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; val 155 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); val 163 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; val 164 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val |= 0x17; val 165 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); val 167 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT; val 168 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l)); val 170 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = settle_cnt; val 171 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l)); val 173 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM | val 175 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l)); val 177 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT; val 178 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l)); val 180 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT; val 181 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l)); val 183 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP | val 185 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l)); val 187 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP; val 188 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l)); val 190 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP; val 191 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l)); val 193 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL; val 194 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + val 198 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; val 199 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); val 201 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS; val 202 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l)); val 204 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE; val 205 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l)); val 207 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xff; val 208 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11)); val 210 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xff; val 211 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(12)); val 213 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xfb; val 214 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(13)); val 216 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xff; val 217 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(14)); val 219 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0x7f; val 220 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(15)); val 222 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xff; val 223 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(16)); val 225 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xff; val 226 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(17)); val 228 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xef; val 229 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(18)); val 231 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xff; val 232 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(19)); val 234 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xff; val 235 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(20)); val 237 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = 0xff; val 238 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(21)); val 245 drivers/media/platform/qcom/camss/camss-csiphy.c u8 val; val 260 drivers/media/platform/qcom/camss/camss-csiphy.c val = readl_relaxed(csiphy->base_clk_mux); val 262 drivers/media/platform/qcom/camss/camss-csiphy.c val &= ~0xf0; val 263 drivers/media/platform/qcom/camss/camss-csiphy.c val |= cfg->csid_id << 4; val 265 drivers/media/platform/qcom/camss/camss-csiphy.c val &= ~0xf; val 266 drivers/media/platform/qcom/camss/camss-csiphy.c val |= cfg->csid_id; val 268 drivers/media/platform/qcom/camss/camss-csiphy.c writel_relaxed(val, csiphy->base_clk_mux); val 269 drivers/media/platform/qcom/camss/camss-ispif.c u32 val; val 288 drivers/media/platform/qcom/camss/camss-ispif.c val = ISPIF_RST_CMD_0_STROBED_RST_EN | val 306 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0); val 397 drivers/media/platform/qcom/camss/camss-ispif.c u32 val; val 401 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); val 402 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(0xf << (vfe * 8)); val 404 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << (vfe * 8)); val 405 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); val 409 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); val 410 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(0xf << (vfe * 12)); val 412 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << (vfe * 12)); val 413 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); val 417 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); val 418 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(0xf << (4 + (vfe * 8))); val 420 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << (4 + (vfe * 8))); val 421 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); val 425 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); val 426 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(0xf << (4 + (vfe * 12))); val 428 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << (4 + (vfe * 12))); val 429 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); val 433 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); val 434 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(0xf << (8 + (vfe * 12))); val 436 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << (8 + (vfe * 12))); val 437 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); val 456 drivers/media/platform/qcom/camss/camss-ispif.c u32 val = 0; val 460 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + val 464 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + val 468 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + val 472 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + val 476 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + val 481 drivers/media/platform/qcom/camss/camss-ispif.c if ((val & 0xf) != 0xf) { val 483 drivers/media/platform/qcom/camss/camss-ispif.c __func__, val); val 546 drivers/media/platform/qcom/camss/camss-ispif.c u32 val; val 548 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); val 551 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(1) | BIT(0)); val 553 drivers/media/platform/qcom/camss/camss-ispif.c val |= csid; val 556 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(5) | BIT(4)); val 558 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << 4); val 561 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(9) | BIT(8)); val 563 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << 8); val 566 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(13) | BIT(12)); val 568 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << 12); val 571 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(21) | BIT(20)); val 573 drivers/media/platform/qcom/camss/camss-ispif.c val |= (csid << 20); val 577 drivers/media/platform/qcom/camss/camss-ispif.c writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); val 593 drivers/media/platform/qcom/camss/camss-ispif.c u32 val; val 613 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + addr); val 615 drivers/media/platform/qcom/camss/camss-ispif.c val |= cid_mask; val 617 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~cid_mask; val 619 drivers/media/platform/qcom/camss/camss-ispif.c writel(val, ispif->base + addr); val 632 drivers/media/platform/qcom/camss/camss-ispif.c u32 val; val 636 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); val 637 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK; val 639 drivers/media/platform/qcom/camss/camss-ispif.c val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE; val 640 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); val 645 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); val 646 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK; val 648 drivers/media/platform/qcom/camss/camss-ispif.c val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE; val 649 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); val 654 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); val 655 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK; val 657 drivers/media/platform/qcom/camss/camss-ispif.c val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE; val 658 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); val 663 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); val 664 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK; val 666 drivers/media/platform/qcom/camss/camss-ispif.c val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE; val 667 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); val 672 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); val 673 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK; val 675 drivers/media/platform/qcom/camss/camss-ispif.c val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE; val 676 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); val 697 drivers/media/platform/qcom/camss/camss-ispif.c u32 addr, val; val 727 drivers/media/platform/qcom/camss/camss-ispif.c val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid); val 729 drivers/media/platform/qcom/camss/camss-ispif.c val = 0; val 731 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + addr); val 745 drivers/media/platform/qcom/camss/camss-ispif.c u32 *val; val 748 drivers/media/platform/qcom/camss/camss-ispif.c val = &ispif->intf_cmd[vfe].cmd_1; val 749 drivers/media/platform/qcom/camss/camss-ispif.c *val &= ~(0x3 << (vc * 2 + 8)); val 750 drivers/media/platform/qcom/camss/camss-ispif.c *val |= (cmd << (vc * 2 + 8)); val 752 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe)); val 755 drivers/media/platform/qcom/camss/camss-ispif.c val = &ispif->intf_cmd[vfe].cmd_0; val 756 drivers/media/platform/qcom/camss/camss-ispif.c *val &= ~(0x3 << (vc * 2 + intf * 8)); val 757 drivers/media/platform/qcom/camss/camss-ispif.c *val |= (cmd << (vc * 2 + intf * 8)); val 759 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe)); val 290 drivers/media/platform/qcom/camss/camss-vfe-4-1.c int val = 0; val 297 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = CALC_WORD(pixel_per_line, 1, 8); val 303 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = CALC_WORD(pixel_per_line, 2, 8); val 307 drivers/media/platform/qcom/camss/camss-vfe-4-1.c return val; val 634 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 val, even_cfg, odd_cfg; val 638 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; val 639 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); val 641 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; val 642 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); val 770 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | val 774 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); val 776 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | val 780 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); val 785 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; val 788 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); val 789 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); val 790 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); val 791 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); val 792 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); val 793 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); val 794 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); val 805 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 val = VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(wm); val 808 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_set(vfe, VFE_0_CGC_OVERRIDE_1, val); val 810 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_clr(vfe, VFE_0_CGC_OVERRIDE_1, val); val 817 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 val; val 821 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; val 824 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; val 828 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; val 831 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; val 835 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); val 837 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = line->fmt[MSM_VFE_PAD_SINK].width * 2; val 838 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; val 839 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); val 841 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; val 842 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); val 844 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = line->fmt[MSM_VFE_PAD_SINK].height - 1; val 845 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); val 847 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = 0xffffffff; val 848 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); val 850 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = 0xffffffff; val 851 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); val 853 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; val 854 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); val 856 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; val 857 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); val 878 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 val = VFE_0_MODULE_CFG_DEMUX | val 884 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); val 891 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 val; val 895 drivers/media/platform/qcom/camss/camss-vfe-4-1.c val, val 896 drivers/media/platform/qcom/camss/camss-vfe-4-1.c (val & VFE_0_CAMIF_STATUS_HALT), val 326 drivers/media/platform/qcom/camss/camss-vfe-4-7.c int val = 0; val 333 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = CALC_WORD(pixel_per_line, 1, 8); val 339 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = CALC_WORD(pixel_per_line, 2, 8); val 343 drivers/media/platform/qcom/camss/camss-vfe-4-7.c return val; val 631 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 val = VFE_0_MODULE_ZOOM_EN_REALIGN_BUF; val 638 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val); val 640 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val); val 644 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE; val 647 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val |= VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL; val 649 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val |= VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL; val 651 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG); val 737 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 val, even_cfg, odd_cfg; val 741 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; val 742 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); val 744 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; val 745 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); val 873 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | val 877 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); val 879 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | val 883 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); val 888 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; val 891 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); val 892 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); val 893 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); val 894 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); val 895 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); val 896 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); val 897 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); val 903 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 val = VFE_0_BUS_BDG_DS_CFG_0_CFG; val 906 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); val 907 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); val 908 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); val 909 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); val 910 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); val 911 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); val 912 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); val 913 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); val 914 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); val 915 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); val 916 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); val 917 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); val 918 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); val 919 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); val 920 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); val 921 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); val 932 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 val; val 936 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; val 939 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; val 943 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; val 946 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; val 950 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val |= VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN; val 951 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); val 953 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; val 954 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val |= (line->fmt[MSM_VFE_PAD_SINK].height - 1) << 16; val 955 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); val 957 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; val 958 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); val 960 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = line->fmt[MSM_VFE_PAD_SINK].height - 1; val 961 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); val 963 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = 0xffffffff; val 964 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG); val 966 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = 0xffffffff; val 967 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN); val 969 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = 0xffffffff; val 970 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); val 972 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; val 973 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); val 975 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; val 976 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); val 1013 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 val; val 1017 drivers/media/platform/qcom/camss/camss-vfe-4-7.c val, val 1018 drivers/media/platform/qcom/camss/camss-vfe-4-7.c (val & VFE_0_CAMIF_STATUS_HALT), val 1337 drivers/media/platform/qcom/venus/helpers.c u32 val; val 1367 drivers/media/platform/qcom/venus/helpers.c ret = readl_poll_timeout(stat, val, val & BIT(1), 1, 100); val 1373 drivers/media/platform/qcom/venus/helpers.c ret = readl_poll_timeout(stat, val, !(val & BIT(1)), 1, 100); val 518 drivers/media/platform/qcom/venus/hfi_venus.c u32 val; val 522 drivers/media/platform/qcom/venus/hfi_venus.c val = venus_readl(hdev, WRAPPER_CPU_AXI_HALT); val 523 drivers/media/platform/qcom/venus/hfi_venus.c val |= WRAPPER_CPU_AXI_HALT_HALT; val 524 drivers/media/platform/qcom/venus/hfi_venus.c venus_writel(hdev, WRAPPER_CPU_AXI_HALT, val); val 527 drivers/media/platform/qcom/venus/hfi_venus.c val, val 528 drivers/media/platform/qcom/venus/hfi_venus.c val & WRAPPER_CPU_AXI_HALT_STATUS_IDLE, val 540 drivers/media/platform/qcom/venus/hfi_venus.c val = venus_readl(hdev, VBIF_AXI_HALT_CTRL0); val 541 drivers/media/platform/qcom/venus/hfi_venus.c val |= VBIF_AXI_HALT_CTRL0_HALT_REQ; val 542 drivers/media/platform/qcom/venus/hfi_venus.c venus_writel(hdev, VBIF_AXI_HALT_CTRL0, val); val 545 drivers/media/platform/qcom/venus/hfi_venus.c ret = readl_poll_timeout(base + VBIF_AXI_HALT_CTRL1, val, val 546 drivers/media/platform/qcom/venus/hfi_venus.c val & VBIF_AXI_HALT_CTRL1_HALT_ACK, val 1476 drivers/media/platform/qcom/venus/hfi_venus.c bool val; val 1503 drivers/media/platform/qcom/venus/hfi_venus.c ret = readx_poll_timeout(venus_cpu_and_video_core_idle, hdev, val, val, val 1514 drivers/media/platform/qcom/venus/hfi_venus.c ret = readx_poll_timeout(venus_cpu_idle_and_pc_ready, hdev, val, val, val 20 drivers/media/platform/qcom/venus/vdec_ctrls.c ctr->post_loop_deb_mode = ctrl->val; val 25 drivers/media/platform/qcom/venus/vdec_ctrls.c ctr->profile = ctrl->val; val 29 drivers/media/platform/qcom/venus/vdec_ctrls.c ctr->level = ctrl->val; val 55 drivers/media/platform/qcom/venus/vdec_ctrls.c ctrl->val = ctr->profile; val 62 drivers/media/platform/qcom/venus/vdec_ctrls.c ctrl->val = ctr->level; val 65 drivers/media/platform/qcom/venus/vdec_ctrls.c ctrl->val = ctr->post_loop_deb_mode; val 70 drivers/media/platform/qcom/venus/vdec_ctrls.c ctrl->val = HFI_BUFREQ_COUNT_MIN(&bufreq, ver); val 81 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->bitrate_mode = ctrl->val; val 84 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->bitrate = ctrl->val; val 100 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->bitrate_peak = ctrl->val; val 103 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_entropy_mode = ctrl->val; val 106 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->profile.mpeg4 = ctrl->val; val 109 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->profile.h264 = ctrl->val; val 112 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->profile.hevc = ctrl->val; val 115 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->profile.vpx = ctrl->val; val 118 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->level.mpeg4 = ctrl->val; val 121 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->level.h264 = ctrl->val; val 124 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->level.hevc = ctrl->val; val 127 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_i_qp = ctrl->val; val 130 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_p_qp = ctrl->val; val 133 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_b_qp = ctrl->val; val 136 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_min_qp = ctrl->val; val 139 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_max_qp = ctrl->val; val 142 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->multi_slice_mode = ctrl->val; val 145 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->multi_slice_max_bytes = ctrl->val; val 148 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->multi_slice_max_mb = ctrl->val; val 151 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_loop_filter_alpha = ctrl->val; val 154 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_loop_filter_beta = ctrl->val; val 157 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_loop_filter_mode = ctrl->val; val 160 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->header_mode = ctrl->val; val 165 drivers/media/platform/qcom/venus/venc_ctrls.c ret = venc_calc_bpframes(ctrl->val, ctr->num_b_frames, &bframes, val 170 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->gop_size = ctrl->val; val 173 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_i_period = ctrl->val; val 176 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->vp8_min_qp = ctrl->val; val 179 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->vp8_max_qp = ctrl->val; val 182 drivers/media/platform/qcom/venus/venc_ctrls.c ret = venc_calc_bpframes(ctr->gop_size, ctrl->val, &bframes, val 403 drivers/media/platform/rcar-vin/rcar-core.c rvin_set_alpha(vin, ctrl->val); val 1196 drivers/media/platform/rcar_drif.c u32 val; val 1203 drivers/media/platform/rcar_drif.c if (!fwnode_property_read_u32(fwnode, "sync-active", &val)) val 1204 drivers/media/platform/rcar_drif.c sdr->mdr1 |= val ? RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH : val 786 drivers/media/platform/rcar_fdp1.c static void fdp1_write(struct fdp1_dev *fdp1, u32 val, unsigned int reg) val 789 drivers/media/platform/rcar_fdp1.c dprintk(fdp1, "Write 0x%08x to 0x%04x\n", val, reg); val 791 drivers/media/platform/rcar_fdp1.c iowrite32(val, fdp1->regs + reg); val 1690 drivers/media/platform/rcar_fdp1.c ctrl->val = 2; val 1692 drivers/media/platform/rcar_fdp1.c ctrl->val = 1; val 1706 drivers/media/platform/rcar_fdp1.c ctx->alpha = ctrl->val; val 1710 drivers/media/platform/rcar_fdp1.c ctx->deint_mode = ctrl->val; val 480 drivers/media/platform/rcar_jpu.c static void jpu_write(struct jpu *jpu, u32 val, unsigned int reg) val 482 drivers/media/platform/rcar_jpu.c iowrite32(val, jpu->regs + reg); val 900 drivers/media/platform/rcar_jpu.c ctx->compr_quality = ctrl->val; val 189 drivers/media/platform/rockchip/rga/rga-hw.c src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2]; val 190 drivers/media/platform/rockchip/rga/rga-hw.c dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2]; val 191 drivers/media/platform/rockchip/rga/rga-hw.c x_factor.val = dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2]; val 192 drivers/media/platform/rockchip/rga/rga-hw.c y_factor.val = dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2]; val 193 drivers/media/platform/rockchip/rga/rga-hw.c src_vir_info.val = dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2]; val 194 drivers/media/platform/rockchip/rga/rga-hw.c src_act_info.val = dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2]; val 195 drivers/media/platform/rockchip/rga/rga-hw.c dst_vir_info.val = dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2]; val 196 drivers/media/platform/rockchip/rga/rga-hw.c dst_act_info.val = dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2]; val 274 drivers/media/platform/rockchip/rga/rga-hw.c x_factor.val = 0; val 287 drivers/media/platform/rockchip/rga/rga-hw.c y_factor.val = 0; val 332 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2] = x_factor.val; val 333 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2] = y_factor.val; val 334 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = src_vir_info.val; val 335 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = src_act_info.val; val 337 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2] = src_info.val; val 346 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = dst_vir_info.val; val 347 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = dst_act_info.val; val 349 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val; val 360 drivers/media/platform/rockchip/rga/rga-hw.c mode.val = 0; val 361 drivers/media/platform/rockchip/rga/rga-hw.c alpha_ctrl0.val = 0; val 362 drivers/media/platform/rockchip/rga/rga-hw.c alpha_ctrl1.val = 0; val 369 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_ALPHA_CTRL0 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl0.val; val 370 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_ALPHA_CTRL1 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl1.val; val 372 drivers/media/platform/rockchip/rga/rga-hw.c dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) >> 2] = mode.val; val 178 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 193 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 218 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 231 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 243 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 253 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 264 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 274 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 288 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 302 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 325 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 337 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 349 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 366 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 401 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 416 drivers/media/platform/rockchip/rga/rga-hw.h unsigned int val; val 138 drivers/media/platform/rockchip/rga/rga.c ctx->hflip = ctrl->val; val 141 drivers/media/platform/rockchip/rga/rga.c ctx->vflip = ctrl->val; val 144 drivers/media/platform/rockchip/rga/rga.c ctx->rotate = ctrl->val; val 147 drivers/media/platform/rockchip/rga/rga.c ctx->fill_color = ctrl->val; val 105 drivers/media/platform/rockchip/rga/rga.h static inline void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask) val 109 drivers/media/platform/rockchip/rga/rga.h temp |= val & mask; val 1075 drivers/media/platform/s3c-camif/camif-capture.c ctrl->name, ctrl->val); val 1081 drivers/media/platform/s3c-camif/camif-capture.c vp->hflip = ctrl->val; val 1085 drivers/media/platform/s3c-camif/camif-capture.c vp->vflip = ctrl->val; val 1499 drivers/media/platform/s3c-camif/camif-capture.c camif->colorfx = camif->ctrl_colorfx->val; val 1501 drivers/media/platform/s3c-camif/camif-capture.c switch (ctrl->val) { val 1507 drivers/media/platform/s3c-camif/camif-capture.c camif->colorfx_cb = camif->ctrl_colorfx_cbcr->val >> 8; val 1508 drivers/media/platform/s3c-camif/camif-capture.c camif->colorfx_cr = camif->ctrl_colorfx_cbcr->val & 0xff; val 1517 drivers/media/platform/s3c-camif/camif-capture.c camif->test_pattern = camif->ctrl_test_pattern->val; val 182 drivers/media/platform/s5p-g2d/g2d.c if (ctrl->val == V4L2_COLORFX_NEGATIVE) val 189 drivers/media/platform/s5p-g2d/g2d.c ctx->flip = ctx->ctrl_hflip->val | (ctx->ctrl_vflip->val << 1); val 1872 drivers/media/platform/s5p-jpeg/jpeg-core.c ctrl->val = s5p_jpeg_to_user_subsampling(ctx); val 1926 drivers/media/platform/s5p-jpeg/jpeg-core.c ret = s5p_jpeg_adjust_subs_ctrl(ctx, &ctrl->val); val 1941 drivers/media/platform/s5p-jpeg/jpeg-core.c ctx->compr_quality = ctrl->val; val 1944 drivers/media/platform/s5p-jpeg/jpeg-core.c ctx->restart_interval = ctrl->val; val 1947 drivers/media/platform/s5p-jpeg/jpeg-core.c ctx->subsampling = ctrl->val; val 693 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c ctx->display_delay = ctrl->val; val 696 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c ctx->display_delay_enable = ctrl->val; val 699 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c ctx->loop_filter_mpeg4 = ctrl->val; val 702 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c ctx->slice_interface = ctrl->val; val 720 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c ctrl->val = ctx->pb_count; val 732 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c ctrl->val = ctx->pb_count; val 1798 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->gop_size = ctrl->val; val 1801 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->slice_mode = ctrl->val; val 1804 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->slice_mb = ctrl->val; val 1807 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->slice_bit = ctrl->val * 8; val 1810 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->intra_refresh_mb = ctrl->val; val 1813 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->pad = ctrl->val; val 1816 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->pad_luma = (ctrl->val >> 16) & 0xff; val 1817 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->pad_cb = (ctrl->val >> 8) & 0xff; val 1818 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->pad_cr = (ctrl->val >> 0) & 0xff; val 1821 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->rc_frame = ctrl->val; val 1824 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->rc_bitrate = ctrl->val; val 1827 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->rc_reaction_coeff = ctrl->val; val 1830 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c ctx->force_frame_type = ctrl->val; val 1837 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->vbv_size = ctrl->val; val 1840 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->mv_h_range = ctrl->val; val 1843 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->mv_v_range = ctrl->val; val 1846 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.cpb_size = ctrl->val; val 1849 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->seq_hdr_mode = ctrl->val; val 1852 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->frame_skip_mode = ctrl->val; val 1855 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->fixed_target_bit = ctrl->val; val 1858 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->num_b_frame = ctrl->val; val 1861 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c switch (ctrl->val) { val 1886 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.level_v4l2 = ctrl->val; val 1887 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.level = h264_level(ctrl->val); val 1894 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.mpeg4.level_v4l2 = ctrl->val; val 1895 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.mpeg4.level = mpeg4_level(ctrl->val); val 1902 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.loop_filter_mode = ctrl->val; val 1905 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.loop_filter_alpha = ctrl->val; val 1908 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.loop_filter_beta = ctrl->val; val 1911 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.entropy_mode = ctrl->val; val 1914 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.num_ref_pic_4p = ctrl->val; val 1917 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264._8x8_transform = ctrl->val; val 1920 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->rc_mb = ctrl->val; val 1923 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_frame_qp = ctrl->val; val 1926 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_min_qp = ctrl->val; val 1929 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_max_qp = ctrl->val; val 1932 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_p_frame_qp = ctrl->val; val 1935 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_b_frame_qp = ctrl->val; val 1939 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.mpeg4.rc_frame_qp = ctrl->val; val 1943 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.mpeg4.rc_min_qp = ctrl->val; val 1947 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.mpeg4.rc_max_qp = ctrl->val; val 1951 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.mpeg4.rc_p_frame_qp = ctrl->val; val 1955 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.mpeg4.rc_b_frame_qp = ctrl->val; val 1958 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_mb_dark = ctrl->val; val 1961 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_mb_smooth = ctrl->val; val 1964 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_mb_static = ctrl->val; val 1967 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.rc_mb_activity = ctrl->val; val 1970 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.vui_sar = ctrl->val; val 1973 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.vui_sar_idc = vui_sar_idc(ctrl->val); val 1976 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.vui_ext_sar_width = ctrl->val; val 1979 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.vui_ext_sar_height = ctrl->val; val 1982 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.open_gop = !ctrl->val; val 1985 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.h264.open_gop_size = ctrl->val; val 1988 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c switch (ctrl->val) { val 2002 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.mpeg4.quarter_pixel = ctrl->val; val 2005 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.num_partitions = ctrl->val; val 2008 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.imd_4x4 = ctrl->val; val 2011 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.num_ref = ctrl->val; val 2014 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.filter_level = ctrl->val; val 2017 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.filter_sharpness = ctrl->val; val 2020 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.golden_frame_ref_period = ctrl->val; val 2023 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.golden_frame_sel = ctrl->val; val 2026 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.rc_min_qp = ctrl->val; val 2029 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.rc_max_qp = ctrl->val; val 2032 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.rc_frame_qp = ctrl->val; val 2035 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.rc_p_frame_qp = ctrl->val; val 2038 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.vp8.profile = ctrl->val; val 2041 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.rc_frame_qp = ctrl->val; val 2044 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.rc_p_frame_qp = ctrl->val; val 2047 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.rc_b_frame_qp = ctrl->val; val 2050 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.rc_framerate = ctrl->val; val 2053 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.rc_min_qp = ctrl->val; val 2054 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c __enc_update_hevc_qp_ctrls_range(ctx, ctrl->val, val 2058 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.rc_max_qp = ctrl->val; val 2060 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c ctrl->val); val 2063 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.level_v4l2 = ctrl->val; val 2064 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.level = hevc_level(ctrl->val); val 2067 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c switch (ctrl->val) { val 2081 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.tier = ctrl->val; val 2084 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.max_partition_depth = ctrl->val; val 2087 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.num_refs_for_p = ctrl->val; val 2090 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.refreshtype = ctrl->val; val 2093 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.const_intra_period_enable = ctrl->val; val 2096 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.lossless_cu_enable = ctrl->val; val 2099 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.wavefront_enable = ctrl->val; val 2102 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.loopfilter = ctrl->val; val 2105 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_enable = ctrl->val; val 2108 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_type = ctrl->val; val 2111 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.num_hier_layer = ctrl->val; val 2114 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_layer[0] = ctrl->val; val 2117 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_layer[1] = ctrl->val; val 2120 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_layer[2] = ctrl->val; val 2123 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_layer[3] = ctrl->val; val 2126 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_layer[4] = ctrl->val; val 2129 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_layer[5] = ctrl->val; val 2132 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_qp_layer[6] = ctrl->val; val 2135 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_bit_layer[0] = ctrl->val; val 2138 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_bit_layer[1] = ctrl->val; val 2141 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_bit_layer[2] = ctrl->val; val 2144 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_bit_layer[3] = ctrl->val; val 2147 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_bit_layer[4] = ctrl->val; val 2150 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_bit_layer[5] = ctrl->val; val 2153 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.hier_bit_layer[6] = ctrl->val; val 2156 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.general_pb_enable = ctrl->val; val 2159 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.temporal_id_enable = ctrl->val; val 2162 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.strong_intra_smooth = ctrl->val; val 2165 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.intra_pu_split_disable = ctrl->val; val 2168 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.tmv_prediction_disable = !ctrl->val; val 2171 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.max_num_merge_mv = ctrl->val; val 2174 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.encoding_nostartcode_enable = ctrl->val; val 2177 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.refreshperiod = ctrl->val; val 2180 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.lf_beta_offset_div2 = ctrl->val; val 2183 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.lf_tc_offset_div2 = ctrl->val; val 2186 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.size_of_length_field = ctrl->val; val 2189 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val; val 2193 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c ctrl->id, ctrl->val); val 2208 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c ctrl->val = ctx->pb_count; val 2219 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c ctrl->val = ctx->pb_count; val 1354 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c unsigned int val = 0; val 1419 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c val = 0; val 1422 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c val = 2; val 1425 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c val = 4; val 1428 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c val = 8; val 1431 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (val & 0xF) << 3; val 109 drivers/media/platform/seco-cec/seco-cec.c u16 val = 0; val 114 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_STATUS_REG_1, &val); val 118 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_STATUS_REG_1, val); val 123 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); val 128 drivers/media/platform/seco-cec/seco-cec.c val | SECOCEC_ENABLE_REG_1_CEC); val 135 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_STATUS_REG_1, &val); val 136 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_STATUS_REG_1, val); val 139 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); val 140 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_ENABLE_REG_1, val & val 186 drivers/media/platform/seco-cec/seco-cec.c u16 payload_len, payload_id_len, destination, val = 0; val 214 drivers/media/platform/seco-cec/seco-cec.c val = payload_msg[i + 1] << 8; val 217 drivers/media/platform/seco-cec/seco-cec.c val |= payload_msg[i]; val 219 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_WRITE_DATA_00 + i / 2, val); val 262 drivers/media/platform/seco-cec/seco-cec.c u16 val = 0; val 278 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_READ_DATA_LENGTH, &val); val 283 drivers/media/platform/seco-cec/seco-cec.c msg.len = min(val + 1, CEC_MAX_MSG_SIZE); val 286 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_READ_BYTE0, &val); val 291 drivers/media/platform/seco-cec/seco-cec.c msg.msg[0] = val; val 294 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_READ_OPERATION_ID, &val); val 298 drivers/media/platform/seco-cec/seco-cec.c msg.msg[1] = val; val 307 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_READ_DATA_00 + i / 2, &val); val 312 drivers/media/platform/seco-cec/seco-cec.c payload_msg[i] = val & 0x00ff; val 315 drivers/media/platform/seco-cec/seco-cec.c payload_msg[i + 1] = (val & 0xff00) >> 8; val 352 drivers/media/platform/seco-cec/seco-cec.c u16 val; val 375 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_STATUS_REG_1, &val); val 379 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_STATUS_REG_1, val); val 384 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); val 389 drivers/media/platform/seco-cec/seco-cec.c val | SECOCEC_ENABLE_REG_1_IR); val 406 drivers/media/platform/seco-cec/seco-cec.c smb_rd16(SECOCEC_ENABLE_REG_1, &val); val 409 drivers/media/platform/seco-cec/seco-cec.c val & ~SECOCEC_ENABLE_REG_1_IR); val 419 drivers/media/platform/seco-cec/seco-cec.c u16 val, status, key, addr, toggle; val 424 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_IR_READ_DATA, &val); val 428 drivers/media/platform/seco-cec/seco-cec.c key = val & SECOCEC_IR_COMMAND_MASK; val 429 drivers/media/platform/seco-cec/seco-cec.c addr = (val & SECOCEC_IR_ADDRESS_MASK) >> SECOCEC_IR_ADDRESS_SHL; val 430 drivers/media/platform/seco-cec/seco-cec.c toggle = (val & SECOCEC_IR_TOGGLE_MASK) >> SECOCEC_IR_TOGGLE_SHL; val 458 drivers/media/platform/seco-cec/seco-cec.c u16 status_val, cec_val, val = 0; val 483 drivers/media/platform/seco-cec/seco-cec.c val = SECOCEC_STATUS_REG_1_CEC; val 487 drivers/media/platform/seco-cec/seco-cec.c val |= SECOCEC_STATUS_REG_1_IR; val 493 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_STATUS_REG_1, val); val 503 drivers/media/platform/seco-cec/seco-cec.c val = SECOCEC_STATUS_REG_1_CEC | SECOCEC_STATUS_REG_1_IR; val 504 drivers/media/platform/seco-cec/seco-cec.c smb_wr16(SECOCEC_STATUS_REG_1, val); val 579 drivers/media/platform/seco-cec/seco-cec.c u16 val; val 614 drivers/media/platform/seco-cec/seco-cec.c ret = smb_rd16(SECOCEC_VERSION, &val); val 619 drivers/media/platform/seco-cec/seco-cec.c if (val < SECOCEC_LATEST_FW) { val 621 drivers/media/platform/seco-cec/seco-cec.c val, SECOCEC_LATEST_FW); val 687 drivers/media/platform/seco-cec/seco-cec.c u16 val; val 690 drivers/media/platform/seco-cec/seco-cec.c smb_rd16(SECOCEC_ENABLE_REG_1, &val); val 692 drivers/media/platform/seco-cec/seco-cec.c smb_wr16(SECOCEC_ENABLE_REG_1, val & ~SECOCEC_ENABLE_REG_1_IR); val 710 drivers/media/platform/seco-cec/seco-cec.c u16 val; val 715 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_STATUS_REG_1, &val); val 719 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_STATUS_REG_1, val); val 724 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); val 728 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_ENABLE_REG_1, val & val 743 drivers/media/platform/seco-cec/seco-cec.c u16 val; val 748 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_STATUS_REG_1, &val); val 752 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_STATUS_REG_1, val); val 757 drivers/media/platform/seco-cec/seco-cec.c status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); val 761 drivers/media/platform/seco-cec/seco-cec.c status = smb_wr16(SECOCEC_ENABLE_REG_1, val | SECOCEC_ENABLE_REG_1_CEC); val 35 drivers/media/platform/sti/bdisp/bdisp-debug.c static void bdisp_dbg_dump_ins(struct seq_file *s, u32 val) val 37 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "INS\t0x%08X\t", val); val 39 drivers/media/platform/sti/bdisp/bdisp-debug.c switch (val & BLT_INS_S1_MASK) { val 59 drivers/media/platform/sti/bdisp/bdisp-debug.c switch (val & BLT_INS_S2_MASK) { val 73 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_INS_S3_MASK) == BLT_INS_S3_MEM) val 76 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_IVMX) val 78 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_CLUT) val 80 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_SCALE) val 82 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_FLICK) val 84 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_CLIP) val 86 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_CKEY) val 88 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_OVMX) val 90 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_DEI) val 92 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_PMASK) val 94 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_VC1R) val 96 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_ROTATE) val 98 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_GRAD) val 100 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_AQLOCK) val 102 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_PACE) val 104 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_INS_IRQ) val 110 drivers/media/platform/sti/bdisp/bdisp-debug.c static void bdisp_dbg_dump_tty(struct seq_file *s, u32 val) val 112 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "TTY\t0x%08X\t", val); val 113 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "Pitch=%d - ", val & 0xFFFF); val 115 drivers/media/platform/sti/bdisp/bdisp-debug.c switch ((val & BLT_TTY_COL_MASK) >> BLT_TTY_COL_SHIFT) { val 139 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_ALPHA_R) val 141 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_CR_NOT_CB) val 143 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_MB) val 145 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_HSO) val 147 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_VSO) val 149 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_DITHER) val 151 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_CHROMA) val 153 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_BIG_END) val 159 drivers/media/platform/sti/bdisp/bdisp-debug.c static void bdisp_dbg_dump_xy(struct seq_file *s, u32 val, char *name) val 161 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "%s\t0x%08X\t", name, val); val 162 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "(%d,%d)\n", val & 0xFFFF, (val >> 16)); val 165 drivers/media/platform/sti/bdisp/bdisp-debug.c static void bdisp_dbg_dump_sz(struct seq_file *s, u32 val, char *name) val 167 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "%s\t0x%08X\t", name, val); val 168 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "%dx%d\n", val & 0x1FFF, (val >> 16) & 0x1FFF); val 172 drivers/media/platform/sti/bdisp/bdisp-debug.c u32 val, u32 addr, char *name) val 176 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "%s\t0x%08X\t", name, val); val 185 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "Pitch=%d - ", val & 0xFFFF); val 187 drivers/media/platform/sti/bdisp/bdisp-debug.c switch ((val & BLT_TTY_COL_MASK) >> BLT_TTY_COL_SHIFT) { val 211 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_TTY_ALPHA_R) && !s3) val 213 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_S1TY_A1_SUBSET) && !s3) val 215 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_TTY_MB) && !s1) val 217 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_HSO) val 219 drivers/media/platform/sti/bdisp/bdisp-debug.c if (val & BLT_TTY_VSO) val 221 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_S1TY_CHROMA_EXT) && (s1 || s2)) val 223 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_S3TY_BLANK_ACC) && s3) val 225 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BTL_S1TY_SUBBYTE) && !s3) val 227 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_S1TY_RGB_EXP) && !s3) val 229 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_TTY_BIG_END) && !s3) val 236 drivers/media/platform/sti/bdisp/bdisp-debug.c static void bdisp_dbg_dump_fctl(struct seq_file *s, u32 val) val 238 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "FCTL\t0x%08X\t", val); val 240 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_FCTL_Y_HV_SCALE) == BLT_FCTL_Y_HV_SCALE) val 242 drivers/media/platform/sti/bdisp/bdisp-debug.c else if ((val & BLT_FCTL_Y_HV_SCALE) == BLT_FCTL_Y_HV_SAMPLE) val 245 drivers/media/platform/sti/bdisp/bdisp-debug.c if ((val & BLT_FCTL_HV_SCALE) == BLT_FCTL_HV_SCALE) val 247 drivers/media/platform/sti/bdisp/bdisp-debug.c else if ((val & BLT_FCTL_HV_SCALE) == BLT_FCTL_HV_SAMPLE) val 253 drivers/media/platform/sti/bdisp/bdisp-debug.c static void bdisp_dbg_dump_rsf(struct seq_file *s, u32 val, char *name) val 257 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "%s\t0x%08X\t", name, val); val 259 drivers/media/platform/sti/bdisp/bdisp-debug.c if (!val) val 262 drivers/media/platform/sti/bdisp/bdisp-debug.c inc = val & 0xFFFF; val 265 drivers/media/platform/sti/bdisp/bdisp-debug.c inc = val >> 16; val 272 drivers/media/platform/sti/bdisp/bdisp-debug.c static void bdisp_dbg_dump_rzi(struct seq_file *s, u32 val, char *name) val 274 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "%s\t0x%08X\t", name, val); val 276 drivers/media/platform/sti/bdisp/bdisp-debug.c if (!val) val 279 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "H: init=%d repeat=%d - ", val & 0x3FF, (val >> 12) & 7); val 280 drivers/media/platform/sti/bdisp/bdisp-debug.c val >>= 16; val 281 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "V: init=%d repeat=%d", val & 0x3FF, (val >> 12) & 7); val 395 drivers/media/platform/sti/bdisp/bdisp-debug.c u32 *val; val 409 drivers/media/platform/sti/bdisp/bdisp-debug.c val = (u32 *)node; val 411 drivers/media/platform/sti/bdisp/bdisp-debug.c seq_printf(s, "0x%08X\n", *val++); val 375 drivers/media/platform/sti/bdisp/bdisp-v4l2.c ctx->hflip = ctrl->val; val 378 drivers/media/platform/sti/bdisp/bdisp-v4l2.c ctx->vflip = ctrl->val; val 159 drivers/media/platform/sti/delta/delta-v4l2.c static void delta_push_dts(struct delta_ctx *ctx, u64 val) val 173 drivers/media/platform/sti/delta/delta-v4l2.c dts->val = val; val 177 drivers/media/platform/sti/delta/delta-v4l2.c static void delta_pop_dts(struct delta_ctx *ctx, u64 *val) val 189 drivers/media/platform/sti/delta/delta-v4l2.c *val = 0; val 196 drivers/media/platform/sti/delta/delta-v4l2.c *val = dts->val; val 200 drivers/media/platform/sti/delta/delta.h u64 val; val 623 drivers/media/platform/sti/hva/hva-v4l2.c ctrl->id, ctrl->val); val 627 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.bitrate_mode = ctrl->val; val 630 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.gop_size = ctrl->val; val 633 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.bitrate = ctrl->val; val 636 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.aspect = ctrl->val; val 639 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.profile = ctrl->val; val 643 drivers/media/platform/sti/hva/hva-v4l2.c v4l2_ctrl_get_menu(ctrl->id)[ctrl->val]); val 646 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.level = ctrl->val; val 650 drivers/media/platform/sti/hva/hva-v4l2.c v4l2_ctrl_get_menu(ctrl->id)[ctrl->val]); val 653 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.entropy_mode = ctrl->val; val 656 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.cpb_size = ctrl->val; val 659 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.dct8x8 = ctrl->val; val 662 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.qpmin = ctrl->val; val 665 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.qpmax = ctrl->val; val 668 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.vui_sar = ctrl->val; val 671 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.vui_sar_idc = ctrl->val; val 674 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.sei_fp = ctrl->val; val 677 drivers/media/platform/sti/hva/hva-v4l2.c ctx->ctrls.sei_fp_type = ctrl->val; val 133 drivers/media/platform/stm32/stm32-cec.c u32 val; val 135 drivers/media/platform/stm32/stm32-cec.c regmap_read(cec->regmap, CEC_RXDR, &val); val 136 drivers/media/platform/stm32/stm32-cec.c cec->rx_msg.msg[cec->rx_msg.len++] = val & 0xFF; val 198 drivers/media/platform/stm32/stm32-cec.c u32 val; val 201 drivers/media/platform/stm32/stm32-cec.c regmap_read_poll_timeout(cec->regmap, CEC_CR, val, !(val & TXSOM), val 188 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) val 190 drivers/media/platform/stm32/stm32-dcmi.c writel_relaxed(val, base + reg); val 729 drivers/media/platform/stm32/stm32-dcmi.c u32 val = 0; val 755 drivers/media/platform/stm32/stm32-dcmi.c val |= CR_EDM_0 | CR_EDM_1; val 758 drivers/media/platform/stm32/stm32-dcmi.c val |= CR_EDM_1; val 761 drivers/media/platform/stm32/stm32-dcmi.c val |= CR_EDM_0; val 770 drivers/media/platform/stm32/stm32-dcmi.c val |= CR_VSPOL; val 774 drivers/media/platform/stm32/stm32-dcmi.c val |= CR_HSPOL; val 778 drivers/media/platform/stm32/stm32-dcmi.c val |= CR_PCKPOL; val 780 drivers/media/platform/stm32/stm32-dcmi.c reg_write(dcmi->regs, DCMI_CR, val); val 466 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c u32 val; val 475 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c val = get_csi_input_format(sdev, csi->config.code, val 477 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c cfg |= CSI_CH_CFG_INPUT_FMT(val); val 479 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c val = get_csi_output_format(sdev, csi->config.pixelformat, val 481 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c cfg |= CSI_CH_CFG_OUTPUT_FMT(val); val 483 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c val = get_csi_input_seq(sdev, csi->config.code, val 485 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c cfg |= CSI_CH_CFG_INPUT_SEQ(val); val 57 drivers/media/platform/tegra-cec/tegra_cec.c static inline void cec_write(struct tegra_cec *cec, u32 reg, u32 val) val 59 drivers/media/platform/tegra-cec/tegra_cec.c writel(val, cec->cec_base + reg); val 77 drivers/media/platform/ti-vpe/cal.c #define reg_write(dev, offset, val) iowrite32(val, dev->base + offset) val 82 drivers/media/platform/ti-vpe/cal.c u32 val = reg_read(dev, offset); \ val 83 drivers/media/platform/ti-vpe/cal.c set_field(&val, field, mask); \ val 84 drivers/media/platform/ti-vpe/cal.c reg_write(dev, offset, val); } val 353 drivers/media/platform/ti-vpe/cal.c u32 val = *valp; val 355 drivers/media/platform/ti-vpe/cal.c val &= ~mask; val 356 drivers/media/platform/ti-vpe/cal.c val |= (field << __ffs(mask)) & mask; val 357 drivers/media/platform/ti-vpe/cal.c *valp = val; val 388 drivers/media/platform/ti-vpe/cal.c u32 val; val 395 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL); val 397 drivers/media/platform/ti-vpe/cal.c set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK); val 398 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0, CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK); val 400 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0xf, CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK); val 401 drivers/media/platform/ti-vpe/cal.c set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_MODE_MASK); val 403 drivers/media/platform/ti-vpe/cal.c set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK); val 404 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0, CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK); val 406 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0x3, CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK); val 407 drivers/media/platform/ti-vpe/cal.c set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_MODE_MASK); val 409 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val); val 414 drivers/media/platform/ti-vpe/cal.c u32 val; val 421 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL); val 423 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK); val 425 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK); val 426 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val); val 538 drivers/media/platform/ti-vpe/cal.c u32 val; val 541 drivers/media/platform/ti-vpe/cal.c val = 0; val 542 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_HL_IRQ_CLEAR, CAL_HL_IRQ_MASK(ctx->csi2_port)); val 543 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(2), val); val 545 drivers/media/platform/ti-vpe/cal.c val = 0; val 546 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_HL_IRQ_CLEAR, CAL_HL_IRQ_MASK(ctx->csi2_port)); val 547 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(3), val); val 555 drivers/media/platform/ti-vpe/cal.c u32 val; val 557 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)); val 558 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_GEN_ENABLE, val 560 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_GEN_ENABLE, val 562 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_GEN_DISABLE, val 564 drivers/media/platform/ti-vpe/cal.c set_field(&val, 407, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK); val 565 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val); val 569 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); val 570 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL, val 572 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON, val 574 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); val 586 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev, CAL_CTRL); val 587 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_CTRL_BURSTSIZE_BURST128, CAL_CTRL_BURSTSIZE_MASK); val 588 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0xF, CAL_CTRL_TAGCNT_MASK); val 589 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED, val 591 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0xFF, CAL_CTRL_MFLAGL_MASK); val 592 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0xFF, CAL_CTRL_MFLAGH_MASK); val 593 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_CTRL, val); val 599 drivers/media/platform/ti-vpe/cal.c u32 val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); val 606 drivers/media/platform/ti-vpe/cal.c set_field(&val, mipi_csi2->clock_lane + 1, lane_mask); val 607 drivers/media/platform/ti-vpe/cal.c set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask); val 615 drivers/media/platform/ti-vpe/cal.c set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); val 616 drivers/media/platform/ti-vpe/cal.c set_field(&val, mipi_csi2->lane_polarities[lane + 1], val 620 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); val 622 drivers/media/platform/ti-vpe/cal.c ctx->csi2_port, val); val 639 drivers/media/platform/ti-vpe/cal.c u32 val; val 641 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev, CAL_CSI2_CTX0(ctx->csi2_port)); val 642 drivers/media/platform/ti-vpe/cal.c set_field(&val, ctx->csi2_port, CAL_CSI2_CTX_CPORT_MASK); val 651 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0x1, CAL_CSI2_CTX_DT_MASK); val 653 drivers/media/platform/ti-vpe/cal.c set_field(&val, ctx->virtual_channel, CAL_CSI2_CTX_VC_MASK); val 655 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0, CAL_CSI2_CTX_LINES_MASK); val 656 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK); val 657 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE, val 659 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_CSI2_CTX0(ctx->csi2_port), val); val 666 drivers/media/platform/ti-vpe/cal.c u32 val; val 668 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev, CAL_PIX_PROC(ctx->csi2_port)); val 669 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_PIX_PROC_EXTRACT_B8, CAL_PIX_PROC_EXTRACT_MASK); val 670 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK); val 671 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK); val 672 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_PIX_PROC_PACK_B8, CAL_PIX_PROC_PACK_MASK); val 673 drivers/media/platform/ti-vpe/cal.c set_field(&val, ctx->csi2_port, CAL_PIX_PROC_CPORT_MASK); val 674 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_GEN_ENABLE, CAL_PIX_PROC_EN_MASK); val 675 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_PIX_PROC(ctx->csi2_port), val); val 683 drivers/media/platform/ti-vpe/cal.c u32 val; val 685 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port)); val 686 drivers/media/platform/ti-vpe/cal.c set_field(&val, ctx->csi2_port, CAL_WR_DMA_CTRL_CPORT_MASK); val 687 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT, val 689 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST, val 691 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR, val 693 drivers/media/platform/ti-vpe/cal.c set_field(&val, CAL_GEN_ENABLE, CAL_WR_DMA_CTRL_STALL_RD_MASK); val 694 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port), val); val 709 drivers/media/platform/ti-vpe/cal.c val = reg_read(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port)); val 711 drivers/media/platform/ti-vpe/cal.c set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK); val 717 drivers/media/platform/ti-vpe/cal.c set_field(&val, (width / 8), CAL_WR_DMA_XSIZE_MASK); val 718 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port), val); val 152 drivers/media/platform/ti-vpe/sc.c u32 val; val 170 drivers/media/platform/ti-vpe/sc.c val = sc_reg0[0]; val 173 drivers/media/platform/ti-vpe/sc.c val &= ~(CFG_SELFGEN_FID | CFG_TRIM | CFG_ENABLE_SIN2_VER_INTP | val 179 drivers/media/platform/ti-vpe/sc.c val |= CFG_SC_BYPASS; val 180 drivers/media/platform/ti-vpe/sc.c sc_reg0[0] = val; val 185 drivers/media/platform/ti-vpe/sc.c val |= CFG_LINEAR; val 192 drivers/media/platform/ti-vpe/sc.c val |= CFG_DCM_4X; val 195 drivers/media/platform/ti-vpe/sc.c val |= CFG_DCM_2X; val 215 drivers/media/platform/ti-vpe/sc.c val |= CFG_USE_RAV; val 251 drivers/media/platform/ti-vpe/sc.c sc_reg0[0] = val; val 294 drivers/media/platform/ti-vpe/vpdma.c u32 val = read_reg(vpdma, offset); val 296 drivers/media/platform/ti-vpe/vpdma.c val &= ~(mask << shift); val 297 drivers/media/platform/ti-vpe/vpdma.c val |= (field & mask) << shift; val 299 drivers/media/platform/ti-vpe/vpdma.c write_reg(vpdma, offset, val); val 981 drivers/media/platform/ti-vpe/vpdma.c u32 val; val 983 drivers/media/platform/ti-vpe/vpdma.c val = read_reg(vpdma, reg_addr); val 985 drivers/media/platform/ti-vpe/vpdma.c val |= (1 << (list_num * 2)); val 987 drivers/media/platform/ti-vpe/vpdma.c val &= ~(1 << (list_num * 2)); val 988 drivers/media/platform/ti-vpe/vpdma.c write_reg(vpdma, reg_addr, val); val 461 drivers/media/platform/ti-vpe/vpe.c u32 val = *valp; val 463 drivers/media/platform/ti-vpe/vpe.c val &= ~(mask << shift); val 464 drivers/media/platform/ti-vpe/vpe.c val |= (field & mask) << shift; val 465 drivers/media/platform/ti-vpe/vpe.c *valp = val; val 471 drivers/media/platform/ti-vpe/vpe.c u32 val = read_reg(dev, offset); val 473 drivers/media/platform/ti-vpe/vpe.c write_field(&val, field, mask, shift); val 475 drivers/media/platform/ti-vpe/vpe.c write_reg(dev, offset, val); val 614 drivers/media/platform/ti-vpe/vpe.c u32 val = 0; val 617 drivers/media/platform/ti-vpe/vpe.c val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE; val 618 drivers/media/platform/ti-vpe/vpe.c write_reg(dev, VPE_CLK_ENABLE, val); val 751 drivers/media/platform/ti-vpe/vpe.c u32 val = 0; val 754 drivers/media/platform/ti-vpe/vpe.c val |= VPE_RGB_OUT_SELECT; val 758 drivers/media/platform/ti-vpe/vpe.c val |= VPE_COLOR_SEPARATE_422; val 764 drivers/media/platform/ti-vpe/vpe.c val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER; val 767 drivers/media/platform/ti-vpe/vpe.c val |= VPE_DS_BYPASS; val 769 drivers/media/platform/ti-vpe/vpe.c mmr_adb->out_fmt_reg[0] = val; val 785 drivers/media/platform/ti-vpe/vpe.c u32 val = 0; val 795 drivers/media/platform/ti-vpe/vpe.c val = VPE_DEI_INTERLACE_BYPASS; val 800 drivers/media/platform/ti-vpe/vpe.c val |= (src_h << VPE_DEI_HEIGHT_SHIFT) | val 804 drivers/media/platform/ti-vpe/vpe.c *dei_mmr0 = val; val 1959 drivers/media/platform/ti-vpe/vpe.c ctx->bufs_per_job = ctrl->val; val 1852 drivers/media/platform/vicodec/vicodec-core.c ctx->state.gop_size = ctrl->val; val 1855 drivers/media/platform/vicodec/vicodec-core.c ctx->state.i_frame_qp = ctrl->val; val 1858 drivers/media/platform/vicodec/vicodec-core.c ctx->state.p_frame_qp = ctrl->val; val 922 drivers/media/platform/vim2m.c if (ctrl->val) val 929 drivers/media/platform/vim2m.c if (ctrl->val) val 936 drivers/media/platform/vim2m.c ctx->transtime = ctrl->val; val 942 drivers/media/platform/vim2m.c ctx->translen = ctrl->val; val 258 drivers/media/platform/vimc/vimc-sensor.c tpg_s_pattern(&vsen->tpg, ctrl->val); val 261 drivers/media/platform/vimc/vimc-sensor.c tpg_s_hflip(&vsen->tpg, ctrl->val); val 264 drivers/media/platform/vimc/vimc-sensor.c tpg_s_vflip(&vsen->tpg, ctrl->val); val 267 drivers/media/platform/vimc/vimc-sensor.c tpg_s_brightness(&vsen->tpg, ctrl->val); val 270 drivers/media/platform/vimc/vimc-sensor.c tpg_s_contrast(&vsen->tpg, ctrl->val); val 273 drivers/media/platform/vimc/vimc-sensor.c tpg_s_hue(&vsen->tpg, ctrl->val); val 276 drivers/media/platform/vimc/vimc-sensor.c tpg_s_saturation(&vsen->tpg, ctrl->val); val 301 drivers/media/platform/vivid/vivid-ctrls.c dev->gain->val = (jiffies_to_msecs(jiffies) / 1000) & 0xff; val 313 drivers/media/platform/vivid/vivid-ctrls.c dev->input_brightness[dev->input] = ctrl->val - dev->input * 128; val 317 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_contrast(&dev->tpg, ctrl->val); val 320 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_saturation(&dev->tpg, ctrl->val); val 323 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_hue(&dev->tpg, ctrl->val); val 326 drivers/media/platform/vivid/vivid-ctrls.c dev->hflip = ctrl->val; val 330 drivers/media/platform/vivid/vivid-ctrls.c dev->vflip = ctrl->val; val 334 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_alpha_component(&dev->tpg, ctrl->val); val 367 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_pattern(&dev->tpg, ctrl->val); val 370 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_colorspace(&dev->tpg, colorspaces[ctrl->val]); val 377 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_xfer_func(&dev->tpg, ctrl->val); val 384 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_ycbcr_enc(&dev->tpg, ctrl->val); val 391 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_hsv_enc(&dev->tpg, ctrl->val ? V4L2_HSV_ENC_256 : val 399 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_quantization(&dev->tpg, ctrl->val); val 408 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_rgb_range(&dev->tpg, ctrl->val); val 411 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_real_rgb_range(&dev->tpg, ctrl->val ? val 415 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_alpha_mode(&dev->tpg, ctrl->val); val 418 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_mv_hor_mode(&dev->tpg, ctrl->val); val 421 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_mv_vert_mode(&dev->tpg, ctrl->val); val 424 drivers/media/platform/vivid/vivid-ctrls.c dev->osd_mode = ctrl->val; val 427 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_perc_fill(&dev->tpg, ctrl->val); val 429 drivers/media/platform/vivid/vivid-ctrls.c dev->must_blank[i] = ctrl->val < 100; val 432 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_insert_sav(&dev->tpg, ctrl->val); val 435 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_insert_eav(&dev->tpg, ctrl->val); val 438 drivers/media/platform/vivid/vivid-ctrls.c dev->sensor_hflip = ctrl->val; val 442 drivers/media/platform/vivid/vivid-ctrls.c dev->sensor_vflip = ctrl->val; val 446 drivers/media/platform/vivid/vivid-ctrls.c dev->reduced_fps = ctrl->val; val 450 drivers/media/platform/vivid/vivid-ctrls.c dev->has_crop_cap = ctrl->val; val 454 drivers/media/platform/vivid/vivid-ctrls.c dev->has_compose_cap = ctrl->val; val 458 drivers/media/platform/vivid/vivid-ctrls.c dev->has_scaler_cap = ctrl->val; val 462 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_show_border(&dev->tpg, ctrl->val); val 465 drivers/media/platform/vivid/vivid-ctrls.c tpg_s_show_square(&dev->tpg, ctrl->val); val 468 drivers/media/platform/vivid/vivid-ctrls.c dev->std_aspect_ratio[dev->input] = ctrl->val; val 473 drivers/media/platform/vivid/vivid-ctrls.c dev->ctrl_dv_timings_signal_mode->val; val 474 drivers/media/platform/vivid/vivid-ctrls.c dev->query_dv_timings[dev->input] = dev->ctrl_dv_timings->val; val 496 drivers/media/platform/vivid/vivid-ctrls.c dev->dv_timings_aspect_ratio[dev->input] = ctrl->val; val 500 drivers/media/platform/vivid/vivid-ctrls.c dev->tstamp_src_is_soe = ctrl->val; val 506 drivers/media/platform/vivid/vivid-ctrls.c dev->edid_max_blocks = ctrl->val; val 871 drivers/media/platform/vivid/vivid-ctrls.c dev->loop_video = ctrl->val; val 902 drivers/media/platform/vivid/vivid-ctrls.c dev->vbi_cap_interlaced = ctrl->val; val 933 drivers/media/platform/vivid/vivid-ctrls.c dev->has_crop_out = ctrl->val; val 937 drivers/media/platform/vivid/vivid-ctrls.c dev->has_compose_out = ctrl->val; val 941 drivers/media/platform/vivid/vivid-ctrls.c dev->has_scaler_out = ctrl->val; val 945 drivers/media/platform/vivid/vivid-ctrls.c dev->dvi_d_out = ctrl->val == V4L2_DV_TX_MODE_DVI_D; val 967 drivers/media/platform/vivid/vivid-ctrls.c dev->display_present[dev->output] = ctrl->val; val 986 drivers/media/platform/vivid/vivid-ctrls.c if (ctrl->val && dev->edid_blocks) val 1054 drivers/media/platform/vivid/vivid-ctrls.c dev->perc_dropped_buffers = ctrl->val; val 1081 drivers/media/platform/vivid/vivid-ctrls.c dev->seq_wrap = ctrl->val; val 1084 drivers/media/platform/vivid/vivid-ctrls.c dev->time_wrap = ctrl->val; val 1085 drivers/media/platform/vivid/vivid-ctrls.c if (ctrl->val == 0) { val 1190 drivers/media/platform/vivid/vivid-ctrls.c dev->ctrl_std_signal_mode->val; val 1193 drivers/media/platform/vivid/vivid-ctrls.c vivid_standard[dev->ctrl_standard->val]; val 1248 drivers/media/platform/vivid/vivid-ctrls.c dev->radio_rx_hw_seek_mode = ctrl->val; val 1251 drivers/media/platform/vivid/vivid-ctrls.c dev->radio_rx_hw_seek_prog_lim = ctrl->val; val 1254 drivers/media/platform/vivid/vivid-ctrls.c dev->rds_gen.use_rbds = ctrl->val; val 1257 drivers/media/platform/vivid/vivid-ctrls.c dev->radio_rx_rds_controls = ctrl->val; val 1278 drivers/media/platform/vivid/vivid-ctrls.c dev->radio_rx_rds_enabled = ctrl->val; val 1346 drivers/media/platform/vivid/vivid-ctrls.c dev->radio_tx_rds_controls = ctrl->val; val 1354 drivers/media/platform/vivid/vivid-ctrls.c v4l2_ctrl_s_ctrl(dev->radio_rx_rds_pty, ctrl->val); val 1366 drivers/media/platform/vivid/vivid-ctrls.c v4l2_ctrl_s_ctrl(dev->radio_rx_rds_ta, ctrl->val); val 1370 drivers/media/platform/vivid/vivid-ctrls.c v4l2_ctrl_s_ctrl(dev->radio_rx_rds_tp, ctrl->val); val 1374 drivers/media/platform/vivid/vivid-ctrls.c v4l2_ctrl_s_ctrl(dev->radio_rx_rds_ms, ctrl->val); val 1403 drivers/media/platform/vivid/vivid-ctrls.c dev->sdr_fm_deviation = ctrl->val; val 500 drivers/media/platform/vivid/vivid-kthread-cap.c dev->brightness->cur.val, val 501 drivers/media/platform/vivid/vivid-kthread-cap.c dev->contrast->cur.val, val 502 drivers/media/platform/vivid/vivid-kthread-cap.c dev->saturation->cur.val, val 503 drivers/media/platform/vivid/vivid-kthread-cap.c dev->hue->cur.val); val 507 drivers/media/platform/vivid/vivid-kthread-cap.c dev->autogain->cur.val, gain, dev->alpha->cur.val); val 513 drivers/media/platform/vivid/vivid-kthread-cap.c dev->volume->cur.val, dev->mute->cur.val); val 518 drivers/media/platform/vivid/vivid-kthread-cap.c dev->int32->cur.val, val 520 drivers/media/platform/vivid/vivid-kthread-cap.c dev->bitmask->cur.val); val 523 drivers/media/platform/vivid/vivid-kthread-cap.c dev->boolean->cur.val, val 524 drivers/media/platform/vivid/vivid-kthread-cap.c dev->menu->qmenu[dev->menu->cur.val], val 528 drivers/media/platform/vivid/vivid-kthread-cap.c dev->int_menu->qmenu_int[dev->int_menu->cur.val], val 529 drivers/media/platform/vivid/vivid-kthread-cap.c dev->int_menu->cur.val); val 70 drivers/media/platform/vivid/vivid-radio-common.c rds->picode = dev->radio_tx_rds_pi->cur.val; val 71 drivers/media/platform/vivid/vivid-radio-common.c rds->pty = dev->radio_tx_rds_pty->cur.val; val 72 drivers/media/platform/vivid/vivid-radio-common.c rds->mono_stereo = dev->radio_tx_rds_mono_stereo->cur.val; val 73 drivers/media/platform/vivid/vivid-radio-common.c rds->art_head = dev->radio_tx_rds_art_head->cur.val; val 74 drivers/media/platform/vivid/vivid-radio-common.c rds->compressed = dev->radio_tx_rds_compressed->cur.val; val 75 drivers/media/platform/vivid/vivid-radio-common.c rds->dyn_pty = dev->radio_tx_rds_dyn_pty->cur.val; val 76 drivers/media/platform/vivid/vivid-radio-common.c rds->ta = dev->radio_tx_rds_ta->cur.val; val 77 drivers/media/platform/vivid/vivid-radio-common.c rds->tp = dev->radio_tx_rds_tp->cur.val; val 78 drivers/media/platform/vivid/vivid-radio-common.c rds->ms = dev->radio_tx_rds_ms->cur.val; val 16 drivers/media/platform/vivid/vivid-vbi-gen.c static void wss_insert(u8 *wss, u32 val, unsigned size) val 19 drivers/media/platform/vivid/vivid-vbi-gen.c *wss++ = (val & (1 << size)) ? 0xc0 : 0x10; val 62 drivers/media/platform/vivid/vivid-vbi-gen.c u8 val = (teletext[bit / 8] & (1 << (bit & 7))) ? 0xc0 : 0x10; val 65 drivers/media/platform/vivid/vivid-vbi-gen.c buf[i++] = val; val 166 drivers/media/platform/vivid/vivid-vbi-gen.c static u8 calc_parity(u8 val) val 172 drivers/media/platform/vivid/vivid-vbi-gen.c tot += (val & (1 << i)) ? 1 : 0; val 173 drivers/media/platform/vivid/vivid-vbi-gen.c return val | ((tot & 1) ? 0 : 0x80); val 46 drivers/media/platform/vsp1/vsp1_brx.c brx->bgcolor = ctrl->val; val 75 drivers/media/platform/vsp1/vsp1_clu.c clu->mode = ctrl->val; val 159 drivers/media/platform/vsp1/vsp1_hgo.c hgo->max_rgb = hgo->ctrls.max_rgb->cur.val; val 161 drivers/media/platform/vsp1/vsp1_hgo.c hgo->num_bins = hgo_num_bins[hgo->ctrls.num_bins->cur.val]; val 263 drivers/media/platform/vsp1/vsp1_rwpf.c rwpf->alpha = ctrl->val; val 82 drivers/media/platform/vsp1/vsp1_sru.c sru->intensity = ctrl->val; val 103 drivers/media/platform/vsp1/vsp1_wpf.c rotation = wpf->flip.ctrls.rotate ? wpf->flip.ctrls.rotate->val : 0; val 114 drivers/media/platform/vsp1/vsp1_wpf.c if (wpf->flip.ctrls.vflip->val) val 117 drivers/media/platform/vsp1/vsp1_wpf.c if (wpf->flip.ctrls.hflip && wpf->flip.ctrls.hflip->val) val 219 drivers/media/platform/xilinx/xilinx-tpg.c XTPG_PATTERN_MASK, xtpg->pattern->cur.val); val 225 drivers/media/platform/xilinx/xilinx-tpg.c passthrough = xtpg->pattern->cur.val == 0; val 378 drivers/media/platform/xilinx/xilinx-tpg.c XTPG_PATTERN_MASK, ctrl->val); val 382 drivers/media/platform/xilinx/xilinx-tpg.c XTPG_PATTERN_CONTROL_CROSS_HAIRS, ctrl->val); val 386 drivers/media/platform/xilinx/xilinx-tpg.c XTPG_PATTERN_CONTROL_MOVING_BOX, ctrl->val); val 391 drivers/media/platform/xilinx/xilinx-tpg.c ctrl->val << val 396 drivers/media/platform/xilinx/xilinx-tpg.c XTPG_PATTERN_CONTROL_STUCK_PIXEL, ctrl->val); val 400 drivers/media/platform/xilinx/xilinx-tpg.c XTPG_PATTERN_CONTROL_NOISE, ctrl->val); val 404 drivers/media/platform/xilinx/xilinx-tpg.c XTPG_PATTERN_CONTROL_MOTION, ctrl->val); val 407 drivers/media/platform/xilinx/xilinx-tpg.c xvip_write(&xtpg->xvip, XTPG_MOTION_SPEED, ctrl->val); val 412 drivers/media/platform/xilinx/xilinx-tpg.c ctrl->val << XTPG_CROSS_HAIRS_ROW_SHIFT); val 417 drivers/media/platform/xilinx/xilinx-tpg.c ctrl->val << XTPG_CROSS_HAIRS_COLUMN_SHIFT); val 422 drivers/media/platform/xilinx/xilinx-tpg.c ctrl->val << XTPG_ZPLATE_START_SHIFT); val 427 drivers/media/platform/xilinx/xilinx-tpg.c ctrl->val << XTPG_ZPLATE_SPEED_SHIFT); val 432 drivers/media/platform/xilinx/xilinx-tpg.c ctrl->val << XTPG_ZPLATE_START_SHIFT); val 437 drivers/media/platform/xilinx/xilinx-tpg.c ctrl->val << XTPG_ZPLATE_SPEED_SHIFT); val 440 drivers/media/platform/xilinx/xilinx-tpg.c xvip_write(&xtpg->xvip, XTPG_BOX_SIZE, ctrl->val); val 443 drivers/media/platform/xilinx/xilinx-tpg.c xvip_write(&xtpg->xvip, XTPG_BOX_COLOR, ctrl->val); val 446 drivers/media/platform/xilinx/xilinx-tpg.c xvip_write(&xtpg->xvip, XTPG_STUCK_PIXEL_THRESH, ctrl->val); val 449 drivers/media/platform/xilinx/xilinx-tpg.c xvip_write(&xtpg->xvip, XTPG_NOISE_GAIN, ctrl->val); val 232 drivers/media/radio/dsbr100.c radio->muted = ctrl->val; val 26 drivers/media/radio/lm7000.h u32 val; val 30 drivers/media/radio/lm7000.h val = freq | LM7000_FM_25 | LM7000_BIT_FM; val 33 drivers/media/radio/lm7000.h data = val & (1 << i) ? LM7000_DATA : 0; val 443 drivers/media/radio/radio-cadet.c if (ctrl->val) val 123 drivers/media/radio/radio-isa.c return isa->drv->ops->s_mute_volume(isa, ctrl->val, val 124 drivers/media/radio/radio-isa.c isa->volume ? isa->volume->val : 0); val 281 drivers/media/radio/radio-isa.c ops->s_mute_volume(isa, true, isa->volume ? isa->volume->cur.val : 0); val 239 drivers/media/radio/radio-keene.c radio->muted = ctrl->val; val 245 drivers/media/radio/radio-keene.c radio->pa = (ctrl->val - 71) * 100 / 62; val 249 drivers/media/radio/radio-keene.c radio->preemph_75_us = ctrl->val == V4L2_PREEMPHASIS_75_uS; val 253 drivers/media/radio/radio-keene.c radio->tx = db2tx[(ctrl->val - (s32)ctrl->minimum) / (s32)ctrl->step]; val 276 drivers/media/radio/radio-ma901.c return ma901radio_set_volume(radio, (u16)ctrl->val); val 302 drivers/media/radio/radio-miropcm20.c snd_aci_cmd(dev->aci, ACI_SET_TUNERMUTE, ctrl->val, -1); val 401 drivers/media/radio/radio-mr800.c return amradio_set_mute(radio, ctrl->val); val 107 drivers/media/radio/radio-sf16fmi.c int val; val 111 drivers/media/radio/radio-sf16fmi.c val = fmi->mute ? 0x00 : 0x08; /* mute/unmute */ val 112 drivers/media/radio/radio-sf16fmi.c outb(val, fmi->io); val 113 drivers/media/radio/radio-sf16fmi.c outb(val | 0x10, fmi->io); val 116 drivers/media/radio/radio-sf16fmi.c outb(val, fmi->io); val 196 drivers/media/radio/radio-sf16fmi.c if (ctrl->val) val 200 drivers/media/radio/radio-sf16fmi.c fmi->mute = ctrl->val; val 157 drivers/media/radio/radio-sf16fmr2.c volume = ctrl->val; val 158 drivers/media/radio/radio-sf16fmr2.c balance = fmr2->balance->cur.val; val 161 drivers/media/radio/radio-sf16fmr2.c balance = ctrl->val; val 162 drivers/media/radio/radio-sf16fmr2.c volume = fmr2->volume->cur.val; val 80 drivers/media/radio/radio-shark.c static void shark_write_val(struct snd_tea575x *tea, u32 val) val 86 drivers/media/radio/radio-shark.c if (shark->last_val == val) val 92 drivers/media/radio/radio-shark.c shark->transfer_buffer[i] |= (val >> (24 - i * 8)) & 0xff; val 99 drivers/media/radio/radio-shark.c shark->last_val = val; val 108 drivers/media/radio/radio-shark.c u32 val = 0; val 131 drivers/media/radio/radio-shark.c val |= shark->transfer_buffer[i] << (24 - i * 8); val 133 drivers/media/radio/radio-shark.c shark->last_val = val; val 140 drivers/media/radio/radio-shark.c if (((val & TEA575X_BIT_BAND_MASK) == TEA575X_BIT_BAND_FM) && val 141 drivers/media/radio/radio-shark.c !(val & TEA575X_BIT_MONO)) val 146 drivers/media/radio/radio-shark.c return val; val 842 drivers/media/radio/radio-si476x.c ctrl->val = !!SI476X_PHDIV_STATUS_LINK_LOCKED(retval); val 874 drivers/media/radio/radio-si476x.c ctrl->val); val 877 drivers/media/radio/radio-si476x.c switch (ctrl->val) { val 904 drivers/media/radio/radio-si476x.c ctrl->val); val 909 drivers/media/radio/radio-si476x.c ctrl->val); val 914 drivers/media/radio/radio-si476x.c ctrl->val); val 925 drivers/media/radio/radio-si476x.c if (ctrl->val) { val 966 drivers/media/radio/radio-si476x.c ctrl->val); val 970 drivers/media/radio/radio-si476x.c mode = si476x_phase_diversity_idx_to_mode(ctrl->val); val 1013 drivers/media/radio/radio-si476x.c reg->val = value; val 1028 drivers/media/radio/radio-si476x.c (unsigned int)reg->val); val 375 drivers/media/radio/radio-tea5764.c tea5764_mute(radio, ctrl->val); val 490 drivers/media/radio/radio-tea5777.c if (c->val) val 36 drivers/media/radio/radio-tea5777.h int (*write_reg)(struct radio_tea5777 *tea, u64 val); val 47 drivers/media/radio/radio-tea5777.h int (*read_reg)(struct radio_tea5777 *tea, u32 *val); val 75 drivers/media/radio/radio-trust.c unsigned char val, mask; val 89 drivers/media/radio/radio-trust.c val = va_arg(args, unsigned); val 91 drivers/media/radio/radio-trust.c if (val & mask) val 170 drivers/media/radio/radio-trust.c write_i2c(tr, 2, TDA7318_ADDR, 0x60 | basstreble2chip[ctrl->val]); val 173 drivers/media/radio/radio-trust.c write_i2c(tr, 2, TDA7318_ADDR, 0x70 | basstreble2chip[ctrl->val]); val 135 drivers/media/radio/radio-wl1273.c u16 val; val 157 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_RDS_SYNC_GET, &val); val 161 drivers/media/radio/radio-wl1273.c if ((val & 0x01) == 0) { val 571 drivers/media/radio/radio-wl1273.c u16 val = WL1273_POWER_SET_FM; val 574 drivers/media/radio/radio-wl1273.c val |= WL1273_POWER_SET_RDS; val 577 drivers/media/radio/radio-wl1273.c r = core->write(core, WL1273_POWER_SET, val); val 581 drivers/media/radio/radio-wl1273.c r = core->write(core, WL1273_POWER_SET, val); val 634 drivers/media/radio/radio-wl1273.c u16 val = WL1273_POWER_SET_FM; val 637 drivers/media/radio/radio-wl1273.c val |= WL1273_POWER_SET_RDS; val 639 drivers/media/radio/radio-wl1273.c r = core->write(core, WL1273_POWER_SET, val); val 877 drivers/media/radio/radio-wl1273.c u16 val; val 884 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_READ_FMANT_TUNE_VALUE, &val); val 891 drivers/media/radio/radio-wl1273.c return val; val 1033 drivers/media/radio/radio-wl1273.c u16 val; val 1060 drivers/media/radio/radio-wl1273.c val = 255; val 1062 drivers/media/radio/radio-wl1273.c val = count; val 1064 drivers/media/radio/radio-wl1273.c core->write(core, WL1273_RDS_CONFIG_DATA_SET, val); val 1066 drivers/media/radio/radio-wl1273.c if (copy_from_user(radio->write_buf + 1, buf, val)) { val 1071 drivers/media/radio/radio-wl1273.c dev_dbg(radio->dev, "Count: %d\n", val); val 1075 drivers/media/radio/radio-wl1273.c core->write_data(core, radio->write_buf, val + 1); val 1077 drivers/media/radio/radio-wl1273.c r = val; val 1181 drivers/media/radio/radio-wl1273.c u16 val; val 1206 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_RDS_SYNC_GET, &val); val 1210 drivers/media/radio/radio-wl1273.c } else if (val == 0) { val 1385 drivers/media/radio/radio-wl1273.c ctrl->val = wl1273_fm_get_tx_ctune(radio); val 1423 drivers/media/radio/radio-wl1273.c if (core->mode == WL1273_MODE_RX && ctrl->val) val 1431 drivers/media/radio/radio-wl1273.c else if (core->mode == WL1273_MODE_TX && ctrl->val) val 1440 drivers/media/radio/radio-wl1273.c if (ctrl->val == 0) val 1447 drivers/media/radio/radio-wl1273.c r = wl1273_fm_set_preemphasis(radio, ctrl->val); val 1451 drivers/media/radio/radio-wl1273.c r = wl1273_fm_set_tx_power(radio, ctrl->val); val 1501 drivers/media/radio/radio-wl1273.c u16 val; val 1530 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_STEREO_GET, &val); val 1534 drivers/media/radio/radio-wl1273.c if (val == 1) val 1539 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_RSSI_LVL_GET, &val); val 1543 drivers/media/radio/radio-wl1273.c tuner->signal = (s16) val; val 1548 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_RDS_SYNC_GET, &val); val 1552 drivers/media/radio/radio-wl1273.c if (val == WL1273_RDS_SYNCHRONIZED) val 1762 drivers/media/radio/radio-wl1273.c u16 val; val 1782 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_MONO_SET, &val); val 1786 drivers/media/radio/radio-wl1273.c if (val == WL1273_TX_STEREO) val 1804 drivers/media/radio/radio-wl1273.c u16 val; val 1819 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_ASIC_ID_GET, &val); val 1823 drivers/media/radio/radio-wl1273.c dev_info(dev, "ASIC_ID: 0x%04x\n", val); val 1825 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_ASIC_VER_GET, &val); val 1829 drivers/media/radio/radio-wl1273.c dev_info(dev, "ASIC Version: 0x%04x\n", val); val 1831 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_FIRM_VER_GET, &val); val 1835 drivers/media/radio/radio-wl1273.c dev_info(dev, "FW version: %d(0x%04x)\n", val, val); val 1837 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_BAND_SET, &val); val 1841 drivers/media/radio/radio-wl1273.c dev_info(dev, "BAND: %d\n", val); val 1844 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_PUPD_SET, &val); val 1848 drivers/media/radio/radio-wl1273.c dev_info(dev, "PUPD: 0x%04x\n", val); val 1850 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_CHANL_SET, &val); val 1854 drivers/media/radio/radio-wl1273.c dev_info(dev, "Tx frequency: %dkHz\n", val*10); val 1858 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_FREQ_SET, &val); val 1862 drivers/media/radio/radio-wl1273.c dev_info(dev, "RX Frequency: %dkHz\n", bf + val*50); val 1864 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_MOST_MODE_SET, &val); val 1868 drivers/media/radio/radio-wl1273.c else if (val == 0) val 1870 drivers/media/radio/radio-wl1273.c else if (val == 1) val 1873 drivers/media/radio/radio-wl1273.c dev_info(dev, "MOST_MODE: Unexpected value: %d\n", val); val 1875 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_MOST_BLEND_SET, &val); val 1878 drivers/media/radio/radio-wl1273.c else if (val == 0) val 1881 drivers/media/radio/radio-wl1273.c else if (val == 1) val 1884 drivers/media/radio/radio-wl1273.c dev_info(dev, "MOST_BLEND: Unexpected val: %d\n", val); val 1886 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_STEREO_GET, &val); val 1889 drivers/media/radio/radio-wl1273.c else if (val == 0) val 1891 drivers/media/radio/radio-wl1273.c else if (val == 1) val 1894 drivers/media/radio/radio-wl1273.c dev_info(dev, "STEREO: Unexpected value: %d\n", val); val 1896 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_RSSI_LVL_GET, &val); val 1900 drivers/media/radio/radio-wl1273.c dev_info(dev, "RX signal strength: %d\n", (s16) val); val 1902 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_POWER_SET, &val); val 1906 drivers/media/radio/radio-wl1273.c dev_info(dev, "POWER: 0x%04x\n", val); val 1908 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_INT_MASK_SET, &val); val 1912 drivers/media/radio/radio-wl1273.c dev_info(dev, "INT_MASK: 0x%04x\n", val); val 1914 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_RDS_SYNC_GET, &val); val 1918 drivers/media/radio/radio-wl1273.c else if (val == 0) val 1921 drivers/media/radio/radio-wl1273.c else if (val == 1) val 1924 drivers/media/radio/radio-wl1273.c dev_info(dev, "RDS_SYNC: Unexpected value: %d\n", val); val 1926 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_I2S_MODE_CONFIG_SET, &val); val 1931 drivers/media/radio/radio-wl1273.c dev_info(dev, "I2S_MODE_CONFIG: 0x%04x\n", val); val 1933 drivers/media/radio/radio-wl1273.c r = core->read(core, WL1273_VOLUME_SET, &val); val 1937 drivers/media/radio/radio-wl1273.c dev_info(dev, "VOLUME: 0x%04x\n", val); val 144 drivers/media/radio/saa7706h.c static int saa7706h_set_reg24(struct v4l2_subdev *sd, u16 reg, u32 val) val 152 drivers/media/radio/saa7706h.c buf[pos++] = val >> 16; val 153 drivers/media/radio/saa7706h.c buf[pos++] = val >> 8; val 154 drivers/media/radio/saa7706h.c buf[pos++] = val; val 159 drivers/media/radio/saa7706h.c static int saa7706h_set_reg24_err(struct v4l2_subdev *sd, u16 reg, u32 val, val 162 drivers/media/radio/saa7706h.c return *err ? *err : saa7706h_set_reg24(sd, reg, val); val 165 drivers/media/radio/saa7706h.c static int saa7706h_set_reg16(struct v4l2_subdev *sd, u16 reg, u16 val) val 173 drivers/media/radio/saa7706h.c buf[pos++] = val >> 8; val 174 drivers/media/radio/saa7706h.c buf[pos++] = val; val 179 drivers/media/radio/saa7706h.c static int saa7706h_set_reg16_err(struct v4l2_subdev *sd, u16 reg, u16 val, val 182 drivers/media/radio/saa7706h.c return *err ? *err : saa7706h_set_reg16(sd, reg, val); val 316 drivers/media/radio/saa7706h.c if (ctrl->val) val 583 drivers/media/radio/si470x/radio-si470x-common.c radio->registers[SYSCONFIG2] |= ctrl->val; val 586 drivers/media/radio/si470x/radio-si470x-common.c if (ctrl->val) val 261 drivers/media/radio/si4713/si4713.c u8 val[SI4713_GET_PROP_NRESP]; val 274 drivers/media/radio/si4713/si4713.c args, ARRAY_SIZE(args), val, val 275 drivers/media/radio/si4713/si4713.c ARRAY_SIZE(val), DEFAULT_TIMEOUT); val 280 drivers/media/radio/si4713/si4713.c *pv = compose_u16(val[2], val[3]); val 284 drivers/media/radio/si4713/si4713.c __func__, prop, *pv, val[0]); val 295 drivers/media/radio/si4713/si4713.c static int si4713_write_property(struct si4713_device *sdev, u16 prop, u16 val) val 310 drivers/media/radio/si4713/si4713.c msb(val), val 311 drivers/media/radio/si4713/si4713.c lsb(val), val 324 drivers/media/radio/si4713/si4713.c __func__, prop, val, resp[0]); val 541 drivers/media/radio/si4713/si4713.c u8 val[SI4713_TXFREQ_NRESP]; val 554 drivers/media/radio/si4713/si4713.c args, ARRAY_SIZE(args), val, val 555 drivers/media/radio/si4713/si4713.c ARRAY_SIZE(val), DEFAULT_TIMEOUT); val 562 drivers/media/radio/si4713/si4713.c frequency, val[0]); val 586 drivers/media/radio/si4713/si4713.c u8 val[SI4713_TXPWR_NRESP]; val 605 drivers/media/radio/si4713/si4713.c args, ARRAY_SIZE(args), val, val 606 drivers/media/radio/si4713/si4713.c ARRAY_SIZE(val), DEFAULT_TIMEOUT); val 613 drivers/media/radio/si4713/si4713.c __func__, power, antcap, val[0]); val 634 drivers/media/radio/si4713/si4713.c u8 val[SI4713_TXMEA_NRESP]; val 654 drivers/media/radio/si4713/si4713.c args, ARRAY_SIZE(args), val, val 655 drivers/media/radio/si4713/si4713.c ARRAY_SIZE(val), DEFAULT_TIMEOUT); val 662 drivers/media/radio/si4713/si4713.c __func__, frequency, antcap, val[0]); val 686 drivers/media/radio/si4713/si4713.c u8 val[SI4713_TXSTATUS_NRESP]; val 695 drivers/media/radio/si4713/si4713.c args, ARRAY_SIZE(args), val, val 696 drivers/media/radio/si4713/si4713.c ARRAY_SIZE(val), DEFAULT_TIMEOUT); val 700 drivers/media/radio/si4713/si4713.c "%s: status=0x%02x\n", __func__, val[0]); val 701 drivers/media/radio/si4713/si4713.c *frequency = compose_u16(val[2], val[3]); val 703 drivers/media/radio/si4713/si4713.c *power = val[5]; val 704 drivers/media/radio/si4713/si4713.c *antcap = val[6]; val 705 drivers/media/radio/si4713/si4713.c *noise = val[7]; val 728 drivers/media/radio/si4713/si4713.c u8 val[SI4713_RDSBUFF_NRESP]; val 741 drivers/media/radio/si4713/si4713.c args, ARRAY_SIZE(args), val, val 742 drivers/media/radio/si4713/si4713.c ARRAY_SIZE(val), DEFAULT_TIMEOUT); val 746 drivers/media/radio/si4713/si4713.c "%s: status=0x%02x\n", __func__, val[0]); val 747 drivers/media/radio/si4713/si4713.c *cbleft = (s8)val[2] - val[3]; val 750 drivers/media/radio/si4713/si4713.c __func__, val[1], val[2], val[3], val[4], val[5]); val 766 drivers/media/radio/si4713/si4713.c u8 val[SI4713_RDSPS_NRESP]; val 777 drivers/media/radio/si4713/si4713.c args, ARRAY_SIZE(args), val, val 778 drivers/media/radio/si4713/si4713.c ARRAY_SIZE(val), DEFAULT_TIMEOUT); val 783 drivers/media/radio/si4713/si4713.c v4l2_dbg(1, debug, &sdev->sd, "%s: status=0x%02x\n", __func__, val[0]); val 1107 drivers/media/radio/si4713/si4713.c u32 val = 0; val 1120 drivers/media/radio/si4713/si4713.c if (ctrl->val) { val 1121 drivers/media/radio/si4713/si4713.c ret = si4713_set_mute(sdev, ctrl->val); val 1128 drivers/media/radio/si4713/si4713.c ret = si4713_set_mute(sdev, ctrl->val); val 1163 drivers/media/radio/si4713/si4713.c sdev->tune_pwr_level->val, sdev->tune_ant_cap->val); val 1173 drivers/media/radio/si4713/si4713.c if (sdev->rds_alt_freqs_enable->val) { val 1174 drivers/media/radio/si4713/si4713.c val = sdev->rds_alt_freqs->p_new.p_u32[0]; val 1175 drivers/media/radio/si4713/si4713.c val = val / 100 - 876 + 0xe101; val 1177 drivers/media/radio/si4713/si4713.c val = 0xe0e0; val 1179 drivers/media/radio/si4713/si4713.c ret = si4713_write_property(sdev, SI4713_TX_RDS_PS_AF, val); val 1188 drivers/media/radio/si4713/si4713.c val = ctrl->val; val 1190 drivers/media/radio/si4713/si4713.c val = val / mul; val 1192 drivers/media/radio/si4713/si4713.c ret = usecs_to_dev(val, table, size); val 1195 drivers/media/radio/si4713/si4713.c val = ret; val 1200 drivers/media/radio/si4713/si4713.c ret = si4713_read_property(sdev, property, &val); val 1203 drivers/media/radio/si4713/si4713.c val = set_bits(val, ctrl->val, bit, mask); val 1206 drivers/media/radio/si4713/si4713.c ret = si4713_write_property(sdev, property, val); val 1210 drivers/media/radio/si4713/si4713.c val = ctrl->val; val 82 drivers/media/radio/tea575x.c static void snd_tea575x_write(struct snd_tea575x *tea, unsigned int val) val 88 drivers/media/radio/tea575x.c return tea->ops->write_val(tea, val); val 94 drivers/media/radio/tea575x.c data = (val >> 24) & TEA575X_DATA; val 95 drivers/media/radio/tea575x.c val <<= 1; /* shift data */ val 142 drivers/media/radio/tea575x.c static u32 snd_tea575x_val_to_freq(struct snd_tea575x *tea, u32 val) val 144 drivers/media/radio/tea575x.c u32 freq = val & TEA575X_BIT_FREQ_MASK; val 208 drivers/media/radio/tea575x.c tea->val &= ~(TEA575X_BIT_FREQ_MASK | TEA575X_BIT_BAND_MASK); val 209 drivers/media/radio/tea575x.c tea->val |= band; val 210 drivers/media/radio/tea575x.c tea->val |= freq & TEA575X_BIT_FREQ_MASK; val 211 drivers/media/radio/tea575x.c snd_tea575x_write(tea, tea->val); val 212 drivers/media/radio/tea575x.c tea->freq = snd_tea575x_val_to_freq(tea, tea->val); val 290 drivers/media/radio/tea575x.c v->audmode = (tea->val & TEA575X_BIT_MONO) ? val 309 drivers/media/radio/tea575x.c u32 orig_val = tea->val; val 313 drivers/media/radio/tea575x.c tea->val &= ~TEA575X_BIT_MONO; val 315 drivers/media/radio/tea575x.c tea->val |= TEA575X_BIT_MONO; val 317 drivers/media/radio/tea575x.c if (tea->band != BAND_AM && tea->val != orig_val) val 393 drivers/media/radio/tea575x.c tea->val &= ~TEA575X_BIT_FREQ_MASK; val 394 drivers/media/radio/tea575x.c tea->val |= TEA575X_BIT_SEARCH; val 396 drivers/media/radio/tea575x.c tea->val |= TEA575X_BIT_UPDOWN; val 398 drivers/media/radio/tea575x.c tea->val &= ~TEA575X_BIT_UPDOWN; val 399 drivers/media/radio/tea575x.c snd_tea575x_write(tea, tea->val); val 406 drivers/media/radio/tea575x.c tea->val &= ~TEA575X_BIT_SEARCH; val 429 drivers/media/radio/tea575x.c snd_tea575x_write(tea, tea->val); val 433 drivers/media/radio/tea575x.c tea->val &= ~TEA575X_BIT_SEARCH; val 437 drivers/media/radio/tea575x.c tea->val &= ~TEA575X_BIT_SEARCH; val 457 drivers/media/radio/tea575x.c tea->mute = ctrl->val; val 507 drivers/media/radio/tea575x.c tea->val = TEA575X_BIT_BAND_FM | TEA575X_BIT_SEARCH_5_28; val 198 drivers/media/radio/wl128x/fmdrv_v4l2.c ctrl->val = fm_tx_get_tune_cap_val(fmdev); val 215 drivers/media/radio/wl128x/fmdrv_v4l2.c return fm_rx_set_volume(fmdev, (u16)ctrl->val); val 218 drivers/media/radio/wl128x/fmdrv_v4l2.c return fmc_set_mute_mode(fmdev, (u8)ctrl->val); val 222 drivers/media/radio/wl128x/fmdrv_v4l2.c return fm_tx_set_pwr_lvl(fmdev, (u8)ctrl->val); val 225 drivers/media/radio/wl128x/fmdrv_v4l2.c return fm_tx_set_preemph_filter(fmdev, (u8) ctrl->val); val 26 drivers/media/rc/fintek-cir.c static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg) val 29 drivers/media/rc/fintek-cir.c __func__, reg, val, fintek->cr_ip, fintek->cr_dp); val 31 drivers/media/rc/fintek-cir.c outb(val, fintek->cr_dp); val 37 drivers/media/rc/fintek-cir.c u8 val; val 40 drivers/media/rc/fintek-cir.c val = inb(fintek->cr_dp); val 43 drivers/media/rc/fintek-cir.c __func__, reg, val, fintek->cr_ip, fintek->cr_dp); val 44 drivers/media/rc/fintek-cir.c return val; val 48 drivers/media/rc/fintek-cir.c static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) val 50 drivers/media/rc/fintek-cir.c u8 tmp = fintek_cr_read(fintek, reg) | val; val 55 drivers/media/rc/fintek-cir.c static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) val 57 drivers/media/rc/fintek-cir.c u8 tmp = fintek_cr_read(fintek, reg) & ~val; val 85 drivers/media/rc/fintek-cir.c static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset) val 87 drivers/media/rc/fintek-cir.c outb(val, fintek->cir_addr + offset); val 27 drivers/media/rc/gpio-ir-recv.c int val; val 30 drivers/media/rc/gpio-ir-recv.c val = gpiod_get_value(gpio_dev->gpiod); val 31 drivers/media/rc/gpio-ir-recv.c if (val >= 0) val 32 drivers/media/rc/gpio-ir-recv.c ir_raw_event_store_edge(gpio_dev->rcdev, val == 1); val 73 drivers/media/rc/ir-hix5hd2.c u32 val; val 77 drivers/media/rc/ir-hix5hd2.c regmap_read(dev->regmap, IR_CLK, &val); val 79 drivers/media/rc/ir-hix5hd2.c val &= ~IR_CLK_RESET; val 80 drivers/media/rc/ir-hix5hd2.c val |= IR_CLK_ENABLE; val 82 drivers/media/rc/ir-hix5hd2.c val &= ~IR_CLK_ENABLE; val 83 drivers/media/rc/ir-hix5hd2.c val |= IR_CLK_RESET; val 85 drivers/media/rc/ir-hix5hd2.c regmap_write(dev->regmap, IR_CLK, val); val 98 drivers/media/rc/ir-hix5hd2.c u32 val, rate; val 112 drivers/media/rc/ir-hix5hd2.c val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT; val 113 drivers/media/rc/ir-hix5hd2.c val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT; val 114 drivers/media/rc/ir-hix5hd2.c val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK val 116 drivers/media/rc/ir-hix5hd2.c val |= IR_CFG_MODE_RAW; val 117 drivers/media/rc/ir-hix5hd2.c val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT; val 118 drivers/media/rc/ir-hix5hd2.c writel_relaxed(val, priv->base + IR_CONFIG); val 47 drivers/media/rc/ir-spi.c u16 val; val 59 drivers/media/rc/ir-spi.c val = (i % 2) ? idata->space : idata->pulse; val 61 drivers/media/rc/ir-spi.c idata->tx_buf[len++] = val; val 380 drivers/media/rc/ite-cir.c u8 val; val 432 drivers/media/rc/ite-cir.c val = (ITE_TX_MAX_RLE * next_rle_us) / max_rle_us; val 435 drivers/media/rc/ite-cir.c last_sent[last_idx++] = val; val 439 drivers/media/rc/ite-cir.c val = (val - 1) & ITE_TX_RLE_MASK; val 443 drivers/media/rc/ite-cir.c val |= ITE_TX_PULSE; val 446 drivers/media/rc/ite-cir.c val |= ITE_TX_SPACE; val 476 drivers/media/rc/ite-cir.c dev->params.put_tx_byte(dev, val); val 573 drivers/media/rc/ite-cir.c u8 val; val 578 drivers/media/rc/ite-cir.c val = inb(dev->cir_addr + IT87_RCR) val 582 drivers/media/rc/ite-cir.c val |= IT87_HCFS; val 585 drivers/media/rc/ite-cir.c val |= IT87_RXEND; val 587 drivers/media/rc/ite-cir.c val |= allowance_bits; val 589 drivers/media/rc/ite-cir.c outb(val, dev->cir_addr + IT87_RCR); val 785 drivers/media/rc/ite-cir.c u8 val; val 793 drivers/media/rc/ite-cir.c val = (inb(dev->cir_addr + IT8708_C0CFR) val 797 drivers/media/rc/ite-cir.c val |= IT85_HCFS; val 799 drivers/media/rc/ite-cir.c outb(val, dev->cir_addr + IT8708_C0CFR); val 805 drivers/media/rc/ite-cir.c val = inb(dev->cir_addr + IT8708_C0RCR) val 809 drivers/media/rc/ite-cir.c val |= IT85_RXEND; val 811 drivers/media/rc/ite-cir.c val |= allowance_bits; val 813 drivers/media/rc/ite-cir.c outb(val, dev->cir_addr + IT8708_C0RCR); val 816 drivers/media/rc/ite-cir.c val = inb(dev->cir_addr + IT8708_C0TCR) & ~IT85_TXMPW; val 817 drivers/media/rc/ite-cir.c val |= pulse_width_bits; val 818 drivers/media/rc/ite-cir.c outb(val, dev->cir_addr + IT8708_C0TCR); val 1007 drivers/media/rc/ite-cir.c static inline void it8709_wm(struct ite_dev *dev, u8 val, int index) val 1010 drivers/media/rc/ite-cir.c outb(val, dev->cir_addr + IT8709_RAM_VAL); val 1043 drivers/media/rc/ite-cir.c static void it8709_wr(struct ite_dev *dev, u8 val, int index) val 1048 drivers/media/rc/ite-cir.c it8709_wm(dev, val, IT8709_REG_VAL); val 1082 drivers/media/rc/ite-cir.c u8 val; val 1086 drivers/media/rc/ite-cir.c val = (it8709_rr(dev, IT85_C0CFR) val 1091 drivers/media/rc/ite-cir.c val |= IT85_HCFS; val 1093 drivers/media/rc/ite-cir.c it8709_wr(dev, val, IT85_C0CFR); val 1096 drivers/media/rc/ite-cir.c val = it8709_rr(dev, IT85_C0RCR) val 1100 drivers/media/rc/ite-cir.c val |= IT85_RXEND; val 1102 drivers/media/rc/ite-cir.c val |= allowance_bits; val 1104 drivers/media/rc/ite-cir.c it8709_wr(dev, val, IT85_C0RCR); val 1107 drivers/media/rc/ite-cir.c val = it8709_rr(dev, IT85_C0TCR) & ~IT85_TXMPW; val 1108 drivers/media/rc/ite-cir.c val |= pulse_width_bits; val 1109 drivers/media/rc/ite-cir.c it8709_wr(dev, val, IT85_C0TCR); val 379 drivers/media/rc/lirc_dev.c u32 val = 0; val 383 drivers/media/rc/lirc_dev.c ret = get_user(val, argp); val 400 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_REC_SCANCODE; val 403 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_REC_MODE2; val 405 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_GET_REC_RESOLUTION; val 409 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_SEND_PULSE; val 411 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_SET_TRANSMITTER_MASK; val 413 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_SET_SEND_CARRIER; val 415 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_SET_SEND_DUTY_CYCLE; val 419 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_SET_REC_CARRIER | val 423 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_USE_WIDEBAND_RECEIVER; val 426 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_MEASURE_CARRIER; val 429 drivers/media/rc/lirc_dev.c val |= LIRC_CAN_SET_REC_TIMEOUT; val 438 drivers/media/rc/lirc_dev.c val = fh->rec_mode; val 447 drivers/media/rc/lirc_dev.c if (val != LIRC_MODE_SCANCODE) val 451 drivers/media/rc/lirc_dev.c if (!(val == LIRC_MODE_MODE2 || val 452 drivers/media/rc/lirc_dev.c val == LIRC_MODE_SCANCODE)) val 458 drivers/media/rc/lirc_dev.c fh->rec_mode = val; val 465 drivers/media/rc/lirc_dev.c val = fh->send_mode; val 471 drivers/media/rc/lirc_dev.c else if (!(val == LIRC_MODE_PULSE || val == LIRC_MODE_SCANCODE)) val 474 drivers/media/rc/lirc_dev.c fh->send_mode = val; val 482 drivers/media/rc/lirc_dev.c ret = dev->s_tx_mask(dev, val); val 489 drivers/media/rc/lirc_dev.c ret = dev->s_tx_carrier(dev, val); val 495 drivers/media/rc/lirc_dev.c else if (val <= 0 || val >= 100) val 498 drivers/media/rc/lirc_dev.c ret = dev->s_tx_duty_cycle(dev, val); val 505 drivers/media/rc/lirc_dev.c else if (val <= 0) val 509 drivers/media/rc/lirc_dev.c val); val 515 drivers/media/rc/lirc_dev.c else if (val <= 0) val 518 drivers/media/rc/lirc_dev.c fh->carrier_low = val; val 525 drivers/media/rc/lirc_dev.c val = dev->rx_resolution / 1000; val 532 drivers/media/rc/lirc_dev.c ret = dev->s_learning_mode(dev, !!val); val 539 drivers/media/rc/lirc_dev.c ret = dev->s_carrier_report(dev, !!val); val 547 drivers/media/rc/lirc_dev.c val = DIV_ROUND_UP(dev->min_timeout, 1000); val 554 drivers/media/rc/lirc_dev.c val = dev->max_timeout / 1000; val 560 drivers/media/rc/lirc_dev.c } else if (val > U32_MAX / 1000) { val 564 drivers/media/rc/lirc_dev.c u32 tmp = val * 1000; val 579 drivers/media/rc/lirc_dev.c val = DIV_ROUND_UP(dev->timeout, 1000); val 586 drivers/media/rc/lirc_dev.c fh->send_timeout_reports = !!val; val 594 drivers/media/rc/lirc_dev.c ret = put_user(val, argp); val 152 drivers/media/rc/mtk-cir.c u32 val; val 155 drivers/media/rc/mtk-cir.c val = DIV_ROUND_CLOSEST(1000000000ul, val 162 drivers/media/rc/mtk-cir.c val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val); val 166 drivers/media/rc/mtk-cir.c dev_dbg(ir->dev, "@chkperiod = %08x\n", val); val 168 drivers/media/rc/mtk-cir.c return val; val 171 drivers/media/rc/mtk-cir.c static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg) val 176 drivers/media/rc/mtk-cir.c tmp = (tmp & ~mask) | val; val 180 drivers/media/rc/mtk-cir.c static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg) val 182 drivers/media/rc/mtk-cir.c __raw_writel(val, ir->base + reg); val 192 drivers/media/rc/mtk-cir.c u32 val; val 194 drivers/media/rc/mtk-cir.c val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); val 195 drivers/media/rc/mtk-cir.c mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]); val 200 drivers/media/rc/mtk-cir.c u32 val; val 202 drivers/media/rc/mtk-cir.c val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); val 203 drivers/media/rc/mtk-cir.c mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]); val 210 drivers/media/rc/mtk-cir.c u32 i, j, val; val 230 drivers/media/rc/mtk-cir.c val = mtk_r32(ir, mtk_chkdata_reg(ir, i)); val 231 drivers/media/rc/mtk-cir.c dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val); val 234 drivers/media/rc/mtk-cir.c wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8; val 300 drivers/media/rc/mtk-cir.c u32 val; val 390 drivers/media/rc/mtk-cir.c val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) & val 392 drivers/media/rc/mtk-cir.c mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask, val 399 drivers/media/rc/mtk-cir.c val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) & val 401 drivers/media/rc/mtk-cir.c mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask, val 408 drivers/media/rc/mtk-cir.c val = mtk_r32(ir, MTK_CONFIG_HIGH_REG); val 409 drivers/media/rc/mtk-cir.c val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN; val 410 drivers/media/rc/mtk-cir.c mtk_w32(ir, val, MTK_CONFIG_HIGH_REG); val 57 drivers/media/rc/nuvoton-cir.c static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) val 60 drivers/media/rc/nuvoton-cir.c outb(val, nvt->cr_efdr); val 71 drivers/media/rc/nuvoton-cir.c static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) val 73 drivers/media/rc/nuvoton-cir.c u8 tmp = nvt_cr_read(nvt, reg) | val; val 78 drivers/media/rc/nuvoton-cir.c static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) val 80 drivers/media/rc/nuvoton-cir.c u8 tmp = nvt_cr_read(nvt, reg) & ~val; val 134 drivers/media/rc/nuvoton-cir.c static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) val 136 drivers/media/rc/nuvoton-cir.c outb(val, nvt->cir_addr + offset); val 147 drivers/media/rc/nuvoton-cir.c u8 val, u8 offset) val 149 drivers/media/rc/nuvoton-cir.c outb(val, nvt->cir_wake_addr + offset); val 251 drivers/media/rc/nuvoton-cir.c unsigned int val; val 263 drivers/media/rc/nuvoton-cir.c ret = kstrtouint(argv[i], 10, &val); val 266 drivers/media/rc/nuvoton-cir.c val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD); val 267 drivers/media/rc/nuvoton-cir.c if (!val || val > 0x7f) { val 271 drivers/media/rc/nuvoton-cir.c wake_buf[i] = val; val 443 drivers/media/rc/nuvoton-cir.c u8 val, psreg, psmask, psval; val 456 drivers/media/rc/nuvoton-cir.c val = nvt_cr_read(nvt, psreg); val 457 drivers/media/rc/nuvoton-cir.c val &= psmask; val 458 drivers/media/rc/nuvoton-cir.c val |= psval; val 459 drivers/media/rc/nuvoton-cir.c nvt_cr_write(nvt, val, psreg); val 496 drivers/media/rc/nuvoton-cir.c u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); val 497 drivers/media/rc/nuvoton-cir.c nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); val 503 drivers/media/rc/nuvoton-cir.c u8 val, config; val 511 drivers/media/rc/nuvoton-cir.c val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); val 512 drivers/media/rc/nuvoton-cir.c nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, val 521 drivers/media/rc/nuvoton-cir.c u8 val; val 523 drivers/media/rc/nuvoton-cir.c val = nvt_cir_reg_read(nvt, CIR_FIFOCON); val 524 drivers/media/rc/nuvoton-cir.c nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); val 644 drivers/media/rc/nuvoton-cir.c u16 val; val 650 drivers/media/rc/nuvoton-cir.c val = 3000000 / (carrier) - 1; val 651 drivers/media/rc/nuvoton-cir.c nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); val 664 drivers/media/rc/nuvoton-cir.c unsigned int val; val 688 drivers/media/rc/nuvoton-cir.c val = DIV_ROUND_UP(raw[i].duration, 1000L) / SAMPLE_PERIOD; val 691 drivers/media/rc/nuvoton-cir.c while (val > 0 && count < WAKEUP_MAX_SIZE) { val 693 drivers/media/rc/nuvoton-cir.c if (complete && i == ret - 1 && val < BUF_LEN_MASK) val 697 drivers/media/rc/nuvoton-cir.c buf_val = (val > BUF_LEN_MASK) ? BUF_LEN_MASK : val; val 700 drivers/media/rc/nuvoton-cir.c val -= buf_val; val 1333 drivers/media/rc/rc-main.c u32 val; val 1343 drivers/media/rc/rc-main.c val = filter->mask; val 1345 drivers/media/rc/rc-main.c val = filter->data; val 1348 drivers/media/rc/rc-main.c return sprintf(buf, "%#x\n", val); val 1378 drivers/media/rc/rc-main.c unsigned long val; val 1381 drivers/media/rc/rc-main.c ret = kstrtoul(buf, 0, &val); val 1400 drivers/media/rc/rc-main.c new_filter.mask = val; val 1402 drivers/media/rc/rc-main.c new_filter.data = val; val 1419 drivers/media/rc/rc-main.c val) { val 1568 drivers/media/rc/rc-main.c #define ADD_HOTPLUG_VAR(fmt, val...) \ val 1570 drivers/media/rc/rc-main.c int err = add_uevent_var(env, fmt, val); \ val 343 drivers/media/rc/redrat3.c unsigned int i, sig_size, single_len, offset, val; val 363 drivers/media/rc/redrat3.c val = get_unaligned_be16(&rr3->irdata.lens[offset]); val 364 drivers/media/rc/redrat3.c single_len = redrat3_len_to_us(val); val 533 drivers/media/rc/redrat3.c u8 *val; val 534 drivers/media/rc/redrat3.c size_t const len = sizeof(*val); val 539 drivers/media/rc/redrat3.c val = kmalloc(len, GFP_KERNEL); val 540 drivers/media/rc/redrat3.c if (!val) val 543 drivers/media/rc/redrat3.c *val = 0x01; val 546 drivers/media/rc/redrat3.c RR3_CPUCS_REG_ADDR, 0, val, len, HZ * 25); val 549 drivers/media/rc/redrat3.c *val = length_fuzz; val 552 drivers/media/rc/redrat3.c RR3_IR_IO_LENGTH_FUZZ, 0, val, len, HZ * 25); val 553 drivers/media/rc/redrat3.c dev_dbg(dev, "set ir parm len fuzz %d rc 0x%02x\n", *val, rc); val 555 drivers/media/rc/redrat3.c *val = (65536 - (minimum_pause * 2000)) / 256; val 558 drivers/media/rc/redrat3.c RR3_IR_IO_MIN_PAUSE, 0, val, len, HZ * 25); val 559 drivers/media/rc/redrat3.c dev_dbg(dev, "set ir parm min pause %d rc 0x%02x\n", *val, rc); val 561 drivers/media/rc/redrat3.c *val = periods_measure_carrier; val 564 drivers/media/rc/redrat3.c RR3_IR_IO_PERIODS_MF, 0, val, len, HZ * 25); val 565 drivers/media/rc/redrat3.c dev_dbg(dev, "set ir parm periods measure carrier %d rc 0x%02x", *val, val 568 drivers/media/rc/redrat3.c *val = RR3_DRIVER_MAXLENS; val 571 drivers/media/rc/redrat3.c RR3_IR_IO_MAX_LENGTHS, 0, val, len, HZ * 25); val 572 drivers/media/rc/redrat3.c dev_dbg(dev, "set ir parm max lens %d rc 0x%02x\n", *val, rc); val 574 drivers/media/rc/redrat3.c kfree(val); val 51 drivers/media/rc/sir_ir.c static void add_read_queue(int flag, unsigned long val); val 93 drivers/media/rc/sir_ir.c static void add_read_queue(int flag, unsigned long val) val 97 drivers/media/rc/sir_ir.c pr_debug("add flag %d with val %lu\n", flag, val); val 105 drivers/media/rc/sir_ir.c if (val > TIME_CONST / 2) val 106 drivers/media/rc/sir_ir.c val -= TIME_CONST / 2; val 108 drivers/media/rc/sir_ir.c val = 1; val 111 drivers/media/rc/sir_ir.c val += TIME_CONST / 2; val 113 drivers/media/rc/sir_ir.c ev.duration = US_TO_NS(val); val 50 drivers/media/rc/sunxi-cir.c #define REG_RXINT_RAL(val) ((val) << 8) val 61 drivers/media/rc/sunxi-cir.c #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1)) val 68 drivers/media/rc/sunxi-cir.c #define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2))) val 70 drivers/media/rc/sunxi-cir.c #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8))) val 164 drivers/media/rc/tango-ir.c u32 val; val 218 drivers/media/rc/tango-ir.c val = NEC_CAP(31) | GPIO_SEL(12) | clkdiv; val 219 drivers/media/rc/tango-ir.c writel_relaxed(val, ir->rc5_base + IR_NEC_CTRL); val 233 drivers/media/rc/winbond-cir.c u8 val; val 235 drivers/media/rc/winbond-cir.c val = inb(addr); val 236 drivers/media/rc/winbond-cir.c val = ((val & ~mask) | (bits & mask)); val 237 drivers/media/rc/winbond-cir.c outb(val, addr); val 286 drivers/media/rc/winbond-cir.c wbcir_to_rc6cells(u8 val) val 291 drivers/media/rc/winbond-cir.c val &= 0x0F; val 293 drivers/media/rc/winbond-cir.c if (val & 0x01) val 297 drivers/media/rc/winbond-cir.c val >>= 1; val 542 drivers/media/rc/winbond-cir.c u8 val; val 553 drivers/media/rc/winbond-cir.c val = freq - 58; val 557 drivers/media/rc/winbond-cir.c val = freq - 27; val 561 drivers/media/rc/winbond-cir.c val = freq - 27; val 574 drivers/media/rc/winbond-cir.c wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); val 587 drivers/media/rc/winbond-cir.c u8 val; val 596 drivers/media/rc/winbond-cir.c val = 0x0; val 599 drivers/media/rc/winbond-cir.c val = 0x1; val 602 drivers/media/rc/winbond-cir.c val = 0x2; val 605 drivers/media/rc/winbond-cir.c val = 0x3; val 618 drivers/media/rc/winbond-cir.c wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); val 199 drivers/media/spi/gs1662.c u16 val; val 202 drivers/media/spi/gs1662.c ret = gs_read_register(spi, reg->reg & 0xFFFF, &val); val 203 drivers/media/spi/gs1662.c reg->val = val; val 213 drivers/media/spi/gs1662.c return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF); val 170 drivers/media/tuners/e4000.c ret = regmap_write(dev->regmap, 0x10, e400_lna_filter_lut[i].val); val 382 drivers/media/tuners/e4000.c dev->lna_gain_auto->cur.val, dev->lna_gain_auto->val, val 383 drivers/media/tuners/e4000.c dev->lna_gain->cur.val, dev->lna_gain->val); val 385 drivers/media/tuners/e4000.c if (dev->lna_gain_auto->val && dev->if_gain_auto->cur.val) val 387 drivers/media/tuners/e4000.c else if (dev->lna_gain_auto->val) val 389 drivers/media/tuners/e4000.c else if (dev->if_gain_auto->cur.val) val 398 drivers/media/tuners/e4000.c if (dev->lna_gain_auto->val == false) { val 399 drivers/media/tuners/e4000.c ret = regmap_write(dev->regmap, 0x14, dev->lna_gain->val); val 418 drivers/media/tuners/e4000.c dev->mixer_gain_auto->cur.val, dev->mixer_gain_auto->val, val 419 drivers/media/tuners/e4000.c dev->mixer_gain->cur.val, dev->mixer_gain->val); val 421 drivers/media/tuners/e4000.c if (dev->mixer_gain_auto->val) val 430 drivers/media/tuners/e4000.c if (dev->mixer_gain_auto->val == false) { val 431 drivers/media/tuners/e4000.c ret = regmap_write(dev->regmap, 0x15, dev->mixer_gain->val); val 451 drivers/media/tuners/e4000.c dev->if_gain_auto->cur.val, dev->if_gain_auto->val, val 452 drivers/media/tuners/e4000.c dev->if_gain->cur.val, dev->if_gain->val); val 454 drivers/media/tuners/e4000.c if (dev->if_gain_auto->val && dev->lna_gain_auto->cur.val) val 456 drivers/media/tuners/e4000.c else if (dev->lna_gain_auto->cur.val) val 458 drivers/media/tuners/e4000.c else if (dev->if_gain_auto->val) val 467 drivers/media/tuners/e4000.c if (dev->if_gain_auto->val == false) { val 468 drivers/media/tuners/e4000.c buf[0] = e4000_if_gain_lut[dev->if_gain->val].reg16_val; val 469 drivers/media/tuners/e4000.c buf[1] = e4000_if_gain_lut[dev->if_gain->val].reg17_val; val 492 drivers/media/tuners/e4000.c dev->pll_lock->val = (uitmp & 0x01); val 539 drivers/media/tuners/e4000.c dev->f_bandwidth = dev->bandwidth->val; val 691 drivers/media/tuners/e4000.c dev->f_bandwidth = dev->bandwidth->val; val 63 drivers/media/tuners/e4000_priv.h u8 val; val 67 drivers/media/tuners/fc0011.c static int fc0011_writereg(struct fc0011_priv *priv, u8 reg, u8 val) val 69 drivers/media/tuners/fc0011.c u8 buf[2] = { reg, val }; val 76 drivers/media/tuners/fc0011.c reg, val); val 83 drivers/media/tuners/fc0011.c static int fc0011_readreg(struct fc0011_priv *priv, u8 reg, u8 *val) val 90 drivers/media/tuners/fc0011.c .flags = I2C_M_RD, .buf = val ? : &dummy, .len = 1 }, val 11 drivers/media/tuners/fc0012.c static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val) val 13 drivers/media/tuners/fc0012.c u8 buf[2] = {reg, val}; val 21 drivers/media/tuners/fc0012.c KBUILD_MODNAME, reg, val); val 27 drivers/media/tuners/fc0012.c static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val) val 33 drivers/media/tuners/fc0012.c .buf = val, .len = 1 }, val 13 drivers/media/tuners/fc0013.c static int fc0013_writereg(struct fc0013_priv *priv, u8 reg, u8 val) val 15 drivers/media/tuners/fc0013.c u8 buf[2] = {reg, val}; val 21 drivers/media/tuners/fc0013.c err("I2C write reg failed, reg: %02x, val: %02x", reg, val); val 27 drivers/media/tuners/fc0013.c static int fc0013_readreg(struct fc0013_priv *priv, u8 reg, u8 *val) val 31 drivers/media/tuners/fc0013.c { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 }, val 120 drivers/media/tuners/fc0013.c int val; val 137 drivers/media/tuners/fc0013.c val = (int)rc_cal + rc_val; val 145 drivers/media/tuners/fc0013.c if (val > 15) val 147 drivers/media/tuners/fc0013.c else if (val < 0) val 150 drivers/media/tuners/fc0013.c ret = fc0013_writereg(priv, 0x10, (u8)val); val 20 drivers/media/tuners/fc2580.c static int fc2580_wr_reg_ff(struct fc2580_dev *dev, u8 reg, u8 val) val 22 drivers/media/tuners/fc2580.c if (val == 0xff) val 25 drivers/media/tuners/fc2580.c return regmap_write(dev->regmap, reg, val); val 284 drivers/media/tuners/fc2580.c fc2580_init_reg_vals[i].val); val 474 drivers/media/tuners/fc2580.c ctrl->id, ctrl->name, ctrl->cur.val, ctrl->val); val 484 drivers/media/tuners/fc2580.c dev->f_bandwidth = dev->bandwidth->val; val 573 drivers/media/tuners/fc2580.c dev->f_bandwidth = dev->bandwidth->val; val 19 drivers/media/tuners/fc2580_priv.h u8 val; val 20 drivers/media/tuners/m88rs6000t.c u8 val; val 487 drivers/media/tuners/m88rs6000t.c unsigned int val, i; val 501 drivers/media/tuners/m88rs6000t.c ret = regmap_read(dev->regmap, 0x5A, &val); val 504 drivers/media/tuners/m88rs6000t.c RF_GC = val & 0x0f; val 506 drivers/media/tuners/m88rs6000t.c ret = regmap_read(dev->regmap, 0x5F, &val); val 509 drivers/media/tuners/m88rs6000t.c IF_GC = val & 0x0f; val 511 drivers/media/tuners/m88rs6000t.c ret = regmap_read(dev->regmap, 0x3F, &val); val 514 drivers/media/tuners/m88rs6000t.c TIA_GC = (val >> 4) & 0x07; val 516 drivers/media/tuners/m88rs6000t.c ret = regmap_read(dev->regmap, 0x77, &val); val 519 drivers/media/tuners/m88rs6000t.c BB_GC = (val >> 4) & 0x0f; val 521 drivers/media/tuners/m88rs6000t.c ret = regmap_read(dev->regmap, 0x76, &val); val 524 drivers/media/tuners/m88rs6000t.c PGA2_GC = val & 0x3f; val 682 drivers/media/tuners/m88rs6000t.c reg_vals[i].reg, reg_vals[i].val); val 138 drivers/media/tuners/max2165.c u8 val; val 141 drivers/media/tuners/max2165.c val = priv->bb_filter_8mhz_cfg; val 143 drivers/media/tuners/max2165.c val = priv->bb_filter_7mhz_cfg; val 145 drivers/media/tuners/max2165.c max2165_mask_write_reg(priv, REG_BASEBAND_CTRL, 0xF0, val << 4); val 23 drivers/media/tuners/mc44s803.c static int mc44s803_writereg(struct mc44s803_priv *priv, u32 val) val 30 drivers/media/tuners/mc44s803.c buf[0] = (val & 0xff0000) >> 16; val 31 drivers/media/tuners/mc44s803.c buf[1] = (val & 0xff00) >> 8; val 32 drivers/media/tuners/mc44s803.c buf[2] = (val & 0xff); val 42 drivers/media/tuners/mc44s803.c static int mc44s803_readreg(struct mc44s803_priv *priv, u8 reg, u32 *val) val 64 drivers/media/tuners/mc44s803.c *val = (buf[0] << 16) | (buf[1] << 8) | buf[2]; val 80 drivers/media/tuners/mc44s803.c u32 val; val 87 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR) | val 90 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 94 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR); val 96 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 102 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) | val 106 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 110 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_POWER, MC44S803_ADDR) | val 113 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 119 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) | val 123 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 131 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_MIXER, MC44S803_ADDR) | val 135 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 141 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) | val 151 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 155 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) | val 163 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 169 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) | val 172 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 178 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_LNAAGC, MC44S803_ADDR) | val 185 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 205 drivers/media/tuners/mc44s803.c u32 r1, r2, n1, n2, lo1, lo2, freq, val; val 224 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_REFDIV, MC44S803_ADDR) | val 229 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 233 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_LO1, MC44S803_ADDR) | val 236 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 240 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_LO2, MC44S803_ADDR) | val 243 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 247 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) | val 252 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 256 drivers/media/tuners/mc44s803.c val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) | val 261 drivers/media/tuners/mc44s803.c err = mc44s803_writereg(priv, val); val 114 drivers/media/tuners/msi001.c u8 val; val 175 drivers/media/tuners/msi001.c bandwidth = dev->bandwidth->val; val 180 drivers/media/tuners/msi001.c bandwidth = bandwidth_lut[i].val; val 189 drivers/media/tuners/msi001.c dev->bandwidth->val = bandwidth_lut[i].freq; val 267 drivers/media/tuners/msi001.c ret = msi001_set_gain(dev, dev->lna_gain->cur.val, val 268 drivers/media/tuners/msi001.c dev->mixer_gain->cur.val, dev->if_gain->cur.val); val 387 drivers/media/tuners/msi001.c ctrl->id, ctrl->name, ctrl->val, ctrl->minimum, ctrl->maximum, val 396 drivers/media/tuners/msi001.c ret = msi001_set_gain(dev, dev->lna_gain->val, val 397 drivers/media/tuners/msi001.c dev->mixer_gain->cur.val, val 398 drivers/media/tuners/msi001.c dev->if_gain->cur.val); val 401 drivers/media/tuners/msi001.c ret = msi001_set_gain(dev, dev->lna_gain->cur.val, val 402 drivers/media/tuners/msi001.c dev->mixer_gain->val, val 403 drivers/media/tuners/msi001.c dev->if_gain->cur.val); val 406 drivers/media/tuners/msi001.c ret = msi001_set_gain(dev, dev->lna_gain->cur.val, val 407 drivers/media/tuners/msi001.c dev->mixer_gain->cur.val, val 408 drivers/media/tuners/msi001.c dev->if_gain->val); val 28 drivers/media/tuners/mt2060.c static int mt2060_readreg(struct mt2060_priv *priv, u8 reg, u8 *val) val 51 drivers/media/tuners/mt2060.c *val = b[1]; val 58 drivers/media/tuners/mt2060.c static int mt2060_writereg(struct mt2060_priv *priv, u8 reg, u8 val) val 71 drivers/media/tuners/mt2060.c buf[1] = val; val 271 drivers/media/tuners/mt2063.c static int mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val) val 280 drivers/media/tuners/mt2063.c status = mt2063_write(state, reg, &val, 1); val 284 drivers/media/tuners/mt2063.c state->reg[reg] = val; val 1043 drivers/media/tuners/mt2063.c u8 val = 0; val 1050 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ val 1052 drivers/media/tuners/mt2063.c val) val 1056 drivers/media/tuners/mt2063.c val); val 1058 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ val 1060 drivers/media/tuners/mt2063.c val) val 1064 drivers/media/tuners/mt2063.c val); val 1066 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ val 1068 drivers/media/tuners/mt2063.c val) val 1072 drivers/media/tuners/mt2063.c val); val 1076 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */ val 1078 drivers/media/tuners/mt2063.c val) val 1082 drivers/media/tuners/mt2063.c val); val 1084 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ val 1086 drivers/media/tuners/mt2063.c val) val 1090 drivers/media/tuners/mt2063.c val); val 1092 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ val 1094 drivers/media/tuners/mt2063.c val) val 1098 drivers/media/tuners/mt2063.c val); val 1102 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ val 1104 drivers/media/tuners/mt2063.c val) val 1108 drivers/media/tuners/mt2063.c val); val 1110 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */ val 1112 drivers/media/tuners/mt2063.c val) val 1116 drivers/media/tuners/mt2063.c val); val 1118 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ val 1120 drivers/media/tuners/mt2063.c val) val 1124 drivers/media/tuners/mt2063.c val); val 1128 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */ val 1130 drivers/media/tuners/mt2063.c val) val 1134 drivers/media/tuners/mt2063.c val); val 1136 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */ val 1138 drivers/media/tuners/mt2063.c val) val 1142 drivers/media/tuners/mt2063.c val); val 1144 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ val 1146 drivers/media/tuners/mt2063.c val) val 1150 drivers/media/tuners/mt2063.c val); val 1177 drivers/media/tuners/mt2063.c u8 val; val 1187 drivers/media/tuners/mt2063.c val = val 1192 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PD1_TGT] != val) val 1193 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); val 1198 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) | val 1200 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_CTRL_2C] != val) val 1201 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val); val 1206 drivers/media/tuners/mt2063.c val = val 1210 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_FIFF_CTRL2] != val) { val 1212 drivers/media/tuners/mt2063.c mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val); val 1214 drivers/media/tuners/mt2063.c val = val 1217 drivers/media/tuners/mt2063.c mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val); val 1218 drivers/media/tuners/mt2063.c val = val 1222 drivers/media/tuners/mt2063.c mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val); val 1232 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) | val 1234 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_LNA_OV] != val) val 1235 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val); val 1240 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) | val 1242 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_LNA_TGT] != val) val 1243 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val); val 1248 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) | val 1250 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_RF_OV] != val) val 1251 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_RF_OV, val); val 1256 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) | val 1258 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PD1_TGT] != val) val 1259 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); val 1264 drivers/media/tuners/mt2063.c u8 val = ACFIFMAX[Mode]; val 1265 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5) val 1266 drivers/media/tuners/mt2063.c val = 5; val 1267 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) | val 1268 drivers/media/tuners/mt2063.c (val & 0x1F); val 1269 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_FIF_OV] != val) val 1270 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val); val 1275 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) | val 1277 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PD2_TGT] != val) val 1278 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val); val 1283 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) | val 1285 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_LNA_TGT] != val) val 1286 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val); val 1291 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) | val 1293 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PD1_TGT] != val) val 1294 drivers/media/tuners/mt2063.c status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); val 1522 drivers/media/tuners/mt2063.c u8 val; val 1544 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08); val 1545 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_CTUNE_CTRL] != val) { val 1547 drivers/media/tuners/mt2063.c mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val); val 1549 drivers/media/tuners/mt2063.c val = state->reg[MT2063_REG_CTUNE_OV]; val 1554 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_CTUNE_OV] != val) { val 1556 drivers/media/tuners/mt2063.c mt2063_setreg(state, MT2063_REG_CTUNE_OV, val); val 1857 drivers/media/tuners/mt2063.c u8 val = *def++; val 1858 drivers/media/tuners/mt2063.c status = mt2063_write(state, reg, &val, 1); val 39 drivers/media/tuners/mt2131.c static int mt2131_readreg(struct mt2131_priv *priv, u8 reg, u8 *val) val 45 drivers/media/tuners/mt2131.c .buf = val, .len = 1 }, val 55 drivers/media/tuners/mt2131.c static int mt2131_writereg(struct mt2131_priv *priv, u8 reg, u8 val) val 57 drivers/media/tuners/mt2131.c u8 buf[2] = { reg, val }; val 48 drivers/media/tuners/mt2266.c static int mt2266_readreg(struct mt2266_priv *priv, u8 reg, u8 *val) val 52 drivers/media/tuners/mt2266.c { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 }, val 62 drivers/media/tuners/mt2266.c static int mt2266_writereg(struct mt2266_priv *priv, u8 reg, u8 val) val 64 drivers/media/tuners/mt2266.c u8 buf[2] = { reg, val }; val 45 drivers/media/tuners/mxl301rf.c static int reg_write(struct mxl301rf_state *state, u8 reg, u8 val) val 47 drivers/media/tuners/mxl301rf.c u8 buf[2] = { reg, val }; val 52 drivers/media/tuners/mxl301rf.c static int reg_read(struct mxl301rf_state *state, u8 reg, u8 *val) val 59 drivers/media/tuners/mxl301rf.c ret = i2c_master_recv(state->i2c, val, 1); val 139 drivers/media/tuners/mxl301rf.c u8 val; val 184 drivers/media/tuners/mxl301rf.c tune0[5].val = shf_tab[i].shf_val; val 185 drivers/media/tuners/mxl301rf.c tune0[6].val = 0xa0 | shf_tab[i].shf_dir; val 208 drivers/media/tuners/mxl301rf.c tune1[0].val = f & 0xff; val 209 drivers/media/tuners/mxl301rf.c tune1[1].val = f >> 8; val 238 drivers/media/tuners/mxl5005s.c u16 val[25]; /* Binary representation of Value */ val 731 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[0].val[0] = 0; val 737 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[1].val[0] = 1; val 743 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[2].val[0] = 0; val 746 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[2].val[1] = 1; val 752 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[3].val[0] = 0; val 758 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[4].val[0] = 0; val 761 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[4].val[1] = 0; val 764 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[4].val[2] = 1; val 770 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[5].val[0] = 0; val 776 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[6].val[0] = 0; val 779 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[6].val[1] = 1; val 785 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[7].val[0] = 0; val 788 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[7].val[1] = 1; val 791 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[7].val[2] = 1; val 794 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[7].val[3] = 0; val 800 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[8].val[0] = 0; val 806 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[9].val[0] = 1; val 809 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[9].val[1] = 1; val 812 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[9].val[2] = 0; val 815 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[9].val[3] = 1; val 821 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[10].val[0] = 1; val 824 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[10].val[1] = 1; val 827 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[10].val[2] = 0; val 830 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[10].val[3] = 1; val 836 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[11].val[0] = 0; val 839 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[11].val[1] = 0; val 842 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[11].val[2] = 0; val 845 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[11].val[3] = 1; val 848 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[11].val[4] = 0; val 854 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[12].val[0] = 0; val 857 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[12].val[1] = 0; val 860 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[12].val[2] = 0; val 863 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[12].val[3] = 1; val 866 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[12].val[4] = 0; val 869 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[12].val[5] = 0; val 875 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[13].val[0] = 1; val 878 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[13].val[1] = 0; val 881 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[13].val[2] = 0; val 884 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[13].val[3] = 1; val 887 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[13].val[4] = 1; val 890 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[13].val[5] = 0; val 893 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[13].val[6] = 0; val 899 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[0] = 0; val 902 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[1] = 0; val 905 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[2] = 0; val 908 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[3] = 0; val 911 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[4] = 0; val 914 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[5] = 0; val 917 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[6] = 0; val 920 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[7] = 0; val 923 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[8] = 0; val 926 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[9] = 0; val 929 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[10] = 0; val 932 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[11] = 0; val 935 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[12] = 0; val 938 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[13] = 1; val 941 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[14] = 1; val 944 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[14].val[15] = 0; val 950 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[15].val[0] = 0; val 953 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[15].val[1] = 1; val 956 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[15].val[2] = 1; val 962 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[16].val[0] = 0; val 965 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[16].val[1] = 1; val 971 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[17].val[0] = 0; val 977 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[18].val[0] = 0; val 983 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[19].val[0] = 0; val 989 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[20].val[0] = 0; val 995 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[21].val[0] = 0; val 1001 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[22].val[0] = 0; val 1007 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[23].val[0] = 1; val 1013 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[24].val[0] = 1; val 1019 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[25].val[0] = 1; val 1022 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[25].val[1] = 1; val 1028 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[26].val[0] = 0; val 1034 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[27].val[0] = 0; val 1040 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[28].val[0] = 0; val 1046 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[29].val[0] = 1; val 1052 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[30].val[0] = 0; val 1055 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[30].val[1] = 1; val 1058 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[30].val[2] = 1; val 1064 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[31].val[0] = 1; val 1067 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[31].val[1] = 0; val 1070 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[31].val[2] = 1; val 1076 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[32].val[0] = 1; val 1079 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[32].val[1] = 1; val 1082 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[32].val[2] = 0; val 1088 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[33].val[0] = 0; val 1091 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[33].val[1] = 1; val 1094 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[33].val[2] = 0; val 1097 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[33].val[3] = 0; val 1103 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[34].val[0] = 1; val 1106 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[34].val[1] = 1; val 1109 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[34].val[2] = 1; val 1112 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[34].val[3] = 1; val 1118 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[35].val[0] = 0; val 1124 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[36].val[0] = 0; val 1130 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[37].val[0] = 0; val 1133 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[37].val[1] = 0; val 1136 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[37].val[2] = 0; val 1139 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[37].val[3] = 0; val 1142 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[37].val[4] = 0; val 1145 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[37].val[5] = 0; val 1148 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[37].val[6] = 0; val 1154 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[38].val[0] = 0; val 1157 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[38].val[1] = 0; val 1160 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[38].val[2] = 0; val 1163 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[38].val[3] = 0; val 1166 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[38].val[4] = 1; val 1169 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[38].val[5] = 0; val 1175 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[39].val[0] = 1; val 1184 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[0].val[0] = 1; val 1187 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[0].val[1] = 1; val 1193 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[1].val[0] = 1; val 1196 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[1].val[1] = 0; val 1202 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[0] = 0; val 1205 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[1] = 0; val 1208 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[2] = 0; val 1211 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[3] = 0; val 1214 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[4] = 0; val 1217 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[5] = 0; val 1220 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[6] = 0; val 1223 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[7] = 0; val 1226 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[2].val[8] = 0; val 1232 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[3].val[0] = 0; val 1238 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[4].val[0] = 0; val 1241 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[4].val[1] = 1; val 1244 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[4].val[2] = 0; val 1250 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[5].val[0] = 0; val 1253 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[5].val[1] = 0; val 1256 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[5].val[2] = 0; val 1259 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[5].val[3] = 0; val 1265 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[6].val[0] = 1; val 1271 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[7].val[0] = 0; val 1277 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[8].val[0] = 1; val 1283 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[9].val[0] = 1; val 1289 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[10].val[0] = 0; val 1295 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[11].val[0] = 1; val 1298 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[11].val[1] = 0; val 1304 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[12].val[0] = 0; val 1307 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[12].val[1] = 0; val 1310 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[12].val[2] = 0; val 1316 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[13].val[0] = 0; val 1319 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[13].val[1] = 0; val 1322 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[13].val[2] = 0; val 1325 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[13].val[3] = 0; val 1328 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[13].val[4] = 0; val 1331 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[13].val[5] = 1; val 1337 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[14].val[0] = 0; val 1340 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[14].val[1] = 0; val 1343 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[14].val[2] = 0; val 1346 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[14].val[3] = 0; val 1349 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[14].val[4] = 0; val 1352 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[14].val[5] = 0; val 1355 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[14].val[6] = 0; val 1361 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[0] = 0; val 1364 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[1] = 0; val 1367 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[2] = 0; val 1370 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[3] = 0; val 1373 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[4] = 0; val 1376 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[5] = 0; val 1379 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[6] = 0; val 1382 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[7] = 0; val 1385 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[8] = 0; val 1388 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[9] = 0; val 1391 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[10] = 0; val 1394 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[11] = 0; val 1397 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[12] = 0; val 1400 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[13] = 0; val 1403 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[14] = 0; val 1406 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[15] = 0; val 1409 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[16] = 1; val 1412 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[15].val[17] = 1; val 1418 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[16].val[0] = 0; val 1421 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[16].val[1] = 0; val 1424 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[16].val[2] = 0; val 1427 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[16].val[3] = 0; val 1430 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[16].val[4] = 1; val 1436 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[17].val[0] = 0; val 1442 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[18].val[0] = 0; val 1445 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[18].val[1] = 0; val 1448 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[18].val[2] = 0; val 1451 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[18].val[3] = 0; val 1457 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[19].val[0] = 1; val 1460 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[19].val[1] = 1; val 1463 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[19].val[2] = 1; val 1469 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[0] = 0; val 1472 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[1] = 0; val 1475 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[2] = 0; val 1478 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[3] = 0; val 1481 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[4] = 0; val 1484 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[5] = 0; val 1487 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[6] = 0; val 1490 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[7] = 0; val 1493 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[8] = 1; val 1496 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[9] = 1; val 1499 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[20].val[10] = 1; val 1505 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[21].val[0] = 0; val 1508 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[21].val[1] = 0; val 1511 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[21].val[2] = 0; val 1514 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[21].val[3] = 0; val 1517 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[21].val[4] = 0; val 1520 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[21].val[5] = 1; val 1526 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[22].val[0] = 1; val 1532 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[23].val[0] = 0; val 1538 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[24].val[0] = 0; val 1544 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[25].val[0] = 0; val 1550 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[26].val[0] = 0; val 1556 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[27].val[0] = 0; val 1562 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[28].val[0] = 0; val 1568 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[29].val[0] = 1; val 1574 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[30].val[0] = 1; val 1580 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[31].val[0] = 0; val 1586 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[32].val[0] = 0; val 1592 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[33].val[0] = 0; val 1598 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[34].val[0] = 0; val 1601 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[34].val[1] = 0; val 1604 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[34].val[2] = 0; val 1607 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[34].val[3] = 0; val 1610 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[34].val[4] = 0; val 1613 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[34].val[5] = 0; val 1619 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[35].val[0] = 0; val 1622 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[35].val[1] = 0; val 1625 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[35].val[2] = 0; val 1628 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[35].val[3] = 0; val 1631 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[35].val[4] = 0; val 1634 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[35].val[5] = 0; val 1641 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[36].val[0] = 1; val 1647 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[37].val[0] = 0; val 1650 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[37].val[1] = 0; val 1656 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[38].val[0] = 0; val 3430 drivers/media/tuners/mxl5005s.c state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); val 3437 drivers/media/tuners/mxl5005s.c ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); val 3452 drivers/media/tuners/mxl5005s.c state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); val 3459 drivers/media/tuners/mxl5005s.c ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); val 3475 drivers/media/tuners/mxl5005s.c state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); val 3483 drivers/media/tuners/mxl5005s.c MXL_Ctrl[i].val[k] * val 3521 drivers/media/tuners/mxl5005s.c ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k); val 3533 drivers/media/tuners/mxl5005s.c ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); val 3547 drivers/media/tuners/mxl5005s.c ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k); val 3875 drivers/media/tuners/mxl5005s.c static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) val 3878 drivers/media/tuners/mxl5005s.c u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; val 3885 drivers/media/tuners/mxl5005s.c dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr); val 73 drivers/media/tuners/mxl5007t.c u8 val; val 163 drivers/media/tuners/mxl5007t.c static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val) val 167 drivers/media/tuners/mxl5007t.c while (reg_pair[i].reg || reg_pair[i].val) { val 169 drivers/media/tuners/mxl5007t.c reg_pair[i].val &= ~mask; val 170 drivers/media/tuners/mxl5007t.c reg_pair[i].val |= val; val 185 drivers/media/tuners/mxl5007t.c while (reg_pair1[i].reg || reg_pair1[i].val) { val 186 drivers/media/tuners/mxl5007t.c while (reg_pair2[j].reg || reg_pair2[j].val) { val 191 drivers/media/tuners/mxl5007t.c reg_pair2[j].val = reg_pair1[i].val; val 231 drivers/media/tuners/mxl5007t.c u8 val; val 235 drivers/media/tuners/mxl5007t.c val = 0x00; val 238 drivers/media/tuners/mxl5007t.c val = 0x02; val 241 drivers/media/tuners/mxl5007t.c val = 0x03; val 244 drivers/media/tuners/mxl5007t.c val = 0x04; val 247 drivers/media/tuners/mxl5007t.c val = 0x05; val 250 drivers/media/tuners/mxl5007t.c val = 0x06; val 253 drivers/media/tuners/mxl5007t.c val = 0x07; val 256 drivers/media/tuners/mxl5007t.c val = 0x08; val 259 drivers/media/tuners/mxl5007t.c val = 0x09; val 262 drivers/media/tuners/mxl5007t.c val = 0x0a; val 265 drivers/media/tuners/mxl5007t.c val = 0x0b; val 271 drivers/media/tuners/mxl5007t.c set_reg_bits(state->tab_init, 0x02, 0x0f, val); val 383 drivers/media/tuners/mxl5007t.c u8 val; val 387 drivers/media/tuners/mxl5007t.c val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A, val 391 drivers/media/tuners/mxl5007t.c val = 0x2a; val 394 drivers/media/tuners/mxl5007t.c val = 0x3f; val 400 drivers/media/tuners/mxl5007t.c set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val); val 448 drivers/media/tuners/mxl5007t.c static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val) val 450 drivers/media/tuners/mxl5007t.c u8 buf[] = { reg, val }; val 469 drivers/media/tuners/mxl5007t.c while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) { val 471 drivers/media/tuners/mxl5007t.c reg_pair[i].reg, reg_pair[i].val); val 477 drivers/media/tuners/mxl5007t.c static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val) val 484 drivers/media/tuners/mxl5007t.c .buf = val, .len = 1 }, val 64 drivers/media/tuners/qm1d1c0042.c static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) val 66 drivers/media/tuners/qm1d1c0042.c u8 wbuf[2] = { reg, val }; val 75 drivers/media/tuners/qm1d1c0042.c static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val) val 87 drivers/media/tuners/qm1d1c0042.c .buf = val, val 184 drivers/media/tuners/qm1d1c0042.c u8 val, mask; val 198 drivers/media/tuners/qm1d1c0042.c val = state->regs[0x02] & 0x0f; val 201 drivers/media/tuners/qm1d1c0042.c val |= conv_table[i][1] << 7; val 202 drivers/media/tuners/qm1d1c0042.c val |= conv_table[i][2] << 4; val 205 drivers/media/tuners/qm1d1c0042.c ret = reg_write(state, 0x02, val); val 224 drivers/media/tuners/qm1d1c0042.c val = state->regs[0x08]; val 227 drivers/media/tuners/qm1d1c0042.c val &= 0xf0; val 228 drivers/media/tuners/qm1d1c0042.c val |= 0x02; val 230 drivers/media/tuners/qm1d1c0042.c ret = reg_write(state, 0x08, val); val 268 drivers/media/tuners/qm1d1c0042.c val = state->regs[0x0c] & mask; val 269 drivers/media/tuners/qm1d1c0042.c ret = reg_write(state, 0x0c, val); val 273 drivers/media/tuners/qm1d1c0042.c val = state->regs[0x0c] | ~mask; val 274 drivers/media/tuners/qm1d1c0042.c ret = reg_write(state, 0x0c, val); val 320 drivers/media/tuners/qm1d1c0042.c u8 val; val 338 drivers/media/tuners/qm1d1c0042.c ret = reg_read(state, 0x00, &val); val 343 drivers/media/tuners/qm1d1c0042.c if (val == reg_initval[reg_index][0x00]) val 12 drivers/media/tuners/qt1010.c static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val) val 18 drivers/media/tuners/qt1010.c .flags = I2C_M_RD, .buf = val, .len = 1 }, val 30 drivers/media/tuners/qt1010.c static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val) val 32 drivers/media/tuners/qt1010.c u8 buf[2] = { reg, val }; val 123 drivers/media/tuners/qt1010.c rd[2].val = reg05; val 126 drivers/media/tuners/qt1010.c rd[4].val = (freq + QT1010_OFFSET) / FREQ1; val 129 drivers/media/tuners/qt1010.c if (mod1 < 8000000) rd[6].val = 0x1d; val 130 drivers/media/tuners/qt1010.c else rd[6].val = 0x1c; val 133 drivers/media/tuners/qt1010.c if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ val 134 drivers/media/tuners/qt1010.c else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */ val 135 drivers/media/tuners/qt1010.c else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */ val 136 drivers/media/tuners/qt1010.c else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */ val 137 drivers/media/tuners/qt1010.c else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */ val 138 drivers/media/tuners/qt1010.c else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */ val 139 drivers/media/tuners/qt1010.c else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */ val 140 drivers/media/tuners/qt1010.c else rd[7].val = 0x0a; /* +28 MHz */ val 143 drivers/media/tuners/qt1010.c if (mod2 < 2000000) rd[8].val = 0x45; val 144 drivers/media/tuners/qt1010.c else rd[8].val = 0x44; val 148 drivers/media/tuners/qt1010.c rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08); val 151 drivers/media/tuners/qt1010.c rd[13].val = 0xfd; /* TODO: correct value calculation */ val 154 drivers/media/tuners/qt1010.c rd[14].val = 0x91; /* TODO: correct value calculation */ val 157 drivers/media/tuners/qt1010.c if (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */ val 158 drivers/media/tuners/qt1010.c else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */ val 159 drivers/media/tuners/qt1010.c else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */ val 160 drivers/media/tuners/qt1010.c else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */ val 161 drivers/media/tuners/qt1010.c else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */ val 162 drivers/media/tuners/qt1010.c else rd[15].val = 0xd0; val 165 drivers/media/tuners/qt1010.c rd[35].val = (reg05 & 0xf0); val 174 drivers/media/tuners/qt1010.c rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval); val 183 drivers/media/tuners/qt1010.c rd[41].val = (priv->reg20_init_val + 0x0d + tmpval); val 186 drivers/media/tuners/qt1010.c rd[43].val = priv->reg25_init_val; val 189 drivers/media/tuners/qt1010.c rd[45].val = 0x92; /* TODO: correct value calculation */ val 195 drivers/media/tuners/qt1010.c freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, \ val 196 drivers/media/tuners/qt1010.c rd[8].val, rd[10].val, rd[13].val, rd[14].val, \ val 197 drivers/media/tuners/qt1010.c rd[15].val, rd[35].val, rd[40].val, rd[41].val, \ val 198 drivers/media/tuners/qt1010.c rd[43].val, rd[45].val); val 202 drivers/media/tuners/qt1010.c err = qt1010_writereg(priv, rd[i].reg, rd[i].val); val 231 drivers/media/tuners/qt1010.c i2c_data[i].val); val 253 drivers/media/tuners/qt1010.c u8 i, uninitialized_var(val); val 267 drivers/media/tuners/qt1010.c i2c_data[i].val); val 269 drivers/media/tuners/qt1010.c err = qt1010_readreg(priv, i2c_data[i].reg, &val); val 273 drivers/media/tuners/qt1010.c *retval = val; val 328 drivers/media/tuners/qt1010.c i2c_data[i].val); val 331 drivers/media/tuners/qt1010.c if (i2c_data[i].val == 0x20) val 338 drivers/media/tuners/qt1010.c if (i2c_data[i].val == 0x25) val 340 drivers/media/tuners/qt1010.c else if (i2c_data[i].val == 0x1f) val 349 drivers/media/tuners/qt1010.c i2c_data[i].val, valptr); val 79 drivers/media/tuners/qt1010_priv.h u8 oper, reg, val; val 332 drivers/media/tuners/r820t.c static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val, val 347 drivers/media/tuners/r820t.c __func__, r + REG_SHADOW_START, len, len, val); val 349 drivers/media/tuners/r820t.c memcpy(&priv->regs[r], val, len); val 352 drivers/media/tuners/r820t.c static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val, val 358 drivers/media/tuners/r820t.c shadow_store(priv, reg, val, len); val 368 drivers/media/tuners/r820t.c memcpy(&priv->buf[1], &val[pos], size); val 389 drivers/media/tuners/r820t.c static inline int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val) val 391 drivers/media/tuners/r820t.c u8 tmp = val; /* work around GCC PR81715 with asan-stack=1 */ val 406 drivers/media/tuners/r820t.c static inline int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val, val 409 drivers/media/tuners/r820t.c u8 tmp = val; val 420 drivers/media/tuners/r820t.c static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len) val 438 drivers/media/tuners/r820t.c val[i] = bitrev8(p[i]); val 441 drivers/media/tuners/r820t.c __func__, reg, len, len, val); val 454 drivers/media/tuners/r820t.c u8 val, reg08, reg09; val 485 drivers/media/tuners/r820t.c val = range->xtal_cap20p | 0x08; val 488 drivers/media/tuners/r820t.c val = range->xtal_cap10p | 0x08; val 491 drivers/media/tuners/r820t.c val = range->xtal_cap0p | 0x00; val 495 drivers/media/tuners/r820t.c val = range->xtal_cap0p | 0x08; val 498 drivers/media/tuners/r820t.c rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b); val 534 drivers/media/tuners/r820t.c u8 ni, si, nint, vco_fine_tune, val; val 637 drivers/media/tuners/r820t.c val = 0x08; val 639 drivers/media/tuners/r820t.c val = 0x00; val 641 drivers/media/tuners/r820t.c rc = r820t_write_reg_mask(priv, 0x12, val, 0x08); val 935 drivers/media/tuners/r820t.c u8 data[5], val; val 1044 drivers/media/tuners/r820t.c val = 1 | priv->xtal_cap_sel << 1; val 1046 drivers/media/tuners/r820t.c val = 0; val 1047 drivers/media/tuners/r820t.c rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f); val 1386 drivers/media/tuners/r820t.c u8 data[3], val; val 1426 drivers/media/tuners/r820t.c val = data[2] & 0x3f; val 1428 drivers/media/tuners/r820t.c if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23)) val 1431 drivers/media/tuners/r820t.c if (val != 0x3f) val 14 drivers/media/tuners/tda18218.c static int tda18218_wr_regs(struct tda18218_priv *priv, u8 reg, u8 *val, u8 len) val 41 drivers/media/tuners/tda18218.c memcpy(&buf[1], &val[len - remaining], len2); val 60 drivers/media/tuners/tda18218.c static int tda18218_rd_regs(struct tda18218_priv *priv, u8 reg, u8 *val, u8 len) val 87 drivers/media/tuners/tda18218.c memcpy(val, &buf[reg], len); val 99 drivers/media/tuners/tda18218.c static int tda18218_wr_reg(struct tda18218_priv *priv, u8 reg, u8 val) val 101 drivers/media/tuners/tda18218.c return tda18218_wr_regs(priv, reg, &val, 1); val 106 drivers/media/tuners/tda18218.c static int tda18218_rd_reg(struct tda18218_priv *priv, u8 reg, u8 *val) val 108 drivers/media/tuners/tda18218.c return tda18218_rd_regs(priv, reg, val, 1); val 283 drivers/media/tuners/tda18218.c u8 val; val 307 drivers/media/tuners/tda18218.c ret = tda18218_rd_reg(priv, R00_ID, &val); val 309 drivers/media/tuners/tda18218.c dev_dbg(&priv->i2c->dev, "%s: chip id=%02x\n", __func__, val); val 310 drivers/media/tuners/tda18218.c if (ret || val != def_regs[R00_ID]) { val 603 drivers/media/tuners/tda18271-common.c u8 val; val 605 drivers/media/tuners/tda18271-common.c int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val); val 610 drivers/media/tuners/tda18271-common.c regs[R_EP1] |= (0x07 & val); val 620 drivers/media/tuners/tda18271-common.c u8 val; val 622 drivers/media/tuners/tda18271-common.c int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val); val 627 drivers/media/tuners/tda18271-common.c regs[R_EB13] |= (0x7c & val); val 637 drivers/media/tuners/tda18271-common.c u8 val; val 639 drivers/media/tuners/tda18271-common.c int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val); val 644 drivers/media/tuners/tda18271-common.c regs[R_EP2] |= (0xe0 & (val << 5)); val 654 drivers/media/tuners/tda18271-common.c u8 val; val 656 drivers/media/tuners/tda18271-common.c int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val); val 661 drivers/media/tuners/tda18271-common.c regs[R_EP2] |= (0x1f & val); val 671 drivers/media/tuners/tda18271-common.c u8 val; val 673 drivers/media/tuners/tda18271-common.c int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val); val 678 drivers/media/tuners/tda18271-common.c regs[R_EP5] |= (0x07 & val); val 688 drivers/media/tuners/tda18271-common.c u8 val; val 690 drivers/media/tuners/tda18271-common.c int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val); val 700 drivers/media/tuners/tda18271-common.c regs[R_EB14] = val; val 19 drivers/media/tuners/tda18271-maps.c u8 val; val 190 drivers/media/tuners/tda18271-maps.c { .rfmax = 62000, .val = 0x00 }, val 191 drivers/media/tuners/tda18271-maps.c { .rfmax = 84000, .val = 0x01 }, val 192 drivers/media/tuners/tda18271-maps.c { .rfmax = 100000, .val = 0x02 }, val 193 drivers/media/tuners/tda18271-maps.c { .rfmax = 140000, .val = 0x03 }, val 194 drivers/media/tuners/tda18271-maps.c { .rfmax = 170000, .val = 0x04 }, val 195 drivers/media/tuners/tda18271-maps.c { .rfmax = 180000, .val = 0x05 }, val 196 drivers/media/tuners/tda18271-maps.c { .rfmax = 865000, .val = 0x06 }, val 197 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0x00 }, /* end */ val 201 drivers/media/tuners/tda18271-maps.c { .rfmax = 61100, .val = 0x74 }, val 202 drivers/media/tuners/tda18271-maps.c { .rfmax = 350000, .val = 0x40 }, val 203 drivers/media/tuners/tda18271-maps.c { .rfmax = 720000, .val = 0x30 }, val 204 drivers/media/tuners/tda18271-maps.c { .rfmax = 865000, .val = 0x40 }, val 205 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0x00 }, /* end */ val 209 drivers/media/tuners/tda18271-maps.c { .rfmax = 47900, .val = 0x38 }, val 210 drivers/media/tuners/tda18271-maps.c { .rfmax = 61100, .val = 0x44 }, val 211 drivers/media/tuners/tda18271-maps.c { .rfmax = 350000, .val = 0x30 }, val 212 drivers/media/tuners/tda18271-maps.c { .rfmax = 720000, .val = 0x24 }, val 213 drivers/media/tuners/tda18271-maps.c { .rfmax = 865000, .val = 0x3c }, val 214 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0x00 }, /* end */ val 218 drivers/media/tuners/tda18271-maps.c { .rfmax = 47900, .val = 0x00 }, val 219 drivers/media/tuners/tda18271-maps.c { .rfmax = 61100, .val = 0x01 }, val 220 drivers/media/tuners/tda18271-maps.c { .rfmax = 152600, .val = 0x02 }, val 221 drivers/media/tuners/tda18271-maps.c { .rfmax = 164700, .val = 0x03 }, val 222 drivers/media/tuners/tda18271-maps.c { .rfmax = 203500, .val = 0x04 }, val 223 drivers/media/tuners/tda18271-maps.c { .rfmax = 457800, .val = 0x05 }, val 224 drivers/media/tuners/tda18271-maps.c { .rfmax = 865000, .val = 0x06 }, val 225 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0x00 }, /* end */ val 229 drivers/media/tuners/tda18271-maps.c { .rfmax = 45400, .val = 0x1f }, val 230 drivers/media/tuners/tda18271-maps.c { .rfmax = 45800, .val = 0x1e }, val 231 drivers/media/tuners/tda18271-maps.c { .rfmax = 46200, .val = 0x1d }, val 232 drivers/media/tuners/tda18271-maps.c { .rfmax = 46700, .val = 0x1c }, val 233 drivers/media/tuners/tda18271-maps.c { .rfmax = 47100, .val = 0x1b }, val 234 drivers/media/tuners/tda18271-maps.c { .rfmax = 47500, .val = 0x1a }, val 235 drivers/media/tuners/tda18271-maps.c { .rfmax = 47900, .val = 0x19 }, val 236 drivers/media/tuners/tda18271-maps.c { .rfmax = 49600, .val = 0x17 }, val 237 drivers/media/tuners/tda18271-maps.c { .rfmax = 51200, .val = 0x16 }, val 238 drivers/media/tuners/tda18271-maps.c { .rfmax = 52900, .val = 0x15 }, val 239 drivers/media/tuners/tda18271-maps.c { .rfmax = 54500, .val = 0x14 }, val 240 drivers/media/tuners/tda18271-maps.c { .rfmax = 56200, .val = 0x13 }, val 241 drivers/media/tuners/tda18271-maps.c { .rfmax = 57800, .val = 0x12 }, val 242 drivers/media/tuners/tda18271-maps.c { .rfmax = 59500, .val = 0x11 }, val 243 drivers/media/tuners/tda18271-maps.c { .rfmax = 61100, .val = 0x10 }, val 244 drivers/media/tuners/tda18271-maps.c { .rfmax = 67600, .val = 0x0d }, val 245 drivers/media/tuners/tda18271-maps.c { .rfmax = 74200, .val = 0x0c }, val 246 drivers/media/tuners/tda18271-maps.c { .rfmax = 80700, .val = 0x0b }, val 247 drivers/media/tuners/tda18271-maps.c { .rfmax = 87200, .val = 0x0a }, val 248 drivers/media/tuners/tda18271-maps.c { .rfmax = 93800, .val = 0x09 }, val 249 drivers/media/tuners/tda18271-maps.c { .rfmax = 100300, .val = 0x08 }, val 250 drivers/media/tuners/tda18271-maps.c { .rfmax = 106900, .val = 0x07 }, val 251 drivers/media/tuners/tda18271-maps.c { .rfmax = 113400, .val = 0x06 }, val 252 drivers/media/tuners/tda18271-maps.c { .rfmax = 119900, .val = 0x05 }, val 253 drivers/media/tuners/tda18271-maps.c { .rfmax = 126500, .val = 0x04 }, val 254 drivers/media/tuners/tda18271-maps.c { .rfmax = 133000, .val = 0x03 }, val 255 drivers/media/tuners/tda18271-maps.c { .rfmax = 139500, .val = 0x02 }, val 256 drivers/media/tuners/tda18271-maps.c { .rfmax = 146100, .val = 0x01 }, val 257 drivers/media/tuners/tda18271-maps.c { .rfmax = 152600, .val = 0x00 }, val 258 drivers/media/tuners/tda18271-maps.c { .rfmax = 154300, .val = 0x1f }, val 259 drivers/media/tuners/tda18271-maps.c { .rfmax = 156100, .val = 0x1e }, val 260 drivers/media/tuners/tda18271-maps.c { .rfmax = 157800, .val = 0x1d }, val 261 drivers/media/tuners/tda18271-maps.c { .rfmax = 159500, .val = 0x1c }, val 262 drivers/media/tuners/tda18271-maps.c { .rfmax = 161200, .val = 0x1b }, val 263 drivers/media/tuners/tda18271-maps.c { .rfmax = 163000, .val = 0x1a }, val 264 drivers/media/tuners/tda18271-maps.c { .rfmax = 164700, .val = 0x19 }, val 265 drivers/media/tuners/tda18271-maps.c { .rfmax = 170200, .val = 0x17 }, val 266 drivers/media/tuners/tda18271-maps.c { .rfmax = 175800, .val = 0x16 }, val 267 drivers/media/tuners/tda18271-maps.c { .rfmax = 181300, .val = 0x15 }, val 268 drivers/media/tuners/tda18271-maps.c { .rfmax = 186900, .val = 0x14 }, val 269 drivers/media/tuners/tda18271-maps.c { .rfmax = 192400, .val = 0x13 }, val 270 drivers/media/tuners/tda18271-maps.c { .rfmax = 198000, .val = 0x12 }, val 271 drivers/media/tuners/tda18271-maps.c { .rfmax = 203500, .val = 0x11 }, val 272 drivers/media/tuners/tda18271-maps.c { .rfmax = 216200, .val = 0x14 }, val 273 drivers/media/tuners/tda18271-maps.c { .rfmax = 228900, .val = 0x13 }, val 274 drivers/media/tuners/tda18271-maps.c { .rfmax = 241600, .val = 0x12 }, val 275 drivers/media/tuners/tda18271-maps.c { .rfmax = 254400, .val = 0x11 }, val 276 drivers/media/tuners/tda18271-maps.c { .rfmax = 267100, .val = 0x10 }, val 277 drivers/media/tuners/tda18271-maps.c { .rfmax = 279800, .val = 0x0f }, val 278 drivers/media/tuners/tda18271-maps.c { .rfmax = 292500, .val = 0x0e }, val 279 drivers/media/tuners/tda18271-maps.c { .rfmax = 305200, .val = 0x0d }, val 280 drivers/media/tuners/tda18271-maps.c { .rfmax = 317900, .val = 0x0c }, val 281 drivers/media/tuners/tda18271-maps.c { .rfmax = 330700, .val = 0x0b }, val 282 drivers/media/tuners/tda18271-maps.c { .rfmax = 343400, .val = 0x0a }, val 283 drivers/media/tuners/tda18271-maps.c { .rfmax = 356100, .val = 0x09 }, val 284 drivers/media/tuners/tda18271-maps.c { .rfmax = 368800, .val = 0x08 }, val 285 drivers/media/tuners/tda18271-maps.c { .rfmax = 381500, .val = 0x07 }, val 286 drivers/media/tuners/tda18271-maps.c { .rfmax = 394200, .val = 0x06 }, val 287 drivers/media/tuners/tda18271-maps.c { .rfmax = 406900, .val = 0x05 }, val 288 drivers/media/tuners/tda18271-maps.c { .rfmax = 419700, .val = 0x04 }, val 289 drivers/media/tuners/tda18271-maps.c { .rfmax = 432400, .val = 0x03 }, val 290 drivers/media/tuners/tda18271-maps.c { .rfmax = 445100, .val = 0x02 }, val 291 drivers/media/tuners/tda18271-maps.c { .rfmax = 457800, .val = 0x01 }, val 292 drivers/media/tuners/tda18271-maps.c { .rfmax = 476300, .val = 0x19 }, val 293 drivers/media/tuners/tda18271-maps.c { .rfmax = 494800, .val = 0x18 }, val 294 drivers/media/tuners/tda18271-maps.c { .rfmax = 513300, .val = 0x17 }, val 295 drivers/media/tuners/tda18271-maps.c { .rfmax = 531800, .val = 0x16 }, val 296 drivers/media/tuners/tda18271-maps.c { .rfmax = 550300, .val = 0x15 }, val 297 drivers/media/tuners/tda18271-maps.c { .rfmax = 568900, .val = 0x14 }, val 298 drivers/media/tuners/tda18271-maps.c { .rfmax = 587400, .val = 0x13 }, val 299 drivers/media/tuners/tda18271-maps.c { .rfmax = 605900, .val = 0x12 }, val 300 drivers/media/tuners/tda18271-maps.c { .rfmax = 624400, .val = 0x11 }, val 301 drivers/media/tuners/tda18271-maps.c { .rfmax = 642900, .val = 0x10 }, val 302 drivers/media/tuners/tda18271-maps.c { .rfmax = 661400, .val = 0x0f }, val 303 drivers/media/tuners/tda18271-maps.c { .rfmax = 679900, .val = 0x0e }, val 304 drivers/media/tuners/tda18271-maps.c { .rfmax = 698400, .val = 0x0d }, val 305 drivers/media/tuners/tda18271-maps.c { .rfmax = 716900, .val = 0x0c }, val 306 drivers/media/tuners/tda18271-maps.c { .rfmax = 735400, .val = 0x0b }, val 307 drivers/media/tuners/tda18271-maps.c { .rfmax = 753900, .val = 0x0a }, val 308 drivers/media/tuners/tda18271-maps.c { .rfmax = 772500, .val = 0x09 }, val 309 drivers/media/tuners/tda18271-maps.c { .rfmax = 791000, .val = 0x08 }, val 310 drivers/media/tuners/tda18271-maps.c { .rfmax = 809500, .val = 0x07 }, val 311 drivers/media/tuners/tda18271-maps.c { .rfmax = 828000, .val = 0x06 }, val 312 drivers/media/tuners/tda18271-maps.c { .rfmax = 846500, .val = 0x05 }, val 313 drivers/media/tuners/tda18271-maps.c { .rfmax = 865000, .val = 0x04 }, val 314 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0x00 }, /* end */ val 318 drivers/media/tuners/tda18271-maps.c { .rfmax = 41000, .val = 0x1e }, val 319 drivers/media/tuners/tda18271-maps.c { .rfmax = 43000, .val = 0x30 }, val 320 drivers/media/tuners/tda18271-maps.c { .rfmax = 45000, .val = 0x43 }, val 321 drivers/media/tuners/tda18271-maps.c { .rfmax = 46000, .val = 0x4d }, val 322 drivers/media/tuners/tda18271-maps.c { .rfmax = 47000, .val = 0x54 }, val 323 drivers/media/tuners/tda18271-maps.c { .rfmax = 47900, .val = 0x64 }, val 324 drivers/media/tuners/tda18271-maps.c { .rfmax = 49100, .val = 0x20 }, val 325 drivers/media/tuners/tda18271-maps.c { .rfmax = 50000, .val = 0x22 }, val 326 drivers/media/tuners/tda18271-maps.c { .rfmax = 51000, .val = 0x2a }, val 327 drivers/media/tuners/tda18271-maps.c { .rfmax = 53000, .val = 0x32 }, val 328 drivers/media/tuners/tda18271-maps.c { .rfmax = 55000, .val = 0x35 }, val 329 drivers/media/tuners/tda18271-maps.c { .rfmax = 56000, .val = 0x3c }, val 330 drivers/media/tuners/tda18271-maps.c { .rfmax = 57000, .val = 0x3f }, val 331 drivers/media/tuners/tda18271-maps.c { .rfmax = 58000, .val = 0x48 }, val 332 drivers/media/tuners/tda18271-maps.c { .rfmax = 59000, .val = 0x4d }, val 333 drivers/media/tuners/tda18271-maps.c { .rfmax = 60000, .val = 0x58 }, val 334 drivers/media/tuners/tda18271-maps.c { .rfmax = 61100, .val = 0x5f }, val 335 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0x00 }, /* end */ val 339 drivers/media/tuners/tda18271-maps.c { .rfmax = 41000, .val = 0x0f }, val 340 drivers/media/tuners/tda18271-maps.c { .rfmax = 43000, .val = 0x1c }, val 341 drivers/media/tuners/tda18271-maps.c { .rfmax = 45000, .val = 0x2f }, val 342 drivers/media/tuners/tda18271-maps.c { .rfmax = 46000, .val = 0x39 }, val 343 drivers/media/tuners/tda18271-maps.c { .rfmax = 47000, .val = 0x40 }, val 344 drivers/media/tuners/tda18271-maps.c { .rfmax = 47900, .val = 0x50 }, val 345 drivers/media/tuners/tda18271-maps.c { .rfmax = 49100, .val = 0x16 }, val 346 drivers/media/tuners/tda18271-maps.c { .rfmax = 50000, .val = 0x18 }, val 347 drivers/media/tuners/tda18271-maps.c { .rfmax = 51000, .val = 0x20 }, val 348 drivers/media/tuners/tda18271-maps.c { .rfmax = 53000, .val = 0x28 }, val 349 drivers/media/tuners/tda18271-maps.c { .rfmax = 55000, .val = 0x2b }, val 350 drivers/media/tuners/tda18271-maps.c { .rfmax = 56000, .val = 0x32 }, val 351 drivers/media/tuners/tda18271-maps.c { .rfmax = 57000, .val = 0x35 }, val 352 drivers/media/tuners/tda18271-maps.c { .rfmax = 58000, .val = 0x3e }, val 353 drivers/media/tuners/tda18271-maps.c { .rfmax = 59000, .val = 0x43 }, val 354 drivers/media/tuners/tda18271-maps.c { .rfmax = 60000, .val = 0x4e }, val 355 drivers/media/tuners/tda18271-maps.c { .rfmax = 61100, .val = 0x55 }, val 356 drivers/media/tuners/tda18271-maps.c { .rfmax = 63000, .val = 0x0f }, val 357 drivers/media/tuners/tda18271-maps.c { .rfmax = 64000, .val = 0x11 }, val 358 drivers/media/tuners/tda18271-maps.c { .rfmax = 65000, .val = 0x12 }, val 359 drivers/media/tuners/tda18271-maps.c { .rfmax = 66000, .val = 0x15 }, val 360 drivers/media/tuners/tda18271-maps.c { .rfmax = 67000, .val = 0x16 }, val 361 drivers/media/tuners/tda18271-maps.c { .rfmax = 68000, .val = 0x17 }, val 362 drivers/media/tuners/tda18271-maps.c { .rfmax = 70000, .val = 0x19 }, val 363 drivers/media/tuners/tda18271-maps.c { .rfmax = 71000, .val = 0x1c }, val 364 drivers/media/tuners/tda18271-maps.c { .rfmax = 72000, .val = 0x1d }, val 365 drivers/media/tuners/tda18271-maps.c { .rfmax = 73000, .val = 0x1f }, val 366 drivers/media/tuners/tda18271-maps.c { .rfmax = 74000, .val = 0x20 }, val 367 drivers/media/tuners/tda18271-maps.c { .rfmax = 75000, .val = 0x21 }, val 368 drivers/media/tuners/tda18271-maps.c { .rfmax = 76000, .val = 0x24 }, val 369 drivers/media/tuners/tda18271-maps.c { .rfmax = 77000, .val = 0x25 }, val 370 drivers/media/tuners/tda18271-maps.c { .rfmax = 78000, .val = 0x27 }, val 371 drivers/media/tuners/tda18271-maps.c { .rfmax = 80000, .val = 0x28 }, val 372 drivers/media/tuners/tda18271-maps.c { .rfmax = 81000, .val = 0x29 }, val 373 drivers/media/tuners/tda18271-maps.c { .rfmax = 82000, .val = 0x2d }, val 374 drivers/media/tuners/tda18271-maps.c { .rfmax = 83000, .val = 0x2e }, val 375 drivers/media/tuners/tda18271-maps.c { .rfmax = 84000, .val = 0x2f }, val 376 drivers/media/tuners/tda18271-maps.c { .rfmax = 85000, .val = 0x31 }, val 377 drivers/media/tuners/tda18271-maps.c { .rfmax = 86000, .val = 0x33 }, val 378 drivers/media/tuners/tda18271-maps.c { .rfmax = 87000, .val = 0x34 }, val 379 drivers/media/tuners/tda18271-maps.c { .rfmax = 88000, .val = 0x35 }, val 380 drivers/media/tuners/tda18271-maps.c { .rfmax = 89000, .val = 0x37 }, val 381 drivers/media/tuners/tda18271-maps.c { .rfmax = 90000, .val = 0x38 }, val 382 drivers/media/tuners/tda18271-maps.c { .rfmax = 91000, .val = 0x39 }, val 383 drivers/media/tuners/tda18271-maps.c { .rfmax = 93000, .val = 0x3c }, val 384 drivers/media/tuners/tda18271-maps.c { .rfmax = 94000, .val = 0x3e }, val 385 drivers/media/tuners/tda18271-maps.c { .rfmax = 95000, .val = 0x3f }, val 386 drivers/media/tuners/tda18271-maps.c { .rfmax = 96000, .val = 0x40 }, val 387 drivers/media/tuners/tda18271-maps.c { .rfmax = 97000, .val = 0x42 }, val 388 drivers/media/tuners/tda18271-maps.c { .rfmax = 99000, .val = 0x45 }, val 389 drivers/media/tuners/tda18271-maps.c { .rfmax = 100000, .val = 0x46 }, val 390 drivers/media/tuners/tda18271-maps.c { .rfmax = 102000, .val = 0x48 }, val 391 drivers/media/tuners/tda18271-maps.c { .rfmax = 103000, .val = 0x4a }, val 392 drivers/media/tuners/tda18271-maps.c { .rfmax = 105000, .val = 0x4d }, val 393 drivers/media/tuners/tda18271-maps.c { .rfmax = 106000, .val = 0x4e }, val 394 drivers/media/tuners/tda18271-maps.c { .rfmax = 107000, .val = 0x50 }, val 395 drivers/media/tuners/tda18271-maps.c { .rfmax = 108000, .val = 0x51 }, val 396 drivers/media/tuners/tda18271-maps.c { .rfmax = 110000, .val = 0x54 }, val 397 drivers/media/tuners/tda18271-maps.c { .rfmax = 111000, .val = 0x56 }, val 398 drivers/media/tuners/tda18271-maps.c { .rfmax = 112000, .val = 0x57 }, val 399 drivers/media/tuners/tda18271-maps.c { .rfmax = 113000, .val = 0x58 }, val 400 drivers/media/tuners/tda18271-maps.c { .rfmax = 114000, .val = 0x59 }, val 401 drivers/media/tuners/tda18271-maps.c { .rfmax = 115000, .val = 0x5c }, val 402 drivers/media/tuners/tda18271-maps.c { .rfmax = 116000, .val = 0x5d }, val 403 drivers/media/tuners/tda18271-maps.c { .rfmax = 117000, .val = 0x5f }, val 404 drivers/media/tuners/tda18271-maps.c { .rfmax = 119000, .val = 0x60 }, val 405 drivers/media/tuners/tda18271-maps.c { .rfmax = 120000, .val = 0x64 }, val 406 drivers/media/tuners/tda18271-maps.c { .rfmax = 121000, .val = 0x65 }, val 407 drivers/media/tuners/tda18271-maps.c { .rfmax = 122000, .val = 0x66 }, val 408 drivers/media/tuners/tda18271-maps.c { .rfmax = 123000, .val = 0x68 }, val 409 drivers/media/tuners/tda18271-maps.c { .rfmax = 124000, .val = 0x69 }, val 410 drivers/media/tuners/tda18271-maps.c { .rfmax = 125000, .val = 0x6c }, val 411 drivers/media/tuners/tda18271-maps.c { .rfmax = 126000, .val = 0x6d }, val 412 drivers/media/tuners/tda18271-maps.c { .rfmax = 127000, .val = 0x6e }, val 413 drivers/media/tuners/tda18271-maps.c { .rfmax = 128000, .val = 0x70 }, val 414 drivers/media/tuners/tda18271-maps.c { .rfmax = 129000, .val = 0x71 }, val 415 drivers/media/tuners/tda18271-maps.c { .rfmax = 130000, .val = 0x75 }, val 416 drivers/media/tuners/tda18271-maps.c { .rfmax = 131000, .val = 0x77 }, val 417 drivers/media/tuners/tda18271-maps.c { .rfmax = 132000, .val = 0x78 }, val 418 drivers/media/tuners/tda18271-maps.c { .rfmax = 133000, .val = 0x7b }, val 419 drivers/media/tuners/tda18271-maps.c { .rfmax = 134000, .val = 0x7e }, val 420 drivers/media/tuners/tda18271-maps.c { .rfmax = 135000, .val = 0x81 }, val 421 drivers/media/tuners/tda18271-maps.c { .rfmax = 136000, .val = 0x82 }, val 422 drivers/media/tuners/tda18271-maps.c { .rfmax = 137000, .val = 0x87 }, val 423 drivers/media/tuners/tda18271-maps.c { .rfmax = 138000, .val = 0x88 }, val 424 drivers/media/tuners/tda18271-maps.c { .rfmax = 139000, .val = 0x8d }, val 425 drivers/media/tuners/tda18271-maps.c { .rfmax = 140000, .val = 0x8e }, val 426 drivers/media/tuners/tda18271-maps.c { .rfmax = 141000, .val = 0x91 }, val 427 drivers/media/tuners/tda18271-maps.c { .rfmax = 142000, .val = 0x95 }, val 428 drivers/media/tuners/tda18271-maps.c { .rfmax = 143000, .val = 0x9a }, val 429 drivers/media/tuners/tda18271-maps.c { .rfmax = 144000, .val = 0x9d }, val 430 drivers/media/tuners/tda18271-maps.c { .rfmax = 145000, .val = 0xa1 }, val 431 drivers/media/tuners/tda18271-maps.c { .rfmax = 146000, .val = 0xa2 }, val 432 drivers/media/tuners/tda18271-maps.c { .rfmax = 147000, .val = 0xa4 }, val 433 drivers/media/tuners/tda18271-maps.c { .rfmax = 148000, .val = 0xa9 }, val 434 drivers/media/tuners/tda18271-maps.c { .rfmax = 149000, .val = 0xae }, val 435 drivers/media/tuners/tda18271-maps.c { .rfmax = 150000, .val = 0xb0 }, val 436 drivers/media/tuners/tda18271-maps.c { .rfmax = 151000, .val = 0xb1 }, val 437 drivers/media/tuners/tda18271-maps.c { .rfmax = 152000, .val = 0xb7 }, val 438 drivers/media/tuners/tda18271-maps.c { .rfmax = 152600, .val = 0xbd }, val 439 drivers/media/tuners/tda18271-maps.c { .rfmax = 154000, .val = 0x20 }, val 440 drivers/media/tuners/tda18271-maps.c { .rfmax = 155000, .val = 0x22 }, val 441 drivers/media/tuners/tda18271-maps.c { .rfmax = 156000, .val = 0x24 }, val 442 drivers/media/tuners/tda18271-maps.c { .rfmax = 157000, .val = 0x25 }, val 443 drivers/media/tuners/tda18271-maps.c { .rfmax = 158000, .val = 0x27 }, val 444 drivers/media/tuners/tda18271-maps.c { .rfmax = 159000, .val = 0x29 }, val 445 drivers/media/tuners/tda18271-maps.c { .rfmax = 160000, .val = 0x2c }, val 446 drivers/media/tuners/tda18271-maps.c { .rfmax = 161000, .val = 0x2d }, val 447 drivers/media/tuners/tda18271-maps.c { .rfmax = 163000, .val = 0x2e }, val 448 drivers/media/tuners/tda18271-maps.c { .rfmax = 164000, .val = 0x2f }, val 449 drivers/media/tuners/tda18271-maps.c { .rfmax = 164700, .val = 0x30 }, val 450 drivers/media/tuners/tda18271-maps.c { .rfmax = 166000, .val = 0x11 }, val 451 drivers/media/tuners/tda18271-maps.c { .rfmax = 167000, .val = 0x12 }, val 452 drivers/media/tuners/tda18271-maps.c { .rfmax = 168000, .val = 0x13 }, val 453 drivers/media/tuners/tda18271-maps.c { .rfmax = 169000, .val = 0x14 }, val 454 drivers/media/tuners/tda18271-maps.c { .rfmax = 170000, .val = 0x15 }, val 455 drivers/media/tuners/tda18271-maps.c { .rfmax = 172000, .val = 0x16 }, val 456 drivers/media/tuners/tda18271-maps.c { .rfmax = 173000, .val = 0x17 }, val 457 drivers/media/tuners/tda18271-maps.c { .rfmax = 174000, .val = 0x18 }, val 458 drivers/media/tuners/tda18271-maps.c { .rfmax = 175000, .val = 0x1a }, val 459 drivers/media/tuners/tda18271-maps.c { .rfmax = 176000, .val = 0x1b }, val 460 drivers/media/tuners/tda18271-maps.c { .rfmax = 178000, .val = 0x1d }, val 461 drivers/media/tuners/tda18271-maps.c { .rfmax = 179000, .val = 0x1e }, val 462 drivers/media/tuners/tda18271-maps.c { .rfmax = 180000, .val = 0x1f }, val 463 drivers/media/tuners/tda18271-maps.c { .rfmax = 181000, .val = 0x20 }, val 464 drivers/media/tuners/tda18271-maps.c { .rfmax = 182000, .val = 0x21 }, val 465 drivers/media/tuners/tda18271-maps.c { .rfmax = 183000, .val = 0x22 }, val 466 drivers/media/tuners/tda18271-maps.c { .rfmax = 184000, .val = 0x24 }, val 467 drivers/media/tuners/tda18271-maps.c { .rfmax = 185000, .val = 0x25 }, val 468 drivers/media/tuners/tda18271-maps.c { .rfmax = 186000, .val = 0x26 }, val 469 drivers/media/tuners/tda18271-maps.c { .rfmax = 187000, .val = 0x27 }, val 470 drivers/media/tuners/tda18271-maps.c { .rfmax = 188000, .val = 0x29 }, val 471 drivers/media/tuners/tda18271-maps.c { .rfmax = 189000, .val = 0x2a }, val 472 drivers/media/tuners/tda18271-maps.c { .rfmax = 190000, .val = 0x2c }, val 473 drivers/media/tuners/tda18271-maps.c { .rfmax = 191000, .val = 0x2d }, val 474 drivers/media/tuners/tda18271-maps.c { .rfmax = 192000, .val = 0x2e }, val 475 drivers/media/tuners/tda18271-maps.c { .rfmax = 193000, .val = 0x2f }, val 476 drivers/media/tuners/tda18271-maps.c { .rfmax = 194000, .val = 0x30 }, val 477 drivers/media/tuners/tda18271-maps.c { .rfmax = 195000, .val = 0x33 }, val 478 drivers/media/tuners/tda18271-maps.c { .rfmax = 196000, .val = 0x35 }, val 479 drivers/media/tuners/tda18271-maps.c { .rfmax = 198000, .val = 0x36 }, val 480 drivers/media/tuners/tda18271-maps.c { .rfmax = 200000, .val = 0x38 }, val 481 drivers/media/tuners/tda18271-maps.c { .rfmax = 201000, .val = 0x3c }, val 482 drivers/media/tuners/tda18271-maps.c { .rfmax = 202000, .val = 0x3d }, val 483 drivers/media/tuners/tda18271-maps.c { .rfmax = 203500, .val = 0x3e }, val 484 drivers/media/tuners/tda18271-maps.c { .rfmax = 206000, .val = 0x0e }, val 485 drivers/media/tuners/tda18271-maps.c { .rfmax = 208000, .val = 0x0f }, val 486 drivers/media/tuners/tda18271-maps.c { .rfmax = 212000, .val = 0x10 }, val 487 drivers/media/tuners/tda18271-maps.c { .rfmax = 216000, .val = 0x11 }, val 488 drivers/media/tuners/tda18271-maps.c { .rfmax = 217000, .val = 0x12 }, val 489 drivers/media/tuners/tda18271-maps.c { .rfmax = 218000, .val = 0x13 }, val 490 drivers/media/tuners/tda18271-maps.c { .rfmax = 220000, .val = 0x14 }, val 491 drivers/media/tuners/tda18271-maps.c { .rfmax = 222000, .val = 0x15 }, val 492 drivers/media/tuners/tda18271-maps.c { .rfmax = 225000, .val = 0x16 }, val 493 drivers/media/tuners/tda18271-maps.c { .rfmax = 228000, .val = 0x17 }, val 494 drivers/media/tuners/tda18271-maps.c { .rfmax = 231000, .val = 0x18 }, val 495 drivers/media/tuners/tda18271-maps.c { .rfmax = 234000, .val = 0x19 }, val 496 drivers/media/tuners/tda18271-maps.c { .rfmax = 235000, .val = 0x1a }, val 497 drivers/media/tuners/tda18271-maps.c { .rfmax = 236000, .val = 0x1b }, val 498 drivers/media/tuners/tda18271-maps.c { .rfmax = 237000, .val = 0x1c }, val 499 drivers/media/tuners/tda18271-maps.c { .rfmax = 240000, .val = 0x1d }, val 500 drivers/media/tuners/tda18271-maps.c { .rfmax = 242000, .val = 0x1e }, val 501 drivers/media/tuners/tda18271-maps.c { .rfmax = 244000, .val = 0x1f }, val 502 drivers/media/tuners/tda18271-maps.c { .rfmax = 247000, .val = 0x20 }, val 503 drivers/media/tuners/tda18271-maps.c { .rfmax = 249000, .val = 0x21 }, val 504 drivers/media/tuners/tda18271-maps.c { .rfmax = 252000, .val = 0x22 }, val 505 drivers/media/tuners/tda18271-maps.c { .rfmax = 253000, .val = 0x23 }, val 506 drivers/media/tuners/tda18271-maps.c { .rfmax = 254000, .val = 0x24 }, val 507 drivers/media/tuners/tda18271-maps.c { .rfmax = 256000, .val = 0x25 }, val 508 drivers/media/tuners/tda18271-maps.c { .rfmax = 259000, .val = 0x26 }, val 509 drivers/media/tuners/tda18271-maps.c { .rfmax = 262000, .val = 0x27 }, val 510 drivers/media/tuners/tda18271-maps.c { .rfmax = 264000, .val = 0x28 }, val 511 drivers/media/tuners/tda18271-maps.c { .rfmax = 267000, .val = 0x29 }, val 512 drivers/media/tuners/tda18271-maps.c { .rfmax = 269000, .val = 0x2a }, val 513 drivers/media/tuners/tda18271-maps.c { .rfmax = 271000, .val = 0x2b }, val 514 drivers/media/tuners/tda18271-maps.c { .rfmax = 273000, .val = 0x2c }, val 515 drivers/media/tuners/tda18271-maps.c { .rfmax = 275000, .val = 0x2d }, val 516 drivers/media/tuners/tda18271-maps.c { .rfmax = 277000, .val = 0x2e }, val 517 drivers/media/tuners/tda18271-maps.c { .rfmax = 279000, .val = 0x2f }, val 518 drivers/media/tuners/tda18271-maps.c { .rfmax = 282000, .val = 0x30 }, val 519 drivers/media/tuners/tda18271-maps.c { .rfmax = 284000, .val = 0x31 }, val 520 drivers/media/tuners/tda18271-maps.c { .rfmax = 286000, .val = 0x32 }, val 521 drivers/media/tuners/tda18271-maps.c { .rfmax = 287000, .val = 0x33 }, val 522 drivers/media/tuners/tda18271-maps.c { .rfmax = 290000, .val = 0x34 }, val 523 drivers/media/tuners/tda18271-maps.c { .rfmax = 293000, .val = 0x35 }, val 524 drivers/media/tuners/tda18271-maps.c { .rfmax = 295000, .val = 0x36 }, val 525 drivers/media/tuners/tda18271-maps.c { .rfmax = 297000, .val = 0x37 }, val 526 drivers/media/tuners/tda18271-maps.c { .rfmax = 300000, .val = 0x38 }, val 527 drivers/media/tuners/tda18271-maps.c { .rfmax = 303000, .val = 0x39 }, val 528 drivers/media/tuners/tda18271-maps.c { .rfmax = 305000, .val = 0x3a }, val 529 drivers/media/tuners/tda18271-maps.c { .rfmax = 306000, .val = 0x3b }, val 530 drivers/media/tuners/tda18271-maps.c { .rfmax = 307000, .val = 0x3c }, val 531 drivers/media/tuners/tda18271-maps.c { .rfmax = 310000, .val = 0x3d }, val 532 drivers/media/tuners/tda18271-maps.c { .rfmax = 312000, .val = 0x3e }, val 533 drivers/media/tuners/tda18271-maps.c { .rfmax = 315000, .val = 0x3f }, val 534 drivers/media/tuners/tda18271-maps.c { .rfmax = 318000, .val = 0x40 }, val 535 drivers/media/tuners/tda18271-maps.c { .rfmax = 320000, .val = 0x41 }, val 536 drivers/media/tuners/tda18271-maps.c { .rfmax = 323000, .val = 0x42 }, val 537 drivers/media/tuners/tda18271-maps.c { .rfmax = 324000, .val = 0x43 }, val 538 drivers/media/tuners/tda18271-maps.c { .rfmax = 325000, .val = 0x44 }, val 539 drivers/media/tuners/tda18271-maps.c { .rfmax = 327000, .val = 0x45 }, val 540 drivers/media/tuners/tda18271-maps.c { .rfmax = 331000, .val = 0x46 }, val 541 drivers/media/tuners/tda18271-maps.c { .rfmax = 334000, .val = 0x47 }, val 542 drivers/media/tuners/tda18271-maps.c { .rfmax = 337000, .val = 0x48 }, val 543 drivers/media/tuners/tda18271-maps.c { .rfmax = 339000, .val = 0x49 }, val 544 drivers/media/tuners/tda18271-maps.c { .rfmax = 340000, .val = 0x4a }, val 545 drivers/media/tuners/tda18271-maps.c { .rfmax = 341000, .val = 0x4b }, val 546 drivers/media/tuners/tda18271-maps.c { .rfmax = 343000, .val = 0x4c }, val 547 drivers/media/tuners/tda18271-maps.c { .rfmax = 345000, .val = 0x4d }, val 548 drivers/media/tuners/tda18271-maps.c { .rfmax = 349000, .val = 0x4e }, val 549 drivers/media/tuners/tda18271-maps.c { .rfmax = 352000, .val = 0x4f }, val 550 drivers/media/tuners/tda18271-maps.c { .rfmax = 353000, .val = 0x50 }, val 551 drivers/media/tuners/tda18271-maps.c { .rfmax = 355000, .val = 0x51 }, val 552 drivers/media/tuners/tda18271-maps.c { .rfmax = 357000, .val = 0x52 }, val 553 drivers/media/tuners/tda18271-maps.c { .rfmax = 359000, .val = 0x53 }, val 554 drivers/media/tuners/tda18271-maps.c { .rfmax = 361000, .val = 0x54 }, val 555 drivers/media/tuners/tda18271-maps.c { .rfmax = 362000, .val = 0x55 }, val 556 drivers/media/tuners/tda18271-maps.c { .rfmax = 364000, .val = 0x56 }, val 557 drivers/media/tuners/tda18271-maps.c { .rfmax = 368000, .val = 0x57 }, val 558 drivers/media/tuners/tda18271-maps.c { .rfmax = 370000, .val = 0x58 }, val 559 drivers/media/tuners/tda18271-maps.c { .rfmax = 372000, .val = 0x59 }, val 560 drivers/media/tuners/tda18271-maps.c { .rfmax = 375000, .val = 0x5a }, val 561 drivers/media/tuners/tda18271-maps.c { .rfmax = 376000, .val = 0x5b }, val 562 drivers/media/tuners/tda18271-maps.c { .rfmax = 377000, .val = 0x5c }, val 563 drivers/media/tuners/tda18271-maps.c { .rfmax = 379000, .val = 0x5d }, val 564 drivers/media/tuners/tda18271-maps.c { .rfmax = 382000, .val = 0x5e }, val 565 drivers/media/tuners/tda18271-maps.c { .rfmax = 384000, .val = 0x5f }, val 566 drivers/media/tuners/tda18271-maps.c { .rfmax = 385000, .val = 0x60 }, val 567 drivers/media/tuners/tda18271-maps.c { .rfmax = 386000, .val = 0x61 }, val 568 drivers/media/tuners/tda18271-maps.c { .rfmax = 388000, .val = 0x62 }, val 569 drivers/media/tuners/tda18271-maps.c { .rfmax = 390000, .val = 0x63 }, val 570 drivers/media/tuners/tda18271-maps.c { .rfmax = 393000, .val = 0x64 }, val 571 drivers/media/tuners/tda18271-maps.c { .rfmax = 394000, .val = 0x65 }, val 572 drivers/media/tuners/tda18271-maps.c { .rfmax = 396000, .val = 0x66 }, val 573 drivers/media/tuners/tda18271-maps.c { .rfmax = 397000, .val = 0x67 }, val 574 drivers/media/tuners/tda18271-maps.c { .rfmax = 398000, .val = 0x68 }, val 575 drivers/media/tuners/tda18271-maps.c { .rfmax = 400000, .val = 0x69 }, val 576 drivers/media/tuners/tda18271-maps.c { .rfmax = 402000, .val = 0x6a }, val 577 drivers/media/tuners/tda18271-maps.c { .rfmax = 403000, .val = 0x6b }, val 578 drivers/media/tuners/tda18271-maps.c { .rfmax = 407000, .val = 0x6c }, val 579 drivers/media/tuners/tda18271-maps.c { .rfmax = 408000, .val = 0x6d }, val 580 drivers/media/tuners/tda18271-maps.c { .rfmax = 409000, .val = 0x6e }, val 581 drivers/media/tuners/tda18271-maps.c { .rfmax = 410000, .val = 0x6f }, val 582 drivers/media/tuners/tda18271-maps.c { .rfmax = 411000, .val = 0x70 }, val 583 drivers/media/tuners/tda18271-maps.c { .rfmax = 412000, .val = 0x71 }, val 584 drivers/media/tuners/tda18271-maps.c { .rfmax = 413000, .val = 0x72 }, val 585 drivers/media/tuners/tda18271-maps.c { .rfmax = 414000, .val = 0x73 }, val 586 drivers/media/tuners/tda18271-maps.c { .rfmax = 417000, .val = 0x74 }, val 587 drivers/media/tuners/tda18271-maps.c { .rfmax = 418000, .val = 0x75 }, val 588 drivers/media/tuners/tda18271-maps.c { .rfmax = 420000, .val = 0x76 }, val 589 drivers/media/tuners/tda18271-maps.c { .rfmax = 422000, .val = 0x77 }, val 590 drivers/media/tuners/tda18271-maps.c { .rfmax = 423000, .val = 0x78 }, val 591 drivers/media/tuners/tda18271-maps.c { .rfmax = 424000, .val = 0x79 }, val 592 drivers/media/tuners/tda18271-maps.c { .rfmax = 427000, .val = 0x7a }, val 593 drivers/media/tuners/tda18271-maps.c { .rfmax = 428000, .val = 0x7b }, val 594 drivers/media/tuners/tda18271-maps.c { .rfmax = 429000, .val = 0x7d }, val 595 drivers/media/tuners/tda18271-maps.c { .rfmax = 432000, .val = 0x7f }, val 596 drivers/media/tuners/tda18271-maps.c { .rfmax = 434000, .val = 0x80 }, val 597 drivers/media/tuners/tda18271-maps.c { .rfmax = 435000, .val = 0x81 }, val 598 drivers/media/tuners/tda18271-maps.c { .rfmax = 436000, .val = 0x83 }, val 599 drivers/media/tuners/tda18271-maps.c { .rfmax = 437000, .val = 0x84 }, val 600 drivers/media/tuners/tda18271-maps.c { .rfmax = 438000, .val = 0x85 }, val 601 drivers/media/tuners/tda18271-maps.c { .rfmax = 439000, .val = 0x86 }, val 602 drivers/media/tuners/tda18271-maps.c { .rfmax = 440000, .val = 0x87 }, val 603 drivers/media/tuners/tda18271-maps.c { .rfmax = 441000, .val = 0x88 }, val 604 drivers/media/tuners/tda18271-maps.c { .rfmax = 442000, .val = 0x89 }, val 605 drivers/media/tuners/tda18271-maps.c { .rfmax = 445000, .val = 0x8a }, val 606 drivers/media/tuners/tda18271-maps.c { .rfmax = 446000, .val = 0x8b }, val 607 drivers/media/tuners/tda18271-maps.c { .rfmax = 447000, .val = 0x8c }, val 608 drivers/media/tuners/tda18271-maps.c { .rfmax = 448000, .val = 0x8e }, val 609 drivers/media/tuners/tda18271-maps.c { .rfmax = 449000, .val = 0x8f }, val 610 drivers/media/tuners/tda18271-maps.c { .rfmax = 450000, .val = 0x90 }, val 611 drivers/media/tuners/tda18271-maps.c { .rfmax = 452000, .val = 0x91 }, val 612 drivers/media/tuners/tda18271-maps.c { .rfmax = 453000, .val = 0x93 }, val 613 drivers/media/tuners/tda18271-maps.c { .rfmax = 454000, .val = 0x94 }, val 614 drivers/media/tuners/tda18271-maps.c { .rfmax = 456000, .val = 0x96 }, val 615 drivers/media/tuners/tda18271-maps.c { .rfmax = 457800, .val = 0x98 }, val 616 drivers/media/tuners/tda18271-maps.c { .rfmax = 461000, .val = 0x11 }, val 617 drivers/media/tuners/tda18271-maps.c { .rfmax = 468000, .val = 0x12 }, val 618 drivers/media/tuners/tda18271-maps.c { .rfmax = 472000, .val = 0x13 }, val 619 drivers/media/tuners/tda18271-maps.c { .rfmax = 473000, .val = 0x14 }, val 620 drivers/media/tuners/tda18271-maps.c { .rfmax = 474000, .val = 0x15 }, val 621 drivers/media/tuners/tda18271-maps.c { .rfmax = 481000, .val = 0x16 }, val 622 drivers/media/tuners/tda18271-maps.c { .rfmax = 486000, .val = 0x17 }, val 623 drivers/media/tuners/tda18271-maps.c { .rfmax = 491000, .val = 0x18 }, val 624 drivers/media/tuners/tda18271-maps.c { .rfmax = 498000, .val = 0x19 }, val 625 drivers/media/tuners/tda18271-maps.c { .rfmax = 499000, .val = 0x1a }, val 626 drivers/media/tuners/tda18271-maps.c { .rfmax = 501000, .val = 0x1b }, val 627 drivers/media/tuners/tda18271-maps.c { .rfmax = 506000, .val = 0x1c }, val 628 drivers/media/tuners/tda18271-maps.c { .rfmax = 511000, .val = 0x1d }, val 629 drivers/media/tuners/tda18271-maps.c { .rfmax = 516000, .val = 0x1e }, val 630 drivers/media/tuners/tda18271-maps.c { .rfmax = 520000, .val = 0x1f }, val 631 drivers/media/tuners/tda18271-maps.c { .rfmax = 521000, .val = 0x20 }, val 632 drivers/media/tuners/tda18271-maps.c { .rfmax = 525000, .val = 0x21 }, val 633 drivers/media/tuners/tda18271-maps.c { .rfmax = 529000, .val = 0x22 }, val 634 drivers/media/tuners/tda18271-maps.c { .rfmax = 533000, .val = 0x23 }, val 635 drivers/media/tuners/tda18271-maps.c { .rfmax = 539000, .val = 0x24 }, val 636 drivers/media/tuners/tda18271-maps.c { .rfmax = 541000, .val = 0x25 }, val 637 drivers/media/tuners/tda18271-maps.c { .rfmax = 547000, .val = 0x26 }, val 638 drivers/media/tuners/tda18271-maps.c { .rfmax = 549000, .val = 0x27 }, val 639 drivers/media/tuners/tda18271-maps.c { .rfmax = 551000, .val = 0x28 }, val 640 drivers/media/tuners/tda18271-maps.c { .rfmax = 556000, .val = 0x29 }, val 641 drivers/media/tuners/tda18271-maps.c { .rfmax = 561000, .val = 0x2a }, val 642 drivers/media/tuners/tda18271-maps.c { .rfmax = 563000, .val = 0x2b }, val 643 drivers/media/tuners/tda18271-maps.c { .rfmax = 565000, .val = 0x2c }, val 644 drivers/media/tuners/tda18271-maps.c { .rfmax = 569000, .val = 0x2d }, val 645 drivers/media/tuners/tda18271-maps.c { .rfmax = 571000, .val = 0x2e }, val 646 drivers/media/tuners/tda18271-maps.c { .rfmax = 577000, .val = 0x2f }, val 647 drivers/media/tuners/tda18271-maps.c { .rfmax = 580000, .val = 0x30 }, val 648 drivers/media/tuners/tda18271-maps.c { .rfmax = 582000, .val = 0x31 }, val 649 drivers/media/tuners/tda18271-maps.c { .rfmax = 584000, .val = 0x32 }, val 650 drivers/media/tuners/tda18271-maps.c { .rfmax = 588000, .val = 0x33 }, val 651 drivers/media/tuners/tda18271-maps.c { .rfmax = 591000, .val = 0x34 }, val 652 drivers/media/tuners/tda18271-maps.c { .rfmax = 596000, .val = 0x35 }, val 653 drivers/media/tuners/tda18271-maps.c { .rfmax = 598000, .val = 0x36 }, val 654 drivers/media/tuners/tda18271-maps.c { .rfmax = 603000, .val = 0x37 }, val 655 drivers/media/tuners/tda18271-maps.c { .rfmax = 604000, .val = 0x38 }, val 656 drivers/media/tuners/tda18271-maps.c { .rfmax = 606000, .val = 0x39 }, val 657 drivers/media/tuners/tda18271-maps.c { .rfmax = 612000, .val = 0x3a }, val 658 drivers/media/tuners/tda18271-maps.c { .rfmax = 615000, .val = 0x3b }, val 659 drivers/media/tuners/tda18271-maps.c { .rfmax = 617000, .val = 0x3c }, val 660 drivers/media/tuners/tda18271-maps.c { .rfmax = 621000, .val = 0x3d }, val 661 drivers/media/tuners/tda18271-maps.c { .rfmax = 622000, .val = 0x3e }, val 662 drivers/media/tuners/tda18271-maps.c { .rfmax = 625000, .val = 0x3f }, val 663 drivers/media/tuners/tda18271-maps.c { .rfmax = 632000, .val = 0x40 }, val 664 drivers/media/tuners/tda18271-maps.c { .rfmax = 633000, .val = 0x41 }, val 665 drivers/media/tuners/tda18271-maps.c { .rfmax = 634000, .val = 0x42 }, val 666 drivers/media/tuners/tda18271-maps.c { .rfmax = 642000, .val = 0x43 }, val 667 drivers/media/tuners/tda18271-maps.c { .rfmax = 643000, .val = 0x44 }, val 668 drivers/media/tuners/tda18271-maps.c { .rfmax = 647000, .val = 0x45 }, val 669 drivers/media/tuners/tda18271-maps.c { .rfmax = 650000, .val = 0x46 }, val 670 drivers/media/tuners/tda18271-maps.c { .rfmax = 652000, .val = 0x47 }, val 671 drivers/media/tuners/tda18271-maps.c { .rfmax = 657000, .val = 0x48 }, val 672 drivers/media/tuners/tda18271-maps.c { .rfmax = 661000, .val = 0x49 }, val 673 drivers/media/tuners/tda18271-maps.c { .rfmax = 662000, .val = 0x4a }, val 674 drivers/media/tuners/tda18271-maps.c { .rfmax = 665000, .val = 0x4b }, val 675 drivers/media/tuners/tda18271-maps.c { .rfmax = 667000, .val = 0x4c }, val 676 drivers/media/tuners/tda18271-maps.c { .rfmax = 670000, .val = 0x4d }, val 677 drivers/media/tuners/tda18271-maps.c { .rfmax = 673000, .val = 0x4e }, val 678 drivers/media/tuners/tda18271-maps.c { .rfmax = 676000, .val = 0x4f }, val 679 drivers/media/tuners/tda18271-maps.c { .rfmax = 677000, .val = 0x50 }, val 680 drivers/media/tuners/tda18271-maps.c { .rfmax = 681000, .val = 0x51 }, val 681 drivers/media/tuners/tda18271-maps.c { .rfmax = 683000, .val = 0x52 }, val 682 drivers/media/tuners/tda18271-maps.c { .rfmax = 686000, .val = 0x53 }, val 683 drivers/media/tuners/tda18271-maps.c { .rfmax = 688000, .val = 0x54 }, val 684 drivers/media/tuners/tda18271-maps.c { .rfmax = 689000, .val = 0x55 }, val 685 drivers/media/tuners/tda18271-maps.c { .rfmax = 691000, .val = 0x56 }, val 686 drivers/media/tuners/tda18271-maps.c { .rfmax = 695000, .val = 0x57 }, val 687 drivers/media/tuners/tda18271-maps.c { .rfmax = 698000, .val = 0x58 }, val 688 drivers/media/tuners/tda18271-maps.c { .rfmax = 703000, .val = 0x59 }, val 689 drivers/media/tuners/tda18271-maps.c { .rfmax = 704000, .val = 0x5a }, val 690 drivers/media/tuners/tda18271-maps.c { .rfmax = 705000, .val = 0x5b }, val 691 drivers/media/tuners/tda18271-maps.c { .rfmax = 707000, .val = 0x5c }, val 692 drivers/media/tuners/tda18271-maps.c { .rfmax = 710000, .val = 0x5d }, val 693 drivers/media/tuners/tda18271-maps.c { .rfmax = 712000, .val = 0x5e }, val 694 drivers/media/tuners/tda18271-maps.c { .rfmax = 717000, .val = 0x5f }, val 695 drivers/media/tuners/tda18271-maps.c { .rfmax = 718000, .val = 0x60 }, val 696 drivers/media/tuners/tda18271-maps.c { .rfmax = 721000, .val = 0x61 }, val 697 drivers/media/tuners/tda18271-maps.c { .rfmax = 722000, .val = 0x62 }, val 698 drivers/media/tuners/tda18271-maps.c { .rfmax = 723000, .val = 0x63 }, val 699 drivers/media/tuners/tda18271-maps.c { .rfmax = 725000, .val = 0x64 }, val 700 drivers/media/tuners/tda18271-maps.c { .rfmax = 727000, .val = 0x65 }, val 701 drivers/media/tuners/tda18271-maps.c { .rfmax = 730000, .val = 0x66 }, val 702 drivers/media/tuners/tda18271-maps.c { .rfmax = 732000, .val = 0x67 }, val 703 drivers/media/tuners/tda18271-maps.c { .rfmax = 735000, .val = 0x68 }, val 704 drivers/media/tuners/tda18271-maps.c { .rfmax = 740000, .val = 0x69 }, val 705 drivers/media/tuners/tda18271-maps.c { .rfmax = 741000, .val = 0x6a }, val 706 drivers/media/tuners/tda18271-maps.c { .rfmax = 742000, .val = 0x6b }, val 707 drivers/media/tuners/tda18271-maps.c { .rfmax = 743000, .val = 0x6c }, val 708 drivers/media/tuners/tda18271-maps.c { .rfmax = 745000, .val = 0x6d }, val 709 drivers/media/tuners/tda18271-maps.c { .rfmax = 747000, .val = 0x6e }, val 710 drivers/media/tuners/tda18271-maps.c { .rfmax = 748000, .val = 0x6f }, val 711 drivers/media/tuners/tda18271-maps.c { .rfmax = 750000, .val = 0x70 }, val 712 drivers/media/tuners/tda18271-maps.c { .rfmax = 752000, .val = 0x71 }, val 713 drivers/media/tuners/tda18271-maps.c { .rfmax = 754000, .val = 0x72 }, val 714 drivers/media/tuners/tda18271-maps.c { .rfmax = 757000, .val = 0x73 }, val 715 drivers/media/tuners/tda18271-maps.c { .rfmax = 758000, .val = 0x74 }, val 716 drivers/media/tuners/tda18271-maps.c { .rfmax = 760000, .val = 0x75 }, val 717 drivers/media/tuners/tda18271-maps.c { .rfmax = 763000, .val = 0x76 }, val 718 drivers/media/tuners/tda18271-maps.c { .rfmax = 764000, .val = 0x77 }, val 719 drivers/media/tuners/tda18271-maps.c { .rfmax = 766000, .val = 0x78 }, val 720 drivers/media/tuners/tda18271-maps.c { .rfmax = 767000, .val = 0x79 }, val 721 drivers/media/tuners/tda18271-maps.c { .rfmax = 768000, .val = 0x7a }, val 722 drivers/media/tuners/tda18271-maps.c { .rfmax = 773000, .val = 0x7b }, val 723 drivers/media/tuners/tda18271-maps.c { .rfmax = 774000, .val = 0x7c }, val 724 drivers/media/tuners/tda18271-maps.c { .rfmax = 776000, .val = 0x7d }, val 725 drivers/media/tuners/tda18271-maps.c { .rfmax = 777000, .val = 0x7e }, val 726 drivers/media/tuners/tda18271-maps.c { .rfmax = 778000, .val = 0x7f }, val 727 drivers/media/tuners/tda18271-maps.c { .rfmax = 779000, .val = 0x80 }, val 728 drivers/media/tuners/tda18271-maps.c { .rfmax = 781000, .val = 0x81 }, val 729 drivers/media/tuners/tda18271-maps.c { .rfmax = 783000, .val = 0x82 }, val 730 drivers/media/tuners/tda18271-maps.c { .rfmax = 784000, .val = 0x83 }, val 731 drivers/media/tuners/tda18271-maps.c { .rfmax = 785000, .val = 0x84 }, val 732 drivers/media/tuners/tda18271-maps.c { .rfmax = 786000, .val = 0x85 }, val 733 drivers/media/tuners/tda18271-maps.c { .rfmax = 793000, .val = 0x86 }, val 734 drivers/media/tuners/tda18271-maps.c { .rfmax = 794000, .val = 0x87 }, val 735 drivers/media/tuners/tda18271-maps.c { .rfmax = 795000, .val = 0x88 }, val 736 drivers/media/tuners/tda18271-maps.c { .rfmax = 797000, .val = 0x89 }, val 737 drivers/media/tuners/tda18271-maps.c { .rfmax = 799000, .val = 0x8a }, val 738 drivers/media/tuners/tda18271-maps.c { .rfmax = 801000, .val = 0x8b }, val 739 drivers/media/tuners/tda18271-maps.c { .rfmax = 802000, .val = 0x8c }, val 740 drivers/media/tuners/tda18271-maps.c { .rfmax = 803000, .val = 0x8d }, val 741 drivers/media/tuners/tda18271-maps.c { .rfmax = 804000, .val = 0x8e }, val 742 drivers/media/tuners/tda18271-maps.c { .rfmax = 810000, .val = 0x90 }, val 743 drivers/media/tuners/tda18271-maps.c { .rfmax = 811000, .val = 0x91 }, val 744 drivers/media/tuners/tda18271-maps.c { .rfmax = 812000, .val = 0x92 }, val 745 drivers/media/tuners/tda18271-maps.c { .rfmax = 814000, .val = 0x93 }, val 746 drivers/media/tuners/tda18271-maps.c { .rfmax = 816000, .val = 0x94 }, val 747 drivers/media/tuners/tda18271-maps.c { .rfmax = 817000, .val = 0x96 }, val 748 drivers/media/tuners/tda18271-maps.c { .rfmax = 818000, .val = 0x97 }, val 749 drivers/media/tuners/tda18271-maps.c { .rfmax = 820000, .val = 0x98 }, val 750 drivers/media/tuners/tda18271-maps.c { .rfmax = 821000, .val = 0x99 }, val 751 drivers/media/tuners/tda18271-maps.c { .rfmax = 822000, .val = 0x9a }, val 752 drivers/media/tuners/tda18271-maps.c { .rfmax = 828000, .val = 0x9b }, val 753 drivers/media/tuners/tda18271-maps.c { .rfmax = 829000, .val = 0x9d }, val 754 drivers/media/tuners/tda18271-maps.c { .rfmax = 830000, .val = 0x9f }, val 755 drivers/media/tuners/tda18271-maps.c { .rfmax = 831000, .val = 0xa0 }, val 756 drivers/media/tuners/tda18271-maps.c { .rfmax = 833000, .val = 0xa1 }, val 757 drivers/media/tuners/tda18271-maps.c { .rfmax = 835000, .val = 0xa2 }, val 758 drivers/media/tuners/tda18271-maps.c { .rfmax = 836000, .val = 0xa3 }, val 759 drivers/media/tuners/tda18271-maps.c { .rfmax = 837000, .val = 0xa4 }, val 760 drivers/media/tuners/tda18271-maps.c { .rfmax = 838000, .val = 0xa6 }, val 761 drivers/media/tuners/tda18271-maps.c { .rfmax = 840000, .val = 0xa8 }, val 762 drivers/media/tuners/tda18271-maps.c { .rfmax = 842000, .val = 0xa9 }, val 763 drivers/media/tuners/tda18271-maps.c { .rfmax = 845000, .val = 0xaa }, val 764 drivers/media/tuners/tda18271-maps.c { .rfmax = 846000, .val = 0xab }, val 765 drivers/media/tuners/tda18271-maps.c { .rfmax = 847000, .val = 0xad }, val 766 drivers/media/tuners/tda18271-maps.c { .rfmax = 848000, .val = 0xae }, val 767 drivers/media/tuners/tda18271-maps.c { .rfmax = 852000, .val = 0xaf }, val 768 drivers/media/tuners/tda18271-maps.c { .rfmax = 853000, .val = 0xb0 }, val 769 drivers/media/tuners/tda18271-maps.c { .rfmax = 858000, .val = 0xb1 }, val 770 drivers/media/tuners/tda18271-maps.c { .rfmax = 860000, .val = 0xb2 }, val 771 drivers/media/tuners/tda18271-maps.c { .rfmax = 861000, .val = 0xb3 }, val 772 drivers/media/tuners/tda18271-maps.c { .rfmax = 862000, .val = 0xb4 }, val 773 drivers/media/tuners/tda18271-maps.c { .rfmax = 863000, .val = 0xb6 }, val 774 drivers/media/tuners/tda18271-maps.c { .rfmax = 864000, .val = 0xb8 }, val 775 drivers/media/tuners/tda18271-maps.c { .rfmax = 865000, .val = 0xb9 }, val 776 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0x00 }, /* end */ val 780 drivers/media/tuners/tda18271-maps.c { .rfmax = 30000, .val = 4 }, val 781 drivers/media/tuners/tda18271-maps.c { .rfmax = 200000, .val = 5 }, val 782 drivers/media/tuners/tda18271-maps.c { .rfmax = 600000, .val = 6 }, val 783 drivers/media/tuners/tda18271-maps.c { .rfmax = 865000, .val = 7 }, val 784 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0 }, /* end */ val 788 drivers/media/tuners/tda18271-maps.c { .rfmax = 47900, .val = 0x00 }, val 789 drivers/media/tuners/tda18271-maps.c { .rfmax = 55000, .val = 0x00 }, val 790 drivers/media/tuners/tda18271-maps.c { .rfmax = 61100, .val = 0x0a }, val 791 drivers/media/tuners/tda18271-maps.c { .rfmax = 64000, .val = 0x0a }, val 792 drivers/media/tuners/tda18271-maps.c { .rfmax = 82000, .val = 0x14 }, val 793 drivers/media/tuners/tda18271-maps.c { .rfmax = 84000, .val = 0x19 }, val 794 drivers/media/tuners/tda18271-maps.c { .rfmax = 119000, .val = 0x1c }, val 795 drivers/media/tuners/tda18271-maps.c { .rfmax = 124000, .val = 0x20 }, val 796 drivers/media/tuners/tda18271-maps.c { .rfmax = 129000, .val = 0x2a }, val 797 drivers/media/tuners/tda18271-maps.c { .rfmax = 134000, .val = 0x32 }, val 798 drivers/media/tuners/tda18271-maps.c { .rfmax = 139000, .val = 0x39 }, val 799 drivers/media/tuners/tda18271-maps.c { .rfmax = 144000, .val = 0x3e }, val 800 drivers/media/tuners/tda18271-maps.c { .rfmax = 149000, .val = 0x3f }, val 801 drivers/media/tuners/tda18271-maps.c { .rfmax = 152600, .val = 0x40 }, val 802 drivers/media/tuners/tda18271-maps.c { .rfmax = 154000, .val = 0x40 }, val 803 drivers/media/tuners/tda18271-maps.c { .rfmax = 164700, .val = 0x41 }, val 804 drivers/media/tuners/tda18271-maps.c { .rfmax = 203500, .val = 0x32 }, val 805 drivers/media/tuners/tda18271-maps.c { .rfmax = 353000, .val = 0x19 }, val 806 drivers/media/tuners/tda18271-maps.c { .rfmax = 356000, .val = 0x1a }, val 807 drivers/media/tuners/tda18271-maps.c { .rfmax = 359000, .val = 0x1b }, val 808 drivers/media/tuners/tda18271-maps.c { .rfmax = 363000, .val = 0x1c }, val 809 drivers/media/tuners/tda18271-maps.c { .rfmax = 366000, .val = 0x1d }, val 810 drivers/media/tuners/tda18271-maps.c { .rfmax = 369000, .val = 0x1e }, val 811 drivers/media/tuners/tda18271-maps.c { .rfmax = 373000, .val = 0x1f }, val 812 drivers/media/tuners/tda18271-maps.c { .rfmax = 376000, .val = 0x20 }, val 813 drivers/media/tuners/tda18271-maps.c { .rfmax = 379000, .val = 0x21 }, val 814 drivers/media/tuners/tda18271-maps.c { .rfmax = 383000, .val = 0x22 }, val 815 drivers/media/tuners/tda18271-maps.c { .rfmax = 386000, .val = 0x23 }, val 816 drivers/media/tuners/tda18271-maps.c { .rfmax = 389000, .val = 0x24 }, val 817 drivers/media/tuners/tda18271-maps.c { .rfmax = 393000, .val = 0x25 }, val 818 drivers/media/tuners/tda18271-maps.c { .rfmax = 396000, .val = 0x26 }, val 819 drivers/media/tuners/tda18271-maps.c { .rfmax = 399000, .val = 0x27 }, val 820 drivers/media/tuners/tda18271-maps.c { .rfmax = 402000, .val = 0x28 }, val 821 drivers/media/tuners/tda18271-maps.c { .rfmax = 404000, .val = 0x29 }, val 822 drivers/media/tuners/tda18271-maps.c { .rfmax = 407000, .val = 0x2a }, val 823 drivers/media/tuners/tda18271-maps.c { .rfmax = 409000, .val = 0x2b }, val 824 drivers/media/tuners/tda18271-maps.c { .rfmax = 412000, .val = 0x2c }, val 825 drivers/media/tuners/tda18271-maps.c { .rfmax = 414000, .val = 0x2d }, val 826 drivers/media/tuners/tda18271-maps.c { .rfmax = 417000, .val = 0x2e }, val 827 drivers/media/tuners/tda18271-maps.c { .rfmax = 419000, .val = 0x2f }, val 828 drivers/media/tuners/tda18271-maps.c { .rfmax = 422000, .val = 0x30 }, val 829 drivers/media/tuners/tda18271-maps.c { .rfmax = 424000, .val = 0x31 }, val 830 drivers/media/tuners/tda18271-maps.c { .rfmax = 427000, .val = 0x32 }, val 831 drivers/media/tuners/tda18271-maps.c { .rfmax = 429000, .val = 0x33 }, val 832 drivers/media/tuners/tda18271-maps.c { .rfmax = 432000, .val = 0x34 }, val 833 drivers/media/tuners/tda18271-maps.c { .rfmax = 434000, .val = 0x35 }, val 834 drivers/media/tuners/tda18271-maps.c { .rfmax = 437000, .val = 0x36 }, val 835 drivers/media/tuners/tda18271-maps.c { .rfmax = 439000, .val = 0x37 }, val 836 drivers/media/tuners/tda18271-maps.c { .rfmax = 442000, .val = 0x38 }, val 837 drivers/media/tuners/tda18271-maps.c { .rfmax = 444000, .val = 0x39 }, val 838 drivers/media/tuners/tda18271-maps.c { .rfmax = 447000, .val = 0x3a }, val 839 drivers/media/tuners/tda18271-maps.c { .rfmax = 449000, .val = 0x3b }, val 840 drivers/media/tuners/tda18271-maps.c { .rfmax = 457800, .val = 0x3c }, val 841 drivers/media/tuners/tda18271-maps.c { .rfmax = 465000, .val = 0x0f }, val 842 drivers/media/tuners/tda18271-maps.c { .rfmax = 477000, .val = 0x12 }, val 843 drivers/media/tuners/tda18271-maps.c { .rfmax = 483000, .val = 0x14 }, val 844 drivers/media/tuners/tda18271-maps.c { .rfmax = 502000, .val = 0x19 }, val 845 drivers/media/tuners/tda18271-maps.c { .rfmax = 508000, .val = 0x1b }, val 846 drivers/media/tuners/tda18271-maps.c { .rfmax = 519000, .val = 0x1c }, val 847 drivers/media/tuners/tda18271-maps.c { .rfmax = 522000, .val = 0x1d }, val 848 drivers/media/tuners/tda18271-maps.c { .rfmax = 524000, .val = 0x1e }, val 849 drivers/media/tuners/tda18271-maps.c { .rfmax = 534000, .val = 0x1f }, val 850 drivers/media/tuners/tda18271-maps.c { .rfmax = 549000, .val = 0x20 }, val 851 drivers/media/tuners/tda18271-maps.c { .rfmax = 554000, .val = 0x22 }, val 852 drivers/media/tuners/tda18271-maps.c { .rfmax = 584000, .val = 0x24 }, val 853 drivers/media/tuners/tda18271-maps.c { .rfmax = 589000, .val = 0x26 }, val 854 drivers/media/tuners/tda18271-maps.c { .rfmax = 658000, .val = 0x27 }, val 855 drivers/media/tuners/tda18271-maps.c { .rfmax = 664000, .val = 0x2c }, val 856 drivers/media/tuners/tda18271-maps.c { .rfmax = 669000, .val = 0x2d }, val 857 drivers/media/tuners/tda18271-maps.c { .rfmax = 699000, .val = 0x2e }, val 858 drivers/media/tuners/tda18271-maps.c { .rfmax = 704000, .val = 0x30 }, val 859 drivers/media/tuners/tda18271-maps.c { .rfmax = 709000, .val = 0x31 }, val 860 drivers/media/tuners/tda18271-maps.c { .rfmax = 714000, .val = 0x32 }, val 861 drivers/media/tuners/tda18271-maps.c { .rfmax = 724000, .val = 0x33 }, val 862 drivers/media/tuners/tda18271-maps.c { .rfmax = 729000, .val = 0x36 }, val 863 drivers/media/tuners/tda18271-maps.c { .rfmax = 739000, .val = 0x38 }, val 864 drivers/media/tuners/tda18271-maps.c { .rfmax = 744000, .val = 0x39 }, val 865 drivers/media/tuners/tda18271-maps.c { .rfmax = 749000, .val = 0x3b }, val 866 drivers/media/tuners/tda18271-maps.c { .rfmax = 754000, .val = 0x3c }, val 867 drivers/media/tuners/tda18271-maps.c { .rfmax = 759000, .val = 0x3d }, val 868 drivers/media/tuners/tda18271-maps.c { .rfmax = 764000, .val = 0x3e }, val 869 drivers/media/tuners/tda18271-maps.c { .rfmax = 769000, .val = 0x3f }, val 870 drivers/media/tuners/tda18271-maps.c { .rfmax = 774000, .val = 0x40 }, val 871 drivers/media/tuners/tda18271-maps.c { .rfmax = 779000, .val = 0x41 }, val 872 drivers/media/tuners/tda18271-maps.c { .rfmax = 784000, .val = 0x43 }, val 873 drivers/media/tuners/tda18271-maps.c { .rfmax = 789000, .val = 0x46 }, val 874 drivers/media/tuners/tda18271-maps.c { .rfmax = 794000, .val = 0x48 }, val 875 drivers/media/tuners/tda18271-maps.c { .rfmax = 799000, .val = 0x4b }, val 876 drivers/media/tuners/tda18271-maps.c { .rfmax = 804000, .val = 0x4f }, val 877 drivers/media/tuners/tda18271-maps.c { .rfmax = 809000, .val = 0x54 }, val 878 drivers/media/tuners/tda18271-maps.c { .rfmax = 814000, .val = 0x59 }, val 879 drivers/media/tuners/tda18271-maps.c { .rfmax = 819000, .val = 0x5d }, val 880 drivers/media/tuners/tda18271-maps.c { .rfmax = 824000, .val = 0x61 }, val 881 drivers/media/tuners/tda18271-maps.c { .rfmax = 829000, .val = 0x68 }, val 882 drivers/media/tuners/tda18271-maps.c { .rfmax = 834000, .val = 0x6e }, val 883 drivers/media/tuners/tda18271-maps.c { .rfmax = 839000, .val = 0x75 }, val 884 drivers/media/tuners/tda18271-maps.c { .rfmax = 844000, .val = 0x7e }, val 885 drivers/media/tuners/tda18271-maps.c { .rfmax = 849000, .val = 0x82 }, val 886 drivers/media/tuners/tda18271-maps.c { .rfmax = 854000, .val = 0x84 }, val 887 drivers/media/tuners/tda18271-maps.c { .rfmax = 859000, .val = 0x8f }, val 888 drivers/media/tuners/tda18271-maps.c { .rfmax = 865000, .val = 0x9a }, val 889 drivers/media/tuners/tda18271-maps.c { .rfmax = 0, .val = 0x00 }, /* end */ val 924 drivers/media/tuners/tda18271-maps.c int val, i = 0; val 933 drivers/media/tuners/tda18271-maps.c val = tda18271_thermometer[i].r1; val 935 drivers/media/tuners/tda18271-maps.c val = tda18271_thermometer[i].r0; val 937 drivers/media/tuners/tda18271-maps.c tda_map("(%d) tm = %d\n", i, val); val 939 drivers/media/tuners/tda18271-maps.c return val; val 1104 drivers/media/tuners/tda18271-maps.c u32 *freq, u8 *val) val 1164 drivers/media/tuners/tda18271-maps.c *val = map[i].val; val 1166 drivers/media/tuners/tda18271-maps.c tda_map("(%d) %s: 0x%02x\n", i, map_name, *val); val 183 drivers/media/tuners/tda18271-priv.h u32 *freq, u8 *val); val 44 drivers/media/tuners/tua9001.c ret = regmap_write(dev->regmap, data[i].reg, data[i].val); val 81 drivers/media/tuners/tua9001.c u16 val; val 92 drivers/media/tuners/tua9001.c val = 0x0000; val 95 drivers/media/tuners/tua9001.c val = 0x1000; val 98 drivers/media/tuners/tua9001.c val = 0x2000; val 101 drivers/media/tuners/tua9001.c val = 0x3000; val 114 drivers/media/tuners/tua9001.c data[0].val = val; val 116 drivers/media/tuners/tua9001.c data[1].val = div_u64((u64) (c->frequency - 150000000) * 48, 1000000); val 127 drivers/media/tuners/tua9001.c ret = regmap_write(dev->regmap, data[i].reg, data[i].val); val 17 drivers/media/tuners/tua9001_priv.h u16 val; val 158 drivers/media/tuners/tuner-xc2028.c static int xc2028_get_reg(struct xc2028_data *priv, u16 reg, u16 *val) val 171 drivers/media/tuners/tuner-xc2028.c *val = (ibuf[1]) | (ibuf[0] << 8); val 237 drivers/media/tuners/xc4000.c static int xc4000_readreg(struct xc4000_priv *priv, u16 reg, u16 *val); val 531 drivers/media/tuners/xc4000.c static int xc4000_readreg(struct xc4000_priv *priv, u16 reg, u16 *val) val 547 drivers/media/tuners/xc4000.c *val = (bval[0] << 8) | bval[1]; val 241 drivers/media/tuners/xc5000.c static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val); val 273 drivers/media/tuners/xc5000.c static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val) val 289 drivers/media/tuners/xc5000.c *val = (bval[0] << 8) | bval[1]; val 868 drivers/media/usb/airspy/airspy.c s->lna_gain_auto->cur.val, s->lna_gain_auto->val, val 869 drivers/media/usb/airspy/airspy.c s->lna_gain->cur.val, s->lna_gain->val); val 871 drivers/media/usb/airspy/airspy.c ret = airspy_ctrl_msg(s, CMD_SET_LNA_AGC, 0, s->lna_gain_auto->val, val 876 drivers/media/usb/airspy/airspy.c if (s->lna_gain_auto->val == false) { val 877 drivers/media/usb/airspy/airspy.c ret = airspy_ctrl_msg(s, CMD_SET_LNA_GAIN, 0, s->lna_gain->val, val 895 drivers/media/usb/airspy/airspy.c s->mixer_gain_auto->cur.val, s->mixer_gain_auto->val, val 896 drivers/media/usb/airspy/airspy.c s->mixer_gain->cur.val, s->mixer_gain->val); val 898 drivers/media/usb/airspy/airspy.c ret = airspy_ctrl_msg(s, CMD_SET_MIXER_AGC, 0, s->mixer_gain_auto->val, val 903 drivers/media/usb/airspy/airspy.c if (s->mixer_gain_auto->val == false) { val 905 drivers/media/usb/airspy/airspy.c s->mixer_gain->val, &u8tmp, 1); val 921 drivers/media/usb/airspy/airspy.c dev_dbg(s->dev, "val=%d->%d\n", s->if_gain->cur.val, s->if_gain->val); val 923 drivers/media/usb/airspy/airspy.c ret = airspy_ctrl_msg(s, CMD_SET_VGA_GAIN, 0, s->if_gain->val, val 59 drivers/media/usb/au0828/au0828-core.c u32 au0828_writereg(struct au0828_dev *dev, u16 reg, u32 val) val 61 drivers/media/usb/au0828/au0828-core.c dprintk(8, "%s(0x%04x, 0x%02x)\n", __func__, reg, val); val 62 drivers/media/usb/au0828/au0828-core.c return send_control_msg(dev, CMD_REQUEST_OUT, val, reg); val 58 drivers/media/usb/au0828/au0828-input.c static int au8522_rc_read(struct au0828_rc *ir, u16 reg, int val, val 70 drivers/media/usb/au0828/au0828-input.c if (val >= 0) { val 71 drivers/media/usb/au0828/au0828-input.c obuf[2] = val; val 48 drivers/media/usb/au0828/au0828-video.c static inline void i2c_gate_ctrl(struct au0828_dev *dev, int val) val 51 drivers/media/usb/au0828/au0828-video.c dev->dvb.frontend->ops.analog_ops.i2c_gate_ctrl(dev->dvb.frontend, val); val 1651 drivers/media/usb/au0828/au0828-video.c reg->val = au0828_read(dev, reg->reg); val 1664 drivers/media/usb/au0828/au0828-video.c return au0828_writereg(dev, reg->reg, reg->val); val 300 drivers/media/usb/au0828/au0828.h extern u32 au0828_write(struct au0828_dev *dev, u16 reg, u32 val); val 69 drivers/media/usb/b2c2/flexcop-usb.c static int flexcop_usb_readwrite_dw(struct flexcop_device *fc, u16 wRegOffsPCI, u32 *val, u8 read) val 80 drivers/media/usb/b2c2/flexcop-usb.c memcpy(fc_usb->data, val, sizeof(*val)); val 100 drivers/media/usb/b2c2/flexcop-usb.c memcpy(val, fc_usb->data, sizeof(*val)); val 306 drivers/media/usb/b2c2/flexcop-usb.c flexcop_ibi_value val; val 307 drivers/media/usb/b2c2/flexcop-usb.c val.raw = 0; val 308 drivers/media/usb/b2c2/flexcop-usb.c flexcop_usb_readwrite_dw(fc, reg, &val.raw, 1); val 309 drivers/media/usb/b2c2/flexcop-usb.c return val; val 313 drivers/media/usb/b2c2/flexcop-usb.c flexcop_ibi_register reg, flexcop_ibi_value val) val 315 drivers/media/usb/b2c2/flexcop-usb.c return flexcop_usb_readwrite_dw(fc, reg, &val.raw, 0); val 612 drivers/media/usb/cpia2/cpia2_v4l.c DBG("Set control id:%d, value:%d\n", ctrl->id, ctrl->val); val 616 drivers/media/usb/cpia2/cpia2_v4l.c cpia2_set_brightness(cam, ctrl->val); val 619 drivers/media/usb/cpia2/cpia2_v4l.c cpia2_set_contrast(cam, ctrl->val); val 622 drivers/media/usb/cpia2/cpia2_v4l.c cpia2_set_saturation(cam, ctrl->val); val 625 drivers/media/usb/cpia2/cpia2_v4l.c cpia2_set_property_mirror(cam, ctrl->val); val 628 drivers/media/usb/cpia2/cpia2_v4l.c cpia2_set_property_flip(cam, ctrl->val); val 631 drivers/media/usb/cpia2/cpia2_v4l.c return cpia2_set_flicker_mode(cam, flicker_table[ctrl->val]); val 633 drivers/media/usb/cpia2/cpia2_v4l.c return cpia2_set_gpio(cam, (cam->top_light->val << 6) | val 634 drivers/media/usb/cpia2/cpia2_v4l.c (cam->bottom_light->val << 7)); val 637 drivers/media/usb/cpia2/cpia2_v4l.c !(ctrl->val & V4L2_JPEG_ACTIVE_MARKER_DHT); val 640 drivers/media/usb/cpia2/cpia2_v4l.c cam->params.vc_params.quality = ctrl->val; val 643 drivers/media/usb/cpia2/cpia2_v4l.c cam->params.camera_state.stream_mode = ctrl->val; val 1115 drivers/media/usb/cx231xx/cx231xx-417.c u32 val = 0; val 1153 drivers/media/usb/cx231xx/cx231xx-417.c retval = mc417_register_read(dev, 0x20f8, &val); val 1155 drivers/media/usb/cx231xx/cx231xx-417.c val); val 1221 drivers/media/usb/cx231xx/cx231xx-417.c mc417_register_read(dev, 0x20f8, &val); val 1222 drivers/media/usb/cx231xx/cx231xx-417.c dprintk(3, "***VIM Capture Lines =%d ***\n", val); val 1918 drivers/media/usb/cx231xx/cx231xx-417.c static int cx231xx_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val) val 1921 drivers/media/usb/cx231xx/cx231xx-417.c int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1; val 66 drivers/media/usb/cx231xx/cx231xx-avcore.c u8 val = 0; val 72 drivers/media/usb/cx231xx/cx231xx-avcore.c verve_read_byte(dev, 0x07, &val); val 73 drivers/media/usb/cx231xx/cx231xx-avcore.c dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); val 75 drivers/media/usb/cx231xx/cx231xx-avcore.c verve_read_byte(dev, 0x07, &val); val 76 drivers/media/usb/cx231xx/cx231xx-avcore.c dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); val 2521 drivers/media/usb/cx231xx/cx231xx-avcore.c u8 val[4] = { 0, 0, 0, 0 }; val 2564 drivers/media/usb/cx231xx/cx231xx-avcore.c val[0] = 0x04; val 2565 drivers/media/usb/cx231xx/cx231xx-avcore.c val[1] = 0xA3; val 2566 drivers/media/usb/cx231xx/cx231xx-avcore.c val[2] = 0x3B; val 2567 drivers/media/usb/cx231xx/cx231xx-avcore.c val[3] = 0x00; val 2570 drivers/media/usb/cx231xx/cx231xx-avcore.c TS1_CFG_REG, val, 4); val 2572 drivers/media/usb/cx231xx/cx231xx-avcore.c val[0] = 0x00; val 2573 drivers/media/usb/cx231xx/cx231xx-avcore.c val[1] = 0x08; val 2574 drivers/media/usb/cx231xx/cx231xx-avcore.c val[2] = 0x00; val 2575 drivers/media/usb/cx231xx/cx231xx-avcore.c val[3] = 0x08; val 2578 drivers/media/usb/cx231xx/cx231xx-avcore.c TS1_LENGTH_REG, val, 4); val 285 drivers/media/usb/cx231xx/cx231xx-core.c u8 val = 0; val 297 drivers/media/usb/cx231xx/cx231xx-core.c val = ENABLE_ONE_BYTE; val 300 drivers/media/usb/cx231xx/cx231xx-core.c val = ENABLE_TWE_BYTE; val 303 drivers/media/usb/cx231xx/cx231xx-core.c val = ENABLE_THREE_BYTE; val 306 drivers/media/usb/cx231xx/cx231xx-core.c val = ENABLE_FOUR_BYTE; val 309 drivers/media/usb/cx231xx/cx231xx-core.c val = 0xFF; /* invalid option */ val 312 drivers/media/usb/cx231xx/cx231xx-core.c if (val == 0xFF) val 317 drivers/media/usb/cx231xx/cx231xx-core.c val, reg, buf, len, HZ); val 403 drivers/media/usb/cx231xx/cx231xx-core.c u8 val = 0; val 415 drivers/media/usb/cx231xx/cx231xx-core.c val = ENABLE_ONE_BYTE; val 418 drivers/media/usb/cx231xx/cx231xx-core.c val = ENABLE_TWE_BYTE; val 421 drivers/media/usb/cx231xx/cx231xx-core.c val = ENABLE_THREE_BYTE; val 424 drivers/media/usb/cx231xx/cx231xx-core.c val = ENABLE_FOUR_BYTE; val 427 drivers/media/usb/cx231xx/cx231xx-core.c val = 0xFF; /* invalid option */ val 430 drivers/media/usb/cx231xx/cx231xx-core.c if (val == 0xFF) val 439 drivers/media/usb/cx231xx/cx231xx-core.c req, 0, val, reg & 0xff, val 449 drivers/media/usb/cx231xx/cx231xx-core.c val, reg, buf, len, HZ); val 621 drivers/media/usb/cx231xx/cx231xx-core.c rc = cx231xx_set_gpio_value(dev, gpio->bit, gpio->val); val 1253 drivers/media/usb/cx231xx/cx231xx-core.c u8 val[4] = { 0, 0, 0, 0 }; val 1255 drivers/media/usb/cx231xx/cx231xx-core.c val[0] = 0x00; val 1256 drivers/media/usb/cx231xx/cx231xx-core.c val[1] = 0x03; val 1257 drivers/media/usb/cx231xx/cx231xx-core.c val[2] = 0x00; val 1258 drivers/media/usb/cx231xx/cx231xx-core.c val[3] = 0x00; val 1260 drivers/media/usb/cx231xx/cx231xx-core.c TS_MODE_REG, val, 4); val 1262 drivers/media/usb/cx231xx/cx231xx-core.c val[0] = 0x00; val 1263 drivers/media/usb/cx231xx/cx231xx-core.c val[1] = 0x70; val 1264 drivers/media/usb/cx231xx/cx231xx-core.c val[2] = 0x04; val 1265 drivers/media/usb/cx231xx/cx231xx-core.c val[3] = 0x00; val 1267 drivers/media/usb/cx231xx/cx231xx-core.c TS1_CFG_REG, val, 4); val 1272 drivers/media/usb/cx231xx/cx231xx-core.c u8 val[4] = { 0, 0, 0, 0 }; val 1274 drivers/media/usb/cx231xx/cx231xx-core.c val[0] = 0x03; val 1275 drivers/media/usb/cx231xx/cx231xx-core.c val[1] = 0x03; val 1276 drivers/media/usb/cx231xx/cx231xx-core.c val[2] = 0x00; val 1277 drivers/media/usb/cx231xx/cx231xx-core.c val[3] = 0x00; val 1279 drivers/media/usb/cx231xx/cx231xx-core.c TS_MODE_REG, val, 4); val 1281 drivers/media/usb/cx231xx/cx231xx-core.c val[0] = 0x04; val 1282 drivers/media/usb/cx231xx/cx231xx-core.c val[1] = 0xA3; val 1283 drivers/media/usb/cx231xx/cx231xx-core.c val[2] = 0x3B; val 1284 drivers/media/usb/cx231xx/cx231xx-core.c val[3] = 0x00; val 1286 drivers/media/usb/cx231xx/cx231xx-core.c TS1_CFG_REG, val, 4); val 1378 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = value[0] | value[1] << 8 | val 1385 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; val 1391 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; val 1397 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; val 1403 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; val 1409 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; val 1415 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; val 1434 drivers/media/usb/cx231xx/cx231xx-video.c data[0] = (u8) reg->val; val 1435 drivers/media/usb/cx231xx/cx231xx-video.c data[1] = (u8) (reg->val >> 8); val 1436 drivers/media/usb/cx231xx/cx231xx-video.c data[2] = (u8) (reg->val >> 16); val 1437 drivers/media/usb/cx231xx/cx231xx-video.c data[3] = (u8) (reg->val >> 24); val 1443 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, reg->val, 1); val 1447 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, reg->val, 1); val 1451 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 1, reg->val, 1); val 1455 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, reg->val, 4); val 1459 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, reg->val, 4); val 1463 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 1, reg->val, 4); val 299 drivers/media/usb/cx231xx/cx231xx.h unsigned char val; val 113 drivers/media/usb/dvb-usb-v2/af9015.c u8 val) val 116 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {WRITE_I2C, addr, reg, 1, 1, 1, &val}; val 126 drivers/media/usb/dvb-usb-v2/af9015.c u8 *val) val 129 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {READ_I2C, addr, reg, 0, 1, 1, val}; val 376 drivers/media/usb/dvb-usb-v2/af9015.c u8 val, i, offset = 0; val 377 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {READ_I2C, AF9015_I2C_EEPROM, 0, 0, 1, 1, &val}; val 396 drivers/media/usb/dvb-usb-v2/af9015.c state->ir_mode = val; val 397 drivers/media/usb/dvb-usb-v2/af9015.c dev_dbg(&intf->dev, "ir mode %02x\n", val); val 405 drivers/media/usb/dvb-usb-v2/af9015.c state->dual_mode = val; val 417 drivers/media/usb/dvb-usb-v2/af9015.c state->af9013_i2c_addr[1] = val >> 1; val 428 drivers/media/usb/dvb-usb-v2/af9015.c switch (val) { val 443 drivers/media/usb/dvb-usb-v2/af9015.c i, val, state->af9013_pdata[i].clk); val 451 drivers/media/usb/dvb-usb-v2/af9015.c state->af9013_pdata[i].if_frequency = val << 8; val 458 drivers/media/usb/dvb-usb-v2/af9015.c state->af9013_pdata[i].if_frequency += val; val 468 drivers/media/usb/dvb-usb-v2/af9015.c state->mt2060_if1[i] = val << 8; val 473 drivers/media/usb/dvb-usb-v2/af9015.c state->mt2060_if1[i] += val; val 482 drivers/media/usb/dvb-usb-v2/af9015.c switch (val) { val 506 drivers/media/usb/dvb-usb-v2/af9015.c val); val 510 drivers/media/usb/dvb-usb-v2/af9015.c state->af9013_pdata[i].tuner = val; val 511 drivers/media/usb/dvb-usb-v2/af9015.c dev_dbg(&intf->dev, "[%d] tuner id %02x\n", i, val); val 768 drivers/media/usb/dvb-usb-v2/af9015.c u8 val, firmware_info[4]; val 779 drivers/media/usb/dvb-usb-v2/af9015.c ret = af9015_read_reg_i2c(d, state->af9013_i2c_addr[1], 0x98be, &val); val 783 drivers/media/usb/dvb-usb-v2/af9015.c dev_dbg(&intf->dev, "firmware status %02x\n", val); val 785 drivers/media/usb/dvb-usb-v2/af9015.c if (val == 0x0c) val 811 drivers/media/usb/dvb-usb-v2/af9015.c for (val = 0x00, timeout = jiffies + msecs_to_jiffies(1000); val 812 drivers/media/usb/dvb-usb-v2/af9015.c !time_after(jiffies, timeout) && val != 0x0c && val != 0x04;) { val 817 drivers/media/usb/dvb-usb-v2/af9015.c 0x98be, &val); val 821 drivers/media/usb/dvb-usb-v2/af9015.c dev_dbg(&intf->dev, "firmware status %02x\n", val); val 827 drivers/media/usb/dvb-usb-v2/af9015.c if (val == 0x04) { val 831 drivers/media/usb/dvb-usb-v2/af9015.c } else if (val != 0x0c) { val 1300 drivers/media/usb/dvb-usb-v2/af9015.c u8 *val = &((u8 *)data)[2]; val 1302 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {WRITE_MEMORY, 0, reg, 0, 0, len, val}; val 1321 drivers/media/usb/dvb-usb-v2/af9015.c u8 *val = &((u8 *)val_buf)[0]; val 1323 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {READ_MEMORY, 0, reg, 0, 0, len, val}; val 114 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_wr_regs(struct dvb_usb_device *d, u32 reg, u8 *val, int len) val 132 drivers/media/usb/dvb-usb-v2/af9035.c memcpy(&wbuf[6], val, len); val 138 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_rd_regs(struct dvb_usb_device *d, u32 reg, u8 *val, int len) val 142 drivers/media/usb/dvb-usb-v2/af9035.c struct usb_req req = { CMD_MEM_RD, mbox, sizeof(wbuf), wbuf, len, val }; val 148 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_wr_reg(struct dvb_usb_device *d, u32 reg, u8 val) val 150 drivers/media/usb/dvb-usb-v2/af9035.c return af9035_wr_regs(d, reg, &val, 1); val 154 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_rd_reg(struct dvb_usb_device *d, u32 reg, u8 *val) val 156 drivers/media/usb/dvb-usb-v2/af9035.c return af9035_rd_regs(d, reg, val, 1); val 160 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_wr_reg_mask(struct dvb_usb_device *d, u32 reg, u8 val, val 172 drivers/media/usb/dvb-usb-v2/af9035.c val &= mask; val 174 drivers/media/usb/dvb-usb-v2/af9035.c val |= tmp; val 177 drivers/media/usb/dvb-usb-v2/af9035.c return af9035_wr_regs(d, reg, &val, 1); val 1010 drivers/media/usb/dvb-usb-v2/af9035.c u8 val; val 1023 drivers/media/usb/dvb-usb-v2/af9035.c val = 0x00; val 1025 drivers/media/usb/dvb-usb-v2/af9035.c val = 0x01; val 1027 drivers/media/usb/dvb-usb-v2/af9035.c ret = af9035_wr_reg_mask(d, 0x00d8e7, val, 0x01); val 1033 drivers/media/usb/dvb-usb-v2/af9035.c val = 0x01; val 1035 drivers/media/usb/dvb-usb-v2/af9035.c val = 0x00; val 1037 drivers/media/usb/dvb-usb-v2/af9035.c ret = af9035_wr_reg_mask(d, 0x00d8eb, val, 0x01); val 1722 drivers/media/usb/dvb-usb-v2/af9035.c ret = af9035_wr_reg_mask(d, tab[i].reg, tab[i].val, val 1805 drivers/media/usb/dvb-usb-v2/af9035.c tab[i].val, tab[i].mask); val 27 drivers/media/usb/dvb-usb-v2/af9035.h u8 val; val 32 drivers/media/usb/dvb-usb-v2/af9035.h u8 val; val 104 drivers/media/usb/dvb-usb-v2/anysee.c static int anysee_read_reg(struct dvb_usb_device *d, u16 reg, u8 *val) val 108 drivers/media/usb/dvb-usb-v2/anysee.c ret = anysee_ctrl_msg(d, buf, sizeof(buf), val, 1); val 109 drivers/media/usb/dvb-usb-v2/anysee.c dev_dbg(&d->udev->dev, "%s: reg=%04x val=%02x\n", __func__, reg, *val); val 113 drivers/media/usb/dvb-usb-v2/anysee.c static int anysee_write_reg(struct dvb_usb_device *d, u16 reg, u8 val) val 115 drivers/media/usb/dvb-usb-v2/anysee.c u8 buf[] = {CMD_REG_WRITE, reg >> 8, reg & 0xff, 0x01, val}; val 116 drivers/media/usb/dvb-usb-v2/anysee.c dev_dbg(&d->udev->dev, "%s: reg=%04x val=%02x\n", __func__, reg, val); val 121 drivers/media/usb/dvb-usb-v2/anysee.c static int anysee_wr_reg_mask(struct dvb_usb_device *d, u16 reg, u8 val, val 133 drivers/media/usb/dvb-usb-v2/anysee.c val &= mask; val 135 drivers/media/usb/dvb-usb-v2/anysee.c val |= tmp; val 138 drivers/media/usb/dvb-usb-v2/anysee.c return anysee_write_reg(d, reg, val); val 142 drivers/media/usb/dvb-usb-v2/anysee.c static int anysee_rd_reg_mask(struct dvb_usb_device *d, u16 reg, u8 *val, val 159 drivers/media/usb/dvb-usb-v2/anysee.c *val = tmp >> i; val 1161 drivers/media/usb/dvb-usb-v2/anysee.c u8 val; val 1163 drivers/media/usb/dvb-usb-v2/anysee.c ret = anysee_ctrl_msg(d, buf, sizeof(buf), &val, 1); val 1167 drivers/media/usb/dvb-usb-v2/anysee.c return val; val 1171 drivers/media/usb/dvb-usb-v2/anysee.c int addr, u8 val) val 1175 drivers/media/usb/dvb-usb-v2/anysee.c u8 buf[] = {CMD_CI, 0x03, 0x40 | addr >> 8, addr & 0xff, 0x00, 1, val}; val 1190 drivers/media/usb/dvb-usb-v2/anysee.c u8 val; val 1192 drivers/media/usb/dvb-usb-v2/anysee.c ret = anysee_ctrl_msg(d, buf, sizeof(buf), &val, 1); val 1196 drivers/media/usb/dvb-usb-v2/anysee.c return val; val 1200 drivers/media/usb/dvb-usb-v2/anysee.c u8 addr, u8 val) val 1204 drivers/media/usb/dvb-usb-v2/anysee.c u8 buf[] = {CMD_CI, 0x05, 0x40, addr, 0x00, 1, val}; val 64 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val; val 65 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_CODE_RATE_TPS_REG, &val); val 70 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c switch (val & V6_CODE_RATE_TPS_MASK) { val 95 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val; val 96 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_MODORDER_TPS_REG, &val); val 101 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c switch ((val & V6_PARAM_CONSTELLATION_MASK) >> 4) { val 120 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val; val 121 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_MODE_TPS_REG, &val); val 126 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c switch ((val & V6_PARAM_FFT_MODE_MASK) >> 2) { val 145 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val; val 146 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_CP_TPS_REG, &val); val 151 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c switch ((val & V6_PARAM_GI_MASK) >> 4) { val 173 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val; val 174 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_TPS_HIERACHY_REG, &val); val 179 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c switch ((val & V6_TPS_HIERARCHY_INFO_MASK) >> 6) { val 204 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val = 0; val 205 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_SYNC_LOCK_REG, &val); val 208 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c *sync_lock = (val & SYNC_LOCK_MASK) >> 4; val 217 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val = 0; val 218 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_RS_LOCK_DET_REG, &val); val 221 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c *rs_lock = (val & RS_LOCK_DET_MASK) >> 3; val 230 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val = 0; val 231 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_TPS_LOCK_REG, &val); val 234 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c *tps_lock = (val & V6_PARAM_TPS_LOCK_MASK) >> 6; val 243 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val = 0; val 244 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_IRQ_STATUS_REG, &val); val 247 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c *fec_lock = (val & IRQ_MASK_FEC_LOCK) >> 4; val 257 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val = 0; val 258 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c int ret = mxl111sf_demod_read_reg(state, V6_CP_LOCK_DET_REG, &val); val 261 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c *cp_lock = (val & V6_CP_LOCK_DET_MASK) >> 2; val 330 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c u8 val; val 336 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c ret = mxl111sf_demod_read_reg(state, V6_FEC_PER_COUNT_REG, &val); val 340 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c fec_per_count = val; val 343 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c ret = mxl111sf_demod_read_reg(state, V6_FEC_PER_SCALE_REG, &val); val 347 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c val &= V6_FEC_PER_SCALE_MASK; val 348 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c val *= 4; val 350 drivers/media/usb/dvb-usb-v2/mxl111sf-demod.c fec_per_scale = 1 << val; val 22 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c static int mxl111sf_set_gpo_state(struct mxl111sf_state *state, u8 pin, u8 val) val 27 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c mxl_debug_adv("(%d, %d)", pin, val); val 34 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c tmp |= (val << (pin - 1)); val 45 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c tmp |= (val << (pin - 3)); val 55 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c static int mxl111sf_get_gpi_state(struct mxl111sf_state *state, u8 pin, u8 *val) val 62 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c *val = 0; val 72 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c *val = (tmp >> (pin + 4)) & 0x01; val 81 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c *val = (tmp >> pin) & 0x01; val 89 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c *val = (tmp >> (pin - 3)) & 0x01; val 101 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c u8 val; val 157 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c gpio_cfg->pin, gpio_cfg->val) : val 159 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c gpio_cfg->pin, &gpio_cfg->val); val 166 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c int gpio, int direction, int val) val 171 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c .val = val, val 174 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c mxl_debug("(%d, %d, %d)", gpio, direction, val); val 548 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c static int mxl111sf_hw_set_gpio(struct mxl111sf_state *state, int gpio, int val) val 550 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c return mxl111sf_hw_do_set_gpio(state, gpio, MXL_GPIO_DIR_OUTPUT, val); val 570 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c static int pca9534_set_gpio(struct mxl111sf_state *state, int gpio, int val) val 581 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c mxl_debug("(%d, %d)", gpio, val); val 597 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c w[1] |= ((val ? 1 : 0) << gpio); val 627 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c int mxl111sf_set_gpio(struct mxl111sf_state *state, int gpio, int val) val 629 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c mxl_debug("(%d, %d)", gpio, val); val 637 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c return pca9534_set_gpio(state, gpio, val); val 639 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.c return mxl111sf_hw_set_gpio(state, gpio, val); val 13 drivers/media/usb/dvb-usb-v2/mxl111sf-gpio.h int mxl111sf_set_gpio(struct mxl111sf_state *state, int gpio, int val); val 263 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c u8 val; val 272 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c ret = mxl111sf_read_reg(state, V8_SPI_MODE_REG, &val); val 277 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c val |= 0x04; val 279 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c val &= ~0x04; val 281 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c ret = mxl111sf_write_reg(state, V8_SPI_MODE_REG, val); val 296 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c u8 val; val 298 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c val = current_value; val 302 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c val |= IDAC_MANUAL_CONTROL_BIT_MASK; val 306 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c val |= IDAC_CURRENT_SINKING_BIT_MASK; val 309 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c val &= ~IDAC_CURRENT_SINKING_BIT_MASK; val 312 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c val &= ~IDAC_MANUAL_CONTROL_BIT_MASK; val 320 drivers/media/usb/dvb-usb-v2/mxl111sf-phy.c ret = mxl111sf_write_reg(state, V6_IDAC_SETTINGS_REG, val); val 135 drivers/media/usb/dvb-usb-v2/mxl111sf.c u8 val = 0; val 138 drivers/media/usb/dvb-usb-v2/mxl111sf.c ret = mxl111sf_read_reg(state, addr, &val); val 145 drivers/media/usb/dvb-usb-v2/mxl111sf.c ret = mxl111sf_read_reg(state, addr, &val); val 150 drivers/media/usb/dvb-usb-v2/mxl111sf.c val &= ~mask; val 151 drivers/media/usb/dvb-usb-v2/mxl111sf.c val |= data; val 153 drivers/media/usb/dvb-usb-v2/mxl111sf.c ret = mxl111sf_write_reg(state, addr, val); val 63 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_wr_regs(struct dvb_usb_device *d, u16 reg, u8 *val, int len) val 76 drivers/media/usb/dvb-usb-v2/rtl28xxu.c req.data = val; val 81 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_rd_regs(struct dvb_usb_device *d, u16 reg, u8 *val, int len) val 94 drivers/media/usb/dvb-usb-v2/rtl28xxu.c req.data = val; val 99 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_wr_reg(struct dvb_usb_device *d, u16 reg, u8 val) val 101 drivers/media/usb/dvb-usb-v2/rtl28xxu.c return rtl28xxu_wr_regs(d, reg, &val, 1); val 104 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_rd_reg(struct dvb_usb_device *d, u16 reg, u8 *val) val 106 drivers/media/usb/dvb-usb-v2/rtl28xxu.c return rtl28xxu_rd_regs(d, reg, val, 1); val 109 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_wr_reg_mask(struct dvb_usb_device *d, u16 reg, u8 val, val 121 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val &= mask; val 123 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val |= tmp; val 126 drivers/media/usb/dvb-usb-v2/rtl28xxu.c return rtl28xxu_wr_reg(d, reg, val); val 762 drivers/media/usb/dvb-usb-v2/rtl28xxu.c u8 val; val 769 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_rd_reg(d, SYS_GPIO_OUT_VAL, &val); val 774 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val &= 0xbf; /* set GPIO6 low */ val 776 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val |= 0x40; /* set GPIO6 high */ val 779 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_wr_reg(d, SYS_GPIO_OUT_VAL, val); val 797 drivers/media/usb/dvb-usb-v2/rtl28xxu.c u8 val; val 810 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val = (1 << 4); val 812 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val = (0 << 4); val 814 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_wr_reg_mask(d, SYS_GPIO_OUT_VAL, val, 0x10); val 820 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val = (1 << 1); val 822 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val = (0 << 1); val 824 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_wr_reg_mask(d, SYS_GPIO_OUT_VAL, val, 0x02); val 1420 drivers/media/usb/dvb-usb-v2/rtl28xxu.c u8 val; val 1425 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_rd_reg(d, USB_SYSCTL_0, &val); val 1430 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val |= 0x09; val 1431 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_wr_reg(d, USB_SYSCTL_0, val); val 1587 drivers/media/usb/dvb-usb-v2/rtl28xxu.c u8 val; val 1597 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val = 0x48; /* enable ADC */ val 1599 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val = 0x00; /* disable ADC */ val 1601 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_wr_reg_mask(d, SYS_DEMOD_CTL, val, 0x48); val 1645 drivers/media/usb/dvb-usb-v2/rtl28xxu.c rc_nec_tab[i].val); val 1742 drivers/media/usb/dvb-usb-v2/rtl28xxu.c init_tab[i].val, init_tab[i].mask); val 1771 drivers/media/usb/dvb-usb-v2/rtl28xxu.c refresh_tab[i].val, refresh_tab[i].mask); val 124 drivers/media/usb/dvb-usb-v2/rtl28xxu.h u8 val; val 129 drivers/media/usb/dvb-usb-v2/rtl28xxu.h u8 val; val 85 drivers/media/usb/dvb-usb-v2/zd1301.c static int zd1301_demod_wreg(void *reg_priv, u16 reg, u8 val) val 91 drivers/media/usb/dvb-usb-v2/zd1301.c (reg >> 0) & 0xff, (reg >> 8) & 0xff, val}; val 103 drivers/media/usb/dvb-usb-v2/zd1301.c static int zd1301_demod_rreg(void *reg_priv, u16 reg, u8 *val) val 115 drivers/media/usb/dvb-usb-v2/zd1301.c *val = buf[6]; val 966 drivers/media/usb/dvb-usb/af9005-fe.c script[i].len, script[i].val))) val 970 drivers/media/usb/dvb-usb/af9005-fe.c temp2 = script[i].val; val 972 drivers/media/usb/dvb-usb/af9005-fe.c temp1 = script[i].val; val 974 drivers/media/usb/dvb-usb/af9005-fe.c temp0 = script[i].val; val 978 drivers/media/usb/dvb-usb/af9005-fe.c state->original_if_unplug_th = script[i].val; val 980 drivers/media/usb/dvb-usb/af9005-fe.c state->original_rf_unplug_th = script[i].val; val 982 drivers/media/usb/dvb-usb/af9005-fe.c state->original_dtop_if_unplug_th = script[i].val; val 984 drivers/media/usb/dvb-usb/af9005-fe.c state->original_dtop_rf_unplug_th = script[i].val; val 15 drivers/media/usb/dvb-usb/af9005-script.h u8 val; val 353 drivers/media/usb/dvb-usb/cxusb-analog.c unsigned char val) val 356 drivers/media/usb/dvb-usb/cxusb-analog.c *(bt656->buf++) = val; val 371 drivers/media/usb/dvb-usb/cxusb-analog.c unsigned char val) val 377 drivers/media/usb/dvb-usb/cxusb-analog.c cxusb_medion_cs_line_smpl(bt656, maxlinesamples, val); val 392 drivers/media/usb/dvb-usb/cxusb-analog.c unsigned char val; val 394 drivers/media/usb/dvb-usb/cxusb-analog.c if (!cxusb_auxbuf_copy(auxbuf, bt656->pos, &val, 1)) val 397 drivers/media/usb/dvb-usb/cxusb-analog.c if (val == CXUSB_BT656_PREAMBLE[0]) { val 400 drivers/media/usb/dvb-usb/cxusb-analog.c buf[0] = val; val 431 drivers/media/usb/dvb-usb/cxusb-analog.c maxlinesmpls, val)) val 221 drivers/media/usb/dvb-usb/dibusb-common.c int dibusb_read_eeprom_byte(struct dvb_usb_device *d, u8 offs, u8 *val) val 233 drivers/media/usb/dvb-usb/dibusb-common.c *val = buf[1]; val 285 drivers/media/usb/dvb-usb/opera1.c u8 val = onoff ? 0x01 : 0x00; val 289 drivers/media/usb/dvb-usb/opera1.c return opera1_xilinx_rw(d->udev, 0xb7, val, val 290 drivers/media/usb/dvb-usb/opera1.c &val, 1, OPERA_WRITE_MSG); val 507 drivers/media/usb/em28xx/em28xx-audio.c u16 val = (0x1f - (value->value.integer.value[0] & 0x1f)) | val 527 drivers/media/usb/em28xx/em28xx-audio.c val |= rc & 0x8000; /* Preserve the mute flag */ val 529 drivers/media/usb/em28xx/em28xx-audio.c rc = em28xx_write_ac97(dev, kcontrol->private_value, val); val 534 drivers/media/usb/em28xx/em28xx-audio.c (val & 0x8000) ? "muted " : "", val 535 drivers/media/usb/em28xx/em28xx-audio.c 0x1f - ((val >> 8) & 0x1f), 0x1f - (val & 0x1f), val 536 drivers/media/usb/em28xx/em28xx-audio.c val, (int)kcontrol->private_value); val 549 drivers/media/usb/em28xx/em28xx-audio.c int val; val 562 drivers/media/usb/em28xx/em28xx-audio.c val = em28xx_read_ac97(dev, kcontrol->private_value); val 564 drivers/media/usb/em28xx/em28xx-audio.c if (val < 0) val 565 drivers/media/usb/em28xx/em28xx-audio.c return val; val 568 drivers/media/usb/em28xx/em28xx-audio.c (val & 0x8000) ? "muted " : "", val 569 drivers/media/usb/em28xx/em28xx-audio.c 0x1f - ((val >> 8) & 0x1f), 0x1f - (val & 0x1f), val 570 drivers/media/usb/em28xx/em28xx-audio.c val, (int)kcontrol->private_value); val 572 drivers/media/usb/em28xx/em28xx-audio.c value->value.integer.value[0] = 0x1f - (val & 0x1f); val 573 drivers/media/usb/em28xx/em28xx-audio.c value->value.integer.value[1] = 0x1f - ((val >> 8) & 0x1f); val 582 drivers/media/usb/em28xx/em28xx-audio.c u16 val = value->value.integer.value[0]; val 602 drivers/media/usb/em28xx/em28xx-audio.c if (val) val 612 drivers/media/usb/em28xx/em28xx-audio.c (val & 0x8000) ? "muted " : "", val 613 drivers/media/usb/em28xx/em28xx-audio.c 0x1f - ((val >> 8) & 0x1f), 0x1f - (val & 0x1f), val 614 drivers/media/usb/em28xx/em28xx-audio.c val, (int)kcontrol->private_value); val 627 drivers/media/usb/em28xx/em28xx-audio.c int val; val 640 drivers/media/usb/em28xx/em28xx-audio.c val = em28xx_read_ac97(dev, kcontrol->private_value); val 642 drivers/media/usb/em28xx/em28xx-audio.c if (val < 0) val 643 drivers/media/usb/em28xx/em28xx-audio.c return val; val 645 drivers/media/usb/em28xx/em28xx-audio.c if (val & 0x8000) val 651 drivers/media/usb/em28xx/em28xx-audio.c (val & 0x8000) ? "muted " : "", val 652 drivers/media/usb/em28xx/em28xx-audio.c 0x1f - ((val >> 8) & 0x1f), 0x1f - (val & 0x1f), val 653 drivers/media/usb/em28xx/em28xx-audio.c val, (int)kcontrol->private_value); val 125 drivers/media/usb/em28xx/em28xx-core.c u8 val; val 127 drivers/media/usb/em28xx/em28xx-core.c ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1); val 131 drivers/media/usb/em28xx/em28xx-core.c return val; val 194 drivers/media/usb/em28xx/em28xx-core.c int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val) val 196 drivers/media/usb/em28xx/em28xx-core.c return em28xx_write_regs(dev, reg, &val, 1); val 205 drivers/media/usb/em28xx/em28xx-core.c int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val, val 215 drivers/media/usb/em28xx/em28xx-core.c newval = (((u8)oldval) & ~bitmask) | (val & bitmask); val 273 drivers/media/usb/em28xx/em28xx-core.c __le16 val; val 284 drivers/media/usb/em28xx/em28xx-core.c (u8 *)&val, sizeof(val)); val 288 drivers/media/usb/em28xx/em28xx-core.c return le16_to_cpu(val); val 296 drivers/media/usb/em28xx/em28xx-core.c int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val) val 302 drivers/media/usb/em28xx/em28xx-core.c value = cpu_to_le16(val); val 734 drivers/media/usb/em28xx/em28xx-core.c gpio->val, val 855 drivers/media/usb/em28xx/em28xx-dvb.c em28xx_write_reg_bits(dev, gpio[i].reg, gpio[i].val, val 1332 drivers/media/usb/em28xx/em28xx-video.c dev->mute = ctrl->val; val 1336 drivers/media/usb/em28xx/em28xx-video.c dev->volume = ctrl->val; val 1351 drivers/media/usb/em28xx/em28xx-video.c dev->mute = ctrl->val; val 1355 drivers/media/usb/em28xx/em28xx-video.c dev->volume = ctrl->val; val 1359 drivers/media/usb/em28xx/em28xx-video.c ret = em28xx_write_reg(dev, EM28XX_R20_YGAIN, ctrl->val); val 1362 drivers/media/usb/em28xx/em28xx-video.c ret = em28xx_write_reg(dev, EM28XX_R21_YOFFSET, ctrl->val); val 1365 drivers/media/usb/em28xx/em28xx-video.c ret = em28xx_write_reg(dev, EM28XX_R22_UVGAIN, ctrl->val); val 1368 drivers/media/usb/em28xx/em28xx-video.c ret = em28xx_write_reg(dev, EM28XX_R23_UOFFSET, ctrl->val); val 1371 drivers/media/usb/em28xx/em28xx-video.c ret = em28xx_write_reg(dev, EM28XX_R24_VOFFSET, ctrl->val); val 1374 drivers/media/usb/em28xx/em28xx-video.c ret = em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, ctrl->val); val 1929 drivers/media/usb/em28xx/em28xx-video.c reg->val = ret; val 1942 drivers/media/usb/em28xx/em28xx-video.c reg->val = ret; val 1944 drivers/media/usb/em28xx/em28xx-video.c __le16 val = 0; val 1947 drivers/media/usb/em28xx/em28xx-video.c reg->reg, (char *)&val, 2); val 1951 drivers/media/usb/em28xx/em28xx-video.c reg->val = le16_to_cpu(val); val 1966 drivers/media/usb/em28xx/em28xx-video.c return em28xx_write_ac97(dev, reg->reg, reg->val); val 1969 drivers/media/usb/em28xx/em28xx-video.c buf = cpu_to_le16(reg->val); val 2522 drivers/media/usb/em28xx/em28xx-video.c u8 val; val 2713 drivers/media/usb/em28xx/em28xx-video.c val = (u8)em28xx_read_reg(dev, EM28XX_R0F_XCLK); val 2715 drivers/media/usb/em28xx/em28xx-video.c (EM28XX_XCLK_AUDIO_UNMUTE | val)); val 415 drivers/media/usb/em28xx/em28xx.h unsigned char val, mask; val 810 drivers/media/usb/em28xx/em28xx.h int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val); val 811 drivers/media/usb/em28xx/em28xx.h int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val, val 816 drivers/media/usb/em28xx/em28xx.h int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val); val 60 drivers/media/usb/go7007/go7007-fw.c #define CODE_ADD(name, val, length) do { \ val 62 drivers/media/usb/go7007/go7007-fw.c name.a |= (val) << name.b; \ val 42 drivers/media/usb/go7007/go7007-i2c.c u16 val; val 67 drivers/media/usb/go7007/go7007-i2c.c if (go7007_read_addr(go, STATUS_REG_ADDR, &val) < 0) val 69 drivers/media/usb/go7007/go7007-i2c.c if (!(val & I2C_STATE_MASK)) val 92 drivers/media/usb/go7007/go7007-i2c.c if (go7007_read_addr(go, I2C_DATA_REG_ADDR, &val) < 0) val 101 drivers/media/usb/go7007/go7007-i2c.c if (go7007_read_addr(go, STATUS_REG_ADDR, &val) < 0) val 103 drivers/media/usb/go7007/go7007-i2c.c if (val & I2C_READ_READY_MASK) val 113 drivers/media/usb/go7007/go7007-i2c.c if (go7007_read_addr(go, I2C_DATA_REG_ADDR, &val) < 0) val 115 drivers/media/usb/go7007/go7007-i2c.c *data = val; val 786 drivers/media/usb/go7007/go7007-v4l2.c go->modet[0].pixel_threshold = ctrl->val; val 789 drivers/media/usb/go7007/go7007-v4l2.c go->modet[0].motion_threshold = ctrl->val; val 792 drivers/media/usb/go7007/go7007-v4l2.c go->modet[0].mb_threshold = ctrl->val; val 795 drivers/media/usb/go7007/go7007-v4l2.c go->modet[1].pixel_threshold = ctrl->val; val 798 drivers/media/usb/go7007/go7007-v4l2.c go->modet[1].motion_threshold = ctrl->val; val 801 drivers/media/usb/go7007/go7007-v4l2.c go->modet[1].mb_threshold = ctrl->val; val 804 drivers/media/usb/go7007/go7007-v4l2.c go->modet[2].pixel_threshold = ctrl->val; val 807 drivers/media/usb/go7007/go7007-v4l2.c go->modet[2].motion_threshold = ctrl->val; val 810 drivers/media/usb/go7007/go7007-v4l2.c go->modet[2].mb_threshold = ctrl->val; val 813 drivers/media/usb/go7007/go7007-v4l2.c go->modet[3].pixel_threshold = ctrl->val; val 816 drivers/media/usb/go7007/go7007-v4l2.c go->modet[3].motion_threshold = ctrl->val; val 819 drivers/media/usb/go7007/go7007-v4l2.c go->modet[3].mb_threshold = ctrl->val; val 185 drivers/media/usb/go7007/s2250-board.c static int write_reg_fp(struct i2c_client *client, u16 addr, u16 val) val 214 drivers/media/usb/go7007/s2250-board.c rc = go7007_usb_vendor_request(go, 0x57, addr, val, buf, 16, 1); val 227 drivers/media/usb/go7007/s2250-board.c if (val_read != val) { val 229 drivers/media/usb/go7007/s2250-board.c val_read, val); val 244 drivers/media/usb/go7007/s2250-board.c dec->reg12b_val = val; val 249 drivers/media/usb/go7007/s2250-board.c static int read_reg_fp(struct i2c_client *client, u16 addr, u16 *val) val 283 drivers/media/usb/go7007/s2250-board.c *val = (buf[0] << 8) | buf[1]; val 373 drivers/media/usb/go7007/s2250-board.c ctrl->val | (oldvalue & ~0xff)); val 376 drivers/media/usb/go7007/s2250-board.c ctrl->val | (oldvalue & ~0xff)); val 382 drivers/media/usb/go7007/s2250-board.c ctrl->val | (oldvalue & ~0x3f)); val 385 drivers/media/usb/go7007/s2250-board.c ctrl->val | (oldvalue & ~0x3f)); val 389 drivers/media/usb/go7007/s2250-board.c write_reg_fp(client, VPX322_ADDR_SAT, ctrl->val); val 392 drivers/media/usb/go7007/s2250-board.c write_reg_fp(client, VPX322_ADDR_HUE, ctrl->val); val 82 drivers/media/usb/gspca/conex.c __u8 val) val 86 drivers/media/usb/gspca/conex.c gspca_dev->usb_buf[0] = val; val 831 drivers/media/usb/gspca/conex.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val, s32 sat) val 836 drivers/media/usb/gspca/conex.c regE5cbx[2] = val; val 849 drivers/media/usb/gspca/conex.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val, s32 sat) val 855 drivers/media/usb/gspca/conex.c regE5acx[2] = val; val 878 drivers/media/usb/gspca/conex.c setbrightness(gspca_dev, ctrl->val, sd->sat->cur.val); val 881 drivers/media/usb/gspca/conex.c setcontrast(gspca_dev, ctrl->val, sd->sat->cur.val); val 884 drivers/media/usb/gspca/conex.c setbrightness(gspca_dev, sd->brightness->cur.val, ctrl->val); val 885 drivers/media/usb/gspca/conex.c setcontrast(gspca_dev, sd->contrast->cur.val, ctrl->val); val 1763 drivers/media/usb/gspca/cpia1.c sd->params.colourParams.brightness = ctrl->val; val 1771 drivers/media/usb/gspca/cpia1.c sd->params.colourParams.contrast = ctrl->val; val 1775 drivers/media/usb/gspca/cpia1.c sd->params.colourParams.saturation = ctrl->val; val 1779 drivers/media/usb/gspca/cpia1.c sd->mainsFreq = ctrl->val == V4L2_CID_POWER_LINE_FREQUENCY_60HZ; val 1786 drivers/media/usb/gspca/cpia1.c ctrl->val != V4L2_CID_POWER_LINE_FREQUENCY_DISABLED, val 1790 drivers/media/usb/gspca/cpia1.c sd->params.qx3.bottomlight = ctrl->val; val 1794 drivers/media/usb/gspca/cpia1.c sd->params.qx3.toplight = ctrl->val; val 1798 drivers/media/usb/gspca/cpia1.c sd->params.compressionTarget.frTargeting = ctrl->val; val 202 drivers/media/usb/gspca/dtcs033.c ctrl->val, sd->gain->val); val 206 drivers/media/usb/gspca/dtcs033.c sd->exposure->val, ctrl->val); val 170 drivers/media/usb/gspca/etoms.c __u8 val) val 174 drivers/media/usb/gspca/etoms.c gspca_dev->usb_buf[0] = val; val 380 drivers/media/usb/gspca/etoms.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 385 drivers/media/usb/gspca/etoms.c reg_w_val(gspca_dev, ET_O_RED + i, val); val 388 drivers/media/usb/gspca/etoms.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 392 drivers/media/usb/gspca/etoms.c memset(RGBG, val, sizeof(RGBG) - 2); val 396 drivers/media/usb/gspca/etoms.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 403 drivers/media/usb/gspca/etoms.c I2cc[3] = val; /* red */ val 404 drivers/media/usb/gspca/etoms.c I2cc[0] = 15 - val; /* blue */ val 698 drivers/media/usb/gspca/etoms.c setbrightness(gspca_dev, ctrl->val); val 701 drivers/media/usb/gspca/etoms.c setcontrast(gspca_dev, ctrl->val); val 704 drivers/media/usb/gspca/etoms.c setcolors(gspca_dev, ctrl->val); val 707 drivers/media/usb/gspca/etoms.c sd->autogain = ctrl->val; val 57 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.brightness = ctrl->val; val 60 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.contrast = ctrl->val; val 63 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.saturation = ctrl->val; val 66 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.hue = ctrl->val; val 69 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.gamma = ctrl->val; val 72 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.mirror = ctrl->val; val 75 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.flip = ctrl->val; val 78 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.AC50Hz = ctrl->val; val 81 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.whitebal = ctrl->val; val 84 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.sharpness = ctrl->val; val 87 drivers/media/usb/gspca/gl860/gl860.c sd->vcur.backlight = ctrl->val; val 539 drivers/media/usb/gspca/gl860/gl860.c unsigned char pref, u32 req, u16 val, u16 index, val 549 drivers/media/usb/gspca/gl860/gl860.c req, pref, val, index, val 554 drivers/media/usb/gspca/gl860/gl860.c req, pref, val, index, NULL, len, 400); val 559 drivers/media/usb/gspca/gl860/gl860.c req, pref, val, index, val 565 drivers/media/usb/gspca/gl860/gl860.c req, pref, val, index, NULL, len, 400); val 571 drivers/media/usb/gspca/gl860/gl860.c r, pref, req, val, index, len); val 586 drivers/media/usb/gspca/gl860/gl860.c ctrl_out(gspca_dev, 0x40, 1, tbl[n].val, val 588 drivers/media/usb/gspca/gl860/gl860.c else if (tbl[n].val == 0xffff) val 591 drivers/media/usb/gspca/gl860/gl860.c msleep(tbl[n].val); val 601 drivers/media/usb/gspca/gl860/gl860.c ctrl_out(gspca_dev, 0x40, 1, tbl[n].val, tbl[n].idx, val 603 drivers/media/usb/gspca/gl860/gl860.c else if (tbl[n].val == 0xffff) val 606 drivers/media/usb/gspca/gl860/gl860.c msleep(tbl[n].val); val 70 drivers/media/usb/gspca/gl860/gl860.h u16 val; val 85 drivers/media/usb/gspca/gl860/gl860.h unsigned char pref, u32 req, u16 val, u16 index, val 121 drivers/media/usb/gspca/jeilinj.c static void setfreq(struct gspca_dev *gspca_dev, s32 val) val 128 drivers/media/usb/gspca/jeilinj.c freq_commands[0][1] |= val >> 1; val 134 drivers/media/usb/gspca/jeilinj.c static void setcamquality(struct gspca_dev *gspca_dev, s32 val) val 143 drivers/media/usb/gspca/jeilinj.c camquality = ((QUALITY_MAX - val) * CAMQUALITY_MAX) val 151 drivers/media/usb/gspca/jeilinj.c static void setautogain(struct gspca_dev *gspca_dev, s32 val) val 158 drivers/media/usb/gspca/jeilinj.c autogain_commands[1][1] = val << 4; val 164 drivers/media/usb/gspca/jeilinj.c static void setred(struct gspca_dev *gspca_dev, s32 val) val 171 drivers/media/usb/gspca/jeilinj.c setred_commands[1][1] = val; val 177 drivers/media/usb/gspca/jeilinj.c static void setgreen(struct gspca_dev *gspca_dev, s32 val) val 184 drivers/media/usb/gspca/jeilinj.c setgreen_commands[1][1] = val; val 190 drivers/media/usb/gspca/jeilinj.c static void setblue(struct gspca_dev *gspca_dev, s32 val) val 197 drivers/media/usb/gspca/jeilinj.c setblue_commands[1][1] = val; val 401 drivers/media/usb/gspca/jeilinj.c setfreq(gspca_dev, ctrl->val); val 404 drivers/media/usb/gspca/jeilinj.c setred(gspca_dev, ctrl->val); val 407 drivers/media/usb/gspca/jeilinj.c setgreen(gspca_dev, ctrl->val); val 410 drivers/media/usb/gspca/jeilinj.c setblue(gspca_dev, ctrl->val); val 413 drivers/media/usb/gspca/jeilinj.c setautogain(gspca_dev, ctrl->val); val 416 drivers/media/usb/gspca/jeilinj.c jpeg_set_qual(sd->jpeg_hdr, ctrl->val); val 417 drivers/media/usb/gspca/jeilinj.c setcamquality(gspca_dev, ctrl->val); val 381 drivers/media/usb/gspca/konica.c reg_w(gspca_dev, ctrl->val, BRIGHTNESS_REG); val 386 drivers/media/usb/gspca/konica.c reg_w(gspca_dev, ctrl->val, CONTRAST_REG); val 391 drivers/media/usb/gspca/konica.c reg_w(gspca_dev, ctrl->val, SATURATION_REG); val 396 drivers/media/usb/gspca/konica.c reg_w(gspca_dev, ctrl->val, WHITEBAL_REG); val 401 drivers/media/usb/gspca/konica.c reg_w(gspca_dev, ctrl->val, SHARPNESS_REG); val 210 drivers/media/usb/gspca/m5602/m5602_core.c unsigned char val = 0; val 211 drivers/media/usb/gspca/m5602/m5602_core.c m5602_read_bridge(sd, i, &val); val 212 drivers/media/usb/gspca/m5602/m5602_core.c pr_info("ALi m5602 address 0x%x contains 0x%x\n", i, val); val 400 drivers/media/usb/gspca/m5602/m5602_mt9m111.c sd->hflip->val, sd->vflip->val); val 403 drivers/media/usb/gspca/m5602/m5602_mt9m111.c hflip = !sd->hflip->val; val 404 drivers/media/usb/gspca/m5602/m5602_mt9m111.c vflip = !sd->vflip->val; val 427 drivers/media/usb/gspca/m5602/m5602_mt9m111.c __s32 val) val 437 drivers/media/usb/gspca/m5602/m5602_mt9m111.c data[1] = ((data[1] & 0xfd) | ((val & 0x01) << 1)); val 441 drivers/media/usb/gspca/m5602/m5602_mt9m111.c gspca_dbg(gspca_dev, D_CONF, "Set auto white balance %d\n", val); val 445 drivers/media/usb/gspca/m5602/m5602_mt9m111.c static int mt9m111_set_gain(struct gspca_dev *gspca_dev, __s32 val) val 456 drivers/media/usb/gspca/m5602/m5602_mt9m111.c if (val >= INITIAL_MAX_GAIN * 2 * 2 * 2) val 459 drivers/media/usb/gspca/m5602/m5602_mt9m111.c if ((val >= INITIAL_MAX_GAIN * 2 * 2) && val 460 drivers/media/usb/gspca/m5602/m5602_mt9m111.c (val < (INITIAL_MAX_GAIN - 1) * 2 * 2 * 2)) val 461 drivers/media/usb/gspca/m5602/m5602_mt9m111.c tmp = (1 << 10) | (val << 9) | val 462 drivers/media/usb/gspca/m5602/m5602_mt9m111.c (val << 8) | (val / 8); val 463 drivers/media/usb/gspca/m5602/m5602_mt9m111.c else if ((val >= INITIAL_MAX_GAIN * 2) && val 464 drivers/media/usb/gspca/m5602/m5602_mt9m111.c (val < INITIAL_MAX_GAIN * 2 * 2)) val 465 drivers/media/usb/gspca/m5602/m5602_mt9m111.c tmp = (1 << 9) | (1 << 8) | (val / 4); val 466 drivers/media/usb/gspca/m5602/m5602_mt9m111.c else if ((val >= INITIAL_MAX_GAIN) && val 467 drivers/media/usb/gspca/m5602/m5602_mt9m111.c (val < INITIAL_MAX_GAIN * 2)) val 468 drivers/media/usb/gspca/m5602/m5602_mt9m111.c tmp = (1 << 8) | (val / 2); val 470 drivers/media/usb/gspca/m5602/m5602_mt9m111.c tmp = val; val 483 drivers/media/usb/gspca/m5602/m5602_mt9m111.c static int mt9m111_set_green_balance(struct gspca_dev *gspca_dev, __s32 val) val 489 drivers/media/usb/gspca/m5602/m5602_mt9m111.c data[1] = (val & 0xff); val 490 drivers/media/usb/gspca/m5602/m5602_mt9m111.c data[0] = (val & 0xff00) >> 8; val 492 drivers/media/usb/gspca/m5602/m5602_mt9m111.c gspca_dbg(gspca_dev, D_CONF, "Set green balance %d\n", val); val 502 drivers/media/usb/gspca/m5602/m5602_mt9m111.c static int mt9m111_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val) val 507 drivers/media/usb/gspca/m5602/m5602_mt9m111.c data[1] = (val & 0xff); val 508 drivers/media/usb/gspca/m5602/m5602_mt9m111.c data[0] = (val & 0xff00) >> 8; val 510 drivers/media/usb/gspca/m5602/m5602_mt9m111.c gspca_dbg(gspca_dev, D_CONF, "Set blue balance %d\n", val); val 516 drivers/media/usb/gspca/m5602/m5602_mt9m111.c static int mt9m111_set_red_balance(struct gspca_dev *gspca_dev, __s32 val) val 521 drivers/media/usb/gspca/m5602/m5602_mt9m111.c data[1] = (val & 0xff); val 522 drivers/media/usb/gspca/m5602/m5602_mt9m111.c data[0] = (val & 0xff00) >> 8; val 524 drivers/media/usb/gspca/m5602/m5602_mt9m111.c gspca_dbg(gspca_dev, D_CONF, "Set red balance %d\n", val); val 542 drivers/media/usb/gspca/m5602/m5602_mt9m111.c err = mt9m111_set_auto_white_balance(gspca_dev, ctrl->val); val 543 drivers/media/usb/gspca/m5602/m5602_mt9m111.c if (err || ctrl->val) val 545 drivers/media/usb/gspca/m5602/m5602_mt9m111.c err = mt9m111_set_green_balance(gspca_dev, sd->green_bal->val); val 548 drivers/media/usb/gspca/m5602/m5602_mt9m111.c err = mt9m111_set_red_balance(gspca_dev, sd->red_bal->val); val 551 drivers/media/usb/gspca/m5602/m5602_mt9m111.c err = mt9m111_set_blue_balance(gspca_dev, sd->blue_bal->val); val 554 drivers/media/usb/gspca/m5602/m5602_mt9m111.c err = mt9m111_set_gain(gspca_dev, ctrl->val); val 323 drivers/media/usb/gspca/m5602/m5602_ov7660.c static int ov7660_set_gain(struct gspca_dev *gspca_dev, __s32 val) val 326 drivers/media/usb/gspca/m5602/m5602_ov7660.c u8 i2c_data = val; val 329 drivers/media/usb/gspca/m5602/m5602_ov7660.c gspca_dbg(gspca_dev, D_CONF, "Setting gain to %d\n", val); val 336 drivers/media/usb/gspca/m5602/m5602_ov7660.c __s32 val) val 342 drivers/media/usb/gspca/m5602/m5602_ov7660.c gspca_dbg(gspca_dev, D_CONF, "Set auto white balance to %d\n", val); val 348 drivers/media/usb/gspca/m5602/m5602_ov7660.c i2c_data = ((i2c_data & 0xfd) | ((val & 0x01) << 1)); val 354 drivers/media/usb/gspca/m5602/m5602_ov7660.c static int ov7660_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val) val 360 drivers/media/usb/gspca/m5602/m5602_ov7660.c gspca_dbg(gspca_dev, D_CONF, "Set auto gain control to %d\n", val); val 366 drivers/media/usb/gspca/m5602/m5602_ov7660.c i2c_data = ((i2c_data & 0xfb) | ((val & 0x01) << 2)); val 372 drivers/media/usb/gspca/m5602/m5602_ov7660.c __s32 val) val 378 drivers/media/usb/gspca/m5602/m5602_ov7660.c gspca_dbg(gspca_dev, D_CONF, "Set auto exposure control to %d\n", val); val 384 drivers/media/usb/gspca/m5602/m5602_ov7660.c val = (val == V4L2_EXPOSURE_AUTO); val 385 drivers/media/usb/gspca/m5602/m5602_ov7660.c i2c_data = ((i2c_data & 0xfe) | ((val & 0x01) << 0)); val 397 drivers/media/usb/gspca/m5602/m5602_ov7660.c sd->hflip->val, sd->vflip->val); val 399 drivers/media/usb/gspca/m5602/m5602_ov7660.c i2c_data = (sd->hflip->val << 5) | (sd->vflip->val << 4); val 418 drivers/media/usb/gspca/m5602/m5602_ov7660.c err = ov7660_set_auto_white_balance(gspca_dev, ctrl->val); val 421 drivers/media/usb/gspca/m5602/m5602_ov7660.c err = ov7660_set_auto_exposure(gspca_dev, ctrl->val); val 424 drivers/media/usb/gspca/m5602/m5602_ov7660.c err = ov7660_set_auto_gain(gspca_dev, ctrl->val); val 425 drivers/media/usb/gspca/m5602/m5602_ov7660.c if (err || ctrl->val) val 427 drivers/media/usb/gspca/m5602/m5602_ov7660.c err = ov7660_set_gain(gspca_dev, sd->gain->val); val 423 drivers/media/usb/gspca/m5602/m5602_ov9650.c sd->vflip->val) || val 425 drivers/media/usb/gspca/m5602/m5602_ov9650.c !sd->vflip->val)) val 551 drivers/media/usb/gspca/m5602/m5602_ov9650.c static int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val) val 557 drivers/media/usb/gspca/m5602/m5602_ov9650.c gspca_dbg(gspca_dev, D_CONF, "Set exposure to %d\n", val); val 560 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = (val >> 10) & 0x3f; val 567 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = (val >> 2) & 0xff; val 574 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = val & 0x03; val 579 drivers/media/usb/gspca/m5602/m5602_ov9650.c static int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val) val 585 drivers/media/usb/gspca/m5602/m5602_ov9650.c gspca_dbg(gspca_dev, D_CONF, "Setting gain to %d\n", val); val 595 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = ((val & 0x0300) >> 2) | val 602 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = val & 0xff; val 607 drivers/media/usb/gspca/m5602/m5602_ov9650.c static int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val) val 613 drivers/media/usb/gspca/m5602/m5602_ov9650.c gspca_dbg(gspca_dev, D_CONF, "Set red gain to %d\n", val); val 615 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = val & 0xff; val 620 drivers/media/usb/gspca/m5602/m5602_ov9650.c static int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val) val 626 drivers/media/usb/gspca/m5602/m5602_ov9650.c gspca_dbg(gspca_dev, D_CONF, "Set blue gain to %d\n", val); val 628 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = val & 0xff; val 638 drivers/media/usb/gspca/m5602/m5602_ov9650.c int hflip = sd->hflip->val; val 639 drivers/media/usb/gspca/m5602/m5602_ov9650.c int vflip = sd->vflip->val; val 659 drivers/media/usb/gspca/m5602/m5602_ov9650.c __s32 val) val 665 drivers/media/usb/gspca/m5602/m5602_ov9650.c gspca_dbg(gspca_dev, D_CONF, "Set auto exposure control to %d\n", val); val 671 drivers/media/usb/gspca/m5602/m5602_ov9650.c val = (val == V4L2_EXPOSURE_AUTO); val 672 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = ((i2c_data & 0xfe) | ((val & 0x01) << 0)); val 678 drivers/media/usb/gspca/m5602/m5602_ov9650.c __s32 val) val 684 drivers/media/usb/gspca/m5602/m5602_ov9650.c gspca_dbg(gspca_dev, D_CONF, "Set auto white balance to %d\n", val); val 690 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = ((i2c_data & 0xfd) | ((val & 0x01) << 1)); val 696 drivers/media/usb/gspca/m5602/m5602_ov9650.c static int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val) val 702 drivers/media/usb/gspca/m5602/m5602_ov9650.c gspca_dbg(gspca_dev, D_CONF, "Set auto gain control to %d\n", val); val 708 drivers/media/usb/gspca/m5602/m5602_ov9650.c i2c_data = ((i2c_data & 0xfb) | ((val & 0x01) << 2)); val 725 drivers/media/usb/gspca/m5602/m5602_ov9650.c err = ov9650_set_auto_white_balance(gspca_dev, ctrl->val); val 726 drivers/media/usb/gspca/m5602/m5602_ov9650.c if (err || ctrl->val) val 728 drivers/media/usb/gspca/m5602/m5602_ov9650.c err = ov9650_set_red_balance(gspca_dev, sd->red_bal->val); val 731 drivers/media/usb/gspca/m5602/m5602_ov9650.c err = ov9650_set_blue_balance(gspca_dev, sd->blue_bal->val); val 734 drivers/media/usb/gspca/m5602/m5602_ov9650.c err = ov9650_set_auto_exposure(gspca_dev, ctrl->val); val 735 drivers/media/usb/gspca/m5602/m5602_ov9650.c if (err || ctrl->val == V4L2_EXPOSURE_AUTO) val 737 drivers/media/usb/gspca/m5602/m5602_ov9650.c err = ov9650_set_exposure(gspca_dev, sd->expo->val); val 740 drivers/media/usb/gspca/m5602/m5602_ov9650.c err = ov9650_set_auto_gain(gspca_dev, ctrl->val); val 741 drivers/media/usb/gspca/m5602/m5602_ov9650.c if (err || ctrl->val) val 743 drivers/media/usb/gspca/m5602/m5602_ov9650.c err = ov9650_set_gain(gspca_dev, sd->gain->val); val 407 drivers/media/usb/gspca/m5602/m5602_po1030.c static int po1030_set_exposure(struct gspca_dev *gspca_dev, __s32 val) val 413 drivers/media/usb/gspca/m5602/m5602_po1030.c gspca_dbg(gspca_dev, D_CONF, "Set exposure to %d\n", val & 0xffff); val 415 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = ((val & 0xff00) >> 8); val 424 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = (val & 0xff); val 433 drivers/media/usb/gspca/m5602/m5602_po1030.c static int po1030_set_gain(struct gspca_dev *gspca_dev, __s32 val) val 439 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = val & 0xff; val 453 drivers/media/usb/gspca/m5602/m5602_po1030.c sd->hflip->val, sd->vflip->val); val 458 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = (0x3f & i2c_data) | (sd->hflip->val << 7) | val 459 drivers/media/usb/gspca/m5602/m5602_po1030.c (sd->vflip->val << 6); val 467 drivers/media/usb/gspca/m5602/m5602_po1030.c static int po1030_set_red_balance(struct gspca_dev *gspca_dev, __s32 val) val 473 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = val & 0xff; val 480 drivers/media/usb/gspca/m5602/m5602_po1030.c static int po1030_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val) val 486 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = val & 0xff; val 494 drivers/media/usb/gspca/m5602/m5602_po1030.c static int po1030_set_green_balance(struct gspca_dev *gspca_dev, __s32 val) val 500 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = val & 0xff; val 513 drivers/media/usb/gspca/m5602/m5602_po1030.c __s32 val) val 523 drivers/media/usb/gspca/m5602/m5602_po1030.c gspca_dbg(gspca_dev, D_CONF, "Set auto white balance to %d\n", val); val 524 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = (i2c_data & 0xfe) | (val & 0x01); val 530 drivers/media/usb/gspca/m5602/m5602_po1030.c __s32 val) val 540 drivers/media/usb/gspca/m5602/m5602_po1030.c gspca_dbg(gspca_dev, D_CONF, "Set auto exposure to %d\n", val); val 541 drivers/media/usb/gspca/m5602/m5602_po1030.c val = (val == V4L2_EXPOSURE_AUTO); val 542 drivers/media/usb/gspca/m5602/m5602_po1030.c i2c_data = (i2c_data & 0xfd) | ((val & 0x01) << 1); val 563 drivers/media/usb/gspca/m5602/m5602_po1030.c err = po1030_set_auto_white_balance(gspca_dev, ctrl->val); val 564 drivers/media/usb/gspca/m5602/m5602_po1030.c if (err || ctrl->val) val 566 drivers/media/usb/gspca/m5602/m5602_po1030.c err = po1030_set_green_balance(gspca_dev, sd->green_bal->val); val 569 drivers/media/usb/gspca/m5602/m5602_po1030.c err = po1030_set_red_balance(gspca_dev, sd->red_bal->val); val 572 drivers/media/usb/gspca/m5602/m5602_po1030.c err = po1030_set_blue_balance(gspca_dev, sd->blue_bal->val); val 575 drivers/media/usb/gspca/m5602/m5602_po1030.c err = po1030_set_auto_exposure(gspca_dev, ctrl->val); val 576 drivers/media/usb/gspca/m5602/m5602_po1030.c if (err || ctrl->val == V4L2_EXPOSURE_AUTO) val 578 drivers/media/usb/gspca/m5602/m5602_po1030.c err = po1030_set_exposure(gspca_dev, sd->expo->val); val 581 drivers/media/usb/gspca/m5602/m5602_po1030.c err = po1030_set_gain(gspca_dev, ctrl->val); val 561 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c static int s5k4aa_set_exposure(struct gspca_dev *gspca_dev, __s32 val) val 567 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c gspca_dbg(gspca_dev, D_CONF, "Set exposure to %d\n", val); val 571 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c data = (val >> 8) & 0xff; val 575 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c data = val & 0xff; val 586 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c int hflip = sd->hflip->val; val 587 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c int vflip = sd->vflip->val; val 633 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c static int s5k4aa_set_gain(struct gspca_dev *gspca_dev, __s32 val) val 639 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c gspca_dbg(gspca_dev, D_CONF, "Set gain to %d\n", val); val 644 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c data = val & 0xff; val 650 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c static int s5k4aa_set_brightness(struct gspca_dev *gspca_dev, __s32 val) val 656 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c gspca_dbg(gspca_dev, D_CONF, "Set brightness to %d\n", val); val 661 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c data = val & 0xff; val 665 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c static int s5k4aa_set_noise(struct gspca_dev *gspca_dev, __s32 val) val 671 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c gspca_dbg(gspca_dev, D_CONF, "Set noise to %d\n", val); val 676 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c data = val & 0x01; val 691 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c err = s5k4aa_set_brightness(gspca_dev, ctrl->val); val 694 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c err = s5k4aa_set_exposure(gspca_dev, ctrl->val); val 697 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c err = s5k4aa_set_gain(gspca_dev, ctrl->val); val 700 drivers/media/usb/gspca/m5602/m5602_s5k4aa.c err = s5k4aa_set_noise(gspca_dev, ctrl->val); val 166 drivers/media/usb/gspca/m5602/m5602_s5k83a.c static int s5k83a_set_led_indication(struct sd *sd, u8 val); val 309 drivers/media/usb/gspca/m5602/m5602_s5k83a.c hflip = sd->hflip->val; val 310 drivers/media/usb/gspca/m5602/m5602_s5k83a.c vflip = sd->vflip->val; val 326 drivers/media/usb/gspca/m5602/m5602_s5k83a.c hflip = sd->hflip->val; val 327 drivers/media/usb/gspca/m5602/m5602_s5k83a.c vflip = sd->vflip->val; val 382 drivers/media/usb/gspca/m5602/m5602_s5k83a.c static int s5k83a_set_gain(struct gspca_dev *gspca_dev, __s32 val) val 402 drivers/media/usb/gspca/m5602/m5602_s5k83a.c data[0] = val >> 3; /* gain, high 5 bits */ val 403 drivers/media/usb/gspca/m5602/m5602_s5k83a.c data[1] = val >> 1; /* gain, high 7 bits */ val 409 drivers/media/usb/gspca/m5602/m5602_s5k83a.c static int s5k83a_set_brightness(struct gspca_dev *gspca_dev, __s32 val) val 415 drivers/media/usb/gspca/m5602/m5602_s5k83a.c data[0] = val; val 420 drivers/media/usb/gspca/m5602/m5602_s5k83a.c static int s5k83a_set_exposure(struct gspca_dev *gspca_dev, __s32 val) val 427 drivers/media/usb/gspca/m5602/m5602_s5k83a.c data[1] = val; val 468 drivers/media/usb/gspca/m5602/m5602_s5k83a.c int hflip = sd->hflip->val; val 469 drivers/media/usb/gspca/m5602/m5602_s5k83a.c int vflip = sd->vflip->val; val 494 drivers/media/usb/gspca/m5602/m5602_s5k83a.c err = s5k83a_set_brightness(gspca_dev, ctrl->val); val 497 drivers/media/usb/gspca/m5602/m5602_s5k83a.c err = s5k83a_set_exposure(gspca_dev, ctrl->val); val 500 drivers/media/usb/gspca/m5602/m5602_s5k83a.c err = s5k83a_set_gain(gspca_dev, ctrl->val); val 512 drivers/media/usb/gspca/m5602/m5602_s5k83a.c static int s5k83a_set_led_indication(struct sd *sd, u8 val) val 521 drivers/media/usb/gspca/m5602/m5602_s5k83a.c if (val) val 550 drivers/media/usb/gspca/m5602/m5602_s5k83a.c u8 val = 0; val 551 drivers/media/usb/gspca/m5602/m5602_s5k83a.c m5602_read_sensor(sd, address, &val, 1); val 552 drivers/media/usb/gspca/m5602/m5602_s5k83a.c pr_info("register 0x%x contains 0x%x\n", address, val); val 38 drivers/media/usb/gspca/mars.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val); val 39 drivers/media/usb/gspca/mars.c static void setcolors(struct gspca_dev *gspca_dev, s32 val); val 40 drivers/media/usb/gspca/mars.c static void setgamma(struct gspca_dev *gspca_dev, s32 val); val 41 drivers/media/usb/gspca/mars.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val); val 101 drivers/media/usb/gspca/mars.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 104 drivers/media/usb/gspca/mars.c gspca_dev->usb_buf[1] = val; val 108 drivers/media/usb/gspca/mars.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 111 drivers/media/usb/gspca/mars.c gspca_dev->usb_buf[1] = val << 3; val 112 drivers/media/usb/gspca/mars.c gspca_dev->usb_buf[2] = ((val >> 2) & 0xf8) | 0x04; val 116 drivers/media/usb/gspca/mars.c static void setgamma(struct gspca_dev *gspca_dev, s32 val) val 119 drivers/media/usb/gspca/mars.c gspca_dev->usb_buf[1] = val * 0x40; val 123 drivers/media/usb/gspca/mars.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val) val 126 drivers/media/usb/gspca/mars.c gspca_dev->usb_buf[1] = val * 4 + 3; val 153 drivers/media/usb/gspca/mars.c if (ctrl->is_new && ctrl->val) val 154 drivers/media/usb/gspca/mars.c sd->illum_bottom->val = 0; val 155 drivers/media/usb/gspca/mars.c if (sd->illum_bottom->is_new && sd->illum_bottom->val) val 156 drivers/media/usb/gspca/mars.c sd->illum_top->val = 0; val 164 drivers/media/usb/gspca/mars.c setbrightness(gspca_dev, ctrl->val); val 167 drivers/media/usb/gspca/mars.c setcolors(gspca_dev, ctrl->val); val 170 drivers/media/usb/gspca/mars.c setgamma(gspca_dev, ctrl->val); val 173 drivers/media/usb/gspca/mars.c setilluminators(gspca_dev, sd->illum_top->val, val 174 drivers/media/usb/gspca/mars.c sd->illum_bottom->val); val 177 drivers/media/usb/gspca/mars.c setsharpness(gspca_dev, ctrl->val); val 782 drivers/media/usb/gspca/mr97310a.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 796 drivers/media/usb/gspca/mr97310a.c if (val > 0) { val 800 drivers/media/usb/gspca/mr97310a.c val = 257 - val; val 804 drivers/media/usb/gspca/mr97310a.c val = quick_clix_table[val]; val 806 drivers/media/usb/gspca/mr97310a.c sensor_write1(gspca_dev, value_reg, val); val 861 drivers/media/usb/gspca/mr97310a.c static void setgain(struct gspca_dev *gspca_dev, s32 val) val 867 drivers/media/usb/gspca/mr97310a.c sensor_write1(gspca_dev, 0x0e, val); val 870 drivers/media/usb/gspca/mr97310a.c sensor_write1(gspca_dev, gainreg, val >> 8); val 871 drivers/media/usb/gspca/mr97310a.c sensor_write1(gspca_dev, gainreg + 1, val & 0xff); val 874 drivers/media/usb/gspca/mr97310a.c sensor_write1(gspca_dev, 0x10, val); val 877 drivers/media/usb/gspca/mr97310a.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 879 drivers/media/usb/gspca/mr97310a.c sensor_write1(gspca_dev, 0x1c, val); val 895 drivers/media/usb/gspca/mr97310a.c setbrightness(gspca_dev, ctrl->val); val 898 drivers/media/usb/gspca/mr97310a.c setcontrast(gspca_dev, ctrl->val); val 901 drivers/media/usb/gspca/mr97310a.c setexposure(gspca_dev, sd->exposure->val, val 902 drivers/media/usb/gspca/mr97310a.c sd->min_clockdiv ? sd->min_clockdiv->val : 0); val 905 drivers/media/usb/gspca/mr97310a.c setgain(gspca_dev, ctrl->val); val 1596 drivers/media/usb/gspca/nw80x.c u8 val[2]; val 1601 drivers/media/usb/gspca/nw80x.c val[0] = len; val 1602 drivers/media/usb/gspca/nw80x.c val[1] = i2c_addr; val 1603 drivers/media/usb/gspca/nw80x.c reg_w(gspca_dev, 0x0502, val, 2); val 1604 drivers/media/usb/gspca/nw80x.c val[0] = 0x01; val 1605 drivers/media/usb/gspca/nw80x.c reg_w(gspca_dev, 0x0501, val, 1); val 1651 drivers/media/usb/gspca/nw80x.c static void setgain(struct gspca_dev *gspca_dev, u8 val) val 1658 drivers/media/usb/gspca/nw80x.c reg_w(gspca_dev, 0x1026, &val, 1); val 1662 drivers/media/usb/gspca/nw80x.c val = swap_bits(val); val 1663 drivers/media/usb/gspca/nw80x.c v[0] = val << 3; val 1664 drivers/media/usb/gspca/nw80x.c v[1] = val >> 5; val 1670 drivers/media/usb/gspca/nw80x.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 1677 drivers/media/usb/gspca/nw80x.c v[0] = ((9 - val) << 3) | 0x01; val 1684 drivers/media/usb/gspca/nw80x.c v[0] = val; val 1685 drivers/media/usb/gspca/nw80x.c v[1] = val >> 8; val 1691 drivers/media/usb/gspca/nw80x.c static void setautogain(struct gspca_dev *gspca_dev, s32 val) val 1696 drivers/media/usb/gspca/nw80x.c if (!val) { val 1977 drivers/media/usb/gspca/nw80x.c setautogain(gspca_dev, ctrl->val); val 1978 drivers/media/usb/gspca/nw80x.c if (!ctrl->val) { val 1980 drivers/media/usb/gspca/nw80x.c setgain(gspca_dev, gspca_dev->gain->val); val 1983 drivers/media/usb/gspca/nw80x.c gspca_dev->exposure->val); val 1989 drivers/media/usb/gspca/nw80x.c setexposure(gspca_dev, gspca_dev->exposure->val); val 583 drivers/media/usb/gspca/ov519.c u8 val; val 587 drivers/media/usb/gspca/ov519.c u8 val; val 2594 drivers/media/usb/gspca/ov519.c reg_w(sd, regvals->reg, regvals->val); val 2604 drivers/media/usb/gspca/ov519.c i2c_w(sd, regvals->reg, regvals->val); val 3210 drivers/media/usb/gspca/ov519.c static void setautogain(struct gspca_dev *gspca_dev, s32 val) val 3214 drivers/media/usb/gspca/ov519.c i2c_w_mask(sd, 0x13, val ? 0x05 : 0x00, 0x05); val 4506 drivers/media/usb/gspca/ov519.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 4535 drivers/media/usb/gspca/ov519.c i2c_w(sd, OV7610_REG_BRT, val); val 4539 drivers/media/usb/gspca/ov519.c i2c_w(sd, OV7610_REG_BRT, val); val 4542 drivers/media/usb/gspca/ov519.c write_i2c_regvals(sd, brit_7660[val], val 4548 drivers/media/usb/gspca/ov519.c i2c_w(sd, OV7670_R55_BRIGHT, ov7670_abs_to_sm(val)); val 4553 drivers/media/usb/gspca/ov519.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 4618 drivers/media/usb/gspca/ov519.c i2c_w(sd, OV7610_REG_CNT, val); val 4622 drivers/media/usb/gspca/ov519.c i2c_w_mask(sd, OV7610_REG_CNT, val >> 4, 0x0f); val 4630 drivers/media/usb/gspca/ov519.c i2c_w(sd, 0x64, ctab[val >> 5]); val 4641 drivers/media/usb/gspca/ov519.c i2c_w(sd, 0x64, ctab[val >> 4]); val 4645 drivers/media/usb/gspca/ov519.c write_i2c_regvals(sd, contrast_7660[val], val 4650 drivers/media/usb/gspca/ov519.c i2c_w(sd, OV7670_R56_CONTRAS, val >> 1); val 4655 drivers/media/usb/gspca/ov519.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 4659 drivers/media/usb/gspca/ov519.c i2c_w(sd, 0x10, val); val 4662 drivers/media/usb/gspca/ov519.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 4685 drivers/media/usb/gspca/ov519.c i2c_w(sd, OV7610_REG_SAT, val); val 4693 drivers/media/usb/gspca/ov519.c i2c_w(sd, OV7610_REG_SAT, val); val 4697 drivers/media/usb/gspca/ov519.c i2c_w(sd, OV7610_REG_SAT, val & 0xf0); val 4700 drivers/media/usb/gspca/ov519.c write_i2c_regvals(sd, colors_7660[val], val 4711 drivers/media/usb/gspca/ov519.c static void setautobright(struct gspca_dev *gspca_dev, s32 val) val 4715 drivers/media/usb/gspca/ov519.c i2c_w_mask(sd, 0x2d, val ? 0x10 : 0x00, 0x10); val 4718 drivers/media/usb/gspca/ov519.c static void setfreq_i(struct sd *sd, s32 val) val 4722 drivers/media/usb/gspca/ov519.c switch (val) { val 4744 drivers/media/usb/gspca/ov519.c switch (val) { val 4777 drivers/media/usb/gspca/ov519.c static void setfreq(struct gspca_dev *gspca_dev, s32 val) val 4781 drivers/media/usb/gspca/ov519.c setfreq_i(sd, val); val 4825 drivers/media/usb/gspca/ov519.c gspca_dev->exposure->val = i2c_r(sd, 0x10); val 4844 drivers/media/usb/gspca/ov519.c setbrightness(gspca_dev, ctrl->val); val 4847 drivers/media/usb/gspca/ov519.c setcontrast(gspca_dev, ctrl->val); val 4850 drivers/media/usb/gspca/ov519.c setfreq(gspca_dev, ctrl->val); val 4854 drivers/media/usb/gspca/ov519.c setautobright(gspca_dev, ctrl->val); val 4855 drivers/media/usb/gspca/ov519.c if (!ctrl->val && sd->brightness->is_new) val 4856 drivers/media/usb/gspca/ov519.c setbrightness(gspca_dev, sd->brightness->val); val 4859 drivers/media/usb/gspca/ov519.c setcolors(gspca_dev, ctrl->val); val 4862 drivers/media/usb/gspca/ov519.c sethvflip(gspca_dev, ctrl->val, sd->vflip->val); val 4866 drivers/media/usb/gspca/ov519.c setautogain(gspca_dev, ctrl->val); val 4867 drivers/media/usb/gspca/ov519.c if (!ctrl->val && gspca_dev->exposure->is_new) val 4868 drivers/media/usb/gspca/ov519.c setexposure(gspca_dev, gspca_dev->exposure->val); val 142 drivers/media/usb/gspca/ov534.c const u8 (*val)[2]; val 658 drivers/media/usb/gspca/ov534.c static void ov534_reg_write(struct gspca_dev *gspca_dev, u16 reg, u8 val) val 666 drivers/media/usb/gspca/ov534.c gspca_dbg(gspca_dev, D_USBO, "SET 01 0000 %04x %02x\n", reg, val); val 667 drivers/media/usb/gspca/ov534.c gspca_dev->usb_buf[0] = val; val 756 drivers/media/usb/gspca/ov534.c static void sccb_reg_write(struct gspca_dev *gspca_dev, u8 reg, u8 val) val 758 drivers/media/usb/gspca/ov534.c gspca_dbg(gspca_dev, D_USBO, "sccb write: %02x %02x\n", reg, val); val 760 drivers/media/usb/gspca/ov534.c ov534_reg_write(gspca_dev, OV534_REG_WRITE, val); val 863 drivers/media/usb/gspca/ov534.c static void sethue(struct gspca_dev *gspca_dev, s32 val) val 881 drivers/media/usb/gspca/ov534.c huesin = fixp_sin16(val) * 0x80 / 0x7fff; val 882 drivers/media/usb/gspca/ov534.c huecos = fixp_cos16(val) * 0x80 / 0x7fff; val 898 drivers/media/usb/gspca/ov534.c static void setsaturation(struct gspca_dev *gspca_dev, s32 val) val 915 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x4f + i, color_tb[val][i]); val 917 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0xa7, val); /* U saturation */ val 918 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0xa8, val); /* V saturation */ val 922 drivers/media/usb/gspca/ov534.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 927 drivers/media/usb/gspca/ov534.c if (val < 0) val 928 drivers/media/usb/gspca/ov534.c val = 0x80 - val; val 929 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x55, val); /* bright */ val 931 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x9b, val); val 935 drivers/media/usb/gspca/ov534.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 940 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x56, val); /* contras */ val 942 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x9c, val); val 945 drivers/media/usb/gspca/ov534.c static void setgain(struct gspca_dev *gspca_dev, s32 val) val 947 drivers/media/usb/gspca/ov534.c switch (val & 0x30) { val 949 drivers/media/usb/gspca/ov534.c val &= 0x0f; val 952 drivers/media/usb/gspca/ov534.c val &= 0x0f; val 953 drivers/media/usb/gspca/ov534.c val |= 0x30; val 956 drivers/media/usb/gspca/ov534.c val &= 0x0f; val 957 drivers/media/usb/gspca/ov534.c val |= 0x70; val 961 drivers/media/usb/gspca/ov534.c val &= 0x0f; val 962 drivers/media/usb/gspca/ov534.c val |= 0xf0; val 965 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x00, val); val 973 drivers/media/usb/gspca/ov534.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 980 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x10, val); /* aech */ val 989 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x08, val >> 7); val 990 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x10, val << 1); val 1008 drivers/media/usb/gspca/ov534.c static void setagc(struct gspca_dev *gspca_dev, s32 val) val 1010 drivers/media/usb/gspca/ov534.c if (val) { val 1023 drivers/media/usb/gspca/ov534.c static void setawb(struct gspca_dev *gspca_dev, s32 val) val 1027 drivers/media/usb/gspca/ov534.c if (val) { val 1042 drivers/media/usb/gspca/ov534.c static void setaec(struct gspca_dev *gspca_dev, s32 val) val 1050 drivers/media/usb/gspca/ov534.c switch (val) { val 1062 drivers/media/usb/gspca/ov534.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val) val 1064 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x91, val); /* Auto de-noise threshold */ val 1065 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x8e, val); /* De-noise threshold */ val 1071 drivers/media/usb/gspca/ov534.c u8 val; val 1074 drivers/media/usb/gspca/ov534.c val = sccb_reg_read(gspca_dev, 0x1e); /* mvfp */ val 1075 drivers/media/usb/gspca/ov534.c val &= ~0x30; val 1077 drivers/media/usb/gspca/ov534.c val |= 0x20; val 1079 drivers/media/usb/gspca/ov534.c val |= 0x10; val 1080 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x1e, val); val 1082 drivers/media/usb/gspca/ov534.c val = sccb_reg_read(gspca_dev, 0x0c); val 1083 drivers/media/usb/gspca/ov534.c val &= ~0xc0; val 1085 drivers/media/usb/gspca/ov534.c val |= 0x40; val 1087 drivers/media/usb/gspca/ov534.c val |= 0x80; val 1088 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x0c, val); val 1092 drivers/media/usb/gspca/ov534.c static void setlightfreq(struct gspca_dev *gspca_dev, s32 val) val 1096 drivers/media/usb/gspca/ov534.c val = val ? 0x9e : 0x00; val 1099 drivers/media/usb/gspca/ov534.c if (val) val 1100 drivers/media/usb/gspca/ov534.c val = 0x9d; /* insert dummy to 25fps for 50Hz */ val 1102 drivers/media/usb/gspca/ov534.c sccb_reg_write(gspca_dev, 0x2b, val); val 1131 drivers/media/usb/gspca/ov534.c if (ctrl->val && sd->gain && gspca_dev->streaming) val 1132 drivers/media/usb/gspca/ov534.c sd->gain->val = getgain(gspca_dev); val 1137 drivers/media/usb/gspca/ov534.c if (ctrl->val == V4L2_EXPOSURE_AUTO && sd->exposure && val 1139 drivers/media/usb/gspca/ov534.c sd->exposure->val = getexposure(gspca_dev); val 1156 drivers/media/usb/gspca/ov534.c sethue(gspca_dev, ctrl->val); val 1159 drivers/media/usb/gspca/ov534.c setsaturation(gspca_dev, ctrl->val); val 1162 drivers/media/usb/gspca/ov534.c setbrightness(gspca_dev, ctrl->val); val 1165 drivers/media/usb/gspca/ov534.c setcontrast(gspca_dev, ctrl->val); val 1169 drivers/media/usb/gspca/ov534.c setagc(gspca_dev, ctrl->val); val 1170 drivers/media/usb/gspca/ov534.c if (!gspca_dev->usb_err && !ctrl->val && sd->gain) val 1171 drivers/media/usb/gspca/ov534.c setgain(gspca_dev, sd->gain->val); val 1174 drivers/media/usb/gspca/ov534.c setawb(gspca_dev, ctrl->val); val 1178 drivers/media/usb/gspca/ov534.c setaec(gspca_dev, ctrl->val); val 1179 drivers/media/usb/gspca/ov534.c if (!gspca_dev->usb_err && ctrl->val == V4L2_EXPOSURE_MANUAL && val 1181 drivers/media/usb/gspca/ov534.c setexposure(gspca_dev, sd->exposure->val); val 1184 drivers/media/usb/gspca/ov534.c setsharpness(gspca_dev, ctrl->val); val 1187 drivers/media/usb/gspca/ov534.c sethvflip(gspca_dev, ctrl->val, sd->vflip->val); val 1190 drivers/media/usb/gspca/ov534.c sethvflip(gspca_dev, sd->hflip->val, ctrl->val); val 1193 drivers/media/usb/gspca/ov534.c setlightfreq(gspca_dev, ctrl->val); val 1358 drivers/media/usb/gspca/ov534.c reg_w_array(gspca_dev, bridge_init[sd->sensor].val, val 1361 drivers/media/usb/gspca/ov534.c sccb_w_array(gspca_dev, sensor_init[sd->sensor].val, val 1409 drivers/media/usb/gspca/ov534.c reg_w_array(gspca_dev, bridge_start[sd->sensor][mode].val, val 1411 drivers/media/usb/gspca/ov534.c sccb_w_array(gspca_dev, sensor_start[sd->sensor][mode].val, val 1106 drivers/media/usb/gspca/ov534_9.c static void reg_w_i(struct gspca_dev *gspca_dev, u16 reg, u8 val) val 1113 drivers/media/usb/gspca/ov534_9.c gspca_dev->usb_buf[0] = val; val 1125 drivers/media/usb/gspca/ov534_9.c static void reg_w(struct gspca_dev *gspca_dev, u16 reg, u8 val) val 1127 drivers/media/usb/gspca/ov534_9.c gspca_dbg(gspca_dev, D_USBO, "reg_w [%04x] = %02x\n", reg, val); val 1128 drivers/media/usb/gspca/ov534_9.c reg_w_i(gspca_dev, reg, val); val 1178 drivers/media/usb/gspca/ov534_9.c static void sccb_write(struct gspca_dev *gspca_dev, u8 reg, u8 val) val 1180 drivers/media/usb/gspca/ov534_9.c gspca_dbg(gspca_dev, D_USBO, "sccb_write [%02x] = %02x\n", reg, val); val 1182 drivers/media/usb/gspca/ov534_9.c reg_w_i(gspca_dev, OV534_REG_WRITE, val); val 1258 drivers/media/usb/gspca/ov534_9.c u8 val; val 1263 drivers/media/usb/gspca/ov534_9.c val = 0x76; val 1264 drivers/media/usb/gspca/ov534_9.c val += sval; val 1265 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x24, val); val 1266 drivers/media/usb/gspca/ov534_9.c val = 0x6a; val 1267 drivers/media/usb/gspca/ov534_9.c val += sval; val 1268 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x25, val); val 1270 drivers/media/usb/gspca/ov534_9.c val = 0x71; val 1272 drivers/media/usb/gspca/ov534_9.c val = 0x94; val 1274 drivers/media/usb/gspca/ov534_9.c val = 0xe6; val 1275 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x26, val); val 1277 drivers/media/usb/gspca/ov534_9.c val = brightness; val 1278 drivers/media/usb/gspca/ov534_9.c if (val < 8) val 1279 drivers/media/usb/gspca/ov534_9.c val = 15 - val; /* f .. 8 */ val 1281 drivers/media/usb/gspca/ov534_9.c val = val - 8; /* 0 .. 7 */ val 1283 drivers/media/usb/gspca/ov534_9.c 0x0f | (val << 4)); val 1287 drivers/media/usb/gspca/ov534_9.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 1290 drivers/media/usb/gspca/ov534_9.c val << 4); val 1295 drivers/media/usb/gspca/ov534_9.c u8 val; val 1298 drivers/media/usb/gspca/ov534_9.c val = sccb_read(gspca_dev, 0x13); /* com8 */ val 1301 drivers/media/usb/gspca/ov534_9.c val |= 0x05; /* agc & aec */ val 1303 drivers/media/usb/gspca/ov534_9.c val &= 0xfa; val 1304 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x13, val); val 1310 drivers/media/usb/gspca/ov534_9.c u8 val; val 1314 drivers/media/usb/gspca/ov534_9.c val = sccb_read(gspca_dev, 0x13); /* com8 */ val 1316 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x13, val); val 1318 drivers/media/usb/gspca/ov534_9.c val = sccb_read(gspca_dev, 0xa1); /* aech */ val 1320 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0xa1, val & 0xe0); /* aec[15:10] = 0 */ val 1323 drivers/media/usb/gspca/ov534_9.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val) val 1325 drivers/media/usb/gspca/ov534_9.c if (val < 0) { /* auto */ val 1326 drivers/media/usb/gspca/ov534_9.c val = sccb_read(gspca_dev, 0x42); /* com17 */ val 1328 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x42, val | 0x40); val 1332 drivers/media/usb/gspca/ov534_9.c if (val != 0) val 1333 drivers/media/usb/gspca/ov534_9.c val = 1 << (val - 1); val 1335 drivers/media/usb/gspca/ov534_9.c val); val 1336 drivers/media/usb/gspca/ov534_9.c val = sccb_read(gspca_dev, 0x42); /* com17 */ val 1338 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x42, val & 0xbf); val 1341 drivers/media/usb/gspca/ov534_9.c static void setsatur(struct gspca_dev *gspca_dev, s32 val) val 1352 drivers/media/usb/gspca/ov534_9.c val1 = matrix[val][0]; val 1353 drivers/media/usb/gspca/ov534_9.c val2 = matrix[val][1]; val 1370 drivers/media/usb/gspca/ov534_9.c u8 val; val 1372 drivers/media/usb/gspca/ov534_9.c val = sccb_read(gspca_dev, 0x13); /* com8 */ val 1375 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x13, val & 0xdf); val 1378 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x13, val | 0x20); val 1380 drivers/media/usb/gspca/ov534_9.c val = sccb_read(gspca_dev, 0x42); /* com17 */ val 1383 drivers/media/usb/gspca/ov534_9.c val |= 0x01; val 1385 drivers/media/usb/gspca/ov534_9.c val &= 0xfe; val 1386 drivers/media/usb/gspca/ov534_9.c sccb_write(gspca_dev, 0x42, val); val 1712 drivers/media/usb/gspca/ov534_9.c setbrightness(gspca_dev, ctrl->val); val 1715 drivers/media/usb/gspca/ov534_9.c setcontrast(gspca_dev, ctrl->val); val 1718 drivers/media/usb/gspca/ov534_9.c setsatur(gspca_dev, ctrl->val); val 1721 drivers/media/usb/gspca/ov534_9.c setlightfreq(gspca_dev, ctrl->val); val 1724 drivers/media/usb/gspca/ov534_9.c setsharpness(gspca_dev, ctrl->val); val 1728 drivers/media/usb/gspca/ov534_9.c setautogain(gspca_dev, ctrl->val); val 1729 drivers/media/usb/gspca/ov534_9.c if (!ctrl->val && gspca_dev->exposure->is_new) val 1730 drivers/media/usb/gspca/ov534_9.c setexposure(gspca_dev, gspca_dev->exposure->val); val 194 drivers/media/usb/gspca/pac207.c static void setcontrol(struct gspca_dev *gspca_dev, u16 reg, u16 val) val 196 drivers/media/usb/gspca/pac207.c pac207_write_reg(gspca_dev, reg, val); val 209 drivers/media/usb/gspca/pac207.c if (ctrl->id == V4L2_CID_AUTOGAIN && ctrl->is_new && ctrl->val) { val 214 drivers/media/usb/gspca/pac207.c gspca_dev->exposure->val = PAC207_EXPOSURE_DEFAULT; val 215 drivers/media/usb/gspca/pac207.c gspca_dev->gain->val = PAC207_GAIN_DEFAULT; val 224 drivers/media/usb/gspca/pac207.c setcontrol(gspca_dev, PAC207_BRIGHTNESS_REG, ctrl->val); val 227 drivers/media/usb/gspca/pac207.c if (gspca_dev->exposure->is_new || (ctrl->is_new && ctrl->val)) val 229 drivers/media/usb/gspca/pac207.c gspca_dev->exposure->val); val 230 drivers/media/usb/gspca/pac207.c if (gspca_dev->gain->is_new || (ctrl->is_new && ctrl->val)) val 232 drivers/media/usb/gspca/pac207.c gspca_dev->gain->val); val 383 drivers/media/usb/gspca/pac7302.c v += (sd->brightness->val - (s32)sd->brightness->maximum) val 385 drivers/media/usb/gspca/pac7302.c v -= delta[i] * sd->contrast->val / (s32)sd->contrast->maximum; val 408 drivers/media/usb/gspca/pac7302.c v = a[i] * sd->saturation->val / (s32)sd->saturation->maximum; val 421 drivers/media/usb/gspca/pac7302.c reg_w(gspca_dev, 0xc6, sd->white_balance->val); val 450 drivers/media/usb/gspca/pac7302.c rgbbalance_ctrl_to_reg_value(sd->red_balance->val)); val 461 drivers/media/usb/gspca/pac7302.c rgbbalance_ctrl_to_reg_value(sd->blue_balance->val)); val 470 drivers/media/usb/gspca/pac7302.c if (gspca_dev->gain->val < 32) { val 471 drivers/media/usb/gspca/pac7302.c reg10 = gspca_dev->gain->val; val 475 drivers/media/usb/gspca/pac7302.c reg12 = gspca_dev->gain->val - 31; val 496 drivers/media/usb/gspca/pac7302.c clockdiv = (90 * gspca_dev->exposure->val + 1999) / 2000; val 521 drivers/media/usb/gspca/pac7302.c exposure = (gspca_dev->exposure->val * 45 * 448) / (1000 * clockdiv); val 539 drivers/media/usb/gspca/pac7302.c hflip = sd->hflip->val; val 542 drivers/media/usb/gspca/pac7302.c vflip = sd->vflip->val; val 559 drivers/media/usb/gspca/pac7302.c reg_w(gspca_dev, 0xb6, sd->sharpness->val); val 579 drivers/media/usb/gspca/pac7302.c if (ctrl->id == V4L2_CID_AUTOGAIN && ctrl->is_new && ctrl->val) { val 584 drivers/media/usb/gspca/pac7302.c gspca_dev->exposure->val = PAC7302_EXPOSURE_DEFAULT; val 585 drivers/media/usb/gspca/pac7302.c gspca_dev->gain->val = PAC7302_GAIN_DEFAULT; val 609 drivers/media/usb/gspca/pac7302.c if (gspca_dev->exposure->is_new || (ctrl->is_new && ctrl->val)) val 611 drivers/media/usb/gspca/pac7302.c if (gspca_dev->gain->is_new || (ctrl->is_new && ctrl->val)) val 698 drivers/media/usb/gspca/pac7302.c atomic_set(&sd->avg_lum, 270 + sd->brightness->val); val 737 drivers/media/usb/gspca/pac7302.c desired_lum = 270 + sd->brightness->val; val 839 drivers/media/usb/gspca/pac7302.c (reg->val <= 0x000000ff) val 844 drivers/media/usb/gspca/pac7302.c value = reg->val; val 285 drivers/media/usb/gspca/pac7311.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 288 drivers/media/usb/gspca/pac7311.c reg_w(gspca_dev, 0x10, val); val 293 drivers/media/usb/gspca/pac7311.c static void setgain(struct gspca_dev *gspca_dev, s32 val) val 297 drivers/media/usb/gspca/pac7311.c reg_w(gspca_dev, 0x0f, gspca_dev->gain->maximum - val + 1); val 303 drivers/media/usb/gspca/pac7311.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 306 drivers/media/usb/gspca/pac7311.c reg_w(gspca_dev, 0x02, val); val 316 drivers/media/usb/gspca/pac7311.c if (gspca_dev->pixfmt.width != 640 && val <= 3) val 327 drivers/media/usb/gspca/pac7311.c if (gspca_dev->pixfmt.width == 640 && val == 2) val 364 drivers/media/usb/gspca/pac7311.c if (ctrl->id == V4L2_CID_AUTOGAIN && ctrl->is_new && ctrl->val) { val 369 drivers/media/usb/gspca/pac7311.c gspca_dev->exposure->val = PAC7311_EXPOSURE_DEFAULT; val 370 drivers/media/usb/gspca/pac7311.c gspca_dev->gain->val = PAC7311_GAIN_DEFAULT; val 379 drivers/media/usb/gspca/pac7311.c setcontrast(gspca_dev, ctrl->val); val 382 drivers/media/usb/gspca/pac7311.c if (gspca_dev->exposure->is_new || (ctrl->is_new && ctrl->val)) val 383 drivers/media/usb/gspca/pac7311.c setexposure(gspca_dev, gspca_dev->exposure->val); val 384 drivers/media/usb/gspca/pac7311.c if (gspca_dev->gain->is_new || (ctrl->is_new && ctrl->val)) val 385 drivers/media/usb/gspca/pac7311.c setgain(gspca_dev, gspca_dev->gain->val); val 388 drivers/media/usb/gspca/pac7311.c sethvflip(gspca_dev, sd->hflip->val, 1); val 159 drivers/media/usb/gspca/se401.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 162 drivers/media/usb/gspca/se401.c se401_write_req(gspca_dev, SE401_REQ_SET_BRT, val, 0); val 165 drivers/media/usb/gspca/se401.c static void setgain(struct gspca_dev *gspca_dev, s32 val) val 167 drivers/media/usb/gspca/se401.c u16 gain = 63 - val; val 177 drivers/media/usb/gspca/se401.c static void setexposure(struct gspca_dev *gspca_dev, s32 val, s32 freq) val 180 drivers/media/usb/gspca/se401.c int integration = val << 6; val 628 drivers/media/usb/gspca/se401.c setbrightness(gspca_dev, ctrl->val); val 631 drivers/media/usb/gspca/se401.c setgain(gspca_dev, ctrl->val); val 634 drivers/media/usb/gspca/se401.c setexposure(gspca_dev, ctrl->val, sd->freq->val); val 289 drivers/media/usb/gspca/sn9c2028.c set_gain(gspca_dev, ctrl->val); val 293 drivers/media/usb/gspca/sn9c2028.c set_gain(gspca_dev, sd->gain->val); val 109 drivers/media/usb/gspca/sn9c20x.c u8 val; val 114 drivers/media/usb/gspca/sn9c20x.c u16 val; val 977 drivers/media/usb/gspca/sn9c20x.c static void i2c_w1(struct gspca_dev *gspca_dev, u8 reg, u8 val) val 989 drivers/media/usb/gspca/sn9c20x.c row[3] = val; val 1002 drivers/media/usb/gspca/sn9c20x.c i2c_w1(gspca_dev, buf->reg, buf->val); val 1007 drivers/media/usb/gspca/sn9c20x.c static void i2c_w2(struct gspca_dev *gspca_dev, u8 reg, u16 val) val 1019 drivers/media/usb/gspca/sn9c20x.c row[3] = val >> 8; val 1020 drivers/media/usb/gspca/sn9c20x.c row[4] = val; val 1032 drivers/media/usb/gspca/sn9c20x.c i2c_w2(gspca_dev, buf->reg, buf->val); val 1037 drivers/media/usb/gspca/sn9c20x.c static void i2c_r1(struct gspca_dev *gspca_dev, u8 reg, u8 *val) val 1055 drivers/media/usb/gspca/sn9c20x.c *val = gspca_dev->usb_buf[4]; val 1058 drivers/media/usb/gspca/sn9c20x.c static void i2c_r2(struct gspca_dev *gspca_dev, u8 reg, u16 *val) val 1076 drivers/media/usb/gspca/sn9c20x.c *val = (gspca_dev->usb_buf[3] << 8) | gspca_dev->usb_buf[4]; val 1330 drivers/media/usb/gspca/sn9c20x.c static void set_gamma(struct gspca_dev *gspca_dev, s32 val) val 1333 drivers/media/usb/gspca/sn9c20x.c u8 gval = val * 0xb8 / 0x100; val 1536 drivers/media/usb/gspca/sn9c20x.c static void set_quality(struct gspca_dev *gspca_dev, s32 val) val 1540 drivers/media/usb/gspca/sn9c20x.c jpeg_set_qual(sd->jpeg_hdr, val); val 1563 drivers/media/usb/gspca/sn9c20x.c reg->val = gspca_dev->usb_buf[0]; val 1568 drivers/media/usb/gspca/sn9c20x.c i2c_r2(gspca_dev, reg->reg, (u16 *) ®->val); val 1571 drivers/media/usb/gspca/sn9c20x.c i2c_r1(gspca_dev, reg->reg, (u8 *) ®->val); val 1587 drivers/media/usb/gspca/sn9c20x.c reg_w1(gspca_dev, reg->reg, reg->val); val 1592 drivers/media/usb/gspca/sn9c20x.c i2c_w2(gspca_dev, reg->reg, reg->val); val 1594 drivers/media/usb/gspca/sn9c20x.c i2c_w1(gspca_dev, reg->reg, reg->val); val 1670 drivers/media/usb/gspca/sn9c20x.c set_cmatrix(gspca_dev, sd->brightness->val, val 1671 drivers/media/usb/gspca/sn9c20x.c sd->contrast->val, sd->saturation->val, sd->hue->val); val 1674 drivers/media/usb/gspca/sn9c20x.c set_gamma(gspca_dev, ctrl->val); val 1678 drivers/media/usb/gspca/sn9c20x.c set_redblue(gspca_dev, sd->blue->val, sd->red->val); val 1682 drivers/media/usb/gspca/sn9c20x.c set_hvflip(gspca_dev, sd->hflip->val, sd->vflip->val); val 1686 drivers/media/usb/gspca/sn9c20x.c set_exposure(gspca_dev, ctrl->val); val 1690 drivers/media/usb/gspca/sn9c20x.c set_gain(gspca_dev, ctrl->val); val 1695 drivers/media/usb/gspca/sn9c20x.c set_gain(gspca_dev, sd->gain->val); val 1697 drivers/media/usb/gspca/sn9c20x.c set_exposure(gspca_dev, sd->exposure->val); val 1700 drivers/media/usb/gspca/sn9c20x.c set_quality(gspca_dev, ctrl->val); val 2213 drivers/media/usb/gspca/sn9c20x.c s32 curqual = sd->jpegqual->cur.val; val 2221 drivers/media/usb/gspca/sn9c20x.c sd->jpegqual->cur.val = new_qual; val 545 drivers/media/usb/gspca/sonixb.c i2cOV[3] = sd->brightness->val; val 562 drivers/media/usb/gspca/sonixb.c if (sd->brightness->val < 127) { val 566 drivers/media/usb/gspca/sonixb.c i2cpbright[4] = 127 - sd->brightness->val; val 568 drivers/media/usb/gspca/sonixb.c i2cpbright[4] = sd->brightness->val - 127; val 582 drivers/media/usb/gspca/sonixb.c u8 gain = gspca_dev->gain->val; val 687 drivers/media/usb/gspca/sonixb.c u16 reg = gspca_dev->exposure->val; val 699 drivers/media/usb/gspca/sonixb.c u8 reg = gspca_dev->exposure->val; val 736 drivers/media/usb/gspca/sonixb.c reg11 = (15 * gspca_dev->exposure->val + 999) / 1000; val 751 drivers/media/usb/gspca/sonixb.c reg10 = (gspca_dev->exposure->val * 15 * reg10_max) val 758 drivers/media/usb/gspca/sonixb.c if (gspca_dev->autogain->val && reg10 < 10) val 796 drivers/media/usb/gspca/sonixb.c if (gspca_dev->exposure->val < 200) { val 797 drivers/media/usb/gspca/sonixb.c i2cpexpo[3] = 255 - (gspca_dev->exposure->val * 255) val 804 drivers/media/usb/gspca/sonixb.c framerate_ctrl = (gspca_dev->exposure->val - 200) val 826 drivers/media/usb/gspca/sonixb.c if (gspca_dev->exposure->val < 150) { val 827 drivers/media/usb/gspca/sonixb.c i2cpexpo[3] = 150 - gspca_dev->exposure->val; val 833 drivers/media/usb/gspca/sonixb.c framerate_ctrl = (gspca_dev->exposure->val - 150) val 859 drivers/media/usb/gspca/sonixb.c switch (sd->plfreq->val) { val 901 drivers/media/usb/gspca/sonixb.c desired_avg_lum = sd->brightness->val * desired_avg_lum / 127; val 961 drivers/media/usb/gspca/sonixb.c if (ctrl->id == V4L2_CID_AUTOGAIN && ctrl->is_new && ctrl->val) { val 966 drivers/media/usb/gspca/sonixb.c gspca_dev->gain->val = gspca_dev->gain->default_value; val 967 drivers/media/usb/gspca/sonixb.c gspca_dev->exposure->val = gspca_dev->exposure->default_value; val 979 drivers/media/usb/gspca/sonixb.c if (gspca_dev->exposure->is_new || (ctrl->is_new && ctrl->val)) val 981 drivers/media/usb/gspca/sonixb.c if (gspca_dev->gain->is_new || (ctrl->is_new && ctrl->val)) val 1228 drivers/media/usb/gspca/sonixj.c static void i2c_w1(struct gspca_dev *gspca_dev, u8 reg, u8 val) val 1235 drivers/media/usb/gspca/sonixj.c gspca_dbg(gspca_dev, D_USBO, "i2c_w1 [%02x] = %02x\n", reg, val); val 1248 drivers/media/usb/gspca/sonixj.c gspca_dev->usb_buf[3] = val; val 1361 drivers/media/usb/gspca/sonixj.c u16 val = 0; val 1384 drivers/media/usb/gspca/sonixj.c val = (gspca_dev->usb_buf[3] << 8) | gspca_dev->usb_buf[4]; val 1389 drivers/media/usb/gspca/sonixj.c if (val != 0xffff) val 1394 drivers/media/usb/gspca/sonixj.c switch (val) { val 1408 drivers/media/usb/gspca/sonixj.c val); val 1416 drivers/media/usb/gspca/sonixj.c u16 val; val 1423 drivers/media/usb/gspca/sonixj.c val = (gspca_dev->usb_buf[3] << 8) | gspca_dev->usb_buf[4]; val 1428 drivers/media/usb/gspca/sonixj.c if (val == 0x7628) { /* soi768 */ val 1436 drivers/media/usb/gspca/sonixj.c gspca_dbg(gspca_dev, D_PROBE, "Sensor ov%04x\n", val); val 1442 drivers/media/usb/gspca/sonixj.c u16 val; val 1449 drivers/media/usb/gspca/sonixj.c val = (gspca_dev->usb_buf[3] << 8) | gspca_dev->usb_buf[4]; val 1452 drivers/media/usb/gspca/sonixj.c if ((val & 0xff00) == 0x7600) { /* ov76xx */ val 1453 drivers/media/usb/gspca/sonixj.c gspca_dbg(gspca_dev, D_PROBE, "Sensor ov%04x\n", val); val 1462 drivers/media/usb/gspca/sonixj.c val = (gspca_dev->usb_buf[3] << 8) | gspca_dev->usb_buf[4]; val 1467 drivers/media/usb/gspca/sonixj.c if (val == 0x1030) { /* po1030 */ val 1472 drivers/media/usb/gspca/sonixj.c pr_err("Unknown sensor %04x\n", val); val 1479 drivers/media/usb/gspca/sonixj.c u16 val; val 1487 drivers/media/usb/gspca/sonixj.c val = gspca_dev->usb_buf[4]; val 1490 drivers/media/usb/gspca/sonixj.c if (val == 0x99) { /* gc0307 (?) */ val 1501 drivers/media/usb/gspca/sonixj.c val = (gspca_dev->usb_buf[3] << 8) | gspca_dev->usb_buf[4]; val 1506 drivers/media/usb/gspca/sonixj.c if (val == 0x2030) { val 1510 drivers/media/usb/gspca/sonixj.c pr_err("Unknown sensor ID %04x\n", val); val 1801 drivers/media/usb/gspca/sonixj.c int brightness = sd->brightness->val; val 1850 drivers/media/usb/gspca/sonixj.c k2 = sd->contrast->val * 37 / (CONTRAST_MAX + 1) val 1876 drivers/media/usb/gspca/sonixj.c colors = sd->saturation->val; val 1898 drivers/media/usb/gspca/sonixj.c rg1b[3] = sd->red_bal->val * 2; val 1899 drivers/media/usb/gspca/sonixj.c rg1b[5] = sd->blue_bal->val * 2; val 1903 drivers/media/usb/gspca/sonixj.c reg_w1(gspca_dev, 0x05, sd->red_bal->val); val 1905 drivers/media/usb/gspca/sonixj.c reg_w1(gspca_dev, 0x06, sd->blue_bal->val); val 1911 drivers/media/usb/gspca/sonixj.c int i, val; val 1939 drivers/media/usb/gspca/sonixj.c val = sd->gamma->val; val 1942 drivers/media/usb/gspca/sonixj.c + delta[i] * (val - GAMMA_DEF) / 32; val 1954 drivers/media/usb/gspca/sonixj.c rexpo[3] = gspca_dev->exposure->val >> 8; val 1958 drivers/media/usb/gspca/sonixj.c rexpo[3] = gspca_dev->exposure->val; val 1976 drivers/media/usb/gspca/sonixj.c if (gspca_dev->autogain->val) val 1982 drivers/media/usb/gspca/sonixj.c if (gspca_dev->autogain->val) val 1996 drivers/media/usb/gspca/sonixj.c rgain[3] = gspca_dev->gain->val; val 2009 drivers/media/usb/gspca/sonixj.c if (sd->vflip->val) val 2015 drivers/media/usb/gspca/sonixj.c if (!sd->vflip->val) val 2021 drivers/media/usb/gspca/sonixj.c if (sd->vflip->val) val 2035 drivers/media/usb/gspca/sonixj.c if (sd->hflip->val) val 2037 drivers/media/usb/gspca/sonixj.c if (sd->vflip->val) val 2048 drivers/media/usb/gspca/sonixj.c reg_w1(gspca_dev, 0x99, sd->sharpness->val); val 2058 drivers/media/usb/gspca/sonixj.c sd->illum->val ? 0x64 : 0x60); val 2062 drivers/media/usb/gspca/sonixj.c sd->illum->val ? 0x77 : 0x74); val 2078 drivers/media/usb/gspca/sonixj.c switch (sd->freq->val) { val 2106 drivers/media/usb/gspca/sonixj.c switch (sd->freq->val) { val 164 drivers/media/usb/gspca/spca1528.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 166 drivers/media/usb/gspca/spca1528.c reg_wb(gspca_dev, 0xc0, 0x0000, 0x00c0, val); val 169 drivers/media/usb/gspca/spca1528.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 171 drivers/media/usb/gspca/spca1528.c reg_wb(gspca_dev, 0xc1, 0x0000, 0x00c1, val); val 174 drivers/media/usb/gspca/spca1528.c static void sethue(struct gspca_dev *gspca_dev, s32 val) val 176 drivers/media/usb/gspca/spca1528.c reg_wb(gspca_dev, 0xc2, 0x0000, 0x0000, val); val 179 drivers/media/usb/gspca/spca1528.c static void setcolor(struct gspca_dev *gspca_dev, s32 val) val 181 drivers/media/usb/gspca/spca1528.c reg_wb(gspca_dev, 0xc3, 0x0000, 0x00c3, val); val 184 drivers/media/usb/gspca/spca1528.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val) val 186 drivers/media/usb/gspca/spca1528.c reg_wb(gspca_dev, 0xc4, 0x0000, 0x00c4, val); val 349 drivers/media/usb/gspca/spca1528.c setbrightness(gspca_dev, ctrl->val); val 352 drivers/media/usb/gspca/spca1528.c setcontrast(gspca_dev, ctrl->val); val 355 drivers/media/usb/gspca/spca1528.c sethue(gspca_dev, ctrl->val); val 358 drivers/media/usb/gspca/spca1528.c setcolor(gspca_dev, ctrl->val); val 361 drivers/media/usb/gspca/spca1528.c setsharpness(gspca_dev, ctrl->val); val 863 drivers/media/usb/gspca/spca500.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 866 drivers/media/usb/gspca/spca500.c (__u8) (val - 128)); val 869 drivers/media/usb/gspca/spca500.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 871 drivers/media/usb/gspca/spca500.c reg_w(gspca_dev, 0x00, 0x8168, val); val 874 drivers/media/usb/gspca/spca500.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 876 drivers/media/usb/gspca/spca500.c reg_w(gspca_dev, 0x00, 0x8169, val); val 891 drivers/media/usb/gspca/spca500.c setbrightness(gspca_dev, ctrl->val); val 894 drivers/media/usb/gspca/spca500.c setcontrast(gspca_dev, ctrl->val); val 897 drivers/media/usb/gspca/spca500.c setcolors(gspca_dev, ctrl->val); val 1781 drivers/media/usb/gspca/spca501.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 1783 drivers/media/usb/gspca/spca501.c reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x12, val); val 1786 drivers/media/usb/gspca/spca501.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 1788 drivers/media/usb/gspca/spca501.c reg_write(gspca_dev, 0x00, 0x00, (val >> 8) & 0xff); val 1789 drivers/media/usb/gspca/spca501.c reg_write(gspca_dev, 0x00, 0x01, val & 0xff); val 1792 drivers/media/usb/gspca/spca501.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 1794 drivers/media/usb/gspca/spca501.c reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x0c, val); val 1797 drivers/media/usb/gspca/spca501.c static void setblue_balance(struct gspca_dev *gspca_dev, s32 val) val 1799 drivers/media/usb/gspca/spca501.c reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x11, val); val 1802 drivers/media/usb/gspca/spca501.c static void setred_balance(struct gspca_dev *gspca_dev, s32 val) val 1804 drivers/media/usb/gspca/spca501.c reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x13, val); val 1945 drivers/media/usb/gspca/spca501.c setbrightness(gspca_dev, ctrl->val); val 1948 drivers/media/usb/gspca/spca501.c setcontrast(gspca_dev, ctrl->val); val 1951 drivers/media/usb/gspca/spca501.c setcolors(gspca_dev, ctrl->val); val 1954 drivers/media/usb/gspca/spca501.c setblue_balance(gspca_dev, ctrl->val); val 1957 drivers/media/usb/gspca/spca501.c setred_balance(gspca_dev, ctrl->val); val 724 drivers/media/usb/gspca/spca505.c setbrightness(gspca_dev, ctrl->val); val 478 drivers/media/usb/gspca/spca506.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 481 drivers/media/usb/gspca/spca506.c spca506_WriteI2c(gspca_dev, val, SAA7113_bright); val 485 drivers/media/usb/gspca/spca506.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 488 drivers/media/usb/gspca/spca506.c spca506_WriteI2c(gspca_dev, val, SAA7113_contrast); val 492 drivers/media/usb/gspca/spca506.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 495 drivers/media/usb/gspca/spca506.c spca506_WriteI2c(gspca_dev, val, SAA7113_saturation); val 499 drivers/media/usb/gspca/spca506.c static void sethue(struct gspca_dev *gspca_dev, s32 val) val 502 drivers/media/usb/gspca/spca506.c spca506_WriteI2c(gspca_dev, val, SAA7113_hue); val 518 drivers/media/usb/gspca/spca506.c setbrightness(gspca_dev, ctrl->val); val 521 drivers/media/usb/gspca/spca506.c setcontrast(gspca_dev, ctrl->val); val 524 drivers/media/usb/gspca/spca506.c setcolors(gspca_dev, ctrl->val); val 527 drivers/media/usb/gspca/spca506.c sethue(gspca_dev, ctrl->val); val 1274 drivers/media/usb/gspca/spca508.c u16 reg, u16 val) val 1285 drivers/media/usb/gspca/spca508.c ret = reg_write(gspca_dev, 0x8805, val & 0x00ff); val 1288 drivers/media/usb/gspca/spca508.c val >>= 8; val 1290 drivers/media/usb/gspca/spca508.c ret = reg_write(gspca_dev, 0x8800, val); val 1457 drivers/media/usb/gspca/spca508.c setbrightness(gspca_dev, ctrl->val); val 454 drivers/media/usb/gspca/spca561.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 464 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 0, val); /* R */ val 465 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 1, val); /* Gr */ val 466 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 2, val); /* B */ val 467 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 3, val); /* Gb */ val 493 drivers/media/usb/gspca/spca561.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 516 drivers/media/usb/gspca/spca561.c if (val <= table[i + 1]) { val 517 drivers/media/usb/gspca/spca561.c expo = val - table[i]; val 531 drivers/media/usb/gspca/spca561.c static void setgain(struct gspca_dev *gspca_dev, s32 val) val 536 drivers/media/usb/gspca/spca561.c if (val < 64) val 537 drivers/media/usb/gspca/spca561.c gspca_dev->usb_buf[0] = val; val 538 drivers/media/usb/gspca/spca561.c else if (val < 128) val 539 drivers/media/usb/gspca/spca561.c gspca_dev->usb_buf[0] = (val / 2) | 0x40; val 541 drivers/media/usb/gspca/spca561.c gspca_dev->usb_buf[0] = (val / 4) | 0xc0; val 547 drivers/media/usb/gspca/spca561.c static void setautogain(struct gspca_dev *gspca_dev, s32 val) val 551 drivers/media/usb/gspca/spca561.c if (val) val 762 drivers/media/usb/gspca/spca561.c setbrightness(gspca_dev, ctrl->val); val 766 drivers/media/usb/gspca/spca561.c setwhite(gspca_dev, sd->hue->val, ctrl->val); val 770 drivers/media/usb/gspca/spca561.c setwhite(gspca_dev, ctrl->val, 0); val 773 drivers/media/usb/gspca/spca561.c setexposure(gspca_dev, ctrl->val); val 776 drivers/media/usb/gspca/spca561.c setgain(gspca_dev, ctrl->val); val 779 drivers/media/usb/gspca/spca561.c setautogain(gspca_dev, ctrl->val); val 86 drivers/media/usb/gspca/sq930x.c u16 val; val 485 drivers/media/usb/gspca/sq930x.c u16 val, idx; val 494 drivers/media/usb/gspca/sq930x.c val = (sensor->i2c_addr << 8) | SQ930_CTRL_I2C_IO; val 495 drivers/media/usb/gspca/sq930x.c idx = (cmd->val & 0xff00) | cmd->reg; val 499 drivers/media/usb/gspca/sq930x.c *buf++ = cmd->val; val 504 drivers/media/usb/gspca/sq930x.c *buf++ = cmd->val >> 8; val 506 drivers/media/usb/gspca/sq930x.c *buf++ = cmd->val; val 510 drivers/media/usb/gspca/sq930x.c val, idx, gspca_dev->usb_buf[0], buf[-1]); val 515 drivers/media/usb/gspca/sq930x.c val, idx, val 530 drivers/media/usb/gspca/sq930x.c u16 val, idx; val 548 drivers/media/usb/gspca/sq930x.c val = (cmd->bw_addr << 8) | SQ930_CTRL_UCBUS_IO; val 560 drivers/media/usb/gspca/sq930x.c val, idx, val 564 drivers/media/usb/gspca/sq930x.c val, idx); val 569 drivers/media/usb/gspca/sq930x.c val, idx, val 584 drivers/media/usb/gspca/sq930x.c static void gpio_set(struct sd *sd, u16 val, u16 mask) val 590 drivers/media/usb/gspca/sq930x.c sd->gpio[0] |= val; val 595 drivers/media/usb/gspca/sq930x.c val >>= 8; val 598 drivers/media/usb/gspca/sq930x.c sd->gpio[1] |= val; val 1077 drivers/media/usb/gspca/sq930x.c setexposure(gspca_dev, ctrl->val, sd->gain->val); val 120 drivers/media/usb/gspca/stk014.c unsigned int val) val 144 drivers/media/usb/gspca/stk014.c gspca_dev->usb_buf[0] = val >> 24; val 145 drivers/media/usb/gspca/stk014.c gspca_dev->usb_buf[1] = val >> 16; val 146 drivers/media/usb/gspca/stk014.c gspca_dev->usb_buf[2] = val >> 8; val 147 drivers/media/usb/gspca/stk014.c gspca_dev->usb_buf[3] = val; val 173 drivers/media/usb/gspca/stk014.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 178 drivers/media/usb/gspca/stk014.c + (val << 16); val 182 drivers/media/usb/gspca/stk014.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 187 drivers/media/usb/gspca/stk014.c + (val << 16); val 191 drivers/media/usb/gspca/stk014.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 196 drivers/media/usb/gspca/stk014.c + (val << 16); val 200 drivers/media/usb/gspca/stk014.c static void setlightfreq(struct gspca_dev *gspca_dev, s32 val) val 202 drivers/media/usb/gspca/stk014.c set_par(gspca_dev, val == 1 val 353 drivers/media/usb/gspca/stk014.c setbrightness(gspca_dev, ctrl->val); val 356 drivers/media/usb/gspca/stk014.c setcontrast(gspca_dev, ctrl->val); val 359 drivers/media/usb/gspca/stk014.c setcolors(gspca_dev, ctrl->val); val 362 drivers/media/usb/gspca/stk014.c setlightfreq(gspca_dev, ctrl->val); val 73 drivers/media/usb/gspca/stk1135.c static void reg_w(struct gspca_dev *gspca_dev, u16 index, u8 val) val 83 drivers/media/usb/gspca/stk1135.c val, val 88 drivers/media/usb/gspca/stk1135.c gspca_dbg(gspca_dev, D_USBO, "reg_w 0x%x:=0x%02x\n", index, val); val 95 drivers/media/usb/gspca/stk1135.c static void reg_w_mask(struct gspca_dev *gspca_dev, u16 index, u8 val, u8 mask) val 97 drivers/media/usb/gspca/stk1135.c val = (reg_r(gspca_dev, index) & ~mask) | (val & mask); val 98 drivers/media/usb/gspca/stk1135.c reg_w(gspca_dev, index, val); val 113 drivers/media/usb/gspca/stk1135.c u8 val; val 116 drivers/media/usb/gspca/stk1135.c val = reg_r(gspca_dev, STK1135_REG_SICTL + 1); val 118 drivers/media/usb/gspca/stk1135.c pr_err("serial bus timeout: status=0x%02x\n", val); val 122 drivers/media/usb/gspca/stk1135.c } while ((val & 0x10) || !(val & 0x05)); val 183 drivers/media/usb/gspca/stk1135.c static void sensor_write(struct gspca_dev *gspca_dev, u16 reg, u16 val) val 186 drivers/media/usb/gspca/stk1135.c sensor_write_16(gspca_dev, reg & 0xff, val); val 190 drivers/media/usb/gspca/stk1135.c u16 reg, u16 val, u16 mask) val 192 drivers/media/usb/gspca/stk1135.c val = (sensor_read(gspca_dev, reg) & ~mask) | (val & mask); val 193 drivers/media/usb/gspca/stk1135.c sensor_write(gspca_dev, reg, val); val 198 drivers/media/usb/gspca/stk1135.c u16 val; val 304 drivers/media/usb/gspca/stk1135.c sensor_write(gspca_dev, cfg[i].reg, cfg[i].val); val 532 drivers/media/usb/gspca/stk1135.c static void sethflip(struct gspca_dev *gspca_dev, s32 val) val 537 drivers/media/usb/gspca/stk1135.c val = !val; val 538 drivers/media/usb/gspca/stk1135.c sensor_write_mask(gspca_dev, 0x020, val ? 0x0002 : 0x0000 , 0x0002); val 541 drivers/media/usb/gspca/stk1135.c static void setvflip(struct gspca_dev *gspca_dev, s32 val) val 546 drivers/media/usb/gspca/stk1135.c val = !val; val 547 drivers/media/usb/gspca/stk1135.c sensor_write_mask(gspca_dev, 0x020, val ? 0x0001 : 0x0000 , 0x0001); val 573 drivers/media/usb/gspca/stk1135.c sethflip(gspca_dev, ctrl->val); val 576 drivers/media/usb/gspca/stk1135.c setvflip(gspca_dev, ctrl->val); val 35 drivers/media/usb/gspca/stv0680.c static int stv_sndctrl(struct gspca_dev *gspca_dev, int set, u8 req, u16 val, val 63 drivers/media/usb/gspca/stv0680.c val, 0, gspca_dev->usb_buf, size, 500); val 105 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c u8 val; val 125 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c val = HDCS_SLEEP_MODE; val 129 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c val = HDCS_RUN_ENABLE; val 136 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c ret = stv06xx_write_sensor(sd, HDCS_REG_CONTROL(sd), val); val 161 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c static int hdcs_set_exposure(struct gspca_dev *gspca_dev, __s32 val) val 179 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c cycles = val * HDCS_CLK_FREQ_MHZ * 257; val 246 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c val, rowexp, srowexp); val 268 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c static int hdcs_set_gain(struct gspca_dev *gspca_dev, __s32 val) val 270 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c gspca_dbg(gspca_dev, D_CONF, "Writing gain %d\n", val); val 272 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c val & 0xff); val 331 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c err = hdcs_set_gain(gspca_dev, ctrl->val); val 334 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c err = hdcs_set_exposure(gspca_dev, ctrl->val); val 522 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c u16 reg, val; val 527 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c stv06xx_read_sensor(sd, reg, &val); val 528 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c pr_info("reg 0x%02x = 0x%02x\n", reg, val); val 125 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h static int hdcs_set_exposure(struct gspca_dev *gspca_dev, __s32 val); val 126 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h static int hdcs_set_gain(struct gspca_dev *gspca_dev, __s32 val); val 85 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = pb0100_set_autogain(gspca_dev, ctrl->val); val 88 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c if (ctrl->val) val 90 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = pb0100_set_gain(gspca_dev, ctrls->gain->val); val 93 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = pb0100_set_exposure(gspca_dev, ctrls->exposure->val); val 96 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = pb0100_set_autogain_target(gspca_dev, ctrl->val); val 321 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c static int pb0100_set_gain(struct gspca_dev *gspca_dev, __s32 val) val 327 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = stv06xx_write_sensor(sd, PB_G1GAIN, val); val 329 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = stv06xx_write_sensor(sd, PB_G2GAIN, val); val 331 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val, err); val 334 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = pb0100_set_red_balance(gspca_dev, ctrls->red->val); val 336 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = pb0100_set_blue_balance(gspca_dev, ctrls->blue->val); val 341 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c static int pb0100_set_red_balance(struct gspca_dev *gspca_dev, __s32 val) val 347 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val += ctrls->gain->val; val 348 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c if (val < 0) val 349 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = 0; val 350 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c else if (val > 255) val 351 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = 255; val 353 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = stv06xx_write_sensor(sd, PB_RGAIN, val); val 355 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val, err); val 360 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c static int pb0100_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val) val 366 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val += ctrls->gain->val; val 367 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c if (val < 0) val 368 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = 0; val 369 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c else if (val > 255) val 370 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = 255; val 372 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = stv06xx_write_sensor(sd, PB_BGAIN, val); val 374 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val, err); val 379 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c static int pb0100_set_exposure(struct gspca_dev *gspca_dev, __s32 val) val 384 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = stv06xx_write_sensor(sd, PB_RINTTIME, val); val 386 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val, err); val 391 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c static int pb0100_set_autogain(struct gspca_dev *gspca_dev, __s32 val) val 397 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c if (val) { val 398 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c if (ctrls->natural->val) val 399 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = BIT(6)|BIT(4)|BIT(0); val 401 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = BIT(4)|BIT(0); val 403 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = 0; val 405 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = stv06xx_write_sensor(sd, PB_EXPGAIN, val); val 407 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val, ctrls->natural->val, err); val 412 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c static int pb0100_set_autogain_target(struct gspca_dev *gspca_dev, __s32 val) val 422 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c brightpixels = (totalpixels * val) >> 8; val 429 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val, err); val 107 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.h static int pb0100_set_gain(struct gspca_dev *gspca_dev, __s32 val); val 108 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.h static int pb0100_set_red_balance(struct gspca_dev *gspca_dev, __s32 val); val 109 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.h static int pb0100_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val); val 110 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.h static int pb0100_set_exposure(struct gspca_dev *gspca_dev, __s32 val); val 111 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.h static int pb0100_set_autogain(struct gspca_dev *gspca_dev, __s32 val); val 112 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.h static int pb0100_set_autogain_target(struct gspca_dev *gspca_dev, __s32 val); val 49 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c static int setbrightness(struct sd *sd, s32 val); val 50 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c static int setcontrast(struct sd *sd, s32 val); val 63 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c err = setbrightness(sd, ctrl->val); val 66 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c err = setcontrast(sd, ctrl->val); val 69 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c err = setgain(sd, ctrl->val); val 72 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c err = setexposure(sd, ctrl->val); val 201 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c static int setbrightness(struct sd *sd, s32 val) val 204 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c return stv06xx_write_bridge(sd, 0x1432, val); val 207 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c static int setcontrast(struct sd *sd, s32 val) val 210 drivers/media/usb/gspca/stv06xx/stv06xx_st6422.c return stv06xx_write_bridge(sd, 0x143a, val | 0xf0); val 44 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c err = vv6410_set_hflip(gspca_dev, ctrl->val); val 49 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c err = vv6410_set_vflip(gspca_dev, ctrl->val); val 52 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c err = vv6410_set_analog_gain(gspca_dev, ctrl->val); val 55 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c err = vv6410_set_exposure(gspca_dev, ctrl->val); val 182 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c static int vv6410_set_hflip(struct gspca_dev *gspca_dev, __s32 val) val 192 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c if (val) val 197 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c gspca_dbg(gspca_dev, D_CONF, "Set horizontal flip to %d\n", val); val 203 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c static int vv6410_set_vflip(struct gspca_dev *gspca_dev, __s32 val) val 213 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c if (val) val 218 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c gspca_dbg(gspca_dev, D_CONF, "Set vertical flip to %d\n", val); val 224 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c static int vv6410_set_analog_gain(struct gspca_dev *gspca_dev, __s32 val) val 229 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c gspca_dbg(gspca_dev, D_CONF, "Set analog gain to %d\n", val); val 230 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c err = stv06xx_write_sensor(sd, VV6410_ANALOGGAIN, 0xf0 | (val & 0xf)); val 235 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c static int vv6410_set_exposure(struct gspca_dev *gspca_dev, __s32 val) val 241 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c val = (val * val >> 14) + val / 4; val 243 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c fine = val % VV6410_CIF_LINELENGTH; val 244 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c coarse = min(512, val / VV6410_CIF_LINELENGTH); val 173 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h static int vv6410_set_hflip(struct gspca_dev *gspca_dev, __s32 val); val 174 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h static int vv6410_set_vflip(struct gspca_dev *gspca_dev, __s32 val); val 175 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h static int vv6410_set_analog_gain(struct gspca_dev *gspca_dev, __s32 val); val 176 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h static int vv6410_set_exposure(struct gspca_dev *gspca_dev, __s32 val); val 107 drivers/media/usb/gspca/sunplus.c u16 val; val 318 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, data->req, data->idx, data->val); val 338 drivers/media/usb/gspca/sunplus.c u8 req, u16 idx, u16 val) val 340 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, req, idx, val); val 344 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, req, idx, val); val 372 drivers/media/usb/gspca/sunplus.c u16 idx, u16 val, u8 endcode, u8 count) val 376 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, req, idx, val); val 518 drivers/media/usb/gspca/sunplus.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 524 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, 0x00, reg, val); val 527 drivers/media/usb/gspca/sunplus.c static void setcontrast(struct gspca_dev *gspca_dev, s32 val) val 533 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, 0x00, reg, val); val 536 drivers/media/usb/gspca/sunplus.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 542 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, 0x00, reg, val); val 928 drivers/media/usb/gspca/sunplus.c setbrightness(gspca_dev, ctrl->val); val 931 drivers/media/usb/gspca/sunplus.c setcontrast(gspca_dev, ctrl->val); val 934 drivers/media/usb/gspca/sunplus.c setcolors(gspca_dev, ctrl->val); val 937 drivers/media/usb/gspca/sunplus.c sd->autogain = ctrl->val; val 383 drivers/media/usb/gspca/t613.c u8 val[6] = {0x62, 0, 0x64, 0, 0x60, 0x05}; val 419 drivers/media/usb/gspca/t613.c val[1] = *p++; val 420 drivers/media/usb/gspca/t613.c val[3] = *p++; val 423 drivers/media/usb/gspca/t613.c reg_w_buf(gspca_dev, val, sizeof val); val 474 drivers/media/usb/gspca/t613.c static void setcolors(struct gspca_dev *gspca_dev, s32 val) val 478 drivers/media/usb/gspca/t613.c reg_to_write = 0x80bb + val * 0x100; /* was 0xc0 */ val 482 drivers/media/usb/gspca/t613.c static void setgamma(struct gspca_dev *gspca_dev, s32 val) val 484 drivers/media/usb/gspca/t613.c gspca_dbg(gspca_dev, D_CONF, "Gamma: %d\n", val); val 486 drivers/media/usb/gspca/t613.c gamma_table[val], sizeof gamma_table[0]); val 496 drivers/media/usb/gspca/t613.c green_gain = sd->gain->val; val 498 drivers/media/usb/gspca/t613.c red_gain = green_gain + sd->red_balance->val; val 504 drivers/media/usb/gspca/t613.c blue_gain = green_gain + sd->blue_balance->val; val 514 drivers/media/usb/gspca/t613.c if (!sd->awb->val) val 520 drivers/media/usb/gspca/t613.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val) val 524 drivers/media/usb/gspca/t613.c reg_to_write = 0x0aa6 + 0x1000 * val; val 529 drivers/media/usb/gspca/t613.c static void setfreq(struct gspca_dev *gspca_dev, s32 val) val 537 drivers/media/usb/gspca/t613.c if (val != 0) val 548 drivers/media/usb/gspca/t613.c switch (val) { val 671 drivers/media/usb/gspca/t613.c static void setmirror(struct gspca_dev *gspca_dev, s32 val) val 676 drivers/media/usb/gspca/t613.c if (val) val 682 drivers/media/usb/gspca/t613.c static void seteffect(struct gspca_dev *gspca_dev, s32 val) val 686 drivers/media/usb/gspca/t613.c switch (val) { val 708 drivers/media/usb/gspca/t613.c if (val == V4L2_COLORFX_SKETCH) val 887 drivers/media/usb/gspca/t613.c sd->gain->val = green_gain; val 888 drivers/media/usb/gspca/t613.c sd->red_balance->val = red_gain - green_gain; val 889 drivers/media/usb/gspca/t613.c sd->blue_balance->val = blue_gain - green_gain; val 907 drivers/media/usb/gspca/t613.c setbrightness(gspca_dev, ctrl->val); val 910 drivers/media/usb/gspca/t613.c setcontrast(gspca_dev, ctrl->val); val 913 drivers/media/usb/gspca/t613.c setcolors(gspca_dev, ctrl->val); val 916 drivers/media/usb/gspca/t613.c setgamma(gspca_dev, ctrl->val); val 919 drivers/media/usb/gspca/t613.c setmirror(gspca_dev, ctrl->val); val 922 drivers/media/usb/gspca/t613.c setsharpness(gspca_dev, ctrl->val); val 925 drivers/media/usb/gspca/t613.c setfreq(gspca_dev, ctrl->val); val 928 drivers/media/usb/gspca/t613.c reg_w(gspca_dev, ctrl->val ? 0xf48e : 0xb48e); val 934 drivers/media/usb/gspca/t613.c seteffect(gspca_dev, ctrl->val); val 426 drivers/media/usb/gspca/topro.c u8 val; val 1014 drivers/media/usb/gspca/topro.c reg_w(gspca_dev, p->reg, p->val); val 1041 drivers/media/usb/gspca/topro.c i2c_w(gspca_dev, p->reg, p->val); val 3844 drivers/media/usb/gspca/topro.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val) val 3849 drivers/media/usb/gspca/topro.c val |= 0x08; /* grid compensation enable */ val 3853 drivers/media/usb/gspca/topro.c val |= 0x04; /* scaling down enable */ val 3854 drivers/media/usb/gspca/topro.c reg_w(gspca_dev, TP6800_R5D_DEMOSAIC_CFG, val); val 3856 drivers/media/usb/gspca/topro.c val = (val << 5) | 0x08; val 3857 drivers/media/usb/gspca/topro.c reg_w(gspca_dev, 0x59, val); val 3861 drivers/media/usb/gspca/topro.c static void setautogain(struct gspca_dev *gspca_dev, s32 val) val 3865 drivers/media/usb/gspca/topro.c sd->ag_cnt = val ? AG_CNT_START : -1; val 3936 drivers/media/usb/gspca/topro.c static void setframerate(struct gspca_dev *gspca_dev, s32 val) val 3947 drivers/media/usb/gspca/topro.c if (val >= 128) val 3967 drivers/media/usb/gspca/topro.c s32 val = gspca_dev->gain->val; val 3970 drivers/media/usb/gspca/topro.c s32 old = gspca_dev->gain->cur.val ? val 3971 drivers/media/usb/gspca/topro.c gspca_dev->gain->cur.val : 1; val 3973 drivers/media/usb/gspca/topro.c sd->blue->val = sd->blue->val * val / old; val 3974 drivers/media/usb/gspca/topro.c if (sd->blue->val > 4095) val 3975 drivers/media/usb/gspca/topro.c sd->blue->val = 4095; val 3976 drivers/media/usb/gspca/topro.c sd->red->val = sd->red->val * val / old; val 3977 drivers/media/usb/gspca/topro.c if (sd->red->val > 4095) val 3978 drivers/media/usb/gspca/topro.c sd->red->val = 4095; val 3982 drivers/media/usb/gspca/topro.c setexposure(gspca_dev, gspca_dev->exposure->val, val 3983 drivers/media/usb/gspca/topro.c gspca_dev->gain->val, val 3984 drivers/media/usb/gspca/topro.c sd->blue->val, sd->red->val); val 3986 drivers/media/usb/gspca/topro.c setexposure(gspca_dev, gspca_dev->exposure->val, val 3987 drivers/media/usb/gspca/topro.c gspca_dev->gain->val, 0, 0); val 4849 drivers/media/usb/gspca/topro.c setsharpness(gspca_dev, ctrl->val); val 4852 drivers/media/usb/gspca/topro.c setgamma(gspca_dev, ctrl->val); val 4855 drivers/media/usb/gspca/topro.c setbgain(gspca_dev, ctrl->val); val 4858 drivers/media/usb/gspca/topro.c setrgain(gspca_dev, ctrl->val); val 4864 drivers/media/usb/gspca/topro.c if (ctrl->val) val 4869 drivers/media/usb/gspca/topro.c jpeg_set_qual(sd->jpeg_hdr, ctrl->val); val 236 drivers/media/usb/gspca/touptek.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 242 drivers/media/usb/gspca/touptek.c value = val * 5; val 244 drivers/media/usb/gspca/touptek.c value = val * 3; val 246 drivers/media/usb/gspca/touptek.c value = val * 3 / 2; val 598 drivers/media/usb/gspca/touptek.c setexposure(gspca_dev, ctrl->val); val 602 drivers/media/usb/gspca/touptek.c setggain(gspca_dev, gspca_dev->gain->val); val 605 drivers/media/usb/gspca/touptek.c sd->blue->val = ctrl->val; val 606 drivers/media/usb/gspca/touptek.c setbgain(gspca_dev, sd->blue->val, gspca_dev->gain->val); val 609 drivers/media/usb/gspca/touptek.c sd->red->val = ctrl->val; val 610 drivers/media/usb/gspca/touptek.c setrgain(gspca_dev, sd->red->val, gspca_dev->gain->val); val 187 drivers/media/usb/gspca/tv8532.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 189 drivers/media/usb/gspca/tv8532.c reg_w2(gspca_dev, R1C_AD_EXPOSE_TIMEL, val); val 194 drivers/media/usb/gspca/tv8532.c static void setgain(struct gspca_dev *gspca_dev, s32 val) val 196 drivers/media/usb/gspca/tv8532.c reg_w2(gspca_dev, R20_GAIN_G1L, val); val 197 drivers/media/usb/gspca/tv8532.c reg_w2(gspca_dev, R22_GAIN_RL, val); val 198 drivers/media/usb/gspca/tv8532.c reg_w2(gspca_dev, R24_GAIN_BL, val); val 199 drivers/media/usb/gspca/tv8532.c reg_w2(gspca_dev, R26_GAIN_G2L, val); val 291 drivers/media/usb/gspca/tv8532.c setexposure(gspca_dev, ctrl->val); val 294 drivers/media/usb/gspca/tv8532.c setgain(gspca_dev, ctrl->val); val 3056 drivers/media/usb/gspca/vc032x.c u8 reg, const u8 *val, val 3064 drivers/media/usb/gspca/vc032x.c gspca_dbg(gspca_dev, D_USBO, "i2c_w %02x %02x\n", reg, *val); val 3067 drivers/media/usb/gspca/vc032x.c reg, *val, val[1]); val 3072 drivers/media/usb/gspca/vc032x.c reg_w_i(gspca_dev, 0xa0, val[0], 0xb336); val 3074 drivers/media/usb/gspca/vc032x.c reg_w_i(gspca_dev, 0xa0, val[1], 0xb337); val 3255 drivers/media/usb/gspca/vc032x.c static void setbrightness(struct gspca_dev *gspca_dev, s32 val) val 3259 drivers/media/usb/gspca/vc032x.c data = val; val 3267 drivers/media/usb/gspca/vc032x.c static void setcontrast(struct gspca_dev *gspca_dev, u8 val) val 3269 drivers/media/usb/gspca/vc032x.c i2c_write(gspca_dev, 0x99, &val, 1); val 3272 drivers/media/usb/gspca/vc032x.c static void setcolors(struct gspca_dev *gspca_dev, u8 val) val 3276 drivers/media/usb/gspca/vc032x.c data = val - (val >> 3) - 1; val 3278 drivers/media/usb/gspca/vc032x.c i2c_write(gspca_dev, 0x95, &val, 1); val 3319 drivers/media/usb/gspca/vc032x.c static void setlightfreq(struct gspca_dev *gspca_dev, s32 val) val 3327 drivers/media/usb/gspca/vc032x.c usb_exchange(gspca_dev, ov7660_freq_tb[val]); val 3330 drivers/media/usb/gspca/vc032x.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val) val 3339 drivers/media/usb/gspca/vc032x.c if (val < 0) val 3342 drivers/media/usb/gspca/vc032x.c data = 0xb5 + val * 3; val 3346 drivers/media/usb/gspca/vc032x.c if (val < 0) val 3349 drivers/media/usb/gspca/vc032x.c data = 0x60 + val * 0x0f; val 3354 drivers/media/usb/gspca/vc032x.c static void setgain(struct gspca_dev *gspca_dev, u8 val) val 3356 drivers/media/usb/gspca/vc032x.c i2c_write(gspca_dev, 0x15, &val, 1); val 3359 drivers/media/usb/gspca/vc032x.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 3363 drivers/media/usb/gspca/vc032x.c data = val >> 8; val 3365 drivers/media/usb/gspca/vc032x.c data = val; val 3369 drivers/media/usb/gspca/vc032x.c static void setautogain(struct gspca_dev *gspca_dev, s32 val) val 3373 drivers/media/usb/gspca/vc032x.c i2c_write(gspca_dev, 0xd1, &data[val], 1); val 3382 drivers/media/usb/gspca/vc032x.c static void setbacklight(struct gspca_dev *gspca_dev, s32 val) val 3387 drivers/media/usb/gspca/vc032x.c data = (val << 4) | 0x0f; val 3389 drivers/media/usb/gspca/vc032x.c v = 613 + 12 * val; val 3394 drivers/media/usb/gspca/vc032x.c v = 1093 - 12 * val; val 3399 drivers/media/usb/gspca/vc032x.c v = 342 + 9 * val; val 3404 drivers/media/usb/gspca/vc032x.c v = 702 - 9 * val; val 3661 drivers/media/usb/gspca/vc032x.c setbrightness(gspca_dev, ctrl->val); val 3664 drivers/media/usb/gspca/vc032x.c setcontrast(gspca_dev, ctrl->val); val 3667 drivers/media/usb/gspca/vc032x.c setcolors(gspca_dev, ctrl->val); val 3670 drivers/media/usb/gspca/vc032x.c sethvflip(gspca_dev, sd->hflip->val, sd->vflip->val); val 3673 drivers/media/usb/gspca/vc032x.c setsharpness(gspca_dev, ctrl->val); val 3676 drivers/media/usb/gspca/vc032x.c setautogain(gspca_dev, ctrl->val); val 3679 drivers/media/usb/gspca/vc032x.c setgain(gspca_dev, ctrl->val); val 3682 drivers/media/usb/gspca/vc032x.c setexposure(gspca_dev, ctrl->val); val 3685 drivers/media/usb/gspca/vc032x.c setbacklight(gspca_dev, ctrl->val); val 3688 drivers/media/usb/gspca/vc032x.c setlightfreq(gspca_dev, ctrl->val); val 417 drivers/media/usb/gspca/w996Xcf.c if (sd->freq->val == 1) { val 453 drivers/media/usb/gspca/w996Xcf.c int val, vs_polarity, hs_polarity; val 476 drivers/media/usb/gspca/w996Xcf.c val = sd->gspca_dev.pixfmt.width * sd->gspca_dev.pixfmt.height; val 477 drivers/media/usb/gspca/w996Xcf.c reg_w(sd, 0x3d, val & 0xffff); /* low bits */ val 478 drivers/media/usb/gspca/w996Xcf.c reg_w(sd, 0x3e, val >> 16); /* high bits */ val 500 drivers/media/usb/gspca/w996Xcf.c val = (vs_polarity << 12) | (hs_polarity << 11); val 509 drivers/media/usb/gspca/w996Xcf.c val |= 0x0003; /* YUV420P */ val 511 drivers/media/usb/gspca/w996Xcf.c val |= 0x0080; /* Enable HW double buffering */ val 517 drivers/media/usb/gspca/w996Xcf.c val |= 0x8000; /* capt. enable */ val 519 drivers/media/usb/gspca/w996Xcf.c reg_w(sd, 0x16, val); val 773 drivers/media/usb/gspca/xirlink_cit.c static void cit_Packet_Format1(struct gspca_dev *gspca_dev, u16 fkey, u16 val) val 777 drivers/media/usb/gspca/xirlink_cit.c cit_send_x_00_05_02_08_01(gspca_dev, val); val 787 drivers/media/usb/gspca/xirlink_cit.c static void cit_PacketFormat2(struct gspca_dev *gspca_dev, u16 fkey, u16 val) val 791 drivers/media/usb/gspca/xirlink_cit.c cit_send_x_00_05_02(gspca_dev, val); val 839 drivers/media/usb/gspca/xirlink_cit.c static void cit_model4_BrightnessPacket(struct gspca_dev *gspca_dev, u16 val) val 844 drivers/media/usb/gspca/xirlink_cit.c cit_write_reg(gspca_dev, val, 0x0127); val 1141 drivers/media/usb/gspca/xirlink_cit.c static int cit_set_brightness(struct gspca_dev *gspca_dev, s32 val) val 1153 drivers/media/usb/gspca/xirlink_cit.c cit_Packet_Format1(gspca_dev, 0x0031, val); val 1154 drivers/media/usb/gspca/xirlink_cit.c cit_Packet_Format1(gspca_dev, 0x0032, val); val 1155 drivers/media/usb/gspca/xirlink_cit.c cit_Packet_Format1(gspca_dev, 0x0033, val); val 1160 drivers/media/usb/gspca/xirlink_cit.c i = 0x60 + val * 2254 / 1000; val 1165 drivers/media/usb/gspca/xirlink_cit.c i = val; val 1173 drivers/media/usb/gspca/xirlink_cit.c i = 0x04 + val * 2794 / 1000; val 1181 drivers/media/usb/gspca/xirlink_cit.c static int cit_set_contrast(struct gspca_dev *gspca_dev, s32 val) val 1189 drivers/media/usb/gspca/xirlink_cit.c i = val * 1000 / 1333; val 1192 drivers/media/usb/gspca/xirlink_cit.c i = val * 2000 / 1333; val 1195 drivers/media/usb/gspca/xirlink_cit.c i = val * 4000 / 1333; val 1198 drivers/media/usb/gspca/xirlink_cit.c i = val * 8000 / 1333; val 1209 drivers/media/usb/gspca/xirlink_cit.c int i, new_contrast = (20 - val) * 1000 / 1333; val 1231 drivers/media/usb/gspca/xirlink_cit.c int i = val / 3; val 1238 drivers/media/usb/gspca/xirlink_cit.c cit_model3_Packet1(gspca_dev, 0x005b, val + 1); val 1244 drivers/media/usb/gspca/xirlink_cit.c static int cit_set_hue(struct gspca_dev *gspca_dev, s32 val) val 1255 drivers/media/usb/gspca/xirlink_cit.c cit_model2_Packet1(gspca_dev, 0x0024, val); val 1263 drivers/media/usb/gspca/xirlink_cit.c int i = 0x05 + val * 1000 / 2540; val 1289 drivers/media/usb/gspca/xirlink_cit.c cit_write_reg(gspca_dev, val, 0x012d); /* Hue */ val 1296 drivers/media/usb/gspca/xirlink_cit.c static int cit_set_sharpness(struct gspca_dev *gspca_dev, s32 val) val 1313 drivers/media/usb/gspca/xirlink_cit.c cit_PacketFormat2(gspca_dev, 0x0013, sa[val]); val 1336 drivers/media/usb/gspca/xirlink_cit.c cit_model3_Packet1(gspca_dev, 0x0060, sv[val].sv1); val 1337 drivers/media/usb/gspca/xirlink_cit.c cit_model3_Packet1(gspca_dev, 0x0061, sv[val].sv2); val 1338 drivers/media/usb/gspca/xirlink_cit.c cit_model3_Packet1(gspca_dev, 0x0062, sv[val].sv3); val 1339 drivers/media/usb/gspca/xirlink_cit.c cit_model3_Packet1(gspca_dev, 0x0063, sv[val].sv4); val 1364 drivers/media/usb/gspca/xirlink_cit.c static void cit_set_lighting(struct gspca_dev *gspca_dev, s32 val) val 1378 drivers/media/usb/gspca/xirlink_cit.c cit_Packet_Format1(gspca_dev, 0x0027, val); val 1384 drivers/media/usb/gspca/xirlink_cit.c static void cit_set_hflip(struct gspca_dev *gspca_dev, s32 val) val 1390 drivers/media/usb/gspca/xirlink_cit.c if (val) val 2971 drivers/media/usb/gspca/xirlink_cit.c cit_set_brightness(gspca_dev, ctrl->val); val 2974 drivers/media/usb/gspca/xirlink_cit.c cit_set_contrast(gspca_dev, ctrl->val); val 2977 drivers/media/usb/gspca/xirlink_cit.c cit_set_hue(gspca_dev, ctrl->val); val 2980 drivers/media/usb/gspca/xirlink_cit.c cit_set_hflip(gspca_dev, ctrl->val); val 2983 drivers/media/usb/gspca/xirlink_cit.c cit_set_sharpness(gspca_dev, ctrl->val); val 2986 drivers/media/usb/gspca/xirlink_cit.c cit_set_lighting(gspca_dev, ctrl->val); val 126 drivers/media/usb/gspca/zc3xx.c u8 val; val 5616 drivers/media/usb/gspca/zc3xx.c reg_w(gspca_dev, action->val, action->idx); val 5623 drivers/media/usb/gspca/zc3xx.c action->val, /* reg */ val 5631 drivers/media/usb/gspca/zc3xx.c action->val); /* valH */ val 5693 drivers/media/usb/gspca/zc3xx.c static void setsharpness(struct gspca_dev *gspca_dev, s32 val) val 5702 drivers/media/usb/gspca/zc3xx.c reg_w(gspca_dev, sharpness_tb[val][0], 0x01c6); val 5706 drivers/media/usb/gspca/zc3xx.c reg_w(gspca_dev, sharpness_tb[val][1], 0x01cb); val 5782 drivers/media/usb/gspca/zc3xx.c static void setexposure(struct gspca_dev *gspca_dev, s32 val) val 5788 drivers/media/usb/gspca/zc3xx.c i2c_write(gspca_dev, 0x25, val >> 9, 0x00); val 5789 drivers/media/usb/gspca/zc3xx.c i2c_write(gspca_dev, 0x26, val >> 1, 0x00); val 5790 drivers/media/usb/gspca/zc3xx.c i2c_write(gspca_dev, 0x27, val << 7, 0x00); val 5793 drivers/media/usb/gspca/zc3xx.c i2c_write(gspca_dev, 0x10, val, 0x00); val 5811 drivers/media/usb/gspca/zc3xx.c static void setlightfreq(struct gspca_dev *gspca_dev, s32 val) val 5895 drivers/media/usb/gspca/zc3xx.c i = val * 2; val 5906 drivers/media/usb/gspca/zc3xx.c && val == 1) /* and 50Hz */ val 5912 drivers/media/usb/gspca/zc3xx.c if (val != 0) /* and filter */ val 5924 drivers/media/usb/gspca/zc3xx.c static void setautogain(struct gspca_dev *gspca_dev, s32 val) val 5929 drivers/media/usb/gspca/zc3xx.c i2c_write(gspca_dev, 0x13, val ? 0xa3 : 0x80, 0x00); val 5931 drivers/media/usb/gspca/zc3xx.c reg_w(gspca_dev, val ? 0x42 : 0x02, 0x0180); val 6347 drivers/media/usb/gspca/zc3xx.c if (ctrl->val && sd->exposure && gspca_dev->streaming) val 6348 drivers/media/usb/gspca/zc3xx.c sd->exposure->val = getexposure(gspca_dev); val 6367 drivers/media/usb/gspca/zc3xx.c if (ctrl->val <= jpeg_qual[i]) val 6370 drivers/media/usb/gspca/zc3xx.c if (i == ARRAY_SIZE(jpeg_qual) || (i > 0 && i == qual && ctrl->val < jpeg_qual[i])) val 6379 drivers/media/usb/gspca/zc3xx.c ctrl->val = jpeg_qual[i]; val 6388 drivers/media/usb/gspca/zc3xx.c setcontrast(gspca_dev, sd->gamma->val, val 6389 drivers/media/usb/gspca/zc3xx.c sd->brightness->val, sd->contrast->val); val 6393 drivers/media/usb/gspca/zc3xx.c setautogain(gspca_dev, ctrl->val); val 6394 drivers/media/usb/gspca/zc3xx.c if (!gspca_dev->usb_err && !ctrl->val && sd->exposure) val 6395 drivers/media/usb/gspca/zc3xx.c setexposure(gspca_dev, sd->exposure->val); val 6398 drivers/media/usb/gspca/zc3xx.c setlightfreq(gspca_dev, ctrl->val); val 6401 drivers/media/usb/gspca/zc3xx.c setsharpness(gspca_dev, ctrl->val); val 299 drivers/media/usb/hackrf/hackrf.c if (dev->rx_bandwidth_auto->val == true) val 302 drivers/media/usb/hackrf/hackrf.c uitmp = dev->rx_bandwidth->val; val 310 drivers/media/usb/hackrf/hackrf.c dev->rx_bandwidth->val = uitmp; val 311 drivers/media/usb/hackrf/hackrf.c dev->rx_bandwidth->cur.val = uitmp; val 315 drivers/media/usb/hackrf/hackrf.c if (dev->tx_bandwidth_auto->val == true) val 318 drivers/media/usb/hackrf/hackrf.c uitmp = dev->tx_bandwidth->val; val 326 drivers/media/usb/hackrf/hackrf.c dev->tx_bandwidth->val = uitmp; val 327 drivers/media/usb/hackrf/hackrf.c dev->tx_bandwidth->cur.val = uitmp; val 376 drivers/media/usb/hackrf/hackrf.c dev->rx_rf_gain->cur.val, dev->rx_rf_gain->val); val 378 drivers/media/usb/hackrf/hackrf.c u8tmp = (dev->rx_rf_gain->val) ? 1 : 0; val 388 drivers/media/usb/hackrf/hackrf.c dev->tx_rf_gain->cur.val, dev->tx_rf_gain->val); val 390 drivers/media/usb/hackrf/hackrf.c u8tmp = (dev->tx_rf_gain->val) ? 1 : 0; val 400 drivers/media/usb/hackrf/hackrf.c dev->rx_lna_gain->cur.val, dev->rx_lna_gain->val); val 403 drivers/media/usb/hackrf/hackrf.c dev->rx_lna_gain->val, &u8tmp, 1); val 411 drivers/media/usb/hackrf/hackrf.c dev->rx_if_gain->cur.val, dev->rx_if_gain->val); val 414 drivers/media/usb/hackrf/hackrf.c dev->rx_if_gain->val, &u8tmp, 1); val 422 drivers/media/usb/hackrf/hackrf.c dev->tx_lna_gain->cur.val, dev->tx_lna_gain->val); val 425 drivers/media/usb/hackrf/hackrf.c dev->tx_lna_gain->val, &u8tmp, 1); val 885 drivers/media/usb/hdpvr/hdpvr-video.c if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR && val 886 drivers/media/usb/hdpvr/hdpvr-video.c dev->video_bitrate->val >= dev->video_bitrate_peak->val) val 887 drivers/media/usb/hdpvr/hdpvr-video.c dev->video_bitrate_peak->val = val 888 drivers/media/usb/hdpvr/hdpvr-video.c dev->video_bitrate->val + 100000; val 903 drivers/media/usb/hdpvr/hdpvr-video.c ret = hdpvr_config_call(dev, CTRL_BRIGHTNESS, ctrl->val); val 906 drivers/media/usb/hdpvr/hdpvr-video.c dev->options.brightness = ctrl->val; val 909 drivers/media/usb/hdpvr/hdpvr-video.c ret = hdpvr_config_call(dev, CTRL_CONTRAST, ctrl->val); val 912 drivers/media/usb/hdpvr/hdpvr-video.c dev->options.contrast = ctrl->val; val 915 drivers/media/usb/hdpvr/hdpvr-video.c ret = hdpvr_config_call(dev, CTRL_SATURATION, ctrl->val); val 918 drivers/media/usb/hdpvr/hdpvr-video.c dev->options.saturation = ctrl->val; val 921 drivers/media/usb/hdpvr/hdpvr-video.c ret = hdpvr_config_call(dev, CTRL_HUE, ctrl->val); val 924 drivers/media/usb/hdpvr/hdpvr-video.c dev->options.hue = ctrl->val; val 927 drivers/media/usb/hdpvr/hdpvr-video.c ret = hdpvr_config_call(dev, CTRL_SHARPNESS, ctrl->val); val 930 drivers/media/usb/hdpvr/hdpvr-video.c dev->options.sharpness = ctrl->val; val 934 drivers/media/usb/hdpvr/hdpvr-video.c opt->audio_codec = ctrl->val; val 954 drivers/media/usb/hdpvr/hdpvr-video.c uint peak_bitrate = dev->video_bitrate_peak->val / 100000; val 955 drivers/media/usb/hdpvr/hdpvr-video.c uint bitrate = dev->video_bitrate->val / 100000; val 958 drivers/media/usb/hdpvr/hdpvr-video.c if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) val 965 drivers/media/usb/hdpvr/hdpvr-video.c ctrl->val != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR); val 14 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c static int pvr2_ctrl_range_check(struct pvr2_ctrl *cptr,int val) val 17 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (!cptr->info->check_value(cptr,val)) return -ERANGE; val 19 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (val < 0) return -ERANGE; val 20 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (val >= cptr->info->def.type_enum.count) return -ERANGE; val 27 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (val < lim) return -ERANGE; val 32 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (val > lim) return -ERANGE; val 39 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int pvr2_ctrl_set_value(struct pvr2_ctrl *cptr,int val) val 41 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c return pvr2_ctrl_set_mask_value(cptr,~0,val); val 46 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int pvr2_ctrl_set_mask_value(struct pvr2_ctrl *cptr,int mask,int val) val 56 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c ret = pvr2_ctrl_range_check(cptr,val); val 61 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c ret = cptr->info->set_value(cptr,mask,val); val 183 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int pvr2_ctrl_get_valname(struct pvr2_ctrl *cptr,int val, val 194 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (pvr2_ctrl_range_check(cptr,val) == 0) { val 195 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (names[val]) { val 198 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c names[val]); val 209 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c val &= cptr->info->def.type_bitmask.valid_bits; val 210 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c for (idx = 0, msk = 1; val; idx++, msk <<= 1) { val 211 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (val & msk) { val 270 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int mask,int val, val 276 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c return cptr->info->val_to_sym(cptr,mask,val,buf,maxlen,len); val 291 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c static unsigned int gen_bitmask_string(int msk,int val,int msk_only, val 312 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c ((val & sm) ? "+" : "-")), val 328 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c } else if (um & val) { val 331 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c um & val); val 334 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c } else if (um & ~val) { val 337 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c um & ~val); val 422 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int mask,val,kv,mode,ret; val 424 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c val = 0; val 455 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c val |= kv; val 459 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c val &= ~kv; val 463 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c val |= kv; val 470 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c *valptr = val; val 534 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int mask,int val, val 542 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c *len = scnprintf(buf,maxlen,"%d",val); val 545 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c *len = scnprintf(buf,maxlen,"%s",val ? "true" : "false"); val 550 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if ((val >= 0) && val 551 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c (val < cptr->info->def.type_enum.count)) { val 552 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c if (names[val]) { val 555 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c names[val]); val 563 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c val & mask & cptr->info->def.type_bitmask.valid_bits, val 574 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int mask,int val, val 580 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c ret = pvr2_ctrl_value_to_sym_internal(cptr,mask,val, val 20 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int pvr2_ctrl_set_value(struct pvr2_ctrl *,int val); val 23 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int pvr2_ctrl_set_mask_value(struct pvr2_ctrl *,int mask,int val); val 71 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int mask,int val, val 82 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int mask,int val, val 94 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int mask,int val, val 94 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c int val = hex_to_bin(*buf++); val 95 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (val < 0 || val >= radix) val 98 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c result += val; val 252 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c u32 msk,val; val 270 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c ret = debugifc_parse_unsigned_number(wptr,wlen,&val); val 273 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c val = msk; val 277 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c ret = pvr2_hdw_gpio_chg_dir(hdw,msk,val); val 279 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c ret = pvr2_hdw_gpio_chg_out(hdw,msk,val); val 409 drivers/media/usb/pvrusb2/pvrusb2-encoder.c int val; val 422 drivers/media/usb/pvrusb2/pvrusb2-encoder.c val = 0xf0; val 425 drivers/media/usb/pvrusb2/pvrusb2-encoder.c val = 0x140; val 430 drivers/media/usb/pvrusb2/pvrusb2-encoder.c val, val); val 52 drivers/media/usb/pvrusb2/pvrusb2-hdw-internal.h typedef int (*pvr2_ctlf_set_value)(struct pvr2_ctrl *,int msk,int val); val 53 drivers/media/usb/pvrusb2/pvrusb2-hdw-internal.h typedef int (*pvr2_ctlf_val_to_sym)(struct pvr2_ctrl *,int msk,int val, val 337 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static void trace_stbit(const char *name,int val) val 341 drivers/media/usb/pvrusb2/pvrusb2-hdw.c name,(val ? "true" : "false")); val 521 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val) val 528 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->bounds.left; val 532 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val) val 539 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->bounds.top; val 543 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val) val 550 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->bounds.width; val 554 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val) val 561 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->bounds.height; val 565 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val) val 572 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->defrect.left; val 576 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val) val 583 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->defrect.top; val 587 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val) val 594 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->defrect.width; val 598 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val) val 605 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->defrect.height; val 609 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val) val 616 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->pixelaspect.numerator; val 620 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val) val 627 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *val = cap->pixelaspect.denominator; val 855 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val, val 859 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val); val 914 drivers/media/usb/pvrusb2/pvrusb2-hdw.c int val = 0; val 920 drivers/media/usb/pvrusb2/pvrusb2-hdw.c val |= (1 << V4L2_TUNER_MODE_MONO); val 923 drivers/media/usb/pvrusb2/pvrusb2-hdw.c val |= (1 << V4L2_TUNER_MODE_STEREO); val 926 drivers/media/usb/pvrusb2/pvrusb2-hdw.c val |= (1 << V4L2_TUNER_MODE_LANG1); val 929 drivers/media/usb/pvrusb2/pvrusb2-hdw.c val |= (1 << V4L2_TUNER_MODE_LANG2); val 931 drivers/media/usb/pvrusb2/pvrusb2-hdw.c *vp = val; val 1312 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val) val 1320 drivers/media/usb/pvrusb2/pvrusb2-hdw.c if (hdw->freqValRadio != val) { val 1321 drivers/media/usb/pvrusb2/pvrusb2-hdw.c hdw->freqValRadio = val; val 1331 drivers/media/usb/pvrusb2/pvrusb2-hdw.c if (hdw->freqValTelevision != val) { val 1332 drivers/media/usb/pvrusb2/pvrusb2-hdw.c hdw->freqValTelevision = val; val 2804 drivers/media/usb/pvrusb2/pvrusb2-hdw.c const char *name, int val) val 2809 drivers/media/usb/pvrusb2/pvrusb2-hdw.c pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val); val 2812 drivers/media/usb/pvrusb2/pvrusb2-hdw.c ctrl.value = val; val 2931 drivers/media/usb/pvrusb2/pvrusb2-hdw.c u32 val; val 2937 drivers/media/usb/pvrusb2/pvrusb2-hdw.c val = 48000; val 2940 drivers/media/usb/pvrusb2/pvrusb2-hdw.c val = 44100; val 2943 drivers/media/usb/pvrusb2/pvrusb2-hdw.c val = 32000; val 2947 drivers/media/usb/pvrusb2/pvrusb2-hdw.c audio, s_clock_freq, val); val 3958 drivers/media/usb/pvrusb2/pvrusb2-hdw.c void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val) val 3974 drivers/media/usb/pvrusb2/pvrusb2-hdw.c pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val); val 3976 drivers/media/usb/pvrusb2/pvrusb2-hdw.c da[0] = val ? 0x01 : 0x00; val 3984 drivers/media/usb/pvrusb2/pvrusb2-hdw.c "cpureset_assert(%d) error=%d",val,ret); val 4988 drivers/media/usb/pvrusb2/pvrusb2-hdw.c int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val) val 4995 drivers/media/usb/pvrusb2/pvrusb2-hdw.c nval = (cval & ~msk) | (val & msk); val 4998 drivers/media/usb/pvrusb2/pvrusb2-hdw.c msk,val,cval,nval); val 5000 drivers/media/usb/pvrusb2/pvrusb2-hdw.c nval = val; val 5008 drivers/media/usb/pvrusb2/pvrusb2-hdw.c int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val) val 5015 drivers/media/usb/pvrusb2/pvrusb2-hdw.c nval = (cval & ~msk) | (val & msk); val 5018 drivers/media/usb/pvrusb2/pvrusb2-hdw.c msk,val,cval,nval); val 5020 drivers/media/usb/pvrusb2/pvrusb2-hdw.c nval = val; val 268 drivers/media/usb/pvrusb2/pvrusb2-hdw.h int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val); val 269 drivers/media/usb/pvrusb2/pvrusb2-hdw.h int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val); val 235 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c u16 val; val 238 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c val = dat[1]; val 239 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c val <<= 8; val 240 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c val |= dat[2]; val 241 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c val >>= 1; val 242 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c val &= ~0x0003; val 243 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c val |= 0x8000; val 244 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c rdata[0] = (val >> 8) & 0xffu; val 245 drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c rdata[1] = val & 0xffu; val 594 drivers/media/usb/pvrusb2/pvrusb2-io.c unsigned int val; val 610 drivers/media/usb/pvrusb2/pvrusb2-io.c val = bp->id << 24; val 611 drivers/media/usb/pvrusb2/pvrusb2-io.c val |= idx; val 612 drivers/media/usb/pvrusb2/pvrusb2-io.c ((unsigned int *)(bp->ptr))[idx] = val; val 113 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c long val; val 115 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c val = pvr2_ctrl_get_min(cip->cptr); val 117 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c cip->chptr, cip->ctl_id, val); val 118 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c return scnprintf(buf, PAGE_SIZE, "%ld\n", val); val 126 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c long val; val 128 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c val = pvr2_ctrl_get_max(cip->cptr); val 130 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c cip->chptr, cip->ctl_id, val); val 131 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c return scnprintf(buf, PAGE_SIZE, "%ld\n", val); val 139 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c int val; val 143 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c ret = pvr2_ctrl_get_def(cip->cptr, &val); val 145 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c ret = pvr2_ctrl_value_to_sym(cip->cptr, ~0, val, val 148 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c cip->chptr, cip->ctl_id, cnt, buf, val); val 158 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c int val; val 162 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c ret = pvr2_ctrl_get_value(cip->cptr, &val); val 164 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c ret = pvr2_ctrl_value_to_sym(cip->cptr, ~0, val, val 167 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c cip->chptr, cip->ctl_id, cnt, buf, val); val 177 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c int val; val 181 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c ret = pvr2_ctrl_get_value(cip->cptr, &val); val 183 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c ret = pvr2_ctrl_custom_value_to_sym(cip->cptr, ~0, val, val 186 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c cip->chptr, cip->ctl_id, cnt, buf, val); val 196 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c long val; val 201 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c for (val = 0; val < ecnt; val++) { val 202 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c pvr2_ctrl_get_valname(cip->cptr, val, buf + bcnt, val 244 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c int mask,val; val 247 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c &mask, &val); val 250 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c &mask, &val); val 253 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c ret = pvr2_ctrl_set_mask_value(cip->cptr, mask, val); val 128 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val = 0; val 132 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_hdw_get_ctrl_by_id(hdw, PVR2_CID_STDCUR), &val); val 133 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c *std = val; val 153 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val = 0; val 157 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_hdw_get_ctrl_by_id(hdw, PVR2_CID_STDDETECT), &val); val 158 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c *std = val; val 169 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val; val 177 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c val = fh->input_map[vi->index]; val 178 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c switch (val) { val 193 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_ctrl_get_valname(cptr, val, val 216 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val; val 220 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c val = 0; val 221 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c ret = pvr2_ctrl_get_value(cptr, &val); val 224 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c if (fh->input_map[idx] == val) { val 354 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val = 0; val 364 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c &val); val 375 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c val = (val * 2) / 125; val 377 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c val /= 62500; val 378 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c vf->frequency = val; val 396 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val; val 399 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c val = 0; val 402 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c &val); val 403 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c vf->fmt.pix.width = val; val 404 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c val = 0; val 407 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c &val); val 408 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c vf->fmt.pix.height = val; val 506 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val; val 529 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_ctrl_get_def(cptr, &val); val 530 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c vc->default_value = val; val 578 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val = 0; val 582 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c &val); val 583 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c vc->value = val; val 607 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val; val 616 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_ctrl_get_def(cptr, &val); val 618 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c ret = pvr2_ctrl_get_value(cptr, &val); val 629 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c ctrl->value = val; val 707 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val = 0; val 718 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_hdw_get_ctrl_by_id(hdw, PVR2_CID_CROPL), &val); val 721 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c sel->r.left = val; val 723 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_hdw_get_ctrl_by_id(hdw, PVR2_CID_CROPT), &val); val 726 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c sel->r.top = val; val 728 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_hdw_get_ctrl_by_id(hdw, PVR2_CID_CROPW), &val); val 731 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c sel->r.width = val; val 733 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c pvr2_hdw_get_ctrl_by_id(hdw, PVR2_CID_CROPH), &val); val 736 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c sel->r.height = val; val 1235 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c int val; val 1238 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c PVR2_CID_STDAVAIL), &val); val 1239 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c dip->devbase.tvnorms = (v4l2_std_id)val; val 71 drivers/media/usb/pwc/pwc-dec23.c unsigned int bit, byte, mask, val; val 78 drivers/media/usb/pwc/pwc-dec23.c val = (byte & mask); val 80 drivers/media/usb/pwc/pwc-dec23.c val = -val; val 81 drivers/media/usb/pwc/pwc-dec23.c *p++ = val; val 519 drivers/media/usb/pwc/pwc-v4l.c (pdev->auto_white_balance->val != awb_auto || val 522 drivers/media/usb/pwc/pwc-v4l.c pdev->red_balance->val = pdev->last_red_balance; val 523 drivers/media/usb/pwc/pwc-v4l.c pdev->blue_balance->val = pdev->last_blue_balance; val 528 drivers/media/usb/pwc/pwc-v4l.c &pdev->red_balance->val); val 533 drivers/media/usb/pwc/pwc-v4l.c &pdev->blue_balance->val); val 536 drivers/media/usb/pwc/pwc-v4l.c pdev->last_red_balance = pdev->red_balance->val; val 537 drivers/media/usb/pwc/pwc-v4l.c pdev->last_blue_balance = pdev->blue_balance->val; val 544 drivers/media/usb/pwc/pwc-v4l.c pdev->gain->val = pdev->last_gain; val 548 drivers/media/usb/pwc/pwc-v4l.c READ_AGC_FORMATTER, &pdev->gain->val); val 551 drivers/media/usb/pwc/pwc-v4l.c pdev->last_gain = pdev->gain->val; val 561 drivers/media/usb/pwc/pwc-v4l.c pdev->exposure->val = pdev->last_exposure; val 566 drivers/media/usb/pwc/pwc-v4l.c &pdev->exposure->val); val 569 drivers/media/usb/pwc/pwc-v4l.c pdev->last_exposure = pdev->exposure->val; val 590 drivers/media/usb/pwc/pwc-v4l.c pdev->auto_white_balance->val); val 594 drivers/media/usb/pwc/pwc-v4l.c if (pdev->auto_white_balance->val != awb_manual) val 601 drivers/media/usb/pwc/pwc-v4l.c if (pdev->auto_white_balance->val == awb_indoor || val 602 drivers/media/usb/pwc/pwc-v4l.c pdev->auto_white_balance->val == awb_outdoor || val 603 drivers/media/usb/pwc/pwc-v4l.c pdev->auto_white_balance->val == awb_fl) val 606 drivers/media/usb/pwc/pwc-v4l.c if (pdev->auto_white_balance->val != awb_manual) val 612 drivers/media/usb/pwc/pwc-v4l.c pdev->red_balance->val); val 620 drivers/media/usb/pwc/pwc-v4l.c pdev->blue_balance->val); val 635 drivers/media/usb/pwc/pwc-v4l.c pdev->autogain->val ? 0 : 0xff); val 639 drivers/media/usb/pwc/pwc-v4l.c if (pdev->autogain->val) val 643 drivers/media/usb/pwc/pwc-v4l.c if (pdev->autogain->val) val 649 drivers/media/usb/pwc/pwc-v4l.c pdev->gain->val); val 660 drivers/media/usb/pwc/pwc-v4l.c int is_auto = pdev->exposure_auto->val == V4L2_EXPOSURE_AUTO; val 679 drivers/media/usb/pwc/pwc-v4l.c pdev->exposure->val); val 694 drivers/media/usb/pwc/pwc-v4l.c pdev->autogain->val ? 0 : 0xff); val 698 drivers/media/usb/pwc/pwc-v4l.c if (pdev->autogain->val) { val 704 drivers/media/usb/pwc/pwc-v4l.c if (pdev->autogain->val) val 710 drivers/media/usb/pwc/pwc-v4l.c pdev->gain->val); val 718 drivers/media/usb/pwc/pwc-v4l.c pdev->exposure->val); val 744 drivers/media/usb/pwc/pwc-v4l.c pdev->ctrl_buf[0] = pdev->motor_pan->val & 0xFF; val 745 drivers/media/usb/pwc/pwc-v4l.c pdev->ctrl_buf[1] = (pdev->motor_pan->val >> 8); val 748 drivers/media/usb/pwc/pwc-v4l.c pdev->ctrl_buf[2] = pdev->motor_tilt->val & 0xFF; val 749 drivers/media/usb/pwc/pwc-v4l.c pdev->ctrl_buf[3] = (pdev->motor_tilt->val >> 8); val 771 drivers/media/usb/pwc/pwc-v4l.c BRIGHTNESS_FORMATTER, ctrl->val); val 775 drivers/media/usb/pwc/pwc-v4l.c CONTRAST_FORMATTER, ctrl->val); val 779 drivers/media/usb/pwc/pwc-v4l.c pdev->saturation_fmt, ctrl->val); val 783 drivers/media/usb/pwc/pwc-v4l.c GAMMA_FORMATTER, ctrl->val); val 805 drivers/media/usb/pwc/pwc-v4l.c ctrl->val ? 0 : 0xff); val 811 drivers/media/usb/pwc/pwc-v4l.c pdev->autocontour->val ? 0 : 0xff); val 816 drivers/media/usb/pwc/pwc-v4l.c pdev->contour->val); val 822 drivers/media/usb/pwc/pwc-v4l.c ctrl->val ? 0 : 0xff); val 827 drivers/media/usb/pwc/pwc-v4l.c ctrl->val ? 0 : 0xff); val 832 drivers/media/usb/pwc/pwc-v4l.c ctrl->val); val 847 drivers/media/usb/pwc/pwc-v4l.c ctrl->val); val 852 drivers/media/usb/pwc/pwc-v4l.c ctrl->val); val 1207 drivers/media/usb/s2255/s2255drv.c mode.bright = ctrl->val; val 1210 drivers/media/usb/s2255/s2255drv.c mode.contrast = ctrl->val; val 1213 drivers/media/usb/s2255/s2255drv.c mode.hue = ctrl->val; val 1216 drivers/media/usb/s2255/s2255drv.c mode.saturation = ctrl->val; val 1220 drivers/media/usb/s2255/s2255drv.c mode.color |= !ctrl->val << 16; val 1223 drivers/media/usb/s2255/s2255drv.c vc->jpegqual = ctrl->val; val 147 drivers/media/usb/stk1160/stk1160-core.c stk1160_write_reg(dev, ctl[i].reg, ctl[i].val); val 113 drivers/media/usb/stk1160/stk1160-v4l.c stk1160_write_reg(dev, std525[i].reg, std525[i].val); val 117 drivers/media/usb/stk1160/stk1160-v4l.c stk1160_write_reg(dev, std625[i].reg, std625[i].val); val 125 drivers/media/usb/stk1160/stk1160-v4l.c u32 val = 0; val 134 drivers/media/usb/stk1160/stk1160-v4l.c val |= STK1160_DEC_UNIT_SIZE; val 135 drivers/media/usb/stk1160/stk1160-v4l.c val |= ctrl->col_en ? STK1160_H_DEC_EN : 0; val 136 drivers/media/usb/stk1160/stk1160-v4l.c val |= ctrl->row_en ? STK1160_V_DEC_EN : 0; val 137 drivers/media/usb/stk1160/stk1160-v4l.c val |= ctrl->col_mode == val 140 drivers/media/usb/stk1160/stk1160-v4l.c val |= ctrl->row_mode == val 150 drivers/media/usb/stk1160/stk1160-v4l.c val, ctrl->col_n, ctrl->row_n); val 154 drivers/media/usb/stk1160/stk1160-v4l.c stk1160_write_reg(dev, STK1160_DMCTRL, val); val 593 drivers/media/usb/stk1160/stk1160-v4l.c u8 val; val 596 drivers/media/usb/stk1160/stk1160-v4l.c rc = stk1160_read_reg(dev, reg->reg, &val); val 597 drivers/media/usb/stk1160/stk1160-v4l.c reg->val = val; val 609 drivers/media/usb/stk1160/stk1160-v4l.c return stk1160_write_reg(dev, reg->reg, reg->val); val 162 drivers/media/usb/stk1160/stk1160.h u16 val; val 218 drivers/media/usb/stkwebcam/stk-sensor.c static int stk_sensor_outb(struct stk_camera *dev, u8 reg, u8 val) val 225 drivers/media/usb/stkwebcam/stk-sensor.c if (stk_camera_write_reg(dev, STK_IIC_TX_VALUE, val)) val 243 drivers/media/usb/stkwebcam/stk-sensor.c static int stk_sensor_inb(struct stk_camera *dev, u8 reg, u8 *val) val 267 drivers/media/usb/stkwebcam/stk-sensor.c *val = tmpval; val 277 drivers/media/usb/stkwebcam/stk-sensor.c while (rv->reg != 0xff || rv->val != 0xff) { val 278 drivers/media/usb/stkwebcam/stk-sensor.c ret = stk_sensor_outb(dev, rv->reg, rv->val); val 286 drivers/media/usb/stkwebcam/stk-webcam.c ret = stk_camera_write_reg(dev, rv->reg, rv->val); val 833 drivers/media/usb/stkwebcam/stk-webcam.c return stk_sensor_set_brightness(dev, ctrl->val); val 836 drivers/media/usb/stkwebcam/stk-webcam.c dev->vsettings.hflip = !ctrl->val; val 838 drivers/media/usb/stkwebcam/stk-webcam.c dev->vsettings.hflip = ctrl->val; val 842 drivers/media/usb/stkwebcam/stk-webcam.c dev->vsettings.vflip = !ctrl->val; val 844 drivers/media/usb/stkwebcam/stk-webcam.c dev->vsettings.vflip = ctrl->val; val 72 drivers/media/usb/stkwebcam/stk-webcam.h unsigned val; val 193 drivers/media/usb/tm6000/tm6000-core.c int val; val 195 drivers/media/usb/tm6000/tm6000-core.c val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, 0) & 0xfc; val 197 drivers/media/usb/tm6000/tm6000-core.c tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val); val 199 drivers/media/usb/tm6000/tm6000-core.c tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val | 1); val 398 drivers/media/usb/tm6000/tm6000-core.c u8 val; val 589 drivers/media/usb/tm6000/tm6000-core.c rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val); val 593 drivers/media/usb/tm6000/tm6000-core.c tab[i].req, tab[i].reg, tab[i].val); val 608 drivers/media/usb/tm6000/tm6000-core.c int val = 0; val 630 drivers/media/usb/tm6000/tm6000-core.c val = tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, areg_0a); val 631 drivers/media/usb/tm6000/tm6000-core.c if (val < 0) val 632 drivers/media/usb/tm6000/tm6000-core.c return val; val 634 drivers/media/usb/tm6000/tm6000-core.c val = tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, val 636 drivers/media/usb/tm6000/tm6000-core.c if (val < 0) val 637 drivers/media/usb/tm6000/tm6000-core.c return val; val 639 drivers/media/usb/tm6000/tm6000-core.c val = tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE, val 641 drivers/media/usb/tm6000/tm6000-core.c if (val < 0) val 642 drivers/media/usb/tm6000/tm6000-core.c return val; val 1126 drivers/media/usb/tm6000/tm6000-video.c u8 val = ctrl->val; val 1130 drivers/media/usb/tm6000/tm6000-video.c tm6000_set_reg(dev, TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, val); val 1133 drivers/media/usb/tm6000/tm6000-video.c tm6000_set_reg(dev, TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, val); val 1136 drivers/media/usb/tm6000/tm6000-video.c tm6000_set_reg(dev, TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, val); val 1139 drivers/media/usb/tm6000/tm6000-video.c tm6000_set_reg(dev, TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ, val); val 1153 drivers/media/usb/tm6000/tm6000-video.c u8 val = ctrl->val; val 1157 drivers/media/usb/tm6000/tm6000-video.c dev->ctl_mute = val; val 1158 drivers/media/usb/tm6000/tm6000-video.c tm6000_tvaudio_set_mute(dev, val); val 1161 drivers/media/usb/tm6000/tm6000-video.c dev->ctl_volume = val; val 1162 drivers/media/usb/tm6000/tm6000-video.c tm6000_set_volume(dev, val); val 814 drivers/media/usb/usbtv/usbtv-video.c data[0] |= (ctrl->val >> 8) & 0xf; val 815 drivers/media/usb/usbtv/usbtv-video.c data[2] = ctrl->val & 0xff; val 821 drivers/media/usb/usbtv/usbtv-video.c data[0] |= (ctrl->val >> 4) & 0xf0; val 822 drivers/media/usb/usbtv/usbtv-video.c data[1] = ctrl->val & 0xff; val 826 drivers/media/usb/usbtv/usbtv-video.c data[0] = ctrl->val >> 8; val 827 drivers/media/usb/usbtv/usbtv-video.c data[1] = ctrl->val & 0xff; val 833 drivers/media/usb/usbtv/usbtv-video.c if (ctrl->val > 0) { val 834 drivers/media/usb/usbtv/usbtv-video.c data[0] = 0x92 + (ctrl->val >> 8); val 835 drivers/media/usb/usbtv/usbtv-video.c data[1] = ctrl->val & 0xff; val 837 drivers/media/usb/usbtv/usbtv-video.c data[0] = 0x82 + (-ctrl->val >> 8); val 838 drivers/media/usb/usbtv/usbtv-video.c data[1] = -ctrl->val & 0xff; val 844 drivers/media/usb/usbtv/usbtv-video.c data[1] = ctrl->val; val 173 drivers/media/usb/usbvision/usbvision-video.c s32 val = v4l2_ctrl_g_ctrl(v4l2_ctrl_find(&usbvision->hdl, val 176 drivers/media/usb/usbvision/usbvision-video.c return sprintf(buf, "%d\n", val); val 185 drivers/media/usb/usbvision/usbvision-video.c s32 val = v4l2_ctrl_g_ctrl(v4l2_ctrl_find(&usbvision->hdl, val 188 drivers/media/usb/usbvision/usbvision-video.c return sprintf(buf, "%d\n", val); val 197 drivers/media/usb/usbvision/usbvision-video.c s32 val = v4l2_ctrl_g_ctrl(v4l2_ctrl_find(&usbvision->hdl, val 200 drivers/media/usb/usbvision/usbvision-video.c return sprintf(buf, "%d\n", val); val 209 drivers/media/usb/usbvision/usbvision-video.c s32 val = v4l2_ctrl_g_ctrl(v4l2_ctrl_find(&usbvision->hdl, val 212 drivers/media/usb/usbvision/usbvision-video.c return sprintf(buf, "%d\n", val); val 434 drivers/media/usb/usbvision/usbvision-video.c reg->val = err_code; val 446 drivers/media/usb/usbvision/usbvision-video.c err_code = usbvision_write_reg(usbvision, reg->reg & 0xff, reg->val); val 1041 drivers/media/usb/uvc/uvc_ctrl.c s32 val; val 1042 drivers/media/usb/uvc/uvc_ctrl.c int ret = __uvc_ctrl_get(chain, master_ctrl, master_map, &val); val 1046 drivers/media/usb/uvc/uvc_ctrl.c if (val != mapping->master_manual) val 1262 drivers/media/usb/uvc/uvc_ctrl.c s32 val = 0; val 1268 drivers/media/usb/uvc/uvc_ctrl.c if (__uvc_ctrl_get(chain, ctrl, mapping, &val) == 0) val 1271 drivers/media/usb/uvc/uvc_ctrl.c uvc_ctrl_send_event(chain, handle, ctrl, mapping, val, changes); val 1423 drivers/media/usb/uvc/uvc_ctrl.c s32 val = 0; val 1425 drivers/media/usb/uvc/uvc_ctrl.c if (__uvc_ctrl_get(handle->chain, ctrl, mapping, &val) == 0) val 1428 drivers/media/usb/uvc/uvc_ctrl.c uvc_ctrl_fill_event(handle->chain, &ev, ctrl, mapping, val, val 2364 drivers/media/usb/uvc/uvc_driver.c static int uvc_clock_param_set(const char *val, const struct kernel_param *kp) val 2366 drivers/media/usb/uvc/uvc_driver.c if (strncasecmp(val, "clock_", strlen("clock_")) == 0) val 2367 drivers/media/usb/uvc/uvc_driver.c val += strlen("clock_"); val 2369 drivers/media/usb/uvc/uvc_driver.c if (strcasecmp(val, "monotonic") == 0) val 2371 drivers/media/usb/uvc/uvc_driver.c else if (strcasecmp(val, "realtime") == 0) val 734 drivers/media/usb/zr364xx/zr364xx.c temp = (0x60 << 8) + 127 - ctrl->val; val 47 drivers/media/v4l2-core/v4l2-ctrls.c return master->is_auto && master->cur.val == master->manual_mode_value; val 54 drivers/media/v4l2-core/v4l2-ctrls.c return master->is_auto && master->val == master->manual_mode_value; val 1645 drivers/media/v4l2-core/v4l2-ctrls.c #define ROUND_TO_RANGE(val, offset_type, ctrl) \ val 1649 drivers/media/v4l2-core/v4l2-ctrls.c val >= (ctrl)->maximum - (s32)((ctrl)->step / 2)) \ val 1650 drivers/media/v4l2-core/v4l2-ctrls.c val = (ctrl)->maximum; \ val 1652 drivers/media/v4l2-core/v4l2-ctrls.c val += (s32)((ctrl)->step / 2); \ val 1653 drivers/media/v4l2-core/v4l2-ctrls.c val = clamp_t(typeof(val), val, \ val 1655 drivers/media/v4l2-core/v4l2-ctrls.c offset = (val) - (ctrl)->minimum; \ val 1657 drivers/media/v4l2-core/v4l2-ctrls.c val = (ctrl)->minimum + offset; \ val 1763 drivers/media/v4l2-core/v4l2-ctrls.c s64 val; val 1773 drivers/media/v4l2-core/v4l2-ctrls.c val = ptr.p_s64[idx]; val 1774 drivers/media/v4l2-core/v4l2-ctrls.c if (ctrl->maximum >= 0 && val >= ctrl->maximum - (s64)(ctrl->step / 2)) val 1775 drivers/media/v4l2-core/v4l2-ctrls.c val = ctrl->maximum; val 1777 drivers/media/v4l2-core/v4l2-ctrls.c val += (s64)(ctrl->step / 2); val 1778 drivers/media/v4l2-core/v4l2-ctrls.c val = clamp_t(s64, val, ctrl->minimum, ctrl->maximum); val 1779 drivers/media/v4l2-core/v4l2-ctrls.c offset = val - ctrl->minimum; val 2496 drivers/media/v4l2-core/v4l2-ctrls.c ctrl->cur.val = ctrl->val = def; val 2503 drivers/media/v4l2-core/v4l2-ctrls.c ctrl->p_new.p = &ctrl->val; val 2504 drivers/media/v4l2-core/v4l2-ctrls.c ctrl->p_cur.p = &ctrl->cur.val; val 4013 drivers/media/v4l2-core/v4l2-ctrls.c !is_cur_manual(master) && ctrl->val == master->manual_mode_value) val 4055 drivers/media/v4l2-core/v4l2-ctrls.c int __v4l2_ctrl_s_ctrl(struct v4l2_ctrl *ctrl, s32 val) val 4061 drivers/media/v4l2-core/v4l2-ctrls.c ctrl->val = val; val 4066 drivers/media/v4l2-core/v4l2-ctrls.c int __v4l2_ctrl_s_ctrl_int64(struct v4l2_ctrl *ctrl, s64 val) val 4072 drivers/media/v4l2-core/v4l2-ctrls.c *ctrl->p_new.p_s64 = val; val 88 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrl->val); val 90 drivers/media/v4l2-core/v4l2-flash-led-class.c brightness = __intensity_to_led_brightness(ctrl, ctrl->val); val 99 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrl->val = call_flash_op(v4l2_flash, val 104 drivers/media/v4l2-core/v4l2-flash-led-class.c if (ctrls[LED_MODE]->val != V4L2_FLASH_LED_MODE_TORCH) val 129 drivers/media/v4l2-core/v4l2-flash-led-class.c if (ctrls[LED_MODE]->val != V4L2_FLASH_LED_MODE_TORCH) val 141 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrl->val = call_flash_op(v4l2_flash, val 145 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrl->val = __led_brightness_to_intensity(ctrl, val 170 drivers/media/v4l2-core/v4l2-flash-led-class.c c->val = fled_cdev->brightness.val; val 176 drivers/media/v4l2-core/v4l2-flash-led-class.c c->val = is_strobing; val 180 drivers/media/v4l2-core/v4l2-flash-led-class.c return led_get_flash_fault(fled_cdev, &c->val); val 188 drivers/media/v4l2-core/v4l2-flash-led-class.c return ((ctrls[LED_MODE]->val != V4L2_FLASH_LED_MODE_FLASH) || val 189 drivers/media/v4l2-core/v4l2-flash-led-class.c (ctrls[STROBE_SOURCE] && (ctrls[STROBE_SOURCE]->val != val 204 drivers/media/v4l2-core/v4l2-flash-led-class.c switch (c->val) { val 212 drivers/media/v4l2-core/v4l2-flash-led-class.c external_strobe = (ctrls[STROBE_SOURCE]->val == val 239 drivers/media/v4l2-core/v4l2-flash-led-class.c external_strobe = (c->val == V4L2_FLASH_STROBE_SOURCE_EXTERNAL); val 246 drivers/media/v4l2-core/v4l2-flash-led-class.c if (ctrls[LED_MODE]->val != V4L2_FLASH_LED_MODE_FLASH) val 264 drivers/media/v4l2-core/v4l2-flash-led-class.c return led_set_flash_timeout(fled_cdev, c->val); val 270 drivers/media/v4l2-core/v4l2-flash-led-class.c return led_set_flash_brightness(fled_cdev, c->val); val 291 drivers/media/v4l2-core/v4l2-flash-led-class.c c->def = s->val; val 496 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrls[FLASH_TIMEOUT]->val); val 503 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrls[FLASH_INTENSITY]->val); val 515 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrls[LED_MODE]->val != V4L2_FLASH_LED_MODE_TORCH) val 517 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrls[STROBE_SOURCE]->val); val 979 drivers/media/v4l2-core/v4l2-fwnode.c u32 val; val 983 drivers/media/v4l2-core/v4l2-fwnode.c if (fwnode_property_read_u32(child, *props, &val)) val 987 drivers/media/v4l2-core/v4l2-fwnode.c if (val == *args) val 701 drivers/media/v4l2-core/v4l2-ioctl.c p->reg, p->val); val 120 drivers/memory/atmel-ebi.c u32 val; val 122 drivers/memory/atmel-ebi.c ret = of_property_read_u32(np, "atmel,smc-tdf-ns", &val); val 125 drivers/memory/atmel-ebi.c ncycles = DIV_ROUND_UP(val, clk_period_ns); val 142 drivers/memory/atmel-ebi.c ret = of_property_read_u32(np, xlate->name, &val); val 155 drivers/memory/atmel-ebi.c ncycles = DIV_ROUND_UP(val, clk_period_ns); val 523 drivers/memory/atmel-ebi.c u32 val; val 578 drivers/memory/atmel-ebi.c ret = of_property_read_u32(np, "#address-cells", &val); val 584 drivers/memory/atmel-ebi.c reg_cells = val; val 586 drivers/memory/atmel-ebi.c ret = of_property_read_u32(np, "#size-cells", &val); val 592 drivers/memory/atmel-ebi.c reg_cells += val; val 295 drivers/memory/brcmstb_dpfe.c u32 val; val 297 drivers/memory/brcmstb_dpfe.c val = readl_relaxed(regs + REG_DCPU_RESET); val 299 drivers/memory/brcmstb_dpfe.c return !(val & DCPU_RESET_MASK); val 304 drivers/memory/brcmstb_dpfe.c u32 val; val 310 drivers/memory/brcmstb_dpfe.c val = readl_relaxed(regs + REG_DCPU_RESET); val 311 drivers/memory/brcmstb_dpfe.c val |= (1 << DCPU_RESET_SHIFT); val 312 drivers/memory/brcmstb_dpfe.c writel_relaxed(val, regs + REG_DCPU_RESET); val 317 drivers/memory/brcmstb_dpfe.c u32 val; val 324 drivers/memory/brcmstb_dpfe.c val = readl_relaxed(regs + REG_DCPU_RESET); val 325 drivers/memory/brcmstb_dpfe.c val &= ~(1 << DCPU_CLK_DISABLE_SHIFT); val 326 drivers/memory/brcmstb_dpfe.c writel_relaxed(val, regs + REG_DCPU_RESET); val 329 drivers/memory/brcmstb_dpfe.c val = readl_relaxed(regs + REG_DCPU_RESET); val 330 drivers/memory/brcmstb_dpfe.c val &= ~(1 << DCPU_RESET_SHIFT); val 331 drivers/memory/brcmstb_dpfe.c writel_relaxed(val, regs + REG_DCPU_RESET); val 726 drivers/memory/brcmstb_dpfe.c unsigned long val; val 729 drivers/memory/brcmstb_dpfe.c if (kstrtoul(buf, 0, &val) < 0) val 741 drivers/memory/brcmstb_dpfe.c writel_relaxed(val, info + DRAM_INFO_INTERVAL); val 47 drivers/memory/da8xx-ddrctl.c u32 val; val 58 drivers/memory/da8xx-ddrctl.c .val = 0x20, val 144 drivers/memory/da8xx-ddrctl.c reg |= setting->val << knob->shift; val 415 drivers/memory/emif.c u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi; val 425 drivers/memory/emif.c val = t_refi * freq_khz / 10000; val 426 drivers/memory/emif.c ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT; val 435 drivers/memory/emif.c u32 tim1 = 0, val = 0; val 437 drivers/memory/emif.c val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; val 438 drivers/memory/emif.c tim1 |= val << T_WTR_SHIFT; val 441 drivers/memory/emif.c val = DIV_ROUND_UP(timings->tFAW, t_ck*4); val 443 drivers/memory/emif.c val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); val 444 drivers/memory/emif.c tim1 |= (val - 1) << T_RRD_SHIFT; val 446 drivers/memory/emif.c val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; val 447 drivers/memory/emif.c tim1 |= val << T_RC_SHIFT; val 449 drivers/memory/emif.c val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck)); val 450 drivers/memory/emif.c tim1 |= (val - 1) << T_RAS_SHIFT; val 452 drivers/memory/emif.c val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; val 453 drivers/memory/emif.c tim1 |= val << T_WR_SHIFT; val 455 drivers/memory/emif.c val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1; val 456 drivers/memory/emif.c tim1 |= val << T_RCD_SHIFT; val 458 drivers/memory/emif.c val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1; val 459 drivers/memory/emif.c tim1 |= val << T_RP_SHIFT; val 468 drivers/memory/emif.c u32 tim1 = 0, val = 0; val 470 drivers/memory/emif.c val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; val 471 drivers/memory/emif.c tim1 = val << T_WTR_SHIFT; val 478 drivers/memory/emif.c val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1; val 480 drivers/memory/emif.c val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck); val 481 drivers/memory/emif.c val = max(min_tck->tRRD, val) - 1; val 483 drivers/memory/emif.c tim1 |= val << T_RRD_SHIFT; val 485 drivers/memory/emif.c val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck); val 486 drivers/memory/emif.c tim1 |= (val - 1) << T_RC_SHIFT; val 488 drivers/memory/emif.c val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck); val 489 drivers/memory/emif.c val = max(min_tck->tRASmin, val) - 1; val 490 drivers/memory/emif.c tim1 |= val << T_RAS_SHIFT; val 492 drivers/memory/emif.c val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; val 493 drivers/memory/emif.c tim1 |= val << T_WR_SHIFT; val 495 drivers/memory/emif.c val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck)); val 496 drivers/memory/emif.c tim1 |= (val - 1) << T_RCD_SHIFT; val 498 drivers/memory/emif.c val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck)); val 499 drivers/memory/emif.c tim1 |= (val - 1) << T_RP_SHIFT; val 509 drivers/memory/emif.c u32 tim2 = 0, val = 0; val 511 drivers/memory/emif.c val = min_tck->tCKE - 1; val 512 drivers/memory/emif.c tim2 |= val << T_CKE_SHIFT; val 514 drivers/memory/emif.c val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1; val 515 drivers/memory/emif.c tim2 |= val << T_RTP_SHIFT; val 518 drivers/memory/emif.c val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1; val 519 drivers/memory/emif.c tim2 |= val << T_XSNR_SHIFT; val 522 drivers/memory/emif.c tim2 |= val << T_XSRD_SHIFT; val 524 drivers/memory/emif.c val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1; val 525 drivers/memory/emif.c tim2 |= val << T_XP_SHIFT; val 535 drivers/memory/emif.c u32 tim3 = 0, val = 0, t_dqsck; val 537 drivers/memory/emif.c val = timings->tRAS_max_ns / addressing->tREFI_ns - 1; val 538 drivers/memory/emif.c val = val > 0xF ? 0xF : val; val 539 drivers/memory/emif.c tim3 |= val << T_RAS_MAX_SHIFT; val 541 drivers/memory/emif.c val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1; val 542 drivers/memory/emif.c tim3 |= val << T_RFC_SHIFT; val 547 drivers/memory/emif.c val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1; val 549 drivers/memory/emif.c val = DIV_ROUND_UP(t_dqsck, t_ck) - 1; val 551 drivers/memory/emif.c tim3 |= val << T_TDQSCKMAX_SHIFT; val 553 drivers/memory/emif.c val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1; val 554 drivers/memory/emif.c tim3 |= val << ZQ_ZQCS_SHIFT; val 556 drivers/memory/emif.c val = DIV_ROUND_UP(timings->tCKESR, t_ck); val 557 drivers/memory/emif.c val = max(min_tck->tCKESR, val) - 1; val 558 drivers/memory/emif.c tim3 |= val << T_CKESR_SHIFT; val 563 drivers/memory/emif.c val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1; val 564 drivers/memory/emif.c tim3 |= val << T_PDLL_UL_SHIFT; val 573 drivers/memory/emif.c u32 zq = 0, val = 0; val 575 drivers/memory/emif.c val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns; val 576 drivers/memory/emif.c zq |= val << ZQ_REFINTERVAL_SHIFT; val 578 drivers/memory/emif.c val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1; val 579 drivers/memory/emif.c zq |= val << ZQ_ZQCL_MULT_SHIFT; val 581 drivers/memory/emif.c val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1; val 582 drivers/memory/emif.c zq |= val << ZQ_ZQINIT_MULT_SHIFT; val 593 drivers/memory/emif.c val = cs1_used ? 1 : 0; val 594 drivers/memory/emif.c zq |= val << ZQ_CS1EN_SHIFT; val 636 drivers/memory/emif.c u32 idle = 0, val = 0; val 643 drivers/memory/emif.c val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1; val 645 drivers/memory/emif.c val = 0x1FF; val 651 drivers/memory/emif.c idle |= val << DLL_CALIB_INTERVAL_SHIFT; val 659 drivers/memory/emif.c u32 calib = 0, val = 0; val 662 drivers/memory/emif.c val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1; val 664 drivers/memory/emif.c val = 0; /* Disabled when voltage is stable */ val 666 drivers/memory/emif.c calib |= val << DLL_CALIB_INTERVAL_SHIFT; val 675 drivers/memory/emif.c u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0; val 677 drivers/memory/emif.c val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1; val 678 drivers/memory/emif.c phy |= val << READ_LATENCY_SHIFT_4D; val 681 drivers/memory/emif.c val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY; val 683 drivers/memory/emif.c val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY; val 685 drivers/memory/emif.c val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY; val 687 drivers/memory/emif.c phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D; val 160 drivers/memory/jz4780-nemc.c uint32_t smcr, val, cycles; val 188 drivers/memory/jz4780-nemc.c if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) { val 190 drivers/memory/jz4780-nemc.c switch (val) { val 199 drivers/memory/jz4780-nemc.c dev_err(nemc->dev, "unsupported bus width: %u\n", val); val 204 drivers/memory/jz4780-nemc.c if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) { val 206 drivers/memory/jz4780-nemc.c cycles = jz4780_nemc_ns_to_cycles(nemc, val); val 209 drivers/memory/jz4780-nemc.c val, cycles); val 216 drivers/memory/jz4780-nemc.c if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) { val 218 drivers/memory/jz4780-nemc.c cycles = jz4780_nemc_ns_to_cycles(nemc, val); val 221 drivers/memory/jz4780-nemc.c val, cycles); val 228 drivers/memory/jz4780-nemc.c if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) { val 230 drivers/memory/jz4780-nemc.c cycles = jz4780_nemc_ns_to_cycles(nemc, val); val 233 drivers/memory/jz4780-nemc.c val, cycles); val 240 drivers/memory/jz4780-nemc.c if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) { val 242 drivers/memory/jz4780-nemc.c cycles = jz4780_nemc_ns_to_cycles(nemc, val); val 245 drivers/memory/jz4780-nemc.c val, cycles); val 252 drivers/memory/jz4780-nemc.c if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) { val 254 drivers/memory/jz4780-nemc.c cycles = jz4780_nemc_ns_to_cycles(nemc, val); val 257 drivers/memory/jz4780-nemc.c val, cycles); val 143 drivers/memory/omap-gpmc.c #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) val 146 drivers/memory/omap-gpmc.c #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) val 151 drivers/memory/omap-gpmc.c #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18) val 154 drivers/memory/omap-gpmc.c #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) val 155 drivers/memory/omap-gpmc.c #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) val 159 drivers/memory/omap-gpmc.c #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) val 161 drivers/memory/omap-gpmc.c #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) val 163 drivers/memory/omap-gpmc.c #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) val 255 drivers/memory/omap-gpmc.c static void gpmc_write_reg(int idx, u32 val) val 257 drivers/memory/omap-gpmc.c writel_relaxed(val, gpmc_base + idx); val 265 drivers/memory/omap-gpmc.c void gpmc_cs_write_reg(int cs, int idx, u32 val) val 270 drivers/memory/omap-gpmc.c writel_relaxed(val, reg_addr); val 2040 drivers/memory/omap-gpmc.c u32 val; val 2137 drivers/memory/omap-gpmc.c val = 8; val 2138 drivers/memory/omap-gpmc.c of_property_read_u32(child, "nand-bus-width", &val); val 2139 drivers/memory/omap-gpmc.c switch (val) { val 2196 drivers/memory/omap-gpmc.c val = gpmc_read_reg(GPMC_CONFIG); val 2197 drivers/memory/omap-gpmc.c val &= ~GPMC_CONFIG_LIMITEDADDRESS; val 2198 drivers/memory/omap-gpmc.c gpmc_write_reg(GPMC_CONFIG, val); val 65 drivers/memory/pl172.c u32 val; val 67 drivers/memory/pl172.c if (!of_property_read_u32(np, name, &val)) { val 68 drivers/memory/pl172.c cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; val 564 drivers/memory/tegra/tegra124-emc.c u32 val, val2, mask; val 582 drivers/memory/tegra/tegra124-emc.c val = readl(emc->regs + EMC_CFG); val 583 drivers/memory/tegra/tegra124-emc.c if (val & EMC_CFG_PWR_MASK) { val 584 drivers/memory/tegra/tegra124-emc.c val &= ~EMC_CFG_POWER_FEATURES_MASK; val 585 drivers/memory/tegra/tegra124-emc.c writel(val, emc->regs + EMC_CFG); val 596 drivers/memory/tegra/tegra124-emc.c val = readl(emc->regs + EMC_SEL_DPD_CTRL); val 597 drivers/memory/tegra/tegra124-emc.c if (val & mask) { val 598 drivers/memory/tegra/tegra124-emc.c val &= ~mask; val 599 drivers/memory/tegra/tegra124-emc.c writel(val, emc->regs + EMC_SEL_DPD_CTRL); val 603 drivers/memory/tegra/tegra124-emc.c val = readl(emc->regs + EMC_BGBIAS_CTL0); val 607 drivers/memory/tegra/tegra124-emc.c (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) { val 612 drivers/memory/tegra/tegra124-emc.c if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) || val 613 drivers/memory/tegra/tegra124-emc.c (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) { val 624 drivers/memory/tegra/tegra124-emc.c val = readl(emc->regs + EMC_XM2DQSPADCTRL2); val 626 drivers/memory/tegra/tegra124-emc.c !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) { val 627 drivers/memory/tegra/tegra124-emc.c val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE; val 632 drivers/memory/tegra/tegra124-emc.c !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) { val 633 drivers/memory/tegra/tegra124-emc.c val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE; val 638 drivers/memory/tegra/tegra124-emc.c writel(val, emc->regs + EMC_XM2DQSPADCTRL2); val 667 drivers/memory/tegra/tegra124-emc.c val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; val 668 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, val, EMC_CFG); val 680 drivers/memory/tegra/tegra124-emc.c val = timing->emc_auto_cal_config; val 681 drivers/memory/tegra/tegra124-emc.c val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START; val 682 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG); val 694 drivers/memory/tegra/tegra124-emc.c val = (timing->emc_mrs_wait_cnt val 697 drivers/memory/tegra/tegra124-emc.c if (cnt < val) val 698 drivers/memory/tegra/tegra124-emc.c cnt = val; val 700 drivers/memory/tegra/tegra124-emc.c val = timing->emc_mrs_wait_cnt val 702 drivers/memory/tegra/tegra124-emc.c val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) val 705 drivers/memory/tegra/tegra124-emc.c writel(val, emc->regs + EMC_MRS_WAIT_CNT); val 708 drivers/memory/tegra/tegra124-emc.c val = timing->emc_cfg_2; val 709 drivers/memory/tegra/tegra124-emc.c val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR; val 710 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, val, EMC_CFG_2); val 744 drivers/memory/tegra/tegra124-emc.c val = timing->emc_mode_reset; val 746 drivers/memory/tegra/tegra124-emc.c val |= EMC_MODE_SET_DLL_RESET; val 747 drivers/memory/tegra/tegra124-emc.c val |= EMC_MODE_SET_LONG_CNT; val 749 drivers/memory/tegra/tegra124-emc.c val &= ~EMC_MODE_SET_DLL_RESET; val 751 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, val, EMC_MRS); val 790 drivers/memory/tegra/tegra124-emc.c u32 val; val 814 drivers/memory/tegra/tegra124-emc.c val = timing->emc_bgbias_ctl0; val 815 drivers/memory/tegra/tegra124-emc.c val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN; val 816 drivers/memory/tegra/tegra124-emc.c val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD; val 817 drivers/memory/tegra/tegra124-emc.c writel(val, emc->regs + EMC_BGBIAS_CTL0); val 181 drivers/memory/ti-aemif.c u32 set, val; val 209 drivers/memory/ti-aemif.c val = readl(aemif->base + offset); val 210 drivers/memory/ti-aemif.c val &= ~CONFIG_MASK; val 211 drivers/memory/ti-aemif.c val |= set; val 212 drivers/memory/ti-aemif.c writel(val, aemif->base + offset); val 217 drivers/memory/ti-aemif.c static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) val 219 drivers/memory/ti-aemif.c return ((val + 1) * NSEC_PER_MSEC) / clk_rate; val 236 drivers/memory/ti-aemif.c u32 val, offset; val 239 drivers/memory/ti-aemif.c val = readl(aemif->base + offset); val 241 drivers/memory/ti-aemif.c data->ta = aemif_cycles_to_nsec(TA_VAL(val), clk_rate); val 242 drivers/memory/ti-aemif.c data->rhold = aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate); val 243 drivers/memory/ti-aemif.c data->rstrobe = aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate); val 244 drivers/memory/ti-aemif.c data->rsetup = aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate); val 245 drivers/memory/ti-aemif.c data->whold = aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate); val 246 drivers/memory/ti-aemif.c data->wstrobe = aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate); val 247 drivers/memory/ti-aemif.c data->wsetup = aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate); val 248 drivers/memory/ti-aemif.c data->enable_ew = EW_VAL(val); val 249 drivers/memory/ti-aemif.c data->enable_ss = SS_VAL(val); val 250 drivers/memory/ti-aemif.c data->asize = val & ASIZE_MAX; val 267 drivers/memory/ti-aemif.c u32 val; val 291 drivers/memory/ti-aemif.c if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) val 292 drivers/memory/ti-aemif.c data->ta = val; val 294 drivers/memory/ti-aemif.c if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) val 295 drivers/memory/ti-aemif.c data->rhold = val; val 297 drivers/memory/ti-aemif.c if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) val 298 drivers/memory/ti-aemif.c data->rstrobe = val; val 300 drivers/memory/ti-aemif.c if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) val 301 drivers/memory/ti-aemif.c data->rsetup = val; val 303 drivers/memory/ti-aemif.c if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) val 304 drivers/memory/ti-aemif.c data->whold = val; val 306 drivers/memory/ti-aemif.c if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) val 307 drivers/memory/ti-aemif.c data->wstrobe = val; val 309 drivers/memory/ti-aemif.c if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) val 310 drivers/memory/ti-aemif.c data->wsetup = val; val 312 drivers/memory/ti-aemif.c if (!of_property_read_u32(np, "ti,cs-bus-width", &val)) val 313 drivers/memory/ti-aemif.c if (val == 16) val 768 drivers/memstick/host/jmb38x_ms.c unsigned char val; val 770 drivers/memstick/host/jmb38x_ms.c pci_read_config_byte(pdev, PCI_PMOS0_CONTROL, &val); val 772 drivers/memstick/host/jmb38x_ms.c val |= PMOS0_ACTIVE_BITS; val 774 drivers/memstick/host/jmb38x_ms.c val &= ~PMOS0_ACTIVE_BITS; val 775 drivers/memstick/host/jmb38x_ms.c pci_write_config_byte(pdev, PCI_PMOS0_CONTROL, val); val 776 drivers/memstick/host/jmb38x_ms.c dev_dbg(&pdev->dev, "JMB38x: set PMOS0 val 0x%x\n", val); val 779 drivers/memstick/host/jmb38x_ms.c pci_read_config_byte(pdev, PCI_PMOS1_CONTROL, &val); val 781 drivers/memstick/host/jmb38x_ms.c val |= PMOS1_ACTIVE_BITS; val 783 drivers/memstick/host/jmb38x_ms.c val &= ~PMOS1_ACTIVE_BITS; val 784 drivers/memstick/host/jmb38x_ms.c pci_write_config_byte(pdev, PCI_PMOS1_CONTROL, val); val 785 drivers/memstick/host/jmb38x_ms.c dev_dbg(&pdev->dev, "JMB38x: set PMOS1 val 0x%x\n", val); val 788 drivers/memstick/host/jmb38x_ms.c pci_read_config_byte(pdev, PCI_CLOCK_CTL, &val); val 789 drivers/memstick/host/jmb38x_ms.c pci_write_config_byte(pdev, PCI_CLOCK_CTL, val & ~0x0f); val 790 drivers/memstick/host/jmb38x_ms.c pci_write_config_byte(pdev, PCI_CLOCK_CTL, val | 0x01); val 135 drivers/memstick/host/rtsx_pci_ms.c u8 val, trans_mode, dma_dir; val 186 drivers/memstick/host/rtsx_pci_ms.c rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val); val 188 drivers/memstick/host/rtsx_pci_ms.c if (val & (MS_INT_CMDNK | MS_INT_ERR | val 192 drivers/memstick/host/rtsx_pci_ms.c if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) val 234 drivers/memstick/host/rtsx_pci_ms.c u8 val; val 236 drivers/memstick/host/rtsx_pci_ms.c rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val); val 237 drivers/memstick/host/rtsx_pci_ms.c dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val); val 240 drivers/memstick/host/rtsx_pci_ms.c *int_reg = val & 0x0F; val 247 drivers/memstick/host/rtsx_pci_ms.c if (val & MS_CRC16_ERR) val 250 drivers/memstick/host/rtsx_pci_ms.c if (!(val & 0x80)) { val 251 drivers/memstick/host/rtsx_pci_ms.c if (val & (MS_INT_ERR | MS_INT_CMDNK)) val 303 drivers/memstick/host/rtsx_pci_ms.c u8 val; val 305 drivers/memstick/host/rtsx_pci_ms.c rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val); val 306 drivers/memstick/host/rtsx_pci_ms.c dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val); val 309 drivers/memstick/host/rtsx_pci_ms.c *int_reg = val & 0x0F; val 316 drivers/memstick/host/rtsx_pci_ms.c if (val & MS_CRC16_ERR) val 319 drivers/memstick/host/rtsx_pci_ms.c if (!(val & 0x80)) { val 320 drivers/memstick/host/rtsx_pci_ms.c if (val & (MS_INT_ERR | MS_INT_CMDNK)) val 352 drivers/memstick/host/rtsx_usb_ms.c u8 val; val 354 drivers/memstick/host/rtsx_usb_ms.c rtsx_usb_ep0_read_register(ucr, MS_TRANS_CFG, &val); val 355 drivers/memstick/host/rtsx_usb_ms.c dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val); val 358 drivers/memstick/host/rtsx_usb_ms.c *int_reg = val & 0x0F; val 365 drivers/memstick/host/rtsx_usb_ms.c if (val & MS_CRC16_ERR) val 368 drivers/memstick/host/rtsx_usb_ms.c if (!(val & 0x80)) { val 369 drivers/memstick/host/rtsx_usb_ms.c if (val & (MS_INT_ERR | MS_INT_CMDNK)) val 420 drivers/memstick/host/rtsx_usb_ms.c u8 val; val 422 drivers/memstick/host/rtsx_usb_ms.c rtsx_usb_ep0_read_register(ucr, MS_TRANS_CFG, &val); val 423 drivers/memstick/host/rtsx_usb_ms.c dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val); val 426 drivers/memstick/host/rtsx_usb_ms.c *int_reg = val & 0x0F; val 433 drivers/memstick/host/rtsx_usb_ms.c if (val & MS_CRC16_ERR) val 436 drivers/memstick/host/rtsx_usb_ms.c if (!(val & 0x80)) { val 437 drivers/memstick/host/rtsx_usb_ms.c if (val & (MS_INT_ERR | MS_INT_CMDNK)) val 722 drivers/memstick/host/rtsx_usb_ms.c u8 val; val 731 drivers/memstick/host/rtsx_usb_ms.c err = rtsx_usb_read_register(ucr, CARD_INT_PEND, &val); val 744 drivers/memstick/host/rtsx_usb_ms.c if (val & MS_INT) { val 102 drivers/message/fusion/mptbase.c static int mpt_set_debug_level(const char *val, const struct kernel_param *kp); val 221 drivers/message/fusion/mptbase.c #define CHIPREG_WRITE32(addr,val) writel(val, addr) val 222 drivers/message/fusion/mptbase.c #define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr) val 245 drivers/message/fusion/mptbase.c static int mpt_set_debug_level(const char *val, const struct kernel_param *kp) val 247 drivers/message/fusion/mptbase.c int ret = param_set_int(val, kp); val 3208 drivers/message/fusion/mptscsih.c int val = 0; val 3210 drivers/message/fusion/mptscsih.c if (sscanf(buf, "%x", &val) != 1) val 3213 drivers/message/fusion/mptscsih.c ioc->debug_level = val; val 485 drivers/mfd/88pm800.c unsigned int val; val 491 drivers/mfd/88pm800.c ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val); val 496 drivers/mfd/88pm800.c if (val & PM800_ALARM_WAKEUP) { val 55 drivers/mfd/88pm80x.c unsigned int val; val 80 drivers/mfd/88pm80x.c ret = regmap_read(chip->regmap, PM80X_CHIP_ID, &val); val 87 drivers/mfd/88pm80x.c if (chip_mapping[i].id == PM80X_CHIP_ID_NUM(val)) { val 95 drivers/mfd/88pm80x.c "Failed to detect Marvell 88PM800:ChipID[0x%x]\n", val); val 92 drivers/mfd/aat2870-core.c static int __aat2870_read(struct aat2870_data *aat2870, u8 addr, u8 *val) val 102 drivers/mfd/aat2870-core.c *val = aat2870->reg_cache[addr].value; val 112 drivers/mfd/aat2870-core.c ret = i2c_master_recv(aat2870->client, val, 1); val 119 drivers/mfd/aat2870-core.c dev_dbg(aat2870->dev, "read: addr=0x%02x, val=0x%02x\n", addr, *val); val 123 drivers/mfd/aat2870-core.c static int __aat2870_write(struct aat2870_data *aat2870, u8 addr, u8 val) val 140 drivers/mfd/aat2870-core.c msg[1] = val; val 147 drivers/mfd/aat2870-core.c aat2870->reg_cache[addr].value = val; val 149 drivers/mfd/aat2870-core.c dev_dbg(aat2870->dev, "write: addr=0x%02x, val=0x%02x\n", addr, val); val 153 drivers/mfd/aat2870-core.c static int aat2870_read(struct aat2870_data *aat2870, u8 addr, u8 *val) val 158 drivers/mfd/aat2870-core.c ret = __aat2870_read(aat2870, addr, val); val 164 drivers/mfd/aat2870-core.c static int aat2870_write(struct aat2870_data *aat2870, u8 addr, u8 val) val 169 drivers/mfd/aat2870-core.c ret = __aat2870_write(aat2870, addr, val); val 176 drivers/mfd/aat2870-core.c u8 val) val 188 drivers/mfd/aat2870-core.c new_val = (old_val & ~mask) | (val & mask); val 218 drivers/mfd/aat2870-core.c u8 addr, val; val 228 drivers/mfd/aat2870-core.c ret = aat2870->read(aat2870, addr, &val); val 231 drivers/mfd/aat2870-core.c "0x%02x", val); val 279 drivers/mfd/aat2870-core.c unsigned long addr, val; val 304 drivers/mfd/aat2870-core.c ret = kstrtoul(start, 16, &val); val 308 drivers/mfd/aat2870-core.c ret = aat2870->write(aat2870, (u8)addr, (u8)val); val 2311 drivers/mfd/ab8500-debugfs.c uint write, val = 0; val 2385 drivers/mfd/ab8500-debugfs.c ret = kstrtouint(b, 0, &val); val 2397 drivers/mfd/ab8500-debugfs.c cfg->addr, cfg->mask, cfg->shift, val); val 2413 drivers/mfd/ab8500-debugfs.c val = (val & cfg->mask) << (cfg->shift); val 2416 drivers/mfd/ab8500-debugfs.c val = (val & cfg->mask) >> (-cfg->shift); val 2418 drivers/mfd/ab8500-debugfs.c val = val | regvalue; val 2421 drivers/mfd/ab8500-debugfs.c (u8)cfg->bank, (u8)cfg->addr, (u8)val); val 365 drivers/mfd/ab8500-gpadc.c u8 val, low_data, high_data, low_data2, high_data2; val 387 drivers/mfd/ab8500-gpadc.c AB8500_GPADC, AB8500_GPADC_STAT_REG, &val); val 390 drivers/mfd/ab8500-gpadc.c if (!(val & GPADC_BUSY)) val 394 drivers/mfd/ab8500-gpadc.c if (looplimit >= 10 && (val & GPADC_BUSY)) { val 406 drivers/mfd/ab8500-gpadc.c val = channel | AVG_1; val 409 drivers/mfd/ab8500-gpadc.c val = channel | AVG_4; val 412 drivers/mfd/ab8500-gpadc.c val = channel | AVG_8; val 415 drivers/mfd/ab8500-gpadc.c val = channel | AVG_16; val 421 drivers/mfd/ab8500-gpadc.c AB8500_GPADC, AB8500_GPADC_CTRL3_REG, val); val 427 drivers/mfd/ab8500-gpadc.c AB8500_GPADC, AB8500_GPADC_CTRL2_REG, val); val 36 drivers/mfd/ab8500-sysctrl.c union power_supply_propval val; val 56 drivers/mfd/ab8500-sysctrl.c &val); val 59 drivers/mfd/ab8500-sysctrl.c if (!ret && val.intval) { val 72 drivers/mfd/ab8500-sysctrl.c POWER_SUPPLY_PROP_TECHNOLOGY, &val); val 73 drivers/mfd/ab8500-sysctrl.c if (!ret && val.intval != POWER_SUPPLY_TECHNOLOGY_UNKNOWN) { val 43 drivers/mfd/adp5520.c int reg, uint8_t *val) val 53 drivers/mfd/adp5520.c *val = (uint8_t)ret; val 58 drivers/mfd/adp5520.c int reg, uint8_t val) val 62 drivers/mfd/adp5520.c ret = i2c_smbus_write_byte_data(client, reg, val); val 65 drivers/mfd/adp5520.c val, reg); val 91 drivers/mfd/adp5520.c int adp5520_write(struct device *dev, int reg, uint8_t val) val 93 drivers/mfd/adp5520.c return __adp5520_write(to_i2c_client(dev), reg, val); val 97 drivers/mfd/adp5520.c int adp5520_read(struct device *dev, int reg, uint8_t *val) val 99 drivers/mfd/adp5520.c return __adp5520_read(to_i2c_client(dev), reg, val); val 45 drivers/mfd/altera-sysmgr.c unsigned int reg, unsigned int val) val 51 drivers/mfd/altera-sysmgr.c val, 0, 0, 0, 0, 0, &result); val 67 drivers/mfd/altera-sysmgr.c unsigned int reg, unsigned int *val) val 75 drivers/mfd/altera-sysmgr.c *val = (unsigned int)result.a1; val 120 drivers/mfd/arizona-core.c unsigned int val; val 124 drivers/mfd/arizona-core.c &val); val 131 drivers/mfd/arizona-core.c if (val & ARIZONA_AIF3_UNDERCLOCKED_STS) val 133 drivers/mfd/arizona-core.c if (val & ARIZONA_AIF2_UNDERCLOCKED_STS) val 135 drivers/mfd/arizona-core.c if (val & ARIZONA_AIF1_UNDERCLOCKED_STS) val 137 drivers/mfd/arizona-core.c if (val & ARIZONA_ISRC3_UNDERCLOCKED_STS) val 139 drivers/mfd/arizona-core.c if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS) val 141 drivers/mfd/arizona-core.c if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS) val 143 drivers/mfd/arizona-core.c if (val & ARIZONA_FX_UNDERCLOCKED_STS) val 145 drivers/mfd/arizona-core.c if (val & ARIZONA_ASRC_UNDERCLOCKED_STS) val 147 drivers/mfd/arizona-core.c if (val & ARIZONA_DAC_UNDERCLOCKED_STS) val 149 drivers/mfd/arizona-core.c if (val & ARIZONA_ADC_UNDERCLOCKED_STS) val 151 drivers/mfd/arizona-core.c if (val & ARIZONA_MIXER_UNDERCLOCKED_STS) val 160 drivers/mfd/arizona-core.c unsigned int val[3]; val 164 drivers/mfd/arizona-core.c &val[0], 3); val 177 drivers/mfd/arizona-core.c val[0] = ((val[0] & 0x60e0) >> 1) | val 178 drivers/mfd/arizona-core.c ((val[0] & 0x1e00) >> 2) | val 179 drivers/mfd/arizona-core.c (val[0] & 0x000f); val 185 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS) val 187 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS) val 189 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS) val 191 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS) val 193 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS) val 195 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS) val 197 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS) val 199 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS) val 201 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS) val 203 drivers/mfd/arizona-core.c if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS) val 206 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS) val 208 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS) val 210 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS) val 212 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS) val 214 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS) val 216 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS) val 218 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS) val 220 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS) val 222 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_ISRC3_OVERCLOCKED_STS) val 224 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS) val 226 drivers/mfd/arizona-core.c if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS) val 229 drivers/mfd/arizona-core.c if (val[2] & ARIZONA_SPDIF_OVERCLOCKED_STS) val 252 drivers/mfd/arizona-core.c unsigned int val = 0; val 256 drivers/mfd/arizona-core.c ret = regmap_read(arizona->regmap, reg, &val); val 258 drivers/mfd/arizona-core.c if ((val & mask) == target) val 268 drivers/mfd/arizona-core.c dev_err(arizona->dev, "Polling reg 0x%x timed out: %x\n", reg, val); val 513 drivers/mfd/arizona-core.c unsigned int val; val 516 drivers/mfd/arizona-core.c ret = regmap_read(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, &val); val 521 drivers/mfd/arizona-core.c } else if (val & ARIZONA_JD1_ENA) { val 993 drivers/mfd/arizona-core.c unsigned int reg, val; val 1149 drivers/mfd/arizona-core.c ARIZONA_WRITE_SEQUENCER_CTRL_3, &val); val 1154 drivers/mfd/arizona-core.c } else if (val & 0x01) { val 1376 drivers/mfd/arizona-core.c val = (arizona->pdata.micbias[i].mV - 1500) / 100; val 1378 drivers/mfd/arizona-core.c val <<= ARIZONA_MICB1_LVL_SHIFT; val 1381 drivers/mfd/arizona-core.c val |= ARIZONA_MICB1_EXT_CAP; val 1384 drivers/mfd/arizona-core.c val |= ARIZONA_MICB1_DISCH; val 1387 drivers/mfd/arizona-core.c val |= ARIZONA_MICB1_RATE; val 1390 drivers/mfd/arizona-core.c val |= ARIZONA_MICB1_BYPASS; val 1398 drivers/mfd/arizona-core.c ARIZONA_MICB1_RATE, val); val 100 drivers/mfd/arizona-irq.c unsigned int val; val 118 drivers/mfd/arizona-irq.c ARIZONA_AOD_IRQ1, &val); val 122 drivers/mfd/arizona-irq.c else if (val) val 132 drivers/mfd/arizona-irq.c &val); val 133 drivers/mfd/arizona-irq.c if (ret == 0 && val & ARIZONA_IRQ1_STS) { val 210 drivers/mfd/as3722.c u32 val; val 214 drivers/mfd/as3722.c ret = as3722_read(as3722, AS3722_ASIC_ID1_REG, &val); val 220 drivers/mfd/as3722.c if (val != AS3722_DEVICE_ID) { val 221 drivers/mfd/as3722.c dev_err(as3722->dev, "Device is not AS3722, ID is 0x%x\n", val); val 225 drivers/mfd/as3722.c ret = as3722_read(as3722, AS3722_ASIC_ID2_REG, &val); val 231 drivers/mfd/as3722.c dev_info(as3722->dev, "AS3722 with revision 0x%x found\n", val); val 238 drivers/mfd/as3722.c u32 val = 0; val 241 drivers/mfd/as3722.c val |= AS3722_INT_PULL_UP; val 243 drivers/mfd/as3722.c val |= AS3722_I2C_PULL_UP; val 246 drivers/mfd/as3722.c AS3722_INT_PULL_UP | AS3722_I2C_PULL_UP, val); val 352 drivers/mfd/as3722.c u8 val = 0; val 392 drivers/mfd/as3722.c val = AS3722_CTRL_SEQU1_AC_OK_PWR_ON; val 394 drivers/mfd/as3722.c AS3722_CTRL_SEQU1_AC_OK_PWR_ON, val); val 107 drivers/mfd/asic3.c u32 val; val 110 drivers/mfd/asic3.c val = asic3_read_register(asic, reg); val 112 drivers/mfd/asic3.c val |= bits; val 114 drivers/mfd/asic3.c val &= ~bits; val 115 drivers/mfd/asic3.c asic3_write_register(asic, reg, val); val 225 drivers/mfd/asic3.c u32 val, bank, index; val 232 drivers/mfd/asic3.c val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); val 233 drivers/mfd/asic3.c val |= 1 << index; val 234 drivers/mfd/asic3.c asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); val 262 drivers/mfd/asic3.c u32 val, bank, index; val 269 drivers/mfd/asic3.c val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); val 270 drivers/mfd/asic3.c val &= ~(1 << index); val 271 drivers/mfd/asic3.c asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); val 95 drivers/mfd/atmel-flexcom.c u32 val; val 101 drivers/mfd/atmel-flexcom.c val = FLEX_MR_OPMODE(ddata->opmode), val 102 drivers/mfd/atmel-flexcom.c writel(val, ddata->base + FLEX_MR); val 36 drivers/mfd/atmel-hlcdc.c unsigned int val) val 48 drivers/mfd/atmel-hlcdc.c writel(val, hregmap->regs + reg); val 54 drivers/mfd/atmel-hlcdc.c unsigned int *val) val 58 drivers/mfd/atmel-hlcdc.c *val = readl(hregmap->regs + reg); val 96 drivers/mfd/atmel-smc.c unsigned int val; val 112 drivers/mfd/atmel-smc.c ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val); val 114 drivers/mfd/atmel-smc.c conf->timings |= val << shift; val 138 drivers/mfd/atmel-smc.c unsigned int val; val 151 drivers/mfd/atmel-smc.c ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val); val 153 drivers/mfd/atmel-smc.c conf->setup |= val << shift; val 177 drivers/mfd/atmel-smc.c unsigned int val; val 190 drivers/mfd/atmel-smc.c ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val); val 192 drivers/mfd/atmel-smc.c conf->pulse |= val << shift; val 216 drivers/mfd/atmel-smc.c unsigned int val; val 228 drivers/mfd/atmel-smc.c ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val); val 230 drivers/mfd/atmel-smc.c conf->cycle |= val << shift; val 72 drivers/mfd/da903x.c int reg, uint8_t *val) val 82 drivers/mfd/da903x.c *val = (uint8_t)ret; val 87 drivers/mfd/da903x.c int len, uint8_t *val) val 91 drivers/mfd/da903x.c ret = i2c_smbus_read_i2c_block_data(client, reg, len, val); val 100 drivers/mfd/da903x.c int reg, uint8_t val) val 104 drivers/mfd/da903x.c ret = i2c_smbus_write_byte_data(client, reg, val); val 107 drivers/mfd/da903x.c val, reg); val 114 drivers/mfd/da903x.c int len, uint8_t *val) val 118 drivers/mfd/da903x.c ret = i2c_smbus_write_i2c_block_data(client, reg, len, val); val 146 drivers/mfd/da903x.c int da903x_write(struct device *dev, int reg, uint8_t val) val 148 drivers/mfd/da903x.c return __da903x_write(to_i2c_client(dev), reg, val); val 152 drivers/mfd/da903x.c int da903x_writes(struct device *dev, int reg, int len, uint8_t *val) val 154 drivers/mfd/da903x.c return __da903x_writes(to_i2c_client(dev), reg, len, val); val 158 drivers/mfd/da903x.c int da903x_read(struct device *dev, int reg, uint8_t *val) val 160 drivers/mfd/da903x.c return __da903x_read(to_i2c_client(dev), reg, val); val 164 drivers/mfd/da903x.c int da903x_reads(struct device *dev, int reg, int len, uint8_t *val) val 166 drivers/mfd/da903x.c return __da903x_reads(to_i2c_client(dev), reg, len, val); val 214 drivers/mfd/da903x.c int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask) val 226 drivers/mfd/da903x.c if ((reg_val & mask) != val) { val 227 drivers/mfd/da903x.c reg_val = (reg_val & ~mask) | val; val 60 drivers/mfd/da9052-i2c.c int val; val 71 drivers/mfd/da9052-i2c.c &val); val 201 drivers/mfd/da9150-core.c int val, ret; val 203 drivers/mfd/da9150-core.c ret = regmap_read(da9150->regmap, reg, &val); val 208 drivers/mfd/da9150-core.c return (u8) val; val 212 drivers/mfd/da9150-core.c void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val) val 216 drivers/mfd/da9150-core.c ret = regmap_write(da9150->regmap, reg, val); val 223 drivers/mfd/da9150-core.c void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val) val 227 drivers/mfd/da9150-core.c ret = regmap_update_bits(da9150->regmap, reg, mask, val); val 656 drivers/mfd/db8500-prcmu.c u32 val; val 660 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + reg); val 661 drivers/mfd/db8500-prcmu.c val = ((val & ~mask) | (value & mask)); val 662 drivers/mfd/db8500-prcmu.c writel(val, (prcmu_base + reg)); val 685 drivers/mfd/db8500-prcmu.c int prcmu_set_rc_a2p(enum romcode_write val) val 687 drivers/mfd/db8500-prcmu.c if (val < RDY_2_DS || val > RDY_2_XP70_RST) val 689 drivers/mfd/db8500-prcmu.c writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); val 730 drivers/mfd/db8500-prcmu.c u32 val; val 758 drivers/mfd/db8500-prcmu.c val = readl(PRCM_CLKOCR); val 759 drivers/mfd/db8500-prcmu.c if (val & div_mask) { val 761 drivers/mfd/db8500-prcmu.c if ((val & mask) != bits) { val 766 drivers/mfd/db8500-prcmu.c if ((val & mask & ~div_mask) != bits) { val 772 drivers/mfd/db8500-prcmu.c writel((bits | (val & ~mask)), PRCM_CLKOCR); val 958 drivers/mfd/db8500-prcmu.c u32 val; val 961 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clock_reg[i]); val 962 drivers/mfd/db8500-prcmu.c div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); val 975 drivers/mfd/db8500-prcmu.c val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | val 977 drivers/mfd/db8500-prcmu.c writel(val, prcmu_base + clock_reg[i]); val 1311 drivers/mfd/db8500-prcmu.c u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); val 1314 drivers/mfd/db8500-prcmu.c val |= PRCM_TCR_STOP_TIMERS; val 1315 drivers/mfd/db8500-prcmu.c writel(val, PRCM_TCR); val 1322 drivers/mfd/db8500-prcmu.c u32 val; val 1331 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clk_mgt[clock].offset); val 1333 drivers/mfd/db8500-prcmu.c val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); val 1335 drivers/mfd/db8500-prcmu.c clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); val 1336 drivers/mfd/db8500-prcmu.c val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); val 1338 drivers/mfd/db8500-prcmu.c writel(val, prcmu_base + clk_mgt[clock].offset); val 1350 drivers/mfd/db8500-prcmu.c u32 val; val 1354 drivers/mfd/db8500-prcmu.c val = readl(PRCM_CGATING_BYPASS); val 1355 drivers/mfd/db8500-prcmu.c writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); val 1361 drivers/mfd/db8500-prcmu.c val = readl(PRCM_CGATING_BYPASS); val 1362 drivers/mfd/db8500-prcmu.c writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); val 1380 drivers/mfd/db8500-prcmu.c u32 val; val 1386 drivers/mfd/db8500-prcmu.c val = readl(PRCM_PLLDSI_ENABLE); val 1388 drivers/mfd/db8500-prcmu.c val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; val 1390 drivers/mfd/db8500-prcmu.c val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; val 1391 drivers/mfd/db8500-prcmu.c writel(val, PRCM_PLLDSI_ENABLE); val 1408 drivers/mfd/db8500-prcmu.c val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; val 1409 drivers/mfd/db8500-prcmu.c writel(val, PRCM_PLLDSI_ENABLE); val 1420 drivers/mfd/db8500-prcmu.c u32 val; val 1422 drivers/mfd/db8500-prcmu.c val = readl(PRCM_DSI_PLLOUT_SEL); val 1423 drivers/mfd/db8500-prcmu.c val &= ~dsiclk[n].divsel_mask; val 1424 drivers/mfd/db8500-prcmu.c val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << val 1426 drivers/mfd/db8500-prcmu.c writel(val, PRCM_DSI_PLLOUT_SEL); val 1432 drivers/mfd/db8500-prcmu.c u32 val; val 1434 drivers/mfd/db8500-prcmu.c val = readl(PRCM_DSITVCLK_DIV); val 1435 drivers/mfd/db8500-prcmu.c enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); val 1436 drivers/mfd/db8500-prcmu.c writel(val, PRCM_DSITVCLK_DIV); val 1474 drivers/mfd/db8500-prcmu.c u32 val; val 1478 drivers/mfd/db8500-prcmu.c val = readl(reg); val 1481 drivers/mfd/db8500-prcmu.c rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); val 1483 drivers/mfd/db8500-prcmu.c d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); val 1487 drivers/mfd/db8500-prcmu.c d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); val 1491 drivers/mfd/db8500-prcmu.c if (val & PRCM_PLL_FREQ_SELDIV2) val 1495 drivers/mfd/db8500-prcmu.c (val & PRCM_PLL_FREQ_DIV2EN) && val 1510 drivers/mfd/db8500-prcmu.c u32 val; val 1514 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clk_mgt[clock].offset); val 1516 drivers/mfd/db8500-prcmu.c if (val & PRCM_CLK_MGT_CLK38) { val 1517 drivers/mfd/db8500-prcmu.c if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) val 1522 drivers/mfd/db8500-prcmu.c val |= clk_mgt[clock].pllsw; val 1523 drivers/mfd/db8500-prcmu.c pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); val 1535 drivers/mfd/db8500-prcmu.c (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { val 1541 drivers/mfd/db8500-prcmu.c val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; val 1542 drivers/mfd/db8500-prcmu.c if (val) val 1543 drivers/mfd/db8500-prcmu.c return rate / val; val 1669 drivers/mfd/db8500-prcmu.c u32 val; val 1674 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clk_mgt[clock].offset); val 1675 drivers/mfd/db8500-prcmu.c src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), val 1678 drivers/mfd/db8500-prcmu.c if (val & PRCM_CLK_MGT_CLK38) { val 1825 drivers/mfd/db8500-prcmu.c u32 val; val 1836 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clk_mgt[clock].offset); val 1837 drivers/mfd/db8500-prcmu.c src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), val 1840 drivers/mfd/db8500-prcmu.c if (val & PRCM_CLK_MGT_CLK38) { val 1843 drivers/mfd/db8500-prcmu.c val |= PRCM_CLK_MGT_CLK38DIV; val 1845 drivers/mfd/db8500-prcmu.c val &= ~PRCM_CLK_MGT_CLK38DIV; val 1848 drivers/mfd/db8500-prcmu.c val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | val 1855 drivers/mfd/db8500-prcmu.c val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; val 1859 drivers/mfd/db8500-prcmu.c val |= min(div, (u32)31); val 1861 drivers/mfd/db8500-prcmu.c val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; val 1862 drivers/mfd/db8500-prcmu.c val |= min(div, (u32)31); val 1864 drivers/mfd/db8500-prcmu.c writel(val, prcmu_base + clk_mgt[clock].offset); val 1951 drivers/mfd/db8500-prcmu.c u32 val; val 1961 drivers/mfd/db8500-prcmu.c val = readl(PRCM_DSI_PLLOUT_SEL); val 1962 drivers/mfd/db8500-prcmu.c val &= ~dsiclk[n].divsel_mask; val 1963 drivers/mfd/db8500-prcmu.c val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); val 1964 drivers/mfd/db8500-prcmu.c writel(val, PRCM_DSI_PLLOUT_SEL); val 1969 drivers/mfd/db8500-prcmu.c u32 val; val 1973 drivers/mfd/db8500-prcmu.c val = readl(PRCM_DSITVCLK_DIV); val 1974 drivers/mfd/db8500-prcmu.c val &= ~dsiescclk[n].div_mask; val 1975 drivers/mfd/db8500-prcmu.c val |= (min(div, (u32)255) << dsiescclk[n].div_shift); val 1976 drivers/mfd/db8500-prcmu.c writel(val, PRCM_DSITVCLK_DIV); val 2060 drivers/mfd/db8500-prcmu.c static int config_hot_period(u16 val) val 2067 drivers/mfd/db8500-prcmu.c writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); val 2278 drivers/mfd/db8500-prcmu.c u32 val; val 2283 drivers/mfd/db8500-prcmu.c val = readl(PRCM_HOSTACCESS_REQ); val 2284 drivers/mfd/db8500-prcmu.c if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) val 2294 drivers/mfd/db8500-prcmu.c val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; val 2295 drivers/mfd/db8500-prcmu.c writel(val, PRCM_HOSTACCESS_REQ); val 2299 drivers/mfd/db8500-prcmu.c val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; val 2300 drivers/mfd/db8500-prcmu.c writel(val, PRCM_HOSTACCESS_REQ); val 2319 drivers/mfd/db8500-prcmu.c u32 val; val 2323 drivers/mfd/db8500-prcmu.c val = readl(PRCM_HOSTACCESS_REQ); val 2324 drivers/mfd/db8500-prcmu.c if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) val 2327 drivers/mfd/db8500-prcmu.c writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), val 2770 drivers/mfd/db8500-prcmu.c u32 val; val 2772 drivers/mfd/db8500-prcmu.c val = readl(PRCM_A9PL_FORCE_CLKEN); val 2773 drivers/mfd/db8500-prcmu.c val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | val 2775 drivers/mfd/db8500-prcmu.c writel(val, (PRCM_A9PL_FORCE_CLKEN)); val 60 drivers/mfd/exynos-lpass.c unsigned int val = 0; val 62 drivers/mfd/exynos-lpass.c regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); val 64 drivers/mfd/exynos-lpass.c val &= ~mask; val 65 drivers/mfd/exynos-lpass.c regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); val 69 drivers/mfd/exynos-lpass.c val |= mask; val 70 drivers/mfd/exynos-lpass.c regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); val 109 drivers/mfd/ezx-pcap.c int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val) val 122 drivers/mfd/ezx-pcap.c tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT | val 134 drivers/mfd/htc-i2cpld.c int val; val 152 drivers/mfd/htc-i2cpld.c val = i2c_smbus_read_byte_data(client, chip->cache_out); val 153 drivers/mfd/htc-i2cpld.c if (val < 0) { val 156 drivers/mfd/htc-i2cpld.c val); val 160 drivers/mfd/htc-i2cpld.c uval = (unsigned long)val; val 213 drivers/mfd/htc-i2cpld.c static void htcpld_chip_set(struct gpio_chip *chip, unsigned offset, int val) val 224 drivers/mfd/htc-i2cpld.c if (val) val 34 drivers/mfd/htc-pasic3.c void pasic3_write_register(struct device *dev, u32 reg, u8 val) val 42 drivers/mfd/htc-pasic3.c __raw_writeb(val, data); val 161 drivers/mfd/intel-lpss.c static void intel_lpss_ltr_set(struct device *dev, s32 val) val 173 drivers/mfd/intel-lpss.c if (val == PM_QOS_LATENCY_ANY || val < 0) { val 180 drivers/mfd/intel-lpss.c if (val > LPSS_PRIV_LTR_VALUE_MASK) val 181 drivers/mfd/intel-lpss.c ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5; val 183 drivers/mfd/intel-lpss.c ltr |= LPSS_PRIV_LTR_SCALE_1US | val; val 172 drivers/mfd/intel_msic.c int intel_msic_reg_read(unsigned short reg, u8 *val) val 174 drivers/mfd/intel_msic.c return intel_scu_ipc_ioread8(reg, val); val 188 drivers/mfd/intel_msic.c int intel_msic_reg_write(unsigned short reg, u8 val) val 190 drivers/mfd/intel_msic.c return intel_scu_ipc_iowrite8(reg, val); val 207 drivers/mfd/intel_msic.c int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask) val 209 drivers/mfd/intel_msic.c return intel_scu_ipc_update_register(reg, val, mask); val 273 drivers/mfd/intel_msic.c int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val) val 278 drivers/mfd/intel_msic.c *val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1)); val 271 drivers/mfd/intel_soc_pmic_bxtwc.c unsigned int *val) val 298 drivers/mfd/intel_soc_pmic_bxtwc.c *val = ipc_out[0]; val 304 drivers/mfd/intel_soc_pmic_bxtwc.c unsigned int val) val 323 drivers/mfd/intel_soc_pmic_bxtwc.c ipc_in[2] = val; val 357 drivers/mfd/intel_soc_pmic_bxtwc.c unsigned int val; val 360 drivers/mfd/intel_soc_pmic_bxtwc.c ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val); val 366 drivers/mfd/intel_soc_pmic_bxtwc.c return sprintf(buf, "0x%02x\n", val); val 373 drivers/mfd/intel_soc_pmic_bxtwc.c unsigned int val; val 376 drivers/mfd/intel_soc_pmic_bxtwc.c ret = kstrtouint(buf, 0, &val); val 380 drivers/mfd/intel_soc_pmic_bxtwc.c ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val); val 383 drivers/mfd/intel_soc_pmic_bxtwc.c val, bxtwc_reg_addr); val 390 drivers/mfd/intel_soc_pmic_bxtwc.c static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store); val 72 drivers/mfd/intel_soc_pmic_chtwc.c unsigned int *val) val 89 drivers/mfd/intel_soc_pmic_chtwc.c *val = ret; val 94 drivers/mfd/intel_soc_pmic_chtwc.c unsigned int val) val 105 drivers/mfd/intel_soc_pmic_chtwc.c ret = i2c_smbus_write_byte_data(client, reg & REG_OFFSET_MASK, val); val 75 drivers/mfd/intel_soc_pmic_mrfld.c unsigned int *val) val 84 drivers/mfd/intel_soc_pmic_mrfld.c *val = ipc_out; val 89 drivers/mfd/intel_soc_pmic_mrfld.c unsigned int val) val 91 drivers/mfd/intel_soc_pmic_mrfld.c u8 ipc_in = val; val 37 drivers/mfd/ipaq-micro.c u32 val; val 55 drivers/mfd/ipaq-micro.c val = readl(micro->base + UTCR3); val 56 drivers/mfd/ipaq-micro.c val |= UTCR3_TIE; val 57 drivers/mfd/ipaq-micro.c writel(val, micro->base + UTCR3); val 284 drivers/mfd/ipaq-micro.c u32 val; val 293 drivers/mfd/ipaq-micro.c val = readl(micro->base + UTCR3); val 294 drivers/mfd/ipaq-micro.c val &= ~UTCR3_TIE; val 295 drivers/mfd/ipaq-micro.c writel(val, micro->base + UTCR3); val 301 drivers/mfd/ipaq-micro.c u32 val; val 327 drivers/mfd/ipaq-micro.c val = readl(micro->base + UTCR3); val 328 drivers/mfd/ipaq-micro.c val &= ~UTCR3_TIE; val 329 drivers/mfd/ipaq-micro.c writel(val, micro->base + UTCR3); val 83 drivers/mfd/lm3533-core.c int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val) val 95 drivers/mfd/lm3533-core.c *val = tmp; val 97 drivers/mfd/lm3533-core.c dev_dbg(lm3533->dev, "read [%02x]: %02x\n", reg, *val); val 103 drivers/mfd/lm3533-core.c int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val) val 107 drivers/mfd/lm3533-core.c dev_dbg(lm3533->dev, "write [%02x]: %02x\n", reg, val); val 109 drivers/mfd/lm3533-core.c ret = regmap_write(lm3533->regmap, reg, val); val 119 drivers/mfd/lm3533-core.c int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask) val 123 drivers/mfd/lm3533-core.c dev_dbg(lm3533->dev, "update [%02x]: %02x/%02x\n", reg, val, mask); val 125 drivers/mfd/lm3533-core.c ret = regmap_update_bits(lm3533->regmap, reg, mask, val); val 169 drivers/mfd/lm3533-core.c u8 val; val 182 drivers/mfd/lm3533-core.c val = bl << shift; val 184 drivers/mfd/lm3533-core.c ret = lm3533_update(lm3533, LM3533_REG_OUTPUT_CONF1, val, mask); val 197 drivers/mfd/lm3533-core.c u8 val; val 217 drivers/mfd/lm3533-core.c val = led << shift; val 219 drivers/mfd/lm3533-core.c ret = lm3533_update(lm3533, reg, val, mask); val 263 drivers/mfd/lm3533-core.c u8 val; val 283 drivers/mfd/lm3533-core.c ret = lm3533_read(lm3533, reg, &val); val 287 drivers/mfd/lm3533-core.c val = (val & mask) >> shift; val 289 drivers/mfd/lm3533-core.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 299 drivers/mfd/lm3533-core.c u8 val; val 302 drivers/mfd/lm3533-core.c if (kstrtou8(buf, 0, &val)) val 306 drivers/mfd/lm3533-core.c ret = lm3533_set_hvled_config(lm3533, id, val); val 308 drivers/mfd/lm3533-core.c ret = lm3533_set_lvled_config(lm3533, id, val); val 75 drivers/mfd/lm3533-ctrlbank.c u8 val; val 81 drivers/mfd/lm3533-ctrlbank.c val = (imax - LM3533_MAX_CURRENT_MIN) / LM3533_MAX_CURRENT_STEP; val 84 drivers/mfd/lm3533-ctrlbank.c ret = lm3533_write(cb->lm3533, reg, val); val 93 drivers/mfd/lm3533-ctrlbank.c int lm3533_ctrlbank_set_##_name(struct lm3533_ctrlbank *cb, u8 val) \ val 98 drivers/mfd/lm3533-ctrlbank.c if (val > LM3533_##_NAME##_MAX) \ val 102 drivers/mfd/lm3533-ctrlbank.c ret = lm3533_write(cb->lm3533, reg, val); \ val 111 drivers/mfd/lm3533-ctrlbank.c int lm3533_ctrlbank_get_##_name(struct lm3533_ctrlbank *cb, u8 *val) \ val 117 drivers/mfd/lm3533-ctrlbank.c ret = lm3533_read(cb->lm3533, reg, val); \ val 236 drivers/mfd/lochnagar-i2c.c unsigned int val = 0; val 259 drivers/mfd/lochnagar-i2c.c LOCHNAGAR2_ANALOGUE_PATH_CTRL1, val, val 260 drivers/mfd/lochnagar-i2c.c (val & done), LOCHNAGAR_CONFIG_POLL_US, val 276 drivers/mfd/lochnagar-i2c.c unsigned int val; val 327 drivers/mfd/lochnagar-i2c.c ret = lochnagar_wait_for_boot(lochnagar->regmap, &val); val 333 drivers/mfd/lochnagar-i2c.c devid = val & LOCHNAGAR_DEVICE_ID_MASK; val 334 drivers/mfd/lochnagar-i2c.c rev = val & LOCHNAGAR_REV_ID_MASK; val 344 drivers/mfd/lochnagar-i2c.c ret = regmap_read(lochnagar->regmap, LOCHNAGAR_FIRMWARE_ID1, &val); val 350 drivers/mfd/lochnagar-i2c.c firmwareid = val; val 352 drivers/mfd/lochnagar-i2c.c ret = regmap_read(lochnagar->regmap, LOCHNAGAR_FIRMWARE_ID2, &val); val 358 drivers/mfd/lochnagar-i2c.c firmwareid |= (val << config->regmap->val_bits); val 76 drivers/mfd/lp3943.c unsigned int val; val 78 drivers/mfd/lp3943.c ret = regmap_read(lp3943->regmap, reg, &val); val 82 drivers/mfd/lp3943.c *read = (u8)val; val 87 drivers/mfd/lp8788-irq.c u8 addr, mask, val; val 91 drivers/mfd/lp8788-irq.c val = _irq_to_val(irq, irqd->enabled[irq]); val 93 drivers/mfd/lp8788-irq.c lp8788_update_bits(irqd->lp, addr, mask, val); val 125 drivers/mfd/lp8788.c unsigned int val; val 127 drivers/mfd/lp8788.c ret = regmap_read(lp->regmap, reg, &val); val 133 drivers/mfd/lp8788.c *data = (u8)val; val 205 drivers/mfd/madera-core.c unsigned int val = 0; val 216 drivers/mfd/madera-core.c regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_1, &val); val 217 drivers/mfd/madera-core.c while (!(val & MADERA_BOOT_DONE_STS1) && val 221 drivers/mfd/madera-core.c regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_1, &val); val 224 drivers/mfd/madera-core.c if (!(val & MADERA_BOOT_DONE_STS1)) { val 462 drivers/mfd/max77620.c unsigned int val; val 468 drivers/mfd/max77620.c ret = regmap_read(chip->rmap, i, &val); val 474 drivers/mfd/max77620.c i - MAX77620_REG_CID0, val); val 475 drivers/mfd/max77620.c cid_val[i - MAX77620_REG_CID0] = val; val 158 drivers/mfd/max77650.c unsigned int val; val 167 drivers/mfd/max77650.c rv = regmap_read(map, MAX77650_REG_CID, &val); val 173 drivers/mfd/max77650.c id = MAX77650_CID_BITS(val); val 297 drivers/mfd/max8997-irq.c u8 val; val 325 drivers/mfd/max8997-irq.c &val) val 105 drivers/mfd/max8997.c int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask) val 114 drivers/mfd/max8997.c u8 new_val = (val & mask) | (old_val & (~mask)); val 101 drivers/mfd/max8998.c int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask) val 110 drivers/mfd/max8998.c u8 new_val = (val & mask) | (old_val & (~mask)); val 271 drivers/mfd/max8998.c u8 val; val 273 drivers/mfd/max8998.c #define SAVE_ITEM(x) { .addr = (x), .val = 0x0, } val 321 drivers/mfd/max8998.c &max8998_dump[i].val); val 334 drivers/mfd/max8998.c max8998_dump[i].val); val 69 drivers/mfd/mc13xxx-core.c int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val) val 73 drivers/mfd/mc13xxx-core.c ret = regmap_read(mc13xxx->regmap, offset, val); val 74 drivers/mfd/mc13xxx-core.c dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val); val 80 drivers/mfd/mc13xxx-core.c int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val) val 82 drivers/mfd/mc13xxx-core.c dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val); val 84 drivers/mfd/mc13xxx-core.c if (val >= BIT(24)) val 87 drivers/mfd/mc13xxx-core.c return regmap_write(mc13xxx->regmap, offset, val); val 92 drivers/mfd/mc13xxx-core.c u32 mask, u32 val) val 94 drivers/mfd/mc13xxx-core.c BUG_ON(val & ~mask); val 96 drivers/mfd/mc13xxx-core.c offset, val, mask); val 98 drivers/mfd/mc13xxx-core.c return regmap_update_bits(mc13xxx->regmap, offset, mask, val); val 62 drivers/mfd/mc13xxx-spi.c void *val, size_t val_size) val 66 drivers/mfd/mc13xxx-spi.c unsigned char *p = val; val 96 drivers/mfd/mcp-core.c void mcp_reg_write(struct mcp *mcp, unsigned int reg, unsigned int val) val 101 drivers/mfd/mcp-core.c mcp->ops->reg_write(mcp, reg, val); val 117 drivers/mfd/mcp-core.c unsigned int val; val 120 drivers/mfd/mcp-core.c val = mcp->ops->reg_read(mcp, reg); val 123 drivers/mfd/mcp-core.c return val; val 75 drivers/mfd/mcp-sa11x0.c mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val) val 81 drivers/mfd/mcp-sa11x0.c writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m)); val 173 drivers/mfd/menelaus.c int val = i2c_smbus_write_byte_data(the_menelaus->client, reg, value); val 175 drivers/mfd/menelaus.c if (val < 0) { val 177 drivers/mfd/menelaus.c return val; val 185 drivers/mfd/menelaus.c int val = i2c_smbus_read_byte_data(the_menelaus->client, reg); val 187 drivers/mfd/menelaus.c if (val < 0) val 190 drivers/mfd/menelaus.c return val; val 287 drivers/mfd/menelaus.c int ret, val; val 297 drivers/mfd/menelaus.c val = ret; val 300 drivers/mfd/menelaus.c val |= MCT_CTRL1_S1_CMD_OD; val 302 drivers/mfd/menelaus.c val &= ~MCT_CTRL1_S1_CMD_OD; val 305 drivers/mfd/menelaus.c val |= MCT_CTRL1_S2_CMD_OD; val 307 drivers/mfd/menelaus.c val &= ~MCT_CTRL1_S2_CMD_OD; val 309 drivers/mfd/menelaus.c ret = menelaus_write_reg(MENELAUS_MCT_CTRL1, val); val 338 drivers/mfd/menelaus.c int ret, val; val 350 drivers/mfd/menelaus.c val = ret; val 353 drivers/mfd/menelaus.c val |= MCT_CTRL2_S1CD_BUFEN | MCT_CTRL2_S1CD_DBEN; val 355 drivers/mfd/menelaus.c val &= ~(MCT_CTRL2_S1CD_BUFEN | MCT_CTRL2_S1CD_DBEN); val 358 drivers/mfd/menelaus.c val |= MCT_CTRL2_S2CD_BUFEN | MCT_CTRL2_S2CD_BEN; val 360 drivers/mfd/menelaus.c val &= ~(MCT_CTRL2_S2CD_BUFEN | MCT_CTRL2_S2CD_BEN); val 362 drivers/mfd/menelaus.c ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, val); val 369 drivers/mfd/menelaus.c val = ret; val 372 drivers/mfd/menelaus.c val |= MCT_CTRL3_SLOT1_EN; val 374 drivers/mfd/menelaus.c val &= ~MCT_CTRL3_SLOT1_EN; val 379 drivers/mfd/menelaus.c val |= MCT_CTRL3_SLOT2_EN; val 381 drivers/mfd/menelaus.c val &= ~MCT_CTRL3_SLOT2_EN; val 390 drivers/mfd/menelaus.c val &= ~(MCT_CTRL3_S1_AUTO_EN | MCT_CTRL3_S2_AUTO_EN); val 391 drivers/mfd/menelaus.c ret = menelaus_write_reg(MENELAUS_MCT_CTRL3, val); val 446 drivers/mfd/menelaus.c u16 val; val 452 drivers/mfd/menelaus.c int val, ret; val 460 drivers/mfd/menelaus.c val = ret & ~(((1 << vtg->vtg_bits) - 1) << vtg->vtg_shift); val 461 drivers/mfd/menelaus.c val |= vtg_val << vtg->vtg_shift; val 465 drivers/mfd/menelaus.c vtg->name, mV, vtg->vtg_reg, val); val 467 drivers/mfd/menelaus.c ret = menelaus_write_reg(vtg->vtg_reg, val); val 487 drivers/mfd/menelaus.c return tbl->val; val 524 drivers/mfd/menelaus.c int fval, rval, val, ret; val 547 drivers/mfd/menelaus.c val = menelaus_read_reg(MENELAUS_VCORE_CTRL1); val 549 drivers/mfd/menelaus.c val |= (VCORE_CTRL1_HW_NSW | VCORE_CTRL1_BYP_COMP); val 550 drivers/mfd/menelaus.c ret = menelaus_write_reg(MENELAUS_VCORE_CTRL1, val); val 576 drivers/mfd/menelaus.c int val; val 581 drivers/mfd/menelaus.c val = menelaus_get_vtg_value(mV, vmem_values, ARRAY_SIZE(vmem_values)); val 582 drivers/mfd/menelaus.c if (val < 0) val 584 drivers/mfd/menelaus.c return menelaus_set_voltage(&vmem_vtg, mV, val, 0x02); val 605 drivers/mfd/menelaus.c int val; val 610 drivers/mfd/menelaus.c val = menelaus_get_vtg_value(mV, vio_values, ARRAY_SIZE(vio_values)); val 611 drivers/mfd/menelaus.c if (val < 0) val 613 drivers/mfd/menelaus.c return menelaus_set_voltage(&vio_vtg, mV, val, 0x02); val 647 drivers/mfd/menelaus.c int val; val 659 drivers/mfd/menelaus.c val = menelaus_get_vtg_value(mV, vdcdc_values, val 661 drivers/mfd/menelaus.c if (val < 0) val 663 drivers/mfd/menelaus.c return menelaus_set_voltage(vtg, mV, val, 0x03); val 683 drivers/mfd/menelaus.c int val; val 688 drivers/mfd/menelaus.c val = menelaus_get_vtg_value(mV, vmmc_values, ARRAY_SIZE(vmmc_values)); val 689 drivers/mfd/menelaus.c if (val < 0) val 691 drivers/mfd/menelaus.c return menelaus_set_voltage(&vmmc_vtg, mV, val, 0x02); val 713 drivers/mfd/menelaus.c int val; val 718 drivers/mfd/menelaus.c val = menelaus_get_vtg_value(mV, vaux_values, ARRAY_SIZE(vaux_values)); val 719 drivers/mfd/menelaus.c if (val < 0) val 721 drivers/mfd/menelaus.c return menelaus_set_voltage(&vaux_vtg, mV, val, 0x02); val 731 drivers/mfd/menelaus.c int menelaus_set_regulator_sleep(int enable, u32 val) val 737 drivers/mfd/menelaus.c ret = menelaus_write_reg(MENELAUS_SLEEP_CTRL2, val); val 741 drivers/mfd/menelaus.c dev_dbg(&c->dev, "regulator sleep configuration: %02x\n", val); val 28 drivers/mfd/menf21bmc.c int val, ret; val 30 drivers/mfd/menf21bmc.c val = i2c_smbus_read_byte_data(client, BMC_CMD_WDT_PROD_STAT); val 31 drivers/mfd/menf21bmc.c if (val < 0) val 32 drivers/mfd/menf21bmc.c return val; val 39 drivers/mfd/menf21bmc.c if (val == 0x00) { val 40 drivers/mfd/motorola-cpcap.c int err, val; val 45 drivers/mfd/motorola-cpcap.c err = regmap_read(regmap, reg, &val); val 49 drivers/mfd/motorola-cpcap.c return !!(val & mask); val 111 drivers/mfd/omap-usb-host.c static inline void usbhs_write(void __iomem *base, u32 reg, u32 val) val 113 drivers/mfd/omap-usb-host.c writel_relaxed(val, base + reg); val 113 drivers/mfd/omap-usb-tll.c static inline void usbtll_write(void __iomem *base, u32 reg, u32 val) val 115 drivers/mfd/omap-usb-tll.c writel_relaxed(val, base + reg); val 123 drivers/mfd/omap-usb-tll.c static inline void usbtll_writeb(void __iomem *base, u32 reg, u8 val) val 125 drivers/mfd/omap-usb-tll.c writeb_relaxed(val, base + reg); val 50 drivers/mfd/pcf50633-core.c unsigned int val; val 53 drivers/mfd/pcf50633-core.c ret = regmap_read(pcf->regmap, reg, &val); val 57 drivers/mfd/pcf50633-core.c return val; val 61 drivers/mfd/pcf50633-core.c int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val) val 63 drivers/mfd/pcf50633-core.c return regmap_write(pcf->regmap, reg, val); val 67 drivers/mfd/pcf50633-core.c int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val) val 69 drivers/mfd/pcf50633-core.c return regmap_update_bits(pcf->regmap, reg, mask, val); val 73 drivers/mfd/pcf50633-core.c int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val) val 75 drivers/mfd/pcf50633-core.c return regmap_update_bits(pcf->regmap, reg, val, 0); val 33 drivers/mfd/pcf50633-gpio.c int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) val 39 drivers/mfd/pcf50633-gpio.c return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val); val 45 drivers/mfd/pcf50633-gpio.c u8 reg, val; val 48 drivers/mfd/pcf50633-gpio.c val = pcf50633_reg_read(pcf, reg) & 0x07; val 50 drivers/mfd/pcf50633-gpio.c return val; val 56 drivers/mfd/pcf50633-gpio.c u8 val, reg; val 59 drivers/mfd/pcf50633-gpio.c val = !!invert << 3; val 61 drivers/mfd/pcf50633-gpio.c return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val); val 67 drivers/mfd/pcf50633-gpio.c u8 reg, val; val 70 drivers/mfd/pcf50633-gpio.c val = pcf50633_reg_read(pcf, reg); val 72 drivers/mfd/pcf50633-gpio.c return val & (1 << 3); val 79 drivers/mfd/pcf50633-gpio.c u8 reg, val, mask; val 84 drivers/mfd/pcf50633-gpio.c val = !!on << (gpio - PCF50633_GPIO1); val 87 drivers/mfd/pcf50633-gpio.c return pcf50633_reg_set_bit_mask(pcf, reg, mask, val); val 521 drivers/mfd/qcom-pm8xxx.c unsigned int val; val 541 drivers/mfd/qcom-pm8xxx.c rc = regmap_read(regmap, REG_HWREV, &val); val 546 drivers/mfd/qcom-pm8xxx.c pr_info("PMIC revision 1: %02X\n", val); val 547 drivers/mfd/qcom-pm8xxx.c rev = val; val 550 drivers/mfd/qcom-pm8xxx.c rc = regmap_read(regmap, REG_HWREV_2, &val); val 556 drivers/mfd/qcom-pm8xxx.c pr_info("PMIC revision 2: %02X\n", val); val 557 drivers/mfd/qcom-pm8xxx.c rev |= val << BITS_PER_BYTE; val 175 drivers/mfd/rc5t583-irq.c int val = 0; val 185 drivers/mfd/rc5t583-irq.c val |= 0x2; val 188 drivers/mfd/rc5t583-irq.c val |= 0x1; val 191 drivers/mfd/rc5t583-irq.c rc5t583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos); val 190 drivers/mfd/retu-mfd.c void *val, size_t val_size) val 202 drivers/mfd/retu-mfd.c *(u16 *)val = ret; val 209 drivers/mfd/retu-mfd.c u16 val; val 213 drivers/mfd/retu-mfd.c BUG_ON(count != sizeof(reg) + sizeof(val)); val 215 drivers/mfd/retu-mfd.c memcpy(&val, data + sizeof(reg), sizeof(val)); val 216 drivers/mfd/retu-mfd.c return i2c_smbus_write_word_data(i2c, reg, val); val 254 drivers/mfd/sec-core.c unsigned int val; val 257 drivers/mfd/sec-core.c if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val)) val 258 drivers/mfd/sec-core.c dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val); val 192 drivers/mfd/si476x-prop.c unsigned int val) val 194 drivers/mfd/si476x-prop.c return si476x_core_cmd_set_property(context, reg, val); val 198 drivers/mfd/si476x-prop.c unsigned *val) val 207 drivers/mfd/si476x-prop.c *val = err; val 116 drivers/mfd/sm501.c static unsigned long decode_div(unsigned long pll2, unsigned long val, val 120 drivers/mfd/sm501.c if (val & selbit) val 123 drivers/mfd/sm501.c return pll2 / div_tab[(val >> lshft) & mask]; val 926 drivers/mfd/sm501.c unsigned long val; val 933 drivers/mfd/sm501.c val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit; val 935 drivers/mfd/sm501.c val |= bit; val 936 drivers/mfd/sm501.c smc501_writel(val, regs); val 977 drivers/mfd/sm501.c unsigned long val; val 985 drivers/mfd/sm501.c val = smc501_readl(regs + SM501_GPIO_DATA_LOW); val 987 drivers/mfd/sm501.c val |= bit; val 989 drivers/mfd/sm501.c val &= ~bit; val 990 drivers/mfd/sm501.c smc501_writel(val, regs); val 996 drivers/mfd/sm501.c smc501_writel(val, regs + SM501_GPIO_DATA_LOW); val 122 drivers/mfd/sprd-sc27xx-spi.c void *val, size_t val_size) val 139 drivers/mfd/sprd-sc27xx-spi.c memcpy(val, rx_buf, val_size); val 80 drivers/mfd/ssbi.c static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg) val 82 drivers/mfd/ssbi.c writel(val, ssbi->base + reg); val 97 drivers/mfd/ssbi.c u32 val; val 100 drivers/mfd/ssbi.c val = ssbi_readl(ssbi, SSBI2_STATUS); val 101 drivers/mfd/ssbi.c if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0)) val 92 drivers/mfd/sta2x11-mfd.c u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val, val 113 drivers/mfd/sta2x11-mfd.c r |= val; val 24 drivers/mfd/stm32-lptimer.c u32 val; val 36 drivers/mfd/stm32-lptimer.c ret = regmap_read(ddata->regmap, STM32_LPTIM_CFGR, &val); val 45 drivers/mfd/stm32-lptimer.c ddata->has_encoder = !!(val & STM32_LPTIM_ENC); val 27 drivers/mfd/stmpe-i2c.c static int i2c_reg_write(struct stmpe *stmpe, u8 reg, u8 val) val 31 drivers/mfd/stmpe-i2c.c return i2c_smbus_write_byte_data(i2c, reg, val); val 28 drivers/mfd/stmpe-spi.c static int spi_reg_write(struct stmpe *stmpe, u8 reg, u8 val) val 31 drivers/mfd/stmpe-spi.c u16 cmd = (val << 8) | reg; val 70 drivers/mfd/stmpe.c static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) val 74 drivers/mfd/stmpe.c dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); val 76 drivers/mfd/stmpe.c ret = stmpe->ci->write_byte(stmpe, reg, val); val 83 drivers/mfd/stmpe.c static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) val 92 drivers/mfd/stmpe.c ret |= val; val 184 drivers/mfd/stmpe.c int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) val 189 drivers/mfd/stmpe.c ret = __stmpe_reg_write(stmpe, reg, val); val 203 drivers/mfd/stmpe.c int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) val 208 drivers/mfd/stmpe.c ret = __stmpe_set_bits(stmpe, reg, mask, val); val 1384 drivers/mfd/stmpe.c u32 val; val 1402 drivers/mfd/stmpe.c if (!of_property_read_u32(np, "st,sample-time", &val)) val 1403 drivers/mfd/stmpe.c stmpe->sample_time = val; val 1404 drivers/mfd/stmpe.c if (!of_property_read_u32(np, "st,mod-12b", &val)) val 1405 drivers/mfd/stmpe.c stmpe->mod_12b = val; val 1406 drivers/mfd/stmpe.c if (!of_property_read_u32(np, "st,ref-sel", &val)) val 1407 drivers/mfd/stmpe.c stmpe->ref_sel = val; val 1408 drivers/mfd/stmpe.c if (!of_property_read_u32(np, "st,adc-freq", &val)) val 1409 drivers/mfd/stmpe.c stmpe->adc_freq = val; val 93 drivers/mfd/stmpe.h int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val); val 48 drivers/mfd/stw481x.c unsigned int val; val 58 drivers/mfd/stw481x.c ret = regmap_read(stw481x->map, STW_PCTL_REG_HI, &val); val 61 drivers/mfd/stw481x.c vrfy = (val & 0x03) << 3; val 62 drivers/mfd/stw481x.c ret = regmap_read(stw481x->map, STW_PCTL_REG_LO, &val); val 65 drivers/mfd/stw481x.c vrfy |= ((val >> 5) & 0x07); val 68 drivers/mfd/stw481x.c return (val >> 1) & 0x0f; val 87 drivers/mfd/stw481x.c unsigned int val; val 89 drivers/mfd/stw481x.c ret = regmap_read(stw481x->map, STW_CONF1, &val); val 92 drivers/mfd/stw481x.c vaux_en = !!(val & STW_CONF1_PDN_VAUX); val 93 drivers/mfd/stw481x.c it_warn = !!(val & STW_CONF1_IT_WARN); val 96 drivers/mfd/stw481x.c (val & STW_CONF1_V_MONITORING) ? "OK" : "LOW"); val 98 drivers/mfd/stw481x.c (val & STW_CONF1_MMC_LS_STATUS) ? "high impedance" : "ON"); val 100 drivers/mfd/stw481x.c (val & STW_CONF1_PDN_VMMC) ? "ON" : "disabled"); val 132 drivers/mfd/stw481x.c ret = regmap_read(stw481x->map, STW_CONF2, &val); val 138 drivers/mfd/stw481x.c (val & STW_CONF2_MASK_TWARN) ? val 141 drivers/mfd/stw481x.c (val & STW_CONF2_VMMC_EXT) ? "internal" : "external"); val 143 drivers/mfd/stw481x.c (val & STW_CONF2_MASK_IT_WAKE_UP) ? "enabled" : "masked"); val 145 drivers/mfd/stw481x.c (val & STW_CONF2_GPO1) ? "low" : "high impedance"); val 147 drivers/mfd/stw481x.c (val & STW_CONF2_GPO2) ? "low" : "high impedance"); val 149 drivers/mfd/stw481x.c ret = regmap_read(stw481x->map, STW_VCORE_SLEEP, &val); val 152 drivers/mfd/stw481x.c vcore_slp = val & 0x0f; val 123 drivers/mfd/tc3589x.c int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val) val 134 drivers/mfd/tc3589x.c ret |= val; val 37 drivers/mfd/ti_am335x_tscadc.c void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val) val 42 drivers/mfd/ti_am335x_tscadc.c tscadc->reg_se_cache |= val; val 80 drivers/mfd/ti_am335x_tscadc.c void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val) val 85 drivers/mfd/ti_am335x_tscadc.c regmap_write(tscadc->regmap, REG_SE, val); val 101 drivers/mfd/ti_am335x_tscadc.c void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val) val 106 drivers/mfd/ti_am335x_tscadc.c tscadc->reg_se_cache &= ~val; val 131 drivers/mfd/ti_am335x_tscadc.c u32 val; val 147 drivers/mfd/ti_am335x_tscadc.c of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { val 149 drivers/mfd/ti_am335x_tscadc.c if (val > 7) { val 151 drivers/mfd/ti_am335x_tscadc.c val); val 199 drivers/mfd/tps65217.c unsigned int *val) val 201 drivers/mfd/tps65217.c return regmap_read(tps->regmap, reg, val); val 214 drivers/mfd/tps65217.c unsigned int val, unsigned int level) val 221 drivers/mfd/tps65217.c return regmap_write(tps->regmap, reg, val); val 229 drivers/mfd/tps65217.c return regmap_write(tps->regmap, reg, val); val 236 drivers/mfd/tps65217.c ret = regmap_write(tps->regmap, reg, val); val 243 drivers/mfd/tps65217.c return regmap_write(tps->regmap, reg, val); val 260 drivers/mfd/tps65217.c unsigned int mask, unsigned int val, unsigned int level) val 272 drivers/mfd/tps65217.c data |= val & mask; val 282 drivers/mfd/tps65217.c unsigned int mask, unsigned int val, unsigned int level) val 284 drivers/mfd/tps65217.c return tps65217_update_bits(tps, reg, mask, val, level); val 57 drivers/mfd/tps65218.c unsigned int val, unsigned int level) val 64 drivers/mfd/tps65218.c return regmap_write(tps->regmap, reg, val); val 72 drivers/mfd/tps65218.c return regmap_write(tps->regmap, reg, val); val 89 drivers/mfd/tps65218.c unsigned int mask, unsigned int val, unsigned int level) val 101 drivers/mfd/tps65218.c data |= val & mask; val 113 drivers/mfd/tps65218.c unsigned int mask, unsigned int val, unsigned int level) val 115 drivers/mfd/tps65218.c return tps65218_update_bits(tps, reg, mask, val, level); val 140 drivers/mfd/tps6586x.c int tps6586x_write(struct device *dev, int reg, uint8_t val) val 144 drivers/mfd/tps6586x.c return regmap_write(tps6586x->regmap, reg, val); val 148 drivers/mfd/tps6586x.c int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val) val 152 drivers/mfd/tps6586x.c return regmap_bulk_write(tps6586x->regmap, reg, val, len); val 156 drivers/mfd/tps6586x.c int tps6586x_read(struct device *dev, int reg, uint8_t *val) val 164 drivers/mfd/tps6586x.c *val = rval; val 169 drivers/mfd/tps6586x.c int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val) val 173 drivers/mfd/tps6586x.c return regmap_bulk_read(tps6586x->regmap, reg, val, len); val 193 drivers/mfd/tps6586x.c int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask) val 197 drivers/mfd/tps6586x.c return regmap_update_bits(tps6586x->regmap, reg, mask, val); val 58 drivers/mfd/tps65911-comparator.c u8 index = 0, val; val 71 drivers/mfd/tps65911-comparator.c val = index << 1; val 72 drivers/mfd/tps65911-comparator.c ret = tps65910_reg_write(tps65910, tps_comp.reg, val); val 80 drivers/mfd/tps65911-comparator.c unsigned int val; val 83 drivers/mfd/tps65911-comparator.c ret = tps65910_reg_read(tps65910, tps_comp.reg, &val); val 87 drivers/mfd/tps65911-comparator.c val >>= 1; val 88 drivers/mfd/tps65911-comparator.c return tps_comp.vsel_table[val]; val 47 drivers/mfd/twl4030-audio.c u8 val; val 49 drivers/mfd/twl4030-audio.c twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, val 53 drivers/mfd/twl4030-audio.c val |= audio->resource[id].mask; val 55 drivers/mfd/twl4030-audio.c val &= ~audio->resource[id].mask; val 58 drivers/mfd/twl4030-audio.c val, audio->resource[id].reg); val 60 drivers/mfd/twl4030-audio.c return val; val 66 drivers/mfd/twl4030-audio.c u8 val; val 68 drivers/mfd/twl4030-audio.c twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, val 71 drivers/mfd/twl4030-audio.c return val; val 81 drivers/mfd/twl4030-audio.c int val; val 92 drivers/mfd/twl4030-audio.c val = twl4030_audio_set_resource(id, 1); val 94 drivers/mfd/twl4030-audio.c val = twl4030_audio_get_resource(id); val 99 drivers/mfd/twl4030-audio.c return val; val 110 drivers/mfd/twl4030-audio.c int val; val 129 drivers/mfd/twl4030-audio.c val = twl4030_audio_set_resource(id, 0); val 131 drivers/mfd/twl4030-audio.c val = twl4030_audio_get_resource(id); val 135 drivers/mfd/twl4030-audio.c return val; val 185 drivers/mfd/twl4030-audio.c u8 val; val 203 drivers/mfd/twl4030-audio.c val = TWL4030_APLL_INFREQ_19200KHZ; val 206 drivers/mfd/twl4030-audio.c val = TWL4030_APLL_INFREQ_26000KHZ; val 209 drivers/mfd/twl4030-audio.c val = TWL4030_APLL_INFREQ_38400KHZ; val 215 drivers/mfd/twl4030-audio.c twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, val, TWL4030_REG_APLL_CTL); val 624 drivers/mfd/twl4030-power.c u8 val; val 639 drivers/mfd/twl4030-power.c &val, regs[i]); val 642 drivers/mfd/twl4030-power.c val = (~bitmask & val) | (bitmask & bitvalues); val 644 drivers/mfd/twl4030-power.c val, regs[i]); val 889 drivers/mfd/twl4030-power.c u8 val; val 928 drivers/mfd/twl4030-power.c err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val, val 932 drivers/mfd/twl4030-power.c } else if (!(val & SEQ_OFFSYNC)) { val 933 drivers/mfd/twl4030-power.c val |= SEQ_OFFSYNC; val 934 drivers/mfd/twl4030-power.c err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val, val 102 drivers/mfd/twl6040.c unsigned int val; val 104 drivers/mfd/twl6040.c ret = regmap_read(twl6040->regmap, reg, &val); val 108 drivers/mfd/twl6040.c return val; val 112 drivers/mfd/twl6040.c int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val) val 116 drivers/mfd/twl6040.c ret = regmap_write(twl6040->regmap, reg, val); val 28 drivers/mfd/ucb1400_core.c unsigned int val; val 37 drivers/mfd/ucb1400_core.c while (!((val = ucb1400_reg_read(ac97, UCB_ADC_DATA)) val 41 drivers/mfd/ucb1400_core.c return val & UCB_ADC_DAT_MASK; val 25 drivers/mfd/ucb1x00-assabet.c int val; \ val 27 drivers/mfd/ucb1x00-assabet.c val = ucb1x00_adc_read(ucb, input, UCB_NOSYNC); \ val 29 drivers/mfd/ucb1x00-assabet.c return sprintf(buf, "%d\n", val); \ val 127 drivers/mfd/ucb1x00-core.c unsigned val; val 130 drivers/mfd/ucb1x00-core.c val = ucb1x00_reg_read(ucb, UCB_IO_DATA); val 133 drivers/mfd/ucb1x00-core.c return !!(val & (1 << offset)); val 239 drivers/mfd/ucb1x00-core.c unsigned int val; val 248 drivers/mfd/ucb1x00-core.c val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); val 249 drivers/mfd/ucb1x00-core.c if (val & UCB_ADC_DAT_VAL) val 256 drivers/mfd/ucb1x00-core.c return UCB_ADC_DAT(val); val 191 drivers/mfd/ucb1x00-ts.c unsigned int val = ucb1x00_reg_read(ts->ucb, UCB_TS_CR); val 194 drivers/mfd/ucb1x00-ts.c return (!(val & (UCB_TS_CR_TSPX_LOW))); val 196 drivers/mfd/ucb1x00-ts.c return (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW)); val 27 drivers/mfd/wm831x-auxadc.c int val; val 44 drivers/mfd/wm831x-auxadc.c req->val = -ETIMEDOUT; val 98 drivers/mfd/wm831x-auxadc.c ret = req->val; val 112 drivers/mfd/wm831x-auxadc.c int ret, input, val; val 127 drivers/mfd/wm831x-auxadc.c val = ret & WM831X_AUX_DATA_MASK; val 143 drivers/mfd/wm831x-auxadc.c req->val = val; val 517 drivers/mfd/wm831x-core.c unsigned int val; val 520 drivers/mfd/wm831x-core.c ret = regmap_read(wm831x->regmap, reg, &val); val 525 drivers/mfd/wm831x-core.c return val; val 575 drivers/mfd/wm831x-core.c unsigned short val) val 581 drivers/mfd/wm831x-core.c ret = wm831x_write(wm831x, reg, 2, &val); val 598 drivers/mfd/wm831x-core.c unsigned short mask, unsigned short val) val 605 drivers/mfd/wm831x-core.c ret = regmap_update_bits(wm831x->regmap, reg, mask, val); val 27 drivers/mfd/wm831x-otp.c int i, val; val 30 drivers/mfd/wm831x-otp.c val = wm831x_reg_read(wm831x, WM831X_UNIQUE_ID_1 + i); val 31 drivers/mfd/wm831x-otp.c if (val < 0) val 32 drivers/mfd/wm831x-otp.c return val; val 34 drivers/mfd/wm831x-otp.c id[i * 2] = (val >> 8) & 0xff; val 35 drivers/mfd/wm831x-otp.c id[(i * 2) + 1] = val & 0xff; val 88 drivers/mfd/wm8350-core.c int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val) val 92 drivers/mfd/wm8350-core.c ret = regmap_write(wm8350->regmap, reg, val); val 14 drivers/misc/ad525x_dpot-i2c.c static int write_d8(void *client, u8 val) val 16 drivers/misc/ad525x_dpot-i2c.c return i2c_smbus_write_byte(client, val); val 19 drivers/misc/ad525x_dpot-i2c.c static int write_r8d8(void *client, u8 reg, u8 val) val 21 drivers/misc/ad525x_dpot-i2c.c return i2c_smbus_write_byte_data(client, reg, val); val 24 drivers/misc/ad525x_dpot-i2c.c static int write_r8d16(void *client, u8 reg, u16 val) val 26 drivers/misc/ad525x_dpot-i2c.c return i2c_smbus_write_word_data(client, reg, val); val 14 drivers/misc/ad525x_dpot-spi.c static int write8(void *client, u8 val) val 16 drivers/misc/ad525x_dpot-spi.c u8 data = val; val 21 drivers/misc/ad525x_dpot-spi.c static int write16(void *client, u8 reg, u8 val) val 23 drivers/misc/ad525x_dpot-spi.c u8 data[2] = {reg, val}; val 28 drivers/misc/ad525x_dpot-spi.c static int write24(void *client, u8 reg, u16 val) val 30 drivers/misc/ad525x_dpot-spi.c u8 data[3] = {reg, val >> 8, val}; val 111 drivers/misc/ad525x_dpot.c static inline int dpot_write_d8(struct dpot_data *dpot, u8 val) val 113 drivers/misc/ad525x_dpot.c return dpot->bdata.bops->write_d8(dpot->bdata.client, val); val 116 drivers/misc/ad525x_dpot.c static inline int dpot_write_r8d8(struct dpot_data *dpot, u8 reg, u16 val) val 118 drivers/misc/ad525x_dpot.c return dpot->bdata.bops->write_r8d8(dpot->bdata.client, reg, val); val 121 drivers/misc/ad525x_dpot.c static inline int dpot_write_r8d16(struct dpot_data *dpot, u8 reg, u16 val) val 123 drivers/misc/ad525x_dpot.c return dpot->bdata.bops->write_r8d16(dpot->bdata.client, reg, val); val 238 drivers/misc/ad525x_dpot.c unsigned int val = 0; val 246 drivers/misc/ad525x_dpot.c val = ((reg & DPOT_RDAC_MASK) << val 249 drivers/misc/ad525x_dpot.c return dpot_write_d8(dpot, val); val 251 drivers/misc/ad525x_dpot.c val = ((reg & DPOT_RDAC_MASK) << val 254 drivers/misc/ad525x_dpot.c return dpot_write_r8d8(dpot, val >> 8, val 255 drivers/misc/ad525x_dpot.c val & 0xFF); val 285 drivers/misc/ad525x_dpot.c val = DPOT_SPI_RDAC | (reg & DPOT_RDAC_MASK); val 288 drivers/misc/ad525x_dpot.c val = DPOT_SPI_EEPROM | (reg & DPOT_RDAC_MASK); val 292 drivers/misc/ad525x_dpot.c val = DPOT_SPI_DEC_ALL_6DB; val 295 drivers/misc/ad525x_dpot.c val = DPOT_SPI_INC_ALL_6DB; val 298 drivers/misc/ad525x_dpot.c val = DPOT_SPI_DEC_ALL; val 301 drivers/misc/ad525x_dpot.c val = DPOT_SPI_INC_ALL; val 318 drivers/misc/ad525x_dpot.c return dpot_write_r8d8(dpot, val, value); val 320 drivers/misc/ad525x_dpot.c return dpot_write_r8d16(dpot, val, value); val 200 drivers/misc/ad525x_dpot.h int (*write_d8)(void *client, u8 val); val 201 drivers/misc/ad525x_dpot.h int (*write_r8d8)(void *client, u8 reg, u8 val); val 202 drivers/misc/ad525x_dpot.h int (*write_r8d16)(void *client, u8 reg, u16 val); val 36 drivers/misc/apds9802als.c int val; val 38 drivers/misc/apds9802als.c val = i2c_smbus_read_byte_data(client, 0x81); val 39 drivers/misc/apds9802als.c if (val < 0) val 40 drivers/misc/apds9802als.c return val; val 41 drivers/misc/apds9802als.c if (val & 1) val 114 drivers/misc/apds9802als.c unsigned long val; val 116 drivers/misc/apds9802als.c ret_val = kstrtoul(buf, 10, &val); val 120 drivers/misc/apds9802als.c if (val < 4096) val 121 drivers/misc/apds9802als.c val = 1; val 122 drivers/misc/apds9802als.c else if (val < 65536) val 123 drivers/misc/apds9802als.c val = 2; val 140 drivers/misc/apds9802als.c if (val == 1) /* Setting detection range up to 4k LUX */ val 50 drivers/misc/cardreader/alcor_pci.c void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr) val 52 drivers/misc/cardreader/alcor_pci.c writeb(val, priv->iobase + addr); val 56 drivers/misc/cardreader/alcor_pci.c void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr) val 58 drivers/misc/cardreader/alcor_pci.c writew(val, priv->iobase + addr); val 62 drivers/misc/cardreader/alcor_pci.c void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr) val 64 drivers/misc/cardreader/alcor_pci.c writel(val, priv->iobase + addr); val 68 drivers/misc/cardreader/alcor_pci.c void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr) val 70 drivers/misc/cardreader/alcor_pci.c iowrite32be(val, priv->iobase + addr); val 20 drivers/misc/cardreader/rtl8411.c u8 val; val 22 drivers/misc/cardreader/rtl8411.c rtsx_pci_read_register(pcr, SYS_VER, &val); val 23 drivers/misc/cardreader/rtl8411.c return val & 0x0F; val 28 drivers/misc/cardreader/rtl8411.c u8 val = 0; val 30 drivers/misc/cardreader/rtl8411.c rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val); val 32 drivers/misc/cardreader/rtl8411.c if (val & 0x2) val 185 drivers/misc/cardreader/rtl8411.c u8 mask, val; val 194 drivers/misc/cardreader/rtl8411.c val = (BPP_ASIC_3V3 << bpp_tuned18_shift) | BPP_PAD_3V3; val 200 drivers/misc/cardreader/rtl8411.c val = (bpp_asic_1v8 << bpp_tuned18_shift) | BPP_PAD_1V8; val 205 drivers/misc/cardreader/rtl8411.c return rtsx_pci_write_register(pcr, LDO_CTL, mask, val); val 18 drivers/misc/cardreader/rts5209.c u8 val; val 20 drivers/misc/cardreader/rts5209.c val = rtsx_pci_readb(pcr, 0x1C); val 21 drivers/misc/cardreader/rts5209.c return val & 0x0F; val 19 drivers/misc/cardreader/rts5227.c u8 val; val 21 drivers/misc/cardreader/rts5227.c rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); val 22 drivers/misc/cardreader/rts5227.c return val & 0x0F; val 18 drivers/misc/cardreader/rts5229.c u8 val; val 20 drivers/misc/cardreader/rts5229.c rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); val 21 drivers/misc/cardreader/rts5229.c return val & 0x0F; val 18 drivers/misc/cardreader/rts5249.c u8 val; val 20 drivers/misc/cardreader/rts5249.c rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); val 21 drivers/misc/cardreader/rts5249.c return val & 0x0F; val 119 drivers/misc/cardreader/rts5249.c u16 val; val 121 drivers/misc/cardreader/rts5249.c pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); val 122 drivers/misc/cardreader/rts5249.c if (val & PCI_EXP_DEVCTL2_LTR_EN) { val 353 drivers/misc/cardreader/rts5249.c u8 val = 0; val 360 drivers/misc/cardreader/rts5249.c val = pcr->aspm_en; val 363 drivers/misc/cardreader/rts5249.c ASPM_MASK_NEG, val); val 368 drivers/misc/cardreader/rts5249.c val = FORCE_ASPM_CTL0; val 369 drivers/misc/cardreader/rts5249.c rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); val 481 drivers/misc/cardreader/rts5249.c static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) val 485 drivers/misc/cardreader/rts5249.c return __rtsx_pci_write_phy_register(pcr, addr, val); val 488 drivers/misc/cardreader/rts5249.c static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) val 492 drivers/misc/cardreader/rts5249.c return __rtsx_pci_read_phy_register(pcr, addr, val); val 573 drivers/misc/cardreader/rts5249.c u8 val = 0; val 581 drivers/misc/cardreader/rts5249.c val = option->ltr_l1off_snooze_sspwrgate; val 585 drivers/misc/cardreader/rts5249.c val = option->ltr_l1off_sspwrgate; val 592 drivers/misc/cardreader/rts5249.c val &= ~L1OFF_MBIAS2_EN_5250; val 594 drivers/misc/cardreader/rts5249.c val |= L1OFF_MBIAS2_EN_5250; val 597 drivers/misc/cardreader/rts5249.c rtsx_set_l1off_sub(pcr, val); val 21 drivers/misc/cardreader/rts5260.c u8 val; val 23 drivers/misc/cardreader/rts5260.c rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); val 24 drivers/misc/cardreader/rts5260.c return val & IC_VERSION_MASK; val 302 drivers/misc/cardreader/rts5260.c u8 mask, val; val 314 drivers/misc/cardreader/rts5260.c val = pcr->hw_param.ocp_glitch; val 315 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); val 332 drivers/misc/cardreader/rts5260.c u8 val = 0; val 334 drivers/misc/cardreader/rts5260.c val = SD_OCP_INT_EN | SD_DETECT_EN; val 335 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); val 349 drivers/misc/cardreader/rts5260.c static int rts5260_get_ocpstat(struct rtsx_pcr *pcr, u8 *val) val 351 drivers/misc/cardreader/rts5260.c return rtsx_pci_read_register(pcr, REG_OCPSTAT, val); val 354 drivers/misc/cardreader/rts5260.c static int rts5260_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val) val 356 drivers/misc/cardreader/rts5260.c return rtsx_pci_read_register(pcr, REG_DV3318_OCPSTAT, val); val 362 drivers/misc/cardreader/rts5260.c u8 val = 0; val 365 drivers/misc/cardreader/rts5260.c val = SD_OCP_INT_CLR | SD_OC_CLR; val 367 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); val 520 drivers/misc/cardreader/rts5260.c u16 val; val 522 drivers/misc/cardreader/rts5260.c pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); val 523 drivers/misc/cardreader/rts5260.c if (val & PCI_EXP_DEVCTL2_LTR_EN) { val 577 drivers/misc/cardreader/rts5260.c u8 val = 0; val 584 drivers/misc/cardreader/rts5260.c val = pcr->aspm_en; val 586 drivers/misc/cardreader/rts5260.c ASPM_MASK_NEG, val); val 591 drivers/misc/cardreader/rts5260.c val = FORCE_ASPM_CTL0; val 592 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); val 604 drivers/misc/cardreader/rts5260.c u8 val = 0; val 612 drivers/misc/cardreader/rts5260.c val = option->ltr_l1off_snooze_sspwrgate; val 616 drivers/misc/cardreader/rts5260.c val = option->ltr_l1off_sspwrgate; val 623 drivers/misc/cardreader/rts5260.c val &= ~L1OFF_MBIAS2_EN_5250; val 625 drivers/misc/cardreader/rts5260.c val |= L1OFF_MBIAS2_EN_5250; val 628 drivers/misc/cardreader/rts5260.c rtsx_set_l1off_sub(pcr, val); val 109 drivers/misc/cardreader/rtsx_pcr.c u8 val = 0; val 112 drivers/misc/cardreader/rtsx_pcr.c val = pcr->aspm_en; val 113 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); val 127 drivers/misc/cardreader/rtsx_pcr.c int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val) val 129 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val); val 184 drivers/misc/cardreader/rtsx_pcr.c u32 val = HAIMR_WRITE_START; val 186 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)(addr & 0x3FFF) << 16; val 187 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)mask << 8; val 188 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)data; val 190 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_writel(pcr, RTSX_HAIMR, val); val 193 drivers/misc/cardreader/rtsx_pcr.c val = rtsx_pci_readl(pcr, RTSX_HAIMR); val 194 drivers/misc/cardreader/rtsx_pcr.c if ((val & HAIMR_TRANS_END) == 0) { val 195 drivers/misc/cardreader/rtsx_pcr.c if (data != (u8)val) val 207 drivers/misc/cardreader/rtsx_pcr.c u32 val = HAIMR_READ_START; val 210 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)(addr & 0x3FFF) << 16; val 211 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_writel(pcr, RTSX_HAIMR, val); val 214 drivers/misc/cardreader/rtsx_pcr.c val = rtsx_pci_readl(pcr, RTSX_HAIMR); val 215 drivers/misc/cardreader/rtsx_pcr.c if ((val & HAIMR_TRANS_END) == 0) val 223 drivers/misc/cardreader/rtsx_pcr.c *data = (u8)(val & 0xFF); val 229 drivers/misc/cardreader/rtsx_pcr.c int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) val 236 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val); val 237 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8)); val 262 drivers/misc/cardreader/rtsx_pcr.c int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) val 265 drivers/misc/cardreader/rtsx_pcr.c return pcr->ops->write_phy(pcr, addr, val); val 267 drivers/misc/cardreader/rtsx_pcr.c return __rtsx_pci_write_phy_register(pcr, addr, val); val 271 drivers/misc/cardreader/rtsx_pcr.c int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) val 312 drivers/misc/cardreader/rtsx_pcr.c if (val) val 313 drivers/misc/cardreader/rtsx_pcr.c *val = data; val 318 drivers/misc/cardreader/rtsx_pcr.c int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) val 321 drivers/misc/cardreader/rtsx_pcr.c return pcr->ops->read_phy(pcr, addr, val); val 323 drivers/misc/cardreader/rtsx_pcr.c return __rtsx_pci_read_phy_register(pcr, addr, val); val 344 drivers/misc/cardreader/rtsx_pcr.c u32 val = 0; val 347 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)(cmd_type & 0x03) << 30; val 348 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)(reg_addr & 0x3FFF) << 16; val 349 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)mask << 8; val 350 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)data; val 355 drivers/misc/cardreader/rtsx_pcr.c put_unaligned_le32(val, ptr); val 365 drivers/misc/cardreader/rtsx_pcr.c u32 val = 1 << 31; val 369 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; val 371 drivers/misc/cardreader/rtsx_pcr.c val |= 0x40000000; val 372 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); val 379 drivers/misc/cardreader/rtsx_pcr.c u32 val = 1 << 31; val 393 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; val 395 drivers/misc/cardreader/rtsx_pcr.c val |= 0x40000000; val 396 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); val 437 drivers/misc/cardreader/rtsx_pcr.c u64 val; val 444 drivers/misc/cardreader/rtsx_pcr.c val = ((u64)addr << 32) | ((u64)len << 12) | option; val 446 drivers/misc/cardreader/rtsx_pcr.c put_unaligned_le64(val, ptr); val 503 drivers/misc/cardreader/rtsx_pcr.c u32 val; val 512 drivers/misc/cardreader/rtsx_pcr.c val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; val 526 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_writel(pcr, RTSX_HDBCTLR, val); val 885 drivers/misc/cardreader/rtsx_pcr.c unsigned int val; val 887 drivers/misc/cardreader/rtsx_pcr.c val = rtsx_pci_readl(pcr, RTSX_BIPR); val 889 drivers/misc/cardreader/rtsx_pcr.c val = pcr->ops->cd_deglitch(pcr); val 891 drivers/misc/cardreader/rtsx_pcr.c return val; val 1150 drivers/misc/cardreader/rtsx_pcr.c u8 val = SD_OCP_INT_EN | SD_DETECT_EN; val 1156 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); val 1182 drivers/misc/cardreader/rtsx_pcr.c u8 val = option->sd_800mA_ocp_thd; val 1188 drivers/misc/cardreader/rtsx_pcr.c SD_OCP_THD_MASK, val); val 1200 drivers/misc/cardreader/rtsx_pcr.c int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val) val 1203 drivers/misc/cardreader/rtsx_pcr.c return pcr->ops->get_ocpstat(pcr, val); val 1205 drivers/misc/cardreader/rtsx_pcr.c return rtsx_pci_read_register(pcr, REG_OCPSTAT, val); val 1214 drivers/misc/cardreader/rtsx_pcr.c u8 val = SD_OCP_INT_CLR | SD_OC_CLR; val 1216 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); val 42 drivers/misc/cardreader/rtsx_pcr.h int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val); val 43 drivers/misc/cardreader/rtsx_pcr.h int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val); val 97 drivers/misc/cardreader/rtsx_pcr.h int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val); val 101 drivers/misc/cardreader/rtsx_pcr.h int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val); val 319 drivers/misc/cardreader/rtsx_usb.c static int rtsx_usb_write_phy_register(struct rtsx_ucr *ucr, u8 addr, u8 val) val 322 drivers/misc/cardreader/rtsx_usb.c val, addr); val 326 drivers/misc/cardreader/rtsx_usb.c rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, HS_VSTAIN, 0xFF, val); val 491 drivers/misc/cardreader/rtsx_usb.c u16 val; val 497 drivers/misc/cardreader/rtsx_usb.c ret = rtsx_usb_get_card_status(ucr, &val); val 505 drivers/misc/cardreader/rtsx_usb.c if (val & cd_mask[card]) val 515 drivers/misc/cardreader/rtsx_usb.c u8 val; val 557 drivers/misc/cardreader/rtsx_usb.c rtsx_usb_read_register(ucr, CFG_MODE, &val); val 558 drivers/misc/cardreader/rtsx_usb.c if ((val & XTAL_FREE) || ((val & CLK_MODE_MASK) == CLK_MODE_NON_XTAL)) { val 570 drivers/misc/cardreader/rtsx_usb.c u8 val; val 586 drivers/misc/cardreader/rtsx_usb.c ret = rtsx_usb_read_register(ucr, HW_VERSION, &val); val 590 drivers/misc/cardreader/rtsx_usb.c ucr->ic_version = val & HW_VER_MASK; val 593 drivers/misc/cardreader/rtsx_usb.c ret = rtsx_usb_read_register(ucr, CARD_SHARE_MODE, &val); val 597 drivers/misc/cardreader/rtsx_usb.c if (val & CARD_SHARE_LQFP_SEL) { val 606 drivers/misc/cardreader/rtsx_usb.c rtsx_usb_read_register(ucr, CFG_MODE_1, &val); val 607 drivers/misc/cardreader/rtsx_usb.c if (val & RTS5179) { val 693 drivers/misc/cardreader/rtsx_usb.c u16 val = 0; val 700 drivers/misc/cardreader/rtsx_usb.c rtsx_usb_get_card_status(ucr, &val); val 704 drivers/misc/cardreader/rtsx_usb.c if (val & (SD_CD | MS_CD)) val 33 drivers/misc/cb710/core.c u32 val; val 38 drivers/misc/cb710/core.c pci_read_config_dword(pdev, 0x48, &val); val 39 drivers/misc/cb710/core.c if (val & 0x80000000) val 204 drivers/misc/cb710/core.c u32 val; val 213 drivers/misc/cb710/core.c pci_read_config_dword(pdev, 0x48, &val); val 214 drivers/misc/cb710/core.c if (!(val & 0x80000000)) { val 215 drivers/misc/cb710/core.c pci_write_config_dword(pdev, 0x48, val|0x71000000); val 216 drivers/misc/cb710/core.c pci_read_config_dword(pdev, 0x48, &val); val 219 drivers/misc/cb710/core.c dev_dbg(&pdev->dev, "PCI config[0x48] = 0x%08X\n", val); val 220 drivers/misc/cb710/core.c if (!(val & 0x70000000)) val 222 drivers/misc/cb710/core.c val = (val >> 28) & 7; val 223 drivers/misc/cb710/core.c if (val & CB710_SLOT_MMC) val 225 drivers/misc/cb710/core.c if (val & CB710_SLOT_MS) val 227 drivers/misc/cb710/core.c if (val & CB710_SLOT_SM) val 262 drivers/misc/cb710/core.c if (val & CB710_SLOT_MMC) { /* MMC/SD slot */ val 269 drivers/misc/cb710/core.c if (val & CB710_SLOT_MS) { /* MemoryStick slot */ val 276 drivers/misc/cb710/core.c if (val & CB710_SLOT_SM) { /* SmartMedia slot */ val 214 drivers/misc/cs5535-mfgpt.c uint16_t val; val 217 drivers/misc/cs5535-mfgpt.c val = cs5535_mfgpt_read(timer, MFGPT_REG_SETUP); val 218 drivers/misc/cs5535-mfgpt.c if (!(val & MFGPT_SETUP_SETUP)) { val 251 drivers/misc/cs5535-mfgpt.c uint32_t val, dummy; val 254 drivers/misc/cs5535-mfgpt.c val = 0xFF; dummy = 0; val 255 drivers/misc/cs5535-mfgpt.c wrmsr(MSR_MFGPT_SETUP, val, dummy); val 292 drivers/misc/cs5535-mfgpt.c uint16_t val; val 305 drivers/misc/cs5535-mfgpt.c val = cs5535_mfgpt_read(&timer, MFGPT_REG_SETUP); val 306 drivers/misc/cs5535-mfgpt.c if (!(val & MFGPT_SETUP_SETUP) || mfgpt_reset_timers == 2) { val 780 drivers/misc/cxl/cxl.h static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val) val 783 drivers/misc/cxl/cxl.h out_be64(_cxl_p1_addr(cxl, reg), val); val 800 drivers/misc/cxl/cxl.h static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val) val 803 drivers/misc/cxl/cxl.h out_be64(_cxl_p1n_addr(afu, reg), val); val 819 drivers/misc/cxl/cxl.h static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val) val 822 drivers/misc/cxl/cxl.h out_be64(_cxl_p2n_addr(afu, reg), val); val 1092 drivers/misc/cxl/cxl.h int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val); val 1093 drivers/misc/cxl/cxl.h int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val); val 1094 drivers/misc/cxl/cxl.h int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val); val 1095 drivers/misc/cxl/cxl.h int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val); val 1096 drivers/misc/cxl/cxl.h int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val); val 1097 drivers/misc/cxl/cxl.h int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val); val 1098 drivers/misc/cxl/cxl.h int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val); val 15 drivers/misc/cxl/debugfs.c static int debugfs_io_u64_get(void *data, u64 *val) val 17 drivers/misc/cxl/debugfs.c *val = in_be64((u64 __iomem *)data); val 21 drivers/misc/cxl/debugfs.c static int debugfs_io_u64_set(void *data, u64 val) val 23 drivers/misc/cxl/debugfs.c out_be64((u64 __iomem *)data, val); val 71 drivers/misc/cxl/flash.c u32 *val; val 93 drivers/misc/cxl/flash.c val = (u32 *)new_prop->value; val 96 drivers/misc/cxl/flash.c dn, name, vd, be32_to_cpu(*val)); val 412 drivers/misc/cxl/guest.c u64 offset, u64 *val) val 436 drivers/misc/cxl/guest.c *val = c; val 439 drivers/misc/cxl/guest.c *val = in_le16((u16 *)cr); val 442 drivers/misc/cxl/guest.c *val = in_le32((unsigned *)cr); val 445 drivers/misc/cxl/guest.c *val = in_le64((u64 *)cr); val 459 drivers/misc/cxl/guest.c u64 val; val 461 drivers/misc/cxl/guest.c rc = _guest_afu_cr_readXX(4, afu, cr_idx, offset, &val); val 463 drivers/misc/cxl/guest.c *out = (u32) val; val 471 drivers/misc/cxl/guest.c u64 val; val 473 drivers/misc/cxl/guest.c rc = _guest_afu_cr_readXX(2, afu, cr_idx, offset, &val); val 475 drivers/misc/cxl/guest.c *out = (u16) val; val 483 drivers/misc/cxl/guest.c u64 val; val 485 drivers/misc/cxl/guest.c rc = _guest_afu_cr_readXX(1, afu, cr_idx, offset, &val); val 487 drivers/misc/cxl/guest.c *out = (u8) val; val 300 drivers/misc/cxl/main.c int val = atomic_cmpxchg(&adapter->contexts_num, -1, 0); val 308 drivers/misc/cxl/main.c if (val != -1) { val 311 drivers/misc/cxl/main.c val); val 1498 drivers/misc/cxl/native.c u32 val; val 1501 drivers/misc/cxl/native.c rc = native_afu_cr_read32(afu, cr, aligned_off, &val); val 1503 drivers/misc/cxl/native.c *out = (val >> ((off & 0x3) * 8)) & 0xffff; val 1510 drivers/misc/cxl/native.c u32 val; val 1513 drivers/misc/cxl/native.c rc = native_afu_cr_read32(afu, cr, aligned_off, &val); val 1515 drivers/misc/cxl/native.c *out = (val >> ((off & 0x3) * 8)) & 0xff; val 28 drivers/misc/cxl/of.c const char *prop_name, u32 *val) val 34 drivers/misc/cxl/of.c *val = be32_to_cpu(prop[0]); val 36 drivers/misc/cxl/of.c pr_info("%s: %#x (%u)\n", prop_name, *val, *val); val 41 drivers/misc/cxl/of.c const char *prop_name, u64 *val) val 47 drivers/misc/cxl/of.c *val = be64_to_cpu(prop[0]); val 49 drivers/misc/cxl/of.c pr_info("%s: %#llx (%llu)\n", prop_name, *val, *val); val 146 drivers/misc/cxl/of.c u32 val = 0, class_code; val 184 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,scratchpad-size", &val); val 185 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,programmable", &val); val 203 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,max-ints", &val); val 204 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,vpd-size", &val); val 211 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,config-record-type", &val); val 239 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,function-number", &val); val 240 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,privileged-function", &val); val 241 drivers/misc/cxl/of.c read_prop_dword(np, "vendor-id", &val); val 242 drivers/misc/cxl/of.c read_prop_dword(np, "device-id", &val); val 243 drivers/misc/cxl/of.c read_prop_dword(np, "revision-id", &val); val 244 drivers/misc/cxl/of.c read_prop_dword(np, "class-code", &val); val 245 drivers/misc/cxl/of.c read_prop_dword(np, "subsystem-vendor-id", &val); val 246 drivers/misc/cxl/of.c read_prop_dword(np, "subsystem-id", &val); val 252 drivers/misc/cxl/of.c val = 0; val 253 drivers/misc/cxl/of.c prop = read_prop_dword(np, "ibm,process-mmio", &val); val 254 drivers/misc/cxl/of.c if (prop && val == 1) val 260 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,supports-aur", &val); val 261 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,supports-csrp", &val); val 262 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,supports-prr", &val); val 265 drivers/misc/cxl/of.c prop = read_prop_dword(np, "ibm,function-error-interrupt", &val); val 267 drivers/misc/cxl/of.c afu->serr_hwirq = val; val 350 drivers/misc/cxl/of.c u32 val = 0; val 359 drivers/misc/cxl/of.c read_prop_dword(np, "#address-cells", &val); val 360 drivers/misc/cxl/of.c read_prop_dword(np, "#size-cells", &val); val 390 drivers/misc/cxl/of.c prop = read_prop_dword(np, "ibm,caia-version", &val); val 392 drivers/misc/cxl/of.c adapter->caia_major = (val & 0xFF00) >> 8; val 393 drivers/misc/cxl/of.c adapter->caia_minor = val & 0xFF; val 396 drivers/misc/cxl/of.c prop = read_prop_dword(np, "ibm,psl-revision", &val); val 398 drivers/misc/cxl/of.c adapter->psl_rev = val; val 407 drivers/misc/cxl/of.c prop = read_prop_dword(np, "vendor-id", &val); val 409 drivers/misc/cxl/of.c adapter->guest->vendor = val; val 411 drivers/misc/cxl/of.c prop = read_prop_dword(np, "device-id", &val); val 413 drivers/misc/cxl/of.c adapter->guest->device = val; val 416 drivers/misc/cxl/of.c read_prop_dword(np, "ibm,privileged-facility", &val); val 417 drivers/misc/cxl/of.c read_prop_dword(np, "revision-id", &val); val 418 drivers/misc/cxl/of.c read_prop_dword(np, "class-code", &val); val 421 drivers/misc/cxl/of.c prop = read_prop_dword(np, "subsystem-vendor-id", &val); val 423 drivers/misc/cxl/of.c adapter->guest->subsystem_vendor = val; val 425 drivers/misc/cxl/of.c prop = read_prop_dword(np, "subsystem-id", &val); val 427 drivers/misc/cxl/of.c adapter->guest->subsystem = val; val 52 drivers/misc/cxl/pci.c #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ val 53 drivers/misc/cxl/pci.c pci_write_config_byte(dev, vsec + 0xa, val) val 71 drivers/misc/cxl/pci.c #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ val 72 drivers/misc/cxl/pci.c pci_write_config_byte(dev, vsec + 0x13, val) val 91 drivers/misc/cxl/pci.c #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) val 92 drivers/misc/cxl/pci.c #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) val 95 drivers/misc/cxl/pci.c #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) val 96 drivers/misc/cxl/pci.c #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) val 97 drivers/misc/cxl/pci.c #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) val 98 drivers/misc/cxl/pci.c #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) val 99 drivers/misc/cxl/pci.c #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) val 100 drivers/misc/cxl/pci.c #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) val 101 drivers/misc/cxl/pci.c #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) val 102 drivers/misc/cxl/pci.c #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) val 104 drivers/misc/cxl/pci.c #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) val 107 drivers/misc/cxl/pci.c #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) val 108 drivers/misc/cxl/pci.c #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) val 109 drivers/misc/cxl/pci.c #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) val 112 drivers/misc/cxl/pci.c #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) val 154 drivers/misc/cxl/pci.c u16 val; val 157 drivers/misc/cxl/pci.c pci_read_config_word(dev, vsec + 0x4, &val); val 158 drivers/misc/cxl/pci.c if (val == CXL_PCI_VSEC_ID) val 168 drivers/misc/cxl/pci.c u32 val; val 172 drivers/misc/cxl/pci.c pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); val 173 drivers/misc/cxl/pci.c dev_info(&dev->dev, "BAR0: %#.8x\n", val); val 174 drivers/misc/cxl/pci.c pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); val 175 drivers/misc/cxl/pci.c dev_info(&dev->dev, "BAR1: %#.8x\n", val); val 176 drivers/misc/cxl/pci.c pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); val 177 drivers/misc/cxl/pci.c dev_info(&dev->dev, "BAR2: %#.8x\n", val); val 178 drivers/misc/cxl/pci.c pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); val 179 drivers/misc/cxl/pci.c dev_info(&dev->dev, "BAR3: %#.8x\n", val); val 180 drivers/misc/cxl/pci.c pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); val 181 drivers/misc/cxl/pci.c dev_info(&dev->dev, "BAR4: %#.8x\n", val); val 182 drivers/misc/cxl/pci.c pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); val 183 drivers/misc/cxl/pci.c dev_info(&dev->dev, "BAR5: %#.8x\n", val); val 198 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x0, &val); val 199 drivers/misc/cxl/pci.c show_reg("Cap ID", (val >> 0) & 0xffff); val 200 drivers/misc/cxl/pci.c show_reg("Cap Ver", (val >> 16) & 0xf); val 201 drivers/misc/cxl/pci.c show_reg("Next Cap Ptr", (val >> 20) & 0xfff); val 202 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x4, &val); val 203 drivers/misc/cxl/pci.c show_reg("VSEC ID", (val >> 0) & 0xffff); val 204 drivers/misc/cxl/pci.c show_reg("VSEC Rev", (val >> 16) & 0xf); val 205 drivers/misc/cxl/pci.c show_reg("VSEC Length", (val >> 20) & 0xfff); val 206 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x8, &val); val 207 drivers/misc/cxl/pci.c show_reg("Num AFUs", (val >> 0) & 0xff); val 208 drivers/misc/cxl/pci.c show_reg("Status", (val >> 8) & 0xff); val 209 drivers/misc/cxl/pci.c show_reg("Mode Control", (val >> 16) & 0xff); val 210 drivers/misc/cxl/pci.c show_reg("Reserved", (val >> 24) & 0xff); val 211 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0xc, &val); val 212 drivers/misc/cxl/pci.c show_reg("PSL Rev", (val >> 0) & 0xffff); val 213 drivers/misc/cxl/pci.c show_reg("CAIA Ver", (val >> 16) & 0xffff); val 214 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x10, &val); val 215 drivers/misc/cxl/pci.c show_reg("Base Image Rev", (val >> 0) & 0xffff); val 216 drivers/misc/cxl/pci.c show_reg("Reserved", (val >> 16) & 0x0fff); val 217 drivers/misc/cxl/pci.c show_reg("Image Control", (val >> 28) & 0x3); val 218 drivers/misc/cxl/pci.c show_reg("Reserved", (val >> 30) & 0x1); val 219 drivers/misc/cxl/pci.c show_reg("Image Loaded", (val >> 31) & 0x1); val 221 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x14, &val); val 222 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 223 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x18, &val); val 224 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 225 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x1c, &val); val 226 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 228 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x20, &val); val 229 drivers/misc/cxl/pci.c show_reg("AFU Descriptor Offset", val); val 230 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x24, &val); val 231 drivers/misc/cxl/pci.c show_reg("AFU Descriptor Size", val); val 232 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x28, &val); val 233 drivers/misc/cxl/pci.c show_reg("Problem State Offset", val); val 234 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x2c, &val); val 235 drivers/misc/cxl/pci.c show_reg("Problem State Size", val); val 237 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x30, &val); val 238 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 239 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x34, &val); val 240 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 241 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x38, &val); val 242 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 243 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x3c, &val); val 244 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 246 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x40, &val); val 247 drivers/misc/cxl/pci.c show_reg("PSL Programming Port", val); val 248 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x44, &val); val 249 drivers/misc/cxl/pci.c show_reg("PSL Programming Control", val); val 251 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x48, &val); val 252 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 253 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x4c, &val); val 254 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 256 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x50, &val); val 257 drivers/misc/cxl/pci.c show_reg("Flash Address Register", val); val 258 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x54, &val); val 259 drivers/misc/cxl/pci.c show_reg("Flash Size Register", val); val 260 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x58, &val); val 261 drivers/misc/cxl/pci.c show_reg("Flash Status/Control Register", val); val 262 drivers/misc/cxl/pci.c pci_read_config_dword(dev, vsec + 0x58, &val); val 263 drivers/misc/cxl/pci.c show_reg("Flash Data Port", val); val 270 drivers/misc/cxl/pci.c u64 val, afu_cr_num, afu_cr_off, afu_cr_len; val 276 drivers/misc/cxl/pci.c val = AFUD_READ_INFO(afu); val 277 drivers/misc/cxl/pci.c show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); val 278 drivers/misc/cxl/pci.c show_reg("num_of_processes", AFUD_NUM_PROCS(val)); val 279 drivers/misc/cxl/pci.c show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); val 280 drivers/misc/cxl/pci.c show_reg("req_prog_mode", val & 0xffffULL); val 281 drivers/misc/cxl/pci.c afu_cr_num = AFUD_NUM_CRS(val); val 283 drivers/misc/cxl/pci.c val = AFUD_READ(afu, 0x8); val 284 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 285 drivers/misc/cxl/pci.c val = AFUD_READ(afu, 0x10); val 286 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 287 drivers/misc/cxl/pci.c val = AFUD_READ(afu, 0x18); val 288 drivers/misc/cxl/pci.c show_reg("Reserved", val); val 290 drivers/misc/cxl/pci.c val = AFUD_READ_CR(afu); val 291 drivers/misc/cxl/pci.c show_reg("Reserved", (val >> (63-7)) & 0xff); val 292 drivers/misc/cxl/pci.c show_reg("AFU_CR_len", AFUD_CR_LEN(val)); val 293 drivers/misc/cxl/pci.c afu_cr_len = AFUD_CR_LEN(val) * 256; val 295 drivers/misc/cxl/pci.c val = AFUD_READ_CR_OFF(afu); val 296 drivers/misc/cxl/pci.c afu_cr_off = val; val 297 drivers/misc/cxl/pci.c show_reg("AFU_CR_offset", val); val 299 drivers/misc/cxl/pci.c val = AFUD_READ_PPPSA(afu); val 300 drivers/misc/cxl/pci.c show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); val 301 drivers/misc/cxl/pci.c show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); val 303 drivers/misc/cxl/pci.c val = AFUD_READ_PPPSA_OFF(afu); val 304 drivers/misc/cxl/pci.c show_reg("PerProcessPSA_offset", val); val 306 drivers/misc/cxl/pci.c val = AFUD_READ_EB(afu); val 307 drivers/misc/cxl/pci.c show_reg("Reserved", (val >> (63-7)) & 0xff); val 308 drivers/misc/cxl/pci.c show_reg("AFU_EB_len", AFUD_EB_LEN(val)); val 310 drivers/misc/cxl/pci.c val = AFUD_READ_EB_OFF(afu); val 311 drivers/misc/cxl/pci.c show_reg("AFU_EB_offset", val); val 314 drivers/misc/cxl/pci.c val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len); val 315 drivers/misc/cxl/pci.c show_reg("CR Vendor", val & 0xffff); val 316 drivers/misc/cxl/pci.c show_reg("CR Device", (val >> 16) & 0xffff); val 752 drivers/misc/cxl/pci.c u8 val; val 762 drivers/misc/cxl/pci.c if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) { val 766 drivers/misc/cxl/pci.c val &= ~CXL_VSEC_PROTOCOL_MASK; val 767 drivers/misc/cxl/pci.c val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; val 768 drivers/misc/cxl/pci.c if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) { val 844 drivers/misc/cxl/pci.c u64 val; val 846 drivers/misc/cxl/pci.c val = AFUD_READ_INFO(afu); val 847 drivers/misc/cxl/pci.c afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); val 848 drivers/misc/cxl/pci.c afu->max_procs_virtualised = AFUD_NUM_PROCS(val); val 849 drivers/misc/cxl/pci.c afu->crs_num = AFUD_NUM_CRS(val); val 851 drivers/misc/cxl/pci.c if (AFUD_AFU_DIRECTED(val)) val 853 drivers/misc/cxl/pci.c if (AFUD_DEDICATED_PROCESS(val)) val 855 drivers/misc/cxl/pci.c if (AFUD_TIME_SLICED(val)) val 858 drivers/misc/cxl/pci.c val = AFUD_READ_PPPSA(afu); val 859 drivers/misc/cxl/pci.c afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; val 860 drivers/misc/cxl/pci.c afu->psa = AFUD_PPPSA_PSA(val); val 861 drivers/misc/cxl/pci.c if ((afu->pp_psa = AFUD_PPPSA_PP(val))) val 864 drivers/misc/cxl/pci.c val = AFUD_READ_CR(afu); val 865 drivers/misc/cxl/pci.c afu->crs_len = AFUD_CR_LEN(val) * 256; val 890 drivers/misc/cxl/pci.c u32 val; val 902 drivers/misc/cxl/pci.c rc = cxl_ops->afu_cr_read32(afu, i, 0, &val); val 903 drivers/misc/cxl/pci.c if (rc || val == 0) { val 92 drivers/misc/cxl/sysfs.c int val; val 94 drivers/misc/cxl/sysfs.c rc = sscanf(buf, "%i", &val); val 95 drivers/misc/cxl/sysfs.c if ((rc != 1) || (val != 1 && val != -1)) val 103 drivers/misc/cxl/sysfs.c if (val == 1) { val 113 drivers/misc/cxl/sysfs.c } else if (val == -1) { val 175 drivers/misc/cxl/sysfs.c int val; val 177 drivers/misc/cxl/sysfs.c rc = sscanf(buf, "%i", &val); val 178 drivers/misc/cxl/sysfs.c if ((rc != 1) || !(val == 1 || val == 0)) val 181 drivers/misc/cxl/sysfs.c adapter->perst_same_image = (val == 1 ? true : false); val 547 drivers/misc/cxl/sysfs.c u64 i, j, val, rc; val 550 drivers/misc/cxl/sysfs.c rc = cxl_ops->afu_cr_read64(afu, cr->cr, off & ~0x7, &val); val 552 drivers/misc/cxl/sysfs.c val = ~0ULL; val 554 drivers/misc/cxl/sysfs.c buf[i] = (val >> (j * 8)) & 0xff; val 117 drivers/misc/cxl/vphb.c int offset, int len, u32 *val) val 137 drivers/misc/cxl/vphb.c *val = val8; val 141 drivers/misc/cxl/vphb.c *val = val16; val 145 drivers/misc/cxl/vphb.c *val = val32; val 157 drivers/misc/cxl/vphb.c int offset, int len, u32 val) val 173 drivers/misc/cxl/vphb.c rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff); val 176 drivers/misc/cxl/vphb.c rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff); val 179 drivers/misc/cxl/vphb.c rc = cxl_ops->afu_cr_write32(afu, record, offset, val); val 59 drivers/misc/ds1682.c unsigned long long val, check; val 71 drivers/misc/ds1682.c val = le32_to_cpu(val_le); val 84 drivers/misc/ds1682.c check = val; val 85 drivers/misc/ds1682.c val = le32_to_cpu(val_le); val 87 drivers/misc/ds1682.c } while (val != check && val != (check + 1)); val 94 drivers/misc/ds1682.c return sprintf(buf, "%llu\n", (sattr->nr == 4) ? (val * 250) : val); val 102 drivers/misc/ds1682.c u64 val; val 109 drivers/misc/ds1682.c rc = kstrtoull(buf, 0, &val); val 118 drivers/misc/ds1682.c do_div(val, 250); val 121 drivers/misc/ds1682.c val_le = cpu_to_le32(val); val 386 drivers/misc/eeprom/at24.c static int at24_read(void *priv, unsigned int off, void *val, size_t count) val 390 drivers/misc/eeprom/at24.c char *buf = val; val 433 drivers/misc/eeprom/at24.c static int at24_write(void *priv, unsigned int off, void *val, size_t count) val 437 drivers/misc/eeprom/at24.c char *buf = val; val 63 drivers/misc/eeprom/at25.c void *val, size_t count) val 66 drivers/misc/eeprom/at25.c char *buf = val; val 129 drivers/misc/eeprom/at25.c static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count) val 132 drivers/misc/eeprom/at25.c const char *buf = val; val 249 drivers/misc/eeprom/at25.c u32 val; val 254 drivers/misc/eeprom/at25.c if (device_property_read_u32(dev, "size", &val) == 0 || val 255 drivers/misc/eeprom/at25.c device_property_read_u32(dev, "at25,byte-len", &val) == 0) { val 256 drivers/misc/eeprom/at25.c chip->byte_len = val; val 262 drivers/misc/eeprom/at25.c if (device_property_read_u32(dev, "pagesize", &val) == 0 || val 263 drivers/misc/eeprom/at25.c device_property_read_u32(dev, "at25,page-size", &val) == 0) { val 264 drivers/misc/eeprom/at25.c chip->page_size = (u16)val; val 270 drivers/misc/eeprom/at25.c if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) { val 271 drivers/misc/eeprom/at25.c chip->flags = (u16)val; val 273 drivers/misc/eeprom/at25.c if (device_property_read_u32(dev, "address-width", &val)) { val 278 drivers/misc/eeprom/at25.c switch (val) { val 294 drivers/misc/eeprom/at25.c val); val 59 drivers/misc/eeprom/eeprom_93xx46.c void *val, size_t count) val 62 drivers/misc/eeprom/eeprom_93xx46.c char *buf = val; val 228 drivers/misc/eeprom/eeprom_93xx46.c void *val, size_t count) val 231 drivers/misc/eeprom/eeprom_93xx46.c char *buf = val; val 251 drivers/misc/eeprom/idt_89hpesx.c #define CSR_REAL_ADDR(val) ((unsigned int)val << 2) val 491 drivers/misc/enclosure.c int val = simple_strtoul(buf, NULL, 0); val 494 drivers/misc/enclosure.c edev->cb->set_fault(edev, ecomp, val); val 549 drivers/misc/enclosure.c int val = simple_strtoul(buf, NULL, 0); val 552 drivers/misc/enclosure.c edev->cb->set_active(edev, ecomp, val); val 573 drivers/misc/enclosure.c int val = simple_strtoul(buf, NULL, 0); val 576 drivers/misc/enclosure.c edev->cb->set_locate(edev, ecomp, val); val 603 drivers/misc/enclosure.c int val; val 607 drivers/misc/enclosure.c val = 1; val 610 drivers/misc/enclosure.c val = 0; val 615 drivers/misc/enclosure.c edev->cb->set_power_status(edev, ecomp, val); val 78 drivers/misc/genwqe/card_base.h u64 val; val 456 drivers/misc/genwqe/card_base.h int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func); val 528 drivers/misc/genwqe/card_base.h int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val); val 530 drivers/misc/genwqe/card_base.h int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val); val 35 drivers/misc/genwqe/card_debugfs.c v_hi = (regs[i].val >> 32) & 0xffffffff; val 36 drivers/misc/genwqe/card_debugfs.c v_lo = (regs[i].val) & 0xffffffff; val 137 drivers/misc/genwqe/card_debugfs.c if (regs[i].val == 0x0ull) val 141 drivers/misc/genwqe/card_debugfs.c regs[i].addr, regs[i].val); val 161 drivers/misc/genwqe/card_debugfs.c if (regs[i].val == 0x0ull) val 165 drivers/misc/genwqe/card_debugfs.c regs[i].addr, regs[i].val); val 1049 drivers/misc/genwqe/card_dev.c u64 val; val 1075 drivers/misc/genwqe/card_dev.c val = __genwqe_readq(cd, reg_offs); val 1076 drivers/misc/genwqe/card_dev.c put_user(val, &io->val64); val 1095 drivers/misc/genwqe/card_dev.c if (get_user(val, &io->val64)) val 1098 drivers/misc/genwqe/card_dev.c __genwqe_writeq(cd, reg_offs, val); val 1111 drivers/misc/genwqe/card_dev.c val = __genwqe_readl(cd, reg_offs); val 1112 drivers/misc/genwqe/card_dev.c put_user(val, &io->val64); val 1131 drivers/misc/genwqe/card_dev.c if (get_user(val, &io->val64)) val 1134 drivers/misc/genwqe/card_dev.c __genwqe_writel(cd, reg_offs, val); val 44 drivers/misc/genwqe/card_utils.c int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val) val 57 drivers/misc/genwqe/card_utils.c __raw_writeq((__force u64)cpu_to_be64(val), cd->mmio + byte_offs); val 95 drivers/misc/genwqe/card_utils.c int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val) val 108 drivers/misc/genwqe/card_utils.c __raw_writel((__force u32)cpu_to_be32(val), cd->mmio + byte_offs); val 770 drivers/misc/genwqe/card_utils.c u64 val) val 777 drivers/misc/genwqe/card_utils.c r[*i].val = val; val 783 drivers/misc/genwqe/card_utils.c unsigned int *i, unsigned int m, u32 addr, u64 val) val 785 drivers/misc/genwqe/card_utils.c return set_reg_idx(cd, r, i, m, addr, 0, val); val 838 drivers/misc/genwqe/card_utils.c regs[i].val = 0xffffffffffffffffull; val 850 drivers/misc/genwqe/card_utils.c u64 eevptr, val, addr; val 859 drivers/misc/genwqe/card_utils.c val = __genwqe_readq(cd, l_addr); val 861 drivers/misc/genwqe/card_utils.c if ((val == 0x0) || (val == -1ull)) val 865 drivers/misc/genwqe/card_utils.c d_len = (val & 0x0000007fff000000ull) >> 24; val 868 drivers/misc/genwqe/card_utils.c d_type = (val & 0x0000008000000000ull) >> 36; val 882 drivers/misc/genwqe/card_utils.c val = __genwqe_readq(cd, addr); val 884 drivers/misc/genwqe/card_utils.c if ((val == 0x0ull) || (val == -1ull)) val 887 drivers/misc/genwqe/card_utils.c traps = (val >> 24) & 0xff; val 888 drivers/misc/genwqe/card_utils.c traces = (val >> 16) & 0xff; val 889 drivers/misc/genwqe/card_utils.c trace_entries = val & 0xffff; val 905 drivers/misc/genwqe/card_utils.c u64 eevptr, e, val, addr; val 924 drivers/misc/genwqe/card_utils.c val = __genwqe_readq(cd, d_addr); val 926 drivers/misc/genwqe/card_utils.c d_addr, i, val); val 931 drivers/misc/genwqe/card_utils.c val = __genwqe_readq(cd, d_addr); val 933 drivers/misc/genwqe/card_utils.c d_addr, 0, val); val 947 drivers/misc/genwqe/card_utils.c val = __genwqe_readq(cd, addr); val 949 drivers/misc/genwqe/card_utils.c if ((val == 0x0ull) || (val == -1ull)) val 952 drivers/misc/genwqe/card_utils.c traps = (val >> 24) & 0xff; /* Number of Traps */ val 953 drivers/misc/genwqe/card_utils.c traces = (val >> 16) & 0xff; /* Number of Traces */ val 954 drivers/misc/genwqe/card_utils.c trace_entries = val & 0xffff; /* Entries per trace */ val 972 drivers/misc/genwqe/card_utils.c val = __genwqe_readq(cd, addr); val 974 drivers/misc/genwqe/card_utils.c (diag_sel<<16) | trace_entry, val); val 987 drivers/misc/genwqe/card_utils.c int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func) val 990 drivers/misc/genwqe/card_utils.c __genwqe_writeq(cd, reg, val); val 22 drivers/misc/habanalabs/debugfs.c u8 i2c_reg, u32 *val) val 39 drivers/misc/habanalabs/debugfs.c HL_DEVICE_TIMEOUT_USEC, (long *) val); val 48 drivers/misc/habanalabs/debugfs.c u8 i2c_reg, u32 val) val 63 drivers/misc/habanalabs/debugfs.c pkt.value = cpu_to_le64(val); val 608 drivers/misc/habanalabs/debugfs.c u32 val; val 620 drivers/misc/habanalabs/debugfs.c rc = hdev->asic_funcs->debugfs_read32(hdev, addr, &val); val 626 drivers/misc/habanalabs/debugfs.c sprintf(tmp_buf, "0x%08x\n", val); val 718 drivers/misc/habanalabs/debugfs.c u32 val; val 725 drivers/misc/habanalabs/debugfs.c entry->i2c_reg, &val); val 733 drivers/misc/habanalabs/debugfs.c sprintf(tmp_buf, "0x%02x\n", val); val 1436 drivers/misc/habanalabs/device.c inline void hl_wreg(struct hl_device *hdev, u32 reg, u32 val) val 1438 drivers/misc/habanalabs/device.c writel(val, hdev->rmmio + reg); val 474 drivers/misc/habanalabs/goya/goya.c u32 val; val 507 drivers/misc/habanalabs/goya/goya.c val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS); val 508 drivers/misc/habanalabs/goya/goya.c if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK) val 1110 drivers/misc/habanalabs/goya/goya.c u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset; val 1123 drivers/misc/habanalabs/goya/goya.c val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset); val 1124 drivers/misc/habanalabs/goya/goya.c if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK) val 1128 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000); val 1147 drivers/misc/habanalabs/goya/goya.c val, val 1148 drivers/misc/habanalabs/goya/goya.c (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK), val 1169 drivers/misc/habanalabs/goya/goya.c val = RREG32(tpc_slm_offset); val 4013 drivers/misc/habanalabs/goya/goya.c void goya_update_eq_ci(struct hl_device *hdev, u32 val) val 4015 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_EQ_CI, val); val 4058 drivers/misc/habanalabs/goya/goya.c static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val) val 4065 drivers/misc/habanalabs/goya/goya.c *val = RREG32(addr - CFG_BASE); val 4070 drivers/misc/habanalabs/goya/goya.c *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] + val 4081 drivers/misc/habanalabs/goya/goya.c *val = readl(hdev->pcie_bar[DDR_BAR_ID] + val 4091 drivers/misc/habanalabs/goya/goya.c *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE); val 4115 drivers/misc/habanalabs/goya/goya.c static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val) val 4122 drivers/misc/habanalabs/goya/goya.c WREG32(addr - CFG_BASE, val); val 4127 drivers/misc/habanalabs/goya/goya.c writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] + val 4138 drivers/misc/habanalabs/goya/goya.c writel(val, hdev->pcie_bar[DDR_BAR_ID] + val 4148 drivers/misc/habanalabs/goya/goya.c *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val; val 4168 drivers/misc/habanalabs/goya/goya.c static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val) val 4175 drivers/misc/habanalabs/goya/goya.c writeq(val, hdev->pcie_bar[DDR_BAR_ID] + val 4391 drivers/misc/habanalabs/goya/goya.c u32 val; val 4396 drivers/misc/habanalabs/goya/goya.c val = RREG32(mmMMU_PAGE_ERROR_CAPTURE); val 4397 drivers/misc/habanalabs/goya/goya.c if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) { val 4398 drivers/misc/habanalabs/goya/goya.c addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK; val 4609 drivers/misc/habanalabs/goya/goya.c u64 val, bool is_dram) val 4638 drivers/misc/habanalabs/goya/goya.c lin_dma_pkt->src_addr = cpu_to_le64(val); val 4685 drivers/misc/habanalabs/goya/goya.c u64 val = 0x7777777777777777ull; val 4690 drivers/misc/habanalabs/goya/goya.c rc = goya_memset_device_memory(hdev, addr, size, val, false); val 4735 drivers/misc/habanalabs/goya/goya.c u64 val = 0x9999999999999999ull; val 4740 drivers/misc/habanalabs/goya/goya.c return goya_memset_device_memory(hdev, addr, size, val, true); val 184 drivers/misc/habanalabs/goya/goyaP.h void goya_update_eq_ci(struct hl_device *hdev, u32 val); val 189 drivers/misc/habanalabs/goya/goyaP.h u8 i2c_addr, u8 i2c_reg, u32 *val); val 191 drivers/misc/habanalabs/goya/goyaP.h u8 i2c_addr, u8 i2c_reg, u32 val); val 204 drivers/misc/habanalabs/goya/goya_coresight.c u32 val, timeout_usec; val 214 drivers/misc/habanalabs/goya/goya_coresight.c val, val 215 drivers/misc/habanalabs/goya/goya_coresight.c up ? val & BIT(position) : !(val & BIT(position)), val 303 drivers/misc/habanalabs/goya/goya_coresight.c u32 val; val 315 drivers/misc/habanalabs/goya/goya_coresight.c val = RREG32(base_reg + 0x304); val 316 drivers/misc/habanalabs/goya/goya_coresight.c val |= 0x1000; val 317 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, val); val 318 drivers/misc/habanalabs/goya/goya_coresight.c val |= 0x40; val 319 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, val); val 381 drivers/misc/habanalabs/goya/goya_coresight.c u32 val; val 386 drivers/misc/habanalabs/goya/goya_coresight.c val = RREG32(base_reg + 0x304); val 387 drivers/misc/habanalabs/goya/goya_coresight.c val |= 0x1000; val 388 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, val); val 389 drivers/misc/habanalabs/goya/goya_coresight.c val |= 0x40; val 390 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, val); val 642 drivers/misc/habanalabs/goya/goya_coresight.c u32 val; val 674 drivers/misc/habanalabs/goya/goya_coresight.c val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); val 550 drivers/misc/habanalabs/habanalabs.h void (*update_eq_ci)(struct hl_device *hdev, u32 val); val 553 drivers/misc/habanalabs/habanalabs.h int (*debugfs_read32)(struct hl_device *hdev, u64 addr, u32 *val); val 554 drivers/misc/habanalabs/habanalabs.h int (*debugfs_write32)(struct hl_device *hdev, u64 addr, u32 val); val 564 drivers/misc/habanalabs/habanalabs.h void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val); val 585 drivers/misc/habanalabs/habanalabs.h void (*wreg)(struct hl_device *hdev, u32 reg, u32 val); val 1032 drivers/misc/habanalabs/habanalabs.h void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); val 1039 drivers/misc/habanalabs/habanalabs.h #define WREG32_P(reg, val, mask) \ val 1043 drivers/misc/habanalabs/habanalabs.h tmp_ |= ((val) & ~(mask)); \ val 1051 drivers/misc/habanalabs/habanalabs.h #define WREG32_FIELD(reg, field, val) \ val 1053 drivers/misc/habanalabs/habanalabs.h (val) << REG_FIELD_SHIFT(reg, field)) val 1058 drivers/misc/habanalabs/habanalabs.h #define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \ val 1069 drivers/misc/habanalabs/habanalabs.h (val) = RREG32(addr); \ val 1073 drivers/misc/habanalabs/habanalabs.h (val) = RREG32(addr); \ val 1094 drivers/misc/habanalabs/habanalabs.h #define hl_poll_timeout_memory(hdev, addr, val, cond, sleep_us, timeout_us, \ val 1108 drivers/misc/habanalabs/habanalabs.h (val) = *((u32 *) (uintptr_t) (addr)); \ val 1110 drivers/misc/habanalabs/habanalabs.h (val) = le32_to_cpu(*(__le32 *) &(val)); \ val 1114 drivers/misc/habanalabs/habanalabs.h (val) = *((u32 *) (uintptr_t) (addr)); \ val 1116 drivers/misc/habanalabs/habanalabs.h (val) = le32_to_cpu(*(__le32 *) &(val)); \ val 1125 drivers/misc/habanalabs/habanalabs.h #define hl_poll_timeout_device_memory(hdev, addr, val, cond, sleep_us, \ val 1137 drivers/misc/habanalabs/habanalabs.h (val) = readl(addr); \ val 1141 drivers/misc/habanalabs/habanalabs.h (val) = readl(addr); \ val 1437 drivers/misc/habanalabs/habanalabs.h u32 hl_hw_queue_add_ptr(u32 ptr, u16 val); val 20 drivers/misc/habanalabs/hw_queue.c inline u32 hl_hw_queue_add_ptr(u32 ptr, u16 val) val 22 drivers/misc/habanalabs/hw_queue.c ptr += val; val 113 drivers/misc/habanalabs/hwmon.c u32 attr, int channel, long *val) val 133 drivers/misc/habanalabs/hwmon.c *val = hl_get_temperature(hdev, channel, attr); val 145 drivers/misc/habanalabs/hwmon.c *val = hl_get_voltage(hdev, channel, attr); val 157 drivers/misc/habanalabs/hwmon.c *val = hl_get_current(hdev, channel, attr); val 168 drivers/misc/habanalabs/hwmon.c *val = hl_get_fan_speed(hdev, channel, attr); val 178 drivers/misc/habanalabs/hwmon.c *val = hl_get_pwm_info(hdev, channel, attr); val 187 drivers/misc/habanalabs/hwmon.c u32 attr, int channel, long val) val 203 drivers/misc/habanalabs/hwmon.c hl_set_pwm_info(hdev, channel, attr, val); val 99 drivers/misc/habanalabs/mmu.c static inline void write_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val) val 108 drivers/misc/habanalabs/mmu.c u64 phys_val = get_phys_addr(ctx, val & PTE_PHYS_ADDR_MASK) | val 109 drivers/misc/habanalabs/mmu.c (val & OFFSET_MASK); val 115 drivers/misc/habanalabs/mmu.c *(u64 *) (uintptr_t) shadow_pte_addr = val; val 120 drivers/misc/habanalabs/mmu.c u64 val) val 124 drivers/misc/habanalabs/mmu.c val); val 125 drivers/misc/habanalabs/mmu.c *(u64 *) (uintptr_t) shadow_pte_addr = val; val 94 drivers/misc/habanalabs/pci.c u32 val; val 111 drivers/misc/habanalabs/pci.c pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val); val 112 drivers/misc/habanalabs/pci.c if (val & PCI_CONFIG_ELBI_STS_MASK) val 116 drivers/misc/habanalabs/pci.c &val); val 123 drivers/misc/habanalabs/pci.c if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE) val 126 drivers/misc/habanalabs/pci.c if (val & PCI_CONFIG_ELBI_STS_ERR) { val 131 drivers/misc/habanalabs/pci.c if (!(val & PCI_CONFIG_ELBI_STS_MASK)) { val 172 drivers/misc/habanalabs/pci.c u16 val; val 175 drivers/misc/habanalabs/pci.c pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val); val 176 drivers/misc/habanalabs/pci.c val |= PCI_BRIDGE_CTL_BUS_RESET; val 177 drivers/misc/habanalabs/pci.c pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val); val 180 drivers/misc/habanalabs/pci.c val &= ~(PCI_BRIDGE_CTL_BUS_RESET); val 181 drivers/misc/habanalabs/pci.c pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val); val 280 drivers/misc/habanalabs/sysfs.c long val; val 285 drivers/misc/habanalabs/sysfs.c val = hl_get_max_power(hdev); val 287 drivers/misc/habanalabs/sysfs.c return sprintf(buf, "%lu\n", val); val 35 drivers/misc/hmc6352.c unsigned long val; val 37 drivers/misc/hmc6352.c ret = kstrtoul(buf, 10, &val); val 40 drivers/misc/hmc6352.c if (val >= strlen(map)) val 42 drivers/misc/hmc6352.c val = array_index_nospec(val, strlen(map)); val 44 drivers/misc/hmc6352.c ret = compass_command(c, map[val]); val 31 drivers/misc/ibmasm/heartbeat.c static int panic_happened(struct notifier_block *n, unsigned long val, void *v) val 382 drivers/misc/ics932s401.c unsigned long val; val 394 drivers/misc/ics932s401.c val = data->regs[reg] | (data->regs[reg + 1] << 8); val 395 drivers/misc/ics932s401.c val &= ICS932S401_SPREAD_MASK; val 398 drivers/misc/ics932s401.c val = 500000 * val / 16384; val 399 drivers/misc/ics932s401.c return sprintf(buf, "-0.%lu%%\n", val); val 73 drivers/misc/isl29003.c u32 reg, u8 mask, u8 shift, u8 val) val 86 drivers/misc/isl29003.c tmp |= val << shift; val 197 drivers/misc/isl29003.c unsigned long val; val 200 drivers/misc/isl29003.c ret = kstrtoul(buf, 10, &val); val 204 drivers/misc/isl29003.c if (val > 3) val 207 drivers/misc/isl29003.c ret = isl29003_set_range(client, val); val 233 drivers/misc/isl29003.c unsigned long val; val 236 drivers/misc/isl29003.c ret = kstrtoul(buf, 10, &val); val 240 drivers/misc/isl29003.c if (val > 3) val 243 drivers/misc/isl29003.c ret = isl29003_set_resolution(client, val); val 266 drivers/misc/isl29003.c unsigned long val; val 269 drivers/misc/isl29003.c ret = kstrtoul(buf, 10, &val); val 273 drivers/misc/isl29003.c if (val > 2) val 276 drivers/misc/isl29003.c ret = isl29003_set_mode(client, val); val 302 drivers/misc/isl29003.c unsigned long val; val 305 drivers/misc/isl29003.c ret = kstrtoul(buf, 10, &val); val 309 drivers/misc/isl29003.c if (val > 1) val 312 drivers/misc/isl29003.c ret = isl29003_set_power_state(client, val); val 28 drivers/misc/isl29020.c int val; val 30 drivers/misc/isl29020.c val = i2c_smbus_read_byte_data(client, 0x00); val 32 drivers/misc/isl29020.c if (val < 0) val 33 drivers/misc/isl29020.c return val; val 34 drivers/misc/isl29020.c return sprintf(buf, "%d000\n", 1 << (2 * (val & 3))); val 42 drivers/misc/isl29020.c int ret_val, val; val 66 drivers/misc/isl29020.c val = i2c_smbus_read_byte_data(client, 0x00); val 68 drivers/misc/isl29020.c if (val < 0) val 69 drivers/misc/isl29020.c return val; val 70 drivers/misc/isl29020.c lux = ((((1 << (2 * (val & 3))))*1000) * ret_val) / 65536; val 79 drivers/misc/isl29020.c unsigned long val; val 81 drivers/misc/isl29020.c ret_val = kstrtoul(buf, 10, &val); val 85 drivers/misc/isl29020.c if (val < 1 || val > 64000) val 89 drivers/misc/isl29020.c if (val <= 1000) val 90 drivers/misc/isl29020.c val = 1; val 91 drivers/misc/isl29020.c else if (val <= 4000) val 92 drivers/misc/isl29020.c val = 2; val 93 drivers/misc/isl29020.c else if (val <= 16000) val 94 drivers/misc/isl29020.c val = 3; val 96 drivers/misc/isl29020.c val = 4; val 103 drivers/misc/isl29020.c ret_val |= val - 1; val 1109 drivers/misc/kgdbts.c int val = 0; val 1112 drivers/misc/kgdbts.c val = ts.run_test(1, 0); val 1114 drivers/misc/kgdbts.c return val; val 93 drivers/misc/lis3lv02d/lis3lv02d.c static int param_set_axis(const char *val, const struct kernel_param *kp) val 95 drivers/misc/lis3lv02d/lis3lv02d.c int ret = param_set_int(val, kp); val 97 drivers/misc/lis3lv02d/lis3lv02d.c int val = *(int *)kp->arg; val 98 drivers/misc/lis3lv02d/lis3lv02d.c if (val < 0) val 99 drivers/misc/lis3lv02d/lis3lv02d.c val = -val; val 100 drivers/misc/lis3lv02d/lis3lv02d.c if (!val || val > 3) val 940 drivers/misc/lis3lv02d/lis3lv02d.c u32 val; val 965 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,click-threshold-x", &val)) val 966 drivers/misc/lis3lv02d/lis3lv02d.c pdata->click_thresh_x = val; val 967 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,click-threshold-y", &val)) val 968 drivers/misc/lis3lv02d/lis3lv02d.c pdata->click_thresh_y = val; val 969 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,click-threshold-z", &val)) val 970 drivers/misc/lis3lv02d/lis3lv02d.c pdata->click_thresh_z = val; val 972 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,click-time-limit", &val)) val 973 drivers/misc/lis3lv02d/lis3lv02d.c pdata->click_time_limit = val; val 974 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,click-latency", &val)) val 975 drivers/misc/lis3lv02d/lis3lv02d.c pdata->click_latency = val; val 976 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,click-window", &val)) val 977 drivers/misc/lis3lv02d/lis3lv02d.c pdata->click_window = val; val 1006 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,wu-duration-1", &val)) val 1007 drivers/misc/lis3lv02d/lis3lv02d.c pdata->duration1 = val; val 1008 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,wu-duration-2", &val)) val 1009 drivers/misc/lis3lv02d/lis3lv02d.c pdata->duration2 = val; val 1023 drivers/misc/lis3lv02d/lis3lv02d.c if (of_get_property(np, "st,wakeup-threshold", &val)) val 1024 drivers/misc/lis3lv02d/lis3lv02d.c pdata->wakeup_thresh = val; val 1038 drivers/misc/lis3lv02d/lis3lv02d.c if (of_get_property(np, "st,wakeup2-threshold", &val)) val 1039 drivers/misc/lis3lv02d/lis3lv02d.c pdata->wakeup_thresh2 = val; val 1041 drivers/misc/lis3lv02d/lis3lv02d.c if (!of_property_read_u32(np, "st,highpass-cutoff-hz", &val)) { val 1042 drivers/misc/lis3lv02d/lis3lv02d.c switch (val) { val 1071 drivers/misc/lis3lv02d/lis3lv02d.c pdata->default_rate = val; val 264 drivers/misc/lis3lv02d/lis3lv02d.h int (*write) (struct lis3lv02d *lis3, int reg, u8 val); val 36 drivers/misc/lis3lv02d/lis3lv02d_spi.c static int lis3_spi_write(struct lis3lv02d *lis3, int reg, u8 val) val 38 drivers/misc/lis3lv02d/lis3lv02d_spi.c u8 tmp[2] = { reg, val }; val 138 drivers/misc/lkdtm/bugs.c u32 val = 0x12345678; val 142 drivers/misc/lkdtm/bugs.c val = 0x87654321; val 143 drivers/misc/lkdtm/bugs.c *p = val; val 279 drivers/misc/lkdtm/bugs.c void (*direct_write_cr4)(unsigned long val); val 58 drivers/misc/lkdtm/heap.c int *base, *val, saw; val 73 drivers/misc/lkdtm/heap.c val = kmalloc(len, GFP_KERNEL); val 74 drivers/misc/lkdtm/heap.c if (!val) { val 80 drivers/misc/lkdtm/heap.c *val = 0x12345678; val 81 drivers/misc/lkdtm/heap.c base[offset] = *val; val 88 drivers/misc/lkdtm/heap.c if (saw != *val) { val 95 drivers/misc/lkdtm/heap.c kfree(val); val 121 drivers/misc/lkdtm/heap.c int saw, *val; val 129 drivers/misc/lkdtm/heap.c val = kmalloc(1024, GFP_KERNEL); val 130 drivers/misc/lkdtm/heap.c if (!val) { val 138 drivers/misc/lkdtm/heap.c *val = 0x12345678; val 139 drivers/misc/lkdtm/heap.c base[0] = *val; val 144 drivers/misc/lkdtm/heap.c if (saw != *val) { val 151 drivers/misc/lkdtm/heap.c kfree(val); val 156 drivers/misc/lkdtm/heap.c int *val; val 158 drivers/misc/lkdtm/heap.c val = kmem_cache_alloc(double_free_cache, GFP_KERNEL); val 159 drivers/misc/lkdtm/heap.c if (!val) { val 165 drivers/misc/lkdtm/heap.c *val = 0x12345678; val 167 drivers/misc/lkdtm/heap.c kmem_cache_free(double_free_cache, val); val 168 drivers/misc/lkdtm/heap.c kmem_cache_free(double_free_cache, val); val 173 drivers/misc/lkdtm/heap.c int *val; val 175 drivers/misc/lkdtm/heap.c val = kmem_cache_alloc(a_cache, GFP_KERNEL); val 176 drivers/misc/lkdtm/heap.c if (!val) { val 182 drivers/misc/lkdtm/heap.c *val = 0x12345679; val 184 drivers/misc/lkdtm/heap.c kmem_cache_free(b_cache, val); val 20 drivers/misc/mei/mei-trace.h TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val), val 21 drivers/misc/mei/mei-trace.h TP_ARGS(dev, reg, offs, val), val 26 drivers/misc/mei/mei-trace.h __field(u32, val) val 32 drivers/misc/mei/mei-trace.h __entry->val = val; val 35 drivers/misc/mei/mei-trace.h __get_str(dev), __entry->reg, __entry->offs, __entry->val) val 39 drivers/misc/mei/mei-trace.h TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val), val 40 drivers/misc/mei/mei-trace.h TP_ARGS(dev, reg, offs, val), val 45 drivers/misc/mei/mei-trace.h __field(u32, val) val 51 drivers/misc/mei/mei-trace.h __entry->val = val; val 54 drivers/misc/mei/mei-trace.h __get_str(dev), __entry->reg, __entry->offs, __entry->val) val 58 drivers/misc/mei/mei-trace.h TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val), val 59 drivers/misc/mei/mei-trace.h TP_ARGS(dev, reg, offs, val), val 64 drivers/misc/mei/mei-trace.h __field(u32, val) val 70 drivers/misc/mei/mei-trace.h __entry->val = val; val 73 drivers/misc/mei/mei-trace.h __get_str(dev), __entry->reg, __entry->offs, __entry->val) val 112 drivers/misc/mic/card/mic_device.h mic_mmio_write(struct mic_mw *mw, u32 val, u32 offset) val 114 drivers/misc/mic/card/mic_device.h iowrite32(val, mw->va + offset); val 113 drivers/misc/mic/host/mic_device.h void (*write_spad)(struct mic_device *mdev, unsigned int idx, u32 val); val 147 drivers/misc/mic/host/mic_device.h mic_mmio_write(struct mic_mw *mw, u32 val, u32 offset) val 149 drivers/misc/mic/host/mic_device.h iowrite32(val, mw->va + offset); val 32 drivers/misc/mic/host/mic_x100.c mic_x100_write_spad(struct mic_device *mdev, unsigned int idx, u32 val) val 35 drivers/misc/mic/host/mic_x100.c val, idx); val 36 drivers/misc/mic/host/mic_x100.c mic_mmio_write(&mdev->mmio, val, val 53 drivers/misc/mic/host/mic_x100.c u32 val = mic_mmio_read(&mdev->mmio, val 58 drivers/misc/mic/host/mic_x100.c "Reading 0x%x from scratch pad index %d\n", val, idx); val 59 drivers/misc/mic/host/mic_x100.c return val; val 196 drivers/misc/mic/scif/scif_fence.c static int _scif_prog_signal(scif_epd_t epd, dma_addr_t dst, u64 val) val 229 drivers/misc/mic/scif/scif_fence.c tx = ddev->device_prep_dma_imm_data(chan, dst, val, 0); val 239 drivers/misc/mic/scif/scif_fence.c status->val = val; val 242 drivers/misc/mic/scif/scif_fence.c src += offsetof(struct scif_status, val); val 243 drivers/misc/mic/scif/scif_fence.c tx = ddev->device_prep_dma_memcpy(chan, dst, src, sizeof(val), val 276 drivers/misc/mic/scif/scif_fence.c src - offsetof(struct scif_status, val)); val 293 drivers/misc/mic/scif/scif_fence.c int scif_prog_signal(scif_epd_t epd, off_t offset, u64 val, val 329 drivers/misc/mic/scif/scif_fence.c *dst_virt = val; val 332 drivers/misc/mic/scif/scif_fence.c err = _scif_prog_signal(epd, dst_dma_addr, val); val 204 drivers/misc/mic/scif/scif_rma.h u64 val; val 351 drivers/misc/mic/scif/scif_rma.h int scif_prog_signal(scif_epd_t epd, off_t offset, u64 val, val 8 drivers/misc/ocxl/config.c #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit))) val 9 drivers/misc/ocxl/config.c #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s) val 76 drivers/misc/ocxl/config.c u16 val; val 89 drivers/misc/ocxl/config.c pci_read_config_word(dev, pos + PCI_PASID_CAP, &val); val 90 drivers/misc/ocxl/config.c fn->max_pasid_log = EXTRACT_BITS(val, 8, 12); val 117 drivers/misc/ocxl/config.c u32 val; val 126 drivers/misc/ocxl/config.c pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val); val 127 drivers/misc/ocxl/config.c afu_present = EXTRACT_BIT(val, 31); val 133 drivers/misc/ocxl/config.c fn->max_afu_index = EXTRACT_BITS(val, 24, 29); val 249 drivers/misc/ocxl/config.c u32 val; val 260 drivers/misc/ocxl/config.c pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val); val 261 drivers/misc/ocxl/config.c while (!EXTRACT_BIT(val, 31)) { val 269 drivers/misc/ocxl/config.c pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val); val 348 drivers/misc/ocxl/config.c u32 val, *ptr; val 352 drivers/misc/ocxl/config.c rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val); val 356 drivers/misc/ocxl/config.c *ptr = le32_to_cpu((__force __le32) val); val 366 drivers/misc/ocxl/config.c u32 val; val 371 drivers/misc/ocxl/config.c rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val); val 374 drivers/misc/ocxl/config.c afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2); val 375 drivers/misc/ocxl/config.c afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16; val 377 drivers/misc/ocxl/config.c rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val); val 380 drivers/misc/ocxl/config.c afu->global_mmio_offset += (u64) val << 32; val 382 drivers/misc/ocxl/config.c rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val); val 385 drivers/misc/ocxl/config.c afu->global_mmio_size = val; val 390 drivers/misc/ocxl/config.c rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val); val 393 drivers/misc/ocxl/config.c afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2); val 394 drivers/misc/ocxl/config.c afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16; val 396 drivers/misc/ocxl/config.c rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val); val 399 drivers/misc/ocxl/config.c afu->pp_mmio_offset += (u64) val << 32; val 401 drivers/misc/ocxl/config.c rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val); val 404 drivers/misc/ocxl/config.c afu->pp_mmio_stride = val; val 664 drivers/misc/ocxl/config.c u16 val; val 666 drivers/misc/ocxl/config.c val = actag_count & OCXL_DVSEC_ACTAG_MASK; val 667 drivers/misc/ocxl/config.c pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val); val 669 drivers/misc/ocxl/config.c val = actag_base & OCXL_DVSEC_ACTAG_MASK; val 670 drivers/misc/ocxl/config.c pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val); val 699 drivers/misc/ocxl/config.c u8 val; val 701 drivers/misc/ocxl/config.c pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val); val 703 drivers/misc/ocxl/config.c val |= 1; val 705 drivers/misc/ocxl/config.c val &= 0xFE; val 706 drivers/misc/ocxl/config.c pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val); val 712 drivers/misc/ocxl/config.c u32 val; val 757 drivers/misc/ocxl/config.c val = recv_cap >> 32; val 758 drivers/misc/ocxl/config.c pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val); val 759 drivers/misc/ocxl/config.c val = recv_cap & GENMASK(31, 0); val 760 drivers/misc/ocxl/config.c pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val); val 768 drivers/misc/ocxl/config.c &val); val 770 drivers/misc/ocxl/config.c *be32ptr = cpu_to_be32(val); val 772 drivers/misc/ocxl/config.c pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val); val 773 drivers/misc/ocxl/config.c recv_cap = (long) val << 32; val 774 drivers/misc/ocxl/config.c pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val); val 775 drivers/misc/ocxl/config.c recv_cap |= val; val 811 drivers/misc/ocxl/config.c u32 val; val 815 drivers/misc/ocxl/config.c &val); val 816 drivers/misc/ocxl/config.c if (EXTRACT_BIT(val, 20)) { val 823 drivers/misc/ocxl/config.c val &= ~OCXL_DVSEC_PASID_MASK; val 824 drivers/misc/ocxl/config.c val |= pasid & OCXL_DVSEC_PASID_MASK; val 825 drivers/misc/ocxl/config.c val |= BIT(20); val 828 drivers/misc/ocxl/config.c val); val 832 drivers/misc/ocxl/config.c &val); val 833 drivers/misc/ocxl/config.c while (EXTRACT_BIT(val, 20)) { val 843 drivers/misc/ocxl/config.c &val); val 852 drivers/misc/ocxl/config.c u32 val; val 854 drivers/misc/ocxl/config.c val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16; val 855 drivers/misc/ocxl/config.c val |= tag_count & OCXL_DVSEC_ACTAG_MASK; val 857 drivers/misc/ocxl/config.c val); val 8 drivers/misc/ocxl/mmio.c enum ocxl_endian endian, u32 *val) val 20 drivers/misc/ocxl/mmio.c *val = readl_be((char *)afu->global_mmio_ptr + offset); val 24 drivers/misc/ocxl/mmio.c *val = readl((char *)afu->global_mmio_ptr + offset); val 33 drivers/misc/ocxl/mmio.c enum ocxl_endian endian, u64 *val) val 45 drivers/misc/ocxl/mmio.c *val = readq_be((char *)afu->global_mmio_ptr + offset); val 49 drivers/misc/ocxl/mmio.c *val = readq((char *)afu->global_mmio_ptr + offset); val 58 drivers/misc/ocxl/mmio.c enum ocxl_endian endian, u32 val) val 70 drivers/misc/ocxl/mmio.c writel_be(val, (char *)afu->global_mmio_ptr + offset); val 74 drivers/misc/ocxl/mmio.c writel(val, (char *)afu->global_mmio_ptr + offset); val 84 drivers/misc/ocxl/mmio.c enum ocxl_endian endian, u64 val) val 96 drivers/misc/ocxl/mmio.c writeq_be(val, (char *)afu->global_mmio_ptr + offset); val 100 drivers/misc/ocxl/mmio.c writeq(val, (char *)afu->global_mmio_ptr + offset); val 257 drivers/misc/pci_endpoint_test.c u32 val; val 273 drivers/misc/pci_endpoint_test.c val = pci_endpoint_test_bar_readl(test, barno, j); val 274 drivers/misc/pci_endpoint_test.c if (val != 0xA0A0A0A0) val 283 drivers/misc/pci_endpoint_test.c u32 val; val 290 drivers/misc/pci_endpoint_test.c val = wait_for_completion_timeout(&test->irq_raised, val 292 drivers/misc/pci_endpoint_test.c if (!val) val 301 drivers/misc/pci_endpoint_test.c u32 val; val 311 drivers/misc/pci_endpoint_test.c val = wait_for_completion_timeout(&test->irq_raised, val 313 drivers/misc/pci_endpoint_test.c if (!val) val 303 drivers/misc/sgi-gru/gru_instructions.h unsigned long val; val 534 drivers/misc/sgi-gru/grukservices.c static inline void restore_present2(void *p, int val) val 537 drivers/misc/sgi-gru/grukservices.c mhdr->present = val; val 680 drivers/misc/sgi-gru/grukservices.c gru_gamer(cb, EOP_ERR_CSWAP, mqd->mq_gpa, XTYPE_DW, mqh.val, avalue, val 24 drivers/misc/sgi-gru/gruprocfs.c unsigned long val = atomic_long_read(v); val 26 drivers/misc/sgi-gru/gruprocfs.c seq_printf(s, "%16lu %s\n", val, id); val 323 drivers/misc/sram.c u32 val; val 329 drivers/misc/sram.c return regmap_read_poll_timeout(regmap, AT91_SECUMOD_RAMRDY, val, val 330 drivers/misc/sram.c val & AT91_SECUMOD_RAMRDY_READY, val 190 drivers/misc/tsl2550.c unsigned long val = simple_strtoul(buf, NULL, 10); val 193 drivers/misc/tsl2550.c if (val > 1) val 197 drivers/misc/tsl2550.c ret = tsl2550_set_power_state(client, val); val 222 drivers/misc/tsl2550.c unsigned long val = simple_strtoul(buf, NULL, 10); val 225 drivers/misc/tsl2550.c if (val > 1) val 232 drivers/misc/tsl2550.c ret = tsl2550_set_operating_mode(client, val); val 111 drivers/misc/vexpress-syscfg.c unsigned int *val) val 115 drivers/misc/vexpress-syscfg.c return vexpress_syscfg_exec(func, index, false, val); val 119 drivers/misc/vexpress-syscfg.c unsigned int val) val 123 drivers/misc/vexpress-syscfg.c return vexpress_syscfg_exec(func, index, true, &val); val 145 drivers/misc/vexpress-syscfg.c const __be32 *val = NULL; val 162 drivers/misc/vexpress-syscfg.c val = prop->value; val 171 drivers/misc/vexpress-syscfg.c energy_quirk[0] = *val; val 172 drivers/misc/vexpress-syscfg.c energy_quirk[2] = *val++; val 173 drivers/misc/vexpress-syscfg.c energy_quirk[1] = *val; val 174 drivers/misc/vexpress-syscfg.c energy_quirk[3] = cpu_to_be32(be32_to_cpup(val) + 1); val 175 drivers/misc/vexpress-syscfg.c val = energy_quirk; val 188 drivers/misc/vexpress-syscfg.c function = be32_to_cpup(val++); val 189 drivers/misc/vexpress-syscfg.c device = be32_to_cpup(val++); val 437 drivers/misc/vmw_balloon.c unsigned int val) val 440 drivers/misc/vmw_balloon.c atomic64_add(val, &b->stats->general_stat[stat]); val 454 drivers/misc/vmw_balloon.c unsigned int val) val 457 drivers/misc/vmw_balloon.c atomic64_add(val, &b->stats->page_stat[stat][size]); val 1240 drivers/mmc/core/block.c u32 val; val 1272 drivers/mmc/core/block.c val = brq->stop.resp[0] & CMD_ERRORS; val 1273 drivers/mmc/core/block.c oor_with_open_end = val & R1_OUT_OF_RANGE && !brq->mrq.sbc; val 1275 drivers/mmc/core/block.c if (val && !oor_with_open_end) val 2706 drivers/mmc/core/block.c static int mmc_dbg_card_status_get(void *data, u64 *val) val 2722 drivers/mmc/core/block.c *val = ret; val 198 drivers/mmc/core/debugfs.c static int mmc_clock_opt_get(void *data, u64 *val) val 202 drivers/mmc/core/debugfs.c *val = host->ios.clock; val 207 drivers/mmc/core/debugfs.c static int mmc_clock_opt_set(void *data, u64 val) val 212 drivers/mmc/core/debugfs.c if (val != 0 && (val > host->f_max || val < host->f_min)) val 216 drivers/mmc/core/debugfs.c mmc_set_clock(host, (unsigned int) val); val 1145 drivers/mmc/core/mmc.c u8 val; val 1155 drivers/mmc/core/mmc.c val = EXT_CSD_TIMING_HS; val 1157 drivers/mmc/core/mmc.c EXT_CSD_HS_TIMING, val, val 1196 drivers/mmc/core/mmc.c val = EXT_CSD_TIMING_HS400 | val 1199 drivers/mmc/core/mmc.c EXT_CSD_HS_TIMING, val, val 1237 drivers/mmc/core/mmc.c u8 val; val 1244 drivers/mmc/core/mmc.c val = EXT_CSD_TIMING_HS; val 1246 drivers/mmc/core/mmc.c val, card->ext_csd.generic_cmd6_time, 0, val 1274 drivers/mmc/core/mmc.c val = EXT_CSD_TIMING_HS200 | val 1277 drivers/mmc/core/mmc.c val, card->ext_csd.generic_cmd6_time, 0, val 1333 drivers/mmc/core/mmc.c u8 val; val 1377 drivers/mmc/core/mmc.c val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE; val 1380 drivers/mmc/core/mmc.c val, val 1391 drivers/mmc/core/mmc.c val = EXT_CSD_TIMING_HS400 | val 1394 drivers/mmc/core/mmc.c EXT_CSD_HS_TIMING, val, val 1435 drivers/mmc/core/mmc.c u8 val; val 1456 drivers/mmc/core/mmc.c val = EXT_CSD_TIMING_HS200 | val 1459 drivers/mmc/core/mmc.c EXT_CSD_HS_TIMING, val, val 978 drivers/mmc/core/mmc_ops.c u8 val = enable ? EXT_CSD_CMDQ_MODE_ENABLED : 0; val 985 drivers/mmc/core/mmc_ops.c val, card->ext_csd.generic_cmd6_time); val 383 drivers/mmc/core/sdio_io.c u8 val; val 391 drivers/mmc/core/sdio_io.c ret = mmc_io_rw_direct(func->card, 0, func->num, addr, 0, &val); val 397 drivers/mmc/core/sdio_io.c return val; val 445 drivers/mmc/core/sdio_io.c u8 val; val 448 drivers/mmc/core/sdio_io.c write_byte, &val); val 454 drivers/mmc/core/sdio_io.c return val; val 635 drivers/mmc/core/sdio_io.c unsigned char val; val 643 drivers/mmc/core/sdio_io.c ret = mmc_io_rw_direct(func->card, 0, 0, addr, 0, &val); val 649 drivers/mmc/core/sdio_io.c return val; val 104 drivers/mmc/host/alcor.c static void alcor_reset(struct alcor_sdmmc_host *host, u8 val) val 109 drivers/mmc/host/alcor.c alcor_write8(priv, val | AU6601_BUF_CTRL_RESET, val 112 drivers/mmc/host/alcor.c if (!(alcor_read8(priv, AU6601_REG_SW_RESET) & val)) val 546 drivers/mmc/host/atmel-mci.c u32 val; val 548 drivers/mmc/host/atmel-mci.c val = buf[ATMCI_DMA / 4]; val 550 drivers/mmc/host/atmel-mci.c val, val & 3, val 551 drivers/mmc/host/atmel-mci.c ((val >> 4) & 3) ? val 552 drivers/mmc/host/atmel-mci.c 1 << (((val >> 4) & 3) + 1) : 1, val 553 drivers/mmc/host/atmel-mci.c val & ATMCI_DMAEN ? " DMAEN" : ""); val 556 drivers/mmc/host/atmel-mci.c u32 val; val 558 drivers/mmc/host/atmel-mci.c val = buf[ATMCI_CFG / 4]; val 560 drivers/mmc/host/atmel-mci.c val, val 561 drivers/mmc/host/atmel-mci.c val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", val 562 drivers/mmc/host/atmel-mci.c val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", val 563 drivers/mmc/host/atmel-mci.c val & ATMCI_CFG_HSMODE ? " HSMODE" : "", val 564 drivers/mmc/host/atmel-mci.c val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); val 166 drivers/mmc/host/au1xmmc.c u32 val = __raw_readl(HOST_CONFIG(host)); val 167 drivers/mmc/host/au1xmmc.c val |= mask; val 168 drivers/mmc/host/au1xmmc.c __raw_writel(val, HOST_CONFIG(host)); val 174 drivers/mmc/host/au1xmmc.c u32 val = __raw_readl(HOST_CONFIG2(host)); val 176 drivers/mmc/host/au1xmmc.c __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); val 181 drivers/mmc/host/au1xmmc.c val &= ~SD_CONFIG2_DF; val 183 drivers/mmc/host/au1xmmc.c __raw_writel(val, HOST_CONFIG2(host)); val 189 drivers/mmc/host/au1xmmc.c u32 val = __raw_readl(HOST_CONFIG(host)); val 190 drivers/mmc/host/au1xmmc.c val &= ~mask; val 191 drivers/mmc/host/au1xmmc.c __raw_writel(val, HOST_CONFIG(host)); val 396 drivers/mmc/host/au1xmmc.c unsigned char *sg_ptr, val; val 423 drivers/mmc/host/au1xmmc.c val = sg_ptr[count]; val 425 drivers/mmc/host/au1xmmc.c __raw_writel((unsigned long)val, HOST_TXPORT(host)); val 453 drivers/mmc/host/au1xmmc.c u32 status, val; val 501 drivers/mmc/host/au1xmmc.c val = __raw_readl(HOST_RXPORT(host)); val 504 drivers/mmc/host/au1xmmc.c sg_ptr[count] = (unsigned char)(val & 0xFF); val 108 drivers/mmc/host/cavium-octeon.c static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val) val 110 drivers/mmc/host/cavium-octeon.c writeq(val, host->base + MIO_EMM_INT(host)); val 112 drivers/mmc/host/cavium-octeon.c writeq(val, host->base + MIO_EMM_INT_EN(host)); val 155 drivers/mmc/host/cavium-octeon.c u64 val; val 243 drivers/mmc/host/cavium-octeon.c val = readq(host->base + MIO_EMM_INT(host)); val 244 drivers/mmc/host/cavium-octeon.c writeq(val, host->base + MIO_EMM_INT(host)); val 30 drivers/mmc/host/cavium-thunderx.c static void thunder_mmc_int_enable(struct cvm_mmc_host *host, u64 val) val 32 drivers/mmc/host/cavium-thunderx.c writeq(val, host->base + MIO_EMM_INT(host)); val 33 drivers/mmc/host/cavium-thunderx.c writeq(val, host->base + MIO_EMM_INT_EN_SET(host)); val 691 drivers/mmc/host/cb710-mmc.c u32 val; val 700 drivers/mmc/host/cb710-mmc.c pci_read_config_dword(chip->pdev, 0x48, &val); val 701 drivers/mmc/host/cb710-mmc.c val = cb710_src_freq_mhz[(val >> 16) & 0xF]; val 702 drivers/mmc/host/cb710-mmc.c dev_dbg(cb710_slot_dev(slot), "source frequency: %dMHz\n", val); val 703 drivers/mmc/host/cb710-mmc.c val *= 1000000; val 706 drivers/mmc/host/cb710-mmc.c mmc->f_max = val; val 707 drivers/mmc/host/cb710-mmc.c mmc->f_min = val >> cb710_clock_divider_log2[CB710_MAX_DIVIDER_IDX]; val 203 drivers/mmc/host/cqhci.h void (*write_l)(struct cqhci_host *host, u32 val, int reg); val 211 drivers/mmc/host/cqhci.h static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) val 214 drivers/mmc/host/cqhci.h host->ops->write_l(host, val, reg); val 216 drivers/mmc/host/cqhci.h writel_relaxed(val, host->mmio + reg); val 828 drivers/mmc/host/davinci_mmc.c int val) val 833 drivers/mmc/host/davinci_mmc.c if (val) /* reset */ val 1063 drivers/mmc/host/davinci_mmc.c unsigned long val, void *data) val 1074 drivers/mmc/host/davinci_mmc.c if (val == CPUFREQ_POSTCHANGE) { val 35 drivers/mmc/host/dw_mmc-hi3798cv200.c u32 val; val 37 drivers/mmc/host/dw_mmc-hi3798cv200.c val = mci_readl(host, UHS_REG); val 40 drivers/mmc/host/dw_mmc-hi3798cv200.c val |= SDMMC_UHS_DDR; val 42 drivers/mmc/host/dw_mmc-hi3798cv200.c val &= ~SDMMC_UHS_DDR; val 43 drivers/mmc/host/dw_mmc-hi3798cv200.c mci_writel(host, UHS_REG, val); val 45 drivers/mmc/host/dw_mmc-hi3798cv200.c val = mci_readl(host, ENABLE_SHIFT); val 47 drivers/mmc/host/dw_mmc-hi3798cv200.c val |= SDMMC_ENABLE_PHASE; val 49 drivers/mmc/host/dw_mmc-hi3798cv200.c val &= ~SDMMC_ENABLE_PHASE; val 50 drivers/mmc/host/dw_mmc-hi3798cv200.c mci_writel(host, ENABLE_SHIFT, val); val 52 drivers/mmc/host/dw_mmc-hi3798cv200.c val = mci_readl(host, DDR_REG); val 54 drivers/mmc/host/dw_mmc-hi3798cv200.c val |= SDMMC_DDR_HS400; val 56 drivers/mmc/host/dw_mmc-hi3798cv200.c val &= ~SDMMC_DDR_HS400; val 57 drivers/mmc/host/dw_mmc-hi3798cv200.c mci_writel(host, DDR_REG, val); val 281 drivers/mmc/host/dw_mmc-k3.c unsigned int val; val 286 drivers/mmc/host/dw_mmc-k3.c val = set ? SDCARD_IO_SEL18 : 0; val 288 drivers/mmc/host/dw_mmc-k3.c SDCARD_IO_SEL18, val); val 290 drivers/mmc/host/dw_mmc-k3.c dev_err(host->dev, "sel18 %u error\n", val); val 580 drivers/mmc/host/dw_mmc.c u32 val; val 602 drivers/mmc/host/dw_mmc.c if (readl_poll_timeout_atomic(&desc->des0, val, val 603 drivers/mmc/host/dw_mmc.c !(val & IDMAC_DES0_OWN), val 652 drivers/mmc/host/dw_mmc.c u32 val; val 674 drivers/mmc/host/dw_mmc.c if (readl_poll_timeout_atomic(&desc->des0, val, val 675 drivers/mmc/host/dw_mmc.c IDMAC_OWN_CLR64(val), val 175 drivers/mmc/host/jz4740_mmc.c uint32_t val) val 178 drivers/mmc/host/jz4740_mmc.c return writel(val, host->base + JZ_REG_MMC_IMASK); val 180 drivers/mmc/host/jz4740_mmc.c return writew(val, host->base + JZ_REG_MMC_IMASK); val 184 drivers/mmc/host/jz4740_mmc.c uint32_t val) val 187 drivers/mmc/host/jz4740_mmc.c writel(val, host->base + JZ_REG_MMC_IREG); val 189 drivers/mmc/host/jz4740_mmc.c writew(val, host->base + JZ_REG_MMC_IREG); val 375 drivers/mmc/host/jz4740_mmc.c uint16_t val = JZ_MMC_STRPCL_CLOCK_START; val 378 drivers/mmc/host/jz4740_mmc.c val |= JZ_MMC_STRPCL_START_OP; val 380 drivers/mmc/host/jz4740_mmc.c writew(val, host->base + JZ_REG_MMC_STRPCL); val 494 drivers/mmc/host/meson-gx-mmc.c unsigned int val = readl(host->regs + host->data->adjust); val 496 drivers/mmc/host/meson-gx-mmc.c val &= ~ADJUST_ADJ_EN; val 497 drivers/mmc/host/meson-gx-mmc.c writel(val, host->regs + host->data->adjust); val 502 drivers/mmc/host/meson-gx-mmc.c unsigned int val; val 506 drivers/mmc/host/meson-gx-mmc.c val = readl(host->regs + host->data->adjust); val 507 drivers/mmc/host/meson-gx-mmc.c val &= ~ADJUST_ADJ_DELAY_MASK; val 508 drivers/mmc/host/meson-gx-mmc.c writel(val, host->regs + host->data->adjust); val 514 drivers/mmc/host/meson-gx-mmc.c unsigned int val, dly, max_dly, i; val 521 drivers/mmc/host/meson-gx-mmc.c val = readl(host->regs + host->data->adjust); val 522 drivers/mmc/host/meson-gx-mmc.c val |= ADJUST_ADJ_EN; val 523 drivers/mmc/host/meson-gx-mmc.c writel(val, host->regs + host->data->adjust); val 526 drivers/mmc/host/meson-gx-mmc.c dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; val 531 drivers/mmc/host/meson-gx-mmc.c val &= ~ADJUST_ADJ_DELAY_MASK; val 532 drivers/mmc/host/meson-gx-mmc.c val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); val 533 drivers/mmc/host/meson-gx-mmc.c writel(val, host->regs + host->data->adjust); val 582 drivers/mmc/host/meson-gx-mmc.c u32 bus_width, val; val 638 drivers/mmc/host/meson-gx-mmc.c val = readl(host->regs + SD_EMMC_CFG); val 639 drivers/mmc/host/meson-gx-mmc.c val &= ~CFG_BUS_WIDTH_MASK; val 640 drivers/mmc/host/meson-gx-mmc.c val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); val 641 drivers/mmc/host/meson-gx-mmc.c writel(val, host->regs + SD_EMMC_CFG); val 648 drivers/mmc/host/meson-gx-mmc.c dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); val 126 drivers/mmc/host/meson-mx-sdio.c u32 val) val 133 drivers/mmc/host/meson-mx-sdio.c regval |= (val & mask); val 546 drivers/mmc/host/mtk-sd.c u32 val = readl(reg); val 548 drivers/mmc/host/mtk-sd.c val |= bs; val 549 drivers/mmc/host/mtk-sd.c writel(val, reg); val 554 drivers/mmc/host/mtk-sd.c u32 val = readl(reg); val 556 drivers/mmc/host/mtk-sd.c val &= ~bs; val 557 drivers/mmc/host/mtk-sd.c writel(val, reg); val 560 drivers/mmc/host/mtk-sd.c static void sdr_set_field(void __iomem *reg, u32 field, u32 val) val 565 drivers/mmc/host/mtk-sd.c tv |= ((val) << (ffs((unsigned int)field) - 1)); val 569 drivers/mmc/host/mtk-sd.c static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) val 573 drivers/mmc/host/mtk-sd.c *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); val 578 drivers/mmc/host/mtk-sd.c u32 val; val 588 drivers/mmc/host/mtk-sd.c val = readl(host->base + MSDC_INT); val 589 drivers/mmc/host/mtk-sd.c writel(val, host->base + MSDC_INT); val 1309 drivers/mmc/host/mtk-sd.c u32 val = readl(host->base + SDC_CFG); val 1311 drivers/mmc/host/mtk-sd.c val &= ~SDC_CFG_BUSWIDTH; val 1316 drivers/mmc/host/mtk-sd.c val |= (MSDC_BUS_1BITS << 16); val 1319 drivers/mmc/host/mtk-sd.c val |= (MSDC_BUS_4BITS << 16); val 1322 drivers/mmc/host/mtk-sd.c val |= (MSDC_BUS_8BITS << 16); val 1326 drivers/mmc/host/mtk-sd.c writel(val, host->base + SDC_CFG); val 1474 drivers/mmc/host/mtk-sd.c u32 val; val 1485 drivers/mmc/host/mtk-sd.c val = readl(host->base + MSDC_INT); val 1486 drivers/mmc/host/mtk-sd.c writel(val, host->base + MSDC_INT); val 1607 drivers/mmc/host/mtk-sd.c u32 val; val 1618 drivers/mmc/host/mtk-sd.c val = readl(host->base + MSDC_INT); val 1619 drivers/mmc/host/mtk-sd.c writel(val, host->base + MSDC_INT); val 2122 drivers/mmc/host/mtk-sd.c int val; val 2130 drivers/mmc/host/mtk-sd.c val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; val 2132 drivers/mmc/host/mtk-sd.c return !!val; val 2134 drivers/mmc/host/mtk-sd.c return !val; val 53 drivers/mmc/host/mvsdio.c #define mvsd_write(offs, val) writel(val, iobase + (offs)) val 397 drivers/mmc/host/mvsdio.c u16 val[2] = {0, 0}; val 398 drivers/mmc/host/mvsdio.c val[0] = mvsd_read(MVSD_FIFO); val 399 drivers/mmc/host/mvsdio.c val[1] = mvsd_read(MVSD_FIFO); val 400 drivers/mmc/host/mvsdio.c memcpy(p, ((void *)&val) + 4 - s, s); val 438 drivers/mmc/host/mvsdio.c u16 val[2] = {0, 0}; val 439 drivers/mmc/host/mvsdio.c memcpy(((void *)&val) + 4 - s, p, s); val 440 drivers/mmc/host/mvsdio.c mvsd_write(MVSD_FIFO, val[0]); val 441 drivers/mmc/host/mvsdio.c mvsd_write(MVSD_FIFO, val[1]); val 210 drivers/mmc/host/mxcmmc.c static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg) val 213 drivers/mmc/host/mxcmmc.c iowrite32be(val, host->base + reg); val 215 drivers/mmc/host/mxcmmc.c writel(val, host->base + reg); val 226 drivers/mmc/host/mxcmmc.c static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg) val 229 drivers/mmc/host/mxcmmc.c iowrite32be(val, host->base + reg); val 231 drivers/mmc/host/mxcmmc.c writew(val, host->base + reg); val 361 drivers/mmc/host/mxs-mmc.c u32 ctrl0, cmd0, cmd1, val; val 425 drivers/mmc/host/mxs-mmc.c val = readl(ssp->base + HW_SSP_TIMING(ssp)); val 426 drivers/mmc/host/mxs-mmc.c val &= ~(BM_SSP_TIMING_TIMEOUT); val 427 drivers/mmc/host/mxs-mmc.c val |= BF_SSP(timeout, TIMING_TIMEOUT); val 428 drivers/mmc/host/mxs-mmc.c writel(val, ssp->base + HW_SSP_TIMING(ssp)); val 81 drivers/mmc/host/omap.c #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) val 161 drivers/mmc/host/omap_hsmmc.c #define OMAP_HSMMC_WRITE(base, reg, val) \ val 162 drivers/mmc/host/omap_hsmmc.c __raw_writel((val), (base) + OMAP_HSMMC_##reg) val 56 drivers/mmc/host/renesas_sdhi_core.c u32 val; val 64 drivers/mmc/host/renesas_sdhi_core.c val = (width == 32) ? 0x0001 : 0x0000; val 67 drivers/mmc/host/renesas_sdhi_core.c val = (width == 32) ? 0x0000 : 0x0001; val 72 drivers/mmc/host/renesas_sdhi_core.c val = 0x0000; val 74 drivers/mmc/host/renesas_sdhi_core.c val = 0x0101; val 76 drivers/mmc/host/renesas_sdhi_core.c val = 0x0001; val 83 drivers/mmc/host/renesas_sdhi_core.c sd_ctrl_write16(host, HOST_MODE, val); val 283 drivers/mmc/host/renesas_sdhi_core.c int addr, u32 val) val 285 drivers/mmc/host/renesas_sdhi_core.c writel(val, priv->scc_ctl + (addr << host->bus_shift)); val 131 drivers/mmc/host/renesas_sdhi_internal_dmac.c int addr, u64 val) val 133 drivers/mmc/host/renesas_sdhi_internal_dmac.c writeq(val, host->ctl + addr); val 154 drivers/mmc/host/renesas_sdhi_internal_dmac.c u64 val = RST_DTRANRST1 | RST_DTRANRST0; val 159 drivers/mmc/host/renesas_sdhi_internal_dmac.c RST_RESERVED_BITS & ~val); val 161 drivers/mmc/host/renesas_sdhi_internal_dmac.c RST_RESERVED_BITS | val); val 679 drivers/mmc/host/rtsx_pci_sdmmc.c u8 val = 0; val 682 drivers/mmc/host/rtsx_pci_sdmmc.c err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); val 683 drivers/mmc/host/rtsx_pci_sdmmc.c if (val & SD_DATA_IDLE) val 1090 drivers/mmc/host/rtsx_pci_sdmmc.c u32 val; val 1100 drivers/mmc/host/rtsx_pci_sdmmc.c val = rtsx_pci_readl(pcr, RTSX_BIPR); val 1101 drivers/mmc/host/rtsx_pci_sdmmc.c dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); val 1102 drivers/mmc/host/rtsx_pci_sdmmc.c if (val & SD_WRITE_PROTECT) val 1115 drivers/mmc/host/rtsx_pci_sdmmc.c u32 val; val 1125 drivers/mmc/host/rtsx_pci_sdmmc.c val = rtsx_pci_card_exist(pcr); val 1126 drivers/mmc/host/rtsx_pci_sdmmc.c dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); val 1127 drivers/mmc/host/rtsx_pci_sdmmc.c if (val & SD_EXIST) val 1172 drivers/mmc/host/rtsx_pci_sdmmc.c u8 stat, mask, val; val 1194 drivers/mmc/host/rtsx_pci_sdmmc.c val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | val 1196 drivers/mmc/host/rtsx_pci_sdmmc.c if ((stat & mask) != val) { val 79 drivers/mmc/host/rtsx_usb_sdmmc.c u8 val = 0; val 81 drivers/mmc/host/rtsx_usb_sdmmc.c rtsx_usb_ep0_read_register(ucr, SD_STAT1, &val); val 82 drivers/mmc/host/rtsx_usb_sdmmc.c dev_dbg(sdmmc_dev(host), "SD_STAT1: 0x%x\n", val); val 83 drivers/mmc/host/rtsx_usb_sdmmc.c rtsx_usb_ep0_read_register(ucr, SD_STAT2, &val); val 84 drivers/mmc/host/rtsx_usb_sdmmc.c dev_dbg(sdmmc_dev(host), "SD_STAT2: 0x%x\n", val); val 85 drivers/mmc/host/rtsx_usb_sdmmc.c rtsx_usb_ep0_read_register(ucr, SD_BUS_STAT, &val); val 86 drivers/mmc/host/rtsx_usb_sdmmc.c dev_dbg(sdmmc_dev(host), "SD_BUS_STAT: 0x%x\n", val); val 658 drivers/mmc/host/rtsx_usb_sdmmc.c u8 val = 0; val 662 drivers/mmc/host/rtsx_usb_sdmmc.c SD_DATA_STATE, &val); val 663 drivers/mmc/host/rtsx_usb_sdmmc.c if (val & SD_DATA_IDLE) val 757 drivers/mmc/host/rtsx_usb_sdmmc.c u16 val; val 765 drivers/mmc/host/rtsx_usb_sdmmc.c err = rtsx_usb_get_card_status(ucr, &val); val 774 drivers/mmc/host/rtsx_usb_sdmmc.c if (val & SD_WP) val 785 drivers/mmc/host/rtsx_usb_sdmmc.c u16 val; val 793 drivers/mmc/host/rtsx_usb_sdmmc.c err = rtsx_usb_get_card_status(ucr, &val); val 801 drivers/mmc/host/rtsx_usb_sdmmc.c if (val & SD_CD) { val 1330 drivers/mmc/host/s3cmci.c unsigned long val, void *data) val 1341 drivers/mmc/host/s3cmci.c if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) || val 1342 drivers/mmc/host/s3cmci.c (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) { val 260 drivers/mmc/host/sdhci-acpi.c u32 val = 0; val 266 drivers/mmc/host/sdhci-acpi.c &val)) { val 271 drivers/mmc/host/sdhci-acpi.c if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) val 274 drivers/mmc/host/sdhci-acpi.c val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; val 277 drivers/mmc/host/sdhci-acpi.c val)) { val 60 drivers/mmc/host/sdhci-bcm-kona.c unsigned int val; val 67 drivers/mmc/host/sdhci-bcm-kona.c val = sdhci_readl(host, KONA_SDHOST_CORECTRL); val 68 drivers/mmc/host/sdhci-bcm-kona.c val |= KONA_SDHOST_RESET; val 69 drivers/mmc/host/sdhci-bcm-kona.c sdhci_writel(host, val, KONA_SDHOST_CORECTRL); val 79 drivers/mmc/host/sdhci-bcm-kona.c val = sdhci_readl(host, KONA_SDHOST_CORECTRL); val 80 drivers/mmc/host/sdhci-bcm-kona.c val &= ~KONA_SDHOST_RESET; val 89 drivers/mmc/host/sdhci-bcm-kona.c sdhci_writel(host, val, KONA_SDHOST_CORECTRL); val 96 drivers/mmc/host/sdhci-bcm-kona.c unsigned int val; val 99 drivers/mmc/host/sdhci-bcm-kona.c val = sdhci_readl(host, KONA_SDHOST_COREIMR); val 100 drivers/mmc/host/sdhci-bcm-kona.c val |= KONA_SDHOST_IP; val 101 drivers/mmc/host/sdhci-bcm-kona.c sdhci_writel(host, val, KONA_SDHOST_COREIMR); val 104 drivers/mmc/host/sdhci-bcm-kona.c val = sdhci_readl(host, KONA_SDHOST_CORECTRL); val 105 drivers/mmc/host/sdhci-bcm-kona.c val |= KONA_SDHOST_EN; val 114 drivers/mmc/host/sdhci-bcm-kona.c sdhci_writel(host, val, KONA_SDHOST_CORECTRL); val 127 drivers/mmc/host/sdhci-bcm-kona.c u32 val; val 138 drivers/mmc/host/sdhci-bcm-kona.c val = sdhci_readl(host, KONA_SDHOST_CORESTAT); val 145 drivers/mmc/host/sdhci-bcm-kona.c val = (val & ~KONA_SDHOST_WP) | val 148 drivers/mmc/host/sdhci-bcm-kona.c val |= KONA_SDHOST_CD_SW; val 149 drivers/mmc/host/sdhci-bcm-kona.c sdhci_writel(host, val, KONA_SDHOST_CORESTAT); val 151 drivers/mmc/host/sdhci-bcm-kona.c val &= ~KONA_SDHOST_CD_SW; val 152 drivers/mmc/host/sdhci-bcm-kona.c sdhci_writel(host, val, KONA_SDHOST_CORESTAT); val 133 drivers/mmc/host/sdhci-cadence.c u32 val; val 138 drivers/mmc/host/sdhci-cadence.c &val); val 143 drivers/mmc/host/sdhci-cadence.c p->data = val; val 248 drivers/mmc/host/sdhci-cadence.c static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) val 255 drivers/mmc/host/sdhci-cadence.c if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) val 260 drivers/mmc/host/sdhci-cadence.c tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val); val 297 drivers/mmc/host/sdhci-esdhc-imx.c static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) val 302 drivers/mmc/host/sdhci-esdhc-imx.c writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); val 309 drivers/mmc/host/sdhci-esdhc-imx.c u32 val = readl(host->ioaddr + reg); val 312 drivers/mmc/host/sdhci-esdhc-imx.c u32 fsl_prss = val; val 314 drivers/mmc/host/sdhci-esdhc-imx.c val = fsl_prss & 0x000FFFFF; val 316 drivers/mmc/host/sdhci-esdhc-imx.c val |= (fsl_prss & 0x0F000000) >> 4; val 318 drivers/mmc/host/sdhci-esdhc-imx.c val |= (fsl_prss & 0x00800000) << 1; val 324 drivers/mmc/host/sdhci-esdhc-imx.c val &= 0xffff0000; val 333 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_CAN_DO_ADMA1) { val 334 drivers/mmc/host/sdhci-esdhc-imx.c val &= ~SDHCI_CAN_DO_ADMA1; val 335 drivers/mmc/host/sdhci-esdhc-imx.c val |= SDHCI_CAN_DO_ADMA2; val 342 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; val 345 drivers/mmc/host/sdhci-esdhc-imx.c val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 val 351 drivers/mmc/host/sdhci-esdhc-imx.c val |= SDHCI_SUPPORT_HS400; val 359 drivers/mmc/host/sdhci-esdhc-imx.c val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 val 365 drivers/mmc/host/sdhci-esdhc-imx.c val = 0; val 366 drivers/mmc/host/sdhci-esdhc-imx.c val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; val 367 drivers/mmc/host/sdhci-esdhc-imx.c val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; val 368 drivers/mmc/host/sdhci-esdhc-imx.c val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; val 372 drivers/mmc/host/sdhci-esdhc-imx.c if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { val 373 drivers/mmc/host/sdhci-esdhc-imx.c val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; val 374 drivers/mmc/host/sdhci-esdhc-imx.c val |= SDHCI_INT_ADMA_ERROR; val 382 drivers/mmc/host/sdhci-esdhc-imx.c ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { val 383 drivers/mmc/host/sdhci-esdhc-imx.c val &= ~SDHCI_INT_RESPONSE; val 390 drivers/mmc/host/sdhci-esdhc-imx.c return val; val 393 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) val 401 drivers/mmc/host/sdhci-esdhc-imx.c if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { val 417 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_INT_ADMA_ERROR) { val 418 drivers/mmc/host/sdhci-esdhc-imx.c val &= ~SDHCI_INT_ADMA_ERROR; val 419 drivers/mmc/host/sdhci-esdhc-imx.c val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; val 425 drivers/mmc/host/sdhci-esdhc-imx.c && (val & SDHCI_INT_DATA_END))) { val 441 drivers/mmc/host/sdhci-esdhc-imx.c writel(val, host->ioaddr + reg); val 449 drivers/mmc/host/sdhci-esdhc-imx.c u32 val; val 463 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); val 464 drivers/mmc/host/sdhci-esdhc-imx.c if (val & ESDHC_VENDOR_SPEC_VSELECT) val 469 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + ESDHC_MIX_CTRL); val 472 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); val 475 drivers/mmc/host/sdhci-esdhc-imx.c if (val & ESDHC_MIX_CTRL_EXE_TUNE) val 477 drivers/mmc/host/sdhci-esdhc-imx.c if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) val 504 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) val 513 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_CLOCK_CARD_EN) val 521 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_CTRL_VDD_180) val 528 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_CTRL_TUNED_CLK) { val 539 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_CTRL_TUNED_CLK) { val 547 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_CTRL_EXEC_TUNING) { val 574 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_TRNS_AUTO_CMD23) { val 575 drivers/mmc/host/sdhci-esdhc-imx.c val &= ~SDHCI_TRNS_AUTO_CMD23; val 576 drivers/mmc/host/sdhci-esdhc-imx.c val |= ESDHC_MIX_CTRL_AC23EN; val 578 drivers/mmc/host/sdhci-esdhc-imx.c m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); val 586 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_TRNS_DMA) val 600 drivers/mmc/host/sdhci-esdhc-imx.c imx_data->scratchpad = val; val 605 drivers/mmc/host/sdhci-esdhc-imx.c val |= SDHCI_CMD_ABORTCMD; val 612 drivers/mmc/host/sdhci-esdhc-imx.c writel(val << 16, val 615 drivers/mmc/host/sdhci-esdhc-imx.c writel(val << 16 | imx_data->scratchpad, val 619 drivers/mmc/host/sdhci-esdhc-imx.c val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); val 622 drivers/mmc/host/sdhci-esdhc-imx.c esdhc_clrset_le(host, 0xffff, val, reg); val 628 drivers/mmc/host/sdhci-esdhc-imx.c u32 val; val 632 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + reg); val 634 drivers/mmc/host/sdhci-esdhc-imx.c ret = val & SDHCI_CTRL_LED; val 635 drivers/mmc/host/sdhci-esdhc-imx.c ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; val 636 drivers/mmc/host/sdhci-esdhc-imx.c ret |= (val & ESDHC_CTRL_4BITBUS); val 637 drivers/mmc/host/sdhci-esdhc-imx.c ret |= (val & ESDHC_CTRL_8BITBUS) << 3; val 644 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) val 660 drivers/mmc/host/sdhci-esdhc-imx.c new_val = val & SDHCI_CTRL_LED; val 666 drivers/mmc/host/sdhci-esdhc-imx.c new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; val 680 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_RESET_DATA) val 684 drivers/mmc/host/sdhci-esdhc-imx.c esdhc_clrset_le(host, 0xff, val, reg); val 687 drivers/mmc/host/sdhci-esdhc-imx.c if (val & SDHCI_RESET_ALL) { val 711 drivers/mmc/host/sdhci-esdhc-imx.c } else if (val & SDHCI_RESET_DATA) { val 746 drivers/mmc/host/sdhci-esdhc-imx.c u32 temp, val; val 749 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); val 750 drivers/mmc/host/sdhci-esdhc-imx.c writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, val 765 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + ESDHC_DLL_CTRL); val 766 drivers/mmc/host/sdhci-esdhc-imx.c writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); val 768 drivers/mmc/host/sdhci-esdhc-imx.c writel(val, host->ioaddr + ESDHC_DLL_CTRL); val 807 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); val 808 drivers/mmc/host/sdhci-esdhc-imx.c writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, val 868 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) val 879 drivers/mmc/host/sdhci-esdhc-imx.c writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); val 882 drivers/mmc/host/sdhci-esdhc-imx.c val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); val 45 drivers/mmc/host/sdhci-iproc.c u32 val = readl(host->ioaddr + reg); val 48 drivers/mmc/host/sdhci-iproc.c mmc_hostname(host->mmc), reg, val); val 49 drivers/mmc/host/sdhci-iproc.c return val; val 56 drivers/mmc/host/sdhci-iproc.c u32 val; val 61 drivers/mmc/host/sdhci-iproc.c val = iproc_host->shadow_cmd; val 65 drivers/mmc/host/sdhci-iproc.c val = iproc_host->shadow_blk; val 67 drivers/mmc/host/sdhci-iproc.c val = sdhci_iproc_readl(host, (reg & ~3)); val 69 drivers/mmc/host/sdhci-iproc.c word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff; val 75 drivers/mmc/host/sdhci-iproc.c u32 val = sdhci_iproc_readl(host, (reg & ~3)); val 76 drivers/mmc/host/sdhci-iproc.c u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff; val 80 drivers/mmc/host/sdhci-iproc.c static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg) val 83 drivers/mmc/host/sdhci-iproc.c mmc_hostname(host->mmc), reg, val); val 85 drivers/mmc/host/sdhci-iproc.c writel(val, host->ioaddr + reg); val 115 drivers/mmc/host/sdhci-iproc.c static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg) val 140 drivers/mmc/host/sdhci-iproc.c newval = (oldval & ~mask) | (val << word_shift); val 156 drivers/mmc/host/sdhci-iproc.c static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg) val 161 drivers/mmc/host/sdhci-iproc.c u32 newval = (oldval & ~mask) | (val << byte_shift); val 122 drivers/mmc/host/sdhci-msm.c #define msm_host_writel(msm_host, val, host, offset) \ val 123 drivers/mmc/host/sdhci-msm.c msm_host->var_ops->msm_writel_relaxed(val, host, offset) val 217 drivers/mmc/host/sdhci-msm.c void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host, val 287 drivers/mmc/host/sdhci-msm.c static void sdhci_msm_mci_variant_writel_relaxed(u32 val, val 293 drivers/mmc/host/sdhci-msm.c writel_relaxed(val, msm_host->core_mem + offset); val 296 drivers/mmc/host/sdhci-msm.c static void sdhci_msm_v5_variant_writel_relaxed(u32 val, val 299 drivers/mmc/host/sdhci-msm.c writel_relaxed(val, host->ioaddr + offset); val 1312 drivers/mmc/host/sdhci-msm.c u32 val = SWITCHABLE_SIGNALING_VOLTAGE; val 1327 drivers/mmc/host/sdhci-msm.c val = msm_host_readl(msm_host, host, val 1330 drivers/mmc/host/sdhci-msm.c !(val & SWITCHABLE_SIGNALING_VOLTAGE)) { val 1583 drivers/mmc/host/sdhci-msm.c static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg) val 1591 drivers/mmc/host/sdhci-msm.c req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW : val 1595 drivers/mmc/host/sdhci-msm.c if (host->pwr && (val & SDHCI_RESET_ALL)) val 1599 drivers/mmc/host/sdhci-msm.c req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON; val 1602 drivers/mmc/host/sdhci-msm.c msm_host->transfer_mode = val; val 1608 drivers/mmc/host/sdhci-msm.c SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 && val 1609 drivers/mmc/host/sdhci-msm.c SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK) val 1628 drivers/mmc/host/sdhci-msm.c static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg) val 1632 drivers/mmc/host/sdhci-msm.c req_type = __sdhci_msm_check_write(host, val, reg); val 1633 drivers/mmc/host/sdhci-msm.c writew_relaxed(val, host->ioaddr + reg); val 1640 drivers/mmc/host/sdhci-msm.c static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg) val 1644 drivers/mmc/host/sdhci-msm.c req_type = __sdhci_msm_check_write(host, val, reg); val 1646 drivers/mmc/host/sdhci-msm.c writeb_relaxed(val, host->ioaddr + reg); val 41 drivers/mmc/host/sdhci-of-arasan.c #define HIWORD_UPDATE(val, mask, shift) \ val 42 drivers/mmc/host/sdhci-of-arasan.c ((val) << (shift) | (mask) << ((shift) + 16)) val 137 drivers/mmc/host/sdhci-of-arasan.c u32 val) val 158 drivers/mmc/host/sdhci-of-arasan.c HIWORD_UPDATE(val, GENMASK(width, 0), val 163 drivers/mmc/host/sdhci-of-arasan.c val << shift); val 396 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) val 400 drivers/mmc/host/sdhci-of-esdhc.c value = esdhc_writel_fixup(host, reg, val, 0); val 404 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) val 408 drivers/mmc/host/sdhci-of-esdhc.c value = esdhc_writel_fixup(host, reg, val, 0); val 412 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) val 421 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_writew_fixup(host, reg, val, value); val 438 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) val 447 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_writew_fixup(host, reg, val, value); val 464 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) val 471 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_writeb_fixup(host, reg, val, value); val 475 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) val 482 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_writeb_fixup(host, reg, val, value); val 565 drivers/mmc/host/sdhci-of-esdhc.c u32 val; val 568 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); val 571 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_CLOCK_SDCLKEN; val 573 drivers/mmc/host/sdhci-of-esdhc.c val &= ~ESDHC_CLOCK_SDCLKEN; val 575 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); val 579 drivers/mmc/host/sdhci-of-esdhc.c val = ESDHC_CLOCK_STABLE; val 583 drivers/mmc/host/sdhci-of-esdhc.c if (sdhci_readl(host, ESDHC_PRSSTAT) & val) val 737 drivers/mmc/host/sdhci-of-esdhc.c u32 val, bus_width = 0; val 754 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_PROCTL); val 755 drivers/mmc/host/sdhci-of-esdhc.c bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK; val 766 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_PROCTL); val 767 drivers/mmc/host/sdhci-of-esdhc.c val &= ~ESDHC_CTRL_BUSWIDTH_MASK; val 768 drivers/mmc/host/sdhci-of-esdhc.c val |= bus_width; val 769 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_PROCTL); val 781 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_TBCTL); val 782 drivers/mmc/host/sdhci-of-esdhc.c val &= ~ESDHC_TB_EN; val 783 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_TBCTL); val 790 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_DLLCFG1); val 791 drivers/mmc/host/sdhci-of-esdhc.c val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; val 792 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_DLLCFG1); val 822 drivers/mmc/host/sdhci-of-esdhc.c u32 val; val 831 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_PROCTL); val 835 drivers/mmc/host/sdhci-of-esdhc.c val &= ~ESDHC_VOLT_SEL; val 836 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_PROCTL); val 848 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_VOLT_SEL; val 849 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_PROCTL); val 858 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_VOLT_SEL; val 859 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_PROCTL); val 887 drivers/mmc/host/sdhci-of-esdhc.c u32 val; val 891 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_DMA_SYSCTL); val 892 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_FLUSH_ASYNC_FIFO; val 893 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_DMA_SYSCTL); val 895 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_TBCTL); val 897 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_TB_EN; val 899 drivers/mmc/host/sdhci-of-esdhc.c val &= ~ESDHC_TB_EN; val 900 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_TBCTL); val 911 drivers/mmc/host/sdhci-of-esdhc.c u32 val; val 920 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_TBCTL); val 921 drivers/mmc/host/sdhci-of-esdhc.c val &= ~(0xf << 8); val 922 drivers/mmc/host/sdhci-of-esdhc.c val |= 8 << 8; val 923 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_TBCTL); val 928 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_TBCTL); val 929 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_TBCTL); val 934 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_TBSTAT); val 935 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_TBSTAT); val 947 drivers/mmc/host/sdhci-of-esdhc.c tbstat_7_0 = val & 0xff; val 948 drivers/mmc/host/sdhci-of-esdhc.c tbstat_15_8 = (val >> 8) & 0xff; val 965 drivers/mmc/host/sdhci-of-esdhc.c u32 val; val 969 drivers/mmc/host/sdhci-of-esdhc.c val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) & val 971 drivers/mmc/host/sdhci-of-esdhc.c val |= window_end & ESDHC_WNDW_END_PTR_MASK; val 972 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_TBPTR); val 975 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_TBCTL); val 976 drivers/mmc/host/sdhci-of-esdhc.c val &= ~ESDHC_TB_MODE_MASK; val 977 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_TB_MODE_SW; val 978 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_TBCTL); val 995 drivers/mmc/host/sdhci-of-esdhc.c u32 val; val 1014 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_TBCTL); val 1015 drivers/mmc/host/sdhci-of-esdhc.c val &= ~ESDHC_TB_MODE_MASK; val 1016 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_TB_MODE_3; val 1017 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_TBCTL); val 1066 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_SDTIMNGCTL); val 1067 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_FLW_CTL_BG; val 1068 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_SDTIMNGCTL); val 1212 drivers/mmc/host/sdhci-of-esdhc.c u32 val; val 1265 drivers/mmc/host/sdhci-of-esdhc.c val = sdhci_readl(host, ESDHC_DMA_SYSCTL); val 1266 drivers/mmc/host/sdhci-of-esdhc.c val |= ESDHC_PERIPHERAL_CLK_SEL; val 1267 drivers/mmc/host/sdhci-of-esdhc.c sdhci_writel(host, val, ESDHC_DMA_SYSCTL); val 32 drivers/mmc/host/sdhci-of-hlwd.c static void sdhci_hlwd_writel(struct sdhci_host *host, u32 val, int reg) val 34 drivers/mmc/host/sdhci-of-hlwd.c sdhci_be32bs_writel(host, val, reg); val 38 drivers/mmc/host/sdhci-of-hlwd.c static void sdhci_hlwd_writew(struct sdhci_host *host, u16 val, int reg) val 40 drivers/mmc/host/sdhci-of-hlwd.c sdhci_be32bs_writew(host, val, reg); val 44 drivers/mmc/host/sdhci-of-hlwd.c static void sdhci_hlwd_writeb(struct sdhci_host *host, u8 val, int reg) val 46 drivers/mmc/host/sdhci-of-hlwd.c sdhci_be32bs_writeb(host, val, reg); val 97 drivers/mmc/host/sdhci-pci-arasan.c u8 val = 0; val 101 drivers/mmc/host/sdhci-pci-arasan.c val = sdhci_readw(host, PHY_ADDR_REG); val 102 drivers/mmc/host/sdhci-pci-arasan.c if (!(val & mask)) val 134 drivers/mmc/host/sdhci-pci-arasan.c u8 val = 0; val 138 drivers/mmc/host/sdhci-pci-arasan.c ret = arasan_phy_read(host, offset, &val); val 141 drivers/mmc/host/sdhci-pci-arasan.c else if (val & mask) val 152 drivers/mmc/host/sdhci-pci-arasan.c u8 val; val 155 drivers/mmc/host/sdhci-pci-arasan.c if (arasan_phy_read(host, IPAD_CTRL1, &val) || val 156 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | RETB_ENBL | PDB_ENBL, IPAD_CTRL1) || val 157 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, IPAD_CTRL2, &val) || val 158 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | RTRIM_EN, IPAD_CTRL2)) val 165 drivers/mmc/host/sdhci-pci-arasan.c if (arasan_phy_read(host, IOREN_CTRL1, &val) || val 166 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | REN_CMND | REN_STRB, IOREN_CTRL1) || val 167 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, IOPU_CTRL1, &val) || val 168 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | PU_CMD, IOPU_CTRL1) || val 169 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, CMD_CTRL, &val) || val 170 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | PDB_CMND, CMD_CTRL) || val 171 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, IOREN_CTRL2, &val) || val 172 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | REN_DATA, IOREN_CTRL2) || val 173 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, IOPU_CTRL2, &val) || val 174 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | PU_DAT, IOPU_CTRL2) || val 175 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, DATA_CTRL, &val) || val 176 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | PDB_DATA, DATA_CTRL) || val 177 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, STRB_CTRL, &val) || val 178 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | PDB_STRB, STRB_CTRL) || val 179 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, CLK_CTRL, &val) || val 180 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | PDB_CLOCK, CLK_CTRL) || val 181 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_read(host, CLKBUF_SEL, &val) || val 182 drivers/mmc/host/sdhci-pci-arasan.c arasan_phy_write(host, val | MAX_CLK_BUF, CLKBUF_SEL) || val 192 drivers/mmc/host/sdhci-pci-arasan.c u8 val; val 202 drivers/mmc/host/sdhci-pci-arasan.c ret = arasan_phy_read(host, IPAD_CTRL1, &val); val 205 drivers/mmc/host/sdhci-pci-arasan.c ret = arasan_phy_write(host, IOPAD(val, drv_type), IPAD_CTRL1); val 464 drivers/mmc/host/sdhci-pci-core.c u32 val = 0; val 473 drivers/mmc/host/sdhci-pci-core.c &val)) { val 478 drivers/mmc/host/sdhci-pci-core.c if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) val 481 drivers/mmc/host/sdhci-pci-core.c val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; val 484 drivers/mmc/host/sdhci-pci-core.c val)) { val 560 drivers/mmc/host/sdhci-pci-core.c u32 val; val 574 drivers/mmc/host/sdhci-pci-core.c err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); val 575 drivers/mmc/host/sdhci-pci-core.c intel_host->drv_strength = err ? 0 : val; val 577 drivers/mmc/host/sdhci-pci-core.c err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); val 578 drivers/mmc/host/sdhci-pci-core.c intel_host->d3_retune = err ? true : !!val; val 667 drivers/mmc/host/sdhci-pci-core.c u32 val; val 669 drivers/mmc/host/sdhci-pci-core.c val = sdhci_readl(host, INTEL_HS400_ES_REG); val 671 drivers/mmc/host/sdhci-pci-core.c val |= INTEL_HS400_ES_BIT; val 673 drivers/mmc/host/sdhci-pci-core.c val &= ~INTEL_HS400_ES_BIT; val 674 drivers/mmc/host/sdhci-pci-core.c sdhci_writel(host, val, INTEL_HS400_ES_REG); val 1487 drivers/mmc/host/sdhci-pci-core.c unsigned int val; val 1489 drivers/mmc/host/sdhci-pci-core.c val = sdhci_readw(host, SDHCI_HOST_CONTROL2); val 1490 drivers/mmc/host/sdhci-pci-core.c val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; val 1491 drivers/mmc/host/sdhci-pci-core.c sdhci_writew(host, val, SDHCI_HOST_CONTROL2); val 1493 drivers/mmc/host/sdhci-pci-core.c val = sdhci_readw(host, SDHCI_HOST_CONTROL2); val 1494 drivers/mmc/host/sdhci-pci-core.c val &= ~SDHCI_CTRL_EXEC_TUNING; val 1495 drivers/mmc/host/sdhci-pci-core.c sdhci_writew(host, val, SDHCI_HOST_CONTROL2); val 1500 drivers/mmc/host/sdhci-pci-core.c unsigned int val; val 1502 drivers/mmc/host/sdhci-pci-core.c pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); val 1503 drivers/mmc/host/sdhci-pci-core.c val &= ~AMD_BIT_MASK; val 1504 drivers/mmc/host/sdhci-pci-core.c val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); val 1505 drivers/mmc/host/sdhci-pci-core.c pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); val 1510 drivers/mmc/host/sdhci-pci-core.c unsigned int val; val 1512 drivers/mmc/host/sdhci-pci-core.c pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); val 1513 drivers/mmc/host/sdhci-pci-core.c val |= AMD_FIFO_PTR; val 1514 drivers/mmc/host/sdhci-pci-core.c pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); val 52 drivers/mmc/host/sdhci-pltfm.h u32 val, int reg) val 54 drivers/mmc/host/sdhci-pltfm.h out_be32(host->ioaddr + reg, val); val 58 drivers/mmc/host/sdhci-pltfm.h u16 val, int reg) val 70 drivers/mmc/host/sdhci-pltfm.h pltfm_host->xfer_mode_shadow = val; val 74 drivers/mmc/host/sdhci-pltfm.h val << 16 | pltfm_host->xfer_mode_shadow, val 78 drivers/mmc/host/sdhci-pltfm.h clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); val 81 drivers/mmc/host/sdhci-pltfm.h static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) val 86 drivers/mmc/host/sdhci-pltfm.h clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); val 42 drivers/mmc/host/sdhci-sirf.c u32 val = readl(host->ioaddr + reg); val 47 drivers/mmc/host/sdhci-sirf.c val = SDHCI_SUPPORT_DDR50 | val 52 drivers/mmc/host/sdhci-sirf.c u32 prss = val; val 55 drivers/mmc/host/sdhci-sirf.c val = prss | (SDHCI_SPEC_300 << 16); val 57 drivers/mmc/host/sdhci-sirf.c return val; val 105 drivers/mmc/host/sdhci-sprd.c u16 val; val 108 drivers/mmc/host/sdhci-sprd.c val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); val 109 drivers/mmc/host/sdhci-sprd.c val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; val 110 drivers/mmc/host/sdhci-sprd.c sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); val 121 drivers/mmc/host/sdhci-sprd.c static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) val 128 drivers/mmc/host/sdhci-sprd.c val = val & SDHCI_SPRD_INT_SIGNAL_MASK; val 130 drivers/mmc/host/sdhci-sprd.c writel_relaxed(val, host->ioaddr + reg); val 133 drivers/mmc/host/sdhci-sprd.c static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) val 139 drivers/mmc/host/sdhci-sprd.c writew_relaxed(val, host->ioaddr + reg); val 142 drivers/mmc/host/sdhci-sprd.c static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) val 154 drivers/mmc/host/sdhci-sprd.c val |= SDHCI_HW_RESET_CARD; val 157 drivers/mmc/host/sdhci-sprd.c writeb_relaxed(val, host->ioaddr + reg); val 218 drivers/mmc/host/sdhci-sprd.c u32 div, val, mask; val 227 drivers/mmc/host/sdhci-sprd.c val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); val 230 drivers/mmc/host/sdhci-sprd.c if (mask != (val & mask)) { val 231 drivers/mmc/host/sdhci-sprd.c val |= mask; val 232 drivers/mmc/host/sdhci-sprd.c sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); val 352 drivers/mmc/host/sdhci-sprd.c int val; val 360 drivers/mmc/host/sdhci-sprd.c val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); val 361 drivers/mmc/host/sdhci-sprd.c val &= ~SDHCI_HW_RESET_CARD; val 362 drivers/mmc/host/sdhci-sprd.c writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); val 366 drivers/mmc/host/sdhci-sprd.c val |= SDHCI_HW_RESET_CARD; val 367 drivers/mmc/host/sdhci-sprd.c writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); val 497 drivers/mmc/host/sdhci-sprd.c u32 val[4]; val 501 drivers/mmc/host/sdhci-sprd.c sdhci_sprd_phy_cfgs[i].property, val, 4); val 506 drivers/mmc/host/sdhci-sprd.c p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); val 170 drivers/mmc/host/sdhci-tegra.c static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) val 180 drivers/mmc/host/sdhci-tegra.c pltfm_host->xfer_mode_shadow = val; val 183 drivers/mmc/host/sdhci-tegra.c writel((val << 16) | pltfm_host->xfer_mode_shadow, val 188 drivers/mmc/host/sdhci-tegra.c writew(val, host->ioaddr + reg); val 191 drivers/mmc/host/sdhci-tegra.c static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) val 202 drivers/mmc/host/sdhci-tegra.c val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); val 204 drivers/mmc/host/sdhci-tegra.c writel(val, host->ioaddr + reg); val 210 drivers/mmc/host/sdhci-tegra.c if (val & SDHCI_INT_CARD_INT) val 239 drivers/mmc/host/sdhci-tegra.c static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) val 246 drivers/mmc/host/sdhci-tegra.c cmd = SDHCI_GET_CMD(val); val 254 drivers/mmc/host/sdhci-tegra.c writew(val, host->ioaddr + reg); val 340 drivers/mmc/host/sdhci-tegra.c u32 val; val 342 drivers/mmc/host/sdhci-tegra.c val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); val 345 drivers/mmc/host/sdhci-tegra.c val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; val 347 drivers/mmc/host/sdhci-tegra.c val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; val 349 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); val 412 drivers/mmc/host/sdhci-tegra.c u32 val; val 418 drivers/mmc/host/sdhci-tegra.c val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); val 421 drivers/mmc/host/sdhci-tegra.c val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; val 423 drivers/mmc/host/sdhci-tegra.c val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; val 425 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); val 773 drivers/mmc/host/sdhci-tegra.c u32 val; val 775 drivers/mmc/host/sdhci-tegra.c val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); val 776 drivers/mmc/host/sdhci-tegra.c val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; val 777 drivers/mmc/host/sdhci-tegra.c val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; val 778 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); val 804 drivers/mmc/host/sdhci-tegra.c u32 val, tun_status; val 823 drivers/mmc/host/sdhci-tegra.c val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); val 824 drivers/mmc/host/sdhci-tegra.c val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; val 825 drivers/mmc/host/sdhci-tegra.c val |= word; val 826 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); val 887 drivers/mmc/host/sdhci-tegra.c u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; val 894 drivers/mmc/host/sdhci-tegra.c val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); val 895 drivers/mmc/host/sdhci-tegra.c tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> val 917 drivers/mmc/host/sdhci-tegra.c val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); val 918 drivers/mmc/host/sdhci-tegra.c start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; val 919 drivers/mmc/host/sdhci-tegra.c end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & val 961 drivers/mmc/host/sdhci-tegra.c u32 val; val 987 drivers/mmc/host/sdhci-tegra.c val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); val 988 drivers/mmc/host/sdhci-tegra.c val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | val 991 drivers/mmc/host/sdhci-tegra.c val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | val 994 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); val 1130 drivers/mmc/host/sdhci-tegra.c static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) val 1145 drivers/mmc/host/sdhci-tegra.c if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && val 1148 drivers/mmc/host/sdhci-tegra.c writel(val, cq_host->mmio + reg); val 1161 drivers/mmc/host/sdhci-tegra.c writel(val, cq_host->mmio + reg); val 1163 drivers/mmc/host/sdhci-tegra.c writel(val, cq_host->mmio + reg); val 1182 drivers/mmc/host/sdhci-tegra.c u32 val; val 1191 drivers/mmc/host/sdhci-tegra.c val = cqhci_readl(cq_host, CQHCI_CFG); val 1192 drivers/mmc/host/sdhci-tegra.c if (val & CQHCI_ENABLE) val 1193 drivers/mmc/host/sdhci-tegra.c cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), val 1196 drivers/mmc/host/sdhci-tegra.c if (val & CQHCI_ENABLE) val 1197 drivers/mmc/host/sdhci-tegra.c cqhci_writel(cq_host, val, CQHCI_CFG); val 1207 drivers/mmc/host/sdhci-tegra.c val = cqhci_readl(cq_host, CQHCI_SSC1); val 1208 drivers/mmc/host/sdhci-tegra.c val &= ~CQHCI_SSC1_CBC_MASK; val 1209 drivers/mmc/host/sdhci-tegra.c cqhci_writel(cq_host, val, CQHCI_SSC1); val 854 drivers/mmc/host/sdhci.c unsigned long long val; val 861 drivers/mmc/host/sdhci.c val = 1000000ULL * data->timeout_clks; val 862 drivers/mmc/host/sdhci.c if (do_div(val, host->clock)) val 864 drivers/mmc/host/sdhci.c target_timeout += val; val 3227 drivers/mmc/host/sdhci.c u8 val; val 3242 drivers/mmc/host/sdhci.c val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); val 3243 drivers/mmc/host/sdhci.c val &= ~mask; val 3244 drivers/mmc/host/sdhci.c val |= wake_val; val 3245 drivers/mmc/host/sdhci.c sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); val 3256 drivers/mmc/host/sdhci.c u8 val; val 3260 drivers/mmc/host/sdhci.c val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); val 3261 drivers/mmc/host/sdhci.c val &= ~mask; val 3262 drivers/mmc/host/sdhci.c sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); val 616 drivers/mmc/host/sdhci.h void (*write_l)(struct sdhci_host *host, u32 val, int reg); val 617 drivers/mmc/host/sdhci.h void (*write_w)(struct sdhci_host *host, u16 val, int reg); val 618 drivers/mmc/host/sdhci.h void (*write_b)(struct sdhci_host *host, u8 val, int reg); val 653 drivers/mmc/host/sdhci.h static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) val 656 drivers/mmc/host/sdhci.h host->ops->write_l(host, val, reg); val 658 drivers/mmc/host/sdhci.h writel(val, host->ioaddr + reg); val 661 drivers/mmc/host/sdhci.h static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) val 664 drivers/mmc/host/sdhci.h host->ops->write_w(host, val, reg); val 666 drivers/mmc/host/sdhci.h writew(val, host->ioaddr + reg); val 669 drivers/mmc/host/sdhci.h static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) val 672 drivers/mmc/host/sdhci.h host->ops->write_b(host, val, reg); val 674 drivers/mmc/host/sdhci.h writeb(val, host->ioaddr + reg); val 703 drivers/mmc/host/sdhci.h static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) val 705 drivers/mmc/host/sdhci.h writel(val, host->ioaddr + reg); val 708 drivers/mmc/host/sdhci.h static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) val 710 drivers/mmc/host/sdhci.h writew(val, host->ioaddr + reg); val 713 drivers/mmc/host/sdhci.h static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) val 715 drivers/mmc/host/sdhci.h writeb(val, host->ioaddr + reg); val 102 drivers/mmc/host/sdhci_am654.c u32 mask, val; val 116 drivers/mmc/host/sdhci_am654.c val = (1 << OTAPDLYENA_SHIFT) | val 118 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); val 148 drivers/mmc/host/sdhci_am654.c val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); val 150 drivers/mmc/host/sdhci_am654.c val); val 167 drivers/mmc/host/sdhci_am654.c val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; val 171 drivers/mmc/host/sdhci_am654.c val |= sdhci_am654->drv_strength << DR_TY_SHIFT; val 172 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); val 181 drivers/mmc/host/sdhci_am654.c val, val & DLLRDY_MASK, 1000, val 197 drivers/mmc/host/sdhci_am654.c int val, mask; val 200 drivers/mmc/host/sdhci_am654.c val = (1 << OTAPDLYENA_SHIFT) | val 202 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); val 218 drivers/mmc/host/sdhci_am654.c static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) val 232 drivers/mmc/host/sdhci_am654.c val &= ~SDHCI_CTRL_HISPD; val 236 drivers/mmc/host/sdhci_am654.c writeb(val, host->ioaddr + reg); val 326 drivers/mmc/host/sdhci_am654.c u32 val; val 334 drivers/mmc/host/sdhci_am654.c regmap_read(sdhci_am654->base, PHY_STAT1, &val); val 335 drivers/mmc/host/sdhci_am654.c if (~val & CALDONE_MASK) { val 340 drivers/mmc/host/sdhci_am654.c PHY_STAT1, val, val 341 drivers/mmc/host/sdhci_am654.c val & CALDONE_MASK, val 261 drivers/mmc/host/sh_mmcif.c unsigned int reg, u32 val) val 263 drivers/mmc/host/sh_mmcif.c writel(val | readl(host->addr + reg), host->addr + reg); val 267 drivers/mmc/host/sh_mmcif.c unsigned int reg, u32 val) val 269 drivers/mmc/host/sh_mmcif.c writel(~val & readl(host->addr + reg), host->addr + reg); val 115 drivers/mmc/host/tifm_sd.c unsigned int pos = 0, val; val 124 drivers/mmc/host/tifm_sd.c val = readl(sock->addr + SOCK_MMCSD_DATA); val 125 drivers/mmc/host/tifm_sd.c buf[pos++] = val & 0xff; val 127 drivers/mmc/host/tifm_sd.c host->bounce_buf_data[0] = (val >> 8) & 0xff; val 131 drivers/mmc/host/tifm_sd.c buf[pos++] = (val >> 8) & 0xff; val 141 drivers/mmc/host/tifm_sd.c unsigned int pos = 0, val; val 145 drivers/mmc/host/tifm_sd.c val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00); val 146 drivers/mmc/host/tifm_sd.c writel(val, sock->addr + SOCK_MMCSD_DATA); val 151 drivers/mmc/host/tifm_sd.c val = buf[pos++]; val 153 drivers/mmc/host/tifm_sd.c host->bounce_buf_data[0] = val & 0xff; val 157 drivers/mmc/host/tifm_sd.c val |= (buf[pos++] << 8) & 0xff00; val 158 drivers/mmc/host/tifm_sd.c writel(val, sock->addr + SOCK_MMCSD_DATA); val 257 drivers/mmc/host/tmio_mmc.h u16 val) val 264 drivers/mmc/host/tmio_mmc.h iowrite16(val, host->ctl + (addr << host->bus_shift)); val 274 drivers/mmc/host/tmio_mmc.h int addr, u32 val) val 277 drivers/mmc/host/tmio_mmc.h val |= host->sdcard_irq_setbit_mask; val 279 drivers/mmc/host/tmio_mmc.h iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift)); val 280 drivers/mmc/host/tmio_mmc.h iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); val 283 drivers/mmc/host/tmio_mmc.h static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val) val 285 drivers/mmc/host/tmio_mmc.h iowrite32(val, host->ctl + (addr << host->bus_shift)); val 471 drivers/mmc/host/uniphier-sd.c u32 val; val 481 drivers/mmc/host/uniphier-sd.c val = 0x00000101; val 483 drivers/mmc/host/uniphier-sd.c val = 0x00000000; val 485 drivers/mmc/host/uniphier-sd.c writel(val, host->ctl + UNIPHIER_SD_HOST_MODE); val 487 drivers/mmc/host/uniphier-sd.c val = 0; val 493 drivers/mmc/host/uniphier-sd.c val |= UNIPHIER_SD_CLKCTL_OFFEN; val 495 drivers/mmc/host/uniphier-sd.c writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); val 504 drivers/mmc/host/uniphier-sd.c u32 val, tmp; val 508 drivers/mmc/host/uniphier-sd.c val = UNIPHIER_SD_VOLT_330; val 512 drivers/mmc/host/uniphier-sd.c val = UNIPHIER_SD_VOLT_180; val 521 drivers/mmc/host/uniphier-sd.c tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val); val 725 drivers/mmc/host/usdhi6rol0.c u32 val; val 739 drivers/mmc/host/usdhi6rol0.c val = usdhi6_read(host, USDHI6_SD_CLK_CTRL) & ~USDHI6_SD_CLK_CTRL_DIV_MASK; val 748 drivers/mmc/host/usdhi6rol0.c val |= 0xff; val 755 drivers/mmc/host/usdhi6rol0.c val |= div >> 2; val 765 drivers/mmc/host/usdhi6rol0.c rate, (val & 0xff) << 2, new_rate); val 774 drivers/mmc/host/usdhi6rol0.c val & ~USDHI6_SD_CLK_CTRL_SCLKEN); val 781 drivers/mmc/host/usdhi6rol0.c usdhi6_write(host, USDHI6_SD_CLK_CTRL, val); val 784 drivers/mmc/host/usdhi6rol0.c !(val & USDHI6_SD_CLK_CTRL_SCLKEN)) val 786 drivers/mmc/host/usdhi6rol0.c val | USDHI6_SD_CLK_CTRL_SCLKEN); val 870 drivers/mmc/host/usdhi6rol0.c u32 val; val 881 drivers/mmc/host/usdhi6rol0.c val = 14; val 884 drivers/mmc/host/usdhi6rol0.c val = 0; val 886 drivers/mmc/host/usdhi6rol0.c val = order_base_2(ticks) - 13; val 892 drivers/mmc/host/usdhi6rol0.c usdhi6_write(host, USDHI6_SD_OPTION, (val << USDHI6_SD_OPTION_TIMEOUT_SHIFT) | val 148 drivers/mmc/host/ushc.c static int ushc_hw_set_host_ctrl(struct ushc_data *ushc, u16 mask, u16 val) val 153 drivers/mmc/host/ushc.c host_ctrl = (ushc->host_ctrl & ~mask) | val; val 2654 drivers/mtd/chips/cfi_cmdset_0001.c static int cfi_intelext_reboot(struct notifier_block *nb, unsigned long val, val 3088 drivers/mtd/chips/cfi_cmdset_0002.c static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val, val 69 drivers/mtd/chips/cfi_util.c map_word val = { {0} }; val 126 drivers/mtd/chips/cfi_util.c val.x[i] = onecmd; val 129 drivers/mtd/chips/cfi_util.c return val; val 133 drivers/mtd/chips/cfi_util.c unsigned long cfi_merge_status(map_word val, struct map_info *map, val 155 drivers/mtd/chips/cfi_util.c onestat = val.x[0]; val 158 drivers/mtd/chips/cfi_util.c onestat |= val.x[i]; val 207 drivers/mtd/chips/cfi_util.c map_word val; val 209 drivers/mtd/chips/cfi_util.c val = cfi_build_cmd(cmd, map, cfi); val 214 drivers/mtd/chips/cfi_util.c map_write(map, val, addr); val 224 drivers/mtd/chips/cfi_util.c map_word val[3]; val 231 drivers/mtd/chips/cfi_util.c val[0] = map_read(map, base + osf*0x10); val 232 drivers/mtd/chips/cfi_util.c val[1] = map_read(map, base + osf*0x11); val 233 drivers/mtd/chips/cfi_util.c val[2] = map_read(map, base + osf*0x12); val 235 drivers/mtd/chips/cfi_util.c if (!map_word_equal(map, qry[0], val[0])) val 238 drivers/mtd/chips/cfi_util.c if (!map_word_equal(map, qry[1], val[1])) val 241 drivers/mtd/chips/cfi_util.c if (!map_word_equal(map, qry[2], val[2])) val 14 drivers/mtd/chips/fwh_lock.h enum fwh_lock_state val; val 70 drivers/mtd/chips/fwh_lock.h map_write(map, CMD(xxlt->val), adr); val 379 drivers/mtd/devices/block2mtd.c static int block2mtd_setup2(const char *val) val 390 drivers/mtd/devices/block2mtd.c if (strnlen(val, sizeof(buf)) >= sizeof(buf)) { val 395 drivers/mtd/devices/block2mtd.c strcpy(str, val); val 431 drivers/mtd/devices/block2mtd.c static int block2mtd_setup(const char *val, const struct kernel_param *kp) val 434 drivers/mtd/devices/block2mtd.c return block2mtd_setup2(val); val 442 drivers/mtd/devices/block2mtd.c return block2mtd_setup2(val); val 451 drivers/mtd/devices/block2mtd.c strlcpy(block2mtd_paramline, val, sizeof(block2mtd_paramline)); val 94 drivers/mtd/devices/docg3.c u8 val = readb(docg3->cascade->base + reg); val 96 drivers/mtd/devices/docg3.c trace_docg3_io(0, 8, reg, (int)val); val 97 drivers/mtd/devices/docg3.c return val; val 102 drivers/mtd/devices/docg3.c u16 val = readw(docg3->cascade->base + reg); val 104 drivers/mtd/devices/docg3.c trace_docg3_io(0, 16, reg, (int)val); val 105 drivers/mtd/devices/docg3.c return val; val 108 drivers/mtd/devices/docg3.c static inline void doc_writeb(struct docg3 *docg3, u8 val, u16 reg) val 110 drivers/mtd/devices/docg3.c writeb(val, docg3->cascade->base + reg); val 111 drivers/mtd/devices/docg3.c trace_docg3_io(1, 8, reg, val); val 114 drivers/mtd/devices/docg3.c static inline void doc_writew(struct docg3 *docg3, u16 val, u16 reg) val 116 drivers/mtd/devices/docg3.c writew(val, docg3->cascade->base + reg); val 117 drivers/mtd/devices/docg3.c trace_docg3_io(1, 16, reg, val); val 139 drivers/mtd/devices/docg3.c u8 val; val 142 drivers/mtd/devices/docg3.c val = doc_readb(docg3, reg); val 143 drivers/mtd/devices/docg3.c doc_vdbg("Read register %04x : %02x\n", reg, val); val 144 drivers/mtd/devices/docg3.c return val; val 149 drivers/mtd/devices/docg3.c u16 val; val 152 drivers/mtd/devices/docg3.c val = doc_readw(docg3, reg); val 153 drivers/mtd/devices/docg3.c doc_vdbg("Read register %04x : %04x\n", reg, val); val 154 drivers/mtd/devices/docg3.c return val; val 320 drivers/mtd/devices/docg3.h TP_PROTO(int op, int width, u16 reg, int val), val 321 drivers/mtd/devices/docg3.h TP_ARGS(op, width, reg, val), val 326 drivers/mtd/devices/docg3.h __field(int, val)), val 331 drivers/mtd/devices/docg3.h __entry->val = val;), val 334 drivers/mtd/devices/docg3.h __entry->reg, __entry->val) val 216 drivers/mtd/devices/phram.c static int phram_setup(const char *val) val 225 drivers/mtd/devices/phram.c if (strnlen(val, sizeof(buf)) >= sizeof(buf)) val 228 drivers/mtd/devices/phram.c strcpy(str, val); val 268 drivers/mtd/devices/phram.c static int phram_param_call(const char *val, const struct kernel_param *kp) val 271 drivers/mtd/devices/phram.c return phram_setup(val); val 281 drivers/mtd/devices/phram.c return phram_setup(val); val 292 drivers/mtd/devices/phram.c if (strlen(val) >= sizeof(phram_paramline)) val 294 drivers/mtd/devices/phram.c strcpy(phram_paramline, val); val 328 drivers/mtd/devices/spear_smi.c u32 val; val 339 drivers/mtd/devices/spear_smi.c val = HOLD1 | BANK_EN | DSEL_TIME | (prescale << 8); val 345 drivers/mtd/devices/spear_smi.c writel(val, dev->io_base + SMI_CR1); val 551 drivers/mtd/devices/spear_smi.c u32 ctrlreg1, val; val 576 drivers/mtd/devices/spear_smi.c ctrlreg1 = val = readl(dev->io_base + SMI_CR1); val 577 drivers/mtd/devices/spear_smi.c val &= ~(SW_MODE | WB_MODE); val 579 drivers/mtd/devices/spear_smi.c val |= FAST_MODE; val 581 drivers/mtd/devices/spear_smi.c writel(val, dev->io_base + SMI_CR1); val 748 drivers/mtd/devices/spear_smi.c u32 val = 0; val 758 drivers/mtd/devices/spear_smi.c val = readl(dev->io_base + SMI_CR1); val 759 drivers/mtd/devices/spear_smi.c writel(val | SW_MODE, dev->io_base + SMI_CR1); val 764 drivers/mtd/devices/spear_smi.c val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) | val 766 drivers/mtd/devices/spear_smi.c writel(val, dev->io_base + SMI_CR2); val 777 drivers/mtd/devices/spear_smi.c val = readl(dev->io_base + SMI_RR); val 778 drivers/mtd/devices/spear_smi.c val &= 0x00ffffff; val 779 drivers/mtd/devices/spear_smi.c ret = get_flash_index(val); val 783 drivers/mtd/devices/spear_smi.c val = readl(dev->io_base + SMI_CR1); val 784 drivers/mtd/devices/spear_smi.c writel(val & ~SW_MODE, dev->io_base + SMI_CR1); val 798 drivers/mtd/devices/spear_smi.c u32 val; val 805 drivers/mtd/devices/spear_smi.c of_property_read_u32(np, "clock-rate", &val); val 806 drivers/mtd/devices/spear_smi.c pdata->clk_rate = val; val 447 drivers/mtd/inftlcore.c static int nrbits(unsigned int val, int bitcount) val 452 drivers/mtd/inftlcore.c total += (((0x1 << i) & val) ? 1 : 0); val 86 drivers/mtd/lpddr/lpddr2_nvm.c map_word val = { {0} }; val 87 drivers/mtd/lpddr/lpddr2_nvm.c val.x[0] = myword; val 88 drivers/mtd/lpddr/lpddr2_nvm.c return val; val 96 drivers/mtd/lpddr/lpddr2_nvm.c u_int val = MR_CFGMASK; val 99 drivers/mtd/lpddr/lpddr2_nvm.c val = val << 16; val 101 drivers/mtd/lpddr/lpddr2_nvm.c return val; val 109 drivers/mtd/lpddr/lpddr2_nvm.c u_int val = SR_OK_DATAMASK; val 112 drivers/mtd/lpddr/lpddr2_nvm.c val = (val << 16)+val; val 114 drivers/mtd/lpddr/lpddr2_nvm.c return val; val 122 drivers/mtd/lpddr/lpddr2_nvm.c u_long val = 0; val 125 drivers/mtd/lpddr/lpddr2_nvm.c val = map->pfow_base + offset*pcm_data->bus_width; val 127 drivers/mtd/lpddr/lpddr2_nvm.c return val; val 65 drivers/mtd/lpddr/qinfo_probe.c unsigned int dsr, val; val 87 drivers/mtd/lpddr/qinfo_probe.c val = CMDVAL(map_read(map, map->pfow_base + PFOW_COMMAND_DATA)); val 88 drivers/mtd/lpddr/qinfo_probe.c return val; val 56 drivers/mtd/maps/dc21285.c map_word val; val 57 drivers/mtd/maps/dc21285.c val.x[0] = *(uint8_t*)(map->virt + ofs); val 58 drivers/mtd/maps/dc21285.c return val; val 63 drivers/mtd/maps/dc21285.c map_word val; val 64 drivers/mtd/maps/dc21285.c val.x[0] = *(uint16_t*)(map->virt + ofs); val 65 drivers/mtd/maps/dc21285.c return val; val 70 drivers/mtd/maps/dc21285.c map_word val; val 71 drivers/mtd/maps/dc21285.c val.x[0] = *(uint32_t*)(map->virt + ofs); val 72 drivers/mtd/maps/dc21285.c return val; val 91 drivers/mtd/maps/ixp4xx.c map_word val; val 92 drivers/mtd/maps/ixp4xx.c val.x[0] = flash_read16(map->virt + ofs); val 93 drivers/mtd/maps/ixp4xx.c return val; val 143 drivers/mtd/maps/nettel.c static int nettel_reboot_notifier(struct notifier_block *nb, unsigned long val, void *v) val 40 drivers/mtd/maps/pci.c map_word val; val 41 drivers/mtd/maps/pci.c val.x[0]= readb(map->base + map->translate(map, ofs)); val 42 drivers/mtd/maps/pci.c return val; val 48 drivers/mtd/maps/pci.c map_word val; val 49 drivers/mtd/maps/pci.c val.x[0] = readl(map->base + map->translate(map, ofs)); val 50 drivers/mtd/maps/pci.c return val; val 59 drivers/mtd/maps/pci.c static void mtd_pci_write8(struct map_info *_map, map_word val, unsigned long ofs) val 62 drivers/mtd/maps/pci.c writeb(val.x[0], map->base + map->translate(map, ofs)); val 65 drivers/mtd/maps/pci.c static void mtd_pci_write32(struct map_info *_map, map_word val, unsigned long ofs) val 68 drivers/mtd/maps/pci.c writel(val.x[0], map->base + map->translate(map, ofs)); val 131 drivers/mtd/maps/physmap-gemini.c u32 val; val 149 drivers/mtd/maps/physmap-gemini.c ret = regmap_read(rmap, GLOBAL_STATUS, &val); val 154 drivers/mtd/maps/physmap-gemini.c dev_dbg(dev, "global status reg: %08x\n", val); val 159 drivers/mtd/maps/physmap-gemini.c if ((val & FLASH_TYPE_MASK) != FLASH_TYPE_PARALLEL) { val 167 drivers/mtd/maps/physmap-gemini.c if (val & FLASH_WIDTH_16BIT) { val 87 drivers/mtd/maps/physmap-versatile.c u32 val; val 110 drivers/mtd/maps/physmap-versatile.c val = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); val 111 drivers/mtd/maps/physmap-versatile.c val |= INTEGRATOR_EBI_WRITE_ENABLE; val 112 drivers/mtd/maps/physmap-versatile.c writel(val, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); val 20 drivers/mtd/maps/tsunami_flash.c map_word val; val 21 drivers/mtd/maps/tsunami_flash.c val.x[0] = tsunami_tig_readb(offset); val 22 drivers/mtd/maps/tsunami_flash.c return val; val 547 drivers/mtd/mtdcore.c void *val, size_t bytes) val 553 drivers/mtd/mtdcore.c err = mtd_read(mtd, offset, bytes, &retlen, val); val 114 drivers/mtd/nand/bbt.c unsigned long val = status & GENMASK(bits_per_block - 1, 0); val 120 drivers/mtd/nand/bbt.c pos[0] |= val << offs; val 126 drivers/mtd/nand/bbt.c pos[1] |= val >> rbits; val 461 drivers/mtd/nand/onenand/omap2.c u32 val; val 476 drivers/mtd/nand/onenand/omap2.c r = of_property_read_u32(np, "reg", &val); val 488 drivers/mtd/nand/onenand/omap2.c c->gpmc_cs = val; val 132 drivers/mtd/nand/onenand/samsung.c unsigned int (*cmd_map)(unsigned int type, unsigned int val); val 179 drivers/mtd/nand/onenand/samsung.c static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val) val 181 drivers/mtd/nand/onenand/samsung.c return (type << S3C64XX_CMD_MAP_SHIFT) | val; val 553 drivers/mtd/nand/raw/atmel/nand-controller.c u32 addr, val; val 582 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val); val 1059 drivers/mtd/nand/raw/atmel/nand-controller.c u32 val; val 1062 drivers/mtd/nand/raw/atmel/nand-controller.c &val)) val 1063 drivers/mtd/nand/raw/atmel/nand-controller.c chip->ecc.strength = val; val 1067 drivers/mtd/nand/raw/atmel/nand-controller.c &val)) val 1068 drivers/mtd/nand/raw/atmel/nand-controller.c chip->ecc.size = val; val 1596 drivers/mtd/nand/raw/atmel/nand-controller.c u32 val; val 1606 drivers/mtd/nand/raw/atmel/nand-controller.c &val); val 1613 drivers/mtd/nand/raw/atmel/nand-controller.c nand->cs[i].id = val; val 1620 drivers/mtd/nand/raw/atmel/nand-controller.c if (!of_property_read_u32(np, "atmel,rb", &val)) { val 1621 drivers/mtd/nand/raw/atmel/nand-controller.c if (val > ATMEL_NFC_MAX_RB_ID) val 1625 drivers/mtd/nand/raw/atmel/nand-controller.c nand->cs[i].rb.id = val; val 1793 drivers/mtd/nand/raw/atmel/nand-controller.c u32 val; val 1801 drivers/mtd/nand/raw/atmel/nand-controller.c ret = of_property_read_u32(np, "#address-cells", &val); val 1807 drivers/mtd/nand/raw/atmel/nand-controller.c reg_cells = val; val 1809 drivers/mtd/nand/raw/atmel/nand-controller.c ret = of_property_read_u32(np, "#size-cells", &val); val 1815 drivers/mtd/nand/raw/atmel/nand-controller.c reg_cells += val; val 650 drivers/mtd/nand/raw/atmel/pmecc.c u32 val; val 660 drivers/mtd/nand/raw/atmel/pmecc.c val = (err_nbr - 1) << 16; val 662 drivers/mtd/nand/raw/atmel/pmecc.c val |= 1; val 664 drivers/mtd/nand/raw/atmel/pmecc.c writel(val, pmecc->regs.errloc + ATMEL_PMERRLOC_ELCFG); val 670 drivers/mtd/nand/raw/atmel/pmecc.c val, val & PMERRLOC_CALC_DONE, 0, val 678 drivers/mtd/nand/raw/atmel/pmecc.c roots_nbr = (val & PMERRLOC_ERR_NUM_MASK) >> 8; val 380 drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c u32 val; val 442 drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2; val 443 drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val); val 34 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c u32 val = brcmnand_readl(mmio); val 36 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c if (val & BCM63138_CTLRDY) { val 37 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c brcmnand_writel(val & ~BCM63138_CTLRDY, mmio); val 49 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c u32 val = brcmnand_readl(mmio); val 52 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c val |= BCM63138_CTLRDY; val 54 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c val &= ~BCM63138_CTLRDY; val 56 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c brcmnand_writel(val, mmio); val 55 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c u32 val = brcmnand_readl(mmio); val 57 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c if (val & (BCM6368_CTRL_READY << BCM6368_NAND_STATUS_SHIFT)) { val 59 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c val &= ~BCM6368_NAND_STATUS_MASK; val 60 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c val |= BCM6368_CTRL_READY << BCM6368_NAND_STATUS_SHIFT; val 61 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c brcmnand_writel(val, mmio); val 73 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c u32 val = brcmnand_readl(mmio); val 76 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c val &= ~BCM6368_NAND_STATUS_MASK; val 79 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c val |= BCM6368_CTRL_READY << BCM6368_NAND_ENABLE_SHIFT; val 81 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c val &= ~(BCM6368_CTRL_READY << BCM6368_NAND_ENABLE_SHIFT); val 83 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c brcmnand_writel(val, mmio); val 496 drivers/mtd/nand/raw/brcmnand/brcmnand.c u32 val) val 498 drivers/mtd/nand/raw/brcmnand/brcmnand.c brcmnand_writel(val, ctrl->nand_base + offs); val 616 drivers/mtd/nand/raw/brcmnand/brcmnand.c enum brcmnand_reg reg, u32 val) val 621 drivers/mtd/nand/raw/brcmnand/brcmnand.c nand_writereg(ctrl, offs, val); val 626 drivers/mtd/nand/raw/brcmnand/brcmnand.c int shift, u32 val) val 631 drivers/mtd/nand/raw/brcmnand/brcmnand.c tmp |= val << shift; val 641 drivers/mtd/nand/raw/brcmnand/brcmnand.c int word, u32 val) val 643 drivers/mtd/nand/raw/brcmnand/brcmnand.c __raw_writel(val, ctrl->nand_fc + word * 4); val 719 drivers/mtd/nand/raw/brcmnand/brcmnand.c static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) val 744 drivers/mtd/nand/raw/brcmnand/brcmnand.c brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); val 848 drivers/mtd/nand/raw/brcmnand/brcmnand.c static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) val 861 drivers/mtd/nand/raw/brcmnand/brcmnand.c tmp |= (!!val) << shift; val 879 drivers/mtd/nand/raw/brcmnand/brcmnand.c u32 val; val 886 drivers/mtd/nand/raw/brcmnand/brcmnand.c val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); val 887 drivers/mtd/nand/raw/brcmnand/brcmnand.c if ((val & mask) == expected_val) val 894 drivers/mtd/nand/raw/brcmnand/brcmnand.c expected_val, val & mask); val 901 drivers/mtd/nand/raw/brcmnand/brcmnand.c u32 val = en ? CS_SELECT_NAND_WP : 0; val 903 drivers/mtd/nand/raw/brcmnand/brcmnand.c brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); val 936 drivers/mtd/nand/raw/brcmnand/brcmnand.c enum flash_dma_reg dma_reg, u32 val) val 940 drivers/mtd/nand/raw/brcmnand/brcmnand.c brcmnand_writel(val, ctrl->flash_dma_base + offs); val 52 drivers/mtd/nand/raw/brcmnand/brcmnand.h static inline void brcmnand_writel(u32 val, void __iomem *addr) val 56 drivers/mtd/nand/raw/brcmnand/brcmnand.h __raw_writel(val, addr); val 58 drivers/mtd/nand/raw/brcmnand/brcmnand.h writel_relaxed(val, addr); val 37 drivers/mtd/nand/raw/brcmnand/iproc_nand.c u32 val = brcmnand_readl(mmio); val 39 drivers/mtd/nand/raw/brcmnand/iproc_nand.c if (val & IPROC_NAND_CTLR_READY) { val 52 drivers/mtd/nand/raw/brcmnand/iproc_nand.c u32 val; val 57 drivers/mtd/nand/raw/brcmnand/iproc_nand.c val = brcmnand_readl(mmio); val 60 drivers/mtd/nand/raw/brcmnand/iproc_nand.c val |= IPROC_NAND_INT_CTRL_READ_ENABLE; val 62 drivers/mtd/nand/raw/brcmnand/iproc_nand.c val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE; val 64 drivers/mtd/nand/raw/brcmnand/iproc_nand.c brcmnand_writel(val, mmio); val 75 drivers/mtd/nand/raw/brcmnand/iproc_nand.c u32 val; val 80 drivers/mtd/nand/raw/brcmnand/iproc_nand.c val = brcmnand_readl(mmio); val 89 drivers/mtd/nand/raw/brcmnand/iproc_nand.c val |= IPROC_NAND_APB_LE_MODE; val 91 drivers/mtd/nand/raw/brcmnand/iproc_nand.c val &= ~IPROC_NAND_APB_LE_MODE; val 93 drivers/mtd/nand/raw/brcmnand/iproc_nand.c val &= ~IPROC_NAND_APB_LE_MODE; val 96 drivers/mtd/nand/raw/brcmnand/iproc_nand.c brcmnand_writel(val, mmio); val 269 drivers/mtd/nand/raw/cs553x_nand.c uint64_t val; val 276 drivers/mtd/nand/raw/cs553x_nand.c rdmsrl(MSR_DIVIL_GLD_CAP, val); val 277 drivers/mtd/nand/raw/cs553x_nand.c val &= ~0xFFULL; val 278 drivers/mtd/nand/raw/cs553x_nand.c if (val != CAP_CS5535 && val != CAP_CS5536) val 282 drivers/mtd/nand/raw/cs553x_nand.c rdmsrl(MSR_DIVIL_BALL_OPTS, val); val 283 drivers/mtd/nand/raw/cs553x_nand.c if (val & PIN_OPT_IDE) { val 289 drivers/mtd/nand/raw/cs553x_nand.c rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val); val 291 drivers/mtd/nand/raw/cs553x_nand.c if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND)) val 292 drivers/mtd/nand/raw/cs553x_nand.c err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF); val 223 drivers/mtd/nand/raw/davinci_nand.c u32 val; val 231 drivers/mtd/nand/raw/davinci_nand.c val = davinci_nand_readl(info, NANDFCR_OFFSET); val 232 drivers/mtd/nand/raw/davinci_nand.c val &= ~(0x03 << 4); val 233 drivers/mtd/nand/raw/davinci_nand.c val |= (info->core_chipsel << 4) | BIT(12); val 234 drivers/mtd/nand/raw/davinci_nand.c davinci_nand_writel(info, NANDFCR_OFFSET, val); val 697 drivers/mtd/nand/raw/davinci_nand.c uint32_t val; val 784 drivers/mtd/nand/raw/davinci_nand.c val = davinci_nand_readl(info, NANDFCR_OFFSET); val 785 drivers/mtd/nand/raw/davinci_nand.c val |= BIT(info->core_chipsel); val 786 drivers/mtd/nand/raw/davinci_nand.c davinci_nand_writel(info, NANDFCR_OFFSET, val); val 805 drivers/mtd/nand/raw/davinci_nand.c val = davinci_nand_readl(info, NRCSR_OFFSET); val 807 drivers/mtd/nand/raw/davinci_nand.c (val >> 8) & 0xff, val & 0xff); val 187 drivers/mtd/nand/raw/diskonchip.c uint8_t val; val 198 drivers/mtd/nand/raw/diskonchip.c val = (uint8_t) (errval[i] >> (2 + bitpos)); val 199 drivers/mtd/nand/raw/diskonchip.c parity ^= val; val 201 drivers/mtd/nand/raw/diskonchip.c data[index] ^= val; val 208 drivers/mtd/nand/raw/diskonchip.c val = (uint8_t) (errval[i] << (8 - bitpos)); val 209 drivers/mtd/nand/raw/diskonchip.c parity ^= val; val 211 drivers/mtd/nand/raw/diskonchip.c data[index] ^= val; val 834 drivers/mtd/nand/raw/fsmc_nand.c u32 val; val 839 drivers/mtd/nand/raw/fsmc_nand.c if (!of_property_read_u32(np, "bank-width", &val)) { val 840 drivers/mtd/nand/raw/fsmc_nand.c if (val == 2) { val 842 drivers/mtd/nand/raw/fsmc_nand.c } else if (val != 1) { val 843 drivers/mtd/nand/raw/fsmc_nand.c dev_err(&pdev->dev, "invalid bank-width %u\n", val); val 864 drivers/mtd/nand/raw/fsmc_nand.c if (!of_property_read_u32(np, "bank", &val)) { val 865 drivers/mtd/nand/raw/fsmc_nand.c if (val > 3) { val 866 drivers/mtd/nand/raw/fsmc_nand.c dev_err(&pdev->dev, "invalid bank %u\n", val); val 869 drivers/mtd/nand/raw/fsmc_nand.c host->bank = val; val 959 drivers/mtd/nand/raw/fsmc_nand.c u32 val; val 961 drivers/mtd/nand/raw/fsmc_nand.c val = readl(host->regs_va + FSMC_PC); val 962 drivers/mtd/nand/raw/fsmc_nand.c val &= ~FSMC_ENABLE; val 963 drivers/mtd/nand/raw/fsmc_nand.c writel(val, host->regs_va + FSMC_PC); val 110 drivers/mtd/nand/raw/gpio.c u32 val; val 115 drivers/mtd/nand/raw/gpio.c if (!of_property_read_u32(dev->of_node, "bank-width", &val)) { val 116 drivers/mtd/nand/raw/gpio.c if (val == 2) { val 118 drivers/mtd/nand/raw/gpio.c } else if (val != 1) { val 119 drivers/mtd/nand/raw/gpio.c dev_err(dev, "invalid bank-width %u\n", val); val 124 drivers/mtd/nand/raw/gpio.c if (!of_property_read_u32(dev->of_node, "chip-delay", &val)) val 125 drivers/mtd/nand/raw/gpio.c plat->chip_delay = val; val 158 drivers/mtd/nand/raw/hisi504_nand.c int val; val 161 drivers/mtd/nand/raw/hisi504_nand.c val = hinfc_read(host, HINFC504_STATUS); val 164 drivers/mtd/nand/raw/hisi504_nand.c while (!(val & HINFC504_READY)) { val 166 drivers/mtd/nand/raw/hisi504_nand.c val = hinfc_read(host, HINFC504_STATUS); val 171 drivers/mtd/nand/raw/hisi504_nand.c if (val & HINFC504_READY) val 183 drivers/mtd/nand/raw/hisi504_nand.c unsigned long val; val 210 drivers/mtd/nand/raw/hisi504_nand.c val = (HINFC504_DMA_CTRL_DMA_START | HINFC504_DMA_CTRL_BURST4_EN val 219 drivers/mtd/nand/raw/hisi504_nand.c val |= HINFC504_DMA_CTRL_WE; val 223 drivers/mtd/nand/raw/hisi504_nand.c hinfc_write(host, val, HINFC504_DMA_CTRL); val 230 drivers/mtd/nand/raw/hisi504_nand.c val = hinfc_read(host, HINFC504_DMA_CTRL); val 231 drivers/mtd/nand/raw/hisi504_nand.c if (!(val & HINFC504_DMA_CTRL_DMA_START)) val 135 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c u32 val, offset = 0; val 144 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c val = readl_relaxed(bch->base + BCH_BHPAR0 + offset); val 147 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c dest8[2] = (val >> 16) & 0xff; val 150 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c dest8[1] = (val >> 8) & 0xff; val 153 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c dest8[0] = val & 0xff; val 113 drivers/mtd/nand/raw/ingenic/jz4780_bch.c u32 val, offset = 0; val 122 drivers/mtd/nand/raw/ingenic/jz4780_bch.c val = readl(bch->base + BCH_BHPAR0 + offset); val 125 drivers/mtd/nand/raw/ingenic/jz4780_bch.c dest8[2] = (val >> 16) & 0xff; val 128 drivers/mtd/nand/raw/ingenic/jz4780_bch.c dest8[1] = (val >> 8) & 0xff; val 131 drivers/mtd/nand/raw/ingenic/jz4780_bch.c dest8[0] = val & 0xff; val 555 drivers/mtd/nand/raw/marvell_nand.c u32 val; val 562 drivers/mtd/nand/raw/marvell_nand.c ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, val 563 drivers/mtd/nand/raw/marvell_nand.c (val & NDCR_ND_RUN) == 0, val 593 drivers/mtd/nand/raw/marvell_nand.c u32 ndcr, val; val 608 drivers/mtd/nand/raw/marvell_nand.c ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, val 609 drivers/mtd/nand/raw/marvell_nand.c val & NDSR_WRCMDREQ, val 653 drivers/mtd/nand/raw/marvell_nand.c u32 val; val 656 drivers/mtd/nand/raw/marvell_nand.c ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, val 657 drivers/mtd/nand/raw/marvell_nand.c val & flag, val 662 drivers/mtd/nand/raw/marvell_nand.c label, val); val 130 drivers/mtd/nand/raw/mpc5121_nfc.c static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val) val 135 drivers/mtd/nand/raw/mpc5121_nfc.c out_be16(prv->regs + reg, val); val 122 drivers/mtd/nand/raw/mtk_ecc.c u32 val; val 125 drivers/mtd/nand/raw/mtk_ecc.c ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, val 126 drivers/mtd/nand/raw/mtk_ecc.c val & ECC_IDLE_MASK, val 73 drivers/mtd/nand/raw/mtk_nand.c #define ADDRCNTR_SEC(val) \ val 74 drivers/mtd/nand/raw/mtk_nand.c (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT) val 229 drivers/mtd/nand/raw/mtk_nand.c static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg) val 231 drivers/mtd/nand/raw/mtk_nand.c writel(val, nfc->regs + reg); val 234 drivers/mtd/nand/raw/mtk_nand.c static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg) val 236 drivers/mtd/nand/raw/mtk_nand.c writew(val, nfc->regs + reg); val 239 drivers/mtd/nand/raw/mtk_nand.c static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg) val 241 drivers/mtd/nand/raw/mtk_nand.c writeb(val, nfc->regs + reg); val 262 drivers/mtd/nand/raw/mtk_nand.c u32 val; val 269 drivers/mtd/nand/raw/mtk_nand.c ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val, val 270 drivers/mtd/nand/raw/mtk_nand.c !(val & MASTER_STA_MASK), 50, val 274 drivers/mtd/nand/raw/mtk_nand.c NFI_MASTER_STA, val); val 284 drivers/mtd/nand/raw/mtk_nand.c u32 val; val 289 drivers/mtd/nand/raw/mtk_nand.c ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, val 290 drivers/mtd/nand/raw/mtk_nand.c !(val & STA_CMD), 10, MTK_TIMEOUT); val 302 drivers/mtd/nand/raw/mtk_nand.c u32 val; val 309 drivers/mtd/nand/raw/mtk_nand.c ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, val 310 drivers/mtd/nand/raw/mtk_nand.c !(val & STA_ADDR), 10, MTK_TIMEOUT); val 431 drivers/mtd/nand/raw/mtk_nand.c u8 val; val 433 drivers/mtd/nand/raw/mtk_nand.c rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val, val 434 drivers/mtd/nand/raw/mtk_nand.c val & PIO_DI_RDY, 10, MTK_TIMEOUT); val 4906 drivers/mtd/nand/raw/nand_base.c u32 val; val 4908 drivers/mtd/nand/raw/nand_base.c ret = of_property_read_u32(np, "nand-ecc-step-size", &val); val 4909 drivers/mtd/nand/raw/nand_base.c return ret ? ret : val; val 4915 drivers/mtd/nand/raw/nand_base.c u32 val; val 4917 drivers/mtd/nand/raw/nand_base.c ret = of_property_read_u32(np, "nand-ecc-strength", &val); val 4918 drivers/mtd/nand/raw/nand_base.c return ret ? ret : val; val 4923 drivers/mtd/nand/raw/nand_base.c u32 val; val 4925 drivers/mtd/nand/raw/nand_base.c if (of_property_read_u32(np, "nand-bus-width", &val)) val 4928 drivers/mtd/nand/raw/nand_base.c switch (val) { val 4931 drivers/mtd/nand/raw/nand_base.c return val; val 88 drivers/mtd/nand/raw/nand_hynix.c static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val) val 95 drivers/mtd/nand/raw/nand_hynix.c NAND_OP_8BIT_DATA_OUT(1, &val, 0), val 103 drivers/mtd/nand/raw/nand_hynix.c chip->legacy.write_byte(chip, val); val 173 drivers/mtd/nand/raw/nand_hynix.c u8 val = in[i]; val 177 drivers/mtd/nand/raw/nand_hynix.c if (in[j] == val) val 183 drivers/mtd/nand/raw/nand_hynix.c *out = val; val 260 drivers/mtd/nand/raw/nand_hynix.c int mode, int reg, bool inv, u8 *val) val 273 drivers/mtd/nand/raw/nand_hynix.c ret = hynix_get_majority(tmp, NAND_HYNIX_1XNM_RR_REPEAT, val); val 278 drivers/mtd/nand/raw/nand_hynix.c *val = ~*val; val 323 drivers/mtd/nand/raw/nand_hynix.c u8 *val = rr->values + (i * nregs); val 326 drivers/mtd/nand/raw/nand_hynix.c false, val); val 331 drivers/mtd/nand/raw/nand_hynix.c true, val); val 30 drivers/mtd/nand/raw/nand_jedec.c int i, val, ret; val 68 drivers/mtd/nand/raw/nand_jedec.c val = le16_to_cpu(p->revision); val 69 drivers/mtd/nand/raw/nand_jedec.c if (val & (1 << 2)) val 71 drivers/mtd/nand/raw/nand_jedec.c else if (val & (1 << 1)) val 75 drivers/mtd/nand/raw/nand_jedec.c pr_info("unsupported JEDEC version: %d\n", val); val 117 drivers/mtd/nand/raw/nand_onfi.c u8 val = 0; val 130 drivers/mtd/nand/raw/nand_onfi.c val |= BIT(j); val 133 drivers/mtd/nand/raw/nand_onfi.c ((u8 *)dstbuf)[i] = val; val 148 drivers/mtd/nand/raw/nand_onfi.c int i, ret, val; val 202 drivers/mtd/nand/raw/nand_onfi.c val = le16_to_cpu(p->revision); val 203 drivers/mtd/nand/raw/nand_onfi.c if (val & ONFI_VERSION_2_3) val 205 drivers/mtd/nand/raw/nand_onfi.c else if (val & ONFI_VERSION_2_2) val 207 drivers/mtd/nand/raw/nand_onfi.c else if (val & ONFI_VERSION_2_1) val 209 drivers/mtd/nand/raw/nand_onfi.c else if (val & ONFI_VERSION_2_0) val 211 drivers/mtd/nand/raw/nand_onfi.c else if (val & ONFI_VERSION_1_0) val 215 drivers/mtd/nand/raw/nand_onfi.c pr_info("unsupported ONFI version: %d\n", val); val 113 drivers/mtd/nand/raw/omap2.c #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) val 114 drivers/mtd/nand/raw/omap2.c #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) val 115 drivers/mtd/nand/raw/omap2.c #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) val 192 drivers/mtd/nand/raw/omap2.c u32 val; val 206 drivers/mtd/nand/raw/omap2.c val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | val 209 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_prefetch_config1); val 397 drivers/mtd/nand/raw/omap2.c u32 val; val 429 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_prefetch_status); val 430 drivers/mtd/nand/raw/omap2.c val = PREFETCH_STATUS_COUNT(val); val 431 drivers/mtd/nand/raw/omap2.c } while (val && (tim++ < limit)); val 465 drivers/mtd/nand/raw/omap2.c u32 val; val 506 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_prefetch_status); val 507 drivers/mtd/nand/raw/omap2.c val = PREFETCH_STATUS_COUNT(val); val 508 drivers/mtd/nand/raw/omap2.c } while (val && (tim++ < limit)); val 671 drivers/mtd/nand/raw/omap2.c u32 val; val 701 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_prefetch_status); val 702 drivers/mtd/nand/raw/omap2.c val = PREFETCH_STATUS_COUNT(val); val 704 drivers/mtd/nand/raw/omap2.c } while (val && (tim++ < limit)); val 924 drivers/mtd/nand/raw/omap2.c u32 val; val 926 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_ecc_config); val 927 drivers/mtd/nand/raw/omap2.c if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) val 931 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_ecc1_result); val 932 drivers/mtd/nand/raw/omap2.c *ecc_code++ = val; /* P128e, ..., P1e */ val 933 drivers/mtd/nand/raw/omap2.c *ecc_code++ = val >> 16; /* P128o, ..., P1o */ val 935 drivers/mtd/nand/raw/omap2.c *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); val 949 drivers/mtd/nand/raw/omap2.c u32 val; val 952 drivers/mtd/nand/raw/omap2.c val = ECCCLEAR | ECC1; val 953 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_control); val 956 drivers/mtd/nand/raw/omap2.c val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | val 958 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_size_config); val 975 drivers/mtd/nand/raw/omap2.c val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); val 976 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_config); val 1041 drivers/mtd/nand/raw/omap2.c u32 val, wr_mode; val 1106 drivers/mtd/nand/raw/omap2.c val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); val 1107 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_size_config); val 1112 drivers/mtd/nand/raw/omap2.c val = ((1 << 16) | /* enable BCH */ val 1120 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_config); val 1148 drivers/mtd/nand/raw/omap2.c u32 val; val 1187 drivers/mtd/nand/raw/omap2.c val = readl(gpmc_regs->gpmc_bch_result6[i]); val 1188 drivers/mtd/nand/raw/omap2.c ecc_code[0] = ((val >> 8) & 0xFF); val 1189 drivers/mtd/nand/raw/omap2.c ecc_code[1] = ((val >> 0) & 0xFF); val 1190 drivers/mtd/nand/raw/omap2.c val = readl(gpmc_regs->gpmc_bch_result5[i]); val 1191 drivers/mtd/nand/raw/omap2.c ecc_code[2] = ((val >> 24) & 0xFF); val 1192 drivers/mtd/nand/raw/omap2.c ecc_code[3] = ((val >> 16) & 0xFF); val 1193 drivers/mtd/nand/raw/omap2.c ecc_code[4] = ((val >> 8) & 0xFF); val 1194 drivers/mtd/nand/raw/omap2.c ecc_code[5] = ((val >> 0) & 0xFF); val 1195 drivers/mtd/nand/raw/omap2.c val = readl(gpmc_regs->gpmc_bch_result4[i]); val 1196 drivers/mtd/nand/raw/omap2.c ecc_code[6] = ((val >> 24) & 0xFF); val 1197 drivers/mtd/nand/raw/omap2.c ecc_code[7] = ((val >> 16) & 0xFF); val 1198 drivers/mtd/nand/raw/omap2.c ecc_code[8] = ((val >> 8) & 0xFF); val 1199 drivers/mtd/nand/raw/omap2.c ecc_code[9] = ((val >> 0) & 0xFF); val 1200 drivers/mtd/nand/raw/omap2.c val = readl(gpmc_regs->gpmc_bch_result3[i]); val 1201 drivers/mtd/nand/raw/omap2.c ecc_code[10] = ((val >> 24) & 0xFF); val 1202 drivers/mtd/nand/raw/omap2.c ecc_code[11] = ((val >> 16) & 0xFF); val 1203 drivers/mtd/nand/raw/omap2.c ecc_code[12] = ((val >> 8) & 0xFF); val 1204 drivers/mtd/nand/raw/omap2.c ecc_code[13] = ((val >> 0) & 0xFF); val 1205 drivers/mtd/nand/raw/omap2.c val = readl(gpmc_regs->gpmc_bch_result2[i]); val 1206 drivers/mtd/nand/raw/omap2.c ecc_code[14] = ((val >> 24) & 0xFF); val 1207 drivers/mtd/nand/raw/omap2.c ecc_code[15] = ((val >> 16) & 0xFF); val 1208 drivers/mtd/nand/raw/omap2.c ecc_code[16] = ((val >> 8) & 0xFF); val 1209 drivers/mtd/nand/raw/omap2.c ecc_code[17] = ((val >> 0) & 0xFF); val 1210 drivers/mtd/nand/raw/omap2.c val = readl(gpmc_regs->gpmc_bch_result1[i]); val 1211 drivers/mtd/nand/raw/omap2.c ecc_code[18] = ((val >> 24) & 0xFF); val 1212 drivers/mtd/nand/raw/omap2.c ecc_code[19] = ((val >> 16) & 0xFF); val 1213 drivers/mtd/nand/raw/omap2.c ecc_code[20] = ((val >> 8) & 0xFF); val 1214 drivers/mtd/nand/raw/omap2.c ecc_code[21] = ((val >> 0) & 0xFF); val 1215 drivers/mtd/nand/raw/omap2.c val = readl(gpmc_regs->gpmc_bch_result0[i]); val 1216 drivers/mtd/nand/raw/omap2.c ecc_code[22] = ((val >> 24) & 0xFF); val 1217 drivers/mtd/nand/raw/omap2.c ecc_code[23] = ((val >> 16) & 0xFF); val 1218 drivers/mtd/nand/raw/omap2.c ecc_code[24] = ((val >> 8) & 0xFF); val 1219 drivers/mtd/nand/raw/omap2.c ecc_code[25] = ((val >> 0) & 0xFF); val 85 drivers/mtd/nand/raw/omap_elm.c static void elm_write_reg(struct elm_info *info, int offset, u32 val) val 87 drivers/mtd/nand/raw/omap_elm.c writel(val, info->elm_base + offset); val 165 drivers/mtd/nand/raw/omap_elm.c u32 val; val 177 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[9]); val 178 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 182 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[5]); val 183 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 187 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[1]); val 188 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 192 drivers/mtd/nand/raw/omap_elm.c val = ecc[0]; val 193 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 197 drivers/mtd/nand/raw/omap_elm.c val = (cpu_to_be32(*(u32 *) &ecc[3]) >> 4) | val 199 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 203 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[0]) >> 12; val 204 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 207 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[22]); val 208 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 210 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[18]); val 211 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 213 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[14]); val 214 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 216 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[10]); val 217 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 219 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[6]); val 220 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 222 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[2]); val 223 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 225 drivers/mtd/nand/raw/omap_elm.c val = cpu_to_be32(*(u32 *) &ecc[0]) >> 16; val 226 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, val); val 94 drivers/mtd/nand/raw/orion_nand.c u32 val = 0; val 115 drivers/mtd/nand/raw/orion_nand.c if (!of_property_read_u32(pdev->dev.of_node, "cle", &val)) val 116 drivers/mtd/nand/raw/orion_nand.c board->cle = (u8)val; val 119 drivers/mtd/nand/raw/orion_nand.c if (!of_property_read_u32(pdev->dev.of_node, "ale", &val)) val 120 drivers/mtd/nand/raw/orion_nand.c board->ale = (u8)val; val 124 drivers/mtd/nand/raw/orion_nand.c "bank-width", &val)) val 125 drivers/mtd/nand/raw/orion_nand.c board->width = (u8)val * 8; val 129 drivers/mtd/nand/raw/orion_nand.c "chip-delay", &val)) val 130 drivers/mtd/nand/raw/orion_nand.c board->chip_delay = (u8)val; val 578 drivers/mtd/nand/raw/qcom_nandc.c u32 val) val 580 drivers/mtd/nand/raw/qcom_nandc.c iowrite32(val, nandc->base + offset); val 648 drivers/mtd/nand/raw/qcom_nandc.c u32 val) val 656 drivers/mtd/nand/raw/qcom_nandc.c *reg = cpu_to_le32(val); val 718 drivers/mtd/nand/raw/s3c2410.c unsigned long val, void *data) val 726 drivers/mtd/nand/raw/s3c2410.c if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || val 727 drivers/mtd/nand/raw/s3c2410.c (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { val 259 drivers/mtd/nand/raw/sh_flctl.c uint32_t val; val 261 drivers/mtd/nand/raw/sh_flctl.c val = readl(FLDTCNTR(flctl)) >> 16; val 262 drivers/mtd/nand/raw/sh_flctl.c if (val & 0xFF) val 60 drivers/mtd/nand/raw/socrates_nand.c uint32_t val; val 62 drivers/mtd/nand/raw/socrates_nand.c val = FPGA_NAND_ENABLE | FPGA_NAND_CMD_READ; val 64 drivers/mtd/nand/raw/socrates_nand.c out_be32(host->io_base, val); val 89 drivers/mtd/nand/raw/socrates_nand.c uint32_t val; val 95 drivers/mtd/nand/raw/socrates_nand.c val = FPGA_NAND_CMD_COMMAND; val 97 drivers/mtd/nand/raw/socrates_nand.c val = FPGA_NAND_CMD_ADDR; val 100 drivers/mtd/nand/raw/socrates_nand.c val |= FPGA_NAND_ENABLE; val 102 drivers/mtd/nand/raw/socrates_nand.c val |= (cmd & 0xff) << FPGA_NAND_DATA_SHIFT; val 104 drivers/mtd/nand/raw/socrates_nand.c out_be32(host->io_base, val); val 239 drivers/mtd/nand/raw/tango_nand.c u32 res, val; val 265 drivers/mtd/nand/raw/tango_nand.c err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000); val 153 drivers/mtd/nand/raw/tegra_nand.c #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off)) val 785 drivers/mtd/nand/raw/tegra_nand.c u32 val, reg = 0; val 787 drivers/mtd/nand/raw/tegra_nand.c val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min, val 789 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TCR_TAR_TRR(OFFSET(val, 3)); val 791 drivers/mtd/nand/raw/tegra_nand.c val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min), val 794 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TCS(OFFSET(val, 2)); val 796 drivers/mtd/nand/raw/tegra_nand.c val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000, val 798 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TRP(OFFSET(val, 1)) | TIMING_TRP_RESP(OFFSET(val, 1)); val 808 drivers/mtd/nand/raw/tegra_nand.c val = DIV_ROUND_UP(timings->tADL_min, period); val 809 drivers/mtd/nand/raw/tegra_nand.c reg = TIMING_TADL(OFFSET(val, 3)); val 97 drivers/mtd/nand/raw/txx9ndfmc.c u32 val, unsigned int reg) val 99 drivers/mtd/nand/raw/txx9ndfmc.c __raw_writel(val, ndregaddr(dev, reg)); val 98 drivers/mtd/nand/raw/vf610_nfc.c #define COL_ADDR(pos, val) (((val) & 0xFF) << (8 * (pos))) val 103 drivers/mtd/nand/raw/vf610_nfc.c #define ROW_ADDR(pos, val) (((val) & 0xFF) << (8 * (pos))) val 178 drivers/mtd/nand/raw/vf610_nfc.c static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val) val 180 drivers/mtd/nand/raw/vf610_nfc.c writel(val, nfc->regs + reg); val 194 drivers/mtd/nand/raw/vf610_nfc.c u32 mask, u32 shift, u32 val) val 197 drivers/mtd/nand/raw/vf610_nfc.c (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); val 235 drivers/mtd/nand/raw/vf610_nfc.c u32 val = swab32(__raw_readl(src + i)); val 237 drivers/mtd/nand/raw/vf610_nfc.c memcpy(dst + i, &val, min(sizeof(val), len - i)); val 270 drivers/mtd/nand/raw/vf610_nfc.c u32 val; val 272 drivers/mtd/nand/raw/vf610_nfc.c memcpy(&val, src + i, min(sizeof(val), len - i)); val 273 drivers/mtd/nand/raw/vf610_nfc.c __raw_writel(swab32(val), dst + i); val 393 drivers/mtd/nand/raw/vf610_nfc.c u8 val = instr->ctx.addr.addrs[i]; val 396 drivers/mtd/nand/raw/vf610_nfc.c col |= COL_ADDR(i, val); val 398 drivers/mtd/nand/raw/vf610_nfc.c row |= ROW_ADDR(i - 2, val); val 22 drivers/mtd/nand/spi/core.c static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) val 32 drivers/mtd/nand/spi/core.c *val = *spinand->scratchbuf; val 36 drivers/mtd/nand/spi/core.c static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) val 41 drivers/mtd/nand/spi/core.c *spinand->scratchbuf = val; val 92 drivers/mtd/nand/spi/core.c int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val) val 102 drivers/mtd/nand/spi/core.c cfg |= val; val 68 drivers/mtd/parsers/afs.c u32 val; val 70 drivers/mtd/parsers/afs.c val = p[i]; val 71 drivers/mtd/parsers/afs.c if (val > ~sum) val 73 drivers/mtd/parsers/afs.c sum += val; val 247 drivers/mtd/spi-nor/cadence-quadspi.c u32 val; val 249 drivers/mtd/spi-nor/cadence-quadspi.c return readl_relaxed_poll_timeout(reg, val, val 250 drivers/mtd/spi-nor/cadence-quadspi.c (((clr ? ~val : val) & mask) == mask), val 284 drivers/mtd/spi-nor/intel-spi.c u32 val; val 286 drivers/mtd/spi-nor/intel-spi.c return readl_poll_timeout(ispi->base + HSFSTS_CTL, val, val 287 drivers/mtd/spi-nor/intel-spi.c !(val & HSFSTS_CTL_SCIP), 40, val 293 drivers/mtd/spi-nor/intel-spi.c u32 val; val 295 drivers/mtd/spi-nor/intel-spi.c return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val, val 296 drivers/mtd/spi-nor/intel-spi.c !(val & SSFSTS_CTL_SCIP), 40, val 302 drivers/mtd/spi-nor/intel-spi.c u32 opmenu0, opmenu1, lvscc, uvscc, val; val 315 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + BYT_BCR); val 316 drivers/mtd/spi-nor/intel-spi.c if (!(val & BYT_BCR_WPD)) { val 317 drivers/mtd/spi-nor/intel-spi.c val |= BYT_BCR_WPD; val 318 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + BYT_BCR); val 319 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + BYT_BCR); val 322 drivers/mtd/spi-nor/intel-spi.c ispi->writeable = !!(val & BYT_BCR_WPD); val 348 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); val 349 drivers/mtd/spi-nor/intel-spi.c val &= ~HSFSTS_CTL_FSMIE; val 350 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); val 377 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->sregs + SSFSTS_CTL); val 378 drivers/mtd/spi-nor/intel-spi.c val &= ~SSFSTS_CTL_FSMIE; val 379 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->sregs + SSFSTS_CTL); val 383 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); val 384 drivers/mtd/spi-nor/intel-spi.c ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN); val 431 drivers/mtd/spi-nor/intel-spi.c u32 val, status; val 434 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); val 435 drivers/mtd/spi-nor/intel-spi.c val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK); val 439 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FCYCLE_RDID; val 442 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FCYCLE_WRSR; val 445 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FCYCLE_RDSR; val 454 drivers/mtd/spi-nor/intel-spi.c val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT; val 455 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val 456 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FGO; val 457 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); val 475 drivers/mtd/spi-nor/intel-spi.c u32 val = 0, status; val 495 drivers/mtd/spi-nor/intel-spi.c val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS; val 496 drivers/mtd/spi-nor/intel-spi.c val |= ret << SSFSTS_CTL_COP_SHIFT; val 497 drivers/mtd/spi-nor/intel-spi.c val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE; val 498 drivers/mtd/spi-nor/intel-spi.c val |= SSFSTS_CTL_SCGO; val 510 drivers/mtd/spi-nor/intel-spi.c val |= SSFSTS_CTL_SPOP; val 515 drivers/mtd/spi-nor/intel-spi.c val |= SSFSTS_CTL_ACS; val 523 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->sregs + SSFSTS_CTL); val 611 drivers/mtd/spi-nor/intel-spi.c u32 val, status; val 640 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); val 641 drivers/mtd/spi-nor/intel-spi.c val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); val 642 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val 643 drivers/mtd/spi-nor/intel-spi.c val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; val 644 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FCYCLE_READ; val 645 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FGO; val 646 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); val 682 drivers/mtd/spi-nor/intel-spi.c u32 val, status; val 697 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); val 698 drivers/mtd/spi-nor/intel-spi.c val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); val 699 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val 700 drivers/mtd/spi-nor/intel-spi.c val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; val 701 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FCYCLE_WRITE; val 710 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FGO; val 711 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); val 744 drivers/mtd/spi-nor/intel-spi.c u32 val, status, cmd; val 778 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); val 779 drivers/mtd/spi-nor/intel-spi.c val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); val 780 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val 781 drivers/mtd/spi-nor/intel-spi.c val |= cmd; val 782 drivers/mtd/spi-nor/intel-spi.c val |= HSFSTS_CTL_FGO; val 783 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); val 146 drivers/mtd/spi-nor/mtk-quadspi.c u8 val = cmdval & 0x1f; val 150 drivers/mtd/spi-nor/mtk-quadspi.c !(reg & val), 100, 10000); val 228 drivers/mtd/spi-nor/mtk-quadspi.c u8 val; val 231 drivers/mtd/spi-nor/mtk-quadspi.c val = readb(mtk_nor->base + MTK_NOR_DUAL_REG); val 235 drivers/mtd/spi-nor/mtk-quadspi.c val &= ~MTK_NOR_4B_ADDR_EN; val 238 drivers/mtd/spi-nor/mtk-quadspi.c val |= MTK_NOR_4B_ADDR_EN; val 246 drivers/mtd/spi-nor/mtk-quadspi.c writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG); val 482 drivers/mtd/spi-nor/spi-nor.c static int write_sr(struct spi_nor *nor, u8 val) val 484 drivers/mtd/spi-nor/spi-nor.c nor->bouncebuf[0] = val; val 1438 drivers/mtd/spi-nor/spi-nor.c u8 shift = ffs(mask) - 1, pow, val; val 1482 drivers/mtd/spi-nor/spi-nor.c val = mask - (pow << shift); val 1483 drivers/mtd/spi-nor/spi-nor.c if (val & ~mask) val 1486 drivers/mtd/spi-nor/spi-nor.c if (!(val & mask)) val 1489 drivers/mtd/spi-nor/spi-nor.c status_new = (status_old & ~mask & ~SR_TB) | val; val 1518 drivers/mtd/spi-nor/spi-nor.c u8 shift = ffs(mask) - 1, pow, val; val 1563 drivers/mtd/spi-nor/spi-nor.c val = 0; /* fully unlocked */ val 1565 drivers/mtd/spi-nor/spi-nor.c val = mask - (pow << shift); val 1567 drivers/mtd/spi-nor/spi-nor.c if (val & ~mask) val 1571 drivers/mtd/spi-nor/spi-nor.c status_new = (status_old & ~mask & ~SR_TB) | val; val 1712 drivers/mtd/spi-nor/spi-nor.c int ret, val; val 1714 drivers/mtd/spi-nor/spi-nor.c val = read_sr(nor); val 1715 drivers/mtd/spi-nor/spi-nor.c if (val < 0) val 1716 drivers/mtd/spi-nor/spi-nor.c return val; val 1717 drivers/mtd/spi-nor/spi-nor.c if (val & SR_QUAD_EN_MX) val 1722 drivers/mtd/spi-nor/spi-nor.c write_sr(nor, val | SR_QUAD_EN_MX); val 99 drivers/mtd/ubi/block.c static int __init ubiblock_set_param(const char *val, val 109 drivers/mtd/ubi/block.c if (!val) val 112 drivers/mtd/ubi/block.c len = strnlen(val, UBIBLOCK_PARAM_LEN); val 120 drivers/mtd/ubi/block.c val, UBIBLOCK_PARAM_LEN); val 124 drivers/mtd/ubi/block.c strcpy(buf, val); val 1350 drivers/mtd/ubi/build.c static int ubi_mtd_param_parse(const char *val, const struct kernel_param *kp) val 1358 drivers/mtd/ubi/build.c if (!val) val 1367 drivers/mtd/ubi/build.c len = strnlen(val, MTD_PARAM_LEN_MAX); val 1370 drivers/mtd/ubi/build.c val, MTD_PARAM_LEN_MAX); val 1379 drivers/mtd/ubi/build.c strcpy(buf, val); val 1389 drivers/mtd/ubi/build.c pr_err("UBI error: too many arguments at \"%s\"\n", val); val 255 drivers/mtd/ubi/debug.c int val; val 263 drivers/mtd/ubi/debug.c val = d->chk_gen; val 265 drivers/mtd/ubi/debug.c val = d->chk_io; val 267 drivers/mtd/ubi/debug.c val = d->chk_fastmap; val 269 drivers/mtd/ubi/debug.c val = d->disable_bgt; val 271 drivers/mtd/ubi/debug.c val = d->emulate_bitflips; val 273 drivers/mtd/ubi/debug.c val = d->emulate_io_failures; val 295 drivers/mtd/ubi/debug.c if (val) val 319 drivers/mtd/ubi/debug.c int val; val 341 drivers/mtd/ubi/debug.c if (kstrtoint(buf, 0, &val) != 0) val 344 drivers/mtd/ubi/debug.c d->emulate_power_cut = val; val 349 drivers/mtd/ubi/debug.c val = 1; val 351 drivers/mtd/ubi/debug.c val = 0; val 358 drivers/mtd/ubi/debug.c d->chk_gen = val; val 360 drivers/mtd/ubi/debug.c d->chk_io = val; val 362 drivers/mtd/ubi/debug.c d->chk_fastmap = val; val 364 drivers/mtd/ubi/debug.c d->disable_bgt = val; val 366 drivers/mtd/ubi/debug.c d->emulate_bitflips = val; val 368 drivers/mtd/ubi/debug.c d->emulate_io_failures = val; val 122 drivers/net/arcnet/com20020.h int ioaddr, int val) val 124 drivers/net/arcnet/com20020.h if (val < 4) { val 125 drivers/net/arcnet/com20020.h lp->config = (lp->config & ~0x03) | val; val 128 drivers/net/arcnet/com20020.h arcnet_outb(val, ioaddr, COM20020_REG_W_SUBADR); val 665 drivers/net/bonding/bond_3ad.c static void __set_agg_ports_ready(struct aggregator *aggregator, int val) val 671 drivers/net/bonding/bond_3ad.c if (val) val 2720 drivers/net/bonding/bond_3ad.c u64 val; val 2722 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->lacpdu_rx); val 2723 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_LACPDU_RX, val, val 2726 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->lacpdu_tx); val 2727 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_LACPDU_TX, val, val 2730 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->lacpdu_unknown_rx); val 2731 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_LACPDU_UNKNOWN_RX, val, val 2734 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->lacpdu_illegal_rx); val 2735 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_LACPDU_ILLEGAL_RX, val, val 2739 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->marker_rx); val 2740 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_MARKER_RX, val, val 2743 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->marker_tx); val 2744 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_MARKER_TX, val, val 2747 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->marker_resp_rx); val 2748 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_MARKER_RESP_RX, val, val 2751 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->marker_resp_tx); val 2752 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_MARKER_RESP_TX, val, val 2755 drivers/net/bonding/bond_3ad.c val = atomic64_read(&stats->marker_unknown_rx); val 2756 drivers/net/bonding/bond_3ad.c if (nla_put_u64_64bit(skb, BOND_3AD_STAT_MARKER_UNKNOWN_RX, val, val 455 drivers/net/bonding/bond_options.c const struct bond_opt_value *bond_opt_get_val(unsigned int option, u64 val) val 464 drivers/net/bonding/bond_options.c if (opt->values[i].value == val) val 486 drivers/net/bonding/bond_options.c static bool bond_opt_check_range(const struct bond_option *opt, u64 val) val 492 drivers/net/bonding/bond_options.c if (!maxval || (minval && val < minval->value) || val > maxval->value) val 509 drivers/net/bonding/bond_options.c struct bond_opt_value *val) val 519 drivers/net/bonding/bond_options.c return val; val 526 drivers/net/bonding/bond_options.c checkval = val->value != ULLONG_MAX; val 528 drivers/net/bonding/bond_options.c if (!val->string) val 530 drivers/net/bonding/bond_options.c p = strchr(val->string, '\n'); val 533 drivers/net/bonding/bond_options.c for (p = val->string; *p; p++) val 540 drivers/net/bonding/bond_options.c rv = sscanf(val->string, "%32s", valstr); val 542 drivers/net/bonding/bond_options.c rv = sscanf(val->string, "%llu", &val->value); val 552 drivers/net/bonding/bond_options.c if (val->value == tbl[i].value) val 567 drivers/net/bonding/bond_options.c if (checkval && bond_opt_check_range(opt, val->value)) val 568 drivers/net/bonding/bond_options.c ret = val; val 604 drivers/net/bonding/bond_options.c int error, const struct bond_opt_value *val) val 611 drivers/net/bonding/bond_options.c if (val) { val 612 drivers/net/bonding/bond_options.c if (val->string) { val 614 drivers/net/bonding/bond_options.c p = strchr(val->string, '\n'); val 618 drivers/net/bonding/bond_options.c opt->name, val->string); val 621 drivers/net/bonding/bond_options.c opt->name, val->value); val 658 drivers/net/bonding/bond_options.c unsigned int option, struct bond_opt_value *val) val 667 drivers/net/bonding/bond_options.c if (WARN_ON(!val) || WARN_ON(!opt)) val 672 drivers/net/bonding/bond_options.c retval = bond_opt_parse(opt, val); val 680 drivers/net/bonding/bond_options.c bond_opt_error_interpret(bond, opt, ret, val); val 696 drivers/net/bonding/bond_options.c unsigned int option, struct bond_opt_value *val) val 702 drivers/net/bonding/bond_options.c ret = __bond_opt_set(bond, option, val); val 202 drivers/net/bonding/bond_sysfs.c const struct bond_opt_value *val; val 204 drivers/net/bonding/bond_sysfs.c val = bond_opt_get_val(BOND_OPT_MODE, BOND_MODE(bond)); val 206 drivers/net/bonding/bond_sysfs.c return sprintf(buf, "%s %d\n", val->string, BOND_MODE(bond)); val 216 drivers/net/bonding/bond_sysfs.c const struct bond_opt_value *val; val 218 drivers/net/bonding/bond_sysfs.c val = bond_opt_get_val(BOND_OPT_XMIT_HASH, bond->params.xmit_policy); val 220 drivers/net/bonding/bond_sysfs.c return sprintf(buf, "%s %d\n", val->string, bond->params.xmit_policy); val 231 drivers/net/bonding/bond_sysfs.c const struct bond_opt_value *val; val 233 drivers/net/bonding/bond_sysfs.c val = bond_opt_get_val(BOND_OPT_ARP_VALIDATE, val 236 drivers/net/bonding/bond_sysfs.c return sprintf(buf, "%s %d\n", val->string, bond->params.arp_validate); val 247 drivers/net/bonding/bond_sysfs.c const struct bond_opt_value *val; val 249 drivers/net/bonding/bond_sysfs.c val = bond_opt_get_val(BOND_OPT_ARP_ALL_TARGETS, val 252 drivers/net/bonding/bond_sysfs.c val->string, bond->params.arp_all_targets); val 263 drivers/net/bonding/bond_sysfs.c const struct bond_opt_value *val; val 265 drivers/net/bonding/bond_sysfs.c val = bond_opt_get_val(BOND_OPT_FAIL_OVER_MAC, val 268 drivers/net/bonding/bond_sysfs.c return sprintf(buf, "%s %d\n", val->string, bond->params.fail_over_mac); val 348 drivers/net/bonding/bond_sysfs.c const struct bond_opt_value *val; val 350 drivers/net/bonding/bond_sysfs.c val = bond_opt_get_val(BOND_OPT_LACP_RATE, bond->params.lacp_fast); val 352 drivers/net/bonding/bond_sysfs.c return sprintf(buf, "%s %d\n", val->string, bond->params.lacp_fast); val 373 drivers/net/bonding/bond_sysfs.c const struct bond_opt_value *val; val 375 drivers/net/bonding/bond_sysfs.c val = bond_opt_get_val(BOND_OPT_AD_SELECT, bond->params.ad_select); val 377 drivers/net/bonding/bond_sysfs.c return sprintf(buf, "%s %d\n", val->string, bond->params.ad_select); val 433 drivers/net/bonding/bond_sysfs.c const struct bond_opt_value *val; val 435 drivers/net/bonding/bond_sysfs.c val = bond_opt_get_val(BOND_OPT_PRIMARY_RESELECT, val 439 drivers/net/bonding/bond_sysfs.c val->string, bond->params.primary_reselect); val 1246 drivers/net/can/c_can/c_can.c u32 val; val 1256 drivers/net/can/c_can/c_can.c val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); val 1257 drivers/net/can/c_can/c_can.c val |= CONTROL_EX_PDR; val 1258 drivers/net/can/c_can/c_can.c priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); val 1280 drivers/net/can/c_can/c_can.c u32 val; val 1294 drivers/net/can/c_can/c_can.c val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); val 1295 drivers/net/can/c_can/c_can.c val &= ~CONTROL_EX_PDR; val 1296 drivers/net/can/c_can/c_can.c priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); val 1297 drivers/net/can/c_can/c_can.c val = priv->read_reg(priv, C_CAN_CTRL_REG); val 1298 drivers/net/can/c_can/c_can.c val &= ~CONTROL_INIT; val 1299 drivers/net/can/c_can/c_can.c priv->write_reg(priv, C_CAN_CTRL_REG, val); val 205 drivers/net/can/c_can/c_can.h void (*write_reg) (const struct c_can_priv *priv, enum reg index, u16 val); val 207 drivers/net/can/c_can/c_can.h void (*write_reg32) (const struct c_can_priv *priv, enum reg index, u32 val); val 57 drivers/net/can/c_can/c_can_pci.c enum reg index, u16 val) val 59 drivers/net/can/c_can/c_can_pci.c writew(val, priv->base + priv->regs[index]); val 69 drivers/net/can/c_can/c_can_pci.c enum reg index, u16 val) val 71 drivers/net/can/c_can/c_can_pci.c writew(val, priv->base + 2 * priv->regs[index]); val 81 drivers/net/can/c_can/c_can_pci.c enum reg index, u16 val) val 83 drivers/net/can/c_can/c_can_pci.c iowrite32((u32)val, priv->base + 2 * priv->regs[index]); val 88 drivers/net/can/c_can/c_can_pci.c u32 val; val 90 drivers/net/can/c_can/c_can_pci.c val = priv->read_reg(priv, index); val 91 drivers/net/can/c_can/c_can_pci.c val |= ((u32) priv->read_reg(priv, index + 1)) << 16; val 93 drivers/net/can/c_can/c_can_pci.c return val; val 97 drivers/net/can/c_can/c_can_pci.c u32 val) val 99 drivers/net/can/c_can/c_can_pci.c priv->write_reg(priv, index + 1, val >> 16); val 100 drivers/net/can/c_can/c_can_pci.c priv->write_reg(priv, index, val); val 57 drivers/net/can/c_can/c_can_platform.c enum reg index, u16 val) val 59 drivers/net/can/c_can/c_can_platform.c writew(val, priv->base + priv->regs[index]); val 69 drivers/net/can/c_can/c_can_platform.c enum reg index, u16 val) val 71 drivers/net/can/c_can/c_can_platform.c writew(val, priv->base + 2 * priv->regs[index]); val 75 drivers/net/can/c_can/c_can_platform.c u32 mask, u32 val) val 82 drivers/net/can/c_can/c_can_platform.c val &= mask; val 92 drivers/net/can/c_can/c_can_platform.c } while ((ctrl & mask) != val); val 144 drivers/net/can/c_can/c_can_platform.c u32 val; val 146 drivers/net/can/c_can/c_can_platform.c val = priv->read_reg(priv, index); val 147 drivers/net/can/c_can/c_can_platform.c val |= ((u32) priv->read_reg(priv, index + 1)) << 16; val 149 drivers/net/can/c_can/c_can_platform.c return val; val 153 drivers/net/can/c_can/c_can_platform.c u32 val) val 155 drivers/net/can/c_can/c_can_platform.c priv->write_reg(priv, index + 1, val >> 16); val 156 drivers/net/can/c_can/c_can_platform.c priv->write_reg(priv, index, val); val 165 drivers/net/can/c_can/c_can_platform.c u32 val) val 167 drivers/net/can/c_can/c_can_platform.c writel(val, priv->base + priv->regs[index]); val 173 drivers/net/can/cc770/cc770.h void (*write_reg)(const struct cc770_priv *priv, int reg, u8 val); val 118 drivers/net/can/cc770/cc770_isa.c int reg, u8 val) val 120 drivers/net/can/cc770/cc770_isa.c writeb(val, priv->reg_base + reg); val 129 drivers/net/can/cc770/cc770_isa.c int reg, u8 val) val 131 drivers/net/can/cc770/cc770_isa.c outb(val, (unsigned long)priv->reg_base + reg); val 139 drivers/net/can/cc770/cc770_isa.c u8 val; val 143 drivers/net/can/cc770/cc770_isa.c val = inb(base + 1); val 146 drivers/net/can/cc770/cc770_isa.c return val; val 150 drivers/net/can/cc770/cc770_isa.c int reg, u8 val) val 157 drivers/net/can/cc770/cc770_isa.c outb(val, base + 1); val 65 drivers/net/can/cc770/cc770_platform.c u8 val) val 67 drivers/net/can/cc770/cc770_platform.c iowrite8(val, priv->reg_base + reg); val 292 drivers/net/can/flexcan.c void (*write)(u32 val, void __iomem *addr); val 358 drivers/net/can/flexcan.c static inline void flexcan_write_be(u32 val, void __iomem *addr) val 360 drivers/net/can/flexcan.c iowrite32be(val, addr); val 368 drivers/net/can/flexcan.c static inline void flexcan_write_le(u32 val, void __iomem *addr) val 370 drivers/net/can/flexcan.c iowrite32(val, addr); val 323 drivers/net/can/grcan.c static inline void grcan_write_reg(u32 __iomem *reg, u32 val) val 325 drivers/net/can/grcan.c iowrite32be(val, reg); val 333 drivers/net/can/grcan.c static inline void grcan_write_reg(u32 __iomem *reg, u32 val) val 335 drivers/net/can/grcan.c iowrite32(val, reg); val 1494 drivers/net/can/grcan.c u8 val; \ val 1498 drivers/net/can/grcan.c ret = kstrtou8(buf, 0, &val); \ val 1499 drivers/net/can/grcan.c if (ret < 0 || val > 1) \ val 1501 drivers/net/can/grcan.c priv->config.name = val; \ val 329 drivers/net/can/m_can/m_can.c u32 val) val 331 drivers/net/can/m_can/m_can.c cdev->ops->write_reg(cdev, reg, val); val 344 drivers/net/can/m_can/m_can.c u32 fpi, unsigned int offset, u32 val) val 349 drivers/net/can/m_can/m_can.c cdev->ops->write_fifo(cdev, addr_offset, val); val 353 drivers/net/can/m_can/m_can.c u32 fpi, u32 val) val 355 drivers/net/can/m_can/m_can.c cdev->ops->write_fifo(cdev, fpi, val); val 375 drivers/net/can/m_can/m_can.c u32 val = 0; val 397 drivers/net/can/m_can/m_can.c val = CCCR_INIT | CCCR_CCE; val 399 drivers/net/can/m_can/m_can.c while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { val 65 drivers/net/can/m_can/m_can.h int (*write_reg)(struct m_can_classdev *cdev, int reg, int val); val 68 drivers/net/can/m_can/m_can.h int val); val 31 drivers/net/can/m_can/m_can_platform.c static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val) val 35 drivers/net/can/m_can/m_can_platform.c writel(val, priv->base + reg); val 40 drivers/net/can/m_can/m_can_platform.c static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val) val 44 drivers/net/can/m_can/m_can_platform.c writel(val, priv->mram_base + offset); val 190 drivers/net/can/m_can/tcan4x5x.c size_t reg_len, const void *val, val 199 drivers/net/can/m_can/tcan4x5x.c { .tx_buf = val, .len = val_len, }, val 214 drivers/net/can/m_can/tcan4x5x.c const u32 *val = data + 4; val 216 drivers/net/can/m_can/tcan4x5x.c return regmap_spi_gather_write(context, reg, 4, val, count - 4); val 221 drivers/net/can/m_can/tcan4x5x.c const void *val, size_t val_len, val 234 drivers/net/can/m_can/tcan4x5x.c void *val, size_t val_size) val 241 drivers/net/can/m_can/tcan4x5x.c return spi_write_then_read(spi, &addr, reg_size, (u32 *)val, val_size); val 258 drivers/net/can/m_can/tcan4x5x.c u32 val; val 260 drivers/net/can/m_can/tcan4x5x.c regmap_read(priv->regmap, priv->reg_offset + reg, &val); val 262 drivers/net/can/m_can/tcan4x5x.c return val; val 268 drivers/net/can/m_can/tcan4x5x.c u32 val; val 270 drivers/net/can/m_can/tcan4x5x.c regmap_read(priv->regmap, priv->mram_start + addr_offset, &val); val 272 drivers/net/can/m_can/tcan4x5x.c return val; val 275 drivers/net/can/m_can/tcan4x5x.c static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val) val 279 drivers/net/can/m_can/tcan4x5x.c return regmap_write(priv->regmap, priv->reg_offset + reg, val); val 283 drivers/net/can/m_can/tcan4x5x.c int addr_offset, int val) val 287 drivers/net/can/m_can/tcan4x5x.c return regmap_write(priv->regmap, priv->mram_start + addr_offset, val); val 302 drivers/net/can/m_can/tcan4x5x.c int reg, int val) val 306 drivers/net/can/m_can/tcan4x5x.c return regmap_write(priv->regmap, reg, val); val 47 drivers/net/can/mscan/mpc5xxx_can.c u32 val; val 86 drivers/net/can/mscan/mpc5xxx_can.c val = in_be32(&cdm->rstcfg); val 88 drivers/net/can/mscan/mpc5xxx_can.c freq *= (val & (1 << 5)) ? 8 : 4; val 89 drivers/net/can/mscan/mpc5xxx_can.c freq /= (val & (1 << 6)) ? 12 : 16; val 222 drivers/net/can/peak_canfd/peak_pciefd_main.c u32 val, u16 reg) val 224 drivers/net/can/peak_canfd/peak_pciefd_main.c writel(val, priv->reg_base + reg); val 235 drivers/net/can/peak_canfd/peak_pciefd_main.c u32 val, u16 reg) val 237 drivers/net/can/peak_canfd/peak_pciefd_main.c writel(val, priv->reg_base + reg); val 558 drivers/net/can/rcar/rcar_canfd.c static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg) val 563 drivers/net/can/rcar/rcar_canfd.c data |= (val & mask); val 572 drivers/net/can/rcar/rcar_canfd.c static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val) val 574 drivers/net/can/rcar/rcar_canfd.c writel(val, base + (offset)); val 577 drivers/net/can/rcar/rcar_canfd.c static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val) val 579 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(val, val, base + (reg)); val 582 drivers/net/can/rcar/rcar_canfd.c static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val) val 584 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(val, 0, base + (reg)); val 588 drivers/net/can/rcar/rcar_canfd.c u32 mask, u32 val) val 590 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(mask, val, base + (reg)); val 1540 drivers/net/can/rcar/rcar_canfd.c u32 val, ch = priv->channel; val 1543 drivers/net/can/rcar/rcar_canfd.c val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch)); val 1544 drivers/net/can/rcar/rcar_canfd.c bec->txerr = RCANFD_CSTS_TECCNT(val); val 1545 drivers/net/can/rcar/rcar_canfd.c bec->rxerr = RCANFD_CSTS_RECCNT(val); val 29 drivers/net/can/rx-offload.c static inline unsigned int can_rx_offload_inc(struct can_rx_offload *offload, unsigned int *val) val 32 drivers/net/can/rx-offload.c return (*val)++; val 34 drivers/net/can/rx-offload.c return (*val)--; val 118 drivers/net/can/sja1000/ems_pci.c int port, u8 val) val 120 drivers/net/can/sja1000/ems_pci.c writeb(val, priv->reg_base + (port * 4)); val 138 drivers/net/can/sja1000/ems_pci.c int port, u8 val) val 140 drivers/net/can/sja1000/ems_pci.c writeb(val, priv->reg_base + port); val 77 drivers/net/can/sja1000/ems_pcmcia.c u8 val) val 79 drivers/net/can/sja1000/ems_pcmcia.c writeb(val, priv->reg_base + port); val 62 drivers/net/can/sja1000/f81601.c u8 val) val 68 drivers/net/can/sja1000/f81601.c writeb(val, priv->reg_base + port); val 113 drivers/net/can/sja1000/kvaser_pci.c int port, u8 val) val 115 drivers/net/can/sja1000/kvaser_pci.c iowrite8(val, priv->reg_base + port); val 156 drivers/net/can/sja1000/peak_pci.c int port, u8 val); val 394 drivers/net/can/sja1000/peak_pci.c int port, u8 val) val 402 drivers/net/can/sja1000/peak_pci.c switch (val) { val 417 drivers/net/can/sja1000/peak_pci.c peak_pci_write_reg(priv, port, val); val 530 drivers/net/can/sja1000/peak_pci.c int port, u8 val) val 532 drivers/net/can/sja1000/peak_pci.c writeb(val, priv->reg_base + (port << 2)); val 414 drivers/net/can/sja1000/plx_pci.c static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) val 416 drivers/net/can/sja1000/plx_pci.c iowrite8(val, priv->reg_base + port); val 631 drivers/net/can/sja1000/plx_pci.c u32 val; val 741 drivers/net/can/sja1000/plx_pci.c val = ioread32(card->conf_addr + PLX_INTCSR); val 743 drivers/net/can/sja1000/plx_pci.c val |= PLX_LINT1_EN | PLX_PCI_INT_EN; val 745 drivers/net/can/sja1000/plx_pci.c val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; val 746 drivers/net/can/sja1000/plx_pci.c iowrite32(val, card->conf_addr + PLX_INTCSR); val 85 drivers/net/can/sja1000/sja1000.c static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val) val 94 drivers/net/can/sja1000/sja1000.c priv->write_reg(priv, SJA1000_CMR, val); val 159 drivers/net/can/sja1000/sja1000.h void (*write_reg) (const struct sja1000_priv *priv, int reg, u8 val); val 75 drivers/net/can/sja1000/sja1000_isa.c int reg, u8 val) val 77 drivers/net/can/sja1000/sja1000_isa.c writeb(val, priv->reg_base + reg); val 86 drivers/net/can/sja1000/sja1000_isa.c int reg, u8 val) val 88 drivers/net/can/sja1000/sja1000_isa.c outb(val, (unsigned long)priv->reg_base + reg); val 106 drivers/net/can/sja1000/sja1000_isa.c int reg, u8 val) val 112 drivers/net/can/sja1000/sja1000_isa.c outb(val, base + 1); val 47 drivers/net/can/sja1000/sja1000_platform.c static void sp_write_reg8(const struct sja1000_priv *priv, int reg, u8 val) val 49 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg); val 57 drivers/net/can/sja1000/sja1000_platform.c static void sp_write_reg16(const struct sja1000_priv *priv, int reg, u8 val) val 59 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg * 2); val 67 drivers/net/can/sja1000/sja1000_platform.c static void sp_write_reg32(const struct sja1000_priv *priv, int reg, u8 val) val 69 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg * 4); val 76 drivers/net/can/sja1000/sja1000_platform.c u8 val; val 80 drivers/net/can/sja1000/sja1000_platform.c val = ioread16(priv->reg_base + 2); val 83 drivers/net/can/sja1000/sja1000_platform.c return val; val 87 drivers/net/can/sja1000/sja1000_platform.c int reg, u8 val) val 94 drivers/net/can/sja1000/sja1000_platform.c iowrite16(val, priv->reg_base + 2); val 73 drivers/net/can/sja1000/tscan1.c static void tscan1_write(const struct sja1000_priv *priv, int reg, u8 val) val 75 drivers/net/can/sja1000/tscan1.c outb(val, (unsigned long)priv->reg_base + reg); val 573 drivers/net/can/softing/softing_main.c unsigned long val; val 576 drivers/net/can/softing/softing_main.c ret = kstrtoul(buf, 0, &val); val 579 drivers/net/can/softing/softing_main.c val &= 0xFF; val 588 drivers/net/can/softing/softing_main.c priv->output = val; val 234 drivers/net/can/spi/hi311x.c u8 val = 0; val 238 drivers/net/can/spi/hi311x.c val = priv->spi_rx_buf[1]; val 240 drivers/net/can/spi/hi311x.c return val; val 243 drivers/net/can/spi/hi311x.c static void hi3110_write(struct spi_device *spi, u8 reg, u8 val) val 248 drivers/net/can/spi/hi311x.c priv->spi_tx_buf[1] = val; val 165 drivers/net/can/spi/mcp251x.c #define GET_BYTE(val, byte) \ val 166 drivers/net/can/spi/mcp251x.c (((val) >> ((byte) * 8)) & 0xff) val 167 drivers/net/can/spi/mcp251x.c #define SET_BYTE(val, byte) \ val 168 drivers/net/can/spi/mcp251x.c (((val) & 0xff) << ((byte) * 8)) val 289 drivers/net/can/spi/mcp251x.c u8 val = 0; val 295 drivers/net/can/spi/mcp251x.c val = priv->spi_rx_buf[2]; val 297 drivers/net/can/spi/mcp251x.c return val; val 313 drivers/net/can/spi/mcp251x.c static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val) val 319 drivers/net/can/spi/mcp251x.c priv->spi_tx_buf[2] = val; val 325 drivers/net/can/spi/mcp251x.c u8 mask, u8 val) val 332 drivers/net/can/spi/mcp251x.c priv->spi_tx_buf[3] = val; val 222 drivers/net/can/sun4i_can.c static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val) val 227 drivers/net/can/sun4i_can.c writel(val, priv->base + SUN4I_REG_CMD_ADDR); val 217 drivers/net/can/ti_hecc.c static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val) val 219 drivers/net/can/ti_hecc.c __raw_writel(val, priv->hecc_ram + mbxno * 4); val 228 drivers/net/can/ti_hecc.c u32 reg, u32 val) val 230 drivers/net/can/ti_hecc.c __raw_writel(val, priv->mbx + mbxno * 0x10 + reg); val 238 drivers/net/can/ti_hecc.c static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) val 240 drivers/net/can/ti_hecc.c __raw_writel(val, priv->base + reg); val 562 drivers/net/can/usb/ems_usb.c static int ems_usb_control_cmd(struct ems_usb *dev, u8 val) val 571 drivers/net/can/usb/ems_usb.c cmd.msg.generic[0] = val; val 206 drivers/net/can/xilinx_can.c u32 val); val 289 drivers/net/can/xilinx_can.c u32 val) val 291 drivers/net/can/xilinx_can.c iowrite32(val, priv->reg_base + reg); val 316 drivers/net/can/xilinx_can.c u32 val) val 318 drivers/net/can/xilinx_can.c iowrite32be(val, priv->reg_base + reg); val 579 drivers/net/dsa/b53/b53_common.c u8 hdr_ctl, val; val 585 drivers/net/dsa/b53/b53_common.c val = BRCM_HDR_P8_EN; val 588 drivers/net/dsa/b53/b53_common.c val = BRCM_HDR_P7_EN; val 591 drivers/net/dsa/b53/b53_common.c val = BRCM_HDR_P5_EN; val 594 drivers/net/dsa/b53/b53_common.c val = 0; val 601 drivers/net/dsa/b53/b53_common.c hdr_ctl |= val; val 603 drivers/net/dsa/b53/b53_common.c hdr_ctl &= ~val; val 784 drivers/net/dsa/b53/b53_common.c static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) val 789 drivers/net/dsa/b53/b53_common.c return priv->ops->phy_write16(priv, addr, reg, val); val 791 drivers/net/dsa/b53/b53_common.c return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); val 899 drivers/net/dsa/b53/b53_common.c u64 val = 0; val 910 drivers/net/dsa/b53/b53_common.c b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); val 916 drivers/net/dsa/b53/b53_common.c val = val32; val 918 drivers/net/dsa/b53/b53_common.c data[i] = (u64)val; val 996 drivers/net/dsa/b53/b53_common.c u8 reg, val, off; val 1001 drivers/net/dsa/b53/b53_common.c val = PORT_OVERRIDE_EN; val 1004 drivers/net/dsa/b53/b53_common.c val = GMII_PO_EN; val 1008 drivers/net/dsa/b53/b53_common.c reg |= val; val 1019 drivers/net/dsa/b53/b53_common.c u8 reg, val, off; val 1024 drivers/net/dsa/b53/b53_common.c val = PORT_OVERRIDE_EN; val 1027 drivers/net/dsa/b53/b53_common.c val = GMII_PO_EN; val 1031 drivers/net/dsa/b53/b53_common.c reg |= val; val 79 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) val 88 drivers/net/dsa/b53/b53_mdio.c *val = mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR, val 94 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) val 103 drivers/net/dsa/b53/b53_mdio.c *val = mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR, REG_MII_DATA0); val 108 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) val 117 drivers/net/dsa/b53/b53_mdio.c *val = mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR, REG_MII_DATA0); val 118 drivers/net/dsa/b53/b53_mdio.c *val |= mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR, val 124 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) val 141 drivers/net/dsa/b53/b53_mdio.c *val = temp; val 146 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) val 163 drivers/net/dsa/b53/b53_mdio.c *val = temp; val 31 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) val 36 drivers/net/dsa/b53/b53_mmap.c *val = readb(regs + (page << 8) + reg); val 41 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) val 50 drivers/net/dsa/b53/b53_mmap.c *val = ioread16be(regs + (page << 8) + reg); val 52 drivers/net/dsa/b53/b53_mmap.c *val = readw(regs + (page << 8) + reg); val 57 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) val 66 drivers/net/dsa/b53/b53_mmap.c *val = ioread32be(regs + (page << 8) + reg); val 68 drivers/net/dsa/b53/b53_mmap.c *val = readl(regs + (page << 8) + reg); val 73 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) val 93 drivers/net/dsa/b53/b53_mmap.c *val = ((u64)hi << 16) | lo; val 106 drivers/net/dsa/b53/b53_mmap.c *val = ((u64)hi << 32) | lo; val 112 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) val 129 drivers/net/dsa/b53/b53_mmap.c *val = ((u64)hi << 32) | lo; val 229 drivers/net/dsa/b53/b53_priv.h u8 reg, val_type val) \ val 234 drivers/net/dsa/b53/b53_priv.h ret = dev->ops->type_op_size(dev, page, reg, val); \ val 42 drivers/net/dsa/b53/b53_spi.c static inline int b53_spi_read_reg(struct spi_device *spi, u8 reg, u8 *val, val 50 drivers/net/dsa/b53/b53_spi.c return spi_write_then_read(spi, txbuf, 2, val, len); val 141 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) val 143 drivers/net/dsa/b53/b53_spi.c return b53_spi_read(dev, page, reg, val, 1); val 146 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) val 148 drivers/net/dsa/b53/b53_spi.c int ret = b53_spi_read(dev, page, reg, (u8 *)val, 2); val 151 drivers/net/dsa/b53/b53_spi.c *val = le16_to_cpu(*val); val 156 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) val 158 drivers/net/dsa/b53/b53_spi.c int ret = b53_spi_read(dev, page, reg, (u8 *)val, 4); val 161 drivers/net/dsa/b53/b53_spi.c *val = le32_to_cpu(*val); val 166 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) val 170 drivers/net/dsa/b53/b53_spi.c *val = 0; val 171 drivers/net/dsa/b53/b53_spi.c ret = b53_spi_read(dev, page, reg, (u8 *)val, 6); val 173 drivers/net/dsa/b53/b53_spi.c *val = le64_to_cpu(*val); val 178 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) val 180 drivers/net/dsa/b53/b53_spi.c int ret = b53_spi_read(dev, page, reg, (u8 *)val, 8); val 183 drivers/net/dsa/b53/b53_spi.c *val = le64_to_cpu(*val); val 153 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) val 167 drivers/net/dsa/b53/b53_srab.c *val = readl(regs + B53_SRAB_RD_L) & 0xff; val 175 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) val 189 drivers/net/dsa/b53/b53_srab.c *val = readl(regs + B53_SRAB_RD_L) & 0xffff; val 197 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) val 211 drivers/net/dsa/b53/b53_srab.c *val = readl(regs + B53_SRAB_RD_L); val 219 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) val 233 drivers/net/dsa/b53/b53_srab.c *val = readl(regs + B53_SRAB_RD_L); val 234 drivers/net/dsa/b53/b53_srab.c *val += ((u64)readl(regs + B53_SRAB_RD_H) & 0xffff) << 32; val 242 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) val 256 drivers/net/dsa/b53/b53_srab.c *val = readl(regs + B53_SRAB_RD_L); val 257 drivers/net/dsa/b53/b53_srab.c *val += (u64)readl(regs + B53_SRAB_RD_H) << 32; val 259 drivers/net/dsa/bcm_sf2.c int regnum, u16 val) val 280 drivers/net/dsa/bcm_sf2.c core_writel(priv, val, reg); val 303 drivers/net/dsa/bcm_sf2.c u16 val) val 311 drivers/net/dsa/bcm_sf2.c return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); val 314 drivers/net/dsa/bcm_sf2.c regnum, val); val 818 drivers/net/dsa/bcm_sf2.c u8 *val) val 822 drivers/net/dsa/bcm_sf2.c *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); val 828 drivers/net/dsa/bcm_sf2.c u16 *val) val 832 drivers/net/dsa/bcm_sf2.c *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); val 838 drivers/net/dsa/bcm_sf2.c u32 *val) val 842 drivers/net/dsa/bcm_sf2.c *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); val 848 drivers/net/dsa/bcm_sf2.c u64 *val) val 852 drivers/net/dsa/bcm_sf2.c *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); val 130 drivers/net/dsa/bcm_sf2.h u32 val, u32 off) \ val 132 drivers/net/dsa/bcm_sf2.h writel_relaxed(val, priv->name + off); \ val 150 drivers/net/dsa/bcm_sf2.h static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \ val 154 drivers/net/dsa/bcm_sf2.h reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \ val 155 drivers/net/dsa/bcm_sf2.h name##_writel(priv, lower_32_bits(val), off); \ val 179 drivers/net/dsa/bcm_sf2.h static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) val 182 drivers/net/dsa/bcm_sf2.h writel_relaxed(val, priv->core + tmp); val 190 drivers/net/dsa/bcm_sf2.h static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off) val 192 drivers/net/dsa/bcm_sf2.h writel_relaxed(val, priv->reg + priv->reg_offsets[off]); val 474 drivers/net/dsa/bcm_sf2_cfp.c u32 reg, tmp, val, offset; val 481 drivers/net/dsa/bcm_sf2_cfp.c val = (u32)be16_to_cpu(port) << 8 | ((reg >> 8) & 0xff); val 486 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, val, offset); val 493 drivers/net/dsa/bcm_sf2_cfp.c val = (u32)(reg & 0xff) << 24 | (u32)(reg >> 16) << 8 | val 499 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, val, offset); val 506 drivers/net/dsa/bcm_sf2_cfp.c val = (u32)(tmp & 0xff) << 24 | (u32)(tmp >> 16) << 8 | val 512 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, val, offset); val 519 drivers/net/dsa/bcm_sf2_cfp.c val = (u32)(reg & 0xff) << 24 | (u32)(reg >> 16) << 8 | val 525 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, val, offset); val 28 drivers/net/dsa/dsa_loop.c unsigned long val; val 114 drivers/net/dsa/dsa_loop.c data[i] = ps->ports[port].mib[i].val; val 125 drivers/net/dsa/dsa_loop.c ps->ports[port].mib[DSA_LOOP_PHY_READ_ERR].val++; val 127 drivers/net/dsa/dsa_loop.c ps->ports[port].mib[DSA_LOOP_PHY_READ_OK].val++; val 141 drivers/net/dsa/dsa_loop.c ps->ports[port].mib[DSA_LOOP_PHY_WRITE_ERR].val++; val 143 drivers/net/dsa/dsa_loop.c ps->ports[port].mib[DSA_LOOP_PHY_WRITE_OK].val++; val 268 drivers/net/dsa/lan9303-core.c u32 val; val 273 drivers/net/dsa/lan9303-core.c ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); val 277 drivers/net/dsa/lan9303-core.c return val & 0xffff; val 280 drivers/net/dsa/lan9303-core.c static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) val 285 drivers/net/dsa/lan9303-core.c return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); val 297 drivers/net/dsa/lan9303-core.c u32 val; val 299 drivers/net/dsa/lan9303-core.c val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); val 300 drivers/net/dsa/lan9303-core.c val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); val 309 drivers/net/dsa/lan9303-core.c ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); val 318 drivers/net/dsa/lan9303-core.c ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); val 324 drivers/net/dsa/lan9303-core.c return val & 0xffff; val 332 drivers/net/dsa/lan9303-core.c int regnum, u16 val) val 348 drivers/net/dsa/lan9303-core.c ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); val 372 drivers/net/dsa/lan9303-core.c static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) val 387 drivers/net/dsa/lan9303-core.c ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); val 404 drivers/net/dsa/lan9303-core.c static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) val 432 drivers/net/dsa/lan9303-core.c ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); val 441 drivers/net/dsa/lan9303-core.c u32 val, u32 mask) val 450 drivers/net/dsa/lan9303-core.c reg = (reg & ~mask) | val; val 456 drivers/net/dsa/lan9303-core.c u16 regnum, u32 val) val 459 drivers/net/dsa/lan9303-core.c chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); val 463 drivers/net/dsa/lan9303-core.c u16 regnum, u32 *val) val 466 drivers/net/dsa/lan9303-core.c chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); val 758 drivers/net/dsa/lan9303-core.c u32 val; val 770 drivers/net/dsa/lan9303-core.c val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0; val 771 drivers/net/dsa/lan9303-core.c return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val); val 1027 drivers/net/dsa/lan9303-core.c u16 val) val 1033 drivers/net/dsa/lan9303-core.c return lan9303_virt_phy_reg_write(chip, regnum, val); val 1037 drivers/net/dsa/lan9303-core.c return chip->ops->phy_write(chip, phy, regnum, val); val 25 drivers/net/dsa/lan9303_mdio.c static void lan9303_mdio_real_write(struct mdio_device *mdio, int reg, u16 val) val 27 drivers/net/dsa/lan9303_mdio.c mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val); val 30 drivers/net/dsa/lan9303_mdio.c static int lan9303_mdio_write(void *ctx, uint32_t reg, uint32_t val) val 36 drivers/net/dsa/lan9303_mdio.c lan9303_mdio_real_write(sw_dev->device, reg, val & 0xffff); val 37 drivers/net/dsa/lan9303_mdio.c lan9303_mdio_real_write(sw_dev->device, reg + 2, (val >> 16) & 0xffff); val 48 drivers/net/dsa/lan9303_mdio.c static int lan9303_mdio_read(void *ctx, uint32_t reg, uint32_t *val) val 54 drivers/net/dsa/lan9303_mdio.c *val = lan9303_mdio_real_read(sw_dev->device, reg); val 55 drivers/net/dsa/lan9303_mdio.c *val |= (lan9303_mdio_real_read(sw_dev->device, reg + 2) << 16); val 62 drivers/net/dsa/lan9303_mdio.c u16 val) val 66 drivers/net/dsa/lan9303_mdio.c return mdiobus_write_nested(sw_dev->device->bus, phy, reg, val); val 263 drivers/net/dsa/lantiq_gswip.c u16 val[5]; val 327 drivers/net/dsa/lantiq_gswip.c static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) val 329 drivers/net/dsa/lantiq_gswip.c __raw_writel(val, priv->gswip + (offset * 4)); val 335 drivers/net/dsa/lantiq_gswip.c u32 val = gswip_switch_r(priv, offset); val 337 drivers/net/dsa/lantiq_gswip.c val &= ~(clear); val 338 drivers/net/dsa/lantiq_gswip.c val |= set; val 339 drivers/net/dsa/lantiq_gswip.c gswip_switch_w(priv, val, offset); val 345 drivers/net/dsa/lantiq_gswip.c u32 val; val 347 drivers/net/dsa/lantiq_gswip.c return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, val 348 drivers/net/dsa/lantiq_gswip.c (val & cleared) == 0, 20, 50000); val 356 drivers/net/dsa/lantiq_gswip.c static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) val 358 drivers/net/dsa/lantiq_gswip.c __raw_writel(val, priv->mdio + (offset * 4)); val 364 drivers/net/dsa/lantiq_gswip.c u32 val = gswip_mdio_r(priv, offset); val 366 drivers/net/dsa/lantiq_gswip.c val &= ~(clear); val 367 drivers/net/dsa/lantiq_gswip.c val |= set; val 368 drivers/net/dsa/lantiq_gswip.c gswip_mdio_w(priv, val, offset); val 376 drivers/net/dsa/lantiq_gswip.c static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) val 378 drivers/net/dsa/lantiq_gswip.c __raw_writel(val, priv->mii + (offset * 4)); val 384 drivers/net/dsa/lantiq_gswip.c u32 val = gswip_mii_r(priv, offset); val 386 drivers/net/dsa/lantiq_gswip.c val &= ~(clear); val 387 drivers/net/dsa/lantiq_gswip.c val |= set; val 388 drivers/net/dsa/lantiq_gswip.c gswip_mii_w(priv, val, offset); val 438 drivers/net/dsa/lantiq_gswip.c static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) val 449 drivers/net/dsa/lantiq_gswip.c gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); val 531 drivers/net/dsa/lantiq_gswip.c for (i = 0; i < ARRAY_SIZE(tbl->val); i++) val 532 drivers/net/dsa/lantiq_gswip.c tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); val 568 drivers/net/dsa/lantiq_gswip.c for (i = 0; i < ARRAY_SIZE(tbl->val); i++) val 569 drivers/net/dsa/lantiq_gswip.c gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); val 614 drivers/net/dsa/lantiq_gswip.c vlan_active.val[0] = port + 1 /* fid */; val 627 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[0] = 0 /* vid */; val 628 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); val 629 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] = 0; val 876 drivers/net/dsa/lantiq_gswip.c vlan_active.val[0] = fid; val 939 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[0] = 0; val 953 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] |= BIT(cpu_port); val 954 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] |= BIT(port); val 1007 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[0] = vid; val 1020 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[0] = vid; val 1022 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] |= BIT(cpu_port); val 1023 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] |= BIT(cpu_port); val 1024 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] |= BIT(port); val 1026 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] &= ~BIT(port); val 1028 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] |= BIT(port); val 1077 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] &= ~BIT(port); val 1078 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] &= ~BIT(port); val 1086 drivers/net/dsa/lantiq_gswip.c if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { val 1252 drivers/net/dsa/lantiq_gswip.c if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) val 1255 drivers/net/dsa/lantiq_gswip.c if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) val 1331 drivers/net/dsa/lantiq_gswip.c mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ val 1332 drivers/net/dsa/lantiq_gswip.c mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; val 1383 drivers/net/dsa/lantiq_gswip.c if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { val 1384 drivers/net/dsa/lantiq_gswip.c if (mac_bridge.val[0] & BIT(port)) val 1387 drivers/net/dsa/lantiq_gswip.c if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) val 84 drivers/net/dsa/lantiq_pce.h #define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \ val 85 drivers/net/dsa/lantiq_pce.h { val, msk, ((ns) << 10 | (out) << 4 | (len) >> 1),\ val 458 drivers/net/dsa/microchip/ksz8795.c static void ksz8795_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) val 546 drivers/net/dsa/microchip/ksz8795.c *val = data; val 549 drivers/net/dsa/microchip/ksz8795.c static void ksz8795_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) val 558 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_RESET) val 562 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_HP_MDIX) val 570 drivers/net/dsa/microchip/ksz8795.c if (!(val & PHY_AUTO_NEG_ENABLE)) val 578 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_SPEED_100MBIT) val 582 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_FULL_DUPLEX) val 590 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_LED_DISABLE) val 594 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_TRANSMIT_DISABLE) val 598 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_AUTO_NEG_RESTART) val 602 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_POWER_DOWN) val 606 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_AUTO_MDIX_DISABLE) val 610 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_FORCE_MDIX) val 614 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_LOOPBACK) val 629 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_AUTO_NEG_SYM_PAUSE) val 631 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_AUTO_NEG_100BTX_FD) val 633 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_AUTO_NEG_100BTX) val 635 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_AUTO_NEG_10BT_FD) val 637 drivers/net/dsa/microchip/ksz8795.c if (val & PHY_AUTO_NEG_10BT) val 1162 drivers/net/dsa/microchip/ksz8795.c u8 val; val 1165 drivers/net/dsa/microchip/ksz8795.c ksz_read8(dev, REG_PORT_1_STATUS_0, &val); val 1166 drivers/net/dsa/microchip/ksz8795.c if (val & PORT_FIBER_MODE) val 93 drivers/net/dsa/microchip/ksz9477.c unsigned int val; val 96 drivers/net/dsa/microchip/ksz9477.c val, !(val & VLAN_START), 10, 1000); val 180 drivers/net/dsa/microchip/ksz9477.c unsigned int val; val 183 drivers/net/dsa/microchip/ksz9477.c val, !(val & ALU_START), 10, 1000); val 188 drivers/net/dsa/microchip/ksz9477.c unsigned int val; val 192 drivers/net/dsa/microchip/ksz9477.c val, !(val & ALU_STAT_START), val 236 drivers/net/dsa/microchip/ksz9477.c unsigned int val; val 248 drivers/net/dsa/microchip/ksz9477.c val, !(val & MIB_COUNTER_READ), 10, 1000); val 269 drivers/net/dsa/microchip/ksz9477.c u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; val 274 drivers/net/dsa/microchip/ksz9477.c ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); val 311 drivers/net/dsa/microchip/ksz9477.c u16 val = 0xffff; val 324 drivers/net/dsa/microchip/ksz9477.c val = 0x1140; val 327 drivers/net/dsa/microchip/ksz9477.c val = 0x796d; val 330 drivers/net/dsa/microchip/ksz9477.c val = 0x0022; val 333 drivers/net/dsa/microchip/ksz9477.c val = 0x1631; val 336 drivers/net/dsa/microchip/ksz9477.c val = 0x05e1; val 339 drivers/net/dsa/microchip/ksz9477.c val = 0xc5e1; val 342 drivers/net/dsa/microchip/ksz9477.c val = 0x0700; val 346 drivers/net/dsa/microchip/ksz9477.c val = 0x3800; val 348 drivers/net/dsa/microchip/ksz9477.c val = 0; val 352 drivers/net/dsa/microchip/ksz9477.c ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); val 355 drivers/net/dsa/microchip/ksz9477.c return val; val 359 drivers/net/dsa/microchip/ksz9477.c u16 val) val 370 drivers/net/dsa/microchip/ksz9477.c ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); val 1133 drivers/net/dsa/microchip/ksz9477.c u8 dev_addr, u16 reg_addr, u16 val) val 1140 drivers/net/dsa/microchip/ksz9477.c ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); val 128 drivers/net/dsa/microchip/ksz_common.c u16 val = 0xffff; val 130 drivers/net/dsa/microchip/ksz_common.c dev->dev_ops->r_phy(dev, addr, reg, &val); val 132 drivers/net/dsa/microchip/ksz_common.c return val; val 136 drivers/net/dsa/microchip/ksz_common.c int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) val 140 drivers/net/dsa/microchip/ksz_common.c dev->dev_ops->w_phy(dev, addr, reg, val); val 127 drivers/net/dsa/microchip/ksz_common.h void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); val 128 drivers/net/dsa/microchip/ksz_common.h void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); val 162 drivers/net/dsa/microchip/ksz_common.h int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val); val 187 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) val 192 drivers/net/dsa/microchip/ksz_common.h *val = value; val 196 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) val 201 drivers/net/dsa/microchip/ksz_common.h *val = value; val 205 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) val 210 drivers/net/dsa/microchip/ksz_common.h *val = value; val 214 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) val 224 drivers/net/dsa/microchip/ksz_common.h *val = swab64((u64)*value); val 247 drivers/net/dsa/microchip/ksz_common.h u32 val[2]; val 251 drivers/net/dsa/microchip/ksz_common.h val[0] = swab32(value & 0xffffffffULL); val 252 drivers/net/dsa/microchip/ksz_common.h val[1] = swab32(value >> 32ULL); val 254 drivers/net/dsa/microchip/ksz_common.h return regmap_bulk_write(dev->regmap[2], reg, val, 2); val 132 drivers/net/dsa/mt7530.c core_write(struct mt7530_priv *priv, u32 reg, u32 val) val 138 drivers/net/dsa/mt7530.c core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); val 147 drivers/net/dsa/mt7530.c u32 val; val 151 drivers/net/dsa/mt7530.c val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); val 152 drivers/net/dsa/mt7530.c val &= ~mask; val 153 drivers/net/dsa/mt7530.c val |= set; val 154 drivers/net/dsa/mt7530.c core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); val 160 drivers/net/dsa/mt7530.c core_set(struct mt7530_priv *priv, u32 reg, u32 val) val 162 drivers/net/dsa/mt7530.c core_rmw(priv, reg, 0, val); val 166 drivers/net/dsa/mt7530.c core_clear(struct mt7530_priv *priv, u32 reg, u32 val) val 168 drivers/net/dsa/mt7530.c core_rmw(priv, reg, val, 0); val 172 drivers/net/dsa/mt7530.c mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) val 180 drivers/net/dsa/mt7530.c lo = val & 0xffff; val 181 drivers/net/dsa/mt7530.c hi = val >> 16; val 225 drivers/net/dsa/mt7530.c mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) val 231 drivers/net/dsa/mt7530.c mt7530_mii_write(priv, reg, val); val 240 drivers/net/dsa/mt7530.c u32 val; val 244 drivers/net/dsa/mt7530.c val = mt7530_mii_read(p->priv, p->reg); val 248 drivers/net/dsa/mt7530.c return val; val 265 drivers/net/dsa/mt7530.c u32 val; val 269 drivers/net/dsa/mt7530.c val = mt7530_mii_read(priv, reg); val 270 drivers/net/dsa/mt7530.c val &= ~mask; val 271 drivers/net/dsa/mt7530.c val |= set; val 272 drivers/net/dsa/mt7530.c mt7530_mii_write(priv, reg, val); val 278 drivers/net/dsa/mt7530.c mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) val 280 drivers/net/dsa/mt7530.c mt7530_rmw(priv, reg, 0, val); val 284 drivers/net/dsa/mt7530.c mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) val 286 drivers/net/dsa/mt7530.c mt7530_rmw(priv, reg, val, 0); val 292 drivers/net/dsa/mt7530.c u32 val; val 297 drivers/net/dsa/mt7530.c val = ATC_BUSY | ATC_MAT(0) | cmd; val 298 drivers/net/dsa/mt7530.c mt7530_write(priv, MT7530_ATC, val); val 301 drivers/net/dsa/mt7530.c ret = readx_poll_timeout(_mt7530_read, &p, val, val 302 drivers/net/dsa/mt7530.c !(val & ATC_BUSY), 20, 20000); val 311 drivers/net/dsa/mt7530.c val = mt7530_read(priv, MT7530_ATC); val 312 drivers/net/dsa/mt7530.c if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) val 316 drivers/net/dsa/mt7530.c *rsp = val; val 512 drivers/net/dsa/mt7530.c u16 val) val 516 drivers/net/dsa/mt7530.c return mdiobus_write_nested(priv->bus, port, regnum, val); val 567 drivers/net/dsa/mt7530.c int val; val 571 drivers/net/dsa/mt7530.c val = mt7530_read(priv, MT7530_MHWTRAP); val 573 drivers/net/dsa/mt7530.c val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; val 574 drivers/net/dsa/mt7530.c val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; val 579 drivers/net/dsa/mt7530.c val |= MHWTRAP_PHY0_SEL; val 583 drivers/net/dsa/mt7530.c val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; val 590 drivers/net/dsa/mt7530.c val &= ~MHWTRAP_P5_DIS; val 603 drivers/net/dsa/mt7530.c val |= MHWTRAP_P5_RGMII_MODE; val 623 drivers/net/dsa/mt7530.c mt7530_write(priv, MT7530_MHWTRAP, val); val 626 drivers/net/dsa/mt7530.c val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); val 948 drivers/net/dsa/mt7530.c u32 val; val 951 drivers/net/dsa/mt7530.c val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; val 952 drivers/net/dsa/mt7530.c mt7530_write(priv, MT7530_VTCR, val); val 955 drivers/net/dsa/mt7530.c ret = readx_poll_timeout(_mt7530_read, &p, val, val 956 drivers/net/dsa/mt7530.c !(val & VTCR_BUSY), 20, 20000); val 962 drivers/net/dsa/mt7530.c val = mt7530_read(priv, MT7530_VTCR); val 963 drivers/net/dsa/mt7530.c if (val & VTCR_INVALID) { val 1004 drivers/net/dsa/mt7530.c u32 val; val 1012 drivers/net/dsa/mt7530.c val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; val 1013 drivers/net/dsa/mt7530.c mt7530_write(priv, MT7530_VAWD1, val); val 1018 drivers/net/dsa/mt7530.c val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : val 1022 drivers/net/dsa/mt7530.c ETAG_CTRL_P(entry->port, val)); val 1040 drivers/net/dsa/mt7530.c u32 val; val 1044 drivers/net/dsa/mt7530.c val = mt7530_read(priv, MT7530_VAWD1); val 1045 drivers/net/dsa/mt7530.c if (!(val & VLAN_VALID)) { val 1056 drivers/net/dsa/mt7530.c val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | val 1058 drivers/net/dsa/mt7530.c mt7530_write(priv, MT7530_VAWD1, val); val 1070 drivers/net/dsa/mt7530.c u32 val; val 1075 drivers/net/dsa/mt7530.c val = mt7530_read(priv, MT7530_VAWD1); val 1077 drivers/net/dsa/mt7530.c entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; val 1179 drivers/net/dsa/mt7530.c u32 id, val; val 1221 drivers/net/dsa/mt7530.c ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, val 1241 drivers/net/dsa/mt7530.c val = mt7530_read(priv, MT7530_MHWTRAP); val 1242 drivers/net/dsa/mt7530.c val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; val 1243 drivers/net/dsa/mt7530.c val |= MHWTRAP_MANUAL; val 1244 drivers/net/dsa/mt7530.c mt7530_write(priv, MT7530_MHWTRAP, val); val 22 drivers/net/dsa/mv88e6060.c static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val) val 24 drivers/net/dsa/mv88e6060.c return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val); val 159 drivers/net/dsa/mv88e6060.c u16 val; val 163 drivers/net/dsa/mv88e6060.c val = addr[0] << 8 | addr[1]; val 168 drivers/net/dsa/mv88e6060.c val &= 0xfeff; val 170 drivers/net/dsa/mv88e6060.c ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val); val 234 drivers/net/dsa/mv88e6060.c mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) val 243 drivers/net/dsa/mv88e6060.c return reg_write(priv, addr, regnum, val); val 52 drivers/net/dsa/mv88e6xxx/chip.c int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) val 58 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_smi_read(chip, addr, reg, val); val 63 drivers/net/dsa/mv88e6xxx/chip.c addr, reg, *val); val 68 drivers/net/dsa/mv88e6xxx/chip.c int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) val 74 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_smi_write(chip, addr, reg, val); val 79 drivers/net/dsa/mv88e6xxx/chip.c addr, reg, val); val 85 drivers/net/dsa/mv88e6xxx/chip.c u16 mask, u16 val) val 97 drivers/net/dsa/mv88e6xxx/chip.c if ((data & mask) == val) val 108 drivers/net/dsa/mv88e6xxx/chip.c int bit, int val) val 111 drivers/net/dsa/mv88e6xxx/chip.c val ? BIT(bit) : 0x0000); val 2600 drivers/net/dsa/mv88e6xxx/chip.c u16 val; val 2603 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); val 2609 drivers/net/dsa/mv88e6xxx/chip.c if (val != 0x01c0) val 2767 drivers/net/dsa/mv88e6xxx/chip.c u16 val; val 2774 drivers/net/dsa/mv88e6xxx/chip.c err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); val 2792 drivers/net/dsa/mv88e6xxx/chip.c if (!(val & 0x3f0)) val 2793 drivers/net/dsa/mv88e6xxx/chip.c val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; val 2796 drivers/net/dsa/mv88e6xxx/chip.c return err ? err : val; val 2799 drivers/net/dsa/mv88e6xxx/chip.c static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) val 2809 drivers/net/dsa/mv88e6xxx/chip.c err = chip->info->ops->phy_write(chip, bus, phy, reg, val); val 321 drivers/net/dsa/mv88e6xxx/chip.h int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); val 322 drivers/net/dsa/mv88e6xxx/chip.h int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); val 353 drivers/net/dsa/mv88e6xxx/chip.h int addr, int reg, u16 *val); val 356 drivers/net/dsa/mv88e6xxx/chip.h int addr, int reg, u16 val); val 632 drivers/net/dsa/mv88e6xxx/chip.h int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); val 633 drivers/net/dsa/mv88e6xxx/chip.h int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); val 635 drivers/net/dsa/mv88e6xxx/chip.h u16 mask, u16 val); val 637 drivers/net/dsa/mv88e6xxx/chip.h int bit, int val); val 16 drivers/net/dsa/mv88e6xxx/global1.c int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) val 20 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_read(chip, addr, reg, val); val 23 drivers/net/dsa/mv88e6xxx/global1.c int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) val 27 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_write(chip, addr, reg, val); val 31 drivers/net/dsa/mv88e6xxx/global1.c bit, int val) val 34 drivers/net/dsa/mv88e6xxx/global1.c bit, val); val 38 drivers/net/dsa/mv88e6xxx/global1.c u16 mask, u16 val) val 41 drivers/net/dsa/mv88e6xxx/global1.c mask, val); val 109 drivers/net/dsa/mv88e6xxx/global1.c u16 val; val 115 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); val 119 drivers/net/dsa/mv88e6xxx/global1.c val |= MV88E6XXX_G1_CTL1_SW_RESET; val 120 drivers/net/dsa/mv88e6xxx/global1.c val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; val 122 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); val 135 drivers/net/dsa/mv88e6xxx/global1.c u16 val; val 139 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); val 143 drivers/net/dsa/mv88e6xxx/global1.c val |= MV88E6XXX_G1_CTL1_SW_RESET; val 145 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); val 165 drivers/net/dsa/mv88e6xxx/global1.c u16 val; val 168 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); val 172 drivers/net/dsa/mv88e6xxx/global1.c val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; val 174 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); val 183 drivers/net/dsa/mv88e6xxx/global1.c u16 val; val 186 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); val 190 drivers/net/dsa/mv88e6xxx/global1.c val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; val 192 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); val 378 drivers/net/dsa/mv88e6xxx/global1.c u16 val) val 388 drivers/net/dsa/mv88e6xxx/global1.c reg |= val & mask; val 443 drivers/net/dsa/mv88e6xxx/global1.c u16 val; val 446 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); val 450 drivers/net/dsa/mv88e6xxx/global1.c val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; val 452 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); val 497 drivers/net/dsa/mv88e6xxx/global1.c void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) val 503 drivers/net/dsa/mv88e6xxx/global1.c *val = 0; val 525 drivers/net/dsa/mv88e6xxx/global1.c *val = value | reg; val 531 drivers/net/dsa/mv88e6xxx/global1.c u16 val; val 533 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); val 538 drivers/net/dsa/mv88e6xxx/global1.c val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; val 539 drivers/net/dsa/mv88e6xxx/global1.c val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; val 541 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); val 268 drivers/net/dsa/mv88e6xxx/global1.h int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); val 269 drivers/net/dsa/mv88e6xxx/global1.h int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); val 271 drivers/net/dsa/mv88e6xxx/global1.h bit, int val); val 273 drivers/net/dsa/mv88e6xxx/global1.h u16 mask, u16 val); val 289 drivers/net/dsa/mv88e6xxx/global1.h void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val); val 27 drivers/net/dsa/mv88e6xxx/global1_atu.c u16 val; val 30 drivers/net/dsa/mv88e6xxx/global1_atu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); val 35 drivers/net/dsa/mv88e6xxx/global1_atu.c val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL; val 37 drivers/net/dsa/mv88e6xxx/global1_atu.c val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL; val 39 drivers/net/dsa/mv88e6xxx/global1_atu.c return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); val 49 drivers/net/dsa/mv88e6xxx/global1_atu.c u16 val; val 58 drivers/net/dsa/mv88e6xxx/global1_atu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); val 63 drivers/net/dsa/mv88e6xxx/global1_atu.c val &= ~0xff0; val 64 drivers/net/dsa/mv88e6xxx/global1_atu.c val |= age_time << 4; val 66 drivers/net/dsa/mv88e6xxx/global1_atu.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); val 87 drivers/net/dsa/mv88e6xxx/global1_atu.c u16 val; val 99 drivers/net/dsa/mv88e6xxx/global1_atu.c &val); val 103 drivers/net/dsa/mv88e6xxx/global1_atu.c val = (val & 0x0fff) | ((fid << 8) & 0xf000); val 105 drivers/net/dsa/mv88e6xxx/global1_atu.c val); val 130 drivers/net/dsa/mv88e6xxx/global1_atu.c u16 val; val 133 drivers/net/dsa/mv88e6xxx/global1_atu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val); val 137 drivers/net/dsa/mv88e6xxx/global1_atu.c entry->state = val & 0xf; val 139 drivers/net/dsa/mv88e6xxx/global1_atu.c entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK); val 140 drivers/net/dsa/mv88e6xxx/global1_atu.c entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip); val 169 drivers/net/dsa/mv88e6xxx/global1_atu.c u16 val; val 173 drivers/net/dsa/mv88e6xxx/global1_atu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val); val 177 drivers/net/dsa/mv88e6xxx/global1_atu.c entry->mac[i * 2] = val >> 8; val 178 drivers/net/dsa/mv88e6xxx/global1_atu.c entry->mac[i * 2 + 1] = val & 0xff; val 187 drivers/net/dsa/mv88e6xxx/global1_atu.c u16 val; val 191 drivers/net/dsa/mv88e6xxx/global1_atu.c val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1]; val 192 drivers/net/dsa/mv88e6xxx/global1_atu.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val); val 321 drivers/net/dsa/mv88e6xxx/global1_atu.c u16 val; val 330 drivers/net/dsa/mv88e6xxx/global1_atu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val); val 344 drivers/net/dsa/mv88e6xxx/global1_atu.c if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) { val 350 drivers/net/dsa/mv88e6xxx/global1_atu.c if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) { val 357 drivers/net/dsa/mv88e6xxx/global1_atu.c if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) { val 364 drivers/net/dsa/mv88e6xxx/global1_atu.c if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) { val 22 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val; val 25 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_read(chip, MV88E6352_G1_VTU_FID, &val); val 29 drivers/net/dsa/mv88e6xxx/global1_vtu.c entry->fid = val & MV88E6352_G1_VTU_FID_MASK; val 37 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val = entry->fid & MV88E6352_G1_VTU_FID_MASK; val 39 drivers/net/dsa/mv88e6xxx/global1_vtu.c return mv88e6xxx_g1_write(chip, MV88E6352_G1_VTU_FID, val); val 47 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val; val 50 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_read(chip, MV88E6352_G1_VTU_SID, &val); val 54 drivers/net/dsa/mv88e6xxx/global1_vtu.c entry->sid = val & MV88E6352_G1_VTU_SID_MASK; val 62 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val = entry->sid & MV88E6352_G1_VTU_SID_MASK; val 64 drivers/net/dsa/mv88e6xxx/global1_vtu.c return mv88e6xxx_g1_write(chip, MV88E6352_G1_VTU_SID, val); val 93 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val; val 96 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_VID, &val); val 100 drivers/net/dsa/mv88e6xxx/global1_vtu.c entry->vid = val & 0xfff; val 102 drivers/net/dsa/mv88e6xxx/global1_vtu.c if (val & MV88E6390_G1_VTU_VID_PAGE) val 105 drivers/net/dsa/mv88e6xxx/global1_vtu.c entry->valid = !!(val & MV88E6XXX_G1_VTU_VID_VALID); val 113 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val = entry->vid & 0xfff; val 116 drivers/net/dsa/mv88e6xxx/global1_vtu.c val |= MV88E6390_G1_VTU_VID_PAGE; val 119 drivers/net/dsa/mv88e6xxx/global1_vtu.c val |= MV88E6XXX_G1_VTU_VID_VALID; val 121 drivers/net/dsa/mv88e6xxx/global1_vtu.c return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_VID, val); val 311 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val; val 326 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_OP, &val); val 330 drivers/net/dsa/mv88e6xxx/global1_vtu.c entry->fid = val & 0x000f; val 331 drivers/net/dsa/mv88e6xxx/global1_vtu.c entry->fid |= (val & 0x0300) >> 4; val 340 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val; val 355 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_OP, &val); val 359 drivers/net/dsa/mv88e6xxx/global1_vtu.c entry->fid = val & 0x000f; val 360 drivers/net/dsa/mv88e6xxx/global1_vtu.c entry->fid |= (val & 0x0f00) >> 4; val 582 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 val; val 590 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_OP, &val); val 598 drivers/net/dsa/mv88e6xxx/global1_vtu.c spid = val & MV88E6XXX_G1_VTU_OP_SPID_MASK; val 600 drivers/net/dsa/mv88e6xxx/global1_vtu.c if (val & MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION) { val 606 drivers/net/dsa/mv88e6xxx/global1_vtu.c if (val & MV88E6XXX_G1_VTU_OP_MISS_VIOLATION) { val 19 drivers/net/dsa/mv88e6xxx/global2.c int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) val 21 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); val 24 drivers/net/dsa/mv88e6xxx/global2.c int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) val 26 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); val 30 drivers/net/dsa/mv88e6xxx/global2.c bit, int val) val 33 drivers/net/dsa/mv88e6xxx/global2.c bit, val); val 70 drivers/net/dsa/mv88e6xxx/global2.c u16 val; val 73 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val); val 78 drivers/net/dsa/mv88e6xxx/global2.c val |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU; val 80 drivers/net/dsa/mv88e6xxx/global2.c val &= ~MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU; val 82 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val); val 118 drivers/net/dsa/mv88e6xxx/global2.c u16 val = (target << 8) | (port & 0x1f); val 124 drivers/net/dsa/mv88e6xxx/global2.c MV88E6XXX_G2_DEVICE_MAPPING_UPDATE | val); val 132 drivers/net/dsa/mv88e6xxx/global2.c u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip)); val 135 drivers/net/dsa/mv88e6xxx/global2.c val |= MV88E6XXX_G2_TRUNK_MASK_HASH; val 138 drivers/net/dsa/mv88e6xxx/global2.c MV88E6XXX_G2_TRUNK_MASK_UPDATE | val); val 147 drivers/net/dsa/mv88e6xxx/global2.c u16 val = (id << 11) | (map & port_mask); val 150 drivers/net/dsa/mv88e6xxx/global2.c MV88E6XXX_G2_TRUNK_MAPPING_UPDATE | val); val 264 drivers/net/dsa/mv88e6xxx/global2.c u16 val = (pointer << 8) | data; val 267 drivers/net/dsa/mv88e6xxx/global2.c MV88E6XXX_G2_SWITCH_MAC_UPDATE | val); val 288 drivers/net/dsa/mv88e6xxx/global2.c u16 val = (pointer << 8) | (data & 0x7); val 291 drivers/net/dsa/mv88e6xxx/global2.c MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE | val); val 469 drivers/net/dsa/mv88e6xxx/global2.c u16 val; val 475 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); val 479 drivers/net/dsa/mv88e6xxx/global2.c *data++ = (val >> 8) & 0xff; val 487 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); val 491 drivers/net/dsa/mv88e6xxx/global2.c *data++ = val & 0xff; val 492 drivers/net/dsa/mv88e6xxx/global2.c *data++ = (val >> 8) & 0xff; val 500 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); val 504 drivers/net/dsa/mv88e6xxx/global2.c *data++ = val & 0xff; val 519 drivers/net/dsa/mv88e6xxx/global2.c u16 val; val 523 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val); val 527 drivers/net/dsa/mv88e6xxx/global2.c if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN)) val 533 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); val 537 drivers/net/dsa/mv88e6xxx/global2.c val = (*data++ << 8) | (val & 0xff); val 539 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); val 549 drivers/net/dsa/mv88e6xxx/global2.c val = *data++; val 550 drivers/net/dsa/mv88e6xxx/global2.c val |= *data++ << 8; val 552 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); val 562 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); val 566 drivers/net/dsa/mv88e6xxx/global2.c val = (val & 0xff00) | *data++; val 568 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); val 762 drivers/net/dsa/mv88e6xxx/global2.c int addr, int reg, u16 *val) val 769 drivers/net/dsa/mv88e6xxx/global2.c val); val 772 drivers/net/dsa/mv88e6xxx/global2.c val); val 776 drivers/net/dsa/mv88e6xxx/global2.c int addr, int reg, u16 val) val 783 drivers/net/dsa/mv88e6xxx/global2.c val); val 786 drivers/net/dsa/mv88e6xxx/global2.c val); val 958 drivers/net/dsa/mv88e6xxx/global2.c u16 val; val 961 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val); val 966 drivers/net/dsa/mv88e6xxx/global2.c val |= MV88E6XXX_G2_MISC_5_BIT_PORT; val 968 drivers/net/dsa/mv88e6xxx/global2.c val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT; val 970 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val); val 296 drivers/net/dsa/mv88e6xxx/global2.h int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); val 297 drivers/net/dsa/mv88e6xxx/global2.h int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); val 299 drivers/net/dsa/mv88e6xxx/global2.h int bit, int val); val 306 drivers/net/dsa/mv88e6xxx/global2.h int addr, int reg, u16 *val); val 309 drivers/net/dsa/mv88e6xxx/global2.h int addr, int reg, u16 val); val 369 drivers/net/dsa/mv88e6xxx/global2.h static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) val 374 drivers/net/dsa/mv88e6xxx/global2.h static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) val 380 drivers/net/dsa/mv88e6xxx/global2.h int reg, int bit, int val) val 399 drivers/net/dsa/mv88e6xxx/global2.h int addr, int reg, u16 *val) val 406 drivers/net/dsa/mv88e6xxx/global2.h int addr, int reg, u16 val) val 56 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 val; val 59 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, reg, &val); val 63 drivers/net/dsa/mv88e6xxx/global2_scratch.c *set = !!(mask & val); val 82 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 val; val 85 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, reg, &val); val 90 drivers/net/dsa/mv88e6xxx/global2_scratch.c val |= mask; val 92 drivers/net/dsa/mv88e6xxx/global2_scratch.c val &= ~mask; val 94 drivers/net/dsa/mv88e6xxx/global2_scratch.c return mv88e6xxx_g2_scratch_write(chip, reg, val); val 107 drivers/net/dsa/mv88e6xxx/global2_scratch.c int val = 0; val 112 drivers/net/dsa/mv88e6xxx/global2_scratch.c pin, &val); val 116 drivers/net/dsa/mv88e6xxx/global2_scratch.c return val; val 152 drivers/net/dsa/mv88e6xxx/global2_scratch.c int val = 0; val 157 drivers/net/dsa/mv88e6xxx/global2_scratch.c pin, &val); val 161 drivers/net/dsa/mv88e6xxx/global2_scratch.c return val; val 195 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 val; val 197 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, reg, &val); val 201 drivers/net/dsa/mv88e6xxx/global2_scratch.c *func = (val & mask) >> offset; val 219 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 val; val 221 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, reg, &val); val 225 drivers/net/dsa/mv88e6xxx/global2_scratch.c val = (val & ~mask) | ((func & mask) << offset); val 227 drivers/net/dsa/mv88e6xxx/global2_scratch.c return mv88e6xxx_g2_scratch_write(chip, reg, val); val 257 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 val; val 259 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, config_data2, &val); val 263 drivers/net/dsa/mv88e6xxx/global2_scratch.c p0_mode = val & MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK; val 268 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, config_data1, &val); val 272 drivers/net/dsa/mv88e6xxx/global2_scratch.c no_cpu = !!(val & MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU); val 274 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, misc_cfg, &val); val 283 drivers/net/dsa/mv88e6xxx/global2_scratch.c val |= MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI; val 285 drivers/net/dsa/mv88e6xxx/global2_scratch.c val &= ~MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI; val 287 drivers/net/dsa/mv88e6xxx/global2_scratch.c return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val); val 532 drivers/net/dsa/mv88e6xxx/hwtstamp.c u16 val; val 535 drivers/net/dsa/mv88e6xxx/hwtstamp.c err = mv88e6xxx_ptp_read(chip, MV88E6165_PTP_CFG, &val); val 538 drivers/net/dsa/mv88e6xxx/hwtstamp.c val |= MV88E6165_PTP_CFG_DISABLE_PTP; val 540 drivers/net/dsa/mv88e6xxx/hwtstamp.c return mv88e6xxx_ptp_write(chip, MV88E6165_PTP_CFG, val); val 545 drivers/net/dsa/mv88e6xxx/hwtstamp.c u16 val; val 548 drivers/net/dsa/mv88e6xxx/hwtstamp.c err = mv88e6xxx_ptp_read(chip, MV88E6165_PTP_CFG, &val); val 552 drivers/net/dsa/mv88e6xxx/hwtstamp.c val &= ~(MV88E6165_PTP_CFG_DISABLE_PTP | MV88E6165_PTP_CFG_TSPEC_MASK); val 554 drivers/net/dsa/mv88e6xxx/hwtstamp.c return mv88e6xxx_ptp_write(chip, MV88E6165_PTP_CFG, val); val 631 drivers/net/dsa/mv88e6xxx/hwtstamp.c u16 val = MV88E6341_PTP_CFG_UPDATE | val 634 drivers/net/dsa/mv88e6xxx/hwtstamp.c err = mv88e6xxx_ptp_write(chip, MV88E6341_PTP_CFG, val); val 17 drivers/net/dsa/mv88e6xxx/phy.c int addr, int reg, u16 *val) val 19 drivers/net/dsa/mv88e6xxx/phy.c return mv88e6xxx_read(chip, addr, reg, val); val 23 drivers/net/dsa/mv88e6xxx/phy.c int addr, int reg, u16 val) val 25 drivers/net/dsa/mv88e6xxx/phy.c return mv88e6xxx_write(chip, addr, reg, val); val 28 drivers/net/dsa/mv88e6xxx/phy.c int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, int reg, u16 *val) val 40 drivers/net/dsa/mv88e6xxx/phy.c return chip->info->ops->phy_read(chip, bus, addr, reg, val); val 43 drivers/net/dsa/mv88e6xxx/phy.c int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, int reg, u16 val) val 55 drivers/net/dsa/mv88e6xxx/phy.c return chip->info->ops->phy_write(chip, bus, addr, reg, val); val 80 drivers/net/dsa/mv88e6xxx/phy.c u8 page, int reg, u16 *val) val 90 drivers/net/dsa/mv88e6xxx/phy.c err = mv88e6xxx_phy_read(chip, phy, reg, val); val 98 drivers/net/dsa/mv88e6xxx/phy.c u8 page, int reg, u16 val) val 110 drivers/net/dsa/mv88e6xxx/phy.c err = mv88e6xxx_phy_write(chip, phy, reg, val); val 204 drivers/net/dsa/mv88e6xxx/phy.c int addr, int reg, u16 *val) val 210 drivers/net/dsa/mv88e6xxx/phy.c err = mv88e6xxx_read(chip, addr, reg, val); val 218 drivers/net/dsa/mv88e6xxx/phy.c int addr, int reg, u16 val) val 224 drivers/net/dsa/mv88e6xxx/phy.c err = mv88e6xxx_write(chip, addr, reg, val); val 18 drivers/net/dsa/mv88e6xxx/phy.h int addr, int reg, u16 *val); val 20 drivers/net/dsa/mv88e6xxx/phy.h int addr, int reg, u16 val); val 22 drivers/net/dsa/mv88e6xxx/phy.h int addr, int reg, u16 *val); val 24 drivers/net/dsa/mv88e6xxx/phy.h int addr, int reg, u16 val); val 28 drivers/net/dsa/mv88e6xxx/phy.h int reg, u16 *val); val 30 drivers/net/dsa/mv88e6xxx/phy.h int reg, u16 val); val 32 drivers/net/dsa/mv88e6xxx/phy.h u8 page, int reg, u16 *val); val 34 drivers/net/dsa/mv88e6xxx/phy.h u8 page, int reg, u16 val); val 21 drivers/net/dsa/mv88e6xxx/port.c u16 *val) val 25 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_read(chip, addr, reg, val); val 29 drivers/net/dsa/mv88e6xxx/port.c u16 val) val 33 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_write(chip, addr, reg, val); val 982 drivers/net/dsa/mv88e6xxx/port.c u16 val; val 985 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); val 990 drivers/net/dsa/mv88e6xxx/port.c val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; val 992 drivers/net/dsa/mv88e6xxx/port.c val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; val 994 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); val 1351 drivers/net/dsa/mv88e6xxx/port.c u16 reg, mask, val; val 1394 drivers/net/dsa/mv88e6xxx/port.c val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; val 1397 drivers/net/dsa/mv88e6xxx/port.c val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; val 1400 drivers/net/dsa/mv88e6xxx/port.c val = MV88E6XXX_PORT_POLICY_CTL_TRAP; val 1403 drivers/net/dsa/mv88e6xxx/port.c val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; val 1414 drivers/net/dsa/mv88e6xxx/port.c reg |= (val << shift) & mask; val 288 drivers/net/dsa/mv88e6xxx/port.h u16 *val); val 290 drivers/net/dsa/mv88e6xxx/port.h u16 val); val 376 drivers/net/dsa/mv88e6xxx/port.h int port, int reg, u16 val); val 379 drivers/net/dsa/mv88e6xxx/port.h int reg, u16 *val); val 19 drivers/net/dsa/mv88e6xxx/port_hidden.c int port, int reg, u16 val) val 25 drivers/net/dsa/mv88e6xxx/port_hidden.c MV88E6XXX_PORT_RESERVED_1A, val); val 48 drivers/net/dsa/mv88e6xxx/port_hidden.c int reg, u16 *val) val 69 drivers/net/dsa/mv88e6xxx/port_hidden.c MV88E6XXX_PORT_RESERVED_1A, val); val 21 drivers/net/dsa/mv88e6xxx/serdes.c u16 *val) val 25 drivers/net/dsa/mv88e6xxx/serdes.c reg, val); val 29 drivers/net/dsa/mv88e6xxx/serdes.c u16 val) val 33 drivers/net/dsa/mv88e6xxx/serdes.c reg, val); val 37 drivers/net/dsa/mv88e6xxx/serdes.c int lane, int device, int reg, u16 *val) val 41 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6xxx_phy_read(chip, lane, reg_c45, val); val 45 drivers/net/dsa/mv88e6xxx/serdes.c int lane, int device, int reg, u16 val) val 49 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6xxx_phy_write(chip, lane, reg_c45, val); val 55 drivers/net/dsa/mv88e6xxx/serdes.c u16 val, new_val; val 58 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6352_serdes_read(chip, MII_BMCR, &val); val 63 drivers/net/dsa/mv88e6xxx/serdes.c new_val = val & ~BMCR_PDOWN; val 65 drivers/net/dsa/mv88e6xxx/serdes.c new_val = val | BMCR_PDOWN; val 67 drivers/net/dsa/mv88e6xxx/serdes.c if (val != new_val) val 133 drivers/net/dsa/mv88e6xxx/serdes.c u64 val = 0; val 143 drivers/net/dsa/mv88e6xxx/serdes.c val = reg; val 151 drivers/net/dsa/mv88e6xxx/serdes.c val = val << 16 | reg; val 154 drivers/net/dsa/mv88e6xxx/serdes.c return val; val 227 drivers/net/dsa/mv88e6xxx/serdes.c u16 val = 0; val 230 drivers/net/dsa/mv88e6xxx/serdes.c val |= MV88E6352_SERDES_INT_LINK_CHANGE; val 232 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6352_serdes_write(chip, MV88E6352_SERDES_INT_ENABLE, val); val 359 drivers/net/dsa/mv88e6xxx/serdes.c u16 val, new_val; val 363 drivers/net/dsa/mv88e6xxx/serdes.c MV88E6390_PCS_CONTROL_1, &val); val 369 drivers/net/dsa/mv88e6xxx/serdes.c new_val = val & ~(MV88E6390_PCS_CONTROL_1_RESET | val 373 drivers/net/dsa/mv88e6xxx/serdes.c new_val = val | MV88E6390_PCS_CONTROL_1_PDOWN; val 375 drivers/net/dsa/mv88e6xxx/serdes.c if (val != new_val) val 386 drivers/net/dsa/mv88e6xxx/serdes.c u16 val, new_val; val 390 drivers/net/dsa/mv88e6xxx/serdes.c MV88E6390_SGMII_CONTROL, &val); val 395 drivers/net/dsa/mv88e6xxx/serdes.c new_val = val & ~(MV88E6390_SGMII_CONTROL_RESET | val 399 drivers/net/dsa/mv88e6xxx/serdes.c new_val = val | MV88E6390_SGMII_CONTROL_PDOWN; val 401 drivers/net/dsa/mv88e6xxx/serdes.c if (val != new_val) val 496 drivers/net/dsa/mv88e6xxx/serdes.c u16 val = 0; val 499 drivers/net/dsa/mv88e6xxx/serdes.c val |= MV88E6390_SGMII_INT_LINK_DOWN | val 503 drivers/net/dsa/mv88e6xxx/serdes.c MV88E6390_SGMII_INT_ENABLE, val); val 56 drivers/net/dsa/mv88e6xxx/smi.c int dev, int reg, int bit, int val) val 67 drivers/net/dsa/mv88e6xxx/smi.c if (!!(data & BIT(bit)) == !!val) val 93 drivers/net/dsa/qca8k.c u32 val; val 98 drivers/net/dsa/qca8k.c val = ret; val 100 drivers/net/dsa/qca8k.c val |= ret << 16; val 109 drivers/net/dsa/qca8k.c return val; val 113 drivers/net/dsa/qca8k.c qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) val 118 drivers/net/dsa/qca8k.c lo = val & 0xffff; val 119 drivers/net/dsa/qca8k.c hi = (u16)(val >> 16); val 145 drivers/net/dsa/qca8k.c u32 val; val 152 drivers/net/dsa/qca8k.c val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); val 156 drivers/net/dsa/qca8k.c return val; val 160 drivers/net/dsa/qca8k.c qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) val 169 drivers/net/dsa/qca8k.c qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); val 175 drivers/net/dsa/qca8k.c qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) val 187 drivers/net/dsa/qca8k.c ret |= val; val 196 drivers/net/dsa/qca8k.c qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val) val 198 drivers/net/dsa/qca8k.c qca8k_rmw(priv, reg, 0, val); val 202 drivers/net/dsa/qca8k.c qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val) val 204 drivers/net/dsa/qca8k.c qca8k_rmw(priv, reg, val, 0); val 208 drivers/net/dsa/qca8k.c qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) val 212 drivers/net/dsa/qca8k.c *val = qca8k_read(priv, reg); val 218 drivers/net/dsa/qca8k.c qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val) val 222 drivers/net/dsa/qca8k.c qca8k_write(priv, reg, val); val 270 drivers/net/dsa/qca8k.c u32 val = qca8k_read(priv, reg); val 271 drivers/net/dsa/qca8k.c int busy = val & mask; val 424 drivers/net/dsa/qca8k.c u32 reg, val; val 444 drivers/net/dsa/qca8k.c val = QCA8K_PORT_PAD_RGMII_EN; val 445 drivers/net/dsa/qca8k.c qca8k_write(priv, reg, val); val 503 drivers/net/dsa/qca8k.c u32 phy, val; val 512 drivers/net/dsa/qca8k.c val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | val 517 drivers/net/dsa/qca8k.c qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); val 526 drivers/net/dsa/qca8k.c u32 phy, val; val 535 drivers/net/dsa/qca8k.c val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | val 539 drivers/net/dsa/qca8k.c qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); val 545 drivers/net/dsa/qca8k.c val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & val 548 drivers/net/dsa/qca8k.c return val; val 304 drivers/net/dsa/realtek-smi-core.c static int realtek_smi_write(void *ctx, u32 reg, u32 val) val 308 drivers/net/dsa/realtek-smi-core.c return realtek_smi_write_reg(smi, reg, val, true); val 311 drivers/net/dsa/realtek-smi-core.c static int realtek_smi_read(void *ctx, u32 reg, u32 *val) val 315 drivers/net/dsa/realtek-smi-core.c return realtek_smi_read_reg(smi, reg, val); val 338 drivers/net/dsa/realtek-smi-core.c u16 val) val 342 drivers/net/dsa/realtek-smi-core.c return smi->ops->phy_write(smi, addr, regnum, val); val 94 drivers/net/dsa/realtek-smi-core.h int (*get_mc_index)(struct realtek_smi *smi, int port, int *val); val 102 drivers/net/dsa/realtek-smi-core.h u16 val); val 122 drivers/net/dsa/realtek-smi-core.h int rtl8366_get_pvid(struct realtek_smi *smi, int port, int *val); val 81 drivers/net/dsa/rtl8366.c int rtl8366_get_pvid(struct realtek_smi *smi, int port, int *val) val 95 drivers/net/dsa/rtl8366.c *val = vlanmc.vid; val 355 drivers/net/dsa/rtl8366rb.c u32 addr, val; val 371 drivers/net/dsa/rtl8366rb.c ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val); val 375 drivers/net/dsa/rtl8366rb.c if (val & RTL8366RB_MIB_CTRL_BUSY_MASK) val 378 drivers/net/dsa/rtl8366rb.c if (val & RTL8366RB_MIB_CTRL_RESET_MASK) val 384 drivers/net/dsa/rtl8366rb.c ret = regmap_read(smi->map, addr + (i - 1), &val); val 387 drivers/net/dsa/rtl8366rb.c *mibvalue = (*mibvalue << 16) | (val & 0xFFFF); val 395 drivers/net/dsa/rtl8366rb.c u32 val; val 401 drivers/net/dsa/rtl8366rb.c val = BIT(line) | BIT(line + 6); val 403 drivers/net/dsa/rtl8366rb.c val = BIT(line); val 404 drivers/net/dsa/rtl8366rb.c return val; val 498 drivers/net/dsa/rtl8366rb.c u32 val; val 516 drivers/net/dsa/rtl8366rb.c &val); val 528 drivers/net/dsa/rtl8366rb.c val = 0; val 533 drivers/net/dsa/rtl8366rb.c val = RTL8366RB_INTERRUPT_POLARITY; val 538 drivers/net/dsa/rtl8366rb.c val); val 571 drivers/net/dsa/rtl8366rb.c u16 val; val 578 drivers/net/dsa/rtl8366rb.c val = addr[0] << 8 | addr[1]; val 579 drivers/net/dsa/rtl8366rb.c ret = regmap_write(smi->map, RTL8366RB_SMAR0, val); val 582 drivers/net/dsa/rtl8366rb.c val = addr[2] << 8 | addr[3]; val 583 drivers/net/dsa/rtl8366rb.c ret = regmap_write(smi->map, RTL8366RB_SMAR1, val); val 586 drivers/net/dsa/rtl8366rb.c val = addr[4] << 8 | addr[5]; val 587 drivers/net/dsa/rtl8366rb.c ret = regmap_write(smi->map, RTL8366RB_SMAR2, val); val 718 drivers/net/dsa/rtl8366rb.c u32 val; val 785 drivers/net/dsa/rtl8366rb.c &val); val 788 drivers/net/dsa/rtl8366rb.c if (!(val & RTL8366RB_PHY_INT_BUSY)) { val 811 drivers/net/dsa/rtl8366rb.c &val); val 814 drivers/net/dsa/rtl8366rb.c if (!(val & RTL8366RB_PHY_INT_BUSY)) { val 935 drivers/net/dsa/rtl8366rb.c val = RTL8366RB_LED_OFF; val 938 drivers/net/dsa/rtl8366rb.c val = RTL8366RB_LED_FORCE; val 944 drivers/net/dsa/rtl8366rb.c val << (i * 4)); val 1019 drivers/net/dsa/rtl8366rb.c u16 val = enable ? 0x3f : 0; val 1029 drivers/net/dsa/rtl8366rb.c 0x3F, val); val 1035 drivers/net/dsa/rtl8366rb.c val << RTL8366RB_LED_1_OFFSET); val 1040 drivers/net/dsa/rtl8366rb.c 0x3F, val); val 1046 drivers/net/dsa/rtl8366rb.c val << RTL8366RB_LED_3_OFFSET); val 1234 drivers/net/dsa/rtl8366rb.c static int rtl8366rb_get_mc_index(struct realtek_smi *smi, int port, int *val) val 1247 drivers/net/dsa/rtl8366rb.c *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) & val 1296 drivers/net/dsa/rtl8366rb.c u32 val; val 1318 drivers/net/dsa/rtl8366rb.c ret = regmap_read(smi->map, RTL8366RB_PHY_ACCESS_DATA_REG, &val); val 1323 drivers/net/dsa/rtl8366rb.c phy, regnum, reg, val); val 1325 drivers/net/dsa/rtl8366rb.c return val; val 1329 drivers/net/dsa/rtl8366rb.c u16 val) val 1345 drivers/net/dsa/rtl8366rb.c phy, regnum, reg, val); val 1347 drivers/net/dsa/rtl8366rb.c ret = regmap_write(smi->map, reg, val); val 1357 drivers/net/dsa/rtl8366rb.c u32 val; val 1364 drivers/net/dsa/rtl8366rb.c ret = regmap_read(smi->map, RTL8366RB_RESET_CTRL_REG, &val); val 1368 drivers/net/dsa/rtl8366rb.c if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW)) val 1384 drivers/net/dsa/rtl8366rb.c u32 val; val 1387 drivers/net/dsa/rtl8366rb.c ret = regmap_read(smi->map, 0x5c, &val); val 1393 drivers/net/dsa/rtl8366rb.c switch (val) { val 1408 drivers/net/dsa/rtl8366rb.c val); val 17 drivers/net/dsa/sja1105/sja1105_static_config.c void sja1105_pack(void *buf, const u64 *val, int start, int end, size_t len) val 19 drivers/net/dsa/sja1105/sja1105_static_config.c int rc = packing(buf, (u64 *)val, start, end, len, val 34 drivers/net/dsa/sja1105/sja1105_static_config.c *val, start, end); val 39 drivers/net/dsa/sja1105/sja1105_static_config.c void sja1105_unpack(const void *buf, u64 *val, int start, int end, size_t len) val 41 drivers/net/dsa/sja1105/sja1105_static_config.c int rc = packing((void *)buf, val, start, end, len, val 56 drivers/net/dsa/sja1105/sja1105_static_config.c void sja1105_packing(void *buf, u64 *val, int start, int end, val 59 drivers/net/dsa/sja1105/sja1105_static_config.c int rc = packing(buf, val, start, end, len, op, QUIRK_LSW32_IS_FIRST); val 73 drivers/net/dsa/sja1105/sja1105_static_config.c *val, start, end); val 331 drivers/net/dsa/sja1105/sja1105_static_config.h void sja1105_pack(void *buf, const u64 *val, int start, int end, size_t len); val 332 drivers/net/dsa/sja1105/sja1105_static_config.h void sja1105_unpack(const void *buf, u64 *val, int start, int end, size_t len); val 333 drivers/net/dsa/sja1105/sja1105_static_config.h void sja1105_packing(void *buf, u64 *val, int start, int end, val 377 drivers/net/dsa/vitesse-vsc73xx-core.c u32 *val) val 379 drivers/net/dsa/vitesse-vsc73xx-core.c return vsc->ops->read(vsc, block, subblock, reg, val); val 383 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val) val 385 drivers/net/dsa/vitesse-vsc73xx-core.c return vsc->ops->write(vsc, block, subblock, reg, val); val 389 drivers/net/dsa/vitesse-vsc73xx-core.c u8 reg, u32 mask, u32 val) val 399 drivers/net/dsa/vitesse-vsc73xx-core.c tmp |= val & mask; val 407 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val; val 413 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_ICPU_MBOX_VAL, &val); val 419 drivers/net/dsa/vitesse-vsc73xx-core.c if (val == 0xffffffff) { val 425 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_CHIPID, &val); val 431 drivers/net/dsa/vitesse-vsc73xx-core.c id = (val >> VSC73XX_CHIPID_ID_SHIFT) & val 445 drivers/net/dsa/vitesse-vsc73xx-core.c rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & val 450 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_ICPU_CTRL, &val); val 462 drivers/net/dsa/vitesse-vsc73xx-core.c icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); val 463 drivers/net/dsa/vitesse-vsc73xx-core.c icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); val 491 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val; val 500 drivers/net/dsa/vitesse-vsc73xx-core.c ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); val 503 drivers/net/dsa/vitesse-vsc73xx-core.c if (val & BIT(16)) { val 508 drivers/net/dsa/vitesse-vsc73xx-core.c val &= 0xFFFFU; val 511 drivers/net/dsa/vitesse-vsc73xx-core.c regnum, phy, val); val 513 drivers/net/dsa/vitesse-vsc73xx-core.c return val; val 517 drivers/net/dsa/vitesse-vsc73xx-core.c u16 val) val 529 drivers/net/dsa/vitesse-vsc73xx-core.c if (regnum == 0 && (val & BIT(15))) { val 540 drivers/net/dsa/vitesse-vsc73xx-core.c val, regnum, phy); val 642 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val; val 655 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_MAC_CFG_1000M_F_RGMII; val 657 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_MAC_CFG_1000M_F_PHY; val 662 drivers/net/dsa/vitesse-vsc73xx-core.c val | val 692 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; val 694 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; val 695 drivers/net/dsa/vitesse-vsc73xx-core.c val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; val 699 drivers/net/dsa/vitesse-vsc73xx-core.c val); val 702 drivers/net/dsa/vitesse-vsc73xx-core.c val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); val 706 drivers/net/dsa/vitesse-vsc73xx-core.c val); val 707 drivers/net/dsa/vitesse-vsc73xx-core.c val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); val 711 drivers/net/dsa/vitesse-vsc73xx-core.c val); val 730 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val = initval; val 734 drivers/net/dsa/vitesse-vsc73xx-core.c val |= VSC73XX_MAC_CFG_RESET; val 735 drivers/net/dsa/vitesse-vsc73xx-core.c vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); val 739 drivers/net/dsa/vitesse-vsc73xx-core.c val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; val 740 drivers/net/dsa/vitesse-vsc73xx-core.c val |= VSC73XX_MAC_CFG_SEED_LOAD; val 741 drivers/net/dsa/vitesse-vsc73xx-core.c val |= VSC73XX_MAC_CFG_WEXC_DIS; val 742 drivers/net/dsa/vitesse-vsc73xx-core.c vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); val 770 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val; val 808 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_ARBEMPTY, &val); val 809 drivers/net/dsa/vitesse-vsc73xx-core.c while (!(val & BIT(port))) { val 812 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_ARBEMPTY, &val); val 847 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_MAC_CFG_1000M_F_RGMII; val 849 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_MAC_CFG_1000M_F_PHY; val 850 drivers/net/dsa/vitesse-vsc73xx-core.c vsc73xx_adjust_enable_port(vsc, port, phydev, val); val 853 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_MAC_CFG_100_10M_F_PHY; val 858 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_MAC_CFG_100_10M_H_PHY; val 863 drivers/net/dsa/vitesse-vsc73xx-core.c vsc73xx_adjust_enable_port(vsc, port, phydev, val); val 866 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_MAC_CFG_100_10M_F_PHY; val 871 drivers/net/dsa/vitesse-vsc73xx-core.c val = VSC73XX_MAC_CFG_100_10M_H_PHY; val 876 drivers/net/dsa/vitesse-vsc73xx-core.c vsc73xx_adjust_enable_port(vsc, port, phydev, val); val 942 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val; val 949 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_C_CFG, &val); val 953 drivers/net/dsa/vitesse-vsc73xx-core.c indices[0] = (val & 0x1f); /* RX counter 0 */ val 954 drivers/net/dsa/vitesse-vsc73xx-core.c indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ val 955 drivers/net/dsa/vitesse-vsc73xx-core.c indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ val 956 drivers/net/dsa/vitesse-vsc73xx-core.c indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ val 957 drivers/net/dsa/vitesse-vsc73xx-core.c indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ val 958 drivers/net/dsa/vitesse-vsc73xx-core.c indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ val 1017 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val; val 1023 drivers/net/dsa/vitesse-vsc73xx-core.c regs[i], &val); val 1028 drivers/net/dsa/vitesse-vsc73xx-core.c data[i] = val; val 1048 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val; val 1052 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_GPIO, &val); val 1056 drivers/net/dsa/vitesse-vsc73xx-core.c return !!(val & BIT(offset)); val 1060 drivers/net/dsa/vitesse-vsc73xx-core.c int val) val 1063 drivers/net/dsa/vitesse-vsc73xx-core.c u32 tmp = val ? BIT(offset) : 0; val 1070 drivers/net/dsa/vitesse-vsc73xx-core.c unsigned int offset, int val) val 1073 drivers/net/dsa/vitesse-vsc73xx-core.c u32 tmp = val ? BIT(offset) : 0; val 1094 drivers/net/dsa/vitesse-vsc73xx-core.c u32 val; val 1098 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_GPIO, &val); val 1102 drivers/net/dsa/vitesse-vsc73xx-core.c return !(val & BIT(offset + 4)); val 56 drivers/net/dsa/vitesse-vsc73xx-platform.c u8 reg, u32 *val) val 68 drivers/net/dsa/vitesse-vsc73xx-platform.c *val = ioread32be(vsc_platform->base_addr + offset); val 74 drivers/net/dsa/vitesse-vsc73xx-platform.c u8 reg, u32 val) val 83 drivers/net/dsa/vitesse-vsc73xx-platform.c iowrite32be(val, vsc_platform->base_addr + offset); val 53 drivers/net/dsa/vitesse-vsc73xx-spi.c u32 *val) val 89 drivers/net/dsa/vitesse-vsc73xx-spi.c *val = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; val 95 drivers/net/dsa/vitesse-vsc73xx-spi.c u32 val) val 122 drivers/net/dsa/vitesse-vsc73xx-spi.c buf[0] = (val >> 24) & 0xff; val 123 drivers/net/dsa/vitesse-vsc73xx-spi.c buf[1] = (val >> 16) & 0xff; val 124 drivers/net/dsa/vitesse-vsc73xx-spi.c buf[2] = (val >> 8) & 0xff; val 125 drivers/net/dsa/vitesse-vsc73xx-spi.c buf[3] = val & 0xff; val 22 drivers/net/dsa/vitesse-vsc73xx.h u32 *val); val 24 drivers/net/dsa/vitesse-vsc73xx.h u32 val); val 2212 drivers/net/ethernet/3com/typhoon.c u32 val; val 2229 drivers/net/ethernet/3com/typhoon.c val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS); val 2230 drivers/net/ethernet/3com/typhoon.c if((val & TYPHOON_INTR_SELF) == 0) { val 2234 drivers/net/ethernet/3com/typhoon.c val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS); val 2235 drivers/net/ethernet/3com/typhoon.c if(val & TYPHOON_INTR_SELF) val 35 drivers/net/ethernet/8390/hydra.c #define ei_outb(val,port) out_8(port,val) val 37 drivers/net/ethernet/8390/hydra.c #define ei_outb_p(val,port) out_8(port,val) val 49 drivers/net/ethernet/8390/mac8390.c #define ei_outb(val, port) out_8(port, val) val 51 drivers/net/ethernet/8390/mac8390.c #define ei_outb_p(val, port) out_8(port, val) val 61 drivers/net/ethernet/8390/mcf8390.c void ei_outb(u32 val, u32 addr) val 66 drivers/net/ethernet/8390/mcf8390.c *rp = RSWAP(val); val 72 drivers/net/ethernet/8390/mcf8390.c NE2000_BYTE *rp, val; val 75 drivers/net/ethernet/8390/mcf8390.c val = *rp; val 76 drivers/net/ethernet/8390/mcf8390.c return (u8) (RSWAP(val) & 0xff); val 81 drivers/net/ethernet/8390/mcf8390.c NE2000_BYTE *rp, val; val 87 drivers/net/ethernet/8390/mcf8390.c val = *rp; val 88 drivers/net/ethernet/8390/mcf8390.c *buf++ = RSWAP(val); val 107 drivers/net/ethernet/8390/mcf8390.c NE2000_BYTE *rp, val; val 113 drivers/net/ethernet/8390/mcf8390.c val = *buf++; val 114 drivers/net/ethernet/8390/mcf8390.c *rp = RSWAP(val); val 90 drivers/net/ethernet/8390/stnic.c byte val; val 92 drivers/net/ethernet/8390/stnic.c val = (*(vhalf *) (PA_83902 + ((reg) << 1)) >> 8) & 0xff; val 94 drivers/net/ethernet/8390/stnic.c return val; val 98 drivers/net/ethernet/8390/stnic.c STNIC_WRITE (int reg, byte val) val 100 drivers/net/ethernet/8390/stnic.c *(vhalf *) (PA_83902 + ((reg) << 1)) = ((half) (val) << 8); val 226 drivers/net/ethernet/8390/stnic.c half val; val 239 drivers/net/ethernet/8390/stnic.c val = *(vhalf *) PA_83902_IF; val 241 drivers/net/ethernet/8390/stnic.c *buf++ = val & 0xff; val 242 drivers/net/ethernet/8390/stnic.c *buf++ = val >> 8; val 244 drivers/net/ethernet/8390/stnic.c *buf++ = val >> 8; val 245 drivers/net/ethernet/8390/stnic.c *buf++ = val & 0xff; val 40 drivers/net/ethernet/8390/zorro8390.c #define ei_outb(val, port) out_8(port, val) val 42 drivers/net/ethernet/8390/zorro8390.c #define ei_outb_p(val, port) out_8(port, val) val 1899 drivers/net/ethernet/adaptec/starfire.c static void set_msglevel(struct net_device *dev, u32 val) val 1901 drivers/net/ethernet/adaptec/starfire.c debug = val; val 155 drivers/net/ethernet/aeroflex/greth.c static inline void greth_write_bd(u32 *bd, u32 val) val 157 drivers/net/ethernet/aeroflex/greth.c __raw_writel(cpu_to_be32(val), bd); val 1184 drivers/net/ethernet/aeroflex/greth.c static int greth_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) val 1192 drivers/net/ethernet/aeroflex/greth.c ((val & 0xFFFF) << 16) | ((phy & 0x1F) << 11) | ((reg & 0x1F) << 6) | 1); val 529 drivers/net/ethernet/agere/et131x.c u32 val = 0; val 618 drivers/net/ethernet/agere/et131x.c &val); val 619 drivers/net/ethernet/agere/et131x.c } while ((val & 0x00010000) == 0); val 620 drivers/net/ethernet/agere/et131x.c } while (val & 0x00040000); val 622 drivers/net/ethernet/agere/et131x.c if ((val & 0xFF00) != 0xC000 || index == 10000) val 565 drivers/net/ethernet/alacritech/slic.h u32 val) val 567 drivers/net/ethernet/alacritech/slic.h iowrite32(val, sdev->regs + reg); val 225 drivers/net/ethernet/alacritech/slicoss.c u32 val; val 227 drivers/net/ethernet/alacritech/slicoss.c val = SLIC_GRCR_RESET | SLIC_GRCR_ADDRAEN | SLIC_GRCR_RCVEN | val 231 drivers/net/ethernet/alacritech/slicoss.c val |= SLIC_GRCR_CTLEN; val 234 drivers/net/ethernet/alacritech/slicoss.c val |= SLIC_GRCR_RCVALL; val 236 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WRCFG, val); val 242 drivers/net/ethernet/alacritech/slicoss.c u32 val; val 244 drivers/net/ethernet/alacritech/slicoss.c val = SLIC_GXCR_RESET | SLIC_GXCR_XMTEN; val 247 drivers/net/ethernet/alacritech/slicoss.c val |= SLIC_GXCR_PAUSEEN; val 249 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WXCFG, val); val 255 drivers/net/ethernet/alacritech/slicoss.c u32 val; val 258 drivers/net/ethernet/alacritech/slicoss.c val = SLIC_GMCR_GAPBB_1000 << SLIC_GMCR_GAPBB_SHIFT | val 263 drivers/net/ethernet/alacritech/slicoss.c val = SLIC_GMCR_GAPBB_100 << SLIC_GMCR_GAPBB_SHIFT | val 269 drivers/net/ethernet/alacritech/slicoss.c val |= SLIC_GMCR_FULLD; val 271 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WMCFG, val); val 961 drivers/net/ethernet/alacritech/slicoss.c u32 val; val 968 drivers/net/ethernet/alacritech/slicoss.c val = MII_ADVERTISE << 16 | ADVERTISE_1000XFULL | val 971 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WPHY, val); val 973 drivers/net/ethernet/alacritech/slicoss.c val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE | val 975 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WPHY, val); val 981 drivers/net/ethernet/alacritech/slicoss.c val = MII_ADVERTISE << 16 | ADVERTISE_100FULL | val 984 drivers/net/ethernet/alacritech/slicoss.c val |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; val 986 drivers/net/ethernet/alacritech/slicoss.c val |= ADVERTISE_CSMA; val 987 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WPHY, val); val 990 drivers/net/ethernet/alacritech/slicoss.c val = MII_CTRL1000 << 16 | ADVERTISE_1000FULL; val 991 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WPHY, val); val 995 drivers/net/ethernet/alacritech/slicoss.c val = SLIC_MIICR_REG_16 | SLIC_MRV_REG16_XOVERON; val 996 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WPHY, val); val 999 drivers/net/ethernet/alacritech/slicoss.c val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE | val 1001 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WPHY, val); val 1004 drivers/net/ethernet/alacritech/slicoss.c val = MII_BMCR << 16 | BMCR_ANENABLE | BMCR_ANRESTART; val 1005 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WPHY, val); val 1013 drivers/net/ethernet/alacritech/slicoss.c u32 val; val 1015 drivers/net/ethernet/alacritech/slicoss.c val = addr[5] | addr[4] << 8 | addr[3] << 16 | addr[2] << 24; val 1017 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WRADDRAL, val); val 1018 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WRADDRBL, val); val 1020 drivers/net/ethernet/alacritech/slicoss.c val = addr[0] << 8 | addr[1]; val 1022 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WRADDRAH, val); val 1023 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WRADDRBH, val); val 1030 drivers/net/ethernet/alacritech/slicoss.c __le32 val; val 1032 drivers/net/ethernet/alacritech/slicoss.c memcpy(&val, fw->data + *offset, sizeof(val)); val 1036 drivers/net/ethernet/alacritech/slicoss.c return le32_to_cpu(val); val 1084 drivers/net/ethernet/alacritech/slicoss.c __le32 val; val 1092 drivers/net/ethernet/alacritech/slicoss.c val = (__le32)fw->data[idx]; val 1093 drivers/net/ethernet/alacritech/slicoss.c instr = le32_to_cpu(val); val 1371 drivers/net/ethernet/alacritech/slicoss.c u32 val; val 1383 drivers/net/ethernet/alacritech/slicoss.c val = SLIC_GXCR_RESET | SLIC_GXCR_PAUSEEN; val 1384 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WXCFG, val); val 1386 drivers/net/ethernet/alacritech/slicoss.c val = SLIC_GRCR_RESET | SLIC_GRCR_CTLEN | SLIC_GRCR_ADDRAEN | val 1388 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WRCFG, val); val 1390 drivers/net/ethernet/alacritech/slicoss.c val = MII_BMCR << 16 | BMCR_PDOWN; val 1391 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WPHY, val); val 511 drivers/net/ethernet/altera/altera_tse.h void csrwr32(u32 val, void __iomem *mac, size_t offs) val 515 drivers/net/ethernet/altera/altera_tse.h writel(val, paddr); val 519 drivers/net/ethernet/altera/altera_tse.h void csrwr16(u16 val, void __iomem *mac, size_t offs) val 523 drivers/net/ethernet/altera/altera_tse.h writew(val, paddr); val 527 drivers/net/ethernet/altera/altera_tse.h void csrwr8(u8 val, void __iomem *mac, size_t offs) val 531 drivers/net/ethernet/altera/altera_tse.h writeb(val, paddr); val 946 drivers/net/ethernet/amazon/ena/ena_com.c u32 val, i; val 952 drivers/net/ethernet/amazon/ena/ena_com.c val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); val 954 drivers/net/ethernet/amazon/ena/ena_com.c if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { val 959 drivers/net/ethernet/amazon/ena/ena_com.c if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == val 330 drivers/net/ethernet/amazon/ena/ena_ethtool.c unsigned int val; val 333 drivers/net/ethernet/amazon/ena/ena_ethtool.c val = ena_com_get_nonadaptive_moderation_interval_tx(adapter->ena_dev); val 336 drivers/net/ethernet/amazon/ena/ena_ethtool.c adapter->tx_ring[i].smoothed_interval = val; val 341 drivers/net/ethernet/amazon/ena/ena_ethtool.c unsigned int val; val 344 drivers/net/ethernet/amazon/ena/ena_ethtool.c val = ena_com_get_nonadaptive_moderation_interval_rx(adapter->ena_dev); val 347 drivers/net/ethernet/amazon/ena/ena_ethtool.c adapter->rx_ring[i].smoothed_interval = val; val 3300 drivers/net/ethernet/amazon/ena/ena_netdev.c u32 val; val 3309 drivers/net/ethernet/amazon/ena/ena_netdev.c val = ethtool_rxfh_indir_default(i, adapter->num_queues); val 3311 drivers/net/ethernet/amazon/ena/ena_netdev.c ENA_IO_RXQ_IDX(val)); val 47 drivers/net/ethernet/amd/am79c961a.c static void write_rreg(u_long base, u_int reg, u_int val) val 53 drivers/net/ethernet/amd/am79c961a.c : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464)); val 67 drivers/net/ethernet/amd/am79c961a.c static inline void write_ireg(u_long base, u_int reg, u_int val) val 73 drivers/net/ethernet/amd/am79c961a.c : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464)); val 87 drivers/net/ethernet/amd/am79c961a.c #define am_writeword(dev,off,val) __raw_writew(val, ISAMEM_BASE + ((off) << 1)) val 169 drivers/net/ethernet/amd/am79c961a.c am79c961_ramtest(struct net_device *dev, unsigned int val) val 176 drivers/net/ethernet/amd/am79c961a.c memset (buffer, val, 65536); val 178 drivers/net/ethernet/amd/am79c961a.c memset (buffer, val ^ 255, 65536); val 181 drivers/net/ethernet/amd/am79c961a.c if (buffer[i] != val && !error) { val 182 drivers/net/ethernet/amd/am79c961a.c printk ("%s: buffer error (%02X %02X) %05X - ", dev->name, val, buffer[i], i); val 185 drivers/net/ethernet/amd/am79c961a.c } else if (error && buffer[i] == val) { val 100 drivers/net/ethernet/amd/amd8111e.c int phy_id, int reg, u32 *val) val 119 drivers/net/ethernet/amd/amd8111e.c *val = reg_val & 0xffff; val 122 drivers/net/ethernet/amd/amd8111e.c *val = 0; val 129 drivers/net/ethernet/amd/amd8111e.c int phy_id, int reg, u32 val) val 140 drivers/net/ethernet/amd/amd8111e.c ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); val 170 drivers/net/ethernet/amd/amd8111e.c int phy_id, int reg_num, int val) val 174 drivers/net/ethernet/amd/amd8111e.c amd8111e_write_phy(lp, phy_id, reg_num, val); val 159 drivers/net/ethernet/amd/ni65.c #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \ val 160 drivers/net/ethernet/amd/ni65.c outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);} val 164 drivers/net/ethernet/amd/ni65.c #define writedatareg(val) {outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);} val 166 drivers/net/ethernet/amd/ni65.c #define writedatareg(val) { writereg(val,CSR0); } val 169 drivers/net/ethernet/amd/ni65.c #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);} val 171 drivers/net/ethernet/amd/ni65.c #define writedatareg(val) { writereg(val,CSR0); } val 327 drivers/net/ethernet/amd/pcnet32.c int val); val 346 drivers/net/ethernet/amd/pcnet32.c static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) val 349 drivers/net/ethernet/amd/pcnet32.c outw(val, addr + PCNET32_WIO_RDP); val 358 drivers/net/ethernet/amd/pcnet32.c static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) val 361 drivers/net/ethernet/amd/pcnet32.c outw(val, addr + PCNET32_WIO_BDP); val 369 drivers/net/ethernet/amd/pcnet32.c static void pcnet32_wio_write_rap(unsigned long addr, u16 val) val 371 drivers/net/ethernet/amd/pcnet32.c outw(val, addr + PCNET32_WIO_RAP); val 401 drivers/net/ethernet/amd/pcnet32.c static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) val 404 drivers/net/ethernet/amd/pcnet32.c outl(val, addr + PCNET32_DWIO_RDP); val 413 drivers/net/ethernet/amd/pcnet32.c static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) val 416 drivers/net/ethernet/amd/pcnet32.c outl(val, addr + PCNET32_DWIO_BDP); val 424 drivers/net/ethernet/amd/pcnet32.c static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) val 426 drivers/net/ethernet/amd/pcnet32.c outl(val, addr + PCNET32_DWIO_RAP); val 463 drivers/net/ethernet/amd/pcnet32.c u16 val; val 466 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, CSR3); val 467 drivers/net/ethernet/amd/pcnet32.c val &= 0x00ff; val 468 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR3, val); val 1404 drivers/net/ethernet/amd/pcnet32.c u16 val; val 1419 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, CSR3); val 1420 drivers/net/ethernet/amd/pcnet32.c val &= 0x00ff; val 1421 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR3, val); val 1773 drivers/net/ethernet/amd/pcnet32.c unsigned int val; val 1774 drivers/net/ethernet/amd/pcnet32.c val = a->read_csr(ioaddr, i + 12) & 0x0ffff; val 1776 drivers/net/ethernet/amd/pcnet32.c dev->dev_addr[2 * i] = val & 0x0ff; val 1777 drivers/net/ethernet/amd/pcnet32.c dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; val 2099 drivers/net/ethernet/amd/pcnet32.c u16 val; val 2134 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_bcr(ioaddr, 2) & ~2; val 2136 drivers/net/ethernet/amd/pcnet32.c val |= 2; val 2137 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 2, val); val 2141 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_bcr(ioaddr, 9) & ~3; val 2143 drivers/net/ethernet/amd/pcnet32.c val |= 1; val 2145 drivers/net/ethernet/amd/pcnet32.c val |= 2; val 2149 drivers/net/ethernet/amd/pcnet32.c val |= 3; val 2151 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 9, val); val 2155 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, 124) & ~0x10; val 2157 drivers/net/ethernet/amd/pcnet32.c val |= 0x10; val 2158 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, 124, val); val 2180 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_bcr(ioaddr, 32) & ~0xb8; val 2182 drivers/net/ethernet/amd/pcnet32.c val |= 0x10; val 2184 drivers/net/ethernet/amd/pcnet32.c val |= 0x08; val 2185 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 32, val); val 2192 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_bcr(ioaddr, 32) & ~0x98; val 2193 drivers/net/ethernet/amd/pcnet32.c val |= 0x20; val 2194 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 32, val); val 2207 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_bcr(ioaddr, 2); val 2208 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 2, val & ~2); val 2209 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_bcr(ioaddr, 32); val 2210 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ val 2260 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, CSR3); val 2261 drivers/net/ethernet/amd/pcnet32.c val |= 0x40; val 2262 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR3, val); val 2606 drivers/net/ethernet/amd/pcnet32.c u16 val; val 2608 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, CSR3); val 2609 drivers/net/ethernet/amd/pcnet32.c val |= 0x5f00; val 2610 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR3, val); val 2772 drivers/net/ethernet/amd/pcnet32.c static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) val 2781 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 34, val); val 1028 drivers/net/ethernet/amd/sunlance.c u32 val; val 1030 drivers/net/ethernet/amd/sunlance.c val = p8[0] << 24; val 1031 drivers/net/ethernet/amd/sunlance.c val |= p8[1] << 16; val 1032 drivers/net/ethernet/amd/sunlance.c val |= p8[2] << 8; val 1033 drivers/net/ethernet/amd/sunlance.c val |= p8[3]; val 1034 drivers/net/ethernet/amd/sunlance.c sbus_writel(val, piobuf); val 1044 drivers/net/ethernet/amd/sunlance.c u32 val = p16[0]<<16 | p16[1]; val 1045 drivers/net/ethernet/amd/sunlance.c sbus_writel(val, piobuf); val 1054 drivers/net/ethernet/amd/sunlance.c u16 val = src[0] << 8 | src[1]; val 1055 drivers/net/ethernet/amd/sunlance.c sbus_writew(val, piobuf); val 1169 drivers/net/ethernet/amd/sunlance.c u32 val; val 1173 drivers/net/ethernet/amd/sunlance.c val = ~0; val 1175 drivers/net/ethernet/amd/sunlance.c val = 0; val 1179 drivers/net/ethernet/amd/sunlance.c sbus_writel(val, &ib->filter[0]); val 1180 drivers/net/ethernet/amd/sunlance.c sbus_writel(val, &ib->filter[1]); val 1183 drivers/net/ethernet/amd/sunlance.c ib->filter [0] = val; val 1184 drivers/net/ethernet/amd/sunlance.c ib->filter [1] = val; val 222 drivers/net/ethernet/amd/xgbe/xgbe-dev.c static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) val 227 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); val 232 drivers/net/ethernet/amd/xgbe/xgbe-dev.c static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) val 237 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); val 243 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int val) val 248 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); val 254 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int val) val 259 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); val 324 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int index, unsigned int val) val 336 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, MAC_RSSDR, val); val 938 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int val = enable ? 1 : 0; val 940 drivers/net/ethernet/amd/xgbe/xgbe-dev.c if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) val 945 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); val 961 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int val = enable ? 1 : 0; val 963 drivers/net/ethernet/amd/xgbe/xgbe-dev.c if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) val 968 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); val 1302 drivers/net/ethernet/amd/xgbe/xgbe-dev.c int reg, u16 val) val 1312 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); val 2812 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int val; val 2814 drivers/net/ethernet/amd/xgbe/xgbe-dev.c val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; val 2816 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); val 2855 drivers/net/ethernet/amd/xgbe/xgbe-dev.c u64 val; val 2886 drivers/net/ethernet/amd/xgbe/xgbe-dev.c val = XGMAC_IOREAD(pdata, reg_lo); val 2889 drivers/net/ethernet/amd/xgbe/xgbe-dev.c val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); val 2891 drivers/net/ethernet/amd/xgbe/xgbe-dev.c return val; val 396 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c unsigned int val) val 409 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c *redrv_val = cpu_to_be16(val); val 458 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c void *val, unsigned int val_len) val 469 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c i2c_op.buf = val; val 479 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c void *val, unsigned int val_len) val 505 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c i2c_op.buf = val; val 601 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c int reg, u16 val) val 613 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); val 616 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) val 628 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c *mii_val = cpu_to_be16(val); val 638 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) val 649 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ret = xgbe_phy_i2c_mii_write(pdata, reg, val); val 651 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); val 12 drivers/net/ethernet/apm/xgene-v2/enet.c void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val) val 16 drivers/net/ethernet/apm/xgene-v2/enet.c iowrite32(val, addr); val 28 drivers/net/ethernet/apm/xgene-v2/enet.h void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val); val 60 drivers/net/ethernet/apm/xgene-v2/mac.h static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val) val 65 drivers/net/ethernet/apm/xgene-v2/mac.h *var |= ((val << pos) & mask); val 75 drivers/net/ethernet/apm/xgene-v2/mac.h #define SET_REG_BITS(var, field, val) \ val 76 drivers/net/ethernet/apm/xgene-v2/mac.h xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val) val 78 drivers/net/ethernet/apm/xgene-v2/mac.h #define SET_REG_BIT(var, field, val) \ val 79 drivers/net/ethernet/apm/xgene-v2/mac.h xgene_set_reg_bits(var, field ## _POS, 1, val) val 15 drivers/net/ethernet/apm/xgene-v2/mdio.c u32 done, val = 0; val 18 drivers/net/ethernet/apm/xgene-v2/mdio.c SET_REG_BITS(&val, PHY_ADDR, phy_id); val 19 drivers/net/ethernet/apm/xgene-v2/mdio.c SET_REG_BITS(&val, REG_ADDR, reg); val 20 drivers/net/ethernet/apm/xgene-v2/mdio.c xge_wr_csr(pdata, MII_MGMT_ADDRESS, val); val 39 drivers/net/ethernet/apm/xgene-v2/mdio.c u32 data, done, val = 0; val 42 drivers/net/ethernet/apm/xgene-v2/mdio.c SET_REG_BITS(&val, PHY_ADDR, phy_id); val 43 drivers/net/ethernet/apm/xgene-v2/mdio.c SET_REG_BITS(&val, REG_ADDR, reg); val 44 drivers/net/ethernet/apm/xgene-v2/mdio.c xge_wr_csr(pdata, MII_MGMT_ADDRESS, val); val 85 drivers/net/ethernet/apm/xgene-v2/ring.h static inline u64 xge_set_desc_bits(int pos, int len, u64 val) val 87 drivers/net/ethernet/apm/xgene-v2/ring.h return (val & ((1ULL << len) - 1)) << pos; val 95 drivers/net/ethernet/apm/xgene-v2/ring.h #define SET_BITS(field, val) \ val 96 drivers/net/ethernet/apm/xgene-v2/ring.h xge_set_desc_bits(field ## _POS, field ## _LEN, val) val 733 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c u32 offset, val = 0; val 744 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c val = (RSS_IPV4_12B << 1) | 0x1; val 745 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c writel(val, base + RSS_CTRL0 + offset); val 37 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 val; val 40 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR; val 41 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c ring_cfg[4] |= (val << RINGTYPE_POS) & val 224 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 offset, u32 val) val 228 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c iowrite32(val, addr); val 232 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 offset, u32 val) val 236 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c iowrite32(val, addr); val 240 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 offset, u32 val) val 244 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c iowrite32(val, addr); val 248 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 offset, u32 val) val 252 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c iowrite32(val, addr); val 291 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 offset, u32 *val) val 295 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c *val = ioread32(addr); val 299 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 offset, u32 *val) val 303 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c *val = ioread32(addr); val 307 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 offset, u32 *val) val 311 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c *val = ioread32(addr); val 620 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c u32 val = 0xffffffff; val 622 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val); val 623 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val); val 624 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val); val 625 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val); val 20 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) val 26 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h *dst |= (val << start) & mask; val 29 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) val 31 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h return (val & GENMASK(end, start)) >> start; val 139 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) val 157 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) val 158 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) val 160 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) val 161 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5) val 162 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) val 163 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) val 164 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4) val 165 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) val 166 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) val 167 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0)) val 168 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16)) val 180 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_NXTFPSEL0(val) (((val) << 20) & GENMASK(23, 20)) val 205 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) val 206 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) val 207 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) val 208 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) val 38 drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c u32 val; val 41 drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR; val 42 drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c ring_cfg[4] |= SET_VAL(X2_RINGTYPE, val); val 14 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val) val 16 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c iowrite32(val, p->eth_csr_addr + offset); val 20 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c u32 val) val 22 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c iowrite32(val, p->base_addr + offset); val 26 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c u32 offset, u32 val) val 28 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c iowrite32(val, p->eth_ring_if_addr + offset); val 32 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c u32 offset, u32 val) val 34 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c iowrite32(val, p->eth_diag_csr_addr + offset); val 38 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c u32 offset, u32 val) val 42 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c iowrite32(val, addr); val 106 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c u32 val; val 108 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c val = (p->enet_id == XGENE_ENET1) ? 0xffffffff : 0; val 109 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val); val 110 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val); val 16 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c u32 offset, u32 val) val 20 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c iowrite32(val, addr); val 24 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c u32 offset, u32 val) val 28 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c iowrite32(val, addr); val 32 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c u32 offset, u32 val) val 36 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c iowrite32(val, addr); val 78 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c u32 offset, u32 val) val 82 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c iowrite32(val, addr); val 86 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c u32 offset, u32 *val) val 90 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c *val = ioread32(addr); val 94 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c u32 offset, u32 *val) val 98 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c *val = ioread32(addr); val 144 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c u32 offset, u32 *val) val 148 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c *val = ioread32(addr); val 58 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define RSIF_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 3) val 61 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2) val 242 drivers/net/ethernet/apple/bmac.c unsigned int val = 0; val 248 drivers/net/ethernet/apple/bmac.c val |= 1 << nb; val 256 drivers/net/ethernet/apple/bmac.c return val; val 260 drivers/net/ethernet/apple/bmac.c bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb) val 265 drivers/net/ethernet/apple/bmac.c b = (val & (1 << nb))? 6: 4; val 276 drivers/net/ethernet/apple/bmac.c unsigned int val; val 287 drivers/net/ethernet/apple/bmac.c val = bmac_mif_readbits(dev, 17); val 290 drivers/net/ethernet/apple/bmac.c return val; val 294 drivers/net/ethernet/apple/bmac.c bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val) val 302 drivers/net/ethernet/apple/bmac.c bmac_mif_writebits(dev, val, 16); val 1091 drivers/net/ethernet/apple/bmac.c unsigned short val; val 1098 drivers/net/ethernet/apple/bmac.c val = (data >> SD0ShiftCount) & 1; val 1103 drivers/net/ethernet/apple/bmac.c return val; val 1107 drivers/net/ethernet/apple/bmac.c bmac_clock_in_bit(struct net_device *dev, unsigned int val) val 1111 drivers/net/ethernet/apple/bmac.c if (val != 0 && val != 1) return; val 1113 drivers/net/ethernet/apple/bmac.c data = (val << SDIShiftCount); val 1140 drivers/net/ethernet/apple/bmac.c unsigned short data, val; val 1145 drivers/net/ethernet/apple/bmac.c val = addr >> (addr_len-i-1); val 1146 drivers/net/ethernet/apple/bmac.c bmac_clock_in_bit(dev, val & 1); val 1152 drivers/net/ethernet/apple/bmac.c val = bmac_clock_out_bit(dev); val 1154 drivers/net/ethernet/apple/bmac.c data |= val; val 16 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c u32 shift, u32 val) val 22 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c reg_new = (reg_old & (~msk)) | (val << shift); val 27 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c aq_hw_write_reg(aq_hw, addr, val); val 31 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h u32 shift, u32 val); val 85 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c u32 val; val 97 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c self, val, val == 0, val 107 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c self, val, val == 0, val 186 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c u32 val; val 195 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c self, val, val == 0, val 216 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c u32 val; val 231 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c self, val, val == 0, val 175 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c u32 val; val 184 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c self, val, val == 0, val 205 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c u32 val; val 220 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c self, val, val == 0, val 255 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U : val 260 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i); val 399 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c u32 val; val 416 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR); val 418 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c (val & ~0x707) | 0x404); val 973 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c u32 val; val 988 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c self, val, val == 1, 1000U, 10000U); val 611 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c u32 val; val 613 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c val = aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR, val 620 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c val ^ 1); val 986 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) val 990 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c HW_ATL_RPF_L4_SPD_SHIFT, val); val 993 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) val 997 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c HW_ATL_RPF_L4_DPD_SHIFT, val); val 478 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter); val 481 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter); val 95 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 gsr, val; val 102 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val = aq_hw_read_reg(self, 0x53C); val 103 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c aq_hw_write_reg(self, 0x53C, val | 0x10); val 114 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val = aq_hw_read_reg(self, 0x53C); val 115 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c aq_hw_write_reg(self, 0x53C, val | 0x10); val 118 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c aq_hw_write_reg(self, 0x53C, val & ~0x10); val 171 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 gsr, val, rbl_status; val 182 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val = aq_hw_read_reg(self, 0x53C); val 183 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c aq_hw_write_reg(self, 0x53C, val | 0x10); val 242 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 val; val 270 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c self, val, val 271 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c (val & HW_ATL_MPI_STATE_MSK) == val 288 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 val; val 291 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c self, val, val == 1U, val 312 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c self, val, val != a, val 316 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c self, val, val 317 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c !(val & 0x100), val 333 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 val; val 337 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val, val == 1U, val 352 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c self, val, val 353 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c (val & 0xF0000000) != val 367 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c self, val, val 368 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c (val & 0x100) == 0, val 426 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 val; val 454 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c aq_hw_write_reg(self, HW_ATL_RPC_CONTROL_ADR, sw.val); val 468 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c sw.val = aq_hw_read_reg(self, HW_ATL_RPC_CONTROL_ADR); val 473 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c self, fw.val, val 563 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR); val 565 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val = val & ~HW_ATL_MPI_SPEED_MSK; val 566 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val |= speed << HW_ATL_MPI_SPEED_SHIFT; val 567 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val); val 578 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR); val 597 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val |= HW_ATL_MPI_DIRTY_WAKE_MSK; val 599 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val &= ~HW_ATL_MPI_DIRTY_WAKE_MSK; val 602 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val = val & ~HW_ATL_MPI_STATE_MSK; val 603 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c val |= state & HW_ATL_MPI_STATE_MSK; val 605 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val); val 739 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 val = hw_atl_reg_glb_mif_id_get(self); val 740 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c u32 mif_rev = val & 0xFFU; val 163 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c u32 val = link_speed_mask_2fw2x_ratemask(speed); val 165 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val); val 318 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c u32 val; val 327 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val, val 329 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c (val & HW_ATL_FW2X_CTRL_TEMPERATURE), val 352 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c u32 val; val 382 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c self, val, val 383 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c val & HW_ATL_FW2X_CTRL_SLEEP_PROXY, val 396 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c u32 val; val 424 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c self, val, val & HW_ATL_FW2X_CTRL_WOL, val 419 drivers/net/ethernet/atheros/ag71xx.c int err, val; val 434 drivers/net/ethernet/atheros/ag71xx.c val = ag71xx_rr(ag, AG71XX_REG_MII_STATUS); val 439 drivers/net/ethernet/atheros/ag71xx.c addr, reg, val); val 441 drivers/net/ethernet/atheros/ag71xx.c return val; val 445 drivers/net/ethernet/atheros/ag71xx.c u16 val) val 450 drivers/net/ethernet/atheros/ag71xx.c addr, reg, val); val 454 drivers/net/ethernet/atheros/ag71xx.c ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val); val 722 drivers/net/ethernet/atheros/ag71xx.c u32 val; val 748 drivers/net/ethernet/atheros/ag71xx.c val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); val 749 drivers/net/ethernet/atheros/ag71xx.c if (val) val 751 drivers/net/ethernet/atheros/ag71xx.c val); val 753 drivers/net/ethernet/atheros/ag71xx.c val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); val 756 drivers/net/ethernet/atheros/ag71xx.c val &= ~0xff000000; val 758 drivers/net/ethernet/atheros/ag71xx.c if (val) val 760 drivers/net/ethernet/atheros/ag71xx.c val); val 48 drivers/net/ethernet/atheros/alx/hw.c u32 val; val 52 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MDIO); val 53 drivers/net/ethernet/atheros/alx/hw.c if (!(val & ALX_MDIO_BUSY)) val 64 drivers/net/ethernet/atheros/alx/hw.c u32 val, clk_sel; val 75 drivers/net/ethernet/atheros/alx/hw.c val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT | val 77 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MDIO_EXTN, val); val 79 drivers/net/ethernet/atheros/alx/hw.c val = ALX_MDIO_SPRES_PRMBL | ALX_MDIO_START | val 83 drivers/net/ethernet/atheros/alx/hw.c val = ALX_MDIO_SPRES_PRMBL | val 88 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MDIO, val); val 93 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MDIO); val 94 drivers/net/ethernet/atheros/alx/hw.c *phy_data = ALX_GET_FIELD(val, ALX_MDIO_DATA); val 101 drivers/net/ethernet/atheros/alx/hw.c u32 val, clk_sel; val 109 drivers/net/ethernet/atheros/alx/hw.c val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT | val 111 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MDIO_EXTN, val); val 113 drivers/net/ethernet/atheros/alx/hw.c val = ALX_MDIO_SPRES_PRMBL | val 118 drivers/net/ethernet/atheros/alx/hw.c val = ALX_MDIO_SPRES_PRMBL | val 124 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MDIO, val); val 239 drivers/net/ethernet/atheros/alx/hw.c u32 val; val 242 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_PHY_CTRL); val 244 drivers/net/ethernet/atheros/alx/hw.c if ((val & ALX_PHY_CTRL_DSPRST_OUT) == 0) val 247 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_DRV); val 248 drivers/net/ethernet/atheros/alx/hw.c val = ALX_GET_FIELD(val, ALX_DRV_PHY); val 249 drivers/net/ethernet/atheros/alx/hw.c if (ALX_DRV_PHY_UNKNOWN == val) val 254 drivers/net/ethernet/atheros/alx/hw.c return val; val 259 drivers/net/ethernet/atheros/alx/hw.c static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val) val 267 drivers/net/ethernet/atheros/alx/hw.c if (val) val 268 drivers/net/ethernet/atheros/alx/hw.c *val = read; val 293 drivers/net/ethernet/atheros/alx/hw.c u32 val; val 300 drivers/net/ethernet/atheros/alx/hw.c if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_STAT | ALX_SLD_START, &val)) val 302 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START); val 309 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_EFLD); val 310 drivers/net/ethernet/atheros/alx/hw.c if (val & (ALX_EFLD_F_EXIST | ALX_EFLD_E_EXIST)) { val 312 drivers/net/ethernet/atheros/alx/hw.c ALX_EFLD_STAT | ALX_EFLD_START, &val)) val 314 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START); val 326 drivers/net/ethernet/atheros/alx/hw.c u32 val; val 329 drivers/net/ethernet/atheros/alx/hw.c val = be32_to_cpu(get_unaligned((__be32 *)(addr + 2))); val 330 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_STAD0, val); val 331 drivers/net/ethernet/atheros/alx/hw.c val = be16_to_cpu(get_unaligned((__be16 *)addr)); val 332 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_STAD1, val); val 337 drivers/net/ethernet/atheros/alx/hw.c u32 val, val2; val 340 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MISC3); val 342 drivers/net/ethernet/atheros/alx/hw.c (val & ~ALX_MISC3_25M_BY_SW) | val 348 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MISC); val 353 drivers/net/ethernet/atheros/alx/hw.c ALX_SET_FIELD(val, ALX_MISC_PSW_OCP, ALX_MISC_PSW_OCP_DEF); val 355 drivers/net/ethernet/atheros/alx/hw.c val &= ~ALX_MISC_INTNLOSC_OPEN; val 356 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MISC, val); val 357 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); val 364 drivers/net/ethernet/atheros/alx/hw.c val &= ~ALX_MISC_INTNLOSC_OPEN; val 367 drivers/net/ethernet/atheros/alx/hw.c val &= ~ALX_MISC_ISO_EN; val 369 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); val 370 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MISC, val); val 378 drivers/net/ethernet/atheros/alx/hw.c u32 rxq, txq, val; val 392 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MAC_STS); val 393 drivers/net/ethernet/atheros/alx/hw.c if (!(val & ALX_MAC_STS_IDLE)) val 403 drivers/net/ethernet/atheros/alx/hw.c u32 val, pmctrl; val 434 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MASTER); val 436 drivers/net/ethernet/atheros/alx/hw.c val | ALX_MASTER_DMA_MAC_RST | ALX_MASTER_OOB_DIS); val 441 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_RFD_PIDX); val 442 drivers/net/ethernet/atheros/alx/hw.c if (val == 0) val 447 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MASTER); val 448 drivers/net/ethernet/atheros/alx/hw.c if ((val & ALX_MASTER_DMA_MAC_RST) == 0) val 457 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS); val 468 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MISC3); val 470 drivers/net/ethernet/atheros/alx/hw.c (val & ~ALX_MISC3_25M_BY_SW) | val 472 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MISC); val 473 drivers/net/ethernet/atheros/alx/hw.c val &= ~ALX_MISC_INTNLOSC_OPEN; val 475 drivers/net/ethernet/atheros/alx/hw.c val &= ~ALX_MISC_ISO_EN; val 476 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MISC, val); val 482 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_SERDES); val 484 drivers/net/ethernet/atheros/alx/hw.c val | ALX_SERDES_MACCLK_SLWDWN | val 493 drivers/net/ethernet/atheros/alx/hw.c u32 val; val 497 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_PHY_CTRL); val 498 drivers/net/ethernet/atheros/alx/hw.c val &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_IDDQ | val 501 drivers/net/ethernet/atheros/alx/hw.c val |= ALX_PHY_CTRL_RST_ANALOG; val 503 drivers/net/ethernet/atheros/alx/hw.c val |= (ALX_PHY_CTRL_HIB_PULSE | ALX_PHY_CTRL_HIB_EN); val 504 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_PHY_CTRL, val); val 506 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT); val 519 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_LPI_CTRL); val 520 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN); val 563 drivers/net/ethernet/atheros/alx/hw.c u32 val; val 574 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_WOL0); val 577 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_PDLL_TRNS1); val 578 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN); val 581 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_UE_SVRT); val 582 drivers/net/ethernet/atheros/alx/hw.c val &= ~(ALX_UE_SVRT_DLPROTERR | ALX_UE_SVRT_FCPROTERR); val 583 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_UE_SVRT, val); val 586 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MASTER); val 588 drivers/net/ethernet/atheros/alx/hw.c if ((val & ALX_MASTER_WAKEN_25M) == 0 || val 589 drivers/net/ethernet/atheros/alx/hw.c (val & ALX_MASTER_PCLKSEL_SRDS) == 0) val 591 drivers/net/ethernet/atheros/alx/hw.c val | ALX_MASTER_PCLKSEL_SRDS | val 594 drivers/net/ethernet/atheros/alx/hw.c if ((val & ALX_MASTER_WAKEN_25M) == 0 || val 595 drivers/net/ethernet/atheros/alx/hw.c (val & ALX_MASTER_PCLKSEL_SRDS) != 0) val 597 drivers/net/ethernet/atheros/alx/hw.c (val & ~ALX_MASTER_PCLKSEL_SRDS) | val 725 drivers/net/ethernet/atheros/alx/hw.c u32 val; val 729 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_DRV); val 730 drivers/net/ethernet/atheros/alx/hw.c ALX_SET_FIELD(val, ALX_DRV_PHY, 0); val 769 drivers/net/ethernet/atheros/alx/hw.c val |= ethadv_to_hw_cfg(hw, ethadv); val 772 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_DRV, val); val 933 drivers/net/ethernet/atheros/alx/hw.c u32 val, raw_mtu, max_payload; val 948 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_MASTER); val 949 drivers/net/ethernet/atheros/alx/hw.c val |= ALX_MASTER_IRQMOD2_EN | val 952 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_MASTER, val); val 967 drivers/net/ethernet/atheros/alx/hw.c val = (raw_mtu + 7) >> 3; val 969 drivers/net/ethernet/atheros/alx/hw.c val = ALX_TXQ1_JUMBO_TSO_TH >> 3; val 970 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN); val 980 drivers/net/ethernet/atheros/alx/hw.c val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_TXQ0_TPD_BURSTPREF_SHIFT | val 984 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_TXQ0, val); val 985 drivers/net/ethernet/atheros/alx/hw.c val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q1_NUMPREF_SHIFT | val 989 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_HQTPD, val); val 992 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_SRAM5); val 993 drivers/net/ethernet/atheros/alx/hw.c val = ALX_GET_FIELD(val, ALX_SRAM_RXF_LEN) << 3; val 994 drivers/net/ethernet/atheros/alx/hw.c if (val > ALX_SRAM_RXF_LEN_8K) { val 996 drivers/net/ethernet/atheros/alx/hw.c val = (val - ALX_RXQ2_RXF_FLOW_CTRL_RSVD) >> 3; val 999 drivers/net/ethernet/atheros/alx/hw.c val = (val - ALX_MTU_STD_ALGN) >> 3; val 1003 drivers/net/ethernet/atheros/alx/hw.c val << ALX_RXQ2_RXF_XON_THRESH_SHIFT); val 1004 drivers/net/ethernet/atheros/alx/hw.c val = ALX_RXQ0_NUM_RFD_PREF_DEF << ALX_RXQ0_NUM_RFD_PREF_SHIFT | val 1011 drivers/net/ethernet/atheros/alx/hw.c ALX_SET_FIELD(val, ALX_RXQ0_ASPM_THRESH, val 1014 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_RXQ0, val); val 1016 drivers/net/ethernet/atheros/alx/hw.c val = alx_read_mem32(hw, ALX_DMA); val 1017 drivers/net/ethernet/atheros/alx/hw.c val = ALX_DMA_RORDER_MODE_OUT << ALX_DMA_RORDER_MODE_SHIFT | val 1023 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_DMA, val); val 1026 drivers/net/ethernet/atheros/alx/hw.c val = ALX_WRR_PRI_RESTRICT_NONE << ALX_WRR_PRI_SHIFT | val 1031 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, ALX_WRR, val); val 1036 drivers/net/ethernet/atheros/alx/hw.c u32 reg, val; val 1041 drivers/net/ethernet/atheros/alx/hw.c val = mask ? PCI_MSIX_ENTRY_CTRL_MASKBIT : 0; val 1043 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, reg, val); val 516 drivers/net/ethernet/atheros/alx/hw.h static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val) val 518 drivers/net/ethernet/atheros/alx/hw.h writeb(val, hw->hw_addr + reg); val 521 drivers/net/ethernet/atheros/alx/hw.h static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val) val 523 drivers/net/ethernet/atheros/alx/hw.h writew(val, hw->hw_addr + reg); val 531 drivers/net/ethernet/atheros/alx/hw.h static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val) val 533 drivers/net/ethernet/atheros/alx/hw.h writel(val, hw->hw_addr + reg); val 1568 drivers/net/ethernet/atheros/alx/main.c u16 val; val 1575 drivers/net/ethernet/atheros/alx/main.c err = alx_read_phy_reg(hw, addr, &val); val 1577 drivers/net/ethernet/atheros/alx/main.c err = alx_read_phy_ext(hw, devad, addr, &val); val 1581 drivers/net/ethernet/atheros/alx/main.c return val; val 1585 drivers/net/ethernet/atheros/alx/main.c int prtad, int devad, u16 addr, u16 val) val 1594 drivers/net/ethernet/atheros/alx/main.c return alx_write_phy_reg(hw, addr, val); val 1596 drivers/net/ethernet/atheros/alx/main.c return alx_write_phy_ext(hw, devad, addr, val); val 252 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c u32 val; val 256 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c AT_READ_REG(hw, REG_MDIO_CTRL, &val); val 257 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c if (!(val & (MDIO_CTRL_BUSY | MDIO_CTRL_START))) val 276 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c u32 val; val 281 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = MDIO_CTRL_SPRES_PRMBL | val 286 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c AT_WRITE_REG(hw, REG_MDIO_CTRL, val); val 288 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val |= MDIO_CTRL_AP_EN; val 289 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val &= ~MDIO_CTRL_START; val 290 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c AT_WRITE_REG(hw, REG_MDIO_CTRL, val); val 305 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c u32 val; val 317 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg); val 318 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c AT_WRITE_REG(hw, REG_MDIO_EXTN, val); val 319 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = MDIO_CTRL_SPRES_PRMBL | val 325 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = MDIO_CTRL_SPRES_PRMBL | val 331 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c AT_WRITE_REG(hw, REG_MDIO_CTRL, val); val 336 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c AT_READ_REG(hw, REG_MDIO_CTRL, &val); val 337 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c *phy_data = (u16)FIELD_GETX(val, MDIO_CTRL_DATA); val 354 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c u32 val; val 366 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg); val 367 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c AT_WRITE_REG(hw, REG_MDIO_EXTN, val); val 368 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = MDIO_CTRL_SPRES_PRMBL | val 374 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = MDIO_CTRL_SPRES_PRMBL | val 380 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c AT_WRITE_REG(hw, REG_MDIO_CTRL, val); val 569 drivers/net/ethernet/atheros/atl1c/atl1c_main.c int reg_num, int val) val 573 drivers/net/ethernet/atheros/atl1c/atl1c_main.c atl1c_write_phy_reg(&adapter->hw, reg_num, val); val 202 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c u32 val; val 205 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | val 209 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c AT_WRITE_REG(hw, REG_MDIO_CTRL, val); val 215 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c val = AT_READ_REG(hw, REG_MDIO_CTRL); val 216 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c if (!(val & (MDIO_START | MDIO_BUSY))) val 220 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c if (!(val & (MDIO_START | MDIO_BUSY))) { val 221 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c *phy_data = (u16)val; val 237 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c u32 val; val 239 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | val 245 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c AT_WRITE_REG(hw, REG_MDIO_CTRL, val); val 250 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c val = AT_READ_REG(hw, REG_MDIO_CTRL); val 251 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c if (!(val & (MDIO_START | MDIO_BUSY))) val 256 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c if (!(val & (MDIO_START | MDIO_BUSY))) val 384 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c u32 val; val 391 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c val = AT_READ_REG(hw, REG_MDIO_CTRL); val 392 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c if (!(val & (MDIO_START | MDIO_BUSY))) val 396 drivers/net/ethernet/atheros/atl1e/atl1e_hw.c if (0 != (val & (MDIO_START | MDIO_BUSY))) { val 459 drivers/net/ethernet/atheros/atl1e/atl1e_main.c int reg_num, int val) val 464 drivers/net/ethernet/atheros/atl1e/atl1e_main.c reg_num & MDIO_REG_ADDR_MASK, val)) val 1933 drivers/net/ethernet/atheros/atl1e/atl1e_main.c u32 val; val 1953 drivers/net/ethernet/atheros/atl1e/atl1e_main.c val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL); val 1955 drivers/net/ethernet/atheros/atl1e/atl1e_main.c val | MASTER_CTRL_MANUAL_INT); val 189 drivers/net/ethernet/atheros/atl1e/atl1e_param.c int val; val 191 drivers/net/ethernet/atheros/atl1e/atl1e_param.c val = tx_desc_cnt[bd]; val 192 drivers/net/ethernet/atheros/atl1e/atl1e_param.c atl1e_validate_option(&val, &opt, adapter); val 193 drivers/net/ethernet/atheros/atl1e/atl1e_param.c adapter->tx_ring.count = (u16) val & 0xFFFC; val 208 drivers/net/ethernet/atheros/atl1e/atl1e_param.c int val; val 210 drivers/net/ethernet/atheros/atl1e/atl1e_param.c val = rx_mem_size[bd]; val 211 drivers/net/ethernet/atheros/atl1e/atl1e_param.c atl1e_validate_option(&val, &opt, adapter); val 212 drivers/net/ethernet/atheros/atl1e/atl1e_param.c adapter->rx_ring.page_size = (u32)val * 1024; val 228 drivers/net/ethernet/atheros/atl1e/atl1e_param.c int val; val 230 drivers/net/ethernet/atheros/atl1e/atl1e_param.c val = int_mod_timer[bd]; val 231 drivers/net/ethernet/atheros/atl1e/atl1e_param.c atl1e_validate_option(&val, &opt, adapter); val 232 drivers/net/ethernet/atheros/atl1e/atl1e_param.c adapter->hw.imt = (u16) val; val 247 drivers/net/ethernet/atheros/atl1e/atl1e_param.c int val; val 249 drivers/net/ethernet/atheros/atl1e/atl1e_param.c val = media_type[bd]; val 250 drivers/net/ethernet/atheros/atl1e/atl1e_param.c atl1e_validate_option(&val, &opt, adapter); val 251 drivers/net/ethernet/atheros/atl1e/atl1e_param.c adapter->hw.media_type = (u16) val; val 208 drivers/net/ethernet/atheros/atlx/atl1.c int val; val 210 drivers/net/ethernet/atheros/atlx/atl1.c val = int_mod_timer[bd]; val 211 drivers/net/ethernet/atheros/atlx/atl1.c atl1_validate_option(&val, &opt, pdev); val 212 drivers/net/ethernet/atheros/atlx/atl1.c adapter->imt = (u16) val; val 344 drivers/net/ethernet/atheros/atlx/atl1.c u32 val; val 347 drivers/net/ethernet/atheros/atlx/atl1.c val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | val 350 drivers/net/ethernet/atheros/atlx/atl1.c iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); val 355 drivers/net/ethernet/atheros/atlx/atl1.c val = ioread32(hw->hw_addr + REG_MDIO_CTRL); val 356 drivers/net/ethernet/atheros/atlx/atl1.c if (!(val & (MDIO_START | MDIO_BUSY))) val 359 drivers/net/ethernet/atheros/atlx/atl1.c if (!(val & (MDIO_START | MDIO_BUSY))) { val 360 drivers/net/ethernet/atheros/atlx/atl1.c *phy_data = (u16) val; val 592 drivers/net/ethernet/atheros/atlx/atl1.c u32 val; val 594 drivers/net/ethernet/atheros/atlx/atl1.c val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | val 598 drivers/net/ethernet/atheros/atlx/atl1.c iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); val 603 drivers/net/ethernet/atheros/atlx/atl1.c val = ioread32(hw->hw_addr + REG_MDIO_CTRL); val 604 drivers/net/ethernet/atheros/atlx/atl1.c if (!(val & (MDIO_START | MDIO_BUSY))) val 608 drivers/net/ethernet/atheros/atlx/atl1.c if (!(val & (MDIO_START | MDIO_BUSY))) val 668 drivers/net/ethernet/atheros/atlx/atl1.c u32 val; val 676 drivers/net/ethernet/atheros/atlx/atl1.c val = ioread32(hw->hw_addr + REG_MDIO_CTRL); val 677 drivers/net/ethernet/atheros/atlx/atl1.c if (!(val & (MDIO_START | MDIO_BUSY))) val 681 drivers/net/ethernet/atheros/atlx/atl1.c if ((val & (MDIO_START | MDIO_BUSY)) != 0) { val 992 drivers/net/ethernet/atheros/atlx/atl1.c int val) val 996 drivers/net/ethernet/atheros/atlx/atl1.c atl1_write_phy_reg(&adapter->hw, reg_num, val); val 2294 drivers/net/ethernet/atheros/atlx/atl1.c u32 val; val 2311 drivers/net/ethernet/atheros/atlx/atl1.c val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & val 2313 drivers/net/ethernet/atheros/atlx/atl1.c if (val) { val 2761 drivers/net/ethernet/atheros/atlx/atl1.c u32 val; val 2771 drivers/net/ethernet/atheros/atlx/atl1.c val = ctrl & BMSR_LSTATUS; val 2772 drivers/net/ethernet/atheros/atlx/atl1.c if (val) val 2777 drivers/net/ethernet/atheros/atlx/atl1.c if (val) { val 2778 drivers/net/ethernet/atheros/atlx/atl1.c val = atl1_get_speed_and_duplex(hw, &speed, &duplex); val 2779 drivers/net/ethernet/atheros/atlx/atl1.c if (val) { val 692 drivers/net/ethernet/atheros/atlx/atl2.c u32 val; val 728 drivers/net/ethernet/atheros/atlx/atl2.c val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); val 730 drivers/net/ethernet/atheros/atlx/atl2.c val | MASTER_CTRL_MANUAL_INT); val 1060 drivers/net/ethernet/atheros/atlx/atl2.c u32 val; val 1082 drivers/net/ethernet/atheros/atlx/atl2.c val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); val 1083 drivers/net/ethernet/atheros/atlx/atl2.c ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | val 2493 drivers/net/ethernet/atheros/atlx/atl2.c u32 val; val 2496 drivers/net/ethernet/atheros/atlx/atl2.c val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | val 2501 drivers/net/ethernet/atheros/atlx/atl2.c ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); val 2507 drivers/net/ethernet/atheros/atlx/atl2.c val = ATL2_READ_REG(hw, REG_MDIO_CTRL); val 2508 drivers/net/ethernet/atheros/atlx/atl2.c if (!(val & (MDIO_START | MDIO_BUSY))) val 2512 drivers/net/ethernet/atheros/atlx/atl2.c if (!(val & (MDIO_START | MDIO_BUSY))) { val 2513 drivers/net/ethernet/atheros/atlx/atl2.c *phy_data = (u16)val; val 2529 drivers/net/ethernet/atheros/atlx/atl2.c u32 val; val 2531 drivers/net/ethernet/atheros/atlx/atl2.c val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | val 2536 drivers/net/ethernet/atheros/atlx/atl2.c ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); val 2542 drivers/net/ethernet/atheros/atlx/atl2.c val = ATL2_READ_REG(hw, REG_MDIO_CTRL); val 2543 drivers/net/ethernet/atheros/atlx/atl2.c if (!(val & (MDIO_START | MDIO_BUSY))) val 2549 drivers/net/ethernet/atheros/atlx/atl2.c if (!(val & (MDIO_START | MDIO_BUSY))) val 2641 drivers/net/ethernet/atheros/atlx/atl2.c u32 val; val 2646 drivers/net/ethernet/atheros/atlx/atl2.c val = ATL2_READ_REG(hw, REG_MDIO_CTRL); val 2647 drivers/net/ethernet/atheros/atlx/atl2.c if (!(val & (MDIO_START | MDIO_BUSY))) val 2651 drivers/net/ethernet/atheros/atlx/atl2.c if (0 != (val & (MDIO_START | MDIO_BUSY))) { val 2957 drivers/net/ethernet/atheros/atlx/atl2.c int val; val 2979 drivers/net/ethernet/atheros/atlx/atl2.c val = TxMemSize[bd]; val 2980 drivers/net/ethernet/atheros/atlx/atl2.c atl2_validate_option(&val, &opt); val 2981 drivers/net/ethernet/atheros/atlx/atl2.c adapter->txd_ring_size = ((u32) val) * 1024; val 3001 drivers/net/ethernet/atheros/atlx/atl2.c val = RxMemBlock[bd]; val 3002 drivers/net/ethernet/atheros/atlx/atl2.c atl2_validate_option(&val, &opt); val 3003 drivers/net/ethernet/atheros/atlx/atl2.c adapter->rxd_ring_size = (u32)val; val 3026 drivers/net/ethernet/atheros/atlx/atl2.c val = IntModTimer[bd]; val 3027 drivers/net/ethernet/atheros/atlx/atl2.c atl2_validate_option(&val, &opt); val 3028 drivers/net/ethernet/atheros/atlx/atl2.c adapter->imt = (u16) val; val 3043 drivers/net/ethernet/atheros/atlx/atl2.c val = FlashVendor[bd]; val 3044 drivers/net/ethernet/atheros/atlx/atl2.c atl2_validate_option(&val, &opt); val 3045 drivers/net/ethernet/atheros/atlx/atl2.c adapter->hw.flash_vendor = (u8) val; val 3060 drivers/net/ethernet/atheros/atlx/atl2.c val = MediaType[bd]; val 3061 drivers/net/ethernet/atheros/atlx/atl2.c atl2_validate_option(&val, &opt); val 3062 drivers/net/ethernet/atheros/atlx/atl2.c adapter->hw.MediaType = (u16) val; val 45 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_writeb(struct nb8800_priv *priv, int reg, u8 val) val 47 drivers/net/ethernet/aurora/nb8800.c writeb_relaxed(val, priv->base + reg); val 50 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_writew(struct nb8800_priv *priv, int reg, u16 val) val 52 drivers/net/ethernet/aurora/nb8800.c writew_relaxed(val, priv->base + reg); val 55 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_writel(struct nb8800_priv *priv, int reg, u32 val) val 57 drivers/net/ethernet/aurora/nb8800.c writel_relaxed(val, priv->base + reg); val 61 drivers/net/ethernet/aurora/nb8800.c u32 mask, u32 val) val 64 drivers/net/ethernet/aurora/nb8800.c u32 new = (old & ~mask) | (val & mask); val 71 drivers/net/ethernet/aurora/nb8800.c u32 mask, u32 val) val 74 drivers/net/ethernet/aurora/nb8800.c u32 new = (old & ~mask) | (val & mask); val 115 drivers/net/ethernet/aurora/nb8800.c u32 val; val 118 drivers/net/ethernet/aurora/nb8800.c val, !(val & MDIO_CMD_GO), 1, 1000); val 140 drivers/net/ethernet/aurora/nb8800.c u32 val; val 147 drivers/net/ethernet/aurora/nb8800.c val = nb8800_readl(priv, NB8800_MDIO_STS); val 148 drivers/net/ethernet/aurora/nb8800.c if (val & MDIO_STS_ERR) val 151 drivers/net/ethernet/aurora/nb8800.c return val & 0xffff; val 154 drivers/net/ethernet/aurora/nb8800.c static int nb8800_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) val 157 drivers/net/ethernet/aurora/nb8800.c MDIO_CMD_DATA(val) | MDIO_CMD_WR; val 542 drivers/net/ethernet/aurora/nb8800.c u32 val; val 545 drivers/net/ethernet/aurora/nb8800.c val = nb8800_readl(priv, NB8800_TXC_SR); val 546 drivers/net/ethernet/aurora/nb8800.c if (val) { val 547 drivers/net/ethernet/aurora/nb8800.c nb8800_writel(priv, NB8800_TXC_SR, val); val 549 drivers/net/ethernet/aurora/nb8800.c if (val & TSR_DI) val 552 drivers/net/ethernet/aurora/nb8800.c if (val & TSR_TI) val 555 drivers/net/ethernet/aurora/nb8800.c if (unlikely(val & TSR_DE)) val 559 drivers/net/ethernet/aurora/nb8800.c if (unlikely(val & TSR_TO)) val 566 drivers/net/ethernet/aurora/nb8800.c val = nb8800_readl(priv, NB8800_RXC_SR); val 567 drivers/net/ethernet/aurora/nb8800.c if (val) { val 568 drivers/net/ethernet/aurora/nb8800.c nb8800_writel(priv, NB8800_RXC_SR, val); val 570 drivers/net/ethernet/aurora/nb8800.c if (likely(val & (RSR_RI | RSR_DI))) { val 575 drivers/net/ethernet/aurora/nb8800.c if (unlikely(val & RSR_DE)) val 579 drivers/net/ethernet/aurora/nb8800.c if (unlikely(val & RSR_RO)) val 712 drivers/net/ethernet/aurora/nb8800.c static void nb8800_mc_init(struct net_device *dev, int val) val 716 drivers/net/ethernet/aurora/nb8800.c nb8800_writeb(priv, NB8800_MC_INIT, val); val 717 drivers/net/ethernet/aurora/nb8800.c readb_poll_timeout_atomic(priv->base + NB8800_MC_INIT, val, !val, val 1155 drivers/net/ethernet/aurora/nb8800.c u32 val; val 1157 drivers/net/ethernet/aurora/nb8800.c val = TX_RETRY_EN | TX_PAD_EN | TX_APPEND_FCS; val 1158 drivers/net/ethernet/aurora/nb8800.c nb8800_writeb(priv, NB8800_TX_CTL1, val); val 1163 drivers/net/ethernet/aurora/nb8800.c val = RX_PAD_STRIP | RX_AF_EN; val 1164 drivers/net/ethernet/aurora/nb8800.c nb8800_writeb(priv, NB8800_RX_CTL, val); val 1187 drivers/net/ethernet/aurora/nb8800.c val = nb8800_readl(priv, NB8800_TXC_CR); val 1188 drivers/net/ethernet/aurora/nb8800.c val &= TCR_LE; /* keep endian setting */ val 1189 drivers/net/ethernet/aurora/nb8800.c val |= TCR_DM; /* DMA descriptor mode */ val 1190 drivers/net/ethernet/aurora/nb8800.c val |= TCR_RS; /* automatically store tx status */ val 1191 drivers/net/ethernet/aurora/nb8800.c val |= TCR_DIE; /* interrupt on DMA chain completion */ val 1192 drivers/net/ethernet/aurora/nb8800.c val |= TCR_TFI(7); /* interrupt after 7 frames transmitted */ val 1193 drivers/net/ethernet/aurora/nb8800.c val |= TCR_BTS(2); /* 32-byte bus transaction size */ val 1194 drivers/net/ethernet/aurora/nb8800.c nb8800_writel(priv, NB8800_TXC_CR, val); val 1197 drivers/net/ethernet/aurora/nb8800.c val = clk_get_rate(priv->clk) / 100; val 1198 drivers/net/ethernet/aurora/nb8800.c nb8800_writel(priv, NB8800_TX_ITR, val); val 1202 drivers/net/ethernet/aurora/nb8800.c val = nb8800_readl(priv, NB8800_RXC_CR); val 1203 drivers/net/ethernet/aurora/nb8800.c val &= RCR_LE; /* keep endian setting */ val 1204 drivers/net/ethernet/aurora/nb8800.c val |= RCR_DM; /* DMA descriptor mode */ val 1205 drivers/net/ethernet/aurora/nb8800.c val |= RCR_RS; /* automatically store rx status */ val 1206 drivers/net/ethernet/aurora/nb8800.c val |= RCR_DIE; /* interrupt at end of DMA chain */ val 1207 drivers/net/ethernet/aurora/nb8800.c val |= RCR_RFI(7); /* interrupt after 7 frames received */ val 1208 drivers/net/ethernet/aurora/nb8800.c val |= RCR_BTS(2); /* 32-byte bus transaction size */ val 1209 drivers/net/ethernet/aurora/nb8800.c nb8800_writel(priv, NB8800_RXC_CR, val); val 1228 drivers/net/ethernet/aurora/nb8800.c val = 100000 / 512; val 1229 drivers/net/ethernet/aurora/nb8800.c nb8800_writeb(priv, NB8800_PQ1, val >> 8); val 1230 drivers/net/ethernet/aurora/nb8800.c nb8800_writeb(priv, NB8800_PQ2, val & 0xff); val 172 drivers/net/ethernet/broadcom/b44.c unsigned long reg, unsigned long val) val 174 drivers/net/ethernet/broadcom/b44.c ssb_write32(bp->sdev, reg, val); val 183 drivers/net/ethernet/broadcom/b44.c u32 val = br32(bp, reg); val 185 drivers/net/ethernet/broadcom/b44.c if (clear && !(val & bit)) val 187 drivers/net/ethernet/broadcom/b44.c if (!clear && (val & bit)) val 203 drivers/net/ethernet/broadcom/b44.c u32 val; val 210 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_CAM_DATA_LO); val 212 drivers/net/ethernet/broadcom/b44.c data[2] = (val >> 24) & 0xFF; val 213 drivers/net/ethernet/broadcom/b44.c data[3] = (val >> 16) & 0xFF; val 214 drivers/net/ethernet/broadcom/b44.c data[4] = (val >> 8) & 0xFF; val 215 drivers/net/ethernet/broadcom/b44.c data[5] = (val >> 0) & 0xFF; val 217 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_CAM_DATA_HI); val 219 drivers/net/ethernet/broadcom/b44.c data[0] = (val >> 8) & 0xFF; val 220 drivers/net/ethernet/broadcom/b44.c data[1] = (val >> 0) & 0xFF; val 225 drivers/net/ethernet/broadcom/b44.c u32 val; val 227 drivers/net/ethernet/broadcom/b44.c val = ((u32) data[2]) << 24; val 228 drivers/net/ethernet/broadcom/b44.c val |= ((u32) data[3]) << 16; val 229 drivers/net/ethernet/broadcom/b44.c val |= ((u32) data[4]) << 8; val 230 drivers/net/ethernet/broadcom/b44.c val |= ((u32) data[5]) << 0; val 231 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_CAM_DATA_LO, val); val 232 drivers/net/ethernet/broadcom/b44.c val = (CAM_DATA_HI_VALID | val 235 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_CAM_DATA_HI, val); val 259 drivers/net/ethernet/broadcom/b44.c static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val) val 270 drivers/net/ethernet/broadcom/b44.c *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA; val 275 drivers/net/ethernet/broadcom/b44.c static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val) val 283 drivers/net/ethernet/broadcom/b44.c (val & MDIO_DATA_DATA))); val 287 drivers/net/ethernet/broadcom/b44.c static inline int b44_readphy(struct b44 *bp, int reg, u32 *val) val 292 drivers/net/ethernet/broadcom/b44.c return __b44_readphy(bp, bp->phy_addr, reg, val); val 295 drivers/net/ethernet/broadcom/b44.c static inline int b44_writephy(struct b44 *bp, int reg, u32 val) val 300 drivers/net/ethernet/broadcom/b44.c return __b44_writephy(bp, bp->phy_addr, reg, val); val 306 drivers/net/ethernet/broadcom/b44.c u32 val; val 308 drivers/net/ethernet/broadcom/b44.c int rc = __b44_readphy(bp, phy_id, location, &val); val 311 drivers/net/ethernet/broadcom/b44.c return val; val 315 drivers/net/ethernet/broadcom/b44.c int val) val 318 drivers/net/ethernet/broadcom/b44.c __b44_writephy(bp, phy_id, location, val); val 323 drivers/net/ethernet/broadcom/b44.c u32 val; val 325 drivers/net/ethernet/broadcom/b44.c int rc = __b44_readphy(bp, phy_id, location, &val); val 328 drivers/net/ethernet/broadcom/b44.c return val; val 332 drivers/net/ethernet/broadcom/b44.c u16 val) val 335 drivers/net/ethernet/broadcom/b44.c return __b44_writephy(bp, phy_id, location, val); val 340 drivers/net/ethernet/broadcom/b44.c u32 val; val 349 drivers/net/ethernet/broadcom/b44.c err = b44_readphy(bp, MII_BMCR, &val); val 351 drivers/net/ethernet/broadcom/b44.c if (val & BMCR_RESET) { val 362 drivers/net/ethernet/broadcom/b44.c u32 val; val 367 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_RXCONFIG); val 369 drivers/net/ethernet/broadcom/b44.c val |= RXCONFIG_FLOW; val 371 drivers/net/ethernet/broadcom/b44.c val &= ~RXCONFIG_FLOW; val 372 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_RXCONFIG, val); val 374 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_MAC_FLOW); val 376 drivers/net/ethernet/broadcom/b44.c val |= (MAC_FLOW_PAUSE_ENAB | val 379 drivers/net/ethernet/broadcom/b44.c val &= ~MAC_FLOW_PAUSE_ENAB; val 380 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_MAC_FLOW, val); val 407 drivers/net/ethernet/broadcom/b44.c u32 val; val 418 drivers/net/ethernet/broadcom/b44.c err = __b44_readphy(bp, 0, MII_BMCR, &val); val 421 drivers/net/ethernet/broadcom/b44.c if (!(val & BMCR_ISOLATE)) val 423 drivers/net/ethernet/broadcom/b44.c val &= ~BMCR_ISOLATE; val 424 drivers/net/ethernet/broadcom/b44.c err = __b44_writephy(bp, 0, MII_BMCR, val); val 440 drivers/net/ethernet/broadcom/b44.c u32 val; val 447 drivers/net/ethernet/broadcom/b44.c if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0) val 450 drivers/net/ethernet/broadcom/b44.c val & MII_ALEDCTRL_ALLMSK)) != 0) val 452 drivers/net/ethernet/broadcom/b44.c if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0) val 455 drivers/net/ethernet/broadcom/b44.c val | MII_TLEDCTRL_ENABLE)) != 0) val 505 drivers/net/ethernet/broadcom/b44.c u64 *val; val 507 drivers/net/ethernet/broadcom/b44.c val = &bp->hw_stats.tx_good_octets; val 511 drivers/net/ethernet/broadcom/b44.c *val++ += br32(bp, reg); val 518 drivers/net/ethernet/broadcom/b44.c *val++ += br32(bp, reg); val 546 drivers/net/ethernet/broadcom/b44.c u32 val = br32(bp, B44_TX_CTRL); val 548 drivers/net/ethernet/broadcom/b44.c val |= TX_CTRL_DUPLEX; val 550 drivers/net/ethernet/broadcom/b44.c val &= ~TX_CTRL_DUPLEX; val 551 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_TX_CTRL, val); val 572 drivers/net/ethernet/broadcom/b44.c u32 val = br32(bp, B44_TX_CTRL); val 576 drivers/net/ethernet/broadcom/b44.c val |= TX_CTRL_DUPLEX; val 578 drivers/net/ethernet/broadcom/b44.c val &= ~TX_CTRL_DUPLEX; val 579 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_TX_CTRL, val); val 1338 drivers/net/ethernet/broadcom/b44.c u32 val = br32(bp, B44_DEVCTRL); val 1340 drivers/net/ethernet/broadcom/b44.c if (val & DEVCTRL_EPR) { val 1341 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR)); val 1371 drivers/net/ethernet/broadcom/b44.c u32 val; val 1374 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_CAM_CTRL); val 1375 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE); val 1383 drivers/net/ethernet/broadcom/b44.c u32 val; val 1395 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_RXCONFIG); val 1396 drivers/net/ethernet/broadcom/b44.c if (!(val & RXCONFIG_CAM_ABSENT)) val 1410 drivers/net/ethernet/broadcom/b44.c u32 val; val 1446 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_ENET_CTRL); val 1447 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE)); val 1550 drivers/net/ethernet/broadcom/b44.c u32 val; val 1592 drivers/net/ethernet/broadcom/b44.c val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE; val 1593 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_WKUP_LEN, val); val 1596 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_DEVCTRL); val 1597 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE); val 1604 drivers/net/ethernet/broadcom/b44.c u16 val; val 1608 drivers/net/ethernet/broadcom/b44.c pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val); val 1609 drivers/net/ethernet/broadcom/b44.c pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE); val 1618 drivers/net/ethernet/broadcom/b44.c u32 val; val 1626 drivers/net/ethernet/broadcom/b44.c val = bp->dev->dev_addr[2] << 24 | val 1630 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_ADDR_LO, val); val 1632 drivers/net/ethernet/broadcom/b44.c val = bp->dev->dev_addr[0] << 8 | val 1634 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_ADDR_HI, val); val 1636 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_DEVCTRL); val 1637 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE); val 1742 drivers/net/ethernet/broadcom/b44.c u32 val; val 1744 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_RXCONFIG); val 1745 drivers/net/ethernet/broadcom/b44.c val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI); val 1746 drivers/net/ethernet/broadcom/b44.c if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) { val 1747 drivers/net/ethernet/broadcom/b44.c val |= RXCONFIG_PROMISC; val 1748 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_RXCONFIG, val); val 1757 drivers/net/ethernet/broadcom/b44.c val |= RXCONFIG_ALLMULTI; val 1764 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_RXCONFIG, val); val 1765 drivers/net/ethernet/broadcom/b44.c val = br32(bp, B44_CAM_CTRL); val 1766 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE); val 2242 drivers/net/ethernet/broadcom/b44.c u32 val = br32(bp, B44_TX_CTRL); val 2244 drivers/net/ethernet/broadcom/b44.c val |= TX_CTRL_DUPLEX; val 2246 drivers/net/ethernet/broadcom/b44.c val &= ~TX_CTRL_DUPLEX; val 2247 drivers/net/ethernet/broadcom/b44.c bw32(bp, B44_TX_CTRL, val); val 43 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val, u32 off) val 45 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writel(val, priv->base + off); val 57 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val, u32 off) val 59 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writel(val, priv->base + off); val 68 drivers/net/ethernet/broadcom/bcm63xx_enet.c u16 val, u32 off) val 70 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writew(val, priv->base + off); val 79 drivers/net/ethernet/broadcom/bcm63xx_enet.c u8 val, u32 off) val 81 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writeb(val, priv->base + off); val 92 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val, u32 off) val 94 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writel(val, bcm_enet_shared_base[0] + off); val 104 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val, u32 off, int chan) val 106 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writel(val, bcm_enet_shared_base[1] + val 116 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val, u32 off, int chan) val 118 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width); val 152 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 tmp, val; val 162 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_MIIDATA_REG); val 163 drivers/net/ethernet/broadcom/bcm63xx_enet.c val &= 0xffff; val 164 drivers/net/ethernet/broadcom/bcm63xx_enet.c return val; val 650 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 656 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | val 658 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_PML_REG(0)); val 660 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]); val 661 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_PMH_DATAVALID_MASK; val 662 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_PMH_REG(0)); val 674 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 679 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_RXCFG_REG); val 682 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_RXCFG_PROMISC_MASK; val 684 drivers/net/ethernet/broadcom/bcm63xx_enet.c val &= ~ENET_RXCFG_PROMISC_MASK; val 689 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_RXCFG_ALLMCAST_MASK; val 691 drivers/net/ethernet/broadcom/bcm63xx_enet.c val &= ~ENET_RXCFG_ALLMCAST_MASK; val 695 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (val & ENET_RXCFG_ALLMCAST_MASK) { val 696 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_RXCFG_REG); val 723 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_RXCFG_REG); val 731 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 733 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_TXCTL_REG); val 735 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_TXCTL_FD_MASK; val 737 drivers/net/ethernet/broadcom/bcm63xx_enet.c val &= ~ENET_TXCTL_FD_MASK; val 738 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_TXCTL_REG); val 746 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 749 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_RXCFG_REG); val 751 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_RXCFG_ENFLOW_MASK; val 753 drivers/net/ethernet/broadcom/bcm63xx_enet.c val &= ~ENET_RXCFG_ENFLOW_MASK; val 754 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_RXCFG_REG); val 760 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_dma_readl(priv, ENETDMA_CFG_REG); val 762 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); val 764 drivers/net/ethernet/broadcom/bcm63xx_enet.c val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); val 765 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_dma_writel(priv, val, ENETDMA_CFG_REG); val 862 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 1025 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = priv->rx_ring_size / 3; val 1026 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); val 1027 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = (priv->rx_ring_size * 2) / 3; val 1028 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); val 1038 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_CTL_REG); val 1039 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_CTL_ENABLE_MASK; val 1040 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_CTL_REG); val 1119 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 1121 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_CTL_REG); val 1122 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_CTL_DISABLE_MASK; val 1123 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_CTL_REG); val 1127 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 1129 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_CTL_REG); val 1130 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (!(val & ENET_CTL_DISABLE_MASK)) val 1147 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 1149 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan); val 1150 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (!(val & ENETDMAC_CHANCFG_EN_MASK)) val 1346 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 1353 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_MIB_REG(s->mib_reg)); val 1357 drivers/net/ethernet/broadcom/bcm63xx_enet.c *(u64 *)p += val; val 1359 drivers/net/ethernet/broadcom/bcm63xx_enet.c *(u32 *)p += val; val 1641 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 1648 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = ENET_CTL_SRESET_MASK; val 1649 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_CTL_REG); val 1654 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_CTL_REG); val 1655 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (!(val & ENET_CTL_SRESET_MASK)) val 1661 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_CTL_REG); val 1663 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_CTL_EPHYSEL_MASK; val 1665 drivers/net/ethernet/broadcom/bcm63xx_enet.c val &= ~ENET_CTL_EPHYSEL_MASK; val 1666 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_CTL_REG); val 1673 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enet_readl(priv, ENET_MIBCTL_REG); val 1674 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENET_MIBCTL_RDCLEAR_MASK; val 1675 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_writel(priv, val, ENET_MIBCTL_REG); val 1988 drivers/net/ethernet/broadcom/bcm63xx_enet.c int val, j, up, advertise, lpa, speed, duplex, media; val 2001 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = bcmenet_sw_mdio_read(priv, external_phy, val 2004 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (val == 0xffff) val 2007 drivers/net/ethernet/broadcom/bcm63xx_enet.c up = (val & BMSR_LSTATUS) ? 1 : 0; val 2040 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (val & BMSR_ESTATEN) { val 2086 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 val; val 2169 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enetsw_readb(priv, ENETSW_GMCR_REG); val 2170 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENETSW_GMCR_RST_MIB_MASK; val 2171 drivers/net/ethernet/broadcom/bcm63xx_enet.c enetsw_writeb(priv, val, ENETSW_GMCR_REG); val 2173 drivers/net/ethernet/broadcom/bcm63xx_enet.c val &= ~ENETSW_GMCR_RST_MIB_MASK; val 2174 drivers/net/ethernet/broadcom/bcm63xx_enet.c enetsw_writeb(priv, val, ENETSW_GMCR_REG); val 2178 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enetsw_readb(priv, ENETSW_IMPOV_REG); val 2179 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; val 2180 drivers/net/ethernet/broadcom/bcm63xx_enet.c enetsw_writeb(priv, val, ENETSW_IMPOV_REG); val 2183 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = enetsw_readb(priv, ENETSW_SWMODE_REG); val 2184 drivers/net/ethernet/broadcom/bcm63xx_enet.c val |= ENETSW_SWMODE_FWD_EN_MASK; val 2185 drivers/net/ethernet/broadcom/bcm63xx_enet.c enetsw_writeb(priv, val, ENETSW_SWMODE_REG); val 2222 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = priv->rx_ring_size / 3; val 2223 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); val 2224 drivers/net/ethernet/broadcom/bcm63xx_enet.c val = (priv->rx_ring_size * 2) / 3; val 2225 drivers/net/ethernet/broadcom/bcm63xx_enet.c enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); val 2423 drivers/net/ethernet/broadcom/bcm63xx_enet.c int val) val 2429 drivers/net/ethernet/broadcom/bcm63xx_enet.c phy_id, location, val); val 36 drivers/net/ethernet/broadcom/bcmsysport.c u32 val, u32 off) \ val 38 drivers/net/ethernet/broadcom/bcmsysport.c writel_relaxed(val, priv->base + offset + off); \ val 62 drivers/net/ethernet/broadcom/bcmsysport.c static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off) val 66 drivers/net/ethernet/broadcom/bcmsysport.c writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off); val 389 drivers/net/ethernet/broadcom/bcmsysport.c u32 val = 0; val 406 drivers/net/ethernet/broadcom/bcmsysport.c val = umac_readl(priv, UMAC_MIB_START + j + offset); val 409 drivers/net/ethernet/broadcom/bcmsysport.c val = rxchk_readl(priv, s->reg_offset); val 410 drivers/net/ethernet/broadcom/bcmsysport.c if (val == ~0) val 414 drivers/net/ethernet/broadcom/bcmsysport.c val = rbuf_readl(priv, s->reg_offset); val 415 drivers/net/ethernet/broadcom/bcmsysport.c if (val == ~0) val 422 drivers/net/ethernet/broadcom/bcmsysport.c *(u32 *)p = val; val 18 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c u32 val; val 22 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c val = bcma_read32(core, reg); val 23 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c if ((val & mask) == value) val 70 drivers/net/ethernet/broadcom/bgmac-platform.c u32 val; val 79 drivers/net/ethernet/broadcom/bgmac-platform.c val = bgmac_idm_read(bgmac, BCMA_RESET_CTL); val 80 drivers/net/ethernet/broadcom/bgmac-platform.c if (val) { val 86 drivers/net/ethernet/broadcom/bgmac-platform.c val = bgmac_idm_read(bgmac, BCMA_IOCTL); val 88 drivers/net/ethernet/broadcom/bgmac-platform.c val |= flags & ~(BGMAC_AWCACHE | BGMAC_ARCACHE | BGMAC_AWUSER | val 90 drivers/net/ethernet/broadcom/bgmac-platform.c val |= BGMAC_CLK_EN; val 91 drivers/net/ethernet/broadcom/bgmac-platform.c bgmac_idm_write(bgmac, BCMA_IOCTL, val); val 121 drivers/net/ethernet/broadcom/bgmac-platform.c u32 val; val 130 drivers/net/ethernet/broadcom/bgmac-platform.c val = NICPM_IOMUX_CTRL_INIT_VAL; val 136 drivers/net/ethernet/broadcom/bgmac-platform.c val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT; val 139 drivers/net/ethernet/broadcom/bgmac-platform.c val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT; val 142 drivers/net/ethernet/broadcom/bgmac-platform.c val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT; val 146 drivers/net/ethernet/broadcom/bgmac-platform.c writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL); val 24 drivers/net/ethernet/broadcom/bgmac.c u32 val; val 28 drivers/net/ethernet/broadcom/bgmac.c val = bgmac_read(bgmac, reg); val 29 drivers/net/ethernet/broadcom/bgmac.c if ((val & mask) == value) val 43 drivers/net/ethernet/broadcom/bgmac.c u32 val; val 56 drivers/net/ethernet/broadcom/bgmac.c val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); val 57 drivers/net/ethernet/broadcom/bgmac.c val &= BGMAC_DMA_TX_STAT; val 58 drivers/net/ethernet/broadcom/bgmac.c if (val == BGMAC_DMA_TX_STAT_DISABLED || val 59 drivers/net/ethernet/broadcom/bgmac.c val == BGMAC_DMA_TX_STAT_IDLEWAIT || val 60 drivers/net/ethernet/broadcom/bgmac.c val == BGMAC_DMA_TX_STAT_STOPPED) { val 68 drivers/net/ethernet/broadcom/bgmac.c ring->mmio_base, val); val 79 drivers/net/ethernet/broadcom/bgmac.c val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); val 80 drivers/net/ethernet/broadcom/bgmac.c if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) val 1379 drivers/net/ethernet/broadcom/bgmac.c u64 val; val 1386 drivers/net/ethernet/broadcom/bgmac.c val = 0; val 1388 drivers/net/ethernet/broadcom/bgmac.c val = (u64)bgmac_read(bgmac, s->offset + 4) << 32; val 1389 drivers/net/ethernet/broadcom/bgmac.c val |= bgmac_read(bgmac, s->offset); val 1390 drivers/net/ethernet/broadcom/bgmac.c data[i] = val; val 273 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 277 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW); val 279 drivers/net/ethernet/broadcom/bnx2.c return val; val 283 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) val 289 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val); val 294 drivers/net/ethernet/broadcom/bnx2.c bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) val 296 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); val 306 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) val 315 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_CTX_CTX_DATA, val); val 319 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL); val 320 drivers/net/ethernet/broadcom/bnx2.c if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) val 326 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_CTX_DATA, val); val 493 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) val 528 drivers/net/ethernet/broadcom/bnx2.c *val = 0x0; val 532 drivers/net/ethernet/broadcom/bnx2.c *val = val1; val 550 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) val 565 drivers/net/ethernet/broadcom/bnx2.c val1 = (bp->phy_addr << 21) | (reg << 16) | val | val 1057 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 1059 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); val 1060 drivers/net/ethernet/broadcom/bnx2.c if (val & BCM5708S_1000X_STAT1_TX_PAUSE) val 1062 drivers/net/ethernet/broadcom/bnx2.c if (val & BCM5708S_1000X_STAT1_RX_PAUSE) val 1115 drivers/net/ethernet/broadcom/bnx2.c u32 val, speed; val 1120 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); val 1128 drivers/net/ethernet/broadcom/bnx2.c speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; val 1144 drivers/net/ethernet/broadcom/bnx2.c if (val & MII_BNX2_GP_TOP_AN_FD) val 1154 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 1157 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); val 1158 drivers/net/ethernet/broadcom/bnx2.c switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { val 1172 drivers/net/ethernet/broadcom/bnx2.c if (val & BCM5708S_1000X_STAT1_FD) val 1296 drivers/net/ethernet/broadcom/bnx2.c u32 val, rx_cid_addr = GET_CID_ADDR(cid); val 1298 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; val 1299 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; val 1300 drivers/net/ethernet/broadcom/bnx2.c val |= 0x02 << 8; val 1303 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_L2CTX_FLOW_CTRL_ENABLE; val 1305 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); val 1324 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 1333 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_EMAC_MODE); val 1335 drivers/net/ethernet/broadcom/bnx2.c val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | val 1343 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_PORT_MII_10M; val 1348 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_PORT_MII; val 1351 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_25G_MODE; val 1354 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_PORT_GMII; val 1359 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_PORT_GMII; val 1364 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_HALF_DUPLEX; val 1365 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_EMAC_MODE, val); val 1375 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_EMAC_TX_MODE); val 1376 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; val 1379 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_TX_MODE_FLOW_EN; val 1380 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_EMAC_TX_MODE, val); val 1471 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 1475 drivers/net/ethernet/broadcom/bnx2.c if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { val 1476 drivers/net/ethernet/broadcom/bnx2.c val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; val 1477 drivers/net/ethernet/broadcom/bnx2.c val |= MII_BNX2_SD_MISC1_FORCE | val 1479 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); val 1515 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 1519 drivers/net/ethernet/broadcom/bnx2.c if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { val 1520 drivers/net/ethernet/broadcom/bnx2.c val &= ~MII_BNX2_SD_MISC1_FORCE; val 1521 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); val 1547 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 1550 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); val 1552 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); val 1554 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); val 1580 drivers/net/ethernet/broadcom/bnx2.c u32 val, an_dbg; val 1586 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_EMAC_STATUS); val 1592 drivers/net/ethernet/broadcom/bnx2.c if ((val & BNX2_EMAC_STATUS_LINK) && val 2189 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2207 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); val 2208 drivers/net/ethernet/broadcom/bnx2.c val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; val 2209 drivers/net/ethernet/broadcom/bnx2.c val |= MII_BNX2_SD_1000XCTL1_FIBER; val 2210 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); val 2213 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); val 2215 drivers/net/ethernet/broadcom/bnx2.c val |= BCM5708S_UP1_2G5; val 2217 drivers/net/ethernet/broadcom/bnx2.c val &= ~BCM5708S_UP1_2G5; val 2218 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); val 2221 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); val 2222 drivers/net/ethernet/broadcom/bnx2.c val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; val 2223 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); val 2227 drivers/net/ethernet/broadcom/bnx2.c val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | val 2229 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); val 2239 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2250 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); val 2251 drivers/net/ethernet/broadcom/bnx2.c val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; val 2252 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); val 2254 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); val 2255 drivers/net/ethernet/broadcom/bnx2.c val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; val 2256 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); val 2259 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, BCM5708S_UP1, &val); val 2260 drivers/net/ethernet/broadcom/bnx2.c val |= BCM5708S_UP1_2G5; val 2261 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, BCM5708S_UP1, val); val 2270 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); val 2271 drivers/net/ethernet/broadcom/bnx2.c val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; val 2272 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); val 2276 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & val 2279 drivers/net/ethernet/broadcom/bnx2.c if (val) { val 2286 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); val 2306 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2310 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, 0x18, &val); val 2311 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); val 2314 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, 0x1c, &val); val 2315 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); val 2318 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2321 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, 0x18, &val); val 2322 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, 0x18, val & ~0x4007); val 2325 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, 0x1c, &val); val 2326 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); val 2335 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2354 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); val 2355 drivers/net/ethernet/broadcom/bnx2.c val &= ~(1 << 8); val 2356 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); val 2362 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, 0x18, &val); val 2363 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, 0x18, val | 0x4000); val 2365 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, 0x10, &val); val 2366 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, 0x10, val | 0x1); val 2370 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, 0x18, &val); val 2371 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, 0x18, val & ~0x4007); val 2373 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, 0x10, &val); val 2374 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, 0x10, val & ~0x1); val 2379 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val); val 2380 drivers/net/ethernet/broadcom/bnx2.c val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED; val 2384 drivers/net/ethernet/broadcom/bnx2.c val |= AUX_CTL_MISC_CTL_AUTOMDIX; val 2386 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); val 2396 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2413 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_PHYSID1, &val); val 2414 drivers/net/ethernet/broadcom/bnx2.c bp->phy_id = val << 16; val 2415 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_PHYSID2, &val); val 2416 drivers/net/ethernet/broadcom/bnx2.c bp->phy_id |= val & 0xffff; val 2529 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2544 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_shmem_rd(bp, BNX2_FW_MB); val 2546 drivers/net/ethernet/broadcom/bnx2.c if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) val 2553 drivers/net/ethernet/broadcom/bnx2.c if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { val 2566 drivers/net/ethernet/broadcom/bnx2.c if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) val 2576 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2578 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); val 2579 drivers/net/ethernet/broadcom/bnx2.c val |= (BNX2_PAGE_BITS - 8) << 16; val 2580 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_CTX_COMMAND, val); val 2582 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_CTX_COMMAND); val 2583 drivers/net/ethernet/broadcom/bnx2.c if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) val 2587 drivers/net/ethernet/broadcom/bnx2.c if (val & BNX2_CTX_COMMAND_MEM_INIT) val 2607 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); val 2608 drivers/net/ethernet/broadcom/bnx2.c if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) val 2612 drivers/net/ethernet/broadcom/bnx2.c if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { val 2668 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2680 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); val 2681 drivers/net/ethernet/broadcom/bnx2.c while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { val 2685 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); val 2687 drivers/net/ethernet/broadcom/bnx2.c val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; val 2690 drivers/net/ethernet/broadcom/bnx2.c if (!(val & (1 << 9))) { val 2691 drivers/net/ethernet/broadcom/bnx2.c good_mbuf[good_mbuf_cnt] = (u16) val; val 2695 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); val 2703 drivers/net/ethernet/broadcom/bnx2.c val = good_mbuf[good_mbuf_cnt]; val 2704 drivers/net/ethernet/broadcom/bnx2.c val = (val << 9) | val | 1; val 2706 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); val 2715 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 2717 drivers/net/ethernet/broadcom/bnx2.c val = (mac_addr[0] << 8) | mac_addr[1]; val 2719 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); val 2721 drivers/net/ethernet/broadcom/bnx2.c val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | val 2724 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); val 3785 drivers/net/ethernet/broadcom/bnx2.c u32 val, cmd, addr; val 3806 drivers/net/ethernet/broadcom/bnx2.c val = (i / 8) | cmd; val 3807 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, addr, val); val 3822 drivers/net/ethernet/broadcom/bnx2.c val = (loc / 2) | cmd; val 3823 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, addr, val); val 3845 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 3848 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_reg_rd_ind(bp, cpu_reg->mode); val 3849 drivers/net/ethernet/broadcom/bnx2.c val |= cpu_reg->mode_value_halt; val 3850 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_wr_ind(bp, cpu_reg->mode, val); val 3898 drivers/net/ethernet/broadcom/bnx2.c val = be32_to_cpu(fw_entry->start_addr); val 3899 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_wr_ind(bp, cpu_reg->pc, val); val 3902 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_reg_rd_ind(bp, cpu_reg->mode); val 3903 drivers/net/ethernet/broadcom/bnx2.c val &= ~cpu_reg->mode_value_halt; val 3905 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_wr_ind(bp, cpu_reg->mode, val); val 3954 drivers/net/ethernet/broadcom/bnx2.c u32 val, wol_msg; val 3981 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_EMAC_MODE); val 3984 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_EMAC_MODE_PORT; val 3985 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_MPKT_RCVD | val 3989 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_PORT_MII; val 3991 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_PORT_GMII; val 3993 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_25G_MODE; val 3996 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_EMAC_MODE, val); val 4005 drivers/net/ethernet/broadcom/bnx2.c val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN; val 4007 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_RPM_SORT_USER0, val); val 4008 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA); val 4016 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_RPM_CONFIG); val 4017 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_RPM_CONFIG_ACPI_ENA; val 4018 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_RPM_CONFIG, val); val 4026 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4036 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); val 4038 drivers/net/ethernet/broadcom/bnx2.c val | BNX2_PORT_FEATURE_ASF_ENABLED); val 4040 drivers/net/ethernet/broadcom/bnx2.c bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val); val 4050 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4055 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_EMAC_MODE); val 4056 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; val 4057 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_EMAC_MODE_MPKT; val 4058 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_EMAC_MODE, val); val 4060 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_RPM_CONFIG); val 4061 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_RPM_CONFIG_ACPI_ENA; val 4062 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_RPM_CONFIG, val); val 4077 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4083 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); val 4084 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_CONDITION_PM_STATE_MASK; val 4085 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_CONDITION_PM_STATE_UNPREP; val 4086 drivers/net/ethernet/broadcom/bnx2.c bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val); val 4104 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4110 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_NVM_SW_ARB); val 4111 drivers/net/ethernet/broadcom/bnx2.c if (val & BNX2_NVM_SW_ARB_ARB_ARB2) val 4127 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4133 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_NVM_SW_ARB); val 4134 drivers/net/ethernet/broadcom/bnx2.c if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) val 4150 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4152 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MISC_CFG); val 4153 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); val 4165 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_NVM_COMMAND); val 4166 drivers/net/ethernet/broadcom/bnx2.c if (val & BNX2_NVM_COMMAND_DONE) val 4179 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4181 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MISC_CFG); val 4182 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); val 4189 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4191 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); val 4194 drivers/net/ethernet/broadcom/bnx2.c val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); val 4200 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4202 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); val 4205 drivers/net/ethernet/broadcom/bnx2.c val & ~(BNX2_NVM_ACCESS_ENABLE_EN | val 4234 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4238 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_NVM_COMMAND); val 4239 drivers/net/ethernet/broadcom/bnx2.c if (val & BNX2_NVM_COMMAND_DONE) val 4276 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4280 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_NVM_COMMAND); val 4281 drivers/net/ethernet/broadcom/bnx2.c if (val & BNX2_NVM_COMMAND_DONE) { val 4295 drivers/net/ethernet/broadcom/bnx2.c bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) val 4314 drivers/net/ethernet/broadcom/bnx2.c memcpy(&val32, val, 4); val 4341 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4351 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_NVM_CFG1); val 4355 drivers/net/ethernet/broadcom/bnx2.c if (val & 0x40000000) { val 4360 drivers/net/ethernet/broadcom/bnx2.c if ((val & FLASH_BACKUP_STRAP_MASK) == val 4371 drivers/net/ethernet/broadcom/bnx2.c if (val & (1 << 23)) val 4379 drivers/net/ethernet/broadcom/bnx2.c if ((val & mask) == (flash->strapping & mask)) { val 4411 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); val 4412 drivers/net/ethernet/broadcom/bnx2.c val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; val 4413 drivers/net/ethernet/broadcom/bnx2.c if (val) val 4414 drivers/net/ethernet/broadcom/bnx2.c bp->flash_size = val; val 4714 drivers/net/ethernet/broadcom/bnx2.c u32 val, sig = 0; val 4722 drivers/net/ethernet/broadcom/bnx2.c val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); val 4723 drivers/net/ethernet/broadcom/bnx2.c if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) val 4726 drivers/net/ethernet/broadcom/bnx2.c if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) { val 4732 drivers/net/ethernet/broadcom/bnx2.c (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) { val 4763 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4777 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); val 4780 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); val 4781 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; val 4782 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); val 4783 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); val 4787 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); val 4788 drivers/net/ethernet/broadcom/bnx2.c if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND)) val 4800 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 4818 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MISC_ID); val 4825 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | val 4828 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); val 4831 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | val 4836 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); val 4848 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG); val 4849 drivers/net/ethernet/broadcom/bnx2.c if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | val 4855 drivers/net/ethernet/broadcom/bnx2.c if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | val 4863 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0); val 4864 drivers/net/ethernet/broadcom/bnx2.c if (val != 0x01020304) { val 4904 drivers/net/ethernet/broadcom/bnx2.c u32 val, mtu; val 4910 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | val 4919 drivers/net/ethernet/broadcom/bnx2.c val |= (0x2 << 20) | (1 << 11); val 4922 drivers/net/ethernet/broadcom/bnx2.c val |= (1 << 23); val 4927 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; val 4929 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_DMA_CONFIG, val); val 4932 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_TDMA_CONFIG); val 4933 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_TDMA_CONFIG_ONE_DMA; val 4934 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_TDMA_CONFIG, val); val 4967 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MQ_CONFIG); val 4968 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; val 4969 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; val 4971 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; val 4973 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_MQ_CONFIG_HALT_DIS; val 4976 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_MQ_CONFIG, val); val 4978 drivers/net/ethernet/broadcom/bnx2.c val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); val 4979 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); val 4980 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val); val 4982 drivers/net/ethernet/broadcom/bnx2.c val = (BNX2_PAGE_BITS - 8) << 24; val 4983 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_RV2P_CONFIG, val); val 4986 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_TBDR_CONFIG); val 4987 drivers/net/ethernet/broadcom/bnx2.c val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; val 4988 drivers/net/ethernet/broadcom/bnx2.c val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; val 4989 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_TBDR_CONFIG, val); val 4991 drivers/net/ethernet/broadcom/bnx2.c val = bp->mac_addr[0] + val 4997 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); val 5001 drivers/net/ethernet/broadcom/bnx2.c val = mtu + ETH_HLEN + ETH_FCS_LEN; val 5002 drivers/net/ethernet/broadcom/bnx2.c if (val > (MAX_ETHERNET_PACKET_SIZE + ETH_HLEN + 4)) val 5003 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; val 5004 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); val 5057 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_HC_CONFIG_COLLECT_STATS; val 5059 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | val 5067 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; val 5071 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; val 5073 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_HC_CONFIG, val); val 5113 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); val 5114 drivers/net/ethernet/broadcom/bnx2.c val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; val 5115 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); val 5156 drivers/net/ethernet/broadcom/bnx2.c u32 val, offset0, offset1, offset2, offset3; val 5170 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; val 5171 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, cid_addr, offset0, val); val 5173 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); val 5174 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, cid_addr, offset1, val); val 5176 drivers/net/ethernet/broadcom/bnx2.c val = (u64) txr->tx_desc_mapping >> 32; val 5177 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, cid_addr, offset2, val); val 5179 drivers/net/ethernet/broadcom/bnx2.c val = (u64) txr->tx_desc_mapping & 0xffffffff; val 5180 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, cid_addr, offset3, val); val 5244 drivers/net/ethernet/broadcom/bnx2.c u32 cid, rx_cid_addr, val; val 5261 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5); val 5262 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); val 5270 drivers/net/ethernet/broadcom/bnx2.c val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; val 5271 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); val 5275 drivers/net/ethernet/broadcom/bnx2.c val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; val 5276 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); val 5278 drivers/net/ethernet/broadcom/bnx2.c val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; val 5279 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); val 5285 drivers/net/ethernet/broadcom/bnx2.c val = (u64) rxr->rx_desc_mapping[0] >> 32; val 5286 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); val 5288 drivers/net/ethernet/broadcom/bnx2.c val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; val 5289 drivers/net/ethernet/broadcom/bnx2.c bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); val 5329 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 5364 drivers/net/ethernet/broadcom/bnx2.c val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | val 5367 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val); val 5693 drivers/net/ethernet/broadcom/bnx2.c u32 offset, rw_mask, ro_mask, save_val, val; val 5707 drivers/net/ethernet/broadcom/bnx2.c val = readl(bp->regview + offset); val 5708 drivers/net/ethernet/broadcom/bnx2.c if ((val & rw_mask) != 0) { val 5712 drivers/net/ethernet/broadcom/bnx2.c if ((val & ro_mask) != (save_val & ro_mask)) { val 5718 drivers/net/ethernet/broadcom/bnx2.c val = readl(bp->regview + offset); val 5719 drivers/net/ethernet/broadcom/bnx2.c if ((val & rw_mask) != rw_mask) { val 5723 drivers/net/ethernet/broadcom/bnx2.c if ((val & ro_mask) != (save_val & ro_mask)) { val 6133 drivers/net/ethernet/broadcom/bnx2.c u32 val; val 6136 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); val 6137 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); val 6139 drivers/net/ethernet/broadcom/bnx2.c if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { val 6145 drivers/net/ethernet/broadcom/bnx2.c } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) val 7948 drivers/net/ethernet/broadcom/bnx2.c u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); val 7949 drivers/net/ethernet/broadcom/bnx2.c u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; val 7959 drivers/net/ethernet/broadcom/bnx2.c if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) val 7960 drivers/net/ethernet/broadcom/bnx2.c strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; val 7962 drivers/net/ethernet/broadcom/bnx2.c strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; val 7010 drivers/net/ethernet/broadcom/bnx2.h #define BNX2_WR(bp, offset, val) \ val 7011 drivers/net/ethernet/broadcom/bnx2.h writel(val, bp->regview + offset) val 7013 drivers/net/ethernet/broadcom/bnx2.h #define BNX2_WR16(bp, offset, val) \ val 7014 drivers/net/ethernet/broadcom/bnx2.h writew(val, bp->regview + offset) val 169 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR_RELAXED(bp, offset, val) \ val 170 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h writel_relaxed((u32)val, REG_ADDR(bp, offset)) val 172 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR16_RELAXED(bp, offset, val) \ val 173 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h writew_relaxed((u16)val, REG_ADDR(bp, offset)) val 175 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) val 176 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) val 177 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) val 180 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) val 207 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) val 212 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) val 219 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ val 220 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h MF_CFG_ADDR(bp, field), (val)) val 228 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) val 767 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define DOORBELL_RELAXED(bp, cid, val) \ val 768 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid))) val 2066 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h u32 val; val 2069 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h val = REG_RD(bp, reg); val 2070 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h if (val == expected) val 2077 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h return val; val 2887 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c u32 val; val 2888 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]); val 2889 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c val &= ~DRV_FLAGS_MTU_MASK; val 2890 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c val |= (bp->dev->mtu << DRV_FLAGS_MTU_SHIFT); val 2892 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED | val 2986 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c u32 val; val 2987 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]); val 2989 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); val 499 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h int bnx2x_set_vf_spoofchk(struct net_device *dev, int idx, bool val); val 74 drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c u32 pri_bit, val = 0; val 100 drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c val |= 1 << (i * 4); val 103 drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c pfc_params.pkt_priority_to_cos = val; val 1030 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) val 1035 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) val 1038 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c bp->dump_preset_idx = val->flag; val 1261 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 val; val 1276 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); val 1277 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) val 1283 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { val 1297 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 val; val 1309 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); val 1310 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) val 1316 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { val 1329 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 val; val 1331 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); val 1335 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c (val | MCPR_NVM_ACCESS_ENABLE_EN | val 1341 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 val; val 1343 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); val 1347 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | val 1355 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 val; val 1380 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); val 1382 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (val & MCPR_NVM_COMMAND_DONE) { val 1383 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); val 1388 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c *ret_val = cpu_to_be32(val); val 1404 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c __be32 val; val 1431 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); val 1432 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c memcpy(ret_buf, &val, 4); val 1443 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); val 1444 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c memcpy(ret_buf, &val, 4); val 1625 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, val 1637 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); val 1655 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); val 1656 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (val & MCPR_NVM_COMMAND_DONE) { val 1674 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 cmd_flags, align_offset, val; val 1700 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = be32_to_cpu(val_be); val 1702 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val &= ~le32_to_cpu((__force __le32) val 1704 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val |= le32_to_cpu((__force __le32) val 1707 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c rc = bnx2x_nvram_write_dword(bp, align_offset, val, val 1723 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 val; val 1761 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c memcpy(&val, data_buf, 4); val 1769 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); val 2353 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 offset, mask, save_val, val; val 2364 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, offset); val 2370 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if ((val & mask) != (wr_val & mask)) { val 2373 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c offset, val, wr_val, mask); val 2388 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 val, index; val 2442 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, prty_tbl[i].offset); val 2443 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (val & ~(prty_tbl[i].hw_mask[index])) { val 2445 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c "%s is 0x%x\n", prty_tbl[i].name, val); val 2457 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, prty_tbl[i].offset); val 2458 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (val & ~(prty_tbl[i].hw_mask[index])) { val 2460 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c "%s is 0x%x\n", prty_tbl[i].name, val); val 3052 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 val; val 3055 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); val 3094 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); val 1754 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ val 1758 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ val 1769 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h #define DCBX_PRI_PG_SET(a, i, val) \ val 1770 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) val 1775 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h #define DCBX_PG_BW_SET(a, i, val) \ val 1776 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) val 4906 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h u8 val[MAX_VLAN_PRIORITIES]; val 5093 drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h u32 val[HC_SB_MAX_DYNAMIC_INDICES]; val 57 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h u32 val; val 63 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h u32 val; val 46 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); val 265 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, addr, op->write.val); val 478 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h u32 val, i; val 518 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val = REG_RD(bp, write_arb_addr[i].l); val 520 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val | (write_arb_data[i][w_order].l << 10)); val 522 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val = REG_RD(bp, write_arb_addr[i].add); val 524 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val | (write_arb_data[i][w_order].add << 10)); val 526 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val = REG_RD(bp, write_arb_addr[i].ubound); val 528 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val | (write_arb_data[i][w_order].ubound << 7)); val 532 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val = write_arb_data[NUM_WR_Q-1][w_order].add; val 533 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; val 534 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; val 535 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); val 537 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val = read_arb_data[NUM_RD_Q-1][r_order].add; val 538 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; val 539 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; val 540 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); val 566 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val = w_order; val 567 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val); val 569 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val = ((w_order == 0) ? 2 : 3); val 573 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_HC_MPS, val); val 574 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_USDM_MPS, val); val 575 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val); val 576 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val); val 577 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val); val 578 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_QM_MPS, val); val 579 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_TM_MPS, val); val 580 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_SRC_MPS, val); val 581 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_DBG_MPS, val); val 582 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR(bp, PXP2_REG_WR_CDU_MPS, val); val 587 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST); val 588 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h val &= 0xFF; val 589 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h if (val <= 0x20) val 222 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = REG_RD(bp, reg); val 224 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= bits; val 225 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, reg, val); val 226 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c return val; val 231 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = REG_RD(bp, reg); val 233 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~bits; val 234 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, reg, val); val 235 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c return val; val 410 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) val 415 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); val 419 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); val 423 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) val 428 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); val 432 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); val 1310 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = 0; val 1340 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (!strict_cos) ? 0x2318 : 0x22E0; val 1341 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); val 1474 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 1485 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); val 1486 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); val 1490 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); val 1491 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); val 1497 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c } while (val & EMAC_MODE_RESET); val 1501 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = ((params->mac_addr[0] << 8) | val 1503 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); val 1505 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = ((params->mac_addr[2] << 24) | val 1509 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); val 1529 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 1534 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); val 1536 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | val 1539 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | val 1542 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); val 1548 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 1564 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | val 1570 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (0<<2); val 1573 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<2); val 1576 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (2<<2); val 1579 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (3<<2); val 1587 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; val 1590 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; val 1593 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; val 1595 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); val 1619 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; val 1620 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | val 1622 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); val 1626 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; val 1630 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; val 1631 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); val 1711 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 1725 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); val 1727 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); val 1729 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); val 1730 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); val 1737 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val, xmac_base; val 1784 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; val 1790 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; val 1794 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; val 1795 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); val 1810 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 1868 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); val 1869 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; val 1892 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; val 1894 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); val 1897 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); val 1899 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x810; val 1901 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~0x810; val 1902 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); val 1922 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0; val 1926 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 1; val 1928 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); val 1945 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = 0x14; val 1950 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<5); val 1951 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c wb_data[0] = val; val 1956 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0xc0; val 1960 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x800000; val 1961 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c wb_data[0] = val; val 1977 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = 0x14; val 1983 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<5); val 1984 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c wb_data[0] = val; val 1990 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0xc0; val 1994 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x800000; val 1995 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c wb_data[0] = val; val 2027 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0x8000; val 2029 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<16); /* enable automatic re-send */ val 2031 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c wb_data[0] = val; val 2037 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0x3; /* Enable RX and TX */ val 2039 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x4; /* Local loopback */ val 2044 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= ((1<<6)|(1<<5)); val 2046 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c wb_data[0] = val; val 2222 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 2245 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MISC_REG_RESET_REG_2); val 2246 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & val 2258 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0; val 2262 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 1; val 2263 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); val 2277 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 2297 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0x3; val 2299 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x4; val 2302 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c wb_data[0] = val; val 2404 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 2426 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0; val 2430 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 1; val 2431 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); val 2590 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 reg, u16 val) val 2601 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c tmp = ((phy->addr << 21) | (reg << 16) | val | val 2627 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val, mode; val 2637 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = ((phy->addr << 21) | (reg << 16) | val 2640 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); val 2645 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); val 2646 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (!(val & EMAC_MDIO_COMM_START_BUSY)) { val 2647 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); val 2652 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & EMAC_MDIO_COMM_START_BUSY) { val 2668 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 2682 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = ((phy->addr << 21) | (devad << 16) | reg | val 2685 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); val 2690 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); val 2691 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (!(val & EMAC_MDIO_COMM_START_BUSY)) { val 2696 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & EMAC_MDIO_COMM_START_BUSY) { val 2703 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = ((phy->addr << 21) | (devad << 16) | val 2706 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); val 2711 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, phy->mdio_ctrl + val 2713 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (!(val & EMAC_MDIO_COMM_START_BUSY)) { val 2714 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); val 2718 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & EMAC_MDIO_COMM_START_BUSY) { val 2741 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 devad, u16 reg, u16 val) val 2778 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c tmp = ((phy->addr << 21) | (devad << 16) | val | val 2972 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val = 0; val 2979 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x8; val 2983 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x4; val 2986 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); val 3088 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val, i; val 3101 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); val 3102 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MCPR_IMC_COMMAND_ENABLE; val 3103 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); val 3106 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (sl_devid << 16) | sl_addr; val 3107 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); val 3110 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (MCPR_IMC_COMMAND_ENABLE) | val 3114 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); val 3118 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); val 3119 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { val 3121 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); val 3133 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (MCPR_IMC_COMMAND_ENABLE) | val 3138 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); val 3142 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); val 3143 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { val 3145 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); val 3170 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 3171 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, devad, reg, &val); val 3172 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); val 3179 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 3180 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, devad, reg, &val); val 3181 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); val 3202 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 devad, u16 reg, u16 val) val 3212 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg, val); val 3324 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 3328 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = SERDES_RESET_BITS << (port*16); val 3331 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); val 3333 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); val 3360 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 3364 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = XGXS_RESET_BITS << (port*16); val 3367 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); val 3369 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); val 3460 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 3463 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); val 3465 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; val 3472 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; val 3477 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; val 3479 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); val 3480 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); val 3656 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_set[i].val); val 3691 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_set[i].val); val 3728 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 lane, i, cl72_ctrl, an_adv = 0, val; val 3745 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_set[i].val); val 3852 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); val 3856 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 1 << 11; val 3863 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 3 << 2; val 3865 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(3 << 2); val 3868 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 3898 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_set[i].val); val 3950 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 misc1_val, tap_val, tx_driver_val, lane, val; val 3984 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); val 3987 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c ((val | 0x0006) & 0xFFFE)); val 4084 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 4102 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_CL73_USERB0_CTRL, &val); val 4103 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(1<<5); val 4104 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<6); val 4106 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_CL73_USERB0_CTRL, val); val 4116 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); val 4117 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(3<<14); val 4118 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<15); val 4120 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); val 4274 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 4277 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_DIGITAL5_MISC6, &val); val 4279 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0xC000; val 4281 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= 0x3FFF; val 4283 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_DIGITAL5_MISC6, val); val 4285 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_DIGITAL5_MISC6, &val); val 4316 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c wc_regs[i].val); val 5184 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val = 0; val 5188 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_OVER_1G_UP1_2_5G; val 5190 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_OVER_1G_UP1_10G; val 5193 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_OVER_1G_UP1, val); val 5205 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 5213 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_CL73_IEEEB1_AN_ADV1, &val); val 5214 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; val 5215 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); val 5218 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_CL73_IEEEB1_AN_ADV1, val); val 5659 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 5662 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); val 5664 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) val 5667 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | val 5673 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_OVER_1G_LP_UP1, &val); val 5675 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & MDIO_OVER_1G_UP1_2_5G) val 5678 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) val 5761 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 5764 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_LP_AUTO_NEG2, &val); val 5766 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) val 5769 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | val 5775 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_DIGITAL3_LP_UP1, &val); val 5777 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & MDIO_OVER_1G_UP1_2_5G) val 5780 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) val 6768 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 addr, val; val 6777 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0; val 6779 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, addr) + 1; val 6780 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, addr, val); val 7091 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 7094 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_STATUS, &val); val 7097 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_STATUS, &val); val 7098 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<5)) val 7100 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & (1<<0)) == 0) val 7224 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 7229 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8073_CHIP_REV, &val); val 7231 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val != 1) { val 7238 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_ROM_VER2, &val); val 7241 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val != 0x102) val 7249 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val, cnt, cnt1 ; val 7253 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8073_CHIP_REV, &val); val 7255 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val > 0) { val 7269 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 7274 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (!(val & (1<<14)) || !(val & (1<<13))) { val 7277 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c } else if (!(val & (1<<15))) { val 7287 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8073_XAUI_WA, &val); val 7288 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<15)) { val 7372 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val = 0, tmp1; val 7405 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); val 7409 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val | (3<<9))); val 7421 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_8073_BAM, &val); val 7424 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_8073_BAM, val | 1); val 7437 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (1<<7); val 7439 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (1<<5); val 7444 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (1<<5); val 7446 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0; val 7449 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<7); val 7455 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<5); val 7456 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); val 7459 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); val 7511 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); val 7783 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 7801 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 7804 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(1<<15); val 7806 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<15); val 7811 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 7854 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val = 0; val 7880 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); val 7881 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == val 7887 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != val 7891 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); val 7899 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); val 7900 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); val 7906 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); val 7907 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == val 7983 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val, i; val 8004 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 8037 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); val 8038 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == val 8044 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != val 8048 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); val 8056 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); val 8057 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); val 8063 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); val 8064 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == val 8120 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; val 8129 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (u8 *)val) != 0) { val 8134 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] << val 8137 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c switch (val[SFP_EEPROM_CON_TYPE_ADDR]) { val 8145 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR]; val 8175 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] & val 8179 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { val 8193 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] & val 8214 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val[SFP_EEPROM_CON_TYPE_ADDR]); val 8260 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val, cmd; val 8265 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, params->shmem_base + val 8268 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == val 8324 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != val 8334 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 val; val 8345 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, val 8350 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 1, 1, &val); val 8360 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 1, 1, &val); val 8368 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 8383 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (1<<4); val 8388 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = (1<<1); val 8393 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 8484 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 8505 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 8506 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<12); val 8508 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (3<<5); val 8513 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= 0xff8f; /* Reset bits 4-6 */ val 8516 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 8624 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val = 0; val 8631 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); val 8632 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(0xf << (lane << 2)); val 8647 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (mode << (lane << 2)); val 8649 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); val 8652 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); val 8685 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = REG_RD(bp, params->shmem_base + val 8706 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == val 8726 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == val 8810 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 alarm_status, val; val 8818 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); val 8820 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(1<<0); val 8822 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<0); val 8823 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); val 8895 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 cnt, val, tmp1; val 8908 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); val 8909 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val) val 8922 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); val 8924 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~0x7; val 8926 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (phy->rx_preemphasis[i] & 0x7); val 8928 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c " reg 0x%x <-- val 0x%x\n", reg, val); val 8929 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); val 9179 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 9201 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 9202 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= 0xff8f; val 9203 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= led_mode_bitmask; val 9207 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 9211 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 9212 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= 0xffe0; val 9213 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= gpio_pins_bitmask; val 9217 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 9238 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 tmp1, val; val 9256 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8727_PCS_GP, &val); val 9257 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (3<<10); val 9260 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8727_PCS_GP, val); val 9382 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = REG_RD(bp, params->shmem_base + val 9444 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == val 9650 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val, fw_ver2, cnt, i; val 9670 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_set[i].reg, reg_set[i].val); val 9673 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); val 9674 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & 1) val 9692 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); val 9693 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & 1) val 9718 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val, led3_blink_rate, offset, i; val 9747 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8481_LINK_SIGNAL, &val); val 9748 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= 0xFE00; val 9749 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x0092; val 9752 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 2 << 12; /* LED5 ON based on source */ val 9756 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_8481_LINK_SIGNAL, val); val 9760 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_set[i].val); val 9768 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = MDIO_PMA_REG_84858_ALLOW_GPHY_ACT | val 9771 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = MDIO_PMA_REG_84823_LED3_STRETCH_EN; val 9777 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 9975 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 9987 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_848xx_CMD_HDLR_STATUS, &val); val 9988 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) && val 9989 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val != PHY84858_STATUS_CMD_SYSTEM_BUSY)) val 10021 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_848xx_CMD_HDLR_STATUS, &val); val 10022 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) || val 10023 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) val 10028 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) { val 10051 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 10064 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_848xx_CMD_HDLR_STATUS, &val); val 10065 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) val 10074 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val == PHY84833_STATUS_CMD_COMPLETE_PASS || val 10075 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val == PHY84833_STATUS_CMD_COMPLETE_ERROR) { val 10096 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_848xx_CMD_HDLR_STATUS, &val); val 10097 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || val 10098 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) val 10103 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { val 10115 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR || val 10116 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val == PHY84833_STATUS_CMD_COMPLETE_PASS) { val 10292 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 10344 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_CTL_REG_84823_MEDIA, &val); val 10345 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | val 10352 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | val 10355 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | val 10366 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; val 10369 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; val 10375 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; val 10380 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; val 10383 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_CTL_REG_84823_MEDIA, val); val 10385 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c params->multi_phy_config, val); val 10413 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_CTL_REG_84823_USER_CTRL_REG, &val); val 10415 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; val 10417 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; val 10419 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_CTL_REG_84823_USER_CTRL_REG, val); val 10423 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_84833_TOP_CFG_FW_REV, &val); val 10426 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && val 10427 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && val 10455 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_8481_AUX_CTRL, &val); val 10456 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x4000; val 10458 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_8481_AUX_CTRL, val); val 10461 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_8481_1G_100T_EXT_CTRL, &val); val 10462 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x1; val 10464 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_8481_1G_100T_EXT_CTRL, val); val 10471 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, &val); val 10472 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x4000; val 10474 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, val); val 10492 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val, val1, val2; val 10554 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 10555 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<5)) val 10561 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 10562 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & (1<<0)) == 0) val 10574 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_CL37_FC_LP, &val); val 10575 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<5)) val 10578 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<6)) val 10581 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<7)) val 10584 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<8)) val 10587 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<9)) val 10592 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_1000T_STATUS, &val); val 10594 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<10)) val 10597 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<11)) val 10602 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_REG_MASTER_STATUS, &val); val 10604 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<11)) val 10682 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 10822 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 10823 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= 0x8000; val 10824 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x2492; val 10829 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 10880 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 10881 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(7<<6); val 10882 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (2<<6); /* A83B[8:6]= 2 */ val 10886 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 10911 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 10913 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (!((val & val 10949 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = ((params->hw_led_mode << val 10956 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 10962 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 10963 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(7<<6); val 10964 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<6); /* A83B[8:6]= 1 */ val 10968 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 11005 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); val 11314 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 11327 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 11364 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 11365 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<5)) val 11370 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c &val); val 11371 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & (1<<0)) == 0) val 11382 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl22_read(bp, phy, 0x5, &val); val 11384 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<5)) val 11387 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<6)) val 11390 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<7)) val 11393 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<8)) val 11396 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<9)) val 11400 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl22_read(bp, phy, 0xa, &val); val 11401 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<10)) val 11404 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (val & (1<<11)) val 11420 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 11434 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl22_read(bp, phy, 0x00, &val); val 11435 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~((1<<6) | (1<<12) | (1<<13)); val 11436 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (1<<6) | (1<<8); val 11437 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl22_write(bp, phy, 0x00, val); val 11444 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl22_read(bp, phy, 0x18, &val); val 11445 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); val 11472 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 fw_ver1, fw_ver2, val; val 11492 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); val 11493 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 0x200; val 11495 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); val 11563 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val, cnt; val 11567 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_7101_RESET, &val); val 11575 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val | (1<<15))); val 11579 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_7101_RESET, &val); val 11581 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((val & (1<<15)) == 0) val 11599 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val = 0; val 11604 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 2; val 11607 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 1; val 11610 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = 0; val 11616 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val); val 12805 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 val = en * 0x1F; val 12809 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= en * 0x20; val 12810 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); val 13197 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val; val 13275 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_TX_POWER_DOWN, &val); val 13281 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (val | 1<<10)); val 13295 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_TX_POWER_DOWN, &val); val 13299 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); val 13305 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_EDC_FFE_MAIN, &val); val 13308 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); val 13321 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 13326 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); val 13327 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= ((1<<MISC_REGISTERS_GPIO_3)| val 13329 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); val 13585 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 phy_ver, val; val 13594 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); val 13595 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); val 14011 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val; val 14070 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); val 14071 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= 1 << (gpio_num + (gpio_port << 2)); val 14072 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); val 147 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h u16 val; val 397 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h u8 devad, u16 reg, u16 val); val 363 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) val 366 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); val 373 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 376 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); val 380 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c return val; val 761 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 addr, val; val 780 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); val 781 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) val 782 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); val 846 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = REG_RD(bp, addr); val 859 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | val 863 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | val 870 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val, port, addr); val 872 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, addr, val); val 873 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (REG_RD(bp, addr) != val) val 879 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); val 881 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(IGU_PF_CONF_MSI_MSIX_EN | val 885 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); val 887 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); val 888 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) val 1277 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 1279 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) val 1282 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c return val; val 1288 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); val 1289 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 0) { val 1290 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("%s usage count=%d\n", msg, val); val 1472 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 1474 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); val 1475 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); val 1477 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PBF_REG_DISABLE_PF); val 1478 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); val 1480 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); val 1481 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); val 1483 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); val 1484 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); val 1486 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); val 1487 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); val 1489 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); val 1490 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); val 1492 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); val 1493 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); val 1495 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); val 1497 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val); val 1548 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = REG_RD(bp, addr); val 1554 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | val 1556 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | val 1559 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; val 1561 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; val 1562 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | val 1566 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | val 1573 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c "write %x to HC %d (addr 0x%x)\n", val, port, addr); val 1575 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, addr, val); val 1577 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; val 1585 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, val 1588 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, addr, val); val 1597 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (0xee0f | (1 << (BP_VN(bp) + 4))); val 1600 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= 0x1100; val 1602 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = 0xffff; val 1604 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); val 1605 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); val 1611 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 1616 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); val 1619 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(IGU_PF_CONF_INT_LINE_EN | val 1621 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= (IGU_PF_CONF_MSI_MSIX_EN | val 1625 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= IGU_PF_CONF_SINGLE_ISR_EN; val 1627 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~IGU_PF_CONF_INT_LINE_EN; val 1628 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= (IGU_PF_CONF_MSI_MSIX_EN | val 1632 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~IGU_PF_CONF_MSI_MSIX_EN; val 1633 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= (IGU_PF_CONF_INT_LINE_EN | val 1640 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); val 1644 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= IGU_PF_CONF_FUNC_EN; val 1647 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); val 1649 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); val 1651 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & IGU_PF_CONF_INT_LINE_EN) val 1658 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (0xee0f | (1 << (BP_VN(bp) + 4))); val 1661 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= 0x1100; val 1663 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = 0xffff; val 1665 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); val 1666 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); val 2921 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 2924 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & val 2926 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { val 2927 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->mf_ov = val; val 2963 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 2980 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (0xff0f | (1 << (BP_VN(bp) + 4))); val 2982 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); val 2983 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); val 2985 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); val 2986 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); val 3940 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 j, val; val 3946 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); val 3947 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & MCPR_ACCESS_LOCK_LOCK) val 3952 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (!(val & MCPR_ACCESS_LOCK_LOCK)) { val 4145 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 4152 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_offset); val 4153 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; val 4154 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, val); val 4171 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_offset); val 4172 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0); val 4173 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, val); val 4183 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 4187 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); val 4188 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("DB hw attention 0x%x\n", val); val 4190 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & 0x2) val 4202 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_offset); val 4203 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1); val 4204 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, val); val 4214 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 4218 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); val 4219 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("CFC hw attention 0x%x\n", val); val 4221 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & 0x2) val 4226 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); val 4227 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("PXP hw attention-0 0x%x\n", val); val 4229 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & 0x18000) val 4233 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); val 4234 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("PXP hw attention-1 0x%x\n", val); val 4246 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_offset); val 4247 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2); val 4248 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, val); val 4258 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 4269 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, val 4272 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & (DRV_STATUS_DCC_EVENT_MASK | val 4275 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val & (DRV_STATUS_DCC_EVENT_MASK | val 4278 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & DRV_STATUS_SET_MF_BW) val 4281 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & DRV_STATUS_DRV_INFO_REQ) val 4284 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & DRV_STATUS_VF_DISABLED) val 4288 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) val 4292 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && val 4297 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & DRV_STATUS_AFEX_EVENT_MASK) val 4299 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val & DRV_STATUS_AFEX_EVENT_MASK); val 4300 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) val 4303 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & DRV_STATUS_OEM_UPDATE_SVID) val 4345 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = CHIP_IS_E1(bp) ? 0 : val 4347 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("GRC time-out 0x%08x\n", val); val 4350 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = CHIP_IS_E1(bp) ? 0 : val 4352 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("GRC reserved 0x%08x\n", val); val 4389 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 4391 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4392 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); val 4403 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 4405 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4406 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); val 4417 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4419 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); val 4420 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; val 4430 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 4434 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4437 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~bit; val 4438 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); val 4450 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 4454 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4457 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= bit; val 4458 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); val 4468 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4473 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c return (val & bit) ? false : true; val 4483 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val1, val; val 4490 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4492 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); val 4495 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val1 = (val & mask) >> shift; val 4501 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~mask; val 4504 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= ((val1 << shift) & mask); val 4506 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); val 4521 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val1, val; val 4528 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4529 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); val 4532 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val1 = (val & mask) >> shift; val 4538 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~mask; val 4541 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= ((val1 << shift) & mask); val 4543 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); val 4559 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); val 4561 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); val 4563 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (val & mask) >> shift; val 4566 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c engine, val); val 4568 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c return val != 0; val 5040 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 5043 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); val 5044 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("PGLUE hw attention 0x%x\n", val); val 5045 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) val 5047 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) val 5049 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) val 5051 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) val 5053 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & val 5056 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & val 5059 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) val 5061 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) val 5063 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) val 5067 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); val 5068 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("ATC hw attention 0x%x\n", val); val 5069 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) val 5071 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) val 5073 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) val 5075 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) val 5077 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) val 5079 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) val 5097 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 5165 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = ~deasserted; val 5166 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, val 5168 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_addr, val); val 6674 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = 0; val 6701 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = *bnx2x_sp(bp, wb_data[0]); val 6702 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val == 0x10) val 6708 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 0x10) { val 6709 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("NIG timeout val = 0x%x\n", val); val 6716 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); val 6717 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val == 1) val 6723 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 0x1) { val 6724 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("PRS timeout val = 0x%x\n", val); val 6757 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = *bnx2x_sp(bp, wb_data[0]); val 6758 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val == 0xb0) val 6764 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 0xb0) { val 6765 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("NIG timeout val = 0x%x\n", val); val 6770 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); val 6771 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 2) val 6772 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("PRS timeout val = 0x%x\n", val); val 6780 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); val 6781 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 3) val 6782 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_ERR("PRS timeout val = 0x%x\n", val); val 6787 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); val 6788 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 1) { val 6817 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 6852 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | val 6856 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | val 6858 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); val 6877 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = 0x1400; val 6884 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; val 6885 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; val 6888 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); val 6918 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 6925 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & val 6928 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) val 6936 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) val 6955 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_SPIO_INT); val 6956 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); val 6957 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, MISC_REG_SPIO_INT, val); val 6960 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); val 6961 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= MISC_SPIO_SPIO5; val 6962 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); val 6967 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); val 6968 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~IGU_PF_CONF_FUNC_EN; val 6970 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); val 6996 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) val 6998 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); val 6999 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); val 7000 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); val 7001 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); val 7002 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); val 7007 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); val 7008 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); val 7009 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); val 7010 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); val 7034 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 7047 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = 0xfffc; val 7049 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; val 7050 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; val 7052 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); val 7102 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); val 7103 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 1) { val 7107 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); val 7108 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 1) { val 7224 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); val 7225 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c } while (factor-- && (val != 1)); val 7227 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 1) { val 7372 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (4 << 24) + (0 << 12) + 1024; val 7373 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); val 7423 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); val 7424 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 1) { val 7428 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); val 7429 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 1) { val 7433 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); val 7434 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 1) { val 7444 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = *bnx2x_sp(bp, wb_data[0]); val 7447 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if ((val == 0) && bnx2x_int_mem_test(bp)) { val 7497 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val, reg; val 7546 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = bp->dev->mtu; val 7548 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c low = 96 + (val/64) + val 7549 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c ((val % 64) ? 1 : 0); val 7637 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = IS_MF(bp) ? 0xF7 : 0x7; val 7639 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= CHIP_IS_E1(bp) ? 0 : 0x10; val 7640 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); val 7683 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = 0; val 7686 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = 1; val 7690 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = 2; val 7695 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c NIG_REG_LLH0_CLS_TYPE), val); val 7705 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); val 7706 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & MISC_SPIO_SPIO5) { val 7709 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_addr); val 7710 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= AEU_INPUTS_ATTN_BITS_SPIO5; val 7711 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_addr, val); val 7937 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 addr, val; val 7955 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, addr); val 7956 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; val 7957 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, addr, val); val 8212 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, main_mem_prty_clr); val 8213 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val) val 8216 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val); val 9046 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 9064 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); val 9065 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val) val 9067 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c "BRB1 is not empty %d blocks are occupied\n", val); val 9141 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 9149 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (mac_addr[0] << 8) | mac_addr[1]; val 9150 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); val 9152 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | val 9154 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); val 9484 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 9493 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, addr); val 9494 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(0x300); val 9495 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, addr, val); val 9497 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); val 9498 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | val 9500 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); val 9507 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 9520 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, HC_REG_CONFIG_1); val 9522 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : val 9523 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); val 9525 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, HC_REG_CONFIG_0); val 9527 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : val 9528 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); val 9531 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); val 9535 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : val 9536 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); val 9548 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); val 9549 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c *magic_val = val & SHARED_MF_CLP_MAGIC; val 9550 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); val 9562 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); val 9564 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); val 9620 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = 0; val 9634 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); val 9635 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & SHR_MEM_VALIDITY_MB) val 9807 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = 0; val 9861 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bnx2x_reset_mcp_prep(bp, &val); val 9877 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (global && bnx2x_reset_mcp_comp(bp, val)) val 10494 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val, base_addr, offset, mask, reset_reg; val 10504 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); val 10506 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if ((mask & reset_reg) && val) { val 10538 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); val 10540 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val & ~(1 << 1)); val 10542 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val | (1 << 1)); val 10562 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) val 10563 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) val 10687 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bool val; val 10692 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); val 10696 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c return val; val 11004 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val, val2, val3, val4, id, boot_mode; val 11009 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_CHIP_NUM); val 11010 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c id = ((val & 0xffff) << 16); val 11011 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_CHIP_REV); val 11012 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c id |= ((val & 0xf) << 12); val 11017 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); val 11018 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c id |= (((val >> 24) & 0xf) << 4); val 11019 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_BOND_ID); val 11020 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c id |= (val & 0xf); val 11038 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); val 11039 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if ((val & 1) == 0) val 11040 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MISC_REG_PORT4MODE_EN); val 11042 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (val >> 1) & 1; val 11043 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : val 11045 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : val 11062 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (REG_RD(bp, 0x2874) & 0x55); val 11064 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { val 11069 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); val 11071 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val & MCPR_NVM_CFG4_FLASH_SIZE)); val 11108 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, dev_info.shared_feature_config.config); val 11109 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) val 11116 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; val 11117 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->common.bc_ver = val; val 11118 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_DEV_INFO("bc_ver %X\n", val); val 11119 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val < BNX2X_BC_VER) { val 11123 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_BC_VER, val); val 11126 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? val 11130 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? val 11133 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? val 11136 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? val 11140 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val >= REQ_BC_VER_4_MT_SUPPORTED) ? val 11143 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? val 11146 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? val 11149 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? val 11152 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? val 11179 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); val 11185 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val, val2, val3, val4); val 11188 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) val 11189 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) val 11195 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 11214 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); val 11215 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) val 11217 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c fid = IGU_FID(val); val 11221 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (IGU_VEC(val) == 0) val 11809 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val, val2; val 11826 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = MF_CFG_RD(bp, func_ext_config[func]. val 11828 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bnx2x_set_mac_buf(iscsi_mac, val, val2); val 11838 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = MF_CFG_RD(bp, func_ext_config[func]. val 11840 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bnx2x_set_mac_buf(fip_mac, val, val2); val 11875 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, dev_info.port_hw_config[port]. val 11877 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bnx2x_set_mac_buf(iscsi_mac, val, val2); val 11881 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, dev_info.port_hw_config[port]. val 11883 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bnx2x_set_mac_buf(fip_mac, val, val2); val 11901 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val, val2; val 11913 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); val 11915 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) val 11916 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); val 11923 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); val 11924 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); val 11933 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); val 11934 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bnx2x_set_mac_buf(bp->phys_port_id, val, val2); val 11973 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val; val 11975 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); val 11978 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != 0xffff) { val 11990 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = 0, val2 = 0; val 12016 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); val 12018 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { val 12023 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); val 12024 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); val 12041 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { val 12100 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = SHMEM_RD(bp, val 12102 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; val 12104 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c switch (val) { val 12123 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = MF_CFG_RD(bp, val 12125 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= FUNC_MF_CFG_E1HOV_TAG_MASK; val 12127 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { val 12182 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val); val 12188 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); val 12197 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & val 12199 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { val 12200 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->mf_ov = val; val 12246 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = MF_CFG_RD(bp, val 12248 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) val 13793 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c int val, period, period1, period2, dif, dif1, dif2; val 13819 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c for (val = 0; val <= 31; val++) { val 13820 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if ((val & 0x7) == 0) val 13822 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c period1 = val * 1000000 / ppb; val 13825 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c dif1 = ppb - (val * 1000000 / period1); val 13830 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c dif2 = ppb - (val * 1000000 / period2); val 13837 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c best_val = val; val 6180 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c memcpy(rdata->c2s_pri_trans_table.val, val 739 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c u32 val; val 751 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); val 752 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN); val 753 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val &= ~IGU_VF_CONF_PARENT_MASK; val 754 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT; val 755 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); val 759 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c vf->abs_vfid, val); val 1089 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c u32 val; val 1094 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); val 1095 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) val 1097 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); val 1107 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)); val 1150 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c u32 val; val 1163 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); val 1164 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK) val 1972 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c u32 val = enable ? (abs_vfid | (1 << 6)) : 0; val 1974 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c REG_WR(bp, reg, val); val 1988 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c u32 val; val 1992 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); val 1993 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN | val 1995 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); val 2963 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c int bnx2x_set_vf_spoofchk(struct net_device *dev, int idx, bool val) val 2974 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c if (vf->spoofchk == val) val 2977 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c vf->spoofchk = val ? 1 : 0; val 2980 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val ? "enabling" : "disabling", idx); val 3009 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c if (val) { val 3021 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c val ? "enable" : "disable", idx, i); val 3028 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c "%s spoofchk for VF[%d]\n", val ? "Enabled" : "Disabled", val 1204 drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c u32 val; val 1207 drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c val = SHMEM2_RD(bp, edebug_driver_if[1]); val 1209 drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT) val 1918 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 reg_type, reg_off, val = 0; val 1924 drivers/net/ethernet/broadcom/bnxt/bnxt.c pci_read_config_dword(bp->pdev, reg_off, &val); val 1930 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = readl(bp->bar0 + reg_off); val 1933 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = readl(bp->bar1 + reg_off); val 1937 drivers/net/ethernet/broadcom/bnxt/bnxt.c val &= fw_health->fw_reset_inprog_reg_mask; val 1938 drivers/net/ethernet/broadcom/bnxt/bnxt.c return val; val 6144 drivers/net/ethernet/broadcom/bnxt/bnxt.c u16 val, tmr, max, flags = 0; val 6151 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = clamp_t(u16, hw_coal->coal_bufs, 1, max); val 6152 drivers/net/ethernet/broadcom/bnxt/bnxt.c req->num_cmpl_aggr_int = cpu_to_le16(val); val 6154 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); val 6155 drivers/net/ethernet/broadcom/bnxt/bnxt.c req->num_cmpl_dma_aggr = cpu_to_le16(val); val 6157 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, val 6159 drivers/net/ethernet/broadcom/bnxt/bnxt.c req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); val 6167 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = tmr / 2; val 6168 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); val 6169 drivers/net/ethernet/broadcom/bnxt/bnxt.c req->int_lat_tmr_min = cpu_to_le16(val); val 6174 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); val 6175 drivers/net/ethernet/broadcom/bnxt/bnxt.c req->cmpl_aggr_dma_tmr = cpu_to_le16(val); val 6180 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = clamp_t(u16, tmr, 1, val 6182 drivers/net/ethernet/broadcom/bnxt/bnxt.c req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); val 9338 drivers/net/ethernet/broadcom/bnxt/bnxt.c u16 *val) val 9361 drivers/net/ethernet/broadcom/bnxt/bnxt.c *val = le16_to_cpu(resp->reg_data); val 9367 drivers/net/ethernet/broadcom/bnxt/bnxt.c u16 val) val 9384 drivers/net/ethernet/broadcom/bnxt/bnxt.c req.reg_data = cpu_to_le16(val); val 9962 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 val; val 9972 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); val 9973 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (val == fw_health->last_fw_heartbeat) val 9976 drivers/net/ethernet/broadcom/bnxt/bnxt.c fw_health->last_fw_heartbeat = val; val 9978 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); val 9979 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (val != fw_health->last_fw_reset_cnt) val 10081 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 val; val 10083 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); val 10084 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (val == fw_health->last_fw_heartbeat) val 10087 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); val 10088 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (val != fw_health->last_fw_reset_cnt) val 10217 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 val[2]; val 10230 drivers/net/ethernet/broadcom/bnxt/bnxt.c fw_ring_id, &val[0], &val[1]); val 10595 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 val = fw_health->fw_reset_seq_vals[reg_idx]; val 10603 drivers/net/ethernet/broadcom/bnxt/bnxt.c pci_write_config_dword(bp->pdev, reg_off, val); val 10611 drivers/net/ethernet/broadcom/bnxt/bnxt.c writel(val, bp->bar0 + reg_off); val 10614 drivers/net/ethernet/broadcom/bnxt/bnxt.c writel(val, bp->bar1 + reg_off); val 10618 drivers/net/ethernet/broadcom/bnxt/bnxt.c pci_read_config_dword(bp->pdev, 0, &val); val 10694 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 val; val 10696 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); val 10697 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (!(val & BNXT_FW_STATUS_SHUTDOWN) && val 10721 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 val; val 10723 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = bnxt_fw_health_readl(bp, val 10725 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (val) val 10727 drivers/net/ethernet/broadcom/bnxt/bnxt.c val); val 22 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c u32 val, health_status; val 28 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); val 29 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c health_status = val & 0xffff; val 43 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c if (val >> 16) { val 44 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c rc = devlink_fmsg_u32_pair_put(fmsg, "Error code", val >> 16); val 49 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); val 50 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c rc = devlink_fmsg_u32_pair_put(fmsg, "Reset count", val); val 293 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c int msg_len, union devlink_param_value *val) val 333 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c bnxt_copy_to_nvm_data(data, val, nvm_param.nvm_num_bits, val 340 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c bnxt_copy_from_nvm_data(val, data, val 365 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c rc = bnxt_hwrm_nvm_req(bp, id, &req, sizeof(req), &ctx->val); val 368 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c ctx->val.vbool = !ctx->val.vbool; val 382 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c ctx->val.vbool = !ctx->val.vbool; val 384 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c return bnxt_hwrm_nvm_req(bp, id, &req, sizeof(req), &ctx->val); val 388 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c union devlink_param_value val, val 399 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c if (val.vu32 > max_val) { val 1452 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c static void accumulate_val(u64 *accum, u64 val, u64 mask) val 1456 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c bool wrapped = val < low_bits(*accum, mask); val 1458 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c *accum = high_bits(*accum, mask) + val; val 188 drivers/net/ethernet/broadcom/cnic.c static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val) val 199 drivers/net/ethernet/broadcom/cnic.c io->data = val; val 235 drivers/net/ethernet/broadcom/cnic.c static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val) val 245 drivers/net/ethernet/broadcom/cnic.c io->data = val; val 2387 drivers/net/ethernet/broadcom/cnic.c u32 val; val 2389 drivers/net/ethernet/broadcom/cnic.c val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG, val 2391 drivers/net/ethernet/broadcom/cnic.c fctx->xstorm_ag_context.cdu_reserved = val; val 2392 drivers/net/ethernet/broadcom/cnic.c val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG, val 2394 drivers/net/ethernet/broadcom/cnic.c fctx->ustorm_ag_context.cdu_usage = val; val 4394 drivers/net/ethernet/broadcom/cnic.c u32 val; val 4406 drivers/net/ethernet/broadcom/cnic.c val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL); val 4407 drivers/net/ethernet/broadcom/cnic.c if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) val 4411 drivers/net/ethernet/broadcom/cnic.c if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { val 4536 drivers/net/ethernet/broadcom/cnic.c u32 val, offset0, offset1, offset2, offset3; val 4575 drivers/net/ethernet/broadcom/cnic.c val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; val 4576 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, cid_addr, offset0, val); val 4578 drivers/net/ethernet/broadcom/cnic.c val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); val 4579 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, cid_addr, offset1, val); val 4588 drivers/net/ethernet/broadcom/cnic.c val = (u64) ring_map >> 32; val 4589 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, cid_addr, offset2, val); val 4590 drivers/net/ethernet/broadcom/cnic.c txbd->tx_bd_haddr_hi = val; val 4592 drivers/net/ethernet/broadcom/cnic.c val = (u64) ring_map & 0xffffffff; val 4593 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, cid_addr, offset3, val); val 4594 drivers/net/ethernet/broadcom/cnic.c txbd->tx_bd_haddr_lo = val; val 4602 drivers/net/ethernet/broadcom/cnic.c u32 cid_addr, sb_id, val, coal_reg, coal_val; val 4630 drivers/net/ethernet/broadcom/cnic.c val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | val 4632 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val); val 4635 drivers/net/ethernet/broadcom/cnic.c val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT; val 4637 drivers/net/ethernet/broadcom/cnic.c val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id); val 4638 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val); val 4651 drivers/net/ethernet/broadcom/cnic.c val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32; val 4652 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); val 4653 drivers/net/ethernet/broadcom/cnic.c rxbd->rx_bd_haddr_hi = val; val 4655 drivers/net/ethernet/broadcom/cnic.c val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff; val 4656 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); val 4657 drivers/net/ethernet/broadcom/cnic.c rxbd->rx_bd_haddr_lo = val; val 4659 drivers/net/ethernet/broadcom/cnic.c val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD); val 4660 drivers/net/ethernet/broadcom/cnic.c cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2)); val 4678 drivers/net/ethernet/broadcom/cnic.c u32 val; val 4680 drivers/net/ethernet/broadcom/cnic.c val = cp->func << 2; val 4682 drivers/net/ethernet/broadcom/cnic.c cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val); val 4684 drivers/net/ethernet/broadcom/cnic.c val = cnic_reg_rd_ind(dev, cp->shmem_base + val 4686 drivers/net/ethernet/broadcom/cnic.c dev->mac_addr[0] = (u8) (val >> 8); val 4687 drivers/net/ethernet/broadcom/cnic.c dev->mac_addr[1] = (u8) val; val 4689 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val); val 4691 drivers/net/ethernet/broadcom/cnic.c val = cnic_reg_rd_ind(dev, cp->shmem_base + val 4693 drivers/net/ethernet/broadcom/cnic.c dev->mac_addr[2] = (u8) (val >> 24); val 4694 drivers/net/ethernet/broadcom/cnic.c dev->mac_addr[3] = (u8) (val >> 16); val 4695 drivers/net/ethernet/broadcom/cnic.c dev->mac_addr[4] = (u8) (val >> 8); val 4696 drivers/net/ethernet/broadcom/cnic.c dev->mac_addr[5] = (u8) val; val 4698 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val); val 4700 drivers/net/ethernet/broadcom/cnic.c val = 4 | BNX2_RPM_SORT_USER2_BC_EN; val 4702 drivers/net/ethernet/broadcom/cnic.c val |= BNX2_RPM_SORT_USER2_PROM_VLAN; val 4705 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, BNX2_RPM_SORT_USER2, val); val 4706 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA); val 4714 drivers/net/ethernet/broadcom/cnic.c u32 val, kcq_cid_addr, kwq_cid_addr; val 4719 drivers/net/ethernet/broadcom/cnic.c val = CNIC_RD(dev, BNX2_MQ_CONFIG); val 4720 drivers/net/ethernet/broadcom/cnic.c val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; val 4722 drivers/net/ethernet/broadcom/cnic.c val |= (12 - 8) << 4; val 4724 drivers/net/ethernet/broadcom/cnic.c val |= (CNIC_PAGE_BITS - 8) << 4; val 4726 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, BNX2_MQ_CONFIG, val); val 4753 drivers/net/ethernet/broadcom/cnic.c val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | val 4755 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val); val 4757 drivers/net/ethernet/broadcom/cnic.c val = (CNIC_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16; val 4758 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val); val 4760 drivers/net/ethernet/broadcom/cnic.c val = ((CNIC_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT; val 4761 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val); val 4763 drivers/net/ethernet/broadcom/cnic.c val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32); val 4764 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val); val 4766 drivers/net/ethernet/broadcom/cnic.c val = (u32) cp->kwq_info.pgtbl_map; val 4767 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val); val 4779 drivers/net/ethernet/broadcom/cnic.c val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | val 4781 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val); val 4783 drivers/net/ethernet/broadcom/cnic.c val = (CNIC_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16; val 4784 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val); val 4786 drivers/net/ethernet/broadcom/cnic.c val = ((CNIC_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT; val 4787 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val); val 4789 drivers/net/ethernet/broadcom/cnic.c val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32); val 4790 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val); val 4792 drivers/net/ethernet/broadcom/cnic.c val = (u32) cp->kcq1.dma.pgtbl_map; val 4793 drivers/net/ethernet/broadcom/cnic.c cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val); val 4928 drivers/net/ethernet/broadcom/cnic.c u32 val; val 4958 drivers/net/ethernet/broadcom/cnic.c val = (u64) ring_map >> 32; val 4959 drivers/net/ethernet/broadcom/cnic.c txbd->next_bd.addr_hi = cpu_to_le32(val); val 4961 drivers/net/ethernet/broadcom/cnic.c data->tx.tx_bd_page_base.hi = cpu_to_le32(val); val 4963 drivers/net/ethernet/broadcom/cnic.c val = (u64) ring_map & 0xffffffff; val 4964 drivers/net/ethernet/broadcom/cnic.c txbd->next_bd.addr_lo = cpu_to_le32(val); val 4966 drivers/net/ethernet/broadcom/cnic.c data->tx.tx_bd_page_base.lo = cpu_to_le32(val); val 4997 drivers/net/ethernet/broadcom/cnic.c u32 val; val 5016 drivers/net/ethernet/broadcom/cnic.c val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32; val 5017 drivers/net/ethernet/broadcom/cnic.c rxbd->addr_hi = cpu_to_le32(val); val 5018 drivers/net/ethernet/broadcom/cnic.c data->rx.bd_page_base.hi = cpu_to_le32(val); val 5020 drivers/net/ethernet/broadcom/cnic.c val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff; val 5021 drivers/net/ethernet/broadcom/cnic.c rxbd->addr_lo = cpu_to_le32(val); val 5022 drivers/net/ethernet/broadcom/cnic.c data->rx.bd_page_base.lo = cpu_to_le32(val); val 5025 drivers/net/ethernet/broadcom/cnic.c val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) >> 32; val 5026 drivers/net/ethernet/broadcom/cnic.c rxcqe->addr_hi = cpu_to_le32(val); val 5027 drivers/net/ethernet/broadcom/cnic.c data->rx.cqe_page_base.hi = cpu_to_le32(val); val 5029 drivers/net/ethernet/broadcom/cnic.c val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) & 0xffffffff; val 5030 drivers/net/ethernet/broadcom/cnic.c rxcqe->addr_lo = cpu_to_le32(val); val 5031 drivers/net/ethernet/broadcom/cnic.c data->rx.cqe_page_base.lo = cpu_to_le32(val); val 3258 drivers/net/ethernet/broadcom/cnic_defs.h u16 val; val 3542 drivers/net/ethernet/broadcom/cnic_defs.h u16 val; val 353 drivers/net/ethernet/broadcom/cnic_if.h #define CNIC_WR(dev, off, val) writel(val, dev->regview + off) val 354 drivers/net/ethernet/broadcom/cnic_if.h #define CNIC_WR16(dev, off, val) writew(val, dev->regview + off) val 355 drivers/net/ethernet/broadcom/cnic_if.h #define CNIC_WR8(dev, off, val) writeb(val, dev->regview + off) val 121 drivers/net/ethernet/broadcom/genet/bcmgenet.c void __iomem *d, dma_addr_t addr, u32 val) val 124 drivers/net/ethernet/broadcom/genet/bcmgenet.c dmadesc_set_length_status(priv, d, val); val 158 drivers/net/ethernet/broadcom/genet/bcmgenet.c static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) val 161 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); val 163 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); val 179 drivers/net/ethernet/broadcom/genet/bcmgenet.c static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) val 182 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); val 184 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + val 197 drivers/net/ethernet/broadcom/genet/bcmgenet.c static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) val 200 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); val 202 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + val 350 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 val, enum dma_reg r) val 352 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + val 364 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 val, enum dma_reg r) val 366 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + val 443 drivers/net/ethernet/broadcom/genet/bcmgenet.c unsigned int ring, u32 val, val 446 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + val 461 drivers/net/ethernet/broadcom/genet/bcmgenet.c unsigned int ring, u32 val, val 464 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + val 906 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 val; val 915 drivers/net/ethernet/broadcom/genet/bcmgenet.c val = bcmgenet_rbuf_readl(priv, new_offset); val 917 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (val == ~0) val 926 drivers/net/ethernet/broadcom/genet/bcmgenet.c val = bcmgenet_rbuf_readl(priv, new_offset); val 928 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (val == ~0) val 932 drivers/net/ethernet/broadcom/genet/bcmgenet.c val = bcmgenet_umac_readl(priv, offset); val 934 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (val == ~0) val 939 drivers/net/ethernet/broadcom/genet/bcmgenet.c return val; val 949 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 val = 0; val 964 drivers/net/ethernet/broadcom/genet/bcmgenet.c val = bcmgenet_umac_readl(priv, val 970 drivers/net/ethernet/broadcom/genet/bcmgenet.c val = bcmgenet_umac_readl(priv, s->reg_offset); val 972 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (val == ~0) val 976 drivers/net/ethernet/broadcom/genet/bcmgenet.c val = bcmgenet_update_stat_misc(priv, val 984 drivers/net/ethernet/broadcom/genet/bcmgenet.c *(u32 *)p = val; val 696 drivers/net/ethernet/broadcom/genet/bcmgenet.h u32 val, u32 off) \ val 699 drivers/net/ethernet/broadcom/genet/bcmgenet.h __raw_writel(val, priv->base + offset + off); \ val 701 drivers/net/ethernet/broadcom/genet/bcmgenet.h writel_relaxed(val, priv->base + offset + off); \ val 311 drivers/net/ethernet/broadcom/sb1250-mac.c u16 val); val 474 drivers/net/ethernet/broadcom/tg3.c static void tg3_write32(struct tg3 *tp, u32 off, u32 val) val 476 drivers/net/ethernet/broadcom/tg3.c writel(val, tp->regs + off); val 484 drivers/net/ethernet/broadcom/tg3.c static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) val 486 drivers/net/ethernet/broadcom/tg3.c writel(val, tp->aperegs + off); val 494 drivers/net/ethernet/broadcom/tg3.c static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) val 500 drivers/net/ethernet/broadcom/tg3.c pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); val 504 drivers/net/ethernet/broadcom/tg3.c static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) val 506 drivers/net/ethernet/broadcom/tg3.c writel(val, tp->regs + off); val 513 drivers/net/ethernet/broadcom/tg3.c u32 val; val 517 drivers/net/ethernet/broadcom/tg3.c pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); val 519 drivers/net/ethernet/broadcom/tg3.c return val; val 522 drivers/net/ethernet/broadcom/tg3.c static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) val 528 drivers/net/ethernet/broadcom/tg3.c TG3_64BIT_REG_LOW, val); val 533 drivers/net/ethernet/broadcom/tg3.c TG3_64BIT_REG_LOW, val); val 539 drivers/net/ethernet/broadcom/tg3.c pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); val 546 drivers/net/ethernet/broadcom/tg3.c (val == 0x1)) { val 555 drivers/net/ethernet/broadcom/tg3.c u32 val; val 559 drivers/net/ethernet/broadcom/tg3.c pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); val 561 drivers/net/ethernet/broadcom/tg3.c return val; val 569 drivers/net/ethernet/broadcom/tg3.c static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) val 573 drivers/net/ethernet/broadcom/tg3.c tp->write32(tp, off, val); val 576 drivers/net/ethernet/broadcom/tg3.c tg3_write32(tp, off, val); val 588 drivers/net/ethernet/broadcom/tg3.c static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) val 590 drivers/net/ethernet/broadcom/tg3.c tp->write32_mbox(tp, off, val); val 597 drivers/net/ethernet/broadcom/tg3.c static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) val 600 drivers/net/ethernet/broadcom/tg3.c writel(val, mbox); val 602 drivers/net/ethernet/broadcom/tg3.c writel(val, mbox); val 613 drivers/net/ethernet/broadcom/tg3.c static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) val 615 drivers/net/ethernet/broadcom/tg3.c writel(val, tp->regs + off + GRCMBOX_BASE); val 618 drivers/net/ethernet/broadcom/tg3.c #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) val 619 drivers/net/ethernet/broadcom/tg3.c #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) val 620 drivers/net/ethernet/broadcom/tg3.c #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) val 621 drivers/net/ethernet/broadcom/tg3.c #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) val 624 drivers/net/ethernet/broadcom/tg3.c #define tw32(reg, val) tp->write32(tp, reg, val) val 625 drivers/net/ethernet/broadcom/tg3.c #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) val 626 drivers/net/ethernet/broadcom/tg3.c #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) val 629 drivers/net/ethernet/broadcom/tg3.c static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) val 640 drivers/net/ethernet/broadcom/tg3.c pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); val 646 drivers/net/ethernet/broadcom/tg3.c tw32_f(TG3PCI_MEM_WIN_DATA, val); val 654 drivers/net/ethernet/broadcom/tg3.c static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) val 660 drivers/net/ethernet/broadcom/tg3.c *val = 0; val 667 drivers/net/ethernet/broadcom/tg3.c pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); val 673 drivers/net/ethernet/broadcom/tg3.c *val = tr32(TG3PCI_MEM_WIN_DATA); val 904 drivers/net/ethernet/broadcom/tg3.c u32 val = tg3_ape_read32(tp, msgoff + i); val 905 drivers/net/ethernet/broadcom/tg3.c memcpy(data, &val, sizeof(u32)); val 1122 drivers/net/ethernet/broadcom/tg3.c u32 *val) val 1136 drivers/net/ethernet/broadcom/tg3.c *val = 0x0; val 1161 drivers/net/ethernet/broadcom/tg3.c *val = frame_val & MI_COM_DATA_MASK; val 1175 drivers/net/ethernet/broadcom/tg3.c static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) val 1177 drivers/net/ethernet/broadcom/tg3.c return __tg3_readphy(tp, tp->phy_addr, reg, val); val 1181 drivers/net/ethernet/broadcom/tg3.c u32 val) val 1203 drivers/net/ethernet/broadcom/tg3.c frame_val |= (val & MI_COM_DATA_MASK); val 1234 drivers/net/ethernet/broadcom/tg3.c static int tg3_writephy(struct tg3 *tp, int reg, u32 val) val 1236 drivers/net/ethernet/broadcom/tg3.c return __tg3_writephy(tp, tp->phy_addr, reg, val); val 1239 drivers/net/ethernet/broadcom/tg3.c static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) val 1256 drivers/net/ethernet/broadcom/tg3.c err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); val 1262 drivers/net/ethernet/broadcom/tg3.c static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) val 1279 drivers/net/ethernet/broadcom/tg3.c err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); val 1285 drivers/net/ethernet/broadcom/tg3.c static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) val 1291 drivers/net/ethernet/broadcom/tg3.c err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); val 1296 drivers/net/ethernet/broadcom/tg3.c static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) val 1302 drivers/net/ethernet/broadcom/tg3.c err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); val 1307 drivers/net/ethernet/broadcom/tg3.c static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) val 1315 drivers/net/ethernet/broadcom/tg3.c err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); val 1330 drivers/net/ethernet/broadcom/tg3.c u32 val; val 1333 drivers/net/ethernet/broadcom/tg3.c err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); val 1339 drivers/net/ethernet/broadcom/tg3.c val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA; val 1341 drivers/net/ethernet/broadcom/tg3.c val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA; val 1344 drivers/net/ethernet/broadcom/tg3.c val | MII_TG3_AUXCTL_ACTL_TX_6DB); val 1349 drivers/net/ethernet/broadcom/tg3.c static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) val 1352 drivers/net/ethernet/broadcom/tg3.c reg | val | MII_TG3_MISC_SHDW_WREN); val 1389 drivers/net/ethernet/broadcom/tg3.c u32 val; val 1393 drivers/net/ethernet/broadcom/tg3.c if (__tg3_readphy(tp, mii_id, reg, &val)) val 1394 drivers/net/ethernet/broadcom/tg3.c val = -EIO; val 1398 drivers/net/ethernet/broadcom/tg3.c return val; val 1401 drivers/net/ethernet/broadcom/tg3.c static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) val 1408 drivers/net/ethernet/broadcom/tg3.c if (__tg3_writephy(tp, mii_id, reg, val)) val 1418 drivers/net/ethernet/broadcom/tg3.c u32 val; val 1425 drivers/net/ethernet/broadcom/tg3.c val = MAC_PHYCFG2_50610_LED_MODES; val 1428 drivers/net/ethernet/broadcom/tg3.c val = MAC_PHYCFG2_AC131_LED_MODES; val 1431 drivers/net/ethernet/broadcom/tg3.c val = MAC_PHYCFG2_RTL8211C_LED_MODES; val 1434 drivers/net/ethernet/broadcom/tg3.c val = MAC_PHYCFG2_RTL8201E_LED_MODES; val 1441 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_PHYCFG2, val); val 1443 drivers/net/ethernet/broadcom/tg3.c val = tr32(MAC_PHYCFG1); val 1444 drivers/net/ethernet/broadcom/tg3.c val &= ~(MAC_PHYCFG1_RGMII_INT | val 1446 drivers/net/ethernet/broadcom/tg3.c val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; val 1447 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_PHYCFG1, val); val 1453 drivers/net/ethernet/broadcom/tg3.c val |= MAC_PHYCFG2_EMODE_MASK_MASK | val 1460 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_PHYCFG2, val); val 1462 drivers/net/ethernet/broadcom/tg3.c val = tr32(MAC_PHYCFG1); val 1463 drivers/net/ethernet/broadcom/tg3.c val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | val 1467 drivers/net/ethernet/broadcom/tg3.c val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; val 1469 drivers/net/ethernet/broadcom/tg3.c val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; val 1471 drivers/net/ethernet/broadcom/tg3.c val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | val 1473 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_PHYCFG1, val); val 1475 drivers/net/ethernet/broadcom/tg3.c val = tr32(MAC_EXT_RGMII_MODE); val 1476 drivers/net/ethernet/broadcom/tg3.c val &= ~(MAC_RGMII_MODE_RX_INT_B | val 1485 drivers/net/ethernet/broadcom/tg3.c val |= MAC_RGMII_MODE_RX_INT_B | val 1490 drivers/net/ethernet/broadcom/tg3.c val |= MAC_RGMII_MODE_TX_ENABLE | val 1494 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_EXT_RGMII_MODE, val); val 1627 drivers/net/ethernet/broadcom/tg3.c u32 val; val 1629 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_RX_CPU_EVENT); val 1630 drivers/net/ethernet/broadcom/tg3.c val |= GRC_RX_CPU_DRIVER_EVENT; val 1631 drivers/net/ethernet/broadcom/tg3.c tw32_f(GRC_RX_CPU_EVENT, val); val 1671 drivers/net/ethernet/broadcom/tg3.c u32 reg, val; val 1673 drivers/net/ethernet/broadcom/tg3.c val = 0; val 1675 drivers/net/ethernet/broadcom/tg3.c val = reg << 16; val 1677 drivers/net/ethernet/broadcom/tg3.c val |= (reg & 0xffff); val 1678 drivers/net/ethernet/broadcom/tg3.c *data++ = val; val 1680 drivers/net/ethernet/broadcom/tg3.c val = 0; val 1682 drivers/net/ethernet/broadcom/tg3.c val = reg << 16; val 1684 drivers/net/ethernet/broadcom/tg3.c val |= (reg & 0xffff); val 1685 drivers/net/ethernet/broadcom/tg3.c *data++ = val; val 1687 drivers/net/ethernet/broadcom/tg3.c val = 0; val 1690 drivers/net/ethernet/broadcom/tg3.c val = reg << 16; val 1692 drivers/net/ethernet/broadcom/tg3.c val |= (reg & 0xffff); val 1694 drivers/net/ethernet/broadcom/tg3.c *data++ = val; val 1697 drivers/net/ethernet/broadcom/tg3.c val = reg << 16; val 1699 drivers/net/ethernet/broadcom/tg3.c val = 0; val 1700 drivers/net/ethernet/broadcom/tg3.c *data++ = val; val 1820 drivers/net/ethernet/broadcom/tg3.c u32 val; val 1845 drivers/net/ethernet/broadcom/tg3.c tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); val 1846 drivers/net/ethernet/broadcom/tg3.c if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) val 2182 drivers/net/ethernet/broadcom/tg3.c u32 val; val 2197 drivers/net/ethernet/broadcom/tg3.c MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); val 2201 drivers/net/ethernet/broadcom/tg3.c val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK; val 2203 drivers/net/ethernet/broadcom/tg3.c MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val); val 2304 drivers/net/ethernet/broadcom/tg3.c u32 val; val 2309 drivers/net/ethernet/broadcom/tg3.c ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); val 2312 drivers/net/ethernet/broadcom/tg3.c val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); val 2354 drivers/net/ethernet/broadcom/tg3.c u32 val; val 2363 drivers/net/ethernet/broadcom/tg3.c if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val)) val 2367 drivers/net/ethernet/broadcom/tg3.c if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || val 2368 drivers/net/ethernet/broadcom/tg3.c val == TG3_CL45_D7_EEERES_STAT_LP_100TX) { val 2374 drivers/net/ethernet/broadcom/tg3.c if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val)) val 2376 drivers/net/ethernet/broadcom/tg3.c dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); val 2379 drivers/net/ethernet/broadcom/tg3.c if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val)) val 2381 drivers/net/ethernet/broadcom/tg3.c dest->eee_enabled = !!val; val 2382 drivers/net/ethernet/broadcom/tg3.c dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val); val 2385 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_EEE_MODE); val 2386 drivers/net/ethernet/broadcom/tg3.c dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); val 2394 drivers/net/ethernet/broadcom/tg3.c u32 val; val 2427 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_EEE_MODE); val 2428 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); val 2434 drivers/net/ethernet/broadcom/tg3.c u32 val; val 2441 drivers/net/ethernet/broadcom/tg3.c val = MII_TG3_DSP_TAP26_ALNOKO | val 2443 drivers/net/ethernet/broadcom/tg3.c tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); val 2447 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_EEE_MODE); val 2448 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); val 2641 drivers/net/ethernet/broadcom/tg3.c u32 val, cpmuctrl; val 2645 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_MISC_CFG); val 2646 drivers/net/ethernet/broadcom/tg3.c tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); val 2649 drivers/net/ethernet/broadcom/tg3.c err = tg3_readphy(tp, MII_BMSR, &val); val 2650 drivers/net/ethernet/broadcom/tg3.c err |= tg3_readphy(tp, MII_BMSR, &val); val 2682 drivers/net/ethernet/broadcom/tg3.c val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; val 2683 drivers/net/ethernet/broadcom/tg3.c tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); val 2690 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_LSPD_1000MB_CLK); val 2691 drivers/net/ethernet/broadcom/tg3.c if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == val 2693 drivers/net/ethernet/broadcom/tg3.c val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; val 2695 drivers/net/ethernet/broadcom/tg3.c tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); val 2752 drivers/net/ethernet/broadcom/tg3.c MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); val 2755 drivers/net/ethernet/broadcom/tg3.c val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); val 2762 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) val 2764 drivers/net/ethernet/broadcom/tg3.c val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); val 3068 drivers/net/ethernet/broadcom/tg3.c u32 val; val 3088 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_MISC_CFG); val 3089 drivers/net/ethernet/broadcom/tg3.c tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); val 3117 drivers/net/ethernet/broadcom/tg3.c val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | val 3120 drivers/net/ethernet/broadcom/tg3.c tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); val 3131 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_LSPD_1000MB_CLK); val 3132 drivers/net/ethernet/broadcom/tg3.c val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; val 3133 drivers/net/ethernet/broadcom/tg3.c val |= CPMU_LSPD_1000MB_MACCLK_12_5; val 3134 drivers/net/ethernet/broadcom/tg3.c tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); val 3195 drivers/net/ethernet/broadcom/tg3.c u32 offset, u32 *val) val 3229 drivers/net/ethernet/broadcom/tg3.c *val = swab32(tmp); val 3291 drivers/net/ethernet/broadcom/tg3.c static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) val 3296 drivers/net/ethernet/broadcom/tg3.c return tg3_nvram_read_using_eeprom(tp, offset, val); val 3314 drivers/net/ethernet/broadcom/tg3.c *val = tr32(NVRAM_RDDATA); val 3324 drivers/net/ethernet/broadcom/tg3.c static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) val 3329 drivers/net/ethernet/broadcom/tg3.c *val = cpu_to_be32(v); val 3337 drivers/net/ethernet/broadcom/tg3.c u32 val; val 3355 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_EEPROM_ADDR); val 3356 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); val 3358 drivers/net/ethernet/broadcom/tg3.c val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | val 3360 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_EEPROM_ADDR, val | val 3367 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_EEPROM_ADDR); val 3369 drivers/net/ethernet/broadcom/tg3.c if (val & EEPROM_ADDR_COMPLETE) val 3373 drivers/net/ethernet/broadcom/tg3.c if (!(val & EEPROM_ADDR_COMPLETE)) { val 3648 drivers/net/ethernet/broadcom/tg3.c u32 val = tr32(GRC_VCPU_EXT_CTRL); val 3650 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); val 3838 drivers/net/ethernet/broadcom/tg3.c u32 val; val 3855 drivers/net/ethernet/broadcom/tg3.c val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); val 3856 drivers/net/ethernet/broadcom/tg3.c if (val & 0xff) { val 4115 drivers/net/ethernet/broadcom/tg3.c u32 val; val 4117 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_VCPU_EXT_CTRL); val 4118 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); val 4121 drivers/net/ethernet/broadcom/tg3.c u32 val; val 4124 drivers/net/ethernet/broadcom/tg3.c tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); val 4125 drivers/net/ethernet/broadcom/tg3.c if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) val 4258 drivers/net/ethernet/broadcom/tg3.c u32 val = tr32(0x7d00); val 4260 drivers/net/ethernet/broadcom/tg3.c val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); val 4261 drivers/net/ethernet/broadcom/tg3.c tw32(0x7d00, val); val 4285 drivers/net/ethernet/broadcom/tg3.c static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) val 4287 drivers/net/ethernet/broadcom/tg3.c switch (val & MII_TG3_AUX_STAT_SPDMASK) { val 4320 drivers/net/ethernet/broadcom/tg3.c *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : val 4322 drivers/net/ethernet/broadcom/tg3.c *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : val 4335 drivers/net/ethernet/broadcom/tg3.c u32 val, new_adv; val 4367 drivers/net/ethernet/broadcom/tg3.c val = 0; val 4370 drivers/net/ethernet/broadcom/tg3.c val |= MDIO_AN_EEE_ADV_100TX; val 4373 drivers/net/ethernet/broadcom/tg3.c val |= MDIO_AN_EEE_ADV_1000T; val 4376 drivers/net/ethernet/broadcom/tg3.c val = 0; val 4384 drivers/net/ethernet/broadcom/tg3.c err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); val 4386 drivers/net/ethernet/broadcom/tg3.c val = 0; val 4394 drivers/net/ethernet/broadcom/tg3.c if (val) val 4395 drivers/net/ethernet/broadcom/tg3.c val = MII_TG3_DSP_TAP26_ALNOKO | val 4398 drivers/net/ethernet/broadcom/tg3.c tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); val 4402 drivers/net/ethernet/broadcom/tg3.c if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) val 4403 drivers/net/ethernet/broadcom/tg3.c tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | val 4516 drivers/net/ethernet/broadcom/tg3.c u32 val; val 4518 drivers/net/ethernet/broadcom/tg3.c err = tg3_readphy(tp, MII_BMCR, &val); val 4522 drivers/net/ethernet/broadcom/tg3.c if (!(val & BMCR_ANENABLE)) { val 4529 drivers/net/ethernet/broadcom/tg3.c switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) { val 4552 drivers/net/ethernet/broadcom/tg3.c if (val & BMCR_FULLDPLX) val 4570 drivers/net/ethernet/broadcom/tg3.c err = tg3_readphy(tp, MII_ADVERTISE, &val); val 4574 drivers/net/ethernet/broadcom/tg3.c adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL); val 4577 drivers/net/ethernet/broadcom/tg3.c tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); val 4586 drivers/net/ethernet/broadcom/tg3.c err = tg3_readphy(tp, MII_CTRL1000, &val); val 4590 drivers/net/ethernet/broadcom/tg3.c adv = mii_ctrl1000_to_ethtool_adv_t(val); val 4592 drivers/net/ethernet/broadcom/tg3.c err = tg3_readphy(tp, MII_ADVERTISE, &val); val 4596 drivers/net/ethernet/broadcom/tg3.c adv = tg3_decode_flowctrl_1000X(val); val 4599 drivers/net/ethernet/broadcom/tg3.c val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL); val 4600 drivers/net/ethernet/broadcom/tg3.c adv = mii_adv_to_ethtool_adv_x(val); val 4701 drivers/net/ethernet/broadcom/tg3.c u32 val; val 4703 drivers/net/ethernet/broadcom/tg3.c if (tg3_readphy(tp, MII_STAT1000, &val)) val 4706 drivers/net/ethernet/broadcom/tg3.c lpeth = mii_stat1000_to_ethtool_lpa_t(val); val 4750 drivers/net/ethernet/broadcom/tg3.c u32 val; val 4752 drivers/net/ethernet/broadcom/tg3.c val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | val 4755 drivers/net/ethernet/broadcom/tg3.c val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT; val 4757 drivers/net/ethernet/broadcom/tg3.c tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val); val 4762 drivers/net/ethernet/broadcom/tg3.c val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | val 4768 drivers/net/ethernet/broadcom/tg3.c val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; val 4771 drivers/net/ethernet/broadcom/tg3.c val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; val 4773 drivers/net/ethernet/broadcom/tg3.c tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); val 4787 drivers/net/ethernet/broadcom/tg3.c u32 bmsr, val; val 4860 drivers/net/ethernet/broadcom/tg3.c tg3_readphy(tp, MII_TG3_ISTAT, &val); val 4861 drivers/net/ethernet/broadcom/tg3.c tg3_readphy(tp, MII_TG3_ISTAT, &val); val 4886 drivers/net/ethernet/broadcom/tg3.c &val); val 4887 drivers/net/ethernet/broadcom/tg3.c if (!err && !(val & (1 << 10))) { val 4890 drivers/net/ethernet/broadcom/tg3.c val | (1 << 10)); val 4974 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, reg, &val) && (val & bit)) val 5538 drivers/net/ethernet/broadcom/tg3.c u32 val = serdes_cfg; val 5541 drivers/net/ethernet/broadcom/tg3.c val |= 0xc010000; val 5543 drivers/net/ethernet/broadcom/tg3.c val |= 0x4010000; val 5544 drivers/net/ethernet/broadcom/tg3.c tw32_f(MAC_SERDES_CFG, val); val 5615 drivers/net/ethernet/broadcom/tg3.c u32 val = serdes_cfg; val 5618 drivers/net/ethernet/broadcom/tg3.c val |= 0xc010000; val 5620 drivers/net/ethernet/broadcom/tg3.c val |= 0x4010000; val 5622 drivers/net/ethernet/broadcom/tg3.c tw32_f(MAC_SERDES_CFG, val); val 6077 drivers/net/ethernet/broadcom/tg3.c u32 val; val 6090 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; val 6091 drivers/net/ethernet/broadcom/tg3.c if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) val 6093 drivers/net/ethernet/broadcom/tg3.c else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) val 6098 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; val 6099 drivers/net/ethernet/broadcom/tg3.c val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); val 6100 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_MISC_CFG, val); val 6103 drivers/net/ethernet/broadcom/tg3.c val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | val 6107 drivers/net/ethernet/broadcom/tg3.c val |= tr32(MAC_TX_LENGTHS) & val 6113 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_TX_LENGTHS, val | val 6116 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_TX_LENGTHS, val | val 6129 drivers/net/ethernet/broadcom/tg3.c val = tr32(PCIE_PWR_MGMT_THRESH); val 6131 drivers/net/ethernet/broadcom/tg3.c val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | val 6134 drivers/net/ethernet/broadcom/tg3.c val |= PCIE_PWR_MGMT_L1_THRESH_MSK; val 6135 drivers/net/ethernet/broadcom/tg3.c tw32(PCIE_PWR_MGMT_THRESH, val); val 7297 drivers/net/ethernet/broadcom/tg3.c u32 val; val 7304 drivers/net/ethernet/broadcom/tg3.c val = tr32(HOSTCC_FLOW_ATTN); val 7305 drivers/net/ethernet/broadcom/tg3.c if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { val 8205 drivers/net/ethernet/broadcom/tg3.c u32 val, bmcr, mac_mode, ptest = 0; val 8233 drivers/net/ethernet/broadcom/tg3.c tg3_readphy(tp, MII_CTRL1000, &val); val 8234 drivers/net/ethernet/broadcom/tg3.c val |= CTL1000_AS_MASTER | val 8236 drivers/net/ethernet/broadcom/tg3.c tg3_writephy(tp, MII_CTRL1000, val); val 8260 drivers/net/ethernet/broadcom/tg3.c tg3_readphy(tp, MII_TG3_FET_PTEST, &val); val 8835 drivers/net/ethernet/broadcom/tg3.c u32 val; val 8854 drivers/net/ethernet/broadcom/tg3.c val = tr32(ofs); val 8855 drivers/net/ethernet/broadcom/tg3.c val &= ~enable_bit; val 8856 drivers/net/ethernet/broadcom/tg3.c tw32_f(ofs, val); val 8868 drivers/net/ethernet/broadcom/tg3.c val = tr32(ofs); val 8869 drivers/net/ethernet/broadcom/tg3.c if ((val & enable_bit) == 0) val 8964 drivers/net/ethernet/broadcom/tg3.c u32 val; val 8971 drivers/net/ethernet/broadcom/tg3.c val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); val 8974 drivers/net/ethernet/broadcom/tg3.c val |= PCISTATE_RETRY_SAME_DMA; val 8977 drivers/net/ethernet/broadcom/tg3.c val |= PCISTATE_ALLOW_APE_CTLSPC_WR | val 8980 drivers/net/ethernet/broadcom/tg3.c pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); val 9016 drivers/net/ethernet/broadcom/tg3.c val = tr32(MSGINT_MODE); val 9017 drivers/net/ethernet/broadcom/tg3.c tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); val 9024 drivers/net/ethernet/broadcom/tg3.c u32 val; val 9028 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); val 9029 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val | val 9045 drivers/net/ethernet/broadcom/tg3.c u32 val; val 9049 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); val 9051 drivers/net/ethernet/broadcom/tg3.c val & ~TG3_CPMU_MAC_ORIDE_ENABLE); val 9056 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_CLCK_ORIDE); val 9057 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); val 9070 drivers/net/ethernet/broadcom/tg3.c u32 val; val 9132 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; val 9133 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); val 9137 drivers/net/ethernet/broadcom/tg3.c val = GRC_MISC_CFG_CORECLK_RESET; val 9149 drivers/net/ethernet/broadcom/tg3.c val |= (1 << 29); val 9168 drivers/net/ethernet/broadcom/tg3.c val |= GRC_MISC_CFG_KEEP_GPHY_POWER; val 9170 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_MISC_CFG, val); val 9196 drivers/net/ethernet/broadcom/tg3.c pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); val 9239 drivers/net/ethernet/broadcom/tg3.c val = 0; val 9241 drivers/net/ethernet/broadcom/tg3.c val = tr32(MEMARB_MODE); val 9242 drivers/net/ethernet/broadcom/tg3.c tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); val 9266 drivers/net/ethernet/broadcom/tg3.c val = tr32(0xc4); val 9268 drivers/net/ethernet/broadcom/tg3.c tw32(0xc4, val | (1 << 15)); val 9281 drivers/net/ethernet/broadcom/tg3.c val = tp->mac_mode; val 9284 drivers/net/ethernet/broadcom/tg3.c val = tp->mac_mode; val 9286 drivers/net/ethernet/broadcom/tg3.c val = 0; val 9288 drivers/net/ethernet/broadcom/tg3.c tw32_f(MAC_MODE, val); val 9299 drivers/net/ethernet/broadcom/tg3.c val = tr32(0x7c00); val 9301 drivers/net/ethernet/broadcom/tg3.c tw32(0x7c00, val | (1 << 25)); val 9310 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); val 9311 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val | val 9321 drivers/net/ethernet/broadcom/tg3.c tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); val 9322 drivers/net/ethernet/broadcom/tg3.c if (val == NIC_SRAM_DATA_SIG_MAGIC) { val 9506 drivers/net/ethernet/broadcom/tg3.c u32 val = ec->stats_block_coalesce_usecs; val 9512 drivers/net/ethernet/broadcom/tg3.c val = 0; val 9514 drivers/net/ethernet/broadcom/tg3.c tw32(HOSTCC_STAT_COAL_TICKS, val); val 9678 drivers/net/ethernet/broadcom/tg3.c u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; val 9695 drivers/net/ethernet/broadcom/tg3.c val = min(nic_rep_thresh, host_rep_thresh); val 9696 drivers/net/ethernet/broadcom/tg3.c tw32(RCVBDI_STD_THRESH, val); val 9708 drivers/net/ethernet/broadcom/tg3.c val = min(bdcache_maxcnt / 2, host_rep_thresh); val 9709 drivers/net/ethernet/broadcom/tg3.c tw32(RCVBDI_JUMBO_THRESH, val); val 9852 drivers/net/ethernet/broadcom/tg3.c u32 val = tp->rss_ind_tbl[i]; val 9855 drivers/net/ethernet/broadcom/tg3.c val <<= 4; val 9856 drivers/net/ethernet/broadcom/tg3.c val |= tp->rss_ind_tbl[i]; val 9858 drivers/net/ethernet/broadcom/tg3.c tw32(reg, val); val 9874 drivers/net/ethernet/broadcom/tg3.c u32 val, rdmac_mode; val 9908 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_CTRL); val 9909 drivers/net/ethernet/broadcom/tg3.c val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); val 9910 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_CTRL, val); val 9912 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_LSPD_10MB_CLK); val 9913 drivers/net/ethernet/broadcom/tg3.c val &= ~CPMU_LSPD_10MB_MACCLK_MASK; val 9914 drivers/net/ethernet/broadcom/tg3.c val |= CPMU_LSPD_10MB_MACCLK_6_25; val 9915 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_LSPD_10MB_CLK, val); val 9917 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); val 9918 drivers/net/ethernet/broadcom/tg3.c val &= ~CPMU_LNK_AWARE_MACCLK_MASK; val 9919 drivers/net/ethernet/broadcom/tg3.c val |= CPMU_LNK_AWARE_MACCLK_6_25; val 9920 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); val 9922 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_HST_ACC); val 9923 drivers/net/ethernet/broadcom/tg3.c val &= ~CPMU_HST_ACC_MACCLK_MASK; val 9924 drivers/net/ethernet/broadcom/tg3.c val |= CPMU_HST_ACC_MACCLK_6_25; val 9925 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_HST_ACC, val); val 9929 drivers/net/ethernet/broadcom/tg3.c val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; val 9930 drivers/net/ethernet/broadcom/tg3.c val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | val 9932 drivers/net/ethernet/broadcom/tg3.c tw32(PCIE_PWR_MGMT_THRESH, val); val 9934 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; val 9935 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); val 9939 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; val 9940 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); val 9947 drivers/net/ethernet/broadcom/tg3.c val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; val 9948 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); val 9950 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); val 9952 drivers/net/ethernet/broadcom/tg3.c val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); val 9962 drivers/net/ethernet/broadcom/tg3.c val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; val 9963 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); val 9965 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_PCIE_TLDLPL_PORT + val 9968 drivers/net/ethernet/broadcom/tg3.c val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); val 9977 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_PADRNG_CTL); val 9978 drivers/net/ethernet/broadcom/tg3.c val |= TG3_CPMU_PADRNG_CTL_RDIV2; val 9979 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_PADRNG_CTL, val); val 9984 drivers/net/ethernet/broadcom/tg3.c val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; val 9985 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); val 9987 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_PCIE_TLDLPL_PORT + val 9989 drivers/net/ethernet/broadcom/tg3.c val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; val 9991 drivers/net/ethernet/broadcom/tg3.c val | TG3_PCIE_DL_LO_FTSMAX_VAL); val 9996 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_LSPD_10MB_CLK); val 9997 drivers/net/ethernet/broadcom/tg3.c val &= ~CPMU_LSPD_10MB_MACCLK_MASK; val 9998 drivers/net/ethernet/broadcom/tg3.c val |= CPMU_LSPD_10MB_MACCLK_6_25; val 9999 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_CPMU_LSPD_10MB_CLK, val); val 10015 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3PCI_PCISTATE); val 10016 drivers/net/ethernet/broadcom/tg3.c val |= PCISTATE_RETRY_SAME_DMA; val 10017 drivers/net/ethernet/broadcom/tg3.c tw32(TG3PCI_PCISTATE, val); val 10024 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3PCI_PCISTATE); val 10025 drivers/net/ethernet/broadcom/tg3.c val |= PCISTATE_ALLOW_APE_CTLSPC_WR | val 10028 drivers/net/ethernet/broadcom/tg3.c tw32(TG3PCI_PCISTATE, val); val 10033 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3PCI_MSI_DATA); val 10034 drivers/net/ethernet/broadcom/tg3.c val |= (1 << 26) | (1 << 28) | (1 << 29); val 10035 drivers/net/ethernet/broadcom/tg3.c tw32(TG3PCI_MSI_DATA, val); val 10048 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3PCI_DMA_RW_CTRL) & val 10051 drivers/net/ethernet/broadcom/tg3.c val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; val 10055 drivers/net/ethernet/broadcom/tg3.c val |= DMA_RWCTRL_TAGGED_STAT_WA; val 10056 drivers/net/ethernet/broadcom/tg3.c tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); val 10079 drivers/net/ethernet/broadcom/tg3.c val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP; val 10085 drivers/net/ethernet/broadcom/tg3.c val |= GRC_MODE_TIME_SYNC_ENABLE; val 10087 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_MODE, tp->grc_mode | val); val 10095 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK; val 10096 drivers/net/ethernet/broadcom/tg3.c tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048); val 10100 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_MISC_CFG); val 10101 drivers/net/ethernet/broadcom/tg3.c val &= ~0xff; val 10102 drivers/net/ethernet/broadcom/tg3.c val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); val 10103 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_MISC_CFG, val); val 10147 drivers/net/ethernet/broadcom/tg3.c val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; val 10149 drivers/net/ethernet/broadcom/tg3.c val |= BUFMGR_MODE_NO_TX_UNDERRUN; val 10154 drivers/net/ethernet/broadcom/tg3.c val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; val 10155 drivers/net/ethernet/broadcom/tg3.c tw32(BUFMGR_MODE, val); val 10212 drivers/net/ethernet/broadcom/tg3.c val = TG3_RX_JMB_RING_SIZE(tp) << val 10215 drivers/net/ethernet/broadcom/tg3.c val | BDINFO_FLAGS_USE_EXT_RECV); val 10227 drivers/net/ethernet/broadcom/tg3.c val = TG3_RX_STD_RING_SIZE(tp); val 10228 drivers/net/ethernet/broadcom/tg3.c val <<= BDINFO_FLAGS_MAXLEN_SHIFT; val 10229 drivers/net/ethernet/broadcom/tg3.c val |= (TG3_RX_STD_DMA_SZ << 2); val 10231 drivers/net/ethernet/broadcom/tg3.c val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; val 10233 drivers/net/ethernet/broadcom/tg3.c val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; val 10235 drivers/net/ethernet/broadcom/tg3.c tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); val 10256 drivers/net/ethernet/broadcom/tg3.c val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | val 10262 drivers/net/ethernet/broadcom/tg3.c val |= tr32(MAC_TX_LENGTHS) & val 10266 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_TX_LENGTHS, val); val 10339 drivers/net/ethernet/broadcom/tg3.c val = tr32(tgtreg); val 10342 drivers/net/ethernet/broadcom/tg3.c val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | val 10345 drivers/net/ethernet/broadcom/tg3.c val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | val 10349 drivers/net/ethernet/broadcom/tg3.c tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); val 10362 drivers/net/ethernet/broadcom/tg3.c val = tr32(tgtreg); val 10363 drivers/net/ethernet/broadcom/tg3.c tw32(tgtreg, val | val 10370 drivers/net/ethernet/broadcom/tg3.c val = tr32(RCVLPC_STATS_ENABLE); val 10371 drivers/net/ethernet/broadcom/tg3.c val &= ~RCVLPC_STATSENAB_DACK_FIX; val 10372 drivers/net/ethernet/broadcom/tg3.c tw32(RCVLPC_STATS_ENABLE, val); val 10375 drivers/net/ethernet/broadcom/tg3.c val = tr32(RCVLPC_STATS_ENABLE); val 10376 drivers/net/ethernet/broadcom/tg3.c val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; val 10377 drivers/net/ethernet/broadcom/tg3.c tw32(RCVLPC_STATS_ENABLE, val); val 10477 drivers/net/ethernet/broadcom/tg3.c val = tr32(MSGINT_MODE); val 10478 drivers/net/ethernet/broadcom/tg3.c val |= MSGINT_MODE_ENABLE; val 10480 drivers/net/ethernet/broadcom/tg3.c val |= MSGINT_MODE_MULTIVEC_EN; val 10482 drivers/net/ethernet/broadcom/tg3.c val |= MSGINT_MODE_ONE_SHOT_DISABLE; val 10483 drivers/net/ethernet/broadcom/tg3.c tw32(MSGINT_MODE, val); val 10491 drivers/net/ethernet/broadcom/tg3.c val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | val 10505 drivers/net/ethernet/broadcom/tg3.c val |= WDMAC_MODE_RX_ACCEL; val 10511 drivers/net/ethernet/broadcom/tg3.c val |= WDMAC_MODE_STATUS_TAG_FIX; val 10514 drivers/net/ethernet/broadcom/tg3.c val |= WDMAC_MODE_BURST_ALL_DATA; val 10516 drivers/net/ethernet/broadcom/tg3.c tw32_f(WDMAC_MODE, val); val 10545 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); val 10546 drivers/net/ethernet/broadcom/tg3.c val |= tg3_lso_rd_dma_workaround_bit(tp); val 10547 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); val 10564 drivers/net/ethernet/broadcom/tg3.c val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; val 10566 drivers/net/ethernet/broadcom/tg3.c val |= RCVDBDI_MODE_LRG_RING_SZ; val 10567 drivers/net/ethernet/broadcom/tg3.c tw32(RCVDBDI_MODE, val); val 10573 drivers/net/ethernet/broadcom/tg3.c val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; val 10575 drivers/net/ethernet/broadcom/tg3.c val |= SNDBDI_MODE_MULTI_TXQ_EN; val 10576 drivers/net/ethernet/broadcom/tg3.c tw32(SNDBDI_MODE, val); val 10606 drivers/net/ethernet/broadcom/tg3.c val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; val 10607 drivers/net/ethernet/broadcom/tg3.c tp->tx_mode &= ~val; val 10608 drivers/net/ethernet/broadcom/tg3.c tp->tx_mode |= tr32(MAC_TX_MODE) & val; val 10658 drivers/net/ethernet/broadcom/tg3.c val = tr32(MAC_SERDES_CFG); val 10659 drivers/net/ethernet/broadcom/tg3.c val &= 0xfffff000; val 10660 drivers/net/ethernet/broadcom/tg3.c val |= 0x880; val 10661 drivers/net/ethernet/broadcom/tg3.c tw32(MAC_SERDES_CFG, val); val 10671 drivers/net/ethernet/broadcom/tg3.c val = 1; val 10673 drivers/net/ethernet/broadcom/tg3.c val = 2; val 10674 drivers/net/ethernet/broadcom/tg3.c tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); val 10924 drivers/net/ethernet/broadcom/tg3.c u32 val; val 10926 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); val 10927 drivers/net/ethernet/broadcom/tg3.c val &= ~tg3_lso_rd_dma_workaround_bit(tp); val 10928 drivers/net/ethernet/broadcom/tg3.c tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); val 10954 drivers/net/ethernet/broadcom/tg3.c u32 val = tr32(HOSTCC_FLOW_ATTN); val 10955 drivers/net/ethernet/broadcom/tg3.c val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; val 10956 drivers/net/ethernet/broadcom/tg3.c if (val) { val 10958 drivers/net/ethernet/broadcom/tg3.c sp->rx_discards.low += val; val 10959 drivers/net/ethernet/broadcom/tg3.c if (sp->rx_discards.low < val) val 11283 drivers/net/ethernet/broadcom/tg3.c u32 val; val 11297 drivers/net/ethernet/broadcom/tg3.c val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; val 11298 drivers/net/ethernet/broadcom/tg3.c tw32(MSGINT_MODE, val); val 11343 drivers/net/ethernet/broadcom/tg3.c val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; val 11344 drivers/net/ethernet/broadcom/tg3.c tw32(MSGINT_MODE, val); val 11636 drivers/net/ethernet/broadcom/tg3.c u32 val = tr32(PCIE_TRANSACTION_CFG); val 11639 drivers/net/ethernet/broadcom/tg3.c val | PCIE_TRANS_CFG_1SHOT_MSI); val 11797 drivers/net/ethernet/broadcom/tg3.c static inline u64 get_stat64(tg3_stat64_t *val) val 11799 drivers/net/ethernet/broadcom/tg3.c return ((u64)val->high << 32) | ((u64)val->low); val 11809 drivers/net/ethernet/broadcom/tg3.c u32 val; val 11811 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { val 11813 drivers/net/ethernet/broadcom/tg3.c val | MII_TG3_TEST1_CRC_EN); val 11814 drivers/net/ethernet/broadcom/tg3.c tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); val 11816 drivers/net/ethernet/broadcom/tg3.c val = 0; val 11818 drivers/net/ethernet/broadcom/tg3.c tp->phy_crc_errors += val; val 12005 drivers/net/ethernet/broadcom/tg3.c __be32 val; val 12037 drivers/net/ethernet/broadcom/tg3.c ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); val 12040 drivers/net/ethernet/broadcom/tg3.c memcpy(data, ((char *)&val) + b_offset, b_count); val 12049 drivers/net/ethernet/broadcom/tg3.c ret = tg3_nvram_read_be32(tp, offset + i, &val); val 12056 drivers/net/ethernet/broadcom/tg3.c memcpy(pd + i, &val, 4); val 12073 drivers/net/ethernet/broadcom/tg3.c ret = tg3_nvram_read_be32(tp, b_offset, &val); val 12076 drivers/net/ethernet/broadcom/tg3.c memcpy(pd, &val, b_count); val 12807 drivers/net/ethernet/broadcom/tg3.c u32 magic, val; val 12816 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, offset, &val)) val 12819 drivers/net/ethernet/broadcom/tg3.c if ((val >> TG3_NVM_DIRTYPE_SHIFT) == val 12825 drivers/net/ethernet/broadcom/tg3.c len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; val 13097 drivers/net/ethernet/broadcom/tg3.c u32 offset, read_mask, write_mask, val, save_val, read_val; val 13279 drivers/net/ethernet/broadcom/tg3.c val = tr32(offset); val 13282 drivers/net/ethernet/broadcom/tg3.c if (((val & read_mask) != read_val) || (val & write_mask)) val 13291 drivers/net/ethernet/broadcom/tg3.c val = tr32(offset); val 13294 drivers/net/ethernet/broadcom/tg3.c if ((val & read_mask) != read_val) val 13298 drivers/net/ethernet/broadcom/tg3.c if ((val & write_mask) != write_mask) val 13322 drivers/net/ethernet/broadcom/tg3.c u32 val; val 13325 drivers/net/ethernet/broadcom/tg3.c tg3_read_mem(tp, offset + j, &val); val 13326 drivers/net/ethernet/broadcom/tg3.c if (val != test_pattern[i]) val 13429 drivers/net/ethernet/broadcom/tg3.c u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; val 13472 drivers/net/ethernet/broadcom/tg3.c val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); val 13473 drivers/net/ethernet/broadcom/tg3.c num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); val 13485 drivers/net/ethernet/broadcom/tg3.c val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; val 13486 drivers/net/ethernet/broadcom/tg3.c th = (struct tcphdr *)&tx_data[val]; val 13524 drivers/net/ethernet/broadcom/tg3.c val = tnapi->tx_prod; val 13525 drivers/net/ethernet/broadcom/tg3.c tnapi->tx_buffers[val].skb = skb; val 13526 drivers/net/ethernet/broadcom/tg3.c dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); val 13536 drivers/net/ethernet/broadcom/tg3.c if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, val 13538 drivers/net/ethernet/broadcom/tg3.c tnapi->tx_buffers[val].skb = NULL; val 13576 drivers/net/ethernet/broadcom/tg3.c val = data_off; val 13621 drivers/net/ethernet/broadcom/tg3.c for (i = data_off; i < rx_len; i++, val++) { val 13622 drivers/net/ethernet/broadcom/tg3.c if (*(rx_data + i) != (u8) (val & 0xff)) val 14316 drivers/net/ethernet/broadcom/tg3.c u32 cursize, val, magic; val 14336 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, cursize, &val) != 0) val 14339 drivers/net/ethernet/broadcom/tg3.c if (val == magic) val 14350 drivers/net/ethernet/broadcom/tg3.c u32 val; val 14352 drivers/net/ethernet/broadcom/tg3.c if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) val 14356 drivers/net/ethernet/broadcom/tg3.c if (val != TG3_EEPROM_MAGIC) { val 14361 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, 0xf0, &val) == 0) { val 14362 drivers/net/ethernet/broadcom/tg3.c if (val != 0) { val 14374 drivers/net/ethernet/broadcom/tg3.c tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; val 14980 drivers/net/ethernet/broadcom/tg3.c u32 val; val 14982 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, 0, &val)) val 14985 drivers/net/ethernet/broadcom/tg3.c if (val != TG3_EEPROM_MAGIC && val 14986 drivers/net/ethernet/broadcom/tg3.c (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) val 15151 drivers/net/ethernet/broadcom/tg3.c u32 val; val 15165 drivers/net/ethernet/broadcom/tg3.c val = tr32(VCPU_CFGSHDW); val 15166 drivers/net/ethernet/broadcom/tg3.c if (val & VCPU_CFGSHDW_ASPM_DBNC) val 15168 drivers/net/ethernet/broadcom/tg3.c if ((val & VCPU_CFGSHDW_WOL_ENABLE) && val 15169 drivers/net/ethernet/broadcom/tg3.c (val & VCPU_CFGSHDW_WOL_MAGPKT)) { val 15176 drivers/net/ethernet/broadcom/tg3.c tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); val 15177 drivers/net/ethernet/broadcom/tg3.c if (val == NIC_SRAM_DATA_SIG_MAGIC) { val 15366 drivers/net/ethernet/broadcom/tg3.c static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val) val 15384 drivers/net/ethernet/broadcom/tg3.c *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA); val 15402 drivers/net/ethernet/broadcom/tg3.c u32 val; val 15409 drivers/net/ethernet/broadcom/tg3.c val = tr32(OTP_STATUS); val 15410 drivers/net/ethernet/broadcom/tg3.c if (val & OTP_STATUS_CMD_DONE) val 15415 drivers/net/ethernet/broadcom/tg3.c return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; val 15758 drivers/net/ethernet/broadcom/tg3.c u32 val; val 15760 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, offset, &val) || val 15761 drivers/net/ethernet/broadcom/tg3.c (val & 0xfc000000) != 0x0c000000 || val 15762 drivers/net/ethernet/broadcom/tg3.c tg3_nvram_read(tp, offset + 4, &val) || val 15763 drivers/net/ethernet/broadcom/tg3.c val != 0) val 15771 drivers/net/ethernet/broadcom/tg3.c u32 val, offset, start, ver_offset; val 15781 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, offset, &val)) val 15784 drivers/net/ethernet/broadcom/tg3.c if ((val & 0xfc000000) == 0x0c000000) { val 15785 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, offset + 4, &val)) val 15788 drivers/net/ethernet/broadcom/tg3.c if (val == 0) val 15823 drivers/net/ethernet/broadcom/tg3.c u32 val, major, minor; val 15826 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) val 15829 drivers/net/ethernet/broadcom/tg3.c major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> val 15831 drivers/net/ethernet/broadcom/tg3.c minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> val 15837 drivers/net/ethernet/broadcom/tg3.c static void tg3_read_sb_ver(struct tg3 *tp, u32 val) val 15843 drivers/net/ethernet/broadcom/tg3.c if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) val 15846 drivers/net/ethernet/broadcom/tg3.c switch (val & TG3_EEPROM_SB_REVISION_MASK) { val 15869 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, offset, &val)) val 15872 drivers/net/ethernet/broadcom/tg3.c build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> val 15874 drivers/net/ethernet/broadcom/tg3.c major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> val 15876 drivers/net/ethernet/broadcom/tg3.c minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; val 15894 drivers/net/ethernet/broadcom/tg3.c u32 val, offset, start; val 15900 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, offset, &val)) val 15903 drivers/net/ethernet/broadcom/tg3.c if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) val 15917 drivers/net/ethernet/broadcom/tg3.c tg3_nvram_read(tp, offset + 8, &val)) val 15920 drivers/net/ethernet/broadcom/tg3.c offset += val - start; val 15987 drivers/net/ethernet/broadcom/tg3.c u32 val, val2; val 15992 drivers/net/ethernet/broadcom/tg3.c if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && val 15994 drivers/net/ethernet/broadcom/tg3.c TG3_OTP_MAGIC0_VALID(val)) { val 15995 drivers/net/ethernet/broadcom/tg3.c u64 val64 = (u64) val << 32 | val2; val 16012 drivers/net/ethernet/broadcom/tg3.c u32 val; val 16024 drivers/net/ethernet/broadcom/tg3.c if (tg3_nvram_read(tp, 0, &val)) val 16027 drivers/net/ethernet/broadcom/tg3.c if (val == TG3_EEPROM_MAGIC) val 16029 drivers/net/ethernet/broadcom/tg3.c else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) val 16030 drivers/net/ethernet/broadcom/tg3.c tg3_read_sb_ver(tp, val); val 16031 drivers/net/ethernet/broadcom/tg3.c else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) val 16206 drivers/net/ethernet/broadcom/tg3.c u32 val; val 16635 drivers/net/ethernet/broadcom/tg3.c val = tr32(MEMARB_MODE); val 16636 drivers/net/ethernet/broadcom/tg3.c tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); val 16644 drivers/net/ethernet/broadcom/tg3.c &val); val 16645 drivers/net/ethernet/broadcom/tg3.c tp->pci_fn = val & 0x7; val 16650 drivers/net/ethernet/broadcom/tg3.c tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); val 16651 drivers/net/ethernet/broadcom/tg3.c if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG) val 16652 drivers/net/ethernet/broadcom/tg3.c val = tr32(TG3_CPMU_STATUS); val 16655 drivers/net/ethernet/broadcom/tg3.c tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; val 16657 drivers/net/ethernet/broadcom/tg3.c tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> val 16822 drivers/net/ethernet/broadcom/tg3.c val = tr32(GRC_MODE); val 16825 drivers/net/ethernet/broadcom/tg3.c val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | val 16831 drivers/net/ethernet/broadcom/tg3.c val &= GRC_MODE_HOST_STACKUP; val 16833 drivers/net/ethernet/broadcom/tg3.c tw32(GRC_MODE, val | tp->grc_mode); val 17061 drivers/net/ethernet/broadcom/tg3.c static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) val 17092 drivers/net/ethernet/broadcom/tg3.c val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; val 17117 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | val 17120 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | val 17126 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | val 17131 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | val 17141 drivers/net/ethernet/broadcom/tg3.c val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; val 17142 drivers/net/ethernet/broadcom/tg3.c val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; val 17148 drivers/net/ethernet/broadcom/tg3.c val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; val 17149 drivers/net/ethernet/broadcom/tg3.c val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; val 17156 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_16 | val 17163 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_32 | val 17170 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_64 | val 17177 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_128 | val 17183 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_256 | val 17187 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_512 | val 17192 drivers/net/ethernet/broadcom/tg3.c val |= (DMA_RWCTRL_READ_BNDRY_1024 | val 17199 drivers/net/ethernet/broadcom/tg3.c return val; val 17250 drivers/net/ethernet/broadcom/tg3.c u32 val; val 17252 drivers/net/ethernet/broadcom/tg3.c val = *(((u32 *)&test_desc) + i); val 17255 drivers/net/ethernet/broadcom/tg3.c pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); val 17266 drivers/net/ethernet/broadcom/tg3.c u32 val; val 17269 drivers/net/ethernet/broadcom/tg3.c val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); val 17271 drivers/net/ethernet/broadcom/tg3.c val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); val 17272 drivers/net/ethernet/broadcom/tg3.c if ((val & 0xffff) == sram_dma_descs) { val 2443 drivers/net/ethernet/broadcom/tg3.h #define TG3_OTP_MAGIC0_VALID(val) \ val 2444 drivers/net/ethernet/broadcom/tg3.h ((((val) & 0xf0000000) == 0xa0000000) ||\ val 2445 drivers/net/ethernet/broadcom/tg3.h (((val) & 0x0f000000) == 0x0a000000)) val 369 drivers/net/ethernet/brocade/bna/bnad_debugfs.c u32 addr, val; val 379 drivers/net/ethernet/brocade/bna/bnad_debugfs.c rc = sscanf(kern_buf, "%x:%x", &addr, &val); val 398 drivers/net/ethernet/brocade/bna/bnad_debugfs.c writel(val, reg_addr); val 325 drivers/net/ethernet/cadence/macb_main.c u32 val; val 327 drivers/net/ethernet/cadence/macb_main.c return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE), val 2514 drivers/net/ethernet/cadence/macb_main.c u64 val = bp->macb_reg_readl(bp, offset); val 2516 drivers/net/ethernet/cadence/macb_main.c bp->ethtool_stats[i] += val; val 2517 drivers/net/ethernet/cadence/macb_main.c *p += val; val 2521 drivers/net/ethernet/cadence/macb_main.c val = bp->macb_reg_readl(bp, offset + 4); val 2522 drivers/net/ethernet/cadence/macb_main.c bp->ethtool_stats[i] += ((u64)val) << 32; val 2523 drivers/net/ethernet/cadence/macb_main.c *(++p) += val; val 3222 drivers/net/ethernet/cadence/macb_main.c u32 val; val 3227 drivers/net/ethernet/cadence/macb_main.c val = gem_readl(bp, DMACFG); val 3229 drivers/net/ethernet/cadence/macb_main.c val |= GEM_BIT(TXCOEN); val 3231 drivers/net/ethernet/cadence/macb_main.c val &= ~GEM_BIT(TXCOEN); val 3233 drivers/net/ethernet/cadence/macb_main.c gem_writel(bp, DMACFG, val); val 3240 drivers/net/ethernet/cadence/macb_main.c u32 val; val 3245 drivers/net/ethernet/cadence/macb_main.c val = gem_readl(bp, NCFGR); val 3247 drivers/net/ethernet/cadence/macb_main.c val |= GEM_BIT(RXCOEN); val 3249 drivers/net/ethernet/cadence/macb_main.c val &= ~GEM_BIT(RXCOEN); val 3251 drivers/net/ethernet/cadence/macb_main.c gem_writel(bp, NCFGR, val); val 3480 drivers/net/ethernet/cadence/macb_main.c u32 val, reg; val 3603 drivers/net/ethernet/cadence/macb_main.c val = 0; val 3605 drivers/net/ethernet/cadence/macb_main.c val = GEM_BIT(RGMII); val 3608 drivers/net/ethernet/cadence/macb_main.c val = MACB_BIT(RMII); val 3610 drivers/net/ethernet/cadence/macb_main.c val = MACB_BIT(MII); val 3613 drivers/net/ethernet/cadence/macb_main.c val |= MACB_BIT(CLKEN); val 3615 drivers/net/ethernet/cadence/macb_main.c macb_or_gem_writel(bp, USRIO, val); val 3619 drivers/net/ethernet/cadence/macb_main.c val = macb_mdc_clk_div(bp); val 3620 drivers/net/ethernet/cadence/macb_main.c val |= macb_dbw(bp); val 3622 drivers/net/ethernet/cadence/macb_main.c val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); val 3623 drivers/net/ethernet/cadence/macb_main.c macb_writel(bp, NCFGR, val); val 4196 drivers/net/ethernet/cadence/macb_main.c int err, val; val 4292 drivers/net/ethernet/cadence/macb_main.c val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10)); val 4293 drivers/net/ethernet/cadence/macb_main.c if (val) val 4294 drivers/net/ethernet/cadence/macb_main.c bp->rx_bd_rd_prefetch = (2 << (val - 1)) * val 4297 drivers/net/ethernet/cadence/macb_main.c val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10)); val 4298 drivers/net/ethernet/cadence/macb_main.c if (val) val 4299 drivers/net/ethernet/cadence/macb_main.c bp->tx_bd_rd_prefetch = (2 << (val - 1)) * val 1422 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u64 val; val 1435 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c val = octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2); val 1436 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c return (val >> SCR2_BIT_FW_LOADED) & 1ULL; val 57 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c u32 val; val 59 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); val 60 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c if (val & 0x000c0000) { val 62 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c val & 0x000c0000); val 65 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c val |= 0xf; /* Enable Link error reporting */ val 68 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); val 74 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c u32 val; val 78 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); val 81 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mps = ((val & (0x7 << 5)) >> 5); val 83 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c val &= ~(0x7 << 5); /* Turn off any MPS bits */ val 84 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c val |= (mps << 5); /* Set MPS */ val 85 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); val 97 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c u32 val; val 101 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); val 104 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mrrs = ((val & (0x7 << 12)) >> 12); val 106 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c val &= ~(0x7 << 12); /* Turn off any MRRS bits */ val 107 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c val |= (mrrs << 12); /* Set MRRS */ val 108 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); val 109 drivers/net/ethernet/cavium/liquidio/cn68xx_device.c u32 val = 0; val 112 drivers/net/ethernet/cavium/liquidio/cn68xx_device.c pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val); val 113 drivers/net/ethernet/cavium/liquidio/cn68xx_device.c val |= 0x3; val 114 drivers/net/ethernet/cavium/liquidio/cn68xx_device.c pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val); val 704 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c static int octnet_gpio_access(struct net_device *netdev, int addr, int val) val 716 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c nctrl.ncmd.s.param2 = val; val 731 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c static int octnet_id_active(struct net_device *netdev, int val) val 742 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c nctrl.ncmd.s.param1 = val; val 2378 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c u64 val; val 2397 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c val = readq(inst_cnt_reg); val 2399 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c val = (val & 0xFFFF000000000000ULL) | val 2402 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c writeq(val, inst_cnt_reg); val 2982 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c u32 val; val 2991 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c pci_read_config_dword(oct->pci_dev, (i * 4), &val); val 2993 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (i * 4), i, val); val 2997 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c pci_read_config_dword(oct->pci_dev, (i * 4), &val); val 2999 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (i * 4), i, val); val 129 drivers/net/ethernet/cavium/liquidio/octeon_config.h #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val val 136 drivers/net/ethernet/cavium/liquidio/octeon_config.h #define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val val 137 drivers/net/ethernet/cavium/liquidio/octeon_config.h #define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val val 1358 drivers/net/ethernet/cavium/liquidio/octeon_device.c u64 val, val 1369 drivers/net/ethernet/cavium/liquidio/octeon_device.c writel(val >> 32, oct->reg_list.pci_win_wr_data_hi); val 1373 drivers/net/ethernet/cavium/liquidio/octeon_device.c writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo); val 749 drivers/net/ethernet/cavium/liquidio/octeon_device.h void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); val 916 drivers/net/ethernet/cavium/liquidio/octeon_device.h u32 flag, u32 val) val 918 drivers/net/ethernet/cavium/liquidio/octeon_device.h if (val) val 220 drivers/net/ethernet/cavium/liquidio/octeon_main.h #define ROUNDUP4(val) (((val) + 3) & 0xfffffffc) val 224 drivers/net/ethernet/cavium/liquidio/octeon_main.h #define ROUNDUP8(val) (((val) + 7) & 0xfffffff8) val 228 drivers/net/ethernet/cavium/liquidio/octeon_main.h #define ROUNDUP16(val) (((val) + 15) & 0xfffffff0) val 232 drivers/net/ethernet/cavium/liquidio/octeon_main.h #define ROUNDUP128(val) (((val) + 127) & 0xffffff80) val 195 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c u32 val) val 197 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c __be32 t = cpu_to_be32(val); val 54 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.h u32 val); val 88 drivers/net/ethernet/cavium/thunder/nic_main.c static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val) val 90 drivers/net/ethernet/cavium/thunder/nic_main.c writeq_relaxed(val, nic->reg_base + offset); val 93 drivers/net/ethernet/cavium/thunder/nicvf_main.c void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val) val 95 drivers/net/ethernet/cavium/thunder/nicvf_main.c writeq_relaxed(val, nic->reg_base + offset); val 104 drivers/net/ethernet/cavium/thunder/nicvf_main.c u64 qidx, u64 val) val 108 drivers/net/ethernet/cavium/thunder/nicvf_main.c writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT)); val 32 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 reg, int bit_pos, int bits, int val) val 43 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (((reg_val & bit_mask) >> bit_pos) == val) val 360 drivers/net/ethernet/cavium/thunder/nicvf_queues.h void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val); val 362 drivers/net/ethernet/cavium/thunder/nicvf_queues.h void nicvf_qset_reg_write(struct nicvf *nic, u64 offset, u64 val); val 365 drivers/net/ethernet/cavium/thunder/nicvf_queues.h u64 qidx, u64 val); val 114 drivers/net/ethernet/cavium/thunder/thunder_bgx.c static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val) val 118 drivers/net/ethernet/cavium/thunder/thunder_bgx.c writeq_relaxed(val, addr); val 121 drivers/net/ethernet/cavium/thunder/thunder_bgx.c static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val) val 125 drivers/net/ethernet/cavium/thunder/thunder_bgx.c writeq_relaxed(val | readq_relaxed(addr), addr); val 1550 drivers/net/ethernet/cavium/thunder/thunder_bgx.c u64 status, val; val 1558 drivers/net/ethernet/cavium/thunder/thunder_bgx.c val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG); val 1559 drivers/net/ethernet/cavium/thunder/thunder_bgx.c val &= ~CMR_EN; val 1560 drivers/net/ethernet/cavium/thunder/thunder_bgx.c bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val); val 1561 drivers/net/ethernet/cavium/thunder/thunder_bgx.c val |= CMR_EN; val 1562 drivers/net/ethernet/cavium/thunder/thunder_bgx.c bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val); val 48 drivers/net/ethernet/chelsio/cxgb/cphy.h u16 reg_addr, u16 val); val 120 drivers/net/ethernet/chelsio/cxgb/cphy.h unsigned int val) val 123 drivers/net/ethernet/chelsio/cxgb/cphy.h reg, val); val 133 drivers/net/ethernet/chelsio/cxgb/cphy.h unsigned int val) val 135 drivers/net/ethernet/chelsio/cxgb/cphy.h return cphy_mdio_write(cphy, MDIO_DEVAD_NONE, reg, val); val 318 drivers/net/ethernet/chelsio/cxgb/cpl5_cmd.h u32 val; val 346 drivers/net/ethernet/chelsio/cxgb/cxgb2.c static void set_msglevel(struct net_device *dev, u32 val) val 350 drivers/net/ethernet/chelsio/cxgb/cxgb2.c adapter->msg_enable = val; val 1196 drivers/net/ethernet/chelsio/cxgb/cxgb2.c u32 val; val 1208 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1211 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val |= S_DATA; val 1213 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val &= ~S_DATA; val 1218 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val &= ~S_CLOCK; val 1219 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1224 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val |= S_CLOCK; val 1225 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1232 drivers/net/ethernet/chelsio/cxgb/cxgb2.c u32 val; val 1276 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1277 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val |= NP_LOAD; val 1279 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1281 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1282 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val &= ~S_LOAD_CORE; val 1283 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val &= ~S_CLOCK; val 1284 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1294 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1295 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val |= S_LOAD_CORE; val 1297 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1299 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1300 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val &= ~S_LOAD_CORE; val 1302 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1306 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1307 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val |= NP_LOAD; val 1309 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1311 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1312 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val &= ~S_LOAD_MEM; val 1313 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val &= ~S_CLOCK; val 1315 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1325 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1326 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val |= S_LOAD_MEM; val 1328 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 1330 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 1331 drivers/net/ethernet/chelsio/cxgb/cxgb2.c val &= ~S_LOAD_MEM; val 1333 drivers/net/ethernet/chelsio/cxgb/cxgb2.c __t1_tpi_write(adapter, A_ELMER0_GPO, val); val 300 drivers/net/ethernet/chelsio/cxgb/espi.c void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val) val 307 drivers/net/ethernet/chelsio/cxgb/espi.c espi->misc_ctrl = (val & ~MON_MASK) | val 20 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c u32 val; val 22 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_read(cphy, reg, &val); val 23 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_write(cphy, reg, val | bitval); val 31 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c u32 val; val 33 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_read(cphy, reg, &val); val 34 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_write(cphy, reg, val & ~bitval); val 202 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c u32 val = 0; val 206 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_read(phy, MII_GBCR, &val); val 207 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL); val 209 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= GBCR_ADV_1000HALF; val 211 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= GBCR_ADV_1000FULL; val 213 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_write(phy, MII_GBCR, val); val 215 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val = 1; val 217 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= ADVERTISE_10HALF; val 219 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= ADVERTISE_10FULL; val 221 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= ADVERTISE_100HALF; val 223 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= ADVERTISE_100FULL; val 225 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= ADVERTISE_PAUSE; val 227 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= ADVERTISE_PAUSE_ASYM; val 228 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_write(phy, MII_ADVERTISE, val); val 276 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c u32 val; val 279 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val); val 285 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT)); val 288 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2); val 290 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val); val 121 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c u32 val; val 125 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val); val 126 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val); val 127 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); val 132 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); val 136 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); val 138 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); val 142 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val); val 143 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val); val 174 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c u32 val = 0; val 178 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); val 179 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c val &= MDIO_STAT1_LSTATUS; val 180 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c *link_ok = (val == MDIO_STAT1_LSTATUS); val 214 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c u32 val; val 223 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val); val 224 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val | 1); val 227 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT2, &val); val 228 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val); val 238 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c u32 val; val 240 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 241 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c val &= ~4; val 242 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 245 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); val 249 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 250 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c val |= 0x8000; val 251 drivers/net/ethernet/chelsio/cxgb/mv88x201x.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 39 drivers/net/ethernet/chelsio/cxgb/my3126.c u32 val; val 47 drivers/net/ethernet/chelsio/cxgb/my3126.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); val 48 drivers/net/ethernet/chelsio/cxgb/my3126.c val16 = (u16) val; val 66 drivers/net/ethernet/chelsio/cxgb/my3126.c OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val); val 67 drivers/net/ethernet/chelsio/cxgb/my3126.c act_count += val; val 70 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 71 drivers/net/ethernet/chelsio/cxgb/my3126.c cphy->elmer_gpo = val; val 73 drivers/net/ethernet/chelsio/cxgb/my3126.c if ( (val & (1 << 8)) || (val & (1 << 19)) || val 76 drivers/net/ethernet/chelsio/cxgb/my3126.c val |= (1 << 9); val 78 drivers/net/ethernet/chelsio/cxgb/my3126.c val |= (1 << 20); val 82 drivers/net/ethernet/chelsio/cxgb/my3126.c val &= ~(1 << 9); val 84 drivers/net/ethernet/chelsio/cxgb/my3126.c val &= ~(1 << 20); val 88 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 90 drivers/net/ethernet/chelsio/cxgb/my3126.c cphy->elmer_gpo = val; val 113 drivers/net/ethernet/chelsio/cxgb/my3126.c u32 val; val 118 drivers/net/ethernet/chelsio/cxgb/my3126.c cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); val 119 drivers/net/ethernet/chelsio/cxgb/my3126.c val16 = (u16) val; val 122 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 123 drivers/net/ethernet/chelsio/cxgb/my3126.c cphy->elmer_gpo = val; val 130 drivers/net/ethernet/chelsio/cxgb/my3126.c val &= ~(1 << 8); val 132 drivers/net/ethernet/chelsio/cxgb/my3126.c val &= ~(1 << 19); val 136 drivers/net/ethernet/chelsio/cxgb/my3126.c val |= (1 << 8); val 138 drivers/net/ethernet/chelsio/cxgb/my3126.c val |= (1 << 19); val 141 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 142 drivers/net/ethernet/chelsio/cxgb/my3126.c cphy->elmer_gpo = val; val 189 drivers/net/ethernet/chelsio/cxgb/my3126.c u32 val; val 191 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 192 drivers/net/ethernet/chelsio/cxgb/my3126.c val &= ~4; val 193 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 196 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); val 200 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 201 drivers/net/ethernet/chelsio/cxgb/my3126.c val |= 0x8000; val 202 drivers/net/ethernet/chelsio/cxgb/my3126.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 268 drivers/net/ethernet/chelsio/cxgb/pm3393.c u32 val = TXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_TXXG_TXEN0; val 271 drivers/net/ethernet/chelsio/cxgb/pm3393.c val |= SUNI1x10GEXP_BITMSK_TXXG_FCRX; val 273 drivers/net/ethernet/chelsio/cxgb/pm3393.c val |= SUNI1x10GEXP_BITMSK_TXXG_FCTX; val 274 drivers/net/ethernet/chelsio/cxgb/pm3393.c pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val); val 501 drivers/net/ethernet/chelsio/cxgb/pm3393.c u32 val, lo, mid, hi, enabled = cmac->instance->enabled; val 546 drivers/net/ethernet/chelsio/cxgb/pm3393.c pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val); val 547 drivers/net/ethernet/chelsio/cxgb/pm3393.c val &= 0xff0f; val 548 drivers/net/ethernet/chelsio/cxgb/pm3393.c pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); val 554 drivers/net/ethernet/chelsio/cxgb/pm3393.c val |= 0x0090; val 555 drivers/net/ethernet/chelsio/cxgb/pm3393.c pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); val 686 drivers/net/ethernet/chelsio/cxgb/pm3393.c u32 val; val 726 drivers/net/ethernet/chelsio/cxgb/pm3393.c t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 727 drivers/net/ethernet/chelsio/cxgb/pm3393.c val &= ~1; val 728 drivers/net/ethernet/chelsio/cxgb/pm3393.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 740 drivers/net/ethernet/chelsio/cxgb/pm3393.c val |= 1; val 741 drivers/net/ethernet/chelsio/cxgb/pm3393.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 752 drivers/net/ethernet/chelsio/cxgb/pm3393.c t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val); val 753 drivers/net/ethernet/chelsio/cxgb/pm3393.c is_pl4_reset_finished = (val & SUNI1x10GEXP_BITMSK_TOP_EXPIRED); val 764 drivers/net/ethernet/chelsio/cxgb/pm3393.c is_pl4_outof_lock = (val & x); val 770 drivers/net/ethernet/chelsio/cxgb/pm3393.c (val & SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED); val 779 drivers/net/ethernet/chelsio/cxgb/pm3393.c i, is_pl4_reset_finished, val, val 343 drivers/net/ethernet/chelsio/cxgb/sge.c void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val) val 348 drivers/net/ethernet/chelsio/cxgb/sge.c s->max_avail = val; val 358 drivers/net/ethernet/chelsio/cxgb/sge.c unsigned int val) val 362 drivers/net/ethernet/chelsio/cxgb/sge.c p->drain_bits_per_1024ns = val * 1024 / 1000; val 495 drivers/net/ethernet/chelsio/cxgb/sge.c static inline void doorbell_pio(struct adapter *adapter, u32 val) val 498 drivers/net/ethernet/chelsio/cxgb/sge.c writel(val, adapter->regs + A_SG_DOORBELL); val 905 drivers/net/ethernet/chelsio/cxgb/sge.c u32 val = readl(sge->adapter->regs + A_PL_ENABLE); val 907 drivers/net/ethernet/chelsio/cxgb/sge.c writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); val 917 drivers/net/ethernet/chelsio/cxgb/sge.c u32 val = readl(sge->adapter->regs + A_PL_ENABLE); val 922 drivers/net/ethernet/chelsio/cxgb/sge.c writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); val 65 drivers/net/ethernet/chelsio/cxgb/subr.c u32 val = readl(adapter->regs + reg) & mask; val 67 drivers/net/ethernet/chelsio/cxgb/subr.c if (!!val == polarity) val 253 drivers/net/ethernet/chelsio/cxgb/subr.c u32 val; val 255 drivers/net/ethernet/chelsio/cxgb/subr.c __t1_tpi_read(adapter, mi1_reg, &val); val 256 drivers/net/ethernet/chelsio/cxgb/subr.c busy = val & F_MI1_OP_BUSY; val 271 drivers/net/ethernet/chelsio/cxgb/subr.c u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) | val 275 drivers/net/ethernet/chelsio/cxgb/subr.c val |= V_MI1_SOF(1); val 276 drivers/net/ethernet/chelsio/cxgb/subr.c t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val); val 288 drivers/net/ethernet/chelsio/cxgb/subr.c unsigned int val; val 295 drivers/net/ethernet/chelsio/cxgb/subr.c __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val); val 297 drivers/net/ethernet/chelsio/cxgb/subr.c return val; val 301 drivers/net/ethernet/chelsio/cxgb/subr.c u16 reg_addr, u16 val) val 308 drivers/net/ethernet/chelsio/cxgb/subr.c __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val); val 330 drivers/net/ethernet/chelsio/cxgb/subr.c unsigned int val; val 347 drivers/net/ethernet/chelsio/cxgb/subr.c __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val); val 349 drivers/net/ethernet/chelsio/cxgb/subr.c return val; val 353 drivers/net/ethernet/chelsio/cxgb/subr.c int mmd_addr, u16 reg_addr, u16 val) val 368 drivers/net/ethernet/chelsio/cxgb/subr.c __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val); val 565 drivers/net/ethernet/chelsio/cxgb/subr.c u16 val; val 574 drivers/net/ethernet/chelsio/cxgb/subr.c pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val); val 575 drivers/net/ethernet/chelsio/cxgb/subr.c } while (!(val & F_VPD_OP_FLAG) && --i); val 577 drivers/net/ethernet/chelsio/cxgb/subr.c if (!(val & F_VPD_OP_FLAG)) { val 902 drivers/net/ethernet/chelsio/cxgb/subr.c u32 val = readl(adapter->regs + A_TP_PC_CONFIG); val 904 drivers/net/ethernet/chelsio/cxgb/subr.c val = G_TP_PC_REV(val); val 905 drivers/net/ethernet/chelsio/cxgb/subr.c if (val == 2) val 907 drivers/net/ethernet/chelsio/cxgb/subr.c else if (val == 3) val 968 drivers/net/ethernet/chelsio/cxgb/subr.c u32 val = readl(adapter->regs + A_MC4_CFG); val 970 drivers/net/ethernet/chelsio/cxgb/subr.c writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG); val 549 drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h #define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0) val 21 drivers/net/ethernet/chelsio/cxgb/tp.c u32 val; val 26 drivers/net/ethernet/chelsio/cxgb/tp.c val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM | val 29 drivers/net/ethernet/chelsio/cxgb/tp.c val |= F_OFFLOAD_DISABLE; val 31 drivers/net/ethernet/chelsio/cxgb/tp.c val |= F_TP_IN_ESPI_CHECK_IP_CSUM | F_TP_IN_ESPI_CHECK_TCP_CSUM; val 32 drivers/net/ethernet/chelsio/cxgb/tp.c writel(val, ap->regs + A_TP_IN_CONFIG); val 142 drivers/net/ethernet/chelsio/cxgb/tp.c u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG); val 145 drivers/net/ethernet/chelsio/cxgb/tp.c val |= csum_bit; val 147 drivers/net/ethernet/chelsio/cxgb/tp.c val &= ~csum_bit; val 148 drivers/net/ethernet/chelsio/cxgb/tp.c writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG); val 35 drivers/net/ethernet/chelsio/cxgb/vsc7326.c static void vsc_read(adapter_t *adapter, u32 addr, u32 *val) val 55 drivers/net/ethernet/chelsio/cxgb/vsc7326.c *val = (vhi << 16) | vlo; val 77 drivers/net/ethernet/chelsio/cxgb/vsc7326.c u32 val; val 80 drivers/net/ethernet/chelsio/cxgb/vsc7326.c t1_tpi_read(adapter, A_ELMER0_GPO, &val); val 81 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val &= ~1; val 82 drivers/net/ethernet/chelsio/cxgb/vsc7326.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 84 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val |= 0x1; /* Enable mac MAC itself */ val 85 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val |= 0x800; /* Turn off the red LED */ val 86 drivers/net/ethernet/chelsio/cxgb/vsc7326.c t1_tpi_write(adapter, A_ELMER0_GPO, val); val 323 drivers/net/ethernet/chelsio/cxgb/vsc7326.c u32 val = 0; val 326 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_read(adapter, REG_MEM_BIST, &val); val 384 drivers/net/ethernet/chelsio/cxgb/vsc7326.c u32 val; val 392 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &val); val 393 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val &= ~0xf0000000; val 394 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, val | (port << 28)); val 530 drivers/net/ethernet/chelsio/cxgb/vsc7326.c u32 val; val 536 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_read(mac->adapter, REG_MODE_CFG(port), &val); val 538 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val |= 0x2; val 540 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val |= 1; val 541 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_write(mac->adapter, REG_MODE_CFG(port), val); val 547 drivers/net/ethernet/chelsio/cxgb/vsc7326.c u32 val; val 553 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_read(mac->adapter, REG_MODE_CFG(port), &val); val 555 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val &= ~0x2; val 557 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val &= ~0x1; val 558 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_write(mac->adapter, REG_MODE_CFG(port), val); val 559 drivers/net/ethernet/chelsio/cxgb/vsc7326.c vsc_read(mac->adapter, REG_MODE_CFG(port), &val); val 685 drivers/net/ethernet/chelsio/cxgb/vsc7326.c u32 val; val 708 drivers/net/ethernet/chelsio/cxgb/vsc7326.c val = (vhi << 16) | vlo; val 709 drivers/net/ethernet/chelsio/cxgb/vsc7326.c } while ((++i < 10000) && (val == 0xffffffff)); val 272 drivers/net/ethernet/chelsio/cxgb3/adapter.h u32 val = readl(adapter->regs + reg_addr); val 274 drivers/net/ethernet/chelsio/cxgb3/adapter.h CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val); val 275 drivers/net/ethernet/chelsio/cxgb3/adapter.h return val; val 278 drivers/net/ethernet/chelsio/cxgb3/adapter.h static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) val 280 drivers/net/ethernet/chelsio/cxgb3/adapter.h CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val); val 281 drivers/net/ethernet/chelsio/cxgb3/adapter.h writel(val, adapter->regs + reg_addr); val 160 drivers/net/ethernet/chelsio/cxgb3/common.h u16 reg_addr, u16 val); val 570 drivers/net/ethernet/chelsio/cxgb3/common.h unsigned int val) val 573 drivers/net/ethernet/chelsio/cxgb3/common.h reg, val); val 603 drivers/net/ethernet/chelsio/cxgb3/common.h unsigned int val; val 643 drivers/net/ethernet/chelsio/cxgb3/common.h u32 val); val 55 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t val; val 702 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c unsigned int val; val 707 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c ret = kstrtouint(buf, 0, &val); val 710 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (val < min_val || val > max_val) val 714 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c ret = (*set) (to_net_dev(d), val); val 734 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c static ssize_t set_nfilters(struct net_device *dev, unsigned int val) val 742 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (val && adap->params.rev == 0) val 744 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers - val 747 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c adap->params.mc5.nfilters = val; val 757 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c static ssize_t set_nservers(struct net_device *dev, unsigned int val) val 764 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters - val 767 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c adap->params.mc5.nservers = val; val 831 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c unsigned int val; val 837 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c ret = kstrtouint(buf, 0, &val); val 840 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (val > 10000000) val 844 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c ret = t3_config_sched(adap, val, sched); val 1535 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c static void set_msglevel(struct net_device *dev, u32 val) val 1540 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c adapter->msg_enable = val; val 2134 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c static int in_range(int val, int lo, int hi) val 2136 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c return val < 0 || (val <= hi && val >= lo); val 2312 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (edata.val < 1 || val 2313 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c (edata.val > 1 && !(adapter->flags & USING_MSIX))) val 2320 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (edata.val + other_qsets > SGE_QSETS) val 2323 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c pi->nqsets = edata.val; val 2339 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c edata.val = pi->nqsets; val 208 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c unsigned int val = 0; val 218 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c val = t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ); val 219 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c for (i = 0; i < 4; i++, val >>= 8) val 220 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c uiip->pgsz_factor[i] = val & 0xFF; val 222 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c val = t3_read_reg(adapter, A_TP_PARA_REG7); val 224 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c uiip->max_rxsz = min((val >> S_PMMAXXFERLEN0)&M_PMMAXXFERLEN0, val 225 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c (val >> S_PMMAXXFERLEN1)&M_PMMAXXFERLEN1); val 230 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c val = min(adapter->params.tp.tx_pg_size, val 232 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c uiip->max_txsz = min(val, uiip->max_txsz); val 235 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c val = t3_read_reg(adapter, A_TP_PARA_REG2); val 236 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c if ((val >> S_MAXRXDATA) != 0x3f60) { val 237 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c val &= (M_RXCOALESCESIZE << S_RXCOALESCESIZE); val 238 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c val |= V_MAXRXDATA(0x3f60); val 240 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c adapter->name, val); val 241 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c t3_write_reg(adapter, A_TP_PARA_REG2, val); val 248 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c val = min(adapter->params.tp.rx_pg_size, val 251 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c uiip->max_rxsz = min(val, uiip->max_rxsz); val 257 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c val |= (uiip->pgsz_factor[i] & 0xF) << (8 * i); val 258 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c if (val && (val != t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ))) { val 260 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c adapter->name, val, uiip->pgsz_factor[0], val 263 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c t3_write_reg(adapter, A_ULPRX_ISCSI_PSZ, val); val 1106 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c req->val = cpu_to_be64(V_TCB_L2T_IX(e->idx)); val 675 drivers/net/ethernet/chelsio/cxgb3/t3_cpl.h __be64 val; val 59 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val = t3_read_reg(adapter, reg); val 61 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c if (!!(val & mask) == polarity) { val 63 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c *valp = val; val 88 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, p->reg_addr + offset, p->val); val 104 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val) val 108 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, addr, v | val); val 164 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val; val 168 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP); val 169 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c while ((val & F_BUSY) && attempts--) val 170 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = t3_read_reg(adap, val 172 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c if (val & F_BUSY) val 175 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1); val 180 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val64 |= (u64) val << 32; val 183 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val >>= shift[mc7->width]; val 184 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val64 |= (u64) val << (step[mc7->width] * i); val 199 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val = F_PREEN | V_CLKDIV(clkdiv); val 201 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adap, A_MI1_CFG, val); val 229 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u16 reg_addr, u16 val) val 239 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, A_MI1_DATA, val); val 293 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u16 reg_addr, u16 val) val 302 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, A_MI1_DATA, val); val 332 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int val; val 334 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c ret = t3_mdio_read(phy, mmd, reg, &val); val 336 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val &= ~clear; val 337 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c ret = t3_mdio_write(phy, mmd, reg, val | set); val 385 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int val = 0; val 387 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c err = t3_mdio_read(phy, MDIO_DEVAD_NONE, MII_CTRL1000, &val); val 391 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); val 393 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_1000HALF; val 395 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_1000FULL; val 397 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c err = t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_CTRL1000, val); val 401 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = 1; val 403 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_10HALF; val 405 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_10FULL; val 407 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_100HALF; val 409 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_100FULL; val 411 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_PAUSE_CAP; val 413 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_PAUSE_ASYM; val 414 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c return t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_ADVERTISE, val); val 427 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int val = 0; val 430 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_1000XHALF; val 432 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_1000XFULL; val 434 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_1000XPAUSE; val 436 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= ADVERTISE_1000XPSE_ASYM; val 437 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c return t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_ADVERTISE, val); val 488 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val; val 490 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c return t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); val 615 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u16 val; val 626 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val); val 627 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c } while (!(val & PCI_VPD_ADDR_F) && --attempts); val 629 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c if (!(val & PCI_VPD_ADDR_F)) { val 649 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u16 val; val 662 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val); val 663 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c } while ((val & PCI_VPD_ADDR_F) && --attempts); val 665 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c if (val & PCI_VPD_ADDR_F) { val 684 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c static int vpdstrtouint(char *s, u8 len, unsigned int base, unsigned int *val) val 690 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c return kstrtouint(strim(tok), base, val); val 693 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c static int vpdstrtou16(char *s, u8 len, unsigned int base, u16 *val) val 699 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c return kstrtou16(strim(tok), base, val); val 828 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val) val 834 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, A_SF_DATA, val); val 918 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int i, c, left, val, offset = addr & 0xff; val 923 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = swab32(addr) | SF_PROG_PAGE; val 926 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c (ret = sf1_write(adapter, 4, 1, val)) != 0) val 931 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c for (val = 0, i = 0; i < c; ++i) val 932 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = (val << 8) + *data++; val 934 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c ret = sf1_write(adapter, c, c != left, val); val 2495 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val; val 2504 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c 0, SG_CONTEXT_CMD_ATTEMPTS, 1, &val)) val 2509 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c return G_CQ_INDEX(val); val 2541 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val = i << 16; val 2544 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= (cpus[cpu_idx++] & 0x3f) << (8 * j); val 2548 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val); val 2664 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val) val 2667 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adap, A_TP_PIO_DATA, val); val 2782 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val; val 2787 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = t3_read_reg(adap, A_TP_PARA_REG3); val 2788 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val &= ~(F_RXCOALESCEENABLE | F_RXCOALESCEPSHEN); val 2791 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= F_RXCOALESCEENABLE; val 2793 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= F_RXCOALESCEPSHEN; val 2798 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adap, A_TP_PARA_REG3, val); val 3184 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val) val 3186 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, addr, val); val 3207 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val; val 3215 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); val 3216 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c slow = val & F_SLOW; val 3217 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c width = G_WIDTH(val); val 3218 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c density = G_DEN(val); val 3220 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); val 3221 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ val 3243 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val | F_CLKEN | F_TERM150); val 3251 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = slow ? 3 : 6; val 3255 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) val 3269 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) || val 3270 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) val 3292 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); val 3293 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c } while ((val & F_BUSY) && --attempts); val 3294 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c if (val & F_BUSY) { val 3322 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u16 val, devid; val 3326 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val); val 3327 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; val 3332 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val & ~PCI_EXP_DEVCTL_READRQ & val 3337 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val); val 3344 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c if (val & PCI_EXP_LNKCTL_ASPM_L0S) /* check LOsEnable */ val 3461 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u16 val; val 3464 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); val 3465 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c p->width = (val >> 4) & 0x3f; val 3562 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2); val 3573 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= F_ENRGMII; val 3576 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, A_XGM_PORT_CFG, val); val 3579 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c val |= F_CLKDIVRESET_; val 3580 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, A_XGM_PORT_CFG, val); val 3582 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val); val 110 drivers/net/ethernet/chelsio/cxgb3/vsc8211.c u32 val; val 113 drivers/net/ethernet/chelsio/cxgb3/vsc8211.c return t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_STATUS, &val); val 371 drivers/net/ethernet/chelsio/cxgb3/vsc8211.c unsigned int val; val 379 drivers/net/ethernet/chelsio/cxgb3/vsc8211.c err = t3_mdio_read(phy, MDIO_DEVAD_NONE, VSC8211_EXT_CTRL, &val); val 382 drivers/net/ethernet/chelsio/cxgb3/vsc8211.c if (val & VSC_CTRL_MEDIA_MODE_HI) { val 406 drivers/net/ethernet/chelsio/cxgb3/vsc8211.c val | VSC_CTRL_CLAUSE37_VIEW); val 98 drivers/net/ethernet/chelsio/cxgb3/xgmac.c u32 val; val 131 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val = F_MAC_RESET_ | F_XGMAC_STOP_EN; val 134 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_PCS_RESET_; val 136 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_PCS_RESET_ | F_XG2G_RESET_; val 138 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_RGMII_RESET_ | F_XG2G_RESET_; val 139 drivers/net/ethernet/chelsio/cxgb3/xgmac.c t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); val 141 drivers/net/ethernet/chelsio/cxgb3/xgmac.c if ((val & F_PCS_RESET_) && adap->params.rev) { val 155 drivers/net/ethernet/chelsio/cxgb3/xgmac.c u32 val; val 192 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val = F_MAC_RESET_; val 194 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_PCS_RESET_; val 196 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_PCS_RESET_ | F_XG2G_RESET_; val 198 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_RGMII_RESET_ | F_XG2G_RESET_; val 199 drivers/net/ethernet/chelsio/cxgb3/xgmac.c t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); val 201 drivers/net/ethernet/chelsio/cxgb3/xgmac.c if ((val & F_PCS_RESET_) && adap->params.rev) { val 302 drivers/net/ethernet/chelsio/cxgb3/xgmac.c u32 val, hash_lo, hash_hi; val 306 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES; val 308 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_COPYALLFRAMES; val 309 drivers/net/ethernet/chelsio/cxgb3/xgmac.c t3_write_reg(adap, A_XGM_RX_CFG + oft, val); val 430 drivers/net/ethernet/chelsio/cxgb3/xgmac.c u32 val; val 438 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val = V_PORTSPEED(0); val 440 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val = V_PORTSPEED(1); val 442 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val = V_PORTSPEED(2); val 444 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val = V_PORTSPEED(3); val 449 drivers/net/ethernet/chelsio/cxgb3/xgmac.c V_PORTSPEED(M_PORTSPEED), val); val 452 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft); val 453 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM); val 458 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(rx_max_pkt_size) / 8); val 460 drivers/net/ethernet/chelsio/cxgb3/xgmac.c t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val); val 515 drivers/net/ethernet/chelsio/cxgb3/xgmac.c int val = F_MAC_RESET_; val 522 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_PCS_RESET_; val 524 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_PCS_RESET_ | F_XG2G_RESET_; val 526 drivers/net/ethernet/chelsio/cxgb3/xgmac.c val |= F_RGMII_RESET_ | F_XG2G_RESET_; val 527 drivers/net/ethernet/chelsio/cxgb3/xgmac.c t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val); val 1711 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c u32 para[2], val[2]; val 1741 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val); val 1747 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tid->uotid_base = val[0]; val 1748 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tid->nuotids = val[1] - val[0] + 1; val 1760 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c para, val); val 1766 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tid->hpftid_base = val[0]; val 1767 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tid->nhpftids = val[1] - val[0] + 1; val 2124 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c u64 tcamy, tcamx, val; val 2143 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); val 2144 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tcamy = DMACH_G(val) << 32; val 2156 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tcam->vniy = (tcam->vniy << 16) | VIDL_G(val); val 2160 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tcam->ivlan = VIDL_G(val); val 2168 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); val 2169 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tcamx = DMACH_G(val) << 32; val 2175 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tcam->vnix = (tcam->vnix << 16) | VIDL_G(val); val 2351 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c u32 val; val 2358 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c val = DBGICMD_V(4) | DBGITID_V(tid); val 2359 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val); val 2360 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tid_data->dbig_cmd = val; val 2362 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */ val 2363 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val); val 2364 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tid_data->dbig_conf = val; val 2367 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c val = 1; val 2368 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c while (val) { val 2369 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A); val 2370 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c val = val & DBGICMDBUSY_F; val 2377 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A); val 2378 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c tid_data->dbig_rsp_stat = val; val 2379 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c if (!(val & 1)) val 1223 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h struct ch_filter_tuple val; val 1302 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) val 1304 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h writel(val, adap->regs + reg_addr); val 1313 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h static inline void writeq(u64 val, volatile void __iomem *addr) val 1315 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h writel(val, addr); val 1316 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h writel(val >> 32, addr + 4); val 1325 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) val 1327 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h writeq(val, adap->regs + reg_addr); val 1500 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u32 val); val 1578 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); val 1731 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h unsigned int mask, unsigned int val); val 1768 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u32 *val); val 1771 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u32 *val); val 1774 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u32 *val, int rw, bool sleep_ok); val 1778 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h const u32 *val, int timeout); val 1781 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h const u32 *val); val 1830 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h unsigned int mmd, unsigned int reg, u16 val); val 1858 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u32 addr, u32 val); val 128 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h static inline __u8 bitswap_1(unsigned char val) val 130 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h return ((val & 0x80) >> 7) | val 131 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h ((val & 0x40) >> 5) | val 132 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h ((val & 0x20) >> 3) | val 133 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h ((val & 0x10) >> 1) | val 134 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h ((val & 0x08) << 1) | val 135 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h ((val & 0x04) << 3) | val 136 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h ((val & 0x02) << 5) | val 137 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h ((val & 0x01) << 7); val 667 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c unsigned long val; val 674 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c err = kstrtoul(s, 0, &val); val 677 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c if (val > 0xffff) val 679 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c adap->params.tp.la_mask = val << 16; val 887 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c static char *unit_conv(char *buf, size_t len, unsigned int val, val 890 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c unsigned int rem = val % factor; val 893 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c snprintf(buf, len, "%u", val / factor); val 897 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c snprintf(buf, len, "%u.%u", val / factor, rem); val 1699 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c u64 tcamy, tcamx, val; val 1719 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); val 1720 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c tcamy = DMACH_G(val) << 32; val 1731 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c (DATAVIDH1_G(data2) << 16) | VIDL_G(val); val 1735 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c ivlan = VIDL_G(val); val 1743 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); val 1744 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c tcamx = DMACH_G(val) << 32; val 1750 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c (DATAVIDH1_G(data2) << 16) | VIDL_G(val); val 1950 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c u32 param[7], val[7]; val 1963 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c param, val); val 1965 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c if (ret < 0 || val[0] == 0) val 1968 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c seq_printf(seq, "Temperature: %dC\n", val[0]); val 1970 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c if (ret < 0 || val[1] == 0) val 1973 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c seq_printf(seq, "Core VDD: %dmV\n", val[1]); val 21 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c static void set_msglevel(struct net_device *dev, u32 val) val 23 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c netdev2adap(dev)->msg_enable = val; val 336 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c unsigned int val; val 340 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c val = 0xffff; val 342 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c val = 0; val 346 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c return t4_identify_port(adap, adap->pf, netdev2pinfo(dev)->viid, val); val 954 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c u32 param, val; val 967 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c val = usecs; val 968 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); val 990 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c u32 param, val; val 1025 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c val = min_timerix; val 1027 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c 1, ¶m, &val); val 46 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c static inline bool is_field_set(u32 val, u32 mask) val 48 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c return val || mask; val 51 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c static inline bool unsupported(u32 conf, u32 conf_mask, u32 val, u32 mask) val 53 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c return !(conf & conf_mask) && is_field_set(val, mask); val 57 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsigned int ftid, u16 word, u64 mask, u64 val, val 74 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->val = cpu_to_be64(val); val 75 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); val 84 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsigned int val, int no_reply) val 87 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (unsigned long long)val << bit_pos, no_reply); val 122 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsigned int word, u64 mask, u64 val, val 137 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->val = cpu_to_be64(val); val 255 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (unsupported(fconf, FCOE_F, fs->val.fcoe, fs->mask.fcoe) || val 256 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, PORT_F, fs->val.iport, fs->mask.iport) || val 257 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, TOS_F, fs->val.tos, fs->mask.tos) || val 258 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, ETHERTYPE_F, fs->val.ethtype, val 260 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, MACMATCH_F, fs->val.macidx, fs->mask.macidx) || val 261 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, MPSHITTYPE_F, fs->val.matchtype, val 263 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, FRAGMENTATION_F, fs->val.frag, fs->mask.frag) || val 264 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, PROTOCOL_F, fs->val.proto, fs->mask.proto) || val 265 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, VNIC_ID_F, fs->val.pfvf_vld, val 267 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, VNIC_ID_F, fs->val.ovlan_vld, val 269 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, VNIC_ID_F, fs->val.encap_vld, val 271 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, VLAN_F, fs->val.ivlan_vld, fs->mask.ivlan_vld)) val 281 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if ((is_field_set(fs->val.pfvf_vld, fs->mask.pfvf_vld) && val 282 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c is_field_set(fs->val.ovlan_vld, fs->mask.ovlan_vld)) || val 283 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (is_field_set(fs->val.pfvf_vld, fs->mask.pfvf_vld) && val 284 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c is_field_set(fs->val.encap_vld, fs->mask.encap_vld)) || val 285 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (is_field_set(fs->val.ovlan_vld, fs->mask.ovlan_vld) && val 286 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c is_field_set(fs->val.encap_vld, fs->mask.encap_vld))) val 288 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (unsupported(iconf, VNIC_F, fs->val.pfvf_vld, fs->mask.pfvf_vld) || val 289 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (is_field_set(fs->val.ovlan_vld, fs->mask.ovlan_vld) && val 292 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.pf > 0x7 || fs->val.vf > 0x7f) val 306 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.iport >= adapter->params.nports) val 316 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.encap_vld && val 619 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ethtype = htons(f->fs.val.ethtype); val 622 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (FW_FILTER_WR_FRAG_V(f->fs.val.frag) | val 624 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) | val 625 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) | val 633 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) | val 635 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) | val 637 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_PORT_V(f->fs.val.iport) | val 639 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) | val 641 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ptcl = f->fs.val.proto; val 643 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ttyp = f->fs.val.tos; val 645 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ivlan = htons(f->fs.val.ivlan); val 647 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ovlan = htons(f->fs.val.ovlan); val 649 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip)); val 651 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip)); val 653 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->lp = htons(f->fs.val.lport); val 655 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->fp = htons(f->fs.val.fport); val 674 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); val 729 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (f->fs.val.encap_vld && f->fs.val.ovlan_vld) val 731 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan & 0x1ff, 0); val 734 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c cxgb4_clip_release(f->dev, (const u32 *)&f->fs.val.lip, 1); val 789 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.iport && !fs->mask.iport) val 791 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.fcoe && !fs->mask.fcoe) val 793 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.matchtype && !fs->mask.matchtype) val 795 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.macidx && !fs->mask.macidx) val 797 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.ethtype && !fs->mask.ethtype) val 799 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.ivlan && !fs->mask.ivlan) val 801 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.ovlan && !fs->mask.ovlan) val 803 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.frag && !fs->mask.frag) val 805 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.tos && !fs->mask.tos) val 807 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.proto && !fs->mask.proto) val 810 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c for (i = 0; i < ARRAY_SIZE(fs->val.lip); i++) { val 811 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c lip |= fs->val.lip[i]; val 813 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fip |= fs->val.fip[i]; val 823 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.lport && !fs->mask.lport) val 825 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.fport && !fs->mask.fport) val 887 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (is_inaddr_any(fs->val.fip, AF_INET6) || val 891 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (is_inaddr_any(fs->val.lip, AF_INET6) || val 895 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (is_inaddr_any(fs->val.fip, AF_INET) || val 899 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (is_inaddr_any(fs->val.lip, AF_INET) || val 904 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (!fs->val.lport || fs->mask.lport != 0xffff) val 907 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (!fs->val.fport || fs->mask.fport != 0xffff) val 963 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (FT_VLAN_VLD_F | fs->val.ivlan) << tp->vlan_shift; val 966 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)fs->val.iport << tp->port_shift; val 969 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (!fs->val.proto) val 972 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)fs->val.proto << tp->protocol_shift; val 976 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)(fs->val.tos) << tp->tos_shift; val 981 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)((fs->val.encap_vld << 16) | val 982 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (fs->val.ovlan)) << tp->vnic_shift; val 985 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)((fs->val.pfvf_vld << 16) | val 986 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (fs->val.pf << 13) | val 987 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (fs->val.vf)) << tp->vnic_shift; val 989 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)((fs->val.ovlan_vld << 16) | val 990 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (fs->val.ovlan)) << tp->vnic_shift; val 994 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)(fs->val.macidx) << tp->macmatch_shift; val 997 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)(fs->val.ethtype) << tp->ethertype_shift; val 1000 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)(fs->val.matchtype) << tp->matchtype_shift; val 1003 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)(fs->val.frag) << tp->frag_shift; val 1006 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple |= (u64)(fs->val.fcoe) << tp->fcoe_shift; val 1020 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->local_port = cpu_to_be16(f->fs.val.lport); val 1021 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->peer_port = cpu_to_be16(f->fs.val.fport); val 1022 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->local_ip_hi = *(__be64 *)(&f->fs.val.lip); val 1023 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->local_ip_lo = *(((__be64 *)&f->fs.val.lip) + 1); val 1024 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->peer_ip_hi = *(__be64 *)(&f->fs.val.fip); val 1025 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->peer_ip_lo = *(((__be64 *)&f->fs.val.fip) + 1); val 1061 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->local_port = cpu_to_be16(f->fs.val.lport); val 1062 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->peer_port = cpu_to_be16(f->fs.val.fport); val 1063 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c memcpy(&req->local_ip, f->fs.val.lip, 4); val 1064 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c memcpy(&req->peer_ip, f->fs.val.fip, 4); val 1159 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan = (fs->val.pf << 13) | fs->val.vf; val 1161 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan_vld = fs->val.pfvf_vld; val 1164 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (f->fs.val.encap_vld) { val 1172 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.vni, val 1178 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan = ret; val 1180 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan_vld = 1; val 1187 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ret = cxgb4_clip_get(f->dev, (const u32 *)&f->fs.val.lip, 1); val 1213 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c set_wr_txq(skb, CPL_PRIORITY_SETUP, f->fs.val.iport & 0x3); val 1218 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c cxgb4_clip_release(f->dev, (const u32 *)&f->fs.val.lip, 1); val 1221 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (f->fs.val.encap_vld && f->fs.val.ovlan_vld) val 1222 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c t4_free_encap_mac_filt(adapter, pi->viid, f->fs.val.ovlan, 1); val 1380 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ipv6_addr_type((const struct in6_addr *)fs->val.lip) != val 1382 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ret = cxgb4_clip_get(dev, (const u32 *)&fs->val.lip, 1); val 1401 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan = (fs->val.pf << 13) | fs->val.vf; val 1403 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan_vld = fs->val.pfvf_vld; val 1406 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (f->fs.val.encap_vld) { val 1414 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.vni, val 1420 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan = ret; val 1422 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.val.ovlan_vld = 1; val 1444 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c cxgb4_clip_release(f->dev, (const u32 *)&f->fs.val.lip, 1); val 1494 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); val 793 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c unsigned int param, val; val 805 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); val 813 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c if (val != 1) val 816 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); val 1845 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c u32 val; val 1853 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = PIDX_V(delta); val 1855 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = PIDX_T5_V(delta); val 1858 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c QID_V(qid) | val); val 2133 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c u32 val; val 2141 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = PIDX_V(delta); val 2143 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = PIDX_T5_V(delta); val 2146 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c QID_V(q->cntxt_id) | val); val 2484 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c u8 *val; val 2507 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c f->fs.val.lport = cpu_to_be16(sport); val 2509 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = (u8 *)&sip; val 2510 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c if ((val[0] | val[1] | val[2] | val[3]) != 0) { val 2512 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c f->fs.val.lip[i] = val[i]; val 2516 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c f->fs.val.iport = port; val 2522 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c f->fs.val.proto = IPPROTO_TCP; val 2981 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c u32 param, val; val 2989 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = FW_VF_LINK_STATE_AUTO; val 2993 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = FW_VF_LINK_STATE_ENABLE; val 2997 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = FW_VF_LINK_STATE_DISABLE; val 3007 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c ¶m, &val); val 3984 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c u32 finiver, finicsum, cfcsum, param, val; val 4040 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c u32 params[7], val[7]; val 4052 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adapter->pf, 0, 1, params, val); val 4068 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c mtype = FW_PARAMS_PARAM_Y_G(val[0]); val 4069 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; val 4098 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val = 0; val 4106 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 1, ¶m, &val); val 4293 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c u32 params[7], val[7]; val 4401 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c params, val); val 4482 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 1, params, val); val 4485 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->sge.dbqtimer_tick = val[0]; val 4516 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); val 4519 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->sge.egr_start = val[0]; val 4520 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->l2t_start = val[1]; val 4521 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->l2t_end = val[2]; val 4522 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->tids.ftid_base = val[3]; val 4523 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->tids.nftids = val[4] - val[3] + 1; val 4524 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->sge.ingr_start = val[5]; val 4533 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c params, val); val 4535 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->rawf_start = val[0]; val 4536 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->rawf_cnt = val[1] - val[0] + 1; val 4548 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); val 4551 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; val 4552 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; val 4596 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); val 4599 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->clipt_start = val[0]; val 4600 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->clipt_end = val[1]; val 4611 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); val 4615 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c if ((val[0] != val[1]) && (ret >= 0)) { val 4617 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->tids.aftid_base = val[0]; val 4618 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->tids.aftid_end = val[1]; val 4627 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val[0] = 1; val 4628 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); val 4641 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 1, params, val); val 4642 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); val 4648 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 1, params, val); val 4649 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); val 4657 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 1, params, val); val 4658 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); val 4667 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 1, params, val); val 4668 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0); val 4700 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c params, val); val 4703 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->tids.ntids = val[0]; val 4705 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->tids.stid_base = val[1]; val 4706 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->tids.nstids = val[2] - val[1] + 1; val 4724 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.ddp.start = val[3]; val 4725 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.ddp.size = val[4] - val[3] + 1; val 4726 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.ofldq_wr_cred = val[5]; val 4742 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c params, val); val 4745 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.stag.start = val[0]; val 4746 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.stag.size = val[1] - val[0] + 1; val 4747 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.rq.start = val[2]; val 4748 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.rq.size = val[3] - val[2] + 1; val 4749 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.pbl.start = val[4]; val 4750 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.pbl.size = val[5] - val[4] + 1; val 4755 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c params, val); val 4757 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.srq.start = val[0]; val 4758 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.srq.size = val[1] - val[0] + 1; val 4773 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val); val 4776 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.qp.start = val[0]; val 4777 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.qp.size = val[1] - val[0] + 1; val 4778 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.cq.start = val[2]; val 4779 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.cq.size = val[3] - val[2] + 1; val 4780 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.ocq.start = val[4]; val 4781 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.ocq.size = val[5] - val[4] + 1; val 4786 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val); val 4792 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.max_ordird_qp = val[0]; val 4793 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.max_ird_adapter = val[1]; val 4803 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val); val 4804 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.write_w_imm_support = (ret == 0 && val[0] != 0); val 4809 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val); val 4810 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->params.write_cmpl_support = (ret == 0 && val[0] != 0); val 4817 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c params, val); val 4820 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.iscsi.start = val[0]; val 4821 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.iscsi.size = val[1] - val[0] + 1; val 4826 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c params, val); val 4828 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.ppod_edram.start = val[0]; val 4830 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val[1] - val[0] + 1; val 4834 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c val[0], val[1], val 4846 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 2, params, val); val 4851 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.ncrypto_fc = val[0]; val 4860 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 2, params, val); val 4863 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.key.start = val[0]; val 4864 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->vres.key.size = val[1] - val[0] + 1; val 113 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.ethtype = ethtype_key; val 115 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.proto = match.key->ip_proto; val 124 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c memcpy(&fs->val.lip[0], &match.key->dst, sizeof(match.key->dst)); val 125 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c memcpy(&fs->val.fip[0], &match.key->src, sizeof(match.key->src)); val 139 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c memcpy(&fs->val.lip[0], match.key->dst.s6_addr, val 141 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c memcpy(&fs->val.fip[0], match.key->src.s6_addr, val 159 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.lport = cpu_to_be16(match.key->dst); val 161 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.fport = cpu_to_be16(match.key->src); val 173 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.tos = match.key->tos; val 181 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.vni = be32_to_cpu(match.key->keyid); val 184 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.encap_vld = 1; val 198 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.ivlan = vlan_tci; val 201 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.ivlan_vld = 1; val 213 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c if (fs->val.ethtype == ETH_P_8021Q) { val 214 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.ethtype = 0; val 222 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->val.iport = netdev2pinfo(dev)->port_id; val 275 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c static void offload_pedit(struct ch_filter_specification *fs, u32 val, u32 mask, val 278 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c u32 set_val = val & ~mask; val 293 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c static void process_pedit_field(struct ch_filter_specification *fs, u32 val, val 301 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, ETH_DMAC_31_0); val 305 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, ETH_DMAC_47_32); val 307 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val >> 16, mask >> 16, val 312 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, ETH_SMAC_47_16); val 318 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP4_SRC); val 321 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP4_DST); val 328 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_SRC_31_0); val 331 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_SRC_63_32); val 334 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_SRC_95_64); val 337 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_SRC_127_96); val 340 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_DST_31_0); val 343 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_DST_63_32); val 346 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_DST_95_64); val 349 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_DST_127_96); val 357 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, cpu_to_be32(val) >> 16, val 361 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, cpu_to_be32(val), val 370 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, cpu_to_be32(val) >> 16, val 374 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, cpu_to_be32(val), val 429 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c u32 mask, val, offset; val 434 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c val = act->mangle.val; val 437 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c process_pedit_field(fs, val, mask, offset, htype); val 50 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c u32 val, mask; val 56 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c val = cls->knode.sel->keys[i].val; val 71 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c for (j = 0; entry[j].val; j++) { val 74 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c err = entry[j].val(fs, val, mask); val 219 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c u32 val, mask; val 245 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c val = cls->knode.sel->keys[j].val; val 249 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c next[i].match_val == val && val 315 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c fs.val.iport = netdev2pinfo(dev)->port_id; val 41 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h int (*val)(struct ch_filter_specification *f, u32 val, u32 mask); val 46 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 48 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->val.tos = (ntohl(val) >> 16) & 0x000000FF; val 55 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 60 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h frag_val = (ntohl(val) >> 13) & 0x00000007; val 64 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->val.frag = 1; val 67 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->val.frag = 0; val 77 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 79 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->val.proto = (ntohl(val) >> 16) & 0x000000FF; val 86 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 88 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.fip[0], &val, sizeof(u32)); val 95 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 97 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.lip[0], &val, sizeof(u32)); val 104 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 0, .val = cxgb4_fill_ipv4_tos }, val 105 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 4, .val = cxgb4_fill_ipv4_frag }, val 106 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 8, .val = cxgb4_fill_ipv4_proto }, val 107 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 12, .val = cxgb4_fill_ipv4_src_ip }, val 108 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 16, .val = cxgb4_fill_ipv4_dst_ip }, val 109 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .val = NULL } val 114 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 116 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->val.tos = (ntohl(val) >> 20) & 0x000000FF; val 123 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 125 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->val.proto = (ntohl(val) >> 8) & 0x000000FF; val 132 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 134 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.fip[0], &val, sizeof(u32)); val 141 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 143 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.fip[4], &val, sizeof(u32)); val 150 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 152 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.fip[8], &val, sizeof(u32)); val 159 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 161 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.fip[12], &val, sizeof(u32)); val 168 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 170 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.lip[0], &val, sizeof(u32)); val 177 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 179 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.lip[4], &val, sizeof(u32)); val 186 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 188 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.lip[8], &val, sizeof(u32)); val 195 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 197 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->val.lip[12], &val, sizeof(u32)); val 204 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 0, .val = cxgb4_fill_ipv6_tos }, val 205 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 4, .val = cxgb4_fill_ipv6_proto }, val 206 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 8, .val = cxgb4_fill_ipv6_src_ip0 }, val 207 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 12, .val = cxgb4_fill_ipv6_src_ip1 }, val 208 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 16, .val = cxgb4_fill_ipv6_src_ip2 }, val 209 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 20, .val = cxgb4_fill_ipv6_src_ip3 }, val 210 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 24, .val = cxgb4_fill_ipv6_dst_ip0 }, val 211 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 28, .val = cxgb4_fill_ipv6_dst_ip1 }, val 212 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 32, .val = cxgb4_fill_ipv6_dst_ip2 }, val 213 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 36, .val = cxgb4_fill_ipv6_dst_ip3 }, val 214 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .val = NULL } val 219 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) val 221 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->val.fport = ntohl(val) >> 16; val 223 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->val.lport = ntohl(val) & 0x0000FFFF; val 230 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 0, .val = cxgb4_fill_l4_ports }, val 231 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .val = NULL } val 235 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .off = 0, .val = cxgb4_fill_l4_ports }, val 236 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .val = NULL } val 16 drivers/net/ethernet/chelsio/cxgb4/cxgb4_thermal.c u32 param, val; val 24 drivers/net/ethernet/chelsio/cxgb4/cxgb4_thermal.c ¶m, &val); val 25 drivers/net/ethernet/chelsio/cxgb4/cxgb4_thermal.c if (ret < 0 || val == 0) val 28 drivers/net/ethernet/chelsio/cxgb4/cxgb4_thermal.c *temp = val * 1000; val 66 drivers/net/ethernet/chelsio/cxgb4/cxgb4_thermal.c u32 param, val; val 77 drivers/net/ethernet/chelsio/cxgb4/cxgb4_thermal.c ¶m, &val); val 81 drivers/net/ethernet/chelsio/cxgb4/cxgb4_thermal.c ch_thermal->trip_temp = val * 1000; val 538 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 val = adap->params.arch.sge_fl_db; val 541 drivers/net/ethernet/chelsio/cxgb4/sge.c val |= PIDX_V(q->pend_cred / 8); val 543 drivers/net/ethernet/chelsio/cxgb4/sge.c val |= PIDX_T5_V(q->pend_cred / 8); val 556 drivers/net/ethernet/chelsio/cxgb4/sge.c val | QID_V(q->cntxt_id)); val 558 drivers/net/ethernet/chelsio/cxgb4/sge.c writel(val | QID_V(q->bar2_qid), val 971 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 val = PIDX_V(n); val 980 drivers/net/ethernet/chelsio/cxgb4/sge.c QID_V(q->cntxt_id) | val); val 986 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 val = PIDX_T5_V(n); val 994 drivers/net/ethernet/chelsio/cxgb4/sge.c WARN_ON(val & DBPRIO_F); val 1010 drivers/net/ethernet/chelsio/cxgb4/sge.c writel(val | QID_V(q->bar2_qid), val 1256 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 val; val 1263 drivers/net/ethernet/chelsio/cxgb4/sge.c val = CPL_TX_TNL_LSO_OPCODE_V(CPL_TX_TNL_LSO) | val 1272 drivers/net/ethernet/chelsio/cxgb4/sge.c tnl_lso->op_to_IpIdSplitOut = htonl(val); val 1277 drivers/net/ethernet/chelsio/cxgb4/sge.c val = skb_inner_mac_header(skb) - skb_mac_header(skb); val 1294 drivers/net/ethernet/chelsio/cxgb4/sge.c htons(CPL_TX_TNL_LSO_TNLHDRLEN_V(val) | val 1299 drivers/net/ethernet/chelsio/cxgb4/sge.c val = CPL_TX_TNL_LSO_ETHHDRLEN_V(in_eth_xtra_len / 4) | val 1303 drivers/net/ethernet/chelsio/cxgb4/sge.c tnl_lso->Flow_to_TcpHdrLen = htonl(val); val 3238 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 val; val 3266 drivers/net/ethernet/chelsio/cxgb4/sge.c val = CIDXINC_V(work_done) | SEINTARM_V(params); val 3273 drivers/net/ethernet/chelsio/cxgb4/sge.c val | INGRESSQID_V((u32)q->cntxt_id)); val 3275 drivers/net/ethernet/chelsio/cxgb4/sge.c writel(val | INGRESSQID_V(q->bar2_qid), val 3302 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 val; val 3321 drivers/net/ethernet/chelsio/cxgb4/sge.c val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params); val 3328 drivers/net/ethernet/chelsio/cxgb4/sge.c val | INGRESSQID_V(q->cntxt_id)); val 3330 drivers/net/ethernet/chelsio/cxgb4/sge.c writel(val | INGRESSQID_V(q->bar2_qid), val 3658 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 param, val, ch_map = 0; val 3666 drivers/net/ethernet/chelsio/cxgb4/sge.c val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X); val 3668 drivers/net/ethernet/chelsio/cxgb4/sge.c val = val 3674 drivers/net/ethernet/chelsio/cxgb4/sge.c val |= CONMCTXT_CNGCHMAP_V(ch_map); val 3677 drivers/net/ethernet/chelsio/cxgb4/sge.c ¶m, &val); val 3874 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 param, val; val 3879 drivers/net/ethernet/chelsio/cxgb4/sge.c val = cmplqid; val 3880 drivers/net/ethernet/chelsio/cxgb4/sge.c return t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); val 61 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val = t4_read_reg(adapter, reg); val 63 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c if (!!(val & mask) == polarity) { val 65 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *valp = val; val 93 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val) val 97 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_write_reg(adapter, addr, v | val); val 152 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) val 165 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); val 733 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val, ldst_addrspace; val 759 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = be32_to_cpu(ldst_cmd.u.pcie.data[0]); val 764 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_hw_pci_read_cfg4(adap, reg, &val); val 765 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c return val; val 2992 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c int lock, u32 val) val 2998 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_write_reg(adapter, SF_DATA_A, val); val 3084 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int i, c, left, val, offset = addr & 0xff; val 3089 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = swab32(addr) | SF_PROG_PAGE; val 3092 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) val 3097 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c for (val = 0, i = 0; i < c; ++i) val 3098 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = (val << 8) + *data++; val 3100 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ret = sf1_write(adapter, c, c != left, 1, val); val 3742 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 param, val; val 3750 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ¶m, &val); val 3753 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *phy_fw_ver = val; val 3790 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 param, val; val 3820 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = phy_fw_size; val 3822 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ¶m, &val, 1, true); val 3825 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c mtype = val >> 8; val 3826 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c maddr = (val & 0xff) << 16; val 3851 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ¶m, &val, 30000); val 3892 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.param[0].val = cpu_to_be32(op); val 3902 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 cfg, val, req, rsp; val 3908 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = t4_read_reg(adap, CIM_DEBUGSTS_A); val 3909 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c req = POLADBGWRPTR_G(val); val 3910 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c rsp = PILADBGWRPTR_G(val); val 4600 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val, fw_err; val 4614 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A); val 4615 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c if (val & TIMER0INT_F) val 5091 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val = 0; val 5097 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F; val 5104 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val); val 5262 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c static int rd_rss_row(struct adapter *adap, int row, u32 *val) val 5266 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 5, 0, val); val 5279 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val; val 5283 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ret = rd_rss_row(adapter, i, &val); val 5286 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *map++ = LKPTBLQUEUE0_G(val); val 5287 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *map++ = LKPTBLQUEUE1_G(val); val 5327 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); val 5334 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c vals[i] = be32_to_cpu(c.u.addrval.val); val 5605 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1]; val 5608 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c #define STAT(x) val[STAT_IDX(x)] val 5612 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_tp_mib_read(adap, val, ARRAY_SIZE(val), val 5620 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_tp_mib_read(adap, val, ARRAY_SIZE(val), val 5710 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val[2]; val 5718 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx, val 5721 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c st->octets_ddp = ((u64)val[0] << 32) | val[1]; val 5735 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val[4]; val 5737 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok); val 5738 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c st->frames = val[0]; val 5739 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c st->drops = val[1]; val 5740 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c st->octets = ((u64)val[2] << 32) | val[3]; val 5797 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int mask, unsigned int val) val 5800 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; val 5801 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_write_reg(adap, TP_PIO_DATA_A, val); val 6184 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 param, val; val 6190 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 0, 1, ¶m, &val); val 6197 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c for (p = 0; p < MAX_NPORTS; p++, val >>= 8) val 6198 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c mps_bg_map[p] = val & 0xff; val 6220 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 param, val = 0; val 6236 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 0, 1, ¶m, &val); val 6238 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c return (val >> (8 * pidx)) & 0xff; val 6523 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 addr, u32 val) val 6536 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.u.addrval.val = cpu_to_be32(val); val 6587 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int mmd, unsigned int reg, u16 val) val 6601 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.u.mdio.rval = cpu_to_be16(val); val 7018 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.val = cpu_to_be32(reset); val 7051 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F); val 7458 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 *val, int rw, bool sleep_ok) val 7477 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *p = cpu_to_be32(*(val + i)); val 7483 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) val 7484 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *val++ = be32_to_cpu(*p); val 7490 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 *val) val 7492 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0, val 7498 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 *val) val 7500 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0, val 7521 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c const u32 *val, int timeout) val 7538 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *p++ = cpu_to_be32(*val++); val 7559 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c const u32 *val) val 7561 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, val 7808 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val; val 7815 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = FW_CMD_LEN16_V(1) | val 7818 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_CMD_LEN16_V(val)); val 7861 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val; val 7867 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = FW_CMD_LEN16_V(1) | val 7869 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.freemacs_to_len16 = cpu_to_be32(val); val 7908 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val; val 7914 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = FW_CMD_LEN16_V(1) | val 7916 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.freemacs_to_len16 = cpu_to_be32(val); val 8872 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u16 val; val 8875 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); val 8876 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c p->speed = val & PCI_EXP_LNKSTA_CLS; val 8877 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; val 9404 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 param, val, v; val 9425 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ¶m, &val); val 9429 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_PARAMS_PARAM_FILTER_MODE_G(val), val 9430 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_PARAMS_PARAM_FILTER_MASK_G(val)); val 9432 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_PARAMS_PARAM_FILTER_MODE_G(val); val 9434 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_PARAMS_PARAM_FILTER_MASK_G(val); val 9613 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 param, val; val 9617 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = 1; val 9618 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ret = t4_set_params(adapter, mbox, pf, vf, 1, ¶m, &val); val 9884 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int val) val 9886 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c return t4_cim_write(adap, addr, 1, &val); val 9902 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int cfg, val, idx; val 9914 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); val 9918 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c idx = UPDBGLAWRPTR_G(val); val 9927 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); val 9930 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c if (val & UPDBGLARDEN_F) { val 9971 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int i, cfg, val, idx; val 9978 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); val 9979 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c idx = DBGLAWPTR_G(val); val 9980 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0; val 9986 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val &= 0xffff; val 9987 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val &= ~DBGLARPTR_V(DBGLARPTR_M); val 9988 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val |= adap->params.tp.la_mask; val 9991 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); val 705 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h __be64 val; val 686 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h __be32 val; val 894 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h __be32 val; val 979 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h u8 val[33]; val 1023 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h __be32 val; val 1412 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h __be32 val; val 3577 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h u8 val[6]; val 442 drivers/net/ethernet/chelsio/cxgb4vf/adapter.h static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) val 444 drivers/net/ethernet/chelsio/cxgb4vf/adapter.h writel(val, adapter->regs + reg_addr); val 453 drivers/net/ethernet/chelsio/cxgb4vf/adapter.h static inline void writeq(u64 val, volatile void __iomem *addr) val 455 drivers/net/ethernet/chelsio/cxgb4vf/adapter.h writel(val, addr); val 456 drivers/net/ethernet/chelsio/cxgb4vf/adapter.h writel(val >> 32, addr + 4); val 481 drivers/net/ethernet/chelsio/cxgb4vf/adapter.h u64 val) val 483 drivers/net/ethernet/chelsio/cxgb4vf/adapter.h writeq(val, adapter->regs + reg_addr); val 1703 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c unsigned int val; val 1707 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c val = 0xffff; val 1709 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c val = 0; val 1713 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c return t4vf_identify_port(pi->adapter, pi->viid, val); val 2583 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c u32 param, val = 0; val 2653 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c val = 1; val 2654 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c (void) t4vf_set_params(adapter, 1, ¶m, &val); val 527 drivers/net/ethernet/chelsio/cxgb4vf/sge.c u32 val = adapter->params.arch.sge_fl_db; val 535 drivers/net/ethernet/chelsio/cxgb4vf/sge.c val |= PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT); val 537 drivers/net/ethernet/chelsio/cxgb4vf/sge.c val |= PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT); val 551 drivers/net/ethernet/chelsio/cxgb4vf/sge.c QID_V(fl->cntxt_id) | val); val 553 drivers/net/ethernet/chelsio/cxgb4vf/sge.c writel(val | QID_V(fl->bar2_qid), val 976 drivers/net/ethernet/chelsio/cxgb4vf/sge.c u32 val = PIDX_V(n); val 979 drivers/net/ethernet/chelsio/cxgb4vf/sge.c QID_V(tq->cntxt_id) | val); val 981 drivers/net/ethernet/chelsio/cxgb4vf/sge.c u32 val = PIDX_T5_V(n); val 989 drivers/net/ethernet/chelsio/cxgb4vf/sge.c WARN_ON(val & DBPRIO_F); val 1024 drivers/net/ethernet/chelsio/cxgb4vf/sge.c writel(val | QID_V(tq->bar2_qid), val 1893 drivers/net/ethernet/chelsio/cxgb4vf/sge.c u32 val; val 1905 drivers/net/ethernet/chelsio/cxgb4vf/sge.c val = CIDXINC_V(work_done) | SEINTARM_V(intr_params); val 1912 drivers/net/ethernet/chelsio/cxgb4vf/sge.c val | INGRESSQID_V((u32)rspq->cntxt_id)); val 1914 drivers/net/ethernet/chelsio/cxgb4vf/sge.c writel(val | INGRESSQID_V(rspq->bar2_qid), val 1942 drivers/net/ethernet/chelsio/cxgb4vf/sge.c u32 val; val 2008 drivers/net/ethernet/chelsio/cxgb4vf/sge.c val = CIDXINC_V(work_done) | SEINTARM_V(intrq->intr_params); val 2014 drivers/net/ethernet/chelsio/cxgb4vf/sge.c val | INGRESSQID_V(intrq->cntxt_id)); val 2016 drivers/net/ethernet/chelsio/cxgb4vf/sge.c writel(val | INGRESSQID_V(intrq->bar2_qid), val 55 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c u32 val; val 57 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c val = t4_read_reg(adapter, whoami); val 58 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c if (val != notready1 && val != notready2) val 61 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c val = t4_read_reg(adapter, whoami); val 62 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c if (val != notready1 && val != notready2) val 515 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c u32 param, val; val 519 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c val = 1; val 520 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c ret = t4vf_set_params(adapter, 1, ¶m, &val); val 647 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c *vals++ = be32_to_cpu(p->val); val 681 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c p->val = cpu_to_be32(*vals++); val 269 drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.h u32 val, u32 orig_tag, val 273 drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.h u32 v = val >> tformat->free_bits; val 277 drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.h val, tformat->free_bits); val 283 drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.h *final_tag = (val << tformat->rsvd_bits) | val 83 drivers/net/ethernet/cirrus/cs89x0.c #define cs89_dbg(val, level, fmt, ...) \ val 85 drivers/net/ethernet/cirrus/cs89x0.c if (val <= net_debug) \ val 181 drivers/net/ethernet/cirrus/ep93xx_eth.c #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off)) val 182 drivers/net/ethernet/cirrus/ep93xx_eth.c #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off)) val 183 drivers/net/ethernet/cirrus/ep93xx_eth.c #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off)) val 1229 drivers/net/ethernet/cisco/enic/vnic_dev.c *(struct filter *)&tlv->val = *data; val 1237 drivers/net/ethernet/cisco/enic/vnic_dev.c action = (struct filter_action *)&tlv->val; val 37 drivers/net/ethernet/cisco/enic/vnic_dev.h static inline void writeq(u64 val, void __iomem *reg) val 39 drivers/net/ethernet/cisco/enic/vnic_dev.h writel(val & 0xffffffff, reg); val 40 drivers/net/ethernet/cisco/enic/vnic_dev.h writel(val >> 32, reg + 0x4UL); val 653 drivers/net/ethernet/cisco/enic/vnic_devcmd.h u_int32_t val[0]; val 225 drivers/net/ethernet/cortina/gemini.c u32 val, u32 vmask) val 234 drivers/net/ethernet/cortina/gemini.c reg = (reg & ~vmask) | val; val 259 drivers/net/ethernet/cortina/gemini.c u32 val; val 263 drivers/net/ethernet/cortina/gemini.c val = readl(port->gmac_base + GMAC_CONFIG0); val 264 drivers/net/ethernet/cortina/gemini.c val |= CONFIG0_TX_RX_DISABLE; val 265 drivers/net/ethernet/cortina/gemini.c writel(val, port->gmac_base + GMAC_CONFIG0); val 276 drivers/net/ethernet/cortina/gemini.c u32 val; val 280 drivers/net/ethernet/cortina/gemini.c val = readl(port->gmac_base + GMAC_CONFIG0); val 281 drivers/net/ethernet/cortina/gemini.c val &= ~CONFIG0_FLOW_CTL; val 283 drivers/net/ethernet/cortina/gemini.c val |= CONFIG0_FLOW_TX; val 285 drivers/net/ethernet/cortina/gemini.c val |= CONFIG0_FLOW_RX; val 286 drivers/net/ethernet/cortina/gemini.c writel(val, port->gmac_base + GMAC_CONFIG0); val 415 drivers/net/ethernet/cortina/gemini.c u8 val; val 421 drivers/net/ethernet/cortina/gemini.c .val = CONFIG0_MAXLEN_1518, val 425 drivers/net/ethernet/cortina/gemini.c .val = CONFIG0_MAXLEN_1522, val 429 drivers/net/ethernet/cortina/gemini.c .val = CONFIG0_MAXLEN_1536, val 433 drivers/net/ethernet/cortina/gemini.c .val = CONFIG0_MAXLEN_1542, val 437 drivers/net/ethernet/cortina/gemini.c .val = CONFIG0_MAXLEN_9k, val 441 drivers/net/ethernet/cortina/gemini.c .val = CONFIG0_MAXLEN_10k, val 456 drivers/net/ethernet/cortina/gemini.c return maxlen->val; val 513 drivers/net/ethernet/cortina/gemini.c u32 val; val 523 drivers/net/ethernet/cortina/gemini.c val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG); val 1115 drivers/net/ethernet/cortina/gemini.c u32 val, mask; val 1124 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); val 1125 drivers/net/ethernet/cortina/gemini.c val = en ? val | mask : val & ~mask; val 1126 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); val 1312 drivers/net/ethernet/cortina/gemini.c u32 val, mask; val 1319 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); val 1320 drivers/net/ethernet/cortina/gemini.c val = enable ? (val | mask) : (val & ~mask); val 1321 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); val 1324 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); val 1325 drivers/net/ethernet/cortina/gemini.c val = enable ? (val | mask) : (val & ~mask); val 1326 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); val 1329 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); val 1330 drivers/net/ethernet/cortina/gemini.c val = enable ? (val | mask) : (val & ~mask); val 1331 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); val 1341 drivers/net/ethernet/cortina/gemini.c u32 val, mask; val 1348 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); val 1349 drivers/net/ethernet/cortina/gemini.c val = enable ? (val | mask) : (val & ~mask); val 1350 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); val 1648 drivers/net/ethernet/cortina/gemini.c unsigned int offs, val; val 1657 drivers/net/ethernet/cortina/gemini.c val = readl(irqif_reg) & readl(irqen_reg); val 1658 drivers/net/ethernet/cortina/gemini.c return val; val 1676 drivers/net/ethernet/cortina/gemini.c u32 val, orr = 0; val 1681 drivers/net/ethernet/cortina/gemini.c val = gmac_get_intr_flags(netdev, 0); val 1682 drivers/net/ethernet/cortina/gemini.c orr |= val; val 1684 drivers/net/ethernet/cortina/gemini.c if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) { val 1694 drivers/net/ethernet/cortina/gemini.c if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6))) val 1697 drivers/net/ethernet/cortina/gemini.c val = gmac_get_intr_flags(netdev, 1); val 1698 drivers/net/ethernet/cortina/gemini.c orr |= val; val 1700 drivers/net/ethernet/cortina/gemini.c if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) { val 1714 drivers/net/ethernet/cortina/gemini.c val = gmac_get_intr_flags(netdev, 4); val 1715 drivers/net/ethernet/cortina/gemini.c orr |= val; val 1717 drivers/net/ethernet/cortina/gemini.c if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8))) val 1720 drivers/net/ethernet/cortina/gemini.c if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) { val 2271 drivers/net/ethernet/cortina/gemini.c u32 val, en; val 2276 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); val 2279 drivers/net/ethernet/cortina/gemini.c if (val & en & SWFQ_EMPTY_INT_BIT) { val 2556 drivers/net/ethernet/cortina/gemini.c u32 val; val 2573 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_TOE_VERSION_REG); val 2575 drivers/net/ethernet/cortina/gemini.c } while (!val && --retry); val 2581 drivers/net/ethernet/cortina/gemini.c (val >> 4) & 0xFFFU, val & 0xFU); val 373 drivers/net/ethernet/dec/tulip/de2104x.c #define dw32(reg, val) iowrite32((val), de->regs + (reg)) val 145 drivers/net/ethernet/dec/tulip/dmfe.c #define dw32(reg, val) iowrite32(val, ioaddr + (reg)) val 146 drivers/net/ethernet/dec/tulip/dmfe.c #define dw16(reg, val) iowrite16(val, ioaddr + (reg)) val 109 drivers/net/ethernet/dec/tulip/media.c void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val) val 113 drivers/net/ethernet/dec/tulip/media.c int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff); val 123 drivers/net/ethernet/dec/tulip/media.c iowrite32(val, ioaddr + comet_miireg2offset[location]); val 37 drivers/net/ethernet/dec/tulip/uli526x.c #define uw32(reg, val) iowrite32(val, ioaddr + (reg)) val 43 drivers/net/ethernet/dec/tulip/xircom_cb.c #define xw32(reg, val) iowrite32(val, ioaddr + (reg)) val 501 drivers/net/ethernet/dec/tulip/xircom_cb.c u32 val; val 506 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR0); val 507 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= 0x01; /* Software reset */ val 508 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR0, val); val 512 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR0); val 513 drivers/net/ethernet/dec/tulip/xircom_cb.c val &= ~0x01; /* disable Software reset */ val 514 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR0, val); val 517 drivers/net/ethernet/dec/tulip/xircom_cb.c val = 0; /* Value 0x00 is a safe and conservative value val 519 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR0, val); val 627 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 629 drivers/net/ethernet/dec/tulip/xircom_cb.c val = 0; val 630 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR3, val); /* Receive descriptor address */ val 631 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR4, val); /* Send descriptor address */ val 643 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 645 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR5); /* Status register */ val 646 drivers/net/ethernet/dec/tulip/xircom_cb.c if (!(val & (1 << 27))) /* no change */ val 651 drivers/net/ethernet/dec/tulip/xircom_cb.c val = (1 << 27); val 652 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR5, val); val 699 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 702 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR6); /* Operation mode */ val 706 drivers/net/ethernet/dec/tulip/xircom_cb.c if ((val&2) && (receive_active(card))) val 710 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val & ~2; /* disable the receiver */ val 711 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR6, val); val 725 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR6); /* Operation mode */ val 726 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val | 2; /* enable the receiver */ val 727 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR6, val); val 753 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 756 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR6); /* Operation mode */ val 757 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val & ~2; /* disable the receiver */ val 758 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR6, val); val 786 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 789 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR6); /* Operation mode */ val 793 drivers/net/ethernet/dec/tulip/xircom_cb.c if ((val&(1<<13)) && (transmit_active(card))) val 796 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val & ~(1 << 13); /* disable the transmitter */ val 797 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR6, val); val 812 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR6); /* Operation mode */ val 813 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val | (1 << 13); /* enable the transmitter */ val 814 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR6, val); val 840 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 843 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR6); /* Operation mode */ val 844 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val & ~2; /* disable the transmitter */ val 845 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR6, val); val 869 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 871 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR7); /* Interrupt enable register */ val 872 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= 1; /* enable the transmit interrupt */ val 873 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR7, val); val 885 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 887 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR7); /* Interrupt enable register */ val 888 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val | (1 << 6); /* enable the receive interrupt */ val 889 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR7, val); val 900 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 902 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR7); /* Interrupt enable register */ val 903 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val | (1 << 27); /* enable the link status chage interrupt */ val 904 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR7, val); val 929 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 931 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR7); /* Interrupt enable register */ val 932 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= (1<<16); /* Normal Interrupt Summary */ val 933 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= (1<<15); /* Abnormal Interrupt Summary */ val 934 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= (1<<13); /* Fatal bus error */ val 935 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= (1<<8); /* Receive Process Stopped */ val 936 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= (1<<7); /* Receive Buffer Unavailable */ val 937 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= (1<<5); /* Transmit Underflow */ val 938 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= (1<<2); /* Transmit Buffer Unavailable */ val 939 drivers/net/ethernet/dec/tulip/xircom_cb.c val |= (1<<1); /* Transmit Process Stopped */ val 940 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR7, val); val 951 drivers/net/ethernet/dec/tulip/xircom_cb.c unsigned int val; val 953 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr32(CSR6); val 954 drivers/net/ethernet/dec/tulip/xircom_cb.c val = val | (1 << 6); val 955 drivers/net/ethernet/dec/tulip/xircom_cb.c xw32(CSR6, val); val 971 drivers/net/ethernet/dec/tulip/xircom_cb.c u8 val; val 973 drivers/net/ethernet/dec/tulip/xircom_cb.c val = xr8(CSR12); val 976 drivers/net/ethernet/dec/tulip/xircom_cb.c if (!(val & (1 << 2))) val 979 drivers/net/ethernet/dec/tulip/xircom_cb.c if (!(val & (1 << 1))) val 16 drivers/net/ethernet/dlink/dl2k.c #define dw32(reg, val) iowrite32(val, ioaddr + (reg)) val 17 drivers/net/ethernet/dlink/dl2k.c #define dw16(reg, val) iowrite16(val, ioaddr + (reg)) val 18 drivers/net/ethernet/dlink/dl2k.c #define dw8(reg, val) iowrite8(val, ioaddr + (reg)) val 1703 drivers/net/ethernet/dlink/sundance.c static void set_msglevel(struct net_device *dev, u32 val) val 1706 drivers/net/ethernet/dlink/sundance.c np->msg_enable = val; val 46 drivers/net/ethernet/dnet.c static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val) val 49 drivers/net/ethernet/dnet.c dnet_writel(bp, val, MACREG_DATA); val 136 drivers/net/ethernet/emulex/benet/be.h static inline u32 MODULO(u32 val, u32 limit) val 139 drivers/net/ethernet/emulex/benet/be.h return val & (limit - 1); val 142 drivers/net/ethernet/emulex/benet/be.h static inline void index_adv(u32 *index, u32 val, u32 limit) val 144 drivers/net/ethernet/emulex/benet/be.h *index = MODULO((*index + val), limit); val 455 drivers/net/ethernet/emulex/benet/be.h #define BE_WRB_F_SET(word, name, val) \ val 456 drivers/net/ethernet/emulex/benet/be.h ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) val 849 drivers/net/ethernet/emulex/benet/be.h #define AMAP_SET_BITS(_struct, field, ptr, val) \ val 854 drivers/net/ethernet/emulex/benet/be.h val) val 877 drivers/net/ethernet/emulex/benet/be.h #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ val 878 drivers/net/ethernet/emulex/benet/be.h AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) val 899 drivers/net/ethernet/emulex/benet/be.h u8 val = 0; val 902 drivers/net/ethernet/emulex/benet/be.h val = (ip_hdr(skb)->protocol == IPPROTO_TCP); val 904 drivers/net/ethernet/emulex/benet/be.h val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); val 906 drivers/net/ethernet/emulex/benet/be.h return val; val 911 drivers/net/ethernet/emulex/benet/be.h u8 val = 0; val 914 drivers/net/ethernet/emulex/benet/be.h val = (ip_hdr(skb)->protocol == IPPROTO_UDP); val 916 drivers/net/ethernet/emulex/benet/be.h val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); val 918 drivers/net/ethernet/emulex/benet/be.h return val; val 122 drivers/net/ethernet/emulex/benet/be_cmds.c u32 val = 0; val 127 drivers/net/ethernet/emulex/benet/be_cmds.c val |= mccq->id & DB_MCCQ_RING_ID_MASK; val 128 drivers/net/ethernet/emulex/benet/be_cmds.c val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; val 131 drivers/net/ethernet/emulex/benet/be_cmds.c iowrite32(val, adapter->db + DB_MCCQ_OFFSET); val 665 drivers/net/ethernet/emulex/benet/be_cmds.c u32 val = 0; val 676 drivers/net/ethernet/emulex/benet/be_cmds.c val |= MPU_MAILBOX_DB_HI_MASK; val 678 drivers/net/ethernet/emulex/benet/be_cmds.c val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; val 679 drivers/net/ethernet/emulex/benet/be_cmds.c iowrite32(val, db); val 686 drivers/net/ethernet/emulex/benet/be_cmds.c val = 0; val 688 drivers/net/ethernet/emulex/benet/be_cmds.c val |= (u32)(mbox_mem->dma >> 4) << 2; val 689 drivers/net/ethernet/emulex/benet/be_cmds.c iowrite32(val, db); val 522 drivers/net/ethernet/emulex/benet/be_ethtool.c u32 val = 0; val 528 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_TP; val 530 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_1000baseT_Full; val 532 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_100baseT_Full; val 534 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_10baseT_Full; val 537 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_Backplane; val 539 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_1000baseKX_Full; val 541 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_10000baseKX4_Full; val 544 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_Backplane; val 546 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_10000baseKR_Full; val 548 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_20000baseKR2_Full; val 551 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_Backplane | val 555 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_Backplane; val 557 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_10000baseKR_Full; val 559 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_40000baseKR4_Full; val 565 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_40000baseCR4_Full; val 568 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_40000baseLR4_Full; val 571 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_40000baseSR4_Full; val 579 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_FIBRE; val 581 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_10000baseT_Full; val 583 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_1000baseT_Full; val 586 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_TP; val 588 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_10000baseT_Full; val 590 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_1000baseT_Full; val 592 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_100baseT_Full; val 595 drivers/net/ethernet/emulex/benet/be_ethtool.c val |= SUPPORTED_TP; val 598 drivers/net/ethernet/emulex/benet/be_ethtool.c return val; val 210 drivers/net/ethernet/emulex/benet/be_main.c u32 val = 0; val 215 drivers/net/ethernet/emulex/benet/be_main.c val |= qid & DB_RQ_RING_ID_MASK; val 216 drivers/net/ethernet/emulex/benet/be_main.c val |= posted << DB_RQ_NUM_POSTED_SHIFT; val 219 drivers/net/ethernet/emulex/benet/be_main.c iowrite32(val, adapter->db + DB_RQ_OFFSET); val 225 drivers/net/ethernet/emulex/benet/be_main.c u32 val = 0; val 230 drivers/net/ethernet/emulex/benet/be_main.c val |= txo->q.id & DB_TXULP_RING_ID_MASK; val 231 drivers/net/ethernet/emulex/benet/be_main.c val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT; val 234 drivers/net/ethernet/emulex/benet/be_main.c iowrite32(val, adapter->db + txo->db_offset); val 241 drivers/net/ethernet/emulex/benet/be_main.c u32 val = 0; val 243 drivers/net/ethernet/emulex/benet/be_main.c val |= qid & DB_EQ_RING_ID_MASK; val 244 drivers/net/ethernet/emulex/benet/be_main.c val |= ((qid & DB_EQ_RING_ID_EXT_MASK) << DB_EQ_RING_ID_EXT_MASK_SHIFT); val 250 drivers/net/ethernet/emulex/benet/be_main.c val |= 1 << DB_EQ_REARM_SHIFT; val 252 drivers/net/ethernet/emulex/benet/be_main.c val |= 1 << DB_EQ_CLR_SHIFT; val 253 drivers/net/ethernet/emulex/benet/be_main.c val |= 1 << DB_EQ_EVNT_SHIFT; val 254 drivers/net/ethernet/emulex/benet/be_main.c val |= num_popped << DB_EQ_NUM_POPPED_SHIFT; val 255 drivers/net/ethernet/emulex/benet/be_main.c val |= eq_delay_mult_enc << DB_EQ_R2I_DLY_SHIFT; val 256 drivers/net/ethernet/emulex/benet/be_main.c iowrite32(val, adapter->db + DB_EQ_OFFSET); val 261 drivers/net/ethernet/emulex/benet/be_main.c u32 val = 0; val 263 drivers/net/ethernet/emulex/benet/be_main.c val |= qid & DB_CQ_RING_ID_MASK; val 264 drivers/net/ethernet/emulex/benet/be_main.c val |= ((qid & DB_CQ_RING_ID_EXT_MASK) << val 271 drivers/net/ethernet/emulex/benet/be_main.c val |= 1 << DB_CQ_REARM_SHIFT; val 272 drivers/net/ethernet/emulex/benet/be_main.c val |= num_popped << DB_CQ_NUM_POPPED_SHIFT; val 273 drivers/net/ethernet/emulex/benet/be_main.c iowrite32(val, adapter->db + DB_CQ_OFFSET); val 603 drivers/net/ethernet/emulex/benet/be_main.c static void accumulate_16bit_val(u32 *acc, u16 val) val 607 drivers/net/ethernet/emulex/benet/be_main.c bool wrapped = val < lo(*acc); val 608 drivers/net/ethernet/emulex/benet/be_main.c u32 newacc = hi(*acc) + val; val 3343 drivers/net/ethernet/emulex/benet/be_main.c u16 val; val 3391 drivers/net/ethernet/emulex/benet/be_main.c val = be_POST_stage_get(adapter); val 3392 drivers/net/ethernet/emulex/benet/be_main.c if ((val & POST_STAGE_FAT_LOG_START) val 3394 drivers/net/ethernet/emulex/benet/be_main.c (val & POST_STAGE_ARMFW_UE) val 3396 drivers/net/ethernet/emulex/benet/be_main.c (val & POST_STAGE_RECOVERABLE_ERR) val 5388 drivers/net/ethernet/emulex/benet/be_main.c u32 val; val 5391 drivers/net/ethernet/emulex/benet/be_main.c val = ioread32(adapter->pcicfg + SLIPORT_SOFTRESET_OFFSET); val 5392 drivers/net/ethernet/emulex/benet/be_main.c val |= SLIPORT_SOFTRESET_SR_MASK; val 5393 drivers/net/ethernet/emulex/benet/be_main.c iowrite32(val, adapter->pcicfg + SLIPORT_SOFTRESET_OFFSET); val 5404 drivers/net/ethernet/emulex/benet/be_main.c u32 val; val 5406 drivers/net/ethernet/emulex/benet/be_main.c val = be_POST_stage_get(adapter); val 5407 drivers/net/ethernet/emulex/benet/be_main.c if ((val & POST_STAGE_RECOVERABLE_ERR) != POST_STAGE_RECOVERABLE_ERR) val 5409 drivers/net/ethernet/emulex/benet/be_main.c ue_err_code = val & POST_ERR_RECOVERY_CODE_MASK; val 5446 drivers/net/ethernet/emulex/benet/be_main.c u32 val; val 5455 drivers/net/ethernet/emulex/benet/be_main.c val = be_POST_stage_get(adapter); val 5456 drivers/net/ethernet/emulex/benet/be_main.c if ((val & POST_STAGE_RECOVERABLE_ERR) != val 5459 drivers/net/ethernet/emulex/benet/be_main.c "Unrecoverable HW error detected: 0x%x\n", val); val 643 drivers/net/ethernet/ethoc.c static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) val 649 drivers/net/ethernet/ethoc.c ethoc_write(priv, MIITX_DATA, val); val 94 drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h #define dpni_set_field(var, field, val) \ val 95 drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field))) val 103 drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h #define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order)) val 11 drivers/net/ethernet/freescale/enetc/enetc.c #define ENETC_TXBDS_NEEDED(val) ((val) + 2) val 731 drivers/net/ethernet/freescale/enetc/enetc.c u32 val; val 734 drivers/net/ethernet/freescale/enetc/enetc.c val = enetc_rd(hw, ENETC_SICAPR0); val 735 drivers/net/ethernet/freescale/enetc/enetc.c si->num_rx_rings = (val >> 16) & 0xff; val 736 drivers/net/ethernet/freescale/enetc/enetc.c si->num_tx_rings = val & 0xff; val 738 drivers/net/ethernet/freescale/enetc/enetc.c val = enetc_rd(hw, ENETC_SIRFSCAPR); val 739 drivers/net/ethernet/freescale/enetc/enetc.c si->num_fs_entries = ENETC_SIRFSCAPR_GET_NUM_RFS(val); val 743 drivers/net/ethernet/freescale/enetc/enetc.c val = enetc_rd(hw, ENETC_SIPCAPR0); val 744 drivers/net/ethernet/freescale/enetc/enetc.c if (val & ENETC_SIPCAPR0_RSS) { val 745 drivers/net/ethernet/freescale/enetc/enetc.c val = enetc_rd(hw, ENETC_SIRSSCAPR); val 746 drivers/net/ethernet/freescale/enetc/enetc.c si->num_rss = ENETC_SIRSSCAPR_GET_NUM_RSS(val); val 546 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c u32 val = enetc_rxbdr_rd(hw, 0, ENETC_RBLENR); val 548 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c if (val != priv->rx_bd_count) val 549 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c netif_err(priv, hw, ndev, "RxBDR[RBLENR] = %d!\n", val); val 551 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c val = enetc_txbdr_rd(hw, 0, ENETC_TBLENR); val 553 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c if (val != priv->tx_bd_count) val 554 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c netif_err(priv, hw, ndev, "TxBDR[TBLENR] = %d!\n", val); val 60 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) val 61 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) val 99 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) val 101 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) val 130 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) val 167 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) val 170 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) val 171 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) val 174 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) val 175 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) val 190 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) val 215 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SET_TX_MTU(val) ((val) << 16) val 216 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) val 301 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_wr_reg(reg, val) iowrite32((val), (reg)) val 321 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) val 325 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) val 328 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) val 332 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_bdr_wr(hw, t, n, off, val) \ val 333 drivers/net/ethernet/freescale/enetc/enetc_hw.h enetc_wr(hw, ENETC_BDR(t, n, off), val) val 336 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_txbdr_wr(hw, n, off, val) \ val 337 drivers/net/ethernet/freescale/enetc/enetc_hw.h enetc_bdr_wr(hw, TX, n, off, val) val 338 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_rxbdr_wr(hw, n, off, val) \ val 339 drivers/net/ethernet/freescale/enetc/enetc_hw.h enetc_bdr_wr(hw, RX, n, off, val) val 388 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_L3_SET_HSIZE(val) ((((val) >> 2) & 0x7f) << 8) val 533 drivers/net/ethernet/freescale/enetc/enetc_hw.h u32 val = enetc_rxbdr_rd(hw, si_idx, ENETC_RBMR); val 535 drivers/net/ethernet/freescale/enetc/enetc_hw.h val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); val 536 drivers/net/ethernet/freescale/enetc/enetc_hw.h enetc_rxbdr_wr(hw, si_idx, ENETC_RBMR, val); val 542 drivers/net/ethernet/freescale/enetc/enetc_hw.h u32 val = enetc_txbdr_rd(hw, si_idx, ENETC_TBMR); val 544 drivers/net/ethernet/freescale/enetc/enetc_hw.h val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); val 545 drivers/net/ethernet/freescale/enetc/enetc_hw.h enetc_txbdr_wr(hw, si_idx, ENETC_TBMR, val); val 551 drivers/net/ethernet/freescale/enetc/enetc_hw.h u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); val 553 drivers/net/ethernet/freescale/enetc/enetc_hw.h val &= ~ENETC_TBMR_PRIO_MASK; val 554 drivers/net/ethernet/freescale/enetc/enetc_hw.h val |= ENETC_TBMR_SET_PRIO(prio); val 555 drivers/net/ethernet/freescale/enetc/enetc_hw.h enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); val 19 drivers/net/ethernet/freescale/enetc/enetc_mdio.c #define enetc_mdio_wr(hw, off, val) \ val 20 drivers/net/ethernet/freescale/enetc/enetc_mdio.c enetc_port_wr(hw, ENETC_##off + ENETC_MDIO_REG_OFFSET, val) val 40 drivers/net/ethernet/freescale/enetc/enetc_mdio.c u32 val; val 42 drivers/net/ethernet/freescale/enetc/enetc_mdio.c return readx_poll_timeout(enetc_mdio_rd_reg, MDIO_CFG, val, val 43 drivers/net/ethernet/freescale/enetc/enetc_mdio.c !(val & MDIO_CFG_BSY), 10, 10 * TIMEOUT); val 70 drivers/net/ethernet/freescale/enetc/enetc_msg.c u32 val; val 85 drivers/net/ethernet/freescale/enetc/enetc_msg.c val = lower_32_bits(msg->dma); val 86 drivers/net/ethernet/freescale/enetc/enetc_msg.c enetc_wr(hw, ENETC_PSIVMSGRCVAR0(idx), val); val 87 drivers/net/ethernet/freescale/enetc/enetc_msg.c val = upper_32_bits(msg->dma); val 88 drivers/net/ethernet/freescale/enetc/enetc_msg.c enetc_wr(hw, ENETC_PSIVMSGRCVAR1(idx), val); val 53 drivers/net/ethernet/freescale/enetc/enetc_pf.c u32 val = enetc_port_rd(hw, ENETC_PSIPVMR); val 55 drivers/net/ethernet/freescale/enetc/enetc_pf.c val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL); val 56 drivers/net/ethernet/freescale/enetc/enetc_pf.c enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val); val 88 drivers/net/ethernet/freescale/enetc/enetc_pf.c u32 val = 0; val 91 drivers/net/ethernet/freescale/enetc/enetc_pf.c val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan; val 93 drivers/net/ethernet/freescale/enetc/enetc_pf.c enetc_port_wr(hw, ENETC_PSIVLANR(si), val); val 443 drivers/net/ethernet/freescale/enetc/enetc_pf.c u32 val; val 446 drivers/net/ethernet/freescale/enetc/enetc_pf.c val = enetc_port_rd(hw, ENETC_PRFSCAPR); val 447 drivers/net/ethernet/freescale/enetc/enetc_pf.c num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val); val 464 drivers/net/ethernet/freescale/enetc/enetc_pf.c u32 val; val 466 drivers/net/ethernet/freescale/enetc/enetc_pf.c val = enetc_port_rd(hw, ENETC_PCAPR0); val 467 drivers/net/ethernet/freescale/enetc/enetc_pf.c num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val)); val 469 drivers/net/ethernet/freescale/enetc/enetc_pf.c val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS); val 470 drivers/net/ethernet/freescale/enetc/enetc_pf.c val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS); val 473 drivers/net/ethernet/freescale/enetc/enetc_pf.c val = ENETC_PSICFGR0_SET_TXBDR(num_rings); val 474 drivers/net/ethernet/freescale/enetc/enetc_pf.c val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); val 483 drivers/net/ethernet/freescale/enetc/enetc_pf.c val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); val 485 drivers/net/ethernet/freescale/enetc/enetc_pf.c enetc_port_wr(hw, ENETC_PSICFGR0(0), val); val 491 drivers/net/ethernet/freescale/enetc/enetc_pf.c val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); val 492 drivers/net/ethernet/freescale/enetc/enetc_pf.c val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE; val 496 drivers/net/ethernet/freescale/enetc/enetc_pf.c val |= ENETC_PSICFGR0_SET_TXBDR(num_rings); val 497 drivers/net/ethernet/freescale/enetc/enetc_pf.c val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); val 501 drivers/net/ethernet/freescale/enetc/enetc_pf.c enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val); val 504 drivers/net/ethernet/freescale/enetc/enetc_pf.c val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); val 505 drivers/net/ethernet/freescale/enetc/enetc_pf.c enetc_port_wr(hw, ENETC_PVCLCTR, val); val 20 drivers/net/ethernet/freescale/enetc/enetc_vf.c u32 val; val 22 drivers/net/ethernet/freescale/enetc/enetc_vf.c val = enetc_vsi_set_msize(msg->size) | lower_32_bits(msg->dma); val 24 drivers/net/ethernet/freescale/enetc/enetc_vf.c enetc_wr(hw, ENETC_VSIMSGSNDAR0, val); val 953 drivers/net/ethernet/freescale/fec_main.c u32 val; val 1004 drivers/net/ethernet/freescale/fec_main.c val = readl(fep->hwp + FEC_RACC); val 1006 drivers/net/ethernet/freescale/fec_main.c val |= FEC_RACC_SHIFT16; val 1009 drivers/net/ethernet/freescale/fec_main.c val |= FEC_RACC_OPTIONS; val 1011 drivers/net/ethernet/freescale/fec_main.c val &= ~FEC_RACC_OPTIONS; val 1012 drivers/net/ethernet/freescale/fec_main.c writel(val, fep->hwp + FEC_RACC); val 1156 drivers/net/ethernet/freescale/fec_main.c u32 val; val 1180 drivers/net/ethernet/freescale/fec_main.c val = readl(fep->hwp + FEC_ECNTRL); val 1181 drivers/net/ethernet/freescale/fec_main.c val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); val 1182 drivers/net/ethernet/freescale/fec_main.c writel(val, fep->hwp + FEC_ECNTRL); val 3804 drivers/net/ethernet/freescale/fec_main.c int val; val 3822 drivers/net/ethernet/freescale/fec_main.c val = readl(fep->hwp + FEC_ECNTRL); val 3823 drivers/net/ethernet/freescale/fec_main.c val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); val 3824 drivers/net/ethernet/freescale/fec_main.c writel(val, fep->hwp + FEC_ECNTRL); val 101 drivers/net/ethernet/freescale/fec_ptp.c u32 val, tempval; val 104 drivers/net/ethernet/freescale/fec_ptp.c val = 0; val 128 drivers/net/ethernet/freescale/fec_ptp.c val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); val 130 drivers/net/ethernet/freescale/fec_ptp.c val &= ~(FEC_T_TMODE_MASK); val 131 drivers/net/ethernet/freescale/fec_ptp.c writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); val 132 drivers/net/ethernet/freescale/fec_ptp.c val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); val 133 drivers/net/ethernet/freescale/fec_ptp.c } while (val & FEC_T_TMODE_MASK); val 156 drivers/net/ethernet/freescale/fec_ptp.c val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval; val 169 drivers/net/ethernet/freescale/fec_ptp.c val += NSEC_PER_SEC; val 177 drivers/net/ethernet/freescale/fec_ptp.c val &= fep->cc.mask; val 178 drivers/net/ethernet/freescale/fec_ptp.c writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); val 181 drivers/net/ethernet/freescale/fec_ptp.c fep->next_counter = (val + fep->reload_period) & fep->cc.mask; val 184 drivers/net/ethernet/freescale/fec_ptp.c val = readl(fep->hwp + FEC_ATIME_CTRL); val 185 drivers/net/ethernet/freescale/fec_ptp.c val |= FEC_T_CTRL_PINPER; val 186 drivers/net/ethernet/freescale/fec_ptp.c writel(val, fep->hwp + FEC_ATIME_CTRL); val 189 drivers/net/ethernet/freescale/fec_ptp.c val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); val 190 drivers/net/ethernet/freescale/fec_ptp.c val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); val 191 drivers/net/ethernet/freescale/fec_ptp.c val &= ~(1 << FEC_T_TDRE_OFFSET); val 192 drivers/net/ethernet/freescale/fec_ptp.c val &= ~(FEC_T_TMODE_MASK); val 193 drivers/net/ethernet/freescale/fec_ptp.c val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET); val 194 drivers/net/ethernet/freescale/fec_ptp.c writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); val 537 drivers/net/ethernet/freescale/fec_ptp.c u32 val; val 541 drivers/net/ethernet/freescale/fec_ptp.c val = readl(fep->hwp + FEC_TCSR(channel)); val 542 drivers/net/ethernet/freescale/fec_ptp.c if (val & FEC_T_TF_MASK) { val 548 drivers/net/ethernet/freescale/fec_ptp.c writel(val, fep->hwp + FEC_TCSR(channel)); val 2718 drivers/net/ethernet/freescale/fman/fman.c u32 val, range[2]; val 2731 drivers/net/ethernet/freescale/fman/fman.c err = of_property_read_u32(fm_node, "cell-index", &val); val 2737 drivers/net/ethernet/freescale/fman/fman.c fman->dts_params.id = (u8)val; val 396 drivers/net/ethernet/freescale/fman/fman_memac.c static void set_exception(struct memac_regs __iomem *regs, u32 val, val 403 drivers/net/ethernet/freescale/fman/fman_memac.c tmp |= val; val 405 drivers/net/ethernet/freescale/fman/fman_memac.c tmp &= ~val; val 1137 drivers/net/ethernet/freescale/fman/fman_port.c int val; val 1143 drivers/net/ethernet/freescale/fman/fman_port.c val = 12; val 1145 drivers/net/ethernet/freescale/fman/fman_port.c val = 3; val 1149 drivers/net/ethernet/freescale/fman/fman_port.c val = 8; val 1151 drivers/net/ethernet/freescale/fman/fman_port.c val = 2; val 1161 drivers/net/ethernet/freescale/fman/fman_port.c val = 8; val 1163 drivers/net/ethernet/freescale/fman/fman_port.c val = 1; val 1166 drivers/net/ethernet/freescale/fman/fman_port.c val = 0; val 1170 drivers/net/ethernet/freescale/fman/fman_port.c return val; val 1196 drivers/net/ethernet/freescale/fman/fman_port.c int val; val 1202 drivers/net/ethernet/freescale/fman/fman_port.c val = 64; val 1204 drivers/net/ethernet/freescale/fman/fman_port.c val = 50; val 1208 drivers/net/ethernet/freescale/fman/fman_port.c val = 96; val 1210 drivers/net/ethernet/freescale/fman/fman_port.c val = 50; val 1213 drivers/net/ethernet/freescale/fman/fman_port.c val = 0; val 1219 drivers/net/ethernet/freescale/fman/fman_port.c val = 48; val 1221 drivers/net/ethernet/freescale/fman/fman_port.c val = 44; val 1225 drivers/net/ethernet/freescale/fman/fman_port.c val = 48; val 1227 drivers/net/ethernet/freescale/fman/fman_port.c val = 45; val 1230 drivers/net/ethernet/freescale/fman/fman_port.c val = 0; val 1234 drivers/net/ethernet/freescale/fman/fman_port.c return val; val 1761 drivers/net/ethernet/freescale/fman/fman_port.c u32 val; val 1790 drivers/net/ethernet/freescale/fman/fman_port.c err = of_property_read_u32(port_node, "cell-index", &val); val 1797 drivers/net/ethernet/freescale/fman/fman_port.c port_id = (u8)val; val 609 drivers/net/ethernet/freescale/fman/mac.c u32 val; val 667 drivers/net/ethernet/freescale/fman/mac.c err = of_property_read_u32(dev_node, "cell-index", &val); val 674 drivers/net/ethernet/freescale/fman/mac.c fman_id = (u8)(val + 1); val 717 drivers/net/ethernet/freescale/fman/mac.c err = of_property_read_u32(mac_node, "cell-index", &val); val 723 drivers/net/ethernet/freescale/fman/mac.c priv->cell_index = (u8)val; val 75 drivers/net/ethernet/freescale/fs_enet/mii-fec.c static int fs_enet_fec_mii_write(struct mii_bus *bus, int phy_id, int location, u16 val) val 85 drivers/net/ethernet/freescale/fs_enet/mii-fec.c out_be32(&fecp->fec_mii_data, (phy_id << 23) | mk_mii_write(location, val)); val 1477 drivers/net/ethernet/freescale/gianfar.c u32 val = 0; val 1480 drivers/net/ethernet/freescale/gianfar.c return val; val 1484 drivers/net/ethernet/freescale/gianfar.c val |= MACCFG1_TX_FLOW; val 1486 drivers/net/ethernet/freescale/gianfar.c val |= MACCFG1_RX_FLOW; val 1500 drivers/net/ethernet/freescale/gianfar.c val |= MACCFG1_TX_FLOW; val 1502 drivers/net/ethernet/freescale/gianfar.c val |= MACCFG1_RX_FLOW; val 1505 drivers/net/ethernet/freescale/gianfar.c return val; val 1182 drivers/net/ethernet/freescale/gianfar.h u32 val; val 1183 drivers/net/ethernet/freescale/gianfar.h val = ioread32be(addr); val 1184 drivers/net/ethernet/freescale/gianfar.h return val; val 1187 drivers/net/ethernet/freescale/gianfar.h static inline void gfar_write(unsigned __iomem *addr, u32 val) val 1189 drivers/net/ethernet/freescale/gianfar.h iowrite32be(val, addr); val 316 drivers/net/ethernet/freescale/ucc_geth.c u32 val = *p_start; val 320 drivers/net/ethernet/freescale/ucc_geth.c if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { val 322 drivers/net/ethernet/freescale/ucc_geth.c (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> val 328 drivers/net/ethernet/freescale/ucc_geth.c (val & ENET_INIT_PARAM_PTR_MASK); val 351 drivers/net/ethernet/freescale/ucc_geth.c u32 val = in_be32(p_start); val 355 drivers/net/ethernet/freescale/ucc_geth.c if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { val 357 drivers/net/ethernet/freescale/ucc_geth.c (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> val 16 drivers/net/ethernet/google/gve/gve_tx.c u32 val) val 18 drivers/net/ethernet/google/gve/gve_tx.c iowrite32be(val, &priv->db_bar2[be32_to_cpu(q_resources->db_index)]); val 259 drivers/net/ethernet/hisilicon/hip04_eth.c u32 val; val 267 drivers/net/ethernet/hisilicon/hip04_eth.c val = SGMII_SPEED_1000; val 269 drivers/net/ethernet/hisilicon/hip04_eth.c val = SGMII_SPEED_100; val 271 drivers/net/ethernet/hisilicon/hip04_eth.c val = SGMII_SPEED_10; val 275 drivers/net/ethernet/hisilicon/hip04_eth.c val = MII_SPEED_100; val 277 drivers/net/ethernet/hisilicon/hip04_eth.c val = MII_SPEED_10; val 281 drivers/net/ethernet/hisilicon/hip04_eth.c val = MII_SPEED_10; val 284 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_PORT_MODE); val 286 drivers/net/ethernet/hisilicon/hip04_eth.c val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF; val 287 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_DUPLEX_TYPE); val 289 drivers/net/ethernet/hisilicon/hip04_eth.c val = GE_MODE_CHANGE_EN; val 290 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG); val 302 drivers/net/ethernet/hisilicon/hip04_eth.c u32 val, tmp, timeout = 0; val 305 drivers/net/ethernet/hisilicon/hip04_eth.c regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val); val 309 drivers/net/ethernet/hisilicon/hip04_eth.c } while (val & 0xfff); val 314 drivers/net/ethernet/hisilicon/hip04_eth.c u32 val; val 316 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + PPE_CFG_STS_MODE); val 317 drivers/net/ethernet/hisilicon/hip04_eth.c val |= PPE_CFG_STS_RX_PKT_CNT_RC; val 318 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_STS_MODE); val 320 drivers/net/ethernet/hisilicon/hip04_eth.c val = BIT(priv->group); val 321 drivers/net/ethernet/hisilicon/hip04_eth.c regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val); val 323 drivers/net/ethernet/hisilicon/hip04_eth.c val = priv->group << PPE_CFG_QOS_VMID_GRP_SHIFT; val 324 drivers/net/ethernet/hisilicon/hip04_eth.c val |= PPE_CFG_QOS_VMID_MODE; val 325 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN); val 327 drivers/net/ethernet/hisilicon/hip04_eth.c val = RX_BUF_SIZE >> PPE_BUF_SIZE_SHIFT; val 328 drivers/net/ethernet/hisilicon/hip04_eth.c regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val); val 330 drivers/net/ethernet/hisilicon/hip04_eth.c val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT; val 331 drivers/net/ethernet/hisilicon/hip04_eth.c val |= PPE_CFG_RX_FIFO_FSFU; val 332 drivers/net/ethernet/hisilicon/hip04_eth.c val |= priv->chan << PPE_CFG_RX_START_SHIFT; val 333 drivers/net/ethernet/hisilicon/hip04_eth.c regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val); val 335 drivers/net/ethernet/hisilicon/hip04_eth.c val = NET_IP_ALIGN << PPE_CFG_RX_CTRL_ALIGN_SHIFT; val 336 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG); val 338 drivers/net/ethernet/hisilicon/hip04_eth.c val = PPE_CFG_RX_PKT_ALIGN; val 339 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG); val 341 drivers/net/ethernet/hisilicon/hip04_eth.c val = PPE_CFG_BUS_LOCAL_REL | PPE_CFG_BUS_BIG_ENDIEN; val 342 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG); val 344 drivers/net/ethernet/hisilicon/hip04_eth.c val = GMAC_PPE_RX_PKT_MAX_LEN; val 345 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG); val 347 drivers/net/ethernet/hisilicon/hip04_eth.c val = GMAC_MAX_PKT_LEN; val 348 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG); val 350 drivers/net/ethernet/hisilicon/hip04_eth.c val = GMAC_MIN_PKT_LEN; val 351 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG); val 353 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG); val 354 drivers/net/ethernet/hisilicon/hip04_eth.c val |= GE_TX_AUTO_NEG | GE_TX_ADD_CRC | GE_TX_SHORT_PAD_THROUGH; val 355 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG); val 357 drivers/net/ethernet/hisilicon/hip04_eth.c val = GE_RX_STRIP_CRC; val 358 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG); val 360 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG); val 361 drivers/net/ethernet/hisilicon/hip04_eth.c val |= GE_RX_STRIP_PAD | GE_RX_PAD_EN; val 362 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG); val 365 drivers/net/ethernet/hisilicon/hip04_eth.c val = GE_AUTO_NEG_CTL; val 366 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG); val 373 drivers/net/ethernet/hisilicon/hip04_eth.c u32 val; val 376 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + GE_PORT_EN); val 377 drivers/net/ethernet/hisilicon/hip04_eth.c val |= GE_RX_PORT_EN | GE_TX_PORT_EN; val 378 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_PORT_EN); val 381 drivers/net/ethernet/hisilicon/hip04_eth.c val = RCV_INT; val 382 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_RINT); val 385 drivers/net/ethernet/hisilicon/hip04_eth.c val = GE_RX_INT_THRESHOLD | GE_RX_TIMEOUT; val 386 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT); val 396 drivers/net/ethernet/hisilicon/hip04_eth.c u32 val; val 403 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + GE_PORT_EN); val 404 drivers/net/ethernet/hisilicon/hip04_eth.c val &= ~(GE_RX_PORT_EN | GE_TX_PORT_EN); val 405 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_PORT_EN); val 410 drivers/net/ethernet/hisilicon/hip04_eth.c u32 val; val 412 drivers/net/ethernet/hisilicon/hip04_eth.c val = phys >> PPE_BUF_SIZE_SHIFT | PPE_TX_BUF_HOLD; val 413 drivers/net/ethernet/hisilicon/hip04_eth.c writel(val, priv->base + PPE_CFG_CPU_ADD_ADDR); val 418 drivers/net/ethernet/hisilicon/hip04_eth.c u32 val; val 420 drivers/net/ethernet/hisilicon/hip04_eth.c val = phys >> PPE_BUF_SIZE_SHIFT; val 421 drivers/net/ethernet/hisilicon/hip04_eth.c regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, val); val 128 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 130 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_IRQ_ENA); val 131 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val | irqs, priv->glb_base + GLB_IRQ_ENA); val 136 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 138 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_IRQ_ENA); val 139 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA); val 157 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 161 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->port_base + ADDRQ_STAT) & TX_CNT_INUSE_MASK; val 162 drivers/net/ethernet/hisilicon/hisi_femac.c while (val < priv->tx_fifo_used_cnt) { val 166 drivers/net/ethernet/hisilicon/hisi_femac.c val, priv->tx_fifo_used_cnt); val 176 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->port_base + ADDRQ_STAT) & TX_CNT_INUSE_MASK; val 445 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 447 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_SOFT_RESET); val 448 drivers/net/ethernet/hisilicon/hisi_femac.c val |= SOFT_RESET_ALL; val 449 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + GLB_SOFT_RESET); val 453 drivers/net/ethernet/hisilicon/hisi_femac.c val &= ~SOFT_RESET_ALL; val 454 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + GLB_SOFT_RESET); val 505 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 507 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->port_base + ADDRQ_STAT); val 508 drivers/net/ethernet/hisilicon/hisi_femac.c val &= BIT_TX_READY; val 509 drivers/net/ethernet/hisilicon/hisi_femac.c if (!val) { val 569 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 571 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_MAC_H16(reg_n)); val 573 drivers/net/ethernet/hisilicon/hisi_femac.c val |= BIT_MACFLT_ENA; val 575 drivers/net/ethernet/hisilicon/hisi_femac.c val &= ~BIT_MACFLT_ENA; val 576 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + GLB_MAC_H16(reg_n)); val 584 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 589 drivers/net/ethernet/hisilicon/hisi_femac.c val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; val 590 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + low); val 592 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + high); val 593 drivers/net/ethernet/hisilicon/hisi_femac.c val &= ~MACFLT_HI16_MASK; val 594 drivers/net/ethernet/hisilicon/hisi_femac.c val |= ((addr[0] << 8) | addr[1]); val 595 drivers/net/ethernet/hisilicon/hisi_femac.c val |= (BIT_MACFLT_ENA | BIT_MACFLT_FW2CPU); val 596 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + high); val 602 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 604 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_FWCTRL); val 606 drivers/net/ethernet/hisilicon/hisi_femac.c val |= FWCTRL_FWALL2CPU; val 608 drivers/net/ethernet/hisilicon/hisi_femac.c val &= ~FWCTRL_FWALL2CPU; val 609 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + GLB_FWCTRL); val 616 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 618 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_MACTCTRL); val 621 drivers/net/ethernet/hisilicon/hisi_femac.c val |= MACTCTRL_MULTI2CPU; val 634 drivers/net/ethernet/hisilicon/hisi_femac.c val &= ~MACTCTRL_MULTI2CPU; val 636 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + GLB_MACTCTRL); val 643 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 645 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_MACTCTRL); val 647 drivers/net/ethernet/hisilicon/hisi_femac.c val |= MACTCTRL_UNI2CPU; val 660 drivers/net/ethernet/hisilicon/hisi_femac.c val &= ~MACTCTRL_UNI2CPU; val 662 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + GLB_MACTCTRL); val 746 drivers/net/ethernet/hisilicon/hisi_femac.c u32 val; val 749 drivers/net/ethernet/hisilicon/hisi_femac.c val = MAC_PORTSEL_STAT_CPU; val 751 drivers/net/ethernet/hisilicon/hisi_femac.c val |= MAC_PORTSEL_RMII; val 752 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->port_base + MAC_PORTSEL); val 758 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_FWCTRL); val 759 drivers/net/ethernet/hisilicon/hisi_femac.c val &= ~(FWCTRL_VLAN_ENABLE | FWCTRL_FWALL2CPU); val 760 drivers/net/ethernet/hisilicon/hisi_femac.c val |= FWCTRL_FW2CPU_ENA; val 761 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + GLB_FWCTRL); val 763 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->glb_base + GLB_MACTCTRL); val 764 drivers/net/ethernet/hisilicon/hisi_femac.c val |= (MACTCTRL_BROAD2CPU | MACTCTRL_MACT_ENA); val 765 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->glb_base + GLB_MACTCTRL); val 767 drivers/net/ethernet/hisilicon/hisi_femac.c val = readl(priv->port_base + MAC_SET); val 768 drivers/net/ethernet/hisilicon/hisi_femac.c val &= ~MAX_FRAME_SIZE_MASK; val 769 drivers/net/ethernet/hisilicon/hisi_femac.c val |= MAX_FRAME_SIZE; val 770 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->port_base + MAC_SET); val 772 drivers/net/ethernet/hisilicon/hisi_femac.c val = RX_COALESCED_TIMER | val 774 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->port_base + RX_COALESCE_SET); val 776 drivers/net/ethernet/hisilicon/hisi_femac.c val = (HW_RX_FIFO_DEPTH << RX_DEPTH_OFFSET) | HW_TX_FIFO_DEPTH; val 777 drivers/net/ethernet/hisilicon/hisi_femac.c writel(val, priv->port_base + QLEN_SET); val 287 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c u32 val; val 295 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = RGMII_SPEED_1000; val 297 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = RGMII_SPEED_100; val 299 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = RGMII_SPEED_10; val 303 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = MII_SPEED_100; val 305 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = MII_SPEED_10; val 309 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = MII_SPEED_10; val 314 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val |= GMAC_FULL_DUPLEX; val 315 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->ctrl_base); val 320 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = GMAC_SPEED_1000; val 322 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = GMAC_SPEED_100; val 324 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = GMAC_SPEED_10; val 325 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->base + PORT_MODE); val 387 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c u32 val; val 397 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = RX_BQ_INT_THRESHOLD | TX_RQ_INT_THRESHOLD << QUEUE_TX_BQ_SHIFT; val 398 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->base + IN_QUEUE_TH); val 433 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c u32 val; val 435 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = mac[1] | (mac[0] << 8); val 436 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->base + STATION_ADDR_HIGH); val 438 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24); val 439 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->base + STATION_ADDR_LOW); val 936 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c int val, ret; val 947 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = readl_relaxed(base + MDIO_RDATA_STATUS); val 948 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c if (val & MDIO_R_VALID) { val 954 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = readl_relaxed(priv->base + MDIO_SINGLE_DATA); val 955 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c ret = (val >> 16) & 0xFFFF; val 960 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c static int hix5hd2_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) val 970 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, base + MDIO_SINGLE_DATA); val 480 drivers/net/ethernet/hisilicon/hns/hnae.h void (*toggle_ring_irq)(struct hnae_ring *ring, u32 val); val 699 drivers/net/ethernet/hisilicon/hns/hnae.h #define hnae_set_field(origin, mask, shift, val) \ val 702 drivers/net/ethernet/hisilicon/hns/hnae.h (origin) |= ((val) << (shift)) & (mask); \ val 705 drivers/net/ethernet/hisilicon/hns/hnae.h #define hnae_set_bit(origin, shift, val) \ val 706 drivers/net/ethernet/hisilicon/hns/hnae.h hnae_set_field((origin), (0x1 << (shift)), (shift), (val)) val 187 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c static void hns_ae_ring_enable_all(struct hnae_handle *handle, int val) val 193 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c hns_rcb_ring_enable_hw(handle->qs[i], val); val 328 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c u32 val; val 332 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c val = dsaf_read_dev(drv, GMAC_FIFO_STATE_REG); val 334 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c if ((val & 0x3f) == 0) val 478 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c u32 val = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG); val 479 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c u32 sta_addr_en = dsaf_get_bit(val, GMAC_ADDR_EN_B); val 1514 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c (soft_mac_entry->tcam_key.high.val == mac_key->high.val) && val 1515 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c (soft_mac_entry->tcam_key.low.val == mac_key->low.val)) val 1643 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.high.val, mac_key.low.val); val 1650 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_dev->ae_dev.name, mac_key.high.val, val 1651 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.low.val, entry_index); val 1660 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c tcam_data.tbl_tcam_data_high = mac_key.high.val; val 1661 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c tcam_data.tbl_tcam_data_low = mac_key.low.val; val 1668 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c soft_mac_entry->tcam_key.high.val = mac_key.high.val; val 1669 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c soft_mac_entry->tcam_key.low.val = mac_key.low.val; val 1699 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.high.val, mac_key.low.val); val 1705 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_dev->ae_dev.name, mac_key.high.val, val 1706 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.low.val, entry_index); val 1802 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_dev->ae_dev.name, mac_key.high.val, val 1803 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.low.val); val 1822 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.high.val, mac_key.low.val); val 1831 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_dev->ae_dev.name, mac_key.high.val, val 1832 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.low.val, entry_index); val 1834 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c tcam_data.tbl_tcam_data_high = mac_key.high.val; val 1835 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c tcam_data.tbl_tcam_data_low = mac_key.low.val; val 1844 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c soft_mac_entry->tcam_key.high.val = mac_key.high.val; val 1845 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c soft_mac_entry->tcam_key.low.val = mac_key.low.val; val 1883 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.high.val, mac_key.low.val); val 1888 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_dev->ae_dev.name, mac_key.high.val, val 1889 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.low.val, entry_index); val 1967 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.high.val, mac_key.low.val); val 1973 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_dev->ae_dev.name, mac_key.high.val, val 1974 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.low.val, entry_index); val 1989 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mac_key.high.val, mac_key.low.val); val 2003 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c tcam_data.tbl_tcam_data_high = mac_key.high.val; val 2004 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c tcam_data.tbl_tcam_data_low = mac_key.low.val; val 2798 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c soft_mac_entry->tcam_key.high.val = mac_key.high.val; val 2799 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c soft_mac_entry->tcam_key.low.val = mac_key.low.val; val 2826 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mask_key.high.val, mask_key.low.val); val 2838 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c mask_key.high.val, mask_key.low.val); val 2852 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c soft_mac_entry->tcam_key.high.val = temp_key.high.val; val 2853 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c soft_mac_entry->tcam_key.low.val = temp_key.low.val; val 2916 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c u32 val, val_tmp; val 2924 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c val = dsaf_read_dev(dsaf_dev, DSAF_VOQ_IN_PKT_NUM_0_REG + val 2928 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c if (val == val_tmp) val 2936 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c val, val_tmp); val 372 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h u32 val; val 381 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h u32 val; val 33 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val) val 36 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val); val 38 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_write_reg(dsaf_dev->sc_base, reg, val); val 192 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c u32 val = 0; val 201 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c &val); val 205 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_set_bit(val, DSAF_LED_ANCHOR_B, CPLD_LED_ON_VALUE); val 207 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c val); val 208 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c mac_cb->cpld_led_value = val; val 251 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c u32 port_type, u32 port, u32 val) val 261 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c obj_args[2].integer.value = val; val 570 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c u32 val = 0; val 578 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c &val); val 582 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c *sfp_prsnt = !val; val 278 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c u32 val; val 282 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c val = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG) & 0x3ffU; val 283 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c if (!val) val 291 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c val); val 196 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val) val 198 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val); val 201 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c void hns_rcb_start(struct hnae_queue *q, u32 val) val 203 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c hns_rcb_ring_enable_hw(q, val); val 119 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h void hns_rcb_start(struct hnae_queue *q, u32 val); val 126 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val); val 1035 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline int dsaf_read_syscon(struct regmap *base, u32 reg, u32 *val) val 1037 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h return regmap_read(base, reg, val); val 1043 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_set_field(origin, mask, shift, val) \ val 1046 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h (origin) |= (((val) << (shift)) & (mask)); \ val 1049 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_set_bit(origin, shift, val) \ val 1050 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_set_field((origin), (1ull << (shift)), (shift), (val)) val 1053 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h u32 shift, u32 val) val 1057 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_set_field(origin, mask, shift, val); val 1061 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_set_dev_field(dev, reg, mask, shift, val) \ val 1062 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val)) val 1064 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_set_dev_bit(dev, reg, bit, val) \ val 1065 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_set_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit), (val)) val 123 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c u32 val = 0; val 125 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c dsaf_set_bit(val, XGMAC_UNIDIR_EN_B, 0); val 126 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c dsaf_set_bit(val, XGMAC_RF_TX_EN_B, 1); val 127 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c dsaf_set_field(val, XGMAC_LF_RF_INSERT_M, XGMAC_LF_RF_INSERT_S, 0); val 128 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c dsaf_write_dev(mac_drv, XGMAC_MAC_TX_LF_RF_CONTROL_REG, val); val 653 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define hnae3_set_field(origin, mask, shift, val) \ val 656 drivers/net/ethernet/hisilicon/hns3/hnae3.h (origin) |= ((val) << (shift)) & (mask); \ val 660 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define hnae3_set_bit(origin, shift, val) \ val 661 drivers/net/ethernet/hisilicon/hns3/hnae3.h hnae3_set_field((origin), (0x1 << (shift)), (shift), (val)) val 28 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) val 3164 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 val, reg, reg_bit; val 3203 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c val = hclge_read_dev(&hdev->hw, reg); val 3204 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { val 3206 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c val = hclge_read_dev(&hdev->hw, reg); val 3355 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 val; val 3367 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); val 3368 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); val 3369 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); val 136 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define hclge_tm_set_field(dest, string, val) \ val 139 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h (HCLGE_TM_SHAP_##string##_LSH), val) val 1404 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c u32 val; val 1413 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c HCLGEVF_VF_RST_ING, val, val 1414 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c !(val & HCLGEVF_VF_RST_ING_BIT), val 1419 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c HCLGEVF_RST_ING, val, val 1420 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c !(val & HCLGEVF_RST_ING_BITS), val 1899 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c u32 val, cmdq_stat_reg, rst_ing_reg; val 1917 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); val 1919 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c val | HCLGEVF_VF_RST_ING_BIT); val 108 drivers/net/ethernet/hisilicon/hns_mdio.c #define mdio_set_field(origin, mask, shift, val) \ val 111 drivers/net/ethernet/hisilicon/hns_mdio.c (origin) |= (((val) & (mask)) << (shift)); \ val 117 drivers/net/ethernet/hisilicon/hns_mdio.c u32 val) val 121 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_set_field(origin, mask, shift, val); val 125 drivers/net/ethernet/hisilicon/hns_mdio.c #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \ val 126 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val)) val 1629 drivers/net/ethernet/hp/hp100.c u_short val; val 1698 drivers/net/ethernet/hp/hp100.c val = hp100_inw(IRQ_STATUS); val 1704 drivers/net/ethernet/hp/hp100.c dev->name, val, hp100_inw(IRQ_MASK), (int) skb->len); val 1986 drivers/net/ethernet/hp/hp100.c u_short val; val 1995 drivers/net/ethernet/hp/hp100.c val = hp100_inw(DROPPED) & 0x0fff; val 1996 drivers/net/ethernet/hp/hp100.c dev->stats.rx_errors += val; val 1997 drivers/net/ethernet/hp/hp100.c dev->stats.rx_over_errors += val; val 1998 drivers/net/ethernet/hp/hp100.c val = hp100_inb(CRC); val 1999 drivers/net/ethernet/hp/hp100.c dev->stats.rx_errors += val; val 2000 drivers/net/ethernet/hp/hp100.c dev->stats.rx_crc_errors += val; val 2001 drivers/net/ethernet/hp/hp100.c val = hp100_inb(ABORT); val 2002 drivers/net/ethernet/hp/hp100.c dev->stats.tx_errors += val; val 2003 drivers/net/ethernet/hp/hp100.c dev->stats.tx_aborted_errors += val; val 2186 drivers/net/ethernet/hp/hp100.c u_int val; val 2201 drivers/net/ethernet/hp/hp100.c val = hp100_inw(IRQ_STATUS); val 2204 drivers/net/ethernet/hp/hp100.c dev->name, lp->mode, (u_int) val, hp100_inb(RX_PKT_CNT), val 2208 drivers/net/ethernet/hp/hp100.c if (val == 0) { /* might be a shared interrupt */ val 2221 drivers/net/ethernet/hp/hp100.c if (val & HP100_RX_PDL_FILL_COMPL) { val 2237 drivers/net/ethernet/hp/hp100.c if (val & HP100_RX_PACKET) { /* Receive Packet Counter is non zero */ val 2240 drivers/net/ethernet/hp/hp100.c else if (!(val & HP100_RX_PDL_FILL_COMPL)) { val 2252 drivers/net/ethernet/hp/hp100.c hp100_outw(val, IRQ_STATUS); val 2260 drivers/net/ethernet/hp/hp100.c if (val & (HP100_TX_ERROR | HP100_RX_ERROR)) { val 2274 drivers/net/ethernet/hp/hp100.c if ((lp->mode == 1) && (val & (HP100_RX_PDA_ZERO))) val 2281 drivers/net/ethernet/hp/hp100.c if ((lp->mode == 1) && (val & (HP100_TX_COMPLETE))) val 2288 drivers/net/ethernet/hp/hp100.c if (val & HP100_MISC_ERROR) { /* New for J2585B */ val 2375 drivers/net/ethernet/hp/hp100.c u_int val; val 2389 drivers/net/ethernet/hp/hp100.c val = hp100_inw(OPTION_LSW); val 2394 drivers/net/ethernet/hp/hp100.c if (!(val & HP100_HW_RST)) val 2397 drivers/net/ethernet/hp/hp100.c for (val = 0; val < 6000; val++) val 2587 drivers/net/ethernet/hp/hp100.c u_short val = 0; val 2680 drivers/net/ethernet/hp/hp100.c val = hp100_inb(VG_LAN_CFG_1); val 2681 drivers/net/ethernet/hp/hp100.c if ((val & (HP100_LINK_UP_ST))) { val 2693 drivers/net/ethernet/hp/hp100.c if (time_before_eq(jiffies, time) && (val & HP100_LINK_UP_ST)) { val 2697 drivers/net/ethernet/hp/hp100.c val = hp100_inw(TRAIN_ALLOW); val 2700 drivers/net/ethernet/hp/hp100.c printk("Driver will use MAC Version \"%s\"\n", (val & HP100_HUB_MACVER) ? "802.12" : "Pre"); val 2701 drivers/net/ethernet/hp/hp100.c printk("hp100: %s: Frame format is %s.\n", dev->name, (val & HP100_MALLOW_FRAMEFMT) ? "802.5" : "802.3"); val 2709 drivers/net/ethernet/hp/hp100.c val = hp100_inw(TRAIN_ALLOW); /* won't work on non-ETR card */ val 2711 drivers/net/ethernet/hp/hp100.c printk("hp100: %s: MAC Configuration requested: 0x%04x, HUB allowed: 0x%04x\n", dev->name, hp100_inw(TRAIN_REQUEST), val); val 2713 drivers/net/ethernet/hp/hp100.c if (val & HP100_MALLOW_ACCDENIED) val 2715 drivers/net/ethernet/hp/hp100.c if (val & HP100_MALLOW_CONFIGURE) val 2717 drivers/net/ethernet/hp/hp100.c if (val & HP100_MALLOW_DUPADDR) val 2730 drivers/net/ethernet/hp/hp100.c val = hp100_inb(VG_LAN_CFG_1); val 2736 drivers/net/ethernet/hp/hp100.c if (val & HP100_LINK_UP_ST) val 79 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c u8 *val, checksum = 0; val 81 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = data; val 84 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c checksum ^= val[idx]; val 107 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c u32 addr, val; val 110 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = hinic_hwif_read_reg(chain->hwif, addr); val 112 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c return HINIC_API_CMD_STATUS_GET(val, CONS_IDX); val 416 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c u32 reg_addr, val; val 420 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = hinic_hwif_read_reg(hwif, reg_addr); val 422 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = HINIC_API_CMD_CHAIN_REQ_CLEAR(val, RESTART); val 423 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val |= HINIC_API_CMD_CHAIN_REQ_SET(1, RESTART); val 425 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c hinic_hwif_write_reg(hwif, reg_addr, val); val 429 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = hinic_hwif_read_reg(hwif, reg_addr); val 431 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c if (!HINIC_API_CMD_CHAIN_REQ_GET(val, RESTART)) { val 479 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c u32 addr, val; val 482 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = upper_32_bits(chain->wb_status_paddr); val 483 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c hinic_hwif_write_reg(hwif, addr, val); val 486 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = lower_32_bits(chain->wb_status_paddr); val 487 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c hinic_hwif_write_reg(hwif, addr, val); val 497 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c u32 addr, val; val 500 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = chain->num_cells; val 501 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c hinic_hwif_write_reg(hwif, addr, val); val 511 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c u32 addr, val; val 514 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = upper_32_bits(chain->head_cell_paddr); val 515 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c hinic_hwif_write_reg(hwif, addr, val); val 518 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = lower_32_bits(chain->head_cell_paddr); val 519 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c hinic_hwif_write_reg(hwif, addr, val); val 19 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_PI_SET(val, member) \ val 20 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((u32)(val) & HINIC_API_CMD_PI_##member##_MASK) << \ val 23 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_PI_CLEAR(val, member) \ val 24 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((val) & (~(HINIC_API_CMD_PI_##member##_MASK \ val 31 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_CHAIN_REQ_SET(val, member) \ val 32 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((u32)(val) & HINIC_API_CMD_CHAIN_REQ_##member##_MASK) << \ val 35 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_CHAIN_REQ_GET(val, member) \ val 36 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((val) >> HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT) & \ val 39 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_CHAIN_REQ_CLEAR(val, member) \ val 40 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((val) & (~(HINIC_API_CMD_CHAIN_REQ_##member##_MASK \ val 57 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_CHAIN_CTRL_SET(val, member) \ val 58 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((u32)(val) & HINIC_API_CMD_CHAIN_CTRL_##member##_MASK) << \ val 61 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_CHAIN_CTRL_CLEAR(val, member) \ val 62 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((val) & (~(HINIC_API_CMD_CHAIN_CTRL_##member##_MASK \ val 75 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_CELL_CTRL_SET(val, member) \ val 76 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((((u64)val) & HINIC_API_CMD_CELL_CTRL_##member##_MASK) << \ val 93 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_DESC_SET(val, member) \ val 94 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((((u64)val) & HINIC_API_CMD_DESC_##member##_MASK) << \ val 101 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_STATUS_HEADER_GET(val, member) \ val 102 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((val) >> HINIC_API_CMD_STATUS_HEADER_##member##_SHIFT) & \ val 111 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h #define HINIC_API_CMD_STATUS_GET(val, member) \ val 112 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((val) >> HINIC_API_CMD_STATUS_##member##_SHIFT) & \ val 38 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c #define CMDQ_CEQE_GET(val, member) \ val 39 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c (((val) >> CMDQ_CEQE_##member##_SHIFT) \ val 46 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c #define CMDQ_WQE_ERRCODE_GET(val, member) \ val 47 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c (((val) >> CMDQ_WQE_ERRCODE_##member##_SHIFT) \ val 30 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h #define HINIC_CMDQ_CTXT_PAGE_INFO_SET(val, member) \ val 31 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((u64)(val) & HINIC_CMDQ_CTXT_##member##_MASK) \ val 34 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h #define HINIC_CMDQ_CTXT_PAGE_INFO_CLEAR(val, member) \ val 35 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h ((val) & (~((u64)HINIC_CMDQ_CTXT_##member##_MASK \ val 44 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h #define HINIC_CMDQ_CTXT_BLOCK_INFO_SET(val, member) \ val 45 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((u64)(val) & HINIC_CMDQ_CTXT_##member##_MASK) \ val 48 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h #define HINIC_CMDQ_CTXT_BLOCK_INFO_CLEAR(val, member) \ val 49 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h ((val) & (~((u64)HINIC_CMDQ_CTXT_##member##_MASK \ val 56 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h #define HINIC_SAVED_DATA_SET(val, member) \ val 57 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((u32)(val) & HINIC_SAVED_DATA_##member##_MASK) \ val 60 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h #define HINIC_SAVED_DATA_GET(val, member) \ val 61 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((val) >> HINIC_SAVED_DATA_##member##_SHIFT) \ val 64 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h #define HINIC_SAVED_DATA_CLEAR(val, member) \ val 65 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h ((val) & (~(HINIC_SAVED_DATA_##member##_MASK \ val 78 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h #define HINIC_CMDQ_DB_INFO_SET(val, member) \ val 79 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((u32)(val) & HINIC_CMDQ_DB_INFO_##member##_MASK) \ val 176 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c static u8 eq_cons_idx_checksum_set(u32 val) val 182 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c checksum ^= ((val >> idx) & 0xF); val 193 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c u32 val, addr = EQ_CONS_IDX_REG_ADDR(eq); val 196 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = hinic_hwif_read_reg(eq->hwif, addr); val 198 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = HINIC_EQ_CI_CLEAR(val, IDX) & val 199 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_EQ_CI_CLEAR(val, WRAPPED) & val 200 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_EQ_CI_CLEAR(val, INT_ARMED) & val 201 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_EQ_CI_CLEAR(val, XOR_CHKSUM); val 203 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= HINIC_EQ_CI_SET(eq->cons_idx, IDX) | val 207 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= HINIC_EQ_CI_SET(eq_cons_idx_checksum_set(val), XOR_CHKSUM); val 209 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c hinic_hwif_write_reg(eq->hwif, addr, val); val 423 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c u32 addr, val, ctrl0; val 429 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = hinic_hwif_read_reg(eq->hwif, addr); val 431 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = HINIC_AEQ_CTRL_0_CLEAR(val, INT_IDX) & val 432 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_AEQ_CTRL_0_CLEAR(val, DMA_ATTR) & val 433 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_AEQ_CTRL_0_CLEAR(val, PCI_INTF_IDX) & val 434 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_AEQ_CTRL_0_CLEAR(val, INT_MODE); val 442 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= ctrl0; val 444 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c hinic_hwif_write_reg(eq->hwif, addr, val); val 449 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = hinic_hwif_read_reg(eq->hwif, addr); val 451 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = HINIC_CEQ_CTRL_0_CLEAR(val, INTR_IDX) & val 452 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_CEQ_CTRL_0_CLEAR(val, DMA_ATTR) & val 453 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_CEQ_CTRL_0_CLEAR(val, KICK_THRESH) & val 454 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_CEQ_CTRL_0_CLEAR(val, PCI_INTF_IDX) & val 455 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_CEQ_CTRL_0_CLEAR(val, INTR_MODE); val 464 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= ctrl0; val 466 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c hinic_hwif_write_reg(eq->hwif, addr, val); val 474 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c u32 addr, val, ctrl1; val 483 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = hinic_hwif_read_reg(eq->hwif, addr); val 485 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = HINIC_AEQ_CTRL_1_CLEAR(val, LEN) & val 486 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_AEQ_CTRL_1_CLEAR(val, ELEM_SIZE) & val 487 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_AEQ_CTRL_1_CLEAR(val, PAGE_SIZE); val 493 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= ctrl1; val 495 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c hinic_hwif_write_reg(eq->hwif, addr, val); val 502 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = hinic_hwif_read_reg(eq->hwif, addr); val 504 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = HINIC_CEQ_CTRL_1_CLEAR(val, LEN) & val 505 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c HINIC_CEQ_CTRL_1_CLEAR(val, PAGE_SIZE); val 510 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= ctrl1; val 512 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c hinic_hwif_write_reg(eq->hwif, addr, val); val 572 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c u32 init_val, addr, val; val 599 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = upper_32_bits(eq->dma_addr[pg]); val 601 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c hinic_hwif_write_reg(hwif, addr, val); val 604 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = lower_32_bits(eq->dma_addr[pg]); val 606 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c hinic_hwif_write_reg(hwif, addr, val); val 29 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_AEQ_CTRL_0_SET(val, member) \ val 30 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_AEQ_CTRL_0_##member##_MASK) << \ val 33 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_AEQ_CTRL_0_CLEAR(val, member) \ val 34 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_AEQ_CTRL_0_##member##_MASK \ val 45 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_AEQ_CTRL_1_SET(val, member) \ val 46 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_AEQ_CTRL_1_##member##_MASK) << \ val 49 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_AEQ_CTRL_1_CLEAR(val, member) \ val 50 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_AEQ_CTRL_1_##member##_MASK \ val 65 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_CEQ_CTRL_0_SET(val, member) \ val 66 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_CEQ_CTRL_0_##member##_MASK) << \ val 69 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_CEQ_CTRL_0_CLEAR(val, member) \ val 70 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_CEQ_CTRL_0_##member##_MASK \ val 79 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_CEQ_CTRL_1_SET(val, member) \ val 80 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_CEQ_CTRL_1_##member##_MASK) << \ val 83 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_CEQ_CTRL_1_CLEAR(val, member) \ val 84 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_CEQ_CTRL_1_##member##_MASK \ val 97 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_EQ_ELEM_DESC_SET(val, member) \ val 98 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_EQ_ELEM_DESC_##member##_MASK) << \ val 101 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_EQ_ELEM_DESC_GET(val, member) \ val 102 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((val) >> HINIC_EQ_ELEM_DESC_##member##_SHIFT) & \ val 115 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_EQ_CI_SET(val, member) \ val 116 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_EQ_CI_##member##_MASK) << \ val 119 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_EQ_CI_CLEAR(val, member) \ val 120 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_EQ_CI_##member##_MASK \ val 72 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c u32 addr, val; val 78 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c val = hinic_hwif_read_reg(hwif, addr); val 80 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c *pending_limit = HINIC_MSIX_ATTR_GET(val, PENDING_LIMIT); val 81 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c *coalesc_timer = HINIC_MSIX_ATTR_GET(val, COALESC_TIMER); val 82 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c *lli_timer = HINIC_MSIX_ATTR_GET(val, LLI_TIMER); val 83 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c *lli_credit_limit = HINIC_MSIX_ATTR_GET(val, LLI_CREDIT); val 84 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c *resend_timer = HINIC_MSIX_ATTR_GET(val, RESEND_TIMER); val 243 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c u32 addr, val, ppf_election; val 248 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c val = hinic_hwif_read_reg(hwif, addr); val 249 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c val = HINIC_PPF_ELECTION_CLEAR(val, IDX); val 253 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c val |= ppf_election; val 254 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c hinic_hwif_write_reg(hwif, addr, val); val 257 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c val = hinic_hwif_read_reg(hwif, addr); val 259 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX); val 279 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c u32 addr, val, dma_attr_entry; val 284 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c val = hinic_hwif_read_reg(hwif, addr); val 285 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c val = HINIC_DMA_ATTR_CLEAR(val, ST) & val 286 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c HINIC_DMA_ATTR_CLEAR(val, AT) & val 287 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c HINIC_DMA_ATTR_CLEAR(val, PH) & val 288 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c HINIC_DMA_ATTR_CLEAR(val, NO_SNOOPING) & val 289 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c HINIC_DMA_ATTR_CLEAR(val, TPH_EN); val 297 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c val |= dma_attr_entry; val 298 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c hinic_hwif_write_reg(hwif, addr, val); val 27 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_DMA_ATTR_SET(val, member) \ val 28 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \ val 31 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_DMA_ATTR_CLEAR(val, member) \ val 32 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((val) & (~(HINIC_DMA_ATTR_##member##_MASK \ val 46 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_FA0_GET(val, member) \ val 47 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK) val 64 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_FA1_GET(val, member) \ val 65 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK) val 73 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_FA4_GET(val, member) \ val 74 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK) val 76 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_FA4_SET(val, member) \ val 77 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT) val 79 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_FA4_CLEAR(val, member) \ val 80 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT))) val 85 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_FA5_SET(val, member) \ val 86 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT) val 88 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_FA5_CLEAR(val, member) \ val 89 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT))) val 94 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_PPF_ELECTION_SET(val, member) \ val 95 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \ val 98 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_PPF_ELECTION_GET(val, member) \ val 99 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \ val 102 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_PPF_ELECTION_CLEAR(val, member) \ val 103 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \ val 118 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_MSIX_ATTR_SET(val, member) \ val 119 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_MSIX_##member##_MASK) << \ val 122 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_MSIX_ATTR_GET(val, member) \ val 123 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((val) >> HINIC_MSIX_##member##_SHIFT) & \ val 130 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h #define HINIC_MSIX_CNT_SET(val, member) \ val 131 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \ val 242 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h u32 val) val 244 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg); val 46 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h #define HINIC_MSG_HEADER_SET(val, member) \ val 47 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h ((u64)((val) & HINIC_MSG_HEADER_##member##_MASK) << \ val 50 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h #define HINIC_MSG_HEADER_GET(val, member) \ val 51 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h (((val) >> HINIC_MSG_HEADER_##member##_SHIFT) & \ val 34 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h #define HINIC_SQ_DB_INFO_SET(val, member) \ val 35 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h (((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \ val 20 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_SQ_CTXT_CEQ_ATTR_SET(val, member) \ val 21 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_CEQ_ATTR_##member##_MASK) \ val 30 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_SQ_CTXT_CI_SET(val, member) \ val 31 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_CI_##member##_MASK) \ val 40 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_SQ_CTXT_WQ_PAGE_SET(val, member) \ val 41 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_WQ_PAGE_##member##_MASK) \ val 58 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_SQ_CTXT_PREF_SET(val, member) \ val 59 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_PREF_##member##_MASK) \ val 66 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_SQ_CTXT_WQ_BLOCK_SET(val, member) \ val 67 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_WQ_BLOCK_##member##_MASK) \ val 76 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_RQ_CTXT_CEQ_ATTR_SET(val, member) \ val 77 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_CEQ_ATTR_##member##_MASK) \ val 86 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_RQ_CTXT_PI_SET(val, member) \ val 87 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_PI_##member##_MASK) << \ val 96 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_RQ_CTXT_WQ_PAGE_SET(val, member) \ val 97 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_WQ_PAGE_##member##_MASK) << \ val 114 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_RQ_CTXT_PREF_SET(val, member) \ val 115 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_PREF_##member##_MASK) << \ val 122 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h #define HINIC_RQ_CTXT_WQ_BLOCK_SET(val, member) \ val 123 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_WQ_BLOCK_##member##_MASK) << \ val 24 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_CMDQ_CTRL_SET(val, member) \ val 25 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \ val 28 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_CMDQ_CTRL_GET(val, member) \ val 29 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((val) >> HINIC_CMDQ_CTRL_##member##_SHIFT) \ val 48 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_CMDQ_WQE_HEADER_SET(val, member) \ val 49 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \ val 52 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_CMDQ_WQE_HEADER_GET(val, member) \ val 53 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((val) >> HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) \ val 84 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_SQ_CTRL_SET(val, member) \ val 85 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \ val 88 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_SQ_CTRL_GET(val, member) \ val 89 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \ val 92 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_SQ_CTRL_CLEAR(val, member) \ val 93 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h ((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \ val 114 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_SQ_TASK_INFO0_SET(val, member) \ val 115 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \ val 128 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_SQ_TASK_INFO1_SET(val, member) \ val 129 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \ val 146 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_SQ_TASK_INFO2_SET(val, member) \ val 147 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \ val 156 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_SQ_TASK_INFO4_SET(val, member) \ val 157 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \ val 168 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_RQ_CQE_STATUS_GET(val, member) \ val 169 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \ val 172 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_RQ_CQE_STATUS_CLEAR(val, member) \ val 173 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h ((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \ val 180 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_RQ_CQE_SGE_GET(val, member) \ val 181 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((val) >> HINIC_RQ_CQE_SGE_##member##_SHIFT) & \ val 194 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_RQ_CTRL_SET(val, member) \ val 195 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \ val 216 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define RQ_CQE_STATUS_GET(val, member) (((val) >> \ val 228 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define RQ_CQE_OFFOLAD_TYPE_GET(val, member) (((val) >> \ val 241 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define RQ_CQE_SGE_GET(val, member) (((val) >> \ val 258 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_RSS_TYPE_SET(val, member) \ val 259 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT) val 261 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h #define HINIC_RSS_TYPE_GET(val, member) \ val 262 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1) val 84 drivers/net/ethernet/i825xx/ether1.c #define ether1_writew(dev, val, addr, type, offset, svflgs) ether1_outw_p (dev, val, addr + (int)(&((type *)0)->offset), svflgs) val 103 drivers/net/ethernet/i825xx/ether1.c ether1_outw_p (struct net_device *dev, unsigned short val, int addr, int svflgs) val 111 drivers/net/ethernet/i825xx/ether1.c writew(val, ETHER1_RAM + ((addr & 4095) << 1)); val 871 drivers/net/ethernet/ibm/emac/core.c u16 val) val 879 drivers/net/ethernet/ibm/emac/core.c DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val); val 910 drivers/net/ethernet/ibm/emac/core.c (val << EMAC_STACR_PHYD_SHIFT); val 943 drivers/net/ethernet/ibm/emac/core.c static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val) val 950 drivers/net/ethernet/ibm/emac/core.c (u8) id, (u8) reg, (u16) val); val 2453 drivers/net/ethernet/ibm/emac/core.c u32 *val, int fatal) val 2463 drivers/net/ethernet/ibm/emac/core.c *val = *prop; val 2494 drivers/net/ethernet/ibm/emac/core.c int regnum, u16 val) val 2496 drivers/net/ethernet/ibm/emac/core.c emac_mdio_write(bus->priv, addr, regnum, val); val 218 drivers/net/ethernet/ibm/emac/mal.h static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val) val 220 drivers/net/ethernet/ibm/emac/mal.h dcr_write(mal->dcr_host, reg, val); val 40 drivers/net/ethernet/ibm/emac/phy.c static inline void _phy_write(struct mii_phy *phy, int reg, int val) val 42 drivers/net/ethernet/ibm/emac/phy.c phy->mdio_write(phy->dev, phy->address, reg, val); val 50 drivers/net/ethernet/ibm/emac/phy.c static inline void gpcs_phy_write(struct mii_phy *phy, int reg, int val) val 52 drivers/net/ethernet/ibm/emac/phy.c phy->mdio_write(phy->dev, phy->gpcs_address, reg, val); val 57 drivers/net/ethernet/ibm/emac/phy.c int val; val 60 drivers/net/ethernet/ibm/emac/phy.c val = phy_read(phy, MII_BMCR); val 61 drivers/net/ethernet/ibm/emac/phy.c val &= ~(BMCR_ISOLATE | BMCR_ANENABLE); val 62 drivers/net/ethernet/ibm/emac/phy.c val |= BMCR_RESET; val 63 drivers/net/ethernet/ibm/emac/phy.c phy_write(phy, MII_BMCR, val); val 68 drivers/net/ethernet/ibm/emac/phy.c val = phy_read(phy, MII_BMCR); val 69 drivers/net/ethernet/ibm/emac/phy.c if (val >= 0 && (val & BMCR_RESET) == 0) val 73 drivers/net/ethernet/ibm/emac/phy.c if ((val & BMCR_ISOLATE) && limit > 0) val 74 drivers/net/ethernet/ibm/emac/phy.c phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); val 81 drivers/net/ethernet/ibm/emac/phy.c int val; val 84 drivers/net/ethernet/ibm/emac/phy.c val = gpcs_phy_read(phy, MII_BMCR); val 85 drivers/net/ethernet/ibm/emac/phy.c val &= ~(BMCR_ISOLATE | BMCR_ANENABLE); val 86 drivers/net/ethernet/ibm/emac/phy.c val |= BMCR_RESET; val 87 drivers/net/ethernet/ibm/emac/phy.c gpcs_phy_write(phy, MII_BMCR, val); val 92 drivers/net/ethernet/ibm/emac/phy.c val = gpcs_phy_read(phy, MII_BMCR); val 93 drivers/net/ethernet/ibm/emac/phy.c if (val >= 0 && (val & BMCR_RESET) == 0) val 97 drivers/net/ethernet/ibm/emac/phy.c if ((val & BMCR_ISOLATE) && limit > 0) val 98 drivers/net/ethernet/ibm/emac/phy.c gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); val 73 drivers/net/ethernet/ibm/emac/phy.h int val); val 2882 drivers/net/ethernet/ibm/ibmvnic.c u64 val = (0xff000000) | scrq->hw_irq; val 2884 drivers/net/ethernet/ibm/ibmvnic.c rc = plpar_hcall_norets(H_EOI, val); val 2890 drivers/net/ethernet/ibm/ibmvnic.c val, rc); val 381 drivers/net/ethernet/intel/e1000/e1000_hw.h #define E1000_WRITE_REG_IO(a, reg, val) \ val 382 drivers/net/ethernet/intel/e1000/e1000_hw.h e1000_write_reg_io((a), E1000_##reg, val) val 580 drivers/net/ethernet/intel/e1000e/e1000.h void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); val 582 drivers/net/ethernet/intel/e1000e/e1000.h #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) val 771 drivers/net/ethernet/intel/e1000e/ethtool.c u32 pat, val; val 778 drivers/net/ethernet/intel/e1000e/ethtool.c val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset); val 779 drivers/net/ethernet/intel/e1000e/ethtool.c if (val != (test[pat] & write & mask)) { val 781 drivers/net/ethernet/intel/e1000e/ethtool.c reg + (offset << 2), val, val 793 drivers/net/ethernet/intel/e1000e/ethtool.c u32 val; val 796 drivers/net/ethernet/intel/e1000e/ethtool.c val = __er32(&adapter->hw, reg); val 797 drivers/net/ethernet/intel/e1000e/ethtool.c if ((write & mask) != (val & mask)) { val 799 drivers/net/ethernet/intel/e1000e/ethtool.c reg, (val & mask), (write & mask)); val 151 drivers/net/ethernet/intel/e1000e/ich8lan.c static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) val 153 drivers/net/ethernet/intel/e1000e/ich8lan.c writew(val, hw->flash_address + reg); val 156 drivers/net/ethernet/intel/e1000e/ich8lan.c static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) val 158 drivers/net/ethernet/intel/e1000e/ich8lan.c writel(val, hw->flash_address + reg); val 163 drivers/net/ethernet/intel/e1000e/ich8lan.c #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) val 164 drivers/net/ethernet/intel/e1000e/ich8lan.c #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) val 132 drivers/net/ethernet/intel/e1000e/netdev.c void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) val 137 drivers/net/ethernet/intel/e1000e/netdev.c writel(val, hw->hw_addr + reg); val 18 drivers/net/ethernet/intel/fm10k/fm10k_common.h #define fm10k_write_reg(hw, reg, val) \ val 22 drivers/net/ethernet/intel/fm10k/fm10k_common.h writel((val), &hw_addr[(reg)]); \ val 26 drivers/net/ethernet/intel/fm10k/fm10k_common.h #define fm10k_write_sw_reg(hw, reg, val) \ val 30 drivers/net/ethernet/intel/fm10k/fm10k_common.h writel((val), &sw_addr[(reg)]); \ val 96 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h #define fm10k_tlv_attr_put_u8(msg, attr_id, val) \ val 97 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h fm10k_tlv_attr_put_value(msg, attr_id, val, 1) val 98 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h #define fm10k_tlv_attr_put_u16(msg, attr_id, val) \ val 99 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h fm10k_tlv_attr_put_value(msg, attr_id, val, 2) val 100 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h #define fm10k_tlv_attr_put_u32(msg, attr_id, val) \ val 101 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h fm10k_tlv_attr_put_value(msg, attr_id, val, 4) val 102 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h #define fm10k_tlv_attr_put_u64(msg, attr_id, val) \ val 103 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h fm10k_tlv_attr_put_value(msg, attr_id, val, 8) val 104 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h #define fm10k_tlv_attr_put_s8(msg, attr_id, val) \ val 105 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h fm10k_tlv_attr_put_value(msg, attr_id, val, 1) val 106 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h #define fm10k_tlv_attr_put_s16(msg, attr_id, val) \ val 107 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h fm10k_tlv_attr_put_value(msg, attr_id, val, 2) val 108 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h #define fm10k_tlv_attr_put_s32(msg, attr_id, val) \ val 109 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h fm10k_tlv_attr_put_value(msg, attr_id, val, 4) val 110 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h #define fm10k_tlv_attr_put_s64(msg, attr_id, val) \ val 111 drivers/net/ethernet/intel/fm10k/fm10k_tlv.h fm10k_tlv_attr_put_value(msg, attr_id, val, 8) val 964 drivers/net/ethernet/intel/i40e/i40e.h u64 val; val 966 drivers/net/ethernet/intel/i40e/i40e.h val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); val 967 drivers/net/ethernet/intel/i40e/i40e.h val <<= 32; val 968 drivers/net/ethernet/intel/i40e/i40e.h val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); val 970 drivers/net/ethernet/intel/i40e/i40e.h return val; val 983 drivers/net/ethernet/intel/i40e/i40e.h u16 addr, u64 val) val 986 drivers/net/ethernet/intel/i40e/i40e.h (u32)(val >> 32)); val 988 drivers/net/ethernet/intel/i40e/i40e.h (u32)(val & 0xFFFFFFFFULL)); val 1097 drivers/net/ethernet/intel/i40e/i40e.h u32 val; val 1099 drivers/net/ethernet/intel/i40e/i40e.h val = I40E_PFINT_DYN_CTLN_INTENA_MASK | val 1102 drivers/net/ethernet/intel/i40e/i40e.h wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); val 742 drivers/net/ethernet/intel/i40e/i40e_adminq.c u32 val = 0; val 755 drivers/net/ethernet/intel/i40e/i40e_adminq.c val = rd32(hw, hw->aq.asq.head); val 756 drivers/net/ethernet/intel/i40e/i40e_adminq.c if (val >= hw->aq.num_asq_entries) { val 758 drivers/net/ethernet/intel/i40e/i40e_adminq.c "AQTX: head overrun at %d\n", val); val 1329 drivers/net/ethernet/intel/i40e/i40e_common.c u32 val; val 1333 drivers/net/ethernet/intel/i40e/i40e_common.c val = rd32(hw, I40E_GLPCI_CNF2); val 1334 drivers/net/ethernet/intel/i40e/i40e_common.c num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> val 1336 drivers/net/ethernet/intel/i40e/i40e_common.c num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> val 1339 drivers/net/ethernet/intel/i40e/i40e_common.c val = rd32(hw, I40E_PFLAN_QALLOC); val 1340 drivers/net/ethernet/intel/i40e/i40e_common.c base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> val 1342 drivers/net/ethernet/intel/i40e/i40e_common.c j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> val 1344 drivers/net/ethernet/intel/i40e/i40e_common.c if (val & I40E_PFLAN_QALLOC_VALID_MASK) val 1349 drivers/net/ethernet/intel/i40e/i40e_common.c val = rd32(hw, I40E_PF_VT_PFALLOC); val 1350 drivers/net/ethernet/intel/i40e/i40e_common.c i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> val 1352 drivers/net/ethernet/intel/i40e/i40e_common.c j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> val 1354 drivers/net/ethernet/intel/i40e/i40e_common.c if (val & I40E_PF_VT_PFALLOC_VALID_MASK) val 1361 drivers/net/ethernet/intel/i40e/i40e_common.c val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; val 1363 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_PFINT_DYN_CTLN(i), val); val 1366 drivers/net/ethernet/intel/i40e/i40e_common.c val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; val 1367 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_PFINT_LNKLST0, val); val 1369 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_PFINT_LNKLSTN(i), val); val 1370 drivers/net/ethernet/intel/i40e/i40e_common.c val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; val 1372 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_VPINT_LNKLST0(i), val); val 1374 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_VPINT_LNKLSTN(i), val); val 1386 drivers/net/ethernet/intel/i40e/i40e_common.c val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); val 1387 drivers/net/ethernet/intel/i40e/i40e_common.c val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; val 1388 drivers/net/ethernet/intel/i40e/i40e_common.c val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); val 1389 drivers/net/ethernet/intel/i40e/i40e_common.c val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; val 1391 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); val 4179 drivers/net/ethernet/intel/i40e/i40e_common.c u32 val; val 4247 drivers/net/ethernet/intel/i40e/i40e_common.c val = rd32(hw, I40E_GLHMC_FCOEFMAX); val 4248 drivers/net/ethernet/intel/i40e/i40e_common.c fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) val 4270 drivers/net/ethernet/intel/i40e/i40e_common.c u32 val; val 4281 drivers/net/ethernet/intel/i40e/i40e_common.c val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); val 4284 drivers/net/ethernet/intel/i40e/i40e_common.c val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; val 4285 drivers/net/ethernet/intel/i40e/i40e_common.c val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & val 4288 drivers/net/ethernet/intel/i40e/i40e_common.c val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; val 4289 drivers/net/ethernet/intel/i40e/i40e_common.c val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & val 4293 drivers/net/ethernet/intel/i40e/i40e_common.c val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; val 4294 drivers/net/ethernet/intel/i40e/i40e_common.c val |= ((u32)settings->fcoe_filt_num << val 4298 drivers/net/ethernet/intel/i40e/i40e_common.c val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; val 4299 drivers/net/ethernet/intel/i40e/i40e_common.c val |= ((u32)settings->fcoe_cntx_num << val 4304 drivers/net/ethernet/intel/i40e/i40e_common.c val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; val 4307 drivers/net/ethernet/intel/i40e/i40e_common.c val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & val 4312 drivers/net/ethernet/intel/i40e/i40e_common.c val |= I40E_PFQF_CTL_0_FD_ENA_MASK; val 4314 drivers/net/ethernet/intel/i40e/i40e_common.c val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; val 4316 drivers/net/ethernet/intel/i40e/i40e_common.c val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; val 4318 drivers/net/ethernet/intel/i40e/i40e_common.c i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); val 5111 drivers/net/ethernet/intel/i40e/i40e_common.c u16 *val) val 5130 drivers/net/ethernet/intel/i40e/i40e_common.c *val = (u16)reg_val_aq; val 5146 drivers/net/ethernet/intel/i40e/i40e_common.c *val = reg_val; val 5248 drivers/net/ethernet/intel/i40e/i40e_common.c u32 val = 0; val 5255 drivers/net/ethernet/intel/i40e/i40e_common.c status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); val 5265 drivers/net/ethernet/intel/i40e/i40e_common.c val = rd32(hw, reg_addr); val 5267 drivers/net/ethernet/intel/i40e/i40e_common.c return val; val 17 drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c u32 val; val 19 drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c val = rd32(hw, I40E_PRTDCB_GENC); val 20 drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c *delay = (u16)((val & I40E_PRTDCB_GENC_PFCLDA_MASK) >> val 19 drivers/net/ethernet/intel/i40e/i40e_diag.c u32 pat, val, orig_val; val 26 drivers/net/ethernet/intel/i40e/i40e_diag.c val = rd32(hw, reg); val 27 drivers/net/ethernet/intel/i40e/i40e_diag.c if ((val & mask) != (pat & mask)) { val 30 drivers/net/ethernet/intel/i40e/i40e_diag.c __func__, reg, pat, val); val 36 drivers/net/ethernet/intel/i40e/i40e_diag.c val = rd32(hw, reg); val 37 drivers/net/ethernet/intel/i40e/i40e_diag.c if (val != orig_val) { val 40 drivers/net/ethernet/intel/i40e/i40e_diag.c __func__, reg, orig_val, val); val 1839 drivers/net/ethernet/intel/i40e/i40e_ethtool.c u32 val; val 1843 drivers/net/ethernet/intel/i40e/i40e_ethtool.c val = X722_EEPROM_SCOPE_LIMIT + 1; val 1844 drivers/net/ethernet/intel/i40e/i40e_ethtool.c return val; val 1846 drivers/net/ethernet/intel/i40e/i40e_ethtool.c val = (rd32(hw, I40E_GLPCI_LBARCTRL) val 1850 drivers/net/ethernet/intel/i40e/i40e_ethtool.c val = (64 * 1024) * BIT(val); val 1851 drivers/net/ethernet/intel/i40e/i40e_ethtool.c return val; val 311 drivers/net/ethernet/intel/i40e/i40e_main.c u32 head, val; val 359 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, val 363 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); val 368 drivers/net/ethernet/intel/i40e/i40e_main.c readl(tx_ring->tail), val); val 875 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 1067 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_PRTPM_EEE_STAT); val 1069 drivers/net/ethernet/intel/i40e/i40e_main.c (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> val 1072 drivers/net/ethernet/intel/i40e/i40e_main.c (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> val 3554 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 3556 drivers/net/ethernet/intel/i40e/i40e_main.c val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | val 3563 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_RQCTL(qp), val); val 3566 drivers/net/ethernet/intel/i40e/i40e_main.c val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | val 3573 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_TQCTL(nextqp), val); val 3576 drivers/net/ethernet/intel/i40e/i40e_main.c val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | val 3585 drivers/net/ethernet/intel/i40e/i40e_main.c val |= (I40E_QUEUE_END_OF_LIST << val 3588 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_TQCTL(qp), val); val 3603 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 3609 drivers/net/ethernet/intel/i40e/i40e_main.c val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | val 3619 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; val 3622 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; val 3624 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_PFINT_ICR0_ENA, val); val 3644 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 3662 drivers/net/ethernet/intel/i40e/i40e_main.c val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | val 3667 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_RQCTL(0), val); val 3670 drivers/net/ethernet/intel/i40e/i40e_main.c val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | val 3675 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_TQCTL(nextqp), val); val 3678 drivers/net/ethernet/intel/i40e/i40e_main.c val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | val 3682 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_TQCTL(0), val); val 3706 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 3708 drivers/net/ethernet/intel/i40e/i40e_main.c val = I40E_PFINT_DYN_CTL0_INTENA_MASK | val 3712 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_PFINT_DYN_CTL0, val); val 3849 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 3851 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx)); val 3852 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK; val 3853 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val); val 3855 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx)); val 3856 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK; val 3857 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), val); val 3934 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val, ena_mask; val 3990 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_GLGEN_RSTAT); val 3991 drivers/net/ethernet/intel/i40e/i40e_main.c val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) val 3993 drivers/net/ethernet/intel/i40e/i40e_main.c if (val == I40E_RESET_CORER) { val 3995 drivers/net/ethernet/intel/i40e/i40e_main.c } else if (val == I40E_RESET_GLOBR) { val 3997 drivers/net/ethernet/intel/i40e/i40e_main.c } else if (val == I40E_RESET_EMPR) { val 4604 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val, qp; val 4641 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); val 4642 drivers/net/ethernet/intel/i40e/i40e_main.c qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) val 4644 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_QUEUE_END_OF_LIST val 4646 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); val 4651 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_QINT_RQCTL(qp)); val 4653 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | val 4658 drivers/net/ethernet/intel/i40e/i40e_main.c val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | val 4661 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_RQCTL(qp), val); val 4663 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_QINT_TQCTL(qp)); val 4665 drivers/net/ethernet/intel/i40e/i40e_main.c next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) val 4668 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | val 4673 drivers/net/ethernet/intel/i40e/i40e_main.c val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | val 4676 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_TQCTL(qp), val); val 4683 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_PFINT_LNKLST0); val 4684 drivers/net/ethernet/intel/i40e/i40e_main.c qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) val 4686 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_QUEUE_END_OF_LIST val 4688 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_PFINT_LNKLST0, val); val 4690 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_QINT_RQCTL(qp)); val 4691 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | val 4696 drivers/net/ethernet/intel/i40e/i40e_main.c val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | val 4699 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_RQCTL(qp), val); val 4701 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_QINT_TQCTL(qp)); val 4703 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | val 4708 drivers/net/ethernet/intel/i40e/i40e_main.c val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | val 4711 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_QINT_TQCTL(qp), val); val 8419 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 8436 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, I40E_GLGEN_RTRIG); val 8437 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_GLGEN_RTRIG_GLOBR_MASK; val 8438 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(&pf->hw, I40E_GLGEN_RTRIG, val); val 8447 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, I40E_GLGEN_RTRIG); val 8448 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_GLGEN_RTRIG_CORER_MASK; val 8449 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(&pf->hw, I40E_GLGEN_RTRIG, val); val 8722 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val, fcnt_prog; val 8724 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, I40E_PFQF_FDSTAT); val 8725 drivers/net/ethernet/intel/i40e/i40e_main.c fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK); val 8735 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val, fcnt_prog; val 8737 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, I40E_PFQF_FDSTAT); val 8738 drivers/net/ethernet/intel/i40e/i40e_main.c fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + val 8739 drivers/net/ethernet/intel/i40e/i40e_main.c ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> val 8750 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val, fcnt_prog; val 8752 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); val 8753 drivers/net/ethernet/intel/i40e/i40e_main.c fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + val 8754 drivers/net/ethernet/intel/i40e/i40e_main.c ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> val 9225 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 9232 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, pf->hw.aq.arq.len); val 9233 drivers/net/ethernet/intel/i40e/i40e_main.c oldval = val; val 9234 drivers/net/ethernet/intel/i40e/i40e_main.c if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { val 9237 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_PF_ARQLEN_ARQVFE_MASK; val 9239 drivers/net/ethernet/intel/i40e/i40e_main.c if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) { val 9242 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK; val 9245 drivers/net/ethernet/intel/i40e/i40e_main.c if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) { val 9248 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK; val 9250 drivers/net/ethernet/intel/i40e/i40e_main.c if (oldval != val) val 9251 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(&pf->hw, pf->hw.aq.arq.len, val); val 9253 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(&pf->hw, pf->hw.aq.asq.len); val 9254 drivers/net/ethernet/intel/i40e/i40e_main.c oldval = val; val 9255 drivers/net/ethernet/intel/i40e/i40e_main.c if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { val 9258 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_PF_ATQLEN_ATQVFE_MASK; val 9260 drivers/net/ethernet/intel/i40e/i40e_main.c if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) { val 9263 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK; val 9265 drivers/net/ethernet/intel/i40e/i40e_main.c if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) { val 9268 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK; val 9270 drivers/net/ethernet/intel/i40e/i40e_main.c if (oldval != val) val 9271 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(&pf->hw, pf->hw.aq.asq.len, val); val 9335 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_PFINT_ICR0_ENA); val 9336 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; val 9337 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_PFINT_ICR0_ENA, val); val 9933 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 10153 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_REG_MSS); val 10154 drivers/net/ethernet/intel/i40e/i40e_main.c if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { val 10155 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_REG_MSS_MIN_MASK; val 10156 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_64BYTE_MSS; val 10157 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_REG_MSS, val); val 14558 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val = rd32(&pf->hw, I40E_GL_FWSTS) & I40E_GL_FWSTS_FWS1B_MASK; val 14563 drivers/net/ethernet/intel/i40e/i40e_main.c val == I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK || val 14564 drivers/net/ethernet/intel/i40e/i40e_main.c val == I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK || val 14565 drivers/net/ethernet/intel/i40e/i40e_main.c val == I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK || val 14566 drivers/net/ethernet/intel/i40e/i40e_main.c val == I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK; val 14569 drivers/net/ethernet/intel/i40e/i40e_main.c val == I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK || val 14570 drivers/net/ethernet/intel/i40e/i40e_main.c val == I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK; val 14742 drivers/net/ethernet/intel/i40e/i40e_main.c u32 val; val 15108 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_REG_MSS); val 15109 drivers/net/ethernet/intel/i40e/i40e_main.c if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { val 15110 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_REG_MSS_MIN_MASK; val 15111 drivers/net/ethernet/intel/i40e/i40e_main.c val |= I40E_64BYTE_MSS; val 15112 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_REG_MSS, val); val 15150 drivers/net/ethernet/intel/i40e/i40e_main.c val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM); val 15151 drivers/net/ethernet/intel/i40e/i40e_main.c val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK; val 15152 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val); val 762 drivers/net/ethernet/intel/i40e/i40e_nvm.c static inline u8 i40e_nvmupd_get_module(u32 val) val 764 drivers/net/ethernet/intel/i40e/i40e_nvm.c return (u8)(val & I40E_NVM_MOD_PNT_MASK); val 766 drivers/net/ethernet/intel/i40e/i40e_nvm.c static inline u8 i40e_nvmupd_get_transaction(u32 val) val 768 drivers/net/ethernet/intel/i40e/i40e_nvm.c return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); val 771 drivers/net/ethernet/intel/i40e/i40e_nvm.c static inline u8 i40e_nvmupd_get_preservation_flags(u32 val) val 773 drivers/net/ethernet/intel/i40e/i40e_nvm.c return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >> val 57 drivers/net/ethernet/intel/i40e/i40e_prototype.h u16 *val); val 909 drivers/net/ethernet/intel/i40e/i40e_txrx.c u32 val; val 918 drivers/net/ethernet/intel/i40e/i40e_txrx.c val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | val 923 drivers/net/ethernet/intel/i40e/i40e_txrx.c val); val 925 drivers/net/ethernet/intel/i40e/i40e_txrx.c val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | val 928 drivers/net/ethernet/intel/i40e/i40e_txrx.c wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); val 942 drivers/net/ethernet/intel/i40e/i40e_txrx.c u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | val 949 drivers/net/ethernet/intel/i40e/i40e_txrx.c I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val); val 951 drivers/net/ethernet/intel/i40e/i40e_txrx.c u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | val 957 drivers/net/ethernet/intel/i40e/i40e_txrx.c wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); val 1483 drivers/net/ethernet/intel/i40e/i40e_txrx.c void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) val 1485 drivers/net/ethernet/intel/i40e/i40e_txrx.c rx_ring->next_to_use = val; val 1488 drivers/net/ethernet/intel/i40e/i40e_txrx.c rx_ring->next_to_alloc = val; val 1496 drivers/net/ethernet/intel/i40e/i40e_txrx.c writel(val, rx_ring->tail); val 2458 drivers/net/ethernet/intel/i40e/i40e_txrx.c u32 val; val 2477 drivers/net/ethernet/intel/i40e/i40e_txrx.c val = I40E_PFINT_DYN_CTLN_INTENA_MASK | val 2481 drivers/net/ethernet/intel/i40e/i40e_txrx.c return val; val 21 drivers/net/ethernet/intel/i40e/i40e_txrx_common.h void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val); val 644 drivers/net/ethernet/intel/iavf/iavf_adminq.c u32 val = 0; val 657 drivers/net/ethernet/intel/iavf/iavf_adminq.c val = rd32(hw, hw->aq.asq.head); val 658 drivers/net/ethernet/intel/iavf/iavf_adminq.c if (val >= hw->aq.num_asq_entries) { val 660 drivers/net/ethernet/intel/iavf/iavf_adminq.c "AQTX: head overrun at %d\n", val); val 2275 drivers/net/ethernet/intel/iavf/iavf_main.c u32 val, oldval; val 2306 drivers/net/ethernet/intel/iavf/iavf_main.c val = rd32(hw, hw->aq.arq.len); val 2307 drivers/net/ethernet/intel/iavf/iavf_main.c if (val == 0xdeadbeef) /* indicates device in reset */ val 2309 drivers/net/ethernet/intel/iavf/iavf_main.c oldval = val; val 2310 drivers/net/ethernet/intel/iavf/iavf_main.c if (val & IAVF_VF_ARQLEN1_ARQVFE_MASK) { val 2312 drivers/net/ethernet/intel/iavf/iavf_main.c val &= ~IAVF_VF_ARQLEN1_ARQVFE_MASK; val 2314 drivers/net/ethernet/intel/iavf/iavf_main.c if (val & IAVF_VF_ARQLEN1_ARQOVFL_MASK) { val 2316 drivers/net/ethernet/intel/iavf/iavf_main.c val &= ~IAVF_VF_ARQLEN1_ARQOVFL_MASK; val 2318 drivers/net/ethernet/intel/iavf/iavf_main.c if (val & IAVF_VF_ARQLEN1_ARQCRIT_MASK) { val 2320 drivers/net/ethernet/intel/iavf/iavf_main.c val &= ~IAVF_VF_ARQLEN1_ARQCRIT_MASK; val 2322 drivers/net/ethernet/intel/iavf/iavf_main.c if (oldval != val) val 2323 drivers/net/ethernet/intel/iavf/iavf_main.c wr32(hw, hw->aq.arq.len, val); val 2325 drivers/net/ethernet/intel/iavf/iavf_main.c val = rd32(hw, hw->aq.asq.len); val 2326 drivers/net/ethernet/intel/iavf/iavf_main.c oldval = val; val 2327 drivers/net/ethernet/intel/iavf/iavf_main.c if (val & IAVF_VF_ATQLEN1_ATQVFE_MASK) { val 2329 drivers/net/ethernet/intel/iavf/iavf_main.c val &= ~IAVF_VF_ATQLEN1_ATQVFE_MASK; val 2331 drivers/net/ethernet/intel/iavf/iavf_main.c if (val & IAVF_VF_ATQLEN1_ATQOVFL_MASK) { val 2333 drivers/net/ethernet/intel/iavf/iavf_main.c val &= ~IAVF_VF_ATQLEN1_ATQOVFL_MASK; val 2335 drivers/net/ethernet/intel/iavf/iavf_main.c if (val & IAVF_VF_ATQLEN1_ATQCRIT_MASK) { val 2337 drivers/net/ethernet/intel/iavf/iavf_main.c val &= ~IAVF_VF_ATQLEN1_ATQCRIT_MASK; val 2339 drivers/net/ethernet/intel/iavf/iavf_main.c if (oldval != val) val 2340 drivers/net/ethernet/intel/iavf/iavf_main.c wr32(hw, hw->aq.asq.len, val); val 336 drivers/net/ethernet/intel/iavf/iavf_txrx.c u32 val; val 344 drivers/net/ethernet/intel/iavf/iavf_txrx.c val = IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK | val 348 drivers/net/ethernet/intel/iavf/iavf_txrx.c IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx), val); val 360 drivers/net/ethernet/intel/iavf/iavf_txrx.c u32 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK | val 368 drivers/net/ethernet/intel/iavf/iavf_txrx.c val); val 775 drivers/net/ethernet/intel/iavf/iavf_txrx.c static inline void iavf_release_rx_desc(struct iavf_ring *rx_ring, u32 val) val 777 drivers/net/ethernet/intel/iavf/iavf_txrx.c rx_ring->next_to_use = val; val 780 drivers/net/ethernet/intel/iavf/iavf_txrx.c rx_ring->next_to_alloc = val; val 788 drivers/net/ethernet/intel/iavf/iavf_txrx.c writel(val, rx_ring->tail); val 1599 drivers/net/ethernet/intel/iavf/iavf_txrx.c u32 val; val 1618 drivers/net/ethernet/intel/iavf/iavf_txrx.c val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK | val 1622 drivers/net/ethernet/intel/iavf/iavf_txrx.c return val; val 84 drivers/net/ethernet/intel/ice/ice.h #define ICE_UP_TABLE_TRANSLATE(val, i) \ val 85 drivers/net/ethernet/intel/ice/ice.h (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \ val 396 drivers/net/ethernet/intel/ice/ice.h u32 val; val 401 drivers/net/ethernet/intel/ice/ice.h val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | val 406 drivers/net/ethernet/intel/ice/ice.h wr32(hw, GLINT_DYN_CTL(vector), val); val 608 drivers/net/ethernet/intel/ice/ice_common.c u16 val; val 624 drivers/net/ethernet/intel/ice/ice_common.c val = i << ICE_AQC_FW_LOG_ID_S; val 625 drivers/net/ethernet/intel/ice/ice_common.c val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; val 626 drivers/net/ethernet/intel/ice/ice_common.c data->entry[chgs++] = cpu_to_le16(val); val 1051 drivers/net/ethernet/intel/ice/ice_common.c u32 val = 0; val 1058 drivers/net/ethernet/intel/ice/ice_common.c val = GLGEN_RTRIG_CORER_M; val 1062 drivers/net/ethernet/intel/ice/ice_common.c val = GLGEN_RTRIG_GLOBR_M; val 1068 drivers/net/ethernet/intel/ice/ice_common.c val |= rd32(hw, GLGEN_RTRIG); val 1069 drivers/net/ethernet/intel/ice/ice_common.c wr32(hw, GLGEN_RTRIG, val); val 852 drivers/net/ethernet/intel/ice/ice_controlq.c u32 val = 0; val 887 drivers/net/ethernet/intel/ice/ice_controlq.c val = rd32(hw, cq->sq.head); val 888 drivers/net/ethernet/intel/ice/ice_controlq.c if (val >= cq->num_sq_entries) { val 891 drivers/net/ethernet/intel/ice/ice_controlq.c val); val 349 drivers/net/ethernet/intel/ice/ice_ethtool.c u32 val, orig_val; val 357 drivers/net/ethernet/intel/ice/ice_ethtool.c val = rd32(hw, reg); val 358 drivers/net/ethernet/intel/ice/ice_ethtool.c if (val == pattern) val 362 drivers/net/ethernet/intel/ice/ice_ethtool.c , __func__, reg, pattern, val); val 367 drivers/net/ethernet/intel/ice/ice_ethtool.c val = rd32(hw, reg); val 368 drivers/net/ethernet/intel/ice/ice_ethtool.c if (val != orig_val) { val 371 drivers/net/ethernet/intel/ice/ice_ethtool.c , __func__, reg, orig_val, val); val 1835 drivers/net/ethernet/intel/ice/ice_lib.c u32 val = intrl / gran; val 1837 drivers/net/ethernet/intel/ice/ice_lib.c if (val) val 1838 drivers/net/ethernet/intel/ice/ice_lib.c return val | GLINT_RATE_INTRL_ENA_M; val 1935 drivers/net/ethernet/intel/ice/ice_lib.c u32 val; val 1939 drivers/net/ethernet/intel/ice/ice_lib.c val = QINT_TQCTL_CAUSE_ENA_M | itr_idx | val 1942 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); val 1965 drivers/net/ethernet/intel/ice/ice_lib.c u32 val; val 1969 drivers/net/ethernet/intel/ice/ice_lib.c val = QINT_RQCTL_CAUSE_ENA_M | itr_idx | val 1972 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); val 2169 drivers/net/ethernet/intel/ice/ice_lib.c u32 val; val 2172 drivers/net/ethernet/intel/ice/ice_lib.c val = rd32(hw, QINT_TQCTL(ring->reg_idx)); val 2173 drivers/net/ethernet/intel/ice/ice_lib.c val &= ~QINT_TQCTL_CAUSE_ENA_M; val 2174 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, QINT_TQCTL(ring->reg_idx), val); val 2890 drivers/net/ethernet/intel/ice/ice_lib.c u32 val; val 2900 drivers/net/ethernet/intel/ice/ice_lib.c val = rd32(hw, QINT_TQCTL(reg)); val 2901 drivers/net/ethernet/intel/ice/ice_lib.c val &= ~QINT_TQCTL_CAUSE_ENA_M; val 2902 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, QINT_TQCTL(reg), val); val 2913 drivers/net/ethernet/intel/ice/ice_lib.c val = rd32(hw, QINT_RQCTL(reg)); val 2914 drivers/net/ethernet/intel/ice/ice_lib.c val &= ~QINT_RQCTL_CAUSE_ENA_M; val 2915 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, QINT_RQCTL(reg), val); val 968 drivers/net/ethernet/intel/ice/ice_main.c u32 oldval, val; val 992 drivers/net/ethernet/intel/ice/ice_main.c val = rd32(hw, cq->rq.len); val 993 drivers/net/ethernet/intel/ice/ice_main.c if (val & (PF_FW_ARQLEN_ARQVFE_M | PF_FW_ARQLEN_ARQOVFL_M | val 995 drivers/net/ethernet/intel/ice/ice_main.c oldval = val; val 996 drivers/net/ethernet/intel/ice/ice_main.c if (val & PF_FW_ARQLEN_ARQVFE_M) val 999 drivers/net/ethernet/intel/ice/ice_main.c if (val & PF_FW_ARQLEN_ARQOVFL_M) { val 1004 drivers/net/ethernet/intel/ice/ice_main.c if (val & PF_FW_ARQLEN_ARQCRIT_M) val 1008 drivers/net/ethernet/intel/ice/ice_main.c val &= ~(PF_FW_ARQLEN_ARQVFE_M | PF_FW_ARQLEN_ARQOVFL_M | val 1010 drivers/net/ethernet/intel/ice/ice_main.c if (oldval != val) val 1011 drivers/net/ethernet/intel/ice/ice_main.c wr32(hw, cq->rq.len, val); val 1014 drivers/net/ethernet/intel/ice/ice_main.c val = rd32(hw, cq->sq.len); val 1015 drivers/net/ethernet/intel/ice/ice_main.c if (val & (PF_FW_ATQLEN_ATQVFE_M | PF_FW_ATQLEN_ATQOVFL_M | val 1017 drivers/net/ethernet/intel/ice/ice_main.c oldval = val; val 1018 drivers/net/ethernet/intel/ice/ice_main.c if (val & PF_FW_ATQLEN_ATQVFE_M) val 1021 drivers/net/ethernet/intel/ice/ice_main.c if (val & PF_FW_ATQLEN_ATQOVFL_M) { val 1026 drivers/net/ethernet/intel/ice/ice_main.c if (val & PF_FW_ATQLEN_ATQCRIT_M) val 1030 drivers/net/ethernet/intel/ice/ice_main.c val &= ~(PF_FW_ATQLEN_ATQVFE_M | PF_FW_ATQLEN_ATQOVFL_M | val 1032 drivers/net/ethernet/intel/ice/ice_main.c if (oldval != val) val 1033 drivers/net/ethernet/intel/ice/ice_main.c wr32(hw, cq->sq.len, val); val 1670 drivers/net/ethernet/intel/ice/ice_main.c u32 val; val 1676 drivers/net/ethernet/intel/ice/ice_main.c val = (PFINT_OICR_ECC_ERR_M | val 1684 drivers/net/ethernet/intel/ice/ice_main.c wr32(hw, PFINT_OICR_ENA, val); val 1856 drivers/net/ethernet/intel/ice/ice_main.c u32 val; val 1858 drivers/net/ethernet/intel/ice/ice_main.c val = ((reg_idx & PFINT_OICR_CTL_MSIX_INDX_M) | val 1860 drivers/net/ethernet/intel/ice/ice_main.c wr32(hw, PFINT_OICR_CTL, val); val 1863 drivers/net/ethernet/intel/ice/ice_main.c val = ((reg_idx & PFINT_FW_CTL_MSIX_INDX_M) | val 1865 drivers/net/ethernet/intel/ice/ice_main.c wr32(hw, PFINT_FW_CTL, val); val 1868 drivers/net/ethernet/intel/ice/ice_main.c val = ((reg_idx & PFINT_MBX_CTL_MSIX_INDX_M) | val 1870 drivers/net/ethernet/intel/ice/ice_main.c wr32(hw, PFINT_MBX_CTL, val); val 4688 drivers/net/ethernet/intel/ice/ice_main.c u32 head, val = 0; val 4693 drivers/net/ethernet/intel/ice/ice_main.c val = rd32(hw, GLINT_DYN_CTL(tx_ring->q_vector->reg_idx)); val 4697 drivers/net/ethernet/intel/ice/ice_main.c head, tx_ring->next_to_use, val); val 379 drivers/net/ethernet/intel/ice/ice_txrx.c static void ice_release_rx_desc(struct ice_ring *rx_ring, u32 val) val 383 drivers/net/ethernet/intel/ice/ice_txrx.c rx_ring->next_to_use = val; val 386 drivers/net/ethernet/intel/ice/ice_txrx.c rx_ring->next_to_alloc = val; val 393 drivers/net/ethernet/intel/ice/ice_txrx.c val &= ~0x7; val 394 drivers/net/ethernet/intel/ice/ice_txrx.c if (prev_ntu != val) { val 401 drivers/net/ethernet/intel/ice/ice_txrx.c writel(val, rx_ring->tail); val 356 drivers/net/ethernet/intel/igb/e1000_regs.h #define wr32(reg, val) \ val 360 drivers/net/ethernet/intel/igb/e1000_regs.h writel((val), &hw_addr[(reg)]); \ val 1207 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 pat, val; val 1212 drivers/net/ethernet/intel/igb/igb_ethtool.c val = rd32(reg) & mask; val 1213 drivers/net/ethernet/intel/igb/igb_ethtool.c if (val != (_test[pat] & write & mask)) { val 1216 drivers/net/ethernet/intel/igb/igb_ethtool.c reg, val, (_test[pat] & write & mask)); val 1229 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 val; val 1232 drivers/net/ethernet/intel/igb/igb_ethtool.c val = rd32(reg); val 1233 drivers/net/ethernet/intel/igb/igb_ethtool.c if ((write & mask) != (val & mask)) { val 1236 drivers/net/ethernet/intel/igb/igb_ethtool.c reg, (val & mask), (write & mask)); val 3330 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 val = 0; val 3334 drivers/net/ethernet/intel/igb/igb_ethtool.c val <<= 8; val 3335 drivers/net/ethernet/intel/igb/igb_ethtool.c val |= adapter->rss_indir_tbl[i + j]; val 3338 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(reg, val << shift); val 1622 drivers/net/ethernet/intel/igb/igb_main.c u32 val; val 1627 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(E1000_I210_TXDCTL(queue)); val 1630 drivers/net/ethernet/intel/igb/igb_main.c val |= E1000_TXDCTL_PRIORITY; val 1632 drivers/net/ethernet/intel/igb/igb_main.c val &= ~E1000_TXDCTL_PRIORITY; val 1634 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_I210_TXDCTL(queue), val); val 1639 drivers/net/ethernet/intel/igb/igb_main.c u32 val; val 1644 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(E1000_I210_TQAVCC(queue)); val 1647 drivers/net/ethernet/intel/igb/igb_main.c val |= E1000_TQAVCC_QUEUEMODE; val 1649 drivers/net/ethernet/intel/igb/igb_main.c val &= ~E1000_TQAVCC_QUEUEMODE; val 1651 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_I210_TQAVCC(queue), val); val 1910 drivers/net/ethernet/intel/igb/igb_main.c u32 val; val 1923 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(E1000_I210_TQAVCTRL); val 1924 drivers/net/ethernet/intel/igb/igb_main.c val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; val 1925 drivers/net/ethernet/intel/igb/igb_main.c val &= ~E1000_TQAVCTRL_DATAFETCHARB; val 1926 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_I210_TQAVCTRL, val); val 1931 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(E1000_TXPBS); val 1932 drivers/net/ethernet/intel/igb/igb_main.c val &= ~I210_TXPBSIZE_MASK; val 1933 drivers/net/ethernet/intel/igb/igb_main.c val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | val 1935 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_TXPBS, val); val 1937 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(E1000_RXPBS); val 1938 drivers/net/ethernet/intel/igb/igb_main.c val &= ~I210_RXPBSIZE_MASK; val 1939 drivers/net/ethernet/intel/igb/igb_main.c val |= I210_RXPBSIZE_PB_30KB; val 1940 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_RXPBS, val); val 1953 drivers/net/ethernet/intel/igb/igb_main.c val = (4096 - 1) / 64; val 1954 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_I210_DTXMXPKTSZ, val); val 1972 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(E1000_I210_TQAVCTRL); val 1977 drivers/net/ethernet/intel/igb/igb_main.c val &= ~E1000_TQAVCTRL_XMIT_MODE; val 1978 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_I210_TQAVCTRL, val); val 4418 drivers/net/ethernet/intel/igb/igb_main.c u32 val, reg; val 4428 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(reg); val 4430 drivers/net/ethernet/intel/igb/igb_main.c val |= E1000_VMOLR_STRVLAN; val 4432 drivers/net/ethernet/intel/igb/igb_main.c val &= ~(E1000_VMOLR_STRVLAN); val 4433 drivers/net/ethernet/intel/igb/igb_main.c wr32(reg, val); val 8834 drivers/net/ethernet/intel/igb/igb_main.c u32 err, val; val 8865 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(E1000_WUS); val 8866 drivers/net/ethernet/intel/igb/igb_main.c if (val & WAKE_PKT_WUS) val 78 drivers/net/ethernet/intel/igb/igb_ptp.c u64 val; val 84 drivers/net/ethernet/intel/igb/igb_ptp.c val = ((u64) hi) << 32; val 85 drivers/net/ethernet/intel/igb/igb_ptp.c val |= lo; val 87 drivers/net/ethernet/intel/igb/igb_ptp.c return val; val 96 drivers/net/ethernet/intel/igb/igb_ptp.c u64 val; val 106 drivers/net/ethernet/intel/igb/igb_ptp.c val = ((u64) hi) << 32; val 107 drivers/net/ethernet/intel/igb/igb_ptp.c val |= lo; val 109 drivers/net/ethernet/intel/igb/igb_ptp.c return val; val 77 drivers/net/ethernet/intel/igbvf/regs.h #define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg) val 80 drivers/net/ethernet/intel/igbvf/regs.h #define array_ew32(reg, offset, val) \ val 81 drivers/net/ethernet/intel/igbvf/regs.h writel((val), hw->hw_addr + E1000_##reg + (offset << 2)) val 1484 drivers/net/ethernet/intel/igc/igc_ethtool.c u32 val = 0; val 1488 drivers/net/ethernet/intel/igc/igc_ethtool.c val <<= 8; val 1489 drivers/net/ethernet/intel/igc/igc_ethtool.c val |= adapter->rss_indir_tbl[i + j]; val 1492 drivers/net/ethernet/intel/igc/igc_ethtool.c wr32(reg, val << shift); val 223 drivers/net/ethernet/intel/igc/igc_regs.h #define wr32(reg, val) \ val 227 drivers/net/ethernet/intel/igc/igc_regs.h writel((val), &hw_addr[(reg)]); \ val 167 drivers/net/ethernet/intel/ixgb/ixgb_main.c u32 val = IXGB_INT_RXT0 | IXGB_INT_RXDMT0 | val 170 drivers/net/ethernet/intel/ixgb/ixgb_main.c val |= IXGB_INT_GPI0; val 171 drivers/net/ethernet/intel/ixgb/ixgb_main.c IXGB_WRITE_REG(&adapter->hw, IMS, val); val 908 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) val 917 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c *val = (u8)atlas_ctl; val 930 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) val 934 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c atlas_ctl = (reg << 8) | val; val 1737 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) val 1746 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c *val = (u8)core_ctl; val 1759 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) val 1763 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c core_ctl = (reg << 8) | val; val 156 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h static inline void writeq(u64 val, void __iomem *addr) val 158 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h writel((u32)val, addr); val 159 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h writel((u32)(val >> 32), addr + 4); val 40 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL); val 42 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c if (val < min_credit) val 43 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c val = min_credit; val 44 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c refill[i] = val; val 1418 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u32 pat, val, before; val 1429 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c val = ixgbe_read_reg(&adapter->hw, reg); val 1430 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c if (val != (test_pattern[pat] & write & mask)) { val 1432 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c reg, val, (test_pattern[pat] & write & mask)); val 1445 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u32 val, before; val 1453 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c val = ixgbe_read_reg(&adapter->hw, reg); val 1454 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c if ((write & mask) != (val & mask)) { val 1456 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c reg, (val & mask), (write & mask)); val 9359 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c __be32 val, m; val 9364 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c val = cls->knode.sel->keys[i].val; val 9367 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c for (j = 0; field_ptr[j].val; j++) { val 9369 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c field_ptr[j].val(input, mask, (__force u32)val, val 9379 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c nexthdr->val == val 9380 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c (__force u32)cls->knode.sel->keys[i].val && val 12 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h int (*val)(struct ixgbe_fdir_filter *input, val 14 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h u32 val, u32 m); val 30 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h u32 val, u32 m) val 32 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h input->filter.formatted.src_ip[0] = (__force __be32)val; val 39 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h u32 val, u32 m) val 41 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h input->filter.formatted.dst_ip[0] = (__force __be32)val; val 47 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h { .off = 12, .val = ixgbe_mat_prgm_sip, val 49 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h { .off = 16, .val = ixgbe_mat_prgm_dip, val 51 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h { .val = NULL } /* terminal node */ val 56 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h u32 val, u32 m) val 58 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h input->filter.formatted.src_port = (__force __be16)(val & 0xffff); val 60 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h input->filter.formatted.dst_port = (__force __be16)(val >> 16); val 67 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h {.off = 0, .val = ixgbe_mat_prgm_ports, val 69 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h { .val = NULL } /* terminal node */ val 73 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h {.off = 0, .val = ixgbe_mat_prgm_ports, val 75 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h { .val = NULL } /* terminal node */ val 85 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h u32 val; val 93 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h .off = 8, .val = 0x600, .mask = 0xff00, .jump = ixgbe_tcp_fields}, val 95 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h .off = 8, .val = 0x1100, .mask = 0xff00, .jump = ixgbe_udp_fields}, val 89 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c u16 reg, u16 *val, bool lock) val 139 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c *val = (high_bits << 8) | low_bits; val 167 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c u16 reg, u16 val, bool lock) val 177 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c csum = ixgbe_ones_comp_byte_add(csum, val >> 8); val 178 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); val 194 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) val 197 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) val 737 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c int regnum, u16 val, u32 gssr) val 745 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val); val 795 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c u16 val) val 801 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr); val 829 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c int regnum, u16 val) val 836 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr); val 174 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h u16 *val, bool lock); val 176 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h u16 val, bool lock); val 3519 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val); val 3521 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h u16 *val); val 3522 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val); val 3524 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h u16 val); val 372 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u16 reg, u16 *val) val 374 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); val 388 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u16 reg, u16 *val) val 390 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); val 403 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u8 addr, u16 reg, u16 val) val 405 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); val 419 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u8 addr, u16 reg, u16 val) val 421 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); val 611 drivers/net/ethernet/intel/ixgbevf/ethtool.c u32 pat, val, before; val 621 drivers/net/ethernet/intel/ixgbevf/ethtool.c val = ixgbevf_read_reg(&adapter->hw, reg); val 622 drivers/net/ethernet/intel/ixgbevf/ethtool.c if (val != (register_test_patterns[pat] & write & mask)) { val 625 drivers/net/ethernet/intel/ixgbevf/ethtool.c reg, val, val 639 drivers/net/ethernet/intel/ixgbevf/ethtool.c u32 val, before; val 647 drivers/net/ethernet/intel/ixgbevf/ethtool.c val = ixgbevf_read_reg(&adapter->hw, reg); val 648 drivers/net/ethernet/intel/ixgbevf/ethtool.c if ((write & mask) != (val & mask)) { val 650 drivers/net/ethernet/intel/ixgbevf/ethtool.c reg, (val & mask), write & mask); val 50 drivers/net/ethernet/jme.c int i, val, again = (reg == MII_BMSR) ? 1 : 0; val 60 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMI); val 61 drivers/net/ethernet/jme.c if ((val & SMI_OP_REQ) == 0) val 73 drivers/net/ethernet/jme.c return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT; val 78 drivers/net/ethernet/jme.c int phy, int reg, int val) val 84 drivers/net/ethernet/jme.c ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | val 101 drivers/net/ethernet/jme.c u32 val; val 114 drivers/net/ethernet/jme.c val = jme_mdio_read(jme->dev, val 120 drivers/net/ethernet/jme.c MII_BMCR, val | BMCR_RESET); val 273 drivers/net/ethernet/jme.c u32 val; val 276 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBCSR); val 278 drivers/net/ethernet/jme.c if (val & SMBCSR_EEPROMD) { val 279 drivers/net/ethernet/jme.c val |= SMBCSR_CNACK; val 280 drivers/net/ethernet/jme.c jwrite32(jme, JME_SMBCSR, val); val 281 drivers/net/ethernet/jme.c val |= SMBCSR_RELOAD; val 282 drivers/net/ethernet/jme.c jwrite32(jme, JME_SMBCSR, val); val 305 drivers/net/ethernet/jme.c u32 val; val 308 drivers/net/ethernet/jme.c val = jread32(jme, JME_RXUMA_LO); val 309 drivers/net/ethernet/jme.c macaddr[0] = (val >> 0) & 0xFF; val 310 drivers/net/ethernet/jme.c macaddr[1] = (val >> 8) & 0xFF; val 311 drivers/net/ethernet/jme.c macaddr[2] = (val >> 16) & 0xFF; val 312 drivers/net/ethernet/jme.c macaddr[3] = (val >> 24) & 0xFF; val 313 drivers/net/ethernet/jme.c val = jread32(jme, JME_RXUMA_HI); val 314 drivers/net/ethernet/jme.c macaddr[4] = (val >> 0) & 0xFF; val 315 drivers/net/ethernet/jme.c macaddr[5] = (val >> 8) & 0xFF; val 679 drivers/net/ethernet/jme.c u32 val; val 687 drivers/net/ethernet/jme.c val = jread32(jme, JME_TXCS); val 688 drivers/net/ethernet/jme.c for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) { val 690 drivers/net/ethernet/jme.c val = jread32(jme, JME_TXCS); val 916 drivers/net/ethernet/jme.c u32 val; val 924 drivers/net/ethernet/jme.c val = jread32(jme, JME_RXCS); val 925 drivers/net/ethernet/jme.c for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) { val 927 drivers/net/ethernet/jme.c val = jread32(jme, JME_RXCS); val 2262 drivers/net/ethernet/jme.c u32 val; val 2264 drivers/net/ethernet/jme.c val = (netdev->dev_addr[3] & 0xff) << 24 | val 2268 drivers/net/ethernet/jme.c jwrite32(jme, JME_RXUMA_LO, val); val 2269 drivers/net/ethernet/jme.c val = (netdev->dev_addr[5] & 0xff) << 8 | val 2271 drivers/net/ethernet/jme.c jwrite32(jme, JME_RXUMA_HI, val); val 2485 drivers/net/ethernet/jme.c u32 val; val 2491 drivers/net/ethernet/jme.c val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE); val 2495 drivers/net/ethernet/jme.c (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0; val 2503 drivers/net/ethernet/jme.c u32 val; val 2530 drivers/net/ethernet/jme.c val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE); val 2531 drivers/net/ethernet/jme.c if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^ val 2535 drivers/net/ethernet/jme.c val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); val 2537 drivers/net/ethernet/jme.c val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); val 2540 drivers/net/ethernet/jme.c MII_ADVERTISE, val); val 2644 drivers/net/ethernet/jme.c u16 val = mii_data->val_in; val 2645 drivers/net/ethernet/jme.c if (!(val & (BMCR_RESET|BMCR_ANENABLE)) && val 2646 drivers/net/ethernet/jme.c (val & BMCR_SPEED1000)) val 2731 drivers/net/ethernet/jme.c u32 val; val 2734 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBCSR); val 2736 drivers/net/ethernet/jme.c while ((val & SMBCSR_BUSY) && --to) { val 2738 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBCSR); val 2750 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBINTF); val 2752 drivers/net/ethernet/jme.c while ((val & SMBINTF_HWCMD) && --to) { val 2754 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBINTF); val 2761 drivers/net/ethernet/jme.c return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT; val 2767 drivers/net/ethernet/jme.c u32 val; val 2770 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBCSR); val 2772 drivers/net/ethernet/jme.c while ((val & SMBCSR_BUSY) && --to) { val 2774 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBCSR); val 2787 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBINTF); val 2789 drivers/net/ethernet/jme.c while ((val & SMBINTF_HWCMD) && --to) { val 2791 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBINTF); val 2805 drivers/net/ethernet/jme.c u32 val; val 2806 drivers/net/ethernet/jme.c val = jread32(jme, JME_SMBCSR); val 2807 drivers/net/ethernet/jme.c return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0; val 1175 drivers/net/ethernet/jme.h const char *msg, u32 val, u32 reg) val 1192 drivers/net/ethernet/jme.h msg, val, regname); val 1196 drivers/net/ethernet/jme.h const char *msg, u32 val, u32 reg) {} val 1207 drivers/net/ethernet/jme.h static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val) val 1209 drivers/net/ethernet/jme.h reg_dbg(jme, "REG WRITE", val, reg); val 1210 drivers/net/ethernet/jme.h writel(val, jme->regs + reg); val 1214 drivers/net/ethernet/jme.h static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val) val 1219 drivers/net/ethernet/jme.h reg_dbg(jme, "REG WRITE FLUSH", val, reg); val 1220 drivers/net/ethernet/jme.h writel(val, jme->regs + reg); val 311 drivers/net/ethernet/korina.c static void mdio_write(struct net_device *dev, int mii_id, int reg, int val) val 321 drivers/net/ethernet/korina.c writel(val, &lp->eth_regs->miimwtd); val 306 drivers/net/ethernet/lantiq_etop.c u32 val = MDIO_REQUEST | val 313 drivers/net/ethernet/lantiq_etop.c ltq_etop_w32(val, LTQ_ETOP_MDIO); val 320 drivers/net/ethernet/lantiq_etop.c u32 val = MDIO_REQUEST | MDIO_READ | val 326 drivers/net/ethernet/lantiq_etop.c ltq_etop_w32(val, LTQ_ETOP_MDIO); val 329 drivers/net/ethernet/lantiq_etop.c val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; val 330 drivers/net/ethernet/lantiq_etop.c return val; val 82 drivers/net/ethernet/lantiq_xrx200.c static void xrx200_pmac_w32(struct xrx200_priv *priv, u32 val, u32 offset) val 84 drivers/net/ethernet/lantiq_xrx200.c __raw_writel(val, priv->pmac_reg + offset); val 90 drivers/net/ethernet/lantiq_xrx200.c u32 val = xrx200_pmac_r32(priv, offset); val 92 drivers/net/ethernet/lantiq_xrx200.c val &= ~(clear); val 93 drivers/net/ethernet/lantiq_xrx200.c val |= set; val 94 drivers/net/ethernet/lantiq_xrx200.c xrx200_pmac_w32(priv, val, offset); val 1190 drivers/net/ethernet/marvell/mv643xx_eth.c u32 val; val 1206 drivers/net/ethernet/marvell/mv643xx_eth.c val = rdlp(mp, off); val 1207 drivers/net/ethernet/marvell/mv643xx_eth.c val |= 1 << txq->index; val 1208 drivers/net/ethernet/marvell/mv643xx_eth.c wrlp(mp, off, val); val 1359 drivers/net/ethernet/marvell/mv643xx_eth.c u32 val = rdlp(mp, SDMA_CONFIG); val 1363 drivers/net/ethernet/marvell/mv643xx_eth.c temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); val 1365 drivers/net/ethernet/marvell/mv643xx_eth.c temp = (val & 0x003fff00) >> 8; val 1377 drivers/net/ethernet/marvell/mv643xx_eth.c u32 val; val 1383 drivers/net/ethernet/marvell/mv643xx_eth.c val = rdlp(mp, SDMA_CONFIG); val 1387 drivers/net/ethernet/marvell/mv643xx_eth.c val &= ~0x023fff80; val 1388 drivers/net/ethernet/marvell/mv643xx_eth.c val |= (temp & 0x8000) << 10; val 1389 drivers/net/ethernet/marvell/mv643xx_eth.c val |= (temp & 0x7fff) << 7; val 1393 drivers/net/ethernet/marvell/mv643xx_eth.c val &= ~0x003fff00; val 1394 drivers/net/ethernet/marvell/mv643xx_eth.c val |= (temp & 0x3fff) << 8; val 1396 drivers/net/ethernet/marvell/mv643xx_eth.c wrlp(mp, SDMA_CONFIG, val); val 144 drivers/net/ethernet/marvell/mvmdio.c u32 val; val 163 drivers/net/ethernet/marvell/mvmdio.c val = readl(dev->regs); val 164 drivers/net/ethernet/marvell/mvmdio.c if (!(val & MVMDIO_SMI_READ_VALID)) { val 169 drivers/net/ethernet/marvell/mvmdio.c return val & GENMASK(15, 0); val 774 drivers/net/ethernet/marvell/mvneta.c u32 val; val 776 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); val 777 drivers/net/ethernet/marvell/mvneta.c return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; val 787 drivers/net/ethernet/marvell/mvneta.c u32 val; val 790 drivers/net/ethernet/marvell/mvneta.c val = rx_done | val 792 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); val 799 drivers/net/ethernet/marvell/mvneta.c val = rx_done; val 802 drivers/net/ethernet/marvell/mvneta.c val = 0xff; val 806 drivers/net/ethernet/marvell/mvneta.c val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; val 809 drivers/net/ethernet/marvell/mvneta.c val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; val 812 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); val 830 drivers/net/ethernet/marvell/mvneta.c u32 val; val 832 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); val 833 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; val 834 drivers/net/ethernet/marvell/mvneta.c val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << val 836 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); val 845 drivers/net/ethernet/marvell/mvneta.c u32 val; val 847 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); val 848 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; val 851 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); val 852 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); val 863 drivers/net/ethernet/marvell/mvneta.c u32 val; val 869 drivers/net/ethernet/marvell/mvneta.c val = min(pend_desc, 255); val 870 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); val 871 drivers/net/ethernet/marvell/mvneta.c pend_desc -= val; val 902 drivers/net/ethernet/marvell/mvneta.c u32 val; val 904 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); val 906 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_RXQ_BUF_SIZE_MASK; val 907 drivers/net/ethernet/marvell/mvneta.c val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); val 909 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); val 916 drivers/net/ethernet/marvell/mvneta.c u32 val; val 918 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); val 919 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_RXQ_HW_BUF_ALLOC; val 920 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); val 927 drivers/net/ethernet/marvell/mvneta.c u32 val; val 929 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); val 930 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_RXQ_HW_BUF_ALLOC; val 931 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); val 938 drivers/net/ethernet/marvell/mvneta.c u32 val; val 940 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); val 941 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; val 942 drivers/net/ethernet/marvell/mvneta.c val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); val 944 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); val 951 drivers/net/ethernet/marvell/mvneta.c u32 val; val 953 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); val 954 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; val 955 drivers/net/ethernet/marvell/mvneta.c val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); val 957 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); val 965 drivers/net/ethernet/marvell/mvneta.c u32 val; val 974 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); val 975 drivers/net/ethernet/marvell/mvneta.c val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; val 976 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); val 1175 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1179 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; val 1182 drivers/net/ethernet/marvell/mvneta.c if (val != 0) val 1184 drivers/net/ethernet/marvell/mvneta.c val << MVNETA_RXQ_DISABLE_SHIFT); val 1192 drivers/net/ethernet/marvell/mvneta.c val); val 1197 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_RXQ_CMD); val 1198 drivers/net/ethernet/marvell/mvneta.c } while (val & MVNETA_RXQ_ENABLE_MASK); val 1203 drivers/net/ethernet/marvell/mvneta.c val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; val 1205 drivers/net/ethernet/marvell/mvneta.c if (val != 0) val 1207 drivers/net/ethernet/marvell/mvneta.c (val << MVNETA_TXQ_DISABLE_SHIFT)); val 1215 drivers/net/ethernet/marvell/mvneta.c val); val 1221 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_TXQ_CMD); val 1223 drivers/net/ethernet/marvell/mvneta.c } while (val & MVNETA_TXQ_ENABLE_MASK); val 1231 drivers/net/ethernet/marvell/mvneta.c val); val 1236 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_PORT_STATUS); val 1237 drivers/net/ethernet/marvell/mvneta.c } while (!(val & MVNETA_TX_FIFO_EMPTY) && val 1238 drivers/net/ethernet/marvell/mvneta.c (val & MVNETA_TX_IN_PRGRS)); val 1246 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1249 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); val 1250 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_GMAC0_PORT_ENABLE; val 1251 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); val 1257 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1260 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); val 1261 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_GMAC0_PORT_ENABLE; val 1262 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); val 1273 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1276 drivers/net/ethernet/marvell/mvneta.c val = 0; val 1278 drivers/net/ethernet/marvell/mvneta.c val = 0x1 | (queue << 1); val 1279 drivers/net/ethernet/marvell/mvneta.c val |= (val << 24) | (val << 16) | (val << 8); val 1283 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); val 1290 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1293 drivers/net/ethernet/marvell/mvneta.c val = 0; val 1295 drivers/net/ethernet/marvell/mvneta.c val = 0x1 | (queue << 1); val 1296 drivers/net/ethernet/marvell/mvneta.c val |= (val << 24) | (val << 16) | (val << 8); val 1300 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); val 1308 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1312 drivers/net/ethernet/marvell/mvneta.c val = 0; val 1315 drivers/net/ethernet/marvell/mvneta.c val = 0x1 | (queue << 1); val 1316 drivers/net/ethernet/marvell/mvneta.c val |= (val << 24) | (val << 16) | (val << 8); val 1320 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); val 1373 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1436 drivers/net/ethernet/marvell/mvneta.c val = MVNETA_ACC_MODE_EXT2; val 1439 drivers/net/ethernet/marvell/mvneta.c val = MVNETA_ACC_MODE_EXT1; val 1440 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_ACC_MODE, val); val 1446 drivers/net/ethernet/marvell/mvneta.c val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); val 1447 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_CONFIG, val); val 1449 drivers/net/ethernet/marvell/mvneta.c val = 0; val 1450 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); val 1454 drivers/net/ethernet/marvell/mvneta.c val = 0; val 1457 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); val 1458 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); val 1459 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; val 1462 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_DESC_SWAP; val 1466 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_SDMA_CONFIG, val); val 1471 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_UNIT_CONTROL); val 1472 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_PHY_POLLING_ENABLE; val 1473 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_UNIT_CONTROL, val); val 1491 drivers/net/ethernet/marvell/mvneta.c u32 val, size, mtu; val 1499 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_TX_MTU); val 1500 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_TX_MTU_MAX; val 1501 drivers/net/ethernet/marvell/mvneta.c val |= mtu; val 1502 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TX_MTU, val); val 1505 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); val 1507 drivers/net/ethernet/marvell/mvneta.c size = val & MVNETA_TX_TOKEN_SIZE_MAX; val 1510 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_TX_TOKEN_SIZE_MAX; val 1511 drivers/net/ethernet/marvell/mvneta.c val |= size; val 1512 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); val 1515 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); val 1517 drivers/net/ethernet/marvell/mvneta.c size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; val 1520 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; val 1521 drivers/net/ethernet/marvell/mvneta.c val |= size; val 1522 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); val 1593 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1597 drivers/net/ethernet/marvell/mvneta.c val = (clk_rate / 1000000) * value; val 1599 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); val 1606 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1608 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); val 1610 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; val 1611 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_TXQ_SENT_THRESH_MASK(value); val 1613 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); val 1633 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1637 drivers/net/ethernet/marvell/mvneta.c val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; val 1638 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); val 1642 drivers/net/ethernet/marvell/mvneta.c val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; val 1643 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); val 1650 drivers/net/ethernet/marvell/mvneta.c u32 val; val 1653 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); val 1654 drivers/net/ethernet/marvell/mvneta.c sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> val 2677 drivers/net/ethernet/marvell/mvneta.c u32 port_cfg_reg, val; val 2681 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_TYPE_PRIO); val 2687 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_FORCE_UNI; val 2693 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_FORCE_UNI; val 2697 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_TYPE_PRIO, val); val 3609 drivers/net/ethernet/marvell/mvneta.c u32 val; val 3614 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); val 3615 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_GMAC_FORCE_LINK_PASS; val 3616 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_GMAC_FORCE_LINK_DOWN; val 3617 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); val 3630 drivers/net/ethernet/marvell/mvneta.c u32 val; val 3633 drivers/net/ethernet/marvell/mvneta.c val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); val 3634 drivers/net/ethernet/marvell/mvneta.c val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; val 3635 drivers/net/ethernet/marvell/mvneta.c val |= MVNETA_GMAC_FORCE_LINK_PASS; val 3636 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); val 4100 drivers/net/ethernet/marvell/mvneta.c u64 val; val 4106 drivers/net/ethernet/marvell/mvneta.c val = 0; val 4110 drivers/net/ethernet/marvell/mvneta.c val = readl_relaxed(base + s->offset); val 4116 drivers/net/ethernet/marvell/mvneta.c val = (u64)high << 32 | low; val 4121 drivers/net/ethernet/marvell/mvneta.c val = phylink_get_eee_err(pp->phylink); val 4124 drivers/net/ethernet/marvell/mvneta.c val = pp->rxqs[0].skb_alloc_err; val 4127 drivers/net/ethernet/marvell/mvneta.c val = pp->rxqs[0].refill_err; val 4133 drivers/net/ethernet/marvell/mvneta.c pp->ethtool_stats[i] += val; val 4179 drivers/net/ethernet/marvell/mvneta.c u32 val; val 4205 drivers/net/ethernet/marvell/mvneta.c val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); val 4206 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_PORT_CONFIG, val); val 42 drivers/net/ethernet/marvell/mvneta_bm.c u32 val; val 44 drivers/net/ethernet/marvell/mvneta_bm.c val = mvneta_bm_read(priv, MVNETA_BM_POOL_BASE_REG(pool_id)); val 45 drivers/net/ethernet/marvell/mvneta_bm.c val |= MVNETA_BM_POOL_ENABLE_MASK; val 46 drivers/net/ethernet/marvell/mvneta_bm.c mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(pool_id), val); val 54 drivers/net/ethernet/marvell/mvneta_bm.c u32 val; val 56 drivers/net/ethernet/marvell/mvneta_bm.c val = mvneta_bm_read(priv, MVNETA_BM_POOL_BASE_REG(pool_id)); val 57 drivers/net/ethernet/marvell/mvneta_bm.c val &= ~MVNETA_BM_POOL_ENABLE_MASK; val 58 drivers/net/ethernet/marvell/mvneta_bm.c mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(pool_id), val); val 63 drivers/net/ethernet/marvell/mvneta_bm.c u32 val; val 65 drivers/net/ethernet/marvell/mvneta_bm.c val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG); val 66 drivers/net/ethernet/marvell/mvneta_bm.c val |= mask; val 67 drivers/net/ethernet/marvell/mvneta_bm.c mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val); val 72 drivers/net/ethernet/marvell/mvneta_bm.c u32 val; val 74 drivers/net/ethernet/marvell/mvneta_bm.c val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG); val 75 drivers/net/ethernet/marvell/mvneta_bm.c val &= ~mask; val 76 drivers/net/ethernet/marvell/mvneta_bm.c mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val); val 82 drivers/net/ethernet/marvell/mvneta_bm.c u32 val; val 84 drivers/net/ethernet/marvell/mvneta_bm.c val = mvneta_bm_read(priv, MVNETA_BM_XBAR_POOL_REG(pool_id)); val 85 drivers/net/ethernet/marvell/mvneta_bm.c val &= ~MVNETA_BM_TARGET_ID_MASK(pool_id); val 86 drivers/net/ethernet/marvell/mvneta_bm.c val &= ~MVNETA_BM_XBAR_ATTR_MASK(pool_id); val 87 drivers/net/ethernet/marvell/mvneta_bm.c val |= MVNETA_BM_TARGET_ID_VAL(pool_id, target_id); val 88 drivers/net/ethernet/marvell/mvneta_bm.c val |= MVNETA_BM_XBAR_ATTR_VAL(pool_id, attr); val 90 drivers/net/ethernet/marvell/mvneta_bm.c mvneta_bm_write(priv, MVNETA_BM_XBAR_POOL_REG(pool_id), val); val 341 drivers/net/ethernet/marvell/mvneta_bm.c u32 val; val 350 drivers/net/ethernet/marvell/mvneta_bm.c val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG); val 353 drivers/net/ethernet/marvell/mvneta_bm.c val &= ~MVNETA_BM_MAX_IN_BURST_SIZE_MASK; val 354 drivers/net/ethernet/marvell/mvneta_bm.c val |= MVNETA_BM_MAX_IN_BURST_SIZE_16BP; val 355 drivers/net/ethernet/marvell/mvneta_bm.c mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val); val 54 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) val 57 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) val 60 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) val 184 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) val 302 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ val 306 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ val 362 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c u32 val; val 364 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val = (way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | lkpid; val 365 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); val 375 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c u32 val; val 377 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; val 378 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); val 498 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c u32 val; val 501 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_INV); val 503 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val &= ~MVPP22_CLS_C2_TCAM_INV_BIT; val 505 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val |= MVPP22_CLS_C2_TCAM_INV_BIT; val 506 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c mvpp2_write(priv, MVPP22_CLS_C2_TCAM_INV, val); val 526 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c u32 val; val 544 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_INV); val 545 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c c2->valid = !(val & MVPP22_CLS_C2_TCAM_INV_BIT); val 950 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c u32 val; val 953 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); val 954 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); val 955 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); val 1064 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c u32 val; val 1072 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); val 1073 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c val &= ~MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); val 1074 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); val 421 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c int val; val 423 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c val = mvpp2_prs_hits(entry->priv, entry->tid); val 424 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c if (val < 0) val 425 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c return val; val 427 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c seq_printf(s, "%d\n", val); val 178 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c __le64 val = cpu_to_le64(addr); val 181 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c tx_desc->pp22.buf_dma_addr_ptp |= val; val 349 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 384 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); val 385 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_BM_START_MASK; val 386 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); val 400 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 404 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); val 405 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); val 420 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 423 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); val 424 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); val 425 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> val 494 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 507 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); val 508 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_BM_STOP_MASK; val 509 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); val 592 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val, mask; val 603 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); val 604 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~mask; val 605 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; val 606 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); val 613 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val, mask; val 624 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); val 625 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~mask; val 626 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; val 627 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); val 668 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val = 0; val 671 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= upper_32_bits(buf_dma_addr) & val 675 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= (upper_32_bits(buf_phys_addr) val 680 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c MVPP22_BM_ADDR_HIGH_RLS_REG, val); val 1073 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1079 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = MVPP2_CAUSE_MISC_SUM_MASK | val 1082 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; val 1086 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c MVPP2_ISR_RX_TX_MASK_REG(port->id), val); val 1092 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1099 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = 0; val 1101 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); val 1110 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c MVPP2_ISR_RX_TX_MASK_REG(port->id), val); val 1124 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1126 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); val 1127 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; val 1128 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); val 1130 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); val 1132 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; val 1134 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= GENCONF_CTRL0_PORT1_RGMII_MII; val 1135 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); val 1141 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1143 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); val 1144 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | val 1146 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); val 1149 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); val 1151 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~GENCONF_CTRL0_PORT0_RGMII; val 1153 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; val 1154 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); val 1163 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1165 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(xpcs + MVPP22_XPCS_CFG0); val 1166 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | val 1168 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); val 1169 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, xpcs + MVPP22_XPCS_CFG0); val 1171 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(mpcs + MVPP22_MPCS_CTRL); val 1172 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; val 1173 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, mpcs + MVPP22_MPCS_CTRL); val 1175 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(mpcs + MVPP22_MPCS_CLK_RESET); val 1176 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); val 1177 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); val 1178 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, mpcs + MVPP22_MPCS_CLK_RESET); val 1184 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1212 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); val 1213 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | val 1215 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); val 1217 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); val 1218 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; val 1219 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); val 1221 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); val 1222 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= GENCONF_SOFT_RESET1_GOP; val 1223 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); val 1235 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1241 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); val 1242 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; val 1243 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); val 1248 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); val 1250 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_XLG_EXT_INT_MASK_XLG; val 1252 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_XLG_EXT_INT_MASK_GIG; val 1253 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); val 1259 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1262 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); val 1263 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | val 1265 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); val 1271 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); val 1272 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; val 1273 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); val 1279 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1285 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_GMAC_INT_MASK); val 1286 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_GMAC_INT_MASK_LINK_STAT; val 1287 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_GMAC_INT_MASK); val 1291 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_INT_MASK); val 1292 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_XLG_INT_MASK_LINK; val 1293 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_INT_MASK); val 1326 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1330 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); val 1331 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_XLG_CTRL0_PORT_EN; val 1332 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; val 1333 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); val 1335 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); val 1336 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_GMAC_PORT_EN_MASK; val 1337 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; val 1338 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); val 1344 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1348 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); val 1349 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_XLG_CTRL0_PORT_EN; val 1350 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); val 1353 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); val 1354 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~(MVPP2_GMAC_PORT_EN_MASK); val 1355 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); val 1361 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1363 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & val 1365 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); val 1372 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1374 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); val 1377 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_GMAC_GMII_LB_EN_MASK; val 1379 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; val 1383 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_GMAC_PCS_LB_EN_MASK; val 1385 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; val 1387 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); val 1399 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u64 val; val 1401 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->stats_base + counter->offset); val 1403 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val += (u64)readl(port->stats_base + counter->offset + 4) << 32; val 1405 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c return val; val 1605 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1607 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | val 1609 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); val 1612 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG) & val 1614 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); val 1622 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1630 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(mpcs + MVPP22_MPCS_CLK_RESET); val 1631 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); val 1632 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_MPCS_CLK_RESET_DIV_SET; val 1633 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, mpcs + MVPP22_MPCS_CLK_RESET); val 1635 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(xpcs + MVPP22_XPCS_CFG0); val 1636 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); val 1643 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1653 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(mpcs + MVPP22_MPCS_CLK_RESET); val 1654 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | val 1656 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; val 1657 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, mpcs + MVPP22_MPCS_CLK_RESET); val 1661 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(xpcs + MVPP22_XPCS_CFG0); val 1662 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); val 1672 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1674 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); val 1675 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; val 1676 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << val 1678 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); val 1684 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1686 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL1_REG); val 1687 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; val 1688 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << val 1690 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL1_REG); val 1696 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c int tx_port_num, val, queue, lrxq; val 1700 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); val 1701 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; val 1703 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); val 1704 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); val 1726 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); val 1727 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; val 1728 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); val 1729 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; val 1730 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); val 1731 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = MVPP2_TXP_TOKEN_SIZE_MAX; val 1732 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); val 1742 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); val 1743 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_SNOOP_PKT_SIZE_MASK | val 1745 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); val 1755 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1760 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); val 1761 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_RXQ_DISABLE_MASK; val 1762 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); val 1768 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1773 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); val 1774 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_RXQ_DISABLE_MASK; val 1775 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); val 1843 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); val 1845 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c return val & MVPP2_RXQ_OCCUPIED_MASK; val 1858 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); val 1860 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); val 1878 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1883 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); val 1884 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; val 1887 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & val 1890 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); val 1931 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val = mvpp2_read_relaxed(port->priv, val 1934 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; val 1953 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 1955 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; val 1956 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); val 1958 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); val 1960 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c return val & MVPP2_TXQ_RSVD_RSLT_MASK; val 2061 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 2064 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_thread_read_relaxed(port->priv, val 2068 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> val 2096 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val, size, mtu; val 2111 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); val 2112 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_TXP_MTU_MAX; val 2113 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= mtu; val 2114 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); val 2117 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); val 2118 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c size = val & MVPP2_TXP_TOKEN_SIZE_MAX; val 2121 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; val 2122 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= size; val 2123 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); val 2127 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, val 2129 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; val 2133 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; val 2134 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= size; val 2137 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val); val 2165 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 2170 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); val 2172 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); val 2200 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); val 2202 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { val 2207 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_usec_to_cycles(rxq->time_coal, freq); val 2210 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); val 2216 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); val 2218 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { val 2223 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); val 2226 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); val 2456 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 2482 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); val 2483 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_TXQ_PENDING_MASK; val 2484 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); val 2504 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); val 2505 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; val 2506 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); val 2507 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; val 2508 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); val 2510 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = MVPP2_TXQ_TOKEN_SIZE_MAX; val 2512 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val); val 2591 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 2594 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); val 2595 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_TXQ_DRAIN_EN_MASK; val 2596 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); val 2617 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_TXQ_DRAIN_EN_MASK; val 2618 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); val 2639 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 2641 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); val 2644 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); val 2645 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); val 2655 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); val 2656 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); val 2736 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 2741 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_INT_STAT); val 2742 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP22_XLG_INT_STAT_LINK) { val 2744 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_STATUS); val 2745 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP22_XLG_STATUS_LINK_UP) val 2751 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_GMAC_INT_STAT); val 2752 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP22_GMAC_INT_STAT_LINK) { val 2754 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_STATUS0); val 2755 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP2_GMAC_STATUS0_LINK_UP) val 4513 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 4529 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = qv->sw_thread_id; val 4530 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; val 4531 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); val 4533 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = qv->first_rxq; val 4534 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; val 4535 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); val 4825 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 4831 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_STATUS); val 4832 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); val 4835 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); val 4836 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) val 4838 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) val 4845 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 4847 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_STATUS0); val 4849 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); val 4850 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); val 4851 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); val 4861 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) val 4863 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) val 4870 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) val 4872 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) val 4900 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); val 4902 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, val 4904 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, val 5132 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 5136 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); val 5137 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; val 5138 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS; val 5139 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); val 5141 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); val 5142 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; val 5143 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_GMAC_FORCE_LINK_PASS; val 5144 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); val 5160 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 5164 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); val 5165 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; val 5166 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; val 5167 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); val 5169 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); val 5170 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP2_GMAC_FORCE_LINK_PASS; val 5171 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_GMAC_FORCE_LINK_DOWN; val 5172 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); val 5566 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val, rdval, wrval; val 5596 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = MVPP22_AXI_CODE_CACHE_NON_CACHE val 5598 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM val 5600 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); val 5601 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); val 5603 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = MVPP22_AXI_CODE_CACHE_RD_CACHE val 5605 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM val 5608 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); val 5610 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = MVPP22_AXI_CODE_CACHE_WR_CACHE val 5612 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM val 5615 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); val 5623 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val; val 5635 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); val 5636 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= MVPP2_PHY_AN_STOP_SMI0_MASK; val 5637 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); val 5639 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); val 5640 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~MVPP22_SMI_POLLING_EN; val 5641 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); val 211 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c u32 val) val 213 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num))); val 218 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c u32 val) val 220 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num))); val 1071 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c u32 val; val 1074 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG); val 1075 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val &= ~MVPP2_PRS_PORT_LU_MASK(port); val 1076 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); val 1077 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); val 1080 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); val 1081 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); val 1082 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); val 1083 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); val 1088 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); val 1089 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val &= ~MVPP2_PRS_INIT_OFF_MASK(port); val 1090 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); val 1091 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); val 2486 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c u32 val; val 2493 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val = mvpp2_read(priv, MVPP2_PRS_TCAM_HIT_CNT_REG); val 2495 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c val &= MVPP2_PRS_TCAM_HIT_CNT_MASK; val 2497 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c return val; val 84 drivers/net/ethernet/marvell/octeontx2/af/cgx.c static void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) val 86 drivers/net/ethernet/marvell/octeontx2/af/cgx.c writeq(val, cgx->reg_base + (lmac << 18) + offset); val 927 drivers/net/ethernet/marvell/octeontx2/af/rvu.c u64 val; val 929 drivers/net/ethernet/marvell/octeontx2/af/rvu.c val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); val 930 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, block->addr, block->lookup_reg, val); val 936 drivers/net/ethernet/marvell/octeontx2/af/rvu.c val = rvu_read64(rvu, block->addr, block->lookup_reg); val 939 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!(val & (1ULL << 12))) val 942 drivers/net/ethernet/marvell/octeontx2/af/rvu.c return (val & 0xFFF); val 268 drivers/net/ethernet/marvell/octeontx2/af/rvu.h static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) val 270 drivers/net/ethernet/marvell/octeontx2/af/rvu.h writeq(val, rvu->afreg_base + ((block << 28) | offset)); val 278 drivers/net/ethernet/marvell/octeontx2/af/rvu.h static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) val 280 drivers/net/ethernet/marvell/octeontx2/af/rvu.h writeq(val, rvu->pfreg_base + offset); val 39 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c u64 val = 0; val 46 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c val = pkind | 1ULL << 62; val 47 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); val 565 drivers/net/ethernet/marvell/pxa168_eth.c u32 val; val 567 drivers/net/ethernet/marvell/pxa168_eth.c val = rdl(pep, PORT_CONFIG); val 569 drivers/net/ethernet/marvell/pxa168_eth.c val |= PCR_PM; val 571 drivers/net/ethernet/marvell/pxa168_eth.c val &= ~PCR_PM; val 572 drivers/net/ethernet/marvell/pxa168_eth.c wrl(pep, PORT_CONFIG, val); val 629 drivers/net/ethernet/marvell/pxa168_eth.c unsigned int val = 0; val 654 drivers/net/ethernet/marvell/pxa168_eth.c val = rdl(pep, PORT_CONFIG); val 655 drivers/net/ethernet/marvell/pxa168_eth.c val |= PCR_EN; val 656 drivers/net/ethernet/marvell/pxa168_eth.c wrl(pep, PORT_CONFIG, val); val 659 drivers/net/ethernet/marvell/pxa168_eth.c val = rdl(pep, SDMA_CMD); val 660 drivers/net/ethernet/marvell/pxa168_eth.c val |= SDMA_CMD_ERD; val 661 drivers/net/ethernet/marvell/pxa168_eth.c wrl(pep, SDMA_CMD, val); val 667 drivers/net/ethernet/marvell/pxa168_eth.c unsigned int val = 0; val 676 drivers/net/ethernet/marvell/pxa168_eth.c val = rdl(pep, SDMA_CMD); val 677 drivers/net/ethernet/marvell/pxa168_eth.c val &= ~SDMA_CMD_ERD; /* abort dma command */ val 685 drivers/net/ethernet/marvell/pxa168_eth.c val = rdl(pep, PORT_CONFIG); val 686 drivers/net/ethernet/marvell/pxa168_eth.c val &= ~PCR_EN; val 687 drivers/net/ethernet/marvell/pxa168_eth.c wrl(pep, PORT_CONFIG, val); val 1306 drivers/net/ethernet/marvell/pxa168_eth.c int val; val 1314 drivers/net/ethernet/marvell/pxa168_eth.c for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) { val 1323 drivers/net/ethernet/marvell/pxa168_eth.c return val & 0xffff; val 96 drivers/net/ethernet/marvell/skge.c static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); val 97 drivers/net/ethernet/marvell/skge.c static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); val 797 drivers/net/ethernet/marvell/skge.c u32 val; val 805 drivers/net/ethernet/marvell/skge.c pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val); val 806 drivers/net/ethernet/marvell/skge.c return val; val 809 drivers/net/ethernet/marvell/skge.c static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val) val 811 drivers/net/ethernet/marvell/skge.c pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val); val 835 drivers/net/ethernet/marvell/skge.c u32 val = skge_vpd_read(pdev, cap, offset); val 836 drivers/net/ethernet/marvell/skge.c int n = min_t(int, length, sizeof(val)); val 838 drivers/net/ethernet/marvell/skge.c memcpy(data, &val, n); val 862 drivers/net/ethernet/marvell/skge.c u32 val; val 863 drivers/net/ethernet/marvell/skge.c int n = min_t(int, length, sizeof(val)); val 865 drivers/net/ethernet/marvell/skge.c if (n < sizeof(val)) val 866 drivers/net/ethernet/marvell/skge.c val = skge_vpd_read(pdev, cap, offset); val 867 drivers/net/ethernet/marvell/skge.c memcpy(&val, data, n); val 869 drivers/net/ethernet/marvell/skge.c skge_vpd_write(pdev, cap, offset, val); val 1084 drivers/net/ethernet/marvell/skge.c static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) val 1089 drivers/net/ethernet/marvell/skge.c *val = xm_read16(hw, port, XM_PHY_DATA); val 1102 drivers/net/ethernet/marvell/skge.c *val = xm_read16(hw, port, XM_PHY_DATA); val 1115 drivers/net/ethernet/marvell/skge.c static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) val 1128 drivers/net/ethernet/marvell/skge.c xm_write16(hw, port, XM_PHY_DATA, val); val 1285 drivers/net/ethernet/marvell/skge.c u16 val; val 1312 drivers/net/ethernet/marvell/skge.c C0hack[i].reg, C0hack[i].val); val 1322 drivers/net/ethernet/marvell/skge.c A1hack[i].reg, A1hack[i].val); val 1893 drivers/net/ethernet/marvell/skge.c static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) val 1897 drivers/net/ethernet/marvell/skge.c gma_write16(hw, port, GM_SMI_DATA, val); val 1911 drivers/net/ethernet/marvell/skge.c static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) val 1927 drivers/net/ethernet/marvell/skge.c *val = gma_read16(hw, port, GM_SMI_DATA); val 2452 drivers/net/ethernet/marvell/skge.c u16 val = 0; val 2456 drivers/net/ethernet/marvell/skge.c err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); val 2458 drivers/net/ethernet/marvell/skge.c err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); val 2460 drivers/net/ethernet/marvell/skge.c data->val_out = val; val 2497 drivers/net/ethernet/marvell/skge.h static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val) val 2499 drivers/net/ethernet/marvell/skge.h writel(val, hw->regs + reg); val 2502 drivers/net/ethernet/marvell/skge.h static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val) val 2504 drivers/net/ethernet/marvell/skge.h writew(val, hw->regs + reg); val 2507 drivers/net/ethernet/marvell/skge.h static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val) val 2509 drivers/net/ethernet/marvell/skge.h writeb(val, hw->regs + reg); val 150 drivers/net/ethernet/marvell/sky2.c static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) val 154 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_SMI_DATA, val); val 177 drivers/net/ethernet/marvell/sky2.c static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) val 190 drivers/net/ethernet/marvell/sky2.c *val = gma_read16(hw, port, GM_SMI_DATA); val 631 drivers/net/ethernet/marvell/sky2.c u16 reg, val; val 670 drivers/net/ethernet/marvell/sky2.c gm_phy_write(hw, port, 17, eee_afe[i].val); val 1380 drivers/net/ethernet/marvell/sky2.c u16 val = 0; val 1383 drivers/net/ethernet/marvell/sky2.c err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); val 1386 drivers/net/ethernet/marvell/sky2.c data->val_out = val; val 4285 drivers/net/ethernet/marvell/sky2.c u32 val; val 4292 drivers/net/ethernet/marvell/sky2.c val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); val 4294 drivers/net/ethernet/marvell/sky2.c memcpy(data, &val, min(sizeof(val), length)); val 4310 drivers/net/ethernet/marvell/sky2.c u32 val = *(u32 *)(data + i); val 4312 drivers/net/ethernet/marvell/sky2.c sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); val 2336 drivers/net/ethernet/marvell/sky2.h static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) val 2338 drivers/net/ethernet/marvell/sky2.h writel(val, hw->regs + reg); val 2341 drivers/net/ethernet/marvell/sky2.h static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) val 2343 drivers/net/ethernet/marvell/sky2.h writew(val, hw->regs + reg); val 2346 drivers/net/ethernet/marvell/sky2.h static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) val 2348 drivers/net/ethernet/marvell/sky2.h writeb(val, hw->regs + reg); val 2381 drivers/net/ethernet/marvell/sky2.h u32 val; val 2384 drivers/net/ethernet/marvell/sky2.h val = gma_read32(hw, port, reg); val 2385 drivers/net/ethernet/marvell/sky2.h } while (gma_read32(hw, port, reg) != val); val 2387 drivers/net/ethernet/marvell/sky2.h return val; val 2392 drivers/net/ethernet/marvell/sky2.h u64 val; val 2395 drivers/net/ethernet/marvell/sky2.h val = gma_read64(hw, port, reg); val 2396 drivers/net/ethernet/marvell/sky2.h } while (gma_read64(hw, port, reg) != val); val 2398 drivers/net/ethernet/marvell/sky2.h return val; val 2425 drivers/net/ethernet/marvell/sky2.h static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) val 2427 drivers/net/ethernet/marvell/sky2.h sky2_write32(hw, Y2_CFG_SPC + reg, val); val 2430 drivers/net/ethernet/marvell/sky2.h static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) val 2432 drivers/net/ethernet/marvell/sky2.h sky2_write16(hw, Y2_CFG_SPC + reg, val); val 46 drivers/net/ethernet/mediatek/mtk_eth_path.c u32 val, mask, set; val 63 drivers/net/ethernet/mediatek/mtk_eth_path.c val = mtk_r32(eth, MTK_MAC_MISC); val 64 drivers/net/ethernet/mediatek/mtk_eth_path.c val = (val & mask) | set; val 65 drivers/net/ethernet/mediatek/mtk_eth_path.c mtk_w32(eth, val, MTK_MAC_MISC); val 76 drivers/net/ethernet/mediatek/mtk_eth_path.c unsigned int val = 0; val 81 drivers/net/ethernet/mediatek/mtk_eth_path.c val = ~(u32)GEPHY_MAC_SEL; val 89 drivers/net/ethernet/mediatek/mtk_eth_path.c regmap_update_bits(eth->infra, INFRA_MISC2, GEPHY_MAC_SEL, val); val 99 drivers/net/ethernet/mediatek/mtk_eth_path.c unsigned int val = 0; val 104 drivers/net/ethernet/mediatek/mtk_eth_path.c val = CO_QPHY_SEL; val 112 drivers/net/ethernet/mediatek/mtk_eth_path.c regmap_update_bits(eth->infra, INFRA_MISC2, CO_QPHY_SEL, val); val 122 drivers/net/ethernet/mediatek/mtk_eth_path.c unsigned int val = 0; val 127 drivers/net/ethernet/mediatek/mtk_eth_path.c val = SYSCFG0_SGMII_GMAC1; val 130 drivers/net/ethernet/mediatek/mtk_eth_path.c val = SYSCFG0_SGMII_GMAC2; val 134 drivers/net/ethernet/mediatek/mtk_eth_path.c regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); val 135 drivers/net/ethernet/mediatek/mtk_eth_path.c val &= SYSCFG0_SGMII_MASK; val 137 drivers/net/ethernet/mediatek/mtk_eth_path.c if ((path == MTK_GMAC1_RGMII && val == SYSCFG0_SGMII_GMAC1) || val 138 drivers/net/ethernet/mediatek/mtk_eth_path.c (path == MTK_GMAC2_RGMII && val == SYSCFG0_SGMII_GMAC2)) val 139 drivers/net/ethernet/mediatek/mtk_eth_path.c val = 0; val 150 drivers/net/ethernet/mediatek/mtk_eth_path.c SYSCFG0_SGMII_MASK, val); val 160 drivers/net/ethernet/mediatek/mtk_eth_path.c unsigned int val = 0; val 163 drivers/net/ethernet/mediatek/mtk_eth_path.c regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); val 167 drivers/net/ethernet/mediatek/mtk_eth_path.c val |= SYSCFG0_SGMII_GMAC1_V2; val 170 drivers/net/ethernet/mediatek/mtk_eth_path.c val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; val 173 drivers/net/ethernet/mediatek/mtk_eth_path.c val |= SYSCFG0_SGMII_GMAC2_V2; val 181 drivers/net/ethernet/mediatek/mtk_eth_path.c SYSCFG0_SGMII_MASK, val); val 58 drivers/net/ethernet/mediatek/mtk_eth_soc.c void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) val 60 drivers/net/ethernet/mediatek/mtk_eth_soc.c __raw_writel(val, eth->base + reg); val 70 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 72 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, reg); val 73 drivers/net/ethernet/mediatek/mtk_eth_soc.c val &= ~mask; val 74 drivers/net/ethernet/mediatek/mtk_eth_soc.c val |= set; val 75 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val, reg); val 135 drivers/net/ethernet/mediatek/mtk_eth_soc.c int phy_reg, u16 val) val 139 drivers/net/ethernet/mediatek/mtk_eth_soc.c return _mtk_mdio_write(eth, phy_addr, phy_reg, val); val 152 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 157 drivers/net/ethernet/mediatek/mtk_eth_soc.c regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); val 159 drivers/net/ethernet/mediatek/mtk_eth_soc.c val & SYSCFG_DRAM_TYPE_DDR2) { val 165 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = (interface == PHY_INTERFACE_MODE_TRGMII) ? val 169 drivers/net/ethernet/mediatek/mtk_eth_soc.c ETHSYS_TRGMII_MT7621_MASK, val); val 176 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 179 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = (speed == SPEED_1000) ? val 181 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val, INTF_MODE); val 187 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = (speed == SPEED_1000) ? 250000000 : 500000000; val 188 drivers/net/ethernet/mediatek/mtk_eth_soc.c ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); val 192 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = (speed == SPEED_1000) ? val 194 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val, TRGMII_RCK_CTRL); val 196 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = (speed == SPEED_1000) ? val 198 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val, TRGMII_TCK_CTRL); val 208 drivers/net/ethernet/mediatek/mtk_eth_soc.c int val, ge_mode, err; val 302 drivers/net/ethernet/mediatek/mtk_eth_soc.c regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); val 303 drivers/net/ethernet/mediatek/mtk_eth_soc.c val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); val 304 drivers/net/ethernet/mediatek/mtk_eth_soc.c val |= SYSCFG0_GE_MODE(ge_mode, mac->id); val 305 drivers/net/ethernet/mediatek/mtk_eth_soc.c regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); val 316 drivers/net/ethernet/mediatek/mtk_eth_soc.c regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); val 337 drivers/net/ethernet/mediatek/mtk_eth_soc.c SYSCFG0_SGMII_MASK, val); val 593 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 596 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, eth->tx_int_mask_reg); val 597 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); val 604 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 607 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, eth->tx_int_mask_reg); val 608 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val | mask, eth->tx_int_mask_reg); val 615 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 618 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, MTK_PDMA_INT_MASK); val 619 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); val 626 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 629 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, MTK_PDMA_INT_MASK); val 630 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); val 1803 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 1810 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); val 1811 drivers/net/ethernet/mediatek/mtk_eth_soc.c if (val & MTK_LRO_RING_RELINQUISH_DONE) { val 2241 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val; val 2246 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, glo_cfg); val 2247 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), val 2253 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, glo_cfg); val 2254 drivers/net/ethernet/mediatek/mtk_eth_soc.c if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { val 2333 drivers/net/ethernet/mediatek/mtk_eth_soc.c int i, val, ret; val 2387 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); val 2388 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); val 2411 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); val 2414 drivers/net/ethernet/mediatek/mtk_eth_soc.c val &= ~0xffff; val 2417 drivers/net/ethernet/mediatek/mtk_eth_soc.c val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; val 2420 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); val 926 drivers/net/ethernet/mediatek/mtk_eth_soc.h void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); val 38 drivers/net/ethernet/mediatek/mtk_sgmii.c unsigned int val; val 47 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); val 48 drivers/net/ethernet/mediatek/mtk_sgmii.c val |= SGMII_REMOTE_FAULT_DIS; val 49 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); val 51 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val); val 52 drivers/net/ethernet/mediatek/mtk_sgmii.c val |= SGMII_AN_RESTART; val 53 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val); val 55 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); val 56 drivers/net/ethernet/mediatek/mtk_sgmii.c val &= ~SGMII_PHYA_PWD; val 57 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val); val 65 drivers/net/ethernet/mediatek/mtk_sgmii.c unsigned int val; val 70 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_read(ss->regmap[id], ss->ana_rgc3, &val); val 71 drivers/net/ethernet/mediatek/mtk_sgmii.c val &= ~RG_PHY_SPEED_MASK; val 73 drivers/net/ethernet/mediatek/mtk_sgmii.c val |= RG_PHY_SPEED_3_125G; val 74 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_write(ss->regmap[id], ss->ana_rgc3, val); val 77 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val); val 78 drivers/net/ethernet/mediatek/mtk_sgmii.c val &= ~SGMII_AN_ENABLE; val 79 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val); val 82 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); val 83 drivers/net/ethernet/mediatek/mtk_sgmii.c val &= ~SGMII_IF_MODE_MASK; val 87 drivers/net/ethernet/mediatek/mtk_sgmii.c val |= SGMII_SPEED_10; val 90 drivers/net/ethernet/mediatek/mtk_sgmii.c val |= SGMII_SPEED_100; val 94 drivers/net/ethernet/mediatek/mtk_sgmii.c val |= SGMII_SPEED_1000; val 99 drivers/net/ethernet/mediatek/mtk_sgmii.c val |= SGMII_DUPLEX_FULL; val 101 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); val 104 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); val 105 drivers/net/ethernet/mediatek/mtk_sgmii.c val &= ~SGMII_PHYA_PWD; val 106 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val); val 114 drivers/net/ethernet/mediatek/mtk_sgmii.c unsigned int val, sid; val 123 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val); val 124 drivers/net/ethernet/mediatek/mtk_sgmii.c val |= SGMII_AN_RESTART; val 125 drivers/net/ethernet/mediatek/mtk_sgmii.c regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val); val 266 drivers/net/ethernet/mellanox/mlx4/cmd.c u32 val; val 281 drivers/net/ethernet/mellanox/mlx4/cmd.c val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31); val 282 drivers/net/ethernet/mellanox/mlx4/cmd.c __raw_writel((__force u32) cpu_to_be32(val), val 221 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) val 223 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; val 1996 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c int val, ret = 0; val 2000 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c val = *(u32 *)data; val 2001 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c if (val < MIN_PKT_LEN || val > MAX_INLINE) val 2004 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c priv->prof->inline_thold = val; val 61 drivers/net/ethernet/mellanox/mlx4/fw.c __be64 val; \ val 66 drivers/net/ethernet/mellanox/mlx4/fw.c case 8: val = get_unaligned((__be64 *)__p); \ val 67 drivers/net/ethernet/mellanox/mlx4/fw.c (dest) = be64_to_cpu(val); break; \ val 1790 drivers/net/ethernet/mellanox/mlx4/fw.c u32 val; val 1793 drivers/net/ethernet/mellanox/mlx4/fw.c val = get_unaligned(addr); val 1794 drivers/net/ethernet/mellanox/mlx4/fw.c val = swab32(val); val 1795 drivers/net/ethernet/mellanox/mlx4/fw.c put_unaligned(val, &bid_u32[i]); val 184 drivers/net/ethernet/mellanox/mlx4/main.c ctx->val.vbool = !!mlx4_internal_err_reset; val 191 drivers/net/ethernet/mellanox/mlx4/main.c mlx4_internal_err_reset = ctx->val.vbool; val 201 drivers/net/ethernet/mellanox/mlx4/main.c ctx->val.vbool = dev->persist->crdump.snapshot_enable; val 211 drivers/net/ethernet/mellanox/mlx4/main.c dev->persist->crdump.snapshot_enable = ctx->val.vbool; val 217 drivers/net/ethernet/mellanox/mlx4/main.c union devlink_param_value val, val 220 drivers/net/ethernet/mellanox/mlx4/main.c u32 value = val.vu32; val 778 drivers/net/ethernet/mellanox/mlx4/main.c void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) val 785 drivers/net/ethernet/mellanox/mlx4/main.c priv->virt2phys_pkey[slave][port - 1][i] = val; val 1376 drivers/net/ethernet/mellanox/mlx4/mlx4.h static inline void set_param_l(u64 *arg, u32 val) val 1378 drivers/net/ethernet/mellanox/mlx4/mlx4.h *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; val 1381 drivers/net/ethernet/mellanox/mlx4/mlx4.h static inline void set_param_h(u64 *arg, u32 val) val 1383 drivers/net/ethernet/mellanox/mlx4/mlx4.h *arg = (*arg & 0xffffffff) | ((u64) val << 32); val 115 drivers/net/ethernet/mellanox/mlx5/core/devlink.c union devlink_param_value val, val 119 drivers/net/ethernet/mellanox/mlx5/core/devlink.c char *value = val.vstr; val 157 drivers/net/ethernet/mellanox/mlx5/core/devlink.c if (!strcmp(ctx->val.vstr, "smfs")) val 172 drivers/net/ethernet/mellanox/mlx5/core/devlink.c strcpy(ctx->val.vstr, "smfs"); val 174 drivers/net/ethernet/mellanox/mlx5/core/devlink.c strcpy(ctx->val.vstr, "dmfs"); val 39 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c #define MASK_VAL(type, spec, name, mask, val, fld) \ val 42 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c .v = MLX5_GET(spec, val, fld)} val 43 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c #define MASK_VAL_BE(type, spec, name, mask, val, fld) \ val 46 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c .v = MLX5_GET_BE(type, spec, val, fld)} val 49 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c #define GET_MASK_VAL(name, type, mask, val, fld) \ val 51 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c name.v = MLX5_GET(type, val, fld), \ val 227 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &fte->val, val 232 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &fte->val, val 237 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &fte->val, val 981 drivers/net/ethernet/mellanox/mlx5/core/en.h int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); val 1577 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c static void mlx5e_set_msglevel(struct net_device *dev, u32 val) val 1579 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val; val 115 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c static void mask_spec(u8 *mask, u8 *val, size_t size) val 119 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c for (i = 0; i < size; i++, mask++, val++) val 120 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c *((u8 *)val) = *((u8 *)mask) & *((u8 *)val); val 2225 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset, val 2237 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c *curr_pval |= (val & mask); val 2511 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c u32 mask, val, offset; val 2529 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c val = act->mangle.val; val 2532 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]); val 2757 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16), val 753 drivers/net/ethernet/mellanox/mlx5/core/eq.c u32 val; val 756 drivers/net/ethernet/mellanox/mlx5/core/eq.c val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); val 758 drivers/net/ethernet/mellanox/mlx5/core/eq.c __raw_writel((__force u32)cpu_to_be32(val), addr); val 352 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val) val 357 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none"); val 362 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val); val 770 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val, val 777 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val)) val 786 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val)) { val 789 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val, val 794 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val, val 800 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val, val 805 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val, val 813 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte_match_param, fte->val, val 957 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val, val 971 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fte->val, val 481 drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c memcpy(in_match_value, &fte->val, sizeof(fte->val)); val 212 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c .key_len = FIELD_SIZEOF(struct fs_fte, val), val 213 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c .key_offset = offsetof(struct fs_fte, val), val 627 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c memcpy(fte->val, &spec->match_value, sizeof(fte->val)); val 198 drivers/net/ethernet/mellanox/mlx5/core/fs_core.h u32 val[MLX5_ST_SZ_DW_MATCH_PARAM]; val 65 drivers/net/ethernet/mellanox/mlx5/core/lib/eq.h u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); val 67 drivers/net/ethernet/mellanox/mlx5/core/lib/eq.h __raw_writel((__force u32)cpu_to_be32(val), addr); val 21 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c #define vsc_read(dev, offset, val) \ val 22 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c pci_read_config_dword((dev)->pdev, (dev)->vsc_addr + (offset), (val)) val 23 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c #define vsc_write(dev, offset, val) \ val 24 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c pci_write_config_dword((dev)->pdev, (dev)->vsc_addr + (offset), (val)) val 127 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c u32 val = 0; val 136 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c ret = vsc_read(dev, VSC_CTRL_OFFSET, &val); val 141 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c val = MLX5_MERGE(val, space, VSC_SPACE_BIT_OFFS, VSC_SPACE_BIT_LEN); val 142 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c ret = vsc_write(dev, VSC_CTRL_OFFSET, val); val 147 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c ret = vsc_read(dev, VSC_CTRL_OFFSET, &val); val 151 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c if (MLX5_EXTRACT(val, VSC_STATUS_BIT_OFFS, VSC_STATUS_BIT_LEN) == 0) val 156 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c MLX5_EXTRACT(val, VSC_SIZE_VLD_BIT_OFFS, VSC_SIZE_VLD_BIT_LEN)) { val 157 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c ret = vsc_read(dev, VSC_ADDR_OFFSET, &val); val 162 drivers/net/ethernet/mellanox/mlx5/core/lib/pci_vsc.c *ret_space_size = MLX5_EXTRACT(val, VSC_ADDR_BIT_OFFS, val 246 drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c match_sz = sizeof(fte->val); val 417 drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c params.match_buf = (u64 *)fte->val; val 101 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c unsigned long val; val 105 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c err = kstrtoul(buf, 10, &val); val 108 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c if (val != 1) val 190 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c unsigned long val; val 193 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c err = kstrtoul(buf, 10, &val); val 196 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c if (val > 255) val 199 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c mlxsw_reg_mfsc_pack(mfsc_pl, mlwsw_hwmon_attr->type_index, val); val 129 drivers/net/ethernet/mellanox/mlxsw/i2c.c __be32 *val = (__be32 *) buf; val 131 drivers/net/ethernet/mellanox/mlxsw/i2c.c *val = htonl(off); val 60 drivers/net/ethernet/mellanox/mlxsw/item.h unsigned short index, u8 val) val 69 drivers/net/ethernet/mellanox/mlxsw/item.h val <<= item->shift; val 70 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; val 73 drivers/net/ethernet/mellanox/mlxsw/item.h tmp |= val; val 94 drivers/net/ethernet/mellanox/mlxsw/item.h unsigned short index, u16 val) val 103 drivers/net/ethernet/mellanox/mlxsw/item.h val <<= item->shift; val 104 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; val 107 drivers/net/ethernet/mellanox/mlxsw/item.h tmp |= val; val 128 drivers/net/ethernet/mellanox/mlxsw/item.h unsigned short index, u32 val) val 137 drivers/net/ethernet/mellanox/mlxsw/item.h val <<= item->shift; val 138 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; val 141 drivers/net/ethernet/mellanox/mlxsw/item.h tmp |= val; val 162 drivers/net/ethernet/mellanox/mlxsw/item.h unsigned short index, u64 val) val 170 drivers/net/ethernet/mellanox/mlxsw/item.h val <<= item->shift; val 171 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; val 174 drivers/net/ethernet/mellanox/mlxsw/item.h tmp |= val; val 244 drivers/net/ethernet/mellanox/mlxsw/item.h u16 index, u8 val) val 250 drivers/net/ethernet/mellanox/mlxsw/item.h val <<= shift; val 251 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; val 254 drivers/net/ethernet/mellanox/mlxsw/item.h tmp |= val; val 277 drivers/net/ethernet/mellanox/mlxsw/item.h static inline void mlxsw_##_type##_##_cname##_##_iname##_set(char *buf, u8 val)\ val 279 drivers/net/ethernet/mellanox/mlxsw/item.h __mlxsw_item_set8(buf, &__ITEM_NAME(_type, _cname, _iname), 0, val); \ val 301 drivers/net/ethernet/mellanox/mlxsw/item.h u8 val) \ val 304 drivers/net/ethernet/mellanox/mlxsw/item.h index, val); \ val 318 drivers/net/ethernet/mellanox/mlxsw/item.h static inline void mlxsw_##_type##_##_cname##_##_iname##_set(char *buf, u16 val)\ val 320 drivers/net/ethernet/mellanox/mlxsw/item.h __mlxsw_item_set16(buf, &__ITEM_NAME(_type, _cname, _iname), 0, val); \ val 342 drivers/net/ethernet/mellanox/mlxsw/item.h u16 val) \ val 345 drivers/net/ethernet/mellanox/mlxsw/item.h index, val); \ val 359 drivers/net/ethernet/mellanox/mlxsw/item.h static inline void mlxsw_##_type##_##_cname##_##_iname##_set(char *buf, u32 val)\ val 361 drivers/net/ethernet/mellanox/mlxsw/item.h __mlxsw_item_set32(buf, &__ITEM_NAME(_type, _cname, _iname), 0, val); \ val 383 drivers/net/ethernet/mellanox/mlxsw/item.h u32 val) \ val 386 drivers/net/ethernet/mellanox/mlxsw/item.h index, val); \ val 400 drivers/net/ethernet/mellanox/mlxsw/item.h static inline void mlxsw_##_type##_##_cname##_##_iname##_set(char *buf, u64 val)\ val 402 drivers/net/ethernet/mellanox/mlxsw/item.h __mlxsw_item_set64(buf, &__ITEM_NAME(_type, _cname, _iname), 0, val); \ val 424 drivers/net/ethernet/mellanox/mlxsw/item.h u64 val) \ val 427 drivers/net/ethernet/mellanox/mlxsw/item.h index, val); \ val 502 drivers/net/ethernet/mellanox/mlxsw/item.h mlxsw_##_type##_##_cname##_##_iname##_set(char *buf, u16 index, u8 val) \ val 506 drivers/net/ethernet/mellanox/mlxsw/item.h index, val); \ val 25 drivers/net/ethernet/mellanox/mlxsw/pci.c #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ val 26 drivers/net/ethernet/mellanox/mlxsw/pci.c iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) val 237 drivers/net/ethernet/mellanox/mlxsw/pci.c u16 val) val 242 drivers/net/ethernet/mellanox/mlxsw/pci.c q->num), val); val 247 drivers/net/ethernet/mellanox/mlxsw/pci.c u16 val) val 252 drivers/net/ethernet/mellanox/mlxsw/pci.c q->num), val); val 1326 drivers/net/ethernet/mellanox/mlxsw/pci.c u32 val; val 1338 drivers/net/ethernet/mellanox/mlxsw/pci.c val = mlxsw_pci_read32(mlxsw_pci, FW_READY); val 1339 drivers/net/ethernet/mellanox/mlxsw/pci.c if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC) val 1344 drivers/net/ethernet/mellanox/mlxsw/pci.c *p_sys_status = val & MLXSW_PCI_FW_READY_MASK; val 124 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h char *cqe, u32 val) \ val 129 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \ val 132 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \ val 135 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \ val 8195 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ val 5257 drivers/net/ethernet/mellanox/mlxsw/spectrum.c union devlink_param_value val, val 5260 drivers/net/ethernet/mellanox/mlxsw/spectrum.c if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) && val 5261 drivers/net/ethernet/mellanox/mlxsw/spectrum.c (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) { val 5308 drivers/net/ethernet/mellanox/mlxsw/spectrum.c ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp); val 5319 drivers/net/ethernet/mellanox/mlxsw/spectrum.c return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32); val 765 drivers/net/ethernet/mellanox/mlxsw/spectrum.h int mlxsw_sp_acl_region_rehash_intrvl_set(struct mlxsw_sp *mlxsw_sp, u32 val); val 934 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c int mlxsw_sp_acl_region_rehash_intrvl_set(struct mlxsw_sp *mlxsw_sp, u32 val) val 939 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c &acl->tcam, val); val 891 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c u32 val) val 896 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c if (val < MLXSW_SP_ACL_TCAM_VREGION_REHASH_INTRVL_MIN && val) val 900 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c tcam->vregion_rehash_intrvl = val; val 903 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c if (val) val 36 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.h u32 val); val 1054 drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c int val; val 1056 drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c val = threshold + MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET; val 1057 drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c if (val < MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN || val 1058 drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c val > MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX) { val 1062 drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c *p_max_buff = val; val 2918 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c unsigned int val; val 2926 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c val = nh_grp->count; val 2929 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c val ^= jhash(&nh->ifindex, sizeof(nh->ifindex), seed); val 2931 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c return jhash(&val, sizeof(val), seed); val 2941 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c unsigned int val = fib6_entry->nrt6; val 2947 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c val ^= jhash(&dev->ifindex, sizeof(dev->ifindex), seed); val 2950 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c return jhash(&val, sizeof(val), seed); val 169 drivers/net/ethernet/micrel/ks8851.c static void ks8851_wrreg16(struct ks8851_net *ks, unsigned reg, unsigned val) val 177 drivers/net/ethernet/micrel/ks8851.c txb[1] = cpu_to_le16(val); val 196 drivers/net/ethernet/micrel/ks8851.c static void ks8851_wrreg8(struct ks8851_net *ks, unsigned reg, unsigned val) val 207 drivers/net/ethernet/micrel/ks8851.c txb[1] = val; val 1128 drivers/net/ethernet/micrel/ks8851.c unsigned val; val 1130 drivers/net/ethernet/micrel/ks8851.c val = ks8851_rdreg16(ks, KS_EEPCR); val 1132 drivers/net/ethernet/micrel/ks8851.c ee->reg_data_out = (val & EEPCR_EESB) ? 1 : 0; val 1133 drivers/net/ethernet/micrel/ks8851.c ee->reg_data_clock = (val & EEPCR_EESCK) ? 1 : 0; val 1134 drivers/net/ethernet/micrel/ks8851.c ee->reg_chip_select = (val & EEPCR_EECS) ? 1 : 0; val 1140 drivers/net/ethernet/micrel/ks8851.c unsigned val = EEPCR_EESA; /* default - eeprom access on */ val 1143 drivers/net/ethernet/micrel/ks8851.c val |= EEPCR_EESRWA; val 1145 drivers/net/ethernet/micrel/ks8851.c val |= EEPCR_EEDO; val 1147 drivers/net/ethernet/micrel/ks8851.c val |= EEPCR_EESCK; val 1149 drivers/net/ethernet/micrel/ks8851.c val |= EEPCR_EECS; val 1151 drivers/net/ethernet/micrel/ks8851.c ks8851_wrreg16(ks, KS_EEPCR, val); val 1181 drivers/net/ethernet/micrel/ks8851.c unsigned val = ks8851_rdreg16(ks, KS_EEPCR); val 1183 drivers/net/ethernet/micrel/ks8851.c ks8851_wrreg16(ks, KS_EEPCR, val & ~EEPCR_EESA); val 2965 drivers/net/ethernet/micrel/ksz884x.c static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val) val 2970 drivers/net/ethernet/micrel/ksz884x.c *val = readw(hw->io + phy); val 2982 drivers/net/ethernet/micrel/ksz884x.c static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val) val 2987 drivers/net/ethernet/micrel/ksz884x.c writew(val, hw->io + phy); val 3563 drivers/net/ethernet/micrel/ksz884x.c u8 val = 0; val 3577 drivers/net/ethernet/micrel/ksz884x.c if ((val & 1)) val 3579 drivers/net/ethernet/micrel/ksz884x.c val >>= 1; val 3583 drivers/net/ethernet/micrel/ksz884x.c val = mask[len]; val 3584 drivers/net/ethernet/micrel/ksz884x.c writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i val 3587 drivers/net/ethernet/micrel/ksz884x.c if (val) val 3593 drivers/net/ethernet/micrel/ksz884x.c if (val) { val 3595 drivers/net/ethernet/micrel/ksz884x.c val <<= (from % 8); val 3596 drivers/net/ethernet/micrel/ksz884x.c bits &= ~val; val 5906 drivers/net/ethernet/micrel/ksz884x.c static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) val 5915 drivers/net/ethernet/micrel/ksz884x.c hw_w_phy(hw, pi, reg_num << 1, val); val 148 drivers/net/ethernet/microchip/enc28j60.c u8 val = 0; val 162 drivers/net/ethernet/microchip/enc28j60.c val = rx_buf[slen - 1]; val 164 drivers/net/ethernet/microchip/enc28j60.c return val; val 170 drivers/net/ethernet/microchip/enc28j60.c static int spi_write_op(struct enc28j60_net *priv, u8 op, u8 addr, u8 val) val 176 drivers/net/ethernet/microchip/enc28j60.c priv->spi_transfer_buf[1] = val; val 410 drivers/net/ethernet/microchip/enc28j60.c static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val) val 416 drivers/net/ethernet/microchip/enc28j60.c while ((nolock_regb_read(priv, reg) & mask) != val) { val 1509 drivers/net/ethernet/microchip/enc28j60.c static void enc28j60_set_msglevel(struct net_device *dev, u32 val) val 1512 drivers/net/ethernet/microchip/enc28j60.c priv->msg_enable = val; val 65 drivers/net/ethernet/microchip/encx24j600-regmap.c static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, val 111 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = spi_write_then_read(ctx->spi, tx_buf, i, val, len); val 117 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 reg, u8 *val, size_t len, val 126 drivers/net/ethernet/microchip/encx24j600-regmap.c { .tx_buf = val, .len = len }, }; val 173 drivers/net/ethernet/microchip/encx24j600-regmap.c static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val, val 178 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE); val 182 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 reg, u8 val) val 184 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE); val 188 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 reg, u8 val) val 190 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE); val 195 drivers/net/ethernet/microchip/encx24j600-regmap.c unsigned int val) val 200 drivers/net/ethernet/microchip/encx24j600-regmap.c unsigned int set_mask = mask & val; val 201 drivers/net/ethernet/microchip/encx24j600-regmap.c unsigned int clr_mask = mask & ~val; val 268 drivers/net/ethernet/microchip/encx24j600-regmap.c void *val, size_t val_size) val 278 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_spi_read(context, reg, val, val_size); val 285 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_read(context, reg, val, val_size); val 351 drivers/net/ethernet/microchip/encx24j600-regmap.c unsigned int *val) val 378 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = regmap_read(ctx->regmap, MIRD, val); val 389 drivers/net/ethernet/microchip/encx24j600-regmap.c unsigned int val) val 400 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = regmap_write(ctx->regmap, MIWR, val); val 412 drivers/net/ethernet/microchip/encx24j600-regmap.c reg & PHREG_MASK, val); val 101 drivers/net/ethernet/microchip/encx24j600.c unsigned int val = 0; val 102 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_read(priv->ctx.regmap, reg, &val); val 107 drivers/net/ethernet/microchip/encx24j600.c return val; val 110 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val) val 113 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_write(priv->ctx.regmap, reg, val); val 117 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg, val); val 121 drivers/net/ethernet/microchip/encx24j600.c u16 mask, u16 val) val 124 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val); val 128 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg, val, mask); val 134 drivers/net/ethernet/microchip/encx24j600.c unsigned int val = 0; val 135 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_read(priv->ctx.phymap, reg, &val); val 140 drivers/net/ethernet/microchip/encx24j600.c return val; val 143 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val) val 146 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_write(priv->ctx.phymap, reg, val); val 150 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg, val); val 713 drivers/net/ethernet/microchip/encx24j600.c unsigned short val; val 715 drivers/net/ethernet/microchip/encx24j600.c val = encx24j600_read_reg(priv, MAADR1); val 717 drivers/net/ethernet/microchip/encx24j600.c ethaddr[0] = val & 0x00ff; val 718 drivers/net/ethernet/microchip/encx24j600.c ethaddr[1] = (val & 0xff00) >> 8; val 720 drivers/net/ethernet/microchip/encx24j600.c val = encx24j600_read_reg(priv, MAADR2); val 722 drivers/net/ethernet/microchip/encx24j600.c ethaddr[2] = val & 0x00ffU; val 723 drivers/net/ethernet/microchip/encx24j600.c ethaddr[3] = (val & 0xff00U) >> 8; val 725 drivers/net/ethernet/microchip/encx24j600.c val = encx24j600_read_reg(priv, MAADR3); val 727 drivers/net/ethernet/microchip/encx24j600.c ethaddr[4] = val & 0x00ffU; val 728 drivers/net/ethernet/microchip/encx24j600.c ethaddr[5] = (val & 0xff00U) >> 8; val 921 drivers/net/ethernet/microchip/encx24j600.c unsigned int val = 0; val 923 drivers/net/ethernet/microchip/encx24j600.c regmap_read(priv->ctx.regmap, reg, &val); val 924 drivers/net/ethernet/microchip/encx24j600.c buff[reg] = val & 0xffff; val 974 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_set_msglevel(struct net_device *dev, u32 val) val 978 drivers/net/ethernet/microchip/encx24j600.c priv->msg_enable = val; val 155 drivers/net/ethernet/microchip/lan743x_ethtool.c u32 val; val 158 drivers/net/ethernet/microchip/lan743x_ethtool.c val = lan743x_csr_read(adapter, E2P_CMD); val 160 drivers/net/ethernet/microchip/lan743x_ethtool.c if (!(val & E2P_CMD_EPC_BUSY_) || val 161 drivers/net/ethernet/microchip/lan743x_ethtool.c (val & E2P_CMD_EPC_TIMEOUT_)) val 166 drivers/net/ethernet/microchip/lan743x_ethtool.c if (val & (E2P_CMD_EPC_TIMEOUT_ | E2P_CMD_EPC_BUSY_)) { val 178 drivers/net/ethernet/microchip/lan743x_ethtool.c u32 val; val 181 drivers/net/ethernet/microchip/lan743x_ethtool.c val = lan743x_csr_read(adapter, E2P_CMD); val 183 drivers/net/ethernet/microchip/lan743x_ethtool.c if (!(val & E2P_CMD_EPC_BUSY_)) val 197 drivers/net/ethernet/microchip/lan743x_ethtool.c u32 val; val 208 drivers/net/ethernet/microchip/lan743x_ethtool.c val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_; val 209 drivers/net/ethernet/microchip/lan743x_ethtool.c val |= (offset & E2P_CMD_EPC_ADDR_MASK_); val 210 drivers/net/ethernet/microchip/lan743x_ethtool.c lan743x_csr_write(adapter, E2P_CMD, val); val 216 drivers/net/ethernet/microchip/lan743x_ethtool.c val = lan743x_csr_read(adapter, E2P_DATA); val 217 drivers/net/ethernet/microchip/lan743x_ethtool.c data[i] = val & 0xFF; val 228 drivers/net/ethernet/microchip/lan743x_ethtool.c u32 val; val 239 drivers/net/ethernet/microchip/lan743x_ethtool.c val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_; val 240 drivers/net/ethernet/microchip/lan743x_ethtool.c lan743x_csr_write(adapter, E2P_CMD, val); val 248 drivers/net/ethernet/microchip/lan743x_ethtool.c val = data[i]; val 249 drivers/net/ethernet/microchip/lan743x_ethtool.c lan743x_csr_write(adapter, E2P_DATA, val); val 252 drivers/net/ethernet/microchip/lan743x_ethtool.c val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_; val 253 drivers/net/ethernet/microchip/lan743x_ethtool.c val |= (offset & E2P_CMD_EPC_ADDR_MASK_); val 254 drivers/net/ethernet/microchip/lan743x_ethtool.c lan743x_csr_write(adapter, E2P_CMD, val); val 732 drivers/net/ethernet/microchip/lan743x_main.c u32 val, mii_access; val 747 drivers/net/ethernet/microchip/lan743x_main.c val = lan743x_csr_read(adapter, MAC_MII_DATA); val 748 drivers/net/ethernet/microchip/lan743x_main.c return (int)(val & 0xFFFF); val 755 drivers/net/ethernet/microchip/lan743x_main.c u32 val, mii_access; val 762 drivers/net/ethernet/microchip/lan743x_main.c val = (u32)regval; val 763 drivers/net/ethernet/microchip/lan743x_main.c lan743x_csr_write(adapter, MAC_MII_DATA, val); val 329 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ val 330 drivers/net/ethernet/microchip/lan743x_main.h ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) val 338 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ val 339 drivers/net/ethernet/microchip/lan743x_main.h ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) val 345 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ val 346 drivers/net/ethernet/microchip/lan743x_main.h ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) val 348 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ val 349 drivers/net/ethernet/microchip/lan743x_main.h (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) val 353 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_OBFF_TX_THRES_SET_(val) \ val 354 drivers/net/ethernet/microchip/lan743x_main.h ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) val 356 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_OBFF_RX_THRES_SET_(val) \ val 357 drivers/net/ethernet/microchip/lan743x_main.h (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) val 377 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_A_RX_WB_THRES_SET_(val) \ val 378 drivers/net/ethernet/microchip/lan743x_main.h ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) val 380 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_A_RX_PF_THRES_SET_(val) \ val 381 drivers/net/ethernet/microchip/lan743x_main.h ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) val 383 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ val 384 drivers/net/ethernet/microchip/lan743x_main.h ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) val 57 drivers/net/ethernet/mscc/ocelot.c u32 val; val 60 drivers/net/ethernet/mscc/ocelot.c ocelot, val, val 61 drivers/net/ethernet/mscc/ocelot.c (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == val 149 drivers/net/ethernet/mscc/ocelot.c u32 val; val 153 drivers/net/ethernet/mscc/ocelot.c val, val 154 drivers/net/ethernet/mscc/ocelot.c (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == val 177 drivers/net/ethernet/mscc/ocelot.c u32 val; val 180 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read(ocelot, ANA_VLANMASK); val 182 drivers/net/ethernet/mscc/ocelot.c val |= BIT(p); val 184 drivers/net/ethernet/mscc/ocelot.c val &= ~BIT(p); val 185 drivers/net/ethernet/mscc/ocelot.c ocelot_write(ocelot, val, ANA_VLANMASK); val 191 drivers/net/ethernet/mscc/ocelot.c u32 val; val 195 drivers/net/ethernet/mscc/ocelot.c val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid); val 197 drivers/net/ethernet/mscc/ocelot.c val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | val 200 drivers/net/ethernet/mscc/ocelot.c ocelot_rmw_gix(ocelot, val, val 207 drivers/net/ethernet/mscc/ocelot.c val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA; val 212 drivers/net/ethernet/mscc/ocelot.c val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | val 215 drivers/net/ethernet/mscc/ocelot.c ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port); val 218 drivers/net/ethernet/mscc/ocelot.c val = REW_TAG_CFG_TAG_TPID_CFG(0); val 223 drivers/net/ethernet/mscc/ocelot.c val |= REW_TAG_CFG_TAG_CFG(1); val 226 drivers/net/ethernet/mscc/ocelot.c val |= REW_TAG_CFG_TAG_CFG(3); val 228 drivers/net/ethernet/mscc/ocelot.c ocelot_rmw_gix(ocelot, val, val 234 drivers/net/ethernet/mscc/ocelot.c val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) | val 236 drivers/net/ethernet/mscc/ocelot.c ocelot_rmw_gix(ocelot, val, val 562 drivers/net/ethernet/mscc/ocelot.c u32 val, ifh[IFH_LEN]; val 567 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read(ocelot, QS_INJ_STATUS); val 568 drivers/net/ethernet/mscc/ocelot.c if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || val 569 drivers/net/ethernet/mscc/ocelot.c (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) val 644 drivers/net/ethernet/mscc/ocelot.c u32 val; val 649 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); val 651 drivers/net/ethernet/mscc/ocelot.c val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); val 652 drivers/net/ethernet/mscc/ocelot.c val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); val 653 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); val 657 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); val 658 drivers/net/ethernet/mscc/ocelot.c ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); val 661 drivers/net/ethernet/mscc/ocelot.c if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) val 688 drivers/net/ethernet/mscc/ocelot.c u32 val; val 694 drivers/net/ethernet/mscc/ocelot.c val = GENMASK(ocelot->num_phys_ports - 1, 0); val 696 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); val 858 drivers/net/ethernet/mscc/ocelot.c u32 val, dst, macl, mach; val 873 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); val 874 drivers/net/ethernet/mscc/ocelot.c if (!(val & ANA_TABLES_MACACCESS_VALID)) val 880 drivers/net/ethernet/mscc/ocelot.c dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; val 1119 drivers/net/ethernet/mscc/ocelot.c u32 val; val 1122 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, val 1125 drivers/net/ethernet/mscc/ocelot.c if (val < (ocelot->stats[idx] & U32_MAX)) val 1129 drivers/net/ethernet/mscc/ocelot.c ~(u64)U32_MAX) + val; val 1289 drivers/net/ethernet/mscc/ocelot.c u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, val 1293 drivers/net/ethernet/mscc/ocelot.c val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | val 1297 drivers/net/ethernet/mscc/ocelot.c val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | val 1301 drivers/net/ethernet/mscc/ocelot.c ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); val 1819 drivers/net/ethernet/mscc/ocelot.c u32 val; val 1824 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); val 1825 drivers/net/ethernet/mscc/ocelot.c val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); val 1826 drivers/net/ethernet/mscc/ocelot.c val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); val 1827 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); val 1853 drivers/net/ethernet/mscc/ocelot.c u32 val; val 1857 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); val 1858 drivers/net/ethernet/mscc/ocelot.c val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); val 1859 drivers/net/ethernet/mscc/ocelot.c val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); val 1861 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); val 1869 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); val 1870 drivers/net/ethernet/mscc/ocelot.c val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); val 1871 drivers/net/ethernet/mscc/ocelot.c val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD); val 1873 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); val 1884 drivers/net/ethernet/mscc/ocelot.c u32 val; val 1888 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); val 1889 drivers/net/ethernet/mscc/ocelot.c val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); val 1890 drivers/net/ethernet/mscc/ocelot.c val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); val 1892 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); val 1898 drivers/net/ethernet/mscc/ocelot.c val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); val 1899 drivers/net/ethernet/mscc/ocelot.c val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); val 1900 drivers/net/ethernet/mscc/ocelot.c val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA); val 1902 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); val 2154 drivers/net/ethernet/mscc/ocelot.c u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); val 2156 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); val 520 drivers/net/ethernet/mscc/ocelot.h void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); val 521 drivers/net/ethernet/mscc/ocelot.h #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) val 522 drivers/net/ethernet/mscc/ocelot.h #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) val 523 drivers/net/ethernet/mscc/ocelot.h #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) val 524 drivers/net/ethernet/mscc/ocelot.h #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) val 526 drivers/net/ethernet/mscc/ocelot.h void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, val 528 drivers/net/ethernet/mscc/ocelot.h #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) val 529 drivers/net/ethernet/mscc/ocelot.h #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) val 530 drivers/net/ethernet/mscc/ocelot.h #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) val 531 drivers/net/ethernet/mscc/ocelot.h #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) val 534 drivers/net/ethernet/mscc/ocelot.h void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); val 542 drivers/net/ethernet/mscc/ocelot.h #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) val 543 drivers/net/ethernet/mscc/ocelot.h #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) val 252 drivers/net/ethernet/mscc/ocelot_ace.c static void vcap_key_bytes_set(struct vcap_data *data, u32 offset, u8 *val, val 263 drivers/net/ethernet/mscc/ocelot_ace.c value += (val[j] << n); val 283 drivers/net/ethernet/mscc/ocelot_ace.c enum ocelot_vcap_bit val) val 285 drivers/net/ethernet/mscc/ocelot_ace.c vcap_key_set(data, offset, 1, val == OCELOT_VCAP_BIT_1 ? 1 : 0, val 286 drivers/net/ethernet/mscc/ocelot_ace.c val == OCELOT_VCAP_BIT_ANY ? 0 : 1); val 289 drivers/net/ethernet/mscc/ocelot_ace.c #define VCAP_KEY_SET(fld, val, msk) \ val 290 drivers/net/ethernet/mscc/ocelot_ace.c vcap_key_set(&data, IS2_HKO_##fld, IS2_HKL_##fld, val, msk) val 293 drivers/net/ethernet/mscc/ocelot_ace.c #define VCAP_KEY_BIT_SET(fld, val) vcap_key_bit_set(&data, IS2_HKO_##fld, val) val 294 drivers/net/ethernet/mscc/ocelot_ace.c #define VCAP_KEY_BYTES_SET(fld, val, msk) \ val 295 drivers/net/ethernet/mscc/ocelot_ace.c vcap_key_bytes_set(&data, IS2_HKO_##fld, val, msk, IS2_HKL_##fld / 8) val 303 drivers/net/ethernet/mscc/ocelot_ace.c #define VCAP_ACT_SET(fld, val) \ val 304 drivers/net/ethernet/mscc/ocelot_ace.c vcap_action_set(data, IS2_AO_##fld, IS2_AL_##fld, val) val 332 drivers/net/ethernet/mscc/ocelot_ace.c u32 val, msk, type, type_mask = 0xf, i, count; val 419 drivers/net/ethernet/mscc/ocelot_ace.c val = ((arp->req == OCELOT_VCAP_BIT_0 ? 1 : 0) | val 423 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_SET(MAC_ARP_ARP_OPCODE, val, msk); val 473 drivers/net/ethernet/mscc/ocelot_ace.c val = ipv6->sip.value[i + 8]; val 476 drivers/net/ethernet/mscc/ocelot_ace.c dip.value.addr[i] = val; val 479 drivers/net/ethernet/mscc/ocelot_ace.c sip.value.addr[i - 4] = val; val 508 drivers/net/ethernet/mscc/ocelot_ace.c val = proto.value[0]; val 511 drivers/net/ethernet/mscc/ocelot_ace.c if (msk == 0xff && (val == 6 || val == 17)) { val 513 drivers/net/ethernet/mscc/ocelot_ace.c tcp = (val == 6 ? val 47 drivers/net/ethernet/mscc/ocelot_board.c u32 val; val 50 drivers/net/ethernet/mscc/ocelot_board.c val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); val 51 drivers/net/ethernet/mscc/ocelot_board.c if (val == XTR_NOT_READY) { val 56 drivers/net/ethernet/mscc/ocelot_board.c val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); val 57 drivers/net/ethernet/mscc/ocelot_board.c } while (val == XTR_NOT_READY); val 60 drivers/net/ethernet/mscc/ocelot_board.c switch (val) { val 68 drivers/net/ethernet/mscc/ocelot_board.c bytes_valid = XTR_VALID_BYTES(val); val 69 drivers/net/ethernet/mscc/ocelot_board.c val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); val 70 drivers/net/ethernet/mscc/ocelot_board.c if (val == XTR_ESCAPE) val 73 drivers/net/ethernet/mscc/ocelot_board.c *rval = val; val 81 drivers/net/ethernet/mscc/ocelot_board.c *rval = val; val 101 drivers/net/ethernet/mscc/ocelot_board.c u32 ifh[4], val, *buf; val 139 drivers/net/ethernet/mscc/ocelot_board.c sz = ocelot_rx_frame_word(ocelot, grp, false, &val); val 140 drivers/net/ethernet/mscc/ocelot_board.c *buf++ = val; val 145 drivers/net/ethernet/mscc/ocelot_board.c sz = ocelot_rx_frame_word(ocelot, grp, false, &val); val 151 drivers/net/ethernet/mscc/ocelot_board.c *buf = val; val 206 drivers/net/ethernet/mscc/ocelot_board.c u32 val, id, txport; val 208 drivers/net/ethernet/mscc/ocelot_board.c val = ocelot_read(ocelot, SYS_PTP_STATUS); val 211 drivers/net/ethernet/mscc/ocelot_board.c if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) val 214 drivers/net/ethernet/mscc/ocelot_board.c WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); val 217 drivers/net/ethernet/mscc/ocelot_board.c id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); val 218 drivers/net/ethernet/mscc/ocelot_board.c txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); val 268 drivers/net/ethernet/mscc/ocelot_board.c u32 val; val 351 drivers/net/ethernet/mscc/ocelot_board.c &val); val 352 drivers/net/ethernet/mscc/ocelot_board.c } while (val); val 16 drivers/net/ethernet/mscc/ocelot_io.c u32 val; val 21 drivers/net/ethernet/mscc/ocelot_io.c ocelot->map[target][reg & REG_MASK] + offset, &val); val 22 drivers/net/ethernet/mscc/ocelot_io.c return val; val 26 drivers/net/ethernet/mscc/ocelot_io.c void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset) val 33 drivers/net/ethernet/mscc/ocelot_io.c ocelot->map[target][reg & REG_MASK] + offset, val); val 37 drivers/net/ethernet/mscc/ocelot_io.c void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, val 46 drivers/net/ethernet/mscc/ocelot_io.c mask, val); val 56 drivers/net/ethernet/mscc/ocelot_io.c void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg) val 58 drivers/net/ethernet/mscc/ocelot_io.c writel(val, port->regs + reg); val 360 drivers/net/ethernet/myricom/myri10ge/myri10ge.c static inline void put_be32(__be32 val, __be32 __iomem * p) val 362 drivers/net/ethernet/myricom/myri10ge/myri10ge.c __raw_writel((__force __u32) val, (__force void __iomem *)p); val 58 drivers/net/ethernet/natsemi/jazzsonic.c #define SONIC_WRITE(reg,val) \ val 60 drivers/net/ethernet/natsemi/jazzsonic.c *((volatile unsigned int *)dev->base_addr+(reg)) = (val); \ val 113 drivers/net/ethernet/natsemi/jazzsonic.c unsigned int val; val 145 drivers/net/ethernet/natsemi/jazzsonic.c val = SONIC_READ(SONIC_CAP0-i); val 146 drivers/net/ethernet/natsemi/jazzsonic.c dev->dev_addr[i*2] = val; val 147 drivers/net/ethernet/natsemi/jazzsonic.c dev->dev_addr[i*2+1] = val >> 8; val 70 drivers/net/ethernet/natsemi/macsonic.c #define SONIC_WRITE(reg,val) (nubus_writew(val, dev->base_addr + (reg * 4) \ val 239 drivers/net/ethernet/natsemi/macsonic.c unsigned short val; val 279 drivers/net/ethernet/natsemi/macsonic.c val = SONIC_READ(SONIC_CAP2); val 280 drivers/net/ethernet/natsemi/macsonic.c dev->dev_addr[5] = val >> 8; val 281 drivers/net/ethernet/natsemi/macsonic.c dev->dev_addr[4] = val & 0xff; val 282 drivers/net/ethernet/natsemi/macsonic.c val = SONIC_READ(SONIC_CAP1); val 283 drivers/net/ethernet/natsemi/macsonic.c dev->dev_addr[3] = val >> 8; val 284 drivers/net/ethernet/natsemi/macsonic.c dev->dev_addr[2] = val & 0xff; val 285 drivers/net/ethernet/natsemi/macsonic.c val = SONIC_READ(SONIC_CAP0); val 286 drivers/net/ethernet/natsemi/macsonic.c dev->dev_addr[1] = val >> 8; val 287 drivers/net/ethernet/natsemi/macsonic.c dev->dev_addr[0] = val & 0xff; val 2643 drivers/net/ethernet/natsemi/natsemi.c static void set_msglevel(struct net_device *dev, u32 val) val 2646 drivers/net/ethernet/natsemi/natsemi.c np->msg_enable = val; val 1676 drivers/net/ethernet/natsemi/ns83820.c u32 val; val 1689 drivers/net/ethernet/natsemi/ns83820.c val = (readl(rfcr) & and_mask) | or_mask; val 1691 drivers/net/ethernet/natsemi/ns83820.c writel(val & ~RFCR_RFEN, rfcr); val 1692 drivers/net/ethernet/natsemi/ns83820.c writel(val, rfcr); val 352 drivers/net/ethernet/natsemi/sonic.h int offset, __u16 val) val 356 drivers/net/ethernet/natsemi/sonic.h __raw_writew(val, base + (offset * 2) + 1); val 358 drivers/net/ethernet/natsemi/sonic.h __raw_writew(val, base + (offset * 2) + 0); val 361 drivers/net/ethernet/natsemi/sonic.h __raw_writew(val, base + (offset * 1) + 0); val 379 drivers/net/ethernet/natsemi/sonic.h int offset, __u16 val) val 383 drivers/net/ethernet/natsemi/sonic.h (entry * SIZEOF_SONIC_CD) + offset, val); val 394 drivers/net/ethernet/natsemi/sonic.h static inline void sonic_set_cam_enable(struct net_device* dev, __u16 val) val 397 drivers/net/ethernet/natsemi/sonic.h sonic_buf_put(lp->cda, lp->dma_bitmode, SONIC_CDA_CAM_ENABLE, val); val 407 drivers/net/ethernet/natsemi/sonic.h int offset, __u16 val) val 411 drivers/net/ethernet/natsemi/sonic.h (entry * SIZEOF_SONIC_TD) + offset, val); val 423 drivers/net/ethernet/natsemi/sonic.h int offset, __u16 val) val 427 drivers/net/ethernet/natsemi/sonic.h (entry * SIZEOF_SONIC_RD) + offset, val); val 439 drivers/net/ethernet/natsemi/sonic.h int offset, __u16 val) val 443 drivers/net/ethernet/natsemi/sonic.h (entry * SIZEOF_SONIC_RR) + offset, val); val 73 drivers/net/ethernet/natsemi/xtsonic.c #define SONIC_WRITE(reg,val) \ val 74 drivers/net/ethernet/natsemi/xtsonic.c *((volatile unsigned int *)dev->base_addr+reg) = val val 165 drivers/net/ethernet/natsemi/xtsonic.c unsigned int val = SONIC_READ(SONIC_CAP0-i); val 166 drivers/net/ethernet/natsemi/xtsonic.c dev->dev_addr[i*2] = val; val 167 drivers/net/ethernet/natsemi/xtsonic.c dev->dev_addr[i*2+1] = val >> 8; val 77 drivers/net/ethernet/neterion/s2io-regs.h #define ADAPTER_UDPI(val) vBIT(val,36,4) val 96 drivers/net/ethernet/neterion/s2io-regs.h #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60) val 224 drivers/net/ethernet/neterion/s2io-regs.h #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) val 228 drivers/net/ethernet/neterion/s2io-regs.h #define TXREQTO_VAL(val) vBIT(val,0,32) val 266 drivers/net/ethernet/neterion/s2io-regs.h #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32) val 272 drivers/net/ethernet/neterion/s2io-regs.h #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16) val 273 drivers/net/ethernet/neterion/s2io-regs.h #define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5) val 274 drivers/net/ethernet/neterion/s2io-regs.h #define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5) val 275 drivers/net/ethernet/neterion/s2io-regs.h #define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4) val 276 drivers/net/ethernet/neterion/s2io-regs.h #define MDIO_OP(val) vBIT(val, 60, 2) val 281 drivers/net/ethernet/neterion/s2io-regs.h #define MDIO_MDIO_DATA(val) vBIT(val, 32, 16) val 292 drivers/net/ethernet/neterion/s2io-regs.h #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) val 293 drivers/net/ethernet/neterion/s2io-regs.h #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) val 294 drivers/net/ethernet/neterion/s2io-regs.h #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) val 301 drivers/net/ethernet/neterion/s2io-regs.h #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) val 309 drivers/net/ethernet/neterion/s2io-regs.h #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12) val 397 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) val 398 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) val 399 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) val 400 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) val 403 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) val 404 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) val 405 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) val 406 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) val 409 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) val 410 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) val 411 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) val 412 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) val 415 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) val 416 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) val 417 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) val 418 drivers/net/ethernet/neterion/s2io-regs.h #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) val 535 drivers/net/ethernet/neterion/s2io-regs.h #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) val 536 drivers/net/ethernet/neterion/s2io-regs.h #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) val 537 drivers/net/ethernet/neterion/s2io-regs.h #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) val 538 drivers/net/ethernet/neterion/s2io-regs.h #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) val 539 drivers/net/ethernet/neterion/s2io-regs.h #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) val 540 drivers/net/ethernet/neterion/s2io-regs.h #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) val 541 drivers/net/ethernet/neterion/s2io-regs.h #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) val 542 drivers/net/ethernet/neterion/s2io-regs.h #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) val 578 drivers/net/ethernet/neterion/s2io-regs.h #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) val 698 drivers/net/ethernet/neterion/s2io-regs.h #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) val 701 drivers/net/ethernet/neterion/s2io-regs.h #define TMAC_AVG_IPG(val) vBIT(val,0,8) val 704 drivers/net/ethernet/neterion/s2io-regs.h #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) val 719 drivers/net/ethernet/neterion/s2io-regs.h #define RMAC_CFG_KEY(val) vBIT(val,0,16) val 763 drivers/net/ethernet/neterion/s2io-regs.h #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) val 791 drivers/net/ethernet/neterion/s2io-regs.h #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) val 792 drivers/net/ethernet/neterion/s2io-regs.h #define RTS_DIX_MAP_SCW(val) s2BIT(val,21) val 808 drivers/net/ethernet/neterion/s2io-regs.h #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) val 809 drivers/net/ethernet/neterion/s2io-regs.h #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) val 897 drivers/net/ethernet/neterion/s2io-regs.h #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16) val 19 drivers/net/ethernet/neterion/s2io.h #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) val 483 drivers/net/ethernet/neterion/s2io.h #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) val 498 drivers/net/ethernet/neterion/s2io.h #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE)) val 499 drivers/net/ethernet/neterion/s2io.h #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12) val 506 drivers/net/ethernet/neterion/s2io.h #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14) val 507 drivers/net/ethernet/neterion/s2io.h #define TXD_UFO_MSS(val) vBIT(val,34,14) val 508 drivers/net/ethernet/neterion/s2io.h #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16) val 516 drivers/net/ethernet/neterion/s2io.h #define TXD_VLAN_TAG(val) vBIT(val,16,16) val 517 drivers/net/ethernet/neterion/s2io.h #define TXD_INT_NUMBER(val) vBIT(val,34,6) val 546 drivers/net/ethernet/neterion/s2io.h #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF) val 547 drivers/net/ethernet/neterion/s2io.h #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) val 555 drivers/net/ethernet/neterion/s2io.h #define SET_VLAN_TAG(val) vBIT(val,48,16) val 556 drivers/net/ethernet/neterion/s2io.h #define SET_NUM_TAG(val) vBIT(val,16,32) val 565 drivers/net/ethernet/neterion/s2io.h #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) val 578 drivers/net/ethernet/neterion/s2io.h #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8) val 579 drivers/net/ethernet/neterion/s2io.h #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16) val 580 drivers/net/ethernet/neterion/s2io.h #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16) val 982 drivers/net/ethernet/neterion/s2io.h static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) val 985 drivers/net/ethernet/neterion/s2io.h writel((u32) (val), addr); val 987 drivers/net/ethernet/neterion/s2io.h writel((u32) (val >> 32), (addr + 4)); val 990 drivers/net/ethernet/neterion/s2io.h writel((u32) (val >> 32), (addr + 4)); val 992 drivers/net/ethernet/neterion/s2io.h writel((u32) (val), addr); val 3566 drivers/net/ethernet/neterion/vxge/vxge-config.c u32 phy_func_0, u32 offset, u32 *val) val 3594 drivers/net/ethernet/neterion/vxge/vxge-config.c *val = 0; val 3596 drivers/net/ethernet/neterion/vxge/vxge-config.c *val = (u32)vxge_bVALn(val64, 32, 32); val 1114 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_NODBW_TYPE(val) vxge_vBIT(val, 0, 8) val 1118 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_NODBW_LAST_TXD_NUMBER(val) vxge_vBIT(val, 32, 8) val 1121 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_NODBW_LIST_NO_SNOOP(val) vxge_vBIT(val, 56, 8) val 1264 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_FIFO_TXD_T_CODE(val) vxge_vBIT(val, 12, 4) val 1268 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_FIFO_TXD_GATHER_CODE(val) vxge_vBIT(val, 22, 2) val 1275 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_FIFO_TXD_LSO_MSS(val) vxge_vBIT(val, 34, 14) val 1277 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val) vxge_vBIT(val, 48, 16) val 1285 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_FIFO_TXD_VLAN_TAG(val) vxge_vBIT(val, 16, 16) val 1287 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_FIFO_TXD_INT_NUMBER(val) vxge_vBIT(val, 34, 6) val 1399 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_T_CODE(val) vxge_vBIT(val, 12, 4) val 1426 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val) vxge_vBIT(val, 2, 14) val 2014 drivers/net/ethernet/neterion/vxge/vxge-config.h static inline void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr) val 2016 drivers/net/ethernet/neterion/vxge/vxge-config.h writel(val, addr + 4); val 2019 drivers/net/ethernet/neterion/vxge/vxge-config.h static inline void __vxge_hw_pio_mem_write32_lower(u32 val, void __iomem *addr) val 2021 drivers/net/ethernet/neterion/vxge/vxge-config.h writel(val, addr); val 415 drivers/net/ethernet/neterion/vxge/vxge-main.h #define VXGE_MODULE_PARAM_INT(p, val) \ val 416 drivers/net/ethernet/neterion/vxge/vxge-main.h static int p = val; \ val 25 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) val 26 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) val 54 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) val 55 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) val 56 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) val 57 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) val 59 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) val 60 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) val 61 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) val 62 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16) val 63 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(val) vxge_vBIT(val, 16, 8) val 66 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) val 76 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) val 77 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) val 113 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val) \ val 114 drivers/net/ethernet/neterion/vxge/vxge-reg.h (val&~VXGE_HW_TOC_KDFC_INITIAL_BIR(7)) val 115 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val) \ val 116 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_bVALn(val, 61, 3) val 117 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_GET_USDC_INITIAL_OFFSET(val) \ val 118 drivers/net/ethernet/neterion/vxge/vxge-reg.h (val&~VXGE_HW_TOC_USDC_INITIAL_BIR(7)) val 119 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_GET_USDC_INITIAL_BIR(val) \ val 120 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_bVALn(val, 61, 3) val 132 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vxge_vBIT(val, 42, 5) val 133 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vxge_vBIT(val, 47, 2) val 134 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) \ val 135 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 49, 15) val 165 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48) val 169 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vxge_vBIT(val, 0, 48) val 174 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) \ val 175 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 55, 5) val 178 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vxge_vBIT(val, 62, 2) val 206 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48) val 209 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vxge_vBIT(val, 0, 12) val 212 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_ETYPE(val) vxge_vBIT(val, 0, 16) val 222 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val) vxge_vBIT(val, 8, 16) val 229 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) \ val 230 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 4, 4) val 233 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) \ val 234 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 10, 2) val 268 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val) \ val 269 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 9, 7) val 273 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val) \ val 274 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 8) val 280 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val) \ val 281 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 9, 7) val 284 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val) \ val 285 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 8) val 291 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val) \ val 292 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 25, 7) val 295 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val) \ val 296 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 8) val 302 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val) \ val 303 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 9, 7) val 306 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val) \ val 307 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 8) val 313 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val) \ val 314 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 25, 7) val 318 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val) \ val 319 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 32) val 322 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val) \ val 323 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 327 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val) \ val 328 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 16) val 331 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val) \ val 332 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 335 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val) \ val 336 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 4) val 339 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val) \ val 340 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 36, 4) val 343 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val) \ val 344 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 40, 2) val 347 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val) \ val 348 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 42, 2) val 352 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY vxge_vBIT(val, 0, 64) val 364 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val) \ val 365 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 48) val 366 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val) \ val 367 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 62, 2) val 371 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val) \ val 372 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 8) val 378 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val) \ val 379 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 9, 7) val 382 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val) \ val 383 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 8) val 389 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val) \ val 390 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 25, 7) val 393 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val) \ val 394 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 8) val 400 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val) \ val 401 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 41, 7) val 404 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val) \ val 405 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 48, 8) val 411 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val) \ val 412 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 57, 7) val 428 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val) vxge_vBIT(val, 0, 8) val 431 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val) vxge_vBIT(val, 8, 8) val 434 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val) \ val 435 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 439 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vxge_vBIT(val, 32, 8) val 442 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR vxge_vBIT(val, 40, 8) val 445 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD vxge_vBIT(val, 48, 16) val 449 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_DAY(val) vxge_vBIT(val, 0, 8) val 452 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MONTH(val) vxge_vBIT(val, 8, 8) val 455 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_YEAR(val) \ val 456 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 460 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR vxge_vBIT(val, 32, 8) val 463 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MINOR vxge_vBIT(val, 40, 8) val 466 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16) val 600 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_SWAPPER_FB_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 602 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vxge_vBIT(val, 0, 64) val 604 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vxge_vBIT(val, 0, 64) val 606 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vxge_vBIT(val, 0, 64) val 608 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vxge_vBIT(val, 0, 64) val 610 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_FIRST_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 612 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vxge_vBIT(val, 0, 64) val 621 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_COMMON_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 623 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 625 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 629 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 631 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 635 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 639 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_VPATH_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) val 643 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_KDFC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61) val 644 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_KDFC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3) val 646 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_USDC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61) val 647 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_USDC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3) val 649 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val) \ val 650 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 652 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val) \ val 653 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 702 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vxge_vBIT(val, 0, 17) val 714 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val) vxge_vBIT(val, 0, 17) val 716 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val) vxge_vBIT(val, 0, 17) val 718 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val) vxge_vBIT(val, 0, 17) val 720 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val) vxge_vBIT(val, 0, 17) val 722 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val) vxge_vBIT(val, 0, 17) val 726 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val) vxge_vBIT(val, 0, 17) val 728 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_STATS_CFG0_STATS_ENABLE(val) vxge_vBIT(val, 0, 17) val 732 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) \ val 733 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 735 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vxge_vBIT(val, 0, 17) val 737 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val) \ val 738 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 740 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val) \ val 741 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 743 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MASK_VECTOR_MASK_VECTOR(val) vxge_vBIT(val, 0, 17) val 745 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val) \ val 746 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 748 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val) \ val 749 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 751 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val) vxge_vBIT(val, 0, 16) val 752 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val) vxge_vBIT(val, 48, 8) val 753 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val) vxge_vBIT(val, 56, 8) val 758 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val) \ val 759 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 17) val 768 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_INT_STATUS0_TIM_INT_STATUS0(val) vxge_vBIT(val, 0, 64) val 770 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_INT_MASK0_TIM_INT_MASK0(val) vxge_vBIT(val, 0, 64) val 772 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_INT_STATUS1_TIM_INT_STATUS1(val) vxge_vBIT(val, 0, 4) val 774 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_INT_MASK1_TIM_INT_MASK1(val) vxge_vBIT(val, 0, 4) val 776 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTI_INT_STATUS_RTI_INT_STATUS(val) vxge_vBIT(val, 0, 17) val 778 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTI_INT_MASK_RTI_INT_MASK(val) vxge_vBIT(val, 0, 17) val 793 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ADAPTER_STATUS_PCC_PCC_IDLE(val) vxge_vBIT(val, 24, 8) val 794 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val) vxge_vBIT(val, 44, 8) val 802 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GEN_CTRL_SPI_NOT_USED(val) vxge_vBIT(val, 6, 4) val 808 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_OUTSTANDING_READ_OUTSTANDING_READ(val) vxge_vBIT(val, 0, 17) val 810 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val) vxge_vBIT(val, 0, 17) val 812 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val) vxge_vBIT(val, 0, 17) val 820 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGMAC_READY_XMACJ_READY(val) vxge_vBIT(val, 0, 17) val 824 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FBIF_READY_FAU_READY(val) vxge_vBIT(val, 0, 17) val 828 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val) vxge_vBIT(val, 3, 5) val 830 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val) vxge_vBIT(val, 0, 17) val 832 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val) \ val 833 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 835 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val) \ val 836 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 5, 3) val 840 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val) \ val 841 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 842 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val) \ val 843 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 845 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val) \ val 846 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 850 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) val 852 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_TCPSYN_EN(val) vxge_vBIT(val, 0, 17) val 854 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_ZL4PYLD_EN(val) vxge_vBIT(val, 0, 17) val 856 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_L4PRTCL_TCP_EN(val) vxge_vBIT(val, 0, 17) val 858 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_L4PRTCL_UDP_EN(val) vxge_vBIT(val, 0, 17) val 860 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_L4PRTCL_FLEX_EN(val) vxge_vBIT(val, 0, 17) val 862 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_IPFRAG_EN(val) vxge_vBIT(val, 0, 17) val 876 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val) \ val 877 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 2, 6) val 879 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val) \ val 880 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 2, 6) val 882 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val) \ val 883 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 2, 6) val 885 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MSIXGRP_NO_TABLE_SIZE(val) vxge_vBIT(val, 5, 11) val 1033 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vxge_vBIT(val, 3, 5) val 1034 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vxge_vBIT(val, 11, 5) val 1035 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vxge_vBIT(val, 19, 5) val 1036 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vxge_vBIT(val, 27, 5) val 1037 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vxge_vBIT(val, 35, 5) val 1038 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vxge_vBIT(val, 43, 5) val 1039 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vxge_vBIT(val, 51, 5) val 1040 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vxge_vBIT(val, 59, 5) val 1042 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vxge_vBIT(val, 3, 5) val 1043 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vxge_vBIT(val, 11, 5) val 1044 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) \ val 1045 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1046 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) \ val 1047 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1048 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) \ val 1049 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1050 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) \ val 1051 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1052 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) \ val 1053 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1054 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) \ val 1055 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1057 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vxge_vBIT(val, 3, 5) val 1058 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) \ val 1059 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1060 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) \ val 1061 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1062 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) \ val 1063 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1064 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) \ val 1065 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1066 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) \ val 1067 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1068 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) \ val 1069 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1070 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) \ val 1071 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1073 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vxge_vBIT(val, 3, 5) val 1074 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) \ val 1075 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1076 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) \ val 1077 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1078 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) \ val 1079 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1080 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) \ val 1081 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1082 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) \ val 1083 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1084 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) \ val 1085 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1086 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) \ val 1087 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1089 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vxge_vBIT(val, 3, 5) val 1090 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) \ val 1091 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1092 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) \ val 1093 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1094 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) \ val 1095 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1096 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) \ val 1097 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1098 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) \ val 1099 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1100 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) \ val 1101 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1102 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) \ val 1103 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1105 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vxge_vBIT(val, 3, 5) val 1106 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) \ val 1107 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1108 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) \ val 1109 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1110 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) \ val 1111 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1112 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) \ val 1113 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1114 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) \ val 1115 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1116 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) \ val 1117 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1118 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) \ val 1119 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1121 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vxge_vBIT(val, 3, 5) val 1122 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) \ val 1123 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1124 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) \ val 1125 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1126 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) \ val 1127 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1128 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) \ val 1129 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1130 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) \ val 1131 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1132 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) \ val 1133 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1134 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) \ val 1135 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1137 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vxge_vBIT(val, 3, 5) val 1138 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) \ val 1139 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1140 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) \ val 1141 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1142 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) \ val 1143 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1144 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) \ val 1145 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1146 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) \ val 1147 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1148 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) \ val 1149 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1150 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) \ val 1151 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1153 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vxge_vBIT(val, 3, 5) val 1154 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) \ val 1155 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1156 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) \ val 1157 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1158 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) \ val 1159 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1160 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) \ val 1161 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1162 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) \ val 1163 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1164 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) \ val 1165 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1166 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) \ val 1167 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1169 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vxge_vBIT(val, 3, 5) val 1170 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) \ val 1171 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1172 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) \ val 1173 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1174 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) \ val 1175 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1176 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) \ val 1177 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1178 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) \ val 1179 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1180 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) \ val 1181 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1182 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) \ val 1183 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1185 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) \ val 1186 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1187 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) \ val 1188 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1189 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) \ val 1190 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1191 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) \ val 1192 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1193 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) \ val 1194 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1195 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) \ val 1196 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1197 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) \ val 1198 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1199 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) \ val 1200 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1202 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) \ val 1203 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1204 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) \ val 1205 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1206 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) \ val 1207 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1208 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) \ val 1209 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1210 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) \ val 1211 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1212 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) \ val 1213 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1214 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) \ val 1215 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1216 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) \ val 1217 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1219 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) \ val 1220 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1221 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) \ val 1222 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1223 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) \ val 1224 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1225 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) \ val 1226 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1227 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) \ val 1228 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1229 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) \ val 1230 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1231 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) \ val 1232 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1233 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) \ val 1234 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1236 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) \ val 1237 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1238 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) \ val 1239 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1240 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) \ val 1241 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1242 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) \ val 1243 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1244 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) \ val 1245 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1246 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) \ val 1247 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1248 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) \ val 1249 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1250 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) \ val 1251 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1253 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) \ val 1254 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1255 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) \ val 1256 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1257 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) \ val 1258 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1259 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) \ val 1260 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1261 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) \ val 1262 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1263 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) \ val 1264 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1265 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) \ val 1266 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1267 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) \ val 1268 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1270 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) \ val 1271 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1272 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) \ val 1273 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1274 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) \ val 1275 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1276 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) \ val 1277 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1278 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) \ val 1279 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1280 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) \ val 1281 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1282 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) \ val 1283 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1284 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) \ val 1285 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1287 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) \ val 1288 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1289 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) \ val 1290 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1291 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) \ val 1292 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1293 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) \ val 1294 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1295 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) \ val 1296 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1297 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) \ val 1298 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1299 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) \ val 1300 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1301 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) \ val 1302 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1304 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) \ val 1305 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1306 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) \ val 1307 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1308 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) \ val 1309 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1310 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) \ val 1311 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1312 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) \ val 1313 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1314 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) \ val 1315 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1316 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) \ val 1317 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1318 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) \ val 1319 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1321 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) \ val 1322 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1323 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) \ val 1324 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1325 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) \ val 1326 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1327 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) \ val 1328 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1329 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) \ val 1330 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1331 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) \ val 1332 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1333 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) \ val 1334 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1335 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) \ val 1336 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1338 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) \ val 1339 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1340 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) \ val 1341 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1342 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) \ val 1343 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1344 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) \ val 1345 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1346 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) \ val 1347 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1348 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) \ val 1349 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1350 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) \ val 1351 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1352 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) \ val 1353 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1355 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) \ val 1356 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1357 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) \ val 1358 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1359 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) \ val 1360 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1361 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) \ val 1362 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 27, 5) val 1363 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) \ val 1364 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 35, 5) val 1365 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) \ val 1366 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 1367 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) \ val 1368 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 1369 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) \ val 1370 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1372 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) \ val 1373 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 1374 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) \ val 1375 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 1376 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) \ val 1377 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 19, 5) val 1383 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vxge_vBIT(val, 3, 5) val 1384 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vxge_vBIT(val, 11, 5) val 1385 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vxge_vBIT(val, 19, 5) val 1386 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vxge_vBIT(val, 27, 5) val 1387 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vxge_vBIT(val, 35, 5) val 1388 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vxge_vBIT(val, 43, 5) val 1389 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vxge_vBIT(val, 51, 5) val 1390 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vxge_vBIT(val, 59, 5) val 1392 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vxge_vBIT(val, 3, 5) val 1393 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vxge_vBIT(val, 11, 5) val 1394 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vxge_vBIT(val, 19, 5) val 1395 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vxge_vBIT(val, 27, 5) val 1396 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vxge_vBIT(val, 35, 5) val 1397 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vxge_vBIT(val, 43, 5) val 1398 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vxge_vBIT(val, 51, 5) val 1399 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vxge_vBIT(val, 59, 5) val 1401 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vxge_vBIT(val, 3, 5) val 1405 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val) \ val 1406 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 1418 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) \ val 1419 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 2, 30) val 1420 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vxge_vBIT(val, 32, 32) val 1422 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vxge_vBIT(val, 2, 10) val 1423 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vxge_vBIT(val, 18, 14) val 1426 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_PRM_CTRL_FB_ROW_SIZE(val) vxge_vBIT(val, 46, 2) val 1428 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_NOA_CTRL_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 3, 5) val 1429 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 11, 5) val 1431 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vxge_vBIT(val, 37, 4) val 1432 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vxge_vBIT(val, 45, 4) val 1433 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vxge_vBIT(val, 53, 4) val 1434 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vxge_vBIT(val, 60, 4) val 1449 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vxge_vBIT(val, 10, 22) val 1450 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vxge_vBIT(val, 39, 9) val 1451 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vxge_vBIT(val, 55, 9) val 1474 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_0(val) vxge_vBIT(val, 5, 3) val 1475 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0(val) vxge_vBIT(val, 17, 15) val 1476 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_1(val) vxge_vBIT(val, 37, 3) val 1477 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_1(val) vxge_vBIT(val, 49, 15) val 1479 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_2(val) vxge_vBIT(val, 5, 3) val 1480 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2(val) vxge_vBIT(val, 17, 15) val 1481 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_3(val) vxge_vBIT(val, 37, 3) val 1482 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_3(val) vxge_vBIT(val, 49, 15) val 1484 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_4(val) vxge_vBIT(val, 5, 3) val 1485 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4(val) vxge_vBIT(val, 17, 15) val 1486 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_5(val) vxge_vBIT(val, 37, 3) val 1487 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_5(val) vxge_vBIT(val, 49, 15) val 1489 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_6(val) vxge_vBIT(val, 5, 3) val 1490 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6(val) vxge_vBIT(val, 17, 15) val 1491 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_7(val) vxge_vBIT(val, 37, 3) val 1492 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_7(val) vxge_vBIT(val, 49, 15) val 1494 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_8(val) vxge_vBIT(val, 17, 15) val 1495 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9(val) vxge_vBIT(val, 49, 15) val 1497 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_10(val) vxge_vBIT(val, 17, 15) val 1498 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11(val) vxge_vBIT(val, 49, 15) val 1500 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_12(val) vxge_vBIT(val, 17, 15) val 1501 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13(val) vxge_vBIT(val, 49, 15) val 1503 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_14(val) vxge_vBIT(val, 17, 15) val 1504 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15(val) vxge_vBIT(val, 49, 15) val 1506 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_VP_PARTITION_8_LENGTH_16(val) vxge_vBIT(val, 17, 15) val 1508 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vxge_vBIT(val, 3, 5) val 1509 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vxge_vBIT(val, 11, 5) val 1510 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vxge_vBIT(val, 19, 5) val 1511 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vxge_vBIT(val, 27, 5) val 1512 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vxge_vBIT(val, 35, 5) val 1513 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vxge_vBIT(val, 43, 5) val 1514 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vxge_vBIT(val, 51, 5) val 1515 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vxge_vBIT(val, 59, 5) val 1520 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vxge_vBIT(val, 3, 5) val 1521 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vxge_vBIT(val, 11, 5) val 1522 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vxge_vBIT(val, 19, 5) val 1523 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vxge_vBIT(val, 27, 5) val 1524 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vxge_vBIT(val, 35, 5) val 1525 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vxge_vBIT(val, 43, 5) val 1526 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vxge_vBIT(val, 51, 5) val 1527 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vxge_vBIT(val, 59, 5) val 1534 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vxge_vBIT(val, 3, 5) val 1535 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vxge_vBIT(val, 11, 5) val 1536 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vxge_vBIT(val, 19, 5) val 1537 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vxge_vBIT(val, 27, 5) val 1538 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vxge_vBIT(val, 35, 5) val 1539 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vxge_vBIT(val, 43, 5) val 1540 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vxge_vBIT(val, 51, 5) val 1541 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vxge_vBIT(val, 59, 5) val 1546 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vxge_vBIT(val, 6, 2) val 1547 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vxge_vBIT(val, 14, 2) val 1548 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vxge_vBIT(val, 22, 2) val 1549 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vxge_vBIT(val, 30, 2) val 1550 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vxge_vBIT(val, 38, 2) val 1551 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vxge_vBIT(val, 46, 2) val 1552 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vxge_vBIT(val, 54, 2) val 1553 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vxge_vBIT(val, 62, 2) val 1555 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vxge_vBIT(val, 6, 2) val 1557 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5) val 1564 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5) val 1580 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val) \ val 1581 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 4) val 1582 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val) \ val 1583 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 4, 4) val 1584 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val) \ val 1585 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 8, 4) val 1586 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val) \ val 1587 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 12, 4) val 1588 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val) \ val 1589 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 4) val 1590 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val) \ val 1591 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 20, 4) val 1592 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val) \ val 1593 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 24, 2) val 1594 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val) \ val 1595 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 26, 2) val 1596 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val) \ val 1597 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 28, 2) val 1598 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val) \ val 1599 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 30, 2) val 1608 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val) \ val 1609 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 40, 7) val 1610 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val) \ val 1611 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 47, 7) val 1612 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val) \ val 1613 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 54, 3) val 1614 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val) \ val 1615 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 57, 3) val 1638 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vxge_vBIT(val, 0, 4) val 1639 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vxge_vBIT(val, 4, 4) val 1640 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vxge_vBIT(val, 8, 4) val 1641 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vxge_vBIT(val, 12, 4) val 1642 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vxge_vBIT(val, 16, 4) val 1643 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vxge_vBIT(val, 20, 4) val 1644 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vxge_vBIT(val, 24, 4) val 1645 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vxge_vBIT(val, 28, 4) val 1657 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vxge_vBIT(val, 50, 14) val 1665 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vxge_vBIT(val, 9, 3) val 1667 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vxge_vBIT(val, 20, 16) val 1671 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vxge_vBIT(val, 48, 8) val 1683 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) \ val 1684 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 1, 7) val 1685 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) val 1686 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) \ val 1687 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 12, 4) val 1688 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4) val 1722 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vxge_vBIT(val, 24, 8) val 1734 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vxge_vBIT(val, 5, 3) val 1735 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vxge_vBIT(val, 9, 3) val 1736 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vxge_vBIT(val, 13, 3) val 1737 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vxge_vBIT(val, 17, 3) val 1738 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vxge_vBIT(val, 21, 3) val 1739 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_DS(val) vxge_vBIT(val, 25, 3) val 1740 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vxge_vBIT(val, 29, 3) val 1741 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vxge_vBIT(val, 33, 3) val 1742 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vxge_vBIT(val, 37, 3) val 1744 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vxge_vBIT(val, 0, 17) val 1746 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) \ val 1747 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 1753 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vxge_vBIT(val, 0, 8) val 1754 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) val 1755 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) \ val 1756 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 8) val 1760 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR0(val) vxge_vBIT(val, 0, 4) val 1761 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1(val) vxge_vBIT(val, 4, 4) val 1762 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR2(val) vxge_vBIT(val, 8, 4) val 1763 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR3(val) vxge_vBIT(val, 12, 4) val 1764 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR0(val) vxge_vBIT(val, 16, 4) val 1765 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR1(val) vxge_vBIT(val, 20, 4) val 1766 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR2(val) vxge_vBIT(val, 24, 4) val 1767 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR3(val) vxge_vBIT(val, 28, 4) val 1792 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val) \ val 1793 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 40, 2) val 1794 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val) \ val 1795 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 42, 2) val 1796 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val) \ val 1797 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 44, 2) val 1798 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val) \ val 1799 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 46, 2) val 1800 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val) \ val 1801 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 48, 2) val 1802 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val) \ val 1803 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 50, 2) val 1804 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val) \ val 1805 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 52, 2) val 1806 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val) \ val 1807 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 54, 2) val 1808 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val) \ val 1809 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 56, 2) val 1810 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val) \ val 1811 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 58, 2) val 1855 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val) \ val 1856 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 1858 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vxge_vBIT(val, 0, 64) val 1860 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val) \ val 1861 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 1867 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vxge_vBIT(val, 2, 2) val 1870 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vxge_vBIT(val, 28, 4) val 1871 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vxge_vBIT(val, 32, 4) val 1874 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID(val) vxge_vBIT(val, 6, 2) val 1875 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_TIMESTAMP_INTERVAL(val) vxge_vBIT(val, 12, 4) val 1877 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vxge_vBIT(val, 32, 16) val 1879 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vxge_vBIT(val, 4, 4) val 1880 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vxge_vBIT(val, 8, 4) val 1883 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_SYS_CMD_OP(val) vxge_vBIT(val, 5, 3) val 1885 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(val) vxge_vBIT(val, 27, 5) val 1886 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8) val 1888 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64) val 1905 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vxge_vBIT(val, 0, 48) val 1910 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) val 1916 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) \ val 1917 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 8, 8) val 1924 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val) \ val 1925 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 16) val 1934 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TIMER_CFG_1_FAST_PER(val) vxge_vBIT(val, 0, 16) val 1935 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER(val) vxge_vBIT(val, 16, 16) val 1936 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vxge_vBIT(val, 32, 16) val 1937 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vxge_vBIT(val, 48, 16) val 1939 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TIMER_CFG_2_CHURN_DET(val) vxge_vBIT(val, 0, 16) val 1940 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT(val) vxge_vBIT(val, 16, 16) val 1941 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vxge_vBIT(val, 32, 16) val 1942 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val) vxge_vBIT(val, 48, 16) val 1944 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) val 1948 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_SYS_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16) val 1952 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR(val) vxge_vBIT(val, 0, 48) val 1956 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_AGGR_ID_CFG_ID(val) vxge_vBIT(val, 0, 16) val 1958 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_AGGR_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16) val 1960 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16) val 1963 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16) val 1965 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vxge_vBIT(val, 0, 48) val 1967 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vxge_vBIT(val, 0, 16) val 1968 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) \ val 1969 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 1983 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vxge_vBIT(val, 0, 16) val 1984 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vxge_vBIT(val, 16, 16) val 1985 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vxge_vBIT(val, 32, 16) val 1986 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vxge_vBIT(val, 48, 16) val 1997 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) val 1999 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16) val 2000 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vxge_vBIT(val, 16, 16) val 2001 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) \ val 2002 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 16) val 2003 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) \ val 2004 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 48, 16) val 2015 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vxge_vBIT(val, 0, 16) val 2018 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16) val 2029 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) \ val 2030 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 48) val 2032 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) \ val 2033 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 16) val 2034 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) \ val 2035 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 2036 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) \ val 2037 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 16) val 2038 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) \ val 2039 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 48, 16) val 2052 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vxge_vBIT(val, 6, 2) val 2066 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vxge_vBIT(val, 37, 3) val 2067 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) \ val 2068 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 41, 3) val 2069 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vxge_vBIT(val, 44, 4) val 2072 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val) \ val 2073 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 56, 4) val 2074 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val) \ val 2075 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 60, 4) val 2077 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_WHILE(val) vxge_vBIT(val, 0, 8) val 2078 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE(val) \ val 2079 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 8, 8) val 2080 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_WAIT_WHILE(val) vxge_vBIT(val, 16, 8) val 2081 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vxge_vBIT(val, 24, 8) val 2082 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val) \ val 2083 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 8) val 2084 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val) \ val 2085 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 40, 8) val 2086 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val) \ val 2087 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 48, 8) val 2088 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val) \ val 2089 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 56, 8) val 2130 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PCC_CONTROL_FE_ENABLE(val) vxge_vBIT(val, 6, 2) val 2134 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PDA_STATUS1_PDA_WRAP_0_CTR(val) vxge_vBIT(val, 4, 4) val 2135 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR(val) vxge_vBIT(val, 12, 4) val 2136 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PDA_STATUS1_PDA_WRAP_2_CTR(val) vxge_vBIT(val, 20, 4) val 2137 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PDA_STATUS1_PDA_WRAP_3_CTR(val) vxge_vBIT(val, 28, 4) val 2138 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PDA_STATUS1_PDA_WRAP_4_CTR(val) vxge_vBIT(val, 36, 4) val 2139 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PDA_STATUS1_PDA_WRAP_5_CTR(val) vxge_vBIT(val, 44, 4) val 2140 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PDA_STATUS1_PDA_WRAP_6_CTR(val) vxge_vBIT(val, 52, 4) val 2141 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PDA_STATUS1_PDA_WRAP_7_CTR(val) vxge_vBIT(val, 60, 4) val 2143 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_BW_TIMER_TIMER_CTRL(val) vxge_vBIT(val, 12, 4) val 2189 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8) val 2190 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) val 2191 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_0(val) vxge_vBIT(val, 16, 8) val 2192 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_1(val) vxge_vBIT(val, 24, 8) val 2193 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2(val) vxge_vBIT(val, 32, 8) val 2194 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_3(val) vxge_vBIT(val, 40, 8) val 2200 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FBMC_ECC_CFG_ENABLE(val) vxge_vBIT(val, 3, 5) val 2317 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RC_CFG2_BUFF1_SIZE(val) vxge_vBIT(val, 0, 16) val 2318 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RC_CFG2_BUFF2_SIZE(val) vxge_vBIT(val, 16, 16) val 2319 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RC_CFG2_BUFF3_SIZE(val) vxge_vBIT(val, 32, 16) val 2320 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RC_CFG2_BUFF4_SIZE(val) vxge_vBIT(val, 48, 16) val 2322 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RC_CFG3_BUFF5_SIZE(val) vxge_vBIT(val, 0, 16) val 2325 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vxge_vBIT(val, 11, 5) val 2327 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXDM_DBG_RD_ADDR(val) vxge_vBIT(val, 0, 12) val 2330 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vxge_vBIT(val, 0, 64) val 2332 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \ val 2333 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 2347 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) val 2349 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vxge_vBIT(val, 3, 5) val 2358 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vxge_vBIT(val, 0, 4) val 2359 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vxge_vBIT(val, 4, 4) val 2413 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vxge_vBIT(val, 0, 2) val 2466 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vxge_vBIT(val, 54, 2) val 2472 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vxge_vBIT(val, 0, 8) val 2473 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vxge_vBIT(val, 8, 2) val 2480 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vxge_vBIT(val, 16, 2) val 2481 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vxge_vBIT(val, 24, 8) val 2482 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vxge_vBIT(val, 32, 2) val 2489 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vxge_vBIT(val, 40, 2) val 2515 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE(val) vxge_vBIT(val, 32, 32) val 2609 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MSG_EXC_CAUSE_MP_MXP(val) vxge_vBIT(val, 0, 32) val 2610 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MSG_EXC_CAUSE_UP_UXP(val) vxge_vBIT(val, 32, 32) val 2733 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val) \ val 2734 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 2, 2) val 2735 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val) \ val 2736 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 4, 2) val 2739 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val) \ val 2740 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 8, 2) val 2741 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val) \ val 2742 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 10, 2) val 2745 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val) \ val 2746 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 14, 2) val 2747 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val) \ val 2748 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 2) val 2749 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) \ val 2750 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 18, 2) val 2751 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) \ val 2752 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 20, 2) val 2764 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) \ val 2765 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 2769 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FAU_LAG_CFG_COLL_ALG(val) vxge_vBIT(val, 2, 2) val 2798 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vxge_vBIT(val, 18, 2) val 2799 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vxge_vBIT(val, 22, 2) val 2821 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) \ val 2822 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 2850 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vxge_vBIT(val, 0, 8) val 2851 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) val 2852 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) \ val 2853 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 8) val 2857 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) \ val 2858 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 1, 7) val 2859 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) val 2860 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) \ val 2861 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 12, 4) val 2862 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4) val 2867 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TXMAC_CFG0_PORT_PAD_BYTE(val) vxge_vBIT(val, 8, 8) val 2869 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TXMAC_CFG1_PORT_AVG_IPG(val) vxge_vBIT(val, 40, 8) val 2879 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_MARKER_CFG_RESP_TIMEOUT(val) vxge_vBIT(val, 16, 16) val 2880 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val) \ val 2881 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 16) val 2885 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vxge_vBIT(val, 6, 2) val 2887 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TX_CFG_COLL_MAX_DELAY(val) vxge_vBIT(val, 16, 16) val 2889 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) \ val 2890 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 8) val 2891 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val) \ val 2892 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 8, 8) val 2893 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val) \ val 2894 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 8) val 2899 drivers/net/ethernet/neterion/vxge/vxge-reg.h VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_SWIF_SRPCIM_TO_MRPCIM_VPLANE_RMSG(val)\ val 2900 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 2904 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_TO_SRPCIM_VPLANE_WMSG_MRPCIM_TO_SRPCIM_VPLANE_WMSG(val) \ val 2905 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 2909 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS0_RSTDROP_MSG(val) vxge_vBIT(val, 0, 32) val 2910 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS0_RSTDROP_CPL(val) vxge_vBIT(val, 32, 32) val 2912 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0(val) vxge_vBIT(val, 0, 32) val 2913 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1(val) vxge_vBIT(val, 32, 32) val 2915 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2(val) vxge_vBIT(val, 0, 32) val 2917 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_PH(val) vxge_vBIT(val, 0, 16) val 2918 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vxge_vBIT(val, 16, 16) val 2919 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vxge_vBIT(val, 32, 16) val 2921 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_PD(val) vxge_vBIT(val, 0, 16) val 2922 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vxge_vBIT(val, 16, 16) val 2923 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vxge_vBIT(val, 32, 16) val 3165 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_TO_MRPCIM_ALARM_REG_PPIF_SRPCIM_TO_MRPCIM_ALARM(val) \ val 3166 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 3170 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_TO_MRPCIM_ALARM_REG_PPIF_VPATH_TO_MRPCIM_ALARM(val) \ val 3171 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 3221 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) \ val 3222 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 13, 51) val 3224 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val) \ val 3225 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 8) val 3227 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val) \ val 3228 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 4, 12) val 3243 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val) \ val 3244 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 47, 5) val 3255 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vxge_vBIT(val, 20, 16) val 3256 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) \ val 3257 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 36, 16) val 3259 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vxge_vBIT(val, 56, 2) val 3263 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\ val 3264 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 57) val 3269 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) \ val 3270 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 18, 6) val 3271 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) \ val 3272 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 26, 6) val 3273 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) \ val 3274 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 34, 6) val 3275 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RDCRDTARB_CFG0_WAIT_CNT(val) vxge_vBIT(val, 48, 4) val 3276 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vxge_vBIT(val, 54, 6) val 3281 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_BF_SW_RESET_BF_SW_RESET(val) vxge_vBIT(val, 0, 8) val 3288 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vxge_vBIT(val, 0, 32) val 3289 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vxge_vBIT(val, 32, 32) val 3291 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val) \ val 3292 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 3294 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val) \ val 3295 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 3297 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val) \ val 3298 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 3300 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vxge_vBIT(val, 0, 32) val 3301 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) \ val 3302 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 3304 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vxge_vBIT(val, 0, 32) val 3305 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vxge_vBIT(val, 32, 32) val 3307 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vxge_vBIT(val, 0, 32) val 3308 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vxge_vBIT(val, 32, 32) val 3310 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vxge_vBIT(val, 32, 32) val 3312 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vxge_vBIT(val, 32, 32) val 3317 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_CFG_DTYPE_SEL(val) vxge_vBIT(val, 3, 5) val 3318 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_CFG_CLIENT_NO_SEL(val) vxge_vBIT(val, 9, 3) val 3319 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_CFG_WR_RD_CPL_SEL(val) vxge_vBIT(val, 14, 2) val 3320 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_GENSTATS_CFG_VPATH_SEL(val) vxge_vBIT(val, 31, 17) val 3342 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ val 3343 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 24, 8) val 3356 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ val 3357 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 24, 8) val 3370 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ val 3371 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 24, 8) val 3378 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) \ val 3379 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 3383 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vxge_vBIT(val, 16, 4) val 3384 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vxge_vBIT(val, 20, 4) val 3386 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_1(val) vxge_vBIT(val, 29, 3) val 3387 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vxge_vBIT(val, 32, 4) val 3388 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vxge_vBIT(val, 36, 4) val 3389 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vxge_vBIT(val, 40, 4) val 3390 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vxge_vBIT(val, 44, 4) val 3392 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vxge_vBIT(val, 0, 4) val 3393 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) \ val 3394 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 48) val 3396 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val) \ val 3397 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 16) val 3398 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val) \ val 3399 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 3400 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val) \ val 3401 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 16) val 3402 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val) \ val 3403 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 48, 16) val 3405 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vxge_vBIT(val, 0, 4) val 3406 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vxge_vBIT(val, 4, 4) val 3408 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) \ val 3409 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 12, 4) val 3410 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vxge_vBIT(val, 16, 4) val 3412 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vxge_vBIT(val, 24, 8) val 3413 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) \ val 3414 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 4) val 3415 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) \ val 3416 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 36, 4) val 3418 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vxge_vBIT(val, 0, 8) val 3426 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_0(val) vxge_vBIT(val, 0, 32) val 3427 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_1(val) vxge_vBIT(val, 32, 32) val 3429 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RATEMGMT_CFG_PORT_MODE(val) vxge_vBIT(val, 2, 2) val 3446 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val) \ val 3447 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 4) val 3448 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESPONSE(val) \ val 3449 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 20, 4) val 3450 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESPONSE(val) \ val 3451 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 24, 4) val 3460 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vxge_vBIT(val, 16, 4) val 3461 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vxge_vBIT(val, 20, 4) val 3462 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vxge_vBIT(val, 24, 4) val 3466 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_CFG_PORT_RESET_CFG_REGS(val) vxge_vBIT(val, 0, 8) val 3467 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vxge_vBIT(val, 10, 2) val 3468 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vxge_vBIT(val, 14, 2) val 3472 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_MGR_CTRL_PORT_ADDR(val) vxge_vBIT(val, 15, 9) val 3473 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_MGR_CTRL_PORT_DATA(val) vxge_vBIT(val, 32, 32) val 3488 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val) \ val 3489 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 18, 6) val 3507 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val) \ val 3508 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 56, 4) val 3509 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val) \ val 3510 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 60, 4) val 3522 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val) \ val 3523 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 43, 5) val 3530 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val) \ val 3531 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 54, 5) val 3532 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \ val 3533 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 3535 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val) \ val 3536 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 3537 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val) \ val 3538 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 3545 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val) \ val 3546 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 10, 6) val 3567 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val) \ val 3568 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 4, 7) val 3569 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \ val 3570 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 11, 5) val 3577 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val) \ val 3578 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 5, 11) val 3579 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val) \ val 3580 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 3581 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val) \ val 3582 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 16) val 3585 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vxge_vBIT(val, 5, 3) val 3586 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DEVAD(val) vxge_vBIT(val, 11, 5) val 3587 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ADDR(val) vxge_vBIT(val, 16, 16) val 3588 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DATA(val) vxge_vBIT(val, 32, 16) val 3589 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vxge_vBIT(val, 49, 2) val 3591 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MDIO_MGR_ACCESS_PORT_PRTAD(val) vxge_vBIT(val, 55, 5) val 3595 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17) val 3599 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8) val 3600 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) val 3601 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_0(val) vxge_vBIT(val, 16, 8) val 3602 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_1(val) vxge_vBIT(val, 24, 8) val 3603 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_2(val) vxge_vBIT(val, 32, 8) val 3604 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_3(val) vxge_vBIT(val, 40, 8) val 3612 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) \ val 3613 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 32) val 3649 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val) \ val 3650 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 3654 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val) \ val 3655 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 3657 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SEL_VPATH_TO_SRPCIM_RMSG_SEL(val) \ val 3658 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 5) val 3660 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val) \ val 3661 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 3699 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PF_SW_RESET_PF_SW_RESET(val) vxge_vBIT(val, 0, 8) val 3708 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7) val 3709 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vxge_vBIT(val, 9, 3) val 3723 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7) val 3743 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val) \ val 3744 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 3748 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \ val 3749 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 3773 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_ALIGNMENT_PREFERENCE(val) vxge_vBIT(val, 30, 2) val 3774 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_MEM_WORD_SIZE(val) vxge_vBIT(val, 46, 2) val 3784 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1(val) \ val 3785 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 3, 5) val 3789 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val) \ val 3790 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 3797 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) val 3801 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) \ val 3802 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 3830 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE(val) \ val 3831 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 24, 8) val 3840 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val) \ val 3841 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 5, 3) val 3842 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val) \ val 3843 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 9, 3) val 3844 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN(val) \ val 3845 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 13, 3) val 3846 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN(val) \ val 3847 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 17, 3) val 3848 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val) \ val 3849 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 21, 3) val 3850 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val) \ val 3851 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 25, 3) val 3852 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val) \ val 3853 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 29, 3) val 3854 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD(val) \ val 3855 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 33, 3) val 3856 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL(val) \ val 3857 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 37, 3) val 3867 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN(val) \ val 3868 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 50, 14) val 3872 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val) \ val 3873 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 9, 3) val 3875 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val) \ val 3876 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 20, 16) val 3882 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val) \ val 3883 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 48, 8) val 3889 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17) val 3904 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val) \ val 3905 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 2, 2) val 3909 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val) \ val 3910 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 28, 4) val 3911 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val) \ val 3912 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 4) val 3915 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val) \ val 3916 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 6, 2) val 3917 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val) vxge_vBIT(val, 12, 4) val 3919 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val) \ val 3920 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 16) val 3922 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val) \ val 3923 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 4, 4) val 3924 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val) \ val 3925 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 8, 4) val 3940 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE(val) vxge_vBIT(val, 8, 8) val 3944 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) val 3947 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WOL_MP_MASK_A_MASK(val) vxge_vBIT(val, 0, 64) val 3949 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WOL_MP_MASK_B_MASK(val) vxge_vBIT(val, 0, 64) val 3957 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val) \ val 3958 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 7, 9) val 3959 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) \ val 3960 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 4) val 3961 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val) \ val 3962 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 20, 4) val 3963 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val) \ val 3964 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 24, 4) val 3968 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val) \ val 3969 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 7, 9) val 3970 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) \ val 3971 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 4) val 3972 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val) \ val 3973 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 20, 4) val 3974 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) \ val 3975 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 24, 4) val 3984 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_USDC_VPATH_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 32) val 4000 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG1_RX_TIMER_VAL(val) vxge_vBIT(val, 3, 29) val 4006 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vxge_vBIT(val, 40, 2) val 4011 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG4_RING_MODE(val) vxge_vBIT(val, 14, 2) val 4018 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG4_BACKOFF_INTERVAL(val) vxge_vBIT(val, 40, 24) val 4020 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG5_RXD0_ADD(val) vxge_vBIT(val, 0, 61) val 4027 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9) val 4028 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9) val 4029 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val) vxge_bVALn(val, 36, 9) val 4031 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2) val 4035 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vxge_vBIT(val, 20, 4) val 4036 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_CFG7_BUFF_SIZE0_MASK(val) vxge_vBIT(val, 27, 5) val 4038 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vxge_vBIT(val, 0, 64) val 4040 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val) vxge_vBIT(val, 48, 16) val 4042 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vxge_vBIT(val, 59, 5) val 4044 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val) vxge_vBIT(val, 51, 13) val 4046 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val) \ val 4047 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 59, 5) val 4049 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vxge_vBIT(val, 48, 16) val 4051 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) \ val 4052 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 4054 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXD_RETURNED_RXD_RETURNED(val) vxge_vBIT(val, 48, 16) val 4058 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val) vxge_vBIT(val, 17, 15) val 4059 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vxge_vBIT(val, 33, 15) val 4060 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val) vxge_vBIT(val, 49, 15) val 4064 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(val) vxge_vBIT(val, 14, 2) val 4067 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) val 4072 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) val 4073 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) val 4074 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) val 4076 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE(val) vxge_vBIT(val, 14, 2) val 4079 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) val 4084 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) val 4085 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) val 4086 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) val 4090 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) val 4095 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) val 4096 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) val 4097 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) val 4099 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) val 4101 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) val 4103 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) val 4105 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val) vxge_vBIT(val, 1, 15) val 4106 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vxge_vBIT(val, 17, 15) val 4107 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val) vxge_vBIT(val, 33, 15) val 4109 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) \ val 4110 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 17, 15) val 4134 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val) vxge_vBIT(val, 2, 14) val 4136 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val) vxge_vBIT(val, 26, 14) val 4142 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val) vxge_vBIT(val, 42, 2) val 4146 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(val) vxge_vBIT(val, 1, 7) val 4147 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vxge_vBIT(val, 8, 4) val 4152 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(val) vxge_vBIT(val, 40, 8) val 4154 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DATA(val) vxge_vBIT(val, 0, 64) val 4156 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DATA(val) vxge_vBIT(val, 0, 64) val 4160 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val) vxge_vBIT(val, 3, 5) val 4163 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(val) vxge_vBIT(val, 6, 2) val 4165 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8) val 4167 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64) val 4194 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_BW_CTRL_DESIRED_BW(val) vxge_vBIT(val, 46, 18) val 4197 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vxge_vBIT(val, 6, 2) val 4198 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vxge_vBIT(val, 8, 8) val 4201 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val) \ val 4202 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 21, 3) val 4204 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val) \ val 4205 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 29, 3) val 4207 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) \ val 4208 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 37, 3) val 4210 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val) \ val 4211 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 51, 5) val 4213 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) \ val 4214 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 61, 3) val 4223 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(val) vxge_vBIT(val, 6, 26) val 4229 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(val) vxge_vBIT(val, 41, 7) val 4230 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(val) vxge_vBIT(val, 49, 7) val 4231 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(val) vxge_vBIT(val, 57, 7) val 4233 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(val) vxge_vBIT(val, 0, 16) val 4234 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(val) vxge_vBIT(val, 16, 16) val 4235 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(val) vxge_vBIT(val, 32, 16) val 4236 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(val) vxge_vBIT(val, 48, 16) val 4239 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val) vxge_vBIT(val, 1, 4) val 4240 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vxge_vBIT(val, 6, 26) val 4241 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(val) vxge_vBIT(val, 32, 6) val 4242 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(val) vxge_vBIT(val, 38, 26) val 4244 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vxge_vBIT(val, 0, 32) val 4245 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vxge_vBIT(val, 35, 5) val 4247 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(val) vxge_vBIT(val, 41, 2) val 4249 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_WRKLD_CLC_HOST_UTIL(val) vxge_vBIT(val, 57, 7) val 4251 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_BITMAP_MASK(val) vxge_vBIT(val, 0, 32) val 4255 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_RING_ASSN_INT_NUM(val) vxge_vBIT(val, 6, 2) val 4260 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_REMAP_TO_VPATH_NUM(val) vxge_vBIT(val, 11, 5) val 4262 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TIM_VPATH_MAP_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) val 4271 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SGRP_ASSIGN_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 64) val 4273 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val) \ val 4274 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 4303 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vxge_vBIT(val, 32, 32) val 4305 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val) \ val 4306 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 32) val 4307 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val) \ val 4308 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 4310 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vxge_vBIT(val, 0, 32) val 4330 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vxge_vBIT(val, 0, 64) val 4334 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DMQ_IR_INT_NUMBER(val) vxge_vBIT(val, 9, 7) val 4335 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DMQ_IR_INT_BITMAP(val) vxge_vBIT(val, 16, 16) val 4337 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64) val 4339 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) val 4341 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) val 4345 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UMQ_INT_NUMBER(val) vxge_vBIT(val, 9, 7) val 4346 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UMQ_INT_BITMAP(val) vxge_vBIT(val, 16, 16) val 4348 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val) vxge_vBIT(val, 0, 8) val 4352 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vxge_vBIT(val, 32, 32) val 4354 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64) val 4356 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) val 4374 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val) \ val 4375 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 48, 16) val 4385 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vxge_vBIT(val, 0, 16) val 4386 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vxge_vBIT(val, 16, 16) val 4387 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vxge_vBIT(val, 32, 16) val 4389 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vxge_vBIT(val, 0, 16) val 4390 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val) \ val 4391 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 16, 16) val 4392 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) \ val 4393 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 4417 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_TO_SRPCIM_WMSG_VPATH_TO_SRPCIM_WMSG(val) \ val 4418 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 4484 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_PPIF_SRPCIM_TO_VPATH_ALARM(val) \ val 4485 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 17) val 4491 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val) vxge_vBIT(val, 0, 8) val 4492 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vxge_vBIT(val, 8, 8) val 4493 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val) vxge_vBIT(val, 16, 8) val 4494 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val) vxge_vBIT(val, 24, 8) val 4495 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vxge_vBIT(val, 32, 8) val 4496 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val) vxge_vBIT(val, 40, 8) val 4499 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vxge_vBIT(val, 6, 2) val 4501 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val) vxge_vBIT(val, 0, 12) val 4503 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val) vxge_vBIT(val, 0, 12) val 4505 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val) vxge_vBIT(val, 0, 12) val 4509 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7) val 4513 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_GENERAL_CFG1_TC_VALUE(val) vxge_vBIT(val, 1, 3) val 4523 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val) vxge_vBIT(val, 1, 3) val 4563 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_STATS_CFG_START_HOST_ADDR(val) vxge_vBIT(val, 0, 57) val 4565 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_INTERRUPT_CFG0_MSIX_FOR_RXTI(val) vxge_vBIT(val, 1, 7) val 4566 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vxge_vBIT(val, 9, 7) val 4567 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val) vxge_vBIT(val, 17, 7) val 4568 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val) vxge_vBIT(val, 25, 7) val 4569 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val) vxge_vBIT(val, 33, 7) val 4573 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7) val 4585 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vxge_vBIT(val, 0, 12) val 4591 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_DATA(val) vxge_vBIT(val, 32, 32) val 4595 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vxge_vBIT(val, 0, 32) val 4597 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vxge_vBIT(val, 0, 32) val 4599 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vxge_vBIT(val, 0, 32) val 4601 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) \ val 4602 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 4604 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) \ val 4605 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 64) val 4607 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32) val 4609 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32) val 4611 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val) \ val 4612 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 32) val 4613 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val) \ val 4614 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 4616 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val) \ val 4617 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 0, 32) val 4618 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val) \ val 4619 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 4621 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val) \ val 4622 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 4624 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val) \ val 4625 drivers/net/ethernet/neterion/vxge/vxge-reg.h vxge_vBIT(val, 32, 32) val 16 drivers/net/ethernet/netronome/nfp/abm/cls.c u8 val; val 49 drivers/net/ethernet/netronome/nfp/abm/cls.c if (knode->val || knode->mask) { val 88 drivers/net/ethernet/netronome/nfp/abm/cls.c if (k->val & ~k->mask) { val 113 drivers/net/ethernet/netronome/nfp/abm/cls.c if ((prio & iter->mask) == iter->val) val 176 drivers/net/ethernet/netronome/nfp/abm/cls.c u8 mask, val; val 185 drivers/net/ethernet/netronome/nfp/abm/cls.c val = be32_to_cpu(knode->sel->keys[0].val) >> tos_off & 0xff; val 198 drivers/net/ethernet/netronome/nfp/abm/cls.c if ((iter->val & cmask) == (val & cmask) && val 214 drivers/net/ethernet/netronome/nfp/abm/cls.c match->val = val; val 53 drivers/net/ethernet/netronome/nfp/abm/ctrl.c u64 val, sym_offset; val 62 drivers/net/ethernet/netronome/nfp/abm/ctrl.c err = __nfp_rtsym_readq(cpp, sym, 3, 0, sym_offset, &val); val 71 drivers/net/ethernet/netronome/nfp/abm/ctrl.c *res = is_u64 ? val : val32; val 75 drivers/net/ethernet/netronome/nfp/abm/ctrl.c int __nfp_abm_ctrl_set_q_lvl(struct nfp_abm *abm, unsigned int id, u32 val) val 82 drivers/net/ethernet/netronome/nfp/abm/ctrl.c if (abm->thresholds[id] == val) val 86 drivers/net/ethernet/netronome/nfp/abm/ctrl.c err = __nfp_rtsym_writel(cpp, abm->q_lvls, 4, 0, sym_offset, val); val 94 drivers/net/ethernet/netronome/nfp/abm/ctrl.c abm->thresholds[id] = val; val 99 drivers/net/ethernet/netronome/nfp/abm/ctrl.c unsigned int queue, u32 val) val 105 drivers/net/ethernet/netronome/nfp/abm/ctrl.c return __nfp_abm_ctrl_set_q_lvl(alink->abm, threshold, val); val 144 drivers/net/ethernet/netronome/nfp/abm/ctrl.c u64 val, sum = 0; val 149 drivers/net/ethernet/netronome/nfp/abm/ctrl.c band, queue, true, &val)) val 151 drivers/net/ethernet/netronome/nfp/abm/ctrl.c sum += val; val 160 drivers/net/ethernet/netronome/nfp/abm/ctrl.c u64 val, sum = 0; val 165 drivers/net/ethernet/netronome/nfp/abm/ctrl.c band, queue, true, &val)) val 167 drivers/net/ethernet/netronome/nfp/abm/ctrl.c sum += val; val 175 drivers/net/ethernet/netronome/nfp/abm/ctrl.c unsigned int queue, unsigned int off, u64 *val) val 181 drivers/net/ethernet/netronome/nfp/abm/ctrl.c *val = nn_readq(alink->vnic, val 184 drivers/net/ethernet/netronome/nfp/abm/ctrl.c *val = 0; val 191 drivers/net/ethernet/netronome/nfp/abm/ctrl.c true, val); val 254 drivers/net/ethernet/netronome/nfp/abm/main.h int __nfp_abm_ctrl_set_q_lvl(struct nfp_abm *abm, unsigned int id, u32 val); val 256 drivers/net/ethernet/netronome/nfp/abm/main.h unsigned int queue, u32 val); val 590 drivers/net/ethernet/netronome/nfp/bpf/jit.c static bool pack_immed(u32 imm, u16 *val, enum immed_shift *shift) val 593 drivers/net/ethernet/netronome/nfp/bpf/jit.c *val = imm; val 596 drivers/net/ethernet/netronome/nfp/bpf/jit.c *val = imm >> 8; val 599 drivers/net/ethernet/netronome/nfp/bpf/jit.c *val = imm >> 16; val 611 drivers/net/ethernet/netronome/nfp/bpf/jit.c u16 val; val 613 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (pack_immed(imm, &val, &shift)) { val 614 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_immed(nfp_prog, dst, val, IMMED_WIDTH_ALL, false, shift); val 615 drivers/net/ethernet/netronome/nfp/bpf/jit.c } else if (pack_immed(~imm, &val, &shift)) { val 616 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_immed(nfp_prog, dst, val, IMMED_WIDTH_ALL, true, shift); val 4541 drivers/net/ethernet/netronome/nfp/bpf/jit.c u32 val; val 4581 drivers/net/ethernet/netronome/nfp/bpf/jit.c val = br_get_offset(prog[i]); val 4582 drivers/net/ethernet/netronome/nfp/bpf/jit.c val -= BR_OFF_RELO; val 4583 drivers/net/ethernet/netronome/nfp/bpf/jit.c switch (val) { val 4585 drivers/net/ethernet/netronome/nfp/bpf/jit.c val = nfp_prog->bpf->helpers.map_lookup; val 4588 drivers/net/ethernet/netronome/nfp/bpf/jit.c val = nfp_prog->bpf->helpers.map_update; val 4591 drivers/net/ethernet/netronome/nfp/bpf/jit.c val = nfp_prog->bpf->helpers.map_delete; val 4594 drivers/net/ethernet/netronome/nfp/bpf/jit.c val = nfp_prog->bpf->helpers.perf_event_output; val 4598 drivers/net/ethernet/netronome/nfp/bpf/jit.c val); val 4602 drivers/net/ethernet/netronome/nfp/bpf/jit.c br_set_offset(&prog[i], val); val 32 drivers/net/ethernet/netronome/nfp/crypto/tls.c u32 off, val; val 36 drivers/net/ethernet/netronome/nfp/crypto/tls.c val = nn_readl(nn, off); val 38 drivers/net/ethernet/netronome/nfp/crypto/tls.c val |= BIT(opcode & 31); val 40 drivers/net/ethernet/netronome/nfp/crypto/tls.c val &= ~BIT(opcode & 31); val 41 drivers/net/ethernet/netronome/nfp/crypto/tls.c nn_writel(nn, off, val); val 119 drivers/net/ethernet/netronome/nfp/devlink_param.c ctx->val.vu8 = arg->invalid_dl_val; val 126 drivers/net/ethernet/netronome/nfp/devlink_param.c ctx->val.vu8 = arg->hi_to_dl[value]; val 157 drivers/net/ethernet/netronome/nfp/devlink_param.c arg->hwinfo_name, arg->dl_to_hi[ctx->val.vu8]); val 171 drivers/net/ethernet/netronome/nfp/devlink_param.c union devlink_param_value val, val 181 drivers/net/ethernet/netronome/nfp/devlink_param.c if (val.vu8 > arg->max_dl_val) { val 186 drivers/net/ethernet/netronome/nfp/devlink_param.c if (val.vu8 == arg->invalid_dl_val) { val 499 drivers/net/ethernet/netronome/nfp/flower/action.c exact = act->mangle.val; val 536 drivers/net/ethernet/netronome/nfp/flower/action.c exact = (__force __be32)act->mangle.val; val 677 drivers/net/ethernet/netronome/nfp/flower/action.c exact = (__force __be32)act->mangle.val; val 717 drivers/net/ethernet/netronome/nfp/flower/action.c exact = act->mangle.val; val 104 drivers/net/ethernet/netronome/nfp/nfp_asm.c u16 val; val 109 drivers/net/ethernet/netronome/nfp/nfp_asm.c val = immed_get_value(*instr); val 110 drivers/net/ethernet/netronome/nfp/nfp_asm.c immed_set_value(instr, val + offset); val 116 drivers/net/ethernet/netronome/nfp/nfp_asm.c u16 val = swreg_value(reg); val 122 drivers/net/ethernet/netronome/nfp/nfp_asm.c return val; val 124 drivers/net/ethernet/netronome/nfp/nfp_asm.c return UR_REG_NN | val; val 126 drivers/net/ethernet/netronome/nfp/nfp_asm.c return UR_REG_XFR | val; val 132 drivers/net/ethernet/netronome/nfp/nfp_asm.c if (val & ~UR_REG_LM_IDX_MAX) { val 137 drivers/net/ethernet/netronome/nfp/nfp_asm.c val; val 142 drivers/net/ethernet/netronome/nfp/nfp_asm.c if (val) { val 155 drivers/net/ethernet/netronome/nfp/nfp_asm.c if (val & ~0xff) { val 159 drivers/net/ethernet/netronome/nfp/nfp_asm.c return UR_REG_IMM_encode(val); val 206 drivers/net/ethernet/netronome/nfp/nfp_asm.c u16 val = swreg_value(reg); val 213 drivers/net/ethernet/netronome/nfp/nfp_asm.c return val; val 215 drivers/net/ethernet/netronome/nfp/nfp_asm.c return RE_REG_XFR | val; val 225 drivers/net/ethernet/netronome/nfp/nfp_asm.c if (val & ~RE_REG_LM_IDX_MAX) { val 230 drivers/net/ethernet/netronome/nfp/nfp_asm.c return RE_REG_LM | FIELD_PREP(RE_REG_LM_IDX, lm_id) | val; val 232 drivers/net/ethernet/netronome/nfp/nfp_asm.c if (val & ~(0x7f | has_imm8 << 7)) { val 236 drivers/net/ethernet/netronome/nfp/nfp_asm.c *i8 = val & 0x80; val 237 drivers/net/ethernet/netronome/nfp/nfp_asm.c return RE_REG_IMM_encode(val & 0x7f); val 194 drivers/net/ethernet/netronome/nfp/nfp_devlink.c const char *val; val 198 drivers/net/ethernet/netronome/nfp/nfp_devlink.c val = nfp_hwinfo_lookup(pf->hwinfo, info->hwinfo); val 199 drivers/net/ethernet/netronome/nfp/nfp_devlink.c if (!val) val 202 drivers/net/ethernet/netronome/nfp/nfp_devlink.c err = devlink_info_version_fixed_put(req, info->key, val); val 28 drivers/net/ethernet/netronome/nfp/nfp_hwmon.c int channel, long *val) val 33 drivers/net/ethernet/netronome/nfp/nfp_hwmon.c long val; val 45 drivers/net/ethernet/netronome/nfp/nfp_hwmon.c *val = const_vals[i].val; val 58 drivers/net/ethernet/netronome/nfp/nfp_hwmon.c return nfp_hwmon_read_sensor(pf->cpp, id, val); val 60 drivers/net/ethernet/netronome/nfp/nfp_hwmon.c return nfp_hwmon_read_sensor(pf->cpp, id, val); val 58 drivers/net/ethernet/netronome/nfp/nfp_main.c u64 val; val 62 drivers/net/ethernet/netronome/nfp/nfp_main.c val = nfp_rtsym_read_le(pf->rtbl, name, &err); val 70 drivers/net/ethernet/netronome/nfp/nfp_main.c return val; val 91 drivers/net/ethernet/netronome/nfp/nfp_main.c u32 val = 0; val 100 drivers/net/ethernet/netronome/nfp/nfp_main.c err = nfp_rtsym_readl(pf->cpp, pf->mbox, NFP_MBOX_CMD, &val); val 101 drivers/net/ethernet/netronome/nfp/nfp_main.c if (err || val) { val 103 drivers/net/ethernet/netronome/nfp/nfp_main.c cmd, val, err); val 118 drivers/net/ethernet/netronome/nfp/nfp_main.c err = nfp_rtsym_readl(pf->cpp, pf->mbox, NFP_MBOX_DATA_LEN, &val); val 130 drivers/net/ethernet/netronome/nfp/nfp_main.c err = nfp_rtsym_readl(pf->cpp, pf->mbox, NFP_MBOX_CMD, &val); val 133 drivers/net/ethernet/netronome/nfp/nfp_main.c if (!val) val 143 drivers/net/ethernet/netronome/nfp/nfp_main.c err = nfp_rtsym_readl(pf->cpp, pf->mbox, NFP_MBOX_DATA_LEN, &val); val 147 drivers/net/ethernet/netronome/nfp/nfp_main.c out_length = min_t(u32, val, min(out_length, max_data_sz)); val 154 drivers/net/ethernet/netronome/nfp/nfp_main.c err = nfp_rtsym_readl(pf->cpp, pf->mbox, NFP_MBOX_RET, &val); val 157 drivers/net/ethernet/netronome/nfp/nfp_main.c if (val) val 158 drivers/net/ethernet/netronome/nfp/nfp_main.c return -val; val 709 drivers/net/ethernet/netronome/nfp/nfp_net.h static inline void nn_writeb(struct nfp_net *nn, int off, u8 val) val 711 drivers/net/ethernet/netronome/nfp/nfp_net.h writeb(val, nn->dp.ctrl_bar + off); val 719 drivers/net/ethernet/netronome/nfp/nfp_net.h static inline void nn_writew(struct nfp_net *nn, int off, u16 val) val 721 drivers/net/ethernet/netronome/nfp/nfp_net.h writew(val, nn->dp.ctrl_bar + off); val 729 drivers/net/ethernet/netronome/nfp/nfp_net.h static inline void nn_writel(struct nfp_net *nn, int off, u32 val) val 731 drivers/net/ethernet/netronome/nfp/nfp_net.h writel(val, nn->dp.ctrl_bar + off); val 739 drivers/net/ethernet/netronome/nfp/nfp_net.h static inline void nn_writeq(struct nfp_net *nn, int off, u64 val) val 741 drivers/net/ethernet/netronome/nfp/nfp_net.h writeq(val, nn->dp.ctrl_bar + off); val 785 drivers/net/ethernet/netronome/nfp/nfp_net.h enum nfp_qcp_ptr ptr, u32 val) val 794 drivers/net/ethernet/netronome/nfp/nfp_net.h while (val > NFP_QCP_MAX_ADD) { val 796 drivers/net/ethernet/netronome/nfp/nfp_net.h val -= NFP_QCP_MAX_ADD; val 799 drivers/net/ethernet/netronome/nfp/nfp_net.h writel(val, q + off); val 810 drivers/net/ethernet/netronome/nfp/nfp_net.h static inline void nfp_qcp_rd_ptr_add(u8 __iomem *q, u32 val) val 812 drivers/net/ethernet/netronome/nfp/nfp_net.h _nfp_qcp_ptr_add(q, NFP_QCP_READ_PTR, val); val 823 drivers/net/ethernet/netronome/nfp/nfp_net.h static inline void nfp_qcp_wr_ptr_add(u8 __iomem *q, u32 val) val 825 drivers/net/ethernet/netronome/nfp/nfp_net.h _nfp_qcp_ptr_add(q, NFP_QCP_WRITE_PTR, val); val 831 drivers/net/ethernet/netronome/nfp/nfp_net.h u32 val; val 838 drivers/net/ethernet/netronome/nfp/nfp_net.h val = readl(q + off); val 841 drivers/net/ethernet/netronome/nfp/nfp_net.h return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask; val 843 drivers/net/ethernet/netronome/nfp/nfp_net.h return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask; val 1053 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c static int nfp_app_set_dump(struct net_device *netdev, struct ethtool_dump *val) val 1061 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c if (val->flag == NFP_DUMP_NSP_DIAG) { val 1062 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c app->pf->dump_flag = val->flag; val 1070 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c val->flag); val 1074 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c app->pf->dump_flag = val->flag; val 108 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c const char *key, *val, *end = hwinfo->data + size; val 111 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c key = val + strlen(val) + 1) { val 113 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c val = key + strlen(key) + 1; val 114 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c if (val >= end) { val 119 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c if (val + strlen(val) + 1 > end) { val 257 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c const char *key, *val, *end; val 265 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c key = val + strlen(val) + 1) { val 267 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c val = key + strlen(key) + 1; val 270 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c return val; val 32 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_mutex.c static u32 nfp_mutex_owner(u32 val) val 34 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_mutex.c return val >> 16; val 37 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_mutex.c static bool nfp_mutex_is_locked(u32 val) val 39 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_mutex.c return (val & 0xffff) == 0x000f; val 42 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_mutex.c static bool nfp_mutex_is_unlocked(u32 val) val 44 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_mutex.c return (val & 0xffff) == 0000; val 321 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c u64 mask, u64 val, u32 timeout_sec) val 333 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c if ((*reg & mask) == val) val 252 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h long *val); val 71 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_cmds.c long *val) val 89 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_cmds.c *val = le32_to_cpu(s.chip_temp); val 92 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_cmds.c *val = le32_to_cpu(s.assembly_power); val 95 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_cmds.c *val = le32_to_cpu(s.assembly_12v_power); val 98 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_cmds.c *val = le32_to_cpu(s.assembly_3v3_power); val 464 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c unsigned int val, const u64 ctrl_bit) val 481 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c if (val == (reg & mask) >> shift) val 485 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg |= (val << shift) & mask; val 495 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NFP_ETH_SET_BIT_CONFIG(nsp, raw_idx, mask, val, ctrl_bit) \ val 497 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c __BF_FIELD_CHECK(mask, 0ULL, val, "NFP_ETH_SET_BIT_CONFIG: "); \ val 499 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c val, ctrl_bit); \ val 448 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_rtsym.c u64 val; val 460 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_rtsym.c val = val32; val 463 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_rtsym.c err = nfp_rtsym_readq(rtbl->cpp, sym, 0, &val); val 479 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_rtsym.c return val; val 208 drivers/net/ethernet/ni/nixge.c static void nixge_dma_write_reg(struct nixge_priv *priv, off_t offset, u32 val) val 210 drivers/net/ethernet/ni/nixge.c writel(val, priv->dma_regs + offset); val 227 drivers/net/ethernet/ni/nixge.c static void nixge_ctrl_write_reg(struct nixge_priv *priv, off_t offset, u32 val) val 229 drivers/net/ethernet/ni/nixge.c writel(val, priv->ctrl_regs + offset); val 237 drivers/net/ethernet/ni/nixge.c #define nixge_ctrl_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \ val 238 drivers/net/ethernet/ni/nixge.c readl_poll_timeout((priv)->ctrl_regs + (addr), (val), (cond), \ val 241 drivers/net/ethernet/ni/nixge.c #define nixge_dma_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \ val 242 drivers/net/ethernet/ni/nixge.c readl_poll_timeout((priv)->dma_regs + (addr), (val), (cond), \ val 1144 drivers/net/ethernet/ni/nixge.c static int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) val 1172 drivers/net/ethernet/ni/nixge.c nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val); val 1185 drivers/net/ethernet/ni/nixge.c nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val); val 616 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h void pch_ch_control_write(struct pci_dev *pdev, u32 val); val 618 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h void pch_ch_event_write(struct pci_dev *pdev, u32 val); val 137 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c u32 hi, lo, val; val 146 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c val = pch_ch_event_read(pdev); val 148 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c if (!(val & RX_SNAPSHOT_LOCKED)) val 176 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c u32 cnt, val; val 191 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c val = pch_ch_event_read(pdev); val 192 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c if (val & TX_SNAPSHOT_LOCKED) val 196 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c if (!(val & TX_SNAPSHOT_LOCKED)) { val 436 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c int val; val 477 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c val = XsumRX; val 478 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c pch_gbe_validate_option(&val, &opt, adapter); val 479 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c if (!val) val 489 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c val = XsumTX; val 490 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c pch_gbe_validate_option(&val, &opt, adapter); val 491 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c if (!val) val 78 drivers/net/ethernet/pasemi/pasemi_mac.c static void write_iob_reg(unsigned int reg, unsigned int val) val 80 drivers/net/ethernet/pasemi/pasemi_mac.c pasemi_write_iob_reg(reg, val); val 89 drivers/net/ethernet/pasemi/pasemi_mac.c unsigned int val) val 91 drivers/net/ethernet/pasemi/pasemi_mac.c pasemi_write_mac_reg(mac->dma_if, reg, val); val 99 drivers/net/ethernet/pasemi/pasemi_mac.c static void write_dma_reg(unsigned int reg, unsigned int val) val 101 drivers/net/ethernet/pasemi/pasemi_mac.c pasemi_write_dma_reg(reg, val); val 268 drivers/net/ethernet/pasemi/pasemi_mac.c u32 val; val 291 drivers/net/ethernet/pasemi/pasemi_mac.c val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); val 292 drivers/net/ethernet/pasemi/pasemi_mac.c val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3); val 294 drivers/net/ethernet/pasemi/pasemi_mac.c write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); val 448 drivers/net/ethernet/pasemi/pasemi_mac.c u32 val; val 478 drivers/net/ethernet/pasemi/pasemi_mac.c val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); val 479 drivers/net/ethernet/pasemi/pasemi_mac.c val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); val 481 drivers/net/ethernet/pasemi/pasemi_mac.c write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); val 131 drivers/net/ethernet/pensando/ionic/ionic_regs.h static inline void ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val) val 133 drivers/net/ethernet/pensando/ionic/ionic_regs.h writeq(val, &db_page[qtype]); val 230 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define netxen_set_msg_peg_id(config_word, val) \ val 231 drivers/net/ethernet/qlogic/netxen/netxen_nic.h ((config_word) &= ~3, (config_word) |= val & 3) val 234 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define netxen_set_msg_count(config_word, val) \ val 235 drivers/net/ethernet/qlogic/netxen/netxen_nic.h ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) val 236 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define netxen_set_msg_ctxid(config_word, val) \ val 237 drivers/net/ethernet/qlogic/netxen/netxen_nic.h ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) val 238 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define netxen_set_msg_opcode(config_word, val) \ val 239 drivers/net/ethernet/qlogic/netxen/netxen_nic.h ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) val 1648 drivers/net/ethernet/qlogic/netxen/netxen_nic.h int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val); val 1687 drivers/net/ethernet/qlogic/netxen/netxen_nic.h int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val); val 1688 drivers/net/ethernet/qlogic/netxen/netxen_nic.h int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val); val 1692 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define NXWR32(adapter, off, val) \ val 1693 drivers/net/ethernet/qlogic/netxen/netxen_nic.h (adapter->crb_write(adapter, off, val)) val 1696 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define NXWRIO(adapter, addr, val) \ val 1697 drivers/net/ethernet/qlogic/netxen/netxen_nic.h (adapter->io_write(adapter, addr, val)) val 270 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c u32 cap, reg, val; val 316 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c val = le32_to_cpu(prq->rds_ring_offset) + val 318 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c prq->sds_ring_offset = cpu_to_le32(val); val 520 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val) val 535 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c if (val == NULL) val 538 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c *val = cmd.rsp.arg1; val 543 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val) val 550 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c cmd.req.arg2 = val; val 111 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c u32 val; val 113 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); val 114 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c if (val == NETXEN_PORT_MODE_802_3_AP) { val 134 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, P3_LINK_SPEED_REG(pcifn)); val 136 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c P3_LINK_SPEED_VAL(pcifn, val); val 356 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c u32 val, port; val 360 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, CRB_XG_STATE_P3); val 361 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val); val 362 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c return (val == XG_LINK_UP_P3) ? 0 : 1; val 364 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, CRB_XG_STATE); val 365 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = (val >> port*8) & 0xff; val 366 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c return (val == XG_LINK_UP) ? 0 : 1; val 416 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_validate_ringparam(u32 val, u32 min, u32 max, char *r_name) val 419 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c num_desc = max(val, min); val 423 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c if (val != num_desc) { val 425 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_nic_driver_name, r_name, num_desc, val); val 476 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c __u32 val; val 485 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port)); val 486 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c pause->rx_pause = netxen_gb_get_rx_flowctl(val); val 487 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL); val 490 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c pause->tx_pause = !(netxen_gb_get_gb0_mask(val)); val 493 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c pause->tx_pause = !(netxen_gb_get_gb1_mask(val)); val 496 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c pause->tx_pause = !(netxen_gb_get_gb2_mask(val)); val 500 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c pause->tx_pause = !(netxen_gb_get_gb3_mask(val)); val 507 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL); val 509 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c pause->tx_pause = !(netxen_xg_get_xg0_mask(val)); val 511 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c pause->tx_pause = !(netxen_xg_get_xg1_mask(val)); val 523 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c __u32 val; val 535 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port)); val 538 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_rx_flowctl(val); val 540 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_unset_rx_flowctl(val); val 543 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val); val 545 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL); val 549 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_unset_gb0_mask(val); val 551 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_set_gb0_mask(val); val 555 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_unset_gb1_mask(val); val 557 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_set_gb1_mask(val); val 561 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_unset_gb2_mask(val); val 563 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_set_gb2_mask(val); val 568 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_unset_gb3_mask(val); val 570 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_gb_set_gb3_mask(val); val 573 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c NXWR32(adapter, NETXEN_NIU_GB_PAUSE_CTL, val); val 577 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL); val 580 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_xg_unset_xg0_mask(val); val 582 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_xg_set_xg0_mask(val); val 585 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_xg_unset_xg1_mask(val); val 587 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_xg_set_xg1_mask(val); val 589 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c NXWR32(adapter, NETXEN_NIU_XG_PAUSE_CTL, val); val 835 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c netxen_set_dump(struct net_device *netdev, struct ethtool_dump *val) val 841 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c switch (val->flag) { val 873 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c if (val->flag == FW_DUMP_LEVELS[i]) { val 874 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c mdump->md_capture_mask = val->flag; val 882 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c "Invalid dump level: 0x%x\n", val->flag); val 696 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define XG_LINK_STATE_P3(pcifn,val) \ val 697 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK) val 790 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define nx_encode_temp(val, state) (((val) << 16) | (state)) val 436 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c u32 val = 0; val 443 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); val 444 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val |= (1UL << (28+port)); val 445 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); val 448 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = 0xffffff; val 449 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); val 450 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); val 453 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = MAC_HI(addr); val 454 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val); val 455 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = MAC_LO(addr); val 456 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val); val 465 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c u32 val = 0; val 472 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); val 473 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val &= ~(1UL << (28+port)); val 474 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); val 476 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = MAC_HI(addr); val 477 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); val 478 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = MAC_LO(addr); val 479 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); val 1292 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c u32 val; val 1295 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = readl(addr); val 1298 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c return val; val 1518 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c u64 val; val 1582 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = ((u64)temp << 32); val 1583 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val |= readl(mem_crb + data_lo); val 1584 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c *data = val; val 1667 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c u64 val; val 1717 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32; val 1718 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO); val 1719 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c *data = val; val 2117 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c u32 val; val 2135 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NX_RD_DUMP_REG(raddr, adapter->ahw.pci_base0, &val); val 2136 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c *data_buff++ = cpu_to_le32(val); val 2137 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c fl_addr += sizeof(val); val 72 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.h #define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \ val 73 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.h ((config_word) |= ((val) & 0x07)) val 87 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.h #define netxen_gb_mii_mgmt_reg_addr(config_word, val) \ val 88 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.h ((config_word) |= ((val) & 0x1F)) val 89 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.h #define netxen_gb_mii_mgmt_phy_addr(config_word, val) \ val 90 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.h ((config_word) |= (((val) & 0x1F) << 8)) val 216 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.h #define netxen_set_phy_speed(config_word, val) \ val 217 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.h ((config_word) |= ((val & 0x03) << 14)) val 418 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c int addr, val; val 461 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 || val 468 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c buf[i].data = val; val 539 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET); val 540 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f)); val 875 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c u32 val, version, major, minor, build; val 913 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c val = nx_get_fw_version(adapter); val 915 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c version = NETXEN_DECODE_VERSION(val); val 927 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL); val 928 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c fw_type = (val & 0x4) ? val 1074 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c __le32 val; val 1086 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]); val 1087 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c if ((__force u32)val != NETXEN_BDINFO_MAGIC) val 1094 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c val = nx_get_fw_version(adapter); val 1101 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c file_fw_ver = NETXEN_DECODE_VERSION(val); val 1111 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c val = nx_get_bios_version(adapter); val 1114 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c if ((__force u32)val != bios) { val 1318 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c u32 val = 0; val 1325 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c val = NXRD32(adapter, CRB_CMDPEG_STATE); val 1326 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c switch (val) { val 1350 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c u32 val = 0; val 1354 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c val = NXRD32(adapter, CRB_RCVPEG_STATE); val 1356 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c if (val == PHAN_PEG_RCV_INITIALIZED) val 1363 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c pr_err("Receive Peg initialization not complete, state: 0x%x.\n", val); val 304 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c u32 val, timeout; val 330 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = NXRD32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE); val 331 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c NXWR32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE, val | 0x1); val 335 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc)); val 340 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c } while (val == NETXEN_BDINFO_MAGIC); val 347 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c u32 val, data; val 349 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = adapter->ahw.board_type; val 350 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c if ((val == NETXEN_BRDTYPE_P3_HMEZ) || val 351 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c (val == NETXEN_BRDTYPE_P3_XG_LOM)) { val 824 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c int i, offset, val, err; val 833 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c err = netxen_rom_fast_read(adapter, offset, &val); val 839 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c ptr32[i] = cpu_to_le32(val); val 936 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c int val, err, first_boot; val 990 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = 0x7654; val 992 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val |= 0x0f000000; val 993 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); val 1004 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = (_NETXEN_NIC_LINUX_MAJOR << 16) val 1007 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c NXWR32(adapter, CRB_DRIVER_VERSION, val); val 1452 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c u32 val; val 1532 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = NXRD32(adapter, NX_CRB_DEV_REF_COUNT); val 1533 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c if (val != 0xffffffff && val != 0) { val 2208 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c u32 val, port, linkup; val 2213 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = NXRD32(adapter, CRB_XG_STATE_P3); val 2214 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val); val 2215 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c linkup = (val == XG_LINK_UP_P3); val 2217 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = NXRD32(adapter, CRB_XG_STATE); val 2218 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = (val >> port*8) & 0xff; val 2219 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c linkup = (val == XG_LINK_UP); val 2986 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c u32 val; val 2994 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c val = NXRD32(adapter, NETXEN_DIMM_CAPABILITY); val 2997 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c if (val & NETXEN_DIMM_VALID_FLAG) { val 3003 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c rows = NETXEN_DIMM_NUMROWS(val); val 3004 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c cols = NETXEN_DIMM_NUMCOLS(val); val 3005 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c ranks = NETXEN_DIMM_NUMRANKS(val); val 3006 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c banks = NETXEN_DIMM_NUMBANKS(val); val 3007 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c dw = NETXEN_DIMM_DATAWIDTH(val); val 3009 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c dimm.presence = (val & NETXEN_DIMM_PRESENT); val 3017 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c dimm.dimm_type = NETXEN_DIMM_TYPE(val); val 3032 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c if (val & NETXEN_DIMM_MEMTYPE_DDR2_SDRAM) val 3035 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c dimm.mem_type = NETXEN_DIMM_MEMTYPE(val); val 3037 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c if (val & NETXEN_DIMM_SIZE) { val 130 drivers/net/ethernet/qlogic/qed/qed.h #define D_TRINE(val, cond1, cond2, true1, true2, def) \ val 131 drivers/net/ethernet/qlogic/qed/qed.h (val == (cond1) ? true1 : \ val 132 drivers/net/ethernet/qlogic/qed/qed.h (val == (cond2) ? true2 : def)) val 961 drivers/net/ethernet/qlogic/qed/qed.h #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) val 962 drivers/net/ethernet/qlogic/qed/qed.h #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) val 964 drivers/net/ethernet/qlogic/qed/qed.h #define DOORBELL(cdev, db_addr, val) \ val 965 drivers/net/ethernet/qlogic/qed/qed.h writel((u32)val, (void __iomem *)((u8 __iomem *)\ val 162 drivers/net/ethernet/qlogic/qed/qed_cxt.c u32 val; val 448 drivers/net/ethernet/qlogic/qed/qed_cxt.c u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; val 501 drivers/net/ethernet/qlogic/qed/qed_cxt.c u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); val 523 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_cli->first.val = *p_line; val 527 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_cli->last.val = *p_line - 1; val 531 drivers/net/ethernet/qlogic/qed/qed_cxt.c client_id, p_cli->first.val, val 532 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_cli->last.val, p_blk->total_size, val 547 drivers/net/ethernet/qlogic/qed/qed_cxt.c cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / val 560 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_cli->first.val = 0; val 561 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_cli->last.val = 0; val 634 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_cli->first.val = curr_line; val 863 drivers/net/ethernet/qlogic/qed/qed_cxt.c ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); val 923 drivers/net/ethernet/qlogic/qed/qed_cxt.c psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); val 966 drivers/net/ethernet/qlogic/qed/qed_cxt.c u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val; val 970 drivers/net/ethernet/qlogic/qed/qed_cxt.c val = p_ent_phys + (j + 1) * sizeof(struct src_ent); val 971 drivers/net/ethernet/qlogic/qed/qed_cxt.c entries[j].next = cpu_to_be64(val); val 975 drivers/net/ethernet/qlogic/qed/qed_cxt.c val = (u64) p_mngr->t2[i + 1].p_phys; val 977 drivers/net/ethernet/qlogic/qed/qed_cxt.c val = 0; val 978 drivers/net/ethernet/qlogic/qed/qed_cxt.c entries[j].next = cpu_to_be64(val); val 1003 drivers/net/ethernet/qlogic/qed/qed_cxt.c size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1); val 1242 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; val 1400 drivers/net/ethernet/qlogic/qed/qed_cxt.c page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; val 1411 drivers/net/ethernet/qlogic/qed/qed_cxt.c page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; val 1477 drivers/net/ethernet/qlogic/qed/qed_cxt.c offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * val 1479 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; val 1486 drivers/net/ethernet/qlogic/qed/qed_cxt.c offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * val 1488 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; val 1604 drivers/net/ethernet/qlogic/qed/qed_cxt.c ilt_clients[i].first.val); val 1606 drivers/net/ethernet/qlogic/qed/qed_cxt.c ilt_clients[i].last.reg, ilt_clients[i].last.val); val 1609 drivers/net/ethernet/qlogic/qed/qed_cxt.c ilt_clients[i].p_size.val); val 1631 drivers/net/ethernet/qlogic/qed/qed_cxt.c blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); val 1645 drivers/net/ethernet/qlogic/qed/qed_cxt.c blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); val 1659 drivers/net/ethernet/qlogic/qed/qed_cxt.c blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); val 1691 drivers/net/ethernet/qlogic/qed/qed_cxt.c line = clients[i].first.val - p_mngr->pf_start_line; val 1693 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[i].first.val * ILT_ENTRY_IN_REGS; val 1695 drivers/net/ethernet/qlogic/qed/qed_cxt.c for (; line <= clients[i].last.val - p_mngr->pf_start_line; val 2046 drivers/net/ethernet/qlogic/qed/qed_cxt.c hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; val 2239 drivers/net/ethernet/qlogic/qed/qed_cxt.c p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - val 2286 drivers/net/ethernet/qlogic/qed/qed_cxt.c hw_p_size = p_cli->p_size.val; val 2419 drivers/net/ethernet/qlogic/qed/qed_cxt.c hw_p_size = p_cli->p_size.val; val 445 drivers/net/ethernet/qlogic/qed/qed_dcbx.c u8 val; val 458 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val = p_results->arr[DCBX_PROTOCOL_ROCE_V2].priority; val 459 drivers/net/ethernet/qlogic/qed/qed_dcbx.c p_prio->roce_v2 = val; val 500 drivers/net/ethernet/qlogic/qed/qed_dcbx.c u32 val; val 507 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val = QED_MFW_GET_FIELD(p_tbl[i].entry, val 509 drivers/net/ethernet/qlogic/qed/qed_dcbx.c entry->sf_ieee = val ? val 663 drivers/net/ethernet/qlogic/qed/qed_dcbx.c bool val; val 683 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val = !!(QED_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) == val 685 drivers/net/ethernet/qlogic/qed/qed_dcbx.c p_operational->ieee = val; val 686 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val = !!(QED_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) == val 688 drivers/net/ethernet/qlogic/qed/qed_dcbx.c p_operational->cee = val; val 690 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val = !!(QED_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) == val 692 drivers/net/ethernet/qlogic/qed/qed_dcbx.c p_operational->local = val; val 926 drivers/net/ethernet/qlogic/qed/qed_dcbx.c u16 val; val 932 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val = (0x1 << p_data->arr[DCBX_PROTOCOL_ROCE].tc) | val 934 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val <<= NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT; val 935 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val |= NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN; val 936 drivers/net/ethernet/qlogic/qed/qed_dcbx.c qed_wr(p_hwfn, p_ptt, NIG_REG_TX_EDPM_CTRL, val); val 1084 drivers/net/ethernet/qlogic/qed/qed_dcbx.c u32 val; val 1114 drivers/net/ethernet/qlogic/qed/qed_dcbx.c val = (((u32)p_params->ets_pri_tc_tbl[i]) << ((7 - i) * 4)); val 1115 drivers/net/ethernet/qlogic/qed/qed_dcbx.c p_ets->pri_tc_tbl[0] |= val; val 337 drivers/net/ethernet/qlogic/qed/qed_debug.c #define SET_VAR_FIELD(var, type, field, val) \ val 342 drivers/net/ethernet/qlogic/qed/qed_debug.c (val) << FIELD_DWORD_SHIFT(type, field); \ val 1761 drivers/net/ethernet/qlogic/qed/qed_debug.c enum dbg_grc_params grc_param, u32 val) val 1765 drivers/net/ethernet/qlogic/qed/qed_debug.c dev_data->grc.param_val[grc_param] = val; val 5133 drivers/net/ethernet/qlogic/qed/qed_debug.c enum dbg_grc_params grc_param, u32 val) val 5139 drivers/net/ethernet/qlogic/qed/qed_debug.c "dbg_grc_config: paramId = %d, val = %d\n", grc_param, val); val 5152 drivers/net/ethernet/qlogic/qed/qed_debug.c if (val < s_grc_param_defs[grc_param].min || val 5153 drivers/net/ethernet/qlogic/qed/qed_debug.c val > s_grc_param_defs[grc_param].max) val 5162 drivers/net/ethernet/qlogic/qed/qed_debug.c if (!val) val 5188 drivers/net/ethernet/qlogic/qed/qed_debug.c qed_grc_set_param(p_hwfn, grc_param, val); val 6219 drivers/net/ethernet/qlogic/qed/qed_debug.c u32 val = 0; val 6221 drivers/net/ethernet/qlogic/qed/qed_debug.c val_ptr = (u8 *)&val; val 6231 drivers/net/ethernet/qlogic/qed/qed_debug.c return val; val 7971 drivers/net/ethernet/qlogic/qed/qed_debug.c __be32 val; val 7991 drivers/net/ethernet/qlogic/qed/qed_debug.c val = cpu_to_be32(*(u32 *)(buffer + i)); val 7992 drivers/net/ethernet/qlogic/qed/qed_debug.c *(u32 *)(buffer + i) = val; val 768 drivers/net/ethernet/qlogic/qed/qed_dev.c u32 addr, val, eng_sel; val 799 drivers/net/ethernet/qlogic/qed/qed_dev.c val = qed_rd(p_hwfn, p_ptt, addr); val 800 drivers/net/ethernet/qlogic/qed/qed_dev.c SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel); val 801 drivers/net/ethernet/qlogic/qed/qed_dev.c qed_wr(p_hwfn, p_ptt, addr, val); val 816 drivers/net/ethernet/qlogic/qed/qed_dev.c u32 addr, val, eng_sel; val 850 drivers/net/ethernet/qlogic/qed/qed_dev.c val = qed_rd(p_hwfn, p_ptt, addr); val 851 drivers/net/ethernet/qlogic/qed/qed_dev.c SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel); val 852 drivers/net/ethernet/qlogic/qed/qed_dev.c qed_wr(p_hwfn, p_ptt, addr, val); val 1293 drivers/net/ethernet/qlogic/qed/qed_dev.c u32 val; val 1298 drivers/net/ethernet/qlogic/qed/qed_dev.c val = qed_rd(p_hwfn, p_ptt, bar_reg); val 1299 drivers/net/ethernet/qlogic/qed/qed_dev.c if (val) val 1300 drivers/net/ethernet/qlogic/qed/qed_dev.c return 1 << (val + 15); val 2546 drivers/net/ethernet/qlogic/qed/qed_dev.c u32 val, wr_mbs, cache_line_size; val 2548 drivers/net/ethernet/qlogic/qed/qed_dev.c val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); val 2549 drivers/net/ethernet/qlogic/qed/qed_dev.c switch (val) { val 2562 drivers/net/ethernet/qlogic/qed/qed_dev.c val); val 2569 drivers/net/ethernet/qlogic/qed/qed_dev.c val = 0; val 2572 drivers/net/ethernet/qlogic/qed/qed_dev.c val = 1; val 2575 drivers/net/ethernet/qlogic/qed/qed_dev.c val = 2; val 2578 drivers/net/ethernet/qlogic/qed/qed_dev.c val = 3; val 2591 drivers/net/ethernet/qlogic/qed/qed_dev.c STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); val 2592 drivers/net/ethernet/qlogic/qed/qed_dev.c if (val > 0) { val 2593 drivers/net/ethernet/qlogic/qed/qed_dev.c STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); val 2594 drivers/net/ethernet/qlogic/qed/qed_dev.c STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); val 2932 drivers/net/ethernet/qlogic/qed/qed_dev.c u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0; val 2939 drivers/net/ethernet/qlogic/qed/qed_dev.c val = qed_rd(p_hwfn, p_ptt, val 2941 drivers/net/ethernet/qlogic/qed/qed_dev.c if (val == set_val) val 2947 drivers/net/ethernet/qlogic/qed/qed_dev.c if (val != set_val) { val 2284 drivers/net/ethernet/qlogic/qed/qed_hsi.h u8 val; /* Event ID value */ val 3041 drivers/net/ethernet/qlogic/qed/qed_hsi.h enum dbg_grc_params grc_param, u32 val); val 10418 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le16 val; val 227 drivers/net/ethernet/qlogic/qed/qed_hw.c u32 hw_addr, u32 val) val 231 drivers/net/ethernet/qlogic/qed/qed_hw.c REG_WR(p_hwfn, bar_addr, val); val 234 drivers/net/ethernet/qlogic/qed/qed_hw.c bar_addr, hw_addr, val); val 242 drivers/net/ethernet/qlogic/qed/qed_hw.c u32 val = REG_RD(p_hwfn, bar_addr); val 246 drivers/net/ethernet/qlogic/qed/qed_hw.c bar_addr, hw_addr, val); val 248 drivers/net/ethernet/qlogic/qed/qed_hw.c return val; val 850 drivers/net/ethernet/qlogic/qed/qed_hw.c u32 size = PAGE_SIZE / 2, val; val 869 drivers/net/ethernet/qlogic/qed/qed_hw.c val = (u32)(uintptr_t)p_tmp; val 870 drivers/net/ethernet/qlogic/qed/qed_hw.c *p_tmp = val; val 896 drivers/net/ethernet/qlogic/qed/qed_hw.c val = (u32)(uintptr_t)p_tmp - size; val 898 drivers/net/ethernet/qlogic/qed/qed_hw.c if (*p_tmp != val) { val 903 drivers/net/ethernet/qlogic/qed/qed_hw.c p_tmp, *p_tmp, val); val 165 drivers/net/ethernet/qlogic/qed/qed_hw.h u32 val); val 86 drivers/net/ethernet/qlogic/qed/qed_init_ops.c void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, u32 rt_offset, u32 val) val 88 drivers/net/ethernet/qlogic/qed/qed_init_ops.c p_hwfn->rt_data.init_val[rt_offset] = val; val 351 drivers/net/ethernet/qlogic/qed/qed_init_ops.c static inline bool comp_eq(u32 val, u32 expected_val) val 353 drivers/net/ethernet/qlogic/qed/qed_init_ops.c return val == expected_val; val 356 drivers/net/ethernet/qlogic/qed/qed_init_ops.c static inline bool comp_and(u32 val, u32 expected_val) val 358 drivers/net/ethernet/qlogic/qed/qed_init_ops.c return (val & expected_val) == expected_val; val 361 drivers/net/ethernet/qlogic/qed/qed_init_ops.c static inline bool comp_or(u32 val, u32 expected_val) val 363 drivers/net/ethernet/qlogic/qed/qed_init_ops.c return (val | expected_val) > 0; val 370 drivers/net/ethernet/qlogic/qed/qed_init_ops.c bool (*comp_check)(u32 val, u32 expected_val); val 371 drivers/net/ethernet/qlogic/qed/qed_init_ops.c u32 delay = QED_INIT_POLL_PERIOD_US, val; val 380 drivers/net/ethernet/qlogic/qed/qed_init_ops.c val = qed_rd(p_hwfn, p_ptt, addr); val 403 drivers/net/ethernet/qlogic/qed/qed_init_ops.c i < QED_INIT_MAX_POLL_COUNT && !comp_check(val, data); val 406 drivers/net/ethernet/qlogic/qed/qed_init_ops.c val = qed_rd(p_hwfn, p_ptt, addr); val 413 drivers/net/ethernet/qlogic/qed/qed_init_ops.c val, le32_to_cpu(cmd->op_data)); val 101 drivers/net/ethernet/qlogic/qed/qed_init_ops.h u32 val); val 103 drivers/net/ethernet/qlogic/qed/qed_init_ops.h #define STORE_RT_REG(hwfn, offset, val) \ val 104 drivers/net/ethernet/qlogic/qed/qed_init_ops.h qed_init_store_rt_reg(hwfn, offset, val) val 106 drivers/net/ethernet/qlogic/qed/qed_init_ops.h #define OVERWRITE_RT_REG(hwfn, offset, val) \ val 107 drivers/net/ethernet/qlogic/qed/qed_init_ops.h qed_init_store_rt_reg(hwfn, offset, val) val 120 drivers/net/ethernet/qlogic/qed/qed_init_ops.h u32 *val, val 123 drivers/net/ethernet/qlogic/qed/qed_init_ops.h #define STORE_RT_REG_AGG(hwfn, offset, val) \ val 124 drivers/net/ethernet/qlogic/qed/qed_init_ops.h qed_init_store_rt_agg(hwfn, offset, (u32 *)&val, sizeof(val)) val 910 drivers/net/ethernet/qlogic/qed/qed_int.c u32 val; val 936 drivers/net/ethernet/qlogic/qed/qed_int.c val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); val 937 drivers/net/ethernet/qlogic/qed/qed_int.c qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); val 957 drivers/net/ethernet/qlogic/qed/qed_int.c u32 block_id = p_aeu->block_index, mask, val; val 977 drivers/net/ethernet/qlogic/qed/qed_int.c val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); val 978 drivers/net/ethernet/qlogic/qed/qed_int.c qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); val 1887 drivers/net/ethernet/qlogic/qed/qed_int.c u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; val 1915 drivers/net/ethernet/qlogic/qed/qed_int.c val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); val 1917 drivers/net/ethernet/qlogic/qed/qed_int.c if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) val 1926 drivers/net/ethernet/qlogic/qed/qed_int.c val, igu_sb_id); val 1952 drivers/net/ethernet/qlogic/qed/qed_int.c u32 val; val 1954 drivers/net/ethernet/qlogic/qed/qed_int.c val = qed_rd(p_hwfn, p_ptt, val 1957 drivers/net/ethernet/qlogic/qed/qed_int.c if (val & BIT((igu_sb_id % 32))) val 1980 drivers/net/ethernet/qlogic/qed/qed_int.c u32 val = 0; val 1982 drivers/net/ethernet/qlogic/qed/qed_int.c val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); val 1983 drivers/net/ethernet/qlogic/qed/qed_int.c val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; val 1984 drivers/net/ethernet/qlogic/qed/qed_int.c val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; val 1985 drivers/net/ethernet/qlogic/qed/qed_int.c qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); val 2014 drivers/net/ethernet/qlogic/qed/qed_int.c u32 val, rval; val 2077 drivers/net/ethernet/qlogic/qed/qed_int.c val = 0; val 2112 drivers/net/ethernet/qlogic/qed/qed_int.c SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, val 2114 drivers/net/ethernet/qlogic/qed/qed_int.c SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); val 2115 drivers/net/ethernet/qlogic/qed/qed_int.c SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, val 2119 drivers/net/ethernet/qlogic/qed/qed_int.c SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); val 2124 drivers/net/ethernet/qlogic/qed/qed_int.c if (rval != val) { val 2127 drivers/net/ethernet/qlogic/qed/qed_int.c sizeof(u32) * igu_sb_id, val); val 2135 drivers/net/ethernet/qlogic/qed/qed_int.c p_block->vector_number, rval, val); val 2145 drivers/net/ethernet/qlogic/qed/qed_int.c u32 val = qed_rd(p_hwfn, p_ptt, val 2152 drivers/net/ethernet/qlogic/qed/qed_int.c p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); val 2153 drivers/net/ethernet/qlogic/qed/qed_int.c p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); val 2154 drivers/net/ethernet/qlogic/qed/qed_int.c p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); val 176 drivers/net/ethernet/qlogic/qed/qed_iscsi.c u16 val; val 211 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->half_way_close_timeout; val 212 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_init->half_way_close_timeout = cpu_to_le16(val); val 220 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->num_tasks; val 221 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_init->func_params.num_tasks = cpu_to_le16(val); val 227 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->cq_num_entries; val 228 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_queue->cq_num_entries = cpu_to_le16(val); val 229 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->cmdq_num_entries; val 230 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_queue->cmdq_num_entries = cpu_to_le16(val); val 238 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = qed_get_igu_sb_id(p_hwfn, i); val 239 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_queue->cq_cmdq_sb_num_arr[i] = cpu_to_le16(val); val 248 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->bdq_xoff_threshold[BDQ_ID_RQ]; val 249 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_queue->bdq_xoff_threshold[BDQ_ID_RQ] = cpu_to_le16(val); val 250 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->bdq_xon_threshold[BDQ_ID_RQ]; val 251 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_queue->bdq_xon_threshold[BDQ_ID_RQ] = cpu_to_le16(val); val 257 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->bdq_xoff_threshold[BDQ_ID_IMM_DATA]; val 258 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_queue->bdq_xoff_threshold[BDQ_ID_IMM_DATA] = cpu_to_le16(val); val 259 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->bdq_xon_threshold[BDQ_ID_IMM_DATA]; val 260 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_queue->bdq_xon_threshold[BDQ_ID_IMM_DATA] = cpu_to_le16(val); val 261 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->rq_buffer_size; val 262 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_queue->rq_buffer_size = cpu_to_le16(val); val 276 drivers/net/ethernet/qlogic/qed/qed_iscsi.c val = p_params->tx_sws_timer; val 277 drivers/net/ethernet/qlogic/qed/qed_iscsi.c p_ramrod->tcp_init.tx_sws_timer = cpu_to_le16(val); val 688 drivers/net/ethernet/qlogic/qed/qed_l2.c u8 abs_vport_id = 0, val; val 722 drivers/net/ethernet/qlogic/qed/qed_l2.c val = p_params->update_accept_any_vlan_flg; val 723 drivers/net/ethernet/qlogic/qed/qed_l2.c p_cmn->update_accept_any_vlan_flg = val; val 726 drivers/net/ethernet/qlogic/qed/qed_l2.c val = p_params->update_inner_vlan_removal_flg; val 727 drivers/net/ethernet/qlogic/qed/qed_l2.c p_cmn->update_inner_vlan_removal_en_flg = val; val 730 drivers/net/ethernet/qlogic/qed/qed_l2.c val = p_params->update_default_vlan_enable_flg; val 731 drivers/net/ethernet/qlogic/qed/qed_l2.c p_cmn->update_default_vlan_en_flg = val; val 742 drivers/net/ethernet/qlogic/qed/qed_l2.c val = p_params->update_anti_spoofing_en_flg; val 743 drivers/net/ethernet/qlogic/qed/qed_l2.c p_ramrod->common.update_anti_spoofing_en_flg = val; val 366 drivers/net/ethernet/qlogic/qed/qed_main.c ctx->val.vbool = cdev->iwarp_cmt; val 379 drivers/net/ethernet/qlogic/qed/qed_main.c cdev->iwarp_cmt = ctx->val.vbool; val 1974 drivers/net/ethernet/qlogic/qed/qed_main.c u32 val; val 1993 drivers/net/ethernet/qlogic/qed/qed_main.c val = cpu_to_be32(*(u32 *)&buf[j]); val 1994 drivers/net/ethernet/qlogic/qed/qed_main.c *(u32 *)&buf[j] = val; val 2618 drivers/net/ethernet/qlogic/qed/qed_main.c static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val) val 2631 drivers/net/ethernet/qlogic/qed/qed_main.c rc = qed_dbg_grc_config(hwfn, ptt, cfg_id, val); val 1250 drivers/net/ethernet/qlogic/qed/qed_mcp.c u32 eee_status, val; val 1259 drivers/net/ethernet/qlogic/qed/qed_mcp.c val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; val 1260 drivers/net/ethernet/qlogic/qed/qed_mcp.c if (val & EEE_1G_ADV) val 1262 drivers/net/ethernet/qlogic/qed/qed_mcp.c if (val & EEE_10G_ADV) val 1264 drivers/net/ethernet/qlogic/qed/qed_mcp.c val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; val 1265 drivers/net/ethernet/qlogic/qed/qed_mcp.c if (val & EEE_1G_ADV) val 1267 drivers/net/ethernet/qlogic/qed/qed_mcp.c if (val & EEE_10G_ADV) val 1708 drivers/net/ethernet/qlogic/qed/qed_mcp.c u32 port_cfg, val; val 1716 drivers/net/ethernet/qlogic/qed/qed_mcp.c val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> val 1718 drivers/net/ethernet/qlogic/qed/qed_mcp.c if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) val 1721 drivers/net/ethernet/qlogic/qed/qed_mcp.c val, MFW_PORT(p_hwfn)); val 1723 drivers/net/ethernet/qlogic/qed/qed_mcp.c val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; val 1724 drivers/net/ethernet/qlogic/qed/qed_mcp.c if (val == OEM_CFG_SCHED_TYPE_ETS) { val 1726 drivers/net/ethernet/qlogic/qed/qed_mcp.c } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { val 1732 drivers/net/ethernet/qlogic/qed/qed_mcp.c val, MFW_PORT(p_hwfn)); val 1736 drivers/net/ethernet/qlogic/qed/qed_mcp.c val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> val 1738 drivers/net/ethernet/qlogic/qed/qed_mcp.c p_hwfn->ufp_info.tc = (u8)val; val 1739 drivers/net/ethernet/qlogic/qed/qed_mcp.c val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> val 1741 drivers/net/ethernet/qlogic/qed/qed_mcp.c if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { val 1743 drivers/net/ethernet/qlogic/qed/qed_mcp.c } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { val 1749 drivers/net/ethernet/qlogic/qed/qed_mcp.c val, MFW_PORT(p_hwfn)); val 1862 drivers/net/ethernet/qlogic/qed/qed_mcp.c __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); val 1869 drivers/net/ethernet/qlogic/qed/qed_mcp.c (__force u32)val); val 2490 drivers/net/ethernet/qlogic/qed/qed_mcp.c __be32 val; val 2497 drivers/net/ethernet/qlogic/qed/qed_mcp.c val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); val 2498 drivers/net/ethernet/qlogic/qed/qed_mcp.c *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; val 1244 drivers/net/ethernet/qlogic/qed/qed_mng_tlv.c u32 addr, size, offset, resp, param, val, global_offsize, global_addr; val 1276 drivers/net/ethernet/qlogic/qed/qed_mng_tlv.c val = qed_rd(p_hwfn, p_ptt, addr + offset); val 1277 drivers/net/ethernet/qlogic/qed/qed_mng_tlv.c val = be32_to_cpu(val); val 1278 drivers/net/ethernet/qlogic/qed/qed_mng_tlv.c memcpy(&p_mfw_buf[offset], &val, sizeof(u32)); val 1325 drivers/net/ethernet/qlogic/qed/qed_mng_tlv.c memcpy(&val, &p_mfw_buf[offset], sizeof(u32)); val 1326 drivers/net/ethernet/qlogic/qed/qed_mng_tlv.c val = cpu_to_be32(val); val 1327 drivers/net/ethernet/qlogic/qed/qed_mng_tlv.c qed_wr(p_hwfn, p_ptt, addr + offset, val); val 131 drivers/net/ethernet/qlogic/qed/qed_ptp.c u32 val; val 134 drivers/net/ethernet/qlogic/qed/qed_ptp.c val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID); val 135 drivers/net/ethernet/qlogic/qed/qed_ptp.c if (!(val & QED_TIMESTAMP_MASK)) { val 136 drivers/net/ethernet/qlogic/qed/qed_ptp.c DP_INFO(p_hwfn, "Invalid Rx timestamp, buf_seqid = %d\n", val); val 140 drivers/net/ethernet/qlogic/qed/qed_ptp.c val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_LSB); val 143 drivers/net/ethernet/qlogic/qed/qed_ptp.c *timestamp |= val; val 157 drivers/net/ethernet/qlogic/qed/qed_ptp.c u32 val; val 160 drivers/net/ethernet/qlogic/qed/qed_ptp.c val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID); val 161 drivers/net/ethernet/qlogic/qed/qed_ptp.c if (!(val & QED_TIMESTAMP_MASK)) { val 163 drivers/net/ethernet/qlogic/qed/qed_ptp.c "Invalid Tx timestamp, buf_seqid = %08x\n", val); val 167 drivers/net/ethernet/qlogic/qed/qed_ptp.c val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_LSB); val 170 drivers/net/ethernet/qlogic/qed/qed_ptp.c *timestamp |= val; val 280 drivers/net/ethernet/qlogic/qed/qed_ptp.c s64 best_val = 0, val, best_period = 0, period, approx_dev, dif, dif2; val 297 drivers/net/ethernet/qlogic/qed/qed_ptp.c for (val = 7; val > 0; val--) { val 298 drivers/net/ethernet/qlogic/qed/qed_ptp.c period = div_s64(val * 1000000000, ppb); val 308 drivers/net/ethernet/qlogic/qed/qed_ptp.c dif = ppb * approx_dev - val * 1000000000; val 326 drivers/net/ethernet/qlogic/qed/qed_ptp.c best_val = val; val 1828 drivers/net/ethernet/qlogic/qed/qed_rdma.c u32 val; val 1830 drivers/net/ethernet/qlogic/qed/qed_rdma.c val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1; val 1832 drivers/net/ethernet/qlogic/qed/qed_rdma.c qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val); val 1835 drivers/net/ethernet/qlogic/qed/qed_rdma.c val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm); val 1134 drivers/net/ethernet/qlogic/qed/qed_roce.c u8 val; val 1140 drivers/net/ethernet/qlogic/qed/qed_roce.c val = qed_rdma_allocated_qps(p_hwfn) ? true : false; val 1141 drivers/net/ethernet/qlogic/qed/qed_roce.c p_hwfn->dcbx_no_edpm = (u8)val; val 119 drivers/net/ethernet/qlogic/qed/qed_selftest.c __be32 val; val 178 drivers/net/ethernet/qlogic/qed/qed_selftest.c val = cpu_to_be32(*(u32 *)&buf[j]); val 179 drivers/net/ethernet/qlogic/qed/qed_selftest.c *(u32 *)&buf[j] = (__force u32)val; val 863 drivers/net/ethernet/qlogic/qed/qed_sriov.c u32 reg_addr, val; val 872 drivers/net/ethernet/qlogic/qed/qed_sriov.c val = enable ? (vf->abs_vf_id | BIT(8)) : 0; val 873 drivers/net/ethernet/qlogic/qed/qed_sriov.c qed_wr(p_hwfn, p_ptt, reg_addr, val); val 897 drivers/net/ethernet/qlogic/qed/qed_sriov.c u32 val = 0; val 903 drivers/net/ethernet/qlogic/qed/qed_sriov.c SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, vf->abs_vf_id); val 904 drivers/net/ethernet/qlogic/qed/qed_sriov.c SET_FIELD(val, IGU_MAPPING_LINE_VALID, 1); val 905 drivers/net/ethernet/qlogic/qed/qed_sriov.c SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, 0); val 911 drivers/net/ethernet/qlogic/qed/qed_sriov.c SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, qid); val 915 drivers/net/ethernet/qlogic/qed/qed_sriov.c sizeof(u32) * p_block->igu_sb_id, val); val 938 drivers/net/ethernet/qlogic/qed/qed_sriov.c u32 addr, val; val 945 drivers/net/ethernet/qlogic/qed/qed_sriov.c val = qed_rd(p_hwfn, p_ptt, addr); val 946 drivers/net/ethernet/qlogic/qed/qed_sriov.c SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0); val 947 drivers/net/ethernet/qlogic/qed/qed_sriov.c qed_wr(p_hwfn, p_ptt, addr, val); val 1403 drivers/net/ethernet/qlogic/qed/qed_sriov.c u32 val = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_BAR1_SIZE); val 1405 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (val) val 1406 drivers/net/ethernet/qlogic/qed/qed_sriov.c return val + 11; val 1705 drivers/net/ethernet/qlogic/qed/qed_sriov.c struct qed_vf_info *p_vf, bool val) val 1710 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (val == p_vf->spoof_chk) { val 1712 drivers/net/ethernet/qlogic/qed/qed_sriov.c "Spoofchk value[%d] is already configured\n", val); val 1720 drivers/net/ethernet/qlogic/qed/qed_sriov.c params.anti_spoofing_en = val; val 1724 drivers/net/ethernet/qlogic/qed/qed_sriov.c p_vf->spoof_chk = val; val 1727 drivers/net/ethernet/qlogic/qed/qed_sriov.c "Spoofchk val[%d] configured\n", val); val 1731 drivers/net/ethernet/qlogic/qed/qed_sriov.c val, p_vf->relative_vf_id); val 3580 drivers/net/ethernet/qlogic/qed/qed_sriov.c u32 val; val 3585 drivers/net/ethernet/qlogic/qed/qed_sriov.c val = qed_rd(p_hwfn, p_ptt, DORQ_REG_VF_USAGE_CNT); val 3586 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (!val) val 3595 drivers/net/ethernet/qlogic/qed/qed_sriov.c p_vf->abs_vf_id, val); val 4281 drivers/net/ethernet/qlogic/qed/qed_sriov.c static int qed_iov_spoofchk_set(struct qed_hwfn *p_hwfn, int vfid, bool val) val 4298 drivers/net/ethernet/qlogic/qed/qed_sriov.c vf->req_spoofchk_val = val; val 4303 drivers/net/ethernet/qlogic/qed/qed_sriov.c rc = __qed_iov_spoofchk_set(p_hwfn, vf, val); val 4355 drivers/net/ethernet/qlogic/qed/qed_sriov.c struct qed_ptt *p_ptt, int vfid, int val) val 4372 drivers/net/ethernet/qlogic/qed/qed_sriov.c return qed_init_vport_rl(p_hwfn, p_ptt, abs_vp_id, (u32)val, val 4827 drivers/net/ethernet/qlogic/qed/qed_sriov.c static int qed_spoof_configure(struct qed_dev *cdev, int vfid, bool val) val 4834 drivers/net/ethernet/qlogic/qed/qed_sriov.c rc = qed_iov_spoofchk_set(p_hwfn, vfid, val); val 631 drivers/net/ethernet/qlogic/qed/qed_vf.c u8 tunn_cls, enum qed_tunn_mode val) val 633 drivers/net/ethernet/qlogic/qed/qed_vf.c if (feature_mask & BIT(val)) { val 1497 drivers/net/ethernet/qlogic/qede/qede_ethtool.c u16 val; val 1518 drivers/net/ethernet/qlogic/qede/qede_ethtool.c val = 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT; val 1519 drivers/net/ethernet/qlogic/qede/qede_ethtool.c first_bd->data.bd_flags.bitfields = val; val 1520 drivers/net/ethernet/qlogic/qede/qede_ethtool.c val = skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK; val 1521 drivers/net/ethernet/qlogic/qede/qede_ethtool.c val = val << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT; val 1522 drivers/net/ethernet/qlogic/qede/qede_ethtool.c first_bd->data.bitfields |= cpu_to_le16(val); val 1537 drivers/net/ethernet/qlogic/qede/qede_ethtool.c val = qed_chain_get_prod_idx(&txq->tx_pbl); val 1538 drivers/net/ethernet/qlogic/qede/qede_ethtool.c txq->tx_db.data.bd_prod = cpu_to_le16(val); val 1774 drivers/net/ethernet/qlogic/qede/qede_ethtool.c u32 val; val 1778 drivers/net/ethernet/qlogic/qede/qede_ethtool.c val = *(u32 *)data; val 1779 drivers/net/ethernet/qlogic/qede/qede_ethtool.c if (val < QEDE_MIN_PKT_LEN || val > QEDE_RX_HDR_SIZE) { val 1978 drivers/net/ethernet/qlogic/qede/qede_ethtool.c static int qede_set_dump(struct net_device *dev, struct ethtool_dump *val) val 1984 drivers/net/ethernet/qlogic/qede/qede_ethtool.c if (val->flag > QEDE_DUMP_CMD_MAX) { val 1985 drivers/net/ethernet/qlogic/qede/qede_ethtool.c DP_ERR(edev, "Invalid command %d\n", val->flag); val 1988 drivers/net/ethernet/qlogic/qede/qede_ethtool.c edev->dump_info.cmd = val->flag; val 2000 drivers/net/ethernet/qlogic/qede/qede_ethtool.c edev->dump_info.args[edev->dump_info.num_args] = val->flag; val 2005 drivers/net/ethernet/qlogic/qede/qede_ethtool.c val->flag, 1); val 608 drivers/net/ethernet/qlogic/qede/qede_filter.c u16 indir_val, val; val 610 drivers/net/ethernet/qlogic/qede/qede_filter.c val = QEDE_RSS_COUNT(edev); val 611 drivers/net/ethernet/qlogic/qede/qede_filter.c indir_val = ethtool_rxfh_indir_default(i, val); val 336 drivers/net/ethernet/qlogic/qede/qede_fp.c u16 val; val 349 drivers/net/ethernet/qlogic/qede/qede_fp.c val = (length & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) << val 352 drivers/net/ethernet/qlogic/qede/qede_fp.c first_bd->data.bitfields |= cpu_to_le16(val); val 1438 drivers/net/ethernet/qlogic/qede/qede_fp.c u16 txq_index, val = 0; val 1528 drivers/net/ethernet/qlogic/qede/qede_fp.c val |= (1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT); val 1536 drivers/net/ethernet/qlogic/qede/qede_fp.c val ^= (1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT); val 1600 drivers/net/ethernet/qlogic/qede/qede_fp.c val |= ((skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) << val 1604 drivers/net/ethernet/qlogic/qede/qede_fp.c first_bd->data.bitfields = cpu_to_le16(val); val 479 drivers/net/ethernet/qlogic/qede/qede_main.c static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val) val 486 drivers/net/ethernet/qlogic/qede/qede_main.c return edev->ops->iov->set_spoof(edev->cdev, vfidx, val); val 2079 drivers/net/ethernet/qlogic/qede/qede_main.c __le16 *val; val 2107 drivers/net/ethernet/qlogic/qede/qede_main.c val = &fp->sb_info->sb_virt->pi_array[RX_PI]; val 2108 drivers/net/ethernet/qlogic/qede/qede_main.c rxq->hw_cons_ptr = val; val 1553 drivers/net/ethernet/qlogic/qlcnic/qlcnic.h #define QLCWR32(adapter, off, val) \ val 1554 drivers/net/ethernet/qlogic/qlcnic/qlcnic.h adapter->ahw->hw_ops->write_reg(adapter, off, val) val 288 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val; val 293 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = readl(base); val 294 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if (val != addr) val 595 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val; val 605 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector; val 606 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c err = request_irq(val, handler, flags, "qlcnic-MB", adapter); val 614 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = adapter->msix_entries[0].vector; val 615 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c err = request_irq(val, handler, flags, "qlcnic", adapter); val 632 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT); val 633 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c adapter->ahw->pci_func = (val >> 24) & 0xff; val 639 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val, limit = 0; val 645 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = readl(addr); val 646 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if (val) { val 661 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val; val 665 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = readl(addr); val 748 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val; val 751 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8); val 753 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = BIT_2; val 755 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val); val 2553 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val, temp, type; val 2568 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = type | (adapter->ahw->intr_tbl[i].type << 4); val 2570 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val |= (adapter->ahw->intr_tbl[i].id << 16); val 2571 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c cmd.req.arg[index++] = val; val 2582 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = cmd.rsp.arg[index]; val 2583 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if (LSB(val)) { val 2590 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c adapter->ahw->intr_tbl[i].id = MSW(val); val 2978 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val, id; val 2980 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); val 2983 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) { val 2984 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = val & ~0x3F; val 2985 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = val | ((adapter->portnum << 2) | val 2987 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); val 2991 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); val 2992 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c id = ((val >> 2) & 0xF); val 2994 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK; val 2995 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS; val 2996 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); val 3000 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = val & ~0x3F; val 3001 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); val 3018 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0; val 3033 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); val 3034 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if (val == temp) { val 3035 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c id = val & 0xFF; val 3057 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); val 3058 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c lock_alive_counter = val >> 8; val 3060 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = lock_alive_counter << 8 | adapter->portnum; val 3061 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); val 3068 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 val, lock_alive_counter, id; val 3070 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); val 3071 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c id = val & 0xFF; val 3072 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c lock_alive_counter = val >> 8; val 3079 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = (lock_alive_counter << 8) | 0xFF; val 3080 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); val 3458 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u64 val; val 3462 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = (((u64) low) | (((u64) hi) << 32)); val 3463 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c *data++ = val; val 3630 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u8 val, drv_sds_rings = adapter->drv_sds_rings; val 3668 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = LSB(MSW(data)); val 3673 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if (val) val 3675 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c "Interrupt test error: 0x%x\n", val); val 51 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30) val 52 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31) val 53 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF) val 419 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000) val 420 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20) val 421 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) val 422 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400) val 423 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000) val 424 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000) val 135 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 137 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); val 138 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if ((val & 0xFFFF)) val 159 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 167 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); val 168 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val |= (adapter->portnum & 0xf); val 169 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val |= mode << 7; val 175 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val |= seconds << 8; val 176 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); val 187 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 189 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); val 190 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val & ~(0x3 << (adapter->portnum * 2)); val 191 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); val 192 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); val 198 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 205 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); val 206 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val & ~0xFF; val 207 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val | QLC_83XX_IDC_MAJOR_VERSION; val 208 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); val 220 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 227 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); val 230 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val | (1 << adapter->portnum); val 232 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val & ~(1 << adapter->portnum); val 234 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); val 245 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 248 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); val 249 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c version = val & 0xFF; val 264 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 273 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 274 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val &= ~QLC_83XX_IDC_GRACEFULL_RESET; val 275 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); val 286 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 293 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); val 295 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val | (1 << adapter->portnum); val 297 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val & ~(1 << adapter->portnum); val 298 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); val 330 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 ack, presence, val; val 342 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); val 343 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val & ~(ack ^ presence); val 346 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); val 349 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c __func__, val); val 824 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 844 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 848 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { val 860 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { val 870 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { val 956 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val, owner; val 958 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 959 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { val 1174 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 idc_params, val; val 1200 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 1201 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; val 1202 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); val 1209 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 state, val; val 1240 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 1241 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; val 1242 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); val 1275 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 1292 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); val 1293 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val & ~(1 << adapter->portnum); val 1294 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); val 1303 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 1314 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 1315 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { val 1324 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 1325 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = val | QLC_83XX_IDC_GRACEFULL_RESET; val 1326 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); val 1437 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val = 0, val1 = 0, reg = 0; val 1440 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err); val 1443 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); val 1456 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, reg + (i * 0x4), &err); val 1459 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c dev_info(&adapter->pdev->dev, "0x%x ", val); val 1475 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, reg + (i * 0x4), &err); val 1478 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c dev_info(&adapter->pdev->dev, "0x%x ", val); val 1494 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, reg, &err); val 1497 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ val 1498 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWR32(adapter, reg, (val | (i << 29))); val 1499 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, reg, &err); val 1502 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c dev_info(&adapter->pdev->dev, "0x%x ", val); val 1507 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err); val 1515 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val, val1); val 1620 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 1623 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); val 1624 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if (val == QLC_83XX_CMDPEG_COMPLETE) val 1629 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); val 2212 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val; val 2218 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 2219 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if (!(val & QLC_83XX_IDC_GRACEFULL_RESET)) val 2222 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { val 252 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c u32 cap, reg, val, reg2; val 305 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c val = le32_to_cpu(prq->rds_ring_offset) + val 307 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c prq->sds_ring_offset = cpu_to_le32(val); val 773 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c u32 type, val; val 782 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c val = type | (ahw->intr_tbl[i].type << 4); val 784 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c val |= (ahw->intr_tbl[i].id << 16); val 785 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c cmd.req.arg[1] = val; val 794 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c val = cmd.rsp.arg[1]; val 795 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c if (LSB(val)) { val 802 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c ahw->intr_tbl[i].id = MSW(val); val 196 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c static u8 qlcnic_dcb_get_num_app(struct qlcnic_adapter *adapter, u32 val) val 199 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c return QLC_82XX_DCB_GET_NUMAPP(val); val 201 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c return QLC_83XX_DCB_GET_NUMAPP(val); val 205 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c u32 val) val 208 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c return QLC_82XX_DCB_PFC_VALID(val); val 210 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c return QLC_83XX_DCB_PFC_VALID(val); val 214 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c u32 val) val 217 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c return QLC_82XX_DCB_TSA_VALID(val); val 219 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c return QLC_83XX_DCB_TSA_VALID(val); val 223 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c u32 val) val 226 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c return QLC_82XX_DCB_GET_PRIOMAP_APP(val); val 228 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c return QLC_83XX_DCB_GET_PRIOMAP_APP(val); val 371 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c static int __qlcnic_dcb_get_capability(struct qlcnic_dcb *dcb, u32 *val) val 379 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c err = qlcnic_dcb_query_hw_capability(dcb, (char *)val); val 383 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c mbx_out = *val; val 573 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c u32 val; val 608 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c val = each->hdr_prio_pfc_map[0]; val 610 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c max_app = qlcnic_dcb_get_num_app(adapter, val); val 643 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c u32 *val = data; val 648 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c if (*val & BIT_8) val 859 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c u8 val = QLC_DCB_GET_MAP(prio); val 875 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c if ((val & tc_cfg->up_tc_map) && (tc_cfg->prio_cfg[prio].valid)) val 316 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c u32 val = 0; val 317 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRD32(adapter, QLCNIC_PORT_MODE_ADDR, &err); val 319 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c if (val == QLCNIC_PORT_MODE_802_3_AP) { val 595 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c u32 val; val 598 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = qlcnic_83xx_test_link(adapter); val 599 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c return (val & 1) ? 0 : 1; val 601 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRD32(adapter, CRB_XG_STATE_P3P, &err); val 604 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = XG_LINK_STATE_P3P(adapter->ahw->pci_func, val); val 605 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c return (val == XG_LINK_UP_P3P) ? 0 : 1; val 650 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_validate_ringparam(u32 val, u32 min, u32 max, char *r_name) val 653 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c num_desc = max(val, min); val 657 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c if (val != num_desc) { val 659 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_driver_name, r_name, num_desc, val); val 791 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c __u32 val; val 801 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), &err); val 804 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c pause->rx_pause = qlcnic_gb_get_rx_flowctl(val); val 805 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, &err); val 810 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c pause->tx_pause = !(qlcnic_gb_get_gb0_mask(val)); val 813 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c pause->tx_pause = !(qlcnic_gb_get_gb1_mask(val)); val 816 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c pause->tx_pause = !(qlcnic_gb_get_gb2_mask(val)); val 820 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c pause->tx_pause = !(qlcnic_gb_get_gb3_mask(val)); val 827 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, &err); val 831 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c pause->tx_pause = !(qlcnic_xg_get_xg0_mask(val)); val 833 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c pause->tx_pause = !(qlcnic_xg_get_xg1_mask(val)); val 847 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c __u32 val; val 857 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), &err); val 862 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_rx_flowctl(val); val 864 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_unset_rx_flowctl(val); val 867 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val); val 868 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c QLCWR32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), val); val 870 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, &err); val 876 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_unset_gb0_mask(val); val 878 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_set_gb0_mask(val); val 882 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_unset_gb1_mask(val); val 884 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_set_gb1_mask(val); val 888 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_unset_gb2_mask(val); val 890 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_set_gb2_mask(val); val 895 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_unset_gb3_mask(val); val 897 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_gb_set_gb3_mask(val); val 900 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c QLCWR32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, val); val 908 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, &err); val 913 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_xg_unset_xg0_mask(val); val 915 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_xg_set_xg0_mask(val); val 918 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_xg_unset_xg1_mask(val); val 920 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_xg_set_xg1_mask(val); val 922 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c QLCWR32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, val); val 1603 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c u32 val; val 1609 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 1610 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val &= ~QLC_83XX_IDC_DISABLE_FW_DUMP; val 1611 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); val 1626 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c u32 val; val 1632 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 1633 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val |= QLC_83XX_IDC_DISABLE_FW_DUMP; val 1634 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); val 1650 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c u32 val; val 1653 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); val 1654 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c state = (val & QLC_83XX_IDC_DISABLE_FW_DUMP) ? false : true; val 1749 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_set_dump(struct net_device *netdev, struct ethtool_dump *val) val 1756 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c switch (val->flag) { val 1777 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_dev_request_reset(adapter, val->flag); val 1801 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_dev_request_reset(adapter, val->flag); val 1819 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c if (val->flag == qlcnic_fw_dump_level[i]) { val 1826 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ret = qlcnic_set_dump_mask(adapter, val->flag); val 1829 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c val->flag); val 505 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define XG_LINK_STATE_P3P(pcifn, val) \ val 506 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3P_MASK) val 548 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define qlcnic_encode_temp(val, state) (((val) << 16) | (state)) val 920 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define qlcnic_set_phy_speed(config_word, val) \ val 921 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h ((config_word) |= ((val & 0x03) << 14)) val 44 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c static inline void writeq(u64 val, void __iomem *addr) val 46 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c writel(((u32) (val)), (addr)); val 47 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c writel(((u32) (val >> 32)), (addr + 4)); val 286 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c void __iomem *val; val 289 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c val = bar0 + QLCNIC_FW_DUMP_REG1; val 290 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c writel(dest, val); val 291 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c readl(val); val 292 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr); val 293 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c *data = readl(val); val 299 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c void __iomem *val; val 302 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c val = bar0 + QLCNIC_FW_DUMP_REG1; val 303 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c writel(dest, val); val 304 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c readl(val); val 305 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr); val 306 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c writel(data, val); val 307 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c readl(val); val 1410 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c u64 val; val 1453 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c val = (u64)temp << 32; val 1454 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c val |= qlcnic_ind_rd(adapter, ms.rd[2]); val 1455 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c *data = val; val 141 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1)) val 391 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c u32 off, val; val 420 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val = QLCRD32(adapter, QLCNIC_CRB_SRE + 0x1000, &err); val 423 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c QLCWR32(adapter, QLCNIC_CRB_SRE + 0x1000, val & (~(0x1))); val 466 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c if (qlcnic_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 || val 473 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c buf[i].data = val; val 550 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c u32 val; val 554 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CMDPEG_STATE); val 556 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c switch (val) { val 575 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c "complete, state: 0x%x.\n", val); val 582 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c u32 val; val 586 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_RCVPEG_STATE); val 588 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c if (val == PHAN_PEG_RCV_INITIALIZED) val 596 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val); val 622 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c u32 val; val 624 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DEV_PARTITION_INFO); val 625 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val = QLC_DEV_GET_DRV(val, adapter->portnum); val 626 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c if ((val & 0x3) != QLCNIC_TYPE_NIC) { val 628 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c "Not an Ethernet NIC func=%u\n", val); val 631 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c adapter->ahw->physical_port = (val >> 2); val 1207 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c u32 val; val 1219 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val = le32_to_cpu(*(__le32 *)&fw->data[QLCNIC_FW_MAGIC_OFFSET]); val 1220 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c if (val != QLCNIC_BDINFO_MAGIC) val 1229 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val = qlcnic_get_fw_version(adapter); val 1230 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c ver = QLCNIC_DECODE_VERSION(val); val 1239 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c val = qlcnic_get_bios_version(adapter); val 1241 drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c if (val != bios) { val 3199 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c u32 val; val 3201 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = adapter->portnum & 0xf; val 3202 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val |= encoding << 7; val 3203 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val |= (jiffies - adapter->dev_rst_time) << 8; val 3205 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_SCRATCH, val); val 3212 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c u32 val; val 3220 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_STATE); val 3223 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_SET_RST_RDY(val, adapter->portnum); val 3225 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_SET_QSCNT_RDY(val, adapter->portnum); val 3227 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_STATE, val); val 3237 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c u32 val; val 3242 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_STATE); val 3243 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_CLR_RST_QSCNT(val, adapter->portnum); val 3244 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_STATE, val); val 3253 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c u32 val; val 3258 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_ACTIVE); val 3259 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_CLR_REF_CNT(val, adapter->portnum); val 3260 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_ACTIVE, val); val 3267 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c } else if (!(val & 0x11111111)) val 3271 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_STATE); val 3272 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_CLR_RST_QSCNT(val, adapter->portnum); val 3273 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_STATE, val); val 3307 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c u32 val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_IDC_VER); val 3309 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c if (val != QLCNIC_DRV_IDC_VER) { val 3311 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c " idc ver = %x; reqd = %x\n", QLCNIC_DRV_IDC_VER, val); val 3320 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c u32 val, prev_state; val 3331 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_ACTIVE); val 3332 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c if (!(val & (1 << (portnum * 4)))) { val 3333 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_SET_REF_CNT(val, portnum); val 3334 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_ACTIVE, val); val 3356 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_STATE); val 3357 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_SET_RST_RDY(val, portnum); val 3358 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_STATE, val); val 3362 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_STATE); val 3363 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_SET_QSCNT_RDY(val, portnum); val 3364 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_STATE, val); val 3396 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DRV_STATE); val 3397 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_CLR_RST_QSCNT(val, portnum); val 3398 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DRV_STATE, val); val 3412 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c u32 val; val 3454 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c val = QLC_SHARED_REG_RD32(adapter, val 3456 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLC_DEV_SET_RST_RDY(val, adapter->portnum); val 3458 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c QLCNIC_CRB_DRV_STATE, val); val 3802 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c int val = pdev->devfn; val 3804 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c while (val-- > 0) { val 3807 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c PCI_DEVFN(PCI_SLOT(pdev->devfn), val)); val 152 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c u32 val; val 505 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c u32 val, data = 0; val 508 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c val = mux->val; val 510 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c qlcnic_ind_wr(adapter, mux->addr, val); val 512 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c *buffer++ = cpu_to_le32(val); val 514 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c val += mux->val_stride; val 563 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c u32 fl_addr, size, val, lck_val, addr; val 581 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c val = qlcnic_ind_rd(adapter, addr); val 583 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c *buffer++ = cpu_to_le32(val); val 593 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c u32 cnt, val, data, addr; val 596 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c val = l1->init_tag_val; val 599 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c qlcnic_ind_wr(adapter, l1->addr, val); val 609 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c val += l1->stride; val 618 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c u32 cnt, val, data, addr; val 622 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c val = l2->init_tag_val; val 627 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c qlcnic_ind_wr(adapter, l2->addr, val); val 656 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c val += l2->stride; val 103 drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c static inline bool qlcnic_sriov_bc_msg_check(u32 val) val 105 drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c return (val & (1 << QLC_BC_MSG)) ? true : false; val 108 drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c static inline bool qlcnic_sriov_channel_free_check(u32 val) val 110 drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c return (val & (1 << QLC_BC_CFREE)) ? true : false; val 113 drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c static inline bool qlcnic_sriov_flr_check(u32 val) val 115 drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c return (val & (1 << QLC_BC_FLR)) ? true : false; val 118 drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c static inline u8 qlcnic_sriov_target_func_id(u32 val) val 120 drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c return (val >> 4) & 0xff; val 216 drivers/net/ethernet/qualcomm/emac/emac-ethtool.c u32 *val = buff; val 223 drivers/net/ethernet/qualcomm/emac/emac-ethtool.c val[i] = readl(adpt->base + emac_regs[i]); val 342 drivers/net/ethernet/qualcomm/emac/emac-mac.c u32 val; val 347 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = (adpt->tpd_burst << NUM_TPD_BURST_PREF_SHFT) & val 350 drivers/net/ethernet/qualcomm/emac/emac-mac.c val |= TXQ_MODE | LS_8023_SP; val 351 drivers/net/ethernet/qualcomm/emac/emac-mac.c val |= (0x0100 << NUM_TXF_BURST_PREF_SHFT) & val 354 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_TXQ_CTRL_0); val 362 drivers/net/ethernet/qualcomm/emac/emac-mac.c u32 val; val 364 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = (adpt->rfd_burst << NUM_RFD_BURST_PREF_SHFT) & val 366 drivers/net/ethernet/qualcomm/emac/emac-mac.c val |= (SP_IPV6 | CUT_THRU_EN); val 368 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_RXQ_CTRL_0); val 370 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = readl(adpt->base + EMAC_RXQ_CTRL_1); val 371 drivers/net/ethernet/qualcomm/emac/emac-mac.c val &= ~(JUMBO_1KAH_BMSK | RFD_PREF_LOW_THRESHOLD_BMSK | val 373 drivers/net/ethernet/qualcomm/emac/emac-mac.c val |= (JUMBO_1KAH << JUMBO_1KAH_SHFT) | val 376 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_RXQ_CTRL_1); val 378 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = readl(adpt->base + EMAC_RXQ_CTRL_2); val 379 drivers/net/ethernet/qualcomm/emac/emac-mac.c val &= ~(RXF_DOF_THRESHOLD_BMSK | RXF_UOF_THRESHOLD_BMSK); val 380 drivers/net/ethernet/qualcomm/emac/emac-mac.c val |= (RXF_DOF_THRESFHOLD << RXF_DOF_THRESHOLD_SHFT) | val 382 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_RXQ_CTRL_2); val 384 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = readl(adpt->base + EMAC_RXQ_CTRL_3); val 385 drivers/net/ethernet/qualcomm/emac/emac-mac.c val &= ~(RXD_TIMER_BMSK | RXD_THRESHOLD_BMSK); val 386 drivers/net/ethernet/qualcomm/emac/emac-mac.c val |= RXD_TH << RXD_THRESHOLD_SHFT; val 387 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_RXQ_CTRL_3); val 445 drivers/net/ethernet/qualcomm/emac/emac-mac.c u32 val; val 462 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = readl(adpt->base + EMAC_AXI_MAST_CTRL); val 463 drivers/net/ethernet/qualcomm/emac/emac-mac.c val &= ~(DATA_BYTE_SWAP | MAX_BOUND); val 464 drivers/net/ethernet/qualcomm/emac/emac-mac.c val |= MAX_BTYPE; val 465 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_AXI_MAST_CTRL); val 42 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define BITS_GET(val, lo, hi) ((le32_to_cpu(val) & GENMASK((hi), (lo))) >> lo) val 43 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define BITS_SET(val, lo, hi, new_val) \ val 44 drivers/net/ethernet/qualcomm/emac/emac-mac.h val = cpu_to_le32((le32_to_cpu(val) & (~GENMASK((hi), (lo)))) | \ val 67 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define RRD_UPDT_SET(rrd, val) BITS_SET((rrd)->word[3], 31, 31, val) val 79 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_BUF_LEN_SET(tpd, val) BITS_SET((tpd)->word[0], 0, 15, val) val 81 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_CSX_SET(tpd, val) BITS_SET((tpd)->word[1], 8, 8, val) val 84 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_LSO_SET(tpd, val) BITS_SET((tpd)->word[1], 12, 12, val) val 89 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_LSOV_SET(tpd, val) BITS_SET((tpd)->word[1], 13, 13, val) val 93 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_IPV4_SET(tpd, val) BITS_SET((tpd)->word[1], 16, 16, val) val 97 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_TYP_SET(tpd, val) BITS_SET((tpd)->word[1], 17, 17, val) val 99 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_BUFFER_ADDR_L_SET(tpd, val) ((tpd)->word[2] = cpu_to_le32(val)) val 103 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_CVLAN_TAG_SET(tpd, val) BITS_SET((tpd)->word[3], 0, 15, val) val 106 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_INSTC_SET(tpd, val) BITS_SET((tpd)->word[3], 17, 17, val) val 111 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_BUFFER_ADDR_H_SET(tpd, val) BITS_SET((tpd)->word[3], 18, 31, val) val 115 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_PAYLOAD_OFFSET_SET(tpd, val) BITS_SET((tpd)->word[1], 0, 7, val) val 119 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_CXSUM_OFFSET_SET(tpd, val) BITS_SET((tpd)->word[1], 18, 25, val) val 122 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_TCPHDR_OFFSET_SET(tpd, val) BITS_SET((tpd)->word[1], 0, 7, val) val 125 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_MSS_SET(tpd, val) BITS_SET((tpd)->word[1], 18, 30, val) val 127 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define TPD_PKT_LEN_SET(tpd, val) ((tpd)->word[2] = cpu_to_le32(val)) val 67 drivers/net/ethernet/qualcomm/emac/emac-phy.c static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) val 78 drivers/net/ethernet/qualcomm/emac/emac-phy.c ((val << MDIO_DATA_SHFT) & MDIO_DATA_BMSK) | val 136 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c u32 val; val 145 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c writel(itr->val, base + itr->offset); val 113 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c u32 val; val 122 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c writel(itr->val, base + itr->offset); val 103 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c u32 val; val 112 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c writel(itr->val, base + itr->offset); val 92 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c u32 val; val 97 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); val 98 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG); val 99 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c val |= AN_ENABLE; val 100 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); val 182 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c u32 val; val 185 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); val 186 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel(((val & ~PHY_RESET) | PHY_RESET), phy->base + val 190 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); val 191 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2); val 73 drivers/net/ethernet/qualcomm/emac/emac.c void emac_reg_update32(void __iomem *addr, u32 mask, u32 val) val 77 drivers/net/ethernet/qualcomm/emac/emac.c writel(((data & ~mask) | val), addr); val 381 drivers/net/ethernet/qualcomm/emac/emac.h void emac_reg_update32(void __iomem *addr, u32 mask, u32 val); val 220 drivers/net/ethernet/rdc/r6040.c int phy_addr, int reg, u16 val) val 225 drivers/net/ethernet/rdc/r6040.c iowrite16(val, ioaddr + MMWD); val 358 drivers/net/ethernet/realtek/8139cp.c #define cpw8(reg,val) writeb((val), cp->regs + (reg)) val 359 drivers/net/ethernet/realtek/8139cp.c #define cpw16(reg,val) writew((val), cp->regs + (reg)) val 360 drivers/net/ethernet/realtek/8139cp.c #define cpw32(reg,val) writel((val), cp->regs + (reg)) val 361 drivers/net/ethernet/realtek/8139cp.c #define cpw8_f(reg,val) do { \ val 362 drivers/net/ethernet/realtek/8139cp.c writeb((val), cp->regs + (reg)); \ val 365 drivers/net/ethernet/realtek/8139cp.c #define cpw16_f(reg,val) do { \ val 366 drivers/net/ethernet/realtek/8139cp.c writew((val), cp->regs + (reg)); \ val 369 drivers/net/ethernet/realtek/8139cp.c #define cpw32_f(reg,val) do { \ val 370 drivers/net/ethernet/realtek/8139cp.c writel((val), cp->regs + (reg)); \ val 1735 drivers/net/ethernet/realtek/8139cp.c static void write_eeprom(void __iomem *ioaddr, int location, u16 val, val 1746 drivers/net/ethernet/realtek/8139cp.c eeprom_cmd(ee_addr, val, 16); val 1775 drivers/net/ethernet/realtek/8139cp.c u16 val; val 1787 drivers/net/ethernet/realtek/8139cp.c val = read_eeprom(cp->regs, offset, addr_len); val 1788 drivers/net/ethernet/realtek/8139cp.c data[i++] = (u8)(val >> 8); val 1793 drivers/net/ethernet/realtek/8139cp.c val = read_eeprom(cp->regs, offset, addr_len); val 1794 drivers/net/ethernet/realtek/8139cp.c data[i++] = (u8)val; val 1795 drivers/net/ethernet/realtek/8139cp.c data[i++] = (u8)(val >> 8); val 1800 drivers/net/ethernet/realtek/8139cp.c val = read_eeprom(cp->regs, offset, addr_len); val 1801 drivers/net/ethernet/realtek/8139cp.c data[i] = (u8)val; val 1813 drivers/net/ethernet/realtek/8139cp.c u16 val; val 1826 drivers/net/ethernet/realtek/8139cp.c val = read_eeprom(cp->regs, offset, addr_len) & 0xff; val 1827 drivers/net/ethernet/realtek/8139cp.c val |= (u16)data[i++] << 8; val 1828 drivers/net/ethernet/realtek/8139cp.c write_eeprom(cp->regs, offset, val, addr_len); val 1833 drivers/net/ethernet/realtek/8139cp.c val = (u16)data[i++]; val 1834 drivers/net/ethernet/realtek/8139cp.c val |= (u16)data[i++] << 8; val 1835 drivers/net/ethernet/realtek/8139cp.c write_eeprom(cp->regs, offset, val, addr_len); val 1840 drivers/net/ethernet/realtek/8139cp.c val = read_eeprom(cp->regs, offset, addr_len) & 0xff00; val 1841 drivers/net/ethernet/realtek/8139cp.c val |= (u16)data[i]; val 1842 drivers/net/ethernet/realtek/8139cp.c write_eeprom(cp->regs, offset, val, addr_len); val 643 drivers/net/ethernet/realtek/8139too.c int val); val 15 drivers/net/ethernet/realtek/r8169_firmware.h typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val); val 1049 drivers/net/ethernet/realtek/r8169_main.c static void rtl_writephy(struct rtl8169_private *tp, int location, int val) val 1053 drivers/net/ethernet/realtek/r8169_main.c r8168dp_1_mdio_write(tp, location, val); val 1057 drivers/net/ethernet/realtek/r8169_main.c r8168dp_2_mdio_write(tp, location, val); val 1060 drivers/net/ethernet/realtek/r8169_main.c r8168g_mdio_write(tp, location, val); val 1063 drivers/net/ethernet/realtek/r8169_main.c r8169_mdio_write(tp, location, val); val 1090 drivers/net/ethernet/realtek/r8169_main.c int val; val 1092 drivers/net/ethernet/realtek/r8169_main.c val = rtl_readphy(tp, reg_addr); val 1093 drivers/net/ethernet/realtek/r8169_main.c rtl_writephy(tp, reg_addr, (val & ~m) | p); val 1125 drivers/net/ethernet/realtek/r8169_main.c u32 val, int type) val 1128 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, ERIDR, val); val 1135 drivers/net/ethernet/realtek/r8169_main.c u32 val) val 1137 drivers/net/ethernet/realtek/r8169_main.c _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); val 1156 drivers/net/ethernet/realtek/r8169_main.c u32 val; val 1158 drivers/net/ethernet/realtek/r8169_main.c val = rtl_eri_read(tp, addr); val 1159 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_write(tp, addr, mask, (val & ~m) | p); val 1725 drivers/net/ethernet/realtek/r8169_main.c u8 val = RTL_R8(tp, ChipCmd); val 1731 drivers/net/ethernet/realtek/r8169_main.c if (!(val & CmdRxEnb) || val == 0xff) val 2140 drivers/net/ethernet/realtek/r8169_main.c u16 val; val 2229 drivers/net/ethernet/realtek/r8169_main.c while ((reg & p->mask) != p->val) val 2247 drivers/net/ethernet/realtek/r8169_main.c u16 val; val 2254 drivers/net/ethernet/realtek/r8169_main.c rtl_writephy(tp, regs->reg, regs->val); val 2277 drivers/net/ethernet/realtek/r8169_main.c static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) val 2279 drivers/net/ethernet/realtek/r8169_main.c if (rtl_readphy(tp, reg) != val) val 2730 drivers/net/ethernet/realtek/r8169_main.c int val; val 2734 drivers/net/ethernet/realtek/r8169_main.c val = rtl_readphy(tp, 0x0d); val 2736 drivers/net/ethernet/realtek/r8169_main.c if ((val & 0x00ff) != 0x006c) { val 2745 drivers/net/ethernet/realtek/r8169_main.c val &= 0xff00; val 2747 drivers/net/ethernet/realtek/r8169_main.c rtl_writephy(tp, 0x0d, val | set[i]); val 2784 drivers/net/ethernet/realtek/r8169_main.c int val; val 2788 drivers/net/ethernet/realtek/r8169_main.c val = rtl_readphy(tp, 0x0d); val 2789 drivers/net/ethernet/realtek/r8169_main.c if ((val & 0x00ff) != 0x006c) { val 2798 drivers/net/ethernet/realtek/r8169_main.c val &= 0xff00; val 2800 drivers/net/ethernet/realtek/r8169_main.c rtl_writephy(tp, 0x0d, val | set[i]); val 4261 drivers/net/ethernet/realtek/r8169_main.c u32 val = TX_DMA_BURST << TxDMAShift | val 4265 drivers/net/ethernet/realtek/r8169_main.c val |= TXCFG_AUTO_FIFO; val 4267 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, TxConfig, val); val 4291 drivers/net/ethernet/realtek/r8169_main.c u32 val; val 4294 drivers/net/ethernet/realtek/r8169_main.c val = 0x000fff00; val 4296 drivers/net/ethernet/realtek/r8169_main.c val = 0x00ffff00; val 4301 drivers/net/ethernet/realtek/r8169_main.c val |= 0xff; val 4303 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, 0x7c, val); val 4377 drivers/net/ethernet/realtek/r8169_main.c static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) val 4387 drivers/net/ethernet/realtek/r8169_main.c pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) val 4393 drivers/net/ethernet/realtek/r8169_main.c rtl_csi_write(tp, 0x070c, csi | val << 24); val 6869 drivers/net/ethernet/realtek/r8169_main.c int phyreg, u16 val) val 6876 drivers/net/ethernet/realtek/r8169_main.c rtl_writephy(tp, phyreg, val); val 2735 drivers/net/ethernet/renesas/sh_eth.c u32 val; val 2737 drivers/net/ethernet/renesas/sh_eth.c val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; val 2738 drivers/net/ethernet/renesas/sh_eth.c iowrite32(val, mdp->tsu_addr + offset); val 2742 drivers/net/ethernet/renesas/sh_eth.c val = addr[4] << 8 | addr[5]; val 2743 drivers/net/ethernet/renesas/sh_eth.c iowrite32(val, mdp->tsu_addr + offset + 4); val 2753 drivers/net/ethernet/renesas/sh_eth.c u32 val; val 2755 drivers/net/ethernet/renesas/sh_eth.c val = ioread32(mdp->tsu_addr + offset); val 2756 drivers/net/ethernet/renesas/sh_eth.c addr[0] = (val >> 24) & 0xff; val 2757 drivers/net/ethernet/renesas/sh_eth.c addr[1] = (val >> 16) & 0xff; val 2758 drivers/net/ethernet/renesas/sh_eth.c addr[2] = (val >> 8) & 0xff; val 2759 drivers/net/ethernet/renesas/sh_eth.c addr[3] = val & 0xff; val 2760 drivers/net/ethernet/renesas/sh_eth.c val = ioread32(mdp->tsu_addr + offset + 4); val 2761 drivers/net/ethernet/renesas/sh_eth.c addr[4] = (val >> 8) & 0xff; val 2762 drivers/net/ethernet/renesas/sh_eth.c addr[5] = val & 0xff; val 113 drivers/net/ethernet/rocker/rocker_main.c #define rocker_write32(rocker, reg, val) \ val 114 drivers/net/ethernet/rocker/rocker_main.c writel((val), (rocker)->hw_addr + (ROCKER_ ## reg)) val 117 drivers/net/ethernet/rocker/rocker_main.c #define rocker_write64(rocker, reg, val) \ val 118 drivers/net/ethernet/rocker/rocker_main.c writeq((val), (rocker)->hw_addr + (ROCKER_ ## reg)) val 861 drivers/net/ethernet/rocker/rocker_main.c u64 val = rocker_read64(rocker_port->rocker, PORT_PHYS_ENABLE); val 864 drivers/net/ethernet/rocker/rocker_main.c val |= 1ULL << rocker_port->pport; val 866 drivers/net/ethernet/rocker/rocker_main.c val &= ~(1ULL << rocker_port->pport); val 867 drivers/net/ethernet/rocker/rocker_main.c rocker_write64(rocker_port->rocker, PORT_PHYS_ENABLE, val); val 234 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c int val = phy_get_eee_err(dev->phydev); val 236 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c if (val) val 237 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c priv->xstats.eee_wakeup_error_n = val; val 1688 drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c u64 val = readl(ioaddr + reg_lo); val 1690 drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c val |= ((u64)readl(ioaddr + reg_hi)) << 32; val 1692 drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c return val; val 356 drivers/net/ethernet/seeq/ether3.c ether3_probe_bus_8(struct net_device *dev, int val) val 360 drivers/net/ethernet/seeq/ether3.c write_low = val & 255; val 361 drivers/net/ethernet/seeq/ether3.c write_high = val >> 8; val 377 drivers/net/ethernet/seeq/ether3.c ether3_probe_bus_16(struct net_device *dev, int val) val 381 drivers/net/ethernet/seeq/ether3.c ether3_outw(val, REG_RECVPTR); val 384 drivers/net/ethernet/seeq/ether3.c printk(KERN_DEBUG "ether3_probe: write16 [%04X], read16 [%04X]\n", val, read_val); val 386 drivers/net/ethernet/seeq/ether3.c return read_val == val; val 492 drivers/net/ethernet/sfc/falcon/net_driver.h #define STRING_TABLE_LOOKUP(val, member) \ val 493 drivers/net/ethernet/sfc/falcon/net_driver.h ((val) < member ## _max) ? member ## _names[val] : "(invalid)" val 489 drivers/net/ethernet/sfc/falcon/nic.c u64 val; val 493 drivers/net/ethernet/sfc/falcon/nic.c val = le16_to_cpup((__le16 *)addr); val 496 drivers/net/ethernet/sfc/falcon/nic.c val = le32_to_cpup((__le32 *)addr); val 499 drivers/net/ethernet/sfc/falcon/nic.c val = le64_to_cpup((__le64 *)addr); val 503 drivers/net/ethernet/sfc/falcon/nic.c val = 0; val 508 drivers/net/ethernet/sfc/falcon/nic.c stats[index] += val; val 510 drivers/net/ethernet/sfc/falcon/nic.c stats[index] = val; val 45 drivers/net/ethernet/sfc/falcon/phy.h void falcon_txc_set_gpio_val(struct ef4_nic *efx, int pin, int val); val 413 drivers/net/ethernet/sfc/falcon/txc43128_phy.c int val = ef4_mdio_read(efx, mmd, TXC_GLRGS_GLCMD); val 416 drivers/net/ethernet/sfc/falcon/txc43128_phy.c val |= (1 << TXC_GLCMD_LMTSWRST_LBN); val 417 drivers/net/ethernet/sfc/falcon/txc43128_phy.c ef4_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, val); val 419 drivers/net/ethernet/sfc/falcon/txc43128_phy.c val = ef4_mdio_read(efx, mmd, TXC_GLRGS_GLCMD); val 420 drivers/net/ethernet/sfc/falcon/txc43128_phy.c if (!(val & (1 << TXC_GLCMD_LMTSWRST_LBN))) val 561 drivers/net/ethernet/sfc/net_driver.h #define STRING_TABLE_LOOKUP(val, member) \ val 562 drivers/net/ethernet/sfc/net_driver.h ((val) < member ## _max) ? member ## _names[val] : "(invalid)" val 496 drivers/net/ethernet/sfc/nic.c u64 val; val 500 drivers/net/ethernet/sfc/nic.c val = le16_to_cpup((__le16 *)addr); val 503 drivers/net/ethernet/sfc/nic.c val = le32_to_cpup((__le32 *)addr); val 506 drivers/net/ethernet/sfc/nic.c val = le64_to_cpup((__le64 *)addr); val 510 drivers/net/ethernet/sfc/nic.c val = 0; val 515 drivers/net/ethernet/sfc/nic.c stats[index] += val; val 517 drivers/net/ethernet/sfc/nic.c stats[index] = val; val 347 drivers/net/ethernet/silan/sc92031.c static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val) val 349 drivers/net/ethernet/silan/sc92031.c _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11)); val 74 drivers/net/ethernet/sis/sis190.c #define SIS_W8(reg, val) writeb ((val), ioaddr + (reg)) val 75 drivers/net/ethernet/sis/sis190.c #define SIS_W16(reg, val) writew ((val), ioaddr + (reg)) val 76 drivers/net/ethernet/sis/sis190.c #define SIS_W32(reg, val) writel ((val), ioaddr + (reg)) val 383 drivers/net/ethernet/sis/sis190.c static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val) val 387 drivers/net/ethernet/sis/sis190.c (((u32) val) << EhnMIIdataShift)); val 398 drivers/net/ethernet/sis/sis190.c static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val) val 402 drivers/net/ethernet/sis/sis190.c mdio_write(tp->mmio_addr, phy_id, reg, val); val 920 drivers/net/ethernet/sis/sis190.c u16 val; val 927 drivers/net/ethernet/sis/sis190.c val = mdio_read(ioaddr, phy_id, MII_BMCR); val 928 drivers/net/ethernet/sis/sis190.c if (val & BMCR_RESET) { val 934 drivers/net/ethernet/sis/sis190.c val = mdio_read_latched(ioaddr, phy_id, MII_BMSR); val 935 drivers/net/ethernet/sis/sis190.c if (!(val & BMSR_ANEGCOMPLETE) && tp->link_status != LNK_AUTONEG) { val 939 drivers/net/ethernet/sis/sis190.c } else if ((val & BMSR_LSTATUS) && tp->link_status != LNK_ON) { val 942 drivers/net/ethernet/sis/sis190.c int val; val 962 drivers/net/ethernet/sis/sis190.c val = mdio_read(ioaddr, phy_id, 0x1f); val 963 drivers/net/ethernet/sis/sis190.c netif_info(tp, link, dev, "mii ext = %04x\n", val); val 965 drivers/net/ethernet/sis/sis190.c val = mdio_read(ioaddr, phy_id, MII_LPA); val 969 drivers/net/ethernet/sis/sis190.c val, adv, autoexp); val 971 drivers/net/ethernet/sis/sis190.c if (val & LPA_NPAGE && autoexp & EXPANSION_NWAY) { val 975 drivers/net/ethernet/sis/sis190.c val = (gigadv & (gigrec >> 2)); val 976 drivers/net/ethernet/sis/sis190.c if (val & ADVERTISE_1000FULL) val 978 drivers/net/ethernet/sis/sis190.c else if (val & ADVERTISE_1000HALF) val 982 drivers/net/ethernet/sis/sis190.c val &= adv; val 984 drivers/net/ethernet/sis/sis190.c for (p = reg31; p->val; p++) { val 985 drivers/net/ethernet/sis/sis190.c if ((val & p->val) == p->val) val 1008 drivers/net/ethernet/sis/sis190.c tp->negotiated_lpa = p->val; val 1013 drivers/net/ethernet/sis/sis190.c } else if (!(val & BMSR_LSTATUS) && tp->link_status != LNK_AUTONEG) val 1715 drivers/net/ethernet/sis/sis190.c int val; val 1719 drivers/net/ethernet/sis/sis190.c val = mdio_read(ioaddr, phy_id, MII_ADVERTISE); val 1723 drivers/net/ethernet/sis/sis190.c mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) | val 209 drivers/net/ethernet/sis/sis900.c #define sw32(reg, val) iowrite32(val, ioaddr + (reg)) val 210 drivers/net/ethernet/sis/sis900.c #define sw8(reg, val) iowrite8(val, ioaddr + (reg)) val 222 drivers/net/ethernet/sis/sis900.c static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val); val 185 drivers/net/ethernet/smsc/epic100.c #define ew16(reg, val) iowrite16(val, ioaddr + (reg)) val 186 drivers/net/ethernet/smsc/epic100.c #define ew32(reg, val) iowrite32(val, ioaddr + (reg)) val 291 drivers/net/ethernet/smsc/epic100.c static void mdio_write(struct net_device *dev, int phy_id, int loc, int val); val 1781 drivers/net/ethernet/smsc/smc911x.c unsigned int val, chip_id, revision; val 1792 drivers/net/ethernet/smsc/smc911x.c val = SMC_GET_BYTE_TEST(lp); val 1794 drivers/net/ethernet/smsc/smc911x.c CARDNAME, val); val 1795 drivers/net/ethernet/smsc/smc911x.c if (val != 0x87654321) { val 1796 drivers/net/ethernet/smsc/smc911x.c netdev_err(dev, "Invalid chip endian 0x%08x\n", val); val 760 drivers/net/ethernet/smsc/smc91x.c static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) val 770 drivers/net/ethernet/smsc/smc91x.c if (val & mask) val 786 drivers/net/ethernet/smsc/smc91x.c unsigned int mii_reg, mask, val; val 791 drivers/net/ethernet/smsc/smc91x.c for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { val 793 drivers/net/ethernet/smsc/smc91x.c val |= mask; val 801 drivers/net/ethernet/smsc/smc91x.c return val; val 1852 drivers/net/ethernet/smsc/smc91x.c unsigned int val, revision_register; val 1858 drivers/net/ethernet/smsc/smc91x.c val = SMC_CURRENT_BANK(lp); val 1860 drivers/net/ethernet/smsc/smc91x.c CARDNAME, val); val 1861 drivers/net/ethernet/smsc/smc91x.c if ((val & 0xFF00) != 0x3300) { val 1862 drivers/net/ethernet/smsc/smc91x.c if ((val & 0xFF) == 0x33) { val 1876 drivers/net/ethernet/smsc/smc91x.c val = SMC_CURRENT_BANK(lp); val 1877 drivers/net/ethernet/smsc/smc91x.c if ((val & 0xFF00) != 0x3300) { val 1889 drivers/net/ethernet/smsc/smc91x.c val = SMC_GET_BASE(lp); val 1890 drivers/net/ethernet/smsc/smc91x.c val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; val 1891 drivers/net/ethernet/smsc/smc91x.c if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { val 1893 drivers/net/ethernet/smsc/smc91x.c CARDNAME, ioaddr, val); val 2271 drivers/net/ethernet/smsc/smc91x.c u32 val; val 2297 drivers/net/ethernet/smsc/smc91x.c &val)) { val 2298 drivers/net/ethernet/smsc/smc91x.c if (val & 1) val 2300 drivers/net/ethernet/smsc/smc91x.c if ((val == 0) || (val & 2)) val 2302 drivers/net/ethernet/smsc/smc91x.c if (val & 4) val 2308 drivers/net/ethernet/smsc/smc91x.c &val)) val 2309 drivers/net/ethernet/smsc/smc91x.c lp->io_shift = val; val 99 drivers/net/ethernet/smsc/smc91x.h static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg, val 103 drivers/net/ethernet/smsc/smc91x.h unsigned int v = val << 16; val 107 drivers/net/ethernet/smsc/smc91x.h writew(val, ioaddr + reg); val 77 drivers/net/ethernet/smsc/smsc911x.c void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val); val 190 drivers/net/ethernet/smsc/smsc911x.c u32 val) val 193 drivers/net/ethernet/smsc/smsc911x.c writel(val, pdata->ioaddr + reg); val 198 drivers/net/ethernet/smsc/smsc911x.c writew(val & 0xFFFF, pdata->ioaddr + reg); val 199 drivers/net/ethernet/smsc/smsc911x.c writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); val 207 drivers/net/ethernet/smsc/smsc911x.c __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val) val 210 drivers/net/ethernet/smsc/smsc911x.c writel(val, pdata->ioaddr + __smsc_shift(pdata, reg)); val 215 drivers/net/ethernet/smsc/smsc911x.c writew(val & 0xFFFF, val 217 drivers/net/ethernet/smsc/smsc911x.c writew((val >> 16) & 0xFFFF, val 226 drivers/net/ethernet/smsc/smsc911x.c u32 val) val 231 drivers/net/ethernet/smsc/smsc911x.c pdata->ops->reg_write(pdata, reg, val); val 478 drivers/net/ethernet/smsc/smsc911x.c u32 val; val 483 drivers/net/ethernet/smsc/smsc911x.c val = smsc911x_reg_read(pdata, MAC_CSR_CMD); val 484 drivers/net/ethernet/smsc/smsc911x.c if (!(val & MAC_CSR_CMD_CSR_BUSY_)) val 488 drivers/net/ethernet/smsc/smsc911x.c "MAC_CSR_CMD: 0x%08X", val); val 522 drivers/net/ethernet/smsc/smsc911x.c unsigned int offset, u32 val) val 536 drivers/net/ethernet/smsc/smsc911x.c smsc911x_reg_write(pdata, MAC_CSR_DATA, val); val 590 drivers/net/ethernet/smsc/smsc911x.c u16 val) val 607 drivers/net/ethernet/smsc/smsc911x.c smsc911x_mac_write(pdata, MII_DATA, val); val 840 drivers/net/ethernet/smsc/smsc911x.c unsigned int i, val; val 857 drivers/net/ethernet/smsc/smsc911x.c val = smsc911x_reg_read(pdata, HW_CFG); val 858 drivers/net/ethernet/smsc/smsc911x.c val &= HW_CFG_TX_FIF_SZ_; val 859 drivers/net/ethernet/smsc/smsc911x.c val |= HW_CFG_SF_; val 860 drivers/net/ethernet/smsc/smsc911x.c smsc911x_reg_write(pdata, HW_CFG, val); val 1188 drivers/net/ethernet/smsc/smsc911x.c unsigned int val; val 1192 drivers/net/ethernet/smsc/smsc911x.c val = smsc911x_reg_read(pdata, RX_DP_CTRL); val 1193 drivers/net/ethernet/smsc/smsc911x.c } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout); val 1197 drivers/net/ethernet/smsc/smsc911x.c "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val); val 141 drivers/net/ethernet/smsc/smsc9420.c u16 val) val 157 drivers/net/ethernet/smsc/smsc9420.c smsc9420_reg_write(pd, MII_DATA, (u32)val); val 330 drivers/net/ethernet/socionext/netsec.c static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) val 332 drivers/net/ethernet/socionext/netsec.c writel(val, priv->ioaddr + reg_addr); val 468 drivers/net/ethernet/socionext/netsec.c int phy_addr, int reg, u16 val) val 473 drivers/net/ethernet/socionext/netsec.c if (netsec_mac_write(priv, GMAC_REG_GDR, val)) val 1569 drivers/net/ethernet/socionext/netsec.c u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); val 1574 drivers/net/ethernet/socionext/netsec.c val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); val 1575 drivers/net/ethernet/socionext/netsec.c netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); val 1578 drivers/net/ethernet/socionext/netsec.c val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); val 1579 drivers/net/ethernet/socionext/netsec.c netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); val 315 drivers/net/ethernet/socionext/sni_ave.c int entry, int offset, u32 val) val 323 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + addr); val 327 drivers/net/ethernet/socionext/sni_ave.c int entry, u32 val) val 329 drivers/net/ethernet/socionext/sni_ave.c ave_desc_write(ndev, id, entry, AVE_DESC_OFS_CMDSTS, val); val 356 drivers/net/ethernet/socionext/sni_ave.c static void ave_irq_restore(struct net_device *ndev, u32 val) val 360 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_GIMR); val 410 drivers/net/ethernet/socionext/sni_ave.c static void ave_ethtool_set_msglevel(struct net_device *ndev, u32 val) val 414 drivers/net/ethernet/socionext/sni_ave.c priv->msg_enable = val; val 520 drivers/net/ethernet/socionext/sni_ave.c u16 val) val 533 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_MDIOWDR); val 635 drivers/net/ethernet/socionext/sni_ave.c u32 val; val 644 drivers/net/ethernet/socionext/sni_ave.c if (readl_poll_timeout(priv->base + AVE_DESCC, val, !val, val 652 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_DESCC); val 653 drivers/net/ethernet/socionext/sni_ave.c val |= AVE_DESCC_RDSTP; val 654 drivers/net/ethernet/socionext/sni_ave.c val &= ~AVE_DESCC_STATUS_MASK; val 655 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_DESCC); val 656 drivers/net/ethernet/socionext/sni_ave.c if (readl_poll_timeout(priv->base + AVE_DESCC, val, val 657 drivers/net/ethernet/socionext/sni_ave.c val & (AVE_DESCC_RDSTP << 16), val 665 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_DESCC); val 666 drivers/net/ethernet/socionext/sni_ave.c val &= ~AVE_DESCC_RDSTP; val 667 drivers/net/ethernet/socionext/sni_ave.c val &= ~AVE_DESCC_STATUS_MASK; val 668 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_DESCC); val 857 drivers/net/ethernet/socionext/sni_ave.c u32 val; val 860 drivers/net/ethernet/socionext/sni_ave.c val = AVE_CFGR_FLE | AVE_CFGR_IPFCEN | AVE_CFGR_CHE; val 862 drivers/net/ethernet/socionext/sni_ave.c val |= AVE_CFGR_MII; val 863 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_CFGR); val 866 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_RSTCTRL); val 867 drivers/net/ethernet/socionext/sni_ave.c val &= ~AVE_RSTCTRL_RMIIRST; val 868 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_RSTCTRL); val 883 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_RSTCTRL); val 884 drivers/net/ethernet/socionext/sni_ave.c val |= AVE_RSTCTRL_RMIIRST; val 885 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_RSTCTRL); val 984 drivers/net/ethernet/socionext/sni_ave.c u32 val; val 989 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_PFEN); val 990 drivers/net/ethernet/socionext/sni_ave.c writel(val | BIT(entry), priv->base + AVE_PFEN); val 998 drivers/net/ethernet/socionext/sni_ave.c u32 val; val 1003 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_PFEN); val 1004 drivers/net/ethernet/socionext/sni_ave.c writel(val & ~BIT(entry), priv->base + AVE_PFEN); val 1091 drivers/net/ethernet/socionext/sni_ave.c u32 val, txcr, rxcr, rxcr_org; val 1096 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_TXCR); val 1097 drivers/net/ethernet/socionext/sni_ave.c val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); val 1100 drivers/net/ethernet/socionext/sni_ave.c val |= AVE_TXCR_TXSPD_1G; val 1102 drivers/net/ethernet/socionext/sni_ave.c val |= AVE_TXCR_TXSPD_100; val 1104 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_TXCR); val 1108 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_LINKSEL); val 1110 drivers/net/ethernet/socionext/sni_ave.c val &= ~AVE_LINKSEL_100M; val 1112 drivers/net/ethernet/socionext/sni_ave.c val |= AVE_LINKSEL_100M; val 1113 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_LINKSEL); val 1268 drivers/net/ethernet/socionext/sni_ave.c u32 val; val 1319 drivers/net/ethernet/socionext/sni_ave.c val = AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_DRPEN | val 1321 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_RXCR); val 1328 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_IIRQC) & AVE_IIRQC_BSCK; val 1329 drivers/net/ethernet/socionext/sni_ave.c val |= AVE_IIRQC_EN0 | (AVE_INTM_COUNT << 16); val 1330 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_IIRQC); val 1332 drivers/net/ethernet/socionext/sni_ave.c val = AVE_GI_RXIINT | AVE_GI_RXOVF | AVE_GI_TX | AVE_GI_RXDROP; val 1333 drivers/net/ethernet/socionext/sni_ave.c ave_irq_restore(ndev, val); val 1468 drivers/net/ethernet/socionext/sni_ave.c u32 val; val 1472 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_RXCR); val 1474 drivers/net/ethernet/socionext/sni_ave.c val &= ~AVE_RXCR_AFEN; val 1476 drivers/net/ethernet/socionext/sni_ave.c val |= AVE_RXCR_AFEN; val 1477 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_RXCR); val 69 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c u16 val; val 71 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(base + TSE_PCS_CONTROL_REG); val 72 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val |= TSE_PCS_SW_RST_MASK; val 73 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(val, base + TSE_PCS_CONTROL_REG); val 76 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(base + TSE_PCS_CONTROL_REG); val 77 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val &= TSE_PCS_SW_RST_MASK; val 78 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c if (val == 0) val 112 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c u16 val = 0; val 116 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); val 117 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val &= TSE_PCS_STATUS_LINK_MASK; val 119 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c if (val != 0) { val 131 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c u16 val = 0; val 137 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); val 138 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val &= TSE_PCS_STATUS_AN_COMPLETED_MASK; val 140 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c if (val != 0) { val 142 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG); val 143 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c speed = val & TSE_PCS_PARTNER_SPEED_MASK; val 144 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c duplex = val & TSE_PCS_PARTNER_DUPLEX_MASK; val 181 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); val 182 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val |= TSE_PCS_CONTROL_RESTART_AN_MASK; val 183 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); val 206 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c u32 val; val 214 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); val 215 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val |= TSE_PCS_CONTROL_AN_EN_MASK; val 216 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); val 218 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); val 219 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val |= TSE_PCS_USE_SGMII_AN_MASK; val 220 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); val 222 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); val 223 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val |= TSE_PCS_CONTROL_RESTART_AN_MASK; val 232 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); val 233 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val &= ~TSE_PCS_CONTROL_AN_EN_MASK; val 234 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); val 236 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); val 237 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val &= ~TSE_PCS_USE_SGMII_AN_MASK; val 238 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); val 240 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); val 241 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val &= ~TSE_PCS_SGMII_SPEED_MASK; val 245 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val |= TSE_PCS_SGMII_SPEED_1000; val 248 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val |= TSE_PCS_SGMII_SPEED_100; val 251 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val |= TSE_PCS_SGMII_SPEED_10; val 256 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); val 32 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val) val 34 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c writel(val, (void *)(gmac->ctl_block + reg)); val 147 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c uint32_t clk_bits, val; val 170 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); val 171 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val &= ~clk_bits; val 172 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); val 175 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val); val 176 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val &= ~(NSS_COMMON_CLK_DIV_MASK val 178 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id); val 179 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val); val 182 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); val 183 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= clk_bits; val 184 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); val 250 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c int val; val 253 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val = stmmac_get_platform_resources(pdev, &stmmac_res); val 254 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c if (val) val 255 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c return val; val 279 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET | val 282 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= NSS_COMMON_GMAC_CTL_CSYS_REQ; val 285 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL; val 288 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL; val 296 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val); val 299 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val); val 300 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id)); val 303 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) << val 307 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) << val 316 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val); val 319 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); val 320 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id); val 323 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | val 327 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) | val 334 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); val 28 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c unsigned int val; val 30 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c val = readl(dwmac->reg); val 34 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c val &= ~ETHMAC_SPEED_100; val 37 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c val |= ETHMAC_SPEED_100; val 41 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c writel(val, dwmac->reg); val 116 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c { .div = 2, .val = 2, }, val 117 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c { .div = 3, .val = 3, }, val 118 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c { .div = 4, .val = 4, }, val 119 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c { .div = 5, .val = 5, }, val 120 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c { .div = 6, .val = 6, }, val 121 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c { .div = 7, .val = 7, }, val 107 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c int mask, int val, unsigned int offset) val 112 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c temp = (temp & ~(mask)) | val; val 186 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c unsigned int val; val 213 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); val 214 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c val &= SDCC_DLL_CONFIG_CK_OUT_EN; val 215 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c if (!val) val 230 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); val 231 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c val &= SDCC_DLL_CONFIG_CK_OUT_EN; val 232 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c if (val) val 68 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define HIWORD_UPDATE(val, mask, shift) \ val 69 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ((val) << (shift) | (mask) << ((shift) + 16)) val 144 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) val 145 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) val 253 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) val 254 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) val 399 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) val 400 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) val 491 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) val 492 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) val 643 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) val 644 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) val 754 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) val 755 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) val 865 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) val 866 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) val 70 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c u32 val; val 77 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG); val 78 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK; val 82 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c val |= EMAC_SPLITTER_CTRL_SPEED_1000; val 85 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c val |= EMAC_SPLITTER_CTRL_SPEED_100; val 88 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c val |= EMAC_SPLITTER_CTRL_SPEED_10; val 93 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG); val 239 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c static int socfpga_set_phy_mode_common(int phymode, u32 *val) val 246 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; val 251 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; val 254 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; val 268 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c u32 ctrl, val, module; val 270 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c if (socfpga_set_phy_mode_common(phymode, &val)) { val 280 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; val 288 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c ctrl |= val << reg_shift; val 330 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c u32 ctrl, val, module; val 332 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c if (socfpga_set_phy_mode_common(phymode, &val)) val 340 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; val 348 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c ctrl |= val; val 202 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c u32 val = 0; val 205 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; val 208 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK; val 212 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; val 224 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); val 232 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c u32 val; val 239 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; val 240 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c regmap_update_bits(regmap, reg, ENMII_MASK, val); val 178 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c int val, ret; val 182 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val = SYSCFG_PMCR_ETH_SEL_MII; val 186 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val = SYSCFG_PMCR_ETH_SEL_GMII; val 188 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val |= SYSCFG_PMCR_ETH_CLK_SEL; val 192 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val = SYSCFG_PMCR_ETH_SEL_RMII; val 194 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; val 201 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val = SYSCFG_PMCR_ETH_SEL_RGMII; val 203 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val |= SYSCFG_PMCR_ETH_CLK_SEL; val 219 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c dwmac->ops->syscfg_eth_mask, val); val 226 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c int val; val 230 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val = SYSCFG_MCU_ETH_SEL_MII; val 234 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c val = SYSCFG_MCU_ETH_SEL_RMII; val 245 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c dwmac->ops->syscfg_eth_mask, val << 23); val 816 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c u32 reg, val; val 825 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; val 831 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; val 839 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c regmap_field_write(gmac->regmap_field, val); val 875 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c u32 reg, val; val 877 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c ret = regmap_field_read(gmac->regmap_field, &val); val 884 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c if (reg != val) val 887 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val, reg); val 914 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { val 915 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c if (val % 100) { val 919 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val /= 100; val 920 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c dev_dbg(priv->device, "set tx-delay to %x\n", val); val 921 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c if (val <= gmac->variant->tx_delay_max) { val 924 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= (val << SYSCON_ETXDC_SHIFT); val 927 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val); val 932 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { val 933 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c if (val % 100) { val 937 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val /= 100; val 938 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c dev_dbg(priv->device, "set rx-delay to %x\n", val); val 939 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c if (val <= gmac->variant->rx_delay_max) { val 942 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= (val << SYSCON_ERXDC_SHIFT); val 945 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val); val 763 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c static void dwmac4_sarc_configure(void __iomem *ioaddr, int val) val 768 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c value |= val << GMAC_CONFIG_SARC_SHIFT; val 307 drivers/net/ethernet/stmicro/stmmac/dwmac5.c u32 val; val 310 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val = readl(ioaddr + MTL_OPERATION_MODE); val 311 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val &= ~MTL_FRPE; val 312 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MTL_OPERATION_MODE); val 314 drivers/net/ethernet/stmicro/stmmac/dwmac5.c ret = readl_poll_timeout(ioaddr + MTL_RXP_CONTROL_STATUS, val, val 315 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val & RXPI, 1, 10000); val 323 drivers/net/ethernet/stmicro/stmmac/dwmac5.c u32 val; val 325 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val = readl(ioaddr + MTL_OPERATION_MODE); val 326 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= MTL_FRPE; val 327 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MTL_OPERATION_MODE); val 336 drivers/net/ethernet/stmicro/stmmac/dwmac5.c for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) { val 337 drivers/net/ethernet/stmicro/stmmac/dwmac5.c int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i; val 338 drivers/net/ethernet/stmicro/stmmac/dwmac5.c u32 val; val 342 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val, !(val & STARTBUSY), 1, 10000); val 347 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val = *((u32 *)&entry->val + i); val 348 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MTL_RXP_IACC_DATA); val 351 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val = real_pos & ADDR; val 352 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS); val 355 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= WRRDN; val 356 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS); val 359 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= STARTBUSY; val 360 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS); val 364 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val, !(val & STARTBUSY), 1, 10000); val 418 drivers/net/ethernet/stmicro/stmmac/dwmac5.c u32 old_val, val; val 422 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val = old_val & ~GMAC_CONFIG_RE; val 423 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + GMAC_CONFIG); val 447 drivers/net/ethernet/stmicro/stmmac/dwmac5.c entry->val.af = 0; val 448 drivers/net/ethernet/stmicro/stmmac/dwmac5.c entry->val.rf = 0; val 449 drivers/net/ethernet/stmicro/stmmac/dwmac5.c entry->val.nc = 1; val 450 drivers/net/ethernet/stmicro/stmmac/dwmac5.c entry->val.ok_index = nve + 2; val 486 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val = (nve << 16) & NPE; val 487 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= nve & NVE; val 488 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MTL_RXP_CONTROL_STATUS); val 504 drivers/net/ethernet/stmicro/stmmac/dwmac5.c u32 val = readl(ioaddr + MAC_PPS_CONTROL); val 514 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val &= ~PPSx_MASK(index); val 517 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= PPSCMDx(index, 0x5); val 518 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= PPSEN0; val 519 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MAC_PPS_CONTROL); val 523 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= PPSCMDx(index, 0x2); val 524 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= TRGTMODSELx(index, 0x2); val 525 drivers/net/ethernet/stmicro/stmmac/dwmac5.c val |= PPSEN0; val 550 drivers/net/ethernet/stmicro/stmmac/dwmac5.c writel(val, ioaddr + MAC_PPS_CONTROL); val 19 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define TRGTMODSELx(x, val) \ val 21 drivers/net/ethernet/stmicro/stmmac/dwmac5.h ((val) << (PPS_MAXIDX(x) - 2)) val 22 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define PPSCMDx(x, val) \ val 24 drivers/net/ethernet/stmicro/stmmac/dwmac5.h ((val) << PPS_MINIDX(x)) val 207 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TRGTMODSELx(x, val) \ val 209 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h ((val) << (XGMAC_PPS_MAXIDX(x) - 2)) val 210 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PPSCMDx(x, val) \ val 212 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h ((val) << XGMAC_PPS_MINIDX(x)) val 321 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 val = 0x0; val 324 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_PWRDWN | XGMAC_MGKPKTEN; val 326 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_PWRDWN | XGMAC_GLBLUCAST | XGMAC_RWKPKTEN; val 327 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c if (val) { val 333 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_PMT); val 509 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 val) val 513 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_RSS_DATA); val 878 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 val = readl(ioaddr + XGMAC_MTL_OPMODE); val 880 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val &= ~XGMAC_FRPE; val 881 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_MTL_OPMODE); val 888 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 val; val 890 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val = readl(ioaddr + XGMAC_MTL_OPMODE); val 891 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_FRPE; val 892 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_MTL_OPMODE); val 901 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) { val 902 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i; val 903 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 val; val 907 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val, !(val & XGMAC_STARTBUSY), 1, 10000); val 912 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val = *((u32 *)&entry->val + i); val 913 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_MTL_RXP_IACC_DATA); val 916 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val = real_pos & XGMAC_ADDR; val 917 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST); val 920 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_WRRDN; val 921 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST); val 924 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_STARTBUSY; val 925 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST); val 929 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val, !(val & XGMAC_STARTBUSY), 1, 10000); val 984 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 old_val, val; val 988 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val = old_val & ~XGMAC_CONFIG_RE; val 989 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_RX_CONFIG); val 1013 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c entry->val.af = 0; val 1014 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c entry->val.rf = 0; val 1015 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c entry->val.nc = 1; val 1016 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c entry->val.ok_index = nve + 2; val 1052 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val = (nve << 16) & XGMAC_NPE; val 1053 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= nve & XGMAC_NVE; val 1054 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_MTL_RXP_CONTROL_STATUS); val 1084 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 val = readl(ioaddr + XGMAC_PPS_CONTROL); val 1094 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val &= ~XGMAC_PPSx_MASK(index); val 1097 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_STOP); val 1098 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_PPS_CONTROL); val 1102 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_START); val 1103 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_TRGTMODSELx(index, XGMAC_PPSCMD_START); val 1104 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c val |= XGMAC_PPSEN0; val 1129 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(val, ioaddr + XGMAC_PPS_CONTROL); val 1133 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c static void dwxgmac2_sarc_configure(void __iomem *ioaddr, int val) val 1138 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c value |= val << XGMAC_CONFIG_SARC_SHIFT; val 365 drivers/net/ethernet/stmicro/stmmac/hwif.h void (*sarc_configure)(void __iomem *ioaddr, int val); val 115 drivers/net/ethernet/stmicro/stmmac/stmmac.h } __packed val; val 511 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c int val = phylink_get_eee_err(priv->phylink); val 512 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c if (val) val 513 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c priv->xstats.phy_eee_wakeup_error_n = val; val 60 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h u32 val = readl(ioaddr + GMAC_AN_STATUS(reg)); val 64 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h if (val & GMAC_AN_STATUS_ANC) val 70 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h if (val & GMAC_AN_STATUS_LS) val 1098 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c sel->keys[0].val = htonl(0xdeadbeef); val 22 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.match_data = 0x0; val 23 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.match_en = 0x0; val 24 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.af = 1; val 25 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.dma_ch_no = 0x0; val 51 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c memset(&first->val, 0, sizeof(first->val)); val 75 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c action_entry->val.af = 1; val 80 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c action_entry->val.rf = 1; val 105 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c data = sel->keys[0].val; val 136 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.match_en = (mask << (rem * 8)) & val 138 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.match_data = (data << (rem * 8)) & val 140 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.frame_offset = real_off; val 143 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c frag->val.match_en = (mask >> (rem * 8)) & val 145 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c frag->val.match_data = (data >> (rem * 8)) & val 147 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c frag->val.frame_offset = real_off + 1; val 152 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.match_en = mask; val 153 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.match_data = data; val 154 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.frame_offset = real_off; val 413 drivers/net/ethernet/sun/cassini.c static int cas_phy_write(struct cas *cp, int reg, u16 val) val 422 drivers/net/ethernet/sun/cassini.c cmd |= val & MIF_FRAME_DATA_MASK; val 746 drivers/net/ethernet/sun/cassini.c u32 val = readl(cp->regs + REG_PCS_MII_CTRL); val 749 drivers/net/ethernet/sun/cassini.c val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN); val 753 drivers/net/ethernet/sun/cassini.c val |= PCS_MII_CTRL_DUPLEX; val 754 drivers/net/ethernet/sun/cassini.c val &= ~PCS_MII_AUTONEG_EN; val 758 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_PCS_MII_CTRL); val 785 drivers/net/ethernet/sun/cassini.c u16 val; val 790 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, MII_BMCR); val 791 drivers/net/ethernet/sun/cassini.c if ((val & BMCR_RESET) == 0) val 865 drivers/net/ethernet/sun/cassini.c u16 val; val 896 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, BROADCOM_MII_REG4); val 897 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, BROADCOM_MII_REG4); val 898 drivers/net/ethernet/sun/cassini.c if (val & 0x0080) { val 901 drivers/net/ethernet/sun/cassini.c val & ~0x0080); val 920 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, MII_BMCR); val 921 drivers/net/ethernet/sun/cassini.c val &= ~BMCR_ANENABLE; val 922 drivers/net/ethernet/sun/cassini.c cas_phy_write(cp, MII_BMCR, val); val 936 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, CAS_MII_1000_CTRL); val 937 drivers/net/ethernet/sun/cassini.c val &= ~CAS_ADVERTISE_1000HALF; val 938 drivers/net/ethernet/sun/cassini.c val |= CAS_ADVERTISE_1000FULL; val 939 drivers/net/ethernet/sun/cassini.c cas_phy_write(cp, CAS_MII_1000_CTRL, val); val 944 drivers/net/ethernet/sun/cassini.c u32 val; val 955 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_PCS_MII_CTRL); val 956 drivers/net/ethernet/sun/cassini.c val |= PCS_MII_RESET; val 957 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_PCS_MII_CTRL); val 976 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_PCS_MII_ADVERT); val 977 drivers/net/ethernet/sun/cassini.c val &= ~PCS_MII_ADVERT_HD; val 978 drivers/net/ethernet/sun/cassini.c val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE | val 980 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_PCS_MII_ADVERT); val 1161 drivers/net/ethernet/sun/cassini.c u32 val; val 1168 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val); val 1169 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask); val 1170 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI); val 1172 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10); val 1173 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop); val 1174 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext); val 1175 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff); val 1176 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext); val 1177 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff); val 1178 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op); val 1179 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID); val 1181 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask); val 1182 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift); val 1183 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab); val 1184 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg); val 1185 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW); val 1194 drivers/net/ethernet/sun/cassini.c u32 val; val 1198 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL); val 1199 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0)); val 1200 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0)); val 1203 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1)); val 1204 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_RX_CFG); val 1206 drivers/net/ethernet/sun/cassini.c val = (unsigned long) cp->init_rxds[0] - val 1208 drivers/net/ethernet/sun/cassini.c writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI); val 1209 drivers/net/ethernet/sun/cassini.c writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW); val 1216 drivers/net/ethernet/sun/cassini.c val = (unsigned long) cp->init_rxds[1] - val 1218 drivers/net/ethernet/sun/cassini.c writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI); val 1219 drivers/net/ethernet/sun/cassini.c writel((desc_dma + val) & 0xffffffff, cp->regs + val 1226 drivers/net/ethernet/sun/cassini.c val = (unsigned long) cp->init_rxcs[0] - val 1228 drivers/net/ethernet/sun/cassini.c writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI); val 1229 drivers/net/ethernet/sun/cassini.c writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW); val 1234 drivers/net/ethernet/sun/cassini.c val = (unsigned long) cp->init_rxcs[i] - val 1236 drivers/net/ethernet/sun/cassini.c writel((desc_dma + val) >> 32, cp->regs + val 1238 drivers/net/ethernet/sun/cassini.c writel((desc_dma + val) & 0xffffffff, cp->regs + val 1264 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(RX_PAUSE_THRESH_OFF, val 1266 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(RX_PAUSE_THRESH_ON, val 1268 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_RX_PAUSE_THRESH); val 1284 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL); val 1285 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL); val 1286 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_RX_BLANK); val 1297 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL); val 1298 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_RX_AE_THRESH); val 1300 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1)); val 1301 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH); val 1310 drivers/net/ethernet/sun/cassini.c val = 0; val 1312 drivers/net/ethernet/sun/cassini.c val = 0x1; val 1314 drivers/net/ethernet/sun/cassini.c val = 0x2; val 1316 drivers/net/ethernet/sun/cassini.c val = 0x3; val 1333 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(RX_PAGE_SIZE, val); val 1334 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i); val 1335 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10)); val 1336 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1); val 1337 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_RX_PAGE_SIZE); val 1343 drivers/net/ethernet/sun/cassini.c val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS); val 1344 drivers/net/ethernet/sun/cassini.c val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK; val 1345 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL); val 1346 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_HP_CFG); val 1449 drivers/net/ethernet/sun/cassini.c u32 val; val 1497 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_RX_CFG); val 1498 drivers/net/ethernet/sun/cassini.c writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG); val 1500 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_MAC_RX_CFG); val 1501 drivers/net/ethernet/sun/cassini.c writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); val 1567 drivers/net/ethernet/sun/cassini.c u16 val; val 1579 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, MII_BMCR); val 1584 drivers/net/ethernet/sun/cassini.c val &= ~(BMCR_ANRESTART | BMCR_ANENABLE); val 1585 drivers/net/ethernet/sun/cassini.c val |= BMCR_FULLDPLX; val 1586 drivers/net/ethernet/sun/cassini.c val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? val 1588 drivers/net/ethernet/sun/cassini.c cas_phy_write(cp, MII_BMCR, val); val 1596 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, MII_BMCR); val 1598 drivers/net/ethernet/sun/cassini.c if (val & CAS_BMCR_SPEED1000) { /* gigabit */ val 1599 drivers/net/ethernet/sun/cassini.c val &= ~CAS_BMCR_SPEED1000; val 1600 drivers/net/ethernet/sun/cassini.c val |= (BMCR_SPEED100 | BMCR_FULLDPLX); val 1601 drivers/net/ethernet/sun/cassini.c cas_phy_write(cp, MII_BMCR, val); val 1605 drivers/net/ethernet/sun/cassini.c if (val & BMCR_SPEED100) { val 1606 drivers/net/ethernet/sun/cassini.c if (val & BMCR_FULLDPLX) /* fd failed */ val 1607 drivers/net/ethernet/sun/cassini.c val &= ~BMCR_FULLDPLX; val 1609 drivers/net/ethernet/sun/cassini.c val &= ~BMCR_SPEED100; val 1611 drivers/net/ethernet/sun/cassini.c cas_phy_write(cp, MII_BMCR, val); val 2878 drivers/net/ethernet/sun/cassini.c u32 val; val 2891 drivers/net/ethernet/sun/cassini.c val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 | val 2901 drivers/net/ethernet/sun/cassini.c val |= CAS_TX_RINGN_BASE(i); val 2909 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_TX_CFG); val 3472 drivers/net/ethernet/sun/cassini.c u32 val; val 3476 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN; val 3477 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_TX_CFG); val 3478 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN; val 3479 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_RX_CFG); val 3482 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN; val 3483 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_MAC_TX_CFG); val 3484 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN; val 3485 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_MAC_RX_CFG); val 3489 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_MAC_TX_CFG); val 3490 drivers/net/ethernet/sun/cassini.c if ((val & MAC_TX_CFG_EN)) val 3497 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_MAC_RX_CFG); val 3498 drivers/net/ethernet/sun/cassini.c if ((val & MAC_RX_CFG_EN)) { val 3533 drivers/net/ethernet/sun/cassini.c u32 val = readl(cp->regs + REG_PCS_MII_LPA); val 3534 drivers/net/ethernet/sun/cassini.c *fd = (val & PCS_MII_LPA_FD) ? 1 : 0; val 3535 drivers/net/ethernet/sun/cassini.c *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00; val 3536 drivers/net/ethernet/sun/cassini.c if (val & PCS_MII_LPA_ASYM_PAUSE) val 3545 drivers/net/ethernet/sun/cassini.c u32 val; val 3552 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, MII_LPA); val 3553 drivers/net/ethernet/sun/cassini.c if (val & CAS_LPA_PAUSE) val 3556 drivers/net/ethernet/sun/cassini.c if (val & CAS_LPA_ASYM_PAUSE) val 3559 drivers/net/ethernet/sun/cassini.c if (val & LPA_DUPLEX) val 3561 drivers/net/ethernet/sun/cassini.c if (val & LPA_100) val 3565 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, CAS_MII_1000_STATUS); val 3566 drivers/net/ethernet/sun/cassini.c if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF)) val 3568 drivers/net/ethernet/sun/cassini.c if (val & CAS_LPA_1000FULL) val 3580 drivers/net/ethernet/sun/cassini.c u32 val; val 3589 drivers/net/ethernet/sun/cassini.c val = cas_phy_read(cp, MII_BMCR); val 3590 drivers/net/ethernet/sun/cassini.c if (val & BMCR_ANENABLE) { val 3594 drivers/net/ethernet/sun/cassini.c if (val & BMCR_FULLDPLX) val 3597 drivers/net/ethernet/sun/cassini.c if (val & BMCR_SPEED100) val 3599 drivers/net/ethernet/sun/cassini.c else if (val & CAS_BMCR_SPEED1000) val 3606 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_PCS_MII_CTRL); val 3608 drivers/net/ethernet/sun/cassini.c if ((val & PCS_MII_AUTONEG_EN) == 0) { val 3609 drivers/net/ethernet/sun/cassini.c if (val & PCS_MII_CTRL_DUPLEX) val 3617 drivers/net/ethernet/sun/cassini.c val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED; val 3619 drivers/net/ethernet/sun/cassini.c val |= MAC_XIF_MII_BUFFER_OUTPUT_EN; val 3621 drivers/net/ethernet/sun/cassini.c val |= MAC_XIF_DISABLE_ECHO; val 3624 drivers/net/ethernet/sun/cassini.c val |= MAC_XIF_FDPLX_LED; val 3626 drivers/net/ethernet/sun/cassini.c val |= MAC_XIF_GMII_MODE; val 3627 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_MAC_XIF_CFG); val 3630 drivers/net/ethernet/sun/cassini.c val = MAC_TX_CFG_IPG_EN; val 3632 drivers/net/ethernet/sun/cassini.c val |= MAC_TX_CFG_IGNORE_CARRIER; val 3633 drivers/net/ethernet/sun/cassini.c val |= MAC_TX_CFG_IGNORE_COLL; val 3636 drivers/net/ethernet/sun/cassini.c val |= MAC_TX_CFG_NEVER_GIVE_UP_EN; val 3637 drivers/net/ethernet/sun/cassini.c val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM; val 3648 drivers/net/ethernet/sun/cassini.c writel(val | MAC_TX_CFG_CARRIER_EXTEND, val 3651 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_MAC_RX_CFG); val 3652 drivers/net/ethernet/sun/cassini.c val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */ val 3653 drivers/net/ethernet/sun/cassini.c writel(val | MAC_RX_CFG_CARRIER_EXTEND, val 3663 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_MAC_TX_CFG); val 3668 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_MAC_RX_CFG); val 3670 drivers/net/ethernet/sun/cassini.c val |= MAC_RX_CFG_STRIP_FCS; val 3674 drivers/net/ethernet/sun/cassini.c val &= ~MAC_RX_CFG_STRIP_FCS; val 3678 drivers/net/ethernet/sun/cassini.c writel(val & ~MAC_RX_CFG_CARRIER_EXTEND, val 3696 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_MAC_CTRL_CFG); val 3697 drivers/net/ethernet/sun/cassini.c val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN); val 3699 drivers/net/ethernet/sun/cassini.c val |= MAC_CTRL_CFG_SEND_PAUSE_EN; val 3701 drivers/net/ethernet/sun/cassini.c val |= MAC_CTRL_CFG_RECV_PAUSE_EN; val 3704 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_MAC_CTRL_CFG); val 3763 drivers/net/ethernet/sun/cassini.c u32 val = readl(cp->regs + REG_SW_RESET); val 3764 drivers/net/ethernet/sun/cassini.c if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0) val 3792 drivers/net/ethernet/sun/cassini.c u32 val; val 3800 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_TX_CFG); val 3801 drivers/net/ethernet/sun/cassini.c val &= ~TX_CFG_DMA_EN; val 3802 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_TX_CFG); val 3804 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_RX_CFG); val 3805 drivers/net/ethernet/sun/cassini.c val &= ~RX_CFG_DMA_EN; val 3806 drivers/net/ethernet/sun/cassini.c writel(val, cp->regs + REG_RX_CFG); val 4147 drivers/net/ethernet/sun/cassini.c u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE); val 4149 drivers/net/ethernet/sun/cassini.c int tlm = CAS_VAL(MAC_SM_TLM, val); val 4152 drivers/net/ethernet/sun/cassini.c (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) { val 4154 drivers/net/ethernet/sun/cassini.c "tx err: MAC_STATE[%08x]\n", val); val 4159 drivers/net/ethernet/sun/cassini.c val = readl(cp->regs + REG_TX_FIFO_PKT_CNT); val 4162 drivers/net/ethernet/sun/cassini.c if ((val == 0) && (wptr != rptr)) { val 4165 drivers/net/ethernet/sun/cassini.c val, wptr, rptr); val 4389 drivers/net/ethernet/sun/cassini.c u32 val; val 4393 drivers/net/ethernet/sun/cassini.c val = hval; val 4395 drivers/net/ethernet/sun/cassini.c val= readl(cp->regs+ethtool_register_table[i].offsets); val 4397 drivers/net/ethernet/sun/cassini.c memcpy(p, (u8 *)&val, sizeof(u32)); val 4810 drivers/net/ethernet/sun/cassini.c u32 val; val 4823 drivers/net/ethernet/sun/cassini.c pci_read_config_dword(pdev, 0x40, &val); val 4824 drivers/net/ethernet/sun/cassini.c val &= ~0x00040000; val 4825 drivers/net/ethernet/sun/cassini.c pci_write_config_dword(pdev, 0x40, val); val 2122 drivers/net/ethernet/sun/cassini.h u16 mask, val; val 56 drivers/net/ethernet/sun/niu.c static void writeq(u64 val, void __iomem *reg) val 58 drivers/net/ethernet/sun/niu.c writel(val & 0xffffffff, reg); val 59 drivers/net/ethernet/sun/niu.c writel(val >> 32, reg + 0x4UL); val 73 drivers/net/ethernet/sun/niu.c #define nw64(reg, val) writeq((val), np->regs + (reg)) val 76 drivers/net/ethernet/sun/niu.c #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) val 79 drivers/net/ethernet/sun/niu.c #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) val 82 drivers/net/ethernet/sun/niu.c #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) val 85 drivers/net/ethernet/sun/niu.c #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) val 105 drivers/net/ethernet/sun/niu.c u64 val = nr64_mac(reg); val 107 drivers/net/ethernet/sun/niu.c if (!(val & bits)) val 140 drivers/net/ethernet/sun/niu.c u64 val = nr64_ipp(reg); val 142 drivers/net/ethernet/sun/niu.c if (!(val & bits)) val 156 drivers/net/ethernet/sun/niu.c u64 val; val 158 drivers/net/ethernet/sun/niu.c val = nr64_ipp(reg); val 159 drivers/net/ethernet/sun/niu.c val |= bits; val 160 drivers/net/ethernet/sun/niu.c nw64_ipp(reg, val); val 179 drivers/net/ethernet/sun/niu.c u64 val = nr64(reg); val 181 drivers/net/ethernet/sun/niu.c if (!(val & bits)) val 217 drivers/net/ethernet/sun/niu.c u64 val = (u64) lp->timer; val 220 drivers/net/ethernet/sun/niu.c val |= LDG_IMGMT_ARM; val 222 drivers/net/ethernet/sun/niu.c nw64(LDG_IMGMT(lp->ldg_num), val); val 228 drivers/net/ethernet/sun/niu.c u64 val; val 241 drivers/net/ethernet/sun/niu.c val = nr64(mask_reg); val 243 drivers/net/ethernet/sun/niu.c val &= ~bits; val 245 drivers/net/ethernet/sun/niu.c val |= bits; val 246 drivers/net/ethernet/sun/niu.c nw64(mask_reg, val); val 292 drivers/net/ethernet/sun/niu.c static u32 phy_decode(u32 val, int port) val 294 drivers/net/ethernet/sun/niu.c return (val >> (port * 2)) & PORT_TYPE_MASK; val 300 drivers/net/ethernet/sun/niu.c u64 val; val 303 drivers/net/ethernet/sun/niu.c val = nr64(MIF_FRAME_OUTPUT); val 304 drivers/net/ethernet/sun/niu.c if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) val 305 drivers/net/ethernet/sun/niu.c return val & MIF_FRAME_OUTPUT_DATA; val 361 drivers/net/ethernet/sun/niu.c static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) val 367 drivers/net/ethernet/sun/niu.c val & 0xffff); val 371 drivers/net/ethernet/sun/niu.c val >> 16); val 375 drivers/net/ethernet/sun/niu.c static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) val 381 drivers/net/ethernet/sun/niu.c val & 0xffff); val 385 drivers/net/ethernet/sun/niu.c val >> 16); val 432 drivers/net/ethernet/sun/niu.c u64 uninitialized_var(sig), mask, val; val 494 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); val 495 drivers/net/ethernet/sun/niu.c mask = val; val 499 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); val 500 drivers/net/ethernet/sun/niu.c mask = val; val 509 drivers/net/ethernet/sun/niu.c if ((sig & mask) == val) val 515 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { val 517 drivers/net/ethernet/sun/niu.c np->port, (int)(sig & mask), (int)val); val 529 drivers/net/ethernet/sun/niu.c u64 uninitialized_var(sig), mask, val; val 589 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P0 | val 600 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P1 | val 615 drivers/net/ethernet/sun/niu.c if ((sig & mask) == val) val 621 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { val 623 drivers/net/ethernet/sun/niu.c np->port, (int)(sig & mask), (int)val); val 639 drivers/net/ethernet/sun/niu.c static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) val 645 drivers/net/ethernet/sun/niu.c *val = (err & 0xffff); val 649 drivers/net/ethernet/sun/niu.c *val |= ((err & 0xffff) << 16); val 655 drivers/net/ethernet/sun/niu.c static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) val 662 drivers/net/ethernet/sun/niu.c *val = (err & 0xffff); val 666 drivers/net/ethernet/sun/niu.c *val |= ((err & 0xffff) << 16); val 673 drivers/net/ethernet/sun/niu.c static int esr_read_reset(struct niu *np, u32 *val) val 680 drivers/net/ethernet/sun/niu.c *val = (err & 0xffff); val 684 drivers/net/ethernet/sun/niu.c *val |= ((err & 0xffff) << 16); val 691 drivers/net/ethernet/sun/niu.c static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) val 696 drivers/net/ethernet/sun/niu.c ESR_RXTX_CTRL_L(chan), val & 0xffff); val 699 drivers/net/ethernet/sun/niu.c ESR_RXTX_CTRL_H(chan), (val >> 16)); val 703 drivers/net/ethernet/sun/niu.c static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) val 708 drivers/net/ethernet/sun/niu.c ESR_GLUE_CTRL0_L(chan), val & 0xffff); val 711 drivers/net/ethernet/sun/niu.c ESR_GLUE_CTRL0_H(chan), (val >> 16)); val 758 drivers/net/ethernet/sun/niu.c u64 ctrl_val, test_cfg_val, sig, mask, val; val 842 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P0 | val 853 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P1 | val 866 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { val 872 drivers/net/ethernet/sun/niu.c np->port, (int)(sig & mask), (int)val); val 882 drivers/net/ethernet/sun/niu.c u64 val; val 884 drivers/net/ethernet/sun/niu.c val = nr64(ENET_SERDES_1_PLL_CFG); val 885 drivers/net/ethernet/sun/niu.c val &= ~ENET_SERDES_PLL_FBDIV2; val 888 drivers/net/ethernet/sun/niu.c val |= ENET_SERDES_PLL_HRATE0; val 891 drivers/net/ethernet/sun/niu.c val |= ENET_SERDES_PLL_HRATE1; val 894 drivers/net/ethernet/sun/niu.c val |= ENET_SERDES_PLL_HRATE2; val 897 drivers/net/ethernet/sun/niu.c val |= ENET_SERDES_PLL_HRATE3; val 902 drivers/net/ethernet/sun/niu.c nw64(ENET_SERDES_1_PLL_CFG, val); val 911 drivers/net/ethernet/sun/niu.c u64 ctrl_val, test_cfg_val, sig, mask, val; val 915 drivers/net/ethernet/sun/niu.c val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 | val 964 drivers/net/ethernet/sun/niu.c nw64(pll_cfg, val); val 1006 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); val 1007 drivers/net/ethernet/sun/niu.c mask = val; val 1011 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); val 1012 drivers/net/ethernet/sun/niu.c mask = val; val 1019 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { val 1021 drivers/net/ethernet/sun/niu.c np->port, (int)(sig & mask), (int)val); val 1032 drivers/net/ethernet/sun/niu.c u64 val; val 1043 drivers/net/ethernet/sun/niu.c val = nr64_pcs(PCS_MII_STAT); val 1045 drivers/net/ethernet/sun/niu.c if (val & PCS_MII_STAT_LINK_STATUS) { val 1065 drivers/net/ethernet/sun/niu.c u64 val, val2; val 1076 drivers/net/ethernet/sun/niu.c val = nr64_xpcs(XPCS_STATUS(0)); val 1081 drivers/net/ethernet/sun/niu.c if ((val & 0x1000ULL) && link_ok) { val 1374 drivers/net/ethernet/sun/niu.c static int mrvl88x2011_act_led(struct niu *np, int val) val 1384 drivers/net/ethernet/sun/niu.c err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); val 1538 drivers/net/ethernet/sun/niu.c u64 val; val 1544 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_CONFIG); val 1545 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_LED_POLARITY; val 1546 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_FORCE_LED_ON; val 1547 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 1549 drivers/net/ethernet/sun/niu.c val = nr64(MIF_CONFIG); val 1550 drivers/net/ethernet/sun/niu.c val |= MIF_CONFIG_INDIRECT_MODE; val 1551 drivers/net/ethernet/sun/niu.c nw64(MIF_CONFIG, val); val 1598 drivers/net/ethernet/sun/niu.c u64 val; val 1600 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_CONFIG); val 1601 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_LED_POLARITY; val 1602 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_FORCE_LED_ON; val 1603 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 1606 drivers/net/ethernet/sun/niu.c val = nr64(MIF_CONFIG); val 1607 drivers/net/ethernet/sun/niu.c val |= MIF_CONFIG_INDIRECT_MODE; val 1608 drivers/net/ethernet/sun/niu.c nw64(MIF_CONFIG, val); val 1656 drivers/net/ethernet/sun/niu.c u64 val; val 1659 drivers/net/ethernet/sun/niu.c val = nr64(MIF_CONFIG); val 1660 drivers/net/ethernet/sun/niu.c val &= ~MIF_CONFIG_INDIRECT_MODE; val 1661 drivers/net/ethernet/sun/niu.c nw64(MIF_CONFIG, val); val 1850 drivers/net/ethernet/sun/niu.c u64 val; val 1853 drivers/net/ethernet/sun/niu.c val = nr64(MIF_CONFIG); val 1854 drivers/net/ethernet/sun/niu.c val &= ~MIF_CONFIG_INDIRECT_MODE; val 1855 drivers/net/ethernet/sun/niu.c nw64(MIF_CONFIG, val); val 2106 drivers/net/ethernet/sun/niu.c u64 sig, mask, val; val 2112 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P0 | val 2123 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P1 | val 2136 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) val 2354 drivers/net/ethernet/sun/niu.c u64 ctrl_val, test_cfg_val, sig, mask, val; val 2439 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P0 | val 2450 drivers/net/ethernet/sun/niu.c val = (ESR_INT_SRDY0_P1 | val 2463 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { val 2656 drivers/net/ethernet/sun/niu.c u64 val, mask; val 2669 drivers/net/ethernet/sun/niu.c val = nr64_mac(reg); val 2671 drivers/net/ethernet/sun/niu.c val |= mask; val 2673 drivers/net/ethernet/sun/niu.c val &= ~mask; val 2674 drivers/net/ethernet/sun/niu.c nw64_mac(reg, val); val 2682 drivers/net/ethernet/sun/niu.c u64 val = nr64_mac(reg); val 2683 drivers/net/ethernet/sun/niu.c val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR); val 2684 drivers/net/ethernet/sun/niu.c val |= num; val 2686 drivers/net/ethernet/sun/niu.c val |= HOST_INFO_MPR; val 2687 drivers/net/ethernet/sun/niu.c nw64_mac(reg, val); val 2859 drivers/net/ethernet/sun/niu.c u64 val = nr64(FFLP_CFG_1); val 2862 drivers/net/ethernet/sun/niu.c val &= ~FFLP_CFG_1_TCAM_DIS; val 2864 drivers/net/ethernet/sun/niu.c val |= FFLP_CFG_1_TCAM_DIS; val 2865 drivers/net/ethernet/sun/niu.c nw64(FFLP_CFG_1, val); val 2870 drivers/net/ethernet/sun/niu.c u64 val = nr64(FFLP_CFG_1); val 2872 drivers/net/ethernet/sun/niu.c val &= ~(FFLP_CFG_1_FFLPINITDONE | val 2875 drivers/net/ethernet/sun/niu.c val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT); val 2876 drivers/net/ethernet/sun/niu.c val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT); val 2877 drivers/net/ethernet/sun/niu.c nw64(FFLP_CFG_1, val); val 2879 drivers/net/ethernet/sun/niu.c val = nr64(FFLP_CFG_1); val 2880 drivers/net/ethernet/sun/niu.c val |= FFLP_CFG_1_FFLPINITDONE; val 2881 drivers/net/ethernet/sun/niu.c nw64(FFLP_CFG_1, val); val 2888 drivers/net/ethernet/sun/niu.c u64 val; val 2895 drivers/net/ethernet/sun/niu.c val = nr64(reg); val 2897 drivers/net/ethernet/sun/niu.c val |= L2_CLS_VLD; val 2899 drivers/net/ethernet/sun/niu.c val &= ~L2_CLS_VLD; val 2900 drivers/net/ethernet/sun/niu.c nw64(reg, val); val 2910 drivers/net/ethernet/sun/niu.c u64 val; val 2918 drivers/net/ethernet/sun/niu.c val = nr64(reg); val 2919 drivers/net/ethernet/sun/niu.c val &= ~L2_CLS_ETYPE; val 2920 drivers/net/ethernet/sun/niu.c val |= (ether_type << L2_CLS_ETYPE_SHIFT); val 2921 drivers/net/ethernet/sun/niu.c nw64(reg, val); val 2931 drivers/net/ethernet/sun/niu.c u64 val; val 2938 drivers/net/ethernet/sun/niu.c val = nr64(reg); val 2940 drivers/net/ethernet/sun/niu.c val |= L3_CLS_VALID; val 2942 drivers/net/ethernet/sun/niu.c val &= ~L3_CLS_VALID; val 2943 drivers/net/ethernet/sun/niu.c nw64(reg, val); val 2953 drivers/net/ethernet/sun/niu.c u64 val; val 2963 drivers/net/ethernet/sun/niu.c val = nr64(reg); val 2964 drivers/net/ethernet/sun/niu.c val &= ~(L3_CLS_IPVER | L3_CLS_PID | val 2967 drivers/net/ethernet/sun/niu.c val |= L3_CLS_IPVER; val 2968 drivers/net/ethernet/sun/niu.c val |= (protocol_id << L3_CLS_PID_SHIFT); val 2969 drivers/net/ethernet/sun/niu.c val |= (tos_mask << L3_CLS_TOSMASK_SHIFT); val 2970 drivers/net/ethernet/sun/niu.c val |= (tos_val << L3_CLS_TOS_SHIFT); val 2971 drivers/net/ethernet/sun/niu.c nw64(reg, val); val 3021 drivers/net/ethernet/sun/niu.c u64 val = hash_addr_regval(index, num_entries); val 3028 drivers/net/ethernet/sun/niu.c nw64(HASH_TBL_ADDR(partition), val); val 3040 drivers/net/ethernet/sun/niu.c u64 val = hash_addr_regval(index, num_entries); val 3047 drivers/net/ethernet/sun/niu.c nw64(HASH_TBL_ADDR(partition), val); val 3056 drivers/net/ethernet/sun/niu.c u64 val; val 3062 drivers/net/ethernet/sun/niu.c val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE; val 3063 drivers/net/ethernet/sun/niu.c nw64(FFLP_CFG_1, val); val 3068 drivers/net/ethernet/sun/niu.c u64 val = nr64(FFLP_CFG_1); val 3070 drivers/net/ethernet/sun/niu.c val &= ~FFLP_CFG_1_FFLPINITDONE; val 3071 drivers/net/ethernet/sun/niu.c val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT); val 3072 drivers/net/ethernet/sun/niu.c nw64(FFLP_CFG_1, val); val 3074 drivers/net/ethernet/sun/niu.c val = nr64(FFLP_CFG_1); val 3075 drivers/net/ethernet/sun/niu.c val |= FFLP_CFG_1_FFLPINITDONE; val 3076 drivers/net/ethernet/sun/niu.c nw64(FFLP_CFG_1, val); val 3078 drivers/net/ethernet/sun/niu.c val = nr64(FCRAM_REF_TMR); val 3079 drivers/net/ethernet/sun/niu.c val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN); val 3080 drivers/net/ethernet/sun/niu.c val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT); val 3081 drivers/net/ethernet/sun/niu.c val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT); val 3082 drivers/net/ethernet/sun/niu.c nw64(FCRAM_REF_TMR, val); val 3089 drivers/net/ethernet/sun/niu.c u64 val; val 3098 drivers/net/ethernet/sun/niu.c val = nr64(reg); val 3099 drivers/net/ethernet/sun/niu.c val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE); val 3100 drivers/net/ethernet/sun/niu.c val |= (mask << FLW_PRT_SEL_MASK_SHIFT); val 3101 drivers/net/ethernet/sun/niu.c val |= (base << FLW_PRT_SEL_BASE_SHIFT); val 3103 drivers/net/ethernet/sun/niu.c val |= FLW_PRT_SEL_EXT; val 3104 drivers/net/ethernet/sun/niu.c nw64(reg, val); val 3123 drivers/net/ethernet/sun/niu.c u64 val = nr64(FFLP_CFG_1); val 3126 drivers/net/ethernet/sun/niu.c val |= FFLP_CFG_1_LLCSNAP; val 3128 drivers/net/ethernet/sun/niu.c val &= ~FFLP_CFG_1_LLCSNAP; val 3129 drivers/net/ethernet/sun/niu.c nw64(FFLP_CFG_1, val); val 3134 drivers/net/ethernet/sun/niu.c u64 val = nr64(FFLP_CFG_1); val 3137 drivers/net/ethernet/sun/niu.c val &= ~FFLP_CFG_1_ERRORDIS; val 3139 drivers/net/ethernet/sun/niu.c val |= FFLP_CFG_1_ERRORDIS; val 3140 drivers/net/ethernet/sun/niu.c nw64(FFLP_CFG_1, val); val 3372 drivers/net/ethernet/sun/niu.c u64 addr, val; val 3377 drivers/net/ethernet/sun/niu.c val = le64_to_cpup(&rp->rcr[index]); val 3378 drivers/net/ethernet/sun/niu.c addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << val 3382 drivers/net/ethernet/sun/niu.c rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> val 3395 drivers/net/ethernet/sun/niu.c if (!(val & RCR_ENTRY_MULTI)) val 3420 drivers/net/ethernet/sun/niu.c u64 addr, val, off; val 3424 drivers/net/ethernet/sun/niu.c val = le64_to_cpup(&rp->rcr[index]); val 3426 drivers/net/ethernet/sun/niu.c len = (val & RCR_ENTRY_L2_LEN) >> val 3430 drivers/net/ethernet/sun/niu.c addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << val 3434 drivers/net/ethernet/sun/niu.c rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> val 3441 drivers/net/ethernet/sun/niu.c ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT); val 3444 drivers/net/ethernet/sun/niu.c !(val & (RCR_ENTRY_NOPORT | val 3449 drivers/net/ethernet/sun/niu.c } else if (!(val & RCR_ENTRY_MULTI)) val 3464 drivers/net/ethernet/sun/niu.c if (!(val & RCR_ENTRY_MULTI)) val 3903 drivers/net/ethernet/sun/niu.c u64 val; val 3905 drivers/net/ethernet/sun/niu.c val = nr64_mac(XTXMAC_STATUS); val 3906 drivers/net/ethernet/sun/niu.c if (val & XTXMAC_STATUS_FRAME_CNT_EXP) val 3908 drivers/net/ethernet/sun/niu.c if (val & XTXMAC_STATUS_BYTE_CNT_EXP) val 3910 drivers/net/ethernet/sun/niu.c if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR) val 3912 drivers/net/ethernet/sun/niu.c if (val & XTXMAC_STATUS_TXMAC_OFLOW) val 3914 drivers/net/ethernet/sun/niu.c if (val & XTXMAC_STATUS_MAX_PSIZE_ERR) val 3916 drivers/net/ethernet/sun/niu.c if (val & XTXMAC_STATUS_TXMAC_UFLOW) val 3919 drivers/net/ethernet/sun/niu.c val = nr64_mac(XRXMAC_STATUS); val 3920 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_LCL_FLT_STATUS) val 3922 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RFLT_DET) val 3924 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_LFLT_CNT_EXP) val 3926 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP) val 3928 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP) val 3930 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP) val 3932 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) val 3934 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) val 3936 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP) val 3938 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP) val 3940 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP) val 3942 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP) val 3944 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP) val 3946 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP) val 3948 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP) val 3950 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP) val 3952 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP) val 3954 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_LENERR_CNT_EXP) val 3956 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_CRCERR_CNT_EXP) val 3958 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXUFLOW) val 3960 drivers/net/ethernet/sun/niu.c if (val & XRXMAC_STATUS_RXOFLOW) val 3963 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_FC_STAT); val 3964 drivers/net/ethernet/sun/niu.c if (val & XMAC_FC_STAT_TX_MAC_NPAUSE) val 3966 drivers/net/ethernet/sun/niu.c if (val & XMAC_FC_STAT_TX_MAC_PAUSE) val 3968 drivers/net/ethernet/sun/niu.c if (val & XMAC_FC_STAT_RX_MAC_RPAUSE) val 3975 drivers/net/ethernet/sun/niu.c u64 val; val 3977 drivers/net/ethernet/sun/niu.c val = nr64_mac(BTXMAC_STATUS); val 3978 drivers/net/ethernet/sun/niu.c if (val & BTXMAC_STATUS_UNDERRUN) val 3980 drivers/net/ethernet/sun/niu.c if (val & BTXMAC_STATUS_MAX_PKT_ERR) val 3982 drivers/net/ethernet/sun/niu.c if (val & BTXMAC_STATUS_BYTE_CNT_EXP) val 3984 drivers/net/ethernet/sun/niu.c if (val & BTXMAC_STATUS_FRAME_CNT_EXP) val 3987 drivers/net/ethernet/sun/niu.c val = nr64_mac(BRXMAC_STATUS); val 3988 drivers/net/ethernet/sun/niu.c if (val & BRXMAC_STATUS_OVERFLOW) val 3990 drivers/net/ethernet/sun/niu.c if (val & BRXMAC_STATUS_FRAME_CNT_EXP) val 3992 drivers/net/ethernet/sun/niu.c if (val & BRXMAC_STATUS_ALIGN_ERR_EXP) val 3994 drivers/net/ethernet/sun/niu.c if (val & BRXMAC_STATUS_CRC_ERR_EXP) val 3996 drivers/net/ethernet/sun/niu.c if (val & BRXMAC_STATUS_LEN_ERR_EXP) val 3999 drivers/net/ethernet/sun/niu.c val = nr64_mac(BMAC_CTRL_STATUS); val 4000 drivers/net/ethernet/sun/niu.c if (val & BMAC_CTRL_STATUS_NOPAUSE) val 4002 drivers/net/ethernet/sun/niu.c if (val & BMAC_CTRL_STATUS_PAUSE) val 4004 drivers/net/ethernet/sun/niu.c if (val & BMAC_CTRL_STATUS_PAUSE_RECV) val 4546 drivers/net/ethernet/sun/niu.c u64 val = nr64(TX_CS(channel)); val 4547 drivers/net/ethernet/sun/niu.c if (val & TX_CS_SNG_STATE) val 4555 drivers/net/ethernet/sun/niu.c u64 val = nr64(TX_CS(channel)); val 4557 drivers/net/ethernet/sun/niu.c val |= TX_CS_STOP_N_GO; val 4558 drivers/net/ethernet/sun/niu.c nw64(TX_CS(channel), val); val 4568 drivers/net/ethernet/sun/niu.c u64 val = nr64(TX_CS(channel)); val 4569 drivers/net/ethernet/sun/niu.c if (!(val & TX_CS_RST)) val 4577 drivers/net/ethernet/sun/niu.c u64 val = nr64(TX_CS(channel)); val 4580 drivers/net/ethernet/sun/niu.c val |= TX_CS_RST; val 4581 drivers/net/ethernet/sun/niu.c nw64(TX_CS(channel), val); val 4592 drivers/net/ethernet/sun/niu.c u64 val; val 4602 drivers/net/ethernet/sun/niu.c val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT; val 4603 drivers/net/ethernet/sun/niu.c val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1); val 4604 drivers/net/ethernet/sun/niu.c nw64(TX_LOG_PAGE_VLD(channel), val); val 4614 drivers/net/ethernet/sun/niu.c u64 val, mask; val 4617 drivers/net/ethernet/sun/niu.c val = nr64(TXC_CONTROL); val 4620 drivers/net/ethernet/sun/niu.c val |= TXC_CONTROL_ENABLE | mask; val 4622 drivers/net/ethernet/sun/niu.c val &= ~mask; val 4623 drivers/net/ethernet/sun/niu.c if ((val & ~TXC_CONTROL_ENABLE) == 0) val 4624 drivers/net/ethernet/sun/niu.c val &= ~TXC_CONTROL_ENABLE; val 4626 drivers/net/ethernet/sun/niu.c nw64(TXC_CONTROL, val); val 4633 drivers/net/ethernet/sun/niu.c u64 val; val 4636 drivers/net/ethernet/sun/niu.c val = nr64(TXC_INT_MASK); val 4637 drivers/net/ethernet/sun/niu.c val &= ~TXC_INT_MASK_VAL(np->port); val 4638 drivers/net/ethernet/sun/niu.c val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port)); val 4644 drivers/net/ethernet/sun/niu.c u64 val = 0; val 4650 drivers/net/ethernet/sun/niu.c val |= (1 << np->tx_rings[i].tx_channel); val 4652 drivers/net/ethernet/sun/niu.c nw64(TXC_PORT_DMA(np->port), val); val 4658 drivers/net/ethernet/sun/niu.c u64 val, ring_len; val 4689 drivers/net/ethernet/sun/niu.c val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) | val 4691 drivers/net/ethernet/sun/niu.c nw64(TX_RNG_CFIG(channel), val); val 4730 drivers/net/ethernet/sun/niu.c u64 val; val 4734 drivers/net/ethernet/sun/niu.c val = PT_DRR_WEIGHT_DEFAULT_10G; val 4739 drivers/net/ethernet/sun/niu.c val = PT_DRR_WEIGHT_DEFAULT_1G; val 4742 drivers/net/ethernet/sun/niu.c nw64(PT_DRR_WT(np->port), val); val 4778 drivers/net/ethernet/sun/niu.c u64 val; val 4788 drivers/net/ethernet/sun/niu.c val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT; val 4789 drivers/net/ethernet/sun/niu.c val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1); val 4790 drivers/net/ethernet/sun/niu.c nw64(RX_LOG_PAGE_VLD(channel), val); val 4797 drivers/net/ethernet/sun/niu.c u64 val; val 4799 drivers/net/ethernet/sun/niu.c val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) | val 4803 drivers/net/ethernet/sun/niu.c nw64(RDC_RED_PARA(rp->rx_channel), val); val 4808 drivers/net/ethernet/sun/niu.c u64 val = 0; val 4813 drivers/net/ethernet/sun/niu.c val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT); val 4816 drivers/net/ethernet/sun/niu.c val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT); val 4819 drivers/net/ethernet/sun/niu.c val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT); val 4822 drivers/net/ethernet/sun/niu.c val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT); val 4827 drivers/net/ethernet/sun/niu.c val |= RBR_CFIG_B_VLD2; val 4830 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT); val 4833 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT); val 4836 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT); val 4839 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT); val 4845 drivers/net/ethernet/sun/niu.c val |= RBR_CFIG_B_VLD1; val 4848 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT); val 4851 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT); val 4854 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT); val 4857 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT); val 4863 drivers/net/ethernet/sun/niu.c val |= RBR_CFIG_B_VLD0; val 4866 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT); val 4869 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT); val 4872 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT); val 4875 drivers/net/ethernet/sun/niu.c val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT); val 4882 drivers/net/ethernet/sun/niu.c *ret = val; val 4888 drivers/net/ethernet/sun/niu.c u64 val = nr64(RXDMA_CFIG1(channel)); val 4892 drivers/net/ethernet/sun/niu.c val |= RXDMA_CFIG1_EN; val 4894 drivers/net/ethernet/sun/niu.c val &= ~RXDMA_CFIG1_EN; val 4895 drivers/net/ethernet/sun/niu.c nw64(RXDMA_CFIG1(channel), val); val 4911 drivers/net/ethernet/sun/niu.c u64 val; val 4936 drivers/net/ethernet/sun/niu.c err = niu_compute_rbr_cfig_b(rp, &val); val 4939 drivers/net/ethernet/sun/niu.c nw64(RBR_CFIG_B(channel), val); val 4954 drivers/net/ethernet/sun/niu.c val = nr64(RX_DMA_CTL_STAT(channel)); val 4955 drivers/net/ethernet/sun/niu.c val |= RX_DMA_CTL_STAT_RBR_EMPTY; val 4956 drivers/net/ethernet/sun/niu.c nw64(RX_DMA_CTL_STAT(channel), val); val 5124 drivers/net/ethernet/sun/niu.c u64 val = nr64(RESET_CFIFO); val 5126 drivers/net/ethernet/sun/niu.c val |= RESET_CFIFO_RST(np->port); val 5127 drivers/net/ethernet/sun/niu.c nw64(RESET_CFIFO, val); val 5130 drivers/net/ethernet/sun/niu.c val &= ~RESET_CFIFO_RST(np->port); val 5131 drivers/net/ethernet/sun/niu.c nw64(RESET_CFIFO, val); val 5173 drivers/net/ethernet/sun/niu.c u64 val = nr64_ipp(IPP_CFIG); val 5175 drivers/net/ethernet/sun/niu.c nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W); val 5182 drivers/net/ethernet/sun/niu.c nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W); val 5203 drivers/net/ethernet/sun/niu.c u64 data[5], rbuf[5], val; val 5240 drivers/net/ethernet/sun/niu.c val = nr64_ipp(IPP_CFIG); val 5241 drivers/net/ethernet/sun/niu.c val &= ~IPP_CFIG_IP_MAX_PKT; val 5242 drivers/net/ethernet/sun/niu.c val |= (IPP_CFIG_IPP_ENABLE | val 5247 drivers/net/ethernet/sun/niu.c nw64_ipp(IPP_CFIG, val); val 5254 drivers/net/ethernet/sun/niu.c u64 val; val 5255 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_CONFIG); val 5260 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_LED_POLARITY; val 5261 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_FORCE_LED_ON; val 5263 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_FORCE_LED_ON; val 5264 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_LED_POLARITY; val 5268 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 5274 drivers/net/ethernet/sun/niu.c u64 val; val 5277 drivers/net/ethernet/sun/niu.c val = nr64(MIF_CONFIG); val 5278 drivers/net/ethernet/sun/niu.c val |= MIF_CONFIG_ATCA_GE; val 5279 drivers/net/ethernet/sun/niu.c nw64(MIF_CONFIG, val); val 5282 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_CONFIG); val 5283 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; val 5285 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_TX_OUTPUT_EN; val 5288 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; val 5289 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_LOOPBACK; val 5291 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_LOOPBACK; val 5295 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_LFS_DISABLE; val 5297 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_LFS_DISABLE; val 5300 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_1G_PCS_BYPASS; val 5302 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_1G_PCS_BYPASS; val 5305 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; val 5308 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_SEL_CLK_25MHZ; val 5310 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_SEL_CLK_25MHZ; val 5312 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 5314 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_CONFIG); val 5315 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_MODE_MASK; val 5317 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_MODE_XGMII; val 5320 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_MODE_GMII; val 5322 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_MODE_MII; val 5325 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 5331 drivers/net/ethernet/sun/niu.c u64 val; val 5333 drivers/net/ethernet/sun/niu.c val = BMAC_XIF_CONFIG_TX_OUTPUT_EN; val 5336 drivers/net/ethernet/sun/niu.c val |= BMAC_XIF_CONFIG_MII_LOOPBACK; val 5338 drivers/net/ethernet/sun/niu.c val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK; val 5341 drivers/net/ethernet/sun/niu.c val |= BMAC_XIF_CONFIG_GMII_MODE; val 5343 drivers/net/ethernet/sun/niu.c val &= ~BMAC_XIF_CONFIG_GMII_MODE; val 5345 drivers/net/ethernet/sun/niu.c val &= ~(BMAC_XIF_CONFIG_LINK_LED | val 5351 drivers/net/ethernet/sun/niu.c val |= BMAC_XIF_CONFIG_25MHZ_CLOCK; val 5353 drivers/net/ethernet/sun/niu.c val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK; val 5355 drivers/net/ethernet/sun/niu.c nw64_mac(BMAC_XIF_CONFIG, val); val 5369 drivers/net/ethernet/sun/niu.c u64 val = nr64_pcs(PCS_MII_CTL); val 5370 drivers/net/ethernet/sun/niu.c val |= PCS_MII_CTL_RST; val 5371 drivers/net/ethernet/sun/niu.c nw64_pcs(PCS_MII_CTL, val); val 5372 drivers/net/ethernet/sun/niu.c while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) { val 5374 drivers/net/ethernet/sun/niu.c val = nr64_pcs(PCS_MII_CTL); val 5381 drivers/net/ethernet/sun/niu.c u64 val = nr64_xpcs(XPCS_CONTROL1); val 5382 drivers/net/ethernet/sun/niu.c val |= XPCS_CONTROL1_RESET; val 5383 drivers/net/ethernet/sun/niu.c nw64_xpcs(XPCS_CONTROL1, val); val 5384 drivers/net/ethernet/sun/niu.c while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) { val 5386 drivers/net/ethernet/sun/niu.c val = nr64_xpcs(XPCS_CONTROL1); val 5393 drivers/net/ethernet/sun/niu.c u64 val; val 5413 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_CONFIG); val 5414 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; val 5415 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 5419 drivers/net/ethernet/sun/niu.c val = nr64_xpcs(XPCS_CONTROL1); val 5421 drivers/net/ethernet/sun/niu.c val |= XPCS_CONTROL1_LOOPBACK; val 5423 drivers/net/ethernet/sun/niu.c val &= ~XPCS_CONTROL1_LOOPBACK; val 5424 drivers/net/ethernet/sun/niu.c nw64_xpcs(XPCS_CONTROL1, val); val 5493 drivers/net/ethernet/sun/niu.c u64 val; val 5495 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_MIN); val 5496 drivers/net/ethernet/sun/niu.c val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE | val 5498 drivers/net/ethernet/sun/niu.c val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT); val 5499 drivers/net/ethernet/sun/niu.c val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT); val 5500 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_MIN, val); val 5506 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_IPG); val 5508 drivers/net/ethernet/sun/niu.c val &= ~XMAC_IPG_IPG_XGMII; val 5509 drivers/net/ethernet/sun/niu.c val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT); val 5511 drivers/net/ethernet/sun/niu.c val &= ~XMAC_IPG_IPG_MII_GMII; val 5512 drivers/net/ethernet/sun/niu.c val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT); val 5514 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_IPG, val); val 5516 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_CONFIG); val 5517 drivers/net/ethernet/sun/niu.c val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC | val 5521 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 5529 drivers/net/ethernet/sun/niu.c u64 val; val 5538 drivers/net/ethernet/sun/niu.c val = nr64_mac(BTXMAC_CONFIG); val 5539 drivers/net/ethernet/sun/niu.c val &= ~(BTXMAC_CONFIG_FCS_DISABLE | val 5541 drivers/net/ethernet/sun/niu.c nw64_mac(BTXMAC_CONFIG, val); val 5623 drivers/net/ethernet/sun/niu.c u64 val; val 5636 drivers/net/ethernet/sun/niu.c val = nr64_mac(XMAC_CONFIG); val 5637 drivers/net/ethernet/sun/niu.c val &= ~(XMAC_CONFIG_RX_MAC_ENABLE | val 5649 drivers/net/ethernet/sun/niu.c val |= (XMAC_CONFIG_HASH_FILTER_EN); val 5650 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 5675 drivers/net/ethernet/sun/niu.c u64 val; val 5688 drivers/net/ethernet/sun/niu.c val = nr64_mac(BRXMAC_CONFIG); val 5689 drivers/net/ethernet/sun/niu.c val &= ~(BRXMAC_CONFIG_ENABLE | val 5696 drivers/net/ethernet/sun/niu.c val |= (BRXMAC_CONFIG_HASH_FILT_EN); val 5697 drivers/net/ethernet/sun/niu.c nw64_mac(BRXMAC_CONFIG, val); val 5699 drivers/net/ethernet/sun/niu.c val = nr64_mac(BMAC_ADDR_CMPEN); val 5700 drivers/net/ethernet/sun/niu.c val |= BMAC_ADDR_CMPEN_EN0; val 5701 drivers/net/ethernet/sun/niu.c nw64_mac(BMAC_ADDR_CMPEN, val); val 5716 drivers/net/ethernet/sun/niu.c u64 val = nr64_mac(XMAC_CONFIG); val 5719 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_TX_ENABLE; val 5721 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_TX_ENABLE; val 5722 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 5727 drivers/net/ethernet/sun/niu.c u64 val = nr64_mac(BTXMAC_CONFIG); val 5730 drivers/net/ethernet/sun/niu.c val |= BTXMAC_CONFIG_ENABLE; val 5732 drivers/net/ethernet/sun/niu.c val &= ~BTXMAC_CONFIG_ENABLE; val 5733 drivers/net/ethernet/sun/niu.c nw64_mac(BTXMAC_CONFIG, val); val 5746 drivers/net/ethernet/sun/niu.c u64 val = nr64_mac(XMAC_CONFIG); val 5748 drivers/net/ethernet/sun/niu.c val &= ~(XMAC_CONFIG_HASH_FILTER_EN | val 5752 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_HASH_FILTER_EN; val 5754 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_PROMISCUOUS; val 5757 drivers/net/ethernet/sun/niu.c val |= XMAC_CONFIG_RX_MAC_ENABLE; val 5759 drivers/net/ethernet/sun/niu.c val &= ~XMAC_CONFIG_RX_MAC_ENABLE; val 5760 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 5765 drivers/net/ethernet/sun/niu.c u64 val = nr64_mac(BRXMAC_CONFIG); val 5767 drivers/net/ethernet/sun/niu.c val &= ~(BRXMAC_CONFIG_HASH_FILT_EN | val 5771 drivers/net/ethernet/sun/niu.c val |= BRXMAC_CONFIG_HASH_FILT_EN; val 5773 drivers/net/ethernet/sun/niu.c val |= BRXMAC_CONFIG_PROMISC; val 5776 drivers/net/ethernet/sun/niu.c val |= BRXMAC_CONFIG_ENABLE; val 5778 drivers/net/ethernet/sun/niu.c val &= ~BRXMAC_CONFIG_ENABLE; val 5779 drivers/net/ethernet/sun/niu.c nw64_mac(BRXMAC_CONFIG, val); val 5892 drivers/net/ethernet/sun/niu.c u64 rd, wr, val; val 5909 drivers/net/ethernet/sun/niu.c val = nr64_ipp(IPP_CFIG); val 5910 drivers/net/ethernet/sun/niu.c val &= ~(IPP_CFIG_IPP_ENABLE | val 5914 drivers/net/ethernet/sun/niu.c nw64_ipp(IPP_CFIG, val); val 6554 drivers/net/ethernet/sun/niu.c __be16 val = vp->h_vlan_encapsulated_proto; val 6556 drivers/net/ethernet/sun/niu.c eth_proto_inner = be16_to_cpu(val); val 6863 drivers/net/ethernet/sun/niu.c u32 offset, len, val; val 6883 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_NCR((offset - b_offset) / 4)); val 6884 drivers/net/ethernet/sun/niu.c memcpy(data, ((char *)&val) + b_offset, b_count); val 6890 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_NCR(offset / 4)); val 6891 drivers/net/ethernet/sun/niu.c memcpy(data, &val, 4); val 6897 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_NCR(offset / 4)); val 6898 drivers/net/ethernet/sun/niu.c memcpy(data, &val, len); val 7822 drivers/net/ethernet/sun/niu.c static void niu_led_state_restore(struct niu *np, u64 val) val 7825 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_CONFIG, val); val 7827 drivers/net/ethernet/sun/niu.c nw64_mac(BMAC_XIF_CONFIG, val); val 7832 drivers/net/ethernet/sun/niu.c u64 val, reg, bit; val 7842 drivers/net/ethernet/sun/niu.c val = nr64_mac(reg); val 7844 drivers/net/ethernet/sun/niu.c val |= bit; val 7846 drivers/net/ethernet/sun/niu.c val &= ~bit; val 7847 drivers/net/ethernet/sun/niu.c nw64_mac(reg, val); val 7994 drivers/net/ethernet/sun/niu.c u16 val; val 7998 drivers/net/ethernet/sun/niu.c val = (err << 8); val 8002 drivers/net/ethernet/sun/niu.c val |= (err & 0xff); val 8004 drivers/net/ethernet/sun/niu.c return val; val 8010 drivers/net/ethernet/sun/niu.c u16 val; val 8015 drivers/net/ethernet/sun/niu.c val = (err & 0xff); val 8020 drivers/net/ethernet/sun/niu.c val |= (err & 0xff) << 8; val 8022 drivers/net/ethernet/sun/niu.c return val; val 8355 drivers/net/ethernet/sun/niu.c u64 val, sum; val 8358 drivers/net/ethernet/sun/niu.c val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ); val 8359 drivers/net/ethernet/sun/niu.c val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT; val 8360 drivers/net/ethernet/sun/niu.c len = val / 4; val 8365 drivers/net/ethernet/sun/niu.c "SPROM: Image size %llu\n", (unsigned long long)val); val 8369 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_NCR(i)); val 8370 drivers/net/ethernet/sun/niu.c sum += (val >> 0) & 0xff; val 8371 drivers/net/ethernet/sun/niu.c sum += (val >> 8) & 0xff; val 8372 drivers/net/ethernet/sun/niu.c sum += (val >> 16) & 0xff; val 8373 drivers/net/ethernet/sun/niu.c sum += (val >> 24) & 0xff; val 8382 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_PHY_TYPE); val 8385 drivers/net/ethernet/sun/niu.c val8 = (val & ESPC_PHY_TYPE_PORT0) >> val 8389 drivers/net/ethernet/sun/niu.c val8 = (val & ESPC_PHY_TYPE_PORT1) >> val 8393 drivers/net/ethernet/sun/niu.c val8 = (val & ESPC_PHY_TYPE_PORT2) >> val 8397 drivers/net/ethernet/sun/niu.c val8 = (val & ESPC_PHY_TYPE_PORT3) >> val 8442 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_MAC_ADDR0); val 8444 drivers/net/ethernet/sun/niu.c "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val); val 8445 drivers/net/ethernet/sun/niu.c dev->dev_addr[0] = (val >> 0) & 0xff; val 8446 drivers/net/ethernet/sun/niu.c dev->dev_addr[1] = (val >> 8) & 0xff; val 8447 drivers/net/ethernet/sun/niu.c dev->dev_addr[2] = (val >> 16) & 0xff; val 8448 drivers/net/ethernet/sun/niu.c dev->dev_addr[3] = (val >> 24) & 0xff; val 8450 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_MAC_ADDR1); val 8452 drivers/net/ethernet/sun/niu.c "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val); val 8453 drivers/net/ethernet/sun/niu.c dev->dev_addr[4] = (val >> 0) & 0xff; val 8454 drivers/net/ethernet/sun/niu.c dev->dev_addr[5] = (val >> 8) & 0xff; val 8467 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_MOD_STR_LEN); val 8469 drivers/net/ethernet/sun/niu.c "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val); val 8470 drivers/net/ethernet/sun/niu.c if (val >= 8 * 4) val 8473 drivers/net/ethernet/sun/niu.c for (i = 0; i < val; i += 4) { val 8481 drivers/net/ethernet/sun/niu.c np->vpd.model[val] = '\0'; val 8483 drivers/net/ethernet/sun/niu.c val = nr64(ESPC_BD_MOD_STR_LEN); val 8485 drivers/net/ethernet/sun/niu.c "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val); val 8486 drivers/net/ethernet/sun/niu.c if (val >= 4 * 4) val 8489 drivers/net/ethernet/sun/niu.c for (i = 0; i < val; i += 4) { val 8497 drivers/net/ethernet/sun/niu.c np->vpd.board_model[val] = '\0'; val 8790 drivers/net/ethernet/sun/niu.c u32 val; val 8801 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_1G, 0) | val 8809 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_10G, 0) | val 8815 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_10G, 0) | val 8818 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_1G, 0) | val 8840 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_10G, 0) | val 8847 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_10G, 0) | val 8852 drivers/net/ethernet/sun/niu.c val = phy_encode(PORT_TYPE_10G, np->port); val 8866 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_10G, 0) | val 8871 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_1G, 0) | val 8885 drivers/net/ethernet/sun/niu.c val = (phy_encode(PORT_TYPE_1G, 0) | val 8898 drivers/net/ethernet/sun/niu.c parent->port_phy = val; val 349 drivers/net/ethernet/sun/sunbmac.c int reg, unsigned short val) val 354 drivers/net/ethernet/sun/sunbmac.c val &= 0xffff; val 382 drivers/net/ethernet/sun/sunbmac.c write_tcvr_bit(bp, tregs, (val >> shift) & 1); val 154 drivers/net/ethernet/sun/sungem.c static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val) val 164 drivers/net/ethernet/sun/sungem.c cmd |= (val & MIF_FRAME_DATA); val 176 drivers/net/ethernet/sun/sungem.c static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val) val 179 drivers/net/ethernet/sun/sungem.c __sungem_phy_write(gp, mii_id, reg, val & 0xffff); val 182 drivers/net/ethernet/sun/sungem.c static inline void sungem_phy_write(struct gem *gp, int reg, u16 val) val 184 drivers/net/ethernet/sun/sungem.c __sungem_phy_write(gp, gp->mii_phy_addr, reg, val); val 364 drivers/net/ethernet/sun/sungem.c u32 val; val 436 drivers/net/ethernet/sun/sungem.c val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) | val 438 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + RXDMA_CFG); val 447 drivers/net/ethernet/sun/sungem.c val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); val 448 drivers/net/ethernet/sun/sungem.c val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); val 449 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + RXDMA_PTHRESH); val 450 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + RXDMA_CFG); val 451 drivers/net/ethernet/sun/sungem.c writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); val 453 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_RXCFG); val 454 drivers/net/ethernet/sun/sungem.c writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); val 1121 drivers/net/ethernet/sun/sungem.c u32 val; val 1124 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + PCS_MIICTRL); val 1125 drivers/net/ethernet/sun/sungem.c val |= PCS_MIICTRL_RST; val 1126 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + PCS_MIICTRL); val 1140 drivers/net/ethernet/sun/sungem.c u32 val; val 1145 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + PCS_CFG); val 1146 drivers/net/ethernet/sun/sungem.c val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO); val 1147 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + PCS_CFG); val 1152 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + PCS_MIIADV); val 1153 drivers/net/ethernet/sun/sungem.c val |= (PCS_MIIADV_FD | PCS_MIIADV_HD | val 1155 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + PCS_MIIADV); val 1160 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + PCS_MIICTRL); val 1161 drivers/net/ethernet/sun/sungem.c val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE); val 1162 drivers/net/ethernet/sun/sungem.c val &= ~PCS_MIICTRL_WB; val 1163 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + PCS_MIICTRL); val 1165 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + PCS_CFG); val 1166 drivers/net/ethernet/sun/sungem.c val |= PCS_CFG_ENABLE; val 1167 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + PCS_CFG); val 1173 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + PCS_SCTRL); val 1175 drivers/net/ethernet/sun/sungem.c val &= ~PCS_SCTRL_LOOP; val 1177 drivers/net/ethernet/sun/sungem.c val |= PCS_SCTRL_LOOP; val 1178 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + PCS_SCTRL); val 1186 drivers/net/ethernet/sun/sungem.c u32 val; val 1199 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + GREG_SWRST); val 1202 drivers/net/ethernet/sun/sungem.c } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST)); val 1213 drivers/net/ethernet/sun/sungem.c u32 val; val 1216 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + TXDMA_CFG); val 1217 drivers/net/ethernet/sun/sungem.c writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); val 1218 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + RXDMA_CFG); val 1219 drivers/net/ethernet/sun/sungem.c writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); val 1220 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_TXCFG); val 1221 drivers/net/ethernet/sun/sungem.c writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); val 1222 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_RXCFG); val 1223 drivers/net/ethernet/sun/sungem.c writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); val 1237 drivers/net/ethernet/sun/sungem.c u32 val; val 1240 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + TXDMA_CFG); val 1241 drivers/net/ethernet/sun/sungem.c writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); val 1242 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + RXDMA_CFG); val 1243 drivers/net/ethernet/sun/sungem.c writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); val 1244 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_TXCFG); val 1245 drivers/net/ethernet/sun/sungem.c writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); val 1246 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_RXCFG); val 1247 drivers/net/ethernet/sun/sungem.c writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); val 1351 drivers/net/ethernet/sun/sungem.c u32 val; val 1381 drivers/net/ethernet/sun/sungem.c val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU); val 1383 drivers/net/ethernet/sun/sungem.c val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL); val 1387 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + MAC_TXCFG); val 1389 drivers/net/ethernet/sun/sungem.c val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED); val 1393 drivers/net/ethernet/sun/sungem.c val |= MAC_XIFCFG_DISE; val 1395 drivers/net/ethernet/sun/sungem.c val |= MAC_XIFCFG_FLED; val 1399 drivers/net/ethernet/sun/sungem.c val |= (MAC_XIFCFG_GMII); val 1401 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + MAC_XIFCFG); val 1407 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_TXCFG); val 1408 drivers/net/ethernet/sun/sungem.c writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); val 1410 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_RXCFG); val 1411 drivers/net/ethernet/sun/sungem.c writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); val 1413 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_TXCFG); val 1414 drivers/net/ethernet/sun/sungem.c writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); val 1416 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_RXCFG); val 1417 drivers/net/ethernet/sun/sungem.c writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); val 1432 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + MAC_MCCFG); val 1434 drivers/net/ethernet/sun/sungem.c val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE); val 1436 drivers/net/ethernet/sun/sungem.c val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE); val 1437 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + MAC_MCCFG); val 1514 drivers/net/ethernet/sun/sungem.c u32 val = readl(gp->regs + PCS_MIISTAT); val 1516 drivers/net/ethernet/sun/sungem.c if (!(val & PCS_MIISTAT_LS)) val 1517 drivers/net/ethernet/sun/sungem.c val = readl(gp->regs + PCS_MIISTAT); val 1519 drivers/net/ethernet/sun/sungem.c if ((val & PCS_MIISTAT_LS) != 0) { val 1709 drivers/net/ethernet/sun/sungem.c u32 val; val 1714 drivers/net/ethernet/sun/sungem.c val = PCS_DMODE_MGM; val 1716 drivers/net/ethernet/sun/sungem.c val = PCS_DMODE_SM | PCS_DMODE_GMOE; val 1718 drivers/net/ethernet/sun/sungem.c val = PCS_DMODE_ESM; val 1721 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + PCS_DMODE); val 1754 drivers/net/ethernet/sun/sungem.c u32 val; val 1756 drivers/net/ethernet/sun/sungem.c val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE); val 1757 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + TXDMA_CFG); val 1765 drivers/net/ethernet/sun/sungem.c val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) | val 1767 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + RXDMA_CFG); val 1774 drivers/net/ethernet/sun/sungem.c val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); val 1775 drivers/net/ethernet/sun/sungem.c val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); val 1776 drivers/net/ethernet/sun/sungem.c writel(val, gp->regs + RXDMA_PTHRESH); val 187 drivers/net/ethernet/sun/sunhme.c static void sbus_hme_write32(void __iomem *reg, u32 val) val 189 drivers/net/ethernet/sun/sunhme.c sbus_writel(val, reg); val 216 drivers/net/ethernet/sun/sunhme.c static void pci_hme_write32(void __iomem *reg, u32 val) val 218 drivers/net/ethernet/sun/sunhme.c writel(val, reg); val 103 drivers/net/ethernet/sun/sunvnet_common.h unsigned int val = mac[4] ^ mac[5]; val 105 drivers/net/ethernet/sun/sunvnet_common.h return val & (VNET_PORT_HASH_MASK); val 246 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int val = enable ? 1 : 0; val 251 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval == val) val 259 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c MAC_PFR_PR_LEN, val); val 276 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int val = enable ? 1 : 0; val 281 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval == val) val 289 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c MAC_PFR_PM_LEN, val); val 394 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int val; val 397 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c val = (pdata->netdev->mtu > XLGMAC_STD_PACKET_MTU) ? 1 : 0; val 401 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c MAC_RCR_JE_LEN, val); val 1458 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int val) val 1466 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c MTL_Q_RQOMR_RTC_LEN, val); val 1692 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int val) val 1700 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c MTL_Q_TQOMR_TTC_LEN, val); val 1708 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int val) val 1716 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c MTL_Q_RQOMR_RSF_LEN, val); val 1724 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int val) val 1732 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c MTL_Q_TQOMR_TSF_LEN, val); val 1843 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u64 val; val 1858 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c val = (u64)readl(pdata->mac_regs + reg_lo); val 1861 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c val |= ((u64)readl(pdata->mac_regs + reg_lo + 4) << 32); val 1863 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c return val; val 2280 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int index, unsigned int val) val 2295 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(val, pdata->mac_regs + MAC_RSSDR); val 113 drivers/net/ethernet/synopsys/dwc-xlgmac.h #define XLGMAC_SET_REG_BITS(var, pos, len, val) ({ \ val 117 drivers/net/ethernet/synopsys/dwc-xlgmac.h typeof(val) _val = (val); \ val 122 drivers/net/ethernet/synopsys/dwc-xlgmac.h #define XLGMAC_SET_REG_BITS_LE(var, pos, len, val) ({ \ val 126 drivers/net/ethernet/synopsys/dwc-xlgmac.h typeof(val) _val = (val); \ val 457 drivers/net/ethernet/synopsys/dwc-xlgmac.h unsigned int val); val 459 drivers/net/ethernet/synopsys/dwc-xlgmac.h unsigned int val); val 463 drivers/net/ethernet/synopsys/dwc-xlgmac.h unsigned int val); val 465 drivers/net/ethernet/synopsys/dwc-xlgmac.h unsigned int val); val 363 drivers/net/ethernet/tehuti/tehuti.c u32 val; val 370 drivers/net/ethernet/tehuti/tehuti.c val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]); val 371 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, regUNC_MAC2_A, val); val 372 drivers/net/ethernet/tehuti/tehuti.c val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]); val 373 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, regUNC_MAC1_A, val); val 374 drivers/net/ethernet/tehuti/tehuti.c val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]); val 375 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, regUNC_MAC0_A, val); val 451 drivers/net/ethernet/tehuti/tehuti.c u32 val, i; val 455 drivers/net/ethernet/tehuti/tehuti.c val = readl(regs + regCLKPLL); val 456 drivers/net/ethernet/tehuti/tehuti.c writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL); val 458 drivers/net/ethernet/tehuti/tehuti.c val = readl(regs + regCLKPLL); val 459 drivers/net/ethernet/tehuti/tehuti.c writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL); val 474 drivers/net/ethernet/tehuti/tehuti.c u32 val, i; val 479 drivers/net/ethernet/tehuti/tehuti.c val = READ_REG(priv, regCLKPLL); val 480 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8); val 482 drivers/net/ethernet/tehuti/tehuti.c val = READ_REG(priv, regCLKPLL); val 483 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST); val 708 drivers/net/ethernet/tehuti/tehuti.c u32 reg, bit, val; val 718 drivers/net/ethernet/tehuti/tehuti.c val = READ_REG(priv, reg); val 719 drivers/net/ethernet/tehuti/tehuti.c DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit); val 721 drivers/net/ethernet/tehuti/tehuti.c val |= bit; val 723 drivers/net/ethernet/tehuti/tehuti.c val &= ~bit; val 724 drivers/net/ethernet/tehuti/tehuti.c DBG2("new val %x\n", val); val 725 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, reg, val); val 792 drivers/net/ethernet/tehuti/tehuti.c u32 reg, val; val 813 drivers/net/ethernet/tehuti/tehuti.c val = READ_REG(priv, reg); val 814 drivers/net/ethernet/tehuti/tehuti.c val |= (1 << (hash % 32)); val 815 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, reg, val); val 863 drivers/net/ethernet/tehuti/tehuti.c u64 val; val 865 drivers/net/ethernet/tehuti/tehuti.c val = READ_REG(priv, reg); val 866 drivers/net/ethernet/tehuti/tehuti.c val |= ((u64) READ_REG(priv, reg + 8)) << 32; val 867 drivers/net/ethernet/tehuti/tehuti.c return val; val 98 drivers/net/ethernet/tehuti/tehuti.h #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) val 144 drivers/net/ethernet/ti/cpmac.c #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \ val 267 drivers/net/ethernet/ti/cpmac.c u32 val; val 273 drivers/net/ethernet/ti/cpmac.c while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY) val 276 drivers/net/ethernet/ti/cpmac.c return MDIO_DATA(val); val 280 drivers/net/ethernet/ti/cpmac.c int reg, u16 val) val 285 drivers/net/ethernet/ti/cpmac.c MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val)); val 1028 drivers/net/ethernet/ti/cpsw.c u32 shift, mask, val; val 1030 drivers/net/ethernet/ti/cpsw.c val = readl_relaxed(&cpsw->regs->ptype); val 1035 drivers/net/ethernet/ti/cpsw.c val = val & mask; val 1037 drivers/net/ethernet/ti/cpsw.c return !val; val 1044 drivers/net/ethernet/ti/cpsw.c u32 shift, mask, val; val 1046 drivers/net/ethernet/ti/cpsw.c val = readl_relaxed(&cpsw->regs->ptype); val 1051 drivers/net/ethernet/ti/cpsw.c val = on ? val | mask : val & ~mask; val 1053 drivers/net/ethernet/ti/cpsw.c writel_relaxed(val, &cpsw->regs->ptype); val 1424 drivers/net/ethernet/ti/cpsw.c u32 val = 0, send_pct, shift; val 1453 drivers/net/ethernet/ti/cpsw.c val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10); val 1454 drivers/net/ethernet/ti/cpsw.c if (!val) val 1455 drivers/net/ethernet/ti/cpsw.c val = 1; val 1457 drivers/net/ethernet/ti/cpsw.c send_pct |= val << shift; val 1458 drivers/net/ethernet/ti/cpsw.c pct += val; val 1473 drivers/net/ethernet/ti/cpsw.c DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100)); val 1485 drivers/net/ethernet/ti/cpsw.c u32 tx_in_ctl_rg, val; val 1499 drivers/net/ethernet/ti/cpsw.c val = slave_read(slave, tx_in_ctl_rg); val 1502 drivers/net/ethernet/ti/cpsw.c val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT); val 1505 drivers/net/ethernet/ti/cpsw.c val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT); val 1509 drivers/net/ethernet/ti/cpsw.c val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT; val 1516 drivers/net/ethernet/ti/cpsw.c val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); val 1518 drivers/net/ethernet/ti/cpsw.c val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); val 1519 drivers/net/ethernet/ti/cpsw.c slave_write(slave, val, tx_in_ctl_rg); val 313 drivers/net/ethernet/ti/cpsw_priv.h static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) val 315 drivers/net/ethernet/ti/cpsw_priv.h writel_relaxed(val, slave->regs + offset); val 191 drivers/net/ethernet/ti/cpsw_sl.c int val; val 199 drivers/net/ethernet/ti/cpsw_sl.c val = readl(sl->sl_base + sl->regs[reg]); val 200 drivers/net/ethernet/ti/cpsw_sl.c dev_dbg(sl->dev, "cpsw_sl: reg: %04X r 0x%08X\n", sl->regs[reg], val); val 201 drivers/net/ethernet/ti/cpsw_sl.c return val; val 204 drivers/net/ethernet/ti/cpsw_sl.c void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val) val 212 drivers/net/ethernet/ti/cpsw_sl.c dev_dbg(sl->dev, "cpsw_sl: reg: %04X w 0x%08X\n", sl->regs[reg], val); val 213 drivers/net/ethernet/ti/cpsw_sl.c writel(val, sl->sl_base + sl->regs[reg]); val 276 drivers/net/ethernet/ti/cpsw_sl.c u32 val; val 284 drivers/net/ethernet/ti/cpsw_sl.c val = cpsw_sl_reg_read(sl, CPSW_SL_MACCONTROL); val 285 drivers/net/ethernet/ti/cpsw_sl.c val |= ctl_funcs; val 286 drivers/net/ethernet/ti/cpsw_sl.c cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, val); val 293 drivers/net/ethernet/ti/cpsw_sl.c u32 val; val 301 drivers/net/ethernet/ti/cpsw_sl.c val = cpsw_sl_reg_read(sl, CPSW_SL_MACCONTROL); val 302 drivers/net/ethernet/ti/cpsw_sl.c val &= ~ctl_funcs; val 303 drivers/net/ethernet/ti/cpsw_sl.c cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, val); val 71 drivers/net/ethernet/ti/cpsw_sl.h void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val); val 192 drivers/net/ethernet/ti/cpts.c u64 val = 0; val 206 drivers/net/ethernet/ti/cpts.c val = event->low; val 211 drivers/net/ethernet/ti/cpts.c return val; val 309 drivers/net/ethernet/ti/davinci_cpdma.c u32 val; val 323 drivers/net/ethernet/ti/davinci_cpdma.c val = dma_reg_read(ctlr, info->reg); val 324 drivers/net/ethernet/ti/davinci_cpdma.c val &= ~(info->mask << info->shift); val 325 drivers/net/ethernet/ti/davinci_cpdma.c val |= (value & info->mask) << info->shift; val 326 drivers/net/ethernet/ti/davinci_cpdma.c dma_reg_write(ctlr, info->reg, val); val 362 drivers/net/ethernet/ti/davinci_emac.c #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) val 365 drivers/net/ethernet/ti/davinci_emac.c #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) val 1013 drivers/net/ethernet/ti/davinci_emac.c u32 val; val 1014 drivers/net/ethernet/ti/davinci_emac.c val = ((mac_addr[5] << 8) | (mac_addr[4])); val 1015 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_MACSRCADDRLO, val); val 1017 drivers/net/ethernet/ti/davinci_emac.c val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ val 1019 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_MACSRCADDRHI, val); val 1020 drivers/net/ethernet/ti/davinci_emac.c val = emac_read(EMAC_RXUNICASTSET); val 1021 drivers/net/ethernet/ti/davinci_emac.c val |= BIT(ch); val 1022 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_RXUNICASTSET, val); val 1023 drivers/net/ethernet/ti/davinci_emac.c val = emac_read(EMAC_RXUNICASTCLEAR); val 1024 drivers/net/ethernet/ti/davinci_emac.c val &= ~BIT(ch); val 1025 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_RXUNICASTCLEAR, val); val 1040 drivers/net/ethernet/ti/davinci_emac.c u32 val; val 1042 drivers/net/ethernet/ti/davinci_emac.c val = ((mac_addr[5] << 8) | mac_addr[4]); val 1043 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_MACADDRLO, val); val 1044 drivers/net/ethernet/ti/davinci_emac.c val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ val 1046 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_MACADDRHI, val); val 1065 drivers/net/ethernet/ti/davinci_emac.c u32 val; val 1067 drivers/net/ethernet/ti/davinci_emac.c val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ val 1069 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_MACADDRHI, val); val 1070 drivers/net/ethernet/ti/davinci_emac.c val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ val 1072 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_MACADDRLO, val); val 1150 drivers/net/ethernet/ti/davinci_emac.c u32 val, mbp_enable, mac_control; val 1198 drivers/net/ethernet/ti/davinci_emac.c val = emac_read(EMAC_MACCONTROL); val 1199 drivers/net/ethernet/ti/davinci_emac.c val |= (EMAC_MACCONTROL_GMIIEN); val 1200 drivers/net/ethernet/ti/davinci_emac.c emac_write(EMAC_MACCONTROL, val); val 216 drivers/net/ethernet/ti/davinci_mdio.c u32 val, ret; val 218 drivers/net/ethernet/ti/davinci_mdio.c ret = readl_poll_timeout(®s->control, val, val & CONTROL_IDLE, val 1865 drivers/net/ethernet/ti/netcp_ethss.c u32 val; val 1867 drivers/net/ethernet/ti/netcp_ethss.c val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en)); val 1872 drivers/net/ethernet/ti/netcp_ethss.c val &= ~GBE_STATS_CD_SEL; val 1876 drivers/net/ethernet/ti/netcp_ethss.c val |= GBE_STATS_CD_SEL; val 1883 drivers/net/ethernet/ti/netcp_ethss.c writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en)); val 2132 drivers/net/ethernet/ti/netcp_ethss.c u32 val = 0; val 2134 drivers/net/ethernet/ti/netcp_ethss.c val = readl(GBE_REG_ADDR(gbe_dev, ss_regs, rgmii_status)); val 2135 drivers/net/ethernet/ti/netcp_ethss.c *status = !!(val & RGMII_REG_STATUS_LINK); val 2903 drivers/net/ethernet/ti/netcp_ethss.c u32 reg, val; val 2933 drivers/net/ethernet/ti/netcp_ethss.c val = GBE_CTL_P0_ENABLE; val 2935 drivers/net/ethernet/ti/netcp_ethss.c val |= ETH_SW_CTL_P0_TX_CRC_REMOVE; val 2938 drivers/net/ethernet/ti/netcp_ethss.c writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, control)); val 31 drivers/net/ethernet/ti/netcp_sgmii.c static void sgmii_write_reg(void __iomem *base, int reg, u32 val) val 33 drivers/net/ethernet/ti/netcp_sgmii.c writel(val, base + reg); val 41 drivers/net/ethernet/ti/netcp_sgmii.c static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val) val 43 drivers/net/ethernet/ti/netcp_sgmii.c writel((readl(base + reg) | val), base + reg); val 35 drivers/net/ethernet/ti/netcp_xgbepcsr.c u32 val; val 134 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_phyb_1p25g_156p25mhz_cmu0[i].val, val 141 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_phyb_10p3125g_156p25mhz_cmu1[i].val, val 157 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_phyb_10p3125g_16bit_lane[i].val, val 176 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_phyb_10p3125g_comlane[i].val, val 436 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_cm_c1_c2[i].val, val 485 drivers/net/ethernet/ti/netcp_xgbepcsr.c u32 val; val 488 drivers/net/ethernet/ti/netcp_xgbepcsr.c val = readl(serdes_regs + 0xa00); val 489 drivers/net/ethernet/ti/netcp_xgbepcsr.c if (val & 0x1f) { val 2848 drivers/net/ethernet/ti/tlan.c tlan_mii_read_reg(struct net_device *dev, u16 phy, u16 reg, u16 *val) val 2908 drivers/net/ethernet/ti/tlan.c *val = tmp; val 3020 drivers/net/ethernet/ti/tlan.c tlan_mii_write_reg(struct net_device *dev, u16 phy, u16 reg, u16 val) val 3045 drivers/net/ethernet/ti/tlan.c tlan_mii_send_data(dev->base_addr, val, 16); /* send data */ val 116 drivers/net/ethernet/toshiba/spider_net.c int reg, int val) val 122 drivers/net/ethernet/toshiba/spider_net.c ((u32)reg << 16) | ((u32)val); val 520 drivers/net/ethernet/toshiba/tc35815.c static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val) val 527 drivers/net/ethernet/toshiba/tc35815.c tc_writel(val, &tr->MD_Data); val 216 drivers/net/ethernet/tundra/tsi108_eth.c int reg, u16 val) val 222 drivers/net/ethernet/tundra/tsi108_eth.c TSI_WRITE_PHY(TSI108_MAC_MII_DATAOUT, val); val 237 drivers/net/ethernet/tundra/tsi108_eth.c static void tsi108_mdio_write(struct net_device *dev, int addr, int reg, int val) val 240 drivers/net/ethernet/tundra/tsi108_eth.c tsi108_write_mii(data, reg, val); val 244 drivers/net/ethernet/tundra/tsi108_eth.c int reg, u16 val) val 250 drivers/net/ethernet/tundra/tsi108_eth.c TSI_WRITE(TSI108_MAC_MII_DATAOUT, val); val 261 drivers/net/ethernet/tundra/tsi108_eth.c int advert, lpa, val, media; val 268 drivers/net/ethernet/tundra/tsi108_eth.c val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR); val 269 drivers/net/ethernet/tundra/tsi108_eth.c if ((val & BMSR_ANEGCOMPLETE) == 0) val 456 drivers/net/ethernet/tundra/tsi108_eth.c unsigned long val; val 464 drivers/net/ethernet/tundra/tsi108_eth.c val = TSI_READ(reg) | *upper; val 477 drivers/net/ethernet/tundra/tsi108_eth.c return val; val 19 drivers/net/ethernet/tundra/tsi108_eth.h #define TSI_WRITE(offset, val) \ val 20 drivers/net/ethernet/tundra/tsi108_eth.h out_be32((data->regs + (offset)), val) val 25 drivers/net/ethernet/tundra/tsi108_eth.h #define TSI_WRITE_PHY(offset, val) \ val 26 drivers/net/ethernet/tundra/tsi108_eth.h out_be32((data->phyregs + (offset)), val) val 414 drivers/net/ethernet/via/via-velocity.c static void velocity_set_int_opt(int *opt, int val, int min, int max, int def, val 417 drivers/net/ethernet/via/via-velocity.c if (val == -1) val 419 drivers/net/ethernet/via/via-velocity.c else if (val < min || val > max) { val 425 drivers/net/ethernet/via/via-velocity.c devname, name, val); val 426 drivers/net/ethernet/via/via-velocity.c *opt = val; val 443 drivers/net/ethernet/via/via-velocity.c static void velocity_set_bool_opt(u32 *opt, int val, int def, u32 flag, val 447 drivers/net/ethernet/via/via-velocity.c if (val == -1) val 449 drivers/net/ethernet/via/via-velocity.c else if (val < 0 || val > 1) { val 455 drivers/net/ethernet/via/via-velocity.c devname, name, val ? "TRUE" : "FALSE"); val 456 drivers/net/ethernet/via/via-velocity.c *opt |= (val ? flag : 0); val 3476 drivers/net/ethernet/via/via-velocity.c static int get_pending_timer_val(int val) val 3478 drivers/net/ethernet/via/via-velocity.c int mult_bits = val >> 6; val 3494 drivers/net/ethernet/via/via-velocity.c return (val & 0x3f) * mult; val 3497 drivers/net/ethernet/via/via-velocity.c static void set_pending_timer_val(int *val, u32 us) val 3515 drivers/net/ethernet/via/via-velocity.c *val = (mult << 6) | ((us >> shift) & 0x3f); val 128 drivers/net/ethernet/xilinx/ll_temac_main.c int val; val 131 drivers/net/ethernet/xilinx/ll_temac_main.c val = temac_indirect_in32_locked(lp, reg); val 133 drivers/net/ethernet/xilinx/ll_temac_main.c return val; val 622 drivers/net/ethernet/xilinx/ll_temac_main.c u32 val; val 658 drivers/net/ethernet/xilinx/ll_temac_main.c val = temac_indirect_in32_locked(lp, XTE_RXC1_OFFSET); val 660 drivers/net/ethernet/xilinx/ll_temac_main.c val & ~XTE_RXC1_RXEN_MASK); val 44 drivers/net/ethernet/xilinx/ll_temac_mdio.c static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) val 50 drivers/net/ethernet/xilinx/ll_temac_mdio.c phy_id, reg, val); val 56 drivers/net/ethernet/xilinx/ll_temac_mdio.c temac_indirect_out32_locked(lp, XTE_MGTDR_OFFSET, val); val 26 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c u32 val; val 29 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c val, val & XAE_MDIO_MCR_READY_MASK, val 89 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c u16 val) val 95 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c phy_id, reg, val); val 101 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val); val 714 drivers/net/ethernet/xilinx/xilinx_emaclite.c u32 val; val 721 drivers/net/ethernet/xilinx/xilinx_emaclite.c val, !(val & XEL_MDIOCTRL_MDIOSTS_MASK), val 782 drivers/net/ethernet/xilinx/xilinx_emaclite.c u16 val) val 789 drivers/net/ethernet/xilinx/xilinx_emaclite.c phy_id, reg, val); val 803 drivers/net/ethernet/xilinx/xilinx_emaclite.c xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); val 285 drivers/net/ethernet/xscale/ixp4xx_eth.c u32 ch, hi, lo, val; val 295 drivers/net/ethernet/xscale/ixp4xx_eth.c val = __raw_readl(®s->channel[ch].ch_event); val 297 drivers/net/ethernet/xscale/ixp4xx_eth.c if (!(val & RX_SNAPSHOT_LOCKED)) val 328 drivers/net/ethernet/xscale/ixp4xx_eth.c u32 ch, cnt, hi, lo, val; val 345 drivers/net/ethernet/xscale/ixp4xx_eth.c val = __raw_readl(®s->channel[ch].ch_event); val 346 drivers/net/ethernet/xscale/ixp4xx_eth.c if (val & TX_SNAPSHOT_LOCKED) val 350 drivers/net/ethernet/xscale/ixp4xx_eth.c if (!(val & TX_SNAPSHOT_LOCKED)) { val 505 drivers/net/ethernet/xscale/ixp4xx_eth.c u16 val) val 511 drivers/net/ethernet/xscale/ixp4xx_eth.c ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); val 515 drivers/net/ethernet/xscale/ixp4xx_eth.c bus->name, phy_id, location, val, ret); val 725 drivers/net/fddi/defxx.c u8 val; val 743 drivers/net/fddi/defxx.c val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); val 744 drivers/net/fddi/defxx.c val &= PI_CONFIG_STAT_0_M_IRQ; val 745 drivers/net/fddi/defxx.c val >>= PI_CONFIG_STAT_0_V_IRQ; val 747 drivers/net/fddi/defxx.c switch (val) { val 777 drivers/net/fddi/defxx.c val = 0; val 778 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_1); val 779 drivers/net/fddi/defxx.c val = PI_DEFEA_K_CSR_IO; val 780 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_0); val 782 drivers/net/fddi/defxx.c val = PI_IO_CMP_M_SLOT; val 783 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_1); val 784 drivers/net/fddi/defxx.c val = (PI_ESIC_K_CSR_IO_LEN - 1) & ~3; val 785 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_0); val 787 drivers/net/fddi/defxx.c val = 0; val 788 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_1); val 789 drivers/net/fddi/defxx.c val = PI_DEFEA_K_BURST_HOLDOFF; val 790 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_0); val 792 drivers/net/fddi/defxx.c val = PI_IO_CMP_M_SLOT; val 793 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_1); val 794 drivers/net/fddi/defxx.c val = (PI_ESIC_K_BURST_HOLDOFF_LEN - 1) & ~3; val 795 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_0); val 798 drivers/net/fddi/defxx.c val = PI_FUNCTION_CNTRL_M_IOCS1; val 800 drivers/net/fddi/defxx.c val |= PI_FUNCTION_CNTRL_M_MEMCS1; val 802 drivers/net/fddi/defxx.c val |= PI_FUNCTION_CNTRL_M_IOCS0; val 803 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_FUNCTION_CNTRL); val 809 drivers/net/fddi/defxx.c val = PI_SLOT_CNTRL_M_ENB; val 810 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_SLOT_CNTRL); val 816 drivers/net/fddi/defxx.c val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); val 818 drivers/net/fddi/defxx.c val |= PI_BURST_HOLDOFF_M_MEM_MAP; val 820 drivers/net/fddi/defxx.c val &= ~PI_BURST_HOLDOFF_M_MEM_MAP; val 821 drivers/net/fddi/defxx.c outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF); val 824 drivers/net/fddi/defxx.c val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); val 825 drivers/net/fddi/defxx.c val |= PI_CONFIG_STAT_0_M_INT_ENB; val 826 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); val 837 drivers/net/fddi/defxx.c pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); val 838 drivers/net/fddi/defxx.c if (val < PFI_K_LAT_TIMER_MIN) { val 839 drivers/net/fddi/defxx.c val = PFI_K_LAT_TIMER_DEF; val 840 drivers/net/fddi/defxx.c pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); val 844 drivers/net/fddi/defxx.c val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB; val 845 drivers/net/fddi/defxx.c dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val); val 883 drivers/net/fddi/defxx.c u8 val; val 893 drivers/net/fddi/defxx.c val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); val 894 drivers/net/fddi/defxx.c val &= ~PI_CONFIG_STAT_0_M_INT_ENB; val 895 drivers/net/fddi/defxx.c outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); val 141 drivers/net/fddi/skfp/fplustm.c static void write_mdr(struct s_smc *smc, u_long val) val 144 drivers/net/fddi/skfp/fplustm.c MDRW(val) ; val 812 drivers/net/fddi/skfp/h/skfbi.h #define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val)) val 857 drivers/net/fddi/skfp/h/skfbi.h #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8) val 481 drivers/net/fddi/skfp/pcmplc.c int val ; val 486 drivers/net/fddi/skfp/pcmplc.c val = inpw(port) & ~(PL_PCM_CNTRL | PL_MAINT) ; val 487 drivers/net/fddi/skfp/pcmplc.c outpw(port,val) ; val 488 drivers/net/fddi/skfp/pcmplc.c outpw(port,val | state) ; val 119 drivers/net/fjes/fjes_regs.h #define wr32(reg, val) \ val 122 drivers/net/fjes/fjes_regs.h writel((val), &base[(reg)]); \ val 186 drivers/net/hamradio/baycom_par.c unsigned char val = PAR97_POWER; val 195 drivers/net/hamradio/baycom_par.c val |= PAR96_TXBIT; val 196 drivers/net/hamradio/baycom_par.c pp->ops->write_data(pp, val); val 197 drivers/net/hamradio/baycom_par.c pp->ops->write_data(pp, val | PAR96_BURST); val 221 drivers/net/hamradio/dmascc.c static void write_scc(struct scc_priv *priv, int reg, int val); val 222 drivers/net/hamradio/dmascc.c static void write_scc_data(struct scc_priv *priv, int val, int fast); val 615 drivers/net/hamradio/dmascc.c static void write_scc(struct scc_priv *priv, int reg, int val) val 622 drivers/net/hamradio/dmascc.c outb(val, priv->scc_cmd); val 627 drivers/net/hamradio/dmascc.c outb_p(val, priv->scc_cmd); val 634 drivers/net/hamradio/dmascc.c outb_p(val, priv->scc_cmd); val 642 drivers/net/hamradio/dmascc.c static void write_scc_data(struct scc_priv *priv, int val, int fast) val 647 drivers/net/hamradio/dmascc.c outb(val, priv->scc_data); val 650 drivers/net/hamradio/dmascc.c outb_p(val, priv->scc_data); val 654 drivers/net/hamradio/dmascc.c outb_p(val, priv->scc_data); val 658 drivers/net/hamradio/dmascc.c outb_p(val, priv->scc_data); val 261 drivers/net/hamradio/scc.c static inline void OutReg(io_port port, unsigned char reg, unsigned char val) val 268 drivers/net/hamradio/scc.c Outb(port, val); udelay(SCC_LDELAY); val 271 drivers/net/hamradio/scc.c Outb(port, val); val 277 drivers/net/hamradio/scc.c unsigned char val) val 279 drivers/net/hamradio/scc.c OutReg(scc->ctrl, reg, (scc->wreg[reg] = val)); val 282 drivers/net/hamradio/scc.c static inline void or(struct scc_channel *scc, unsigned char reg, unsigned char val) val 284 drivers/net/hamradio/scc.c OutReg(scc->ctrl, reg, (scc->wreg[reg] |= val)); val 287 drivers/net/hamradio/scc.c static inline void cl(struct scc_channel *scc, unsigned char reg, unsigned char val) val 289 drivers/net/hamradio/scc.c OutReg(scc->ctrl, reg, (scc->wreg[reg] &= ~val)); val 1839 drivers/net/hyperv/netvsc_drv.c static void netvsc_set_msglevel(struct net_device *ndev, u32 val) val 1843 drivers/net/hyperv/netvsc_drv.c ndev_ctx->msg_enable = val; val 388 drivers/net/ieee802154/at86rf230.c at86rf230_async_write_reg(struct at86rf230_local *lp, u8 reg, u8 val, val 395 drivers/net/ieee802154/at86rf230.c ctx->buf[1] = val; val 1214 drivers/net/ieee802154/at86rf230.c u8 val; val 1219 drivers/net/ieee802154/at86rf230.c val = 1; val 1222 drivers/net/ieee802154/at86rf230.c val = 2; val 1227 drivers/net/ieee802154/at86rf230.c val = 3; val 1230 drivers/net/ieee802154/at86rf230.c val = 0; val 1240 drivers/net/ieee802154/at86rf230.c return at86rf230_write_subreg(lp, SR_CCA_MODE, val); val 1508 drivers/net/ieee802154/at86rf230.c unsigned int part, version, val; val 1513 drivers/net/ieee802154/at86rf230.c rc = __at86rf230_read(lp, RG_MAN_ID_0, &val); val 1516 drivers/net/ieee802154/at86rf230.c man_id |= val; val 1518 drivers/net/ieee802154/at86rf230.c rc = __at86rf230_read(lp, RG_MAN_ID_1, &val); val 1521 drivers/net/ieee802154/at86rf230.c man_id |= (val << 8); val 549 drivers/net/ieee802154/atusb.c u8 val; val 554 drivers/net/ieee802154/atusb.c val = 1; val 557 drivers/net/ieee802154/atusb.c val = 2; val 562 drivers/net/ieee802154/atusb.c val = 3; val 565 drivers/net/ieee802154/atusb.c val = 0; val 575 drivers/net/ieee802154/atusb.c return atusb_write_subreg(atusb, SR_CCA_MODE, val); val 526 drivers/net/ieee802154/mrf24j40.c void *val, size_t val_size) val 530 drivers/net/ieee802154/mrf24j40.c return spi_write_then_read(spi, reg, reg_size, val, val_size); val 544 drivers/net/ieee802154/mrf24j40.c u8 val = BIT_TXNTRIG; val 548 drivers/net/ieee802154/mrf24j40.c val |= BIT_TXNSECEN; val 551 drivers/net/ieee802154/mrf24j40.c val |= BIT_TXNACKREQ; val 555 drivers/net/ieee802154/mrf24j40.c devrec->tx_post_buf[1] = val; val 635 drivers/net/ieee802154/mrf24j40.c u8 val; val 645 drivers/net/ieee802154/mrf24j40.c val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND; val 647 drivers/net/ieee802154/mrf24j40.c RFCON0_CH_MASK, val); val 716 drivers/net/ieee802154/mrf24j40.c u8 val; val 720 drivers/net/ieee802154/mrf24j40.c val = BIT_PANCOORD; val 722 drivers/net/ieee802154/mrf24j40.c val = 0; val 724 drivers/net/ieee802154/mrf24j40.c BIT_PANCOORD, val); val 838 drivers/net/ieee802154/mrf24j40.c u8 val; val 841 drivers/net/ieee802154/mrf24j40.c val = min_be << TXMCR_MIN_BE_SHIFT; val 843 drivers/net/ieee802154/mrf24j40.c val |= retries << TXMCR_CSMA_RETRIES_SHIFT; val 847 drivers/net/ieee802154/mrf24j40.c val); val 854 drivers/net/ieee802154/mrf24j40.c u8 val; val 859 drivers/net/ieee802154/mrf24j40.c val = 2; val 862 drivers/net/ieee802154/mrf24j40.c val = 1; val 867 drivers/net/ieee802154/mrf24j40.c val = 3; val 879 drivers/net/ieee802154/mrf24j40.c val << BBREG2_CCA_MODE_SHIFT); val 934 drivers/net/ieee802154/mrf24j40.c u8 val; val 937 drivers/net/ieee802154/mrf24j40.c val = TXPWRL_0 << TXPWRL_SHIFT; val 940 drivers/net/ieee802154/mrf24j40.c val = TXPWRL_10 << TXPWRL_SHIFT; val 943 drivers/net/ieee802154/mrf24j40.c val = TXPWRL_20 << TXPWRL_SHIFT; val 946 drivers/net/ieee802154/mrf24j40.c val = TXPWRL_30 << TXPWRL_SHIFT; val 954 drivers/net/ieee802154/mrf24j40.c val |= (TXPWRS_0 << TXPWRS_SHIFT); val 957 drivers/net/ieee802154/mrf24j40.c val |= (TXPWRS_0_5 << TXPWRS_SHIFT); val 960 drivers/net/ieee802154/mrf24j40.c val |= (TXPWRS_1_2 << TXPWRS_SHIFT); val 963 drivers/net/ieee802154/mrf24j40.c val |= (TXPWRS_1_9 << TXPWRS_SHIFT); val 966 drivers/net/ieee802154/mrf24j40.c val |= (TXPWRS_2_8 << TXPWRS_SHIFT); val 969 drivers/net/ieee802154/mrf24j40.c val |= (TXPWRS_3_7 << TXPWRS_SHIFT); val 972 drivers/net/ieee802154/mrf24j40.c val |= (TXPWRS_4_9 << TXPWRS_SHIFT); val 975 drivers/net/ieee802154/mrf24j40.c val |= (TXPWRS_6_3 << TXPWRS_SHIFT); val 982 drivers/net/ieee802154/mrf24j40.c TXPWRL_MASK | TXPWRS_MASK, val); val 251 drivers/net/macvlan.c u32 val = __get_unaligned_cpu32(addr + 2); val 253 drivers/net/macvlan.c val ^= macvlan_hash_mix(vlan); val 254 drivers/net/macvlan.c return hash_32(val, MACVLAN_MC_FILTER_BITS); val 609 drivers/net/mii.c u16 val = mii_data->val_in; val 615 drivers/net/mii.c if (val & (BMCR_RESET|BMCR_ANENABLE)) val 620 drivers/net/mii.c (val & BMCR_FULLDPLX)) val 629 drivers/net/mii.c mii_if->advertising = val; val 638 drivers/net/mii.c mii_data->reg_num, val); val 545 drivers/net/netdevsim/dev.c u64 val; val 547 drivers/net/netdevsim/dev.c err = devlink_resource_size_get(devlink, res_ids[i], &val); val 549 drivers/net/netdevsim/dev.c err = nsim_fib_set_max(net, res_ids[i], val, extack); val 67 drivers/net/netdevsim/fib.c int nsim_fib_set_max(struct net *net, enum nsim_resource_id res_id, u64 val, val 94 drivers/net/netdevsim/fib.c if (val < entry->num) { val 98 drivers/net/netdevsim/fib.c entry->max = val; val 124 drivers/net/netdevsim/netdev.c static int nsim_set_vf_spoofchk(struct net_device *dev, int vf, bool val) val 131 drivers/net/netdevsim/netdev.c nsim_bus_dev->vfconfigs[vf].spoofchk_enabled = val; val 136 drivers/net/netdevsim/netdev.c static int nsim_set_vf_rss_query_en(struct net_device *dev, int vf, bool val) val 143 drivers/net/netdevsim/netdev.c nsim_bus_dev->vfconfigs[vf].rss_query_enabled = val; val 148 drivers/net/netdevsim/netdev.c static int nsim_set_vf_trust(struct net_device *dev, int vf, bool val) val 155 drivers/net/netdevsim/netdev.c nsim_bus_dev->vfconfigs[vf].trusted = val; val 179 drivers/net/netdevsim/netdevsim.h int nsim_fib_set_max(struct net *net, enum nsim_resource_id res_id, u64 val, val 201 drivers/net/phy/adin.c u32 val; val 204 drivers/net/phy/adin.c if (device_property_read_u32(dev, prop_name, &val)) val 207 drivers/net/phy/adin.c rc = adin_lookup_reg_value(tbl, val); val 211 drivers/net/phy/adin.c val, prop_name, dflt); val 220 drivers/net/phy/adin.c u32 val; val 238 drivers/net/phy/adin.c val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps", val 242 drivers/net/phy/adin.c reg |= ADIN1300_GE_RGMII_RX_SEL(val); val 251 drivers/net/phy/adin.c val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps", val 255 drivers/net/phy/adin.c reg |= ADIN1300_GE_RGMII_GTX_SEL(val); val 266 drivers/net/phy/adin.c u32 val; val 280 drivers/net/phy/adin.c val = adin_get_reg_value(phydev, "adi,fifo-depth-bits", val 285 drivers/net/phy/adin.c reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val); val 293 drivers/net/phy/adin.c int val, cnt, enable; val 295 drivers/net/phy/adin.c val = phy_read(phydev, ADIN1300_PHY_CTRL2); val 296 drivers/net/phy/adin.c if (val < 0) val 297 drivers/net/phy/adin.c return val; val 303 drivers/net/phy/adin.c enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val); val 313 drivers/net/phy/adin.c u16 val; val 323 drivers/net/phy/adin.c val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt); val 324 drivers/net/phy/adin.c val |= ADIN1300_LINKING_EN; val 328 drivers/net/phy/adin.c val); val 338 drivers/net/phy/adin.c int val; val 340 drivers/net/phy/adin.c val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2); val 341 drivers/net/phy/adin.c if (val < 0) val 342 drivers/net/phy/adin.c return val; val 344 drivers/net/phy/adin.c if (ADIN1300_NRG_PD_EN & val) { val 345 drivers/net/phy/adin.c if (val & ADIN1300_NRG_PD_TX_EN) val 359 drivers/net/phy/adin.c u16 val; val 365 drivers/net/phy/adin.c val = ADIN1300_NRG_PD_EN; val 371 drivers/net/phy/adin.c val |= ADIN1300_NRG_PD_TX_EN; val 381 drivers/net/phy/adin.c val); val 498 drivers/net/phy/adin.c u16 val) val 514 drivers/net/phy/adin.c return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val); val 654 drivers/net/phy/adin.c u32 *val) val 662 drivers/net/phy/adin.c *val = (ret & 0xffff); val 671 drivers/net/phy/adin.c *val <<= 16; val 672 drivers/net/phy/adin.c *val |= (ret & 0xffff); val 681 drivers/net/phy/adin.c u32 val; val 685 drivers/net/phy/adin.c ret = adin_read_mmd_stat_regs(phydev, stat, &val); val 692 drivers/net/phy/adin.c val = (ret & 0xffff); val 695 drivers/net/phy/adin.c priv->stats[i] += val; val 84 drivers/net/phy/aquantia_hwmon.c int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); val 86 drivers/net/phy/aquantia_hwmon.c if (val < 0) val 87 drivers/net/phy/aquantia_hwmon.c return val; val 89 drivers/net/phy/aquantia_hwmon.c return !!(val & bit); val 94 drivers/net/phy/aquantia_hwmon.c int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit); val 96 drivers/net/phy/aquantia_hwmon.c if (val < 0) val 97 drivers/net/phy/aquantia_hwmon.c return val; val 99 drivers/net/phy/aquantia_hwmon.c *value = val; val 169 drivers/net/phy/aquantia_main.c int val; val 171 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); val 172 drivers/net/phy/aquantia_main.c if (val < 0) val 175 drivers/net/phy/aquantia_main.c ret = val & GENMASK(len_l - 1, 0); val 177 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); val 178 drivers/net/phy/aquantia_main.c if (val < 0) val 181 drivers/net/phy/aquantia_main.c ret += (val & GENMASK(len_h - 1, 0)) << 16; val 191 drivers/net/phy/aquantia_main.c u64 val; val 195 drivers/net/phy/aquantia_main.c val = aqr107_get_stat(phydev, i); val 196 drivers/net/phy/aquantia_main.c if (val == U64_MAX) val 200 drivers/net/phy/aquantia_main.c priv->sgmii_stats[i] += val; val 275 drivers/net/phy/aquantia_main.c int val; val 278 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); val 279 drivers/net/phy/aquantia_main.c if (val < 0) val 280 drivers/net/phy/aquantia_main.c return val; val 284 drivers/net/phy/aquantia_main.c val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); val 287 drivers/net/phy/aquantia_main.c val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); val 295 drivers/net/phy/aquantia_main.c int val; val 297 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS1); val 298 drivers/net/phy/aquantia_main.c if (val < 0) val 299 drivers/net/phy/aquantia_main.c return val; val 301 drivers/net/phy/aquantia_main.c return !!(val & MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT); val 306 drivers/net/phy/aquantia_main.c int val; val 308 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); val 309 drivers/net/phy/aquantia_main.c if (val < 0) val 310 drivers/net/phy/aquantia_main.c return val; val 312 drivers/net/phy/aquantia_main.c switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { val 336 drivers/net/phy/aquantia_main.c if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) val 346 drivers/net/phy/aquantia_main.c int val, ret; val 355 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); val 356 drivers/net/phy/aquantia_main.c if (val < 0) val 357 drivers/net/phy/aquantia_main.c return val; val 359 drivers/net/phy/aquantia_main.c switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { val 378 drivers/net/phy/aquantia_main.c val = aqr107_read_downshift_event(phydev); val 379 drivers/net/phy/aquantia_main.c if (val <= 0) val 380 drivers/net/phy/aquantia_main.c return val; val 390 drivers/net/phy/aquantia_main.c int val, cnt, enable; val 392 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); val 393 drivers/net/phy/aquantia_main.c if (val < 0) val 394 drivers/net/phy/aquantia_main.c return val; val 396 drivers/net/phy/aquantia_main.c enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); val 397 drivers/net/phy/aquantia_main.c cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); val 406 drivers/net/phy/aquantia_main.c int val = 0; val 412 drivers/net/phy/aquantia_main.c val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; val 413 drivers/net/phy/aquantia_main.c val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); val 418 drivers/net/phy/aquantia_main.c MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); val 452 drivers/net/phy/aquantia_main.c int val, retries = 100; val 455 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); val 456 drivers/net/phy/aquantia_main.c if (val < 0) val 457 drivers/net/phy/aquantia_main.c return val; val 459 drivers/net/phy/aquantia_main.c } while (!val && --retries); val 461 drivers/net/phy/aquantia_main.c return val ? 0 : -ETIMEDOUT; val 467 drivers/net/phy/aquantia_main.c int val; val 469 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); val 470 drivers/net/phy/aquantia_main.c if (val < 0) val 473 drivers/net/phy/aquantia_main.c fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); val 474 drivers/net/phy/aquantia_main.c fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); val 476 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); val 477 drivers/net/phy/aquantia_main.c if (val < 0) val 480 drivers/net/phy/aquantia_main.c build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); val 481 drivers/net/phy/aquantia_main.c prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); val 543 drivers/net/phy/aquantia_main.c int mode, val; val 548 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); val 550 drivers/net/phy/aquantia_main.c if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) val 553 drivers/net/phy/aquantia_main.c short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; val 554 drivers/net/phy/aquantia_main.c downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; val 556 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); val 557 drivers/net/phy/aquantia_main.c if (val < 0) val 560 drivers/net/phy/aquantia_main.c fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); val 561 drivers/net/phy/aquantia_main.c fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); val 563 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); val 564 drivers/net/phy/aquantia_main.c if (val < 0) val 567 drivers/net/phy/aquantia_main.c afr = val & MDIO_AN_RX_VEND_STAT3_AFR; val 575 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); val 576 drivers/net/phy/aquantia_main.c if (val < 0) val 579 drivers/net/phy/aquantia_main.c mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); val 101 drivers/net/phy/at803x.c u16 val; val 108 drivers/net/phy/at803x.c val = ret & 0xffff; val 109 drivers/net/phy/at803x.c val &= ~clear; val 110 drivers/net/phy/at803x.c val |= set; val 112 drivers/net/phy/at803x.c return phy_write(phydev, AT803X_DEBUG_DATA, val); val 17 drivers/net/phy/bcm-phy-lib.c int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val) val 25 drivers/net/phy/bcm-phy-lib.c return phy_write(phydev, MII_BCM54XX_EXP_DATA, val); val 31 drivers/net/phy/bcm-phy-lib.c int val; val 33 drivers/net/phy/bcm-phy-lib.c val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); val 34 drivers/net/phy/bcm-phy-lib.c if (val < 0) val 35 drivers/net/phy/bcm-phy-lib.c return val; val 37 drivers/net/phy/bcm-phy-lib.c val = phy_read(phydev, MII_BCM54XX_EXP_DATA); val 42 drivers/net/phy/bcm-phy-lib.c return val; val 57 drivers/net/phy/bcm-phy-lib.c int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val) val 59 drivers/net/phy/bcm-phy-lib.c return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); val 64 drivers/net/phy/bcm-phy-lib.c u16 reg, u16 chl, u16 val) val 81 drivers/net/phy/bcm-phy-lib.c rc = bcm_phy_write_exp(phydev, tmp, val); val 149 drivers/net/phy/bcm-phy-lib.c u16 val) val 154 drivers/net/phy/bcm-phy-lib.c MII_BCM54XX_SHD_DATA(val)); val 160 drivers/net/phy/bcm-phy-lib.c int val; val 163 drivers/net/phy/bcm-phy-lib.c val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); val 164 drivers/net/phy/bcm-phy-lib.c if (val < 0) val 165 drivers/net/phy/bcm-phy-lib.c return val; val 167 drivers/net/phy/bcm-phy-lib.c val |= BCM54XX_SHD_SCR3_DLLAPD_DIS; val 168 drivers/net/phy/bcm-phy-lib.c bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); val 171 drivers/net/phy/bcm-phy-lib.c val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); val 172 drivers/net/phy/bcm-phy-lib.c if (val < 0) val 173 drivers/net/phy/bcm-phy-lib.c return val; val 176 drivers/net/phy/bcm-phy-lib.c val &= BCM_APD_CLR_MASK; val 179 drivers/net/phy/bcm-phy-lib.c val |= BCM54XX_SHD_APD_EN; val 181 drivers/net/phy/bcm-phy-lib.c val |= BCM_NO_ANEG_APD_EN; val 184 drivers/net/phy/bcm-phy-lib.c val |= BCM_APD_SINGLELP_EN; val 187 drivers/net/phy/bcm-phy-lib.c return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); val 193 drivers/net/phy/bcm-phy-lib.c int val; val 196 drivers/net/phy/bcm-phy-lib.c val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL); val 197 drivers/net/phy/bcm-phy-lib.c if (val < 0) val 198 drivers/net/phy/bcm-phy-lib.c return val; val 201 drivers/net/phy/bcm-phy-lib.c val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X; val 203 drivers/net/phy/bcm-phy-lib.c val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X); val 205 drivers/net/phy/bcm-phy-lib.c phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); val 208 drivers/net/phy/bcm-phy-lib.c val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV); val 209 drivers/net/phy/bcm-phy-lib.c if (val < 0) val 210 drivers/net/phy/bcm-phy-lib.c return val; val 213 drivers/net/phy/bcm-phy-lib.c val |= (MDIO_EEE_100TX | MDIO_EEE_1000T); val 215 drivers/net/phy/bcm-phy-lib.c val &= ~(MDIO_EEE_100TX | MDIO_EEE_1000T); val 217 drivers/net/phy/bcm-phy-lib.c phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); val 225 drivers/net/phy/bcm-phy-lib.c int val; val 227 drivers/net/phy/bcm-phy-lib.c val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); val 228 drivers/net/phy/bcm-phy-lib.c if (val < 0) val 229 drivers/net/phy/bcm-phy-lib.c return val; val 232 drivers/net/phy/bcm-phy-lib.c if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) { val 237 drivers/net/phy/bcm-phy-lib.c val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2); val 238 drivers/net/phy/bcm-phy-lib.c if (val < 0) val 239 drivers/net/phy/bcm-phy-lib.c return val; val 242 drivers/net/phy/bcm-phy-lib.c if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) { val 246 drivers/net/phy/bcm-phy-lib.c val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT; val 247 drivers/net/phy/bcm-phy-lib.c val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK; val 248 drivers/net/phy/bcm-phy-lib.c *count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET; val 257 drivers/net/phy/bcm-phy-lib.c int val = 0, ret = 0; val 266 drivers/net/phy/bcm-phy-lib.c val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); val 267 drivers/net/phy/bcm-phy-lib.c if (val < 0) val 268 drivers/net/phy/bcm-phy-lib.c return val; val 271 drivers/net/phy/bcm-phy-lib.c val |= MII_BCM54XX_AUXCTL_MISC_WREN; val 274 drivers/net/phy/bcm-phy-lib.c val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN; val 277 drivers/net/phy/bcm-phy-lib.c val); val 279 drivers/net/phy/bcm-phy-lib.c val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN; val 282 drivers/net/phy/bcm-phy-lib.c val); val 287 drivers/net/phy/bcm-phy-lib.c val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2); val 288 drivers/net/phy/bcm-phy-lib.c val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK << val 294 drivers/net/phy/bcm-phy-lib.c val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS; val 297 drivers/net/phy/bcm-phy-lib.c val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT; val 300 drivers/net/phy/bcm-phy-lib.c val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) << val 305 drivers/net/phy/bcm-phy-lib.c return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val); val 348 drivers/net/phy/bcm-phy-lib.c int val; val 351 drivers/net/phy/bcm-phy-lib.c val = phy_read(phydev, stat.reg); val 352 drivers/net/phy/bcm-phy-lib.c if (val < 0) { val 355 drivers/net/phy/bcm-phy-lib.c val >>= stat.shift; val 356 drivers/net/phy/bcm-phy-lib.c val = val & ((1 << stat.bits) - 1); val 357 drivers/net/phy/bcm-phy-lib.c shadow[i] += val; val 30 drivers/net/phy/bcm-phy-lib.h int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val); val 34 drivers/net/phy/bcm-phy-lib.h u16 reg, u16 val) val 36 drivers/net/phy/bcm-phy-lib.h return bcm_phy_write_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER, val); val 39 drivers/net/phy/bcm-phy-lib.h int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val); val 48 drivers/net/phy/bcm-phy-lib.h u16 val); val 57 drivers/net/phy/bcm87xx.c int val; val 59 drivers/net/phy/bcm87xx.c val = 0; val 61 drivers/net/phy/bcm87xx.c val = phy_read(phydev, regnum); val 62 drivers/net/phy/bcm87xx.c if (val < 0) { val 63 drivers/net/phy/bcm87xx.c ret = val; val 66 drivers/net/phy/bcm87xx.c val &= mask; val 68 drivers/net/phy/bcm87xx.c val |= val_bits; val 70 drivers/net/phy/bcm87xx.c ret = phy_write(phydev, regnum, val); val 33 drivers/net/phy/broadcom.c int val; val 38 drivers/net/phy/broadcom.c val = phy_read(phydev, MII_CTRL1000); val 39 drivers/net/phy/broadcom.c val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; val 40 drivers/net/phy/broadcom.c phy_write(phydev, MII_CTRL1000, val); val 88 drivers/net/phy/broadcom.c int rc, val; val 91 drivers/net/phy/broadcom.c val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); val 92 drivers/net/phy/broadcom.c val |= MII_BCM54XX_AUXCTL_MISC_WREN; val 96 drivers/net/phy/broadcom.c val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; val 101 drivers/net/phy/broadcom.c val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; val 104 drivers/net/phy/broadcom.c val); val 109 drivers/net/phy/broadcom.c val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); val 113 drivers/net/phy/broadcom.c val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; val 118 drivers/net/phy/broadcom.c val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN; val 120 drivers/net/phy/broadcom.c rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); val 187 drivers/net/phy/broadcom.c int val; val 189 drivers/net/phy/broadcom.c val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75); val 190 drivers/net/phy/broadcom.c if (val < 0) val 193 drivers/net/phy/broadcom.c val |= MII_BCM54XX_EXP_EXP75_CM_OSC; val 194 drivers/net/phy/broadcom.c err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val); val 210 drivers/net/phy/broadcom.c int val; val 219 drivers/net/phy/broadcom.c val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); val 220 drivers/net/phy/broadcom.c if (val < 0) val 223 drivers/net/phy/broadcom.c orig = val; val 236 drivers/net/phy/broadcom.c val &= ~BCM54XX_SHD_SCR3_DEF_CLK125; val 242 drivers/net/phy/broadcom.c val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS; val 244 drivers/net/phy/broadcom.c val |= BCM54XX_SHD_SCR3_DLLAPD_DIS; val 247 drivers/net/phy/broadcom.c val |= BCM54XX_SHD_SCR3_TRDDAPD; val 249 drivers/net/phy/broadcom.c if (orig != val) val 250 drivers/net/phy/broadcom.c bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); val 252 drivers/net/phy/broadcom.c val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); val 253 drivers/net/phy/broadcom.c if (val < 0) val 256 drivers/net/phy/broadcom.c orig = val; val 259 drivers/net/phy/broadcom.c val |= BCM54XX_SHD_APD_EN; val 261 drivers/net/phy/broadcom.c val &= ~BCM54XX_SHD_APD_EN; val 263 drivers/net/phy/broadcom.c if (orig != val) val 264 drivers/net/phy/broadcom.c bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); val 269 drivers/net/phy/broadcom.c int reg, err, val; val 309 drivers/net/phy/broadcom.c val = bcm_phy_read_exp(phydev, val 311 drivers/net/phy/broadcom.c val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; val 314 drivers/net/phy/broadcom.c val); val 325 drivers/net/phy/broadcom.c val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) | val 327 drivers/net/phy/broadcom.c bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val); val 329 drivers/net/phy/broadcom.c val = BCM_LED_MULTICOLOR_IN_PHASE | val 332 drivers/net/phy/broadcom.c bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val); val 464 drivers/net/phy/broadcom.c int val; val 466 drivers/net/phy/broadcom.c val = phy_read(phydev, reg); val 467 drivers/net/phy/broadcom.c if (val < 0) val 468 drivers/net/phy/broadcom.c return val; val 470 drivers/net/phy/broadcom.c return phy_write(phydev, reg, val | set); val 211 drivers/net/phy/dp83640.c u16 val) val 213 drivers/net/phy/dp83640.c return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); val 220 drivers/net/phy/dp83640.c int val; val 226 drivers/net/phy/dp83640.c val = phy_read(phydev, regnum); val 228 drivers/net/phy/dp83640.c return val; val 233 drivers/net/phy/dp83640.c int page, u32 regnum, u16 val) val 242 drivers/net/phy/dp83640.c broadcast_write(phydev, regnum, val); val 244 drivers/net/phy/dp83640.c phy_write(phydev, regnum, val); val 301 drivers/net/phy/dp83640.c u16 gpio, ptp_trig, val; val 318 drivers/net/phy/dp83640.c val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; val 321 drivers/net/phy/dp83640.c val |= TRIG_DIS; val 324 drivers/net/phy/dp83640.c ext_write(0, phydev, PAGE4, PTP_CTL, val); val 340 drivers/net/phy/dp83640.c val |= TRIG_LOAD; val 341 drivers/net/phy/dp83640.c ext_write(0, phydev, PAGE4, PTP_CTL, val); val 355 drivers/net/phy/dp83640.c val &= ~TRIG_LOAD; val 356 drivers/net/phy/dp83640.c val |= TRIG_EN; val 357 drivers/net/phy/dp83640.c ext_write(0, phydev, PAGE4, PTP_CTL, val); val 425 drivers/net/phy/dp83640.c unsigned int val[4]; val 431 drivers/net/phy/dp83640.c val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ val 432 drivers/net/phy/dp83640.c val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ val 433 drivers/net/phy/dp83640.c val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ val 434 drivers/net/phy/dp83640.c val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ val 438 drivers/net/phy/dp83640.c ts->tv_nsec = val[0] | (val[1] << 16); val 439 drivers/net/phy/dp83640.c ts->tv_sec = val[2] | (val[3] << 16); val 608 drivers/net/phy/dp83640.c int val; val 610 drivers/net/phy/dp83640.c val = phy_read(phydev, PHYCR2); val 612 drivers/net/phy/dp83640.c val |= BC_WRITE; val 614 drivers/net/phy/dp83640.c val &= ~BC_WRITE; val 615 drivers/net/phy/dp83640.c phy_write(phydev, PHYCR2, val); val 627 drivers/net/phy/dp83640.c u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; val 675 drivers/net/phy/dp83640.c val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; val 676 drivers/net/phy/dp83640.c val |= TRIG_LOAD; val 677 drivers/net/phy/dp83640.c ext_write(0, master, PAGE4, PTP_CTL, val); val 680 drivers/net/phy/dp83640.c val &= ~TRIG_LOAD; val 681 drivers/net/phy/dp83640.c val |= TRIG_EN; val 682 drivers/net/phy/dp83640.c ext_write(0, master, PAGE4, PTP_CTL, val); val 685 drivers/net/phy/dp83640.c val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; val 686 drivers/net/phy/dp83640.c val |= TRIG_DIS; val 687 drivers/net/phy/dp83640.c ext_write(0, master, PAGE4, PTP_CTL, val); val 692 drivers/net/phy/dp83640.c val = ext_read(master, PAGE4, PTP_STS); val 693 drivers/net/phy/dp83640.c phydev_info(master, "master PTP_STS 0x%04hx\n", val); val 694 drivers/net/phy/dp83640.c val = ext_read(master, PAGE4, PTP_ESTS); val 695 drivers/net/phy/dp83640.c phydev_info(master, "master PTP_ESTS 0x%04hx\n", val); val 704 drivers/net/phy/dp83640.c val = ext_read(tmp->phydev, PAGE4, PTP_STS); val 705 drivers/net/phy/dp83640.c phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val); val 706 drivers/net/phy/dp83640.c val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); val 707 drivers/net/phy/dp83640.c phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val); val 71 drivers/net/phy/dp83848.c int val; val 76 drivers/net/phy/dp83848.c val = phy_read(phydev, MII_BMCR); val 77 drivers/net/phy/dp83848.c if (!(val & BMCR_ANENABLE)) val 222 drivers/net/phy/dp83867.c const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); val 223 drivers/net/phy/dp83867.c const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> val 225 drivers/net/phy/dp83867.c const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> val 314 drivers/net/phy/dp83867.c int ret, val, bs; val 341 drivers/net/phy/dp83867.c val = phy_read(phydev, MII_DP83867_PHYCTRL); val 342 drivers/net/phy/dp83867.c if (val < 0) val 343 drivers/net/phy/dp83867.c return val; val 344 drivers/net/phy/dp83867.c val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; val 345 drivers/net/phy/dp83867.c val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); val 359 drivers/net/phy/dp83867.c val &= ~DP83867_PHYCR_RESERVED_MASK; val 361 drivers/net/phy/dp83867.c ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); val 372 drivers/net/phy/dp83867.c val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); val 374 drivers/net/phy/dp83867.c val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); val 376 drivers/net/phy/dp83867.c val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); val 379 drivers/net/phy/dp83867.c val |= DP83867_RGMII_TX_CLK_DELAY_EN; val 382 drivers/net/phy/dp83867.c val |= DP83867_RGMII_RX_CLK_DELAY_EN; val 384 drivers/net/phy/dp83867.c phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); val 425 drivers/net/phy/dp83867.c val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); val 431 drivers/net/phy/dp83867.c val |= DP83867_SGMII_TYPE; val 433 drivers/net/phy/dp83867.c val &= ~DP83867_SGMII_TYPE; val 434 drivers/net/phy/dp83867.c phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); val 437 drivers/net/phy/dp83867.c val = phy_read(phydev, DP83867_CFG3); val 440 drivers/net/phy/dp83867.c val |= DP83867_CFG3_INT_OE; val 442 drivers/net/phy/dp83867.c val |= DP83867_CFG3_ROBUST_AUTO_MDIX; val 443 drivers/net/phy/dp83867.c phy_write(phydev, DP83867_CFG3, val); val 453 drivers/net/phy/dp83867.c val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; val 456 drivers/net/phy/dp83867.c val = dp83867->clk_output_sel << val 461 drivers/net/phy/dp83867.c mask, val); val 64 drivers/net/phy/et1011c.c u32 val; val 70 drivers/net/phy/et1011c.c val = phy_read(phydev, ET1011C_STATUS_REG); val 71 drivers/net/phy/et1011c.c if ((val & ET1011C_SPEED_MASK) == val 73 drivers/net/phy/et1011c.c val = phy_read(phydev, ET1011C_CONFIG_REG); val 74 drivers/net/phy/et1011c.c val &= ~ET1011C_TX_FIFO_MASK; val 75 drivers/net/phy/et1011c.c phy_write(phydev, ET1011C_CONFIG_REG, val\ val 105 drivers/net/phy/fixed_phy.c u16 val) val 277 drivers/net/phy/icplus.c u16 val; val 281 drivers/net/phy/icplus.c val = IP101A_G_IRQ_PIN_USED; val 283 drivers/net/phy/icplus.c val = IP101A_G_IRQ_ALL_MASK; val 285 drivers/net/phy/icplus.c return phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, val); val 290 drivers/net/phy/icplus.c int val = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); val 292 drivers/net/phy/icplus.c if (val < 0) val 295 drivers/net/phy/icplus.c return val & (IP101A_G_IRQ_SPEED_CHANGE | val 224 drivers/net/phy/lxt.c int val = phy_read(phydev, MII_LXT973_PCR); val 226 drivers/net/phy/lxt.c if (val & PCR_FIBER_SELECT) { val 231 drivers/net/phy/lxt.c val = phy_read(phydev, MII_BMCR); val 232 drivers/net/phy/lxt.c val |= (BMCR_SPEED100 | BMCR_FULLDPLX); val 233 drivers/net/phy/lxt.c val &= ~BMCR_ANENABLE; val 234 drivers/net/phy/lxt.c phy_write(phydev, MII_BMCR, val); val 243 drivers/net/phy/marvell.c int val; val 250 drivers/net/phy/marvell.c val = reg; val 251 drivers/net/phy/marvell.c val &= ~MII_M1011_PHY_SCR_AUTO_CROSS; val 254 drivers/net/phy/marvell.c val |= MII_M1011_PHY_SCR_MDI; val 257 drivers/net/phy/marvell.c val |= MII_M1011_PHY_SCR_MDI_X; val 262 drivers/net/phy/marvell.c val |= MII_M1011_PHY_SCR_AUTO_CROSS; val 266 drivers/net/phy/marvell.c if (val != reg) { val 268 drivers/net/phy/marvell.c err = phy_write(phydev, MII_M1011_PHY_SCR, val); val 273 drivers/net/phy/marvell.c return val != reg; val 399 drivers/net/phy/marvell.c int val; val 408 drivers/net/phy/marvell.c val = 0; val 410 drivers/net/phy/marvell.c val = __phy_read(phydev, reg); val 411 drivers/net/phy/marvell.c if (val < 0) { val 412 drivers/net/phy/marvell.c ret = val; val 415 drivers/net/phy/marvell.c val &= mask; val 417 drivers/net/phy/marvell.c val |= val_bits; val 419 drivers/net/phy/marvell.c ret = __phy_write(phydev, reg, val); val 1043 drivers/net/phy/marvell.c int val; val 1045 drivers/net/phy/marvell.c val = phy_read(phydev, MII_88E1540_COPPER_CTRL3); val 1046 drivers/net/phy/marvell.c if (val < 0) val 1047 drivers/net/phy/marvell.c return val; val 1049 drivers/net/phy/marvell.c if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) { val 1054 drivers/net/phy/marvell.c val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val); val 1056 drivers/net/phy/marvell.c switch (val) { val 1079 drivers/net/phy/marvell.c int val, ret; val 1095 drivers/net/phy/marvell.c val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS; val 1097 drivers/net/phy/marvell.c val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS; val 1099 drivers/net/phy/marvell.c val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS; val 1101 drivers/net/phy/marvell.c val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS; val 1103 drivers/net/phy/marvell.c val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val); val 1106 drivers/net/phy/marvell.c MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val); val 1613 drivers/net/phy/marvell.c int val; val 1616 drivers/net/phy/marvell.c val = phy_read_paged(phydev, stat.page, stat.reg); val 1617 drivers/net/phy/marvell.c if (val < 0) { val 1620 drivers/net/phy/marvell.c val = val & ((1 << stat.bits) - 1); val 1621 drivers/net/phy/marvell.c priv->stats[i] += val; val 1643 drivers/net/phy/marvell.c int val; val 1664 drivers/net/phy/marvell.c val = __phy_read(phydev, MII_88E1121_MISC_TEST); val 1665 drivers/net/phy/marvell.c if (val < 0) { val 1666 drivers/net/phy/marvell.c ret = val; val 1676 drivers/net/phy/marvell.c *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000; val 143 drivers/net/phy/marvell10g.c u16 val; val 151 drivers/net/phy/marvell10g.c val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; val 154 drivers/net/phy/marvell10g.c MV_V2_TEMP_CTRL_MASK, val); val 292 drivers/net/phy/marvell10g.c int ret, val; val 299 drivers/net/phy/marvell10g.c val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, val 301 drivers/net/phy/marvell10g.c if (val < 0) val 302 drivers/net/phy/marvell10g.c return val; val 306 drivers/net/phy/marvell10g.c val & MDIO_PMA_NG_EXTABLE_2_5GBT); val 310 drivers/net/phy/marvell10g.c val & MDIO_PMA_NG_EXTABLE_5GBT); val 350 drivers/net/phy/marvell10g.c int val; val 352 drivers/net/phy/marvell10g.c val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); val 353 drivers/net/phy/marvell10g.c if (val < 0) val 354 drivers/net/phy/marvell10g.c return val; val 356 drivers/net/phy/marvell10g.c if (val & MDIO_STAT1_LSTATUS) val 405 drivers/net/phy/marvell10g.c int val; val 415 drivers/net/phy/marvell10g.c val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); val 416 drivers/net/phy/marvell10g.c if (val < 0) val 417 drivers/net/phy/marvell10g.c return val; val 419 drivers/net/phy/marvell10g.c if (val & MDIO_STAT1_LSTATUS) val 422 drivers/net/phy/marvell10g.c val = genphy_c45_read_link(phydev); val 423 drivers/net/phy/marvell10g.c if (val < 0) val 424 drivers/net/phy/marvell10g.c return val; val 426 drivers/net/phy/marvell10g.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); val 427 drivers/net/phy/marvell10g.c if (val < 0) val 428 drivers/net/phy/marvell10g.c return val; val 430 drivers/net/phy/marvell10g.c if (val & MDIO_AN_STAT1_COMPLETE) { val 431 drivers/net/phy/marvell10g.c val = genphy_c45_read_lpa(phydev); val 432 drivers/net/phy/marvell10g.c if (val < 0) val 433 drivers/net/phy/marvell10g.c return val; val 436 drivers/net/phy/marvell10g.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); val 437 drivers/net/phy/marvell10g.c if (val < 0) val 438 drivers/net/phy/marvell10g.c return val; val 440 drivers/net/phy/marvell10g.c mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); val 447 drivers/net/phy/marvell10g.c val = genphy_c45_read_pma(phydev); val 448 drivers/net/phy/marvell10g.c if (val < 0) val 449 drivers/net/phy/marvell10g.c return val; val 453 drivers/net/phy/marvell10g.c val = genphy_c45_read_mdix(phydev); val 454 drivers/net/phy/marvell10g.c if (val < 0) val 455 drivers/net/phy/marvell10g.c return val; val 457 drivers/net/phy/marvell10g.c val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP); val 458 drivers/net/phy/marvell10g.c if (val < 0) val 459 drivers/net/phy/marvell10g.c return val; val 461 drivers/net/phy/marvell10g.c switch (val & MV_PCS_PAIRSWAP_MASK) { val 74 drivers/net/phy/mdio-aspeed.c static int aspeed_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) val 80 drivers/net/phy/mdio-aspeed.c __func__, addr, regnum, val); val 91 drivers/net/phy/mdio-aspeed.c | FIELD_PREP(ASPEED_MDIO_CTRL_MIIWDATA, val); val 43 drivers/net/phy/mdio-bcm-iproc.c u32 val; val 47 drivers/net/phy/mdio-bcm-iproc.c val = readl(base + MII_CTRL_OFFSET); val 48 drivers/net/phy/mdio-bcm-iproc.c if ((val & BIT(MII_CTRL_BUSY_SHIFT)) == 0) val 59 drivers/net/phy/mdio-bcm-iproc.c u32 val; val 61 drivers/net/phy/mdio-bcm-iproc.c val = (IPROC_GPHY_MDCDIV << MII_CTRL_DIV_SHIFT) | val 63 drivers/net/phy/mdio-bcm-iproc.c writel(val, base + MII_CTRL_OFFSET); val 95 drivers/net/phy/mdio-bcm-iproc.c int reg, u16 val) val 111 drivers/net/phy/mdio-bcm-iproc.c ((u32)(val) & MII_DATA_MASK); val 60 drivers/net/phy/mdio-bcm-unimac.c static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val, val 64 drivers/net/phy/mdio-bcm-unimac.c __raw_writel(val, priv->base + offset); val 66 drivers/net/phy/mdio-bcm-unimac.c writel_relaxed(val, priv->base + offset); val 129 drivers/net/phy/mdio-bcm-unimac.c int reg, u16 val) val 136 drivers/net/phy/mdio-bcm-unimac.c (reg << MDIO_REG_SHIFT) | (0xffff & val); val 44 drivers/net/phy/mdio-bitbang.c static void mdiobb_send_bit(struct mdiobb_ctrl *ctrl, int val) val 48 drivers/net/phy/mdio-bitbang.c ops->set_mdio_data(ctrl, val); val 69 drivers/net/phy/mdio-bitbang.c static void mdiobb_send_num(struct mdiobb_ctrl *ctrl, u16 val, int bits) val 74 drivers/net/phy/mdio-bitbang.c mdiobb_send_bit(ctrl, (val >> i) & 1); val 184 drivers/net/phy/mdio-bitbang.c static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) val 198 drivers/net/phy/mdio-bitbang.c mdiobb_send_num(ctrl, val, 16); val 96 drivers/net/phy/mdio-cavium.c if (smi_rd.s.val) val 103 drivers/net/phy/mdio-cavium.c int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val) val 124 drivers/net/phy/mdio-cavium.c smi_wr.s.dat = val; val 74 drivers/net/phy/mdio-cavium.h OCT_MDIO_BITFIELD_FIELD(u64 val:1, val 85 drivers/net/phy/mdio-cavium.h OCT_MDIO_BITFIELD_FIELD(u64 val:1, val 101 drivers/net/phy/mdio-cavium.h static inline void oct_mdio_writeq(u64 val, u64 addr) val 103 drivers/net/phy/mdio-cavium.h cvmx_write_csr(addr, val); val 113 drivers/net/phy/mdio-cavium.h #define oct_mdio_writeq(val, addr) writeq(val, (void *)addr) val 118 drivers/net/phy/mdio-cavium.h int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val); val 30 drivers/net/phy/mdio-hisi-femac.c u32 val; val 33 drivers/net/phy/mdio-hisi-femac.c val, val & MDIO_RW_FINISH, 20, 10000); val 59 drivers/net/phy/mdio-i2c.c static int i2c_mii_write(struct mii_bus *bus, int phy_id, int reg, u16 val) val 70 drivers/net/phy/mdio-i2c.c data[1] = val >> 8; val 71 drivers/net/phy/mdio-i2c.c data[2] = val; val 44 drivers/net/phy/mdio-mscc-miim.c u32 val; val 46 drivers/net/phy/mdio-mscc-miim.c readl_poll_timeout(miim->regs + MSCC_MIIM_REG_STATUS, val, val 47 drivers/net/phy/mdio-mscc-miim.c !(val & MSCC_MIIM_STATUS_STAT_BUSY), 100, 250000); val 48 drivers/net/phy/mdio-mscc-miim.c if (val & MSCC_MIIM_STATUS_STAT_BUSY) val 57 drivers/net/phy/mdio-mscc-miim.c u32 val; val 72 drivers/net/phy/mdio-mscc-miim.c val = readl(miim->regs + MSCC_MIIM_REG_DATA); val 73 drivers/net/phy/mdio-mscc-miim.c if (val & MSCC_MIIM_DATA_ERROR) { val 78 drivers/net/phy/mdio-mscc-miim.c ret = val & 0xFFFF; val 59 drivers/net/phy/mdio-mux-bcm-iproc.c u32 val; val 62 drivers/net/phy/mdio-mux-bcm-iproc.c val = readl(md->base + MDIO_SCAN_CTRL_OFFSET); val 63 drivers/net/phy/mdio-mux-bcm-iproc.c val |= BIT(MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR); val 64 drivers/net/phy/mdio-mux-bcm-iproc.c writel(val, md->base + MDIO_SCAN_CTRL_OFFSET); val 72 drivers/net/phy/mdio-mux-bcm-iproc.c val = divisor; val 73 drivers/net/phy/mdio-mux-bcm-iproc.c val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT; val 74 drivers/net/phy/mdio-mux-bcm-iproc.c writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET); val 75 drivers/net/phy/mdio-mux-bcm-iproc.c writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET); val 82 drivers/net/phy/mdio-mux-bcm-iproc.c u32 val; val 85 drivers/net/phy/mdio-mux-bcm-iproc.c val = readl(base + MDIO_STAT_OFFSET); val 86 drivers/net/phy/mdio-mux-bcm-iproc.c if ((val & MDIO_STAT_DONE) == result) val 108 drivers/net/phy/mdio-mux-bcm-iproc.c u16 phyid, u32 reg, u16 val, u32 op) val 120 drivers/net/phy/mdio-mux-bcm-iproc.c param |= val << MDIO_PARAM_PHY_DATA; val 153 drivers/net/phy/mdio-mux-bcm-iproc.c int phyid, int reg, u16 val) val 159 drivers/net/phy/mdio-mux-bcm-iproc.c ret = start_miim_ops(md->base, phyid, reg, val, MDIO_CTRL_WRITE_OP); val 74 drivers/net/phy/mdio-mux-meson-g12a.c u32 val, m, n; val 76 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); val 77 drivers/net/phy/mdio-mux-meson-g12a.c m = FIELD_GET(PLL_CTL0_M, val); val 78 drivers/net/phy/mdio-mux-meson-g12a.c n = FIELD_GET(PLL_CTL0_N, val); val 86 drivers/net/phy/mdio-mux-meson-g12a.c u32 val = readl(pll->base + ETH_PLL_CTL0); val 89 drivers/net/phy/mdio-mux-meson-g12a.c val |= PLL_CTL0_RST | PLL_CTL0_EN; val 90 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); val 93 drivers/net/phy/mdio-mux-meson-g12a.c val &= ~PLL_CTL0_RST; val 94 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); val 101 drivers/net/phy/mdio-mux-meson-g12a.c return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, val 102 drivers/net/phy/mdio-mux-meson-g12a.c val & PLL_CTL0_LOCK_DIG, 0, PLL_LOCK_TIMEOUT); val 108 drivers/net/phy/mdio-mux-meson-g12a.c u32 val; val 110 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); val 111 drivers/net/phy/mdio-mux-meson-g12a.c val &= ~PLL_CTL0_EN; val 112 drivers/net/phy/mdio-mux-meson-g12a.c val |= PLL_CTL0_RST; val 113 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); val 119 drivers/net/phy/mdio-mux-meson-g12a.c unsigned int val; val 121 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); val 123 drivers/net/phy/mdio-mux-meson-g12a.c return (val & PLL_CTL0_LOCK_DIG) ? 1 : 0; val 62 drivers/net/phy/mdio-mux.c int regnum, u16 val) val 76 drivers/net/phy/mdio-mux.c r = pb->mii_bus->write(pb->mii_bus, phy_id, regnum, val); val 109 drivers/net/phy/mdio-xgene.c u32 val, done; val 112 drivers/net/phy/mdio-xgene.c val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); val 113 drivers/net/phy/mdio-xgene.c xgene_mdio_wr_mac(pdata, MII_MGMT_ADDRESS_ADDR, val); val 136 drivers/net/phy/mdio-xgene.c u32 offset, u32 val) val 138 drivers/net/phy/mdio-xgene.c iowrite32(val, pdata->diag_csr_addr + offset); val 196 drivers/net/phy/mdio-xgene.c u32 offset, u32 *val) val 200 drivers/net/phy/mdio-xgene.c *val = ioread32(addr); val 204 drivers/net/phy/mdio-xgene.c u32 offset, u32 val) val 208 drivers/net/phy/mdio-xgene.c iowrite32(val, addr); val 216 drivers/net/phy/mdio-xgene.c u32 status, val; val 218 drivers/net/phy/mdio-xgene.c val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg) | val 220 drivers/net/phy/mdio-xgene.c xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val); val 222 drivers/net/phy/mdio-xgene.c val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_WRITE); val 223 drivers/net/phy/mdio-xgene.c xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val); val 238 drivers/net/phy/mdio-xgene.c u32 data, status, val; val 241 drivers/net/phy/mdio-xgene.c val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg); val 242 drivers/net/phy/mdio-xgene.c xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val); val 244 drivers/net/phy/mdio-xgene.c val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_READ); val 245 drivers/net/phy/mdio-xgene.c xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val); val 99 drivers/net/phy/mdio-xgene.h static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val) val 101 drivers/net/phy/mdio-xgene.h return (val & ((1ULL << len) - 1)) << pos; val 104 drivers/net/phy/mdio-xgene.h #define SET_VAL(field, val) \ val 105 drivers/net/phy/mdio-xgene.h xgene_enet_set_field_value(field ## _POS, field ## _LEN, val) val 574 drivers/net/phy/mdio_bus.c int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val) val 580 drivers/net/phy/mdio_bus.c err = bus->write(bus, addr, regnum, val); val 582 drivers/net/phy/mdio_bus.c trace_mdio_access(bus, 0, addr, regnum, val, err); val 653 drivers/net/phy/mdio_bus.c int mdiobus_write_nested(struct mii_bus *bus, int addr, u32 regnum, u16 val) val 660 drivers/net/phy/mdio_bus.c err = __mdiobus_write(bus, addr, regnum, val); val 678 drivers/net/phy/mdio_bus.c int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val) val 685 drivers/net/phy/mdio_bus.c err = __mdiobus_write(bus, addr, regnum, val); val 203 drivers/net/phy/meson-gxl.c u16 val; val 207 drivers/net/phy/meson-gxl.c val = INTSRC_ANEG_PR val 214 drivers/net/phy/meson-gxl.c val = 0; val 222 drivers/net/phy/meson-gxl.c return phy_write(phydev, INTSRC_MASK, val); val 134 drivers/net/phy/micrel.c u32 regnum, u16 val) val 137 drivers/net/phy/micrel.c return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); val 184 drivers/net/phy/micrel.c static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) val 192 drivers/net/phy/micrel.c if (val) val 200 drivers/net/phy/micrel.c static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) val 222 drivers/net/phy/micrel.c temp |= val << shift; val 506 drivers/net/phy/micrel.c int val[4] = {-1, -2, -3, -4}; val 514 drivers/net/phy/micrel.c if (!of_property_read_u32(of_node, field[i], val + i)) val 527 drivers/net/phy/micrel.c if (val[i] != -(i + 1)) { val 531 drivers/net/phy/micrel.c (((val[i] / KSZ9031_PS_TO_REG) & maxval) val 661 drivers/net/phy/micrel.c int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), val 683 drivers/net/phy/micrel.c val[i] = skewval + KSZ9131_OFFSET; val 697 drivers/net/phy/micrel.c if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { val 701 drivers/net/phy/micrel.c (((val[i] / KSZ9131_STEP) & maxval) val 864 drivers/net/phy/micrel.c int val; val 867 drivers/net/phy/micrel.c val = phy_read(phydev, stat.reg); val 868 drivers/net/phy/micrel.c if (val < 0) { val 871 drivers/net/phy/micrel.c val = val & ((1 << stat.bits) - 1); val 872 drivers/net/phy/micrel.c priv->stats[i] += val; val 73 drivers/net/phy/microchip.c int val, save_page, ret = 0; val 111 drivers/net/phy/microchip.c val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR); val 112 drivers/net/phy/microchip.c if (!(val & 0x8000)) val 280 drivers/net/phy/microchip.c int val; val 284 drivers/net/phy/microchip.c val = LAN88XX_EXT_MODE_CTRL_MDI_; val 287 drivers/net/phy/microchip.c val = LAN88XX_EXT_MODE_CTRL_MDI_X_; val 290 drivers/net/phy/microchip.c val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_; val 299 drivers/net/phy/microchip.c buf |= val; val 306 drivers/net/phy/microchip.c int val; val 309 drivers/net/phy/microchip.c val = phy_read_mmd(phydev, MDIO_MMD_PCS, val 311 drivers/net/phy/microchip.c val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_; val 314 drivers/net/phy/microchip.c val); val 47 drivers/net/phy/microchip_t1.c u16 val; val 52 drivers/net/phy/microchip_t1.c u8 offset, u16 val) val 62 drivers/net/phy/microchip_t1.c rc = phy_write(phydev, offset, val); val 70 drivers/net/phy/microchip_t1.c rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val); val 90 drivers/net/phy/microchip_t1.c u8 bank, u8 offset, u16 val, u16 mask) val 97 drivers/net/phy/microchip_t1.c rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val); val 101 drivers/net/phy/microchip_t1.c new = val | (rc & (mask ^ 0xFFFF)); val 170 drivers/net/phy/microchip_t1.c init[i].val, val 174 drivers/net/phy/microchip_t1.c init[i].offset, init[i].val); val 185 drivers/net/phy/microchip_t1.c int rc, val = 0; val 191 drivers/net/phy/microchip_t1.c val = LAN87XX_MASK_LINK_UP | LAN87XX_MASK_LINK_DOWN; val 194 drivers/net/phy/microchip_t1.c rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); val 318 drivers/net/phy/mscc.c u32 val; val 471 drivers/net/phy/mscc.c int val; val 473 drivers/net/phy/mscc.c val = phy_read_paged(phydev, priv->hw_stats[i].page, val 475 drivers/net/phy/mscc.c if (val < 0) val 478 drivers/net/phy/mscc.c val = val & priv->hw_stats[i].mask; val 479 drivers/net/phy/mscc.c priv->stats[i] += val; val 888 drivers/net/phy/mscc.c static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) val 890 drivers/net/phy/mscc.c __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); val 891 drivers/net/phy/mscc.c __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); val 931 drivers/net/phy/mscc.c vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); val 971 drivers/net/phy/mscc.c vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); val 981 drivers/net/phy/mscc.c static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) val 990 drivers/net/phy/mscc.c return __mdiobus_write(phydev->mdio.bus, priv->base_addr, regnum, val); val 1007 drivers/net/phy/mscc.c static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) val 1009 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); val 1010 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); val 1015 drivers/net/phy/mscc.c static int vsc8584_cmd(struct phy_device *phydev, u16 val) val 1023 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); val 1328 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); val 1337 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); val 1507 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); val 1516 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); val 1616 drivers/net/phy/mscc.c u16 addr, val; val 1629 drivers/net/phy/mscc.c val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, val 1631 drivers/net/phy/mscc.c if (val & PHY_ADDR_REVERSED) val 1649 drivers/net/phy/mscc.c if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) { val 1668 drivers/net/phy/mscc.c val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); val 1669 drivers/net/phy/mscc.c val &= ~MAC_CFG_MASK; val 1671 drivers/net/phy/mscc.c val |= MAC_CFG_QSGMII; val 1673 drivers/net/phy/mscc.c val |= MAC_CFG_SGMII; val 1675 drivers/net/phy/mscc.c ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); val 1679 drivers/net/phy/mscc.c val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | val 1682 drivers/net/phy/mscc.c val |= PROC_CMD_QSGMII_MAC; val 1684 drivers/net/phy/mscc.c val |= PROC_CMD_SGMII_MAC; val 1686 drivers/net/phy/mscc.c ret = vsc8584_cmd(phydev, val); val 1712 drivers/net/phy/mscc.c val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); val 1713 drivers/net/phy/mscc.c val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK); val 1714 drivers/net/phy/mscc.c val |= MEDIA_OP_MODE_COPPER | (VSC8584_MAC_IF_SELECTION_SGMII << val 1716 drivers/net/phy/mscc.c ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); val 1830 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); val 1851 drivers/net/phy/mscc.c u32 val, val_l, val_h; val 1876 drivers/net/phy/mscc.c val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); val 1878 drivers/net/phy/mscc.c !(val & MSCC_PHY_CSR_CNTL_19_CMD)); val 1880 drivers/net/phy/mscc.c if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) val 1896 drivers/net/phy/mscc.c u32 target, u32 reg, u32 val) val 1914 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); val 1917 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); val 1929 drivers/net/phy/mscc.c val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); val 1931 drivers/net/phy/mscc.c !(val & MSCC_PHY_CSR_CNTL_19_CMD)); val 1933 drivers/net/phy/mscc.c if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) val 1946 drivers/net/phy/mscc.c u32 val; val 1957 drivers/net/phy/mscc.c val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg); val 1959 drivers/net/phy/mscc.c if (val == 0xffffffff) val 1962 drivers/net/phy/mscc.c } while (time_before(jiffies, deadline) && (val & op)); val 1964 drivers/net/phy/mscc.c if (val & op) val 1986 drivers/net/phy/mscc.c u16 val, addr; val 1999 drivers/net/phy/mscc.c val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); val 2001 drivers/net/phy/mscc.c if (val & PHY_ADDR_REVERSED) val 2017 drivers/net/phy/mscc.c if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) val 2025 drivers/net/phy/mscc.c val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); val 2027 drivers/net/phy/mscc.c val &= ~MAC_CFG_MASK; val 2028 drivers/net/phy/mscc.c val |= MAC_CFG_QSGMII; val 2029 drivers/net/phy/mscc.c ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); val 202 drivers/net/phy/phy-c45.c int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); val 204 drivers/net/phy/phy-c45.c return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; val 219 drivers/net/phy/phy-c45.c int val, devad; val 223 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); val 224 drivers/net/phy/phy-c45.c if (val < 0) val 225 drivers/net/phy/phy-c45.c return val; val 230 drivers/net/phy/phy-c45.c if (val & MDIO_AN_CTRL1_RESTART) { val 245 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, devad, MDIO_STAT1); val 246 drivers/net/phy/phy-c45.c if (val < 0) val 247 drivers/net/phy/phy-c45.c return val; val 248 drivers/net/phy/phy-c45.c else if (val & MDIO_STAT1_LSTATUS) val 252 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, devad, MDIO_STAT1); val 253 drivers/net/phy/phy-c45.c if (val < 0) val 254 drivers/net/phy/phy-c45.c return val; val 256 drivers/net/phy/phy-c45.c if (!(val & MDIO_STAT1_LSTATUS)) val 278 drivers/net/phy/phy-c45.c int val; val 280 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); val 281 drivers/net/phy/phy-c45.c if (val < 0) val 282 drivers/net/phy/phy-c45.c return val; val 284 drivers/net/phy/phy-c45.c if (!(val & MDIO_AN_STAT1_COMPLETE)) { val 296 drivers/net/phy/phy-c45.c val & MDIO_AN_STAT1_LPABLE); val 299 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); val 300 drivers/net/phy/phy-c45.c if (val < 0) val 301 drivers/net/phy/phy-c45.c return val; val 303 drivers/net/phy/phy-c45.c mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); val 304 drivers/net/phy/phy-c45.c phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; val 305 drivers/net/phy/phy-c45.c phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; val 308 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); val 309 drivers/net/phy/phy-c45.c if (val < 0) val 310 drivers/net/phy/phy-c45.c return val; val 312 drivers/net/phy/phy-c45.c mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); val 324 drivers/net/phy/phy-c45.c int val; val 328 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); val 329 drivers/net/phy/phy-c45.c if (val < 0) val 330 drivers/net/phy/phy-c45.c return val; val 332 drivers/net/phy/phy-c45.c switch (val & MDIO_CTRL1_SPEEDSEL) { val 368 drivers/net/phy/phy-c45.c int val; val 371 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, val 373 drivers/net/phy/phy-c45.c if (val < 0) val 374 drivers/net/phy/phy-c45.c return val; val 376 drivers/net/phy/phy-c45.c switch (val) { val 408 drivers/net/phy/phy-c45.c int val; val 412 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); val 413 drivers/net/phy/phy-c45.c if (val < 0) val 414 drivers/net/phy/phy-c45.c return val; val 416 drivers/net/phy/phy-c45.c if (val & MDIO_AN_STAT1_ABLE) val 421 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); val 422 drivers/net/phy/phy-c45.c if (val < 0) val 423 drivers/net/phy/phy-c45.c return val; val 427 drivers/net/phy/phy-c45.c val & MDIO_PMA_STAT2_10GBSR); val 431 drivers/net/phy/phy-c45.c val & MDIO_PMA_STAT2_10GBLR); val 435 drivers/net/phy/phy-c45.c val & MDIO_PMA_STAT2_10GBER); val 437 drivers/net/phy/phy-c45.c if (val & MDIO_PMA_STAT2_EXTABLE) { val 438 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); val 439 drivers/net/phy/phy-c45.c if (val < 0) val 440 drivers/net/phy/phy-c45.c return val; val 444 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_10GBLRM); val 447 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_10GBT); val 450 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_10GBKX4); val 453 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_10GBKR); val 456 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_1000BT); val 459 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_1000BKX); val 463 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_100BTX); val 466 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_100BTX); val 470 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_10BT); val 473 drivers/net/phy/phy-c45.c val & MDIO_PMA_EXTABLE_10BT); val 475 drivers/net/phy/phy-c45.c if (val & MDIO_PMA_EXTABLE_NBT) { val 476 drivers/net/phy/phy-c45.c val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, val 478 drivers/net/phy/phy-c45.c if (val < 0) val 479 drivers/net/phy/phy-c45.c return val; val 483 drivers/net/phy/phy-c45.c val & MDIO_PMA_NG_EXTABLE_2_5GBT); val 487 drivers/net/phy/phy-c45.c val & MDIO_PMA_NG_EXTABLE_5GBT); val 377 drivers/net/phy/phy-core.c int val; val 383 drivers/net/phy/phy-core.c val = phydev->drv->read_mmd(phydev, devad, regnum); val 387 drivers/net/phy/phy-core.c val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, addr); val 395 drivers/net/phy/phy-core.c val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA); val 397 drivers/net/phy/phy-core.c return val; val 432 drivers/net/phy/phy-core.c int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) val 440 drivers/net/phy/phy-core.c ret = phydev->drv->write_mmd(phydev, devad, regnum, val); val 445 drivers/net/phy/phy-core.c addr, val); val 453 drivers/net/phy/phy-core.c __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); val 471 drivers/net/phy/phy-core.c int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) val 476 drivers/net/phy/phy-core.c ret = __phy_write_mmd(phydev, devad, regnum, val); val 812 drivers/net/phy/phy-core.c int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val) val 818 drivers/net/phy/phy-core.c ret = __phy_write(phydev, regnum, val); val 401 drivers/net/phy/phy.c u16 val = mii_data->val_in; val 435 drivers/net/phy/phy.c if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0) { val 439 drivers/net/phy/phy.c if (val & BMCR_FULLDPLX) val 443 drivers/net/phy/phy.c if (val & BMCR_SPEED1000) val 445 drivers/net/phy/phy.c else if (val & BMCR_SPEED100) val 457 drivers/net/phy/phy.c val); val 462 drivers/net/phy/phy.c val); val 471 drivers/net/phy/phy.c mdiobus_write(phydev->mdio.bus, prtad, devad, val); val 475 drivers/net/phy/phy.c val & BMCR_RESET) val 1095 drivers/net/phy/phy.c int val; val 1101 drivers/net/phy/phy.c val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); val 1102 drivers/net/phy/phy.c if (val < 0) val 1103 drivers/net/phy/phy.c return val; val 1104 drivers/net/phy/phy.c data->supported = mmd_eee_cap_to_ethtool_sup_t(val); val 1107 drivers/net/phy/phy.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); val 1108 drivers/net/phy/phy.c if (val < 0) val 1109 drivers/net/phy/phy.c return val; val 1110 drivers/net/phy/phy.c data->advertised = mmd_eee_adv_to_ethtool_adv_t(val); val 1114 drivers/net/phy/phy.c val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); val 1115 drivers/net/phy/phy.c if (val < 0) val 1116 drivers/net/phy/phy.c return val; val 1117 drivers/net/phy/phy.c data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); val 1941 drivers/net/phy/phy_device.c int val; val 1947 drivers/net/phy/phy_device.c val = phy_read(phydev, MII_BMSR); val 1948 drivers/net/phy/phy_device.c if (val < 0) val 1949 drivers/net/phy/phy_device.c return val; val 1952 drivers/net/phy/phy_device.c val & BMSR_ANEGCAPABLE); val 1955 drivers/net/phy/phy_device.c val & BMSR_100FULL); val 1957 drivers/net/phy/phy_device.c val & BMSR_100HALF); val 1959 drivers/net/phy/phy_device.c val & BMSR_10FULL); val 1961 drivers/net/phy/phy_device.c val & BMSR_10HALF); val 1963 drivers/net/phy/phy_device.c if (val & BMSR_ESTATEN) { val 1964 drivers/net/phy/phy_device.c val = phy_read(phydev, MII_ESTATUS); val 1965 drivers/net/phy/phy_device.c if (val < 0) val 1966 drivers/net/phy/phy_device.c return val; val 1969 drivers/net/phy/phy_device.c phydev->supported, val & ESTATUS_1000_TFULL); val 1971 drivers/net/phy/phy_device.c phydev->supported, val & ESTATUS_1000_THALF); val 1973 drivers/net/phy/phy_device.c phydev->supported, val & ESTATUS_1000_XFULL); val 1991 drivers/net/phy/phy_device.c u16 regnum, u16 val) val 1459 drivers/net/phy/phylink.c int val; val 1467 drivers/net/phy/phylink.c val = swphy_read_reg(reg, &fs); val 1470 drivers/net/phy/phylink.c val &= ~BMSR_ANEGCOMPLETE; val 1472 drivers/net/phy/phylink.c return val; val 1516 drivers/net/phy/phylink.c unsigned int reg, unsigned int val) val 1553 drivers/net/phy/phylink.c return mdiobus_write(phydev->mdio.bus, prtad, devad, val); val 1560 drivers/net/phy/phylink.c int val = 0xffff; val 1566 drivers/net/phy/phylink.c val = phylink_mii_emul_read(reg, &state); val 1575 drivers/net/phy/phylink.c val = phylink_get_mac_state(pl, &state); val 1576 drivers/net/phy/phylink.c if (val < 0) val 1577 drivers/net/phy/phylink.c return val; val 1579 drivers/net/phy/phylink.c val = phylink_mii_emul_read(reg, &state); val 1584 drivers/net/phy/phylink.c return val & 0xffff; val 1588 drivers/net/phy/phylink.c unsigned int reg, unsigned int val) val 95 drivers/net/phy/realtek.c u16 val; val 98 drivers/net/phy/realtek.c val = BIT(13) | BIT(12) | BIT(11); val 100 drivers/net/phy/realtek.c val = 0; val 102 drivers/net/phy/realtek.c return phy_write_paged(phydev, 0x7, RTL8201F_IER, val); val 133 drivers/net/phy/realtek.c u16 val; val 136 drivers/net/phy/realtek.c val = RTL8211F_INER_LINK_STATUS; val 138 drivers/net/phy/realtek.c val = 0; val 140 drivers/net/phy/realtek.c return phy_write_paged(phydev, 0xa42, RTL821x_INER, val); val 175 drivers/net/phy/realtek.c u16 val; val 184 drivers/net/phy/realtek.c val = 0; val 188 drivers/net/phy/realtek.c val = RTL8211F_TX_DELAY; val 195 drivers/net/phy/realtek.c val); val 202 drivers/net/phy/realtek.c val ? "Enabling" : "Disabling"); val 206 drivers/net/phy/realtek.c val ? "enabled" : "disabled"); val 215 drivers/net/phy/realtek.c u16 val; val 220 drivers/net/phy/realtek.c val = 0; val 223 drivers/net/phy/realtek.c val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; val 226 drivers/net/phy/realtek.c val = RTL8211E_RX_DELAY; val 229 drivers/net/phy/realtek.c val = RTL8211E_TX_DELAY; val 252 drivers/net/phy/realtek.c val); val 310 drivers/net/phy/realtek.c u16 val) val 316 drivers/net/phy/realtek.c ret = __phy_write(phydev, 0x10, val); val 350 drivers/net/phy/realtek.c u16 val) val 352 drivers/net/phy/realtek.c int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); val 359 drivers/net/phy/realtek.c ret = __phy_write(phydev, 0x12, val); val 368 drivers/net/phy/realtek.c int val; val 370 drivers/net/phy/realtek.c val = phy_read_paged(phydev, 0xa61, 0x13); val 371 drivers/net/phy/realtek.c if (val < 0) val 372 drivers/net/phy/realtek.c return val; val 375 drivers/net/phy/realtek.c phydev->supported, val & RTL_SUPPORTS_2500FULL); val 377 drivers/net/phy/realtek.c phydev->supported, val & RTL_SUPPORTS_5000FULL); val 379 drivers/net/phy/realtek.c phydev->supported, val & RTL_SUPPORTS_10000FULL); val 425 drivers/net/phy/realtek.c int val; val 428 drivers/net/phy/realtek.c val = phy_read(phydev, 0x13); val 431 drivers/net/phy/realtek.c return val >= 0 && val & RTL_SUPPORTS_2500FULL; val 88 drivers/net/phy/rockchip.c int val, ret; val 94 drivers/net/phy/rockchip.c val = phy_read(phydev, MII_INTERNAL_CTRL_STATUS); val 95 drivers/net/phy/rockchip.c if (val < 0) val 96 drivers/net/phy/rockchip.c return val; val 97 drivers/net/phy/rockchip.c val &= ~MII_AUTO_MDIX_EN; val 98 drivers/net/phy/rockchip.c ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); val 123 drivers/net/phy/rockchip.c int reg, err, val; val 131 drivers/net/phy/rockchip.c val = reg; val 134 drivers/net/phy/rockchip.c val &= ~MII_MDIX_EN; val 137 drivers/net/phy/rockchip.c val |= MII_MDIX_EN; val 145 drivers/net/phy/rockchip.c if (val != reg) { val 147 drivers/net/phy/rockchip.c err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); val 510 drivers/net/phy/sfp.c __be16 val; val 513 drivers/net/phy/sfp.c err = sfp_read(sfp, true, reg, &val, sizeof(val)); val 517 drivers/net/phy/sfp.c *value = be16_to_cpu(val); val 1381 drivers/net/phy/sfp.c u8 val; val 1416 drivers/net/phy/sfp.c err = sfp_read(sfp, true, SFP_EXT_STATUS, &val, sizeof(val)); val 1417 drivers/net/phy/sfp.c if (err != sizeof(val)) { val 1423 drivers/net/phy/sfp.c val |= BIT(0); val 1425 drivers/net/phy/sfp.c err = sfp_write(sfp, true, SFP_EXT_STATUS, &val, sizeof(val)); val 1426 drivers/net/phy/sfp.c if (err != sizeof(val)) { val 1572 drivers/net/phy/sfp.c int val = sfp_sm_mod_probe(sfp); val 1574 drivers/net/phy/sfp.c if (val == 0) val 1576 drivers/net/phy/sfp.c else if (val > 0) val 1577 drivers/net/phy/sfp.c sfp_sm_ins_next(sfp, SFP_MOD_HPOWER, val); val 1578 drivers/net/phy/sfp.c else if (val != -EAGAIN) val 170 drivers/net/phy/smsc.c int val; val 173 drivers/net/phy/smsc.c val = phy_read(phydev, stat.reg); val 174 drivers/net/phy/smsc.c if (val < 0) val 177 drivers/net/phy/smsc.c ret = val; val 170 drivers/net/phy/spi_ks8995.c static inline u8 get_chip_id(u8 val) val 172 drivers/net/phy/spi_ks8995.c return (val >> ID1_CHIPID_S) & ID1_CHIPID_M; val 175 drivers/net/phy/spi_ks8995.c static inline u8 get_chip_rev(u8 val) val 177 drivers/net/phy/spi_ks8995.c return (val >> ID1_REVISION_S) & ID1_REVISION_M; val 265 drivers/net/phy/spi_ks8995.c static inline int ks8995_write_reg(struct ks8995_switch *ks, u8 addr, u8 val) val 267 drivers/net/phy/spi_ks8995.c char buf = val; val 35 drivers/net/phy/xilinx_gmii2rgmii.c u16 val = 0; val 45 drivers/net/phy/xilinx_gmii2rgmii.c val = mdiobus_read(bus, addr, XILINX_GMII2RGMII_REG); val 46 drivers/net/phy/xilinx_gmii2rgmii.c val &= ~XILINX_GMII2RGMII_SPEED_MASK; val 49 drivers/net/phy/xilinx_gmii2rgmii.c val |= BMCR_SPEED1000; val 51 drivers/net/phy/xilinx_gmii2rgmii.c val |= BMCR_SPEED100; val 53 drivers/net/phy/xilinx_gmii2rgmii.c val |= BMCR_SPEED10; val 55 drivers/net/phy/xilinx_gmii2rgmii.c mdiobus_write(bus, addr, XILINX_GMII2RGMII_REG, val); val 288 drivers/net/ppp/ppp_async.c int err, val; val 317 drivers/net/ppp/ppp_async.c val = 0; val 318 drivers/net/ppp/ppp_async.c if (put_user(val, p)) val 408 drivers/net/ppp/ppp_async.c int err, val; val 414 drivers/net/ppp/ppp_async.c val = ap->flags | ap->rbits; val 415 drivers/net/ppp/ppp_async.c if (put_user(val, p)) val 420 drivers/net/ppp/ppp_async.c if (get_user(val, p)) val 422 drivers/net/ppp/ppp_async.c ap->flags = val & ~SC_RCV_BITS; val 424 drivers/net/ppp/ppp_async.c ap->rbits = val & SC_RCV_BITS; val 471 drivers/net/ppp/ppp_async.c if (get_user(val, p)) val 473 drivers/net/ppp/ppp_async.c if (val < PPP_MRU) val 474 drivers/net/ppp/ppp_async.c val = PPP_MRU; val 475 drivers/net/ppp/ppp_async.c ap->mru = val; val 954 drivers/net/ppp/ppp_async.c u32 val; val 997 drivers/net/ppp/ppp_async.c val = get_unaligned_be16(data + 2); val 999 drivers/net/ppp/ppp_async.c ap->mru = val; val 1001 drivers/net/ppp/ppp_async.c ap->chan.mtu = val; val 1004 drivers/net/ppp/ppp_async.c val = get_unaligned_be32(data + 2); val 1006 drivers/net/ppp/ppp_async.c ap->raccm = val; val 1008 drivers/net/ppp/ppp_async.c ap->xaccm[0] = val; val 585 drivers/net/ppp/ppp_generic.c int err = -EFAULT, val, val2, i; val 652 drivers/net/ppp/ppp_generic.c if (get_user(val, p)) val 654 drivers/net/ppp/ppp_generic.c ppp->mru = val; val 659 drivers/net/ppp/ppp_generic.c if (get_user(val, p)) val 662 drivers/net/ppp/ppp_generic.c cflags = ppp->flags & ~val; val 664 drivers/net/ppp/ppp_generic.c if (!(ppp->flags & SC_MULTILINK) && (val & SC_MULTILINK)) val 667 drivers/net/ppp/ppp_generic.c ppp->flags = val & SC_FLAG_BITS; val 675 drivers/net/ppp/ppp_generic.c val = ppp->flags | ppp->xstate | ppp->rstate; val 676 drivers/net/ppp/ppp_generic.c if (put_user(val, p)) val 692 drivers/net/ppp/ppp_generic.c if (get_user(val, p)) val 694 drivers/net/ppp/ppp_generic.c ppp->debug = val; val 713 drivers/net/ppp/ppp_generic.c if (get_user(val, p)) val 716 drivers/net/ppp/ppp_generic.c if ((val >> 16) != 0) { val 717 drivers/net/ppp/ppp_generic.c val2 = val >> 16; val 718 drivers/net/ppp/ppp_generic.c val &= 0xffff; val 720 drivers/net/ppp/ppp_generic.c vj = slhc_init(val2+1, val+1); val 811 drivers/net/ppp/ppp_generic.c if (get_user(val, p)) val 814 drivers/net/ppp/ppp_generic.c ppp->mrru = val; val 282 drivers/net/ppp/ppp_synctty.c int err, val; val 310 drivers/net/ppp/ppp_synctty.c val = 0; val 311 drivers/net/ppp/ppp_synctty.c if (put_user(val, p)) val 399 drivers/net/ppp/ppp_synctty.c int err, val; val 407 drivers/net/ppp/ppp_synctty.c val = ap->flags | ap->rbits; val 408 drivers/net/ppp/ppp_synctty.c if (put_user(val, (int __user *) argp)) val 413 drivers/net/ppp/ppp_synctty.c if (get_user(val, (int __user *) argp)) val 415 drivers/net/ppp/ppp_synctty.c ap->flags = val & ~SC_RCV_BITS; val 417 drivers/net/ppp/ppp_synctty.c ap->rbits = val & SC_RCV_BITS; val 464 drivers/net/ppp/ppp_synctty.c if (get_user(val, (int __user *) argp)) val 466 drivers/net/ppp/ppp_synctty.c if (val < PPP_MRU) val 467 drivers/net/ppp/ppp_synctty.c val = PPP_MRU; val 468 drivers/net/ppp/ppp_synctty.c ap->mru = val; val 743 drivers/net/ppp/pppoe.c int val; val 767 drivers/net/ppp/pppoe.c if (get_user(val, (int __user *)arg)) val 770 drivers/net/ppp/pppoe.c if (val < (po->pppoe_dev->mtu val 780 drivers/net/ppp/pppoe.c if (get_user(val, (int __user *)arg)) val 575 drivers/net/ppp/pptp.c int err, val; val 580 drivers/net/ppp/pptp.c val = opt->ppp_flags; val 581 drivers/net/ppp/pptp.c if (put_user(val, p)) val 586 drivers/net/ppp/pptp.c if (get_user(val, p)) val 588 drivers/net/ppp/pptp.c opt->ppp_flags = val & ~SC_RCV_BITS; val 56 drivers/net/sungem_phy.c static inline void __sungem_phy_write(struct mii_phy* phy, int id, int reg, int val) val 58 drivers/net/sungem_phy.c phy->mdio_write(phy->dev, id, reg, val); val 66 drivers/net/sungem_phy.c static inline void sungem_phy_write(struct mii_phy* phy, int reg, int val) val 68 drivers/net/sungem_phy.c phy->mdio_write(phy->dev, phy->mii_id, reg, val); val 73 drivers/net/sungem_phy.c u16 val; val 76 drivers/net/sungem_phy.c val = __sungem_phy_read(phy, phy_id, MII_BMCR); val 77 drivers/net/sungem_phy.c val &= ~(BMCR_ISOLATE | BMCR_PDOWN); val 78 drivers/net/sungem_phy.c val |= BMCR_RESET; val 79 drivers/net/sungem_phy.c __sungem_phy_write(phy, phy_id, MII_BMCR, val); val 84 drivers/net/sungem_phy.c val = __sungem_phy_read(phy, phy_id, MII_BMCR); val 85 drivers/net/sungem_phy.c if ((val & BMCR_RESET) == 0) val 89 drivers/net/sungem_phy.c if ((val & BMCR_ISOLATE) && limit > 0) val 90 drivers/net/sungem_phy.c __sungem_phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE); val 551 drivers/net/sungem_phy.c u16 val; val 554 drivers/net/sungem_phy.c val = sungem_phy_read(phy, MII_BCM5400_AUXSTATUS); val 555 drivers/net/sungem_phy.c link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >> val 563 drivers/net/sungem_phy.c val = sungem_phy_read(phy, MII_LPA); val 565 drivers/net/sungem_phy.c ((val & LPA_PAUSE) != 0); val 86 drivers/net/tap.c static inline u16 tap16_to_cpu(struct tap_queue *q, __virtio16 val) val 88 drivers/net/tap.c return __virtio16_to_cpu(tap_is_little_endian(q), val); val 91 drivers/net/tap.c static inline __virtio16 cpu_to_tap16(struct tap_queue *q, u16 val) val 93 drivers/net/tap.c return __cpu_to_virtio16(tap_is_little_endian(q), val); val 630 drivers/net/team/team.c int val; val 638 drivers/net/team/team.c val = atomic_dec_if_positive(&team->notify_peers.count_pending); val 639 drivers/net/team/team.c if (val < 0) { val 645 drivers/net/team/team.c if (val) val 676 drivers/net/team/team.c int val; val 684 drivers/net/team/team.c val = atomic_dec_if_positive(&team->mcast_rejoin.count_pending); val 685 drivers/net/team/team.c if (val < 0) { val 691 drivers/net/team/team.c if (val) val 393 drivers/net/tun.c static inline u16 tun16_to_cpu(struct tun_struct *tun, __virtio16 val) val 395 drivers/net/tun.c return __virtio16_to_cpu(tun_is_little_endian(tun), val); val 398 drivers/net/tun.c static inline __virtio16 cpu_to_tun16(struct tun_struct *tun, u16 val) val 400 drivers/net/tun.c return __cpu_to_virtio16(tun_is_little_endian(tun), val); val 224 drivers/net/usb/asix.h void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val); val 228 drivers/net/usb/asix.h int val); val 477 drivers/net/usb/asix_common.c void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val) val 480 drivers/net/usb/asix_common.c __le16 res = cpu_to_le16(val); val 486 drivers/net/usb/asix_common.c phy_id, loc, val); val 542 drivers/net/usb/asix_common.c asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc, int val) val 545 drivers/net/usb/asix_common.c __le16 res = cpu_to_le16(val); val 551 drivers/net/usb/asix_common.c phy_id, loc, val); val 36 drivers/net/usb/ax88172a.c u16 val) val 38 drivers/net/usb/ax88172a.c asix_mdio_write(((struct usbnet *)bus->priv)->net, phy_id, regnum, val); val 362 drivers/net/usb/ax88179_178a.c int val) val 365 drivers/net/usb/ax88179_178a.c u16 res = (u16) val; val 634 drivers/net/usb/ax88179_178a.c int val; val 637 drivers/net/usb/ax88179_178a.c val = ax88179_phy_read_mmd_indirect(dev, MDIO_PCS_EEE_ABLE, val 639 drivers/net/usb/ax88179_178a.c if (val < 0) val 640 drivers/net/usb/ax88179_178a.c return val; val 641 drivers/net/usb/ax88179_178a.c data->supported = mmd_eee_cap_to_ethtool_sup_t(val); val 644 drivers/net/usb/ax88179_178a.c val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_ADV, val 646 drivers/net/usb/ax88179_178a.c if (val < 0) val 647 drivers/net/usb/ax88179_178a.c return val; val 648 drivers/net/usb/ax88179_178a.c data->advertised = mmd_eee_adv_to_ethtool_adv_t(val); val 651 drivers/net/usb/ax88179_178a.c val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_LPABLE, val 653 drivers/net/usb/ax88179_178a.c if (val < 0) val 654 drivers/net/usb/ax88179_178a.c return val; val 655 drivers/net/usb/ax88179_178a.c data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); val 195 drivers/net/usb/catc.c #define catc_set_reg(catc, reg, val) catc_ctrl_msg(catc, USB_DIR_OUT, SetReg, val, reg, NULL, 0) val 204 drivers/net/usb/catc.c #define catc_set_reg_async(catc, reg, val) catc_ctrl_async(catc, USB_DIR_OUT, SetReg, val, reg, NULL, 0, NULL) val 152 drivers/net/usb/cdc_ncm.c u32 val, max, min; val 165 drivers/net/usb/cdc_ncm.c val = clamp_t(u32, new_rx, min, max); val 166 drivers/net/usb/cdc_ncm.c if (val != new_rx) val 169 drivers/net/usb/cdc_ncm.c return val; val 175 drivers/net/usb/cdc_ncm.c u32 val, max, min; val 184 drivers/net/usb/cdc_ncm.c val = clamp_t(u32, new_tx, min, max); val 185 drivers/net/usb/cdc_ncm.c if (val != new_tx) val 188 drivers/net/usb/cdc_ncm.c return val; val 227 drivers/net/usb/cdc_ncm.c unsigned long val; val 230 drivers/net/usb/cdc_ncm.c if (kstrtoul(buf, 0, &val)) val 233 drivers/net/usb/cdc_ncm.c ctx->min_tx_pkt = val; val 241 drivers/net/usb/cdc_ncm.c unsigned long val; val 243 drivers/net/usb/cdc_ncm.c if (kstrtoul(buf, 0, &val) || cdc_ncm_check_rx_max(dev, val) != val) val 246 drivers/net/usb/cdc_ncm.c cdc_ncm_update_rxtx_max(dev, val, ctx->tx_max); val 254 drivers/net/usb/cdc_ncm.c unsigned long val; val 256 drivers/net/usb/cdc_ncm.c if (kstrtoul(buf, 0, &val) || cdc_ncm_check_tx_max(dev, val) != val) val 259 drivers/net/usb/cdc_ncm.c cdc_ncm_update_rxtx_max(dev, ctx->rx_max, val); val 268 drivers/net/usb/cdc_ncm.c unsigned long val; val 270 drivers/net/usb/cdc_ncm.c ret = kstrtoul(buf, 0, &val); val 273 drivers/net/usb/cdc_ncm.c if (val && (val < CDC_NCM_TIMER_INTERVAL_MIN || val > CDC_NCM_TIMER_INTERVAL_MAX)) val 277 drivers/net/usb/cdc_ncm.c ctx->timer_interval = val * NSEC_PER_USEC; val 380 drivers/net/usb/cdc_ncm.c u32 val; val 382 drivers/net/usb/cdc_ncm.c val = cdc_ncm_check_rx_max(dev, new_rx); val 385 drivers/net/usb/cdc_ncm.c if (val != ctx->rx_max) { val 386 drivers/net/usb/cdc_ncm.c __le32 dwNtbInMaxSize = cpu_to_le32(val); val 388 drivers/net/usb/cdc_ncm.c dev_info(&dev->intf->dev, "setting rx_max = %u\n", val); val 397 drivers/net/usb/cdc_ncm.c ctx->rx_max = val; val 407 drivers/net/usb/cdc_ncm.c val = cdc_ncm_check_tx_max(dev, new_tx); val 408 drivers/net/usb/cdc_ncm.c if (val != ctx->tx_max) val 409 drivers/net/usb/cdc_ncm.c dev_info(&dev->intf->dev, "setting tx_max = %u\n", val); val 418 drivers/net/usb/cdc_ncm.c if (val != le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize) && val 419 drivers/net/usb/cdc_ncm.c val % usb_maxpacket(dev->udev, dev->out, 1) == 0) val 420 drivers/net/usb/cdc_ncm.c val++; val 423 drivers/net/usb/cdc_ncm.c if (netif_running(dev->net) && val > ctx->tx_max) { val 431 drivers/net/usb/cdc_ncm.c ctx->tx_max = val; val 434 drivers/net/usb/cdc_ncm.c ctx->tx_max = val; val 612 drivers/net/usb/cdc_ncm.c u32 val; val 620 drivers/net/usb/cdc_ncm.c val = ctx->tx_ndp_modulus; val 622 drivers/net/usb/cdc_ncm.c if ((val < USB_CDC_NCM_NDP_ALIGN_MIN_SIZE) || val 623 drivers/net/usb/cdc_ncm.c (val != ((-val) & val)) || (val >= ctx->tx_max)) { val 634 drivers/net/usb/cdc_ncm.c val = ctx->tx_modulus; val 636 drivers/net/usb/cdc_ncm.c if ((val < USB_CDC_NCM_NDP_ALIGN_MIN_SIZE) || val 637 drivers/net/usb/cdc_ncm.c (val != ((-val) & val)) || (val >= ctx->tx_max)) { val 197 drivers/net/usb/ch9200.c int phy_id, int loc, int val) val 208 drivers/net/usb/ch9200.c buff[0] = (unsigned char)val; val 209 drivers/net/usb/ch9200.c buff[1] = (unsigned char)(val >> 8); val 240 drivers/net/usb/dm9601.c int val) val 243 drivers/net/usb/dm9601.c __le16 res = cpu_to_le16(val); val 251 drivers/net/usb/dm9601.c phy_id, loc, val); val 1655 drivers/net/usb/hso.c int val = 0; val 1685 drivers/net/usb/hso.c val |= 0x01; val 1687 drivers/net/usb/hso.c val |= 0x02; val 1693 drivers/net/usb/hso.c 0x21, val, if_num, NULL, 0, val 614 drivers/net/usb/lan78xx.c u32 val; val 618 drivers/net/usb/lan78xx.c ret = lan78xx_read_reg(dev, MII_ACC, &val); val 622 drivers/net/usb/lan78xx.c if (!(val & MII_ACC_MII_BUSY_)) val 647 drivers/net/usb/lan78xx.c u32 val; val 651 drivers/net/usb/lan78xx.c ret = lan78xx_read_reg(dev, E2P_CMD, &val); val 655 drivers/net/usb/lan78xx.c if (!(val & E2P_CMD_EPC_BUSY_) || val 656 drivers/net/usb/lan78xx.c (val & E2P_CMD_EPC_TIMEOUT_)) val 661 drivers/net/usb/lan78xx.c if (val & (E2P_CMD_EPC_TIMEOUT_ | E2P_CMD_EPC_BUSY_)) { val 672 drivers/net/usb/lan78xx.c u32 val; val 676 drivers/net/usb/lan78xx.c ret = lan78xx_read_reg(dev, E2P_CMD, &val); val 680 drivers/net/usb/lan78xx.c if (!(val & E2P_CMD_EPC_BUSY_)) val 693 drivers/net/usb/lan78xx.c u32 val; val 701 drivers/net/usb/lan78xx.c ret = lan78xx_read_reg(dev, HW_CFG, &val); val 702 drivers/net/usb/lan78xx.c saved = val; val 704 drivers/net/usb/lan78xx.c val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_); val 705 drivers/net/usb/lan78xx.c ret = lan78xx_write_reg(dev, HW_CFG, val); val 713 drivers/net/usb/lan78xx.c val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_; val 714 drivers/net/usb/lan78xx.c val |= (offset & E2P_CMD_EPC_ADDR_MASK_); val 715 drivers/net/usb/lan78xx.c ret = lan78xx_write_reg(dev, E2P_CMD, val); val 725 drivers/net/usb/lan78xx.c ret = lan78xx_read_reg(dev, E2P_DATA, &val); val 731 drivers/net/usb/lan78xx.c data[i] = val & 0xFF; val 761 drivers/net/usb/lan78xx.c u32 val; val 769 drivers/net/usb/lan78xx.c ret = lan78xx_read_reg(dev, HW_CFG, &val); val 770 drivers/net/usb/lan78xx.c saved = val; val 772 drivers/net/usb/lan78xx.c val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_); val 773 drivers/net/usb/lan78xx.c ret = lan78xx_write_reg(dev, HW_CFG, val); val 781 drivers/net/usb/lan78xx.c val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_; val 782 drivers/net/usb/lan78xx.c ret = lan78xx_write_reg(dev, E2P_CMD, val); val 794 drivers/net/usb/lan78xx.c val = data[i]; val 795 drivers/net/usb/lan78xx.c ret = lan78xx_write_reg(dev, E2P_DATA, val); val 802 drivers/net/usb/lan78xx.c val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_; val 803 drivers/net/usb/lan78xx.c val |= (offset & E2P_CMD_EPC_ADDR_MASK_); val 804 drivers/net/usb/lan78xx.c ret = lan78xx_write_reg(dev, E2P_CMD, val); val 1729 drivers/net/usb/lan78xx.c u32 val, addr; val 1751 drivers/net/usb/lan78xx.c ret = lan78xx_read_reg(dev, MII_DATA, &val); val 1753 drivers/net/usb/lan78xx.c ret = (int)(val & 0xFFFF); val 1766 drivers/net/usb/lan78xx.c u32 val, addr; val 1780 drivers/net/usb/lan78xx.c val = (u32)regval; val 1781 drivers/net/usb/lan78xx.c ret = lan78xx_write_reg(dev, MII_DATA, val); val 171 drivers/net/usb/mcs7830.c __le16 val; val 196 drivers/net/usb/mcs7830.c ret = mcs7830_get_reg(dev, HIF_REG_PHY_DATA, 2, &val); val 199 drivers/net/usb/mcs7830.c ret = le16_to_cpu(val); val 201 drivers/net/usb/mcs7830.c index, val, i); val 207 drivers/net/usb/mcs7830.c static int mcs7830_write_phy(struct usbnet *dev, u8 index, u16 val) val 221 drivers/net/usb/mcs7830.c le_val = cpu_to_le16(val); val 244 drivers/net/usb/mcs7830.c index, val, i); val 313 drivers/net/usb/mcs7830.c int location, int val) val 316 drivers/net/usb/mcs7830.c mcs7830_write_phy(dev, location, val); val 274 drivers/net/usb/pegasus.c static void mdio_write(struct net_device *dev, int phy_id, int loc, int val) val 277 drivers/net/usb/pegasus.c u16 data = val; val 58 drivers/net/usb/plusb.c pl_vendor_req(struct usbnet *dev, u8 req, u8 val, u8 index) val 63 drivers/net/usb/plusb.c val, index, NULL, 0); val 67 drivers/net/usb/plusb.c pl_clear_QuickLink_features(struct usbnet *dev, int val) val 69 drivers/net/usb/plusb.c return pl_vendor_req(dev, 1, (u8) val, 0); val 73 drivers/net/usb/plusb.c pl_set_QuickLink_features(struct usbnet *dev, int val) val 75 drivers/net/usb/plusb.c return pl_vendor_req(dev, 3, (u8) val, 0); val 1183 drivers/net/usb/r8152.c void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) val 1193 drivers/net/usb/r8152.c r8152_mdio_write(tp, reg, val); val 5099 drivers/net/usb/r8152.c u16 val; val 5101 drivers/net/usb/r8152.c val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); val 5102 drivers/net/usb/r8152.c supported = mmd_eee_cap_to_ethtool_sup_t(val); val 5104 drivers/net/usb/r8152.c val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); val 5105 drivers/net/usb/r8152.c adv = mmd_eee_adv_to_ethtool_adv_t(val); val 5107 drivers/net/usb/r8152.c val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); val 5108 drivers/net/usb/r8152.c lp = mmd_eee_adv_to_ethtool_adv_t(val); val 5121 drivers/net/usb/r8152.c u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); val 5124 drivers/net/usb/r8152.c tp->eee_adv = val; val 5134 drivers/net/usb/r8152.c u16 val; val 5136 drivers/net/usb/r8152.c val = ocp_reg_read(tp, OCP_EEE_ABLE); val 5137 drivers/net/usb/r8152.c supported = mmd_eee_cap_to_ethtool_sup_t(val); val 5139 drivers/net/usb/r8152.c val = ocp_reg_read(tp, OCP_EEE_ADV); val 5140 drivers/net/usb/r8152.c adv = mmd_eee_adv_to_ethtool_adv_t(val); val 5142 drivers/net/usb/r8152.c val = ocp_reg_read(tp, OCP_EEE_LPABLE); val 5143 drivers/net/usb/r8152.c lp = mmd_eee_adv_to_ethtool_adv_t(val); val 5308 drivers/net/usb/r8152.c u32 val; val 5312 drivers/net/usb/r8152.c val = *(u32 *)d; val 5313 drivers/net/usb/r8152.c if (val < ETH_ZLEN) { val 5319 drivers/net/usb/r8152.c if (tp->rx_copybreak != val) { val 5323 drivers/net/usb/r8152.c tp->rx_copybreak = val; val 5327 drivers/net/usb/r8152.c tp->rx_copybreak = val; val 162 drivers/net/usb/smsc75xx.c u32 val; val 166 drivers/net/usb/smsc75xx.c ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm); val 172 drivers/net/usb/smsc75xx.c if (!(val & MII_ACCESS_BUSY)) val 183 drivers/net/usb/smsc75xx.c u32 val, addr; val 213 drivers/net/usb/smsc75xx.c ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm); val 219 drivers/net/usb/smsc75xx.c ret = (u16)(val & 0xFFFF); val 230 drivers/net/usb/smsc75xx.c u32 val, addr; val 242 drivers/net/usb/smsc75xx.c val = regval; val 243 drivers/net/usb/smsc75xx.c ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm); val 297 drivers/net/usb/smsc75xx.c u32 val; val 301 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg(dev, E2P_CMD, &val); val 307 drivers/net/usb/smsc75xx.c if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT)) val 312 drivers/net/usb/smsc75xx.c if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) { val 323 drivers/net/usb/smsc75xx.c u32 val; val 327 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg(dev, E2P_CMD, &val); val 333 drivers/net/usb/smsc75xx.c if (!(val & E2P_CMD_BUSY)) val 346 drivers/net/usb/smsc75xx.c u32 val; val 357 drivers/net/usb/smsc75xx.c val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR); val 358 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg(dev, E2P_CMD, val); val 368 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg(dev, E2P_DATA, &val); val 374 drivers/net/usb/smsc75xx.c data[i] = val & 0xFF; val 384 drivers/net/usb/smsc75xx.c u32 val; val 395 drivers/net/usb/smsc75xx.c val = E2P_CMD_BUSY | E2P_CMD_EWEN; val 396 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg(dev, E2P_CMD, val); val 409 drivers/net/usb/smsc75xx.c val = data[i]; val 410 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg(dev, E2P_DATA, val); val 417 drivers/net/usb/smsc75xx.c val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR); val 418 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg(dev, E2P_CMD, val); val 1566 drivers/net/usb/smsc75xx.c u32 val; val 1569 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val); val 1575 drivers/net/usb/smsc75xx.c val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST)); val 1576 drivers/net/usb/smsc75xx.c val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS; val 1578 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 1592 drivers/net/usb/smsc75xx.c u32 val; val 1595 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val); val 1601 drivers/net/usb/smsc75xx.c val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST); val 1602 drivers/net/usb/smsc75xx.c val |= PMT_CTL_SUS_MODE_1; val 1604 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 1611 drivers/net/usb/smsc75xx.c val &= ~PMT_CTL_WUPS; val 1612 drivers/net/usb/smsc75xx.c val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN); val 1614 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 1628 drivers/net/usb/smsc75xx.c u32 val; val 1631 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val); val 1637 drivers/net/usb/smsc75xx.c val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST); val 1638 drivers/net/usb/smsc75xx.c val |= PMT_CTL_SUS_MODE_2; val 1640 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 1654 drivers/net/usb/smsc75xx.c u32 val; val 1657 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val); val 1663 drivers/net/usb/smsc75xx.c if (val & FCT_RX_CTL_RXUSED) { val 1668 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val); val 1674 drivers/net/usb/smsc75xx.c val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST); val 1675 drivers/net/usb/smsc75xx.c val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN; val 1677 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 1684 drivers/net/usb/smsc75xx.c val &= ~PMT_CTL_WUPS; val 1685 drivers/net/usb/smsc75xx.c val |= PMT_CTL_WUPS_WOL; val 1687 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 1789 drivers/net/usb/smsc75xx.c u32 val, link_up; val 1820 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 1826 drivers/net/usb/smsc75xx.c val &= ~(WUCSR_MPEN | WUCSR_WUEN); val 1828 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 1834 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val); val 1840 drivers/net/usb/smsc75xx.c val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN); val 1842 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 1902 drivers/net/usb/smsc75xx.c val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST val 1904 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007); val 1915 drivers/net/usb/smsc75xx.c val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16) val 1917 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003); val 1925 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 1931 drivers/net/usb/smsc75xx.c val |= WUCSR_WUFR; val 1933 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 1940 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 1946 drivers/net/usb/smsc75xx.c val |= WUCSR_WUEN; val 1948 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 1955 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 1961 drivers/net/usb/smsc75xx.c val &= ~WUCSR_WUEN; val 1963 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 1971 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 1977 drivers/net/usb/smsc75xx.c val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN); val 1979 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 1988 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val); val 1995 drivers/net/usb/smsc75xx.c val &= ~PMT_CTL_WUPS; val 1996 drivers/net/usb/smsc75xx.c val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN); val 1998 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 2007 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 2014 drivers/net/usb/smsc75xx.c val |= WUCSR_MPR | WUCSR_MPEN; val 2016 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 2025 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 2031 drivers/net/usb/smsc75xx.c val |= WUCSR_BCAST_FR | WUCSR_BCST_EN; val 2033 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 2042 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 2048 drivers/net/usb/smsc75xx.c val |= WUCSR_WUFR | WUCSR_PFDA_EN; val 2050 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 2058 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val); val 2064 drivers/net/usb/smsc75xx.c val |= MAC_RX_RXEN; val 2066 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val); val 2092 drivers/net/usb/smsc75xx.c u32 val; val 2101 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val); val 2107 drivers/net/usb/smsc75xx.c val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN val 2110 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, WUCSR, val); val 2117 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val); val 2123 drivers/net/usb/smsc75xx.c val &= ~PMT_CTL_WOL_EN; val 2124 drivers/net/usb/smsc75xx.c val |= PMT_CTL_WUPS; val 2126 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 2136 drivers/net/usb/smsc75xx.c ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val); val 2142 drivers/net/usb/smsc75xx.c val |= PMT_CTL_PHY_PWRUP; val 2144 drivers/net/usb/smsc75xx.c ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val); val 159 drivers/net/usb/smsc95xx.c u32 val; val 163 drivers/net/usb/smsc95xx.c ret = __smsc95xx_read_reg(dev, MII_ADDR, &val, in_pm); val 169 drivers/net/usb/smsc95xx.c if (!(val & MII_BUSY_)) val 180 drivers/net/usb/smsc95xx.c u32 val, addr; val 208 drivers/net/usb/smsc95xx.c ret = __smsc95xx_read_reg(dev, MII_DATA, &val, in_pm); val 214 drivers/net/usb/smsc95xx.c ret = (u16)(val & 0xFFFF); val 225 drivers/net/usb/smsc95xx.c u32 val, addr; val 237 drivers/net/usb/smsc95xx.c val = regval; val 238 drivers/net/usb/smsc95xx.c ret = __smsc95xx_write_reg(dev, MII_DATA, val, in_pm); val 290 drivers/net/usb/smsc95xx.c u32 val; val 294 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg(dev, E2P_CMD, &val); val 300 drivers/net/usb/smsc95xx.c if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) val 305 drivers/net/usb/smsc95xx.c if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { val 316 drivers/net/usb/smsc95xx.c u32 val; val 320 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg(dev, E2P_CMD, &val); val 326 drivers/net/usb/smsc95xx.c if (!(val & E2P_CMD_BUSY_)) val 339 drivers/net/usb/smsc95xx.c u32 val; val 350 drivers/net/usb/smsc95xx.c val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); val 351 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg(dev, E2P_CMD, val); val 361 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg(dev, E2P_DATA, &val); val 367 drivers/net/usb/smsc95xx.c data[i] = val & 0xFF; val 377 drivers/net/usb/smsc95xx.c u32 val; val 388 drivers/net/usb/smsc95xx.c val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_; val 389 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg(dev, E2P_CMD, val); val 402 drivers/net/usb/smsc95xx.c val = data[i]; val 403 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg(dev, E2P_DATA, val); val 410 drivers/net/usb/smsc95xx.c val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_); val 411 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg(dev, E2P_CMD, val); val 778 drivers/net/usb/smsc95xx.c u32 val; val 788 drivers/net/usb/smsc95xx.c buf = smsc95xx_read_reg(dev, STRAP_STATUS, &val); val 789 drivers/net/usb/smsc95xx.c if (val & STRAP_STATUS_AMDIX_EN_) val 1251 drivers/net/usb/smsc95xx.c u32 val; val 1292 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg(dev, ID_REV, &val); val 1295 drivers/net/usb/smsc95xx.c val >>= 16; val 1296 drivers/net/usb/smsc95xx.c pdata->chip_id = val; val 1299 drivers/net/usb/smsc95xx.c if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9530_) || val 1300 drivers/net/usb/smsc95xx.c (val == ID_REV_CHIP_ID_89530_) || (val == ID_REV_CHIP_ID_9730_)) val 1304 drivers/net/usb/smsc95xx.c else if (val == ID_REV_CHIP_ID_9512_) val 1385 drivers/net/usb/smsc95xx.c u32 val; val 1388 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); val 1392 drivers/net/usb/smsc95xx.c val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_)); val 1393 drivers/net/usb/smsc95xx.c val |= PM_CTL_SUS_MODE_0; val 1395 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1400 drivers/net/usb/smsc95xx.c val &= ~PM_CTL_WUPS_; val 1401 drivers/net/usb/smsc95xx.c val |= PM_CTL_WUPS_WOL_; val 1405 drivers/net/usb/smsc95xx.c val |= PM_CTL_WUPS_ED_; val 1407 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1412 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); val 1425 drivers/net/usb/smsc95xx.c u32 val; val 1445 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); val 1449 drivers/net/usb/smsc95xx.c val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); val 1450 drivers/net/usb/smsc95xx.c val |= PM_CTL_SUS_MODE_1; val 1452 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1457 drivers/net/usb/smsc95xx.c val &= ~PM_CTL_WUPS_; val 1458 drivers/net/usb/smsc95xx.c val |= (PM_CTL_WUPS_ED_ | PM_CTL_ED_EN_); val 1460 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1472 drivers/net/usb/smsc95xx.c u32 val; val 1475 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); val 1479 drivers/net/usb/smsc95xx.c val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); val 1480 drivers/net/usb/smsc95xx.c val |= PM_CTL_SUS_MODE_2; val 1482 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1494 drivers/net/usb/smsc95xx.c u32 val; val 1497 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, RX_FIFO_INF, &val); val 1501 drivers/net/usb/smsc95xx.c if (val & RX_FIFO_INF_USED_) { val 1506 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); val 1510 drivers/net/usb/smsc95xx.c val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); val 1511 drivers/net/usb/smsc95xx.c val |= PM_CTL_SUS_MODE_3 | PM_CTL_RES_CLR_WKP_STS; val 1513 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1518 drivers/net/usb/smsc95xx.c val &= ~PM_CTL_WUPS_; val 1519 drivers/net/usb/smsc95xx.c val |= PM_CTL_WUPS_WOL_; val 1521 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1581 drivers/net/usb/smsc95xx.c u32 val, link_up; val 1615 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); val 1619 drivers/net/usb/smsc95xx.c val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_); val 1621 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); val 1625 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); val 1629 drivers/net/usb/smsc95xx.c val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_); val 1631 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1756 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); val 1760 drivers/net/usb/smsc95xx.c val |= WUCSR_WUFR_; val 1762 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); val 1769 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); val 1773 drivers/net/usb/smsc95xx.c val |= WUCSR_MPR_; val 1775 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); val 1781 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); val 1787 drivers/net/usb/smsc95xx.c val |= WUCSR_WAKE_EN_; val 1790 drivers/net/usb/smsc95xx.c val &= ~WUCSR_WAKE_EN_; val 1795 drivers/net/usb/smsc95xx.c val |= WUCSR_MPEN_; val 1798 drivers/net/usb/smsc95xx.c val &= ~WUCSR_MPEN_; val 1801 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); val 1806 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); val 1810 drivers/net/usb/smsc95xx.c val |= PM_CTL_WOL_EN_; val 1814 drivers/net/usb/smsc95xx.c val |= PM_CTL_ED_EN_; val 1816 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 1848 drivers/net/usb/smsc95xx.c u32 val; val 1862 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); val 1866 drivers/net/usb/smsc95xx.c val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_); val 1868 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); val 1873 drivers/net/usb/smsc95xx.c ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); val 1877 drivers/net/usb/smsc95xx.c val &= ~PM_CTL_WOL_EN_; val 1878 drivers/net/usb/smsc95xx.c val |= PM_CTL_WUPS_; val 1880 drivers/net/usb/smsc95xx.c ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); val 208 drivers/net/usb/sr9700.c int val) val 211 drivers/net/usb/sr9700.c __le16 res = cpu_to_le16(val); val 219 drivers/net/usb/sr9700.c phy_id, loc, val); val 354 drivers/net/usb/sr9800.c sr_mdio_write(struct net_device *net, int phy_id, int loc, int val) val 357 drivers/net/usb/sr9800.c __le16 res = cpu_to_le16(val); val 361 drivers/net/usb/sr9800.c phy_id, loc, val); val 572 drivers/net/vmxnet3/vmxnet3_drv.c u32 val; val 604 drivers/net/vmxnet3/vmxnet3_drv.c val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; val 628 drivers/net/vmxnet3/vmxnet3_drv.c val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; val 633 drivers/net/vmxnet3/vmxnet3_drv.c | val | rbi->len); val 394 drivers/net/vmxnet3/vmxnet3_int.h #define VMXNET3_WRITE_BAR0_REG(adapter, reg, val) \ val 395 drivers/net/vmxnet3/vmxnet3_int.h writel((val), (adapter)->hw_addr0 + (reg)) val 399 drivers/net/vmxnet3/vmxnet3_int.h #define VMXNET3_WRITE_BAR1_REG(adapter, reg, val) \ val 400 drivers/net/vmxnet3/vmxnet3_int.h writel((val), (adapter)->hw_addr1 + (reg)) val 1120 drivers/net/wan/fsl_ucc_hdlc.c u32 val; val 1122 drivers/net/wan/fsl_ucc_hdlc.c ret = of_property_read_u32_index(np, "cell-index", 0, &val); val 1128 drivers/net/wan/fsl_ucc_hdlc.c ucc_num = val - 1; val 52 drivers/net/wan/hd64572.h #define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */ val 53 drivers/net/wan/hd64572.h #define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */ val 54 drivers/net/wan/hd64572.h #define IR0_M(val, chan) ((val)<<(8*(chan))) /* Int MSCI */ val 359 drivers/net/wan/ixp4xx_hss.c u32 *val = (u32*)msg; val 362 drivers/net/wan/ixp4xx_hss.c port->id, val[0], val[1], npe_name(port->npe)); val 1963 drivers/net/wan/lmc/lmc_main.c u32 val; val 2017 drivers/net/wan/lmc/lmc_main.c val = LMC_CSR_READ(sc, csr_sia_general); val 2018 drivers/net/wan/lmc/lmc_main.c val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE); val 2019 drivers/net/wan/lmc/lmc_main.c LMC_CSR_WRITE(sc, csr_sia_general, val); val 44 drivers/net/wan/lmc/lmc_var.h #define LMC_CSR_WRITE(sc, reg, val) \ val 45 drivers/net/wan/lmc/lmc_var.h outl((val), (sc)->lmc_csrs.reg) val 157 drivers/net/wan/z85230.c static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val) val 161 drivers/net/wan/z85230.c z8530_write_port(c->ctrlio, val); val 173 drivers/net/wan/z85230.c static inline void write_zsctrl(struct z8530_channel *c, u8 val) val 175 drivers/net/wan/z85230.c z8530_write_port(c->ctrlio, val); val 187 drivers/net/wan/z85230.c static inline void write_zsdata(struct z8530_channel *c, u8 val) val 189 drivers/net/wan/z85230.c z8530_write_port(c->dataio, val); val 853 drivers/net/wimax/i2400m/control.c __le32 val; val 879 drivers/net/wimax/i2400m/control.c cmd->tlv.length = cpu_to_le16(sizeof(cmd->val)); val 880 drivers/net/wimax/i2400m/control.c cmd->val = cpu_to_le32(I2400M_WAKEUP_ENABLED); val 23 drivers/net/wimax/i2400m/debugfs.c int debugfs_netdev_queue_stopped_get(void *data, u64 *val) val 26 drivers/net/wimax/i2400m/debugfs.c *val = netif_queue_stopped(i2400m->wimax_dev.net_dev); val 148 drivers/net/wimax/i2400m/debugfs.c int debugfs_i2400m_suspend_set(void *data, u64 val) val 168 drivers/net/wimax/i2400m/debugfs.c int debugfs_i2400m_reset_set(void *data, u64 val) val 172 drivers/net/wimax/i2400m/debugfs.c enum i2400m_reset_type rt = val; val 834 drivers/net/wimax/i2400m/i2400m.h return I2400M_PLD_SIZE_MASK & le32_to_cpu(pld->val); val 840 drivers/net/wimax/i2400m/i2400m.h return (I2400M_PLD_TYPE_MASK & le32_to_cpu(pld->val)) val 848 drivers/net/wimax/i2400m/i2400m.h pld->val = cpu_to_le32( val 34 drivers/net/wimax/i2400m/sysfs.c unsigned val; val 37 drivers/net/wimax/i2400m/sysfs.c if (sscanf(buf, "%u\n", &val) != 1) val 39 drivers/net/wimax/i2400m/sysfs.c if (val != 0 && (val < 100 || val > 300000 || val % 100 != 0)) { val 42 drivers/net/wimax/i2400m/sysfs.c val); val 45 drivers/net/wimax/i2400m/sysfs.c result = i2400m_set_idle_timeout(i2400m, val); val 784 drivers/net/wimax/i2400m/tx.c le32_to_cpu(tx_msg->pld[num_pls].val), val 286 drivers/net/wimax/i2400m/usb-fw.c long val; val 307 drivers/net/wimax/i2400m/usb-fw.c val = wait_for_completion_interruptible_timeout( val 309 drivers/net/wimax/i2400m/usb-fw.c if (val == 0) { val 314 drivers/net/wimax/i2400m/usb-fw.c if (val == -ERESTARTSYS) { val 267 drivers/net/wireless/admtek/adm8211.c u16 val = buf[i] | (buf[i + 1] << 8); val 268 drivers/net/wireless/admtek/adm8211.c adm8211_write_sram(dev, addr + i / 2, val); val 272 drivers/net/wireless/admtek/adm8211.c u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) | val 274 drivers/net/wireless/admtek/adm8211.c adm8211_write_sram(dev, addr + i / 4, val); val 12 drivers/net/wireless/admtek/adm8211.h #define ADM8211_CSR_WRITE(r, val) iowrite32((val), &priv->map->r) val 301 drivers/net/wireless/ath/ar5523/ar5523.c static int ar5523_config(struct ar5523 *ar, u32 reg, u32 val) val 308 drivers/net/wireless/ath/ar5523/ar5523.c *(__be32 *)write.data = cpu_to_be32(val); val 350 drivers/net/wireless/ath/ar5523/ar5523.c static int ar5523_get_capability(struct ar5523 *ar, u32 cap, u32 *val) val 363 drivers/net/wireless/ath/ar5523/ar5523.c *val = be32_to_cpu(val_be); val 992 drivers/net/wireless/ath/ar5523/ar5523.c __be32 val; val 997 drivers/net/wireless/ath/ar5523/ar5523.c val = cpu_to_be32(0); val 998 drivers/net/wireless/ath/ar5523/ar5523.c ar5523_cmd_write(ar, WDCMSG_BIND, &val, sizeof(val), 0); val 1021 drivers/net/wireless/ath/ar5523/ar5523.c &val, sizeof(val), AR5523_CMD_FLAG_MAGIC); val 1027 drivers/net/wireless/ath/ar5523/ar5523.c be32_to_cpu(val)); val 1031 drivers/net/wireless/ath/ar5523/ar5523.c val = cpu_to_be32(TARGET_DEVICE_AWAKE); val 1032 drivers/net/wireless/ath/ar5523/ar5523.c ar5523_cmd_write(ar, WDCMSG_SET_PWR_MODE, &val, sizeof(val), 0); val 127 drivers/net/wireless/ath/ath.h void (*multi_read)(void *, u32 *addr, u32 *val, u16 count); val 128 drivers/net/wireless/ath/ath.h void (*write)(void *, u32 val, u32 reg_offset); val 281 drivers/net/wireless/ath/ath10k/ahb.c u32 val; val 284 drivers/net/wireless/ath/ath10k/ahb.c val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); val 285 drivers/net/wireless/ath/ath10k/ahb.c val |= AHB_AXI_BUS_HALT_REQ; val 286 drivers/net/wireless/ath/ath10k/ahb.c ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); val 291 drivers/net/wireless/ath/ath10k/ahb.c val = ath10k_ahb_tcsr_read32(ar, haltack_reg); val 292 drivers/net/wireless/ath/ath10k/ahb.c if (val & AHB_AXI_BUS_HALT_ACK) val 298 drivers/net/wireless/ath/ath10k/ahb.c if (!(val & AHB_AXI_BUS_HALT_ACK)) { val 299 drivers/net/wireless/ath/ath10k/ahb.c ath10k_err(ar, "failed to halt axi bus: %d\n", val); val 310 drivers/net/wireless/ath/ath10k/ahb.c u32 val; val 343 drivers/net/wireless/ath/ath10k/ahb.c val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); val 344 drivers/net/wireless/ath/ath10k/ahb.c val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; val 345 drivers/net/wireless/ath/ath10k/ahb.c ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); val 375 drivers/net/wireless/ath/ath10k/ahb.c val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); val 376 drivers/net/wireless/ath/ath10k/ahb.c val &= ~AHB_AXI_BUS_HALT_REQ; val 377 drivers/net/wireless/ath/ath10k/ahb.c ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); val 379 drivers/net/wireless/ath/ath10k/ahb.c val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); val 380 drivers/net/wireless/ath/ath10k/ahb.c val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; val 381 drivers/net/wireless/ath/ath10k/ahb.c ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); val 557 drivers/net/wireless/ath/ath10k/ahb.c u32 val; val 573 drivers/net/wireless/ath/ath10k/ahb.c val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV); val 574 drivers/net/wireless/ath/ath10k/ahb.c ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val); val 615 drivers/net/wireless/ath/ath10k/ahb.c u32 addr, val; val 618 drivers/net/wireless/ath/ath10k/ahb.c val = ath10k_ahb_read32(ar, addr); val 619 drivers/net/wireless/ath/ath10k/ahb.c val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK; val 620 drivers/net/wireless/ath/ath10k/ahb.c ath10k_ahb_write32(ar, addr, val); val 694 drivers/net/wireless/ath/ath10k/ahb.c u32 val = 0, region = addr & 0xfffff; val 696 drivers/net/wireless/ath/ath10k/ahb.c val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); val 703 drivers/net/wireless/ath/ath10k/ahb.c val |= region; val 705 drivers/net/wireless/ath/ath10k/ahb.c val |= 0x100000 | region; val 708 drivers/net/wireless/ath/ath10k/ahb.c return val; val 233 drivers/net/wireless/ath/ath10k/bmi.h #define ath10k_bmi_read32(ar, item, val) \ val 242 drivers/net/wireless/ath/ath10k/bmi.h *val = __le32_to_cpu(tmp); \ val 246 drivers/net/wireless/ath/ath10k/bmi.h #define ath10k_bmi_write32(ar, item, val) \ val 250 drivers/net/wireless/ath/ath10k/bmi.h __le32 v = __cpu_to_le32(val); \ val 2522 drivers/net/wireless/ath/ath10k/core.c u32 val; val 2669 drivers/net/wireless/ath/ath10k/core.c val = 0; val 2671 drivers/net/wireless/ath/ath10k/core.c val = WMI_10_4_PEER_STATS; val 2674 drivers/net/wireless/ath/ath10k/core.c val |= WMI_10_4_VDEV_STATS; val 2677 drivers/net/wireless/ath/ath10k/core.c val |= WMI_10_4_BSS_CHANNEL_INFO_64; val 2687 drivers/net/wireless/ath/ath10k/core.c val |= WMI_10_4_COEX_GPIO_SUPPORT; val 2691 drivers/net/wireless/ath/ath10k/core.c val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; val 2695 drivers/net/wireless/ath/ath10k/core.c val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; val 2699 drivers/net/wireless/ath/ath10k/core.c val |= WMI_10_4_TX_DATA_ACK_RSSI; val 2702 drivers/net/wireless/ath/ath10k/core.c val |= WMI_10_4_REPORT_AIRTIME; val 2704 drivers/net/wireless/ath/ath10k/core.c status = ath10k_mac_ext_resource_config(ar, val); val 1967 drivers/net/wireless/ath/ath10k/debug.c bool val; val 1976 drivers/net/wireless/ath/ath10k/debug.c if (strtobool(buf, &val) != 0) val 1987 drivers/net/wireless/ath/ath10k/debug.c if (!(test_bit(ATH10K_FLAG_BTCOEX, &ar->dev_flags) ^ val)) { val 1995 drivers/net/wireless/ath/ath10k/debug.c ret = ath10k_wmi_pdev_set_param(ar, pdev_param, val); val 2006 drivers/net/wireless/ath/ath10k/debug.c if (val) val 2103 drivers/net/wireless/ath/ath10k/debug.c bool val; val 2111 drivers/net/wireless/ath/ath10k/debug.c if (strtobool(buf, &val) != 0) val 2122 drivers/net/wireless/ath/ath10k/debug.c if (!(test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags) ^ val)) { val 2127 drivers/net/wireless/ath/ath10k/debug.c if (val) val 2356 drivers/net/wireless/ath/ath10k/debug.c bool val; val 2358 drivers/net/wireless/ath/ath10k/debug.c if (kstrtobool_from_user(user_buf, count, &val)) val 2361 drivers/net/wireless/ath/ath10k/debug.c if (!val) val 199 drivers/net/wireless/ath/ath10k/mac.c int ath10k_mac_ext_resource_config(struct ath10k *ar, u32 val) val 209 drivers/net/wireless/ath/ath10k/mac.c ret = ath10k_wmi_ext_resource_config(ar, platform_type, val); val 4532 drivers/net/wireless/ath/ath10k/mac.c u32 val; val 4540 drivers/net/wireless/ath/ath10k/mac.c val = ath10k_mac_get_vht_cap_bf_sts(ar); val 4541 drivers/net/wireless/ath/ath10k/mac.c val <<= IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; val 4542 drivers/net/wireless/ath/ath10k/mac.c val &= IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK; val 4544 drivers/net/wireless/ath/ath10k/mac.c vht_cap.cap |= val; val 4549 drivers/net/wireless/ath/ath10k/mac.c val = ath10k_mac_get_vht_cap_bf_sound_dim(ar); val 4550 drivers/net/wireless/ath/ath10k/mac.c val <<= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT; val 4551 drivers/net/wireless/ath/ath10k/mac.c val &= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK; val 4553 drivers/net/wireless/ath/ath10k/mac.c vht_cap.cap |= val; val 73 drivers/net/wireless/ath/ath10k/mac.h int ath10k_mac_ext_resource_config(struct ath10k *ar, u32 val); val 432 drivers/net/wireless/ath/ath10k/pci.c u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + val 435 drivers/net/wireless/ath/ath10k/pci.c return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; val 654 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 657 drivers/net/wireless/ath/ath10k/pci.c if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { val 659 drivers/net/wireless/ath/ath10k/pci.c offset, offset + sizeof(val), ar_pci->mem_len); val 670 drivers/net/wireless/ath/ath10k/pci.c val = ioread32(ar_pci->mem + offset); val 673 drivers/net/wireless/ath/ath10k/pci.c return val; val 695 drivers/net/wireless/ath/ath10k/pci.c void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) val 697 drivers/net/wireless/ath/ath10k/pci.c ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); val 705 drivers/net/wireless/ath/ath10k/pci.c void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) val 707 drivers/net/wireless/ath/ath10k/pci.c ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); val 854 drivers/net/wireless/ath/ath10k/pci.c u32 val = 0, region = addr & 0xfffff; val 856 drivers/net/wireless/ath/ath10k/pci.c val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) val 858 drivers/net/wireless/ath/ath10k/pci.c val |= 0x100000 | region; val 859 drivers/net/wireless/ath/ath10k/pci.c return val; val 869 drivers/net/wireless/ath/ath10k/pci.c u32 val = 0, region = addr & 0xfffff; val 871 drivers/net/wireless/ath/ath10k/pci.c val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) val 873 drivers/net/wireless/ath/ath10k/pci.c val |= ((addr >= 0x100000) ? 0x100000 : 0) | region; val 874 drivers/net/wireless/ath/ath10k/pci.c return val; val 879 drivers/net/wireless/ath/ath10k/pci.c u32 val = 0, region = addr & 0xfffff; val 881 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); val 882 drivers/net/wireless/ath/ath10k/pci.c val |= 0x100000 | region; val 883 drivers/net/wireless/ath/ath10k/pci.c return val; val 1010 drivers/net/wireless/ath/ath10k/pci.c __le32 val = 0; val 1013 drivers/net/wireless/ath/ath10k/pci.c ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); val 1014 drivers/net/wireless/ath/ath10k/pci.c *value = __le32_to_cpu(val); val 1165 drivers/net/wireless/ath/ath10k/pci.c __le32 val = __cpu_to_le32(value); val 1167 drivers/net/wireless/ath/ath10k/pci.c return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); val 1565 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 1570 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + val 1572 drivers/net/wireless/ath/ath10k/pci.c if (val != config) { val 1574 drivers/net/wireless/ath/ath10k/pci.c val, config); val 1877 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 1884 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + val 1886 drivers/net/wireless/ath/ath10k/pci.c val &= ~CORE_CTRL_PCIE_REG_31_MASK; val 1888 drivers/net/wireless/ath/ath10k/pci.c CORE_CTRL_ADDRESS, val); val 1905 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 1912 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + val 1914 drivers/net/wireless/ath/ath10k/pci.c val |= CORE_CTRL_PCIE_REG_31_MASK; val 1916 drivers/net/wireless/ath/ath10k/pci.c CORE_CTRL_ADDRESS, val); val 2263 drivers/net/wireless/ath/ath10k/pci.c u32 addr, val; val 2266 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, addr); val 2267 drivers/net/wireless/ath/ath10k/pci.c val |= CORE_CTRL_CPU_INTR_MASK; val 2268 drivers/net/wireless/ath/ath10k/pci.c ath10k_pci_write32(ar, addr, val); val 2544 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 2546 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); val 2547 drivers/net/wireless/ath/ath10k/pci.c val &= ~FW_IND_EVENT_PENDING; val 2548 drivers/net/wireless/ath/ath10k/pci.c ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); val 2553 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 2555 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); val 2556 drivers/net/wireless/ath/ath10k/pci.c return (val == 0xffffffff); val 2562 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 2564 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); val 2566 drivers/net/wireless/ath/ath10k/pci.c val | SOC_RESET_CONTROL_SI0_RST_MASK); val 2567 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); val 2571 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); val 2573 drivers/net/wireless/ath/ath10k/pci.c val & ~SOC_RESET_CONTROL_SI0_RST_MASK); val 2574 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); val 2581 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 2585 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + val 2588 drivers/net/wireless/ath/ath10k/pci.c val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); val 2593 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 2595 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + val 2599 drivers/net/wireless/ath/ath10k/pci.c val | SOC_RESET_CONTROL_CE_RST_MASK); val 2602 drivers/net/wireless/ath/ath10k/pci.c val & ~SOC_RESET_CONTROL_CE_RST_MASK); val 2607 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 2609 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + val 2613 drivers/net/wireless/ath/ath10k/pci.c val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); val 2673 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 2710 drivers/net/wireless/ath/ath10k/pci.c &val); val 2909 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 2923 drivers/net/wireless/ath/ath10k/pci.c pci_read_config_dword(pdev, 0x40, &val); val 2924 drivers/net/wireless/ath/ath10k/pci.c if ((val & 0x0000ff00) != 0) val 2925 drivers/net/wireless/ath/ath10k/pci.c pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); val 3282 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 3289 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); val 3292 drivers/net/wireless/ath/ath10k/pci.c val); val 3295 drivers/net/wireless/ath/ath10k/pci.c if (val == 0xffffffff) val 3299 drivers/net/wireless/ath/ath10k/pci.c if (val & FW_IND_EVENT_PENDING) val 3302 drivers/net/wireless/ath/ath10k/pci.c if (val & FW_IND_INITIALIZED) val 3315 drivers/net/wireless/ath/ath10k/pci.c if (val == 0xffffffff) { val 3320 drivers/net/wireless/ath/ath10k/pci.c if (val & FW_IND_EVENT_PENDING) { val 3325 drivers/net/wireless/ath/ath10k/pci.c if (!(val & FW_IND_INITIALIZED)) { val 3327 drivers/net/wireless/ath/ath10k/pci.c val); val 3337 drivers/net/wireless/ath/ath10k/pci.c u32 val; val 3348 drivers/net/wireless/ath/ath10k/pci.c val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); val 3349 drivers/net/wireless/ath/ath10k/pci.c val |= 1; val 3350 drivers/net/wireless/ath/ath10k/pci.c ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); val 3360 drivers/net/wireless/ath/ath10k/pci.c val &= ~1; val 3361 drivers/net/wireless/ath/ath10k/pci.c ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); val 208 drivers/net/wireless/ath/ath10k/pci.h void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val); val 209 drivers/net/wireless/ath/ath10k/pci.h void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val); val 84 drivers/net/wireless/ath/ath10k/sdio.c unsigned char val) val 91 drivers/net/wireless/ath/ath10k/sdio.c FIELD_PREP(GENMASK(7, 0), val); val 212 drivers/net/wireless/ath/ath10k/sdio.c static int ath10k_sdio_write32(struct ath10k *ar, u32 addr, u32 val) val 220 drivers/net/wireless/ath/ath10k/sdio.c sdio_writel(func, val, addr, &ret); val 223 drivers/net/wireless/ath/ath10k/sdio.c val, addr, ret); val 228 drivers/net/wireless/ath/ath10k/sdio.c addr, val); val 236 drivers/net/wireless/ath/ath10k/sdio.c static int ath10k_sdio_writesb32(struct ath10k *ar, u32 addr, u32 val) val 247 drivers/net/wireless/ath/ath10k/sdio.c *buf = cpu_to_le32(val); val 254 drivers/net/wireless/ath/ath10k/sdio.c val, addr, ret); val 259 drivers/net/wireless/ath/ath10k/sdio.c addr, val); val 269 drivers/net/wireless/ath/ath10k/sdio.c static int ath10k_sdio_read32(struct ath10k *ar, u32 addr, u32 *val) val 276 drivers/net/wireless/ath/ath10k/sdio.c *val = sdio_readl(func, addr, &ret); val 284 drivers/net/wireless/ath/ath10k/sdio.c addr, *val); val 752 drivers/net/wireless/ath/ath10k/sdio.c u32 val; val 761 drivers/net/wireless/ath/ath10k/sdio.c ret = ath10k_sdio_read32(ar, MBOX_COUNT_DEC_ADDRESS, &val); val 1554 drivers/net/wireless/ath/ath10k/sdio.c u32 val; val 1557 drivers/net/wireless/ath/ath10k/sdio.c ret = ath10k_sdio_read32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, &val); val 1565 drivers/net/wireless/ath/ath10k/sdio.c val &= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF; val 1567 drivers/net/wireless/ath/ath10k/sdio.c val |= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON; val 1569 drivers/net/wireless/ath/ath10k/sdio.c ret = ath10k_sdio_write32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, val); val 1607 drivers/net/wireless/ath/ath10k/sdio.c __le32 *val; val 1610 drivers/net/wireless/ath/ath10k/sdio.c val = kzalloc(sizeof(*val), GFP_KERNEL); val 1611 drivers/net/wireless/ath/ath10k/sdio.c if (!val) val 1614 drivers/net/wireless/ath/ath10k/sdio.c ret = ath10k_sdio_hif_diag_read(ar, address, val, sizeof(*val)); val 1618 drivers/net/wireless/ath/ath10k/sdio.c *value = __le32_to_cpu(*val); val 1621 drivers/net/wireless/ath/ath10k/sdio.c kfree(val); val 1653 drivers/net/wireless/ath/ath10k/sdio.c u32 addr, val; val 1658 drivers/net/wireless/ath/ath10k/sdio.c ret = ath10k_sdio_hif_diag_read32(ar, addr, &val); val 1664 drivers/net/wireless/ath/ath10k/sdio.c if (val & HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK) { val 477 drivers/net/wireless/ath/ath10k/snoc.c u32 val; val 479 drivers/net/wireless/ath/ath10k/snoc.c val = ioread32(ar_snoc->mem + offset); val 481 drivers/net/wireless/ath/ath10k/snoc.c return val; val 386 drivers/net/wireless/ath/ath10k/spectral.c unsigned long val; val 395 drivers/net/wireless/ath/ath10k/spectral.c if (kstrtoul(buf, 0, &val)) val 398 drivers/net/wireless/ath/ath10k/spectral.c if (val > 255) val 402 drivers/net/wireless/ath/ath10k/spectral.c ar->spectral.config.count = val; val 442 drivers/net/wireless/ath/ath10k/spectral.c unsigned long val; val 451 drivers/net/wireless/ath/ath10k/spectral.c if (kstrtoul(buf, 0, &val)) val 454 drivers/net/wireless/ath/ath10k/spectral.c if (val < 64 || val > SPECTRAL_ATH10K_MAX_NUM_BINS) val 457 drivers/net/wireless/ath/ath10k/spectral.c if (!is_power_of_2(val)) val 461 drivers/net/wireless/ath/ath10k/spectral.c ar->spectral.config.fft_size = ilog2(val); val 6450 drivers/net/wireless/ath/ath10k/wmi.c u32 len, val; val 6491 drivers/net/wireless/ath/ath10k/wmi.c val = TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; val 6492 drivers/net/wireless/ath/ath10k/wmi.c config.rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(val); val 6523 drivers/net/wireless/ath/ath10k/wmi.c u32 len, val; val 6559 drivers/net/wireless/ath/ath10k/wmi.c val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; val 6560 drivers/net/wireless/ath/ath10k/wmi.c config.rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(val); val 6588 drivers/net/wireless/ath/ath10k/wmi.c u32 len, val, features; val 6632 drivers/net/wireless/ath/ath10k/wmi.c val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; val 6633 drivers/net/wireless/ath/ath10k/wmi.c config.rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(val); val 8491 drivers/net/wireless/ath/ath10k/wmi.c u32 val; val 8511 drivers/net/wireless/ath/ath10k/wmi.c val = vdev->tx_ftm_suc; val 8512 drivers/net/wireless/ath/ath10k/wmi.c if (val & WMI_VDEV_STATS_FTM_COUNT_VALID) val 8515 drivers/net/wireless/ath/ath10k/wmi.c MS(val, WMI_VDEV_STATS_FTM_COUNT)); val 8516 drivers/net/wireless/ath/ath10k/wmi.c val = vdev->tx_ftm_suc_retry; val 8517 drivers/net/wireless/ath/ath10k/wmi.c if (val & WMI_VDEV_STATS_FTM_COUNT_VALID) val 8520 drivers/net/wireless/ath/ath10k/wmi.c MS(val, WMI_VDEV_STATS_FTM_COUNT)); val 8521 drivers/net/wireless/ath/ath10k/wmi.c val = vdev->tx_ftm_fail; val 8522 drivers/net/wireless/ath/ath10k/wmi.c if (val & WMI_VDEV_STATS_FTM_COUNT_VALID) val 8525 drivers/net/wireless/ath/ath10k/wmi.c MS(val, WMI_VDEV_STATS_FTM_COUNT)); val 8526 drivers/net/wireless/ath/ath10k/wmi.c val = vdev->rx_ftmr_cnt; val 8527 drivers/net/wireless/ath/ath10k/wmi.c if (val & WMI_VDEV_STATS_FTM_COUNT_VALID) val 8530 drivers/net/wireless/ath/ath10k/wmi.c MS(val, WMI_VDEV_STATS_FTM_COUNT)); val 8531 drivers/net/wireless/ath/ath10k/wmi.c val = vdev->rx_ftmr_dup_cnt; val 8532 drivers/net/wireless/ath/ath10k/wmi.c if (val & WMI_VDEV_STATS_FTM_COUNT_VALID) val 8535 drivers/net/wireless/ath/ath10k/wmi.c MS(val, WMI_VDEV_STATS_FTM_COUNT)); val 8536 drivers/net/wireless/ath/ath10k/wmi.c val = vdev->rx_iftmr_cnt; val 8537 drivers/net/wireless/ath/ath10k/wmi.c if (val & WMI_VDEV_STATS_FTM_COUNT_VALID) val 8540 drivers/net/wireless/ath/ath10k/wmi.c MS(val, WMI_VDEV_STATS_FTM_COUNT)); val 8541 drivers/net/wireless/ath/ath10k/wmi.c val = vdev->rx_iftmr_dup_cnt; val 8542 drivers/net/wireless/ath/ath10k/wmi.c if (val & WMI_VDEV_STATS_FTM_COUNT_VALID) val 8545 drivers/net/wireless/ath/ath10k/wmi.c MS(val, WMI_VDEV_STATS_FTM_COUNT)); val 75 drivers/net/wireless/ath/ath10k/wmi.h static inline a_sle32 a_cpu_to_sle32(s32 val) val 77 drivers/net/wireless/ath/ath10k/wmi.h return (__force a_sle32)cpu_to_le32(val); val 80 drivers/net/wireless/ath/ath10k/wmi.h static inline s32 a_sle32_to_cpu(a_sle32 val) val 82 drivers/net/wireless/ath/ath10k/wmi.h return le32_to_cpu((__force __le32)val); val 113 drivers/net/wireless/ath/ath5k/ani.c static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; val 115 drivers/net/wireless/ath/ath5k/ani.c if (level < 0 || level >= ARRAY_SIZE(val) || val 123 drivers/net/wireless/ath/ath5k/ani.c AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]); val 137 drivers/net/wireless/ath/ath5k/ani.c static const int val[] = { 0, 4, 8 }; val 139 drivers/net/wireless/ath/ath5k/ani.c if (level < 0 || level >= ARRAY_SIZE(val)) { val 145 drivers/net/wireless/ath/ath5k/ani.c AR5K_PHY_SIG_FIRSTEP, val[level]); val 199 drivers/net/wireless/ath/ath5k/ani.c static const int val[] = { 8, 6 }; val 201 drivers/net/wireless/ath/ath5k/ani.c AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]); val 1497 drivers/net/wireless/ath/ath5k/ath5k.h int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, val 1592 drivers/net/wireless/ath/ath5k/ath5k.h int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); val 1671 drivers/net/wireless/ath/ath5k/ath5k.h static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) val 1673 drivers/net/wireless/ath/ath5k/ath5k.h iowrite32(val, ath5k_ahb_reg(ah, reg)); val 1683 drivers/net/wireless/ath/ath5k/ath5k.h static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) val 1685 drivers/net/wireless/ath/ath5k/ath5k.h iowrite32(val, ah->iobase + reg); val 1706 drivers/net/wireless/ath/ath5k/ath5k.h static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) val 1711 drivers/net/wireless/ath/ath5k/ath5k.h bit = (val >> i) & 1; val 212 drivers/net/wireless/ath/ath5k/base.c ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) val 221 drivers/net/wireless/ath/ath5k/base.c if ((val & 0xf0) == srev_names[i].sr_val) val 224 drivers/net/wireless/ath/ath5k/base.c if ((val & 0xff) == srev_names[i].sr_val) { val 238 drivers/net/wireless/ath/ath5k/base.c static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) val 241 drivers/net/wireless/ath/ath5k/base.c ath5k_hw_reg_write(ah, val, reg_offset); val 110 drivers/net/wireless/ath/ath5k/base.h const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val); val 912 drivers/net/wireless/ath/ath5k/debug.c u16 val, *buf; val 916 drivers/net/wireless/ath/ath5k/debug.c res = ath5k_hw_nvram_read(ah, AR5K_EEPROM_SIZE_UPPER, &val); val 920 drivers/net/wireless/ath/ath5k/debug.c if (val == 0) { val 923 drivers/net/wireless/ath/ath5k/debug.c eesize = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << val 925 drivers/net/wireless/ath/ath5k/debug.c ath5k_hw_nvram_read(ah, AR5K_EEPROM_SIZE_LOWER, &val); val 926 drivers/net/wireless/ath/ath5k/debug.c eesize = eesize | val; val 941 drivers/net/wireless/ath/ath5k/debug.c if (!ath5k_hw_nvram_read(ah, i, &val)) { val 945 drivers/net/wireless/ath/ath5k/debug.c buf[i] = val; val 43 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 50 drivers/net/wireless/ath/ath5k/eeprom.c val = (5 * bin) + 4800; val 52 drivers/net/wireless/ath/ath5k/eeprom.c val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : val 56 drivers/net/wireless/ath/ath5k/eeprom.c val = bin + 2300; val 58 drivers/net/wireless/ath/ath5k/eeprom.c val = bin + 2400; val 61 drivers/net/wireless/ath/ath5k/eeprom.c return val; val 76 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 96 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val); val 97 drivers/net/wireless/ath/ath5k/eeprom.c if (val) { val 98 drivers/net/wireless/ath/ath5k/eeprom.c eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << val 100 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val); val 101 drivers/net/wireless/ath/ath5k/eeprom.c eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE; val 119 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); val 120 drivers/net/wireless/ath/ath5k/eeprom.c cksum ^= val; val 152 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); val 153 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; val 154 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; val 156 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); val 157 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; val 158 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; val 161 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val); val 163 drivers/net/wireless/ath/ath5k/eeprom.c if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val) val 168 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val); val 169 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL); val 170 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false; val 178 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val); val 179 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ? val 194 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 197 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 198 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; val 199 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f; val 200 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; val 202 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 203 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; val 204 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; val 205 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] = val & 0x3f; val 207 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 208 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; val 209 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; val 210 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; val 212 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 213 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; val 214 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; val 215 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; val 216 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; val 218 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 219 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; val 220 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; val 221 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ant_control[mode][i++] = val & 0x3f; val 254 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 257 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 258 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); val 261 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[mode][3] = (val >> 5) & 0x7; val 262 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_db[mode][3] = (val >> 2) & 0x7; val 263 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[mode][2] = (val << 1) & 0x7; val 265 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 266 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[mode][2] |= (val >> 15) & 0x1; val 267 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_db[mode][2] = (val >> 12) & 0x7; val 268 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[mode][1] = (val >> 9) & 0x7; val 269 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_db[mode][1] = (val >> 6) & 0x7; val 270 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[mode][0] = (val >> 3) & 0x7; val 271 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_db[mode][0] = val & 0x7; val 275 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[mode][1] = (val >> 4) & 0x7; val 276 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_db[mode][1] = val & 0x7; val 280 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 281 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; val 282 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_thr_62[mode] = val & 0xff; val 287 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 288 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; val 289 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; val 291 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 292 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; val 294 drivers/net/wireless/ath/ath5k/eeprom.c if ((val & 0xff) & 0x80) val 295 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); val 297 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_noise_floor_thr[mode] = val & 0xff; val 303 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 304 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; val 305 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_x_gain[mode] = (val >> 1) & 0xf; val 306 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_xpd[mode] = val & 0x1; val 310 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; val 313 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 314 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_false_detect[mode] = (val >> 6) & 0x7f; val 317 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_xr_power[mode] = val & 0x3f; val 320 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ob[mode][0] = val & 0x7; val 321 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_db[mode][0] = (val >> 3) & 0x7; val 329 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_i_gain[mode] = (val >> 13) & 0x7; val 331 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 332 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_i_gain[mode] |= (val << 3) & 0x38; val 335 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; val 337 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; val 343 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_i_cal[mode] = (val >> 8) & 0x3f; val 344 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_q_cal[mode] = (val >> 3) & 0x1f; val 358 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 359 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_margin_tx_rx[mode] = val & 0x3f; val 362 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 365 drivers/net/wireless/ath/ath5k/eeprom.c ath5k_eeprom_bin2freq(ee, val & 0xff, mode); val 370 drivers/net/wireless/ath/ath5k/eeprom.c ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); val 374 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 376 drivers/net/wireless/ath/ath5k/eeprom.c ath5k_eeprom_bin2freq(ee, val & 0xff, mode); val 381 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; val 384 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 387 drivers/net/wireless/ath/ath5k/eeprom.c ath5k_eeprom_bin2freq(ee, val & 0xff, mode); val 392 drivers/net/wireless/ath/ath5k/eeprom.c ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); val 396 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 397 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_turbo_max_power[mode] = val & 0x7f; val 398 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_xr_power[mode] = (val >> 7) & 0x3f; val 400 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 402 drivers/net/wireless/ath/ath5k/eeprom.c ath5k_eeprom_bin2freq(ee, val & 0xff, mode); val 407 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; val 409 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 410 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_i_cal[mode] = (val >> 5) & 0x3f; val 411 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_q_cal[mode] = val & 0x1f; val 414 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 415 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_cck_ofdm_gain_delta = val & 0xff; val 428 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f; val 430 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7; val 431 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 432 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3; val 433 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f; val 435 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f; val 436 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 437 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7; val 438 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff; val 441 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_pd_gain_overlap = (val >> 9) & 0xf; val 444 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f; val 446 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7; val 447 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 448 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1; val 449 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f; val 451 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f; val 452 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 453 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5; val 454 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff; val 517 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 521 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(o++, val); val 523 drivers/net/wireless/ath/ath5k/eeprom.c freq1 = val & 0xff; val 531 drivers/net/wireless/ath/ath5k/eeprom.c freq2 = (val >> 8) & 0xff; val 553 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 563 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 564 drivers/net/wireless/ath/ath5k/eeprom.c pcal[0].freq = (val >> 9) & mask; val 565 drivers/net/wireless/ath/ath5k/eeprom.c pcal[1].freq = (val >> 2) & mask; val 566 drivers/net/wireless/ath/ath5k/eeprom.c pcal[2].freq = (val << 5) & mask; val 568 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 569 drivers/net/wireless/ath/ath5k/eeprom.c pcal[2].freq |= (val >> 11) & 0x1f; val 570 drivers/net/wireless/ath/ath5k/eeprom.c pcal[3].freq = (val >> 4) & mask; val 571 drivers/net/wireless/ath/ath5k/eeprom.c pcal[4].freq = (val << 3) & mask; val 573 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 574 drivers/net/wireless/ath/ath5k/eeprom.c pcal[4].freq |= (val >> 13) & 0x7; val 575 drivers/net/wireless/ath/ath5k/eeprom.c pcal[5].freq = (val >> 6) & mask; val 576 drivers/net/wireless/ath/ath5k/eeprom.c pcal[6].freq = (val << 1) & mask; val 578 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 579 drivers/net/wireless/ath/ath5k/eeprom.c pcal[6].freq |= (val >> 15) & 0x1; val 580 drivers/net/wireless/ath/ath5k/eeprom.c pcal[7].freq = (val >> 8) & mask; val 581 drivers/net/wireless/ath/ath5k/eeprom.c pcal[8].freq = (val >> 1) & mask; val 582 drivers/net/wireless/ath/ath5k/eeprom.c pcal[9].freq = (val << 6) & mask; val 584 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 585 drivers/net/wireless/ath/ath5k/eeprom.c pcal[9].freq |= (val >> 10) & 0x3f; val 799 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 850 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 851 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M); val 852 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M); val 853 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M); val 855 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 856 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[0] |= ((val >> 14) & 0x3); val 857 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M); val 858 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M); val 859 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M); val 861 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 862 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[3] |= ((val >> 12) & 0xf); val 863 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M); val 864 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M); val 866 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 867 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M); val 868 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M); val 869 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M); val 871 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 872 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[8] |= ((val >> 14) & 0x3); val 873 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M); val 874 drivers/net/wireless/ath/ath5k/eeprom.c cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M); val 1024 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 1082 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1083 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff); val 1084 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff); val 1090 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1091 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pcdac_x0[1] = (val & 0x1f); val 1092 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f); val 1093 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f); val 1098 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1099 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff); val 1100 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff); val 1102 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1103 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pwr_x3[2] = (val & 0xff); val 1113 drivers/net/wireless/ath/ath5k/eeprom.c chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f); val 1119 drivers/net/wireless/ath/ath5k/eeprom.c gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff); val 1287 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 1343 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1344 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr_i[0] = val & 0x1f; val 1345 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac_i[0] = (val >> 5) & 0x7f; val 1346 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[0][0] = (val >> 12) & 0xf; val 1348 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1349 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[0][0] = val & 0x3f; val 1350 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[0][1] = (val >> 6) & 0xf; val 1351 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[0][1] = (val >> 10) & 0x3f; val 1353 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1354 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[0][2] = val & 0xf; val 1355 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[0][2] = (val >> 4) & 0x3f; val 1366 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr_i[1] = (val >> 10) & 0x1f; val 1368 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac_i[1] = (val >> 15) & 0x1; val 1369 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1370 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac_i[1] |= (val & 0x3F) << 1; val 1372 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[1][0] = (val >> 6) & 0xf; val 1373 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[1][0] = (val >> 10) & 0x3f; val 1375 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1376 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[1][1] = val & 0xf; val 1377 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[1][1] = (val >> 4) & 0x3f; val 1378 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[1][2] = (val >> 10) & 0xf; val 1380 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[1][2] = (val >> 14) & 0x3; val 1381 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1382 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[1][2] |= (val & 0xF) << 2; val 1391 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[0][3] = (val >> 10) & 0xf; val 1393 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[0][3] = (val >> 14) & 0x3; val 1394 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1395 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[0][3] |= (val & 0xF) << 2; val 1403 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr_i[2] = (val >> 4) & 0x1f; val 1404 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac_i[2] = (val >> 9) & 0x7f; val 1406 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1407 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[2][0] = (val >> 0) & 0xf; val 1408 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[2][0] = (val >> 4) & 0x3f; val 1409 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[2][1] = (val >> 10) & 0xf; val 1411 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[2][1] = (val >> 14) & 0x3; val 1412 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1413 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[2][1] |= (val & 0xF) << 2; val 1415 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[2][2] = (val >> 4) & 0xf; val 1416 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[2][2] = (val >> 8) & 0x3f; val 1421 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[1][3] = (val >> 4) & 0xf; val 1422 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[1][3] = (val >> 8) & 0x3f; val 1426 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr_i[3] = (val >> 14) & 0x3; val 1427 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1428 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2; val 1430 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac_i[3] = (val >> 3) & 0x7f; val 1431 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[3][0] = (val >> 10) & 0xf; val 1432 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[3][0] = (val >> 14) & 0x3; val 1434 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1435 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[3][0] |= (val & 0xF) << 2; val 1436 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[3][1] = (val >> 4) & 0xf; val 1437 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[3][1] = (val >> 8) & 0x3f; val 1439 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[3][2] = (val >> 14) & 0x3; val 1440 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1441 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2; val 1443 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[3][2] = (val >> 2) & 0x3f; val 1444 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[3][3] = (val >> 8) & 0xf; val 1446 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[3][3] = (val >> 12) & 0xF; val 1447 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1448 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4; val 1450 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[2][3] = (val >> 14) & 0x3; val 1451 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1452 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2; val 1454 drivers/net/wireless/ath/ath5k/eeprom.c pcinfo->pddac[2][3] = (val >> 2) & 0x3f; val 1476 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 1504 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1506 drivers/net/wireless/ath/ath5k/eeprom.c ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode); val 1508 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f); val 1509 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f; val 1511 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1514 drivers/net/wireless/ath/ath5k/eeprom.c val == 0) { val 1519 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7); val 1520 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f); val 1521 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f); val 1525 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1527 drivers/net/wireless/ath/ath5k/eeprom.c ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); val 1529 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f); val 1530 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f; val 1532 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1535 drivers/net/wireless/ath/ath5k/eeprom.c val == 0) { val 1540 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf; val 1541 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f); val 1542 drivers/net/wireless/ath/ath5k/eeprom.c rate_pcal_info[i].target_power_54 = (val & 0x3f); val 1606 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 1613 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1614 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ctl[i] = (val >> 8) & 0xff; val 1615 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_ctl[i + 1] = val & 0xff; val 1646 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1647 drivers/net/wireless/ath/ath5k/eeprom.c rep[j].freq = (val >> 8) & fmask; val 1648 drivers/net/wireless/ath/ath5k/eeprom.c rep[j + 1].freq = val & fmask; val 1651 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1652 drivers/net/wireless/ath/ath5k/eeprom.c rep[j].edge = (val >> 8) & pmask; val 1653 drivers/net/wireless/ath/ath5k/eeprom.c rep[j].flag = (val >> 14) & 1; val 1654 drivers/net/wireless/ath/ath5k/eeprom.c rep[j + 1].edge = val & pmask; val 1655 drivers/net/wireless/ath/ath5k/eeprom.c rep[j + 1].flag = (val >> 6) & 1; val 1658 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1659 drivers/net/wireless/ath/ath5k/eeprom.c rep[0].freq = (val >> 9) & fmask; val 1660 drivers/net/wireless/ath/ath5k/eeprom.c rep[1].freq = (val >> 2) & fmask; val 1661 drivers/net/wireless/ath/ath5k/eeprom.c rep[2].freq = (val << 5) & fmask; val 1663 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1664 drivers/net/wireless/ath/ath5k/eeprom.c rep[2].freq |= (val >> 11) & 0x1f; val 1665 drivers/net/wireless/ath/ath5k/eeprom.c rep[3].freq = (val >> 4) & fmask; val 1666 drivers/net/wireless/ath/ath5k/eeprom.c rep[4].freq = (val << 3) & fmask; val 1668 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1669 drivers/net/wireless/ath/ath5k/eeprom.c rep[4].freq |= (val >> 13) & 0x7; val 1670 drivers/net/wireless/ath/ath5k/eeprom.c rep[5].freq = (val >> 6) & fmask; val 1671 drivers/net/wireless/ath/ath5k/eeprom.c rep[6].freq = (val << 1) & fmask; val 1673 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1674 drivers/net/wireless/ath/ath5k/eeprom.c rep[6].freq |= (val >> 15) & 0x1; val 1675 drivers/net/wireless/ath/ath5k/eeprom.c rep[7].freq = (val >> 8) & fmask; val 1677 drivers/net/wireless/ath/ath5k/eeprom.c rep[0].edge = (val >> 2) & pmask; val 1678 drivers/net/wireless/ath/ath5k/eeprom.c rep[1].edge = (val << 4) & pmask; val 1680 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1681 drivers/net/wireless/ath/ath5k/eeprom.c rep[1].edge |= (val >> 12) & 0xf; val 1682 drivers/net/wireless/ath/ath5k/eeprom.c rep[2].edge = (val >> 6) & pmask; val 1683 drivers/net/wireless/ath/ath5k/eeprom.c rep[3].edge = val & pmask; val 1685 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1686 drivers/net/wireless/ath/ath5k/eeprom.c rep[4].edge = (val >> 10) & pmask; val 1687 drivers/net/wireless/ath/ath5k/eeprom.c rep[5].edge = (val >> 4) & pmask; val 1688 drivers/net/wireless/ath/ath5k/eeprom.c rep[6].edge = (val << 2) & pmask; val 1690 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset++, val); val 1691 drivers/net/wireless/ath/ath5k/eeprom.c rep[6].edge |= (val >> 14) & 0x3; val 1692 drivers/net/wireless/ath/ath5k/eeprom.c rep[7].edge = (val >> 8) & pmask; val 1709 drivers/net/wireless/ath/ath5k/eeprom.c u16 val; val 1724 drivers/net/wireless/ath/ath5k/eeprom.c AR5K_EEPROM_READ(offset, val); val 1725 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_spur_chans[i][0] = val; val 1727 drivers/net/wireless/ath/ath5k/eeprom.c val); val 1728 drivers/net/wireless/ath/ath5k/eeprom.c ee->ee_spur_chans[i][1] = val; val 159 drivers/net/wireless/ath/ath5k/gpio.c ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val) val 170 drivers/net/wireless/ath/ath5k/gpio.c data |= (val & 1) << gpio; val 322 drivers/net/wireless/ath/ath5k/mac80211-ops.c u32 mfilt[2], val; val 331 drivers/net/wireless/ath/ath5k/mac80211-ops.c val = get_unaligned_le32(ha->addr + 0); val 332 drivers/net/wireless/ath/ath5k/mac80211-ops.c pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; val 333 drivers/net/wireless/ath/ath5k/mac80211-ops.c val = get_unaligned_le32(ha->addr + 3); val 334 drivers/net/wireless/ath/ath5k/mac80211-ops.c pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; val 623 drivers/net/wireless/ath/ath5k/pcu.c u32 val; val 625 drivers/net/wireless/ath/ath5k/pcu.c val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; val 633 drivers/net/wireless/ath/ath5k/pcu.c ath5k_hw_reg_write(ah, val, AR5K_BEACON); val 634 drivers/net/wireless/ath/ath5k/pcu.c ath5k_hw_reg_write(ah, val, AR5K_BEACON); val 1004 drivers/net/wireless/ath/ath5k/pcu.c u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; val 1006 drivers/net/wireless/ath/ath5k/pcu.c AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); val 1008 drivers/net/wireless/ath/ath5k/pcu.c AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); val 194 drivers/net/wireless/ath/ath5k/phy.c u32 val, u8 reg_id, bool set) val 241 drivers/net/wireless/ath/ath5k/phy.c data = ath5k_hw_bitswap(val, num_bits); val 1525 drivers/net/wireless/ath/ath5k/phy.c s32 val; val 1527 drivers/net/wireless/ath/ath5k/phy.c val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); val 1528 drivers/net/wireless/ath/ath5k/phy.c return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); val 1597 drivers/net/wireless/ath/ath5k/phy.c u32 val; val 1630 drivers/net/wireless/ath/ath5k/phy.c val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; val 1631 drivers/net/wireless/ath/ath5k/phy.c val |= (nf * 2) & AR5K_PHY_NF_M; val 1632 drivers/net/wireless/ath/ath5k/phy.c ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); val 1646 drivers/net/wireless/ath/ath5k/phy.c val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); val 1647 drivers/net/wireless/ath/ath5k/phy.c ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); val 3246 drivers/net/wireless/ath/ath5k/phy.c u32 val = get_unaligned_le32(&pdadc_out[4 * i]); val 3247 drivers/net/wireless/ath/ath5k/phy.c ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); val 67 drivers/net/wireless/ath/ath5k/reset.c ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, val 77 drivers/net/wireless/ath/ath5k/reset.c else if ((data & flag) == val) val 397 drivers/net/wireless/ath/ath5k/reset.c ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) val 400 drivers/net/wireless/ath/ath5k/reset.c u32 mask = val ? val : ~0U; val 408 drivers/net/wireless/ath/ath5k/reset.c ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL); val 414 drivers/net/wireless/ath/ath5k/reset.c val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA val 419 drivers/net/wireless/ath/ath5k/reset.c val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; val 423 drivers/net/wireless/ath/ath5k/reset.c ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false); val 430 drivers/net/wireless/ath/ath5k/reset.c if ((val & AR5K_RESET_CTL_PCU) == 0) val 451 drivers/net/wireless/ath/ath5k/reset.c u32 val = 0; val 457 drivers/net/wireless/ath/ath5k/reset.c val |= AR5K_AR2315_RESET_WMAC; val 459 drivers/net/wireless/ath/ath5k/reset.c val |= AR5K_AR2315_RESET_BB_WARM; val 464 drivers/net/wireless/ath/ath5k/reset.c val |= AR5K_AR5312_RESET_WMAC0; val 466 drivers/net/wireless/ath/ath5k/reset.c val |= AR5K_AR5312_RESET_BB0_COLD | val 470 drivers/net/wireless/ath/ath5k/reset.c val |= AR5K_AR5312_RESET_WMAC1; val 472 drivers/net/wireless/ath/ath5k/reset.c val |= AR5K_AR5312_RESET_BB1_COLD | val 479 drivers/net/wireless/ath/ath5k/reset.c iowrite32(regval | val, reg); val 484 drivers/net/wireless/ath/ath5k/reset.c iowrite32(regval & ~val, reg); val 26 drivers/net/wireless/ath/ath5k/sysfs.c int val, ret; \ val 28 drivers/net/wireless/ath/ath5k/sysfs.c ret = kstrtoint(buf, 10, &val); \ val 31 drivers/net/wireless/ath/ath5k/sysfs.c set(ah, val); \ val 226 drivers/net/wireless/ath/ath6kl/bmi.h #define ath6kl_bmi_write_hi32(ar, item, val) \ val 232 drivers/net/wireless/ath/ath6kl/bmi.h v = cpu_to_le32(val); \ val 236 drivers/net/wireless/ath/ath6kl/bmi.h #define ath6kl_bmi_read_hi32(ar, item, val) \ val 238 drivers/net/wireless/ath/ath6kl/bmi.h u32 addr, *check_type = val; \ val 242 drivers/net/wireless/ath/ath6kl/bmi.h (void) (check_type == val); \ val 246 drivers/net/wireless/ath/ath6kl/bmi.h *val = le32_to_cpu(tmp); \ val 843 drivers/net/wireless/ath/ath6kl/debug.c u32 val; val 846 drivers/net/wireless/ath/ath6kl/debug.c ret = kstrtou32_from_user(user_buf, count, 0, &val); val 849 drivers/net/wireless/ath/ath6kl/debug.c if (val == 0) { val 1323 drivers/net/wireless/ath/ath6kl/debug.c u8 val; val 1325 drivers/net/wireless/ath/ath6kl/debug.c ret = kstrtou8_from_user(user_buf, count, 0, &val); val 1329 drivers/net/wireless/ath/ath6kl/debug.c ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, 0, val); val 1368 drivers/net/wireless/ath/ath6kl/debug.c u8 val; val 1370 drivers/net/wireless/ath/ath6kl/debug.c ret = kstrtou8_from_user(user_buf, count, 0, &val); val 1374 drivers/net/wireless/ath/ath6kl/debug.c ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, 0, val); val 961 drivers/net/wireless/ath/ath6kl/init.c __le32 *val; val 1072 drivers/net/wireless/ath/ath6kl/init.c val = (__le32 *) data; val 1073 drivers/net/wireless/ath/ath6kl/init.c ar->hw.reserved_ram_size = le32_to_cpup(val); val 1100 drivers/net/wireless/ath/ath6kl/init.c if (ie_len != sizeof(*val)) val 1103 drivers/net/wireless/ath/ath6kl/init.c val = (__le32 *) data; val 1104 drivers/net/wireless/ath/ath6kl/init.c ar->hw.dataset_patch_addr = le32_to_cpup(val); val 1111 drivers/net/wireless/ath/ath6kl/init.c if (ie_len != sizeof(*val)) val 1114 drivers/net/wireless/ath/ath6kl/init.c val = (__le32 *) data; val 1115 drivers/net/wireless/ath/ath6kl/init.c ar->hw.board_addr = le32_to_cpup(val); val 1122 drivers/net/wireless/ath/ath6kl/init.c if (ie_len != sizeof(*val)) val 1125 drivers/net/wireless/ath/ath6kl/init.c val = (__le32 *) data; val 1126 drivers/net/wireless/ath/ath6kl/init.c ar->vif_max = min_t(unsigned int, le32_to_cpup(val), val 814 drivers/net/wireless/ath/ath6kl/main.c static void ath6kl_add_le32(__le32 *var, __le32 val) val 816 drivers/net/wireless/ath/ath6kl/main.c *var = cpu_to_le32(le32_to_cpu(*var) + le32_to_cpu(val)); val 123 drivers/net/wireless/ath/ath6kl/sdio.c unsigned char val) val 133 drivers/net/wireless/ath/ath6kl/sdio.c (val & 0xFF); val 1046 drivers/net/wireless/ath/ath6kl/sdio.c u32 val = (__force u32) data; val 1050 drivers/net/wireless/ath/ath6kl/sdio.c (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC); val 66 drivers/net/wireless/ath/ath6kl/wmi.h static inline a_sle32 a_cpu_to_sle32(s32 val) val 68 drivers/net/wireless/ath/ath6kl/wmi.h return (__force a_sle32) cpu_to_le32(val); val 71 drivers/net/wireless/ath/ath6kl/wmi.h static inline s32 a_sle32_to_cpu(a_sle32 val) val 73 drivers/net/wireless/ath/ath6kl/wmi.h return le32_to_cpu((__force __le32) val); val 76 drivers/net/wireless/ath/ath6kl/wmi.h static inline a_sle16 a_cpu_to_sle16(s16 val) val 78 drivers/net/wireless/ath/ath6kl/wmi.h return (__force a_sle16) cpu_to_le16(val); val 81 drivers/net/wireless/ath/ath6kl/wmi.h static inline s16 a_sle16_to_cpu(a_sle16 val) val 83 drivers/net/wireless/ath/ath6kl/wmi.h return le16_to_cpu((__force __le16) val); val 618 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 val; val 635 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PCU_MISC_MODE2) & val 639 drivers/net/wireless/ath/ath9k/ar5008_phy.c val &= ~AR_PCU_MISC_MODE2_HWWAR1; val 642 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = val & (~AR_PCU_MISC_MODE2_HWWAR2); val 644 drivers/net/wireless/ath/ath9k/ar5008_phy.c val |= AR_PCU_MISC_MODE2_CFP_IGNORE; val 646 drivers/net/wireless/ath/ath9k/ar5008_phy.c REG_WRITE(ah, AR_PCU_MISC_MODE2, val); val 662 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); val 663 drivers/net/wireless/ath/ath9k/ar5008_phy.c val &= ~AR_PHY_RIFS_INIT_DELAY; val 664 drivers/net/wireless/ath/ath9k/ar5008_phy.c REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); val 735 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 val = INI_RA(&ah->iniModes, i, modesIndex); val 738 drivers/net/wireless/ath/ath9k/ar5008_phy.c val &= ~AR_AN_TOP2_PWDCLKIND; val 740 drivers/net/wireless/ath/ath9k/ar5008_phy.c REG_WRITE(ah, reg, val); val 770 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 val = INI_RA(&ah->iniCommon, i, 1); val 772 drivers/net/wireless/ath/ath9k/ar5008_phy.c REG_WRITE(ah, reg, val); val 1155 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 val; val 1165 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PHY_SFCORR); val 1166 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); val 1167 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); val 1168 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); val 1170 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PHY_SFCORR_LOW); val 1171 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); val 1172 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); val 1173 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); val 1175 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PHY_SFCORR_EXT); val 1176 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); val 1177 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); val 1178 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); val 1179 drivers/net/wireless/ath/ath9k/ar5008_phy.c iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); val 264 drivers/net/wireless/ath/ath9k/ar9002_calib.c u32 qGainMismatch, iGainMismatch, val, i; val 299 drivers/net/wireless/ath/ath9k/ar9002_calib.c val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); val 300 drivers/net/wireless/ath/ath9k/ar9002_calib.c val &= 0xfffff000; val 301 drivers/net/wireless/ath/ath9k/ar9002_calib.c val |= (qGainMismatch) | (iGainMismatch << 6); val 302 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); val 317 drivers/net/wireless/ath/ath9k/ar9002_calib.c u32 iOddMeasOffset, iEvenMeasOffset, val, i; val 354 drivers/net/wireless/ath/ath9k/ar9002_calib.c val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); val 355 drivers/net/wireless/ath/ath9k/ar9002_calib.c val &= 0xc0000fff; val 356 drivers/net/wireless/ath/ath9k/ar9002_calib.c val |= (qDcMismatch << 12) | (iDcMismatch << 21); val 357 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); val 206 drivers/net/wireless/ath/ath9k/ar9002_hw.c u32 val; val 254 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = REG_READ(ah, AR_WA); val 264 drivers/net/wireless/ath/ath9k/ar9002_hw.c val |= AR_WA_D3_L1_DISABLE; val 268 drivers/net/wireless/ath/ath9k/ar9002_hw.c val |= AR_WA_D3_L1_DISABLE; val 271 drivers/net/wireless/ath/ath9k/ar9002_hw.c val |= AR_WA_D3_L1_DISABLE; val 280 drivers/net/wireless/ath/ath9k/ar9002_hw.c val &= ~(AR_WA_BIT6 | AR_WA_BIT7); val 284 drivers/net/wireless/ath/ath9k/ar9002_hw.c val |= AR_WA_BIT22; val 287 drivers/net/wireless/ath/ath9k/ar9002_hw.c val |= AR_WA_BIT23; val 289 drivers/net/wireless/ath/ath9k/ar9002_hw.c REG_WRITE(ah, AR_WA, val); val 292 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = ah->config.pcie_waen; val 293 drivers/net/wireless/ath/ath9k/ar9002_hw.c val &= (~AR_WA_D3_L1_DISABLE); val 296 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = AR9285_WA_DEFAULT; val 297 drivers/net/wireless/ath/ath9k/ar9002_hw.c val &= (~AR_WA_D3_L1_DISABLE); val 303 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = AR9280_WA_DEFAULT; val 304 drivers/net/wireless/ath/ath9k/ar9002_hw.c val &= (~AR_WA_D3_L1_DISABLE); val 306 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = AR_WA_DEFAULT; val 312 drivers/net/wireless/ath/ath9k/ar9002_hw.c val |= (AR_WA_BIT6 | AR_WA_BIT7); val 315 drivers/net/wireless/ath/ath9k/ar9002_hw.c val |= AR_WA_BIT23; val 317 drivers/net/wireless/ath/ath9k/ar9002_hw.c REG_WRITE(ah, AR_WA, val); val 326 drivers/net/wireless/ath/ath9k/ar9002_hw.c u32 val; val 337 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; val 338 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); val 340 drivers/net/wireless/ath/ath9k/ar9002_hw.c return ath9k_hw_reverse_bits(val, 8); val 345 drivers/net/wireless/ath/ath9k/ar9002_hw.c u32 val; val 349 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = ar9002_hw_get_radiorev(ah); val 350 drivers/net/wireless/ath/ath9k/ar9002_hw.c switch (val & AR_RADIO_SREV_MAJOR) { val 352 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = AR_RAD5133_SREV_MAJOR; val 362 drivers/net/wireless/ath/ath9k/ar9002_hw.c val & AR_RADIO_SREV_MAJOR); val 366 drivers/net/wireless/ath/ath9k/ar9002_hw.c ah->hw_version.analog5GhzRev = val; val 440 drivers/net/wireless/ath/ath9k/ar9002_hw.c u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); val 445 drivers/net/wireless/ath/ath9k/ar9002_hw.c val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; val 448 drivers/net/wireless/ath/ath9k/ar9002_hw.c REG_WRITE(ah, reg, val|val_orig); val 450 drivers/net/wireless/ath/ath9k/ar9002_hw.c REG_WRITE(ah, reg, val); val 344 drivers/net/wireless/ath/ath9k/ar9003_calib.c u32 temp, val; val 481 drivers/net/wireless/ath/ath9k/ar9003_calib.c val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff; val 482 drivers/net/wireless/ath/ath9k/ar9003_calib.c val |= (osdac_ch0 << 30); val 483 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val); val 502 drivers/net/wireless/ath/ath9k/ar9003_calib.c val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff; val 503 drivers/net/wireless/ath/ath9k/ar9003_calib.c val |= (osdac_ch1 << 30); val 504 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val); val 523 drivers/net/wireless/ath/ath9k/ar9003_calib.c val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff; val 524 drivers/net/wireless/ath/ath9k/ar9003_calib.c val |= (osdac_ch2 << 30); val 525 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val); val 3019 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c u16 val; val 3021 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) val 3024 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c *buffer = (val >> (8 * (address % 2))) & 0xff; val 3031 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c u16 val; val 3033 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) val 3036 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c buffer[0] = val >> 8; val 3037 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c buffer[1] = val & 0xff; val 3640 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; val 3641 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c return le16_to_cpu(val); val 4213 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c u32 val; val 4227 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain]; val 4229 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c AR_PHY_EXT_CCA0_THRESH62_1, val); val 4458 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c u32 val; val 4462 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c val = SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) | val 4466 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c val = SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_ACK) | val 4470 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_TPC, val); val 5548 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c u32 val; val 5556 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c val = REG_READ(ah, AR_PHY_POWER_TX_SUB); val 5559 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c val & 0xFFFFFFC0); val 5562 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c val & 0xFFFFF000); val 1024 drivers/net/wireless/ath/ath9k/ar9003_hw.c u32 val = ah->config.aspm_l1_fix; val 1025 drivers/net/wireless/ath/ath9k/ar9003_hw.c if ((val & 0xff000000) == 0x17000000) { val 1026 drivers/net/wireless/ath/ath9k/ar9003_hw.c val &= 0x00ffffff; val 1027 drivers/net/wireless/ath/ath9k/ar9003_hw.c val |= 0x27000000; val 1028 drivers/net/wireless/ath/ath9k/ar9003_hw.c REG_WRITE(ah, 0x570c, val); val 31 drivers/net/wireless/ath/ath9k/ar9003_mac.c u32 val, ctl12, ctl17; val 36 drivers/net/wireless/ath/ath9k/ar9003_mac.c val = (ATHEROS_VENDOR_ID << AR_DescId_S) | val 41 drivers/net/wireless/ath/ath9k/ar9003_mac.c checksum += val; val 42 drivers/net/wireless/ath/ath9k/ar9003_mac.c WRITE_ONCE(ads->info, val); val 56 drivers/net/wireless/ath/ath9k/ar9003_mac.c checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen); val 57 drivers/net/wireless/ath/ath9k/ar9003_mac.c WRITE_ONCE(ads->ctl3, val); val 58 drivers/net/wireless/ath/ath9k/ar9003_mac.c checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen); val 59 drivers/net/wireless/ath/ath9k/ar9003_mac.c WRITE_ONCE(ads->ctl5, val); val 60 drivers/net/wireless/ath/ath9k/ar9003_mac.c checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen); val 61 drivers/net/wireless/ath/ath9k/ar9003_mac.c WRITE_ONCE(ads->ctl7, val); val 62 drivers/net/wireless/ath/ath9k/ar9003_mac.c checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen); val 63 drivers/net/wireless/ath/ath9k/ar9003_mac.c WRITE_ONCE(ads->ctl9, val); val 135 drivers/net/wireless/ath/ath9k/ar9003_mac.c val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S; val 136 drivers/net/wireless/ath/ath9k/ar9003_mac.c ctl12 |= SM(val, AR_PAPRDChainMask); val 21 drivers/net/wireless/ath/ath9k/ar9003_paprd.c void ar9003_paprd_enable(struct ath_hw *ah, bool val) val 43 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = false; val 47 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = false; val 51 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = false; val 55 drivers/net/wireless/ath/ath9k/ar9003_paprd.c if (val) { val 61 drivers/net/wireless/ath/ath9k/ar9003_paprd.c AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); val 64 drivers/net/wireless/ath/ath9k/ar9003_paprd.c AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); val 67 drivers/net/wireless/ath/ath9k/ar9003_paprd.c AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); val 152 drivers/net/wireless/ath/ath9k/ar9003_paprd.c int i, val; val 220 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = 148; val 224 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = 145; val 226 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = 147; val 228 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = 137; val 233 drivers/net/wireless/ath/ath9k/ar9003_paprd.c AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val); val 255 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = -10; val 258 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val = -15; val 262 drivers/net/wireless/ath/ath9k/ar9003_paprd.c val); val 696 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 val; val 712 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); val 713 drivers/net/wireless/ath/ath9k/ar9003_phy.c val |= AR_AGG_WEP_ENABLE_FIX | val 716 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PCU_MISC_MODE2, val); val 770 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 val = INI_RA(iniArr, i, column); val 772 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, reg, val); val 1407 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 val; val 1418 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_SFCORR); val 1419 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); val 1420 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); val 1421 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); val 1423 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_SFCORR_LOW); val 1424 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); val 1425 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); val 1426 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); val 1428 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_SFCORR_EXT); val 1429 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); val 1430 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); val 1431 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); val 1432 drivers/net/wireless/ath/ath9k/ar9003_phy.c iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); val 2012 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 val; val 2016 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_RADAR_0); val 2017 drivers/net/wireless/ath/ath9k/ar9003_phy.c val &= (~AR_PHY_RADAR_0_FIRPWR); val 2018 drivers/net/wireless/ath/ath9k/ar9003_phy.c val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR); val 2019 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_RADAR_0, val); val 2021 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_RADAR_0); val 2022 drivers/net/wireless/ath/ath9k/ar9003_phy.c val &= ~AR_PHY_RADAR_0_FIRPWR; val 2023 drivers/net/wireless/ath/ath9k/ar9003_phy.c val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR); val 2024 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_RADAR_0, val); val 2051 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 val, idle_count; val 2071 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; val 2073 drivers/net/wireless/ath/ath9k/ar9003_phy.c (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & val 2164 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 val; val 2175 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_RESTART); val 2176 drivers/net/wireless/ath/ath9k/ar9003_phy.c val &= ~AR_PHY_RESTART_ENA; val 2177 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_RESTART, val); val 75 drivers/net/wireless/ath/ath9k/ar9003_rtt.c u32 val; val 77 drivers/net/wireless/ath/ath9k/ar9003_rtt.c val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA); val 78 drivers/net/wireless/ath/ath9k/ar9003_rtt.c REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); val 80 drivers/net/wireless/ath/ath9k/ar9003_rtt.c val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | val 83 drivers/net/wireless/ath/ath9k/ar9003_rtt.c REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); val 86 drivers/net/wireless/ath/ath9k/ar9003_rtt.c val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); val 87 drivers/net/wireless/ath/ath9k/ar9003_rtt.c REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); val 95 drivers/net/wireless/ath/ath9k/ar9003_rtt.c val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE); val 96 drivers/net/wireless/ath/ath9k/ar9003_rtt.c REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); val 144 drivers/net/wireless/ath/ath9k/ar9003_rtt.c u32 val; val 146 drivers/net/wireless/ath/ath9k/ar9003_rtt.c val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | val 150 drivers/net/wireless/ath/ath9k/ar9003_rtt.c REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); val 153 drivers/net/wireless/ath/ath9k/ar9003_rtt.c val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); val 154 drivers/net/wireless/ath/ath9k/ar9003_rtt.c REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); val 162 drivers/net/wireless/ath/ath9k/ar9003_rtt.c val = MS(REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain)), val 166 drivers/net/wireless/ath/ath9k/ar9003_rtt.c return val; val 186 drivers/net/wireless/ath/ath9k/ar9003_wow.c u32 val = 0, rval; val 193 drivers/net/wireless/ath/ath9k/ar9003_wow.c val = AR_WOW_STATUS(rval); val 200 drivers/net/wireless/ath/ath9k/ar9003_wow.c val &= ah->wow.wow_event_mask; val 202 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (val) { val 203 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (val & AR_WOW_MAGIC_PAT_FOUND) val 205 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (AR_WOW_PATTERN_FOUND(val)) val 207 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (val & AR_WOW_KEEP_ALIVE_FAIL) val 209 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (val & AR_WOW_BEACON_FAIL) val 214 drivers/net/wireless/ath/ath9k/ar9003_wow.c val = AR_WOW_STATUS2(rval); val 215 drivers/net/wireless/ath/ath9k/ar9003_wow.c val &= ah->wow.wow_event_mask2; val 217 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (val) { val 218 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (AR_WOW2_PATTERN_FOUND(val)) val 442 drivers/net/wireless/ath/ath9k/ath9k.h #define case_rtn_string(val) case val: return #val val 75 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c u32 val; val 79 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c val = data->low_val; val 80 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c val |= ((u32)data->high_val) << 16; val 84 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c val = swahb32(val); val 87 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c iowrite32(val, mem + reg); val 323 drivers/net/wireless/ath/ath9k/btcoex.c u32 val; val 349 drivers/net/wireless/ath/ath9k/btcoex.c val = REG_READ(ah, 0x50040); val 350 drivers/net/wireless/ath/ath9k/btcoex.c val &= 0xFFFFFEFF; val 351 drivers/net/wireless/ath/ath9k/btcoex.c REG_WRITE(ah, 0x50040, val); val 857 drivers/net/wireless/ath/ath9k/common-spectral.c unsigned long val; val 866 drivers/net/wireless/ath/ath9k/common-spectral.c if (kstrtoul(buf, 0, &val)) val 869 drivers/net/wireless/ath/ath9k/common-spectral.c if (val > 1) val 872 drivers/net/wireless/ath/ath9k/common-spectral.c spec_priv->spec_config.short_repeat = val; val 905 drivers/net/wireless/ath/ath9k/common-spectral.c unsigned long val; val 914 drivers/net/wireless/ath/ath9k/common-spectral.c if (kstrtoul(buf, 0, &val)) val 917 drivers/net/wireless/ath/ath9k/common-spectral.c if (val > 255) val 920 drivers/net/wireless/ath/ath9k/common-spectral.c spec_priv->spec_config.count = val; val 953 drivers/net/wireless/ath/ath9k/common-spectral.c unsigned long val; val 962 drivers/net/wireless/ath/ath9k/common-spectral.c if (kstrtoul(buf, 0, &val)) val 965 drivers/net/wireless/ath/ath9k/common-spectral.c if (val > 255) val 968 drivers/net/wireless/ath/ath9k/common-spectral.c spec_priv->spec_config.period = val; val 1001 drivers/net/wireless/ath/ath9k/common-spectral.c unsigned long val; val 1010 drivers/net/wireless/ath/ath9k/common-spectral.c if (kstrtoul(buf, 0, &val)) val 1013 drivers/net/wireless/ath/ath9k/common-spectral.c if (val > 15) val 1016 drivers/net/wireless/ath/ath9k/common-spectral.c spec_priv->spec_config.fft_period = val; val 145 drivers/net/wireless/ath/ath9k/debug.c unsigned int val; val 175 drivers/net/wireless/ath/ath9k/debug.c ani_info[i].name, ani_info[i].val); val 409 drivers/net/wireless/ath/ath9k/debug.c u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; val 411 drivers/net/wireless/ath/ath9k/debug.c u32 *qcuBase = &val[0], *dcuBase = &val[4]; val 426 drivers/net/wireless/ath/ath9k/debug.c val[i] = REG_READ_D(ah, AR_DMADBG_0 + (i * sizeof(u32))); val 427 drivers/net/wireless/ath/ath9k/debug.c seq_printf(file, "%d: %08x ", i, val[i]); val 447 drivers/net/wireless/ath/ath9k/debug.c (val[2] & (0x7 << (i * 3))) >> (i * 3), val 454 drivers/net/wireless/ath/ath9k/debug.c (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); val 456 drivers/net/wireless/ath/ath9k/debug.c (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); val 458 drivers/net/wireless/ath/ath9k/debug.c (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); val 460 drivers/net/wireless/ath/ath9k/debug.c (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); val 462 drivers/net/wireless/ath/ath9k/debug.c (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); val 464 drivers/net/wireless/ath/ath9k/debug.c (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); val 1081 drivers/net/wireless/ath/ath9k/debug.c unsigned long val; val 1090 drivers/net/wireless/ath/ath9k/debug.c if (kstrtoul(buf, 0, &val)) val 1093 drivers/net/wireless/ath/ath9k/debug.c if (val != 1) val 1144 drivers/net/wireless/ath/ath9k/debug.c unsigned long val; val 1154 drivers/net/wireless/ath/ath9k/debug.c if (kstrtoul(buf, 0, &val)) val 1157 drivers/net/wireless/ath/ath9k/debug.c if (val > 1) val 1160 drivers/net/wireless/ath/ath9k/debug.c tpc_enabled = !!val; val 1204 drivers/net/wireless/ath/ath9k/debug.c long val; val 1214 drivers/net/wireless/ath/ath9k/debug.c val = 0; val 1215 drivers/net/wireless/ath/ath9k/debug.c else if (kstrtol(buf, 0, &val)) val 1218 drivers/net/wireless/ath/ath9k/debug.c if (val > 0) val 1221 drivers/net/wireless/ath/ath9k/debug.c if (val < -120) val 1224 drivers/net/wireless/ath/ath9k/debug.c ah->nf_override = val; val 101 drivers/net/wireless/ath/ath9k/dfs_debug.c unsigned long val; val 110 drivers/net/wireless/ath/ath9k/dfs_debug.c if (kstrtoul(buf, 0, &val)) val 113 drivers/net/wireless/ath/ath9k/dfs_debug.c if (val == DFS_STATS_RESET_MAGIC) val 20 drivers/net/wireless/ath/ath9k/eeprom.c void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val) val 22 drivers/net/wireless/ath/ath9k/eeprom.c REG_WRITE(ah, reg, val); val 29 drivers/net/wireless/ath/ath9k/eeprom.c u32 shift, u32 val) val 31 drivers/net/wireless/ath/ath9k/eeprom.c REG_RMW(ah, reg, ((val << shift) & mask), mask); val 671 drivers/net/wireless/ath/ath9k/eeprom.h void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); val 673 drivers/net/wireless/ath/ath9k/eeprom.h u32 shift, u32 val); val 55 drivers/net/wireless/ath/ath9k/gpio.c u32 val = (brightness == LED_OFF); val 58 drivers/net/wireless/ath/ath9k/gpio.c val = !val; val 60 drivers/net/wireless/ath/ath9k/gpio.c ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, val); val 239 drivers/net/wireless/ath/ath9k/htc_drv_init.c __be32 val, reg = cpu_to_be32(reg_offset); val 244 drivers/net/wireless/ath/ath9k/htc_drv_init.c (u8 *) &val, sizeof(val), val 252 drivers/net/wireless/ath/ath9k/htc_drv_init.c return be32_to_cpu(val); val 256 drivers/net/wireless/ath/ath9k/htc_drv_init.c u32 *val, u16 count) val 279 drivers/net/wireless/ath/ath9k/htc_drv_init.c val[i] = be32_to_cpu(tmpval[i]); val 302 drivers/net/wireless/ath/ath9k/htc_drv_init.c static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) val 309 drivers/net/wireless/ath/ath9k/htc_drv_init.c cpu_to_be32(val), val 315 drivers/net/wireless/ath/ath9k/htc_drv_init.c (u8 *) &val, sizeof(val), val 323 drivers/net/wireless/ath/ath9k/htc_drv_init.c static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) val 334 drivers/net/wireless/ath/ath9k/htc_drv_init.c priv->wmi->multi_write[priv->wmi->multi_write_idx].val = val 335 drivers/net/wireless/ath/ath9k/htc_drv_init.c cpu_to_be32(val); val 346 drivers/net/wireless/ath/ath9k/htc_drv_init.c static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) val 353 drivers/net/wireless/ath/ath9k/htc_drv_init.c ath9k_regwrite_buffer(hw_priv, val, reg_offset); val 355 drivers/net/wireless/ath/ath9k/htc_drv_init.c ath9k_regwrite_single(hw_priv, val, reg_offset); val 496 drivers/net/wireless/ath/ath9k/htc_drv_init.c u32 val; val 498 drivers/net/wireless/ath/ath9k/htc_drv_init.c val = REG_READ(ah, reg_offset); val 499 drivers/net/wireless/ath/ath9k/htc_drv_init.c val &= ~clr; val 500 drivers/net/wireless/ath/ath9k/htc_drv_init.c val |= set; val 501 drivers/net/wireless/ath/ath9k/htc_drv_init.c REG_WRITE(ah, reg_offset, val); val 77 drivers/net/wireless/ath/ath9k/hw.c bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) val 84 drivers/net/wireless/ath/ath9k/hw.c if ((REG_READ(ah, reg) & mask) == val) val 92 drivers/net/wireless/ath/ath9k/hw.c timeout, reg, REG_READ(ah, reg), mask, val); val 155 drivers/net/wireless/ath/ath9k/hw.c u32 ath9k_hw_reverse_bits(u32 val, u32 n) val 161 drivers/net/wireless/ath/ath9k/hw.c retval = (retval << 1) | (val & 1); val 162 drivers/net/wireless/ath/ath9k/hw.c val >>= 1; val 258 drivers/net/wireless/ath/ath9k/hw.c u32 val; val 270 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_SREV); val 271 drivers/net/wireless/ath/ath9k/hw.c ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); val 296 drivers/net/wireless/ath/ath9k/hw.c val = srev & AR_SREV_ID; val 298 drivers/net/wireless/ath/ath9k/hw.c if (val == 0xFF) { val 299 drivers/net/wireless/ath/ath9k/hw.c val = srev; val 301 drivers/net/wireless/ath/ath9k/hw.c (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; val 302 drivers/net/wireless/ath/ath9k/hw.c ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); val 307 drivers/net/wireless/ath/ath9k/hw.c ah->is_pciexpress = (val & val 311 drivers/net/wireless/ath/ath9k/hw.c ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); val 313 drivers/net/wireless/ath/ath9k/hw.c ah->hw_version.macRev = val & AR_SREV_REVISION; val 1008 drivers/net/wireless/ath/ath9k/hw.c u32 val = ath9k_hw_mac_to_clks(ah, us - 2); val 1009 drivers/net/wireless/ath/ath9k/hw.c val = min(val, (u32) 0xFFFF); val 1010 drivers/net/wireless/ath/ath9k/hw.c REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); val 1015 drivers/net/wireless/ath/ath9k/hw.c u32 val = ath9k_hw_mac_to_clks(ah, us); val 1016 drivers/net/wireless/ath/ath9k/hw.c val = min(val, (u32) 0xFFFF); val 1017 drivers/net/wireless/ath/ath9k/hw.c REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); val 1022 drivers/net/wireless/ath/ath9k/hw.c u32 val = ath9k_hw_mac_to_clks(ah, us); val 1023 drivers/net/wireless/ath/ath9k/hw.c val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); val 1024 drivers/net/wireless/ath/ath9k/hw.c REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); val 1029 drivers/net/wireless/ath/ath9k/hw.c u32 val = ath9k_hw_mac_to_clks(ah, us); val 1030 drivers/net/wireless/ath/ath9k/hw.c val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); val 1031 drivers/net/wireless/ath/ath9k/hw.c REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); val 1384 drivers/net/wireless/ath/ath9k/hw.c u32 val; val 1387 drivers/net/wireless/ath/ath9k/hw.c val = AR_RC_HOSTIF; val 1389 drivers/net/wireless/ath/ath9k/hw.c val |= AR_RC_AHB; val 1390 drivers/net/wireless/ath/ath9k/hw.c REG_WRITE(ah, AR_RC, val); val 1632 drivers/net/wireless/ath/ath9k/hw.c u32 val; val 1634 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_NAV); val 1635 drivers/net/wireless/ath/ath9k/hw.c if (val != 0xdeadbeef && val > 0x7fff) { val 1636 drivers/net/wireless/ath/ath9k/hw.c ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); val 2181 drivers/net/wireless/ath/ath9k/hw.c u32 val; val 2210 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; val 2211 drivers/net/wireless/ath/ath9k/hw.c if (val == AR_RTC_STATUS_ON) val 2813 drivers/net/wireless/ath/ath9k/hw.c u32 val = 0xffffffff; val 2822 drivers/net/wireless/ath/ath9k/hw.c val = MS_REG_READ(AR9271, gpio); val 2824 drivers/net/wireless/ath/ath9k/hw.c val = MS_REG_READ(AR9287, gpio); val 2826 drivers/net/wireless/ath/ath9k/hw.c val = MS_REG_READ(AR9285, gpio); val 2828 drivers/net/wireless/ath/ath9k/hw.c val = MS_REG_READ(AR928X, gpio); val 2830 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); val 2832 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio); val 2834 drivers/net/wireless/ath/ath9k/hw.c val = MS_REG_READ(AR, gpio); val 2836 drivers/net/wireless/ath/ath9k/hw.c val = gpio_get_value(gpio) & BIT(gpio); val 2841 drivers/net/wireless/ath/ath9k/hw.c return !!val; val 2845 drivers/net/wireless/ath/ath9k/hw.c void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) val 2850 drivers/net/wireless/ath/ath9k/hw.c val = !val; val 2852 drivers/net/wireless/ath/ath9k/hw.c val = !!val; val 2858 drivers/net/wireless/ath/ath9k/hw.c REG_RMW(ah, out_addr, val << gpio, BIT(gpio)); val 2860 drivers/net/wireless/ath/ath9k/hw.c gpio_set_value(gpio, val); val 1035 drivers/net/wireless/ath/ath9k/hw.h void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); val 1041 drivers/net/wireless/ath/ath9k/hw.h bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); val 1045 drivers/net/wireless/ath/ath9k/hw.h u32 ath9k_hw_reverse_bits(u32 val, u32 n); val 1117 drivers/net/wireless/ath/ath9k/hw.h void ar9003_paprd_enable(struct ath_hw *ah, bool val); val 173 drivers/net/wireless/ath/ath9k/init.c static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) val 182 drivers/net/wireless/ath/ath9k/init.c iowrite32(val, sc->mem + reg_offset); val 185 drivers/net/wireless/ath/ath9k/init.c iowrite32(val, sc->mem + reg_offset); val 193 drivers/net/wireless/ath/ath9k/init.c u32 val; val 198 drivers/net/wireless/ath/ath9k/init.c val = ioread32(sc->mem + reg_offset); val 201 drivers/net/wireless/ath/ath9k/init.c val = ioread32(sc->mem + reg_offset); val 202 drivers/net/wireless/ath/ath9k/init.c return val; val 206 drivers/net/wireless/ath/ath9k/init.c u32 *val, u16 count) val 211 drivers/net/wireless/ath/ath9k/init.c val[i] = ath9k_ioread32(hw_priv, addr[i]); val 218 drivers/net/wireless/ath/ath9k/init.c u32 val; val 220 drivers/net/wireless/ath/ath9k/init.c val = ioread32(sc->mem + reg_offset); val 221 drivers/net/wireless/ath/ath9k/init.c val &= ~clr; val 222 drivers/net/wireless/ath/ath9k/init.c val |= set; val 223 drivers/net/wireless/ath/ath9k/init.c iowrite32(val, sc->mem + reg_offset); val 225 drivers/net/wireless/ath/ath9k/init.c return val; val 234 drivers/net/wireless/ath/ath9k/init.c u32 val; val 238 drivers/net/wireless/ath/ath9k/init.c val = __ath9k_reg_rmw(sc, reg_offset, set, clr); val 241 drivers/net/wireless/ath/ath9k/init.c val = __ath9k_reg_rmw(sc, reg_offset, set, clr); val 243 drivers/net/wireless/ath/ath9k/init.c return val; val 2217 drivers/net/wireless/ath/ath9k/main.c static bool validate_antenna_mask(struct ath_hw *ah, u32 val) val 2222 drivers/net/wireless/ath/ath9k/main.c switch (val & 0x7) { val 890 drivers/net/wireless/ath/ath9k/pci.c u32 val; val 939 drivers/net/wireless/ath/ath9k/pci.c pci_read_config_dword(pdev, 0x40, &val); val 940 drivers/net/wireless/ath/ath9k/pci.c if ((val & 0x0000ff00) != 0) val 941 drivers/net/wireless/ath/ath9k/pci.c pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); val 1053 drivers/net/wireless/ath/ath9k/pci.c u32 val; val 1060 drivers/net/wireless/ath/ath9k/pci.c pci_read_config_dword(pdev, 0x40, &val); val 1061 drivers/net/wireless/ath/ath9k/pci.c if ((val & 0x0000ff00) != 0) val 1062 drivers/net/wireless/ath/ath9k/pci.c pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); val 133 drivers/net/wireless/ath/ath9k/wmi.h __be32 val; val 1609 drivers/net/wireless/ath/ath9k/xmit.c ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val) val 1613 drivers/net/wireless/ath/ath9k/xmit.c u16 mask_val = mask * val; val 43 drivers/net/wireless/ath/carl9170/cmd.c int carl9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val) val 47 drivers/net/wireless/ath/carl9170/cmd.c cpu_to_le32(val), val 56 drivers/net/wireless/ath/carl9170/cmd.c "(val %#x) failed (%d)\n", reg, val, err); val 94 drivers/net/wireless/ath/carl9170/cmd.c int carl9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val) val 96 drivers/net/wireless/ath/carl9170/cmd.c return carl9170_read_mreg(ar, 1, ®, val); val 45 drivers/net/wireless/ath/carl9170/cmd.h int carl9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val); val 46 drivers/net/wireless/ath/carl9170/cmd.h int carl9170_read_reg(struct ar9170 *ar, const u32 reg, u32 *val); val 157 drivers/net/wireless/ath/carl9170/cmd.h __cmd->wreg.regs[__nreg].val = cpu_to_le32(v); \ val 702 drivers/net/wireless/ath/carl9170/debug.c int res, val; val 707 drivers/net/wireless/ath/carl9170/debug.c res = sscanf(buf, "%d", &val); val 711 drivers/net/wireless/ath/carl9170/debug.c if (!((val > CARL9170_ERP_INVALID) && val 712 drivers/net/wireless/ath/carl9170/debug.c (val < __CARL9170_ERP_NUM))) val 715 drivers/net/wireless/ath/carl9170/debug.c ar->erp_mode = val; val 725 drivers/net/wireless/ath/carl9170/debug.c u32 reg, val; val 733 drivers/net/wireless/ath/carl9170/debug.c res = sscanf(buf, "0x%X 0x%X", ®, &val); val 749 drivers/net/wireless/ath/carl9170/debug.c err = carl9170_write_reg(ar, reg, val); val 123 drivers/net/wireless/ath/carl9170/fwcmd.h __le32 val; val 130 drivers/net/wireless/ath/carl9170/fwcmd.h u8 val[0]; val 46 drivers/net/wireless/ath/carl9170/mac.c u32 val; val 49 drivers/net/wireless/ath/carl9170/mac.c val = 0x010a; val 52 drivers/net/wireless/ath/carl9170/mac.c val = 0x105; val 54 drivers/net/wireless/ath/carl9170/mac.c val = 0x104; val 57 drivers/net/wireless/ath/carl9170/mac.c return carl9170_write_reg(ar, AR9170_MAC_REG_DYNAMIC_SIFS_ACK, val); val 441 drivers/net/wireless/ath/carl9170/phy.c u32 val; val 459 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_SETTLING, val 461 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling); val 462 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_SETTLING, val); val 466 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_DESIRED_SZ, is_2ghz, is_40mhz); val 467 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize); val 468 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize); val 469 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_DESIRED_SZ, val); val 472 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_RF_CTL4, is_2ghz, is_40mhz); val 473 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff); val 474 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff); val 475 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn); val 476 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn); val 477 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_RF_CTL4, val); val 480 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_RF_CTL3, is_2ghz, is_40mhz); val 481 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn); val 482 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_RF_CTL3, val); val 485 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(0x1c8864, is_2ghz, is_40mhz); val 486 drivers/net/wireless/ath/carl9170/phy.c val = (val & ~0x7f000) | (m->thresh62 << 12); val 487 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(0x1c8864, val); val 490 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_RXGAIN, is_2ghz, is_40mhz); val 491 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]); val 492 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_RXGAIN, val); val 495 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_RXGAIN_CHAIN_2, val 497 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]); val 498 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_RXGAIN_CHAIN_2, val); val 501 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ, is_2ghz, is_40mhz); val 502 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[0]); val 505 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_GAIN_2GHZ_BSW_MARGIN, val, m->bswMargin[0]); val 506 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ, val); val 509 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, val 511 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[1]); val 512 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, val); val 515 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(0), val 517 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[0]); val 518 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[0]); val 519 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(0), val); val 522 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(2), val 524 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[1]); val 525 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[1]); val 526 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(2), val); val 529 drivers/net/wireless/ath/carl9170/phy.c val = carl9170_def_val(AR9170_PHY_REG_TPCRG1, is_2ghz, is_40mhz); val 530 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_1, val, val 532 drivers/net/wireless/ath/carl9170/phy.c SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_2, val, val 534 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(AR9170_PHY_REG_TPCRG1, val); val 546 drivers/net/wireless/ath/carl9170/phy.c u32 val; val 555 drivers/net/wireless/ath/carl9170/phy.c val = ar5416_phy_init[i]._2ghz_40; val 557 drivers/net/wireless/ath/carl9170/phy.c val = ar5416_phy_init[i]._5ghz_40; val 560 drivers/net/wireless/ath/carl9170/phy.c val = ar5416_phy_init[i]._2ghz_20; val 562 drivers/net/wireless/ath/carl9170/phy.c val = ar5416_phy_init[i]._5ghz_20; val 565 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(ar5416_phy_init[i].reg, val); val 45 drivers/net/wireless/ath/dfs_pri_detector.c static u32 pde_get_multiple(u32 val, u32 fraction, u32 tolerance) val 54 drivers/net/wireless/ath/dfs_pri_detector.c delta = (val < fraction) ? (fraction - val) : (val - fraction); val 60 drivers/net/wireless/ath/dfs_pri_detector.c factor = val / fraction; val 61 drivers/net/wireless/ath/dfs_pri_detector.c remainder = val % fraction; val 30 drivers/net/wireless/ath/wcn36xx/smd.c #define WCN36XX_CFG_VAL(id, val) \ val 33 drivers/net/wireless/ath/wcn36xx/smd.c .value = val \ val 85 drivers/net/wireless/ath/wcn36xx/smd.c u32 *val; val 98 drivers/net/wireless/ath/wcn36xx/smd.c val = (u32 *) (entry + 1); val 99 drivers/net/wireless/ath/wcn36xx/smd.c *val = value; val 385 drivers/net/wireless/ath/wil6210/debugfs.c static int wil_debugfs_iomem_x32_set(void *data, u64 val) val 396 drivers/net/wireless/ath/wil6210/debugfs.c writel_relaxed(val, (void __iomem *)d->offset); val 405 drivers/net/wireless/ath/wil6210/debugfs.c static int wil_debugfs_iomem_x32_get(void *data, u64 *val) val 416 drivers/net/wireless/ath/wil6210/debugfs.c *val = readl((void __iomem *)d->offset); val 440 drivers/net/wireless/ath/wil6210/debugfs.c static int wil_debugfs_ulong_set(void *data, u64 val) val 442 drivers/net/wireless/ath/wil6210/debugfs.c *(ulong *)data = val; val 446 drivers/net/wireless/ath/wil6210/debugfs.c static int wil_debugfs_ulong_get(void *data, u64 *val) val 448 drivers/net/wireless/ath/wil6210/debugfs.c *val = *(ulong *)data; val 750 drivers/net/wireless/ath/wil6210/debugfs.c int val; val 753 drivers/net/wireless/ath/wil6210/debugfs.c rc = kstrtoint_from_user(buf, count, 0, &val); val 762 drivers/net/wireless/ath/wil6210/debugfs.c val < 0 ? "Disabling" : "Enabling", val); val 764 drivers/net/wireless/ath/wil6210/debugfs.c if (!wil->ring_rx.va || val > wil->ring_rx.size) { val 765 drivers/net/wireless/ath/wil6210/debugfs.c wil_err(wil, "Invalid descriptors threshold, %d\n", val); val 769 drivers/net/wireless/ath/wil6210/debugfs.c rc = wmi_rbufcap_cfg(wil, val < 0 ? 0 : 1, val < 0 ? 0 : val); val 1800 drivers/net/wireless/ath/wil6210/debugfs.c int val, rc, i; val 1803 drivers/net/wireless/ath/wil6210/debugfs.c rc = kstrtoint_from_user(buf, len, 0, &val); val 1808 drivers/net/wireless/ath/wil6210/debugfs.c if (val == 1) val 1810 drivers/net/wireless/ath/wil6210/debugfs.c val = 500; val 1811 drivers/net/wireless/ath/wil6210/debugfs.c if (val && (val < 50 || val > 1000)) { val 1812 drivers/net/wireless/ath/wil6210/debugfs.c wil_err(wil, "Invalid resolution %d\n", val); val 1816 drivers/net/wireless/ath/wil6210/debugfs.c enable = !!val; val 1821 drivers/net/wireless/ath/wil6210/debugfs.c enable ? "Enabling" : "Disabling", val); val 1826 drivers/net/wireless/ath/wil6210/debugfs.c wil->tx_latency_res = val; val 2090 drivers/net/wireless/ath/wil6210/debugfs.c int val; val 2093 drivers/net/wireless/ath/wil6210/debugfs.c rc = kstrtoint_from_user(buf_, count, 0, &val); val 2099 drivers/net/wireless/ath/wil6210/debugfs.c wil_info(wil, "%s led %d\n", val ? "Enabling" : "Disabling", led_id); val 2100 drivers/net/wireless/ath/wil6210/debugfs.c rc = wmi_led_cfg(wil, val); val 2103 drivers/net/wireless/ath/wil6210/debugfs.c val ? "Enabling" : "Disabling", led_id); val 30 drivers/net/wireless/ath/wil6210/fw.c void wil_memset_toio_32(volatile void __iomem *dst, u32 val, val 36 drivers/net/wireless/ath/wil6210/fw.c __raw_writel(val, d++); val 31 drivers/net/wireless/ath/wil6210/fw_inc.c void __iomem **ioaddr, __le32 val, val 34 drivers/net/wireless/ath/wil6210/fw_inc.c *ioaddr = wmi_buffer_block(wil, val, size); val 36 drivers/net/wireless/ath/wil6210/fw_inc.c wil_err_fw(wil, "bad %s: 0x%08x\n", msg, le32_to_cpu(val)); val 59 drivers/net/wireless/ath/wil6210/main.c static int mtu_max_set(const char *val, const struct kernel_param *kp) val 66 drivers/net/wireless/ath/wil6210/main.c ret = param_set_uint(val, kp); val 88 drivers/net/wireless/ath/wil6210/main.c static int ring_order_set(const char *val, const struct kernel_param *kp) val 93 drivers/net/wireless/ath/wil6210/main.c ret = kstrtouint(val, 0, &x); val 850 drivers/net/wireless/ath/wil6210/main.c u32 val; val 858 drivers/net/wireless/ath/wil6210/main.c val = wil_r(wil, RGF_USER_BL + val 861 drivers/net/wireless/ath/wil6210/main.c if (val & BL_SHUTDOWN_HS_RTD) { val 1551 drivers/net/wireless/ath/wil6210/main.c __le32 val = cpu_to_le32(wil->fw_calib_result | val 1553 drivers/net/wireless/ath/wil6210/main.c wil_w(wil, RGF_USER_FW_CALIB_RESULT, (u32 __force)val); val 669 drivers/net/wireless/ath/wil6210/txrx.h static inline bool wil_val_in_range(int val, int min, int max) val 671 drivers/net/wireless/ath/wil6210/txrx.h return val >= min && val < max; val 399 drivers/net/wireless/ath/wil6210/txrx_edma.h u16 val = wil_rx_status_get_flow_id(msg); val 401 drivers/net/wireless/ath/wil6210/txrx_edma.h if (val & WIL_RX_EDMA_DLPF_LU_MISS_BIT) val 403 drivers/net/wireless/ath/wil6210/txrx_edma.h return (val >> WIL_RX_EDMA_DLPF_LU_MISS_CID_POS) & val 407 drivers/net/wireless/ath/wil6210/txrx_edma.h return (val >> WIL_RX_EDMA_DLPF_LU_HIT_CID_POS) & val 413 drivers/net/wireless/ath/wil6210/txrx_edma.h u16 val = wil_rx_status_get_flow_id(msg); val 415 drivers/net/wireless/ath/wil6210/txrx_edma.h if (val & WIL_RX_EDMA_DLPF_LU_MISS_BIT) val 417 drivers/net/wireless/ath/wil6210/txrx_edma.h return (val >> WIL_RX_EDMA_DLPF_LU_MISS_TID_POS) & val 421 drivers/net/wireless/ath/wil6210/txrx_edma.h return val & WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK; val 443 drivers/net/wireless/ath/wil6210/txrx_edma.h u8 val = WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1, val 446 drivers/net/wireless/ath/wil6210/txrx_edma.h switch (val) { val 1139 drivers/net/wireless/ath/wil6210/wil6210.h static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) val 1141 drivers/net/wireless/ath/wil6210/wil6210.h writel(val, wil->csr + HOSTADDR(reg)); val 1146 drivers/net/wireless/ath/wil6210/wil6210.h static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) val 1148 drivers/net/wireless/ath/wil6210/wil6210.h wil_w(wil, reg, wil_r(wil, reg) | val); val 1152 drivers/net/wireless/ath/wil6210/wil6210.h static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) val 1154 drivers/net/wireless/ath/wil6210/wil6210.h wil_w(wil, reg, wil_r(wil, reg) & ~val); val 71 drivers/net/wireless/broadcom/b43/debugfs.c u16 val; val 79 drivers/net/wireless/broadcom/b43/debugfs.c val = b43_shm_read16(dev, routing, addr); val 80 drivers/net/wireless/broadcom/b43/debugfs.c fappend("0x%04X\n", val); val 113 drivers/net/wireless/broadcom/b43/debugfs.c u16 val; val 132 drivers/net/wireless/broadcom/b43/debugfs.c val = 0; val 134 drivers/net/wireless/broadcom/b43/debugfs.c val = b43_shm_read16(dev, routing, addr); val 135 drivers/net/wireless/broadcom/b43/debugfs.c val &= mask; val 136 drivers/net/wireless/broadcom/b43/debugfs.c val |= set; val 137 drivers/net/wireless/broadcom/b43/debugfs.c b43_shm_write16(dev, routing, addr, val); val 147 drivers/net/wireless/broadcom/b43/debugfs.c u32 val; val 155 drivers/net/wireless/broadcom/b43/debugfs.c val = b43_shm_read32(dev, routing, addr); val 156 drivers/net/wireless/broadcom/b43/debugfs.c fappend("0x%08X\n", val); val 189 drivers/net/wireless/broadcom/b43/debugfs.c u32 val; val 208 drivers/net/wireless/broadcom/b43/debugfs.c val = 0; val 210 drivers/net/wireless/broadcom/b43/debugfs.c val = b43_shm_read32(dev, routing, addr); val 211 drivers/net/wireless/broadcom/b43/debugfs.c val &= mask; val 212 drivers/net/wireless/broadcom/b43/debugfs.c val |= set; val 213 drivers/net/wireless/broadcom/b43/debugfs.c b43_shm_write32(dev, routing, addr, val); val 226 drivers/net/wireless/broadcom/b43/debugfs.c u16 val; val 232 drivers/net/wireless/broadcom/b43/debugfs.c val = b43_read16(dev, addr); val 233 drivers/net/wireless/broadcom/b43/debugfs.c fappend("0x%04X\n", val); val 262 drivers/net/wireless/broadcom/b43/debugfs.c u16 val; val 275 drivers/net/wireless/broadcom/b43/debugfs.c val = 0; val 277 drivers/net/wireless/broadcom/b43/debugfs.c val = b43_read16(dev, addr); val 278 drivers/net/wireless/broadcom/b43/debugfs.c val &= mask; val 279 drivers/net/wireless/broadcom/b43/debugfs.c val |= set; val 280 drivers/net/wireless/broadcom/b43/debugfs.c b43_write16(dev, addr, val); val 290 drivers/net/wireless/broadcom/b43/debugfs.c u32 val; val 296 drivers/net/wireless/broadcom/b43/debugfs.c val = b43_read32(dev, addr); val 297 drivers/net/wireless/broadcom/b43/debugfs.c fappend("0x%08X\n", val); val 326 drivers/net/wireless/broadcom/b43/debugfs.c u32 val; val 339 drivers/net/wireless/broadcom/b43/debugfs.c val = 0; val 341 drivers/net/wireless/broadcom/b43/debugfs.c val = b43_read32(dev, addr); val 342 drivers/net/wireless/broadcom/b43/debugfs.c val &= mask; val 343 drivers/net/wireless/broadcom/b43/debugfs.c val |= set; val 344 drivers/net/wireless/broadcom/b43/debugfs.c b43_write32(dev, addr, val); val 138 drivers/net/wireless/broadcom/b43/dma.c u32 val; val 140 drivers/net/wireless/broadcom/b43/dma.c val = b43_dma_read(ring, B43_DMA32_RXSTATUS); val 141 drivers/net/wireless/broadcom/b43/dma.c val &= B43_DMA32_RXDPTR; val 143 drivers/net/wireless/broadcom/b43/dma.c return (val / sizeof(struct b43_dmadesc32)); val 233 drivers/net/wireless/broadcom/b43/dma.c u32 val; val 235 drivers/net/wireless/broadcom/b43/dma.c val = b43_dma_read(ring, B43_DMA64_RXSTATUS); val 236 drivers/net/wireless/broadcom/b43/dma.c val &= B43_DMA64_RXSTATDPTR; val 238 drivers/net/wireless/broadcom/b43/dma.c return (val / sizeof(struct b43_dmadesc64)); val 832 drivers/net/wireless/broadcom/b43/lo.c u16 val; val 850 drivers/net/wireless/broadcom/b43/lo.c val = (u8)(cal->ctl.q); val 851 drivers/net/wireless/broadcom/b43/lo.c val |= ((u8)(cal->ctl.i)) << 4; val 860 drivers/net/wireless/broadcom/b43/lo.c | ((val & 0x00FF) << 8); val 864 drivers/net/wireless/broadcom/b43/lo.c | (val & 0x00FF); val 464 drivers/net/wireless/broadcom/b43/main.c static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) val 472 drivers/net/wireless/broadcom/b43/main.c val = swab32(val); val 475 drivers/net/wireless/broadcom/b43/main.c b43_write32(dev, B43_MMIO_RAM_DATA, val); val 1379 drivers/net/wireless/broadcom/b43/main.c u32 val = 0; val 1381 drivers/net/wireless/broadcom/b43/main.c val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1); val 1382 drivers/net/wireless/broadcom/b43/main.c val <<= 16; val 1383 drivers/net/wireless/broadcom/b43/main.c val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0); val 1385 drivers/net/wireless/broadcom/b43/main.c return val; val 254 drivers/net/wireless/broadcom/b43/phy_common.c u16 val; val 258 drivers/net/wireless/broadcom/b43/phy_common.c val = b43_radio_read(dev, offset); val 259 drivers/net/wireless/broadcom/b43/phy_common.c if ((val & mask) == value) val 361 drivers/net/wireless/broadcom/b43/phy_g.c static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val) val 364 drivers/net/wireless/broadcom/b43/phy_g.c b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val); val 370 drivers/net/wireless/broadcom/b43/phy_g.c u16 val; val 373 drivers/net/wireless/broadcom/b43/phy_g.c val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA); val 375 drivers/net/wireless/broadcom/b43/phy_g.c return (s16) val; val 379 drivers/net/wireless/broadcom/b43/phy_g.c static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val) val 386 drivers/net/wireless/broadcom/b43/phy_g.c tmp -= val; val 1583 drivers/net/wireless/broadcom/b43/phy_g.c u16 offset, val; val 1623 drivers/net/wireless/broadcom/b43/phy_g.c val = 0x1E1F; val 1625 drivers/net/wireless/broadcom/b43/phy_g.c b43_phy_write(dev, offset, val); val 1626 drivers/net/wireless/broadcom/b43/phy_g.c val -= 0x0202; val 1628 drivers/net/wireless/broadcom/b43/phy_g.c val = 0x3E3F; val 1630 drivers/net/wireless/broadcom/b43/phy_g.c b43_phy_write(dev, offset, val); val 1631 drivers/net/wireless/broadcom/b43/phy_g.c val -= 0x0202; val 1633 drivers/net/wireless/broadcom/b43/phy_g.c val = 0x2120; val 1635 drivers/net/wireless/broadcom/b43/phy_g.c b43_phy_write(dev, offset, (val & 0x3F3F)); val 1636 drivers/net/wireless/broadcom/b43/phy_g.c val += 0x0202; val 220 drivers/net/wireless/broadcom/b43/phy_ht.c static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val) val 230 drivers/net/wireless/broadcom/b43/phy_ht.c tmp |= (val & mask); val 296 drivers/net/wireless/broadcom/b43/phy_ht.c u16 val; val 298 drivers/net/wireless/broadcom/b43/phy_ht.c val = 0x1E1F; val 300 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); val 301 drivers/net/wireless/broadcom/b43/phy_ht.c val -= 0x202; val 303 drivers/net/wireless/broadcom/b43/phy_ht.c val = 0x3E3F; val 305 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); val 306 drivers/net/wireless/broadcom/b43/phy_ht.c val -= 0x202; val 320 drivers/net/wireless/broadcom/b43/phy_n.c u16 reg, tmp, tmp2, val; val 349 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 5; val 351 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 4; val 352 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); val 359 drivers/net/wireless/broadcom/b43/phy_n.c val = value; val 363 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 2; val 365 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); val 372 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 1; val 376 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 3; val 378 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); val 391 drivers/net/wireless/broadcom/b43/phy_n.c u16 reg, tmp, val; val 458 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 5; val 461 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 4; val 463 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); val 468 drivers/net/wireless/broadcom/b43/phy_n.c val = value; val 471 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 2; val 473 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); val 478 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 1; val 481 drivers/net/wireless/broadcom/b43/phy_n.c val = value << 3; val 483 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); val 509 drivers/net/wireless/broadcom/b43/phy_n.c static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) val 520 drivers/net/wireless/broadcom/b43/phy_n.c tmp |= (val & mask); val 1742 drivers/net/wireless/broadcom/b43/phy_n.c u16 reg, val; val 1776 drivers/net/wireless/broadcom/b43/phy_n.c val = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 4 : 8; val 1778 drivers/net/wireless/broadcom/b43/phy_n.c val = 16; val 1780 drivers/net/wireless/broadcom/b43/phy_n.c val = 32; val 1781 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_set(dev, reg, val); val 1789 drivers/net/wireless/broadcom/b43/phy_n.c val = 0x0100; val 1791 drivers/net/wireless/broadcom/b43/phy_n.c val = 0x0200; val 1793 drivers/net/wireless/broadcom/b43/phy_n.c val = 0x0300; val 1799 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, 0xFCFF, val); val 1800 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, 0xF3FF, val << 2); val 1809 drivers/net/wireless/broadcom/b43/phy_n.c val = (band == NL80211_BAND_5GHZ) ? 0xC : 0xE; val 1811 drivers/net/wireless/broadcom/b43/phy_n.c val = 0x11; val 1814 drivers/net/wireless/broadcom/b43/phy_n.c b43_radio_write(dev, reg, val); val 1830 drivers/net/wireless/broadcom/b43/phy_n.c u16 val; val 1837 drivers/net/wireless/broadcom/b43/phy_n.c val = 0; val 1841 drivers/net/wireless/broadcom/b43/phy_n.c val = 1; val 1844 drivers/net/wireless/broadcom/b43/phy_n.c val = 2; val 1847 drivers/net/wireless/broadcom/b43/phy_n.c val = 3; val 1850 drivers/net/wireless/broadcom/b43/phy_n.c val = (val << 12) | (val << 14); val 1851 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); val 1852 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); val 2295 drivers/net/wireless/broadcom/b43/phy_n.c u8 code, val; val 2313 drivers/net/wireless/broadcom/b43/phy_n.c val = 6; val 2316 drivers/net/wireless/broadcom/b43/phy_n.c val = 4; val 2335 drivers/net/wireless/broadcom/b43/phy_n.c b43_radio_write(dev, B2055_C1_PD_RXTX, val); val 2340 drivers/net/wireless/broadcom/b43/phy_n.c b43_radio_write(dev, B2055_C2_PD_RXTX, val); val 3604 drivers/net/wireless/broadcom/b43/phy_n.c u16 bmask, val, tmp; val 3662 drivers/net/wireless/broadcom/b43/phy_n.c val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; val 3665 drivers/net/wireless/broadcom/b43/phy_n.c if (val) val 3666 drivers/net/wireless/broadcom/b43/phy_n.c val |= B43_NPHY_TXPCTL_CMD_PCTLEN; val 3668 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val); val 5960 drivers/net/wireless/broadcom/b43/phy_n.c u16 val; val 5962 drivers/net/wireless/broadcom/b43/phy_n.c val = 0x1E1F; val 5964 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); val 5965 drivers/net/wireless/broadcom/b43/phy_n.c val -= 0x202; val 5967 drivers/net/wireless/broadcom/b43/phy_n.c val = 0x3E3F; val 5969 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); val 5970 drivers/net/wireless/broadcom/b43/phy_n.c val -= 0x202; val 625 drivers/net/wireless/broadcom/b43/tables_phy_lcn.c u32 val; val 632 drivers/net/wireless/broadcom/b43/tables_phy_lcn.c val = ((pa_gain << 24) | val 636 drivers/net/wireless/broadcom/b43/tables_phy_lcn.c b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0xc0 + i), val); val 639 drivers/net/wireless/broadcom/b43/tables_phy_lcn.c val = b43_lcntab_read(dev, B43_LCNTAB32(0x7, 0x140 + i)); val 640 drivers/net/wireless/broadcom/b43/tables_phy_lcn.c val &= 0x000fffff; val 641 drivers/net/wireless/broadcom/b43/tables_phy_lcn.c val |= ((gain_table[i].dac << 28) | val 643 drivers/net/wireless/broadcom/b43/tables_phy_lcn.c b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0x140 + i), val); val 102 drivers/net/wireless/broadcom/b43legacy/dma.c u32 val; val 104 drivers/net/wireless/broadcom/b43legacy/dma.c val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS); val 105 drivers/net/wireless/broadcom/b43legacy/dma.c val &= B43legacy_DMA32_RXDPTR; val 107 drivers/net/wireless/broadcom/b43legacy/dma.c return (val / sizeof(struct b43legacy_dmadesc32)); val 302 drivers/net/wireless/broadcom/b43legacy/ilt.c void b43legacy_ilt_write(struct b43legacy_wldev *dev, u16 offset, u16 val) val 305 drivers/net/wireless/broadcom/b43legacy/ilt.c b43legacy_phy_write(dev, B43legacy_PHY_ILT_G_DATA1, val); val 308 drivers/net/wireless/broadcom/b43legacy/ilt.c void b43legacy_ilt_write32(struct b43legacy_wldev *dev, u16 offset, u32 val) val 312 drivers/net/wireless/broadcom/b43legacy/ilt.c (val & 0xFFFF0000) >> 16); val 314 drivers/net/wireless/broadcom/b43legacy/ilt.c val & 0x0000FFFF); val 30 drivers/net/wireless/broadcom/b43legacy/ilt.h void b43legacy_ilt_write(struct b43legacy_wldev *dev, u16 offset, u16 val); val 32 drivers/net/wireless/broadcom/b43legacy/ilt.h u32 val); val 242 drivers/net/wireless/broadcom/b43legacy/main.c u32 val) val 250 drivers/net/wireless/broadcom/b43legacy/main.c val = swab32(val); val 253 drivers/net/wireless/broadcom/b43legacy/main.c b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val); val 752 drivers/net/wireless/broadcom/b43legacy/main.c u32 val = 0; val 754 drivers/net/wireless/broadcom/b43legacy/main.c val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A); val 755 drivers/net/wireless/broadcom/b43legacy/main.c val <<= 16; val 756 drivers/net/wireless/broadcom/b43legacy/main.c val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408); val 758 drivers/net/wireless/broadcom/b43legacy/main.c return val; val 110 drivers/net/wireless/broadcom/b43legacy/phy.c void b43legacy_phy_write(struct b43legacy_wldev *dev, u16 offset, u16 val) val 113 drivers/net/wireless/broadcom/b43legacy/phy.c b43legacy_write16(dev, B43legacy_MMIO_PHY_DATA, val); val 425 drivers/net/wireless/broadcom/b43legacy/phy.c int val; val 432 drivers/net/wireless/broadcom/b43legacy/phy.c val = 0x3C3D; val 434 drivers/net/wireless/broadcom/b43legacy/phy.c b43legacy_phy_write(dev, offset, val); val 435 drivers/net/wireless/broadcom/b43legacy/phy.c val -= 0x0202; val 474 drivers/net/wireless/broadcom/b43legacy/phy.c u16 val; val 481 drivers/net/wireless/broadcom/b43legacy/phy.c val = 0x3C3D; val 483 drivers/net/wireless/broadcom/b43legacy/phy.c b43legacy_phy_write(dev, offset, val); val 484 drivers/net/wireless/broadcom/b43legacy/phy.c val -= 0x0202; val 645 drivers/net/wireless/broadcom/b43legacy/phy.c u16 val; val 689 drivers/net/wireless/broadcom/b43legacy/phy.c val = 0x1E1F; val 691 drivers/net/wireless/broadcom/b43legacy/phy.c b43legacy_phy_write(dev, offset, val); val 692 drivers/net/wireless/broadcom/b43legacy/phy.c val -= 0x0202; val 694 drivers/net/wireless/broadcom/b43legacy/phy.c val = 0x3E3F; val 696 drivers/net/wireless/broadcom/b43legacy/phy.c b43legacy_phy_write(dev, offset, val); val 697 drivers/net/wireless/broadcom/b43legacy/phy.c val -= 0x0202; val 699 drivers/net/wireless/broadcom/b43legacy/phy.c val = 0x2120; val 701 drivers/net/wireless/broadcom/b43legacy/phy.c b43legacy_phy_write(dev, offset, (val & 0x3F3F)); val 702 drivers/net/wireless/broadcom/b43legacy/phy.c val += 0x0202; val 169 drivers/net/wireless/broadcom/b43legacy/phy.h void b43legacy_phy_write(struct b43legacy_wldev *dev, u16 offset, u16 val); val 126 drivers/net/wireless/broadcom/b43legacy/radio.c void b43legacy_radio_write16(struct b43legacy_wldev *dev, u16 offset, u16 val) val 129 drivers/net/wireless/broadcom/b43legacy/radio.c b43legacy_write16(dev, B43legacy_MMIO_RADIO_DATA_LOW, val); val 317 drivers/net/wireless/broadcom/b43legacy/radio.c void b43legacy_nrssi_hw_write(struct b43legacy_wldev *dev, u16 offset, s16 val) val 320 drivers/net/wireless/broadcom/b43legacy/radio.c b43legacy_phy_write(dev, B43legacy_PHY_NRSSILT_DATA, (u16)val); val 326 drivers/net/wireless/broadcom/b43legacy/radio.c u16 val; val 329 drivers/net/wireless/broadcom/b43legacy/radio.c val = b43legacy_phy_read(dev, B43legacy_PHY_NRSSILT_DATA); val 331 drivers/net/wireless/broadcom/b43legacy/radio.c return (s16)val; val 335 drivers/net/wireless/broadcom/b43legacy/radio.c void b43legacy_nrssi_hw_update(struct b43legacy_wldev *dev, u16 val) val 342 drivers/net/wireless/broadcom/b43legacy/radio.c tmp -= val; val 1784 drivers/net/wireless/broadcom/b43legacy/radio.c void b43legacy_radio_set_txantenna(struct b43legacy_wldev *dev, u32 val) val 1788 drivers/net/wireless/broadcom/b43legacy/radio.c val <<= 8; val 1790 drivers/net/wireless/broadcom/b43legacy/radio.c b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0022, tmp | val); val 1792 drivers/net/wireless/broadcom/b43legacy/radio.c b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x03A8, tmp | val); val 1794 drivers/net/wireless/broadcom/b43legacy/radio.c b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0054, tmp | val); val 46 drivers/net/wireless/broadcom/b43legacy/radio.h void b43legacy_radio_write16(struct b43legacy_wldev *dev, u16 offset, u16 val); val 65 drivers/net/wireless/broadcom/b43legacy/radio.h void b43legacy_radio_set_txantenna(struct b43legacy_wldev *dev, u32 val); val 78 drivers/net/wireless/broadcom/b43legacy/radio.h void b43legacy_nrssi_hw_write(struct b43legacy_wldev *dev, u16 offset, s16 val); val 79 drivers/net/wireless/broadcom/b43legacy/radio.h void b43legacy_nrssi_hw_update(struct b43legacy_wldev *dev, u16 val); val 980 drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c int val) val 1501 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c s32 val = 0; val 1505 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED; val 1507 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED; val 1509 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA_AUTH_DISABLED; val 1510 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c brcmf_dbg(CONN, "setting wpa_auth to 0x%0x\n", val); val 1511 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c err = brcmf_fil_bsscfg_int_set(ifp, "wpa_auth", val); val 1528 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c s32 val = 0; val 1533 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = 0; val 1537 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = 1; val 1541 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = 2; val 1546 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c err = brcmf_fil_bsscfg_int_set(ifp, "auth", val); val 1639 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c s32 val; val 1654 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c err = brcmf_fil_bsscfg_int_get(netdev_priv(ndev), "wpa_auth", &val); val 1659 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c if (val & (WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED)) { val 1662 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA_AUTH_UNSPECIFIED; val 1667 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA_AUTH_PSK; val 1674 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c } else if (val & (WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED)) { val 1677 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA2_AUTH_UNSPECIFIED; val 1682 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA2_AUTH_1X_SHA256; val 1687 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA2_AUTH_PSK_SHA256; val 1690 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA2_AUTH_PSK; val 1693 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA2_AUTH_UNSPECIFIED | WPA2_AUTH_FT; val 1698 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WPA2_AUTH_PSK | WPA2_AUTH_FT; val 1745 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c brcmf_dbg(CONN, "setting wpa_auth to %d\n", val); val 1746 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "wpa_auth", val); val 1764 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c s32 val; val 1814 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WL_AUTH_SHARED_KEY; /* shared key */ val 1815 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c err = brcmf_fil_bsscfg_int_set(ifp, "auth", val); val 2120 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c scbval.val = cpu_to_le32(reason_code); val 2287 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c s32 val; val 2333 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WEP_ENABLED; val 2338 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WEP_ENABLED; val 2349 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = TKIP_ENABLED; val 2354 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = AES_ENABLED; val 2359 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = AES_ENABLED; val 2377 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c wsec |= val; val 2579 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c rssi = le32_to_cpu(scbval.val); val 2709 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c rssi = le32_to_cpu(scb_val.val); val 4798 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c scbval.val = cpu_to_le32(params->reason_code); val 6152 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c u32 val; val 6159 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WLC_BAND_5G; val 6160 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &val); val 6170 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c val = WLC_N_BW_40ALL; val 6171 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c err = brcmf_fil_iovar_int_set(ifp, "mimo_bw_cap", val); val 281 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 val, base; val 285 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); val 286 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if (val & SSB_TMSLOW_RESET) val 289 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); val 290 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if ((val & SSB_TMSLOW_CLOCK) != 0) { val 295 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); val 297 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val | SSB_TMSLOW_REJECT); val 299 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); val 304 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); val 305 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if (val & SSB_TMSHIGH_BUSY) val 308 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); val 309 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if (val & SSB_IDLOW_INITIATOR) { val 310 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, val 312 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val |= SSB_IMSTATE_REJECT; val 314 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_SB(base, sbimstate), val); val 315 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, val 324 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | val 326 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val); val 327 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); val 331 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); val 332 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if (val & SSB_IDLOW_INITIATOR) { val 333 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, val 335 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val &= ~SSB_IMSTATE_REJECT; val 337 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_SB(base, sbimstate), val); val 536 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u16 reg, u32 val) val 538 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val); val 759 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 val; val 762 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, *eromaddr); val 766 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return val; val 769 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c *type = (val & DMP_DESC_TYPE_MSK); val 773 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return val; val 780 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 val, szdesc; val 787 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc); val 789 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S; val 803 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc); val 819 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if (val & DMP_DESC_ADDRSIZE_GT32) val 822 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S; val 837 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S; val 841 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c *regbase = val & DMP_SLAVE_ADDR_BASE; val 843 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c *wrapbase = val & DMP_SLAVE_ADDR_BASE; val 855 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 val; val 864 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type); val 865 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if (!(val & DMP_DESC_VALID)) val 875 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S; val 878 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type); val 879 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT)) val 883 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S; val 884 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S; val 885 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S; val 886 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S; val 887 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S; val 991 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 val; val 1007 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL); val 1008 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val &= ARMCR4_BCMA_IOCTL_CPUHALT; val 1009 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT, val 1024 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 val; val 1041 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = chip->ops->read32(chip->ctx, val 1043 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c pub->pmurev = val & PCAP_REV_MASK; val 1044 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c pub->pmucaps = val; val 918 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c u32 val; val 931 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c ret = brcmf_fil_iovar_int_get(ifp, "arpoe", &val); val 936 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c ret = brcmf_fil_iovar_int_get(ifp, "arp_version", &val); val 938 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c val = 1; val 939 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c if (val == 1) val 47 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.c #define BRCMF_ENUM_DEF(id, val) \ val 48 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.c { val, #id }, val 95 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.h #define BRCMF_ENUM_DEF(id, val) \ val 96 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.h BRCMF_E_##id = (val), val 523 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h __le32 val; val 165 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c #define BRCMF_FWS_MODE_SET_REUSESEQ(x, val) ((x) = \ val 167 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c (((val) & 1) << BRCMF_FWS_MODE_REUSESEQ_SHIFT)) val 23 drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.c u32 val; val 37 drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.c if (of_property_read_u32(np, "brcm,drive-strength", &val) == 0) val 38 drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.c sdio->drive_strength = val; val 575 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c u32 val; val 585 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); val 587 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c val); val 605 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c val = brcmf_pcie_read_reg32(devinfo, val 608 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c cfg_offset[i], val); val 611 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c val); val 1716 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c u32 val; val 1721 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); val 1722 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c if (val != 0xffffffff) val 1724 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c val); val 2523 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c unsigned long val; val 2528 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret); val 2533 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val &= bus->hostintmask; val 2534 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); val 2537 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c if (val) { val 2538 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret); val 2540 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c atomic_or(val, &bus->intstatus); val 3390 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c u8 val; val 3412 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); val 3417 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val |= 1 << wakeupctrl; val 3418 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); val 3449 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c u8 val; val 3458 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); val 3464 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { val 3465 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << val 3468 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val, &err); val 3856 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c u32 val, rev; val 3858 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val = brcmf_sdiod_readl(sdiodev, addr, NULL); val 3870 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; val 3872 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val &= ~CID_ID_MASK; val 3873 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c val |= BRCM_CC_4339_CHIP_ID; val 3877 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c return val; val 3880 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) val 3884 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(sdiodev, addr, val, NULL); val 543 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val) val 553 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c if (mask || val) val 554 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c bcma_maskset32(cc, regoff, ~mask, val); val 175 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.h u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val); val 180 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.h uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val); val 603 drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c s8 val; val 607 drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c val = 1; val 609 drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c val = 0; val 611 drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c brcms_c_set_shortslot_override(wl->wlc, val); val 1329 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, val 1339 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if ((val & ~mask) || idx >= MHFMAX) val 1362 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val; val 1375 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val; val 1377 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val; val 1417 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val) val 1422 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (val & ~mask) val 1425 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c new_maccontrol = (maccontrol & ~mask) | val; val 2760 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c u32 w, val; val 2776 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c val = bcma_read32(core, D11REGOFFS(objdata)); val 2777 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (val != (u32) 0xaa5555aa) { val 2779 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c "expected 0xaa5555aa\n", wlc_hw->unit, val); val 2789 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c val = bcma_read32(core, D11REGOFFS(objdata)); val 2790 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (val != (u32) 0x55aaaa55) { val 2792 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c "expected 0x55aaaa55\n", wlc_hw->unit, val); val 3991 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val) val 3997 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val); val 4001 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->_g = (bool) val; val 4004 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->g_override = (s8) val; val 4007 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->gmode_user = (u8) val; val 4010 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->overlap = (s8) val; val 4013 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->nmode_user = (s8) val; val 4016 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->n_cfg = (s8) val; val 4019 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->n_cfg_override = (s8) val; val 4022 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->nongf = (bool) val; val 4025 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->nongf_override = (s8) val; val 4028 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->n_pam_override = (s8) val; val 4031 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->protection->n_obss = (bool) val; val 4040 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val) val 4048 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val) val 4050 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc->stf->ldpc = val; val 4055 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false)); val 59 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h #define GFIELD(val, field) \ val 60 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h (((val) >> field ## _S) & field ## _M) val 61 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h #define SFIELD(val, field, bits) \ val 62 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h (((val) & (~(field ## _M << field ## _S))) | \ val 643 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h void brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, val 646 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val); val 188 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val) val 195 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_write16(pi->d11core, D11REGOFFS(radioregdata), val); val 198 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_write16(pi->d11core, D11REGOFFS(phy4wdatalo), val); val 234 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val) val 239 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c write_radio_reg(pi, addr, (rval & val)); val 242 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val) val 247 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c write_radio_reg(pi, addr, (rval | val)); val 258 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val) val 263 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c write_radio_reg(pi, addr, (rval & ~mask) | (val & mask)); val 266 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void write_phy_channel_reg(struct brcms_phy *pi, uint val) val 268 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_write16(pi->d11core, D11REGOFFS(phychannel), val); val 279 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val) val 283 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_write16(pi->d11core, D11REGOFFS(phyregdata), val); val 287 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_write32(pi->d11core, D11REGOFFS(phyregaddr), addr | (val << 16)); val 296 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val) val 299 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_mask16(pi->d11core, D11REGOFFS(phyregdata), val); val 303 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val) val 306 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_set16(pi->d11core, D11REGOFFS(phyregdata), val); val 310 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val) val 312 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c val &= mask; val 314 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_maskset16(pi->d11core, D11REGOFFS(phyregdata), ~mask, val); val 838 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val) val 851 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c write_phy_reg(pi, pi->tbl_data_hi, (u16) (val >> 16)); val 852 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c write_phy_reg(pi, pi->tbl_data_lo, (u16) val); val 854 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c write_phy_reg(pi, pi->tbl_data_lo, (u16) val); val 2140 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val) val 2145 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c pi->sh->rx_antdiv = val; val 2148 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c if (val > ANT_RX_DIV_FORCE_1) val 2168 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c if (val > ANT_RX_DIV_FORCE_1) { val 2172 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c ((ANT_RX_DIV_START_1 == val) ? 1 : 0) << 0); val 2175 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0); val 239 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_hal.h void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool val); val 246 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_hal.h void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val); val 248 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_hal.h void wlc_phy_hold_upd(struct brcms_phy_pub *ppi, u32 id, bool val); val 249 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_hal.h void wlc_phy_mute_upd(struct brcms_phy_pub *ppi, bool val, u32 flags); val 896 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); val 897 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); val 898 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); val 899 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val); val 902 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); val 903 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); val 904 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val); val 907 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); val 922 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val); val 924 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void write_phy_channel_reg(struct brcms_phy *pi, uint val); val 1073 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val); val 959 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c #define LCNPHY_IQLOCC_READ(val) \ val 960 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c ((u8)(-(s8)(((val) & 0xf0) >> 4) + (s8)((val) & 0x0f))) val 963 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c #define LCNPHY_TEMPSENSE(val) ((s16)((val > 255) ? (val - 512) : val)) val 2931 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c u32 val; val 3007 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi); val 3011 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c tab.tbl_ptr = &val; val 3570 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c u32 curval1, curval2, stpptr, curptr, strptr, val; val 3618 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = bcma_read32(pi->d11core, D11REGOFFS(tplatewrdata)); val 3619 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c imag = ((val >> 16) & 0x3ff); val 3620 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c real = ((val) & 0x3ff); val 3903 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c u32 val; val 3971 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c tab.tbl_ptr = &val; val 3980 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = (val & 0xfff00000) | val 3984 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = didq; val 4351 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c u32 val; val 4362 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c tab.tbl_ptr = &val; val 4369 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = (((u32) pa_gain << 24) | val 4376 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = (gain_table[j].dac << 28) | (gain_table[j].bb_mult << 20); val 4385 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c u32 val, bbmult, rfgain; val 4421 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = (((index << shift) + (5 * temp) + val 4425 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c tab.tbl_ptr = &val; val 4612 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c u32 val; val 4620 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c tab.tbl_ptr = &val; val 4622 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = 100; val 4630 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c tab.tbl_ptr = &val; val 4633 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = 150; val 4637 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c val = 220; val 14134 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 addr, val; val 14136 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x1e1f; val 14139 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, addr, val); val 14141 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x3e3f; val 14143 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val -= 0x0202; val 14695 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 val; val 14700 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = read_phy_reg(pi, 0xed); val 14702 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= RX_GF_MM_AUTO; val 14703 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val &= ~RX_GF_OR_MM; val 14705 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= RX_GF_OR_MM; val 14707 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0xed, val); val 18044 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 val; val 18059 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 10; val 18061 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 0x92, mask, val); val 18077 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 6; val 18081 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18097 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 6; val 18101 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18104 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 0; val 18108 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18112 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << ((core == PHY_CORE_0) ? val 18114 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0x78, mask, val); val 18116 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c SPINWAIT(((read_phy_reg(pi, 0x78) & val) val 18118 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c if (WARN(read_phy_reg(pi, 0x78) & val, val 18123 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0 << 0; val 18127 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18135 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 5; val 18137 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 4; val 18142 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18152 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 5; val 18155 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 4; val 18160 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18168 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 0; val 18172 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, val); val 18182 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 2; val 18186 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, val); val 18196 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 11; val 18200 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18205 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 0; val 18208 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 2; val 18213 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18221 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 1; val 18225 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, val); val 18235 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 3; val 18239 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, val); val 18249 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 11; val 18253 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 18258 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 1; val 18261 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = value << 3; val 18266 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 19207 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 val; val 19342 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = read_phy_reg(pi, 0x01); val 19343 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA); val 19344 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA)); val 19561 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 val; val 19565 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = read_phy_reg(pi, 0x01); val 19566 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA); val 19568 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA)); val 21036 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 val; val 21038 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand; val 21039 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c if (CHSPEC_IS5G(chanspec) && !val) { val 21041 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = bcma_read16(pi->d11core, D11REGOFFS(psm_phy_hdr_param)); val 21043 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c (val | MAC_PHY_FORCE_CLK)); val 21048 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c bcma_write16(pi->d11core, D11REGOFFS(psm_phy_hdr_param), val); val 21051 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c } else if (!CHSPEC_IS5G(chanspec) && val) { val 21055 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = bcma_read16(pi->d11core, D11REGOFFS(psm_phy_hdr_param)); val 21057 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c (val | MAC_PHY_FORCE_CLK)); val 21062 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c bcma_write16(pi->d11core, D11REGOFFS(psm_phy_hdr_param), val); val 21097 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = CHSPEC_CHANNEL(chanspec); val 21100 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c if ((val == 13) || (val == 14) || (val == 153)) val 21102 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c } else if (((val >= 5) && (val <= 8)) || (val == 13) val 21103 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c || (val == 14)) { val 21107 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c if (val == 54) val 21110 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c ((val == 38) || (val == 102) || (val == 118))) { val 21305 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val) val 21319 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c new_ctl = (curr_ctl & (~mask)) | (val & mask); val 21646 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 mask, val; val 21703 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 2; val 21706 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 3; val 21711 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 4; val 21714 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 5; val 21719 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); val 21722 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 5; val 21724 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 0xe5 : 0xe6, mask, val); val 21728 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 8; val 21732 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); val 21734 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 1 << 10; val 21738 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); val 21742 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 2 << 8; val 21746 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); val 21748 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 2 << 10; val 21752 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); val 21755 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 3 << 8; val 21759 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); val 21761 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 3 << 10; val 21765 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); val 21782 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x0; val 21784 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x1; val 21786 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x2; val 21788 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x3; val 21791 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = (val << 12) | (val << 14); val 21792 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa6, mask, val); val 21793 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa7, mask, val); val 21799 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x1; val 21801 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x2; val 21803 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0x3; val 21806 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = (val << 4); val 21807 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0x7a, mask, val); val 21808 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0x7d, mask, val); val 23907 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 val, mask; val 23914 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = (0x2 << 8); val 23915 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= (0x2 << 10); val 23916 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa6, mask, val); val 23917 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa7, mask, val); val 23919 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = read_phy_reg(pi, 0x8f); val 23920 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->tx_rx_cal_phy_saveregs[2] = val; val 23921 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= ((0x1 << 9) | (0x1 << 10)); val 23922 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x8f, val); val 23924 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = read_phy_reg(pi, 0xa5); val 23925 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->tx_rx_cal_phy_saveregs[3] = val; val 23926 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= ((0x1 << 9) | (0x1 << 10)); val 23927 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0xa5, val); val 23933 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c &val); val 23934 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->tx_rx_cal_phy_saveregs[5] = val; val 23935 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0; val 23937 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c &val); val 23940 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c &val); val 23941 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->tx_rx_cal_phy_saveregs[6] = val; val 23942 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = 0; val 23944 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c &val); val 24030 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = (0x2 << 12); val 24031 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= (0x2 << 14); val 24032 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa6, mask, val); val 24033 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa7, mask, val); val 24035 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = read_phy_reg(pi, 0xa5); val 24036 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->tx_rx_cal_phy_saveregs[2] = val; val 24037 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= ((0x1 << 12) | (0x1 << 13)); val 24038 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0xa5, val); val 24041 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c &val); val 24042 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->tx_rx_cal_phy_saveregs[3] = val; val 24043 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= 0x2000; val 24045 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c &val); val 24048 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c &val); val 24049 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->tx_rx_cal_phy_saveregs[4] = val; val 24050 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= 0x2000; val 24052 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c &val); val 24056 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120; val 24057 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x91, val); val 24058 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x92, val); val 25194 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c s32 i, val = 0; val 25201 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c i, 32, &val); val 25665 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 val; val 25898 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = val 25901 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0xc1, val); val 28192 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 mask = 0, val = 0, ishw = 0; val 28268 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val = (ishw << 14) | (ishw << 13); val 28272 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c val |= (ishw << 15); val 28275 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0x1e7, mask, val); val 111 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c u16 val, int bands) val 113 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c brcms_b_mhf(physhim->wlc_hw, idx, mask, val, bands); val 136 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val) val 138 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c brcms_b_mctrl(physhim->wlc_hw, mask, val); val 145 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.h void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, u16 val, val 151 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.h void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val); val 289 drivers/net/wireless/broadcom/brcm80211/brcmsmac/pub.h void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val); val 47 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c static void brcms_c_stf_stbc_rx_ht_update(struct brcms_c_info *wlc, int val) val 51 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c if ((wlc->stf->rxstreams == 1) && (val != HT_CAP_RX_STBC_NO)) val 193 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c static int brcms_c_stf_spatial_policy_set(struct brcms_c_info *wlc, int val) val 199 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c val); val 201 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c wlc->stf->spatial_policy = (s8) val; val 203 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c core_mask = (val == MAX_SPATIAL_EXPANSION) ? val 133 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define CONF_HAS(config, val) ((config) & (1 << (val))) val 138 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define CONF_IS(config, val) ((config) == (1 << (val))) val 139 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) val 140 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) val 141 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) val 142 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) val 146 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NCONF_HAS(val) CONF_HAS(NCONF, val) val 148 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NCONF_IS(val) CONF_IS(NCONF, val) val 149 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NCONF_GE(val) CONF_GE(NCONF, val) val 150 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NCONF_GT(val) CONF_GT(NCONF, val) val 151 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NCONF_LT(val) CONF_LT(NCONF, val) val 152 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NCONF_LE(val) CONF_LE(NCONF, val) val 154 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val) val 156 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNCONF_IS(val) CONF_IS(LCNCONF, val) val 157 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNCONF_GE(val) CONF_GE(LCNCONF, val) val 158 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNCONF_GT(val) CONF_GT(LCNCONF, val) val 159 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNCONF_LT(val) CONF_LT(LCNCONF, val) val 160 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNCONF_LE(val) CONF_LE(LCNCONF, val) val 162 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11CONF_HAS(val) CONF_HAS(D11CONF, val) val 164 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11CONF_IS(val) CONF_IS(D11CONF, val) val 165 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11CONF_GE(val) CONF_GE(D11CONF, val) val 166 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11CONF_GT(val) CONF_GT(D11CONF, val) val 167 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11CONF_LT(val) CONF_LT(D11CONF, val) val 168 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11CONF_LE(val) CONF_LE(D11CONF, val) val 170 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val) val 171 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define PHYCONF_IS(val) CONF_IS(PHYTYPE, val) val 173 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NREV_IS(var, val) \ val 174 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val)))) val 176 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NREV_GE(var, val) \ val 177 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val)))) val 179 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NREV_GT(var, val) \ val 180 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val)))) val 182 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NREV_LT(var, val) \ val 183 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val)))) val 185 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NREV_LE(var, val) \ val 186 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val)))) val 188 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNREV_IS(var, val) \ val 189 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val)))) val 191 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNREV_GE(var, val) \ val 192 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val)))) val 194 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNREV_GT(var, val) \ val 195 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val)))) val 197 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNREV_LT(var, val) \ val 198 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val)))) val 200 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNREV_LE(var, val) \ val 201 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val)))) val 203 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11REV_IS(var, val) \ val 204 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val)))) val 206 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11REV_GE(var, val) \ val 207 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val)))) val 209 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11REV_GT(var, val) \ val 210 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val)))) val 212 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11REV_LT(var, val) \ val 213 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val)))) val 215 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11REV_LE(var, val) \ val 216 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val)))) val 218 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define PHYTYPE_IS(var, val)\ val 219 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val)))) val 273 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val))) val 98 drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c u16 val; val 110 drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c val = ch->chspec & BRCMU_CHSPEC_D11N_SB_MASK; val 111 drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c if (val == BRCMU_CHSPEC_D11N_SB_L) { val 139 drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c u16 val; val 151 drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c val = ch->chspec & BRCMU_CHSPEC_D11AC_SB_MASK; val 152 drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c if (val == BRCMU_CHSPEC_D11AC_SB_L) { val 155 drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c } else if (val == BRCMU_CHSPEC_D11AC_SB_U) { val 1629 drivers/net/wireless/cisco/airo.c #define MIC_ACCUM(val) \ val 1630 drivers/net/wireless/cisco/airo.c context->accum += (u64)(val) * be32_to_cpu(context->coeff[coeff_position++]); val 1711 drivers/net/wireless/cisco/airo.c u32 val; val 1722 drivers/net/wireless/cisco/airo.c val = ntohl(context->part.d32); val 1723 drivers/net/wireless/cisco/airo.c MIC_ACCUM(val & mask32[byte_position]); /* zero empty bytes */ val 1734 drivers/net/wireless/cisco/airo.c val = (u32)sum; val 1735 drivers/net/wireless/cisco/airo.c digest[0] = (val>>24) & 0xFF; val 1736 drivers/net/wireless/cisco/airo.c digest[1] = (val>>16) & 0xFF; val 1737 drivers/net/wireless/cisco/airo.c digest[2] = (val>>8) & 0xFF; val 1738 drivers/net/wireless/cisco/airo.c digest[3] = val & 0xFF; val 3547 drivers/net/wireless/cisco/airo.c static void OUT4500( struct airo_info *ai, u16 reg, u16 val ) { val 3551 drivers/net/wireless/cisco/airo.c outw( val, ai->dev->base_addr + reg ); val 3553 drivers/net/wireless/cisco/airo.c outb( val & 0xff, ai->dev->base_addr + reg ); val 3554 drivers/net/wireless/cisco/airo.c outb( val >> 8, ai->dev->base_addr + reg + 1 ); val 7645 drivers/net/wireless/cisco/airo.c int val = AIROMAGIC; val 7649 drivers/net/wireless/cisco/airo.c else if (copy_to_user(com.data,(char *)&val,sizeof(val))) val 331 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void read_register(struct net_device *dev, u32 reg, u32 * val) val 335 drivers/net/wireless/intel/ipw2x00/ipw2100.c *val = ioread32(priv->ioaddr + reg); val 336 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("r: 0x%08X => 0x%08X\n", reg, *val); val 339 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_register(struct net_device *dev, u32 reg, u32 val) val 343 drivers/net/wireless/intel/ipw2x00/ipw2100.c iowrite32(val, priv->ioaddr + reg); val 344 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("w: 0x%08X <= 0x%08X\n", reg, val); val 348 drivers/net/wireless/intel/ipw2x00/ipw2100.c u16 * val) val 352 drivers/net/wireless/intel/ipw2x00/ipw2100.c *val = ioread16(priv->ioaddr + reg); val 353 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("r: 0x%08X => %04X\n", reg, *val); val 356 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void read_register_byte(struct net_device *dev, u32 reg, u8 * val) val 360 drivers/net/wireless/intel/ipw2x00/ipw2100.c *val = ioread8(priv->ioaddr + reg); val 361 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("r: 0x%08X => %02X\n", reg, *val); val 364 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_register_word(struct net_device *dev, u32 reg, u16 val) val 368 drivers/net/wireless/intel/ipw2x00/ipw2100.c iowrite16(val, priv->ioaddr + reg); val 369 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("w: 0x%08X <= %04X\n", reg, val); val 372 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_register_byte(struct net_device *dev, u32 reg, u8 val) val 376 drivers/net/wireless/intel/ipw2x00/ipw2100.c iowrite8(val, priv->ioaddr + reg); val 377 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("w: 0x%08X =< %02X\n", reg, val); val 380 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void read_nic_dword(struct net_device *dev, u32 addr, u32 * val) val 384 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register(dev, IPW_REG_INDIRECT_ACCESS_DATA, val); val 387 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_nic_dword(struct net_device *dev, u32 addr, u32 val) val 391 drivers/net/wireless/intel/ipw2x00/ipw2100.c write_register(dev, IPW_REG_INDIRECT_ACCESS_DATA, val); val 394 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void read_nic_word(struct net_device *dev, u32 addr, u16 * val) val 398 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register_word(dev, IPW_REG_INDIRECT_ACCESS_DATA, val); val 401 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_nic_word(struct net_device *dev, u32 addr, u16 val) val 405 drivers/net/wireless/intel/ipw2x00/ipw2100.c write_register_word(dev, IPW_REG_INDIRECT_ACCESS_DATA, val); val 408 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void read_nic_byte(struct net_device *dev, u32 addr, u8 * val) val 412 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register_byte(dev, IPW_REG_INDIRECT_ACCESS_DATA, val); val 415 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_nic_byte(struct net_device *dev, u32 addr, u8 val) val 419 drivers/net/wireless/intel/ipw2x00/ipw2100.c write_register_byte(dev, IPW_REG_INDIRECT_ACCESS_DATA, val); val 428 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_nic_dword_auto_inc(struct net_device *dev, u32 val) val 430 drivers/net/wireless/intel/ipw2x00/ipw2100.c write_register(dev, IPW_REG_AUTOINCREMENT_DATA, val); val 518 drivers/net/wireless/intel/ipw2x00/ipw2100.c void *val, u32 * len) val 546 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_nic_dword(priv->net_dev, addr, val); val 585 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_nic_memory(priv->net_dev, addr, total_length, val); val 596 drivers/net/wireless/intel/ipw2x00/ipw2100.c static int ipw2100_set_ordinal(struct ipw2100_priv *priv, u32 ord, u32 * val, val 612 drivers/net/wireless/intel/ipw2x00/ipw2100.c write_nic_dword(priv->net_dev, addr, *val); val 1187 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 val; val 1205 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_nic_dword(priv->net_dev, addr + 0xFC, &val); val 1206 drivers/net/wireless/intel/ipw2x00/ipw2100.c priv->eeprom_version = (val >> 24) & 0xFF; val 1216 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_nic_dword(priv->net_dev, addr + 0x20, &val); val 1217 drivers/net/wireless/intel/ipw2x00/ipw2100.c if (!((val >> 24) & 0x01)) val 3515 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 val; val 3520 drivers/net/wireless/intel/ipw2x00/ipw2100.c pci_read_config_dword(pci_dev, i * 16 + j, &val); val 3521 drivers/net/wireless/intel/ipw2x00/ipw2100.c out += sprintf(out, "%08X ", val); val 3800 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 val = 0; val 3805 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register(dev, hw_data[i].addr, &val); val 3807 drivers/net/wireless/intel/ipw2x00/ipw2100.c hw_data[i].name, hw_data[i].addr, val); val 3954 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 val = 0; val 3969 drivers/net/wireless/intel/ipw2x00/ipw2100.c if (ipw2100_get_ordinal(priv, ord_data[loop].index, &val, val 3976 drivers/net/wireless/intel/ipw2x00/ipw2100.c ord_data[loop].index, val, val 4159 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 val; val 4162 drivers/net/wireless/intel/ipw2x00/ipw2100.c ret = kstrtou32(buf, 0, &val); val 4166 drivers/net/wireless/intel/ipw2x00/ipw2100.c ipw2100_debug_level = val; val 4221 drivers/net/wireless/intel/ipw2x00/ipw2100.c unsigned long val; val 4228 drivers/net/wireless/intel/ipw2x00/ipw2100.c ret = kstrtoul(buf, 0, &val); val 4232 drivers/net/wireless/intel/ipw2x00/ipw2100.c priv->ieee->scan_age = val; val 4250 drivers/net/wireless/intel/ipw2x00/ipw2100.c int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) | val 4252 drivers/net/wireless/intel/ipw2x00/ipw2100.c return sprintf(buf, "%i\n", val); val 6159 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 val; val 6217 drivers/net/wireless/intel/ipw2x00/ipw2100.c pci_read_config_dword(pci_dev, 0x40, &val); val 6218 drivers/net/wireless/intel/ipw2x00/ipw2100.c if ((val & 0x0000ff00) != 0) val 6219 drivers/net/wireless/intel/ipw2x00/ipw2100.c pci_write_config_dword(pci_dev, 0x40, val & 0xffff00ff); val 6433 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 val; val 6458 drivers/net/wireless/intel/ipw2x00/ipw2100.c pci_read_config_dword(pci_dev, 0x40, &val); val 6459 drivers/net/wireless/intel/ipw2x00/ipw2100.c if ((val & 0x0000ff00) != 0) val 6460 drivers/net/wireless/intel/ipw2x00/ipw2100.c pci_write_config_dword(pci_dev, 0x40, val & 0xffff00ff); val 6777 drivers/net/wireless/intel/ipw2x00/ipw2100.c u16 val; val 6865 drivers/net/wireless/intel/ipw2x00/ipw2100.c val = 0; val 6869 drivers/net/wireless/intel/ipw2x00/ipw2100.c range->freq[val].i = i + 1; val 6870 drivers/net/wireless/intel/ipw2x00/ipw2100.c range->freq[val].m = ipw2100_frequencies[i] * 100000; val 6871 drivers/net/wireless/intel/ipw2x00/ipw2100.c range->freq[val].e = 1; val 6872 drivers/net/wireless/intel/ipw2x00/ipw2100.c val++; val 6874 drivers/net/wireless/intel/ipw2x00/ipw2100.c if (val == IW_MAX_FREQUENCIES) val 6877 drivers/net/wireless/intel/ipw2x00/ipw2100.c range->num_frequency = val; val 7114 drivers/net/wireless/intel/ipw2x00/ipw2100.c int val; val 7115 drivers/net/wireless/intel/ipw2x00/ipw2100.c unsigned int len = sizeof(val); val 7131 drivers/net/wireless/intel/ipw2x00/ipw2100.c err = ipw2100_get_ordinal(priv, IPW_ORD_CURRENT_TX_RATE, &val, &len); val 7137 drivers/net/wireless/intel/ipw2x00/ipw2100.c switch (val & TX_RATE_MASK) { val 327 drivers/net/wireless/intel/ipw2x00/ipw2200.c u8 val) val 329 drivers/net/wireless/intel/ipw2x00/ipw2200.c writeb(val, ipw->hw_base + ofs); val 333 drivers/net/wireless/intel/ipw2x00/ipw2200.c #define ipw_write8(ipw, ofs, val) do { \ val 335 drivers/net/wireless/intel/ipw2x00/ipw2200.c __LINE__, (u32)(ofs), (u32)(val)); \ val 336 drivers/net/wireless/intel/ipw2x00/ipw2200.c _ipw_write8(ipw, ofs, val); \ val 341 drivers/net/wireless/intel/ipw2x00/ipw2200.c u16 val) val 343 drivers/net/wireless/intel/ipw2x00/ipw2200.c writew(val, ipw->hw_base + ofs); val 347 drivers/net/wireless/intel/ipw2x00/ipw2200.c #define ipw_write16(ipw, ofs, val) do { \ val 349 drivers/net/wireless/intel/ipw2x00/ipw2200.c __LINE__, (u32)(ofs), (u32)(val)); \ val 350 drivers/net/wireless/intel/ipw2x00/ipw2200.c _ipw_write16(ipw, ofs, val); \ val 355 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 val) val 357 drivers/net/wireless/intel/ipw2x00/ipw2200.c writel(val, ipw->hw_base + ofs); val 361 drivers/net/wireless/intel/ipw2x00/ipw2200.c #define ipw_write32(ipw, ofs, val) do { \ val 363 drivers/net/wireless/intel/ipw2x00/ipw2200.c __LINE__, (u32)(ofs), (u32)(val)); \ val 364 drivers/net/wireless/intel/ipw2x00/ipw2200.c _ipw_write32(ipw, ofs, val); \ val 604 drivers/net/wireless/intel/ipw2x00/ipw2200.c static char *ipw_error_desc(u32 val) val 606 drivers/net/wireless/intel/ipw2x00/ipw2200.c switch (val) { val 676 drivers/net/wireless/intel/ipw2x00/ipw2200.c static int ipw_get_ordinal(struct ipw_priv *priv, u32 ord, void *val, u32 * len) val 682 drivers/net/wireless/intel/ipw2x00/ipw2200.c if (!priv || !val || !len) { val 724 drivers/net/wireless/intel/ipw2x00/ipw2200.c *((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord); val 752 drivers/net/wireless/intel/ipw2x00/ipw2200.c *((u32 *) val) = val 806 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_read_indirect(priv, addr, val, total_len); val 1193 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 val; val 1199 drivers/net/wireless/intel/ipw2x00/ipw2200.c val = simple_strtoul(p, &p, 16); val 1201 drivers/net/wireless/intel/ipw2x00/ipw2200.c val = simple_strtoul(p, &p, 10); val 1206 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_debug_level = val; val 1481 drivers/net/wireless/intel/ipw2x00/ipw2200.c unsigned long val; val 1493 drivers/net/wireless/intel/ipw2x00/ipw2200.c val = simple_strtoul(p, &p, 16); val 1495 drivers/net/wireless/intel/ipw2x00/ipw2200.c val = simple_strtoul(p, &p, 10); val 1499 drivers/net/wireless/intel/ipw2x00/ipw2200.c priv->ieee->scan_age = val; val 1767 drivers/net/wireless/intel/ipw2x00/ipw2200.c int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) | val 1769 drivers/net/wireless/intel/ipw2x00/ipw2200.c return sprintf(buf, "%i\n", val); val 2432 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 val; val 2439 drivers/net/wireless/intel/ipw2x00/ipw2200.c get_random_bytes(&val, sizeof(val)); val 2441 drivers/net/wireless/intel/ipw2x00/ipw2200.c return ipw_send_cmd_pdu(priv, IPW_CMD_SEED_NUMBER, sizeof(val), &val); val 4079 drivers/net/wireless/intel/ipw2x00/ipw2200.c static s16 exponential_average(s16 prev_avg, s16 val, u8 depth) val 4081 drivers/net/wireless/intel/ipw2x00/ipw2200.c return ((depth-1)*prev_avg + val)/depth; val 4084 drivers/net/wireless/intel/ipw2x00/ipw2200.c static void average_add(struct average *avg, s16 val) val 4087 drivers/net/wireless/intel/ipw2x00/ipw2200.c avg->sum += val; val 4088 drivers/net/wireless/intel/ipw2x00/ipw2200.c avg->entries[avg->pos++] = val; val 11606 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 length, val; val 11651 drivers/net/wireless/intel/ipw2x00/ipw2200.c pci_read_config_dword(pdev, 0x40, &val); val 11652 drivers/net/wireless/intel/ipw2x00/ipw2200.c if ((val & 0x0000ff00) != 0) val 11653 drivers/net/wireless/intel/ipw2x00/ipw2200.c pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); val 11885 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 val; val 11904 drivers/net/wireless/intel/ipw2x00/ipw2200.c pci_read_config_dword(pdev, 0x40, &val); val 11905 drivers/net/wireless/intel/ipw2x00/ipw2200.c if ((val & 0x0000ff00) != 0) val 11906 drivers/net/wireless/intel/ipw2x00/ipw2200.c pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); val 229 drivers/net/wireless/intel/ipw2x00/libipw_module.c unsigned long val; val 234 drivers/net/wireless/intel/ipw2x00/libipw_module.c if (sscanf(buf, "%li", &val) != 1) val 238 drivers/net/wireless/intel/ipw2x00/libipw_module.c libipw_debug_level = val; val 1666 drivers/net/wireless/intel/iwlegacy/3945-mac.c u32 val; val 1680 drivers/net/wireless/intel/iwlegacy/3945-mac.c val = _il_rd(il, HBUS_TARG_MEM_RDAT); val 1681 drivers/net/wireless/intel/iwlegacy/3945-mac.c if (val != le32_to_cpu(*image)) { val 1684 drivers/net/wireless/intel/iwlegacy/3945-mac.c save_len - len, val, le32_to_cpu(*image)); val 1706 drivers/net/wireless/intel/iwlegacy/3945-mac.c u32 val; val 1718 drivers/net/wireless/intel/iwlegacy/3945-mac.c val = _il_rd(il, HBUS_TARG_MEM_RDAT); val 1719 drivers/net/wireless/intel/iwlegacy/3945-mac.c if (val != le32_to_cpu(*image)) { val 1722 drivers/net/wireless/intel/iwlegacy/3945-mac.c "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val, val 3088 drivers/net/wireless/intel/iwlegacy/3945-mac.c unsigned long val; val 3091 drivers/net/wireless/intel/iwlegacy/3945-mac.c ret = kstrtoul(buf, 0, &val); val 3095 drivers/net/wireless/intel/iwlegacy/3945-mac.c il->debug_level = val; val 3132 drivers/net/wireless/intel/iwlegacy/3945-mac.c u32 val; val 3134 drivers/net/wireless/intel/iwlegacy/3945-mac.c val = simple_strtoul(p, &p, 10); val 3138 drivers/net/wireless/intel/iwlegacy/3945-mac.c il3945_hw_reg_set_txpower(il, val); val 2473 drivers/net/wireless/intel/iwlegacy/3945.c u32 val; val 2478 drivers/net/wireless/intel/iwlegacy/3945.c val = il_rd_prph(il, BSM_WR_DWCOUNT_REG); val 2481 drivers/net/wireless/intel/iwlegacy/3945.c val = il_rd_prph(il, reg); val 2482 drivers/net/wireless/intel/iwlegacy/3945.c if (val != le32_to_cpu(*image)) { val 2486 drivers/net/wireless/intel/iwlegacy/3945.c len, val, le32_to_cpu(*image)); val 105 drivers/net/wireless/intel/iwlegacy/4965-calib.c u32 val; val 136 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = max(silence_rssi_b, silence_rssi_c); val 137 drivers/net/wireless/intel/iwlegacy/4965-calib.c max_silence_rssi = max(silence_rssi_a, (u8) val); val 147 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->nrg_silence_rssi[i]; val 148 drivers/net/wireless/intel/iwlegacy/4965-calib.c silence_ref = max(silence_ref, val); val 157 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c); val 158 drivers/net/wireless/intel/iwlegacy/4965-calib.c data->nrg_value[i] = min(rx_info->beacon_energy_a, val); val 224 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->nrg_th_cck + NRG_STEP_CCK; val 225 drivers/net/wireless/intel/iwlegacy/4965-calib.c data->nrg_th_cck = min((u32) ranges->min_nrg_cck, val); val 269 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_cck + AUTO_CORR_STEP_CCK; val 271 drivers/net/wireless/intel/iwlegacy/4965-calib.c min((u32) ranges->auto_corr_max_cck, val); val 273 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK; val 275 drivers/net/wireless/intel/iwlegacy/4965-calib.c min((u32) ranges->auto_corr_max_cck_mrc, val); val 281 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_cck - AUTO_CORR_STEP_CCK; val 282 drivers/net/wireless/intel/iwlegacy/4965-calib.c data->auto_corr_cck = max((u32) ranges->auto_corr_min_cck, val); val 283 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK; val 285 drivers/net/wireless/intel/iwlegacy/4965-calib.c max((u32) ranges->auto_corr_min_cck_mrc, val); val 294 drivers/net/wireless/intel/iwlegacy/4965-calib.c u32 val; val 309 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM; val 311 drivers/net/wireless/intel/iwlegacy/4965-calib.c min((u32) ranges->auto_corr_max_ofdm, val); val 313 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM; val 315 drivers/net/wireless/intel/iwlegacy/4965-calib.c min((u32) ranges->auto_corr_max_ofdm_mrc, val); val 317 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM; val 319 drivers/net/wireless/intel/iwlegacy/4965-calib.c min((u32) ranges->auto_corr_max_ofdm_x1, val); val 321 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM; val 323 drivers/net/wireless/intel/iwlegacy/4965-calib.c min((u32) ranges->auto_corr_max_ofdm_mrc_x1, val); val 332 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM; val 334 drivers/net/wireless/intel/iwlegacy/4965-calib.c max((u32) ranges->auto_corr_min_ofdm, val); val 336 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM; val 338 drivers/net/wireless/intel/iwlegacy/4965-calib.c max((u32) ranges->auto_corr_min_ofdm_mrc, val); val 340 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM; val 342 drivers/net/wireless/intel/iwlegacy/4965-calib.c max((u32) ranges->auto_corr_min_ofdm_x1, val); val 344 drivers/net/wireless/intel/iwlegacy/4965-calib.c val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM; val 346 drivers/net/wireless/intel/iwlegacy/4965-calib.c max((u32) ranges->auto_corr_min_ofdm_mrc_x1, val); val 4564 drivers/net/wireless/intel/iwlegacy/4965-mac.c unsigned long val; val 4567 drivers/net/wireless/intel/iwlegacy/4965-mac.c ret = kstrtoul(buf, 0, &val); val 4571 drivers/net/wireless/intel/iwlegacy/4965-mac.c il->debug_level = val; val 4611 drivers/net/wireless/intel/iwlegacy/4965-mac.c unsigned long val; val 4614 drivers/net/wireless/intel/iwlegacy/4965-mac.c ret = kstrtoul(buf, 10, &val); val 4618 drivers/net/wireless/intel/iwlegacy/4965-mac.c ret = il_set_tx_power(il, val, false); val 35 drivers/net/wireless/intel/iwlegacy/4965.c u32 val; val 47 drivers/net/wireless/intel/iwlegacy/4965.c val = _il_rd(il, HBUS_TARG_MEM_RDAT); val 48 drivers/net/wireless/intel/iwlegacy/4965.c if (val != le32_to_cpu(*image)) { val 66 drivers/net/wireless/intel/iwlegacy/4965.c u32 val; val 80 drivers/net/wireless/intel/iwlegacy/4965.c val = _il_rd(il, HBUS_TARG_MEM_RDAT); val 81 drivers/net/wireless/intel/iwlegacy/4965.c if (val != le32_to_cpu(*image)) { val 84 drivers/net/wireless/intel/iwlegacy/4965.c save_len - len, val, le32_to_cpu(*image)); val 271 drivers/net/wireless/intel/iwlegacy/4965.c u32 val; val 276 drivers/net/wireless/intel/iwlegacy/4965.c val = il_rd_prph(il, BSM_WR_DWCOUNT_REG); val 279 drivers/net/wireless/intel/iwlegacy/4965.c val = il_rd_prph(il, reg); val 280 drivers/net/wireless/intel/iwlegacy/4965.c if (val != le32_to_cpu(*image)) { val 284 drivers/net/wireless/intel/iwlegacy/4965.c len, val, le32_to_cpu(*image)); val 647 drivers/net/wireless/intel/iwlegacy/4965.c s32 val; val 652 drivers/net/wireless/intel/iwlegacy/4965.c il4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val); val 653 drivers/net/wireless/intel/iwlegacy/4965.c return val + y2; val 69 drivers/net/wireless/intel/iwlegacy/common.c u32 val; val 96 drivers/net/wireless/intel/iwlegacy/common.c val = _il_rd(il, CSR_GP_CNTRL); val 98 drivers/net/wireless/intel/iwlegacy/common.c "(CSR_GP_CNTRL 0x%08x)\n", val); val 128 drivers/net/wireless/intel/iwlegacy/common.c u32 val; val 132 drivers/net/wireless/intel/iwlegacy/common.c val = _il_rd_prph(il, reg); val 135 drivers/net/wireless/intel/iwlegacy/common.c return val; val 140 drivers/net/wireless/intel/iwlegacy/common.c il_wr_prph(struct il_priv *il, u32 addr, u32 val) val 146 drivers/net/wireless/intel/iwlegacy/common.c _il_wr_prph(il, addr, val); val 172 drivers/net/wireless/intel/iwlegacy/common.c il_write_targ_mem(struct il_priv *il, u32 addr, u32 val) val 179 drivers/net/wireless/intel/iwlegacy/common.c _il_wr(il, HBUS_TARG_MEM_WDAT, val); val 1965 drivers/net/wireless/intel/iwlegacy/common.h void il_wr_prph(struct il_priv *il, u32 addr, u32 val); val 1967 drivers/net/wireless/intel/iwlegacy/common.h void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val); val 1984 drivers/net/wireless/intel/iwlegacy/common.h _il_write8(struct il_priv *il, u32 ofs, u8 val) val 1986 drivers/net/wireless/intel/iwlegacy/common.h writeb(val, il->hw_base + ofs); val 1988 drivers/net/wireless/intel/iwlegacy/common.h #define il_write8(il, ofs, val) _il_write8(il, ofs, val) val 1991 drivers/net/wireless/intel/iwlegacy/common.h _il_wr(struct il_priv *il, u32 ofs, u32 val) val 1993 drivers/net/wireless/intel/iwlegacy/common.h writel(val, il->hw_base + ofs); val 2055 drivers/net/wireless/intel/iwlegacy/common.h _il_wr_prph(struct il_priv *il, u32 addr, u32 val) val 2058 drivers/net/wireless/intel/iwlegacy/common.h _il_wr(il, HBUS_TARG_PRPH_WDAT, val); val 2091 drivers/net/wireless/intel/iwlegacy/common.h u32 val; val 2095 drivers/net/wireless/intel/iwlegacy/common.h val = _il_rd_prph(il, reg); val 2096 drivers/net/wireless/intel/iwlegacy/common.h _il_wr_prph(il, reg, (val & ~mask)); val 308 drivers/net/wireless/intel/iwlegacy/debug.c u32 val; val 335 drivers/net/wireless/intel/iwlegacy/debug.c val = val 342 drivers/net/wireless/intel/iwlegacy/debug.c val &= BYTE1_MASK; val 345 drivers/net/wireless/intel/iwlegacy/debug.c val &= BYTE2_MASK; val 348 drivers/net/wireless/intel/iwlegacy/debug.c val &= BYTE3_MASK; val 354 drivers/net/wireless/intel/iwlegacy/debug.c pos += scnprintf(buf + pos, bufsz - pos, "0x%08x ", val); val 172 drivers/net/wireless/intel/iwlwifi/dvm/calib.c u32 val; val 203 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = max(silence_rssi_b, silence_rssi_c); val 204 drivers/net/wireless/intel/iwlwifi/dvm/calib.c max_silence_rssi = max(silence_rssi_a, (u8) val); val 214 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->nrg_silence_rssi[i]; val 215 drivers/net/wireless/intel/iwlwifi/dvm/calib.c silence_ref = max(silence_ref, val); val 225 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c); val 226 drivers/net/wireless/intel/iwlwifi/dvm/calib.c data->nrg_value[i] = min(rx_info->beacon_energy_a, val); val 292 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->nrg_th_cck + NRG_STEP_CCK; val 293 drivers/net/wireless/intel/iwlwifi/dvm/calib.c data->nrg_th_cck = min((u32)ranges->min_nrg_cck, val); val 337 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_cck + AUTO_CORR_STEP_CCK; val 339 drivers/net/wireless/intel/iwlwifi/dvm/calib.c min((u32)ranges->auto_corr_max_cck, val); val 341 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK; val 343 drivers/net/wireless/intel/iwlwifi/dvm/calib.c min((u32)ranges->auto_corr_max_cck_mrc, val); val 349 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_cck - AUTO_CORR_STEP_CCK; val 351 drivers/net/wireless/intel/iwlwifi/dvm/calib.c max((u32)ranges->auto_corr_min_cck, val); val 352 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK; val 354 drivers/net/wireless/intel/iwlwifi/dvm/calib.c max((u32)ranges->auto_corr_min_cck_mrc, val); val 365 drivers/net/wireless/intel/iwlwifi/dvm/calib.c u32 val; val 380 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM; val 382 drivers/net/wireless/intel/iwlwifi/dvm/calib.c min((u32)ranges->auto_corr_max_ofdm, val); val 384 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM; val 386 drivers/net/wireless/intel/iwlwifi/dvm/calib.c min((u32)ranges->auto_corr_max_ofdm_mrc, val); val 388 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM; val 390 drivers/net/wireless/intel/iwlwifi/dvm/calib.c min((u32)ranges->auto_corr_max_ofdm_x1, val); val 392 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM; val 394 drivers/net/wireless/intel/iwlwifi/dvm/calib.c min((u32)ranges->auto_corr_max_ofdm_mrc_x1, val); val 403 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM; val 405 drivers/net/wireless/intel/iwlwifi/dvm/calib.c max((u32)ranges->auto_corr_min_ofdm, val); val 407 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM; val 409 drivers/net/wireless/intel/iwlwifi/dvm/calib.c max((u32)ranges->auto_corr_min_ofdm_mrc, val); val 411 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM; val 413 drivers/net/wireless/intel/iwlwifi/dvm/calib.c max((u32)ranges->auto_corr_min_ofdm_x1, val); val 415 drivers/net/wireless/intel/iwlwifi/dvm/calib.c val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM; val 417 drivers/net/wireless/intel/iwlwifi/dvm/calib.c max((u32)ranges->auto_corr_min_ofdm_mrc_x1, val); val 59 drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c u32 val = 0; val 105 drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c val = iwl_trans_read_mem32(priv->trans, sram); val 115 drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c "%02x", (val >> (8 * (3 - offset))) & 0xff); val 118 drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c "%02x ", (val >> (8 * offset)) & 0xff); val 124 drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c val = iwl_trans_read_mem32(priv->trans, sram); val 747 drivers/net/wireless/intel/iwlwifi/dvm/rx.c u32 val, rssi_a, rssi_b, rssi_c, max_rssi; val 750 drivers/net/wireless/intel/iwlwifi/dvm/rx.c val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_AGC_IDX]); val 751 drivers/net/wireless/intel/iwlwifi/dvm/rx.c agc = (val & IWLAGN_OFDM_AGC_MSK) >> IWLAGN_OFDM_AGC_BIT_POS; val 759 drivers/net/wireless/intel/iwlwifi/dvm/rx.c val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_RSSI_AB_IDX]); val 760 drivers/net/wireless/intel/iwlwifi/dvm/rx.c rssi_a = (val & IWLAGN_OFDM_RSSI_INBAND_A_BITMSK) >> val 762 drivers/net/wireless/intel/iwlwifi/dvm/rx.c rssi_b = (val & IWLAGN_OFDM_RSSI_INBAND_B_BITMSK) >> val 764 drivers/net/wireless/intel/iwlwifi/dvm/rx.c val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_RSSI_C_IDX]); val 765 drivers/net/wireless/intel/iwlwifi/dvm/rx.c rssi_c = (val & IWLAGN_OFDM_RSSI_INBAND_C_BITMSK) >> val 122 drivers/net/wireless/intel/iwlwifi/fw/api/filter.h __be32 val; val 1063 drivers/net/wireless/intel/iwlwifi/fw/dbg.c __le32 *val = range->data; val 1074 drivers/net/wireless/intel/iwlwifi/fw/dbg.c *val++ = cpu_to_le32(prph_val); val 1085 drivers/net/wireless/intel/iwlwifi/fw/dbg.c __le32 *val = range->data; val 1092 drivers/net/wireless/intel/iwlwifi/fw/dbg.c *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); val 593 drivers/net/wireless/intel/iwlwifi/fw/file.h __le32 val; val 23 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_PROTO(const struct device *dev, u32 offs, u32 val), val 24 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_ARGS(dev, offs, val), val 28 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __field(u32, val) val 33 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __entry->val = val; val 36 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __get_str(dev), __entry->offs, __entry->val) val 40 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_PROTO(const struct device *dev, u32 offs, u8 val), val 41 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_ARGS(dev, offs, val), val 45 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __field(u8, val) val 50 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __entry->val = val; val 53 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __get_str(dev), __entry->offs, __entry->val) val 57 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_PROTO(const struct device *dev, u32 offs, u32 val), val 58 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_ARGS(dev, offs, val), val 62 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __field(u32, val) val 67 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __entry->val = val; val 70 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __get_str(dev), __entry->offs, __entry->val) val 74 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_PROTO(const struct device *dev, u64 offs, u64 val), val 75 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_ARGS(dev, offs, val), val 79 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __field(u64, val) val 84 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __entry->val = val; val 87 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __get_str(dev), __entry->offs, __entry->val) val 91 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_PROTO(const struct device *dev, u32 offs, u32 val), val 92 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_ARGS(dev, offs, val), val 96 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __field(u32, val) val 101 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __entry->val = val; val 104 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __get_str(dev), __entry->offs, __entry->val) val 108 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_PROTO(const struct device *dev, u64 offs, u64 val), val 109 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_ARGS(dev, offs, val), val 113 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __field(u64, val) val 118 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __entry->val = val; val 121 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __get_str(dev), __entry->offs, __entry->val) val 125 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_PROTO(const struct device *dev, u32 offs, u32 val), val 126 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h TP_ARGS(dev, offs, val), val 130 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __field(u32, val) val 135 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __entry->val = val; val 138 drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h __get_str(dev), __entry->offs, __entry->val) val 103 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val) val 105 drivers/net/wireless/intel/iwlwifi/iwl-io.c trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val); val 106 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_trans_write8(trans, ofs, val); val 110 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val) val 112 drivers/net/wireless/intel/iwlwifi/iwl-io.c trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val); val 113 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_trans_write32(trans, ofs, val); val 117 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val) val 119 drivers/net/wireless/intel/iwlwifi/iwl-io.c trace_iwlwifi_dev_iowrite64(trans->dev, ofs, val); val 120 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_trans_write32(trans, ofs, lower_32_bits(val)); val 121 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_trans_write32(trans, ofs + 4, upper_32_bits(val)); val 127 drivers/net/wireless/intel/iwlwifi/iwl-io.c u32 val = iwl_trans_read32(trans, ofs); val 129 drivers/net/wireless/intel/iwlwifi/iwl-io.c trace_iwlwifi_dev_ioread32(trans->dev, ofs, val); val 130 drivers/net/wireless/intel/iwlwifi/iwl-io.c return val; val 205 drivers/net/wireless/intel/iwlwifi/iwl-io.c u32 val = iwl_trans_read_prph(trans, ofs); val 206 drivers/net/wireless/intel/iwlwifi/iwl-io.c trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val); val 207 drivers/net/wireless/intel/iwlwifi/iwl-io.c return val; val 211 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val) val 213 drivers/net/wireless/intel/iwlwifi/iwl-io.c trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val); val 214 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_trans_write_prph(trans, ofs, val); val 218 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val) val 220 drivers/net/wireless/intel/iwlwifi/iwl-io.c trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val); val 221 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff); val 222 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_write_prph_no_grab(trans, ofs + 4, val >> 32); val 229 drivers/net/wireless/intel/iwlwifi/iwl-io.c u32 val = 0x5a5a5a5a; val 232 drivers/net/wireless/intel/iwlwifi/iwl-io.c val = iwl_read_prph_no_grab(trans, ofs); val 235 drivers/net/wireless/intel/iwlwifi/iwl-io.c return val; val 239 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val) val 244 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_write_prph_no_grab(trans, ofs, val); val 295 drivers/net/wireless/intel/iwlwifi/iwl-io.c u32 val; val 298 drivers/net/wireless/intel/iwlwifi/iwl-io.c val = iwl_read_prph_no_grab(trans, ofs); val 299 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_write_prph_no_grab(trans, ofs, (val & ~mask)); val 64 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val); val 65 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val); val 66 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val); val 91 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val); val 92 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val); val 93 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val); val 130 drivers/net/wireless/intel/iwlwifi/iwl-io.h u32 val) val 133 drivers/net/wireless/intel/iwlwifi/iwl-io.h val); val 137 drivers/net/wireless/intel/iwlwifi/iwl-io.h u32 val) val 139 drivers/net/wireless/intel/iwlwifi/iwl-io.h iwl_write_prph(trans, ofs + trans->trans_cfg->umac_prph_offset, val); val 588 drivers/net/wireless/intel/iwlwifi/iwl-trans.h void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); val 589 drivers/net/wireless/intel/iwlwifi/iwl-trans.h void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); val 592 drivers/net/wireless/intel/iwlwifi/iwl-trans.h void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); val 1137 drivers/net/wireless/intel/iwlwifi/iwl-trans.h static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) val 1139 drivers/net/wireless/intel/iwlwifi/iwl-trans.h trans->ops->write8(trans, ofs, val); val 1142 drivers/net/wireless/intel/iwlwifi/iwl-trans.h static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) val 1144 drivers/net/wireless/intel/iwlwifi/iwl-trans.h trans->ops->write32(trans, ofs, val); val 1158 drivers/net/wireless/intel/iwlwifi/iwl-trans.h u32 val) val 1160 drivers/net/wireless/intel/iwlwifi/iwl-trans.h return trans->ops->write_prph(trans, ofs, val); val 1193 drivers/net/wireless/intel/iwlwifi/iwl-trans.h u32 val) val 1195 drivers/net/wireless/intel/iwlwifi/iwl-trans.h return iwl_trans_write_mem(trans, addr, &val, 1); val 67 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c enum iwl_dbgfs_pm_mask param, int val) val 79 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "debugfs: set keep_alive= %d sec\n", val); val 80 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (val * MSEC_PER_SEC < 3 * dtimper_msec) val 83 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c val * MSEC_PER_SEC, 3 * dtimper_msec); val 84 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->keep_alive_seconds = val; val 89 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c val ? "enabled" : "disabled"); val 90 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->skip_over_dtim = val; val 93 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "skip_dtim_periods=%d\n", val); val 94 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->skip_dtim_periods = val; val 97 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "rx_data_timeout=%d\n", val); val 98 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->rx_data_timeout = val; val 101 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "tx_data_timeout=%d\n", val); val 102 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->tx_data_timeout = val; val 105 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "lprx %s\n", val ? "enabled" : "disabled"); val 106 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->lprx_ena = val; val 109 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "lprx_rssi_threshold=%d\n", val); val 110 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->lprx_rssi_threshold = val; val 113 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "snooze_enable=%d\n", val); val 114 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->snooze_ena = val; val 117 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "uapsd_misbehaving_enable=%d\n", val); val 118 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->uapsd_misbehaving = val; val 121 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c IWL_DEBUG_POWER(mvm, "use_ps_poll=%d\n", val); val 122 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->use_ps_poll = val; val 133 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c int val, ret; val 136 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 11, "%d", &val) != 1) val 140 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 15, "%d", &val) != 1) val 144 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 18, "%d", &val) != 1) val 148 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 16, "%d", &val) != 1) val 152 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 16, "%d", &val) != 1) val 156 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 5, "%d", &val) != 1) val 160 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 20, "%d", &val) != 1) val 162 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (val > POWER_LPRX_RSSI_THRESHOLD_MAX || val < val 167 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 14, "%d", &val) != 1) val 171 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 18, "%d", &val) != 1) val 175 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c if (sscanf(buf + 12, "%d", &val) != 1) val 183 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c iwl_dbgfs_update_pm(mvm, vif, param, val); val 530 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c int ret, val; val 536 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c if (sscanf(buf + 21, "%d", &val) != 1) val 538 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c mvm->disable_power_off = val; val 540 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c if (sscanf(buf + 21, "%d", &val) != 1) val 542 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c mvm->disable_power_off_d3 = val; val 1430 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c be32_to_cpu(attr->val), val 1471 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c attr->val = cpu_to_be32(value); val 141 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .val = cpu_to_be32(0x08060001), val 167 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .val = cpu_to_be32(0x00440000), val 1806 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c attr->val = vif->bss_conf.arp_addr_list[0]; val 1809 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c attr->val = *(__be32 *)&vif->addr[2]; val 159 drivers/net/wireless/intel/iwlwifi/mvm/rx.c u32 val; val 161 drivers/net/wireless/intel/iwlwifi/mvm/rx.c val = val 163 drivers/net/wireless/intel/iwlwifi/mvm/rx.c energy_a = (val & IWL_RX_INFO_ENERGY_ANT_A_MSK) >> val 166 drivers/net/wireless/intel/iwlwifi/mvm/rx.c energy_b = (val & IWL_RX_INFO_ENERGY_ANT_B_MSK) >> val 169 drivers/net/wireless/intel/iwlwifi/mvm/rx.c energy_c = (val & IWL_RX_INFO_ENERGY_ANT_C_MSK) >> val 505 drivers/net/wireless/intel/iwlwifi/mvm/utils.c u32 val, base = mvm->trans->dbg.lmac_error_event_table[lmac_num]; val 525 drivers/net/wireless/intel/iwlwifi/mvm/utils.c val = iwl_trans_read_mem32(trans, base); val 526 drivers/net/wireless/intel/iwlwifi/mvm/utils.c if (((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50)) { val 1655 drivers/net/wireless/intel/iwlwifi/pcie/rx.c u32 val = 0; val 1673 drivers/net/wireless/intel/iwlwifi/pcie/rx.c val |= read; val 1686 drivers/net/wireless/intel/iwlwifi/pcie/rx.c if (val == 0xffffffff) val 1687 drivers/net/wireless/intel/iwlwifi/pcie/rx.c val = 0; val 1696 drivers/net/wireless/intel/iwlwifi/pcie/rx.c if (val & 0xC0000) val 1697 drivers/net/wireless/intel/iwlwifi/pcie/rx.c val |= 0x8000; val 1699 drivers/net/wireless/intel/iwlwifi/pcie/rx.c inta = (0xff & val) | ((0xff00 & val) << 16); val 2037 drivers/net/wireless/intel/iwlwifi/pcie/rx.c u32 val; val 2047 drivers/net/wireless/intel/iwlwifi/pcie/rx.c val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; val 2049 drivers/net/wireless/intel/iwlwifi/pcie/rx.c val |= CSR_DRAM_INT_TBL_ENABLE | val 2053 drivers/net/wireless/intel/iwlwifi/pcie/rx.c IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); val 2055 drivers/net/wireless/intel/iwlwifi/pcie/rx.c iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); val 274 drivers/net/wireless/intel/iwlwifi/pcie/trans.c static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) val 276 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); val 791 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 val, last_read_idx = 0; val 824 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); val 825 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val = val | (sec_num << shift_param); val 826 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); val 926 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 val = le32_to_cpu(dest->reg_ops[i].val); val 930 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_write32(trans, addr, val); val 933 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_set_bit(trans, addr, BIT(val)); val 936 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_clear_bit(trans, addr, BIT(val)); val 939 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_write_prph(trans, addr, val); val 942 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_set_bits_prph(trans, addr, BIT(val)); val 945 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_clear_bits_prph(trans, addr, BIT(val)); val 948 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (iwl_read_prph(trans, addr) & BIT(val)) { val 951 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val, addr); val 1136 drivers/net/wireless/intel/iwlwifi/pcie/trans.c int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; val 1152 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); val 1163 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 val, idx; val 1171 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val = BIT(MSIX_FH_INT_CAUSES_Q(0)); val 1175 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); val 1177 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); val 1179 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val = MSIX_FH_INT_CAUSES_Q(0); val 1181 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val |= MSIX_NON_AUTO_CLEAR_CAUSE; val 1182 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); val 1185 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); val 1555 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 val; val 1602 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val = iwl_read32(trans, CSR_RESET); val 1603 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (val & CSR_RESET_REG_FLAG_NEVO_RESET) val 1888 drivers/net/wireless/intel/iwlwifi/pcie/trans.c static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) val 1890 drivers/net/wireless/intel/iwlwifi/pcie/trans.c writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); val 1893 drivers/net/wireless/intel/iwlwifi/pcie/trans.c static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) val 1895 drivers/net/wireless/intel/iwlwifi/pcie/trans.c writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); val 1921 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 val) val 1927 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); val 3010 drivers/net/wireless/intel/iwlwifi/pcie/trans.c __le32 *val; val 3015 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val = (void *)(*data)->data; val 3018 drivers/net/wireless/intel/iwlwifi/pcie/trans.c *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); val 3030 drivers/net/wireless/intel/iwlwifi/pcie/trans.c __le32 *val; val 3038 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val = (void *)(*data)->data; val 3043 drivers/net/wireless/intel/iwlwifi/pcie/trans.c *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); val 3048 drivers/net/wireless/intel/iwlwifi/pcie/trans.c *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, val 23 drivers/net/wireless/intersil/hostap/hostap.h int hostap_set_word(struct net_device *dev, int rid, u16 val); val 24 drivers/net/wireless/intersil/hostap/hostap.h int hostap_set_string(struct net_device *dev, int rid, const char *val); val 40 drivers/net/wireless/intersil/hostap/hostap.h int hostap_set_hostapd(local_info_t *local, int val, int rtnl_locked); val 41 drivers/net/wireless/intersil/hostap/hostap.h int hostap_set_hostapd_sta(local_info_t *local, int val, int rtnl_locked); val 327 drivers/net/wireless/intersil/hostap/hostap_cs.c u8 val; val 333 drivers/net/wireless/intersil/hostap/hostap_cs.c res = pcmcia_read_config_byte(hw_priv->link, CISREG_COR, &val); val 340 drivers/net/wireless/intersil/hostap/hostap_cs.c val); val 342 drivers/net/wireless/intersil/hostap/hostap_cs.c val |= COR_SOFT_RESET; val 343 drivers/net/wireless/intersil/hostap/hostap_cs.c res = pcmcia_write_config_byte(hw_priv->link, CISREG_COR, val); val 352 drivers/net/wireless/intersil/hostap/hostap_cs.c val &= ~COR_SOFT_RESET; val 354 drivers/net/wireless/intersil/hostap/hostap_cs.c val |= COR_IREQ_ENA; val 355 drivers/net/wireless/intersil/hostap/hostap_cs.c res = pcmcia_write_config_byte(hw_priv->link, CISREG_COR, val); val 4 drivers/net/wireless/intersil/hostap/hostap_download.c u16 val, reg; val 37 drivers/net/wireless/intersil/hostap/hostap_download.c val = HFA384X_INW(HFA384X_CONTROL_OFF); val 44 drivers/net/wireless/intersil/hostap/hostap_download.c if ((val & HFA384X_AUX_PORT_MASK) != HFA384X_AUX_PORT_DISABLED) val 46 drivers/net/wireless/intersil/hostap/hostap_download.c val &= ~HFA384X_AUX_PORT_MASK; val 47 drivers/net/wireless/intersil/hostap/hostap_download.c val |= HFA384X_AUX_PORT_ENABLE; val 53 drivers/net/wireless/intersil/hostap/hostap_download.c if ((val & HFA384X_AUX_PORT_MASK) != HFA384X_AUX_PORT_ENABLED) val 55 drivers/net/wireless/intersil/hostap/hostap_download.c val &= ~HFA384X_AUX_PORT_MASK; val 56 drivers/net/wireless/intersil/hostap/hostap_download.c val |= HFA384X_AUX_PORT_DISABLE; val 58 drivers/net/wireless/intersil/hostap/hostap_download.c HFA384X_OUTW(val, HFA384X_CONTROL_OFF); val 64 drivers/net/wireless/intersil/hostap/hostap_download.c val = HFA384X_INW(HFA384X_CONTROL_OFF); val 65 drivers/net/wireless/intersil/hostap/hostap_download.c val &= HFA384X_AUX_PORT_MASK; val 67 drivers/net/wireless/intersil/hostap/hostap_download.c if ((enable && val == HFA384X_AUX_PORT_ENABLED) || val 68 drivers/net/wireless/intersil/hostap/hostap_download.c (!enable && val == HFA384X_AUX_PORT_DISABLED)) val 1896 drivers/net/wireless/intersil/hostap/hostap_hw.c u16 val, val2, val3; val 1900 drivers/net/wireless/intersil/hostap/hostap_hw.c val = HFA384X_INW(reg); val 1904 drivers/net/wireless/intersil/hostap/hostap_hw.c if (val == val2 && val == val3) val 1905 drivers/net/wireless/intersil/hostap/hostap_hw.c return val; val 1909 drivers/net/wireless/intersil/hostap/hostap_hw.c dev->name, i, reg, val, val2, val3); val 1910 drivers/net/wireless/intersil/hostap/hostap_hw.c if ((val == val2 || val == val3) && val != 0) val 1911 drivers/net/wireless/intersil/hostap/hostap_hw.c return val; val 1916 drivers/net/wireless/intersil/hostap/hostap_hw.c "%04x (%04x %04x %04x)\n", dev->name, reg, val, val2, val3); val 1917 drivers/net/wireless/intersil/hostap/hostap_hw.c return val; val 3001 drivers/net/wireless/intersil/hostap/hostap_hw.c u16 val; val 3018 drivers/net/wireless/intersil/hostap/hostap_hw.c val = entry->aid; val 3020 drivers/net/wireless/intersil/hostap/hostap_hw.c val |= 0x8000; val 3021 drivers/net/wireless/intersil/hostap/hostap_hw.c if (hostap_set_word(local->dev, HFA384X_RID_CNFTIMCTRL, val)) { val 132 drivers/net/wireless/intersil/hostap/hostap_info.c u16 val; val 149 drivers/net/wireless/intersil/hostap/hostap_info.c val = buf[0] | (buf[1] << 8); val 150 drivers/net/wireless/intersil/hostap/hostap_info.c if (!non_sta_mode || val != HFA384X_LINKSTATUS_DISCONNECTED) { val 152 drivers/net/wireless/intersil/hostap/hostap_info.c local->dev->name, val, hfa384x_linkstatus_str(val)); val 163 drivers/net/wireless/intersil/hostap/hostap_info.c local->prev_link_status = val; val 418 drivers/net/wireless/intersil/hostap/hostap_info.c int val = local->prev_link_status; val 423 drivers/net/wireless/intersil/hostap/hostap_info.c val == HFA384X_LINKSTATUS_CONNECTED || val 424 drivers/net/wireless/intersil/hostap/hostap_info.c val == HFA384X_LINKSTATUS_AP_CHANGE || val 425 drivers/net/wireless/intersil/hostap/hostap_info.c val == HFA384X_LINKSTATUS_AP_IN_RANGE; val 83 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 93 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = le16_to_cpu(*(__le16 *) buf); /* string length */ val 95 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (len - 2 < val || val > 10) val 98 drivers/net/wireless/intersil/hostap/hostap_ioctl.c memcpy(rates, buf + 2, val); val 99 drivers/net/wireless/intersil/hostap/hostap_ioctl.c return val; val 234 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 270 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->get_rid(dev, HFA384X_RID_CNFWEPFLAGS, &val, 2, 1) < 0) val 275 drivers/net/wireless/intersil/hostap/hostap_ioctl.c le16_to_cpus(&val); val 276 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (val & HFA384X_WEPFLAGS_PRIVACYINVOKED) val 280 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (val & HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED) val 397 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 405 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->get_rid(dev, HFA384X_RID_TXRATECONTROL, &val, 2, 1) < val 409 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if ((val & 0x1) && (val > 1)) val 424 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->get_rid(dev, HFA384X_RID_CURRENTTXRATE, &val, 2, 1) < val 428 drivers/net/wireless/intersil/hostap/hostap_ioctl.c switch (val) { val 479 drivers/net/wireless/intersil/hostap/hostap_ioctl.c __le16 val; val 485 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->get_rid(dev, HFA384X_RID_CNFSYSTEMSCALE, &val, 2, 1) < val 489 drivers/net/wireless/intersil/hostap/hostap_ioctl.c sens->value = le16_to_cpu(val); val 544 drivers/net/wireless/intersil/hostap/hostap_ioctl.c __le16 val; val 550 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = cpu_to_le16(2347); val 554 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = cpu_to_le16(rts->value); val 556 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->set_rid(dev, HFA384X_RID_RTSTHRESHOLD, &val, 2) || val 571 drivers/net/wireless/intersil/hostap/hostap_ioctl.c __le16 val; val 576 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->get_rid(dev, HFA384X_RID_RTSTHRESHOLD, &val, 2, 1) < val 580 drivers/net/wireless/intersil/hostap/hostap_ioctl.c rts->value = le16_to_cpu(val); val 594 drivers/net/wireless/intersil/hostap/hostap_ioctl.c __le16 val; val 600 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = cpu_to_le16(2346); val 604 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = cpu_to_le16(rts->value & ~0x1); /* even numbers only */ val 607 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->set_rid(dev, HFA384X_RID_FRAGMENTATIONTHRESHOLD, &val, val 621 drivers/net/wireless/intersil/hostap/hostap_ioctl.c __le16 val; val 627 drivers/net/wireless/intersil/hostap/hostap_ioctl.c &val, 2, 1) < 0) val 630 drivers/net/wireless/intersil/hostap/hostap_ioctl.c rts->value = le16_to_cpu(val); val 786 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 793 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = le16_to_cpu(*(__le16 *) name); val 794 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (len > MAX_NAME_LEN + 2 || len < 0 || val > MAX_NAME_LEN) val 797 drivers/net/wireless/intersil/hostap/hostap_ioctl.c name[val + 2] = '\0'; val 798 drivers/net/wireless/intersil/hostap/hostap_ioctl.c data->length = val + 1; val 799 drivers/net/wireless/intersil/hostap/hostap_ioctl.c memcpy(nickname, name + 2, val + 1); val 848 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 853 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->get_rid(dev, HFA384X_RID_CURRENTCHANNEL, &val, 2, 1) < val 857 drivers/net/wireless/intersil/hostap/hostap_ioctl.c le16_to_cpus(&val); val 858 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (val < 1 || val > FREQ_COUNT) val 861 drivers/net/wireless/intersil/hostap/hostap_ioctl.c freq->m = freq_list[val - 1] * 100000; val 928 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 946 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = le16_to_cpu(*(__le16 *) ssid); val 947 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (len > MAX_SSID_LEN + 2 || len < 0 || val > MAX_SSID_LEN) { val 950 drivers/net/wireless/intersil/hostap/hostap_ioctl.c data->length = val; val 966 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 1002 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = 0; val 1005 drivers/net/wireless/intersil/hostap/hostap_ioctl.c range->freq[val].i = i + 1; val 1006 drivers/net/wireless/intersil/hostap/hostap_ioctl.c range->freq[val].m = freq_list[i] * 100000; val 1007 drivers/net/wireless/intersil/hostap/hostap_ioctl.c range->freq[val].e = 1; val 1008 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val++; val 1010 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (val == IW_MAX_FREQUENCIES) val 1013 drivers/net/wireless/intersil/hostap/hostap_ioctl.c range->num_frequency = val; val 1475 drivers/net/wireless/intersil/hostap/hostap_ioctl.c static int prism2_txpower_hfa386x_to_dBm(u16 val) val 1479 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (val > 255) val 1480 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = 255; val 1482 drivers/net/wireless/intersil/hostap/hostap_ioctl.c tmp = val; val 1488 drivers/net/wireless/intersil/hostap/hostap_ioctl.c static u16 prism2_txpower_dBm_to_hfa386x(int val) val 1492 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (val > 20) val 1494 drivers/net/wireless/intersil/hostap/hostap_ioctl.c else if (val < -43) val 1497 drivers/net/wireless/intersil/hostap/hostap_ioctl.c tmp = val; val 1515 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 1523 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = 0xff; /* use all standby and sleep modes */ val 1526 drivers/net/wireless/intersil/hostap/hostap_ioctl.c &val, NULL); val 1535 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = 0; /* disable all standby and sleep modes */ val 1537 drivers/net/wireless/intersil/hostap/hostap_ioctl.c HFA386X_CR_A_D_TEST_MODES2, &val, NULL); val 1546 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = HFA384X_TEST_CFG_BIT_ALC; val 1548 drivers/net/wireless/intersil/hostap/hostap_ioctl.c (HFA384X_TEST_CFG_BITS << 8), 1, &val, NULL); val 1555 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = HFA384X_TEST_CFG_BIT_ALC; val 1557 drivers/net/wireless/intersil/hostap/hostap_ioctl.c (HFA384X_TEST_CFG_BITS << 8), 0, &val, NULL); val 1575 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = prism2_txpower_dBm_to_hfa386x(local->txpower); val 1577 drivers/net/wireless/intersil/hostap/hostap_ioctl.c HFA386X_CR_MANUAL_TX_POWER, &val, NULL)) val 2326 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 val; val 2374 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = HFA384X_TEST_CFG_BIT_ALC; val 2377 drivers/net/wireless/intersil/hostap/hostap_ioctl.c value == 0 ? 0 : 1, &val, NULL); val 2881 drivers/net/wireless/intersil/hostap/hostap_ioctl.c u16 cr, val; val 2887 drivers/net/wireless/intersil/hostap/hostap_ioctl.c val = *(extra + 1); val 2888 drivers/net/wireless/intersil/hostap/hostap_ioctl.c if (local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, cr, &val, NULL)) val 283 drivers/net/wireless/intersil/hostap/hostap_main.c int hostap_set_word(struct net_device *dev, int rid, u16 val) val 286 drivers/net/wireless/intersil/hostap/hostap_main.c __le16 tmp = cpu_to_le16(val); val 292 drivers/net/wireless/intersil/hostap/hostap_main.c int hostap_set_string(struct net_device *dev, int rid, const char *val) val 299 drivers/net/wireless/intersil/hostap/hostap_main.c len = strlen(val); val 304 drivers/net/wireless/intersil/hostap/hostap_main.c memcpy(buf + 2, val, len); val 328 drivers/net/wireless/intersil/hostap/hostap_main.c u16 val, old_val; val 342 drivers/net/wireless/intersil/hostap/hostap_main.c if (local->func->get_rid(local->dev, HFA384X_RID_CNFWEPFLAGS, &val, 2, val 347 drivers/net/wireless/intersil/hostap/hostap_main.c le16_to_cpus(&val); val 348 drivers/net/wireless/intersil/hostap/hostap_main.c old_val = val; val 351 drivers/net/wireless/intersil/hostap/hostap_main.c val |= HFA384X_WEPFLAGS_PRIVACYINVOKED; val 353 drivers/net/wireless/intersil/hostap/hostap_main.c val &= ~HFA384X_WEPFLAGS_PRIVACYINVOKED; val 357 drivers/net/wireless/intersil/hostap/hostap_main.c val &= ~HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED; val 359 drivers/net/wireless/intersil/hostap/hostap_main.c val |= HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED; val 363 drivers/net/wireless/intersil/hostap/hostap_main.c val |= HFA384X_WEPFLAGS_HOSTENCRYPT; val 365 drivers/net/wireless/intersil/hostap/hostap_main.c val &= ~HFA384X_WEPFLAGS_HOSTENCRYPT; val 368 drivers/net/wireless/intersil/hostap/hostap_main.c val |= HFA384X_WEPFLAGS_HOSTDECRYPT; val 370 drivers/net/wireless/intersil/hostap/hostap_main.c val &= ~HFA384X_WEPFLAGS_HOSTDECRYPT; val 372 drivers/net/wireless/intersil/hostap/hostap_main.c if (val != old_val && val 373 drivers/net/wireless/intersil/hostap/hostap_main.c hostap_set_word(local->dev, HFA384X_RID_CNFWEPFLAGS, val)) { val 375 drivers/net/wireless/intersil/hostap/hostap_main.c val); val 420 drivers/net/wireless/intersil/hostap/hostap_main.c u16 val; val 426 drivers/net/wireless/intersil/hostap/hostap_main.c NULL, &val) == 0) { val 427 drivers/net/wireless/intersil/hostap/hostap_main.c val &= ~(BIT(2) | BIT(1)); val 430 drivers/net/wireless/intersil/hostap/hostap_main.c val |= BIT(1); val 435 drivers/net/wireless/intersil/hostap/hostap_main.c val |= BIT(2); val 440 drivers/net/wireless/intersil/hostap/hostap_main.c HFA386X_CR_TX_CONFIGURE, &val, NULL)) { val 450 drivers/net/wireless/intersil/hostap/hostap_main.c NULL, &val) == 0) { val 451 drivers/net/wireless/intersil/hostap/hostap_main.c val &= ~(BIT(1) | BIT(0)); val 456 drivers/net/wireless/intersil/hostap/hostap_main.c val |= BIT(0); val 459 drivers/net/wireless/intersil/hostap/hostap_main.c val |= BIT(0) | BIT(1); val 464 drivers/net/wireless/intersil/hostap/hostap_main.c HFA386X_CR_RX_CONFIGURE, &val, NULL)) { val 477 drivers/net/wireless/intersil/hostap/hostap_main.c u16 val; val 481 drivers/net/wireless/intersil/hostap/hostap_main.c val = HFA384X_ROAMING_HOST; val 484 drivers/net/wireless/intersil/hostap/hostap_main.c val = HFA384X_ROAMING_DISABLED; val 488 drivers/net/wireless/intersil/hostap/hostap_main.c val = HFA384X_ROAMING_FIRMWARE; val 492 drivers/net/wireless/intersil/hostap/hostap_main.c return hostap_set_word(local->dev, HFA384X_RID_CNFROAMINGMODE, val); val 498 drivers/net/wireless/intersil/hostap/hostap_main.c int val = local->auth_algs; val 505 drivers/net/wireless/intersil/hostap/hostap_main.c val != PRISM2_AUTH_OPEN && val != PRISM2_AUTH_SHARED_KEY) val 506 drivers/net/wireless/intersil/hostap/hostap_main.c val = PRISM2_AUTH_OPEN; val 508 drivers/net/wireless/intersil/hostap/hostap_main.c if (hostap_set_word(local->dev, HFA384X_RID_CNFAUTHENTICATION, val)) { val 937 drivers/net/wireless/intersil/hostap/hostap_main.c int hostap_set_hostapd(local_info_t *local, int val, int rtnl_locked) val 941 drivers/net/wireless/intersil/hostap/hostap_main.c if (val < 0 || val > 1) val 944 drivers/net/wireless/intersil/hostap/hostap_main.c if (local->hostapd == val) val 947 drivers/net/wireless/intersil/hostap/hostap_main.c if (val) { val 962 drivers/net/wireless/intersil/hostap/hostap_main.c int hostap_set_hostapd_sta(local_info_t *local, int val, int rtnl_locked) val 966 drivers/net/wireless/intersil/hostap/hostap_main.c if (val < 0 || val > 1) val 969 drivers/net/wireless/intersil/hostap/hostap_main.c if (local->hostapd_sta == val) val 972 drivers/net/wireless/intersil/hostap/hostap_main.c if (val) { val 1064 drivers/net/wireless/intersil/hostap/hostap_main.c __le16 val = cpu_to_le16(reason); val 1072 drivers/net/wireless/intersil/hostap/hostap_main.c (u8 *) &val, 2); val 366 drivers/net/wireless/intersil/orinoco/hermes.h __le16 val[16]; val 422 drivers/net/wireless/intersil/orinoco/hermes.h #define hermes_write_reg(hw, off, val) \ val 423 drivers/net/wireless/intersil/orinoco/hermes.h (iowrite16((val), (hw)->iobase + ((off) << (hw)->reg_spacing))) val 425 drivers/net/wireless/intersil/orinoco/hermes.h #define hermes_write_regn(hw, name, val) \ val 426 drivers/net/wireless/intersil/orinoco/hermes.h hermes_write_reg((hw), HERMES_##name, (val)) val 319 drivers/net/wireless/intersil/orinoco/hermes_dld.c u8 val[length]; \ val 309 drivers/net/wireless/intersil/orinoco/hw.c memcpy(priv->nick, &nickbuf.val, len); val 529 drivers/net/wireless/intersil/orinoco/hw.c memcpy(&idbuf.val, priv->desired_essid, sizeof(idbuf.val)); val 550 drivers/net/wireless/intersil/orinoco/hw.c memcpy(&idbuf.val, priv->nick, sizeof(idbuf.val)); val 743 drivers/net/wireless/intersil/orinoco/hw.c u16 val; val 746 drivers/net/wireless/intersil/orinoco/hw.c HERMES_RID_CURRENTTXRATE, &val); val 757 drivers/net/wireless/intersil/orinoco/hw.c if (val == 6) val 760 drivers/net/wireless/intersil/orinoco/hw.c *bitrate = val * 1000000; val 765 drivers/net/wireless/intersil/orinoco/hw.c if (bitrate_table[i].intersil_txratectrl == val) { val 772 drivers/net/wireless/intersil/orinoco/hw.c priv->ndev->name, val); val 1119 drivers/net/wireless/intersil/orinoco/hw.c char *p = (char *)(&essidbuf.val); val 1211 drivers/net/wireless/intersil/orinoco/hw.c unsigned char *p = (unsigned char *)&list.val; val 1286 drivers/net/wireless/intersil/orinoco/hw.c memcpy(idbuf.val, ssid->ssid, len); val 496 drivers/net/wireless/intersil/orinoco/wext.c u16 val; val 506 drivers/net/wireless/intersil/orinoco/wext.c HERMES_RID_CNFSYSTEMSCALE, &val); val 512 drivers/net/wireless/intersil/orinoco/wext.c srq->value = val; val 524 drivers/net/wireless/intersil/orinoco/wext.c int val = srq->value; val 530 drivers/net/wireless/intersil/orinoco/wext.c if ((val < 1) || (val > 3)) val 535 drivers/net/wireless/intersil/orinoco/wext.c priv->ap_density = val; val 1129 drivers/net/wireless/intersil/orinoco/wext.c int val = *((int *) extra); val 1135 drivers/net/wireless/intersil/orinoco/wext.c priv->ibss_port = val; val 1150 drivers/net/wireless/intersil/orinoco/wext.c int *val = (int *) extra; val 1152 drivers/net/wireless/intersil/orinoco/wext.c *val = priv->ibss_port; val 1162 drivers/net/wireless/intersil/orinoco/wext.c int val = *((int *) extra); val 1169 drivers/net/wireless/intersil/orinoco/wext.c switch (val) { val 1208 drivers/net/wireless/intersil/orinoco/wext.c int *val = (int *) extra; val 1210 drivers/net/wireless/intersil/orinoco/wext.c *val = priv->prefer_port3; val 1221 drivers/net/wireless/intersil/orinoco/wext.c int val; val 1231 drivers/net/wireless/intersil/orinoco/wext.c val = *((int *) extra); val 1236 drivers/net/wireless/intersil/orinoco/wext.c if (val) val 1252 drivers/net/wireless/intersil/orinoco/wext.c int *val = (int *) extra; val 1257 drivers/net/wireless/intersil/orinoco/wext.c *val = priv->preamble; val 87 drivers/net/wireless/intersil/p54/p54pci.h #define P54P_WRITE(r, val) __raw_writel((__force u32)(__le32)(val), &priv->map->r) val 105 drivers/net/wireless/intersil/p54/p54spi.c __le32 val; val 107 drivers/net/wireless/intersil/p54/p54spi.c p54spi_spi_read(priv, addr, &val, sizeof(val)); val 109 drivers/net/wireless/intersil/p54/p54spi.c return le32_to_cpu(val); val 112 drivers/net/wireless/intersil/p54/p54spi.c static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val) val 114 drivers/net/wireless/intersil/p54/p54spi.c p54spi_spi_write(priv, addr, &val, sizeof(val)); val 117 drivers/net/wireless/intersil/p54/p54spi.c static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val) val 119 drivers/net/wireless/intersil/p54/p54spi.c p54spi_spi_write(priv, addr, &val, sizeof(val)); val 279 drivers/net/wireless/intersil/p54/p54spi.c static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val) val 281 drivers/net/wireless/intersil/p54/p54spi.c p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val)); val 345 drivers/net/wireless/intersil/p54/p54usb.c reg->val = cpu_to_le32(ISL38XX_DEV_INT_DATA); val 395 drivers/net/wireless/intersil/p54/p54usb.c __le32 addr, __le32 val) val 407 drivers/net/wireless/intersil/p54/p54usb.c buf->val = val; val 414 drivers/net/wireless/intersil/p54/p54usb.c __le32 addr, __le32 *val) val 439 drivers/net/wireless/intersil/p54/p54usb.c *val = *reg; val 96 drivers/net/wireless/intersil/p54/p54usb.h __le32 val; val 63 drivers/net/wireless/intersil/prism54/isl_38xx.h isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset) val 65 drivers/net/wireless/intersil/prism54/isl_38xx.h writel(val, base + offset); val 407 drivers/net/wireless/mac80211_hwsim.c u32 val; val 415 drivers/net/wireless/mac80211_hwsim.c val = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_TEST]); val 416 drivers/net/wireless/mac80211_hwsim.c wiphy_dbg(wiphy, "%s: test=%u\n", __func__, val); val 432 drivers/net/wireless/mac80211_hwsim.c nla_put_u32(skb, QCA_WLAN_VENDOR_ATTR_TEST, val + 1); val 446 drivers/net/wireless/mac80211_hwsim.c nla_put_u32(skb, QCA_WLAN_VENDOR_ATTR_TEST, val + 2); val 708 drivers/net/wireless/mac80211_hwsim.c static int hwsim_fops_ps_read(void *dat, u64 *val) val 711 drivers/net/wireless/mac80211_hwsim.c *val = data->ps; val 715 drivers/net/wireless/mac80211_hwsim.c static int hwsim_fops_ps_write(void *dat, u64 val) val 720 drivers/net/wireless/mac80211_hwsim.c if (val != PS_DISABLED && val != PS_ENABLED && val != PS_AUTO_POLL && val 721 drivers/net/wireless/mac80211_hwsim.c val != PS_MANUAL_POLL) val 724 drivers/net/wireless/mac80211_hwsim.c if (val == PS_MANUAL_POLL) { val 735 drivers/net/wireless/mac80211_hwsim.c data->ps = val; val 738 drivers/net/wireless/mac80211_hwsim.c if (old_ps == PS_DISABLED && val != PS_DISABLED) { val 742 drivers/net/wireless/mac80211_hwsim.c } else if (old_ps != PS_DISABLED && val == PS_DISABLED) { val 755 drivers/net/wireless/mac80211_hwsim.c static int hwsim_write_simulate_radar(void *dat, u64 val) val 767 drivers/net/wireless/mac80211_hwsim.c static int hwsim_fops_group_read(void *dat, u64 *val) val 770 drivers/net/wireless/mac80211_hwsim.c *val = data->group; val 774 drivers/net/wireless/mac80211_hwsim.c static int hwsim_fops_group_write(void *dat, u64 val) val 777 drivers/net/wireless/mac80211_hwsim.c data->group = val; val 418 drivers/net/wireless/marvell/libertas/cmd.c int lbs_set_snmp_mib(struct lbs_private *priv, u32 oid, u16 val) val 431 drivers/net/wireless/marvell/libertas/cmd.c cmd.value[0] = val; val 439 drivers/net/wireless/marvell/libertas/cmd.c *((__le16 *)(&cmd.value)) = cpu_to_le16(val); val 448 drivers/net/wireless/marvell/libertas/cmd.c le16_to_cpu(cmd.oid), le16_to_cpu(cmd.bufsize), val); val 106 drivers/net/wireless/marvell/libertas/cmd.h int lbs_set_snmp_mib(struct lbs_private *priv, u32 oid, u16 val); val 441 drivers/net/wireless/marvell/libertas/debugfs.c u32 val = 0; val 446 drivers/net/wireless/marvell/libertas/debugfs.c ret = lbs_get_reg(priv, CMD_MAC_REG_ACCESS, priv->mac_offset, &val); val 450 drivers/net/wireless/marvell/libertas/debugfs.c priv->mac_offset, val); val 511 drivers/net/wireless/marvell/libertas/debugfs.c u32 val; val 516 drivers/net/wireless/marvell/libertas/debugfs.c ret = lbs_get_reg(priv, CMD_BBP_REG_ACCESS, priv->bbp_offset, &val); val 520 drivers/net/wireless/marvell/libertas/debugfs.c priv->bbp_offset, val); val 583 drivers/net/wireless/marvell/libertas/debugfs.c u32 val; val 588 drivers/net/wireless/marvell/libertas/debugfs.c ret = lbs_get_reg(priv, CMD_RF_REG_ACCESS, priv->rf_offset, &val); val 592 drivers/net/wireless/marvell/libertas/debugfs.c priv->rf_offset, val); val 809 drivers/net/wireless/marvell/libertas/debugfs.c int val = 0; val 826 drivers/net/wireless/marvell/libertas/debugfs.c val = *((u8 *) d[i].addr); val 828 drivers/net/wireless/marvell/libertas/debugfs.c val = *((u16 *) d[i].addr); val 830 drivers/net/wireless/marvell/libertas/debugfs.c val = *((u32 *) d[i].addr); val 832 drivers/net/wireless/marvell/libertas/debugfs.c val = *((u64 *) d[i].addr); val 834 drivers/net/wireless/marvell/libertas/debugfs.c pos += sprintf(p + pos, "%s=%d\n", d[i].name, val); val 98 drivers/net/wireless/marvell/libertas/if_cs.c unsigned int val = ioread8(card->iobase + reg); val 100 drivers/net/wireless/marvell/libertas/if_cs.c printk(KERN_INFO "inb %08x<%02x\n", reg, val); val 101 drivers/net/wireless/marvell/libertas/if_cs.c return val; val 105 drivers/net/wireless/marvell/libertas/if_cs.c unsigned int val = ioread16(card->iobase + reg); val 107 drivers/net/wireless/marvell/libertas/if_cs.c printk(KERN_INFO "inw %08x<%04x\n", reg, val); val 108 drivers/net/wireless/marvell/libertas/if_cs.c return val; val 122 drivers/net/wireless/marvell/libertas/if_cs.c static inline void if_cs_write8(struct if_cs_card *card, uint reg, u8 val) val 125 drivers/net/wireless/marvell/libertas/if_cs.c printk(KERN_INFO "outb %08x>%02x\n", reg, val); val 126 drivers/net/wireless/marvell/libertas/if_cs.c iowrite8(val, card->iobase + reg); val 129 drivers/net/wireless/marvell/libertas/if_cs.c static inline void if_cs_write16(struct if_cs_card *card, uint reg, u16 val) val 132 drivers/net/wireless/marvell/libertas/if_cs.c printk(KERN_INFO "outw %08x>%04x\n", reg, val); val 133 drivers/net/wireless/marvell/libertas/if_cs.c iowrite16(val, card->iobase + reg); val 166 drivers/net/wireless/marvell/libertas/if_cs.c u8 val = if_cs_read8(card, addr); val 167 drivers/net/wireless/marvell/libertas/if_cs.c if (val == reg) val 182 drivers/net/wireless/marvell/libertas/if_spi.c static inline int spu_write_u16(struct if_spi_card *card, u16 reg, u16 val) val 186 drivers/net/wireless/marvell/libertas/if_spi.c buff = cpu_to_le16(val); val 253 drivers/net/wireless/marvell/libertas/if_spi.c static inline int spu_read_u16(struct if_spi_card *card, u16 reg, u16 *val) val 260 drivers/net/wireless/marvell/libertas/if_spi.c *val = le16_to_cpup(&buf); val 268 drivers/net/wireless/marvell/libertas/if_spi.c static int spu_read_u32(struct if_spi_card *card, u16 reg, u32 *val) val 275 drivers/net/wireless/marvell/libertas/if_spi.c *val = le32_to_cpup(&buf); val 294 drivers/net/wireless/marvell/libertas/if_spi.c u16 val; val 295 drivers/net/wireless/marvell/libertas/if_spi.c err = spu_read_u16(card, reg, &val); val 299 drivers/net/wireless/marvell/libertas/if_spi.c if ((val & target_mask) == target) val 302 drivers/net/wireless/marvell/libertas/if_spi.c if (val) val 308 drivers/net/wireless/marvell/libertas/if_spi.c __func__, val, target_mask, target); val 322 drivers/net/wireless/marvell/libertas/if_spi.c u32 val = 0; val 323 drivers/net/wireless/marvell/libertas/if_spi.c err = spu_read_u32(card, reg, &val); val 326 drivers/net/wireless/marvell/libertas/if_spi.c if (val == target) val 100 drivers/net/wireless/marvell/libertas/mesh.c ie->val.oui[0] = 0x00; val 101 drivers/net/wireless/marvell/libertas/mesh.c ie->val.oui[1] = 0x50; val 102 drivers/net/wireless/marvell/libertas/mesh.c ie->val.oui[2] = 0x43; val 103 drivers/net/wireless/marvell/libertas/mesh.c ie->val.type = MARVELL_MESH_IE_TYPE; val 104 drivers/net/wireless/marvell/libertas/mesh.c ie->val.subtype = MARVELL_MESH_IE_SUBTYPE; val 105 drivers/net/wireless/marvell/libertas/mesh.c ie->val.version = MARVELL_MESH_IE_VERSION; val 106 drivers/net/wireless/marvell/libertas/mesh.c ie->val.active_protocol_id = MARVELL_MESH_PROTO_ID_HWMP; val 107 drivers/net/wireless/marvell/libertas/mesh.c ie->val.active_metric_id = MARVELL_MESH_METRIC_ID; val 108 drivers/net/wireless/marvell/libertas/mesh.c ie->val.mesh_capability = MARVELL_MESH_CAPABILITY; val 112 drivers/net/wireless/marvell/libertas/mesh.c ie->val.mesh_id_len = mesh_wdev->mesh_id_up_len; val 113 drivers/net/wireless/marvell/libertas/mesh.c memcpy(ie->val.mesh_id, mesh_wdev->ssid, val 118 drivers/net/wireless/marvell/libertas/mesh.c IEEE80211_MAX_SSID_LEN + ie->val.mesh_id_len; val 128 drivers/net/wireless/marvell/libertas/mesh.c action, priv->mesh_tlv, chan, ie->val.mesh_id_len, val 129 drivers/net/wireless/marvell/libertas/mesh.c ie->val.mesh_id); val 529 drivers/net/wireless/marvell/libertas/mesh.c if (defs.meshie.val.mesh_id_len > IEEE80211_MAX_SSID_LEN) { val 531 drivers/net/wireless/marvell/libertas/mesh.c defs.meshie.val.mesh_id_len = IEEE80211_MAX_SSID_LEN; val 534 drivers/net/wireless/marvell/libertas/mesh.c memcpy(buf, defs.meshie.val.mesh_id, defs.meshie.val.mesh_id_len); val 535 drivers/net/wireless/marvell/libertas/mesh.c buf[defs.meshie.val.mesh_id_len] = '\n'; val 536 drivers/net/wireless/marvell/libertas/mesh.c buf[defs.meshie.val.mesh_id_len + 1] = '\0'; val 538 drivers/net/wireless/marvell/libertas/mesh.c return defs.meshie.val.mesh_id_len + 1; val 573 drivers/net/wireless/marvell/libertas/mesh.c memcpy(ie->val.mesh_id, buf, len); val 575 drivers/net/wireless/marvell/libertas/mesh.c ie->val.mesh_id_len = len; val 604 drivers/net/wireless/marvell/libertas/mesh.c return snprintf(buf, 5, "%d\n", defs.meshie.val.active_protocol_id); val 638 drivers/net/wireless/marvell/libertas/mesh.c ie->val.active_protocol_id = datum; val 665 drivers/net/wireless/marvell/libertas/mesh.c return snprintf(buf, 5, "%d\n", defs.meshie.val.active_metric_id); val 699 drivers/net/wireless/marvell/libertas/mesh.c ie->val.active_metric_id = datum; val 726 drivers/net/wireless/marvell/libertas/mesh.c return snprintf(buf, 5, "%d\n", defs.meshie.val.mesh_capability); val 760 drivers/net/wireless/marvell/libertas/mesh.c ie->val.mesh_capability = datum; val 258 drivers/net/wireless/marvell/libertas/types.h struct mrvl_meshie_val val; val 2113 drivers/net/wireless/marvell/mwifiex/pcie.c u32 txlen, tx_blocks = 0, tries, len, val; val 2140 drivers/net/wireless/marvell/mwifiex/pcie.c ret = mwifiex_read_reg(adapter, PCIE_SCRATCH_13_REG, &val); val 2147 drivers/net/wireless/marvell/mwifiex/pcie.c if (val == MWIFIEX_PCIE_FLR_HAPPENS) { val 233 drivers/net/wireless/marvell/mwifiex/sdio.c u8 val; val 236 drivers/net/wireless/marvell/mwifiex/sdio.c val = sdio_readb(card->func, reg, &ret); val 239 drivers/net/wireless/marvell/mwifiex/sdio.c *data = val; val 257 drivers/net/wireless/marvell/mwifiex/util.c long val; val 276 drivers/net/wireless/marvell/mwifiex/util.c val = *((u8 *)addr); val 279 drivers/net/wireless/marvell/mwifiex/util.c val = get_unaligned((u16 *)addr); val 282 drivers/net/wireless/marvell/mwifiex/util.c val = get_unaligned((u32 *)addr); val 285 drivers/net/wireless/marvell/mwifiex/util.c val = get_unaligned((long long *)addr); val 288 drivers/net/wireless/marvell/mwifiex/util.c val = -1; val 292 drivers/net/wireless/marvell/mwifiex/util.c p += sprintf(p, "%#lx ", val); val 96 drivers/net/wireless/marvell/mwifiex/util.h static inline void le16_unaligned_add_cpu(__le16 *var, u16 val) val 98 drivers/net/wireless/marvell/mwifiex/util.h put_unaligned_le16(get_unaligned_le16(var) + val, var); val 8 drivers/net/wireless/mediatek/mt76/debugfs.c mt76_reg_set(void *data, u64 val) val 12 drivers/net/wireless/mediatek/mt76/debugfs.c dev->bus->wr(dev, dev->debugfs_reg, val); val 17 drivers/net/wireless/mediatek/mt76/debugfs.c mt76_reg_get(void *data, u64 *val) val 21 drivers/net/wireless/mediatek/mt76/debugfs.c *val = dev->bus->rr(dev, dev->debugfs_reg); val 50 drivers/net/wireless/mediatek/mt76/debugfs.c s8 *val, int len) val 56 drivers/net/wireless/mediatek/mt76/debugfs.c seq_printf(file, " %2d", val[i]); val 11 drivers/net/wireless/mediatek/mt76/mmio.c u32 val; val 13 drivers/net/wireless/mediatek/mt76/mmio.c val = readl(dev->mmio.regs + offset); val 14 drivers/net/wireless/mediatek/mt76/mmio.c trace_reg_rr(dev, offset, val); val 16 drivers/net/wireless/mediatek/mt76/mmio.c return val; val 19 drivers/net/wireless/mediatek/mt76/mmio.c static void mt76_mmio_wr(struct mt76_dev *dev, u32 offset, u32 val) val 21 drivers/net/wireless/mediatek/mt76/mmio.c trace_reg_wr(dev, offset, val); val 22 drivers/net/wireless/mediatek/mt76/mmio.c writel(val, dev->mmio.regs + offset); val 25 drivers/net/wireless/mediatek/mt76/mmio.c static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val) val 27 drivers/net/wireless/mediatek/mt76/mmio.c val |= mt76_mmio_rr(dev, offset) & ~mask; val 28 drivers/net/wireless/mediatek/mt76/mmio.c mt76_mmio_wr(dev, offset, val); val 29 drivers/net/wireless/mediatek/mt76/mmio.c return val; val 39 drivers/net/wireless/mediatek/mt76/mt76.h void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); val 40 drivers/net/wireless/mediatek/mt76/mt76.h u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); val 541 drivers/net/wireless/mediatek/mt76/mt76.h #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) val 542 drivers/net/wireless/mediatek/mt76/mt76.h #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) val 557 drivers/net/wireless/mediatek/mt76/mt76.h #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) val 558 drivers/net/wireless/mediatek/mt76/mt76.h #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) val 571 drivers/net/wireless/mediatek/mt76/mt76.h bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, val 576 drivers/net/wireless/mediatek/mt76/mt76.h bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, val 630 drivers/net/wireless/mediatek/mt76/mt76.h s8 *val, int len); val 642 drivers/net/wireless/mediatek/mt76/mt76.h static inline int mt76_incr(int val, int size) val 644 drivers/net/wireless/mediatek/mt76/mt76.h return (val + 1) & (size - 1); val 648 drivers/net/wireless/mediatek/mt76/mt76.h static inline int mt76_decr(int val, int size) val 650 drivers/net/wireless/mediatek/mt76/mt76.h return (val - 1) & (size - 1); val 816 drivers/net/wireless/mediatek/mt76/mt76.h u8 req_type, u16 val, u16 offset, val 819 drivers/net/wireless/mediatek/mt76/mt76.h const u16 offset, const u32 val); val 44 drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c mt7603_edcca_set(void *data, u64 val) val 50 drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c dev->ed_monitor_enabled = !!val; val 61 drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c mt7603_edcca_get(void *data, u64 *val) val 65 drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c *val = dev->ed_monitor_enabled; val 40 drivers/net/wireless/mediatek/mt76/mt7603/dma.c u32 val; val 46 drivers/net/wireless/mediatek/mt76/mt7603/dma.c val = le32_to_cpu(txd[1]); val 47 drivers/net/wireless/mediatek/mt76/mt7603/dma.c idx = FIELD_GET(MT_TXD1_WLAN_IDX, val); val 48 drivers/net/wireless/mediatek/mt76/mt7603/dma.c skb->priority = FIELD_GET(MT_TXD1_TID, val); val 58 drivers/net/wireless/mediatek/mt76/mt7603/dma.c val = le32_to_cpu(txd[0]); val 59 drivers/net/wireless/mediatek/mt76/mt7603/dma.c skb_set_queue_mapping(skb, FIELD_GET(MT_TXD0_Q_IDX, val)); val 61 drivers/net/wireless/mediatek/mt76/mt7603/dma.c val &= ~(MT_TXD0_P_IDX | MT_TXD0_Q_IDX); val 62 drivers/net/wireless/mediatek/mt76/mt7603/dma.c val |= FIELD_PREP(MT_TXD0_Q_IDX, MT_TX_HW_QUEUE_MGMT); val 63 drivers/net/wireless/mediatek/mt76/mt7603/dma.c txd[0] = cpu_to_le32(val); val 9 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c u32 val; val 12 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_CTRL); val 13 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val &= ~(MT_EFUSE_CTRL_AIN | val 15 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf); val 16 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val |= MT_EFUSE_CTRL_KICK; val 17 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c mt76_wr(dev, base + MT_EFUSE_CTRL, val); val 24 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_CTRL); val 25 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT || val 26 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c WARN_ON_ONCE(!(val & MT_EFUSE_CTRL_VALID))) { val 32 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_RDATA(i)); val 33 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c put_unaligned_le32(val, data + 4 * i); val 134 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c u16 val = get_unaligned_le16(dev->eeprom.data); val 136 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c switch (val) { val 362 drivers/net/wireless/mediatek/mt76/mt7603/init.c u32 val, addr; val 364 drivers/net/wireless/mediatek/mt76/mt7603/init.c val = MT_LED_STATUS_DURATION(0xffff) | val 369 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt76_wr(dev, addr, val); val 371 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt76_wr(dev, addr, val); val 373 drivers/net/wireless/mediatek/mt76/mt7603/init.c val = MT_LED_CTRL_REPLAY(mt76->led_pin) | val 376 drivers/net/wireless/mediatek/mt76/mt7603/init.c val |= MT_LED_CTRL_POLARITY(mt76->led_pin); val 378 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt76_wr(dev, addr, val); val 424 drivers/net/wireless/mediatek/mt76/mt7603/init.c static void mt7603_wr(struct mt76_dev *mdev, u32 offset, u32 val) val 429 drivers/net/wireless/mediatek/mt76/mt7603/init.c dev->bus_ops->wr(mdev, addr, val); val 432 drivers/net/wireless/mediatek/mt76/mt7603/init.c static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) val 437 drivers/net/wireless/mediatek/mt76/mt7603/init.c return dev->bus_ops->rmw(mdev, addr, mask, val); val 453 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt7603_txpower_signed(int val) val 455 drivers/net/wireless/mediatek/mt76/mt7603/init.c bool sign = val & BIT(6); val 457 drivers/net/wireless/mediatek/mt76/mt7603/init.c if (!(val & BIT(7))) val 460 drivers/net/wireless/mediatek/mt76/mt7603/init.c val &= GENMASK(5, 0); val 462 drivers/net/wireless/mediatek/mt76/mt7603/init.c val = -val; val 464 drivers/net/wireless/mediatek/mt76/mt7603/init.c return val; val 44 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 val; val 64 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = MT7603_CFEND_RATE_DEFAULT; val 66 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = MT7603_CFEND_RATE_11B; val 68 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val); val 159 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 val = mt76_rr(dev, addr + 3 * 4); val 161 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val &= ~MT_WTBL1_W3_SKIP_TX; val 162 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val |= enabled * MT_WTBL1_W3_SKIP_TX; val 164 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_wr(dev, addr + 3 * 4, val); val 309 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 val; val 313 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = mt76_rr(dev, addr + 2 * 4); val 314 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL; val 315 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) | val 320 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val |= MT_WTBL1_W2_HT; val 322 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val |= MT_WTBL1_W2_VHT; val 324 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_wr(dev, addr + 2 * 4, val); val 327 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = mt76_rr(dev, addr + 9 * 4); val 328 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | val 331 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val |= MT_WTBL2_W9_SHORT_GI_20; val 333 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val |= MT_WTBL2_W9_SHORT_GI_40; val 334 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_wr(dev, addr + 9 * 4, val); val 568 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u16 val; val 573 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = r->hw_value_short; val 575 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = r->hw_value; val 577 drivers/net/wireless/mediatek/mt76/mt7603/mac.c phy = val >> 8; val 578 drivers/net/wireless/mediatek/mt76/mt7603/mac.c rate_idx = val & 0xff; val 600 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u16 val[4]; val 652 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); val 662 drivers/net/wireless/mediatek/mt76/mt7603/mac.c probe_val = val[0]; val 668 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); val 674 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); val 680 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); val 691 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) | val 692 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1])); val 695 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) | val 696 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) | val 697 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) | val 698 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2])); val 701 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) | val 702 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) | val 703 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3])); val 797 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 val; val 821 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | val 823 drivers/net/wireless/mediatek/mt76/mt7603/mac.c txwi[0] = cpu_to_le32(val); val 825 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = MT_TXD1_LONG_FORMAT | val 833 drivers/net/wireless/mediatek/mt76/mt7603/mac.c txwi[1] = cpu_to_le32(val); val 838 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) | val 842 drivers/net/wireless/mediatek/mt76/mt7603/mac.c txwi[2] = cpu_to_le32(val); val 849 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT | val 851 drivers/net/wireless/mediatek/mt76/mt7603/mac.c txwi[5] = cpu_to_le32(val); val 862 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = MT_TXD6_FIXED_BW | val 865 drivers/net/wireless/mediatek/mt76/mt7603/mac.c txwi[6] |= cpu_to_le32(val); val 880 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) | val 888 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val &= ~MT_TXD3_SN_VALID; val 890 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4); val 892 drivers/net/wireless/mediatek/mt76/mt7603/mac.c txwi[3] = cpu_to_le32(val); val 1354 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 val; val 1360 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = mt76_rr(dev, MT_WPDMA_DEBUG); val 1361 drivers/net/wireless/mediatek/mt76/mt7603/mac.c return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val); val 1382 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 val; val 1387 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = mt7603_dma_debug(dev, 9); val 1388 drivers/net/wireless/mediatek/mt76/mt7603/mac.c return (val & BIT(8)) && (val & 0xf) != 0xf; val 1417 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 addr, val; val 1427 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = mt76_rr(dev, addr) >> 16; val 1429 drivers/net/wireless/mediatek/mt76/mt7603/mac.c if (is_mt7628(dev) && (val & 0x4001) == 0x4001) val 1432 drivers/net/wireless/mediatek/mt76/mt7603/mac.c return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001; val 1485 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val) val 1489 drivers/net/wireless/mediatek/mt76/mt7603/mac.c if (val == dev->ed_strict_mode) val 1492 drivers/net/wireless/mediatek/mt76/mt7603/mac.c dev->ed_strict_mode = val; val 1514 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 val = mt76_rr(dev, MT_AGC(41)); val 1523 drivers/net/wireless/mediatek/mt76/mt7603/mac.c rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val); val 1527 drivers/net/wireless/mediatek/mt76/mt7603/mac.c rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val); val 1628 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 val; val 1630 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = mt76_rr(dev, MT_PHYCTRL_STAT_PD); val 1631 drivers/net/wireless/mediatek/mt76/mt7603/mac.c pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val); val 1632 drivers/net/wireless/mediatek/mt76/mt7603/mac.c pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val); val 1634 drivers/net/wireless/mediatek/mt76/mt7603/mac.c val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY); val 1635 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val); val 1636 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val); val 501 drivers/net/wireless/mediatek/mt76/mt7603/main.c u32 val; val 513 drivers/net/wireless/mediatek/mt76/mt7603/main.c val = mt76_rr(dev, MT_WMM_TXOP(queue)); val 514 drivers/net/wireless/mediatek/mt76/mt7603/main.c val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(queue)); val 515 drivers/net/wireless/mediatek/mt76/mt7603/main.c val |= params->txop << MT_WMM_TXOP_SHIFT(queue); val 516 drivers/net/wireless/mediatek/mt76/mt7603/main.c mt76_wr(dev, MT_WMM_TXOP(queue), val); val 518 drivers/net/wireless/mediatek/mt76/mt7603/main.c val = mt76_rr(dev, MT_WMM_AIFSN); val 519 drivers/net/wireless/mediatek/mt76/mt7603/main.c val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(queue)); val 520 drivers/net/wireless/mediatek/mt76/mt7603/main.c val |= params->aifs << MT_WMM_AIFSN_SHIFT(queue); val 521 drivers/net/wireless/mediatek/mt76/mt7603/main.c mt76_wr(dev, MT_WMM_AIFSN, val); val 523 drivers/net/wireless/mediatek/mt76/mt7603/main.c val = mt76_rr(dev, MT_WMM_CWMIN); val 524 drivers/net/wireless/mediatek/mt76/mt7603/main.c val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(queue)); val 525 drivers/net/wireless/mediatek/mt76/mt7603/main.c val |= cw_min << MT_WMM_CWMIN_SHIFT(queue); val 526 drivers/net/wireless/mediatek/mt76/mt7603/main.c mt76_wr(dev, MT_WMM_CWMIN, val); val 528 drivers/net/wireless/mediatek/mt76/mt7603/main.c val = mt76_rr(dev, MT_WMM_CWMAX(queue)); val 529 drivers/net/wireless/mediatek/mt76/mt7603/main.c val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(queue)); val 530 drivers/net/wireless/mediatek/mt76/mt7603/main.c val |= cw_max << MT_WMM_CWMAX_SHIFT(queue); val 531 drivers/net/wireless/mediatek/mt76/mt7603/main.c mt76_wr(dev, MT_WMM_CWMAX(queue), val); val 171 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c u32 addr, val; val 211 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c val = mt76_rr(dev, MT_TOP_MISC2); val 212 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c if (val & BIT(1)) { val 350 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c u8 val; val 377 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c data[i].val = eep[req_fields[i]]; val 250 drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h void mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val); val 6 drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c mt7615_radar_pattern_set(void *data, u64 val) val 17 drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c mt7615_scs_set(void *data, u64 val) val 21 drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c mt7615_mac_set_scs(dev, val); val 27 drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c mt7615_scs_get(void *data, u64 *val) val 31 drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c *val = dev->scs_en; val 14 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c u32 val; val 17 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_CTRL); val 18 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val &= ~(MT_EFUSE_CTRL_AIN | MT_EFUSE_CTRL_MODE); val 19 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf); val 20 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val |= MT_EFUSE_CTRL_KICK; val 21 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c mt76_wr(dev, base + MT_EFUSE_CTRL, val); val 28 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_CTRL); val 29 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT || val 30 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c WARN_ON_ONCE(!(val & MT_EFUSE_CTRL_VALID))) { val 36 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_RDATA(i)); val 37 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c put_unaligned_le32(val, data + 4 * i); val 45 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c u32 val, base = mt7615_reg_map(dev, MT_EFUSE_BASE); val 49 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_BASE_CTRL); val 50 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c if (val & MT_EFUSE_BASE_CTRL_EMPTY) val 83 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c u16 val = get_unaligned_le16(dev->eeprom.data); val 85 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c switch (val) { val 95 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c u8 val, *eeprom = dev->mt76.eeprom.data; val 97 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = FIELD_GET(MT_EE_NIC_WIFI_CONF_BAND_SEL, val 99 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c switch (val) { val 23 drivers/net/wireless/mediatek/mt76/mt7615/init.c u32 val; val 30 drivers/net/wireless/mediatek/mt76/mt7615/init.c val = mt76_rmw(dev, MT_TMAC_TRCR0, val 34 drivers/net/wireless/mediatek/mt76/mt7615/init.c mt76_wr(dev, MT_TMAC_TRCR1, val); val 36 drivers/net/wireless/mediatek/mt76/mt7615/init.c val = MT_AGG_ACR_PKT_TIME_EN | MT_AGG_ACR_NO_BA_AR_RULE | val 39 drivers/net/wireless/mediatek/mt76/mt7615/init.c mt76_wr(dev, MT_AGG_ACR0, val); val 40 drivers/net/wireless/mediatek/mt76/mt7615/init.c mt76_wr(dev, MT_AGG_ACR1, val); val 280 drivers/net/wireless/mediatek/mt76/mt7615/mac.c u16 val; val 285 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = r->hw_value_short; val 287 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = r->hw_value; val 289 drivers/net/wireless/mediatek/mt76/mt7615/mac.c phy = val >> 8; val 290 drivers/net/wireless/mediatek/mt76/mt7615/mac.c rate_idx = val & 0xff; val 319 drivers/net/wireless/mediatek/mt76/mt7615/mac.c u32 val; val 349 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | val 352 drivers/net/wireless/mediatek/mt76/mt7615/mac.c txwi[0] = cpu_to_le32(val); val 354 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = MT_TXD1_LONG_FORMAT | val 363 drivers/net/wireless/mediatek/mt76/mt7615/mac.c txwi[1] = cpu_to_le32(val); val 365 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | val 371 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val |= MT_TXD2_BIP; val 379 drivers/net/wireless/mediatek/mt76/mt7615/mac.c txwi[2] = cpu_to_le32(val); val 395 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = MT_TXD6_FIXED_BW | val 398 drivers/net/wireless/mediatek/mt76/mt7615/mac.c txwi[6] |= cpu_to_le32(val); val 414 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT | val 416 drivers/net/wireless/mediatek/mt76/mt7615/mac.c txwi[5] = cpu_to_le32(val); val 423 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); val 426 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val |= MT_TXD3_SN_VALID; val 431 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val |= MT_TXD3_SN_VALID; val 433 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val |= FIELD_PREP(MT_TXD3_SEQ, seqno); val 435 drivers/net/wireless/mediatek/mt76/mt7615/mac.c txwi[3] |= cpu_to_le32(val); val 473 drivers/net/wireless/mediatek/mt76/mt7615/mac.c u16 val[4]; val 524 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val[0] = mt7615_mac_tx_rate_val(dev, &rates[0], stbc, &bw); val 534 drivers/net/wireless/mediatek/mt76/mt7615/mac.c probe_val = val[0]; val 537 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val[1] = mt7615_mac_tx_rate_val(dev, &rates[1], stbc, &bw); val 543 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val[2] = mt7615_mac_tx_rate_val(dev, &rates[2], stbc, &bw); val 549 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val[3] = mt7615_mac_tx_rate_val(dev, &rates[3], stbc, &bw); val 569 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) | val 570 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1])); val 573 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) | val 574 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) | val 575 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) | val 576 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2])); val 579 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) | val 580 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) | val 581 drivers/net/wireless/mediatek/mt76/mt7615/mac.c FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3])); val 1173 drivers/net/wireless/mediatek/mt76/mt7615/mac.c u16 val; val 1177 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = *sensitivity * 2 + 512; val 1180 drivers/net/wireless/mediatek/mt76/mt7615/mac.c MT_WF_PHY_B0_PD_OFDM(val)); val 1182 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = *sensitivity + 256; val 1185 drivers/net/wireless/mediatek/mt76/mt7615/mac.c MT_WF_PHY_B0_PD_CCK(val)); val 1188 drivers/net/wireless/mediatek/mt76/mt7615/mac.c MT_WF_PHY_B1_PD_CCK(val)); val 1197 drivers/net/wireless/mediatek/mt76/mt7615/mac.c u32 val, rts_cnt = 0, rts_retries_cnt = 0, rts_err_rate = 0; val 1207 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = mt76_rr(dev, MT_MIB_MB_SDR0(i)); val 1208 drivers/net/wireless/mediatek/mt76/mt7615/mac.c data = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); val 1210 drivers/net/wireless/mediatek/mt76/mt7615/mac.c rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); val 1215 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = mt76_rr(dev, MT_WF_PHY_R0_B0_PHYCTRL_STS0); val 1216 drivers/net/wireless/mediatek/mt76/mt7615/mac.c pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val); val 1217 drivers/net/wireless/mediatek/mt76/mt7615/mac.c pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val); val 1219 drivers/net/wireless/mediatek/mt76/mt7615/mac.c val = mt76_rr(dev, MT_WF_PHY_R0_B0_PHYCTRL_STS5); val 1220 drivers/net/wireless/mediatek/mt76/mt7615/mac.c mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val); val 1221 drivers/net/wireless/mediatek/mt76/mt7615/mac.c mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val); val 429 drivers/net/wireless/mediatek/mt76/mt7615/main.c static int mt7615_set_rts_threshold(struct ieee80211_hw *hw, u32 val) val 434 drivers/net/wireless/mediatek/mt76/mt7615/main.c mt7615_mcu_set_rts_thresh(dev, val); val 57 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c u32 val; val 78 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) | val 81 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c txd[0] = cpu_to_le32(val); val 83 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c val = MT_TXD1_LONG_FORMAT | val 86 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c txd[1] = cpu_to_le32(val); val 515 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c u32 val; val 517 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE); val 519 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c if (val != FW_STATE_FW_DOWNLOAD) { val 619 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c int mt7615_mcu_set_rts_thresh(struct mt7615_dev *dev, u32 val) val 630 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c .len_thresh = cpu_to_le32(val), val 1219 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c u8 rx_sel, u8 val) val 1225 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c u8 val; val 1231 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c .val = val, val 1353 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c u32 msk, val = 0; val 1376 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c val |= MT_WTBL_W5_SHORT_GI_20; val 1378 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c val |= MT_WTBL_W5_SHORT_GI_40; val 1393 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c val |= MT_WTBL_W5_SHORT_GI_80; val 1395 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c val |= MT_WTBL_W5_SHORT_GI_160; val 1421 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c wtbl_raw->val = cpu_to_le32(val); val 365 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h __le32 val; val 37 drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h #define MT_FRAC(val, div) (((val) << MT_FRAC_SCALE) / (div)) val 200 drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h u8 rx_sel, u8 val); val 247 drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h int mt7615_mcu_set_rts_thresh(struct mt7615_dev *dev, u32 val); val 84 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c u8 val; val 86 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_2G_TARGET_POWER) >> 8; val 87 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c if (mt76x02_field_valid(val)) val 88 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c dev->cal.rx.temp_offset = mt76x02_sign_extend(val, 8); val 96 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c u8 val; val 98 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_FREQ_OFFSET); val 99 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c if (!mt76x02_field_valid(val)) val 100 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = 0; val 101 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c caldata->freq_offset = val; val 103 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TSSI_BOUND4) >> 8; val 104 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c if (!mt76x02_field_valid(val)) val 105 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = 0; val 107 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c caldata->freq_offset -= mt76x02_sign_extend(val, 8); val 114 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c s8 val, lna_5g[3], lna_2g; val 122 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = rssi_offset >> (8 * i); val 123 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c if (val < -10 || val > 10) val 124 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = 0; val 126 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c caldata->rssi_offset[i] = val; val 133 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c u8 val; val 136 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_5G_TARGET_POWER) >> 8; val 142 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = data >> 8; val 144 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = data; val 149 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c return mt76x02_rate_power_val(val); val 157 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c u16 val, addr; val 163 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_BYRATE_BASE); val 164 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->cck[0] = t->cck[1] = s6_to_s8(val); val 165 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->cck[2] = t->cck[3] = s6_to_s8(val >> 8); val 169 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, addr); val 170 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->ofdm[0] = t->ofdm[1] = s6_to_s8(val); val 171 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->ofdm[2] = t->ofdm[3] = s6_to_s8(val >> 8); val 175 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, addr); val 176 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->ofdm[4] = t->ofdm[5] = s6_to_s8(val); val 177 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->ofdm[6] = t->ofdm[7] = s6_to_s8(val >> 8); val 181 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, addr); val 182 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->ht[0] = t->ht[1] = t->vht[0] = t->vht[1] = s6_to_s8(val); val 183 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->ht[2] = t->ht[3] = t->vht[2] = t->vht[3] = s6_to_s8(val >> 8); val 187 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, addr); val 188 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->ht[4] = t->ht[5] = t->vht[4] = t->vht[5] = s6_to_s8(val); val 189 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->ht[6] = t->ht[7] = t->vht[6] = t->vht[7] = s6_to_s8(val >> 8); val 193 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, addr); val 194 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->stbc[0] = t->stbc[1] = s6_to_s8(val); val 195 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->stbc[2] = t->stbc[3] = s6_to_s8(val >> 8); val 199 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, addr); val 200 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->stbc[4] = t->stbc[5] = s6_to_s8(val); val 201 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->stbc[6] = t->stbc[7] = s6_to_s8(val >> 8); val 204 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = mt76x02_eeprom_get(dev, 0x132); val 205 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->vht[8] = s6_to_s8(val); val 206 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c t->vht[9] = s6_to_s8(val >> 8); val 287 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c u16 val; val 289 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = get_unaligned_le16(dev->mt76.eeprom.data); val 290 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c if (!val) val 291 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val = get_unaligned_le16(dev->mt76.eeprom.data + val 294 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c switch (val) { val 300 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c val); val 26 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h static inline s8 s6_to_s8(u32 val) val 28 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h s8 ret = val & GENMASK(5, 0); val 34 drivers/net/wireless/mediatek/mt76/mt76x0/init.c mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable) val 45 drivers/net/wireless/mediatek/mt76/mt76x0/init.c val |= (MT_WLAN_FUN_CTRL_WLAN_EN | val 48 drivers/net/wireless/mediatek/mt76/mt76x0/init.c val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); val 50 drivers/net/wireless/mediatek/mt76/mt76x0/init.c mt76_wr(dev, MT_WLAN_FUN_CTRL, val); val 63 drivers/net/wireless/mediatek/mt76/mt76x0/init.c u32 val; val 65 drivers/net/wireless/mediatek/mt76/mt76x0/init.c val = mt76_rr(dev, MT_WLAN_FUN_CTRL); val 68 drivers/net/wireless/mediatek/mt76/mt76x0/init.c val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; val 69 drivers/net/wireless/mediatek/mt76/mt76x0/init.c val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; val 71 drivers/net/wireless/mediatek/mt76/mt76x0/init.c if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { val 72 drivers/net/wireless/mediatek/mt76/mt76x0/init.c val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | val 74 drivers/net/wireless/mediatek/mt76/mt76x0/init.c mt76_wr(dev, MT_WLAN_FUN_CTRL, val); val 77 drivers/net/wireless/mediatek/mt76/mt76x0/init.c val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | val 82 drivers/net/wireless/mediatek/mt76/mt76x0/init.c mt76_wr(dev, MT_WLAN_FUN_CTRL, val); val 85 drivers/net/wireless/mediatek/mt76/mt76x0/init.c mt76x0_set_wlan_state(dev, val, enable); val 123 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c u16 val; val 127 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0); val 128 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c if (!(val & MT_EE_NIC_CONF_0_PA_IO_CURRENT)) val 16 drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c u32 val, ilm_len, dlm_len, offset = 0; val 50 drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c val = le16_to_cpu(hdr->fw_ver); val 52 drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf); val 54 drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c val = le16_to_cpu(hdr->fw_ver); val 57 drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf, val 62 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val; val 87 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76_rr(dev, MT_RF_CSR_CFG); val 88 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == reg && val 89 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) val 90 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c ret = FIELD_GET(MT_RF_CSR_CFG_DATA, val); val 103 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val) val 108 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c .value = val, val 115 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c return mt76x0_rf_csr_wr(dev, offset, val); val 122 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val; val 132 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = pair.value; val 134 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c ret = val = mt76x0_rf_csr_rr(dev, offset); val 137 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c return (ret < 0) ? ret : val; val 141 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val) val 149 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val |= ret & ~mask; val 151 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c ret = mt76x0_rf_wr(dev, offset, val); val 152 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c return ret ? ret : val; val 156 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val) val 158 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c return mt76x0_rf_rmw(dev, offset, 0, val); val 188 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val; val 191 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76_rr(dev, MT_BBP(CORE, 0)); val 192 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (val && ~val) val 201 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c dev_dbg(dev->mt76.dev, "BBP version %08x\n", val); val 412 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val = pair->value; val 415 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c gain = FIELD_GET(MT_BBP_AGC_GAIN, val); val 417 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val &= ~MT_BBP_AGC_GAIN; val 418 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val |= FIELD_PREP(MT_BBP_AGC_GAIN, gain); val 419 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_wr(dev, pair->reg, val); val 506 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val; val 520 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050; val 521 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_wr(dev, MT_BBP(CORE, 34), val); val 547 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val; val 549 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050; val 550 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_wr(dev, MT_BBP(CORE, 34), val); val 579 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val, reg; val 582 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76_rr(dev, reg); val 583 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c return (val & (3 << (tx_rate * 2))) >> (tx_rate * 2); val 665 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c static s16 mt76x0_phy_lin2db(u16 val) val 667 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 mantissa = val << 4; val 703 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u16 val; val 718 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_5G + i * 2); val 720 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c tssi_offset = val >> 8; val 725 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_2G); val 727 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c tssi_offset = val >> 8; val 731 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c tssi_slope = val & 0xff; val 827 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c s8 val; val 837 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76x0_phy_get_delta_power(dev, tx_mode, target_power, val 839 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, val); val 863 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val, tx_alc, reg_val; val 892 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x701; val 894 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x801; val 896 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x901; val 898 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x600; val 901 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x02_mcu_calibrate(dev, MCU_CAL_FULL, val); val 940 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val; val 975 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x201; val 977 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x601; val 978 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_wr(dev, MT_TX_SW_CFG0, val); val 1020 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c s8 val; val 1036 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76_rr(dev, MT_BBP(CORE, 35)); val 1037 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = (35 * (val - dev->cal.rx.temp_offset)) / 10 + 25; val 1039 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (abs(val - dev->cal.temp_vco) > 20) { val 1042 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c dev->cal.temp_vco = val; val 1044 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (abs(val - dev->cal.temp) > 30) { val 1046 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c dev->cal.temp = val; val 1122 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u8 val = rp[i].value; val 1128 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x70; val 1130 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x63; val 1132 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x73; val 1137 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x10; val 1139 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x12; val 1143 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x1d; val 1145 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x00; val 1147 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = 0x0c; val 1152 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_wr(dev, reg, val); val 1159 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u8 val; val 1192 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76x0_rf_rr(dev, MT_RF(0, 22)); val 47 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c u32 val; val 49 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c val = mt76_rr(dev, MT_USB_DMA_CFG); val 51 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c val |= MT_USB_DMA_CFG_RX_BULK_EN | val 57 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c val &= ~MT_USB_DMA_CFG_RX_BULK_AGG_EN; val 58 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c mt76_wr(dev, MT_USB_DMA_CFG, val); val 60 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c val = mt76_rr(dev, MT_COM_REG0); val 61 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c if (val & 1) val 64 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c val = mt76_rr(dev, MT_USB_DMA_CFG); val 66 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c val |= MT_USB_DMA_CFG_RX_DROP_OR_PAD; val 67 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c mt76_wr(dev, MT_USB_DMA_CFG, val); val 68 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c val &= ~MT_USB_DMA_CFG_RX_DROP_OR_PAD; val 69 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c mt76_wr(dev, MT_USB_DMA_CFG, val); val 90 drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c u32 val; val 117 drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c val = le16_to_cpu(hdr->fw_ver); val 120 drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf, val 144 drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c val = mt76_rr(dev, MT_USB_DMA_CFG); val 145 drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c val |= MT_USB_DMA_CFG_UDMA_TX_WL_DROP; val 146 drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c mt76_wr(dev, MT_USB_DMA_CFG, val); val 147 drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c val &= ~MT_USB_DMA_CFG_UDMA_TX_WL_DROP; val 148 drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c mt76_wr(dev, MT_USB_DMA_CFG, val); val 167 drivers/net/wireless/mediatek/mt76/mt76x02.h int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val); val 13 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c u16 val; val 17 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c val = i * dev->beacon_ops->slot_size; val 18 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c regs[i / 4] |= (val / 64) << (8 * (i % 4)); val 109 drivers/net/wireless/mediatek/mt76/mt76x02_debugfs.c mt76_edcca_set(void *data, u64 val) val 116 drivers/net/wireless/mediatek/mt76/mt76x02_debugfs.c dev->ed_monitor_enabled = !!val; val 127 drivers/net/wireless/mediatek/mt76/mt76x02_debugfs.c mt76_edcca_get(void *data, u64 *val) val 131 drivers/net/wireless/mediatek/mt76/mt76x02_debugfs.c *val = dev->ed_monitor_enabled; val 183 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c static int mt76x02_dfs_get_multiple(int val, int frac, int margin) val 190 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c if (abs(val - frac) <= margin) val 193 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c factor = val / frac; val 194 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c remainder = val % frac; val 15 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c u32 val; val 18 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val = mt76_rr(dev, MT_EFUSE_CTRL); val 19 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val &= ~(MT_EFUSE_CTRL_AIN | val 21 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf); val 22 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val |= FIELD_PREP(MT_EFUSE_CTRL_MODE, mode); val 23 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val |= MT_EFUSE_CTRL_KICK; val 24 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c mt76_wr(dev, MT_EFUSE_CTRL, val); val 31 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val = mt76_rr(dev, MT_EFUSE_CTRL); val 32 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) { val 38 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val = mt76_rr(dev, MT_EFUSE_DATA(i)); val 39 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c put_unaligned_le32(val, data + 4 * i); val 74 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c u16 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0); val 76 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c switch (FIELD_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, val)) { val 105 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c u16 val; val 107 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_LNA_GAIN); val 108 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c *lna_2g = val & 0xff; val 109 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c lna_5g[0] = val >> 8; val 111 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_1); val 112 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c lna_5g[1] = val >> 8; val 114 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_1); val 115 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c lna_5g[2] = val >> 8; val 134 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c u16 val; val 137 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1); val 138 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c if (val & MT_EE_NIC_CONF_1_LNA_EXT_2G) val 140 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c if (val & MT_EE_NIC_CONF_1_LNA_EXT_5G) val 133 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h static inline bool mt76x02_field_valid(u8 val) val 135 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h return val != 0 && val != 0xff; val 139 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h mt76x02_sign_extend(u32 val, unsigned int size) val 141 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h bool sign = val & BIT(size - 1); val 143 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h val &= BIT(size - 1) - 1; val 145 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h return sign ? val : -val; val 149 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h mt76x02_sign_extend_optional(u32 val, unsigned int size) val 151 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h bool enable = val & BIT(size); val 153 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h return enable ? mt76x02_sign_extend(val, size) : 0; val 156 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h static inline s8 mt76x02_rate_power_val(u8 val) val 158 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h if (!mt76x02_field_valid(val)) val 161 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h return mt76x02_sign_extend_optional(val, 7); val 41 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c u32 val; val 47 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); val 48 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); val 49 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); val 50 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); val 149 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); val 153 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c if ((val & bit) != (bit * drop)) val 154 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); val 183 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c u16 val; val 187 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c val = r->hw_value_short; val 189 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c val = r->hw_value; val 191 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c phy = val >> 8; val 192 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c rate_idx = val & 0xff; val 848 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val) val 852 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c if (val != ~0) val 856 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val); val 967 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c u32 val = mt76_rr(dev, 0x10f4); val 969 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) val 1050 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c u32 active, val, busy; val 1053 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c val = mt76_rr(dev, MT_ED_CCA_TIMER); val 1058 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c busy = (val * 100) / active; val 1099 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); val 1101 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c dev->aggr_stats[idx++] += val & 0xffff; val 1102 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c dev->aggr_stats[idx++] += val >> 16; val 184 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val); val 75 drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c u32 val) val 82 drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c .value = cpu_to_le32(val), val 99 drivers/net/wireless/mediatek/mt76/mt76x02_mcu.h u32 val); val 311 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c u32 val; val 317 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) | val 320 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c mt76_set(dev, MT_WPDMA_GLO_CFG, val); val 334 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG); val 336 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE | val 339 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE; val 340 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c mt76_wr(dev, MT_WPDMA_GLO_CFG, val); val 14 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c u32 val; val 16 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val = mt76_rr(dev, MT_BBP(AGC, 0)); val 17 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val &= ~BIT(4); val 21 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= BIT(3); val 24 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val &= ~BIT(3); val 28 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c mt76_wr(dev, MT_BBP(AGC, 0), val); val 30 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val = mt76_rr(dev, MT_BBP(AGC, 0)); val 53 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c u32 val = 0; val 55 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v1 & (BIT(6) - 1)) << 0; val 56 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v2 & (BIT(6) - 1)) << 8; val 57 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v3 & (BIT(6) - 1)) << 16; val 58 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v4 & (BIT(6) - 1)) << 24; val 59 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c return val; val 104 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h TP_PROTO(struct mt76x02_dev *dev, u32 val, u32 mask), val 106 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h TP_ARGS(dev, val, mask), val 110 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h __field(u32, val) val 116 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h __entry->val = val; val 122 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h DEV_PR_ARG, __entry->val, __entry->mask val 24 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c u32 reg, val; val 32 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c val = get_unaligned_le32(data + 4 * i); val 34 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c usb->mcu.rp[i].value = val; val 42 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c val = get_unaligned_le32(data + 8 * i + 4); val 45 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c usb->mcu.rp[i].value = val; val 137 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c static inline void skb_put_le32(struct sk_buff *skb, u32 val) val 139 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c put_unaligned_le32(val, skb_put(skb, 4)); val 232 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c u32 val; val 257 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c val = mt76_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX); val 258 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c val++; val 259 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c mt76_wr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX, val); val 97 drivers/net/wireless/mediatek/mt76/mt76x02_util.c u32 val; val 99 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val = MT_LED_STATUS_DURATION(0xff) | val 103 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_wr(dev, MT_LED_S0(mdev->led_pin), val); val 104 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_wr(dev, MT_LED_S1(mdev->led_pin), val); val 106 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val = MT_LED_CTRL_REPLAY(mdev->led_pin) | val 109 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val |= MT_LED_CTRL_POLARITY(mdev->led_pin); val 110 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_wr(dev, MT_LED_CTRL, val); val 490 drivers/net/wireless/mediatek/mt76/mt76x02_util.c u32 val; val 499 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val = FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop) | val 503 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_wr(dev, MT_EDCA_CFG_AC(qid), val); val 505 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val = mt76_rr(dev, MT_WMM_TXOP(qid)); val 506 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(qid)); val 507 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val |= params->txop << MT_WMM_TXOP_SHIFT(qid); val 508 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_wr(dev, MT_WMM_TXOP(qid), val); val 510 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val = mt76_rr(dev, MT_WMM_AIFSN); val 511 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(qid)); val 512 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val |= params->aifs << MT_WMM_AIFSN_SHIFT(qid); val 513 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_wr(dev, MT_WMM_AIFSN, val); val 515 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val = mt76_rr(dev, MT_WMM_CWMIN); val 516 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(qid)); val 517 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val |= cw_min << MT_WMM_CWMIN_SHIFT(qid); val 518 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_wr(dev, MT_WMM_CWMIN, val); val 520 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val = mt76_rr(dev, MT_WMM_CWMAX); val 521 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(qid)); val 522 drivers/net/wireless/mediatek/mt76/mt76x02_util.c val |= cw_max << MT_WMM_CWMAX_SHIFT(qid); val 523 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_wr(dev, MT_WMM_CWMAX, val); val 559 drivers/net/wireless/mediatek/mt76/mt76x02_util.c int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val) val 563 drivers/net/wireless/mediatek/mt76/mt76x02_util.c if (val != ~0 && val > 0xffff) val 567 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76x02_mac_set_rts_thresh(dev, val); val 86 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c u16 val; val 105 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = get_unaligned_le16(efuse + MT_EE_BT_RCAL_RESULT); val 106 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c if (val != 0xffff) val 107 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c eeprom[MT_EE_BT_RCAL_RESULT] = val & 0xff; val 109 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = get_unaligned_le16(efuse + MT_EE_BT_VCDL_CALIBRATION); val 110 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c if (val != 0xffff) val 111 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8; val 113 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = get_unaligned_le16(efuse + MT_EE_BT_PMUCFG); val 114 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c if (val != 0xffff) val 115 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c eeprom[MT_EE_BT_PMUCFG] = val & 0xff; val 120 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c u16 val = get_unaligned_le16(dev->mt76.eeprom.data); val 122 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c if (!val) val 123 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID); val 125 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c switch (val) { val 130 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val); val 178 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c mt76x2_set_rx_gain_group(struct mt76x02_dev *dev, u8 val) val 182 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c if (!mt76x02_field_valid(val)) { val 188 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c dest[0] = mt76x02_sign_extend(val, 4); val 189 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c dest[1] = mt76x02_sign_extend(val >> 4, 4); val 193 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c mt76x2_set_rssi_offset(struct mt76x02_dev *dev, int chain, u8 val) val 197 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c if (!mt76x02_field_valid(val)) { val 202 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c dest[chain] = mt76x02_sign_extend_optional(val, 7); val 255 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c u16 val; val 258 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8; val 260 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x2_get_5g_rx_gain(dev, channel); val 262 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c mt76x2_set_rx_gain_group(dev, val); val 264 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c mt76x02_get_rx_gain(dev, chan->band, &val, &lna_2g, lna_5g); val 265 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c mt76x2_set_rssi_offset(dev, 0, val); val 266 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c mt76x2_set_rssi_offset(dev, 1, val >> 8); val 282 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c u16 val; val 288 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_CCK); val 289 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->cck[0] = t->cck[1] = mt76x02_rate_power_val(val); val 290 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->cck[2] = t->cck[3] = mt76x02_rate_power_val(val >> 8); val 293 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M); val 295 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M); val 296 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ofdm[0] = t->ofdm[1] = mt76x02_rate_power_val(val); val 297 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ofdm[2] = t->ofdm[3] = mt76x02_rate_power_val(val >> 8); val 300 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M); val 302 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M); val 303 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ofdm[4] = t->ofdm[5] = mt76x02_rate_power_val(val); val 304 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ofdm[6] = t->ofdm[7] = mt76x02_rate_power_val(val >> 8); val 306 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0); val 307 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ht[0] = t->ht[1] = mt76x02_rate_power_val(val); val 308 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ht[2] = t->ht[3] = mt76x02_rate_power_val(val >> 8); val 310 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4); val 311 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ht[4] = t->ht[5] = mt76x02_rate_power_val(val); val 312 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ht[6] = t->ht[7] = mt76x02_rate_power_val(val >> 8); val 314 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8); val 315 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ht[8] = t->ht[9] = mt76x02_rate_power_val(val); val 316 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ht[10] = t->ht[11] = mt76x02_rate_power_val(val >> 8); val 318 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12); val 319 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ht[12] = t->ht[13] = mt76x02_rate_power_val(val); val 320 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->ht[14] = t->ht[15] = mt76x02_rate_power_val(val >> 8); val 322 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS0); val 323 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->vht[0] = t->vht[1] = mt76x02_rate_power_val(val); val 324 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->vht[2] = t->vht[3] = mt76x02_rate_power_val(val >> 8); val 326 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS4); val 327 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->vht[4] = t->vht[5] = mt76x02_rate_power_val(val); val 328 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->vht[6] = t->vht[7] = mt76x02_rate_power_val(val >> 8); val 330 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8); val 332 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val >>= 8; val 333 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->vht[8] = t->vht[9] = mt76x02_rate_power_val(val >> 8); val 350 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c u16 val; val 367 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER); val 368 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->target_power = val >> 8; val 380 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c u16 val; val 419 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN); val 420 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->target_power = val & 0xff; val 459 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c u16 val, slope; val 470 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8; val 471 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c t->temp_25_ref = val & 0x7f; val 54 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h u32 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1); val 57 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h return val & MT_EE_NIC_CONF_1_LNA_EXT_2G; val 59 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h return val & MT_EE_NIC_CONF_1_LNA_EXT_5G; val 65 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h u16 val; val 67 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G); val 68 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h if (!(val & BIT(15))) val 14 drivers/net/wireless/mediatek/mt76/mt76x2/init.c u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL); val 17 drivers/net/wireless/mediatek/mt76/mt76x2/init.c val |= (MT_WLAN_FUN_CTRL_WLAN_EN | val 20 drivers/net/wireless/mediatek/mt76/mt76x2/init.c val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN | val 23 drivers/net/wireless/mediatek/mt76/mt76x2/init.c mt76_wr(dev, MT_WLAN_FUN_CTRL, val); val 29 drivers/net/wireless/mediatek/mt76/mt76x2/init.c u32 val; val 34 drivers/net/wireless/mediatek/mt76/mt76x2/init.c val = mt76_rr(dev, MT_WLAN_FUN_CTRL); val 36 drivers/net/wireless/mediatek/mt76/mt76x2/init.c val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; val 38 drivers/net/wireless/mediatek/mt76/mt76x2/init.c if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { val 39 drivers/net/wireless/mediatek/mt76/mt76x2/init.c val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF; val 40 drivers/net/wireless/mediatek/mt76/mt76x2/init.c mt76_wr(dev, MT_WLAN_FUN_CTRL, val); val 43 drivers/net/wireless/mediatek/mt76/mt76x2/init.c val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF; val 46 drivers/net/wireless/mediatek/mt76/mt76x2/init.c mt76_wr(dev, MT_WLAN_FUN_CTRL, val); val 61 drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c u32 val; val 63 drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c val = BIT(31); val 64 drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c val |= (mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0) >> 8) & 0x00ff; val 65 drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c val |= (mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1) << 8) & 0xff00; val 66 drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c msg.cfg = cpu_to_le32(val); val 14 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c u32 val; val 16 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c val = MT_PBF_SYS_CTRL_MCU_RESET | val 22 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_set(dev, MT_PBF_SYS_CTRL, val); val 23 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_clear(dev, MT_PBF_SYS_CTRL, val); val 72 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c u32 val; val 78 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c val = mt76_rr(dev, MT_WPDMA_GLO_CFG); val 80 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN | val 85 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3); val 87 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_wr(dev, MT_WPDMA_GLO_CFG, val); val 211 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c u32 val; val 216 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c val = MT_WLAN_MTC_CTRL_STATE_UP | val 220 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000); val 87 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c u32 offset, val; val 105 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c val = le16_to_cpu(hdr->fw_ver); val 107 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf); val 109 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c val = le16_to_cpu(hdr->build_ver); val 110 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c dev_info(dev->mt76.dev, "Build: %x\n", val); val 132 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); val 133 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c if (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1) val 73 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c u32 val; val 75 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val = mt76_rr(dev, MT_BBP(AGC, 0)); val 76 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val &= ~(BIT(4) | BIT(1)); val 87 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val &= ~(BIT(3) | BIT(0)); val 98 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val &= ~BIT(3); val 99 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val |= BIT(0); val 110 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val &= ~BIT(0); val 111 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val |= BIT(3); val 114 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c mt76_wr(dev, MT_BBP(AGC, 0), val); val 213 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c u8 val = mt76x02_eeprom_get(dev, MT_EE_BT_RCAL_RESULT); val 215 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c if (val != 0xff) val 92 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c u32 val; val 95 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val = 0x3c3c023c; val 97 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val = 0x363c023c; val 99 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val); val 100 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val); val 104 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c u32 val = 0x0f3c3c3c; val 106 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val); val 107 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val); val 247 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c u32 val; val 253 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val = 0x1836 << 16; val 256 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val = 0x1e42 << 16; val 261 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val = 0x0f36 << 16; val 263 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val |= 0xf8; val 266 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[0])); val 268 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[1])); val 281 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c u32 val; val 302 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf; val 304 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val |= 0x3; val 306 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c val |= 0x5; val 307 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_wr(dev, MT_BBP(AGC, 26), val); val 15 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); val 17 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c val |= MT_USB_DMA_CFG_RX_DROP_OR_PAD | val 24 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c val &= ~MT_USB_DMA_CFG_RX_BULK_AGG_EN; val 25 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val); val 51 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c u32 val = (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift; val 58 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val); val 72 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c u32 val; val 78 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c val = MT_WLAN_MTC_CTRL_STATE_UP | val 82 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_poll(dev, MT_VEND_ADDR(CFG, 0x148), val, val, 1000); val 108 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c u32 val, i; val 118 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c val = mt76_rr(dev, MT_VEND_ADDR(EEPROM, i)); val 119 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c put_unaligned_le32(val, dev->mt76.eeprom.data + i); val 124 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c int i, count = 0, val; val 139 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); val 140 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c if (!(val & MT_USB_DMA_CFG_TX_BUSY) && i > 10) val 192 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); val 193 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c if (!(val & MT_USB_DMA_CFG_RX_BUSY) && i > 10) val 61 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c u32 val, patch_mask, patch_reg; val 99 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c val = MT_USB_DMA_CFG_RX_BULK_EN | val 102 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val); val 146 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c u32 val, dlm_offset = MT76U_MCU_DLM_OFFSET; val 169 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c val = le16_to_cpu(hdr->fw_ver); val 171 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf); val 173 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c val = le16_to_cpu(hdr->build_ver); val 174 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c dev_info(dev->mt76.dev, "Build: %x\n", val); val 182 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c val = MT_USB_DMA_CFG_RX_BULK_EN | val 185 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val); val 148 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c u8 val = mt76x02_eeprom_get(dev, MT_EE_BT_RCAL_RESULT); val 150 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c if (val != 0xff) val 22 drivers/net/wireless/mediatek/mt76/trace.h #define REG_ENTRY __field(u32, reg) __field(u32, val) val 23 drivers/net/wireless/mediatek/mt76/trace.h #define REG_ASSIGN __entry->reg = reg; __entry->val = val val 25 drivers/net/wireless/mediatek/mt76/trace.h #define REG_PR_ARG __entry->reg, __entry->val val 28 drivers/net/wireless/mediatek/mt76/trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), val 29 drivers/net/wireless/mediatek/mt76/trace.h TP_ARGS(dev, reg, val), val 45 drivers/net/wireless/mediatek/mt76/trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), val 46 drivers/net/wireless/mediatek/mt76/trace.h TP_ARGS(dev, reg, val) val 50 drivers/net/wireless/mediatek/mt76/trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), val 51 drivers/net/wireless/mediatek/mt76/trace.h TP_ARGS(dev, reg, val) val 20 drivers/net/wireless/mediatek/mt76/usb.c u8 req_type, u16 val, u16 offset, val 34 drivers/net/wireless/mediatek/mt76/usb.c ret = usb_control_msg(udev, pipe, req, req_type, val, val 49 drivers/net/wireless/mediatek/mt76/usb.c u8 req_type, u16 val, u16 offset, val 56 drivers/net/wireless/mediatek/mt76/usb.c val, offset, buf, len); val 57 drivers/net/wireless/mediatek/mt76/usb.c trace_usb_reg_wr(dev, offset, val); val 108 drivers/net/wireless/mediatek/mt76/usb.c static void __mt76u_wr(struct mt76_dev *dev, u32 addr, u32 val) val 124 drivers/net/wireless/mediatek/mt76/usb.c usb->reg_val = cpu_to_le32(val); val 128 drivers/net/wireless/mediatek/mt76/usb.c trace_usb_reg_wr(dev, addr, val); val 131 drivers/net/wireless/mediatek/mt76/usb.c static void mt76u_wr(struct mt76_dev *dev, u32 addr, u32 val) val 134 drivers/net/wireless/mediatek/mt76/usb.c __mt76u_wr(dev, addr, val); val 139 drivers/net/wireless/mediatek/mt76/usb.c u32 mask, u32 val) val 142 drivers/net/wireless/mediatek/mt76/usb.c val |= __mt76u_rr(dev, addr) & ~mask; val 143 drivers/net/wireless/mediatek/mt76/usb.c __mt76u_wr(dev, addr, val); val 146 drivers/net/wireless/mediatek/mt76/usb.c return val; val 153 drivers/net/wireless/mediatek/mt76/usb.c const u32 *val = data; val 158 drivers/net/wireless/mediatek/mt76/usb.c put_unaligned(val[i], (u32 *)usb->data); val 170 drivers/net/wireless/mediatek/mt76/usb.c const u16 offset, const u32 val) val 175 drivers/net/wireless/mediatek/mt76/usb.c val & 0xffff, offset, NULL, 0); val 178 drivers/net/wireless/mediatek/mt76/usb.c val >> 16, offset + 2, NULL, 0); val 22 drivers/net/wireless/mediatek/mt76/usb_trace.h #define REG_ENTRY __field(u32, reg) __field(u32, val) val 23 drivers/net/wireless/mediatek/mt76/usb_trace.h #define REG_ASSIGN __entry->reg = reg; __entry->val = val val 25 drivers/net/wireless/mediatek/mt76/usb_trace.h #define REG_PR_ARG __entry->reg, __entry->val val 28 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), val 29 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_ARGS(dev, reg, val), val 45 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), val 46 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_ARGS(dev, reg, val) val 50 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), val 51 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_ARGS(dev, reg, val) val 9 drivers/net/wireless/mediatek/mt76/util.c bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, val 17 drivers/net/wireless/mediatek/mt76/util.c if (cur == val) val 27 drivers/net/wireless/mediatek/mt76/util.c bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, val 35 drivers/net/wireless/mediatek/mt76/util.c if (cur == val) val 12 drivers/net/wireless/mediatek/mt7601u/core.c u32 val; val 18 drivers/net/wireless/mediatek/mt7601u/core.c val = mt7601u_rr(dev, MT_MAC_CSR0); val 19 drivers/net/wireless/mediatek/mt7601u/core.c if (val && ~val) val 28 drivers/net/wireless/mediatek/mt7601u/core.c bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, val 39 drivers/net/wireless/mediatek/mt7601u/core.c if (cur == val) val 50 drivers/net/wireless/mediatek/mt7601u/core.c bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, val 61 drivers/net/wireless/mediatek/mt7601u/core.c if (cur == val) val 13 drivers/net/wireless/mediatek/mt7601u/debugfs.c mt76_reg_set(void *data, u64 val) val 17 drivers/net/wireless/mediatek/mt7601u/debugfs.c mt76_wr(dev, dev->debugfs_reg, val); val 22 drivers/net/wireless/mediatek/mt7601u/debugfs.c mt76_reg_get(void *data, u64 *val) val 26 drivers/net/wireless/mediatek/mt7601u/debugfs.c *val = mt76_rr(dev, dev->debugfs_reg); val 17 drivers/net/wireless/mediatek/mt7601u/eeprom.c field_valid(u8 val) val 19 drivers/net/wireless/mediatek/mt7601u/eeprom.c return val != 0xff; val 23 drivers/net/wireless/mediatek/mt7601u/eeprom.c field_validate(u8 val) val 25 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (!field_valid(val)) val 28 drivers/net/wireless/mediatek/mt7601u/eeprom.c return val; val 35 drivers/net/wireless/mediatek/mt7601u/eeprom.c u32 val; val 38 drivers/net/wireless/mediatek/mt7601u/eeprom.c val = mt76_rr(dev, MT_EFUSE_CTRL); val 39 drivers/net/wireless/mediatek/mt7601u/eeprom.c val &= ~(MT_EFUSE_CTRL_AIN | val 41 drivers/net/wireless/mediatek/mt7601u/eeprom.c val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf) | val 44 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt76_wr(dev, MT_EFUSE_CTRL, val); val 49 drivers/net/wireless/mediatek/mt7601u/eeprom.c val = mt76_rr(dev, MT_EFUSE_CTRL); val 50 drivers/net/wireless/mediatek/mt7601u/eeprom.c if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) { val 59 drivers/net/wireless/mediatek/mt7601u/eeprom.c val = mt76_rr(dev, MT_EFUSE_DATA(i)); val 60 drivers/net/wireless/mediatek/mt7601u/eeprom.c put_unaligned_le32(val, data + 4 * i); val 147 drivers/net/wireless/mediatek/mt7601u/eeprom.c u32 i, val; val 150 drivers/net/wireless/mediatek/mt7601u/eeprom.c val = mt7601u_rr(dev, MT_TX_ALC_CFG_0); val 151 drivers/net/wireless/mediatek/mt7601u/eeprom.c max_pwr = FIELD_GET(MT_TX_ALC_CFG_0_LIMIT_0, val); val 181 drivers/net/wireless/mediatek/mt7601u/eeprom.c u8 val = eeprom[MT_EE_COUNTRY_REGION]; val 184 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (val < 8) val 185 drivers/net/wireless/mediatek/mt7601u/eeprom.c idx = val; val 186 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (val > 31 && val < 33) val 187 drivers/net/wireless/mediatek/mt7601u/eeprom.c idx = val - 32 + 8; val 192 drivers/net/wireless/mediatek/mt7601u/eeprom.c val, chan_bounds[idx].start, val 239 drivers/net/wireless/mediatek/mt7601u/eeprom.c u32 val; val 241 drivers/net/wireless/mediatek/mt7601u/eeprom.c val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_1) & 0x0000ff00) >> 8); val 242 drivers/net/wireless/mediatek/mt7601u/eeprom.c val |= ((mt7601u_rr(dev, MT_TX_PWR_CFG_2) & 0x0000ff00) << 8); val 243 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_wr(dev, MT_TX_PWR_CFG_7, val); val 245 drivers/net/wireless/mediatek/mt7601u/eeprom.c val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_4) & 0x0000ff00) >> 8); val 246 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_wr(dev, MT_TX_PWR_CFG_9, val); val 263 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_save_power_rate(struct mt7601u_dev *dev, s8 delta, u32 val, int i) val 269 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->cck[0], delta, (val >> 0) & 0xff); val 270 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->cck[1], delta, (val >> 8) & 0xff); val 275 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->ofdm[0], delta, (val >> 16) & 0xff); val 276 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->ofdm[1], delta, (val >> 24) & 0xff); val 279 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->ofdm[2], delta, (val >> 0) & 0xff); val 280 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->ofdm[3], delta, (val >> 8) & 0xff); val 281 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->ht[0], delta, (val >> 16) & 0xff); val 282 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->ht[1], delta, (val >> 24) & 0xff); val 285 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->ht[2], delta, (val >> 0) & 0xff); val 286 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_set_power_rate(&t->ht[3], delta, (val >> 8) & 0xff); val 292 drivers/net/wireless/mediatek/mt7601u/eeprom.c get_delta(u8 val) val 296 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (!field_valid(val) || !(val & BIT(7))) val 299 drivers/net/wireless/mediatek/mt7601u/eeprom.c ret = val & 0x1f; val 302 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (val & BIT(6)) val 311 drivers/net/wireless/mediatek/mt7601u/eeprom.c u32 val; val 318 drivers/net/wireless/mediatek/mt7601u/eeprom.c val = get_unaligned_le32(eeprom + MT_EE_TX_POWER_BYRATE(i)); val 320 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_save_power_rate(dev, bw40_delta, val, i); val 322 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (~val) val 323 drivers/net/wireless/mediatek/mt7601u/eeprom.c mt7601u_wr(dev, MT_TX_PWR_CFG_0 + i * 4, val); val 133 drivers/net/wireless/mediatek/mt7601u/eeprom.h static inline u32 int_to_s6(int val) val 135 drivers/net/wireless/mediatek/mt7601u/eeprom.h if (val < -0x20) val 137 drivers/net/wireless/mediatek/mt7601u/eeprom.h if (val > 0x1f) val 140 drivers/net/wireless/mediatek/mt7601u/eeprom.h return val & 0x3f; val 16 drivers/net/wireless/mediatek/mt7601u/init.c mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable) val 27 drivers/net/wireless/mediatek/mt7601u/init.c val |= (MT_WLAN_FUN_CTRL_WLAN_EN | val 30 drivers/net/wireless/mediatek/mt7601u/init.c val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); val 32 drivers/net/wireless/mediatek/mt7601u/init.c mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); val 43 drivers/net/wireless/mediatek/mt7601u/init.c val = mt7601u_rr(dev, MT_CMB_CTRL); val 45 drivers/net/wireless/mediatek/mt7601u/init.c if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD) val 61 drivers/net/wireless/mediatek/mt7601u/init.c u32 val; val 65 drivers/net/wireless/mediatek/mt7601u/init.c val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL); val 68 drivers/net/wireless/mediatek/mt7601u/init.c val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; val 69 drivers/net/wireless/mediatek/mt7601u/init.c val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; val 71 drivers/net/wireless/mediatek/mt7601u/init.c if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { val 72 drivers/net/wireless/mediatek/mt7601u/init.c val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | val 74 drivers/net/wireless/mediatek/mt7601u/init.c mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); val 77 drivers/net/wireless/mediatek/mt7601u/init.c val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | val 82 drivers/net/wireless/mediatek/mt7601u/init.c mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); val 85 drivers/net/wireless/mediatek/mt7601u/init.c mt7601u_set_wlan_state(dev, val, enable); val 101 drivers/net/wireless/mediatek/mt7601u/init.c u32 val; val 103 drivers/net/wireless/mediatek/mt7601u/init.c val = FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) | val 109 drivers/net/wireless/mediatek/mt7601u/init.c val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN; val 110 drivers/net/wireless/mediatek/mt7601u/init.c mt7601u_wr(dev, MT_USB_DMA_CFG, val); val 112 drivers/net/wireless/mediatek/mt7601u/init.c val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP; val 113 drivers/net/wireless/mediatek/mt7601u/init.c mt7601u_wr(dev, MT_USB_DMA_CFG, val); val 114 drivers/net/wireless/mediatek/mt7601u/init.c val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP; val 115 drivers/net/wireless/mediatek/mt7601u/init.c mt7601u_wr(dev, MT_USB_DMA_CFG, val); val 123 drivers/net/wireless/mediatek/mt7601u/mac.c u16 val; val 127 drivers/net/wireless/mediatek/mt7601u/mac.c val = r->hw_value_short; val 129 drivers/net/wireless/mediatek/mt7601u/mac.c val = r->hw_value; val 131 drivers/net/wireless/mediatek/mt7601u/mac.c phy = val >> 8; val 132 drivers/net/wireless/mediatek/mt7601u/mac.c rate_idx = val & 0xff; val 160 drivers/net/wireless/mediatek/mt7601u/mac.c u32 val; val 162 drivers/net/wireless/mediatek/mt7601u/mac.c val = mt7601u_rr(dev, MT_TX_STAT_FIFO); val 163 drivers/net/wireless/mediatek/mt7601u/mac.c stat.valid = !!(val & MT_TX_STAT_FIFO_VALID); val 164 drivers/net/wireless/mediatek/mt7601u/mac.c stat.success = !!(val & MT_TX_STAT_FIFO_SUCCESS); val 165 drivers/net/wireless/mediatek/mt7601u/mac.c stat.aggr = !!(val & MT_TX_STAT_FIFO_AGGR); val 166 drivers/net/wireless/mediatek/mt7601u/mac.c stat.ack_req = !!(val & MT_TX_STAT_FIFO_ACKREQ); val 167 drivers/net/wireless/mediatek/mt7601u/mac.c stat.pktid = FIELD_GET(MT_TX_STAT_FIFO_PID_TYPE, val); val 168 drivers/net/wireless/mediatek/mt7601u/mac.c stat.wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, val); val 169 drivers/net/wireless/mediatek/mt7601u/mac.c stat.rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, val); val 269 drivers/net/wireless/mediatek/mt7601u/mac.c u32 val = mt7601u_rr(dev, MT_BEACON_TIME_CFG); val 271 drivers/net/wireless/mediatek/mt7601u/mac.c val &= ~(MT_BEACON_TIME_CFG_TIMER_EN | val 276 drivers/net/wireless/mediatek/mt7601u/mac.c mt7601u_wr(dev, MT_BEACON_TIME_CFG, val); val 280 drivers/net/wireless/mediatek/mt7601u/mac.c val &= ~MT_BEACON_TIME_CFG_INTVAL; val 281 drivers/net/wireless/mediatek/mt7601u/mac.c val |= FIELD_PREP(MT_BEACON_TIME_CFG_INTVAL, interval << 4) | val 289 drivers/net/wireless/mediatek/mt7601u/mac.c u32 val = mt7601u_rr(dev, 0x10f4); val 291 drivers/net/wireless/mediatek/mt7601u/mac.c if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) val 331 drivers/net/wireless/mediatek/mt7601u/mac.c u32 val = mt7601u_rr(dev, spans[i].addr_base + j * 4); val 333 drivers/net/wireless/mediatek/mt7601u/mac.c spans[i].stat_base[j * 2] += val & 0xffff; val 334 drivers/net/wireless/mediatek/mt7601u/mac.c spans[i].stat_base[j * 2 + 1] += val >> 16; val 341 drivers/net/wireless/mediatek/mt7601u/mac.c n += (val >> 16) + (val & 0xffff); val 342 drivers/net/wireless/mediatek/mt7601u/mac.c sum += (val & 0xffff) * (1 + k * 2) + val 343 drivers/net/wireless/mediatek/mt7601u/mac.c (val >> 16) * (2 + k * 2); val 536 drivers/net/wireless/mediatek/mt7601u/mac.c u32 val; val 559 drivers/net/wireless/mediatek/mt7601u/mac.c val = mt7601u_rr(dev, MT_WCID_ATTR(idx)); val 560 drivers/net/wireless/mediatek/mt7601u/mac.c val &= ~MT_WCID_ATTR_PKEY_MODE & ~MT_WCID_ATTR_PKEY_MODE_EXT; val 561 drivers/net/wireless/mediatek/mt7601u/mac.c val |= FIELD_PREP(MT_WCID_ATTR_PKEY_MODE, cipher & 7) | val 563 drivers/net/wireless/mediatek/mt7601u/mac.c val &= ~MT_WCID_ATTR_PAIRWISE; val 564 drivers/net/wireless/mediatek/mt7601u/mac.c val |= MT_WCID_ATTR_PAIRWISE * val 566 drivers/net/wireless/mediatek/mt7601u/mac.c mt7601u_wr(dev, MT_WCID_ATTR(idx), val); val 576 drivers/net/wireless/mediatek/mt7601u/mac.c u32 val; val 587 drivers/net/wireless/mediatek/mt7601u/mac.c val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); val 588 drivers/net/wireless/mediatek/mt7601u/mac.c val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); val 589 drivers/net/wireless/mediatek/mt7601u/mac.c val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); val 590 drivers/net/wireless/mediatek/mt7601u/mac.c mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); val 29 drivers/net/wireless/mediatek/mt7601u/mcu.c static inline void skb_put_le32(struct sk_buff *skb, u32 val) val 31 drivers/net/wireless/mediatek/mt7601u/mcu.c put_unaligned_le32(val, skb_put(skb, 4)); val 154 drivers/net/wireless/mediatek/mt7601u/mcu.c enum mcu_function func, u32 val) val 162 drivers/net/wireless/mediatek/mt7601u/mcu.c .value = cpu_to_le32(val), val 191 drivers/net/wireless/mediatek/mt7601u/mcu.c mt7601u_mcu_calibrate(struct mt7601u_dev *dev, enum mcu_calibrate cal, u32 val) val 199 drivers/net/wireless/mediatek/mt7601u/mcu.c .value = cpu_to_le32(val), val 288 drivers/net/wireless/mediatek/mt7601u/mcu.c u32 val; val 326 drivers/net/wireless/mediatek/mt7601u/mcu.c val = mt7601u_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX); val 327 drivers/net/wireless/mediatek/mt7601u/mcu.c val++; val 328 drivers/net/wireless/mediatek/mt7601u/mcu.c mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX, val); val 409 drivers/net/wireless/mediatek/mt7601u/mcu.c u32 val; val 436 drivers/net/wireless/mediatek/mt7601u/mcu.c val = le16_to_cpu(hdr->fw_ver); val 439 drivers/net/wireless/mediatek/mt7601u/mcu.c (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf, val 464 drivers/net/wireless/mediatek/mt7601u/mcu.c val = mt76_set(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_CLR); val 465 drivers/net/wireless/mediatek/mt7601u/mcu.c val &= ~MT_USB_DMA_CFG_TX_CLR; val 466 drivers/net/wireless/mediatek/mt7601u/mcu.c mt7601u_wr(dev, MT_USB_DMA_CFG, val); val 83 drivers/net/wireless/mediatek/mt7601u/mcu.h mt7601u_mcu_calibrate(struct mt7601u_dev *dev, enum mcu_calibrate cal, u32 val); val 284 drivers/net/wireless/mediatek/mt7601u/mt7601u.h void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val); val 285 drivers/net/wireless/mediatek/mt7601u/mt7601u.h u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); val 286 drivers/net/wireless/mediatek/mt7601u/mt7601u.h u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); val 291 drivers/net/wireless/mediatek/mt7601u/mt7601u.h bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, val 293 drivers/net/wireless/mediatek/mt7601u/mt7601u.h bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, val 305 drivers/net/wireless/mediatek/mt7601u/mt7601u.h static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val) val 307 drivers/net/wireless/mediatek/mt7601u/mt7601u.h return mt7601u_wr(dev, offset, val); val 311 drivers/net/wireless/mediatek/mt7601u/mt7601u.h mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) val 313 drivers/net/wireless/mediatek/mt7601u/mt7601u.h return mt7601u_rmw(dev, offset, mask, val); val 316 drivers/net/wireless/mediatek/mt7601u/mt7601u.h static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val) val 318 drivers/net/wireless/mediatek/mt7601u/mt7601u.h return mt76_rmw(dev, offset, 0, val); val 321 drivers/net/wireless/mediatek/mt7601u/mt7601u.h static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val) val 323 drivers/net/wireless/mediatek/mt7601u/mt7601u.h return mt76_rmw(dev, offset, val, 0); val 57 drivers/net/wireless/mediatek/mt7601u/phy.c u32 val; val 78 drivers/net/wireless/mediatek/mt7601u/phy.c val = mt7601u_rr(dev, MT_RF_CSR_CFG); val 79 drivers/net/wireless/mediatek/mt7601u/phy.c if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == offset && val 80 drivers/net/wireless/mediatek/mt7601u/phy.c FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) { val 81 drivers/net/wireless/mediatek/mt7601u/phy.c ret = FIELD_GET(MT_RF_CSR_CFG_DATA, val); val 95 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val) val 102 drivers/net/wireless/mediatek/mt7601u/phy.c val |= ret & ~mask; val 103 drivers/net/wireless/mediatek/mt7601u/phy.c ret = mt7601u_rf_wr(dev, bank, offset, val); val 107 drivers/net/wireless/mediatek/mt7601u/phy.c return val; val 111 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val) val 113 drivers/net/wireless/mediatek/mt7601u/phy.c return mt7601u_rf_rmw(dev, bank, offset, 0, val); val 122 drivers/net/wireless/mediatek/mt7601u/phy.c static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val) val 136 drivers/net/wireless/mediatek/mt7601u/phy.c FIELD_PREP(MT_BBP_CSR_CFG_VAL, val) | val 139 drivers/net/wireless/mediatek/mt7601u/phy.c trace_bbp_write(dev, offset, val); val 146 drivers/net/wireless/mediatek/mt7601u/phy.c u32 val; val 167 drivers/net/wireless/mediatek/mt7601u/phy.c val = mt7601u_rr(dev, MT_BBP_CSR_CFG); val 168 drivers/net/wireless/mediatek/mt7601u/phy.c if (FIELD_GET(MT_BBP_CSR_CFG_REG_NUM, val) == offset) { val 169 drivers/net/wireless/mediatek/mt7601u/phy.c ret = FIELD_GET(MT_BBP_CSR_CFG_VAL, val); val 182 drivers/net/wireless/mediatek/mt7601u/phy.c static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) val 189 drivers/net/wireless/mediatek/mt7601u/phy.c val |= ret & ~mask; val 190 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_bbp_wr(dev, offset, val); val 192 drivers/net/wireless/mediatek/mt7601u/phy.c return val; val 195 drivers/net/wireless/mediatek/mt7601u/phy.c static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) val 202 drivers/net/wireless/mediatek/mt7601u/phy.c val |= ret & ~mask; val 203 drivers/net/wireless/mediatek/mt7601u/phy.c if (ret != val) val 204 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_bbp_wr(dev, offset, val); val 206 drivers/net/wireless/mediatek/mt7601u/phy.c return val; val 212 drivers/net/wireless/mediatek/mt7601u/phy.c u8 val; val 215 drivers/net/wireless/mediatek/mt7601u/phy.c val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION); val 216 drivers/net/wireless/mediatek/mt7601u/phy.c if (val && val != 0xff) val 249 drivers/net/wireless/mediatek/mt7601u/phy.c int val; val 254 drivers/net/wireless/mediatek/mt7601u/phy.c val = 8; val 255 drivers/net/wireless/mediatek/mt7601u/phy.c val -= lna[aux_lna][bw][lna_id]; val 256 drivers/net/wireless/mediatek/mt7601u/phy.c val -= FIELD_GET(MT_RXWI_GAIN_RSSI_VAL, rxwi->gain); val 257 drivers/net/wireless/mediatek/mt7601u/phy.c val -= dev->ee->lna_gain; val 258 drivers/net/wireless/mediatek/mt7601u/phy.c val -= dev->ee->rssi_offset[0]; val 260 drivers/net/wireless/mediatek/mt7601u/phy.c return val; val 533 drivers/net/wireless/mediatek/mt7601u/phy.c u8 val; val 536 drivers/net/wireless/mediatek/mt7601u/phy.c val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10); val 539 drivers/net/wireless/mediatek/mt7601u/phy.c for (i = 100; i && (val & 0x10); i--) val 540 drivers/net/wireless/mediatek/mt7601u/phy.c val = mt7601u_bbp_rr(dev, 47); val 542 drivers/net/wireless/mediatek/mt7601u/phy.c temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP); val 881 drivers/net/wireless/mediatek/mt7601u/phy.c u32 val; val 936 drivers/net/wireless/mediatek/mt7601u/phy.c val = mt7601u_rr(dev, MT_TX_ALC_CFG_1); val 937 drivers/net/wireless/mediatek/mt7601u/phy.c curr_pwr = s6_to_int(FIELD_GET(MT_TX_ALC_CFG_1_TEMP_COMP, val)); val 939 drivers/net/wireless/mediatek/mt7601u/phy.c val = (val & ~MT_TX_ALC_CFG_1_TEMP_COMP) | int_to_s6(diff_pwr); val 940 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_wr(dev, MT_TX_ALC_CFG_1, val); val 969 drivers/net/wireless/mediatek/mt7601u/phy.c u8 val = mt7601u_agc_default(dev); val 987 drivers/net/wireless/mediatek/mt7601u/phy.c val -= 0x20; val 989 drivers/net/wireless/mediatek/mt7601u/phy.c val -= 0x10; val 991 drivers/net/wireless/mediatek/mt7601u/phy.c if (val != mt7601u_bbp_rr(dev, 66)) val 992 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_bbp_wr(dev, 66, val); val 1176 drivers/net/wireless/mediatek/mt7601u/phy.c u32 val, old; val 1188 drivers/net/wireless/mediatek/mt7601u/phy.c val = old & ~(MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); val 1189 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_wr(dev, MT_MAC_SYS_CTRL, val); val 24 drivers/net/wireless/mediatek/mt7601u/trace.h #define REG_ENTRY __field(u32, reg) __field(u32, val) val 25 drivers/net/wireless/mediatek/mt7601u/trace.h #define REG_ASSIGN __entry->reg = reg; __entry->val = val val 27 drivers/net/wireless/mediatek/mt7601u/trace.h #define REG_PR_ARG __entry->reg, __entry->val val 30 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), val 31 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val), val 47 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), val 48 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val) val 52 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), val 53 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val) val 100 drivers/net/wireless/mediatek/mt7601u/trace.h u16 val, u16 offset, void *buf, size_t buflen, int ret), val 101 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, pipe, req, req_type, val, offset, buf, buflen, ret), val 105 drivers/net/wireless/mediatek/mt7601u/trace.h __field(u16, val) __field(u16, offset) __field(void*, buf) val 113 drivers/net/wireless/mediatek/mt7601u/trace.h __entry->val = val; val 122 drivers/net/wireless/mediatek/mt7601u/trace.h __entry->req_type, __entry->val, __entry->offset, val 127 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, int offset, u16 val), val 128 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, offset, val), val 136 drivers/net/wireless/mediatek/mt7601u/trace.h __entry->v = val; val 142 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), val 143 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val), val 148 drivers/net/wireless/mediatek/mt7601u/trace.h __field(u8, val) val 157 drivers/net/wireless/mediatek/mt7601u/trace.h DEV_PR_ARG, __entry->bank, __entry->reg, __entry->val val 162 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), val 163 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val) val 167 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), val 168 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val) val 172 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), val 173 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val), val 177 drivers/net/wireless/mediatek/mt7601u/trace.h __field(u8, val) val 185 drivers/net/wireless/mediatek/mt7601u/trace.h DEV_PR_ARG, __entry->reg, __entry->val val 190 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), val 191 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val) val 195 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), val 196 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val) val 200 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 val), val 201 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, val), val 204 drivers/net/wireless/mediatek/mt7601u/trace.h __field(u8, val) val 208 drivers/net/wireless/mediatek/mt7601u/trace.h __entry->val = val; val 211 drivers/net/wireless/mediatek/mt7601u/trace.h DEV_PR_FMT "%02hhx", DEV_PR_ARG, __entry->val val 216 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 val), val 217 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, val) val 221 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 val), val 222 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, val) val 226 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 val), val 227 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, val) val 364 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 val), val 365 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, val) val 265 drivers/net/wireless/mediatek/mt7601u/tx.c u32 val; val 281 drivers/net/wireless/mediatek/mt7601u/tx.c val = FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) | val 289 drivers/net/wireless/mediatek/mt7601u/tx.c val |= 0x60; val 291 drivers/net/wireless/mediatek/mt7601u/tx.c val |= FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop); val 292 drivers/net/wireless/mediatek/mt7601u/tx.c mt76_wr(dev, MT_EDCA_CFG_AC(hw_q), val); val 294 drivers/net/wireless/mediatek/mt7601u/tx.c val = mt76_rr(dev, MT_WMM_TXOP(hw_q)); val 295 drivers/net/wireless/mediatek/mt7601u/tx.c val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(hw_q)); val 296 drivers/net/wireless/mediatek/mt7601u/tx.c val |= params->txop << MT_WMM_TXOP_SHIFT(hw_q); val 297 drivers/net/wireless/mediatek/mt7601u/tx.c mt76_wr(dev, MT_WMM_TXOP(hw_q), val); val 299 drivers/net/wireless/mediatek/mt7601u/tx.c val = mt76_rr(dev, MT_WMM_AIFSN); val 300 drivers/net/wireless/mediatek/mt7601u/tx.c val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(hw_q)); val 301 drivers/net/wireless/mediatek/mt7601u/tx.c val |= params->aifs << MT_WMM_AIFSN_SHIFT(hw_q); val 302 drivers/net/wireless/mediatek/mt7601u/tx.c mt76_wr(dev, MT_WMM_AIFSN, val); val 304 drivers/net/wireless/mediatek/mt7601u/tx.c val = mt76_rr(dev, MT_WMM_CWMIN); val 305 drivers/net/wireless/mediatek/mt7601u/tx.c val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(hw_q)); val 306 drivers/net/wireless/mediatek/mt7601u/tx.c val |= cw_min << MT_WMM_CWMIN_SHIFT(hw_q); val 307 drivers/net/wireless/mediatek/mt7601u/tx.c mt76_wr(dev, MT_WMM_CWMIN, val); val 309 drivers/net/wireless/mediatek/mt7601u/tx.c val = mt76_rr(dev, MT_WMM_CWMAX); val 310 drivers/net/wireless/mediatek/mt7601u/tx.c val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(hw_q)); val 311 drivers/net/wireless/mediatek/mt7601u/tx.c val |= cw_max << MT_WMM_CWMAX_SHIFT(hw_q); val 312 drivers/net/wireless/mediatek/mt7601u/tx.c mt76_wr(dev, MT_WMM_CWMAX, val); val 88 drivers/net/wireless/mediatek/mt7601u/usb.c const u8 direction, const u16 val, const u16 offset, val 99 drivers/net/wireless/mediatek/mt7601u/usb.c val, offset, buf, buflen, val 101 drivers/net/wireless/mediatek/mt7601u/usb.c trace_mt_vend_req(dev, pipe, req, req_type, val, offset, val 128 drivers/net/wireless/mediatek/mt7601u/usb.c u32 val = ~0; val 135 drivers/net/wireless/mediatek/mt7601u/usb.c val = get_unaligned_le32(dev->vend_buf); val 140 drivers/net/wireless/mediatek/mt7601u/usb.c trace_reg_read(dev, offset, val); val 141 drivers/net/wireless/mediatek/mt7601u/usb.c return val; val 157 drivers/net/wireless/mediatek/mt7601u/usb.c const u16 offset, const u32 val) val 160 drivers/net/wireless/mediatek/mt7601u/usb.c val & 0xffff, offset, NULL, 0); val 163 drivers/net/wireless/mediatek/mt7601u/usb.c val >> 16, offset + 2, NULL, 0); val 164 drivers/net/wireless/mediatek/mt7601u/usb.c trace_reg_write(dev, offset, val); val 169 drivers/net/wireless/mediatek/mt7601u/usb.c const u16 offset, const u32 val) val 174 drivers/net/wireless/mediatek/mt7601u/usb.c ret = __mt7601u_vendor_single_wr(dev, req, offset, val); val 180 drivers/net/wireless/mediatek/mt7601u/usb.c void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val) val 184 drivers/net/wireless/mediatek/mt7601u/usb.c mt7601u_vendor_single_wr(dev, MT_VEND_WRITE, offset, val); val 187 drivers/net/wireless/mediatek/mt7601u/usb.c u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) val 190 drivers/net/wireless/mediatek/mt7601u/usb.c val |= __mt7601u_rr(dev, offset) & ~mask; val 191 drivers/net/wireless/mediatek/mt7601u/usb.c __mt7601u_vendor_single_wr(dev, MT_VEND_WRITE, offset, val); val 194 drivers/net/wireless/mediatek/mt7601u/usb.c return val; val 197 drivers/net/wireless/mediatek/mt7601u/usb.c u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) val 203 drivers/net/wireless/mediatek/mt7601u/usb.c val |= reg & ~mask; val 204 drivers/net/wireless/mediatek/mt7601u/usb.c if (reg != val) val 206 drivers/net/wireless/mediatek/mt7601u/usb.c offset, val); val 209 drivers/net/wireless/mediatek/mt7601u/usb.c return val; val 65 drivers/net/wireless/mediatek/mt7601u/usb.h const u8 direction, const u16 val, const u16 offset, val 69 drivers/net/wireless/mediatek/mt7601u/usb.h const u16 offset, const u32 val); val 300 drivers/net/wireless/quantenna/qtnfmac/commands.c memcpy(tlv->val, s->ht_cap, sizeof(*s->ht_cap)); val 309 drivers/net/wireless/quantenna/qtnfmac/commands.c memcpy(tlv->val, s->vht_cap, sizeof(*s->vht_cap)); val 320 drivers/net/wireless/quantenna/qtnfmac/commands.c qlink_acl_data_cfg2q(s->acl, (struct qlink_acl_data *)tlv->val); val 576 drivers/net/wireless/quantenna/qtnfmac/commands.c map = tlv->val; val 580 drivers/net/wireless/quantenna/qtnfmac/commands.c stats = (const struct qlink_sta_stats *)tlv->val; val 587 drivers/net/wireless/quantenna/qtnfmac/commands.c tlv = (const struct qlink_tlv_hdr *)(tlv->val + tlv_len); val 898 drivers/net/wireless/quantenna/qtnfmac/commands.c bld_name = (const void *)tlv->val; val 901 drivers/net/wireless/quantenna/qtnfmac/commands.c bld_rev = (const void *)tlv->val; val 904 drivers/net/wireless/quantenna/qtnfmac/commands.c bld_type = (const void *)tlv->val; val 907 drivers/net/wireless/quantenna/qtnfmac/commands.c bld_label = (const void *)tlv->val; val 910 drivers/net/wireless/quantenna/qtnfmac/commands.c hw_id = (const void *)tlv->val; val 913 drivers/net/wireless/quantenna/qtnfmac/commands.c calibration_ver = (const void *)tlv->val; val 916 drivers/net/wireless/quantenna/qtnfmac/commands.c uboot_ver = (const void *)tlv->val; val 919 drivers/net/wireless/quantenna/qtnfmac/commands.c hwinfo->max_scan_ssids = *tlv->val; val 926 drivers/net/wireless/quantenna/qtnfmac/commands.c tlv = (struct qlink_tlv_hdr *)(tlv->val + tlv_value_len); val 1057 drivers/net/wireless/quantenna/qtnfmac/commands.c comb_num = (void *)tlv->val; val 1093 drivers/net/wireless/quantenna/qtnfmac/commands.c rec = (void *)tlv->val; val 1129 drivers/net/wireless/quantenna/qtnfmac/commands.c ext_capa = (u8 *)tlv->val; val 1135 drivers/net/wireless/quantenna/qtnfmac/commands.c ext_capa_mask = (u8 *)tlv->val; val 1142 drivers/net/wireless/quantenna/qtnfmac/commands.c wowlan = (void *)tlv->val; val 1184 drivers/net/wireless/quantenna/qtnfmac/commands.c tlv = (struct qlink_tlv_hdr *)(tlv->val + tlv_value_len); val 1364 drivers/net/wireless/quantenna/qtnfmac/commands.c qchan = (const struct qlink_channel *)tlv->val; val 1436 drivers/net/wireless/quantenna/qtnfmac/commands.c qtnf_cmd_resp_band_fill_htcap(tlv->val, &band->ht_cap); val 1445 drivers/net/wireless/quantenna/qtnfmac/commands.c qtnf_cmd_resp_band_fill_vhtcap(tlv->val, val 1454 drivers/net/wireless/quantenna/qtnfmac/commands.c tlv = (struct qlink_tlv_hdr *)(tlv->val + tlv_dlen); val 1532 drivers/net/wireless/quantenna/qtnfmac/commands.c tlv = (struct qlink_tlv_hdr *)(tlv->val + tlv_value_len); val 1571 drivers/net/wireless/quantenna/qtnfmac/commands.c qlink_stats = (void *)tlv->val; val 1589 drivers/net/wireless/quantenna/qtnfmac/commands.c tlv = (struct qlink_tlv_hdr *)(tlv->val + tlv_value_len); val 2080 drivers/net/wireless/quantenna/qtnfmac/commands.c randmac = (struct qlink_random_mac_addr *)hdr->val; val 2605 drivers/net/wireless/quantenna/qtnfmac/commands.c qlink_acl_data_cfg2q(params, (struct qlink_acl_data *)tlv->val); val 93 drivers/net/wireless/quantenna/qtnfmac/event.c tlv = (struct qlink_tlv_hdr *)(tlv->val + tlv_value_len); val 280 drivers/net/wireless/quantenna/qtnfmac/event.c tlv = (struct qlink_tlv_hdr *)(tlv->val + tlv_value_len); val 429 drivers/net/wireless/quantenna/qtnfmac/event.c tlv = (struct qlink_tlv_hdr *)(tlv->val + tlv_value_len); val 82 drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg) val 84 drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h writel(val, basereg); val 385 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c u32 val; val 387 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c val = readl(PCIE_HHBM_CONFIG(ps->pcie_reg_base)); val 388 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c val |= HHBM_CONFIG_SOFT_RESET; val 389 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base)); val 391 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c val &= ~HHBM_CONFIG_SOFT_RESET; val 393 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c val |= HHBM_64BIT; val 395 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base)); val 406 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c u32 val; val 411 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c val = tx_bd_size * sizeof(struct qtnf_pearl_tx_bd); val 413 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c if (!is_power_of_2(tx_bd_size) || val > PCIE_HHBM_MAX_SIZE) { val 429 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c val = priv->rx_bd_num * sizeof(dma_addr_t); val 430 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c if (val > PCIE_HHBM_MAX_SIZE) { val 1214 drivers/net/wireless/quantenna/qtnfmac/qlink.h u8 val[0]; val 27 drivers/net/wireless/quantenna/qtnfmac/qlink_util.h memcpy(hdr->val, arr, arr_len); val 45 drivers/net/wireless/quantenna/qtnfmac/qlink_util.h *hdr->val = value; val 56 drivers/net/wireless/quantenna/qtnfmac/qlink_util.h memcpy(hdr->val, &tmp, sizeof(tmp)); val 67 drivers/net/wireless/quantenna/qtnfmac/qlink_util.h memcpy(hdr->val, &tmp, sizeof(tmp)); val 169 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8180.h u8 __iomem *addr, u8 val) val 171 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8180.h iowrite8(val, addr); val 175 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8180.h __le16 __iomem *addr, u16 val) val 177 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8180.h iowrite16(val, addr); val 181 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8180.h __le32 __iomem *addr, u32 val) val 183 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8180.h iowrite32(val, addr); val 165 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c __le32 *addr, u32 val) val 167 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c __le32 buf = cpu_to_le32(val); val 464 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u64 val; val 494 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c val = le64_to_cpu(priv->b_tx_status.buf); val 496 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c cmd_type = (val >> 30) & 0x3; val 504 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c pkt_rc = val & 0xFF; val 505 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c tok = val & (1 << 15); val 506 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c seq_no = (val >> 16) & 0xFFF; val 185 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h u8 *addr, u8 val, u8 idx); val 187 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h static inline void rtl818x_iowrite8(struct rtl8187_priv *priv, u8 *addr, u8 val) val 189 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h rtl818x_iowrite8_idx(priv, addr, val, 0); val 193 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h __le16 *addr, u16 val, u8 idx); val 196 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h u16 val) val 198 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h rtl818x_iowrite16_idx(priv, addr, val, 0); val 202 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h __le32 *addr, u32 val, u8 idx); val 205 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h u32 val) val 207 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h rtl818x_iowrite32_idx(priv, addr, val, 0); val 25 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c u8 val; val 31 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c &priv->io_dmabuf->bits8, sizeof(val), HZ / 2); val 33 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c val = priv->io_dmabuf->bits8; val 36 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c return val; val 42 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c __le16 val; val 48 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c &priv->io_dmabuf->bits16, sizeof(val), HZ / 2); val 50 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c val = priv->io_dmabuf->bits16; val 53 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c return le16_to_cpu(val); val 59 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c __le32 val; val 65 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c &priv->io_dmabuf->bits32, sizeof(val), HZ / 2); val 67 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c val = priv->io_dmabuf->bits32; val 70 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c return le32_to_cpu(val); val 74 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c u8 *addr, u8 val, u8 idx) val 78 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c priv->io_dmabuf->bits8 = val; val 82 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c &priv->io_dmabuf->bits8, sizeof(val), HZ / 2); val 88 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c __le16 *addr, u16 val, u8 idx) val 92 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c priv->io_dmabuf->bits16 = cpu_to_le16(val); val 96 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c &priv->io_dmabuf->bits16, sizeof(val), HZ / 2); val 102 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c __le32 *addr, u32 val, u8 idx) val 106 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c priv->io_dmabuf->bits32 = cpu_to_le32(val); val 110 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c &priv->io_dmabuf->bits32, sizeof(val), HZ / 2); val 869 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h u8 val; val 874 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h u32 val; val 879 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h u32 val; val 1366 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); val 1367 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); val 1368 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); val 709 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) val 715 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c priv->usb_buf.val8 = val; val 725 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c __func__, addr, val); val 729 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) val 735 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c priv->usb_buf.val16 = cpu_to_le16(val); val 744 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c __func__, addr, val); val 748 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) val 754 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c priv->usb_buf.val32 = cpu_to_le32(val); val 763 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c __func__, addr, val); val 2148 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u8 val; val 2152 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val = array[i].val; val 2154 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (reg == 0xffff && val == 0xff) val 2157 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ret = rtl8xxxu_write8(priv, reg, val); val 2161 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c "(reg: %04x, val %02x)\n", reg, val); val 2177 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u32 val; val 2181 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val = array[i].val; val 2183 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (reg == 0xffff && val == 0xffffffff) val 2186 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ret = rtl8xxxu_write32(priv, reg, val); val 2187 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (ret != sizeof(val)) { val 2343 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u32 val; val 2347 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val = array[i].val; val 2349 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (reg == 0xff && val == 0xffffffff) val 2373 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ret = rtl8xxxu_write_rfreg(priv, path, reg, val); val 906 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c u8 val = (u8)level; val 910 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); val 798 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c u8 val = (u8) level; val 802 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); val 759 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c u8 val = (u8)level; val 763 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val); val 293 drivers/net/wireless/realtek/rtlwifi/debug.c u32 addr, val, len; val 307 drivers/net/wireless/realtek/rtlwifi/debug.c num = sscanf(tmp, "%x %x %x", &addr, &val, &len); val 314 drivers/net/wireless/realtek/rtlwifi/debug.c rtl_write_byte(rtlpriv, addr, (u8)val); val 317 drivers/net/wireless/realtek/rtlwifi/debug.c rtl_write_word(rtlpriv, addr, (u16)val); val 320 drivers/net/wireless/realtek/rtlwifi/debug.c rtl_write_dword(rtlpriv, addr, val); val 283 drivers/net/wireless/realtek/rtlwifi/pci.h static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val) val 285 drivers/net/wireless/realtek/rtlwifi/pci.h writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr); val 289 drivers/net/wireless/realtek/rtlwifi/pci.h u32 addr, u16 val) val 291 drivers/net/wireless/realtek/rtlwifi/pci.h writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr); val 295 drivers/net/wireless/realtek/rtlwifi/pci.h u32 addr, u32 val) val 297 drivers/net/wireless/realtek/rtlwifi/pci.h writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr); val 296 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 304 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *((u32 *)(val)) = rtlpci->receive_config; val 307 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 317 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *((bool *)(val)) = true; val 322 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *((bool *)(val)) = false; val 324 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *((bool *)(val)) = true; val 328 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *((bool *)(val)) = ppsc->fw_current_inpsmode; val 338 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *((u64 *)(val)) = tsf; val 348 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 361 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c val[idx]); val 365 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c u16 b_rate_cfg = ((u16 *)val)[0]; val 383 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c val[idx]); val 387 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); val 388 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); val 390 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); val 391 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); val 398 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *((u16 *)val)); val 404 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 406 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_SLOT, val[0]); val 416 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c u8 short_preamble = (bool)*val; val 429 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_SECCFG, *val); val 435 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c min_spacing_to_set = *val; val 446 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c *val = min_spacing_to_set; val 459 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c density_to_set = *val; val 478 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c factor_toset = *val; val 509 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c u8 e_aci = *val; val 518 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c u8 e_aci = *val; val 568 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); val 569 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtlpci->receive_config = ((u32 *)(val))[0]; val 572 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c u8 retry_limit = *val; val 582 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtlefuse->efuse_usedbytes = *((u16 *)val); val 585 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtlefuse->efuse_usedpercentage = *val; val 588 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val)); val 597 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); val 599 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7)); val 603 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl88e_set_fw_pwrmode_cmd(hw, *val); val 606 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c ppsc->fw_current_inpsmode = *((bool *)val); val 612 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c bool enter_fwlps = *((bool *)val); val 621 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c u8 mstatus = *val; val 680 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val)); val 683 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl88e_set_p2p_ps_offload_cmd(hw, *val); val 694 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c u8 btype_ibss = *val; val 715 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c array[1] = *((u8 *)val); val 7 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.h void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 22 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.h void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 732 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c bool istx, u8 desc_name, u8 *val) val 742 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c set_tx_desc_next_desc_address(pdesc, *(u32 *)val); val 755 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c set_rx_desc_buff_addr(pdesc, *(u32 *)val); val 758 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c set_rx_desc_pkt_len(pdesc, *(u32 *)val); val 793 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h bool istx, u8 desc_name, u8 *val); val 71 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 79 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *((u32 *) (val)) = rtlpci->receive_config; val 82 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 92 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *((bool *) (val)) = true; val 97 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *((bool *) (val)) = false; val 99 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *((bool *) (val)) = true; val 104 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *((bool *) (val)) = ppsc->fw_current_inpsmode; val 114 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *((u64 *) (val)) = tsf; val 126 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 140 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c val[idx]); val 145 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u16 rate_cfg = ((u16 *) val)[0]; val 164 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c val[idx]); val 169 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); val 170 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); val 172 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); val 173 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); val 180 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *((u16 *) val)); val 187 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 189 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_SLOT, val[0]); val 200 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u8 short_preamble = (bool)*val; val 213 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c min_spacing_to_set = *val; val 224 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *val = min_spacing_to_set; val 238 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c density_to_set = *val; val 265 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c factor_toset = *(val); val 297 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u8 e_aci = *(val); val 308 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u8 e_aci = *(val); val 359 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); val 360 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtlpci->receive_config = ((u32 *) (val))[0]; val 364 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u8 retry_limit = val[0]; val 375 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtlefuse->efuse_usedbytes = *((u16 *) val); val 378 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtlefuse->efuse_usedpercentage = *val; val 381 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); val 384 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_SECCFG, *val); val 393 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); val 396 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *val | BIT(7)); val 402 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u8 psmode = *val; val 409 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl92c_set_fw_pwrmode_cmd(hw, *val); val 413 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c ppsc->fw_current_inpsmode = *((bool *) val); val 416 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u8 mstatus = *val; val 453 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl92c_set_fw_joinbss_report_cmd(hw, *val); val 458 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl92c_set_p2p_ps_offload_cmd(hw, *val); val 471 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u8 btype_ibss = val[0]; val 492 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c bool enter_fwlps = *((bool *)val); val 529 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c array[1] = *((u8 *)val); val 2254 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c u8 val; val 2259 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c val = hwinfo[RF_OPTION4]; val 2260 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtlpriv->btcoexist.eeprom_bt_type = ((val & 0xe) >> 1); val 2261 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtlpriv->btcoexist.eeprom_bt_ant_num = (val & 0x1); val 2262 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtlpriv->btcoexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4); val 2264 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c ((val & 0x20) >> 5); val 20 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.h void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 35 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.h void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 627 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c u8 desc_name, u8 *val) val 638 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c set_tx_desc_next_desc_address(pdesc, *(u32 *)val); val 652 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c set_rx_desc_buff_addr(pdesc, *(u32 *)val); val 655 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c set_rx_desc_pkt_len(pdesc, *(u32 *)val); val 523 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h u8 desc_name, u8 *val); val 1471 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 1479 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((u32 *)(val)) = mac->rx_conf; val 1482 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 1491 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((bool *) (val)) = true; val 1496 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((bool *) (val)) = false; val 1498 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((bool *) (val)) = true; val 1503 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((bool *) (val)) = ppsc->fw_current_inpsmode; val 1512 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((u64 *)(val)) = tsf; val 1516 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0); val 1519 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1); val 1522 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2); val 1548 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 1562 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c val[idx]); val 1567 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c u16 rate_cfg = ((u16 *) val)[0]; val 1591 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c val[idx]); val 1596 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]); val 1597 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]); val 1598 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); val 1599 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); val 1600 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]); val 1601 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]); val 1609 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_SLOT, val[0]); val 1611 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 1627 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c u1baifs = sifstime + (2 * val[0]); val 1641 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c u8 short_preamble = (bool)*val; val 1653 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c min_spacing_to_set = *val; val 1674 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *val = min_spacing_to_set; val 1686 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c density_to_set = *val; val 1704 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c factor_toset = *val; val 1731 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c u8 e_aci = *val; val 1771 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); val 1772 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c mac->rx_conf = ((u32 *) (val))[0]; val 1778 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c u8 retry_limit = val[0]; val 1792 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtlefuse->efuse_usedbytes = *((u16 *) val); val 1795 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtlefuse->efuse_usedpercentage = *val; val 1798 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); val 1801 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_SECCFG, *val); val 1807 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val); val 1810 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *val | BIT(7)); val 1814 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c u8 psmode = *val; val 1819 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl92c_set_fw_pwrmode_cmd(hw, (*val)); val 1823 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c ppsc->fw_current_inpsmode = *((bool *) val); val 1826 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c u8 mstatus = *val; val 1852 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl92c_set_fw_joinbss_report_cmd(hw, (*val)); val 1865 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c u8 btype_ibss = val[0]; val 1880 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val); val 1881 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c mac->rx_mgt_filter = *(u16 *)val; val 1884 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val); val 1885 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c mac->rx_ctrl_filter = *(u16 *)val; val 1888 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val); val 1889 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c mac->rx_data_filter = *(u16 *)val; val 1895 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c array[1] = *((u8 *)val); val 67 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.h void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 68 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.h void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 91 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 99 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((u32 *) (val)) = rtlpci->receive_config; val 102 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 111 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((bool *) (val)) = true; val 116 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((bool *) (val)) = false; val 118 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((bool *) (val)) = true; val 123 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((bool *) (val)) = ppsc->fw_current_inpsmode; val 132 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((u64 *) (val)) = tsf; val 136 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((bool *)(val)) = rtlpriv->dm.interrupt_migration; val 139 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((bool *)(val)) = rtlpriv->dm.disable_tx_int; val 149 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 163 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c val[idx]); val 167 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c u16 rate_cfg = ((u16 *) val)[0]; val 189 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c val[idx]); val 193 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); val 194 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); val 195 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); val 196 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); val 202 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *((u16 *) val)); val 208 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 209 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_SLOT, val[0]); val 218 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c u8 short_preamble = (bool) (*val); val 230 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c min_spacing_to_set = *val; val 237 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c *val = min_spacing_to_set; val 249 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c density_to_set = *val; val 271 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c factor_toset = *val; val 294 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c u8 e_aci = *val; val 302 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c u8 e_aci = *val; val 350 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); val 351 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtlpci->receive_config = ((u32 *) (val))[0]; val 354 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c u8 retry_limit = val[0]; val 365 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtlefuse->efuse_usedbytes = *((u16 *) val); val 368 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtlefuse->efuse_usedpercentage = *val; val 371 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val)); val 374 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_SECCFG, *val); val 377 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val)); val 382 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c ppsc->fw_current_inpsmode = *((bool *) val); val 385 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c u8 mstatus = (*val); val 413 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl92d_set_fw_joinbss_report_cmd(hw, (*val)); val 425 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c u8 btype_ibss = val[0]; val 441 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c bool int_migration = *(bool *) (val); val 458 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c bool disable_ac_int = *((bool *) val); val 7 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 22 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 749 drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c u8 desc_name, u8 *val) val 758 drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val); val 772 drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val); val 775 drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val); val 715 drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h u8 desc_name, u8 *val); val 274 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 282 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c *((u32 *)(val)) = rtlpci->receive_config; val 285 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 294 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c *((bool *)(val)) = true; val 299 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c *((bool *)(val)) = false; val 301 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c *((bool *)(val)) = true; val 306 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c *((bool *)(val)) = ppsc->fw_current_inpsmode; val 316 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c *((u64 *)(val)) = tsf; val 407 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 419 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]); val 422 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c u16 b_rate_cfg = ((u16 *)val)[0]; val 432 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]); val 435 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); val 436 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); val 438 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); val 439 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); val 445 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c *((u16 *)val)); val 451 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 453 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_SLOT, val[0]); val 462 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c u8 short_preamble = (bool)(*(u8 *)val); val 472 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); val 482 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c fac = *((u8 *)val); val 503 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c u8 e_aci = *((u8 *)val); val 511 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c u8 e_aci = *((u8 *)val); val 562 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); val 563 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtlpci->receive_config = ((u32 *)(val))[0]; val 567 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c u8 retry_limit = ((u8 *)(val))[0]; val 578 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c efuse->efuse_usedbytes = *((u16 *)val); val 581 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c efuse->efuse_usedpercentage = *((u8 *)val); val 584 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val)); val 593 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val)); val 596 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c ((*(u8 *)val) | BIT(7))); val 601 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); val 604 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c ppsc->fw_current_inpsmode = *((bool *)val); val 610 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c bool b_enter_fwlps = *((bool *)val); val 619 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c u8 mstatus = (*(u8 *)val); val 629 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); val 641 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c u8 btype_ibss = ((u8 *)(val))[0]; val 663 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c array[1] = *((u8 *)val); val 7 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.h void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 22 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.h void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 895 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c u8 desc_name, u8 *val) val 898 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c u8 q_idx = *val; val 905 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c set_tx_desc_next_desc_address(pdesc, *(u32 *)val); val 939 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c set_rx_buffer_physical_low(pdesc, (*(dma_addr_t *)val) & val 942 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c ((u64)(*(dma_addr_t *)val) val 267 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h u32 val, bool dma64) val 270 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h *(pbd + 4 * off + 2) = cpu_to_le32(val); val 310 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h static inline void set_tx_buff_desc_addr_high_0(__le32 *pdesc, u32 val, val 314 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h *(pdesc + 2) = cpu_to_le32(val); val 739 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h u8 desc_name, u8 *val); val 19 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 27 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c *((u32 *) (val)) = rtlpci->receive_config; val 31 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 35 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c *((bool *) (val)) = ppsc->fw_current_inpsmode; val 46 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c *((u64 *) (val)) = tsf; val 51 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; val 62 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 73 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]); val 74 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]); val 78 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u16 rate_cfg = ((u16 *) val)[0]; val 101 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]); val 103 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c ((u16 *)(val + 4))[0]); val 107 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]); val 108 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]); val 115 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 117 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, SLOT_TIME, val[0]); val 128 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u8 short_preamble = (bool) (*val); val 140 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c min_spacing_to_set = *val; val 157 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c *val = min_spacing_to_set; val 171 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c density_to_set = *val; val 193 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c factor_toset = *val; val 225 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u8 e_aci = *val; val 235 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u8 e_aci = *val; val 285 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]); val 286 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtlpci->receive_config = ((u32 *) (val))[0]; val 290 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u8 retry_limit = val[0]; val 301 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtlefuse->efuse_usedbytes = *((u16 *) val); val 305 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtlefuse->efuse_usedpercentage = *val; val 312 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, REG_SECR, *val); val 322 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c ppsc->fw_current_inpsmode = *((bool *) val); val 335 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c bool bmrc_toset = *((bool *)val); val 378 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c bool enter_fwlps = *((bool *)val); val 2516 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u32 val; val 2518 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c pci_read_config_dword(rtlpci->pdev, 0x40, &val); val 2519 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if ((val & 0x0000ff00) != 0) val 2521 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c val & 0xffff00ff); val 21 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.h u8 variable, u8 *val); val 39 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.h u8 *val); val 287 drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.c u8 index, u32 val) val 295 drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.c u32 writeval = val; val 552 drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c u8 desc_name, u8 *val) val 561 drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val); val 575 drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c SET_RX_STATUS__DESC_BUFF_ADDR(pdesc, *(u32 *) val); val 578 drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c SET_RX_STATUS_DESC_PKT_LEN(pdesc, *(u32 *) val); val 19 drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.h u8 desc_name, u8 *val); val 75 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 83 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *((u32 *)(val)) = rtlpci->receive_config; val 86 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 96 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *((bool *)(val)) = true; val 101 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *((bool *)(val)) = false; val 103 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *((bool *)(val)) = true; val 108 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *((bool *)(val)) = ppsc->fw_current_inpsmode; val 118 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *((u64 *)(val)) = tsf; val 131 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 144 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c val[idx]); val 149 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c u16 b_rate_cfg = ((u16 *)val)[0]; val 168 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c val[idx]); val 173 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); val 174 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); val 176 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); val 177 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); val 184 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *((u16 *)val)); val 191 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 193 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_SLOT, val[0]); val 204 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c u8 short_preamble = (bool)(*(u8 *)val); val 217 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c min_spacing_to_set = *((u8 *)val); val 228 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c *val = min_spacing_to_set; val 242 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c density_to_set = *((u8 *)val); val 268 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c factor_toset = *((u8 *)val); val 299 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c u8 e_aci = *((u8 *)val); val 310 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c u8 e_aci = *((u8 *)val); val 362 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); val 363 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtlpci->receive_config = ((u32 *)(val))[0]; val 367 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c u8 retry_limit = ((u8 *)(val))[0]; val 378 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtlefuse->efuse_usedbytes = *((u16 *)val); val 381 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtlefuse->efuse_usedpercentage = *((u8 *)val); val 384 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val)); val 387 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); val 397 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c (*(u8 *)val)); val 400 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c ((*(u8 *)val) | BIT(7))); val 406 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c u8 psmode = (*(u8 *)val); val 411 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); val 415 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c ppsc->fw_current_inpsmode = *((bool *)val); val 418 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c u8 mstatus = (*(u8 *)val); val 455 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val)); val 460 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); val 474 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c u8 btype_ibss = ((u8 *)(val))[0]; val 494 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c bool b_enter_fwlps = *((bool *)val); val 11 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.h void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 28 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.h void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 590 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c bool istx, u8 desc_name, u8 *val) val 600 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c set_tx_desc_next_desc_address(pdesc, *(u32 *)val); val 613 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c set_rx_desc_buff_addr(pdesc, *(u32 *)val); val 616 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c set_rx_desc_pkt_len(pdesc, *(u32 *)val); val 526 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h u8 *pdesc, bool istx, u8 desc_name, u8 *val); val 286 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 294 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *((u32 *)(val)) = rtlpci->receive_config; val 297 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 306 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *((bool *)(val)) = true; val 311 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *((bool *)(val)) = false; val 313 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *((bool *)(val)) = true; val 318 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *((bool *)(val)) = ppsc->fw_current_inpsmode; val 328 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *((u64 *)(val)) = tsf; val 390 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 402 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]); val 405 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c u16 b_rate_cfg = ((u16 *)val)[0]; val 420 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]); val 424 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); val 425 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); val 427 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); val 428 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); val 434 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *((u16 *)val)); val 440 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 442 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_SLOT, val[0]); val 452 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c u8 short_preamble = (bool)(*(u8 *)val); val 464 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); val 470 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c min_spacing_to_set = *((u8 *)val); val 480 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c *val = min_spacing_to_set; val 494 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c density_to_set = *((u8 *)val); val 513 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c factor_toset = *((u8 *)val); val 544 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c u8 e_aci = *((u8 *)val); val 553 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c u8 e_aci = *((u8 *)val); val 605 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); val 606 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtlpci->receive_config = ((u32 *)(val))[0]; val 609 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c u8 retry_limit = ((u8 *)(val))[0]; val 620 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtlefuse->efuse_usedbytes = *((u16 *)val); val 623 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtlefuse->efuse_usedpercentage = *((u8 *)val); val 626 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val)); val 635 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val)); val 638 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c ((*(u8 *)val) | BIT(7))); val 643 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); val 646 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c ppsc->fw_current_inpsmode = *((bool *)val); val 652 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c bool b_enter_fwlps = *((bool *)val); val 661 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c u8 mstatus = (*(u8 *)val); val 671 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); val 682 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c u8 btype_ibss = ((u8 *)(val))[0]; val 703 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c array[1] = *((u8 *)val); val 7 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.h void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 24 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.h void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 643 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c bool istx, u8 desc_name, u8 *val) val 653 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c set_tx_desc_next_desc_address(pdesc, *(u32 *)val); val 666 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c set_rx_desc_buff_addr(pdesc, *(u32 *)val); val 669 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c set_rx_desc_pkt_len(pdesc, *(u32 *)val); val 638 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h bool istx, u8 desc_name, u8 *val); val 108 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c u8 val; val 112 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c val = rtl_read_byte(rtlpriv, REG_HMETFR); val 115 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c } while ((val & 0x0F) && (count < 1000)); val 388 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 397 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID); val 398 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4); val 401 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID); val 402 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4); val 405 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3; val 408 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u8 *)(val)) = mac->slot_time; val 411 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL); val 414 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND); val 417 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u32 *)(val)) = rtlpci->receive_config; val 420 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; val 430 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((bool *)(val)) = true; val 435 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((bool *)(val)) = false; val 437 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((bool *)(val)) = true; val 441 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((bool *)(val)) = ppsc->fw_current_inpsmode; val 451 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((u64 *)(val)) = tsf; val 456 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((bool *)(val)) = true; val 458 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *((bool *)(val)) = false; val 467 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) val 481 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c val[idx]); val 486 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u16 b_rate_cfg = ((u16 *)val)[0]; val 494 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c val[idx]); val 499 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); val 500 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]); val 502 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); val 503 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); val 505 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); val 506 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]); val 509 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); val 515 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c "HW_VAR_SLOT_TIME %x\n", val[0]); val 517 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_SLOT, val[0]); val 527 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 short_preamble = (bool)(*(u8 *)val); val 542 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); val 548 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c min_spacing_to_set = *((u8 *)val); val 559 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c *val = min_spacing_to_set; val 572 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c density_to_set = *((u8 *)val); val 584 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u32 ampdu_len = (*((u8 *)val)); val 589 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c (0x2000 << (*((u8 *)val))) - 1; val 595 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c (0x2000 << (*((u8 *)val))) - 1; val 605 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 e_aci = *((u8 *)val); val 614 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 e_aci = *((u8 *)val); val 665 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); val 666 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlpci->receive_config = ((u32 *)(val))[0]; val 669 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 retry_limit = ((u8 *)(val))[0]; val 679 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlefuse->efuse_usedbytes = *((u16 *)val); val 682 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlefuse->efuse_usedpercentage = *((u8 *)val); val 685 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val)); val 695 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c (*(u8 *)val)); val 698 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c ((*(u8 *)val) | BIT(7))); val 703 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); val 706 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c ppsc->fw_current_inpsmode = *((bool *)val); val 714 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c bool b_enter_fwlps = *((bool *)val); val 722 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 mstatus = (*(u8 *)val); val 733 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); val 743 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 btype_ibss = ((u8 *)(val))[0]; val 761 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u32 us_nav_upper = *(u32 *)val; val 777 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c array[1] = *((u8 *)val); val 7 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.h void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 24 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.h void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); val 1794 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u8 *val = array[i+6]; val 1798 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c chnl, val); val 879 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c bool istx, u8 desc_name, u8 *val) val 889 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c set_tx_desc_next_desc_address(pdesc, *(u32 *)val); val 903 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c set_rx_desc_buff_addr(pdesc, *(u32 *)val); val 906 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c set_rx_desc_pkt_len(pdesc, *(u32 *)val); val 644 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h bool istx, u8 desc_name, u8 *val); val 160 drivers/net/wireless/realtek/rtlwifi/usb.c static void _usb_write_async(struct usb_device *udev, u32 addr, u32 val, val 171 drivers/net/wireless/realtek/rtlwifi/usb.c data = cpu_to_le32(val); val 176 drivers/net/wireless/realtek/rtlwifi/usb.c static void _usb_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val) val 180 drivers/net/wireless/realtek/rtlwifi/usb.c _usb_write_async(to_usb_device(dev), addr, val, 1); val 183 drivers/net/wireless/realtek/rtlwifi/usb.c static void _usb_write16_async(struct rtl_priv *rtlpriv, u32 addr, u16 val) val 187 drivers/net/wireless/realtek/rtlwifi/usb.c _usb_write_async(to_usb_device(dev), addr, val, 2); val 190 drivers/net/wireless/realtek/rtlwifi/usb.c static void _usb_write32_async(struct rtl_priv *rtlpriv, u32 addr, u32 val) val 194 drivers/net/wireless/realtek/rtlwifi/usb.c _usb_write_async(to_usb_device(dev), addr, val, 4); val 1466 drivers/net/wireless/realtek/rtlwifi/wifi.h void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val); val 1467 drivers/net/wireless/realtek/rtlwifi/wifi.h void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val); val 1468 drivers/net/wireless/realtek/rtlwifi/wifi.h void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val); val 2243 drivers/net/wireless/realtek/rtlwifi/wifi.h void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val); val 2244 drivers/net/wireless/realtek/rtlwifi/wifi.h void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val); val 2284 drivers/net/wireless/realtek/rtlwifi/wifi.h u8 desc_name, u8 *val); val 2731 drivers/net/wireless/realtek/rtlwifi/wifi.h u8 *val; val 258 drivers/net/wireless/realtek/rtw88/coex.c u16 val = 0x2; val 263 drivers/net/wireless/realtek/rtw88/coex.c val |= coex_stat->score_board; val 270 drivers/net/wireless/realtek/rtw88/coex.c val &= ~COEX_SCBD_FIX2M; val 272 drivers/net/wireless/realtek/rtw88/coex.c val |= COEX_SCBD_FIX2M; val 275 drivers/net/wireless/realtek/rtw88/coex.c val |= bitpos; val 277 drivers/net/wireless/realtek/rtw88/coex.c val &= ~bitpos; val 280 drivers/net/wireless/realtek/rtw88/coex.c if (val != coex_stat->score_board) { val 281 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->score_board = val; val 282 drivers/net/wireless/realtek/rtw88/coex.c val |= BIT_BT_INT_EN; val 283 drivers/net/wireless/realtek/rtw88/coex.c rtw_write16(rtwdev, REG_WIFI_BT_INFO, val); val 726 drivers/net/wireless/realtek/rtw88/coex.c u32 val; val 728 drivers/net/wireless/realtek/rtw88/coex.c if (!ltecoex_read_reg(rtwdev, addr, &val)) { val 733 drivers/net/wireless/realtek/rtw88/coex.c return val; val 737 drivers/net/wireless/realtek/rtw88/coex.c u32 mask, u32 val) val 743 drivers/net/wireless/realtek/rtw88/coex.c tmp = (tmp & (~mask)) | ((val << shift) & mask); val 2439 drivers/net/wireless/realtek/rtw88/coex.c u8 val; val 2449 drivers/net/wireless/realtek/rtw88/coex.c val = coex_stat->wl_fw_dbg_info_pre[i]; val 2450 drivers/net/wireless/realtek/rtw88/coex.c if (buf[i] >= val) val 2451 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->wl_fw_dbg_info[i] = buf[i] - val; val 2453 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->wl_fw_dbg_info[i] = val - buf[i]; val 351 drivers/net/wireless/realtek/rtw88/coex.h u32 mask, u32 val); val 103 drivers/net/wireless/realtek/rtw88/debug.c u32 val, len, addr; val 109 drivers/net/wireless/realtek/rtw88/debug.c val = rtw_read8(rtwdev, addr); val 110 drivers/net/wireless/realtek/rtw88/debug.c seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); val 113 drivers/net/wireless/realtek/rtw88/debug.c val = rtw_read16(rtwdev, addr); val 114 drivers/net/wireless/realtek/rtw88/debug.c seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); val 117 drivers/net/wireless/realtek/rtw88/debug.c val = rtw_read32(rtwdev, addr); val 118 drivers/net/wireless/realtek/rtw88/debug.c seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); val 128 drivers/net/wireless/realtek/rtw88/debug.c u32 val, addr, mask; val 135 drivers/net/wireless/realtek/rtw88/debug.c val = rtw_read_rf(rtwdev, path, addr, mask); val 138 drivers/net/wireless/realtek/rtw88/debug.c path, addr, mask, val); val 194 drivers/net/wireless/realtek/rtw88/debug.c u32 val, command; val 206 drivers/net/wireless/realtek/rtw88/debug.c val = rtw_read32(rtwdev, RTW_SEC_READ_REG); val 207 drivers/net/wireless/realtek/rtw88/debug.c seq_printf(m, "%8.8x", val); val 310 drivers/net/wireless/realtek/rtw88/debug.c u32 addr, val, len; val 316 drivers/net/wireless/realtek/rtw88/debug.c num = sscanf(tmp, "%x %x %x", &addr, &val, &len); val 324 drivers/net/wireless/realtek/rtw88/debug.c "reg write8 0x%03x: 0x%08x\n", addr, val); val 325 drivers/net/wireless/realtek/rtw88/debug.c rtw_write8(rtwdev, addr, (u8)val); val 329 drivers/net/wireless/realtek/rtw88/debug.c "reg write16 0x%03x: 0x%08x\n", addr, val); val 330 drivers/net/wireless/realtek/rtw88/debug.c rtw_write16(rtwdev, addr, (u16)val); val 334 drivers/net/wireless/realtek/rtw88/debug.c "reg write32 0x%03x: 0x%08x\n", addr, val); val 335 drivers/net/wireless/realtek/rtw88/debug.c rtw_write32(rtwdev, addr, (u32)val); val 353 drivers/net/wireless/realtek/rtw88/debug.c u32 path, addr, mask, val; val 358 drivers/net/wireless/realtek/rtw88/debug.c num = sscanf(tmp, "%x %x %x %x", &path, &addr, &mask, &val); val 365 drivers/net/wireless/realtek/rtw88/debug.c rtw_write_rf(rtwdev, path, addr, mask, val); val 368 drivers/net/wireless/realtek/rtw88/debug.c path, addr, mask, val); val 404 drivers/net/wireless/realtek/rtw88/debug.c u32 val; val 409 drivers/net/wireless/realtek/rtw88/debug.c val = rtw_read32(rtwdev, debugfs_priv->cb_data); val 424 drivers/net/wireless/realtek/rtw88/debug.c u32 val; val 429 drivers/net/wireless/realtek/rtw88/debug.c val = rtw_read32(rtwdev, debugfs_priv->cb_data); val 547 drivers/net/wireless/realtek/rtw88/fw.c u8 val; val 559 drivers/net/wireless/realtek/rtw88/fw.c val = rtw_read8(rtwdev, REG_CR + 1); val 560 drivers/net/wireless/realtek/rtw88/fw.c bckp[0] = val; val 561 drivers/net/wireless/realtek/rtw88/fw.c val |= BIT_ENSWBCN >> 8; val 562 drivers/net/wireless/realtek/rtw88/fw.c rtw_write8(rtwdev, REG_CR + 1, val); val 564 drivers/net/wireless/realtek/rtw88/fw.c val = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL + 2); val 565 drivers/net/wireless/realtek/rtw88/fw.c bckp[1] = val; val 566 drivers/net/wireless/realtek/rtw88/fw.c val &= ~(BIT_EN_BCNQ_DL >> 16); val 567 drivers/net/wireless/realtek/rtw88/fw.c rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 2, val); val 23 drivers/net/wireless/realtek/rtw88/hci.h void (*write8)(struct rtw_dev *rtwdev, u32 addr, u8 val); val 24 drivers/net/wireless/realtek/rtw88/hci.h void (*write16)(struct rtw_dev *rtwdev, u32 addr, u16 val); val 25 drivers/net/wireless/realtek/rtw88/hci.h void (*write32)(struct rtw_dev *rtwdev, u32 addr, u32 val); val 77 drivers/net/wireless/realtek/rtw88/hci.h static inline void rtw_write8(struct rtw_dev *rtwdev, u32 addr, u8 val) val 79 drivers/net/wireless/realtek/rtw88/hci.h rtwdev->hci.ops->write8(rtwdev, addr, val); val 82 drivers/net/wireless/realtek/rtw88/hci.h static inline void rtw_write16(struct rtw_dev *rtwdev, u32 addr, u16 val) val 84 drivers/net/wireless/realtek/rtw88/hci.h rtwdev->hci.ops->write16(rtwdev, addr, val); val 87 drivers/net/wireless/realtek/rtw88/hci.h static inline void rtw_write32(struct rtw_dev *rtwdev, u32 addr, u32 val) val 89 drivers/net/wireless/realtek/rtw88/hci.h rtwdev->hci.ops->write32(rtwdev, addr, val); val 94 drivers/net/wireless/realtek/rtw88/hci.h u8 val; val 96 drivers/net/wireless/realtek/rtw88/hci.h val = rtw_read8(rtwdev, addr); val 97 drivers/net/wireless/realtek/rtw88/hci.h rtw_write8(rtwdev, addr, val | bit); val 102 drivers/net/wireless/realtek/rtw88/hci.h u16 val; val 104 drivers/net/wireless/realtek/rtw88/hci.h val = rtw_read16(rtwdev, addr); val 105 drivers/net/wireless/realtek/rtw88/hci.h rtw_write16(rtwdev, addr, val | bit); val 110 drivers/net/wireless/realtek/rtw88/hci.h u32 val; val 112 drivers/net/wireless/realtek/rtw88/hci.h val = rtw_read32(rtwdev, addr); val 113 drivers/net/wireless/realtek/rtw88/hci.h rtw_write32(rtwdev, addr, val | bit); val 118 drivers/net/wireless/realtek/rtw88/hci.h u8 val; val 120 drivers/net/wireless/realtek/rtw88/hci.h val = rtw_read8(rtwdev, addr); val 121 drivers/net/wireless/realtek/rtw88/hci.h rtw_write8(rtwdev, addr, val & ~bit); val 126 drivers/net/wireless/realtek/rtw88/hci.h u16 val; val 128 drivers/net/wireless/realtek/rtw88/hci.h val = rtw_read16(rtwdev, addr); val 129 drivers/net/wireless/realtek/rtw88/hci.h rtw_write16(rtwdev, addr, val & ~bit); val 134 drivers/net/wireless/realtek/rtw88/hci.h u32 val; val 136 drivers/net/wireless/realtek/rtw88/hci.h val = rtw_read32(rtwdev, addr); val 137 drivers/net/wireless/realtek/rtw88/hci.h rtw_write32(rtwdev, addr, val & ~bit); val 145 drivers/net/wireless/realtek/rtw88/hci.h u32 val; val 148 drivers/net/wireless/realtek/rtw88/hci.h val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); val 151 drivers/net/wireless/realtek/rtw88/hci.h return val; val 363 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1); val 371 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR); val 375 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].val = BIT_H2CQ_FULL; val 384 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1); val 388 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN; val 391 drivers/net/wireless/realtek/rtw88/mac.c rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val); val 397 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].val = tmp; val 529 drivers/net/wireless/realtek/rtw88/mac.c u32 val; val 536 drivers/net/wireless/realtek/rtw88/mac.c val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL); val 537 drivers/net/wireless/realtek/rtw88/mac.c val |= BIT_DDMACH0_RESET_CHKSUM_STS; val 538 drivers/net/wireless/realtek/rtw88/mac.c rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val); val 591 drivers/net/wireless/realtek/rtw88/mac.c u16 val; val 606 drivers/net/wireless/realtek/rtw88/mac.c val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800); val 607 drivers/net/wireless/realtek/rtw88/mac.c val |= BIT_MCUFWDL_EN; val 608 drivers/net/wireless/realtek/rtw88/mac.c rtw_write16(rtwdev, REG_MCUFW_CTRL, val); val 440 drivers/net/wireless/realtek/rtw88/main.h u32 val; val 1404 drivers/net/wireless/realtek/rtw88/main.h bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); val 65 drivers/net/wireless/realtek/rtw88/pci.c static void rtw_pci_write8(struct rtw_dev *rtwdev, u32 addr, u8 val) val 69 drivers/net/wireless/realtek/rtw88/pci.c writeb(val, rtwpci->mmap + addr); val 72 drivers/net/wireless/realtek/rtw88/pci.c static void rtw_pci_write16(struct rtw_dev *rtwdev, u32 addr, u16 val) val 76 drivers/net/wireless/realtek/rtw88/pci.c writew(val, rtwpci->mmap + addr); val 79 drivers/net/wireless/realtek/rtw88/pci.c static void rtw_pci_write32(struct rtw_dev *rtwdev, u32 addr, u32 val) val 83 drivers/net/wireless/realtek/rtw88/pci.c writel(val, rtwpci->mmap + addr); val 674 drivers/net/wireless/realtek/rtw88/phy.c u32 val, direct_addr; val 685 drivers/net/wireless/realtek/rtw88/phy.c val = rtw_read32_mask(rtwdev, direct_addr, mask); val 687 drivers/net/wireless/realtek/rtw88/phy.c return val; val 864 drivers/net/wireless/realtek/rtw88/phy.c #define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8)) val 876 drivers/net/wireless/realtek/rtw88/phy.c u32 addr, u32 mask, u32 val, u8 *rate, val 889 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 899 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 904 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1); val 914 drivers/net/wireless/realtek/rtw88/phy.c tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 918 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0); val 929 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 939 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 949 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 959 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 968 drivers/net/wireless/realtek/rtw88/phy.c val, i); val 980 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 992 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1004 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1016 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1028 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1040 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1052 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1064 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1076 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1088 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1100 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1112 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1124 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1136 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1148 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1160 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 1170 drivers/net/wireless/realtek/rtw88/phy.c pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); val 77 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 val; val 88 drivers/net/wireless/realtek/rtw88/rtw8822c.c backup[i].val = rtw_read32(rtwdev, addrs[i]); val 94 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); val 96 drivers/net/wireless/realtek/rtw88/rtw8822c.c backup_rf[path * i + i].val = val; val 106 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 val; val 113 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = backup_rf[path * i + i].val; val 115 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); val 183 drivers/net/wireless/realtek/rtw88/rtw8822c.c static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) val 206 drivers/net/wireless/realtek/rtw88/rtw8822c.c *val = t; val 630 drivers/net/wireless/realtek/rtw88/rtw8822c.c u16 val; val 638 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); val 639 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_msbk[path][vec][i] = val; val 666 drivers/net/wireless/realtek/rtw88/rtw8822c.c u8 val; val 668 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); val 669 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_dck[RF_PATH_A][0][0] = val; val 670 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); val 671 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_dck[RF_PATH_A][0][1] = val; val 672 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); val 673 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_dck[RF_PATH_A][1][0] = val; val 674 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); val 675 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_dck[RF_PATH_A][1][1] = val; val 677 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); val 678 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_dck[RF_PATH_B][0][0] = val; val 679 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); val 680 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_dck[RF_PATH_B][1][0] = val; val 681 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); val 682 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_dck[RF_PATH_B][0][1] = val; val 683 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); val 684 drivers/net/wireless/realtek/rtw88/rtw8822c.c dm_info->dack_dck[RF_PATH_B][1][1] = val; val 720 drivers/net/wireless/realtek/rtw88/rtw8822c.c u8 val; val 723 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = dm_info->dack_dck[RF_PATH_A][0][0]; val 724 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); val 725 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = dm_info->dack_dck[RF_PATH_A][0][1]; val 726 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); val 729 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = dm_info->dack_dck[RF_PATH_A][1][0]; val 730 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); val 731 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = dm_info->dack_dck[RF_PATH_A][1][1]; val 732 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); val 735 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = dm_info->dack_dck[RF_PATH_B][0][0]; val 736 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); val 737 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = dm_info->dack_dck[RF_PATH_B][0][1]; val 738 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); val 741 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = dm_info->dack_dck[RF_PATH_B][1][0]; val 742 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); val 743 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = dm_info->dack_dck[RF_PATH_B][1][1]; val 744 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); val 2108 drivers/net/wireless/realtek/rtw88/rtw8822c.c bckp[i].val = rtw_read32(rtwdev, reg[i]); val 2386 drivers/net/wireless/realtek/rtw88/rtw8822c.c static u32 rtw8822c_psd_log2base(u32 val) val 2394 drivers/net/wireless/realtek/rtw88/rtw8822c.c if (val == 0) val 2397 drivers/net/wireless/realtek/rtw88/rtw8822c.c val_integerd_b = __fls(val) + 1; val 2399 drivers/net/wireless/realtek/rtw88/rtw8822c.c tmp = (val * 100) / (1 << val_integerd_b); val 23 drivers/net/wireless/realtek/rtw88/util.c bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val) val 29 drivers/net/wireless/realtek/rtw88/util.c *val = rtw_read32(rtwdev, LTECOEX_READ_DATA); val 50 drivers/net/wireless/realtek/rtw88/util.c u32 val; val 56 drivers/net/wireless/realtek/rtw88/util.c val = bckp->val; val 60 drivers/net/wireless/realtek/rtw88/util.c rtw_write8(rtwdev, reg, (u8)val); val 63 drivers/net/wireless/realtek/rtw88/util.c rtw_write16(rtwdev, reg, (u16)val); val 66 drivers/net/wireless/realtek/rtw88/util.c rtw_write32(rtwdev, reg, (u32)val); val 62 drivers/net/wireless/st/cw1200/fwio.c #define APB_WRITE(reg, val) \ val 64 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \ val 68 drivers/net/wireless/st/cw1200/fwio.c #define APB_WRITE2(reg, val) \ val 70 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \ val 74 drivers/net/wireless/st/cw1200/fwio.c #define APB_READ(reg, val) \ val 76 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \ val 80 drivers/net/wireless/st/cw1200/fwio.c #define REG_WRITE(reg, val) \ val 82 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_reg_write_32(priv, (reg), (val)); \ val 86 drivers/net/wireless/st/cw1200/fwio.c #define REG_READ(reg, val) \ val 88 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_reg_read_32(priv, (reg), &(val)); \ val 265 drivers/net/wireless/st/cw1200/fwio.c static int config_reg_read(struct cw1200_common *priv, u32 *val) val 275 drivers/net/wireless/st/cw1200/fwio.c *val = val16; val 281 drivers/net/wireless/st/cw1200/fwio.c cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val); val 287 drivers/net/wireless/st/cw1200/fwio.c static int config_reg_write(struct cw1200_common *priv, u32 val) val 293 drivers/net/wireless/st/cw1200/fwio.c (u16)val); val 297 drivers/net/wireless/st/cw1200/fwio.c return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val); val 67 drivers/net/wireless/st/cw1200/hwio.c u16 addr, u32 *val) val 71 drivers/net/wireless/st/cw1200/hwio.c *val = le32_to_cpu(tmp); val 76 drivers/net/wireless/st/cw1200/hwio.c u16 addr, u32 val) val 78 drivers/net/wireless/st/cw1200/hwio.c __le32 tmp = cpu_to_le32(val); val 83 drivers/net/wireless/st/cw1200/hwio.c u16 addr, u16 *val) val 87 drivers/net/wireless/st/cw1200/hwio.c *val = le16_to_cpu(tmp); val 92 drivers/net/wireless/st/cw1200/hwio.c u16 addr, u16 val) val 94 drivers/net/wireless/st/cw1200/hwio.c __le16 tmp = cpu_to_le16(val); val 167 drivers/net/wireless/st/cw1200/hwio.h u16 addr, u16 *val) val 172 drivers/net/wireless/st/cw1200/hwio.h *val = le32_to_cpu(tmp) & 0xfffff; val 177 drivers/net/wireless/st/cw1200/hwio.h u16 addr, u16 val) val 179 drivers/net/wireless/st/cw1200/hwio.h __le32 tmp = cpu_to_le32((u32)val); val 184 drivers/net/wireless/st/cw1200/hwio.h u16 addr, u32 *val) val 188 drivers/net/wireless/st/cw1200/hwio.h *val = le32_to_cpu(tmp); val 193 drivers/net/wireless/st/cw1200/hwio.h u16 addr, u32 val) val 195 drivers/net/wireless/st/cw1200/hwio.h __le32 tmp = cpu_to_le32(val); val 196 drivers/net/wireless/st/cw1200/hwio.h return cw1200_reg_write(priv, addr, &tmp, sizeof(val)); val 221 drivers/net/wireless/st/cw1200/hwio.h u32 addr, u32 *val) val 225 drivers/net/wireless/st/cw1200/hwio.h *val = le32_to_cpu(tmp); val 230 drivers/net/wireless/st/cw1200/hwio.h u32 addr, u32 val) val 232 drivers/net/wireless/st/cw1200/hwio.h __le32 tmp = cpu_to_le32(val); val 233 drivers/net/wireless/st/cw1200/hwio.h return cw1200_apb_write(priv, addr, &tmp, sizeof(val)); val 236 drivers/net/wireless/st/cw1200/hwio.h u32 addr, u32 *val) val 240 drivers/net/wireless/st/cw1200/hwio.h *val = le32_to_cpu(tmp); val 44 drivers/net/wireless/st/cw1200/wsm.c type val; \ val 47 drivers/net/wireless/st/cw1200/wsm.c val = cvt(*(type2 *)(buf)->data); \ val 49 drivers/net/wireless/st/cw1200/wsm.c val; \ val 65 drivers/net/wireless/st/cw1200/wsm.c #define __WSM_PUT(buf, val, type, type2, cvt) \ val 70 drivers/net/wireless/st/cw1200/wsm.c *(type2 *)(buf)->data = cvt(val); \ val 74 drivers/net/wireless/st/cw1200/wsm.c #define WSM_PUT8(buf, val) __WSM_PUT(buf, val, u8, u8, (u8)) val 75 drivers/net/wireless/st/cw1200/wsm.c #define WSM_PUT16(buf, val) __WSM_PUT(buf, val, u16, __le16, __cpu_to_le16) val 76 drivers/net/wireless/st/cw1200/wsm.c #define WSM_PUT32(buf, val) __WSM_PUT(buf, val, u32, __le32, __cpu_to_le32) val 1289 drivers/net/wireless/st/cw1200/wsm.h __le32 val = __cpu_to_le32(power_level); val 1291 drivers/net/wireless/st/cw1200/wsm.h &val, sizeof(val)); val 1302 drivers/net/wireless/st/cw1200/wsm.h } val = { val 1310 drivers/net/wireless/st/cw1200/wsm.h &val, sizeof(val)); val 1374 drivers/net/wireless/st/cw1200/wsm.h __le32 val = 0; val 1376 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(0)); val 1378 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(1)); val 1380 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(2)); val 1382 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(3)); val 1383 drivers/net/wireless/st/cw1200/wsm.h return wsm_write_mib(priv, WSM_MIB_ID_RX_FILTER, &val, sizeof(val)); val 1428 drivers/net/wireless/st/cw1200/wsm.h } val; val 1429 drivers/net/wireless/st/cw1200/wsm.h val.enabled = __cpu_to_le32(arg->enabled); val 1430 drivers/net/wireless/st/cw1200/wsm.h val.bcn_count = __cpu_to_le32(arg->bcn_count); val 1431 drivers/net/wireless/st/cw1200/wsm.h return wsm_write_mib(priv, WSM_MIB_ID_BEACON_FILTER_ENABLE, &val, val 1432 drivers/net/wireless/st/cw1200/wsm.h sizeof(val)); val 1450 drivers/net/wireless/st/cw1200/wsm.h u8 val = arg->power_mode; val 1452 drivers/net/wireless/st/cw1200/wsm.h val |= BIT(4); val 1454 drivers/net/wireless/st/cw1200/wsm.h val |= BIT(5); val 1455 drivers/net/wireless/st/cw1200/wsm.h return wsm_write_mib(priv, WSM_MIB_ID_OPERATIONAL_POWER_MODE, &val, val 1456 drivers/net/wireless/st/cw1200/wsm.h sizeof(val)); val 1488 drivers/net/wireless/st/cw1200/wsm.h __le32 val = 0; val 1491 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(0)); val 1493 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(1)); val 1495 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(2)); val 1497 drivers/net/wireless/st/cw1200/wsm.h &val, sizeof(val)); val 1512 drivers/net/wireless/st/cw1200/wsm.h struct wsm_mib_block_ack_policy val = { val 1516 drivers/net/wireless/st/cw1200/wsm.h return wsm_write_mib(priv, WSM_MIB_ID_BLOCK_ACK_POLICY, &val, val 1517 drivers/net/wireless/st/cw1200/wsm.h sizeof(val)); val 392 drivers/net/wireless/ti/wl1251/boot.c u32 dest_addr, val; val 421 drivers/net/wireless/ti/wl1251/boot.c val = (nvs_ptr[0] | (nvs_ptr[1] << 8) val 426 drivers/net/wireless/ti/wl1251/boot.c dest_addr, val); val 427 drivers/net/wireless/ti/wl1251/boot.c wl1251_mem_write32(wl, dest_addr, val); val 451 drivers/net/wireless/ti/wl1251/boot.c val = (nvs_ptr[0] | (nvs_ptr[1] << 8) val 456 drivers/net/wireless/ti/wl1251/boot.c nvs_start, val); val 457 drivers/net/wireless/ti/wl1251/boot.c wl1251_mem_write32(wl, nvs_start, val); val 72 drivers/net/wireless/ti/wl1251/io.c void wl1251_mem_write32(struct wl1251 *wl, int addr, u32 val) val 74 drivers/net/wireless/ti/wl1251/io.c wl1251_write32(wl, wl1251_translate_mem_addr(wl, addr), val); val 82 drivers/net/wireless/ti/wl1251/io.c void wl1251_reg_write32(struct wl1251 *wl, int addr, u32 val) val 84 drivers/net/wireless/ti/wl1251/io.c wl1251_write32(wl, wl1251_translate_reg_addr(wl, addr), val); val 30 drivers/net/wireless/ti/wl1251/io.h static inline void wl1251_write32(struct wl1251 *wl, int addr, u32 val) val 32 drivers/net/wireless/ti/wl1251/io.h wl->buffer_32 = cpu_to_le32(val); val 48 drivers/net/wireless/ti/wl1251/io.h static inline void wl1251_write_elp(struct wl1251 *wl, int addr, u32 val) val 51 drivers/net/wireless/ti/wl1251/io.h wl->if_ops->write_elp(wl, addr, val); val 53 drivers/net/wireless/ti/wl1251/io.h wl->if_ops->write(wl, addr, &val, sizeof(u32)); val 60 drivers/net/wireless/ti/wl1251/io.h void wl1251_mem_write32(struct wl1251 *wl, int addr, u32 val); val 63 drivers/net/wireless/ti/wl1251/io.h void wl1251_reg_write32(struct wl1251 *wl, int addr, u32 val); val 84 drivers/net/wireless/ti/wl1251/sdio.c static void wl1251_sdio_read_elp(struct wl1251 *wl, int addr, u32 *val) val 97 drivers/net/wireless/ti/wl1251/sdio.c *val = sdio_writeb_readb(func, wl_sdio->elp_val, addr, &ret); val 104 drivers/net/wireless/ti/wl1251/sdio.c static void wl1251_sdio_write_elp(struct wl1251 *wl, int addr, u32 val) val 111 drivers/net/wireless/ti/wl1251/sdio.c sdio_writeb(func, val, addr, &ret); val 117 drivers/net/wireless/ti/wl1251/sdio.c wl_sdio->elp_val = val; val 250 drivers/net/wireless/ti/wl1251/wl1251.h void (*read_elp)(struct wl1251 *wl, int addr, u32 *val); val 251 drivers/net/wireless/ti/wl1251/wl1251.h void (*write_elp)(struct wl1251 *wl, int addr, u32 val); val 722 drivers/net/wireless/ti/wl12xx/main.c u16 val) val 733 drivers/net/wireless/ti/wl12xx/main.c ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val); val 749 drivers/net/wireless/ti/wl12xx/main.c u32 val; val 766 drivers/net/wireless/ti/wl12xx/main.c ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val); val 769 drivers/net/wireless/ti/wl12xx/main.c } while (!(val & OCP_READY_MASK) && --timeout); val 777 drivers/net/wireless/ti/wl12xx/main.c if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) { val 783 drivers/net/wireless/ti/wl12xx/main.c *out = val & 0xffff; val 986 drivers/net/wireless/ti/wl12xx/main.c u16 val; val 988 drivers/net/wireless/ti/wl12xx/main.c ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val); val 992 drivers/net/wireless/ti/wl12xx/main.c val &= FREF_CLK_TYPE_BITS; val 993 drivers/net/wireless/ti/wl12xx/main.c ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val); val 998 drivers/net/wireless/ti/wl12xx/main.c ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val); val 1002 drivers/net/wireless/ti/wl12xx/main.c val |= NO_PULL; val 1003 drivers/net/wireless/ti/wl12xx/main.c ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val); val 1007 drivers/net/wireless/ti/wl12xx/main.c u16 val; val 1009 drivers/net/wireless/ti/wl12xx/main.c ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val); val 1013 drivers/net/wireless/ti/wl12xx/main.c val &= FREF_CLK_POLARITY_BITS; val 1014 drivers/net/wireless/ti/wl12xx/main.c val |= CLK_REQ_OUTN_SEL; val 1015 drivers/net/wireless/ti/wl12xx/main.c ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); val 13 drivers/net/wireless/ti/wl18xx/io.c int wl18xx_top_reg_write(struct wl1271 *wl, int addr, u16 val) val 26 drivers/net/wireless/ti/wl18xx/io.c tmp = (tmp & 0xffff0000) | val; val 33 drivers/net/wireless/ti/wl18xx/io.c tmp = (tmp & 0xffff) | (val << 16); val 43 drivers/net/wireless/ti/wl18xx/io.c u32 val = 0; val 51 drivers/net/wireless/ti/wl18xx/io.c ret = wlcore_read32(wl, addr, &val); val 53 drivers/net/wireless/ti/wl18xx/io.c *out = val & 0xffff; val 55 drivers/net/wireless/ti/wl18xx/io.c ret = wlcore_read32(wl, addr - 2, &val); val 57 drivers/net/wireless/ti/wl18xx/io.c *out = (val & 0xffff0000) >> 16; val 11 drivers/net/wireless/ti/wl18xx/io.h int __must_check wl18xx_top_reg_write(struct wl1271 *wl, int addr, u16 val); val 276 drivers/net/wireless/ti/wlcore/boot.c u32 dest_addr, val; val 374 drivers/net/wireless/ti/wlcore/boot.c val = (nvs_ptr[0] | (nvs_ptr[1] << 8) val 379 drivers/net/wireless/ti/wlcore/boot.c dest_addr, val); val 380 drivers/net/wireless/ti/wlcore/boot.c ret = wlcore_write32(wl, dest_addr, val); val 95 drivers/net/wireless/ti/wlcore/io.h u32 *val) val 104 drivers/net/wireless/ti/wlcore/io.h if (val) val 105 drivers/net/wireless/ti/wlcore/io.h *val = le32_to_cpu(*wl->buffer_32); val 111 drivers/net/wireless/ti/wlcore/io.h u32 val) val 113 drivers/net/wireless/ti/wlcore/io.h *wl->buffer_32 = cpu_to_le32(val); val 168 drivers/net/wireless/ti/wlcore/io.h u32 *val) val 170 drivers/net/wireless/ti/wlcore/io.h return wlcore_raw_read32(wl, wlcore_translate_addr(wl, addr), val); val 174 drivers/net/wireless/ti/wlcore/io.h u32 val) val 176 drivers/net/wireless/ti/wlcore/io.h return wlcore_raw_write32(wl, wlcore_translate_addr(wl, addr), val); val 180 drivers/net/wireless/ti/wlcore/io.h u32 *val) val 184 drivers/net/wireless/ti/wlcore/io.h val); val 188 drivers/net/wireless/ti/wlcore/io.h u32 val) val 192 drivers/net/wireless/ti/wlcore/io.h val); val 278 drivers/net/wireless/ti/wlcore/testmode.c u32 val; val 286 drivers/net/wireless/ti/wlcore/testmode.c val = nla_get_u32(tb[WL1271_TM_ATTR_PLT_MODE]); val 288 drivers/net/wireless/ti/wlcore/testmode.c switch (val) { val 294 drivers/net/wireless/ti/wlcore/testmode.c ret = wl1271_plt_start(wl, val); val 592 drivers/net/wireless/zydas/zd1201.c static inline int zd1201_getconfig16(struct zd1201 *zd, int rid, short *val) val 600 drivers/net/wireless/zydas/zd1201.c *val = le16_to_cpu(zdval); val 604 drivers/net/wireless/zydas/zd1201.c static inline int zd1201_setconfig16(struct zd1201 *zd, int rid, short val) val 606 drivers/net/wireless/zydas/zd1201.c __le16 zdval = cpu_to_le16(val); val 705 drivers/net/wireless/zydas/zd1201.c int err, val; val 712 drivers/net/wireless/zydas/zd1201.c val = ZD1201_CNFAUTHENTICATION_OPENSYSTEM; val 713 drivers/net/wireless/zydas/zd1201.c val |= ZD1201_CNFAUTHENTICATION_SHAREDKEY; val 714 drivers/net/wireless/zydas/zd1201.c err = zd1201_setconfig16(zd, ZD1201_RID_CNFAUTHENTICATION, val); val 1307 drivers/net/wireless/zydas/zd1201.c short val = rts->value; val 1310 drivers/net/wireless/zydas/zd1201.c val = ZD1201_RTSMAX; val 1311 drivers/net/wireless/zydas/zd1201.c if (val > ZD1201_RTSMAX) val 1313 drivers/net/wireless/zydas/zd1201.c if (val < 0) val 1316 drivers/net/wireless/zydas/zd1201.c err = zd1201_setconfig16(zd, ZD1201_RID_CNFRTSTHRESHOLD, val); val 1344 drivers/net/wireless/zydas/zd1201.c short val = frag->value; val 1347 drivers/net/wireless/zydas/zd1201.c val = ZD1201_FRAGMAX; val 1348 drivers/net/wireless/zydas/zd1201.c if (val > ZD1201_FRAGMAX) val 1350 drivers/net/wireless/zydas/zd1201.c if (val < ZD1201_FRAGMIN) val 1352 drivers/net/wireless/zydas/zd1201.c if (val & 1) val 1354 drivers/net/wireless/zydas/zd1201.c err = zd1201_setconfig16(zd, ZD1201_RID_CNFFRAGTHRESHOLD, val); val 22 drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c #define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff)) val 247 drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c u32 val; val 250 drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]); val 252 drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c val = UW2453_REGWRITE(1, uw2453_std_synth[idx]); val 254 drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c r = zd_rfwrite_locked(chip, val, RF_RV_BITS); val 266 drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c u32 val = 0x40000 | value; val 267 drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS); val 230 drivers/net/xen-netback/common.h u32 val; val 36 drivers/net/xen-netback/hash.c unsigned int len, u32 val) val 48 drivers/net/xen-netback/hash.c new->val = val; val 83 drivers/net/xen-netback/hash.c u32 val; val 85 drivers/net/xen-netback/hash.c val = xen_netif_toeplitz_hash(vif->hash.key, val 90 drivers/net/xen-netback/hash.c xenvif_add_hash(vif, data, len, val); val 92 drivers/net/xen-netback/hash.c return val; val 118 drivers/net/xen-netback/hash.c u32 val; val 134 drivers/net/xen-netback/hash.c val = entry->val; val 144 drivers/net/xen-netback/hash.c val = xenvif_new_hash(vif, data, len); val 146 drivers/net/xen-netback/hash.c return val; val 838 drivers/net/xen-netback/xenbus.c unsigned int val; val 844 drivers/net/xen-netback/xenbus.c "ctrl-ring-ref", "%u", &val); val 848 drivers/net/xen-netback/xenbus.c ring_ref = val; val 851 drivers/net/xen-netback/xenbus.c "event-channel-ctrl", "%u", &val); val 859 drivers/net/xen-netback/xenbus.c evtchn = val; val 171 drivers/nfc/nfcmrvl/fw_dnld.c memcpy(cmd.param.val, &priv->fw_dnld.header->ref_clock, 4); val 203 drivers/nfc/nfcmrvl/fw_dnld.c memcpy(cmd.param.val, val 206 drivers/nfc/nfcmrvl/fw_dnld.c cmd.param.val[4] = val 211 drivers/nfc/nfcmrvl/fw_dnld.c memcpy(cmd.param.val, val 214 drivers/nfc/nfcmrvl/fw_dnld.c cmd.param.val[4] = 0; val 218 drivers/nfc/nfcmrvl/fw_dnld.c memcpy(cmd.param.val, val 221 drivers/nfc/nfcmrvl/fw_dnld.c cmd.param.val[4] = 0; val 83 drivers/nfc/nfcmrvl/main.c __u8 val = 1; val 85 drivers/nfc/nfcmrvl/main.c nci_set_config(ndev, NFCMRVL_PB_BAIL_OUT, 1, &val); val 470 drivers/nfc/trf7970a.c static int trf7970a_read(struct trf7970a *trf, u8 reg, u8 *val) val 475 drivers/nfc/trf7970a.c ret = spi_write_then_read(trf->spi, &addr, 1, val, 1); val 480 drivers/nfc/trf7970a.c dev_dbg(trf->dev, "read(0x%x): 0x%x\n", addr, *val); val 514 drivers/nfc/trf7970a.c static int trf7970a_write(struct trf7970a *trf, u8 reg, u8 val) val 516 drivers/nfc/trf7970a.c u8 buf[2] = { reg, val }; val 519 drivers/nfc/trf7970a.c dev_dbg(trf->dev, "write(0x%x): 0x%x\n", reg, val); val 420 drivers/ntb/hw/amd/ntb_hw_amd.c int idx, u32 val) val 430 drivers/ntb/hw/amd/ntb_hw_amd.c writel(val, mmio + AMD_SPAD_OFFSET + offset); val 449 drivers/ntb/hw/amd/ntb_hw_amd.c int sidx, u32 val) val 459 drivers/ntb/hw/amd/ntb_hw_amd.c writel(val, mmio + AMD_SPAD_OFFSET + offset); val 85 drivers/ntb/hw/amd/ntb_hw_amd.h static inline void _write64(u64 val, void __iomem *mmio) val 87 drivers/ntb/hw/amd/ntb_hw_amd.h writel(val, mmio); val 88 drivers/ntb/hw/amd/ntb_hw_amd.h writel(val >> 32, mmio + sizeof(u32)); val 1890 drivers/ntb/hw/idt/ntb_hw_idt.c const enum idt_temp_val type, long *val) val 1912 drivers/ntb/hw/idt/ntb_hw_idt.c *val = idt_get_temp_sval(data); val 1921 drivers/ntb/hw/idt/ntb_hw_idt.c *val = idt_get_temp_uval(data); val 1931 drivers/ntb/hw/idt/ntb_hw_idt.c const enum idt_temp_val type, const long val) val 1938 drivers/ntb/hw/idt/ntb_hw_idt.c fmt = idt_temp_get_fmt(val); val 307 drivers/ntb/hw/intel/ntb_hw_gen1.c static inline int ndev_spad_write(struct intel_ntb_dev *ndev, int idx, u32 val, val 316 drivers/ntb/hw/intel/ntb_hw_gen1.c iowrite32(val, mmio + (idx << 2)); val 1168 drivers/ntb/hw/intel/ntb_hw_gen1.c int intel_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val) val 1172 drivers/ntb/hw/intel/ntb_hw_gen1.c return ndev_spad_write(ndev, idx, val, val 1196 drivers/ntb/hw/intel/ntb_hw_gen1.c u32 val) val 1200 drivers/ntb/hw/intel/ntb_hw_gen1.c return ndev_spad_write(ndev, sidx, val, val 175 drivers/ntb/hw/intel/ntb_hw_gen1.h int intel_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val); val 178 drivers/ntb/hw/intel/ntb_hw_gen1.h u32 val); val 156 drivers/ntb/hw/mscc/ntb_hw_switchtec.c u32 val) val 161 drivers/ntb/hw/mscc/ntb_hw_switchtec.c iowrite32(val, &sndev->mmio_peer_dbmsg->omsg[idx].msg); val 742 drivers/ntb/hw/mscc/ntb_hw_switchtec.c static int switchtec_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val) val 752 drivers/ntb/hw/mscc/ntb_hw_switchtec.c sndev->self_shared->spad[idx] = val; val 775 drivers/ntb/hw/mscc/ntb_hw_switchtec.c int sidx, u32 val) val 788 drivers/ntb/hw/mscc/ntb_hw_switchtec.c iowrite32(val, &sndev->peer_shared->spad[sidx]); val 1027 drivers/ntb/ntb_transport.c u32 val; val 1065 drivers/ntb/ntb_transport.c val = ntb_spad_read(ndev, VERSION); val 1066 drivers/ntb/ntb_transport.c dev_dbg(&pdev->dev, "Remote version = %d\n", val); val 1067 drivers/ntb/ntb_transport.c if (val != NTB_TRANSPORT_VERSION) val 1070 drivers/ntb/ntb_transport.c val = ntb_spad_read(ndev, NUM_QPS); val 1071 drivers/ntb/ntb_transport.c dev_dbg(&pdev->dev, "Remote max number of qps = %d\n", val); val 1072 drivers/ntb/ntb_transport.c if (val != nt->qp_count) val 1075 drivers/ntb/ntb_transport.c val = ntb_spad_read(ndev, NUM_MWS); val 1076 drivers/ntb/ntb_transport.c dev_dbg(&pdev->dev, "Remote number of mws = %d\n", val); val 1077 drivers/ntb/ntb_transport.c if (val != nt->mw_count) val 1083 drivers/ntb/ntb_transport.c val = ntb_spad_read(ndev, MW0_SZ_HIGH + (i * 2)); val 1084 drivers/ntb/ntb_transport.c val64 = (u64)val << 32; val 1086 drivers/ntb/ntb_transport.c val = ntb_spad_read(ndev, MW0_SZ_LOW + (i * 2)); val 1087 drivers/ntb/ntb_transport.c val64 |= val; val 1131 drivers/ntb/ntb_transport.c int val; val 1135 drivers/ntb/ntb_transport.c val = ntb_spad_read(nt->ndev, QP_LINKS); val 1137 drivers/ntb/ntb_transport.c ntb_peer_spad_write(nt->ndev, PIDX, QP_LINKS, val | BIT(qp->qp_num)); val 1140 drivers/ntb/ntb_transport.c dev_dbg_ratelimited(&pdev->dev, "Remote QP link status = %x\n", val); val 1143 drivers/ntb/ntb_transport.c if (val & BIT(qp->qp_num)) { val 2335 drivers/ntb/ntb_transport.c int val; val 2342 drivers/ntb/ntb_transport.c val = ntb_spad_read(qp->ndev, QP_LINKS); val 2344 drivers/ntb/ntb_transport.c ntb_peer_spad_write(qp->ndev, PIDX, QP_LINKS, val & ~BIT(qp->qp_num)); val 305 drivers/ntb/test/ntb_perf.c u32 val; val 321 drivers/ntb/test/ntb_perf.c val = ntb_spad_read(perf->ntb, PERF_SPAD_CMD(peer->gidx)); val 322 drivers/ntb/test/ntb_perf.c if (val == PERF_CMD_INVAL) val 325 drivers/ntb/test/ntb_perf.c *cmd = val; val 327 drivers/ntb/test/ntb_perf.c val = ntb_spad_read(perf->ntb, PERF_SPAD_LDATA(peer->gidx)); val 328 drivers/ntb/test/ntb_perf.c *data = val; val 330 drivers/ntb/test/ntb_perf.c val = ntb_spad_read(perf->ntb, PERF_SPAD_HDATA(peer->gidx)); val 331 drivers/ntb/test/ntb_perf.c *data |= (u64)val << 32; val 394 drivers/ntb/test/ntb_perf.c u32 val; val 401 drivers/ntb/test/ntb_perf.c val = ntb_msg_read(perf->ntb, pidx, PERF_MSG_CMD); val 402 drivers/ntb/test/ntb_perf.c *cmd = val; val 404 drivers/ntb/test/ntb_perf.c val = ntb_msg_read(perf->ntb, pidx, PERF_MSG_LDATA); val 405 drivers/ntb/test/ntb_perf.c *data = val; val 407 drivers/ntb/test/ntb_perf.c val = ntb_msg_read(perf->ntb, pidx, PERF_MSG_HDATA); val 408 drivers/ntb/test/ntb_perf.c *data |= (u64)val << 32; val 1299 drivers/ntb/test/ntb_perf.c u8 val; val 1301 drivers/ntb/test/ntb_perf.c ret = kstrtou8_from_user(ubuf, size, 0, &val); val 1305 drivers/ntb/test/ntb_perf.c ret = perf_set_tcnt(perf, val); val 471 drivers/ntb/test/ntb_tool.c bool val; val 474 drivers/ntb/test/ntb_tool.c ret = kstrtobool_from_user(ubuf, size, &val); val 478 drivers/ntb/test/ntb_tool.c if (val) val 521 drivers/ntb/test/ntb_tool.c bool val; val 524 drivers/ntb/test/ntb_tool.c ret = kstrtobool_from_user(ubuf, size, &val); val 531 drivers/ntb/test/ntb_tool.c !!(ntb_link_is_up(tc->ntb, NULL, NULL) & link_msk) == val)) val 708 drivers/ntb/test/ntb_tool.c unsigned int val; val 711 drivers/ntb/test/ntb_tool.c ret = kstrtouint_from_user(ubuf, size, 0, &val); val 716 drivers/ntb/test/ntb_tool.c if (val) { val 717 drivers/ntb/test/ntb_tool.c ret = tool_setup_mw(inmw->tc, inmw->pidx, inmw->widx, val); val 1132 drivers/ntb/test/ntb_tool.c u64 val; val 1135 drivers/ntb/test/ntb_tool.c ret = kstrtou64_from_user(ubuf, size, 0, &val); val 1139 drivers/ntb/test/ntb_tool.c if (wait_event_interruptible(tc->db_wq, ntb_db_read(tc->ntb) == val)) val 1174 drivers/ntb/test/ntb_tool.c u32 val; val 1182 drivers/ntb/test/ntb_tool.c ret = kstrtou32_from_user(ubuf, size, 0, &val); val 1186 drivers/ntb/test/ntb_tool.c ret = ntb_spad_write(spad->tc->ntb, spad->sidx, val); val 1215 drivers/ntb/test/ntb_tool.c u32 val; val 1223 drivers/ntb/test/ntb_tool.c ret = kstrtou32_from_user(ubuf, size, 0, &val); val 1227 drivers/ntb/test/ntb_tool.c ret = ntb_peer_spad_write(spad->tc->ntb, spad->pidx, spad->sidx, val); val 1302 drivers/ntb/test/ntb_tool.c u32 val; val 1305 drivers/ntb/test/ntb_tool.c ret = kstrtou32_from_user(ubuf, size, 0, &val); val 1309 drivers/ntb/test/ntb_tool.c ret = ntb_peer_msg_write(msg->tc->ntb, msg->pidx, msg->midx, val); val 1382 drivers/ntb/test/ntb_tool.c u64 val; val 1385 drivers/ntb/test/ntb_tool.c ret = kstrtou64_from_user(ubuf, size, 0, &val); val 1390 drivers/ntb/test/ntb_tool.c ntb_msg_read_sts(tc->ntb) == val)) val 970 drivers/nvdimm/namespace_devs.c static ssize_t __size_store(struct device *dev, unsigned long long val) val 1009 drivers/nvdimm/namespace_devs.c div_u64_rem(val, PAGE_SIZE * nd_region->ndr_mappings, &remainder); val 1011 drivers/nvdimm/namespace_devs.c dev_dbg(dev, "%llu is not %ldK aligned\n", val, val 1032 drivers/nvdimm/namespace_devs.c if (val > available + allocated) val 1035 drivers/nvdimm/namespace_devs.c if (val == allocated) val 1038 drivers/nvdimm/namespace_devs.c val = div_u64(val, nd_region->ndr_mappings); val 1040 drivers/nvdimm/namespace_devs.c if (val < allocated) val 1042 drivers/nvdimm/namespace_devs.c allocated - val); val 1044 drivers/nvdimm/namespace_devs.c rc = grow_dpa_allocation(nd_region, &label_id, val - allocated); val 1053 drivers/nvdimm/namespace_devs.c val * nd_region->ndr_mappings); val 1062 drivers/nvdimm/namespace_devs.c if (val == 0 && id != 0 && nd_region->ns_seed != dev && !ndns->claim) val 1072 drivers/nvdimm/namespace_devs.c unsigned long long val; val 1076 drivers/nvdimm/namespace_devs.c rc = kstrtoull(buf, 0, &val); val 1083 drivers/nvdimm/namespace_devs.c rc = __size_store(dev, val); val 1097 drivers/nvdimm/namespace_devs.c if (rc == 0 && val == 0 && uuid) { val 1103 drivers/nvdimm/namespace_devs.c dev_dbg(dev, "%llx %s (%d)\n", val, rc < 0 ? "fail" : "success", rc); val 2374 drivers/nvme/host/core.c static void nvme_set_latency_tolerance(struct device *dev, s32 val) val 2379 drivers/nvme/host/core.c switch (val) { val 2386 drivers/nvme/host/core.c latency = val; val 142 drivers/nvme/host/fabrics.c int nvmf_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) val 157 drivers/nvme/host/fabrics.c *val = le64_to_cpu(res.u64); val 188 drivers/nvme/host/fabrics.c int nvmf_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) val 204 drivers/nvme/host/fabrics.c *val = le64_to_cpu(res.u64); val 234 drivers/nvme/host/fabrics.c int nvmf_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) val 244 drivers/nvme/host/fabrics.c cmd.prop_set.value = cpu_to_le64(val); val 165 drivers/nvme/host/fabrics.h int nvmf_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val); val 166 drivers/nvme/host/fabrics.h int nvmf_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val); val 167 drivers/nvme/host/fabrics.h int nvmf_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val); val 3241 drivers/nvme/host/fc.c __nvme_fc_parse_u64(substring_t *sstr, u64 *val) val 3247 drivers/nvme/host/fc.c *val = token64; val 390 drivers/nvme/host/nvme.h int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); val 391 drivers/nvme/host/nvme.h int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); val 392 drivers/nvme/host/nvme.h int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); val 61 drivers/nvme/host/pci.c static int io_queue_depth_set(const char *val, const struct kernel_param *kp); val 133 drivers/nvme/host/pci.c static int io_queue_depth_set(const char *val, const struct kernel_param *kp) val 137 drivers/nvme/host/pci.c ret = kstrtoint(val, 10, &n); val 141 drivers/nvme/host/pci.c return param_set_int(val, kp); val 2676 drivers/nvme/host/pci.c static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) val 2678 drivers/nvme/host/pci.c *val = readl(to_nvme_dev(ctrl)->bar + off); val 2682 drivers/nvme/host/pci.c static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) val 2684 drivers/nvme/host/pci.c writel(val, to_nvme_dev(ctrl)->bar + off); val 2688 drivers/nvme/host/pci.c static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) val 2690 drivers/nvme/host/pci.c *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); val 146 drivers/nvme/host/rdma.c static inline void put_unaligned_le24(u32 val, u8 *p) val 148 drivers/nvme/host/rdma.c *p++ = val; val 149 drivers/nvme/host/rdma.c *p++ = val >> 8; val 150 drivers/nvme/host/rdma.c *p++ = val >> 16; val 529 drivers/nvme/target/configfs.c bool val; val 531 drivers/nvme/target/configfs.c if (strtobool(page, &val)) val 541 drivers/nvme/target/configfs.c ns->buffered_io = val; val 12 drivers/nvme/target/fabrics-cmd.c u64 val = le64_to_cpu(req->cmd->prop_set.value); val 24 drivers/nvme/target/fabrics-cmd.c nvmet_update_cc(req->sq->ctrl, val); val 39 drivers/nvme/target/fabrics-cmd.c u64 val = 0; val 44 drivers/nvme/target/fabrics-cmd.c val = ctrl->cap; val 53 drivers/nvme/target/fabrics-cmd.c val = ctrl->subsys->ver; val 56 drivers/nvme/target/fabrics-cmd.c val = ctrl->cc; val 59 drivers/nvme/target/fabrics-cmd.c val = ctrl->csts; val 75 drivers/nvme/target/fabrics-cmd.c req->cqe->result.u64 = cpu_to_le64(val); val 2436 drivers/nvme/target/fc.c __nvme_fc_parse_u64(substring_t *sstr, u64 *val) val 2442 drivers/nvme/target/fc.c *val = token64; val 162 drivers/nvmem/bcm-ocotp.c static int bcm_otpc_read(void *context, unsigned int offset, void *val, val 166 drivers/nvmem/bcm-ocotp.c u32 *buf = val; val 193 drivers/nvmem/bcm-ocotp.c static int bcm_otpc_write(void *context, unsigned int offset, void *val, val 197 drivers/nvmem/bcm-ocotp.c u32 *buf = val; val 46 drivers/nvmem/core.c void *val, size_t bytes) val 49 drivers/nvmem/core.c return nvmem->reg_read(nvmem->priv, offset, val, bytes); val 55 drivers/nvmem/core.c void *val, size_t bytes) val 58 drivers/nvmem/core.c return nvmem->reg_write(nvmem->priv, offset, val, bytes); val 1092 drivers/nvmem/core.c int nvmem_cell_read_u16(struct device *dev, const char *cell_id, u16 *val) val 1107 drivers/nvmem/core.c if (len != sizeof(*val)) { val 1112 drivers/nvmem/core.c memcpy(val, buf, sizeof(*val)); val 1129 drivers/nvmem/core.c int nvmem_cell_read_u32(struct device *dev, const char *cell_id, u32 *val) val 1144 drivers/nvmem/core.c if (len != sizeof(*val)) { val 1149 drivers/nvmem/core.c memcpy(val, buf, sizeof(*val)); val 49 drivers/nvmem/imx-ocotp-scu.c u32 *val) val 66 drivers/nvmem/imx-ocotp-scu.c *val = msg.word; val 72 drivers/nvmem/imx-ocotp-scu.c void *val, size_t bytes) val 109 drivers/nvmem/imx-ocotp-scu.c memcpy(val, (u8 *)p + offset % 4, bytes); val 120 drivers/nvmem/imx-ocotp.c void *val, size_t bytes) val 124 drivers/nvmem/imx-ocotp.c u32 *buf = val; val 243 drivers/nvmem/imx-ocotp.c static int imx_ocotp_write(void *context, unsigned int offset, void *val, val 247 drivers/nvmem/imx-ocotp.c u32 *buf = val; val 55 drivers/nvmem/lpc18xx_eeprom.c u32 reg, u32 val) val 57 drivers/nvmem/lpc18xx_eeprom.c writel(val, eeprom->reg_base + reg); val 69 drivers/nvmem/lpc18xx_eeprom.c u32 val; val 75 drivers/nvmem/lpc18xx_eeprom.c val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT); val 77 drivers/nvmem/lpc18xx_eeprom.c if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) { val 91 drivers/nvmem/lpc18xx_eeprom.c void *val, size_t bytes) val 113 drivers/nvmem/lpc18xx_eeprom.c writel(*(u32 *)val, eeprom->mem_base + offset); val 119 drivers/nvmem/lpc18xx_eeprom.c val += eeprom->val_bytes; val 130 drivers/nvmem/lpc18xx_eeprom.c void *val, size_t bytes) val 141 drivers/nvmem/lpc18xx_eeprom.c *(u32 *)val = readl(eeprom->mem_base + offset); val 143 drivers/nvmem/lpc18xx_eeprom.c val += eeprom->val_bytes; val 42 drivers/nvmem/lpc18xx_otp.c void *val, size_t bytes) val 47 drivers/nvmem/lpc18xx_otp.c u32 *buf = val; val 18 drivers/nvmem/meson-efuse.c void *val, size_t bytes) val 20 drivers/nvmem/meson-efuse.c return meson_sm_call_read((u8 *)val, bytes, SM_EFUSE_READ, offset, val 25 drivers/nvmem/meson-efuse.c void *val, size_t bytes) val 27 drivers/nvmem/meson-efuse.c return meson_sm_call_write((u8 *)val, bytes, SM_EFUSE_WRITE, offset, val 22 drivers/nvmem/mtk-efuse.c u32 *val = _val; val 26 drivers/nvmem/mtk-efuse.c *val++ = readl(priv->base + reg + (i++ * 4)); val 35 drivers/nvmem/mtk-efuse.c u32 *val = _val; val 39 drivers/nvmem/mtk-efuse.c writel(*val++, priv->base + reg + (i++ * 4)); val 59 drivers/nvmem/mxs-ocotp.c void *val, size_t bytes) val 62 drivers/nvmem/mxs-ocotp.c u32 *buf = val; val 21 drivers/nvmem/qfprom.c u8 *val = _val; val 25 drivers/nvmem/qfprom.c *val++ = readb(priv->base + reg + i++); val 274 drivers/nvmem/rave-sp-eeprom.c void *val, size_t bytes) val 277 drivers/nvmem/rave-sp-eeprom.c offset, val, bytes); val 281 drivers/nvmem/rave-sp-eeprom.c void *val, size_t bytes) val 284 drivers/nvmem/rave-sp-eeprom.c offset, val, bytes); val 56 drivers/nvmem/rockchip-efuse.c void *val, size_t bytes) val 59 drivers/nvmem/rockchip-efuse.c u8 *buf = val; val 96 drivers/nvmem/rockchip-efuse.c void *val, size_t bytes) val 141 drivers/nvmem/rockchip-efuse.c memcpy(val, buf + addr_offset, bytes); val 151 drivers/nvmem/rockchip-efuse.c void *val, size_t bytes) val 197 drivers/nvmem/rockchip-efuse.c memcpy(val, buf + addr_offset, bytes); val 91 drivers/nvmem/sc27xx-efuse.c u32 val; val 95 drivers/nvmem/sc27xx-efuse.c val, (val & bits), val 106 drivers/nvmem/sc27xx-efuse.c static int sc27xx_efuse_read(void *context, u32 offset, void *val, size_t bytes) val 178 drivers/nvmem/sc27xx-efuse.c memcpy(val, &buf, bytes); val 52 drivers/nvmem/snvs_lpgpr.c static int snvs_lpgpr_write(void *context, unsigned int offset, void *val, val 74 drivers/nvmem/snvs_lpgpr.c return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val, val 78 drivers/nvmem/snvs_lpgpr.c static int snvs_lpgpr_read(void *context, unsigned int offset, void *val, val 85 drivers/nvmem/snvs_lpgpr.c val, bytes / 4); val 73 drivers/nvmem/stm32-romem.c u32 roffset, rbytes, val; val 74 drivers/nvmem/stm32-romem.c u8 *buf8 = buf, *val8 = (u8 *)&val; val 90 drivers/nvmem/stm32-romem.c val = readl_relaxed( val 94 drivers/nvmem/stm32-romem.c &val); val 41 drivers/nvmem/sunxi_sid.c void *val, size_t bytes) val 45 drivers/nvmem/sunxi_sid.c memcpy_fromio(val, sid->base + sid->value_offset + offset, bytes); val 82 drivers/nvmem/sunxi_sid.c void *val, size_t bytes) val 90 drivers/nvmem/sunxi_sid.c ret = sun8i_sid_register_readout(sid, offset, val); val 94 drivers/nvmem/sunxi_sid.c val += 4; val 107 drivers/nvmem/sunxi_sid.c memcpy(val, &word, bytes); val 23 drivers/nvmem/uniphier-efuse.c u8 *val = _val; val 27 drivers/nvmem/uniphier-efuse.c *val++ = readb(priv->base + reg + offs); val 147 drivers/nvmem/vf610-ocotp.c void *val, size_t bytes) val 151 drivers/nvmem/vf610-ocotp.c u32 reg, *buf = val; val 22 drivers/nvmem/zynqmp_nvmem.c void *val, size_t bytes) val 36 drivers/nvmem/zynqmp_nvmem.c *(int *)val = version & SILICON_REVISION_MASK; val 208 drivers/of/address.c u32 val = be32_to_cpu(prop[0]); val 209 drivers/of/address.c if ((val & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0)) { val 1692 drivers/of/base.c __be32 val = *(map - new_size + i); val 1695 drivers/of/base.c val &= ~pass[i]; val 1696 drivers/of/base.c val |= cpu_to_be32(out_args->args[i]) & pass[i]; val 1699 drivers/of/base.c out_args->args[i] = be32_to_cpu(val); val 46 drivers/of/fdt.c const void *val; val 72 drivers/of/fdt.c val = fdt_getprop(initial_boot_params, memory, "reg", &len); val 76 drivers/of/fdt.c fdt_setprop(initial_boot_params, memory, "reg", val, val 122 drivers/of/fdt.c const __be32 *val; val 126 drivers/of/fdt.c val = fdt_getprop_by_offset(blob, cur, &pname, &sz); val 127 drivers/of/fdt.c if (!val) { val 154 drivers/of/fdt.c np->phandle = be32_to_cpup(val); val 162 drivers/of/fdt.c np->phandle = be32_to_cpup(val); val 166 drivers/of/fdt.c pp->value = (__be32 *)val; val 693 drivers/of/overlay.c u32 val; val 696 drivers/of/overlay.c ret = of_property_read_u32(info_node, "target", &val); val 698 drivers/of/overlay.c node = of_find_node_by_phandle(val); val 701 drivers/of/overlay.c info_node, val); val 117 drivers/of/property.c const u32 *val = of_find_property_value_of_size(np, propname, val 122 drivers/of/property.c if (IS_ERR(val)) val 123 drivers/of/property.c return PTR_ERR(val); val 125 drivers/of/property.c *out_value = be32_to_cpup(((__be32 *)val) + index); val 149 drivers/of/property.c const u64 *val = of_find_property_value_of_size(np, propname, val 153 drivers/of/property.c if (IS_ERR(val)) val 154 drivers/of/property.c return PTR_ERR(val); val 156 drivers/of/property.c *out_value = be64_to_cpup(((__be64 *)val) + index); val 188 drivers/of/property.c const u8 *val = of_find_property_value_of_size(np, propname, val 193 drivers/of/property.c if (IS_ERR(val)) val 194 drivers/of/property.c return PTR_ERR(val); val 203 drivers/of/property.c *out_values++ = *val++; val 236 drivers/of/property.c const __be16 *val = of_find_property_value_of_size(np, propname, val 241 drivers/of/property.c if (IS_ERR(val)) val 242 drivers/of/property.c return PTR_ERR(val); val 251 drivers/of/property.c *out_values++ = be16_to_cpup(val++); val 281 drivers/of/property.c const __be32 *val = of_find_property_value_of_size(np, propname, val 286 drivers/of/property.c if (IS_ERR(val)) val 287 drivers/of/property.c return PTR_ERR(val); val 296 drivers/of/property.c *out_values++ = be32_to_cpup(val++); val 318 drivers/of/property.c const __be32 *val = of_find_property_value_of_size(np, propname, val 323 drivers/of/property.c if (IS_ERR(val)) val 324 drivers/of/property.c return PTR_ERR(val); val 326 drivers/of/property.c *out_value = of_read_number(val, 2); val 355 drivers/of/property.c const __be32 *val = of_find_property_value_of_size(np, propname, val 360 drivers/of/property.c if (IS_ERR(val)) val 361 drivers/of/property.c return PTR_ERR(val); val 370 drivers/of/property.c *out_values++ = of_read_number(val, 2); val 371 drivers/of/property.c val += 2; val 840 drivers/of/property.c unsigned int elem_size, void *val, val 845 drivers/of/property.c if (!val) val 851 drivers/of/property.c return of_property_read_u8_array(node, propname, val, nval); val 853 drivers/of/property.c return of_property_read_u16_array(node, propname, val, nval); val 855 drivers/of/property.c return of_property_read_u32_array(node, propname, val, nval); val 857 drivers/of/property.c return of_property_read_u64_array(node, propname, val, nval); val 865 drivers/of/property.c const char *propname, const char **val, val 870 drivers/of/property.c return val ? val 871 drivers/of/property.c of_property_read_string_array(node, propname, val, nval) : val 223 drivers/opp/of.c u32 val; val 233 drivers/opp/of.c if (!of_property_read_u32(np, "clock-latency", &val)) val 234 drivers/opp/of.c opp_table->clock_latency_ns_max = val; val 553 drivers/opp/of.c u32 val; val 597 drivers/opp/of.c if (!of_property_read_u32(np, "clock-latency-ns", &val)) val 598 drivers/opp/of.c new_opp->clock_latency_ns = val; val 721 drivers/opp/of.c const __be32 *val; val 740 drivers/opp/of.c val = prop->value; val 742 drivers/opp/of.c unsigned long freq = be32_to_cpup(val++) * 1000; val 743 drivers/opp/of.c unsigned long volt = be32_to_cpup(val++); val 79 drivers/opp/ti-opp-supply.c const __be32 *val; val 133 drivers/opp/ti-opp-supply.c val = prop->value; val 138 drivers/opp/ti-opp-supply.c table->reference_uv = be32_to_cpup(val++); val 139 drivers/opp/ti-opp-supply.c efuse_offset = be32_to_cpup(val++); val 57 drivers/oprofile/buffer_sync.c task_free_notify(struct notifier_block *self, unsigned long val, void *data) val 72 drivers/oprofile/buffer_sync.c task_exit_notify(struct notifier_block *self, unsigned long val, void *data) val 88 drivers/oprofile/buffer_sync.c munmap_notify(struct notifier_block *self, unsigned long val, void *data) val 115 drivers/oprofile/buffer_sync.c module_load_notify(struct notifier_block *self, unsigned long val, void *data) val 118 drivers/oprofile/buffer_sync.c if (val != MODULE_STATE_COMING) val 333 drivers/oprofile/buffer_sync.c unsigned long code, pc, val; val 364 drivers/oprofile/buffer_sync.c while (op_cpu_buffer_get_data(entry, &val)) val 365 drivers/oprofile/buffer_sync.c add_event_entry(val); val 423 drivers/oprofile/buffer_sync.c static inline int is_code(unsigned long val) val 425 drivers/oprofile/buffer_sync.c return val == ESCAPE_CODE; val 497 drivers/oprofile/buffer_sync.c unsigned long val; val 534 drivers/oprofile/buffer_sync.c && op_cpu_buffer_get_data(&entry, &val)) { val 536 drivers/oprofile/buffer_sync.c new = (struct task_struct *)val; val 386 drivers/oprofile/cpu_buffer.c int oprofile_add_data(struct op_entry *entry, unsigned long val) val 390 drivers/oprofile/cpu_buffer.c return op_cpu_buffer_add_data(entry, val); val 393 drivers/oprofile/cpu_buffer.c int oprofile_add_data64(struct op_entry *entry, u64 val) val 403 drivers/oprofile/cpu_buffer.c if (!op_cpu_buffer_add_data(entry, (u32)val)) val 405 drivers/oprofile/cpu_buffer.c return op_cpu_buffer_add_data(entry, (u32)(val >> 32)); val 85 drivers/oprofile/cpu_buffer.h int op_cpu_buffer_add_data(struct op_entry *entry, unsigned long val) val 89 drivers/oprofile/cpu_buffer.h *entry->data = val; val 104 drivers/oprofile/cpu_buffer.h int op_cpu_buffer_get_data(struct op_entry *entry, unsigned long *val) val 109 drivers/oprofile/cpu_buffer.h *val = *entry->data; val 228 drivers/oprofile/oprof.c int oprofile_set_ulong(unsigned long *addr, unsigned long val) val 234 drivers/oprofile/oprof.c *addr = val; val 47 drivers/oprofile/oprof.h int oprofile_set_ulong(unsigned long *addr, unsigned long val); val 41 drivers/oprofile/oprofile_files.c unsigned long val; val 47 drivers/oprofile/oprofile_files.c retval = oprofilefs_ulong_from_user(&val, buf, count); val 51 drivers/oprofile/oprofile_files.c retval = oprofile_set_timeout(val); val 77 drivers/oprofile/oprofile_files.c unsigned long val; val 86 drivers/oprofile/oprofile_files.c retval = oprofilefs_ulong_from_user(&val, buf, count); val 90 drivers/oprofile/oprofile_files.c retval = oprofile_set_ulong(&oprofile_backtrace_depth, val); val 137 drivers/oprofile/oprofile_files.c unsigned long val; val 143 drivers/oprofile/oprofile_files.c retval = oprofilefs_ulong_from_user(&val, buf, count); val 148 drivers/oprofile/oprofile_files.c if (val) val 54 drivers/oprofile/oprofilefs.c ssize_t oprofilefs_ulong_to_user(unsigned long val, char __user *buf, size_t count, loff_t *offset) val 57 drivers/oprofile/oprofilefs.c size_t maxlen = snprintf(tmpbuf, TMPBUFSIZE, "%lu\n", val); val 71 drivers/oprofile/oprofilefs.c int oprofilefs_ulong_from_user(unsigned long *val, char const __user *buf, size_t count) val 88 drivers/oprofile/oprofilefs.c *val = simple_strtoul(tmpbuf, NULL, 0); val 96 drivers/oprofile/oprofilefs.c unsigned long *val = file->private_data; val 97 drivers/oprofile/oprofilefs.c return oprofilefs_ulong_to_user(*val, buf, count, offset); val 166 drivers/oprofile/oprofilefs.c char const *name, unsigned long *val) val 169 drivers/oprofile/oprofilefs.c &ulong_fops, 0644, val); val 174 drivers/oprofile/oprofilefs.c char const *name, unsigned long *val) val 177 drivers/oprofile/oprofilefs.c &ulong_ro_fops, 0444, val); val 183 drivers/oprofile/oprofilefs.c atomic_t *val = file->private_data; val 184 drivers/oprofile/oprofilefs.c return oprofilefs_ulong_to_user(atomic_read(val), buf, count, offset); val 196 drivers/oprofile/oprofilefs.c char const *name, atomic_t *val) val 199 drivers/oprofile/oprofilefs.c &atomic_ro_fops, 0444, val); val 182 drivers/parisc/dino.c int size, u32 *val) val 199 drivers/parisc/dino.c *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); val 201 drivers/parisc/dino.c *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); val 203 drivers/parisc/dino.c *val = readl(base_addr + DINO_CONFIG_DATA); val 217 drivers/parisc/dino.c int size, u32 val) val 237 drivers/parisc/dino.c writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); val 239 drivers/parisc/dino.c writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); val 241 drivers/parisc/dino.c writel(val, base_addr + DINO_CONFIG_DATA); val 282 drivers/parisc/dino.c static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ val 289 drivers/parisc/dino.c write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ val 439 drivers/parisc/eisa.c int val; val 445 drivers/parisc/eisa.c val = (int) simple_strtoul(cur, &pe, 0); val 446 drivers/parisc/eisa.c if (val > 15 || val < 0) { val 450 drivers/parisc/eisa.c if (val == 2) { val 451 drivers/parisc/eisa.c val = 9; val 453 drivers/parisc/eisa.c eisa_make_irq_edge(val); /* clear the corresponding bit */ val 454 drivers/parisc/eisa.c EISA_DBG("setting IRQ %d to edge-triggered mode\n", val); val 179 drivers/parisc/iosapic.c static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val) val 182 drivers/parisc/iosapic.c writel(val, iosapic + IOSAPIC_REG_WINDOW); val 929 drivers/parisc/lba_pci.c static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ val 931 drivers/parisc/lba_pci.c DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \ val 932 drivers/parisc/lba_pci.c WRITE_REG##size(val, astro_iop_base + addr); \ val 986 drivers/parisc/lba_pci.c static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \ val 989 drivers/parisc/lba_pci.c DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \ val 990 drivers/parisc/lba_pci.c WRITE_REG##size(val, where); \ val 130 drivers/parisc/sba_iommu.c #define WRITE_REG32(val, addr) writel((val), (addr)) val 131 drivers/parisc/sba_iommu.c #define WRITE_REG64(val, addr) writeq((val), (addr)) val 519 drivers/parisc/sba_iommu.c #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) val 66 drivers/parport/ieee1284_ops.c unsigned char val = (PARPORT_STATUS_ERROR val 72 drivers/parport/ieee1284_ops.c if (!parport_wait_peripheral (port, mask, val)) val 72 drivers/parport/parport_amiga.c static unsigned char amiga_frob_control( struct parport *p, unsigned char mask, unsigned char val) val 76 drivers/parport/parport_amiga.c DPRINTK(KERN_DEBUG "frob_control mask %02x, value %02x\n",mask,val); val 78 drivers/parport/parport_amiga.c amiga_write_control(p, (old & ~mask) ^ val); val 78 drivers/parport/parport_atari.c unsigned char val) val 81 drivers/parport/parport_atari.c parport_atari_write_control(p, (old & ~mask) ^ val); val 145 drivers/parport/parport_ax88796.c unsigned char val) val 151 drivers/parport/parport_ax88796.c mask, val, old); val 153 drivers/parport/parport_ax88796.c parport_ax88796_write_control(p, (old & ~mask) | val); val 81 drivers/parport/parport_gsc.h unsigned char val = parport_readb (DATA (p)); val 84 drivers/parport/parport_gsc.h p, val); val 86 drivers/parport/parport_gsc.h return val; val 93 drivers/parport/parport_gsc.h unsigned char val) val 100 drivers/parport/parport_gsc.h mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); val 102 drivers/parport/parport_gsc.h ctr = (ctr & ~mask) ^ val; val 149 drivers/parport/parport_gsc.h unsigned char val) val 160 drivers/parport/parport_gsc.h (val & 0x20) ? "reverse" : "forward"); val 161 drivers/parport/parport_gsc.h if (val & 0x20) val 169 drivers/parport/parport_gsc.h val &= wm; val 171 drivers/parport/parport_gsc.h return __parport_gsc_frob_control (p, mask, val); val 819 drivers/parport/parport_ip32.c unsigned int val) val 822 drivers/parport/parport_ip32.c c = (parport_ip32_read_econtrol(p) & ~mask) ^ val; val 920 drivers/parport/parport_ip32.c unsigned int val) val 923 drivers/parport/parport_ip32.c c = (__parport_ip32_read_control(p) & ~mask) ^ val; val 969 drivers/parport/parport_ip32.c unsigned char val) val 974 drivers/parport/parport_ip32.c CHECK_EXTRA_BITS(p, val, wm); val 975 drivers/parport/parport_ip32.c __parport_ip32_frob_control(p, mask & wm, val & wm); val 141 drivers/parport/parport_mfc3.c static unsigned char mfc3_frob_control( struct parport *p, unsigned char mask, unsigned char val) val 145 drivers/parport/parport_mfc3.c DPRINTK(KERN_DEBUG "frob_control mask %02x, value %02x\n",mask,val); val 147 drivers/parport/parport_mfc3.c mfc3_write_control(p, (old & ~mask) ^ val); val 3097 drivers/parport/parport_pc.c static int __init parport_parse_param(const char *s, int *val, val 3103 drivers/parport/parport_pc.c *val = automatic; val 3105 drivers/parport/parport_pc.c *val = none; val 3107 drivers/parport/parport_pc.c *val = nofifo; val 3112 drivers/parport/parport_pc.c *val = r; val 3121 drivers/parport/parport_pc.c static int __init parport_parse_irq(const char *irqstr, int *val) val 3123 drivers/parport/parport_pc.c return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, val 3127 drivers/parport/parport_pc.c static int __init parport_parse_dma(const char *dmastr, int *val) val 3129 drivers/parport/parport_pc.c return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, val 3180 drivers/parport/parport_pc.c int val; val 3188 drivers/parport/parport_pc.c if (parport_parse_irq(irq[i], &val)) val 3190 drivers/parport/parport_pc.c irqval[i] = val; val 3191 drivers/parport/parport_pc.c if (parport_parse_dma(dma[i], &val)) val 3193 drivers/parport/parport_pc.c dmaval[i] = val; val 3197 drivers/parport/parport_pc.c if (irq[0] && !parport_parse_irq(irq[0], &val)) val 3198 drivers/parport/parport_pc.c switch (val) { val 3201 drivers/parport/parport_pc.c irqval[0] = val; val 3210 drivers/parport/parport_pc.c if (dma[0] && !parport_parse_dma(dma[0], &val)) val 3211 drivers/parport/parport_pc.c switch (val) { val 3214 drivers/parport/parport_pc.c dmaval[0] = val; val 3243 drivers/parport/parport_pc.c int val; val 3257 drivers/parport/parport_pc.c val = simple_strtoul(str, &endptr, 0); val 3268 drivers/parport/parport_pc.c io[parport_setup_ptr] = val; val 3274 drivers/parport/parport_pc.c if (parport_parse_irq(sep, &val)) val 3276 drivers/parport/parport_pc.c irqval[parport_setup_ptr] = val; val 3279 drivers/parport/parport_pc.c if (parport_parse_dma(sep, &val)) val 3281 drivers/parport/parport_pc.c dmaval[parport_setup_ptr] = val; val 137 drivers/parport/parport_sunbpp.c unsigned char val) val 146 drivers/parport/parport_sunbpp.c if (val & PARPORT_CONTROL_STROBE) { val 153 drivers/parport/parport_sunbpp.c if (val & PARPORT_CONTROL_AUTOFD) { val 160 drivers/parport/parport_sunbpp.c if (val & PARPORT_CONTROL_INIT) { val 167 drivers/parport/parport_sunbpp.c if (val & PARPORT_CONTROL_SELECT) { val 209 drivers/parport/parport_sunbpp.c u8 val = sbus_readb(®s->p_tcr); val 212 drivers/parport/parport_sunbpp.c val |= P_TCR_DIR; val 213 drivers/parport/parport_sunbpp.c sbus_writeb(val, ®s->p_tcr); val 78 drivers/pci/access.c int where, int size, u32 *val) val 84 drivers/pci/access.c *val = ~0; val 89 drivers/pci/access.c *val = readb(addr); val 91 drivers/pci/access.c *val = readw(addr); val 93 drivers/pci/access.c *val = readl(addr); val 100 drivers/pci/access.c int where, int size, u32 val) val 109 drivers/pci/access.c writeb(val, addr); val 111 drivers/pci/access.c writew(val, addr); val 113 drivers/pci/access.c writel(val, addr); val 120 drivers/pci/access.c int where, int size, u32 *val) val 126 drivers/pci/access.c *val = ~0; val 130 drivers/pci/access.c *val = readl(addr); val 133 drivers/pci/access.c *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); val 140 drivers/pci/access.c int where, int size, u32 val) val 150 drivers/pci/access.c writel(val, addr); val 169 drivers/pci/access.c tmp |= val << ((where & 0x3) * 8); val 223 drivers/pci/access.c (struct pci_dev *dev, int pos, type *val) \ val 235 drivers/pci/access.c *val = (type)data; \ val 243 drivers/pci/access.c (struct pci_dev *dev, int pos, type val) \ val 252 drivers/pci/access.c pos, sizeof(type), val); \ val 406 drivers/pci/access.c int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) val 410 drivers/pci/access.c *val = 0; val 415 drivers/pci/access.c ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); val 422 drivers/pci/access.c *val = 0; val 435 drivers/pci/access.c *val = PCI_EXP_SLTSTA_PDS; val 441 drivers/pci/access.c int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) val 445 drivers/pci/access.c *val = 0; val 450 drivers/pci/access.c ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); val 457 drivers/pci/access.c *val = 0; val 463 drivers/pci/access.c *val = PCI_EXP_SLTSTA_PDS; val 469 drivers/pci/access.c int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) val 477 drivers/pci/access.c return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); val 481 drivers/pci/access.c int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) val 489 drivers/pci/access.c return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); val 497 drivers/pci/access.c u16 val; val 499 drivers/pci/access.c ret = pcie_capability_read_word(dev, pos, &val); val 501 drivers/pci/access.c val &= ~clear; val 502 drivers/pci/access.c val |= set; val 503 drivers/pci/access.c ret = pcie_capability_write_word(dev, pos, val); val 514 drivers/pci/access.c u32 val; val 516 drivers/pci/access.c ret = pcie_capability_read_dword(dev, pos, &val); val 518 drivers/pci/access.c val &= ~clear; val 519 drivers/pci/access.c val |= set; val 520 drivers/pci/access.c ret = pcie_capability_write_dword(dev, pos, val); val 527 drivers/pci/access.c int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) val 530 drivers/pci/access.c *val = ~0; val 533 drivers/pci/access.c return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); val 537 drivers/pci/access.c int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) val 540 drivers/pci/access.c *val = ~0; val 543 drivers/pci/access.c return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); val 548 drivers/pci/access.c u32 *val) val 551 drivers/pci/access.c *val = ~0; val 554 drivers/pci/access.c return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); val 558 drivers/pci/access.c int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) val 562 drivers/pci/access.c return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); val 566 drivers/pci/access.c int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) val 570 drivers/pci/access.c return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); val 575 drivers/pci/access.c u32 val) val 579 drivers/pci/access.c return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); val 653 drivers/pci/controller/dwc/pci-dra7xx.c u32 val; val 668 drivers/pci/controller/dwc/pci-dra7xx.c val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN; val 669 drivers/pci/controller/dwc/pci-dra7xx.c regmap_update_bits(pcie_syscon, pcie_reg, mask, val); val 862 drivers/pci/controller/dwc/pci-dra7xx.c u32 val; val 868 drivers/pci/controller/dwc/pci-dra7xx.c val = dw_pcie_readl_dbi(pci, PCI_COMMAND); val 869 drivers/pci/controller/dwc/pci-dra7xx.c val &= ~PCI_COMMAND_MEMORY; val 870 drivers/pci/controller/dwc/pci-dra7xx.c dw_pcie_writel_dbi(pci, PCI_COMMAND, val); val 879 drivers/pci/controller/dwc/pci-dra7xx.c u32 val; val 885 drivers/pci/controller/dwc/pci-dra7xx.c val = dw_pcie_readl_dbi(pci, PCI_COMMAND); val 886 drivers/pci/controller/dwc/pci-dra7xx.c val |= PCI_COMMAND_MEMORY; val 887 drivers/pci/controller/dwc/pci-dra7xx.c dw_pcie_writel_dbi(pci, PCI_COMMAND, val); val 164 drivers/pci/controller/dwc/pci-exynos.c static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) val 166 drivers/pci/controller/dwc/pci-exynos.c writel(val, base + reg); val 176 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 178 drivers/pci/controller/dwc/pci-exynos.c val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_AWMISC); val 180 drivers/pci/controller/dwc/pci-exynos.c val |= PCIE_ELBI_SLV_DBI_ENABLE; val 182 drivers/pci/controller/dwc/pci-exynos.c val &= ~PCIE_ELBI_SLV_DBI_ENABLE; val 183 drivers/pci/controller/dwc/pci-exynos.c exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_AWMISC); val 188 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 190 drivers/pci/controller/dwc/pci-exynos.c val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_ARMISC); val 192 drivers/pci/controller/dwc/pci-exynos.c val |= PCIE_ELBI_SLV_DBI_ENABLE; val 194 drivers/pci/controller/dwc/pci-exynos.c val &= ~PCIE_ELBI_SLV_DBI_ENABLE; val 195 drivers/pci/controller/dwc/pci-exynos.c exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_ARMISC); val 200 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 202 drivers/pci/controller/dwc/pci-exynos.c val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET); val 203 drivers/pci/controller/dwc/pci-exynos.c val &= ~PCIE_CORE_RESET_ENABLE; val 204 drivers/pci/controller/dwc/pci-exynos.c exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET); val 212 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 214 drivers/pci/controller/dwc/pci-exynos.c val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET); val 215 drivers/pci/controller/dwc/pci-exynos.c val |= PCIE_CORE_RESET_ENABLE; val 217 drivers/pci/controller/dwc/pci-exynos.c exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET); val 273 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 275 drivers/pci/controller/dwc/pci-exynos.c val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE); val 276 drivers/pci/controller/dwc/pci-exynos.c exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE); val 281 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 284 drivers/pci/controller/dwc/pci-exynos.c val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | val 286 drivers/pci/controller/dwc/pci-exynos.c exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE); val 301 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 306 drivers/pci/controller/dwc/pci-exynos.c val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL); val 307 drivers/pci/controller/dwc/pci-exynos.c val |= IRQ_MSI_ENABLE; val 308 drivers/pci/controller/dwc/pci-exynos.c exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL); val 323 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 326 drivers/pci/controller/dwc/pci-exynos.c dw_pcie_read(base + reg, size, &val); val 328 drivers/pci/controller/dwc/pci-exynos.c return val; val 332 drivers/pci/controller/dwc/pci-exynos.c u32 reg, size_t size, u32 val) val 337 drivers/pci/controller/dwc/pci-exynos.c dw_pcie_write(base + reg, size, val); val 342 drivers/pci/controller/dwc/pci-exynos.c u32 *val) val 349 drivers/pci/controller/dwc/pci-exynos.c ret = dw_pcie_read(pci->dbi_base + where, size, val); val 355 drivers/pci/controller/dwc/pci-exynos.c u32 val) val 362 drivers/pci/controller/dwc/pci-exynos.c ret = dw_pcie_write(pci->dbi_base + where, size, val); val 370 drivers/pci/controller/dwc/pci-exynos.c u32 val; val 372 drivers/pci/controller/dwc/pci-exynos.c val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_RDLH_LINKUP); val 373 drivers/pci/controller/dwc/pci-exynos.c if (val == PCIE_ELBI_LTSSM_ENABLE) val 159 drivers/pci/controller/dwc/pci-imx6.c bool val; val 164 drivers/pci/controller/dwc/pci-imx6.c val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & val 168 drivers/pci/controller/dwc/pci-imx6.c if (val == exp_val) val 180 drivers/pci/controller/dwc/pci-imx6.c u32 val; val 183 drivers/pci/controller/dwc/pci-imx6.c val = PCIE_PHY_CTRL_DATA(addr); val 184 drivers/pci/controller/dwc/pci-imx6.c dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); val 186 drivers/pci/controller/dwc/pci-imx6.c val |= PCIE_PHY_CTRL_CAP_ADR; val 187 drivers/pci/controller/dwc/pci-imx6.c dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); val 193 drivers/pci/controller/dwc/pci-imx6.c val = PCIE_PHY_CTRL_DATA(addr); val 194 drivers/pci/controller/dwc/pci-imx6.c dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); val 315 drivers/pci/controller/dwc/pci-imx6.c unsigned long val; val 318 drivers/pci/controller/dwc/pci-imx6.c val = 255; val 320 drivers/pci/controller/dwc/pci-imx6.c val = -1; val 322 drivers/pci/controller/dwc/pci-imx6.c regs->uregs[reg] = val; val 485 drivers/pci/controller/dwc/pci-imx6.c u32 val; val 489 drivers/pci/controller/dwc/pci-imx6.c IOMUXC_GPR22, val, val 490 drivers/pci/controller/dwc/pci-imx6.c val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, val 608 drivers/pci/controller/dwc/pci-imx6.c unsigned int mask, val; val 613 drivers/pci/controller/dwc/pci-imx6.c val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, val 617 drivers/pci/controller/dwc/pci-imx6.c val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, val 621 drivers/pci/controller/dwc/pci-imx6.c regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); val 679 drivers/pci/controller/dwc/pci-imx6.c u16 val; val 705 drivers/pci/controller/dwc/pci-imx6.c pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); val 706 drivers/pci/controller/dwc/pci-imx6.c val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << val 708 drivers/pci/controller/dwc/pci-imx6.c val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; val 709 drivers/pci/controller/dwc/pci-imx6.c val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; val 710 drivers/pci/controller/dwc/pci-imx6.c pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); val 712 drivers/pci/controller/dwc/pci-imx6.c pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); val 713 drivers/pci/controller/dwc/pci-imx6.c val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << val 715 drivers/pci/controller/dwc/pci-imx6.c val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; val 716 drivers/pci/controller/dwc/pci-imx6.c val |= PCIE_PHY_ATEOVRD_EN; val 717 drivers/pci/controller/dwc/pci-imx6.c pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); val 1020 drivers/pci/controller/dwc/pci-imx6.c u16 val; val 1193 drivers/pci/controller/dwc/pci-imx6.c val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP + val 1195 drivers/pci/controller/dwc/pci-imx6.c val |= PCI_MSI_FLAGS_ENABLE; val 1197 drivers/pci/controller/dwc/pci-imx6.c val); val 145 drivers/pci/controller/dwc/pci-keystone.c u32 val) val 147 drivers/pci/controller/dwc/pci-keystone.c writel(val, ks_pcie->va_app_base + offset); val 367 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 369 drivers/pci/controller/dwc/pci-keystone.c val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val 370 drivers/pci/controller/dwc/pci-keystone.c val |= DBI_CS2; val 371 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); val 374 drivers/pci/controller/dwc/pci-keystone.c val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val 375 drivers/pci/controller/dwc/pci-keystone.c } while (!(val & DBI_CS2)); val 386 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 388 drivers/pci/controller/dwc/pci-keystone.c val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val 389 drivers/pci/controller/dwc/pci-keystone.c val &= ~DBI_CS2; val 390 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); val 393 drivers/pci/controller/dwc/pci-keystone.c val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val 394 drivers/pci/controller/dwc/pci-keystone.c } while (val & DBI_CS2); val 399 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 416 drivers/pci/controller/dwc/pci-keystone.c val = ilog2(OB_WIN_SIZE); val 417 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, OB_SIZE, val); val 428 drivers/pci/controller/dwc/pci-keystone.c val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val 429 drivers/pci/controller/dwc/pci-keystone.c val |= OB_XLAT_EN_VAL; val 430 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); val 435 drivers/pci/controller/dwc/pci-keystone.c u32 *val) val 447 drivers/pci/controller/dwc/pci-keystone.c return dw_pcie_read(pp->va_cfg0_base + where, size, val); val 452 drivers/pci/controller/dwc/pci-keystone.c u32 val) val 464 drivers/pci/controller/dwc/pci-keystone.c return dw_pcie_write(pp->va_cfg0_base + where, size, val); val 498 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 500 drivers/pci/controller/dwc/pci-keystone.c val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); val 501 drivers/pci/controller/dwc/pci-keystone.c val &= PORT_LOGIC_LTSSM_STATE_MASK; val 502 drivers/pci/controller/dwc/pci-keystone.c return (val == PORT_LOGIC_LTSSM_STATE_L0); val 508 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 511 drivers/pci/controller/dwc/pci-keystone.c val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val 512 drivers/pci/controller/dwc/pci-keystone.c val &= ~LTSSM_EN_VAL; val 513 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); val 520 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 528 drivers/pci/controller/dwc/pci-keystone.c val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val 529 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); val 893 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 896 drivers/pci/controller/dwc/pci-keystone.c dw_pcie_read(base + reg, size, &val); val 898 drivers/pci/controller/dwc/pci-keystone.c return val; val 902 drivers/pci/controller/dwc/pci-keystone.c u32 reg, size_t size, u32 val) val 907 drivers/pci/controller/dwc/pci-keystone.c dw_pcie_write(base + reg, size, val); val 1069 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 1078 drivers/pci/controller/dwc/pci-keystone.c val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; val 1080 drivers/pci/controller/dwc/pci-keystone.c ret = regmap_update_bits(syscon, 0, mask, val); val 1094 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 1106 drivers/pci/controller/dwc/pci-keystone.c val = RC; val 1109 drivers/pci/controller/dwc/pci-keystone.c val = EP; val 1116 drivers/pci/controller/dwc/pci-keystone.c ret = regmap_update_bits(syscon, 0, mask, val); val 1127 drivers/pci/controller/dwc/pci-keystone.c u32 val; val 1131 drivers/pci/controller/dwc/pci-keystone.c val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP); val 1132 drivers/pci/controller/dwc/pci-keystone.c if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { val 1133 drivers/pci/controller/dwc/pci-keystone.c val &= ~((u32)PCI_EXP_LNKCAP_SLS); val 1134 drivers/pci/controller/dwc/pci-keystone.c val |= link_speed; val 1136 drivers/pci/controller/dwc/pci-keystone.c val); val 1139 drivers/pci/controller/dwc/pci-keystone.c val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2); val 1140 drivers/pci/controller/dwc/pci-keystone.c if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { val 1141 drivers/pci/controller/dwc/pci-keystone.c val &= ~((u32)PCI_EXP_LNKCAP_SLS); val 1142 drivers/pci/controller/dwc/pci-keystone.c val |= link_speed; val 1144 drivers/pci/controller/dwc/pci-keystone.c val); val 78 drivers/pci/controller/dwc/pci-layerscape.c u32 val; val 81 drivers/pci/controller/dwc/pci-layerscape.c val = ioread32(pci->dbi_base + PCIE_STRFMR1); val 82 drivers/pci/controller/dwc/pci-layerscape.c val &= 0xDFFFFFFF; val 83 drivers/pci/controller/dwc/pci-layerscape.c iowrite32(val, pci->dbi_base + PCIE_STRFMR1); val 268 drivers/pci/controller/dwc/pci-meson.c static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg) val 270 drivers/pci/controller/dwc/pci-meson.c writel(val, mp->mem_res.elbi_base + reg); val 283 drivers/pci/controller/dwc/pci-meson.c static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg) val 285 drivers/pci/controller/dwc/pci-meson.c writel(val, mp->mem_res.cfg_base + reg); val 297 drivers/pci/controller/dwc/pci-meson.c u32 val; val 299 drivers/pci/controller/dwc/pci-meson.c val = meson_cfg_readl(mp, PCIE_CFG0); val 300 drivers/pci/controller/dwc/pci-meson.c val |= APP_LTSSM_ENABLE; val 301 drivers/pci/controller/dwc/pci-meson.c meson_cfg_writel(mp, val, PCIE_CFG0); val 303 drivers/pci/controller/dwc/pci-meson.c val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF); val 304 drivers/pci/controller/dwc/pci-meson.c val &= ~LINK_CAPABLE_MASK; val 305 drivers/pci/controller/dwc/pci-meson.c meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF); val 307 drivers/pci/controller/dwc/pci-meson.c val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF); val 308 drivers/pci/controller/dwc/pci-meson.c val |= LINK_CAPABLE_X1 | FAST_LINK_MODE; val 309 drivers/pci/controller/dwc/pci-meson.c meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF); val 311 drivers/pci/controller/dwc/pci-meson.c val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF); val 312 drivers/pci/controller/dwc/pci-meson.c val &= ~NUM_OF_LANES_MASK; val 313 drivers/pci/controller/dwc/pci-meson.c meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF); val 315 drivers/pci/controller/dwc/pci-meson.c val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF); val 316 drivers/pci/controller/dwc/pci-meson.c val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE; val 317 drivers/pci/controller/dwc/pci-meson.c meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF); val 342 drivers/pci/controller/dwc/pci-meson.c u32 val; val 345 drivers/pci/controller/dwc/pci-meson.c val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); val 346 drivers/pci/controller/dwc/pci-meson.c val &= ~PCIE_CAP_MAX_PAYLOAD_MASK; val 347 drivers/pci/controller/dwc/pci-meson.c meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); val 349 drivers/pci/controller/dwc/pci-meson.c val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); val 350 drivers/pci/controller/dwc/pci-meson.c val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); val 351 drivers/pci/controller/dwc/pci-meson.c meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); val 356 drivers/pci/controller/dwc/pci-meson.c u32 val; val 359 drivers/pci/controller/dwc/pci-meson.c val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); val 360 drivers/pci/controller/dwc/pci-meson.c val &= ~PCIE_CAP_MAX_READ_REQ_MASK; val 361 drivers/pci/controller/dwc/pci-meson.c meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); val 363 drivers/pci/controller/dwc/pci-meson.c val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); val 364 drivers/pci/controller/dwc/pci-meson.c val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size); val 365 drivers/pci/controller/dwc/pci-meson.c meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); val 399 drivers/pci/controller/dwc/pci-meson.c u32 *val) val 404 drivers/pci/controller/dwc/pci-meson.c ret = dw_pcie_read(pci->dbi_base + where, size, val); val 414 drivers/pci/controller/dwc/pci-meson.c *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff); val 416 drivers/pci/controller/dwc/pci-meson.c *val = PCI_CLASS_BRIDGE_PCI; val 418 drivers/pci/controller/dwc/pci-meson.c *val = PCI_CLASS_BRIDGE_PCI & 0xff; val 420 drivers/pci/controller/dwc/pci-meson.c *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff; val 426 drivers/pci/controller/dwc/pci-meson.c int size, u32 val) val 430 drivers/pci/controller/dwc/pci-meson.c return dw_pcie_write(pci->dbi_base + where, size, val); val 156 drivers/pci/controller/dwc/pcie-al.c u32 val) val 158 drivers/pci/controller/dwc/pcie-al.c writel_relaxed(val, pcie->controller_base + offset); val 253 drivers/pci/controller/dwc/pcie-al.c u32 *val) val 263 drivers/pci/controller/dwc/pcie-al.c rc = dw_pcie_read(pci_addr + where, size, val); val 268 drivers/pci/controller/dwc/pcie-al.c (pci_addr + where), *val); val 275 drivers/pci/controller/dwc/pcie-al.c u32 val) val 285 drivers/pci/controller/dwc/pcie-al.c rc = dw_pcie_write(pci_addr + where, size, val); val 290 drivers/pci/controller/dwc/pcie-al.c (pci_addr + where), val); val 223 drivers/pci/controller/dwc/pcie-armada8k.c u32 val; val 230 drivers/pci/controller/dwc/pcie-armada8k.c val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); val 231 drivers/pci/controller/dwc/pcie-armada8k.c dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); val 96 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 98 drivers/pci/controller/dwc/pcie-artpec6.c regmap_read(artpec6_pcie->regmap, offset, &val); val 99 drivers/pci/controller/dwc/pcie-artpec6.c return val; val 102 drivers/pci/controller/dwc/pcie-artpec6.c static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val) val 104 drivers/pci/controller/dwc/pcie-artpec6.c regmap_write(artpec6_pcie->regmap, offset, val); val 127 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 129 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); val 130 drivers/pci/controller/dwc/pcie-artpec6.c val |= PCIECFG_LTSSM_ENABLE; val 131 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); val 139 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 141 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); val 142 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~PCIECFG_LTSSM_ENABLE; val 143 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); val 156 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 162 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, NOCCFG); val 165 drivers/pci/controller/dwc/pcie-artpec6.c (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE))); val 172 drivers/pci/controller/dwc/pcie-artpec6.c val = readl(artpec6_pcie->phy_base + PHY_STATUS); val 174 drivers/pci/controller/dwc/pcie-artpec6.c } while (retries && !(val & PHY_COSPLLLOCK)); val 183 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 190 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, NOCCFG); val 193 drivers/pci/controller/dwc/pcie-artpec6.c (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE))); val 223 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 225 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); val 226 drivers/pci/controller/dwc/pcie-artpec6.c val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */ val 230 drivers/pci/controller/dwc/pcie-artpec6.c val |= PCIECFG_REFCLK_ENABLE; val 231 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~PCIECFG_DBG_OEN; val 232 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~PCIECFG_CLKREQ_B; val 233 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); val 236 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, NOCCFG); val 237 drivers/pci/controller/dwc/pcie-artpec6.c val |= NOCCFG_ENABLE_CLK_PCIE; val 238 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, NOCCFG, val); val 241 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); val 242 drivers/pci/controller/dwc/pcie-artpec6.c val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE; val 243 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); val 246 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, NOCCFG); val 247 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~NOCCFG_POWER_PCIE_IDLEREQ; val 248 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, NOCCFG, val); val 254 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 258 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIESTAT); val 259 drivers/pci/controller/dwc/pcie-artpec6.c extrefclk = !!(val & PCIESTAT_EXTREFCLK); val 263 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); val 264 drivers/pci/controller/dwc/pcie-artpec6.c val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */ val 267 drivers/pci/controller/dwc/pcie-artpec6.c val |= PCIECFG_REFCLKSEL; val 269 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~PCIECFG_REFCLKSEL; val 270 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); val 273 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, NOCCFG); val 274 drivers/pci/controller/dwc/pcie-artpec6.c val |= NOCCFG_ENABLE_CLK_PCIE; val 275 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, NOCCFG, val); val 278 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, NOCCFG); val 279 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~NOCCFG_POWER_PCIE_IDLEREQ; val 280 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, NOCCFG, val); val 298 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 307 drivers/pci/controller/dwc/pcie-artpec6.c val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF); val 308 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~ACK_N_FTS_MASK; val 309 drivers/pci/controller/dwc/pcie-artpec6.c val |= ACK_N_FTS(180); val 310 drivers/pci/controller/dwc/pcie-artpec6.c dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val); val 316 drivers/pci/controller/dwc/pcie-artpec6.c val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val 317 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~FAST_TRAINING_SEQ_MASK; val 318 drivers/pci/controller/dwc/pcie-artpec6.c val |= FAST_TRAINING_SEQ(180); val 319 drivers/pci/controller/dwc/pcie-artpec6.c dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); val 324 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 326 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); val 329 drivers/pci/controller/dwc/pcie-artpec6.c val |= PCIECFG_CORE_RESET_REQ; val 332 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~PCIECFG_NOC_RESET; val 335 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); val 340 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 342 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); val 345 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~PCIECFG_CORE_RESET_REQ; val 348 drivers/pci/controller/dwc/pcie-artpec6.c val |= PCIECFG_NOC_RESET; val 351 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); val 549 drivers/pci/controller/dwc/pcie-artpec6.c u32 val; val 554 drivers/pci/controller/dwc/pcie-artpec6.c val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); val 555 drivers/pci/controller/dwc/pcie-artpec6.c val &= ~PCIECFG_DEVICE_TYPE_MASK; val 556 drivers/pci/controller/dwc/pcie-artpec6.c artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); val 218 drivers/pci/controller/dwc/pcie-designware-ep.c u32 val, reg; val 224 drivers/pci/controller/dwc/pcie-designware-ep.c val = dw_pcie_readw_dbi(pci, reg); val 225 drivers/pci/controller/dwc/pcie-designware-ep.c if (!(val & PCI_MSI_FLAGS_ENABLE)) val 228 drivers/pci/controller/dwc/pcie-designware-ep.c val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; val 230 drivers/pci/controller/dwc/pcie-designware-ep.c return val; val 237 drivers/pci/controller/dwc/pcie-designware-ep.c u32 val, reg; val 243 drivers/pci/controller/dwc/pcie-designware-ep.c val = dw_pcie_readw_dbi(pci, reg); val 244 drivers/pci/controller/dwc/pcie-designware-ep.c val &= ~PCI_MSI_FLAGS_QMASK; val 245 drivers/pci/controller/dwc/pcie-designware-ep.c val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; val 247 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writew_dbi(pci, reg, val); val 257 drivers/pci/controller/dwc/pcie-designware-ep.c u32 val, reg; val 263 drivers/pci/controller/dwc/pcie-designware-ep.c val = dw_pcie_readw_dbi(pci, reg); val 264 drivers/pci/controller/dwc/pcie-designware-ep.c if (!(val & PCI_MSIX_FLAGS_ENABLE)) val 267 drivers/pci/controller/dwc/pcie-designware-ep.c val &= PCI_MSIX_FLAGS_QSIZE; val 269 drivers/pci/controller/dwc/pcie-designware-ep.c return val; val 276 drivers/pci/controller/dwc/pcie-designware-ep.c u32 val, reg; val 282 drivers/pci/controller/dwc/pcie-designware-ep.c val = dw_pcie_readw_dbi(pci, reg); val 283 drivers/pci/controller/dwc/pcie-designware-ep.c val &= ~PCI_MSIX_FLAGS_QSIZE; val 284 drivers/pci/controller/dwc/pcie-designware-ep.c val |= interrupts; val 286 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writew_dbi(pci, reg, val); val 24 drivers/pci/controller/dwc/pcie-designware-host.c u32 *val) val 29 drivers/pci/controller/dwc/pcie-designware-host.c return pp->ops->rd_own_conf(pp, where, size, val); val 32 drivers/pci/controller/dwc/pcie-designware-host.c return dw_pcie_read(pci->dbi_base + where, size, val); val 36 drivers/pci/controller/dwc/pcie-designware-host.c u32 val) val 41 drivers/pci/controller/dwc/pcie-designware-host.c return pp->ops->wr_own_conf(pp, where, size, val); val 44 drivers/pci/controller/dwc/pcie-designware-host.c return dw_pcie_write(pci->dbi_base + where, size, val); val 81 drivers/pci/controller/dwc/pcie-designware-host.c unsigned long val; val 95 drivers/pci/controller/dwc/pcie-designware-host.c val = status; val 97 drivers/pci/controller/dwc/pcie-designware-host.c while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, val 528 drivers/pci/controller/dwc/pcie-designware-host.c u32 devfn, int where, int size, u32 *val, val 556 drivers/pci/controller/dwc/pcie-designware-host.c ret = dw_pcie_write(va_cfg_base + where, size, *val); val 558 drivers/pci/controller/dwc/pcie-designware-host.c ret = dw_pcie_read(va_cfg_base + where, size, val); val 569 drivers/pci/controller/dwc/pcie-designware-host.c u32 devfn, int where, int size, u32 *val) val 573 drivers/pci/controller/dwc/pcie-designware-host.c size, val); val 575 drivers/pci/controller/dwc/pcie-designware-host.c return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val, val 580 drivers/pci/controller/dwc/pcie-designware-host.c u32 devfn, int where, int size, u32 val) val 584 drivers/pci/controller/dwc/pcie-designware-host.c size, val); val 586 drivers/pci/controller/dwc/pcie-designware-host.c return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val, val 609 drivers/pci/controller/dwc/pcie-designware-host.c int size, u32 *val) val 614 drivers/pci/controller/dwc/pcie-designware-host.c *val = 0xffffffff; val 619 drivers/pci/controller/dwc/pcie-designware-host.c return dw_pcie_rd_own_conf(pp, where, size, val); val 621 drivers/pci/controller/dwc/pcie-designware-host.c return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); val 625 drivers/pci/controller/dwc/pcie-designware-host.c int where, int size, u32 val) val 633 drivers/pci/controller/dwc/pcie-designware-host.c return dw_pcie_wr_own_conf(pp, where, size, val); val 635 drivers/pci/controller/dwc/pcie-designware-host.c return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); val 645 drivers/pci/controller/dwc/pcie-designware-host.c u32 val, ctrl, num_ctrls; val 676 drivers/pci/controller/dwc/pcie-designware-host.c val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); val 677 drivers/pci/controller/dwc/pcie-designware-host.c val &= 0xffff00ff; val 678 drivers/pci/controller/dwc/pcie-designware-host.c val |= 0x00000100; val 679 drivers/pci/controller/dwc/pcie-designware-host.c dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); val 682 drivers/pci/controller/dwc/pcie-designware-host.c val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); val 683 drivers/pci/controller/dwc/pcie-designware-host.c val &= 0xff000000; val 684 drivers/pci/controller/dwc/pcie-designware-host.c val |= 0x00ff0100; val 685 drivers/pci/controller/dwc/pcie-designware-host.c dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); val 688 drivers/pci/controller/dwc/pcie-designware-host.c val = dw_pcie_readl_dbi(pci, PCI_COMMAND); val 689 drivers/pci/controller/dwc/pcie-designware-host.c val &= 0xffff0000; val 690 drivers/pci/controller/dwc/pcie-designware-host.c val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | val 692 drivers/pci/controller/dwc/pcie-designware-host.c dw_pcie_writel_dbi(pci, PCI_COMMAND, val); val 714 drivers/pci/controller/dwc/pcie-designware-host.c dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val 715 drivers/pci/controller/dwc/pcie-designware-host.c val |= PORT_LOGIC_SPEED_CHANGE; val 716 drivers/pci/controller/dwc/pcie-designware-host.c dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); val 97 drivers/pci/controller/dwc/pcie-designware.c int dw_pcie_read(void __iomem *addr, int size, u32 *val) val 100 drivers/pci/controller/dwc/pcie-designware.c *val = 0; val 105 drivers/pci/controller/dwc/pcie-designware.c *val = readl(addr); val 107 drivers/pci/controller/dwc/pcie-designware.c *val = readw(addr); val 109 drivers/pci/controller/dwc/pcie-designware.c *val = readb(addr); val 111 drivers/pci/controller/dwc/pcie-designware.c *val = 0; val 119 drivers/pci/controller/dwc/pcie-designware.c int dw_pcie_write(void __iomem *addr, int size, u32 val) val 125 drivers/pci/controller/dwc/pcie-designware.c writel(val, addr); val 127 drivers/pci/controller/dwc/pcie-designware.c writew(val, addr); val 129 drivers/pci/controller/dwc/pcie-designware.c writeb(val, addr); val 140 drivers/pci/controller/dwc/pcie-designware.c u32 val; val 145 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_read(pci->dbi_base + reg, size, &val); val 149 drivers/pci/controller/dwc/pcie-designware.c return val; val 153 drivers/pci/controller/dwc/pcie-designware.c void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) val 158 drivers/pci/controller/dwc/pcie-designware.c pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); val 162 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_write(pci->dbi_base + reg, size, val); val 171 drivers/pci/controller/dwc/pcie-designware.c u32 val; val 176 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_read(pci->dbi_base2 + reg, size, &val); val 180 drivers/pci/controller/dwc/pcie-designware.c return val; val 183 drivers/pci/controller/dwc/pcie-designware.c void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) val 188 drivers/pci/controller/dwc/pcie-designware.c pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); val 192 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); val 200 drivers/pci/controller/dwc/pcie-designware.c u32 val; val 205 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_read(pci->atu_base + reg, size, &val); val 209 drivers/pci/controller/dwc/pcie-designware.c return val; val 212 drivers/pci/controller/dwc/pcie-designware.c void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val) val 217 drivers/pci/controller/dwc/pcie-designware.c pci->ops->write_dbi(pci, pci->atu_base, reg, size, val); val 221 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_write(pci->atu_base + reg, size, val); val 234 drivers/pci/controller/dwc/pcie-designware.c u32 val) val 238 drivers/pci/controller/dwc/pcie-designware.c dw_pcie_writel_atu(pci, offset + reg, val); val 245 drivers/pci/controller/dwc/pcie-designware.c u32 retries, val; val 267 drivers/pci/controller/dwc/pcie-designware.c val = dw_pcie_readl_ob_unroll(pci, index, val 269 drivers/pci/controller/dwc/pcie-designware.c if (val & PCIE_ATU_ENABLE) val 280 drivers/pci/controller/dwc/pcie-designware.c u32 retries, val; val 311 drivers/pci/controller/dwc/pcie-designware.c val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); val 312 drivers/pci/controller/dwc/pcie-designware.c if (val & PCIE_ATU_ENABLE) val 328 drivers/pci/controller/dwc/pcie-designware.c u32 val) val 332 drivers/pci/controller/dwc/pcie-designware.c dw_pcie_writel_atu(pci, offset + reg, val); val 340 drivers/pci/controller/dwc/pcie-designware.c u32 retries, val; val 368 drivers/pci/controller/dwc/pcie-designware.c val = dw_pcie_readl_ib_unroll(pci, index, val 370 drivers/pci/controller/dwc/pcie-designware.c if (val & PCIE_ATU_ENABLE) val 384 drivers/pci/controller/dwc/pcie-designware.c u32 retries, val; val 415 drivers/pci/controller/dwc/pcie-designware.c val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); val 416 drivers/pci/controller/dwc/pcie-designware.c if (val & PCIE_ATU_ENABLE) val 467 drivers/pci/controller/dwc/pcie-designware.c u32 val; val 472 drivers/pci/controller/dwc/pcie-designware.c val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); val 473 drivers/pci/controller/dwc/pcie-designware.c return ((val & PCIE_PORT_DEBUG1_LINK_UP) && val 474 drivers/pci/controller/dwc/pcie-designware.c (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); val 479 drivers/pci/controller/dwc/pcie-designware.c u32 val; val 481 drivers/pci/controller/dwc/pcie-designware.c val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); val 482 drivers/pci/controller/dwc/pcie-designware.c if (val == 0xffffffff) val 491 drivers/pci/controller/dwc/pcie-designware.c u32 val; val 513 drivers/pci/controller/dwc/pcie-designware.c val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val 514 drivers/pci/controller/dwc/pcie-designware.c val &= ~PORT_LINK_MODE_MASK; val 517 drivers/pci/controller/dwc/pcie-designware.c val |= PORT_LINK_MODE_1_LANES; val 520 drivers/pci/controller/dwc/pcie-designware.c val |= PORT_LINK_MODE_2_LANES; val 523 drivers/pci/controller/dwc/pcie-designware.c val |= PORT_LINK_MODE_4_LANES; val 526 drivers/pci/controller/dwc/pcie-designware.c val |= PORT_LINK_MODE_8_LANES; val 532 drivers/pci/controller/dwc/pcie-designware.c dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); val 535 drivers/pci/controller/dwc/pcie-designware.c val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val 536 drivers/pci/controller/dwc/pcie-designware.c val &= ~PORT_LOGIC_LINK_WIDTH_MASK; val 539 drivers/pci/controller/dwc/pcie-designware.c val |= PORT_LOGIC_LINK_WIDTH_1_LANES; val 542 drivers/pci/controller/dwc/pcie-designware.c val |= PORT_LOGIC_LINK_WIDTH_2_LANES; val 545 drivers/pci/controller/dwc/pcie-designware.c val |= PORT_LOGIC_LINK_WIDTH_4_LANES; val 548 drivers/pci/controller/dwc/pcie-designware.c val |= PORT_LOGIC_LINK_WIDTH_8_LANES; val 551 drivers/pci/controller/dwc/pcie-designware.c dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); val 554 drivers/pci/controller/dwc/pcie-designware.c val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); val 555 drivers/pci/controller/dwc/pcie-designware.c val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | val 557 drivers/pci/controller/dwc/pcie-designware.c dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); val 153 drivers/pci/controller/dwc/pcie-designware.h int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); val 154 drivers/pci/controller/dwc/pcie-designware.h int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); val 156 drivers/pci/controller/dwc/pcie-designware.h unsigned int devfn, int where, int size, u32 *val); val 158 drivers/pci/controller/dwc/pcie-designware.h unsigned int devfn, int where, int size, u32 val); val 234 drivers/pci/controller/dwc/pcie-designware.h size_t size, u32 val); val 238 drivers/pci/controller/dwc/pcie-designware.h size_t size, u32 val); val 266 drivers/pci/controller/dwc/pcie-designware.h int dw_pcie_read(void __iomem *addr, int size, u32 *val); val 267 drivers/pci/controller/dwc/pcie-designware.h int dw_pcie_write(void __iomem *addr, int size, u32 val); val 270 drivers/pci/controller/dwc/pcie-designware.h void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val); val 272 drivers/pci/controller/dwc/pcie-designware.h void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); val 274 drivers/pci/controller/dwc/pcie-designware.h void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val); val 286 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) val 288 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_dbi(pci, reg, 0x4, val); val 296 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val) val 298 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_dbi(pci, reg, 0x2, val); val 306 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val) val 308 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_dbi(pci, reg, 0x1, val); val 316 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) val 318 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_dbi2(pci, reg, 0x4, val); val 326 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) val 328 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_atu(pci, reg, 0x4, val); val 339 drivers/pci/controller/dwc/pcie-designware.h u32 val; val 342 drivers/pci/controller/dwc/pcie-designware.h val = dw_pcie_readl_dbi(pci, reg); val 343 drivers/pci/controller/dwc/pcie-designware.h val |= PCIE_DBI_RO_WR_EN; val 344 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_writel_dbi(pci, reg, val); val 350 drivers/pci/controller/dwc/pcie-designware.h u32 val; val 353 drivers/pci/controller/dwc/pcie-designware.h val = dw_pcie_readl_dbi(pci, reg); val 354 drivers/pci/controller/dwc/pcie-designware.h val &= ~PCIE_DBI_RO_WR_EN; val 355 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_writel_dbi(pci, reg, val); val 27 drivers/pci/controller/dwc/pcie-hisi.c int size, u32 *val) val 38 drivers/pci/controller/dwc/pcie-hisi.c size, val); val 41 drivers/pci/controller/dwc/pcie-hisi.c return pci_generic_config_read(bus, devfn, where, size, val); val 45 drivers/pci/controller/dwc/pcie-hisi.c int where, int size, u32 val) val 56 drivers/pci/controller/dwc/pcie-hisi.c size, val); val 59 drivers/pci/controller/dwc/pcie-hisi.c return pci_generic_config_write(bus, devfn, where, size, val); val 146 drivers/pci/controller/dwc/pcie-hisi.c u32 *val) val 158 drivers/pci/controller/dwc/pcie-hisi.c *val = *(u8 __force *) walker; val 160 drivers/pci/controller/dwc/pcie-hisi.c *val = *(u16 __force *) walker; val 162 drivers/pci/controller/dwc/pcie-hisi.c *val = reg_val; val 171 drivers/pci/controller/dwc/pcie-hisi.c u32 val) val 181 drivers/pci/controller/dwc/pcie-hisi.c dw_pcie_writel_dbi(pci, reg, val); val 184 drivers/pci/controller/dwc/pcie-hisi.c *(u16 __force *) walker = val; val 188 drivers/pci/controller/dwc/pcie-hisi.c *(u8 __force *) walker = val; val 198 drivers/pci/controller/dwc/pcie-hisi.c u32 val; val 201 drivers/pci/controller/dwc/pcie-hisi.c 0x100 * hisi_pcie->port_id, &val); val 203 drivers/pci/controller/dwc/pcie-hisi.c return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); val 209 drivers/pci/controller/dwc/pcie-hisi.c u32 val; val 211 drivers/pci/controller/dwc/pcie-hisi.c val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4); val 213 drivers/pci/controller/dwc/pcie-hisi.c return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); val 72 drivers/pci/controller/dwc/pcie-histb.c static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val) val 74 drivers/pci/controller/dwc/pcie-histb.c writel(val, histb_pcie->ctrl + reg); val 81 drivers/pci/controller/dwc/pcie-histb.c u32 val; val 83 drivers/pci/controller/dwc/pcie-histb.c val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0); val 85 drivers/pci/controller/dwc/pcie-histb.c val |= PCIE_ELBI_SLV_DBI_ENABLE; val 87 drivers/pci/controller/dwc/pcie-histb.c val &= ~PCIE_ELBI_SLV_DBI_ENABLE; val 88 drivers/pci/controller/dwc/pcie-histb.c histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, val); val 95 drivers/pci/controller/dwc/pcie-histb.c u32 val; val 97 drivers/pci/controller/dwc/pcie-histb.c val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL1); val 99 drivers/pci/controller/dwc/pcie-histb.c val |= PCIE_ELBI_SLV_DBI_ENABLE; val 101 drivers/pci/controller/dwc/pcie-histb.c val &= ~PCIE_ELBI_SLV_DBI_ENABLE; val 102 drivers/pci/controller/dwc/pcie-histb.c histb_pcie_writel(hipcie, PCIE_SYS_CTRL1, val); val 108 drivers/pci/controller/dwc/pcie-histb.c u32 val; val 111 drivers/pci/controller/dwc/pcie-histb.c dw_pcie_read(base + reg, size, &val); val 114 drivers/pci/controller/dwc/pcie-histb.c return val; val 118 drivers/pci/controller/dwc/pcie-histb.c u32 reg, size_t size, u32 val) val 121 drivers/pci/controller/dwc/pcie-histb.c dw_pcie_write(base + reg, size, val); val 126 drivers/pci/controller/dwc/pcie-histb.c int size, u32 *val) val 132 drivers/pci/controller/dwc/pcie-histb.c ret = dw_pcie_read(pci->dbi_base + where, size, val); val 139 drivers/pci/controller/dwc/pcie-histb.c int size, u32 val) val 145 drivers/pci/controller/dwc/pcie-histb.c ret = dw_pcie_write(pci->dbi_base + where, size, val); val 97 drivers/pci/controller/dwc/pcie-kirin.c u32 val, u32 reg) val 99 drivers/pci/controller/dwc/pcie-kirin.c writel(val, kirin_pcie->apb_base + reg); val 109 drivers/pci/controller/dwc/pcie-kirin.c u32 val, u32 reg) val 111 drivers/pci/controller/dwc/pcie-kirin.c writel(val, kirin_pcie->phy_base + reg); val 213 drivers/pci/controller/dwc/pcie-kirin.c u32 val; val 215 drivers/pci/controller/dwc/pcie-kirin.c regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); val 216 drivers/pci/controller/dwc/pcie-kirin.c val |= PCIE_DEBOUNCE_PARAM; val 217 drivers/pci/controller/dwc/pcie-kirin.c val &= ~PCIE_OE_BYPASS; val 218 drivers/pci/controller/dwc/pcie-kirin.c regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val); val 313 drivers/pci/controller/dwc/pcie-kirin.c u32 val; val 315 drivers/pci/controller/dwc/pcie-kirin.c val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR); val 317 drivers/pci/controller/dwc/pcie-kirin.c val = val | PCIE_ELBI_SLV_DBI_ENABLE; val 319 drivers/pci/controller/dwc/pcie-kirin.c val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; val 321 drivers/pci/controller/dwc/pcie-kirin.c kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR); val 327 drivers/pci/controller/dwc/pcie-kirin.c u32 val; val 329 drivers/pci/controller/dwc/pcie-kirin.c val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR); val 331 drivers/pci/controller/dwc/pcie-kirin.c val = val | PCIE_ELBI_SLV_DBI_ENABLE; val 333 drivers/pci/controller/dwc/pcie-kirin.c val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; val 335 drivers/pci/controller/dwc/pcie-kirin.c kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR); val 339 drivers/pci/controller/dwc/pcie-kirin.c int where, int size, u32 *val) val 346 drivers/pci/controller/dwc/pcie-kirin.c ret = dw_pcie_read(pci->dbi_base + where, size, val); val 353 drivers/pci/controller/dwc/pcie-kirin.c int where, int size, u32 val) val 360 drivers/pci/controller/dwc/pcie-kirin.c ret = dw_pcie_write(pci->dbi_base + where, size, val); val 380 drivers/pci/controller/dwc/pcie-kirin.c u32 reg, size_t size, u32 val) val 385 drivers/pci/controller/dwc/pcie-kirin.c dw_pcie_write(base + reg, size, val); val 392 drivers/pci/controller/dwc/pcie-kirin.c u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0); val 394 drivers/pci/controller/dwc/pcie-kirin.c if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE) val 203 drivers/pci/controller/dwc/pcie-qcom.c u32 val; val 206 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL); val 207 drivers/pci/controller/dwc/pcie-qcom.c val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE; val 208 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); val 278 drivers/pci/controller/dwc/pcie-qcom.c u32 val; val 318 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val 319 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(0); val 320 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); val 323 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); val 324 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(16); val 325 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); val 464 drivers/pci/controller/dwc/pcie-qcom.c u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); val 466 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(31); val 467 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); val 487 drivers/pci/controller/dwc/pcie-qcom.c u32 val; val 490 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_LTSSM); val 491 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(8); val 492 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_LTSSM); val 553 drivers/pci/controller/dwc/pcie-qcom.c u32 val; val 587 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val 588 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(0); val 589 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); val 595 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); val 596 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(29); val 597 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); val 599 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); val 600 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(4); val 601 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); val 603 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); val 604 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(31); val 605 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); val 742 drivers/pci/controller/dwc/pcie-qcom.c u32 val; val 868 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val 869 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(0); val 870 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); val 876 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); val 877 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(29); val 878 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); val 880 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); val 881 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(4); val 882 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); val 884 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); val 885 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(31); val 886 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); val 967 drivers/pci/controller/dwc/pcie-qcom.c u32 val; val 1027 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val 1028 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(0); val 1029 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); val 1043 drivers/pci/controller/dwc/pcie-qcom.c val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); val 1044 drivers/pci/controller/dwc/pcie-qcom.c val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT; val 1045 drivers/pci/controller/dwc/pcie-qcom.c writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); val 1073 drivers/pci/controller/dwc/pcie-qcom.c u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); val 1075 drivers/pci/controller/dwc/pcie-qcom.c return !!(val & PCI_EXP_LNKSTA_DLLLA); val 77 drivers/pci/controller/dwc/pcie-spear13xx.c u32 val; val 92 drivers/pci/controller/dwc/pcie-spear13xx.c dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); val 93 drivers/pci/controller/dwc/pcie-spear13xx.c val &= ~PCI_EXP_DEVCTL_READRQ; val 94 drivers/pci/controller/dwc/pcie-spear13xx.c dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); val 105 drivers/pci/controller/dwc/pcie-spear13xx.c 4, &val); val 106 drivers/pci/controller/dwc/pcie-spear13xx.c if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val 107 drivers/pci/controller/dwc/pcie-spear13xx.c val &= ~((u32)PCI_EXP_LNKCAP_SLS); val 108 drivers/pci/controller/dwc/pcie-spear13xx.c val |= PCI_EXP_LNKCAP_SLS_2_5GB; val 110 drivers/pci/controller/dwc/pcie-spear13xx.c PCI_EXP_LNKCAP, 4, val); val 114 drivers/pci/controller/dwc/pcie-spear13xx.c 2, &val); val 115 drivers/pci/controller/dwc/pcie-spear13xx.c if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val 116 drivers/pci/controller/dwc/pcie-spear13xx.c val &= ~((u32)PCI_EXP_LNKCAP_SLS); val 117 drivers/pci/controller/dwc/pcie-spear13xx.c val |= PCI_EXP_LNKCAP_SLS_2_5GB; val 119 drivers/pci/controller/dwc/pcie-spear13xx.c PCI_EXP_LNKCTL2, 2, val); val 315 drivers/pci/controller/dwc/pcie-tegra194.c u16 val; val 322 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); val 323 drivers/pci/controller/dwc/pcie-tegra194.c if (val & PCI_EXP_LNKSTA_LBMS) { val 324 drivers/pci/controller/dwc/pcie-tegra194.c current_link_width = (val & PCI_EXP_LNKSTA_NLW) >> val 328 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + val 330 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~PCI_EXP_LNKCTL2_TLS; val 331 drivers/pci/controller/dwc/pcie-tegra194.c val |= PCI_EXP_LNKCTL2_TLS_2_5GT; val 333 drivers/pci/controller/dwc/pcie-tegra194.c PCI_EXP_LNKCTL2, val); val 335 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + val 337 drivers/pci/controller/dwc/pcie-tegra194.c val |= PCI_EXP_LNKCTL_RL; val 339 drivers/pci/controller/dwc/pcie-tegra194.c PCI_EXP_LNKCTL, val); val 348 drivers/pci/controller/dwc/pcie-tegra194.c u32 val, tmp; val 351 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_STATUS_L0); val 352 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { val 353 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); val 354 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) { val 355 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); val 358 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CAR_RESET_OVRD); val 359 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; val 360 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_CAR_RESET_OVRD); val 362 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CAR_RESET_OVRD); val 363 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; val 364 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_CAR_RESET_OVRD); val 366 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL); val 367 drivers/pci/controller/dwc/pcie-tegra194.c val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE; val 368 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val); val 372 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L0_INT_INT) { val 373 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); val 374 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) { val 380 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) { val 392 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_STATUS_L0); val 393 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) { val 394 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_STATUS_L1_18); val 396 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) { val 400 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) { val 404 drivers/pci/controller/dwc/pcie-tegra194.c if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) { val 424 drivers/pci/controller/dwc/pcie-tegra194.c u32 *val) val 435 drivers/pci/controller/dwc/pcie-tegra194.c *val = 0x00000000; val 439 drivers/pci/controller/dwc/pcie-tegra194.c return dw_pcie_read(pci->dbi_base + where, size, val); val 443 drivers/pci/controller/dwc/pcie-tegra194.c u32 val) val 456 drivers/pci/controller/dwc/pcie-tegra194.c return dw_pcie_write(pci->dbi_base + where, size, val); val 462 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 464 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); val 465 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~PCI_L1SS_CAP_ASPM_L1_1; val 466 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); val 471 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 473 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); val 474 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~PCI_L1SS_CAP_ASPM_L1_2; val 475 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); val 480 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 482 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]); val 483 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT); val 484 drivers/pci/controller/dwc/pcie-tegra194.c val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; val 485 drivers/pci/controller/dwc/pcie-tegra194.c val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT; val 486 drivers/pci/controller/dwc/pcie-tegra194.c val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; val 487 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); val 488 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]); val 490 drivers/pci/controller/dwc/pcie-tegra194.c return val; val 497 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 519 drivers/pci/controller/dwc/pcie-tegra194.c val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; val 520 drivers/pci/controller/dwc/pcie-tegra194.c val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; val 521 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); val 529 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 531 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); val 532 drivers/pci/controller/dwc/pcie-tegra194.c pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; val 535 drivers/pci/controller/dwc/pcie-tegra194.c val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; val 536 drivers/pci/controller/dwc/pcie-tegra194.c val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; val 537 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val); val 540 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); val 541 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); val 542 drivers/pci/controller/dwc/pcie-tegra194.c val |= (pcie->aspm_cmrt << 8); val 543 drivers/pci/controller/dwc/pcie-tegra194.c val |= (pcie->aspm_pwr_on_t << 19); val 544 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); val 547 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL); val 548 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~L0S_ENTRANCE_LAT_MASK; val 549 drivers/pci/controller/dwc/pcie-tegra194.c val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT); val 550 drivers/pci/controller/dwc/pcie-tegra194.c val |= ENTER_ASPM; val 551 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val); val 577 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 580 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_EN_L0_0); val 581 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; val 582 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_INTR_EN_L0_0); val 584 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); val 585 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN; val 586 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); val 589 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_EN_L0_0); val 590 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN; val 591 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_INTR_EN_L0_0); val 593 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_EN_L1_18); val 594 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR; val 595 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR; val 596 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_INTR_EN_L1_18); val 615 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 618 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_EN_L0_0); val 619 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; val 620 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L0_0_INT_INT_EN; val 621 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_INTR_EN_L0_0); val 623 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); val 624 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L1_8_INTX_EN; val 625 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; val 626 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; val 628 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L1_8_AER_INT_EN; val 629 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); val 636 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 641 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_INTR_EN_L0_0); val 642 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN; val 643 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN; val 644 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_INTR_EN_L0_0); val 678 drivers/pci/controller/dwc/pcie-tegra194.c u32 val, offset, i; val 683 drivers/pci/controller/dwc/pcie-tegra194.c + (i * 2), 2, &val); val 684 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK; val 685 drivers/pci/controller/dwc/pcie-tegra194.c val |= GEN3_GEN4_EQ_PRESET_INIT; val 686 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK; val 687 drivers/pci/controller/dwc/pcie-tegra194.c val |= (GEN3_GEN4_EQ_PRESET_INIT << val 690 drivers/pci/controller/dwc/pcie-tegra194.c + (i * 2), 2, val); val 695 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_read(pci->dbi_base + offset + i, 1, &val); val 696 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK; val 697 drivers/pci/controller/dwc/pcie-tegra194.c val |= GEN3_GEN4_EQ_PRESET_INIT; val 698 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK; val 699 drivers/pci/controller/dwc/pcie-tegra194.c val |= (GEN3_GEN4_EQ_PRESET_INIT << val 701 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_write(pci->dbi_base + offset + i, 1, val); val 704 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); val 705 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; val 706 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); val 708 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); val 709 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; val 710 drivers/pci/controller/dwc/pcie-tegra194.c val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); val 711 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; val 712 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); val 714 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); val 715 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; val 716 drivers/pci/controller/dwc/pcie-tegra194.c val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); val 717 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); val 719 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); val 720 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK; val 721 drivers/pci/controller/dwc/pcie-tegra194.c val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT); val 722 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK; val 723 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); val 725 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); val 726 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; val 727 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); val 734 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 736 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); val 737 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); val 738 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); val 740 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE); val 741 drivers/pci/controller/dwc/pcie-tegra194.c val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE; val 742 drivers/pci/controller/dwc/pcie-tegra194.c val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE; val 743 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val); val 748 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL); val 749 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~(N_FTS_MASK << N_FTS_SHIFT); val 750 drivers/pci/controller/dwc/pcie-tegra194.c val |= N_FTS_VAL << N_FTS_SHIFT; val 751 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val); val 753 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL); val 754 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~FTS_MASK; val 755 drivers/pci/controller/dwc/pcie-tegra194.c val |= FTS_VAL; val 756 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val); val 759 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); val 760 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT); val 761 drivers/pci/controller/dwc/pcie-tegra194.c val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 << val 763 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); val 767 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + val 769 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~PCI_EXP_LNKCAP_SLS; val 770 drivers/pci/controller/dwc/pcie-tegra194.c val |= pcie->max_speed; val 772 drivers/pci/controller/dwc/pcie-tegra194.c val); val 776 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); val 777 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~PCI_EXP_LNKCAP_MLW; val 778 drivers/pci/controller/dwc/pcie-tegra194.c val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT); val 779 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); val 785 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); val 786 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; val 787 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); val 790 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); val 791 drivers/pci/controller/dwc/pcie-tegra194.c val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; val 792 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); val 800 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_PINMUX); val 801 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~APPL_PINMUX_PEX_RST; val 802 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_PINMUX); val 807 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CTRL); val 808 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_CTRL_LTSSM_EN; val 809 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_CTRL); val 812 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_PINMUX); val 813 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_PINMUX_PEX_RST; val 814 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_PINMUX); val 823 drivers/pci/controller/dwc/pcie-tegra194.c u32 val, tmp, offset, speed; val 836 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_DEBUG); val 837 drivers/pci/controller/dwc/pcie-tegra194.c val &= APPL_DEBUG_LTSSM_STATE_MASK; val 838 drivers/pci/controller/dwc/pcie-tegra194.c val >>= APPL_DEBUG_LTSSM_STATE_SHIFT; val 841 drivers/pci/controller/dwc/pcie-tegra194.c if (!(val == 0x11 && !tmp)) { val 849 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CTRL); val 850 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~APPL_CTRL_LTSSM_EN; val 851 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_CTRL); val 857 drivers/pci/controller/dwc/pcie-tegra194.c val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); val 858 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~PCI_DLF_EXCHANGE_ENABLE; val 859 drivers/pci/controller/dwc/pcie-tegra194.c dw_pcie_writel_dbi(pci, offset, val); val 879 drivers/pci/controller/dwc/pcie-tegra194.c u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); val 881 drivers/pci/controller/dwc/pcie-tegra194.c return !!(val & PCI_EXP_LNKSTA_DLLLA); val 1131 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 1165 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CTRL); val 1166 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << val 1168 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_CTRL_HW_HOT_RST_EN; val 1169 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_CTRL); val 1187 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CTRL); val 1188 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL); val 1190 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CFG_MISC); val 1191 drivers/pci/controller/dwc/pcie-tegra194.c val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); val 1192 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_CFG_MISC); val 1195 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_PINMUX); val 1196 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN; val 1197 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_PINMUX_CLKREQ_OUT_OVRD; val 1198 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_PINMUX); val 1298 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 1303 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_RADM_STATUS); val 1304 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_PM_XMT_TURNOFF_STATE; val 1305 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_RADM_STATUS); val 1307 drivers/pci/controller/dwc/pcie-tegra194.c return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, val 1308 drivers/pci/controller/dwc/pcie-tegra194.c val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, val 1605 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 1611 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CTRL); val 1612 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << val 1614 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_CTRL_HW_HOT_RST_EN; val 1615 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_CTRL); val 1667 drivers/pci/controller/dwc/pcie-tegra194.c u32 val; val 1673 drivers/pci/controller/dwc/pcie-tegra194.c val = appl_readl(pcie, APPL_CTRL); val 1674 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << val 1676 drivers/pci/controller/dwc/pcie-tegra194.c val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST << val 1678 drivers/pci/controller/dwc/pcie-tegra194.c val &= ~APPL_CTRL_HW_HOT_RST_EN; val 1679 drivers/pci/controller/dwc/pcie-tegra194.c appl_writel(pcie, val, APPL_CTRL); val 74 drivers/pci/controller/dwc/pcie-uniphier.c u32 val; val 76 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_APP_READY_CTRL); val 78 drivers/pci/controller/dwc/pcie-uniphier.c val |= PCL_APP_LTSSM_ENABLE; val 80 drivers/pci/controller/dwc/pcie-uniphier.c val &= ~PCL_APP_LTSSM_ENABLE; val 81 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_APP_READY_CTRL); val 86 drivers/pci/controller/dwc/pcie-uniphier.c u32 val; val 89 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_APP_PM0); val 90 drivers/pci/controller/dwc/pcie-uniphier.c val |= PCL_SYS_AUX_PWR_DET; val 91 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_APP_PM0); val 94 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_PINCTRL0); val 95 drivers/pci/controller/dwc/pcie-uniphier.c val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL val 97 drivers/pci/controller/dwc/pcie-uniphier.c val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN val 99 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_PINCTRL0); val 106 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_PINCTRL0); val 107 drivers/pci/controller/dwc/pcie-uniphier.c val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN; val 108 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_PINCTRL0); val 131 drivers/pci/controller/dwc/pcie-uniphier.c u32 val, mask; val 133 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_STATUS_LINK); val 136 drivers/pci/controller/dwc/pcie-uniphier.c return (val & mask) == mask; val 175 drivers/pci/controller/dwc/pcie-uniphier.c u32 val; val 177 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INTX); val 178 drivers/pci/controller/dwc/pcie-uniphier.c val &= ~PCL_RCV_INTX_ALL_STATUS; val 179 drivers/pci/controller/dwc/pcie-uniphier.c val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT); val 180 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_RCV_INTX); val 188 drivers/pci/controller/dwc/pcie-uniphier.c u32 val; val 190 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INTX); val 191 drivers/pci/controller/dwc/pcie-uniphier.c val &= ~PCL_RCV_INTX_ALL_MASK; val 192 drivers/pci/controller/dwc/pcie-uniphier.c val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); val 193 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_RCV_INTX); val 201 drivers/pci/controller/dwc/pcie-uniphier.c u32 val; val 203 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INTX); val 204 drivers/pci/controller/dwc/pcie-uniphier.c val &= ~PCL_RCV_INTX_ALL_MASK; val 205 drivers/pci/controller/dwc/pcie-uniphier.c val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); val 206 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_RCV_INTX); val 237 drivers/pci/controller/dwc/pcie-uniphier.c u32 val, bit, virq; val 240 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INT); val 242 drivers/pci/controller/dwc/pcie-uniphier.c if (val & PCL_CFG_BW_MGT_STATUS) val 244 drivers/pci/controller/dwc/pcie-uniphier.c if (val & PCL_CFG_LINK_AUTO_BW_STATUS) val 246 drivers/pci/controller/dwc/pcie-uniphier.c if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) val 248 drivers/pci/controller/dwc/pcie-uniphier.c if (val & PCL_CFG_PME_MSI_STATUS) val 251 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_RCV_INT); val 256 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INTX); val 257 drivers/pci/controller/dwc/pcie-uniphier.c reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val); val 108 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) val 109 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) val 115 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) val 206 drivers/pci/controller/pci-aardvark.c static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) val 208 drivers/pci/controller/pci-aardvark.c writel(val, pcie->base + reg); val 218 drivers/pci/controller/pci-aardvark.c u32 val, ltssm_state; val 220 drivers/pci/controller/pci-aardvark.c val = advk_readl(pcie, CFG_REG); val 221 drivers/pci/controller/pci-aardvark.c ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; val 430 drivers/pci/controller/pci-aardvark.c u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); val 431 drivers/pci/controller/pci-aardvark.c *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE; val 444 drivers/pci/controller/pci-aardvark.c u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & val 447 drivers/pci/controller/pci-aardvark.c val |= (PCI_EXP_LNKSTA_LT << 16); val 448 drivers/pci/controller/pci-aardvark.c *value = val; val 483 drivers/pci/controller/pci-aardvark.c u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & val 486 drivers/pci/controller/pci-aardvark.c val |= PCIE_MSG_PM_PME_MASK; val 487 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, val, PCIE_ISR0_MASK_REG); val 548 drivers/pci/controller/pci-aardvark.c int where, int size, u32 *val) val 555 drivers/pci/controller/pci-aardvark.c *val = 0xffffffff; val 561 drivers/pci/controller/pci-aardvark.c size, val); val 594 drivers/pci/controller/pci-aardvark.c *val = advk_readl(pcie, PIO_RD_DATA); val 596 drivers/pci/controller/pci-aardvark.c *val = (*val >> (8 * (where & 3))) & 0xff; val 598 drivers/pci/controller/pci-aardvark.c *val = (*val >> (8 * (where & 3))) & 0xffff; val 604 drivers/pci/controller/pci-aardvark.c int where, int size, u32 val) val 617 drivers/pci/controller/pci-aardvark.c size, val); val 642 drivers/pci/controller/pci-aardvark.c reg = val << (8 * offset); val 131 drivers/pci/controller/pci-ftpci100.c resource_size_t mem_size, u32 *val) val 185 drivers/pci/controller/pci-ftpci100.c *val = outval; val 390 drivers/pci/controller/pci-ftpci100.c u32 val; val 404 drivers/pci/controller/pci-ftpci100.c ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val); val 412 drivers/pci/controller/pci-ftpci100.c i + 1, range.pci_addr, end, val); val 415 drivers/pci/controller/pci-ftpci100.c 4, val); val 443 drivers/pci/controller/pci-ftpci100.c u32 val; val 499 drivers/pci/controller/pci-ftpci100.c resource_size(io), &val)) { val 501 drivers/pci/controller/pci-ftpci100.c writel(val, p->base + PCI_IOSIZE); val 525 drivers/pci/controller/pci-ftpci100.c val = readl(p->base + PCI_CTRL); val 526 drivers/pci/controller/pci-ftpci100.c val |= PCI_COMMAND_IO; val 527 drivers/pci/controller/pci-ftpci100.c val |= PCI_COMMAND_MEMORY; val 528 drivers/pci/controller/pci-ftpci100.c val |= PCI_COMMAND_MASTER; val 529 drivers/pci/controller/pci-ftpci100.c writel(val, p->base + PCI_CTRL); val 543 drivers/pci/controller/pci-ftpci100.c u32 val; val 546 drivers/pci/controller/pci-ftpci100.c FARADAY_PCI_STATUS_CMD, 4, &val); val 549 drivers/pci/controller/pci-ftpci100.c if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) { val 663 drivers/pci/controller/pci-hyperv.c int size, u32 *val) val 672 drivers/pci/controller/pci-hyperv.c memcpy(val, ((u8 *)&hpdev->desc.v_id) + where, size); val 675 drivers/pci/controller/pci-hyperv.c memcpy(val, ((u8 *)&hpdev->desc.rev) + where - val 679 drivers/pci/controller/pci-hyperv.c memcpy(val, (u8 *)&hpdev->desc.subsystem_id + where - val 684 drivers/pci/controller/pci-hyperv.c *val = 0; val 692 drivers/pci/controller/pci-hyperv.c *val = 0; val 702 drivers/pci/controller/pci-hyperv.c *val = readb(addr); val 705 drivers/pci/controller/pci-hyperv.c *val = readw(addr); val 708 drivers/pci/controller/pci-hyperv.c *val = readl(addr); val 756 drivers/pci/controller/pci-hyperv.c int size, u32 val) val 773 drivers/pci/controller/pci-hyperv.c writeb(val, addr); val 776 drivers/pci/controller/pci-hyperv.c writew(val, addr); val 779 drivers/pci/controller/pci-hyperv.c writel(val, addr); val 806 drivers/pci/controller/pci-hyperv.c int where, int size, u32 *val) val 816 drivers/pci/controller/pci-hyperv.c _hv_pcifront_read_config(hpdev, where, size, val); val 834 drivers/pci/controller/pci-hyperv.c int where, int size, u32 val) val 844 drivers/pci/controller/pci-hyperv.c _hv_pcifront_write_config(hpdev, where, size, val); val 110 drivers/pci/controller/pci-mvebu.c static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) val 112 drivers/pci/controller/pci-mvebu.c writel(val, port->base + reg); val 230 drivers/pci/controller/pci-mvebu.c u32 devfn, int where, int size, u32 *val) val 239 drivers/pci/controller/pci-mvebu.c *val = readb_relaxed(conf_data + (where & 3)); val 242 drivers/pci/controller/pci-mvebu.c *val = readw_relaxed(conf_data + (where & 2)); val 245 drivers/pci/controller/pci-mvebu.c *val = readl_relaxed(conf_data); val 254 drivers/pci/controller/pci-mvebu.c u32 devfn, int where, int size, u32 val) val 263 drivers/pci/controller/pci-mvebu.c writeb(val, conf_data + (where & 3)); val 266 drivers/pci/controller/pci-mvebu.c writew(val, conf_data + (where & 2)); val 269 drivers/pci/controller/pci-mvebu.c writel(val, conf_data); val 616 drivers/pci/controller/pci-mvebu.c int where, int size, u32 val) val 629 drivers/pci/controller/pci-mvebu.c size, val); val 636 drivers/pci/controller/pci-mvebu.c where, size, val); val 643 drivers/pci/controller/pci-mvebu.c int size, u32 *val) val 651 drivers/pci/controller/pci-mvebu.c *val = 0xffffffff; val 658 drivers/pci/controller/pci-mvebu.c size, val); val 661 drivers/pci/controller/pci-mvebu.c *val = 0xffffffff; val 667 drivers/pci/controller/pci-mvebu.c where, size, val); val 114 drivers/pci/controller/pci-rcar-gen2.c int slot, val; val 128 drivers/pci/controller/pci-rcar-gen2.c val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG : val 131 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); val 174 drivers/pci/controller/pci-rcar-gen2.c u32 val; val 183 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG); val 184 drivers/pci/controller/pci-rcar-gen2.c val |= RCAR_PCI_INT_ALLERRORS; val 185 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG); val 197 drivers/pci/controller/pci-rcar-gen2.c u32 val; val 203 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(reg + RCAR_PCI_UNIT_REV_REG); val 204 drivers/pci/controller/pci-rcar-gen2.c dev_info(dev, "PCI: bus%u revision %x\n", sys->busnr, val); val 207 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD; val 208 drivers/pci/controller/pci-rcar-gen2.c val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST; val 209 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + RCAR_USBCTR_REG); val 213 drivers/pci/controller/pci-rcar-gen2.c val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK | val 219 drivers/pci/controller/pci-rcar-gen2.c val |= RCAR_USBCTR_PCIAHB_WIN1_2G; val 222 drivers/pci/controller/pci-rcar-gen2.c val |= RCAR_USBCTR_PCIAHB_WIN1_1G; val 225 drivers/pci/controller/pci-rcar-gen2.c val |= RCAR_USBCTR_PCIAHB_WIN1_512M; val 233 drivers/pci/controller/pci-rcar-gen2.c val |= RCAR_USBCTR_PCIAHB_WIN1_256M; val 236 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + RCAR_USBCTR_REG); val 242 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG); val 243 drivers/pci/controller/pci-rcar-gen2.c val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 | val 245 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG); val 252 drivers/pci/controller/pci-rcar-gen2.c val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM; val 253 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG); val 262 drivers/pci/controller/pci-rcar-gen2.c val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET; val 263 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + PCI_BASE_ADDRESS_0); val 265 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(reg + PCI_COMMAND); val 266 drivers/pci/controller/pci-rcar-gen2.c val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | val 268 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + PCI_COMMAND); val 1591 drivers/pci/controller/pci-tegra.c u32 val; val 1594 drivers/pci/controller/pci-tegra.c val = afi_readl(pcie, AFI_PCIE_PME); val 1595 drivers/pci/controller/pci-tegra.c val |= (0x1 << soc->ports[port->index].pme.turnoff_bit); val 1596 drivers/pci/controller/pci-tegra.c afi_writel(pcie, val, AFI_PCIE_PME); val 1599 drivers/pci/controller/pci-tegra.c err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val, val 1600 drivers/pci/controller/pci-tegra.c val & (0x1 << ack_bit), 1, PME_ACK_TIMEOUT); val 1607 drivers/pci/controller/pci-tegra.c val = afi_readl(pcie, AFI_PCIE_PME); val 1608 drivers/pci/controller/pci-tegra.c val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit); val 1609 drivers/pci/controller/pci-tegra.c afi_writel(pcie, val, AFI_PCIE_PME); val 16 drivers/pci/controller/pci-thunder-ecam.c static void set_val(u32 v, int where, int size, u32 *val) val 26 drivers/pci/controller/pci-thunder-ecam.c *val = v; val 30 drivers/pci/controller/pci-thunder-ecam.c unsigned int devfn, int where, int size, u32 *val) val 39 drivers/pci/controller/pci-thunder-ecam.c set_val(e0, where, size, val); val 45 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 51 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 60 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 70 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 76 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 80 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 87 drivers/pci/controller/pci-thunder-ecam.c int where, int size, u32 *val) val 103 drivers/pci/controller/pci-thunder-ecam.c return pci_generic_config_read(bus, devfn, where, size, val); val 108 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 122 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 128 drivers/pci/controller/pci-thunder-ecam.c int where, int size, u32 *val) val 139 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 150 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 163 drivers/pci/controller/pci-thunder-ecam.c size, val); val 174 drivers/pci/controller/pci-thunder-ecam.c *val = 0; val 180 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 200 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 209 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 215 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 222 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 234 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 241 drivers/pci/controller/pci-thunder-ecam.c size, val); val 246 drivers/pci/controller/pci-thunder-ecam.c size, val); val 251 drivers/pci/controller/pci-thunder-ecam.c size, val); val 256 drivers/pci/controller/pci-thunder-ecam.c size, val); val 261 drivers/pci/controller/pci-thunder-ecam.c size, val); val 272 drivers/pci/controller/pci-thunder-ecam.c *val = ~0; val 279 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 287 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 299 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 305 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 310 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 315 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 320 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 325 drivers/pci/controller/pci-thunder-ecam.c set_val(v, where, size, val); val 330 drivers/pci/controller/pci-thunder-ecam.c return pci_generic_config_read(bus, devfn, where, size, val); val 334 drivers/pci/controller/pci-thunder-ecam.c int where, int size, u32 val) val 345 drivers/pci/controller/pci-thunder-ecam.c return pci_generic_config_write(bus, devfn, where, size, val); val 27 drivers/pci/controller/pci-thunder-pem.c int where, int size, u32 *val) val 34 drivers/pci/controller/pci-thunder-pem.c *val = ~0; val 124 drivers/pci/controller/pci-thunder-pem.c *val = read_val; val 129 drivers/pci/controller/pci-thunder-pem.c int where, int size, u32 *val) val 142 drivers/pci/controller/pci-thunder-pem.c return thunder_pem_bridge_read(bus, devfn, where, size, val); val 144 drivers/pci/controller/pci-thunder-pem.c return pci_generic_config_read(bus, devfn, where, size, val); val 205 drivers/pci/controller/pci-thunder-pem.c int where, int size, u32 val) val 230 drivers/pci/controller/pci-thunder-pem.c val = (val & 0xff) << (8 * (where & 3)); val 231 drivers/pci/controller/pci-thunder-pem.c val |= (u32)read_val; val 239 drivers/pci/controller/pci-thunder-pem.c val = (val & 0xffff) << (8 * (where & 3)); val 240 drivers/pci/controller/pci-thunder-pem.c val |= (u32)read_val; val 257 drivers/pci/controller/pci-thunder-pem.c val &= ~mask; val 266 drivers/pci/controller/pci-thunder-pem.c val |= thunder_pem_bridge_w1_bits(where_aligned); val 272 drivers/pci/controller/pci-thunder-pem.c write_val = (((u64)val) << 32) | where_aligned; val 278 drivers/pci/controller/pci-thunder-pem.c int where, int size, u32 val) val 290 drivers/pci/controller/pci-thunder-pem.c return thunder_pem_bridge_write(bus, devfn, where, size, val); val 293 drivers/pci/controller/pci-thunder-pem.c return pci_generic_config_write(bus, devfn, where, size, val); val 487 drivers/pci/controller/pci-v3-semi.c unsigned int val; val 496 drivers/pci/controller/pci-v3-semi.c regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val); val 502 drivers/pci/controller/pci-v3-semi.c if (!(val & INTEGRATOR_SC_PCI_ENABLE)) { val 622 drivers/pci/controller/pci-v3-semi.c u32 val; val 628 drivers/pci/controller/pci-v3-semi.c val = ((u32)range->pci_addr) & V3_PCI_BASE_M_ADR_BASE; val 629 drivers/pci/controller/pci-v3-semi.c *pci_base = val; val 635 drivers/pci/controller/pci-v3-semi.c val = ((u32)range->cpu_addr) & V3_PCI_MAP_M_MAP_ADR; val 639 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_1MB; val 642 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_2MB; val 645 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_4MB; val 648 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_8MB; val 651 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_16MB; val 654 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_32MB; val 657 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_64MB; val 660 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_128MB; val 663 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_256MB; val 666 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_512MB; val 669 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_1GB; val 672 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_BASE_ADR_SIZE_2GB; val 679 drivers/pci/controller/pci-v3-semi.c val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE; val 680 drivers/pci/controller/pci-v3-semi.c *pci_map = val; val 741 drivers/pci/controller/pci-v3-semi.c u16 val; val 827 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); val 828 drivers/pci/controller/pci-v3-semi.c val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); val 829 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); val 832 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); val 833 drivers/pci/controller/pci-v3-semi.c val &= ~V3_SYSTEM_M_RST_OUT; val 834 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); val 837 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CFG); val 838 drivers/pci/controller/pci-v3-semi.c val |= V3_PCI_CFG_M_RETRY_EN; val 839 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CFG); val 842 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_LB_CFG); val 843 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */ val 844 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */ val 845 drivers/pci/controller/pci-v3-semi.c val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */ val 846 drivers/pci/controller/pci-v3-semi.c val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */ val 847 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_LB_CFG); val 850 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); val 851 drivers/pci/controller/pci-v3-semi.c val |= PCI_COMMAND_MASTER; val 852 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); val 872 drivers/pci/controller/pci-v3-semi.c val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS | val 877 drivers/pci/controller/pci-v3-semi.c val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT; val 878 drivers/pci/controller/pci-v3-semi.c val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT; val 879 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CFG); val 898 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_LB_CFG); val 899 drivers/pci/controller/pci-v3-semi.c val |= V3_LB_CFG_LB_LB_INT; val 900 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_LB_CFG); val 912 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); val 913 drivers/pci/controller/pci-v3-semi.c val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE; val 914 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); val 923 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); val 924 drivers/pci/controller/pci-v3-semi.c val |= V3_SYSTEM_M_RST_OUT; val 925 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); val 930 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); val 931 drivers/pci/controller/pci-v3-semi.c val |= V3_SYSTEM_M_LOCK; val 932 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); val 119 drivers/pci/controller/pci-versatile.c u32 val; val 173 drivers/pci/controller/pci-versatile.c val = readl(local_pci_cfg_base + PCI_COMMAND); val 174 drivers/pci/controller/pci-versatile.c val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; val 175 drivers/pci/controller/pci-versatile.c writel(val, local_pci_cfg_base + PCI_COMMAND); val 80 drivers/pci/controller/pci-xgene.c static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val) val 82 drivers/pci/controller/pci-xgene.c writel(val, port->csr_base + reg); val 166 drivers/pci/controller/pci-xgene.c int where, int size, u32 *val) val 170 drivers/pci/controller/pci-xgene.c if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != val 185 drivers/pci/controller/pci-xgene.c *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); val 188 drivers/pci/controller/pci-xgene.c *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); val 291 drivers/pci/controller/pci-xgene.c u32 val; val 294 drivers/pci/controller/pci-xgene.c val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); val 295 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, addr, val); val 298 drivers/pci/controller/pci-xgene.c val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); val 299 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, addr + 0x04, val); val 302 drivers/pci/controller/pci-xgene.c val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); val 303 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, addr + 0x04, val); val 306 drivers/pci/controller/pci-xgene.c val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); val 307 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, addr + 0x08, val); val 574 drivers/pci/controller/pci-xgene.c u32 val, lanes = 0, speed = 0; val 580 drivers/pci/controller/pci-xgene.c val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; val 581 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, BRIDGE_CFG_0, val); val 139 drivers/pci/controller/pcie-iproc-msi.c int eq, u32 val) val 143 drivers/pci/controller/pcie-iproc-msi.c writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); val 380 drivers/pci/controller/pcie-iproc-msi.c u32 val; val 404 drivers/pci/controller/pcie-iproc-msi.c val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT | val 406 drivers/pci/controller/pcie-iproc-msi.c iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val); val 413 drivers/pci/controller/pcie-iproc-msi.c val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq); val 414 drivers/pci/controller/pcie-iproc-msi.c val |= BIT(eq); val 415 drivers/pci/controller/pcie-iproc-msi.c iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val); val 422 drivers/pci/controller/pcie-iproc-msi.c u32 eq, val; val 426 drivers/pci/controller/pcie-iproc-msi.c val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq); val 427 drivers/pci/controller/pcie-iproc-msi.c val &= ~BIT(eq); val 428 drivers/pci/controller/pcie-iproc-msi.c iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val); val 431 drivers/pci/controller/pcie-iproc-msi.c val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq); val 432 drivers/pci/controller/pcie-iproc-msi.c val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT | val 434 drivers/pci/controller/pcie-iproc-msi.c iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val); val 75 drivers/pci/controller/pcie-iproc-platform.c u32 val; val 78 drivers/pci/controller/pcie-iproc-platform.c &val); val 84 drivers/pci/controller/pcie-iproc-platform.c pcie->ob.axi_offset = val; val 428 drivers/pci/controller/pcie-iproc.c enum iproc_pcie_reg reg, u32 val) val 435 drivers/pci/controller/pcie-iproc.c writel(val, pcie->base + offset); val 448 drivers/pci/controller/pcie-iproc.c u32 val; val 451 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN); val 453 drivers/pci/controller/pcie-iproc.c val &= ~APB_ERR_EN; val 455 drivers/pci/controller/pcie-iproc.c val |= APB_ERR_EN; val 456 drivers/pci/controller/pcie-iproc.c iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val); val 467 drivers/pci/controller/pcie-iproc.c u32 val; val 470 drivers/pci/controller/pcie-iproc.c val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | val 476 drivers/pci/controller/pcie-iproc.c iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); val 530 drivers/pci/controller/pcie-iproc.c static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, u32 *val) val 536 drivers/pci/controller/pcie-iproc.c dev_id = *val >> 16; val 550 drivers/pci/controller/pcie-iproc.c *val &= ~IPROC_PCI_PM_CAP_MASK; val 551 drivers/pci/controller/pcie-iproc.c *val |= IPROC_PCI_EXP_CAP << 8 | PCI_CAP_ID_PM; val 558 drivers/pci/controller/pcie-iproc.c *val = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2) << 16 | val 565 drivers/pci/controller/pcie-iproc.c *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); val 574 drivers/pci/controller/pcie-iproc.c int where, int size, u32 *val) val 586 drivers/pci/controller/pcie-iproc.c ret = pci_generic_config_read32(bus, devfn, where, size, val); val 588 drivers/pci/controller/pcie-iproc.c iproc_pcie_fix_cap(pcie, where, val); val 600 drivers/pci/controller/pcie-iproc.c *val = data; val 602 drivers/pci/controller/pcie-iproc.c *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); val 619 drivers/pci/controller/pcie-iproc.c if ((*val & DEVICE_ID_MASK) == val 665 drivers/pci/controller/pcie-iproc.c int size, u32 *val) val 671 drivers/pci/controller/pcie-iproc.c *val = ~0; val 675 drivers/pci/controller/pcie-iproc.c *val = readl(addr); val 678 drivers/pci/controller/pcie-iproc.c *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); val 685 drivers/pci/controller/pcie-iproc.c int size, u32 val) val 695 drivers/pci/controller/pcie-iproc.c writel(val, addr); val 701 drivers/pci/controller/pcie-iproc.c tmp |= val << ((where & 0x3) * 8); val 708 drivers/pci/controller/pcie-iproc.c int where, int size, u32 *val) val 715 drivers/pci/controller/pcie-iproc.c ret = iproc_pcie_config_read(bus, devfn, where, size, val); val 717 drivers/pci/controller/pcie-iproc.c ret = pci_generic_config_read32(bus, devfn, where, size, val); val 724 drivers/pci/controller/pcie-iproc.c int where, int size, u32 val) val 729 drivers/pci/controller/pcie-iproc.c ret = pci_generic_config_write32(bus, devfn, where, size, val); val 743 drivers/pci/controller/pcie-iproc.c u32 val; val 754 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); val 755 drivers/pci/controller/pcie-iproc.c val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & val 757 drivers/pci/controller/pcie-iproc.c iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); val 760 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); val 761 drivers/pci/controller/pcie-iproc.c val |= RC_PCIE_RST_OUTPUT; val 762 drivers/pci/controller/pcie-iproc.c iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); val 779 drivers/pci/controller/pcie-iproc.c u32 hdr_type, link_ctrl, link_status, class, val; val 789 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); val 790 drivers/pci/controller/pcie-iproc.c if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) { val 857 drivers/pci/controller/pcie-iproc.c u32 val; val 859 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx)); val 861 drivers/pci/controller/pcie-iproc.c return !!(val & OARR_VALID); val 1054 drivers/pci/controller/pcie-iproc.c u32 val; val 1056 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx)); val 1058 drivers/pci/controller/pcie-iproc.c return !!(val & (BIT(ib_map->nr_sizes) - 1)); val 1074 drivers/pci/controller/pcie-iproc.c u32 val; val 1106 drivers/pci/controller/pcie-iproc.c val = readl(pcie->base + imap_offset); val 1107 drivers/pci/controller/pcie-iproc.c val |= lower_32_bits(axi_addr) | IMAP_VALID; val 1108 drivers/pci/controller/pcie-iproc.c writel(val, pcie->base + imap_offset); val 1292 drivers/pci/controller/pcie-iproc.c u32 val; val 1299 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); val 1300 drivers/pci/controller/pcie-iproc.c val &= ~MSI_ENABLE_CFG; val 1301 drivers/pci/controller/pcie-iproc.c iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); val 1318 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE); val 1319 drivers/pci/controller/pcie-iproc.c val |= GIC_V3_CFG; val 1320 drivers/pci/controller/pcie-iproc.c iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val); val 1333 drivers/pci/controller/pcie-iproc.c val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); val 1334 drivers/pci/controller/pcie-iproc.c val |= MSI_ENABLE_CFG; val 1335 drivers/pci/controller/pcie-iproc.c iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); val 266 drivers/pci/controller/pcie-mediatek.c u32 val; val 269 drivers/pci/controller/pcie-mediatek.c err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, val 270 drivers/pci/controller/pcie-mediatek.c !(val & APP_CFG_REQ), 10, val 282 drivers/pci/controller/pcie-mediatek.c int where, int size, u32 *val) val 303 drivers/pci/controller/pcie-mediatek.c *val = readl(port->base + PCIE_CFG_RDATA); val 306 drivers/pci/controller/pcie-mediatek.c *val = (*val >> (8 * (where & 3))) & 0xff; val 308 drivers/pci/controller/pcie-mediatek.c *val = (*val >> (8 * (where & 3))) & 0xffff; val 314 drivers/pci/controller/pcie-mediatek.c int where, int size, u32 val) val 324 drivers/pci/controller/pcie-mediatek.c val = val << 8 * (where & 3); val 325 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_CFG_WDATA); val 328 drivers/pci/controller/pcie-mediatek.c val = readl(port->base + PCIE_APP_TLP_REQ); val 329 drivers/pci/controller/pcie-mediatek.c val |= APP_CFG_REQ; val 330 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_APP_TLP_REQ); val 361 drivers/pci/controller/pcie-mediatek.c int where, int size, u32 *val) val 369 drivers/pci/controller/pcie-mediatek.c *val = ~0; val 373 drivers/pci/controller/pcie-mediatek.c ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val); val 375 drivers/pci/controller/pcie-mediatek.c *val = ~0; val 381 drivers/pci/controller/pcie-mediatek.c int where, int size, u32 val) val 390 drivers/pci/controller/pcie-mediatek.c return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val); val 524 drivers/pci/controller/pcie-mediatek.c u32 val; val 528 drivers/pci/controller/pcie-mediatek.c val = lower_32_bits(msg_addr); val 529 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_IMSI_ADDR); val 531 drivers/pci/controller/pcie-mediatek.c val = readl(port->base + PCIE_INT_MASK); val 532 drivers/pci/controller/pcie-mediatek.c val &= ~MSI_MASK; val 533 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_INT_MASK); val 666 drivers/pci/controller/pcie-mediatek.c u32 val; val 671 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_SYS_CFG_V2); val 672 drivers/pci/controller/pcie-mediatek.c val |= PCIE_CSR_LTSSM_EN(port->slot) | val 674 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_SYS_CFG_V2); val 688 drivers/pci/controller/pcie-mediatek.c val = readl(port->base + PCIE_RST_CTRL); val 689 drivers/pci/controller/pcie-mediatek.c val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | val 691 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_RST_CTRL); val 695 drivers/pci/controller/pcie-mediatek.c val = PCI_VENDOR_ID_MEDIATEK; val 696 drivers/pci/controller/pcie-mediatek.c writew(val, port->base + PCIE_CONF_VEND_ID); val 698 drivers/pci/controller/pcie-mediatek.c val = PCI_CLASS_BRIDGE_PCI; val 699 drivers/pci/controller/pcie-mediatek.c writew(val, port->base + PCIE_CONF_CLASS_ID); val 706 drivers/pci/controller/pcie-mediatek.c err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, val 707 drivers/pci/controller/pcie-mediatek.c !!(val & PCIE_PORT_LINKUP_V2), 20, val 713 drivers/pci/controller/pcie-mediatek.c val = readl(port->base + PCIE_INT_MASK); val 714 drivers/pci/controller/pcie-mediatek.c val &= ~INTX_MASK; val 715 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_INT_MASK); val 721 drivers/pci/controller/pcie-mediatek.c val = lower_32_bits(mem->start) | val 723 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); val 725 drivers/pci/controller/pcie-mediatek.c val = upper_32_bits(mem->start); val 726 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); val 729 drivers/pci/controller/pcie-mediatek.c val = PCIE2AHB_SIZE | WIN_ENABLE; val 730 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_AXI_WINDOW0); val 757 drivers/pci/controller/pcie-mediatek.c u32 val; val 761 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_SYS_CFG); val 762 drivers/pci/controller/pcie-mediatek.c val |= PCIE_PORT_PERST(port->slot); val 763 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_SYS_CFG); val 766 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_SYS_CFG); val 767 drivers/pci/controller/pcie-mediatek.c val &= ~PCIE_PORT_PERST(port->slot); val 768 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_SYS_CFG); val 771 drivers/pci/controller/pcie-mediatek.c err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, val 772 drivers/pci/controller/pcie-mediatek.c !!(val & PCIE_PORT_LINKUP), 20, val 778 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_INT_ENABLE); val 779 drivers/pci/controller/pcie-mediatek.c val |= PCIE_PORT_INT_EN(port->slot); val 780 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_INT_ENABLE); val 792 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_CFG_DATA); val 793 drivers/pci/controller/pcie-mediatek.c val &= ~PCIE_FC_CREDIT_MASK; val 794 drivers/pci/controller/pcie-mediatek.c val |= PCIE_FC_CREDIT_VAL(0x806c); val 797 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_CFG_DATA); val 802 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_CFG_DATA); val 803 drivers/pci/controller/pcie-mediatek.c val &= ~PCIE_FTS_NUM_MASK; val 804 drivers/pci/controller/pcie-mediatek.c val |= PCIE_FTS_NUM_L0(0x50); val 807 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_CFG_DATA); val 170 drivers/pci/controller/pcie-mobiveil.c u32 val; val 172 drivers/pci/controller/pcie-mobiveil.c val = readl(pcie->csr_axi_slave_base + PAB_CTRL); val 173 drivers/pci/controller/pcie-mobiveil.c val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT); val 174 drivers/pci/controller/pcie-mobiveil.c val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT; val 176 drivers/pci/controller/pcie-mobiveil.c writel(val, pcie->csr_axi_slave_base + PAB_CTRL); val 191 drivers/pci/controller/pcie-mobiveil.c static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val) val 194 drivers/pci/controller/pcie-mobiveil.c *val = 0; val 200 drivers/pci/controller/pcie-mobiveil.c *val = readl(addr); val 203 drivers/pci/controller/pcie-mobiveil.c *val = readw(addr); val 206 drivers/pci/controller/pcie-mobiveil.c *val = readb(addr); val 209 drivers/pci/controller/pcie-mobiveil.c *val = 0; val 216 drivers/pci/controller/pcie-mobiveil.c static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val) val 223 drivers/pci/controller/pcie-mobiveil.c writel(val, addr); val 226 drivers/pci/controller/pcie-mobiveil.c writew(val, addr); val 229 drivers/pci/controller/pcie-mobiveil.c writeb(val, addr); val 241 drivers/pci/controller/pcie-mobiveil.c u32 val; val 246 drivers/pci/controller/pcie-mobiveil.c ret = mobiveil_pcie_read(addr, size, &val); val 250 drivers/pci/controller/pcie-mobiveil.c return val; val 253 drivers/pci/controller/pcie-mobiveil.c static void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, val 261 drivers/pci/controller/pcie-mobiveil.c ret = mobiveil_pcie_write(addr, size, val); val 271 drivers/pci/controller/pcie-mobiveil.c static void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) val 273 drivers/pci/controller/pcie-mobiveil.c mobiveil_csr_write(pcie, val, off, 0x4); val 347 drivers/pci/controller/pcie-mobiveil.c u32 bit, virq, val, mask; val 357 drivers/pci/controller/pcie-mobiveil.c val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); val 359 drivers/pci/controller/pcie-mobiveil.c intr_status = val & mask; val 160 drivers/pci/controller/pcie-rcar.c static void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, val 163 drivers/pci/controller/pcie-rcar.c writel(val, pcie->base + reg); val 179 drivers/pci/controller/pcie-rcar.c u32 val = rcar_pci_read_reg(pcie, where & ~3); val 181 drivers/pci/controller/pcie-rcar.c val &= ~(mask << shift); val 182 drivers/pci/controller/pcie-rcar.c val |= data << shift; val 183 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, val, where & ~3); val 189 drivers/pci/controller/pcie-rcar.c u32 val = rcar_pci_read_reg(pcie, where & ~3); val 191 drivers/pci/controller/pcie-rcar.c return val >> shift; val 275 drivers/pci/controller/pcie-rcar.c int where, int size, u32 *val) val 281 drivers/pci/controller/pcie-rcar.c bus, devfn, where, val); val 283 drivers/pci/controller/pcie-rcar.c *val = 0xffffffff; val 288 drivers/pci/controller/pcie-rcar.c *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; val 290 drivers/pci/controller/pcie-rcar.c *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; val 293 drivers/pci/controller/pcie-rcar.c bus->number, devfn, where, size, *val); val 300 drivers/pci/controller/pcie-rcar.c int where, int size, u32 val) val 313 drivers/pci/controller/pcie-rcar.c bus->number, devfn, where, size, val); val 318 drivers/pci/controller/pcie-rcar.c data |= ((val & 0xff) << shift); val 322 drivers/pci/controller/pcie-rcar.c data |= ((val & 0xffff) << shift); val 324 drivers/pci/controller/pcie-rcar.c data = val; val 62 drivers/pci/controller/pcie-rockchip-host.c u32 val; val 65 drivers/pci/controller/pcie-rockchip-host.c val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1); val 66 drivers/pci/controller/pcie-rockchip-host.c val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK; val 67 drivers/pci/controller/pcie-rockchip-host.c val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */ val 68 drivers/pci/controller/pcie-rockchip-host.c rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1); val 90 drivers/pci/controller/pcie-rockchip-host.c u32 val; val 96 drivers/pci/controller/pcie-rockchip-host.c val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP); val 97 drivers/pci/controller/pcie-rockchip-host.c map = val & PCIE_CORE_LANE_MAP_MASK; val 100 drivers/pci/controller/pcie-rockchip-host.c if (val & PCIE_CORE_LANE_MAP_REVERSE) val 107 drivers/pci/controller/pcie-rockchip-host.c int where, int size, u32 *val) val 114 drivers/pci/controller/pcie-rockchip-host.c *val = 0; val 119 drivers/pci/controller/pcie-rockchip-host.c *val = readl(addr); val 121 drivers/pci/controller/pcie-rockchip-host.c *val = readw(addr); val 123 drivers/pci/controller/pcie-rockchip-host.c *val = readb(addr); val 125 drivers/pci/controller/pcie-rockchip-host.c *val = 0; val 132 drivers/pci/controller/pcie-rockchip-host.c int where, int size, u32 val) val 141 drivers/pci/controller/pcie-rockchip-host.c writel(val, addr); val 153 drivers/pci/controller/pcie-rockchip-host.c tmp |= val << ((where & 0x3) * 8); val 161 drivers/pci/controller/pcie-rockchip-host.c int where, int size, u32 *val) val 169 drivers/pci/controller/pcie-rockchip-host.c *val = 0; val 181 drivers/pci/controller/pcie-rockchip-host.c *val = readl(rockchip->reg_base + busdev); val 183 drivers/pci/controller/pcie-rockchip-host.c *val = readw(rockchip->reg_base + busdev); val 185 drivers/pci/controller/pcie-rockchip-host.c *val = readb(rockchip->reg_base + busdev); val 187 drivers/pci/controller/pcie-rockchip-host.c *val = 0; val 195 drivers/pci/controller/pcie-rockchip-host.c int where, int size, u32 val) val 212 drivers/pci/controller/pcie-rockchip-host.c writel(val, rockchip->reg_base + busdev); val 214 drivers/pci/controller/pcie-rockchip-host.c writew(val, rockchip->reg_base + busdev); val 216 drivers/pci/controller/pcie-rockchip-host.c writeb(val, rockchip->reg_base + busdev); val 224 drivers/pci/controller/pcie-rockchip-host.c int size, u32 *val) val 229 drivers/pci/controller/pcie-rockchip-host.c *val = 0xffffffff; val 234 drivers/pci/controller/pcie-rockchip-host.c return rockchip_pcie_rd_own_conf(rockchip, where, size, val); val 237 drivers/pci/controller/pcie-rockchip-host.c val); val 241 drivers/pci/controller/pcie-rockchip-host.c int where, int size, u32 val) val 249 drivers/pci/controller/pcie-rockchip-host.c return rockchip_pcie_wr_own_conf(rockchip, where, size, val); val 252 drivers/pci/controller/pcie-rockchip-host.c val); val 21 drivers/pci/controller/pcie-rockchip.h #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) val 22 drivers/pci/controller/pcie-rockchip.h #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) val 323 drivers/pci/controller/pcie-rockchip.h static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, val 326 drivers/pci/controller/pcie-rockchip.h writel(val, rockchip->apb_base + reg); val 63 drivers/pci/controller/pcie-tango.c u32 val; val 66 drivers/pci/controller/pcie-tango.c val = readl_relaxed(pcie->base + SMP8759_ENABLE + offset); val 67 drivers/pci/controller/pcie-tango.c val = unmask ? val | bit : val & ~bit; val 68 drivers/pci/controller/pcie-tango.c writel_relaxed(val, pcie->base + SMP8759_ENABLE + offset); val 174 drivers/pci/controller/pcie-tango.c int where, int size, u32 *val) val 190 drivers/pci/controller/pcie-tango.c ret = pci_generic_config_read(bus, devfn, where, size, val); val 197 drivers/pci/controller/pcie-tango.c int where, int size, u32 val) val 204 drivers/pci/controller/pcie-tango.c ret = pci_generic_config_write(bus, devfn, where, size, val); val 180 drivers/pci/controller/pcie-xilinx-nwl.c static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) val 182 drivers/pci/controller/pcie-xilinx-nwl.c writel(val, pcie->breg_base + off); val 389 drivers/pci/controller/pcie-xilinx-nwl.c u32 val; val 394 drivers/pci/controller/pcie-xilinx-nwl.c val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); val 395 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); val 405 drivers/pci/controller/pcie-xilinx-nwl.c u32 val; val 410 drivers/pci/controller/pcie-xilinx-nwl.c val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); val 411 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); val 125 drivers/pci/controller/pcie-xilinx.c static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg) val 127 drivers/pci/controller/pcie-xilinx.c writel(val, port->reg_base + reg); val 143 drivers/pci/controller/pcie-xilinx.c unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR); val 145 drivers/pci/controller/pcie-xilinx.c if (val & XILINX_PCIE_RPEFR_ERR_VALID) { val 147 drivers/pci/controller/pcie-xilinx.c val & XILINX_PCIE_RPEFR_REQ_ID); val 392 drivers/pci/controller/pcie-xilinx.c u32 val, mask, status; val 395 drivers/pci/controller/pcie-xilinx.c val = pcie_read(port, XILINX_PCIE_REG_IDR); val 398 drivers/pci/controller/pcie-xilinx.c status = val & mask; val 433 drivers/pci/controller/pcie-xilinx.c val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); val 436 drivers/pci/controller/pcie-xilinx.c if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { val 442 drivers/pci/controller/pcie-xilinx.c if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { val 443 drivers/pci/controller/pcie-xilinx.c val = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & val 446 drivers/pci/controller/pcie-xilinx.c val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >> val 448 drivers/pci/controller/pcie-xilinx.c val = irq_find_mapping(port->leg_domain, val); val 457 drivers/pci/controller/pcie-xilinx.c !(val & XILINX_PCIE_RPIFR1_MSI_INTR)) val 458 drivers/pci/controller/pcie-xilinx.c generic_handle_irq(val); val 223 drivers/pci/endpoint/pci-ep-cfs.c u32 val; \ val 228 drivers/pci/endpoint/pci-ep-cfs.c ret = kstrtou32(page, 0, &val); \ val 231 drivers/pci/endpoint/pci-ep-cfs.c epf->header->_name = val; \ val 239 drivers/pci/endpoint/pci-ep-cfs.c u16 val; \ val 244 drivers/pci/endpoint/pci-ep-cfs.c ret = kstrtou16(page, 0, &val); \ val 247 drivers/pci/endpoint/pci-ep-cfs.c epf->header->_name = val; \ val 255 drivers/pci/endpoint/pci-ep-cfs.c u8 val; \ val 260 drivers/pci/endpoint/pci-ep-cfs.c ret = kstrtou8(page, 0, &val); \ val 263 drivers/pci/endpoint/pci-ep-cfs.c epf->header->_name = val; \ val 270 drivers/pci/endpoint/pci-ep-cfs.c u8 val; val 273 drivers/pci/endpoint/pci-ep-cfs.c ret = kstrtou8(page, 0, &val); val 277 drivers/pci/endpoint/pci-ep-cfs.c to_pci_epf_group(item)->epf->msi_interrupts = val; val 292 drivers/pci/endpoint/pci-ep-cfs.c u16 val; val 295 drivers/pci/endpoint/pci-ep-cfs.c ret = kstrtou16(page, 0, &val); val 299 drivers/pci/endpoint/pci-ep-cfs.c to_pci_epf_group(item)->epf->msix_interrupts = val; val 231 drivers/pci/hotplug/acpiphp_glue.c u32 val; val 324 drivers/pci/hotplug/acpiphp_glue.c &val, 60*1000)) val 177 drivers/pci/hotplug/shpchp_hpc.c static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) val 179 drivers/pci/hotplug/shpchp_hpc.c writeb(val, ctrl->creg + reg); val 187 drivers/pci/hotplug/shpchp_hpc.c static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) val 189 drivers/pci/hotplug/shpchp_hpc.c writew(val, ctrl->creg + reg); val 197 drivers/pci/hotplug/shpchp_hpc.c static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) val 199 drivers/pci/hotplug/shpchp_hpc.c writel(val, ctrl->creg + reg); val 220 drivers/pci/of.c u32 val; val 223 drivers/pci/of.c ret = of_property_read_u32(of_chosen, "linux,pci-probe-only", &val); val 230 drivers/pci/of.c if (val) val 235 drivers/pci/of.c pr_info("PROBE_ONLY %sabled\n", val ? "en" : "dis"); val 942 drivers/pci/pci-acpi.c u8 val; val 969 drivers/pci/pci-acpi.c if (fwnode_property_read_u8(fwnode, "HotPlugSupportInD3", &val)) val 972 drivers/pci/pci-acpi.c return val == 1; val 1218 drivers/pci/pci-acpi.c u8 val; val 1222 drivers/pci/pci-acpi.c if (device_property_read_u8(&dev->dev, "ExternalFacingPort", &val)) val 1230 drivers/pci/pci-acpi.c if (val) val 67 drivers/pci/pci-sysfs.c unsigned long val; val 69 drivers/pci/pci-sysfs.c if (kstrtoul(buf, 0, &val) < 0) val 72 drivers/pci/pci-sysfs.c pdev->broken_parity_status = !!val; val 283 drivers/pci/pci-sysfs.c unsigned long val; val 284 drivers/pci/pci-sysfs.c ssize_t result = kstrtoul(buf, 0, &val); val 296 drivers/pci/pci-sysfs.c else if (val) val 387 drivers/pci/pci-sysfs.c unsigned long val; val 389 drivers/pci/pci-sysfs.c if (kstrtoul(buf, 0, &val) < 0) val 401 drivers/pci/pci-sysfs.c pdev->no_msi = !val; val 403 drivers/pci/pci-sysfs.c val ? "allowed" : "disallowed"); val 407 drivers/pci/pci-sysfs.c if (val) val 413 drivers/pci/pci-sysfs.c val ? "allowed" : "disallowed"); val 420 drivers/pci/pci-sysfs.c unsigned long val; val 423 drivers/pci/pci-sysfs.c if (kstrtoul(buf, 0, &val) < 0) val 426 drivers/pci/pci-sysfs.c if (val) { val 454 drivers/pci/pci-sysfs.c unsigned long val; val 457 drivers/pci/pci-sysfs.c if (kstrtoul(buf, 0, &val) < 0) val 460 drivers/pci/pci-sysfs.c if (val) { val 473 drivers/pci/pci-sysfs.c unsigned long val; val 475 drivers/pci/pci-sysfs.c if (kstrtoul(buf, 0, &val) < 0) val 478 drivers/pci/pci-sysfs.c if (val && device_remove_file_self(dev, attr)) val 489 drivers/pci/pci-sysfs.c unsigned long val; val 492 drivers/pci/pci-sysfs.c if (kstrtoul(buf, 0, &val) < 0) val 495 drivers/pci/pci-sysfs.c if (val) { val 514 drivers/pci/pci-sysfs.c unsigned long val; val 516 drivers/pci/pci-sysfs.c if (kstrtoul(buf, 0, &val) < 0) val 519 drivers/pci/pci-sysfs.c pdev->d3cold_allowed = !!val; val 703 drivers/pci/pci-sysfs.c u8 val; val 704 drivers/pci/pci-sysfs.c pci_user_read_config_byte(dev, off, &val); val 705 drivers/pci/pci-sysfs.c data[off - init_off] = val; val 711 drivers/pci/pci-sysfs.c u16 val; val 712 drivers/pci/pci-sysfs.c pci_user_read_config_word(dev, off, &val); val 713 drivers/pci/pci-sysfs.c data[off - init_off] = val & 0xff; val 714 drivers/pci/pci-sysfs.c data[off - init_off + 1] = (val >> 8) & 0xff; val 720 drivers/pci/pci-sysfs.c u32 val; val 721 drivers/pci/pci-sysfs.c pci_user_read_config_dword(dev, off, &val); val 722 drivers/pci/pci-sysfs.c data[off - init_off] = val & 0xff; val 723 drivers/pci/pci-sysfs.c data[off - init_off + 1] = (val >> 8) & 0xff; val 724 drivers/pci/pci-sysfs.c data[off - init_off + 2] = (val >> 16) & 0xff; val 725 drivers/pci/pci-sysfs.c data[off - init_off + 3] = (val >> 24) & 0xff; val 731 drivers/pci/pci-sysfs.c u16 val; val 732 drivers/pci/pci-sysfs.c pci_user_read_config_word(dev, off, &val); val 733 drivers/pci/pci-sysfs.c data[off - init_off] = val & 0xff; val 734 drivers/pci/pci-sysfs.c data[off - init_off + 1] = (val >> 8) & 0xff; val 740 drivers/pci/pci-sysfs.c u8 val; val 741 drivers/pci/pci-sysfs.c pci_user_read_config_byte(dev, off, &val); val 742 drivers/pci/pci-sysfs.c data[off - init_off] = val; val 782 drivers/pci/pci-sysfs.c u16 val = data[off - init_off]; val 783 drivers/pci/pci-sysfs.c val |= (u16) data[off - init_off + 1] << 8; val 784 drivers/pci/pci-sysfs.c pci_user_write_config_word(dev, off, val); val 790 drivers/pci/pci-sysfs.c u32 val = data[off - init_off]; val 791 drivers/pci/pci-sysfs.c val |= (u32) data[off - init_off + 1] << 8; val 792 drivers/pci/pci-sysfs.c val |= (u32) data[off - init_off + 2] << 16; val 793 drivers/pci/pci-sysfs.c val |= (u32) data[off - init_off + 3] << 24; val 794 drivers/pci/pci-sysfs.c pci_user_write_config_dword(dev, off, val); val 800 drivers/pci/pci-sysfs.c u16 val = data[off - init_off]; val 801 drivers/pci/pci-sysfs.c val |= (u16) data[off - init_off + 1] << 8; val 802 drivers/pci/pci-sysfs.c pci_user_write_config_word(dev, off, val); val 1310 drivers/pci/pci-sysfs.c unsigned long val; val 1311 drivers/pci/pci-sysfs.c ssize_t result = kstrtoul(buf, 0, &val); val 1316 drivers/pci/pci-sysfs.c if (val != 1) val 1367 drivers/pci/pci.c u32 val; val 1369 drivers/pci/pci.c pci_read_config_dword(pdev, offset, &val); val 1370 drivers/pci/pci.c if (!force && val == saved_val) val 1375 drivers/pci/pci.c offset, val, saved_val); val 1380 drivers/pci/pci.c pci_read_config_dword(pdev, offset, &val); val 1381 drivers/pci/pci.c if (val == saved_val) val 182 drivers/pci/pcie/aer_inject.c int size, u32 *val) val 193 drivers/pci/pcie/aer_inject.c rv = ops->read(bus, devfn, where, size, val); val 200 drivers/pci/pcie/aer_inject.c int size, u32 val) val 211 drivers/pci/pcie/aer_inject.c rv = ops->write(bus, devfn, where, size, val); val 218 drivers/pci/pcie/aer_inject.c int where, int size, u32 *val) val 238 drivers/pci/pcie/aer_inject.c *val = *sim; val 243 drivers/pci/pcie/aer_inject.c rv = aer_inj_read(bus, devfn, where, size, val); val 249 drivers/pci/pcie/aer_inject.c int where, int size, u32 val) val 271 drivers/pci/pcie/aer_inject.c *sim ^= val; val 273 drivers/pci/pcie/aer_inject.c *sim = val; val 278 drivers/pci/pcie/aer_inject.c rv = aer_inj_write(bus, devfn, where, size, val); val 154 drivers/pci/pcie/aspm.c u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0; val 159 drivers/pci/pcie/aspm.c val); val 343 drivers/pci/pcie/aspm.c static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val) val 347 drivers/pci/pcie/aspm.c return val * 2; val 349 drivers/pci/pcie/aspm.c return val * 10; val 351 drivers/pci/pcie/aspm.c return val * 100; val 667 drivers/pci/pcie/aspm.c u32 val; val 669 drivers/pci/pcie/aspm.c pci_read_config_dword(pdev, pos, &val); val 670 drivers/pci/pcie/aspm.c val &= ~clear; val 671 drivers/pci/pcie/aspm.c val |= set; val 672 drivers/pci/pcie/aspm.c pci_write_config_dword(pdev, pos, val); val 678 drivers/pci/pcie/aspm.c u32 val, enable_req; val 738 drivers/pci/pcie/aspm.c val = 0; val 740 drivers/pci/pcie/aspm.c val |= PCI_L1SS_CTL1_ASPM_L1_1; val 742 drivers/pci/pcie/aspm.c val |= PCI_L1SS_CTL1_ASPM_L1_2; val 744 drivers/pci/pcie/aspm.c val |= PCI_L1SS_CTL1_PCIPM_L1_1; val 746 drivers/pci/pcie/aspm.c val |= PCI_L1SS_CTL1_PCIPM_L1_2; val 750 drivers/pci/pcie/aspm.c PCI_L1SS_CTL1_L1SS_MASK, val); val 752 drivers/pci/pcie/aspm.c PCI_L1SS_CTL1_L1SS_MASK, val); val 755 drivers/pci/pcie/aspm.c static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) val 758 drivers/pci/pcie/aspm.c PCI_EXP_LNKCTL_ASPMC, val); val 1136 drivers/pci/pcie/aspm.c static int pcie_aspm_set_policy(const char *val, val 1144 drivers/pci/pcie/aspm.c i = sysfs_match_string(policy_str, val); val 62 drivers/pci/proc.c unsigned char val; val 63 drivers/pci/proc.c pci_user_read_config_byte(dev, pos, &val); val 64 drivers/pci/proc.c __put_user(val, buf); val 71 drivers/pci/proc.c unsigned short val; val 72 drivers/pci/proc.c pci_user_read_config_word(dev, pos, &val); val 73 drivers/pci/proc.c __put_user(cpu_to_le16(val), (__le16 __user *) buf); val 80 drivers/pci/proc.c unsigned int val; val 81 drivers/pci/proc.c pci_user_read_config_dword(dev, pos, &val); val 82 drivers/pci/proc.c __put_user(cpu_to_le32(val), (__le32 __user *) buf); val 89 drivers/pci/proc.c unsigned short val; val 90 drivers/pci/proc.c pci_user_read_config_word(dev, pos, &val); val 91 drivers/pci/proc.c __put_user(cpu_to_le16(val), (__le16 __user *) buf); val 98 drivers/pci/proc.c unsigned char val; val 99 drivers/pci/proc.c pci_user_read_config_byte(dev, pos, &val); val 100 drivers/pci/proc.c __put_user(val, buf); val 139 drivers/pci/proc.c unsigned char val; val 140 drivers/pci/proc.c __get_user(val, buf); val 141 drivers/pci/proc.c pci_user_write_config_byte(dev, pos, val); val 148 drivers/pci/proc.c __le16 val; val 149 drivers/pci/proc.c __get_user(val, (__le16 __user *) buf); val 150 drivers/pci/proc.c pci_user_write_config_word(dev, pos, le16_to_cpu(val)); val 157 drivers/pci/proc.c __le32 val; val 158 drivers/pci/proc.c __get_user(val, (__le32 __user *) buf); val 159 drivers/pci/proc.c pci_user_write_config_dword(dev, pos, le32_to_cpu(val)); val 166 drivers/pci/proc.c __le16 val; val 167 drivers/pci/proc.c __get_user(val, (__le16 __user *) buf); val 168 drivers/pci/proc.c pci_user_write_config_word(dev, pos, le16_to_cpu(val)); val 175 drivers/pci/proc.c unsigned char val; val 176 drivers/pci/proc.c __get_user(val, buf); val 177 drivers/pci/proc.c pci_user_write_config_byte(dev, pos, val); val 816 drivers/pci/quirks.c u32 val; val 819 drivers/pci/quirks.c pci_read_config_dword(dev, reg, &val); val 822 drivers/pci/quirks.c if (!(val & 1)) val 824 drivers/pci/quirks.c base = val & 0xfffc; val 860 drivers/pci/quirks.c u32 val; val 863 drivers/pci/quirks.c pci_read_config_dword(dev, reg, &val); val 866 drivers/pci/quirks.c if (!(val & 1)) val 870 drivers/pci/quirks.c base = val & 0xfffc; val 871 drivers/pci/quirks.c mask = (val >> 16) & 0xfc; val 1531 drivers/pci/quirks.c u16 val; val 1536 drivers/pci/quirks.c pci_read_config_word(dev, 0xF2, &val); val 1537 drivers/pci/quirks.c if (val & 0x8) { val 1538 drivers/pci/quirks.c pci_write_config_word(dev, 0xF2, val & (~0x8)); val 1539 drivers/pci/quirks.c pci_read_config_word(dev, 0xF2, &val); val 1540 drivers/pci/quirks.c if (val & 0x8) val 1542 drivers/pci/quirks.c val); val 1581 drivers/pci/quirks.c u32 val; val 1587 drivers/pci/quirks.c val = readl(asus_rcba_base + 0x3418); val 1590 drivers/pci/quirks.c writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); val 1617 drivers/pci/quirks.c u8 val = 0; val 1618 drivers/pci/quirks.c pci_read_config_byte(dev, 0x77, &val); val 1619 drivers/pci/quirks.c if (val & 0x10) { val 1621 drivers/pci/quirks.c pci_write_config_byte(dev, 0x77, val & ~0x10); val 1675 drivers/pci/quirks.c u8 val; val 1686 drivers/pci/quirks.c pci_read_config_byte(dev, 0x50, &val); val 1687 drivers/pci/quirks.c if (val & 0xc0) { val 1688 drivers/pci/quirks.c pci_write_config_byte(dev, 0x50, val & (~0xc0)); val 1689 drivers/pci/quirks.c pci_read_config_byte(dev, 0x50, &val); val 1690 drivers/pci/quirks.c if (val & 0xc0) val 1692 drivers/pci/quirks.c val); val 3318 drivers/pci/quirks.c u8 val; val 3320 drivers/pci/quirks.c rc = pci_read_config_byte(dev, 0x00D0, &val); val 3324 drivers/pci/quirks.c dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; val 3326 drivers/pci/quirks.c rc = pci_read_config_byte(dev, 0x00D1, &val); val 3330 drivers/pci/quirks.c dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; val 3753 drivers/pci/quirks.c u32 val; val 3772 drivers/pci/quirks.c val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; val 3773 drivers/pci/quirks.c iowrite32(val, mmio_base + PCH_PP_CONTROL); val 3777 drivers/pci/quirks.c val = ioread32(mmio_base + PCH_PP_STATUS); val 3778 drivers/pci/quirks.c if ((val & 0xb0000000) == 0) val 5277 drivers/pci/quirks.c u32 val; val 5284 drivers/pci/quirks.c pci_read_config_dword(gpu, 0x488, &val); val 5285 drivers/pci/quirks.c if (val & BIT(25)) val 5289 drivers/pci/quirks.c pci_write_config_dword(gpu, 0x488, val | BIT(25)); val 210 drivers/pci/vpd.c u32 val; val 223 drivers/pci/vpd.c ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); val 230 drivers/pci/vpd.c *buf++ = val; val 234 drivers/pci/vpd.c val >>= 8; val 272 drivers/pci/vpd.c u32 val; val 274 drivers/pci/vpd.c val = *buf++; val 275 drivers/pci/vpd.c val |= *buf++ << 8; val 276 drivers/pci/vpd.c val |= *buf++ << 16; val 277 drivers/pci/vpd.c val |= *buf++ << 24; val 279 drivers/pci/vpd.c ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); val 472 drivers/pci/vpd.c u8 val = buf[i]; val 474 drivers/pci/vpd.c if (val & PCI_VPD_LRDT) { val 479 drivers/pci/vpd.c if (val == rdt) val 485 drivers/pci/vpd.c u8 tag = val & ~PCI_VPD_SRDT_LEN_MASK; val 179 drivers/pci/xen-pcifront.c int where, int size, u32 *val) val 206 drivers/pci/xen-pcifront.c *val = op.value; val 210 drivers/pci/xen-pcifront.c *val = 0; val 218 drivers/pci/xen-pcifront.c int where, int size, u32 val) val 227 drivers/pci/xen-pcifront.c .value = val, val 237 drivers/pci/xen-pcifront.c PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); val 40 drivers/pcmcia/bcm63xx_pcmcia.c u32 val, u32 off) val 42 drivers/pcmcia/bcm63xx_pcmcia.c bcm_writel(val, skt->base + off); val 80 drivers/pcmcia/bcm63xx_pcmcia.c u32 val; val 90 drivers/pcmcia/bcm63xx_pcmcia.c val = pcmcia_readl(skt, PCMCIA_C1_REG); val 92 drivers/pcmcia/bcm63xx_pcmcia.c val |= PCMCIA_C1_RESET_MASK; val 94 drivers/pcmcia/bcm63xx_pcmcia.c val &= ~PCMCIA_C1_RESET_MASK; val 98 drivers/pcmcia/bcm63xx_pcmcia.c val ^= PCMCIA_C1_RESET_MASK; val 100 drivers/pcmcia/bcm63xx_pcmcia.c pcmcia_writel(skt, val, PCMCIA_C1_REG); val 165 drivers/pcmcia/bcm63xx_pcmcia.c u32 val; val 170 drivers/pcmcia/bcm63xx_pcmcia.c val = pcmcia_readl(skt, PCMCIA_C1_REG); val 172 drivers/pcmcia/bcm63xx_pcmcia.c if (!(val & PCMCIA_C1_CD1_MASK) && !(val & PCMCIA_C1_CD2_MASK)) val 180 drivers/pcmcia/bcm63xx_pcmcia.c val |= PCMCIA_C1_VS1OE_MASK; val 181 drivers/pcmcia/bcm63xx_pcmcia.c val |= PCMCIA_C1_VS2OE_MASK; val 182 drivers/pcmcia/bcm63xx_pcmcia.c pcmcia_writel(skt, val, PCMCIA_C1_REG); val 186 drivers/pcmcia/bcm63xx_pcmcia.c val = pcmcia_readl(skt, PCMCIA_C1_REG); val 187 drivers/pcmcia/bcm63xx_pcmcia.c stat |= (val & PCMCIA_C1_VS1_MASK) ? IN_VS1 : 0; val 188 drivers/pcmcia/bcm63xx_pcmcia.c stat |= (val & PCMCIA_C1_VS2_MASK) ? IN_VS2 : 0; val 191 drivers/pcmcia/bcm63xx_pcmcia.c val &= ~PCMCIA_C1_VS1OE_MASK; val 192 drivers/pcmcia/bcm63xx_pcmcia.c val |= PCMCIA_C1_VS2OE_MASK; val 193 drivers/pcmcia/bcm63xx_pcmcia.c pcmcia_writel(skt, val, PCMCIA_C1_REG); val 197 drivers/pcmcia/bcm63xx_pcmcia.c val = pcmcia_readl(skt, PCMCIA_C1_REG); val 198 drivers/pcmcia/bcm63xx_pcmcia.c stat |= (val & PCMCIA_C1_CD1_MASK) ? IN_CD1_VS2H : 0; val 199 drivers/pcmcia/bcm63xx_pcmcia.c stat |= (val & PCMCIA_C1_CD2_MASK) ? IN_CD2_VS2H : 0; val 202 drivers/pcmcia/bcm63xx_pcmcia.c val |= PCMCIA_C1_VS1OE_MASK; val 203 drivers/pcmcia/bcm63xx_pcmcia.c val &= ~PCMCIA_C1_VS2OE_MASK; val 204 drivers/pcmcia/bcm63xx_pcmcia.c pcmcia_writel(skt, val, PCMCIA_C1_REG); val 208 drivers/pcmcia/bcm63xx_pcmcia.c val = pcmcia_readl(skt, PCMCIA_C1_REG); val 209 drivers/pcmcia/bcm63xx_pcmcia.c stat |= (val & PCMCIA_C1_CD1_MASK) ? IN_CD1_VS1H : 0; val 210 drivers/pcmcia/bcm63xx_pcmcia.c stat |= (val & PCMCIA_C1_CD2_MASK) ? IN_CD2_VS1H : 0; val 218 drivers/pcmcia/bcm63xx_pcmcia.c val &= ~(PCMCIA_C1_VS1OE_MASK | PCMCIA_C1_VS2OE_MASK); val 221 drivers/pcmcia/bcm63xx_pcmcia.c val &= ~(PCMCIA_C1_EN_PCMCIA_MASK | PCMCIA_C1_EN_CARDBUS_MASK); val 223 drivers/pcmcia/bcm63xx_pcmcia.c val |= PCMCIA_C1_EN_PCMCIA_MASK; val 225 drivers/pcmcia/bcm63xx_pcmcia.c val |= PCMCIA_C1_EN_CARDBUS_MASK; val 227 drivers/pcmcia/bcm63xx_pcmcia.c pcmcia_writel(skt, val, PCMCIA_C1_REG); val 332 drivers/pcmcia/bcm63xx_pcmcia.c u32 val; val 400 drivers/pcmcia/bcm63xx_pcmcia.c val = pcmcia_readl(skt, PCMCIA_C1_REG); val 401 drivers/pcmcia/bcm63xx_pcmcia.c val &= PCMCIA_C1_CBIDSEL_MASK; val 402 drivers/pcmcia/bcm63xx_pcmcia.c val |= PCMCIA_C1_EN_PCMCIA_GPIO_MASK; val 403 drivers/pcmcia/bcm63xx_pcmcia.c pcmcia_writel(skt, val, PCMCIA_C1_REG); val 410 drivers/pcmcia/bcm63xx_pcmcia.c val = PCMCIA_C2_DATA16_MASK; val 411 drivers/pcmcia/bcm63xx_pcmcia.c val |= 10 << PCMCIA_C2_RWCOUNT_SHIFT; val 412 drivers/pcmcia/bcm63xx_pcmcia.c val |= 6 << PCMCIA_C2_INACTIVE_SHIFT; val 413 drivers/pcmcia/bcm63xx_pcmcia.c val |= 3 << PCMCIA_C2_SETUP_SHIFT; val 414 drivers/pcmcia/bcm63xx_pcmcia.c val |= 3 << PCMCIA_C2_HOLD_SHIFT; val 415 drivers/pcmcia/bcm63xx_pcmcia.c pcmcia_writel(skt, val, PCMCIA_C2_REG); val 185 drivers/pcmcia/i82092.c unsigned char val; val 191 drivers/pcmcia/i82092.c val = inb(port+1); val 193 drivers/pcmcia/i82092.c return val; val 230 drivers/pcmcia/i82092.c unsigned char val; val 236 drivers/pcmcia/i82092.c val = inb(port+1); val 237 drivers/pcmcia/i82092.c val |= mask; val 239 drivers/pcmcia/i82092.c outb(val,port+1); val 247 drivers/pcmcia/i82092.c unsigned char val; val 253 drivers/pcmcia/i82092.c val = inb(port+1); val 254 drivers/pcmcia/i82092.c val &= ~mask; val 256 drivers/pcmcia/i82092.c outb(val,port+1); val 263 drivers/pcmcia/i82092.c unsigned char val; val 270 drivers/pcmcia/i82092.c val = value & 255; val 271 drivers/pcmcia/i82092.c outb(val,port+1); val 276 drivers/pcmcia/i82092.c val = value>>8; val 277 drivers/pcmcia/i82092.c outb(val,port+1); val 362 drivers/pcmcia/i82092.c unsigned int val; val 371 drivers/pcmcia/i82092.c val = indirect_read(socketno, 1); /* Interface status register */ val 372 drivers/pcmcia/i82092.c if ((val&12)==12) { val 223 drivers/pcmcia/i82365.c u_char val; val 225 drivers/pcmcia/i82365.c outb(reg, port); val = inb(port+1); val 227 drivers/pcmcia/i82365.c return val; val 237 drivers/pcmcia/i82365.c u_char val = I365_REG(socket[sock].psock, reg); val 238 drivers/pcmcia/i82365.c outb(val, port); outb(data, port+1); val 574 drivers/pcmcia/i82365.c u_char val; val 588 drivers/pcmcia/i82365.c if ((val = i365_get(sockets, I365_IDENT)) & 0x70) val 590 drivers/pcmcia/i82365.c switch (val) { val 605 drivers/pcmcia/i82365.c val = i365_get(sockets, I365_IDENT); val 606 drivers/pcmcia/i82365.c if (val & I365_IDENT_VADEM) { val 608 drivers/pcmcia/i82365.c type = ((val & 7) >= 4) ? IS_VG469 : IS_VG468; val 612 drivers/pcmcia/i82365.c val = i365_get(sockets, RF5C_CHIP_ID); val 613 drivers/pcmcia/i82365.c if ((val == RF5C_CHIP_RF5C296) || (val == RF5C_CHIP_RF5C396)) val 618 drivers/pcmcia/i82365.c val = i365_get(sockets, PD67_CHIP_INFO); val 619 drivers/pcmcia/i82365.c if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { val 620 drivers/pcmcia/i82365.c val = i365_get(sockets, PD67_CHIP_INFO); val 621 drivers/pcmcia/i82365.c if ((val & PD67_INFO_CHIP_ID) == 0) { val 622 drivers/pcmcia/i82365.c type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; val 156 drivers/pcmcia/pcmcia_resource.c off_t where, u8 *val, val 179 drivers/pcmcia/pcmcia_resource.c ret = accessf(s, 1, addr, 1, val); val 193 drivers/pcmcia/pcmcia_resource.c int pcmcia_read_config_byte(struct pcmcia_device *p_dev, off_t where, u8 *val) val 195 drivers/pcmcia/pcmcia_resource.c return pcmcia_access_config(p_dev, where, val, pcmcia_read_cis_mem); val 206 drivers/pcmcia/pcmcia_resource.c int pcmcia_write_config_byte(struct pcmcia_device *p_dev, off_t where, u8 val) val 208 drivers/pcmcia/pcmcia_resource.c return pcmcia_access_config(p_dev, where, &val, pcmcia_write_cis_mem); val 65 drivers/pcmcia/pd6729.c unsigned char val; val 72 drivers/pcmcia/pd6729.c val = inb(port + 1); val 75 drivers/pcmcia/pd6729.c return val; val 116 drivers/pcmcia/pd6729.c unsigned char val; val 123 drivers/pcmcia/pd6729.c val = inb(port + 1); val 124 drivers/pcmcia/pd6729.c val |= mask; val 126 drivers/pcmcia/pd6729.c outb(val, port + 1); val 134 drivers/pcmcia/pd6729.c unsigned char val; val 141 drivers/pcmcia/pd6729.c val = inb(port + 1); val 142 drivers/pcmcia/pd6729.c val &= ~mask; val 144 drivers/pcmcia/pd6729.c outb(val, port + 1); val 152 drivers/pcmcia/pd6729.c unsigned char val; val 160 drivers/pcmcia/pd6729.c val = value & 255; val 161 drivers/pcmcia/pd6729.c outb(val, port + 1); val 166 drivers/pcmcia/pd6729.c val = value >> 8; val 167 drivers/pcmcia/pd6729.c outb(val, port + 1); val 118 drivers/pcmcia/pxa2xx_base.c uint32_t val; val 120 drivers/pcmcia/pxa2xx_base.c val = ((pxa2xx_mcxx_setup(speed, clock) val 127 drivers/pcmcia/pxa2xx_base.c __raw_writel(val, MCMEM(sock)); val 134 drivers/pcmcia/pxa2xx_base.c uint32_t val; val 136 drivers/pcmcia/pxa2xx_base.c val = ((pxa2xx_mcxx_setup(speed, clock) val 143 drivers/pcmcia/pxa2xx_base.c __raw_writel(val, MCIO(sock)); val 150 drivers/pcmcia/pxa2xx_base.c uint32_t val; val 152 drivers/pcmcia/pxa2xx_base.c val = ((pxa2xx_mcxx_setup(speed, clock) val 159 drivers/pcmcia/pxa2xx_base.c __raw_writel(val, MCATT(sock)); val 188 drivers/pcmcia/pxa2xx_base.c unsigned long val, val 191 drivers/pcmcia/pxa2xx_base.c switch (val) { val 100 drivers/pcmcia/sa1111_generic.c u32 pccr_skt_mask, pccr_set_mask, val; val 128 drivers/pcmcia/sa1111_generic.c val = readl_relaxed(s->dev->mapbase + PCCR); val 129 drivers/pcmcia/sa1111_generic.c val &= ~pccr_skt_mask; val 130 drivers/pcmcia/sa1111_generic.c val |= pccr_set_mask & pccr_skt_mask; val 131 drivers/pcmcia/sa1111_generic.c writel_relaxed(val, s->dev->mapbase + PCCR); val 115 drivers/pcmcia/sa11xx_base.c unsigned long val, val 118 drivers/pcmcia/sa11xx_base.c switch (val) { val 688 drivers/pcmcia/soc_common.c unsigned int val, struct bittbl *bits, int sz) val 695 drivers/pcmcia/soc_common.c if (val & bits[i].mask) val 746 drivers/pcmcia/soc_common.c unsigned long val, void *data) val 751 drivers/pcmcia/soc_common.c return skt->ops->frequency_change(skt, val, freqs); val 126 drivers/pcmcia/tcic.c u_char val = inb(tcic_base+reg); val 127 drivers/pcmcia/tcic.c printk(KERN_DEBUG "tcic_getb(%#lx) = %#x\n", tcic_base+reg, val); val 128 drivers/pcmcia/tcic.c return val; val 133 drivers/pcmcia/tcic.c u_short val = inw(tcic_base+reg); val 134 drivers/pcmcia/tcic.c printk(KERN_DEBUG "tcic_getw(%#lx) = %#x\n", tcic_base+reg, val); val 135 drivers/pcmcia/tcic.c return val; val 844 drivers/pcmcia/ti113x.h u32 val, val_orig; val 847 drivers/pcmcia/ti113x.h val_orig = val = config_readl(socket, TI113X_SYSTEM_CONTROL); val 850 drivers/pcmcia/ti113x.h val |= TI113X_SCR_KEEPCLK; val 852 drivers/pcmcia/ti113x.h if (!(val & TI122X_SCR_MRBURSTUP)) { val 855 drivers/pcmcia/ti113x.h val |= TI122X_SCR_MRBURSTUP; val 857 drivers/pcmcia/ti113x.h if (val_orig != val) val 858 drivers/pcmcia/ti113x.h config_writel(socket, TI113X_SYSTEM_CONTROL, val); val 864 drivers/pcmcia/ti113x.h val = config_readb(socket, TI1250_DIAGNOSTIC); val 866 drivers/pcmcia/ti113x.h (val & TI1250_DIAG_PCI_CSC) ? "CSCINT" : "INTVAL"); val 868 drivers/pcmcia/ti113x.h (val & TI1250_DIAG_PCI_IREQ) ? "PCI" : "ISA"); val 245 drivers/pcmcia/vrc4171_card.c u_int val = 0; val 255 drivers/pcmcia/vrc4171_card.c val |= SS_STSCHG; val 258 drivers/pcmcia/vrc4171_card.c val |= SS_BATDEAD; val 260 drivers/pcmcia/vrc4171_card.c val |= SS_BATWARN; val 263 drivers/pcmcia/vrc4171_card.c val |= SS_DETECT; val 265 drivers/pcmcia/vrc4171_card.c val |= SS_WRPROT; val 267 drivers/pcmcia/vrc4171_card.c val |= SS_READY; val 269 drivers/pcmcia/vrc4171_card.c val |= SS_POWERON; val 274 drivers/pcmcia/vrc4171_card.c val |= SS_3VCARD | SS_XVCARD; val 277 drivers/pcmcia/vrc4171_card.c val |= SS_XVCARD; val 280 drivers/pcmcia/vrc4171_card.c val |= SS_3VCARD; val 287 drivers/pcmcia/vrc4171_card.c *value = val; val 63 drivers/pcmcia/vrc4173_cardu.c uint16_t val; val 65 drivers/pcmcia/vrc4173_cardu.c val = readb(socket->base + EXCA_REGS_BASE + offset); val 66 drivers/pcmcia/vrc4173_cardu.c val |= (u16)readb(socket->base + EXCA_REGS_BASE + offset + 1) << 8; val 68 drivers/pcmcia/vrc4173_cardu.c return val; val 71 drivers/pcmcia/vrc4173_cardu.c static inline void exca_writeb(vrc4173_socket_t *socket, uint16_t offset, uint8_t val) val 73 drivers/pcmcia/vrc4173_cardu.c writeb(val, socket->base + EXCA_REGS_BASE + offset); val 76 drivers/pcmcia/vrc4173_cardu.c static inline void exca_writew(vrc4173_socket_t *socket, uint8_t offset, uint16_t val) val 78 drivers/pcmcia/vrc4173_cardu.c writeb((u8)val, socket->base + EXCA_REGS_BASE + offset); val 79 drivers/pcmcia/vrc4173_cardu.c writeb((u8)(val >> 8), socket->base + EXCA_REGS_BASE + offset + 1); val 87 drivers/pcmcia/vrc4173_cardu.c static inline void cardbus_socket_writel(vrc4173_socket_t *socket, u16 offset, uint32_t val) val 89 drivers/pcmcia/vrc4173_cardu.c writel(val, socket->base + CARDBUS_SOCKET_REGS_BASE + offset); val 170 drivers/pcmcia/vrc4173_cardu.c u_int val = 0; val 173 drivers/pcmcia/vrc4173_cardu.c if (status & CARD_PWR) val |= SS_POWERON; val 174 drivers/pcmcia/vrc4173_cardu.c if (status & READY) val |= SS_READY; val 175 drivers/pcmcia/vrc4173_cardu.c if (status & CARD_WP) val |= SS_WRPROT; val 177 drivers/pcmcia/vrc4173_cardu.c val |= SS_DETECT; val 179 drivers/pcmcia/vrc4173_cardu.c if (status & STSCHG) val |= SS_STSCHG; val 183 drivers/pcmcia/vrc4173_cardu.c if (status == BV_DETECT_WARN) val |= SS_BATWARN; val 184 drivers/pcmcia/vrc4173_cardu.c else val |= SS_BATDEAD; val 189 drivers/pcmcia/vrc4173_cardu.c if (state & VOL_3V_CARD_DT) val |= SS_3VCARD; val 190 drivers/pcmcia/vrc4173_cardu.c if (state & VOL_XV_CARD_DT) val |= SS_XVCARD; val 191 drivers/pcmcia/vrc4173_cardu.c if (state & CB_CARD_DT) val |= SS_CARDBUS; val 194 drivers/pcmcia/vrc4173_cardu.c val |= SS_PENDING; val 196 drivers/pcmcia/vrc4173_cardu.c *value = val; val 229 drivers/pcmcia/vrc4173_cardu.c uint8_t val; val 234 drivers/pcmcia/vrc4173_cardu.c val = set_Vcc_value(state->Vcc); val 235 drivers/pcmcia/vrc4173_cardu.c val |= set_Vpp_value(state->Vpp); val 236 drivers/pcmcia/vrc4173_cardu.c if (state->flags & SS_OUTPUT_ENA) val |= CARD_OUT_EN; val 237 drivers/pcmcia/vrc4173_cardu.c exca_writeb(socket, PWR_CNT, val); val 239 drivers/pcmcia/vrc4173_cardu.c val = exca_readb(socket, INT_GEN_CNT) & CARD_REST0; val 240 drivers/pcmcia/vrc4173_cardu.c if (state->flags & SS_RESET) val &= ~CARD_REST0; val 241 drivers/pcmcia/vrc4173_cardu.c else val |= CARD_REST0; val 242 drivers/pcmcia/vrc4173_cardu.c if (state->flags & SS_IOCARD) val |= CARD_TYPE_IO; val 243 drivers/pcmcia/vrc4173_cardu.c exca_writeb(socket, INT_GEN_CNT, val); val 86 drivers/pcmcia/yenta_socket.c u32 val = readl(socket->base + reg); val 87 drivers/pcmcia/yenta_socket.c debug("%04x %08x\n", socket, reg, val); val 88 drivers/pcmcia/yenta_socket.c return val; val 91 drivers/pcmcia/yenta_socket.c static inline void cb_writel(struct yenta_socket *socket, unsigned reg, u32 val) val 93 drivers/pcmcia/yenta_socket.c debug("%04x %08x\n", socket, reg, val); val 94 drivers/pcmcia/yenta_socket.c writel(val, socket->base + reg); val 100 drivers/pcmcia/yenta_socket.c u8 val; val 101 drivers/pcmcia/yenta_socket.c pci_read_config_byte(socket->dev, offset, &val); val 102 drivers/pcmcia/yenta_socket.c debug("%04x %02x\n", socket, offset, val); val 103 drivers/pcmcia/yenta_socket.c return val; val 108 drivers/pcmcia/yenta_socket.c u16 val; val 109 drivers/pcmcia/yenta_socket.c pci_read_config_word(socket->dev, offset, &val); val 110 drivers/pcmcia/yenta_socket.c debug("%04x %04x\n", socket, offset, val); val 111 drivers/pcmcia/yenta_socket.c return val; val 116 drivers/pcmcia/yenta_socket.c u32 val; val 117 drivers/pcmcia/yenta_socket.c pci_read_config_dword(socket->dev, offset, &val); val 118 drivers/pcmcia/yenta_socket.c debug("%04x %08x\n", socket, offset, val); val 119 drivers/pcmcia/yenta_socket.c return val; val 122 drivers/pcmcia/yenta_socket.c static inline void config_writeb(struct yenta_socket *socket, unsigned offset, u8 val) val 124 drivers/pcmcia/yenta_socket.c debug("%04x %02x\n", socket, offset, val); val 125 drivers/pcmcia/yenta_socket.c pci_write_config_byte(socket->dev, offset, val); val 128 drivers/pcmcia/yenta_socket.c static inline void config_writew(struct yenta_socket *socket, unsigned offset, u16 val) val 130 drivers/pcmcia/yenta_socket.c debug("%04x %04x\n", socket, offset, val); val 131 drivers/pcmcia/yenta_socket.c pci_write_config_word(socket->dev, offset, val); val 134 drivers/pcmcia/yenta_socket.c static inline void config_writel(struct yenta_socket *socket, unsigned offset, u32 val) val 136 drivers/pcmcia/yenta_socket.c debug("%04x %08x\n", socket, offset, val); val 137 drivers/pcmcia/yenta_socket.c pci_write_config_dword(socket->dev, offset, val); val 142 drivers/pcmcia/yenta_socket.c u8 val = readb(socket->base + 0x800 + reg); val 143 drivers/pcmcia/yenta_socket.c debug("%04x %02x\n", socket, reg, val); val 144 drivers/pcmcia/yenta_socket.c return val; val 149 drivers/pcmcia/yenta_socket.c u16 val; val 150 drivers/pcmcia/yenta_socket.c val = readb(socket->base + 0x800 + reg); val 151 drivers/pcmcia/yenta_socket.c val |= readb(socket->base + 0x800 + reg + 1) << 8; val 152 drivers/pcmcia/yenta_socket.c debug("%04x %04x\n", socket, reg, val); val 153 drivers/pcmcia/yenta_socket.c return val; val 156 drivers/pcmcia/yenta_socket.c static inline void exca_writeb(struct yenta_socket *socket, unsigned reg, u8 val) val 158 drivers/pcmcia/yenta_socket.c debug("%04x %02x\n", socket, reg, val); val 159 drivers/pcmcia/yenta_socket.c writeb(val, socket->base + 0x800 + reg); val 163 drivers/pcmcia/yenta_socket.c static void exca_writew(struct yenta_socket *socket, unsigned reg, u16 val) val 165 drivers/pcmcia/yenta_socket.c debug("%04x %04x\n", socket, reg, val); val 166 drivers/pcmcia/yenta_socket.c writeb(val, socket->base + 0x800 + reg); val 167 drivers/pcmcia/yenta_socket.c writeb(val >> 8, socket->base + 0x800 + reg + 1); val 182 drivers/pcmcia/yenta_socket.c unsigned val; val 185 drivers/pcmcia/yenta_socket.c val = cb_readl(socket, i); val 186 drivers/pcmcia/yenta_socket.c offset += snprintf(buf + offset, PAGE_SIZE - offset, " %08x", val); val 191 drivers/pcmcia/yenta_socket.c unsigned char val; val 199 drivers/pcmcia/yenta_socket.c val = exca_readb(socket, i); val 200 drivers/pcmcia/yenta_socket.c offset += snprintf(buf + offset, PAGE_SIZE - offset, " %02x", val); val 215 drivers/pcmcia/yenta_socket.c unsigned int val; val 218 drivers/pcmcia/yenta_socket.c val = (state & CB_3VCARD) ? SS_3VCARD : 0; val 219 drivers/pcmcia/yenta_socket.c val |= (state & CB_XVCARD) ? SS_XVCARD : 0; val 220 drivers/pcmcia/yenta_socket.c val |= (state & (CB_5VCARD | CB_3VCARD | CB_XVCARD | CB_YVCARD)) ? 0 : SS_PENDING; val 221 drivers/pcmcia/yenta_socket.c val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? SS_PENDING : 0; val 225 drivers/pcmcia/yenta_socket.c val |= SS_CARDBUS; val 226 drivers/pcmcia/yenta_socket.c val |= (state & CB_CARDSTS) ? SS_STSCHG : 0; val 227 drivers/pcmcia/yenta_socket.c val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? 0 : SS_DETECT; val 228 drivers/pcmcia/yenta_socket.c val |= (state & CB_PWRCYCLE) ? SS_POWERON | SS_READY : 0; val 231 drivers/pcmcia/yenta_socket.c val |= ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; val 233 drivers/pcmcia/yenta_socket.c val |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; val 235 drivers/pcmcia/yenta_socket.c val |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; val 236 drivers/pcmcia/yenta_socket.c val |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; val 238 drivers/pcmcia/yenta_socket.c val |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; val 239 drivers/pcmcia/yenta_socket.c val |= (status & I365_CS_READY) ? SS_READY : 0; val 240 drivers/pcmcia/yenta_socket.c val |= (status & I365_CS_POWERON) ? SS_POWERON : 0; val 243 drivers/pcmcia/yenta_socket.c *value = val; val 916 drivers/pcmcia/yenta_socket.c unsigned long val; val 928 drivers/pcmcia/yenta_socket.c val = probe_irq_on() & isa_irq_mask; val 930 drivers/pcmcia/yenta_socket.c if (!((val >> i) & 1)) val 940 drivers/pcmcia/yenta_socket.c mask = probe_irq_mask(val) & 0xffff; val 670 drivers/perf/arm-cci.c u32 val; val 673 drivers/perf/arm-cci.c val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) | CCI_PMCR_CEN; val 674 drivers/perf/arm-cci.c writel(val, cci_pmu->ctrl_base + CCI_PMCR); val 687 drivers/perf/arm-cci.c u32 val; val 690 drivers/perf/arm-cci.c val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN; val 691 drivers/perf/arm-cci.c writel(val, cci_pmu->ctrl_base + CCI_PMCR); val 1015 drivers/perf/arm-cci.c u64 val = 1ULL << 31; val 1016 drivers/perf/arm-cci.c local64_set(&hwc->prev_count, val); val 894 drivers/perf/arm-ccn.c u32 val, dt_cfg; val 913 drivers/perf/arm-ccn.c val = readl(xp->base + CCN_XP_DT_CONFIG); val 914 drivers/perf/arm-ccn.c val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK << val 916 drivers/perf/arm-ccn.c val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx); val 917 drivers/perf/arm-ccn.c writel(val, xp->base + CCN_XP_DT_CONFIG); val 955 drivers/perf/arm-ccn.c u32 val; val 964 drivers/perf/arm-ccn.c val = readl(source->base + CCN_XP_DT_INTERFACE_SEL); val 965 drivers/perf/arm-ccn.c val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK << val 967 drivers/perf/arm-ccn.c val |= CCN_CONFIG_DIR(event->attr.config) << val 969 drivers/perf/arm-ccn.c val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK << val 971 drivers/perf/arm-ccn.c val |= CCN_CONFIG_PORT(event->attr.config) << val 973 drivers/perf/arm-ccn.c val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK << val 975 drivers/perf/arm-ccn.c val |= CCN_CONFIG_VC(event->attr.config) << val 977 drivers/perf/arm-ccn.c writel(val, source->base + CCN_XP_DT_INTERFACE_SEL); val 1002 drivers/perf/arm-ccn.c u32 val, id; val 1010 drivers/perf/arm-ccn.c val = readl(source->base + CCN_XP_PMU_EVENT_SEL); val 1011 drivers/perf/arm-ccn.c val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK << val 1013 drivers/perf/arm-ccn.c val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); val 1014 drivers/perf/arm-ccn.c writel(val, source->base + CCN_XP_PMU_EVENT_SEL); val 1024 drivers/perf/arm-ccn.c u32 val, port; val 1046 drivers/perf/arm-ccn.c val = readl(source->base + CCN_HNF_PMU_EVENT_SEL); val 1047 drivers/perf/arm-ccn.c val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK << val 1049 drivers/perf/arm-ccn.c val |= CCN_CONFIG_EVENT(event->attr.config) << val 1051 drivers/perf/arm-ccn.c writel(val, source->base + CCN_HNF_PMU_EVENT_SEL); val 1058 drivers/perf/arm-ccn.c u32 xp, offset, val; val 1073 drivers/perf/arm-ccn.c val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); val 1074 drivers/perf/arm-ccn.c val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK << val 1076 drivers/perf/arm-ccn.c val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4); val 1077 drivers/perf/arm-ccn.c writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); val 1148 drivers/perf/arm-ccn.c u32 val = readl(ccn->dt.base + CCN_DT_PMCR); val 1149 drivers/perf/arm-ccn.c val |= CCN_DT_PMCR__PMU_EN; val 1150 drivers/perf/arm-ccn.c writel(val, ccn->dt.base + CCN_DT_PMCR); val 1157 drivers/perf/arm-ccn.c u32 val = readl(ccn->dt.base + CCN_DT_PMCR); val 1158 drivers/perf/arm-ccn.c val &= ~CCN_DT_PMCR__PMU_EN; val 1159 drivers/perf/arm-ccn.c writel(val, ccn->dt.base + CCN_DT_PMCR); val 1349 drivers/perf/arm-ccn.c u32 val, type, id; val 1353 drivers/perf/arm-ccn.c val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 + val 1355 drivers/perf/arm-ccn.c if (!(val & (1 << (region % 32)))) val 1359 drivers/perf/arm-ccn.c val = readl(base + CCN_ALL_OLY_ID); val 1360 drivers/perf/arm-ccn.c type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) & val 1362 drivers/perf/arm-ccn.c id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) & val 250 drivers/perf/arm_dsu_pmu.c u64 val; val 267 drivers/perf/arm_dsu_pmu.c val = __dsu_pmu_read_pmccntr(); val 269 drivers/perf/arm_dsu_pmu.c val = __dsu_pmu_read_counter(idx); val 272 drivers/perf/arm_dsu_pmu.c return val; val 275 drivers/perf/arm_dsu_pmu.c static void dsu_pmu_write_counter(struct perf_event *event, u64 val) val 293 drivers/perf/arm_dsu_pmu.c __dsu_pmu_write_pmccntr(val); val 295 drivers/perf/arm_dsu_pmu.c __dsu_pmu_write_counter(idx, val); val 384 drivers/perf/arm_dsu_pmu.c u64 val = DSU_PMU_COUNTER_MASK(idx) >> 1; val 386 drivers/perf/arm_dsu_pmu.c local64_set(&event->hw.prev_count, val); val 387 drivers/perf/arm_dsu_pmu.c dsu_pmu_write_counter(event, val); val 192 drivers/perf/arm_smmuv3_pmu.c u32 val) val 194 drivers/perf/arm_smmuv3_pmu.c writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx)); val 197 drivers/perf/arm_smmuv3_pmu.c static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val) val 199 drivers/perf/arm_smmuv3_pmu.c writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx)); val 326 drivers/perf/fsl_imx8_ddr_perf.c int val; val 336 drivers/perf/fsl_imx8_ddr_perf.c val = CNTL_EN | CNTL_CLEAR; val 337 drivers/perf/fsl_imx8_ddr_perf.c val |= FIELD_PREP(CNTL_CSV_MASK, config); val 338 drivers/perf/fsl_imx8_ddr_perf.c writel(val, pmu->base + reg); val 341 drivers/perf/fsl_imx8_ddr_perf.c val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; val 342 drivers/perf/fsl_imx8_ddr_perf.c writel(val, pmu->base + reg); val 79 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c struct hw_perf_event *hwc, u64 val) val 88 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel((u32)val, val 103 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c u32 val; val 106 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_PERF_CTRL); val 107 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val |= DDRC_PERF_CTRL_EN; val 108 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_PERF_CTRL); val 113 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c u32 val; val 116 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_PERF_CTRL); val 117 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val &= ~DDRC_PERF_CTRL_EN; val 118 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_PERF_CTRL); val 124 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c u32 val; val 127 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL); val 128 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val |= (1 << GET_DDRC_EVENTID(hwc)); val 129 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL); val 135 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c u32 val; val 138 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL); val 139 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val &= ~(1 << GET_DDRC_EVENTID(hwc)); val 140 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL); val 162 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c u32 val; val 165 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_INT_MASK); val 166 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val &= ~(1 << GET_DDRC_EVENTID(hwc)); val 167 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_INT_MASK); val 173 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c u32 val; val 176 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_INT_MASK); val 177 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val |= (1 << GET_DDRC_EVENTID(hwc)); val 178 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_INT_MASK); val 65 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c struct hw_perf_event *hwc, u64 val) val 75 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writeq(val, hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx)); val 81 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c u32 reg, reg_idx, shift, val; val 95 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + reg); val 96 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val &= ~(HHA_EVTYPE_NONE << shift); val 97 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val |= (type << shift); val 98 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + reg); val 103 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c u32 val; val 109 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_PERF_CTRL); val 110 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val |= HHA_PERF_CTRL_EN; val 111 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_PERF_CTRL); val 116 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c u32 val; val 122 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_PERF_CTRL); val 123 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val &= ~(HHA_PERF_CTRL_EN); val 124 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_PERF_CTRL); val 130 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c u32 val; val 133 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_EVENT_CTRL); val 134 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val |= (1 << hwc->idx); val 135 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_EVENT_CTRL); val 141 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c u32 val; val 144 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_EVENT_CTRL); val 145 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val &= ~(1 << hwc->idx); val 146 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_EVENT_CTRL); val 152 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c u32 val; val 155 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_INT_MASK); val 156 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val &= ~(1 << hwc->idx); val 157 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_INT_MASK); val 163 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c u32 val; val 166 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_INT_MASK); val 167 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val |= (1 << hwc->idx); val 168 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_INT_MASK); val 64 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c struct hw_perf_event *hwc, u64 val) val 74 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writeq(val, l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx)); val 80 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c u32 reg, reg_idx, shift, val; val 94 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + reg); val 95 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val &= ~(L3C_EVTYPE_NONE << shift); val 96 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val |= (type << shift); val 97 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + reg); val 102 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c u32 val; val 108 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_PERF_CTRL); val 109 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val |= L3C_PERF_CTRL_EN; val 110 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_PERF_CTRL); val 115 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c u32 val; val 121 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_PERF_CTRL); val 122 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val &= ~(L3C_PERF_CTRL_EN); val 123 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_PERF_CTRL); val 129 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c u32 val; val 132 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_EVENT_CTRL); val 133 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val |= (1 << hwc->idx); val 134 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_EVENT_CTRL); val 140 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c u32 val; val 143 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_EVENT_CTRL); val 144 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val &= ~(1 << hwc->idx); val 145 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_EVENT_CTRL); val 151 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c u32 val; val 153 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_INT_MASK); val 155 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val &= ~(1 << hwc->idx); val 156 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_INT_MASK); val 162 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c u32 val; val 164 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_INT_MASK); val 166 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val |= (1 << hwc->idx); val 167 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_INT_MASK); val 216 drivers/perf/hisilicon/hisi_uncore_pmu.c u64 val = BIT_ULL(hisi_pmu->counter_bits - 1); val 218 drivers/perf/hisilicon/hisi_uncore_pmu.c local64_set(&hwc->prev_count, val); val 220 drivers/perf/hisilicon/hisi_uncore_pmu.c hisi_pmu->ops->write_counter(hisi_pmu, hwc, val); val 112 drivers/perf/qcom_l2_pmu.c static void set_l2_indirect_reg(u64 reg, u64 val) val 119 drivers/perf/qcom_l2_pmu.c write_sysreg_s(val, L2CPUSRDR_EL1); val 133 drivers/perf/qcom_l2_pmu.c u64 val; val 139 drivers/perf/qcom_l2_pmu.c val = read_sysreg_s(L2CPUSRDR_EL1); val 142 drivers/perf/qcom_l2_pmu.c return val; val 270 drivers/perf/qcom_l2_pmu.c static inline void cluster_pmu_set_evccntcr(u32 val) val 272 drivers/perf/qcom_l2_pmu.c set_l2_indirect_reg(L2PMCCNTCR, val); val 275 drivers/perf/qcom_l2_pmu.c static inline void cluster_pmu_set_evcntcr(u32 ctr, u32 val) val 277 drivers/perf/qcom_l2_pmu.c set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val); val 280 drivers/perf/qcom_l2_pmu.c static inline void cluster_pmu_set_evtyper(u32 ctr, u32 val) val 282 drivers/perf/qcom_l2_pmu.c set_l2_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val); val 314 drivers/perf/qcom_l2_pmu.c u32 val = L2PMXEVFILTER_SUFILTER_ALL | val 318 drivers/perf/qcom_l2_pmu.c set_l2_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val); val 768 drivers/perf/qcom_l2_pmu.c int val; val 770 drivers/perf/qcom_l2_pmu.c val = get_l2_indirect_reg(L2PMCR); val 776 drivers/perf/qcom_l2_pmu.c return ((val >> L2PMCR_NUM_EV_SHIFT) & L2PMCR_NUM_EV_MASK) + 1; val 29 drivers/perf/thunderx2_pmu.c #define DMC_EVENT_CFG(idx, val) ((val) << (((idx) * 8) + 1)) val 221 drivers/perf/thunderx2_pmu.c static inline void reg_writel(u32 val, unsigned long addr) val 223 drivers/perf/thunderx2_pmu.c writel(val, (void __iomem *)addr); val 270 drivers/perf/thunderx2_pmu.c u32 val; val 274 drivers/perf/thunderx2_pmu.c val = GET_EVENTID(event) << 3; val 275 drivers/perf/thunderx2_pmu.c reg_writel(val, hwc->config_base); val 287 drivers/perf/thunderx2_pmu.c u32 val; val 295 drivers/perf/thunderx2_pmu.c val = reg_readl(hwc->config_base); val 296 drivers/perf/thunderx2_pmu.c val &= ~DMC_EVENT_CFG(idx, 0x1f); val 297 drivers/perf/thunderx2_pmu.c val |= DMC_EVENT_CFG(idx, event_id); val 298 drivers/perf/thunderx2_pmu.c reg_writel(val, hwc->config_base); val 305 drivers/perf/thunderx2_pmu.c u32 val; val 310 drivers/perf/thunderx2_pmu.c val = reg_readl(hwc->config_base); val 311 drivers/perf/thunderx2_pmu.c val &= ~DMC_EVENT_CFG(idx, 0x1f); val 312 drivers/perf/thunderx2_pmu.c reg_writel(val, hwc->config_base); val 107 drivers/perf/xgene_pmu.c void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val); val 108 drivers/perf/xgene_pmu.c void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val); val 109 drivers/perf/xgene_pmu.c void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val); val 110 drivers/perf/xgene_pmu.c void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val); val 760 drivers/perf/xgene_pmu.c xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) val 762 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); val 766 drivers/perf/xgene_pmu.c xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) val 770 drivers/perf/xgene_pmu.c cnt_hi = upper_32_bits(val); val 771 drivers/perf/xgene_pmu.c cnt_lo = lower_32_bits(val); val 779 drivers/perf/xgene_pmu.c xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val) val 781 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx)); val 785 drivers/perf/xgene_pmu.c xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) val 787 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMAMR0); val 791 drivers/perf/xgene_pmu.c xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { } val 794 drivers/perf/xgene_pmu.c xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) val 796 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMAMR1); val 800 drivers/perf/xgene_pmu.c xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { } val 805 drivers/perf/xgene_pmu.c u32 val; val 807 drivers/perf/xgene_pmu.c val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET); val 808 drivers/perf/xgene_pmu.c val |= 1 << idx; val 809 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET); val 815 drivers/perf/xgene_pmu.c u32 val; val 817 drivers/perf/xgene_pmu.c val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR); val 818 drivers/perf/xgene_pmu.c val |= 1 << idx; val 819 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR); val 825 drivers/perf/xgene_pmu.c u32 val; val 827 drivers/perf/xgene_pmu.c val = readl(pmu_dev->inf->csr + PMU_PMINTENSET); val 828 drivers/perf/xgene_pmu.c val |= 1 << idx; val 829 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMINTENSET); val 835 drivers/perf/xgene_pmu.c u32 val; val 837 drivers/perf/xgene_pmu.c val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR); val 838 drivers/perf/xgene_pmu.c val |= 1 << idx; val 839 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR); val 844 drivers/perf/xgene_pmu.c u32 val; val 846 drivers/perf/xgene_pmu.c val = readl(pmu_dev->inf->csr + PMU_PMCR); val 847 drivers/perf/xgene_pmu.c val |= PMU_PMCR_P; val 848 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMCR); val 853 drivers/perf/xgene_pmu.c u32 val; val 855 drivers/perf/xgene_pmu.c val = readl(pmu_dev->inf->csr + PMU_PMCR); val 856 drivers/perf/xgene_pmu.c val |= PMU_PMCR_E; val 857 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMCR); val 862 drivers/perf/xgene_pmu.c u32 val; val 864 drivers/perf/xgene_pmu.c val = readl(pmu_dev->inf->csr + PMU_PMCR); val 865 drivers/perf/xgene_pmu.c val &= ~PMU_PMCR_E; val 866 drivers/perf/xgene_pmu.c writel(val, pmu_dev->inf->csr + PMU_PMCR); val 984 drivers/perf/xgene_pmu.c u64 val = 1ULL << 31; val 986 drivers/perf/xgene_pmu.c local64_set(&hw->prev_count, val); val 987 drivers/perf/xgene_pmu.c xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val); val 1238 drivers/perf/xgene_pmu.c u32 val; val 1243 drivers/perf/xgene_pmu.c val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG); val 1255 drivers/perf/xgene_pmu.c if (val & intr_mcu) { val 1260 drivers/perf/xgene_pmu.c if (val & intr_mcb) { val 1265 drivers/perf/xgene_pmu.c if (val & intr_l3c) { val 1270 drivers/perf/xgene_pmu.c if (val & intr_iob) { val 170 drivers/phy/allwinner/phy-sun4i-usb.c static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val) val 172 drivers/phy/allwinner/phy-sun4i-usb.c if (val) val 173 drivers/phy/allwinner/phy-sun4i-usb.c val = ISCR_FORCE_ID_HIGH; val 175 drivers/phy/allwinner/phy-sun4i-usb.c val = ISCR_FORCE_ID_LOW; val 177 drivers/phy/allwinner/phy-sun4i-usb.c sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_ID_MASK, val); val 180 drivers/phy/allwinner/phy-sun4i-usb.c static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val) val 182 drivers/phy/allwinner/phy-sun4i-usb.c if (val) val 183 drivers/phy/allwinner/phy-sun4i-usb.c val = ISCR_FORCE_VBUS_HIGH; val 185 drivers/phy/allwinner/phy-sun4i-usb.c val = ISCR_FORCE_VBUS_LOW; val 187 drivers/phy/allwinner/phy-sun4i-usb.c sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_VBUS_MASK, val); val 271 drivers/phy/allwinner/phy-sun4i-usb.c u32 val; val 293 drivers/phy/allwinner/phy-sun4i-usb.c val = readl(data->base + data->cfg->phyctl_offset); val 294 drivers/phy/allwinner/phy-sun4i-usb.c val |= PHY_CTL_VBUSVLDEXT; val 295 drivers/phy/allwinner/phy-sun4i-usb.c val &= ~PHY_CTL_SIDDQ; val 296 drivers/phy/allwinner/phy-sun4i-usb.c writel(val, data->base + data->cfg->phyctl_offset); val 300 drivers/phy/allwinner/phy-sun4i-usb.c val = readl(phy->pmu + REG_PMU_UNK1); val 301 drivers/phy/allwinner/phy-sun4i-usb.c writel(val & ~2, phy->pmu + REG_PMU_UNK1); val 384 drivers/phy/allwinner/phy-sun4i-usb.c union power_supply_propval val; val 388 drivers/phy/allwinner/phy-sun4i-usb.c POWER_SUPPLY_PROP_PRESENT, &val); val 390 drivers/phy/allwinner/phy-sun4i-usb.c return val.intval; val 631 drivers/phy/allwinner/phy-sun4i-usb.c unsigned long val, void *v) val 638 drivers/phy/allwinner/phy-sun4i-usb.c if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply) val 72 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c unsigned int val, reg; val 82 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, val 83 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c (val & PHY_R5_PHY_CR_ACK), val 90 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, val 91 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c !(val & PHY_R5_PHY_CR_ACK), val 103 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c unsigned int val; val 113 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, val 114 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c (val & PHY_R5_PHY_CR_ACK), val 119 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val); val 123 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, val 124 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c !(val & PHY_R5_PHY_CR_ACK), val 136 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c unsigned int val, reg; val 150 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, val 151 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c (val & PHY_R5_PHY_CR_ACK), val 158 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, val 159 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c (val & PHY_R5_PHY_CR_ACK) == 0, val 168 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, val 169 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c (val & PHY_R5_PHY_CR_ACK), val 176 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, val 177 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c (val & PHY_R5_PHY_CR_ACK) == 0, val 63 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c u32 val; val 83 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c val = readl(core->base + PCIE_CFG_OFFSET); val 84 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c val &= ~BIT(shift); val 85 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c writel(val, core->base + PCIE_CFG_OFFSET); val 92 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c val = readl(core->base + PCIE_CFG_OFFSET); val 93 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c val |= BIT(shift); val 94 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c writel(val, core->base + PCIE_CFG_OFFSET); val 36 drivers/phy/broadcom/phy-bcm-kona-usb2.c u32 val; val 38 drivers/phy/broadcom/phy-bcm-kona-usb2.c val = readl(phy->regs + OTGCTL); val 41 drivers/phy/broadcom/phy-bcm-kona-usb2.c val &= ~(OTGCTL_OTGSTAT2 | OTGCTL_OTGSTAT1 | val 43 drivers/phy/broadcom/phy-bcm-kona-usb2.c val |= OTGCTL_PRST_N_SW | OTGCTL_HRESET_N; val 45 drivers/phy/broadcom/phy-bcm-kona-usb2.c val &= ~(OTGCTL_PRST_N_SW | OTGCTL_HRESET_N); val 47 drivers/phy/broadcom/phy-bcm-kona-usb2.c writel(val, phy->regs + OTGCTL); val 53 drivers/phy/broadcom/phy-bcm-kona-usb2.c u32 val; val 56 drivers/phy/broadcom/phy-bcm-kona-usb2.c val = readl(phy->regs + P1CTL); val 57 drivers/phy/broadcom/phy-bcm-kona-usb2.c val &= ~P1CTL_NON_DRIVING; val 58 drivers/phy/broadcom/phy-bcm-kona-usb2.c val |= P1CTL_SOFT_RESET; val 59 drivers/phy/broadcom/phy-bcm-kona-usb2.c writel(val, phy->regs + P1CTL); val 60 drivers/phy/broadcom/phy-bcm-kona-usb2.c writel(val & ~P1CTL_SOFT_RESET, phy->regs + P1CTL); val 63 drivers/phy/broadcom/phy-bcm-kona-usb2.c writel(val | P1CTL_SOFT_RESET, phy->regs + P1CTL); val 264 drivers/phy/broadcom/phy-bcm-ns-usb3.c u32 val; val 267 drivers/phy/broadcom/phy-bcm-ns-usb3.c val = readl(addr); val 268 drivers/phy/broadcom/phy-bcm-ns-usb3.c if ((val & mask) == value) val 91 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c u32 val; val 95 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->icfgdrd_regs + usb_reg); val 96 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c if (val & reg_mask) val 107 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c u32 val; val 109 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->icfgdrd_regs + ICFG_FSM_CTRL); val 112 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~DRD_DEVICE_MODE; val 113 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val |= DRD_HOST_MODE; val 115 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~DRD_HOST_MODE; val 116 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val |= DRD_DEVICE_MODE; val 118 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL); val 127 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c u32 val; val 129 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->crmu_usb2_ctrl); val 130 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~AFE_CORERDY_VDDC; val 131 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->crmu_usb2_ctrl); val 133 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->crmu_usb2_ctrl); val 134 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~DRD_DEV_MODE; val 135 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->crmu_usb2_ctrl); val 138 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->icfgdrd_regs + ICFG_FSM_CTRL); val 139 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~(DRD_HOST_MODE | DRD_DEVICE_MODE | ICFG_OFF_MODE); val 140 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL); val 151 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c u32 val; val 156 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->idmdrd_rst_ctrl); val 157 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~IDM_RST_BIT; val 158 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->idmdrd_rst_ctrl); val 160 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->crmu_usb2_ctrl); val 161 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val |= (AFE_CORERDY_VDDC | DRD_DEV_MODE); val 162 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->crmu_usb2_ctrl); val 165 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->crmu_usb2_ctrl); val 166 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val |= (PHY_PLL_RESETB | PHY_RESETB); val 167 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->crmu_usb2_ctrl); val 177 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->crmu_usb2_ctrl); val 178 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val |= AFE_CORERDY_VDDC; val 179 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->crmu_usb2_ctrl); val 187 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->idmdrd_rst_ctrl); val 188 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~IDM_RST_BIT; val 189 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->idmdrd_rst_ctrl); val 192 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->usb2h_strap_reg); val 193 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val |= OHCI_OVRCUR_POL; val 194 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->usb2h_strap_reg); val 203 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c u32 val; val 206 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->icfgdrd_regs + ICFG_FSM_CTRL); val 210 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~(DRD_HOST_MODE | DRD_DEVICE_MODE); val 211 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL); val 213 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = (val & ~DRD_HOST_MODE) | DRD_DEVICE_MODE; val 214 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL); val 216 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->icfgdrd_regs + ICFG_DRD_P0CTL); val 217 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val |= ICFG_DEV_BIT; val 218 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->icfgdrd_regs + ICFG_DRD_P0CTL); val 222 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~(DRD_HOST_MODE | DRD_DEVICE_MODE); val 223 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL); val 225 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = (val & ~DRD_DEVICE_MODE) | DRD_HOST_MODE; val 226 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL); val 228 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->usb2h_strap_reg); val 229 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val |= OHCI_OVRCUR_POL; val 230 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->usb2h_strap_reg); val 232 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->icfgdrd_regs + ICFG_DRD_P0CTL); val 233 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~ICFG_DEV_BIT; val 234 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->icfgdrd_regs + ICFG_DRD_P0CTL); val 303 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c u32 val; val 396 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val = readl(driver->crmu_usb2_ctrl); val 397 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c val &= ~(AFE_CORERDY_VDDC | PHY_RESETB); val 398 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c writel(val, driver->crmu_usb2_ctrl); val 173 drivers/phy/broadcom/phy-bcm-sr-pcie.c u32 val; val 178 drivers/phy/broadcom/phy-bcm-sr-pcie.c regmap_read(core->mhb, MHB_MEM_PW_PAXC_OFFSET, &val); val 179 drivers/phy/broadcom/phy-bcm-sr-pcie.c if ((val & MHB_PWR_STATUS_MASK) != MHB_PWR_STATUS_MASK) { val 298 drivers/phy/broadcom/phy-brcm-sata.c unsigned int val; val 304 drivers/phy/broadcom/phy-brcm-sata.c val = 0x0; val 305 drivers/phy/broadcom/phy-brcm-sata.c val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT); val 306 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT); val 307 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); val 308 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); val 309 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); val 310 drivers/phy/broadcom/phy-brcm-sata.c val = 0x0; val 311 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); val 312 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT); val 313 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); val 314 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); val 317 drivers/phy/broadcom/phy-brcm-sata.c val = NS2_PLL1_ACTRL2_MAGIC; val 318 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); val 319 drivers/phy/broadcom/phy-brcm-sata.c val = NS2_PLL1_ACTRL3_MAGIC; val 320 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); val 321 drivers/phy/broadcom/phy-brcm-sata.c val = NS2_PLL1_ACTRL4_MAGIC; val 322 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); val 339 drivers/phy/broadcom/phy-brcm-sata.c val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, val 341 drivers/phy/broadcom/phy-brcm-sata.c if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) val 363 drivers/phy/broadcom/phy-brcm-sata.c unsigned int val, try; val 373 drivers/phy/broadcom/phy-brcm-sata.c val = 0x0; val 374 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT); val 375 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT); val 376 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); val 377 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); val 378 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val); val 380 drivers/phy/broadcom/phy-brcm-sata.c val = 0x0; val 381 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); val 382 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT); val 383 drivers/phy/broadcom/phy-brcm-sata.c val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); val 384 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val); val 394 drivers/phy/broadcom/phy-brcm-sata.c val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR; val 396 drivers/phy/broadcom/phy-brcm-sata.c ~val, val); val 397 drivers/phy/broadcom/phy-brcm-sata.c val = PLLCONTROL_0_SEQ_START; val 399 drivers/phy/broadcom/phy-brcm-sata.c ~val, 0); val 402 drivers/phy/broadcom/phy-brcm-sata.c ~val, val); val 407 drivers/phy/broadcom/phy-brcm-sata.c val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, val 409 drivers/phy/broadcom/phy-brcm-sata.c if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) val 437 drivers/phy/broadcom/phy-brcm-sata.c unsigned int val, try; val 440 drivers/phy/broadcom/phy-brcm-sata.c val = SR_PLL1_ACTRL2_MAGIC; val 441 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); val 442 drivers/phy/broadcom/phy-brcm-sata.c val = SR_PLL1_ACTRL3_MAGIC; val 443 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); val 444 drivers/phy/broadcom/phy-brcm-sata.c val = SR_PLL1_ACTRL4_MAGIC; val 445 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); val 448 drivers/phy/broadcom/phy-brcm-sata.c val = SR_PLL0_ACTRL6_MAGIC; val 449 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val); val 454 drivers/phy/broadcom/phy-brcm-sata.c val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, val 456 drivers/phy/broadcom/phy-brcm-sata.c if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) val 462 drivers/phy/broadcom/phy-brcm-sata.c if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) { val 473 drivers/phy/broadcom/phy-brcm-sata.c val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) | val 477 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); val 478 drivers/phy/broadcom/phy-brcm-sata.c val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) | val 481 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); val 409 drivers/phy/broadcom/phy-brcm-usb-init.c static inline void brcmusb_writel(u32 val, void __iomem *addr) val 411 drivers/phy/broadcom/phy-brcm-usb-init.c writel(val, addr); val 473 drivers/phy/broadcom/phy-brcm-usb-init.c u32 val, int mode) val 477 drivers/phy/broadcom/phy-brcm-usb-init.c data = (reg << 16) | val | mode; val 522 drivers/phy/broadcom/phy-brcm-usb-init.c u32 val; val 526 drivers/phy/broadcom/phy-brcm-usb-init.c val = brcmusb_usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200; val 527 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3); val 532 drivers/phy/broadcom/phy-brcm-usb-init.c u32 val, ofs; val 540 drivers/phy/broadcom/phy-brcm-usb-init.c val = brcmusb_usb_mdio_read(ctrl_base, 0x05, MDIO_USB3); val 541 drivers/phy/broadcom/phy-brcm-usb-init.c val = (val & ~0x800f) | 0x800d; val 542 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3); val 549 drivers/phy/broadcom/phy-brcm-usb-init.c u32 val, ofs; val 557 drivers/phy/broadcom/phy-brcm-usb-init.c val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200; val 558 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); val 565 drivers/phy/broadcom/phy-brcm-usb-init.c u32 val, ofs; val 573 drivers/phy/broadcom/phy-brcm-usb-init.c val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3); val 574 drivers/phy/broadcom/phy-brcm-usb-init.c val &= ~0x0008; val 575 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); val 647 drivers/phy/broadcom/phy-brcm-usb-init.c u32 val; val 651 drivers/phy/broadcom/phy-brcm-usb-init.c val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf; val 652 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); val 659 drivers/phy/broadcom/phy-brcm-usb-init.c val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf; val 660 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); val 708 drivers/phy/broadcom/phy-brcm-usb-init.c u32 val; val 713 drivers/phy/broadcom/phy-brcm-usb-init.c val = brcmusb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT)); val 716 drivers/phy/broadcom/phy-brcm-usb-init.c val |= (1 << 27); val 717 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(val, USB_XHCI_EC_REG(xhci_ec_base, IRADAT)); val 125 drivers/phy/cadence/phy-cadence-dp.c unsigned int val); val 432 drivers/phy/cadence/phy-cadence-dp.c unsigned int val) val 437 drivers/phy/cadence/phy-cadence-dp.c writel(((val << start_bit) | (read_val & ~(((1 << num_bits) - 1) << val 77 drivers/phy/cadence/phy-cadence-sierra.c u16 val; val 120 drivers/phy/cadence/phy-cadence-sierra.c writel(vals[j].val, phy->base + val 68 drivers/phy/hisilicon/phy-hi3660-usb3.c u32 val, mask; val 77 drivers/phy/hisilicon/phy-hi3660-usb3.c val = USB_TCXO_EN | (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START); val 78 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, val); val 83 drivers/phy/hisilicon/phy-hi3660-usb3.c val = IP_RST_USB3OTGPHY_POR | IP_RST_USB3OTG; val 84 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_write(priv->peri_crg, PERI_CRG_RSTEN4, val); val 89 drivers/phy/hisilicon/phy-hi3660-usb3.c val = SC_USB3PHY_ABB_GT_EN; val 90 drivers/phy/hisilicon/phy-hi3660-usb3.c mask = val; val 91 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL0, mask, val); val 95 drivers/phy/hisilicon/phy-hi3660-usb3.c val = REF_SSP_EN; val 96 drivers/phy/hisilicon/phy-hi3660-usb3.c mask = val; val 97 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL7, mask, val); val 111 drivers/phy/hisilicon/phy-hi3660-usb3.c val = IP_RST_USB3OTGPHY_POR | IP_RST_USB3OTG; val 112 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_write(priv->peri_crg, PERI_CRG_RSTDIS4, val); val 120 drivers/phy/hisilicon/phy-hi3660-usb3.c val = USBOTG3_CTRL3_VBUSVLDEXT | USBOTG3_CTRL3_VBUSVLDEXTSEL; val 121 drivers/phy/hisilicon/phy-hi3660-usb3.c mask = val; val 122 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL3, mask, val); val 143 drivers/phy/hisilicon/phy-hi3660-usb3.c u32 val; val 147 drivers/phy/hisilicon/phy-hi3660-usb3.c val = IP_RST_USB3OTGPHY_POR; val 148 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_write(priv->peri_crg, PERI_CRG_RSTEN4, val); val 153 drivers/phy/hisilicon/phy-hi3660-usb3.c val = USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START; val 154 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, val); val 51 drivers/phy/hisilicon/phy-hi6220-usb.c u32 val, mask; val 53 drivers/phy/hisilicon/phy-hi6220-usb.c val = RST0_USBOTG_BUS | RST0_POR_PICOPHY | val 55 drivers/phy/hisilicon/phy-hi6220-usb.c mask = val; val 56 drivers/phy/hisilicon/phy-hi6220-usb.c regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val); val 57 drivers/phy/hisilicon/phy-hi6220-usb.c regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val); val 63 drivers/phy/hisilicon/phy-hi6220-usb.c u32 val, mask; val 67 drivers/phy/hisilicon/phy-hi6220-usb.c val = CTRL5_USBOTG_RES_SEL | CTRL5_PICOPHY_ACAENB; val 68 drivers/phy/hisilicon/phy-hi6220-usb.c mask = val | CTRL5_PICOPHY_BC_MODE; val 69 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL5, mask, val); val 73 drivers/phy/hisilicon/phy-hi6220-usb.c val = CTRL4_PICO_VBUSVLDEXT | CTRL4_PICO_VBUSVLDEXTSEL | val 75 drivers/phy/hisilicon/phy-hi6220-usb.c mask = val | CTRL4_PICO_SIDDQ | CTRL4_PICO_OGDISABLE; val 76 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val); val 84 drivers/phy/hisilicon/phy-hi6220-usb.c val = CTRL4_PICO_SIDDQ; val 85 drivers/phy/hisilicon/phy-hi6220-usb.c mask = val; val 86 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val); val 47 drivers/phy/hisilicon/phy-hisi-inno-usb2.c u32 val; val 49 drivers/phy/hisilicon/phy-hisi-inno-usb2.c val = (data & PHY_TEST_DATA) | val 53 drivers/phy/hisilicon/phy-hisi-inno-usb2.c writel(val, reg); val 55 drivers/phy/hisilicon/phy-hisi-inno-usb2.c val |= PHY_TEST_CLK; val 56 drivers/phy/hisilicon/phy-hisi-inno-usb2.c writel(val, reg); val 58 drivers/phy/hisilicon/phy-hisi-inno-usb2.c val &= ~PHY_TEST_CLK; val 59 drivers/phy/hisilicon/phy-hisi-inno-usb2.c writel(val, reg); val 56 drivers/phy/hisilicon/phy-histb-combphy.c u32 val; val 59 drivers/phy/hisilicon/phy-histb-combphy.c val = readl(reg); val 60 drivers/phy/hisilicon/phy-histb-combphy.c val &= ~COMBPHY_TEST_ADDR_MASK; val 61 drivers/phy/hisilicon/phy-histb-combphy.c val |= addr << COMBPHY_TEST_ADDR_SHIFT; val 62 drivers/phy/hisilicon/phy-histb-combphy.c val &= ~COMBPHY_TEST_DATA_MASK; val 63 drivers/phy/hisilicon/phy-histb-combphy.c val |= data << COMBPHY_TEST_DATA_SHIFT; val 64 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, reg); val 67 drivers/phy/hisilicon/phy-histb-combphy.c val &= ~COMBPHY_TEST_WRITE; val 68 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, reg); val 69 drivers/phy/hisilicon/phy-histb-combphy.c val |= COMBPHY_TEST_WRITE; val 70 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, reg); val 108 drivers/phy/hisilicon/phy-histb-combphy.c u32 val; val 116 drivers/phy/hisilicon/phy-histb-combphy.c val = readl(priv->mmio + COMBPHY_CFG_REG); val 117 drivers/phy/hisilicon/phy-histb-combphy.c val &= ~COMBPHY_BYPASS_CODEC; val 118 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, priv->mmio + COMBPHY_CFG_REG); val 127 drivers/phy/hisilicon/phy-histb-combphy.c val = readl(priv->mmio + COMBPHY_CFG_REG); val 128 drivers/phy/hisilicon/phy-histb-combphy.c val |= COMBPHY_CLKREF_OUT_OEN; val 129 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, priv->mmio + COMBPHY_CFG_REG); val 145 drivers/phy/hisilicon/phy-histb-combphy.c u32 val; val 148 drivers/phy/hisilicon/phy-histb-combphy.c val = readl(priv->mmio + COMBPHY_CFG_REG); val 149 drivers/phy/hisilicon/phy-histb-combphy.c val &= ~COMBPHY_CLKREF_OUT_OEN; val 150 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, priv->mmio + COMBPHY_CFG_REG); val 64 drivers/phy/hisilicon/phy-hix5hd2-sata.c u32 val, data[2]; val 81 drivers/phy/hisilicon/phy-hix5hd2-sata.c val = readl_relaxed(priv->base + SATA_PHY0_CTLL); val 82 drivers/phy/hisilicon/phy-hix5hd2-sata.c val &= ~(MPLL_MULTIPLIER_MASK | REF_USE_PAD); val 83 drivers/phy/hisilicon/phy-hix5hd2-sata.c val |= MPLL_MULTIPLIER_50M << MPLL_MULTIPLIER_SHIFT | val 85 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PHY0_CTLL); val 87 drivers/phy/hisilicon/phy-hix5hd2-sata.c val &= ~PHY_RESET; val 88 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PHY0_CTLL); val 90 drivers/phy/hisilicon/phy-hix5hd2-sata.c val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1); val 91 drivers/phy/hisilicon/phy-hix5hd2-sata.c val &= ~AMPLITUDE_MASK; val 92 drivers/phy/hisilicon/phy-hix5hd2-sata.c val |= AMPLITUDE_GEN3 << AMPLITUDE_GEN3_SHIFT | val 95 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1); val 97 drivers/phy/hisilicon/phy-hix5hd2-sata.c val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2); val 98 drivers/phy/hisilicon/phy-hix5hd2-sata.c val &= ~PREEMPH_MASK; val 99 drivers/phy/hisilicon/phy-hix5hd2-sata.c val |= PREEMPH_GEN3 << PREEMPH_GEN3_SHIFT | val 102 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2); val 105 drivers/phy/hisilicon/phy-hix5hd2-sata.c val = readl_relaxed(priv->base + SATA_PORT_PHYCTL); val 106 drivers/phy/hisilicon/phy-hix5hd2-sata.c val &= ~SPEED_MODE_MASK; val 107 drivers/phy/hisilicon/phy-hix5hd2-sata.c val |= SPEED_MODE_GEN1 << HALF_RATE_SHIFT | val 110 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); val 113 drivers/phy/hisilicon/phy-hix5hd2-sata.c val &= ~SPEED_MODE_MASK; val 114 drivers/phy/hisilicon/phy-hix5hd2-sata.c val |= SPEED_MODE_GEN3 << HALF_RATE_SHIFT | val 117 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); val 119 drivers/phy/hisilicon/phy-hix5hd2-sata.c val &= ~(SPEED_MODE_MASK | SPEED_CTRL); val 120 drivers/phy/hisilicon/phy-hix5hd2-sata.c val |= SPEED_MODE_GEN2 << HALF_RATE_SHIFT | val 123 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); val 60 drivers/phy/marvell/phy-armada38x-comphy.c u32 val; val 62 drivers/phy/marvell/phy-armada38x-comphy.c val = readl_relaxed(lane->base + offset) & ~mask; val 63 drivers/phy/marvell/phy-armada38x-comphy.c writel(val | value, lane->base + offset); val 78 drivers/phy/marvell/phy-armada38x-comphy.c u32 val; val 81 drivers/phy/marvell/phy-armada38x-comphy.c ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val, val 82 drivers/phy/marvell/phy-armada38x-comphy.c (val & mask) == value, val 137 drivers/phy/marvell/phy-armada38x-comphy.c u32 val; val 152 drivers/phy/marvell/phy-armada38x-comphy.c val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR); val 153 drivers/phy/marvell/phy-armada38x-comphy.c val = (val >> (4 * lane->n)) & 0xf; val 156 drivers/phy/marvell/phy-armada38x-comphy.c val != gbe_mux[lane->n][lane->port]) { val 188 drivers/phy/marvell/phy-armada38x-comphy.c u32 val; val 190 drivers/phy/marvell/phy-armada38x-comphy.c ret = of_property_read_u32(child, "reg", &val); val 197 drivers/phy/marvell/phy-armada38x-comphy.c if (val >= MAX_A38X_COMPHY || priv->lane[val].base) { val 208 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].base = base + 0x28 * val; val 209 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].priv = priv; val 210 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].n = val; val 211 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].port = -1; val 212 drivers/phy/marvell/phy-armada38x-comphy.c phy_set_drvdata(phy, &priv->lane[val]); val 66 drivers/phy/marvell/phy-berlin-sata.c u32 phy_base, u32 reg, u32 mask, u32 val) val 76 drivers/phy/marvell/phy-berlin-sata.c regval |= val; val 327 drivers/phy/marvell/phy-mvebu-cp110-comphy.c u32 val; val 329 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); val 330 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; val 331 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_CONF1_PWRUP; val 332 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); val 335 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); val 336 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL | val 346 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | val 350 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xb) | val 355 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) | val 360 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) | val 372 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); val 375 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, &val); val 380 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN; val 384 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN; val 393 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, val); val 397 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 398 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | val 401 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 404 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 405 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG1_RESET | val 407 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 413 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val); val 414 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_CONF6_40B; val 415 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val); val 418 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); val 419 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; val 421 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE; val 422 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); val 425 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); val 426 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) | val 428 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) | val 430 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); val 432 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); val 433 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7); val 434 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1); val 435 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); val 443 drivers/phy/marvell/phy-mvebu-cp110-comphy.c u32 val; val 446 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); val 447 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG0_PU_PLL | val 450 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); val 454 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val, val 455 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | val 458 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | val 463 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 464 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG1_RX_INIT; val 465 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 469 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val, val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT, val 471 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (!(val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT)) val 474 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 475 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_SERDES_CFG1_RX_INIT; val 476 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 485 drivers/phy/marvell/phy-mvebu-cp110-comphy.c u32 val; val 492 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); val 493 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; val 494 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL; val 495 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); val 497 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); val 498 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN; val 499 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); val 501 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); val 502 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; val 503 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_CONF1_PWRUP; val 504 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); val 506 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val 507 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf); val 508 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1); val 509 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val 518 drivers/phy/marvell/phy-mvebu-cp110-comphy.c u32 val; val 525 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); val 526 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL | val 528 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); val 530 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); val 531 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN; val 532 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); val 534 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); val 535 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN; val 536 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); val 538 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); val 539 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL; val 540 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); val 542 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val 543 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf); val 544 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xd); val 545 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val 547 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); val 548 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) | val 550 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x1) | val 553 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); val 555 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); val 556 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL); val 557 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); val 559 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); val 560 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3); val 561 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1); val 562 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); val 571 drivers/phy/marvell/phy-mvebu-cp110-comphy.c u32 val; val 578 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); val 579 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL | val 581 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); val 583 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); val 584 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN; val 585 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); val 588 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); val 589 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SPEED_DIV_TX_FORCE; val 590 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); val 592 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); val 593 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN; val 594 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); val 597 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); val 598 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL; val 599 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); val 601 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val 602 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) | val 604 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) | val 606 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val 608 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); val 609 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf); val 610 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN; val 611 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); val 613 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); val 614 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_TX_SLEW_RATE_EMPH(0x3) | val 616 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); val 619 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); val 620 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f); val 621 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_IMP_CAL_TX_EXT(0xe) | val 623 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); val 625 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); val 626 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_GEN1_S5_ICP(0xf); val 627 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); val 629 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); val 630 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) | val 634 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S1_RX_DFE_EN | val 639 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); val 641 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); val 642 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL); val 643 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); val 645 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); val 646 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3); val 647 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1); val 648 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); val 650 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); val 651 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_GEN1_S3_FBCK_SEL; val 652 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); val 655 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); val 656 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_TRAINING5_RX_TIMER(0x3ff); val 657 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_TRAINING5_RX_TIMER(0x13); val 658 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); val 661 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); val 662 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_TRAINING0_P2P_HOLD; val 663 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); val 665 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); val 666 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_TX_PRESET_INDEX(0xf); val 667 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_TX_PRESET_INDEX(0x2); /* preset coeff */ val 668 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); val 670 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); val 671 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN; val 672 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); val 674 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); val 675 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN | val 677 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); val 679 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); val 680 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_FRAME_DETECT0_PATN(0x1ff); val 681 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_FRAME_DETECT0_PATN(0x88); val 682 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); val 684 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DME(lane->id)); val 685 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_DME_ETH_MODE; val 686 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DME(lane->id)); val 688 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); val 689 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_VDD_CAL0_CONT_MODE; val 690 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); val 692 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); val 693 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_SP_CALIB_SAMPLER(0x3); val 694 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_SP_CALIB_SAMPLER(0x3) | val 696 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); val 697 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_SP_CALIB_SAMPLER_EN; val 698 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); val 701 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); val 702 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f); val 703 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a); val 704 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); val 714 drivers/phy/marvell/phy-mvebu-cp110-comphy.c u32 val; val 721 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val); val 722 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); val 723 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val); val 725 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); val 726 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); val 727 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id); val 728 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); val 746 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 747 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= MVEBU_COMPHY_SERDES_CFG1_RF_RESET; val 748 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 860 drivers/phy/marvell/phy-mvebu-cp110-comphy.c u32 val; val 862 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 863 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | val 866 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); val 868 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); val 869 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); val 870 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); val 872 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val); val 873 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); val 874 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val); val 1022 drivers/phy/marvell/phy-mvebu-cp110-comphy.c u32 val; val 1024 drivers/phy/marvell/phy-mvebu-cp110-comphy.c ret = of_property_read_u32(child, "reg", &val); val 1031 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (val >= MVEBU_COMPHY_LANES) { val 1053 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id = val; val 268 drivers/phy/marvell/phy-pxa-28nm-usb2.c unsigned int val; val 270 drivers/phy/marvell/phy-pxa-28nm-usb2.c val = readw(base + PHY_28NM_PLL_REG1); val 271 drivers/phy/marvell/phy-pxa-28nm-usb2.c val &= ~PHY_28NM_PLL_PU_PLL; val 272 drivers/phy/marvell/phy-pxa-28nm-usb2.c writew(val, base + PHY_28NM_PLL_REG1); val 275 drivers/phy/marvell/phy-pxa-28nm-usb2.c val = readw(base + PHY_28NM_TX_REG0); val 276 drivers/phy/marvell/phy-pxa-28nm-usb2.c val &= ~PHY_28NM_TX_PU_ANA; val 277 drivers/phy/marvell/phy-pxa-28nm-usb2.c writew(val, base + PHY_28NM_TX_REG0); val 280 drivers/phy/marvell/phy-pxa-28nm-usb2.c val = readw(base + PHY_28NM_OTG_REG); val 281 drivers/phy/marvell/phy-pxa-28nm-usb2.c val &= ~PHY_28NM_OTG_PU_OTG; val 282 drivers/phy/marvell/phy-pxa-28nm-usb2.c writew(val, base + PHY_28NM_OTG_REG); val 46 drivers/phy/mediatek/phy-mtk-ufs.c static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg) val 48 drivers/phy/mediatek/phy-mtk-ufs.c writel(val, phy->mmio + reg); val 53 drivers/phy/mediatek/phy-mtk-ufs.c u32 val; val 55 drivers/phy/mediatek/phy-mtk-ufs.c val = mphy_readl(phy, reg); val 56 drivers/phy/mediatek/phy-mtk-ufs.c val |= bit; val 57 drivers/phy/mediatek/phy-mtk-ufs.c mphy_writel(phy, val, reg); val 62 drivers/phy/mediatek/phy-mtk-ufs.c u32 val; val 64 drivers/phy/mediatek/phy-mtk-ufs.c val = mphy_readl(phy, reg); val 65 drivers/phy/mediatek/phy-mtk-ufs.c val &= ~bit; val 66 drivers/phy/mediatek/phy-mtk-ufs.c mphy_writel(phy, val, reg); val 178 drivers/phy/motorola/phy-cpcap-usb.c int val, error; val 180 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_read(ddata->reg, CPCAP_REG_INTS1, &val); val 184 drivers/phy/motorola/phy-cpcap-usb.c s->id_ground = val & BIT(15); val 185 drivers/phy/motorola/phy-cpcap-usb.c s->id_float = val & BIT(14); val 186 drivers/phy/motorola/phy-cpcap-usb.c s->vbusov = val & BIT(11); val 188 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_read(ddata->reg, CPCAP_REG_INTS2, &val); val 192 drivers/phy/motorola/phy-cpcap-usb.c s->vbusvld = val & BIT(3); val 193 drivers/phy/motorola/phy-cpcap-usb.c s->sessvld = val & BIT(2); val 194 drivers/phy/motorola/phy-cpcap-usb.c s->sessend = val & BIT(1); val 195 drivers/phy/motorola/phy-cpcap-usb.c s->se1 = val & BIT(0); val 197 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_read(ddata->reg, CPCAP_REG_INTS4, &val); val 201 drivers/phy/motorola/phy-cpcap-usb.c s->dm = val & BIT(1); val 202 drivers/phy/motorola/phy-cpcap-usb.c s->dp = val & BIT(0); val 184 drivers/phy/motorola/phy-mapphone-mdm6600.c static void phy_mdm6600_cmd(struct phy_mdm6600 *ddata, int val) val 188 drivers/phy/motorola/phy-mapphone-mdm6600.c values[0] = val; val 95 drivers/phy/phy-pistachio-usb.c unsigned int val; val 97 drivers/phy/phy-pistachio-usb.c regmap_read(p_phy->cr_top, USB_PHY_STATUS, &val); val 98 drivers/phy/phy-pistachio-usb.c if (val & USB_PHY_STATUS_VBUS_FAULT) { val 103 drivers/phy/phy-pistachio-usb.c if ((val & USB_PHY_STATUS_RX_PHY_CLK) && val 104 drivers/phy/phy-pistachio-usb.c (val & USB_PHY_STATUS_RX_UTMI_CLK)) val 554 drivers/phy/phy-xgene.c u32 val; val 564 drivers/phy/phy-xgene.c val = readl(csr_base + indirect_cmd_reg); val 565 drivers/phy/phy-xgene.c } while (!(val & CFG_IND_CMD_DONE_MASK) && val 567 drivers/phy/phy-xgene.c if (!(val & CFG_IND_CMD_DONE_MASK)) val 576 drivers/phy/phy-xgene.c u32 val; val 584 drivers/phy/phy-xgene.c val = readl(csr_base + indirect_cmd_reg); val 585 drivers/phy/phy-xgene.c } while (!(val & CFG_IND_CMD_DONE_MASK) && val 588 drivers/phy/phy-xgene.c if (!(val & CFG_IND_CMD_DONE_MASK)) val 597 drivers/phy/phy-xgene.c u32 val; val 606 drivers/phy/phy-xgene.c SATA_ENET_SDS_IND_RDATA_REG, reg, &val); val 607 drivers/phy/phy-xgene.c pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); val 627 drivers/phy/phy-xgene.c u32 val; val 629 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, reg, &val); val 630 drivers/phy/phy-xgene.c val |= bits; val 631 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, reg, val); val 632 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, reg, &val); val 633 drivers/phy/phy-xgene.c val &= ~bits; val 634 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, reg, val); val 640 drivers/phy/phy-xgene.c u32 val; val 642 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, reg, &val); val 643 drivers/phy/phy-xgene.c val &= ~bits; val 644 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, reg, val); val 650 drivers/phy/phy-xgene.c u32 val; val 652 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, reg, &val); val 653 drivers/phy/phy-xgene.c val |= bits; val 654 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, reg, val); val 660 drivers/phy/phy-xgene.c u32 val; val 667 drivers/phy/phy-xgene.c SATA_ENET_SDS_IND_RDATA_REG, reg, &val); val 669 drivers/phy/phy-xgene.c val); val 686 drivers/phy/phy-xgene.c u32 val; val 688 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); val 689 drivers/phy/phy-xgene.c val &= ~bits; val 690 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); val 696 drivers/phy/phy-xgene.c u32 val; val 698 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); val 699 drivers/phy/phy-xgene.c val |= bits; val 700 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); val 707 drivers/phy/phy-xgene.c u32 val; val 710 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG12, &val); val 711 drivers/phy/phy-xgene.c val = CMU_REG12_STATE_DELAY9_SET(val, 0x1); val 712 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG12, val); val 720 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG0, &val); val 721 drivers/phy/phy-xgene.c val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0); val 722 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG0, val); val 724 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG1, &val); val 725 drivers/phy/phy-xgene.c val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); val 726 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG1, val); val 730 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG0, &val); val 731 drivers/phy/phy-xgene.c val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1); val 732 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG0, val); val 734 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG1, &val); val 735 drivers/phy/phy-xgene.c val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); val 736 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG1, val); val 745 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG1, &val); val 746 drivers/phy/phy-xgene.c val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); val 747 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG1, val); val 749 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG1, &val); val 750 drivers/phy/phy-xgene.c val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); val 751 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG1, val); val 761 drivers/phy/phy-xgene.c u32 val; val 766 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG34, &val); val 767 drivers/phy/phy-xgene.c val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7); val 768 drivers/phy/phy-xgene.c val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc); val 769 drivers/phy/phy-xgene.c val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3); val 770 drivers/phy/phy-xgene.c val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8); val 771 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG34, val); val 775 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG0, &val); val 777 drivers/phy/phy-xgene.c val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4); val 779 drivers/phy/phy-xgene.c val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7); val 780 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG0, val); val 783 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG1, &val); val 784 drivers/phy/phy-xgene.c val = CMU_REG1_PLL_CP_SET(val, 0x1); val 786 drivers/phy/phy-xgene.c val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5); val 788 drivers/phy/phy-xgene.c val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3); val 790 drivers/phy/phy-xgene.c val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); val 792 drivers/phy/phy-xgene.c val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1); val 793 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG1, val); val 799 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG2, &val); val 801 drivers/phy/phy-xgene.c val = CMU_REG2_PLL_LFRES_SET(val, 0xa); val 804 drivers/phy/phy-xgene.c val = CMU_REG2_PLL_LFRES_SET(val, 0x3); val 811 drivers/phy/phy-xgene.c val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M); val 812 drivers/phy/phy-xgene.c val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M); val 814 drivers/phy/phy-xgene.c val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M); val 815 drivers/phy/phy-xgene.c val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M); val 817 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG2, val); val 820 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG3, &val); val 822 drivers/phy/phy-xgene.c val = CMU_REG3_VCOVARSEL_SET(val, 0x3); val 823 drivers/phy/phy-xgene.c val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10); val 825 drivers/phy/phy-xgene.c val = CMU_REG3_VCOVARSEL_SET(val, 0xF); val 827 drivers/phy/phy-xgene.c val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15); val 829 drivers/phy/phy-xgene.c val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a); val 830 drivers/phy/phy-xgene.c val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15); val 832 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG3, val); val 835 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG26, &val); val 836 drivers/phy/phy-xgene.c val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0); val 837 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG26, val); val 840 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG5, &val); val 841 drivers/phy/phy-xgene.c val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3); val 842 drivers/phy/phy-xgene.c val = CMU_REG5_PLL_LFCAP_SET(val, 0x3); val 844 drivers/phy/phy-xgene.c val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7); val 846 drivers/phy/phy-xgene.c val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4); val 847 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG5, val); val 850 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG6, &val); val 851 drivers/phy/phy-xgene.c val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2); val 852 drivers/phy/phy-xgene.c val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0); val 853 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG6, val); val 857 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG9, &val); val 858 drivers/phy/phy-xgene.c val = CMU_REG9_TX_WORD_MODE_CH1_SET(val, val 860 drivers/phy/phy-xgene.c val = CMU_REG9_TX_WORD_MODE_CH0_SET(val, val 862 drivers/phy/phy-xgene.c val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1); val 864 drivers/phy/phy-xgene.c val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0); val 865 drivers/phy/phy-xgene.c val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0); val 867 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG9, val); val 870 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG10, &val); val 871 drivers/phy/phy-xgene.c val = CMU_REG10_VREG_REFSEL_SET(val, 0x1); val 872 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG10, val); val 876 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG16, &val); val 877 drivers/phy/phy-xgene.c val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1); val 878 drivers/phy/phy-xgene.c val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1); val 880 drivers/phy/phy-xgene.c val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4); val 882 drivers/phy/phy-xgene.c val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); val 883 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG16, val); val 886 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG30, &val); val 887 drivers/phy/phy-xgene.c val = CMU_REG30_PCIE_MODE_SET(val, 0x0); val 888 drivers/phy/phy-xgene.c val = CMU_REG30_LOCK_COUNT_SET(val, 0x3); val 889 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG30, val); val 894 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG32, &val); val 895 drivers/phy/phy-xgene.c val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3); val 897 drivers/phy/phy-xgene.c val = CMU_REG32_IREF_ADJ_SET(val, 0x3); val 899 drivers/phy/phy-xgene.c val = CMU_REG32_IREF_ADJ_SET(val, 0x1); val 900 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG32, val); val 915 drivers/phy/phy-xgene.c u32 val; val 918 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG35, &val); val 919 drivers/phy/phy-xgene.c val = CMU_REG35_PLL_SSC_MOD_SET(val, 98); val 920 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG35, val); val 923 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG36, &val); val 924 drivers/phy/phy-xgene.c val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30); val 925 drivers/phy/phy-xgene.c val = CMU_REG36_PLL_SSC_EN_SET(val, 1); val 926 drivers/phy/phy-xgene.c val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1); val 927 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG36, val); val 940 drivers/phy/phy-xgene.c u32 val; val 949 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG0, &val); val 950 drivers/phy/phy-xgene.c val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10); val 951 drivers/phy/phy-xgene.c val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10); val 952 drivers/phy/phy-xgene.c val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10); val 953 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG0, val); val 956 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG1, &val); val 957 drivers/phy/phy-xgene.c val = RXTX_REG1_RXACVCM_SET(val, 0x7); val 958 drivers/phy/phy-xgene.c val = RXTX_REG1_CTLE_EQ_SET(val, val 961 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG1, val); val 965 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG2, &val); val 966 drivers/phy/phy-xgene.c val = RXTX_REG2_VTT_ENA_SET(val, 0x1); val 967 drivers/phy/phy-xgene.c val = RXTX_REG2_VTT_SEL_SET(val, 0x1); val 968 drivers/phy/phy-xgene.c val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1); val 969 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG2, val); val 972 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG4, &val); val 973 drivers/phy/phy-xgene.c val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); val 974 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG4, val); val 977 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG1, &val); val 978 drivers/phy/phy-xgene.c val = RXTX_REG1_RXVREG1_SET(val, 0x2); val 979 drivers/phy/phy-xgene.c val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2); val 980 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG1, val); val 984 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG5, &val); val 985 drivers/phy/phy-xgene.c val = RXTX_REG5_TX_CN1_SET(val, val 988 drivers/phy/phy-xgene.c val = RXTX_REG5_TX_CP1_SET(val, val 991 drivers/phy/phy-xgene.c val = RXTX_REG5_TX_CN2_SET(val, val 994 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG5, val); val 997 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG6, &val); val 998 drivers/phy/phy-xgene.c val = RXTX_REG6_TXAMP_CNTL_SET(val, val 1001 drivers/phy/phy-xgene.c val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1); val 1002 drivers/phy/phy-xgene.c val = RXTX_REG6_TX_IDLE_SET(val, 0x0); val 1003 drivers/phy/phy-xgene.c val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0); val 1004 drivers/phy/phy-xgene.c val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0); val 1005 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG6, val); val 1008 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG7, &val); val 1009 drivers/phy/phy-xgene.c val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0); val 1010 drivers/phy/phy-xgene.c val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); val 1011 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG7, val); val 1014 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG8, &val); val 1015 drivers/phy/phy-xgene.c val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1); val 1016 drivers/phy/phy-xgene.c val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0); val 1017 drivers/phy/phy-xgene.c val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1); val 1018 drivers/phy/phy-xgene.c val = RXTX_REG8_SD_DISABLE_SET(val, 0x0); val 1019 drivers/phy/phy-xgene.c val = RXTX_REG8_SD_VREF_SET(val, 0x4); val 1020 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG8, val); val 1023 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG11, &val); val 1024 drivers/phy/phy-xgene.c val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0); val 1025 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG11, val); val 1028 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG12, &val); val 1029 drivers/phy/phy-xgene.c val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1); val 1030 drivers/phy/phy-xgene.c val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0); val 1031 drivers/phy/phy-xgene.c val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0); val 1032 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG12, val); val 1035 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG26, &val); val 1036 drivers/phy/phy-xgene.c val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0); val 1037 drivers/phy/phy-xgene.c val = RXTX_REG26_BLWC_ENA_SET(val, 0x1); val 1038 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG26, val); val 1046 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG61, &val); val 1047 drivers/phy/phy-xgene.c val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1); val 1048 drivers/phy/phy-xgene.c val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0); val 1049 drivers/phy/phy-xgene.c val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0); val 1050 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG61, val); val 1052 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG62, &val); val 1053 drivers/phy/phy-xgene.c val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0); val 1054 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG62, val); val 1059 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); val 1060 drivers/phy/phy-xgene.c val = RXTX_REG89_MU_TH7_SET(val, 0xe); val 1061 drivers/phy/phy-xgene.c val = RXTX_REG89_MU_TH8_SET(val, 0xe); val 1062 drivers/phy/phy-xgene.c val = RXTX_REG89_MU_TH9_SET(val, 0xe); val 1063 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); val 1069 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); val 1070 drivers/phy/phy-xgene.c val = RXTX_REG96_MU_FREQ1_SET(val, 0x10); val 1071 drivers/phy/phy-xgene.c val = RXTX_REG96_MU_FREQ2_SET(val, 0x10); val 1072 drivers/phy/phy-xgene.c val = RXTX_REG96_MU_FREQ3_SET(val, 0x10); val 1073 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); val 1079 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); val 1080 drivers/phy/phy-xgene.c val = RXTX_REG99_MU_PHASE1_SET(val, 0x7); val 1081 drivers/phy/phy-xgene.c val = RXTX_REG99_MU_PHASE2_SET(val, 0x7); val 1082 drivers/phy/phy-xgene.c val = RXTX_REG99_MU_PHASE3_SET(val, 0x7); val 1083 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); val 1086 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG102, &val); val 1087 drivers/phy/phy-xgene.c val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0); val 1088 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG102, val); val 1092 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG125, &val); val 1093 drivers/phy/phy-xgene.c val = RXTX_REG125_SIGN_PQ_SET(val, val 1096 drivers/phy/phy-xgene.c val = RXTX_REG125_PQ_REG_SET(val, val 1099 drivers/phy/phy-xgene.c val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1); val 1100 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG125, val); val 1102 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG127, &val); val 1103 drivers/phy/phy-xgene.c val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0); val 1104 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG127, val); val 1106 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG128, &val); val 1107 drivers/phy/phy-xgene.c val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3); val 1108 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG128, val); val 1110 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG145, &val); val 1111 drivers/phy/phy-xgene.c val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3); val 1112 drivers/phy/phy-xgene.c val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0); val 1114 drivers/phy/phy-xgene.c val = RXTX_REG145_RXES_ENA_SET(val, 0x1); val 1115 drivers/phy/phy-xgene.c val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1); val 1117 drivers/phy/phy-xgene.c val = RXTX_REG145_RXES_ENA_SET(val, 0x0); val 1118 drivers/phy/phy-xgene.c val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0); val 1120 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG145, val); val 1139 drivers/phy/phy-xgene.c u32 val; val 1153 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG1, &val); val 1154 drivers/phy/phy-xgene.c val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); val 1155 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG1, val); val 1179 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG17, &val); val 1180 drivers/phy/phy-xgene.c val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12); val 1181 drivers/phy/phy-xgene.c val = CMU_REG17_RESERVED_7_SET(val, 0x0); val 1182 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG17, val); val 1190 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG17, &val); val 1191 drivers/phy/phy-xgene.c val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29); val 1192 drivers/phy/phy-xgene.c val = CMU_REG17_RESERVED_7_SET(val, 0x0); val 1193 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG17, val); val 1197 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG17, &val); val 1198 drivers/phy/phy-xgene.c val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28); val 1199 drivers/phy/phy-xgene.c val = CMU_REG17_RESERVED_7_SET(val, 0x0); val 1200 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG17, val); val 1208 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG7, &val); val 1209 drivers/phy/phy-xgene.c if (CMU_REG7_PLL_CALIB_DONE_RD(val)) val 1218 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG7, &val); val 1220 drivers/phy/phy-xgene.c CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed"); val 1221 drivers/phy/phy-xgene.c if (CMU_REG7_VCO_CAL_FAIL_RD(val)) { val 1228 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG15, &val); val 1229 drivers/phy/phy-xgene.c dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); val 1237 drivers/phy/phy-xgene.c u32 val; val 1241 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, CMU_REG16, &val); val 1242 drivers/phy/phy-xgene.c val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); val 1243 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, CMU_REG16, val); val 1255 drivers/phy/phy-xgene.c u32 val; val 1262 drivers/phy/phy-xgene.c val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ val 1271 drivers/phy/phy-xgene.c val = readl(sds_base + SATA_ENET_SDS_CTL1); val 1272 drivers/phy/phy-xgene.c val = CFG_I_SPD_SEL_CDR_OVR1_SET(val, val 1274 drivers/phy/phy-xgene.c writel(val, sds_base + SATA_ENET_SDS_CTL1); val 1277 drivers/phy/phy-xgene.c val = readl(sds_base + SATA_ENET_SDS_CTL0); val 1278 drivers/phy/phy-xgene.c val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421); val 1279 drivers/phy/phy-xgene.c writel(val, sds_base + SATA_ENET_SDS_CTL0); val 1295 drivers/phy/phy-xgene.c val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0); val 1296 drivers/phy/phy-xgene.c val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3); val 1297 drivers/phy/phy-xgene.c val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3); val 1298 drivers/phy/phy-xgene.c writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0); val 1347 drivers/phy/phy-xgene.c u32 val; val 1405 drivers/phy/phy-xgene.c serdes_reg[i].val); val 1434 drivers/phy/phy-xgene.c u32 val; val 1458 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG21, &val); val 1459 drivers/phy/phy-xgene.c lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val); val 1460 drivers/phy/phy-xgene.c lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val); val 1461 drivers/phy/phy-xgene.c fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val); val 1463 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG22, &val); val 1464 drivers/phy/phy-xgene.c lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val); val 1465 drivers/phy/phy-xgene.c lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val); val 1466 drivers/phy/phy-xgene.c fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val); val 1468 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG23, &val); val 1469 drivers/phy/phy-xgene.c lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val); val 1470 drivers/phy/phy-xgene.c lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val); val 1472 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG24, &val); val 1473 drivers/phy/phy-xgene.c lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val); val 1474 drivers/phy/phy-xgene.c lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val); val 1476 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG121, &val); val 1477 drivers/phy/phy-xgene.c sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val); val 1510 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG127, &val); val 1511 drivers/phy/phy-xgene.c val = RXTX_REG127_DO_LATCH_MANCAL_SET(val, val 1513 drivers/phy/phy-xgene.c val = RXTX_REG127_XO_LATCH_MANCAL_SET(val, val 1515 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG127, val); val 1517 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG128, &val); val 1518 drivers/phy/phy-xgene.c val = RXTX_REG128_EO_LATCH_MANCAL_SET(val, val 1520 drivers/phy/phy-xgene.c val = RXTX_REG128_SO_LATCH_MANCAL_SET(val, val 1522 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG128, val); val 1524 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG129, &val); val 1525 drivers/phy/phy-xgene.c val = RXTX_REG129_DE_LATCH_MANCAL_SET(val, val 1527 drivers/phy/phy-xgene.c val = RXTX_REG129_XE_LATCH_MANCAL_SET(val, val 1529 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG129, val); val 1531 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG130, &val); val 1532 drivers/phy/phy-xgene.c val = RXTX_REG130_EE_LATCH_MANCAL_SET(val, val 1534 drivers/phy/phy-xgene.c val = RXTX_REG130_SE_LATCH_MANCAL_SET(val, val 1536 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG130, val); val 1539 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG14, &val); val 1540 drivers/phy/phy-xgene.c val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val, val 1542 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG14, val); val 1558 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG14, &val); val 1559 drivers/phy/phy-xgene.c val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1); val 1560 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG14, val); val 1563 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG127, &val); val 1564 drivers/phy/phy-xgene.c val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1); val 1566 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG127, val); val 1569 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG12, &val); val 1570 drivers/phy/phy-xgene.c val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0); val 1571 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG12, val); val 72 drivers/phy/qualcomm/phy-qcom-pcie2.c u32 val; val 75 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); val 76 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~BIT(1); val 77 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); val 82 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); val 83 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~BIT(0); val 84 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); val 87 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); val 88 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= BIT(0); val 89 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); val 94 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); val 95 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= BIT(0); val 96 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); val 99 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1); val 100 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~0x7f; val 101 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= TX_AMP_VAL; val 102 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1); val 104 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2); val 105 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~0x7f; val 106 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= TX_AMP_VAL; val 107 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2); val 110 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1); val 111 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~0x3f; val 112 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= TX_DEEMPH_GEN2_6DB_VAL; val 113 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1); val 115 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2); val 116 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~0x3f; val 117 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= TX_DEEMPH_GEN2_3_5DB_VAL; val 118 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2); val 120 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3); val 121 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~0x3f; val 122 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= TX_DEEMPH_GEN1_VAL; val 123 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3); val 126 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_CONFIGBITS); val 127 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~0x7; val 128 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= PHY_RX0_EQ_GEN2_VAL; val 129 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_CONFIGBITS); val 132 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3); val 133 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~0x1f; val 134 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= PHY_TX0_TERM_OFFST_VAL; val 135 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3); val 138 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_CTRL); val 139 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~BIT(1); val 140 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_CTRL); val 143 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); val 144 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~BIT(0); val 145 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); val 163 drivers/phy/qualcomm/phy-qcom-pcie2.c ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val, val 164 drivers/phy/qualcomm/phy-qcom-pcie2.c !(val & BIT(0)), 1000, 10); val 175 drivers/phy/qualcomm/phy-qcom-pcie2.c u32 val; val 177 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); val 178 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= BIT(0); val 179 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); val 80 drivers/phy/qualcomm/phy-qcom-qmp.c unsigned int val; val 91 drivers/phy/qualcomm/phy-qcom-qmp.c .val = v, \ val 97 drivers/phy/qualcomm/phy-qcom-qmp.c .val = v, \ val 1004 drivers/phy/qualcomm/phy-qcom-qmp.c static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) val 1009 drivers/phy/qualcomm/phy-qcom-qmp.c reg |= val; val 1016 drivers/phy/qualcomm/phy-qcom-qmp.c static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) val 1021 drivers/phy/qualcomm/phy-qcom-qmp.c reg &= ~val; val 1292 drivers/phy/qualcomm/phy-qcom-qmp.c writel(t->val, base + regs[t->offset]); val 1294 drivers/phy/qualcomm/phy-qcom-qmp.c writel(t->val, base + t->offset); val 1373 drivers/phy/qualcomm/phy-qcom-qmp.c unsigned int mask, val; val 1382 drivers/phy/qualcomm/phy-qcom-qmp.c ret = readl_poll_timeout(status, val, (val & mask), 10, val 1452 drivers/phy/qualcomm/phy-qcom-qmp.c unsigned int mask, val, ready; val 1550 drivers/phy/qualcomm/phy-qcom-qmp.c ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, val 90 drivers/phy/qualcomm/phy-qcom-qusb2.c unsigned int val; val 101 drivers/phy/qualcomm/phy-qcom-qusb2.c .val = v, \ val 107 drivers/phy/qualcomm/phy-qcom-qusb2.c .val = v, \ val 338 drivers/phy/qualcomm/phy-qcom-qusb2.c u32 val, u32 mask) val 344 drivers/phy/qualcomm/phy-qcom-qusb2.c reg |= val & mask; val 351 drivers/phy/qualcomm/phy-qcom-qusb2.c static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) val 356 drivers/phy/qualcomm/phy-qcom-qusb2.c reg |= val; val 363 drivers/phy/qualcomm/phy-qcom-qusb2.c static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) val 368 drivers/phy/qualcomm/phy-qcom-qusb2.c reg &= ~val; val 384 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(tbl[i].val, base + regs[tbl[i].offset]); val 386 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(tbl[i].val, base + tbl[i].offset); val 435 drivers/phy/qualcomm/phy-qcom-qusb2.c u8 *val; val 448 drivers/phy/qualcomm/phy-qcom-qusb2.c val = nvmem_cell_read(qphy->cell, NULL); val 449 drivers/phy/qualcomm/phy-qcom-qusb2.c if (IS_ERR(val) || !val[0]) { val 457 drivers/phy/qualcomm/phy-qcom-qusb2.c val[0] << HSTX_TRIM_SHIFT, val 461 drivers/phy/qualcomm/phy-qcom-qusb2.c val[0] << HSTX_TRIM_SHIFT, val 597 drivers/phy/qualcomm/phy-qcom-qusb2.c unsigned int val = 0; val 643 drivers/phy/qualcomm/phy-qcom-qusb2.c val = readl(qphy->base + QUSB2PHY_PLL_TEST); val 700 drivers/phy/qualcomm/phy-qcom-qusb2.c val &= ~CLK_REF_SEL; val 702 drivers/phy/qualcomm/phy-qcom-qusb2.c val |= CLK_REF_SEL; val 704 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(val, qphy->base + QUSB2PHY_PLL_TEST); val 713 drivers/phy/qualcomm/phy-qcom-qusb2.c val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); val 714 drivers/phy/qualcomm/phy-qcom-qusb2.c if (!(val & cfg->mask_core_ready)) { val 716 drivers/phy/qualcomm/phy-qcom-qusb2.c "QUSB2PHY pll lock failed: status reg = %x\n", val); val 20 drivers/phy/qualcomm/phy-qcom-ufs-i.h #define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \ val 23 drivers/phy/qualcomm/phy-qcom-ufs-i.h .cfg_value = val, \ val 112 drivers/phy/qualcomm/phy-qcom-ufs-i.h void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val); val 113 drivers/phy/qualcomm/phy-qcom-ufs-i.h void (*power_control)(struct ufs_qcom_phy *phy, bool val); val 51 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val) val 53 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); val 62 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val) val 85 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c u32 val; val 88 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c val, (val & MASK_PCS_READY), 10, 1000000); val 70 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val) val 75 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c if (val) { val 122 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val) val 124 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK, val 143 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c u32 val; val 146 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c val, (val & MASK_PCS_READY), 10, 1000000); val 26 drivers/phy/qualcomm/phy-qcom-usb-hs.c u8 val; val 50 drivers/phy/qualcomm/phy-qcom-usb-hs.c u8 val = 0; val 55 drivers/phy/qualcomm/phy-qcom-usb-hs.c val |= ULPI_INT_IDGRD; val 58 drivers/phy/qualcomm/phy-qcom-usb-hs.c val |= ULPI_INT_SESS_VALID; val 63 drivers/phy/qualcomm/phy-qcom-usb-hs.c ret = ulpi_write(uphy->ulpi, ULPI_USB_INT_EN_RISE, val); val 66 drivers/phy/qualcomm/phy-qcom-usb-hs.c ret = ulpi_write(uphy->ulpi, ULPI_USB_INT_EN_FALL, val); val 145 drivers/phy/qualcomm/phy-qcom-usb-hs.c seq->val); val 229 drivers/phy/qualcomm/phy-qcom-usb-hs.c uphy->init_seq[size / 2].addr = uphy->init_seq[size / 2].val = 0; val 61 drivers/phy/ralink/phy-ralink-usb.c static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) val 63 drivers/phy/ralink/phy-ralink-usb.c writel(val, phy->base + reg); val 147 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val = readl(usb2_base + USB2_COMMCTRL); val 149 drivers/phy/renesas/phy-rcar-gen3-usb2.c dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, host); val 151 drivers/phy/renesas/phy-rcar-gen3-usb2.c val &= ~USB2_COMMCTRL_OTG_PERI; val 153 drivers/phy/renesas/phy-rcar-gen3-usb2.c val |= USB2_COMMCTRL_OTG_PERI; val 154 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_COMMCTRL); val 160 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val = readl(usb2_base + USB2_LINECTRL1); val 162 drivers/phy/renesas/phy-rcar-gen3-usb2.c dev_vdbg(ch->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm); val 163 drivers/phy/renesas/phy-rcar-gen3-usb2.c val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); val 165 drivers/phy/renesas/phy-rcar-gen3-usb2.c val |= USB2_LINECTRL1_DP_RPD; val 167 drivers/phy/renesas/phy-rcar-gen3-usb2.c val |= USB2_LINECTRL1_DM_RPD; val 168 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_LINECTRL1); val 174 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val = readl(usb2_base + USB2_ADPCTRL); val 176 drivers/phy/renesas/phy-rcar-gen3-usb2.c dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus); val 178 drivers/phy/renesas/phy-rcar-gen3-usb2.c val |= USB2_ADPCTRL_DRVVBUS; val 180 drivers/phy/renesas/phy-rcar-gen3-usb2.c val &= ~USB2_ADPCTRL_DRVVBUS; val 181 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_ADPCTRL); val 187 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val = readl(usb2_base + USB2_OBINTEN); val 190 drivers/phy/renesas/phy-rcar-gen3-usb2.c val |= USB2_OBINT_BITS; val 192 drivers/phy/renesas/phy-rcar-gen3-usb2.c val &= ~USB2_OBINT_BITS; val 193 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_OBINTEN); val 219 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val; val 221 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = readl(usb2_base + USB2_LINECTRL1); val 222 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val | USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1); val 228 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = readl(usb2_base + USB2_LINECTRL1); val 229 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val & ~USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1); val 370 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val; val 373 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = readl(usb2_base + USB2_LINECTRL1); val 374 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = (val & ~USB2_LINECTRL1_DP_RPD) | USB2_LINECTRL1_DPRPD_EN | val 376 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_LINECTRL1); val 378 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = readl(usb2_base + USB2_VBCTRL); val 379 drivers/phy/renesas/phy-rcar-gen3-usb2.c val &= ~USB2_VBCTRL_OCCLREN; val 380 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL); val 381 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = readl(usb2_base + USB2_ADPCTRL); val 382 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL); val 397 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val; val 400 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = readl(usb2_base + USB2_INT_ENABLE); val 401 drivers/phy/renesas/phy-rcar-gen3-usb2.c val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits; val 402 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_INT_ENABLE); val 423 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val; val 430 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = readl(usb2_base + USB2_INT_ENABLE); val 431 drivers/phy/renesas/phy-rcar-gen3-usb2.c val &= ~rphy->int_enable_bits; val 433 drivers/phy/renesas/phy-rcar-gen3-usb2.c val &= ~USB2_INT_ENABLE_UCOM_INTEN; val 434 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_INT_ENABLE); val 444 drivers/phy/renesas/phy-rcar-gen3-usb2.c u32 val; val 457 drivers/phy/renesas/phy-rcar-gen3-usb2.c val = readl(usb2_base + USB2_USBCTR); val 458 drivers/phy/renesas/phy-rcar-gen3-usb2.c val |= USB2_USBCTR_PLL_RST; val 459 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_USBCTR); val 460 drivers/phy/renesas/phy-rcar-gen3-usb2.c val &= ~USB2_USBCTR_PLL_RST; val 461 drivers/phy/renesas/phy-rcar-gen3-usb2.c writel(val, usb2_base + USB2_USBCTR); val 59 drivers/phy/renesas/phy-rcar-gen3-usb3.c u16 val = CLKSET1_USB30_PLL_MULTI_USB_EXTAL | val 63 drivers/phy/renesas/phy-rcar-gen3-usb3.c val |= CLKSET1_PHYRESET; val 65 drivers/phy/renesas/phy-rcar-gen3-usb3.c writew(val, r->base + USB30_CLKSET1); val 70 drivers/phy/renesas/phy-rcar-gen3-usb3.c u16 val = SSC_SET_SSC_EN; val 74 drivers/phy/renesas/phy-rcar-gen3-usb3.c val |= SSC_SET_RANGE_4980; val 77 drivers/phy/renesas/phy-rcar-gen3-usb3.c val |= SSC_SET_RANGE_4492; val 80 drivers/phy/renesas/phy-rcar-gen3-usb3.c val |= SSC_SET_RANGE_4003; val 88 drivers/phy/renesas/phy-rcar-gen3-usb3.c writew(val, r->base + USB30_SSC_SET); val 23 drivers/phy/rockchip/phy-rockchip-emmc.c #define HIWORD_UPDATE(val, mask, shift) \ val 24 drivers/phy/rockchip/phy-rockchip-emmc.c ((val) << (shift) | (mask) << ((shift) + 16)) val 338 drivers/phy/rockchip/phy-rockchip-emmc.c u32 val; val 363 drivers/phy/rockchip/phy-rockchip-emmc.c if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val)) val 364 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val); val 382 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) val 384 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_write(inno->regmap, reg * 4, val); val 389 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u32 val; val 391 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_read(inno->regmap, reg * 4, &val); val 393 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c return val; val 397 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u8 mask, u8 val) val 399 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_update_bits(inno->regmap, reg * 4, mask, val); val 402 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ val 403 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \ val 779 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u32 val; val 797 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE; val 799 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c val |= RK3328_PRE_PLL_FRAC_DIV_DISABLE; val 800 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); val 816 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, val 233 drivers/phy/rockchip/phy-rockchip-inno-usb2.c unsigned int val, mask, tmp; val 237 drivers/phy/rockchip/phy-rockchip-inno-usb2.c val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); val 239 drivers/phy/rockchip/phy-rockchip-inno-usb2.c return regmap_write(base, reg->offset, val); val 26 drivers/phy/rockchip/phy-rockchip-pcie.c #define HIWORD_UPDATE(val, mask, shift) \ val 27 drivers/phy/rockchip/phy-rockchip-pcie.c ((val) << (shift) | (mask) << ((shift) + 16)) val 125 drivers/phy/rockchip/phy-rockchip-pcie.c u32 val; val 133 drivers/phy/rockchip/phy-rockchip-pcie.c &val); val 134 drivers/phy/rockchip/phy-rockchip-pcie.c return val; val 564 drivers/phy/rockchip/phy-rockchip-typec.c u32 val = en << reg->enable_bit; val 566 drivers/phy/rockchip/phy-rockchip-typec.c return regmap_write(tcphy->grf_regs, reg->offset, val | mask); val 590 drivers/phy/rockchip/phy-rockchip-typec.c u16 val; val 601 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + CMN_TXPUCAL_CTRL); val 602 drivers/phy/rockchip/phy-rockchip-typec.c pu_calib_code = CMN_CALIB_CODE_POS(val); val 603 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + CMN_TXPDCAL_CTRL); val 604 drivers/phy/rockchip/phy-rockchip-typec.c pd_calib_code = CMN_CALIB_CODE_POS(val); val 605 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + CMN_TXPU_ADJ_CTRL); val 606 drivers/phy/rockchip/phy-rockchip-typec.c pu_adj = CMN_CALIB_CODE(val); val 607 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + CMN_TXPD_ADJ_CTRL); val 608 drivers/phy/rockchip/phy-rockchip-typec.c pd_adj = CMN_CALIB_CODE(val); val 617 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + TX_DIG_CTRL_REG_2); val 618 drivers/phy/rockchip/phy-rockchip-typec.c val &= ~(TX_RESCAL_CODE_MASK << TX_RESCAL_CODE_OFFSET); val 619 drivers/phy/rockchip/phy-rockchip-typec.c val |= calib << TX_RESCAL_CODE_OFFSET; val 620 drivers/phy/rockchip/phy-rockchip-typec.c writel(val, tcphy->base + TX_DIG_CTRL_REG_2); val 717 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + TX_DIG_CTRL_REG_2); val 718 drivers/phy/rockchip/phy-rockchip-typec.c val |= TX_HIGH_Z_TM_EN; val 719 drivers/phy/rockchip/phy-rockchip-typec.c writel(val, tcphy->base + TX_DIG_CTRL_REG_2); val 726 drivers/phy/rockchip/phy-rockchip-typec.c u32 val; val 776 drivers/phy/rockchip/phy-rockchip-typec.c val, val & CMN_READY, 10, val 872 drivers/phy/rockchip/phy-rockchip-typec.c u32 val; val 899 drivers/phy/rockchip/phy-rockchip-typec.c regmap_read(tcphy->grf_regs, reg->offset, &val); val 900 drivers/phy/rockchip/phy-rockchip-typec.c if (!(val & BIT(reg->enable_bit))) { val 950 drivers/phy/rockchip/phy-rockchip-typec.c u32 val; val 984 drivers/phy/rockchip/phy-rockchip-typec.c val, val & DP_MODE_A2, 1000, val 996 drivers/phy/rockchip/phy-rockchip-typec.c val, val & DP_MODE_A0, 1000, val 28 drivers/phy/rockchip/phy-rockchip-usb.c #define HIWORD_UPDATE(val, mask) \ val 29 drivers/phy/rockchip/phy-rockchip-usb.c ((val) | (mask) << 16) val 83 drivers/phy/rockchip/phy-rockchip-usb.c u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); val 85 drivers/phy/rockchip/phy-rockchip-usb.c return regmap_write(phy->base->reg_base, phy->reg_offset, val); val 123 drivers/phy/rockchip/phy-rockchip-usb.c u32 val; val 125 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); val 129 drivers/phy/rockchip/phy-rockchip-usb.c return (val & UOC_CON0_SIDDQ) ? 0 : 1; val 329 drivers/phy/rockchip/phy-rockchip-usb.c u32 val; val 336 drivers/phy/rockchip/phy-rockchip-usb.c val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N val 342 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_write(grf, regoffs + UOC_CON0, val); val 346 drivers/phy/rockchip/phy-rockchip-usb.c val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL, val 348 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_write(grf, regoffs + UOC_CON2, val); val 352 drivers/phy/rockchip/phy-rockchip-usb.c val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING val 359 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_write(grf, UOC_CON3, val); val 377 drivers/phy/rockchip/phy-rockchip-usb.c u32 val; val 384 drivers/phy/rockchip/phy-rockchip-usb.c val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL val 388 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_write(grf, RK3188_UOC0_CON0, val); val 427 drivers/phy/rockchip/phy-rockchip-usb.c u32 val; val 434 drivers/phy/rockchip/phy-rockchip-usb.c val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL val 438 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_write(grf, RK3288_UOC0_CON3, val); val 73 drivers/phy/samsung/phy-exynos-pcie.c static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) val 75 drivers/phy/samsung/phy-exynos-pcie.c writel(val, base + offset); val 134 drivers/phy/samsung/phy-exynos-pcie.c u32 val; val 141 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER); val 142 drivers/phy/samsung/phy-exynos-pcie.c val &= ~PCIE_PHY_COMMON_PD_CMN; val 143 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER); val 145 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER); val 146 drivers/phy/samsung/phy-exynos-pcie.c val &= ~PCIE_PHY_TRSV0_PD_TSV; val 147 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER); val 149 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER); val 150 drivers/phy/samsung/phy-exynos-pcie.c val &= ~PCIE_PHY_TRSV1_PD_TSV; val 151 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER); val 153 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER); val 154 drivers/phy/samsung/phy-exynos-pcie.c val &= ~PCIE_PHY_TRSV2_PD_TSV; val 155 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER); val 157 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER); val 158 drivers/phy/samsung/phy-exynos-pcie.c val &= ~PCIE_PHY_TRSV3_PD_TSV; val 159 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER); val 167 drivers/phy/samsung/phy-exynos-pcie.c u32 val; val 169 drivers/phy/samsung/phy-exynos-pcie.c if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val, val 170 drivers/phy/samsung/phy-exynos-pcie.c (val != 0), 1, 500)) { val 171 drivers/phy/samsung/phy-exynos-pcie.c dev_err(&phy->dev, "PLL Locked: 0x%x\n", val); val 175 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER); val 176 drivers/phy/samsung/phy-exynos-pcie.c val |= PCIE_PHY_COMMON_PD_CMN; val 177 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER); val 179 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER); val 180 drivers/phy/samsung/phy-exynos-pcie.c val |= PCIE_PHY_TRSV0_PD_TSV; val 181 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER); val 183 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER); val 184 drivers/phy/samsung/phy-exynos-pcie.c val |= PCIE_PHY_TRSV1_PD_TSV; val 185 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER); val 187 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER); val 188 drivers/phy/samsung/phy-exynos-pcie.c val |= PCIE_PHY_TRSV2_PD_TSV; val 189 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER); val 191 drivers/phy/samsung/phy-exynos-pcie.c val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER); val 192 drivers/phy/samsung/phy-exynos-pcie.c val |= PCIE_PHY_TRSV3_PD_TSV; val 193 drivers/phy/samsung/phy-exynos-pcie.c exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER); val 260 drivers/phy/samsung/phy-exynos5-usbdrd.c unsigned int val; val 265 drivers/phy/samsung/phy-exynos5-usbdrd.c val = on ? 0 : EXYNOS4_PHY_ENABLE; val 268 drivers/phy/samsung/phy-exynos5-usbdrd.c EXYNOS4_PHY_ENABLE, val); val 557 drivers/phy/samsung/phy-exynos5-usbdrd.c u32 val, u32 cmd) val 562 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); val 574 drivers/phy/samsung/phy-exynos5-usbdrd.c "CRPORT handshake timeout1 (0x%08x)\n", val); val 580 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); val 592 drivers/phy/samsung/phy-exynos5-usbdrd.c "CRPORT handshake timeout2 (0x%08x)\n", val); val 89 drivers/phy/samsung/phy-exynos5250-sata.c u32 val = 0; val 99 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); val 101 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); val 102 drivers/phy/samsung/phy-exynos5250-sata.c val |= RESET_GLOBAL_RST_N | RESET_CMN_RST_N | RESET_CMN_BLOCK_RST_N val 105 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); val 107 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); val 108 drivers/phy/samsung/phy-exynos5250-sata.c val |= LINK_RESET; val 109 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); val 111 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); val 112 drivers/phy/samsung/phy-exynos5250-sata.c val |= RESET_CMN_RST_N; val 113 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); val 115 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); val 116 drivers/phy/samsung/phy-exynos5250-sata.c val &= ~PHCTRLM_REF_RATE; val 117 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); val 120 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); val 121 drivers/phy/samsung/phy-exynos5250-sata.c val |= PHCTRLM_HIGH_SPEED; val 122 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); val 124 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0); val 125 drivers/phy/samsung/phy-exynos5250-sata.c val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED; val 126 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0); val 128 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_MODE0); val 129 drivers/phy/samsung/phy-exynos5250-sata.c val |= SATA_SPD_GEN3; val 130 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0); val 137 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); val 138 drivers/phy/samsung/phy-exynos5250-sata.c val &= ~RESET_CMN_RST_N; val 139 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); val 141 drivers/phy/samsung/phy-exynos5250-sata.c val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); val 142 drivers/phy/samsung/phy-exynos5250-sata.c val |= RESET_CMN_RST_N; val 143 drivers/phy/samsung/phy-exynos5250-sata.c writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); val 69 drivers/phy/socionext/phy-uniphier-pcie.c u32 val; val 72 drivers/phy/socionext/phy-uniphier-pcie.c val = FIELD_PREP(TESTI_DAT_MASK, 1); val 73 drivers/phy/socionext/phy-uniphier-pcie.c val |= FIELD_PREP(TESTI_ADR_MASK, reg); val 74 drivers/phy/socionext/phy-uniphier-pcie.c uniphier_pciephy_testio_write(priv, val); val 75 drivers/phy/socionext/phy-uniphier-pcie.c val = readl(priv->base + PCL_PHY_TEST_O); val 78 drivers/phy/socionext/phy-uniphier-pcie.c val &= ~FIELD_PREP(TESTI_DAT_MASK, mask); val 79 drivers/phy/socionext/phy-uniphier-pcie.c val = FIELD_PREP(TESTI_DAT_MASK, mask & param); val 80 drivers/phy/socionext/phy-uniphier-pcie.c val |= FIELD_PREP(TESTI_ADR_MASK, reg); val 81 drivers/phy/socionext/phy-uniphier-pcie.c uniphier_pciephy_testio_write(priv, val); val 82 drivers/phy/socionext/phy-uniphier-pcie.c uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN); val 83 drivers/phy/socionext/phy-uniphier-pcie.c uniphier_pciephy_testio_write(priv, val); val 86 drivers/phy/socionext/phy-uniphier-pcie.c val = FIELD_PREP(TESTI_DAT_MASK, 1); val 87 drivers/phy/socionext/phy-uniphier-pcie.c val |= FIELD_PREP(TESTI_ADR_MASK, reg); val 88 drivers/phy/socionext/phy-uniphier-pcie.c uniphier_pciephy_testio_write(priv, val); val 94 drivers/phy/socionext/phy-uniphier-pcie.c u32 val; val 96 drivers/phy/socionext/phy-uniphier-pcie.c val = readl(priv->base + PCL_PHY_RESET); val 97 drivers/phy/socionext/phy-uniphier-pcie.c val &= ~PCL_PHY_RESET_N; val 98 drivers/phy/socionext/phy-uniphier-pcie.c val |= PCL_PHY_RESET_N_MNMODE; val 99 drivers/phy/socionext/phy-uniphier-pcie.c writel(val, priv->base + PCL_PHY_RESET); val 104 drivers/phy/socionext/phy-uniphier-pcie.c u32 val; val 106 drivers/phy/socionext/phy-uniphier-pcie.c val = readl(priv->base + PCL_PHY_RESET); val 107 drivers/phy/socionext/phy-uniphier-pcie.c val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N; val 108 drivers/phy/socionext/phy-uniphier-pcie.c writel(val, priv->base + PCL_PHY_RESET); val 99 drivers/phy/socionext/phy-uniphier-usb3hs.c const char *name, unsigned int *val) val 112 drivers/phy/socionext/phy-uniphier-usb3hs.c *val = *buf; val 175 drivers/phy/socionext/phy-uniphier-usb3hs.c u32 val; val 179 drivers/phy/socionext/phy-uniphier-usb3hs.c val = readl(priv->base + HSPHY_CFG1); val 180 drivers/phy/socionext/phy-uniphier-usb3hs.c val &= ~HSPHY_CFG1_ADR_MASK; val 181 drivers/phy/socionext/phy-uniphier-usb3hs.c val |= FIELD_PREP(HSPHY_CFG1_ADR_MASK, p->field.reg_no) val 183 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(val, priv->base + HSPHY_CFG1); val 185 drivers/phy/socionext/phy-uniphier-usb3hs.c val = readl(priv->base + HSPHY_CFG1); val 186 drivers/phy/socionext/phy-uniphier-usb3hs.c val &= ~HSPHY_CFG1_ADR_EN; val 187 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(val, priv->base + HSPHY_CFG1); val 189 drivers/phy/socionext/phy-uniphier-usb3hs.c val = readl(priv->base + HSPHY_CFG1); val 190 drivers/phy/socionext/phy-uniphier-usb3hs.c val &= ~FIELD_PREP(HSPHY_CFG1_DAT_MASK, field_mask); val 192 drivers/phy/socionext/phy-uniphier-usb3hs.c val |= FIELD_PREP(HSPHY_CFG1_DAT_MASK, data) | HSPHY_CFG1_DAT_EN; val 193 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(val, priv->base + HSPHY_CFG1); val 195 drivers/phy/socionext/phy-uniphier-usb3hs.c val = readl(priv->base + HSPHY_CFG1); val 196 drivers/phy/socionext/phy-uniphier-usb3hs.c val &= ~HSPHY_CFG1_DAT_EN; val 197 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(val, priv->base + HSPHY_CFG1); val 79 drivers/phy/socionext/phy-uniphier-usb3ss.c u32 val; val 84 drivers/phy/socionext/phy-uniphier-usb3ss.c val = FIELD_PREP(TESTI_DAT_MASK, 1); val 85 drivers/phy/socionext/phy-uniphier-usb3ss.c val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); val 86 drivers/phy/socionext/phy-uniphier-usb3ss.c uniphier_u3ssphy_testio_write(priv, val); val 87 drivers/phy/socionext/phy-uniphier-usb3ss.c val = readl(priv->base + SSPHY_TESTO); val 90 drivers/phy/socionext/phy-uniphier-usb3ss.c val &= ~FIELD_PREP(TESTI_DAT_MASK, field_mask); val 92 drivers/phy/socionext/phy-uniphier-usb3ss.c val = FIELD_PREP(TESTI_DAT_MASK, data); val 93 drivers/phy/socionext/phy-uniphier-usb3ss.c val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); val 94 drivers/phy/socionext/phy-uniphier-usb3ss.c uniphier_u3ssphy_testio_write(priv, val); val 95 drivers/phy/socionext/phy-uniphier-usb3ss.c uniphier_u3ssphy_testio_write(priv, val | TESTI_WR_EN); val 96 drivers/phy/socionext/phy-uniphier-usb3ss.c uniphier_u3ssphy_testio_write(priv, val); val 99 drivers/phy/socionext/phy-uniphier-usb3ss.c val = FIELD_PREP(TESTI_DAT_MASK, 1); val 100 drivers/phy/socionext/phy-uniphier-usb3ss.c val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); val 101 drivers/phy/socionext/phy-uniphier-usb3ss.c uniphier_u3ssphy_testio_write(priv, val); val 232 drivers/phy/st/phy-miphy28lp.c u16 val; val 367 drivers/phy/st/phy-miphy28lp.c u8 val; val 372 drivers/phy/st/phy-miphy28lp.c val = RST_APPLI_SW | RST_CONF_SW; val 373 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONF_RESET); val 379 drivers/phy/st/phy-miphy28lp.c val = AUTO_RST_RX | TERM_EN_SW; val 380 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONTROL); val 382 drivers/phy/st/phy-miphy28lp.c val = AUTO_RST_RX | TERM_EN_SW | DIS_LINK_RST; val 383 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONTROL); val 391 drivers/phy/st/phy-miphy28lp.c u8 val; val 406 drivers/phy/st/phy-miphy28lp.c val = (0x68 << 1) | TX_SLEW_CAL_MAN_EN; val 407 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_TX_CAL_MAN); val 409 drivers/phy/st/phy-miphy28lp.c val = VGA_OFFSET_POLARITY | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64; val 412 drivers/phy/st/phy-miphy28lp.c val |= OFFSET_COMPENSATION_EN; val 414 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); val 423 drivers/phy/st/phy-miphy28lp.c val = EN_DIGIT_SIGNAL_CHECK | EN_FIRST_HALF; val 424 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL); val 488 drivers/phy/st/phy-miphy28lp.c u8 val; val 492 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); val 497 drivers/phy/st/phy-miphy28lp.c } while (!(val & COMP_DONE)); val 535 drivers/phy/st/phy-miphy28lp.c u8 val; val 542 drivers/phy/st/phy-miphy28lp.c val = RST_COMP_SW | RST_PLL_SW; val 543 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RESET); val 563 drivers/phy/st/phy-miphy28lp.c u8 val; val 570 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(base + MIPHY_BOUNDARY_2); val 571 drivers/phy/st/phy-miphy28lp.c val |= SSC_EN_SW; val 572 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_2); val 574 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); val 575 drivers/phy/st/phy-miphy28lp.c val |= SSC_SEL; val 576 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); val 578 drivers/phy/st/phy-miphy28lp.c for (val = 0; val < MIPHY_SATA_BANK_NB; val++) { val 579 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONF); val 601 drivers/phy/st/phy-miphy28lp.c u8 val; val 608 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(base + MIPHY_BOUNDARY_2); val 609 drivers/phy/st/phy-miphy28lp.c val |= SSC_EN_SW; val 610 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_2); val 612 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); val 613 drivers/phy/st/phy-miphy28lp.c val |= SSC_SEL; val 614 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); val 616 drivers/phy/st/phy-miphy28lp.c for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) { val 617 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONF); val 648 drivers/phy/st/phy-miphy28lp.c u8 val; val 674 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL); val 675 drivers/phy/st/phy-miphy28lp.c val |= PX_RX_POL; val 676 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); val 728 drivers/phy/st/phy-miphy28lp.c u8 val; val 739 drivers/phy/st/phy-miphy28lp.c val = RX_SPDSEL_20DEC | TX_SPDSEL_20DEC; val 740 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_SPEED); val 747 drivers/phy/st/phy-miphy28lp.c val = OFFSET_COMPENSATION_EN | VGA_OFFSET_POLARITY | val 749 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); val 753 drivers/phy/st/phy-miphy28lp.c val = EQ_DC_GAIN | VGA_GAIN; val 754 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL); val 763 drivers/phy/st/phy-miphy28lp.c val = SSC_SEL | GENSEL_SEL; val 764 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); val 810 drivers/phy/st/phy-miphy28lp.c u8 val; val 820 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); val 821 drivers/phy/st/phy-miphy28lp.c if ((val & mask) != mask) val 834 drivers/phy/st/phy-miphy28lp.c u32 val; val 844 drivers/phy/st/phy-miphy28lp.c miphy_phy->syscfg_reg[SYSCFG_STATUS], &val); val 846 drivers/phy/st/phy-miphy28lp.c if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY) val 113 drivers/phy/st/phy-spear1310-miphy.c u32 val; val 121 drivers/phy/st/phy-spear1310-miphy.c val = SPEAR1310_PCIE_CFG_VAL(0); val 124 drivers/phy/st/phy-spear1310-miphy.c val = SPEAR1310_PCIE_CFG_VAL(1); val 127 drivers/phy/st/phy-spear1310-miphy.c val = SPEAR1310_PCIE_CFG_VAL(2); val 134 drivers/phy/st/phy-spear1310-miphy.c SPEAR1310_PCIE_CFG_MASK(priv->id), val); val 45 drivers/phy/tegra/phy-tegra194-p2u.c u32 val; val 47 drivers/phy/tegra/phy-tegra194-p2u.c val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3); val 48 drivers/phy/tegra/phy-tegra194-p2u.c val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN; val 49 drivers/phy/tegra/phy-tegra194-p2u.c val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN; val 50 drivers/phy/tegra/phy-tegra194-p2u.c p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3); val 52 drivers/phy/tegra/phy-tegra194-p2u.c val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4); val 53 drivers/phy/tegra/phy-tegra194-p2u.c val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN; val 54 drivers/phy/tegra/phy-tegra194-p2u.c p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN4); val 56 drivers/phy/tegra/phy-tegra194-p2u.c val = p2u_readl(phy, P2U_RX_DEBOUNCE_TIME); val 57 drivers/phy/tegra/phy-tegra194-p2u.c val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK; val 58 drivers/phy/tegra/phy-tegra194-p2u.c val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL; val 59 drivers/phy/tegra/phy-tegra194-p2u.c p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME); val 116 drivers/phy/ti/phy-am654-serdes.c u32 val; val 122 drivers/phy/ti/phy-am654-serdes.c return regmap_field_read_poll_timeout(phy->pll_ok, val, val, 1000, val 175 drivers/phy/ti/phy-am654-serdes.c u32 val; val 189 drivers/phy/ti/phy-am654-serdes.c return regmap_field_read_poll_timeout(phy->cmu_ok_i_0, val, val, val 325 drivers/phy/ti/phy-am654-serdes.c unsigned int val; val 327 drivers/phy/ti/phy-am654-serdes.c regmap_read(regmap, reg, &val); val 328 drivers/phy/ti/phy-am654-serdes.c val &= AM654_SERDES_CTRL_CLKSEL_MASK; val 329 drivers/phy/ti/phy-am654-serdes.c val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT; val 331 drivers/phy/ti/phy-am654-serdes.c return serdes_am654_mux_table[val][mux->clk_id]; val 343 drivers/phy/ti/phy-am654-serdes.c u32 val; val 348 drivers/phy/ti/phy-am654-serdes.c regmap_read(regmap, reg, &val); val 349 drivers/phy/ti/phy-am654-serdes.c val &= AM654_SERDES_CTRL_CLKSEL_MASK; val 350 drivers/phy/ti/phy-am654-serdes.c val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT; val 353 drivers/phy/ti/phy-am654-serdes.c parents[i] = serdes_am654_mux_table[val][i]; val 359 drivers/phy/ti/phy-am654-serdes.c for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) { val 360 drivers/phy/ti/phy-am654-serdes.c p = serdes_am654_mux_table[val]; val 382 drivers/phy/ti/phy-am654-serdes.c val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT; val 384 drivers/phy/ti/phy-am654-serdes.c val); val 92 drivers/phy/ti/phy-da8xx-usb.c u32 val; val 96 drivers/phy/ti/phy-da8xx-usb.c val = CFGCHIP2_OTGMODE_FORCE_HOST; val 99 drivers/phy/ti/phy-da8xx-usb.c val = CFGCHIP2_OTGMODE_FORCE_DEVICE; val 102 drivers/phy/ti/phy-da8xx-usb.c val = CFGCHIP2_OTGMODE_NO_OVERRIDE; val 109 drivers/phy/ti/phy-da8xx-usb.c val); val 84 drivers/phy/ti/phy-dm816x-usb.c unsigned int val; val 96 drivers/phy/ti/phy-dm816x-usb.c regmap_read(phy->syscon, phy->usb_ctrl, &val); val 97 drivers/phy/ti/phy-dm816x-usb.c if ((val & 3) != 0) val 100 drivers/phy/ti/phy-dm816x-usb.c val); val 107 drivers/phy/ti/phy-dm816x-usb.c regmap_read(phy->syscon, phy->usbphy_ctrl, &val); val 108 drivers/phy/ti/phy-dm816x-usb.c val |= DM816X_USBPHY_CTRL_TXRISETUNE | val 111 drivers/phy/ti/phy-dm816x-usb.c regmap_write(phy->syscon, phy->usbphy_ctrl, val); val 124 drivers/phy/ti/phy-dm816x-usb.c unsigned int mask, val; val 128 drivers/phy/ti/phy-dm816x-usb.c val = ~BIT(phy->instance); val 130 drivers/phy/ti/phy-dm816x-usb.c mask, val); val 142 drivers/phy/ti/phy-dm816x-usb.c unsigned int mask, val; val 156 drivers/phy/ti/phy-dm816x-usb.c val = BIT(phy->instance); val 158 drivers/phy/ti/phy-dm816x-usb.c mask, val); val 26 drivers/phy/ti/phy-omap-control.c u32 val; val 45 drivers/phy/ti/phy-omap-control.c val = readl(control_phy->pcie_pcs); val 46 drivers/phy/ti/phy-omap-control.c val &= ~(OMAP_CTRL_PCIE_PCS_MASK << val 48 drivers/phy/ti/phy-omap-control.c val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT); val 49 drivers/phy/ti/phy-omap-control.c writel(val, control_phy->pcie_pcs); val 60 drivers/phy/ti/phy-omap-control.c u32 val; val 78 drivers/phy/ti/phy-omap-control.c val = readl(control_phy->power); val 83 drivers/phy/ti/phy-omap-control.c val &= ~OMAP_CTRL_DEV_PHY_PD; val 85 drivers/phy/ti/phy-omap-control.c val |= OMAP_CTRL_DEV_PHY_PD; val 94 drivers/phy/ti/phy-omap-control.c val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | val 96 drivers/phy/ti/phy-omap-control.c val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << val 98 drivers/phy/ti/phy-omap-control.c val |= rate << val 101 drivers/phy/ti/phy-omap-control.c val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; val 102 drivers/phy/ti/phy-omap-control.c val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << val 109 drivers/phy/ti/phy-omap-control.c val &= ~OMAP_CTRL_USB2_PHY_PD; val 111 drivers/phy/ti/phy-omap-control.c val |= OMAP_CTRL_USB2_PHY_PD; val 116 drivers/phy/ti/phy-omap-control.c val &= ~(AM437X_CTRL_USB2_PHY_PD | val 118 drivers/phy/ti/phy-omap-control.c val |= (AM437X_CTRL_USB2_OTGVDET_EN | val 121 drivers/phy/ti/phy-omap-control.c val &= ~(AM437X_CTRL_USB2_OTGVDET_EN | val 123 drivers/phy/ti/phy-omap-control.c val |= (AM437X_CTRL_USB2_PHY_PD | val 133 drivers/phy/ti/phy-omap-control.c writel(val, control_phy->power); val 146 drivers/phy/ti/phy-omap-control.c u32 val; val 148 drivers/phy/ti/phy-omap-control.c val = readl(ctrl_phy->otghs_control); val 149 drivers/phy/ti/phy-omap-control.c val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND); val 150 drivers/phy/ti/phy-omap-control.c val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID; val 151 drivers/phy/ti/phy-omap-control.c writel(val, ctrl_phy->otghs_control); val 164 drivers/phy/ti/phy-omap-control.c u32 val; val 166 drivers/phy/ti/phy-omap-control.c val = readl(ctrl_phy->otghs_control); val 167 drivers/phy/ti/phy-omap-control.c val &= ~OMAP_CTRL_DEV_SESSEND; val 168 drivers/phy/ti/phy-omap-control.c val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID | val 170 drivers/phy/ti/phy-omap-control.c writel(val, ctrl_phy->otghs_control); val 183 drivers/phy/ti/phy-omap-control.c u32 val; val 185 drivers/phy/ti/phy-omap-control.c val = readl(ctrl_phy->otghs_control); val 186 drivers/phy/ti/phy-omap-control.c val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID); val 187 drivers/phy/ti/phy-omap-control.c val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND; val 188 drivers/phy/ti/phy-omap-control.c writel(val, ctrl_phy->otghs_control); val 98 drivers/phy/ti/phy-omap-usb2.c u32 val; val 107 drivers/phy/ti/phy-omap-usb2.c val = phy->power_on; val 109 drivers/phy/ti/phy-omap-usb2.c val = phy->power_off; val 112 drivers/phy/ti/phy-omap-usb2.c phy->mask, val); val 169 drivers/phy/ti/phy-omap-usb2.c u32 val; val 182 drivers/phy/ti/phy-omap-usb2.c val = omap_usb_readl(phy->phy_base, USB2PHY_ANA_CONFIG1); val 183 drivers/phy/ti/phy-omap-usb2.c val |= USB2PHY_DISCON_BYP_LATCH; val 184 drivers/phy/ti/phy-omap-usb2.c omap_usb_writel(phy->phy_base, USB2PHY_ANA_CONFIG1, val); val 338 drivers/phy/ti/phy-ti-pipe3.c u32 val; val 357 drivers/phy/ti/phy-ti-pipe3.c val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; val 359 drivers/phy/ti/phy-ti-pipe3.c mask, val); val 366 drivers/phy/ti/phy-ti-pipe3.c val = PIPE3_PHY_TX_POWERON; val 369 drivers/phy/ti/phy-ti-pipe3.c val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; val 373 drivers/phy/ti/phy-ti-pipe3.c mask, val); val 376 drivers/phy/ti/phy-ti-pipe3.c val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; val 378 drivers/phy/ti/phy-ti-pipe3.c mask, val); val 389 drivers/phy/ti/phy-ti-pipe3.c u32 val; val 395 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); val 396 drivers/phy/ti/phy-ti-pipe3.c if (val & PLL_LOCK) val 406 drivers/phy/ti/phy-ti-pipe3.c u32 val; val 413 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); val 414 drivers/phy/ti/phy-ti-pipe3.c val &= ~PLL_REGN_MASK; val 415 drivers/phy/ti/phy-ti-pipe3.c val |= dpll_params->n << PLL_REGN_SHIFT; val 416 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); val 418 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); val 419 drivers/phy/ti/phy-ti-pipe3.c val &= ~PLL_SELFREQDCO_MASK; val 420 drivers/phy/ti/phy-ti-pipe3.c val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; val 421 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); val 423 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); val 424 drivers/phy/ti/phy-ti-pipe3.c val &= ~PLL_REGM_MASK; val 425 drivers/phy/ti/phy-ti-pipe3.c val |= dpll_params->m << PLL_REGM_SHIFT; val 426 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); val 428 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); val 429 drivers/phy/ti/phy-ti-pipe3.c val &= ~PLL_REGM_F_MASK; val 430 drivers/phy/ti/phy-ti-pipe3.c val |= dpll_params->mf << PLL_REGM_F_SHIFT; val 431 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); val 433 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); val 434 drivers/phy/ti/phy-ti-pipe3.c val &= ~PLL_SD_MASK; val 435 drivers/phy/ti/phy-ti-pipe3.c val |= dpll_params->sd << PLL_SD_SHIFT; val 436 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); val 445 drivers/phy/ti/phy-ti-pipe3.c u32 val; val 448 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY); val 449 drivers/phy/ti/phy-ti-pipe3.c val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV); val 450 drivers/phy/ti/phy-ti-pipe3.c val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT); val 451 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val); val 453 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES); val 454 drivers/phy/ti/phy-ti-pipe3.c val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK | val 457 drivers/phy/ti/phy-ti-pipe3.c val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT | val 466 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val); val 468 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM); val 469 drivers/phy/ti/phy-ti-pipe3.c val &= ~MEM_DLL_TRIM_SEL_MASK; val 470 drivers/phy/ti/phy-ti-pipe3.c val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT; val 471 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val); val 473 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL); val 474 drivers/phy/ti/phy-ti-pipe3.c val &= ~MEM_DLL_PHINT_RATE_MASK; val 475 drivers/phy/ti/phy-ti-pipe3.c val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT; val 476 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val); val 478 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER); val 479 drivers/phy/ti/phy-ti-pipe3.c val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK | val 481 drivers/phy/ti/phy-ti-pipe3.c val |= s->eq_lev << MEM_EQLEV_SHIFT | val 486 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val); val 489 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->phy_rx, val 491 drivers/phy/ti/phy-ti-pipe3.c val &= ~MEM_CDR_LOS_SOURCE_MASK; val 493 drivers/phy/ti/phy-ti-pipe3.c val); val 500 drivers/phy/ti/phy-ti-pipe3.c u32 val; val 515 drivers/phy/ti/phy-ti-pipe3.c val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; val 517 drivers/phy/ti/phy-ti-pipe3.c PCIE_PCS_MASK, val); val 522 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); val 523 drivers/phy/ti/phy-ti-pipe3.c if (val & PLL_IDLE) { val 524 drivers/phy/ti/phy-ti-pipe3.c val &= ~PLL_IDLE; val 525 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); val 530 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); val 531 drivers/phy/ti/phy-ti-pipe3.c if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) val 549 drivers/phy/ti/phy-ti-pipe3.c u32 val; val 561 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); val 562 drivers/phy/ti/phy-ti-pipe3.c val |= PLL_IDLE; val 563 drivers/phy/ti/phy-ti-pipe3.c ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); val 569 drivers/phy/ti/phy-ti-pipe3.c val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); val 570 drivers/phy/ti/phy-ti-pipe3.c if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) val 574 drivers/phy/ti/phy-ti-pipe3.c if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { val 576 drivers/phy/ti/phy-ti-pipe3.c val); val 96 drivers/phy/ti/phy-tusb1210.c u8 val, reg; val 122 drivers/phy/ti/phy-tusb1210.c device_property_read_u8(&ulpi->dev, "ihstx", &val); val 123 drivers/phy/ti/phy-tusb1210.c reg = val << TUSB1210_VENDOR_SPECIFIC2_IHSTX_SHIFT; val 126 drivers/phy/ti/phy-tusb1210.c device_property_read_u8(&ulpi->dev, "zhsdrv", &val); val 127 drivers/phy/ti/phy-tusb1210.c reg |= val << TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_SHIFT; val 130 drivers/phy/ti/phy-tusb1210.c device_property_read_u8(&ulpi->dev, "datapolarity", &val); val 131 drivers/phy/ti/phy-tusb1210.c reg |= val << TUSB1210_VENDOR_SPECIFIC2_DP_SHIFT; val 348 drivers/phy/ti/phy-twl4030-usb.c int val = twl4030_usb_read(twl, PHY_CLK_CTRL); val 350 drivers/phy/ti/phy-twl4030-usb.c if (val >= 0) { val 353 drivers/phy/ti/phy-twl4030-usb.c val |= REQ_PHY_DPLL_CLK; val 355 drivers/phy/ti/phy-twl4030-usb.c (u8)val) < 0); val 368 drivers/phy/ti/phy-twl4030-usb.c val &= ~REQ_PHY_DPLL_CLK; val 370 drivers/phy/ti/phy-twl4030-usb.c (u8)val) < 0); val 778 drivers/phy/ti/phy-twl4030-usb.c int val; val 800 drivers/phy/ti/phy-twl4030-usb.c val = twl4030_usb_read(twl, PHY_CLK_CTRL); val 801 drivers/phy/ti/phy-twl4030-usb.c if (val >= 0) { val 802 drivers/phy/ti/phy-twl4030-usb.c val |= PHY_CLK_CTRL_CLOCKGATING_EN; val 803 drivers/phy/ti/phy-twl4030-usb.c val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK); val 804 drivers/phy/ti/phy-twl4030-usb.c twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val); val 54 drivers/pinctrl/actions/pinctrl-owl.c static void owl_update_bits(void __iomem *base, u32 mask, u32 val) val 60 drivers/pinctrl/actions/pinctrl-owl.c reg_val = (reg_val & ~mask) | (val & mask); val 164 drivers/pinctrl/actions/pinctrl-owl.c u32 *val) val 183 drivers/pinctrl/actions/pinctrl-owl.c *val = (id << g->mfpctl_shift); val 195 drivers/pinctrl/actions/pinctrl-owl.c u32 val, mask; val 199 drivers/pinctrl/actions/pinctrl-owl.c if (get_group_mfp_mask_val(g, function, &mask, &val)) val 204 drivers/pinctrl/actions/pinctrl-owl.c owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val); val 519 drivers/pinctrl/actions/pinctrl-owl.c u32 val; val 521 drivers/pinctrl/actions/pinctrl-owl.c val = readl_relaxed(base); val 524 drivers/pinctrl/actions/pinctrl-owl.c val |= BIT(pin); val 526 drivers/pinctrl/actions/pinctrl-owl.c val &= ~BIT(pin); val 528 drivers/pinctrl/actions/pinctrl-owl.c writel_relaxed(val, base); val 583 drivers/pinctrl/actions/pinctrl-owl.c u32 val; val 592 drivers/pinctrl/actions/pinctrl-owl.c val = readl_relaxed(gpio_base + port->dat); val 595 drivers/pinctrl/actions/pinctrl-owl.c return !!(val & BIT(offset)); val 726 drivers/pinctrl/actions/pinctrl-owl.c u32 val; val 739 drivers/pinctrl/actions/pinctrl-owl.c val = readl_relaxed(gpio_base + port->intc_msk); val 740 drivers/pinctrl/actions/pinctrl-owl.c if (val == 0) val 2554 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c u32 val = (pattern << __ffs(desc->mask)); val 2581 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c desc->mask, val); val 2722 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c u32 val = (pattern << __ffs(desc->mask)); val 2756 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c u32 value = ~val & desc->mask; val 2767 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c desc->mask, val); val 2256 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c u32 val = (pattern << __ffs(desc->mask)); val 2276 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c u32 clear = ~val & desc->mask; val 2286 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c desc->mask, val); val 427 drivers/pinctrl/aspeed/pinctrl-aspeed.c u32 val; val 463 drivers/pinctrl/aspeed/pinctrl-aspeed.c match = (elem->val == value); val 481 drivers/pinctrl/aspeed/pinctrl-aspeed.c unsigned int val; val 490 drivers/pinctrl/aspeed/pinctrl-aspeed.c rc = regmap_read(pdata->scu, pconf->reg, &val); val 495 drivers/pinctrl/aspeed/pinctrl-aspeed.c (val & BIT(pconf->bit)) >> pconf->bit); val 528 drivers/pinctrl/aspeed/pinctrl-aspeed.c unsigned int val; val 543 drivers/pinctrl/aspeed/pinctrl-aspeed.c val = pmap->val << pconf->bit; val 546 drivers/pinctrl/aspeed/pinctrl-aspeed.c BIT(pconf->bit), val); val 552 drivers/pinctrl/aspeed/pinctrl-aspeed.c __func__, pconf->reg, pconf->bit, pmap->val, val 487 drivers/pinctrl/aspeed/pinmux-aspeed.h #define SIG_DESC_IP_BIT(ip, reg, idx, val) \ val 488 drivers/pinctrl/aspeed/pinmux-aspeed.h { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) } val 498 drivers/pinctrl/aspeed/pinmux-aspeed.h #define SIG_DESC_BIT(reg, idx, val) \ val 499 drivers/pinctrl/aspeed/pinmux-aspeed.h SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val) val 1104 drivers/pinctrl/bcm/pinctrl-bcm281xx.c u32 *val, val 1119 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, val 1130 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, val 1133 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, val 1139 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 1, val 1142 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, val 1148 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, val 1151 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 1, val 1158 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, val 1166 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, val 1181 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, (arg/2)-1, val 1220 drivers/pinctrl/bcm/pinctrl-bcm281xx.c u32 *val, val 1247 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, j+1, val 1253 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, val 1260 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, val 1268 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, val 1290 drivers/pinctrl/bcm/pinctrl-bcm281xx.c u32 *val, val 1305 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, val 1313 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, val 241 drivers/pinctrl/bcm/pinctrl-bcm2835.c u32 val) val 243 drivers/pinctrl/bcm/pinctrl-bcm2835.c writel(val, pc->base + reg); val 264 drivers/pinctrl/bcm/pinctrl-bcm2835.c u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); val 265 drivers/pinctrl/bcm/pinctrl-bcm2835.c enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; val 267 drivers/pinctrl/bcm/pinctrl-bcm2835.c dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, val 277 drivers/pinctrl/bcm/pinctrl-bcm2835.c u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); val 278 drivers/pinctrl/bcm/pinctrl-bcm2835.c enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; val 280 drivers/pinctrl/bcm/pinctrl-bcm2835.c dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, val 288 drivers/pinctrl/bcm/pinctrl-bcm2835.c val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); val 289 drivers/pinctrl/bcm/pinctrl-bcm2835.c val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); val 291 drivers/pinctrl/bcm/pinctrl-bcm2835.c dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, val 293 drivers/pinctrl/bcm/pinctrl-bcm2835.c bcm2835_gpio_wr(pc, FSEL_REG(pin), val); val 296 drivers/pinctrl/bcm/pinctrl-bcm2835.c val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); val 297 drivers/pinctrl/bcm/pinctrl-bcm2835.c val |= fsel << FSEL_SHIFT(pin); val 299 drivers/pinctrl/bcm/pinctrl-bcm2835.c dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, val 301 drivers/pinctrl/bcm/pinctrl-bcm2835.c bcm2835_gpio_wr(pc, FSEL_REG(pin), val); val 782 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c u32 val, mask = 0x7; val 820 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c val = readl(pinctrl->base0 + grp->mux.offset); val 821 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c val &= ~(mask << grp->mux.shift); val 822 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c val |= grp->mux.alt << grp->mux.shift; val 823 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c writel(val, pinctrl->base0 + grp->mux.offset); val 853 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c u32 val; val 862 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c val = readl(pinctrl->base1 + mux->offset); val 863 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c val |= 0x3 << mux->shift; val 864 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c writel(val, pinctrl->base1 + mux->offset); val 881 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c u32 val; val 889 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c val = readl(pinctrl->base1 + mux->offset); val 890 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c val &= ~(0x3 << mux->shift); val 891 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c writel(val, pinctrl->base1 + mux->offset); val 144 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c u32 val; val 146 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val = readl(chip->base + offset); val 148 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val |= BIT(shift); val 150 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val &= ~BIT(shift); val 151 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(val, chip->base + offset); val 174 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + val 177 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { val 204 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c u32 val = BIT(shift); val 206 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(val, chip->base + offset); val 339 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c int val) val 346 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); val 349 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); val 363 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) val 369 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); val 372 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); val 549 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c u32 val; val 571 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val = readl(base + offset); val 572 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val &= ~BIT(shift); val 573 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val |= ((strength >> i) & 0x1) << shift; val 574 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(val, base + offset); val 586 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c u32 val; val 601 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val = readl(base + offset) & BIT(shift); val 602 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val >>= shift; val 603 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c *strength += (val << i); val 578 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val, mask; val 627 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = readl(base_address + grp->mux.offset); val 628 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val &= ~(mask << grp->mux.shift); val 629 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val |= grp->mux.alt << grp->mux.shift; val 630 drivers/pinctrl/bcm/pinctrl-ns2-mux.c writel(val, (base_address + grp->mux.offset)); val 665 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val; val 670 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = readl(base_address + pin_data->pin_conf.offset); val 671 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en); val 674 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en; val 676 drivers/pinctrl/bcm/pinctrl-ns2-mux.c writel(val, (base_address + pin_data->pin_conf.offset)); val 711 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val; val 716 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = readl(base_address + pin_data->pin_conf.offset); val 717 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift); val 720 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift; val 722 drivers/pinctrl/bcm/pinctrl-ns2-mux.c writel(val, (base_address + pin_data->pin_conf.offset)); val 735 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val; val 738 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); val 739 drivers/pinctrl/bcm/pinctrl-ns2-mux.c *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK; val 752 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val; val 757 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = readl(base_address + pin_data->pin_conf.offset); val 758 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift); val 761 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift; val 763 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift; val 764 drivers/pinctrl/bcm/pinctrl-ns2-mux.c writel(val, (base_address + pin_data->pin_conf.offset)); val 779 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val; val 782 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); val 783 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK; val 787 drivers/pinctrl/bcm/pinctrl-ns2-mux.c if (val == NS2_PIN_PULL_UP) val 790 drivers/pinctrl/bcm/pinctrl-ns2-mux.c if (val == NS2_PIN_PULL_DOWN) val 800 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val; val 810 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = readl(base_address + pin_data->pin_conf.offset); val 811 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift); val 812 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift; val 813 drivers/pinctrl/bcm/pinctrl-ns2-mux.c writel(val, (base_address + pin_data->pin_conf.offset)); val 826 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val; val 830 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); val 831 drivers/pinctrl/bcm/pinctrl-ns2-mux.c *strength = (val >> pin_data->pin_conf.drive_shift) & val 107 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c u32 val; val 115 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val = readl(base_address + reg); val 117 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val |= BIT(gpio); val 119 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val &= ~BIT(gpio); val 121 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c writel(val, base_address + reg); val 176 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c u32 val = BIT(gpio); val 181 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val); val 292 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c int val) val 299 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); val 302 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); val 306 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) val 312 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); val 315 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); val 394 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c u32 val; val 408 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val = readl(chip->io_ctrl + offset); val 409 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val &= ~BIT(shift); val 410 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val |= ((strength >> (i-1)) & 0x1) << shift; val 411 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c writel(val, chip->io_ctrl + offset); val 423 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c u32 val; val 433 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val = readl(chip->io_ctrl + offset) & BIT(shift); val 434 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val >>= shift; val 435 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c *strength += (val << i); val 619 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c u32 val, count; val 622 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) { val 652 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c gc->ngpio = val; val 694 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val = readl(chip->base + NSP_CHIP_A_INT_MASK); val 695 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val = val | NSP_CHIP_A_GPIO_INT_BIT; val 696 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c writel(val, (chip->base + NSP_CHIP_A_INT_MASK)); val 395 drivers/pinctrl/bcm/pinctrl-nsp-mux.c u32 val, mask; val 447 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val = readl(base_address); val 448 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val &= ~(mask << grp->mux.shift); val 449 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val |= grp->mux.alt << grp->mux.shift; val 450 drivers/pinctrl/bcm/pinctrl-nsp-mux.c writel(val, base_address); val 486 drivers/pinctrl/bcm/pinctrl-nsp-mux.c u32 val; val 490 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val = readl(pinctrl->base0); val 491 drivers/pinctrl/bcm/pinctrl-nsp-mux.c if ((val & BIT(pin)) != (*gpio_select << pin)) { val 492 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val &= ~BIT(pin); val 493 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val |= *gpio_select << pin; val 494 drivers/pinctrl/bcm/pinctrl-nsp-mux.c writel(val, pinctrl->base0); val 507 drivers/pinctrl/bcm/pinctrl-nsp-mux.c u32 val; val 511 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val = readl(pinctrl->base0); val 512 drivers/pinctrl/bcm/pinctrl-nsp-mux.c if ((val & (1 << pin)) == (*gpio_select << pin)) { val 513 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val &= ~(1 << pin); val 515 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val |= (1 << pin); val 516 drivers/pinctrl/bcm/pinctrl-nsp-mux.c writel(val, pinctrl->base0); val 160 drivers/pinctrl/berlin/berlin.c u32 mask, val; val 167 drivers/pinctrl/berlin/berlin.c val = function_desc->muxval << group_desc->lsb; val 168 drivers/pinctrl/berlin/berlin.c regmap_update_bits(pctrl->regmap, group_desc->offset, mask, val); val 796 drivers/pinctrl/cirrus/pinctrl-lochnagar.c unsigned int val; val 801 drivers/pinctrl/cirrus/pinctrl-lochnagar.c ret = regmap_read(regmap, LOCHNAGAR2_GPIO_CHANNEL1 + i, &val); val 805 drivers/pinctrl/cirrus/pinctrl-lochnagar.c val &= LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK; val 807 drivers/pinctrl/cirrus/pinctrl-lochnagar.c if (val == op) val 810 drivers/pinctrl/cirrus/pinctrl-lochnagar.c if (free < 0 && !val) val 991 drivers/pinctrl/cirrus/pinctrl-lochnagar.c unsigned int val = 0; val 998 drivers/pinctrl/cirrus/pinctrl-lochnagar.c val = aif->master_mask; val 1003 drivers/pinctrl/cirrus/pinctrl-lochnagar.c ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val); val 680 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int val; val 684 drivers/pinctrl/cirrus/pinctrl-madera-core.c val = MADERA_GP1_DIR; val 686 drivers/pinctrl/cirrus/pinctrl-madera-core.c val = 0; val 688 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_DIR_MASK, val); val 826 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int val; val 860 drivers/pinctrl/cirrus/pinctrl-madera-core.c val = pinconf_to_config_argument(*configs); val 863 drivers/pinctrl/cirrus/pinctrl-madera-core.c conf[1] |= madera_pin_make_drv_str(priv, val); val 872 drivers/pinctrl/cirrus/pinctrl-madera-core.c val = pinconf_to_config_argument(*configs); val 873 drivers/pinctrl/cirrus/pinctrl-madera-core.c if (val) val 879 drivers/pinctrl/cirrus/pinctrl-madera-core.c val = pinconf_to_config_argument(*configs); val 881 drivers/pinctrl/cirrus/pinctrl-madera-core.c if (val) val 887 drivers/pinctrl/cirrus/pinctrl-madera-core.c val = pinconf_to_config_argument(*configs); val 889 drivers/pinctrl/cirrus/pinctrl-madera-core.c if (val) val 904 drivers/pinctrl/cirrus/pinctrl-madera-core.c val = pinconf_to_config_argument(*configs); val 906 drivers/pinctrl/cirrus/pinctrl-madera-core.c if (val) val 208 drivers/pinctrl/freescale/pinctrl-imx.c u32 val = pin_mmio->input_val; val 209 drivers/pinctrl/freescale/pinctrl-imx.c u8 select = val & 0xff; val 210 drivers/pinctrl/freescale/pinctrl-imx.c u8 width = (val >> 8) & 0xff; val 211 drivers/pinctrl/freescale/pinctrl-imx.c u8 shift = (val >> 16) & 0xff; val 217 drivers/pinctrl/freescale/pinctrl-imx.c val = readl(ipctl->base + pin_mmio->input_reg); val 218 drivers/pinctrl/freescale/pinctrl-imx.c val &= ~mask; val 219 drivers/pinctrl/freescale/pinctrl-imx.c val |= select << shift; val 220 drivers/pinctrl/freescale/pinctrl-imx.c writel(val, ipctl->base + pin_mmio->input_reg); val 53 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_FUNCTION(val) (BIT(0) & val) val 54 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1) val 55 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2) val 56 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4) val 57 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8) val 58 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10) val 71 drivers/pinctrl/freescale/pinctrl-mxs.c u32 val, reg; val 78 drivers/pinctrl/freescale/pinctrl-mxs.c ret = of_property_read_u32(np, "fsl,drive-strength", &val); val 80 drivers/pinctrl/freescale/pinctrl-mxs.c config = val | MA_PRESENT; val 81 drivers/pinctrl/freescale/pinctrl-mxs.c ret = of_property_read_u32(np, "fsl,voltage", &val); val 83 drivers/pinctrl/freescale/pinctrl-mxs.c config |= val << VOL_SHIFT | VOL_PRESENT; val 84 drivers/pinctrl/freescale/pinctrl-mxs.c ret = of_property_read_u32(np, "fsl,pull-up", &val); val 86 drivers/pinctrl/freescale/pinctrl-mxs.c config |= val << PULL_SHIFT | PULL_PRESENT; val 357 drivers/pinctrl/freescale/pinctrl-mxs.c u32 val, i; val 362 drivers/pinctrl/freescale/pinctrl-mxs.c if (of_property_read_u32(np, "reg", &val)) val 365 drivers/pinctrl/freescale/pinctrl-mxs.c snprintf(group, length, "%s.%d", np->name, val); val 406 drivers/pinctrl/freescale/pinctrl-mxs.c u32 val; val 421 drivers/pinctrl/freescale/pinctrl-mxs.c if (of_property_read_u32(child, "reg", &val)) val 448 drivers/pinctrl/freescale/pinctrl-mxs.c if (of_property_read_u32(child, "reg", &val)) val 488 drivers/pinctrl/freescale/pinctrl-mxs.c if (of_property_read_u32(child, "reg", &val)) { val 24 drivers/pinctrl/freescale/pinctrl-scu.c u32 val; val 35 drivers/pinctrl/freescale/pinctrl-scu.c u32 val; val 65 drivers/pinctrl/freescale/pinctrl-scu.c *config = resp->val; val 78 drivers/pinctrl/freescale/pinctrl-scu.c unsigned int val; val 86 drivers/pinctrl/freescale/pinctrl-scu.c val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE; val 87 drivers/pinctrl/freescale/pinctrl-scu.c val |= mux << BP_PAD_CTL_IFMUX; val 95 drivers/pinctrl/freescale/pinctrl-scu.c msg.val = val; val 100 drivers/pinctrl/freescale/pinctrl-scu.c pin_id, conf, val); val 98 drivers/pinctrl/intel/pinctrl-baytrail.c u32 val; val 908 drivers/pinctrl/intel/pinctrl-baytrail.c u32 conf, pull, val, debounce; val 914 drivers/pinctrl/intel/pinctrl-baytrail.c val = readl(val_reg); val 924 drivers/pinctrl/intel/pinctrl-baytrail.c if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) val 932 drivers/pinctrl/intel/pinctrl-baytrail.c if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) val 993 drivers/pinctrl/intel/pinctrl-baytrail.c u32 conf, val, debounce; val 999 drivers/pinctrl/intel/pinctrl-baytrail.c val = readl(val_reg); val 1018 drivers/pinctrl/intel/pinctrl-baytrail.c if (val & BYT_INPUT_EN) { val 1019 drivers/pinctrl/intel/pinctrl-baytrail.c val &= ~BYT_INPUT_EN; val 1020 drivers/pinctrl/intel/pinctrl-baytrail.c writel(val, val_reg); val 1040 drivers/pinctrl/intel/pinctrl-baytrail.c if (val & BYT_INPUT_EN) { val 1041 drivers/pinctrl/intel/pinctrl-baytrail.c val &= ~BYT_INPUT_EN; val 1042 drivers/pinctrl/intel/pinctrl-baytrail.c writel(val, val_reg); val 1127 drivers/pinctrl/intel/pinctrl-baytrail.c u32 val; val 1130 drivers/pinctrl/intel/pinctrl-baytrail.c val = readl(reg); val 1133 drivers/pinctrl/intel/pinctrl-baytrail.c return !!(val & BYT_LEVEL); val 1199 drivers/pinctrl/intel/pinctrl-baytrail.c u32 conf0, val; val 1229 drivers/pinctrl/intel/pinctrl-baytrail.c val = readl(reg); val 1270 drivers/pinctrl/intel/pinctrl-baytrail.c val & BYT_INPUT_EN ? " " : "in", val 1271 drivers/pinctrl/intel/pinctrl-baytrail.c val & BYT_OUTPUT_EN ? " " : "out", val 1272 drivers/pinctrl/intel/pinctrl-baytrail.c val & BYT_LEVEL ? "hi" : "lo", val 1685 drivers/pinctrl/intel/pinctrl-baytrail.c vg->saved_context[i].val = value; val 1724 drivers/pinctrl/intel/pinctrl-baytrail.c vg->saved_context[i].val) { val 1728 drivers/pinctrl/intel/pinctrl-baytrail.c v |= vg->saved_context[i].val; val 1809 drivers/pinctrl/intel/pinctrl-cherryview.c u32 val; val 1819 drivers/pinctrl/intel/pinctrl-cherryview.c val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; val 1820 drivers/pinctrl/intel/pinctrl-cherryview.c if (ctx->padctrl0 != val) { val 1827 drivers/pinctrl/intel/pinctrl-cherryview.c val = readl(reg); val 1828 drivers/pinctrl/intel/pinctrl-cherryview.c if (ctx->padctrl1 != val) { val 1531 drivers/pinctrl/intel/pinctrl-intel.c u32 val; val 1536 drivers/pinctrl/intel/pinctrl-intel.c val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); val 1537 drivers/pinctrl/intel/pinctrl-intel.c pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; val 1538 drivers/pinctrl/intel/pinctrl-intel.c val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); val 1539 drivers/pinctrl/intel/pinctrl-intel.c pads[i].padcfg1 = val; val 1624 drivers/pinctrl/intel/pinctrl-intel.c u32 val; val 1630 drivers/pinctrl/intel/pinctrl-intel.c val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; val 1631 drivers/pinctrl/intel/pinctrl-intel.c if (val != pads[i].padcfg0) { val 1638 drivers/pinctrl/intel/pinctrl-intel.c val = readl(padcfg); val 1639 drivers/pinctrl/intel/pinctrl-intel.c if (val != pads[i].padcfg1) { val 1647 drivers/pinctrl/intel/pinctrl-intel.c val = readl(padcfg); val 1648 drivers/pinctrl/intel/pinctrl-intel.c if (val != pads[i].padcfg2) { val 102 drivers/pinctrl/mediatek/pinctrl-moore.c int val, val2, err, reg, ret = 1; val 136 drivers/pinctrl/mediatek/pinctrl-moore.c err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val); val 140 drivers/pinctrl/mediatek/pinctrl-moore.c if (!val) val 146 drivers/pinctrl/mediatek/pinctrl-moore.c err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); val 151 drivers/pinctrl/mediatek/pinctrl-moore.c if ((val && param == PIN_CONFIG_INPUT_ENABLE) || val 152 drivers/pinctrl/mediatek/pinctrl-moore.c (!val && param == PIN_CONFIG_OUTPUT_ENABLE)) val 157 drivers/pinctrl/mediatek/pinctrl-moore.c err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); val 165 drivers/pinctrl/mediatek/pinctrl-moore.c if (val || !val2) val 183 drivers/pinctrl/mediatek/pinctrl-moore.c err = mtk_hw_get_value(hw, desc, reg, &val); val 187 drivers/pinctrl/mediatek/pinctrl-moore.c ret = val; val 45 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val) val 47 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c writel_relaxed(val, pctl->base[i] + reg); val 57 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c u32 val; val 59 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c val = mtk_r32(pctl, i, reg); val 60 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c val &= ~mask; val 61 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c val |= set; val 62 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c mtk_w32(pctl, i, reg, val); val 535 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c const struct mtk_pin_desc *desc, int *val) val 553 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step; val 580 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c const struct mtk_pin_desc *desc, int *val) val 591 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c *val = ((val1 & 0x7) / tb->scal + 1) * tb->step; val 638 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c u32 *val) val 650 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c err = hw->soc->bias_get(hw, desc, pullup, val); val 673 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c *val = (t | t2 << 1) & 0x7; val 705 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c const struct mtk_pin_desc *desc, u32 *val) val 722 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c *val = (en | e0 << 1 | e1 << 2) & 0x7; val 222 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h const struct mtk_pin_desc *desc, int *val); val 229 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h u32 *val); val 233 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h const struct mtk_pin_desc *desc, u32 *val); val 284 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h const struct mtk_pin_desc *desc, int *val); val 289 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h const struct mtk_pin_desc *desc, int *val); val 296 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h u32 *val); val 300 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h const struct mtk_pin_desc *desc, u32 *val); val 198 drivers/pinctrl/mediatek/pinctrl-mtk-common.c unsigned int val; val 212 drivers/pinctrl/mediatek/pinctrl-mtk-common.c val = driving / drv_grp->step - 1; val 217 drivers/pinctrl/mediatek/pinctrl-mtk-common.c val <<= shift; val 219 drivers/pinctrl/mediatek/pinctrl-mtk-common.c pin_drv->offset, mask, val); val 678 drivers/pinctrl/mediatek/pinctrl-mtk-common.c unsigned int val; val 692 drivers/pinctrl/mediatek/pinctrl-mtk-common.c val = (mode << (GPIO_MODE_BITS * bit)); val 694 drivers/pinctrl/mediatek/pinctrl-mtk-common.c reg_addr, mask, val); val 81 drivers/pinctrl/mediatek/pinctrl-paris.c int val, val2, err, reg, ret = 1; val 115 drivers/pinctrl/mediatek/pinctrl-paris.c err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val); val 119 drivers/pinctrl/mediatek/pinctrl-paris.c if (!val) val 125 drivers/pinctrl/mediatek/pinctrl-paris.c err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); val 130 drivers/pinctrl/mediatek/pinctrl-paris.c if ((val && param == PIN_CONFIG_INPUT_ENABLE) || val 131 drivers/pinctrl/mediatek/pinctrl-paris.c (!val && param == PIN_CONFIG_OUTPUT_ENABLE)) val 136 drivers/pinctrl/mediatek/pinctrl-paris.c err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); val 144 drivers/pinctrl/mediatek/pinctrl-paris.c if (val || !val2) val 162 drivers/pinctrl/mediatek/pinctrl-paris.c err = mtk_hw_get_value(hw, desc, reg, &val); val 166 drivers/pinctrl/mediatek/pinctrl-paris.c ret = val; val 194 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, val; val 202 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_read(pc->reg_gpio, reg, &val); val 206 drivers/pinctrl/meson/pinctrl-meson.c return BIT(bit) & val ? 1 : 0; val 276 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, val = 0; val 285 drivers/pinctrl/meson/pinctrl-meson.c val = BIT(bit); val 287 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); val 396 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, val; val 405 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_read(pc->reg_pullen, reg, &val); val 409 drivers/pinctrl/meson/pinctrl-meson.c if (!(val & BIT(bit))) { val 414 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_read(pc->reg_pull, reg, &val); val 418 drivers/pinctrl/meson/pinctrl-meson.c if (val & BIT(bit)) val 433 drivers/pinctrl/meson/pinctrl-meson.c unsigned int val; val 446 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_read(pc->reg_ds, reg, &val); val 450 drivers/pinctrl/meson/pinctrl-meson.c switch ((val >> bit) & 0x3) { val 572 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, val; val 581 drivers/pinctrl/meson/pinctrl-meson.c regmap_read(pc->reg_gpio, reg, &val); val 583 drivers/pinctrl/meson/pinctrl-meson.c return !!(val & BIT(bit)); val 63 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val[NB_FUNCS]; val 118 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .val = {0, _mask}, \ val 128 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .val = {0, _mask}, \ val 138 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .val = {_val1, _val2}, \ val 148 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .val = {_v1, _v2, _v3}, \ val 159 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .val = {_v1, _v2}, \ val 346 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c int func, val; val 355 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = grp->val[func]; val 357 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); val 400 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int val, mask; val 404 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_read(info->regmap, reg, &val); val 406 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c return !(val & mask); val 414 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int mask, val, ret; val 425 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = value ? mask : 0; val 426 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); val 435 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int val, mask; val 440 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_read(info->regmap, reg, &val); val 442 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c return (val & mask) != 0; val 450 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int mask, val; val 454 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = value ? mask : 0; val 456 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); val 530 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val, reg = IRQ_EN; val 535 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); val 536 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val & ~d->mask, info->base + reg); val 544 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val, reg = IRQ_EN; val 549 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); val 550 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val | d->mask, info->base + reg); val 558 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val, reg = IRQ_WKUP; val 563 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); val 565 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val |= (BIT(d->hwirq % GPIO_PER_REG)); val 567 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val &= ~(BIT(d->hwirq % GPIO_PER_REG)); val 568 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val, info->base + reg); val 578 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val, reg = IRQ_POL; val 583 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); val 586 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val &= ~(BIT(d->hwirq % GPIO_PER_REG)); val 589 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val |= (BIT(d->hwirq % GPIO_PER_REG)); val 599 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */ val 601 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */ val 608 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val, info->base + reg); val 112 drivers/pinctrl/mvebu/pinctrl-mvebu.c if (config == grp->settings[n].val) { val 303 drivers/pinctrl/mvebu/pinctrl-mvebu.c config = setting->val; val 333 drivers/pinctrl/mvebu/pinctrl-mvebu.c config = setting->val; val 789 drivers/pinctrl/mvebu/pinctrl-mvebu.c unsigned int val; val 792 drivers/pinctrl/mvebu/pinctrl-mvebu.c err = regmap_read(data->regmap.map, data->regmap.offset + off, &val); val 796 drivers/pinctrl/mvebu/pinctrl-mvebu.c *config = (val >> shift) & MVEBU_MPP_MASK; val 85 drivers/pinctrl/mvebu/pinctrl-mvebu.h u8 val; val 159 drivers/pinctrl/mvebu/pinctrl-mvebu.h .val = _val, \ val 94 drivers/pinctrl/nomadik/pinctrl-abx500.c u8 val; val 99 drivers/pinctrl/nomadik/pinctrl-abx500.c AB8500_MISC, reg, &val); val 107 drivers/pinctrl/nomadik/pinctrl-abx500.c *bit = !!(val & BIT(pos)); val 113 drivers/pinctrl/nomadik/pinctrl-abx500.c unsigned offset, int val) val 121 drivers/pinctrl/nomadik/pinctrl-abx500.c AB8500_MISC, reg, BIT(pos), val << pos); val 162 drivers/pinctrl/nomadik/pinctrl-abx500.c static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) val 167 drivers/pinctrl/nomadik/pinctrl-abx500.c ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); val 174 drivers/pinctrl/nomadik/pinctrl-abx500.c int val) val 200 drivers/pinctrl/nomadik/pinctrl-abx500.c return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); val 245 drivers/pinctrl/nomadik/pinctrl-abx500.c int val; val 275 drivers/pinctrl/nomadik/pinctrl-abx500.c val = 0; val 277 drivers/pinctrl/nomadik/pinctrl-abx500.c val++; val 280 drivers/pinctrl/nomadik/pinctrl-abx500.c offset, val); val 192 drivers/pinctrl/nomadik/pinctrl-nomadik.c #define PIN_CFG_OUTPUT(num, alt, val) \ val 194 drivers/pinctrl/nomadik/pinctrl-nomadik.c (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) val 365 drivers/pinctrl/nomadik/pinctrl-nomadik.c unsigned offset, int val) val 367 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (val) val 374 drivers/pinctrl/nomadik/pinctrl-nomadik.c unsigned offset, int val) val 377 drivers/pinctrl/nomadik/pinctrl-nomadik.c __nmk_gpio_set_output(nmk_chip, offset, val); val 439 drivers/pinctrl/nomadik/pinctrl-nomadik.c u32 val; val 441 drivers/pinctrl/nomadik/pinctrl-nomadik.c val = readl(reg); val 442 drivers/pinctrl/nomadik/pinctrl-nomadik.c val = ((val & ~mask) | (value & mask)); val 443 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(val, reg); val 888 drivers/pinctrl/nomadik/pinctrl-nomadik.c int val) val 894 drivers/pinctrl/nomadik/pinctrl-nomadik.c __nmk_gpio_set_output(nmk_chip, offset, val); val 900 drivers/pinctrl/nomadik/pinctrl-nomadik.c int val) val 906 drivers/pinctrl/nomadik/pinctrl-nomadik.c __nmk_gpio_make_output(nmk_chip, offset, val); val 974 drivers/pinctrl/nomadik/pinctrl-nomadik.c int val; val 985 drivers/pinctrl/nomadik/pinctrl-nomadik.c val = nmk_gpio_get_input(chip, offset); val 986 drivers/pinctrl/nomadik/pinctrl-nomadik.c seq_printf(s, " VAL %d", val); val 1378 drivers/pinctrl/nomadik/pinctrl-nomadik.c static int nmk_dt_pin_config(int index, int val, unsigned long *config) val 1386 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (val < nmk_cfg_params[index].size) { val 1388 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_cfg_params[index].choice[val]; val 1411 drivers/pinctrl/nomadik/pinctrl-nomadik.c int i, val, ret; val 1415 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_cfg_params[i].property, &val); val 1417 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (nmk_dt_pin_config(i, val, &cfg) == 0) { val 1740 drivers/pinctrl/nomadik/pinctrl-nomadik.c int pull, slpm, output, val, i; val 1760 drivers/pinctrl/nomadik/pinctrl-nomadik.c val = PIN_VAL(cfg); val 1782 drivers/pinctrl/nomadik/pinctrl-nomadik.c val = slpm_val - 1; val 1790 drivers/pinctrl/nomadik/pinctrl-nomadik.c slpm_val ? (val ? "high" : "low") : "same"); val 1797 drivers/pinctrl/nomadik/pinctrl-nomadik.c output ? (val ? "high" : "low") : "", val 1806 drivers/pinctrl/nomadik/pinctrl-nomadik.c __nmk_gpio_make_output(nmk_chip, bit, val); val 106 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c unsigned long val; val 110 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c val = ioread32(reg) | pinmask; val 111 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(val, reg); val 120 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c unsigned long val; val 124 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c val = ioread32(reg) & ~pinmask; val 125 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(val, reg); val 1444 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c u32 val; val 1453 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val); val 1454 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c return !!(val & SRCNT_ESPI); val 1510 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int flg, val; val 1515 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) val 1517 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ds = val ? DSHI(flg) : DSLO(flg); val 1519 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c "pin %d strength %d = %d\n", pin, val, ds); val 210 drivers/pinctrl/pinconf-generic.c u32 val; val 214 drivers/pinctrl/pinconf-generic.c ret = of_property_read_u32(np, par->property, &val); val 222 drivers/pinctrl/pinconf-generic.c val = par->default_value; val 224 drivers/pinctrl/pinconf-generic.c pr_debug("found %s with value %u\n", par->property, val); val 225 drivers/pinctrl/pinconf-generic.c cfg[*ncfg] = pinconf_to_config_packed(par->param, val); val 657 drivers/pinctrl/pinctrl-artpec6.c unsigned int regval, val; val 672 drivers/pinctrl/pinctrl-artpec6.c val = ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT; val 675 drivers/pinctrl/pinctrl-artpec6.c val = artpec6_pin_groups[group].config val 678 drivers/pinctrl/pinctrl-artpec6.c val = ARTPEC6_CONFIG_0 val 686 drivers/pinctrl/pinctrl-artpec6.c regval |= val; val 712 drivers/pinctrl/pinctrl-artpec6.c u32 val; val 717 drivers/pinctrl/pinctrl-artpec6.c val = readl_relaxed(pmx->base + reg); val 718 drivers/pinctrl/pinctrl-artpec6.c val &= ~ARTPEC6_PINMUX_SEL_MASK; val 719 drivers/pinctrl/pinctrl-artpec6.c val |= ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT; val 720 drivers/pinctrl/pinctrl-artpec6.c writel_relaxed(val, pmx->base + reg); val 927 drivers/pinctrl/pinctrl-artpec6.c u32 val; val 929 drivers/pinctrl/pinctrl-artpec6.c val = readl_relaxed(base + artpec6_pmx_reg_offset(i)); val 930 drivers/pinctrl/pinctrl-artpec6.c val &= ~ARTPEC6_PINMUX_DRV_MASK; val 931 drivers/pinctrl/pinctrl-artpec6.c val |= ARTPEC6_DRIVE_8mA_SET << ARTPEC6_PINMUX_DRV_SHIFT; val 932 drivers/pinctrl/pinctrl-artpec6.c writel_relaxed(val, base + artpec6_pmx_reg_offset(i)); val 238 drivers/pinctrl/pinctrl-as3722.c u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option); val 242 drivers/pinctrl/pinctrl-as3722.c __func__, group, function, val); val 245 drivers/pinctrl/pinctrl-as3722.c AS3722_GPIO_IOSF_MASK, val); val 253 drivers/pinctrl/pinctrl-as3722.c switch (val) { val 446 drivers/pinctrl/pinctrl-as3722.c u32 val; val 475 drivers/pinctrl/pinctrl-as3722.c ret = as3722_read(as3722, reg, &val); val 482 drivers/pinctrl/pinctrl-as3722.c val = !!(val & AS3722_GPIOn_SIGNAL(offset)); val 483 drivers/pinctrl/pinctrl-as3722.c return (invert_enable) ? !val : val; val 492 drivers/pinctrl/pinctrl-as3722.c u32 val; val 495 drivers/pinctrl/pinctrl-as3722.c ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val); val 501 drivers/pinctrl/pinctrl-as3722.c en_invert = !!(val & AS3722_GPIO_INV); val 504 drivers/pinctrl/pinctrl-as3722.c val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset); val 506 drivers/pinctrl/pinctrl-as3722.c val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0; val 509 drivers/pinctrl/pinctrl-as3722.c AS3722_GPIOn_SIGNAL(offset), val); val 152 drivers/pinctrl/pinctrl-at91-pio4.c unsigned int val) val 154 drivers/pinctrl/pinctrl-at91-pio4.c writel_relaxed(val, atmel_pioctrl->reg_base val 351 drivers/pinctrl/pinctrl-at91-pio4.c static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) val 357 drivers/pinctrl/pinctrl-at91-pio4.c val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, val 398 drivers/pinctrl/pinctrl-at91.c static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val) val 400 drivers/pinctrl/pinctrl-at91.c *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1; val 405 drivers/pinctrl/pinctrl-at91.c bool is_on, bool val) val 407 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); val 1078 drivers/pinctrl/pinctrl-at91.c int val, num_conf = 0; val 1096 drivers/pinctrl/pinctrl-at91.c val = config >> DEBOUNCE_VAL_SHIFT; val 1097 drivers/pinctrl/pinctrl-at91.c seq_printf(s, "(%d)", val); val 1442 drivers/pinctrl/pinctrl-at91.c int val) val 1448 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); val 1467 drivers/pinctrl/pinctrl-at91.c int val) val 1473 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); val 121 drivers/pinctrl/pinctrl-axp209.c unsigned int val; val 124 drivers/pinctrl/pinctrl-axp209.c ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val); val 128 drivers/pinctrl/pinctrl-axp209.c return !!(val & BIT(offset + pctl->desc->gpio_status_offset)); val 135 drivers/pinctrl/pinctrl-axp209.c unsigned int val; val 142 drivers/pinctrl/pinctrl-axp209.c ret = regmap_read(pctl->regmap, reg, &val); val 151 drivers/pinctrl/pinctrl-axp209.c if ((val & AXP20X_GPIO_FUNCTIONS) > 2) val 158 drivers/pinctrl/pinctrl-axp209.c return val & 2; val 222 drivers/pinctrl/pinctrl-coh901.c u32 val; val 226 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, dor)); val 228 drivers/pinctrl/pinctrl-coh901.c writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); val 230 drivers/pinctrl/pinctrl-coh901.c writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); val 239 drivers/pinctrl/pinctrl-coh901.c u32 val; val 242 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, pcr)); val 244 drivers/pinctrl/pinctrl-coh901.c val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); val 245 drivers/pinctrl/pinctrl-coh901.c writel(val, U300_PIN_REG(offset, pcr)); val 256 drivers/pinctrl/pinctrl-coh901.c u32 val; val 259 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, pcr)); val 264 drivers/pinctrl/pinctrl-coh901.c oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << val 268 drivers/pinctrl/pinctrl-coh901.c val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << val 270 drivers/pinctrl/pinctrl-coh901.c val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL val 272 drivers/pinctrl/pinctrl-coh901.c writel(val, U300_PIN_REG(offset, pcr)); val 344 drivers/pinctrl/pinctrl-coh901.c u32 val; val 350 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, per)); val 351 drivers/pinctrl/pinctrl-coh901.c writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); val 354 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, per)); val 355 drivers/pinctrl/pinctrl-coh901.c writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); val 358 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, pcr)); val 359 drivers/pinctrl/pinctrl-coh901.c val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK val 361 drivers/pinctrl/pinctrl-coh901.c val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL val 363 drivers/pinctrl/pinctrl-coh901.c writel(val, U300_PIN_REG(offset, pcr)); val 366 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, pcr)); val 367 drivers/pinctrl/pinctrl-coh901.c val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK val 369 drivers/pinctrl/pinctrl-coh901.c val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN val 371 drivers/pinctrl/pinctrl-coh901.c writel(val, U300_PIN_REG(offset, pcr)); val 374 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, pcr)); val 375 drivers/pinctrl/pinctrl-coh901.c val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK val 377 drivers/pinctrl/pinctrl-coh901.c val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE val 379 drivers/pinctrl/pinctrl-coh901.c writel(val, U300_PIN_REG(offset, pcr)); val 403 drivers/pinctrl/pinctrl-coh901.c u32 val; val 405 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, icr)); val 409 drivers/pinctrl/pinctrl-coh901.c writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); val 414 drivers/pinctrl/pinctrl-coh901.c writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); val 426 drivers/pinctrl/pinctrl-coh901.c u32 val; val 443 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, icr)); val 444 drivers/pinctrl/pinctrl-coh901.c writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); val 449 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, icr)); val 450 drivers/pinctrl/pinctrl-coh901.c writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); val 463 drivers/pinctrl/pinctrl-coh901.c u32 val; val 469 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, ien)); val 470 drivers/pinctrl/pinctrl-coh901.c writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); val 479 drivers/pinctrl/pinctrl-coh901.c u32 val; val 483 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(offset, ien)); val 484 drivers/pinctrl/pinctrl-coh901.c writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); val 503 drivers/pinctrl/pinctrl-coh901.c unsigned long val; val 508 drivers/pinctrl/pinctrl-coh901.c val = readl(U300_PIN_REG(pinoffset, iev)); val 510 drivers/pinctrl/pinctrl-coh901.c val &= 0xFFU; /* 8 bits per port */ val 512 drivers/pinctrl/pinctrl-coh901.c writel(val, U300_PIN_REG(pinoffset, iev)); val 515 drivers/pinctrl/pinctrl-coh901.c if (val != 0) { val 518 drivers/pinctrl/pinctrl-coh901.c for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { val 621 drivers/pinctrl/pinctrl-coh901.c u32 val; val 665 drivers/pinctrl/pinctrl-coh901.c val = readl(gpio->base + U300_GPIO_CR); val 668 drivers/pinctrl/pinctrl-coh901.c ((val & 0x000001FC) >> 2), val 669 drivers/pinctrl/pinctrl-coh901.c ((val & 0x0000FE00) >> 9), val 670 drivers/pinctrl/pinctrl-coh901.c ((val & 0x0000FE00) >> 9) * 8); val 70 drivers/pinctrl/pinctrl-da850-pupd.c u32 val; val 73 drivers/pinctrl/pinctrl-da850-pupd.c val = readl(data->base + DA850_PUPD_ENA); val 74 drivers/pinctrl/pinctrl-da850-pupd.c arg = !!(~val & BIT(selector)); val 86 drivers/pinctrl/pinctrl-da850-pupd.c val = readl(data->base + DA850_PUPD_SEL); val 88 drivers/pinctrl/pinctrl-da850-pupd.c val = ~val; val 89 drivers/pinctrl/pinctrl-da850-pupd.c arg = !!(val & BIT(selector)); val 40 drivers/pinctrl/pinctrl-falcon.c #define pad_w32(p, val, reg) ltq_w32(val, p + reg) val 2383 drivers/pinctrl/pinctrl-gemini.c u32 val; val 2390 drivers/pinctrl/pinctrl-gemini.c regmap_read(pmx->map, conf->reg, &val); val 2391 drivers/pinctrl/pinctrl-gemini.c val &= conf->mask; val 2392 drivers/pinctrl/pinctrl-gemini.c val >>= (ffs(conf->mask) - 1); val 2393 drivers/pinctrl/pinctrl-gemini.c *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val); val 2450 drivers/pinctrl/pinctrl-gemini.c u32 val; val 2474 drivers/pinctrl/pinctrl-gemini.c val = 0; val 2477 drivers/pinctrl/pinctrl-gemini.c val = 1; val 2480 drivers/pinctrl/pinctrl-gemini.c val = 2; val 2483 drivers/pinctrl/pinctrl-gemini.c val = 3; val 2491 drivers/pinctrl/pinctrl-gemini.c val <<= (ffs(grp->driving_mask) - 1); val 2494 drivers/pinctrl/pinctrl-gemini.c val); val 2497 drivers/pinctrl/pinctrl-gemini.c grp->name, arg, grp->driving_mask, val); val 2530 drivers/pinctrl/pinctrl-gemini.c u32 val; val 2553 drivers/pinctrl/pinctrl-gemini.c ret = regmap_read(map, GLOBAL_WORD_ID, &val); val 2558 drivers/pinctrl/pinctrl-gemini.c val >>= 8; val 2559 drivers/pinctrl/pinctrl-gemini.c val &= 0xffff; val 2560 drivers/pinctrl/pinctrl-gemini.c if (val == 0x3512) { val 2567 drivers/pinctrl/pinctrl-gemini.c } else if (val == 0x3516) { val 2575 drivers/pinctrl/pinctrl-gemini.c dev_err(dev, "unknown chip ID: %04x\n", val); val 2579 drivers/pinctrl/pinctrl-gemini.c ret = regmap_read(map, GLOBAL_MISC_CTRL, &val); val 2580 drivers/pinctrl/pinctrl-gemini.c dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val); val 2582 drivers/pinctrl/pinctrl-gemini.c val &= PADS_MASK; val 2584 drivers/pinctrl/pinctrl-gemini.c val ^= 0x0f; val 2586 drivers/pinctrl/pinctrl-gemini.c tmp = val; val 2589 drivers/pinctrl/pinctrl-gemini.c (val & BIT(i)) ? "enabled" : "disabled"); val 2593 drivers/pinctrl/pinctrl-gemini.c regmap_read(map, GLOBAL_STATUS, &val); val 2594 drivers/pinctrl/pinctrl-gemini.c pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); val 1335 drivers/pinctrl/pinctrl-ingenic.c unsigned int val; val 1337 drivers/pinctrl/pinctrl-ingenic.c regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); val 1339 drivers/pinctrl/pinctrl-ingenic.c return (u32) val; val 1373 drivers/pinctrl/pinctrl-ingenic.c unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); val 1375 drivers/pinctrl/pinctrl-ingenic.c return !!(val & BIT(offset)); val 1633 drivers/pinctrl/pinctrl-ingenic.c unsigned int val; val 1635 drivers/pinctrl/pinctrl-ingenic.c regmap_read(jzpc->map, offt * 0x100 + reg, &val); val 1637 drivers/pinctrl/pinctrl-ingenic.c return val & BIT(idx); val 103 drivers/pinctrl/pinctrl-lantiq.c u32 val; val 105 drivers/pinctrl/pinctrl-lantiq.c info->params[i].property, &val); val 109 drivers/pinctrl/pinctrl-lantiq.c val); val 61 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_PINTSEL_VAL(val, n) \ val 62 drivers/pinctrl/pinctrl-lpc18xx.c ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8)) val 732 drivers/pinctrl/pinctrl-lpc18xx.c static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg) val 739 drivers/pinctrl/pinctrl-lpc18xx.c if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val) val 764 drivers/pinctrl/pinctrl-lpc18xx.c u32 val; val 770 drivers/pinctrl/pinctrl-lpc18xx.c val = lpc18xx_gpio_to_pintsel_val(gpio); val 777 drivers/pinctrl/pinctrl-lpc18xx.c ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg); val 781 drivers/pinctrl/pinctrl-lpc18xx.c return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg); val 985 drivers/pinctrl/pinctrl-lpc18xx.c u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0; val 995 drivers/pinctrl/pinctrl-lpc18xx.c val = lpc18xx_gpio_to_pintsel_val(gpio); val 1001 drivers/pinctrl/pinctrl-lpc18xx.c reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val); val 242 drivers/pinctrl/pinctrl-max77620.c u8 val; val 246 drivers/pinctrl/pinctrl-max77620.c val = 0; val 248 drivers/pinctrl/pinctrl-max77620.c val = 1 << group; val 255 drivers/pinctrl/pinctrl-max77620.c BIT(group), val); val 275 drivers/pinctrl/pinctrl-max77620.c unsigned int val; val 291 drivers/pinctrl/pinctrl-max77620.c ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val); val 296 drivers/pinctrl/pinctrl-max77620.c if (val & BIT(pin)) val 301 drivers/pinctrl/pinctrl-max77620.c ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val); val 306 drivers/pinctrl/pinctrl-max77620.c if (val & BIT(pin)) val 323 drivers/pinctrl/pinctrl-max77620.c unsigned int val; val 326 drivers/pinctrl/pinctrl-max77620.c ret = regmap_read(mpci->rmap, addr, &val); val 331 drivers/pinctrl/pinctrl-max77620.c *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; val 401 drivers/pinctrl/pinctrl-max77620.c unsigned int val; val 413 drivers/pinctrl/pinctrl-max77620.c val = param_val ? 0 : 1; val 417 drivers/pinctrl/pinctrl-max77620.c val); val 421 drivers/pinctrl/pinctrl-max77620.c mpci->pin_info[pin].drv_type = val ? val 426 drivers/pinctrl/pinctrl-max77620.c val = param_val ? 1 : 0; val 430 drivers/pinctrl/pinctrl-max77620.c val); val 434 drivers/pinctrl/pinctrl-max77620.c mpci->pin_info[pin].drv_type = val ? val 170 drivers/pinctrl/pinctrl-mcp23s08.c static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) val 172 drivers/pinctrl/pinctrl-mcp23s08.c return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); val 175 drivers/pinctrl/pinctrl-mcp23s08.c static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) val 177 drivers/pinctrl/pinctrl-mcp23s08.c return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); val 183 drivers/pinctrl/pinctrl-mcp23s08.c u16 val = enabled ? 0xffff : 0x0000; val 185 drivers/pinctrl/pinctrl-mcp23s08.c mask, val); val 331 drivers/pinctrl/pinctrl-mcp23s08.c const void *val, size_t val_size) val 338 drivers/pinctrl/pinctrl-mcp23s08.c { .tx_buf = val, .len = val_size, }, }; val 349 drivers/pinctrl/pinctrl-mcp23s08.c void *val, size_t val_size) val 361 drivers/pinctrl/pinctrl-mcp23s08.c return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); val 579 drivers/pinctrl/pinctrl-ocelot.c unsigned int val; val 581 drivers/pinctrl/pinctrl-ocelot.c regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); val 583 drivers/pinctrl/pinctrl-ocelot.c return !!(val & BIT(offset % 32)); val 603 drivers/pinctrl/pinctrl-ocelot.c unsigned int val; val 605 drivers/pinctrl/pinctrl-ocelot.c regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); val 607 drivers/pinctrl/pinctrl-ocelot.c return !(val & BIT(offset % 32)); val 576 drivers/pinctrl/pinctrl-palmas.c unsigned int val; val 587 drivers/pinctrl/pinctrl-palmas.c g->mux_reg_add, &val); val 593 drivers/pinctrl/pinctrl-palmas.c val &= g->mux_reg_mask; val 594 drivers/pinctrl/pinctrl-palmas.c pci->pins_current_opt[i] = val >> g->mux_bit_shift; val 603 drivers/pinctrl/pinctrl-palmas.c int val; val 605 drivers/pinctrl/pinctrl-palmas.c val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0; val 608 drivers/pinctrl/pinctrl-palmas.c PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val); val 618 drivers/pinctrl/pinctrl-palmas.c int val; val 620 drivers/pinctrl/pinctrl-palmas.c val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0; val 623 drivers/pinctrl/pinctrl-palmas.c PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val); val 756 drivers/pinctrl/pinctrl-palmas.c unsigned int val; val 794 drivers/pinctrl/pinctrl-palmas.c ret = palmas_read(pci->palmas, base, add, &val); val 801 drivers/pinctrl/pinctrl-palmas.c rval = val & opt->pud_info->pullup_dn_mask; val 826 drivers/pinctrl/pinctrl-palmas.c ret = palmas_read(pci->palmas, base, add, &val); val 832 drivers/pinctrl/pinctrl-palmas.c rval = val & opt->od_info->od_mask; val 836 drivers/pinctrl/pinctrl-pistachio.c static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg) val 838 drivers/pinctrl/pinctrl-pistachio.c writel(val, pctl->base + reg); val 851 drivers/pinctrl/pinctrl-pistachio.c static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val, val 854 drivers/pinctrl/pinctrl-pistachio.c writel(val, bank->base + reg); val 858 drivers/pinctrl/pinctrl-pistachio.c u32 reg, unsigned int bit, u32 val) val 864 drivers/pinctrl/pinctrl-pistachio.c gpio_writel(bank, (0x10000 | val) << bit, reg); val 951 drivers/pinctrl/pinctrl-pistachio.c u32 val; val 964 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, pg->mux_reg); val 965 drivers/pinctrl/pinctrl-pistachio.c val &= ~(pg->mux_mask << pg->mux_shift); val 966 drivers/pinctrl/pinctrl-pistachio.c val |= i << pg->mux_shift; val 967 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, pg->mux_reg); val 977 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, pf->scenario_reg); val 978 drivers/pinctrl/pinctrl-pistachio.c val &= ~(pf->scenario_mask << pf->scenario_shift); val 979 drivers/pinctrl/pinctrl-pistachio.c val |= i << pf->scenario_shift; val 980 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, pf->scenario_reg); val 1003 drivers/pinctrl/pinctrl-pistachio.c u32 val, arg; val 1007 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); val 1008 drivers/pinctrl/pinctrl-pistachio.c arg = !!(val & PADS_SCHMITT_EN_BIT(pin)); val 1011 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> val 1013 drivers/pinctrl/pinctrl-pistachio.c arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ; val 1016 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> val 1018 drivers/pinctrl/pinctrl-pistachio.c arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP; val 1021 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> val 1023 drivers/pinctrl/pinctrl-pistachio.c arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN; val 1026 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> val 1028 drivers/pinctrl/pinctrl-pistachio.c arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS; val 1031 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); val 1032 drivers/pinctrl/pinctrl-pistachio.c arg = !!(val & PADS_SLEW_RATE_BIT(pin)); val 1035 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >> val 1037 drivers/pinctrl/pinctrl-pistachio.c switch (val & PADS_DRIVE_STRENGTH_MASK) { val 1068 drivers/pinctrl/pinctrl-pistachio.c u32 drv, val, arg; val 1077 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); val 1079 drivers/pinctrl/pinctrl-pistachio.c val |= PADS_SCHMITT_EN_BIT(pin); val 1081 drivers/pinctrl/pinctrl-pistachio.c val &= ~PADS_SCHMITT_EN_BIT(pin); val 1082 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin)); val 1085 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); val 1086 drivers/pinctrl/pinctrl-pistachio.c val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); val 1087 drivers/pinctrl/pinctrl-pistachio.c val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin); val 1088 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); val 1091 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); val 1092 drivers/pinctrl/pinctrl-pistachio.c val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); val 1093 drivers/pinctrl/pinctrl-pistachio.c val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin); val 1094 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); val 1097 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); val 1098 drivers/pinctrl/pinctrl-pistachio.c val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); val 1099 drivers/pinctrl/pinctrl-pistachio.c val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin); val 1100 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); val 1103 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); val 1104 drivers/pinctrl/pinctrl-pistachio.c val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); val 1105 drivers/pinctrl/pinctrl-pistachio.c val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin); val 1106 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); val 1109 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); val 1111 drivers/pinctrl/pinctrl-pistachio.c val |= PADS_SLEW_RATE_BIT(pin); val 1113 drivers/pinctrl/pinctrl-pistachio.c val &= ~PADS_SLEW_RATE_BIT(pin); val 1114 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin)); val 1117 drivers/pinctrl/pinctrl-pistachio.c val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)); val 1118 drivers/pinctrl/pinctrl-pistachio.c val &= ~(PADS_DRIVE_STRENGTH_MASK << val 1139 drivers/pinctrl/pinctrl-pistachio.c val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin); val 1140 drivers/pinctrl/pinctrl-pistachio.c pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin)); val 139 drivers/pinctrl/pinctrl-rk805.c int ret, val; val 141 drivers/pinctrl/pinctrl-rk805.c ret = regmap_read(pci->rk808->regmap, pci->pin_cfg[offset].reg, &val); val 147 drivers/pinctrl/pinctrl-rk805.c return !!(val & pci->pin_cfg[offset].val_msk); val 182 drivers/pinctrl/pinctrl-rk805.c unsigned int val; val 191 drivers/pinctrl/pinctrl-rk805.c &val); val 197 drivers/pinctrl/pinctrl-rk805.c return !(val & pci->pin_cfg[offset].dir_msk); val 1142 drivers/pinctrl/pinctrl-rockchip.c unsigned int val; val 1181 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_read(regmap, reg, &val); val 1185 drivers/pinctrl/pinctrl-rockchip.c return ((val >> bit) & mask); val 577 drivers/pinctrl/pinctrl-rza1.c u16 val = ioread16(mem); val 580 drivers/pinctrl/pinctrl-rza1.c val |= BIT(bit); val 582 drivers/pinctrl/pinctrl-rza1.c val &= ~BIT(bit); val 584 drivers/pinctrl/pinctrl-rza1.c iowrite16(val, mem); val 190 drivers/pinctrl/pinctrl-rza2.c unsigned int offset, int val) val 194 drivers/pinctrl/pinctrl-rza2.c rza2_chip_set(chip, offset, val); val 183 drivers/pinctrl/pinctrl-rzn1.c u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1); val 185 drivers/pinctrl/pinctrl-rzn1.c writel(val, &ipctl->lev1->status_protect); val 189 drivers/pinctrl/pinctrl-rzn1.c u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2); val 191 drivers/pinctrl/pinctrl-rzn1.c writel(val, &ipctl->lev2->status_protect); val 48 drivers/pinctrl/pinctrl-single.c unsigned val; val 63 drivers/pinctrl/pinctrl-single.c unsigned val; val 204 drivers/pinctrl/pinctrl-single.c void (*write)(unsigned val, void __iomem *reg); val 255 drivers/pinctrl/pinctrl-single.c static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) val 257 drivers/pinctrl/pinctrl-single.c writeb(val, reg); val 260 drivers/pinctrl/pinctrl-single.c static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) val 262 drivers/pinctrl/pinctrl-single.c writew(val, reg); val 265 drivers/pinctrl/pinctrl-single.c static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) val 267 drivers/pinctrl/pinctrl-single.c writel(val, reg); val 275 drivers/pinctrl/pinctrl-single.c unsigned val, mux_bytes; val 283 drivers/pinctrl/pinctrl-single.c val = pcs->read(pcs->base + offset); val 286 drivers/pinctrl/pinctrl-single.c seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); val 358 drivers/pinctrl/pinctrl-single.c unsigned val, mask; val 362 drivers/pinctrl/pinctrl-single.c val = pcs->read(vals->reg); val 369 drivers/pinctrl/pinctrl-single.c val &= ~mask; val 370 drivers/pinctrl/pinctrl-single.c val |= (vals->val & mask); val 371 drivers/pinctrl/pinctrl-single.c pcs->write(val, vals->reg); val 672 drivers/pinctrl/pinctrl-single.c unsigned val; val 674 drivers/pinctrl/pinctrl-single.c val = pcs->read(pcs->base + offset); val 675 drivers/pinctrl/pinctrl-single.c if (val & pcs_soc->irq_enable_mask) { val 677 drivers/pinctrl/pinctrl-single.c (unsigned long)pcs->res->start + offset, val); val 678 drivers/pinctrl/pinctrl-single.c val &= ~pcs_soc->irq_enable_mask; val 679 drivers/pinctrl/pinctrl-single.c pcs->write(val, pcs->base + offset); val 836 drivers/pinctrl/pinctrl-single.c (*conf)->val = value; val 1023 drivers/pinctrl/pinctrl-single.c vals[found].val = pinctrl_spec.args[1]; val 1118 drivers/pinctrl/pinctrl-single.c unsigned offset, val; val 1135 drivers/pinctrl/pinctrl-single.c val = pinctrl_spec.args[1]; val 1139 drivers/pinctrl/pinctrl-single.c pinctrl_spec.np, offset, val, mask); val 1146 drivers/pinctrl/pinctrl-single.c val_pos = val & mask_pos; val 1167 drivers/pinctrl/pinctrl-single.c vals[found].val = val_pos; val 1719 drivers/pinctrl/pinctrl-single.c u32 val; val 1721 drivers/pinctrl/pinctrl-single.c error = of_property_read_u32(np, name, &val); val 129 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_PACK(conf, val, param) (conf |=\ val 130 drivers/pinctrl/pinctrl-st.c ((val & ST_PINCONF_ ##param ##_MASK) << \ val 188 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) val 194 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ val 195 drivers/pinctrl/pinctrl-st.c ST_PINCONF_PACK(conf, val, RT_DELAY) val 421 drivers/pinctrl/pinctrl-st.c unsigned int val; val 428 drivers/pinctrl/pinctrl-st.c regmap_field_read(alt, &val); val 429 drivers/pinctrl/pinctrl-st.c val &= ~(0xf << offset); val 430 drivers/pinctrl/pinctrl-st.c val |= function << offset; val 431 drivers/pinctrl/pinctrl-st.c regmap_field_write(alt, val); val 437 drivers/pinctrl/pinctrl-st.c unsigned int val; val 443 drivers/pinctrl/pinctrl-st.c regmap_field_read(alt, &val); val 445 drivers/pinctrl/pinctrl-st.c return (val >> offset) & 0xf; val 506 drivers/pinctrl/pinctrl-st.c unsigned int val = 0; val 508 drivers/pinctrl/pinctrl-st.c regmap_field_read(field, &val); val 510 drivers/pinctrl/pinctrl-st.c val |= BIT(pin); val 512 drivers/pinctrl/pinctrl-st.c val &= ~BIT(pin); val 513 drivers/pinctrl/pinctrl-st.c regmap_field_write(field, val); val 603 drivers/pinctrl/pinctrl-st.c unsigned int delay_bits, delay, delay0, delay1, val; val 606 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) val 609 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) val 612 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) val 615 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) val 618 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) val 1315 drivers/pinctrl/pinctrl-st.c u32 val; val 1347 drivers/pinctrl/pinctrl-st.c val = readl(bank->base + REG_PIO_PCOMP); val 1348 drivers/pinctrl/pinctrl-st.c val &= ~BIT(pin); val 1349 drivers/pinctrl/pinctrl-st.c val |= (comp << pin); val 1350 drivers/pinctrl/pinctrl-st.c writel(val, bank->base + REG_PIO_PCOMP); val 1383 drivers/pinctrl/pinctrl-st.c int n, val, ecfg; val 1405 drivers/pinctrl/pinctrl-st.c val = st_gpio_get(&bank->gpio_chip, n); val 1408 drivers/pinctrl/pinctrl-st.c val ? bank->base + REG_PIO_SET_PCOMP : val 1412 drivers/pinctrl/pinctrl-st.c !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) val 131 drivers/pinctrl/pinctrl-stmfx.c u32 val; val 134 drivers/pinctrl/pinctrl-stmfx.c ret = regmap_read(pctl->stmfx->map, reg, &val); val 140 drivers/pinctrl/pinctrl-stmfx.c return ret ? ret : !(val & mask); val 344 drivers/pinctrl/pinctrl-stmfx.c int dir, type, pupd, val; val 359 drivers/pinctrl/pinctrl-stmfx.c val = stmfx_gpio_get(&pctl->gpio_chip, offset); val 360 drivers/pinctrl/pinctrl-stmfx.c if (val < 0) val 364 drivers/pinctrl/pinctrl-stmfx.c seq_printf(s, "output %s ", val ? "high" : "low"); val 371 drivers/pinctrl/pinctrl-stmfx.c seq_printf(s, "input %s ", val ? "high" : "low"); val 513 drivers/pinctrl/pinctrl-stmfx.c int val; val 518 drivers/pinctrl/pinctrl-stmfx.c val = stmfx_gpio_get(&pctl->gpio_chip, offset); val 519 drivers/pinctrl/pinctrl-stmfx.c if (val < 0) val 522 drivers/pinctrl/pinctrl-stmfx.c if (val) { val 523 drivers/pinctrl/pinctrl-sx150x.c unsigned int n, val = 0; val 531 drivers/pinctrl/pinctrl-sx150x.c val |= SX150X_IRQ_TYPE_EDGE_RISING; val 533 drivers/pinctrl/pinctrl-sx150x.c val |= SX150X_IRQ_TYPE_EDGE_FALLING; val 535 drivers/pinctrl/pinctrl-sx150x.c sx150x_irq_set_sense(pctl, n, val); val 543 drivers/pinctrl/pinctrl-sx150x.c unsigned int val; val 546 drivers/pinctrl/pinctrl-sx150x.c err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val); val 550 drivers/pinctrl/pinctrl-sx150x.c err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); val 554 drivers/pinctrl/pinctrl-sx150x.c status = val; val 946 drivers/pinctrl/pinctrl-sx150x.c unsigned int reg, unsigned int val) val 974 drivers/pinctrl/pinctrl-sx150x.c a = val & 0x00ff0000; val 975 drivers/pinctrl/pinctrl-sx150x.c b = val & 0x0000ff00; val 977 drivers/pinctrl/pinctrl-sx150x.c val &= 0xff0000ff; val 978 drivers/pinctrl/pinctrl-sx150x.c val |= b << 8; val 979 drivers/pinctrl/pinctrl-sx150x.c val |= a >> 8; val 982 drivers/pinctrl/pinctrl-sx150x.c return val; val 1004 drivers/pinctrl/pinctrl-sx150x.c unsigned int idx, val; val 1035 drivers/pinctrl/pinctrl-sx150x.c for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { val 1036 drivers/pinctrl/pinctrl-sx150x.c val <<= 8; val 1042 drivers/pinctrl/pinctrl-sx150x.c val |= ret; val 1045 drivers/pinctrl/pinctrl-sx150x.c *result = sx150x_maybe_swizzle(pctl, reg, val); val 1051 drivers/pinctrl/pinctrl-sx150x.c unsigned int val) val 1058 drivers/pinctrl/pinctrl-sx150x.c val = sx150x_maybe_swizzle(pctl, reg, val); val 1062 drivers/pinctrl/pinctrl-sx150x.c const u8 byte = (val >> n) & 0xff; val 938 drivers/pinctrl/pinctrl-u300.c u16 regval, val, mask; val 945 drivers/pinctrl/pinctrl-u300.c val = upmx_mask->bits; val 947 drivers/pinctrl/pinctrl-u300.c val = 0; val 953 drivers/pinctrl/pinctrl-u300.c regval |= val; val 1533 drivers/pinctrl/pinctrl-xway.c static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) val 1537 drivers/pinctrl/pinctrl-xway.c if (val) val 1559 drivers/pinctrl/pinctrl-xway.c static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val) val 1568 drivers/pinctrl/pinctrl-xway.c xway_gpio_set(chip, pin, val); val 89 drivers/pinctrl/pxa/pinctrl-pxa2xx.c uint32_t val; val 98 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = readl_relaxed(gpdr); val 99 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32)); val 100 drivers/pinctrl/pxa/pinctrl-pxa2xx.c writel_relaxed(val, gpdr); val 146 drivers/pinctrl/pxa/pinctrl-pxa2xx.c u32 val; val 163 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = readl_relaxed(gafr); val 164 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = (val & ~(0x3 << shift)) | ((df->muxval >> 1) << shift); val 165 drivers/pinctrl/pxa/pinctrl-pxa2xx.c writel_relaxed(val, gafr); val 167 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = readl_relaxed(gpdr); val 168 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = (val & ~BIT(pin % 32)) | ((df->muxval & 1) ? BIT(pin % 32) : 0); val 169 drivers/pinctrl/pxa/pinctrl-pxa2xx.c writel_relaxed(val, gpdr); val 192 drivers/pinctrl/pxa/pinctrl-pxa2xx.c u32 val; val 195 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = readl_relaxed(pgsr) & BIT(pin % 32); val 196 drivers/pinctrl/pxa/pinctrl-pxa2xx.c *config = val ? PIN_CONFIG_LOW_POWER_MODE : 0; val 200 drivers/pinctrl/pxa/pinctrl-pxa2xx.c pin, !!val); val 215 drivers/pinctrl/pxa/pinctrl-pxa2xx.c u32 val; val 231 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = readl_relaxed(pgsr); val 232 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = (val & ~BIT(pin % 32)) | (is_set ? BIT(pin % 32) : 0); val 233 drivers/pinctrl/pxa/pinctrl-pxa2xx.c writel_relaxed(val, pgsr); val 75 drivers/pinctrl/qcom/pinctrl-msm.c static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \ val 78 drivers/pinctrl/qcom/pinctrl-msm.c writel(val, pctrl->regs[g->tile] + g->name##_reg); \ val 164 drivers/pinctrl/qcom/pinctrl-msm.c u32 val, mask; val 180 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_ctl(pctrl, g); val 181 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~mask; val 182 drivers/pinctrl/qcom/pinctrl-msm.c val |= i << g->mux_bit; val 183 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_ctl(val, pctrl, g); val 250 drivers/pinctrl/qcom/pinctrl-msm.c static unsigned msm_regval_to_drive(u32 val) val 252 drivers/pinctrl/qcom/pinctrl-msm.c return (val + 1) * 2; val 266 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 274 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_ctl(pctrl, g); val 275 drivers/pinctrl/qcom/pinctrl-msm.c arg = (val >> bit) & mask; val 313 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_io(pctrl, g); val 314 drivers/pinctrl/qcom/pinctrl-msm.c arg = !!(val & BIT(g->in_bit)); val 344 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 387 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_io(pctrl, g); val 389 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->out_bit); val 391 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->out_bit); val 392 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_io(val, pctrl, g); val 415 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_ctl(pctrl, g); val 416 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~(mask << bit); val 417 drivers/pinctrl/qcom/pinctrl-msm.c val |= arg << bit; val 418 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_ctl(val, pctrl, g); val 436 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 442 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_ctl(pctrl, g); val 443 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->oe_bit); val 444 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_ctl(val, pctrl, g); val 456 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 462 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_io(pctrl, g); val 464 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->out_bit); val 466 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->out_bit); val 467 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_io(val, pctrl, g); val 469 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_ctl(pctrl, g); val 470 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->oe_bit); val 471 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_ctl(val, pctrl, g); val 482 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 486 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_ctl(pctrl, g); val 489 drivers/pinctrl/qcom/pinctrl-msm.c return val & BIT(g->oe_bit) ? 0 : 1; val 496 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 500 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_io(pctrl, g); val 501 drivers/pinctrl/qcom/pinctrl-msm.c return !!(val & BIT(g->in_bit)); val 509 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 515 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_io(pctrl, g); val 517 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->out_bit); val 519 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->out_bit); val 520 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_io(val, pctrl, g); val 540 drivers/pinctrl/qcom/pinctrl-msm.c int val; val 569 drivers/pinctrl/qcom/pinctrl-msm.c val = !!(io_reg & BIT(g->out_bit)); val 571 drivers/pinctrl/qcom/pinctrl-msm.c val = !!(io_reg & BIT(g->in_bit)); val 574 drivers/pinctrl/qcom/pinctrl-msm.c seq_printf(s, " %-4s func%d", val ? "high" : "low", func); val 683 drivers/pinctrl/qcom/pinctrl-msm.c unsigned val, val2, intstat; val 687 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_io(pctrl, g) & BIT(g->in_bit); val 695 drivers/pinctrl/qcom/pinctrl-msm.c if (intstat || (val == val2)) val 699 drivers/pinctrl/qcom/pinctrl-msm.c val, val2); val 708 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 714 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_intr_cfg(pctrl, g); val 736 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->intr_raw_status_bit); val 738 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->intr_enable_bit); val 739 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_intr_cfg(val, pctrl, g); val 752 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 764 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_intr_status(pctrl, g); val 765 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->intr_status_bit); val 766 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_intr_status(val, pctrl, g); val 769 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_intr_cfg(pctrl, g); val 770 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_raw_status_bit); val 771 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_enable_bit); val 772 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_intr_cfg(val, pctrl, g); val 796 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 802 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_intr_status(pctrl, g); val 804 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_status_bit); val 806 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->intr_status_bit); val 807 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_intr_status(val, pctrl, g); val 821 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 836 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_intr_target(pctrl, g); val 837 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~(7 << g->intr_target_bit); val 838 drivers/pinctrl/qcom/pinctrl-msm.c val |= g->intr_target_kpss_val << g->intr_target_bit; val 839 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_intr_target(val, pctrl, g); val 846 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_intr_cfg(pctrl, g); val 847 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_raw_status_bit); val 849 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~(3 << g->intr_detection_bit); val 850 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~(1 << g->intr_polarity_bit); val 853 drivers/pinctrl/qcom/pinctrl-msm.c val |= 1 << g->intr_detection_bit; val 854 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); val 857 drivers/pinctrl/qcom/pinctrl-msm.c val |= 2 << g->intr_detection_bit; val 858 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); val 861 drivers/pinctrl/qcom/pinctrl-msm.c val |= 3 << g->intr_detection_bit; val 862 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); val 867 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); val 871 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~(1 << g->intr_detection_bit); val 872 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~(1 << g->intr_polarity_bit); val 875 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_detection_bit); val 876 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); val 879 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_detection_bit); val 882 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_detection_bit); val 883 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); val 888 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); val 894 drivers/pinctrl/qcom/pinctrl-msm.c msm_writel_intr_cfg(val, pctrl, g); val 967 drivers/pinctrl/qcom/pinctrl-msm.c u32 val; val 978 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_intr_status(pctrl, g); val 979 drivers/pinctrl/qcom/pinctrl-msm.c if (val & BIT(g->intr_status_bit)) { val 217 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c unsigned int val; val 220 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = regmap_read(state->map, pad->base + addr, &val); val 224 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = val; val 231 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c unsigned int val) val 235 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = regmap_write(state->map, pad->base + addr, val); val 296 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c unsigned int val; val 323 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; val 325 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; val 327 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; val 329 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = PMIC_GPIO_MODE_DIGITAL_INPUT; val 333 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c PMIC_GPIO_REG_MODE_CTL, val); val 337 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->atest - 1; val 339 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); val 343 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->out_value val 345 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val |= pad->function val 348 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); val 352 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; val 353 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; val 354 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; val 356 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); val 361 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; val 363 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); val 458 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c unsigned int val; val 539 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; val 541 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); val 545 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; val 547 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); val 551 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; val 552 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; val 554 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); val 559 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = 0; val 562 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->dtest_buffer - 1; val 563 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; val 565 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = BIT(pad->dtest_buffer - 1); val 568 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); val 573 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; val 575 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; val 577 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; val 579 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = PMIC_GPIO_MODE_DIGITAL_INPUT; val 583 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c PMIC_GPIO_REG_MODE_CTL, val); val 587 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->atest - 1; val 589 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); val 593 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->out_value val 595 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val |= pad->function val 598 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); val 602 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; val 603 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; val 604 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; val 606 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); val 611 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; val 613 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); val 623 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c int ret, val, function; val 640 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); val 642 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { val 697 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c unsigned pin, int val) val 702 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); val 777 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c int type, subtype, val, dir; val 822 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, val 824 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0) val 825 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return val; val 827 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); val 828 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; val 830 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); val 831 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0) val 832 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return val; val 834 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; val 836 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); val 837 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0) val 838 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return val; val 840 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; val 842 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; val 844 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; val 871 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); val 872 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0) val 873 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return val; val 875 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; val 878 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); val 879 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0) val 880 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return val; val 882 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; val 885 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL); val 886 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0) val 887 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return val; val 889 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) val 891 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; val 893 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->dtest_buffer = ffs(val); val 897 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); val 898 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0) val 899 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return val; val 901 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; val 904 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; val 908 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = pmic_gpio_read(state, pad, val 910 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c if (val < 0) val 911 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c return val; val 912 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; val 179 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c unsigned int val; val 182 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c ret = regmap_read(state->map, pad->base + addr, &val); val 186 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c ret = val; val 193 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c unsigned int val) val 197 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c ret = regmap_write(state->map, pad->base + addr, val); val 259 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c unsigned int val; val 294 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | val 298 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); val 306 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c unsigned int val; val 317 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; val 319 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); val 407 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c unsigned int val; val 475 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; val 477 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); val 482 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; val 485 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val); val 490 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; val 492 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); val 508 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; val 510 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); val 573 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c unsigned pin, int val) val 578 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); val 661 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c int type, subtype, val, dir; val 695 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); val 696 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c if (val < 0) val 697 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return val; val 699 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; val 701 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; val 745 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; val 753 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); val 754 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c if (val < 0) val 755 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return val; val 757 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; val 762 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); val 763 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c if (val < 0) val 764 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return val; val 766 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; val 771 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); val 772 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c if (val < 0) val 773 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return val; val 775 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; val 778 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); val 779 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c if (val < 0) val 780 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return val; val 782 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->drive_strength = val; val 784 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); val 785 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c if (val < 0) val 786 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return val; val 788 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->aout_level = val; val 790 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); val 791 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c if (val < 0) val 792 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c return val; val 794 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->is_enabled = !!val; val 133 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c unsigned int val = bank << 4; val 136 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c ret = regmap_write(pctrl->regmap, pin->reg, val); val 142 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c ret = regmap_read(pctrl->regmap, pin->reg, &val); val 148 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c return val; val 154 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c u8 val) val 158 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= PM8XXX_BANK_WRITE; val 159 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= bank << 4; val 161 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c ret = regmap_write(pctrl->regmap, pin->reg, val); val 232 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c u8 val; val 235 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->function << 1; val 237 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 4, val); val 329 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c u8 val; val 403 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->power_source << 1; val 404 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= PM8XXX_GPIO_MODE_ENABLED; val 405 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 0, val); val 409 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->mode << 2; val 410 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= pin->open_drain << 1; val 411 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= pin->output_value; val 412 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 1, val); val 416 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->bias << 1; val 417 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 2, val); val 421 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->output_strength << 2; val 422 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= pin->disable; val 423 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 3, val); val 427 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->function << 1; val 428 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 4, val); val 432 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = 0; val 434 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= BIT(3); val 435 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 5, val); val 460 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c u8 val; val 463 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->mode << 2; val 465 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 1, val); val 476 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c u8 val; val 481 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->mode << 2; val 482 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= pin->open_drain << 1; val 483 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= pin->output_value; val 485 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 1, val); val 513 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c u8 val; val 517 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pin->mode << 2; val 518 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= pin->open_drain << 1; val 519 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= pin->output_value; val 521 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pm8xxx_write_bank(pctrl, pin, 1, val); val 641 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c int val; val 643 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pm8xxx_read_bank(pctrl, pin, 0); val 644 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (val < 0) val 645 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c return val; val 647 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->power_source = (val >> 1) & 0x7; val 649 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pm8xxx_read_bank(pctrl, pin, 1); val 650 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (val < 0) val 651 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c return val; val 653 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->mode = (val >> 2) & 0x3; val 654 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->open_drain = !!(val & BIT(1)); val 655 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->output_value = val & BIT(0); val 657 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pm8xxx_read_bank(pctrl, pin, 2); val 658 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (val < 0) val 659 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c return val; val 661 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->bias = (val >> 1) & 0x7; val 667 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pm8xxx_read_bank(pctrl, pin, 3); val 668 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (val < 0) val 669 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c return val; val 671 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->output_strength = (val >> 2) & 0x3; val 672 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->disable = val & BIT(0); val 674 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pm8xxx_read_bank(pctrl, pin, 4); val 675 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (val < 0) val 676 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c return val; val 678 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->function = (val >> 1) & 0x7; val 680 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val = pm8xxx_read_bank(pctrl, pin, 5); val 681 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (val < 0) val 682 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c return val; val 684 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->inverted = !(val & BIT(3)); val 171 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c u8 val; val 232 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c val = type << 5 | level << 2 | ctrl; val 233 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c ret = regmap_write(pctrl->regmap, pin->reg, val); val 652 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c unsigned int val; val 658 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c ret = regmap_read(pctrl->regmap, pin->reg, &val); val 664 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c type = (val >> 5) & 7; val 665 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c level = (val >> 2) & 7; val 666 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c ctrl = (val) & 3; val 146 drivers/pinctrl/samsung/pinctrl-s3c24xx.c u32 val; val 155 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val = readl(reg); val 156 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val &= ~(mask << shift); val 157 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val |= bank->eint_func << shift; val 158 drivers/pinctrl/samsung/pinctrl-s3c24xx.c writel(val, reg); val 171 drivers/pinctrl/samsung/pinctrl-s3c24xx.c u32 val; val 185 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val = readl(reg); val 186 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val &= ~(EINT_MASK << shift); val 187 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val |= trigger << shift; val 188 drivers/pinctrl/samsung/pinctrl-s3c24xx.c writel(val, reg); val 275 drivers/pinctrl/samsung/pinctrl-s3c64xx.c u32 val; val 291 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(reg); val 292 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val &= ~(mask << shift); val 293 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val |= bank->eint_func << shift; val 294 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, reg); val 309 drivers/pinctrl/samsung/pinctrl-s3c64xx.c u32 val; val 311 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(reg); val 313 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val |= 1 << index; val 315 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val &= ~(1 << index); val 316 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, reg); val 346 drivers/pinctrl/samsung/pinctrl-s3c64xx.c u32 val; val 361 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(reg); val 362 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val &= ~(EINT_CON_MASK << shift); val 363 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val |= trigger << shift; val 364 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, reg); val 515 drivers/pinctrl/samsung/pinctrl-s3c64xx.c u32 val; val 517 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(d->virt_base + EINT0MASK_REG); val 519 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val |= 1 << ddata->eints[irqd->hwirq]; val 521 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val &= ~(1 << ddata->eints[irqd->hwirq]); val 522 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, d->virt_base + EINT0MASK_REG); val 554 drivers/pinctrl/samsung/pinctrl-s3c64xx.c u32 val; val 573 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(reg); val 574 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val &= ~(EINT_CON_MASK << shift); val 575 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val |= trigger << shift; val 576 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, reg); val 181 drivers/pinctrl/samsung/pinctrl-samsung.c u32 val; val 190 drivers/pinctrl/samsung/pinctrl-samsung.c ret = of_property_read_u32(np, "samsung,pin-function", &val); val 195 drivers/pinctrl/samsung/pinctrl-samsung.c ret = of_property_read_u32(np, cfg_params[i].property, &val); val 197 drivers/pinctrl/samsung/pinctrl-samsung.c config = PINCFG_PACK(cfg_params[i].param, val); val 407 drivers/pinctrl/samsung/pinctrl-samsung.c data |= func->val << shift; val 704 drivers/pinctrl/samsung/pinctrl-samsung.c if (of_property_read_u32(func_np, "samsung,pin-function", &func->val)) val 329 drivers/pinctrl/samsung/pinctrl-samsung.h u32 val; val 513 drivers/pinctrl/sh-pfc/pinctrl.c u32 val; val 520 drivers/pinctrl/sh-pfc/pinctrl.c val = sh_pfc_read(pfc, reg); val 523 drivers/pinctrl/sh-pfc/pinctrl.c val = (val >> offset) & GENMASK(size - 1, 0); val 528 drivers/pinctrl/sh-pfc/pinctrl.c return (val + 1) * (size == 2 ? 6 : 3); val 539 drivers/pinctrl/sh-pfc/pinctrl.c u32 val; val 557 drivers/pinctrl/sh-pfc/pinctrl.c val = sh_pfc_read(pfc, reg); val 558 drivers/pinctrl/sh-pfc/pinctrl.c val &= ~GENMASK(offset + size - 1, offset); val 559 drivers/pinctrl/sh-pfc/pinctrl.c val |= strength << offset; val 561 drivers/pinctrl/sh-pfc/pinctrl.c sh_pfc_write(pfc, reg, val); val 640 drivers/pinctrl/sh-pfc/pinctrl.c u32 pocctrl, val; val 651 drivers/pinctrl/sh-pfc/pinctrl.c val = sh_pfc_read(pfc, pocctrl); val 654 drivers/pinctrl/sh-pfc/pinctrl.c arg = (val & BIT(bit)) ? 3300 : 1800; val 708 drivers/pinctrl/sh-pfc/pinctrl.c u32 pocctrl, val; val 722 drivers/pinctrl/sh-pfc/pinctrl.c val = sh_pfc_read(pfc, pocctrl); val 724 drivers/pinctrl/sh-pfc/pinctrl.c val |= BIT(bit); val 726 drivers/pinctrl/sh-pfc/pinctrl.c val &= ~BIT(bit); val 727 drivers/pinctrl/sh-pfc/pinctrl.c sh_pfc_write(pfc, pocctrl, val); val 5640 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 val, pin_in_bank; val 5649 drivers/pinctrl/sirf/pinctrl-atlas7.c val = readl(ctrl_reg); val 5651 drivers/pinctrl/sirf/pinctrl-atlas7.c writel(val, ctrl_reg); val 5660 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 val, pin_in_bank; val 5666 drivers/pinctrl/sirf/pinctrl-atlas7.c val = readl(ctrl_reg); val 5667 drivers/pinctrl/sirf/pinctrl-atlas7.c val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK | val 5669 drivers/pinctrl/sirf/pinctrl-atlas7.c writel(val, ctrl_reg); val 5691 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 val, pin_in_bank; val 5700 drivers/pinctrl/sirf/pinctrl-atlas7.c val = readl(ctrl_reg); val 5701 drivers/pinctrl/sirf/pinctrl-atlas7.c val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK; val 5702 drivers/pinctrl/sirf/pinctrl-atlas7.c val |= ATLAS7_GPIO_CTL_INTR_EN_MASK; val 5703 drivers/pinctrl/sirf/pinctrl-atlas7.c writel(val, ctrl_reg); val 5715 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 val, pin_in_bank; val 5724 drivers/pinctrl/sirf/pinctrl-atlas7.c val = readl(ctrl_reg); val 5725 drivers/pinctrl/sirf/pinctrl-atlas7.c val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK | val 5733 drivers/pinctrl/sirf/pinctrl-atlas7.c val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK | val 5735 drivers/pinctrl/sirf/pinctrl-atlas7.c val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK; val 5739 drivers/pinctrl/sirf/pinctrl-atlas7.c val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK; val 5740 drivers/pinctrl/sirf/pinctrl-atlas7.c val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK | val 5745 drivers/pinctrl/sirf/pinctrl-atlas7.c val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK | val 5751 drivers/pinctrl/sirf/pinctrl-atlas7.c val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK | val 5753 drivers/pinctrl/sirf/pinctrl-atlas7.c val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK; val 5757 drivers/pinctrl/sirf/pinctrl-atlas7.c val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK; val 5758 drivers/pinctrl/sirf/pinctrl-atlas7.c val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK | val 5763 drivers/pinctrl/sirf/pinctrl-atlas7.c writel(val, ctrl_reg); val 5835 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 val, pin_in_bank; val 5841 drivers/pinctrl/sirf/pinctrl-atlas7.c val = readl(ctrl_reg); val 5842 drivers/pinctrl/sirf/pinctrl-atlas7.c val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK; val 5843 drivers/pinctrl/sirf/pinctrl-atlas7.c writel(val, ctrl_reg); val 5947 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 val, pin_in_bank; val 5955 drivers/pinctrl/sirf/pinctrl-atlas7.c val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank)); val 5959 drivers/pinctrl/sirf/pinctrl-atlas7.c return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK); val 426 drivers/pinctrl/sirf/pinctrl-sirf.c u32 val, offset; val 433 drivers/pinctrl/sirf/pinctrl-sirf.c val = readl(sgpio->chip.regs + offset); val 435 drivers/pinctrl/sirf/pinctrl-sirf.c writel(val, sgpio->chip.regs + offset); val 444 drivers/pinctrl/sirf/pinctrl-sirf.c u32 val, offset; val 451 drivers/pinctrl/sirf/pinctrl-sirf.c val = readl(sgpio->chip.regs + offset); val 452 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; val 453 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; val 454 drivers/pinctrl/sirf/pinctrl-sirf.c writel(val, sgpio->chip.regs + offset); val 474 drivers/pinctrl/sirf/pinctrl-sirf.c u32 val, offset; val 481 drivers/pinctrl/sirf/pinctrl-sirf.c val = readl(sgpio->chip.regs + offset); val 482 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; val 483 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; val 484 drivers/pinctrl/sirf/pinctrl-sirf.c writel(val, sgpio->chip.regs + offset); val 495 drivers/pinctrl/sirf/pinctrl-sirf.c u32 val, offset; val 502 drivers/pinctrl/sirf/pinctrl-sirf.c val = readl(sgpio->chip.regs + offset); val 503 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); val 509 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | val 511 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; val 514 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; val 515 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | val 519 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | val 524 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | val 526 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; val 529 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; val 530 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | val 535 drivers/pinctrl/sirf/pinctrl-sirf.c writel(val, sgpio->chip.regs + offset); val 603 drivers/pinctrl/sirf/pinctrl-sirf.c u32 val; val 605 drivers/pinctrl/sirf/pinctrl-sirf.c val = readl(sgpio->chip.regs + ctrl_offset); val 606 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; val 607 drivers/pinctrl/sirf/pinctrl-sirf.c writel(val, sgpio->chip.regs + ctrl_offset); val 715 drivers/pinctrl/sirf/pinctrl-sirf.c u32 val; val 720 drivers/pinctrl/sirf/pinctrl-sirf.c val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); val 724 drivers/pinctrl/sirf/pinctrl-sirf.c return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); val 756 drivers/pinctrl/sirf/pinctrl-sirf.c u32 val = readl(sgpio->chip.regs + offset); val 757 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_PULL_MASK; val 758 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_PULL_HIGH; val 759 drivers/pinctrl/sirf/pinctrl-sirf.c writel(val, sgpio->chip.regs + offset); val 773 drivers/pinctrl/sirf/pinctrl-sirf.c u32 val = readl(sgpio->chip.regs + offset); val 774 drivers/pinctrl/sirf/pinctrl-sirf.c val |= SIRFSOC_GPIO_CTL_PULL_MASK; val 775 drivers/pinctrl/sirf/pinctrl-sirf.c val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; val 776 drivers/pinctrl/sirf/pinctrl-sirf.c writel(val, sgpio->chip.regs + offset); val 84 drivers/pinctrl/spear/pinctrl-plgpio.c u32 val = readl_relaxed(reg_off); val 86 drivers/pinctrl/spear/pinctrl-plgpio.c return !!(val & (1 << offset)); val 93 drivers/pinctrl/spear/pinctrl-plgpio.c u32 val = readl_relaxed(reg_off); val 95 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(val | (1 << offset), reg_off); val 102 drivers/pinctrl/spear/pinctrl-plgpio.c u32 val = readl_relaxed(reg_off); val 104 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(val & ~(1 << offset), reg_off); val 324 drivers/pinctrl/spear/pinctrl-plgpio.c unsigned int supported_type = 0, val; val 341 drivers/pinctrl/spear/pinctrl-plgpio.c val = readl_relaxed(reg_off); val 345 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(val | (1 << offset), reg_off); val 347 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(val & ~(1 << offset), reg_off); val 449 drivers/pinctrl/spear/pinctrl-plgpio.c u32 val; val 458 drivers/pinctrl/spear/pinctrl-plgpio.c if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) { val 459 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->chip.ngpio = val; val 465 drivers/pinctrl/spear/pinctrl-plgpio.c if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val)) val 466 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->regs.enb = val; val 470 drivers/pinctrl/spear/pinctrl-plgpio.c if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) { val 471 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->regs.wdata = val; val 477 drivers/pinctrl/spear/pinctrl-plgpio.c if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) { val 478 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->regs.dir = val; val 484 drivers/pinctrl/spear/pinctrl-plgpio.c if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) { val 485 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->regs.ie = val; val 491 drivers/pinctrl/spear/pinctrl-plgpio.c if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) { val 492 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->regs.rdata = val; val 498 drivers/pinctrl/spear/pinctrl-plgpio.c if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) { val 499 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->regs.mis = val; val 505 drivers/pinctrl/spear/pinctrl-plgpio.c if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val)) val 506 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->regs.eit = val; val 35 drivers/pinctrl/spear/pinctrl-spear.c u32 val, temp, j; val 40 drivers/pinctrl/spear/pinctrl-spear.c val = pmx_readl(pmx, muxreg->reg); val 41 drivers/pinctrl/spear/pinctrl-spear.c val &= ~muxreg->mask; val 44 drivers/pinctrl/spear/pinctrl-spear.c temp = muxreg->val; val 46 drivers/pinctrl/spear/pinctrl-spear.c temp = ~muxreg->val; val 48 drivers/pinctrl/spear/pinctrl-spear.c val |= muxreg->mask & temp; val 49 drivers/pinctrl/spear/pinctrl-spear.c pmx_writel(pmx, val, muxreg->reg); val 57 drivers/pinctrl/spear/pinctrl-spear.c u32 val; val 72 drivers/pinctrl/spear/pinctrl-spear.c val = pmx_readl(pmx, pmx_mode->reg); val 73 drivers/pinctrl/spear/pinctrl-spear.c val &= ~pmx_mode->mask; val 74 drivers/pinctrl/spear/pinctrl-spear.c val |= pmx_mode->val; val 75 drivers/pinctrl/spear/pinctrl-spear.c pmx_writel(pmx, val, pmx_mode->reg); val 37 drivers/pinctrl/spear/pinctrl-spear.h u32 val; val 49 drivers/pinctrl/spear/pinctrl-spear.h u32 val; val 65 drivers/pinctrl/spear/pinctrl-spear.h .val = __ste ? __mask : 0, \ val 74 drivers/pinctrl/spear/pinctrl-spear.h .val = __ste1 ? __mask : 0, \ val 78 drivers/pinctrl/spear/pinctrl-spear.h .val = __ste2 ? __mask : 0, \ val 190 drivers/pinctrl/spear/pinctrl-spear.h static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) val 192 drivers/pinctrl/spear/pinctrl-spear.h writel_relaxed(val, pmx->vbase + reg); val 242 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2C0_MASK, val 246 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2C0_MASK, val 278 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SSP0_MASK, val 282 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SSP0_MASK, val 307 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SSP0_CS0_MASK, val 311 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SSP0_CS0_MASK, val 336 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SSP0_CS1_2_MASK, val 340 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SSP0_CS1_2_MASK, val 373 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2S0_MASK, val 377 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2S0_MASK, val 409 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2S1_MASK, val 413 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2S1_MASK, val 447 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_CLCD1_MASK, val 451 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_CLCD1_MASK, val 476 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_CLCD2_MASK, val 480 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_CLCD2_MASK, val 512 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_EGPIO_0_GRP_MASK, val 516 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_EGPIO_1_GRP_MASK, val 520 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_EGPIO_0_GRP_MASK, val 524 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_EGPIO_1_GRP_MASK, val 556 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SMI_MASK, val 560 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SMI_MASK, val 584 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SMI_MASK, val 588 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, val 592 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SMI_MASK, val 596 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, val 630 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GMII_MASK, val 634 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GMII_MASK, val 668 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 672 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 676 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 680 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_RGMII_REG0_MASK, val 684 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_RGMII_REG1_MASK, val 688 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_RGMII_REG2_MASK, val 722 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 726 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SMII_0_1_2_MASK, val 758 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 762 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NFCE2_MASK, val 798 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NAND8BIT_0_MASK, val 802 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NAND8BIT_1_MASK, val 806 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NAND8BIT_0_MASK, val 810 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NAND8BIT_1_MASK, val 836 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NAND16BIT_1_MASK, val 840 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NAND16BIT_1_MASK, val 865 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NAND_4CHIPS_MASK, val 869 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NAND_4CHIPS_MASK, val 905 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_KEYBOARD_6X6_MASK, val 930 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_KBD_ROWCOL68_MASK, val 934 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_KBD_ROWCOL68_MASK, val 967 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_UART0_MASK, val 971 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_UART0_MASK, val 996 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_UART0_MODEM_MASK, val 1000 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_UART0_MODEM_MASK, val 1032 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GPT0_TMR0_MASK, val 1036 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GPT0_TMR0_MASK, val 1061 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GPT0_TMR1_MASK, val 1065 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GPT0_TMR1_MASK, val 1097 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GPT1_TMR0_MASK, val 1101 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GPT1_TMR0_MASK, val 1126 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GPT1_TMR1_MASK, val 1130 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_GPT1_TMR1_MASK, val 1165 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCI_DATA8_15_MASK, \ val 1170 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIFALL_1_MASK, \ val 1174 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIFALL_2_MASK, \ val 1178 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCI_DATA8_15_MASK, \ val 1183 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ val 1188 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIFALL_2_MASK, \ val 1197 drivers/pinctrl/spear/pinctrl-spear1310.c .val = MCIF_SEL_SD, val 1229 drivers/pinctrl/spear/pinctrl-spear1310.c .val = MCIF_SEL_CF, val 1261 drivers/pinctrl/spear/pinctrl-spear1310.c .val = MCIF_SEL_XD, val 1293 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_TOUCH_XY_MASK, val 1297 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_TOUCH_XY_MASK, val 1330 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1334 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2C0_MASK, val 1360 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1365 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIDATA1_MASK | val 1399 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1403 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2S0_MASK, val 1435 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1439 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2S0_MASK | PMX_CLCD1_MASK, val 1471 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1475 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_CLCD1_MASK, val 1509 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1513 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_CLCD1_MASK, val 1545 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1549 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_CLCD1_MASK, val 1582 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1586 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_CLCD1_MASK | PMX_SMI_MASK, val 1612 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1616 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, val 1650 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1654 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_SMI_MASK, val 1680 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1684 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1688 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIDATA4_MASK, val 1692 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIDATA5_MASK, val 1719 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1724 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIDATA6_MASK | val 1759 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1763 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_KBD_ROWCOL25_MASK, val 1790 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1795 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIIORDRE_MASK | val 1822 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1827 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIRESETCF_MASK | val 1862 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1866 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1870 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NFRSTPWDWN2_MASK, val 1874 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_NFRSTPWDWN3_MASK, val 1900 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1904 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, val 1938 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1942 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, val 1968 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 1972 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_KBD_ROWCOL25_MASK, val 2009 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 2013 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 2017 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 2021 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCI_DATA8_15_MASK, val 2025 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_PCI_REG1_MASK, val 2029 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_PCI_REG2_MASK, val 2060 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PCIE_CFG_VAL(0), val 2082 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PCIE_CFG_VAL(1), val 2104 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PCIE_CFG_VAL(2), val 2134 drivers/pinctrl/spear/pinctrl-spear1310.c .val = SATA_CFG_VAL(0), val 2156 drivers/pinctrl/spear/pinctrl-spear1310.c .val = SATA_CFG_VAL(1), val 2178 drivers/pinctrl/spear/pinctrl-spear1310.c .val = SATA_CFG_VAL(2), val 2211 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 2217 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | val 2245 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 2250 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | val 2285 drivers/pinctrl/spear/pinctrl-spear1310.c .val = 0, val 2290 drivers/pinctrl/spear/pinctrl-spear1310.c .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK val 220 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 224 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 228 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 232 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 236 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 240 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 244 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 248 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 281 drivers/pinctrl/spear/pinctrl-spear1340.c .val = FSMC_8BIT_REG7_MASK, val 306 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 310 drivers/pinctrl/spear/pinctrl-spear1340.c .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, val 337 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 341 drivers/pinctrl/spear/pinctrl-spear1340.c .val = FSMC_PNOR_AND_MCIF_REG6_MASK, val 375 drivers/pinctrl/spear/pinctrl-spear1340.c .val = KBD_ROW_COL_MASK, val 379 drivers/pinctrl/spear/pinctrl-spear1340.c .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, val 404 drivers/pinctrl/spear/pinctrl-spear1340.c .val = KBD_COL5_MASK, val 408 drivers/pinctrl/spear/pinctrl-spear1340.c .val = PWM1_AND_KBD_COL5_REG0_MASK, val 441 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SPDIF_IN_REG0_MASK, val 473 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SPDIF_OUT_REG4_MASK, val 477 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SPDIF_OUT_ENB_MASK, val 509 drivers/pinctrl/spear/pinctrl-spear1340.c .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, val 515 drivers/pinctrl/spear/pinctrl-spear1340.c .val = UART0_ENH_AND_GPT_REG0_MASK | val 549 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 553 drivers/pinctrl/spear/pinctrl-spear1340.c .val = PWM0_AND_SSP0_CS1_REG0_MASK, val 578 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 582 drivers/pinctrl/spear/pinctrl-spear1340.c .val = PWM1_AND_KBD_COL5_REG0_MASK, val 607 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 611 drivers/pinctrl/spear/pinctrl-spear1340.c .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, val 636 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 640 drivers/pinctrl/spear/pinctrl-spear1340.c .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, val 673 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_REG1_MASK, val 699 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 703 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM0_REG2_MASK, val 729 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 733 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM1_REG1_MASK, val 737 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM1_REG2_MASK, val 763 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 767 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM2_REG1_MASK, val 793 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 797 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM3_REG0_MASK, val 801 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM3_REG1_MASK, val 835 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CAM0_MASK, val 839 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM0_REG2_MASK, val 872 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CAM1_MASK, val 876 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM1_REG1_MASK, val 880 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM1_REG2_MASK, val 913 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CAM2_MASK, val 917 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM2_REG1_MASK, val 950 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CAM3_MASK, val 954 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM3_REG0_MASK, val 958 drivers/pinctrl/spear/pinctrl-spear1340.c .val = VIP_AND_CAM3_REG1_MASK, val 990 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SMI_REG2_MASK, val 1022 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SSP0_REG2_MASK, val 1047 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SSP0_CS1_MASK, val 1051 drivers/pinctrl/spear/pinctrl-spear1340.c .val = PWM0_AND_SSP0_CS1_REG0_MASK, val 1076 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SSP0_CS2_MASK, val 1080 drivers/pinctrl/spear/pinctrl-spear1340.c .val = TS_AND_SSP0_CS2_REG2_MASK, val 1105 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SSP0_CS3_REG4_MASK, val 1138 drivers/pinctrl/spear/pinctrl-spear1340.c .val = UART0_REG2_MASK, val 1163 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 1167 drivers/pinctrl/spear/pinctrl-spear1340.c .val = UART0_ENH_AND_GPT_REG0_MASK, val 1199 drivers/pinctrl/spear/pinctrl-spear1340.c .val = UART1_REG2_MASK, val 1231 drivers/pinctrl/spear/pinctrl-spear1340.c .val = I2S_IN_REG2_MASK, val 1235 drivers/pinctrl/spear/pinctrl-spear1340.c .val = I2S_IN_REG3_MASK, val 1260 drivers/pinctrl/spear/pinctrl-spear1340.c .val = I2S_OUT_REG3_MASK, val 1294 drivers/pinctrl/spear/pinctrl-spear1340.c .val = GMAC_REG3_MASK, \ val 1298 drivers/pinctrl/spear/pinctrl-spear1340.c .val = GMAC_REG4_MASK, \ val 1307 drivers/pinctrl/spear/pinctrl-spear1340.c .val = GMAC_PHY_IF_GMII_VAL, val 1332 drivers/pinctrl/spear/pinctrl-spear1340.c .val = GMAC_PHY_IF_RGMII_VAL, val 1357 drivers/pinctrl/spear/pinctrl-spear1340.c .val = GMAC_PHY_IF_RMII_VAL, val 1382 drivers/pinctrl/spear/pinctrl-spear1340.c .val = GMAC_PHY_IF_SGMII_VAL, val 1415 drivers/pinctrl/spear/pinctrl-spear1340.c .val = I2C0_REG4_MASK, val 1447 drivers/pinctrl/spear/pinctrl-spear1340.c .val = I2C1_REG0_MASK, val 1479 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CEC0_REG4_MASK, val 1511 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CEC1_REG4_MASK, val 1546 drivers/pinctrl/spear/pinctrl-spear1340.c .val = MCIF_MASK, \ val 1550 drivers/pinctrl/spear/pinctrl-spear1340.c .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ val 1554 drivers/pinctrl/spear/pinctrl-spear1340.c .val = MCIF_REG7_MASK, \ val 1563 drivers/pinctrl/spear/pinctrl-spear1340.c .val = MCIF_SEL_SD, val 1595 drivers/pinctrl/spear/pinctrl-spear1340.c .val = MCIF_SEL_CF, val 1627 drivers/pinctrl/spear/pinctrl-spear1340.c .val = MCIF_SEL_XD, val 1663 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 1667 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, val 1671 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CLCD_AND_ARM_TRACE_REG5_MASK, val 1675 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CLCD_AND_ARM_TRACE_REG6_MASK, val 1699 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0, val 1703 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 1707 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 1711 drivers/pinctrl/spear/pinctrl-spear1340.c .val = 0x0, val 1746 drivers/pinctrl/spear/pinctrl-spear1340.c .val = ARM_TRACE_MASK, val 1750 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CLCD_AND_ARM_TRACE_REG4_MASK, val 1754 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CLCD_AND_ARM_TRACE_REG5_MASK, val 1758 drivers/pinctrl/spear/pinctrl-spear1340.c .val = CLCD_AND_ARM_TRACE_REG6_MASK, val 1792 drivers/pinctrl/spear/pinctrl-spear1340.c .val = MIPHY_DBG_MASK, val 1796 drivers/pinctrl/spear/pinctrl-spear1340.c .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, val 1828 drivers/pinctrl/spear/pinctrl-spear1340.c .val = PCIE_CFG_VAL, val 1860 drivers/pinctrl/spear/pinctrl-spear1340.c .val = SATA_CFG_VAL, val 1977 drivers/pinctrl/spear/pinctrl-spear1340.c unsigned int val; val 1990 drivers/pinctrl/spear/pinctrl-spear1340.c val = pmx_readl(pmx, regoffset); val 1992 drivers/pinctrl/spear/pinctrl-spear1340.c val &= ~(0x1 << bitoffset); val 1994 drivers/pinctrl/spear/pinctrl-spear1340.c val |= 0x1 << bitoffset; val 1996 drivers/pinctrl/spear/pinctrl-spear1340.c pmx_writel(pmx, val, regoffset); val 44 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x00, val 52 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x01, val 60 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x02, val 68 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x03, val 76 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x04, val 84 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x05, val 92 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x06, val 100 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x07, val 108 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x08, val 116 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x0C, val 124 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x0D, val 132 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0xE, val 140 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0x0F, val 165 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 192 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 227 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 254 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 288 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 325 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 361 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 387 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 420 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 454 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 492 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 524 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 560 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 587 drivers/pinctrl/spear/pinctrl-spear300.c .val = 0, val 29 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 61 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 93 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 125 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 157 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 189 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 221 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 253 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 285 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 317 drivers/pinctrl/spear/pinctrl-spear310.c .val = 0, val 37 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0x0, val 45 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0x1, val 53 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0x2, val 61 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0x3, val 69 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0x1, val 466 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_CLCD_PL_69_VAL, val 472 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL | val 479 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL | val 485 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL | val 523 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 531 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, val 536 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL | val 542 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_EMI_PL_69_VAL, val 548 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | val 555 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL | val 561 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL | val 566 drivers/pinctrl/spear/pinctrl-spear320.c .val = EMI_FSMC_DYNAMIC_MUX_MASK, val 605 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL | val 611 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL | val 616 drivers/pinctrl/spear/pinctrl-spear320.c .val = EMI_FSMC_DYNAMIC_MUX_MASK, val 642 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 650 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, val 654 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | val 697 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SPP_PL_69_VAL, val 703 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL | val 709 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SPP_PL_80_TO_85_VAL, val 742 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 750 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM2_PL_34_VAL, val 782 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 791 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL | val 796 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SDHCI_PL_50_VAL, val 800 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SDHCI_PL_99_VAL, val 804 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SDHCI_PL_100_101_VAL, val 812 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 816 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SDHCI_CD_PL_12_VAL, val 820 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SDHCI_CD_PORT_12_VAL, val 828 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SDHCI_CD_PL_51_VAL, val 832 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SDHCI_CD_PORT_51_VAL, val 899 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 903 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 911 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL, val 915 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL, val 952 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 960 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_PL_28_29_VAL, val 1002 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1006 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL | val 1011 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL, val 1020 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1029 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL | val 1035 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL, val 1044 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1052 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | val 1057 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, val 1061 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL, val 1069 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PL_80_TO_85_VAL, val 1073 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, val 1077 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART1_ENH_PORT_81_TO_85_VAL, val 1164 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1172 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART2_PL_0_1_VAL, val 1212 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1216 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PL_8_9_VAL, val 1220 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PORT_8_VAL, val 1228 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1232 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PL_15_16_VAL, val 1236 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PORT_15_VAL, val 1244 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1248 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PL_41_42_VAL, val 1252 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PORT_41_VAL, val 1260 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PL_52_53_VAL, val 1264 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PORT_52_VAL, val 1272 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL, val 1276 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PORT_73_VAL, val 1284 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PL_94_95_VAL, val 1288 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PORT_94_VAL, val 1296 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL, val 1300 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART3_PORT_99_VAL, val 1421 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1425 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PL_6_7_VAL, val 1429 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PORT_6_VAL, val 1437 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1441 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PL_13_14_VAL, val 1445 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PORT_13_VAL, val 1453 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1457 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PL_39_VAL, val 1461 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PL_40_VAL, val 1465 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PORT_39_VAL, val 1473 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PL_71_72_VAL, val 1477 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PORT_71_VAL, val 1485 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PL_92_93_VAL, val 1489 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PORT_92_VAL, val 1498 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART4_PL_100_101_VAL | val 1607 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1611 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PL_4_5_VAL, val 1615 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PORT_4_VAL, val 1623 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1627 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PL_37_38_VAL, val 1631 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PORT_37_VAL, val 1639 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PL_69_VAL, val 1643 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PL_70_VAL, val 1647 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PORT_69_VAL, val 1655 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PL_90_91_VAL, val 1659 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART5_PORT_90_VAL, val 1737 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1741 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART6_PL_2_3_VAL, val 1745 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART6_PORT_2_VAL, val 1753 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART6_PL_88_89_VAL, val 1757 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_UART6_PORT_88_VAL, val 1808 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_RS485_PL_77_78_79_VAL, val 1841 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1849 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_TOUCH_Y_PL_5_VAL, val 1853 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_TOUCH_X_PL_36_VAL, val 1890 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1898 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_CAN0_PL_32_33_VAL, val 1935 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1943 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_CAN1_PL_30_31_VAL, val 1983 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 1987 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM_0_1_PL_8_9_VAL, val 1995 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2003 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL, val 2011 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2015 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL, val 2023 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2031 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM0_1_PL_37_38_VAL, val 2039 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2043 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM1_PL_42_VAL | val 2052 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM1_PL_59_VAL, val 2056 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM0_PL_60_VAL, val 2064 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM0_1_PL_88_89_VAL, val 2196 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2204 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM_2_PL_7_VAL, val 2212 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2220 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM2_PL_13_VAL, val 2228 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2232 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM_2_PL_29_VAL, val 2240 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2244 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM_MASK, val 2248 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM2_PL_34_VAL, val 2256 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2260 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM2_PL_41_VAL, val 2268 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM2_PL_58_VAL, val 2276 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM2_PL_87_VAL, val 2403 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2407 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM_3_PL_6_VAL, val 2415 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2423 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM3_PL_12_VAL, val 2431 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2435 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM_3_PL_28_VAL, val 2443 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2447 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM3_PL_40_VAL, val 2455 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM3_PL_57_VAL, val 2463 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_PWM3_PL_86_VAL, val 2576 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2584 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PL_17_18_19_20_VAL, val 2588 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PL_17_18_19_20_VAL, val 2592 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PORT_17_TO_20_VAL, val 2600 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2604 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL | val 2609 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PORT_36_TO_39_VAL, val 2617 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2621 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PL_48_49_VAL, val 2625 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PL_50_51_VAL, val 2629 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PORT_48_TO_51_VAL, val 2637 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PL_65_TO_68_VAL, val 2641 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PORT_65_TO_68_VAL, val 2649 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL, val 2653 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP1_PORT_94_TO_97_VAL, val 2751 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2759 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PL_13_14_15_16_VAL, val 2763 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PORT_13_TO_16_VAL, val 2772 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2776 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL | val 2781 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PORT_32_TO_35_VAL, val 2789 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2793 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL, val 2797 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PORT_44_TO_47_VAL, val 2805 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PL_61_TO_64_VAL, val 2809 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PORT_61_TO_64_VAL, val 2817 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL, val 2821 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SSP2_PORT_90_TO_93_VAL, val 2919 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL | val 2925 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL | val 2932 drivers/pinctrl/spear/pinctrl-spear320.c .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) | val 2969 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 2977 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SMII_PL_10_11_VAL, val 2981 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_SMII_PL_21_TO_27_VAL, val 2987 drivers/pinctrl/spear/pinctrl-spear320.c .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT) val 2998 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL | val 3004 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL, val 3010 drivers/pinctrl/spear/pinctrl-spear320.c .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT) val 3073 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 3077 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C1_PL_8_9_VAL, val 3081 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C1_PORT_8_9_VAL, val 3089 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL, val 3093 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C1_PORT_98_99_VAL, val 3145 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 3149 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PL_0_1_VAL, val 3153 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PORT_0_1_VAL, val 3161 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 3165 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PL_2_3_VAL, val 3169 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PORT_2_3_VAL, val 3177 drivers/pinctrl/spear/pinctrl-spear320.c .val = 0, val 3181 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PL_19_VAL, val 3185 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PL_20_VAL, val 3189 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PORT_19_20_VAL, val 3197 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PL_75_76_VAL, val 3201 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PORT_75_76_VAL, val 3209 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PL_96_97_VAL, val 3213 drivers/pinctrl/spear/pinctrl-spear320.c .val = PMX_I2C2_PORT_96_97_VAL, val 27 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_FIRDA_MASK, val 60 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_I2C_MASK, val 93 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_SSP_CS_MASK, val 126 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_SSP_MASK, val 160 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_MII_MASK, val 193 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_GPIO_PIN0_MASK, val 219 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_GPIO_PIN1_MASK, val 245 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_GPIO_PIN2_MASK, val 271 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_GPIO_PIN3_MASK, val 297 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_GPIO_PIN4_MASK, val 323 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_GPIO_PIN5_MASK, val 358 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_UART0_MODEM_MASK, val 391 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_UART0_MASK, val 424 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_TIMER_0_1_MASK, val 457 drivers/pinctrl/spear/pinctrl-spear3xx.c .val = PMX_TIMER_2_3_MASK, val 391 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned int val = 0; val 398 drivers/pinctrl/sprd/pinctrl-sprd.c val &= PIN_FUNC_SEL_1; val 401 drivers/pinctrl/sprd/pinctrl-sprd.c val |= PIN_FUNC_SEL_2; val 404 drivers/pinctrl/sprd/pinctrl-sprd.c val |= PIN_FUNC_SEL_3; val 407 drivers/pinctrl/sprd/pinctrl-sprd.c val |= PIN_FUNC_SEL_4; val 422 drivers/pinctrl/sprd/pinctrl-sprd.c reg |= val; val 503 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned int val = 0; val 509 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(19); val 512 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(20); val 515 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(19) | BIT(20); val 518 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(21); val 521 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(21) | BIT(19); val 524 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(21) | BIT(20); val 527 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(19) | BIT(20) | BIT(21); val 530 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22); val 533 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(19); val 536 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(20); val 539 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(20) | BIT(19); val 542 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(21); val 545 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(21) | BIT(19); val 548 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(21) | BIT(20); val 551 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(21) | BIT(20) | BIT(19); val 557 drivers/pinctrl/sprd/pinctrl-sprd.c return val; val 590 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned int param, arg, shift, mask, val; val 595 drivers/pinctrl/sprd/pinctrl-sprd.c val = 0; val 600 drivers/pinctrl/sprd/pinctrl-sprd.c val = arg; val 605 drivers/pinctrl/sprd/pinctrl-sprd.c val |= AP_SLEEP_MODE; val 607 drivers/pinctrl/sprd/pinctrl-sprd.c val |= PUBCP_SLEEP_MODE; val 609 drivers/pinctrl/sprd/pinctrl-sprd.c val |= TGLDSP_SLEEP_MODE; val 611 drivers/pinctrl/sprd/pinctrl-sprd.c val |= AGDSP_SLEEP_MODE; val 619 drivers/pinctrl/sprd/pinctrl-sprd.c val |= SLEEP_INPUT; val 621 drivers/pinctrl/sprd/pinctrl-sprd.c val &= ~SLEEP_INPUT; val 629 drivers/pinctrl/sprd/pinctrl-sprd.c val |= SLEEP_OUTPUT; val 638 drivers/pinctrl/sprd/pinctrl-sprd.c val = sprd_pinconf_drive(arg); val 644 drivers/pinctrl/sprd/pinctrl-sprd.c val |= SLEEP_PULL_DOWN; val 648 drivers/pinctrl/sprd/pinctrl-sprd.c val |= PULL_DOWN; val 655 drivers/pinctrl/sprd/pinctrl-sprd.c val |= INPUT_SCHMITT; val 657 drivers/pinctrl/sprd/pinctrl-sprd.c val &= ~INPUT_SCHMITT; val 664 drivers/pinctrl/sprd/pinctrl-sprd.c val |= SLEEP_PULL_UP; val 669 drivers/pinctrl/sprd/pinctrl-sprd.c val |= PULL_UP_20K; val 671 drivers/pinctrl/sprd/pinctrl-sprd.c val |= PULL_UP_4_7K; val 690 drivers/pinctrl/sprd/pinctrl-sprd.c reg |= (val & PINCTRL_BIT_MASK(pin->bit_width)) val 696 drivers/pinctrl/sprd/pinctrl-sprd.c reg |= val; val 693 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 710 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + alt_offset); val 711 drivers/pinctrl/stm32/pinctrl-stm32.c val &= ~GENMASK(alt_shift + 3, alt_shift); val 712 drivers/pinctrl/stm32/pinctrl-stm32.c val |= (alt << alt_shift); val 713 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + alt_offset); val 715 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_MODER); val 716 drivers/pinctrl/stm32/pinctrl-stm32.c val &= ~GENMASK(pin * 2 + 1, pin * 2); val 717 drivers/pinctrl/stm32/pinctrl-stm32.c val |= mode << (pin * 2); val 718 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_MODER); val 735 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 743 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + alt_offset); val 744 drivers/pinctrl/stm32/pinctrl-stm32.c val &= GENMASK(alt_shift + 3, alt_shift); val 745 drivers/pinctrl/stm32/pinctrl-stm32.c *alt = val >> alt_shift; val 747 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_MODER); val 748 drivers/pinctrl/stm32/pinctrl-stm32.c val &= GENMASK(pin * 2 + 1, pin * 2); val 749 drivers/pinctrl/stm32/pinctrl-stm32.c *mode = val >> (pin * 2); val 815 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 829 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_TYPER); val 830 drivers/pinctrl/stm32/pinctrl-stm32.c val &= ~BIT(offset); val 831 drivers/pinctrl/stm32/pinctrl-stm32.c val |= drive << offset; val 832 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_TYPER); val 850 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 855 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_TYPER); val 856 drivers/pinctrl/stm32/pinctrl-stm32.c val &= BIT(offset); val 861 drivers/pinctrl/stm32/pinctrl-stm32.c return (val >> offset); val 869 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 883 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); val 884 drivers/pinctrl/stm32/pinctrl-stm32.c val &= ~GENMASK(offset * 2 + 1, offset * 2); val 885 drivers/pinctrl/stm32/pinctrl-stm32.c val |= speed << (offset * 2); val 886 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); val 904 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 909 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); val 910 drivers/pinctrl/stm32/pinctrl-stm32.c val &= GENMASK(offset * 2 + 1, offset * 2); val 915 drivers/pinctrl/stm32/pinctrl-stm32.c return (val >> (offset * 2)); val 923 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 937 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); val 938 drivers/pinctrl/stm32/pinctrl-stm32.c val &= ~GENMASK(offset * 2 + 1, offset * 2); val 939 drivers/pinctrl/stm32/pinctrl-stm32.c val |= bias << (offset * 2); val 940 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); val 958 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 963 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); val 964 drivers/pinctrl/stm32/pinctrl-stm32.c val &= GENMASK(offset * 2 + 1, offset * 2); val 969 drivers/pinctrl/stm32/pinctrl-stm32.c return (val >> (offset * 2)); val 976 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val; val 982 drivers/pinctrl/stm32/pinctrl-stm32.c val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & val 985 drivers/pinctrl/stm32/pinctrl-stm32.c val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & val 991 drivers/pinctrl/stm32/pinctrl-stm32.c return val; val 1087 drivers/pinctrl/stm32/pinctrl-stm32.c bool val; val 1104 drivers/pinctrl/stm32/pinctrl-stm32.c val = stm32_pconf_get(bank, offset, true); val 1106 drivers/pinctrl/stm32/pinctrl-stm32.c val ? "high" : "low", val 1114 drivers/pinctrl/stm32/pinctrl-stm32.c val = stm32_pconf_get(bank, offset, false); val 1116 drivers/pinctrl/stm32/pinctrl-stm32.c val ? "high" : "low", val 1490 drivers/pinctrl/stm32/pinctrl-stm32.c u32 val, alt, mode, offset = stm32_gpio_pin(pin); val 1517 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); val 1518 drivers/pinctrl/stm32/pinctrl-stm32.c val = val >> STM32_GPIO_BKP_VAL; val 1519 drivers/pinctrl/stm32/pinctrl-stm32.c __stm32_gpio_set(bank, offset, val); val 1522 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); val 1523 drivers/pinctrl/stm32/pinctrl-stm32.c val >>= STM32_GPIO_BKP_TYPE; val 1524 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_driving(bank, offset, val); val 1528 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; val 1529 drivers/pinctrl/stm32/pinctrl-stm32.c val >>= STM32_GPIO_BKP_SPEED_SHIFT; val 1530 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_speed(bank, offset, val); val 1534 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; val 1535 drivers/pinctrl/stm32/pinctrl-stm32.c val >>= STM32_GPIO_BKP_PUPD_SHIFT; val 1536 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_bias(bank, offset, val); val 170 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val; val 183 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (of_property_read_u32(node, "allwinner,pull", &val)) val 186 drivers/pinctrl/sunxi/pinctrl-sunxi.c switch (val) { val 200 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val; val 203 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (!of_property_read_u32(node, "drive-strength", &val)) { val 205 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (val < 10) val 209 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (val > 40) val 210 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 40; val 213 drivers/pinctrl/sunxi/pinctrl-sunxi.c return rounddown(val, 10); val 217 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (of_property_read_u32(node, "allwinner,drive", &val)) val 220 drivers/pinctrl/sunxi/pinctrl-sunxi.c return (val + 1) * 10; val 476 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 offset, shift, mask, val; val 486 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = (readl(pctl->membase + offset) >> shift) & mask; val 490 drivers/pinctrl/sunxi/pinctrl-sunxi.c arg = (val + 1) * 10; val 494 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (val != SUN4I_PINCTRL_PULL_UP) val 500 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (val != SUN4I_PINCTRL_PULL_DOWN) val 506 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (val != SUN4I_PINCTRL_NO_PULL) val 543 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 arg, val; val 564 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = arg / 10 - 1; val 567 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 0; val 572 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 1; val 577 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 2; val 588 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(reg | val << shift, pctl->membase + offset); val 619 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val, reg; val 640 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 0x0; /* 1.8V */ val 642 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 0x6; /* 2.5V */ val 644 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 0x9; /* 2.8V */ val 646 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 0xA; /* 3.0V */ val 648 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = 0xD; /* 3.3V */ val 654 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); val 657 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = uV <= 1800000 ? 1 : 0; val 662 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); val 704 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val, mask; val 709 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = readl(pctl->membase + sunxi_mux_reg(pin)); val 711 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel((val & ~mask) | config << sunxi_mux_offset(pin), val 848 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val; val 853 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; val 858 drivers/pinctrl/sunxi/pinctrl-sunxi.c return !!val; val 1027 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val; val 1032 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = readl(pctl->membase + reg); val 1033 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(val & ~(1 << idx), pctl->membase + reg); val 1044 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val; val 1049 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = readl(pctl->membase + reg); val 1050 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(val | (1 << idx), pctl->membase + reg); val 1124 drivers/pinctrl/sunxi/pinctrl-sunxi.c unsigned long bank, reg, val; val 1134 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = readl(pctl->membase + reg); val 1136 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (val) { val 1140 drivers/pinctrl/sunxi/pinctrl-sunxi.c for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { val 33 drivers/pinctrl/tegra/pinctrl-tegra.c static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) val 35 drivers/pinctrl/tegra/pinctrl-tegra.c writel_relaxed(val, pmx->regs[bank] + reg); val 108 drivers/pinctrl/tegra/pinctrl-tegra.c u32 val; val 126 drivers/pinctrl/tegra/pinctrl-tegra.c ret = of_property_read_u32(np, cfg_params[i].property, &val); val 128 drivers/pinctrl/tegra/pinctrl-tegra.c config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); val 256 drivers/pinctrl/tegra/pinctrl-tegra.c u32 val; val 270 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, g->mux_bank, g->mux_reg); val 271 drivers/pinctrl/tegra/pinctrl-tegra.c val &= ~(0x3 << g->mux_bit); val 272 drivers/pinctrl/tegra/pinctrl-tegra.c val |= i << g->mux_bit; val 273 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_writel(pmx, val, g->mux_bank, g->mux_reg); val 449 drivers/pinctrl/tegra/pinctrl-tegra.c u32 val, mask; val 458 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); val 460 drivers/pinctrl/tegra/pinctrl-tegra.c arg = (val >> bit) & mask; val 478 drivers/pinctrl/tegra/pinctrl-tegra.c u32 val, mask; val 491 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); val 495 drivers/pinctrl/tegra/pinctrl-tegra.c if ((val & BIT(bit)) && !arg) { val 515 drivers/pinctrl/tegra/pinctrl-tegra.c val &= ~(mask << bit); val 516 drivers/pinctrl/tegra/pinctrl-tegra.c val |= arg << bit; val 517 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_writel(pmx, val, bank, reg); val 546 drivers/pinctrl/tegra/pinctrl-tegra.c u32 val; val 556 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); val 557 drivers/pinctrl/tegra/pinctrl-tegra.c val >>= bit; val 558 drivers/pinctrl/tegra/pinctrl-tegra.c val &= (1 << width) - 1; val 561 drivers/pinctrl/tegra/pinctrl-tegra.c strip_prefix(cfg_params[i].property), val); val 614 drivers/pinctrl/tegra/pinctrl-tegra.c u32 val; val 629 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); val 630 drivers/pinctrl/tegra/pinctrl-tegra.c val &= ~g->parked_bitmask; val 631 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_writel(pmx, val, bank, reg); val 165 drivers/pinctrl/ti/pinctrl-ti-iodelay.c static inline u32 ti_iodelay_extract(u32 val, u32 mask) val 167 drivers/pinctrl/ti/pinctrl-ti-iodelay.c return (val & mask) >> __ffs(mask); val 286 drivers/pinctrl/ti/pinctrl-ti-iodelay.c u32 val; val 296 drivers/pinctrl/ti/pinctrl-ti-iodelay.c r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val); val 299 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask); val 302 drivers/pinctrl/ti/pinctrl-ti-iodelay.c r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val); val 306 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ti_iodelay_extract(val, reg->coarse_ref_count_mask); val 308 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ti_iodelay_extract(val, reg->coarse_delay_count_mask); val 311 drivers/pinctrl/ti/pinctrl-ti-iodelay.c val); val 326 drivers/pinctrl/ti/pinctrl-ti-iodelay.c r = regmap_read(iod->regmap, reg->reg_fine_offset, &val); val 330 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ti_iodelay_extract(val, reg->fine_ref_count_mask); val 332 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ti_iodelay_extract(val, reg->fine_delay_count_mask); val 335 drivers/pinctrl/ti/pinctrl-ti-iodelay.c val); val 212 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int pupdctrl, reg, shift, val; val 246 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_read(priv->regmap, reg, &val); val 250 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c val = (val >> shift) & 1; val 252 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c return (val == expected) ? 0 : -EINVAL; val 259 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, shift, mask, val; val 269 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_read(priv->regmap, reg, &val); val 273 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c val = 0; val 276 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c *strength = strengths[(val >> shift) & mask]; val 287 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, mask, val; val 300 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_read(priv->regmap, reg, &val); val 304 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c return val & mask ? 0 : -EINVAL; val 350 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int val = 1; val 363 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c val = 0; val 413 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift); val 421 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, shift, mask, val; val 433 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c for (val = 0; val <= mask; val++) { val 434 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c if (strengths[val] > strength) val 438 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c if (val == 0) { val 448 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c val--; val 451 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c mask << shift, val << shift); val 29 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 val; val 31 drivers/pinctrl/vt8500/pinctrl-wmt.c val = readl_relaxed(data->base + reg); val 32 drivers/pinctrl/vt8500/pinctrl-wmt.c val |= mask; val 33 drivers/pinctrl/vt8500/pinctrl-wmt.c writel_relaxed(val, data->base + reg); val 39 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 val; val 41 drivers/pinctrl/vt8500/pinctrl-wmt.c val = readl_relaxed(data->base + reg); val 42 drivers/pinctrl/vt8500/pinctrl-wmt.c val &= ~mask; val 43 drivers/pinctrl/vt8500/pinctrl-wmt.c writel_relaxed(val, data->base + reg); val 486 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 val; val 488 drivers/pinctrl/vt8500/pinctrl-wmt.c val = readl_relaxed(data->base + reg_dir); val 490 drivers/pinctrl/vt8500/pinctrl-wmt.c return !(val & BIT(bit)); val 509 drivers/pinctrl/vt8500/pinctrl-wmt.c int val) val 521 drivers/pinctrl/vt8500/pinctrl-wmt.c if (val) val 68 drivers/pinctrl/zte/pinctrl-zx.c u32 val, mval; val 108 drivers/pinctrl/zte/pinctrl-zx.c val = readl(zpctl->aux_base + aoffset); val 109 drivers/pinctrl/zte/pinctrl-zx.c val &= ~(0x3 << abitpos); val 110 drivers/pinctrl/zte/pinctrl-zx.c val |= (mval & 0x3) << abitpos; val 111 drivers/pinctrl/zte/pinctrl-zx.c writel(val, zpctl->aux_base + aoffset); val 117 drivers/pinctrl/zte/pinctrl-zx.c val = readl(zpctl->base + offset); val 118 drivers/pinctrl/zte/pinctrl-zx.c val &= ~(mask << bitpos); val 119 drivers/pinctrl/zte/pinctrl-zx.c val |= (mval & mask) << bitpos; val 120 drivers/pinctrl/zte/pinctrl-zx.c writel(val, zpctl->base + offset); val 126 drivers/pinctrl/zte/pinctrl-zx.c val = readl(zpctl->aux_base + aoffset); val 127 drivers/pinctrl/zte/pinctrl-zx.c val &= ~(0x3 << abitpos); val 128 drivers/pinctrl/zte/pinctrl-zx.c val |= NONAON_MVAL << abitpos; val 129 drivers/pinctrl/zte/pinctrl-zx.c writel(val, zpctl->aux_base + aoffset); val 137 drivers/pinctrl/zte/pinctrl-zx.c val = readl(zpctl->base + offset); val 138 drivers/pinctrl/zte/pinctrl-zx.c val &= ~(mask << bitpos); val 139 drivers/pinctrl/zte/pinctrl-zx.c val |= (mval & mask) << bitpos; val 140 drivers/pinctrl/zte/pinctrl-zx.c writel(val, zpctl->base + offset); val 163 drivers/pinctrl/zte/pinctrl-zx.c u32 val; val 169 drivers/pinctrl/zte/pinctrl-zx.c val = readl(zpctl->aux_base + data->coffset); val 170 drivers/pinctrl/zte/pinctrl-zx.c val = val >> data->cbitpos; val 174 drivers/pinctrl/zte/pinctrl-zx.c val &= ZX_PULL_DOWN; val 175 drivers/pinctrl/zte/pinctrl-zx.c val = !!val; val 176 drivers/pinctrl/zte/pinctrl-zx.c if (val == 0) val 180 drivers/pinctrl/zte/pinctrl-zx.c val &= ZX_PULL_UP; val 181 drivers/pinctrl/zte/pinctrl-zx.c val = !!val; val 182 drivers/pinctrl/zte/pinctrl-zx.c if (val == 0) val 186 drivers/pinctrl/zte/pinctrl-zx.c val &= ZX_INPUT_ENABLE; val 187 drivers/pinctrl/zte/pinctrl-zx.c val = !!val; val 188 drivers/pinctrl/zte/pinctrl-zx.c if (val == 0) val 192 drivers/pinctrl/zte/pinctrl-zx.c val &= ZX_DS_MASK; val 193 drivers/pinctrl/zte/pinctrl-zx.c val = val >> ZX_DS_SHIFT; val 196 drivers/pinctrl/zte/pinctrl-zx.c val &= ZX_SLEW; val 197 drivers/pinctrl/zte/pinctrl-zx.c val = !!val; val 203 drivers/pinctrl/zte/pinctrl-zx.c *config = pinconf_to_config_packed(param, val); val 216 drivers/pinctrl/zte/pinctrl-zx.c u32 val, arg; val 223 drivers/pinctrl/zte/pinctrl-zx.c val = readl(zpctl->aux_base + data->coffset); val 231 drivers/pinctrl/zte/pinctrl-zx.c val |= ZX_PULL_DOWN << data->cbitpos; val 234 drivers/pinctrl/zte/pinctrl-zx.c val |= ZX_PULL_UP << data->cbitpos; val 237 drivers/pinctrl/zte/pinctrl-zx.c val |= ZX_INPUT_ENABLE << data->cbitpos; val 240 drivers/pinctrl/zte/pinctrl-zx.c val &= ~(ZX_DS_MASK << data->cbitpos); val 241 drivers/pinctrl/zte/pinctrl-zx.c val |= ZX_DS_VALUE(arg) << data->cbitpos; val 245 drivers/pinctrl/zte/pinctrl-zx.c val |= ZX_SLEW << data->cbitpos; val 247 drivers/pinctrl/zte/pinctrl-zx.c val &= ~ZX_SLEW << data->cbitpos; val 254 drivers/pinctrl/zte/pinctrl-zx.c writel(val, zpctl->aux_base + data->coffset); val 180 drivers/platform/chrome/cros_ec_lightbar.c unsigned int val; val 183 drivers/platform/chrome/cros_ec_lightbar.c if (kstrtouint(buf, 0, &val)) val 192 drivers/platform/chrome/cros_ec_lightbar.c param->set_brightness.num = val; val 226 drivers/platform/chrome/cros_ec_lightbar.c unsigned int val[4]; val 241 drivers/platform/chrome/cros_ec_lightbar.c ret = sscanf(buf, "%i", &val[i++]); val 248 drivers/platform/chrome/cros_ec_lightbar.c param->set_rgb.led = val[0]; val 249 drivers/platform/chrome/cros_ec_lightbar.c param->set_rgb.red = val[1]; val 250 drivers/platform/chrome/cros_ec_lightbar.c param->set_rgb.green = val[2]; val 251 drivers/platform/chrome/cros_ec_lightbar.c param->set_rgb.blue = val[3]; val 688 drivers/platform/chrome/cros_ec_spi.c u32 val; val 691 drivers/platform/chrome/cros_ec_spi.c ret = of_property_read_u32(np, "google,cros-ec-spi-pre-delay", &val); val 693 drivers/platform/chrome/cros_ec_spi.c ec_spi->start_of_msg_delay = val; val 695 drivers/platform/chrome/cros_ec_spi.c ret = of_property_read_u32(np, "google,cros-ec-spi-msg-delay", &val); val 697 drivers/platform/chrome/cros_ec_spi.c ec_spi->end_of_msg_delay = val; val 172 drivers/platform/chrome/wilco_ec/debugfs.c u8 val; /* BIT(0)=ENTRY_TO_FACT_MODE, BIT(1)=SPI_CHROME_SEL */ val 175 drivers/platform/chrome/wilco_ec/debugfs.c static int h1_gpio_get(void *arg, u64 *val) val 199 drivers/platform/chrome/wilco_ec/debugfs.c *val = rs.val; val 102 drivers/platform/chrome/wilco_ec/properties.c u8 *val) val 115 drivers/platform/chrome/wilco_ec/properties.c *val = msg.data[0]; val 122 drivers/platform/chrome/wilco_ec/properties.c u8 val) val 127 drivers/platform/chrome/wilco_ec/properties.c msg.data[0] = val; val 22 drivers/platform/chrome/wilco_ec/sysfs.c u8 val; /* Either 0 or 1 */ val 53 drivers/platform/chrome/wilco_ec/sysfs.c u8 val; val 55 drivers/platform/chrome/wilco_ec/sysfs.c ret = kstrtou8(buf, 10, &val); val 58 drivers/platform/chrome/wilco_ec/sysfs.c if (val > 1) val 64 drivers/platform/chrome/wilco_ec/sysfs.c rq.val = val; val 411 drivers/platform/x86/alienware-wmi.c long unsigned int val; val 413 drivers/platform/x86/alienware-wmi.c val = LEGACY_BOOTING; val 415 drivers/platform/x86/alienware-wmi.c val = LEGACY_SUSPEND; val 417 drivers/platform/x86/alienware-wmi.c val = LEGACY_RUNNING; val 419 drivers/platform/x86/alienware-wmi.c val = WMAX_RUNNING; val 420 drivers/platform/x86/alienware-wmi.c lighting_control_state = val; val 108 drivers/platform/x86/apple-gmux.c u8 val) val 110 drivers/platform/x86/apple-gmux.c outb(val, gmux_data->iostart + port); val 119 drivers/platform/x86/apple-gmux.c u32 val) val 125 drivers/platform/x86/apple-gmux.c tmpval = (val >> (i * 8)) & 0xff; val 164 drivers/platform/x86/apple-gmux.c u8 val; val 170 drivers/platform/x86/apple-gmux.c val = inb(gmux_data->iostart + GMUX_PORT_VALUE); val 173 drivers/platform/x86/apple-gmux.c return val; val 177 drivers/platform/x86/apple-gmux.c u8 val) val 180 drivers/platform/x86/apple-gmux.c outb(val, gmux_data->iostart + GMUX_PORT_VALUE); val 189 drivers/platform/x86/apple-gmux.c u32 val; val 195 drivers/platform/x86/apple-gmux.c val = inl(gmux_data->iostart + GMUX_PORT_VALUE); val 198 drivers/platform/x86/apple-gmux.c return val; val 202 drivers/platform/x86/apple-gmux.c u32 val) val 210 drivers/platform/x86/apple-gmux.c tmpval = (val >> (i * 8)) & 0xff; val 228 drivers/platform/x86/apple-gmux.c static void gmux_write8(struct apple_gmux_data *gmux_data, int port, u8 val) val 231 drivers/platform/x86/apple-gmux.c gmux_index_write8(gmux_data, port, val); val 233 drivers/platform/x86/apple-gmux.c gmux_pio_write8(gmux_data, port, val); val 245 drivers/platform/x86/apple-gmux.c u32 val) val 248 drivers/platform/x86/apple-gmux.c gmux_index_write32(gmux_data, port, val); val 250 drivers/platform/x86/apple-gmux.c gmux_pio_write32(gmux_data, port, val); val 255 drivers/platform/x86/apple-gmux.c u16 val; val 261 drivers/platform/x86/apple-gmux.c val = inb(gmux_data->iostart + 0xcc) | val 264 drivers/platform/x86/apple-gmux.c if (val == 0x55aa) val 362 drivers/platform/x86/asus-laptop.c static int write_acpi_int_ret(acpi_handle handle, const char *method, int val, val 375 drivers/platform/x86/asus-laptop.c in_obj.integer.value = val; val 384 drivers/platform/x86/asus-laptop.c static int write_acpi_int(acpi_handle handle, const char *method, int val) val 386 drivers/platform/x86/asus-laptop.c return write_acpi_int_ret(handle, method, val, NULL); val 432 drivers/platform/x86/asus-laptop.c unsigned long long val; val 434 drivers/platform/x86/asus-laptop.c acpi_evaluate_integer(asus->handle, method, NULL, &val); val 442 drivers/platform/x86/asus-laptop.c delta = abs(curr - (short)val); val 443 drivers/platform/x86/asus-laptop.c if (delta < 128 && !(val & ~0xffff)) val 446 drivers/platform/x86/asus-laptop.c return clamp_val((short)val, -PEGA_ACC_CLAMP, PEGA_ACC_CLAMP); val 113 drivers/platform/x86/classmate-laptop.c static acpi_status cmpc_accel_set_sensitivity_v4(acpi_handle handle, int val) val 121 drivers/platform/x86/classmate-laptop.c param[1].integer.value = val; val 131 drivers/platform/x86/classmate-laptop.c static acpi_status cmpc_accel_set_g_select_v4(acpi_handle handle, int val) val 139 drivers/platform/x86/classmate-laptop.c param[1].integer.value = val; val 483 drivers/platform/x86/classmate-laptop.c static acpi_status cmpc_accel_set_sensitivity(acpi_handle handle, int val) val 491 drivers/platform/x86/classmate-laptop.c param[1].integer.value = val; val 698 drivers/platform/x86/classmate-laptop.c unsigned long long val = 0; val 702 drivers/platform/x86/classmate-laptop.c if (ACPI_SUCCESS(cmpc_get_tablet(dev->handle, &val))) { val 703 drivers/platform/x86/classmate-laptop.c input_report_switch(inputdev, SW_TABLET_MODE, !val); val 711 drivers/platform/x86/classmate-laptop.c unsigned long long val = 0; val 718 drivers/platform/x86/classmate-laptop.c if (ACPI_SUCCESS(cmpc_get_tablet(acpi->handle, &val))) { val 719 drivers/platform/x86/classmate-laptop.c input_report_switch(inputdev, SW_TABLET_MODE, !val); val 740 drivers/platform/x86/classmate-laptop.c unsigned long long val = 0; val 741 drivers/platform/x86/classmate-laptop.c if (ACPI_SUCCESS(cmpc_get_tablet(to_acpi_device(dev)->handle, &val))) { val 742 drivers/platform/x86/classmate-laptop.c input_report_switch(inputdev, SW_TABLET_MODE, !val); val 405 drivers/platform/x86/compal-laptop.c long val; val 408 drivers/platform/x86/compal-laptop.c err = kstrtol(buf, 10, &val); val 411 drivers/platform/x86/compal-laptop.c if (val < 0) val 414 drivers/platform/x86/compal-laptop.c data->pwm_enable = val; val 416 drivers/platform/x86/compal-laptop.c switch (val) { val 444 drivers/platform/x86/compal-laptop.c long val; val 447 drivers/platform/x86/compal-laptop.c err = kstrtol(buf, 10, &val); val 450 drivers/platform/x86/compal-laptop.c if (val < 0 || val > 255) val 453 drivers/platform/x86/compal-laptop.c data->curr_pwm = val; val 457 drivers/platform/x86/compal-laptop.c set_pwm(val); val 555 drivers/platform/x86/compal-laptop.c union power_supply_propval *val) val 561 drivers/platform/x86/compal-laptop.c val->intval = bat_status(); val 564 drivers/platform/x86/compal-laptop.c val->intval = bat_health(); val 567 drivers/platform/x86/compal-laptop.c val->intval = bat_is_present(); val 570 drivers/platform/x86/compal-laptop.c val->intval = bat_technology(); val 573 drivers/platform/x86/compal-laptop.c val->intval = ec_read_u16(BAT_VOLTAGE_DESIGN) * 1000; val 576 drivers/platform/x86/compal-laptop.c val->intval = ec_read_u16(BAT_VOLTAGE_NOW) * 1000; val 579 drivers/platform/x86/compal-laptop.c val->intval = ec_read_s16(BAT_CURRENT_NOW) * 1000; val 582 drivers/platform/x86/compal-laptop.c val->intval = ec_read_s16(BAT_CURRENT_AVG) * 1000; val 585 drivers/platform/x86/compal-laptop.c val->intval = ec_read_u8(BAT_POWER) * 1000000; val 588 drivers/platform/x86/compal-laptop.c val->intval = ec_read_u16(BAT_CHARGE_DESIGN) * 1000; val 591 drivers/platform/x86/compal-laptop.c val->intval = ec_read_u16(BAT_CHARGE_NOW) * 1000; val 594 drivers/platform/x86/compal-laptop.c val->intval = ec_read_u8(BAT_CHARGE_LIMIT); val 597 drivers/platform/x86/compal-laptop.c val->intval = BAT_CHARGE_LIMIT_MAX; val 600 drivers/platform/x86/compal-laptop.c val->intval = ec_read_u8(BAT_CAPACITY); val 603 drivers/platform/x86/compal-laptop.c val->intval = bat_capacity_level(); val 611 drivers/platform/x86/compal-laptop.c val->intval = ((222 - (int)ec_read_u8(BAT_TEMP)) * 1000) >> 8; val 614 drivers/platform/x86/compal-laptop.c val->intval = ec_read_s8(BAT_TEMP_AVG) * 10; val 618 drivers/platform/x86/compal-laptop.c val->strval = data->bat_model_name; val 621 drivers/platform/x86/compal-laptop.c val->strval = data->bat_manufacturer_name; val 624 drivers/platform/x86/compal-laptop.c val->strval = data->bat_serial_number; val 634 drivers/platform/x86/compal-laptop.c const union power_supply_propval *val) val 640 drivers/platform/x86/compal-laptop.c level = val->intval; val 303 drivers/platform/x86/dcdbas.c unsigned long val = simple_strtoul(buf, NULL, 10); val 314 drivers/platform/x86/dcdbas.c switch (val) { val 1385 drivers/platform/x86/dell-laptop.c int val; val 1396 drivers/platform/x86/dell-laptop.c val = buffer.output[1]; val 1401 drivers/platform/x86/dell-laptop.c return (val == token->value); val 183 drivers/platform/x86/eeepc-laptop.c static int write_acpi_int(acpi_handle handle, const char *method, int val) val 187 drivers/platform/x86/eeepc-laptop.c status = acpi_execute_simple_method(handle, (char *)method, val); val 192 drivers/platform/x86/eeepc-laptop.c static int read_acpi_int(acpi_handle handle, const char *method, int *val) val 199 drivers/platform/x86/eeepc-laptop.c *val = -1; val 202 drivers/platform/x86/eeepc-laptop.c *val = result; val 260 drivers/platform/x86/eeepc-laptop.c static int parse_arg(const char *buf, int *val) val 262 drivers/platform/x86/eeepc-laptop.c if (sscanf(buf, "%i", val) != 1) val 710 drivers/platform/x86/eeepc-laptop.c int val; val 713 drivers/platform/x86/eeepc-laptop.c val = get_acpi(eeepc, CM_ASL_WLAN); val 715 drivers/platform/x86/eeepc-laptop.c if (val == 1 || val == 0) val 716 drivers/platform/x86/eeepc-laptop.c *value = val; val 82 drivers/platform/x86/hdaps.c static inline int __check_latch(u16 port, u8 val) val 84 drivers/platform/x86/hdaps.c if (__get_latch(port) == val) val 93 drivers/platform/x86/hdaps.c static int __wait_latch(u16 port, u8 val) val 98 drivers/platform/x86/hdaps.c if (!__check_latch(port, val)) val 146 drivers/platform/x86/hdaps.c static int hdaps_readb_one(unsigned int port, u8 *val) val 157 drivers/platform/x86/hdaps.c *val = inb(port); val 269 drivers/platform/x86/hp-wmi.c int val = 0, ret; val 271 drivers/platform/x86/hp-wmi.c ret = hp_wmi_perform_query(query, HPWMI_READ, &val, val 272 drivers/platform/x86/hp-wmi.c sizeof(val), sizeof(val)); val 277 drivers/platform/x86/hp-wmi.c return val; val 631 drivers/platform/x86/hp-wmi.c int err, val; val 644 drivers/platform/x86/hp-wmi.c val = hp_wmi_hw_state(HPWMI_DOCK_MASK); val 645 drivers/platform/x86/hp-wmi.c if (!(val < 0)) { val 647 drivers/platform/x86/hp-wmi.c input_report_switch(hp_wmi_input_dev, SW_DOCK, val); val 651 drivers/platform/x86/hp-wmi.c val = hp_wmi_hw_state(HPWMI_TABLET_MASK); val 652 drivers/platform/x86/hp-wmi.c if (!(val < 0)) { val 654 drivers/platform/x86/hp-wmi.c input_report_switch(hp_wmi_input_dev, SW_TABLET_MODE, val); val 131 drivers/platform/x86/hp_accel.c static int lis3lv02d_acpi_write(struct lis3lv02d *lis3, int reg, u8 val) val 141 drivers/platform/x86/hp_accel.c in_obj[1].integer.value = val; val 107 drivers/platform/x86/ideapad-laptop.c static int read_method_int(acpi_handle handle, const char *method, int *val) val 114 drivers/platform/x86/ideapad-laptop.c *val = -1; val 117 drivers/platform/x86/ideapad-laptop.c *val = result; val 124 drivers/platform/x86/ideapad-laptop.c int result, val; val 126 drivers/platform/x86/ideapad-laptop.c result = read_method_int(handle, "GBMD", &val); val 127 drivers/platform/x86/ideapad-laptop.c *ret = val; val 183 drivers/platform/x86/ideapad-laptop.c int val; val 192 drivers/platform/x86/ideapad-laptop.c if (method_vpcr(handle, 1, &val)) val 194 drivers/platform/x86/ideapad-laptop.c if (val == 0) { val 195 drivers/platform/x86/ideapad-laptop.c if (method_vpcr(handle, 0, &val)) val 197 drivers/platform/x86/ideapad-laptop.c *data = val; val 207 drivers/platform/x86/ideapad-laptop.c int val; val 218 drivers/platform/x86/ideapad-laptop.c if (method_vpcr(handle, 1, &val)) val 220 drivers/platform/x86/ideapad-laptop.c if (val == 0) val 78 drivers/platform/x86/intel-vbtn.c unsigned int val = !(event & 1); /* Even=press, Odd=release */ val 95 drivers/platform/x86/intel-vbtn.c val, val 107 drivers/platform/x86/intel-vbtn.c autorelease = val && (!ke_rel || ke_rel->type == KE_IGNORE); val 109 drivers/platform/x86/intel-vbtn.c if (sparse_keymap_report_event(priv->input_dev, event, val, autorelease)) val 39 drivers/platform/x86/intel_atomisp2_pm.c u32 val = enable ? ISPSSPM0_IUNIT_POWER_ON : val 44 drivers/platform/x86/intel_atomisp2_pm.c val, ISPSSPM0_ISPSSC_MASK); val 59 drivers/platform/x86/intel_atomisp2_pm.c if (tmp == val) val 90 drivers/platform/x86/intel_atomisp2_pm.c u32 val; val 99 drivers/platform/x86/intel_atomisp2_pm.c pci_read_config_dword(pdev, PCI_CSI_CONTROL, &val); val 100 drivers/platform/x86/intel_atomisp2_pm.c val |= PCI_CSI_CONTROL_PORTS_OFF_MASK; val 101 drivers/platform/x86/intel_atomisp2_pm.c pci_write_config_dword(pdev, PCI_CSI_CONTROL, val); val 95 drivers/platform/x86/intel_bxtwc_tmu.c unsigned int val; val 98 drivers/platform/x86/intel_bxtwc_tmu.c regmap_read(wctmu->regmap, BXTWC_MIRQLVL1, &val); val 100 drivers/platform/x86/intel_bxtwc_tmu.c val | BXTWC_MIRQLVL1_MTMU); val 101 drivers/platform/x86/intel_bxtwc_tmu.c regmap_read(wctmu->regmap, BXTWC_MTMUIRQ_REG, &val); val 103 drivers/platform/x86/intel_bxtwc_tmu.c val | BXTWC_TMU_ALRM_MASK); val 233 drivers/platform/x86/intel_ips.c #define thm_writeb(off, val) writeb((val), ips->regmap + (off)) val 234 drivers/platform/x86/intel_ips.c #define thm_writew(off, val) writew((val), ips->regmap + (off)) val 235 drivers/platform/x86/intel_ips.c #define thm_writel(off, val) writel((val), ips->regmap + (off)) val 834 drivers/platform/x86/intel_ips.c u64 val; val 836 drivers/platform/x86/intel_ips.c val = thm_readq(THM_MGTV); val 837 drivers/platform/x86/intel_ips.c val = (val & TV_MASK) >> TV_SHIFT; val 843 drivers/platform/x86/intel_ips.c ret = ((val * slope + 0x40) >> 7) + offset; val 850 drivers/platform/x86/intel_ips.c u16 val; val 852 drivers/platform/x86/intel_ips.c val = thm_readw(THM_PTV) & PTV_MASK; val 854 drivers/platform/x86/intel_ips.c return val; val 860 drivers/platform/x86/intel_ips.c u16 val; val 862 drivers/platform/x86/intel_ips.c val = thm_readw(reg); val 863 drivers/platform/x86/intel_ips.c if (!(val & CTV_TEMP_ERROR)) val 864 drivers/platform/x86/intel_ips.c val = (val) >> 6; /* discard fractional component */ val 866 drivers/platform/x86/intel_ips.c val = 0; val 868 drivers/platform/x86/intel_ips.c return val; val 873 drivers/platform/x86/intel_ips.c u32 val; val 880 drivers/platform/x86/intel_ips.c val = thm_readl(THM_CEC); val 883 drivers/platform/x86/intel_ips.c ret = (((val - *last) * 1000) / period); val 885 drivers/platform/x86/intel_ips.c *last = val; val 891 drivers/platform/x86/intel_ips.c static u16 update_average_temp(u16 avg, u16 val) val 896 drivers/platform/x86/intel_ips.c ret = (val * 100 / temp_decay_factor) + val 902 drivers/platform/x86/intel_ips.c static u16 update_average_power(u32 avg, u32 val) val 906 drivers/platform/x86/intel_ips.c ret = (val / power_decay_factor) + val 982 drivers/platform/x86/intel_ips.c u16 val; val 986 drivers/platform/x86/intel_ips.c val = read_ctv(ips, 0); val 987 drivers/platform/x86/intel_ips.c ctv1_samples[i] = val; val 989 drivers/platform/x86/intel_ips.c val = read_ctv(ips, 1); val 990 drivers/platform/x86/intel_ips.c ctv2_samples[i] = val; val 992 drivers/platform/x86/intel_ips.c val = read_mgtv(ips); val 993 drivers/platform/x86/intel_ips.c mch_samples[i] = val; val 1037 drivers/platform/x86/intel_ips.c u16 val; val 1040 drivers/platform/x86/intel_ips.c val = read_ptv(ips); val 1041 drivers/platform/x86/intel_ips.c ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val); val 1044 drivers/platform/x86/intel_ips.c val = read_ctv(ips, 0); val 1046 drivers/platform/x86/intel_ips.c update_average_temp(ips->ctv1_avg_temp, val); val 1055 drivers/platform/x86/intel_ips.c val = read_ctv(ips, 1); val 1057 drivers/platform/x86/intel_ips.c update_average_temp(ips->ctv2_avg_temp, val); val 1061 drivers/platform/x86/intel_ips.c val = read_mgtv(ips); val 1062 drivers/platform/x86/intel_ips.c ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val); val 1111 drivers/platform/x86/intel_ips.c u16 val = thm_readw(reg); \ val 1112 drivers/platform/x86/intel_ips.c dev_dbg(ips->dev, #reg ": 0x%04x\n", val); \ val 1116 drivers/platform/x86/intel_ips.c u32 val = thm_readl(reg); \ val 1117 drivers/platform/x86/intel_ips.c dev_dbg(ips->dev, #reg ": 0x%08x\n", val); \ val 1121 drivers/platform/x86/intel_ips.c u64 val = thm_readq(reg); \ val 1122 drivers/platform/x86/intel_ips.c dev_dbg(ips->dev, #reg ": 0x%016x\n", val); \ val 213 drivers/platform/x86/intel_mid_thermal.c static int configure_adc(int val) val 222 drivers/platform/x86/intel_mid_thermal.c if (val) { val 379 drivers/platform/x86/intel_pmc_core.c reg_offset, u32 val) val 381 drivers/platform/x86/intel_pmc_core.c writel(val, pmcdev->regbase + reg_offset); val 389 drivers/platform/x86/intel_pmc_core.c static int pmc_core_dev_state_get(void *data, u64 *val) val 396 drivers/platform/x86/intel_pmc_core.c *val = pmc_core_adjust_slp_s0_step(value); val 532 drivers/platform/x86/intel_pmc_core.c u32 mphy_common_reg, val; val 550 drivers/platform/x86/intel_pmc_core.c val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET); val 555 drivers/platform/x86/intel_pmc_core.c map[index].bit_mask & val ? "Active" : "Idle"); val 569 drivers/platform/x86/intel_pmc_core.c u32 val, buf_size, fd; val 575 drivers/platform/x86/intel_pmc_core.c if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) { val 580 drivers/platform/x86/intel_pmc_core.c if (val > map->ltr_ignore_max) { val 586 drivers/platform/x86/intel_pmc_core.c fd |= (1U << val); val 663 drivers/platform/x86/intel_pmc_core.c static u32 convert_ltr_scale(u32 val) val 689 drivers/platform/x86/intel_pmc_core.c if (val > 5) { val 694 drivers/platform/x86/intel_pmc_core.c return 1U << (5 * val); val 702 drivers/platform/x86/intel_pmc_core.c u32 ltr_raw_data, scale, val; val 715 drivers/platform/x86/intel_pmc_core.c val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr); val 716 drivers/platform/x86/intel_pmc_core.c decoded_non_snoop_ltr = val * convert_ltr_scale(scale); val 721 drivers/platform/x86/intel_pmc_core.c val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr); val 722 drivers/platform/x86/intel_pmc_core.c decoded_snoop_ltr = val * convert_ltr_scale(scale); val 312 drivers/platform/x86/intel_pmc_ipc.c int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) val 326 drivers/platform/x86/intel_pmc_ipc.c new_val |= val & mask; val 333 drivers/platform/x86/intel_pmc_ipc.c if ((new_val & mask) != (val & mask)) { val 587 drivers/platform/x86/intel_pmc_ipc.c unsigned long val; val 591 drivers/platform/x86/intel_pmc_ipc.c if (kstrtoul(buf, 0, &val)) val 594 drivers/platform/x86/intel_pmc_ipc.c if (val) val 148 drivers/platform/x86/intel_punit_ipc.c u32 val; val 156 drivers/platform/x86/intel_punit_ipc.c val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK; val 157 drivers/platform/x86/intel_punit_ipc.c val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT; val 158 drivers/platform/x86/intel_punit_ipc.c ipc_write_cmd(ipcdev, type, val); val 183 drivers/platform/x86/intel_punit_ipc.c u32 val; val 197 drivers/platform/x86/intel_punit_ipc.c val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK; val 198 drivers/platform/x86/intel_punit_ipc.c val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT; val 199 drivers/platform/x86/intel_punit_ipc.c ipc_write_cmd(ipcdev, type, val); val 649 drivers/platform/x86/intel_telemetry_debugfs.c static int telem_s0ix_res_get(void *data, u64 *val) val 660 drivers/platform/x86/intel_telemetry_debugfs.c *val = s0ix_total_res; val 539 drivers/platform/x86/lg-laptop.c u32 val; val 542 drivers/platform/x86/lg-laptop.c val = 0x22; val 544 drivers/platform/x86/lg-laptop.c val = 0; val 546 drivers/platform/x86/lg-laptop.c val = 0x24; val 547 drivers/platform/x86/lg-laptop.c r = lg_wmab(WM_KEY_LIGHT, WM_SET, val); val 554 drivers/platform/x86/lg-laptop.c int val; val 568 drivers/platform/x86/lg-laptop.c val = LED_FULL; val 571 drivers/platform/x86/lg-laptop.c val = LED_HALF; val 574 drivers/platform/x86/lg-laptop.c val = LED_OFF; val 579 drivers/platform/x86/lg-laptop.c return val; val 1761 drivers/platform/x86/mlx-platform.c mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) val 1765 drivers/platform/x86/mlx-platform.c *val = ioread8(ctx->base + reg); val 1770 drivers/platform/x86/mlx-platform.c mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) val 1774 drivers/platform/x86/mlx-platform.c iowrite8(val, ctx->base + reg); val 219 drivers/platform/x86/panasonic-laptop.c static int acpi_pcc_write_sset(struct pcc_acpi *pcc, int func, int val) val 225 drivers/platform/x86/panasonic-laptop.c .integer.value = val, }, val 403 drivers/platform/x86/panasonic-laptop.c int val; val 405 drivers/platform/x86/panasonic-laptop.c if (count && sscanf(buf, "%i", &val) == 1 && val 406 drivers/platform/x86/panasonic-laptop.c (val == 0 || val == 1)) { val 407 drivers/platform/x86/panasonic-laptop.c acpi_pcc_write_sset(pcc, SINF_STICKY_KEY, val); val 408 drivers/platform/x86/panasonic-laptop.c pcc->sticky_mode = val; val 208 drivers/platform/x86/pmc_atom.c static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val) val 210 drivers/platform/x86/pmc_atom.c writel(val, pmc->regmap + reg_offset); val 1478 drivers/platform/x86/samsung-laptop.c unsigned long val, void *ptr) val 1483 drivers/platform/x86/samsung-laptop.c if (val == PM_POST_HIBERNATION && val 1487 drivers/platform/x86/samsung-laptop.c if (val == PM_POST_HIBERNATION && samsung->quirks->lid_handling) val 8167 drivers/platform/x86/thinkpad_acpi.c u8 val; val 8169 drivers/platform/x86/thinkpad_acpi.c if (ec_read(fan_select_offset, &val) < 0) val 8171 drivers/platform/x86/thinkpad_acpi.c val &= 0xFEU; val 8172 drivers/platform/x86/thinkpad_acpi.c if (ec_write(fan_select_offset, val) < 0) val 8181 drivers/platform/x86/thinkpad_acpi.c u8 val; val 8186 drivers/platform/x86/thinkpad_acpi.c if (ec_read(fan_select_offset, &val) < 0) val 8188 drivers/platform/x86/thinkpad_acpi.c val |= 0x01U; val 8189 drivers/platform/x86/thinkpad_acpi.c if (ec_write(fan_select_offset, val) < 0) val 10302 drivers/platform/x86/thinkpad_acpi.c static int __init set_ibm_param(const char *val, const struct kernel_param *kp) val 10307 drivers/platform/x86/thinkpad_acpi.c if (!kp || !kp->name || !val) val 10318 drivers/platform/x86/thinkpad_acpi.c if (strlen(val) > sizeof(ibms_init[i].param) - 2) val 10320 drivers/platform/x86/thinkpad_acpi.c strcpy(ibms_init[i].param, val); val 298 drivers/platform/x86/toshiba_acpi.c static int write_acpi_int(const char *methodName, int val) val 302 drivers/platform/x86/toshiba_acpi.c status = acpi_execute_simple_method(NULL, (char *)methodName, val); val 2461 drivers/platform/x86/toshiba_acpi.c int *val, int *val2, long mask) val 2471 drivers/platform/x86/toshiba_acpi.c *val = ret; val 111 drivers/pnp/isapnp/core.c unsigned char val = inb(isapnp_rdp); val 112 drivers/pnp/isapnp/core.c return val; val 123 drivers/pnp/isapnp/core.c unsigned short val; val 125 drivers/pnp/isapnp/core.c val = isapnp_read_byte(idx); val 126 drivers/pnp/isapnp/core.c val = (val << 8) + isapnp_read_byte(idx + 1); val 127 drivers/pnp/isapnp/core.c return val; val 130 drivers/pnp/isapnp/core.c void isapnp_write_byte(unsigned char idx, unsigned char val) val 133 drivers/pnp/isapnp/core.c write_data(val); val 136 drivers/pnp/isapnp/core.c static void isapnp_write_word(unsigned char idx, unsigned short val) val 138 drivers/pnp/isapnp/core.c isapnp_write_byte(idx, val >> 8); val 139 drivers/pnp/isapnp/core.c isapnp_write_byte(idx + 1, val); val 42 drivers/pnp/isapnp/proc.c unsigned char val; val 43 drivers/pnp/isapnp/proc.c val = isapnp_read_byte(pos); val 44 drivers/pnp/isapnp/proc.c __put_user(val, buf); val 83 drivers/power/avs/rockchip-io-domain.c u32 val; val 87 drivers/power/avs/rockchip-io-domain.c val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1; val 88 drivers/power/avs/rockchip-io-domain.c val <<= supply->idx; val 91 drivers/power/avs/rockchip-io-domain.c val |= (BIT(supply->idx) << 16); val 93 drivers/power/avs/rockchip-io-domain.c ret = regmap_write(iod->grf, iod->soc_data->grf_offset, val); val 153 drivers/power/avs/rockchip-io-domain.c u32 val; val 163 drivers/power/avs/rockchip-io-domain.c val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC << 16); val 164 drivers/power/avs/rockchip-io-domain.c ret = regmap_write(iod->grf, PX30_IO_VSEL, val); val 172 drivers/power/avs/rockchip-io-domain.c u32 val; val 182 drivers/power/avs/rockchip-io-domain.c val = RK3288_SOC_CON2_FLASH0 | (RK3288_SOC_CON2_FLASH0 << 16); val 183 drivers/power/avs/rockchip-io-domain.c ret = regmap_write(iod->grf, RK3288_SOC_CON2, val); val 191 drivers/power/avs/rockchip-io-domain.c u32 val; val 201 drivers/power/avs/rockchip-io-domain.c val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16); val 202 drivers/power/avs/rockchip-io-domain.c ret = regmap_write(iod->grf, RK3328_SOC_CON4, val); val 210 drivers/power/avs/rockchip-io-domain.c u32 val; val 220 drivers/power/avs/rockchip-io-domain.c val = RK3368_SOC_CON15_FLASH0 | (RK3368_SOC_CON15_FLASH0 << 16); val 221 drivers/power/avs/rockchip-io-domain.c ret = regmap_write(iod->grf, RK3368_SOC_CON15, val); val 229 drivers/power/avs/rockchip-io-domain.c u32 val; val 239 drivers/power/avs/rockchip-io-domain.c val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16); val 240 drivers/power/avs/rockchip-io-domain.c ret = regmap_write(iod->grf, RK3399_PMUGRF_CON0, val); val 780 drivers/power/avs/smartreflex.c static int omap_sr_autocomp_show(void *data, u64 *val) val 789 drivers/power/avs/smartreflex.c *val = sr_info->autocomp_active; val 794 drivers/power/avs/smartreflex.c static int omap_sr_autocomp_store(void *data, u64 val) val 804 drivers/power/avs/smartreflex.c if (val > 1) { val 805 drivers/power/avs/smartreflex.c pr_warn("%s: Invalid argument %lld\n", __func__, val); val 810 drivers/power/avs/smartreflex.c if (sr_info->autocomp_active != val) { val 811 drivers/power/avs/smartreflex.c if (!val) val 39 drivers/power/reset/gemini-poweroff.c u32 val; val 42 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); val 43 drivers/power/reset/gemini-poweroff.c val |= GEMINI_CTRL_IRQ_CLR; val 44 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); val 46 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_STATREG); val 47 drivers/power/reset/gemini-poweroff.c val &= 0x70U; val 48 drivers/power/reset/gemini-poweroff.c switch (val) { val 79 drivers/power/reset/gemini-poweroff.c u32 val; val 82 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); val 83 drivers/power/reset/gemini-poweroff.c val |= GEMINI_CTRL_ENABLE | GEMINI_CTRL_IRQ_CLR; val 84 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); val 86 drivers/power/reset/gemini-poweroff.c val &= ~GEMINI_CTRL_ENABLE; val 87 drivers/power/reset/gemini-poweroff.c val |= GEMINI_CTRL_SHUTDOWN; val 88 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); val 96 drivers/power/reset/gemini-poweroff.c u32 val; val 115 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_IDREG); val 116 drivers/power/reset/gemini-poweroff.c val &= 0xFFFFFF00U; val 117 drivers/power/reset/gemini-poweroff.c if (val != GEMINI_PWC_ID) { val 119 drivers/power/reset/gemini-poweroff.c val); val 129 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); val 130 drivers/power/reset/gemini-poweroff.c val |= GEMINI_CTRL_ENABLE; val 131 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); val 134 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); val 135 drivers/power/reset/gemini-poweroff.c val |= GEMINI_CTRL_IRQ_CLR; val 136 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); val 139 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_STATREG); val 140 drivers/power/reset/gemini-poweroff.c while (val & 0x70U) val 141 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_STATREG); val 144 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); val 145 drivers/power/reset/gemini-poweroff.c val |= GEMINI_CTRL_IRQ_CLR; val 146 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); val 79 drivers/power/reset/keystone-reset.c u32 val; val 111 drivers/power/reset/keystone-reset.c val = of_property_read_bool(np, "ti,soft-reset"); val 112 drivers/power/reset/keystone-reset.c val = val ? RSCFG_RSTYPE_SOFT : RSCFG_RSTYPE_HARD; val 118 drivers/power/reset/keystone-reset.c ret = regmap_write(pllctrl_regs, rspll_offset + RSCFG_RG, val); val 129 drivers/power/reset/keystone-reset.c ret = of_property_read_u32_index(np, "ti,wdt-list", i, &val); val 138 drivers/power/reset/keystone-reset.c if (val >= WDT_MUX_NUMBER) { val 144 drivers/power/reset/keystone-reset.c rg = rsmux_offset + val * 4; val 805 drivers/power/supply/88pm860x_battery.c union power_supply_propval *val) val 813 drivers/power/supply/88pm860x_battery.c val->intval = info->present; val 826 drivers/power/supply/88pm860x_battery.c val->intval = data; val 829 drivers/power/supply/88pm860x_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 836 drivers/power/supply/88pm860x_battery.c val->intval = data * 1000; val 843 drivers/power/supply/88pm860x_battery.c val->intval = data * 1000; val 849 drivers/power/supply/88pm860x_battery.c val->intval = data; val 861 drivers/power/supply/88pm860x_battery.c val->intval = data; val 871 drivers/power/supply/88pm860x_battery.c const union power_supply_propval *val) val 473 drivers/power/supply/88pm860x_charger.c union power_supply_propval val; val 493 drivers/power/supply/88pm860x_charger.c &val); val 496 drivers/power/supply/88pm860x_charger.c vbatt = val.intval / 1000; val 509 drivers/power/supply/88pm860x_charger.c &val); val 593 drivers/power/supply/88pm860x_charger.c union power_supply_propval *val) val 601 drivers/power/supply/88pm860x_charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 603 drivers/power/supply/88pm860x_charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 606 drivers/power/supply/88pm860x_charger.c val->intval = info->online; val 821 drivers/power/supply/ab8500_btemp.c union power_supply_propval *val) val 829 drivers/power/supply/ab8500_btemp.c val->intval = 0; val 831 drivers/power/supply/ab8500_btemp.c val->intval = 1; val 834 drivers/power/supply/ab8500_btemp.c val->intval = di->bm->bat_type[di->bm->batt_id].name; val 837 drivers/power/supply/ab8500_btemp.c val->intval = ab8500_btemp_get_temp(di); val 1002 drivers/power/supply/ab8500_btemp.c u8 val; val 1052 drivers/power/supply/ab8500_btemp.c AB8500_BTEMP_HIGH_TH, &val); val 1057 drivers/power/supply/ab8500_btemp.c switch (val) { val 345 drivers/power/supply/ab8500_charger.c u8 val; val 364 drivers/power/supply/ab8500_charger.c ret = abx500_get_register_interruptible(di->dev, bank, reg, &val); val 380 drivers/power/supply/ab8500_charger.c val |= (1 << bit); val 382 drivers/power/supply/ab8500_charger.c val &= ~(1 << bit); val 385 drivers/power/supply/ab8500_charger.c ret = abx500_set_register_interruptible(di->dev, bank, reg, val); val 483 drivers/power/supply/ab8500_charger.c u8 val; val 489 drivers/power/supply/ab8500_charger.c AB8500_CH_STATUS1_REG, &val); val 495 drivers/power/supply/ab8500_charger.c if (val & MAIN_CH_CV_ON) val 579 drivers/power/supply/ab8500_charger.c u8 val; val 584 drivers/power/supply/ab8500_charger.c AB8500_CH_USBCH_STAT1_REG, &val); val 590 drivers/power/supply/ab8500_charger.c if (val & USB_CH_CV_ON) val 622 drivers/power/supply/ab8500_charger.c u8 val; val 626 drivers/power/supply/ab8500_charger.c AB8500_CH_STATUS1_REG, &val); val 632 drivers/power/supply/ab8500_charger.c if (val & MAIN_CH_DET) val 647 drivers/power/supply/ab8500_charger.c AB8500_CH_USBCH_STAT1_REG, &val); val 654 drivers/power/supply/ab8500_charger.c val); val 655 drivers/power/supply/ab8500_charger.c if ((val & VBUS_DET_DBNC1) && (val & VBUS_DET_DBNC100)) val 805 drivers/power/supply/ab8500_charger.c u8 val; val 808 drivers/power/supply/ab8500_charger.c AB8500_INTERRUPT, AB8500_IT_SOURCE21_REG, &val); val 815 drivers/power/supply/ab8500_charger.c AB8500_USB_LINE_STAT_REG, &val); val 818 drivers/power/supply/ab8500_charger.c AB8500_USB, AB8500_USB_LINK1_STAT_REG, &val); val 826 drivers/power/supply/ab8500_charger.c val = (val & AB8500_USB_LINK_STATUS) >> USB_LINK_STATUS_SHIFT; val 828 drivers/power/supply/ab8500_charger.c val = (val & AB8505_USB_LINK_STATUS) >> USB_LINK_STATUS_SHIFT; val 830 drivers/power/supply/ab8500_charger.c (enum ab8500_charger_link_status) val); val 845 drivers/power/supply/ab8500_charger.c u8 val; val 856 drivers/power/supply/ab8500_charger.c &val); val 858 drivers/power/supply/ab8500_charger.c __func__, val); val 866 drivers/power/supply/ab8500_charger.c AB8500_USB, AB8500_USB_LINE_STAT_REG, &val); val 869 drivers/power/supply/ab8500_charger.c AB8500_USB, AB8500_USB_LINK1_STAT_REG, &val); val 875 drivers/power/supply/ab8500_charger.c val); val 884 drivers/power/supply/ab8500_charger.c val = (val & AB8500_USB_LINK_STATUS) >> val 887 drivers/power/supply/ab8500_charger.c val = (val & AB8505_USB_LINK_STATUS) >> val 889 drivers/power/supply/ab8500_charger.c if (val) val 893 drivers/power/supply/ab8500_charger.c (enum ab8500_charger_link_status) val); val 2240 drivers/power/supply/ab8500_charger.c u8 val; val 2263 drivers/power/supply/ab8500_charger.c AB8500_USB_LINE_STAT_REG, &val); val 2266 drivers/power/supply/ab8500_charger.c AB8500_USB_LINK1_STAT_REG, &val); val 2269 drivers/power/supply/ab8500_charger.c dev_dbg(di->dev, "UsbLineStatus register = 0x%02x\n", val); val 2279 drivers/power/supply/ab8500_charger.c if (((val & link_status) >> USB_LINK_STATUS_SHIFT) == val 2308 drivers/power/supply/ab8500_charger.c &val); val 2312 drivers/power/supply/ab8500_charger.c &val); val 2315 drivers/power/supply/ab8500_charger.c (val & link_status) >> USB_LINK_STATUS_SHIFT); val 2875 drivers/power/supply/ab8500_charger.c union power_supply_propval *val) val 2885 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 2887 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 2889 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 2891 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 2894 drivers/power/supply/ab8500_charger.c val->intval = di->ac.charger_online; val 2897 drivers/power/supply/ab8500_charger.c val->intval = di->ac.charger_connected; val 2904 drivers/power/supply/ab8500_charger.c val->intval = di->ac.charger_voltage * 1000; val 2912 drivers/power/supply/ab8500_charger.c val->intval = di->ac.cv_active; val 2918 drivers/power/supply/ab8500_charger.c val->intval = di->ac.charger_current * 1000; val 2942 drivers/power/supply/ab8500_charger.c union power_supply_propval *val) val 2952 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 2954 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 2956 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 2958 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 2960 drivers/power/supply/ab8500_charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 2963 drivers/power/supply/ab8500_charger.c val->intval = di->usb.charger_online; val 2966 drivers/power/supply/ab8500_charger.c val->intval = di->usb.charger_connected; val 2972 drivers/power/supply/ab8500_charger.c val->intval = di->usb.charger_voltage * 1000; val 2980 drivers/power/supply/ab8500_charger.c val->intval = di->usb.cv_active; val 2986 drivers/power/supply/ab8500_charger.c val->intval = di->usb.charger_current * 1000; val 2994 drivers/power/supply/ab8500_charger.c val->intval = 1; val 2996 drivers/power/supply/ab8500_charger.c val->intval = 0; val 613 drivers/power/supply/ab8500_fg.c int val; val 659 drivers/power/supply/ab8500_fg.c val = (low | (high << 8) | 0xFFFFE000); val 661 drivers/power/supply/ab8500_fg.c val = (low | (high << 8)); val 672 drivers/power/supply/ab8500_fg.c val = (val * QLSB_NANO_AMP_HOURS_X10 * 36 * 4) / val 691 drivers/power/supply/ab8500_fg.c (*res) = val; val 756 drivers/power/supply/ab8500_fg.c int val; val 786 drivers/power/supply/ab8500_fg.c val = (low | (med << 8) | (high << 16) | 0xFFE00000); val 788 drivers/power/supply/ab8500_fg.c val = (low | (med << 8) | (high << 16)); val 796 drivers/power/supply/ab8500_fg.c di->accu_charge = (val * QLSB_NANO_AMP_HOURS_X10) / val 805 drivers/power/supply/ab8500_fg.c di->avg_curr = (val * QLSB_NANO_AMP_HOURS_X10 * 36) / val 815 drivers/power/supply/ab8500_fg.c di->bm->fg_res, di->fg_samples, val, di->accu_charge); val 2087 drivers/power/supply/ab8500_fg.c union power_supply_propval *val) val 2101 drivers/power/supply/ab8500_fg.c val->intval = BATT_OVV_VALUE * 1000; val 2103 drivers/power/supply/ab8500_fg.c val->intval = di->vbat * 1000; val 2106 drivers/power/supply/ab8500_fg.c val->intval = di->inst_curr * 1000; val 2109 drivers/power/supply/ab8500_fg.c val->intval = di->avg_curr * 1000; val 2112 drivers/power/supply/ab8500_fg.c val->intval = ab8500_fg_convert_mah_to_uwh(di, val 2116 drivers/power/supply/ab8500_fg.c val->intval = ab8500_fg_convert_mah_to_uwh(di, val 2122 drivers/power/supply/ab8500_fg.c val->intval = ab8500_fg_convert_mah_to_uwh(di, val 2125 drivers/power/supply/ab8500_fg.c val->intval = ab8500_fg_convert_mah_to_uwh(di, val 2129 drivers/power/supply/ab8500_fg.c val->intval = di->bat_cap.max_mah_design; val 2132 drivers/power/supply/ab8500_fg.c val->intval = di->bat_cap.max_mah; val 2137 drivers/power/supply/ab8500_fg.c val->intval = di->bat_cap.max_mah; val 2139 drivers/power/supply/ab8500_fg.c val->intval = di->bat_cap.prev_mah; val 2144 drivers/power/supply/ab8500_fg.c val->intval = 100; val 2146 drivers/power/supply/ab8500_fg.c val->intval = di->bat_cap.prev_percent; val 2151 drivers/power/supply/ab8500_fg.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN; val 2153 drivers/power/supply/ab8500_fg.c val->intval = di->bat_cap.prev_level; val 1713 drivers/power/supply/abx500_chargalg.c union power_supply_propval *val) val 1719 drivers/power/supply/abx500_chargalg.c val->intval = di->charge_status; val 1723 drivers/power/supply/abx500_chargalg.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 1726 drivers/power/supply/abx500_chargalg.c val->intval = POWER_SUPPLY_HEALTH_COLD; val 1728 drivers/power/supply/abx500_chargalg.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 1731 drivers/power/supply/abx500_chargalg.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 1733 drivers/power/supply/abx500_chargalg.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 86 drivers/power/supply/act8945a_charger.c static int act8945a_get_charger_state(struct regmap *regmap, int *val) val 105 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_STATUS_CHARGING; val 109 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_STATUS_FULL; val 111 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_STATUS_CHARGING; val 116 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_STATUS_DISCHARGING; val 118 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_STATUS_NOT_CHARGING; val 125 drivers/power/supply/act8945a_charger.c static int act8945a_get_charge_type(struct regmap *regmap, int *val) val 143 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 146 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_FAST; val 149 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_NONE; val 154 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_NONE; val 156 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN; val 163 drivers/power/supply/act8945a_charger.c static int act8945a_get_battery_health(struct regmap *regmap, int *val) val 186 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_HEALTH_UNKNOWN; val 189 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_HEALTH_OVERHEAT; val 191 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; val 193 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 195 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_HEALTH_GOOD; val 202 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_HEALTH_GOOD; val 210 drivers/power/supply/act8945a_charger.c struct regmap *regmap, int *val) val 233 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CAPACITY_LEVEL_LOW; val 237 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CAPACITY_LEVEL_HIGH; val 239 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CAPACITY_LEVEL_LOW; val 243 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CAPACITY_LEVEL_FULL; val 245 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; val 250 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN; val 252 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; val 255 drivers/power/supply/act8945a_charger.c *val = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; val 277 drivers/power/supply/act8945a_charger.c struct regmap *regmap, int *val) val 301 drivers/power/supply/act8945a_charger.c *val = MAX_CURRENT_AC_HIGH_PRE; val 303 drivers/power/supply/act8945a_charger.c *val = MAX_CURRENT_AC_LOW_PRE; val 305 drivers/power/supply/act8945a_charger.c *val = MAX_CURRENT_USB_PRE; val 311 drivers/power/supply/act8945a_charger.c *val = MAX_CURRENT_AC_HIGH; val 313 drivers/power/supply/act8945a_charger.c *val = MAX_CURRENT_AC_LOW; val 316 drivers/power/supply/act8945a_charger.c *val = MAX_CURRENT_USB_HIGH; val 318 drivers/power/supply/act8945a_charger.c *val = MAX_CURRENT_USB_LOW; val 324 drivers/power/supply/act8945a_charger.c *val = 0; val 344 drivers/power/supply/act8945a_charger.c union power_supply_propval *val) val 352 drivers/power/supply/act8945a_charger.c ret = act8945a_get_charger_state(regmap, &val->intval); val 355 drivers/power/supply/act8945a_charger.c ret = act8945a_get_charge_type(regmap, &val->intval); val 358 drivers/power/supply/act8945a_charger.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 361 drivers/power/supply/act8945a_charger.c ret = act8945a_get_battery_health(regmap, &val->intval); val 365 drivers/power/supply/act8945a_charger.c regmap, &val->intval); val 369 drivers/power/supply/act8945a_charger.c regmap, &val->intval); val 372 drivers/power/supply/act8945a_charger.c val->strval = act8945a_charger_model; val 375 drivers/power/supply/act8945a_charger.c val->strval = act8945a_charger_manufacturer; val 145 drivers/power/supply/adp5061.c static int adp5061_get_array_index(const int *array, u8 size, int val) val 150 drivers/power/supply/adp5061.c if (val < array[i]) val 176 drivers/power/supply/adp5061.c union power_supply_propval *val) val 186 drivers/power/supply/adp5061.c val->intval = adp5061_in_current_lim[mode] * 1000; val 191 drivers/power/supply/adp5061.c static int adp5061_set_input_current_limit(struct adp5061_state *st, int val) val 196 drivers/power/supply/adp5061.c val /= 1000; val 199 drivers/power/supply/adp5061.c val); val 208 drivers/power/supply/adp5061.c static int adp5061_set_min_voltage(struct adp5061_state *st, int val) val 213 drivers/power/supply/adp5061.c val /= 1000; val 216 drivers/power/supply/adp5061.c val); val 226 drivers/power/supply/adp5061.c union power_supply_propval *val) val 236 drivers/power/supply/adp5061.c val->intval = adp5061_vmin[regval] * 1000; val 242 drivers/power/supply/adp5061.c union power_supply_propval *val) val 252 drivers/power/supply/adp5061.c val->intval = adp5061_const_chg_vmax[mode] * 1000; val 258 drivers/power/supply/adp5061.c union power_supply_propval *val) val 271 drivers/power/supply/adp5061.c val->intval = adp5061_vmax[regval] * 1000; val 276 drivers/power/supply/adp5061.c static int adp5061_set_max_voltage(struct adp5061_state *st, int val) val 281 drivers/power/supply/adp5061.c val /= 1000; val 282 drivers/power/supply/adp5061.c if (val > 4500) val 283 drivers/power/supply/adp5061.c val = 4500; val 286 drivers/power/supply/adp5061.c ARRAY_SIZE(adp5061_vmax), val); val 297 drivers/power/supply/adp5061.c static int adp5061_set_const_chg_vmax(struct adp5061_state *st, int val) val 302 drivers/power/supply/adp5061.c val /= 1000; val 305 drivers/power/supply/adp5061.c val); val 314 drivers/power/supply/adp5061.c static int adp5061_set_const_chg_current(struct adp5061_state *st, int val) val 320 drivers/power/supply/adp5061.c val /= 1000; val 321 drivers/power/supply/adp5061.c if (val > ADP5061_ICHG_MAX) val 322 drivers/power/supply/adp5061.c val = ADP5061_ICHG_MAX; val 326 drivers/power/supply/adp5061.c val); val 336 drivers/power/supply/adp5061.c union power_supply_propval *val) val 349 drivers/power/supply/adp5061.c val->intval = adp5061_const_ichg[regval] * 1000; val 355 drivers/power/supply/adp5061.c union power_supply_propval *val) val 365 drivers/power/supply/adp5061.c val->intval = adp5061_prechg_current[regval] * 1000; val 370 drivers/power/supply/adp5061.c static int adp5061_set_prechg_current(struct adp5061_state *st, int val) val 375 drivers/power/supply/adp5061.c val /= 1000; val 378 drivers/power/supply/adp5061.c val); val 388 drivers/power/supply/adp5061.c union power_supply_propval *val) val 398 drivers/power/supply/adp5061.c val->intval = adp5061_vweak_th[regval] * 1000; val 403 drivers/power/supply/adp5061.c static int adp5061_set_vweak_th(struct adp5061_state *st, int val) val 408 drivers/power/supply/adp5061.c val /= 1000; val 411 drivers/power/supply/adp5061.c val); val 421 drivers/power/supply/adp5061.c union power_supply_propval *val) val 432 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 434 drivers/power/supply/adp5061.c val->intval = chg_type; val 440 drivers/power/supply/adp5061.c union power_supply_propval *val) val 451 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 456 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 459 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_STATUS_FULL; val 463 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 466 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 473 drivers/power/supply/adp5061.c union power_supply_propval *val) val 485 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN; val 488 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; val 491 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_LOW; val 494 drivers/power/supply/adp5061.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; val 502 drivers/power/supply/adp5061.c union power_supply_propval *val) val 512 drivers/power/supply/adp5061.c val->intval = adp5061_iend[regval]; val 517 drivers/power/supply/adp5061.c static int adp5061_set_termination_current(struct adp5061_state *st, int val) val 523 drivers/power/supply/adp5061.c val); val 534 drivers/power/supply/adp5061.c union power_supply_propval *val) val 548 drivers/power/supply/adp5061.c val->intval = 0; val 550 drivers/power/supply/adp5061.c val->intval = 1; val 553 drivers/power/supply/adp5061.c return adp5061_get_chg_type(st, val); val 558 drivers/power/supply/adp5061.c return adp5061_get_input_current_limit(st, val); val 563 drivers/power/supply/adp5061.c return adp5061_get_max_voltage(st, val); val 569 drivers/power/supply/adp5061.c return adp5061_get_min_voltage(st, val); val 574 drivers/power/supply/adp5061.c return adp5061_get_chg_volt_lim(st, val); val 580 drivers/power/supply/adp5061.c return adp5061_get_const_chg_current(st, val); val 586 drivers/power/supply/adp5061.c return adp5061_get_prechg_current(st, val); val 593 drivers/power/supply/adp5061.c return adp5061_get_vweak_th(st, val); val 599 drivers/power/supply/adp5061.c return adp5061_get_charger_status(st, val); val 605 drivers/power/supply/adp5061.c return adp5061_get_battery_status(st, val); val 608 drivers/power/supply/adp5061.c return adp5061_get_termination_current(st, val); val 618 drivers/power/supply/adp5061.c const union power_supply_propval *val) val 624 drivers/power/supply/adp5061.c return adp5061_set_input_current_limit(st, val->intval); val 626 drivers/power/supply/adp5061.c return adp5061_set_max_voltage(st, val->intval); val 628 drivers/power/supply/adp5061.c return adp5061_set_min_voltage(st, val->intval); val 630 drivers/power/supply/adp5061.c return adp5061_set_const_chg_vmax(st, val->intval); val 632 drivers/power/supply/adp5061.c return adp5061_set_const_chg_current(st, val->intval); val 634 drivers/power/supply/adp5061.c return adp5061_set_prechg_current(st, val->intval); val 636 drivers/power/supply/adp5061.c return adp5061_set_vweak_th(st, val->intval); val 638 drivers/power/supply/adp5061.c return adp5061_set_termination_current(st, val->intval); val 18 drivers/power/supply/apm_power.c #define PSY_PROP(psy, prop, val) (power_supply_get_property(psy, \ val 19 drivers/power/supply/apm_power.c POWER_SUPPLY_PROP_##prop, val)) val 21 drivers/power/supply/apm_power.c #define _MPSY_PROP(prop, val) (power_supply_get_property(main_battery, \ val 22 drivers/power/supply/apm_power.c prop, val)) val 24 drivers/power/supply/apm_power.c #define MPSY_PROP(prop, val) _MPSY_PROP(POWER_SUPPLY_PROP_##prop, val) val 59 drivers/power/supply/axp20x_ac_power.c union power_supply_propval *val) val 71 drivers/power/supply/axp20x_ac_power.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 75 drivers/power/supply/axp20x_ac_power.c val->intval = POWER_SUPPLY_HEALTH_UNKNOWN; val 83 drivers/power/supply/axp20x_ac_power.c val->intval = !!(reg & AXP20X_PWR_STATUS_ACIN_PRESENT); val 91 drivers/power/supply/axp20x_ac_power.c val->intval = !!(reg & AXP20X_PWR_STATUS_ACIN_AVAIL); val 94 drivers/power/supply/axp20x_ac_power.c if (val->intval && power->has_acin_path_sel) { val 100 drivers/power/supply/axp20x_ac_power.c val->intval = !!(reg & AXP813_ACIN_PATH_SEL); val 106 drivers/power/supply/axp20x_ac_power.c ret = iio_read_channel_processed(power->acin_v, &val->intval); val 111 drivers/power/supply/axp20x_ac_power.c val->intval *= 1000; val 116 drivers/power/supply/axp20x_ac_power.c ret = iio_read_channel_processed(power->acin_i, &val->intval); val 121 drivers/power/supply/axp20x_ac_power.c val->intval *= 1000; val 130 drivers/power/supply/axp20x_ac_power.c val->intval = AXP813_VHOLD_REG_TO_UV(reg); val 139 drivers/power/supply/axp20x_ac_power.c val->intval = AXP813_CURR_LIMIT_REG_TO_UA(reg); val 141 drivers/power/supply/axp20x_ac_power.c if (val->intval > 4000000) val 142 drivers/power/supply/axp20x_ac_power.c val->intval = 4000000; val 155 drivers/power/supply/axp20x_ac_power.c const union power_supply_propval *val) val 161 drivers/power/supply/axp20x_ac_power.c if (val->intval < 4000000 || val->intval > 4700000) val 166 drivers/power/supply/axp20x_ac_power.c AXP813_VHOLD_UV_TO_BIT(val->intval)); val 169 drivers/power/supply/axp20x_ac_power.c if (val->intval < 1500000 || val->intval > 4000000) val 174 drivers/power/supply/axp20x_ac_power.c AXP813_CURR_LIMIT_UA_TO_BIT(val->intval)); val 64 drivers/power/supply/axp20x_battery.c int (*get_max_voltage)(struct axp20x_batt_ps *batt, int *val); val 65 drivers/power/supply/axp20x_battery.c int (*set_max_voltage)(struct axp20x_batt_ps *batt, int val); val 81 drivers/power/supply/axp20x_battery.c int *val) val 91 drivers/power/supply/axp20x_battery.c *val = 4100000; val 94 drivers/power/supply/axp20x_battery.c *val = 4150000; val 97 drivers/power/supply/axp20x_battery.c *val = 4200000; val 100 drivers/power/supply/axp20x_battery.c *val = 4360000; val 110 drivers/power/supply/axp20x_battery.c int *val) val 120 drivers/power/supply/axp20x_battery.c *val = 4100000; val 123 drivers/power/supply/axp20x_battery.c *val = 4200000; val 126 drivers/power/supply/axp20x_battery.c *val = 4220000; val 129 drivers/power/supply/axp20x_battery.c *val = 4240000; val 139 drivers/power/supply/axp20x_battery.c int *val) val 149 drivers/power/supply/axp20x_battery.c *val = 4100000; val 152 drivers/power/supply/axp20x_battery.c *val = 4150000; val 155 drivers/power/supply/axp20x_battery.c *val = 4200000; val 158 drivers/power/supply/axp20x_battery.c *val = 4350000; val 168 drivers/power/supply/axp20x_battery.c int *val) val 172 drivers/power/supply/axp20x_battery.c ret = regmap_read(axp->regmap, AXP20X_CHRG_CTRL1, val); val 176 drivers/power/supply/axp20x_battery.c *val &= AXP20X_CHRG_CTRL1_TGT_CURR; val 178 drivers/power/supply/axp20x_battery.c *val = *val * axp->data->ccc_scale + axp->data->ccc_offset; val 185 drivers/power/supply/axp20x_battery.c union power_supply_propval *val) val 199 drivers/power/supply/axp20x_battery.c val->intval = !!(reg & AXP20X_PWR_OP_BATT_PRESENT); val 209 drivers/power/supply/axp20x_battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 219 drivers/power/supply/axp20x_battery.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 232 drivers/power/supply/axp20x_battery.c val->intval = POWER_SUPPLY_STATUS_FULL; val 234 drivers/power/supply/axp20x_battery.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 244 drivers/power/supply/axp20x_battery.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 248 drivers/power/supply/axp20x_battery.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 253 drivers/power/supply/axp20x_battery.c &val->intval); val 259 drivers/power/supply/axp20x_battery.c val->intval = axp20x_batt->max_ccc; val 273 drivers/power/supply/axp20x_battery.c ret = iio_read_channel_processed(chan, &val->intval); val 278 drivers/power/supply/axp20x_battery.c val->intval *= 1000; val 289 drivers/power/supply/axp20x_battery.c val->intval = 100; val 304 drivers/power/supply/axp20x_battery.c val->intval = reg & AXP209_FG_PERCENT; val 309 drivers/power/supply/axp20x_battery.c &val->intval); val 316 drivers/power/supply/axp20x_battery.c val->intval = 2600000 + 100000 * (reg & AXP20X_V_OFF_MASK); val 321 drivers/power/supply/axp20x_battery.c &val->intval); val 326 drivers/power/supply/axp20x_battery.c val->intval *= 1000; val 337 drivers/power/supply/axp20x_battery.c int val) val 339 drivers/power/supply/axp20x_battery.c switch (val) { val 341 drivers/power/supply/axp20x_battery.c val = AXP20X_CHRG_CTRL1_TGT_4_1V; val 345 drivers/power/supply/axp20x_battery.c val = AXP20X_CHRG_CTRL1_TGT_4_2V; val 359 drivers/power/supply/axp20x_battery.c AXP20X_CHRG_CTRL1_TGT_VOLT, val); val 363 drivers/power/supply/axp20x_battery.c int val) val 365 drivers/power/supply/axp20x_battery.c switch (val) { val 367 drivers/power/supply/axp20x_battery.c val = AXP20X_CHRG_CTRL1_TGT_4_1V; val 371 drivers/power/supply/axp20x_battery.c val = AXP20X_CHRG_CTRL1_TGT_4_15V; val 375 drivers/power/supply/axp20x_battery.c val = AXP20X_CHRG_CTRL1_TGT_4_2V; val 389 drivers/power/supply/axp20x_battery.c AXP20X_CHRG_CTRL1_TGT_VOLT, val); val 454 drivers/power/supply/axp20x_battery.c const union power_supply_propval *val) val 460 drivers/power/supply/axp20x_battery.c return axp20x_set_voltage_min_design(axp20x_batt, val->intval); val 463 drivers/power/supply/axp20x_battery.c return axp20x_batt->data->set_max_voltage(axp20x_batt, val->intval); val 467 drivers/power/supply/axp20x_battery.c val->intval); val 470 drivers/power/supply/axp20x_battery.c val->intval); val 81 drivers/power/supply/axp20x_usb_power.c unsigned int val; val 84 drivers/power/supply/axp20x_usb_power.c ret = regmap_read(power->regmap, AXP20X_PWR_INPUT_STATUS, &val); val 88 drivers/power/supply/axp20x_usb_power.c val &= (AXP20X_PWR_STATUS_VBUS_PRESENT | AXP20X_PWR_STATUS_VBUS_USED); val 89 drivers/power/supply/axp20x_usb_power.c if (val != power->old_status) val 92 drivers/power/supply/axp20x_usb_power.c power->old_status = val; val 106 drivers/power/supply/axp20x_usb_power.c static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val) val 117 drivers/power/supply/axp20x_usb_power.c *val = -1; /* No 100mA limit */ val 119 drivers/power/supply/axp20x_usb_power.c *val = 100000; val 122 drivers/power/supply/axp20x_usb_power.c *val = 500000; val 125 drivers/power/supply/axp20x_usb_power.c *val = 900000; val 128 drivers/power/supply/axp20x_usb_power.c *val = -1; val 135 drivers/power/supply/axp20x_usb_power.c static int axp813_get_current_max(struct axp20x_usb_power *power, int *val) val 145 drivers/power/supply/axp20x_usb_power.c *val = 900000; val 148 drivers/power/supply/axp20x_usb_power.c *val = 1500000; val 151 drivers/power/supply/axp20x_usb_power.c *val = 2000000; val 154 drivers/power/supply/axp20x_usb_power.c *val = 2500000; val 161 drivers/power/supply/axp20x_usb_power.c enum power_supply_property psp, union power_supply_propval *val) val 173 drivers/power/supply/axp20x_usb_power.c val->intval = AXP20X_VBUS_VHOLD_uV(v); val 178 drivers/power/supply/axp20x_usb_power.c &val->intval); val 186 drivers/power/supply/axp20x_usb_power.c val->intval *= 1000; val 195 drivers/power/supply/axp20x_usb_power.c val->intval = ret * 1700; /* 1 step = 1.7 mV */ val 199 drivers/power/supply/axp20x_usb_power.c return axp813_get_current_max(power, &val->intval); val 200 drivers/power/supply/axp20x_usb_power.c return axp20x_get_current_max(power, &val->intval); val 204 drivers/power/supply/axp20x_usb_power.c &val->intval); val 212 drivers/power/supply/axp20x_usb_power.c val->intval *= 1000; val 221 drivers/power/supply/axp20x_usb_power.c val->intval = ret * 375; /* 1 step = 0.375 mA */ val 235 drivers/power/supply/axp20x_usb_power.c val->intval = POWER_SUPPLY_HEALTH_UNKNOWN; val 239 drivers/power/supply/axp20x_usb_power.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 248 drivers/power/supply/axp20x_usb_power.c val->intval = val 253 drivers/power/supply/axp20x_usb_power.c val->intval = !!(input & AXP20X_PWR_STATUS_VBUS_PRESENT); val 256 drivers/power/supply/axp20x_usb_power.c val->intval = !!(input & AXP20X_PWR_STATUS_VBUS_USED); val 268 drivers/power/supply/axp20x_usb_power.c int val; val 279 drivers/power/supply/axp20x_usb_power.c val = (intval - 4000000) / 100000; val 283 drivers/power/supply/axp20x_usb_power.c val << AXP20X_VBUS_VHOLD_OFFSET); val 294 drivers/power/supply/axp20x_usb_power.c int val; val 305 drivers/power/supply/axp20x_usb_power.c val = (intval - 1000000) / 500000; val 308 drivers/power/supply/axp20x_usb_power.c AXP20X_VBUS_CLIMIT_MASK, val); val 319 drivers/power/supply/axp20x_usb_power.c int val; val 328 drivers/power/supply/axp20x_usb_power.c val = (900000 - intval) / 400000; val 331 drivers/power/supply/axp20x_usb_power.c AXP20X_VBUS_CLIMIT_MASK, val); val 341 drivers/power/supply/axp20x_usb_power.c const union power_supply_propval *val) val 347 drivers/power/supply/axp20x_usb_power.c return axp20x_usb_power_set_voltage_min(power, val->intval); val 352 drivers/power/supply/axp20x_usb_power.c val->intval); val 353 drivers/power/supply/axp20x_usb_power.c return axp20x_usb_power_set_current_max(power, val->intval); val 199 drivers/power/supply/axp288_charger.c unsigned int val; val 202 drivers/power/supply/axp288_charger.c ret = regmap_read(info->regmap, AXP20X_CHRG_BAK_CTRL, &val); val 206 drivers/power/supply/axp288_charger.c val >>= CHRG_VBUS_ILIM_BIT_POS; val 207 drivers/power/supply/axp288_charger.c switch (val) { val 301 drivers/power/supply/axp288_charger.c unsigned int val; val 303 drivers/power/supply/axp288_charger.c ret = regmap_read(info->regmap, AXP20X_PWR_INPUT_STATUS, &val); val 307 drivers/power/supply/axp288_charger.c if (val & PS_STAT_VBUS_PRESENT) val 315 drivers/power/supply/axp288_charger.c unsigned int val; val 317 drivers/power/supply/axp288_charger.c ret = regmap_read(info->regmap, AXP20X_PWR_INPUT_STATUS, &val); val 321 drivers/power/supply/axp288_charger.c if (val & PS_STAT_VBUS_VALID) val 330 drivers/power/supply/axp288_charger.c unsigned int val; val 332 drivers/power/supply/axp288_charger.c ret = regmap_read(info->regmap, AXP20X_PWR_INPUT_STATUS, &val); val 333 drivers/power/supply/axp288_charger.c if ((ret < 0) || !(val & PS_STAT_VBUS_PRESENT)) val 336 drivers/power/supply/axp288_charger.c pwr_stat = val; val 338 drivers/power/supply/axp288_charger.c ret = regmap_read(info->regmap, AXP20X_PWR_OP_MODE, &val); val 342 drivers/power/supply/axp288_charger.c chrg_stat = val; val 359 drivers/power/supply/axp288_charger.c const union power_supply_propval *val) val 367 drivers/power/supply/axp288_charger.c scaled_val = min(val->intval, info->max_cc); val 374 drivers/power/supply/axp288_charger.c scaled_val = min(val->intval, info->max_cv); val 381 drivers/power/supply/axp288_charger.c ret = axp288_charger_set_vbus_inlmt(info, val->intval); val 394 drivers/power/supply/axp288_charger.c union power_supply_propval *val) val 403 drivers/power/supply/axp288_charger.c val->intval = 0; val 409 drivers/power/supply/axp288_charger.c val->intval = ret; val 414 drivers/power/supply/axp288_charger.c val->intval = 0; val 420 drivers/power/supply/axp288_charger.c val->intval = ret; val 423 drivers/power/supply/axp288_charger.c val->intval = axp288_get_charger_health(info); val 426 drivers/power/supply/axp288_charger.c val->intval = info->cc * 1000; val 429 drivers/power/supply/axp288_charger.c val->intval = info->max_cc * 1000; val 432 drivers/power/supply/axp288_charger.c val->intval = info->cv * 1000; val 435 drivers/power/supply/axp288_charger.c val->intval = info->max_cv * 1000; val 441 drivers/power/supply/axp288_charger.c val->intval = ret; val 598 drivers/power/supply/axp288_charger.c unsigned int val; val 600 drivers/power/supply/axp288_charger.c ret = regmap_read(info->regmap, AXP20X_PWR_INPUT_STATUS, &val); val 607 drivers/power/supply/axp288_charger.c if (!(val & PS_STAT_VBUS_VALID)) { val 689 drivers/power/supply/axp288_charger.c unsigned int val; val 744 drivers/power/supply/axp288_charger.c ret = regmap_read(info->regmap, AXP20X_CHRG_CTRL1, &val); val 752 drivers/power/supply/axp288_charger.c cv = (val & CHRG_CCCV_CV_MASK) >> CHRG_CCCV_CV_BIT_POS; val 769 drivers/power/supply/axp288_charger.c cc = (val & CHRG_CCCV_CC_MASK) >> CHRG_CCCV_CC_BIT_POS; val 798 drivers/power/supply/axp288_charger.c unsigned int val; val 804 drivers/power/supply/axp288_charger.c ret = regmap_read(axp20x->regmap, AXP20X_CC_CTRL, &val); val 807 drivers/power/supply/axp288_charger.c if (val == 0) val 141 drivers/power/supply/axp288_fuel_gauge.c unsigned int val; val 144 drivers/power/supply/axp288_fuel_gauge.c ret = regmap_read(info->regmap, reg, &val); val 156 drivers/power/supply/axp288_fuel_gauge.c return val; val 159 drivers/power/supply/axp288_fuel_gauge.c static int fuel_gauge_reg_writeb(struct axp288_fg_info *info, int reg, u8 val) val 163 drivers/power/supply/axp288_fuel_gauge.c ret = regmap_write(info->regmap, reg, (unsigned int)val); val 436 drivers/power/supply/axp288_fuel_gauge.c union power_supply_propval *val) val 445 drivers/power/supply/axp288_fuel_gauge.c val->intval = info->status; val 448 drivers/power/supply/axp288_fuel_gauge.c val->intval = fuel_gauge_battery_health(info); val 454 drivers/power/supply/axp288_fuel_gauge.c val->intval = PROP_VOLT(value); val 460 drivers/power/supply/axp288_fuel_gauge.c val->intval = PROP_VOLT(value); val 466 drivers/power/supply/axp288_fuel_gauge.c val->intval = PROP_CURR(value); val 474 drivers/power/supply/axp288_fuel_gauge.c val->intval = 1; val 476 drivers/power/supply/axp288_fuel_gauge.c val->intval = 0; val 486 drivers/power/supply/axp288_fuel_gauge.c val->intval = (ret & FG_REP_CAP_VAL_MASK); val 492 drivers/power/supply/axp288_fuel_gauge.c val->intval = (ret & 0x0f); val 495 drivers/power/supply/axp288_fuel_gauge.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 502 drivers/power/supply/axp288_fuel_gauge.c val->intval = ret * FG_DES_CAP_RES_LSB; val 509 drivers/power/supply/axp288_fuel_gauge.c val->intval = ret * FG_DES_CAP_RES_LSB; val 512 drivers/power/supply/axp288_fuel_gauge.c val->intval = PROP_VOLT(info->max_volt); val 529 drivers/power/supply/axp288_fuel_gauge.c const union power_supply_propval *val) val 537 drivers/power/supply/axp288_fuel_gauge.c if ((val->intval < 0) || (val->intval > 15)) { val 545 drivers/power/supply/axp288_fuel_gauge.c ret |= (val->intval & 0xf); val 753 drivers/power/supply/axp288_fuel_gauge.c unsigned int val; val 762 drivers/power/supply/axp288_fuel_gauge.c ret = regmap_read(axp20x->regmap, AXP20X_CC_CTRL, &val); val 765 drivers/power/supply/axp288_fuel_gauge.c if (val == 0) val 200 drivers/power/supply/bd70528-charger.c static int bd70528_get_charger_status(struct bd70528_psy *bdpsy, int *val) val 222 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_STATUS_NOT_CHARGING; val 225 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_STATUS_FULL; val 230 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_STATUS_CHARGING; val 233 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_STATUS_UNKNOWN; val 240 drivers/power/supply/bd70528-charger.c static int bd70528_get_charge_type(struct bd70528_psy *bdpsy, int *val) val 254 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 258 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_CHARGE_TYPE_FAST; val 270 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_CHARGE_TYPE_NONE; val 273 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN; val 280 drivers/power/supply/bd70528-charger.c static int bd70528_get_battery_health(struct bd70528_psy *bdpsy, int *val) val 293 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_HEALTH_DEAD; val 295 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 297 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; val 299 drivers/power/supply/bd70528-charger.c *val = POWER_SUPPLY_HEALTH_GOOD; val 304 drivers/power/supply/bd70528-charger.c static int bd70528_get_online(struct bd70528_psy *bdpsy, int *val) val 316 drivers/power/supply/bd70528-charger.c *val = (v & BD70528_MASK_CHG_DCIN1_UVLO) ? 1 : 0; val 321 drivers/power/supply/bd70528-charger.c static int bd70528_get_present(struct bd70528_psy *bdpsy, int *val) val 333 drivers/power/supply/bd70528-charger.c *val = (v & BD70528_MASK_CHG_BAT_DETECT) ? 1 : 0; val 403 drivers/power/supply/bd70528-charger.c unsigned int *val) val 409 drivers/power/supply/bd70528-charger.c *val = r[i].min + (sel - r[i].low_sel) * r[i].step; val 424 drivers/power/supply/bd70528-charger.c int selectors, unsigned int val, val 432 drivers/power/supply/bd70528-charger.c if (r[i].min <= val) { val 433 drivers/power/supply/bd70528-charger.c if (r[i].min + r[i].step * r[i].vals >= val) { val 435 drivers/power/supply/bd70528-charger.c *sel = r[i].low_sel + (val - r[i].min) / val 519 drivers/power/supply/bd70528-charger.c union power_supply_propval *val) val 526 drivers/power/supply/bd70528-charger.c return bd70528_get_charger_status(bdpsy, &val->intval); val 528 drivers/power/supply/bd70528-charger.c return bd70528_get_charge_type(bdpsy, &val->intval); val 530 drivers/power/supply/bd70528-charger.c return bd70528_get_battery_health(bdpsy, &val->intval); val 532 drivers/power/supply/bd70528-charger.c return bd70528_get_present(bdpsy, &val->intval); val 534 drivers/power/supply/bd70528-charger.c ret = get_current_limit(bdpsy, &val->intval); val 535 drivers/power/supply/bd70528-charger.c val->intval *= 1000; val 538 drivers/power/supply/bd70528-charger.c ret = get_charge_current(bdpsy, &val->intval); val 539 drivers/power/supply/bd70528-charger.c val->intval *= 1000; val 542 drivers/power/supply/bd70528-charger.c return bd70528_get_online(bdpsy, &val->intval); val 544 drivers/power/supply/bd70528-charger.c val->strval = bd70528_charger_model; val 547 drivers/power/supply/bd70528-charger.c val->strval = bd70528_charger_manufacturer; val 677 drivers/power/supply/bd70528-charger.c const union power_supply_propval *val) val 683 drivers/power/supply/bd70528-charger.c return set_current_limit(bdpsy, val->intval / 1000); val 685 drivers/power/supply/bd70528-charger.c return set_charge_current(bdpsy, val->intval / 1000); val 191 drivers/power/supply/bq2415x_charger.c u8 val; val 203 drivers/power/supply/bq2415x_charger.c msg[1].buf = &val; val 204 drivers/power/supply/bq2415x_charger.c msg[1].len = sizeof(val); val 213 drivers/power/supply/bq2415x_charger.c return val; val 242 drivers/power/supply/bq2415x_charger.c static int bq2415x_i2c_write(struct bq2415x_device *bq, u8 reg, u8 val) val 250 drivers/power/supply/bq2415x_charger.c data[1] = val; val 271 drivers/power/supply/bq2415x_charger.c static int bq2415x_i2c_write_mask(struct bq2415x_device *bq, u8 reg, u8 val, val 284 drivers/power/supply/bq2415x_charger.c ret |= val << shift; val 291 drivers/power/supply/bq2415x_charger.c bool val, u8 bit) val 295 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write_mask(bq, reg, val, BIT(bit), bit); val 524 drivers/power/supply/bq2415x_charger.c int val; val 527 drivers/power/supply/bq2415x_charger.c val = 0; val 529 drivers/power/supply/bq2415x_charger.c val = 1; val 531 drivers/power/supply/bq2415x_charger.c val = 2; val 533 drivers/power/supply/bq2415x_charger.c val = 3; val 535 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write_mask(bq, BQ2415X_REG_CONTROL, val, val 562 drivers/power/supply/bq2415x_charger.c int val; val 566 drivers/power/supply/bq2415x_charger.c val = 0; val 568 drivers/power/supply/bq2415x_charger.c val = 1; val 570 drivers/power/supply/bq2415x_charger.c val = 2; val 572 drivers/power/supply/bq2415x_charger.c val = 3; val 574 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write_mask(bq, BQ2415X_REG_CONTROL, val, val 594 drivers/power/supply/bq2415x_charger.c int val = (mV/10 - 350) / 2; val 600 drivers/power/supply/bq2415x_charger.c if (val < 0) val 601 drivers/power/supply/bq2415x_charger.c val = 0; val 602 drivers/power/supply/bq2415x_charger.c else if (val > 47) val 605 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write_mask(bq, BQ2415X_REG_VOLTAGE, val, val 623 drivers/power/supply/bq2415x_charger.c int val; val 628 drivers/power/supply/bq2415x_charger.c val = (mA * bq->init_data.resistor_sense - 37400) / 6800; val 629 drivers/power/supply/bq2415x_charger.c if (val < 0) val 630 drivers/power/supply/bq2415x_charger.c val = 0; val 631 drivers/power/supply/bq2415x_charger.c else if (val > 7) val 632 drivers/power/supply/bq2415x_charger.c val = 7; val 634 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write_mask(bq, BQ2415X_REG_CURRENT, val, val 657 drivers/power/supply/bq2415x_charger.c int val; val 662 drivers/power/supply/bq2415x_charger.c val = (mA * bq->init_data.resistor_sense - 3400) / 3400; val 663 drivers/power/supply/bq2415x_charger.c if (val < 0) val 664 drivers/power/supply/bq2415x_charger.c val = 0; val 665 drivers/power/supply/bq2415x_charger.c else if (val > 7) val 666 drivers/power/supply/bq2415x_charger.c val = 7; val 668 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write_mask(bq, BQ2415X_REG_CURRENT, val, val 807 drivers/power/supply/bq2415x_charger.c unsigned long val, void *v) val 815 drivers/power/supply/bq2415x_charger.c if (val != PSY_EVENT_PROP_CHANGED) val 998 drivers/power/supply/bq2415x_charger.c union power_supply_propval *val) val 1009 drivers/power/supply/bq2415x_charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 1011 drivers/power/supply/bq2415x_charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 1013 drivers/power/supply/bq2415x_charger.c val->intval = POWER_SUPPLY_STATUS_FULL; val 1015 drivers/power/supply/bq2415x_charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 1018 drivers/power/supply/bq2415x_charger.c val->strval = bq->model; val 1242 drivers/power/supply/bq2415x_charger.c unsigned int val; val 1244 drivers/power/supply/bq2415x_charger.c if (sscanf(buf, "%x %x", ®, &val) != 2) val 1247 drivers/power/supply/bq2415x_charger.c if (reg > 4 || val > 255) val 1250 drivers/power/supply/bq2415x_charger.c ret = bq2415x_i2c_write(bq, reg, val); val 1293 drivers/power/supply/bq2415x_charger.c long val; val 1296 drivers/power/supply/bq2415x_charger.c if (kstrtol(buf, 10, &val) < 0) val 1300 drivers/power/supply/bq2415x_charger.c ret = bq2415x_set_current_limit(bq, val); val 1302 drivers/power/supply/bq2415x_charger.c ret = bq2415x_set_weak_battery_voltage(bq, val); val 1304 drivers/power/supply/bq2415x_charger.c ret = bq2415x_set_battery_regulation_voltage(bq, val); val 1306 drivers/power/supply/bq2415x_charger.c ret = bq2415x_set_charge_current(bq, val); val 1308 drivers/power/supply/bq2415x_charger.c ret = bq2415x_set_termination_current(bq, val); val 1353 drivers/power/supply/bq2415x_charger.c long val; val 1356 drivers/power/supply/bq2415x_charger.c if (kstrtol(buf, 10, &val) < 0) val 1360 drivers/power/supply/bq2415x_charger.c command = val ? BQ2415X_CHARGE_TERMINATION_ENABLE : val 1363 drivers/power/supply/bq2415x_charger.c command = val ? BQ2415X_HIGH_IMPEDANCE_ENABLE : val 1366 drivers/power/supply/bq2415x_charger.c command = val ? BQ2415X_OTG_PIN_ENABLE : val 1369 drivers/power/supply/bq2415x_charger.c command = val ? BQ2415X_STAT_PIN_ENABLE : val 295 drivers/power/supply/bq24190_charger.c int *val) val 305 drivers/power/supply/bq24190_charger.c *val = tbl[v]; val 313 drivers/power/supply/bq24190_charger.c int val) val 317 drivers/power/supply/bq24190_charger.c idx = bq24190_find_idx(tbl, tbl_size, val); val 499 drivers/power/supply/bq24190_charger.c static int bq24190_set_charge_mode(struct regulator_dev *dev, u8 val) val 513 drivers/power/supply/bq24190_charger.c BQ24190_REG_POC_CHG_CONFIG_SHIFT, val); val 535 drivers/power/supply/bq24190_charger.c u8 val; val 546 drivers/power/supply/bq24190_charger.c BQ24190_REG_POC_CHG_CONFIG_SHIFT, &val); val 551 drivers/power/supply/bq24190_charger.c return ret ? ret : val == BQ24190_REG_POC_CHG_CONFIG_OTG; val 710 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 737 drivers/power/supply/bq24190_charger.c val->intval = type; val 743 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 758 drivers/power/supply/bq24190_charger.c switch (val->intval) { val 798 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 857 drivers/power/supply/bq24190_charger.c val->intval = health; val 863 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 880 drivers/power/supply/bq24190_charger.c val->intval = pg_stat && !batfet_disable; val 886 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val); val 888 drivers/power/supply/bq24190_charger.c union power_supply_propval *val); val 890 drivers/power/supply/bq24190_charger.c union power_supply_propval *val); val 892 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val); val 895 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 897 drivers/power/supply/bq24190_charger.c return bq24190_battery_set_online(bdi, val); val 901 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 903 drivers/power/supply/bq24190_charger.c return bq24190_battery_get_status(bdi, val); val 907 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 909 drivers/power/supply/bq24190_charger.c return bq24190_battery_get_temp_alert_max(bdi, val); val 913 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 915 drivers/power/supply/bq24190_charger.c return bq24190_battery_set_temp_alert_max(bdi, val); val 919 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 930 drivers/power/supply/bq24190_charger.c val->intval = ++v * 128 * 1000; val 935 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 946 drivers/power/supply/bq24190_charger.c val->intval = ++v * 128 * 1000; val 951 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 973 drivers/power/supply/bq24190_charger.c val->intval = curr; val 978 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 982 drivers/power/supply/bq24190_charger.c val->intval = bq24190_ccc_ichg_values[idx]; val 987 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 990 drivers/power/supply/bq24190_charger.c int ret, curr = val->intval; val 1009 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 1020 drivers/power/supply/bq24190_charger.c val->intval = voltage; val 1025 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 1029 drivers/power/supply/bq24190_charger.c val->intval = bq24190_cvc_vreg_values[idx]; val 1034 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 1039 drivers/power/supply/bq24190_charger.c ARRAY_SIZE(bq24190_cvc_vreg_values), val->intval); val 1043 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 1055 drivers/power/supply/bq24190_charger.c val->intval = iinlimit; val 1060 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 1066 drivers/power/supply/bq24190_charger.c ARRAY_SIZE(bq24190_isc_iinlim_values), val->intval); val 1070 drivers/power/supply/bq24190_charger.c enum power_supply_property psp, union power_supply_propval *val) val 1083 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_charge_type(bdi, val); val 1086 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_health(bdi, val); val 1089 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_online(bdi, val); val 1092 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_status(bdi, val); val 1095 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_temp_alert_max(bdi, val); val 1098 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_precharge(bdi, val); val 1101 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_charge_term(bdi, val); val 1104 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_current(bdi, val); val 1107 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_current_max(bdi, val); val 1110 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_voltage(bdi, val); val 1113 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_voltage_max(bdi, val); val 1116 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_get_iinlimit(bdi, val); val 1119 drivers/power/supply/bq24190_charger.c val->intval = POWER_SUPPLY_SCOPE_SYSTEM; val 1123 drivers/power/supply/bq24190_charger.c val->strval = bdi->model_name; val 1127 drivers/power/supply/bq24190_charger.c val->strval = BQ24190_MANUFACTURER; val 1142 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 1155 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_set_online(bdi, val); val 1158 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_set_temp_alert_max(bdi, val); val 1161 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_set_charge_type(bdi, val); val 1164 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_set_current(bdi, val); val 1167 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_set_voltage(bdi, val); val 1170 drivers/power/supply/bq24190_charger.c ret = bq24190_charger_set_iinlimit(bdi, val); val 1260 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 1306 drivers/power/supply/bq24190_charger.c val->intval = status; val 1312 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 1346 drivers/power/supply/bq24190_charger.c val->intval = health; val 1351 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 1362 drivers/power/supply/bq24190_charger.c val->intval = !batfet_disable; val 1367 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 1371 drivers/power/supply/bq24190_charger.c BQ24190_REG_MOC_BATFET_DISABLE_SHIFT, !val->intval); val 1375 drivers/power/supply/bq24190_charger.c union power_supply_propval *val) val 1387 drivers/power/supply/bq24190_charger.c val->intval = temp; val 1392 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 1398 drivers/power/supply/bq24190_charger.c ARRAY_SIZE(bq24190_ictrc_treg_values), val->intval); val 1402 drivers/power/supply/bq24190_charger.c enum power_supply_property psp, union power_supply_propval *val) val 1416 drivers/power/supply/bq24190_charger.c ret = bq24190_battery_get_status(bdi, val); val 1419 drivers/power/supply/bq24190_charger.c ret = bq24190_battery_get_health(bdi, val); val 1422 drivers/power/supply/bq24190_charger.c ret = bq24190_battery_get_online(bdi, val); val 1426 drivers/power/supply/bq24190_charger.c val->intval = POWER_SUPPLY_TECHNOLOGY_UNKNOWN; val 1430 drivers/power/supply/bq24190_charger.c ret = bq24190_battery_get_temp_alert_max(bdi, val); val 1433 drivers/power/supply/bq24190_charger.c val->intval = POWER_SUPPLY_SCOPE_SYSTEM; val 1448 drivers/power/supply/bq24190_charger.c const union power_supply_propval *val) val 1462 drivers/power/supply/bq24190_charger.c ret = bq24190_battery_set_online(bdi, val); val 1465 drivers/power/supply/bq24190_charger.c ret = bq24190_battery_set_temp_alert_max(bdi, val); val 214 drivers/power/supply/bq24257_charger.c int val; val 216 drivers/power/supply/bq24257_charger.c ret = regmap_field_read(bq->rmap_fields[field_id], &val); val 220 drivers/power/supply/bq24257_charger.c return val; val 224 drivers/power/supply/bq24257_charger.c enum bq24257_fields field_id, u8 val) val 226 drivers/power/supply/bq24257_charger.c return regmap_field_write(bq->rmap_fields[field_id], val); val 262 drivers/power/supply/bq24257_charger.c union power_supply_propval *val) val 280 drivers/power/supply/bq24257_charger.c val->intval = bq24257_iilimit_map[ret]; val 286 drivers/power/supply/bq24257_charger.c const union power_supply_propval *val) val 297 drivers/power/supply/bq24257_charger.c bq24257_find_idx(val->intval, val 304 drivers/power/supply/bq24257_charger.c union power_supply_propval *val) val 316 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 318 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 320 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 322 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_STATUS_FULL; val 324 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 328 drivers/power/supply/bq24257_charger.c val->strval = BQ24257_MANUFACTURER; val 332 drivers/power/supply/bq24257_charger.c val->strval = bq2425x_chip_name[bq->chip]; val 336 drivers/power/supply/bq24257_charger.c val->intval = state.power_good; val 342 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 347 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 352 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 356 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; val 360 drivers/power/supply/bq24257_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 367 drivers/power/supply/bq24257_charger.c val->intval = bq24257_ichg_map[bq->init_data.ichg]; val 371 drivers/power/supply/bq24257_charger.c val->intval = bq24257_ichg_map[BQ24257_ICHG_MAP_SIZE - 1]; val 375 drivers/power/supply/bq24257_charger.c val->intval = bq24257_vbat_map[bq->init_data.vbat]; val 379 drivers/power/supply/bq24257_charger.c val->intval = bq24257_vbat_map[BQ24257_VBAT_MAP_SIZE - 1]; val 383 drivers/power/supply/bq24257_charger.c val->intval = bq24257_iterm_map[bq->init_data.iterm]; val 387 drivers/power/supply/bq24257_charger.c return bq24257_get_input_current_limit(bq, val); val 398 drivers/power/supply/bq24257_charger.c const union power_supply_propval *val) val 404 drivers/power/supply/bq24257_charger.c return bq24257_set_input_current_limit(bq, val); val 813 drivers/power/supply/bq24257_charger.c long val; val 816 drivers/power/supply/bq24257_charger.c if (kstrtol(buf, 10, &val) < 0) val 820 drivers/power/supply/bq24257_charger.c ret = bq24257_field_write(bq, F_HZ_MODE, (bool)val); val 822 drivers/power/supply/bq24257_charger.c ret = bq24257_field_write(bq, F_SYSOFF, (bool)val); val 254 drivers/power/supply/bq24735-charger.c union power_supply_propval *val) val 260 drivers/power/supply/bq24735-charger.c val->intval = bq24735_charger_is_present(charger) ? 1 : 0; val 265 drivers/power/supply/bq24735-charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 268 drivers/power/supply/bq24735-charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 271 drivers/power/supply/bq24735-charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 284 drivers/power/supply/bq24735-charger.c const union power_supply_propval *val) val 291 drivers/power/supply/bq24735-charger.c switch (val->intval) { val 325 drivers/power/supply/bq24735-charger.c u32 val; val 335 drivers/power/supply/bq24735-charger.c ret = of_property_read_u32(np, "ti,charge-current", &val); val 337 drivers/power/supply/bq24735-charger.c pdata->charge_current = val; val 339 drivers/power/supply/bq24735-charger.c ret = of_property_read_u32(np, "ti,charge-voltage", &val); val 341 drivers/power/supply/bq24735-charger.c pdata->charge_voltage = val; val 343 drivers/power/supply/bq24735-charger.c ret = of_property_read_u32(np, "ti,input-current", &val); val 345 drivers/power/supply/bq24735-charger.c pdata->input_current = val; val 293 drivers/power/supply/bq25890_charger.c int val; val 295 drivers/power/supply/bq25890_charger.c ret = regmap_field_read(bq->rmap_fields[field_id], &val); val 299 drivers/power/supply/bq25890_charger.c return val; val 303 drivers/power/supply/bq25890_charger.c enum bq25890_fields field_id, u8 val) val 305 drivers/power/supply/bq25890_charger.c return regmap_field_write(bq->rmap_fields[field_id], val); val 363 drivers/power/supply/bq25890_charger.c union power_supply_propval *val) val 376 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 378 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 381 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 383 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_STATUS_FULL; val 385 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 390 drivers/power/supply/bq25890_charger.c val->strval = BQ25890_MANUFACTURER; val 395 drivers/power/supply/bq25890_charger.c val->strval = "BQ25890"; val 397 drivers/power/supply/bq25890_charger.c val->strval = "BQ25895"; val 399 drivers/power/supply/bq25890_charger.c val->strval = "BQ25896"; val 401 drivers/power/supply/bq25890_charger.c val->strval = "UNKNOWN"; val 406 drivers/power/supply/bq25890_charger.c val->intval = state.online; val 411 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 413 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 415 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; val 417 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 419 drivers/power/supply/bq25890_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 428 drivers/power/supply/bq25890_charger.c val->intval = ret * 50000; val 432 drivers/power/supply/bq25890_charger.c val->intval = bq25890_find_val(bq->init_data.ichg, TBL_ICHG); val 437 drivers/power/supply/bq25890_charger.c val->intval = 0; val 446 drivers/power/supply/bq25890_charger.c val->intval = 2304000 + ret * 20000; val 450 drivers/power/supply/bq25890_charger.c val->intval = bq25890_find_val(bq->init_data.vreg, TBL_VREG); val 454 drivers/power/supply/bq25890_charger.c val->intval = bq25890_find_val(bq->init_data.iterm, TBL_ITERM); val 463 drivers/power/supply/bq25890_charger.c val->intval = 2304000 + ret * 20000; val 732 drivers/power/supply/bq25890_charger.c static int bq25890_usb_notifier(struct notifier_block *nb, unsigned long val, val 738 drivers/power/supply/bq25890_charger.c bq->usb_event = val; val 878 drivers/power/supply/bq27xxx_battery.c static int poll_interval_param_set(const char *val, const struct kernel_param *kp) val 884 drivers/power/supply/bq27xxx_battery.c ret = param_set_uint(val, kp); val 1077 drivers/power/supply/bq27xxx_battery.c unsigned int val) val 1096 drivers/power/supply/bq27xxx_battery.c if (be16_to_cpup(prev) == val) { val 1097 drivers/power/supply/bq27xxx_battery.c dev_info(di->dev, "%s has %u\n", str, val); val 1113 drivers/power/supply/bq27xxx_battery.c "\n", str, be16_to_cpup(prev), val); val 1117 drivers/power/supply/bq27xxx_battery.c dev_info(di->dev, "update %s to %u\n", str, val); val 1119 drivers/power/supply/bq27xxx_battery.c *prev = cpu_to_be16(val); val 1644 drivers/power/supply/bq27xxx_battery.c union power_supply_propval *val) val 1662 drivers/power/supply/bq27xxx_battery.c val->intval = curr * BQ27XXX_CURRENT_CONSTANT / BQ27XXX_RS; val 1665 drivers/power/supply/bq27xxx_battery.c val->intval = (int)((s16)curr) * 1000; val 1672 drivers/power/supply/bq27xxx_battery.c union power_supply_propval *val) val 1694 drivers/power/supply/bq27xxx_battery.c val->intval = status; val 1700 drivers/power/supply/bq27xxx_battery.c union power_supply_propval *val) val 1724 drivers/power/supply/bq27xxx_battery.c val->intval = level; val 1734 drivers/power/supply/bq27xxx_battery.c union power_supply_propval *val) val 1744 drivers/power/supply/bq27xxx_battery.c val->intval = volt * 1000; val 1750 drivers/power/supply/bq27xxx_battery.c union power_supply_propval *val) val 1755 drivers/power/supply/bq27xxx_battery.c val->intval = value; val 1762 drivers/power/supply/bq27xxx_battery.c union power_supply_propval *val) val 1779 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_battery_status(di, val); val 1782 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_battery_voltage(di, val); val 1785 drivers/power/supply/bq27xxx_battery.c val->intval = di->cache.flags < 0 ? 0 : 1; val 1788 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_battery_current(di, val); val 1791 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.capacity, val); val 1794 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_battery_capacity_level(di, val); val 1797 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.temperature, val); val 1799 drivers/power/supply/bq27xxx_battery.c val->intval -= 2731; /* convert decidegree k to c */ val 1802 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.time_to_empty, val); val 1805 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.time_to_empty_avg, val); val 1808 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.time_to_full, val); val 1811 drivers/power/supply/bq27xxx_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 1814 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(bq27xxx_battery_read_nac(di), val); val 1817 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.charge_full, val); val 1820 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->charge_design_full, val); val 1830 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.cycle_count, val); val 1833 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.energy, val); val 1836 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.power_avg, val); val 1839 drivers/power/supply/bq27xxx_battery.c ret = bq27xxx_simple_value(di->cache.health, val); val 1842 drivers/power/supply/bq27xxx_battery.c val->strval = BQ27XXX_MANUFACTURER; val 37 drivers/power/supply/bq27xxx_battery_hdq.c u8 val; val 41 drivers/power/supply/bq27xxx_battery_hdq.c val = w1_read_8(sl->master); val 44 drivers/power/supply/bq27xxx_battery_hdq.c return val; val 88 drivers/power/supply/charger-manager.c union power_supply_propval val; val 105 drivers/power/supply/charger-manager.c &val); val 106 drivers/power/supply/charger-manager.c if (ret == 0 && val.intval) val 121 drivers/power/supply/charger-manager.c POWER_SUPPLY_PROP_PRESENT, &val); val 123 drivers/power/supply/charger-manager.c if (ret == 0 && val.intval) { val 144 drivers/power/supply/charger-manager.c union power_supply_propval val; val 159 drivers/power/supply/charger-manager.c &val); val 161 drivers/power/supply/charger-manager.c if (ret == 0 && val.intval) { val 180 drivers/power/supply/charger-manager.c union power_supply_propval val; val 189 drivers/power/supply/charger-manager.c POWER_SUPPLY_PROP_VOLTAGE_NOW, &val); val 194 drivers/power/supply/charger-manager.c *uV = val.intval; val 207 drivers/power/supply/charger-manager.c union power_supply_propval val; val 230 drivers/power/supply/charger-manager.c &val); val 237 drivers/power/supply/charger-manager.c if (val.intval == 0) { val 247 drivers/power/supply/charger-manager.c &val); val 254 drivers/power/supply/charger-manager.c if (val.intval == POWER_SUPPLY_STATUS_FULL || val 255 drivers/power/supply/charger-manager.c val.intval == POWER_SUPPLY_STATUS_DISCHARGING || val 256 drivers/power/supply/charger-manager.c val.intval == POWER_SUPPLY_STATUS_NOT_CHARGING) val 274 drivers/power/supply/charger-manager.c union power_supply_propval val; val 289 drivers/power/supply/charger-manager.c val.intval = 0; val 293 drivers/power/supply/charger-manager.c POWER_SUPPLY_PROP_CHARGE_FULL, &val); val 294 drivers/power/supply/charger-manager.c if (!ret && val.intval > desc->fullbatt_full_capacity) { val 311 drivers/power/supply/charger-manager.c val.intval = 0; val 314 drivers/power/supply/charger-manager.c POWER_SUPPLY_PROP_CAPACITY, &val); val 315 drivers/power/supply/charger-manager.c if (!ret && val.intval >= desc->fullbatt_soc) { val 884 drivers/power/supply/charger-manager.c union power_supply_propval *val) val 895 drivers/power/supply/charger-manager.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 897 drivers/power/supply/charger-manager.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 899 drivers/power/supply/charger-manager.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 903 drivers/power/supply/charger-manager.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 905 drivers/power/supply/charger-manager.c val->intval = POWER_SUPPLY_HEALTH_COLD; val 907 drivers/power/supply/charger-manager.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 911 drivers/power/supply/charger-manager.c val->intval = 1; val 913 drivers/power/supply/charger-manager.c val->intval = 0; val 916 drivers/power/supply/charger-manager.c ret = get_batt_uV(cm, &val->intval); val 925 drivers/power/supply/charger-manager.c POWER_SUPPLY_PROP_CURRENT_NOW, val); val 929 drivers/power/supply/charger-manager.c return cm_get_battery_temperature(cm, &val->intval); val 933 drivers/power/supply/charger-manager.c val->intval = 100; val 944 drivers/power/supply/charger-manager.c POWER_SUPPLY_PROP_CAPACITY, val); val 948 drivers/power/supply/charger-manager.c if (val->intval > 100) { val 949 drivers/power/supply/charger-manager.c val->intval = 100; val 952 drivers/power/supply/charger-manager.c if (val->intval < 0) val 953 drivers/power/supply/charger-manager.c val->intval = 0; val 972 drivers/power/supply/charger-manager.c val->intval = 100; val 979 drivers/power/supply/charger-manager.c val->intval = 1; val 981 drivers/power/supply/charger-manager.c val->intval = 0; val 985 drivers/power/supply/charger-manager.c val->intval = 1; val 987 drivers/power/supply/charger-manager.c val->intval = 0; val 1001 drivers/power/supply/charger-manager.c val); val 1003 drivers/power/supply/charger-manager.c val->intval = 1; val 1007 drivers/power/supply/charger-manager.c val->intval = (val->intval > 0) ? val 1008 drivers/power/supply/charger-manager.c val->intval : 1; val 1011 drivers/power/supply/charger-manager.c val->intval = 0; val 1428 drivers/power/supply/charger-manager.c union power_supply_propval val; val 1433 drivers/power/supply/charger-manager.c POWER_SUPPLY_PROP_TEMP, &val); val 1622 drivers/power/supply/charger-manager.c union power_supply_propval val; val 1741 drivers/power/supply/charger-manager.c POWER_SUPPLY_PROP_CHARGE_NOW, &val)) { val 1748 drivers/power/supply/charger-manager.c &val)) { val 93 drivers/power/supply/collie_battery.c union power_supply_propval *val) val 105 drivers/power/supply/collie_battery.c val->intval = bat->status; val 108 drivers/power/supply/collie_battery.c val->intval = bat->technology; val 111 drivers/power/supply/collie_battery.c val->intval = collie_read_bat(bat); val 115 drivers/power/supply/collie_battery.c val->intval = bat->bat_max; val 117 drivers/power/supply/collie_battery.c val->intval = bat->full_chrg; val 120 drivers/power/supply/collie_battery.c val->intval = bat->bat_max; val 123 drivers/power/supply/collie_battery.c val->intval = bat->bat_min; val 126 drivers/power/supply/collie_battery.c val->intval = collie_read_temp(bat); val 129 drivers/power/supply/collie_battery.c val->intval = bat->is_present ? bat->is_present(bat) : 1; val 433 drivers/power/supply/cpcap-battery.c union power_supply_propval *val) val 452 drivers/power/supply/cpcap-battery.c val->intval = 1; val 454 drivers/power/supply/cpcap-battery.c val->intval = 0; val 458 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_STATUS_FULL; val 462 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 464 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 467 drivers/power/supply/cpcap-battery.c val->intval = ddata->config.info.technology; val 470 drivers/power/supply/cpcap-battery.c val->intval = cpcap_battery_get_voltage(ddata); val 473 drivers/power/supply/cpcap-battery.c val->intval = ddata->config.info.voltage_max_design; val 476 drivers/power/supply/cpcap-battery.c val->intval = ddata->config.info.voltage_min_design; val 481 drivers/power/supply/cpcap-battery.c val->intval = cpcap_battery_cc_get_avg_current(ddata); val 485 drivers/power/supply/cpcap-battery.c val->intval = cpcap_battery_cc_to_ua(ddata, sample, val 490 drivers/power/supply/cpcap-battery.c val->intval = latest->current_ua; val 493 drivers/power/supply/cpcap-battery.c val->intval = latest->counter_uah; val 497 drivers/power/supply/cpcap-battery.c val->intval = div64_s64(tmp, 100); val 504 drivers/power/supply/cpcap-battery.c val->intval = div64_s64(tmp, 100); val 511 drivers/power/supply/cpcap-battery.c val->intval = div64_s64(tmp, 100); val 515 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_FULL; val 517 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_HIGH; val 519 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; val 521 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_LOW; val 523 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; val 525 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN; val 528 drivers/power/supply/cpcap-battery.c val->intval = ddata->config.info.charge_full_design; val 531 drivers/power/supply/cpcap-battery.c val->intval = POWER_SUPPLY_SCOPE_SYSTEM; val 534 drivers/power/supply/cpcap-battery.c val->intval = latest->temperature; val 59 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_TR(val) (((val) & 0x3) << 10) val 70 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_VCHRG(val) (((val) & 0xf) << 4) val 93 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_ICHRG(val) (((val) & 0xf) << 0) val 219 drivers/power/supply/cpcap-charger.c union power_supply_propval *val) val 225 drivers/power/supply/cpcap-charger.c val->intval = ddata->status; val 229 drivers/power/supply/cpcap-charger.c val->intval = cpcap_charger_get_charge_voltage(ddata) * val 232 drivers/power/supply/cpcap-charger.c val->intval = 0; val 236 drivers/power/supply/cpcap-charger.c val->intval = cpcap_charger_get_charge_current(ddata) * val 239 drivers/power/supply/cpcap-charger.c val->intval = 0; val 242 drivers/power/supply/cpcap-charger.c val->intval = ddata->status == POWER_SUPPLY_STATUS_CHARGING; val 409 drivers/power/supply/cpcap-charger.c int val, error; val 411 drivers/power/supply/cpcap-charger.c error = regmap_read(ddata->reg, CPCAP_REG_INTS1, &val); val 415 drivers/power/supply/cpcap-charger.c s->chrg_det = val & BIT(13); val 416 drivers/power/supply/cpcap-charger.c s->rvrs_chrg = val & BIT(12); val 417 drivers/power/supply/cpcap-charger.c s->vbusov = val & BIT(11); val 419 drivers/power/supply/cpcap-charger.c error = regmap_read(ddata->reg, CPCAP_REG_INTS2, &val); val 423 drivers/power/supply/cpcap-charger.c s->chrg_se1b = val & BIT(13); val 424 drivers/power/supply/cpcap-charger.c s->rvrs_mode = val & BIT(6); val 425 drivers/power/supply/cpcap-charger.c s->chrgcurr1 = val & BIT(4); val 426 drivers/power/supply/cpcap-charger.c s->vbusvld = val & BIT(3); val 428 drivers/power/supply/cpcap-charger.c error = regmap_read(ddata->reg, CPCAP_REG_INTS4, &val); val 432 drivers/power/supply/cpcap-charger.c s->battdetb = val & BIT(6); val 366 drivers/power/supply/cros_usbpd-charger.c union power_supply_propval *val) val 409 drivers/power/supply/cros_usbpd-charger.c val->intval = port->psy_online; val 412 drivers/power/supply/cros_usbpd-charger.c val->intval = port->psy_status; val 415 drivers/power/supply/cros_usbpd-charger.c val->intval = port->psy_current_max * 1000; val 418 drivers/power/supply/cros_usbpd-charger.c val->intval = port->psy_voltage_max_design * 1000; val 421 drivers/power/supply/cros_usbpd-charger.c val->intval = port->psy_voltage_now * 1000; val 424 drivers/power/supply/cros_usbpd-charger.c val->intval = port->psy_usb_type; val 428 drivers/power/supply/cros_usbpd-charger.c val->intval = -1; val 430 drivers/power/supply/cros_usbpd-charger.c val->intval = input_current_limit * 1000; val 434 drivers/power/supply/cros_usbpd-charger.c val->intval = -1; val 436 drivers/power/supply/cros_usbpd-charger.c val->intval = input_voltage_limit * 1000; val 439 drivers/power/supply/cros_usbpd-charger.c val->strval = port->model_name; val 442 drivers/power/supply/cros_usbpd-charger.c val->strval = port->manufacturer; val 453 drivers/power/supply/cros_usbpd-charger.c const union power_supply_propval *val) val 462 drivers/power/supply/cros_usbpd-charger.c if (val->intval >= U16_MAX * 1000) val 465 drivers/power/supply/cros_usbpd-charger.c if (val->intval < 0) val 468 drivers/power/supply/cros_usbpd-charger.c intval = val->intval / 1000; val 217 drivers/power/supply/da9030_battery.c uint8_t val; val 219 drivers/power/supply/da9030_battery.c da903x_read(charger->master, DA9030_CHARGE_CONTROL, &val); val 220 drivers/power/supply/da9030_battery.c charger->is_on = (val & DA9030_CHRG_CHARGER_ENABLE) ? 1 : 0; val 221 drivers/power/supply/da9030_battery.c charger->mA = ((val >> 3) & 0xf) * 100; val 222 drivers/power/supply/da9030_battery.c charger->mV = (val & 0x7) * 50 + 4000; val 232 drivers/power/supply/da9030_battery.c uint8_t val; val 235 drivers/power/supply/da9030_battery.c val = DA9030_CHRG_CHARGER_ENABLE; val 236 drivers/power/supply/da9030_battery.c val |= (charger->charge_milliamp / 100) << 3; val 237 drivers/power/supply/da9030_battery.c val |= (charger->charge_millivolt - 4000) / 50; val 240 drivers/power/supply/da9030_battery.c val = 0; val 244 drivers/power/supply/da9030_battery.c da903x_write(charger->master, DA9030_CHARGE_CONTROL, val); val 315 drivers/power/supply/da9030_battery.c union power_supply_propval *val) val 319 drivers/power/supply/da9030_battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 321 drivers/power/supply/da9030_battery.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 323 drivers/power/supply/da9030_battery.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 328 drivers/power/supply/da9030_battery.c union power_supply_propval *val) val 331 drivers/power/supply/da9030_battery.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 333 drivers/power/supply/da9030_battery.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 335 drivers/power/supply/da9030_battery.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 340 drivers/power/supply/da9030_battery.c union power_supply_propval *val) val 346 drivers/power/supply/da9030_battery.c da9030_battery_check_status(charger, val); val 349 drivers/power/supply/da9030_battery.c da9030_battery_check_health(charger, val); val 352 drivers/power/supply/da9030_battery.c val->intval = charger->battery_info->technology; val 355 drivers/power/supply/da9030_battery.c val->intval = charger->battery_info->voltage_max_design; val 358 drivers/power/supply/da9030_battery.c val->intval = charger->battery_info->voltage_min_design; val 361 drivers/power/supply/da9030_battery.c val->intval = da9030_reg_to_mV(charger->adc.vbat_res) * 1000; val 364 drivers/power/supply/da9030_battery.c val->intval = val 368 drivers/power/supply/da9030_battery.c val->strval = charger->battery_info->name; val 494 drivers/power/supply/da9052-battery.c union power_supply_propval *val) val 509 drivers/power/supply/da9052-battery.c ret = da9052_bat_check_status(bat, &val->intval); val 512 drivers/power/supply/da9052-battery.c val->intval = val 516 drivers/power/supply/da9052-battery.c ret = da9052_bat_check_presence(bat, &val->intval); val 519 drivers/power/supply/da9052-battery.c ret = da9052_bat_check_health(bat, &val->intval); val 522 drivers/power/supply/da9052-battery.c val->intval = DA9052_BAT_CUTOFF_VOLT * 1000; val 525 drivers/power/supply/da9052-battery.c ret = da9052_bat_read_volt(bat, &val->intval); val 528 drivers/power/supply/da9052-battery.c ret = da9052_read_chg_current(bat, &val->intval); val 531 drivers/power/supply/da9052-battery.c ret = da9052_bat_read_capacity(bat, &val->intval); val 534 drivers/power/supply/da9052-battery.c val->intval = da9052_adc_read_temp(bat->da9052); val 535 drivers/power/supply/da9052-battery.c ret = val->intval; val 538 drivers/power/supply/da9052-battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 46 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 48 drivers/power/supply/da9150-charger.c val->intval = (psy == charger->supply_online) ? 1 : 0; val 55 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 65 drivers/power/supply/da9150-charger.c val->intval = v_val * 1000; val 71 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 81 drivers/power/supply/da9150-charger.c val->intval = i_val * 1000; val 87 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 97 drivers/power/supply/da9150-charger.c val->intval = t_val / 100; val 111 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 118 drivers/power/supply/da9150-charger.c ret = da9150_charger_supply_online(charger, psy, val); val 121 drivers/power/supply/da9150-charger.c ret = da9150_charger_vbus_voltage_now(charger, val); val 124 drivers/power/supply/da9150-charger.c ret = da9150_charger_ibus_current_avg(charger, val); val 127 drivers/power/supply/da9150-charger.c ret = da9150_charger_tjunc_temp(charger, val); val 139 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 148 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 161 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 168 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 171 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_STATUS_FULL; val 174 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 182 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 191 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_HEALTH_COLD; val 194 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 204 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 207 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 210 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 218 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 225 drivers/power/supply/da9150-charger.c val->intval = 0; val 227 drivers/power/supply/da9150-charger.c val->intval = 1; val 233 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 241 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; val 246 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 249 drivers/power/supply/da9150-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; val 257 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 264 drivers/power/supply/da9150-charger.c val->intval = ((reg & DA9150_CHG_VFAULT_MASK) * 50000) + 2500000; val 270 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 279 drivers/power/supply/da9150-charger.c val->intval = v_val * 1000; val 285 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 292 drivers/power/supply/da9150-charger.c val->intval = reg * 25000; val 298 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 305 drivers/power/supply/da9150-charger.c val->intval = ((reg & DA9150_CHG_VBAT_MASK) * 25000) + 3650000; val 323 drivers/power/supply/da9150-charger.c union power_supply_propval *val) val 330 drivers/power/supply/da9150-charger.c ret = da9150_charger_battery_status(charger, val); val 333 drivers/power/supply/da9150-charger.c ret = da9150_charger_supply_online(charger, psy, val); val 336 drivers/power/supply/da9150-charger.c ret = da9150_charger_battery_health(charger, val); val 339 drivers/power/supply/da9150-charger.c ret = da9150_charger_battery_present(charger, val); val 342 drivers/power/supply/da9150-charger.c ret = da9150_charger_battery_charge_type(charger, val); val 345 drivers/power/supply/da9150-charger.c ret = da9150_charger_battery_voltage_min(charger, val); val 348 drivers/power/supply/da9150-charger.c ret = da9150_charger_battery_voltage_now(charger, val); val 351 drivers/power/supply/da9150-charger.c ret = da9150_charger_battery_current_max(charger, val); val 354 drivers/power/supply/da9150-charger.c ret = da9150_charger_battery_voltage_max(charger, val); val 446 drivers/power/supply/da9150-charger.c static int da9150_charger_otg_ncb(struct notifier_block *nb, unsigned long val, val 452 drivers/power/supply/da9150-charger.c dev_dbg(charger->dev, "DA9150 OTG notify %lu\n", val); val 454 drivers/power/supply/da9150-charger.c charger->usb_event = val; val 107 drivers/power/supply/da9150-fg.c u32 val) val 118 drivers/power/supply/da9150-fg.c buf[i] = (val >> (i * DA9150_QIF_BYTE_SIZE)) & val 165 drivers/power/supply/da9150-fg.c u32 val; val 168 drivers/power/supply/da9150-fg.c val = da9150_fg_read_attr(fg, code, size); val 171 drivers/power/supply/da9150-fg.c return val; val 176 drivers/power/supply/da9150-fg.c u32 val) val 202 drivers/power/supply/da9150-fg.c da9150_fg_write_attr(fg, code, size, val); val 224 drivers/power/supply/da9150-fg.c union power_supply_propval *val) val 226 drivers/power/supply/da9150-fg.c val->intval = da9150_fg_read_attr_sync(fg, DA9150_QIF_SOC_PCT, val 229 drivers/power/supply/da9150-fg.c if (val->intval > 100) val 230 drivers/power/supply/da9150-fg.c val->intval = 100; val 236 drivers/power/supply/da9150-fg.c union power_supply_propval *val) val 255 drivers/power/supply/da9150-fg.c val->intval = (int) res; val 261 drivers/power/supply/da9150-fg.c union power_supply_propval *val) val 265 drivers/power/supply/da9150-fg.c val->intval = da9150_fg_read_attr_sync(fg, DA9150_QIF_UAVG, val 268 drivers/power/supply/da9150-fg.c res = (u64) (val->intval * 186ULL); val 270 drivers/power/supply/da9150-fg.c val->intval = (int) res; val 276 drivers/power/supply/da9150-fg.c union power_supply_propval *val) val 278 drivers/power/supply/da9150-fg.c val->intval = da9150_fg_read_attr_sync(fg, DA9150_QIF_FCC_MAH, val 281 drivers/power/supply/da9150-fg.c val->intval = val->intval * 1000; val 291 drivers/power/supply/da9150-fg.c union power_supply_propval *val) val 293 drivers/power/supply/da9150-fg.c val->intval = da9150_fg_read_attr_sync(fg, DA9150_QIF_NTCAVG, val 296 drivers/power/supply/da9150-fg.c val->intval = (val->intval * 10) / 1048576; val 311 drivers/power/supply/da9150-fg.c union power_supply_propval *val) val 318 drivers/power/supply/da9150-fg.c ret = da9150_fg_capacity(fg, val); val 321 drivers/power/supply/da9150-fg.c ret = da9150_fg_current_avg(fg, val); val 324 drivers/power/supply/da9150-fg.c ret = da9150_fg_voltage_avg(fg, val); val 327 drivers/power/supply/da9150-fg.c ret = da9150_fg_charge_full(fg, val); val 330 drivers/power/supply/da9150-fg.c ret = da9150_fg_temp(fg, val); val 343 drivers/power/supply/da9150-fg.c union power_supply_propval val; val 345 drivers/power/supply/da9150-fg.c da9150_fg_capacity(fg, &val); val 346 drivers/power/supply/da9150-fg.c if (val.intval != fg->soc) { val 347 drivers/power/supply/da9150-fg.c fg->soc = val.intval; val 546 drivers/power/supply/ds2760_battery.c union power_supply_propval *val) val 552 drivers/power/supply/ds2760_battery.c val->intval = di->charge_status; val 562 drivers/power/supply/ds2760_battery.c val->intval = di->voltage_uV; val 565 drivers/power/supply/ds2760_battery.c val->intval = di->current_uA; val 568 drivers/power/supply/ds2760_battery.c val->intval = di->rated_capacity; val 571 drivers/power/supply/ds2760_battery.c val->intval = di->full_active_uAh; val 574 drivers/power/supply/ds2760_battery.c val->intval = di->empty_uAh; val 577 drivers/power/supply/ds2760_battery.c val->intval = di->accum_current_uAh; val 580 drivers/power/supply/ds2760_battery.c val->intval = di->temp_C; val 583 drivers/power/supply/ds2760_battery.c val->intval = di->life_sec; val 586 drivers/power/supply/ds2760_battery.c val->intval = di->rem_capacity; val 597 drivers/power/supply/ds2760_battery.c const union power_supply_propval *val) val 604 drivers/power/supply/ds2760_battery.c ds2760_battery_write_active_full(di, val->intval / 1000L); val 609 drivers/power/supply/ds2760_battery.c ds2760_battery_set_current_accum(di, val->intval); val 61 drivers/power/supply/ds2780_battery.c static inline int ds2780_read8(struct ds2780_device_info *dev_info, u8 *val, val 64 drivers/power/supply/ds2780_battery.c return ds2780_battery_io(dev_info, val, addr, sizeof(u8), 0); val 67 drivers/power/supply/ds2780_battery.c static int ds2780_read16(struct ds2780_device_info *dev_info, s16 *val, val 77 drivers/power/supply/ds2780_battery.c *val = (raw[0] << 8) | raw[1]; val 83 drivers/power/supply/ds2780_battery.c u8 *val, int addr, size_t count) val 85 drivers/power/supply/ds2780_battery.c return ds2780_battery_io(dev_info, val, addr, count, 0); val 88 drivers/power/supply/ds2780_battery.c static inline int ds2780_write(struct ds2780_device_info *dev_info, u8 *val, val 91 drivers/power/supply/ds2780_battery.c return ds2780_battery_io(dev_info, val, addr, count, 1); val 377 drivers/power/supply/ds2780_battery.c union power_supply_propval *val) val 384 drivers/power/supply/ds2780_battery.c ret = ds2780_get_voltage(dev_info, &val->intval); val 388 drivers/power/supply/ds2780_battery.c ret = ds2780_get_temperature(dev_info, &val->intval); val 392 drivers/power/supply/ds2780_battery.c val->strval = model; val 396 drivers/power/supply/ds2780_battery.c val->strval = manufacturer; val 400 drivers/power/supply/ds2780_battery.c ret = ds2780_get_current(dev_info, CURRENT_NOW, &val->intval); val 404 drivers/power/supply/ds2780_battery.c ret = ds2780_get_current(dev_info, CURRENT_AVG, &val->intval); val 408 drivers/power/supply/ds2780_battery.c ret = ds2780_get_status(dev_info, &val->intval); val 412 drivers/power/supply/ds2780_battery.c ret = ds2780_get_capacity(dev_info, &val->intval); val 416 drivers/power/supply/ds2780_battery.c ret = ds2780_get_accumulated_current(dev_info, &val->intval); val 420 drivers/power/supply/ds2780_battery.c ret = ds2780_get_charge_now(dev_info, &val->intval); val 65 drivers/power/supply/ds2781_battery.c static inline int ds2781_read8(struct ds2781_device_info *dev_info, u8 *val, val 68 drivers/power/supply/ds2781_battery.c return ds2781_battery_io(dev_info, val, addr, sizeof(u8), 0); val 71 drivers/power/supply/ds2781_battery.c static int ds2781_read16(struct ds2781_device_info *dev_info, s16 *val, val 81 drivers/power/supply/ds2781_battery.c *val = (raw[0] << 8) | raw[1]; val 87 drivers/power/supply/ds2781_battery.c u8 *val, int addr, size_t count) val 89 drivers/power/supply/ds2781_battery.c return ds2781_battery_io(dev_info, val, addr, count, 0); val 92 drivers/power/supply/ds2781_battery.c static inline int ds2781_write(struct ds2781_device_info *dev_info, u8 *val, val 95 drivers/power/supply/ds2781_battery.c return ds2781_battery_io(dev_info, val, addr, count, 1); val 163 drivers/power/supply/ds2781_battery.c char val[2]; val 166 drivers/power/supply/ds2781_battery.c ret = w1_ds2781_read(dev_info, val, DS2781_VOLT_MSB, 2 * sizeof(u8)); val 178 drivers/power/supply/ds2781_battery.c voltage_raw = (val[0] << 3) | val 179 drivers/power/supply/ds2781_battery.c (val[1] >> 5); val 192 drivers/power/supply/ds2781_battery.c char val[2]; val 195 drivers/power/supply/ds2781_battery.c ret = w1_ds2781_read(dev_info, val, DS2781_TEMP_MSB, 2 * sizeof(u8)); val 208 drivers/power/supply/ds2781_battery.c temp_raw = ((val[0]) << 3) | val 209 drivers/power/supply/ds2781_battery.c (val[1] >> 5); val 379 drivers/power/supply/ds2781_battery.c union power_supply_propval *val) val 386 drivers/power/supply/ds2781_battery.c ret = ds2781_get_voltage(dev_info, &val->intval); val 390 drivers/power/supply/ds2781_battery.c ret = ds2781_get_temperature(dev_info, &val->intval); val 394 drivers/power/supply/ds2781_battery.c val->strval = model; val 398 drivers/power/supply/ds2781_battery.c val->strval = manufacturer; val 402 drivers/power/supply/ds2781_battery.c ret = ds2781_get_current(dev_info, CURRENT_NOW, &val->intval); val 406 drivers/power/supply/ds2781_battery.c ret = ds2781_get_current(dev_info, CURRENT_AVG, &val->intval); val 410 drivers/power/supply/ds2781_battery.c ret = ds2781_get_status(dev_info, &val->intval); val 414 drivers/power/supply/ds2781_battery.c ret = ds2781_get_capacity(dev_info, &val->intval); val 418 drivers/power/supply/ds2781_battery.c ret = ds2781_get_accumulated_current(dev_info, &val->intval); val 422 drivers/power/supply/ds2781_battery.c ret = ds2781_get_charge_now(dev_info, &val->intval); val 69 drivers/power/supply/ds2782_battery.c static inline int ds278x_read_reg(struct ds278x_info *info, int reg, u8 *val) val 79 drivers/power/supply/ds2782_battery.c *val = ret; val 84 drivers/power/supply/ds2782_battery.c s16 *val) val 94 drivers/power/supply/ds2782_battery.c *val = swab16(ret); val 244 drivers/power/supply/ds2782_battery.c union power_supply_propval *val) val 251 drivers/power/supply/ds2782_battery.c ret = ds278x_get_status(info, &val->intval); val 255 drivers/power/supply/ds2782_battery.c ret = info->ops->get_battery_capacity(info, &val->intval); val 259 drivers/power/supply/ds2782_battery.c ret = info->ops->get_battery_voltage(info, &val->intval); val 263 drivers/power/supply/ds2782_battery.c ret = info->ops->get_battery_current(info, &val->intval); val 267 drivers/power/supply/ds2782_battery.c ret = ds278x_get_temp(info, &val->intval); val 145 drivers/power/supply/generic-adc-battery.c enum power_supply_property psp, union power_supply_propval *val) val 163 drivers/power/supply/generic-adc-battery.c val->intval = gab_get_status(adc_bat); val 166 drivers/power/supply/generic-adc-battery.c val->intval = 0; val 169 drivers/power/supply/generic-adc-battery.c val->intval = pdata->cal_charge(result); val 177 drivers/power/supply/generic-adc-battery.c val->intval = result; val 180 drivers/power/supply/generic-adc-battery.c val->intval = bat_info->technology; val 183 drivers/power/supply/generic-adc-battery.c val->intval = bat_info->voltage_min_design; val 186 drivers/power/supply/generic-adc-battery.c val->intval = bat_info->voltage_max_design; val 189 drivers/power/supply/generic-adc-battery.c val->intval = bat_info->charge_full_design; val 192 drivers/power/supply/generic-adc-battery.c val->strval = bat_info->name; val 64 drivers/power/supply/goldfish_battery.c union power_supply_propval *val) val 71 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_AC_ONLINE); val 74 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_VOLTAGE_MAX); val 77 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_CURRENT_MAX); val 88 drivers/power/supply/goldfish_battery.c union power_supply_propval *val) val 95 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_STATUS); val 98 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_HEALTH); val 101 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_PRESENT); val 104 drivers/power/supply/goldfish_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 107 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_CAPACITY); val 110 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_VOLTAGE); val 113 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_TEMP); val 116 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, val 120 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_CURRENT_NOW); val 123 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_CURRENT_AVG); val 126 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, val 130 drivers/power/supply/goldfish_battery.c val->intval = GOLDFISH_BATTERY_READ(data, BATTERY_CYCLE_COUNT); val 47 drivers/power/supply/gpio-charger.c enum power_supply_property psp, union power_supply_propval *val) val 53 drivers/power/supply/gpio-charger.c val->intval = gpiod_get_value_cansleep(gpio_charger->gpiod); val 57 drivers/power/supply/gpio-charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 59 drivers/power/supply/gpio-charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 26 drivers/power/supply/ingenic-battery.c union power_supply_propval *val) val 34 drivers/power/supply/ingenic-battery.c ret = iio_read_channel_processed(bat->channel, &val->intval); val 35 drivers/power/supply/ingenic-battery.c val->intval *= 1000; val 36 drivers/power/supply/ingenic-battery.c if (val->intval < info->voltage_min_design_uv) val 37 drivers/power/supply/ingenic-battery.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 38 drivers/power/supply/ingenic-battery.c else if (val->intval > info->voltage_max_design_uv) val 39 drivers/power/supply/ingenic-battery.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 41 drivers/power/supply/ingenic-battery.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 44 drivers/power/supply/ingenic-battery.c ret = iio_read_channel_processed(bat->channel, &val->intval); val 45 drivers/power/supply/ingenic-battery.c val->intval *= 1000; val 48 drivers/power/supply/ingenic-battery.c val->intval = info->voltage_min_design_uv; val 51 drivers/power/supply/ingenic-battery.c val->intval = info->voltage_max_design_uv; val 130 drivers/power/supply/ipaq_micro_battery.c union power_supply_propval *val) val 138 drivers/power/supply/ipaq_micro_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_NiCd; val 141 drivers/power/supply/ipaq_micro_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_NiMH; val 144 drivers/power/supply/ipaq_micro_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 147 drivers/power/supply/ipaq_micro_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LIPO; val 150 drivers/power/supply/ipaq_micro_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_UNKNOWN; val 155 drivers/power/supply/ipaq_micro_battery.c val->intval = get_status(b); val 158 drivers/power/supply/ipaq_micro_battery.c val->intval = 4700000; val 161 drivers/power/supply/ipaq_micro_battery.c val->intval = get_capacity(b); val 164 drivers/power/supply/ipaq_micro_battery.c val->intval = mb->temperature; val 167 drivers/power/supply/ipaq_micro_battery.c val->intval = mb->voltage; val 178 drivers/power/supply/ipaq_micro_battery.c union power_supply_propval *val) val 184 drivers/power/supply/ipaq_micro_battery.c val->intval = mb->ac; val 66 drivers/power/supply/isp1704_charger.c static inline int isp1704_write(struct isp1704_charger *isp, u32 reg, u32 val) val 68 drivers/power/supply/isp1704_charger.c return usb_phy_io_write(isp->phy, val, reg); val 294 drivers/power/supply/isp1704_charger.c unsigned long val, void *v) val 306 drivers/power/supply/isp1704_charger.c union power_supply_propval *val) val 312 drivers/power/supply/isp1704_charger.c val->intval = isp->present; val 315 drivers/power/supply/isp1704_charger.c val->intval = isp->online; val 318 drivers/power/supply/isp1704_charger.c val->intval = isp->current_max; val 321 drivers/power/supply/isp1704_charger.c val->strval = isp->model; val 324 drivers/power/supply/isp1704_charger.c val->strval = "NXP"; val 39 drivers/power/supply/lego_ev3_battery.c union power_supply_propval *val) val 46 drivers/power/supply/lego_ev3_battery.c val->intval = batt->technology; val 50 drivers/power/supply/lego_ev3_battery.c ret = iio_read_channel_processed(batt->iio_v, &val->intval); val 54 drivers/power/supply/lego_ev3_battery.c val->intval *= 2000; val 55 drivers/power/supply/lego_ev3_battery.c val->intval += 50000; val 64 drivers/power/supply/lego_ev3_battery.c val->intval += val2; val 67 drivers/power/supply/lego_ev3_battery.c val->intval = batt->v_max; val 70 drivers/power/supply/lego_ev3_battery.c val->intval = batt->v_min; val 74 drivers/power/supply/lego_ev3_battery.c ret = iio_read_channel_processed(batt->iio_i, &val->intval); val 78 drivers/power/supply/lego_ev3_battery.c val->intval *= 20000; val 79 drivers/power/supply/lego_ev3_battery.c val->intval /= 15; val 82 drivers/power/supply/lego_ev3_battery.c val->intval = POWER_SUPPLY_SCOPE_SYSTEM; val 93 drivers/power/supply/lego_ev3_battery.c const union power_supply_propval *val) val 109 drivers/power/supply/lego_ev3_battery.c switch (val->intval) { val 140 drivers/power/supply/lp8727_charger.c u8 val; val 149 drivers/power/supply/lp8727_charger.c val = LP8727_ID200_EN | LP8727_ADC_EN | LP8727_CP_EN; val 150 drivers/power/supply/lp8727_charger.c ret = lp8727_write_byte(pchg, LP8727_CTRL1, val); val 154 drivers/power/supply/lp8727_charger.c val = LP8727_INT_EN | LP8727_CHGDET_EN; val 155 drivers/power/supply/lp8727_charger.c return lp8727_write_byte(pchg, LP8727_CTRL2, val); val 160 drivers/power/supply/lp8727_charger.c u8 val; val 162 drivers/power/supply/lp8727_charger.c lp8727_read_byte(pchg, LP8727_STATUS1, &val); val 163 drivers/power/supply/lp8727_charger.c return val & LP8727_DCPORT; val 168 drivers/power/supply/lp8727_charger.c u8 val; val 170 drivers/power/supply/lp8727_charger.c lp8727_read_byte(pchg, LP8727_STATUS1, &val); val 171 drivers/power/supply/lp8727_charger.c return val & LP8727_CHPORT; val 215 drivers/power/supply/lp8727_charger.c u8 val; val 217 drivers/power/supply/lp8727_charger.c lp8727_read_byte(pchg, LP8727_CTRL2, &val); val 218 drivers/power/supply/lp8727_charger.c val |= LP8727_CHGDET_EN; val 219 drivers/power/supply/lp8727_charger.c lp8727_write_byte(pchg, LP8727_CTRL2, val); val 308 drivers/power/supply/lp8727_charger.c union power_supply_propval *val) val 315 drivers/power/supply/lp8727_charger.c val->intval = lp8727_is_charger_attached(psy->desc->name, pchg->devid); val 334 drivers/power/supply/lp8727_charger.c union power_supply_propval *val) val 344 drivers/power/supply/lp8727_charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 350 drivers/power/supply/lp8727_charger.c val->intval = (read & LP8727_CHGSTAT) == LP8727_STAT_EOC ? val 358 drivers/power/supply/lp8727_charger.c val->intval = lp8727_is_high_temperature(temp) ? val 367 drivers/power/supply/lp8727_charger.c val->intval = pdata->get_batt_present(); val 374 drivers/power/supply/lp8727_charger.c val->intval = pdata->get_batt_level(); val 381 drivers/power/supply/lp8727_charger.c val->intval = pdata->get_batt_capacity(); val 388 drivers/power/supply/lp8727_charger.c val->intval = pdata->get_batt_temp(); val 402 drivers/power/supply/lp8727_charger.c u8 val; val 412 drivers/power/supply/lp8727_charger.c val = (ichg << LP8727_ICHG_SHIFT) | eoc_level; val 413 drivers/power/supply/lp8727_charger.c lp8727_write_byte(pchg, LP8727_CHGCTRL2, val); val 145 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 152 drivers/power/supply/lp8788-charger.c val->intval = lp8788_is_charger_detected(pchg); val 156 drivers/power/supply/lp8788-charger.c val->intval = LP8788_ISEL_STEP * val 167 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 180 drivers/power/supply/lp8788-charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 186 drivers/power/supply/lp8788-charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 189 drivers/power/supply/lp8788-charger.c val->intval = POWER_SUPPLY_STATUS_FULL; val 192 drivers/power/supply/lp8788-charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 200 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 210 drivers/power/supply/lp8788-charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 212 drivers/power/supply/lp8788-charger.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 214 drivers/power/supply/lp8788-charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 220 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 229 drivers/power/supply/lp8788-charger.c val->intval = !(data & LP8788_NO_BATT_M); val 244 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 246 drivers/power/supply/lp8788-charger.c return lp8788_get_vbatt_adc(pchg, &val->intval); val 250 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 274 drivers/power/supply/lp8788-charger.c val->intval = LP8788_MAX_BATT_CAPACITY; val 280 drivers/power/supply/lp8788-charger.c val->intval = (vbatt * LP8788_MAX_BATT_CAPACITY) / max_vbatt; val 281 drivers/power/supply/lp8788-charger.c val->intval = min(val->intval, LP8788_MAX_BATT_CAPACITY); val 288 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 302 drivers/power/supply/lp8788-charger.c val->intval = result * 10; val 308 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 314 drivers/power/supply/lp8788-charger.c val->intval = LP8788_ISEL_STEP * val 321 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 327 drivers/power/supply/lp8788-charger.c val->intval = LP8788_VTERM_MIN + LP8788_VTERM_STEP * read; val 334 drivers/power/supply/lp8788-charger.c union power_supply_propval *val) val 340 drivers/power/supply/lp8788-charger.c return lp8788_get_battery_status(pchg, val); val 342 drivers/power/supply/lp8788-charger.c return lp8788_get_battery_health(pchg, val); val 344 drivers/power/supply/lp8788-charger.c return lp8788_get_battery_present(pchg, val); val 346 drivers/power/supply/lp8788-charger.c return lp8788_get_battery_voltage(pchg, val); val 348 drivers/power/supply/lp8788-charger.c return lp8788_get_battery_capacity(pchg, val); val 350 drivers/power/supply/lp8788-charger.c return lp8788_get_battery_temperature(pchg, val); val 352 drivers/power/supply/lp8788-charger.c return lp8788_get_battery_charging_current(pchg, val); val 354 drivers/power/supply/lp8788-charger.c return lp8788_get_charging_termination_voltage(pchg, val); val 384 drivers/power/supply/lp8788-charger.c ret = lp8788_write_byte(lp, param->addr, param->val); val 629 drivers/power/supply/lp8788-charger.c u8 val; val 631 drivers/power/supply/lp8788-charger.c lp8788_read_byte(pchg->lp, LP8788_CHG_EOC, &val); val 632 drivers/power/supply/lp8788-charger.c val = (val & LP8788_CHG_EOC_TIME_M) >> LP8788_CHG_EOC_TIME_S; val 635 drivers/power/supply/lp8788-charger.c stime[val]); val 649 drivers/power/supply/lp8788-charger.c u8 val; val 652 drivers/power/supply/lp8788-charger.c lp8788_read_byte(pchg->lp, LP8788_CHG_EOC, &val); val 654 drivers/power/supply/lp8788-charger.c mode = val & LP8788_CHG_EOC_MODE_M; val 655 drivers/power/supply/lp8788-charger.c val = (val & LP8788_CHG_EOC_LEVEL_M) >> LP8788_CHG_EOC_LEVEL_S; val 656 drivers/power/supply/lp8788-charger.c level = mode ? abs_level[val] : relative_level[val]; val 42 drivers/power/supply/lt3651-charger.c enum power_supply_property psp, union power_supply_propval *val) val 49 drivers/power/supply/lt3651-charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 53 drivers/power/supply/lt3651-charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 55 drivers/power/supply/lt3651-charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 58 drivers/power/supply/lt3651-charger.c val->intval = gpiod_get_value(lt3651_charger->acpr_gpio); val 62 drivers/power/supply/lt3651-charger.c val->intval = POWER_SUPPLY_HEALTH_UNKNOWN; val 66 drivers/power/supply/lt3651-charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 74 drivers/power/supply/lt3651-charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 77 drivers/power/supply/lt3651-charger.c val->intval = gpiod_get_value(lt3651_charger->chrg_gpio) ? val 200 drivers/power/supply/ltc2941-battery-gauge.c enum ltc294x_reg reg, int *val) val 209 drivers/power/supply/ltc2941-battery-gauge.c *val = convert_bin_to_uAh(info, value); val 213 drivers/power/supply/ltc2941-battery-gauge.c static int ltc294x_set_charge_now(const struct ltc294x_info *info, int val) val 220 drivers/power/supply/ltc2941-battery-gauge.c value = convert_uAh_to_bin(info, val); val 255 drivers/power/supply/ltc2941-battery-gauge.c enum ltc294x_reg reg, int val) val 260 drivers/power/supply/ltc2941-battery-gauge.c value = convert_uAh_to_bin(info, val); val 274 drivers/power/supply/ltc2941-battery-gauge.c const struct ltc294x_info *info, int *val) val 281 drivers/power/supply/ltc2941-battery-gauge.c *val = convert_bin_to_uAh(info, value); val 285 drivers/power/supply/ltc2941-battery-gauge.c static int ltc294x_get_voltage(const struct ltc294x_info *info, int *val) val 311 drivers/power/supply/ltc2941-battery-gauge.c *val = value; val 315 drivers/power/supply/ltc2941-battery-gauge.c static int ltc294x_get_current(const struct ltc294x_info *info, int *val) val 332 drivers/power/supply/ltc2941-battery-gauge.c *val = 1000 * (value / (info->r_sense * 0x7FFF)); /* in uA */ val 336 drivers/power/supply/ltc2941-battery-gauge.c static int ltc294x_get_temperature(const struct ltc294x_info *info, int *val) val 353 drivers/power/supply/ltc2941-battery-gauge.c *val = value / 0xFFFF - 2722; val 359 drivers/power/supply/ltc2941-battery-gauge.c union power_supply_propval *val) val 366 drivers/power/supply/ltc2941-battery-gauge.c &val->intval); val 369 drivers/power/supply/ltc2941-battery-gauge.c &val->intval); val 372 drivers/power/supply/ltc2941-battery-gauge.c &val->intval); val 374 drivers/power/supply/ltc2941-battery-gauge.c return ltc294x_get_charge_counter(info, &val->intval); val 376 drivers/power/supply/ltc2941-battery-gauge.c return ltc294x_get_voltage(info, &val->intval); val 378 drivers/power/supply/ltc2941-battery-gauge.c return ltc294x_get_current(info, &val->intval); val 380 drivers/power/supply/ltc2941-battery-gauge.c return ltc294x_get_temperature(info, &val->intval); val 388 drivers/power/supply/ltc2941-battery-gauge.c const union power_supply_propval *val) val 395 drivers/power/supply/ltc2941-battery-gauge.c LTC294X_REG_CHARGE_THR_HIGH_MSB, val->intval); val 398 drivers/power/supply/ltc2941-battery-gauge.c LTC294X_REG_CHARGE_THR_LOW_MSB, val->intval); val 400 drivers/power/supply/ltc2941-battery-gauge.c return ltc294x_set_charge_now(info, val->intval); val 27 drivers/power/supply/max14577_charger.c enum maxim_device_type dev_type, u8 val) { val 28 drivers/power/supply/max14577_charger.c switch (val) { val 35 drivers/power/supply/max14577_charger.c return val; val 39 drivers/power/supply/max14577_charger.c val |= 0x8; val 40 drivers/power/supply/max14577_charger.c return val; val 42 drivers/power/supply/max14577_charger.c WARN_ONCE(1, "max14577: Unsupported chgtyp register value 0x%02x", val); val 43 drivers/power/supply/max14577_charger.c return val; val 47 drivers/power/supply/max14577_charger.c static int max14577_get_charger_state(struct max14577_charger *chg, int *val) val 69 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_STATUS_DISCHARGING; val 80 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_STATUS_FULL; val 82 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_STATUS_CHARGING; val 86 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_STATUS_DISCHARGING; val 97 drivers/power/supply/max14577_charger.c static int max14577_get_charge_type(struct max14577_charger *chg, int *val) val 114 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_FAST; val 116 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_NONE; val 121 drivers/power/supply/max14577_charger.c static int max14577_get_online(struct max14577_charger *chg, int *val) val 141 drivers/power/supply/max14577_charger.c *val = 1; val 148 drivers/power/supply/max14577_charger.c *val = 0; val 160 drivers/power/supply/max14577_charger.c static int max14577_get_battery_health(struct max14577_charger *chg, int *val) val 174 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_HEALTH_DEAD; val 183 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 188 drivers/power/supply/max14577_charger.c *val = POWER_SUPPLY_HEALTH_GOOD; val 199 drivers/power/supply/max14577_charger.c static int max14577_get_present(struct max14577_charger *chg, int *val) val 201 drivers/power/supply/max14577_charger.c *val = 1; val 244 drivers/power/supply/max14577_charger.c unsigned int val = uvolt; val 246 drivers/power/supply/max14577_charger.c val -= MAXIM_CHARGER_CONSTANT_VOLTAGE_MIN; val 247 drivers/power/supply/max14577_charger.c val /= MAXIM_CHARGER_CONSTANT_VOLTAGE_STEP; val 249 drivers/power/supply/max14577_charger.c reg_data = 0x1 + val; val 251 drivers/power/supply/max14577_charger.c reg_data = val; /* Fix for gap between 4.18V and 4.22V */ val 412 drivers/power/supply/max14577_charger.c union power_supply_propval *val) val 419 drivers/power/supply/max14577_charger.c ret = max14577_get_charger_state(chg, &val->intval); val 422 drivers/power/supply/max14577_charger.c ret = max14577_get_charge_type(chg, &val->intval); val 425 drivers/power/supply/max14577_charger.c ret = max14577_get_battery_health(chg, &val->intval); val 428 drivers/power/supply/max14577_charger.c ret = max14577_get_present(chg, &val->intval); val 431 drivers/power/supply/max14577_charger.c ret = max14577_get_online(chg, &val->intval); val 435 drivers/power/supply/max14577_charger.c val->strval = model_names[chg->max14577->dev_type]; val 438 drivers/power/supply/max14577_charger.c val->strval = manufacturer; val 514 drivers/power/supply/max14577_charger.c unsigned int val; val 525 drivers/power/supply/max14577_charger.c val = reg_data + 3; val 528 drivers/power/supply/max14577_charger.c val = 0; val 531 drivers/power/supply/max14577_charger.c val = 5; val 535 drivers/power/supply/max14577_charger.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 542 drivers/power/supply/max14577_charger.c unsigned long val; val 545 drivers/power/supply/max14577_charger.c ret = kstrtoul(buf, 10, &val); val 549 drivers/power/supply/max14577_charger.c ret = max14577_set_fast_charge_timer(chg, val); val 90 drivers/power/supply/max14656_charger_detector.c static int max14656_read_reg(struct i2c_client *client, int reg, u8 *val) val 101 drivers/power/supply/max14656_charger_detector.c *val = ret; val 105 drivers/power/supply/max14656_charger_detector.c static int max14656_write_reg(struct i2c_client *client, int reg, u8 val) val 109 drivers/power/supply/max14656_charger_detector.c ret = i2c_smbus_write_byte_data(client, reg, val); val 113 drivers/power/supply/max14656_charger_detector.c val, reg, ret); val 120 drivers/power/supply/max14656_charger_detector.c u8 length, u8 *val) val 124 drivers/power/supply/max14656_charger_detector.c ret = i2c_smbus_read_i2c_block_data(client, reg, length, val); val 174 drivers/power/supply/max14656_charger_detector.c uint8_t val = 0; val 178 drivers/power/supply/max14656_charger_detector.c if (max14656_read_reg(client, MAX14656_DEVICE_ID, &val)) val 181 drivers/power/supply/max14656_charger_detector.c if ((val & DEVICE_VENDOR_MASK) != 0x20) { val 183 drivers/power/supply/max14656_charger_detector.c ((val & DEVICE_VENDOR_MASK) >> 4)); val 186 drivers/power/supply/max14656_charger_detector.c rev = val & DEVICE_REV_MASK; val 212 drivers/power/supply/max14656_charger_detector.c union power_supply_propval *val) val 218 drivers/power/supply/max14656_charger_detector.c val->intval = chip->online; val 221 drivers/power/supply/max14656_charger_detector.c val->strval = MAX14656_NAME; val 224 drivers/power/supply/max14656_charger_detector.c val->strval = MAX14656_MANUFACTURER; val 49 drivers/power/supply/max17040_battery.c union power_supply_propval *val) val 55 drivers/power/supply/max17040_battery.c val->intval = chip->status; val 58 drivers/power/supply/max17040_battery.c val->intval = chip->online; val 61 drivers/power/supply/max17040_battery.c val->intval = chip->vcell; val 64 drivers/power/supply/max17040_battery.c val->intval = chip->soc; val 175 drivers/power/supply/max17042_battery.c u32 val; val 177 drivers/power/supply/max17042_battery.c ret = regmap_read(chip->regmap, MAX17042_AvgVCELL, &val); val 182 drivers/power/supply/max17042_battery.c vavg = val * 625 / 8; val 186 drivers/power/supply/max17042_battery.c ret = regmap_read(chip->regmap, MAX17042_VCELL, &val); val 191 drivers/power/supply/max17042_battery.c vbatt = val * 625 / 8; val 230 drivers/power/supply/max17042_battery.c union power_supply_propval *val) val 243 drivers/power/supply/max17042_battery.c ret = max17042_get_status(chip, &val->intval); val 253 drivers/power/supply/max17042_battery.c val->intval = 0; val 255 drivers/power/supply/max17042_battery.c val->intval = 1; val 258 drivers/power/supply/max17042_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 265 drivers/power/supply/max17042_battery.c val->intval = data; val 272 drivers/power/supply/max17042_battery.c val->intval = data >> 8; val 273 drivers/power/supply/max17042_battery.c val->intval *= 20000; /* Units of LSB = 20mV */ val 280 drivers/power/supply/max17042_battery.c val->intval = (data & 0xff) * 20000; /* Units of 20mV */ val 290 drivers/power/supply/max17042_battery.c val->intval = data >> 7; val 291 drivers/power/supply/max17042_battery.c val->intval *= 10000; /* Units of LSB = 10mV */ val 298 drivers/power/supply/max17042_battery.c val->intval = data * 625 / 8; val 305 drivers/power/supply/max17042_battery.c val->intval = data * 625 / 8; val 312 drivers/power/supply/max17042_battery.c val->intval = data * 625 / 8; val 319 drivers/power/supply/max17042_battery.c val->intval = data >> 8; val 328 drivers/power/supply/max17042_battery.c val->intval = data64; val 337 drivers/power/supply/max17042_battery.c val->intval = data64; val 346 drivers/power/supply/max17042_battery.c val->intval = data64; val 353 drivers/power/supply/max17042_battery.c val->intval = data * 1000 / 2; val 356 drivers/power/supply/max17042_battery.c ret = max17042_get_temperature(chip, &val->intval); val 365 drivers/power/supply/max17042_battery.c val->intval = sign_extend32(data & 0xff, 7) * 10; val 372 drivers/power/supply/max17042_battery.c val->intval = sign_extend32(data >> 8, 7) * 10; val 375 drivers/power/supply/max17042_battery.c val->intval = chip->pdata->temp_min; val 378 drivers/power/supply/max17042_battery.c val->intval = chip->pdata->temp_max; val 381 drivers/power/supply/max17042_battery.c ret = max17042_get_battery_health(chip, &val->intval); val 386 drivers/power/supply/max17042_battery.c val->intval = POWER_SUPPLY_SCOPE_SYSTEM; val 394 drivers/power/supply/max17042_battery.c val->intval = sign_extend32(data, 15); val 395 drivers/power/supply/max17042_battery.c val->intval *= 1562500 / chip->pdata->r_sns; val 406 drivers/power/supply/max17042_battery.c val->intval = sign_extend32(data, 15); val 407 drivers/power/supply/max17042_battery.c val->intval *= 1562500 / chip->pdata->r_sns; val 420 drivers/power/supply/max17042_battery.c const union power_supply_propval *val) val 435 drivers/power/supply/max17042_battery.c temp = val->intval / 10; val 449 drivers/power/supply/max17042_battery.c temp = val->intval / 10; val 844 drivers/power/supply/max17042_battery.c u32 val; val 846 drivers/power/supply/max17042_battery.c regmap_read(chip->regmap, MAX17042_STATUS, &val); val 847 drivers/power/supply/max17042_battery.c if ((val & STATUS_INTR_SOCMIN_BIT) || val 848 drivers/power/supply/max17042_battery.c (val & STATUS_INTR_SOCMAX_BIT)) { val 1016 drivers/power/supply/max17042_battery.c u32 val; val 1108 drivers/power/supply/max17042_battery.c regmap_read(chip->regmap, MAX17042_STATUS, &val); val 1109 drivers/power/supply/max17042_battery.c if (val & STATUS_POR_BIT) { val 100 drivers/power/supply/max1721x_battery.c int val = (int16_t)(reg); val 102 drivers/power/supply/max1721x_battery.c return val * 10 / 256; /* in tenths of deg. C */ val 115 drivers/power/supply/max1721x_battery.c int val = (int16_t)(reg); val 117 drivers/power/supply/max1721x_battery.c return val * 156252; val 129 drivers/power/supply/max1721x_battery.c union power_supply_propval *val) val 142 drivers/power/supply/max1721x_battery.c val->intval = val 148 drivers/power/supply/max1721x_battery.c val->intval = max172xx_percent_to_ps(reg); val 152 drivers/power/supply/max1721x_battery.c val->intval = max172xx_voltage_to_ps(reg); val 156 drivers/power/supply/max1721x_battery.c val->intval = max172xx_capacity_to_ps(reg); val 160 drivers/power/supply/max1721x_battery.c val->intval = max172xx_capacity_to_ps(reg); val 164 drivers/power/supply/max1721x_battery.c val->intval = max172xx_time_to_ps(reg); val 168 drivers/power/supply/max1721x_battery.c val->intval = max172xx_time_to_ps(reg); val 172 drivers/power/supply/max1721x_battery.c val->intval = max172xx_temperature_to_ps(reg); val 177 drivers/power/supply/max1721x_battery.c val->intval = val 182 drivers/power/supply/max1721x_battery.c val->intval = val 191 drivers/power/supply/max1721x_battery.c val->strval = info->DeviceName; val 195 drivers/power/supply/max1721x_battery.c val->strval = info->ManufacturerName; val 199 drivers/power/supply/max1721x_battery.c val->strval = info->SerialNumber; val 229 drivers/power/supply/max1721x_battery.c unsigned int val; val 236 drivers/power/supply/max1721x_battery.c if (regmap_read(info->regmap, reg++, &val)) val 238 drivers/power/supply/max1721x_battery.c *str++ = val>>8 & 0x00FF; val 239 drivers/power/supply/max1721x_battery.c *str++ = val & 0x00FF; val 247 drivers/power/supply/max1721x_battery.c unsigned int val[3]; val 252 drivers/power/supply/max1721x_battery.c if (regmap_read(info->regmap, MAX1721X_REG_SER_HEX, &val[0])) val 254 drivers/power/supply/max1721x_battery.c if (regmap_read(info->regmap, MAX1721X_REG_SER_HEX + 1, &val[1])) val 256 drivers/power/supply/max1721x_battery.c if (regmap_read(info->regmap, MAX1721X_REG_SER_HEX + 2, &val[2])) val 259 drivers/power/supply/max1721x_battery.c snprintf(str, 13, "%04X%04X%04X", val[0], val[1], val[2]); val 89 drivers/power/supply/max77650-charger.c unsigned int val) val 94 drivers/power/supply/max77650-charger.c if (val == max77650_charger_vchgin_min_table[i]) { val 110 drivers/power/supply/max77650-charger.c unsigned int val) val 115 drivers/power/supply/max77650-charger.c if (val == max77650_charger_ichgin_lim_table[i]) { val 192 drivers/power/supply/max77650-charger.c union power_supply_propval *val) val 204 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 213 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 222 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 225 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_STATUS_FULL; val 228 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 236 drivers/power/supply/max77650-charger.c val->intval = MAX77650_CHARGER_CHG_CHARGING(reg); val 244 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; val 254 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; val 258 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 261 drivers/power/supply/max77650-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN; val 32 drivers/power/supply/max77693_charger.c static int max77693_get_charger_state(struct regmap *regmap, int *val) val 51 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_STATUS_CHARGING; val 54 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_STATUS_FULL; val 58 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_STATUS_NOT_CHARGING; val 63 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_STATUS_DISCHARGING; val 67 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_STATUS_UNKNOWN; val 73 drivers/power/supply/max77693_charger.c static int max77693_get_charge_type(struct regmap *regmap, int *val) val 92 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 98 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_FAST; val 106 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_NONE; val 110 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN; val 125 drivers/power/supply/max77693_charger.c static int max77693_get_battery_health(struct regmap *regmap, int *val) val 139 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_HEALTH_DEAD; val 144 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_HEALTH_GOOD; val 151 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; val 154 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 157 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 161 drivers/power/supply/max77693_charger.c *val = POWER_SUPPLY_HEALTH_UNKNOWN; val 168 drivers/power/supply/max77693_charger.c static int max77693_get_present(struct regmap *regmap, int *val) val 181 drivers/power/supply/max77693_charger.c *val = (data & CHG_INT_OK_DETBAT_MASK) ? 0 : 1; val 186 drivers/power/supply/max77693_charger.c static int max77693_get_online(struct regmap *regmap, int *val) val 195 drivers/power/supply/max77693_charger.c *val = (data & CHG_INT_OK_CHGIN_MASK) ? 1 : 0; val 212 drivers/power/supply/max77693_charger.c union power_supply_propval *val) val 220 drivers/power/supply/max77693_charger.c ret = max77693_get_charger_state(regmap, &val->intval); val 223 drivers/power/supply/max77693_charger.c ret = max77693_get_charge_type(regmap, &val->intval); val 226 drivers/power/supply/max77693_charger.c ret = max77693_get_battery_health(regmap, &val->intval); val 229 drivers/power/supply/max77693_charger.c ret = max77693_get_present(regmap, &val->intval); val 232 drivers/power/supply/max77693_charger.c ret = max77693_get_online(regmap, &val->intval); val 235 drivers/power/supply/max77693_charger.c val->strval = max77693_charger_model; val 238 drivers/power/supply/max77693_charger.c val->strval = max77693_charger_manufacturer; val 260 drivers/power/supply/max77693_charger.c unsigned long val; val 263 drivers/power/supply/max77693_charger.c ret = kstrtoul(buf, 10, &val); val 267 drivers/power/supply/max77693_charger.c ret = fn(chg, val); val 278 drivers/power/supply/max77693_charger.c unsigned int data, val; val 291 drivers/power/supply/max77693_charger.c val = 4 + (data - 1) * 2; val 295 drivers/power/supply/max77693_charger.c val = 0; val 299 drivers/power/supply/max77693_charger.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 344 drivers/power/supply/max77693_charger.c unsigned int data, val; val 356 drivers/power/supply/max77693_charger.c val = 100000 + data * 25000; val 358 drivers/power/supply/max77693_charger.c val = data * 50000; val 360 drivers/power/supply/max77693_charger.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 395 drivers/power/supply/max77693_charger.c unsigned int data, val; val 406 drivers/power/supply/max77693_charger.c val = data * 10; val 408 drivers/power/supply/max77693_charger.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 38 drivers/power/supply/max8903_charger.c union power_supply_propval *val) val 44 drivers/power/supply/max8903_charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 47 drivers/power/supply/max8903_charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 49 drivers/power/supply/max8903_charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 51 drivers/power/supply/max8903_charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 55 drivers/power/supply/max8903_charger.c val->intval = 0; val 57 drivers/power/supply/max8903_charger.c val->intval = 1; val 60 drivers/power/supply/max8903_charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 62 drivers/power/supply/max8903_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 195 drivers/power/supply/max8925_power.c union power_supply_propval *val) val 202 drivers/power/supply/max8925_power.c val->intval = info->ac_online; val 208 drivers/power/supply/max8925_power.c val->intval = ret * 2000; /* unit is uV */ val 229 drivers/power/supply/max8925_power.c union power_supply_propval *val) val 236 drivers/power/supply/max8925_power.c val->intval = info->usb_online; val 242 drivers/power/supply/max8925_power.c val->intval = ret * 2000; /* unit is uV */ val 263 drivers/power/supply/max8925_power.c union power_supply_propval *val) val 270 drivers/power/supply/max8925_power.c val->intval = info->bat_online; val 276 drivers/power/supply/max8925_power.c val->intval = ret * 2000; /* unit is uV */ val 289 drivers/power/supply/max8925_power.c val->intval = 0; val 291 drivers/power/supply/max8925_power.c val->intval = ret; /* unit is mA */ val 307 drivers/power/supply/max8925_power.c val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; val 311 drivers/power/supply/max8925_power.c val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 314 drivers/power/supply/max8925_power.c val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; val 326 drivers/power/supply/max8925_power.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 328 drivers/power/supply/max8925_power.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 330 drivers/power/supply/max8925_power.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 31 drivers/power/supply/max8997_charger.c union power_supply_propval *val) val 40 drivers/power/supply/max8997_charger.c val->intval = 0; val 45 drivers/power/supply/max8997_charger.c val->intval = POWER_SUPPLY_STATUS_FULL; val 49 drivers/power/supply/max8997_charger.c val->intval = 0; val 54 drivers/power/supply/max8997_charger.c val->intval = 1; val 58 drivers/power/supply/max8997_charger.c val->intval = 0; val 64 drivers/power/supply/max8997_charger.c val->intval = 1; val 94 drivers/power/supply/max8997_charger.c int val = (pdata->eoc_mA - 50) / 10; val 95 drivers/power/supply/max8997_charger.c if (val < 0) val 96 drivers/power/supply/max8997_charger.c val = 0; val 97 drivers/power/supply/max8997_charger.c if (val > 0xf) val 98 drivers/power/supply/max8997_charger.c val = 0xf; val 101 drivers/power/supply/max8997_charger.c MAX8997_REG_MBCCTRL5, val, 0xf); val 31 drivers/power/supply/max8998_charger.c union power_supply_propval *val) val 44 drivers/power/supply/max8998_charger.c val->intval = 0; val 46 drivers/power/supply/max8998_charger.c val->intval = 1; val 53 drivers/power/supply/max8998_charger.c val->intval = 0; val 55 drivers/power/supply/max8998_charger.c val->intval = 1; val 66 drivers/power/supply/olpc_battery.c union power_supply_propval *val) val 77 drivers/power/supply/olpc_battery.c val->intval = !!(status & BAT_STAT_AC); val 99 drivers/power/supply/olpc_battery.c union power_supply_propval *val, uint8_t ec_byte) val 103 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 105 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 107 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_STATUS_FULL; val 109 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 113 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 115 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_STATUS_FULL; val 117 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 123 drivers/power/supply/olpc_battery.c static int olpc_bat_get_health(union power_supply_propval *val) val 134 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 138 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 142 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 149 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 160 drivers/power/supply/olpc_battery.c static int olpc_bat_get_mfr(union power_supply_propval *val) val 172 drivers/power/supply/olpc_battery.c val->strval = "Gold Peak"; val 175 drivers/power/supply/olpc_battery.c val->strval = "BYD"; val 178 drivers/power/supply/olpc_battery.c val->strval = "Unknown"; val 185 drivers/power/supply/olpc_battery.c static int olpc_bat_get_tech(union power_supply_propval *val) val 197 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_NiMH; val 200 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LiFe; val 203 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_UNKNOWN; val 210 drivers/power/supply/olpc_battery.c static int olpc_bat_get_charge_full_design(union power_supply_propval *val) val 231 drivers/power/supply/olpc_battery.c val->intval = 3000000*.8; val 242 drivers/power/supply/olpc_battery.c val->intval = 2800000; val 256 drivers/power/supply/olpc_battery.c static int olpc_bat_get_charge_now(union power_supply_propval *val) val 270 drivers/power/supply/olpc_battery.c val->intval = soc * (full.intval / 100); val 274 drivers/power/supply/olpc_battery.c static int olpc_bat_get_voltage_max_design(union power_supply_propval *val) val 296 drivers/power/supply/olpc_battery.c val->intval = 6000000; val 306 drivers/power/supply/olpc_battery.c val->intval = 6400000; val 309 drivers/power/supply/olpc_battery.c val->intval = 6500000; val 336 drivers/power/supply/olpc_battery.c union power_supply_propval *val) val 360 drivers/power/supply/olpc_battery.c ret = olpc_bat_get_status(data, val, ec_byte); val 366 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 368 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; val 370 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; val 373 drivers/power/supply/olpc_battery.c val->intval = !!(ec_byte & (BAT_STAT_PRESENT | val 379 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 381 drivers/power/supply/olpc_battery.c ret = olpc_bat_get_health(val); val 388 drivers/power/supply/olpc_battery.c ret = olpc_bat_get_mfr(val); val 393 drivers/power/supply/olpc_battery.c ret = olpc_bat_get_tech(val); val 403 drivers/power/supply/olpc_battery.c val->intval = ecword_to_cpu(data, ec_word) * 9760L / 32; val 411 drivers/power/supply/olpc_battery.c val->intval = ecword_to_cpu(data, ec_word) * 15625L / 120; val 417 drivers/power/supply/olpc_battery.c val->intval = ec_byte; val 421 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_FULL; val 423 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_LOW; val 425 drivers/power/supply/olpc_battery.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; val 428 drivers/power/supply/olpc_battery.c ret = olpc_bat_get_charge_full_design(val); val 433 drivers/power/supply/olpc_battery.c ret = olpc_bat_get_charge_now(val); val 442 drivers/power/supply/olpc_battery.c val->intval = ecword_to_cpu(data, ec_word) * 10 / 256; val 449 drivers/power/supply/olpc_battery.c val->intval = (int)ecword_to_cpu(data, ec_word) * 10 / 256; val 456 drivers/power/supply/olpc_battery.c val->intval = ecword_to_cpu(data, ec_word) * 6250 / 15; val 464 drivers/power/supply/olpc_battery.c val->strval = data->bat_serial; val 467 drivers/power/supply/olpc_battery.c ret = olpc_bat_get_voltage_max_design(val); val 281 drivers/power/supply/pcf50633-charger.c union power_supply_propval *val) val 288 drivers/power/supply/pcf50633-charger.c val->intval = mbc->adapter_online; val 299 drivers/power/supply/pcf50633-charger.c union power_supply_propval *val) val 308 drivers/power/supply/pcf50633-charger.c val->intval = mbc->usb_online && val 320 drivers/power/supply/pcf50633-charger.c union power_supply_propval *val) val 329 drivers/power/supply/pcf50633-charger.c val->intval = mbc->usb_online && val 55 drivers/power/supply/pda_power.c union power_supply_propval *val) val 60 drivers/power/supply/pda_power.c val->intval = pdata->is_ac_online ? val 63 drivers/power/supply/pda_power.c val->intval = pdata->is_usb_online ? val 126 drivers/power/supply/pm2301_charger.c static int pm2xxx_reg_read(struct pm2xxx_charger *pm2, int reg, u8 *val) val 134 drivers/power/supply/pm2301_charger.c 1, val); val 145 drivers/power/supply/pm2301_charger.c static int pm2xxx_reg_write(struct pm2xxx_charger *pm2, int reg, u8 val) val 153 drivers/power/supply/pm2301_charger.c 1, &val); val 197 drivers/power/supply/pm2301_charger.c static int pm2xxx_charger_batt_therm_mngt(struct pm2xxx_charger *pm2, int val) val 205 drivers/power/supply/pm2301_charger.c static int pm2xxx_charger_die_therm_mngt(struct pm2xxx_charger *pm2, int val) val 212 drivers/power/supply/pm2301_charger.c static int pm2xxx_charger_ovv_mngt(struct pm2xxx_charger *pm2, int val) val 224 drivers/power/supply/pm2301_charger.c static int pm2xxx_charger_wd_exp_mngt(struct pm2xxx_charger *pm2, int val) val 234 drivers/power/supply/pm2301_charger.c static int pm2xxx_charger_vbat_lsig_mngt(struct pm2xxx_charger *pm2, int val) val 238 drivers/power/supply/pm2301_charger.c switch (val) { val 268 drivers/power/supply/pm2301_charger.c static int pm2xxx_charger_bat_disc_mngt(struct pm2xxx_charger *pm2, int val) val 275 drivers/power/supply/pm2301_charger.c static int pm2xxx_charger_detection(struct pm2xxx_charger *pm2, u8 *val) val 279 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_read(pm2, PM2XXX_SRCE_REG_INT2, val); val 286 drivers/power/supply/pm2301_charger.c *val &= (PM2XXX_INT2_S_ITVPWR1PLUG | PM2XXX_INT2_S_ITVPWR2PLUG); val 292 drivers/power/supply/pm2301_charger.c static int pm2xxx_charger_itv_pwr_plug_mngt(struct pm2xxx_charger *pm2, int val) val 316 drivers/power/supply/pm2301_charger.c int val) val 324 drivers/power/supply/pm2301_charger.c static int pm2_int_reg0(void *pm2_data, int val) val 329 drivers/power/supply/pm2301_charger.c if (val & PM2XXX_INT1_ITVBATLOWR) { val 336 drivers/power/supply/pm2301_charger.c if (val & PM2XXX_INT1_ITVBATLOWF) { val 343 drivers/power/supply/pm2301_charger.c if (val & PM2XXX_INT1_ITVBATDISCONNECT) { val 353 drivers/power/supply/pm2301_charger.c static int pm2_int_reg1(void *pm2_data, int val) val 358 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT2_ITVPWR1PLUG | PM2XXX_INT2_ITVPWR2PLUG)) { val 360 drivers/power/supply/pm2301_charger.c ret = pm2xxx_charger_itv_pwr_plug_mngt(pm2, val & val 364 drivers/power/supply/pm2301_charger.c if (val & val 367 drivers/power/supply/pm2301_charger.c ret = pm2xxx_charger_itv_pwr_unplug_mngt(pm2, val & val 375 drivers/power/supply/pm2301_charger.c static int pm2_int_reg2(void *pm2_data, int val) val 380 drivers/power/supply/pm2301_charger.c if (val & PM2XXX_INT3_ITAUTOTIMEOUTWD) val 381 drivers/power/supply/pm2301_charger.c ret = pm2xxx_charger_wd_exp_mngt(pm2, val); val 383 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT3_ITCHPRECHARGEWD | val 392 drivers/power/supply/pm2301_charger.c static int pm2_int_reg3(void *pm2_data, int val) val 397 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT4_ITCHARGINGON)) { val 402 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT4_ITVRESUME)) { val 407 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT4_ITBATTFULL)) { val 411 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT4_ITCVPHASE)) { val 415 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT4_ITVPWR2OVV | PM2XXX_INT4_ITVPWR1OVV)) { val 417 drivers/power/supply/pm2301_charger.c ret = pm2xxx_charger_ovv_mngt(pm2, val & val 422 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT4_S_ITBATTEMPCOLD | val 424 drivers/power/supply/pm2301_charger.c ret = pm2xxx_charger_batt_therm_mngt(pm2, val & val 433 drivers/power/supply/pm2301_charger.c static int pm2_int_reg4(void *pm2_data, int val) val 438 drivers/power/supply/pm2301_charger.c if (val & PM2XXX_INT5_ITVSYSTEMOVV) { val 440 drivers/power/supply/pm2301_charger.c ret = pm2xxx_charger_ovv_mngt(pm2, val & val 445 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT5_ITTHERMALWARNINGFALL | val 450 drivers/power/supply/pm2301_charger.c ret = pm2xxx_charger_die_therm_mngt(pm2, val & val 460 drivers/power/supply/pm2301_charger.c static int pm2_int_reg5(void *pm2_data, int val) val 465 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT6_ITVPWR2DROP | PM2XXX_INT6_ITVPWR1DROP)) { val 469 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT6_ITVPWR2VALIDRISE | val 508 drivers/power/supply/pm2301_charger.c u8 val; val 512 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_read(pm2, PM2XXX_SRCE_REG_INT4, &val); val 518 drivers/power/supply/pm2301_charger.c if (val & PM2XXX_INT4_S_ITCVPHASE) val 571 drivers/power/supply/pm2301_charger.c u8 val; val 585 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_read(pm2, PM2XXX_BATT_CTRL_REG6, &val); val 587 drivers/power/supply/pm2301_charger.c val &= ~PM2XXX_DIR_CH_CC_CURRENT_MASK; val 588 drivers/power/supply/pm2301_charger.c val |= curr_index; val 589 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_write(pm2, PM2XXX_BATT_CTRL_REG6, val); val 603 drivers/power/supply/pm2301_charger.c union power_supply_propval *val) val 612 drivers/power/supply/pm2301_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 614 drivers/power/supply/pm2301_charger.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 616 drivers/power/supply/pm2301_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 618 drivers/power/supply/pm2301_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 620 drivers/power/supply/pm2301_charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 623 drivers/power/supply/pm2301_charger.c val->intval = pm2->ac.charger_online; val 626 drivers/power/supply/pm2301_charger.c val->intval = pm2->ac.charger_connected; val 630 drivers/power/supply/pm2301_charger.c val->intval = pm2->ac.cv_active; val 710 drivers/power/supply/pm2301_charger.c u8 val; val 747 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_read(pm2, PM2XXX_BATT_CTRL_REG8, &val); val 752 drivers/power/supply/pm2301_charger.c val &= ~PM2XXX_CH_VOLT_MASK; val 753 drivers/power/supply/pm2301_charger.c val |= volt_index; val 754 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_write(pm2, PM2XXX_BATT_CTRL_REG8, val); val 760 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_read(pm2, PM2XXX_BATT_CTRL_REG6, &val); val 765 drivers/power/supply/pm2301_charger.c val &= ~PM2XXX_DIR_CH_CC_CURRENT_MASK; val 766 drivers/power/supply/pm2301_charger.c val |= curr_index; val 767 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_write(pm2, PM2XXX_BATT_CTRL_REG6, val); val 774 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_read(pm2, PM2XXX_LED_CTRL_REG, &val); val 780 drivers/power/supply/pm2301_charger.c val |= PM2XXX_ANTI_OVERSHOOT_EN; val 781 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_write(pm2, PM2XXX_LED_CTRL_REG, val); val 877 drivers/power/supply/pm2301_charger.c u8 val; val 883 drivers/power/supply/pm2301_charger.c ret = pm2xxx_reg_read(pm2, PM2XXX_SRCE_REG_INT5, &val); val 888 drivers/power/supply/pm2301_charger.c if (val & (PM2XXX_INT5_S_ITTHERMALWARNINGRISE val 891 drivers/power/supply/pm2301_charger.c else if (val & (PM2XXX_INT5_S_ITTHERMALWARNINGFALL val 982 drivers/power/supply/pm2301_charger.c u8 val; val 1153 drivers/power/supply/pm2301_charger.c &val); val 1155 drivers/power/supply/pm2301_charger.c ret = pm2xxx_charger_detection(pm2, &val); val 1157 drivers/power/supply/pm2301_charger.c if ((ret == 0) && val) { val 32 drivers/power/supply/pmu_battery.c union power_supply_propval *val) val 36 drivers/power/supply/pmu_battery.c val->intval = (!!(pmu_power_flags & PMU_PWR_AC_PRESENT)) || val 84 drivers/power/supply/pmu_battery.c union power_supply_propval *val) val 92 drivers/power/supply/pmu_battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 94 drivers/power/supply/pmu_battery.c val->intval = POWER_SUPPLY_STATUS_FULL; val 96 drivers/power/supply/pmu_battery.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 99 drivers/power/supply/pmu_battery.c val->intval = !!(pbi->flags & PMU_BATT_PRESENT); val 102 drivers/power/supply/pmu_battery.c val->strval = pmu_bat_get_model_name(pbi); val 105 drivers/power/supply/pmu_battery.c val->intval = pbi->charge * 1000; /* mWh -> µWh */ val 108 drivers/power/supply/pmu_battery.c val->intval = pbi->max_charge * 1000; /* mWh -> µWh */ val 111 drivers/power/supply/pmu_battery.c val->intval = pbi->amperage * 1000; /* mA -> µA */ val 114 drivers/power/supply/pmu_battery.c val->intval = pbi->voltage * 1000; /* mV -> µV */ val 117 drivers/power/supply/pmu_battery.c val->intval = pbi->time_remaining; val 396 drivers/power/supply/power_supply_core.c union power_supply_propval val = {0,}; val 412 drivers/power/supply/power_supply_core.c val.intval = curr; val 415 drivers/power/supply/power_supply_core.c POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val); val 774 drivers/power/supply/power_supply_core.c union power_supply_propval *val) val 782 drivers/power/supply/power_supply_core.c return psy->desc->get_property(psy, psp, val); val 788 drivers/power/supply/power_supply_core.c const union power_supply_propval *val) val 793 drivers/power/supply/power_supply_core.c return psy->desc->set_property(psy, psp, val); val 848 drivers/power/supply/power_supply_core.c union power_supply_propval val; val 853 drivers/power/supply/power_supply_core.c ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TEMP, &val); val 858 drivers/power/supply/power_supply_core.c *temp = val.intval * 100; val 897 drivers/power/supply/power_supply_core.c union power_supply_propval val; val 902 drivers/power/supply/power_supply_core.c POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX, &val); val 906 drivers/power/supply/power_supply_core.c *state = val.intval; val 915 drivers/power/supply/power_supply_core.c union power_supply_propval val; val 920 drivers/power/supply/power_supply_core.c POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT, &val); val 924 drivers/power/supply/power_supply_core.c *state = val.intval; val 933 drivers/power/supply/power_supply_core.c union power_supply_propval val; val 937 drivers/power/supply/power_supply_core.c val.intval = state; val 939 drivers/power/supply/power_supply_core.c POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT, &val); val 153 drivers/power/supply/power_supply_hwmon.c u32 attr, int channel, long *val) val 190 drivers/power/supply/power_supply_hwmon.c *val = pspval.intval; val 197 drivers/power/supply/power_supply_hwmon.c u32 attr, int channel, long val) val 208 drivers/power/supply/power_supply_hwmon.c pspval.intval = val; val 167 drivers/power/supply/qcom_smbb.c static unsigned int smbb_hw_lookup(unsigned int val, int (*fn)(unsigned int)) val 172 drivers/power/supply/qcom_smbb.c for (widx = sel = 0; (*fn)(widx) <= val; ++widx) val 257 drivers/power/supply/qcom_smbb.c enum smbb_attr which, unsigned int val) val 266 drivers/power/supply/qcom_smbb.c if (val > prop->max || val < prop->min) { val 284 drivers/power/supply/qcom_smbb.c if (val > wval) { val 288 drivers/power/supply/qcom_smbb.c val = wval; val 292 drivers/power/supply/qcom_smbb.c wval = smbb_hw_lookup(val, prop->hw_fn); val 300 drivers/power/supply/qcom_smbb.c if (out != val) { val 317 drivers/power/supply/qcom_smbb.c unsigned int val; val 322 drivers/power/supply/qcom_smbb.c rc = regmap_read(chg->regmap, chg->addr + prop->reg, &val); val 327 drivers/power/supply/qcom_smbb.c val = prop->hw_fn(val); val 328 drivers/power/supply/qcom_smbb.c dev_dbg(chg->dev, "%s => %d\n", prop->name, val); val 330 drivers/power/supply/qcom_smbb.c chg->attr[which] = val; val 339 drivers/power/supply/qcom_smbb.c unsigned int val; val 344 drivers/power/supply/qcom_smbb.c rc = of_property_read_u32(chg->dev->of_node, prop->name, &val); val 346 drivers/power/supply/qcom_smbb.c rc = smbb_charger_attr_write(chg, which, val); val 400 drivers/power/supply/qcom_smbb.c unsigned int val; val 403 drivers/power/supply/qcom_smbb.c rc = regmap_read(chg->regmap, chg->addr + SMBB_BAT_TEMP_STATUS, &val); val 408 drivers/power/supply/qcom_smbb.c if (val & TEMP_STATUS_OK) { val 412 drivers/power/supply/qcom_smbb.c if (val & TEMP_STATUS_HOT) val 490 drivers/power/supply/qcom_smbb.c union power_supply_propval *val) val 498 drivers/power/supply/qcom_smbb.c val->intval = !(chg->status & STATUS_CHG_GONE) && val 503 drivers/power/supply/qcom_smbb.c val->intval = chg->attr[ATTR_USBIN_IMAX]; val 506 drivers/power/supply/qcom_smbb.c val->intval = 2500000; val 518 drivers/power/supply/qcom_smbb.c const union power_supply_propval *val) val 526 drivers/power/supply/qcom_smbb.c val->intval); val 538 drivers/power/supply/qcom_smbb.c union power_supply_propval *val) val 546 drivers/power/supply/qcom_smbb.c val->intval = !(chg->status & STATUS_CHG_GONE) && val 551 drivers/power/supply/qcom_smbb.c val->intval = chg->attr[ATTR_DCIN_IMAX]; val 554 drivers/power/supply/qcom_smbb.c val->intval = 2500000; val 566 drivers/power/supply/qcom_smbb.c const union power_supply_propval *val) val 574 drivers/power/supply/qcom_smbb.c val->intval); val 592 drivers/power/supply/qcom_smbb.c union power_supply_propval *val) val 605 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 607 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 609 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_STATUS_FULL; val 611 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 613 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 615 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 619 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 621 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 623 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_HEALTH_COLD; val 627 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; val 629 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 631 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; val 634 drivers/power/supply/qcom_smbb.c val->intval = !!(status & STATUS_BAT_PRESENT); val 637 drivers/power/supply/qcom_smbb.c val->intval = chg->attr[ATTR_BAT_IMAX]; val 640 drivers/power/supply/qcom_smbb.c val->intval = chg->attr[ATTR_BAT_VMAX]; val 647 drivers/power/supply/qcom_smbb.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 650 drivers/power/supply/qcom_smbb.c val->intval = 3000000; /* single-cell li-ion low end */ val 662 drivers/power/supply/qcom_smbb.c const union power_supply_propval *val) val 669 drivers/power/supply/qcom_smbb.c rc = smbb_charger_attr_write(chg, ATTR_BAT_IMAX, val->intval); val 672 drivers/power/supply/qcom_smbb.c rc = smbb_charger_attr_write(chg, ATTR_BAT_VMAX, val->intval); val 28 drivers/power/supply/rt5033_battery.c u32 val; val 30 drivers/power/supply/rt5033_battery.c regmap_read(battery->regmap, RT5033_FUEL_REG_CONFIG_L, &val); val 32 drivers/power/supply/rt5033_battery.c return (val & RT5033_FUEL_BAT_PRESENT) ? true : false; val 70 drivers/power/supply/rt5033_battery.c union power_supply_propval *val) val 78 drivers/power/supply/rt5033_battery.c val->intval = rt5033_battery_get_watt_prop(battery->client, val 82 drivers/power/supply/rt5033_battery.c val->intval = rt5033_battery_get_present(battery->client); val 85 drivers/power/supply/rt5033_battery.c val->intval = rt5033_battery_get_capacity(battery->client); val 273 drivers/power/supply/rt9455_charger.c const int tbl[], int tbl_size, int *val) val 283 drivers/power/supply/rt9455_charger.c *val = tbl[v]; val 290 drivers/power/supply/rt9455_charger.c const int tbl[], int tbl_size, int val) val 292 drivers/power/supply/rt9455_charger.c unsigned int idx = rt9455_find_idx(tbl, tbl_size, val); val 353 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 370 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 390 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 393 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 396 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_STATUS_FULL; val 399 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 405 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 411 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 420 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 424 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 428 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 439 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 443 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; val 454 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 458 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; val 462 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 466 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; val 477 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 485 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 500 drivers/power/supply/rt9455_charger.c val->intval = !v; val 506 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 517 drivers/power/supply/rt9455_charger.c val->intval = (int)v; val 523 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 537 drivers/power/supply/rt9455_charger.c val->intval = curr; val 543 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 547 drivers/power/supply/rt9455_charger.c val->intval = rt9455_ichrg_values[idx]; val 553 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 567 drivers/power/supply/rt9455_charger.c val->intval = voltage; val 573 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 577 drivers/power/supply/rt9455_charger.c val->intval = rt9455_vmreg_values[idx]; val 583 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 606 drivers/power/supply/rt9455_charger.c val->intval = ichrg * ieoc_percentage / 100; val 613 drivers/power/supply/rt9455_charger.c union power_supply_propval *val) val 619 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_status(info, val); val 621 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_health(info, val); val 623 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_battery_presence(info, val); val 625 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_online(info, val); val 627 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_current(info, val); val 629 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_current_max(info, val); val 631 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_voltage(info, val); val 633 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_voltage_max(info, val); val 635 drivers/power/supply/rt9455_charger.c val->intval = POWER_SUPPLY_SCOPE_SYSTEM; val 638 drivers/power/supply/rt9455_charger.c return rt9455_charger_get_term_current(info, val); val 640 drivers/power/supply/rt9455_charger.c val->strval = RT9455_MODEL_NAME; val 643 drivers/power/supply/rt9455_charger.c val->strval = RT9455_MANUFACTURER; val 30 drivers/power/supply/rx51_battery.c int val, err; val 31 drivers/power/supply/rx51_battery.c err = iio_read_channel_average_raw(channel, &val); val 34 drivers/power/supply/rx51_battery.c return val; val 149 drivers/power/supply/rx51_battery.c union power_supply_propval *val) val 155 drivers/power/supply/rx51_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 158 drivers/power/supply/rx51_battery.c val->intval = 4200000; val 161 drivers/power/supply/rx51_battery.c val->intval = rx51_battery_read_voltage(di) ? 1 : 0; val 164 drivers/power/supply/rx51_battery.c val->intval = rx51_battery_read_voltage(di); val 167 drivers/power/supply/rx51_battery.c val->intval = rx51_battery_read_temperature(di); val 170 drivers/power/supply/rx51_battery.c val->intval = rx51_battery_read_capacity(di); val 176 drivers/power/supply/rx51_battery.c if (val->intval == INT_MAX || val->intval == INT_MIN) val 74 drivers/power/supply/s3c_adc_battery.c union power_supply_propval *val) val 95 drivers/power/supply/s3c_adc_battery.c val->intval = bat->volt_value; val 98 drivers/power/supply/s3c_adc_battery.c val->intval = bat->pdata->backup_volt_min; val 101 drivers/power/supply/s3c_adc_battery.c val->intval = bat->pdata->backup_volt_max; val 142 drivers/power/supply/s3c_adc_battery.c union power_supply_propval *val) val 210 drivers/power/supply/s3c_adc_battery.c val->intval = bat->level == 100000 ? val 213 drivers/power/supply/s3c_adc_battery.c val->intval = bat->status; val 216 drivers/power/supply/s3c_adc_battery.c val->intval = 100000; val 219 drivers/power/supply/s3c_adc_battery.c val->intval = 0; val 222 drivers/power/supply/s3c_adc_battery.c val->intval = bat->level; val 225 drivers/power/supply/s3c_adc_battery.c val->intval = bat->volt_value; val 228 drivers/power/supply/s3c_adc_battery.c val->intval = bat->cur_value; val 313 drivers/power/supply/sbs-battery.c union power_supply_propval *val) val 322 drivers/power/supply/sbs-battery.c val->intval = 0; val 329 drivers/power/supply/sbs-battery.c val->intval = 1; /* battery present */ val 332 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_HEALTH_UNKNOWN; val 339 drivers/power/supply/sbs-battery.c union power_supply_propval *val) val 351 drivers/power/supply/sbs-battery.c val->intval = 0; /* battery removed */ val 358 drivers/power/supply/sbs-battery.c val->intval = 0; /* battery removed */ val 364 drivers/power/supply/sbs-battery.c val->intval = 0; val 376 drivers/power/supply/sbs-battery.c val->intval = 0; val 378 drivers/power/supply/sbs-battery.c val->intval = 1; val 381 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; val 383 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 385 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_HEALTH_DEAD; val 387 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 395 drivers/power/supply/sbs-battery.c union power_supply_propval *val) val 410 drivers/power/supply/sbs-battery.c val->intval = ret; val 413 drivers/power/supply/sbs-battery.c val->intval = val 416 drivers/power/supply/sbs-battery.c val->intval = val 419 drivers/power/supply/sbs-battery.c val->intval = val 422 drivers/power/supply/sbs-battery.c val->intval = val 430 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_STATUS_FULL; val 432 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 434 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 436 drivers/power/supply/sbs-battery.c sbs_status_correct(client, &val->intval); val 439 drivers/power/supply/sbs-battery.c chip->last_state = val->intval; val 440 drivers/power/supply/sbs-battery.c else if (chip->last_state != val->intval) { val 447 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 452 drivers/power/supply/sbs-battery.c val->intval = min(ret, 100); val 454 drivers/power/supply/sbs-battery.c val->intval = 0; val 461 drivers/power/supply/sbs-battery.c int reg_offset, enum power_supply_property psp, char *val) val 465 drivers/power/supply/sbs-battery.c ret = sbs_read_string_data(client, sbs_data[reg_offset].addr, val); val 474 drivers/power/supply/sbs-battery.c enum power_supply_property psp, union power_supply_propval *val) val 487 drivers/power/supply/sbs-battery.c val->intval *= BATTERY_MODE_CAP_MULT_WATT; val 497 drivers/power/supply/sbs-battery.c val->intval *= BASE_UNIT_CONVERSION; val 504 drivers/power/supply/sbs-battery.c val->intval -= TEMP_KELVIN_TO_CELSIUS; val 512 drivers/power/supply/sbs-battery.c val->intval *= TIME_UNIT_CONVERSION; val 549 drivers/power/supply/sbs-battery.c union power_supply_propval *val) val 565 drivers/power/supply/sbs-battery.c val->intval = ret; val 576 drivers/power/supply/sbs-battery.c union power_supply_propval *val) val 585 drivers/power/supply/sbs-battery.c val->strval = sbs_serial; val 606 drivers/power/supply/sbs-battery.c union power_supply_propval *val) val 617 drivers/power/supply/sbs-battery.c val->intval = ret; val 618 drivers/power/supply/sbs-battery.c chip->is_present = val->intval; val 630 drivers/power/supply/sbs-battery.c psp, val); val 633 drivers/power/supply/sbs-battery.c val); val 641 drivers/power/supply/sbs-battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 659 drivers/power/supply/sbs-battery.c ret = sbs_get_battery_capacity(client, ret, psp, val); val 664 drivers/power/supply/sbs-battery.c ret = sbs_get_battery_serial_number(client, val); val 682 drivers/power/supply/sbs-battery.c ret = sbs_get_battery_property(client, ret, psp, val); val 692 drivers/power/supply/sbs-battery.c val->strval = model_name; val 702 drivers/power/supply/sbs-battery.c val->strval = manufacturer; val 723 drivers/power/supply/sbs-battery.c sbs_unit_adjustment(client, psp, val); val 727 drivers/power/supply/sbs-battery.c "%s: property = %d, value = %x\n", __func__, psp, val->intval); val 46 drivers/power/supply/sbs-charger.c union power_supply_propval *val) val 55 drivers/power/supply/sbs-charger.c val->intval = !!(reg & SBS_CHARGER_STATUS_BATTERY_PRESENT); val 59 drivers/power/supply/sbs-charger.c val->intval = !!(reg & SBS_CHARGER_STATUS_AC_PRESENT); val 63 drivers/power/supply/sbs-charger.c val->intval = POWER_SUPPLY_STATUS_UNKNOWN; val 66 drivers/power/supply/sbs-charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 69 drivers/power/supply/sbs-charger.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 71 drivers/power/supply/sbs-charger.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 77 drivers/power/supply/sbs-charger.c val->intval = POWER_SUPPLY_HEALTH_COLD; val 79 drivers/power/supply/sbs-charger.c val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; val 81 drivers/power/supply/sbs-charger.c val->intval = POWER_SUPPLY_HEALTH_GOOD; val 171 drivers/power/supply/sbs-charger.c int ret, val; val 191 drivers/power/supply/sbs-charger.c ret = regmap_read(chip->regmap, SBS_CHARGER_REG_STATUS, &val); val 196 drivers/power/supply/sbs-charger.c chip->last_state = val; val 94 drivers/power/supply/sbs-manager.c union power_supply_propval *val) val 104 drivers/power/supply/sbs-manager.c val->intval = !!(regval & SBSM_BIT_AC_PRESENT); val 113 drivers/power/supply/sbs-manager.c val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; val 116 drivers/power/supply/sbs-manager.c val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 124 drivers/power/supply/sbs-manager.c val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; val 145 drivers/power/supply/sbs-manager.c const union power_supply_propval *val) val 156 drivers/power/supply/sbs-manager.c regval = val->intval == val 94 drivers/power/supply/sc2731_charger.c u32 val; val 97 drivers/power/supply/sc2731_charger.c val = 0; val 99 drivers/power/supply/sc2731_charger.c val = 3; val 101 drivers/power/supply/sc2731_charger.c val = 2; val 103 drivers/power/supply/sc2731_charger.c val = 1; val 107 drivers/power/supply/sc2731_charger.c val << SC2731_CUR_LIMIT_SHIFT); val 112 drivers/power/supply/sc2731_charger.c u32 val; val 121 drivers/power/supply/sc2731_charger.c val = (cur - SC2731_CURRENT_PRECHG) / SC2731_CURRENT_STEP; val 131 drivers/power/supply/sc2731_charger.c SC2731_CUR_MASK, val); val 136 drivers/power/supply/sc2731_charger.c u32 val; val 139 drivers/power/supply/sc2731_charger.c ret = regmap_read(info->regmap, SC2731_CHARGE_STATUS, &val); val 143 drivers/power/supply/sc2731_charger.c if (val & SC2731_CHARGE_FULL) val 153 drivers/power/supply/sc2731_charger.c u32 val; val 155 drivers/power/supply/sc2731_charger.c ret = regmap_read(info->regmap, info->base + SC2731_CHG_CFG1, &val); val 159 drivers/power/supply/sc2731_charger.c val &= SC2731_CUR_MASK; val 160 drivers/power/supply/sc2731_charger.c *cur = val * SC2731_CURRENT_STEP + SC2731_CURRENT_PRECHG; val 169 drivers/power/supply/sc2731_charger.c u32 val; val 171 drivers/power/supply/sc2731_charger.c ret = regmap_read(info->regmap, info->base + SC2731_CHG_CFG5, &val); val 175 drivers/power/supply/sc2731_charger.c val = (val & SC2731_CUR_LIMIT_MASK) >> SC2731_CUR_LIMIT_SHIFT; val 177 drivers/power/supply/sc2731_charger.c switch (val) { val 204 drivers/power/supply/sc2731_charger.c const union power_supply_propval *val) val 218 drivers/power/supply/sc2731_charger.c ret = sc2731_charger_set_current(info, val->intval / 1000); val 225 drivers/power/supply/sc2731_charger.c val->intval / 1000); val 240 drivers/power/supply/sc2731_charger.c union power_supply_propval *val) val 251 drivers/power/supply/sc2731_charger.c val->intval = sc2731_charger_get_status(info); val 253 drivers/power/supply/sc2731_charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 258 drivers/power/supply/sc2731_charger.c val->intval = 0; val 264 drivers/power/supply/sc2731_charger.c val->intval = cur * 1000; val 270 drivers/power/supply/sc2731_charger.c val->intval = 0; val 276 drivers/power/supply/sc2731_charger.c val->intval = cur * 1000; val 401 drivers/power/supply/sc27xx_fuel_gauge.c static int sc27xx_fgu_get_vbat_vol(struct sc27xx_fgu_data *data, int *val) val 413 drivers/power/supply/sc27xx_fuel_gauge.c *val = sc27xx_fgu_adc_to_voltage(data, vol); val 418 drivers/power/supply/sc27xx_fuel_gauge.c static int sc27xx_fgu_get_current(struct sc27xx_fgu_data *data, int *val) val 430 drivers/power/supply/sc27xx_fuel_gauge.c *val = sc27xx_fgu_adc_to_current(data, cur - SC27XX_FGU_CUR_BASIC_ADC); val 435 drivers/power/supply/sc27xx_fuel_gauge.c static int sc27xx_fgu_get_vbat_ocv(struct sc27xx_fgu_data *data, int *val) val 448 drivers/power/supply/sc27xx_fuel_gauge.c *val = vol * 1000 - cur * data->internal_resist; val 453 drivers/power/supply/sc27xx_fuel_gauge.c static int sc27xx_fgu_get_charge_vol(struct sc27xx_fgu_data *data, int *val) val 461 drivers/power/supply/sc27xx_fuel_gauge.c *val = vol * 1000; val 488 drivers/power/supply/sc27xx_fuel_gauge.c union power_supply_propval val; val 498 drivers/power/supply/sc27xx_fuel_gauge.c &val); val 503 drivers/power/supply/sc27xx_fuel_gauge.c *status = val.intval; val 511 drivers/power/supply/sc27xx_fuel_gauge.c union power_supply_propval *val) val 525 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = value; val 533 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = value; val 537 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = data->bat_present; val 545 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = value; val 549 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 557 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = value; val 565 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = value * 1000; val 573 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = value; val 581 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = value; val 590 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = value * 1000; val 594 drivers/power/supply/sc27xx_fuel_gauge.c val->intval = data->total_cap * 1000; val 609 drivers/power/supply/sc27xx_fuel_gauge.c const union power_supply_propval *val) val 618 drivers/power/supply/sc27xx_fuel_gauge.c ret = sc27xx_fgu_save_last_cap(data, val->intval); val 624 drivers/power/supply/sc27xx_fuel_gauge.c sc27xx_fgu_adjust_cap(data, val->intval); val 203 drivers/power/supply/smb347-charger.c static int hw_to_current(const unsigned int *tbl, size_t size, unsigned int val) val 205 drivers/power/supply/smb347-charger.c if (val >= size) val 207 drivers/power/supply/smb347-charger.c return tbl[val]; val 211 drivers/power/supply/smb347-charger.c static int current_to_hw(const unsigned int *tbl, size_t size, unsigned int val) val 216 drivers/power/supply/smb347-charger.c if (val < tbl[i]) val 233 drivers/power/supply/smb347-charger.c unsigned int val; val 236 drivers/power/supply/smb347-charger.c ret = regmap_read(smb->regmap, IRQSTAT_E, &val); val 245 drivers/power/supply/smb347-charger.c dc = !(val & IRQSTAT_E_DCIN_UV_STAT); val 247 drivers/power/supply/smb347-charger.c usb = !(val & IRQSTAT_E_USBIN_UV_STAT); val 287 drivers/power/supply/smb347-charger.c unsigned int val; val 293 drivers/power/supply/smb347-charger.c ret = regmap_read(smb->regmap, STAT_C, &val); val 297 drivers/power/supply/smb347-charger.c return (val & STAT_C_CHG_MASK) >> STAT_C_CHG_SHIFT; val 467 drivers/power/supply/smb347-charger.c int val; val 470 drivers/power/supply/smb347-charger.c val = smb->pdata->chip_temp_threshold; val 473 drivers/power/supply/smb347-charger.c val = clamp_val(val, 100, 130) - 100; val 474 drivers/power/supply/smb347-charger.c val /= 10; val 478 drivers/power/supply/smb347-charger.c val << CFG_OTG_TEMP_THRESHOLD_SHIFT); val 484 drivers/power/supply/smb347-charger.c val = smb->pdata->soft_cold_temp_limit; val 486 drivers/power/supply/smb347-charger.c val = clamp_val(val, 0, 15); val 487 drivers/power/supply/smb347-charger.c val /= 5; val 489 drivers/power/supply/smb347-charger.c val = ~val & 0x3; val 493 drivers/power/supply/smb347-charger.c val << CFG_TEMP_LIMIT_SOFT_COLD_SHIFT); val 501 drivers/power/supply/smb347-charger.c val = smb->pdata->soft_hot_temp_limit; val 503 drivers/power/supply/smb347-charger.c val = clamp_val(val, 40, 55) - 40; val 504 drivers/power/supply/smb347-charger.c val /= 5; val 508 drivers/power/supply/smb347-charger.c val << CFG_TEMP_LIMIT_SOFT_HOT_SHIFT); val 516 drivers/power/supply/smb347-charger.c val = smb->pdata->hard_cold_temp_limit; val 518 drivers/power/supply/smb347-charger.c val = clamp_val(val, -5, 10) + 5; val 519 drivers/power/supply/smb347-charger.c val /= 5; val 521 drivers/power/supply/smb347-charger.c val = ~val & 0x3; val 525 drivers/power/supply/smb347-charger.c val << CFG_TEMP_LIMIT_HARD_COLD_SHIFT); val 533 drivers/power/supply/smb347-charger.c val = smb->pdata->hard_hot_temp_limit; val 535 drivers/power/supply/smb347-charger.c val = clamp_val(val, 50, 65) - 50; val 536 drivers/power/supply/smb347-charger.c val /= 5; val 540 drivers/power/supply/smb347-charger.c val << CFG_TEMP_LIMIT_HARD_HOT_SHIFT); val 573 drivers/power/supply/smb347-charger.c val = smb->pdata->soft_temp_limit_compensation & 0x3; val 577 drivers/power/supply/smb347-charger.c val << CFG_THERM_SOFT_HOT_COMPENSATION_SHIFT); val 583 drivers/power/supply/smb347-charger.c val << CFG_THERM_SOFT_COLD_COMPENSATION_SHIFT); val 589 drivers/power/supply/smb347-charger.c val = current_to_hw(ccc_tbl, ARRAY_SIZE(ccc_tbl), val 591 drivers/power/supply/smb347-charger.c if (val < 0) val 592 drivers/power/supply/smb347-charger.c return val; val 596 drivers/power/supply/smb347-charger.c (val & 0x3) << CFG_OTG_CC_COMPENSATION_SHIFT); val 621 drivers/power/supply/smb347-charger.c unsigned int val; val 673 drivers/power/supply/smb347-charger.c val = CFG_PIN_EN_CTRL_ACTIVE_LOW; val 676 drivers/power/supply/smb347-charger.c val = CFG_PIN_EN_CTRL_ACTIVE_HIGH; val 679 drivers/power/supply/smb347-charger.c val = 0; val 684 drivers/power/supply/smb347-charger.c val); val 933 drivers/power/supply/smb347-charger.c union power_supply_propval *val) val 940 drivers/power/supply/smb347-charger.c val->intval = smb->mains_online; val 948 drivers/power/supply/smb347-charger.c val->intval = ret; val 956 drivers/power/supply/smb347-charger.c val->intval = ret; val 974 drivers/power/supply/smb347-charger.c union power_supply_propval *val) val 981 drivers/power/supply/smb347-charger.c val->intval = smb->usb_online; val 989 drivers/power/supply/smb347-charger.c val->intval = ret; val 997 drivers/power/supply/smb347-charger.c val->intval = ret; val 1016 drivers/power/supply/smb347-charger.c unsigned int val; val 1021 drivers/power/supply/smb347-charger.c ret = regmap_read(smb->regmap, STAT_C, &val); val 1025 drivers/power/supply/smb347-charger.c if ((val & STAT_C_CHARGER_ERROR) || val 1026 drivers/power/supply/smb347-charger.c (val & STAT_C_HOLDOFF_STAT)) { val 1033 drivers/power/supply/smb347-charger.c if ((val & STAT_C_CHG_MASK) >> STAT_C_CHG_SHIFT) { val 1039 drivers/power/supply/smb347-charger.c } else if (val & STAT_C_CHG_TERM) { val 1060 drivers/power/supply/smb347-charger.c union power_supply_propval *val) val 1075 drivers/power/supply/smb347-charger.c val->intval = ret; val 1088 drivers/power/supply/smb347-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; val 1091 drivers/power/supply/smb347-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; val 1094 drivers/power/supply/smb347-charger.c val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; val 1100 drivers/power/supply/smb347-charger.c val->intval = pdata->battery_info.technology; val 1104 drivers/power/supply/smb347-charger.c val->intval = pdata->battery_info.voltage_min_design; val 1108 drivers/power/supply/smb347-charger.c val->intval = pdata->battery_info.voltage_max_design; val 1112 drivers/power/supply/smb347-charger.c val->intval = pdata->battery_info.charge_full_design; val 1116 drivers/power/supply/smb347-charger.c val->strval = pdata->battery_info.name; val 41 drivers/power/supply/test_power.c union power_supply_propval *val) val 45 drivers/power/supply/test_power.c val->intval = ac_online; val 55 drivers/power/supply/test_power.c union power_supply_propval *val) val 59 drivers/power/supply/test_power.c val->intval = usb_online; val 69 drivers/power/supply/test_power.c union power_supply_propval *val) val 73 drivers/power/supply/test_power.c val->strval = "Test battery"; val 76 drivers/power/supply/test_power.c val->strval = "Linux"; val 79 drivers/power/supply/test_power.c val->strval = UTS_RELEASE; val 82 drivers/power/supply/test_power.c val->intval = battery_status; val 85 drivers/power/supply/test_power.c val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; val 88 drivers/power/supply/test_power.c val->intval = battery_health; val 91 drivers/power/supply/test_power.c val->intval = battery_present; val 94 drivers/power/supply/test_power.c val->intval = battery_technology; val 97 drivers/power/supply/test_power.c val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; val 101 drivers/power/supply/test_power.c val->intval = battery_capacity; val 105 drivers/power/supply/test_power.c val->intval = 100; val 109 drivers/power/supply/test_power.c val->intval = 3600; val 112 drivers/power/supply/test_power.c val->intval = 26; val 115 drivers/power/supply/test_power.c val->intval = battery_voltage; val 92 drivers/power/supply/tosa_battery.c union power_supply_propval *val) val 104 drivers/power/supply/tosa_battery.c val->intval = bat->status; val 107 drivers/power/supply/tosa_battery.c val->intval = bat->technology; val 110 drivers/power/supply/tosa_battery.c val->intval = tosa_read_bat(bat); val 114 drivers/power/supply/tosa_battery.c val->intval = bat->bat_max; val 116 drivers/power/supply/tosa_battery.c val->intval = bat->full_chrg; val 119 drivers/power/supply/tosa_battery.c val->intval = bat->bat_max; val 122 drivers/power/supply/tosa_battery.c val->intval = bat->bat_min; val 125 drivers/power/supply/tosa_battery.c val->intval = tosa_read_temp(bat); val 128 drivers/power/supply/tosa_battery.c val->intval = bat->is_present ? bat->is_present(bat) : 1; val 126 drivers/power/supply/tps65090-charger.c union power_supply_propval *val) val 131 drivers/power/supply/tps65090-charger.c val->intval = charger->ac_online; val 106 drivers/power/supply/tps65217_charger.c union power_supply_propval *val) val 111 drivers/power/supply/tps65217_charger.c val->intval = charger->online; val 119 drivers/power/supply/tps65217_charger.c int ret, val; val 124 drivers/power/supply/tps65217_charger.c ret = tps65217_reg_read(charger->tps, TPS65217_REG_STATUS, &val); val 131 drivers/power/supply/tps65217_charger.c dev_dbg(charger->dev, "%s: 0x%x\n", __func__, val); val 134 drivers/power/supply/tps65217_charger.c if (val & CHARGER_STATUS_PRESENT) { val 148 drivers/power/supply/tps65217_charger.c ret = tps65217_reg_read(charger->tps, TPS65217_REG_CHGCONFIG0, &val); val 155 drivers/power/supply/tps65217_charger.c if (val & TPS65217_CHGCONFIG0_ACTIVE) val 96 drivers/power/supply/twl4030_charger.c int val, err; val 101 drivers/power/supply/twl4030_charger.c err = iio_read_channel_processed(channel_vac, &val); val 104 drivers/power/supply/twl4030_charger.c return val > 4500; val 159 drivers/power/supply/twl4030_charger.c u8 val = 0; val 162 drivers/power/supply/twl4030_charger.c ret = twl_i2c_read_u8(mod_no, &val, reg); val 166 drivers/power/supply/twl4030_charger.c val &= ~clear; val 167 drivers/power/supply/twl4030_charger.c val |= set; val 169 drivers/power/supply/twl4030_charger.c return twl_i2c_write_u8(mod_no, val, reg); val 172 drivers/power/supply/twl4030_charger.c static int twl4030_bci_read(u8 reg, u8 *val) val 174 drivers/power/supply/twl4030_charger.c return twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, val, reg); val 187 drivers/power/supply/twl4030_charger.c u8 val; val 190 drivers/power/supply/twl4030_charger.c ret = twl4030_bci_read(reg + 1, &val); val 194 drivers/power/supply/twl4030_charger.c temp = (int)(val & 0x03) << 8; val 197 drivers/power/supply/twl4030_charger.c ret = twl4030_bci_read(reg, &val); val 201 drivers/power/supply/twl4030_charger.c return temp | val; val 664 drivers/power/supply/twl4030_charger.c static int twl4030_bci_usb_ncb(struct notifier_block *nb, unsigned long val, val 669 drivers/power/supply/twl4030_charger.c dev_dbg(bci->dev, "OTG notify %lu\n", val); val 677 drivers/power/supply/twl4030_charger.c bci->event = val; val 791 drivers/power/supply/twl4030_charger.c union power_supply_propval *val) val 823 drivers/power/supply/twl4030_charger.c val->intval = twl4030_bci_state_to_status(state); val 825 drivers/power/supply/twl4030_charger.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 836 drivers/power/supply/twl4030_charger.c val->intval = ret * 6843; val 842 drivers/power/supply/twl4030_charger.c val->intval = ret * 9775; val 852 drivers/power/supply/twl4030_charger.c val->intval = ret; val 855 drivers/power/supply/twl4030_charger.c val->intval = is_charging && val 860 drivers/power/supply/twl4030_charger.c val->intval = -1; val 863 drivers/power/supply/twl4030_charger.c val->intval = bci->ac_cur; val 866 drivers/power/supply/twl4030_charger.c val->intval = bci->usb_cur_target; val 868 drivers/power/supply/twl4030_charger.c if (val->intval < 0) { val 871 drivers/power/supply/twl4030_charger.c val->intval = twl4030bci_read_adc_val(TWL4030_BCIIREF1); val 872 drivers/power/supply/twl4030_charger.c if (val->intval < 0) val 873 drivers/power/supply/twl4030_charger.c return val->intval; val 877 drivers/power/supply/twl4030_charger.c val->intval = regval2ua(val->intval, bcictl1 & val 890 drivers/power/supply/twl4030_charger.c const union power_supply_propval *val) val 897 drivers/power/supply/twl4030_charger.c bci->usb_cur_target = val->intval; val 899 drivers/power/supply/twl4030_charger.c bci->ac_cur = val->intval; val 47 drivers/power/supply/twl4030_madc_battery.c int val, err; val 48 drivers/power/supply/twl4030_madc_battery.c err = iio_read_channel_processed(channel, &val); val 52 drivers/power/supply/twl4030_madc_battery.c return val; val 109 drivers/power/supply/twl4030_madc_battery.c union power_supply_propval *val) val 117 drivers/power/supply/twl4030_madc_battery.c val->intval = POWER_SUPPLY_STATUS_FULL; val 120 drivers/power/supply/twl4030_madc_battery.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 122 drivers/power/supply/twl4030_madc_battery.c val->intval = POWER_SUPPLY_STATUS_DISCHARGING; val 126 drivers/power/supply/twl4030_madc_battery.c val->intval = twl4030_madc_bat_get_voltage(bat) * 1000; val 129 drivers/power/supply/twl4030_madc_battery.c val->intval = POWER_SUPPLY_TECHNOLOGY_LION; val 132 drivers/power/supply/twl4030_madc_battery.c val->intval = twl4030_madc_bat_get_current(bat); val 136 drivers/power/supply/twl4030_madc_battery.c val->intval = 1; val 141 drivers/power/supply/twl4030_madc_battery.c val->intval = (percent * bat->pdata->capacity) / 100; val 145 drivers/power/supply/twl4030_madc_battery.c val->intval = twl4030_madc_bat_voltscale(bat, val 149 drivers/power/supply/twl4030_madc_battery.c val->intval = bat->pdata->capacity; val 152 drivers/power/supply/twl4030_madc_battery.c val->intval = twl4030_madc_bat_get_temp(bat); val 161 drivers/power/supply/twl4030_madc_battery.c val->intval = (3600l * chg) / 400; val 118 drivers/power/supply/ucs1002_power.c union power_supply_propval *val) val 127 drivers/power/supply/ucs1002_power.c val->intval = !!(reg & F_CHG_ACT); val 133 drivers/power/supply/ucs1002_power.c union power_supply_propval *val) val 186 drivers/power/supply/ucs1002_power.c val->intval = 0; val 189 drivers/power/supply/ucs1002_power.c val->intval += bit_weights_uAh[i]; val 195 drivers/power/supply/ucs1002_power.c union power_supply_propval *val) val 214 drivers/power/supply/ucs1002_power.c val->intval = 0; val 217 drivers/power/supply/ucs1002_power.c val->intval += bit_weights_uA[i]; val 231 drivers/power/supply/ucs1002_power.c union power_supply_propval *val) val 240 drivers/power/supply/ucs1002_power.c val->intval = ucs1002_current_limit_uA[reg & UCS1002_ILIM_SW_MASK]; val 245 drivers/power/supply/ucs1002_power.c static int ucs1002_set_max_current(struct ucs1002_info *info, u32 val) val 251 drivers/power/supply/ucs1002_power.c if (val == ucs1002_current_limit_uA[idx]) val 284 drivers/power/supply/ucs1002_power.c static int ucs1002_set_usb_type(struct ucs1002_info *info, int val) val 288 drivers/power/supply/ucs1002_power.c if (val < 0 || val >= ARRAY_SIZE(ucs1002_usb_types)) val 291 drivers/power/supply/ucs1002_power.c switch (ucs1002_usb_types[val]) { val 313 drivers/power/supply/ucs1002_power.c union power_supply_propval *val) val 341 drivers/power/supply/ucs1002_power.c val->intval = type; val 347 drivers/power/supply/ucs1002_power.c union power_supply_propval *val) val 367 drivers/power/supply/ucs1002_power.c val->intval = health; val 374 drivers/power/supply/ucs1002_power.c union power_supply_propval *val) val 380 drivers/power/supply/ucs1002_power.c return ucs1002_get_online(info, val); val 382 drivers/power/supply/ucs1002_power.c return ucs1002_get_charge(info, val); val 384 drivers/power/supply/ucs1002_power.c return ucs1002_get_current(info, val); val 386 drivers/power/supply/ucs1002_power.c return ucs1002_get_max_current(info, val); val 388 drivers/power/supply/ucs1002_power.c return ucs1002_get_usb_type(info, val); val 390 drivers/power/supply/ucs1002_power.c return ucs1002_get_health(info, val); val 392 drivers/power/supply/ucs1002_power.c val->intval = info->present; val 395 drivers/power/supply/ucs1002_power.c val->strval = UCS1002_MANUFACTURER; val 404 drivers/power/supply/ucs1002_power.c const union power_supply_propval *val) val 410 drivers/power/supply/ucs1002_power.c return ucs1002_set_max_current(info, val->intval); val 412 drivers/power/supply/ucs1002_power.c return ucs1002_set_usb_type(info, val->intval); val 83 drivers/power/supply/wilco-charger.c union power_supply_propval *val) val 113 drivers/power/supply/wilco-charger.c val->intval = raw; val 120 drivers/power/supply/wilco-charger.c const union power_supply_propval *val) val 127 drivers/power/supply/wilco-charger.c mode = psp_val_to_charge_mode(val->intval); val 132 drivers/power/supply/wilco-charger.c if (val->intval < CHARGE_LOWER_LIMIT_MIN || val 133 drivers/power/supply/wilco-charger.c val->intval > CHARGE_LOWER_LIMIT_MAX) val 136 drivers/power/supply/wilco-charger.c val->intval); val 138 drivers/power/supply/wilco-charger.c if (val->intval < CHARGE_UPPER_LIMIT_MIN || val 139 drivers/power/supply/wilco-charger.c val->intval > CHARGE_UPPER_LIMIT_MAX) val 142 drivers/power/supply/wilco-charger.c val->intval); val 28 drivers/power/supply/wm831x_backup.c union power_supply_propval *val) val 34 drivers/power/supply/wm831x_backup.c val->intval = ret; val 114 drivers/power/supply/wm831x_backup.c union power_supply_propval *val) val 127 drivers/power/supply/wm831x_backup.c val->intval = POWER_SUPPLY_STATUS_CHARGING; val 129 drivers/power/supply/wm831x_backup.c val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; val 134 drivers/power/supply/wm831x_backup.c val); val 139 drivers/power/supply/wm831x_backup.c val->intval = 1; val 141 drivers/power/supply/wm831x_backup.c val->intval = 0; val 37 drivers/power/supply/wm831x_power.c union power_supply_propval *val) val 46 drivers/power/supply/wm831x_power.c val->intval = 1; val 48 drivers/power/supply/wm831x_power.c val->intval = 0; val 55 drivers/power/supply/wm831x_power.c union power_supply_propval *val) val 61 drivers/power/supply/wm831x_power.c val->intval = ret; val 71 drivers/power/supply/wm831x_power.c union power_supply_propval *val) val 79 drivers/power/supply/wm831x_power.c ret = wm831x_power_check_online(wm831x, WM831X_PWR_WALL, val); val 82 drivers/power/supply/wm831x_power.c ret = wm831x_power_read_voltage(wm831x, WM831X_AUX_WALL, val); val 102 drivers/power/supply/wm831x_power.c union power_supply_propval *val) val 110 drivers/power/supply/wm831x_power.c ret = wm831x_power_check_online(wm831x, WM831X_PWR_USB, val); val 113 drivers/power/supply/wm831x_power.c ret = wm831x_power_read_voltage(wm831x, WM831X_AUX_USB, val); val 170 drivers/power/supply/wm831x_power.c int val; val 238 drivers/power/supply/wm831x_power.c struct chg_map *map, int count, int val, val 245 drivers/power/supply/wm831x_power.c if (val == map[i].val) val 249 drivers/power/supply/wm831x_power.c name, val, units); val 252 drivers/power/supply/wm831x_power.c dev_dbg(wm831x->dev, "Set %s of %d%s\n", name, val, units); val 434 drivers/power/supply/wm831x_power.c union power_supply_propval *val) val 442 drivers/power/supply/wm831x_power.c ret = wm831x_bat_check_status(wm831x, &val->intval); val 446 drivers/power/supply/wm831x_power.c val); val 449 drivers/power/supply/wm831x_power.c ret = wm831x_power_read_voltage(wm831x, WM831X_AUX_BATT, val); val 452 drivers/power/supply/wm831x_power.c ret = wm831x_bat_check_health(wm831x, &val->intval); val 455 drivers/power/supply/wm831x_power.c ret = wm831x_bat_check_type(wm831x, &val->intval); val 249 drivers/power/supply/wm8350_power.c union power_supply_propval *val) val 256 drivers/power/supply/wm8350_power.c val->intval = !!(wm8350_get_supplies(wm8350) & val 260 drivers/power/supply/wm8350_power.c val->intval = wm8350_read_line_uvolts(wm8350); val 279 drivers/power/supply/wm8350_power.c union power_supply_propval *val) val 286 drivers/power/supply/wm8350_power.c val->intval = !!(wm8350_get_supplies(wm8350) & val 290 drivers/power/supply/wm8350_power.c val->intval = wm8350_read_usb_uvolts(wm8350); val 345 drivers/power/supply/wm8350_power.c union power_supply_propval *val) val 352 drivers/power/supply/wm8350_power.c val->intval = wm8350_batt_status(wm8350); val 355 drivers/power/supply/wm8350_power.c val->intval = !!(wm8350_get_supplies(wm8350) & val 359 drivers/power/supply/wm8350_power.c val->intval = wm8350_read_battery_uvolts(wm8350); val 362 drivers/power/supply/wm8350_power.c val->intval = wm8350_bat_check_health(wm8350); val 365 drivers/power/supply/wm8350_power.c val->intval = wm8350_bat_get_charge_type(wm8350); val 47 drivers/power/supply/wm97xx_battery.c union power_supply_propval *val) val 53 drivers/power/supply/wm97xx_battery.c val->intval = bat_status; val 56 drivers/power/supply/wm97xx_battery.c val->intval = pdata->batt_tech; val 60 drivers/power/supply/wm97xx_battery.c val->intval = wm97xx_read_bat(bat_ps); val 66 drivers/power/supply/wm97xx_battery.c val->intval = wm97xx_read_temp(bat_ps); val 72 drivers/power/supply/wm97xx_battery.c val->intval = pdata->max_voltage; val 78 drivers/power/supply/wm97xx_battery.c val->intval = pdata->min_voltage; val 83 drivers/power/supply/wm97xx_battery.c val->intval = 1; val 42 drivers/power/supply/z2_battery.c union power_supply_propval *val) val 49 drivers/power/supply/z2_battery.c val->intval = charger->bat_status; val 52 drivers/power/supply/z2_battery.c val->intval = info->batt_tech; val 56 drivers/power/supply/z2_battery.c val->intval = z2_read_bat(charger); val 62 drivers/power/supply/z2_battery.c val->intval = info->max_voltage; val 68 drivers/power/supply/z2_battery.c val->intval = info->min_voltage; val 73 drivers/power/supply/z2_battery.c val->intval = 1; val 96 drivers/powercap/intel_rapl_common.c u64 (*compute_time_window)(struct rapl_package *rp, u64 val, val 230 drivers/powercap/intel_rapl_common.c u64 val; val 237 drivers/powercap/intel_rapl_common.c if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) { val 241 drivers/powercap/intel_rapl_common.c *mode = val; val 357 drivers/powercap/intel_rapl_common.c u64 val; val 381 drivers/powercap/intel_rapl_common.c if (rapl_read_data_raw(rd, prim, true, &val)) val 384 drivers/powercap/intel_rapl_common.c *data = val; val 427 drivers/powercap/intel_rapl_common.c u64 val; val 441 drivers/powercap/intel_rapl_common.c ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val); val 444 drivers/powercap/intel_rapl_common.c ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val); val 451 drivers/powercap/intel_rapl_common.c *data = val; val 476 drivers/powercap/intel_rapl_common.c u64 val; val 493 drivers/powercap/intel_rapl_common.c if (rapl_read_data_raw(rd, prim, true, &val)) val 496 drivers/powercap/intel_rapl_common.c *data = val; val 1002 drivers/powercap/intel_rapl_common.c u64 val; val 1010 drivers/powercap/intel_rapl_common.c rpi[prim].unit, &val)) val 1011 drivers/powercap/intel_rapl_common.c rp->domains[dmn].rdd.primitives[prim] = val; val 103 drivers/powercap/intel_rapl_msr.c u64 val; val 105 drivers/powercap/intel_rapl_msr.c ra->err = rdmsrl_safe(msr, &val); val 109 drivers/powercap/intel_rapl_msr.c val &= ~ra->mask; val 110 drivers/powercap/intel_rapl_msr.c val |= ra->value; val 112 drivers/powercap/intel_rapl_msr.c ra->err = wrmsrl_safe(msr, val); val 242 drivers/ps3/ps3-lpm.c void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val) val 258 drivers/ps3/ps3-lpm.c counter0415 = (u64)val << 32; val 264 drivers/ps3/ps3-lpm.c counter0415 = (u64)val; val 272 drivers/ps3/ps3-lpm.c counter2637 = (u64)val << 32; val 278 drivers/ps3/ps3-lpm.c counter2637 = (u64)val; val 292 drivers/ps3/ps3-lpm.c phys_ctr, val, ps3_result(result)); val 305 drivers/ps3/ps3-lpm.c u32 val; val 308 drivers/ps3/ps3-lpm.c val = ps3_read_phys_ctr(cpu, phys_ctr); val 311 drivers/ps3/ps3-lpm.c val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff); val 313 drivers/ps3/ps3-lpm.c return val; val 324 drivers/ps3/ps3-lpm.c void ps3_write_ctr(u32 cpu, u32 ctr, u32 val) val 335 drivers/ps3/ps3-lpm.c val = (val << 16) | (phys_val & 0xffff); val 337 drivers/ps3/ps3-lpm.c val = (val & 0xffff) | (phys_val & 0xffff0000); val 340 drivers/ps3/ps3-lpm.c ps3_write_phys_ctr(cpu, phys_ctr, val); val 362 drivers/ps3/ps3-lpm.c void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val) val 374 drivers/ps3/ps3-lpm.c result = lv1_set_lpm_counter_control(lpm_priv->lpm_id, ctr, val, mask, val 390 drivers/ps3/ps3-lpm.c u64 val = 0; val 400 drivers/ps3/ps3-lpm.c result = lv1_set_lpm_interval(lpm_priv->lpm_id, 0, 0, &val); val 402 drivers/ps3/ps3-lpm.c val = 0; val 407 drivers/ps3/ps3-lpm.c return (u32)val; val 414 drivers/ps3/ps3-lpm.c &val); val 416 drivers/ps3/ps3-lpm.c val = 0; val 421 drivers/ps3/ps3-lpm.c return (u32)val; val 439 drivers/ps3/ps3-lpm.c void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val) val 446 drivers/ps3/ps3-lpm.c if (val != lpm_priv->shadow.group_control) val 448 drivers/ps3/ps3-lpm.c val, val 451 drivers/ps3/ps3-lpm.c lpm_priv->shadow.group_control = val; val 454 drivers/ps3/ps3-lpm.c if (val != lpm_priv->shadow.debug_bus_control) val 456 drivers/ps3/ps3-lpm.c val, val 459 drivers/ps3/ps3-lpm.c lpm_priv->shadow.debug_bus_control = val; val 463 drivers/ps3/ps3-lpm.c val |= (PS3_PM_CONTROL_PPU_TH0_BOOKMARK | val 465 drivers/ps3/ps3-lpm.c if (val != lpm_priv->shadow.pm_control) val 467 drivers/ps3/ps3-lpm.c val, val 471 drivers/ps3/ps3-lpm.c lpm_priv->shadow.pm_control = val; val 474 drivers/ps3/ps3-lpm.c result = lv1_set_lpm_interval(lpm_priv->lpm_id, val, val 478 drivers/ps3/ps3-lpm.c if (val != lpm_priv->shadow.pm_start_stop) val 480 drivers/ps3/ps3-lpm.c val, val 483 drivers/ps3/ps3-lpm.c lpm_priv->shadow.pm_start_stop = val; val 147 drivers/ps3/ps3-vuart.c u64 val; val 170 drivers/ps3/ps3-vuart.c PARAM_RX_TRIGGER, &val); val 178 drivers/ps3/ps3-vuart.c trig->rx = size - val; val 77 drivers/ptp/ptp_ixp46x.c u32 ack = 0, lo, hi, val; val 79 drivers/ptp/ptp_ixp46x.c val = __raw_readl(®s->event); val 81 drivers/ptp/ptp_ixp46x.c if (val & TSER_SNS) { val 95 drivers/ptp/ptp_ixp46x.c if (val & TSER_SNM) { val 109 drivers/ptp/ptp_ixp46x.c if (val & TTIPEND) val 139 drivers/ptp/ptp_pch.c u32 val; val 141 drivers/ptp/ptp_pch.c val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH); val 142 drivers/ptp/ptp_pch.c iowrite32(val, (&chip->regs->ts_sel)); val 174 drivers/ptp/ptp_pch.c u32 val; val 176 drivers/ptp/ptp_pch.c val = ioread32(&chip->regs->control) | PCH_TSC_RESET; val 177 drivers/ptp/ptp_pch.c iowrite32(val, (&chip->regs->control)); val 178 drivers/ptp/ptp_pch.c val = val & ~PCH_TSC_RESET; val 179 drivers/ptp/ptp_pch.c iowrite32(val, (&chip->regs->control)); val 185 drivers/ptp/ptp_pch.c u32 val; val 187 drivers/ptp/ptp_pch.c val = ioread32(&chip->regs->ch_control); val 189 drivers/ptp/ptp_pch.c return val; val 193 drivers/ptp/ptp_pch.c void pch_ch_control_write(struct pci_dev *pdev, u32 val) val 197 drivers/ptp/ptp_pch.c iowrite32(val, (&chip->regs->ch_control)); val 204 drivers/ptp/ptp_pch.c u32 val; val 206 drivers/ptp/ptp_pch.c val = ioread32(&chip->regs->ch_event); val 208 drivers/ptp/ptp_pch.c return val; val 212 drivers/ptp/ptp_pch.c void pch_ch_event_write(struct pci_dev *pdev, u32 val) val 216 drivers/ptp/ptp_pch.c iowrite32(val, (&chip->regs->ch_event)); val 223 drivers/ptp/ptp_pch.c u32 val; val 225 drivers/ptp/ptp_pch.c val = ioread32(&chip->regs->src_uuid_lo); val 227 drivers/ptp/ptp_pch.c return val; val 234 drivers/ptp/ptp_pch.c u32 val; val 236 drivers/ptp/ptp_pch.c val = ioread32(&chip->regs->src_uuid_hi); val 238 drivers/ptp/ptp_pch.c return val; val 313 drivers/ptp/ptp_pch.c u32 val; val 322 drivers/ptp/ptp_pch.c val = tmp * 16; val 329 drivers/ptp/ptp_pch.c val += tmp; val 340 drivers/ptp/ptp_pch.c iowrite32(val, &chip->regs->ts_st[i]); val 354 drivers/ptp/ptp_pch.c u32 ack = 0, lo, hi, val; val 356 drivers/ptp/ptp_pch.c val = ioread32(®s->event); val 358 drivers/ptp/ptp_pch.c if (val & PCH_TSE_SNS) { val 372 drivers/ptp/ptp_pch.c if (val & PCH_TSE_SNM) { val 386 drivers/ptp/ptp_pch.c if (val & PCH_TSE_TTIPEND) val 130 drivers/ptp/ptp_qoriq.c u32 ack = 0, lo, hi, mask, val, irqs; val 134 drivers/ptp/ptp_qoriq.c val = ptp_qoriq->read(®s->ctrl_regs->tmr_tevent); val 139 drivers/ptp/ptp_qoriq.c irqs = val & mask; val 8 drivers/ptp/ptp_qoriq_debugfs.c static int ptp_qoriq_fiper1_lpbk_get(void *data, u64 *val) val 15 drivers/ptp/ptp_qoriq_debugfs.c *val = ctrl & PP1L ? 1 : 0; val 20 drivers/ptp/ptp_qoriq_debugfs.c static int ptp_qoriq_fiper1_lpbk_set(void *data, u64 val) val 27 drivers/ptp/ptp_qoriq_debugfs.c if (val == 0) val 39 drivers/ptp/ptp_qoriq_debugfs.c static int ptp_qoriq_fiper2_lpbk_get(void *data, u64 *val) val 46 drivers/ptp/ptp_qoriq_debugfs.c *val = ctrl & PP2L ? 1 : 0; val 51 drivers/ptp/ptp_qoriq_debugfs.c static int ptp_qoriq_fiper2_lpbk_set(void *data, u64 val) val 58 drivers/ptp/ptp_qoriq_debugfs.c if (val == 0) val 90 drivers/pwm/pwm-atmel.c unsigned long offset, unsigned long val) val 92 drivers/pwm/pwm-atmel.c writel_relaxed(val, chip->base + offset); val 105 drivers/pwm/pwm-atmel.c unsigned long val) val 109 drivers/pwm/pwm-atmel.c writel_relaxed(val, chip->base + base + offset); val 150 drivers/pwm/pwm-atmel.c u32 val; val 154 drivers/pwm/pwm-atmel.c val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); val 155 drivers/pwm/pwm-atmel.c val &= ~PWM_CMR_UPD_CDTY; val 156 drivers/pwm/pwm-atmel.c atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); val 217 drivers/pwm/pwm-atmel.c u32 pres, val; val 254 drivers/pwm/pwm-atmel.c val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); val 255 drivers/pwm/pwm-atmel.c val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); val 257 drivers/pwm/pwm-atmel.c val &= ~PWM_CMR_CPOL; val 259 drivers/pwm/pwm-atmel.c val |= PWM_CMR_CPOL; val 260 drivers/pwm/pwm-atmel.c atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); val 115 drivers/pwm/pwm-bcm-kona.c u64 val, div, rate; val 135 drivers/pwm/pwm-bcm-kona.c val = rate * period_ns; val 136 drivers/pwm/pwm-bcm-kona.c pc = div64_u64(val, div); val 137 drivers/pwm/pwm-bcm-kona.c val = rate * duty_ns; val 138 drivers/pwm/pwm-bcm-kona.c dc = div64_u64(val, div); val 64 drivers/pwm/pwm-fsl-ftm.c u32 val; val 66 drivers/pwm/pwm-fsl-ftm.c regmap_read(fpc->regmap, FTM_FMS, &val); val 67 drivers/pwm/pwm-fsl-ftm.c if (val & FTM_FMS_WPEN) val 207 drivers/pwm/pwm-fsl-ftm.c u32 val; val 209 drivers/pwm/pwm-fsl-ftm.c regmap_read(fpc->regmap, FTM_OUTMASK, &val); val 210 drivers/pwm/pwm-fsl-ftm.c if (~val & 0xFF) val 219 drivers/pwm/pwm-fsl-ftm.c u32 val; val 221 drivers/pwm/pwm-fsl-ftm.c regmap_read(fpc->regmap, FTM_OUTMASK, &val); val 222 drivers/pwm/pwm-fsl-ftm.c if (~(val | BIT(pwm->hwpwm)) & 0xFF) val 81 drivers/pwm/pwm-img.c u32 reg, u32 val) val 83 drivers/pwm/pwm-img.c writel(val, chip->base + reg); val 95 drivers/pwm/pwm-img.c u32 val, div, duty, timebase; val 135 drivers/pwm/pwm-img.c val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); val 136 drivers/pwm/pwm-img.c val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm)); val 137 drivers/pwm/pwm-img.c val |= (div & PWM_CTRL_CFG_DIV_MASK) << val 139 drivers/pwm/pwm-img.c img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); val 141 drivers/pwm/pwm-img.c val = (duty << PWM_CH_CFG_DUTY_SHIFT) | val 143 drivers/pwm/pwm-img.c img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val); val 153 drivers/pwm/pwm-img.c u32 val; val 161 drivers/pwm/pwm-img.c val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); val 162 drivers/pwm/pwm-img.c val |= BIT(pwm->hwpwm); val 163 drivers/pwm/pwm-img.c img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); val 174 drivers/pwm/pwm-img.c u32 val; val 177 drivers/pwm/pwm-img.c val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); val 178 drivers/pwm/pwm-img.c val &= ~BIT(pwm->hwpwm); val 179 drivers/pwm/pwm-img.c img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); val 239 drivers/pwm/pwm-img.c u64 val; val 295 drivers/pwm/pwm-img.c val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase; val 296 drivers/pwm/pwm-img.c do_div(val, clk_rate); val 297 drivers/pwm/pwm-img.c pwm->max_period_ns = val; val 299 drivers/pwm/pwm-img.c val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS; val 300 drivers/pwm/pwm-img.c do_div(val, clk_rate); val 301 drivers/pwm/pwm-img.c pwm->min_period_ns = val; val 329 drivers/pwm/pwm-img.c u32 val; val 338 drivers/pwm/pwm-img.c val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); val 339 drivers/pwm/pwm-img.c val &= ~BIT(i); val 340 drivers/pwm/pwm-img.c img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); val 74 drivers/pwm/pwm-imx-tpm.c u32 val; val 129 drivers/pwm/pwm-imx-tpm.c p->val = DIV_ROUND_CLOSEST_ULL(tmp, real_state->period); val 142 drivers/pwm/pwm-imx-tpm.c u32 rate, val, prescale; val 150 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_SC); val 151 drivers/pwm/pwm-imx-tpm.c prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val); val 157 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); val 158 drivers/pwm/pwm-imx-tpm.c if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED) val 168 drivers/pwm/pwm-imx-tpm.c state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false; val 180 drivers/pwm/pwm-imx-tpm.c u32 val, cmod, cur_prescale; val 194 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_SC); val 195 drivers/pwm/pwm-imx-tpm.c cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val); val 196 drivers/pwm/pwm-imx-tpm.c cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val); val 201 drivers/pwm/pwm-imx-tpm.c val &= ~PWM_IMX_TPM_SC_PS; val 202 drivers/pwm/pwm-imx-tpm.c val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale); val 203 drivers/pwm/pwm-imx-tpm.c writel(val, tpm->base + PWM_IMX_TPM_SC); val 233 drivers/pwm/pwm-imx-tpm.c writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); val 243 drivers/pwm/pwm-imx-tpm.c != p->val) { val 256 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); val 257 drivers/pwm/pwm-imx-tpm.c val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA | val 267 drivers/pwm/pwm-imx-tpm.c val |= PWM_IMX_TPM_CnSC_MSB; val 268 drivers/pwm/pwm-imx-tpm.c val |= (state->polarity == PWM_POLARITY_NORMAL) ? val 272 drivers/pwm/pwm-imx-tpm.c writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); val 276 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_SC); val 279 drivers/pwm/pwm-imx-tpm.c val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK; val 282 drivers/pwm/pwm-imx-tpm.c val &= ~PWM_IMX_TPM_SC_CMOD; val 284 drivers/pwm/pwm-imx-tpm.c writel(val, tpm->base + PWM_IMX_TPM_SC); val 342 drivers/pwm/pwm-imx-tpm.c u32 val; val 377 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_PARAM); val 378 drivers/pwm/pwm-imx-tpm.c tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val); val 122 drivers/pwm/pwm-imx27.c u32 period, prescaler, pwm_clk, val; val 130 drivers/pwm/pwm-imx27.c val = readl(imx->mmio_base + MX3_PWMCR); val 132 drivers/pwm/pwm-imx27.c if (val & MX3_PWMCR_EN) val 137 drivers/pwm/pwm-imx27.c switch (FIELD_GET(MX3_PWMCR_POUTC, val)) { val 148 drivers/pwm/pwm-imx27.c prescaler = MX3_PWMCR_PRESCALER_GET(val); val 151 drivers/pwm/pwm-imx27.c val = readl(imx->mmio_base + MX3_PWMPR); val 152 drivers/pwm/pwm-imx27.c period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val; val 160 drivers/pwm/pwm-imx27.c val = readl(imx->mmio_base + MX3_PWMSAR); val 161 drivers/pwm/pwm-imx27.c tmp = NSEC_PER_SEC * (u64)(val); val 100 drivers/pwm/pwm-lp3943.c u8 val, reg_duty, reg_prescale; val 122 drivers/pwm/pwm-lp3943.c val = (u8)(period_ns / LP3943_MIN_PERIOD - 1); val 124 drivers/pwm/pwm-lp3943.c err = lp3943_write_byte(lp3943, reg_prescale, val); val 128 drivers/pwm/pwm-lp3943.c val = (u8)(duty_ns * LP3943_MAX_DUTY / period_ns); val 130 drivers/pwm/pwm-lp3943.c return lp3943_write_byte(lp3943, reg_duty, val); val 135 drivers/pwm/pwm-lp3943.c u8 val) val 145 drivers/pwm/pwm-lp3943.c val << mux[index].shift); val 157 drivers/pwm/pwm-lp3943.c u8 val; val 160 drivers/pwm/pwm-lp3943.c val = LP3943_DIM_PWM0; val 162 drivers/pwm/pwm-lp3943.c val = LP3943_DIM_PWM1; val 169 drivers/pwm/pwm-lp3943.c return lp3943_pwm_set_mode(lp3943_pwm, pwm_map, val); val 113 drivers/pwm/pwm-lpc18xx-sct.c u32 reg, u32 val) val 115 drivers/pwm/pwm-lpc18xx-sct.c writel(val, lpc18xx_pwm->base + reg); val 128 drivers/pwm/pwm-lpc18xx-sct.c u32 val; val 137 drivers/pwm/pwm-lpc18xx-sct.c val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE); val 138 drivers/pwm/pwm-lpc18xx-sct.c val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm); val 139 drivers/pwm/pwm-lpc18xx-sct.c val |= LPC18XX_PWM_RES(pwm->hwpwm, action); val 140 drivers/pwm/pwm-lpc18xx-sct.c lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val); val 148 drivers/pwm/pwm-lpc18xx-sct.c u64 val; val 150 drivers/pwm/pwm-lpc18xx-sct.c val = (u64)period_ns * lpc18xx_pwm->clk_rate; val 151 drivers/pwm/pwm-lpc18xx-sct.c do_div(val, NSEC_PER_SEC); val 155 drivers/pwm/pwm-lpc18xx-sct.c (u32)val - 1); val 159 drivers/pwm/pwm-lpc18xx-sct.c (u32)val - 1); val 167 drivers/pwm/pwm-lpc18xx-sct.c u64 val; val 169 drivers/pwm/pwm-lpc18xx-sct.c val = (u64)duty_ns * lpc18xx_pwm->clk_rate; val 170 drivers/pwm/pwm-lpc18xx-sct.c do_div(val, NSEC_PER_SEC); val 174 drivers/pwm/pwm-lpc18xx-sct.c (u32)val); val 178 drivers/pwm/pwm-lpc18xx-sct.c (u32)val); val 330 drivers/pwm/pwm-lpc18xx-sct.c u64 val; val 366 drivers/pwm/pwm-lpc18xx-sct.c val = (u64)NSEC_PER_SEC * LPC18XX_PWM_TIMER_MAX; val 367 drivers/pwm/pwm-lpc18xx-sct.c do_div(val, lpc18xx_pwm->clk_rate); val 368 drivers/pwm/pwm-lpc18xx-sct.c lpc18xx_pwm->max_period_ns = val; val 395 drivers/pwm/pwm-lpc18xx-sct.c val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) | val 398 drivers/pwm/pwm-lpc18xx-sct.c LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val); val 426 drivers/pwm/pwm-lpc18xx-sct.c val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL); val 427 drivers/pwm/pwm-lpc18xx-sct.c val &= ~LPC18XX_PWM_BIDIR; val 428 drivers/pwm/pwm-lpc18xx-sct.c val &= ~LPC18XX_PWM_CTRL_HALT; val 429 drivers/pwm/pwm-lpc18xx-sct.c val &= ~LPC18XX_PWM_PRE_MASK; val 430 drivers/pwm/pwm-lpc18xx-sct.c val |= LPC18XX_PWM_PRE(0); val 431 drivers/pwm/pwm-lpc18xx-sct.c lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val); val 445 drivers/pwm/pwm-lpc18xx-sct.c u32 val; val 447 drivers/pwm/pwm-lpc18xx-sct.c val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL); val 449 drivers/pwm/pwm-lpc18xx-sct.c val | LPC18XX_PWM_CTRL_HALT); val 35 drivers/pwm/pwm-lpc32xx.c u32 val; val 54 drivers/pwm/pwm-lpc32xx.c val = readl(lpc32xx->base + (pwm->hwpwm << 2)); val 55 drivers/pwm/pwm-lpc32xx.c val &= ~0xFFFF; val 56 drivers/pwm/pwm-lpc32xx.c val |= (period_cycles << 8) | duty_cycles; val 57 drivers/pwm/pwm-lpc32xx.c writel(val, lpc32xx->base + (pwm->hwpwm << 2)); val 65 drivers/pwm/pwm-lpc32xx.c u32 val; val 72 drivers/pwm/pwm-lpc32xx.c val = readl(lpc32xx->base + (pwm->hwpwm << 2)); val 73 drivers/pwm/pwm-lpc32xx.c val |= PWM_ENABLE; val 74 drivers/pwm/pwm-lpc32xx.c writel(val, lpc32xx->base + (pwm->hwpwm << 2)); val 82 drivers/pwm/pwm-lpc32xx.c u32 val; val 84 drivers/pwm/pwm-lpc32xx.c val = readl(lpc32xx->base + (pwm->hwpwm << 2)); val 85 drivers/pwm/pwm-lpc32xx.c val &= ~PWM_ENABLE; val 86 drivers/pwm/pwm-lpc32xx.c writel(val, lpc32xx->base + (pwm->hwpwm << 2)); val 103 drivers/pwm/pwm-lpc32xx.c u32 val; val 130 drivers/pwm/pwm-lpc32xx.c val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); val 131 drivers/pwm/pwm-lpc32xx.c val &= ~PWM_PIN_LEVEL; val 132 drivers/pwm/pwm-lpc32xx.c writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); val 56 drivers/pwm/pwm-lpss.c u32 val; val 70 drivers/pwm/pwm-lpss.c err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms); val 68 drivers/pwm/pwm-rockchip.c u32 val; val 85 drivers/pwm/pwm-rockchip.c val = readl_relaxed(pc->base + pc->data->regs.ctrl); val 87 drivers/pwm/pwm-rockchip.c state->enabled = ((val & enable_conf) != enable_conf) ? val 90 drivers/pwm/pwm-rockchip.c state->enabled = ((val & enable_conf) == enable_conf) ? val 93 drivers/pwm/pwm-rockchip.c if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) val 162 drivers/pwm/pwm-rockchip.c u32 val; val 170 drivers/pwm/pwm-rockchip.c val = readl_relaxed(pc->base + pc->data->regs.ctrl); val 173 drivers/pwm/pwm-rockchip.c val |= enable_conf; val 175 drivers/pwm/pwm-rockchip.c val &= ~enable_conf; val 177 drivers/pwm/pwm-rockchip.c writel_relaxed(val, pc->base + pc->data->regs.ctrl); val 482 drivers/pwm/pwm-samsung.c u32 val; val 490 drivers/pwm/pwm-samsung.c of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { val 491 drivers/pwm/pwm-samsung.c if (val >= SAMSUNG_PWM_NUM) { val 497 drivers/pwm/pwm-samsung.c chip->variant.output_mask |= BIT(val); val 87 drivers/pwm/pwm-sifive.c u32 val; val 98 drivers/pwm/pwm-sifive.c val = PWM_SIFIVE_PWMCFG_EN_ALWAYS | val 100 drivers/pwm/pwm-sifive.c writel(val, ddata->regs + PWM_SIFIVE_PWMCFG); val 113 drivers/pwm/pwm-sifive.c u32 duty, val; val 120 drivers/pwm/pwm-sifive.c val = readl(ddata->regs + PWM_SIFIVE_PWMCFG); val 121 drivers/pwm/pwm-sifive.c if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS)) val 72 drivers/pwm/pwm-spear.c unsigned long val) val 74 drivers/pwm/pwm-spear.c writel_relaxed(val, chip->mmio_base + (num << 4) + offset); val 81 drivers/pwm/pwm-spear.c u64 val, div, clk_rate; val 99 drivers/pwm/pwm-spear.c val = clk_rate * period_ns; val 100 drivers/pwm/pwm-spear.c pv = div64_u64(val, div); val 101 drivers/pwm/pwm-spear.c val = clk_rate * duty_ns; val 102 drivers/pwm/pwm-spear.c dc = div64_u64(val, div); val 141 drivers/pwm/pwm-spear.c u32 val; val 147 drivers/pwm/pwm-spear.c val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); val 148 drivers/pwm/pwm-spear.c val |= PWMCR_PWM_ENABLE; val 149 drivers/pwm/pwm-spear.c spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); val 157 drivers/pwm/pwm-spear.c u32 val; val 159 drivers/pwm/pwm-spear.c val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); val 160 drivers/pwm/pwm-spear.c val &= ~PWMCR_PWM_ENABLE; val 161 drivers/pwm/pwm-spear.c spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); val 179 drivers/pwm/pwm-spear.c u32 val; val 215 drivers/pwm/pwm-spear.c val = readl_relaxed(pc->mmio_base + PWMMCR); val 216 drivers/pwm/pwm-spear.c val |= PWMMCR_PWM_ENABLE; val 217 drivers/pwm/pwm-spear.c writel_relaxed(val, pc->mmio_base + PWMMCR); val 61 drivers/pwm/pwm-sprd.c u32 reg, u32 val) val 65 drivers/pwm/pwm-sprd.c writel_relaxed(val, spc->base + offset); val 74 drivers/pwm/pwm-sprd.c u32 val, duty, prescale; val 89 drivers/pwm/pwm-sprd.c val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); val 90 drivers/pwm/pwm-sprd.c if (val & SPRD_PWM_ENABLE_BIT) val 103 drivers/pwm/pwm-sprd.c val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); val 104 drivers/pwm/pwm-sprd.c prescale = val & SPRD_PWM_PRESCALE_MSK; val 108 drivers/pwm/pwm-sprd.c val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); val 109 drivers/pwm/pwm-sprd.c duty = val & SPRD_PWM_DUTY_MSK; val 40 drivers/pwm/pwm-stm32-lp.c u32 val, mask, cfgr, presc = 0; val 96 drivers/pwm/pwm-stm32-lp.c val = FIELD_PREP(STM32_LPTIM_PRESC, presc); val 97 drivers/pwm/pwm-stm32-lp.c val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); val 107 drivers/pwm/pwm-stm32-lp.c val); val 129 drivers/pwm/pwm-stm32-lp.c ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, val 130 drivers/pwm/pwm-stm32-lp.c (val & STM32_LPTIM_CMPOK_ARROK), val 166 drivers/pwm/pwm-stm32-lp.c u32 val, presc, prd; val 169 drivers/pwm/pwm-stm32-lp.c regmap_read(priv->regmap, STM32_LPTIM_CR, &val); val 170 drivers/pwm/pwm-stm32-lp.c state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); val 175 drivers/pwm/pwm-stm32-lp.c regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val); val 176 drivers/pwm/pwm-stm32-lp.c presc = FIELD_GET(STM32_LPTIM_PRESC, val); val 177 drivers/pwm/pwm-stm32-lp.c state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); val 184 drivers/pwm/pwm-stm32-lp.c regmap_read(priv->regmap, STM32_LPTIM_CMP, &val); val 185 drivers/pwm/pwm-stm32-lp.c tmp = prd - val; val 100 drivers/pwm/pwm-sun4i.c u32 val, unsigned long offset) val 102 drivers/pwm/pwm-sun4i.c writel(val, chip->base + offset); val 111 drivers/pwm/pwm-sun4i.c u32 val; val 116 drivers/pwm/pwm-sun4i.c val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); val 118 drivers/pwm/pwm-sun4i.c if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && val 122 drivers/pwm/pwm-sun4i.c prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; val 127 drivers/pwm/pwm-sun4i.c if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) val 132 drivers/pwm/pwm-sun4i.c if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == val 138 drivers/pwm/pwm-sun4i.c val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); val 140 drivers/pwm/pwm-sun4i.c tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val); val 143 drivers/pwm/pwm-sun4i.c tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val); val 223 drivers/pwm/pwm-sun4i.c u32 period, duty, val; val 245 drivers/pwm/pwm-sun4i.c val = (duty & PWM_DTY_MASK) | PWM_PRD(period); val 246 drivers/pwm/pwm-sun4i.c sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); val 61 drivers/pwm/pwm-tegra.c unsigned long val) val 63 drivers/pwm/pwm-tegra.c writel(val, chip->regs + (num << 4)); val 72 drivers/pwm/pwm-tegra.c u32 val = 0; val 83 drivers/pwm/pwm-tegra.c val = (u32)c << PWM_DUTY_SHIFT; val 110 drivers/pwm/pwm-tegra.c val |= rate << PWM_SCALE_SHIFT; val 121 drivers/pwm/pwm-tegra.c val |= PWM_ENABLE; val 123 drivers/pwm/pwm-tegra.c pwm_writel(pc, pwm->hwpwm, val); val 138 drivers/pwm/pwm-tegra.c u32 val; val 144 drivers/pwm/pwm-tegra.c val = pwm_readl(pc, pwm->hwpwm); val 145 drivers/pwm/pwm-tegra.c val |= PWM_ENABLE; val 146 drivers/pwm/pwm-tegra.c pwm_writel(pc, pwm->hwpwm, val); val 154 drivers/pwm/pwm-tegra.c u32 val; val 156 drivers/pwm/pwm-tegra.c val = pwm_readl(pc, pwm->hwpwm); val 157 drivers/pwm/pwm-tegra.c val &= ~PWM_ENABLE; val 158 drivers/pwm/pwm-tegra.c pwm_writel(pc, pwm->hwpwm, val); val 136 drivers/pwm/pwm-tiehrpwm.c unsigned short val; val 138 drivers/pwm/pwm-tiehrpwm.c val = readw(base + offset); val 139 drivers/pwm/pwm-tiehrpwm.c val &= ~mask; val 140 drivers/pwm/pwm-tiehrpwm.c val |= value & mask; val 141 drivers/pwm/pwm-tiehrpwm.c writew(val, base + offset); val 96 drivers/pwm/pwm-twl-led.c u8 val; val 99 drivers/pwm/pwm-twl-led.c ret = twl_i2c_read_u8(TWL4030_MODULE_LED, &val, TWL4030_LEDEN_REG); val 105 drivers/pwm/pwm-twl-led.c val |= TWL4030_LED_TOGGLE(pwm->hwpwm, TWL4030_LED_PINS); val 107 drivers/pwm/pwm-twl-led.c ret = twl_i2c_write_u8(TWL4030_MODULE_LED, val, TWL4030_LEDEN_REG); val 121 drivers/pwm/pwm-twl-led.c u8 val; val 124 drivers/pwm/pwm-twl-led.c ret = twl_i2c_read_u8(TWL4030_MODULE_LED, &val, TWL4030_LEDEN_REG); val 130 drivers/pwm/pwm-twl-led.c val &= ~TWL4030_LED_TOGGLE(pwm->hwpwm, TWL4030_LED_PINS); val 132 drivers/pwm/pwm-twl-led.c ret = twl_i2c_write_u8(TWL4030_MODULE_LED, val, TWL4030_LEDEN_REG); val 161 drivers/pwm/pwm-twl-led.c u8 val; val 164 drivers/pwm/pwm-twl-led.c ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, TWL6030_LED_PWM_CTRL2); val 171 drivers/pwm/pwm-twl-led.c val &= ~TWL6040_LED_MODE_MASK; val 172 drivers/pwm/pwm-twl-led.c val |= TWL6040_LED_MODE_ON; val 174 drivers/pwm/pwm-twl-led.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_LED_PWM_CTRL2); val 188 drivers/pwm/pwm-twl-led.c u8 val; val 191 drivers/pwm/pwm-twl-led.c ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, TWL6030_LED_PWM_CTRL2); val 198 drivers/pwm/pwm-twl-led.c val &= ~TWL6040_LED_MODE_MASK; val 199 drivers/pwm/pwm-twl-led.c val |= TWL6040_LED_MODE_OFF; val 201 drivers/pwm/pwm-twl-led.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_LED_PWM_CTRL2); val 213 drivers/pwm/pwm-twl-led.c u8 val; val 216 drivers/pwm/pwm-twl-led.c ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, TWL6030_LED_PWM_CTRL2); val 223 drivers/pwm/pwm-twl-led.c val &= ~TWL6040_LED_MODE_MASK; val 224 drivers/pwm/pwm-twl-led.c val |= TWL6040_LED_MODE_OFF; val 226 drivers/pwm/pwm-twl-led.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_LED_PWM_CTRL2); val 239 drivers/pwm/pwm-twl-led.c u8 val; val 242 drivers/pwm/pwm-twl-led.c ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, TWL6030_LED_PWM_CTRL2); val 249 drivers/pwm/pwm-twl-led.c val &= ~TWL6040_LED_MODE_MASK; val 250 drivers/pwm/pwm-twl-led.c val |= TWL6040_LED_MODE_HW; val 252 drivers/pwm/pwm-twl-led.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_LED_PWM_CTRL2); val 98 drivers/pwm/pwm-twl.c u8 val; val 101 drivers/pwm/pwm-twl.c ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_GPBR1_REG); val 107 drivers/pwm/pwm-twl.c val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); val 109 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG); val 113 drivers/pwm/pwm-twl.c val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); val 115 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG); val 128 drivers/pwm/pwm-twl.c u8 val; val 131 drivers/pwm/pwm-twl.c ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_GPBR1_REG); val 137 drivers/pwm/pwm-twl.c val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); val 139 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG); val 143 drivers/pwm/pwm-twl.c val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); val 145 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG); val 157 drivers/pwm/pwm-twl.c u8 val, mask, bits; val 168 drivers/pwm/pwm-twl.c ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_PMBR1_REG); val 176 drivers/pwm/pwm-twl.c twl->twl4030_pwm_mux |= (val & mask); val 179 drivers/pwm/pwm-twl.c val &= ~mask; val 180 drivers/pwm/pwm-twl.c val |= bits; val 182 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_PMBR1_REG); val 195 drivers/pwm/pwm-twl.c u8 val, mask; val 203 drivers/pwm/pwm-twl.c ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_PMBR1_REG); val 210 drivers/pwm/pwm-twl.c val &= ~mask; val 211 drivers/pwm/pwm-twl.c val |= (twl->twl4030_pwm_mux & mask); val 213 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_PMBR1_REG); val 225 drivers/pwm/pwm-twl.c u8 val; val 228 drivers/pwm/pwm-twl.c val = twl->twl6030_toggle3; val 229 drivers/pwm/pwm-twl.c val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); val 230 drivers/pwm/pwm-twl.c val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); val 232 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG); val 238 drivers/pwm/pwm-twl.c twl->twl6030_toggle3 = val; val 248 drivers/pwm/pwm-twl.c u8 val; val 251 drivers/pwm/pwm-twl.c val = twl->twl6030_toggle3; val 252 drivers/pwm/pwm-twl.c val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); val 253 drivers/pwm/pwm-twl.c val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); val 255 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG); val 261 drivers/pwm/pwm-twl.c val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXEN); val 263 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG); val 269 drivers/pwm/pwm-twl.c val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXEN); val 271 drivers/pwm/pwm-twl.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG); val 277 drivers/pwm/pwm-twl.c twl->twl6030_toggle3 = val; val 79 drivers/pwm/pwm-vt8500.c u32 val; val 117 drivers/pwm/pwm-vt8500.c val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); val 118 drivers/pwm/pwm-vt8500.c val |= CTRL_AUTOLOAD; val 119 drivers/pwm/pwm-vt8500.c writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); val 130 drivers/pwm/pwm-vt8500.c u32 val; val 138 drivers/pwm/pwm-vt8500.c val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); val 139 drivers/pwm/pwm-vt8500.c val |= CTRL_ENABLE; val 140 drivers/pwm/pwm-vt8500.c writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); val 149 drivers/pwm/pwm-vt8500.c u32 val; val 151 drivers/pwm/pwm-vt8500.c val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); val 152 drivers/pwm/pwm-vt8500.c val &= ~CTRL_ENABLE; val 153 drivers/pwm/pwm-vt8500.c writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); val 164 drivers/pwm/pwm-vt8500.c u32 val; val 166 drivers/pwm/pwm-vt8500.c val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); val 169 drivers/pwm/pwm-vt8500.c val |= CTRL_INVERT; val 171 drivers/pwm/pwm-vt8500.c val &= ~CTRL_INVERT; val 173 drivers/pwm/pwm-vt8500.c writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); val 55 drivers/pwm/sysfs.c unsigned int val; val 58 drivers/pwm/sysfs.c ret = kstrtouint(buf, 0, &val); val 64 drivers/pwm/sysfs.c state.period = val; val 90 drivers/pwm/sysfs.c unsigned int val; val 93 drivers/pwm/sysfs.c ret = kstrtouint(buf, 0, &val); val 99 drivers/pwm/sysfs.c state.duty_cycle = val; val 125 drivers/pwm/sysfs.c int val, ret; val 127 drivers/pwm/sysfs.c ret = kstrtoint(buf, 0, &val); val 135 drivers/pwm/sysfs.c switch (val) { val 139 drivers/rapidio/rio-sysfs.c u8 val; val 140 drivers/rapidio/rio-sysfs.c rio_read_config_8(dev, off, &val); val 141 drivers/rapidio/rio-sysfs.c data[off - init_off] = val; val 147 drivers/rapidio/rio-sysfs.c u16 val; val 148 drivers/rapidio/rio-sysfs.c rio_read_config_16(dev, off, &val); val 149 drivers/rapidio/rio-sysfs.c data[off - init_off] = (val >> 8) & 0xff; val 150 drivers/rapidio/rio-sysfs.c data[off - init_off + 1] = val & 0xff; val 156 drivers/rapidio/rio-sysfs.c u32 val; val 157 drivers/rapidio/rio-sysfs.c rio_read_config_32(dev, off, &val); val 158 drivers/rapidio/rio-sysfs.c data[off - init_off] = (val >> 24) & 0xff; val 159 drivers/rapidio/rio-sysfs.c data[off - init_off + 1] = (val >> 16) & 0xff; val 160 drivers/rapidio/rio-sysfs.c data[off - init_off + 2] = (val >> 8) & 0xff; val 161 drivers/rapidio/rio-sysfs.c data[off - init_off + 3] = val & 0xff; val 167 drivers/rapidio/rio-sysfs.c u16 val; val 168 drivers/rapidio/rio-sysfs.c rio_read_config_16(dev, off, &val); val 169 drivers/rapidio/rio-sysfs.c data[off - init_off] = (val >> 8) & 0xff; val 170 drivers/rapidio/rio-sysfs.c data[off - init_off + 1] = val & 0xff; val 176 drivers/rapidio/rio-sysfs.c u8 val; val 177 drivers/rapidio/rio-sysfs.c rio_read_config_8(dev, off, &val); val 178 drivers/rapidio/rio-sysfs.c data[off - init_off] = val; val 210 drivers/rapidio/rio-sysfs.c u16 val = data[off - init_off + 1]; val 211 drivers/rapidio/rio-sysfs.c val |= (u16) data[off - init_off] << 8; val 212 drivers/rapidio/rio-sysfs.c rio_write_config_16(dev, off, val); val 218 drivers/rapidio/rio-sysfs.c u32 val = data[off - init_off + 3]; val 219 drivers/rapidio/rio-sysfs.c val |= (u32) data[off - init_off + 2] << 8; val 220 drivers/rapidio/rio-sysfs.c val |= (u32) data[off - init_off + 1] << 16; val 221 drivers/rapidio/rio-sysfs.c val |= (u32) data[off - init_off] << 24; val 222 drivers/rapidio/rio-sysfs.c rio_write_config_32(dev, off, val); val 228 drivers/rapidio/rio-sysfs.c u16 val = data[off - init_off + 1]; val 229 drivers/rapidio/rio-sysfs.c val |= (u16) data[off - init_off] << 8; val 230 drivers/rapidio/rio-sysfs.c rio_write_config_16(dev, off, val); val 291 drivers/rapidio/rio-sysfs.c long val; val 294 drivers/rapidio/rio-sysfs.c if (kstrtol(buf, 0, &val) < 0) val 297 drivers/rapidio/rio-sysfs.c if (val == RIO_MPORT_ANY) { val 302 drivers/rapidio/rio-sysfs.c if (val < 0 || val >= RIO_MAX_MPORTS) val 305 drivers/rapidio/rio-sysfs.c rc = rio_mport_scan((int)val); val 388 drivers/ras/cec.c static int u64_get(void *data, u64 *val) val 390 drivers/ras/cec.c *val = *(u64 *)data; val 395 drivers/ras/cec.c static int pfn_set(void *data, u64 val) val 397 drivers/ras/cec.c *(u64 *)data = val; val 399 drivers/ras/cec.c cec_add_elem(val); val 406 drivers/ras/cec.c static int decay_interval_set(void *data, u64 val) val 408 drivers/ras/cec.c if (val < CEC_DECAY_MIN_INTERVAL) val 411 drivers/ras/cec.c if (val > CEC_DECAY_MAX_INTERVAL) val 414 drivers/ras/cec.c *(u64 *)data = val; val 415 drivers/ras/cec.c decay_interval = val; val 423 drivers/ras/cec.c static int action_threshold_set(void *data, u64 val) val 425 drivers/ras/cec.c *(u64 *)data = val; val 427 drivers/ras/cec.c if (val > COUNT_MASK) val 428 drivers/ras/cec.c val = COUNT_MASK; val 430 drivers/ras/cec.c action_threshold = val; val 46 drivers/regulator/aat2870-regulator.c u8 val; val 49 drivers/regulator/aat2870-regulator.c ret = aat2870->read(aat2870, ri->voltage_addr, &val); val 53 drivers/regulator/aat2870-regulator.c return (val & ri->voltage_mask) >> ri->voltage_shift; val 77 drivers/regulator/aat2870-regulator.c u8 val; val 80 drivers/regulator/aat2870-regulator.c ret = aat2870->read(aat2870, ri->enable_addr, &val); val 84 drivers/regulator/aat2870-regulator.c return val & ri->enable_mask ? 1 : 0; val 316 drivers/regulator/ab8500.c u8 bank, reg, mask, val; val 344 drivers/regulator/ab8500.c val = info->mode_val_normal; val 346 drivers/regulator/ab8500.c val = info->update_val_normal; val 363 drivers/regulator/ab8500.c val = info->mode_val_idle; val 365 drivers/regulator/ab8500.c val = info->update_val_idle; val 374 drivers/regulator/ab8500.c bank, reg, mask, val); val 385 drivers/regulator/ab8500.c mask, val); val 389 drivers/regulator/ab8500.c info->update_val = val; val 405 drivers/regulator/ab8500.c u8 val; val 425 drivers/regulator/ab8500.c info->mode_bank, info->mode_reg, &val); val 426 drivers/regulator/ab8500.c val = val & info->mode_mask; val 432 drivers/regulator/ab8500.c val = info->update_val; val 437 drivers/regulator/ab8500.c if (val == val_normal) val 439 drivers/regulator/ab8500.c else if (val == val_idle) val 240 drivers/regulator/act8865-regulator.c int id = rdev->desc->id, reg, val; val 245 drivers/regulator/act8865-regulator.c val = 0xa8; val 249 drivers/regulator/act8865-regulator.c val = 0xa8; val 253 drivers/regulator/act8865-regulator.c val = 0xa8; val 257 drivers/regulator/act8865-regulator.c val = 0xe8; val 261 drivers/regulator/act8865-regulator.c val = 0xe8; val 265 drivers/regulator/act8865-regulator.c val = 0xe8; val 269 drivers/regulator/act8865-regulator.c val = 0xe8; val 276 drivers/regulator/act8865-regulator.c val |= BIT(4); val 282 drivers/regulator/act8865-regulator.c return regmap_write(regmap, reg, val); val 313 drivers/regulator/act8865-regulator.c int reg, val = 0; val 345 drivers/regulator/act8865-regulator.c val = BIT(5); val 349 drivers/regulator/act8865-regulator.c val = BIT(5); val 355 drivers/regulator/act8865-regulator.c return regmap_update_bits(regmap, reg, BIT(5), val); val 362 drivers/regulator/act8865-regulator.c int reg, ret, val = 0; val 390 drivers/regulator/act8865-regulator.c ret = regmap_read(regmap, reg, &val); val 394 drivers/regulator/act8865-regulator.c if (id <= ACT8865_ID_DCDC3 && (val & BIT(5))) val 396 drivers/regulator/act8865-regulator.c else if (id > ACT8865_ID_DCDC3 && !(val & BIT(5))) val 587 drivers/regulator/act8865-regulator.c unsigned int val; val 591 drivers/regulator/act8865-regulator.c ret = regmap_read(map, ACT8600_APCH_STAT, &val); val 595 drivers/regulator/act8865-regulator.c state0 = val & ACT8600_APCH_CSTATE0; val 596 drivers/regulator/act8865-regulator.c state1 = val & ACT8600_APCH_CSTATE1; val 609 drivers/regulator/act8865-regulator.c enum power_supply_property psp, union power_supply_propval *val) val 620 drivers/regulator/act8865-regulator.c val->intval = ret; val 86 drivers/regulator/act8945a-regulator.c int reg, val; val 91 drivers/regulator/act8945a-regulator.c val = 0xa8; val 95 drivers/regulator/act8945a-regulator.c val = 0xa8; val 99 drivers/regulator/act8945a-regulator.c val = 0xa8; val 103 drivers/regulator/act8945a-regulator.c val = 0xe8; val 107 drivers/regulator/act8945a-regulator.c val = 0xe8; val 111 drivers/regulator/act8945a-regulator.c val = 0xe8; val 115 drivers/regulator/act8945a-regulator.c val = 0xe8; val 122 drivers/regulator/act8945a-regulator.c val |= BIT(4); val 128 drivers/regulator/act8945a-regulator.c return regmap_write(regmap, reg, val); val 159 drivers/regulator/act8945a-regulator.c int reg, ret, val = 0; val 190 drivers/regulator/act8945a-regulator.c val = BIT(5); val 194 drivers/regulator/act8945a-regulator.c val = BIT(5); val 200 drivers/regulator/act8945a-regulator.c ret = regmap_update_bits(regmap, reg, BIT(5), val); val 40 drivers/regulator/ad5398.c unsigned short val; val 43 drivers/regulator/ad5398.c ret = i2c_master_recv(client, (char *)&val, 2); val 48 drivers/regulator/ad5398.c *data = be16_to_cpu(val); val 55 drivers/regulator/ad5398.c unsigned short val; val 58 drivers/regulator/ad5398.c val = cpu_to_be16(data); val 59 drivers/regulator/ad5398.c ret = i2c_master_send(client, (char *)&val, 2); val 39 drivers/regulator/anatop-regulator.c u32 val; val 50 drivers/regulator/anatop-regulator.c regmap_read(reg->regmap, anatop_reg->delay_reg, &val); val 51 drivers/regulator/anatop-regulator.c val = (val >> anatop_reg->delay_bit_shift) & val 54 drivers/regulator/anatop-regulator.c val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1; val 173 drivers/regulator/anatop-regulator.c u32 val; val 261 drivers/regulator/anatop-regulator.c ret = regmap_read(config.regmap, rdesc->vsel_reg, &val); val 267 drivers/regulator/anatop-regulator.c sreg->sel = (val & rdesc->vsel_mask) >> vol_bit_shift; val 46 drivers/regulator/arizona-ldo1.c unsigned int val; val 50 drivers/regulator/arizona-ldo1.c val = ARIZONA_LDO1_HI_PWR; val 52 drivers/regulator/arizona-ldo1.c val = 0; val 55 drivers/regulator/arizona-ldo1.c ARIZONA_LDO1_HI_PWR, val); val 59 drivers/regulator/arizona-ldo1.c if (val) val 68 drivers/regulator/arizona-ldo1.c unsigned int val; val 71 drivers/regulator/arizona-ldo1.c ret = regmap_read(regmap, ARIZONA_LDO1_CONTROL_2, &val); val 75 drivers/regulator/arizona-ldo1.c if (val & ARIZONA_LDO1_HI_PWR) val 52 drivers/regulator/arizona-micsupp.c unsigned int val; val 55 drivers/regulator/arizona-micsupp.c ret = regmap_read(micsupp->regmap, micsupp->enable_reg, &val); val 65 drivers/regulator/arizona-micsupp.c if ((val & (ARIZONA_CPMIC_ENA | ARIZONA_CPMIC_BYPASS)) == val 32 drivers/regulator/as3711-regulator.c u8 val; val 36 drivers/regulator/as3711-regulator.c val = fast_bit | low_noise_bit; val 39 drivers/regulator/as3711-regulator.c val = low_noise_bit; val 42 drivers/regulator/as3711-regulator.c val = 0; val 49 drivers/regulator/as3711-regulator.c low_noise_bit | fast_bit, val); val 56 drivers/regulator/as3711-regulator.c unsigned int val; val 57 drivers/regulator/as3711-regulator.c int ret = regmap_read(rdev->regmap, AS3711_SD_CONTROL_1, &val); val 62 drivers/regulator/as3711-regulator.c if ((val & mask) == mask) val 65 drivers/regulator/as3711-regulator.c if ((val & mask) == low_noise_bit) val 68 drivers/regulator/as3711-regulator.c if (!(val & mask)) val 424 drivers/regulator/as3722-regulator.c u32 val; val 430 drivers/regulator/as3722-regulator.c ret = as3722_read(as3722, as3722_reg_lookup[id].control_reg, &val); val 437 drivers/regulator/as3722-regulator.c if (val & as3722_reg_lookup[id].mode_mask) val 449 drivers/regulator/as3722-regulator.c u8 val = 0; val 457 drivers/regulator/as3722-regulator.c val = as3722_reg_lookup[id].mode_mask; val 465 drivers/regulator/as3722-regulator.c as3722_reg_lookup[id].mode_mask, val); val 477 drivers/regulator/as3722-regulator.c unsigned val; val 479 drivers/regulator/as3722-regulator.c err = as3722_read(as3722_regs->as3722, AS3722_FUSE7_REG, &val); val 485 drivers/regulator/as3722-regulator.c if (val & AS3722_FUSE7_SD0_LOW_VOLTAGE) val 547 drivers/regulator/as3722-regulator.c unsigned int val; val 553 drivers/regulator/as3722-regulator.c val = ext_pwr_ctrl << (ffs(as3722_reg_lookup[id].sleep_ctrl_mask) - 1); val 556 drivers/regulator/as3722-regulator.c as3722_reg_lookup[id].sleep_ctrl_mask, val); val 317 drivers/regulator/bd718x7-regulator.c unsigned int val; val 340 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO5_VRMON80, val 348 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO6_VRMON80, val 504 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 528 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 555 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 582 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 604 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 628 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 654 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 676 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 699 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 722 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 748 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 773 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 800 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 824 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 848 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 872 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 899 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 923 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 945 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 969 drivers/regulator/bd718x7-regulator.c .val = BD718XX_BUCK_SEL, val 995 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 1017 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 1040 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 1063 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 1088 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 1115 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 1140 drivers/regulator/bd718x7-regulator.c .val = BD718XX_LDO_SEL, val 1258 drivers/regulator/bd718x7-regulator.c r->init.mask, r->init.val); val 1270 drivers/regulator/bd718x7-regulator.c r->additional_inits[j].val); val 53 drivers/regulator/bd9571mwv-regulator.c unsigned int val; val 56 drivers/regulator/bd9571mwv-regulator.c ret = regmap_read(rdev->regmap, BD9571MWV_AVS_SET_MONI, &val); val 60 drivers/regulator/bd9571mwv-regulator.c return val & BD9571MWV_AVS_SET_MONI_MASK; val 78 drivers/regulator/bd9571mwv-regulator.c unsigned int val; val 85 drivers/regulator/bd9571mwv-regulator.c ret = regmap_read(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), &val); val 89 drivers/regulator/bd9571mwv-regulator.c val &= rdev->desc->vsel_mask; val 90 drivers/regulator/bd9571mwv-regulator.c val >>= ffs(rdev->desc->vsel_mask) - 1; val 92 drivers/regulator/bd9571mwv-regulator.c return val; val 275 drivers/regulator/bd9571mwv-regulator.c unsigned int val; val 301 drivers/regulator/bd9571mwv-regulator.c val = 0; val 302 drivers/regulator/bd9571mwv-regulator.c of_property_read_u32(bd->dev->of_node, "rohm,ddr-backup-power", &val); val 303 drivers/regulator/bd9571mwv-regulator.c if (val & ~BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK) { val 305 drivers/regulator/bd9571mwv-regulator.c "rohm,ddr-backup-power", val); val 308 drivers/regulator/bd9571mwv-regulator.c bdreg->bkup_mode_cnt_keepon = val; val 104 drivers/regulator/da903x.c uint8_t val, mask; val 109 drivers/regulator/da903x.c val = selector << info->vol_shift; val 112 drivers/regulator/da903x.c return da903x_update(da9034_dev, info->vol_reg, val, mask); val 119 drivers/regulator/da903x.c uint8_t val, mask; val 125 drivers/regulator/da903x.c ret = da903x_read(da9034_dev, info->vol_reg, &val); val 130 drivers/regulator/da903x.c val = (val & mask) >> info->vol_shift; val 132 drivers/regulator/da903x.c return val; val 173 drivers/regulator/da903x.c uint8_t val, mask; val 176 drivers/regulator/da903x.c val = selector << info->vol_shift; val 178 drivers/regulator/da903x.c val |= DA9030_LDO_UNLOCK; /* have to set UNLOCK bits */ val 182 drivers/regulator/da903x.c ret = da903x_update(da903x_dev, info->vol_reg, val, mask); val 186 drivers/regulator/da903x.c return da903x_update(da903x_dev, info->vol_reg, val, mask); val 236 drivers/regulator/da903x.c uint8_t val, mask; val 239 drivers/regulator/da903x.c val = selector << info->vol_shift; val 242 drivers/regulator/da903x.c ret = da903x_update(da9034_dev, info->vol_reg, val, mask); val 112 drivers/regulator/da9055-regulator.c int val = 0; val 116 drivers/regulator/da9055-regulator.c val = DA9055_BUCK_MODE_SYNC << info->mode.shift; val 119 drivers/regulator/da9055-regulator.c val = DA9055_BUCK_MODE_AUTO << info->mode.shift; val 122 drivers/regulator/da9055-regulator.c val = DA9055_BUCK_MODE_SLEEP << info->mode.shift; val 127 drivers/regulator/da9055-regulator.c info->mode.mask, val); val 151 drivers/regulator/da9055-regulator.c int val = 0; val 156 drivers/regulator/da9055-regulator.c val = DA9055_LDO_MODE_SYNC; val 159 drivers/regulator/da9055-regulator.c val = DA9055_LDO_MODE_SLEEP; val 165 drivers/regulator/da9055-regulator.c val << volt.sl_shift); val 111 drivers/regulator/da9062-regulator.c unsigned val; val 115 drivers/regulator/da9062-regulator.c val = BUCK_MODE_SYNC; val 118 drivers/regulator/da9062-regulator.c val = BUCK_MODE_AUTO; val 121 drivers/regulator/da9062-regulator.c val = BUCK_MODE_SLEEP; val 127 drivers/regulator/da9062-regulator.c return regmap_field_write(regl->mode, val); val 139 drivers/regulator/da9062-regulator.c unsigned int val, mode = 0; val 142 drivers/regulator/da9062-regulator.c ret = regmap_field_read(regl->mode, &val); val 146 drivers/regulator/da9062-regulator.c switch (val) { val 160 drivers/regulator/da9062-regulator.c ret = regmap_field_read(regl->sleep, &val); val 164 drivers/regulator/da9062-regulator.c if (val) val 180 drivers/regulator/da9062-regulator.c unsigned val; val 184 drivers/regulator/da9062-regulator.c val = 0; val 187 drivers/regulator/da9062-regulator.c val = 1; val 193 drivers/regulator/da9062-regulator.c return regmap_field_write(regl->sleep, val); val 199 drivers/regulator/da9062-regulator.c int ret, val; val 201 drivers/regulator/da9062-regulator.c ret = regmap_field_read(regl->sleep, &val); val 205 drivers/regulator/da9062-regulator.c if (val) val 281 drivers/regulator/da9062-regulator.c int val; val 285 drivers/regulator/da9062-regulator.c val = BUCK_MODE_SYNC; val 288 drivers/regulator/da9062-regulator.c val = BUCK_MODE_AUTO; val 291 drivers/regulator/da9062-regulator.c val = BUCK_MODE_SLEEP; val 297 drivers/regulator/da9062-regulator.c return regmap_field_write(regl->mode, val); val 304 drivers/regulator/da9062-regulator.c unsigned val; val 308 drivers/regulator/da9062-regulator.c val = 0; val 311 drivers/regulator/da9062-regulator.c val = 1; val 317 drivers/regulator/da9062-regulator.c return regmap_field_write(regl->suspend_sleep, val); val 199 drivers/regulator/da9063-regulator.c unsigned val; val 203 drivers/regulator/da9063-regulator.c val = BUCK_MODE_SYNC; val 206 drivers/regulator/da9063-regulator.c val = BUCK_MODE_AUTO; val 209 drivers/regulator/da9063-regulator.c val = BUCK_MODE_SLEEP; val 215 drivers/regulator/da9063-regulator.c return regmap_field_write(regl->mode, val); val 228 drivers/regulator/da9063-regulator.c unsigned int val, mode = 0; val 231 drivers/regulator/da9063-regulator.c ret = regmap_field_read(regl->mode, &val); val 235 drivers/regulator/da9063-regulator.c switch (val) { val 250 drivers/regulator/da9063-regulator.c ret = regmap_field_read(regl->suspend, &val); val 255 drivers/regulator/da9063-regulator.c if (val) val 260 drivers/regulator/da9063-regulator.c ret = regmap_field_read(field, &val); val 264 drivers/regulator/da9063-regulator.c if (val) val 280 drivers/regulator/da9063-regulator.c unsigned val; val 284 drivers/regulator/da9063-regulator.c val = 0; val 287 drivers/regulator/da9063-regulator.c val = 1; val 293 drivers/regulator/da9063-regulator.c return regmap_field_write(regl->sleep, val); val 300 drivers/regulator/da9063-regulator.c int ret, val; val 303 drivers/regulator/da9063-regulator.c ret = regmap_field_read(regl->suspend, &val); val 308 drivers/regulator/da9063-regulator.c if (val) val 313 drivers/regulator/da9063-regulator.c ret = regmap_field_read(field, &val); val 317 drivers/regulator/da9063-regulator.c if (val) val 392 drivers/regulator/da9063-regulator.c int val; val 396 drivers/regulator/da9063-regulator.c val = BUCK_MODE_SYNC; val 399 drivers/regulator/da9063-regulator.c val = BUCK_MODE_AUTO; val 402 drivers/regulator/da9063-regulator.c val = BUCK_MODE_SLEEP; val 408 drivers/regulator/da9063-regulator.c return regmap_field_write(regl->mode, val); val 414 drivers/regulator/da9063-regulator.c unsigned val; val 418 drivers/regulator/da9063-regulator.c val = 0; val 421 drivers/regulator/da9063-regulator.c val = 1; val 427 drivers/regulator/da9063-regulator.c return regmap_field_write(regl->suspend_sleep, val); val 725 drivers/regulator/da9063-regulator.c int id, irq, n, n_regulators, ret, val; val 746 drivers/regulator/da9063-regulator.c ret = regmap_read(da9063->regmap, DA9063_REG_CONFIG_H, &val); val 752 drivers/regulator/da9063-regulator.c bcores_merged = val & DA9063_BCORE_MERGE; val 753 drivers/regulator/da9063-regulator.c bmem_bio_merged = val & DA9063_BUCK_MERGE; val 73 drivers/regulator/da9210-regulator.c unsigned int val, handled = 0; val 76 drivers/regulator/da9210-regulator.c error = regmap_read(chip->regmap, DA9210_REG_EVENT_B, &val); val 82 drivers/regulator/da9210-regulator.c if (val & DA9210_E_OVCURR) { val 88 drivers/regulator/da9210-regulator.c if (val & DA9210_E_NPWRGOOD) { val 94 drivers/regulator/da9210-regulator.c if (val & (DA9210_E_TEMP_WARN | DA9210_E_TEMP_CRIT)) { val 97 drivers/regulator/da9210-regulator.c handled |= val & (DA9210_E_TEMP_WARN | DA9210_E_TEMP_CRIT); val 99 drivers/regulator/da9210-regulator.c if (val & DA9210_E_VMAX) { val 123 drivers/regulator/da9211-regulator.c int val = 0; val 127 drivers/regulator/da9211-regulator.c val = DA9211_BUCK_MODE_SYNC; val 130 drivers/regulator/da9211-regulator.c val = DA9211_BUCK_MODE_AUTO; val 133 drivers/regulator/da9211-regulator.c val = DA9211_BUCK_MODE_SLEEP; val 138 drivers/regulator/da9211-regulator.c 0x03, val); val 168 drivers/regulator/fan53555.c unsigned int val; val 171 drivers/regulator/fan53555.c ret = regmap_read(rdev->regmap, di->mode_reg, &val); val 174 drivers/regulator/fan53555.c if (val & di->mode_mask) val 463 drivers/regulator/fan53555.c unsigned int val; val 507 drivers/regulator/fan53555.c ret = regmap_read(regmap, FAN53555_ID1, &val); val 512 drivers/regulator/fan53555.c di->chip_id = val & DIE_ID; val 514 drivers/regulator/fan53555.c ret = regmap_read(regmap, FAN53555_ID2, &val); val 519 drivers/regulator/fan53555.c di->chip_rev = val & DIE_REV; val 167 drivers/regulator/gpio-regulator.c u32 val; val 170 drivers/regulator/gpio-regulator.c &val); val 177 drivers/regulator/gpio-regulator.c val ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; val 29 drivers/regulator/helpers.c unsigned int val; val 32 drivers/regulator/helpers.c ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val); val 36 drivers/regulator/helpers.c val &= rdev->desc->enable_mask; val 40 drivers/regulator/helpers.c return val != rdev->desc->enable_val; val 41 drivers/regulator/helpers.c return val == 0; val 44 drivers/regulator/helpers.c return val == rdev->desc->enable_val; val 45 drivers/regulator/helpers.c return val != 0; val 61 drivers/regulator/helpers.c unsigned int val; val 64 drivers/regulator/helpers.c val = rdev->desc->disable_val; val 66 drivers/regulator/helpers.c val = rdev->desc->enable_val; val 67 drivers/regulator/helpers.c if (!val) val 68 drivers/regulator/helpers.c val = rdev->desc->enable_mask; val 72 drivers/regulator/helpers.c rdev->desc->enable_mask, val); val 87 drivers/regulator/helpers.c unsigned int val; val 90 drivers/regulator/helpers.c val = rdev->desc->enable_val; val 91 drivers/regulator/helpers.c if (!val) val 92 drivers/regulator/helpers.c val = rdev->desc->enable_mask; val 94 drivers/regulator/helpers.c val = rdev->desc->disable_val; val 98 drivers/regulator/helpers.c rdev->desc->enable_mask, val); val 133 drivers/regulator/helpers.c unsigned int val; val 140 drivers/regulator/helpers.c ret = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &val); val 148 drivers/regulator/helpers.c val &= rdev->desc->vsel_mask; val 149 drivers/regulator/helpers.c val >>= ffs(rdev->desc->vsel_mask) - 1; val 159 drivers/regulator/helpers.c return val + voltages_in_range; val 235 drivers/regulator/helpers.c unsigned int val; val 238 drivers/regulator/helpers.c ret = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &val); val 242 drivers/regulator/helpers.c val &= rdev->desc->vsel_mask; val 243 drivers/regulator/helpers.c val >>= ffs(rdev->desc->vsel_mask) - 1; val 245 drivers/regulator/helpers.c return val; val 681 drivers/regulator/helpers.c unsigned int val; val 684 drivers/regulator/helpers.c val = rdev->desc->bypass_val_on; val 685 drivers/regulator/helpers.c if (!val) val 686 drivers/regulator/helpers.c val = rdev->desc->bypass_mask; val 688 drivers/regulator/helpers.c val = rdev->desc->bypass_val_off; val 692 drivers/regulator/helpers.c rdev->desc->bypass_mask, val); val 703 drivers/regulator/helpers.c unsigned int val; val 705 drivers/regulator/helpers.c val = rdev->desc->soft_start_val_on; val 706 drivers/regulator/helpers.c if (!val) val 707 drivers/regulator/helpers.c val = rdev->desc->soft_start_mask; val 710 drivers/regulator/helpers.c rdev->desc->soft_start_mask, val); val 721 drivers/regulator/helpers.c unsigned int val; val 723 drivers/regulator/helpers.c val = rdev->desc->pull_down_val_on; val 724 drivers/regulator/helpers.c if (!val) val 725 drivers/regulator/helpers.c val = rdev->desc->pull_down_mask; val 728 drivers/regulator/helpers.c rdev->desc->pull_down_mask, val); val 740 drivers/regulator/helpers.c unsigned int val; val 744 drivers/regulator/helpers.c ret = regmap_read(rdev->regmap, rdev->desc->bypass_reg, &val); val 751 drivers/regulator/helpers.c *enable = (val & rdev->desc->bypass_mask) == val_on; val 767 drivers/regulator/helpers.c unsigned int val; val 770 drivers/regulator/helpers.c val = rdev->desc->active_discharge_on; val 772 drivers/regulator/helpers.c val = rdev->desc->active_discharge_off; val 776 drivers/regulator/helpers.c rdev->desc->active_discharge_mask, val); val 845 drivers/regulator/helpers.c unsigned int val; val 848 drivers/regulator/helpers.c ret = regmap_read(rdev->regmap, rdev->desc->csel_reg, &val); val 852 drivers/regulator/helpers.c val &= rdev->desc->csel_mask; val 853 drivers/regulator/helpers.c val >>= ffs(rdev->desc->csel_mask) - 1; val 856 drivers/regulator/helpers.c if (val >= rdev->desc->n_current_limits) val 859 drivers/regulator/helpers.c return rdev->desc->curr_table[val]; val 53 drivers/regulator/lm363x-regulator.c unsigned int val, addr, mask; val 76 drivers/regulator/lm363x-regulator.c if (regmap_read(rdev->regmap, addr, &val)) val 79 drivers/regulator/lm363x-regulator.c val = (val & mask) >> LM3631_ENTIME_SHIFT; val 82 drivers/regulator/lm363x-regulator.c return ldo_cont_enable_time[val]; val 84 drivers/regulator/lm363x-regulator.c return ENABLE_TIME_USEC * val; val 119 drivers/regulator/lochnagar-regulator.c unsigned int val; val 122 drivers/regulator/lochnagar-regulator.c ret = of_property_read_u32(np, "cirrus,micbias-input", &val); val 127 drivers/regulator/lochnagar-regulator.c mask, val << shift); val 27 drivers/regulator/lp3971.c static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val); val 111 drivers/regulator/lp3971.c u16 val; val 113 drivers/regulator/lp3971.c val = lp3971_reg_read(lp3971, LP3971_LDO_ENABLE_REG); val 114 drivers/regulator/lp3971.c return (val & mask) != 0; val 139 drivers/regulator/lp3971.c u16 val, reg; val 142 drivers/regulator/lp3971.c val = (reg >> LDO_VOL_CONTR_SHIFT(ldo)) & LDO_VOL_CONTR_MASK; val 144 drivers/regulator/lp3971.c return val; val 173 drivers/regulator/lp3971.c u16 val; val 175 drivers/regulator/lp3971.c val = lp3971_reg_read(lp3971, LP3971_BUCK_VOL_ENABLE_REG); val 176 drivers/regulator/lp3971.c return (val & mask) != 0; val 342 drivers/regulator/lp3971.c u16 val = 0; val 346 drivers/regulator/lp3971.c lp3971_i2c_read(lp3971->i2c, reg, 1, &val); val 349 drivers/regulator/lp3971.c (unsigned)val&0xff); val 353 drivers/regulator/lp3971.c return val & 0xff; val 356 drivers/regulator/lp3971.c static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val) val 365 drivers/regulator/lp3971.c tmp = (tmp & ~mask) | val; val 368 drivers/regulator/lp3971.c (unsigned)val&0xff); val 409 drivers/regulator/lp3971.c u16 val; val 426 drivers/regulator/lp3971.c ret = lp3971_i2c_read(i2c, LP3971_SYS_CONTROL1_REG, 1, &val); val 427 drivers/regulator/lp3971.c if (ret == 0 && (val & SYS_CONTROL1_INIT_MASK) != SYS_CONTROL1_INIT_VAL) val 188 drivers/regulator/lp3972.c u16 val = 0; val 192 drivers/regulator/lp3972.c lp3972_i2c_read(lp3972->i2c, reg, 1, &val); val 195 drivers/regulator/lp3972.c (unsigned)val & 0xff); val 199 drivers/regulator/lp3972.c return val & 0xff; val 202 drivers/regulator/lp3972.c static int lp3972_set_bits(struct lp3972 *lp3972, u8 reg, u16 mask, u16 val) val 211 drivers/regulator/lp3972.c tmp = (tmp & ~mask) | val; val 214 drivers/regulator/lp3972.c (unsigned)val & 0xff); val 226 drivers/regulator/lp3972.c u16 val; val 228 drivers/regulator/lp3972.c val = lp3972_reg_read(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo)); val 229 drivers/regulator/lp3972.c return !!(val & mask); val 257 drivers/regulator/lp3972.c u16 val, reg; val 260 drivers/regulator/lp3972.c val = (reg >> LP3972_LDO_VOL_CONTR_SHIFT(ldo)) & mask; val 262 drivers/regulator/lp3972.c return val; val 319 drivers/regulator/lp3972.c u16 val; val 321 drivers/regulator/lp3972.c val = lp3972_reg_read(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck)); val 322 drivers/regulator/lp3972.c return !!(val & mask); val 330 drivers/regulator/lp3972.c u16 val; val 332 drivers/regulator/lp3972.c val = lp3972_set_bits(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck), val 334 drivers/regulator/lp3972.c return val; val 342 drivers/regulator/lp3972.c u16 val; val 344 drivers/regulator/lp3972.c val = lp3972_set_bits(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck), val 346 drivers/regulator/lp3972.c return val; val 504 drivers/regulator/lp3972.c u16 val; val 521 drivers/regulator/lp3972.c ret = lp3972_i2c_read(i2c, LP3972_SYS_CONTROL1_REG, 1, &val); val 523 drivers/regulator/lp3972.c (val & SYS_CONTROL1_INIT_MASK) != SYS_CONTROL1_INIT_VAL) { val 525 drivers/regulator/lp3972.c dev_err(&i2c->dev, "chip reported: val = 0x%x\n", val); val 159 drivers/regulator/lp872x.c unsigned int val; val 161 drivers/regulator/lp872x.c ret = regmap_read(lp->regmap, addr, &val); val 167 drivers/regulator/lp872x.c *data = (u8)val; val 185 drivers/regulator/lp872x.c u8 val, mask, shift; val 207 drivers/regulator/lp872x.c ret = lp872x_read_byte(lp, LP872X_GENERAL_CFG, &val); val 211 drivers/regulator/lp872x.c val = (val & mask) >> shift; val 212 drivers/regulator/lp872x.c if (val >= size) val 215 drivers/regulator/lp872x.c return *(time_usec + val); val 224 drivers/regulator/lp872x.c u8 addr, val; val 243 drivers/regulator/lp872x.c ret = lp872x_read_byte(lp, addr, &val); val 247 drivers/regulator/lp872x.c val = (val & LP872X_START_DELAY_M) >> LP872X_START_DELAY_S; val 249 drivers/regulator/lp872x.c return val > MAX_DELAY ? 0 : val * time_step_us; val 265 drivers/regulator/lp872x.c u8 val, addr; val 267 drivers/regulator/lp872x.c if (lp872x_read_byte(lp, LP872X_GENERAL_CFG, &val)) val 272 drivers/regulator/lp872x.c if (val & LP8720_EXT_DVS_M) { val 276 drivers/regulator/lp872x.c if (lp872x_read_byte(lp, LP8720_ENABLE, &val)) val 279 drivers/regulator/lp872x.c addr = val & LP8720_DVS_SEL_M ? val 284 drivers/regulator/lp872x.c if (val & LP8725_DVS1_M) val 291 drivers/regulator/lp872x.c addr = val & LP8725_DVS2_M ? val 338 drivers/regulator/lp872x.c u8 addr, val; val 345 drivers/regulator/lp872x.c ret = lp872x_read_byte(lp, addr, &val); val 349 drivers/regulator/lp872x.c return val & LP872X_VOUT_M; val 356 drivers/regulator/lp872x.c u8 addr, mask, shift, val; val 379 drivers/regulator/lp872x.c val = LP872X_FORCE_PWM << shift; val 381 drivers/regulator/lp872x.c val = LP872X_AUTO_PWM << shift; val 385 drivers/regulator/lp872x.c return lp872x_update_bits(lp, addr, mask, val); val 392 drivers/regulator/lp872x.c u8 addr, mask, val; val 412 drivers/regulator/lp872x.c ret = lp872x_read_byte(lp, addr, &val); val 416 drivers/regulator/lp872x.c return val & mask ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; val 59 drivers/regulator/lp8755.c unsigned int *val) val 61 drivers/regulator/lp8755.c return regmap_read(pchip->regmap, reg, val); val 71 drivers/regulator/lp8755.c unsigned int val) val 73 drivers/regulator/lp8755.c return regmap_write(pchip->regmap, reg, val); val 84 drivers/regulator/lp8755.c unsigned int mask, unsigned int val) val 86 drivers/regulator/lp8755.c return regmap_update_bits(pchip->regmap, reg, mask, val); val 166 drivers/regulator/lp8788-buck.c u8 val, mask; val 179 drivers/regulator/lp8788-buck.c lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val); val 181 drivers/regulator/lp8788-buck.c return val & mask ? REGISTER : EXTPIN; val 207 drivers/regulator/lp8788-buck.c u8 val, idx, addr; val 219 drivers/regulator/lp8788-buck.c lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val); val 220 drivers/regulator/lp8788-buck.c idx = (val & LP8788_BUCK1_DVS_M) >> LP8788_BUCK1_DVS_S; val 242 drivers/regulator/lp8788-buck.c lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val); val 243 drivers/regulator/lp8788-buck.c idx = (val & LP8788_BUCK2_DVS_M) >> LP8788_BUCK2_DVS_S; val 278 drivers/regulator/lp8788-buck.c u8 val, addr; val 284 drivers/regulator/lp8788-buck.c ret = lp8788_read_byte(buck->lp, addr, &val); val 288 drivers/regulator/lp8788-buck.c return val & LP8788_VOUT_M; val 295 drivers/regulator/lp8788-buck.c u8 val, addr = LP8788_BUCK1_TIMESTEP + id; val 297 drivers/regulator/lp8788-buck.c if (lp8788_read_byte(buck->lp, addr, &val)) val 300 drivers/regulator/lp8788-buck.c val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S; val 302 drivers/regulator/lp8788-buck.c return ENABLE_TIME_USEC * val; val 309 drivers/regulator/lp8788-buck.c u8 mask, val; val 314 drivers/regulator/lp8788-buck.c val = LP8788_FORCE_PWM << BUCK_FPWM_SHIFT(id); val 317 drivers/regulator/lp8788-buck.c val = LP8788_AUTO_PWM << BUCK_FPWM_SHIFT(id); val 323 drivers/regulator/lp8788-buck.c return lp8788_update_bits(buck->lp, LP8788_BUCK_PWM, mask, val); val 330 drivers/regulator/lp8788-buck.c u8 val; val 333 drivers/regulator/lp8788-buck.c ret = lp8788_read_byte(buck->lp, LP8788_BUCK_PWM, &val); val 337 drivers/regulator/lp8788-buck.c return val & BUCK_FPWM_MASK(id) ? val 463 drivers/regulator/lp8788-buck.c u8 val[] = { LP8788_BUCK1_DVS_PIN, LP8788_BUCK2_DVS_PIN }; val 482 drivers/regulator/lp8788-buck.c val[id]); val 157 drivers/regulator/lp8788-ldo.c u8 val, addr = LP8788_DLDO1_TIMESTEP + id; val 159 drivers/regulator/lp8788-ldo.c if (lp8788_read_byte(ldo->lp, addr, &val)) val 162 drivers/regulator/lp8788-ldo.c val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S; val 164 drivers/regulator/lp8788-ldo.c return ENABLE_TIME_USEC * val; val 95 drivers/regulator/ltc3676.c int mask, val; val 103 drivers/regulator/ltc3676.c val = 0; /* select DVBxA */ val 106 drivers/regulator/ltc3676.c val = LTC3676_DVBxA_REF_SELECT; /* select DVBxB */ val 115 drivers/regulator/ltc3676.c mask, val); val 103 drivers/regulator/max77620-regulator.c unsigned int val; val 106 drivers/regulator/max77620-regulator.c ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val); val 113 drivers/regulator/max77620-regulator.c return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; val 120 drivers/regulator/max77620-regulator.c unsigned int val; val 134 drivers/regulator/max77620-regulator.c ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val); val 140 drivers/regulator/max77620-regulator.c ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; val 168 drivers/regulator/max77620-regulator.c unsigned int val = 0; val 184 drivers/regulator/max77620-regulator.c val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT); val 190 drivers/regulator/max77620-regulator.c val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT); val 196 drivers/regulator/max77620-regulator.c mask, val); val 240 drivers/regulator/max77620-regulator.c unsigned int val, addr; val 254 drivers/regulator/max77620-regulator.c ret = regmap_read(pmic->rmap, addr, &val); val 261 drivers/regulator/max77620-regulator.c return (val & mask) >> shift; val 318 drivers/regulator/max77620-regulator.c unsigned int val; val 324 drivers/regulator/max77620-regulator.c val = 0; val 326 drivers/regulator/max77620-regulator.c val = 1; val 328 drivers/regulator/max77620-regulator.c val = 2; val 330 drivers/regulator/max77620-regulator.c val = 3; val 331 drivers/regulator/max77620-regulator.c val <<= MAX77620_SD_SR_SHIFT; val 335 drivers/regulator/max77620-regulator.c val = 1; val 337 drivers/regulator/max77620-regulator.c val = 0; val 341 drivers/regulator/max77620-regulator.c ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, mask, val); val 356 drivers/regulator/max77620-regulator.c u8 val, mask; val 367 drivers/regulator/max77620-regulator.c val = rpdata->power_ok ? mask : 0; val 370 drivers/regulator/max77620-regulator.c mask, val); val 495 drivers/regulator/max77620-regulator.c u8 val; val 520 drivers/regulator/max77620-regulator.c val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0; val 522 drivers/regulator/max77620-regulator.c MAX77620_SD_FPWM_MASK, val); val 548 drivers/regulator/max77620-regulator.c unsigned int val; val 557 drivers/regulator/max77620-regulator.c ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &val); val 563 drivers/regulator/max77620-regulator.c fpwm = !!(val & MAX77620_SD_FPWM_MASK); val 71 drivers/regulator/max77650-regulator.c int val, rv, en; val 76 drivers/regulator/max77650-regulator.c rv = regmap_read(map, rdesc->regB, &val); val 80 drivers/regulator/max77650-regulator.c en = MAX77650_REGULATOR_EN_CTRL_BITS(val); val 335 drivers/regulator/max77650-regulator.c unsigned int val; val 353 drivers/regulator/max77650-regulator.c rv = regmap_read(map, MAX77650_REG_CID, &val); val 360 drivers/regulator/max77650-regulator.c switch (MAX77650_CID_BITS(val)) { val 122 drivers/regulator/max77686-regulator.c unsigned int val, shift; val 127 drivers/regulator/max77686-regulator.c val = MAX77686_OFF_PWRREQ; val 130 drivers/regulator/max77686-regulator.c rdev->desc->enable_mask, val << shift); val 134 drivers/regulator/max77686-regulator.c max77686->opmode[id] = val; val 143 drivers/regulator/max77686-regulator.c unsigned int val; val 152 drivers/regulator/max77686-regulator.c val = MAX77686_LDO_LOWPOWER_PWRREQ; val 155 drivers/regulator/max77686-regulator.c val = max77686_map_normal_mode(max77686, id); val 165 drivers/regulator/max77686-regulator.c val << MAX77686_OPMODE_SHIFT); val 169 drivers/regulator/max77686-regulator.c max77686->opmode[id] = val; val 177 drivers/regulator/max77686-regulator.c unsigned int val; val 183 drivers/regulator/max77686-regulator.c val = MAX77686_OFF_PWRREQ; val 186 drivers/regulator/max77686-regulator.c val = MAX77686_LDO_LOWPOWER_PWRREQ; val 189 drivers/regulator/max77686-regulator.c val = max77686_map_normal_mode(max77686, id); val 199 drivers/regulator/max77686-regulator.c val << MAX77686_OPMODE_SHIFT); val 203 drivers/regulator/max77686-regulator.c max77686->opmode[id] = val; val 61 drivers/regulator/max77693-regulator.c unsigned int val; val 76 drivers/regulator/max77693-regulator.c val = chg_min_uA + reg_data->uA_step * sel; val 77 drivers/regulator/max77693-regulator.c if (val > chg_max_uA) val 80 drivers/regulator/max77693-regulator.c return val; val 96 drivers/regulator/max77802-regulator.c unsigned int val = MAX77802_OFF_PWRREQ; val 101 drivers/regulator/max77802-regulator.c max77802->opmode[id] = val; val 103 drivers/regulator/max77802-regulator.c rdev->desc->enable_mask, val << shift); val 115 drivers/regulator/max77802-regulator.c unsigned int val; val 120 drivers/regulator/max77802-regulator.c val = MAX77802_OPMODE_LP; /* ON in Low Power Mode */ val 123 drivers/regulator/max77802-regulator.c val = MAX77802_OPMODE_NORMAL; /* ON in Normal Mode */ val 131 drivers/regulator/max77802-regulator.c max77802->opmode[id] = val; val 133 drivers/regulator/max77802-regulator.c rdev->desc->enable_mask, val << shift); val 165 drivers/regulator/max77802-regulator.c unsigned int val; val 186 drivers/regulator/max77802-regulator.c val = MAX77802_LP_PWRREQ; val 207 drivers/regulator/max77802-regulator.c rdev->desc->enable_mask, val << shift); val 528 drivers/regulator/max77802-regulator.c int i, val; val 548 drivers/regulator/max77802-regulator.c ret = regmap_read(iodev->regmap, regulators[i].enable_reg, &val); val 552 drivers/regulator/max77802-regulator.c val = MAX77802_OPMODE_NORMAL; val 554 drivers/regulator/max77802-regulator.c val = val >> shift & MAX77802_OPMODE_MASK; val 562 drivers/regulator/max77802-regulator.c if (val == MAX77802_STATUS_OFF) val 565 drivers/regulator/max77802-regulator.c max77802->opmode[id] = val; val 63 drivers/regulator/max8649.c unsigned int val; val 66 drivers/regulator/max8649.c ret = regmap_read(info->regmap, rdev->desc->vsel_reg, &val); val 69 drivers/regulator/max8649.c val &= MAX8649_VOL_MASK; val 70 drivers/regulator/max8649.c voltage = regulator_list_voltage_linear(rdev, (unsigned char)val); val 73 drivers/regulator/max8649.c ret = regmap_read(info->regmap, MAX8649_RAMP, &val); val 76 drivers/regulator/max8649.c ret = (val & MAX8649_RAMP_MASK) >> 5; val 104 drivers/regulator/max8649.c unsigned int val; val 107 drivers/regulator/max8649.c ret = regmap_read(info->regmap, rdev->desc->vsel_reg, &val); val 110 drivers/regulator/max8649.c if (val & MAX8649_FORCE_PWM) val 155 drivers/regulator/max8649.c unsigned int val; val 192 drivers/regulator/max8649.c ret = regmap_read(info->regmap, MAX8649_CHIP_ID1, &val); val 198 drivers/regulator/max8649.c dev_info(info->dev, "Detected MAX8649 (ID:%x)\n", val); val 73 drivers/regulator/max8660.c static int max8660_write(struct max8660 *max8660, u8 reg, u8 mask, u8 val) val 80 drivers/regulator/max8660.c u8 reg_val = (max8660->shadow_regs[reg] & mask) | val; val 101 drivers/regulator/max8660.c u8 val = max8660->shadow_regs[MAX8660_OVER1]; val 104 drivers/regulator/max8660.c return !!(val & mask); val 199 drivers/regulator/max8660.c u8 val = max8660->shadow_regs[MAX8660_OVER2]; val 202 drivers/regulator/max8660.c return !!(val & mask); val 280 drivers/regulator/max8907-regulator.c unsigned int val; val 299 drivers/regulator/max8907-regulator.c ret = regmap_read(max8907->regmap_gen, MAX8907_REG_II2RR, &val); val 303 drivers/regulator/max8907-regulator.c if ((val & MAX8907_II2RR_VERSION_MASK) == val 340 drivers/regulator/max8907-regulator.c &val); val 344 drivers/regulator/max8907-regulator.c if ((val & MAX8907_MASK_LDO_SEQ) != val 349 drivers/regulator/max8907-regulator.c &val); val 353 drivers/regulator/max8907-regulator.c if ((val & (MAX8907_MASK_OUT5V_VINEN | val 299 drivers/regulator/max8973-regulator.c unsigned int val; val 303 drivers/regulator/max8973-regulator.c val = MAX8973_CKKADV_TRIP_75mV_PER_US; val 305 drivers/regulator/max8973-regulator.c val = MAX8973_CKKADV_TRIP_150mV_PER_US; val 307 drivers/regulator/max8973-regulator.c val = MAX8973_CKKADV_TRIP_DISABLE; val 310 drivers/regulator/max8973-regulator.c MAX8973_CKKADV_TRIP_MASK, val); val 476 drivers/regulator/max8973-regulator.c unsigned int val; val 479 drivers/regulator/max8973-regulator.c ret = regmap_read(mchip->regmap, MAX8973_CHIPID1, &val); val 486 drivers/regulator/max8973-regulator.c if (val & MAX77621_CHIPID_TJINT_S) val 152 drivers/regulator/max8997-regulator.c int val; val 161 drivers/regulator/max8997-regulator.c val = desc->min + desc->step * selector; val 162 drivers/regulator/max8997-regulator.c if (val > desc->max) val 165 drivers/regulator/max8997-regulator.c return val; val 247 drivers/regulator/max8997-regulator.c u8 val; val 253 drivers/regulator/max8997-regulator.c ret = max8997_read_reg(i2c, reg, &val); val 257 drivers/regulator/max8997-regulator.c return (val & mask) == pattern; val 357 drivers/regulator/max8997-regulator.c u8 val; val 363 drivers/regulator/max8997-regulator.c ret = max8997_read_reg(i2c, reg, &val); val 367 drivers/regulator/max8997-regulator.c val >>= shift; val 368 drivers/regulator/max8997-regulator.c val &= mask; val 370 drivers/regulator/max8997-regulator.c return val; val 404 drivers/regulator/max8997-regulator.c u8 val = 0x0; val 417 drivers/regulator/max8997-regulator.c val = 0x1; val 419 drivers/regulator/max8997-regulator.c val = 0x0; val 428 drivers/regulator/max8997-regulator.c val = lb; val 431 drivers/regulator/max8997-regulator.c val = 0xf; val 437 drivers/regulator/max8997-regulator.c *selector = val; val 439 drivers/regulator/max8997-regulator.c ret = max8997_update_reg(i2c, reg, val << shift, mask); val 78 drivers/regulator/max8998.c u8 val; val 84 drivers/regulator/max8998.c ret = max8998_read_reg(i2c, reg, &val); val 88 drivers/regulator/max8998.c return val & (1 << shift); val 185 drivers/regulator/max8998.c u8 val; val 191 drivers/regulator/max8998.c ret = max8998_read_reg(i2c, reg, &val); val 195 drivers/regulator/max8998.c val >>= shift; val 196 drivers/regulator/max8998.c val &= mask; val 198 drivers/regulator/max8998.c return val; val 338 drivers/regulator/max8998.c u8 val = 0; val 345 drivers/regulator/max8998.c ret = max8998_read_reg(i2c, MAX8998_REG_ONOFF4, &val); val 351 drivers/regulator/max8998.c if (max8998->iodev->type == TYPE_MAX8998 && !(val & MAX8998_ENRAMP)) val 356 drivers/regulator/max8998.c return DIV_ROUND_UP(difference, (val & 0x0f) + 1); val 295 drivers/regulator/mc13783-regulator.c u32 val) val 301 drivers/regulator/mc13783-regulator.c BUG_ON(val & ~mask); val 310 drivers/regulator/mc13783-regulator.c (priv->powermisc_pwgt_state & ~mask) | val; val 314 drivers/regulator/mc13783-regulator.c valread = (valread & ~mask) | val; val 366 drivers/regulator/mc13783-regulator.c unsigned int val; val 369 drivers/regulator/mc13783-regulator.c ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val); val 377 drivers/regulator/mc13783-regulator.c val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) | val 380 drivers/regulator/mc13783-regulator.c return (val & mc13xxx_regulators[id].enable_bit) != 0; val 303 drivers/regulator/mc13892-regulator.c u32 val) val 309 drivers/regulator/mc13892-regulator.c BUG_ON(val & ~mask); val 318 drivers/regulator/mc13892-regulator.c (priv->powermisc_pwgt_state & ~mask) | val; val 322 drivers/regulator/mc13892-regulator.c valread = (valread & ~mask) | val; val 372 drivers/regulator/mc13892-regulator.c unsigned int val; val 375 drivers/regulator/mc13892-regulator.c ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val); val 383 drivers/regulator/mc13892-regulator.c val = (val & ~MC13892_POWERMISC_PWGTSPI_M) | val 386 drivers/regulator/mc13892-regulator.c return (val & mc13892_regulators[id].enable_bit) != 0; val 402 drivers/regulator/mc13892-regulator.c unsigned int val, selector; val 408 drivers/regulator/mc13892-regulator.c mc13892_regulators[id].vsel_reg, &val); val 424 drivers/regulator/mc13892-regulator.c selector = val & mc13892_regulators[id].vsel_mask; val 427 drivers/regulator/mc13892-regulator.c (val & MC13892_SWITCHERS0_SWxHI)) { val 432 drivers/regulator/mc13892-regulator.c __func__, id, val, selector); val 510 drivers/regulator/mc13892-regulator.c unsigned int val; val 513 drivers/regulator/mc13892-regulator.c ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val); val 519 drivers/regulator/mc13892-regulator.c if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN) val 537 drivers/regulator/mc13892-regulator.c u32 val; val 558 drivers/regulator/mc13892-regulator.c ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val); val 563 drivers/regulator/mc13892-regulator.c if ((val & 0x0000FFFF) == 0x45d0) { val 57 drivers/regulator/mc13xxx-regulator-core.c unsigned int val; val 59 drivers/regulator/mc13xxx-regulator-core.c ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val); val 63 drivers/regulator/mc13xxx-regulator-core.c return (val & mc13xxx_regulators[id].enable_bit) != 0; val 83 drivers/regulator/mc13xxx-regulator-core.c unsigned int val; val 88 drivers/regulator/mc13xxx-regulator-core.c mc13xxx_regulators[id].vsel_reg, &val); val 92 drivers/regulator/mc13xxx-regulator-core.c val = (val & mc13xxx_regulators[id].vsel_mask) val 95 drivers/regulator/mc13xxx-regulator-core.c dev_dbg(rdev_get_dev(rdev), "%s id: %d val: %d\n", __func__, id, val); val 97 drivers/regulator/mc13xxx-regulator-core.c BUG_ON(val >= mc13xxx_regulators[id].desc.n_voltages); val 99 drivers/regulator/mc13xxx-regulator-core.c return rdev->desc->volt_table[val]; val 178 drivers/regulator/mcp16502.c unsigned int val; val 185 drivers/regulator/mcp16502.c ret = regmap_read(rdev->regmap, reg, &val); val 189 drivers/regulator/mcp16502.c switch (val & MCP16502_MODE) { val 209 drivers/regulator/mcp16502.c int val; val 218 drivers/regulator/mcp16502.c val = MCP16502_MODE_FPWM; val 221 drivers/regulator/mcp16502.c val = MCP16502_MODE_AUTO_PFM; val 227 drivers/regulator/mcp16502.c reg = regmap_update_bits(rdev->regmap, reg, MCP16502_MODE, val); val 245 drivers/regulator/mcp16502.c unsigned int val; val 248 drivers/regulator/mcp16502.c &val); val 252 drivers/regulator/mcp16502.c if (val & MCP16502_FLT) val 254 drivers/regulator/mcp16502.c else if (val & MCP16502_ENS) val 256 drivers/regulator/mcp16502.c else if (!(val & MCP16502_ENS)) val 174 drivers/regulator/mt6323-regulator.c int ret, val = 0; val 185 drivers/regulator/mt6323-regulator.c val = MT6323_LDO_MODE_LP; val 188 drivers/regulator/mt6323-regulator.c val = MT6323_LDO_MODE_NORMAL; val 194 drivers/regulator/mt6323-regulator.c val <<= ffs(info->modeset_mask) - 1; val 197 drivers/regulator/mt6323-regulator.c info->modeset_mask, val); val 204 drivers/regulator/mt6323-regulator.c unsigned int val; val 215 drivers/regulator/mt6323-regulator.c ret = regmap_read(rdev->regmap, info->modeset_reg, &val); val 219 drivers/regulator/mt6323-regulator.c val &= info->modeset_mask; val 220 drivers/regulator/mt6323-regulator.c val >>= ffs(info->modeset_mask) - 1; val 222 drivers/regulator/mt6323-regulator.c if (val & 0x1) val 332 drivers/regulator/mt6358-regulator.c int val; val 336 drivers/regulator/mt6358-regulator.c val = MT6358_BUCK_MODE_FORCE_PWM; val 339 drivers/regulator/mt6358-regulator.c val = MT6358_BUCK_MODE_AUTO; val 347 drivers/regulator/mt6358-regulator.c info->modeset_shift, val); val 349 drivers/regulator/mt6358-regulator.c val <<= info->modeset_shift; val 352 drivers/regulator/mt6358-regulator.c info->modeset_mask, val); val 186 drivers/regulator/mt6380-regulator.c int ret, val = 0; val 191 drivers/regulator/mt6380-regulator.c val = MT6380_REGULATOR_MODE_AUTO; val 194 drivers/regulator/mt6380-regulator.c val = MT6380_REGULATOR_MODE_FORCE_PWM; val 200 drivers/regulator/mt6380-regulator.c val <<= ffs(info->modeset_mask) - 1; val 203 drivers/regulator/mt6380-regulator.c info->modeset_mask, val); val 210 drivers/regulator/mt6380-regulator.c unsigned int val; val 215 drivers/regulator/mt6380-regulator.c ret = regmap_read(rdev->regmap, info->modeset_reg, &val); val 219 drivers/regulator/mt6380-regulator.c val &= info->modeset_mask; val 220 drivers/regulator/mt6380-regulator.c val >>= ffs(info->modeset_mask) - 1; val 222 drivers/regulator/mt6380-regulator.c switch (val) { val 153 drivers/regulator/mt6397-regulator.c int ret, val; val 157 drivers/regulator/mt6397-regulator.c val = MT6397_BUCK_MODE_FORCE_PWM; val 160 drivers/regulator/mt6397-regulator.c val = MT6397_BUCK_MODE_AUTO; val 169 drivers/regulator/mt6397-regulator.c info->modeset_shift, val); val 171 drivers/regulator/mt6397-regulator.c val <<= info->modeset_shift; val 173 drivers/regulator/mt6397-regulator.c info->modeset_mask, val); val 814 drivers/regulator/palmas-regulator.c unsigned int val = 0; val 821 drivers/regulator/palmas-regulator.c val = PALMAS_REGEN1_CTRL_MODE_SLEEP; val 824 drivers/regulator/palmas-regulator.c addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val); val 780 drivers/regulator/pfuze100-regulator.c int val; val 792 drivers/regulator/pfuze100-regulator.c desc->vsel_reg, &val); val 798 drivers/regulator/pfuze100-regulator.c if (val & sw_hi) { val 97 drivers/regulator/pv88060-regulator.c int val = 0; val 101 drivers/regulator/pv88060-regulator.c val = PV88060_BUCK_MODE_SYNC; val 104 drivers/regulator/pv88060-regulator.c val = PV88060_BUCK_MODE_AUTO; val 107 drivers/regulator/pv88060-regulator.c val = PV88060_BUCK_MODE_SLEEP; val 114 drivers/regulator/pv88060-regulator.c PV88060_BUCK_MODE_MASK, val); val 240 drivers/regulator/pv88080-regulator.c int val = 0; val 244 drivers/regulator/pv88080-regulator.c val = PV88080_BUCK_MODE_SYNC; val 247 drivers/regulator/pv88080-regulator.c val = PV88080_BUCK_MODE_AUTO; val 250 drivers/regulator/pv88080-regulator.c val = PV88080_BUCK_MODE_SLEEP; val 257 drivers/regulator/pv88080-regulator.c PV88080_BUCK1_MODE_MASK, val); val 119 drivers/regulator/pv88090-regulator.c int val = 0; val 123 drivers/regulator/pv88090-regulator.c val = PV88090_BUCK_MODE_SYNC; val 126 drivers/regulator/pv88090-regulator.c val = PV88090_BUCK_MODE_AUTO; val 129 drivers/regulator/pv88090-regulator.c val = PV88090_BUCK_MODE_SLEEP; val 136 drivers/regulator/pv88090-regulator.c PV88090_BUCK1_MODE_MASK, val); val 56 drivers/regulator/qcom_rpm-regulator.c u32 val[MAX_REQUEST_LEN]; val 196 drivers/regulator/qcom_rpm-regulator.c vreg->val[req->word] &= ~req->mask; val 197 drivers/regulator/qcom_rpm-regulator.c vreg->val[req->word] |= value << req->shift; val 202 drivers/regulator/qcom_rpm-regulator.c vreg->val, val 647 drivers/regulator/qcom_rpm-regulator.c vreg->val[req->word] &= ~req->mask; val 648 drivers/regulator/qcom_rpm-regulator.c vreg->val[req->word] |= value << req->shift; val 695 drivers/regulator/qcom_rpm-regulator.c u32 val; val 728 drivers/regulator/qcom_rpm-regulator.c ret = of_property_read_u32(node, key, &val); val 730 drivers/regulator/qcom_rpm-regulator.c val = QCOM_RPM_FORCE_MODE_NONE; val 743 drivers/regulator/qcom_rpm-regulator.c switch (val) { val 547 drivers/regulator/qcom_spmi-regulator.c static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val, val 550 drivers/regulator/qcom_spmi-regulator.c return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); val 959 drivers/regulator/qcom_spmi-regulator.c u8 val = 0; val 962 drivers/regulator/qcom_spmi-regulator.c val = mask; val 964 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); val 971 drivers/regulator/qcom_spmi-regulator.c u8 val; val 974 drivers/regulator/qcom_spmi-regulator.c ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1); val 975 drivers/regulator/qcom_spmi-regulator.c *enable = val & SPMI_COMMON_MODE_BYPASS_MASK; val 1021 drivers/regulator/qcom_spmi-regulator.c u8 val; val 1025 drivers/regulator/qcom_spmi-regulator.c val = SPMI_COMMON_MODE_HPM_MASK; val 1028 drivers/regulator/qcom_spmi-regulator.c val = SPMI_COMMON_MODE_AUTO_MASK; val 1031 drivers/regulator/qcom_spmi-regulator.c val = 0; val 1035 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); val 1043 drivers/regulator/qcom_spmi-regulator.c u8 val; val 1047 drivers/regulator/qcom_spmi-regulator.c val = SPMI_FTSMPS426_MODE_HPM_MASK; val 1050 drivers/regulator/qcom_spmi-regulator.c val = SPMI_FTSMPS426_MODE_AUTO_MASK; val 1053 drivers/regulator/qcom_spmi-regulator.c val = SPMI_FTSMPS426_MODE_LPM_MASK; val 1059 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); val 223 drivers/regulator/rk808-regulator.c unsigned int val; val 231 drivers/regulator/rk808-regulator.c &val); val 235 drivers/regulator/rk808-regulator.c val &= rdev->desc->vsel_mask; val 236 drivers/regulator/rk808-regulator.c val >>= ffs(rdev->desc->vsel_mask) - 1; val 238 drivers/regulator/rk808-regulator.c return val; val 245 drivers/regulator/rk808-regulator.c unsigned int old_sel, tmp, val, mask = rdev->desc->vsel_mask; val 247 drivers/regulator/rk808-regulator.c ret = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &val); val 251 drivers/regulator/rk808-regulator.c tmp = val & ~mask; val 252 drivers/regulator/rk808-regulator.c old_sel = val & mask; val 263 drivers/regulator/rk808-regulator.c val = old_sel << (ffs(mask) - 1); val 264 drivers/regulator/rk808-regulator.c val |= tmp; val 272 drivers/regulator/rk808-regulator.c ret = regmap_write(rdev->regmap, rdev->desc->vsel_reg, val); val 277 drivers/regulator/rk808-regulator.c val = tmp | sel; val 278 drivers/regulator/rk808-regulator.c ret = regmap_write(rdev->regmap, rdev->desc->vsel_reg, val); val 493 drivers/regulator/rk808-regulator.c unsigned int id_slp, msk, val; val 508 drivers/regulator/rk808-regulator.c val = msk; val 510 drivers/regulator/rk808-regulator.c val = 0; val 512 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, msk, val); val 565 drivers/regulator/rk808-regulator.c unsigned int val; val 568 drivers/regulator/rk808-regulator.c err = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &val); val 572 drivers/regulator/rk808-regulator.c if (val & FPWM_MODE) val 580 drivers/regulator/rk808-regulator.c unsigned int val; val 583 drivers/regulator/rk808-regulator.c ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val); val 588 drivers/regulator/rk808-regulator.c val |= (rdev->desc->enable_mask & 0xf0); val 589 drivers/regulator/rk808-regulator.c val &= rdev->desc->enable_mask; val 593 drivers/regulator/rk808-regulator.c return val != rdev->desc->enable_val; val 594 drivers/regulator/rk808-regulator.c return (val == 0); val 597 drivers/regulator/rk808-regulator.c return val == rdev->desc->enable_val; val 598 drivers/regulator/rk808-regulator.c return val != 0; val 232 drivers/regulator/s2mps11.c unsigned int val; val 237 drivers/regulator/s2mps11.c val = S2MPS14_ENABLE_SUSPEND; val 239 drivers/regulator/s2mps11.c val = rdev->desc->enable_mask; val 244 drivers/regulator/s2mps11.c val = S2MPS14_ENABLE_SUSPEND; val 246 drivers/regulator/s2mps11.c val = S2MPS14_ENABLE_EXT_CONTROL; val 248 drivers/regulator/s2mps11.c val = rdev->desc->enable_mask; val 252 drivers/regulator/s2mps11.c val = S2MPU02_ENABLE_SUSPEND; val 254 drivers/regulator/s2mps11.c val = rdev->desc->enable_mask; val 261 drivers/regulator/s2mps11.c rdev->desc->enable_mask, val); val 267 drivers/regulator/s2mps11.c unsigned int val, state; val 313 drivers/regulator/s2mps11.c ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val); val 325 drivers/regulator/s2mps11.c if (!(val & rdev->desc->enable_mask)) val 895 drivers/regulator/s5m8767.c unsigned int val; val 898 drivers/regulator/s5m8767.c val = S5M8767_DVS_BUCK_RAMP_5; val 901 drivers/regulator/s5m8767.c val = S5M8767_DVS_BUCK_RAMP_10; val 904 drivers/regulator/s5m8767.c val = S5M8767_DVS_BUCK_RAMP_25; val 907 drivers/regulator/s5m8767.c val = S5M8767_DVS_BUCK_RAMP_50; val 910 drivers/regulator/s5m8767.c val = S5M8767_DVS_BUCK_RAMP_100; val 913 drivers/regulator/s5m8767.c val = S5M8767_DVS_BUCK_RAMP_10; val 918 drivers/regulator/s5m8767.c val << S5M8767_DVS_BUCK_RAMP_SHIFT); val 251 drivers/regulator/slg51000-regulator.c unsigned int reg, val; val 283 drivers/regulator/slg51000-regulator.c ret = regmap_read(chip->regmap, reg, &val); val 293 drivers/regulator/slg51000-regulator.c if (val & SLG51000_SEL_VRANGE_MASK) val 310 drivers/regulator/slg51000-regulator.c ret = regmap_read(chip->regmap, reg, &val); val 317 drivers/regulator/slg51000-regulator.c if (val & SLG51000_SEL_BYP_MODE_MASK) { val 426 drivers/regulator/slg51000-regulator.c unsigned int val = 0; val 429 drivers/regulator/slg51000-regulator.c ret = regmap_read(chip->regmap, SLG51000_SYSCTL_FAULT_LOG1, &val); val 435 drivers/regulator/slg51000-regulator.c if (val & SLG51000_FLT_OVER_TEMP_MASK) val 437 drivers/regulator/slg51000-regulator.c if (val & SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK) val 439 drivers/regulator/slg51000-regulator.c if (val & SLG51000_FLT_RST_MASK) val 441 drivers/regulator/slg51000-regulator.c if (val & SLG51000_FLT_POR_MASK) val 49 drivers/regulator/stm32-pwr.c u32 val; val 51 drivers/regulator/stm32-pwr.c val = readl_relaxed(priv->base + REG_PWR_CR3); val 53 drivers/regulator/stm32-pwr.c return (val & priv->ready_mask); val 59 drivers/regulator/stm32-pwr.c u32 val; val 61 drivers/regulator/stm32-pwr.c val = readl_relaxed(priv->base + REG_PWR_CR3); val 63 drivers/regulator/stm32-pwr.c return (val & rdev->desc->enable_mask); val 70 drivers/regulator/stm32-pwr.c u32 val; val 72 drivers/regulator/stm32-pwr.c val = readl_relaxed(priv->base + REG_PWR_CR3); val 73 drivers/regulator/stm32-pwr.c val |= rdev->desc->enable_mask; val 74 drivers/regulator/stm32-pwr.c writel_relaxed(val, priv->base + REG_PWR_CR3); val 77 drivers/regulator/stm32-pwr.c ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val, val 89 drivers/regulator/stm32-pwr.c u32 val; val 91 drivers/regulator/stm32-pwr.c val = readl_relaxed(priv->base + REG_PWR_CR3); val 92 drivers/regulator/stm32-pwr.c val &= ~rdev->desc->enable_mask; val 93 drivers/regulator/stm32-pwr.c writel_relaxed(val, priv->base + REG_PWR_CR3); val 96 drivers/regulator/stm32-pwr.c ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val, val 44 drivers/regulator/stm32-vrefbuf.c u32 val; val 53 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); val 54 drivers/regulator/stm32-vrefbuf.c val = (val & ~STM32_HIZ) | STM32_ENVR; val 55 drivers/regulator/stm32-vrefbuf.c writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); val 63 drivers/regulator/stm32-vrefbuf.c ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, val 64 drivers/regulator/stm32-vrefbuf.c val & STM32_VRR, 650, 10000); val 67 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); val 68 drivers/regulator/stm32-vrefbuf.c val = (val & ~STM32_ENVR) | STM32_HIZ; val 69 drivers/regulator/stm32-vrefbuf.c writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); val 81 drivers/regulator/stm32-vrefbuf.c u32 val; val 90 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); val 91 drivers/regulator/stm32-vrefbuf.c val &= ~STM32_ENVR; val 92 drivers/regulator/stm32-vrefbuf.c writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); val 123 drivers/regulator/stm32-vrefbuf.c u32 val; val 132 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); val 133 drivers/regulator/stm32-vrefbuf.c val = (val & ~STM32_VRS) | FIELD_PREP(STM32_VRS, sel); val 134 drivers/regulator/stm32-vrefbuf.c writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); val 145 drivers/regulator/stm32-vrefbuf.c u32 val; val 154 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); val 155 drivers/regulator/stm32-vrefbuf.c ret = FIELD_GET(STM32_VRS, val); val 61 drivers/regulator/sy8824x.c u32 val; val 64 drivers/regulator/sy8824x.c ret = regmap_read(rdev->regmap, cfg->mode_reg, &val); val 67 drivers/regulator/sy8824x.c if (val & SY8824C_MODE) val 131 drivers/regulator/ti-abb-regulator.c u32 val; val 133 drivers/regulator/ti-abb-regulator.c val = readl(reg); val 134 drivers/regulator/ti-abb-regulator.c val &= ~mask; val 135 drivers/regulator/ti-abb-regulator.c val |= (value << __ffs(mask)) & mask; val 136 drivers/regulator/ti-abb-regulator.c writel(val, reg); val 138 drivers/regulator/ti-abb-regulator.c return val; val 222 drivers/regulator/ti-abb-regulator.c u32 val; val 224 drivers/regulator/ti-abb-regulator.c val = readl(abb->ldo_base); val 226 drivers/regulator/ti-abb-regulator.c val &= ~(abb->ldovbb_override_mask | abb->ldovbb_vset_mask); val 231 drivers/regulator/ti-abb-regulator.c val |= abb->ldovbb_override_mask; val 232 drivers/regulator/ti-abb-regulator.c val |= info->vset << __ffs(abb->ldovbb_vset_mask); val 236 drivers/regulator/ti-abb-regulator.c writel(val, abb->ldo_base); val 179 drivers/regulator/tps62360-regulator.c int val; val 185 drivers/regulator/tps62360-regulator.c val = FORCE_PWM_ENABLE; val 189 drivers/regulator/tps62360-regulator.c val = 0; val 198 drivers/regulator/tps62360-regulator.c REG_VSET0 + tps->curr_vset_id, FORCE_PWM_ENABLE, val); val 209 drivers/regulator/tps62360-regulator.c REG_VSET0 + i, FORCE_PWM_ENABLE, val); val 123 drivers/regulator/tps6507x-regulator.c u8 val; val 126 drivers/regulator/tps6507x-regulator.c err = tps->mfd->read_dev(tps->mfd, reg, 1, &val); val 131 drivers/regulator/tps6507x-regulator.c return val; val 134 drivers/regulator/tps6507x-regulator.c static inline int tps6507x_pmic_write(struct tps6507x_pmic *tps, u8 reg, u8 val) val 136 drivers/regulator/tps6507x-regulator.c return tps->mfd->write_dev(tps->mfd, reg, 1, &val); val 199 drivers/regulator/tps6507x-regulator.c static int tps6507x_pmic_reg_write(struct tps6507x_pmic *tps, u8 reg, u8 val) val 205 drivers/regulator/tps6507x-regulator.c err = tps6507x_pmic_write(tps, reg, val); val 228 drivers/regulator/tps65217-regulator.c unsigned int val; val 256 drivers/regulator/tps65217-regulator.c ret = tps65217_reg_read(tps, regulators[i].bypass_reg, &val); val 257 drivers/regulator/tps65217-regulator.c tps->strobes[i] = val & regulators[i].bypass_mask; val 318 drivers/regulator/tps65218-regulator.c unsigned int val; val 341 drivers/regulator/tps65218-regulator.c ret = regmap_read(tps->regmap, regulators[i].bypass_reg, &val); val 345 drivers/regulator/tps65218-regulator.c tps->strobes[i] = val & regulators[i].bypass_mask; val 195 drivers/regulator/tps6524x-regulator.c static int __write_reg(struct tps6524x *hw, int reg, int val) val 198 drivers/regulator/tps6524x-regulator.c u16 cmd = CMD_WRITE(reg), out = val; val 237 drivers/regulator/tps6524x-regulator.c static int __rmw_reg(struct tps6524x *hw, int reg, int mask, int val) val 246 drivers/regulator/tps6524x-regulator.c ret |= val; val 253 drivers/regulator/tps6524x-regulator.c static int rmw_protect(struct tps6524x *hw, int reg, int mask, int val) val 265 drivers/regulator/tps6524x-regulator.c ret = __rmw_reg(hw, reg, mask, val); val 293 drivers/regulator/tps6524x-regulator.c int val) val 295 drivers/regulator/tps6524x-regulator.c if (val & ~field->mask) val 300 drivers/regulator/tps6524x-regulator.c val << field->shift); val 533 drivers/regulator/tps80031-regulator.c unsigned val = 0; val 535 drivers/regulator/tps80031-regulator.c val = MISC2_LDOUSB_IN_VSYS; val 537 drivers/regulator/tps80031-regulator.c val = MISC2_LDOUSB_IN_PMID; val 540 drivers/regulator/tps80031-regulator.c TPS80031_MISC2, val, val 136 drivers/regulator/twl-regulator.c u8 val; val 139 drivers/regulator/twl-regulator.c ret = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val, val 144 drivers/regulator/twl-regulator.c if (!(val & PB_I2C_BUSY)) val 157 drivers/regulator/twl-regulator.c u8 val; val 161 drivers/regulator/twl-regulator.c ret = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val, val 167 drivers/regulator/twl-regulator.c ret = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val | PB_I2C_BWEN, val 191 drivers/regulator/twl-regulator.c return twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val, val 124 drivers/regulator/twl6030-regulator.c int grp = 0, val; val 135 drivers/regulator/twl6030-regulator.c val = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_STATE); val 136 drivers/regulator/twl6030-regulator.c val = TWL6030_CFG_STATE_APP(val); val 138 drivers/regulator/twl6030-regulator.c return grp && (val == TWL6030_CFG_STATE_ON); val 182 drivers/regulator/twl6030-regulator.c int val; val 184 drivers/regulator/twl6030-regulator.c val = twlreg_grp(rdev); val 185 drivers/regulator/twl6030-regulator.c if (val < 0) val 186 drivers/regulator/twl6030-regulator.c return val; val 188 drivers/regulator/twl6030-regulator.c val = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_STATE); val 190 drivers/regulator/twl6030-regulator.c switch (TWL6030_CFG_STATE_APP(val)) { val 210 drivers/regulator/twl6030-regulator.c int val; val 219 drivers/regulator/twl6030-regulator.c val = grp << TWL6030_CFG_STATE_GRP_SHIFT; val 223 drivers/regulator/twl6030-regulator.c val |= TWL6030_CFG_STATE_ON; val 226 drivers/regulator/twl6030-regulator.c val |= TWL6030_CFG_STATE_SLEEP; val 233 drivers/regulator/twl6030-regulator.c return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_STATE, val); val 118 drivers/regulator/virtual.c long val; val 120 drivers/regulator/virtual.c if (kstrtol(buf, 10, &val) != 0) val 125 drivers/regulator/virtual.c data->min_uV = val; val 144 drivers/regulator/virtual.c long val; val 146 drivers/regulator/virtual.c if (kstrtol(buf, 10, &val) != 0) val 151 drivers/regulator/virtual.c data->max_uV = val; val 170 drivers/regulator/virtual.c long val; val 172 drivers/regulator/virtual.c if (kstrtol(buf, 10, &val) != 0) val 177 drivers/regulator/virtual.c data->min_uA = val; val 196 drivers/regulator/virtual.c long val; val 198 drivers/regulator/virtual.c if (kstrtol(buf, 10, &val) != 0) val 203 drivers/regulator/virtual.c data->max_uA = val; val 65 drivers/regulator/wm831x-dcdc.c int val; val 67 drivers/regulator/wm831x-dcdc.c val = wm831x_reg_read(wm831x, reg); val 68 drivers/regulator/wm831x-dcdc.c if (val < 0) val 69 drivers/regulator/wm831x-dcdc.c return val; val 71 drivers/regulator/wm831x-dcdc.c val = (val & WM831X_DC1_ON_MODE_MASK) >> WM831X_DC1_ON_MODE_SHIFT; val 73 drivers/regulator/wm831x-dcdc.c switch (val) { val 91 drivers/regulator/wm831x-dcdc.c int val; val 95 drivers/regulator/wm831x-dcdc.c val = WM831X_DCDC_MODE_FAST; val 98 drivers/regulator/wm831x-dcdc.c val = WM831X_DCDC_MODE_NORMAL; val 101 drivers/regulator/wm831x-dcdc.c val = WM831X_DCDC_MODE_STANDBY; val 104 drivers/regulator/wm831x-dcdc.c val = WM831X_DCDC_MODE_IDLE; val 111 drivers/regulator/wm831x-dcdc.c val << WM831X_DC1_ON_MODE_SHIFT); val 267 drivers/regulator/wm8350-regulator.c u16 val; val 295 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK; val 296 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, volt_reg, val | sel); val 304 drivers/regulator/wm8350-regulator.c u16 val; val 308 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER) val 311 drivers/regulator/wm8350-regulator.c val | wm8350->pmic.dcdc1_hib_mode); val 314 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER) val 317 drivers/regulator/wm8350-regulator.c val | wm8350->pmic.dcdc3_hib_mode); val 320 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER) val 323 drivers/regulator/wm8350-regulator.c val | wm8350->pmic.dcdc4_hib_mode); val 326 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER) val 329 drivers/regulator/wm8350-regulator.c val | wm8350->pmic.dcdc6_hib_mode); val 344 drivers/regulator/wm8350-regulator.c u16 val; val 348 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER); val 349 drivers/regulator/wm8350-regulator.c wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; val 351 drivers/regulator/wm8350-regulator.c val | WM8350_DCDC_HIB_MODE_DIS); val 354 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER); val 355 drivers/regulator/wm8350-regulator.c wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; val 357 drivers/regulator/wm8350-regulator.c val | WM8350_DCDC_HIB_MODE_DIS); val 360 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER); val 361 drivers/regulator/wm8350-regulator.c wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; val 363 drivers/regulator/wm8350-regulator.c val | WM8350_DCDC_HIB_MODE_DIS); val 366 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER); val 367 drivers/regulator/wm8350-regulator.c wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; val 369 drivers/regulator/wm8350-regulator.c val | WM8350_DCDC_HIB_MODE_DIS); val 384 drivers/regulator/wm8350-regulator.c u16 val; val 388 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL) val 390 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val | val 394 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL) val 396 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val | val 409 drivers/regulator/wm8350-regulator.c u16 val; val 413 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL) val 415 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val | val 419 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL) val 421 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val | val 482 drivers/regulator/wm8350-regulator.c u16 val; val 508 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK; val 509 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, volt_reg, val | sel); val 517 drivers/regulator/wm8350-regulator.c u16 val; val 537 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK; val 538 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, volt_reg, val); val 546 drivers/regulator/wm8350-regulator.c u16 val; val 566 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK; val 567 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS); val 575 drivers/regulator/wm8350-regulator.c u16 val; val 607 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, slot_reg) & val 611 drivers/regulator/wm8350-regulator.c val | (start << WM8350_DC1_ENSLOT_SHIFT) | val 622 drivers/regulator/wm8350-regulator.c u16 val; val 648 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK; val 649 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6))); val 657 drivers/regulator/wm8350-regulator.c u16 val; val 664 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL) val 667 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val | val 674 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL) val 677 drivers/regulator/wm8350-regulator.c wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val | val 725 drivers/regulator/wm8350-regulator.c u16 val; val 733 drivers/regulator/wm8350-regulator.c val = 1 << (dcdc - WM8350_DCDC_1); val 738 drivers/regulator/wm8350-regulator.c wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); val 739 drivers/regulator/wm8350-regulator.c wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); val 744 drivers/regulator/wm8350-regulator.c wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); val 745 drivers/regulator/wm8350-regulator.c wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); val 751 drivers/regulator/wm8350-regulator.c wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); val 752 drivers/regulator/wm8350-regulator.c wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); val 757 drivers/regulator/wm8350-regulator.c wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); val 1112 drivers/regulator/wm8350-regulator.c u16 val; val 1120 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER); val 1121 drivers/regulator/wm8350-regulator.c wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; val 1124 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER); val 1125 drivers/regulator/wm8350-regulator.c wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; val 1128 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER); val 1129 drivers/regulator/wm8350-regulator.c wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; val 1132 drivers/regulator/wm8350-regulator.c val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER); val 1133 drivers/regulator/wm8350-regulator.c wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; val 102 drivers/remoteproc/qcom_q6v5_adsp.c unsigned int val; val 106 drivers/remoteproc/qcom_q6v5_adsp.c val = readl(adsp->qdsp6ss_base + RET_CFG_REG); val 107 drivers/remoteproc/qcom_q6v5_adsp.c val |= 0x1; val 108 drivers/remoteproc/qcom_q6v5_adsp.c writel(val, adsp->qdsp6ss_base + RET_CFG_REG); val 114 drivers/remoteproc/qcom_q6v5_adsp.c adsp->halt_lpass + LPASS_PWR_ON_REG, &val); val 115 drivers/remoteproc/qcom_q6v5_adsp.c if (ret || !val) val 120 drivers/remoteproc/qcom_q6v5_adsp.c &val); val 121 drivers/remoteproc/qcom_q6v5_adsp.c if (ret || val) val 131 drivers/remoteproc/qcom_q6v5_adsp.c adsp->halt_lpass + LPASS_HALTACK_REG, &val); val 132 drivers/remoteproc/qcom_q6v5_adsp.c if (ret || val || time_after(jiffies, timeout)) val 139 drivers/remoteproc/qcom_q6v5_adsp.c adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val); val 140 drivers/remoteproc/qcom_q6v5_adsp.c if (ret || !val) val 177 drivers/remoteproc/qcom_q6v5_adsp.c unsigned int val; val 216 drivers/remoteproc/qcom_q6v5_adsp.c val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); val 424 drivers/remoteproc/qcom_q6v5_mss.c s32 val; val 428 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG); val 429 drivers/remoteproc/qcom_q6v5_mss.c if (val) val 438 drivers/remoteproc/qcom_q6v5_mss.c return val; val 445 drivers/remoteproc/qcom_q6v5_mss.c s32 val; val 449 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); val 450 drivers/remoteproc/qcom_q6v5_mss.c if (val < 0) val 453 drivers/remoteproc/qcom_q6v5_mss.c if (!status && val) val 455 drivers/remoteproc/qcom_q6v5_mss.c else if (status && val == status) val 464 drivers/remoteproc/qcom_q6v5_mss.c return val; val 469 drivers/remoteproc/qcom_q6v5_mss.c u32 val; val 474 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_SLEEP); val 475 drivers/remoteproc/qcom_q6v5_mss.c val |= 0x1; val 476 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_SLEEP); val 479 drivers/remoteproc/qcom_q6v5_mss.c val, !(val & BIT(31)), 1, val 492 drivers/remoteproc/qcom_q6v5_mss.c val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); val 507 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_RESET_REG); val 508 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; val 509 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_RESET_REG); val 512 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); val 513 drivers/remoteproc/qcom_q6v5_mss.c val |= 0x1; val 514 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); val 518 drivers/remoteproc/qcom_q6v5_mss.c val, !(val & BIT(31)), 1, val 526 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 527 drivers/remoteproc/qcom_q6v5_mss.c val |= QDSP6v56_BHS_ON; val 528 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 529 drivers/remoteproc/qcom_q6v5_mss.c val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 533 drivers/remoteproc/qcom_q6v5_mss.c val |= QDSP6v56_LDO_BYP; val 534 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 537 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 538 drivers/remoteproc/qcom_q6v5_mss.c val &= ~QDSP6v56_CLAMP_QMC_MEM; val 539 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 542 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; val 543 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 546 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); val 548 drivers/remoteproc/qcom_q6v5_mss.c val |= BIT(i); val 549 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + val 556 drivers/remoteproc/qcom_q6v5_mss.c val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); val 560 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 561 drivers/remoteproc/qcom_q6v5_mss.c val &= ~QDSP6v56_CLAMP_WL; val 562 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 565 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_RESET_REG); val 566 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; val 567 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_RESET_REG); val 570 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 571 drivers/remoteproc/qcom_q6v5_mss.c val |= QDSS_BHS_ON | QDSS_LDO_BYP; val 572 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 573 drivers/remoteproc/qcom_q6v5_mss.c val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 579 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 580 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | val 582 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 583 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_L2DATA_SLP_NRET_N_2; val 584 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 585 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_L2DATA_SLP_NRET_N_1; val 586 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 587 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_L2DATA_SLP_NRET_N_0; val 588 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 591 drivers/remoteproc/qcom_q6v5_mss.c val &= ~Q6SS_CLAMP_IO; val 592 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 595 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_RESET_REG); val 596 drivers/remoteproc/qcom_q6v5_mss.c val &= ~Q6SS_CORE_ARES; val 597 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_RESET_REG); val 600 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); val 601 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_CLK_ENABLE; val 602 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); val 605 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_RESET_REG); val 606 drivers/remoteproc/qcom_q6v5_mss.c val &= ~Q6SS_STOP_CORE; val 607 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_RESET_REG); val 629 drivers/remoteproc/qcom_q6v5_mss.c unsigned int val; val 633 drivers/remoteproc/qcom_q6v5_mss.c ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); val 634 drivers/remoteproc/qcom_q6v5_mss.c if (!ret && val) val 643 drivers/remoteproc/qcom_q6v5_mss.c ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val); val 644 drivers/remoteproc/qcom_q6v5_mss.c if (ret || val || time_after(jiffies, timeout)) val 650 drivers/remoteproc/qcom_q6v5_mss.c ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); val 651 drivers/remoteproc/qcom_q6v5_mss.c if (ret || !val) val 861 drivers/remoteproc/qcom_q6v5_mss.c u32 val; val 872 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 873 drivers/remoteproc/qcom_q6v5_mss.c val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL | val 875 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); val 99 drivers/remoteproc/qcom_q6v5_wcss.c u32 val; val 103 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_RESET_REG); val 104 drivers/remoteproc/qcom_q6v5_wcss.c val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; val 105 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_RESET_REG); val 108 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_XO_CBCR); val 109 drivers/remoteproc/qcom_q6v5_wcss.c val |= 0x1; val 110 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_XO_CBCR); val 114 drivers/remoteproc/qcom_q6v5_wcss.c val, !(val & BIT(31)), 1, val 122 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); val 123 drivers/remoteproc/qcom_q6v5_wcss.c val |= Q6SS_BHS_ON; val 124 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 128 drivers/remoteproc/qcom_q6v5_wcss.c val |= Q6SS_LDO_BYP; val 129 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 132 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); val 133 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_CLAMP_QMC_MEM; val 134 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 137 drivers/remoteproc/qcom_q6v5_wcss.c val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; val 138 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 141 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); val 143 drivers/remoteproc/qcom_q6v5_wcss.c val |= BIT(i); val 144 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); val 150 drivers/remoteproc/qcom_q6v5_wcss.c val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); val 154 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); val 155 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_CLAMP_WL; val 156 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 159 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_CLAMP_IO; val 160 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 163 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_RESET_REG); val 164 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_CORE_ARES; val 165 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_RESET_REG); val 168 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); val 169 drivers/remoteproc/qcom_q6v5_wcss.c val |= Q6SS_CLK_ENABLE; val 170 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); val 173 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_RESET_REG); val 174 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_STOP_CORE; val 175 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_RESET_REG); val 241 drivers/remoteproc/qcom_q6v5_wcss.c unsigned int val; val 245 drivers/remoteproc/qcom_q6v5_wcss.c ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); val 246 drivers/remoteproc/qcom_q6v5_wcss.c if (!ret && val) val 255 drivers/remoteproc/qcom_q6v5_wcss.c ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val); val 256 drivers/remoteproc/qcom_q6v5_wcss.c if (ret || val || time_after(jiffies, timeout)) val 262 drivers/remoteproc/qcom_q6v5_wcss.c ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); val 263 drivers/remoteproc/qcom_q6v5_wcss.c if (ret || !val) val 273 drivers/remoteproc/qcom_q6v5_wcss.c u32 val; val 279 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->rmb_base + SSCAON_CONFIG); val 280 drivers/remoteproc/qcom_q6v5_wcss.c val |= SSCAON_ENABLE; val 281 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->rmb_base + SSCAON_CONFIG); val 284 drivers/remoteproc/qcom_q6v5_wcss.c val |= SSCAON_BUS_EN; val 285 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~SSCAON_BUS_MUX_MASK; val 286 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->rmb_base + SSCAON_CONFIG); val 289 drivers/remoteproc/qcom_q6v5_wcss.c val |= BIT(1); val 290 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->rmb_base + SSCAON_CONFIG); val 294 drivers/remoteproc/qcom_q6v5_wcss.c val, (val & 0xffff) == 0x400, 1000, val 306 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->rmb_base + SSCAON_CONFIG); val 307 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~SSCAON_ENABLE; val 308 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->rmb_base + SSCAON_CONFIG); val 319 drivers/remoteproc/qcom_q6v5_wcss.c u32 val; val 326 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); val 327 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_CLK_ENABLE; val 328 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); val 331 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); val 332 drivers/remoteproc/qcom_q6v5_wcss.c val |= Q6SS_CLAMP_IO; val 333 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 336 drivers/remoteproc/qcom_q6v5_wcss.c val |= QDSS_BHS_ON; val 337 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 340 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_L2DATA_STBY_N; val 341 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 344 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_SLP_RET_N; val 345 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 349 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); val 350 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~BIT(i); val 351 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); val 356 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); val 357 drivers/remoteproc/qcom_q6v5_wcss.c val |= Q6SS_CLAMP_QMC_MEM; val 358 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 361 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~Q6SS_BHS_ON; val 362 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); val 367 drivers/remoteproc/qcom_q6v5_wcss.c val, !(val & BHS_EN_REST_ACK), 1000, val 156 drivers/remoteproc/qcom_wcnss.c u32 val; val 159 drivers/remoteproc/qcom_wcnss.c val = readl(wcnss->spare_out); val 160 drivers/remoteproc/qcom_wcnss.c val |= WCNSS_SPARE_NVBIN_DLND; val 161 drivers/remoteproc/qcom_wcnss.c writel(val, wcnss->spare_out); val 166 drivers/remoteproc/qcom_wcnss.c u32 val; val 171 drivers/remoteproc/qcom_wcnss.c val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN; val 172 drivers/remoteproc/qcom_wcnss.c writel(val, wcnss->pmu_cfg); val 175 drivers/remoteproc/qcom_wcnss.c val &= ~WCNSS_PMU_XO_MODE_MASK; val 177 drivers/remoteproc/qcom_wcnss.c val |= WCNSS_PMU_XO_MODE_48 << 1; val 179 drivers/remoteproc/qcom_wcnss.c val |= WCNSS_PMU_XO_MODE_19p2 << 1; val 180 drivers/remoteproc/qcom_wcnss.c writel(val, wcnss->pmu_cfg); val 183 drivers/remoteproc/qcom_wcnss.c val |= WCNSS_PMU_IRIS_RESET; val 184 drivers/remoteproc/qcom_wcnss.c writel(val, wcnss->pmu_cfg); val 191 drivers/remoteproc/qcom_wcnss.c val &= ~WCNSS_PMU_IRIS_RESET; val 192 drivers/remoteproc/qcom_wcnss.c writel(val, wcnss->pmu_cfg); val 195 drivers/remoteproc/qcom_wcnss.c val |= WCNSS_PMU_IRIS_XO_CFG; val 196 drivers/remoteproc/qcom_wcnss.c writel(val, wcnss->pmu_cfg); val 203 drivers/remoteproc/qcom_wcnss.c val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP; val 204 drivers/remoteproc/qcom_wcnss.c val &= ~WCNSS_PMU_IRIS_XO_CFG; val 205 drivers/remoteproc/qcom_wcnss.c writel(val, wcnss->pmu_cfg); val 117 drivers/remoteproc/st_slim_rproc.c u32 val; val 120 drivers/remoteproc/st_slim_rproc.c val = SLIM_CLK_GATE_DIS | SLIM_CLK_GATE_RESET; val 121 drivers/remoteproc/st_slim_rproc.c writel(val, slim_rproc->slimcore + SLIM_CLK_GATE_OFST); val 157 drivers/remoteproc/st_slim_rproc.c u32 val; val 168 drivers/remoteproc/st_slim_rproc.c val = readl(slim_rproc->slimcore + SLIM_EN_OFST); val 169 drivers/remoteproc/st_slim_rproc.c if (val & SLIM_EN_RUN) val 343 drivers/remoteproc/stm32_rproc.c int val, err; val 345 drivers/remoteproc/stm32_rproc.c val = hold ? HOLD_BOOT : RELEASE_BOOT; val 349 drivers/remoteproc/stm32_rproc.c hold_boot.reg, val, 0, 0, 0, 0, &smc_res); val 353 drivers/remoteproc/stm32_rproc.c hold_boot.mask, val); val 31 drivers/reset/reset-ath79.c u32 val; val 34 drivers/reset/reset-ath79.c val = readl(ath79_reset->base); val 36 drivers/reset/reset-ath79.c val |= BIT(id); val 38 drivers/reset/reset-ath79.c val &= ~BIT(id); val 39 drivers/reset/reset-ath79.c writel(val, ath79_reset->base); val 62 drivers/reset/reset-ath79.c u32 val; val 64 drivers/reset/reset-ath79.c val = readl(ath79_reset->base); val 66 drivers/reset/reset-ath79.c return !!(val & BIT(id)); val 40 drivers/reset/reset-lantiq.c u32 val; val 43 drivers/reset/reset-lantiq.c ret = regmap_read(priv->regmap, priv->status_offset, &val); val 47 drivers/reset/reset-lantiq.c return !!(val & BIT(status)); val 73 drivers/reset/reset-lantiq.c u32 val = assert ? BIT(set) : 0; val 77 drivers/reset/reset-lantiq.c val); val 36 drivers/reset/reset-meson-audio-arb.c u32 val; val 41 drivers/reset/reset-meson-audio-arb.c val = readl(arb->regs); val 44 drivers/reset/reset-meson-audio-arb.c val &= ~BIT(arb->reset_bits[id]); val 46 drivers/reset/reset-meson-audio-arb.c val |= BIT(arb->reset_bits[id]); val 48 drivers/reset/reset-meson-audio-arb.c writel(val, arb->regs); val 57 drivers/reset/reset-meson-audio-arb.c u32 val; val 61 drivers/reset/reset-meson-audio-arb.c val = readl(arb->regs); val 63 drivers/reset/reset-meson-audio-arb.c return !(val & BIT(arb->reset_bits[id])); val 260 drivers/reset/reset-uniphier.c unsigned int mask, val; val 268 drivers/reset/reset-uniphier.c val = mask; val 270 drivers/reset/reset-uniphier.c val = ~mask; val 273 drivers/reset/reset-uniphier.c val = ~val; val 275 drivers/reset/reset-uniphier.c return regmap_write_bits(priv->regmap, p->reg, mask, val); val 301 drivers/reset/reset-uniphier.c unsigned int val; val 307 drivers/reset/reset-uniphier.c ret = regmap_read(priv->regmap, p->reg, &val); val 311 drivers/reset/reset-uniphier.c asserted = !!(val & BIT(p->bit)); val 49 drivers/reset/reset-zynqmp.c int val, err; val 51 drivers/reset/reset-zynqmp.c err = priv->eemi_ops->reset_get_status(ZYNQMP_RESET_ID + id, &val); val 55 drivers/reset/reset-zynqmp.c return val; val 1178 drivers/rpmsg/qcom_glink_native.c __be32 *val = defaults; val 1186 drivers/rpmsg/qcom_glink_native.c val = prop->value; val 1192 drivers/rpmsg/qcom_glink_native.c size = be32_to_cpup(val++); val 1193 drivers/rpmsg/qcom_glink_native.c num_intents = be32_to_cpup(val++); val 86 drivers/rtc/rtc-ab-eoz9.c int val; val 88 drivers/rtc/rtc-ab-eoz9.c ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val); val 95 drivers/rtc/rtc-ab-eoz9.c if (val & ABEOZ9_REG_CTRL_STATUS_PON) { val 100 drivers/rtc/rtc-ab-eoz9.c if (val & ABEOZ9_REG_CTRL_STATUS_V1F) { val 106 drivers/rtc/rtc-ab-eoz9.c if ((val & ABEOZ9_REG_CTRL_STATUS_V2F)) { val 278 drivers/rtc/rtc-ab-eoz9.c unsigned int val; val 280 drivers/rtc/rtc-ab-eoz9.c ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val); val 284 drivers/rtc/rtc-ab-eoz9.c if ((val & ABEOZ9_REG_CTRL_STATUS_V1F) || val 285 drivers/rtc/rtc-ab-eoz9.c (val & ABEOZ9_REG_CTRL_STATUS_V2F)) { val 293 drivers/rtc/rtc-ab-eoz9.c ret = regmap_read(regmap, ABEOZ9_REG_REG_TEMP, &val); val 296 drivers/rtc/rtc-ab-eoz9.c *temp = 1000 * (val + ABEOZ953_TEMP_MIN); val 604 drivers/rtc/rtc-abx80x.c u8 val = ABX8XX_WDT_WDS | timeout_bits(timeout); val 610 drivers/rtc/rtc-abx80x.c return i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_WDT, val); val 107 drivers/rtc/rtc-ac100.c { .val = 0, .div = 1 }, val 108 drivers/rtc/rtc-ac100.c { .val = 1, .div = 2 }, val 109 drivers/rtc/rtc-ac100.c { .val = 2, .div = 4 }, val 110 drivers/rtc/rtc-ac100.c { .val = 3, .div = 8 }, val 111 drivers/rtc/rtc-ac100.c { .val = 4, .div = 16 }, val 112 drivers/rtc/rtc-ac100.c { .val = 5, .div = 32 }, val 113 drivers/rtc/rtc-ac100.c { .val = 6, .div = 64 }, val 114 drivers/rtc/rtc-ac100.c { .val = 7, .div = 122 }, val 155 drivers/rtc/rtc-ac100.c tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); val 240 drivers/rtc/rtc-ac100.c pre_div = ac100_clkout_prediv[pre_div].val; val 444 drivers/rtc/rtc-ac100.c unsigned int val; val 446 drivers/rtc/rtc-ac100.c val = en ? AC100_ALM_INT_ENABLE : 0; val 448 drivers/rtc/rtc-ac100.c return regmap_write(regmap, AC100_ALM_INT_ENA, val); val 457 drivers/rtc/rtc-ac100.c unsigned int val; val 460 drivers/rtc/rtc-ac100.c ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val); val 464 drivers/rtc/rtc-ac100.c alrm->enabled = !!(val & AC100_ALM_INT_ENABLE); val 528 drivers/rtc/rtc-ac100.c unsigned int val = 0; val 534 drivers/rtc/rtc-ac100.c ret = regmap_read(regmap, AC100_ALM_INT_STA, &val); val 538 drivers/rtc/rtc-ac100.c if (val & AC100_ALM_INT_ENABLE) { val 543 drivers/rtc/rtc-ac100.c ret = regmap_write(regmap, AC100_ALM_INT_STA, val); val 104 drivers/rtc/rtc-armada38x.c static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset) val 108 drivers/rtc/rtc-armada38x.c writel(val, rtc->regs + offset); val 191 drivers/rtc/rtc-armada38x.c u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); val 193 drivers/rtc/rtc-armada38x.c writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT); val 198 drivers/rtc/rtc-armada38x.c u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); val 200 drivers/rtc/rtc-armada38x.c writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT); val 267 drivers/rtc/rtc-armada38x.c u32 val; val 272 drivers/rtc/rtc-armada38x.c val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN; val 276 drivers/rtc/rtc-armada38x.c alrm->enabled = val ? 1 : 0; val 327 drivers/rtc/rtc-armada38x.c u32 val; val 336 drivers/rtc/rtc-armada38x.c val = rtc->data->read_rtc_reg(rtc, reg_irq); val 344 drivers/rtc/rtc-armada38x.c if (val & RTC_IRQ_FREQ_EN) { val 345 drivers/rtc/rtc-armada38x.c if (val & RTC_IRQ_FREQ_1HZ) val 37 drivers/rtc/rtc-at91rm9200.c #define at91_rtc_write(field, val) \ val 38 drivers/rtc/rtc-at91rm9200.c writel_relaxed((val), at91_rtc_regs + field) val 83 drivers/rtc/rtc-at91sam9.c #define rtt_writel(rtc, field, val) \ val 84 drivers/rtc/rtc-at91sam9.c writel((val), (rtc)->rtt + AT91_RTT_ ## field) val 88 drivers/rtc/rtc-at91sam9.c unsigned int val; val 90 drivers/rtc/rtc-at91sam9.c regmap_read(rtc->gpbr, rtc->gpbr_offset, &val); val 92 drivers/rtc/rtc-at91sam9.c return val; val 95 drivers/rtc/rtc-at91sam9.c static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val) val 97 drivers/rtc/rtc-at91sam9.c regmap_write(rtc->gpbr, rtc->gpbr_offset, val); val 35 drivers/rtc/rtc-bq4802.c static void bq4802_write_io(struct bq4802 *p, int off, u8 val) val 37 drivers/rtc/rtc-bq4802.c outb(val, p->ioport + off); val 45 drivers/rtc/rtc-bq4802.c static void bq4802_write_mem(struct bq4802 *p, int off, u8 val) val 47 drivers/rtc/rtc-bq4802.c writeb(val, p->regs + off); val 55 drivers/rtc/rtc-bq4802.c u8 val; val 59 drivers/rtc/rtc-bq4802.c val = p->read(p, 0x0e); val 60 drivers/rtc/rtc-bq4802.c p->write(p, 0xe, val | 0x08); val 71 drivers/rtc/rtc-bq4802.c p->write(p, 0x0e, val); val 95 drivers/rtc/rtc-bq4802.c u8 sec, min, hrs, day, mon, yrs, century, val; val 119 drivers/rtc/rtc-bq4802.c val = p->read(p, 0x0e); val 120 drivers/rtc/rtc-bq4802.c p->write(p, 0x0e, val | 0x08); val 130 drivers/rtc/rtc-bq4802.c p->write(p, 0x0e, val); val 200 drivers/rtc/rtc-cmos.c static inline void cmos_write_bank2(unsigned char val, unsigned char addr) val 203 drivers/rtc/rtc-cmos.c outb(val, RTC_PORT(3)); val 215 drivers/rtc/rtc-cmos.c static inline void cmos_write_bank2(unsigned char val, unsigned char addr) val 593 drivers/rtc/rtc-cmos.c static int cmos_nvram_read(void *priv, unsigned int off, void *val, val 596 drivers/rtc/rtc-cmos.c unsigned char *buf = val; val 614 drivers/rtc/rtc-cmos.c static int cmos_nvram_write(void *priv, unsigned int off, void *val, val 618 drivers/rtc/rtc-cmos.c unsigned char *buf = val; val 1375 drivers/rtc/rtc-cmos.c const __be32 *val; val 1380 drivers/rtc/rtc-cmos.c val = of_get_property(node, "ctrl-reg", NULL); val 1381 drivers/rtc/rtc-cmos.c if (val) val 1382 drivers/rtc/rtc-cmos.c CMOS_WRITE(be32_to_cpup(val), RTC_CONTROL); val 1384 drivers/rtc/rtc-cmos.c val = of_get_property(node, "freq-reg", NULL); val 1385 drivers/rtc/rtc-cmos.c if (val) val 1386 drivers/rtc/rtc-cmos.c CMOS_WRITE(be32_to_cpup(val), RTC_FREQ_SELECT); val 277 drivers/rtc/rtc-da9063.c unsigned int val; val 293 drivers/rtc/rtc-da9063.c &val); val 297 drivers/rtc/rtc-da9063.c if (val & config->rtc_event_alarm_mask) val 113 drivers/rtc/rtc-davinci.c u32 val, u32 addr) val 115 drivers/rtc/rtc-davinci.c writel(val, davinci_rtc->base + addr); val 130 drivers/rtc/rtc-davinci.c unsigned long val, u8 addr) val 135 drivers/rtc/rtc-davinci.c rtcif_write(davinci_rtc, val, PRTCIF_LDATA); val 43 drivers/rtc/rtc-digicolor.c u8 val; val 50 drivers/rtc/rtc-digicolor.c rtc->regs + DC_RTC_CONTROL, val, val 51 drivers/rtc/rtc-digicolor.c !(val & DC_RTC_GO_BUSY), CMD_DELAY_US, CMD_TIMEOUT_US); val 59 drivers/rtc/rtc-digicolor.c static int dc_rtc_read(struct dc_rtc *rtc, unsigned long *val) val 79 drivers/rtc/rtc-digicolor.c *val = reference + time1; val 83 drivers/rtc/rtc-digicolor.c static int dc_rtc_write(struct dc_rtc *rtc, u32 val) val 87 drivers/rtc/rtc-digicolor.c writel_relaxed(val, rtc->regs + DC_RTC_REFERENCE); val 40 drivers/rtc/rtc-ds1286.c unsigned char val; val 44 drivers/rtc/rtc-ds1286.c val = ds1286_rtc_read(priv, RTC_CMD); val 46 drivers/rtc/rtc-ds1286.c val &= ~RTC_TDM; val 48 drivers/rtc/rtc-ds1286.c val |= RTC_TDM; val 49 drivers/rtc/rtc-ds1286.c ds1286_rtc_write(priv, val, RTC_CMD); val 61 drivers/rtc/rtc-ds1286.c unsigned char val; val 67 drivers/rtc/rtc-ds1286.c val = ds1286_rtc_read(priv, RTC_CMD); val 68 drivers/rtc/rtc-ds1286.c val |= RTC_WAM; val 69 drivers/rtc/rtc-ds1286.c ds1286_rtc_write(priv, val, RTC_CMD); val 75 drivers/rtc/rtc-ds1286.c val = ds1286_rtc_read(priv, RTC_CMD); val 76 drivers/rtc/rtc-ds1286.c val &= ~RTC_WAM; val 77 drivers/rtc/rtc-ds1286.c ds1286_rtc_write(priv, val, RTC_CMD); val 811 drivers/rtc/rtc-ds1307.c u8 val; val 815 drivers/rtc/rtc-ds1307.c val = ctrl_reg & M41TXX_M_CALIBRATION; val 819 drivers/rtc/rtc-ds1307.c *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); val 821 drivers/rtc/rtc-ds1307.c *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); val 1188 drivers/rtc/rtc-ds1307.c static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, val 1195 drivers/rtc/rtc-ds1307.c val, bytes); val 1198 drivers/rtc/rtc-ds1307.c static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, val 1205 drivers/rtc/rtc-ds1307.c val, bytes); val 96 drivers/rtc/rtc-ds1343.c int val; val 98 drivers/rtc/rtc-ds1343.c if (copy_from_user(&val, (int __user *)arg, sizeof(int))) val 101 drivers/rtc/rtc-ds1343.c return regmap_write(priv->map, DS1343_TRICKLE_REG, val); val 152 drivers/rtc/rtc-ds1343.c static int ds1343_nvram_write(void *priv, unsigned int off, void *val, val 157 drivers/rtc/rtc-ds1343.c return regmap_bulk_write(ds1343->map, DS1343_NVRAM + off, val, bytes); val 160 drivers/rtc/rtc-ds1343.c static int ds1343_nvram_read(void *priv, unsigned int off, void *val, val 165 drivers/rtc/rtc-ds1343.c return regmap_bulk_read(ds1343->map, DS1343_NVRAM + off, val, bytes); val 432 drivers/rtc/rtc-ds1374.c u32 val; val 435 drivers/rtc/rtc-ds1374.c ret = ds1374_read_rtc(save_client, &val, DS1374_REG_WDALM0, 3); val 102 drivers/rtc/rtc-ds1511.c rtc_write(uint8_t val, uint32_t reg) val 104 drivers/rtc/rtc-ds1511.c writeb(val, ds1511_base + (reg * reg_spacing)); val 108 drivers/rtc/rtc-ds1511.c rtc_write_alarm(uint8_t val, enum ds1511reg reg) val 110 drivers/rtc/rtc-ds1511.c rtc_write((val | 0x80), reg); val 224 drivers/rtc/rtc-ds1553.c static int ds1553_nvram_read(void *priv, unsigned int pos, void *val, val 230 drivers/rtc/rtc-ds1553.c u8 *buf = val; val 237 drivers/rtc/rtc-ds1553.c static int ds1553_nvram_write(void *priv, unsigned int pos, void *val, val 243 drivers/rtc/rtc-ds1553.c u8 *buf = val; val 76 drivers/rtc/rtc-ds1685.c ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask) val 79 drivers/rtc/rtc-ds1685.c return (bcd2bin(val) & bcd_mask); val 81 drivers/rtc/rtc-ds1685.c return (val & bin_mask); val 94 drivers/rtc/rtc-ds1685.c ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask) val 97 drivers/rtc/rtc-ds1685.c return (bin2bcd(val) & bcd_mask); val 99 drivers/rtc/rtc-ds1685.c return (val & bin_mask); val 812 drivers/rtc/rtc-ds1685.c static int ds1685_nvram_read(void *priv, unsigned int pos, void *val, val 818 drivers/rtc/rtc-ds1685.c u8 *buf = val; val 879 drivers/rtc/rtc-ds1685.c static int ds1685_nvram_write(void *priv, unsigned int pos, void *val, val 885 drivers/rtc/rtc-ds1685.c u8 *buf = val; val 118 drivers/rtc/rtc-ds1742.c static int ds1742_nvram_read(void *priv, unsigned int pos, void *val, val 123 drivers/rtc/rtc-ds1742.c u8 *buf = val; val 130 drivers/rtc/rtc-ds1742.c static int ds1742_nvram_write(void *priv, unsigned int pos, void *val, val 135 drivers/rtc/rtc-ds1742.c u8 *buf = val; val 464 drivers/rtc/rtc-ds3232.c static int ds3232_nvmem_read(void *priv, unsigned int offset, void *val, val 470 drivers/rtc/rtc-ds3232.c val, bytes); val 473 drivers/rtc/rtc-ds3232.c static int ds3232_nvmem_write(void *priv, unsigned int offset, void *val, val 479 drivers/rtc/rtc-ds3232.c val, bytes); val 54 drivers/rtc/rtc-fsl-ftm-alarm.c static inline void rtc_writel(struct ftm_rtc *dev, u32 reg, u32 val) val 57 drivers/rtc/rtc-fsl-ftm-alarm.c iowrite32be(val, dev->base + reg); val 59 drivers/rtc/rtc-fsl-ftm-alarm.c iowrite32(val, dev->base + reg); val 64 drivers/rtc/rtc-fsl-ftm-alarm.c u32 val; val 67 drivers/rtc/rtc-fsl-ftm-alarm.c val = rtc_readl(rtc, FTM_SC); val 68 drivers/rtc/rtc-fsl-ftm-alarm.c val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK); val 69 drivers/rtc/rtc-fsl-ftm-alarm.c val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ)); val 70 drivers/rtc/rtc-fsl-ftm-alarm.c rtc_writel(rtc, FTM_SC, val); val 75 drivers/rtc/rtc-fsl-ftm-alarm.c u32 val; val 78 drivers/rtc/rtc-fsl-ftm-alarm.c val = rtc_readl(rtc, FTM_SC); val 79 drivers/rtc/rtc-fsl-ftm-alarm.c val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK); val 80 drivers/rtc/rtc-fsl-ftm-alarm.c rtc_writel(rtc, FTM_SC, val); val 114 drivers/rtc/rtc-fsl-ftm-alarm.c u32 val; val 116 drivers/rtc/rtc-fsl-ftm-alarm.c val = rtc_readl(rtc, FTM_SC); val 117 drivers/rtc/rtc-fsl-ftm-alarm.c val |= FTM_SC_TOIE; val 118 drivers/rtc/rtc-fsl-ftm-alarm.c rtc_writel(rtc, FTM_SC, val); val 123 drivers/rtc/rtc-fsl-ftm-alarm.c u32 val; val 125 drivers/rtc/rtc-fsl-ftm-alarm.c val = rtc_readl(rtc, FTM_SC); val 126 drivers/rtc/rtc-fsl-ftm-alarm.c val &= ~FTM_SC_TOIE; val 127 drivers/rtc/rtc-fsl-ftm-alarm.c rtc_writel(rtc, FTM_SC, val); val 170 drivers/rtc/rtc-imxdi.c static void di_write_busy_wait(const struct imxdi_dev *imxdi, u32 val, val 174 drivers/rtc/rtc-imxdi.c writel(val, imxdi->ioaddr + reg); val 496 drivers/rtc/rtc-imxdi.c static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg) val 510 drivers/rtc/rtc-imxdi.c writel(val, imxdi->ioaddr + reg); val 521 drivers/rtc/rtc-imxdi.c "val = 0x%08x reg = 0x%08x\n", val, reg); val 83 drivers/rtc/rtc-isl12022.c uint8_t reg, uint8_t val) val 85 drivers/rtc/rtc-isl12022.c uint8_t data[2] = { reg, val }; val 46 drivers/rtc/rtc-isl12026.c u8 val; val 59 drivers/rtc/rtc-isl12026.c .buf = &val val 68 drivers/rtc/rtc-isl12026.c ret = val; val 136 drivers/rtc/rtc-isl12026.c static int isl12026_write_reg(struct i2c_client *client, int reg, u8 val) val 139 drivers/rtc/rtc-isl12026.c u8 op[3] = {0, reg, val}; val 279 drivers/rtc/rtc-isl12026.c void *val, size_t bytes) val 293 drivers/rtc/rtc-isl12026.c .buf = val val 323 drivers/rtc/rtc-isl12026.c void *val, size_t bytes) val 327 drivers/rtc/rtc-isl12026.c u8 *v = val; val 105 drivers/rtc/rtc-jz4740.c uint32_t val) val 114 drivers/rtc/rtc-jz4740.c writel(val, rtc->base + reg); val 60 drivers/rtc/rtc-lpc24xx.c #define rtc_writel(dev, reg, val) writel((val), (dev)->rtc_base + (reg)) val 44 drivers/rtc/rtc-lpc32xx.c #define rtc_writel(dev, reg, val) \ val 45 drivers/rtc/rtc-lpc32xx.c __raw_writel((val), (dev)->rtc_base + (reg)) val 252 drivers/rtc/rtc-m41t80.c int val; val 254 drivers/rtc/rtc-m41t80.c val = i2c_smbus_read_byte_data(client, M41T80_REG_WDAY); val 255 drivers/rtc/rtc-m41t80.c if (val < 0) val 256 drivers/rtc/rtc-m41t80.c return val; val 258 drivers/rtc/rtc-m41t80.c buf[M41T80_REG_WDAY] |= (val & 0xf0); val 479 drivers/rtc/rtc-m41t80.c int reg, ret, val = 0; val 482 drivers/rtc/rtc-m41t80.c val = 1; val 484 drivers/rtc/rtc-m41t80.c val = 2; val 486 drivers/rtc/rtc-m41t80.c val = 15 - ilog2(rate); val 492 drivers/rtc/rtc-m41t80.c reg = (reg & 0x0f) | (val << 4); val 496 drivers/rtc/rtc-m41t80.c m41t80->freq = m41t80_decode_freq(val); val 26 drivers/rtc/rtc-m48t59.c #define M48T59_WRITE(val, reg) \ val 27 drivers/rtc/rtc-m48t59.c (pdata->write_byte(dev, pdata->offset + reg, val)) val 45 drivers/rtc/rtc-m48t59.c m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val) val 49 drivers/rtc/rtc-m48t59.c writeb(val, m48t59->ioaddr+ofs); val 68 drivers/rtc/rtc-m48t59.c u8 val; val 79 drivers/rtc/rtc-m48t59.c val = M48T59_READ(M48T59_WDAY); val 81 drivers/rtc/rtc-m48t59.c (val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) { val 90 drivers/rtc/rtc-m48t59.c tm->tm_wday = bcd2bin(val & 0x07); val 108 drivers/rtc/rtc-m48t59.c u8 val = 0; val 136 drivers/rtc/rtc-m48t59.c val = (M48T59_WDAY_CEB | M48T59_WDAY_CB); val 137 drivers/rtc/rtc-m48t59.c val |= (bin2bcd(tm->tm_wday) & 0x07); val 138 drivers/rtc/rtc-m48t59.c M48T59_WRITE(val, M48T59_WDAY); val 155 drivers/rtc/rtc-m48t59.c u8 val; val 173 drivers/rtc/rtc-m48t59.c val = M48T59_READ(M48T59_WDAY); val 174 drivers/rtc/rtc-m48t59.c if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) val 274 drivers/rtc/rtc-m48t59.c u8 val; val 277 drivers/rtc/rtc-m48t59.c val = M48T59_READ(M48T59_FLAGS); val 281 drivers/rtc/rtc-m48t59.c (val & M48T59_FLAGS_BF) ? "low" : "normal"); val 321 drivers/rtc/rtc-m48t59.c static int m48t59_nvram_read(void *priv, unsigned int offset, void *val, val 330 drivers/rtc/rtc-m48t59.c u8 *buf = val; val 342 drivers/rtc/rtc-m48t59.c static int m48t59_nvram_write(void *priv, unsigned int offset, void *val, val 351 drivers/rtc/rtc-m48t59.c u8 *buf = val; val 397 drivers/rtc/rtc-max77686.c unsigned int val; val 426 drivers/rtc/rtc-max77686.c ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val); val 433 drivers/rtc/rtc-max77686.c if (val) val 450 drivers/rtc/rtc-max77686.c info->drv_data->alarm_pending_status_reg, &val); val 457 drivers/rtc/rtc-max77686.c if (val & (1 << 4)) /* RTCA1 */ val 125 drivers/rtc/rtc-max8907.c unsigned int val; val 135 drivers/rtc/rtc-max8907.c ret = regmap_read(rtc->regmap, MAX8907_REG_ALARM0_CNTL, &val); val 139 drivers/rtc/rtc-max8907.c alrm->enabled = !!(val & 0x7f); val 182 drivers/rtc/rtc-max8997.c u8 val; val 206 drivers/rtc/rtc-max8997.c ret = max8997_read_reg(info->max8997->i2c, MAX8997_REG_STATUS1, &val); val 213 drivers/rtc/rtc-max8997.c if (val & (1 << 4)) /* RTCA1 */ val 369 drivers/rtc/rtc-max8997.c u8 val, mask; val 375 drivers/rtc/rtc-max8997.c val = (1 << WTSR_EN_SHIFT) | (3 << WTSRT_SHIFT); val 377 drivers/rtc/rtc-max8997.c val = 0; val 384 drivers/rtc/rtc-max8997.c ret = max8997_update_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, val, mask); val 397 drivers/rtc/rtc-max8997.c u8 val, mask; val 403 drivers/rtc/rtc-max8997.c val = (1 << SMPL_EN_SHIFT) | (0 << SMPLT_SHIFT); val 405 drivers/rtc/rtc-max8997.c val = 0; val 412 drivers/rtc/rtc-max8997.c ret = max8997_update_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, val, mask); val 421 drivers/rtc/rtc-max8997.c val = 0; val 422 drivers/rtc/rtc-max8997.c max8997_read_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, &val); val 423 drivers/rtc/rtc-max8997.c pr_info("WTSR_SMPL(0x%02x)\n", val); val 140 drivers/rtc/rtc-max8998.c u8 val; val 149 drivers/rtc/rtc-max8998.c ret = max8998_read_reg(info->rtc, MAX8998_ALARM0_CONF, &val); val 153 drivers/rtc/rtc-max8998.c alrm->enabled = !!val; val 155 drivers/rtc/rtc-max8998.c ret = max8998_read_reg(info->rtc, MAX8998_RTC_STATUS, &val); val 159 drivers/rtc/rtc-max8998.c if (val & ALARM0_STATUS) val 118 drivers/rtc/rtc-meson.c u32 tmp, val = 0; val 123 drivers/rtc/rtc-meson.c val <<= 1; val 126 drivers/rtc/rtc-meson.c val |= tmp & RTC_ADDR1_SDO; val 129 drivers/rtc/rtc-meson.c return val; val 135 drivers/rtc/rtc-meson.c u32 val; val 138 drivers/rtc/rtc-meson.c val = RTC_ADDR0_LINE_SDI | RTC_ADDR0_LINE_SEN | RTC_ADDR0_LINE_SCLK; val 139 drivers/rtc/rtc-meson.c regmap_update_bits(rtc->peripheral, RTC_ADDR0, val, 0); val 143 drivers/rtc/rtc-meson.c if (!regmap_read_poll_timeout(rtc->peripheral, RTC_ADDR1, val, val 144 drivers/rtc/rtc-meson.c val & RTC_ADDR1_S_READY, 10, val 280 drivers/rtc/rtc-mpc5121.c int val; val 283 drivers/rtc/rtc-mpc5121.c val = 1; val 285 drivers/rtc/rtc-mpc5121.c val = 0; val 287 drivers/rtc/rtc-mpc5121.c out_8(®s->alm_enable, val); val 288 drivers/rtc/rtc-mpc5121.c rtc->wkalarm.enabled = val; val 85 drivers/rtc/rtc-msm6242.c static inline void msm6242_write(struct msm6242_priv *priv, unsigned int val, val 88 drivers/rtc/rtc-msm6242.c __raw_writel(val, &priv->regs[reg]); val 91 drivers/rtc/rtc-msm6242.c static inline void msm6242_set(struct msm6242_priv *priv, unsigned int val, val 94 drivers/rtc/rtc-msm6242.c msm6242_write(priv, msm6242_read(priv, reg) | val, reg); val 97 drivers/rtc/rtc-msm6242.c static inline void msm6242_clear(struct msm6242_priv *priv, unsigned int val, val 100 drivers/rtc/rtc-msm6242.c msm6242_write(priv, msm6242_read(priv, reg) & ~val, reg); val 108 drivers/rtc/rtc-mt7622.c static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val) val 110 drivers/rtc/rtc-mt7622.c writel_relaxed(val, rtc->base + reg); val 120 drivers/rtc/rtc-mt7622.c u32 val; val 122 drivers/rtc/rtc-mt7622.c val = mtk_r32(rtc, reg); val 123 drivers/rtc/rtc-mt7622.c val &= ~mask; val 124 drivers/rtc/rtc-mt7622.c val |= set; val 125 drivers/rtc/rtc-mt7622.c mtk_w32(rtc, reg, val); val 128 drivers/rtc/rtc-mt7622.c static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val) val 130 drivers/rtc/rtc-mt7622.c mtk_rmw(rtc, reg, 0, val); val 133 drivers/rtc/rtc-mt7622.c static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val) val 135 drivers/rtc/rtc-mt7622.c mtk_rmw(rtc, reg, val, 0); val 243 drivers/rtc/rtc-mxc.c time64_t val; val 247 drivers/rtc/rtc-mxc.c val = get_alarm_or_time(dev, MXC_RTC_TIME); val 248 drivers/rtc/rtc-mxc.c } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); val 250 drivers/rtc/rtc-mxc.c rtc_time64_to_tm(val, tm); val 165 drivers/rtc/rtc-omap.c static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) val 167 drivers/rtc/rtc-omap.c writeb(val, rtc->base + reg); val 170 drivers/rtc/rtc-omap.c static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) val 172 drivers/rtc/rtc-omap.c writel(val, rtc->base + reg); val 417 drivers/rtc/rtc-omap.c u32 val; val 421 drivers/rtc/rtc-omap.c val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); val 422 drivers/rtc/rtc-omap.c rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); val 451 drivers/rtc/rtc-omap.c val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); val 453 drivers/rtc/rtc-omap.c val | OMAP_RTC_INTERRUPTS_IT_ALARM2); val 457 drivers/rtc/rtc-omap.c val = rtc_read(rtc, OMAP_RTC_STATUS_REG); val 458 drivers/rtc/rtc-omap.c if (!(val & OMAP_RTC_STATUS_ALARM2)) val 485 drivers/rtc/rtc-omap.c u32 val; val 491 drivers/rtc/rtc-omap.c val = rtc_readl(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG); val 492 drivers/rtc/rtc-omap.c val |= OMAP_RTC_PMIC_POWER_EN_EN | OMAP_RTC_PMIC_EXT_WKUP_POL(0) | val 494 drivers/rtc/rtc-omap.c rtc_writel(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG, val); val 603 drivers/rtc/rtc-omap.c u32 val; val 606 drivers/rtc/rtc-omap.c val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); val 610 drivers/rtc/rtc-omap.c if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin))) val 614 drivers/rtc/rtc-omap.c if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin)) val 631 drivers/rtc/rtc-omap.c u32 val; val 636 drivers/rtc/rtc-omap.c val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); val 639 drivers/rtc/rtc-omap.c val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin); val 648 drivers/rtc/rtc-omap.c val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin); val 650 drivers/rtc/rtc-omap.c val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin); val 653 drivers/rtc/rtc-omap.c val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin); val 663 drivers/rtc/rtc-omap.c rtc_writel(rtc, OMAP_RTC_PMIC_REG, val); val 692 drivers/rtc/rtc-omap.c u32 *val = _val; val 696 drivers/rtc/rtc-omap.c val[i] = rtc_readl(rtc, val 706 drivers/rtc/rtc-omap.c u32 *val = _val; val 712 drivers/rtc/rtc-omap.c OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]); val 118 drivers/rtc/rtc-palmas.c u8 val; val 120 drivers/rtc/rtc-palmas.c val = enabled ? PALMAS_RTC_INTERRUPTS_REG_IT_ALARM : 0; val 122 drivers/rtc/rtc-palmas.c PALMAS_RTC_INTERRUPTS_REG, val); val 123 drivers/rtc/rtc-pcf2123.c int ret, val; val 130 drivers/rtc/rtc-pcf2123.c val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT); val 133 drivers/rtc/rtc-pcf2123.c val *= 2; val 135 drivers/rtc/rtc-pcf2123.c *offset = ((long)val) * OFFSET_STEP; val 252 drivers/rtc/rtc-pcf2123.c unsigned int val = 0; val 266 drivers/rtc/rtc-pcf2123.c ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val); val 270 drivers/rtc/rtc-pcf2123.c alm->enabled = !!(val & CTRL2_AIE); val 311 drivers/rtc/rtc-pcf2123.c unsigned int val = 0; val 315 drivers/rtc/rtc-pcf2123.c regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val); val 318 drivers/rtc/rtc-pcf2123.c if (val & CTRL2_AF) { val 336 drivers/rtc/rtc-pcf2123.c unsigned int val = 0; val 350 drivers/rtc/rtc-pcf2123.c ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL1, &val); val 354 drivers/rtc/rtc-pcf2123.c dev_dbg(dev, "received data from RTC (0x%08X)\n", val); val 355 drivers/rtc/rtc-pcf2123.c if (!(val & CTRL1_STOP)) val 222 drivers/rtc/rtc-pcf2127.c void *val, size_t bytes) val 234 drivers/rtc/rtc-pcf2127.c val, bytes); val 240 drivers/rtc/rtc-pcf2127.c void *val, size_t bytes) val 252 drivers/rtc/rtc-pcf2127.c val, bytes); val 565 drivers/rtc/rtc-pcf2127.c const void *val, size_t val_size) val 580 drivers/rtc/rtc-pcf2127.c memcpy(buf + 1, val, val_size); val 593 drivers/rtc/rtc-pcf2127.c void *val, size_t val_size) val 606 drivers/rtc/rtc-pcf2127.c ret = i2c_master_recv(client, val, val_size); val 154 drivers/rtc/rtc-pcf85063.c unsigned int val; val 167 drivers/rtc/rtc-pcf85063.c ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val); val 171 drivers/rtc/rtc-pcf85063.c alrm->enabled = !!(val & PCF85063_CTRL2_AIE); val 216 drivers/rtc/rtc-pcf85063.c unsigned int val; val 219 drivers/rtc/rtc-pcf85063.c err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val); val 223 drivers/rtc/rtc-pcf85063.c if (val & PCF85063_CTRL2_AF) { val 237 drivers/rtc/rtc-pcf85063.c long val; val 245 drivers/rtc/rtc-pcf85063.c val = sign_extend32(reg & ~PCF85063_OFFSET_MODE, val 249 drivers/rtc/rtc-pcf85063.c *offset = val * PCF85063_OFFSET_STEP1; val 251 drivers/rtc/rtc-pcf85063.c *offset = val * PCF85063_OFFSET_STEP0; val 333 drivers/rtc/rtc-pcf85063.c void *val, size_t bytes) val 335 drivers/rtc/rtc-pcf85063.c return regmap_read(priv, PCF85063_REG_RAM, val); val 339 drivers/rtc/rtc-pcf85063.c void *val, size_t bytes) val 341 drivers/rtc/rtc-pcf85063.c return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val); val 307 drivers/rtc/rtc-pcf8523.c s8 val; val 314 drivers/rtc/rtc-pcf8523.c val = value << 1; val 315 drivers/rtc/rtc-pcf8523.c *offset = (value & REG_OFFSET_MODE ? 4069 : 4340) * (val >> 1); val 185 drivers/rtc/rtc-pcf85363.c unsigned int val; val 199 drivers/rtc/rtc-pcf85363.c ret = regmap_read(pcf85363->regmap, CTRL_INTA_EN, &val); val 203 drivers/rtc/rtc-pcf85363.c alrm->enabled = !!(val & INT_A1IE); val 298 drivers/rtc/rtc-pcf85363.c static int pcf85363_nvram_read(void *priv, unsigned int offset, void *val, val 304 drivers/rtc/rtc-pcf85363.c val, bytes); val 307 drivers/rtc/rtc-pcf85363.c static int pcf85363_nvram_write(void *priv, unsigned int offset, void *val, val 313 drivers/rtc/rtc-pcf85363.c val, bytes); val 316 drivers/rtc/rtc-pcf85363.c static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val, val 324 drivers/rtc/rtc-pcf85363.c (*(unsigned char *) val) = (unsigned char) tmp_val; val 329 drivers/rtc/rtc-pcf85363.c static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val, val 335 drivers/rtc/rtc-pcf85363.c tmp_val = *((unsigned char *)val); val 67 drivers/rtc/rtc-r7301.c unsigned int val; val 69 drivers/rtc/rtc-r7301.c regmap_read(priv->regmap, reg_stride * reg, &val); val 71 drivers/rtc/rtc-r7301.c return val & 0xf; val 74 drivers/rtc/rtc-r7301.c static void rtc7301_write(struct rtc7301_priv *priv, u8 val, unsigned int reg) val 78 drivers/rtc/rtc-r7301.c regmap_write(priv->regmap, reg_stride * reg, val); val 82 drivers/rtc/rtc-r7301.c u8 mask, u8 val) val 86 drivers/rtc/rtc-r7301.c regmap_update_bits(priv->regmap, reg_stride * reg, mask, val); val 94 drivers/rtc/rtc-r7301.c u8 val; val 96 drivers/rtc/rtc-r7301.c val = rtc7301_read(priv, RTC7301_CONTROL); val 97 drivers/rtc/rtc-r7301.c if (!(val & RTC7301_CONTROL_BUSY)) val 119 drivers/rtc/rtc-r7301.c u8 val = 0; val 125 drivers/rtc/rtc-r7301.c val |= RTC7301_CONTROL_BANK_SEL_0; val 127 drivers/rtc/rtc-r7301.c val |= RTC7301_CONTROL_BANK_SEL_1; val 131 drivers/rtc/rtc-r7301.c RTC7301_CONTROL_BANK_SEL_1, val); val 41 drivers/rtc/rtc-rc5t583.c u8 val; val 44 drivers/rtc/rtc-rc5t583.c val = enabled ? SET_YAL : 0; val 47 drivers/rtc/rtc-rc5t583.c val); val 76 drivers/rtc/rtc-rp5c01.c static inline void rp5c01_write(struct rp5c01_priv *priv, unsigned int val, val 79 drivers/rtc/rtc-rp5c01.c __raw_writel(val, &priv->regs[reg]); val 163 drivers/rtc/rtc-rp5c01.c static int rp5c01_nvram_read(void *_priv, unsigned int pos, void *val, val 167 drivers/rtc/rtc-rp5c01.c u8 *buf = val; val 191 drivers/rtc/rtc-rp5c01.c static int rp5c01_nvram_write(void *_priv, unsigned int pos, void *val, val 195 drivers/rtc/rtc-rp5c01.c u8 *buf = val; val 58 drivers/rtc/rtc-rtd119x.c u32 val; val 60 drivers/rtc/rtc-rtd119x.c val = readl_relaxed(data->base + RTD_RTCCR); val 61 drivers/rtc/rtc-rtd119x.c val |= RTD_RTCCR_RTCRST; val 62 drivers/rtc/rtc-rtd119x.c writel_relaxed(val, data->base + RTD_RTCCR); val 64 drivers/rtc/rtc-rtd119x.c val &= ~RTD_RTCCR_RTCRST; val 65 drivers/rtc/rtc-rtd119x.c writel(val, data->base + RTD_RTCCR); val 71 drivers/rtc/rtc-rtd119x.c u32 val; val 73 drivers/rtc/rtc-rtd119x.c val = readl_relaxed(data->base + RTD_RTCEN); val 75 drivers/rtc/rtc-rtd119x.c if ((val & RTD_RTCEN_RTCEN_MASK) == 0x5a) val 171 drivers/rtc/rtc-rtd119x.c u32 val; val 196 drivers/rtc/rtc-rtd119x.c val = readl_relaxed(data->base + RTD_RTCACR); val 197 drivers/rtc/rtc-rtd119x.c if (!(val & RTD_RTCACR_RTCPWR)) { val 443 drivers/rtc/rtc-rv3028.c static int rv3028_nvram_write(void *priv, unsigned int offset, void *val, val 446 drivers/rtc/rtc-rv3028.c return regmap_bulk_write(priv, RV3028_RAM1 + offset, val, bytes); val 449 drivers/rtc/rtc-rv3028.c static int rv3028_nvram_read(void *priv, unsigned int offset, void *val, val 452 drivers/rtc/rtc-rv3028.c return regmap_bulk_read(priv, RV3028_RAM1 + offset, val, bytes); val 455 drivers/rtc/rtc-rv3028.c static int rv3028_eeprom_write(void *priv, unsigned int offset, void *val, val 460 drivers/rtc/rtc-rv3028.c u8 *buf = val; val 520 drivers/rtc/rtc-rv3028.c static int rv3028_eeprom_read(void *priv, unsigned int offset, void *val, val 525 drivers/rtc/rtc-rv3028.c u8 *buf = val; val 175 drivers/rtc/rtc-rv3029c2.c static int rv3029_set_sr(struct device *dev, u8 val) val 180 drivers/rtc/rtc-rv3029c2.c buf[0] = val; val 456 drivers/rtc/rtc-rv8803.c static int rv8803_nvram_write(void *priv, unsigned int offset, void *val, val 461 drivers/rtc/rtc-rv8803.c ret = rv8803_write_reg(priv, RV8803_RAM, *(u8 *)val); val 469 drivers/rtc/rtc-rv8803.c void *val, size_t bytes) val 477 drivers/rtc/rtc-rv8803.c *(u8 *)val = ret; val 191 drivers/rtc/rtc-rx8581.c static int rx8571_nvram_read(void *priv, unsigned int offset, void *val, val 197 drivers/rtc/rtc-rx8581.c val, bytes); val 200 drivers/rtc/rtc-rx8581.c static int rx8571_nvram_write(void *priv, unsigned int offset, void *val, val 206 drivers/rtc/rtc-rx8581.c val, bytes); val 209 drivers/rtc/rtc-rx8581.c static int rx85x1_nvram_read(void *priv, unsigned int offset, void *val, val 217 drivers/rtc/rtc-rx8581.c (*(unsigned char *)val) = (unsigned char) tmp_val; val 222 drivers/rtc/rtc-rx8581.c static int rx85x1_nvram_write(void *priv, unsigned int offset, void *val, val 228 drivers/rtc/rtc-rx8581.c tmp_val = *((unsigned char *)val); val 644 drivers/rtc/rtc-s3c.c int val; val 649 drivers/rtc/rtc-s3c.c val = (info->rtc->max_user_freq / freq) - 1; val 650 drivers/rtc/rtc-s3c.c tmp |= val; val 658 drivers/rtc/rtc-s3c.c int val; val 663 drivers/rtc/rtc-s3c.c val = (info->rtc->max_user_freq / freq) - 1; val 665 drivers/rtc/rtc-s3c.c tmp |= S3C2443_TICNT_PART(val); val 666 drivers/rtc/rtc-s3c.c writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); val 668 drivers/rtc/rtc-s3c.c writel(S3C2416_TICNT2_PART(val), info->base + S3C2416_TICNT2); val 676 drivers/rtc/rtc-s3c.c int val; val 681 drivers/rtc/rtc-s3c.c val = (info->rtc->max_user_freq / freq) - 1; val 683 drivers/rtc/rtc-s3c.c tmp |= S3C2443_TICNT_PART(val); val 684 drivers/rtc/rtc-s3c.c writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); val 691 drivers/rtc/rtc-s3c.c int val; val 693 drivers/rtc/rtc-s3c.c val = (info->rtc->max_user_freq / freq) - 1; val 694 drivers/rtc/rtc-s3c.c writel(val, info->base + S3C2410_TICNT); val 241 drivers/rtc/rtc-s5m.c unsigned int val; val 246 drivers/rtc/rtc-s5m.c ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val); val 247 drivers/rtc/rtc-s5m.c val &= S5M_ALARM0_STATUS; val 253 drivers/rtc/rtc-s5m.c &val); val 254 drivers/rtc/rtc-s5m.c val &= S2MPS_ALARM0_STATUS; val 262 drivers/rtc/rtc-s5m.c if (val) val 453 drivers/rtc/rtc-s5m.c unsigned int val; val 464 drivers/rtc/rtc-s5m.c ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val); val 468 drivers/rtc/rtc-s5m.c alrm->enabled = !!val; val 135 drivers/rtc/rtc-sc27xx.c u32 val; val 137 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_SPG_VALUE, &val); val 141 drivers/rtc/rtc-sc27xx.c val &= ~SPRD_RTC_ALMLOCK_MASK; val 143 drivers/rtc/rtc-sc27xx.c val |= SPRD_RTC_ALM_LOCK; val 145 drivers/rtc/rtc-sc27xx.c val |= SPRD_RTC_ALM_UNLOCK | SPRD_RTC_POWEROFF_ALM_FLAG; val 147 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_SPG_UPD, val); val 153 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_RAW_STS, val, val 154 drivers/rtc/rtc-sc27xx.c (val & SPRD_RTC_SPG_UPD_EN), val 170 drivers/rtc/rtc-sc27xx.c u32 val, sec, min, hour, day; val 196 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + sec_reg, &val); val 200 drivers/rtc/rtc-sc27xx.c sec = val & SPRD_RTC_SEC_MASK; val 202 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + min_reg, &val); val 206 drivers/rtc/rtc-sc27xx.c min = val & SPRD_RTC_MIN_MASK; val 208 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + hour_reg, &val); val 212 drivers/rtc/rtc-sc27xx.c hour = val & SPRD_RTC_HOUR_MASK; val 214 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + day_reg, &val); val 218 drivers/rtc/rtc-sc27xx.c day = val & SPRD_RTC_DAY_MASK; val 227 drivers/rtc/rtc-sc27xx.c u32 sec, min, hour, day, val; val 289 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_RAW_STS, val, val 290 drivers/rtc/rtc-sc27xx.c ((val & sts_mask) == sts_mask), val 306 drivers/rtc/rtc-sc27xx.c u32 val; val 315 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_EN, &val); val 319 drivers/rtc/rtc-sc27xx.c alrm->enabled = !!(val & SPRD_RTC_AUXALM_EN); val 321 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_RAW_STS, &val); val 325 drivers/rtc/rtc-sc27xx.c alrm->pending = !!(val & SPRD_RTC_AUXALM_EN); val 415 drivers/rtc/rtc-sc27xx.c u32 val; val 434 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_EN, &val); val 438 drivers/rtc/rtc-sc27xx.c alrm->enabled = !!(val & SPRD_RTC_ALARM_EN); val 440 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_RAW_STS, &val); val 444 drivers/rtc/rtc-sc27xx.c alrm->pending = !!(val & SPRD_RTC_ALARM_EN); val 554 drivers/rtc/rtc-sc27xx.c u32 val; val 557 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_PWR_STS, &val); val 566 drivers/rtc/rtc-sc27xx.c rtc->valid = val == SPRD_RTC_POWER_RESET_VALUE ? false : true; val 572 drivers/rtc/rtc-sc27xx.c u32 val; val 575 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_SPG_VALUE, &val); val 589 drivers/rtc/rtc-sc27xx.c if (!(val & SPRD_RTC_POWEROFF_ALM_FLAG)) val 60 drivers/rtc/rtc-sirfsoc.c u32 val; val 62 drivers/rtc/rtc-sirfsoc.c regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val); val 63 drivers/rtc/rtc-sirfsoc.c return val; val 67 drivers/rtc/rtc-sirfsoc.c u32 offset, u32 val) val 69 drivers/rtc/rtc-sirfsoc.c regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val); val 90 drivers/rtc/rtc-spear.c unsigned int val; val 94 drivers/rtc/rtc-spear.c val = readl(config->ioaddr + STATUS_REG); val 95 drivers/rtc/rtc-spear.c val |= RTC_INT_MASK; val 96 drivers/rtc/rtc-spear.c writel(val, config->ioaddr + STATUS_REG); val 102 drivers/rtc/rtc-spear.c unsigned int val; val 104 drivers/rtc/rtc-spear.c val = readl(config->ioaddr + CTRL_REG); val 105 drivers/rtc/rtc-spear.c if (!(val & INT_ENABLE)) { val 107 drivers/rtc/rtc-spear.c val |= INT_ENABLE; val 108 drivers/rtc/rtc-spear.c writel(val, config->ioaddr + CTRL_REG); val 114 drivers/rtc/rtc-spear.c unsigned int val; val 116 drivers/rtc/rtc-spear.c val = readl(config->ioaddr + CTRL_REG); val 117 drivers/rtc/rtc-spear.c if (val & INT_ENABLE) { val 118 drivers/rtc/rtc-spear.c val &= ~INT_ENABLE; val 119 drivers/rtc/rtc-spear.c writel(val, config->ioaddr + CTRL_REG); val 233 drivers/rtc/rtc-stk17ta8.c static int stk17ta8_nvram_read(void *priv, unsigned int pos, void *val, val 238 drivers/rtc/rtc-stk17ta8.c u8 *buf = val; val 245 drivers/rtc/rtc-stk17ta8.c static int stk17ta8_nvram_write(void *priv, unsigned int pos, void *val, val 250 drivers/rtc/rtc-stk17ta8.c u8 *buf = val; val 159 drivers/rtc/rtc-sun6i.c u32 val = 0; val 161 drivers/rtc/rtc-sun6i.c val = readl(rtc->base + SUN6I_LOSC_CTRL); val 162 drivers/rtc/rtc-sun6i.c if (val & SUN6I_LOSC_CTRL_EXT_OSC) val 169 drivers/rtc/rtc-sun6i.c val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); val 170 drivers/rtc/rtc-sun6i.c val &= GENMASK(4, 0); val 173 drivers/rtc/rtc-sun6i.c return parent_rate / (val + 1); val 187 drivers/rtc/rtc-sun6i.c u32 val; val 193 drivers/rtc/rtc-sun6i.c val = readl(rtc->base + SUN6I_LOSC_CTRL); val 194 drivers/rtc/rtc-sun6i.c val &= ~SUN6I_LOSC_CTRL_EXT_OSC; val 195 drivers/rtc/rtc-sun6i.c val |= SUN6I_LOSC_CTRL_KEY; val 196 drivers/rtc/rtc-sun6i.c val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; val 198 drivers/rtc/rtc-sun6i.c val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; val 199 drivers/rtc/rtc-sun6i.c val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; val 201 drivers/rtc/rtc-sun6i.c writel(val, rtc->base + SUN6I_LOSC_CTRL); val 415 drivers/rtc/rtc-sun6i.c u32 val; val 418 drivers/rtc/rtc-sun6i.c val = readl(chip->base + SUN6I_ALRM_IRQ_STA); val 420 drivers/rtc/rtc-sun6i.c if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { val 421 drivers/rtc/rtc-sun6i.c val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; val 422 drivers/rtc/rtc-sun6i.c writel(val, chip->base + SUN6I_ALRM_IRQ_STA); val 149 drivers/rtc/rtc-sunxi.c u32 val; val 151 drivers/rtc/rtc-sunxi.c val = readl(chip->base + SUNXI_ALRM_IRQ_STA); val 153 drivers/rtc/rtc-sunxi.c if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) { val 154 drivers/rtc/rtc-sunxi.c val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND; val 155 drivers/rtc/rtc-sunxi.c writel(val, chip->base + SUNXI_ALRM_IRQ_STA); val 50 drivers/rtc/rtc-tps65910.c u8 val = 0; val 53 drivers/rtc/rtc-tps65910.c val = TPS65910_RTC_INTERRUPTS_IT_ALARM; val 55 drivers/rtc/rtc-tps65910.c return regmap_write(tps->regmap, TPS65910_RTC_INTERRUPTS, val); val 187 drivers/rtc/rtc-twl.c unsigned char val; val 194 drivers/rtc/rtc-twl.c val = twl_rtc->rtc_irq_bits | bit; val 195 drivers/rtc/rtc-twl.c val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M; val 196 drivers/rtc/rtc-twl.c ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG); val 198 drivers/rtc/rtc-twl.c twl_rtc->rtc_irq_bits = val; val 208 drivers/rtc/rtc-twl.c unsigned char val; val 215 drivers/rtc/rtc-twl.c val = twl_rtc->rtc_irq_bits & ~bit; val 216 drivers/rtc/rtc-twl.c ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG); val 218 drivers/rtc/rtc-twl.c twl_rtc->rtc_irq_bits = val; val 203 drivers/rtc/rtc-tx4939.c static int tx4939_nvram_read(void *priv, unsigned int pos, void *val, val 208 drivers/rtc/rtc-tx4939.c u8 *buf = val; val 219 drivers/rtc/rtc-tx4939.c static int tx4939_nvram_write(void *priv, unsigned int pos, void *val, val 224 drivers/rtc/rtc-tx4939.c u8 *buf = val; val 88 drivers/rtc/sysfs.c unsigned long val; val 91 drivers/rtc/sysfs.c err = kstrtoul(buf, 0, &val); val 95 drivers/rtc/sysfs.c if (val >= 4096 || val == 0) val 98 drivers/rtc/sysfs.c rtc->max_user_freq = (int)val; val 135 drivers/s390/block/dasd_devmap.c unsigned int val; val 152 drivers/s390/block/dasd_devmap.c if (!kstrtouint(str, 16, &val)) { val 154 drivers/s390/block/dasd_devmap.c if (val > 0xffff) val 156 drivers/s390/block/dasd_devmap.c *devno = val; val 162 drivers/s390/block/dasd_devmap.c if (kstrtouint(tok, 16, &val) || val > 0xff) val 164 drivers/s390/block/dasd_devmap.c *id0 = val; val 167 drivers/s390/block/dasd_devmap.c if (kstrtouint(tok, 16, &val) || val > 0xff) val 169 drivers/s390/block/dasd_devmap.c *id1 = val; val 172 drivers/s390/block/dasd_devmap.c if (kstrtouint(tok, 16, &val) || val > 0xffff) val 174 drivers/s390/block/dasd_devmap.c *devno = val; val 732 drivers/s390/block/dasd_devmap.c unsigned int val; val 735 drivers/s390/block/dasd_devmap.c if (kstrtouint(buf, 0, &val) || val > 1) val 738 drivers/s390/block/dasd_devmap.c rc = dasd_set_feature(to_ccwdev(dev), DASD_FEATURE_FAILFAST, val); val 778 drivers/s390/block/dasd_devmap.c unsigned int val; val 781 drivers/s390/block/dasd_devmap.c if (kstrtouint(buf, 0, &val) || val > 1) val 784 drivers/s390/block/dasd_devmap.c rc = dasd_set_feature(cdev, DASD_FEATURE_READONLY, val); val 793 drivers/s390/block/dasd_devmap.c val = val || test_bit(DASD_FLAG_DEVICE_RO, &device->flags); val 804 drivers/s390/block/dasd_devmap.c set_disk_ro(device->block->gdp, val); val 836 drivers/s390/block/dasd_devmap.c unsigned int val; val 839 drivers/s390/block/dasd_devmap.c if (kstrtouint(buf, 0, &val) || val > 1) val 842 drivers/s390/block/dasd_devmap.c rc = dasd_set_feature(to_ccwdev(dev), DASD_FEATURE_ERPLOG, val); val 872 drivers/s390/block/dasd_devmap.c unsigned int val; val 879 drivers/s390/block/dasd_devmap.c if (kstrtouint(buf, 0, &val) || val > 1) val 886 drivers/s390/block/dasd_devmap.c if (val) val 922 drivers/s390/block/dasd_devmap.c unsigned long val; val 928 drivers/s390/block/dasd_devmap.c if ((kstrtoul(buf, 10, &val) != 0) || val > 1) val 935 drivers/s390/block/dasd_devmap.c if (val) val 1204 drivers/s390/block/dasd_devmap.c unsigned int val; val 1211 drivers/s390/block/dasd_devmap.c if (kstrtouint(buf, 0, &val) || val > 1) val 1214 drivers/s390/block/dasd_devmap.c if (val) val 1248 drivers/s390/block/dasd_devmap.c unsigned long val; val 1254 drivers/s390/block/dasd_devmap.c if ((kstrtoul(buf, 10, &val) != 0) || val 1255 drivers/s390/block/dasd_devmap.c (val > DASD_EXPIRES_MAX) || val == 0) { val 1260 drivers/s390/block/dasd_devmap.c if (val) val 1261 drivers/s390/block/dasd_devmap.c device->default_expires = val; val 1288 drivers/s390/block/dasd_devmap.c unsigned long val; val 1294 drivers/s390/block/dasd_devmap.c if ((kstrtoul(buf, 10, &val) != 0) || val 1295 drivers/s390/block/dasd_devmap.c (val > DASD_RETRIES_MAX)) { val 1300 drivers/s390/block/dasd_devmap.c if (val) val 1301 drivers/s390/block/dasd_devmap.c device->default_retries = val; val 1330 drivers/s390/block/dasd_devmap.c unsigned long val; val 1336 drivers/s390/block/dasd_devmap.c if ((kstrtoul(buf, 10, &val) != 0) || val 1337 drivers/s390/block/dasd_devmap.c val > UINT_MAX / HZ) { val 1347 drivers/s390/block/dasd_devmap.c device->blk_timeout = val; val 1364 drivers/s390/block/dasd_devmap.c unsigned int val; val 1370 drivers/s390/block/dasd_devmap.c if ((kstrtouint(buf, 16, &val) != 0) || val > 0xff) val 1371 drivers/s390/block/dasd_devmap.c val = 0; val 1374 drivers/s390/block/dasd_devmap.c device->discipline->reset_path(device, (__u8) val); val 1537 drivers/s390/block/dasd_devmap.c unsigned long val; val 1543 drivers/s390/block/dasd_devmap.c if (kstrtoul(buf, 10, &val) != 0 || val > DASD_THRHLD_MAX) { val 1548 drivers/s390/block/dasd_devmap.c device->path_thrhld = val; val 1581 drivers/s390/block/dasd_devmap.c unsigned int val; val 1584 drivers/s390/block/dasd_devmap.c if (kstrtouint(buf, 0, &val) || val > 1) val 1588 drivers/s390/block/dasd_devmap.c DASD_FEATURE_PATH_AUTODISABLE, val); val 1622 drivers/s390/block/dasd_devmap.c unsigned long val; val 1628 drivers/s390/block/dasd_devmap.c if ((kstrtoul(buf, 10, &val) != 0) || val 1629 drivers/s390/block/dasd_devmap.c (val > DASD_INTERVAL_MAX) || val == 0) { val 1634 drivers/s390/block/dasd_devmap.c if (val) val 1635 drivers/s390/block/dasd_devmap.c device->path_interval = val; val 1652 drivers/s390/block/dasd_devmap.c int val = 0; \ val 1657 drivers/s390/block/dasd_devmap.c val = _func(device); \ val 1660 drivers/s390/block/dasd_devmap.c return snprintf(buf, PAGE_SIZE, "%d\n", val); \ val 364 drivers/s390/char/keyboard.c ushort *key_map, val, ov; val 384 drivers/s390/char/keyboard.c val = U(key_map[kb_index]); val 385 drivers/s390/char/keyboard.c if (KTYP(val) >= KBD_NR_TYPES) val 386 drivers/s390/char/keyboard.c val = K_HOLE; val 388 drivers/s390/char/keyboard.c val = (kb_index ? K_HOLE : K_NOSUCHMAP); val 389 drivers/s390/char/keyboard.c return put_user(val, &user_kbe->kb_value); val 125 drivers/s390/char/sclp.h static inline void sccb_set_mask(u8 *masks, size_t len, int i, sccb_mask_t val) val 128 drivers/s390/char/sclp.h memcpy(masks + i * len, &val, min(sizeof(val), len)); val 142 drivers/s390/char/sclp.h #define sccb_set_generic_mask(sccb, i, val) \ val 146 drivers/s390/char/sclp.h sccb_set_mask(__sccb->masks, __sccb->mask_length, i, val); \ val 148 drivers/s390/char/sclp.h #define sccb_set_recv_mask(sccb, val) sccb_set_generic_mask(sccb, 0, val) val 149 drivers/s390/char/sclp.h #define sccb_set_send_mask(sccb, val) sccb_set_generic_mask(sccb, 1, val) val 150 drivers/s390/char/sclp.h #define sccb_set_sclp_recv_mask(sccb, val) sccb_set_generic_mask(sccb, 2, val) val 151 drivers/s390/char/sclp.h #define sccb_set_sclp_send_mask(sccb, val) sccb_set_generic_mask(sccb, 3, val) val 33 drivers/s390/char/sclp_early_core.c __ctl_store(cr0.val, 0, 0); val 34 drivers/s390/char/sclp_early_core.c cr0_new.val = cr0.val & ~CR0_IRQ_SUBCLASS_MASK; val 37 drivers/s390/char/sclp_early_core.c __ctl_load(cr0_new.val, 0, 0); val 60 drivers/s390/char/sclp_early_core.c __ctl_load(cr0.val, 0, 0); val 77 drivers/s390/cio/blacklist.c static int pure_hex(char **cp, unsigned int *val, int min_digit, val 83 drivers/s390/cio/blacklist.c *val = 0; val 90 drivers/s390/cio/blacklist.c *val = *val * 16 + value; val 95 drivers/s390/cio/blacklist.c if ((diff < min_digit) || (diff > max_digit) || (*val > max_val)) val 105 drivers/s390/cio/blacklist.c int val, rc, ret; val 114 drivers/s390/cio/blacklist.c val = simple_strtoul(str, &str_work, 16); val 117 drivers/s390/cio/blacklist.c if (val <= __MAX_SUBCHANNEL) { val 118 drivers/s390/cio/blacklist.c *devno = val; val 295 drivers/s390/cio/chp.c int val; val 298 drivers/s390/cio/chp.c if (sscanf(buf, "%d %c", &val, &delim) != 1) val 300 drivers/s390/cio/chp.c if (val != 0 && val != 1) val 303 drivers/s390/cio/chp.c chp_cfg_schedule(cp->chpid, val); val 601 drivers/s390/cio/cmf.c u32 val; val 623 drivers/s390/cio/cmf.c val = cmb->device_connect_time; val 626 drivers/s390/cio/cmf.c val = cmb->function_pending_time; val 629 drivers/s390/cio/cmf.c val = cmb->device_disconnect_time; val 632 drivers/s390/cio/cmf.c val = cmb->control_unit_queuing_time; val 635 drivers/s390/cio/cmf.c val = cmb->device_active_only_time; val 640 drivers/s390/cio/cmf.c ret = time_to_avg_nsec(val, cmb->sample_count); val 855 drivers/s390/cio/cmf.c u32 val; val 877 drivers/s390/cio/cmf.c val = cmb->device_connect_time; val 880 drivers/s390/cio/cmf.c val = cmb->function_pending_time; val 883 drivers/s390/cio/cmf.c val = cmb->device_disconnect_time; val 886 drivers/s390/cio/cmf.c val = cmb->control_unit_queuing_time; val 889 drivers/s390/cio/cmf.c val = cmb->device_active_only_time; val 892 drivers/s390/cio/cmf.c val = cmb->device_busy_time; val 895 drivers/s390/cio/cmf.c val = cmb->initial_command_response_time; val 900 drivers/s390/cio/cmf.c ret = time_to_avg_nsec(val, cmb->sample_count); val 1090 drivers/s390/cio/cmf.c unsigned long val; val 1093 drivers/s390/cio/cmf.c ret = kstrtoul(buf, 16, &val); val 1097 drivers/s390/cio/cmf.c switch (val) { val 898 drivers/s390/cio/css.c unsigned long val; val 901 drivers/s390/cio/css.c ret = kstrtoul(buf, 16, &val); val 905 drivers/s390/cio/css.c switch (val) { val 247 drivers/s390/cio/qdio_debug.c unsigned long val; val 253 drivers/s390/cio/qdio_debug.c ret = kstrtoul_from_user(ubuf, count, 10, &val); val 257 drivers/s390/cio/qdio_debug.c switch (val) { val 214 drivers/s390/cio/qdio_main.c __state = q->slsb.val[bufnr]; val 228 drivers/s390/cio/qdio_main.c q->slsb.val[bufnr] == SLSB_P_OUTPUT_PENDING && val 233 drivers/s390/cio/qdio_main.c if (q->slsb.val[bufnr] != __state) val 258 drivers/s390/cio/qdio_main.c xchg(&q->slsb.val[bufnr], state); val 207 drivers/s390/cio/qdio_setup.c q->slib->slsba = (unsigned long)&q->slsb.val[0]; val 408 drivers/s390/cio/qdio_setup.c (unsigned long)&irq_ptr_qs[i]->slsb.val[0]; val 107 drivers/s390/scsi/zfcp_sysfs.c unsigned long val; val 109 drivers/s390/scsi/zfcp_sysfs.c if (kstrtoul(buf, 0, &val) || val != 0) val 145 drivers/s390/scsi/zfcp_sysfs.c unsigned long val; val 148 drivers/s390/scsi/zfcp_sysfs.c if (kstrtoul(buf, 0, &val) || val != 0) val 192 drivers/s390/scsi/zfcp_sysfs.c unsigned long val; val 198 drivers/s390/scsi/zfcp_sysfs.c if (kstrtoul(buf, 0, &val) || val != 0) { val 525 drivers/s390/scsi/zfcp_sysfs.c unsigned long val; val 527 drivers/s390/scsi/zfcp_sysfs.c if (kstrtoul(buf, 0, &val) || val != 0) val 1415 drivers/s390/virtio/virtio_ccw.c static int __init pure_hex(char **cp, unsigned int *val, int min_digit, val 1421 drivers/s390/virtio/virtio_ccw.c *val = 0; val 1428 drivers/s390/virtio/virtio_ccw.c *val = *val * 16 + value; val 1433 drivers/s390/virtio/virtio_ccw.c if ((diff < min_digit) || (diff > max_digit) || (*val > max_val)) val 142 drivers/sbus/char/bbc_envctrl.c s8 val = -1; val 150 drivers/sbus/char/bbc_envctrl.c val = tp->curr_amb_temp; val 154 drivers/sbus/char/bbc_envctrl.c val = tp->curr_cpu_temp; val 159 drivers/sbus/char/bbc_envctrl.c tp->index, type, val); val 54 drivers/sbus/char/bbc_i2c.c static void set_device_claimage(struct bbc_i2c_bus *bp, struct platform_device *op, int val) val 60 drivers/sbus/char/bbc_i2c.c bp->devs[i].client_claimed = val; val 132 drivers/sbus/char/bbc_i2c.c long val; val 134 drivers/sbus/char/bbc_i2c.c val = wait_event_interruptible_timeout( val 139 drivers/sbus/char/bbc_i2c.c if (val > 0) { val 150 drivers/sbus/char/bbc_i2c.c int bbc_i2c_writeb(struct bbc_i2c_client *client, unsigned char val, int off) val 170 drivers/sbus/char/bbc_i2c.c writeb(val, bp->i2c_control_regs + 0x1); val 81 drivers/sbus/char/bbc_i2c.h extern int bbc_i2c_writeb(struct bbc_i2c_client *, unsigned char val, int off); val 1135 drivers/scsi/3w-xxxx.c unsigned char *val) val 1157 drivers/scsi/3w-xxxx.c memcpy(param->data, val, param_size); val 430 drivers/scsi/53c700.h __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \ val 431 drivers/scsi/53c700.h (script)[A_##symbol##_used[i]] = bS_to_host(val); \ val 455 drivers/scsi/53c700.h __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ val 456 drivers/scsi/53c700.h val &= 0xff00ffff; \ val 457 drivers/scsi/53c700.h val |= ((value) & 0xff) << 16; \ val 458 drivers/scsi/53c700.h (script)[A_##symbol##_used[i]] = bS_to_host(val); \ val 461 drivers/scsi/53c700.h #symbol, A_##symbol##_used[i], val)); \ val 469 drivers/scsi/53c700.h __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ val 470 drivers/scsi/53c700.h val &= 0xffff0000; \ val 471 drivers/scsi/53c700.h val |= ((value) & 0xffff); \ val 472 drivers/scsi/53c700.h (script)[A_##symbol##_used[i]] = bS_to_host(val); \ val 475 drivers/scsi/53c700.h #symbol, A_##symbol##_used[i], val)); \ val 185 drivers/scsi/FlashPoint.c #define WR_HARPOON(ioport,val) outb((u8) val, (u32)ioport) val 186 drivers/scsi/FlashPoint.c #define WRW_HARPOON(ioport,val) outw((u16)val, (u32)ioport) val 286 drivers/scsi/NCR5380.h unsigned int reg, u8 bit, u8 val, val 289 drivers/scsi/NCR5380.h if ((NCR5380_read(reg) & bit) == val) val 292 drivers/scsi/NCR5380.h return NCR5380_poll_politely2(hostdata, reg, bit, val, val 293 drivers/scsi/NCR5380.h reg, bit, val, wait); val 2685 drivers/scsi/aacraid/aacraid.h void aac_printf(struct aac_dev *dev, u32 val); val 1001 drivers/scsi/aacraid/commsup.c void aac_printf(struct aac_dev *dev, u32 val) val 1006 drivers/scsi/aacraid/commsup.c int length = val & 0xffff; val 1007 drivers/scsi/aacraid/commsup.c int level = (val >> 16) & 0xffff; val 759 drivers/scsi/aacraid/src.c u_int32_t val; val 762 drivers/scsi/aacraid/src.c val = readl(((char *)(dev->base) + IBW_SWR_OFFSET)); val 763 drivers/scsi/aacraid/src.c val |= 0x01; val 764 drivers/scsi/aacraid/src.c writel(val, ((char *)(dev->base) + IBW_SWR_OFFSET)); val 1318 drivers/scsi/aacraid/src.c u_int32_t val; val 1337 drivers/scsi/aacraid/src.c val = src_readl(dev, MUnit.IDR); val 1338 drivers/scsi/aacraid/src.c val |= 0x40; val 1339 drivers/scsi/aacraid/src.c src_writel(dev, MUnit.IDR, val); val 1342 drivers/scsi/aacraid/src.c val = PMC_ALL_INTERRUPT_BITS; val 1343 drivers/scsi/aacraid/src.c src_writel(dev, MUnit.IOAR, val); val 1344 drivers/scsi/aacraid/src.c val = src_readl(dev, MUnit.OIMR); val 1347 drivers/scsi/aacraid/src.c val & (~(PMC_GLOBAL_INT_BIT2 | PMC_GLOBAL_INT_BIT0))); val 1352 drivers/scsi/aacraid/src.c val = src_readl(dev, MUnit.IDR); val 1353 drivers/scsi/aacraid/src.c val &= ~0x40; val 1354 drivers/scsi/aacraid/src.c src_writel(dev, MUnit.IDR, val); val 1360 drivers/scsi/aacraid/src.c val = src_readl(dev, MUnit.IDR); val 1361 drivers/scsi/aacraid/src.c val |= 0x20; val 1362 drivers/scsi/aacraid/src.c src_writel(dev, MUnit.IDR, val); val 1368 drivers/scsi/aacraid/src.c val = src_readl(dev, MUnit.IDR); val 1369 drivers/scsi/aacraid/src.c val |= 0x10; val 1370 drivers/scsi/aacraid/src.c src_writel(dev, MUnit.IDR, val); val 1376 drivers/scsi/aacraid/src.c val = src_readl(dev, MUnit.IDR); val 1377 drivers/scsi/aacraid/src.c val |= 0x80; val 1378 drivers/scsi/aacraid/src.c src_writel(dev, MUnit.IDR, val); val 1381 drivers/scsi/aacraid/src.c val = PMC_ALL_INTERRUPT_BITS; val 1382 drivers/scsi/aacraid/src.c src_writel(dev, MUnit.IOAR, val); val 1384 drivers/scsi/aacraid/src.c val = src_readl(dev, MUnit.OIMR); val 1386 drivers/scsi/aacraid/src.c val & (~(PMC_GLOBAL_INT_BIT2))); val 65 drivers/scsi/advansys.c #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0) val 804 drivers/scsi/advansys.c #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val) val 807 drivers/scsi/advansys.c #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val) val 808 drivers/scsi/advansys.c #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val) val 811 drivers/scsi/advansys.c #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val) val 812 drivers/scsi/advansys.c #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val) val 3658 drivers/scsi/advansys.c uchar val; val 3660 drivers/scsi/advansys.c val = AscGetChipControl(iop_base) & val 3665 drivers/scsi/advansys.c val |= CC_BANK_ONE; val 3667 drivers/scsi/advansys.c val |= CC_DIAG | CC_BANK_ONE; val 3669 drivers/scsi/advansys.c val &= ~CC_BANK_ONE; val 3671 drivers/scsi/advansys.c AscSetChipControl(iop_base, val); val 100 drivers/scsi/aha1542.c static int aha1542_outb(unsigned int base, u8 val) val 104 drivers/scsi/aha1542.c outb(val, DATA(base)); val 392 drivers/scsi/aic7xxx/aic79xx_osm.c void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val); val 394 drivers/scsi/aic7xxx/aic79xx_osm.c long port, uint16_t val); val 431 drivers/scsi/aic7xxx/aic79xx_osm.c ahd_outb(struct ahd_softc * ahd, long port, uint8_t val) val 434 drivers/scsi/aic7xxx/aic79xx_osm.c writeb(val, ahd->bshs[0].maddr + port); val 436 drivers/scsi/aic7xxx/aic79xx_osm.c outb(val, ahd->bshs[(port) >> 8].ioport + (port & 0xFF)); val 442 drivers/scsi/aic7xxx/aic79xx_osm.c ahd_outw_atomic(struct ahd_softc * ahd, long port, uint16_t val) val 445 drivers/scsi/aic7xxx/aic79xx_osm.c writew(val, ahd->bshs[0].maddr + port); val 447 drivers/scsi/aic7xxx/aic79xx_osm.c outw(val, ahd->bshs[(port) >> 8].ioport + (port & 0xFF)); val 358 drivers/scsi/aic7xxx/aic79xx_osm.h void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val); val 360 drivers/scsi/aic7xxx/aic79xx_osm.h long port, uint16_t val); val 413 drivers/scsi/aic7xxx/aic7xxx_osm.c ahc_outb(struct ahc_softc * ahc, long port, uint8_t val) val 416 drivers/scsi/aic7xxx/aic7xxx_osm.c writeb(val, ahc->bsh.maddr + port); val 418 drivers/scsi/aic7xxx/aic7xxx_osm.c outb(val, ahc->bsh.ioport + port); val 371 drivers/scsi/aic7xxx/aic7xxx_osm.h void ahc_outb(struct ahc_softc * ahc, long port, uint8_t val); val 18 drivers/scsi/aic94xx/aic94xx_reg.c unsigned long offs, u8 val) val 21 drivers/scsi/aic94xx/aic94xx_reg.c outb(val, val 24 drivers/scsi/aic94xx/aic94xx_reg.c writeb(val, asd_ha->io_handle[0].addr + offs); val 29 drivers/scsi/aic94xx/aic94xx_reg.c unsigned long offs, u16 val) val 32 drivers/scsi/aic94xx/aic94xx_reg.c outw(val, val 35 drivers/scsi/aic94xx/aic94xx_reg.c writew(val, asd_ha->io_handle[0].addr + offs); val 40 drivers/scsi/aic94xx/aic94xx_reg.c unsigned long offs, u32 val) val 43 drivers/scsi/aic94xx/aic94xx_reg.c outl(val, val 46 drivers/scsi/aic94xx/aic94xx_reg.c writel(val, asd_ha->io_handle[0].addr + offs); val 54 drivers/scsi/aic94xx/aic94xx_reg.c u8 val; val 56 drivers/scsi/aic94xx/aic94xx_reg.c val = inb((unsigned long) asd_ha->io_handle[0].addr val 59 drivers/scsi/aic94xx/aic94xx_reg.c val = readb(asd_ha->io_handle[0].addr + offs); val 61 drivers/scsi/aic94xx/aic94xx_reg.c return val; val 67 drivers/scsi/aic94xx/aic94xx_reg.c u16 val; val 69 drivers/scsi/aic94xx/aic94xx_reg.c val = inw((unsigned long)asd_ha->io_handle[0].addr val 72 drivers/scsi/aic94xx/aic94xx_reg.c val = readw(asd_ha->io_handle[0].addr + offs); val 74 drivers/scsi/aic94xx/aic94xx_reg.c return val; val 80 drivers/scsi/aic94xx/aic94xx_reg.c u32 val; val 82 drivers/scsi/aic94xx/aic94xx_reg.c val = inl((unsigned long) asd_ha->io_handle[0].addr val 85 drivers/scsi/aic94xx/aic94xx_reg.c val = readl(asd_ha->io_handle[0].addr + offs); val 87 drivers/scsi/aic94xx/aic94xx_reg.c return val; val 119 drivers/scsi/aic94xx/aic94xx_reg.c u32 reg, type val) \ val 123 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_##ord(asd_ha, (unsigned long)map_offs, val); \ val 177 drivers/scsi/aic94xx/aic94xx_reg.c static void __asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val) val 183 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swa_byte (asd_ha, reg,val); val 186 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swb_byte (asd_ha, reg, val); val 189 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swc_byte (asd_ha, reg, val); val 193 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swb_byte (asd_ha, reg, val); val 198 drivers/scsi/aic94xx/aic94xx_reg.c void asd_write_reg_##ord (struct asd_ha_struct *asd_ha, u32 reg, type val)\ val 206 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swa_##ord (asd_ha, reg,val); \ val 209 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swb_##ord (asd_ha, reg, val); \ val 212 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swc_##ord (asd_ha, reg, val); \ val 216 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swb_##ord (asd_ha, reg, val); \ val 228 drivers/scsi/aic94xx/aic94xx_reg.c u8 val; val 232 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swa_byte (asd_ha, reg); val 235 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swb_byte (asd_ha, reg); val 238 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swc_byte (asd_ha, reg); val 242 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swb_byte (asd_ha, reg); val 244 drivers/scsi/aic94xx/aic94xx_reg.c return val; val 251 drivers/scsi/aic94xx/aic94xx_reg.c type val; \ val 257 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swa_##ord (asd_ha, reg); \ val 260 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swb_##ord (asd_ha, reg); \ val 263 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swc_##ord (asd_ha, reg); \ val 267 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swb_##ord (asd_ha, reg); \ val 270 drivers/scsi/aic94xx/aic94xx_reg.c return val; \ val 50 drivers/scsi/aic94xx/aic94xx_reg.h void asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val); val 51 drivers/scsi/aic94xx/aic94xx_reg.h void asd_write_reg_word(struct asd_ha_struct *asd_ha, u32 reg, u16 val); val 52 drivers/scsi/aic94xx/aic94xx_reg.h void asd_write_reg_dword(struct asd_ha_struct *asd_ha, u32 reg, u32 val); val 64 drivers/scsi/aic94xx/aic94xx_reg.h type val = read##S (io_handle->addr + (unsigned long) offs); \ val 66 drivers/scsi/aic94xx/aic94xx_reg.h return val; \ val 75 drivers/scsi/aic94xx/aic94xx_reg.h u32 offs, type val) \ val 78 drivers/scsi/aic94xx/aic94xx_reg.h write##S (val, io_handle->addr + (unsigned long) offs); \ val 115 drivers/scsi/aic94xx/aic94xx_reg.h u16 offs, type val) \ val 119 drivers/scsi/aic94xx/aic94xx_reg.h asd_write_reg_##ord (asd_ha, CTXACCESS, val); \ val 127 drivers/scsi/aic94xx/aic94xx_reg.h u16 offs, u8 val) val 132 drivers/scsi/aic94xx/aic94xx_reg.h rval = (val << 8) | (rval & 0xFF); val 134 drivers/scsi/aic94xx/aic94xx_reg.h rval = (rval & 0xFF00) | val; val 168 drivers/scsi/aic94xx/aic94xx_reg.h u16 offs, type val) \ val 172 drivers/scsi/aic94xx/aic94xx_reg.h asd_write_reg_##ord (asd_ha, CTXACCESS, val); \ val 180 drivers/scsi/aic94xx/aic94xx_reg.h u16 offs, u8 val) val 185 drivers/scsi/aic94xx/aic94xx_reg.h rval = (val << 8) | (rval & 0xFF); val 187 drivers/scsi/aic94xx/aic94xx_reg.h rval = (rval & 0xFF00) | val; val 1777 drivers/scsi/aic94xx/aic94xx_reg_def.h #define PCIC_MBAR0_SIZE(val) \ val 1778 drivers/scsi/aic94xx/aic94xx_reg_def.h (((val) & PCIC_MBAR0_SIZE_MASK) >> PCIC_MBAR0_SIZE_SHIFT) val 182 drivers/scsi/aic94xx/aic94xx_seq.c u32 val = asd_read_reg_dword(asd_ha, addr); val 184 drivers/scsi/aic94xx/aic94xx_seq.c if (le32_to_cpu(*prog) != val) { val 188 drivers/scsi/aic94xx/aic94xx_seq.c i, val, le32_to_cpu(*prog)); val 224 drivers/scsi/aic94xx/aic94xx_seq.c u32 val = asd_read_reg_dword(asd_ha, LmSEQRAM(lseq)+i); val 226 drivers/scsi/aic94xx/aic94xx_seq.c if (le32_to_cpu(*prog) != val) { val 447 drivers/scsi/aic94xx/aic94xx_seq.c u8 val = hweight8(con); val 448 drivers/scsi/aic94xx/aic94xx_seq.c asd_write_reg_byte(asd_ha, CSEQ_MAX_CSEQ_MODE, (val<<4)|val); val 103 drivers/scsi/am53c974.c static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg) val 105 drivers/scsi/am53c974.c iowrite8(val, esp->regs + (reg * 4UL)); val 113 drivers/scsi/am53c974.c static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg) val 115 drivers/scsi/am53c974.c return iowrite32(val, esp->regs + (reg * 4UL)); val 215 drivers/scsi/am53c974.c u32 val = 0; val 224 drivers/scsi/am53c974.c val |= ESP_DMA_CMD_DIR; val 225 drivers/scsi/am53c974.c pci_esp_write8(esp, ESP_DMA_CMD_IDLE | val, ESP_DMA_CMD); val 240 drivers/scsi/am53c974.c pci_esp_write8(esp, ESP_DMA_CMD_START | val, ESP_DMA_CMD); val 209 drivers/scsi/arm/acornscsi.c #define sbic_arm_writenext(host, val) writeb((val), (host)->base + SBIC_REGVAL) val 187 drivers/scsi/arm/cumana_1.c u8 val; val 191 drivers/scsi/arm/cumana_1.c val = readb(base + 0x2100 + (reg << 2)); val 196 drivers/scsi/arm/cumana_1.c return val; val 147 drivers/scsi/arm/fas216.c static inline void fas216_writeb(FAS216_Info *info, unsigned int reg, unsigned int val) val 150 drivers/scsi/arm/fas216.c writeb(val, info->scsi.io_base + off); val 83 drivers/scsi/atari_scsi.c #define SCSI_DMA_WRITE_P(elt,val) \ val 85 drivers/scsi/atari_scsi.c unsigned long v = val; \ val 47 drivers/scsi/atp870u.c static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val) val 49 drivers/scsi/atp870u.c outb(val, atp->baseport + reg); val 52 drivers/scsi/atp870u.c static inline void atp_writew_base(struct atp_unit *atp, u8 reg, u16 val) val 54 drivers/scsi/atp870u.c outw(val, atp->baseport + reg); val 57 drivers/scsi/atp870u.c static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val) val 59 drivers/scsi/atp870u.c outb(val, atp->ioport[channel] + reg); val 62 drivers/scsi/atp870u.c static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val) val 64 drivers/scsi/atp870u.c outw(val, atp->ioport[channel] + reg); val 67 drivers/scsi/atp870u.c static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val) val 69 drivers/scsi/atp870u.c outb(val, atp->pciport[channel] + reg); val 72 drivers/scsi/atp870u.c static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val) val 74 drivers/scsi/atp870u.c outl(val, atp->pciport[channel] + reg); val 933 drivers/scsi/atp870u.c static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val) val 938 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, *val); val 945 drivers/scsi/atp870u.c *val |= 0x4000; /* assert DB6 */ val 946 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, *val); val 947 drivers/scsi/atp870u.c *val &= 0xdfff; /* assert DB5 */ val 948 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, *val); val 953 drivers/scsi/atp870u.c *val |= 0x8000; /* no DB4-0, assert DB7 */ val 954 drivers/scsi/atp870u.c *val &= 0xe0ff; val 955 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, *val); val 956 drivers/scsi/atp870u.c *val &= 0xbfff; /* release DB6 */ val 957 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, *val); val 971 drivers/scsi/atp870u.c unsigned short int m, assignid_map, val; val 1049 drivers/scsi/atp870u.c val = 0x0080; /* bsy */ val 1050 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, val); val 1051 drivers/scsi/atp870u.c val |= 0x0040; /* sel */ val 1052 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, val); val 1053 drivers/scsi/atp870u.c val |= 0x0004; /* msg */ val 1054 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, val); val 1056 drivers/scsi/atp870u.c val &= 0x007f; /* no bsy */ val 1057 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, val); val 1059 drivers/scsi/atp870u.c val &= 0x00fb; /* after 1ms no msg */ val 1060 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, val); val 1072 drivers/scsi/atp870u.c val |= 0x8003; /* io,cd,db7 */ val 1073 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, val); val 1075 drivers/scsi/atp870u.c val &= 0x00bf; /* no sel */ val 1076 drivers/scsi/atp870u.c atp_writew_io(dev, 0, 0x1c, val); val 1101 drivers/scsi/atp870u.c val &= 0x00ff; /* synchronization */ val 1102 drivers/scsi/atp870u.c val |= 0x3f00; val 1103 drivers/scsi/atp870u.c fun_scam(dev, &val); val 1105 drivers/scsi/atp870u.c val &= 0x00ff; /* isolation */ val 1106 drivers/scsi/atp870u.c val |= 0x2000; val 1107 drivers/scsi/atp870u.c fun_scam(dev, &val); val 1116 drivers/scsi/atp870u.c val &= 0x00ff; /* get ID_STRING */ val 1117 drivers/scsi/atp870u.c val |= 0x2000; val 1118 drivers/scsi/atp870u.c k = fun_scam(dev, &val); val 1176 drivers/scsi/atp870u.c val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */ val 1178 drivers/scsi/atp870u.c val |= m; val 1179 drivers/scsi/atp870u.c fun_scam(dev, &val); val 1180 drivers/scsi/atp870u.c val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */ val 1182 drivers/scsi/atp870u.c val |= m; val 1183 drivers/scsi/atp870u.c fun_scam(dev, &val); val 40 drivers/scsi/be2iscsi/be.h static inline u32 MODULO(u16 val, u16 limit) val 43 drivers/scsi/be2iscsi/be.h return val & (limit - 1); val 172 drivers/scsi/be2iscsi/be.h #define AMAP_SET_BITS(_struct, field, ptr, val) \ val 177 drivers/scsi/be2iscsi/be.h val) val 564 drivers/scsi/be2iscsi/be_cmds.c u32 val = 0; val 567 drivers/scsi/be2iscsi/be_cmds.c val |= mccq->id & DB_MCCQ_RING_ID_MASK; val 568 drivers/scsi/be2iscsi/be_cmds.c val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; val 571 drivers/scsi/be2iscsi/be_cmds.c iowrite32(val, phba->db_va + DB_MCCQ_OFFSET); val 638 drivers/scsi/be2iscsi/be_cmds.c u32 val = 0; val 647 drivers/scsi/be2iscsi/be_cmds.c val &= ~MPU_MAILBOX_DB_RDY_MASK; val 648 drivers/scsi/be2iscsi/be_cmds.c val |= MPU_MAILBOX_DB_HI_MASK; val 649 drivers/scsi/be2iscsi/be_cmds.c val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; val 650 drivers/scsi/be2iscsi/be_cmds.c iowrite32(val, db); val 656 drivers/scsi/be2iscsi/be_cmds.c val = 0; val 657 drivers/scsi/be2iscsi/be_cmds.c val &= ~MPU_MAILBOX_DB_RDY_MASK; val 658 drivers/scsi/be2iscsi/be_cmds.c val &= ~MPU_MAILBOX_DB_HI_MASK; val 659 drivers/scsi/be2iscsi/be_cmds.c val |= (u32) (mbox_mem->dma >> 4) << 2; val 660 drivers/scsi/be2iscsi/be_cmds.c iowrite32(val, db); val 82 drivers/scsi/be2iscsi/be_main.c beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\ val 84 drivers/scsi/be2iscsi/be_main.c if (val >= _minval && val <= _maxval) {\ val 88 drivers/scsi/be2iscsi/be_main.c phba->attr_##_name, val); \ val 89 drivers/scsi/be2iscsi/be_main.c phba->attr_##_name = val;\ val 95 drivers/scsi/be2iscsi/be_main.c "range allowed is ["#_minval" - "#_maxval"]\n", val);\ val 120 drivers/scsi/be2iscsi/be_main.c beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \ val 122 drivers/scsi/be2iscsi/be_main.c if (val >= _minval && val <= _maxval) {\ val 123 drivers/scsi/be2iscsi/be_main.c phba->attr_##_name = val;\ val 129 drivers/scsi/be2iscsi/be_main.c "range allowed is ["#_minval" - "#_maxval"]\n", val);\ val 639 drivers/scsi/be2iscsi/be_main.c u32 val = 0; val 642 drivers/scsi/be2iscsi/be_main.c val |= 1 << DB_EQ_REARM_SHIFT; val 644 drivers/scsi/be2iscsi/be_main.c val |= 1 << DB_EQ_CLR_SHIFT; val 646 drivers/scsi/be2iscsi/be_main.c val |= 1 << DB_EQ_EVNT_SHIFT; val 648 drivers/scsi/be2iscsi/be_main.c val |= num_processed << DB_EQ_NUM_POPPED_SHIFT; val 650 drivers/scsi/be2iscsi/be_main.c val |= (id & DB_EQ_RING_ID_LOW_MASK); val 653 drivers/scsi/be2iscsi/be_main.c val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) & val 657 drivers/scsi/be2iscsi/be_main.c iowrite32(val, phba->db_va + DB_EQ_OFFSET); val 874 drivers/scsi/be2iscsi/be_main.c u32 val = 0; val 877 drivers/scsi/be2iscsi/be_main.c val |= 1 << DB_CQ_REARM_SHIFT; val 879 drivers/scsi/be2iscsi/be_main.c val |= num_processed << DB_CQ_NUM_POPPED_SHIFT; val 882 drivers/scsi/be2iscsi/be_main.c val |= (id & DB_CQ_RING_ID_LOW_MASK); val 885 drivers/scsi/be2iscsi/be_main.c val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) & val 889 drivers/scsi/be2iscsi/be_main.c iowrite32(val, phba->db_va + DB_CQ_OFFSET); val 444 drivers/scsi/bfa/bfa_fcpim.c u32 val, idx; val 446 drivers/scsi/bfa/bfa_fcpim.c val = (u32)(jiffies - ioim->start_time); val 451 drivers/scsi/bfa/bfa_fcpim.c io_lat->min[idx] = (io_lat->min[idx] < val) ? io_lat->min[idx] : val; val 452 drivers/scsi/bfa/bfa_fcpim.c io_lat->max[idx] = (io_lat->max[idx] > val) ? io_lat->max[idx] : val; val 453 drivers/scsi/bfa/bfa_fcpim.c io_lat->avg[idx] += val; val 315 drivers/scsi/bfa/bfad_debugfs.c int addr, val, rc; val 324 drivers/scsi/bfa/bfad_debugfs.c rc = sscanf(kern_buf, "%x:%x", &addr, &val); val 347 drivers/scsi/bfa/bfad_debugfs.c writel(val, reg_addr); val 157 drivers/scsi/bnx2fc/bnx2fc.h u32 val; \ val 159 drivers/scsi/bnx2fc/bnx2fc.h val = fw_stats->stat.cnt; \ val 160 drivers/scsi/bnx2fc/bnx2fc.h if (hba->prev_stats.stat.cnt <= val) \ val 161 drivers/scsi/bnx2fc/bnx2fc.h val -= hba->prev_stats.stat.cnt; \ val 163 drivers/scsi/bnx2fc/bnx2fc.h val += (0xfffffff - hba->prev_stats.stat.cnt); \ val 164 drivers/scsi/bnx2fc/bnx2fc.h hba->bfw_stats.cnt += val; \ val 2935 drivers/scsi/bnx2fc/bnx2fc_fcoe.c int rval, val; val 2937 drivers/scsi/bnx2fc/bnx2fc_fcoe.c rval = kstrtouint(buf, 10, &val); val 2940 drivers/scsi/bnx2fc/bnx2fc_fcoe.c if (val > 255) val 2943 drivers/scsi/bnx2fc/bnx2fc_fcoe.c interface->tm_timeout = (u8)val; val 130 drivers/scsi/bnx2i/bnx2i.h #define REG_WR(__hba, offset, val) \ val 131 drivers/scsi/bnx2i/bnx2i.h writel(val, __hba->regview + offset) val 156 drivers/scsi/bnx2i/bnx2i.h u64 val, *out; \ val 158 drivers/scsi/bnx2i/bnx2i.h val = __hba->bnx2i_stats.field; \ val 160 drivers/scsi/bnx2i/bnx2i.h *out = cpu_to_le64(val); \ val 162 drivers/scsi/bnx2i/bnx2i.h *out = cpu_to_le64(val); \ val 704 drivers/scsi/bnx2i/bnx2i_hwi.c static int bnx2i_power_of2(u32 val) val 707 drivers/scsi/bnx2i/bnx2i_hwi.c if (val & (val - 1)) val 709 drivers/scsi/bnx2i/bnx2i_hwi.c val--; val 710 drivers/scsi/bnx2i/bnx2i_hwi.c while (val) { val 711 drivers/scsi/bnx2i/bnx2i_hwi.c val = val >> 1; val 62 drivers/scsi/bnx2i/bnx2i_sysfs.c u32 val; val 73 drivers/scsi/bnx2i/bnx2i_sysfs.c if (sscanf(buf, " 0x%x ", &val) > 0) { val 74 drivers/scsi/bnx2i/bnx2i_sysfs.c if ((val >= BNX2I_SQ_WQES_MIN) && (val <= max_sq_size) && val 75 drivers/scsi/bnx2i/bnx2i_sysfs.c (is_power_of_2(val))) val 76 drivers/scsi/bnx2i/bnx2i_sysfs.c hba->max_sqes = val; val 115 drivers/scsi/bnx2i/bnx2i_sysfs.c u32 val; val 121 drivers/scsi/bnx2i/bnx2i_sysfs.c if (sscanf(buf, " 0x%x ", &val) > 0) { val 122 drivers/scsi/bnx2i/bnx2i_sysfs.c if ((val >= BNX2I_CCELLS_MIN) && val 123 drivers/scsi/bnx2i/bnx2i_sysfs.c (val <= BNX2I_CCELLS_MAX)) { val 124 drivers/scsi/bnx2i/bnx2i_sysfs.c hba->num_ccell = val; val 47 drivers/scsi/csiostor/csio_defs.h #define CSIO_INC_STATS(elem, val) ((elem)->stats.val++) val 48 drivers/scsi/csiostor/csio_defs.h #define CSIO_DEC_STATS(elem, val) ((elem)->stats.val--) val 59 drivers/scsi/csiostor/csio_defs.h static inline void writeq(u64 val, void __iomem *addr) val 61 drivers/scsi/csiostor/csio_defs.h writel(val, addr); val 62 drivers/scsi/csiostor/csio_defs.h writel(val >> 32, addr + 4); val 136 drivers/scsi/csiostor/csio_hw.c uint32_t val; val 138 drivers/scsi/csiostor/csio_hw.c val = csio_rd_reg32(hw, reg); val 140 drivers/scsi/csiostor/csio_hw.c if (!!(val & mask) == polarity) { val 142 drivers/scsi/csiostor/csio_hw.c *valp = val; val 164 drivers/scsi/csiostor/csio_hw.c unsigned int mask, unsigned int val) val 167 drivers/scsi/csiostor/csio_hw.c val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask; val 168 drivers/scsi/csiostor/csio_hw.c csio_wr_reg32(hw, val, TP_PIO_DATA_A); val 175 drivers/scsi/csiostor/csio_hw.c uint32_t val = csio_rd_reg32(hw, reg) & ~mask; val 177 drivers/scsi/csiostor/csio_hw.c csio_wr_reg32(hw, val | value, reg); val 214 drivers/scsi/csiostor/csio_hw.c uint16_t val = 0; val 225 drivers/scsi/csiostor/csio_hw.c pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val); val 226 drivers/scsi/csiostor/csio_hw.c } while (!(val & PCI_VPD_ADDR_F) && --attempts); val 228 drivers/scsi/csiostor/csio_hw.c if (!(val & PCI_VPD_ADDR_F)) { val 425 drivers/scsi/csiostor/csio_hw.c int32_t lock, uint32_t val) val 432 drivers/scsi/csiostor/csio_hw.c csio_wr_reg32(hw, val, SF_DATA_A); val 532 drivers/scsi/csiostor/csio_hw.c uint32_t i, c, left, val, offset = addr & 0xff; val 537 drivers/scsi/csiostor/csio_hw.c val = swab32(addr) | SF_PROG_PAGE; val 543 drivers/scsi/csiostor/csio_hw.c ret = csio_hw_sf1_write(hw, 4, 1, 1, val); val 549 drivers/scsi/csiostor/csio_hw.c for (val = 0, i = 0; i < c; ++i) val 550 drivers/scsi/csiostor/csio_hw.c val = (val << 8) + *data++; val 552 drivers/scsi/csiostor/csio_hw.c ret = csio_hw_sf1_write(hw, c, c != left, 1, val); val 1795 drivers/scsi/csiostor/csio_hw.c u32 param, val; val 1799 drivers/scsi/csiostor/csio_hw.c val = 1; val 1802 drivers/scsi/csiostor/csio_hw.c hw->pfn, 0, 1, ¶m, &val, true, val 241 drivers/scsi/csiostor/csio_lnode.c csio_append_attrib(uint8_t **ptr, uint16_t type, void *val, size_t val_len) val 255 drivers/scsi/csiostor/csio_lnode.c memcpy(ae->value, val, val_len); val 296 drivers/scsi/csiostor/csio_lnode.c __be32 val; val 346 drivers/scsi/csiostor/csio_lnode.c val = htonl(FC_PORTSPEED_1GBIT | FC_PORTSPEED_10GBIT); val 348 drivers/scsi/csiostor/csio_lnode.c &val, val 353 drivers/scsi/csiostor/csio_lnode.c val = htonl(FC_PORTSPEED_1GBIT); val 355 drivers/scsi/csiostor/csio_lnode.c val = htonl(FC_PORTSPEED_10GBIT); val 357 drivers/scsi/csiostor/csio_lnode.c val = htonl(FC_PORTSPEED_25GBIT); val 359 drivers/scsi/csiostor/csio_lnode.c val = htonl(FC_PORTSPEED_40GBIT); val 361 drivers/scsi/csiostor/csio_lnode.c val = htonl(FC_PORTSPEED_50GBIT); val 363 drivers/scsi/csiostor/csio_lnode.c val = htonl(FC_PORTSPEED_100GBIT); val 365 drivers/scsi/csiostor/csio_lnode.c val = htonl(CSIO_HBA_PORTSPEED_UNKNOWN); val 367 drivers/scsi/csiostor/csio_lnode.c &val, FC_FDMI_PORT_ATTR_CURRENTPORTSPEED_LEN); val 173 drivers/scsi/csiostor/csio_mb.c cmdp->val = htonl(reset); val 195 drivers/scsi/csiostor/csio_mb.c const u32 *params, u32 *val, bool wr, val 216 drivers/scsi/csiostor/csio_mb.c temp_val = *val++; val 242 drivers/scsi/csiostor/csio_mb.c u32 *val) val 246 drivers/scsi/csiostor/csio_mb.c __be32 *p = &rsp->param[0].val; val 252 drivers/scsi/csiostor/csio_mb.c *val++ = ntohl(*p); val 1150 drivers/scsi/cxgbi/cxgb3i/cxgb3i.c u64 val = pg_idx < DDP_PGIDX_MAX ? pg_idx : 0; val 1165 drivers/scsi/cxgbi/cxgb3i/cxgb3i.c req->val = cpu_to_be64(val << 28); val 1186 drivers/scsi/cxgbi/cxgb3i/cxgb3i.c u64 val = (hcrc ? 1 : 0) | (dcrc ? 2 : 0); val 1201 drivers/scsi/cxgbi/cxgb3i/cxgb3i.c req->val = cpu_to_be64(val << 24); val 626 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[0].val = htonl(csk->cdev->pfvf); val 628 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[1].val = htonl(csk->tx_chan); val 630 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[2].val = htonl(csk->tx_chan); val 632 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[3].val = htonl(csk->rss_qid); val 634 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[4].val = htonl(csk->snd_nxt); val 636 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[5].val = htonl(csk->rcv_nxt); val 638 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[6].val = htonl(csk->snd_win); val 640 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[7].val = htonl(csk->advmss); val 642 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[8].val = 0; val 644 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[8].val = 16384; val 650 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[9].val = cpu_to_be32(0); val 652 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c flowc->mnemval[9].val = cpu_to_be32((vlan & VLAN_PRIO_MASK) >> val 675 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c unsigned int wr_ulp_mode = 0, val; val 698 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c val = skb_peek(&csk->write_queue) ? 0 : 1; val 700 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c FW_OFLD_TX_DATA_WR_SHOVE_V(val)); val 2016 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c req->val = cpu_to_be64(pg_idx << 8); val 2051 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c req->val = cpu_to_be64(((hcrc ? ULP_CRC_HEADER : 0) | val 2256 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c cxgb4_dcb_change_notify(struct notifier_block *self, unsigned long val, val 246 drivers/scsi/cxlflash/main.c u64 val = 0x1; val 253 drivers/scsi/cxlflash/main.c writeq_be(val, reset_reg); val 255 drivers/scsi/cxlflash/main.c val = readq_be(reset_reg); val 256 drivers/scsi/cxlflash/main.c if ((val & 0x1) == 0x0) { val 271 drivers/scsi/cxlflash/main.c __func__, rc, val, nretry); val 268 drivers/scsi/cxlflash/superpipe.c u64 val; val 273 drivers/scsi/cxlflash/superpipe.c val = (SISL_CTX_CAP_READ_CMD | SISL_CTX_CAP_WRITE_CMD); val 274 drivers/scsi/cxlflash/superpipe.c writeq_be(val, &ctrl_map->ctx_cap); val 275 drivers/scsi/cxlflash/superpipe.c val = readq_be(&ctrl_map->ctx_cap); val 276 drivers/scsi/cxlflash/superpipe.c if (val != (SISL_CTX_CAP_READ_CMD | SISL_CTX_CAP_WRITE_CMD)) { val 278 drivers/scsi/cxlflash/superpipe.c __func__, val); val 286 drivers/scsi/cxlflash/superpipe.c val = cfg->ops->get_irq_objhndl(ctxi->ctx, i); val 287 drivers/scsi/cxlflash/superpipe.c writeq_be(val, &ctrl_map->lisn_ea[i]); val 291 drivers/scsi/cxlflash/superpipe.c val = hwq->ctx_hndl; val 292 drivers/scsi/cxlflash/superpipe.c writeq_be(SISL_LISN_PASID(val, val), &ctrl_map->lisn_pasid[0]); val 293 drivers/scsi/cxlflash/superpipe.c writeq_be(SISL_LISN_PASID(0UL, val), &ctrl_map->lisn_pasid[1]); val 298 drivers/scsi/cxlflash/superpipe.c val = SISL_RHT_CNT_ID((u64)MAX_RHT_PER_CONTEXT, (u64)(hwq->ctx_hndl)); val 299 drivers/scsi/cxlflash/superpipe.c writeq_be(val, &ctrl_map->rht_cnt_id); val 261 drivers/scsi/dpt/osd_util.h uLONG netSwap4(uLONG val); val 130 drivers/scsi/esp_scsi.c void scsi_esp_cmd(struct esp *esp, u8 val) val 137 drivers/scsi/esp_scsi.c p->val = val; val 142 drivers/scsi/esp_scsi.c esp_log_command("cmd[%02x]\n", val); val 143 drivers/scsi/esp_scsi.c esp_write8(val, ESP_CMD); val 165 drivers/scsi/esp_scsi.c static void esp_event(struct esp *esp, u8 val) val 172 drivers/scsi/esp_scsi.c p->val = val; val 177 drivers/scsi/esp_scsi.c esp->event = val; val 194 drivers/scsi/esp_scsi.c p->val, p->sreg, p->seqreg, val 235 drivers/scsi/esp_scsi.c static void esp_set_all_config3(struct esp *esp, u8 val) val 240 drivers/scsi/esp_scsi.c esp->target[i].esp_config3 = val; val 495 drivers/scsi/esp_scsi.c u8 val = esp->target[tgt].esp_config3; val 497 drivers/scsi/esp_scsi.c if (val != esp->prev_cfg3) { val 498 drivers/scsi/esp_scsi.c esp->prev_cfg3 = val; val 499 drivers/scsi/esp_scsi.c esp_write8(val, ESP_CFG3); val 659 drivers/scsi/esp_scsi.c u8 *p, val; val 688 drivers/scsi/esp_scsi.c val = tgt; val 690 drivers/scsi/esp_scsi.c val |= ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT; val 691 drivers/scsi/esp_scsi.c esp_write8(val, ESP_BUSID); val 696 drivers/scsi/esp_scsi.c val = (p - esp->command_block); val 698 drivers/scsi/esp_scsi.c esp_send_dma_cmd(esp, val, 16, ESP_CMD_SELA); val 740 drivers/scsi/esp_scsi.c u32 val, start_cmd; val 855 drivers/scsi/esp_scsi.c val = tgt; val 857 drivers/scsi/esp_scsi.c val |= ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT; val 858 drivers/scsi/esp_scsi.c esp_write8(val, ESP_BUSID); val 863 drivers/scsi/esp_scsi.c val = (p - esp->command_block); val 872 drivers/scsi/esp_scsi.c esp_send_dma_cmd(esp, val, 16, start_cmd); val 1976 drivers/scsi/esp_scsi.c u8 val; val 1979 drivers/scsi/esp_scsi.c val = esp->fifo[0]; val 1981 drivers/scsi/esp_scsi.c val = esp_read8(ESP_FDATA); val 1982 drivers/scsi/esp_scsi.c esp->msg_in[esp->msg_in_len++] = val; val 1984 drivers/scsi/esp_scsi.c esp_log_msgin("Got msgin byte %x\n", val); val 2213 drivers/scsi/esp_scsi.c u8 val; val 2220 drivers/scsi/esp_scsi.c val = esp_read8(ESP_CFG2); val 2221 drivers/scsi/esp_scsi.c val &= ~ESP_CONFIG2_MAGIC; val 2224 drivers/scsi/esp_scsi.c if (val != (ESP_CONFIG2_SCSI2ENAB | ESP_CONFIG2_REGPARITY)) { val 2241 drivers/scsi/esp_scsi.c val = esp_read8(ESP_CFG3); val 2242 drivers/scsi/esp_scsi.c if (val != 5) { val 2288 drivers/scsi/esp_scsi.c u8 val; val 2297 drivers/scsi/esp_scsi.c val = esp_read8(ESP_CFG1); val 2298 drivers/scsi/esp_scsi.c val |= ESP_CONFIG1_SRRDISAB; val 2299 drivers/scsi/esp_scsi.c esp_write8(val, ESP_CFG1); val 344 drivers/scsi/esp_scsi.h u8 val; val 361 drivers/scsi/esp_scsi.h void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg); val 99 drivers/scsi/fcoe/fcoe_sysfs.c static int fcoe_str_to_dev_loss(const char *buf, unsigned long *val) val 103 drivers/scsi/fcoe/fcoe_sysfs.c ret = kstrtoul(buf, 0, val); val 109 drivers/scsi/fcoe/fcoe_sysfs.c if (*val > UINT_MAX) val 116 drivers/scsi/fcoe/fcoe_sysfs.c unsigned long val) val 125 drivers/scsi/fcoe/fcoe_sysfs.c if (val > UINT_MAX) val 128 drivers/scsi/fcoe/fcoe_sysfs.c fcoe_fcf_dev_loss_tmo(fcf) = val; val 498 drivers/scsi/fcoe/fcoe_sysfs.c unsigned long val; val 501 drivers/scsi/fcoe/fcoe_sysfs.c rc = fcoe_str_to_dev_loss(buf, &val); val 505 drivers/scsi/fcoe/fcoe_sysfs.c fcoe_ctlr_fcf_dev_loss_tmo(ctlr) = val; val 508 drivers/scsi/fcoe/fcoe_sysfs.c fcoe_fcf_set_dev_loss_tmo(fcf, val); val 541 drivers/scsi/fcoe/fcoe_sysfs.c unsigned long val; val 544 drivers/scsi/fcoe/fcoe_sysfs.c rc = fcoe_str_to_dev_loss(buf, &val); val 548 drivers/scsi/fcoe/fcoe_sysfs.c rc = fcoe_fcf_set_dev_loss_tmo(fcf, val); val 156 drivers/scsi/fnic/fnic_debugfs.c unsigned long val; val 169 drivers/scsi/fnic/fnic_debugfs.c ret = kstrtoul(buf, 10, &val); val 174 drivers/scsi/fnic/fnic_debugfs.c fnic_tracing_enabled = val; val 176 drivers/scsi/fnic/fnic_debugfs.c fnic_fc_tracing_enabled = val; val 178 drivers/scsi/fnic/fnic_debugfs.c fnic_fc_trace_cleared = val; val 519 drivers/scsi/fnic/fnic_debugfs.c unsigned long val; val 530 drivers/scsi/fnic/fnic_debugfs.c ret = kstrtoul(buf, 10, &val); val 534 drivers/scsi/fnic/fnic_debugfs.c fnic->reset_stats = val; val 114 drivers/scsi/fnic/fnic_trace.c struct timespec64 val; val 132 drivers/scsi/fnic/fnic_trace.c jiffies_to_timespec64(tbp->timestamp.low, &val); val 134 drivers/scsi/fnic/fnic_trace.c sprint_symbol(str, tbp->fnaddr.val); val 135 drivers/scsi/fnic/fnic_trace.c jiffies_to_timespec64(tbp->timestamp.val, &val); val 144 drivers/scsi/fnic/fnic_trace.c "%16llx %16llx %16llx\n", (u64)val.tv_sec, val 145 drivers/scsi/fnic/fnic_trace.c val.tv_nsec, str, tbp->host_no, tbp->tag, val 174 drivers/scsi/fnic/fnic_trace.c jiffies_to_timespec64(tbp->timestamp.low, &val); val 176 drivers/scsi/fnic/fnic_trace.c sprint_symbol(str, tbp->fnaddr.val); val 177 drivers/scsi/fnic/fnic_trace.c jiffies_to_timespec64(tbp->timestamp.val, &val); val 186 drivers/scsi/fnic/fnic_trace.c "%16llx %16llx %16llx\n", (u64)val.tv_sec, val 187 drivers/scsi/fnic/fnic_trace.c val.tv_nsec, str, tbp->host_no, tbp->tag, val 65 drivers/scsi/fnic/fnic_trace.h u64 val; val 95 drivers/scsi/fnic/fnic_trace.h trace_buf->timestamp.val = jiffies; \ val 96 drivers/scsi/fnic/fnic_trace.h trace_buf->fnaddr.val = (u64)(unsigned long)_fn; \ val 76 drivers/scsi/fnic/vnic_dev.h static inline void writeq(u64 val, void __iomem *reg) val 78 drivers/scsi/fnic/vnic_dev.h writel(val & 0xffffffff, reg); val 79 drivers/scsi/fnic/vnic_dev.h writel(val >> 32, reg + 0x4UL); val 3184 drivers/scsi/gdth.c int val = 0, c = *++cur_str; val 3187 drivers/scsi/gdth.c val = 0; val 3189 drivers/scsi/gdth.c val = 1; val 3191 drivers/scsi/gdth.c val = (int)simple_strtoul(cur_str, NULL, 0); val 3194 drivers/scsi/gdth.c disable = val; val 3196 drivers/scsi/gdth.c reserve_mode = val; val 3198 drivers/scsi/gdth.c reverse_scan = val; val 3200 drivers/scsi/gdth.c hdr_channel = val; val 3202 drivers/scsi/gdth.c max_ids = val; val 3204 drivers/scsi/gdth.c rescan = val; val 3206 drivers/scsi/gdth.c shared_access = val; val 3208 drivers/scsi/gdth.c reserve_list[0] = val; val 3504 drivers/scsi/hisi_sas/hisi_sas_main.c int val; val 3509 drivers/scsi/hisi_sas/hisi_sas_main.c val = kstrtouint_from_user(buf, count, 0, &phy_no); val 3510 drivers/scsi/hisi_sas/hisi_sas_main.c if (val) val 3511 drivers/scsi/hisi_sas/hisi_sas_main.c return val; val 3632 drivers/scsi/hisi_sas/hisi_sas_main.c int val; val 3634 drivers/scsi/hisi_sas/hisi_sas_main.c val = kstrtouint_from_user(buf, count, 0, &enable); val 3635 drivers/scsi/hisi_sas/hisi_sas_main.c if (val) val 3636 drivers/scsi/hisi_sas/hisi_sas_main.c return val; val 3647 drivers/scsi/hisi_sas/hisi_sas_main.c val = hisi_hba->hw->set_bist(hisi_hba, enable); val 3648 drivers/scsi/hisi_sas/hisi_sas_main.c if (val < 0) val 3649 drivers/scsi/hisi_sas/hisi_sas_main.c return val; val 420 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c u32 off, u32 val) val 424 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c writel(val, regs); val 428 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c int phy_no, u32 off, u32 val) val 432 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c writel(val, regs); val 560 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c u32 val; val 623 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); val 624 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c if (RESET_VALUE != (val & RESET_VALUE)) { val 636 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); val 637 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c if (val & RESET_VALUE) { val 1708 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c u32 val; val 1712 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0); val 1713 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val); val 1714 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1); val 1715 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val); val 1716 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2); val 1717 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val); val 743 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) val 747 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c writel(val, regs); val 751 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c u32 off, u32 val) val 755 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c writel(val, regs); val 1014 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c u32 val; val 1086 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); val 1087 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (reset_val != (val & reset_val)) { val 1099 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c &val); val 1100 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (val & reset_val) { val 2941 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c u32 val; val 2947 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c val = hisi_sas_read32(hisi_hba, ecc_error->reg); val 2948 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c val &= ecc_error->msk; val 2949 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c val >>= ecc_error->shift; val 2951 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c ecc_error->msg, val); val 2961 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c u32 val; val 2967 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c val = hisi_sas_read32(hisi_hba, ecc_error->reg); val 2968 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c val &= ecc_error->msk; val 2969 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c val >>= ecc_error->shift; val 2971 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c ecc_error->msg, irq_value, val); val 3107 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c static void cq_tasklet_v2_hw(unsigned long val) val 3109 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; val 522 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) val 526 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c writel(val, regs); val 530 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 off, u32 val) val 534 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c writel(val, regs); val 545 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ val 549 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ val 552 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ val 556 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ val 848 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 val; val 857 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, val 1917 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 val; val 1923 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c val = hisi_sas_read32(hisi_hba, ecc_error->reg); val 1924 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c val &= ecc_error->msk; val 1925 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c val >>= ecc_error->shift; val 1927 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c ecc_error->msg, irq_value, val); val 2293 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c static void cq_tasklet_v3_hw(unsigned long val) val 2295 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; val 2922 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 i, val; val 2927 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c val = hisi_sas_read32(hisi_hba, TAB_DFX); val 2928 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (val == 0xffffffff) val 2932 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (val != 0xffffffff) { val 2938 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c buf[0] = val; val 32 drivers/scsi/hpsa.h void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); val 443 drivers/scsi/hpsa.h static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) val 445 drivers/scsi/hpsa.h if (val) { /* Turn interrupts on */ val 460 drivers/scsi/hpsa.h static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val) val 462 drivers/scsi/hpsa.h if (val) { /* Turn interrupts on */ val 474 drivers/scsi/hpsa.h static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) val 476 drivers/scsi/hpsa.h if (val) { /* turn on interrupts */ val 191 drivers/scsi/hpsa_cmd.h u64 val; val 283 drivers/scsi/hptiop.c _tag = hba->u.mvfrey.outlist[cur_rptr].val; val 105 drivers/scsi/hptiop.h __le32 val; val 340 drivers/scsi/initio.c u16 val = 0; val 354 drivers/scsi/initio.c val += (rb << i); val 360 drivers/scsi/initio.c return val; val 372 drivers/scsi/initio.c static void initio_se2_wr(unsigned long base, u8 addr, u16 val) val 381 drivers/scsi/initio.c if (val & 0x8000) val 388 drivers/scsi/initio.c val <<= 1; val 1985 drivers/scsi/ipr.h static inline void writeq(u64 val, void __iomem *addr) val 1987 drivers/scsi/ipr.h writel(((u32) (val >> 32)), addr); val 1988 drivers/scsi/ipr.h writel(((u32) (val)), (addr + 4)); val 5253 drivers/scsi/ips.c uint32_t val; val 5257 drivers/scsi/ips.c val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); val 5259 drivers/scsi/ips.c return (val); val 5275 drivers/scsi/ips.c uint32_t val; val 5293 drivers/scsi/ips.c while ((val = val 5298 drivers/scsi/ips.c if (!(val & IPS_BIT_START_STOP)) val 5302 drivers/scsi/ips.c "ips_issue val [0x%x].\n", val); val 5329 drivers/scsi/ips.c uint32_t val; val 5347 drivers/scsi/ips.c while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { val 5351 drivers/scsi/ips.c if (!(val & IPS_BIT_START_STOP)) val 5355 drivers/scsi/ips.c "ips_issue val [0x%x].\n", val); val 1447 drivers/scsi/isci/host.c u32 val; val 1450 drivers/scsi/isci/host.c val = readl(&ihost->smu_registers->clock_gating_control); val 1451 drivers/scsi/isci/host.c val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) | val 1454 drivers/scsi/isci/host.c val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE); val 1455 drivers/scsi/isci/host.c writel(val, &ihost->smu_registers->clock_gating_control); val 2139 drivers/scsi/isci/host.c unsigned long i, state, val; val 2186 drivers/scsi/isci/host.c val = readl(&ihost->smu_registers->device_context_capacity); val 2189 drivers/scsi/isci/host.c ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS); val 2190 drivers/scsi/isci/host.c ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS); val 2191 drivers/scsi/isci/host.c ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES); val 2205 drivers/scsi/isci/host.c val = readl(&ihost->scu_registers->sdma.pdma_configuration); val 2206 drivers/scsi/isci/host.c val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); val 2207 drivers/scsi/isci/host.c writel(val, &ihost->scu_registers->sdma.pdma_configuration); val 2209 drivers/scsi/isci/host.c val = readl(&ihost->scu_registers->sdma.cdma_configuration); val 2210 drivers/scsi/isci/host.c val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); val 2211 drivers/scsi/isci/host.c writel(val, &ihost->scu_registers->sdma.cdma_configuration); val 2765 drivers/scsi/isci/host.c u32 val = 0x444; /* all ODx.n clear */ val 2778 drivers/scsi/isci/host.c val &= ~(bit << ((i << 2) + 2)); val 2783 drivers/scsi/isci/host.c writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]); val 674 drivers/scsi/isci/phy.c u32 val; val 677 drivers/scsi/isci/phy.c val = readl(&iphy->link_layer_registers->transmit_comsas_signal); val 678 drivers/scsi/isci/phy.c val &= ~SCU_SAS_LLTXCOMSAS_GEN_VAL(NEGTIME, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_MASK); val 679 drivers/scsi/isci/phy.c val |= SCU_SAS_LLTXCOMSAS_GEN_VAL(NEGTIME, timeout); val 681 drivers/scsi/isci/phy.c writel(val, &iphy->link_layer_registers->transmit_comsas_signal); val 1204 drivers/scsi/isci/phy.c u32 val; val 1207 drivers/scsi/isci/phy.c val = readl(&ll->phy_configuration); val 1208 drivers/scsi/isci/phy.c val &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) | val 1211 drivers/scsi/isci/phy.c writel(val, &ll->phy_configuration); val 1216 drivers/scsi/isci/phy.c val = readl(&ll->phy_configuration); val 1217 drivers/scsi/isci/phy.c val |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE); val 1218 drivers/scsi/isci/phy.c writel(val, &ll->phy_configuration); val 146 drivers/scsi/isci/port.c u32 val; val 153 drivers/scsi/isci/port.c val = readl(&iphy->link_layer_registers->link_layer_control); val 155 drivers/scsi/isci/port.c writel(val, &iphy->link_layer_registers->link_layer_control); val 831 drivers/scsi/isci/registers.h #define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \ val 832 drivers/scsi/isci/registers.h SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name, val) val 854 drivers/scsi/isci/registers.h #define SCU_PTSGCR_GEN_VAL(name, val) \ val 855 drivers/scsi/isci/registers.h SCU_GEN_VALUE(SCU_PTSG_CONTROL_ ## name, val) val 866 drivers/scsi/isci/registers.h #define SCU_RTCR_GEN_VAL(name, val) \ val 867 drivers/scsi/isci/registers.h SCU_GEN_VALUE(SCU_PTSG_ ## name, val) val 874 drivers/scsi/isci/registers.h #define SCU_RTCCR_GEN_VAL(name, val) \ val 875 drivers/scsi/isci/registers.h SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_ ## name, val) val 32 drivers/scsi/jazz_esp.c static void jazz_esp_write8(struct esp *esp, u8 val, unsigned long reg) val 34 drivers/scsi/jazz_esp.c *(volatile u8 *)(esp->regs + reg) = val; val 3210 drivers/scsi/libiscsi.c int val; val 3306 drivers/scsi/libiscsi.c sscanf(buf, "%d", &val); val 3307 drivers/scsi/libiscsi.c session->discovery_sess = !!val; val 1644 drivers/scsi/lpfc/lpfc_attr.c unsigned long val = 0; val 1651 drivers/scsi/lpfc/lpfc_attr.c rc = kstrtoul(pval, 0, &val); val 1656 drivers/scsi/lpfc/lpfc_attr.c val = 0; val 1661 drivers/scsi/lpfc/lpfc_attr.c switch (val) { val 1663 drivers/scsi/lpfc/lpfc_attr.c val = 0x0; /* Disable */ val 1666 drivers/scsi/lpfc/lpfc_attr.c val = 0x1; /* Enable two port trunk */ val 1669 drivers/scsi/lpfc/lpfc_attr.c val = 0x2; /* Enable four port trunk */ val 1676 drivers/scsi/lpfc/lpfc_attr.c "0070 Set trunk mode with val %ld ", val); val 1688 drivers/scsi/lpfc/lpfc_attr.c val); val 2169 drivers/scsi/lpfc/lpfc_attr.c int val=0; val 2174 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1) val 2177 drivers/scsi/lpfc/lpfc_attr.c if ((val & 0x3) != val) val 2181 drivers/scsi/lpfc/lpfc_attr.c val = 0; val 2185 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_poll, val); val 2191 drivers/scsi/lpfc/lpfc_attr.c if (val & ENABLE_FCP_RING_POLLING) { val 2192 drivers/scsi/lpfc/lpfc_attr.c if ((val & DISABLE_FCP_RING_INT) && val 2204 drivers/scsi/lpfc/lpfc_attr.c } else if (val != 0x0) { val 2209 drivers/scsi/lpfc/lpfc_attr.c if (!(val & DISABLE_FCP_RING_INT) && val 2224 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_poll = val; val 2317 drivers/scsi/lpfc/lpfc_attr.c static inline bool lpfc_rangecheck(uint val, uint min, uint max) val 2319 drivers/scsi/lpfc/lpfc_attr.c return val >= min && val <= max; val 2337 drivers/scsi/lpfc/lpfc_attr.c lpfc_enable_bbcr_set(struct lpfc_hba *phba, uint val) val 2339 drivers/scsi/lpfc/lpfc_attr.c if (lpfc_rangecheck(val, 0, 1) && phba->sli_rev == LPFC_SLI_REV4) { val 2342 drivers/scsi/lpfc/lpfc_attr.c LPFC_DRIVER_NAME, phba->cfg_enable_bbcr, val); val 2343 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_enable_bbcr = val; val 2348 drivers/scsi/lpfc/lpfc_attr.c LPFC_DRIVER_NAME, val); val 2400 drivers/scsi/lpfc/lpfc_attr.c uint val = 0;\ val 2401 drivers/scsi/lpfc/lpfc_attr.c val = phba->cfg_##attr;\ val 2427 drivers/scsi/lpfc/lpfc_attr.c lpfc_##attr##_init(struct lpfc_hba *phba, uint val) \ val 2429 drivers/scsi/lpfc/lpfc_attr.c if (lpfc_rangecheck(val, minval, maxval)) {\ val 2430 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_##attr = val;\ val 2435 drivers/scsi/lpfc/lpfc_attr.c "allowed range is ["#minval", "#maxval"]\n", val); \ val 2462 drivers/scsi/lpfc/lpfc_attr.c lpfc_##attr##_set(struct lpfc_hba *phba, uint val) \ val 2464 drivers/scsi/lpfc/lpfc_attr.c if (lpfc_rangecheck(val, minval, maxval)) {\ val 2467 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_##attr, val); \ val 2468 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_##attr = val;\ val 2473 drivers/scsi/lpfc/lpfc_attr.c "allowed range is ["#minval", "#maxval"]\n", val); \ val 2506 drivers/scsi/lpfc/lpfc_attr.c uint val = 0;\ val 2509 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1)\ val 2511 drivers/scsi/lpfc/lpfc_attr.c if (lpfc_##attr##_set(phba, val) == 0) \ val 2586 drivers/scsi/lpfc/lpfc_attr.c lpfc_##attr##_init(struct lpfc_vport *vport, uint val) \ val 2588 drivers/scsi/lpfc/lpfc_attr.c if (lpfc_rangecheck(val, minval, maxval)) {\ val 2589 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_##attr = val;\ val 2594 drivers/scsi/lpfc/lpfc_attr.c "allowed range is ["#minval", "#maxval"]\n", val); \ val 2618 drivers/scsi/lpfc/lpfc_attr.c lpfc_##attr##_set(struct lpfc_vport *vport, uint val) \ val 2620 drivers/scsi/lpfc/lpfc_attr.c if (lpfc_rangecheck(val, minval, maxval)) {\ val 2625 drivers/scsi/lpfc/lpfc_attr.c val, val); \ val 2626 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_##attr = val;\ val 2631 drivers/scsi/lpfc/lpfc_attr.c "allowed range is ["#minval", "#maxval"]\n", val); \ val 2659 drivers/scsi/lpfc/lpfc_attr.c uint val = 0;\ val 2662 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1)\ val 2664 drivers/scsi/lpfc/lpfc_attr.c if (lpfc_##attr##_set(vport, val) == 0) \ val 3089 drivers/scsi/lpfc/lpfc_attr.c unsigned long val; val 3099 drivers/scsi/lpfc/lpfc_attr.c ret = kstrtoul(buf, 0, &val); val 3100 drivers/scsi/lpfc/lpfc_attr.c if (ret || (val > 0x7f)) val 3103 drivers/scsi/lpfc/lpfc_attr.c if (val) val 3104 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_oas_priority = (uint8_t)val; val 3223 drivers/scsi/lpfc/lpfc_attr.c int val = 0; val 3231 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1) val 3234 drivers/scsi/lpfc/lpfc_attr.c if ((val != 0) && (val != 1)) val 3237 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_oas_lun_state = val; val 3631 drivers/scsi/lpfc/lpfc_attr.c lpfc_nodev_tmo_init(struct lpfc_vport *vport, int val) val 3635 drivers/scsi/lpfc/lpfc_attr.c if (val != LPFC_DEF_DEVLOSS_TMO) val 3643 drivers/scsi/lpfc/lpfc_attr.c if (val >= LPFC_MIN_DEVLOSS_TMO && val <= LPFC_MAX_DEVLOSS_TMO) { val 3644 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_nodev_tmo = val; val 3645 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_devloss_tmo = val; val 3651 drivers/scsi/lpfc/lpfc_attr.c val, LPFC_MIN_DEVLOSS_TMO, LPFC_MAX_DEVLOSS_TMO); val 3710 drivers/scsi/lpfc/lpfc_attr.c lpfc_nodev_tmo_set(struct lpfc_vport *vport, int val) val 3719 drivers/scsi/lpfc/lpfc_attr.c if (val >= LPFC_MIN_DEVLOSS_TMO && val <= LPFC_MAX_DEVLOSS_TMO) { val 3720 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_nodev_tmo = val; val 3721 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_devloss_tmo = val; val 3726 drivers/scsi/lpfc/lpfc_attr.c fc_host_dev_loss_tmo(lpfc_shost_from_vport(vport)) = val; val 3733 drivers/scsi/lpfc/lpfc_attr.c val, LPFC_MIN_DEVLOSS_TMO, LPFC_MAX_DEVLOSS_TMO); val 3769 drivers/scsi/lpfc/lpfc_attr.c lpfc_devloss_tmo_set(struct lpfc_vport *vport, int val) val 3771 drivers/scsi/lpfc/lpfc_attr.c if (val >= LPFC_MIN_DEVLOSS_TMO && val <= LPFC_MAX_DEVLOSS_TMO) { val 3772 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_nodev_tmo = val; val 3773 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_devloss_tmo = val; val 3775 drivers/scsi/lpfc/lpfc_attr.c fc_host_dev_loss_tmo(lpfc_shost_from_vport(vport)) = val; val 3783 drivers/scsi/lpfc/lpfc_attr.c val, LPFC_MIN_DEVLOSS_TMO, LPFC_MAX_DEVLOSS_TMO); val 3878 drivers/scsi/lpfc/lpfc_attr.c lpfc_tgt_queue_depth_set(struct lpfc_vport *vport, uint val) val 3883 drivers/scsi/lpfc/lpfc_attr.c if (!lpfc_rangecheck(val, LPFC_MIN_TGT_QDEPTH, LPFC_MAX_TGT_QDEPTH)) val 3886 drivers/scsi/lpfc/lpfc_attr.c if (val == vport->cfg_tgt_queue_depth) val 3890 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_tgt_queue_depth = val; val 3959 drivers/scsi/lpfc/lpfc_attr.c lpfc_restrict_login_init(struct lpfc_vport *vport, int val) val 3961 drivers/scsi/lpfc/lpfc_attr.c if (val < 0 || val > 1) { val 3965 drivers/scsi/lpfc/lpfc_attr.c val); val 3973 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_restrict_login = val; val 3994 drivers/scsi/lpfc/lpfc_attr.c lpfc_restrict_login_set(struct lpfc_vport *vport, int val) val 3996 drivers/scsi/lpfc/lpfc_attr.c if (val < 0 || val > 1) { val 4000 drivers/scsi/lpfc/lpfc_attr.c val); val 4004 drivers/scsi/lpfc/lpfc_attr.c if (vport->port_type == LPFC_PHYSICAL_PORT && val != 0) { val 4011 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_restrict_login = val; val 4074 drivers/scsi/lpfc/lpfc_attr.c int val = 0; val 4087 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(val_buf, "%i", &val) != 1) val 4090 drivers/scsi/lpfc/lpfc_attr.c if (val >= 0 && val <= 6) { val 4093 drivers/scsi/lpfc/lpfc_attr.c val == 4) { val 4096 drivers/scsi/lpfc/lpfc_attr.c val); val 4101 drivers/scsi/lpfc/lpfc_attr.c val == 4) { val 4106 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_topology = val; val 4112 drivers/scsi/lpfc/lpfc_attr.c prev_val, val); val 4113 drivers/scsi/lpfc/lpfc_attr.c if (prev_val != val && phba->sli_rev == LPFC_SLI_REV4) val 4125 drivers/scsi/lpfc/lpfc_attr.c phba->brd_no, val); val 4516 drivers/scsi/lpfc/lpfc_attr.c int val = LPFC_USER_LINK_SPEED_AUTO; val 4534 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(val_buf, "%i", &val) != 1) val 4539 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_link_speed, val, nolip ? "(nolip)" : "(lip)"); val 4541 drivers/scsi/lpfc/lpfc_attr.c if (((val == LPFC_USER_LINK_SPEED_1G) && !(phba->lmt & LMT_1Gb)) || val 4542 drivers/scsi/lpfc/lpfc_attr.c ((val == LPFC_USER_LINK_SPEED_2G) && !(phba->lmt & LMT_2Gb)) || val 4543 drivers/scsi/lpfc/lpfc_attr.c ((val == LPFC_USER_LINK_SPEED_4G) && !(phba->lmt & LMT_4Gb)) || val 4544 drivers/scsi/lpfc/lpfc_attr.c ((val == LPFC_USER_LINK_SPEED_8G) && !(phba->lmt & LMT_8Gb)) || val 4545 drivers/scsi/lpfc/lpfc_attr.c ((val == LPFC_USER_LINK_SPEED_10G) && !(phba->lmt & LMT_10Gb)) || val 4546 drivers/scsi/lpfc/lpfc_attr.c ((val == LPFC_USER_LINK_SPEED_16G) && !(phba->lmt & LMT_16Gb)) || val 4547 drivers/scsi/lpfc/lpfc_attr.c ((val == LPFC_USER_LINK_SPEED_32G) && !(phba->lmt & LMT_32Gb)) || val 4548 drivers/scsi/lpfc/lpfc_attr.c ((val == LPFC_USER_LINK_SPEED_64G) && !(phba->lmt & LMT_64Gb))) { val 4552 drivers/scsi/lpfc/lpfc_attr.c val); val 4555 drivers/scsi/lpfc/lpfc_attr.c if (val >= LPFC_USER_LINK_SPEED_16G && val 4560 drivers/scsi/lpfc/lpfc_attr.c val); val 4564 drivers/scsi/lpfc/lpfc_attr.c switch (val) { val 4574 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_link_speed = val; val 4591 drivers/scsi/lpfc/lpfc_attr.c val, LPFC_LINK_SPEED_STRING); val 4618 drivers/scsi/lpfc/lpfc_attr.c lpfc_link_speed_init(struct lpfc_hba *phba, int val) val 4620 drivers/scsi/lpfc/lpfc_attr.c if (val >= LPFC_USER_LINK_SPEED_16G && phba->cfg_topology == 4) { val 4624 drivers/scsi/lpfc/lpfc_attr.c val); val 4628 drivers/scsi/lpfc/lpfc_attr.c switch (val) { val 4637 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_link_speed = val; val 4643 drivers/scsi/lpfc/lpfc_attr.c "["LPFC_LINK_SPEED_STRING"]\n", val); val 4695 drivers/scsi/lpfc/lpfc_attr.c int val = 0, rc = -EINVAL; val 4699 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1) val 4702 drivers/scsi/lpfc/lpfc_attr.c switch (val) { val 4770 drivers/scsi/lpfc/lpfc_attr.c int val, rc = -1; val 4774 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1) val 4776 drivers/scsi/lpfc/lpfc_attr.c if (val != 1) val 4838 drivers/scsi/lpfc/lpfc_attr.c int val = 0, rc = -EINVAL; val 4843 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1) val 4845 drivers/scsi/lpfc/lpfc_attr.c if (val < 0) val 4849 drivers/scsi/lpfc/lpfc_attr.c if (val == 0) { val 4866 drivers/scsi/lpfc/lpfc_attr.c if (val <= LPFC_MAX_VFN_PER_PFN) val 4867 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_sriov_nr_virtfn = val; val 4871 drivers/scsi/lpfc/lpfc_attr.c "allowed.\n", val); val 4914 drivers/scsi/lpfc/lpfc_attr.c int val = 0, rc = -EINVAL; val 4919 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1) val 4921 drivers/scsi/lpfc/lpfc_attr.c if (val != 1) val 4950 drivers/scsi/lpfc/lpfc_attr.c lpfc_request_firmware_upgrade_init(struct lpfc_hba *phba, int val) val 4952 drivers/scsi/lpfc/lpfc_attr.c if (val >= 0 && val <= 1) { val 4953 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_request_firmware_upgrade = val; val 5014 drivers/scsi/lpfc/lpfc_attr.c lpfc_force_rscn_init(struct lpfc_hba *phba, int val) val 5046 drivers/scsi/lpfc/lpfc_attr.c int val = 0, i; val 5055 drivers/scsi/lpfc/lpfc_attr.c if (sscanf(buf, "%i", &val) != 1) val 5063 drivers/scsi/lpfc/lpfc_attr.c if (val && (val < LPFC_MIN_IMAX || val > LPFC_MAX_IMAX)) val 5066 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_auto_imax = (val) ? 0 : 1; val 5067 drivers/scsi/lpfc/lpfc_attr.c if (phba->cfg_fcp_imax && !val) { val 5077 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_fcp_imax = (uint32_t)val; val 5117 drivers/scsi/lpfc/lpfc_attr.c lpfc_fcp_imax_init(struct lpfc_hba *phba, int val) val 5124 drivers/scsi/lpfc/lpfc_attr.c if ((val >= LPFC_MIN_IMAX && val <= LPFC_MAX_IMAX) || val 5125 drivers/scsi/lpfc/lpfc_attr.c (val == 0)) { val 5126 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_fcp_imax = val; val 5132 drivers/scsi/lpfc/lpfc_attr.c val); val 5164 drivers/scsi/lpfc/lpfc_attr.c unsigned long val; val 5174 drivers/scsi/lpfc/lpfc_attr.c if (kstrtoul(buf, 0, &val)) val 5177 drivers/scsi/lpfc/lpfc_attr.c if (val < LPFC_CQ_MIN_PROC_LIMIT || val > LPFC_CQ_MAX_PROC_LIMIT) val 5180 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_cq_max_proc_limit = (uint32_t)val; val 5233 drivers/scsi/lpfc/lpfc_attr.c lpfc_cq_max_proc_limit_init(struct lpfc_hba *phba, int val) val 5240 drivers/scsi/lpfc/lpfc_attr.c if (val >= LPFC_CQ_MIN_PROC_LIMIT && val <= LPFC_CQ_MAX_PROC_LIMIT) { val 5241 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_cq_max_proc_limit = val; val 5411 drivers/scsi/lpfc/lpfc_attr.c lpfc_fcp_cpu_map_init(struct lpfc_hba *phba, int val) val 5418 drivers/scsi/lpfc/lpfc_attr.c if (val >= LPFC_MIN_CPU_MAP && val <= LPFC_MAX_CPU_MAP) { val 5419 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_fcp_cpu_map = val; val 5425 drivers/scsi/lpfc/lpfc_attr.c "default\n", val); val 5491 drivers/scsi/lpfc/lpfc_attr.c lpfc_max_scsicmpl_time_set(struct lpfc_vport *vport, int val) val 5496 drivers/scsi/lpfc/lpfc_attr.c if (val == vport->cfg_max_scsicmpl_time) val 5498 drivers/scsi/lpfc/lpfc_attr.c if ((val < 0) || (val > 60000)) val 5500 drivers/scsi/lpfc/lpfc_attr.c vport->cfg_max_scsicmpl_time = val; val 5908 drivers/scsi/lpfc/lpfc_attr.c lpfc_sg_seg_cnt_init(struct lpfc_hba *phba, int val) val 5910 drivers/scsi/lpfc/lpfc_attr.c if (val >= LPFC_MIN_SG_SEG_CNT && val <= LPFC_MAX_SG_SEG_CNT) { val 5911 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_sg_seg_cnt = val; val 5917 drivers/scsi/lpfc/lpfc_attr.c val, LPFC_MIN_SG_SEG_CNT, LPFC_MAX_SG_SEG_CNT); val 63 drivers/scsi/mac_esp.c static inline void mac_esp_write8(struct esp *esp, u8 val, unsigned long reg) val 65 drivers/scsi/mac_esp.c nubus_writeb(val, esp->regs + reg * 16); val 3169 drivers/scsi/megaraid/megaraid_sas_base.c int val = 0; val 3172 drivers/scsi/megaraid/megaraid_sas_base.c if (kstrtoint(buf, 0, &val) != 0) val 3176 drivers/scsi/megaraid/megaraid_sas_base.c instance->fw_crash_buffer_offset = val; val 3245 drivers/scsi/megaraid/megaraid_sas_base.c int val = 0; val 3248 drivers/scsi/megaraid/megaraid_sas_base.c if (kstrtoint(buf, 0, &val) != 0) val 3251 drivers/scsi/megaraid/megaraid_sas_base.c if ((val <= AVAILABLE || val > COPY_ERROR)) { val 3257 drivers/scsi/megaraid/megaraid_sas_base.c instance->fw_crash_state = val; val 3259 drivers/scsi/megaraid/megaraid_sas_base.c if ((val == COPIED) || (val == COPY_ERROR)) { val 3263 drivers/scsi/megaraid/megaraid_sas_base.c if (val == COPY_ERROR) val 3327 drivers/scsi/megaraid/megaraid_sas_base.c u32 val = 0; val 3332 drivers/scsi/megaraid/megaraid_sas_base.c if (kstrtou32(buf, 0, &val) != 0) { val 3338 drivers/scsi/megaraid/megaraid_sas_base.c if (val) val 2514 drivers/scsi/megaraid/megaraid_sas_fusion.c u8 val = cdb[1] & 0xE0; val 2517 drivers/scsi/megaraid/megaraid_sas_fusion.c cdb[1] = val | ((u8)(start_blk >> 16) & 0x1f); val 165 drivers/scsi/mpt3sas/mpt3sas_base.c _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp) val 167 drivers/scsi/mpt3sas/mpt3sas_base.c int ret = param_set_int(val, kp); val 2801 drivers/scsi/mpt3sas/mpt3sas_ctl.c int val = 0; val 2803 drivers/scsi/mpt3sas/mpt3sas_ctl.c if (sscanf(buf, "%x", &val) != 1) val 2806 drivers/scsi/mpt3sas/mpt3sas_ctl.c ioc->logging_level = val; val 2837 drivers/scsi/mpt3sas/mpt3sas_ctl.c int val = 0; val 2839 drivers/scsi/mpt3sas/mpt3sas_ctl.c if (sscanf(buf, "%d", &val) != 1) val 2842 drivers/scsi/mpt3sas/mpt3sas_ctl.c ioc->fwfault_debug = val; val 3076 drivers/scsi/mpt3sas/mpt3sas_ctl.c int val = 0; val 3078 drivers/scsi/mpt3sas/mpt3sas_ctl.c if (sscanf(buf, "%d", &val) != 1) val 3081 drivers/scsi/mpt3sas/mpt3sas_ctl.c ioc->ring_buffer_offset = val; val 3452 drivers/scsi/mpt3sas/mpt3sas_ctl.c int val = 0; val 3457 drivers/scsi/mpt3sas/mpt3sas_ctl.c if (kstrtoint(buf, 0, &val) != 0) val 3460 drivers/scsi/mpt3sas/mpt3sas_ctl.c switch (val) { val 296 drivers/scsi/mpt3sas/mpt3sas_scsih.c _scsih_set_debug_level(const char *val, const struct kernel_param *kp) val 298 drivers/scsi/mpt3sas/mpt3sas_scsih.c int ret = param_set_int(val, kp); val 15 drivers/scsi/mvsas/mv_chips.h #define mw32(reg, val) writel((val), regs + reg) val 16 drivers/scsi/mvsas/mv_chips.h #define mw32_f(reg, val) do { \ val 17 drivers/scsi/mvsas/mv_chips.h mw32(reg, val); \ val 21 drivers/scsi/mvsas/mv_chips.h #define iow32(reg, val) outl(val, (unsigned long)(regs + reg)) val 23 drivers/scsi/mvsas/mv_chips.h #define iow16(reg, val) outw((unsigned long)(val, regs + reg)) val 25 drivers/scsi/mvsas/mv_chips.h #define iow8(reg, val) outb((unsigned long)(val, regs + reg)) val 35 drivers/scsi/mvsas/mv_chips.h static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val) val 39 drivers/scsi/mvsas/mv_chips.h mw32(MVS_CMD_DATA, val); val 49 drivers/scsi/mvsas/mv_chips.h static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val) val 53 drivers/scsi/mvsas/mv_chips.h mw32(MVS_P0_SER_CTLSTAT + port * 4, val); val 55 drivers/scsi/mvsas/mv_chips.h mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val); val 68 drivers/scsi/mvsas/mv_chips.h u32 port, u32 val) val 73 drivers/scsi/mvsas/mv_chips.h writel(val, regs + port * 8); val 75 drivers/scsi/mvsas/mv_chips.h writel(val, regs2 + (port - 4) * 8); val 85 drivers/scsi/mvsas/mv_chips.h u32 port, u32 val) val 88 drivers/scsi/mvsas/mv_chips.h MVS_P4_CFG_DATA, port, val); val 106 drivers/scsi/mvsas/mv_chips.h u32 port, u32 val) val 109 drivers/scsi/mvsas/mv_chips.h MVS_P4_VSR_DATA, port, val); val 127 drivers/scsi/mvsas/mv_chips.h u32 port, u32 val) val 130 drivers/scsi/mvsas/mv_chips.h MVS_P4_INT_STAT, port, val); val 141 drivers/scsi/mvsas/mv_chips.h u32 port, u32 val) val 144 drivers/scsi/mvsas/mv_chips.h MVS_P4_INT_MASK, port, val); val 712 drivers/scsi/mvsas/mv_init.c unsigned int val = 0; val 720 drivers/scsi/mvsas/mv_init.c if (sscanf(buffer, "%u", &val) != 1) val 723 drivers/scsi/mvsas/mv_init.c if (val >= 0x10000) { val 725 drivers/scsi/mvsas/mv_init.c "too long\n", val); val 729 drivers/scsi/mvsas/mv_init.c interrupt_coalescing = val; val 101 drivers/scsi/mvsas/mv_sas.h void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val); val 104 drivers/scsi/mvsas/mv_sas.h void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val); val 108 drivers/scsi/mvsas/mv_sas.h void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val); val 112 drivers/scsi/mvsas/mv_sas.h void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val); val 115 drivers/scsi/mvsas/mv_sas.h void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val); val 2404 drivers/scsi/myrs.c __le32 val = cpu_to_le32(DAC960_GEM_IDB_HWMBOX_NEW_CMD << 24); val 2406 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_READ_OFFSET); val 2411 drivers/scsi/myrs.c __le32 val = cpu_to_le32(DAC960_GEM_IDB_HWMBOX_ACK_STS << 24); val 2413 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_CLEAR_OFFSET); val 2418 drivers/scsi/myrs.c __le32 val = cpu_to_le32(DAC960_GEM_IDB_GEN_IRQ << 24); val 2420 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_READ_OFFSET); val 2425 drivers/scsi/myrs.c __le32 val = cpu_to_le32(DAC960_GEM_IDB_CTRL_RESET << 24); val 2427 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_READ_OFFSET); val 2432 drivers/scsi/myrs.c __le32 val = cpu_to_le32(DAC960_GEM_IDB_HWMBOX_NEW_CMD << 24); val 2434 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_READ_OFFSET); val 2439 drivers/scsi/myrs.c __le32 val; val 2441 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_IDB_READ_OFFSET); val 2442 drivers/scsi/myrs.c return (le32_to_cpu(val) >> 24) & DAC960_GEM_IDB_HWMBOX_FULL; val 2447 drivers/scsi/myrs.c __le32 val; val 2449 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_IDB_READ_OFFSET); val 2450 drivers/scsi/myrs.c return (le32_to_cpu(val) >> 24) & DAC960_GEM_IDB_INIT_IN_PROGRESS; val 2455 drivers/scsi/myrs.c __le32 val = cpu_to_le32(DAC960_GEM_ODB_HWMBOX_ACK_IRQ << 24); val 2457 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_ODB_CLEAR_OFFSET); val 2462 drivers/scsi/myrs.c __le32 val = cpu_to_le32(DAC960_GEM_ODB_MMBOX_ACK_IRQ << 24); val 2464 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_ODB_CLEAR_OFFSET); val 2469 drivers/scsi/myrs.c __le32 val = cpu_to_le32((DAC960_GEM_ODB_HWMBOX_ACK_IRQ | val 2472 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_ODB_CLEAR_OFFSET); val 2477 drivers/scsi/myrs.c __le32 val; val 2479 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_ODB_READ_OFFSET); val 2480 drivers/scsi/myrs.c return (le32_to_cpu(val) >> 24) & DAC960_GEM_ODB_HWMBOX_STS_AVAIL; val 2485 drivers/scsi/myrs.c __le32 val; val 2487 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_ODB_READ_OFFSET); val 2488 drivers/scsi/myrs.c return (le32_to_cpu(val) >> 24) & DAC960_GEM_ODB_MMBOX_STS_AVAIL; val 2493 drivers/scsi/myrs.c __le32 val = cpu_to_le32((DAC960_GEM_IRQMASK_HWMBOX_IRQ | val 2495 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IRQMASK_CLEAR_OFFSET); val 2500 drivers/scsi/myrs.c __le32 val = 0; val 2502 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IRQMASK_READ_OFFSET); val 2507 drivers/scsi/myrs.c __le32 val; val 2509 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_IRQMASK_READ_OFFSET); val 2510 drivers/scsi/myrs.c return !((le32_to_cpu(val) >> 24) & val 2547 drivers/scsi/myrs.c __le32 val; val 2549 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_ERRSTS_READ_OFFSET); val 2550 drivers/scsi/myrs.c if (!((le32_to_cpu(val) >> 24) & DAC960_GEM_ERRSTS_PENDING)) val 2552 drivers/scsi/myrs.c *error = val & ~(DAC960_GEM_ERRSTS_PENDING << 24); val 2699 drivers/scsi/myrs.c u8 val; val 2701 drivers/scsi/myrs.c val = readb(base + DAC960_BA_IDB_OFFSET); val 2702 drivers/scsi/myrs.c return !(val & DAC960_BA_IDB_HWMBOX_EMPTY); val 2707 drivers/scsi/myrs.c u8 val; val 2709 drivers/scsi/myrs.c val = readb(base + DAC960_BA_IDB_OFFSET); val 2710 drivers/scsi/myrs.c return !(val & DAC960_BA_IDB_INIT_DONE); val 2731 drivers/scsi/myrs.c u8 val; val 2733 drivers/scsi/myrs.c val = readb(base + DAC960_BA_ODB_OFFSET); val 2734 drivers/scsi/myrs.c return val & DAC960_BA_ODB_HWMBOX_STS_AVAIL; val 2739 drivers/scsi/myrs.c u8 val; val 2741 drivers/scsi/myrs.c val = readb(base + DAC960_BA_ODB_OFFSET); val 2742 drivers/scsi/myrs.c return val & DAC960_BA_ODB_MMBOX_STS_AVAIL; val 2757 drivers/scsi/myrs.c u8 val; val 2759 drivers/scsi/myrs.c val = readb(base + DAC960_BA_IRQMASK_OFFSET); val 2760 drivers/scsi/myrs.c return !(val & DAC960_BA_IRQMASK_DISABLE_IRQ); val 2796 drivers/scsi/myrs.c u8 val; val 2798 drivers/scsi/myrs.c val = readb(base + DAC960_BA_ERRSTS_OFFSET); val 2799 drivers/scsi/myrs.c if (!(val & DAC960_BA_ERRSTS_PENDING)) val 2801 drivers/scsi/myrs.c val &= ~DAC960_BA_ERRSTS_PENDING; val 2802 drivers/scsi/myrs.c *error = val; val 2949 drivers/scsi/myrs.c u8 val; val 2951 drivers/scsi/myrs.c val = readb(base + DAC960_LP_IDB_OFFSET); val 2952 drivers/scsi/myrs.c return val & DAC960_LP_IDB_HWMBOX_FULL; val 2957 drivers/scsi/myrs.c u8 val; val 2959 drivers/scsi/myrs.c val = readb(base + DAC960_LP_IDB_OFFSET); val 2960 drivers/scsi/myrs.c return val & DAC960_LP_IDB_INIT_IN_PROGRESS; val 2981 drivers/scsi/myrs.c u8 val; val 2983 drivers/scsi/myrs.c val = readb(base + DAC960_LP_ODB_OFFSET); val 2984 drivers/scsi/myrs.c return val & DAC960_LP_ODB_HWMBOX_STS_AVAIL; val 2989 drivers/scsi/myrs.c u8 val; val 2991 drivers/scsi/myrs.c val = readb(base + DAC960_LP_ODB_OFFSET); val 2992 drivers/scsi/myrs.c return val & DAC960_LP_ODB_MMBOX_STS_AVAIL; val 3007 drivers/scsi/myrs.c u8 val; val 3009 drivers/scsi/myrs.c val = readb(base + DAC960_LP_IRQMASK_OFFSET); val 3010 drivers/scsi/myrs.c return !(val & DAC960_LP_IRQMASK_DISABLE_IRQ); val 3045 drivers/scsi/myrs.c u8 val; val 3047 drivers/scsi/myrs.c val = readb(base + DAC960_LP_ERRSTS_OFFSET); val 3048 drivers/scsi/myrs.c if (!(val & DAC960_LP_ERRSTS_PENDING)) val 3050 drivers/scsi/myrs.c val &= ~DAC960_LP_ERRSTS_PENDING; val 3051 drivers/scsi/myrs.c *error = val; val 657 drivers/scsi/ncr53c8xx.c int i, val, c; val 663 drivers/scsi/ncr53c8xx.c val = 0; val 668 drivers/scsi/ncr53c8xx.c val = 0; val 670 drivers/scsi/ncr53c8xx.c val = 1; val 672 drivers/scsi/ncr53c8xx.c val = (int) simple_strtoul(pv, &pe, 0); val 676 drivers/scsi/ncr53c8xx.c driver_setup.default_tags = val; val 687 drivers/scsi/ncr53c8xx.c driver_setup.master_parity = val; val 690 drivers/scsi/ncr53c8xx.c driver_setup.scsi_parity = val; val 693 drivers/scsi/ncr53c8xx.c driver_setup.disconnection = val; val 696 drivers/scsi/ncr53c8xx.c driver_setup.special_features = val; val 699 drivers/scsi/ncr53c8xx.c driver_setup.force_sync_nego = val; val 702 drivers/scsi/ncr53c8xx.c driver_setup.reverse_probe = val; val 705 drivers/scsi/ncr53c8xx.c driver_setup.default_sync = val; val 708 drivers/scsi/ncr53c8xx.c driver_setup.verbose = val; val 711 drivers/scsi/ncr53c8xx.c driver_setup.debug = val; val 714 drivers/scsi/ncr53c8xx.c driver_setup.burst_max = val; val 717 drivers/scsi/ncr53c8xx.c driver_setup.led_pin = val; val 720 drivers/scsi/ncr53c8xx.c driver_setup.max_wide = val? 1:0; val 723 drivers/scsi/ncr53c8xx.c driver_setup.settle_delay = val; val 726 drivers/scsi/ncr53c8xx.c driver_setup.diff_support = val; val 729 drivers/scsi/ncr53c8xx.c driver_setup.irqm = val; val 732 drivers/scsi/ncr53c8xx.c driver_setup.pci_fix_up = val; val 735 drivers/scsi/ncr53c8xx.c driver_setup.bus_check = val; val 738 drivers/scsi/ncr53c8xx.c driver_setup.optimize = val; val 741 drivers/scsi/ncr53c8xx.c driver_setup.recovery = val; val 744 drivers/scsi/ncr53c8xx.c driver_setup.use_nvram = val; val 752 drivers/scsi/ncr53c8xx.c driver_setup.excludes[xi++] = val; val 755 drivers/scsi/ncr53c8xx.c driver_setup.host_id = val; val 759 drivers/scsi/ncr53c8xx.c driver_setup.iarb = val; val 380 drivers/scsi/ncr53c8xx.h #define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o)) val 387 drivers/scsi/ncr53c8xx.h #define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o)) val 388 drivers/scsi/ncr53c8xx.h #define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o)) val 395 drivers/scsi/ncr53c8xx.h #define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o)) val 396 drivers/scsi/ncr53c8xx.h #define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o)) val 410 drivers/scsi/ncr53c8xx.h #define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0) val 412 drivers/scsi/ncr53c8xx.h #define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o)) val 414 drivers/scsi/ncr53c8xx.h #define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o)) val 422 drivers/scsi/ncr53c8xx.h #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val)) val 423 drivers/scsi/ncr53c8xx.h #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val)) val 424 drivers/scsi/ncr53c8xx.h #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val)) val 2911 drivers/scsi/nsp32.c int ret, val, i; val 2946 drivers/scsi/nsp32.c val = nsp32_prom_read(data, i); val 2948 drivers/scsi/nsp32.c "rom address 0x%x : 0x%x", i, val); val 3073 drivers/scsi/nsp32.c int entry, val; val 3090 drivers/scsi/nsp32.c val = 0x0c; val 3093 drivers/scsi/nsp32.c val = 0x19; val 3096 drivers/scsi/nsp32.c val = 0x32; val 3099 drivers/scsi/nsp32.c val = 0x00; val 3102 drivers/scsi/nsp32.c val = 0x0c; val 3105 drivers/scsi/nsp32.c entry = nsp32_search_period_entry(data, target, val); val 3122 drivers/scsi/nsp32.c int i, val; val 3169 drivers/scsi/nsp32.c val = 0; val 3171 drivers/scsi/nsp32.c val += (nsp32_prom_read_bit(data) << i); val 3180 drivers/scsi/nsp32.c return val; val 3183 drivers/scsi/nsp32.c static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val) val 3190 drivers/scsi/nsp32.c if (val == 0) { val 3246 drivers/scsi/nsp32.c static void nsp32_prom_write_bit(nsp32_hw_data *data, int val) val 3249 drivers/scsi/nsp32.c nsp32_prom_set(data, SDA, val); val 3256 drivers/scsi/nsp32.c int val; val 3262 drivers/scsi/nsp32.c val = nsp32_prom_get(data, SDA); val 3267 drivers/scsi/nsp32.c return val; val 14 drivers/scsi/nsp32_io.h unsigned char val) val 16 drivers/scsi/nsp32_io.h outb(val, (base + index)); val 27 drivers/scsi/nsp32_io.h unsigned short val) val 29 drivers/scsi/nsp32_io.h outw(val, (base + index)); val 40 drivers/scsi/nsp32_io.h unsigned long val) val 42 drivers/scsi/nsp32_io.h outl(val, (base + index)); val 55 drivers/scsi/nsp32_io.h unsigned char val) val 61 drivers/scsi/nsp32_io.h writeb(val, ptr); val 76 drivers/scsi/nsp32_io.h unsigned short val) val 82 drivers/scsi/nsp32_io.h writew(cpu_to_le16(val), ptr); val 97 drivers/scsi/nsp32_io.h unsigned long val) val 103 drivers/scsi/nsp32_io.h writel(cpu_to_le32(val), ptr); val 127 drivers/scsi/nsp32_io.h unsigned char val) val 130 drivers/scsi/nsp32_io.h outb(val, base + DATA_REG_LOW); val 142 drivers/scsi/nsp32_io.h unsigned short val) val 145 drivers/scsi/nsp32_io.h outw(val, base + DATA_REG_LOW); val 162 drivers/scsi/nsp32_io.h unsigned long val) val 166 drivers/scsi/nsp32_io.h h = (val & 0xffff0000) >> 16; val 167 drivers/scsi/nsp32_io.h l = (val & 0x0000ffff) >> 0; val 190 drivers/scsi/nsp32_io.h unsigned char val) val 198 drivers/scsi/nsp32_io.h writeb(val, data_ptr ); val 215 drivers/scsi/nsp32_io.h unsigned short val) val 223 drivers/scsi/nsp32_io.h writew(cpu_to_le16(val), data_ptr ); val 17 drivers/scsi/pcmcia/nsp_io.h unsigned char val); val 32 drivers/scsi/pcmcia/nsp_io.h unsigned char val) val 34 drivers/scsi/pcmcia/nsp_io.h outb(val, (base + index)); val 180 drivers/scsi/pcmcia/nsp_io.h unsigned char val) val 184 drivers/scsi/pcmcia/nsp_io.h writeb(val, ptr); val 209 drivers/scsi/pcmcia/nsp_io.h unsigned char val) val 215 drivers/scsi/pcmcia/nsp_io.h writeb(val, data_ptr); val 49 drivers/scsi/pm8001/pm8001_chips.h static inline void pm8001_write_32(void *addr, u32 offset, __le32 val) val 51 drivers/scsi/pm8001/pm8001_chips.h *((__le32 *)(addr + offset)) = val; val 61 drivers/scsi/pm8001/pm8001_chips.h u32 addr, u32 val) val 63 drivers/scsi/pm8001/pm8001_chips.h writel(val, pm8001_ha->io_mem[bar].memvirtaddr + addr); val 69 drivers/scsi/pm8001/pm8001_chips.h static inline void pm8001_mw32(void __iomem *addr, u32 offset, u32 val) val 71 drivers/scsi/pm8001/pm8001_chips.h writel(val, addr + offset); val 316 drivers/scsi/pm8001/pm8001_ctl.c int val = 0; val 318 drivers/scsi/pm8001/pm8001_ctl.c if (sscanf(buf, "%x", &val) != 1) val 321 drivers/scsi/pm8001/pm8001_ctl.c pm8001_ha->logging_level = val; val 4022 drivers/scsi/pmcraid.c u8 val; val 4024 drivers/scsi/pmcraid.c if (kstrtou8(buf, 10, &val)) val 4027 drivers/scsi/pmcraid.c if (val > 2) val 4032 drivers/scsi/pmcraid.c pinstance->current_log_level = val; val 31 drivers/scsi/qedf/drv_fcoe_fw_funcs.c u32 io_size, val; val 55 drivers/scsi/qedf/drv_fcoe_fw_funcs.c val = cpu_to_le32(task_params->cq_rss_number); val 56 drivers/scsi/qedf/drv_fcoe_fw_funcs.c t_st_ctx->read_only.glbl_q_num = val; val 69 drivers/scsi/qedf/drv_fcoe_fw_funcs.c val = cpu_to_le32(sense_data_buffer_phys_addr.hi); val 70 drivers/scsi/qedf/drv_fcoe_fw_funcs.c m_st_ctx->rsp_buf_addr.hi = val; val 71 drivers/scsi/qedf/drv_fcoe_fw_funcs.c val = cpu_to_le32(sense_data_buffer_phys_addr.lo); val 72 drivers/scsi/qedf/drv_fcoe_fw_funcs.c m_st_ctx->rsp_buf_addr.lo = val; val 124 drivers/scsi/qedf/drv_fcoe_fw_funcs.c u32 val; val 154 drivers/scsi/qedf/drv_fcoe_fw_funcs.c val = cpu_to_le32(task_params->cq_rss_number); val 155 drivers/scsi/qedf/drv_fcoe_fw_funcs.c t_st_ctx->read_only.glbl_q_num = val; val 23 drivers/scsi/qedf/drv_scsi_fw_funcs.c u32 val; val 25 drivers/scsi/qedf/drv_scsi_fw_funcs.c val = cpu_to_le32(sgl_task_params->sgl_phys_addr.lo); val 26 drivers/scsi/qedf/drv_scsi_fw_funcs.c ctx_sgl_params->sgl_addr.lo = val; val 27 drivers/scsi/qedf/drv_scsi_fw_funcs.c val = cpu_to_le32(sgl_task_params->sgl_phys_addr.hi); val 28 drivers/scsi/qedf/drv_scsi_fw_funcs.c ctx_sgl_params->sgl_addr.hi = val; val 29 drivers/scsi/qedf/drv_scsi_fw_funcs.c val = cpu_to_le32(sgl_task_params->total_buffer_size); val 30 drivers/scsi/qedf/drv_scsi_fw_funcs.c ctx_sgl_params->sgl_total_length = val; val 34 drivers/scsi/qedf/drv_scsi_fw_funcs.c val = cpu_to_le32(sgl_task_params->sgl[sge_index].sge_addr.lo); val 35 drivers/scsi/qedf/drv_scsi_fw_funcs.c ctx_data_desc->sge[sge_index].sge_addr.lo = val; val 36 drivers/scsi/qedf/drv_scsi_fw_funcs.c val = cpu_to_le32(sgl_task_params->sgl[sge_index].sge_addr.hi); val 37 drivers/scsi/qedf/drv_scsi_fw_funcs.c ctx_data_desc->sge[sge_index].sge_addr.hi = val; val 38 drivers/scsi/qedf/drv_scsi_fw_funcs.c val = cpu_to_le32(sgl_task_params->sgl[sge_index].sge_len); val 39 drivers/scsi/qedf/drv_scsi_fw_funcs.c ctx_data_desc->sge[sge_index].sge_len = val; val 29 drivers/scsi/qedf/qedf.h #define U64_HI(val) ((u32)(((u64)(val)) >> 32)) val 30 drivers/scsi/qedf/qedf.h #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff)) val 158 drivers/scsi/qedf/qedf_debugfs.c uint32_t val; val 171 drivers/scsi/qedf/qedf_debugfs.c rval = kstrtouint(kern_buf, 10, &val); val 176 drivers/scsi/qedf/qedf_debugfs.c if (val == 1) val 179 drivers/scsi/qedf/qedf_debugfs.c qedf_debug = val; val 181 drivers/scsi/qedf/qedf_debugfs.c QEDF_INFO(qedf_dbg, QEDF_LOG_DEBUGFS, "Setting debug=0x%x.\n", val); val 380 drivers/scsi/qedi/qedi.h #define QEDI_U64_HI(val) ((u32)(((u64)(val)) >> 32)) val 381 drivers/scsi/qedi/qedi.h #define QEDI_U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff)) val 28 drivers/scsi/qedi/qedi_fw_api.c u32 val; val 34 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(sgl_task_params->sgl_phys_addr.lo); val 35 drivers/scsi/qedi/qedi_fw_api.c ctx_sgl_params->sgl_addr.lo = val; val 36 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(sgl_task_params->sgl_phys_addr.hi); val 37 drivers/scsi/qedi/qedi_fw_api.c ctx_sgl_params->sgl_addr.hi = val; val 38 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(sgl_task_params->total_buffer_size); val 39 drivers/scsi/qedi/qedi_fw_api.c ctx_sgl_params->sgl_total_length = val; val 43 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(sgl_task_params->sgl[sge_index].sge_addr.lo); val 44 drivers/scsi/qedi/qedi_fw_api.c ctx_data_desc->sge[sge_index].sge_addr.lo = val; val 45 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(sgl_task_params->sgl[sge_index].sge_addr.hi); val 46 drivers/scsi/qedi/qedi_fw_api.c ctx_data_desc->sge[sge_index].sge_addr.hi = val; val 47 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(sgl_task_params->sgl[sge_index].sge_len); val 48 drivers/scsi/qedi/qedi_fw_api.c ctx_data_desc->sge[sge_index].sge_len = val; val 206 drivers/scsi/qedi/qedi_fw_api.c u32 val; val 218 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(pdu_header->data[index]); val 219 drivers/scsi/qedi/qedi_fw_api.c context->ystorm_st_context.pdu_hdr.data.data[index] = val; val 239 drivers/scsi/qedi/qedi_fw_api.c u32 val; val 247 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(cmd->extended_cdb_sge.sge_addr.lo); val 248 drivers/scsi/qedi/qedi_fw_api.c ctx_pdu_hdr->ext_cdb_cmd.cdb_sge.sge_addr.lo = val; val 249 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(cmd->extended_cdb_sge.sge_addr.hi); val 250 drivers/scsi/qedi/qedi_fw_api.c ctx_pdu_hdr->ext_cdb_cmd.cdb_sge.sge_addr.hi = val; val 251 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(cmd->extended_cdb_sge.sge_len); val 252 drivers/scsi/qedi/qedi_fw_api.c ctx_pdu_hdr->ext_cdb_cmd.cdb_sge.sge_len = val; val 261 drivers/scsi/qedi/qedi_fw_api.c u32 val; val 265 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(expected_data_transfer_len); val 266 drivers/scsi/qedi/qedi_fw_api.c ustorm_st_cxt->exp_data_transfer_len = val; val 281 drivers/scsi/qedi/qedi_fw_api.c u32 max_unsolicited_data = 0, val; val 306 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(exp_data_transfer_len); val 307 drivers/scsi/qedi/qedi_fw_api.c context->ustorm_ag_context.exp_data_acked = val; val 316 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(task_size); val 317 drivers/scsi/qedi/qedi_fw_api.c context->ustorm_ag_context.exp_cont_len = val; val 330 drivers/scsi/qedi/qedi_fw_api.c u32 val; val 340 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(dif_task_params->initial_ref_tag); val 341 drivers/scsi/qedi/qedi_fw_api.c rdif_context->initial_ref_tag = val; val 430 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(dif_task_params->initial_ref_tag); val 431 drivers/scsi/qedi/qedi_fw_api.c tdif_context->initial_ref_tag = val; val 492 drivers/scsi/qedi/qedi_fw_api.c u32 task_size, val; val 507 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(task_size + val 509 drivers/scsi/qedi/qedi_fw_api.c cxt->ystorm_st_context.pdu_hdr.r2t.desired_data_trns_len = val; val 513 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(task_size); val 515 drivers/scsi/qedi/qedi_fw_api.c val; val 518 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(cmd_params->sense_data_buffer_phys_addr.lo); val 519 drivers/scsi/qedi/qedi_fw_api.c cxt->mstorm_st_context.sense_db.lo = val; val 521 drivers/scsi/qedi/qedi_fw_api.c val = cpu_to_le32(cmd_params->sense_data_buffer_phys_addr.hi); val 522 drivers/scsi/qedi/qedi_fw_api.c cxt->mstorm_st_context.sense_db.hi = val; val 4026 drivers/scsi/qla1280.c int val; val 4050 drivers/scsi/qla1280.c unsigned long val; val 4058 drivers/scsi/qla1280.c val = 0x10000; val 4061 drivers/scsi/qla1280.c val = 0; val 4064 drivers/scsi/qla1280.c val = simple_strtoul(ptr, &ptr, 0); val 4068 drivers/scsi/qla1280.c if (!val) val 4072 drivers/scsi/qla1280.c if (!val) val 4074 drivers/scsi/qla1280.c else if (val != 0x10000) val 4075 drivers/scsi/qla1280.c driver_setup.sync_mask = val; val 4078 drivers/scsi/qla1280.c if (!val) val 4080 drivers/scsi/qla1280.c else if (val != 0x10000) val 4081 drivers/scsi/qla1280.c driver_setup.wide_mask = val; val 4084 drivers/scsi/qla1280.c if (!val) val 4086 drivers/scsi/qla1280.c else if (val != 0x10000) val 4087 drivers/scsi/qla1280.c driver_setup.ppr_mask = val; val 4090 drivers/scsi/qla1280.c qla1280_verbose = val; val 4120 drivers/scsi/qla1280.c ret = setup_token[i].val; val 339 drivers/scsi/qla2xxx/qla_attr.c int val, valid; val 348 drivers/scsi/qla2xxx/qla_attr.c if (sscanf(buf, "%d:%x:%x", &val, &start, &size) < 1) val 360 drivers/scsi/qla2xxx/qla_attr.c switch (val) { val 1196 drivers/scsi/qla2xxx/qla_attr.c int val = 0; val 1202 drivers/scsi/qla2xxx/qla_attr.c if (sscanf(buf, "%d", &val) != 1) val 1205 drivers/scsi/qla2xxx/qla_attr.c if (val) val 1232 drivers/scsi/qla2xxx/qla_attr.c int val = 0; val 1235 drivers/scsi/qla2xxx/qla_attr.c if (sscanf(buf, "%d", &val) != 1) val 1237 drivers/scsi/qla2xxx/qla_attr.c if (val > 25500 || val < 100) val 1240 drivers/scsi/qla2xxx/qla_attr.c zio_timer = (uint16_t)(val / 100); val 1261 drivers/scsi/qla2xxx/qla_attr.c int val = 0; val 1265 drivers/scsi/qla2xxx/qla_attr.c if (sscanf(buf, "%d", &val) != 1) val 1267 drivers/scsi/qla2xxx/qla_attr.c if (val < 0 || val > 256) val 1270 drivers/scsi/qla2xxx/qla_attr.c atomic_set(&vha->hw->zio_threshold, val); val 1294 drivers/scsi/qla2xxx/qla_attr.c int val = 0; val 1300 drivers/scsi/qla2xxx/qla_attr.c if (sscanf(buf, "%d", &val) != 1) val 1311 drivers/scsi/qla2xxx/qla_attr.c if (val) val 1634 drivers/scsi/qla2xxx/qla_attr.c int val = 0; val 1639 drivers/scsi/qla2xxx/qla_attr.c if (sscanf(buf, "%d", &val) != 1) val 1642 drivers/scsi/qla2xxx/qla_attr.c vha->hw->allow_cna_fw_dump = val != 0; val 2157 drivers/scsi/qla2xxx/qla_attr.c int val = 0; val 2159 drivers/scsi/qla2xxx/qla_attr.c if (sscanf(buf, "%d", &val) != 1) val 2162 drivers/scsi/qla2xxx/qla_attr.c if (val > FW_MAX_EXCHANGES_CNT) val 2163 drivers/scsi/qla2xxx/qla_attr.c val = FW_MAX_EXCHANGES_CNT; val 2164 drivers/scsi/qla2xxx/qla_attr.c else if (val < 0) val 2165 drivers/scsi/qla2xxx/qla_attr.c val = 0; val 2167 drivers/scsi/qla2xxx/qla_attr.c vha->u_ql2xexchoffld = val; val 2194 drivers/scsi/qla2xxx/qla_attr.c int val = 0; val 2196 drivers/scsi/qla2xxx/qla_attr.c if (sscanf(buf, "%d", &val) != 1) val 2199 drivers/scsi/qla2xxx/qla_attr.c if (val > FW_MAX_EXCHANGES_CNT) val 2200 drivers/scsi/qla2xxx/qla_attr.c val = FW_MAX_EXCHANGES_CNT; val 2201 drivers/scsi/qla2xxx/qla_attr.c else if (val < 0) val 2202 drivers/scsi/qla2xxx/qla_attr.c val = 0; val 2204 drivers/scsi/qla2xxx/qla_attr.c vha->u_ql2xiniexchg = val; val 2085 drivers/scsi/qla2xxx/qla_bsg.c rval = qla2x00_write_serdes_word(vha, sr.addr, sr.val); val 2089 drivers/scsi/qla2xxx/qla_bsg.c rval = qla2x00_read_serdes_word(vha, sr.addr, &sr.val); val 2127 drivers/scsi/qla2xxx/qla_bsg.c rval = qla8044_write_serdes_word(vha, sr.addr, sr.val); val 2131 drivers/scsi/qla2xxx/qla_bsg.c rval = qla8044_read_serdes_word(vha, sr.addr, &sr.val); val 233 drivers/scsi/qla2xxx/qla_bsg.h uint16_t val; val 239 drivers/scsi/qla2xxx/qla_bsg.h uint32_t val; val 875 drivers/scsi/qla2xxx/qla_gbl.h extern void qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val); val 4458 drivers/scsi/qla2xxx/qla_init.c const u8 *val; val 4461 drivers/scsi/qla2xxx/qla_init.c val = of_get_property(dp, "port-wwn", &len); val 4462 drivers/scsi/qla2xxx/qla_init.c if (val && len >= WWN_SIZE) val 4463 drivers/scsi/qla2xxx/qla_init.c memcpy(nv->port_name, val, WWN_SIZE); val 4465 drivers/scsi/qla2xxx/qla_init.c val = of_get_property(dp, "node-wwn", &len); val 4466 drivers/scsi/qla2xxx/qla_init.c if (val && len >= WWN_SIZE) val 4467 drivers/scsi/qla2xxx/qla_init.c memcpy(nv->node_name, val, WWN_SIZE); val 7063 drivers/scsi/qla2xxx/qla_init.c const u8 *val; val 7066 drivers/scsi/qla2xxx/qla_init.c val = of_get_property(dp, "port-wwn", &len); val 7067 drivers/scsi/qla2xxx/qla_init.c if (val && len >= WWN_SIZE) val 7068 drivers/scsi/qla2xxx/qla_init.c memcpy(nv->port_name, val, WWN_SIZE); val 7070 drivers/scsi/qla2xxx/qla_init.c val = of_get_property(dp, "node-wwn", &len); val 7071 drivers/scsi/qla2xxx/qla_init.c if (val && len >= WWN_SIZE) val 7072 drivers/scsi/qla2xxx/qla_init.c memcpy(nv->node_name, val, WWN_SIZE); val 5330 drivers/scsi/qla2xxx/qla_mbx.c uint16_t val; val 5346 drivers/scsi/qla2xxx/qla_mbx.c val = ha->set_data_rate; val 5352 drivers/scsi/qla2xxx/qla_mbx.c val = ha->set_data_rate = PORT_SPEED_AUTO; val 5358 drivers/scsi/qla2xxx/qla_mbx.c mcp->mb[2] = val; val 376 drivers/scsi/qla2xxx/qla_mr.h #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\ val 377 drivers/scsi/qla2xxx/qla_mr.h WRT_REG_DWORD((ha)->cregbase + off, val) val 382 drivers/scsi/qla2xxx/qla_mr.h #define QLAFX00_HBA_RST_REG(ha, val)\ val 383 drivers/scsi/qla2xxx/qla_mr.h WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_RST_REG, val) val 401 drivers/scsi/qla2xxx/qla_mr.h #define QLAFX00_WR_REG(ha, off, val) \ val 402 drivers/scsi/qla2xxx/qla_mr.h WRT_REG_DWORD((ha)->cregbase + off, val) val 992 drivers/scsi/qla2xxx/qla_nx.c qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) val 1003 drivers/scsi/qla2xxx/qla_nx.c *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); val 1012 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; val 1018 drivers/scsi/qla2xxx/qla_nx.c ret = qla82xx_read_status_reg(ha, &val); val 1019 drivers/scsi/qla2xxx/qla_nx.c done = val & 1; val 1035 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; val 1043 drivers/scsi/qla2xxx/qla_nx.c if (qla82xx_read_status_reg(ha, &val) != 0) val 1045 drivers/scsi/qla2xxx/qla_nx.c if ((val & 2) != 2) val 1051 drivers/scsi/qla2xxx/qla_nx.c qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) val 1057 drivers/scsi/qla2xxx/qla_nx.c qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); val 1144 drivers/scsi/qla2xxx/qla_nx.c int addr, val; val 1181 drivers/scsi/qla2xxx/qla_nx.c val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); val 1182 drivers/scsi/qla2xxx/qla_nx.c qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); val 1247 drivers/scsi/qla2xxx/qla_nx.c if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || val 1254 drivers/scsi/qla2xxx/qla_nx.c buf[i].data = val; val 1475 drivers/scsi/qla2xxx/qla_nx.c uint64_t off8, val, mem_crb, word[2] = {0, 0}; val 1534 drivers/scsi/qla2xxx/qla_nx.c val = word[0]; val 1536 drivers/scsi/qla2xxx/qla_nx.c val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | val 1542 drivers/scsi/qla2xxx/qla_nx.c *(uint8_t *)data = val; val 1545 drivers/scsi/qla2xxx/qla_nx.c *(uint16_t *)data = val; val 1548 drivers/scsi/qla2xxx/qla_nx.c *(uint32_t *)data = val; val 1551 drivers/scsi/qla2xxx/qla_nx.c *(uint64_t *)data = val; val 1648 drivers/scsi/qla2xxx/qla_nx.c unsigned long val = 0; val 1653 drivers/scsi/qla2xxx/qla_nx.c val = 0; val 1657 drivers/scsi/qla2xxx/qla_nx.c val = control + QLA82XX_MSIX_TBL_SPACE; val 1660 drivers/scsi/qla2xxx/qla_nx.c return val; val 1885 drivers/scsi/qla2xxx/qla_nx.c __le32 val; val 1898 drivers/scsi/qla2xxx/qla_nx.c val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); val 1899 drivers/scsi/qla2xxx/qla_nx.c if ((__force u32)val != QLA82XX_BDINFO_MAGIC) val 1913 drivers/scsi/qla2xxx/qla_nx.c u32 val = 0; val 1919 drivers/scsi/qla2xxx/qla_nx.c val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); val 1922 drivers/scsi/qla2xxx/qla_nx.c switch (val) { val 1933 drivers/scsi/qla2xxx/qla_nx.c val, retries); val 1940 drivers/scsi/qla2xxx/qla_nx.c "Cmd Peg initialization failed: 0x%x.\n", val); val 1942 drivers/scsi/qla2xxx/qla_nx.c val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); val 1952 drivers/scsi/qla2xxx/qla_nx.c u32 val = 0; val 1958 drivers/scsi/qla2xxx/qla_nx.c val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); val 1961 drivers/scsi/qla2xxx/qla_nx.c switch (val) { val 1972 drivers/scsi/qla2xxx/qla_nx.c val, retries); val 1979 drivers/scsi/qla2xxx/qla_nx.c "Rcv Peg initialization failed: 0x%x.\n", val); val 2557 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; val 2562 drivers/scsi/qla2xxx/qla_nx.c if (qla82xx_rom_fast_read(ha, faddr, &val)) { val 2567 drivers/scsi/qla2xxx/qla_nx.c dwptr[i] = cpu_to_le32(val); val 2577 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; val 2587 drivers/scsi/qla2xxx/qla_nx.c ret = qla82xx_read_status_reg(ha, &val); val 2591 drivers/scsi/qla2xxx/qla_nx.c val &= ~(BLOCK_PROTECT_BITS << 2); val 2592 drivers/scsi/qla2xxx/qla_nx.c ret = qla82xx_write_status_reg(ha, val); val 2594 drivers/scsi/qla2xxx/qla_nx.c val |= (BLOCK_PROTECT_BITS << 2); val 2595 drivers/scsi/qla2xxx/qla_nx.c qla82xx_write_status_reg(ha, val); val 2611 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; val 2621 drivers/scsi/qla2xxx/qla_nx.c ret = qla82xx_read_status_reg(ha, &val); val 2625 drivers/scsi/qla2xxx/qla_nx.c val |= (BLOCK_PROTECT_BITS << 2); val 2627 drivers/scsi/qla2xxx/qla_nx.c ret = qla82xx_write_status_reg(ha, val); val 1173 drivers/scsi/qla2xxx/qla_nx.h #define qla82xx_encode_temp(val, state) (((val) << 16) | (state)) val 41 drivers/scsi/qla2xxx/qla_nx2.c qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val) val 43 drivers/scsi/qla2xxx/qla_nx2.c writel(val, (void __iomem *)((ha)->nx_pcibase + addr)); val 72 drivers/scsi/qla2xxx/qla_nx2.c uint32_t val; val 77 drivers/scsi/qla2xxx/qla_nx2.c val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum)); val 79 drivers/scsi/qla2xxx/qla_nx2.c if (val != addr) { val 83 drivers/scsi/qla2xxx/qla_nx2.c __func__, addr, val); val 1319 drivers/scsi/qla2xxx/qla_nx2.c uint32_t val, ret_val = QLA_FUNCTION_FAILED; val 1324 drivers/scsi/qla2xxx/qla_nx2.c val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE); val 1325 drivers/scsi/qla2xxx/qla_nx2.c if (val == PHAN_INITIALIZE_COMPLETE) { val 1328 drivers/scsi/qla2xxx/qla_nx2.c "complete! state=0x%x\n", __func__, val); val 840 drivers/scsi/qla2xxx/tcm_qla2xxx.c unsigned long val; \ val 843 drivers/scsi/qla2xxx/tcm_qla2xxx.c ret = kstrtoul(page, 0, &val); \ val 850 drivers/scsi/qla2xxx/tcm_qla2xxx.c if ((val != 0) && (val != 1)) { \ val 851 drivers/scsi/qla2xxx/tcm_qla2xxx.c pr_err("Illegal boolean value %lu\n", val); \ val 855 drivers/scsi/qla2xxx/tcm_qla2xxx.c a->name = val; \ val 946 drivers/scsi/qla2xxx/tcm_qla2xxx.c unsigned long val; val 947 drivers/scsi/qla2xxx/tcm_qla2xxx.c int ret = kstrtoul(page, 0, &val); val 953 drivers/scsi/qla2xxx/tcm_qla2xxx.c if (val != 0 && val != 1 && val != 3) { val 954 drivers/scsi/qla2xxx/tcm_qla2xxx.c pr_err("Invalid qla2xxx fabric_prot_type: %lu\n", val); val 957 drivers/scsi/qla2xxx/tcm_qla2xxx.c tpg->tpg_attrib.fabric_prot_type = val; val 21 drivers/scsi/qla4xxx/ql4_83xx.c void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val) val 23 drivers/scsi/qla4xxx/ql4_83xx.c writel(val, (void __iomem *)(ha->nx_pcibase + addr)); val 28 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t val; val 32 drivers/scsi/qla4xxx/ql4_83xx.c val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); val 33 drivers/scsi/qla4xxx/ql4_83xx.c if (val != addr) { val 35 drivers/scsi/qla4xxx/ql4_83xx.c __func__, addr, val); val 681 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t val, ret_val = QLA_ERROR; val 685 drivers/scsi/qla4xxx/ql4_83xx.c val = qla4_83xx_rd_reg(ha, QLA83XX_CMDPEG_STATE); val 686 drivers/scsi/qla4xxx/ql4_83xx.c if (val == PHAN_INITIALIZE_COMPLETE) { val 689 drivers/scsi/qla4xxx/ql4_83xx.c __func__, val)); val 1408 drivers/scsi/qla4xxx/ql4_83xx.c u32 val = 0, val1 = 0; val 1411 drivers/scsi/qla4xxx/ql4_83xx.c status = qla4_83xx_rd_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL, &val); val 1412 drivers/scsi/qla4xxx/ql4_83xx.c DEBUG2(ql4_printk(KERN_INFO, ha, "SRE-Shim Ctrl:0x%x\n", val)); val 1419 drivers/scsi/qla4xxx/ql4_83xx.c QLA83XX_PORT0_RXB_PAUSE_THRS + (i * 0x4), &val); val 1420 drivers/scsi/qla4xxx/ql4_83xx.c DEBUG2(pr_info("0x%x ", val)); val 1430 drivers/scsi/qla4xxx/ql4_83xx.c QLA83XX_PORT1_RXB_PAUSE_THRS + (i * 0x4), &val); val 1431 drivers/scsi/qla4xxx/ql4_83xx.c DEBUG2(pr_info("0x%x ", val)); val 1441 drivers/scsi/qla4xxx/ql4_83xx.c QLA83XX_PORT0_RXB_TC_MAX_CELL + (i * 0x4), &val); val 1442 drivers/scsi/qla4xxx/ql4_83xx.c DEBUG2(pr_info("0x%x ", val)); val 1452 drivers/scsi/qla4xxx/ql4_83xx.c QLA83XX_PORT1_RXB_TC_MAX_CELL + (i * 0x4), &val); val 1453 drivers/scsi/qla4xxx/ql4_83xx.c DEBUG2(pr_info("0x%x ", val)); val 1464 drivers/scsi/qla4xxx/ql4_83xx.c &val); val 1465 drivers/scsi/qla4xxx/ql4_83xx.c val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ val 1467 drivers/scsi/qla4xxx/ql4_83xx.c (val | (i << 29))); val 1470 drivers/scsi/qla4xxx/ql4_83xx.c &val); val 1471 drivers/scsi/qla4xxx/ql4_83xx.c DEBUG2(pr_info("0x%x ", val)); val 1482 drivers/scsi/qla4xxx/ql4_83xx.c &val); val 1483 drivers/scsi/qla4xxx/ql4_83xx.c val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ val 1485 drivers/scsi/qla4xxx/ql4_83xx.c (val | (i << 29))); val 1488 drivers/scsi/qla4xxx/ql4_83xx.c &val); val 1489 drivers/scsi/qla4xxx/ql4_83xx.c DEBUG2(pr_info("0x%x ", val)); val 1495 drivers/scsi/qla4xxx/ql4_83xx.c &val); val 1501 drivers/scsi/qla4xxx/ql4_83xx.c val, val1)); val 200 drivers/scsi/qla4xxx/ql4_fw.h static inline uint32_t set_rmask(uint32_t val) val 202 drivers/scsi/qla4xxx/ql4_fw.h return (val & 0xffff) | (val << 16); val 206 drivers/scsi/qla4xxx/ql4_fw.h static inline uint32_t clr_rmask(uint32_t val) val 208 drivers/scsi/qla4xxx/ql4_fw.h return 0 | (val << 16); val 232 drivers/scsi/qla4xxx/ql4_glbl.h void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val); val 152 drivers/scsi/qla4xxx/ql4_nvram.c u16 val = 0; val 155 drivers/scsi/qla4xxx/ql4_nvram.c eeprom_readword(offset, &val, ha); val 156 drivers/scsi/qla4xxx/ql4_nvram.c return val; val 161 drivers/scsi/qla4xxx/ql4_nvram.c u16 val = 0; val 170 drivers/scsi/qla4xxx/ql4_nvram.c val = le16_to_cpu(rd_nvram_word(ha, index)); val 173 drivers/scsi/qla4xxx/ql4_nvram.c rval = (u8)((val & 0xff00) >> 8); val 175 drivers/scsi/qla4xxx/ql4_nvram.c rval = (u8)((val & 0x00ff)); val 984 drivers/scsi/qla4xxx/ql4_nx.c int addr, val; val 1020 drivers/scsi/qla4xxx/ql4_nx.c val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); val 1021 drivers/scsi/qla4xxx/ql4_nx.c qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); val 1088 drivers/scsi/qla4xxx/ql4_nx.c if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || val 1096 drivers/scsi/qla4xxx/ql4_nx.c buf[i].data = val; val 1372 drivers/scsi/qla4xxx/ql4_nx.c uint64_t off8, val, mem_crb, word[2] = {0, 0}; val 1433 drivers/scsi/qla4xxx/ql4_nx.c val = word[0]; val 1435 drivers/scsi/qla4xxx/ql4_nx.c val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | val 1441 drivers/scsi/qla4xxx/ql4_nx.c *(uint8_t *)data = val; val 1444 drivers/scsi/qla4xxx/ql4_nx.c *(uint16_t *)data = val; val 1447 drivers/scsi/qla4xxx/ql4_nx.c *(uint32_t *)data = val; val 1450 drivers/scsi/qla4xxx/ql4_nx.c *(uint64_t *)data = val; val 1564 drivers/scsi/qla4xxx/ql4_nx.c u32 val = 0; val 1569 drivers/scsi/qla4xxx/ql4_nx.c val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE); val 1570 drivers/scsi/qla4xxx/ql4_nx.c if ((val == PHAN_INITIALIZE_COMPLETE) || val 1571 drivers/scsi/qla4xxx/ql4_nx.c (val == PHAN_INITIALIZE_ACK)) val 3664 drivers/scsi/qla4xxx/ql4_nx.c uint32_t val; val 3678 drivers/scsi/qla4xxx/ql4_nx.c if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) { val 3683 drivers/scsi/qla4xxx/ql4_nx.c dwptr[i] = __constant_cpu_to_le32(val); val 33 drivers/scsi/qla4xxx/ql4_nx.h #define qla82xx_encode_temp(val, state) (((val) << 16) | (state)) val 5890 drivers/scsi/qla4xxx/ql4_os.c uint8_t val; val 5915 drivers/scsi/qla4xxx/ql4_os.c val = rd_nvram_byte(ha, addr); val 5916 drivers/scsi/qla4xxx/ql4_os.c if (!(val & 0x07)) { val 5918 drivers/scsi/qla4xxx/ql4_os.c "options : 0x%x\n", __func__, val)); val 5924 drivers/scsi/qla4xxx/ql4_os.c val = rd_nvram_byte(ha, pri_addr); val 5925 drivers/scsi/qla4xxx/ql4_os.c if (val & BIT_7) val 5926 drivers/scsi/qla4xxx/ql4_os.c ddb_index[0] = (val & 0x7f); val 5929 drivers/scsi/qla4xxx/ql4_os.c val = rd_nvram_byte(ha, sec_addr); val 5930 drivers/scsi/qla4xxx/ql4_os.c if (val & BIT_7) val 5931 drivers/scsi/qla4xxx/ql4_os.c ddb_index[1] = (val & 0x7f); val 153 drivers/scsi/qlogicpti.c u16 val; val 162 drivers/scsi/qlogicpti.c val = (SBUS_CFG1_BENAB | SBUS_CFG1_B64); val 166 drivers/scsi/qlogicpti.c val = (SBUS_CFG1_BENAB | SBUS_CFG1_B32); val 168 drivers/scsi/qlogicpti.c val = (SBUS_CFG1_BENAB | SBUS_CFG1_B16); val 170 drivers/scsi/qlogicpti.c val = (SBUS_CFG1_BENAB | SBUS_CFG1_B8); val 172 drivers/scsi/qlogicpti.c val = 0; /* No sbus bursts for you... */ val 174 drivers/scsi/qlogicpti.c sbus_writew(val, qpti->qregs + SBUS_CFG1); val 369 drivers/scsi/scsi_devinfo.c unsigned long long val; val 370 drivers/scsi/scsi_devinfo.c int ret = kstrtoull(strflags, 0, &val); val 376 drivers/scsi/scsi_devinfo.c flags = (__force blist_flags_t)val; val 2334 drivers/scsi/scsi_error.c int error = 0, rtn, val; val 2339 drivers/scsi/scsi_error.c error = get_user(val, arg); val 2369 drivers/scsi/scsi_error.c switch (val & ~SG_SCSI_RESET_NO_ESCALATE) { val 2375 drivers/scsi/scsi_error.c if (rtn == SUCCESS || (val & SG_SCSI_RESET_NO_ESCALATE)) val 2380 drivers/scsi/scsi_error.c if (rtn == SUCCESS || (val & SG_SCSI_RESET_NO_ESCALATE)) val 2385 drivers/scsi/scsi_error.c if (rtn == SUCCESS || (val & SG_SCSI_RESET_NO_ESCALATE)) val 115 drivers/scsi/scsi_sysfs.c static int check_set(unsigned long long *val, char *src) val 120 drivers/scsi/scsi_sysfs.c *val = SCAN_WILD_CARD; val 125 drivers/scsi/scsi_sysfs.c *val = simple_strtoull(src, &last, 0); val 934 drivers/scsi/scsi_sysfs.c int val = test_bit(SDEV_EVT_##Cap_name, sdev->supported_events);\ val 935 drivers/scsi/scsi_sysfs.c return snprintf(buf, 20, "%d\n", val); \ val 944 drivers/scsi/scsi_sysfs.c int val = simple_strtoul(buf, NULL, 0); \ val 945 drivers/scsi/scsi_sysfs.c if (val == 0) \ val 947 drivers/scsi/scsi_sysfs.c else if (val == 1) \ val 711 drivers/scsi/scsi_transport_fc.c int val; \ val 720 drivers/scsi/scsi_transport_fc.c val = simple_strtoul(buf, &cp, 0); \ val 723 drivers/scsi/scsi_transport_fc.c i->f->set_rport_##field(rport, val); \ val 837 drivers/scsi/scsi_transport_fc.c static int fc_str_to_dev_loss(const char *buf, unsigned long *val) val 841 drivers/scsi/scsi_transport_fc.c *val = simple_strtoul(buf, &cp, 0); val 847 drivers/scsi/scsi_transport_fc.c if (*val > UINT_MAX) val 854 drivers/scsi/scsi_transport_fc.c unsigned long val) val 866 drivers/scsi/scsi_transport_fc.c if (val > UINT_MAX) val 874 drivers/scsi/scsi_transport_fc.c val > SCSI_DEVICE_BLOCK_MAX_TIMEOUT) val 877 drivers/scsi/scsi_transport_fc.c i->f->set_rport_dev_loss_tmo(rport, val); val 887 drivers/scsi/scsi_transport_fc.c unsigned long val; val 890 drivers/scsi/scsi_transport_fc.c rc = fc_str_to_dev_loss(buf, &val); val 894 drivers/scsi/scsi_transport_fc.c rc = fc_rport_set_dev_loss_tmo(rport, val); val 964 drivers/scsi/scsi_transport_fc.c int val; val 975 drivers/scsi/scsi_transport_fc.c val = simple_strtoul(buf, &cp, 0); val 976 drivers/scsi/scsi_transport_fc.c if ((*cp && (*cp != '\n')) || (val < 0)) val 982 drivers/scsi/scsi_transport_fc.c if ((val >= rport->dev_loss_tmo) || val 983 drivers/scsi/scsi_transport_fc.c (val > SCSI_DEVICE_BLOCK_MAX_TIMEOUT)) val 986 drivers/scsi/scsi_transport_fc.c rport->fast_io_fail_tmo = val; val 1079 drivers/scsi/scsi_transport_fc.c int val; \ val 1086 drivers/scsi/scsi_transport_fc.c val = simple_strtoul(buf, &cp, 0); \ val 1089 drivers/scsi/scsi_transport_fc.c i->f->set_vport_##field(vport, val); \ val 1146 drivers/scsi/scsi_transport_fc.c u32 val; \ val 1151 drivers/scsi/scsi_transport_fc.c val = simple_strtoul(buf, &cp, 0); \ val 1154 drivers/scsi/scsi_transport_fc.c vport->field = val; \ val 1346 drivers/scsi/scsi_transport_fc.c int val; \ val 1351 drivers/scsi/scsi_transport_fc.c val = simple_strtoul(buf, &cp, 0); \ val 1354 drivers/scsi/scsi_transport_fc.c i->f->set_host_##field(shost, val); \ val 1602 drivers/scsi/scsi_transport_fc.c enum fc_tgtid_binding_type val; val 1605 drivers/scsi/scsi_transport_fc.c if (get_fc_tgtid_bind_type_match(buf, &val)) val 1609 drivers/scsi/scsi_transport_fc.c if (val != fc_host_tgtid_bind_type(shost)) { val 1621 drivers/scsi/scsi_transport_fc.c fc_host_tgtid_bind_type(shost) = val; val 1657 drivers/scsi/scsi_transport_fc.c unsigned long val, flags; val 1660 drivers/scsi/scsi_transport_fc.c rc = fc_str_to_dev_loss(buf, &val); val 1664 drivers/scsi/scsi_transport_fc.c fc_host_dev_loss_tmo(shost) = val; val 1667 drivers/scsi/scsi_transport_fc.c fc_rport_set_dev_loss_tmo(rport, val); val 4063 drivers/scsi/scsi_transport_iscsi.c int val; \ val 4074 drivers/scsi/scsi_transport_iscsi.c val = simple_strtoul(buf, &cp, 0); \ val 4077 drivers/scsi/scsi_transport_iscsi.c session->field = val; \ val 1205 drivers/scsi/scsi_transport_sas.c int val; val 1207 drivers/scsi/scsi_transport_sas.c val = i->f->get_bay_identifier(rphy); val 1208 drivers/scsi/scsi_transport_sas.c if (val < 0) val 1209 drivers/scsi/scsi_transport_sas.c return val; val 1210 drivers/scsi/scsi_transport_sas.c return sprintf(buf, "%d\n", val); val 285 drivers/scsi/scsi_transport_spi.c int val; \ val 290 drivers/scsi/scsi_transport_spi.c val = simple_strtoul(buf, NULL, 0); \ val 291 drivers/scsi/scsi_transport_spi.c tp->field = val; \ val 317 drivers/scsi/scsi_transport_spi.c int val; \ val 324 drivers/scsi/scsi_transport_spi.c val = simple_strtoul(buf, NULL, 0); \ val 325 drivers/scsi/scsi_transport_spi.c i->f->set_##field(starget, val); \ val 335 drivers/scsi/scsi_transport_spi.c int val; \ val 344 drivers/scsi/scsi_transport_spi.c val = simple_strtoul(buf, NULL, 0); \ val 345 drivers/scsi/scsi_transport_spi.c if (val > tp->max_##field) \ val 346 drivers/scsi/scsi_transport_spi.c val = tp->max_##field; \ val 347 drivers/scsi/scsi_transport_spi.c i->f->set_##field(starget, val); \ val 320 drivers/scsi/sd.c unsigned int val; val 326 drivers/scsi/sd.c err = kstrtouint(buf, 10, &val); val 331 drivers/scsi/sd.c if (val <= T10_PI_TYPE3_PROTECTION) val 332 drivers/scsi/sd.c sdkp->protection_type = val; val 209 drivers/scsi/ses.c enum enclosure_component_setting val) val 224 drivers/scsi/ses.c switch (val) { val 269 drivers/scsi/ses.c enum enclosure_component_setting val) val 284 drivers/scsi/ses.c switch (val) { val 300 drivers/scsi/ses.c enum enclosure_component_setting val) val 315 drivers/scsi/ses.c switch (val) { val 356 drivers/scsi/ses.c int val) val 371 drivers/scsi/ses.c switch (val) { val 382 drivers/scsi/ses.c ecomp->power_status = val; val 871 drivers/scsi/sg.c int val; val 874 drivers/scsi/sg.c val = 0; val 876 drivers/scsi/sg.c if (val >= SG_MAX_QUEUE) val 878 drivers/scsi/sg.c rinfo[val].req_state = srp->done + 1; val 879 drivers/scsi/sg.c rinfo[val].problem = val 884 drivers/scsi/sg.c rinfo[val].duration = val 888 drivers/scsi/sg.c rinfo[val].duration = val 892 drivers/scsi/sg.c rinfo[val].orphan = srp->orphan; val 893 drivers/scsi/sg.c rinfo[val].sg_io_owned = srp->sg_io_owned; val 894 drivers/scsi/sg.c rinfo[val].pack_id = srp->header.pack_id; val 895 drivers/scsi/sg.c rinfo[val].usr_ptr = srp->header.usr_ptr; val 896 drivers/scsi/sg.c val++; val 905 drivers/scsi/sg.c int result, val, read_only; val 945 drivers/scsi/sg.c result = get_user(val, ip); val 948 drivers/scsi/sg.c if (val < 0) val 950 drivers/scsi/sg.c if (val >= mult_frac((s64)INT_MAX, USER_HZ, HZ)) val 951 drivers/scsi/sg.c val = min_t(s64, mult_frac((s64)INT_MAX, USER_HZ, HZ), val 953 drivers/scsi/sg.c sfp->timeout_user = val; val 954 drivers/scsi/sg.c sfp->timeout = mult_frac(val, HZ, USER_HZ); val 993 drivers/scsi/sg.c result = get_user(val, ip); val 996 drivers/scsi/sg.c sfp->force_packid = val ? 1 : 0; val 1015 drivers/scsi/sg.c val = 0; val 1018 drivers/scsi/sg.c ++val; val 1021 drivers/scsi/sg.c return put_user(val, ip); val 1025 drivers/scsi/sg.c result = get_user(val, ip); val 1028 drivers/scsi/sg.c if (val < 0) val 1030 drivers/scsi/sg.c val = min_t(int, val, val 1033 drivers/scsi/sg.c if (val != sfp->reserve.bufflen) { val 1041 drivers/scsi/sg.c sg_build_reserve(sfp, val); val 1046 drivers/scsi/sg.c val = min_t(int, sfp->reserve.bufflen, val 1048 drivers/scsi/sg.c return put_user(val, ip); val 1050 drivers/scsi/sg.c result = get_user(val, ip); val 1053 drivers/scsi/sg.c sfp->cmd_q = val ? 1 : 0; val 1058 drivers/scsi/sg.c result = get_user(val, ip); val 1061 drivers/scsi/sg.c sfp->keep_orphan = val; val 1066 drivers/scsi/sg.c result = get_user(val, ip); val 1069 drivers/scsi/sg.c if (val > SG_MAX_CDB_SIZE) val 1071 drivers/scsi/sg.c sfp->next_cmd_len = (val > 0) ? val : 0; val 1077 drivers/scsi/sg.c val = (sdp->device ? 1 : 0); val 1078 drivers/scsi/sg.c return put_user(val, ip); val 1107 drivers/scsi/sg.c result = get_user(val, ip); val 1110 drivers/scsi/sg.c sdp->sgdebug = (char) val; val 1606 drivers/scsi/sg.c int val; val 1611 drivers/scsi/sg.c val = atomic_inc_return(&sdp->detaching); val 1612 drivers/scsi/sg.c if (val > 1) val 57 drivers/scsi/sim710.c int val = (int)simple_strtoul(++next, NULL, 0); val 60 drivers/scsi/sim710.c slot = val; val 65 drivers/scsi/sim710.c printk(KERN_WARNING "sim710: Illegal slot %d for id %d\n", slot, val); val 67 drivers/scsi/sim710.c id_array[slot] = val; val 177 drivers/scsi/sim710.c __u8 val; val 181 drivers/scsi/sim710.c val = inb(io_addr + 0x4); val 182 drivers/scsi/sim710.c scsi_id = ffs(val) - 1; val 184 drivers/scsi/sim710.c if(scsi_id > 7 || (val & ~(1<<scsi_id)) != 0) { val 415 drivers/scsi/snic/snic.h const char *show_opcode_name(int val); val 125 drivers/scsi/snic/snic_debugfs.c unsigned long val; val 136 drivers/scsi/snic/snic_debugfs.c ret = kstrtoul(buf, 10, &val); val 140 drivers/scsi/snic/snic_debugfs.c snic->reset_stats = val; val 34 drivers/scsi/snic/vnic_dev.h static inline void writeq(u64 val, void __iomem *reg) val 36 drivers/scsi/snic/vnic_dev.h writel(lower_32_bits(val), reg); val 37 drivers/scsi/snic/vnic_dev.h writel(upper_32_bits(val), reg + 0x4UL); val 121 drivers/scsi/st.c int *val; val 4121 drivers/scsi/st.c if (parms[i].val) val 4122 drivers/scsi/st.c *parms[i].val = ints[i + 1]; val 4129 drivers/scsi/st.c if (parms[i].val) val 4130 drivers/scsi/st.c *parms[i].val = val 181 drivers/scsi/sun3_scsi.c static inline void sun3_udc_write(unsigned short val, unsigned char reg) val 185 drivers/scsi/sun3_scsi.c dregs->udc_data = val; val 54 drivers/scsi/sun3x_esp.c static void sun3x_esp_write8(struct esp *esp, u8 val, unsigned long reg) val 56 drivers/scsi/sun3x_esp.c writeb(val, esp->regs + (reg * 4UL)); val 73 drivers/scsi/sun3x_esp.c u32 val; val 75 drivers/scsi/sun3x_esp.c val = dma_read32(DMA_CSR); val 76 drivers/scsi/sun3x_esp.c dma_write32(val | DMA_RST_SCSI, DMA_CSR); val 77 drivers/scsi/sun3x_esp.c dma_write32(val & ~DMA_RST_SCSI, DMA_CSR); val 80 drivers/scsi/sun3x_esp.c val = dma_read32(DMA_CSR); val 81 drivers/scsi/sun3x_esp.c dma_write32(val | DMA_INT_ENAB, DMA_CSR); val 108 drivers/scsi/sun3x_esp.c u32 val; val 112 drivers/scsi/sun3x_esp.c while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) { val 121 drivers/scsi/sun3x_esp.c val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB); val 122 drivers/scsi/sun3x_esp.c val |= DMA_FIFO_INV; val 123 drivers/scsi/sun3x_esp.c dma_write32(val, DMA_CSR); val 124 drivers/scsi/sun3x_esp.c val &= ~DMA_FIFO_INV; val 125 drivers/scsi/sun3x_esp.c dma_write32(val, DMA_CSR); val 248 drivers/scsi/sun3x_esp.c u32 val; val 253 drivers/scsi/sun3x_esp.c val = dma_read32(DMA_CSR); val 254 drivers/scsi/sun3x_esp.c dma_write32(val & ~DMA_INT_ENAB, DMA_CSR); val 176 drivers/scsi/sun_esp.c u8 bursts, val; val 180 drivers/scsi/sun_esp.c val = of_getintprop_default(dma_dp, "burst-sizes", 0xff); val 181 drivers/scsi/sun_esp.c if (val != 0xff) val 182 drivers/scsi/sun_esp.c bursts &= val; val 184 drivers/scsi/sun_esp.c val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff); val 185 drivers/scsi/sun_esp.c if (val != 0xff) val 186 drivers/scsi/sun_esp.c bursts &= val; val 204 drivers/scsi/sun_esp.c static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg) val 206 drivers/scsi/sun_esp.c sbus_writeb(val, esp->regs + (reg * 4UL)); val 226 drivers/scsi/sun_esp.c u32 val; val 239 drivers/scsi/sun_esp.c val = dma_read32(DMA_CSR); val 240 drivers/scsi/sun_esp.c dma_write32(val | DMA_RST_SCSI, DMA_CSR); val 241 drivers/scsi/sun_esp.c dma_write32(val & ~DMA_RST_SCSI, DMA_CSR); val 283 drivers/scsi/sun_esp.c val = dma_read32(DMA_CSR); val 284 drivers/scsi/sun_esp.c dma_write32(val | DMA_3CLKS, DMA_CSR); val 289 drivers/scsi/sun_esp.c val = dma_read32(DMA_CSR); val 290 drivers/scsi/sun_esp.c val &= ~DMA_3CLKS; val 291 drivers/scsi/sun_esp.c val |= DMA_2CLKS; val 293 drivers/scsi/sun_esp.c val &= ~DMA_BRST_SZ; val 294 drivers/scsi/sun_esp.c val |= DMA_BRST32; val 296 drivers/scsi/sun_esp.c dma_write32(val, DMA_CSR); val 300 drivers/scsi/sun_esp.c val = dma_read32(DMA_CSR); val 301 drivers/scsi/sun_esp.c val |= DMA_ADD_ENABLE; val 302 drivers/scsi/sun_esp.c val &= ~DMA_BCNT_ENAB; val 304 drivers/scsi/sun_esp.c val |= DMA_ESC_BURST; val 306 drivers/scsi/sun_esp.c val &= ~(DMA_ESC_BURST); val 308 drivers/scsi/sun_esp.c dma_write32(val, DMA_CSR); val 316 drivers/scsi/sun_esp.c val = dma_read32(DMA_CSR); val 317 drivers/scsi/sun_esp.c dma_write32(val | DMA_INT_ENAB, DMA_CSR); val 364 drivers/scsi/sun_esp.c u32 val; val 368 drivers/scsi/sun_esp.c while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) { val 377 drivers/scsi/sun_esp.c val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB); val 378 drivers/scsi/sun_esp.c val |= DMA_FIFO_INV; val 379 drivers/scsi/sun_esp.c dma_write32(val, DMA_CSR); val 380 drivers/scsi/sun_esp.c val &= ~DMA_FIFO_INV; val 381 drivers/scsi/sun_esp.c dma_write32(val, DMA_CSR); val 498 drivers/scsi/sun_esp.c u32 val = dma_read32(DMA_CSR); val 500 drivers/scsi/sun_esp.c dma_write32(val & ~DMA_RST_SCSI, DMA_CSR); val 558 drivers/scsi/sun_esp.c u32 val; val 563 drivers/scsi/sun_esp.c val = dma_read32(DMA_CSR); val 564 drivers/scsi/sun_esp.c dma_write32(val & ~DMA_INT_ENAB, DMA_CSR); val 88 drivers/scsi/sym53c8xx_2/sym_glue.c int val = (int) simple_strtoul(p, &next_p, 0); val 89 drivers/scsi/sym53c8xx_2/sym_glue.c sym_driver_setup.excludes[xi++] = val; val 188 drivers/scsi/sym53c8xx_2/sym_hipd.h #define OUTB_OFF(np, o, val) iowrite8((val), np->s.ioaddr + (o)) val 189 drivers/scsi/sym53c8xx_2/sym_hipd.h #define OUTW_OFF(np, o, val) iowrite16((val), np->s.ioaddr + (o)) val 190 drivers/scsi/sym53c8xx_2/sym_hipd.h #define OUTL_OFF(np, o, val) iowrite32((val), np->s.ioaddr + (o)) val 106 drivers/scsi/ufs/ufs-hisi.h #define ufs_sys_ctrl_writel(host, val, reg) \ val 107 drivers/scsi/ufs/ufs-hisi.h writel((val), (host)->ufs_sys_ctrl + (reg)) val 392 drivers/scsi/ufs/ufs.h enum ufs_ref_clk_freq val; val 555 drivers/scsi/ufs/ufshcd.c u32 val, unsigned long interval_us, val 562 drivers/scsi/ufs/ufshcd.c val = val & mask; val 564 drivers/scsi/ufs/ufshcd.c while ((ufshcd_readl(hba, reg) & mask) != val) { val 570 drivers/scsi/ufs/ufshcd.c if ((ufshcd_readl(hba, reg) & mask) != val) val 4910 drivers/scsi/ufs/ufshcd.c u32 val; val 4915 drivers/scsi/ufs/ufshcd.c val = hba->ee_ctrl_mask & ~mask; val 4916 drivers/scsi/ufs/ufshcd.c val &= MASK_EE_STATUS; val 4918 drivers/scsi/ufs/ufshcd.c QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); val 4938 drivers/scsi/ufs/ufshcd.c u32 val; val 4943 drivers/scsi/ufs/ufshcd.c val = hba->ee_ctrl_mask | mask; val 4944 drivers/scsi/ufs/ufshcd.c val &= MASK_EE_STATUS; val 4946 drivers/scsi/ufs/ufshcd.c QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); val 6811 drivers/scsi/ufs/ufshcd.c return ufs_ref_clk_freqs[i].val; val 780 drivers/scsi/ufs/ufshcd.h #define ufshcd_writel(hba, val, reg) \ val 781 drivers/scsi/ufs/ufshcd.h writel((val), (hba)->mmio_base + (reg)) val 792 drivers/scsi/ufs/ufshcd.h static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) val 798 drivers/scsi/ufs/ufshcd.h tmp |= (val & mask); val 807 drivers/scsi/ufs/ufshcd.h u32 val, unsigned long interval_us, val 755 drivers/scsi/virtio_scsi.c #define virtscsi_config_set(vdev, fld, val) \ val 757 drivers/scsi/virtio_scsi.c typeof(((struct virtio_scsi_config *)0)->fld) __val = (val); \ val 210 drivers/scsi/vmw_pvscsi.c u32 offset, u32 val) val 212 drivers/scsi/vmw_pvscsi.c writel(val, adapter->mmioBase + offset); val 226 drivers/scsi/vmw_pvscsi.c u32 val) val 228 drivers/scsi/vmw_pvscsi.c pvscsi_reg_write(adapter, PVSCSI_REG_OFFSET_INTR_STATUS, val); val 1139 drivers/scsi/vmw_pvscsi.c u32 val; val 1146 drivers/scsi/vmw_pvscsi.c val = pvscsi_reg_read(adapter, PVSCSI_REG_OFFSET_COMMAND_STATUS); val 1147 drivers/scsi/vmw_pvscsi.c if (val == -1) { val 1181 drivers/scsi/vmw_pvscsi.c u32 val = pvscsi_read_intr_status(adapter); val 1183 drivers/scsi/vmw_pvscsi.c if (!(val & PVSCSI_INTR_ALL_SUPPORTED)) val 1185 drivers/scsi/vmw_pvscsi.c pvscsi_write_intr_status(devp, val); val 1806 drivers/scsi/wd33c93.c check_setup_args(char *key, int *flags, int *val, char *buf) val 1823 drivers/scsi/wd33c93.c *val = -1; val 1828 drivers/scsi/wd33c93.c *val = simple_strtoul(cp, NULL, 0); val 1933 drivers/scsi/wd33c93.c int val; val 1984 drivers/scsi/wd33c93.c if (check_setup_args("clock", &flags, &val, buf)) { val 1985 drivers/scsi/wd33c93.c hostdata->clock_freq = set_clk_freq(val, &val); val 1986 drivers/scsi/wd33c93.c calc_sx_table(val, hostdata->sx_table); val 1989 drivers/scsi/wd33c93.c if (check_setup_args("nosync", &flags, &val, buf)) val 1990 drivers/scsi/wd33c93.c hostdata->no_sync = val; val 1992 drivers/scsi/wd33c93.c if (check_setup_args("nodma", &flags, &val, buf)) val 1993 drivers/scsi/wd33c93.c hostdata->no_dma = (val == -1) ? 1 : val; val 1995 drivers/scsi/wd33c93.c if (check_setup_args("period", &flags, &val, buf)) val 1997 drivers/scsi/wd33c93.c hostdata->sx_table[round_period((unsigned int) val, val 2000 drivers/scsi/wd33c93.c if (check_setup_args("disconnect", &flags, &val, buf)) { val 2001 drivers/scsi/wd33c93.c if ((val >= DIS_NEVER) && (val <= DIS_ALWAYS)) val 2002 drivers/scsi/wd33c93.c hostdata->disconnect = val; val 2007 drivers/scsi/wd33c93.c if (check_setup_args("level2", &flags, &val, buf)) val 2008 drivers/scsi/wd33c93.c hostdata->level2 = val; val 2010 drivers/scsi/wd33c93.c if (check_setup_args("debug", &flags, &val, buf)) val 2011 drivers/scsi/wd33c93.c hostdata->args = val & DB_MASK; val 2013 drivers/scsi/wd33c93.c if (check_setup_args("burst", &flags, &val, buf)) val 2014 drivers/scsi/wd33c93.c hostdata->dma_mode = val ? CTRL_BURST:CTRL_DMA; val 2017 drivers/scsi/wd33c93.c && check_setup_args("fast", &flags, &val, buf)) val 2018 drivers/scsi/wd33c93.c hostdata->fast = !!val; val 2020 drivers/scsi/wd33c93.c if ((i = check_setup_args("next", &flags, &val, buf))) { val 2025 drivers/scsi/wd33c93.c if (check_setup_args("proc", &flags, &val, buf)) val 2026 drivers/scsi/wd33c93.c hostdata->proc = val; val 60 drivers/scsi/wd719x.c static inline void wd719x_writeb(struct wd719x *wd, u8 reg, u8 val) val 62 drivers/scsi/wd719x.c iowrite8(val, wd->base + reg); val 65 drivers/scsi/wd719x.c static inline void wd719x_writew(struct wd719x *wd, u8 reg, u16 val) val 67 drivers/scsi/wd719x.c iowrite16(val, wd->base + reg); val 70 drivers/scsi/wd719x.c static inline void wd719x_writel(struct wd719x *wd, u8 reg, u32 val) val 72 drivers/scsi/wd719x.c iowrite32(val, wd->base + reg); val 172 drivers/scsi/zorro_esp.c static void zorro_esp_write8(struct esp *esp, u8 val, unsigned long reg) val 174 drivers/scsi/zorro_esp.c writeb(val, esp->regs + (reg * 4UL)); val 179 drivers/sh/clk/cpg.c unsigned int val; val 181 drivers/sh/clk/cpg.c val = sh_clk_read(clk); val 182 drivers/sh/clk/cpg.c val |= CPG_CKSTP_BIT; val 190 drivers/sh/clk/cpg.c val |= clk->div_mask; val 192 drivers/sh/clk/cpg.c sh_clk_write(val, clk); val 211 drivers/sh/clk/cpg.c u32 val; val 224 drivers/sh/clk/cpg.c val = (sh_clk_read(clk) >> clk->src_shift); val 225 drivers/sh/clk/cpg.c val &= (1 << clk->src_width) - 1; val 227 drivers/sh/clk/cpg.c if (val >= clk->parent_num) { val 232 drivers/sh/clk/cpg.c clk_reparent(clk, clk->parent_table[val]); val 642 drivers/siox/siox-core.c u64 val; val 644 drivers/siox/siox-core.c ret = kstrtou64(buf, 0, &val); val 650 drivers/siox/siox-core.c smaster->poll_interval = nsecs_to_jiffies(val); val 294 drivers/slimbus/messaging.c int slim_read(struct slim_device *sdev, u32 addr, size_t count, u8 *val) val 298 drivers/slimbus/messaging.c slim_fill_msg(&msg, addr, count, val, NULL); val 337 drivers/slimbus/messaging.c int slim_write(struct slim_device *sdev, u32 addr, size_t count, u8 *val) val 341 drivers/slimbus/messaging.c slim_fill_msg(&msg, addr, count, NULL, val); val 18 drivers/soc/actions/owl-sps-helper.c u32 val; val 22 drivers/soc/actions/owl-sps-helper.c val = readl(base + OWL_SPS_PG_CTL); val 23 drivers/soc/actions/owl-sps-helper.c ack = val & ack_mask; val 28 drivers/soc/actions/owl-sps-helper.c val |= pwr_mask; val 30 drivers/soc/actions/owl-sps-helper.c val &= ~pwr_mask; val 32 drivers/soc/actions/owl-sps-helper.c writel(val, base + OWL_SPS_PG_CTL); val 35 drivers/soc/actions/owl-sps-helper.c val = readl(base + OWL_SPS_PG_CTL); val 36 drivers/soc/actions/owl-sps-helper.c if ((val & ack_mask) == (enable ? ack_mask : 0)) val 41 drivers/soc/amlogic/meson-canvas.c static void canvas_write(struct meson_canvas *canvas, u32 reg, u32 val) val 43 drivers/soc/amlogic/meson-canvas.c writel_relaxed(val, canvas->reg_base + reg); val 494 drivers/soc/amlogic/meson-clk-measure.c unsigned int val; val 517 drivers/soc/amlogic/meson-clk-measure.c val, !(val & MSR_BUSY), 10, 10000); val 527 drivers/soc/amlogic/meson-clk-measure.c regmap_read(priv->regmap, MSR_CLK_REG2, &val); val 531 drivers/soc/amlogic/meson-clk-measure.c if (val >= MSR_VAL_MASK) val 534 drivers/soc/amlogic/meson-clk-measure.c return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL, val 560 drivers/soc/amlogic/meson-clk-measure.c int val; val 562 drivers/soc/amlogic/meson-clk-measure.c val = meson_measure_best_id(clk_msr_id, &precision); val 563 drivers/soc/amlogic/meson-clk-measure.c if (val < 0) val 564 drivers/soc/amlogic/meson-clk-measure.c return val; val 566 drivers/soc/amlogic/meson-clk-measure.c seq_printf(s, "%d\t+/-%dHz\n", val, precision); val 576 drivers/soc/amlogic/meson-clk-measure.c int val, i; val 585 drivers/soc/amlogic/meson-clk-measure.c val = meson_measure_best_id(&msr_table[i], &precision); val 586 drivers/soc/amlogic/meson-clk-measure.c if (val < 0) val 587 drivers/soc/amlogic/meson-clk-measure.c return val; val 590 drivers/soc/amlogic/meson-clk-measure.c msr_table[i].name, val, precision); val 117 drivers/soc/aspeed/aspeed-lpc-snoop.c static void put_fifo_with_discard(struct aspeed_lpc_snoop_channel *chan, u8 val) val 123 drivers/soc/aspeed/aspeed-lpc-snoop.c kfifo_put(&chan->fifo, val); val 147 drivers/soc/aspeed/aspeed-lpc-snoop.c u8 val = (data & SNPWDR_CH0_MASK) >> SNPWDR_CH0_SHIFT; val 149 drivers/soc/aspeed/aspeed-lpc-snoop.c put_fifo_with_discard(&lpc_snoop->chan[0], val); val 152 drivers/soc/aspeed/aspeed-lpc-snoop.c u8 val = (data & SNPWDR_CH1_MASK) >> SNPWDR_CH1_SHIFT; val 154 drivers/soc/aspeed/aspeed-lpc-snoop.c put_fifo_with_discard(&lpc_snoop->chan[1], val); val 110 drivers/soc/bcm/bcm2835-power.c #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg)) val 130 drivers/soc/bcm/bcm2835-power.c #define ASB_WRITE(reg, val) writel(PM_PASSWORD | (val), power->asb + (reg)) val 44 drivers/soc/bcm/brcmstb/biuctrl.c static inline void cbc_writel(u32 val, int reg) val 51 drivers/soc/bcm/brcmstb/biuctrl.c writel(val, cpubiuctrl_base + offset); val 80 drivers/soc/bcm/brcmstb/pm/pm-mips.c #define AON_SAVE_SRAM(base, idx, val) \ val 81 drivers/soc/bcm/brcmstb/pm/pm-mips.c __raw_writel(val, base + (idx << 2)) val 52 drivers/soc/dove/pmu.c u32 val; val 55 drivers/soc/dove/pmu.c val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); val 56 drivers/soc/dove/pmu.c writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); val 57 drivers/soc/dove/pmu.c writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST); val 67 drivers/soc/dove/pmu.c u32 val = ~BIT(id); val 70 drivers/soc/dove/pmu.c val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST); val 71 drivers/soc/dove/pmu.c writel_relaxed(val, pmu->pmc_base + PMC_SW_RST); val 81 drivers/soc/dove/pmu.c u32 val = BIT(id); val 84 drivers/soc/dove/pmu.c val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST); val 85 drivers/soc/dove/pmu.c writel_relaxed(val, pmu->pmc_base + PMC_SW_RST); val 148 drivers/soc/dove/pmu.c unsigned int val; val 156 drivers/soc/dove/pmu.c val = ~pmu_dom->iso_mask; val 157 drivers/soc/dove/pmu.c val &= readl_relaxed(pmu_base + PMU_ISO); val 158 drivers/soc/dove/pmu.c writel_relaxed(val, pmu_base + PMU_ISO); val 163 drivers/soc/dove/pmu.c val = ~pmu_dom->rst_mask; val 164 drivers/soc/dove/pmu.c val &= readl_relaxed(pmc_base + PMC_SW_RST); val 165 drivers/soc/dove/pmu.c writel_relaxed(val, pmc_base + PMC_SW_RST); val 169 drivers/soc/dove/pmu.c val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask; val 170 drivers/soc/dove/pmu.c writel_relaxed(val, pmu_base + PMU_PWR); val 182 drivers/soc/dove/pmu.c unsigned int val; val 189 drivers/soc/dove/pmu.c val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR); val 190 drivers/soc/dove/pmu.c writel_relaxed(val, pmu_base + PMU_PWR); val 194 drivers/soc/dove/pmu.c val = pmu_dom->rst_mask; val 195 drivers/soc/dove/pmu.c val |= readl_relaxed(pmc_base + PMC_SW_RST); val 196 drivers/soc/dove/pmu.c writel_relaxed(val, pmc_base + PMC_SW_RST); val 201 drivers/soc/dove/pmu.c val = pmu_dom->iso_mask; val 202 drivers/soc/dove/pmu.c val |= readl_relaxed(pmu_base + PMU_ISO); val 203 drivers/soc/dove/pmu.c writel_relaxed(val, pmu_base + PMU_ISO); val 214 drivers/soc/dove/pmu.c unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR); val 219 drivers/soc/dove/pmu.c pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask)); val 196 drivers/soc/fsl/qbman/bman.c static inline void bm_out(struct bm_portal *p, u32 offset, u32 val) val 198 drivers/soc/fsl/qbman/bman.c iowrite32be(val, p->addr.ci + offset); val 84 drivers/soc/fsl/qbman/bman_ccsr.c static inline void bm_ccsr_out(u32 offset, u32 val) val 86 drivers/soc/fsl/qbman/bman_ccsr.c iowrite32be(val, bm_ccsr_start + offset/4); val 368 drivers/soc/fsl/qbman/qman.c static inline void qm_out(struct qm_portal *p, u32 offset, u32 val) val 370 drivers/soc/fsl/qbman/qman.c iowrite32be(val, p->addr.ci + offset); val 2385 drivers/soc/fsl/qbman/qman.c static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val) val 2391 drivers/soc/fsl/qbman/qman.c cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi)); val 2394 drivers/soc/fsl/qbman/qman.c static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val) val 2399 drivers/soc/fsl/qbman/qman.c cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi)); val 284 drivers/soc/fsl/qbman/qman_ccsr.c static inline void qm_ccsr_out(u32 offset, u32 val) val 286 drivers/soc/fsl/qbman/qman_ccsr.c iowrite32be(val, qm_ccsr_start + offset/4); val 237 drivers/soc/fsl/qbman/qman_portal.c u32 val; val 269 drivers/soc/fsl/qbman/qman_portal.c err = of_property_read_u32(node, "cell-index", &val); val 275 drivers/soc/fsl/qbman/qman_portal.c pcfg->channel = val; val 62 drivers/soc/fsl/qe/gpio.c static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) val 72 drivers/soc/fsl/qe/gpio.c if (val) val 124 drivers/soc/fsl/qe/gpio.c static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) val 130 drivers/soc/fsl/qe/gpio.c qe_gpio_set(gc, gpio, val); val 125 drivers/soc/fsl/qe/qe_io.c int par_io_data_set(u8 port, u8 pin, u8 val) val 138 drivers/soc/fsl/qe/qe_io.c if (val == 0) /* clear */ val 42 drivers/soc/fsl/qe/qe_tdm.c u32 val; val 70 drivers/soc/fsl/qe/qe_tdm.c ret = of_property_read_u32_index(np, "fsl,tx-timeslot-mask", 0, &val); val 75 drivers/soc/fsl/qe/qe_tdm.c utdm->tx_ts_mask = val; val 77 drivers/soc/fsl/qe/qe_tdm.c ret = of_property_read_u32_index(np, "fsl,rx-timeslot-mask", 0, &val); val 83 drivers/soc/fsl/qe/qe_tdm.c utdm->rx_ts_mask = val; val 85 drivers/soc/fsl/qe/qe_tdm.c ret = of_property_read_u32_index(np, "fsl,tdm-id", 0, &val); val 91 drivers/soc/fsl/qe/qe_tdm.c utdm->tdm_port = val; val 110 drivers/soc/fsl/qe/qe_tdm.c ret = of_property_read_u32_index(np, "fsl,siram-entry-id", 0, &val); val 116 drivers/soc/fsl/qe/qe_tdm.c utdm->siram_entry_id = val; val 23 drivers/soc/fsl/qe/usb.c u32 val; val 26 drivers/soc/fsl/qe/usb.c case QE_CLK3: val = QE_CMXGCR_USBCS_CLK3; break; val 27 drivers/soc/fsl/qe/usb.c case QE_CLK5: val = QE_CMXGCR_USBCS_CLK5; break; val 28 drivers/soc/fsl/qe/usb.c case QE_CLK7: val = QE_CMXGCR_USBCS_CLK7; break; val 29 drivers/soc/fsl/qe/usb.c case QE_CLK9: val = QE_CMXGCR_USBCS_CLK9; break; val 30 drivers/soc/fsl/qe/usb.c case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break; val 31 drivers/soc/fsl/qe/usb.c case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break; val 32 drivers/soc/fsl/qe/usb.c case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break; val 33 drivers/soc/fsl/qe/usb.c case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break; val 34 drivers/soc/fsl/qe/usb.c case QE_BRG9: val = QE_CMXGCR_USBCS_BRG9; break; val 35 drivers/soc/fsl/qe/usb.c case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break; val 46 drivers/soc/fsl/qe/usb.c clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val); val 43 drivers/soc/gemini/soc-gemini.c u32 val; val 57 drivers/soc/gemini/soc-gemini.c val = (GEMINI_DEFAULT_BURST_SIZE << GEMINI_ARB1_BURST_SHIFT) | val 64 drivers/soc/gemini/soc-gemini.c val); val 67 drivers/soc/gemini/soc-gemini.c rev >> 8, rev & 0xff, val); val 63 drivers/soc/imx/gpc.c u32 val; val 66 drivers/soc/imx/gpc.c regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PDNSCR_OFFS, &val); val 67 drivers/soc/imx/gpc.c iso = val & 0x3f; val 68 drivers/soc/imx/gpc.c iso2sw = (val >> 8) & 0x3f; val 75 drivers/soc/imx/gpc.c val = BIT(pd->cntr_pdn_bit); val 76 drivers/soc/imx/gpc.c regmap_update_bits(pd->regmap, GPC_CNTR, val, val); val 91 drivers/soc/imx/gpc.c u32 val, req; val 115 drivers/soc/imx/gpc.c ret = regmap_read_poll_timeout(pd->regmap, GPC_CNTR, val, !(val & req), val 92 drivers/soc/imx/soc-imx-scu.c u32 val; val 116 drivers/soc/imx/soc-imx-scu.c val = id & 0x1f; val 117 drivers/soc/imx/soc-imx-scu.c soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x", val); val 122 drivers/soc/imx/soc-imx-scu.c val = (id >> 5) & 0xf; val 123 drivers/soc/imx/soc-imx-scu.c val = (((val >> 2) + 1) << 4) | (val & 0x3); val 126 drivers/soc/imx/soc-imx-scu.c (val >> 4) & 0xf, val 127 drivers/soc/imx/soc-imx-scu.c val & 0xf); val 135 drivers/soc/ixp4xx/ixp4xx-npe.c u32 reg, val; val 188 drivers/soc/ixp4xx/ixp4xx-npe.c u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); val 189 drivers/soc/ixp4xx/ixp4xx-npe.c npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); val 253 drivers/soc/ixp4xx/ixp4xx-npe.c u8 val, u32 ctx) val 258 drivers/soc/ixp4xx/ixp4xx-npe.c (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ val 259 drivers/soc/ixp4xx/ixp4xx-npe.c (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */ val 264 drivers/soc/ixp4xx/ixp4xx-npe.c u16 val, u32 ctx) val 269 drivers/soc/ixp4xx/ixp4xx-npe.c (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ val 270 drivers/soc/ixp4xx/ixp4xx-npe.c (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */ val 275 drivers/soc/ixp4xx/ixp4xx-npe.c u32 val, u32 ctx) val 278 drivers/soc/ixp4xx/ixp4xx-npe.c if (npe_logical_reg_write16(npe, addr, val >> 16, ctx)) val 280 drivers/soc/ixp4xx/ixp4xx-npe.c return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx); val 285 drivers/soc/ixp4xx/ixp4xx-npe.c u32 val, ctl, exec_count, ctx_reg2; val 325 drivers/soc/ixp4xx/ixp4xx-npe.c for (val = 0; val < NPE_PHYS_REG; val++) { val 326 drivers/soc/ixp4xx/ixp4xx-npe.c if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0)) val 329 drivers/soc/ixp4xx/ixp4xx-npe.c if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0)) val 337 drivers/soc/ixp4xx/ixp4xx-npe.c val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG); val 338 drivers/soc/ixp4xx/ixp4xx-npe.c val &= ~ECS_REG_0_NEXTPC_MASK; val 339 drivers/soc/ixp4xx/ixp4xx-npe.c val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK; val 340 drivers/soc/ixp4xx/ixp4xx-npe.c npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val); val 367 drivers/soc/ixp4xx/ixp4xx-npe.c for (val = 0; val < ARRAY_SIZE(ecs_reset); val++) val 368 drivers/soc/ixp4xx/ixp4xx-npe.c npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, val 369 drivers/soc/ixp4xx/ixp4xx-npe.c ecs_reset[val].val); val 381 drivers/soc/ixp4xx/ixp4xx-npe.c val = ixp4xx_read_feature_bits(); val 383 drivers/soc/ixp4xx/ixp4xx-npe.c ixp4xx_write_feature_bits(val & val 386 drivers/soc/ixp4xx/ixp4xx-npe.c ixp4xx_write_feature_bits(val | val 28 drivers/soc/ixp4xx/ixp4xx-qmgr.c void qmgr_put_entry(unsigned int queue, u32 val) val 34 drivers/soc/ixp4xx/ixp4xx-qmgr.c qmgr_queue_descs[queue], queue, val); val 36 drivers/soc/ixp4xx/ixp4xx-qmgr.c __raw_writel(val, &qmgr_regs->acc[queue][0]); val 41 drivers/soc/ixp4xx/ixp4xx-qmgr.c u32 val; val 42 drivers/soc/ixp4xx/ixp4xx-qmgr.c val = __raw_readl(&qmgr_regs->acc[queue][0]); val 47 drivers/soc/ixp4xx/ixp4xx-qmgr.c qmgr_queue_descs[queue], queue, val); val 49 drivers/soc/ixp4xx/ixp4xx-qmgr.c return val; val 35 drivers/soc/mediatek/mtk-infracfg.c u32 val; val 45 drivers/soc/mediatek/mtk-infracfg.c val, (val & mask) == mask, val 67 drivers/soc/mediatek/mtk-infracfg.c u32 val; val 75 drivers/soc/mediatek/mtk-infracfg.c val, !(val & mask), val 1005 drivers/soc/mediatek/mtk-pmic-wrap.c static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) val 1007 drivers/soc/mediatek/mtk-pmic-wrap.c writel(val, wrp->base + wrp->master->regs[reg]); val 1012 drivers/soc/mediatek/mtk-pmic-wrap.c u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); val 1014 drivers/soc/mediatek/mtk-pmic-wrap.c return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE; val 1019 drivers/soc/mediatek/mtk-pmic-wrap.c u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); val 1021 drivers/soc/mediatek/mtk-pmic-wrap.c return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR; val 1045 drivers/soc/mediatek/mtk-pmic-wrap.c u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); val 1047 drivers/soc/mediatek/mtk-pmic-wrap.c return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) && val 1048 drivers/soc/mediatek/mtk-pmic-wrap.c (val & PWRAP_STATE_SYNC_IDLE0); val 189 drivers/soc/mediatek/mtk-scpsys.c u32 val; val 209 drivers/soc/mediatek/mtk-scpsys.c val = readl(ctl_addr); val 210 drivers/soc/mediatek/mtk-scpsys.c val |= PWR_ON_BIT; val 211 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 212 drivers/soc/mediatek/mtk-scpsys.c val |= PWR_ON_2ND_BIT; val 213 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 221 drivers/soc/mediatek/mtk-scpsys.c val &= ~PWR_CLK_DIS_BIT; val 222 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 224 drivers/soc/mediatek/mtk-scpsys.c val &= ~PWR_ISO_BIT; val 225 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 227 drivers/soc/mediatek/mtk-scpsys.c val |= PWR_RST_B_BIT; val 228 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 230 drivers/soc/mediatek/mtk-scpsys.c val &= ~scpd->data->sram_pdn_bits; val 231 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 279 drivers/soc/mediatek/mtk-scpsys.c u32 val; val 291 drivers/soc/mediatek/mtk-scpsys.c val = readl(ctl_addr); val 292 drivers/soc/mediatek/mtk-scpsys.c val |= scpd->data->sram_pdn_bits; val 293 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 301 drivers/soc/mediatek/mtk-scpsys.c val |= PWR_ISO_BIT; val 302 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 304 drivers/soc/mediatek/mtk-scpsys.c val &= ~PWR_RST_B_BIT; val 305 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 307 drivers/soc/mediatek/mtk-scpsys.c val |= PWR_CLK_DIS_BIT; val 308 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 310 drivers/soc/mediatek/mtk-scpsys.c val &= ~PWR_ON_BIT; val 311 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 313 drivers/soc/mediatek/mtk-scpsys.c val &= ~PWR_ON_2ND_BIT; val 314 drivers/soc/mediatek/mtk-scpsys.c writel(val, ctl_addr); val 188 drivers/soc/qcom/qcom-geni-se.c u32 val; val 190 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(base + SE_IRQ_EN); val 191 drivers/soc/qcom/qcom-geni-se.c val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; val 192 drivers/soc/qcom/qcom-geni-se.c val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; val 193 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, base + SE_IRQ_EN); val 195 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); val 196 drivers/soc/qcom/qcom-geni-se.c val &= ~GENI_DMA_MODE_EN; val 197 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); val 204 drivers/soc/qcom/qcom-geni-se.c u32 val; val 206 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(base + GENI_CGC_CTRL); val 207 drivers/soc/qcom/qcom-geni-se.c val |= DEFAULT_CGC_EN; val 208 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, base + GENI_CGC_CTRL); val 210 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(base + SE_DMA_GENERAL_CFG); val 211 drivers/soc/qcom/qcom-geni-se.c val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; val 212 drivers/soc/qcom/qcom-geni-se.c val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; val 213 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, base + SE_DMA_GENERAL_CFG); val 240 drivers/soc/qcom/qcom-geni-se.c u32 val; val 249 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); val 250 drivers/soc/qcom/qcom-geni-se.c val |= M_COMMON_GENI_M_IRQ_EN; val 251 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); val 253 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); val 254 drivers/soc/qcom/qcom-geni-se.c val |= S_COMMON_GENI_S_IRQ_EN; val 255 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); val 262 drivers/soc/qcom/qcom-geni-se.c u32 val; val 266 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); val 268 drivers/soc/qcom/qcom-geni-se.c val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; val 269 drivers/soc/qcom/qcom-geni-se.c val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; val 271 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); val 273 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); val 275 drivers/soc/qcom/qcom-geni-se.c val |= S_CMD_DONE_EN; val 276 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); val 278 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); val 279 drivers/soc/qcom/qcom-geni-se.c val &= ~GENI_DMA_MODE_EN; val 280 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); val 285 drivers/soc/qcom/qcom-geni-se.c u32 val; val 289 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); val 290 drivers/soc/qcom/qcom-geni-se.c val |= GENI_DMA_MODE_EN; val 291 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); val 631 drivers/soc/qcom/qcom-geni-se.c u32 val; val 640 drivers/soc/qcom/qcom-geni-se.c val = GENI_SE_DMA_DONE_EN; val 641 drivers/soc/qcom/qcom-geni-se.c val |= GENI_SE_DMA_EOT_EN; val 642 drivers/soc/qcom/qcom-geni-se.c val |= GENI_SE_DMA_AHB_ERR_EN; val 643 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); val 667 drivers/soc/qcom/qcom-geni-se.c u32 val; val 676 drivers/soc/qcom/qcom-geni-se.c val = GENI_SE_DMA_DONE_EN; val 677 drivers/soc/qcom/qcom-geni-se.c val |= GENI_SE_DMA_EOT_EN; val 678 drivers/soc/qcom/qcom-geni-se.c val |= GENI_SE_DMA_AHB_ERR_EN; val 679 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); val 124 drivers/soc/qcom/qcom_aoss.c u32 val; val 131 drivers/soc/qcom/qcom_aoss.c val = readl(qmp->msgram + QMP_DESC_VERSION); val 132 drivers/soc/qcom/qcom_aoss.c if (val != QMP_VERSION) { val 133 drivers/soc/qcom/qcom_aoss.c dev_err(qmp->dev, "unsupported QMP version %d\n", val); val 145 drivers/soc/qcom/qcom_aoss.c val = readl(qmp->msgram + QMP_DESC_UCORE_LINK_STATE); val 146 drivers/soc/qcom/qcom_aoss.c writel(val, qmp->msgram + QMP_DESC_UCORE_LINK_STATE_ACK); val 183 drivers/soc/qcom/smp2p.c u32 val; val 218 drivers/soc/qcom/smp2p.c val = readl(entry->value); val 220 drivers/soc/qcom/smp2p.c status = val ^ entry->last_value; val 221 drivers/soc/qcom/smp2p.c entry->last_value = val; val 231 drivers/soc/qcom/smp2p.c if ((val & BIT(i) && test_bit(i, entry->irq_rising)) || val 232 drivers/soc/qcom/smp2p.c (!(val & BIT(i)) && test_bit(i, entry->irq_falling))) { val 322 drivers/soc/qcom/smp2p.c u32 val; val 325 drivers/soc/qcom/smp2p.c val = orig = readl(entry->value); val 326 drivers/soc/qcom/smp2p.c val &= ~mask; val 327 drivers/soc/qcom/smp2p.c val |= value; val 328 drivers/soc/qcom/smp2p.c writel(val, entry->value); val 331 drivers/soc/qcom/smp2p.c if (val != orig) val 147 drivers/soc/qcom/smsm.c u32 val; val 152 drivers/soc/qcom/smsm.c val = orig = readl(smsm->local_state); val 153 drivers/soc/qcom/smsm.c val &= ~mask; val 154 drivers/soc/qcom/smsm.c val |= value; val 157 drivers/soc/qcom/smsm.c changes = val ^ orig; val 164 drivers/soc/qcom/smsm.c writel(val, smsm->local_state); val 174 drivers/soc/qcom/smsm.c val = readl(smsm->subscription + host); val 175 drivers/soc/qcom/smsm.c if (val & changes && hostp->ipc_regmap) { val 204 drivers/soc/qcom/smsm.c u32 val; val 206 drivers/soc/qcom/smsm.c val = readl(entry->remote_state); val 207 drivers/soc/qcom/smsm.c changed = val ^ entry->last_value; val 208 drivers/soc/qcom/smsm.c entry->last_value = val; val 214 drivers/soc/qcom/smsm.c if (val & BIT(i)) { val 242 drivers/soc/qcom/smsm.c u32 val; val 245 drivers/soc/qcom/smsm.c val = readl(entry->subscription + smsm->local_host); val 246 drivers/soc/qcom/smsm.c val &= ~BIT(irq); val 247 drivers/soc/qcom/smsm.c writel(val, entry->subscription + smsm->local_host); val 267 drivers/soc/qcom/smsm.c u32 val; val 272 drivers/soc/qcom/smsm.c val = readl(entry->subscription + smsm->local_host); val 273 drivers/soc/qcom/smsm.c val |= BIT(irq); val 274 drivers/soc/qcom/smsm.c writel(val, entry->subscription + smsm->local_host); val 116 drivers/soc/qcom/spm.c enum spm_reg reg, u32 val) val 119 drivers/soc/qcom/spm.c writel_relaxed(val, drv->reg_base + val 125 drivers/soc/qcom/spm.c enum spm_reg reg, u32 val) val 133 drivers/soc/qcom/spm.c writel_relaxed(val, drv->reg_base + val 137 drivers/soc/qcom/spm.c if (ret == val) val 14 drivers/soc/rockchip/grf.c #define HIWORD_UPDATE(val, mask, shift) \ val 15 drivers/soc/rockchip/grf.c ((val) << (shift) | (mask) << ((shift) + 16)) val 20 drivers/soc/rockchip/grf.c u32 val; val 163 drivers/soc/rockchip/grf.c const struct rockchip_grf_value *val = &grf_info->values[i]; val 166 drivers/soc/rockchip/grf.c val->desc, val->reg, val->val); val 167 drivers/soc/rockchip/grf.c ret = regmap_write(grf, val->reg, val->val); val 170 drivers/soc/rockchip/grf.c __func__, val->reg, ret); val 138 drivers/soc/rockchip/pm_domains.c unsigned int val; val 140 drivers/soc/rockchip/pm_domains.c regmap_read(pmu->regmap, pmu->info->idle_offset, &val); val 141 drivers/soc/rockchip/pm_domains.c return (val & pd_info->idle_mask) == pd_info->idle_mask; val 146 drivers/soc/rockchip/pm_domains.c unsigned int val; val 148 drivers/soc/rockchip/pm_domains.c regmap_read(pmu->regmap, pmu->info->ack_offset, &val); val 149 drivers/soc/rockchip/pm_domains.c return val; val 159 drivers/soc/rockchip/pm_domains.c unsigned int val; val 177 drivers/soc/rockchip/pm_domains.c ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val, val 178 drivers/soc/rockchip/pm_domains.c (val & pd_info->ack_mask) == target_ack, val 183 drivers/soc/rockchip/pm_domains.c genpd->name, val); val 251 drivers/soc/rockchip/pm_domains.c unsigned int val; val 257 drivers/soc/rockchip/pm_domains.c regmap_read(pmu->regmap, pmu->info->status_offset, &val); val 260 drivers/soc/rockchip/pm_domains.c return !(val & pd->info->status_mask); val 28 drivers/soc/samsung/exynos-pmu.c void pmu_raw_writel(u32 val, u32 offset) val 30 drivers/soc/samsung/exynos-pmu.c writel_relaxed(val, pmu_base_addr + offset); val 53 drivers/soc/samsung/exynos-pmu.c pmu_raw_writel(pmu_data->pmu_config[i].val[mode], val 18 drivers/soc/samsung/exynos-pmu.h u8 val[NUM_SYS_POWERDOWN]; val 40 drivers/soc/samsung/exynos-pmu.h extern void pmu_raw_writel(u32 val, u32 offset); val 26 drivers/soc/sunxi/sunxi_sram.c u8 val; val 47 drivers/soc/sunxi/sunxi_sram.c .val = _val, \ val 117 drivers/soc/sunxi/sunxi_sram.c u32 val; val 141 drivers/soc/sunxi/sunxi_sram.c val = readl(base + sram_data->reg); val 142 drivers/soc/sunxi/sunxi_sram.c val >>= sram_data->offset; val 143 drivers/soc/sunxi/sunxi_sram.c val &= GENMASK(sram_data->width - 1, 0); val 147 drivers/soc/sunxi/sunxi_sram.c func->reg_val == val ? val 172 drivers/soc/sunxi/sunxi_sram.c u8 val; val 185 drivers/soc/sunxi/sunxi_sram.c val = args.args[0]; val 200 drivers/soc/sunxi/sunxi_sram.c if (val == func->val) { val 226 drivers/soc/sunxi/sunxi_sram.c u32 val, mask; val 252 drivers/soc/sunxi/sunxi_sram.c val = readl(base + sram_data->reg); val 253 drivers/soc/sunxi/sunxi_sram.c val &= ~mask; val 254 drivers/soc/sunxi/sunxi_sram.c writel(val | ((device << sram_data->offset) & mask), val 36 drivers/soc/tegra/fuse/fuse-tegra.c u32 val; val 38 drivers/soc/tegra/fuse/fuse-tegra.c val = fuse->read(fuse, round_down(offset, 4)); val 39 drivers/soc/tegra/fuse/fuse-tegra.c val >>= (offset % 4) * 8; val 40 drivers/soc/tegra/fuse/fuse-tegra.c val &= 0xff; val 42 drivers/soc/tegra/fuse/fuse-tegra.c return val; val 57 drivers/soc/tegra/fuse/speedo-tegra20.c u32 val; val 70 drivers/soc/tegra/fuse/speedo-tegra20.c val = 0; val 74 drivers/soc/tegra/fuse/speedo-tegra20.c val = (val << 1) | (reg & 0x1); val 76 drivers/soc/tegra/fuse/speedo-tegra20.c val = val * SPEEDO_MULT; val 77 drivers/soc/tegra/fuse/speedo-tegra20.c pr_debug("Tegra CPU speedo value %u\n", val); val 80 drivers/soc/tegra/fuse/speedo-tegra20.c if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i]) val 85 drivers/soc/tegra/fuse/speedo-tegra20.c val = 0; val 89 drivers/soc/tegra/fuse/speedo-tegra20.c val = (val << 1) | (reg & 0x1); val 91 drivers/soc/tegra/fuse/speedo-tegra20.c val = val * SPEEDO_MULT; val 92 drivers/soc/tegra/fuse/speedo-tegra20.c pr_debug("Core speedo value %u\n", val); val 95 drivers/soc/tegra/fuse/speedo-tegra20.c if (val <= soc_process_speedos[sku_info->soc_speedo_id][i]) val 1213 drivers/soc/tegra/pmc.c u32 mask, u32 val, unsigned long timeout) val 1221 drivers/soc/tegra/pmc.c if ((value & mask) == val) val 86 drivers/soc/ti/knav_qmss_acc.c u32 *list, *list_cpu, val, idx, notifies; val 143 drivers/soc/ti/knav_qmss_acc.c val = list[ACC_LIST_ENTRY_DESC_IDX]; val 144 drivers/soc/ti/knav_qmss_acc.c if (!val) val 171 drivers/soc/ti/knav_qmss_acc.c kq->descs[idx] = val; val 174 drivers/soc/ti/knav_qmss_acc.c val, idx, queue + range_base); val 494 drivers/soc/ti/knav_qmss_queue.c u32 val = 0; val 498 drivers/soc/ti/knav_qmss_queue.c val = readl_relaxed(addr); val 500 drivers/soc/ti/knav_qmss_queue.c val &= flags; val 501 drivers/soc/ti/knav_qmss_queue.c if (!val) val 505 drivers/soc/ti/knav_qmss_queue.c return val ? -ETIMEDOUT : 0; val 644 drivers/soc/ti/knav_qmss_queue.c u32 val; val 646 drivers/soc/ti/knav_qmss_queue.c val = (u32)dma | ((size / 16) - 1); val 647 drivers/soc/ti/knav_qmss_queue.c writel_relaxed(val, &qh->reg_push[0].ptr_size_thresh); val 666 drivers/soc/ti/knav_qmss_queue.c u32 val, idx; val 676 drivers/soc/ti/knav_qmss_queue.c val = inst->descs[idx]; val 678 drivers/soc/ti/knav_qmss_queue.c val = readl_relaxed(&qh->reg_pop[0].ptr_size_thresh); val 679 drivers/soc/ti/knav_qmss_queue.c if (unlikely(!val)) val 683 drivers/soc/ti/knav_qmss_queue.c dma = val & DESC_PTR_MASK; val 685 drivers/soc/ti/knav_qmss_queue.c *size = ((val & DESC_SIZE_MASK) + 1) * 16; val 1552 drivers/soc/ti/knav_qmss_queue.c u32 val, timeout = 1000; val 1555 drivers/soc/ti/knav_qmss_queue.c val = readl_relaxed(&pdsp->regs->control) & ~PDSP_CTRL_ENABLE; val 1556 drivers/soc/ti/knav_qmss_queue.c writel_relaxed(val, &pdsp->regs->control); val 1610 drivers/soc/ti/knav_qmss_queue.c u32 val, timeout = 1000; val 1619 drivers/soc/ti/knav_qmss_queue.c val = readl_relaxed(&pdsp->regs->control); val 1620 drivers/soc/ti/knav_qmss_queue.c val &= ~(PDSP_CTRL_PC_MASK | PDSP_CTRL_SOFT_RESET); val 1621 drivers/soc/ti/knav_qmss_queue.c writel_relaxed(val, &pdsp->regs->control); val 1624 drivers/soc/ti/knav_qmss_queue.c val = readl_relaxed(&pdsp->regs->control) | PDSP_CTRL_ENABLE; val 1625 drivers/soc/ti/knav_qmss_queue.c writel_relaxed(val, &pdsp->regs->control); val 277 drivers/soc/ti/pm33xx.c u32 val = 0; val 300 drivers/soc/ti/pm33xx.c (void *)&val); val 409 drivers/soc/ti/pm33xx.c unsigned long val = 0; val 430 drivers/soc/ti/pm33xx.c 4, (void *)&val); val 431 drivers/soc/ti/pm33xx.c val = pm_sram->resume_address; val 433 drivers/soc/ti/pm33xx.c 4, (void *)&val); val 82 drivers/soc/ti/wkup_m3_ipc.c u32 val, int ipc_reg_num) val 88 drivers/soc/ti/wkup_m3_ipc.c writel(val, m3_ipc->ipc_mem_base + val 105 drivers/soc/ti/wkup_m3_ipc.c int val; val 107 drivers/soc/ti/wkup_m3_ipc.c val = wkup_m3_ctrl_ipc_read(m3_ipc, 2); val 109 drivers/soc/ti/wkup_m3_ipc.c return val & M3_FW_VERSION_MASK; val 250 drivers/soc/ti/wkup_m3_ipc.c int val; val 252 drivers/soc/ti/wkup_m3_ipc.c val = wkup_m3_ctrl_ipc_read(m3_ipc, 1); val 254 drivers/soc/ti/wkup_m3_ipc.c i = M3_STATUS_RESP_MASK & val; val 350 drivers/soc/ti/wkup_m3_ipc.c int j, val; val 352 drivers/soc/ti/wkup_m3_ipc.c val = wkup_m3_ctrl_ipc_read(m3_ipc, 6); val 354 drivers/soc/ti/wkup_m3_ipc.c wakeup_src_idx = val & M3_WAKE_SRC_MASK; val 106 drivers/soc/versatile/soc-integrator.c u32 val; val 118 drivers/soc/versatile/soc-integrator.c &val); val 121 drivers/soc/versatile/soc-integrator.c integrator_coreid = val; val 143 drivers/soc/versatile/soc-integrator.c dev_info(dev, " Manufacturer: %02x\n", (val >> 24)); val 144 drivers/soc/versatile/soc-integrator.c dev_info(dev, " Architecture: %s\n", integrator_arch_str(val)); val 145 drivers/soc/versatile/soc-integrator.c dev_info(dev, " FPGA: %s\n", integrator_fpga_str(val)); val 146 drivers/soc/versatile/soc-integrator.c dev_info(dev, " Build: %02x\n", (val >> 4) & 0xFF); val 147 drivers/soc/versatile/soc-integrator.c dev_info(dev, " Rev: %c\n", ('A' + (val & 0x03))); val 271 drivers/soc/xilinx/xlnx_vcu.c u32 val = xvcu_read(iomem, offset); val 273 drivers/soc/xilinx/xlnx_vcu.c val &= ~(mask << shift); val 274 drivers/soc/xilinx/xlnx_vcu.c val |= (field & mask) << shift; val 276 drivers/soc/xilinx/xlnx_vcu.c xvcu_write(iomem, offset, val); val 27 drivers/soc/zte/zx2967_pm_domains.c u32 val; val 29 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd)); val 31 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); val 33 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); val 34 drivers/soc/zte/zx2967_pm_domains.c writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd)); val 38 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd)) val 40 drivers/soc/zte/zx2967_pm_domains.c } while (--loop && !val); val 47 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd)); val 48 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); val 49 drivers/soc/zte/zx2967_pm_domains.c writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd)); val 52 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd)); val 53 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); val 54 drivers/soc/zte/zx2967_pm_domains.c writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd)); val 57 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd)); val 58 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); val 59 drivers/soc/zte/zx2967_pm_domains.c writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd)); val 71 drivers/soc/zte/zx2967_pm_domains.c u32 val; val 73 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd)); val 74 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); val 75 drivers/soc/zte/zx2967_pm_domains.c writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd)); val 78 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd)); val 79 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); val 80 drivers/soc/zte/zx2967_pm_domains.c writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd)); val 83 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd)); val 84 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); val 85 drivers/soc/zte/zx2967_pm_domains.c writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd)); val 88 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd)); val 90 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); val 92 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); val 93 drivers/soc/zte/zx2967_pm_domains.c writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd)); val 97 drivers/soc/zte/zx2967_pm_domains.c val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd)) val 99 drivers/soc/zte/zx2967_pm_domains.c } while (--loop && val); val 327 drivers/soundwire/bus.c int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) val 333 drivers/soundwire/bus.c slave->dev_num, SDW_MSG_FLAG_READ, val); val 355 drivers/soundwire/bus.c int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) val 361 drivers/soundwire/bus.c slave->dev_num, SDW_MSG_FLAG_WRITE, val); val 612 drivers/soundwire/bus.c u8 val = 0; val 618 drivers/soundwire/bus.c val |= mask; val 619 drivers/soundwire/bus.c val |= SDW_DPN_INT_PORT_READY; val 621 drivers/soundwire/bus.c val &= ~(mask); val 622 drivers/soundwire/bus.c val &= ~SDW_DPN_INT_PORT_READY; val 625 drivers/soundwire/bus.c ret = sdw_update(slave, addr, (mask | SDW_DPN_INT_PORT_READY), val); val 628 drivers/soundwire/bus.c "SDW_DPN_INTMASK write failed:%d\n", val); val 637 drivers/soundwire/bus.c u8 val; val 645 drivers/soundwire/bus.c val = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH | val 649 drivers/soundwire/bus.c ret = sdw_update(slave, SDW_SCP_INTMASK1, val, val); val 661 drivers/soundwire/bus.c val = prop->dp0_prop->imp_def_interrupts; val 662 drivers/soundwire/bus.c val |= SDW_DP0_INT_PORT_READY | SDW_DP0_INT_BRA_FAILURE; val 664 drivers/soundwire/bus.c ret = sdw_update(slave, SDW_DP0_INTMASK, val, val); val 668 drivers/soundwire/bus.c return val; val 155 drivers/soundwire/bus.h sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) val 163 drivers/soundwire/bus.h tmp = (tmp & ~mask) | val; val 205 drivers/soundwire/cadence_master.c int offset, u32 mask, u32 val) val 210 drivers/soundwire/cadence_master.c tmp = (tmp & ~mask) | val; val 926 drivers/soundwire/cadence_master.c u32 val; val 933 drivers/soundwire/cadence_master.c val = (r << CDNS_MCP_FRAME_SHAPE_ROW_OFFSET) | c; val 935 drivers/soundwire/cadence_master.c return val; val 946 drivers/soundwire/cadence_master.c u32 val; val 970 drivers/soundwire/cadence_master.c val = cdns_set_initial_frame_shape(prop->default_row, val 972 drivers/soundwire/cadence_master.c cdns_writel(cdns, CDNS_MCP_FRAME_SHAPE_INIT, val); val 983 drivers/soundwire/cadence_master.c val = cdns_readl(cdns, CDNS_MCP_CONFIG); val 986 drivers/soundwire/cadence_master.c val |= CDNS_MCP_CONFIG_MCMD_RETRY; val 989 drivers/soundwire/cadence_master.c val |= 0xF << SDW_REG_SHIFT(CDNS_MCP_CONFIG_MPREQ_DELAY); val 992 drivers/soundwire/cadence_master.c val &= ~CDNS_MCP_CONFIG_BUS_REL; val 995 drivers/soundwire/cadence_master.c val &= ~CDNS_MCP_CONFIG_SNIFFER; val 998 drivers/soundwire/cadence_master.c val &= ~CDNS_MCP_CONFIG_CMD; val 1001 drivers/soundwire/cadence_master.c val &= ~CDNS_MCP_CONFIG_OP; val 1002 drivers/soundwire/cadence_master.c val |= CDNS_MCP_CONFIG_OP_NORMAL; val 1004 drivers/soundwire/cadence_master.c cdns_writel(cdns, CDNS_MCP_CONFIG, val); val 1219 drivers/soundwire/cadence_master.c u32 offset, val = 0; val 1222 drivers/soundwire/cadence_master.c val = CDNS_PORTCTRL_DIRN; val 1225 drivers/soundwire/cadence_master.c cdns_updatel(cdns, offset, CDNS_PORTCTRL_DIRN, val); val 1227 drivers/soundwire/cadence_master.c val = port->num; val 1228 drivers/soundwire/cadence_master.c val |= ((1 << ch) - 1) << SDW_REG_SHIFT(CDNS_PDI_CONFIG_CHANNEL); val 1229 drivers/soundwire/cadence_master.c cdns_writel(cdns, CDNS_PDI_CONFIG(pdi->num), val); val 425 drivers/soundwire/stream.c int ret = 0, val; val 483 drivers/soundwire/stream.c val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num)); val 484 drivers/soundwire/stream.c val &= p_rt->ch_mask; val 485 drivers/soundwire/stream.c if (!time_left || val) { val 253 drivers/spi/atmel-quadspi.c icr |= QSPI_ICR_OPT(op->addr.val & 0xff); val 260 drivers/spi/atmel-quadspi.c (op->addr.val & 0xffff); val 263 drivers/spi/atmel-quadspi.c iar = (op->addr.val << 8) & 0xffffff; val 269 drivers/spi/atmel-quadspi.c iar = op->addr.val & 0xffffff; val 273 drivers/spi/atmel-quadspi.c iar = op->addr.val & 0x7ffffff; val 338 drivers/spi/atmel-quadspi.c if (op->addr.val + op->data.nbytes > aq->mmap_size) val 129 drivers/spi/spi-armada-3700.c u32 val; val 131 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 132 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_AUTO_CS; val 133 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 138 drivers/spi/spi-armada-3700.c u32 val; val 140 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); val 141 drivers/spi/spi-armada-3700.c val |= (A3700_SPI_EN << cs); val 142 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); val 148 drivers/spi/spi-armada-3700.c u32 val; val 150 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); val 151 drivers/spi/spi-armada-3700.c val &= ~(A3700_SPI_EN << cs); val 152 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); val 158 drivers/spi/spi-armada-3700.c u32 val; val 160 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 161 drivers/spi/spi-armada-3700.c val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); val 162 drivers/spi/spi-armada-3700.c val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); val 168 drivers/spi/spi-armada-3700.c val |= A3700_SPI_DATA_PIN0; val 171 drivers/spi/spi-armada-3700.c val |= A3700_SPI_DATA_PIN1; val 174 drivers/spi/spi-armada-3700.c val |= A3700_SPI_ADDR_PIN; val 181 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 188 drivers/spi/spi-armada-3700.c u32 val; val 190 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 192 drivers/spi/spi-armada-3700.c val |= A3700_SPI_FIFO_MODE; val 194 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_FIFO_MODE; val 195 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 201 drivers/spi/spi-armada-3700.c u32 val; val 203 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 206 drivers/spi/spi-armada-3700.c val |= A3700_SPI_CLK_POL; val 208 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_CLK_POL; val 211 drivers/spi/spi-armada-3700.c val |= A3700_SPI_CLK_PHA; val 213 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_CLK_PHA; val 215 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 221 drivers/spi/spi-armada-3700.c u32 val; val 233 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 234 drivers/spi/spi-armada-3700.c val = val & ~A3700_SPI_CLK_PRESCALE_MASK; val 236 drivers/spi/spi-armada-3700.c val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); val 237 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 240 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); val 241 drivers/spi/spi-armada-3700.c val |= A3700_SPI_CLK_CAPT_EDGE; val 242 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); val 248 drivers/spi/spi-armada-3700.c u32 val; val 250 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 252 drivers/spi/spi-armada-3700.c val |= A3700_SPI_BYTE_LEN; val 254 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_BYTE_LEN; val 255 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 263 drivers/spi/spi-armada-3700.c u32 val; val 265 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 266 drivers/spi/spi-armada-3700.c val |= A3700_SPI_FIFO_FLUSH; val 267 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 270 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 271 drivers/spi/spi-armada-3700.c if (!(val & A3700_SPI_FIFO_FLUSH)) val 282 drivers/spi/spi-armada-3700.c u32 val; val 286 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 287 drivers/spi/spi-armada-3700.c val |= A3700_SPI_SRST; val 288 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 292 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 293 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_SRST; val 294 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 407 drivers/spi/spi-armada-3700.c u32 val; val 409 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 410 drivers/spi/spi-armada-3700.c val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); val 411 drivers/spi/spi-armada-3700.c val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; val 412 drivers/spi/spi-armada-3700.c val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); val 413 drivers/spi/spi-armada-3700.c val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; val 414 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 450 drivers/spi/spi-armada-3700.c u32 val = 0; val 470 drivers/spi/spi-armada-3700.c val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) val 472 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); val 478 drivers/spi/spi-armada-3700.c val = 0; val 480 drivers/spi/spi-armada-3700.c val = (val << 8) | a3700_spi->tx_buf[0]; val 483 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); val 490 drivers/spi/spi-armada-3700.c u32 val; val 492 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); val 493 drivers/spi/spi-armada-3700.c return (val & A3700_SPI_WFIFO_FULL); val 498 drivers/spi/spi-armada-3700.c u32 val; val 501 drivers/spi/spi-armada-3700.c val = *(u32 *)a3700_spi->tx_buf; val 502 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); val 512 drivers/spi/spi-armada-3700.c u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); val 514 drivers/spi/spi-armada-3700.c return (val & A3700_SPI_RFIFO_EMPTY); val 519 drivers/spi/spi-armada-3700.c u32 val; val 522 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); val 525 drivers/spi/spi-armada-3700.c memcpy(a3700_spi->rx_buf, &val, 4); val 536 drivers/spi/spi-armada-3700.c *a3700_spi->rx_buf = val & 0xff; val 537 drivers/spi/spi-armada-3700.c val >>= 8; val 551 drivers/spi/spi-armada-3700.c u32 val; val 553 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 554 drivers/spi/spi-armada-3700.c val |= A3700_SPI_XFER_STOP; val 555 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 558 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 559 drivers/spi/spi-armada-3700.c if (!(val & A3700_SPI_XFER_START)) val 566 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_XFER_STOP; val 567 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 600 drivers/spi/spi-armada-3700.c u32 val; val 632 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 633 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_RW_EN; val 634 drivers/spi/spi-armada-3700.c val |= A3700_SPI_XFER_START; val 635 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 638 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 639 drivers/spi/spi-armada-3700.c val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); val 640 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 712 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 713 drivers/spi/spi-armada-3700.c val |= A3700_SPI_XFER_STOP; val 714 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 718 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val 719 drivers/spi/spi-armada-3700.c if (!(val & A3700_SPI_XFER_START)) val 730 drivers/spi/spi-armada-3700.c val &= ~A3700_SPI_XFER_STOP; val 731 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); val 747 drivers/spi/spi-armada-3700.c u32 val; val 761 drivers/spi/spi-armada-3700.c val = *a3700_spi->tx_buf; val 763 drivers/spi/spi-armada-3700.c val = *(u32 *)a3700_spi->tx_buf; val 765 drivers/spi/spi-armada-3700.c spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); val 772 drivers/spi/spi-armada-3700.c val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); val 774 drivers/spi/spi-armada-3700.c memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len); val 54 drivers/spi/spi-ath79.c static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val) val 56 drivers/spi/spi-ath79.c iowrite32(val, sp->base + reg); val 69 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_CMD_WRITE(reg, val) \ val 70 drivers/spi/spi-axi-spi-engine.c SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val)) val 443 drivers/spi/spi-bcm-qspi.c u32 val, mask; val 445 drivers/spi/spi-bcm-qspi.c val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); val 447 drivers/spi/spi-bcm-qspi.c if (val & mask || qspi->s3_strap_override_ctrl & mask) { val 692 drivers/spi/spi-bcm-qspi.c u8 val) val 697 drivers/spi/spi-bcm-qspi.c bcm_qspi_write(qspi, MSPI, reg_offset, val); val 701 drivers/spi/spi-bcm-qspi.c u16 val) val 707 drivers/spi/spi-bcm-qspi.c bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8)); val 708 drivers/spi/spi-bcm-qspi.c bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff)); val 716 drivers/spi/spi-bcm-qspi.c static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val) val 718 drivers/spi/spi-bcm-qspi.c bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val); val 736 drivers/spi/spi-bcm-qspi.c u8 val = buf ? buf[tp.byte] : 0x00; val 738 drivers/spi/spi-bcm-qspi.c write_txram_slot_u8(qspi, slot, val); val 739 drivers/spi/spi-bcm-qspi.c dev_dbg(&qspi->pdev->dev, "WR %02x\n", val); val 742 drivers/spi/spi-bcm-qspi.c u16 val = buf ? buf[tp.byte / 2] : 0x0000; val 744 drivers/spi/spi-bcm-qspi.c write_txram_slot_u16(qspi, slot, val); val 745 drivers/spi/spi-bcm-qspi.c dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); val 805 drivers/spi/spi-bcm-qspi.c from = op->addr.val; val 921 drivers/spi/spi-bcm-qspi.c cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); val 960 drivers/spi/spi-bcm-qspi.c addr = op->addr.val; val 1144 drivers/spi/spi-bcm-qspi.c u32 val = 0; val 1146 drivers/spi/spi-bcm-qspi.c val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID); val 1147 drivers/spi/spi-bcm-qspi.c qspi->bspi_maj_rev = (val >> 8) & 0xff; val 1148 drivers/spi/spi-bcm-qspi.c qspi->bspi_min_rev = val & 0xff; val 1205 drivers/spi/spi-bcm-qspi.c u32 val; val 1245 drivers/spi/spi-bcm-qspi.c if (!of_property_read_u32(dev->of_node, "num-cs", &val)) val 1246 drivers/spi/spi-bcm-qspi.c master->num_chipselect = val; val 1293 drivers/spi/spi-bcm-qspi.c for (val = 0; val < num_irqs; val++) { val 1295 drivers/spi/spi-bcm-qspi.c name = qspi_irq_tab[val].irq_name; val 1296 drivers/spi/spi-bcm-qspi.c if (qspi_irq_tab[val].irq_source == SINGLE_L2) { val 1306 drivers/spi/spi-bcm-qspi.c qspi_irq_tab[val].irq_handler, 0, val 1308 drivers/spi/spi-bcm-qspi.c &qspi->dev_ids[val]); val 1314 drivers/spi/spi-bcm-qspi.c qspi->dev_ids[val].dev = qspi; val 1315 drivers/spi/spi-bcm-qspi.c qspi->dev_ids[val].irqp = &qspi_irq_tab[val]; val 1318 drivers/spi/spi-bcm-qspi.c qspi_irq_tab[val].irq_name, val 199 drivers/spi/spi-bcm2835.c static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) val 201 drivers/spi/spi-bcm2835.c writel(val, bs->regs + reg); val 241 drivers/spi/spi-bcm2835.c u32 val; val 247 drivers/spi/spi-bcm2835.c val = bcm2835_rd(bs, BCM2835_SPI_FIFO); val 249 drivers/spi/spi-bcm2835.c memcpy(bs->rx_buf, &val, len); val 267 drivers/spi/spi-bcm2835.c u32 val; val 275 drivers/spi/spi-bcm2835.c memcpy(&val, bs->tx_buf, len); val 278 drivers/spi/spi-bcm2835.c val = 0; val 280 drivers/spi/spi-bcm2835.c bcm2835_wr(bs, BCM2835_SPI_FIFO, val); val 306 drivers/spi/spi-bcm2835.c u8 val; val 312 drivers/spi/spi-bcm2835.c val = bcm2835_rd(bs, BCM2835_SPI_FIFO); val 314 drivers/spi/spi-bcm2835.c *bs->rx_buf++ = val; val 326 drivers/spi/spi-bcm2835.c u8 val; val 332 drivers/spi/spi-bcm2835.c val = bs->tx_buf ? *bs->tx_buf++ : 0; val 333 drivers/spi/spi-bcm2835.c bcm2835_wr(bs, BCM2835_SPI_FIFO, val); val 152 drivers/spi/spi-bcm2835aux.c u32 val) val 154 drivers/spi/spi-bcm2835aux.c writel(val, bs->regs + reg); val 133 drivers/spi/spi-cadence.c static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) val 135 drivers/spi/spi-cadence.c writel_relaxed(val, xspi->regs + offset); val 68 drivers/spi/spi-coldfire-qspi.c static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) val 70 drivers/spi/spi-coldfire-qspi.c writew(val, mcfqspi->iobase + MCFQSPI_QMR); val 73 drivers/spi/spi-coldfire-qspi.c static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val) val 75 drivers/spi/spi-coldfire-qspi.c writew(val, mcfqspi->iobase + MCFQSPI_QDLYR); val 83 drivers/spi/spi-coldfire-qspi.c static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val) val 85 drivers/spi/spi-coldfire-qspi.c writew(val, mcfqspi->iobase + MCFQSPI_QWR); val 88 drivers/spi/spi-coldfire-qspi.c static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val) val 90 drivers/spi/spi-coldfire-qspi.c writew(val, mcfqspi->iobase + MCFQSPI_QIR); val 93 drivers/spi/spi-coldfire-qspi.c static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val) val 95 drivers/spi/spi-coldfire-qspi.c writew(val, mcfqspi->iobase + MCFQSPI_QAR); val 98 drivers/spi/spi-coldfire-qspi.c static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val) val 100 drivers/spi/spi-coldfire-qspi.c writew(val, mcfqspi->iobase + MCFQSPI_QDR); val 159 drivers/spi/spi-dw.h static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) val 161 drivers/spi/spi-dw.h __raw_writel(val, dws->regs + offset); val 164 drivers/spi/spi-dw.h static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) val 166 drivers/spi/spi-dw.h __raw_writew(val, dws->regs + offset); val 180 drivers/spi/spi-dw.h static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) val 184 drivers/spi/spi-dw.h dw_writew(dws, offset, val); val 188 drivers/spi/spi-dw.h dw_writel(dws, offset, val); val 20 drivers/spi/spi-efm32.c #define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask) val 147 drivers/spi/spi-efm32.c u8 val = 0; val 150 drivers/spi/spi-efm32.c val = *ddata->tx_buf; val 155 drivers/spi/spi-efm32.c efm32_spi_write32(ddata, val, REG_TXDATA); val 156 drivers/spi/spi-efm32.c efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val); val 179 drivers/spi/spi-ep93xx.c u32 val = 0; val 183 drivers/spi/spi-ep93xx.c val = ((u16 *)xfer->tx_buf)[espi->tx]; val 187 drivers/spi/spi-ep93xx.c val = ((u8 *)xfer->tx_buf)[espi->tx]; val 190 drivers/spi/spi-ep93xx.c writel(val, espi->mmio + SSPDR); val 197 drivers/spi/spi-ep93xx.c u32 val; val 199 drivers/spi/spi-ep93xx.c val = readl(espi->mmio + SSPDR); val 202 drivers/spi/spi-ep93xx.c ((u16 *)xfer->rx_buf)[espi->rx] = val; val 206 drivers/spi/spi-ep93xx.c ((u8 *)xfer->rx_buf)[espi->rx] = val; val 437 drivers/spi/spi-ep93xx.c u32 val; val 469 drivers/spi/spi-ep93xx.c val = readl(espi->mmio + SSPCR1); val 470 drivers/spi/spi-ep93xx.c val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); val 471 drivers/spi/spi-ep93xx.c writel(val, espi->mmio + SSPCR1); val 483 drivers/spi/spi-ep93xx.c u32 val; val 507 drivers/spi/spi-ep93xx.c val = readl(espi->mmio + SSPCR1); val 508 drivers/spi/spi-ep93xx.c val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); val 509 drivers/spi/spi-ep93xx.c writel(val, espi->mmio + SSPCR1); val 546 drivers/spi/spi-ep93xx.c u32 val; val 553 drivers/spi/spi-ep93xx.c val = readl(espi->mmio + SSPCR1); val 554 drivers/spi/spi-ep93xx.c val |= SSPCR1_SSE; val 555 drivers/spi/spi-ep93xx.c writel(val, espi->mmio + SSPCR1); val 563 drivers/spi/spi-ep93xx.c u32 val; val 565 drivers/spi/spi-ep93xx.c val = readl(espi->mmio + SSPCR1); val 566 drivers/spi/spi-ep93xx.c val &= ~SSPCR1_SSE; val 567 drivers/spi/spi-ep93xx.c writel(val, espi->mmio + SSPCR1); val 106 drivers/spi/spi-falcon.c u32 val; val 174 drivers/spi/spi-falcon.c val = 0; val 179 drivers/spi/spi-falcon.c val = (val << 8) | (*txp++); val 197 drivers/spi/spi-falcon.c ltq_ebu_w32(val, SFADDR); val 201 drivers/spi/spi-falcon.c alen, val, dumlen); val 223 drivers/spi/spi-falcon.c val = 0; val 226 drivers/spi/spi-falcon.c val |= (*txp++) << (8 * len++); val 233 drivers/spi/spi-falcon.c ltq_ebu_w32(val, SFDATA); val 238 drivers/spi/spi-falcon.c val = 0; val 263 drivers/spi/spi-falcon.c val = ltq_ebu_r32(SFSTAT); val 264 drivers/spi/spi-falcon.c if (val & SFSTAT_CMD_ERR) { val 267 drivers/spi/spi-falcon.c dev_err(dev, " (%x)\n", val); val 272 drivers/spi/spi-falcon.c } while (val & SFSTAT_CMD_PEND); val 273 drivers/spi/spi-falcon.c val = ltq_ebu_r32(SFDATA); val 275 drivers/spi/spi-falcon.c *rxp = (val & 0xFF); val 277 drivers/spi/spi-falcon.c val >>= 8; val 289 drivers/spi/spi-falcon.c val = ltq_ebu_r32(SFSTAT); val 290 drivers/spi/spi-falcon.c if (val & SFSTAT_CMD_ERR) { val 292 drivers/spi/spi-falcon.c dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val); val 132 drivers/spi/spi-fsl-espi.c u32 val) val 134 drivers/spi/spi-fsl-espi.c iowrite32be(val, espi->reg_base + offset); val 138 drivers/spi/spi-fsl-espi.c u16 val) val 140 drivers/spi/spi-fsl-espi.c iowrite16be(val, espi->reg_base + offset); val 144 drivers/spi/spi-fsl-espi.c u8 val) val 146 drivers/spi/spi-fsl-espi.c iowrite8(val, espi->reg_base + offset); val 282 drivers/spi/spi-fsl-espi.c u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF); val 285 drivers/spi/spi-fsl-espi.c *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val); val 287 drivers/spi/spi-fsl-espi.c *(u32 *)(rx_buf + espi->rx_pos) = val; val 292 drivers/spi/spi-fsl-espi.c u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF); val 294 drivers/spi/spi-fsl-espi.c *(u16 *)(rx_buf + espi->rx_pos) = swab16(val); val 299 drivers/spi/spi-fsl-espi.c u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF); val 302 drivers/spi/spi-fsl-espi.c *(u8 *)(rx_buf + espi->rx_pos) = val; val 82 drivers/spi/spi-fsl-lib.h static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val) val 84 drivers/spi/spi-fsl-lib.h iowrite32be(val, reg); val 140 drivers/spi/spi-fsl-lpspi.c unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \ val 143 drivers/spi/spi-fsl-lpspi.c *(type *)fsl_lpspi->rx_buf = val; \ val 151 drivers/spi/spi-fsl-lpspi.c type val = 0; \ val 154 drivers/spi/spi-fsl-lpspi.c val = *(type *)fsl_lpspi->tx_buf; \ val 159 drivers/spi/spi-fsl-lpspi.c writel(val, fsl_lpspi->base + IMX7ULP_TDR); \ val 312 drivers/spi/spi-fsl-qspi.c static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) val 315 drivers/spi/spi-fsl-qspi.c iowrite32(val, addr); val 317 drivers/spi/spi-fsl-qspi.c iowrite32be(val, addr); val 420 drivers/spi/spi-fsl-qspi.c u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); val 552 drivers/spi/spi-fsl-qspi.c u32 val; val 555 drivers/spi/spi-fsl-qspi.c memcpy(&val, op->data.buf.out + i, 4); val 556 drivers/spi/spi-fsl-qspi.c val = fsl_qspi_endian_xchg(q, val); val 557 drivers/spi/spi-fsl-qspi.c qspi_writel(q, val, base + QUADSPI_TBDR); val 561 drivers/spi/spi-fsl-qspi.c memcpy(&val, op->data.buf.out + i, op->data.nbytes - i); val 562 drivers/spi/spi-fsl-qspi.c val = fsl_qspi_endian_xchg(q, val); val 563 drivers/spi/spi-fsl-qspi.c qspi_writel(q, val, base + QUADSPI_TBDR); val 578 drivers/spi/spi-fsl-qspi.c u32 val; val 581 drivers/spi/spi-fsl-qspi.c val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); val 582 drivers/spi/spi-fsl-qspi.c val = fsl_qspi_endian_xchg(q, val); val 583 drivers/spi/spi-fsl-qspi.c memcpy(buf + i, &val, 4); val 587 drivers/spi/spi-fsl-qspi.c val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); val 588 drivers/spi/spi-fsl-qspi.c val = fsl_qspi_endian_xchg(q, val); val 589 drivers/spi/spi-fsl-qspi.c memcpy(buf + i, &val, op->data.nbytes - i); val 114 drivers/spi/spi-img-spfi.c static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg) val 116 drivers/spi/spi-img-spfi.c writel(val, spfi->regs + reg); val 121 drivers/spi/spi-img-spfi.c u32 val; val 123 drivers/spi/spi-img-spfi.c val = spfi_readl(spfi, SPFI_CONTROL); val 124 drivers/spi/spi-img-spfi.c val |= SPFI_CONTROL_SPFI_EN; val 125 drivers/spi/spi-img-spfi.c spfi_writel(spfi, val, SPFI_CONTROL); val 416 drivers/spi/spi-img-spfi.c u32 val; val 418 drivers/spi/spi-img-spfi.c val = spfi_readl(spfi, SPFI_PORT_STATE); val 419 drivers/spi/spi-img-spfi.c val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << val 421 drivers/spi/spi-img-spfi.c val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT; val 423 drivers/spi/spi-img-spfi.c val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); val 425 drivers/spi/spi-img-spfi.c val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); val 427 drivers/spi/spi-img-spfi.c val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); val 429 drivers/spi/spi-img-spfi.c val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); val 430 drivers/spi/spi-img-spfi.c spfi_writel(spfi, val, SPFI_PORT_STATE); val 497 drivers/spi/spi-img-spfi.c u32 val, div; val 506 drivers/spi/spi-img-spfi.c val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); val 507 drivers/spi/spi-img-spfi.c val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << val 509 drivers/spi/spi-img-spfi.c val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; val 510 drivers/spi/spi-img-spfi.c spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); val 515 drivers/spi/spi-img-spfi.c val = spfi_readl(spfi, SPFI_CONTROL); val 516 drivers/spi/spi-img-spfi.c val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA); val 518 drivers/spi/spi-img-spfi.c val |= SPFI_CONTROL_SEND_DMA; val 520 drivers/spi/spi-img-spfi.c val |= SPFI_CONTROL_GET_DMA; val 521 drivers/spi/spi-img-spfi.c val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT); val 524 drivers/spi/spi-img-spfi.c val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT; val 527 drivers/spi/spi-img-spfi.c val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; val 528 drivers/spi/spi-img-spfi.c val |= SPFI_CONTROL_SE; val 529 drivers/spi/spi-img-spfi.c spfi_writel(spfi, val, SPFI_CONTROL); val 142 drivers/spi/spi-imx.c unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ val 145 drivers/spi/spi-imx.c *(type *)spi_imx->rx_buf = val; \ val 155 drivers/spi/spi-imx.c type val = 0; \ val 158 drivers/spi/spi-imx.c val = *(type *)spi_imx->tx_buf; \ val 164 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPITXDATA); \ val 284 drivers/spi/spi-imx.c unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); val 293 drivers/spi/spi-imx.c val = cpu_to_be32(val); val 295 drivers/spi/spi-imx.c val = (val << 16) | (val >> 16); val 297 drivers/spi/spi-imx.c *(u32 *)spi_imx->rx_buf = val; val 307 drivers/spi/spi-imx.c u32 val; val 321 drivers/spi/spi-imx.c val = readl(spi_imx->base + MXC_CSPIRXDATA); val 325 drivers/spi/spi-imx.c *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; val 334 drivers/spi/spi-imx.c u32 val = 0; val 340 drivers/spi/spi-imx.c val = *(u32 *)spi_imx->tx_buf; val 349 drivers/spi/spi-imx.c val = cpu_to_be32(val); val 351 drivers/spi/spi-imx.c val = (val << 16) | (val >> 16); val 353 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPITXDATA); val 359 drivers/spi/spi-imx.c u32 val = 0; val 375 drivers/spi/spi-imx.c val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); val 381 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPITXDATA); val 386 drivers/spi/spi-imx.c u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); val 389 drivers/spi/spi-imx.c int n_bytes = spi_imx->slave_burst % sizeof(val); val 392 drivers/spi/spi-imx.c n_bytes = sizeof(val); val 395 drivers/spi/spi-imx.c ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); val 406 drivers/spi/spi-imx.c u32 val = 0; val 407 drivers/spi/spi-imx.c int n_bytes = spi_imx->count % sizeof(val); val 410 drivers/spi/spi-imx.c n_bytes = sizeof(val); val 413 drivers/spi/spi-imx.c memcpy(((u8 *)&val) + sizeof(val) - n_bytes, val 415 drivers/spi/spi-imx.c val = cpu_to_be32(val); val 421 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPITXDATA); val 465 drivers/spi/spi-imx.c unsigned val = 0; val 468 drivers/spi/spi-imx.c val |= MX51_ECSPI_INT_TEEN; val 471 drivers/spi/spi-imx.c val |= MX51_ECSPI_INT_RREN; val 474 drivers/spi/spi-imx.c val |= MX51_ECSPI_INT_RDREN; val 476 drivers/spi/spi-imx.c writel(val, spi_imx->base + MX51_ECSPI_INT); val 671 drivers/spi/spi-imx.c unsigned int val = 0; val 674 drivers/spi/spi-imx.c val |= MX31_INTREG_TEEN; val 676 drivers/spi/spi-imx.c val |= MX31_INTREG_RREN; val 678 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPIINT); val 776 drivers/spi/spi-imx.c unsigned int val = 0; val 779 drivers/spi/spi-imx.c val |= MX21_INTREG_TEEN; val 781 drivers/spi/spi-imx.c val |= MX21_INTREG_RREN; val 783 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPIINT); val 852 drivers/spi/spi-imx.c unsigned int val = 0; val 855 drivers/spi/spi-imx.c val |= MX1_INTREG_TEEN; val 857 drivers/spi/spi-imx.c val |= MX1_INTREG_RREN; val 859 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPIINT); val 35 drivers/spi/spi-iproc-qspi.c u32 val = 0, sts = 0; val 39 drivers/spi/spi-iproc-qspi.c val |= 1UL << i; val 42 drivers/spi/spi-iproc-qspi.c if (val & INTR_MSPI_DONE_MASK) val 45 drivers/spi/spi-iproc-qspi.c if (val & BSPI_LR_INTERRUPTS_ALL) val 48 drivers/spi/spi-iproc-qspi.c if (val & BSPI_LR_INTERRUPTS_ERROR) val 75 drivers/spi/spi-iproc-qspi.c u32 val; val 80 drivers/spi/spi-iproc-qspi.c val = bcm_qspi_readl(priv->big_endian, mmio); val 83 drivers/spi/spi-iproc-qspi.c val = val | (mask << INTR_BASE_BIT_SHIFT); val 85 drivers/spi/spi-iproc-qspi.c val = val & ~(mask << INTR_BASE_BIT_SHIFT); val 87 drivers/spi/spi-iproc-qspi.c bcm_qspi_writel(priv->big_endian, val, mmio); val 194 drivers/spi/spi-lantiq-ssc.c static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val, val 197 drivers/spi/spi-lantiq-ssc.c __raw_writel(val, spi->regbase + reg); val 203 drivers/spi/spi-lantiq-ssc.c u32 val = __raw_readl(spi->regbase + reg); val 205 drivers/spi/spi-lantiq-ssc.c val &= ~clr; val 206 drivers/spi/spi-lantiq-ssc.c val |= set; val 207 drivers/spi/spi-lantiq-ssc.c __raw_writel(val, spi->regbase + reg); val 231 drivers/spi/spi-lantiq-ssc.c u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S; val 233 drivers/spi/spi-lantiq-ssc.c val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; val 234 drivers/spi/spi-lantiq-ssc.c lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON); val 239 drivers/spi/spi-lantiq-ssc.c u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S; val 241 drivers/spi/spi-lantiq-ssc.c val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; val 242 drivers/spi/spi-lantiq-ssc.c lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON); val 333 drivers/spi/spi-mem.c tmpbuf[i + 1] = op->addr.val >> val 448 drivers/spi/spi-mem.c op.addr.val = desc->info.offset + offs; val 468 drivers/spi/spi-mem.c op.addr.val = desc->info.offset + offs; val 117 drivers/spi/spi-meson-spicc.c #define writel_bits_relaxed(mask, val, addr) \ val 118 drivers/spi/spi-meson-spicc.c writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) val 72 drivers/spi/spi-mt7621.c static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val) val 74 drivers/spi/spi-mt7621.c iowrite32(val, rs->base + reg); val 171 drivers/spi/spi-mt7621.c u32 val = (min(tx_len, 4) * 8) << 24; val 175 drivers/spi/spi-mt7621.c val |= (tx_len - 4) * 8; val 176 drivers/spi/spi-mt7621.c val |= (rx * 8) << 12; val 177 drivers/spi/spi-mt7621.c mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val); val 181 drivers/spi/spi-mt7621.c val = mt7621_spi_read(rs, MT7621_SPI_TRANS); val 182 drivers/spi/spi-mt7621.c val |= SPI_CTL_START; val 183 drivers/spi/spi-mt7621.c mt7621_spi_write(rs, MT7621_SPI_TRANS, val); val 189 drivers/spi/spi-mt7621.c val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i); val 190 drivers/spi/spi-mt7621.c *buf++ = val & 0xff; val 191 drivers/spi/spi-mt7621.c val >>= 8; val 207 drivers/spi/spi-mt7621.c int val = 0; val 210 drivers/spi/spi-mt7621.c val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3)); val 212 drivers/spi/spi-mt7621.c val <<= (4 - len) * 8; val 213 drivers/spi/spi-mt7621.c val = swab32(val); val 224 drivers/spi/spi-mt7621.c val |= *buf++ << (8 * (len & 3)); val 229 drivers/spi/spi-mt7621.c val = swab32(val); val 230 drivers/spi/spi-mt7621.c mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val); val 231 drivers/spi/spi-mt7621.c val = 0; val 238 drivers/spi/spi-mt7621.c val = swab32(val); val 239 drivers/spi/spi-mt7621.c val >>= (4 - len) * 8; val 241 drivers/spi/spi-mt7621.c mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val); val 401 drivers/spi/spi-mxic.c addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); val 323 drivers/spi/spi-npcm-fiu.c u32 val; val 353 drivers/spi/spi-npcm-fiu.c ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, val 354 drivers/spi/spi-npcm-fiu.c (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0, val 377 drivers/spi/spi-npcm-fiu.c u32 val; val 402 drivers/spi/spi-npcm-fiu.c regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val); val 414 drivers/spi/spi-npcm-fiu.c return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, val 415 drivers/spi/spi-npcm-fiu.c (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0, val 480 drivers/spi/spi-npcm-fiu.c addr = ((u32)op->addr.val + i); val 535 drivers/spi/spi-npcm-fiu.c op->dummy.buswidth, op->data.buswidth, op->addr.val, val 553 drivers/spi/spi-npcm-fiu.c ret = npcm_fiu_uma_read(mem, op, op->addr.val, false, val 565 drivers/spi/spi-npcm-fiu.c u32 addr = op->addr.val; val 75 drivers/spi/spi-npcm-pspi.c u16 val; val 77 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_CTL1); val 78 drivers/spi/spi-npcm-pspi.c val |= mask; val 79 drivers/spi/spi-npcm-pspi.c iowrite16(val, priv->base + NPCM_PSPI_CTL1); val 84 drivers/spi/spi-npcm-pspi.c u16 val; val 86 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_CTL1); val 87 drivers/spi/spi-npcm-pspi.c val &= ~mask; val 88 drivers/spi/spi-npcm-pspi.c iowrite16(val, priv->base + NPCM_PSPI_CTL1); val 93 drivers/spi/spi-npcm-pspi.c u16 val; val 95 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_CTL1); val 96 drivers/spi/spi-npcm-pspi.c val |= NPCM_PSPI_CTL1_SPIEN; val 97 drivers/spi/spi-npcm-pspi.c iowrite16(val, priv->base + NPCM_PSPI_CTL1); val 102 drivers/spi/spi-npcm-pspi.c u16 val; val 104 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_CTL1); val 105 drivers/spi/spi-npcm-pspi.c val &= ~NPCM_PSPI_CTL1_SPIEN; val 106 drivers/spi/spi-npcm-pspi.c iowrite16(val, priv->base + NPCM_PSPI_CTL1); val 223 drivers/spi/spi-npcm-pspi.c u16 val; val 233 drivers/spi/spi-npcm-pspi.c val = ioread8(priv->base + NPCM_PSPI_DATA); val 236 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_DATA); val 243 drivers/spi/spi-npcm-pspi.c *priv->rx_buf = val; val 296 drivers/spi/spi-npcm-pspi.c u16 val; val 306 drivers/spi/spi-npcm-pspi.c val = ioread8(NPCM_PSPI_DATA + priv->base); val 348 drivers/spi/spi-nxp-fspi.c static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) val 351 drivers/spi/spi-nxp-fspi.c iowrite32(val, addr); val 353 drivers/spi/spi-nxp-fspi.c iowrite32be(val, addr); val 423 drivers/spi/spi-nxp-fspi.c if (op->addr.val >= f->memmap_phy_size) val 649 drivers/spi/spi-nxp-fspi.c memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len); val 762 drivers/spi/spi-nxp-fspi.c fspi_writel(f, op->addr.val, base + FSPI_IPCR0); val 207 drivers/spi/spi-oc-tiny.c u32 val; val 225 drivers/spi/spi-oc-tiny.c if (!of_property_read_u32(np, "clock-frequency", &val)) val 226 drivers/spi/spi-oc-tiny.c hw->freq = val; val 227 drivers/spi/spi-oc-tiny.c if (!of_property_read_u32(np, "baud-width", &val)) val 228 drivers/spi/spi-oc-tiny.c hw->baudwidth = val; val 83 drivers/spi/spi-omap-100k.c unsigned int val; val 87 drivers/spi/spi-omap-100k.c val = readw(spi100k->base + SPI_SETUP1); val 88 drivers/spi/spi-omap-100k.c val |= SPI_SETUP1_CLOCK_ENABLE; val 89 drivers/spi/spi-omap-100k.c writew(val, spi100k->base + SPI_SETUP1); val 94 drivers/spi/spi-omap-100k.c unsigned int val; val 98 drivers/spi/spi-omap-100k.c val = readw(spi100k->base + SPI_SETUP1); val 99 drivers/spi/spi-omap-100k.c val &= ~SPI_SETUP1_CLOCK_ENABLE; val 100 drivers/spi/spi-omap-100k.c writew(val, spi100k->base + SPI_SETUP1); val 108 drivers/spi/spi-omap-uwire.c static inline void uwire_write_reg(int idx, u16 val) val 110 drivers/spi/spi-omap-uwire.c __raw_writew(val, uwire_base + (idx << uwire_idx_shift)); val 120 drivers/spi/spi-omap-uwire.c u16 w, val = 0; val 124 drivers/spi/spi-omap-uwire.c val ^= 0x03; val 125 drivers/spi/spi-omap-uwire.c val = flags & 0x3f; val 137 drivers/spi/spi-omap-uwire.c w |= val << shift; val 141 drivers/spi/spi-omap-uwire.c static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch) val 149 drivers/spi/spi-omap-uwire.c if ((w & mask) == val) val 154 drivers/spi/spi-omap-uwire.c __func__, w, mask, val); val 210 drivers/spi/spi-omap-uwire.c u16 val, w; val 229 drivers/spi/spi-omap-uwire.c val = *buf++; val 232 drivers/spi/spi-omap-uwire.c val |= *buf++ << 8; val 235 drivers/spi/spi-omap-uwire.c val <<= 16 - bits; val 239 drivers/spi/spi-omap-uwire.c dev_name(&spi->dev), bits, val); val 244 drivers/spi/spi-omap-uwire.c uwire_write_reg(UWIRE_TDR, val); val 247 drivers/spi/spi-omap-uwire.c val = START | w | (bits << 5); val 249 drivers/spi/spi-omap-uwire.c uwire_write_reg(UWIRE_CSR, val); val 277 drivers/spi/spi-omap-uwire.c val = START | w | (bits << 0); val 278 drivers/spi/spi-omap-uwire.c uwire_write_reg(UWIRE_CSR, val); val 291 drivers/spi/spi-omap-uwire.c val = uwire_read_reg(UWIRE_RDR); val 292 drivers/spi/spi-omap-uwire.c val &= (1 << bits) - 1; val 293 drivers/spi/spi-omap-uwire.c *buf++ = (u8) val; val 295 drivers/spi/spi-omap-uwire.c *buf++ = val >> 8; val 299 drivers/spi/spi-omap-uwire.c dev_name(&spi->dev), bits, val); val 546 drivers/spi/spi-omap-uwire.c int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000; val 547 drivers/spi/spi-omap-uwire.c omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9); val 146 drivers/spi/spi-omap2-mcspi.c int idx, u32 val) val 150 drivers/spi/spi-omap2-mcspi.c writel_relaxed(val, mcspi->base + idx); val 161 drivers/spi/spi-omap2-mcspi.c int idx, u32 val) val 165 drivers/spi/spi-omap2-mcspi.c writel_relaxed(val, cs->base + idx); val 182 drivers/spi/spi-omap2-mcspi.c static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) val 186 drivers/spi/spi-omap2-mcspi.c cs->chconf0 = val; val 187 drivers/spi/spi-omap2-mcspi.c mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); val 351 drivers/spi/spi-omap2-mcspi.c u32 val; val 353 drivers/spi/spi-omap2-mcspi.c return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC); val 115 drivers/spi/spi-orion.c u32 val; val 117 drivers/spi/spi-orion.c val = readl(reg_addr); val 118 drivers/spi/spi-orion.c val |= mask; val 119 drivers/spi/spi-orion.c writel(val, reg_addr); val 126 drivers/spi/spi-orion.c u32 val; val 128 drivers/spi/spi-orion.c val = readl(reg_addr); val 129 drivers/spi/spi-orion.c val &= ~mask; val 130 drivers/spi/spi-orion.c writel(val, reg_addr); val 167 drivers/spi/spi-pic32-sqi.c u32 val, div; val 173 drivers/spi/spi-pic32-sqi.c val = readl(sqi->regs + PESQI_CLK_CTRL_REG); val 175 drivers/spi/spi-pic32-sqi.c val &= ~(PESQI_CLK_STABLE | (PESQI_CLKDIV << PESQI_CLKDIV_SHIFT)); val 176 drivers/spi/spi-pic32-sqi.c val |= div << PESQI_CLKDIV_SHIFT; val 177 drivers/spi/spi-pic32-sqi.c writel(val, sqi->regs + PESQI_CLK_CTRL_REG); val 180 drivers/spi/spi-pic32-sqi.c return readl_poll_timeout(sqi->regs + PESQI_CLK_CTRL_REG, val, val 181 drivers/spi/spi-pic32-sqi.c val & PESQI_CLK_STABLE, 1, 5000); val 348 drivers/spi/spi-pic32-sqi.c u32 val; val 371 drivers/spi/spi-pic32-sqi.c val = readl(sqi->regs + PESQI_CONF_REG); val 372 drivers/spi/spi-pic32-sqi.c val &= ~(PESQI_CPOL | PESQI_CPHA | PESQI_LSBF); val 374 drivers/spi/spi-pic32-sqi.c val |= PESQI_CPOL; val 376 drivers/spi/spi-pic32-sqi.c val |= PESQI_LSBF; val 377 drivers/spi/spi-pic32-sqi.c val |= PESQI_CPHA; val 378 drivers/spi/spi-pic32-sqi.c writel(val, sqi->regs + PESQI_CONF_REG); val 409 drivers/spi/spi-pic32-sqi.c val = PESQI_DMA_EN | PESQI_POLL_EN | PESQI_BDP_START; val 410 drivers/spi/spi-pic32-sqi.c writel(val, sqi->regs + PESQI_BD_CTRL_REG); val 510 drivers/spi/spi-pic32-sqi.c u32 val; val 522 drivers/spi/spi-pic32-sqi.c readl_poll_timeout_atomic(sqi->regs + PESQI_CONF_REG, val, val 523 drivers/spi/spi-pic32-sqi.c !(val & PESQI_SOFT_RESET), 1, 5000); val 532 drivers/spi/spi-pic32-sqi.c val = readl(sqi->regs + PESQI_CMD_THRES_REG); val 533 drivers/spi/spi-pic32-sqi.c val &= ~(PESQI_TXTHR_MASK << PESQI_TXTHR_SHIFT); val 534 drivers/spi/spi-pic32-sqi.c val &= ~(PESQI_RXTHR_MASK << PESQI_RXTHR_SHIFT); val 535 drivers/spi/spi-pic32-sqi.c val |= (1U << PESQI_TXTHR_SHIFT) | (1U << PESQI_RXTHR_SHIFT); val 536 drivers/spi/spi-pic32-sqi.c writel(val, sqi->regs + PESQI_CMD_THRES_REG); val 538 drivers/spi/spi-pic32-sqi.c val = readl(sqi->regs + PESQI_INT_THRES_REG); val 539 drivers/spi/spi-pic32-sqi.c val &= ~(PESQI_TXTHR_MASK << PESQI_TXTHR_SHIFT); val 540 drivers/spi/spi-pic32-sqi.c val &= ~(PESQI_RXTHR_MASK << PESQI_RXTHR_SHIFT); val 541 drivers/spi/spi-pic32-sqi.c val |= (1U << PESQI_TXTHR_SHIFT) | (1U << PESQI_RXTHR_SHIFT); val 542 drivers/spi/spi-pic32-sqi.c writel(val, sqi->regs + PESQI_INT_THRES_REG); val 545 drivers/spi/spi-pic32-sqi.c val = readl(sqi->regs + PESQI_CONF_REG); val 548 drivers/spi/spi-pic32-sqi.c val &= ~PESQI_MODE; val 549 drivers/spi/spi-pic32-sqi.c val |= PESQI_MODE_DMA << PESQI_MODE_SHIFT; val 550 drivers/spi/spi-pic32-sqi.c writel(val, sqi->regs + PESQI_CONF_REG); val 553 drivers/spi/spi-pic32-sqi.c val |= PESQI_QUAD_LANE << PESQI_LANES_SHIFT; val 556 drivers/spi/spi-pic32-sqi.c val |= PESQI_BURST_EN; val 559 drivers/spi/spi-pic32-sqi.c val |= 3U << PESQI_CSEN_SHIFT; val 560 drivers/spi/spi-pic32-sqi.c writel(val, sqi->regs + PESQI_CONF_REG); val 448 drivers/spi/spi-pic32.c u32 val; val 464 drivers/spi/spi-pic32.c val = readl(&pic32s->regs->ctrl); val 467 drivers/spi/spi-pic32.c val |= CTRL_CKP; val 469 drivers/spi/spi-pic32.c val &= ~CTRL_CKP; val 472 drivers/spi/spi-pic32.c val &= ~CTRL_CKE; val 474 drivers/spi/spi-pic32.c val |= CTRL_CKE; val 477 drivers/spi/spi-pic32.c val |= CTRL_SMP; val 478 drivers/spi/spi-pic32.c writel(val, &pic32s->regs->ctrl); val 43 drivers/spi/spi-pl022.c #define SSP_WRITE_BITS(reg, val, mask, sb) \ val 44 drivers/spi/spi-pl022.c ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) val 51 drivers/spi/spi-pl022.c #define GEN_MASK_BITS(val, mask, sb) \ val 52 drivers/spi/spi-pl022.c (((val)<<(sb)) & (mask)) val 97 drivers/spi/spi-pxa2xx.h unsigned reg, u32 val) val 99 drivers/spi/spi-pxa2xx.h __raw_writel(val, drv_data->ioaddr + reg); val 116 drivers/spi/spi-pxa2xx.h static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) val 120 drivers/spi/spi-pxa2xx.h val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK; val 122 drivers/spi/spi-pxa2xx.h pxa2xx_spi_write(drv_data, SSSR, val); val 977 drivers/spi/spi-qup.c static void spi_qup_set_cs(struct spi_device *spi, bool val) val 986 drivers/spi/spi-qup.c if (!val) val 381 drivers/spi/spi-rspi.c static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) val 387 drivers/spi/spi-rspi.c data |= (val & mask); val 195 drivers/spi/spi-s3c64xx.c u32 val; val 199 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_CH_CFG); val 200 drivers/spi/spi-s3c64xx.c val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); val 201 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_CH_CFG); val 203 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_CH_CFG); val 204 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_CH_SW_RST; val 205 drivers/spi/spi-s3c64xx.c val &= ~S3C64XX_SPI_CH_HS_EN; val 206 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_CH_CFG); val 211 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_STATUS); val 212 drivers/spi/spi-s3c64xx.c } while (TX_FIFO_LVL(val, sdd) && loops--); val 220 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_STATUS); val 221 drivers/spi/spi-s3c64xx.c if (RX_FIFO_LVL(val, sdd)) val 230 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_CH_CFG); val 231 drivers/spi/spi-s3c64xx.c val &= ~S3C64XX_SPI_CH_SW_RST; val 232 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_CH_CFG); val 234 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_MODE_CFG); val 235 drivers/spi/spi-s3c64xx.c val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); val 236 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_MODE_CFG); val 425 drivers/spi/spi-s3c64xx.c unsigned long val = 1; val 432 drivers/spi/spi-s3c64xx.c val = msecs_to_loops(timeout_ms); val 436 drivers/spi/spi-s3c64xx.c } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); val 446 drivers/spi/spi-s3c64xx.c unsigned long val; val 454 drivers/spi/spi-s3c64xx.c val = msecs_to_jiffies(ms) + 10; val 455 drivers/spi/spi-s3c64xx.c val = wait_for_completion_timeout(&sdd->xfer_completion, val); val 466 drivers/spi/spi-s3c64xx.c if (val && !xfer->rx_buf) { val 467 drivers/spi/spi-s3c64xx.c val = msecs_to_loops(10); val 471 drivers/spi/spi-s3c64xx.c && --val) { val 479 drivers/spi/spi-s3c64xx.c if (!val) val 489 drivers/spi/spi-s3c64xx.c unsigned long val; val 500 drivers/spi/spi-s3c64xx.c val = msecs_to_loops(ms); val 503 drivers/spi/spi-s3c64xx.c } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); val 505 drivers/spi/spi-s3c64xx.c if (!val) val 554 drivers/spi/spi-s3c64xx.c u32 val; val 558 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_CLK_CFG); val 559 drivers/spi/spi-s3c64xx.c val &= ~S3C64XX_SPI_ENCLK_ENABLE; val 560 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_CLK_CFG); val 564 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_CH_CFG); val 565 drivers/spi/spi-s3c64xx.c val &= ~(S3C64XX_SPI_CH_SLAVE | val 570 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_CPOL_L; val 573 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_CPHA_B; val 575 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_CH_CFG); val 578 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_MODE_CFG); val 579 drivers/spi/spi-s3c64xx.c val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK val 584 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; val 585 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; val 588 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; val 589 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; val 592 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; val 593 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; val 597 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_MODE_CFG); val 604 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_CLK_CFG); val 605 drivers/spi/spi-s3c64xx.c val &= ~S3C64XX_SPI_PSR_MASK; val 606 drivers/spi/spi-s3c64xx.c val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) val 608 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_CLK_CFG); val 611 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_CLK_CFG); val 612 drivers/spi/spi-s3c64xx.c val |= S3C64XX_SPI_ENCLK_ENABLE; val 613 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_CLK_CFG); val 898 drivers/spi/spi-s3c64xx.c unsigned int val, clr = 0; val 900 drivers/spi/spi-s3c64xx.c val = readl(sdd->regs + S3C64XX_SPI_STATUS); val 902 drivers/spi/spi-s3c64xx.c if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { val 906 drivers/spi/spi-s3c64xx.c if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { val 910 drivers/spi/spi-s3c64xx.c if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { val 914 drivers/spi/spi-s3c64xx.c if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { val 930 drivers/spi/spi-s3c64xx.c unsigned int val; val 949 drivers/spi/spi-s3c64xx.c val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | val 953 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_PENDING_CLR); val 958 drivers/spi/spi-s3c64xx.c val = readl(regs + S3C64XX_SPI_MODE_CFG); val 959 drivers/spi/spi-s3c64xx.c val &= ~S3C64XX_SPI_MODE_4BURST; val 960 drivers/spi/spi-s3c64xx.c val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); val 961 drivers/spi/spi-s3c64xx.c val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); val 962 drivers/spi/spi-s3c64xx.c writel(val, regs + S3C64XX_SPI_MODE_CFG); val 282 drivers/spi/spi-sc18is602.c const __be32 *val; val 285 drivers/spi/spi-sc18is602.c val = of_get_property(np, "clock-frequency", &len); val 286 drivers/spi/spi-sc18is602.c if (val && len >= sizeof(__be32)) val 287 drivers/spi/spi-sc18is602.c hw->freq = be32_to_cpup(val); val 46 drivers/spi/spi-sh-hspi.c static void hspi_write(struct hspi_priv *hspi, int reg, u32 val) val 48 drivers/spi/spi-sh-hspi.c iowrite32(val, hspi->addr + reg); val 58 drivers/spi/spi-sh-hspi.c u32 val = hspi_read(hspi, reg); val 60 drivers/spi/spi-sh-hspi.c val &= ~mask; val 61 drivers/spi/spi-sh-hspi.c val |= set & mask; val 63 drivers/spi/spi-sh-hspi.c hspi_write(hspi, reg, val); val 69 drivers/spi/spi-sh-hspi.c static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val) val 74 drivers/spi/spi-sh-hspi.c if ((mask & hspi_read(hspi, SPSR)) == val) val 323 drivers/spi/spi-sh-msiof.c u32 val; val 340 drivers/spi/spi-sh-msiof.c val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT; val 341 drivers/spi/spi-sh-msiof.c val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT; val 343 drivers/spi/spi-sh-msiof.c return val; val 28 drivers/spi/spi-sh-sci.c unsigned char val; val 50 drivers/spi/spi-sh-sci.c sp->val |= bits; val 52 drivers/spi/spi-sh-sci.c sp->val &= ~bits; val 54 drivers/spi/spi-sh-sci.c iowrite8(sp->val, SCSPTR(sp)); val 159 drivers/spi/spi-sh-sci.c sp->val = ioread8(SCSPTR(sp)); val 103 drivers/spi/spi-sh.c static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val, val 109 drivers/spi/spi-sh.c tmp |= val; val 113 drivers/spi/spi-sh.c static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val, val 119 drivers/spi/spi-sh.c tmp &= ~val; val 140 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(s, val) \ val 141 drivers/spi/spi-sirf.c ((val) & (s)->fifo_level_chk_mask) val 167 drivers/spi/spi-sprd-adi.c u32 val, rd_addr; val 193 drivers/spi/spi-sprd-adi.c val = readl_relaxed(sadi->base + REG_ADI_RD_DATA); val 194 drivers/spi/spi-sprd-adi.c if (!(val & BIT_RD_CMD_BUSY)) val 212 drivers/spi/spi-sprd-adi.c rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT; val 216 drivers/spi/spi-sprd-adi.c reg_paddr, val); val 221 drivers/spi/spi-sprd-adi.c *read_val = val & RD_VALUE_MASK; val 229 drivers/spi/spi-sprd-adi.c static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val) val 256 drivers/spi/spi-sprd-adi.c writel_relaxed(val, (void __iomem *)reg); val 279 drivers/spi/spi-sprd-adi.c u32 phy_reg, val; val 289 drivers/spi/spi-sprd-adi.c ret = sprd_adi_read(sadi, phy_reg, &val); val 293 drivers/spi/spi-sprd-adi.c *(u32 *)t->rx_buf = val; val 307 drivers/spi/spi-sprd-adi.c val = *p; val 308 drivers/spi/spi-sprd-adi.c ret = sprd_adi_write(sadi, phy_reg, val); val 322 drivers/spi/spi-sprd-adi.c u32 val; val 325 drivers/spi/spi-sprd-adi.c sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val); val 326 drivers/spi/spi-sprd-adi.c val |= HWRST_STATUS_WATCHDOG; val 327 drivers/spi/spi-sprd-adi.c sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val); val 336 drivers/spi/spi-sprd-adi.c u32 val, reboot_mode = 0; val 368 drivers/spi/spi-sprd-adi.c sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val); val 369 drivers/spi/spi-sprd-adi.c val &= ~HWRST_STATUS_WATCHDOG; val 370 drivers/spi/spi-sprd-adi.c val |= reboot_mode; val 371 drivers/spi/spi-sprd-adi.c sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val); val 374 drivers/spi/spi-sprd-adi.c sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val); val 375 drivers/spi/spi-sprd-adi.c val |= BIT_WDG_EN; val 376 drivers/spi/spi-sprd-adi.c sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val); val 379 drivers/spi/spi-sprd-adi.c sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val); val 380 drivers/spi/spi-sprd-adi.c val |= BIT_WDG_EN; val 381 drivers/spi/spi-sprd-adi.c sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val); val 392 drivers/spi/spi-sprd-adi.c sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val); val 393 drivers/spi/spi-sprd-adi.c val |= BIT_WDG_RUN | BIT_WDG_RST; val 394 drivers/spi/spi-sprd-adi.c sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val); val 196 drivers/spi/spi-sprd.c u32 val, us; val 200 drivers/spi/spi-sprd.c ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, val 201 drivers/spi/spi-sprd.c val & SPRD_SPI_TX_END_IRQ, 0, us); val 207 drivers/spi/spi-sprd.c ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val, val 208 drivers/spi/spi-sprd.c !(val & SPRD_SPI_TX_BUSY), 0, us); val 221 drivers/spi/spi-sprd.c u32 val, us; val 225 drivers/spi/spi-sprd.c ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, val 226 drivers/spi/spi-sprd.c val & SPRD_SPI_RX_END_IRQ, 0, us); val 249 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1); val 251 drivers/spi/spi-sprd.c val &= ~SPRD_SPI_RTX_MD_MASK; val 252 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL1); val 257 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0); val 260 drivers/spi/spi-sprd.c val &= ~(SPRD_SPI_CHNL_LEN_MASK << SPRD_SPI_CHNL_LEN); val 261 drivers/spi/spi-sprd.c val |= bits << SPRD_SPI_CHNL_LEN; val 262 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL0); val 267 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8); val 270 drivers/spi/spi-sprd.c val &= ~SPRD_SPI_TX_LEN_H_MASK; val 271 drivers/spi/spi-sprd.c val |= length >> SPRD_SPI_TX_LEN_H_OFFSET; val 272 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL8); val 274 drivers/spi/spi-sprd.c val = length & SPRD_SPI_TX_LEN_L_MASK; val 275 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL9); val 280 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10); val 283 drivers/spi/spi-sprd.c val &= ~SPRD_SPI_RX_LEN_H_MASK; val 284 drivers/spi/spi-sprd.c val |= length >> SPRD_SPI_RX_LEN_H_OFFSET; val 285 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL10); val 287 drivers/spi/spi-sprd.c val = length & SPRD_SPI_RX_LEN_L_MASK; val 288 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL11); val 295 drivers/spi/spi-sprd.c u32 val; val 297 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL0); val 300 drivers/spi/spi-sprd.c val &= ~SPRD_SPI_CS0_VALID; val 301 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL0); val 303 drivers/spi/spi-sprd.c val |= SPRD_SPI_CSN_MASK; val 304 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL0); val 310 drivers/spi/spi-sprd.c u32 val; val 313 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL4); val 314 drivers/spi/spi-sprd.c val &= ~(SPRD_SPI_START_RX | SPRD_SPI_ONLY_RECV_MASK); val 315 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL4); val 318 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL4); val 319 drivers/spi/spi-sprd.c val |= len & SPRD_SPI_ONLY_RECV_MASK; val 320 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL4); val 323 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL4); val 324 drivers/spi/spi-sprd.c val |= SPRD_SPI_START_RX; val 325 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL4); val 459 drivers/spi/spi-sprd.c u32 val; val 465 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_INT_EN); val 466 drivers/spi/spi-sprd.c writel_relaxed(val | SPRD_SPI_TX_END_INT_EN | val 478 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2); val 481 drivers/spi/spi-sprd.c val |= SPRD_SPI_DMA_EN; val 483 drivers/spi/spi-sprd.c val &= ~SPRD_SPI_DMA_EN; val 485 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL2); val 675 drivers/spi/spi-sprd.c u32 val; val 677 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL0); val 678 drivers/spi/spi-sprd.c val &= ~(SPRD_SPI_SCK_REV | SPRD_SPI_NG_TX | SPRD_SPI_NG_RX); val 680 drivers/spi/spi-sprd.c val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX; val 681 drivers/spi/spi-sprd.c val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0; val 682 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL0); val 700 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL7); val 701 drivers/spi/spi-sprd.c val &= ~SPRD_SPI_MODE_MASK; val 704 drivers/spi/spi-sprd.c val |= SPRD_SPI_3WIRE_MODE << SPRD_SPI_MODE_OFFSET; val 706 drivers/spi/spi-sprd.c val |= SPRD_SPI_4WIRE_MODE << SPRD_SPI_MODE_OFFSET; val 709 drivers/spi/spi-sprd.c val |= SPRD_SPI_DATA_LINE2_EN; val 711 drivers/spi/spi-sprd.c val &= ~SPRD_SPI_DATA_LINE2_EN; val 713 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL7); val 721 drivers/spi/spi-sprd.c u32 val, mode = 0; val 766 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL1); val 767 drivers/spi/spi-sprd.c val &= ~SPRD_SPI_RTX_MD_MASK; val 773 drivers/spi/spi-sprd.c writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1); val 816 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS); val 818 drivers/spi/spi-sprd.c if (val & SPRD_SPI_MASK_TX_END) { val 826 drivers/spi/spi-sprd.c if (val & SPRD_SPI_MASK_RX_END) { val 142 drivers/spi/spi-stm32-qspi.c static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr) val 144 drivers/spi/spi-stm32-qspi.c *val = readb_relaxed(addr); val 147 drivers/spi/spi-stm32-qspi.c static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr) val 149 drivers/spi/spi-stm32-qspi.c writeb_relaxed(*val, addr); val 155 drivers/spi/spi-stm32-qspi.c void (*tx_fifo)(u8 *val, void __iomem *addr); val 187 drivers/spi/spi-stm32-qspi.c memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val, val 337 drivers/spi/spi-stm32-qspi.c op->addr.val, op->data.nbytes); val 343 drivers/spi/spi-stm32-qspi.c addr_max = op->addr.val + op->data.nbytes + 1; val 390 drivers/spi/spi-stm32-qspi.c writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR); val 234 drivers/spi/spi-synquacer.c u32 rate, val, div; val 275 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_PCC(cs)); val 276 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_PCC_SAFESYNC; val 278 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_SAFESYNC; val 280 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_SAFESYNC; val 282 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_SAFESYNC; val 285 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_CPHA; val 287 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_PCC_CPHA; val 290 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_CPOL; val 292 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_PCC_CPOL; val 295 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_SSPOL; val 297 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_PCC_SSPOL; val 300 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_SDIR; val 302 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_PCC_SDIR; val 305 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_ACES; val 307 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_PCC_ACES; val 310 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_RTM; val 312 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_PCC_RTM; val 314 drivers/spi/spi-synquacer.c val |= (3 << SYNQUACER_HSSPI_PCC_SS2CD_SHIFT); val 315 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_PCC_SENDIAN; val 317 drivers/spi/spi-synquacer.c val &= ~(SYNQUACER_HSSPI_PCC_CDRS_MASK << val 319 drivers/spi/spi-synquacer.c val |= ((div >> 1) << SYNQUACER_HSSPI_PCC_CDRS_SHIFT); val 321 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_PCC(cs)); val 323 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG); val 324 drivers/spi/spi-synquacer.c val &= ~(SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_MASK << val 326 drivers/spi/spi-synquacer.c val |= ((bpw / 8 - 1) << SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_SHIFT); val 327 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG); val 329 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 330 drivers/spi/spi-synquacer.c val &= ~(SYNQUACER_HSSPI_DMTRP_DATA_MASK << val 334 drivers/spi/spi-synquacer.c val |= (SYNQUACER_HSSPI_DMTRP_DATA_RX << val 337 drivers/spi/spi-synquacer.c val |= (SYNQUACER_HSSPI_DMTRP_DATA_TX << val 340 drivers/spi/spi-synquacer.c val &= ~(3 << SYNQUACER_HSSPI_DMTRP_BUS_WIDTH_SHIFT); val 341 drivers/spi/spi-synquacer.c val |= ((bus_width >> 1) << SYNQUACER_HSSPI_DMTRP_BUS_WIDTH_SHIFT); val 342 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 362 drivers/spi/spi-synquacer.c u32 val; val 364 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 365 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_DMSTOP_STOP; val 366 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 368 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG); val 369 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_FIFOCFG_RX_FLUSH; val 370 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_FIFOCFG_TX_FLUSH; val 371 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG); val 431 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG); val 432 drivers/spi/spi-synquacer.c val &= ~(SYNQUACER_HSSPI_FIFOCFG_RX_THRESHOLD_MASK << val 434 drivers/spi/spi-synquacer.c val |= ((sspi->rx_words > SYNQUACER_HSSPI_FIFO_DEPTH ? val 437 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG); val 444 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 445 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_DMSTART_START; val 446 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 449 drivers/spi/spi-synquacer.c val = SYNQUACER_HSSPI_TXE_FIFO_EMPTY; val 450 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_TXE); val 459 drivers/spi/spi-synquacer.c val = SYNQUACER_HSSPI_RXE_FIFO_MORE_THAN_THRESHOLD | val 461 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_RXE); val 467 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 468 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_DMSTOP_STOP; val 469 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 487 drivers/spi/spi-synquacer.c u32 val; val 489 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 490 drivers/spi/spi-synquacer.c val &= ~(SYNQUACER_HSSPI_DMPSEL_CS_MASK << val 492 drivers/spi/spi-synquacer.c val |= spi->chip_select << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT; val 493 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val 499 drivers/spi/spi-synquacer.c u32 val; val 505 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_MCTRL) & val 507 drivers/spi/spi-synquacer.c if (enable && val) val 509 drivers/spi/spi-synquacer.c if (!enable && !val) val 519 drivers/spi/spi-synquacer.c u32 val; val 535 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMCFG); val 536 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_DMCFG_SSDC; val 537 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_DMCFG_MSTARTEN; val 538 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMCFG); val 540 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_MCTRL); val 542 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_MCTRL_CDSS; val 544 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_MCTRL_CDSS; val 546 drivers/spi/spi-synquacer.c val &= ~SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN; val 547 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_MCTRL_MEN; val 548 drivers/spi/spi-synquacer.c val |= SYNQUACER_HSSPI_MCTRL_SYNCON; val 551 drivers/spi/spi-synquacer.c writel(val, sspi->regs + SYNQUACER_HSSPI_REG_MCTRL); val 561 drivers/spi/spi-synquacer.c uint32_t val; val 564 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_RXF); val 565 drivers/spi/spi-synquacer.c if ((val & SYNQUACER_HSSPI_RXF_SLAVE_RELEASED) || val 566 drivers/spi/spi-synquacer.c (val & SYNQUACER_HSSPI_RXF_FIFO_MORE_THAN_THRESHOLD)) { val 581 drivers/spi/spi-synquacer.c uint32_t val; val 584 drivers/spi/spi-synquacer.c val = readl(sspi->regs + SYNQUACER_HSSPI_REG_TXF); val 585 drivers/spi/spi-synquacer.c if (val & SYNQUACER_HSSPI_TXF_FIFO_EMPTY) { val 70 drivers/spi/spi-tegra114.c #define SPI_CS_SETUP_HOLD(reg, cs, val) \ val 71 drivers/spi/spi-tegra114.c ((((val) & 0xFFu) << ((cs) * 8)) | \ val 83 drivers/spi/spi-tegra114.c #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \ val 84 drivers/spi/spi-tegra114.c (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \ val 86 drivers/spi/spi-tegra114.c #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \ val 87 drivers/spi/spi-tegra114.c (reg = (((val) & 0x1F) << ((cs) * 8)) | \ val 93 drivers/spi/spi-tegra114.c #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF) val 94 drivers/spi/spi-tegra114.c #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF) val 109 drivers/spi/spi-tegra114.c #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F) val 110 drivers/spi/spi-tegra114.c #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F) val 234 drivers/spi/spi-tegra114.c u32 val, unsigned long reg) val 236 drivers/spi/spi-tegra114.c writel(val, tspi->base + reg); val 245 drivers/spi/spi-tegra114.c u32 val; val 248 drivers/spi/spi-tegra114.c val = tegra_spi_readl(tspi, SPI_TRANS_STATUS); val 249 drivers/spi/spi-tegra114.c tegra_spi_writel(tspi, val, SPI_TRANS_STATUS); val 252 drivers/spi/spi-tegra114.c val = tegra_spi_readl(tspi, SPI_FIFO_STATUS); val 253 drivers/spi/spi-tegra114.c if (val & SPI_ERR) val 538 drivers/spi/spi-tegra114.c u32 val; val 544 drivers/spi/spi-tegra114.c val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1); val 545 drivers/spi/spi-tegra114.c tegra_spi_writel(tspi, val, SPI_DMA_BLK); val 555 drivers/spi/spi-tegra114.c val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1; val 558 drivers/spi/spi-tegra114.c val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4; val 561 drivers/spi/spi-tegra114.c val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8; val 567 drivers/spi/spi-tegra114.c val |= SPI_IE_TX; val 570 drivers/spi/spi-tegra114.c val |= SPI_IE_RX; val 573 drivers/spi/spi-tegra114.c tegra_spi_writel(tspi, val, SPI_DMA_CTL); val 574 drivers/spi/spi-tegra114.c tspi->dma_control_reg = val; val 622 drivers/spi/spi-tegra114.c tspi->dma_control_reg = val; val 624 drivers/spi/spi-tegra114.c val |= SPI_DMA_EN; val 625 drivers/spi/spi-tegra114.c tegra_spi_writel(tspi, val, SPI_DMA_CTL); val 632 drivers/spi/spi-tegra114.c u32 val; val 640 drivers/spi/spi-tegra114.c val = SPI_DMA_BLK_SET(cur_words - 1); val 641 drivers/spi/spi-tegra114.c tegra_spi_writel(tspi, val, SPI_DMA_BLK); val 643 drivers/spi/spi-tegra114.c val = 0; val 645 drivers/spi/spi-tegra114.c val |= SPI_IE_TX; val 648 drivers/spi/spi-tegra114.c val |= SPI_IE_RX; val 650 drivers/spi/spi-tegra114.c tegra_spi_writel(tspi, val, SPI_DMA_CTL); val 651 drivers/spi/spi-tegra114.c tspi->dma_control_reg = val; val 655 drivers/spi/spi-tegra114.c val = tspi->command1_reg; val 656 drivers/spi/spi-tegra114.c val |= SPI_PIO; val 657 drivers/spi/spi-tegra114.c tegra_spi_writel(tspi, val, SPI_COMMAND1); val 940 drivers/spi/spi-tegra114.c u32 val; val 964 drivers/spi/spi-tegra114.c val = tegra_spi_readl(tspi, SPI_INTR_MASK); val 965 drivers/spi/spi-tegra114.c val &= ~SPI_INTR_ALL_MASK; val 966 drivers/spi/spi-tegra114.c tegra_spi_writel(tspi, val, SPI_INTR_MASK); val 974 drivers/spi/spi-tegra114.c val = tspi->def_command1_reg; val 976 drivers/spi/spi-tegra114.c val &= ~SPI_CS_POL_INACTIVE(spi->chip_select); val 978 drivers/spi/spi-tegra114.c val |= SPI_CS_POL_INACTIVE(spi->chip_select); val 979 drivers/spi/spi-tegra114.c tspi->def_command1_reg = val; val 146 drivers/spi/spi-tegra20-sflash.c u32 val, unsigned long reg) val 148 drivers/spi/spi-tegra20-sflash.c writel(val, tsd->base + reg); val 226 drivers/spi/spi-tegra20-sflash.c u32 val = 0; val 230 drivers/spi/spi-tegra20-sflash.c val |= SPI_IE_TXC; val 233 drivers/spi/spi-tegra20-sflash.c val |= SPI_IE_RXC; val 235 drivers/spi/spi-tegra20-sflash.c tegra_sflash_writel(tsd, val, SPI_DMA_CTL); val 236 drivers/spi/spi-tegra20-sflash.c tsd->dma_control_reg = val; val 242 drivers/spi/spi-tegra20-sflash.c val |= SPI_DMA_BLK_COUNT(cur_words); val 243 drivers/spi/spi-tegra20-sflash.c tegra_sflash_writel(tsd, val, SPI_DMA_CTL); val 244 drivers/spi/spi-tegra20-sflash.c tsd->dma_control_reg = val; val 245 drivers/spi/spi-tegra20-sflash.c val |= SPI_DMA_EN; val 246 drivers/spi/spi-tegra20-sflash.c tegra_sflash_writel(tsd, val, SPI_DMA_CTL); val 76 drivers/spi/spi-tegra20-slink.c #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) val 77 drivers/spi/spi-tegra20-slink.c #define SLINK_WORD(val) (((val) >> 5) & 0x1f) val 78 drivers/spi/spi-tegra20-slink.c #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) val 125 drivers/spi/spi-tegra20-slink.c #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) val 126 drivers/spi/spi-tegra20-slink.c #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) val 127 drivers/spi/spi-tegra20-slink.c #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) val 217 drivers/spi/spi-tegra20-slink.c u32 val, unsigned long reg) val 219 drivers/spi/spi-tegra20-slink.c writel(val, tspi->base + reg); val 474 drivers/spi/spi-tegra20-slink.c u32 val; val 487 drivers/spi/spi-tegra20-slink.c val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); val 488 drivers/spi/spi-tegra20-slink.c val |= tspi->packed_size; val 497 drivers/spi/spi-tegra20-slink.c val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; val 499 drivers/spi/spi-tegra20-slink.c val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; val 501 drivers/spi/spi-tegra20-slink.c val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; val 504 drivers/spi/spi-tegra20-slink.c val |= SLINK_IE_TXC; val 507 drivers/spi/spi-tegra20-slink.c val |= SLINK_IE_RXC; val 509 drivers/spi/spi-tegra20-slink.c tegra_slink_writel(tspi, val, SLINK_DMA_CTL); val 510 drivers/spi/spi-tegra20-slink.c tspi->dma_control_reg = val; val 544 drivers/spi/spi-tegra20-slink.c val |= SLINK_PACKED; val 545 drivers/spi/spi-tegra20-slink.c tegra_slink_writel(tspi, val, SLINK_DMA_CTL); val 549 drivers/spi/spi-tegra20-slink.c tspi->dma_control_reg = val; val 551 drivers/spi/spi-tegra20-slink.c val |= SLINK_DMA_EN; val 552 drivers/spi/spi-tegra20-slink.c tegra_slink_writel(tspi, val, SLINK_DMA_CTL); val 559 drivers/spi/spi-tegra20-slink.c u32 val; val 562 drivers/spi/spi-tegra20-slink.c val = tspi->packed_size; val 564 drivers/spi/spi-tegra20-slink.c val |= SLINK_IE_TXC; val 567 drivers/spi/spi-tegra20-slink.c val |= SLINK_IE_RXC; val 569 drivers/spi/spi-tegra20-slink.c tegra_slink_writel(tspi, val, SLINK_DMA_CTL); val 570 drivers/spi/spi-tegra20-slink.c tspi->dma_control_reg = val; val 576 drivers/spi/spi-tegra20-slink.c val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); val 577 drivers/spi/spi-tegra20-slink.c tegra_slink_writel(tspi, val, SLINK_DMA_CTL); val 578 drivers/spi/spi-tegra20-slink.c tspi->dma_control_reg = val; val 582 drivers/spi/spi-tegra20-slink.c val |= SLINK_PACKED; val 583 drivers/spi/spi-tegra20-slink.c tegra_slink_writel(tspi, val, SLINK_DMA_CTL); val 587 drivers/spi/spi-tegra20-slink.c tspi->dma_control_reg = val; val 588 drivers/spi/spi-tegra20-slink.c val |= SLINK_DMA_EN; val 589 drivers/spi/spi-tegra20-slink.c tegra_slink_writel(tspi, val, SLINK_DMA_CTL); val 747 drivers/spi/spi-tegra20-slink.c u32 val; val 764 drivers/spi/spi-tegra20-slink.c val = tspi->def_command_reg; val 766 drivers/spi/spi-tegra20-slink.c val |= cs_pol_bit[spi->chip_select]; val 768 drivers/spi/spi-tegra20-slink.c val &= ~cs_pol_bit[spi->chip_select]; val 769 drivers/spi/spi-tegra20-slink.c tspi->def_command_reg = val; val 137 drivers/spi/spi-ti-qspi.c unsigned long val, unsigned long reg) val 139 drivers/spi/spi-ti-qspi.c writel(val, qspi->base + reg); val 543 drivers/spi/spi-ti-qspi.c from = op->addr.val; val 153 drivers/spi/spi-tle62x0.c unsigned long val; val 156 drivers/spi/spi-tle62x0.c val = simple_strtoul(buf, &endp, 0); val 160 drivers/spi/spi-tle62x0.c dev_dbg(dev, "setting gpio %d to %ld\n", gpio_num, val); val 164 drivers/spi/spi-tle62x0.c if (val) val 218 drivers/spi/spi-topcliff-pch.c static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val) val 221 drivers/spi/spi-topcliff-pch.c iowrite32(val, (data->io_remap_addr + idx)); val 90 drivers/spi/spi-txx9.c static void txx9spi_wr(struct txx9spi *c, u32 val, int reg) val 92 drivers/spi/spi-txx9.c __raw_writel(val, c->membase + reg); val 98 drivers/spi/spi-txx9.c int val = (spi->mode & SPI_CS_HIGH) ? on : !on; val 106 drivers/spi/spi-txx9.c c->last_chipselect_val = val; val 111 drivers/spi/spi-txx9.c gpio_set_value(spi->chip_select, val); val 99 drivers/spi/spi-uniphier.c u32 val; val 101 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_IE); val 102 drivers/spi/spi-uniphier.c val |= mask; val 103 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_IE); val 109 drivers/spi/spi-uniphier.c u32 val; val 111 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_IE); val 112 drivers/spi/spi-uniphier.c val &= ~mask; val 113 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_IE); val 172 drivers/spi/spi-uniphier.c u32 val; val 174 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_TXWDS); val 175 drivers/spi/spi-uniphier.c val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK); val 176 drivers/spi/spi-uniphier.c val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size); val 177 drivers/spi/spi-uniphier.c val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size); val 178 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_TXWDS); val 180 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_RXWDS); val 181 drivers/spi/spi-uniphier.c val &= ~SSI_RXWDS_DTLEN_MASK; val 182 drivers/spi/spi-uniphier.c val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size); val 183 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_RXWDS); val 190 drivers/spi/spi-uniphier.c u32 val, ckdiv; val 199 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_CKS); val 200 drivers/spi/spi-uniphier.c val &= ~SSI_CKS_CKRAT_MASK; val 201 drivers/spi/spi-uniphier.c val |= ckdiv & SSI_CKS_CKRAT_MASK; val 202 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_CKS); val 209 drivers/spi/spi-uniphier.c u32 val; val 235 drivers/spi/spi-uniphier.c val = SSI_FC_TXFFL | SSI_FC_RXFFL; val 236 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_FC); val 242 drivers/spi/spi-uniphier.c u32 val = 0; val 250 drivers/spi/spi-uniphier.c val = *priv->tx_buf; val 253 drivers/spi/spi-uniphier.c val = get_unaligned_le16(priv->tx_buf); val 256 drivers/spi/spi-uniphier.c val = get_unaligned_le32(priv->tx_buf); val 263 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_TXDR); val 269 drivers/spi/spi-uniphier.c u32 val; val 274 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_RXDR); val 279 drivers/spi/spi-uniphier.c *priv->rx_buf = val; val 282 drivers/spi/spi-uniphier.c put_unaligned_le16(val, priv->rx_buf); val 285 drivers/spi/spi-uniphier.c put_unaligned_le32(val, priv->rx_buf); val 296 drivers/spi/spi-uniphier.c u32 val; val 298 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_FC); val 299 drivers/spi/spi-uniphier.c val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK); val 300 drivers/spi/spi-uniphier.c val |= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold); val 301 drivers/spi/spi-uniphier.c val |= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold); val 302 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_FC); val 325 drivers/spi/spi-uniphier.c u32 val; val 327 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_FPS); val 330 drivers/spi/spi-uniphier.c val |= SSI_FPS_FSPOL; val 332 drivers/spi/spi-uniphier.c val &= ~SSI_FPS_FSPOL; val 334 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_FPS); val 438 drivers/spi/spi-uniphier.c u32 val, stat; val 441 drivers/spi/spi-uniphier.c val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC; val 442 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_IC); val 96 drivers/spi/spi-xilinx.c static void xspi_write32(u32 val, void __iomem *addr) val 98 drivers/spi/spi-xilinx.c iowrite32(val, addr); val 106 drivers/spi/spi-xilinx.c static void xspi_write32_be(u32 val, void __iomem *addr) val 108 drivers/spi/spi-xilinx.c iowrite32be(val, addr); val 112 drivers/spi/spi-xlp.c int regoff, u32 val) val 114 drivers/spi/spi-xlp.c writel(val, priv->base + regoff + cs * SPI_CS_OFFSET); val 118 drivers/spi/spi-xlp.c int regoff, u32 val) val 120 drivers/spi/spi-xlp.c writel(val, priv->base + regoff); val 32 drivers/spi/spi-xtensa-xtfpga.c unsigned addr, u32 val) val 34 drivers/spi/spi-xtensa-xtfpga.c __raw_writel(val, spi->regs + addr); val 156 drivers/spi/spi-zynq-qspi.c u32 val) val 158 drivers/spi/spi-zynq-qspi.c writel_relaxed(val, xqspi->regs + offset); val 543 drivers/spi/spi-zynq-qspi.c xqspi->txbuf[i] = op->addr.val >> val 193 drivers/spi/spi-zynqmp-gqspi.c u32 val) val 195 drivers/spi/spi-zynqmp-gqspi.c writel_relaxed(val, (xqspi->regs + offset)); val 202 drivers/spmi/spmi-pmic-arb.c u32 offset, u32 val) val 204 drivers/spmi/spmi-pmic-arb.c writel_relaxed(val, pmic_arb->wr_base + offset); val 208 drivers/spmi/spmi-pmic-arb.c u32 offset, u32 val) val 210 drivers/spmi/spmi-pmic-arb.c writel_relaxed(val, pmic_arb->rd_base + offset); val 111 drivers/ssb/driver_gige.c int reg, int size, u32 *val) val 124 drivers/ssb/driver_gige.c *val = gige_pcicfg_read8(dev, reg); val 127 drivers/ssb/driver_gige.c *val = gige_pcicfg_read16(dev, reg); val 130 drivers/ssb/driver_gige.c *val = gige_pcicfg_read32(dev, reg); val 141 drivers/ssb/driver_gige.c int reg, int size, u32 val) val 154 drivers/ssb/driver_gige.c gige_pcicfg_write8(dev, reg, val); val 157 drivers/ssb/driver_gige.c gige_pcicfg_write16(dev, reg, val); val 160 drivers/ssb/driver_gige.c gige_pcicfg_write32(dev, reg, val); val 109 drivers/ssb/driver_gpio.c u32 val = ssb_chipco_gpio_in(&bus->chipco, BIT(gpio)); val 111 drivers/ssb/driver_gpio.c ssb_chipco_gpio_polarity(&bus->chipco, BIT(gpio), val); val 125 drivers/ssb/driver_gpio.c u32 val = chipco_read32(chipco, SSB_CHIPCO_GPIOIN); val 128 drivers/ssb/driver_gpio.c unsigned long irqs = (val ^ pol) & mask; val 136 drivers/ssb/driver_gpio.c ssb_chipco_gpio_polarity(chipco, irqs, val & irqs); val 306 drivers/ssb/driver_gpio.c u32 val = ssb_extif_gpio_in(&bus->extif, BIT(gpio)); val 308 drivers/ssb/driver_gpio.c ssb_extif_gpio_polarity(&bus->extif, BIT(gpio), val); val 322 drivers/ssb/driver_gpio.c u32 val = ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN); val 325 drivers/ssb/driver_gpio.c unsigned long irqs = (val ^ pol) & mask; val 333 drivers/ssb/driver_gpio.c ssb_extif_gpio_polarity(extif, irqs, val & irqs); val 59 drivers/ssb/driver_pcicore.c #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) val 115 drivers/ssb/driver_pcicore.c u32 addr, val; val 129 drivers/ssb/driver_pcicore.c if (mips_busprobe32(val, mmio)) { val 130 drivers/ssb/driver_pcicore.c val = 0xffffffff; val 134 drivers/ssb/driver_pcicore.c val = readl(mmio); val 135 drivers/ssb/driver_pcicore.c val >>= (8 * (off & 3)); val 139 drivers/ssb/driver_pcicore.c *((u8 *)buf) = (u8)val; val 142 drivers/ssb/driver_pcicore.c *((u16 *)buf) = (u16)val; val 145 drivers/ssb/driver_pcicore.c *((u32 *)buf) = (u32)val; val 161 drivers/ssb/driver_pcicore.c u32 addr, val = 0; val 175 drivers/ssb/driver_pcicore.c if (mips_busprobe32(val, mmio)) { val 176 drivers/ssb/driver_pcicore.c val = 0xffffffff; val 182 drivers/ssb/driver_pcicore.c val = readl(mmio); val 183 drivers/ssb/driver_pcicore.c val &= ~(0xFF << (8 * (off & 3))); val 184 drivers/ssb/driver_pcicore.c val |= *((const u8 *)buf) << (8 * (off & 3)); val 187 drivers/ssb/driver_pcicore.c val = readl(mmio); val 188 drivers/ssb/driver_pcicore.c val &= ~(0xFFFF << (8 * (off & 3))); val 189 drivers/ssb/driver_pcicore.c val |= *((const u16 *)buf) << (8 * (off & 3)); val 192 drivers/ssb/driver_pcicore.c val = *((const u32 *)buf); val 195 drivers/ssb/driver_pcicore.c writel(val, mmio); val 205 drivers/ssb/driver_pcicore.c int reg, int size, u32 *val) val 212 drivers/ssb/driver_pcicore.c PCI_FUNC(devfn), reg, val, size); val 219 drivers/ssb/driver_pcicore.c int reg, int size, u32 val) val 226 drivers/ssb/driver_pcicore.c PCI_FUNC(devfn), reg, &val, size); val 320 drivers/ssb/driver_pcicore.c u32 val; val 328 drivers/ssb/driver_pcicore.c val = SSB_PCICORE_CTL_RST_OE; val 329 drivers/ssb/driver_pcicore.c val |= SSB_PCICORE_CTL_CLK_OE; val 330 drivers/ssb/driver_pcicore.c pcicore_write32(pc, SSB_PCICORE_CTL, val); val 331 drivers/ssb/driver_pcicore.c val |= SSB_PCICORE_CTL_CLK; /* Clock on */ val 332 drivers/ssb/driver_pcicore.c pcicore_write32(pc, SSB_PCICORE_CTL, val); val 334 drivers/ssb/driver_pcicore.c val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ val 335 drivers/ssb/driver_pcicore.c pcicore_write32(pc, SSB_PCICORE_CTL, val); val 336 drivers/ssb/driver_pcicore.c val = SSB_PCICORE_ARBCTL_INTERN; val 337 drivers/ssb/driver_pcicore.c pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); val 372 drivers/ssb/driver_pcicore.c val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; val 373 drivers/ssb/driver_pcicore.c ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); val 375 drivers/ssb/driver_pcicore.c val = 0; val 376 drivers/ssb/driver_pcicore.c ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); val 992 drivers/ssb/main.c u32 val; val 996 drivers/ssb/main.c val = ssb_read32(dev, SSB_TMSLOW); val 997 drivers/ssb/main.c val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; val 999 drivers/ssb/main.c return (val == SSB_TMSLOW_CLOCK); val 1017 drivers/ssb/main.c u32 val; val 1029 drivers/ssb/main.c val = ssb_read32(dev, SSB_IMSTATE); val 1030 drivers/ssb/main.c if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { val 1031 drivers/ssb/main.c val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); val 1032 drivers/ssb/main.c ssb_write32(dev, SSB_IMSTATE, val); val 1052 drivers/ssb/main.c u32 val; val 1055 drivers/ssb/main.c val = ssb_read32(dev, reg); val 1057 drivers/ssb/main.c if ((val & bitmask) == bitmask) val 1060 drivers/ssb/main.c if (!(val & bitmask)) val 1074 drivers/ssb/main.c u32 reject, val; val 1087 drivers/ssb/main.c val = ssb_read32(dev, SSB_IMSTATE); val 1088 drivers/ssb/main.c val |= SSB_IMSTATE_REJECT; val 1089 drivers/ssb/main.c ssb_write32(dev, SSB_IMSTATE, val); val 1101 drivers/ssb/main.c val = ssb_read32(dev, SSB_IMSTATE); val 1102 drivers/ssb/main.c val &= ~SSB_IMSTATE_REJECT; val 1103 drivers/ssb/main.c ssb_write32(dev, SSB_IMSTATE, val); val 73 drivers/ssb/pcihost_wrapper.c u32 val; val 91 drivers/ssb/pcihost_wrapper.c pci_read_config_dword(dev, 0x40, &val); val 92 drivers/ssb/pcihost_wrapper.c if ((val & 0x0000ff00) != 0) val 93 drivers/ssb/pcihost_wrapper.c pci_write_config_dword(dev, 0x40, val & 0xffff00ff); val 102 drivers/ssb/pcmcia.c u8 val; val 121 drivers/ssb/pcmcia.c err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_ADDRESS0, &val); val 124 drivers/ssb/pcmcia.c read_addr |= ((u32)(val & 0x0F)) << 12; val 125 drivers/ssb/pcmcia.c err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_ADDRESS1, &val); val 128 drivers/ssb/pcmcia.c read_addr |= ((u32)val) << 16; val 129 drivers/ssb/pcmcia.c err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_ADDRESS2, &val); val 132 drivers/ssb/pcmcia.c read_addr |= ((u32)val) << 24; val 170 drivers/ssb/pcmcia.c u8 val; val 177 drivers/ssb/pcmcia.c err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_MEMSEG, &val); val 180 drivers/ssb/pcmcia.c if (val == seg) val 765 drivers/ssb/pcmcia.c u8 val; val 768 drivers/ssb/pcmcia.c err = ssb_pcmcia_cfg_read(bus, cor, &val); val 771 drivers/ssb/pcmcia.c val &= ~COR_SOFT_RESET; val 772 drivers/ssb/pcmcia.c val |= COR_FUNC_ENA | COR_IREQ_ENA | COR_LEVEL_REQ; val 773 drivers/ssb/pcmcia.c err = ssb_pcmcia_cfg_write(bus, cor, val); val 110 drivers/ssb/sdio.c static int ssb_sdio_writeb(struct ssb_bus *bus, unsigned int addr, u8 val) val 114 drivers/ssb/sdio.c sdio_writeb(bus->host_sdio, val, addr, &error); val 117 drivers/ssb/sdio.c addr, val, error); val 126 drivers/ssb/sdio.c u8 val; val 129 drivers/ssb/sdio.c val = sdio_readb(bus->host_sdio, addr, &error); val 132 drivers/ssb/sdio.c addr, val, error); val 135 drivers/ssb/sdio.c return val; val 169 drivers/ssb/sdio.c u32 val; val 173 drivers/ssb/sdio.c val = sdio_readl(bus->host_sdio, offset, &error); val 177 drivers/ssb/sdio.c bus->sdio_sbaddr >> 16, offset, val, error); val 180 drivers/ssb/sdio.c return val; val 232 drivers/ssb/sdio.c u8 val = 0xff; val 240 drivers/ssb/sdio.c val = sdio_readb(bus->host_sdio, offset, &error); val 243 drivers/ssb/sdio.c bus->sdio_sbaddr >> 16, offset, val, error); val 248 drivers/ssb/sdio.c return val; val 254 drivers/ssb/sdio.c u16 val = 0xffff; val 262 drivers/ssb/sdio.c val = sdio_readw(bus->host_sdio, offset, &error); val 265 drivers/ssb/sdio.c bus->sdio_sbaddr >> 16, offset, val, error); val 270 drivers/ssb/sdio.c return val; val 276 drivers/ssb/sdio.c u32 val = 0xffffffff; val 285 drivers/ssb/sdio.c val = sdio_readl(bus->host_sdio, offset, &error); val 288 drivers/ssb/sdio.c bus->sdio_sbaddr >> 16, offset, val, error); val 293 drivers/ssb/sdio.c return val; val 343 drivers/ssb/sdio.c static void ssb_sdio_write8(struct ssb_device *dev, u16 offset, u8 val) val 353 drivers/ssb/sdio.c sdio_writeb(bus->host_sdio, val, offset, &error); val 356 drivers/ssb/sdio.c bus->sdio_sbaddr >> 16, offset, val, error); val 362 drivers/ssb/sdio.c static void ssb_sdio_write16(struct ssb_device *dev, u16 offset, u16 val) val 372 drivers/ssb/sdio.c sdio_writew(bus->host_sdio, val, offset, &error); val 375 drivers/ssb/sdio.c bus->sdio_sbaddr >> 16, offset, val, error); val 381 drivers/ssb/sdio.c static void ssb_sdio_write32(struct ssb_device *dev, u16 offset, u32 val) val 392 drivers/ssb/sdio.c sdio_writel(bus->host_sdio, val, offset, &error); val 395 drivers/ssb/sdio.c bus->sdio_sbaddr >> 16, offset, val, error); val 541 drivers/staging/android/ion/ion.c static int debug_shrink_set(void *data, u64 val) val 548 drivers/staging/android/ion/ion.c sc.nr_to_scan = val; val 550 drivers/staging/android/ion/ion.c if (!val) { val 559 drivers/staging/android/ion/ion.c static int debug_shrink_get(void *data, u64 *val) val 569 drivers/staging/android/ion/ion.c *val = objs; val 783 drivers/staging/comedi/comedidev.h unsigned int val) val 785 drivers/staging/comedi/comedidev.h return val ^ s->maxdata ^ (s->maxdata >> 1); val 898 drivers/staging/comedi/comedidev.h unsigned int val) val 900 drivers/staging/comedi/comedidev.h if (*arg != val) { val 901 drivers/staging/comedi/comedidev.h *arg = val; val 919 drivers/staging/comedi/comedidev.h unsigned int val) val 921 drivers/staging/comedi/comedidev.h if (*arg < val) { val 922 drivers/staging/comedi/comedidev.h *arg = val; val 940 drivers/staging/comedi/comedidev.h unsigned int val) val 942 drivers/staging/comedi/comedidev.h if (*arg > val) { val 943 drivers/staging/comedi/comedidev.h *arg = val; val 58 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int val; val 62 drivers/staging/comedi/drivers/addi_apci_1500.c val = inb(dev->iobase + APCI1500_Z8536_CTRL_REG); val 65 drivers/staging/comedi/drivers/addi_apci_1500.c return val; val 69 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int val, unsigned int reg) val 75 drivers/staging/comedi/drivers/addi_apci_1500.c outb(val, dev->iobase + APCI1500_Z8536_CTRL_REG); val 193 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int val; val 195 drivers/staging/comedi/drivers/addi_apci_1500.c val = z8536_read(dev, reg); val 196 drivers/staging/comedi/drivers/addi_apci_1500.c if ((val & Z8536_STAT_IE_IP) == Z8536_STAT_IE_IP) { val 197 drivers/staging/comedi/drivers/addi_apci_1500.c val &= 0x0f; /* preserve any write bits */ val 198 drivers/staging/comedi/drivers/addi_apci_1500.c val |= Z8536_CMD_CLR_IP_IUS; val 199 drivers/staging/comedi/drivers/addi_apci_1500.c z8536_write(dev, val, reg); val 212 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int val; val 214 drivers/staging/comedi/drivers/addi_apci_1500.c val = inl(devpriv->amcc + AMCC_OP_REG_INTCSR); val 215 drivers/staging/comedi/drivers/addi_apci_1500.c if (!(val & INTCSR_INTR_ASSERTED)) val 223 drivers/staging/comedi/drivers/addi_apci_1500.c val = inb(dev->iobase + APCI1500_Z8536_PORTB_REG); val 224 drivers/staging/comedi/drivers/addi_apci_1500.c val &= 0xc0; val 225 drivers/staging/comedi/drivers/addi_apci_1500.c if (val) { val 226 drivers/staging/comedi/drivers/addi_apci_1500.c if (val & 0x80) /* voltage error */ val 228 drivers/staging/comedi/drivers/addi_apci_1500.c if (val & 0x40) /* short circuit error */ val 290 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int val; val 313 drivers/staging/comedi/drivers/addi_apci_1500.c val = z8536_read(dev, Z8536_PA_MODE_REG); val 314 drivers/staging/comedi/drivers/addi_apci_1500.c val &= ~Z8536_PAB_MODE_PMS_MASK; val 315 drivers/staging/comedi/drivers/addi_apci_1500.c val |= (pa_mode | Z8536_PAB_MODE_IMO); val 316 drivers/staging/comedi/drivers/addi_apci_1500.c z8536_write(dev, val, Z8536_PA_MODE_REG); val 332 drivers/staging/comedi/drivers/addi_apci_1500.c val = z8536_read(dev, Z8536_PB_MODE_REG); val 333 drivers/staging/comedi/drivers/addi_apci_1500.c val &= ~Z8536_PAB_MODE_PMS_MASK; val 334 drivers/staging/comedi/drivers/addi_apci_1500.c val |= (pb_mode | Z8536_PAB_MODE_IMO); val 335 drivers/staging/comedi/drivers/addi_apci_1500.c z8536_write(dev, val, Z8536_PB_MODE_REG); val 575 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int val; val 579 drivers/staging/comedi/drivers/addi_apci_1500.c val = data[1] & s->maxdata; val 580 drivers/staging/comedi/drivers/addi_apci_1500.c z8536_write(dev, val & 0xff, Z8536_CT_RELOAD_LSB_REG(chan)); val 581 drivers/staging/comedi/drivers/addi_apci_1500.c z8536_write(dev, (val >> 8) & 0xff, val 594 drivers/staging/comedi/drivers/addi_apci_1500.c val = z8536_read(dev, Z8536_CT_CMDSTAT_REG(chan)); val 595 drivers/staging/comedi/drivers/addi_apci_1500.c if (val & Z8536_CT_STAT_CIP) val 597 drivers/staging/comedi/drivers/addi_apci_1500.c if (val & Z8536_CT_CMDSTAT_GCB) val 599 drivers/staging/comedi/drivers/addi_apci_1500.c if (val & Z8536_STAT_IP) { val 612 drivers/staging/comedi/drivers/addi_apci_1500.c val = Z8536_CT_MODE_ECE | val 617 drivers/staging/comedi/drivers/addi_apci_1500.c val = Z8536_CT_MODE_ETE | val 622 drivers/staging/comedi/drivers/addi_apci_1500.c val = Z8536_CT_MODE_CSC | val 627 drivers/staging/comedi/drivers/addi_apci_1500.c val = Z8536_CT_MODE_CSC | val 632 drivers/staging/comedi/drivers/addi_apci_1500.c val = Z8536_CT_MODE_REB | val 637 drivers/staging/comedi/drivers/addi_apci_1500.c val = Z8536_CT_MODE_EOE | val 646 drivers/staging/comedi/drivers/addi_apci_1500.c z8536_write(dev, val, Z8536_CT_MODE_REG(chan)); val 680 drivers/staging/comedi/drivers/addi_apci_1500.c val = z8536_read(dev, Z8536_CT_MODE_REG(chan)); val 681 drivers/staging/comedi/drivers/addi_apci_1500.c val &= Z8536_CT_MODE_EGE; val 683 drivers/staging/comedi/drivers/addi_apci_1500.c val |= Z8536_CT_MODE_EGE; val 686 drivers/staging/comedi/drivers/addi_apci_1500.c z8536_write(dev, val, Z8536_CT_MODE_REG(chan)); val 725 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int val; val 735 drivers/staging/comedi/drivers/addi_apci_1500.c val = z8536_read(dev, Z8536_CT_VAL_MSB_REG(chan)) << 8; val 736 drivers/staging/comedi/drivers/addi_apci_1500.c val |= z8536_read(dev, Z8536_CT_VAL_LSB_REG(chan)); val 738 drivers/staging/comedi/drivers/addi_apci_1500.c data[i] = val; val 489 drivers/staging/comedi/drivers/addi_apci_1564.c unsigned int val; val 504 drivers/staging/comedi/drivers/addi_apci_1564.c val = inl(devpriv->timer + ADDI_TCW_CTRL_REG); val 505 drivers/staging/comedi/drivers/addi_apci_1564.c if (val & ADDI_TCW_CTRL_IRQ_ENA) val 507 drivers/staging/comedi/drivers/addi_apci_1564.c if (val & ADDI_TCW_CTRL_TIMER_ENA) val 509 drivers/staging/comedi/drivers/addi_apci_1564.c val = inl(devpriv->timer + ADDI_TCW_STATUS_REG); val 510 drivers/staging/comedi/drivers/addi_apci_1564.c if (val & ADDI_TCW_STATUS_OVERFLOW) val 541 drivers/staging/comedi/drivers/addi_apci_1564.c unsigned int val = data[insn->n - 1]; val 543 drivers/staging/comedi/drivers/addi_apci_1564.c outl(val, devpriv->timer + ADDI_TCW_RELOAD_REG); val 572 drivers/staging/comedi/drivers/addi_apci_1564.c unsigned int val; val 576 drivers/staging/comedi/drivers/addi_apci_1564.c val = inl(iobase + ADDI_TCW_CTRL_REG); val 577 drivers/staging/comedi/drivers/addi_apci_1564.c val |= ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA; val 579 drivers/staging/comedi/drivers/addi_apci_1564.c outl(val, iobase + ADDI_TCW_CTRL_REG); val 582 drivers/staging/comedi/drivers/addi_apci_1564.c val = inl(iobase + ADDI_TCW_CTRL_REG); val 583 drivers/staging/comedi/drivers/addi_apci_1564.c val &= ~(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA); val 584 drivers/staging/comedi/drivers/addi_apci_1564.c outl(val, iobase + ADDI_TCW_CTRL_REG); val 596 drivers/staging/comedi/drivers/addi_apci_1564.c val = inl(iobase + ADDI_TCW_CTRL_REG); val 597 drivers/staging/comedi/drivers/addi_apci_1564.c if (val & ADDI_TCW_CTRL_IRQ_ENA) val 599 drivers/staging/comedi/drivers/addi_apci_1564.c if (val & ADDI_TCW_CTRL_CNTR_ENA) val 601 drivers/staging/comedi/drivers/addi_apci_1564.c val = inl(iobase + ADDI_TCW_STATUS_REG); val 602 drivers/staging/comedi/drivers/addi_apci_1564.c if (val & ADDI_TCW_STATUS_OVERFLOW) val 625 drivers/staging/comedi/drivers/addi_apci_1564.c unsigned int val = data[insn->n - 1]; val 627 drivers/staging/comedi/drivers/addi_apci_1564.c outl(val, iobase + ADDI_TCW_RELOAD_REG); val 656 drivers/staging/comedi/drivers/addi_apci_1564.c unsigned int val; val 669 drivers/staging/comedi/drivers/addi_apci_1564.c val = inl(devpriv->eeprom + APCI1564_EEPROM_REG); val 670 drivers/staging/comedi/drivers/addi_apci_1564.c if (APCI1564_EEPROM_TO_REV(val) == 0) { val 168 drivers/staging/comedi/drivers/addi_apci_2032.c unsigned int val; val 174 drivers/staging/comedi/drivers/addi_apci_2032.c val = inl(dev->iobase + APCI2032_STATUS_REG) & APCI2032_STATUS_IRQ; val 175 drivers/staging/comedi/drivers/addi_apci_2032.c if (!val) val 181 drivers/staging/comedi/drivers/addi_apci_2032.c val = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3; val 183 drivers/staging/comedi/drivers/addi_apci_2032.c outl(~val & 3, dev->iobase + APCI2032_INT_CTRL_REG); val 190 drivers/staging/comedi/drivers/addi_apci_2032.c if (subpriv->active && (val & subpriv->enabled_isns) != 0) { val 198 drivers/staging/comedi/drivers/addi_apci_2032.c if (val & (1 << chan)) val 158 drivers/staging/comedi/drivers/addi_apci_3120.c unsigned int val, unsigned int reg) val 165 drivers/staging/comedi/drivers/addi_apci_3120.c outw(val & 0xffff, devpriv->addon + APCI3120_ADDON_DATA_REG); val 168 drivers/staging/comedi/drivers/addi_apci_3120.c outw((val >> 16) & 0xffff, devpriv->addon + APCI3120_ADDON_DATA_REG); val 314 drivers/staging/comedi/drivers/addi_apci_3120.c unsigned int timer, unsigned int val) val 322 drivers/staging/comedi/drivers/addi_apci_3120.c outw(val & 0xffff, dev->iobase + APCI3120_TIMER_REG); val 329 drivers/staging/comedi/drivers/addi_apci_3120.c outw((val >> 16) & 0xffff, dev->iobase + APCI3120_TIMER_REG); val 337 drivers/staging/comedi/drivers/addi_apci_3120.c unsigned int val; val 343 drivers/staging/comedi/drivers/addi_apci_3120.c val = inw(dev->iobase + APCI3120_TIMER_REG); val 350 drivers/staging/comedi/drivers/addi_apci_3120.c val |= (inw(dev->iobase + APCI3120_TIMER_REG) << 16); val 353 drivers/staging/comedi/drivers/addi_apci_3120.c return val; val 400 drivers/staging/comedi/drivers/addi_apci_3120.c unsigned int val; val 402 drivers/staging/comedi/drivers/addi_apci_3120.c val = APCI3120_CHANLIST_MUX(chan) | val 407 drivers/staging/comedi/drivers/addi_apci_3120.c val |= APCI3120_CHANLIST_UNIPOLAR; val 409 drivers/staging/comedi/drivers/addi_apci_3120.c outw(val, dev->iobase + APCI3120_CHANLIST_REG); val 500 drivers/staging/comedi/drivers/addi_apci_3120.c unsigned short val; val 504 drivers/staging/comedi/drivers/addi_apci_3120.c val = inw(dev->iobase + APCI3120_AI_FIFO_REG); val 505 drivers/staging/comedi/drivers/addi_apci_3120.c comedi_buf_write_samples(s, &val, 1); val 769 drivers/staging/comedi/drivers/addi_apci_3120.c unsigned int val = data[i]; val 776 drivers/staging/comedi/drivers/addi_apci_3120.c outw(APCI3120_AO_MUX(chan) | APCI3120_AO_DATA(val), val 779 drivers/staging/comedi/drivers/addi_apci_3120.c s->readback[chan] = val; val 132 drivers/staging/comedi/drivers/addi_apci_3501.c unsigned int val = data[i]; val 146 drivers/staging/comedi/drivers/addi_apci_3501.c outl(cfg | APCI3501_AO_DATA_VAL(val), val 149 drivers/staging/comedi/drivers/addi_apci_3501.c s->readback[chan] = val; val 182 drivers/staging/comedi/drivers/addi_apci_3501.c unsigned char val; val 185 drivers/staging/comedi/drivers/addi_apci_3501.c val = inb(iobase + AMCC_OP_REG_MCSR_NVCMD); val 186 drivers/staging/comedi/drivers/addi_apci_3501.c } while (val & 0x80); val 192 drivers/staging/comedi/drivers/addi_apci_3501.c unsigned short val = 0; val 220 drivers/staging/comedi/drivers/addi_apci_3501.c val |= tmp; val 222 drivers/staging/comedi/drivers/addi_apci_3501.c val |= (tmp << 8); val 225 drivers/staging/comedi/drivers/addi_apci_3501.c return val; val 241 drivers/staging/comedi/drivers/addi_apci_3501.c unsigned short val; val 247 drivers/staging/comedi/drivers/addi_apci_3501.c val = apci3501_eeprom_readw(devpriv->amcc, addr + 10); val 248 drivers/staging/comedi/drivers/addi_apci_3501.c return (val >> 4) & 0x3ff; val 261 drivers/staging/comedi/drivers/addi_apci_3501.c unsigned int val; val 266 drivers/staging/comedi/drivers/addi_apci_3501.c val = apci3501_eeprom_readw(devpriv->amcc, 2 * addr); val 268 drivers/staging/comedi/drivers/addi_apci_3501.c data[i] = val; val 276 drivers/staging/comedi/drivers/addi_apci_3501.c unsigned int val; val 286 drivers/staging/comedi/drivers/addi_apci_3501.c val = APCI3501_AO_DATA_BIPOLAR | APCI3501_AO_DATA_VAL(0); val 296 drivers/staging/comedi/drivers/addi_apci_3501.c outl(val | APCI3501_AO_DATA_CHAN(chan), val 353 drivers/staging/comedi/drivers/addi_apci_3xxx.c unsigned int val; val 361 drivers/staging/comedi/drivers/addi_apci_3xxx.c val = readl(dev->mmio + 28); val 362 drivers/staging/comedi/drivers/addi_apci_3xxx.c comedi_buf_write_samples(s, &val, 1); val 386 drivers/staging/comedi/drivers/addi_apci_3xxx.c unsigned int val; val 402 drivers/staging/comedi/drivers/addi_apci_3xxx.c val = (range & 3) | ((range >> 2) << 6) | val 404 drivers/staging/comedi/drivers/addi_apci_3xxx.c writel(val, dev->mmio + 0); val 620 drivers/staging/comedi/drivers/addi_apci_3xxx.c unsigned int val = data[i]; val 626 drivers/staging/comedi/drivers/addi_apci_3xxx.c writel((val << 8) | chan, dev->mmio + 100); val 633 drivers/staging/comedi/drivers/addi_apci_3xxx.c s->readback[chan] = val; val 703 drivers/staging/comedi/drivers/addi_apci_3xxx.c unsigned int val; val 713 drivers/staging/comedi/drivers/addi_apci_3xxx.c val = inl(dev->iobase + 80); val 714 drivers/staging/comedi/drivers/addi_apci_3xxx.c val |= (inl(dev->iobase + 64) << 8); val 716 drivers/staging/comedi/drivers/addi_apci_3xxx.c val |= (inl(dev->iobase + 112) << 16); val 718 drivers/staging/comedi/drivers/addi_apci_3xxx.c val |= (inl(dev->iobase + 96) << 16); val 720 drivers/staging/comedi/drivers/addi_apci_3xxx.c data[1] = val; val 727 drivers/staging/comedi/drivers/addi_apci_3xxx.c unsigned int val; val 737 drivers/staging/comedi/drivers/addi_apci_3xxx.c val = readl(dev->mmio + 16); val 738 drivers/staging/comedi/drivers/addi_apci_3xxx.c writel(val, dev->mmio + 16); val 745 drivers/staging/comedi/drivers/addi_apci_3xxx.c val = readl(dev->mmio + 28); val 65 drivers/staging/comedi/drivers/adl_pci6208.c unsigned int val = data[i]; val 73 drivers/staging/comedi/drivers/adl_pci6208.c outw(comedi_offset_munge(s, val), val 76 drivers/staging/comedi/drivers/adl_pci6208.c s->readback[chan] = val; val 87 drivers/staging/comedi/drivers/adl_pci6208.c unsigned int val; val 89 drivers/staging/comedi/drivers/adl_pci6208.c val = inw(dev->iobase + PCI6208_DIO); val 90 drivers/staging/comedi/drivers/adl_pci6208.c val = (val & PCI6208_DIO_DI_MASK) >> PCI6208_DIO_DI_SHIFT; val 92 drivers/staging/comedi/drivers/adl_pci6208.c data[1] = val; val 115 drivers/staging/comedi/drivers/adl_pci6208.c unsigned int val; val 162 drivers/staging/comedi/drivers/adl_pci6208.c val = inw(dev->iobase + PCI6208_DIO); val 163 drivers/staging/comedi/drivers/adl_pci6208.c val = (val & PCI6208_DIO_DO_MASK) >> PCI6208_DIO_DO_SHIFT; val 164 drivers/staging/comedi/drivers/adl_pci6208.c s->state = val; val 115 drivers/staging/comedi/drivers/adl_pci7x3x.c unsigned int val = s->state; val 124 drivers/staging/comedi/drivers/adl_pci7x3x.c val |= val << 16; val 126 drivers/staging/comedi/drivers/adl_pci7x3x.c outl(val, dev->iobase + reg); val 575 drivers/staging/comedi/drivers/adl_pci9111.c unsigned int val = s->readback[chan]; val 579 drivers/staging/comedi/drivers/adl_pci9111.c val = data[i]; val 580 drivers/staging/comedi/drivers/adl_pci9111.c outw(val, dev->iobase + PCI9111_AO_REG); val 582 drivers/staging/comedi/drivers/adl_pci9111.c s->readback[chan] = val; val 337 drivers/staging/comedi/drivers/adl_pci9118.c unsigned int val; val 359 drivers/staging/comedi/drivers/adl_pci9118.c val = PCI9118_AI_CHANLIST_CHAN(chan0) | val 363 drivers/staging/comedi/drivers/adl_pci9118.c outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG); val 373 drivers/staging/comedi/drivers/adl_pci9118.c val = PCI9118_AI_CHANLIST_CHAN(chan) | val 375 drivers/staging/comedi/drivers/adl_pci9118.c outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG); val 380 drivers/staging/comedi/drivers/adl_pci9118.c val = PCI9118_AI_CHANLIST_CHAN(chan0) | val 383 drivers/staging/comedi/drivers/adl_pci9118.c outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG); val 1327 drivers/staging/comedi/drivers/adl_pci9118.c unsigned int val; val 1350 drivers/staging/comedi/drivers/adl_pci9118.c val = inl(dev->iobase + PCI9118_AI_FIFO_REG); val 1352 drivers/staging/comedi/drivers/adl_pci9118.c data[i] = (val & 0xffff) ^ 0x8000; val 1354 drivers/staging/comedi/drivers/adl_pci9118.c data[i] = (val >> 4) & 0xfff; val 1366 drivers/staging/comedi/drivers/adl_pci9118.c unsigned int val = s->readback[chan]; val 1370 drivers/staging/comedi/drivers/adl_pci9118.c val = data[i]; val 1371 drivers/staging/comedi/drivers/adl_pci9118.c outl(val, dev->iobase + PCI9118_AO_REG(chan)); val 1373 drivers/staging/comedi/drivers/adl_pci9118.c s->readback[chan] = val; val 114 drivers/staging/comedi/drivers/adq12b.c unsigned int val; val 119 drivers/staging/comedi/drivers/adq12b.c val = ADQ12B_CTREG_RANGE(range) | ADQ12B_CTREG_CHAN(chan); val 120 drivers/staging/comedi/drivers/adq12b.c if (val != devpriv->last_ctreg) { val 121 drivers/staging/comedi/drivers/adq12b.c outb(val, dev->iobase + ADQ12B_CTREG); val 122 drivers/staging/comedi/drivers/adq12b.c devpriv->last_ctreg = val; val 126 drivers/staging/comedi/drivers/adq12b.c val = inb(dev->iobase + ADQ12B_ADLOW); /* trigger A/D */ val 133 drivers/staging/comedi/drivers/adq12b.c val = inb(dev->iobase + ADQ12B_ADHIG) << 8; val 134 drivers/staging/comedi/drivers/adq12b.c val |= inb(dev->iobase + ADQ12B_ADLOW); /* retriggers A/D */ val 136 drivers/staging/comedi/drivers/adq12b.c data[i] = val; val 159 drivers/staging/comedi/drivers/adq12b.c unsigned int val; val 165 drivers/staging/comedi/drivers/adq12b.c val = (s->state >> chan) & 0x01; val 166 drivers/staging/comedi/drivers/adq12b.c outb((val << 3) | chan, val 303 drivers/staging/comedi/drivers/adv_pci1710.c unsigned int *val) val 325 drivers/staging/comedi/drivers/adv_pci1710.c *val = sample & s->maxdata; val 348 drivers/staging/comedi/drivers/adv_pci1710.c unsigned int val; val 357 drivers/staging/comedi/drivers/adv_pci1710.c ret = pci1710_ai_read_sample(dev, s, 0, &val); val 361 drivers/staging/comedi/drivers/adv_pci1710.c data[i] = val; val 398 drivers/staging/comedi/drivers/adv_pci1710.c unsigned int val; val 417 drivers/staging/comedi/drivers/adv_pci1710.c ret = pci1710_ai_read_sample(dev, s, s->async->cur_chan, &val); val 423 drivers/staging/comedi/drivers/adv_pci1710.c comedi_buf_write_samples(s, &val, 1); val 458 drivers/staging/comedi/drivers/adv_pci1710.c unsigned int val; val 461 drivers/staging/comedi/drivers/adv_pci1710.c ret = pci1710_ai_read_sample(dev, s, s->async->cur_chan, &val); val 467 drivers/staging/comedi/drivers/adv_pci1710.c if (!comedi_buf_write_samples(s, &val, 1)) val 643 drivers/staging/comedi/drivers/adv_pci1710.c unsigned int val = s->readback[chan]; val 651 drivers/staging/comedi/drivers/adv_pci1710.c val = data[i]; val 652 drivers/staging/comedi/drivers/adv_pci1710.c outw(val, dev->iobase + PCI171X_DA_REG(chan)); val 655 drivers/staging/comedi/drivers/adv_pci1710.c s->readback[chan] = val; val 77 drivers/staging/comedi/drivers/adv_pci1720.c unsigned int val; val 81 drivers/staging/comedi/drivers/adv_pci1720.c val = inb(dev->iobase + PCI1720_AO_RANGE_REG); val 82 drivers/staging/comedi/drivers/adv_pci1720.c val &= ~PCI1720_AO_RANGE_MASK(chan); val 83 drivers/staging/comedi/drivers/adv_pci1720.c val |= PCI1720_AO_RANGE(chan, range); val 84 drivers/staging/comedi/drivers/adv_pci1720.c outb(val, dev->iobase + PCI1720_AO_RANGE_REG); val 86 drivers/staging/comedi/drivers/adv_pci1720.c val = s->readback[chan]; val 88 drivers/staging/comedi/drivers/adv_pci1720.c val = data[i]; val 90 drivers/staging/comedi/drivers/adv_pci1720.c outb(val & 0xff, dev->iobase + PCI1720_AO_LSB_REG(chan)); val 91 drivers/staging/comedi/drivers/adv_pci1720.c outb((val >> 8) & 0xff, dev->iobase + PCI1720_AO_MSB_REG(chan)); val 97 drivers/staging/comedi/drivers/adv_pci1720.c s->readback[chan] = val; val 87 drivers/staging/comedi/drivers/adv_pci1723.c unsigned int val = data[i]; val 89 drivers/staging/comedi/drivers/adv_pci1723.c outw(val, dev->iobase + PCI1723_AO_REG(chan)); val 90 drivers/staging/comedi/drivers/adv_pci1723.c s->readback[chan] = val; val 137 drivers/staging/comedi/drivers/adv_pci1723.c unsigned int val; val 187 drivers/staging/comedi/drivers/adv_pci1723.c val = inw(dev->iobase + PCI1723_DIO_CTRL_REG); val 188 drivers/staging/comedi/drivers/adv_pci1723.c if (!(val & PCI1723_DIO_CTRL_LDIO)) val 190 drivers/staging/comedi/drivers/adv_pci1723.c if (!(val & PCI1723_DIO_CTRL_HDIO)) val 103 drivers/staging/comedi/drivers/adv_pci1724.c unsigned int val = data[i]; val 109 drivers/staging/comedi/drivers/adv_pci1724.c outl(ctrl | PCI1724_DAC_CTRL_DATA(val), val 112 drivers/staging/comedi/drivers/adv_pci1724.c s->readback[chan] = val; val 97 drivers/staging/comedi/drivers/adv_pci1760.c unsigned char cmd, unsigned short val) val 102 drivers/staging/comedi/drivers/adv_pci1760.c outb(val & 0xff, dev->iobase + PCI1760_OMB_REG(0)); val 103 drivers/staging/comedi/drivers/adv_pci1760.c outb((val >> 8) & 0xff, dev->iobase + PCI1760_OMB_REG(1)); val 122 drivers/staging/comedi/drivers/adv_pci1760.c unsigned char cmd, unsigned short val) val 140 drivers/staging/comedi/drivers/adv_pci1760.c ret = pci1760_send_cmd(dev, cmd, val); val 119 drivers/staging/comedi/drivers/aio_aio12_8.c unsigned int val; val 143 drivers/staging/comedi/drivers/aio_aio12_8.c val = inw(dev->iobase + AIO12_8_ADC_REG) & s->maxdata; val 147 drivers/staging/comedi/drivers/aio_aio12_8.c val = comedi_offset_munge(s, val); val 149 drivers/staging/comedi/drivers/aio_aio12_8.c data[i] = val; val 161 drivers/staging/comedi/drivers/aio_aio12_8.c unsigned int val = s->readback[chan]; val 168 drivers/staging/comedi/drivers/aio_aio12_8.c val = data[i]; val 169 drivers/staging/comedi/drivers/aio_aio12_8.c outw(val, dev->iobase + AIO12_8_DAC_REG(chan)); val 171 drivers/staging/comedi/drivers/aio_aio12_8.c s->readback[chan] = val; val 48 drivers/staging/comedi/drivers/aio_iiro_16.c unsigned int val; val 50 drivers/staging/comedi/drivers/aio_iiro_16.c val = inb(dev->iobase + AIO_IIRO_16_INPUT_0_7); val 51 drivers/staging/comedi/drivers/aio_iiro_16.c val |= inb(dev->iobase + AIO_IIRO_16_INPUT_8_15) << 8; val 53 drivers/staging/comedi/drivers/aio_iiro_16.c return val; val 61 drivers/staging/comedi/drivers/aio_iiro_16.c unsigned int val; val 67 drivers/staging/comedi/drivers/aio_iiro_16.c val = aio_iiro_16_read_inputs(dev); val 68 drivers/staging/comedi/drivers/aio_iiro_16.c val |= (status << 16); val 70 drivers/staging/comedi/drivers/aio_iiro_16.c comedi_buf_write_samples(s, &val, 1); val 44 drivers/staging/comedi/drivers/amplc_dio200.h void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val); val 104 drivers/staging/comedi/drivers/amplc_dio200_common.c unsigned int offset, unsigned char val) val 112 drivers/staging/comedi/drivers/amplc_dio200_common.c writeb(val, dev->mmio + offset); val 114 drivers/staging/comedi/drivers/amplc_dio200_common.c outb(val, dev->iobase + offset); val 131 drivers/staging/comedi/drivers/amplc_dio200_common.c unsigned int offset, unsigned int val) val 139 drivers/staging/comedi/drivers/amplc_dio200_common.c writel(val, dev->mmio + offset); val 141 drivers/staging/comedi/drivers/amplc_dio200_common.c outl(val, dev->iobase + offset); val 244 drivers/staging/comedi/drivers/amplc_dio200_common.c unsigned short val; val 247 drivers/staging/comedi/drivers/amplc_dio200_common.c val = 0; val 251 drivers/staging/comedi/drivers/amplc_dio200_common.c val |= (1U << n); val 254 drivers/staging/comedi/drivers/amplc_dio200_common.c comedi_buf_write_samples(s, &val, 1); val 621 drivers/staging/comedi/drivers/amplc_dio200_common.c unsigned int val; val 639 drivers/staging/comedi/drivers/amplc_dio200_common.c val = dio200_read8(dev, subpriv->ofs + I8255_DATA_A_REG); val 640 drivers/staging/comedi/drivers/amplc_dio200_common.c val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_B_REG) << 8; val 641 drivers/staging/comedi/drivers/amplc_dio200_common.c val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_C_REG) << 16; val 643 drivers/staging/comedi/drivers/amplc_dio200_common.c data[1] = val; val 769 drivers/staging/comedi/drivers/amplc_dio200_common.c void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val) val 771 drivers/staging/comedi/drivers/amplc_dio200_common.c dio200_write8(dev, DIO200_ENHANCE, val); val 425 drivers/staging/comedi/drivers/amplc_pci224.c unsigned int val = s->readback[chan]; val 429 drivers/staging/comedi/drivers/amplc_pci224.c val = data[i]; val 430 drivers/staging/comedi/drivers/amplc_pci224.c pci224_ao_set_data(dev, chan, range, val); val 432 drivers/staging/comedi/drivers/amplc_pci224.c s->readback[chan] = val; val 830 drivers/staging/comedi/drivers/amplc_pci230.c unsigned int val = s->readback[chan]; val 841 drivers/staging/comedi/drivers/amplc_pci230.c val = data[i]; val 842 drivers/staging/comedi/drivers/amplc_pci230.c pci230_ao_write_nofifo(dev, val, chan); val 844 drivers/staging/comedi/drivers/amplc_pci230.c s->readback[chan] = val; val 2022 drivers/staging/comedi/drivers/amplc_pci230.c unsigned short val; val 2060 drivers/staging/comedi/drivers/amplc_pci230.c val = pci230_ai_read(dev); val 2061 drivers/staging/comedi/drivers/amplc_pci230.c if (!comedi_buf_write_samples(s, &val, 1)) val 64 drivers/staging/comedi/drivers/c6xdigio.c unsigned int val, unsigned int status) val 66 drivers/staging/comedi/drivers/c6xdigio.c outb_p(val, dev->iobase + C6XDIGIO_DATA_REG); val 75 drivers/staging/comedi/drivers/c6xdigio.c unsigned int val; val 77 drivers/staging/comedi/drivers/c6xdigio.c val = inb(dev->iobase + C6XDIGIO_STATUS_REG); val 78 drivers/staging/comedi/drivers/c6xdigio.c val >>= 3; val 79 drivers/staging/comedi/drivers/c6xdigio.c val &= 0x07; val 81 drivers/staging/comedi/drivers/c6xdigio.c *bits = val; val 87 drivers/staging/comedi/drivers/c6xdigio.c unsigned int chan, unsigned int val) val 92 drivers/staging/comedi/drivers/c6xdigio.c if (val > 498) val 93 drivers/staging/comedi/drivers/c6xdigio.c val = 498; val 94 drivers/staging/comedi/drivers/c6xdigio.c if (val < 2) val 95 drivers/staging/comedi/drivers/c6xdigio.c val = 2; val 97 drivers/staging/comedi/drivers/c6xdigio.c bits = (val >> 0) & 0x03; val 99 drivers/staging/comedi/drivers/c6xdigio.c bits = (val >> 2) & 0x03; val 101 drivers/staging/comedi/drivers/c6xdigio.c bits = (val >> 4) & 0x03; val 103 drivers/staging/comedi/drivers/c6xdigio.c bits = (val >> 6) & 0x03; val 105 drivers/staging/comedi/drivers/c6xdigio.c bits = (val >> 8) & 0x03; val 115 drivers/staging/comedi/drivers/c6xdigio.c unsigned int val = 0; val 121 drivers/staging/comedi/drivers/c6xdigio.c val |= (bits << 0); val 124 drivers/staging/comedi/drivers/c6xdigio.c val |= (bits << 3); val 127 drivers/staging/comedi/drivers/c6xdigio.c val |= (bits << 6); val 130 drivers/staging/comedi/drivers/c6xdigio.c val |= (bits << 9); val 133 drivers/staging/comedi/drivers/c6xdigio.c val |= (bits << 12); val 136 drivers/staging/comedi/drivers/c6xdigio.c val |= (bits << 15); val 139 drivers/staging/comedi/drivers/c6xdigio.c val |= (bits << 18); val 142 drivers/staging/comedi/drivers/c6xdigio.c val |= (bits << 21); val 146 drivers/staging/comedi/drivers/c6xdigio.c return val; val 155 drivers/staging/comedi/drivers/c6xdigio.c unsigned int val = (s->state >> (16 * chan)) & 0xffff; val 159 drivers/staging/comedi/drivers/c6xdigio.c val = data[i]; val 160 drivers/staging/comedi/drivers/c6xdigio.c c6xdigio_pwm_write(dev, chan, val); val 170 drivers/staging/comedi/drivers/c6xdigio.c s->state |= (val << (16 * chan)); val 181 drivers/staging/comedi/drivers/c6xdigio.c unsigned int val; val 184 drivers/staging/comedi/drivers/c6xdigio.c val = (s->state >> (16 * chan)) & 0xffff; val 187 drivers/staging/comedi/drivers/c6xdigio.c data[i] = val; val 198 drivers/staging/comedi/drivers/c6xdigio.c unsigned int val; val 202 drivers/staging/comedi/drivers/c6xdigio.c val = c6xdigio_encoder_read(dev, chan); val 205 drivers/staging/comedi/drivers/c6xdigio.c data[i] = comedi_offset_munge(s, val); val 200 drivers/staging/comedi/drivers/cb_das16_cs.c unsigned int val = s->readback[chan]; val 206 drivers/staging/comedi/drivers/cb_das16_cs.c val = data[i]; val 222 drivers/staging/comedi/drivers/cb_das16_cs.c if ((val >> bit) & 0x1) val 239 drivers/staging/comedi/drivers/cb_das16_cs.c s->readback[chan] = val; val 411 drivers/staging/comedi/drivers/cb_pcidas.c unsigned int val = s->readback[chan]; val 424 drivers/staging/comedi/drivers/cb_pcidas.c val = data[i]; val 425 drivers/staging/comedi/drivers/cb_pcidas.c outw(val, devpriv->pcibar4 + PCIDAS_AO_DATA_REG(chan)); val 428 drivers/staging/comedi/drivers/cb_pcidas.c s->readback[chan] = val; val 442 drivers/staging/comedi/drivers/cb_pcidas.c unsigned int val = s->readback[chan]; val 459 drivers/staging/comedi/drivers/cb_pcidas.c val = data[i]; val 460 drivers/staging/comedi/drivers/cb_pcidas.c outw(val, devpriv->pcibar4 + PCIDAS_AO_FIFO_REG); val 463 drivers/staging/comedi/drivers/cb_pcidas.c s->readback[chan] = val; val 521 drivers/staging/comedi/drivers/cb_pcidas.c unsigned int val, unsigned int len, val 537 drivers/staging/comedi/drivers/cb_pcidas.c if (val & bit) val 567 drivers/staging/comedi/drivers/cb_pcidas.c unsigned int val = data[insn->n - 1]; val 569 drivers/staging/comedi/drivers/cb_pcidas.c if (s->readback[chan] != val) { val 571 drivers/staging/comedi/drivers/cb_pcidas.c cb_pcidas_calib_write(dev, (chan << 8) | val, 11, val 573 drivers/staging/comedi/drivers/cb_pcidas.c s->readback[chan] = val; val 580 drivers/staging/comedi/drivers/cb_pcidas.c static void cb_pcidas_dac08_write(struct comedi_device *dev, unsigned int val) val 584 drivers/staging/comedi/drivers/cb_pcidas.c val |= PCIDAS_CALIB_EN | PCIDAS_CALIB_SRC(devpriv->calib_src); val 587 drivers/staging/comedi/drivers/cb_pcidas.c outw(val, devpriv->pcibar1 + PCIDAS_CALIB_REG); val 589 drivers/staging/comedi/drivers/cb_pcidas.c outw(val | PCIDAS_CALIB_DAC08_SEL, val 592 drivers/staging/comedi/drivers/cb_pcidas.c outw(val, devpriv->pcibar1 + PCIDAS_CALIB_REG); val 604 drivers/staging/comedi/drivers/cb_pcidas.c unsigned int val = data[insn->n - 1]; val 606 drivers/staging/comedi/drivers/cb_pcidas.c if (s->readback[chan] != val) { val 607 drivers/staging/comedi/drivers/cb_pcidas.c cb_pcidas_dac08_write(dev, val); val 608 drivers/staging/comedi/drivers/cb_pcidas.c s->readback[chan] = val; val 616 drivers/staging/comedi/drivers/cb_pcidas.c unsigned int chan, unsigned int val) val 622 drivers/staging/comedi/drivers/cb_pcidas.c cb_pcidas_calib_write(dev, (chan << 8) | val, 10, true); val 625 drivers/staging/comedi/drivers/cb_pcidas.c cb_pcidas_calib_write(dev, val, 7, true); val 637 drivers/staging/comedi/drivers/cb_pcidas.c unsigned int val = data[insn->n - 1]; val 639 drivers/staging/comedi/drivers/cb_pcidas.c if (s->readback[chan] != val) { val 640 drivers/staging/comedi/drivers/cb_pcidas.c cb_pcidas_trimpot_write(dev, chan, val); val 641 drivers/staging/comedi/drivers/cb_pcidas.c s->readback[chan] = val; val 1168 drivers/staging/comedi/drivers/cb_pcidas.c unsigned short val; val 1174 drivers/staging/comedi/drivers/cb_pcidas.c val = inw(devpriv->pcibar2 + PCIDAS_AI_DATA_REG); val 1175 drivers/staging/comedi/drivers/cb_pcidas.c comedi_buf_write_samples(s, &val, 1); val 1380 drivers/staging/comedi/drivers/cb_pcidas.c unsigned int val = s->maxdata / 2; val 1383 drivers/staging/comedi/drivers/cb_pcidas.c cb_pcidas_calib_write(dev, (i << 8) | val, 11, false); val 1384 drivers/staging/comedi/drivers/cb_pcidas.c s->readback[i] = val; val 2725 drivers/staging/comedi/drivers/cb_pcidas64.c unsigned short val; val 2727 drivers/staging/comedi/drivers/cb_pcidas64.c val = readw(devpriv->main_iobase + ADC_FIFO_REG); val 2728 drivers/staging/comedi/drivers/cb_pcidas64.c comedi_buf_write_samples(s, &val, 1); val 2754 drivers/staging/comedi/drivers/cb_pcidas64.c unsigned short val; val 2757 drivers/staging/comedi/drivers/cb_pcidas64.c val = fifo_data & 0xffff; val 2758 drivers/staging/comedi/drivers/cb_pcidas64.c comedi_buf_write_samples(s, &val, 1); val 2761 drivers/staging/comedi/drivers/cb_pcidas64.c val = (fifo_data >> 16) & 0xffff; val 2762 drivers/staging/comedi/drivers/cb_pcidas64.c comedi_buf_write_samples(s, &val, 1); val 3102 drivers/staging/comedi/drivers/cb_pcidas64.c unsigned int val = s->readback[chan]; val 3115 drivers/staging/comedi/drivers/cb_pcidas64.c val = data[i]; val 3117 drivers/staging/comedi/drivers/cb_pcidas64.c writew(val & 0xff, val 3119 drivers/staging/comedi/drivers/cb_pcidas64.c writew((val >> 8) & 0xf, val 3122 drivers/staging/comedi/drivers/cb_pcidas64.c writew(val, val 3128 drivers/staging/comedi/drivers/cb_pcidas64.c s->readback[chan] = val; val 3640 drivers/staging/comedi/drivers/cb_pcidas64.c unsigned int val = data[insn->n - 1]; val 3642 drivers/staging/comedi/drivers/cb_pcidas64.c if (s->readback[chan] != val) { val 3643 drivers/staging/comedi/drivers/cb_pcidas64.c caldac_write(dev, chan, val); val 3644 drivers/staging/comedi/drivers/cb_pcidas64.c s->readback[chan] = val; val 3693 drivers/staging/comedi/drivers/cb_pcidas64.c unsigned int val = data[insn->n - 1]; val 3695 drivers/staging/comedi/drivers/cb_pcidas64.c if (s->readback[chan] != val) { val 3696 drivers/staging/comedi/drivers/cb_pcidas64.c ad8402_write(dev, chan, val); val 3697 drivers/staging/comedi/drivers/cb_pcidas64.c s->readback[chan] = val; val 3771 drivers/staging/comedi/drivers/cb_pcidas64.c unsigned int val; val 3776 drivers/staging/comedi/drivers/cb_pcidas64.c val = read_eeprom(dev, CR_CHAN(insn->chanspec)); val 3778 drivers/staging/comedi/drivers/cb_pcidas64.c data[i] = val; val 227 drivers/staging/comedi/drivers/cb_pcimdas.c unsigned int val = s->readback[chan]; val 231 drivers/staging/comedi/drivers/cb_pcimdas.c val = data[i]; val 232 drivers/staging/comedi/drivers/cb_pcimdas.c outw(val, devpriv->daqio + PCIMDAS_AO_REG(chan)); val 234 drivers/staging/comedi/drivers/cb_pcimdas.c s->readback[chan] = val; val 245 drivers/staging/comedi/drivers/cb_pcimdas.c unsigned int val; val 247 drivers/staging/comedi/drivers/cb_pcimdas.c val = inb(devpriv->BADR3 + PCIMDAS_DI_DO_REG); val 249 drivers/staging/comedi/drivers/cb_pcimdas.c data[1] = val & 0x0f; val 91 drivers/staging/comedi/drivers/cb_pcimdda.c unsigned int val = s->readback[chan]; val 95 drivers/staging/comedi/drivers/cb_pcimdda.c val = data[i]; val 106 drivers/staging/comedi/drivers/cb_pcimdda.c outb(val & 0x00ff, offset); val 107 drivers/staging/comedi/drivers/cb_pcimdda.c outb((val >> 8) & 0x00ff, offset + 1); val 109 drivers/staging/comedi/drivers/cb_pcimdda.c s->readback[chan] = val; val 127 drivers/staging/comedi/drivers/comedi_8254.c unsigned int val; val 133 drivers/staging/comedi/drivers/comedi_8254.c val = readb(i8254->mmio + reg_offset); val 135 drivers/staging/comedi/drivers/comedi_8254.c val = inb(i8254->iobase + reg_offset); val 139 drivers/staging/comedi/drivers/comedi_8254.c val = readw(i8254->mmio + reg_offset); val 141 drivers/staging/comedi/drivers/comedi_8254.c val = inw(i8254->iobase + reg_offset); val 145 drivers/staging/comedi/drivers/comedi_8254.c val = readl(i8254->mmio + reg_offset); val 147 drivers/staging/comedi/drivers/comedi_8254.c val = inl(i8254->iobase + reg_offset); val 150 drivers/staging/comedi/drivers/comedi_8254.c return val & 0xff; val 154 drivers/staging/comedi/drivers/comedi_8254.c unsigned int val, unsigned int reg) val 162 drivers/staging/comedi/drivers/comedi_8254.c writeb(val, i8254->mmio + reg_offset); val 164 drivers/staging/comedi/drivers/comedi_8254.c outb(val, i8254->iobase + reg_offset); val 168 drivers/staging/comedi/drivers/comedi_8254.c writew(val, i8254->mmio + reg_offset); val 170 drivers/staging/comedi/drivers/comedi_8254.c outw(val, i8254->iobase + reg_offset); val 174 drivers/staging/comedi/drivers/comedi_8254.c writel(val, i8254->mmio + reg_offset); val 176 drivers/staging/comedi/drivers/comedi_8254.c outl(val, i8254->iobase + reg_offset); val 207 drivers/staging/comedi/drivers/comedi_8254.c unsigned int val; val 217 drivers/staging/comedi/drivers/comedi_8254.c val = __i8254_read(i8254, counter); val 218 drivers/staging/comedi/drivers/comedi_8254.c val |= (__i8254_read(i8254, counter) << 8); val 220 drivers/staging/comedi/drivers/comedi_8254.c return val; val 231 drivers/staging/comedi/drivers/comedi_8254.c unsigned int counter, unsigned int val) val 237 drivers/staging/comedi/drivers/comedi_8254.c if (val > 0xffff) val 241 drivers/staging/comedi/drivers/comedi_8254.c byte = val & 0xff; val 243 drivers/staging/comedi/drivers/comedi_8254.c byte = (val >> 8) & 0xff; val 281 drivers/staging/comedi/drivers/comedi_8254.c unsigned int val, unsigned int mode) val 285 drivers/staging/comedi/drivers/comedi_8254.c if (val > 0xffff) val 291 drivers/staging/comedi/drivers/comedi_8254.c comedi_8254_write(i8254, counter, val); val 103 drivers/staging/comedi/drivers/comedi_8254.h unsigned int counter, unsigned int val); val 108 drivers/staging/comedi/drivers/comedi_8254.h unsigned int counter, unsigned int val, unsigned int mode); val 75 drivers/staging/comedi/drivers/dac02.c unsigned int val; val 79 drivers/staging/comedi/drivers/dac02.c val = data[i]; val 81 drivers/staging/comedi/drivers/dac02.c s->readback[chan] = val; val 89 drivers/staging/comedi/drivers/dac02.c val = s->maxdata - val; val 95 drivers/staging/comedi/drivers/dac02.c outb((val << 4) & 0xf0, dev->iobase + DAC02_AO_LSB(chan)); val 96 drivers/staging/comedi/drivers/dac02.c outb((val >> 4) & 0xff, dev->iobase + DAC02_AO_MSB(chan)); val 403 drivers/staging/comedi/drivers/daqboard2000.c unsigned int val = data[i]; val 406 drivers/staging/comedi/drivers/daqboard2000.c writew(val, dev->mmio + DB2K_REG_DAC_SETTING(chan)); val 412 drivers/staging/comedi/drivers/daqboard2000.c s->readback[chan] = val; val 624 drivers/staging/comedi/drivers/daqboard2000.c unsigned int val; val 631 drivers/staging/comedi/drivers/daqboard2000.c val = readw(dev->mmio + DB2K_REG_DAC_STATUS); val 632 drivers/staging/comedi/drivers/daqboard2000.c if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0) val 641 drivers/staging/comedi/drivers/daqboard2000.c val = readw(dev->mmio + DB2K_REG_DAC_STATUS); val 642 drivers/staging/comedi/drivers/daqboard2000.c if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0) val 331 drivers/staging/comedi/drivers/das08.c unsigned int val = s->readback[chan]; val 335 drivers/staging/comedi/drivers/das08.c val = data[i]; val 336 drivers/staging/comedi/drivers/das08.c das08_ao_set_data(dev, chan, val); val 338 drivers/staging/comedi/drivers/das08.c s->readback[chan] = val; val 829 drivers/staging/comedi/drivers/das16.c unsigned int val; val 844 drivers/staging/comedi/drivers/das16.c val = inb(dev->iobase + DAS16_AI_MSB_REG) << 8; val 845 drivers/staging/comedi/drivers/das16.c val |= inb(dev->iobase + DAS16_AI_LSB_REG); val 847 drivers/staging/comedi/drivers/das16.c val >>= 4; val 848 drivers/staging/comedi/drivers/das16.c val &= s->maxdata; val 850 drivers/staging/comedi/drivers/das16.c data[i] = val; val 865 drivers/staging/comedi/drivers/das16.c unsigned int val = data[i]; val 867 drivers/staging/comedi/drivers/das16.c s->readback[chan] = val; val 869 drivers/staging/comedi/drivers/das16.c val <<= 4; val 871 drivers/staging/comedi/drivers/das16.c outb(val & 0xff, dev->iobase + DAS16_AO_LSB_REG(chan)); val 872 drivers/staging/comedi/drivers/das16.c outb((val >> 8) & 0xff, dev->iobase + DAS16_AO_MSB_REG(chan)); val 333 drivers/staging/comedi/drivers/das16m1.c unsigned short val; val 344 drivers/staging/comedi/drivers/das16m1.c val = inw(dev->iobase + DAS16M1_AI_REG); val 345 drivers/staging/comedi/drivers/das16m1.c data[i] = DAS16M1_AI_TO_SAMPLE(val); val 823 drivers/staging/comedi/drivers/das1800.c unsigned short val; val 825 drivers/staging/comedi/drivers/das1800.c val = chan | ((range & 0x3) << 8); val 826 drivers/staging/comedi/drivers/das1800.c outw(val, dev->iobase + DAS1800_QRAM); val 998 drivers/staging/comedi/drivers/das1800.c unsigned int val = data[i]; val 1000 drivers/staging/comedi/drivers/das1800.c s->readback[chan] = val; val 1002 drivers/staging/comedi/drivers/das1800.c val = comedi_offset_munge(s, val); val 1006 drivers/staging/comedi/drivers/das1800.c outw(val, dev->iobase + DAS1800_DAC); val 1010 drivers/staging/comedi/drivers/das1800.c val = comedi_offset_munge(s, s->readback[update_chan]); val 1013 drivers/staging/comedi/drivers/das1800.c outw(val, dev->iobase + DAS1800_DAC); val 144 drivers/staging/comedi/drivers/das6402.c unsigned int val) val 147 drivers/staging/comedi/drivers/das6402.c outb(DAS6402_STATUS_W_EXTEND | val, dev->iobase + DAS6402_STATUS_REG); val 148 drivers/staging/comedi/drivers/das6402.c outb(val, dev->iobase + DAS6402_STATUS_REG); val 166 drivers/staging/comedi/drivers/das6402.c unsigned int val; val 168 drivers/staging/comedi/drivers/das6402.c val = inw(dev->iobase + DAS6402_AI_DATA_REG); val 170 drivers/staging/comedi/drivers/das6402.c val >>= 4; val 171 drivers/staging/comedi/drivers/das6402.c return val; val 189 drivers/staging/comedi/drivers/das6402.c unsigned int val; val 191 drivers/staging/comedi/drivers/das6402.c val = das6402_ai_read_sample(dev, s); val 192 drivers/staging/comedi/drivers/das6402.c comedi_buf_write_samples(s, &val, 1); val 424 drivers/staging/comedi/drivers/das6402.c unsigned int val; val 428 drivers/staging/comedi/drivers/das6402.c val = devpriv->ao_range; val 429 drivers/staging/comedi/drivers/das6402.c val &= ~DAS6402_AO_RANGE_MASK(chan); val 430 drivers/staging/comedi/drivers/das6402.c val |= DAS6402_AO_RANGE(chan, range); val 431 drivers/staging/comedi/drivers/das6402.c if (val != devpriv->ao_range) { val 432 drivers/staging/comedi/drivers/das6402.c devpriv->ao_range = val; val 433 drivers/staging/comedi/drivers/das6402.c outb(val, dev->iobase + DAS6402_TRIG_REG); val 449 drivers/staging/comedi/drivers/das6402.c val = data[i]; val 451 drivers/staging/comedi/drivers/das6402.c s->readback[chan] = val; val 459 drivers/staging/comedi/drivers/das6402.c val <<= 4; val 460 drivers/staging/comedi/drivers/das6402.c outw(val, dev->iobase + DAS6402_AO_DATA_REG(chan)); val 466 drivers/staging/comedi/drivers/das6402.c outb(val & 0xff, val 468 drivers/staging/comedi/drivers/das6402.c outb((val >> 8) & 0xff, val 212 drivers/staging/comedi/drivers/das800.c unsigned int val, unsigned int reg) val 219 drivers/staging/comedi/drivers/das800.c outb(val, dev->iobase + 2); val 430 drivers/staging/comedi/drivers/das800.c unsigned int val; val 458 drivers/staging/comedi/drivers/das800.c val = das800_ai_get_sample(dev); val 460 drivers/staging/comedi/drivers/das800.c fifo_empty = !!(val & FIFO_EMPTY); val 461 drivers/staging/comedi/drivers/das800.c fifo_overflow = !!(val & FIFO_OVF); val 472 drivers/staging/comedi/drivers/das800.c val >>= 4; /* 12-bit sample */ val 474 drivers/staging/comedi/drivers/das800.c val &= s->maxdata; val 475 drivers/staging/comedi/drivers/das800.c comedi_buf_write_samples(s, &val, 1); val 530 drivers/staging/comedi/drivers/das800.c unsigned int val; val 557 drivers/staging/comedi/drivers/das800.c val = das800_ai_get_sample(dev); val 559 drivers/staging/comedi/drivers/das800.c val >>= 4; /* 12-bit sample */ val 560 drivers/staging/comedi/drivers/das800.c data[i] = val & s->maxdata; val 181 drivers/staging/comedi/drivers/dmm32at.c unsigned int val; val 183 drivers/staging/comedi/drivers/dmm32at.c val = inb(dev->iobase + DMM32AT_AI_LSB_REG); val 184 drivers/staging/comedi/drivers/dmm32at.c val |= (inb(dev->iobase + DMM32AT_AI_MSB_REG) << 8); val 187 drivers/staging/comedi/drivers/dmm32at.c return comedi_offset_munge(s, val); val 407 drivers/staging/comedi/drivers/dmm32at.c unsigned int val; val 422 drivers/staging/comedi/drivers/dmm32at.c val = dmm32at_ai_get_sample(dev, s); val 423 drivers/staging/comedi/drivers/dmm32at.c comedi_buf_write_samples(s, &val, 1); val 460 drivers/staging/comedi/drivers/dmm32at.c unsigned int val = data[i]; val 464 drivers/staging/comedi/drivers/dmm32at.c outb(val & 0xff, dev->iobase + DMM32AT_AO_LSB_REG); val 465 drivers/staging/comedi/drivers/dmm32at.c outb((val >> 8) | DMM32AT_AO_MSB_DACH(chan), val 476 drivers/staging/comedi/drivers/dmm32at.c s->readback[chan] = val; val 491 drivers/staging/comedi/drivers/dt2801.c unsigned int val = 0; val 501 drivers/staging/comedi/drivers/dt2801.c dt2801_readdata(dev, &val); val 503 drivers/staging/comedi/drivers/dt2801.c data[1] = val; val 185 drivers/staging/comedi/drivers/dt2811.c unsigned int val; val 187 drivers/staging/comedi/drivers/dt2811.c val = inb(dev->iobase + DT2811_ADDATA_LO_REG) | val 190 drivers/staging/comedi/drivers/dt2811.c return val & s->maxdata; val 214 drivers/staging/comedi/drivers/dt2811.c unsigned short val; val 216 drivers/staging/comedi/drivers/dt2811.c val = dt2811_ai_read_sample(dev, s); val 217 drivers/staging/comedi/drivers/dt2811.c comedi_buf_write_samples(s, &val, 1); val 501 drivers/staging/comedi/drivers/dt2811.c unsigned int val = s->readback[chan]; val 505 drivers/staging/comedi/drivers/dt2811.c val = data[i]; val 506 drivers/staging/comedi/drivers/dt2811.c outb(val & 0xff, dev->iobase + DT2811_DADATA_LO_REG(chan)); val 507 drivers/staging/comedi/drivers/dt2811.c outb((val >> 8) & 0xff, val 510 drivers/staging/comedi/drivers/dt2811.c s->readback[chan] = val; val 77 drivers/staging/comedi/drivers/dt2817.c unsigned int val; val 91 drivers/staging/comedi/drivers/dt2817.c val = inb(iobase + 0); val 92 drivers/staging/comedi/drivers/dt2817.c val |= (inb(iobase + 1) << 8); val 93 drivers/staging/comedi/drivers/dt2817.c val |= (inb(iobase + 2) << 16); val 94 drivers/staging/comedi/drivers/dt2817.c val |= (inb(iobase + 3) << 24); val 96 drivers/staging/comedi/drivers/dt2817.c data[1] = val; val 405 drivers/staging/comedi/drivers/dt282x.c unsigned int val; val 413 drivers/staging/comedi/drivers/dt282x.c val = buf[i]; val 414 drivers/staging/comedi/drivers/dt282x.c val &= s->maxdata; val 416 drivers/staging/comedi/drivers/dt282x.c val = comedi_offset_munge(s, val); val 418 drivers/staging/comedi/drivers/dt282x.c buf[i] = val; val 621 drivers/staging/comedi/drivers/dt282x.c unsigned int val; val 647 drivers/staging/comedi/drivers/dt282x.c val = inw(dev->iobase + DT2821_ADDAT_REG); val 648 drivers/staging/comedi/drivers/dt282x.c val &= s->maxdata; val 650 drivers/staging/comedi/drivers/dt282x.c val = comedi_offset_munge(s, val); val 652 drivers/staging/comedi/drivers/dt282x.c data[i] = val; val 807 drivers/staging/comedi/drivers/dt282x.c unsigned int val = data[i]; val 809 drivers/staging/comedi/drivers/dt282x.c s->readback[chan] = val; val 812 drivers/staging/comedi/drivers/dt282x.c val = comedi_offset_munge(s, val); val 816 drivers/staging/comedi/drivers/dt282x.c outw(val, dev->iobase + DT2821_DADAT_REG); val 530 drivers/staging/comedi/drivers/dt3000.c unsigned int val = s->readback[chan]; val 534 drivers/staging/comedi/drivers/dt3000.c val = data[i]; val 535 drivers/staging/comedi/drivers/dt3000.c dt3k_writesingle(dev, DPR_SUBSYS_AO, chan, val); val 537 drivers/staging/comedi/drivers/dt3000.c s->readback[chan] = val; val 435 drivers/staging/comedi/drivers/dt9812.c u8 val[3]; val 456 drivers/staging/comedi/drivers/dt9812.c ret = dt9812_read_multiple_registers(dev, 3, reg, val); val 469 drivers/staging/comedi/drivers/dt9812.c if ((val[0] & (F020_MASK_ADC0CN_AD0INT | F020_MASK_ADC0CN_AD0BUSY)) == val 478 drivers/staging/comedi/drivers/dt9812.c *value = ((val[1] << 8) | val[2]) + 0x800; val 481 drivers/staging/comedi/drivers/dt9812.c *value = (val[1] << 8) | val[2]; val 578 drivers/staging/comedi/drivers/dt9812.c u16 val = 0; val 583 drivers/staging/comedi/drivers/dt9812.c ret = dt9812_analog_in(dev, chan, &val, DT9812_GAIN_1); val 586 drivers/staging/comedi/drivers/dt9812.c data[i] = val; val 616 drivers/staging/comedi/drivers/dt9812.c unsigned int val = data[i]; val 619 drivers/staging/comedi/drivers/dt9812.c ret = dt9812_analog_out(dev, chan, val); val 623 drivers/staging/comedi/drivers/dt9812.c s->readback[chan] = val; val 56 drivers/staging/comedi/drivers/fl512.c unsigned int val; val 67 drivers/staging/comedi/drivers/fl512.c val = inb(dev->iobase + FL512_AI_LSB_REG); val 68 drivers/staging/comedi/drivers/fl512.c val |= (inb(dev->iobase + FL512_AI_MSB_REG) << 8); val 69 drivers/staging/comedi/drivers/fl512.c val &= s->maxdata; val 71 drivers/staging/comedi/drivers/fl512.c data[i] = val; val 83 drivers/staging/comedi/drivers/fl512.c unsigned int val = s->readback[chan]; val 87 drivers/staging/comedi/drivers/fl512.c val = data[i]; val 90 drivers/staging/comedi/drivers/fl512.c outb(val & 0x0ff, dev->iobase + FL512_AO_DATA_REG(chan)); val 91 drivers/staging/comedi/drivers/fl512.c outb((val >> 8) & 0xf, dev->iobase + FL512_AO_DATA_REG(chan)); val 94 drivers/staging/comedi/drivers/fl512.c s->readback[chan] = val; val 170 drivers/staging/comedi/drivers/icp_multi.c unsigned int val = data[i]; val 178 drivers/staging/comedi/drivers/icp_multi.c writew(val, dev->mmio + ICP_MULTI_AO); val 184 drivers/staging/comedi/drivers/icp_multi.c s->readback[chan] = val; val 153 drivers/staging/comedi/drivers/ii_pci20kc.c unsigned int val = data[i]; val 155 drivers/staging/comedi/drivers/ii_pci20kc.c s->readback[chan] = val; val 158 drivers/staging/comedi/drivers/ii_pci20kc.c val = comedi_offset_munge(s, val); val 160 drivers/staging/comedi/drivers/ii_pci20kc.c writeb(val & 0xff, iobase + II20K_AO_LSB_REG(chan)); val 161 drivers/staging/comedi/drivers/ii_pci20kc.c writeb((val >> 8) & 0xff, iobase + II20K_AO_MSB_REG(chan)); val 189 drivers/staging/comedi/drivers/ii_pci20kc.c unsigned char val; val 198 drivers/staging/comedi/drivers/ii_pci20kc.c val = (range < 3) ? II20K_AI_OPT_TIMEBASE(0) : II20K_AI_OPT_TIMEBASE(2); val 199 drivers/staging/comedi/drivers/ii_pci20kc.c writeb(val, iobase + II20K_AI_OPT_REG); val 202 drivers/staging/comedi/drivers/ii_pci20kc.c val = (range < 2) ? 0x58 : (range < 3) ? 0x93 : 0x99; val 203 drivers/staging/comedi/drivers/ii_pci20kc.c writeb(val, iobase + II20K_AI_SET_TIME_REG); val 209 drivers/staging/comedi/drivers/ii_pci20kc.c val = II20K_AI_CHANLIST_ONBOARD_ONLY | val 213 drivers/staging/comedi/drivers/ii_pci20kc.c writeb(val, iobase + II20K_AI_CHANLIST_REG); val 234 drivers/staging/comedi/drivers/ii_pci20kc.c unsigned int val; val 243 drivers/staging/comedi/drivers/ii_pci20kc.c val = readb(iobase + II20K_AI_LSB_REG); val 244 drivers/staging/comedi/drivers/ii_pci20kc.c val |= (readb(iobase + II20K_AI_MSB_REG) << 8); val 247 drivers/staging/comedi/drivers/ii_pci20kc.c data[i] = comedi_offset_munge(s, val); val 220 drivers/staging/comedi/drivers/jr3_pci.c unsigned int val = 0; val 231 drivers/staging/comedi/drivers/jr3_pci.c val = get_s16(&spriv->sensor->filter[filter].fx); val 234 drivers/staging/comedi/drivers/jr3_pci.c val = get_s16(&spriv->sensor->filter[filter].fy); val 237 drivers/staging/comedi/drivers/jr3_pci.c val = get_s16(&spriv->sensor->filter[filter].fz); val 240 drivers/staging/comedi/drivers/jr3_pci.c val = get_s16(&spriv->sensor->filter[filter].mx); val 243 drivers/staging/comedi/drivers/jr3_pci.c val = get_s16(&spriv->sensor->filter[filter].my); val 246 drivers/staging/comedi/drivers/jr3_pci.c val = get_s16(&spriv->sensor->filter[filter].mz); val 249 drivers/staging/comedi/drivers/jr3_pci.c val = get_s16(&spriv->sensor->filter[filter].v1); val 252 drivers/staging/comedi/drivers/jr3_pci.c val = get_s16(&spriv->sensor->filter[filter].v2); val 255 drivers/staging/comedi/drivers/jr3_pci.c val += 0x4000; val 257 drivers/staging/comedi/drivers/jr3_pci.c val = get_u16(&spriv->sensor->model_no); val 259 drivers/staging/comedi/drivers/jr3_pci.c val = get_u16(&spriv->sensor->serial_no); val 262 drivers/staging/comedi/drivers/jr3_pci.c return val; val 308 drivers/staging/comedi/drivers/jr3_pci.c unsigned int *val) val 313 drivers/staging/comedi/drivers/jr3_pci.c if (pos && val) { val 318 drivers/staging/comedi/drivers/jr3_pci.c *val = 0; val 323 drivers/staging/comedi/drivers/jr3_pci.c *val = (*val << 4) + value; val 12 drivers/staging/comedi/drivers/jr3_pci.h static inline void set_u16(u32 __iomem *p, u16 val) val 14 drivers/staging/comedi/drivers/jr3_pci.h writel(val, p); val 22 drivers/staging/comedi/drivers/jr3_pci.h static inline void set_s16(s32 __iomem *p, s16 val) val 24 drivers/staging/comedi/drivers/jr3_pci.h writel(val, p); val 47 drivers/staging/comedi/drivers/ke_counter.c unsigned int val; val 51 drivers/staging/comedi/drivers/ke_counter.c val = data[0]; val 54 drivers/staging/comedi/drivers/ke_counter.c outb((val >> 24) & 0xff, dev->iobase + KE_SIGN_REG(chan)); val 55 drivers/staging/comedi/drivers/ke_counter.c outb((val >> 16) & 0xff, dev->iobase + KE_MSB_REG(chan)); val 56 drivers/staging/comedi/drivers/ke_counter.c outb((val >> 8) & 0xff, dev->iobase + KE_MID_REG(chan)); val 57 drivers/staging/comedi/drivers/ke_counter.c outb((val >> 0) & 0xff, dev->iobase + KE_LSB_REG(chan)); val 69 drivers/staging/comedi/drivers/ke_counter.c unsigned int val; val 76 drivers/staging/comedi/drivers/ke_counter.c val = inb(dev->iobase + KE_LSB_REG(chan)); val 77 drivers/staging/comedi/drivers/ke_counter.c val |= (inb(dev->iobase + KE_MID_REG(chan)) << 8); val 78 drivers/staging/comedi/drivers/ke_counter.c val |= (inb(dev->iobase + KE_MSB_REG(chan)) << 16); val 79 drivers/staging/comedi/drivers/ke_counter.c val |= (inb(dev->iobase + KE_SIGN_REG(chan)) << 24); val 81 drivers/staging/comedi/drivers/ke_counter.c data[i] = val; val 316 drivers/staging/comedi/drivers/me4000.c unsigned int val; val 329 drivers/staging/comedi/drivers/me4000.c val = inl(devpriv->plx_regbase + PLX9052_CNTRL); val 330 drivers/staging/comedi/drivers/me4000.c val |= PLX9052_CNTRL_UIO2_DATA; val 331 drivers/staging/comedi/drivers/me4000.c outl(val, devpriv->plx_regbase + PLX9052_CNTRL); val 338 drivers/staging/comedi/drivers/me4000.c val = inl(devpriv->plx_regbase + PLX9052_INTCSR); val 339 drivers/staging/comedi/drivers/me4000.c if (!(val & PLX9052_INTCSR_LI2STAT)) { val 345 drivers/staging/comedi/drivers/me4000.c val = inl(devpriv->plx_regbase + PLX9052_CNTRL); val 346 drivers/staging/comedi/drivers/me4000.c val &= ~PLX9052_CNTRL_UIO2_DATA; val 347 drivers/staging/comedi/drivers/me4000.c outl(val, devpriv->plx_regbase + PLX9052_CNTRL); val 361 drivers/staging/comedi/drivers/me4000.c val = inl(devpriv->plx_regbase + PLX9052_CNTRL); val 362 drivers/staging/comedi/drivers/me4000.c if (val & PLX9052_CNTRL_UIO1_DATA) { val 370 drivers/staging/comedi/drivers/me4000.c val = inl(devpriv->plx_regbase + PLX9052_CNTRL); val 371 drivers/staging/comedi/drivers/me4000.c if (!(val & PLX9052_CNTRL_UIO0_DATA)) { val 378 drivers/staging/comedi/drivers/me4000.c val = inl(devpriv->plx_regbase + PLX9052_CNTRL); val 379 drivers/staging/comedi/drivers/me4000.c val |= PLX9052_CNTRL_UIO2_DATA; val 380 drivers/staging/comedi/drivers/me4000.c outl(val, devpriv->plx_regbase + PLX9052_CNTRL); val 401 drivers/staging/comedi/drivers/me4000.c unsigned int val; val 408 drivers/staging/comedi/drivers/me4000.c val = inl(devpriv->plx_regbase + PLX9052_CNTRL); val 409 drivers/staging/comedi/drivers/me4000.c val |= PLX9052_CNTRL_PCI_RESET; val 410 drivers/staging/comedi/drivers/me4000.c outl(val, devpriv->plx_regbase + PLX9052_CNTRL); val 411 drivers/staging/comedi/drivers/me4000.c val &= ~PLX9052_CNTRL_PCI_RESET; val 412 drivers/staging/comedi/drivers/me4000.c outl(val, devpriv->plx_regbase + PLX9052_CNTRL); val 421 drivers/staging/comedi/drivers/me4000.c val = ME4000_AO_CTRL_IMMEDIATE_STOP | ME4000_AO_CTRL_STOP; val 423 drivers/staging/comedi/drivers/me4000.c outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan)); val 440 drivers/staging/comedi/drivers/me4000.c unsigned int val; val 443 drivers/staging/comedi/drivers/me4000.c val = inl(dev->iobase + ME4000_AI_DATA_REG); val 444 drivers/staging/comedi/drivers/me4000.c return comedi_offset_munge(s, val); val 508 drivers/staging/comedi/drivers/me4000.c unsigned int val; val 517 drivers/staging/comedi/drivers/me4000.c val = me4000_ai_get_sample(dev, s); val 518 drivers/staging/comedi/drivers/me4000.c data[i] = comedi_offset_munge(s, val); val 190 drivers/staging/comedi/drivers/me_daq.c unsigned int val; val 201 drivers/staging/comedi/drivers/me_daq.c val = s->state & 0xffff; val 203 drivers/staging/comedi/drivers/me_daq.c val = readw(mmio_porta); val 206 drivers/staging/comedi/drivers/me_daq.c val |= (s->state & 0xffff0000); val 208 drivers/staging/comedi/drivers/me_daq.c val |= (readw(mmio_portb) << 16); val 210 drivers/staging/comedi/drivers/me_daq.c data[1] = val; val 237 drivers/staging/comedi/drivers/me_daq.c unsigned int val; val 261 drivers/staging/comedi/drivers/me_daq.c val = ME_AI_FIFO_CHANLIST_CHAN(chan) | ME_AI_FIFO_CHANLIST_GAIN(range); val 263 drivers/staging/comedi/drivers/me_daq.c val |= ME_AI_FIFO_CHANLIST_UNIPOLAR; val 265 drivers/staging/comedi/drivers/me_daq.c val |= ME_AI_FIFO_CHANLIST_DIFF; val 266 drivers/staging/comedi/drivers/me_daq.c writew(val, dev->mmio + ME_AI_FIFO_REG); val 282 drivers/staging/comedi/drivers/me_daq.c val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata; val 285 drivers/staging/comedi/drivers/me_daq.c data[i] = comedi_offset_munge(s, val); val 303 drivers/staging/comedi/drivers/me_daq.c unsigned int val = s->readback[chan]; val 327 drivers/staging/comedi/drivers/me_daq.c val = data[i]; val 329 drivers/staging/comedi/drivers/me_daq.c writew(val, dev->mmio + ME_AO_DATA_REG(chan)); val 331 drivers/staging/comedi/drivers/me_daq.c s->readback[chan] = val; val 161 drivers/staging/comedi/drivers/mf6x4.c unsigned int val = s->readback[chan]; val 171 drivers/staging/comedi/drivers/mf6x4.c val = data[i]; val 172 drivers/staging/comedi/drivers/mf6x4.c iowrite16(val, dev->mmio + MF6X4_DAC_REG(chan)); val 174 drivers/staging/comedi/drivers/mf6x4.c s->readback[chan] = val; val 100 drivers/staging/comedi/drivers/multiq3.c unsigned int val; val 120 drivers/staging/comedi/drivers/multiq3.c val = inb(dev->iobase + MULTIQ3_AI_REG) << 8; val 121 drivers/staging/comedi/drivers/multiq3.c val |= inb(dev->iobase + MULTIQ3_AI_REG); val 122 drivers/staging/comedi/drivers/multiq3.c val &= s->maxdata; val 125 drivers/staging/comedi/drivers/multiq3.c data[i] = comedi_offset_munge(s, val); val 137 drivers/staging/comedi/drivers/multiq3.c unsigned int val = s->readback[chan]; val 141 drivers/staging/comedi/drivers/multiq3.c val = data[i]; val 144 drivers/staging/comedi/drivers/multiq3.c outw(val, dev->iobase + MULTIQ3_AO_REG); val 147 drivers/staging/comedi/drivers/multiq3.c s->readback[chan] = val; val 180 drivers/staging/comedi/drivers/multiq3.c unsigned int val; val 195 drivers/staging/comedi/drivers/multiq3.c val = inb(dev->iobase + MULTIQ3_ENC_DATA_REG); val 196 drivers/staging/comedi/drivers/multiq3.c val |= (inb(dev->iobase + MULTIQ3_ENC_DATA_REG) << 8); val 197 drivers/staging/comedi/drivers/multiq3.c val |= (inb(dev->iobase + MULTIQ3_ENC_DATA_REG) << 16); val 214 drivers/staging/comedi/drivers/multiq3.c data[i] = (val + ((s->maxdata + 1) >> 1)) & s->maxdata; val 85 drivers/staging/comedi/drivers/ni_6527.c unsigned int val) val 89 drivers/staging/comedi/drivers/ni_6527.c if (val != devpriv->filter_interval) { val 90 drivers/staging/comedi/drivers/ni_6527.c writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0)); val 91 drivers/staging/comedi/drivers/ni_6527.c writeb((val >> 8) & 0xff, val 93 drivers/staging/comedi/drivers/ni_6527.c writeb((val >> 16) & 0x0f, val 98 drivers/staging/comedi/drivers/ni_6527.c devpriv->filter_interval = val; val 103 drivers/staging/comedi/drivers/ni_6527.c unsigned int val) val 105 drivers/staging/comedi/drivers/ni_6527.c writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0)); val 106 drivers/staging/comedi/drivers/ni_6527.c writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1)); val 107 drivers/staging/comedi/drivers/ni_6527.c writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2)); val 149 drivers/staging/comedi/drivers/ni_6527.c unsigned int val; val 151 drivers/staging/comedi/drivers/ni_6527.c val = readb(dev->mmio + NI6527_DI_REG(0)); val 152 drivers/staging/comedi/drivers/ni_6527.c val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8); val 153 drivers/staging/comedi/drivers/ni_6527.c val |= (readb(dev->mmio + NI6527_DI_REG(2)) << 16); val 155 drivers/staging/comedi/drivers/ni_6527.c data[1] = val; val 170 drivers/staging/comedi/drivers/ni_6527.c unsigned int val = s->state ^ 0xffffff; val 173 drivers/staging/comedi/drivers/ni_6527.c writeb(val & 0xff, dev->mmio + NI6527_DO_REG(0)); val 175 drivers/staging/comedi/drivers/ni_6527.c writeb((val >> 8) & 0xff, val 178 drivers/staging/comedi/drivers/ni_6527.c writeb((val >> 16) & 0xff, val 356 drivers/staging/comedi/drivers/ni_65xx.c unsigned int val; val 375 drivers/staging/comedi/drivers/ni_65xx.c val = readb(dev->mmio + NI_65XX_FILTER_ENA(port)); val 378 drivers/staging/comedi/drivers/ni_65xx.c val |= chan_mask; val 380 drivers/staging/comedi/drivers/ni_65xx.c val &= ~chan_mask; val 382 drivers/staging/comedi/drivers/ni_65xx.c writeb(val, dev->mmio + NI_65XX_FILTER_ENA(port)); val 402 drivers/staging/comedi/drivers/ni_65xx.c val = readb(dev->mmio + NI_65XX_IO_SEL_REG(port)); val 403 drivers/staging/comedi/drivers/ni_65xx.c data[1] = (val == NI_65XX_IO_SEL_INPUT) ? COMEDI_INPUT val 682 drivers/staging/comedi/drivers/ni_660x.c unsigned int val; val 688 drivers/staging/comedi/drivers/ni_660x.c val = ni_660x_read(dev, 0, NI660X_IO_CFG(chan)); val 689 drivers/staging/comedi/drivers/ni_660x.c val &= ~NI660X_IO_CFG_IN_SEL_MASK(chan); val 690 drivers/staging/comedi/drivers/ni_660x.c val |= NI660X_IO_CFG_IN_SEL(chan, value); val 691 drivers/staging/comedi/drivers/ni_660x.c ni_660x_write(dev, 0, val, NI660X_IO_CFG(chan)); val 78 drivers/staging/comedi/drivers/ni_670x.c unsigned int val = s->readback[chan]; val 92 drivers/staging/comedi/drivers/ni_670x.c val = data[i]; val 97 drivers/staging/comedi/drivers/ni_670x.c writel(val, dev->mmio + AO_VALUE_OFFSET); val 99 drivers/staging/comedi/drivers/ni_670x.c s->readback[chan] = val; val 132 drivers/staging/comedi/drivers/ni_at_ao.c unsigned int val = s->readback[chan]; val 139 drivers/staging/comedi/drivers/ni_at_ao.c val = data[i]; val 142 drivers/staging/comedi/drivers/ni_at_ao.c outw(comedi_offset_munge(s, val), val 145 drivers/staging/comedi/drivers/ni_at_ao.c s->readback[chan] = val; val 240 drivers/staging/comedi/drivers/ni_at_ao.c unsigned int val = data[insn->n - 1]; val 241 drivers/staging/comedi/drivers/ni_at_ao.c unsigned int bitstring = ((chan & 0x7) << 8) | val; val 259 drivers/staging/comedi/drivers/ni_at_ao.c s->readback[chan] = val; val 225 drivers/staging/comedi/drivers/ni_atmio16d.c unsigned short val; val 227 drivers/staging/comedi/drivers/ni_atmio16d.c val = inw(dev->iobase + AD_FIFO_REG); val 228 drivers/staging/comedi/drivers/ni_atmio16d.c comedi_buf_write_samples(s, &val, 1); val 525 drivers/staging/comedi/drivers/ni_atmio16d.c unsigned int val = data[i]; val 527 drivers/staging/comedi/drivers/ni_atmio16d.c s->readback[chan] = val; val 530 drivers/staging/comedi/drivers/ni_atmio16d.c val ^= 0x800; val 532 drivers/staging/comedi/drivers/ni_atmio16d.c outw(val, dev->iobase + reg); val 80 drivers/staging/comedi/drivers/ni_daq_700.c unsigned int val; val 88 drivers/staging/comedi/drivers/ni_daq_700.c val = s->state & 0xff; val 89 drivers/staging/comedi/drivers/ni_daq_700.c val |= inb(dev->iobase + DIO_R) << 8; val 91 drivers/staging/comedi/drivers/ni_daq_700.c data[1] = val; val 892 drivers/staging/comedi/drivers/ni_labpc_common.c unsigned int chan, unsigned int val) val 896 drivers/staging/comedi/drivers/ni_labpc_common.c devpriv->write_byte(dev, val & 0xff, DAC_LSB_REG(chan)); val 897 drivers/staging/comedi/drivers/ni_labpc_common.c devpriv->write_byte(dev, (val >> 8) & 0xff, DAC_MSB_REG(chan)); val 899 drivers/staging/comedi/drivers/ni_labpc_common.c s->readback[chan] = val; val 1133 drivers/staging/comedi/drivers/ni_labpc_common.c unsigned int val = data[insn->n - 1]; val 1135 drivers/staging/comedi/drivers/ni_labpc_common.c if (s->readback[chan] != val) { val 1136 drivers/staging/comedi/drivers/ni_labpc_common.c write_caldac(dev, chan, val); val 1137 drivers/staging/comedi/drivers/ni_labpc_common.c s->readback[chan] = val; val 1175 drivers/staging/comedi/drivers/ni_labpc_common.c unsigned int val = data[insn->n - 1]; val 1181 drivers/staging/comedi/drivers/ni_labpc_common.c labpc_eeprom_write(dev, chan, val); val 1182 drivers/staging/comedi/drivers/ni_labpc_common.c s->readback[chan] = val; val 475 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int val; val 478 drivers/staging/comedi/drivers/ni_mio_common.c val = m_series_stc_read(dev, reg); val 482 drivers/staging/comedi/drivers/ni_mio_common.c val = ni_readw(dev, reg * 2); val 485 drivers/staging/comedi/drivers/ni_mio_common.c val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG); val 489 drivers/staging/comedi/drivers/ni_mio_common.c return val; val 495 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int val; val 498 drivers/staging/comedi/drivers/ni_mio_common.c val = m_series_stc_read(dev, reg); val 500 drivers/staging/comedi/drivers/ni_mio_common.c val = ni_stc_readw(dev, reg) << 16; val 501 drivers/staging/comedi/drivers/ni_mio_common.c val |= ni_stc_readw(dev, reg + 1); val 503 drivers/staging/comedi/drivers/ni_mio_common.c return val; val 753 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int val = 0; val 766 drivers/staging/comedi/drivers/ni_mio_common.c val = NISTC_INTA_ENA_G0_GATE; val 770 drivers/staging/comedi/drivers/ni_mio_common.c val = NISTC_INTB_ENA_G1_GATE; val 772 drivers/staging/comedi/drivers/ni_mio_common.c ni_stc_writew(dev, val, reg); val 2530 drivers/staging/comedi/drivers/ni_mio_common.c unsigned short val = array[i]; val 2537 drivers/staging/comedi/drivers/ni_mio_common.c val = comedi_offset_munge(s, val); val 2539 drivers/staging/comedi/drivers/ni_mio_common.c buf = cpu_to_le16(val); val 2542 drivers/staging/comedi/drivers/ni_mio_common.c array[i] = val; val 2701 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int val = data[i]; val 2703 drivers/staging/comedi/drivers/ni_mio_common.c s->readback[chan] = val; val 2710 drivers/staging/comedi/drivers/ni_mio_common.c val = comedi_offset_munge(s, val); val 2712 drivers/staging/comedi/drivers/ni_mio_common.c ni_ao_win_outw(dev, val, reg); val 2718 drivers/staging/comedi/drivers/ni_mio_common.c ni_writew(dev, val, reg); val 2725 drivers/staging/comedi/drivers/ni_mio_common.c val = comedi_offset_munge(s, val); val 2727 drivers/staging/comedi/drivers/ni_mio_common.c ni_writew(dev, val, reg); val 4085 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout); val 4089 drivers/staging/comedi/drivers/ni_mio_common.c data[i] = val; val 4102 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int val = data[insn->n - 1]; val 4109 drivers/staging/comedi/drivers/ni_mio_common.c devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val); val 4292 drivers/staging/comedi/drivers/ni_mio_common.c static int pack_mb88341(int addr, int val, int *bitstring) val 4306 drivers/staging/comedi/drivers/ni_mio_common.c ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff); val 4310 drivers/staging/comedi/drivers/ni_mio_common.c static int pack_dac8800(int addr, int val, int *bitstring) val 4312 drivers/staging/comedi/drivers/ni_mio_common.c *bitstring = ((addr & 0x7) << 8) | (val & 0xff); val 4316 drivers/staging/comedi/drivers/ni_mio_common.c static int pack_dac8043(int addr, int val, int *bitstring) val 4318 drivers/staging/comedi/drivers/ni_mio_common.c *bitstring = val & 0xfff; val 4322 drivers/staging/comedi/drivers/ni_mio_common.c static int pack_ad8522(int addr, int val, int *bitstring) val 4324 drivers/staging/comedi/drivers/ni_mio_common.c *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000); val 4328 drivers/staging/comedi/drivers/ni_mio_common.c static int pack_ad8804(int addr, int val, int *bitstring) val 4330 drivers/staging/comedi/drivers/ni_mio_common.c *bitstring = ((addr & 0xf) << 8) | (val & 0xff); val 4334 drivers/staging/comedi/drivers/ni_mio_common.c static int pack_ad8842(int addr, int val, int *bitstring) val 4336 drivers/staging/comedi/drivers/ni_mio_common.c *bitstring = ((addr + 1) << 8) | (val & 0xff); val 4356 drivers/staging/comedi/drivers/ni_mio_common.c static void ni_write_caldac(struct comedi_device *dev, int addr, int val) val 4365 drivers/staging/comedi/drivers/ni_mio_common.c if (devpriv->caldacs[addr] == val) val 4367 drivers/staging/comedi/drivers/ni_mio_common.c devpriv->caldacs[addr] = val; val 4374 drivers/staging/comedi/drivers/ni_mio_common.c bits = caldacs[type].packbits(addr, val, &bitstring); val 4515 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int val; val 4519 drivers/staging/comedi/drivers/ni_mio_common.c val = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); val 4521 drivers/staging/comedi/drivers/ni_mio_common.c data[i] = val; val 4596 drivers/staging/comedi/drivers/ni_mio_common.c unsigned short val = devpriv->pfi_output_select_reg[index]; val 4601 drivers/staging/comedi/drivers/ni_mio_common.c val &= ~NI_M_PFI_OUT_SEL_MASK(chan); val 4602 drivers/staging/comedi/drivers/ni_mio_common.c val |= NI_M_PFI_OUT_SEL(chan, source); val 4603 drivers/staging/comedi/drivers/ni_mio_common.c ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index)); val 4604 drivers/staging/comedi/drivers/ni_mio_common.c devpriv->pfi_output_select_reg[index] = val; val 74 drivers/staging/comedi/drivers/ni_routing/ni_route_values.h #define Gi_SRC(val, subsel) ((val) | ((subsel) << 6)) val 1610 drivers/staging/comedi/drivers/ni_tio.c unsigned int val; val 1625 drivers/staging/comedi/drivers/ni_tio.c val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)); val 1626 drivers/staging/comedi/drivers/ni_tio.c if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx))) val 1627 drivers/staging/comedi/drivers/ni_tio.c val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)); val 1629 drivers/staging/comedi/drivers/ni_tio.c return val; val 166 drivers/staging/comedi/drivers/ni_usb6501.c unsigned int val, u8 *bitmap) val 184 drivers/staging/comedi/drivers/ni_usb6501.c tx[14] = val & 0xff; val 190 drivers/staging/comedi/drivers/ni_usb6501.c tx[14] = val & 0xff; val 197 drivers/staging/comedi/drivers/ni_usb6501.c tx[14] = val & 0xff; val 198 drivers/staging/comedi/drivers/ni_usb6501.c tx[15] = (val >> 8) & 0xff; val 199 drivers/staging/comedi/drivers/ni_usb6501.c tx[16] = (val >> 16) & 0xff; val 248 drivers/staging/comedi/drivers/ni_usb6501.c u32 *val) val 256 drivers/staging/comedi/drivers/ni_usb6501.c if ((command == READ_COUNTER || command == WRITE_COUNTER) && !val) val 283 drivers/staging/comedi/drivers/ni_usb6501.c *((__be32 *)&tx[12]) = cpu_to_be32(*val); val 317 drivers/staging/comedi/drivers/ni_usb6501.c *val = be32_to_cpu(*((__be32 *)&devpriv->usb_rx_buf[12])); val 395 drivers/staging/comedi/drivers/ni_usb6501.c u32 val = 0; val 408 drivers/staging/comedi/drivers/ni_usb6501.c ret = ni6501_counter_command(dev, WRITE_COUNTER, &val); val 423 drivers/staging/comedi/drivers/ni_usb6501.c u32 val; val 427 drivers/staging/comedi/drivers/ni_usb6501.c ret = ni6501_counter_command(dev, READ_COUNTER, &val); val 430 drivers/staging/comedi/drivers/ni_usb6501.c data[i] = val; val 444 drivers/staging/comedi/drivers/ni_usb6501.c u32 val = data[insn->n - 1]; val 446 drivers/staging/comedi/drivers/ni_usb6501.c ret = ni6501_counter_command(dev, WRITE_COUNTER, &val); val 166 drivers/staging/comedi/drivers/pcl711.c unsigned int val; val 168 drivers/staging/comedi/drivers/pcl711.c val = inb(dev->iobase + PCL711_AI_MSB_REG) << 8; val 169 drivers/staging/comedi/drivers/pcl711.c val |= inb(dev->iobase + PCL711_AI_LSB_REG); val 171 drivers/staging/comedi/drivers/pcl711.c return val & s->maxdata; val 358 drivers/staging/comedi/drivers/pcl711.c unsigned int chan, unsigned int val) val 360 drivers/staging/comedi/drivers/pcl711.c outb(val & 0xff, dev->iobase + PCL711_AO_LSB_REG(chan)); val 361 drivers/staging/comedi/drivers/pcl711.c outb((val >> 8) & 0xff, dev->iobase + PCL711_AO_MSB_REG(chan)); val 370 drivers/staging/comedi/drivers/pcl711.c unsigned int val = s->readback[chan]; val 374 drivers/staging/comedi/drivers/pcl711.c val = data[i]; val 375 drivers/staging/comedi/drivers/pcl711.c pcl711_ao_write(dev, chan, val); val 377 drivers/staging/comedi/drivers/pcl711.c s->readback[chan] = val; val 387 drivers/staging/comedi/drivers/pcl711.c unsigned int val; val 389 drivers/staging/comedi/drivers/pcl711.c val = inb(dev->iobase + PCL711_DI_LSB_REG); val 390 drivers/staging/comedi/drivers/pcl711.c val |= (inb(dev->iobase + PCL711_DI_MSB_REG) << 8); val 392 drivers/staging/comedi/drivers/pcl711.c data[1] = val; val 242 drivers/staging/comedi/drivers/pcl726.c unsigned int val = data[i]; val 244 drivers/staging/comedi/drivers/pcl726.c s->readback[chan] = val; val 248 drivers/staging/comedi/drivers/pcl726.c val = comedi_offset_munge(s, val); val 251 drivers/staging/comedi/drivers/pcl726.c outb((val >> 8) & 0xff, dev->iobase + PCL726_AO_MSB_REG(chan)); val 252 drivers/staging/comedi/drivers/pcl726.c outb(val & 0xff, dev->iobase + PCL726_AO_LSB_REG(chan)); val 264 drivers/staging/comedi/drivers/pcl726.c unsigned int val; val 267 drivers/staging/comedi/drivers/pcl726.c val = inb(dev->iobase + PCL727_DI_LSB_REG); val 268 drivers/staging/comedi/drivers/pcl726.c val |= (inb(dev->iobase + PCL727_DI_MSB_REG) << 8); val 270 drivers/staging/comedi/drivers/pcl726.c val = inb(dev->iobase + PCL726_DI_LSB_REG); val 271 drivers/staging/comedi/drivers/pcl726.c val |= (inb(dev->iobase + PCL726_DI_MSB_REG) << 8); val 274 drivers/staging/comedi/drivers/pcl726.c data[1] = val; val 241 drivers/staging/comedi/drivers/pcl730.c unsigned int val; val 243 drivers/staging/comedi/drivers/pcl730.c val = inb(dev->iobase + reg); val 245 drivers/staging/comedi/drivers/pcl730.c val |= (inb(dev->iobase + reg + 1) << 8); val 247 drivers/staging/comedi/drivers/pcl730.c val |= (inb(dev->iobase + reg + 2) << 16); val 249 drivers/staging/comedi/drivers/pcl730.c val |= (inb(dev->iobase + reg + 3) << 24); val 251 drivers/staging/comedi/drivers/pcl730.c return val; val 604 drivers/staging/comedi/drivers/pcl812.c unsigned int val; val 606 drivers/staging/comedi/drivers/pcl812.c val = inb(dev->iobase + PCL812_AI_MSB_REG) << 8; val 607 drivers/staging/comedi/drivers/pcl812.c val |= inb(dev->iobase + PCL812_AI_LSB_REG); val 609 drivers/staging/comedi/drivers/pcl812.c return val & s->maxdata; val 779 drivers/staging/comedi/drivers/pcl812.c unsigned short val; val 787 drivers/staging/comedi/drivers/pcl812.c val = pcl812_ai_get_sample(dev, s); val 788 drivers/staging/comedi/drivers/pcl812.c comedi_buf_write_samples(s, &val, 1); val 804 drivers/staging/comedi/drivers/pcl812.c unsigned short val; val 807 drivers/staging/comedi/drivers/pcl812.c val = ptr[bufptr++]; val 808 drivers/staging/comedi/drivers/pcl812.c comedi_buf_write_samples(s, &val, 1); val 946 drivers/staging/comedi/drivers/pcl812.c unsigned int val = s->readback[chan]; val 950 drivers/staging/comedi/drivers/pcl812.c val = data[i]; val 951 drivers/staging/comedi/drivers/pcl812.c outb(val & 0xff, dev->iobase + PCL812_AO_LSB_REG(chan)); val 952 drivers/staging/comedi/drivers/pcl812.c outb((val >> 8) & 0x0f, dev->iobase + PCL812_AO_MSB_REG(chan)); val 954 drivers/staging/comedi/drivers/pcl812.c s->readback[chan] = val; val 189 drivers/staging/comedi/drivers/pcl816.c unsigned int val; val 191 drivers/staging/comedi/drivers/pcl816.c val = inb(dev->iobase + PCL816_AI_MSB_REG) << 8; val 192 drivers/staging/comedi/drivers/pcl816.c val |= inb(dev->iobase + PCL816_AI_LSB_REG); val 194 drivers/staging/comedi/drivers/pcl816.c return val & s->maxdata; val 229 drivers/staging/comedi/drivers/pcl816.c unsigned short val; val 233 drivers/staging/comedi/drivers/pcl816.c val = ptr[bufptr++]; val 234 drivers/staging/comedi/drivers/pcl816.c comedi_buf_write_samples(s, &val, 1); val 385 drivers/staging/comedi/drivers/pcl818.c unsigned int val; val 387 drivers/staging/comedi/drivers/pcl818.c val = inb(dev->iobase + PCL818_FI_DATALO); val 388 drivers/staging/comedi/drivers/pcl818.c val |= (inb(dev->iobase + PCL818_FI_DATAHI) << 8); val 391 drivers/staging/comedi/drivers/pcl818.c *chan = val & 0xf; val 393 drivers/staging/comedi/drivers/pcl818.c return (val >> 4) & s->maxdata; val 400 drivers/staging/comedi/drivers/pcl818.c unsigned int val; val 402 drivers/staging/comedi/drivers/pcl818.c val = inb(dev->iobase + PCL818_AI_MSB_REG) << 8; val 403 drivers/staging/comedi/drivers/pcl818.c val |= inb(dev->iobase + PCL818_AI_LSB_REG); val 406 drivers/staging/comedi/drivers/pcl818.c *chan = val & 0xf; val 408 drivers/staging/comedi/drivers/pcl818.c return (val >> 4) & s->maxdata; val 426 drivers/staging/comedi/drivers/pcl818.c unsigned int chan, unsigned int val) val 443 drivers/staging/comedi/drivers/pcl818.c comedi_buf_write_samples(s, &val, 1); val 462 drivers/staging/comedi/drivers/pcl818.c unsigned int val; val 470 drivers/staging/comedi/drivers/pcl818.c val = pcl818_ai_get_sample(dev, s, &chan); val 471 drivers/staging/comedi/drivers/pcl818.c pcl818_ai_write_sample(dev, s, chan, val); val 483 drivers/staging/comedi/drivers/pcl818.c unsigned int val; val 491 drivers/staging/comedi/drivers/pcl818.c val = ptr[i]; val 492 drivers/staging/comedi/drivers/pcl818.c chan = val & 0xf; val 493 drivers/staging/comedi/drivers/pcl818.c val = (val >> 4) & s->maxdata; val 494 drivers/staging/comedi/drivers/pcl818.c if (!pcl818_ai_write_sample(dev, s, chan, val)) val 504 drivers/staging/comedi/drivers/pcl818.c unsigned int val; val 528 drivers/staging/comedi/drivers/pcl818.c val = pcl818_ai_get_fifo_sample(dev, s, &chan); val 529 drivers/staging/comedi/drivers/pcl818.c if (!pcl818_ai_write_sample(dev, s, chan, val)) val 836 drivers/staging/comedi/drivers/pcl818.c unsigned int val = s->readback[chan]; val 840 drivers/staging/comedi/drivers/pcl818.c val = data[i]; val 841 drivers/staging/comedi/drivers/pcl818.c outb((val & 0x000f) << 4, val 843 drivers/staging/comedi/drivers/pcl818.c outb((val & 0x0ff0) >> 4, val 846 drivers/staging/comedi/drivers/pcl818.c s->readback[chan] = val; val 74 drivers/staging/comedi/drivers/pcmad.c unsigned int val; val 85 drivers/staging/comedi/drivers/pcmad.c val = inb(dev->iobase + PCMAD_LSB) | val 90 drivers/staging/comedi/drivers/pcmad.c val >>= 4; val 94 drivers/staging/comedi/drivers/pcmad.c val ^= ((s->maxdata + 1) >> 1); val 97 drivers/staging/comedi/drivers/pcmad.c data[i] = val; val 65 drivers/staging/comedi/drivers/pcmda12.c unsigned int val = s->readback[chan]; val 70 drivers/staging/comedi/drivers/pcmda12.c val = data[i]; val 71 drivers/staging/comedi/drivers/pcmda12.c outb(val & 0xff, ioreg); val 72 drivers/staging/comedi/drivers/pcmda12.c outb((val >> 8) & 0xff, ioreg + 1); val 81 drivers/staging/comedi/drivers/pcmda12.c s->readback[chan] = val; val 185 drivers/staging/comedi/drivers/pcmmio.c static void pcmmio_dio_write(struct comedi_device *dev, unsigned int val, val 195 drivers/staging/comedi/drivers/pcmmio.c outb(val & 0xff, iobase + PCMMIO_PORT_REG(port + 0)); val 196 drivers/staging/comedi/drivers/pcmmio.c outb((val >> 8) & 0xff, iobase + PCMMIO_PORT_REG(port + 1)); val 197 drivers/staging/comedi/drivers/pcmmio.c outb((val >> 16) & 0xff, iobase + PCMMIO_PORT_REG(port + 2)); val 200 drivers/staging/comedi/drivers/pcmmio.c outb(val & 0xff, iobase + PCMMIO_PAGE_REG(0)); val 201 drivers/staging/comedi/drivers/pcmmio.c outb((val >> 8) & 0xff, iobase + PCMMIO_PAGE_REG(1)); val 202 drivers/staging/comedi/drivers/pcmmio.c outb((val >> 16) & 0xff, iobase + PCMMIO_PAGE_REG(2)); val 213 drivers/staging/comedi/drivers/pcmmio.c unsigned int val; val 218 drivers/staging/comedi/drivers/pcmmio.c val = inb(iobase + PCMMIO_PORT_REG(port + 0)); val 219 drivers/staging/comedi/drivers/pcmmio.c val |= (inb(iobase + PCMMIO_PORT_REG(port + 1)) << 8); val 220 drivers/staging/comedi/drivers/pcmmio.c val |= (inb(iobase + PCMMIO_PORT_REG(port + 2)) << 16); val 223 drivers/staging/comedi/drivers/pcmmio.c val = inb(iobase + PCMMIO_PAGE_REG(0)); val 224 drivers/staging/comedi/drivers/pcmmio.c val |= (inb(iobase + PCMMIO_PAGE_REG(1)) << 8); val 225 drivers/staging/comedi/drivers/pcmmio.c val |= (inb(iobase + PCMMIO_PAGE_REG(2)) << 16); val 229 drivers/staging/comedi/drivers/pcmmio.c return val; val 251 drivers/staging/comedi/drivers/pcmmio.c unsigned int val; val 263 drivers/staging/comedi/drivers/pcmmio.c val = ~s->state & chanmask; val 264 drivers/staging/comedi/drivers/pcmmio.c val &= s->io_bits; val 265 drivers/staging/comedi/drivers/pcmmio.c pcmmio_dio_write(dev, val, 0, port); val 269 drivers/staging/comedi/drivers/pcmmio.c val = pcmmio_dio_read(dev, 0, port); val 272 drivers/staging/comedi/drivers/pcmmio.c data[1] = ~val & chanmask; val 328 drivers/staging/comedi/drivers/pcmmio.c unsigned int val = 0; val 344 drivers/staging/comedi/drivers/pcmmio.c val |= (1 << i); val 347 drivers/staging/comedi/drivers/pcmmio.c comedi_buf_write_samples(s, &val, 1); val 540 drivers/staging/comedi/drivers/pcmmio.c unsigned int val; val 577 drivers/staging/comedi/drivers/pcmmio.c val = inb(iobase + PCMMIO_AI_LSB_REG); val 578 drivers/staging/comedi/drivers/pcmmio.c val |= inb(iobase + PCMMIO_AI_MSB_REG) << 8; val 587 drivers/staging/comedi/drivers/pcmmio.c val = inb(iobase + PCMMIO_AI_LSB_REG); val 588 drivers/staging/comedi/drivers/pcmmio.c val |= inb(iobase + PCMMIO_AI_MSB_REG) << 8; val 592 drivers/staging/comedi/drivers/pcmmio.c val = comedi_offset_munge(s, val); val 594 drivers/staging/comedi/drivers/pcmmio.c data[i] = val; val 647 drivers/staging/comedi/drivers/pcmmio.c unsigned int val = data[i]; val 650 drivers/staging/comedi/drivers/pcmmio.c outb(val & 0xff, iobase + PCMMIO_AO_LSB_REG); val 651 drivers/staging/comedi/drivers/pcmmio.c outb((val >> 8) & 0xff, iobase + PCMMIO_AO_MSB_REG); val 659 drivers/staging/comedi/drivers/pcmmio.c s->readback[chan] = val; val 153 drivers/staging/comedi/drivers/pcmuio.c static void pcmuio_write(struct comedi_device *dev, unsigned int val, val 164 drivers/staging/comedi/drivers/pcmuio.c outb(val & 0xff, iobase + PCMUIO_PORT_REG(port + 0)); val 165 drivers/staging/comedi/drivers/pcmuio.c outb((val >> 8) & 0xff, iobase + PCMUIO_PORT_REG(port + 1)); val 166 drivers/staging/comedi/drivers/pcmuio.c outb((val >> 16) & 0xff, iobase + PCMUIO_PORT_REG(port + 2)); val 169 drivers/staging/comedi/drivers/pcmuio.c outb(val & 0xff, iobase + PCMUIO_PAGE_REG(0)); val 170 drivers/staging/comedi/drivers/pcmuio.c outb((val >> 8) & 0xff, iobase + PCMUIO_PAGE_REG(1)); val 171 drivers/staging/comedi/drivers/pcmuio.c outb((val >> 16) & 0xff, iobase + PCMUIO_PAGE_REG(2)); val 183 drivers/staging/comedi/drivers/pcmuio.c unsigned int val; val 188 drivers/staging/comedi/drivers/pcmuio.c val = inb(iobase + PCMUIO_PORT_REG(port + 0)); val 189 drivers/staging/comedi/drivers/pcmuio.c val |= (inb(iobase + PCMUIO_PORT_REG(port + 1)) << 8); val 190 drivers/staging/comedi/drivers/pcmuio.c val |= (inb(iobase + PCMUIO_PORT_REG(port + 2)) << 16); val 193 drivers/staging/comedi/drivers/pcmuio.c val = inb(iobase + PCMUIO_PAGE_REG(0)); val 194 drivers/staging/comedi/drivers/pcmuio.c val |= (inb(iobase + PCMUIO_PAGE_REG(1)) << 8); val 195 drivers/staging/comedi/drivers/pcmuio.c val |= (inb(iobase + PCMUIO_PAGE_REG(2)) << 16); val 199 drivers/staging/comedi/drivers/pcmuio.c return val; val 221 drivers/staging/comedi/drivers/pcmuio.c unsigned int val; val 233 drivers/staging/comedi/drivers/pcmuio.c val = ~s->state & chanmask; val 234 drivers/staging/comedi/drivers/pcmuio.c val &= s->io_bits; val 235 drivers/staging/comedi/drivers/pcmuio.c pcmuio_write(dev, val, asic, 0, port); val 239 drivers/staging/comedi/drivers/pcmuio.c val = pcmuio_read(dev, asic, 0, port); val 242 drivers/staging/comedi/drivers/pcmuio.c data[1] = ~val & chanmask; val 307 drivers/staging/comedi/drivers/pcmuio.c unsigned int val = 0; val 323 drivers/staging/comedi/drivers/pcmuio.c val |= (1 << i); val 326 drivers/staging/comedi/drivers/pcmuio.c comedi_buf_write_samples(s, &val, 1); val 343 drivers/staging/comedi/drivers/pcmuio.c unsigned int val; val 346 drivers/staging/comedi/drivers/pcmuio.c val = inb(iobase + PCMUIO_INT_PENDING_REG) & 0x07; val 347 drivers/staging/comedi/drivers/pcmuio.c if (!val) val 351 drivers/staging/comedi/drivers/pcmuio.c val = pcmuio_read(dev, asic, PCMUIO_PAGE_INT_ID, 0); val 355 drivers/staging/comedi/drivers/pcmuio.c pcmuio_handle_intr_subdev(dev, s, val); val 200 drivers/staging/comedi/drivers/quatech_daqp_cs.c unsigned int val; val 206 drivers/staging/comedi/drivers/quatech_daqp_cs.c val = inb(dev->iobase + DAQP_AI_FIFO_REG); val 207 drivers/staging/comedi/drivers/quatech_daqp_cs.c val |= inb(dev->iobase + DAQP_AI_FIFO_REG) << 8; val 208 drivers/staging/comedi/drivers/quatech_daqp_cs.c return comedi_offset_munge(s, val); val 268 drivers/staging/comedi/drivers/quatech_daqp_cs.c unsigned int val; val 270 drivers/staging/comedi/drivers/quatech_daqp_cs.c val = DAQP_SCANLIST_CHANNEL(chan) | DAQP_SCANLIST_GAIN(range); val 273 drivers/staging/comedi/drivers/quatech_daqp_cs.c val |= DAQP_SCANLIST_DIFFERENTIAL; val 276 drivers/staging/comedi/drivers/quatech_daqp_cs.c val |= DAQP_SCANLIST_START; val 278 drivers/staging/comedi/drivers/quatech_daqp_cs.c outb(val & 0xff, dev->iobase + DAQP_SCANLIST_REG); val 279 drivers/staging/comedi/drivers/quatech_daqp_cs.c outb((val >> 8) & 0xff, dev->iobase + DAQP_SCANLIST_REG); val 364 drivers/staging/comedi/drivers/quatech_daqp_cs.c static void daqp_set_pacer(struct comedi_device *dev, unsigned int val) val 366 drivers/staging/comedi/drivers/quatech_daqp_cs.c outb(val & 0xff, dev->iobase + DAQP_PACER_LOW_REG); val 367 drivers/staging/comedi/drivers/quatech_daqp_cs.c outb((val >> 8) & 0xff, dev->iobase + DAQP_PACER_MID_REG); val 368 drivers/staging/comedi/drivers/quatech_daqp_cs.c outb((val >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH_REG); val 647 drivers/staging/comedi/drivers/quatech_daqp_cs.c unsigned int val = data[i]; val 656 drivers/staging/comedi/drivers/quatech_daqp_cs.c outw((chan << 12) | comedi_offset_munge(s, val), val 659 drivers/staging/comedi/drivers/quatech_daqp_cs.c s->readback[chan] = val; val 1024 drivers/staging/comedi/drivers/rtd520.c unsigned int val = data[i]; val 1028 drivers/staging/comedi/drivers/rtd520.c val = comedi_offset_munge(s, val); val 1029 drivers/staging/comedi/drivers/rtd520.c val |= (val & ((s->maxdata + 1) >> 1)) << 1; val 1033 drivers/staging/comedi/drivers/rtd520.c val <<= 3; val 1035 drivers/staging/comedi/drivers/rtd520.c writew(val, devpriv->las1 + LAS1_DAC_FIFO(chan)); val 183 drivers/staging/comedi/drivers/rti800.c unsigned int val; val 191 drivers/staging/comedi/drivers/rti800.c val = inb(dev->iobase + RTI800_ADCLO); val 192 drivers/staging/comedi/drivers/rti800.c val |= (inb(dev->iobase + RTI800_ADCHI) & 0xf) << 8; val 195 drivers/staging/comedi/drivers/rti800.c val = comedi_offset_munge(s, val); val 197 drivers/staging/comedi/drivers/rti800.c data[i] = val; val 215 drivers/staging/comedi/drivers/rti800.c unsigned int val = data[i]; val 217 drivers/staging/comedi/drivers/rti800.c s->readback[chan] = val; val 220 drivers/staging/comedi/drivers/rti800.c val = comedi_offset_munge(s, val); val 222 drivers/staging/comedi/drivers/rti800.c outb(val & 0xff, dev->iobase + reg_lo); val 223 drivers/staging/comedi/drivers/rti800.c outb((val >> 8) & 0xff, dev->iobase + reg_hi); val 53 drivers/staging/comedi/drivers/rti802.c unsigned int val = data[i]; val 55 drivers/staging/comedi/drivers/rti802.c s->readback[chan] = val; val 59 drivers/staging/comedi/drivers/rti802.c val = comedi_offset_munge(s, val); val 61 drivers/staging/comedi/drivers/rti802.c outb(val & 0xff, dev->iobase + RTI802_DATALOW); val 62 drivers/staging/comedi/drivers/rti802.c outb((val >> 8) & 0xff, dev->iobase + RTI802_DATAHIGH); val 176 drivers/staging/comedi/drivers/s526.c unsigned int chan, unsigned int val) val 179 drivers/staging/comedi/drivers/s526.c outw((val >> 16) & 0xffff, dev->iobase + S526_GPCT_MSB_REG(chan)); val 180 drivers/staging/comedi/drivers/s526.c outw(val & 0xffff, dev->iobase + S526_GPCT_LSB_REG(chan)); val 186 drivers/staging/comedi/drivers/s526.c unsigned int val; val 189 drivers/staging/comedi/drivers/s526.c val = inw(dev->iobase + S526_GPCT_LSB_REG(chan)) & 0xffff; val 190 drivers/staging/comedi/drivers/s526.c val |= (inw(dev->iobase + S526_GPCT_MSB_REG(chan)) & 0xff) << 16; val 192 drivers/staging/comedi/drivers/s526.c return val; val 216 drivers/staging/comedi/drivers/s526.c unsigned int val; val 234 drivers/staging/comedi/drivers/s526.c val = data[1] & 0xffff; val 235 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); val 238 drivers/staging/comedi/drivers/s526.c if ((val & S526_GPCT_MODE_AUTOLOAD_MASK) == val 250 drivers/staging/comedi/drivers/s526.c val = S526_GPCT_MODE_CTDIR_CTRL_QUAD; val 254 drivers/staging/comedi/drivers/s526.c val |= S526_GPCT_MODE_CLK_SRC_QUADX2; val 256 drivers/staging/comedi/drivers/s526.c val |= S526_GPCT_MODE_CLK_SRC_QUADX4; val 258 drivers/staging/comedi/drivers/s526.c val |= S526_GPCT_MODE_CLK_SRC_QUADX1; val 271 drivers/staging/comedi/drivers/s526.c val |= S526_GPCT_MODE_AUTOLOAD_IXRISE; val 275 drivers/staging/comedi/drivers/s526.c val = data[1] & 0xffff; val 276 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); val 287 drivers/staging/comedi/drivers/s526.c if ((val & S526_GPCT_MODE_AUTOLOAD_MASK) == val 310 drivers/staging/comedi/drivers/s526.c val = data[1] & 0xffff; val 312 drivers/staging/comedi/drivers/s526.c val &= ~S526_GPCT_MODE_PR_SELECT_MASK; val 313 drivers/staging/comedi/drivers/s526.c val |= S526_GPCT_MODE_PR_SELECT_PR0; val 314 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); val 320 drivers/staging/comedi/drivers/s526.c val = data[1] & 0xffff; val 322 drivers/staging/comedi/drivers/s526.c val &= ~S526_GPCT_MODE_PR_SELECT_MASK; val 323 drivers/staging/comedi/drivers/s526.c val |= S526_GPCT_MODE_PR_SELECT_PR1; val 324 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); val 331 drivers/staging/comedi/drivers/s526.c val = data[4] & 0xffff; val 332 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_GPCT_CTRL_REG(chan)); val 347 drivers/staging/comedi/drivers/s526.c val = data[1] & 0xffff; val 349 drivers/staging/comedi/drivers/s526.c val &= ~S526_GPCT_MODE_PR_SELECT_MASK; val 350 drivers/staging/comedi/drivers/s526.c val |= S526_GPCT_MODE_PR_SELECT_PR0; val 351 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); val 357 drivers/staging/comedi/drivers/s526.c val = data[1] & 0xffff; val 359 drivers/staging/comedi/drivers/s526.c val &= ~S526_GPCT_MODE_PR_SELECT_MASK; val 360 drivers/staging/comedi/drivers/s526.c val |= S526_GPCT_MODE_PR_SELECT_PR1; val 361 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); val 368 drivers/staging/comedi/drivers/s526.c val = data[4] & 0xffff; val 369 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_GPCT_CTRL_REG(chan)); val 440 drivers/staging/comedi/drivers/s526.c unsigned int val; val 465 drivers/staging/comedi/drivers/s526.c val = inw(dev->iobase + S526_AI_REG); val 466 drivers/staging/comedi/drivers/s526.c data[i] = comedi_offset_munge(s, val); val 479 drivers/staging/comedi/drivers/s526.c unsigned int val = s->readback[chan]; val 487 drivers/staging/comedi/drivers/s526.c val = data[i]; val 488 drivers/staging/comedi/drivers/s526.c outw(val, dev->iobase + S526_AO_REG); val 496 drivers/staging/comedi/drivers/s526.c s->readback[chan] = val; val 109 drivers/staging/comedi/drivers/s626.c unsigned int val = (cmd << 16) | cmd; val 111 drivers/staging/comedi/drivers/s626.c writel(val, dev->mmio + reg); val 123 drivers/staging/comedi/drivers/s626.c unsigned int val; val 125 drivers/staging/comedi/drivers/s626.c val = readl(dev->mmio + reg); val 127 drivers/staging/comedi/drivers/s626.c return (val & cmd) ? true : false; val 212 drivers/staging/comedi/drivers/s626.c unsigned int val; val 219 drivers/staging/comedi/drivers/s626.c val = readl(dev->mmio + S626_P_DEBIAD); val 220 drivers/staging/comedi/drivers/s626.c val &= mask; val 221 drivers/staging/comedi/drivers/s626.c val |= wdata; val 222 drivers/staging/comedi/drivers/s626.c writel(val & 0xffff, dev->mmio + S626_P_DEBIAD); val 241 drivers/staging/comedi/drivers/s626.c static int s626_i2c_handshake(struct comedi_device *dev, u32 val) val 247 drivers/staging/comedi/drivers/s626.c writel(val, dev->mmio + S626_P_I2CCTRL); val 357 drivers/staging/comedi/drivers/s626.c static int s626_send_dac(struct comedi_device *dev, u32 val) val 380 drivers/staging/comedi/drivers/s626.c *devpriv->dac_wbuf = val; val 521 drivers/staging/comedi/drivers/s626.c u32 val; val 571 drivers/staging/comedi/drivers/s626.c val = 0x0F000000; /* Continue clock after target DAC data val 574 drivers/staging/comedi/drivers/s626.c val |= 0x00004000; /* Address the two main dual-DAC devices val 577 drivers/staging/comedi/drivers/s626.c val |= ((u32)(chan & 1) << 15); /* Address the DAC channel val 580 drivers/staging/comedi/drivers/s626.c val |= (u32)dacdata; /* Include DAC setpoint data. */ val 581 drivers/staging/comedi/drivers/s626.c return s626_send_dac(dev, val); val 2058 drivers/staging/comedi/drivers/s626.c unsigned int val; val 2064 drivers/staging/comedi/drivers/s626.c val = s626_debi_read(dev, cntr_latch_reg); val 2065 drivers/staging/comedi/drivers/s626.c val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16); val 2066 drivers/staging/comedi/drivers/s626.c data[i] = val; val 47 drivers/staging/comedi/drivers/ssv_dnp.c unsigned int val; val 64 drivers/staging/comedi/drivers/ssv_dnp.c val = inb(CSCDR) & 0x0f; val 65 drivers/staging/comedi/drivers/ssv_dnp.c outb(((s->state >> 12) & 0xf0) | val, CSCDR); val 69 drivers/staging/comedi/drivers/ssv_dnp.c val = inb(CSCDR); val 71 drivers/staging/comedi/drivers/ssv_dnp.c val |= (inb(CSCDR) << 8); val 73 drivers/staging/comedi/drivers/ssv_dnp.c val |= ((inb(CSCDR) & 0xf0) << 12); val 75 drivers/staging/comedi/drivers/ssv_dnp.c data[1] = val; val 87 drivers/staging/comedi/drivers/ssv_dnp.c unsigned int val; val 114 drivers/staging/comedi/drivers/ssv_dnp.c val = inb(CSCDR); val 116 drivers/staging/comedi/drivers/ssv_dnp.c val |= mask; val 118 drivers/staging/comedi/drivers/ssv_dnp.c val &= ~mask; val 119 drivers/staging/comedi/drivers/ssv_dnp.c outb(val, CSCDR); val 256 drivers/staging/comedi/drivers/usbdux.c u16 val = le16_to_cpu(devpriv->in_buf[i]); val 260 drivers/staging/comedi/drivers/usbdux.c val = comedi_offset_munge(s, val); val 263 drivers/staging/comedi/drivers/usbdux.c if (!comedi_buf_write_samples(s, &val, 1)) val 393 drivers/staging/comedi/drivers/usbdux.c unsigned short val; val 395 drivers/staging/comedi/drivers/usbdux.c if (!comedi_buf_read_samples(s, &val, 1)) { val 402 drivers/staging/comedi/drivers/usbdux.c *datap++ = val & 0xff; val 403 drivers/staging/comedi/drivers/usbdux.c *datap++ = (val >> 8) & 0xff; val 405 drivers/staging/comedi/drivers/usbdux.c s->readback[chan] = val; val 744 drivers/staging/comedi/drivers/usbdux.c unsigned int val; val 766 drivers/staging/comedi/drivers/usbdux.c val = le16_to_cpu(devpriv->insn_buf[1]); val 770 drivers/staging/comedi/drivers/usbdux.c val = comedi_offset_munge(s, val); val 772 drivers/staging/comedi/drivers/usbdux.c data[i] = val; val 818 drivers/staging/comedi/drivers/usbdux.c unsigned int val = data[i]; val 821 drivers/staging/comedi/drivers/usbdux.c *p = cpu_to_le16(val); val 827 drivers/staging/comedi/drivers/usbdux.c s->readback[chan] = val; val 208 drivers/staging/comedi/drivers/usbduxsigma.c u32 val; val 222 drivers/staging/comedi/drivers/usbduxsigma.c val = be32_to_cpu(devpriv->in_buf[i + 1]); val 223 drivers/staging/comedi/drivers/usbduxsigma.c val &= 0x00ffffff; /* strip status byte */ val 224 drivers/staging/comedi/drivers/usbduxsigma.c val = comedi_offset_munge(s, val); val 225 drivers/staging/comedi/drivers/usbduxsigma.c if (!comedi_buf_write_samples(s, &val, 1)) val 353 drivers/staging/comedi/drivers/usbduxsigma.c unsigned short val; val 355 drivers/staging/comedi/drivers/usbduxsigma.c if (!comedi_buf_read_samples(s, &val, 1)) { val 361 drivers/staging/comedi/drivers/usbduxsigma.c *datap++ = val; val 363 drivers/staging/comedi/drivers/usbduxsigma.c s->readback[chan] = val; val 730 drivers/staging/comedi/drivers/usbduxsigma.c u32 val; val 739 drivers/staging/comedi/drivers/usbduxsigma.c val = be32_to_cpu(get_unaligned((__be32 val 741 drivers/staging/comedi/drivers/usbduxsigma.c val &= 0x00ffffff; /* strip status byte */ val 742 drivers/staging/comedi/drivers/usbduxsigma.c data[i] = comedi_offset_munge(s, val); val 1213 drivers/staging/comedi/drivers/usbduxsigma.c u32 val; val 1253 drivers/staging/comedi/drivers/usbduxsigma.c val = be32_to_cpu(get_unaligned((__be32 *)(devpriv->insn_buf + 1))); val 1254 drivers/staging/comedi/drivers/usbduxsigma.c val &= 0x00ffffff; /* strip status byte */ val 1256 drivers/staging/comedi/drivers/usbduxsigma.c return (int)comedi_offset_munge(s, val); val 522 drivers/staging/comedi/drivers/vmk80xx.c unsigned long val; val 544 drivers/staging/comedi/drivers/vmk80xx.c val = int_sqrt(debtime * 1000 / 115); val 545 drivers/staging/comedi/drivers/vmk80xx.c if (((val + 1) * val) < debtime * 1000 / 115) val 546 drivers/staging/comedi/drivers/vmk80xx.c val += 1; val 548 drivers/staging/comedi/drivers/vmk80xx.c devpriv->usb_tx_buf[6 + chan] = val; val 3523 drivers/staging/exfat/exfat_super.c buf->f_fsid.val[0] = (u32)id; val 3524 drivers/staging/exfat/exfat_super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 154 drivers/staging/fbtft/fb_hx8357d.c u8 val; val 158 drivers/staging/fbtft/fb_hx8357d.c val = HX8357D_MADCTL_MV | HX8357D_MADCTL_MX; val 161 drivers/staging/fbtft/fb_hx8357d.c val = 0; val 164 drivers/staging/fbtft/fb_hx8357d.c val = HX8357D_MADCTL_MV | HX8357D_MADCTL_MY; val 167 drivers/staging/fbtft/fb_hx8357d.c val = HX8357D_MADCTL_MX | HX8357D_MADCTL_MY; val 171 drivers/staging/fbtft/fb_hx8357d.c val |= (par->bgr ? HX8357D_MADCTL_RGB : HX8357D_MADCTL_BGR); val 174 drivers/staging/fbtft/fb_hx8357d.c write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, val); val 98 drivers/staging/fbtft/fb_ili9340.c u8 val; val 102 drivers/staging/fbtft/fb_ili9340.c val = ILI9340_MADCTL_MV; val 105 drivers/staging/fbtft/fb_ili9340.c val = ILI9340_MADCTL_MY; val 108 drivers/staging/fbtft/fb_ili9340.c val = ILI9340_MADCTL_MV | ILI9340_MADCTL_MY | ILI9340_MADCTL_MX; val 111 drivers/staging/fbtft/fb_ili9340.c val = ILI9340_MADCTL_MX; val 115 drivers/staging/fbtft/fb_ili9340.c write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, val | (par->bgr << 3)); val 440 drivers/staging/fbtft/fbtft-core.c unsigned int val; val 452 drivers/staging/fbtft/fbtft-core.c val = chan_to_field(red, &info->var.red); val 453 drivers/staging/fbtft/fbtft-core.c val |= chan_to_field(green, &info->var.green); val 454 drivers/staging/fbtft/fbtft-core.c val |= chan_to_field(blue, &info->var.blue); val 456 drivers/staging/fbtft/fbtft-core.c pal[regno] = val; val 912 drivers/staging/fbtft/fbtft-core.c u32 val; val 919 drivers/staging/fbtft/fbtft-core.c p = of_prop_next_u32(prop, NULL, &val); val 928 drivers/staging/fbtft/fbtft-core.c if (val & FBTFT_OF_INIT_CMD) { val 929 drivers/staging/fbtft/fbtft-core.c val &= 0xFFFF; val 931 drivers/staging/fbtft/fbtft-core.c while (p && !(val & 0xFFFF0000)) { val 938 drivers/staging/fbtft/fbtft-core.c buf[i++] = val; val 939 drivers/staging/fbtft/fbtft-core.c p = of_prop_next_u32(prop, p, &val); val 965 drivers/staging/fbtft/fbtft-core.c } else if (val & FBTFT_OF_INIT_DELAY) { val 967 drivers/staging/fbtft/fbtft-core.c "init: msleep(%u)\n", val & 0xFFFF); val 968 drivers/staging/fbtft/fbtft-core.c msleep(val & 0xFFFF); val 969 drivers/staging/fbtft/fbtft-core.c p = of_prop_next_u32(prop, p, &val); val 972 drivers/staging/fbtft/fbtft-core.c val); val 1145 drivers/staging/fbtft/fbtft-core.c u32 val = 0; val 1147 drivers/staging/fbtft/fbtft-core.c ret = of_property_read_u32(node, propname, &val); val 1149 drivers/staging/fbtft/fbtft-core.c pr_info("%s: %s = %u\n", __func__, propname, val); val 1151 drivers/staging/fbtft/fbtft-core.c return val; val 47 drivers/staging/fbtft/fbtft-io.c u64 val, dc, tmp; val 68 drivers/staging/fbtft/fbtft-io.c val = *src & 0x00FF; val 71 drivers/staging/fbtft/fbtft-io.c tmp |= val << bits--; val 5 drivers/staging/fbtft/fbtft-sysfs.c static int get_next_ulong(char **str_p, unsigned long *val, char *sep, int base) val 17 drivers/staging/fbtft/fbtft-sysfs.c return kstrtoul(p_val, base, val); val 25 drivers/staging/fbtft/fbtft-sysfs.c unsigned long val = 0; val 68 drivers/staging/fbtft/fbtft-sysfs.c ret = get_next_ulong(&curve_p, &val, " ", 16); val 71 drivers/staging/fbtft/fbtft-sysfs.c curves[curve_counter * par->gamma.num_values + value_counter] = val; val 403 drivers/staging/fieldbus/anybuss/host.c unsigned int val; val 408 drivers/staging/fieldbus/anybuss/host.c regmap_read(regmap, i, &val); val 409 drivers/staging/fieldbus/anybuss/host.c if ((u8)val != (u8)i) val 1266 drivers/staging/fieldbus/anybuss/host.c u8 val[4]; val 1337 drivers/staging/fieldbus/anybuss/host.c regmap_bulk_read(cd->regmap, REG_BOOTLOADER_V, val, 2); val 1339 drivers/staging/fieldbus/anybuss/host.c val[0], val[1]); val 1340 drivers/staging/fieldbus/anybuss/host.c regmap_bulk_read(cd->regmap, REG_API_V, val, 2); val 1341 drivers/staging/fieldbus/anybuss/host.c dev_info(dev, "API version: %02X%02X", val[0], val[1]); val 1342 drivers/staging/fieldbus/anybuss/host.c regmap_bulk_read(cd->regmap, REG_FIELDBUS_V, val, 2); val 1343 drivers/staging/fieldbus/anybuss/host.c dev_info(dev, "Fieldbus version: %02X%02X", val[0], val[1]); val 1344 drivers/staging/fieldbus/anybuss/host.c regmap_bulk_read(cd->regmap, REG_SERIAL_NO, val, 4); val 1346 drivers/staging/fieldbus/anybuss/host.c val[0], val[1], val[2], val[3]); val 1347 drivers/staging/fieldbus/anybuss/host.c add_device_randomness(&val, 4); val 1351 drivers/staging/fieldbus/anybuss/host.c regmap_bulk_read(cd->regmap, REG_MODULE_SW_V, val, 2); val 1353 drivers/staging/fieldbus/anybuss/host.c val[0], val[1]); val 76 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h #define dpsw_set_field(var, field, val) \ val 77 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h ((var) |= (((val) << DPSW_##field##_SHIFT) & DPSW_MASK(field))) val 110 drivers/staging/fsl-dpaa2/ethsw/dpsw.h u32 val; val 2000 drivers/staging/fwserial/fwserial.c int key, val; val 2024 drivers/staging/fwserial/fwserial.c while (fw_csr_iterator_next(&ci, &key, &val)) { val 2026 drivers/staging/fwserial/fwserial.c peer->mgmt_addr = CSR_REGISTER_BASE + 4 * val; val 26 drivers/staging/fwserial/fwserial.h static inline void fwtty_profile_data(unsigned int stat[], unsigned int val) val 28 drivers/staging/fwserial/fwserial.h int n = (val) ? min(ilog2(val) + 1, DISTRIBUTION_MAX_INDEX) : 0; val 417 drivers/staging/gasket/apex_driver.c u32 val = gasket_dev_read_32(gasket_dev, APEX_BAR_INDEX, val 421 drivers/staging/gasket/apex_driver.c return (val & SCU3_CUR_RST_GCB_BIT_MASK); val 513 drivers/staging/gasket/apex_driver.c uint val; val 532 drivers/staging/gasket/apex_driver.c val = gasket_page_table_num_entries(gpt); val 535 drivers/staging/gasket/apex_driver.c val = gasket_page_table_num_simple_entries(gpt); val 538 drivers/staging/gasket/apex_driver.c val = gasket_page_table_num_active_pages(gpt); val 546 drivers/staging/gasket/apex_driver.c ret = scnprintf(buf, PAGE_SIZE, "%u\n", val); val 1672 drivers/staging/gasket/gasket_core.c u64 offset, u64 mask, u64 val, val 1680 drivers/staging/gasket/gasket_core.c if ((tmp & mask) == val) val 635 drivers/staging/gasket/gasket_core.h u64 offset, u64 mask, u64 val, val 433 drivers/staging/greybus/audio_topology.c unsigned int mask, val; val 460 drivers/staging/greybus/audio_topology.c val = ucontrol->value.integer.value[0] & mask; val 461 drivers/staging/greybus/audio_topology.c connect = !!val; val 464 drivers/staging/greybus/audio_topology.c if (gbvalue.value.integer_value[0] != val) { val 468 drivers/staging/greybus/audio_topology.c widget->value = val; val 765 drivers/staging/greybus/audio_topology.c unsigned int val, mux, change; val 806 drivers/staging/greybus/audio_topology.c val = mux << e->shift_l; val 819 drivers/staging/greybus/audio_topology.c val |= ucontrol->value.enumerated.item[1] << e->shift_r; val 847 drivers/staging/greybus/audio_topology.c widget->value = val; val 528 drivers/staging/greybus/light.c v4l2_s->val = channel_s->max; val 617 drivers/staging/greybus/light.c fcdev->brightness.val = brightness; val 625 drivers/staging/greybus/light.c *brightness = fcdev->brightness.val; val 695 drivers/staging/greybus/light.c fcdev->timeout.val = timeout; val 783 drivers/staging/greybus/light.c fset->val = channel->intensity_uA.max; val 791 drivers/staging/greybus/light.c fset->val = channel->timeout_us.max; val 722 drivers/staging/greybus/loopback.c static void gb_loopback_update_stats(struct gb_loopback_stats *stats, u32 val) val 724 drivers/staging/greybus/loopback.c if (stats->min > val) val 725 drivers/staging/greybus/loopback.c stats->min = val; val 726 drivers/staging/greybus/loopback.c if (stats->max < val) val 727 drivers/staging/greybus/loopback.c stats->max = val; val 728 drivers/staging/greybus/loopback.c stats->sum += val; val 733 drivers/staging/greybus/loopback.c u64 val, u32 count) val 735 drivers/staging/greybus/loopback.c stats->sum += val; val 738 drivers/staging/greybus/loopback.c do_div(val, count); val 739 drivers/staging/greybus/loopback.c if (stats->min > val) val 740 drivers/staging/greybus/loopback.c stats->min = val; val 741 drivers/staging/greybus/loopback.c if (stats->max < val) val 742 drivers/staging/greybus/loopback.c stats->max = val; val 20 drivers/staging/greybus/power_supply.c int val; val 370 drivers/staging/greybus/power_supply.c if ((prop->val == GB_POWER_SUPPLY_STATUS_CHARGING) && val 396 drivers/staging/greybus/power_supply.c int val = prop->val; val 406 drivers/staging/greybus/power_supply.c else if (val < prev_val && val 407 drivers/staging/greybus/power_supply.c prev_val - val > psyc->tolerance_change) val 409 drivers/staging/greybus/power_supply.c else if (val > prev_val && val 410 drivers/staging/greybus/power_supply.c val - prev_val > psyc->tolerance_change) val 596 drivers/staging/greybus/power_supply.c int val; val 610 drivers/staging/greybus/power_supply.c val = le32_to_cpu(resp.prop_val); val 611 drivers/staging/greybus/power_supply.c if (val == prop->val) val 614 drivers/staging/greybus/power_supply.c prop->previous_val = prop->val; val 615 drivers/staging/greybus/power_supply.c prop->val = val; val 624 drivers/staging/greybus/power_supply.c union power_supply_propval *val) val 632 drivers/staging/greybus/power_supply.c val->intval = prop->val; val 638 drivers/staging/greybus/power_supply.c union power_supply_propval *val) val 642 drivers/staging/greybus/power_supply.c val->strval = gbpsy->model_name; val 645 drivers/staging/greybus/power_supply.c val->strval = gbpsy->manufacturer; val 648 drivers/staging/greybus/power_supply.c val->strval = gbpsy->serial_number; val 659 drivers/staging/greybus/power_supply.c union power_supply_propval *val) val 669 drivers/staging/greybus/power_supply.c ret = __gb_power_supply_property_get(gbpsy, psp, val); val 671 drivers/staging/greybus/power_supply.c ret = __gb_power_supply_property_strval_get(gbpsy, psp, val); val 755 drivers/staging/greybus/power_supply.c union power_supply_propval *val) val 761 drivers/staging/greybus/power_supply.c return _gb_power_supply_property_get(gbpsy, psp, val); val 766 drivers/staging/greybus/power_supply.c int val) val 785 drivers/staging/greybus/power_supply.c req.prop_val = cpu_to_le32((s32)val); val 793 drivers/staging/greybus/power_supply.c prop->val = val; val 802 drivers/staging/greybus/power_supply.c const union power_supply_propval *val) val 806 drivers/staging/greybus/power_supply.c return gb_power_supply_property_set(gbpsy, psp, val->intval); val 141 drivers/staging/greybus/tools/loopback_test.c uint32_t val = 0; \ val 148 drivers/staging/greybus/tools/loopback_test.c val += t->devices[i].results.field; \ val 151 drivers/staging/greybus/tools/loopback_test.c val /= count; \ val 152 drivers/staging/greybus/tools/loopback_test.c return val; \ val 288 drivers/staging/greybus/tools/loopback_test.c int fd, val; val 291 drivers/staging/greybus/tools/loopback_test.c val = read_sysfs_int_fd(fd, sys_pfx, node); val 293 drivers/staging/greybus/tools/loopback_test.c return val; val 299 drivers/staging/greybus/tools/loopback_test.c float val; val 302 drivers/staging/greybus/tools/loopback_test.c val = read_sysfs_float_fd(fd, sys_pfx, node); val 304 drivers/staging/greybus/tools/loopback_test.c return val; val 307 drivers/staging/greybus/tools/loopback_test.c void write_sysfs_val(const char *sys_pfx, const char *node, int val) val 313 drivers/staging/greybus/tools/loopback_test.c len = snprintf(buf, sizeof(buf), "%d", val); val 82 drivers/staging/greybus/vibrator.c unsigned long val; val 85 drivers/staging/greybus/vibrator.c retval = kstrtoul(buf, 10, &val); val 91 drivers/staging/greybus/vibrator.c if (val) val 92 drivers/staging/greybus/vibrator.c retval = turn_on(vib, (u16)val); val 152 drivers/staging/iio/accel/adis16203.c int val, val 160 drivers/staging/iio/accel/adis16203.c return adis_write_reg_16(st, addr, val & 0x3FFF); val 165 drivers/staging/iio/accel/adis16203.c int *val, int *val2, val 176 drivers/staging/iio/accel/adis16203.c ADIS16203_ERROR_ACTIVE, val); val 181 drivers/staging/iio/accel/adis16203.c *val = 1; val 184 drivers/staging/iio/accel/adis16203.c *val = 0; val 189 drivers/staging/iio/accel/adis16203.c *val = -470; /* -0.47 C */ val 193 drivers/staging/iio/accel/adis16203.c *val = 0; val 200 drivers/staging/iio/accel/adis16203.c *val = 25000 / -470 - 1278; /* 25 C = 1278 */ val 207 drivers/staging/iio/accel/adis16203.c *val = sign_extend32(val16, 13); val 210 drivers/staging/iio/accel/adis16240.c s16 val = 0; val 215 drivers/staging/iio/accel/adis16240.c this_attr->address, (u16 *)&val); val 219 drivers/staging/iio/accel/adis16240.c if (val & ADIS16240_ERROR_ACTIVE) val 222 drivers/staging/iio/accel/adis16240.c val = (s16)(val << shift) >> shift; val 223 drivers/staging/iio/accel/adis16240.c return sprintf(buf, "%d\n", val); val 247 drivers/staging/iio/accel/adis16240.c int *val, int *val2, val 258 drivers/staging/iio/accel/adis16240.c ADIS16240_ERROR_ACTIVE, val); val 263 drivers/staging/iio/accel/adis16240.c *val = 4; val 269 drivers/staging/iio/accel/adis16240.c *val = 244; /* 0.244 C */ val 273 drivers/staging/iio/accel/adis16240.c *val = 0; val 281 drivers/staging/iio/accel/adis16240.c *val = 0; val 285 drivers/staging/iio/accel/adis16240.c *val = 25000 / 244 - 0x133; /* 25 C = 0x133 */ val 292 drivers/staging/iio/accel/adis16240.c *val = sign_extend32(val16, 9); val 299 drivers/staging/iio/accel/adis16240.c *val = sign_extend32(val16, 9); val 307 drivers/staging/iio/accel/adis16240.c int val, val 317 drivers/staging/iio/accel/adis16240.c return adis_write_reg_16(st, addr, val & GENMASK(9, 0)); val 368 drivers/staging/iio/adc/ad7192.c bool val; val 370 drivers/staging/iio/adc/ad7192.c ret = strtobool(buf, &val); val 380 drivers/staging/iio/adc/ad7192.c if (val) val 388 drivers/staging/iio/adc/ad7192.c if (val) val 482 drivers/staging/iio/adc/ad7192.c int val, int val2) val 489 drivers/staging/iio/adc/ad7192.c freq = val * 1000 + val2; val 552 drivers/staging/iio/adc/ad7192.c int *val, val 561 drivers/staging/iio/adc/ad7192.c return ad_sigma_delta_single_conversion(indio_dev, chan, val); val 566 drivers/staging/iio/adc/ad7192.c *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; val 571 drivers/staging/iio/adc/ad7192.c *val = 0; val 579 drivers/staging/iio/adc/ad7192.c *val = -(1 << (chan->scan_type.realbits - 1)); val 581 drivers/staging/iio/adc/ad7192.c *val = 0; val 584 drivers/staging/iio/adc/ad7192.c *val -= 273 * ad7192_get_temp_scale(unipolar); val 587 drivers/staging/iio/adc/ad7192.c *val = st->fclk / val 591 drivers/staging/iio/adc/ad7192.c *val = ad7192_get_3db_filter_freq(st); val 601 drivers/staging/iio/adc/ad7192.c int val, val 633 drivers/staging/iio/adc/ad7192.c if (!val) { val 638 drivers/staging/iio/adc/ad7192.c div = st->fclk / (val * st->f_order * 1024); val 649 drivers/staging/iio/adc/ad7192.c ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); val 150 drivers/staging/iio/adc/ad7280a.c static unsigned char ad7280_calc_crc8(unsigned char *crc_tab, unsigned int val) val 154 drivers/staging/iio/adc/ad7280a.c crc = crc_tab[val >> 16 & 0xFF]; val 155 drivers/staging/iio/adc/ad7280a.c crc = crc_tab[crc ^ (val >> 8 & 0xFF)]; val 157 drivers/staging/iio/adc/ad7280a.c return crc ^ (val & 0xFF); val 160 drivers/staging/iio/adc/ad7280a.c static int ad7280_check_crc(struct ad7280_state *st, unsigned int val) val 162 drivers/staging/iio/adc/ad7280a.c unsigned char crc = ad7280_calc_crc8(st->crc_tab, val >> 10); val 164 drivers/staging/iio/adc/ad7280a.c if (crc != ((val >> 2) & 0xFF)) val 186 drivers/staging/iio/adc/ad7280a.c static int __ad7280_read32(struct ad7280_state *st, unsigned int *val) val 201 drivers/staging/iio/adc/ad7280a.c *val = be32_to_cpu(st->buf[1]); val 207 drivers/staging/iio/adc/ad7280a.c unsigned int addr, bool all, unsigned int val) val 210 drivers/staging/iio/adc/ad7280a.c (val & 0xFF) << 13 | all << 12; val 347 drivers/staging/iio/adc/ad7280a.c unsigned int val, n; val 373 drivers/staging/iio/adc/ad7280a.c ret = __ad7280_read32(st, &val); val 377 drivers/staging/iio/adc/ad7280a.c if (val == 0) val 380 drivers/staging/iio/adc/ad7280a.c if (ad7280_check_crc(st, val)) { val 385 drivers/staging/iio/adc/ad7280a.c if (n != ad7280a_devaddr(val >> 27)) { val 475 drivers/staging/iio/adc/ad7280a.c unsigned long val; val 478 drivers/staging/iio/adc/ad7280a.c ret = kstrtoul(buf, 10, &val); val 482 drivers/staging/iio/adc/ad7280a.c val /= 71500; val 484 drivers/staging/iio/adc/ad7280a.c if (val > 31) val 490 drivers/staging/iio/adc/ad7280a.c 0, (val & 0x1F) << 3); val 691 drivers/staging/iio/adc/ad7280a.c unsigned int val; val 695 drivers/staging/iio/adc/ad7280a.c val = 1000 + (st->cell_threshhigh * 1568) / 100; val 698 drivers/staging/iio/adc/ad7280a.c val = 1000 + (st->cell_threshlow * 1568) / 100; val 701 drivers/staging/iio/adc/ad7280a.c val = (st->aux_threshhigh * 196) / 10; val 704 drivers/staging/iio/adc/ad7280a.c val = (st->aux_threshlow * 196) / 10; val 710 drivers/staging/iio/adc/ad7280a.c return sprintf(buf, "%u\n", val); val 722 drivers/staging/iio/adc/ad7280a.c long val; val 725 drivers/staging/iio/adc/ad7280a.c ret = kstrtol(buf, 10, &val); val 732 drivers/staging/iio/adc/ad7280a.c val = ((val - 1000) * 100) / 1568; /* LSB 15.68mV */ val 736 drivers/staging/iio/adc/ad7280a.c val = (val * 10) / 196; /* LSB 19.6mV */ val 742 drivers/staging/iio/adc/ad7280a.c val = clamp(val, 0L, 0xFFL); val 747 drivers/staging/iio/adc/ad7280a.c st->cell_threshhigh = val; val 750 drivers/staging/iio/adc/ad7280a.c st->cell_threshlow = val; val 753 drivers/staging/iio/adc/ad7280a.c st->aux_threshhigh = val; val 756 drivers/staging/iio/adc/ad7280a.c st->aux_threshlow = val; val 761 drivers/staging/iio/adc/ad7280a.c this_attr->address, 1, val); val 867 drivers/staging/iio/adc/ad7280a.c int *val, val 887 drivers/staging/iio/adc/ad7280a.c *val = ret; val 892 drivers/staging/iio/adc/ad7280a.c *val = 4000; val 894 drivers/staging/iio/adc/ad7280a.c *val = 5000; val 82 drivers/staging/iio/addac/adt7316-spi.c static int adt7316_spi_write(void *client, u8 reg, u8 val) val 84 drivers/staging/iio/addac/adt7316-spi.c return adt7316_spi_multi_write(client, reg, 1, &val); val 1248 drivers/staging/iio/addac/adt7316.c u8 val; val 1251 drivers/staging/iio/addac/adt7316.c ret = chip->bus.read(chip->bus.client, offset_addr, &val); val 1255 drivers/staging/iio/addac/adt7316.c data = (int)val; val 1256 drivers/staging/iio/addac/adt7316.c if (val & 0x80) val 1268 drivers/staging/iio/addac/adt7316.c u8 val; val 1278 drivers/staging/iio/addac/adt7316.c val = (u8)data; val 1280 drivers/staging/iio/addac/adt7316.c ret = chip->bus.write(chip->bus.client, offset_addr, val); val 1902 drivers/staging/iio/addac/adt7316.c u8 val; val 1910 drivers/staging/iio/addac/adt7316.c ret = chip->bus.read(chip->bus.client, this_attr->address, &val); val 1914 drivers/staging/iio/addac/adt7316.c data = (int)val; val 1934 drivers/staging/iio/addac/adt7316.c u8 val; val 1957 drivers/staging/iio/addac/adt7316.c val = (u8)data; val 1959 drivers/staging/iio/addac/adt7316.c ret = chip->bus.write(chip->bus.client, this_attr->address, val); val 20 drivers/staging/iio/addac/adt7316.h int (*write)(void *client, u8 reg, u8 val); val 102 drivers/staging/iio/cdc/ad7150.c int *val, val 116 drivers/staging/iio/cdc/ad7150.c *val = swab16(ret); val 123 drivers/staging/iio/cdc/ad7150.c *val = swab16(ret); val 288 drivers/staging/iio/cdc/ad7150.c int *val, int *val2) val 296 drivers/staging/iio/cdc/ad7150.c *val = chip->mag_sensitivity[rising][chan->channel]; val 299 drivers/staging/iio/cdc/ad7150.c *val = chip->thresh_sensitivity[rising][chan->channel]; val 302 drivers/staging/iio/cdc/ad7150.c *val = chip->threshold[rising][chan->channel]; val 314 drivers/staging/iio/cdc/ad7150.c int val, int val2) val 323 drivers/staging/iio/cdc/ad7150.c chip->mag_sensitivity[rising][chan->channel] = val; val 326 drivers/staging/iio/cdc/ad7150.c chip->thresh_sensitivity[rising][chan->channel] = val; val 329 drivers/staging/iio/cdc/ad7150.c chip->threshold[rising][chan->channel] = val; val 366 drivers/staging/iio/cdc/ad7746.c int val) val 371 drivers/staging/iio/cdc/ad7746.c if (val >= ad7746_cap_filter_rate_table[i][0]) val 384 drivers/staging/iio/cdc/ad7746.c int val) val 389 drivers/staging/iio/cdc/ad7746.c if (val >= ad7746_vt_filter_rate_table[i][0]) val 422 drivers/staging/iio/cdc/ad7746.c int val, val 433 drivers/staging/iio/cdc/ad7746.c if (val != 1) { val 438 drivers/staging/iio/cdc/ad7746.c val = (val2 * 1024) / 15625; val 452 drivers/staging/iio/cdc/ad7746.c ret = i2c_smbus_write_word_swapped(chip->client, reg, val); val 459 drivers/staging/iio/cdc/ad7746.c if (val < 0 || val > 0xFFFF) { val 464 drivers/staging/iio/cdc/ad7746.c AD7746_REG_CAP_OFFH, val); val 471 drivers/staging/iio/cdc/ad7746.c if (val < 0 || val > 43008000) { /* 21pF */ val 482 drivers/staging/iio/cdc/ad7746.c val /= 338646; val 484 drivers/staging/iio/cdc/ad7746.c chip->capdac[chan->channel][chan->differential] = val > 0 ? val 485 drivers/staging/iio/cdc/ad7746.c AD7746_CAPDAC_DACP(val) | AD7746_CAPDAC_DACEN : 0; val 510 drivers/staging/iio/cdc/ad7746.c ret = ad7746_store_cap_filter_rate_setup(chip, val); val 513 drivers/staging/iio/cdc/ad7746.c ret = ad7746_store_vt_filter_rate_setup(chip, val); val 530 drivers/staging/iio/cdc/ad7746.c int *val, int *val2, val 563 drivers/staging/iio/cdc/ad7746.c *val = (be32_to_cpu(chip->data.d32) & 0xFFFFFF) - 0x800000; val 571 drivers/staging/iio/cdc/ad7746.c *val = (*val * 125) / 256; val 575 drivers/staging/iio/cdc/ad7746.c *val = *val * 6; val 600 drivers/staging/iio/cdc/ad7746.c *val = 1; val 610 drivers/staging/iio/cdc/ad7746.c *val = ret; val 615 drivers/staging/iio/cdc/ad7746.c *val = AD7746_CAPDAC_DACP(chip->capdac[chan->channel] val 624 drivers/staging/iio/cdc/ad7746.c *val = 0; val 630 drivers/staging/iio/cdc/ad7746.c *val = 1170; val 645 drivers/staging/iio/cdc/ad7746.c *val = ad7746_cap_filter_rate_table[idx][0]; val 651 drivers/staging/iio/cdc/ad7746.c *val = ad7746_vt_filter_rate_table[idx][0]; val 178 drivers/staging/iio/frequency/ad9832.c unsigned long val; val 180 drivers/staging/iio/frequency/ad9832.c ret = kstrtoul(buf, 10, &val); val 188 drivers/staging/iio/frequency/ad9832.c ret = ad9832_write_frequency(st, this_attr->address, val); val 194 drivers/staging/iio/frequency/ad9832.c ret = ad9832_write_phase(st, this_attr->address, val); val 197 drivers/staging/iio/frequency/ad9832.c if (val) val 206 drivers/staging/iio/frequency/ad9832.c if (val == 1) { val 208 drivers/staging/iio/frequency/ad9832.c } else if (val == 0) { val 219 drivers/staging/iio/frequency/ad9832.c if (val > 3) { val 225 drivers/staging/iio/frequency/ad9832.c st->ctrl_fp |= AD9832_PHASE(val); val 232 drivers/staging/iio/frequency/ad9832.c if (val) val 151 drivers/staging/iio/frequency/ad9834.c unsigned long val; val 153 drivers/staging/iio/frequency/ad9834.c ret = kstrtoul(buf, 10, &val); val 161 drivers/staging/iio/frequency/ad9834.c ret = ad9834_write_frequency(st, this_attr->address, val); val 165 drivers/staging/iio/frequency/ad9834.c ret = ad9834_write_phase(st, this_attr->address, val); val 173 drivers/staging/iio/frequency/ad9834.c if (val) val 182 drivers/staging/iio/frequency/ad9834.c if (val) val 191 drivers/staging/iio/frequency/ad9834.c if (!val) { val 193 drivers/staging/iio/frequency/ad9834.c } else if (val == 1) { val 204 drivers/staging/iio/frequency/ad9834.c if (val) val 173 drivers/staging/iio/impedance-analyzer/ad5933.c unsigned char val, timeout = AD5933_MAX_RETRIES; val 177 drivers/staging/iio/impedance-analyzer/ad5933.c ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val); val 180 drivers/staging/iio/impedance-analyzer/ad5933.c if (val & event) val 181 drivers/staging/iio/impedance-analyzer/ad5933.c return val; val 299 drivers/staging/iio/impedance-analyzer/ad5933.c unsigned long val; val 302 drivers/staging/iio/impedance-analyzer/ad5933.c ret = kstrtoul(buf, 10, &val); val 306 drivers/staging/iio/impedance-analyzer/ad5933.c if (val > AD5933_MAX_OUTPUT_FREQ_Hz) val 312 drivers/staging/iio/impedance-analyzer/ad5933.c ret = ad5933_set_freq(st, this_attr->address, val); val 378 drivers/staging/iio/impedance-analyzer/ad5933.c u16 val; val 383 drivers/staging/iio/impedance-analyzer/ad5933.c ret = kstrtou16(buf, 10, &val); val 396 drivers/staging/iio/impedance-analyzer/ad5933.c if (val == st->range_avail[i]) { val 415 drivers/staging/iio/impedance-analyzer/ad5933.c val = clamp(val, (u16)0, (u16)0x7FF); val 416 drivers/staging/iio/impedance-analyzer/ad5933.c st->settling_cycles = val; val 419 drivers/staging/iio/impedance-analyzer/ad5933.c if (val > 1022) val 420 drivers/staging/iio/impedance-analyzer/ad5933.c val = (val >> 2) | (3 << 9); val 421 drivers/staging/iio/impedance-analyzer/ad5933.c else if (val > 511) val 422 drivers/staging/iio/impedance-analyzer/ad5933.c val = (val >> 1) | BIT(9); val 424 drivers/staging/iio/impedance-analyzer/ad5933.c dat = cpu_to_be16(val); val 430 drivers/staging/iio/impedance-analyzer/ad5933.c val = clamp(val, (u16)0, (u16)511); val 431 drivers/staging/iio/impedance-analyzer/ad5933.c st->freq_points = val; val 433 drivers/staging/iio/impedance-analyzer/ad5933.c dat = cpu_to_be16(val); val 500 drivers/staging/iio/impedance-analyzer/ad5933.c int *val, val 526 drivers/staging/iio/impedance-analyzer/ad5933.c *val = sign_extend32(be16_to_cpu(dat), 13); val 530 drivers/staging/iio/impedance-analyzer/ad5933.c *val = 1000; val 627 drivers/staging/iio/impedance-analyzer/ad5933.c int val[2]; val 654 drivers/staging/iio/impedance-analyzer/ad5933.c val[0] = be16_to_cpu(buf[0]); val 655 drivers/staging/iio/impedance-analyzer/ad5933.c val[1] = be16_to_cpu(buf[1]); val 657 drivers/staging/iio/impedance-analyzer/ad5933.c val[0] = be16_to_cpu(buf[0]); val 659 drivers/staging/iio/impedance-analyzer/ad5933.c iio_push_to_buffers(indio_dev, val); val 19 drivers/staging/iio/meter/ade7854-i2c.c u32 val, val 33 drivers/staging/iio/meter/ade7854-i2c.c st->tx[2] = val & 0xFF; val 37 drivers/staging/iio/meter/ade7854-i2c.c st->tx[2] = (val >> 8) & 0xFF; val 38 drivers/staging/iio/meter/ade7854-i2c.c st->tx[3] = val & 0xFF; val 42 drivers/staging/iio/meter/ade7854-i2c.c st->tx[2] = (val >> 16) & 0xFF; val 43 drivers/staging/iio/meter/ade7854-i2c.c st->tx[3] = (val >> 8) & 0xFF; val 44 drivers/staging/iio/meter/ade7854-i2c.c st->tx[4] = val & 0xFF; val 48 drivers/staging/iio/meter/ade7854-i2c.c st->tx[2] = (val >> 24) & 0xFF; val 49 drivers/staging/iio/meter/ade7854-i2c.c st->tx[3] = (val >> 16) & 0xFF; val 50 drivers/staging/iio/meter/ade7854-i2c.c st->tx[4] = (val >> 8) & 0xFF; val 51 drivers/staging/iio/meter/ade7854-i2c.c st->tx[5] = val & 0xFF; val 69 drivers/staging/iio/meter/ade7854-i2c.c u32 *val, val 90 drivers/staging/iio/meter/ade7854-i2c.c *val = st->rx[0]; val 93 drivers/staging/iio/meter/ade7854-i2c.c *val = (st->rx[0] << 8) | st->rx[1]; val 96 drivers/staging/iio/meter/ade7854-i2c.c *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2]; val 99 drivers/staging/iio/meter/ade7854-i2c.c *val = (st->rx[0] << 24) | (st->rx[1] << 16) | val 19 drivers/staging/iio/meter/ade7854-spi.c u32 val, val 37 drivers/staging/iio/meter/ade7854-spi.c st->tx[3] = val & 0xFF; val 41 drivers/staging/iio/meter/ade7854-spi.c st->tx[3] = (val >> 8) & 0xFF; val 42 drivers/staging/iio/meter/ade7854-spi.c st->tx[4] = val & 0xFF; val 46 drivers/staging/iio/meter/ade7854-spi.c st->tx[3] = (val >> 16) & 0xFF; val 47 drivers/staging/iio/meter/ade7854-spi.c st->tx[4] = (val >> 8) & 0xFF; val 48 drivers/staging/iio/meter/ade7854-spi.c st->tx[5] = val & 0xFF; val 52 drivers/staging/iio/meter/ade7854-spi.c st->tx[3] = (val >> 24) & 0xFF; val 53 drivers/staging/iio/meter/ade7854-spi.c st->tx[4] = (val >> 16) & 0xFF; val 54 drivers/staging/iio/meter/ade7854-spi.c st->tx[5] = (val >> 8) & 0xFF; val 55 drivers/staging/iio/meter/ade7854-spi.c st->tx[6] = val & 0xFF; val 71 drivers/staging/iio/meter/ade7854-spi.c u32 *val, val 104 drivers/staging/iio/meter/ade7854-spi.c *val = st->rx[0]; val 107 drivers/staging/iio/meter/ade7854-spi.c *val = be16_to_cpup((const __be16 *)st->rx); val 110 drivers/staging/iio/meter/ade7854-spi.c *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2]; val 113 drivers/staging/iio/meter/ade7854-spi.c *val = be32_to_cpup((const __be32 *)st->rx); val 29 drivers/staging/iio/meter/ade7854.c u32 val = 0; val 34 drivers/staging/iio/meter/ade7854.c ret = st->read_reg(dev, this_attr->address, &val, 8); val 38 drivers/staging/iio/meter/ade7854.c return sprintf(buf, "%u\n", val); val 46 drivers/staging/iio/meter/ade7854.c u32 val = 0; val 51 drivers/staging/iio/meter/ade7854.c ret = st->read_reg(dev, this_attr->address, &val, 16); val 55 drivers/staging/iio/meter/ade7854.c return sprintf(buf, "%u\n", val); val 63 drivers/staging/iio/meter/ade7854.c u32 val; val 68 drivers/staging/iio/meter/ade7854.c ret = st->read_reg(dev, this_attr->address, &val, 24); val 72 drivers/staging/iio/meter/ade7854.c return sprintf(buf, "%u\n", val); val 80 drivers/staging/iio/meter/ade7854.c u32 val = 0; val 85 drivers/staging/iio/meter/ade7854.c ret = st->read_reg(dev, this_attr->address, &val, 32); val 89 drivers/staging/iio/meter/ade7854.c return sprintf(buf, "%u\n", val); val 102 drivers/staging/iio/meter/ade7854.c u8 val; val 104 drivers/staging/iio/meter/ade7854.c ret = kstrtou8(buf, 10, &val); val 107 drivers/staging/iio/meter/ade7854.c ret = st->write_reg(dev, this_attr->address, val, 8); val 123 drivers/staging/iio/meter/ade7854.c u16 val; val 125 drivers/staging/iio/meter/ade7854.c ret = kstrtou16(buf, 10, &val); val 128 drivers/staging/iio/meter/ade7854.c ret = st->write_reg(dev, this_attr->address, val, 16); val 144 drivers/staging/iio/meter/ade7854.c u32 val; val 146 drivers/staging/iio/meter/ade7854.c ret = kstrtou32(buf, 10, &val); val 149 drivers/staging/iio/meter/ade7854.c ret = st->write_reg(dev, this_attr->address, val, 24); val 165 drivers/staging/iio/meter/ade7854.c u32 val; val 167 drivers/staging/iio/meter/ade7854.c ret = kstrtou32(buf, 10, &val); val 170 drivers/staging/iio/meter/ade7854.c ret = st->write_reg(dev, this_attr->address, val, 32); val 180 drivers/staging/iio/meter/ade7854.c u32 val; val 182 drivers/staging/iio/meter/ade7854.c st->read_reg(dev, ADE7854_CONFIG, &val, 16); val 183 drivers/staging/iio/meter/ade7854.c val |= BIT(7); /* Software Chip Reset */ val 185 drivers/staging/iio/meter/ade7854.c return st->write_reg(dev, ADE7854_CONFIG, val, 16); val 159 drivers/staging/iio/meter/ade7854.h int (*read_reg)(struct device *dev, u16 reg_address, u32 *val, val 161 drivers/staging/iio/meter/ade7854.h int (*write_reg)(struct device *dev, u16 reg_address, u32 val, val 461 drivers/staging/iio/resolver/ad2s1210.c int *val, val 498 drivers/staging/iio/resolver/ad2s1210.c *val = pos; val 509 drivers/staging/iio/resolver/ad2s1210.c *val = vel; val 245 drivers/staging/isdn/avm/avmcard.h unsigned int val = 0; val 246 drivers/staging/isdn/avm/avmcard.h val |= b1_get_byte(base); val 247 drivers/staging/isdn/avm/avmcard.h val |= (b1_get_byte(base) << 8); val 248 drivers/staging/isdn/avm/avmcard.h val |= (b1_get_byte(base) << 16); val 249 drivers/staging/isdn/avm/avmcard.h val |= (b1_get_byte(base) << 24); val 250 drivers/staging/isdn/avm/avmcard.h return val; val 258 drivers/staging/isdn/avm/avmcard.h static inline void b1_put_byte(unsigned int base, unsigned char val) val 261 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_WRITE, val); val 264 drivers/staging/isdn/avm/avmcard.h static inline int b1_save_put_byte(unsigned int base, unsigned char val) val 269 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_WRITE, val); val 273 drivers/staging/isdn/avm/avmcard.h static inline void b1_put_word(unsigned int base, unsigned int val) val 275 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, val & 0xff); val 276 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, (val >> 8) & 0xff); val 277 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, (val >> 16) & 0xff); val 278 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, (val >> 24) & 0xff); val 136 drivers/staging/isdn/avm/b1dma.c static int WriteReg(avmcard *card, u32 reg, u8 val) val 141 drivers/staging/isdn/avm/b1dma.c u32 tmp = val; val 161 drivers/staging/isdn/avm/b1dma.c static inline void _put_byte(void **pp, u8 val) val 164 drivers/staging/isdn/avm/b1dma.c *s++ = val; val 168 drivers/staging/isdn/avm/b1dma.c static inline void _put_word(void **pp, u32 val) val 171 drivers/staging/isdn/avm/b1dma.c *s++ = val & 0xff; val 172 drivers/staging/isdn/avm/b1dma.c *s++ = (val >> 8) & 0xff; val 173 drivers/staging/isdn/avm/b1dma.c *s++ = (val >> 16) & 0xff; val 174 drivers/staging/isdn/avm/b1dma.c *s++ = (val >> 24) & 0xff; val 189 drivers/staging/isdn/avm/b1dma.c u8 val; val 190 drivers/staging/isdn/avm/b1dma.c val = *s++; val 192 drivers/staging/isdn/avm/b1dma.c return val; val 198 drivers/staging/isdn/avm/b1dma.c u32 val; val 199 drivers/staging/isdn/avm/b1dma.c val = *s++; val 200 drivers/staging/isdn/avm/b1dma.c val |= (*s++ << 8); val 201 drivers/staging/isdn/avm/b1dma.c val |= (*s++ << 16); val 202 drivers/staging/isdn/avm/b1dma.c val |= (*s++ << 24); val 204 drivers/staging/isdn/avm/b1dma.c return val; val 197 drivers/staging/isdn/avm/c4.c u32 val; val 206 drivers/staging/isdn/avm/c4.c if (copy_from_user(&val, dp, sizeof(val))) val 209 drivers/staging/isdn/avm/c4.c memcpy(&val, dp, sizeof(val)); val 211 drivers/staging/isdn/avm/c4.c if (c4_poke(card, loadoff, val)) { val 221 drivers/staging/isdn/avm/c4.c val = 0; val 223 drivers/staging/isdn/avm/c4.c if (copy_from_user(&val, dp, left)) val 226 drivers/staging/isdn/avm/c4.c memcpy(&val, dp, left); val 228 drivers/staging/isdn/avm/c4.c if (c4_poke(card, loadoff, val)) { val 239 drivers/staging/isdn/avm/c4.c static inline void _put_byte(void **pp, u8 val) val 242 drivers/staging/isdn/avm/c4.c *s++ = val; val 246 drivers/staging/isdn/avm/c4.c static inline void _put_word(void **pp, u32 val) val 249 drivers/staging/isdn/avm/c4.c *s++ = val & 0xff; val 250 drivers/staging/isdn/avm/c4.c *s++ = (val >> 8) & 0xff; val 251 drivers/staging/isdn/avm/c4.c *s++ = (val >> 16) & 0xff; val 252 drivers/staging/isdn/avm/c4.c *s++ = (val >> 24) & 0xff; val 267 drivers/staging/isdn/avm/c4.c u8 val; val 268 drivers/staging/isdn/avm/c4.c val = *s++; val 270 drivers/staging/isdn/avm/c4.c return val; val 276 drivers/staging/isdn/avm/c4.c u32 val; val 277 drivers/staging/isdn/avm/c4.c val = *s++; val 278 drivers/staging/isdn/avm/c4.c val |= (*s++ << 8); val 279 drivers/staging/isdn/avm/c4.c val |= (*s++ << 16); val 280 drivers/staging/isdn/avm/c4.c val |= (*s++ << 24); val 282 drivers/staging/isdn/avm/c4.c return val; val 758 drivers/staging/isdn/avm/c4.c static int queue_sendconfigword(avmcard *card, u32 val) val 774 drivers/staging/isdn/avm/c4.c _put_word(&p, val); val 816 drivers/staging/isdn/avm/c4.c u8 val[4]; val 830 drivers/staging/isdn/avm/c4.c if (copy_from_user(val, dp, sizeof(val))) val 833 drivers/staging/isdn/avm/c4.c memcpy(val, dp, sizeof(val)); val 835 drivers/staging/isdn/avm/c4.c if ((retval = queue_sendconfig(card, val)) != 0) val 837 drivers/staging/isdn/avm/c4.c left -= sizeof(val); val 838 drivers/staging/isdn/avm/c4.c dp += sizeof(val); val 841 drivers/staging/isdn/avm/c4.c memset(val, 0, sizeof(val)); val 843 drivers/staging/isdn/avm/c4.c if (copy_from_user(&val, dp, left)) val 846 drivers/staging/isdn/avm/c4.c memcpy(&val, dp, left); val 848 drivers/staging/isdn/avm/c4.c if ((retval = queue_sendconfig(card, val)) != 0) val 1593 drivers/staging/isdn/gigaset/bas-gigaset.c static int req_submit(struct bc_state *bcs, int req, int val, int timeout) val 1599 drivers/staging/isdn/gigaset/bas-gigaset.c gig_dbg(DEBUG_USBREQ, "-------> 0x%02x (%d)", req, val); val 1613 drivers/staging/isdn/gigaset/bas-gigaset.c ucs->dr_ctrl.wValue = cpu_to_le16(val); val 1110 drivers/staging/isdn/gigaset/ev-layer.c unsigned long val; val 1380 drivers/staging/isdn/gigaset/ev-layer.c val = simple_strtoul(s, (char **) &e, 10); val 1381 drivers/staging/isdn/gigaset/ev-layer.c if (val > INT_MAX || e == s) val 1390 drivers/staging/isdn/gigaset/ev-layer.c cs->fwver[i] = val; val 608 drivers/staging/isdn/gigaset/ser-gigaset.c int rc, val; val 618 drivers/staging/isdn/gigaset/ser-gigaset.c val = 0; val 619 drivers/staging/isdn/gigaset/ser-gigaset.c rc = put_user(val, p); val 155 drivers/staging/isdn/gigaset/usb-gigaset.c unsigned mask, val; val 159 drivers/staging/isdn/gigaset/usb-gigaset.c val = tiocm_to_gigaset(new_state); val 161 drivers/staging/isdn/gigaset/usb-gigaset.c gig_dbg(DEBUG_USBREQ, "set flags 0x%02x with mask 0x%02x", val, mask); val 163 drivers/staging/isdn/gigaset/usb-gigaset.c (val & 0xff) | ((mask & 0xff) << 8), 0, val 175 drivers/staging/isdn/gigaset/usb-gigaset.c static int set_value(struct cardstate *cs, u8 req, u16 val) val 181 drivers/staging/isdn/gigaset/usb-gigaset.c (unsigned)req, (unsigned)val); val 191 drivers/staging/isdn/gigaset/usb-gigaset.c val, 0, NULL, 0, 2000 /*?*/); val 210 drivers/staging/isdn/gigaset/usb-gigaset.c u16 val; val 232 drivers/staging/isdn/gigaset/usb-gigaset.c val = 0x383fff / rate + 1; val 234 drivers/staging/isdn/gigaset/usb-gigaset.c return set_value(cs, 1, val); val 243 drivers/staging/isdn/gigaset/usb-gigaset.c u16 val = 0; val 247 drivers/staging/isdn/gigaset/usb-gigaset.c val |= (cflag & PARODD) ? 0x10 : 0x20; val 252 drivers/staging/isdn/gigaset/usb-gigaset.c val |= 5 << 8; break; val 254 drivers/staging/isdn/gigaset/usb-gigaset.c val |= 6 << 8; break; val 256 drivers/staging/isdn/gigaset/usb-gigaset.c val |= 7 << 8; break; val 258 drivers/staging/isdn/gigaset/usb-gigaset.c val |= 8 << 8; break; val 261 drivers/staging/isdn/gigaset/usb-gigaset.c val |= 8 << 8; val 268 drivers/staging/isdn/gigaset/usb-gigaset.c val |= 1; /* 1.5 stop bits */ val 270 drivers/staging/isdn/gigaset/usb-gigaset.c val |= 2; /* 2 stop bits */ val 273 drivers/staging/isdn/gigaset/usb-gigaset.c return set_value(cs, 3, val); val 28 drivers/staging/isdn/hysdn/boardergo.c #define byteout(addr, val) outb(val, addr) val 131 drivers/staging/isdn/hysdn/boardergo.c unsigned char val; val 138 drivers/staging/isdn/hysdn/boardergo.c val = bytein(card->iobase + PCI9050_INTR_REG); /* get actual value */ val 139 drivers/staging/isdn/hysdn/boardergo.c val &= ~(PCI9050_INTR_REG_ENPCI | PCI9050_INTR_REG_EN1); /* mask irq */ val 140 drivers/staging/isdn/hysdn/boardergo.c byteout(card->iobase + PCI9050_INTR_REG, val); val 101 drivers/staging/kpc2000/kpc2000/core.c u64 val; val 103 drivers/staging/kpc2000/kpc2000/core.c val = readq(pcard->sysinfo_regs_base + REG_CPLD_CONFIG); val 104 drivers/staging/kpc2000/kpc2000/core.c return sprintf(buf, "%016llx\n", val); val 133 drivers/staging/kpc2000/kpc2000/core.c u64 val; val 135 drivers/staging/kpc2000/kpc2000/core.c val = readq(pcard->sysinfo_regs_base + REG_INTERRUPT_MASK); val 136 drivers/staging/kpc2000/kpc2000/core.c return sprintf(buf, "%016llx\n", val); val 144 drivers/staging/kpc2000/kpc2000/core.c u64 val; val 146 drivers/staging/kpc2000/kpc2000/core.c val = readq(pcard->sysinfo_regs_base + REG_INTERRUPT_ACTIVE); val 147 drivers/staging/kpc2000/kpc2000/core.c return sprintf(buf, "%016llx\n", val); val 156 drivers/staging/kpc2000/kpc2000/core.c u64 val; val 158 drivers/staging/kpc2000/kpc2000/core.c val = readq(pcard->sysinfo_regs_base + REG_PCIE_ERROR_COUNT); val 159 drivers/staging/kpc2000/kpc2000/core.c return sprintf(buf, "%016llx\n", val); val 165 drivers/staging/kpc2000/kpc2000_spi.c u64 val; val 171 drivers/staging/kpc2000/kpc2000_spi.c val = readq(addr); val 172 drivers/staging/kpc2000/kpc2000_spi.c return val; val 176 drivers/staging/kpc2000/kpc2000_spi.c kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val) val 181 drivers/staging/kpc2000/kpc2000_spi.c writeq(val, addr); val 183 drivers/staging/kpc2000/kpc2000_spi.c cs->conf_cache = val; val 220 drivers/staging/kpc2000/kpc2000_spi.c char val = *tx++; val 227 drivers/staging/kpc2000/kpc2000_spi.c kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, val); val 167 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h u32 val = GetEngineControl(eng); val 169 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h val |= set_bits; val 170 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h val &= ~clear_bits; val 171 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h WriteEngineControl(eng, val); val 1287 drivers/staging/ks7010/ks_hostif.c enum mib_attribute attr, int val) val 1289 drivers/staging/ks7010/ks_hostif.c __le32 v = cpu_to_le32(val); val 1297 drivers/staging/ks7010/ks_hostif.c bool val) val 1299 drivers/staging/ks7010/ks_hostif.c __le32 v = cpu_to_le32(val); val 1631 drivers/staging/ks7010/ks_hostif.c &priv->reg.wep_key[0].val[0], val 1639 drivers/staging/ks7010/ks_hostif.c &priv->reg.wep_key[1].val[0], val 1647 drivers/staging/ks7010/ks_hostif.c &priv->reg.wep_key[2].val[0], val 1655 drivers/staging/ks7010/ks_hostif.c &priv->reg.wep_key[3].val[0], val 44 drivers/staging/ks7010/ks_wlan.h u8 val[13 * 2 + 1]; val 811 drivers/staging/ks7010/ks_wlan_net.c memcpy(&priv->reg.wep_key[index].val[0], &key.key[0], val 896 drivers/staging/ks7010/ks_wlan_net.c memcpy(extra, priv->reg.wep_key[index].val, enc->length); val 2239 drivers/staging/media/allegro-dvt/allegro-core.c "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val); val 2243 drivers/staging/media/allegro-dvt/allegro-core.c channel->level = ctrl->val; val 2246 drivers/staging/media/allegro-dvt/allegro-core.c channel->bitrate_mode = ctrl->val; val 2249 drivers/staging/media/allegro-dvt/allegro-core.c channel->bitrate = ctrl->val; val 2252 drivers/staging/media/allegro-dvt/allegro-core.c channel->bitrate_peak = ctrl->val; val 2255 drivers/staging/media/allegro-dvt/allegro-core.c channel->cpb_size = ctrl->val; val 2258 drivers/staging/media/allegro-dvt/allegro-core.c channel->gop_size = ctrl->val; val 39 drivers/staging/media/allegro-dvt/nal-h264.c int (*rbsp_bit)(struct rbsp *rbsp, int *val); val 40 drivers/staging/media/allegro-dvt/nal-h264.c int (*rbsp_bits)(struct rbsp *rbsp, int n, unsigned int *val); val 41 drivers/staging/media/allegro-dvt/nal-h264.c int (*rbsp_uev)(struct rbsp *rbsp, unsigned int *val); val 42 drivers/staging/media/allegro-dvt/nal-h264.c int (*rbsp_sev)(struct rbsp *rbsp, int *val); val 326 drivers/staging/media/hantro/hantro.h u32 val, u32 reg) val 328 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); val 329 drivers/staging/media/hantro/hantro.h writel_relaxed(val, vpu->enc_base + reg); val 332 drivers/staging/media/hantro/hantro.h static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg) val 334 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); val 335 drivers/staging/media/hantro/hantro.h writel(val, vpu->enc_base + reg); val 340 drivers/staging/media/hantro/hantro.h u32 val = readl(vpu->enc_base + reg); val 342 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); val 343 drivers/staging/media/hantro/hantro.h return val; val 347 drivers/staging/media/hantro/hantro.h u32 val, u32 reg) val 349 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); val 350 drivers/staging/media/hantro/hantro.h writel_relaxed(val, vpu->dec_base + reg); val 353 drivers/staging/media/hantro/hantro.h static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) val 355 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); val 356 drivers/staging/media/hantro/hantro.h writel(val, vpu->dec_base + reg); val 361 drivers/staging/media/hantro/hantro.h u32 val = readl(vpu->dec_base + reg); val 363 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); val 364 drivers/staging/media/hantro/hantro.h return val; val 369 drivers/staging/media/hantro/hantro.h u32 val) val 375 drivers/staging/media/hantro/hantro.h v |= ((val & reg->mask) << reg->shift); val 274 drivers/staging/media/hantro/hantro_drv.c vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); val 278 drivers/staging/media/hantro/hantro_drv.c ctx->jpeg_quality = ctrl->val; val 335 drivers/staging/media/hantro/hantro_g1_vp8_dec.c u32 val = 0; val 345 drivers/staging/media/hantro/hantro_g1_vp8_dec.c val = (hantro_vp8_dec_mc_filter[i][0] << 2) | val 366 drivers/staging/media/hantro/hantro_g1_vp8_dec.c hantro_reg_write(vpu, ®, val); val 1088 drivers/staging/media/imx/imx-ic-prpencvf.c hflip = (ctrl->val == 1); val 1091 drivers/staging/media/imx/imx-ic-prpencvf.c vflip = (ctrl->val == 1); val 1094 drivers/staging/media/imx/imx-ic-prpencvf.c rotation = ctrl->val; val 629 drivers/staging/media/imx/imx-media-csc-scaler.c hflip = ctrl->val; val 632 drivers/staging/media/imx/imx-media-csc-scaler.c vflip = ctrl->val; val 635 drivers/staging/media/imx/imx-media-csc-scaler.c rotate = ctrl->val; val 99 drivers/staging/media/imx/imx-media-fim.c fim->enabled = en->cur.val; val 100 drivers/staging/media/imx/imx-media-fim.c fim->icap_flags = icap_edge->cur.val; val 101 drivers/staging/media/imx/imx-media-fim.c fim->icap_channel = icap_chan->cur.val; val 102 drivers/staging/media/imx/imx-media-fim.c fim->num_avg = num->cur.val; val 103 drivers/staging/media/imx/imx-media-fim.c fim->num_skip = skip->cur.val; val 104 drivers/staging/media/imx/imx-media-fim.c fim->tolerance_min = tol_min->cur.val; val 105 drivers/staging/media/imx/imx-media-fim.c fim->tolerance_max = tol_max->cur.val; val 107 drivers/staging/media/imx/imx-media-fim.c fim->enabled = en->val; val 108 drivers/staging/media/imx/imx-media-fim.c fim->icap_flags = icap_edge->val; val 109 drivers/staging/media/imx/imx-media-fim.c fim->icap_channel = icap_chan->val; val 110 drivers/staging/media/imx/imx-media-fim.c fim->num_avg = num->val; val 111 drivers/staging/media/imx/imx-media-fim.c fim->num_skip = skip->val; val 112 drivers/staging/media/imx/imx-media-fim.c fim->tolerance_min = tol_min->val; val 113 drivers/staging/media/imx/imx-media-fim.c fim->tolerance_max = tol_max->val; val 423 drivers/staging/media/imx/imx-media-vdic.c motion = ctrl->val; val 205 drivers/staging/media/imx/imx6-mipi-csi2.c mbps_per_lane = DIV_ROUND_UP_ULL(2 * ctrl->qmenu_int[ctrl->val], val 232 drivers/staging/media/imx/imx7-media-csi.c unsigned int val = 0; val 235 drivers/staging/media/imx/imx7-media-csi.c val = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL | val 237 drivers/staging/media/imx/imx7-media-csi.c imx7_csi_reg_write(csi, val, CSI_CSICR1); val 242 drivers/staging/media/imx/imx7-media-csi.c val = BIT_DMA_REFLASH_RFF; val 243 drivers/staging/media/imx/imx7-media-csi.c imx7_csi_reg_write(csi, val, CSI_CSICR3); val 343 drivers/staging/media/imx/imx7-mipi-csis.c u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); val 346 drivers/staging/media/imx/imx7-mipi-csis.c val | MIPI_CSIS_CMN_CTRL_RESET); val 371 drivers/staging/media/imx/imx7-mipi-csis.c u32 val, mask; val 373 drivers/staging/media/imx/imx7-mipi-csis.c val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); val 375 drivers/staging/media/imx/imx7-mipi-csis.c val |= MIPI_CSIS_CMN_CTRL_ENABLE; val 377 drivers/staging/media/imx/imx7-mipi-csis.c val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; val 378 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); val 380 drivers/staging/media/imx/imx7-mipi-csis.c val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); val 381 drivers/staging/media/imx/imx7-mipi-csis.c val &= ~MIPI_CSIS_DPHYCTRL_ENABLE; val 384 drivers/staging/media/imx/imx7-mipi-csis.c val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE); val 386 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); val 393 drivers/staging/media/imx/imx7-mipi-csis.c u32 val; val 396 drivers/staging/media/imx/imx7-mipi-csis.c val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); val 397 drivers/staging/media/imx/imx7-mipi-csis.c val = (val & ~MIPI_CSIS_ISPCFG_FMT_MASK) | state->csis_fmt->fmt_reg; val 398 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val); val 401 drivers/staging/media/imx/imx7-mipi-csis.c val = mf->width | (mf->height << 16); val 402 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val); val 407 drivers/staging/media/imx/imx7-mipi-csis.c u32 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); val 409 drivers/staging/media/imx/imx7-mipi-csis.c val = ((val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | (hs_settle << 24)); val 411 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); val 417 drivers/staging/media/imx/imx7-mipi-csis.c u32 val; val 419 drivers/staging/media/imx/imx7-mipi-csis.c val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); val 420 drivers/staging/media/imx/imx7-mipi-csis.c val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; val 421 drivers/staging/media/imx/imx7-mipi-csis.c val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; val 422 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); val 428 drivers/staging/media/imx/imx7-mipi-csis.c val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); val 430 drivers/staging/media/imx/imx7-mipi-csis.c val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT; val 432 drivers/staging/media/imx/imx7-mipi-csis.c val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT; val 433 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val); val 435 drivers/staging/media/imx/imx7-mipi-csis.c val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) | val 438 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH0, val); val 440 drivers/staging/media/imx/imx7-mipi-csis.c val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL); val 441 drivers/staging/media/imx/imx7-mipi-csis.c val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC; val 443 drivers/staging/media/imx/imx7-mipi-csis.c val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; val 445 drivers/staging/media/imx/imx7-mipi-csis.c val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC; val 447 drivers/staging/media/imx/imx7-mipi-csis.c val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); val 448 drivers/staging/media/imx/imx7-mipi-csis.c val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; val 449 drivers/staging/media/imx/imx7-mipi-csis.c mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val); val 455 drivers/staging/media/imx/imx7-mipi-csis.c val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); val 457 drivers/staging/media/imx/imx7-mipi-csis.c val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | val 205 drivers/staging/media/ipu3/ipu3-css.c u32 val; val 207 drivers/staging/media/ipu3/ipu3-css.c return readl_poll_timeout(base + reg, val, (val & mask) == cmp, val 216 drivers/staging/media/ipu3/ipu3-css.c u32 pm_ctrl, state, val; val 263 drivers/staging/media/ipu3/ipu3-css.c val = pm_ctrl & ~(IMGU_PM_CTRL_CSS_PWRDN | IMGU_PM_CTRL_RST_AT_EOF); val 264 drivers/staging/media/ipu3/ipu3-css.c writel(val, base + IMGU_REG_PM_CTRL); val 271 drivers/staging/media/ipu3/ipu3-css.c val = (freq / IMGU_SYSTEM_REQ_FREQ_DIVIDER) & IMGU_SYSTEM_REQ_FREQ_MASK; val 272 drivers/staging/media/ipu3/ipu3-css.c writel(val, base + IMGU_REG_SYSTEM_REQ); val 291 drivers/staging/media/ipu3/ipu3-css.c val = readl(base + IMGU_REG_PM_CTRL); /* get pm_ctrl */ val 292 drivers/staging/media/ipu3/ipu3-css.c val &= ~(IMGU_PM_CTRL_CSS_PWRDN | IMGU_PM_CTRL_RST_AT_EOF); val 293 drivers/staging/media/ipu3/ipu3-css.c val |= pm_ctrl & (IMGU_PM_CTRL_CSS_PWRDN | IMGU_PM_CTRL_RST_AT_EOF); val 294 drivers/staging/media/ipu3/ipu3-css.c writel(val, base + IMGU_REG_PM_CTRL); val 329 drivers/staging/media/ipu3/ipu3-css.c u32 val, i; val 337 drivers/staging/media/ipu3/ipu3-css.c val = readl(base + IMGU_REG_SP_CTRL(0)) | IMGU_CTRL_IRQ_READY; val 338 drivers/staging/media/ipu3/ipu3-css.c writel(val, base + IMGU_REG_SP_CTRL(0)); val 339 drivers/staging/media/ipu3/ipu3-css.c writel(val | IMGU_CTRL_IRQ_CLEAR, base + IMGU_REG_SP_CTRL(0)); val 427 drivers/staging/media/ipu3/ipu3-css.c u32 val, i; val 456 drivers/staging/media/ipu3/ipu3-css.c val = readl(base + stream_monitors[i].reg); val 457 drivers/staging/media/ipu3/ipu3-css.c if (val & stream_monitors[i].mask) { val 1589 drivers/staging/media/ipu3/ipu3-css.c u32 val = max_t(u32, IPU3_CSS_MIN_RES, res); val 1591 drivers/staging/media/ipu3/ipu3-css.c return DIV_ROUND_CLOSEST(val, align) * align; val 2372 drivers/staging/media/ipu3/ipu3-css.c u32 val = readl(base + IMGU_REG_SP_DMEM_BASE(0) + val 2376 drivers/staging/media/ipu3/ipu3-css.c __func__, i, cnt, val); val 104 drivers/staging/media/ipu3/ipu3-mmu.c u32 val; val 108 drivers/staging/media/ipu3/ipu3-mmu.c val, (val & 1) == halt, 1000, 100000); val 1022 drivers/staging/media/ipu3/ipu3-v4l2.c ctrl->val, ctrl->id, imgu_sd->pipe); val 1026 drivers/staging/media/ipu3/ipu3-v4l2.c atomic_set(&imgu_sd->running_mode, ctrl->val); val 23 drivers/staging/media/meson/vdec/vdec_helpers.c void amvdec_write_dos(struct amvdec_core *core, u32 reg, u32 val) val 25 drivers/staging/media/meson/vdec/vdec_helpers.c writel_relaxed(val, core->dos_base + reg); val 29 drivers/staging/media/meson/vdec/vdec_helpers.c void amvdec_write_dos_bits(struct amvdec_core *core, u32 reg, u32 val) val 31 drivers/staging/media/meson/vdec/vdec_helpers.c amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) | val); val 35 drivers/staging/media/meson/vdec/vdec_helpers.c void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val) val 37 drivers/staging/media/meson/vdec/vdec_helpers.c amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) & ~val); val 47 drivers/staging/media/meson/vdec/vdec_helpers.c void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val) val 49 drivers/staging/media/meson/vdec/vdec_helpers.c writel_relaxed(val, core->esparser_base + reg); val 24 drivers/staging/media/meson/vdec/vdec_helpers.h void amvdec_write_dos(struct amvdec_core *core, u32 reg, u32 val); val 25 drivers/staging/media/meson/vdec/vdec_helpers.h void amvdec_write_dos_bits(struct amvdec_core *core, u32 reg, u32 val); val 26 drivers/staging/media/meson/vdec/vdec_helpers.h void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val); val 28 drivers/staging/media/meson/vdec/vdec_helpers.h void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val); val 77 drivers/staging/media/omap4iss/iss.h u32 val; val 414 drivers/staging/media/soc_camera/mt9t031.c reg->val = reg_read(client, reg->reg); val 416 drivers/staging/media/soc_camera/mt9t031.c if (reg->val > 0xffff) val 430 drivers/staging/media/soc_camera/mt9t031.c if (reg_write(client, reg->reg, reg->val) < 0) val 448 drivers/staging/media/soc_camera/mt9t031.c mt9t031->exposure->val = val 467 drivers/staging/media/soc_camera/mt9t031.c if (ctrl->val) val 475 drivers/staging/media/soc_camera/mt9t031.c if (ctrl->val) val 484 drivers/staging/media/soc_camera/mt9t031.c if (ctrl->val <= ctrl->default_value) { val 487 drivers/staging/media/soc_camera/mt9t031.c data = ((ctrl->val - (s32)ctrl->minimum) * 8 + range / 2) / range; val 498 drivers/staging/media/soc_camera/mt9t031.c unsigned long gain = ((ctrl->val - (s32)ctrl->default_value - 1) * val 518 drivers/staging/media/soc_camera/mt9t031.c if (ctrl->val == V4L2_EXPOSURE_MANUAL) { val 520 drivers/staging/media/soc_camera/mt9t031.c unsigned int shutter = ((exp->val - (s32)exp->minimum) * 1048 + val 491 drivers/staging/media/soc_camera/soc_mt9v022.c reg->val = reg_read(client, reg->reg); val 493 drivers/staging/media/soc_camera/soc_mt9v022.c if (reg->val > 0xffff) val 507 drivers/staging/media/soc_camera/soc_mt9v022.c if (reg_write(client, reg->reg, reg->val) < 0) val 541 drivers/staging/media/soc_camera/soc_mt9v022.c gain->val = ((data - 16) * range + 24) / 48 + gain->minimum; val 549 drivers/staging/media/soc_camera/soc_mt9v022.c exp->val = ((data - 1) * range + 239) / 479 + exp->minimum; val 555 drivers/staging/media/soc_camera/soc_mt9v022.c ctrl->val = data; val 561 drivers/staging/media/soc_camera/soc_mt9v022.c ctrl->val = data; val 577 drivers/staging/media/soc_camera/soc_mt9v022.c if (ctrl->val) val 585 drivers/staging/media/soc_camera/soc_mt9v022.c if (ctrl->val) val 593 drivers/staging/media/soc_camera/soc_mt9v022.c if (ctrl->val) { val 601 drivers/staging/media/soc_camera/soc_mt9v022.c unsigned long gain_val = ((gain->val - (s32)gain->minimum) * val 621 drivers/staging/media/soc_camera/soc_mt9v022.c if (ctrl->val == V4L2_EXPOSURE_AUTO) { val 626 drivers/staging/media/soc_camera/soc_mt9v022.c unsigned long shutter = ((exp->val - (s32)exp->minimum) * val 646 drivers/staging/media/soc_camera/soc_mt9v022.c ctrl->val) < 0) val 651 drivers/staging/media/soc_camera/soc_mt9v022.c ctrl->val) < 0) val 638 drivers/staging/media/soc_camera/soc_ov5642.c static int reg_read(struct i2c_client *client, u16 reg, u8 *val) val 651 drivers/staging/media/soc_camera/soc_ov5642.c ret = i2c_master_recv(client, val, 1); val 660 drivers/staging/media/soc_camera/soc_ov5642.c static int reg_write(struct i2c_client *client, u16 reg, u8 val) val 663 drivers/staging/media/soc_camera/soc_ov5642.c unsigned char data[3] = { reg >> 8, reg & 0xff, val }; val 695 drivers/staging/media/soc_camera/soc_ov5642.c u8 val; val 702 drivers/staging/media/soc_camera/soc_ov5642.c ret = reg_read(client, reg->reg, &val); val 704 drivers/staging/media/soc_camera/soc_ov5642.c reg->val = (__u64)val; val 714 drivers/staging/media/soc_camera/soc_ov5642.c if (reg->reg & ~0xffff || reg->val & ~0xff) val 717 drivers/staging/media/soc_camera/soc_ov5642.c return reg_write(client, reg->reg, reg->val); val 189 drivers/staging/media/soc_camera/soc_ov9740.c u8 val; val 396 drivers/staging/media/soc_camera/soc_ov9740.c static int ov9740_reg_read(struct i2c_client *client, u16 reg, u8 *val) val 410 drivers/staging/media/soc_camera/soc_ov9740.c .buf = val, val 426 drivers/staging/media/soc_camera/soc_ov9740.c static int ov9740_reg_write(struct i2c_client *client, u16 reg, u8 val) val 431 drivers/staging/media/soc_camera/soc_ov9740.c u8 val; val 438 drivers/staging/media/soc_camera/soc_ov9740.c buf.val = val; val 458 drivers/staging/media/soc_camera/soc_ov9740.c u8 val; val 461 drivers/staging/media/soc_camera/soc_ov9740.c ret = ov9740_reg_read(client, reg, &val); val 469 drivers/staging/media/soc_camera/soc_ov9740.c val |= set; val 470 drivers/staging/media/soc_camera/soc_ov9740.c val &= ~unset; val 472 drivers/staging/media/soc_camera/soc_ov9740.c ret = ov9740_reg_write(client, reg, val); val 492 drivers/staging/media/soc_camera/soc_ov9740.c regarray[i].reg, regarray[i].val); val 748 drivers/staging/media/soc_camera/soc_ov9740.c priv->flag_vflip = ctrl->val; val 751 drivers/staging/media/soc_camera/soc_ov9740.c priv->flag_hflip = ctrl->val; val 794 drivers/staging/media/soc_camera/soc_ov9740.c u8 val; val 801 drivers/staging/media/soc_camera/soc_ov9740.c ret = ov9740_reg_read(client, reg->reg, &val); val 805 drivers/staging/media/soc_camera/soc_ov9740.c reg->val = (__u64)val; val 815 drivers/staging/media/soc_camera/soc_ov9740.c if (reg->reg & ~0xffff || reg->val & ~0xff) val 818 drivers/staging/media/soc_camera/soc_ov9740.c return ov9740_reg_write(client, reg->reg, reg->val); val 159 drivers/staging/media/sunxi/cedrus/cedrus.h static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) val 161 drivers/staging/media/sunxi/cedrus/cedrus.h writel(val, dev->base + reg); val 277 drivers/staging/media/sunxi/cedrus/cedrus_h264.c u32 val; val 279 drivers/staging/media/sunxi/cedrus/cedrus_h264.c val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | val 281 drivers/staging/media/sunxi/cedrus/cedrus_h264.c cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); val 286 drivers/staging/media/sunxi/cedrus/cedrus_h264.c u32 val; val 288 drivers/staging/media/sunxi/cedrus/cedrus_h264.c val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | val 290 drivers/staging/media/sunxi/cedrus/cedrus_h264.c cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); val 133 drivers/staging/media/tegra-vde/vde.c static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val) val 135 drivers/staging/media/tegra-vde/vde.c tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF), val 137 drivers/staging/media/tegra-vde/vde.c tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16), val 613 drivers/staging/most/core.c int most_set_cfg_buffer_size(char *mdev, char *mdev_ch, u16 val) val 619 drivers/staging/most/core.c c->cfg.buffer_size = val; val 623 drivers/staging/most/core.c int most_set_cfg_subbuffer_size(char *mdev, char *mdev_ch, u16 val) val 629 drivers/staging/most/core.c c->cfg.subbuffer_size = val; val 633 drivers/staging/most/core.c int most_set_cfg_dbr_size(char *mdev, char *mdev_ch, u16 val) val 639 drivers/staging/most/core.c c->cfg.dbr_size = val; val 643 drivers/staging/most/core.c int most_set_cfg_num_buffers(char *mdev, char *mdev_ch, u16 val) val 649 drivers/staging/most/core.c c->cfg.num_buffers = val; val 693 drivers/staging/most/core.c int most_set_cfg_packets_xact(char *mdev, char *mdev_ch, u16 val) val 699 drivers/staging/most/core.c c->cfg.packets_per_xact = val; val 329 drivers/staging/most/core.h int most_set_cfg_buffer_size(char *mdev, char *mdev_ch, u16 val); val 330 drivers/staging/most/core.h int most_set_cfg_subbuffer_size(char *mdev, char *mdev_ch, u16 val); val 331 drivers/staging/most/core.h int most_set_cfg_dbr_size(char *mdev, char *mdev_ch, u16 val); val 332 drivers/staging/most/core.h int most_set_cfg_num_buffers(char *mdev, char *mdev_ch, u16 val); val 335 drivers/staging/most/core.h int most_set_cfg_packets_xact(char *mdev, char *mdev_ch, u16 val); val 704 drivers/staging/most/dim2/dim2.c static int get_dim2_clk_speed(const char *clock_speed, u8 *val) val 710 drivers/staging/most/dim2/dim2.c *val = clk_mt[i].clk_speed; val 145 drivers/staging/most/dim2/hal.c static void dim2_transfer_madr(u32 val) val 147 drivers/staging/most/dim2/hal.c writel(val, &g.dim2->MADR); val 77 drivers/staging/most/sound/sound.c #define swap16(val) ( \ val 78 drivers/staging/most/sound/sound.c (((u16)(val) << 8) & (u16)0xFF00) | \ val 79 drivers/staging/most/sound/sound.c (((u16)(val) >> 8) & (u16)0x00FF)) val 81 drivers/staging/most/sound/sound.c #define swap32(val) ( \ val 82 drivers/staging/most/sound/sound.c (((u32)(val) << 24) & (u32)0xFF000000) | \ val 83 drivers/staging/most/sound/sound.c (((u32)(val) << 8) & (u32)0x00FF0000) | \ val 84 drivers/staging/most/sound/sound.c (((u32)(val) >> 8) & (u32)0x0000FF00) | \ val 85 drivers/staging/most/sound/sound.c (((u32)(val) >> 24) & (u32)0x000000FF)) val 921 drivers/staging/most/usb/usb.c u16 val; val 934 drivers/staging/most/usb/usb.c err = drci_rd_reg(dci_obj->usb_device, reg_addr, &val); val 938 drivers/staging/most/usb/usb.c return snprintf(buf, PAGE_SIZE, "%04x\n", val); val 944 drivers/staging/most/usb/usb.c u16 val; val 949 drivers/staging/most/usb/usb.c int err = kstrtou16(buf, 16, &val); val 955 drivers/staging/most/usb/usb.c dci_obj->reg_addr = val; val 960 drivers/staging/most/usb/usb.c err = drci_wr_reg(usb_dev, dci_obj->reg_addr, val); val 962 drivers/staging/most/usb/usb.c err = start_sync_ep(usb_dev, val); val 964 drivers/staging/most/usb/usb.c err = drci_wr_reg(usb_dev, reg_addr, val); val 189 drivers/staging/mt7621-dma/mtk-hsdma.c unsigned int reg, u32 val) val 191 drivers/staging/mt7621-dma/mtk-hsdma.c writel(val, hsdma->base + reg); val 111 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c u32 val; val 113 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c regmap_read(phy->regmap, reg, &val); val 115 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c return val; val 118 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32 reg) val 120 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c regmap_write(phy->regmap, reg, val); val 142 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c u32 val; val 147 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_FRC_H_XTAL_REG); val 148 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE); val 149 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_FRC_H_XTAL_TYPE; val 150 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_XTAL_TYPE_VAL(0x00); val 151 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_FRC_H_XTAL_REG); val 156 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, offset); val 157 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); val 158 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_FRC_PHY_EN; val 159 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, offset); val 162 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_H_PLL_REG); val 163 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_H_PLL_PREDIV); val 166 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_PLL_PREDIV_VAL(0x01); val 167 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_H_PLL_REG); val 170 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_PLL_PREDIV_VAL(0x00); val 171 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_H_PLL_REG); val 176 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_H_PLL_FBKSEL_REG); val 177 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_H_PLL_FBKSEL); val 178 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_PLL_FBKSEL_VAL(0x01); val 179 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_H_PLL_FBKSEL_REG); val 182 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_H_LCDDS_SSC_PRD_REG); val 183 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_H_LCDDS_SSC_PRD); val 184 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000); val 185 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG); val 188 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_H_LCDDS_SSC_PRD_REG); val 189 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_H_LCDDS_SSC_PRD); val 190 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d); val 191 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG); val 194 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG); val 195 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_H_LCDDS_SSC_DELTA | val 197 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a); val 198 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a); val 199 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_H_LCDDS_SSC_DELTA_REG); val 206 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_LCDDS_CLK_PH_INV_REG); val 207 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_LCDDS_CLK_PH_INV); val 208 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_LCDDS_CLK_PH_INV; val 209 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_LCDDS_CLK_PH_INV_REG); val 212 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_H_PLL_REG); val 213 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR | val 215 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_PLL_BC_VAL(0x02); val 216 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_PLL_BP_VAL(0x06); val 217 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_PLL_IR_VAL(0x02); val 218 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_PLL_IC_VAL(0x01); val 219 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_PLL_DIVEN_VAL(0x02); val 220 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_H_PLL_REG); val 222 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_H_PLL_BR_REG); val 223 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_H_PLL_BR); val 224 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_H_PLL_BR_VAL(0x00); val 225 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_H_PLL_BR_REG); val 229 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(phy, RG_PE1_MSTCKDIV_REG); val 230 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV); val 231 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= (RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV); val 232 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, val, RG_PE1_MSTCKDIV_REG); val 255 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c u32 val; val 258 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(mphy, offset); val 259 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); val 260 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= (RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); val 261 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(mphy, val, offset); val 272 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c u32 val; val 275 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val = phy_read(mphy, offset); val 276 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); val 277 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c val |= RG_PE1_FRC_PHY_EN; val 278 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(mphy, val, offset); val 152 drivers/staging/mt7621-pci/pci-mt7621.c static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) val 154 drivers/staging/mt7621-pci/pci-mt7621.c writel(val, pcie->base + reg); val 163 drivers/staging/mt7621-pci/pci-mt7621.c u32 val, u32 reg) val 165 drivers/staging/mt7621-pci/pci-mt7621.c writel(val, port->base + reg); val 202 drivers/staging/mt7621-pci/pci-mt7621.c u32 reg, u32 val) val 207 drivers/staging/mt7621-pci/pci-mt7621.c pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); val 457 drivers/staging/mt7621-pci/pci-mt7621.c u32 val = 0; val 472 drivers/staging/mt7621-pci/pci-mt7621.c val = read_config(pcie, slot, PCIE_FTS_NUM); val 474 drivers/staging/mt7621-pci/pci-mt7621.c (unsigned int)val); val 508 drivers/staging/mt7621-pci/pci-mt7621.c u32 val; val 511 drivers/staging/mt7621-pci/pci-mt7621.c val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); val 512 drivers/staging/mt7621-pci/pci-mt7621.c val |= PCIE_PORT_INT_EN(slot); val 513 drivers/staging/mt7621-pci/pci-mt7621.c pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); val 532 drivers/staging/mt7621-pci/pci-mt7621.c u32 val; val 543 drivers/staging/mt7621-pci/pci-mt7621.c val = read_config(pcie, slot, PCI_COMMAND); val 544 drivers/staging/mt7621-pci/pci-mt7621.c val |= PCI_COMMAND_MASTER; val 545 drivers/staging/mt7621-pci/pci-mt7621.c write_config(pcie, slot, PCI_COMMAND, val); val 547 drivers/staging/mt7621-pci/pci-mt7621.c val = read_config(pcie, slot, PCIE_FTS_NUM); val 548 drivers/staging/mt7621-pci/pci-mt7621.c val &= ~PCIE_FTS_NUM_MASK; val 549 drivers/staging/mt7621-pci/pci-mt7621.c val |= PCIE_FTS_NUM_L0(0x50); val 550 drivers/staging/mt7621-pci/pci-mt7621.c write_config(pcie, slot, PCIE_FTS_NUM, val); val 557 drivers/staging/mt7621-pci/pci-mt7621.c u32 val = 0; val 583 drivers/staging/mt7621-pci/pci-mt7621.c val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); val 584 drivers/staging/mt7621-pci/pci-mt7621.c val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK); val 585 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x1 << MT7621_BR0_SHIFT; val 586 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x0 << MT7621_BR1_SHIFT; val 587 drivers/staging/mt7621-pci/pci-mt7621.c pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); val 590 drivers/staging/mt7621-pci/pci-mt7621.c val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); val 591 drivers/staging/mt7621-pci/pci-mt7621.c val &= ~MT7621_BR_ALL_MASK; val 592 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x1 << MT7621_BR0_SHIFT; val 593 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x2 << MT7621_BR1_SHIFT; val 594 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x0 << MT7621_BR2_SHIFT; val 595 drivers/staging/mt7621-pci/pci-mt7621.c pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); val 598 drivers/staging/mt7621-pci/pci-mt7621.c val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); val 599 drivers/staging/mt7621-pci/pci-mt7621.c val &= ~MT7621_BR_ALL_MASK; val 600 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x0 << MT7621_BR0_SHIFT; val 601 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x2 << MT7621_BR1_SHIFT; val 602 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x1 << MT7621_BR2_SHIFT; val 603 drivers/staging/mt7621-pci/pci-mt7621.c pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); val 606 drivers/staging/mt7621-pci/pci-mt7621.c val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); val 607 drivers/staging/mt7621-pci/pci-mt7621.c val &= ~MT7621_BR_ALL_MASK; val 608 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x2 << MT7621_BR0_SHIFT; val 609 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x0 << MT7621_BR1_SHIFT; val 610 drivers/staging/mt7621-pci/pci-mt7621.c val |= 0x1 << MT7621_BR2_SHIFT; val 611 drivers/staging/mt7621-pci/pci-mt7621.c pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); val 35 drivers/staging/netlogic/xlr_net.c static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val) val 37 drivers/staging/netlogic/xlr_net.c __raw_writel(val, base + reg); val 45 drivers/staging/netlogic/xlr_net.c static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask) val 50 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask)); val 521 drivers/staging/netlogic/xlr_net.c u32 val; val 558 drivers/staging/netlogic/xlr_net.c val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) | val 562 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val); val 569 drivers/staging/netlogic/xlr_net.c u32 val; val 590 drivers/staging/netlogic/xlr_net.c val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7)); val 591 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val); val 592 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val); val 597 drivers/staging/netlogic/xlr_net.c static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val) val 610 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val); val 664 drivers/staging/netlogic/xlr_net.c static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val) val 669 drivers/staging/netlogic/xlr_net.c ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val); val 671 drivers/staging/netlogic/xlr_net.c phy_addr, regnum, val, ret); val 723 drivers/staging/nvec/nvec.c u32 val; val 731 drivers/staging/nvec/nvec.c val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN | val 733 drivers/staging/nvec/nvec.c writel(val, nvec->base + I2C_CNFG); val 224 drivers/staging/nvec/nvec_power.c union power_supply_propval *val) val 230 drivers/staging/nvec/nvec_power.c val->intval = power->on; val 240 drivers/staging/nvec/nvec_power.c union power_supply_propval *val) val 246 drivers/staging/nvec/nvec_power.c val->intval = power->bat_status; val 249 drivers/staging/nvec/nvec_power.c val->intval = power->bat_cap; val 252 drivers/staging/nvec/nvec_power.c val->intval = power->bat_present; val 255 drivers/staging/nvec/nvec_power.c val->intval = power->bat_voltage_now; val 258 drivers/staging/nvec/nvec_power.c val->intval = power->bat_current_now; val 261 drivers/staging/nvec/nvec_power.c val->intval = power->bat_current_avg; val 264 drivers/staging/nvec/nvec_power.c val->intval = power->time_remain; val 267 drivers/staging/nvec/nvec_power.c val->intval = power->charge_full_design; val 270 drivers/staging/nvec/nvec_power.c val->intval = power->charge_last_full; val 273 drivers/staging/nvec/nvec_power.c val->intval = power->critical_capacity; val 276 drivers/staging/nvec/nvec_power.c val->intval = power->capacity_remain; val 279 drivers/staging/nvec/nvec_power.c val->intval = power->bat_temperature; val 282 drivers/staging/nvec/nvec_power.c val->strval = power->bat_manu; val 285 drivers/staging/nvec/nvec_power.c val->strval = power->bat_model; val 288 drivers/staging/nvec/nvec_power.c val->intval = power->bat_type_enum; val 1234 drivers/staging/octeon/octeon-stubs.h static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) val 46 drivers/staging/olpc_dcon/olpc_dcon.c static s32 dcon_write(struct dcon_priv *dcon, u8 reg, u16 val) val 48 drivers/staging/olpc_dcon/olpc_dcon.c return i2c_smbus_write_word_data(dcon->client, reg, val); val 180 drivers/staging/olpc_dcon/olpc_dcon_xo_1.c static void dcon_set_dconload_1(int val) val 182 drivers/staging/olpc_dcon/olpc_dcon_xo_1.c gpiod_set_value(gpios[OLPC_DCON_LOAD], val); val 180 drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c static void dcon_set_dconload_xo_1_5(int val) val 182 drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c gpiod_set_value(gpios[OLPC_DCON_LOAD], val); val 2166 drivers/staging/qlge/qlge.h static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val) val 2168 drivers/staging/qlge/qlge.h writel(val, qdev->reg_base + reg); val 2181 drivers/staging/qlge/qlge.h static inline void ql_write_db_reg(u32 val, void __iomem *addr) val 2183 drivers/staging/qlge/qlge.h writel(val, addr); val 2197 drivers/staging/qlge/qlge.h static inline void ql_write_db_reg_relaxed(u32 val, void __iomem *addr) val 2199 drivers/staging/qlge/qlge.h writel_relaxed(val, addr); val 567 drivers/staging/qlge/qlge_dbg.c u32 val; val 579 drivers/staging/qlge/qlge_dbg.c val = RT_IDX_RS val 582 drivers/staging/qlge/qlge_dbg.c ql_write32(qdev, RT_IDX, val); val 608 drivers/staging/qlge/qlge_dbg.c u32 val; val 662 drivers/staging/qlge/qlge_dbg.c val = initial_val val 666 drivers/staging/qlge/qlge_dbg.c ql_write32(qdev, MAC_ADDR_IDX, val); val 162 drivers/staging/ralink-gdma/ralink-gdma.c unsigned int reg, uint32_t val) val 164 drivers/staging/ralink-gdma/ralink-gdma.c writel(val, dma_dev->base + reg); val 1020 drivers/staging/rtl8188eu/core/rtw_cmd.c u8 val = 0; val 1022 drivers/staging/rtl8188eu/core/rtw_cmd.c rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &val); val 1024 drivers/staging/rtl8188eu/core/rtw_cmd.c while (!val) { val 1032 drivers/staging/rtl8188eu/core/rtw_cmd.c rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &val); val 38 drivers/staging/rtl8188eu/core/rtw_debug.c u32 addr, val, len; val 46 drivers/staging/rtl8188eu/core/rtw_debug.c int num = sscanf(tmp, "%x %x %x", &addr, &val, &len); val 54 drivers/staging/rtl8188eu/core/rtw_debug.c usb_write8(padapter, addr, (u8)val); val 57 drivers/staging/rtl8188eu/core/rtw_debug.c usb_write16(padapter, addr, (u16)val); val 60 drivers/staging/rtl8188eu/core/rtw_debug.c usb_write32(padapter, addr, val); val 60 drivers/staging/rtl8188eu/core/rtw_ieee80211.c int rtw_get_bit_value_from_ieee_value(u8 val) val 68 drivers/staging/rtl8188eu/core/rtw_ieee80211.c if (dot11_rate_table[i] == val) val 263 drivers/staging/rtl8188eu/core/rtw_mlme.c __le16 val; val 265 drivers/staging/rtl8188eu/core/rtw_mlme.c memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->ies), 2); val 267 drivers/staging/rtl8188eu/core/rtw_mlme.c return le16_to_cpu(val); val 886 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c unsigned short val; val 931 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c val = *(unsigned short *)rtw_get_capability_from_ie(ie); val 933 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_, &val, &pattrib->pktlen); val 267 drivers/staging/rtl8188eu/core/rtw_security.c static void secmicputuint32(u8 *p, u32 val) val 273 drivers/staging/rtl8188eu/core/rtw_security.c *p++ = (u8)(val & 0xff); val 274 drivers/staging/rtl8188eu/core/rtw_security.c val >>= 8; val 621 drivers/staging/rtl8188eu/core/rtw_security.c pnl = (u16)(dot11txpn.val); val 622 drivers/staging/rtl8188eu/core/rtw_security.c pnh = (u32)(dot11txpn.val>>16); val 698 drivers/staging/rtl8188eu/core/rtw_security.c pnl = (u16)(dot11txpn.val); val 699 drivers/staging/rtl8188eu/core/rtw_security.c pnh = (u32)(dot11txpn.val>>16); val 159 drivers/staging/rtl8188eu/core/rtw_wlan_util.c unsigned char val; val 163 drivers/staging/rtl8188eu/core/rtw_wlan_util.c val = pmlmeext->basicrate[i]; val 165 drivers/staging/rtl8188eu/core/rtw_wlan_util.c if ((val != 0xff) && (val != 0xfe)) { val 166 drivers/staging/rtl8188eu/core/rtw_wlan_util.c if (rate == ratetbl_val_2wifirate(val)) val 346 drivers/staging/rtl8188eu/core/rtw_wlan_util.c __le16 val; val 348 drivers/staging/rtl8188eu/core/rtw_wlan_util.c memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->ies), 2); val 350 drivers/staging/rtl8188eu/core/rtw_wlan_util.c return le16_to_cpu(val); val 413 drivers/staging/rtl8188eu/core/rtw_wlan_util.c unsigned int i, val, addr; val 422 drivers/staging/rtl8188eu/core/rtw_wlan_util.c val = ctrl | (mac[0] << 16) | (mac[1] << 24); val 425 drivers/staging/rtl8188eu/core/rtw_wlan_util.c val = mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24); val 429 drivers/staging/rtl8188eu/core/rtw_wlan_util.c val = key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | val 434 drivers/staging/rtl8188eu/core/rtw_wlan_util.c cam_val[0] = val; val 1129 drivers/staging/rtl8188eu/hal/usb_halinit.c static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val) val 1132 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 mode = *((u8 *)val); val 1186 drivers/staging/rtl8188eu/hal/usb_halinit.c static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val) val 1194 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, (reg_macid + idx), val[idx]); val 1197 drivers/staging/rtl8188eu/hal/usb_halinit.c static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val) val 1205 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, (reg_bssid + idx), val[idx]); val 1208 drivers/staging/rtl8188eu/hal/usb_halinit.c static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val) val 1214 drivers/staging/rtl8188eu/hal/usb_halinit.c if (*((u8 *)val)) val 1220 drivers/staging/rtl8188eu/hal/usb_halinit.c void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val) val 1232 drivers/staging/rtl8188eu/hal/usb_halinit.c val8 |= *((u8 *)val); val 1241 drivers/staging/rtl8188eu/hal/usb_halinit.c val8 |= *((u8 *)val) << 2; val 1246 drivers/staging/rtl8188eu/hal/usb_halinit.c hw_var_set_opmode(Adapter, variable, val); val 1249 drivers/staging/rtl8188eu/hal/usb_halinit.c hw_var_set_macaddr(Adapter, variable, val); val 1252 drivers/staging/rtl8188eu/hal/usb_halinit.c hw_var_set_bssid(Adapter, variable, val); val 1263 drivers/staging/rtl8188eu/hal/usb_halinit.c hal_set_brate_cfg(val, &BrateCfg); val 1290 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_TXPAUSE, *((u8 *)val)); val 1293 drivers/staging/rtl8188eu/hal/usb_halinit.c hw_var_set_bcn_func(Adapter, variable, val); val 1320 drivers/staging/rtl8188eu/hal/usb_halinit.c if (*((u8 *)val)) { val 1344 drivers/staging/rtl8188eu/hal/usb_halinit.c if (*((u8 *)val)) { /* under sitesurvey */ val 1378 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 type = *((u8 *)val); val 1406 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val)); val 1414 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_SLOT, val[0]); val 1434 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_R2T_SIFS, val[0]); /* SIFS_T2T_CCK (0x08) */ val 1435 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_R2T_SIFS + 1, val[1]); /* SIFS_R2T_CCK(0x08) */ val 1437 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */ val 1438 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_T2T_SIFS + 1, val[3]); /* SIFS_R2T_OFDM(0x0a) */ val 1443 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 bShortPreamble = *((bool *)val); val 1453 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_SECCFG, *((u8 *)val)); val 1456 drivers/staging/rtl8188eu/hal/usb_halinit.c if (val[0]) val 1462 drivers/staging/rtl8188eu/hal/usb_halinit.c if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) { val 1466 drivers/staging/rtl8188eu/hal/usb_halinit.c podmpriv->SupportAbility |= *((u32 *)val); val 1470 drivers/staging/rtl8188eu/hal/usb_halinit.c podmpriv->SupportAbility &= *((u32 *)val); val 1474 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 ucIndex = *((u8 *)val); val 1502 drivers/staging/rtl8188eu/hal/usb_halinit.c u32 *cam_val = (u32 *)val; val 1511 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]); val 1514 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]); val 1517 drivers/staging/rtl8188eu/hal/usb_halinit.c haldata->AcParam_BE = ((u32 *)(val))[0]; val 1518 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]); val 1521 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]); val 1525 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 acm_ctrl = *((u8 *)val); val 1555 drivers/staging/rtl8188eu/hal/usb_halinit.c MinSpacingToSet = *((u8 *)val); val 1586 drivers/staging/rtl8188eu/hal/usb_halinit.c FactorToSet = *((u8 *)val); val 1606 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 threshold = *((u8 *)val); val 1617 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 psmode = (*(u8 *)val); val 1628 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 mstatus = (*(u8 *)val); val 1636 drivers/staging/rtl8188eu/hal/usb_halinit.c u32 rx_gain = ((u32 *)(val))[0]; val 1651 drivers/staging/rtl8188eu/hal/usb_halinit.c u16 min_rpt_time = (*(u16 *)val); val 1658 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 Optimum_antenna = (*(u8 *)val); val 1670 drivers/staging/rtl8188eu/hal/usb_halinit.c haldata->EfuseUsedBytes = *((u16 *)val); val 1703 drivers/staging/rtl8188eu/hal/usb_halinit.c haldata->bMacPwrCtrlOn = *val; val 1708 drivers/staging/rtl8188eu/hal/usb_halinit.c u8 maxMacid = *val; val 1715 drivers/staging/rtl8188eu/hal/usb_halinit.c rtl8188e_set_FwMediaStatus_cmd(Adapter, (*(__le16 *)val)); val 1726 drivers/staging/rtl8188eu/hal/usb_halinit.c void rtw_hal_get_hwreg(struct adapter *Adapter, u8 variable, u8 *val) val 1730 drivers/staging/rtl8188eu/hal/usb_halinit.c *((u16 *)(val)) = Adapter->HalData->BasicRateSet; val 1733 drivers/staging/rtl8188eu/hal/usb_halinit.c val[0] = usb_read8(Adapter, REG_TXPAUSE); val 1737 drivers/staging/rtl8188eu/hal/usb_halinit.c val[0] = (BIT(0) & usb_read8(Adapter, REG_TDECTRL + 2)) ? true : false; val 1745 drivers/staging/rtl8188eu/hal/usb_halinit.c val[0] = true; val 1752 drivers/staging/rtl8188eu/hal/usb_halinit.c val[0] = false; val 1754 drivers/staging/rtl8188eu/hal/usb_halinit.c val[0] = true; val 1759 drivers/staging/rtl8188eu/hal/usb_halinit.c val[0] = Adapter->HalData->CurAntenna; val 1762 drivers/staging/rtl8188eu/hal/usb_halinit.c *((u16 *)(val)) = Adapter->HalData->EfuseUsedBytes; val 1765 drivers/staging/rtl8188eu/hal/usb_halinit.c *val = Adapter->HalData->bMacPwrCtrlOn; val 1768 drivers/staging/rtl8188eu/hal/usb_halinit.c *val = ((usb_read32(Adapter, REG_HGQ_INFORMATION) & 0x0000ff00) == 0) ? true : false; val 170 drivers/staging/rtl8188eu/include/hal_intf.h void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val); val 171 drivers/staging/rtl8188eu/include/hal_intf.h void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val); val 762 drivers/staging/rtl8188eu/include/ieee80211.h int rtw_get_bit_value_from_ieee_value(u8 val); val 50 drivers/staging/rtl8188eu/include/rtw_security.h u64 val; val 246 drivers/staging/rtl8188eu/include/rtw_security.h static inline u32 rotr(u32 val, int bits) val 248 drivers/staging/rtl8188eu/include/rtw_security.h return (val >> bits) | (val << (32 - bits)); val 46 drivers/staging/rtl8188eu/include/rtw_xmit.h dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val+1);\ val 60 drivers/staging/rtl8188eu/include/rtw_xmit.h dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ val 73 drivers/staging/rtl8188eu/include/rtw_xmit.h dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ val 51 drivers/staging/rtl8188eu/include/usb_ops_linux.h int usb_write8(struct adapter *adapter, u32 addr, u8 val); val 52 drivers/staging/rtl8188eu/include/usb_ops_linux.h int usb_write16(struct adapter *adapter, u32 addr, u16 val); val 53 drivers/staging/rtl8188eu/include/usb_ops_linux.h int usb_write32(struct adapter *adapter, u32 addr, u32 val); val 858 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c u16 val; val 904 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c for (i = 0, val = 0; i < MAX_CHANNEL_NUM; i++) { val 907 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c range->freq[val].i = pmlmeext->channel_set[i].ChannelNum; val 908 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000; val 909 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c range->freq[val].e = 1; val 910 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c val++; val 913 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c if (val == IW_MAX_FREQUENCIES) val 917 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c range->num_channels = val; val 918 drivers/staging/rtl8188eu/os_dep/ioctl_linux.c range->num_frequency = val; val 509 drivers/staging/rtl8188eu/os_dep/usb_ops_linux.c int usb_write8(struct adapter *adapter, u32 addr, u8 val) val 523 drivers/staging/rtl8188eu/os_dep/usb_ops_linux.c data = val; val 528 drivers/staging/rtl8188eu/os_dep/usb_ops_linux.c int usb_write16(struct adapter *adapter, u32 addr, u16 val) val 544 drivers/staging/rtl8188eu/os_dep/usb_ops_linux.c data = cpu_to_le32(val & 0x0000ffff); val 550 drivers/staging/rtl8188eu/os_dep/usb_ops_linux.c int usb_write32(struct adapter *adapter, u32 addr, u32 val) val 565 drivers/staging/rtl8188eu/os_dep/usb_ops_linux.c data = cpu_to_le32(val); val 83 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val) val 90 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c rtl92e_writew(dev, BSSIDR, *(u16 *)val); val 91 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2)); val 96 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c enum rt_op_mode OpMode = *((enum rt_op_mode *)(val)); val 128 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c Type = val[0]; val 145 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c priv->slot_time = val[0]; val 146 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c rtl92e_writeb(dev, SLOT_TIME, val[0]); val 154 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c priv->short_preamble = (bool)*val; val 163 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]); val 168 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c u8 pAcParam = *val; val 222 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c u8 pAcParam = *val; val 280 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c rtl92e_writeb(dev, SIFS, val[0]); val 281 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c rtl92e_writeb(dev, SIFS+1, val[0]); val 286 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c u8 Rf_Timing = *val; val 24 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.h void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val); val 13 drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c static void _rtl92e_gpio_write_bit(struct net_device *dev, int no, bool val) val 17 drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c if (val) val 65 drivers/staging/rtl8192e/rtl8192e/rtl_pm.c u32 val; val 78 drivers/staging/rtl8192e/rtl8192e/rtl_pm.c pci_read_config_dword(pdev, 0x40, &val); val 79 drivers/staging/rtl8192e/rtl8192e/rtl_pm.c if ((val & 0x0000ff00) != 0) val 80 drivers/staging/rtl8192e/rtl8192e/rtl_pm.c pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); val 311 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c u16 val; val 353 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c for (i = 0, val = 0; i < 14; i++) { val 355 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c range->freq[val].i = i + 1; val 356 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c range->freq[val].m = rtllib_wlan_frequencies[i] * val 358 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c range->freq[val].e = 1; val 359 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c val++; val 362 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c if (val == IW_MAX_FREQUENCIES) val 365 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c range->num_frequency = val; val 366 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c range->num_channels = val; val 1783 drivers/staging/rtl8192e/rtllib.h void (*SetHwRegHandler)(struct net_device *dev, u8 variable, u8 *val); val 121 drivers/staging/rtl8192e/rtllib_crypt_tkip.c static inline u16 RotR1(u16 val) val 123 drivers/staging/rtl8192e/rtllib_crypt_tkip.c return (val >> 1) | (val << 15); val 127 drivers/staging/rtl8192e/rtllib_crypt_tkip.c static inline u8 Lo8(u16 val) val 129 drivers/staging/rtl8192e/rtllib_crypt_tkip.c return val & 0xff; val 133 drivers/staging/rtl8192e/rtllib_crypt_tkip.c static inline u8 Hi8(u16 val) val 135 drivers/staging/rtl8192e/rtllib_crypt_tkip.c return val >> 8; val 139 drivers/staging/rtl8192e/rtllib_crypt_tkip.c static inline u16 Lo16(u32 val) val 141 drivers/staging/rtl8192e/rtllib_crypt_tkip.c return val & 0xffff; val 145 drivers/staging/rtl8192e/rtllib_crypt_tkip.c static inline u16 Hi16(u32 val) val 147 drivers/staging/rtl8192e/rtllib_crypt_tkip.c return val >> 16; val 131 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c static inline u16 RotR1(u16 val) val 133 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c return (val >> 1) | (val << 15); val 137 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c static inline u8 Lo8(u16 val) val 139 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c return val & 0xff; val 143 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c static inline u8 Hi8(u16 val) val 145 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c return val >> 8; val 149 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c static inline u16 Lo16(u32 val) val 151 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c return val & 0xffff; val 155 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c static inline u16 Hi16(u32 val) val 157 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c return val >> 16; val 253 drivers/staging/rtl8192u/ieee80211/ieee80211_module.c unsigned long val; val 254 drivers/staging/rtl8192u/ieee80211/ieee80211_module.c int err = kstrtoul_from_user(buffer, count, 0, &val); val 258 drivers/staging/rtl8192u/ieee80211/ieee80211_module.c ieee80211_debug_level = val; val 228 drivers/staging/rtl8192u/r8192U_wx.c u16 val; val 296 drivers/staging/rtl8192u/r8192U_wx.c for (i = 0, val = 0; i < 14; i++) { val 300 drivers/staging/rtl8192u/r8192U_wx.c range->freq[val].i = i + 1; val 301 drivers/staging/rtl8192u/r8192U_wx.c range->freq[val].m = ieee80211_wlan_frequencies[i] * 100000; val 302 drivers/staging/rtl8192u/r8192U_wx.c range->freq[val].e = 1; val 303 drivers/staging/rtl8192u/r8192U_wx.c val++; val 309 drivers/staging/rtl8192u/r8192U_wx.c if (val == IW_MAX_FREQUENCIES) val 312 drivers/staging/rtl8192u/r8192U_wx.c range->num_frequency = val; val 313 drivers/staging/rtl8192u/r8192U_wx.c range->num_channels = val; val 171 drivers/staging/rtl8712/rtl8712_cmd.c u32 val; val 176 drivers/staging/rtl8712/rtl8712_cmd.c memcpy(pcmd->rsp, (u8 *)&val, pcmd->rspsz); val 46 drivers/staging/rtl8712/rtl8712_io.c void r8712_write8(struct _adapter *adapter, u32 addr, u8 val) val 50 drivers/staging/rtl8712/rtl8712_io.c hdl->io_ops._write8(hdl, addr, val); val 53 drivers/staging/rtl8712/rtl8712_io.c void r8712_write16(struct _adapter *adapter, u32 addr, u16 val) val 57 drivers/staging/rtl8712/rtl8712_io.c hdl->io_ops._write16(hdl, addr, val); val 60 drivers/staging/rtl8712/rtl8712_io.c void r8712_write32(struct _adapter *adapter, u32 addr, u32 val) val 64 drivers/staging/rtl8712/rtl8712_io.c hdl->io_ops._write32(hdl, addr, val); val 254 drivers/staging/rtl8712/rtl871x_cmd.c int r8712_setrfreg_cmd(struct _adapter *padapter, u8 offset, u32 val) val 270 drivers/staging/rtl8712/rtl871x_cmd.c pwriterfparm->value = val; val 724 drivers/staging/rtl8712/rtl871x_cmd.h int r8712_setrfreg_cmd(struct _adapter *padapter, u8 offset, u32 val); val 87 drivers/staging/rtl8712/rtl871x_io.h void (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); val 88 drivers/staging/rtl8712/rtl871x_io.h void (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); val 89 drivers/staging/rtl8712/rtl871x_io.h void (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); val 104 drivers/staging/rtl8712/rtl871x_io.h /*volatile*/ u32 val; val 228 drivers/staging/rtl8712/rtl871x_io.h void r8712_write8(struct _adapter *adapter, u32 addr, u8 val); val 229 drivers/staging/rtl8712/rtl871x_io.h void r8712_write16(struct _adapter *adapter, u32 addr, u16 val); val 230 drivers/staging/rtl8712/rtl871x_io.h void r8712_write32(struct _adapter *adapter, u32 addr, u32 val); val 864 drivers/staging/rtl8712/rtl871x_ioctl_linux.c u16 val; val 899 drivers/staging/rtl8712/rtl871x_ioctl_linux.c for (i = 0, val = 0; i < 14; i++) { val 901 drivers/staging/rtl8712/rtl871x_ioctl_linux.c range->freq[val].i = i + 1; val 902 drivers/staging/rtl8712/rtl871x_ioctl_linux.c range->freq[val].m = ieee80211_wlan_frequencies[i] * 100000; val 903 drivers/staging/rtl8712/rtl871x_ioctl_linux.c range->freq[val].e = 1; val 904 drivers/staging/rtl8712/rtl871x_ioctl_linux.c val++; val 905 drivers/staging/rtl8712/rtl871x_ioctl_linux.c if (val == IW_MAX_FREQUENCIES) val 908 drivers/staging/rtl8712/rtl871x_ioctl_linux.c range->num_frequency = val; val 155 drivers/staging/rtl8712/rtl871x_mlme.h sint val) val 160 drivers/staging/rtl8712/rtl871x_mlme.h pmlmepriv->num_of_scanned = val; val 256 drivers/staging/rtl8712/rtl871x_security.c static void secmicputuint32(u8 *p, u32 val) val 262 drivers/staging/rtl8712/rtl871x_security.c *p++ = (u8) (val & 0xff); val 263 drivers/staging/rtl8712/rtl871x_security.c val >>= 8; val 595 drivers/staging/rtl8712/rtl871x_security.c pnl = (u16)(txpn.val); val 596 drivers/staging/rtl8712/rtl871x_security.c pnh = (u32)(txpn.val >> 16); val 678 drivers/staging/rtl8712/rtl871x_security.c pnl = (u16)(txpn.val); val 679 drivers/staging/rtl8712/rtl871x_security.c pnh = (u32)(txpn.val >> 16); val 39 drivers/staging/rtl8712/rtl871x_security.h u64 val; val 45 drivers/staging/rtl8712/rtl871x_xmit.h txpn.val = (txpn.val == 0xffffff) ? 0 : (txpn.val+1);\ val 61 drivers/staging/rtl8712/rtl871x_xmit.h txpn.val = txpn.val == 0xffffffffffffULL ? 0 : \ val 62 drivers/staging/rtl8712/rtl871x_xmit.h (txpn.val+1);\ val 75 drivers/staging/rtl8712/rtl871x_xmit.h txpn.val = txpn.val == 0xffffffffffffULL ? 0 : \ val 76 drivers/staging/rtl8712/rtl871x_xmit.h (txpn.val+1);\ val 85 drivers/staging/rtl8712/usb_ops.c static void usb_write8(struct intf_hdl *intfhdl, u32 addr, u8 val) val 100 drivers/staging/rtl8712/usb_ops.c data = cpu_to_le32((u32)val & 0x000000ff); val 105 drivers/staging/rtl8712/usb_ops.c static void usb_write16(struct intf_hdl *intfhdl, u32 addr, u16 val) val 120 drivers/staging/rtl8712/usb_ops.c data = cpu_to_le32((u32)val & 0x0000ffff); val 125 drivers/staging/rtl8712/usb_ops.c static void usb_write32(struct intf_hdl *intfhdl, u32 addr, u32 val) val 140 drivers/staging/rtl8712/usb_ops.c data = cpu_to_le32(val); val 56 drivers/staging/rtl8723bs/core/rtw_ieee80211.c int rtw_get_bit_value_from_ieee_value(u8 val) val 62 drivers/staging/rtl8723bs/core/rtw_ieee80211.c if (dot11_rate_table[i] == val) val 33 drivers/staging/rtl8723bs/core/rtw_io.c #define rtw_le16_to_cpu(val) val val 34 drivers/staging/rtl8723bs/core/rtw_io.c #define rtw_le32_to_cpu(val) val val 35 drivers/staging/rtl8723bs/core/rtw_io.c #define rtw_cpu_to_le16(val) val val 36 drivers/staging/rtl8723bs/core/rtw_io.c #define rtw_cpu_to_le32(val) val val 81 drivers/staging/rtl8723bs/core/rtw_io.c int _rtw_write8(struct adapter *adapter, u32 addr, u8 val) val 86 drivers/staging/rtl8723bs/core/rtw_io.c int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); val 91 drivers/staging/rtl8723bs/core/rtw_io.c ret = _write8(pintfhdl, addr, val); val 95 drivers/staging/rtl8723bs/core/rtw_io.c int _rtw_write16(struct adapter *adapter, u32 addr, u16 val) val 100 drivers/staging/rtl8723bs/core/rtw_io.c int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); val 105 drivers/staging/rtl8723bs/core/rtw_io.c ret = _write16(pintfhdl, addr, val); val 108 drivers/staging/rtl8723bs/core/rtw_io.c int _rtw_write32(struct adapter *adapter, u32 addr, u32 val) val 113 drivers/staging/rtl8723bs/core/rtw_io.c int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); val 118 drivers/staging/rtl8723bs/core/rtw_io.c ret = _write32(pintfhdl, addr, val); val 343 drivers/staging/rtl8723bs/core/rtw_mlme.c __le16 val; val 345 drivers/staging/rtl8723bs/core/rtw_mlme.c memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2); val 347 drivers/staging/rtl8723bs/core/rtw_mlme.c return le16_to_cpu(val); val 1211 drivers/staging/rtl8723bs/core/rtw_mlme.c psta->dot11txpn.val = psta->dot11txpn.val + 1; val 3100 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c unsigned short val; val 3146 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c val = *(unsigned short *)rtw_get_capability_from_ie(ie); val 3148 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_, (unsigned char *)&val, &(pattrib->pktlen)); val 330 drivers/staging/rtl8723bs/core/rtw_security.c static void secmicputuint32(u8 *p, u32 val) val 336 drivers/staging/rtl8723bs/core/rtw_security.c *p++ = (u8) (val & 0xff); val 337 drivers/staging/rtl8723bs/core/rtw_security.c val >>= 8; val 715 drivers/staging/rtl8723bs/core/rtw_security.c pnl = (u16)(dot11txpn.val); val 716 drivers/staging/rtl8723bs/core/rtw_security.c pnh = (u32)(dot11txpn.val>>16); val 835 drivers/staging/rtl8723bs/core/rtw_security.c pnl = (u16)(dot11txpn.val); val 836 drivers/staging/rtl8723bs/core/rtw_security.c pnh = (u32)(dot11txpn.val>>16); val 177 drivers/staging/rtl8723bs/core/rtw_wlan_util.c unsigned char val; val 181 drivers/staging/rtl8723bs/core/rtw_wlan_util.c val = pmlmeext->basicrate[i]; val 183 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if ((val != 0xff) && (val != 0xfe)) val 184 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if (rate == ratetbl_val_2wifirate(val)) val 461 drivers/staging/rtl8723bs/core/rtw_wlan_util.c __le16 val; val 462 drivers/staging/rtl8723bs/core/rtw_wlan_util.c memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2); val 464 drivers/staging/rtl8723bs/core/rtw_wlan_util.c return le16_to_cpu(val); val 562 drivers/staging/rtl8723bs/core/rtw_wlan_util.c unsigned int i, val, addr; val 571 drivers/staging/rtl8723bs/core/rtw_wlan_util.c val = (ctrl | (mac[0] << 16) | (mac[1] << 24)); val 574 drivers/staging/rtl8723bs/core/rtw_wlan_util.c val = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24)); val 578 drivers/staging/rtl8723bs/core/rtw_wlan_util.c val = (key[i] | (key[i+1] << 8) | (key[i+2] << 16) | (key[i+3] << 24)); val 582 drivers/staging/rtl8723bs/core/rtw_wlan_util.c cam_val[0] = val; val 2211 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if (psecpriv->dot11PrivacyAlgrthm != _NO_PRIVACY_ && psta->dot11txpn.val > 0) val 2212 drivers/staging/rtl8723bs/core/rtw_wlan_util.c psta->dot11txpn.val--; val 2233 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if (pwrpriv->wowlan_fw_iv > psta->dot11txpn.val) { val 2235 drivers/staging/rtl8723bs/core/rtw_wlan_util.c psta->dot11txpn.val = pwrpriv->wowlan_fw_iv + 2; val 2238 drivers/staging/rtl8723bs/core/rtw_wlan_util.c psta->dot11txpn.val += 2; val 2240 drivers/staging/rtl8723bs/core/rtw_wlan_util.c DBG_871X("%s: dot11txpn: 0x%016llx\n", __func__, psta->dot11txpn.val); val 11 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c #define HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(val) \ val 13 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, val); \ val 14 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c pCoexDm->psTdmaDuAdjType = val; \ val 787 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c u8 val = (u8)level; val 794 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x883, 0x3e, val); val 777 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c u8 *val = Array[i+6]; val 787 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c val val 1009 drivers/staging/rtl8723bs/hal/hal_com.c void SetHwReg(struct adapter *adapter, u8 variable, u8 *val) val 1034 drivers/staging/rtl8723bs/hal/hal_com.c if (val) { /* Enable default key related setting */ val 1045 drivers/staging/rtl8723bs/hal/hal_com.c odm->SupportAbility = *((u32 *)val); val 1048 drivers/staging/rtl8723bs/hal/hal_com.c if (*((u8 *)val) == true) { val 1057 drivers/staging/rtl8723bs/hal/hal_com.c if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) { val 1062 drivers/staging/rtl8723bs/hal/hal_com.c odm->SupportAbility |= *((u32 *)val); val 1070 drivers/staging/rtl8723bs/hal/hal_com.c odm->SupportAbility &= *((u32 *)val); val 1089 drivers/staging/rtl8723bs/hal/hal_com.c void GetHwReg(struct adapter *adapter, u8 variable, u8 *val) val 1096 drivers/staging/rtl8723bs/hal/hal_com.c *((u16 *)val) = hal_data->BasicRateSet; val 1099 drivers/staging/rtl8723bs/hal/hal_com.c *((u32 *)val) = odm->SupportAbility; val 1102 drivers/staging/rtl8723bs/hal/hal_com.c *((u8 *)val) = hal_data->rf_type; val 133 drivers/staging/rtl8723bs/hal/hal_intf.c void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val) val 136 drivers/staging/rtl8723bs/hal/hal_intf.c padapter->HalFunc.SetHwRegHandler(padapter, variable, val); val 139 drivers/staging/rtl8723bs/hal/hal_intf.c void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val) val 142 drivers/staging/rtl8723bs/hal/hal_intf.c padapter->HalFunc.GetHwRegHandler(padapter, variable, val); val 197 drivers/staging/rtl8723bs/hal/hal_intf.c u8 val = false; val 199 drivers/staging/rtl8723bs/hal/hal_intf.c val = padapter->HalFunc.check_ips_status(padapter); val 203 drivers/staging/rtl8723bs/hal/hal_intf.c return val; val 2238 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u8 val; val 2243 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val = rtw_read8(padapter, REG_LEDCFG2); val 2245 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */ val 2246 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_LEDCFG2, val); val 3317 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c static void hw_var_set_opmode(struct adapter *padapter, u8 variable, u8 *val) val 3320 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u8 mode = *((u8 *)val); val 3412 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c static void hw_var_set_macaddr(struct adapter *padapter, u8 variable, u8 *val) val 3420 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(GET_PRIMARY_ADAPTER(padapter), (reg_macid+idx), val[idx]); val 3423 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c static void hw_var_set_bssid(struct adapter *padapter, u8 variable, u8 *val) val 3431 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, (reg_bssid+idx), val[idx]); val 3434 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c static void hw_var_set_bcn_func(struct adapter *padapter, u8 variable, u8 *val) val 3440 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (*(u8 *)val) val 3455 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c static void hw_var_set_correct_tsf(struct adapter *padapter, u8 variable, u8 *val) val 3496 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c static void hw_var_set_mlme_disconnect(struct adapter *padapter, u8 variable, u8 *val) val 3514 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c static void hw_var_set_mlme_sitesurvey(struct adapter *padapter, u8 variable, u8 *val) val 3538 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (*((u8 *)val)) { val 3575 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c static void hw_var_set_mlme_join(struct adapter *padapter, u8 variable, u8 *val) val 3587 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c type = *(u8 *)val; val 3779 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val) val 3788 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val8 |= *val; val 3794 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val8 |= *val << 2; val 3799 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hw_var_set_opmode(padapter, variable, val); val 3803 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hw_var_set_macaddr(padapter, variable, val); val 3807 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hw_var_set_bssid(padapter, variable, val); val 3817 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c HalSetBrateCfg(padapter, val, &BrateCfg); val 3849 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_TXPAUSE, *val); val 3853 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hw_var_set_bcn_func(padapter, variable, val); val 3857 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hw_var_set_correct_tsf(padapter, variable, val); val 3864 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (*val) val 3873 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hw_var_set_mlme_disconnect(padapter, variable, val); val 3877 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hw_var_set_mlme_sitesurvey(padapter, variable, val); val 3879 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hal_btcoex_ScanNotify(padapter, *val?true:false); val 3883 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c hw_var_set_mlme_join(padapter, variable, val); val 3885 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c switch (*val) { val 3916 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write16(padapter, REG_BCN_INTERVAL, *((u16 *)val)); val 3920 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_SLOT, *val); val 3926 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */ val 3927 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_RESP_SIFS_CCK+1, val[1]); /* SIFS_R2T_CCK(0x08) */ val 3929 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /* SIFS_T2T_OFDM (0x0a) */ val 3930 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_RESP_SIFS_OFDM+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */ val 3936 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u8 bShortPreamble = *val; val 3949 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u8 ucIndex = *val; val 3982 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u32 *cam_val = (u32 *)val; val 3992 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val)); val 3996 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val)); val 4000 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->AcParam_BE = ((u32 *)(val))[0]; val 4001 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val)); val 4005 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val)); val 4010 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u8 ctrl = *((u8 *)val); val 4033 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u32 AMPDULen = (*((u8 *)val)); val 4036 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c AMPDULen = (0x2000 << (*((u8 *)val)))-1; val 4046 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u8 psmode = *val; val 4067 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtl8723b_set_FwJoinBssRpt_cmd(padapter, *val); val 4073 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u32 rx_gain = *(u32 *)val; val 4085 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->EfuseUsedPercentage = *val; val 4089 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->EfuseUsedBytes = *((u16 *)val); val 4094 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->EfuseHal.BTEfuseUsedPercentage = *val; val 4100 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val); val 4102 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c BTEfuseUsedBytes = *((u16 *)val); val 4147 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->bMacPwrCtrlOn = *val; val 4153 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u32 usNavUpper = *((u32 *)val); val 4169 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u16 mstatus_rpt = (*(u16 *)val); val 4208 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val32 = *(u32 *)val; val 4227 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val32 = *(u32 *)val; val 4245 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c SetHwReg(padapter, variable, val); val 4250 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c void GetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val) val 4258 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = rtw_read8(padapter, REG_TXPAUSE); val 4265 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = (BIT(0) & val8) ? true : false; val 4280 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = true; val 4285 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = false; val 4287 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = true; val 4293 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = pHalData->EfuseUsedPercentage; val 4297 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *((u16 *)val) = pHalData->EfuseUsedBytes; val 4302 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = pHalData->EfuseHal.BTEfuseUsedPercentage; val 4308 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes; val 4310 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *((u16 *)val) = BTEfuseUsedBytes; val 4315 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = pHalData->bMacPwrCtrlOn; val 4319 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = (val16 & BIT(10)) ? true:false; val 4323 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1) & BIT7; val 4326 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON); val 4327 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (*val == 0xEA) val 4328 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = 0; val 4331 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = rtw_read8(padapter, REG_SYS_CLKR); val 4335 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c GetHwReg(padapter, variable, val); val 1412 drivers/staging/rtl8723bs/hal/sdio_halinit.c static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val) val 1429 drivers/staging/rtl8723bs/hal/sdio_halinit.c u8 mstatus = (*(u8 *)val); val 1440 drivers/staging/rtl8723bs/hal/sdio_halinit.c val8 = *val; val 1454 drivers/staging/rtl8723bs/hal/sdio_halinit.c val8 = *val; val 1460 drivers/staging/rtl8723bs/hal/sdio_halinit.c poidparam = (struct wowlan_ioctl_param *)val; val 1677 drivers/staging/rtl8723bs/hal/sdio_halinit.c poidparam = (struct wowlan_ioctl_param *)val; val 1777 drivers/staging/rtl8723bs/hal/sdio_halinit.c SetHwReg8723B(padapter, variable, val); val 1786 drivers/staging/rtl8723bs/hal/sdio_halinit.c static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val) val 1790 drivers/staging/rtl8723bs/hal/sdio_halinit.c *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B); val 1796 drivers/staging/rtl8723bs/hal/sdio_halinit.c *((u16 *)val) = rtw_read16(padapter, 0x88); val 1800 drivers/staging/rtl8723bs/hal/sdio_halinit.c GetHwReg8723B(padapter, variable, val); val 176 drivers/staging/rtl8723bs/hal/sdio_ops.c u32 val; val 205 drivers/staging/rtl8723bs/hal/sdio_ops.c val = sd_read32(intfhdl, ftaddr, NULL); val 218 drivers/staging/rtl8723bs/hal/sdio_ops.c val = le32_to_cpu(le_tmp); val 222 drivers/staging/rtl8723bs/hal/sdio_ops.c return val; val 270 drivers/staging/rtl8723bs/hal/sdio_ops.c static s32 sdio_write8(struct intf_hdl *intfhdl, u32 addr, u8 val) val 276 drivers/staging/rtl8723bs/hal/sdio_ops.c sd_write8(intfhdl, ftaddr, val, &err); val 281 drivers/staging/rtl8723bs/hal/sdio_ops.c static s32 sdio_write16(struct intf_hdl *intfhdl, u32 addr, u16 val) val 287 drivers/staging/rtl8723bs/hal/sdio_ops.c le_tmp = cpu_to_le16(val); val 291 drivers/staging/rtl8723bs/hal/sdio_ops.c static s32 sdio_write32(struct intf_hdl *intfhdl, u32 addr, u32 val) val 313 drivers/staging/rtl8723bs/hal/sdio_ops.c le_tmp = cpu_to_le32(val); val 321 drivers/staging/rtl8723bs/hal/sdio_ops.c sd_write32(intfhdl, ftaddr, val, &err); val 323 drivers/staging/rtl8723bs/hal/sdio_ops.c le_tmp = cpu_to_le32(val); val 652 drivers/staging/rtl8723bs/hal/sdio_ops.c u8 val = 0; val 656 drivers/staging/rtl8723bs/hal/sdio_ops.c sd_cmd52_read(intfhdl, addr, 1, &val); val 658 drivers/staging/rtl8723bs/hal/sdio_ops.c return val; val 663 drivers/staging/rtl8723bs/hal/sdio_ops.c __le16 val = 0; val 667 drivers/staging/rtl8723bs/hal/sdio_ops.c sd_cmd52_read(intfhdl, addr, 2, (u8 *)&val); val 669 drivers/staging/rtl8723bs/hal/sdio_ops.c return le16_to_cpu(val); val 676 drivers/staging/rtl8723bs/hal/sdio_ops.c u32 val = 0; val 684 drivers/staging/rtl8723bs/hal/sdio_ops.c val = le32_to_cpu(le_tmp); val 686 drivers/staging/rtl8723bs/hal/sdio_ops.c val = sd_read32(intfhdl, addr, NULL); val 688 drivers/staging/rtl8723bs/hal/sdio_ops.c return val; val 240 drivers/staging/rtl8723bs/include/hal_com.h void SetHwReg(struct adapter *padapter, u8 variable, u8 *val); val 241 drivers/staging/rtl8723bs/include/hal_com.h void GetHwReg(struct adapter *padapter, u8 variable, u8 *val); val 216 drivers/staging/rtl8723bs/include/hal_intf.h void (*SetHwRegHandler)(struct adapter *padapter, u8 variable, u8 *val); val 217 drivers/staging/rtl8723bs/include/hal_intf.h void (*GetHwRegHandler)(struct adapter *padapter, u8 variable, u8 *val); val 235 drivers/staging/rtl8723bs/include/hal_intf.h u8 (*interface_ps_func)(struct adapter *padapter, enum HAL_INTF_PS_FUNC efunc_id, u8 *val); val 329 drivers/staging/rtl8723bs/include/hal_intf.h void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val); val 330 drivers/staging/rtl8723bs/include/hal_intf.h void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val); val 1163 drivers/staging/rtl8723bs/include/ieee80211.h int rtw_get_bit_value_from_ieee_value(u8 val); val 142 drivers/staging/rtl8723bs/include/osdep_service.h u32 val; val 144 drivers/staging/rtl8723bs/include/osdep_service.h val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2; val 146 drivers/staging/rtl8723bs/include/osdep_service.h return val; val 153 drivers/staging/rtl8723bs/include/osdep_service.h u32 val; val 155 drivers/staging/rtl8723bs/include/osdep_service.h val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3; val 157 drivers/staging/rtl8723bs/include/osdep_service.h return val; val 184 drivers/staging/rtl8723bs/include/osdep_service.h #define RTW_PUT_BE16(a, val) \ val 186 drivers/staging/rtl8723bs/include/osdep_service.h (a)[0] = ((u16) (val)) >> 8; \ val 187 drivers/staging/rtl8723bs/include/osdep_service.h (a)[1] = ((u16) (val)) & 0xff; \ val 191 drivers/staging/rtl8723bs/include/osdep_service.h #define RTW_PUT_LE16(a, val) \ val 193 drivers/staging/rtl8723bs/include/osdep_service.h (a)[1] = ((u16) (val)) >> 8; \ val 194 drivers/staging/rtl8723bs/include/osdep_service.h (a)[0] = ((u16) (val)) & 0xff; \ val 199 drivers/staging/rtl8723bs/include/osdep_service.h #define RTW_PUT_BE24(a, val) \ val 201 drivers/staging/rtl8723bs/include/osdep_service.h (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \ val 202 drivers/staging/rtl8723bs/include/osdep_service.h (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ val 203 drivers/staging/rtl8723bs/include/osdep_service.h (a)[2] = (u8) (((u32) (val)) & 0xff); \ val 208 drivers/staging/rtl8723bs/include/osdep_service.h #define RTW_PUT_BE32(a, val) \ val 210 drivers/staging/rtl8723bs/include/osdep_service.h (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ val 211 drivers/staging/rtl8723bs/include/osdep_service.h (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ val 212 drivers/staging/rtl8723bs/include/osdep_service.h (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ val 213 drivers/staging/rtl8723bs/include/osdep_service.h (a)[3] = (u8) (((u32) (val)) & 0xff); \ val 218 drivers/staging/rtl8723bs/include/osdep_service.h #define RTW_PUT_LE32(a, val) \ val 220 drivers/staging/rtl8723bs/include/osdep_service.h (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ val 221 drivers/staging/rtl8723bs/include/osdep_service.h (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ val 222 drivers/staging/rtl8723bs/include/osdep_service.h (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ val 223 drivers/staging/rtl8723bs/include/osdep_service.h (a)[0] = (u8) (((u32) (val)) & 0xff); \ val 230 drivers/staging/rtl8723bs/include/osdep_service.h #define RTW_PUT_BE64(a, val) \ val 232 drivers/staging/rtl8723bs/include/osdep_service.h (a)[0] = (u8) (((u64) (val)) >> 56); \ val 233 drivers/staging/rtl8723bs/include/osdep_service.h (a)[1] = (u8) (((u64) (val)) >> 48); \ val 234 drivers/staging/rtl8723bs/include/osdep_service.h (a)[2] = (u8) (((u64) (val)) >> 40); \ val 235 drivers/staging/rtl8723bs/include/osdep_service.h (a)[3] = (u8) (((u64) (val)) >> 32); \ val 236 drivers/staging/rtl8723bs/include/osdep_service.h (a)[4] = (u8) (((u64) (val)) >> 24); \ val 237 drivers/staging/rtl8723bs/include/osdep_service.h (a)[5] = (u8) (((u64) (val)) >> 16); \ val 238 drivers/staging/rtl8723bs/include/osdep_service.h (a)[6] = (u8) (((u64) (val)) >> 8); \ val 239 drivers/staging/rtl8723bs/include/osdep_service.h (a)[7] = (u8) (((u64) (val)) & 0xff); \ val 258 drivers/staging/rtl8723bs/include/rtl8723b_hal.h void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val); val 259 drivers/staging/rtl8723bs/include/rtl8723b_hal.h void GetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val); val 84 drivers/staging/rtl8723bs/include/rtw_io.h int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); val 85 drivers/staging/rtl8723bs/include/rtw_io.h int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); val 86 drivers/staging/rtl8723bs/include/rtw_io.h int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); val 89 drivers/staging/rtl8723bs/include/rtw_io.h int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); val 90 drivers/staging/rtl8723bs/include/rtw_io.h int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); val 91 drivers/staging/rtl8723bs/include/rtw_io.h int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); val 114 drivers/staging/rtl8723bs/include/rtw_io.h volatile u32 val; val 288 drivers/staging/rtl8723bs/include/rtw_io.h extern int _rtw_write8(struct adapter *adapter, u32 addr, u8 val); val 289 drivers/staging/rtl8723bs/include/rtw_io.h extern int _rtw_write16(struct adapter *adapter, u32 addr, u16 val); val 290 drivers/staging/rtl8723bs/include/rtw_io.h extern int _rtw_write32(struct adapter *adapter, u32 addr, u32 val); val 300 drivers/staging/rtl8723bs/include/rtw_io.h #define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val)) val 301 drivers/staging/rtl8723bs/include/rtw_io.h #define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val)) val 302 drivers/staging/rtl8723bs/include/rtw_io.h #define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val)) val 314 drivers/staging/rtl8723bs/include/rtw_io.h extern void ioreq_write8(struct adapter *adapter, u32 addr, u8 val); val 315 drivers/staging/rtl8723bs/include/rtw_io.h extern void ioreq_write16(struct adapter *adapter, u32 addr, u16 val); val 316 drivers/staging/rtl8723bs/include/rtw_io.h extern void ioreq_write32(struct adapter *adapter, u32 addr, u32 val); val 329 drivers/staging/rtl8723bs/include/rtw_io.h extern void async_write8(struct adapter *adapter, u32 addr, u8 val, val 331 drivers/staging/rtl8723bs/include/rtw_io.h extern void async_write16(struct adapter *adapter, u32 addr, u16 val, val 333 drivers/staging/rtl8723bs/include/rtw_io.h extern void async_write32(struct adapter *adapter, u32 addr, u32 val, val 555 drivers/staging/rtl8723bs/include/rtw_mlme.h static inline void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val) val 558 drivers/staging/rtl8723bs/include/rtw_mlme.h pmlmepriv->num_of_scanned = val; val 432 drivers/staging/rtl8723bs/include/rtw_mp.h void _write_rfreg(struct adapter *padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); val 435 drivers/staging/rtl8723bs/include/rtw_mp.h void write_macreg(struct adapter *padapter, u32 addr, u32 val, u32 sz); val 437 drivers/staging/rtl8723bs/include/rtw_mp.h void write_bbreg(struct adapter *padapter, u32 addr, u32 bitmask, u32 val); val 439 drivers/staging/rtl8723bs/include/rtw_mp.h void write_rfreg(struct adapter *padapter, u8 rfpath, u32 addr, u32 val); val 55 drivers/staging/rtl8723bs/include/rtw_security.h u64 val; val 300 drivers/staging/rtl8723bs/include/rtw_security.h static inline u32 rotr(u32 val, int bits) val 302 drivers/staging/rtl8723bs/include/rtw_security.h return (val >> bits) | (val << (32 - bits)); val 342 drivers/staging/rtl8723bs/include/rtw_security.h #define WPA_PUT_LE16(a, val) \ val 344 drivers/staging/rtl8723bs/include/rtw_security.h (a)[1] = ((u16) (val)) >> 8; \ val 345 drivers/staging/rtl8723bs/include/rtw_security.h (a)[0] = ((u16) (val)) & 0xff; \ val 348 drivers/staging/rtl8723bs/include/rtw_security.h #define WPA_PUT_BE32(a, val) \ val 350 drivers/staging/rtl8723bs/include/rtw_security.h (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ val 351 drivers/staging/rtl8723bs/include/rtw_security.h (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ val 352 drivers/staging/rtl8723bs/include/rtw_security.h (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ val 353 drivers/staging/rtl8723bs/include/rtw_security.h (a)[3] = (u8) (((u32) (val)) & 0xff); \ val 356 drivers/staging/rtl8723bs/include/rtw_security.h #define WPA_PUT_BE64(a, val) \ val 358 drivers/staging/rtl8723bs/include/rtw_security.h (a)[0] = (u8) (((u64) (val)) >> 56); \ val 359 drivers/staging/rtl8723bs/include/rtw_security.h (a)[1] = (u8) (((u64) (val)) >> 48); \ val 360 drivers/staging/rtl8723bs/include/rtw_security.h (a)[2] = (u8) (((u64) (val)) >> 40); \ val 361 drivers/staging/rtl8723bs/include/rtw_security.h (a)[3] = (u8) (((u64) (val)) >> 32); \ val 362 drivers/staging/rtl8723bs/include/rtw_security.h (a)[4] = (u8) (((u64) (val)) >> 24); \ val 363 drivers/staging/rtl8723bs/include/rtw_security.h (a)[5] = (u8) (((u64) (val)) >> 16); \ val 364 drivers/staging/rtl8723bs/include/rtw_security.h (a)[6] = (u8) (((u64) (val)) >> 8); \ val 365 drivers/staging/rtl8723bs/include/rtw_security.h (a)[7] = (u8) (((u64) (val)) & 0xff); \ val 48 drivers/staging/rtl8723bs/include/rtw_xmit.h dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0: (dot11txpn.val+1);\ val 62 drivers/staging/rtl8723bs/include/rtw_xmit.h dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\ val 75 drivers/staging/rtl8723bs/include/rtw_xmit.h dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\ val 23 drivers/staging/rtl8723bs/include/sdio_ops.h s32 _sdio_write32(struct adapter *padapter, u32 addr, u32 val); val 1029 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c u16 val; val 1076 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c for (i = 0, val = 0; i < MAX_CHANNEL_NUM; i++) { val 1080 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c range->freq[val].i = pmlmeext->channel_set[i].ChannelNum; val 1081 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000; val 1082 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c range->freq[val].e = 1; val 1083 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c val++; val 1086 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if (val == IW_MAX_FREQUENCIES) val 1090 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c range->num_channels = val; val 1091 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c range->num_frequency = val; val 100 drivers/staging/rts5208/ms.c u8 val, err_code = 0; val 152 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); val 156 drivers/staging/rts5208/ms.c if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) val 193 drivers/staging/rts5208/ms.c u8 val = 0; val 195 drivers/staging/rts5208/ms.c rtsx_read_register(chip, MS_TRANS_CFG, &val); val 196 drivers/staging/rts5208/ms.c dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val); val 201 drivers/staging/rts5208/ms.c if (val & MS_CRC16_ERR) { val 206 drivers/staging/rts5208/ms.c if (CHK_MSPRO(ms_card) && !(val & 0x80)) { val 207 drivers/staging/rts5208/ms.c if (val & (MS_INT_ERR | MS_INT_CMDNK)) { val 214 drivers/staging/rts5208/ms.c if (val & MS_RDY_TIMEOUT) { val 260 drivers/staging/rts5208/ms.c u8 val = 0; val 262 drivers/staging/rts5208/ms.c rtsx_read_register(chip, MS_TRANS_CFG, &val); val 266 drivers/staging/rts5208/ms.c if (val & MS_CRC16_ERR) { val 271 drivers/staging/rts5208/ms.c if (CHK_MSPRO(ms_card) && !(val & 0x80)) { val 272 drivers/staging/rts5208/ms.c if (val & (MS_INT_ERR | MS_INT_CMDNK)) { val 279 drivers/staging/rts5208/ms.c if (val & MS_RDY_TIMEOUT) { val 591 drivers/staging/rts5208/ms.c u8 val; val 606 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val); val 610 drivers/staging/rts5208/ms.c dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val); val 611 drivers/staging/rts5208/ms.c if (val != 0x01) { val 612 drivers/staging/rts5208/ms.c if (val != 0x02) val 618 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val); val 622 drivers/staging/rts5208/ms.c dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val); val 623 drivers/staging/rts5208/ms.c if (val != 0) { val 628 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val); val 632 drivers/staging/rts5208/ms.c dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val); val 633 drivers/staging/rts5208/ms.c if (val == 0) { val 634 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, PPBUF_BASE2, &val); val 638 drivers/staging/rts5208/ms.c if (val & WRT_PRTCT) val 643 drivers/staging/rts5208/ms.c } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) { val 652 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val); val 656 drivers/staging/rts5208/ms.c dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val); val 657 drivers/staging/rts5208/ms.c if (val == 0) { val 659 drivers/staging/rts5208/ms.c } else if (val == 7) { val 675 drivers/staging/rts5208/ms.c u8 val; val 687 drivers/staging/rts5208/ms.c NO_WAIT_INT, &val, 1); val 699 drivers/staging/rts5208/ms.c } while (!(val & INT_REG_CED)); val 702 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 709 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 710 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) val 877 drivers/staging/rts5208/ms.c u8 val, *buf, class_code, device_type, sub_class, data[16]; val 924 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); val 929 drivers/staging/rts5208/ms.c if (!(val & MS_INT_BREQ)) { val 948 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); val 954 drivers/staging/rts5208/ms.c if ((val & MS_INT_CED) || !(val & MS_INT_BREQ)) val 1233 drivers/staging/rts5208/ms.c u8 val[2]; val 1239 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2); val 1243 drivers/staging/rts5208/ms.c if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) { val 1256 drivers/staging/rts5208/ms.c u8 val, data[10]; val 1296 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 1300 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 1304 drivers/staging/rts5208/ms.c if (val & INT_REG_CED) { val 1305 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 1337 drivers/staging/rts5208/ms.c u8 val, data[16]; val 1371 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 1375 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 1379 drivers/staging/rts5208/ms.c if (val & INT_REG_CED) { val 1380 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 1393 drivers/staging/rts5208/ms.c u8 val, data[6]; val 1420 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 1424 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 1429 drivers/staging/rts5208/ms.c if (val & INT_REG_CED) { val 1430 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 1431 drivers/staging/rts5208/ms.c if (!(val & INT_REG_BREQ)) { val 1440 drivers/staging/rts5208/ms.c if (!(val & INT_REG_BREQ)) { val 1462 drivers/staging/rts5208/ms.c u8 val, data[8], extra[MS_EXTRA_SIZE]; val 1497 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 1501 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 1506 drivers/staging/rts5208/ms.c if (val & INT_REG_CED) { val 1507 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 1520 drivers/staging/rts5208/ms.c u8 val, data[6]; val 1550 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 1554 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 1565 drivers/staging/rts5208/ms.c if (val & INT_REG_CED) { val 1566 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 1628 drivers/staging/rts5208/ms.c u8 extra[MS_EXTRA_SIZE], val, i, j, data[16]; val 1643 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, PPBUF_BASE2, &val); val 1647 drivers/staging/rts5208/ms.c if (val & BUF_FULL) { val 1652 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 1656 drivers/staging/rts5208/ms.c if (!(val & INT_REG_CED)) { val 1701 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 1705 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 1710 drivers/staging/rts5208/ms.c if (val & INT_REG_CED) { val 1711 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 1764 drivers/staging/rts5208/ms.c if (!(val & INT_REG_BREQ)) { val 1808 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 1812 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 1817 drivers/staging/rts5208/ms.c if (val & INT_REG_CED) { val 1818 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 1857 drivers/staging/rts5208/ms.c NO_WAIT_INT, &val, 1); val 1861 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 1866 drivers/staging/rts5208/ms.c if (val & INT_REG_CED) { val 1867 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 1884 drivers/staging/rts5208/ms.c u8 val, extra[MS_EXTRA_SIZE], j, *ptr; val 1903 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, PPBUF_BASE2, &val); val 1907 drivers/staging/rts5208/ms.c if (val & WRT_PRTCT) val 2617 drivers/staging/rts5208/ms.c u8 val, trans_mode, rw_tpc, rw_cmd; val 2661 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); val 2671 drivers/staging/rts5208/ms.c !(val & MS_INT_BREQ) || val 2675 drivers/staging/rts5208/ms.c if (val & MS_INT_BREQ) { val 2715 drivers/staging/rts5208/ms.c rtsx_read_register(chip, MS_TRANS_CFG, &val); val 2725 drivers/staging/rts5208/ms.c if (val & MS_INT_BREQ) val 2728 drivers/staging/rts5208/ms.c if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { val 2961 drivers/staging/rts5208/ms.c u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6]; val 3014 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 3018 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 3022 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 3023 drivers/staging/rts5208/ms.c if (val & INT_REG_BREQ) { val 3046 drivers/staging/rts5208/ms.c if (!(val & INT_REG_BREQ)) { val 3053 drivers/staging/rts5208/ms.c if (!(val & INT_REG_CED)) { val 3060 drivers/staging/rts5208/ms.c &val, 1); val 3064 drivers/staging/rts5208/ms.c if (!(val & INT_REG_CED)) { val 3103 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); val 3109 drivers/staging/rts5208/ms.c if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { val 3130 drivers/staging/rts5208/ms.c u8 page_addr, val, data[16]; val 3214 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 3227 drivers/staging/rts5208/ms.c if (val & INT_REG_CMDNK) { val 3231 drivers/staging/rts5208/ms.c if (val & INT_REG_ERR) { val 3235 drivers/staging/rts5208/ms.c if (!(val & INT_REG_BREQ)) { val 3274 drivers/staging/rts5208/ms.c retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); val 3279 drivers/staging/rts5208/ms.c if (!(val & INT_REG_CED)) { val 3285 drivers/staging/rts5208/ms.c if (!(val & INT_REG_CED)) { val 3293 drivers/staging/rts5208/ms.c NO_WAIT_INT, &val, 1); val 3300 drivers/staging/rts5208/ms.c if (!(val & INT_REG_CED)) { val 3683 drivers/staging/rts5208/ms.c u8 val; val 3693 drivers/staging/rts5208/ms.c val = *rtsx_get_cmd_data(chip); val 3694 drivers/staging/rts5208/ms.c if (val & MS_INT_ERR) val 3705 drivers/staging/rts5208/ms.c u8 val; val 3707 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, MS_TRANSFER, &val); val 3710 drivers/staging/rts5208/ms.c if (val & MS_TRANSFER_ERR) val 3713 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); val 3717 drivers/staging/rts5208/ms.c if (val & (MS_INT_ERR | MS_INT_CMDNK)) val 3726 drivers/staging/rts5208/ms.c u8 val; val 3728 drivers/staging/rts5208/ms.c retval = rtsx_read_register(chip, MS_TRANSFER, &val); val 3731 drivers/staging/rts5208/ms.c if (val & MS_TRANSFER_ERR) val 55 drivers/staging/rts5208/rtsx.h #define rtsx_read_config_byte(chip, where, val) \ val 56 drivers/staging/rts5208/rtsx.h pci_read_config_byte((chip)->rtsx->pci, where, val) val 58 drivers/staging/rts5208/rtsx.h #define rtsx_write_config_byte(chip, where, val) \ val 59 drivers/staging/rts5208/rtsx.h pci_write_config_byte((chip)->rtsx->pci, where, val) val 921 drivers/staging/rts5208/rtsx_card.c u8 mask, val; val 925 drivers/staging/rts5208/rtsx_card.c val = MS_POWER_OFF; val 928 drivers/staging/rts5208/rtsx_card.c val = SD_POWER_OFF; val 931 drivers/staging/rts5208/rtsx_card.c retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val); val 639 drivers/staging/rts5208/rtsx_chip.c u8 val = 0; val 644 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, CLK_SEL, &val); val 647 drivers/staging/rts5208/rtsx_chip.c chip->asic_code = val == 0 ? 1 : 0; val 660 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, 0xFE80, &val); val 663 drivers/staging/rts5208/rtsx_chip.c chip->ic_version = val; val 667 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, PDINFO, &val); val 670 drivers/staging/rts5208/rtsx_chip.c dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); val 671 drivers/staging/rts5208/rtsx_chip.c chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; val 673 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, 0xFE50, &val); val 676 drivers/staging/rts5208/rtsx_chip.c chip->hw_bypass_sd = val & 0x01 ? 1 : 0; val 678 drivers/staging/rts5208/rtsx_chip.c rtsx_read_config_byte(chip, 0x0E, &val); val 679 drivers/staging/rts5208/rtsx_chip.c if (val & 0x80) val 685 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); val 688 drivers/staging/rts5208/rtsx_chip.c chip->auto_delink_en = val & 0x80 ? 1 : 0; val 697 drivers/staging/rts5208/rtsx_chip.c u8 val = 0, max_func; val 703 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, CLK_SEL, &val); val 706 drivers/staging/rts5208/rtsx_chip.c chip->asic_code = val == 0 ? 1 : 0; val 711 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, PDINFO, &val); val 714 drivers/staging/rts5208/rtsx_chip.c dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); val 715 drivers/staging/rts5208/rtsx_chip.c chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; val 717 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val); val 720 drivers/staging/rts5208/rtsx_chip.c dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val); val 721 drivers/staging/rts5208/rtsx_chip.c chip->baro_pkg = val & 0x04 ? QFN : LQFP; val 723 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, 0xFE5A, &val); val 726 drivers/staging/rts5208/rtsx_chip.c chip->hw_bypass_sd = val & 0x10 ? 1 : 0; val 740 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); val 743 drivers/staging/rts5208/rtsx_chip.c chip->auto_delink_en = val & 0x80 ? 1 : 0; val 981 drivers/staging/rts5208/rtsx_chip.c u8 val; val 987 drivers/staging/rts5208/rtsx_chip.c rtsx_read_register(chip, 0xFD30, &val); val 988 drivers/staging/rts5208/rtsx_chip.c if (val & 0x02) { val 1001 drivers/staging/rts5208/rtsx_chip.c u32 val; val 1007 drivers/staging/rts5208/rtsx_chip.c rtsx_read_cfg_dw(chip, 1, 0x04, &val); val 1008 drivers/staging/rts5208/rtsx_chip.c if (val & 0x07) val 1136 drivers/staging/rts5208/rtsx_chip.c u8 val; val 1152 drivers/staging/rts5208/rtsx_chip.c val = 0x02; val 1154 drivers/staging/rts5208/rtsx_chip.c val = 0x0A; val 1156 drivers/staging/rts5208/rtsx_chip.c rtsx_write_register(chip, CHANGE_LINK_STATE, val, val); val 1213 drivers/staging/rts5208/rtsx_chip.c u8 val; val 1215 drivers/staging/rts5208/rtsx_chip.c rtsx_read_config_byte(chip, 0, &val); val 1285 drivers/staging/rts5208/rtsx_chip.c u8 val; val 1287 drivers/staging/rts5208/rtsx_chip.c rtsx_read_register(chip, addr, &val); val 1288 drivers/staging/rts5208/rtsx_chip.c dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val); val 1300 drivers/staging/rts5208/rtsx_chip.c u32 val = 3 << 30; val 1302 drivers/staging/rts5208/rtsx_chip.c val |= (u32)(addr & 0x3FFF) << 16; val 1303 drivers/staging/rts5208/rtsx_chip.c val |= (u32)mask << 8; val 1304 drivers/staging/rts5208/rtsx_chip.c val |= (u32)data; val 1306 drivers/staging/rts5208/rtsx_chip.c rtsx_writel(chip, RTSX_HAIMR, val); val 1309 drivers/staging/rts5208/rtsx_chip.c val = rtsx_readl(chip, RTSX_HAIMR); val 1310 drivers/staging/rts5208/rtsx_chip.c if ((val & BIT(31)) == 0) { val 1311 drivers/staging/rts5208/rtsx_chip.c if (data != (u8)val) val 1323 drivers/staging/rts5208/rtsx_chip.c u32 val = 2 << 30; val 1329 drivers/staging/rts5208/rtsx_chip.c val |= (u32)(addr & 0x3FFF) << 16; val 1331 drivers/staging/rts5208/rtsx_chip.c rtsx_writel(chip, RTSX_HAIMR, val); val 1334 drivers/staging/rts5208/rtsx_chip.c val = rtsx_readl(chip, RTSX_HAIMR); val 1335 drivers/staging/rts5208/rtsx_chip.c if ((val & BIT(31)) == 0) val 1343 drivers/staging/rts5208/rtsx_chip.c *data = (u8)(val & 0xFF); val 1349 drivers/staging/rts5208/rtsx_chip.c u32 val) val 1359 drivers/staging/rts5208/rtsx_chip.c (u8)(val & mask & 0xFF)); val 1365 drivers/staging/rts5208/rtsx_chip.c val >>= 8; val 1395 drivers/staging/rts5208/rtsx_chip.c int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val) val 1428 drivers/staging/rts5208/rtsx_chip.c if (val) val 1429 drivers/staging/rts5208/rtsx_chip.c *val = data; val 1540 drivers/staging/rts5208/rtsx_chip.c int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) val 1547 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val); val 1550 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); val 1576 drivers/staging/rts5208/rtsx_chip.c int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) val 1613 drivers/staging/rts5208/rtsx_chip.c if (val) val 1614 drivers/staging/rts5208/rtsx_chip.c *val = data; val 1619 drivers/staging/rts5208/rtsx_chip.c int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) val 1644 drivers/staging/rts5208/rtsx_chip.c if (val) val 1645 drivers/staging/rts5208/rtsx_chip.c *val = data; val 1650 drivers/staging/rts5208/rtsx_chip.c int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) val 1657 drivers/staging/rts5208/rtsx_chip.c if (val & (u8)(1 << i)) val 1986 drivers/staging/rts5208/rtsx_chip.c u16 val = chip->aspm_l0s_l1_en | 0x0100; val 1989 drivers/staging/rts5208/rtsx_chip.c 0xC0, 0xFFF, val); val 2139 drivers/staging/rts5208/rtsx_chip.c u8 mask = 0, val = 0; val 2153 drivers/staging/rts5208/rtsx_chip.c val = mask; val 2154 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_write_register(chip, FPDCTL, mask, val); val 963 drivers/staging/rts5208/rtsx_chip.h u8 func_no, u16 addr, u32 mask, u32 val); val 964 drivers/staging/rts5208/rtsx_chip.h int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val); val 969 drivers/staging/rts5208/rtsx_chip.h int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val); val 970 drivers/staging/rts5208/rtsx_chip.h int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val); val 971 drivers/staging/rts5208/rtsx_chip.h int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val); val 972 drivers/staging/rts5208/rtsx_chip.h int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val); val 1337 drivers/staging/rts5208/rtsx_scsi.c u32 val; val 1350 drivers/staging/rts5208/rtsx_scsi.c val = rtsx_readl(chip, addr); val 1351 drivers/staging/rts5208/rtsx_scsi.c dev_dbg(rtsx_dev(chip), "Host register (0x%x): 0x%x\n", addr, val); val 1353 drivers/staging/rts5208/rtsx_scsi.c buf[0] = (u8)(val >> 24); val 1354 drivers/staging/rts5208/rtsx_scsi.c buf[1] = (u8)(val >> 16); val 1355 drivers/staging/rts5208/rtsx_scsi.c buf[2] = (u8)(val >> 8); val 1356 drivers/staging/rts5208/rtsx_scsi.c buf[3] = (u8)val; val 1368 drivers/staging/rts5208/rtsx_scsi.c u32 val; val 1385 drivers/staging/rts5208/rtsx_scsi.c val = ((u32)buf[0] << 24) | ((u32)buf[1] << 16) | ((u32)buf[2] val 1388 drivers/staging/rts5208/rtsx_scsi.c rtsx_writel(chip, addr, val); val 1799 drivers/staging/rts5208/rtsx_scsi.c u16 val; val 1829 drivers/staging/rts5208/rtsx_scsi.c retval = rtsx_read_phy_register(chip, addr + i, &val); val 1838 drivers/staging/rts5208/rtsx_scsi.c buf[2 * i] = (u8)(val >> 8); val 1839 drivers/staging/rts5208/rtsx_scsi.c buf[2 * i + 1] = (u8)val; val 1858 drivers/staging/rts5208/rtsx_scsi.c u16 val; val 1894 drivers/staging/rts5208/rtsx_scsi.c val = ((u16)buf[2 * i] << 8) | buf[2 * i + 1]; val 1895 drivers/staging/rts5208/rtsx_scsi.c retval = rtsx_write_phy_register(chip, addr + i, val); val 2102 drivers/staging/rts5208/rtsx_scsi.c u16 val; val 2132 drivers/staging/rts5208/rtsx_scsi.c retval = rtsx_read_phy_register(chip, 0x08, &val); val 2197 drivers/staging/rts5208/rtsx_scsi.c retval = rtsx_write_phy_register(chip, 0x08, val); val 199 drivers/staging/rts5208/rtsx_transport.c u32 val = 0; val 201 drivers/staging/rts5208/rtsx_transport.c val |= (u32)(cmd_type & 0x03) << 30; val 202 drivers/staging/rts5208/rtsx_transport.c val |= (u32)(reg_addr & 0x3FFF) << 16; val 203 drivers/staging/rts5208/rtsx_transport.c val |= (u32)mask << 8; val 204 drivers/staging/rts5208/rtsx_transport.c val |= (u32)data; val 208 drivers/staging/rts5208/rtsx_transport.c cb[(chip->ci)++] = cpu_to_le32(val); val 215 drivers/staging/rts5208/rtsx_transport.c u32 val = BIT(31); val 219 drivers/staging/rts5208/rtsx_transport.c val |= (u32)(chip->ci * 4) & 0x00FFFFFF; val 221 drivers/staging/rts5208/rtsx_transport.c val |= 0x40000000; val 222 drivers/staging/rts5208/rtsx_transport.c rtsx_writel(chip, RTSX_HCBCTLR, val); val 229 drivers/staging/rts5208/rtsx_transport.c u32 val = BIT(31); val 252 drivers/staging/rts5208/rtsx_transport.c val |= (u32)(chip->ci * 4) & 0x00FFFFFF; val 254 drivers/staging/rts5208/rtsx_transport.c val |= 0x40000000; val 255 drivers/staging/rts5208/rtsx_transport.c rtsx_writel(chip, RTSX_HCBCTLR, val); val 291 drivers/staging/rts5208/rtsx_transport.c u64 val = 0; val 303 drivers/staging/rts5208/rtsx_transport.c val = ((u64)addr << 32) | ((u64)temp_len << 12) | temp_opt; val 306 drivers/staging/rts5208/rtsx_transport.c sgb[(chip->sgi)++] = cpu_to_le64(val); val 327 drivers/staging/rts5208/rtsx_transport.c u32 val = TRIG_DMA; val 410 drivers/staging/rts5208/rtsx_transport.c val |= (u32)(dir & 0x01) << 29; val 411 drivers/staging/rts5208/rtsx_transport.c val |= ADMA_MODE; val 418 drivers/staging/rts5208/rtsx_transport.c rtsx_writel(chip, RTSX_HDBCTLR, val); val 526 drivers/staging/rts5208/rtsx_transport.c u32 val = TRIG_DMA; val 554 drivers/staging/rts5208/rtsx_transport.c val |= (u32)(dir & 0x01) << 29; val 555 drivers/staging/rts5208/rtsx_transport.c val |= ADMA_MODE; val 562 drivers/staging/rts5208/rtsx_transport.c rtsx_writel(chip, RTSX_HDBCTLR, val); val 635 drivers/staging/rts5208/rtsx_transport.c u32 val = BIT(31); val 661 drivers/staging/rts5208/rtsx_transport.c val |= (u32)(dir & 0x01) << 29; val 662 drivers/staging/rts5208/rtsx_transport.c val |= (u32)(len & 0x00FFFFFF); val 675 drivers/staging/rts5208/rtsx_transport.c rtsx_writel(chip, RTSX_HDBCTLR, val); val 167 drivers/staging/rts5208/sd.c u8 val; val 169 drivers/staging/rts5208/sd.c rtsx_read_register(chip, REG_SD_STAT1, &val); val 170 drivers/staging/rts5208/sd.c dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val); val 172 drivers/staging/rts5208/sd.c rtsx_read_register(chip, REG_SD_CFG3, &val); val 173 drivers/staging/rts5208/sd.c dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val); val 501 drivers/staging/rts5208/sd.c u8 val = 0; val 504 drivers/staging/rts5208/sd.c val |= 0x10; val 509 drivers/staging/rts5208/sd.c if (val & 0x10) val 510 drivers/staging/rts5208/sd.c val |= 0x04; val 512 drivers/staging/rts5208/sd.c val |= 0x08; val 515 drivers/staging/rts5208/sd.c if (val & 0x10) val 516 drivers/staging/rts5208/sd.c val |= 0x04; val 518 drivers/staging/rts5208/sd.c val |= 0x08; val 522 drivers/staging/rts5208/sd.c if (val & 0x10) val 523 drivers/staging/rts5208/sd.c val |= 0x04; val 525 drivers/staging/rts5208/sd.c val |= 0x08; val 528 drivers/staging/rts5208/sd.c retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val); val 580 drivers/staging/rts5208/sd.c u8 mask = 0, val = 0; val 584 drivers/staging/rts5208/sd.c val = 0x00; val 586 drivers/staging/rts5208/sd.c val = 0x40; val 588 drivers/staging/rts5208/sd.c val = 0x20; val 590 drivers/staging/rts5208/sd.c retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val); val 819 drivers/staging/rts5208/sd.c u8 val; val 857 drivers/staging/rts5208/sd.c rtsx_read_register(chip, SD_VP_CTL, &val); val 858 drivers/staging/rts5208/sd.c dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val); val 859 drivers/staging/rts5208/sd.c rtsx_read_register(chip, SD_DCMPS_CTL, &val); val 860 drivers/staging/rts5208/sd.c dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val); val 898 drivers/staging/rts5208/sd.c val = *rtsx_get_cmd_data(chip); val 899 drivers/staging/rts5208/sd.c if (val & DCMPS_ERROR) val 902 drivers/staging/rts5208/sd.c if ((val & DCMPS_CURRENT_PHASE) != sample_point) val 931 drivers/staging/rts5208/sd.c rtsx_read_register(chip, SD_VP_CTL, &val); val 932 drivers/staging/rts5208/sd.c dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val); val 933 drivers/staging/rts5208/sd.c rtsx_read_register(chip, SD_DCMPS_CTL, &val); val 934 drivers/staging/rts5208/sd.c dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val); val 1409 drivers/staging/rts5208/sd.c u8 val = 0; val 1412 drivers/staging/rts5208/sd.c retval = rtsx_read_register(chip, SD_DATA_STATE, &val); val 1415 drivers/staging/rts5208/sd.c if (val & SD_DATA_IDLE) { val 1421 drivers/staging/rts5208/sd.c dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val); val 2242 drivers/staging/rts5208/sd.c u32 val; val 2278 drivers/staging/rts5208/sd.c val = rtsx_readl(chip, RTSX_BIPR); val 2279 drivers/staging/rts5208/sd.c if (val & SD_WRITE_PROTECT) val 357 drivers/staging/rts5208/spi.c int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) val 389 drivers/staging/rts5208/spi.c if (val) val 390 drivers/staging/rts5208/spi.c *val = data; val 399 drivers/staging/rts5208/spi.c int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) val 416 drivers/staging/rts5208/spi.c rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val); val 42 drivers/staging/rts5208/spi.h int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val); val 43 drivers/staging/rts5208/spi.h int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val); val 11 drivers/staging/sm750fb/ddk750_display.c unsigned long reg, val, reserved; val 22 drivers/staging/sm750fb/ddk750_display.c val = peek32(reg); val 30 drivers/staging/sm750fb/ddk750_display.c val |= DISPLAY_CTRL_TIMING; val 31 drivers/staging/sm750fb/ddk750_display.c poke32(reg, val); val 33 drivers/staging/sm750fb/ddk750_display.c val |= DISPLAY_CTRL_PLANE; val 42 drivers/staging/sm750fb/ddk750_display.c poke32(reg, val); val 43 drivers/staging/sm750fb/ddk750_display.c } while ((peek32(reg) & ~reserved) != (val & ~reserved)); val 55 drivers/staging/sm750fb/ddk750_display.c val &= ~DISPLAY_CTRL_PLANE; val 56 drivers/staging/sm750fb/ddk750_display.c poke32(reg, val); val 58 drivers/staging/sm750fb/ddk750_display.c val &= ~DISPLAY_CTRL_TIMING; val 59 drivers/staging/sm750fb/ddk750_display.c poke32(reg, val); val 615 drivers/staging/sm750fb/sm750.c u32 val; val 620 drivers/staging/sm750fb/sm750.c val = chan_to_field(red, &var->red); val 621 drivers/staging/sm750fb/sm750.c val |= chan_to_field(green, &var->green); val 622 drivers/staging/sm750fb/sm750.c val |= chan_to_field(blue, &var->blue); val 623 drivers/staging/sm750fb/sm750.c par->pseudo_palette[regno] = val; val 117 drivers/staging/sm750fb/sm750_hw.c unsigned int val; val 123 drivers/staging/sm750fb/sm750_hw.c val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK; val 124 drivers/staging/sm750fb/sm750_hw.c val |= SYSTEM_CTRL_DPMS_VPHN; val 125 drivers/staging/sm750fb/sm750_hw.c poke32(SYSTEM_CTRL, val); val 130 drivers/staging/sm750fb/sm750_hw.c val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK; val 131 drivers/staging/sm750fb/sm750_hw.c val |= SYSTEM_CTRL_DPMS_VPHP; val 132 drivers/staging/sm750fb/sm750_hw.c poke32(SYSTEM_CTRL, val); val 135 drivers/staging/sm750fb/sm750_hw.c val = peek32(PANEL_DISPLAY_CTRL) & val 142 drivers/staging/sm750fb/sm750_hw.c val |= PANEL_DISPLAY_CTRL_DOUBLE_PIXEL; val 145 drivers/staging/sm750fb/sm750_hw.c val |= PANEL_DISPLAY_CTRL_DUAL_DISPLAY; val 148 drivers/staging/sm750fb/sm750_hw.c poke32(PANEL_DISPLAY_CTRL, val); val 415 drivers/staging/sm750fb/sm750_hw.c unsigned int val; val 417 drivers/staging/sm750fb/sm750_hw.c val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK; val 418 drivers/staging/sm750fb/sm750_hw.c poke32(CRT_DISPLAY_CTRL, val | dpms); val 420 drivers/staging/sm750fb/sm750_hw.c val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK; val 421 drivers/staging/sm750fb/sm750_hw.c poke32(CRT_DISPLAY_CTRL, val | crtdb); val 460 drivers/staging/sm750fb/sm750_hw.c unsigned int val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK; val 462 drivers/staging/sm750fb/sm750_hw.c poke32(SYSTEM_CTRL, val | dpms); val 464 drivers/staging/sm750fb/sm750_hw.c val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK; val 465 drivers/staging/sm750fb/sm750_hw.c poke32(CRT_DISPLAY_CTRL, val | crtdb); val 469 drivers/staging/sm750fb/sm750_hw.c unsigned int val = peek32(PANEL_DISPLAY_CTRL); val 471 drivers/staging/sm750fb/sm750_hw.c val &= ~PANEL_DISPLAY_CTRL_DATA; val 472 drivers/staging/sm750fb/sm750_hw.c val |= pps; val 473 drivers/staging/sm750fb/sm750_hw.c poke32(PANEL_DISPLAY_CTRL, val); val 516 drivers/staging/sm750fb/sm750_hw.c unsigned int val = peek32(DE_STATE2); val 518 drivers/staging/sm750fb/sm750_hw.c if ((val & mask) == val 534 drivers/staging/sm750fb/sm750_hw.c unsigned int val = peek32(SYSTEM_CTRL); val 536 drivers/staging/sm750fb/sm750_hw.c if ((val & mask) == val 137 drivers/staging/speakup/keyhelp.c u_short *p_keys, val; val 203 drivers/staging/speakup/keyhelp.c val = p_keys[n]; val 206 drivers/staging/speakup/keyhelp.c say_key(val); val 273 drivers/staging/speakup/main.c static void bleep(u_short val) val 281 drivers/staging/speakup/main.c freq = vals[val % 12]; val 282 drivers/staging/speakup/main.c if (val > 11) val 283 drivers/staging/speakup/main.c freq *= (1 << (val / 12)); val 303 drivers/staging/speakup/main.c char val = synth->is_alive(synth); val 305 drivers/staging/speakup/main.c if (val == 0) val 309 drivers/staging/speakup/main.c if (val == 2 || spk_killed) { val 1928 drivers/staging/speakup/main.c int val = this_speakup_key - (FIRST_EDIT_BITS - 1); val 1930 drivers/staging/speakup/main.c if (spk_special_handler || val < 1 || val > 6) { val 1934 drivers/staging/speakup/main.c pb_edit = &spk_punc_info[val]; val 2259 drivers/staging/speakup/main.c unsigned char val = KVAL(param->value); val 2263 drivers/staging/speakup/main.c do_handle_shift(vc, val, up); val 2267 drivers/staging/speakup/main.c do_handle_latin(vc, val, up); val 2270 drivers/staging/speakup/main.c do_handle_cursor(vc, val, up); val 2273 drivers/staging/speakup/main.c do_handle_spec(vc, val, up); val 61 drivers/staging/speakup/speakup.h int spk_set_num_var(int val, struct st_var_header *var, int how); val 180 drivers/staging/speakup/varhandlers.c int val; val 189 drivers/staging/speakup/varhandlers.c val = var_data->u.n.value; val 197 drivers/staging/speakup/varhandlers.c val = var_data->u.n.default_val; val 200 drivers/staging/speakup/varhandlers.c val = input; val 203 drivers/staging/speakup/varhandlers.c val += input; val 206 drivers/staging/speakup/varhandlers.c val -= input; val 210 drivers/staging/speakup/varhandlers.c if (val < var_data->u.n.low || val > var_data->u.n.high) val 213 drivers/staging/speakup/varhandlers.c var_data->u.n.value = val; val 215 drivers/staging/speakup/varhandlers.c *p_val = msecs_to_jiffies(val); val 219 drivers/staging/speakup/varhandlers.c *p_val = val; val 221 drivers/staging/speakup/varhandlers.c spk_punc_mask = spk_punc_masks[val]; val 225 drivers/staging/speakup/varhandlers.c val *= var_data->u.n.multiplier; val 226 drivers/staging/speakup/varhandlers.c val += var_data->u.n.offset; val 239 drivers/staging/speakup/varhandlers.c sprintf(cp, var_data->u.n.synth_fmt, (int)val); val 242 drivers/staging/speakup/varhandlers.c var_data->u.n.out_str[val]); val 330 drivers/staging/speakup/varhandlers.c int val; val 333 drivers/staging/speakup/varhandlers.c val = simple_strtoul(skip_spaces(start), &start, 10); val 336 drivers/staging/speakup/varhandlers.c *dest = (u_char)val; val 131 drivers/staging/uwb/drp-avail.c unsigned long val = 0; val 134 drivers/staging/uwb/drp-avail.c BUG_ON(len > sizeof(val)); val 137 drivers/staging/uwb/drp-avail.c val <<= 8; val 138 drivers/staging/uwb/drp-avail.c val |= array[top - 1]; val 141 drivers/staging/uwb/drp-avail.c val <<= 8 * (sizeof(val) - len); /* padding */ val 142 drivers/staging/uwb/drp-avail.c return val; val 195 drivers/staging/uwb/drp-avail.c unsigned long val; val 199 drivers/staging/uwb/drp-avail.c len = buffer_size - itr >= sizeof(val) ? val 200 drivers/staging/uwb/drp-avail.c sizeof(val) : buffer_size - itr; val 201 drivers/staging/uwb/drp-avail.c val = get_val(buffer, itr, len); val 202 drivers/staging/uwb/drp-avail.c bmp_itr[itr / sizeof(val)] = val; val 203 drivers/staging/uwb/drp-avail.c itr += sizeof(val); val 408 drivers/staging/uwb/i1480/dfu/mac.c u32 *val = (u32 *) i1480->cmd_buf; val 417 drivers/staging/uwb/i1480/dfu/mac.c if (*val == 0x55555555UL) /* fw running? cool */ val 66 drivers/staging/uwb/whci.c u32 val; val 68 drivers/staging/uwb/whci.c val = le_readl(reg); val 69 drivers/staging/uwb/whci.c if ((val & mask) == result) val 74 drivers/staging/vc04_services/bcm2835-audio/bcm2835-ctl.c int val, *valp; val 86 drivers/staging/vc04_services/bcm2835-audio/bcm2835-ctl.c val = ucontrol->value.integer.value[0]; val 88 drivers/staging/vc04_services/bcm2835-audio/bcm2835-ctl.c if (val != *valp) { val 89 drivers/staging/vc04_services/bcm2835-audio/bcm2835-ctl.c *valp = val; val 159 drivers/staging/vc04_services/bcm2835-audio/bcm2835-ctl.c unsigned int val = 0; val 165 drivers/staging/vc04_services/bcm2835-audio/bcm2835-ctl.c val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); val 167 drivers/staging/vc04_services/bcm2835-audio/bcm2835-ctl.c change = val != chip->spdif_status; val 168 drivers/staging/vc04_services/bcm2835-audio/bcm2835-ctl.c chip->spdif_status = val; val 169 drivers/staging/vc04_services/bcm2835-camera/controls.c rational_value.num = ctrl->val; val 187 drivers/staging/vc04_services/bcm2835-camera/controls.c u32_value = ctrl->val; val 201 drivers/staging/vc04_services/bcm2835-camera/controls.c if (ctrl->val > mmal_ctrl->max || ctrl->val < mmal_ctrl->min) val 205 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->iso = iso_values[ctrl->val]; val 208 drivers/staging/vc04_services/bcm2835-camera/controls.c (ctrl->val == V4L2_ISO_SENSITIVITY_MANUAL); val 231 drivers/staging/vc04_services/bcm2835-camera/controls.c s32_value = (ctrl->val - 12) * 2; /* Convert from index to 1/6ths */ val 248 drivers/staging/vc04_services/bcm2835-camera/controls.c u32_value = ((ctrl->val % 360) / 90) * 90; val 276 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->hflip = ctrl->val; val 278 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->vflip = ctrl->val; val 323 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->manual_shutter_speed = ctrl->val * 100; val 325 drivers/staging/vc04_services/bcm2835-camera/controls.c switch (ctrl->val) { val 335 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->exposure_mode_v4l2_user = ctrl->val; val 337 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->exp_auto_priority = ctrl->val; val 368 drivers/staging/vc04_services/bcm2835-camera/controls.c switch (ctrl->val) { val 411 drivers/staging/vc04_services/bcm2835-camera/controls.c switch (ctrl->val) { val 440 drivers/staging/vc04_services/bcm2835-camera/controls.c switch (ctrl->val) { val 497 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->red_gain = ctrl->val; val 499 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->blue_gain = ctrl->val; val 520 drivers/staging/vc04_services/bcm2835-camera/controls.c if (ctrl->val == v4l2_to_mmal_effects_values[i].v4l2_effect) { val 561 drivers/staging/vc04_services/bcm2835-camera/controls.c mmal_ctrl, ctrl->id, ctrl->val, imagefx.effect, val 577 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->colourfx.u = (ctrl->val & 0xff00) >> 8; val 578 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->colourfx.v = ctrl->val & 0xff; val 587 drivers/staging/vc04_services/bcm2835-camera/controls.c __func__, mmal_ctrl, ctrl->id, ctrl->val, ret, val 599 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->capture.encode_bitrate = ctrl->val; val 604 drivers/staging/vc04_services/bcm2835-camera/controls.c mmal_ctrl->mmal_id, &ctrl->val, val 605 drivers/staging/vc04_services/bcm2835-camera/controls.c sizeof(ctrl->val)); val 609 drivers/staging/vc04_services/bcm2835-camera/controls.c __func__, mmal_ctrl, ctrl->id, ctrl->val, ret, val 629 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->capture.encode_bitrate_mode = ctrl->val; val 630 drivers/staging/vc04_services/bcm2835-camera/controls.c switch (ctrl->val) { val 656 drivers/staging/vc04_services/bcm2835-camera/controls.c u32_value = ctrl->val; val 672 drivers/staging/vc04_services/bcm2835-camera/controls.c u32_value = ctrl->val; val 687 drivers/staging/vc04_services/bcm2835-camera/controls.c switch (ctrl->val) { val 692 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->capture.enc_profile = ctrl->val; val 699 drivers/staging/vc04_services/bcm2835-camera/controls.c switch (ctrl->val) { val 712 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->capture.enc_level = ctrl->val; val 799 drivers/staging/vc04_services/bcm2835-camera/controls.c "scene mode selected %d, was %d\n", ctrl->val, val 803 drivers/staging/vc04_services/bcm2835-camera/controls.c if (ctrl->val == dev->scene_mode) val 806 drivers/staging/vc04_services/bcm2835-camera/controls.c if (ctrl->val == V4L2_SCENE_MODE_NONE) { val 846 drivers/staging/vc04_services/bcm2835-camera/controls.c ctrl->val) { val 857 drivers/staging/vc04_services/bcm2835-camera/controls.c dev->scene_mode = ctrl->val; val 892 drivers/staging/vc04_services/bcm2835-camera/controls.c __func__, ctrl->val, ret); val 205 drivers/staging/wilc1000/wilc_hif.c wid.val = (s8 *)&abort_running_scan; val 266 drivers/staging/wilc1000/wilc_hif.c wid_list[index].val = search_ssid_vals; val 267 drivers/staging/wilc1000/wilc_hif.c buffer = wid_list[index].val; val 284 drivers/staging/wilc1000/wilc_hif.c wid_list[index].val = (s8 *)request->ie; val 291 drivers/staging/wilc1000/wilc_hif.c wid_list[index].val = (s8 *)&scan_type; val 298 drivers/staging/wilc1000/wilc_hif.c wid_list[index].val = (s8 *)&request->duration; val 316 drivers/staging/wilc1000/wilc_hif.c wid_list[index].val = ch_freq_list; val 323 drivers/staging/wilc1000/wilc_hif.c wid_list[index].val = (s8 *)&scan_source; val 357 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = conn_attr->req_ies; val 364 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = (s8 *)&conn_attr->security; val 370 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = (s8 *)&conn_attr->auth_type; val 376 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = (u8 *)bss_param; val 424 drivers/staging/wilc1000/wilc_hif.c wid.val = (s8 *)&dummy_reason_code; val 619 drivers/staging/wilc1000/wilc_hif.c wid.val = assoc_resp_info; val 769 drivers/staging/wilc1000/wilc_hif.c wid.val = (s8 *)&dummy_reason_code; val 816 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = (s8 *)&stats->link_speed; val 822 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = (s8 *)&stats->rssi; val 828 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = (s8 *)&stats->tx_cnt; val 834 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = (s8 *)&stats->rx_cnt; val 840 drivers/staging/wilc1000/wilc_hif.c wid_list[wid_cnt].val = (s8 *)&stats->tx_fail_cnt; val 919 drivers/staging/wilc1000/wilc_hif.c wid.val = kmalloc(wid.size, GFP_KERNEL); val 920 drivers/staging/wilc1000/wilc_hif.c if (!wid.val) val 923 drivers/staging/wilc1000/wilc_hif.c wid.val[0] = remain_on_chan_flag; val 924 drivers/staging/wilc1000/wilc_hif.c wid.val[1] = (s8)hif_remain_ch->ch; val 927 drivers/staging/wilc1000/wilc_hif.c kfree(wid.val); val 954 drivers/staging/wilc1000/wilc_hif.c wid.val = kmalloc(wid.size, GFP_KERNEL); val 955 drivers/staging/wilc1000/wilc_hif.c if (!wid.val) val 958 drivers/staging/wilc1000/wilc_hif.c wid.val[0] = remain_on_chan_flag; val 959 drivers/staging/wilc1000/wilc_hif.c wid.val[1] = WILC_FALSE_FRMWR_CHANNEL; val 962 drivers/staging/wilc1000/wilc_hif.c kfree(wid.val); val 1022 drivers/staging/wilc1000/wilc_hif.c wid.val = kmalloc(wid.size, GFP_KERNEL); val 1023 drivers/staging/wilc1000/wilc_hif.c if (!wid.val) val 1026 drivers/staging/wilc1000/wilc_hif.c cur_byte = wid.val; val 1042 drivers/staging/wilc1000/wilc_hif.c kfree(wid.val); val 1106 drivers/staging/wilc1000/wilc_hif.c wid.val = &index; val 1123 drivers/staging/wilc1000/wilc_hif.c wid.val = &index; val 1146 drivers/staging/wilc1000/wilc_hif.c wid.val = (u8 *)wep_key; val 1171 drivers/staging/wilc1000/wilc_hif.c wid_list[0].val = &mode; val 1176 drivers/staging/wilc1000/wilc_hif.c wid_list[1].val = (s8 *)&auth_type; val 1185 drivers/staging/wilc1000/wilc_hif.c wid_list[2].val = (u8 *)wep_key; val 1214 drivers/staging/wilc1000/wilc_hif.c wid_list[0].val = (s8 *)&cipher_mode; val 1236 drivers/staging/wilc1000/wilc_hif.c wid_list[1].val = (u8 *)key_buf; val 1263 drivers/staging/wilc1000/wilc_hif.c wid.val = (s8 *)key_buf; val 1308 drivers/staging/wilc1000/wilc_hif.c wid_list[0].val = (s8 *)&cipher_mode; val 1313 drivers/staging/wilc1000/wilc_hif.c wid_list[1].val = (u8 *)gtk_key; val 1323 drivers/staging/wilc1000/wilc_hif.c wid.val = (u8 *)gtk_key; val 1338 drivers/staging/wilc1000/wilc_hif.c wid.val = (u8 *)pmkid; val 1351 drivers/staging/wilc1000/wilc_hif.c wid.val = mac_addr; val 1401 drivers/staging/wilc1000/wilc_hif.c wid.val = &channel; val 1420 drivers/staging/wilc1000/wilc_hif.c wid.val = (u8 *)&drv; val 1440 drivers/staging/wilc1000/wilc_hif.c wid.val = kzalloc(wid.size, GFP_KERNEL); val 1441 drivers/staging/wilc1000/wilc_hif.c if (!wid.val) val 1444 drivers/staging/wilc1000/wilc_hif.c ether_addr_copy(wid.val, mac); val 1446 drivers/staging/wilc1000/wilc_hif.c kfree(wid.val); val 1454 drivers/staging/wilc1000/wilc_hif.c wid.val = (s8 *)out_val; val 1476 drivers/staging/wilc1000/wilc_hif.c wid.val = rssi_level; val 1512 drivers/staging/wilc1000/wilc_hif.c wid_list[i].val = (s8 *)¶m->short_retry_limit; val 1519 drivers/staging/wilc1000/wilc_hif.c wid_list[i].val = (s8 *)¶m->long_retry_limit; val 1526 drivers/staging/wilc1000/wilc_hif.c wid_list[i].val = (s8 *)¶m->frag_threshold; val 1533 drivers/staging/wilc1000/wilc_hif.c wid_list[i].val = (s8 *)¶m->rts_threshold; val 1783 drivers/staging/wilc1000/wilc_hif.c wid.val = (u8 *)®_frame; val 1816 drivers/staging/wilc1000/wilc_hif.c wid.val = kzalloc(wid.size, GFP_KERNEL); val 1817 drivers/staging/wilc1000/wilc_hif.c if (!wid.val) val 1820 drivers/staging/wilc1000/wilc_hif.c cur_byte = wid.val; val 1842 drivers/staging/wilc1000/wilc_hif.c kfree(wid.val); val 1856 drivers/staging/wilc1000/wilc_hif.c wid.val = &del_beacon; val 1875 drivers/staging/wilc1000/wilc_hif.c wid.val = kmalloc(wid.size, GFP_KERNEL); val 1876 drivers/staging/wilc1000/wilc_hif.c if (!wid.val) val 1879 drivers/staging/wilc1000/wilc_hif.c cur_byte = wid.val; val 1886 drivers/staging/wilc1000/wilc_hif.c kfree(wid.val); val 1899 drivers/staging/wilc1000/wilc_hif.c wid.val = kzalloc(wid.size, GFP_KERNEL); val 1900 drivers/staging/wilc1000/wilc_hif.c if (!wid.val) val 1904 drivers/staging/wilc1000/wilc_hif.c eth_broadcast_addr(wid.val); val 1906 drivers/staging/wilc1000/wilc_hif.c ether_addr_copy(wid.val, mac_addr); val 1912 drivers/staging/wilc1000/wilc_hif.c kfree(wid.val); val 1941 drivers/staging/wilc1000/wilc_hif.c wid.val = (u8 *)&del_sta; val 1960 drivers/staging/wilc1000/wilc_hif.c wid.val = kmalloc(wid.size, GFP_KERNEL); val 1961 drivers/staging/wilc1000/wilc_hif.c if (!wid.val) val 1964 drivers/staging/wilc1000/wilc_hif.c cur_byte = wid.val; val 1971 drivers/staging/wilc1000/wilc_hif.c kfree(wid.val); val 1987 drivers/staging/wilc1000/wilc_hif.c wid.val = &power_mode; val 2024 drivers/staging/wilc1000/wilc_hif.c wid.val = &tx_power; val 2036 drivers/staging/wilc1000/wilc_hif.c wid.val = tx_power; val 871 drivers/staging/wilc1000/wilc_sdio.c static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val) val 884 drivers/staging/wilc1000/wilc_sdio.c flags = val & (BIT(MAX_NUN_INT_THRPT_ENH2) - 1); val 890 drivers/staging/wilc1000/wilc_sdio.c if (val & SEL_VMM_TBL0) val 893 drivers/staging/wilc1000/wilc_sdio.c if (val & SEL_VMM_TBL1) val 896 drivers/staging/wilc1000/wilc_sdio.c if (val & EN_VMM) val 925 drivers/staging/wilc1000/wilc_sdio.c flags = val & (BIT(MAX_NUM_INT) - 1); val 966 drivers/staging/wilc1000/wilc_sdio.c if (val & SEL_VMM_TBL0) val 969 drivers/staging/wilc1000/wilc_sdio.c if (val & SEL_VMM_TBL1) val 972 drivers/staging/wilc1000/wilc_sdio.c if (val & EN_VMM) val 975 drivers/staging/wilc1000/wilc_spi.c static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) val 985 drivers/staging/wilc1000/wilc_spi.c val); val 988 drivers/staging/wilc1000/wilc_spi.c flags = val & (BIT(MAX_NUM_INT) - 1); val 1022 drivers/staging/wilc1000/wilc_spi.c if (val & SEL_VMM_TBL0) val 1025 drivers/staging/wilc1000/wilc_spi.c if (val & SEL_VMM_TBL1) val 1034 drivers/staging/wilc1000/wilc_spi.c if (val & EN_VMM) { val 1138 drivers/staging/wilc1000/wilc_wlan.c wids[i].val, val 1145 drivers/staging/wilc1000/wilc_wlan.c wids[i].val, val 238 drivers/staging/wilc1000/wilc_wlan.h int (*hif_clear_int_ext)(struct wilc *wilc, u32 val); val 147 drivers/staging/wilc1000/wilc_wlan_cfg.c wl->cfg.b[i].val = info[4]; val 163 drivers/staging/wilc1000/wilc_wlan_cfg.c hw->val = get_unaligned_le16(&info[4]); val 179 drivers/staging/wilc1000/wilc_wlan_cfg.c w->val = get_unaligned_le32(&info[4]); val 226 drivers/staging/wilc1000/wilc_wlan_cfg.c wl->cfg.b[i].val = info[3]; val 298 drivers/staging/wilc1000/wilc_wlan_cfg.c memcpy(buffer, &wl->cfg.b[i].val, 1); val 310 drivers/staging/wilc1000/wilc_wlan_cfg.c memcpy(buffer, &wl->cfg.hw[i].val, 2); val 322 drivers/staging/wilc1000/wilc_wlan_cfg.c memcpy(buffer, &wl->cfg.w[i].val, 4); val 12 drivers/staging/wilc1000/wilc_wlan_cfg.h u8 val; val 17 drivers/staging/wilc1000/wilc_wlan_cfg.h u16 val; val 22 drivers/staging/wilc1000/wilc_wlan_cfg.h u32 val; val 200 drivers/staging/wilc1000/wilc_wlan_if.h s8 *val; val 1386 drivers/staging/wlan-ng/hfa384x.h static inline int hfa384x_drvr_getconfig16(struct hfa384x *hw, u16 rid, void *val) val 1390 drivers/staging/wlan-ng/hfa384x.h result = hfa384x_drvr_getconfig(hw, rid, val, sizeof(u16)); val 1392 drivers/staging/wlan-ng/hfa384x.h le16_to_cpus(val); val 1396 drivers/staging/wlan-ng/hfa384x.h static inline int hfa384x_drvr_setconfig16(struct hfa384x *hw, u16 rid, u16 val) val 1398 drivers/staging/wlan-ng/hfa384x.h __le16 value = cpu_to_le16(val); val 1410 drivers/staging/wlan-ng/hfa384x.h hfa384x_drvr_setconfig16_async(struct hfa384x *hw, u16 rid, u16 val) val 1412 drivers/staging/wlan-ng/hfa384x.h __le16 value = cpu_to_le16(val); val 922 drivers/staging/wusbcore/devconnect.c int wusb_usb_ncb(struct notifier_block *nb, unsigned long val, val 927 drivers/staging/wusbcore/devconnect.c switch (val) { val 15 drivers/staging/wusbcore/host/whci/hw.c void whc_write_wusbcmd(struct whc *whc, u32 mask, u32 val) val 23 drivers/staging/wusbcore/host/whci/hw.c cmd = (cmd & ~mask) | val; val 134 drivers/staging/wusbcore/host/whci/whcd.h void whc_write_wusbcmd(struct whc *whc, u32 mask, u32 val); val 390 drivers/staging/wusbcore/wa-rpipe.c #define AIM_CHECK(rdf, val, text) \ val 392 drivers/staging/wusbcore/wa-rpipe.c if (rpipe->descr.rdf != (val)) { \ val 395 drivers/staging/wusbcore/wa-rpipe.c rpipe->descr.rdf, (val)); \ val 384 drivers/staging/wusbcore/wusbhc.h extern int wusb_usb_ncb(struct notifier_block *nb, unsigned long val, val 1438 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[0].val = cpu_to_be32(FW_PFVF_CMD_PFN_V val 1441 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[1].val = cpu_to_be32(csk->tx_chan); val 1443 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[2].val = cpu_to_be32(csk->tx_chan); val 1445 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[3].val = cpu_to_be32(csk->rss_qid); val 1447 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[4].val = cpu_to_be32(csk->snd_nxt); val 1449 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[5].val = cpu_to_be32(csk->rcv_nxt); val 1451 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[6].val = cpu_to_be32(csk->snd_win); val 1453 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[7].val = cpu_to_be32(csk->emss); val 1457 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[8].val = cpu_to_be32(CXGBIT_MAX_ISO_PAYLOAD); val 1459 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[8].val = cpu_to_be32(16384); val 1465 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[index].val = cpu_to_be32(csk->snd_wscale); val 1473 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[index].val = cpu_to_be32(0); val 1475 drivers/target/iscsi/cxgbit/cxgbit_cm.c flowc->mnemval[index].val = cpu_to_be32( val 1509 drivers/target/iscsi/cxgbit/cxgbit_cm.c req->val = cpu_to_be64(((hcrc ? ULP_CRC_HEADER : 0) | val 1545 drivers/target/iscsi/cxgbit/cxgbit_cm.c req->val = cpu_to_be64(pg_idx << 8); val 297 drivers/target/iscsi/iscsi_target_configfs.c u32 val; \ val 300 drivers/target/iscsi/iscsi_target_configfs.c ret = kstrtou32(page, 0, &val); \ val 303 drivers/target/iscsi/iscsi_target_configfs.c ret = iscsit_na_##name(nacl, val); \ val 742 drivers/target/iscsi/iscsi_target_configfs.c u32 val; \ val 748 drivers/target/iscsi/iscsi_target_configfs.c ret = kstrtou32(page, 0, &val); \ val 751 drivers/target/iscsi/iscsi_target_configfs.c ret = iscsit_ta_##name(tpg, val); \ val 691 drivers/target/loopback/tcm_loop.c unsigned long val; val 692 drivers/target/loopback/tcm_loop.c int ret = kstrtoul(page, 0, &val); val 698 drivers/target/loopback/tcm_loop.c if (val != 0 && val != 1 && val != 3) { val 699 drivers/target/loopback/tcm_loop.c pr_err("Invalid qla2xxx fabric_prot_type: %lu\n", val); val 702 drivers/target/loopback/tcm_loop.c tl_tpg->tl_fabric_prot_type = val; val 2110 drivers/target/sbp/sbp_target.c unsigned long val; val 2120 drivers/target/sbp/sbp_target.c if (kstrtoul(page, 16, &val) < 0) val 2122 drivers/target/sbp/sbp_target.c if (val > 0xffffff) val 2125 drivers/target/sbp/sbp_target.c tport->directory_id = val; val 2145 drivers/target/sbp/sbp_target.c unsigned long val; val 2148 drivers/target/sbp/sbp_target.c if (kstrtoul(page, 0, &val) < 0) val 2150 drivers/target/sbp/sbp_target.c if ((val != 0) && (val != 1)) val 2153 drivers/target/sbp/sbp_target.c if (tport->enable == val) val 2156 drivers/target/sbp/sbp_target.c if (val) { val 2171 drivers/target/sbp/sbp_target.c tport->enable = val; val 2206 drivers/target/sbp/sbp_target.c unsigned long val; val 2209 drivers/target/sbp/sbp_target.c if (kstrtoul(page, 0, &val) < 0) val 2211 drivers/target/sbp/sbp_target.c if ((val < 1) || (val > 127)) val 2214 drivers/target/sbp/sbp_target.c if (tport->mgt_orb_timeout == val) val 2217 drivers/target/sbp/sbp_target.c tport->mgt_orb_timeout = val; val 2241 drivers/target/sbp/sbp_target.c unsigned long val; val 2244 drivers/target/sbp/sbp_target.c if (kstrtoul(page, 0, &val) < 0) val 2246 drivers/target/sbp/sbp_target.c if ((val < 1) || (val > 32767)) val 2249 drivers/target/sbp/sbp_target.c if (tport->max_reconnect_timeout == val) val 2252 drivers/target/sbp/sbp_target.c tport->max_reconnect_timeout = val; val 2276 drivers/target/sbp/sbp_target.c unsigned long val; val 2278 drivers/target/sbp/sbp_target.c if (kstrtoul(page, 0, &val) < 0) val 2280 drivers/target/sbp/sbp_target.c if ((val < 1) || (val > 127)) val 2285 drivers/target/sbp/sbp_target.c tport->max_logins_per_lun = val; val 555 drivers/target/target_core_configfs.c u32 val; \ val 558 drivers/target/target_core_configfs.c ret = kstrtou32(page, 0, &val); \ val 561 drivers/target/target_core_configfs.c da->_name = val; \ val 680 drivers/target/target_core_configfs.c u32 val; val 683 drivers/target/target_core_configfs.c ret = kstrtou32(page, 0, &val); val 687 drivers/target/target_core_configfs.c if (val != 0 && val != 1 && val != 2) { val 688 drivers/target/target_core_configfs.c pr_err("Illegal value %d\n", val); val 698 drivers/target/target_core_configfs.c da->emulate_ua_intlck_ctrl = val; val 700 drivers/target/target_core_configfs.c da->da_dev, val); val 1001 drivers/target/target_core_configfs.c u32 val; val 1004 drivers/target/target_core_configfs.c ret = kstrtou32(page, 0, &val); val 1014 drivers/target/target_core_configfs.c if (!val) { val 1019 drivers/target/target_core_configfs.c if (val > dev->dev_attrib.queue_depth) { val 1020 drivers/target/target_core_configfs.c if (val > dev->dev_attrib.hw_queue_depth) { val 1023 drivers/target/target_core_configfs.c " TCQ: %u\n", dev, val, val 1028 drivers/target/target_core_configfs.c da->queue_depth = dev->queue_depth = val; val 1029 drivers/target/target_core_configfs.c pr_debug("dev[%p]: SE Device TCQ Depth changed to: %u\n", dev, val); val 1037 drivers/target/target_core_configfs.c u32 val; val 1040 drivers/target/target_core_configfs.c ret = kstrtou32(page, 0, &val); val 1050 drivers/target/target_core_configfs.c if (val > da->hw_max_sectors) { val 1053 drivers/target/target_core_configfs.c da->da_dev, val, da->hw_max_sectors); val 1057 drivers/target/target_core_configfs.c da->optimal_sectors = val; val 1059 drivers/target/target_core_configfs.c da->da_dev, val); val 1067 drivers/target/target_core_configfs.c u32 val; val 1070 drivers/target/target_core_configfs.c ret = kstrtou32(page, 0, &val); val 1081 drivers/target/target_core_configfs.c if (val != 512 && val != 1024 && val != 2048 && val != 4096) { val 1084 drivers/target/target_core_configfs.c da->da_dev, val); val 1088 drivers/target/target_core_configfs.c da->block_size = val; val 1090 drivers/target/target_core_configfs.c da->hw_max_sectors = da->max_bytes_per_io / val; val 1093 drivers/target/target_core_configfs.c da->da_dev, val); val 148 drivers/target/target_core_spc.c int val = hex_to_bin(*p); val 150 drivers/target/target_core_spc.c if (val < 0) val 155 drivers/target/target_core_spc.c buf[cnt++] |= val; val 158 drivers/target/target_core_spc.c buf[cnt] = val << 4; val 260 drivers/target/target_core_user.c u8 val; val 262 drivers/target/target_core_user.c ret = kstrtou8(str, 0, &val); val 266 drivers/target/target_core_user.c if (val > 1) { val 267 drivers/target/target_core_user.c pr_err("Invalid block netlink value %u\n", val); val 271 drivers/target/target_core_user.c tcmu_netlink_blocked = val; val 306 drivers/target/target_core_user.c u8 val; val 308 drivers/target/target_core_user.c ret = kstrtou8(str, 0, &val); val 312 drivers/target/target_core_user.c if (val != 1) { val 313 drivers/target/target_core_user.c pr_err("Invalid reset netlink value %u\n", val); val 2100 drivers/target/target_core_user.c int val, ret; val 2102 drivers/target/target_core_user.c ret = match_int(arg, &val); val 2109 drivers/target/target_core_user.c if (val <= 0) { val 2111 drivers/target/target_core_user.c val); val 2114 drivers/target/target_core_user.c *dev_attrib = val; val 2120 drivers/target/target_core_user.c int val, ret; val 2122 drivers/target/target_core_user.c ret = match_int(arg, &val); val 2129 drivers/target/target_core_user.c if (val <= 0) { val 2130 drivers/target/target_core_user.c pr_err("Invalid max_data_area %d.\n", val); val 2141 drivers/target/target_core_user.c udev->max_blocks = TCMU_MBS_TO_BLOCKS(val); val 2144 drivers/target/target_core_user.c val, TCMU_BLOCKS_TO_MBS(tcmu_global_max_blocks)); val 2260 drivers/target/target_core_user.c u32 val; val 2268 drivers/target/target_core_user.c ret = kstrtou32(page, 0, &val); val 2272 drivers/target/target_core_user.c udev->cmd_time_out = val * MSEC_PER_SEC; val 2294 drivers/target/target_core_user.c s32 val; val 2297 drivers/target/target_core_user.c ret = kstrtos32(page, 0, &val); val 2301 drivers/target/target_core_user.c if (val >= 0) { val 2302 drivers/target/target_core_user.c udev->qfull_time_out = val * MSEC_PER_SEC; val 2303 drivers/target/target_core_user.c } else if (val == -1) { val 2304 drivers/target/target_core_user.c udev->qfull_time_out = val; val 2306 drivers/target/target_core_user.c printk(KERN_ERR "Invalid qfull timeout value %d\n", val); val 2421 drivers/target/target_core_user.c u64 val; val 2424 drivers/target/target_core_user.c ret = kstrtou64(page, 0, &val); val 2430 drivers/target/target_core_user.c ret = tcmu_send_dev_size_event(udev, val); val 2436 drivers/target/target_core_user.c udev->dev_size = val; val 2457 drivers/target/target_core_user.c s8 val; val 2460 drivers/target/target_core_user.c ret = kstrtos8(page, 0, &val); val 2464 drivers/target/target_core_user.c udev->nl_reply_supported = val; val 2478 drivers/target/target_core_user.c static int tcmu_send_emulate_write_cache(struct tcmu_dev *udev, u8 val) val 2488 drivers/target/target_core_user.c ret = nla_put_u8(skb, TCMU_ATTR_WRITECACHE, val); val 2503 drivers/target/target_core_user.c u8 val; val 2506 drivers/target/target_core_user.c ret = kstrtou8(page, 0, &val); val 2512 drivers/target/target_core_user.c ret = tcmu_send_emulate_write_cache(udev, val); val 2519 drivers/target/target_core_user.c da->emulate_write_cache = val; val 2544 drivers/target/target_core_user.c u8 val; val 2552 drivers/target/target_core_user.c ret = kstrtou8(page, 0, &val); val 2556 drivers/target/target_core_user.c if (val > 1) { val 2557 drivers/target/target_core_user.c pr_err("Invalid block value %d\n", val); val 2561 drivers/target/target_core_user.c if (!val) val 2576 drivers/target/target_core_user.c u8 val; val 2584 drivers/target/target_core_user.c ret = kstrtou8(page, 0, &val); val 2588 drivers/target/target_core_user.c if (val != 1 && val != 2) { val 2589 drivers/target/target_core_user.c pr_err("Invalid reset ring value %d\n", val); val 2593 drivers/target/target_core_user.c tcmu_reset_ring(udev, val); val 56 drivers/target/tcm_fc/tfc_conf.c int val; val 77 drivers/target/tcm_fc/tfc_conf.c val = hex_to_bin(c); val 78 drivers/target/tcm_fc/tfc_conf.c if (val < 0 || (strict && isupper(c))) val 80 drivers/target/tcm_fc/tfc_conf.c *wwn = (*wwn << 4) | val; val 187 drivers/tee/optee/optee_private.h static inline void reg_pair_from_64(u32 *reg0, u32 *reg1, u64 val) val 189 drivers/tee/optee/optee_private.h *reg0 = val >> 32; val 190 drivers/tee/optee/optee_private.h *reg1 = val; val 94 drivers/thermal/broadcom/bcm2835_thermal.c u32 val = readl(data->regs + BCM2835_TS_TSENSSTAT); val 96 drivers/thermal/broadcom/bcm2835_thermal.c if (!(val & BCM2835_TS_TSENSSTAT_VALID)) val 99 drivers/thermal/broadcom/bcm2835_thermal.c val &= BCM2835_TS_TSENSSTAT_DATA_MASK; val 102 drivers/thermal/broadcom/bcm2835_thermal.c val, val 171 drivers/thermal/broadcom/bcm2835_thermal.c u32 val; val 226 drivers/thermal/broadcom/bcm2835_thermal.c val = readl(data->regs + BCM2835_TS_TSENSCTL); val 227 drivers/thermal/broadcom/bcm2835_thermal.c if (!(val & BCM2835_TS_TSENSCTL_RSTB)) { val 245 drivers/thermal/broadcom/bcm2835_thermal.c val = (BCM2835_TS_TSENSCTL_CTRL_DEFAULT << val 250 drivers/thermal/broadcom/bcm2835_thermal.c val |= (0xFE << BCM2835_TS_TSENSCTL_RSTDELAY_SHIFT); val 253 drivers/thermal/broadcom/bcm2835_thermal.c val |= bcm2835_thermal_temp2adc(trip_temp, val 259 drivers/thermal/broadcom/bcm2835_thermal.c writel(val, data->regs + BCM2835_TS_TSENSCTL); val 260 drivers/thermal/broadcom/bcm2835_thermal.c val |= BCM2835_TS_TSENSCTL_RSTB; val 261 drivers/thermal/broadcom/bcm2835_thermal.c writel(val, data->regs + BCM2835_TS_TSENSCTL); val 145 drivers/thermal/broadcom/brcmstb_thermal.c u32 val; val 148 drivers/thermal/broadcom/brcmstb_thermal.c val = __raw_readl(priv->tmon_base + AVS_TMON_STATUS); val 150 drivers/thermal/broadcom/brcmstb_thermal.c if (!(val & AVS_TMON_STATUS_valid_msk)) { val 155 drivers/thermal/broadcom/brcmstb_thermal.c val = (val & AVS_TMON_STATUS_data_msk) >> AVS_TMON_STATUS_data_shift; val 157 drivers/thermal/broadcom/brcmstb_thermal.c t = avs_tmon_code_to_temp(priv->thermal, val); val 170 drivers/thermal/broadcom/brcmstb_thermal.c u32 val = __raw_readl(priv->tmon_base + trip->enable_offs); val 175 drivers/thermal/broadcom/brcmstb_thermal.c val |= trip->enable_mask; val 177 drivers/thermal/broadcom/brcmstb_thermal.c val &= ~trip->enable_mask; val 179 drivers/thermal/broadcom/brcmstb_thermal.c __raw_writel(val, priv->tmon_base + trip->enable_offs); val 186 drivers/thermal/broadcom/brcmstb_thermal.c u32 val = __raw_readl(priv->tmon_base + trip->reg_offs); val 188 drivers/thermal/broadcom/brcmstb_thermal.c val &= trip->reg_msk; val 189 drivers/thermal/broadcom/brcmstb_thermal.c val >>= trip->reg_shift; val 191 drivers/thermal/broadcom/brcmstb_thermal.c return avs_tmon_code_to_temp(priv->thermal, val); val 199 drivers/thermal/broadcom/brcmstb_thermal.c u32 val, orig; val 204 drivers/thermal/broadcom/brcmstb_thermal.c val = avs_tmon_temp_to_code(priv->thermal, temp, val 207 drivers/thermal/broadcom/brcmstb_thermal.c val <<= trip->reg_shift; val 208 drivers/thermal/broadcom/brcmstb_thermal.c val &= trip->reg_msk; val 212 drivers/thermal/broadcom/brcmstb_thermal.c orig |= val; val 218 drivers/thermal/broadcom/brcmstb_thermal.c u32 val; val 220 drivers/thermal/broadcom/brcmstb_thermal.c val = __raw_readl(priv->tmon_base + AVS_TMON_TEMP_INT_CODE); val 221 drivers/thermal/broadcom/brcmstb_thermal.c return avs_tmon_code_to_temp(priv->thermal, val); val 27 drivers/thermal/broadcom/ns-thermal.c u32 val; val 29 drivers/thermal/broadcom/ns-thermal.c val = readl(ns_thermal->pvtmon + PVTMON_CONTROL0); val 30 drivers/thermal/broadcom/ns-thermal.c if ((val & PVTMON_CONTROL0_SEL_MASK) != PVTMON_CONTROL0_SEL_TEMP_MONITOR) { val 32 drivers/thermal/broadcom/ns-thermal.c val &= ~PVTMON_CONTROL0_SEL_MASK; val 35 drivers/thermal/broadcom/ns-thermal.c val |= PVTMON_CONTROL0_SEL_TEMP_MONITOR; val 37 drivers/thermal/broadcom/ns-thermal.c writel(val, ns_thermal->pvtmon + PVTMON_CONTROL0); val 40 drivers/thermal/broadcom/ns-thermal.c val = readl(ns_thermal->pvtmon + PVTMON_STATUS); val 41 drivers/thermal/broadcom/ns-thermal.c *temp = slope * val + offset; val 175 drivers/thermal/clock_cooling.c unsigned long val; val 177 drivers/thermal/clock_cooling.c if (clock_cooling_get_property(ccdev, (unsigned long)freq, &val, val 181 drivers/thermal/clock_cooling.c return val; val 66 drivers/thermal/da9062-thermal.c unsigned int val; val 85 drivers/thermal/da9062-thermal.c &val); val 92 drivers/thermal/da9062-thermal.c if (val & DA9062AA_E_TEMP_MASK) { val 264 drivers/thermal/imx_thermal.c u32 val; val 268 drivers/thermal/imx_thermal.c regmap_read(map, soc_data->temp_data, &val); val 269 drivers/thermal/imx_thermal.c wait = !(val & soc_data->temp_valid_mask); val 291 drivers/thermal/imx_thermal.c regmap_read(map, soc_data->temp_data, &val); val 300 drivers/thermal/imx_thermal.c if ((val & soc_data->temp_valid_mask) == 0) { val 305 drivers/thermal/imx_thermal.c n_meas = (val & soc_data->temp_value_mask) val 571 drivers/thermal/imx_thermal.c u32 val; val 581 drivers/thermal/imx_thermal.c ret = regmap_read(map, OCOTP_ANA1, &val); val 586 drivers/thermal/imx_thermal.c ret = imx_init_calib(pdev, val); val 590 drivers/thermal/imx_thermal.c ret = regmap_read(map, OCOTP_MEM0, &val); val 595 drivers/thermal/imx_thermal.c imx_init_temp_grade(pdev, val); val 603 drivers/thermal/imx_thermal.c u32 val; val 605 drivers/thermal/imx_thermal.c ret = nvmem_cell_read_u32(&pdev->dev, "calib", &val); val 609 drivers/thermal/imx_thermal.c ret = imx_init_calib(pdev, val); val 613 drivers/thermal/imx_thermal.c ret = nvmem_cell_read_u32(&pdev->dev, "temp_grade", &val); val 616 drivers/thermal/imx_thermal.c imx_init_temp_grade(pdev, val); val 146 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c u64 val; val 149 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); val 153 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val = (val >> 24) & 0xff; val 154 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c return sprintf(buf, "%d\n", (int)val); val 159 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c u64 val; val 165 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); val 169 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val &= ~GENMASK_ULL(31, 24); val 170 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val |= (tcc & 0xff) << 24; val 172 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val); val 185 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c u64 val; val 188 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c err = rdmsrl_safe(MSR_PLATFORM_INFO, &val); val 192 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c if (!(val & BIT(30))) val 214 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c u32 val; val 221 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val = (eax >> 16) & 0xff; val 222 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c if (val) val 223 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c return val; val 513 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c u64 val; val 518 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val = readq((void __iomem *)ra->reg); val 519 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val &= ~ra->mask; val 520 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val |= ra->value; val 521 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c writeq(val, (void __iomem *)ra->reg); val 232 drivers/thermal/intel/intel_powerclamp.c u64 val; val 237 drivers/thermal/intel/intel_powerclamp.c if (!rdmsrl_safe(info->msr_index, &val)) val 247 drivers/thermal/intel/intel_powerclamp.c u64 val; val 253 drivers/thermal/intel/intel_powerclamp.c if (!rdmsrl_safe(info->msr_index, &val)) val 254 drivers/thermal/intel/intel_powerclamp.c count += val; val 50 drivers/thermal/intel/intel_soc_dts_iosf.c u32 val; val 57 drivers/thermal/intel/intel_soc_dts_iosf.c val = (eax >> 16) & 0xff; val 58 drivers/thermal/intel/intel_soc_dts_iosf.c if (val) val 59 drivers/thermal/intel/intel_soc_dts_iosf.c *tj_max = val * 1000; val 111 drivers/thermal/intel/x86_pkg_temp_thermal.c u32 eax, edx, val; val 118 drivers/thermal/intel/x86_pkg_temp_thermal.c val = (eax >> 16) & 0xff; val 119 drivers/thermal/intel/x86_pkg_temp_thermal.c *tj_max = val * 1000; val 121 drivers/thermal/intel/x86_pkg_temp_thermal.c return val ? 0 : -EINVAL; val 50 drivers/thermal/max77620_thermal.c unsigned int val; val 53 drivers/thermal/max77620_thermal.c ret = regmap_read(mtherm->rmap, MAX77620_REG_STATLBT, &val); val 59 drivers/thermal/max77620_thermal.c if (val & MAX77620_IRQ_TJALRM2_MASK) val 61 drivers/thermal/max77620_thermal.c else if (val & MAX77620_IRQ_TJALRM1_MASK) val 553 drivers/thermal/mtk_thermal.c u32 val; val 558 drivers/thermal/mtk_thermal.c val = readl(mt->thermal_base + PTPCORESEL); val 559 drivers/thermal/mtk_thermal.c val &= ~0xf; val 560 drivers/thermal/mtk_thermal.c val |= bank->id; val 561 drivers/thermal/mtk_thermal.c writel(val, mt->thermal_base + PTPCORESEL); val 87 drivers/thermal/qcom/qcom-spmi-temp-alarm.c unsigned int val; val 90 drivers/thermal/qcom/qcom-spmi-temp-alarm.c ret = regmap_read(chip->map, chip->base + addr, &val); val 94 drivers/thermal/qcom/qcom-spmi-temp-alarm.c *data = val; val 81 drivers/thermal/qoriq_thermal.c static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr) val 84 drivers/thermal/qoriq_thermal.c iowrite32(val, addr); val 86 drivers/thermal/qoriq_thermal.c iowrite32be(val, addr); val 101 drivers/thermal/qoriq_thermal.c u32 val; val 103 drivers/thermal/qoriq_thermal.c val = tmu_read(qdata, &qdata->regs->site[qsensor->id].tritsr); val 104 drivers/thermal/qoriq_thermal.c *temp = (val & 0xff) * 1000; val 147 drivers/thermal/qoriq_thermal.c int i, val, len; val 171 drivers/thermal/qoriq_thermal.c val = of_read_number(calibration, 1); val 172 drivers/thermal/qoriq_thermal.c tmu_write(data, val, &data->regs->ttcfgr); val 173 drivers/thermal/qoriq_thermal.c val = of_read_number(calibration + 1, 1); val 174 drivers/thermal/qoriq_thermal.c tmu_write(data, val, &data->regs->tscfgr); val 171 drivers/thermal/rcar_gen3_thermal.c int mcelsius, val; val 178 drivers/thermal/rcar_gen3_thermal.c val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1, val 181 drivers/thermal/rcar_gen3_thermal.c val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b2, val 183 drivers/thermal/rcar_gen3_thermal.c mcelsius = FIXPT_TO_MCELSIUS(val); val 198 drivers/thermal/rcar_gen3_thermal.c int celsius, val; val 202 drivers/thermal/rcar_gen3_thermal.c val = celsius * tsc->coef.a1 + tsc->coef.b1; val 204 drivers/thermal/rcar_gen3_thermal.c val = celsius * tsc->coef.a2 + tsc->coef.b2; val 206 drivers/thermal/rcar_gen3_thermal.c return INT_FIXPT(val); val 236 drivers/thermal/rcar_gen3_thermal.c u32 val = on ? IRQ_TEMPD1 | IRQ_TEMP2 : 0; val 239 drivers/thermal/rcar_gen3_thermal.c rcar_gen3_thermal_write(priv->tscs[i], REG_GEN3_IRQMSK, val); val 163 drivers/thermal/rcar_thermal.c u32 val; val 165 drivers/thermal/rcar_thermal.c val = ioread32(common->base + reg); val 166 drivers/thermal/rcar_thermal.c val &= ~mask; val 167 drivers/thermal/rcar_thermal.c val |= (data & mask); val 168 drivers/thermal/rcar_thermal.c iowrite32(val, common->base + reg); val 188 drivers/thermal/rcar_thermal.c u32 val; val 190 drivers/thermal/rcar_thermal.c val = ioread32(priv->base + reg); val 191 drivers/thermal/rcar_thermal.c val &= ~mask; val 192 drivers/thermal/rcar_thermal.c val |= (data & mask); val 193 drivers/thermal/rcar_thermal.c iowrite32(val, priv->base + reg); val 697 drivers/thermal/rockchip_thermal.c u32 val; val 699 drivers/thermal/rockchip_thermal.c val = readl_relaxed(regs + TSADCV2_INT_PD); val 700 drivers/thermal/rockchip_thermal.c writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); val 705 drivers/thermal/rockchip_thermal.c u32 val; val 707 drivers/thermal/rockchip_thermal.c val = readl_relaxed(regs + TSADCV2_INT_PD); val 708 drivers/thermal/rockchip_thermal.c writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); val 713 drivers/thermal/rockchip_thermal.c u32 val; val 715 drivers/thermal/rockchip_thermal.c val = readl_relaxed(regs + TSADCV2_AUTO_CON); val 717 drivers/thermal/rockchip_thermal.c val |= TSADCV2_AUTO_EN; val 719 drivers/thermal/rockchip_thermal.c val &= ~TSADCV2_AUTO_EN; val 721 drivers/thermal/rockchip_thermal.c writel_relaxed(val, regs + TSADCV2_AUTO_CON); val 733 drivers/thermal/rockchip_thermal.c u32 val; val 735 drivers/thermal/rockchip_thermal.c val = readl_relaxed(regs + TSADCV2_AUTO_CON); val 737 drivers/thermal/rockchip_thermal.c val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; val 739 drivers/thermal/rockchip_thermal.c val &= ~TSADCV2_AUTO_EN; val 741 drivers/thermal/rockchip_thermal.c writel_relaxed(val, regs + TSADCV2_AUTO_CON); val 747 drivers/thermal/rockchip_thermal.c u32 val; val 749 drivers/thermal/rockchip_thermal.c val = readl_relaxed(regs + TSADCV2_DATA(chn)); val 751 drivers/thermal/rockchip_thermal.c return rk_tsadcv2_code_to_temp(table, val, temp); val 791 drivers/thermal/rockchip_thermal.c u32 tshut_value, val; val 801 drivers/thermal/rockchip_thermal.c val = readl_relaxed(regs + TSADCV2_AUTO_CON); val 802 drivers/thermal/rockchip_thermal.c writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); val 810 drivers/thermal/rockchip_thermal.c u32 val; val 812 drivers/thermal/rockchip_thermal.c val = readl_relaxed(regs + TSADCV2_INT_EN); val 814 drivers/thermal/rockchip_thermal.c val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); val 815 drivers/thermal/rockchip_thermal.c val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); val 817 drivers/thermal/rockchip_thermal.c val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); val 818 drivers/thermal/rockchip_thermal.c val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); val 821 drivers/thermal/rockchip_thermal.c writel_relaxed(val, regs + TSADCV2_INT_EN); val 680 drivers/thermal/samsung/exynos_tmu.c static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, val 686 drivers/thermal/samsung/exynos_tmu.c val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); val 687 drivers/thermal/samsung/exynos_tmu.c val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); val 689 drivers/thermal/samsung/exynos_tmu.c val &= ~(EXYNOS7_EMUL_DATA_MASK << val 691 drivers/thermal/samsung/exynos_tmu.c val |= (temp_to_code(data, temp) << val 695 drivers/thermal/samsung/exynos_tmu.c val &= ~(EXYNOS_EMUL_DATA_MASK << val 697 drivers/thermal/samsung/exynos_tmu.c val |= (temp_to_code(data, temp) << val 702 drivers/thermal/samsung/exynos_tmu.c val &= ~EXYNOS_EMUL_ENABLE; val 705 drivers/thermal/samsung/exynos_tmu.c return val; val 711 drivers/thermal/samsung/exynos_tmu.c unsigned int val; val 723 drivers/thermal/samsung/exynos_tmu.c val = readl(data->base + emul_con); val 724 drivers/thermal/samsung/exynos_tmu.c val = get_emul_con_reg(data, val, temp); val 725 drivers/thermal/samsung/exynos_tmu.c writel(val, data->base + emul_con); val 95 drivers/thermal/spear_thermal.c int ret = 0, val; val 97 drivers/thermal/spear_thermal.c if (!np || !of_property_read_u32(np, "st,thermal-flags", &val)) { val 124 drivers/thermal/spear_thermal.c stdev->flags = val; val 84 drivers/thermal/st/st_thermal.c unsigned int val; val 88 drivers/thermal/st/st_thermal.c ret = regmap_field_read(sensor->dcorrect, &val); val 94 drivers/thermal/st/st_thermal.c if (!val) { val 52 drivers/thermal/st/st_thermal_memmap.c const unsigned int val = power_state ? mask : 0; val 54 drivers/thermal/st/st_thermal_memmap.c return regmap_update_bits(sensor->regmap, STIH416_MPE_CONF, mask, val); val 76 drivers/thermal/tegra/soctherm-fuse.c u32 val; val 80 drivers/thermal/tegra/soctherm-fuse.c err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val); val 84 drivers/thermal/tegra/soctherm-fuse.c shared->base_cp = (val & tfuse->fuse_base_cp_mask) >> val 86 drivers/thermal/tegra/soctherm-fuse.c shared->base_ft = (val & tfuse->fuse_base_ft_mask) >> val 89 drivers/thermal/tegra/soctherm-fuse.c shifted_ft = (val & tfuse->fuse_shift_ft_mask) >> val 94 drivers/thermal/tegra/soctherm-fuse.c err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val); val 99 drivers/thermal/tegra/soctherm-fuse.c shifted_cp = sign_extend32(val, 5); val 112 drivers/thermal/tegra/soctherm-fuse.c u32 val, calib; val 122 drivers/thermal/tegra/soctherm-fuse.c err = tegra_fuse_readl(sensor->calib_fuse_offset, &val); val 126 drivers/thermal/tegra/soctherm-fuse.c actual_tsensor_cp = (shared->base_cp * 64) + sign_extend32(val, 12); val 127 drivers/thermal/tegra/soctherm-fuse.c val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK) >> val 129 drivers/thermal/tegra/soctherm-fuse.c actual_tsensor_ft = (shared->base_ft * 32) + sign_extend32(val, 12); val 389 drivers/thermal/tegra/soctherm.c unsigned int val; val 391 drivers/thermal/tegra/soctherm.c val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT; val 392 drivers/thermal/tegra/soctherm.c writel(val, base + SENSOR_CONFIG0); val 394 drivers/thermal/tegra/soctherm.c val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT; val 395 drivers/thermal/tegra/soctherm.c val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT; val 396 drivers/thermal/tegra/soctherm.c val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT; val 397 drivers/thermal/tegra/soctherm.c val |= SENSOR_CONFIG1_TEMP_ENABLE; val 398 drivers/thermal/tegra/soctherm.c writel(val, base + SENSOR_CONFIG1); val 411 drivers/thermal/tegra/soctherm.c static int translate_temp(u16 val) val 415 drivers/thermal/tegra/soctherm.c t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000; val 416 drivers/thermal/tegra/soctherm.c if (val & READBACK_ADD_HALF) val 418 drivers/thermal/tegra/soctherm.c if (val & READBACK_NEGATE) val 427 drivers/thermal/tegra/soctherm.c u32 val; val 429 drivers/thermal/tegra/soctherm.c val = readl(zone->reg); val 430 drivers/thermal/tegra/soctherm.c val = REG_GET_MASK(val, zone->sg->sensor_temp_mask); val 431 drivers/thermal/tegra/soctherm.c *out_temp = translate_temp(val); val 1615 drivers/thermal/tegra/soctherm.c u32 val; val 1622 drivers/thermal/tegra/soctherm.c if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) { val 1624 drivers/thermal/tegra/soctherm.c stc->oc_cfg.alarm_cnt_thresh = val; val 1627 drivers/thermal/tegra/soctherm.c if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val)) val 1628 drivers/thermal/tegra/soctherm.c stc->oc_cfg.throt_period = val; val 1630 drivers/thermal/tegra/soctherm.c if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val)) val 1631 drivers/thermal/tegra/soctherm.c stc->oc_cfg.alarm_filter = val; val 1643 drivers/thermal/tegra/soctherm.c u32 val; val 1645 drivers/thermal/tegra/soctherm.c ret = of_property_read_u32(np, "nvidia,priority", &val); val 1650 drivers/thermal/tegra/soctherm.c stc->priority = val; val 1654 drivers/thermal/tegra/soctherm.c "nvidia,cpu-throt-percent", &val); val 1657 drivers/thermal/tegra/soctherm.c val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH) val 1658 drivers/thermal/tegra/soctherm.c stc->cpu_throt_level = val; val 1659 drivers/thermal/tegra/soctherm.c else if (!ts->soc->use_ccroc && val <= 100) val 1660 drivers/thermal/tegra/soctherm.c stc->cpu_throt_depth = val; val 1667 drivers/thermal/tegra/soctherm.c ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val); val 1668 drivers/thermal/tegra/soctherm.c if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH) val 1669 drivers/thermal/tegra/soctherm.c stc->gpu_throt_level = val; val 24 drivers/thermal/thermal-generic-adc.c static int gadc_thermal_adc_to_temp(struct gadc_thermal_info *gti, int val) val 30 drivers/thermal/thermal-generic-adc.c return val; val 33 drivers/thermal/thermal-generic-adc.c if (val >= gti->lookup_table[2 * i + 1]) val 48 drivers/thermal/thermal-generic-adc.c temp = temp_hi + mult_frac(temp_lo - temp_hi, val - adc_hi, val 58 drivers/thermal/thermal-generic-adc.c int val; val 61 drivers/thermal/thermal-generic-adc.c ret = iio_read_channel_processed(gti->channel, &val); val 66 drivers/thermal/thermal-generic-adc.c *temp = gadc_thermal_adc_to_temp(gti, val); val 57 drivers/thermal/ti-soc-thermal/ti-bandgap.c static void ti_bandgap_writel(struct ti_bandgap *bgp, u32 val, u32 reg) val 59 drivers/thermal/ti-soc-thermal/ti-bandgap.c writel(val, bgp->base + reg); val 68 drivers/thermal/ti-soc-thermal/ti-bandgap.c #define RMW_BITS(bgp, id, reg, mask, val) \ val 76 drivers/thermal/ti-soc-thermal/ti-bandgap.c r |= (val) << __ffs(t->mask); \ val 918 drivers/thermal/ti-soc-thermal/ti-bandgap.c u32 val; val 926 drivers/thermal/ti-soc-thermal/ti-bandgap.c val = ti_bandgap_readl(bgp, tsr->bgap_efuse); val 927 drivers/thermal/ti-soc-thermal/ti-bandgap.c if (!val) val 1130 drivers/thermal/ti-soc-thermal/ti-bandgap.c u32 val = 0; val 1136 drivers/thermal/ti-soc-thermal/ti-bandgap.c val = ti_bandgap_readl(bgp, tsr->bgap_counter); val 330 drivers/thermal/ti-soc-thermal/ti-bandgap.h int ti_bandgap_write_thot(struct ti_bandgap *bgp, int id, int val); val 332 drivers/thermal/ti-soc-thermal/ti-bandgap.h int ti_bandgap_write_tcold(struct ti_bandgap *bgp, int id, int val); val 50 drivers/thermal/uniphier_thermal.c #define SETALERT_TEMP_OVF_VALUE(val) (((val) & GENMASK(7, 0)) << 16) val 66 drivers/thermal/uniphier_thermal.c #define TMODSETUP0_VAL(val) (((val) & GENMASK(13, 0)) << 16) val 68 drivers/thermal/uniphier_thermal.c #define TMODSETUP1_VAL(val) ((val) & GENMASK(14, 0)) val 94 drivers/thermal/uniphier_thermal.c u32 val; val 109 drivers/thermal/uniphier_thermal.c ret = regmap_read(map, tdev->data->map_base + TMODCOEF, &val); val 112 drivers/thermal/uniphier_thermal.c if (!val) { val 63 drivers/thermal/zx2967_thermal.c u32 val; val 75 drivers/thermal/zx2967_thermal.c val = readl_relaxed(regs + ZX2967_THERMAL_SEL); val 76 drivers/thermal/zx2967_thermal.c val &= ~ZX2967_THERMAL_ID_MASK; val 77 drivers/thermal/zx2967_thermal.c val |= ZX2967_THERMAL_ID; val 78 drivers/thermal/zx2967_thermal.c writel_relaxed(val, regs + ZX2967_THERMAL_SEL); val 87 drivers/thermal/zx2967_thermal.c val, val & ZX2967_THERMAL_READY, 300, val 96 drivers/thermal/zx2967_thermal.c val = readl_relaxed(regs + ZX2967_THERMAL_CTRL) val 105 drivers/thermal/zx2967_thermal.c *temp = DIV_ROUND_CLOSEST(((s32)val + priv->tzd->tzp->offset) * 1000, val 95 drivers/thunderbolt/eeprom.c static int tb_eeprom_out(struct tb_switch *sw, u8 val) val 103 drivers/thunderbolt/eeprom.c ctl.data_out = val & 0x80; val 107 drivers/thunderbolt/eeprom.c val <<= 1; val 115 drivers/thunderbolt/eeprom.c static int tb_eeprom_in(struct tb_switch *sw, u8 *val) val 122 drivers/thunderbolt/eeprom.c *val = 0; val 124 drivers/thunderbolt/eeprom.c *val <<= 1; val 128 drivers/thunderbolt/eeprom.c *val |= ctl.data_in; val 136 drivers/thunderbolt/eeprom.c static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val, val 153 drivers/thunderbolt/eeprom.c res = tb_eeprom_in(sw, val + i); val 163 drivers/thunderbolt/eeprom.c u8 val = 0xff; val 165 drivers/thunderbolt/eeprom.c val ^= data[i]; val 167 drivers/thunderbolt/eeprom.c val = (val << 1) ^ ((val & 0x80) ? 7 : 0); val 169 drivers/thunderbolt/eeprom.c return val; val 1386 drivers/thunderbolt/icm.c u32 val; val 1389 drivers/thunderbolt/icm.c val = ioread32(nhi->iobase + REG_FW_STS); val 1390 drivers/thunderbolt/icm.c if (val & REG_FW_STS_NVM_AUTH_DONE) val 1680 drivers/thunderbolt/icm.c u32 val; val 1686 drivers/thunderbolt/icm.c val = ioread32(nhi->iobase + REG_FW_STS); val 1687 drivers/thunderbolt/icm.c val |= REG_FW_STS_CIO_RESET_REQ; val 1688 drivers/thunderbolt/icm.c iowrite32(val, nhi->iobase + REG_FW_STS); val 1691 drivers/thunderbolt/icm.c val = ioread32(nhi->iobase + REG_FW_STS); val 1692 drivers/thunderbolt/icm.c val |= REG_FW_STS_ICM_EN_INVERT; val 1693 drivers/thunderbolt/icm.c val |= REG_FW_STS_ICM_EN_CPU; val 1694 drivers/thunderbolt/icm.c iowrite32(val, nhi->iobase + REG_FW_STS); val 1704 drivers/thunderbolt/icm.c u32 val; val 1707 drivers/thunderbolt/icm.c val = ioread32(nhi->iobase + REG_FW_STS); val 1708 drivers/thunderbolt/icm.c if (val & REG_FW_STS_ICM_EN) val 1720 drivers/thunderbolt/icm.c val = ioread32(nhi->iobase + REG_FW_STS); val 1721 drivers/thunderbolt/icm.c if (val & REG_FW_STS_NVM_AUTH_DONE) val 341 drivers/thunderbolt/nhi.c u32 val; val 343 drivers/thunderbolt/nhi.c val = ioread32(ring->nhi->iobase + reg); val 345 drivers/thunderbolt/nhi.c val &= ~BIT(bit); val 347 drivers/thunderbolt/nhi.c val |= BIT(bit); val 348 drivers/thunderbolt/nhi.c iowrite32(val, ring->nhi->iobase + reg); val 761 drivers/thunderbolt/nhi.c u32 val; val 765 drivers/thunderbolt/nhi.c val = ioread32(nhi->iobase + REG_INMAIL_CMD); val 766 drivers/thunderbolt/nhi.c val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR); val 767 drivers/thunderbolt/nhi.c val |= REG_INMAIL_OP_REQUEST | cmd; val 768 drivers/thunderbolt/nhi.c iowrite32(val, nhi->iobase + REG_INMAIL_CMD); val 772 drivers/thunderbolt/nhi.c val = ioread32(nhi->iobase + REG_INMAIL_CMD); val 773 drivers/thunderbolt/nhi.c if (!(val & REG_INMAIL_OP_REQUEST)) val 778 drivers/thunderbolt/nhi.c if (val & REG_INMAIL_OP_REQUEST) val 780 drivers/thunderbolt/nhi.c if (val & REG_INMAIL_ERROR) val 795 drivers/thunderbolt/nhi.c u32 val; val 797 drivers/thunderbolt/nhi.c val = ioread32(nhi->iobase + REG_OUTMAIL_CMD); val 798 drivers/thunderbolt/nhi.c val &= REG_OUTMAIL_CMD_OPMODE_MASK; val 799 drivers/thunderbolt/nhi.c val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT; val 801 drivers/thunderbolt/nhi.c return (enum nhi_fw_mode)val; val 890 drivers/thunderbolt/nhi.c u8 val; val 896 drivers/thunderbolt/nhi.c if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val)) val 897 drivers/thunderbolt/nhi.c return !!val; val 1086 drivers/thunderbolt/nhi.c u8 val; val 1088 drivers/thunderbolt/nhi.c if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val)) val 1089 drivers/thunderbolt/nhi.c return !!val; val 63 drivers/thunderbolt/nhi_ops.c u32 val; val 67 drivers/thunderbolt/nhi_ops.c pci_read_config_dword(nhi->pdev, VS_CAP_9, &val); val 68 drivers/thunderbolt/nhi_ops.c if (val & VS_CAP_9_FW_READY) val 254 drivers/thunderbolt/switch.c static int tb_switch_nvm_read(void *priv, unsigned int offset, void *val, val 267 drivers/thunderbolt/switch.c ret = dma_port_flash_read(sw->dma_port, offset, val, bytes); val 277 drivers/thunderbolt/switch.c static int tb_switch_nvm_no_read(void *priv, unsigned int offset, void *val, val 283 drivers/thunderbolt/switch.c static int tb_switch_nvm_write(void *priv, unsigned int offset, void *val, val 307 drivers/thunderbolt/switch.c memcpy(sw->nvm->buf + offset, val, bytes); val 348 drivers/thunderbolt/switch.c u32 val; val 368 drivers/thunderbolt/switch.c ret = dma_port_flash_read(sw->dma_port, NVM_FLASH_SIZE, &val, val 369 drivers/thunderbolt/switch.c sizeof(val)); val 374 drivers/thunderbolt/switch.c nvm_size = (SZ_1M << (val & 7)) / 8; val 377 drivers/thunderbolt/switch.c ret = dma_port_flash_read(sw->dma_port, NVM_VERSION, &val, val 378 drivers/thunderbolt/switch.c sizeof(val)); val 382 drivers/thunderbolt/switch.c nvm->major = val >> 16; val 383 drivers/thunderbolt/switch.c nvm->minor = val >> 8; val 1053 drivers/thunderbolt/switch.c static int tb_switch_set_authorized(struct tb_switch *sw, unsigned int val) val 1063 drivers/thunderbolt/switch.c switch (val) { val 1083 drivers/thunderbolt/switch.c sw->authorized = val; val 1098 drivers/thunderbolt/switch.c unsigned int val; val 1101 drivers/thunderbolt/switch.c ret = kstrtouint(buf, 0, &val); val 1104 drivers/thunderbolt/switch.c if (val > 2) val 1108 drivers/thunderbolt/switch.c ret = tb_switch_set_authorized(sw, val); val 1233 drivers/thunderbolt/switch.c bool val; val 1249 drivers/thunderbolt/switch.c ret = kstrtobool(buf, &val); val 1256 drivers/thunderbolt/switch.c if (val) { val 293 drivers/tty/cyclades.c static void cyy_writeb(struct cyclades_port *port, u32 reg, u8 val) val 297 drivers/tty/cyclades.c cy_writeb(port->u.cyy.base_addr + (reg << card->bus_index), val); val 1229 drivers/tty/hvc/hvc_iucv.c static int hvc_iucv_setup_filter(const char *val) val 1236 drivers/tty/hvc/hvc_iucv.c count = strlen(val); val 1237 drivers/tty/hvc/hvc_iucv.c if (count == 0 || (count == 1 && val[0] == '\n')) { val 1245 drivers/tty/hvc/hvc_iucv.c residual = val; val 1260 drivers/tty/hvc/hvc_iucv.c residual = val; val 1295 drivers/tty/hvc/hvc_iucv.c static int param_set_vmidfilter(const char *val, const struct kernel_param *kp) val 1302 drivers/tty/hvc/hvc_iucv.c if (!val) val 1307 drivers/tty/hvc/hvc_iucv.c rc = hvc_iucv_setup_filter(val); val 1309 drivers/tty/hvc/hvc_iucv.c hvc_iucv_filter_string = val; /* defer... */ val 1471 drivers/tty/hvc/hvc_iucv.c static int __init hvc_iucv_config(char *val) val 1473 drivers/tty/hvc/hvc_iucv.c return kstrtoul(val, 10, &hvc_iucv_devices); val 160 drivers/tty/ipwireless/network.c int err, val; val 167 drivers/tty/ipwireless/network.c val = network->flags | network->rbits; val 168 drivers/tty/ipwireless/network.c if (put_user(val, user_arg)) val 174 drivers/tty/ipwireless/network.c if (get_user(val, user_arg)) val 176 drivers/tty/ipwireless/network.c network->flags = val & ~SC_RCV_BITS; val 177 drivers/tty/ipwireless/network.c network->rbits = val & SC_RCV_BITS; val 228 drivers/tty/ipwireless/network.c if (get_user(val, user_arg)) val 230 drivers/tty/ipwireless/network.c if (val < PPP_MRU) val 231 drivers/tty/ipwireless/network.c val = PPP_MRU; val 232 drivers/tty/ipwireless/network.c network->mru = val; val 424 drivers/tty/ipwireless/tty.c int val = 0; val 426 drivers/tty/ipwireless/tty.c if (put_user(val, (int __user *) arg)) val 1732 drivers/tty/moxa.c unsigned int clock, val; val 1741 drivers/tty/moxa.c val = clock / baud; val 1742 drivers/tty/moxa.c moxafunc(ofsAddr, FC_SetBaud, val); val 1743 drivers/tty/moxa.c baud = clock / val; val 1851 drivers/tty/moxa.c int val; val 1855 drivers/tty/moxa.c val = moxafuncret(ofsAddr, FC_LineStatus, 0); val 1857 drivers/tty/moxa.c val = readw(ofsAddr + FlagStat) >> 4; val 1858 drivers/tty/moxa.c val &= 0x0B; val 1859 drivers/tty/moxa.c if (val & 8) val 1860 drivers/tty/moxa.c val |= 4; val 1861 drivers/tty/moxa.c moxa_new_dcdstate(port, val & 8); val 1862 drivers/tty/moxa.c val &= 7; val 1863 drivers/tty/moxa.c return val; val 1690 drivers/tty/mxser.c unsigned char val, mask; val 1707 drivers/tty/mxser.c val = inb(info->opmode_ioaddr); val 1708 drivers/tty/mxser.c val &= mask; val 1709 drivers/tty/mxser.c val |= (opmode << shiftbit); val 1710 drivers/tty/mxser.c outb(val, info->opmode_ioaddr); val 401 drivers/tty/n_gsm.c static int gsm_read_ea(unsigned int *val, u8 c) val 404 drivers/tty/n_gsm.c *val <<= 7; val 405 drivers/tty/n_gsm.c *val |= c >> 1; val 162 drivers/tty/pty.c int val; val 163 drivers/tty/pty.c if (get_user(val, arg)) val 165 drivers/tty/pty.c if (val) val 3076 drivers/tty/rocket.c Byte_t val; val 3079 drivers/tty/rocket.c val = sInB(CtlP->MReg3IO); val 3081 drivers/tty/rocket.c if ((val & 2) == 0) { val 3082 drivers/tty/rocket.c val = sInB(CtlP->MReg2IO); val 3083 drivers/tty/rocket.c sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03)); val 81 drivers/tty/serial/8250/8250_aspeed_vuart.c unsigned long val; val 84 drivers/tty/serial/8250/8250_aspeed_vuart.c err = kstrtoul(buf, 0, &val); val 88 drivers/tty/serial/8250/8250_aspeed_vuart.c writeb(val >> 8, vuart->regs + ASPEED_VUART_ADDRH); val 89 drivers/tty/serial/8250/8250_aspeed_vuart.c writeb(val >> 0, vuart->regs + ASPEED_VUART_ADDRL); val 113 drivers/tty/serial/8250/8250_aspeed_vuart.c unsigned long val; val 117 drivers/tty/serial/8250/8250_aspeed_vuart.c err = kstrtoul(buf, 0, &val); val 121 drivers/tty/serial/8250/8250_aspeed_vuart.c val <<= ASPEED_VUART_GCRB_HOST_SIRQ_SHIFT; val 122 drivers/tty/serial/8250/8250_aspeed_vuart.c val &= ASPEED_VUART_GCRB_HOST_SIRQ_MASK; val 126 drivers/tty/serial/8250/8250_aspeed_vuart.c reg |= val; val 394 drivers/tty/serial/8250/8250_dw.c u32 val; val 434 drivers/tty/serial/8250/8250_dw.c err = device_property_read_u32(dev, "reg-shift", &val); val 436 drivers/tty/serial/8250/8250_dw.c p->regshift = val; val 438 drivers/tty/serial/8250/8250_dw.c err = device_property_read_u32(dev, "reg-io-width", &val); val 439 drivers/tty/serial/8250/8250_dw.c if (!err && val == 4) { val 1359 drivers/tty/serial/8250/8250_omap.c u32 val; val 1361 drivers/tty/serial/8250/8250_omap.c val = serial_in(up, UART_OMAP_SCR); val 1367 drivers/tty/serial/8250/8250_omap.c if (!val) val 1136 drivers/tty/serial/8250/8250_pci.c u8 LCR, val; val 1140 drivers/tty/serial/8250/8250_pci.c val = inb(base + UART_SCR); val 1142 drivers/tty/serial/8250/8250_pci.c return val; val 1160 drivers/tty/serial/8250/8250_pci.c u8 LCR, val, qmcr; val 1164 drivers/tty/serial/8250/8250_pci.c val = inb(base + UART_SCR); val 1165 drivers/tty/serial/8250/8250_pci.c outb(val | 0x10, base + UART_SCR); val 1167 drivers/tty/serial/8250/8250_pci.c outb(val, base + UART_SCR); val 1176 drivers/tty/serial/8250/8250_pci.c u8 LCR, val; val 1180 drivers/tty/serial/8250/8250_pci.c val = inb(base + UART_SCR); val 1181 drivers/tty/serial/8250/8250_pci.c outb(val | 0x10, base + UART_SCR); val 1183 drivers/tty/serial/8250/8250_pci.c outb(val, base + UART_SCR); val 1190 drivers/tty/serial/8250/8250_pci.c u8 LCR, val; val 1194 drivers/tty/serial/8250/8250_pci.c val = inb(base + UART_SCR); val 1195 drivers/tty/serial/8250/8250_pci.c if (val & 0x20) { val 1712 drivers/tty/serial/8250/8250_pci.c unsigned int val; val 1724 drivers/tty/serial/8250/8250_pci.c val = inb(p->iobase + offset); val 1726 drivers/tty/serial/8250/8250_pci.c if (val == 0) val 1727 drivers/tty/serial/8250/8250_pci.c val = up->ier; val 1729 drivers/tty/serial/8250/8250_pci.c return val; val 1902 drivers/tty/serial/8250/8250_port.c unsigned int val; val 1908 drivers/tty/serial/8250/8250_port.c val = serial8250_MSR_to_TIOCM(status); val 1910 drivers/tty/serial/8250/8250_port.c return mctrl_gpio_get(up->gpios, &val); val 1912 drivers/tty/serial/8250/8250_port.c return val; val 115 drivers/tty/serial/8250/serial_cs.c u8 val; val 118 drivers/tty/serial/8250/serial_cs.c ret = pcmcia_read_config_byte(link, 0x800, &val); val 122 drivers/tty/serial/8250/serial_cs.c ret = pcmcia_write_config_byte(link, 0x800, val | 1); val 298 drivers/tty/serial/amba-pl011.c static void pl011_write(unsigned int val, const struct uart_amba_port *uap, val 304 drivers/tty/serial/amba-pl011.c writel_relaxed(val, addr); val 306 drivers/tty/serial/amba-pl011.c writew_relaxed(val, addr); val 1823 drivers/tty/serial/amba-pl011.c unsigned long val; val 1825 drivers/tty/serial/amba-pl011.c val = pl011_read(uap, lcrh); val 1826 drivers/tty/serial/amba-pl011.c val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); val 1827 drivers/tty/serial/amba-pl011.c pl011_write(val, uap, lcrh); val 67 drivers/tty/serial/ar933x_uart.c unsigned int val) val 73 drivers/tty/serial/ar933x_uart.c t |= val; val 79 drivers/tty/serial/ar933x_uart.c unsigned int val) val 81 drivers/tty/serial/ar933x_uart.c ar933x_uart_rmw(up, offset, 0, val); val 86 drivers/tty/serial/ar933x_uart.c unsigned int val) val 88 drivers/tty/serial/ar933x_uart.c ar933x_uart_rmw(up, offset, val, 0); val 80 drivers/tty/serial/arc_uart.c #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val) val 83 drivers/tty/serial/arc_uart.c #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val) val 84 drivers/tty/serial/arc_uart.c #define UART_SET_BAUDL(uart, val) UART_REG_SET(uart, R_BAUDL, val) val 86 drivers/tty/serial/arc_uart.c #define UART_CLR_STATUS(uart, val) UART_REG_CLR(uart, R_STS, val) val 586 drivers/tty/serial/arc_uart.c u32 val; val 604 drivers/tty/serial/arc_uart.c if (of_property_read_u32(np, "clock-frequency", &val)) { val 608 drivers/tty/serial/arc_uart.c port->uartclk = val; val 610 drivers/tty/serial/arc_uart.c if (of_property_read_u32(np, "current-speed", &val)) { val 614 drivers/tty/serial/arc_uart.c uart->baud = val; val 94 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 96 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_IR_REG); val 97 drivers/tty/serial/bcm63xx_uart.c return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0; val 105 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 107 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_MCTL_REG); val 108 drivers/tty/serial/bcm63xx_uart.c val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK); val 111 drivers/tty/serial/bcm63xx_uart.c val |= UART_MCTL_DTR_MASK; val 113 drivers/tty/serial/bcm63xx_uart.c val |= UART_MCTL_RTS_MASK; val 114 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_MCTL_REG); val 116 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 118 drivers/tty/serial/bcm63xx_uart.c val |= UART_CTL_LOOPBACK_MASK; val 120 drivers/tty/serial/bcm63xx_uart.c val &= ~UART_CTL_LOOPBACK_MASK; val 121 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 129 drivers/tty/serial/bcm63xx_uart.c unsigned int val, mctrl; val 132 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_EXTINP_REG); val 133 drivers/tty/serial/bcm63xx_uart.c if (val & UART_EXTINP_RI_MASK) val 135 drivers/tty/serial/bcm63xx_uart.c if (val & UART_EXTINP_CTS_MASK) val 137 drivers/tty/serial/bcm63xx_uart.c if (val & UART_EXTINP_DCD_MASK) val 139 drivers/tty/serial/bcm63xx_uart.c if (val & UART_EXTINP_DSR_MASK) val 149 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 151 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 152 drivers/tty/serial/bcm63xx_uart.c val &= ~(UART_CTL_TXEN_MASK); val 153 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 155 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_IR_REG); val 156 drivers/tty/serial/bcm63xx_uart.c val &= ~UART_TX_INT_MASK; val 157 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_IR_REG); val 165 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 167 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_IR_REG); val 168 drivers/tty/serial/bcm63xx_uart.c val |= UART_TX_INT_MASK; val 169 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_IR_REG); val 171 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 172 drivers/tty/serial/bcm63xx_uart.c val |= UART_CTL_TXEN_MASK; val 173 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 181 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 183 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_IR_REG); val 184 drivers/tty/serial/bcm63xx_uart.c val &= ~UART_RX_INT_MASK; val 185 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_IR_REG); val 193 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 195 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_IR_REG); val 196 drivers/tty/serial/bcm63xx_uart.c val |= UART_IR_MASK(UART_IR_EXTIP); val 197 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_IR_REG); val 206 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 210 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 212 drivers/tty/serial/bcm63xx_uart.c val |= UART_CTL_XMITBRK_MASK; val 214 drivers/tty/serial/bcm63xx_uart.c val &= ~UART_CTL_XMITBRK_MASK; val 215 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 249 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 253 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 254 drivers/tty/serial/bcm63xx_uart.c val |= UART_CTL_RSTRXFIFO_MASK; val 255 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 313 drivers/tty/serial/bcm63xx_uart.c unsigned int val, max_count; val 331 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_MCTL_REG); val 332 drivers/tty/serial/bcm63xx_uart.c val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT; val 333 drivers/tty/serial/bcm63xx_uart.c max_count = port->fifosize - val; val 355 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_IR_REG); val 356 drivers/tty/serial/bcm63xx_uart.c val &= ~UART_TX_INT_MASK; val 357 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_IR_REG); val 400 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 402 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 403 drivers/tty/serial/bcm63xx_uart.c val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); val 404 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 412 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 414 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 415 drivers/tty/serial/bcm63xx_uart.c val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | val 417 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 425 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 428 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 429 drivers/tty/serial/bcm63xx_uart.c val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK; val 430 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 442 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 454 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_MCTL_REG); val 455 drivers/tty/serial/bcm63xx_uart.c val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK); val 456 drivers/tty/serial/bcm63xx_uart.c val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT; val 457 drivers/tty/serial/bcm63xx_uart.c val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT; val 458 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_MCTL_REG); val 461 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_CTL_REG); val 462 drivers/tty/serial/bcm63xx_uart.c val &= ~UART_CTL_RXTMOUTCNT_MASK; val 463 drivers/tty/serial/bcm63xx_uart.c val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT; val 464 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_CTL_REG); val 467 drivers/tty/serial/bcm63xx_uart.c val = UART_EXTINP_INT_MASK; val 468 drivers/tty/serial/bcm63xx_uart.c val |= UART_EXTINP_DCD_NOSENSE_MASK; val 469 drivers/tty/serial/bcm63xx_uart.c val |= UART_EXTINP_CTS_NOSENSE_MASK; val 470 drivers/tty/serial/bcm63xx_uart.c bcm_uart_writel(port, val, UART_EXTINP_REG); val 665 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 667 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_IR_REG); val 668 drivers/tty/serial/bcm63xx_uart.c if (val & UART_IR_STAT(UART_IR_TXEMPTY)) val 677 drivers/tty/serial/bcm63xx_uart.c unsigned int val; val 679 drivers/tty/serial/bcm63xx_uart.c val = bcm_uart_readl(port, UART_EXTINP_REG); val 680 drivers/tty/serial/bcm63xx_uart.c if (val & UART_EXTINP_CTS_MASK) val 112 drivers/tty/serial/cpm_uart/cpm_uart.h u32 val = (u32)addr; val 115 drivers/tty/serial/cpm_uart/cpm_uart.h if (likely(val >= mem && val < mem + pinfo->mem_size)) { val 116 drivers/tty/serial/cpm_uart/cpm_uart.h offset = val - mem; val 128 drivers/tty/serial/cpm_uart/cpm_uart.h u32 val = addr; val 131 drivers/tty/serial/cpm_uart/cpm_uart.h if (likely(val >= dma && val < dma + pinfo->mem_size)) { val 132 drivers/tty/serial/cpm_uart/cpm_uart.h offset = val - dma; val 237 drivers/tty/serial/earlycon.c const __be32 *val; val 250 drivers/tty/serial/earlycon.c val = of_get_flat_dt_prop(node, "reg-offset", NULL); val 251 drivers/tty/serial/earlycon.c if (val) val 252 drivers/tty/serial/earlycon.c port->mapbase += be32_to_cpu(*val); val 255 drivers/tty/serial/earlycon.c val = of_get_flat_dt_prop(node, "reg-shift", NULL); val 256 drivers/tty/serial/earlycon.c if (val) val 257 drivers/tty/serial/earlycon.c port->regshift = be32_to_cpu(*val); val 261 drivers/tty/serial/earlycon.c val = of_get_flat_dt_prop(node, "reg-io-width", NULL); val 262 drivers/tty/serial/earlycon.c if (val) { val 263 drivers/tty/serial/earlycon.c switch (be32_to_cpu(*val)) { val 279 drivers/tty/serial/earlycon.c val = of_get_flat_dt_prop(node, "current-speed", NULL); val 280 drivers/tty/serial/earlycon.c if (val) val 281 drivers/tty/serial/earlycon.c early_console_dev.baud = be32_to_cpu(*val); val 283 drivers/tty/serial/earlycon.c val = of_get_flat_dt_prop(node, "clock-frequency", NULL); val 284 drivers/tty/serial/earlycon.c if (val) val 285 drivers/tty/serial/earlycon.c port->uartclk = be32_to_cpu(*val); val 331 drivers/tty/serial/fsl_lpuart.c static inline void lpuart32_write(struct uart_port *port, u32 val, val 336 drivers/tty/serial/fsl_lpuart.c writel(val, port->membase + off); val 339 drivers/tty/serial/fsl_lpuart.c iowrite32be(val, port->membase + off); val 536 drivers/tty/serial/fsl_lpuart.c u32 val; val 548 drivers/tty/serial/fsl_lpuart.c val = lpuart32_read(&sport->port, UARTFIFO); val 549 drivers/tty/serial/fsl_lpuart.c val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; val 550 drivers/tty/serial/fsl_lpuart.c lpuart32_write(&sport->port, val, UARTFIFO); val 552 drivers/tty/serial/fsl_lpuart.c val = readb(sport->port.membase + UARTCFIFO); val 553 drivers/tty/serial/fsl_lpuart.c val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; val 554 drivers/tty/serial/fsl_lpuart.c writeb(val, sport->port.membase + UARTCFIFO); val 1377 drivers/tty/serial/fsl_lpuart.c unsigned char val, cr2; val 1386 drivers/tty/serial/fsl_lpuart.c val = readb(sport->port.membase + UARTPFIFO); val 1387 drivers/tty/serial/fsl_lpuart.c writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, val 1420 drivers/tty/serial/fsl_lpuart.c unsigned long val, ctrl; val 1430 drivers/tty/serial/fsl_lpuart.c val = lpuart32_read(&sport->port, UARTFIFO); val 1431 drivers/tty/serial/fsl_lpuart.c val |= UARTFIFO_TXFE | UARTFIFO_RXFE; val 1432 drivers/tty/serial/fsl_lpuart.c val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; val 1433 drivers/tty/serial/fsl_lpuart.c lpuart32_write(&sport->port, val, UARTFIFO); val 1436 drivers/tty/serial/fsl_lpuart.c val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); val 1437 drivers/tty/serial/fsl_lpuart.c lpuart32_write(&sport->port, val, UARTWATER); val 131 drivers/tty/serial/ifx6x60.c ifx_spi_power_state_set(struct ifx_spi_device *ifx_dev, unsigned char val) val 143 drivers/tty/serial/ifx6x60.c ifx_dev->power_status |= val; val 156 drivers/tty/serial/ifx6x60.c ifx_spi_power_state_clear(struct ifx_spi_device *ifx_dev, unsigned char val) val 163 drivers/tty/serial/ifx6x60.c ifx_dev->power_status &= ~val; val 247 drivers/tty/serial/ifx6x60.c int val = gpio_get_value(ifx_dev->gpio.srdy); val 248 drivers/tty/serial/ifx6x60.c if (!val) { val 901 drivers/tty/serial/ifx6x60.c int val = gpio_get_value(ifx_dev->gpio.reset_out); val 904 drivers/tty/serial/ifx6x60.c if (val == 0) { val 284 drivers/tty/serial/imx.c static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) val 288 drivers/tty/serial/imx.c sport->ucr1 = val; val 291 drivers/tty/serial/imx.c sport->ucr2 = val; val 294 drivers/tty/serial/imx.c sport->ucr3 = val; val 297 drivers/tty/serial/imx.c sport->ucr4 = val; val 300 drivers/tty/serial/imx.c sport->ufcr = val; val 305 drivers/tty/serial/imx.c writel(val, sport->port.membase + offset); val 1226 drivers/tty/serial/imx.c unsigned int val; val 1229 drivers/tty/serial/imx.c val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); val 1230 drivers/tty/serial/imx.c val |= txwl << UFCR_TXTL_SHF | rxwl; val 1231 drivers/tty/serial/imx.c imx_uart_writel(sport, val, UFCR); val 1006 drivers/tty/serial/ip22zilog.c unsigned char val = readb(&channel->control); val 1007 drivers/tty/serial/ip22zilog.c if (val & Tx_BUF_EMP) { val 293 drivers/tty/serial/max310x.c unsigned int val = 0; val 295 drivers/tty/serial/max310x.c regmap_read(s->regmap, port->iobase + reg, &val); val 297 drivers/tty/serial/max310x.c return val; val 300 drivers/tty/serial/max310x.c static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) val 304 drivers/tty/serial/max310x.c regmap_write(s->regmap, port->iobase + reg, val); val 307 drivers/tty/serial/max310x.c static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) val 311 drivers/tty/serial/max310x.c regmap_update_bits(s->regmap, port->iobase + reg, mask, val); val 317 drivers/tty/serial/max310x.c unsigned int val = 0; val 320 drivers/tty/serial/max310x.c ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); val 324 drivers/tty/serial/max310x.c if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { val 326 drivers/tty/serial/max310x.c "%s ID 0x%02x does not match\n", s->devtype->name, val); val 336 drivers/tty/serial/max310x.c unsigned int val = 0; val 342 drivers/tty/serial/max310x.c ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); val 346 drivers/tty/serial/max310x.c if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { val 357 drivers/tty/serial/max310x.c unsigned int val = 0; val 365 drivers/tty/serial/max310x.c regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); val 367 drivers/tty/serial/max310x.c if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { val 369 drivers/tty/serial/max310x.c "%s ID 0x%02x does not match\n", s->devtype->name, val); val 388 drivers/tty/serial/max310x.c unsigned int val = 0; val 396 drivers/tty/serial/max310x.c regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); val 398 drivers/tty/serial/max310x.c if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { val 400 drivers/tty/serial/max310x.c "%s ID 0x%02x does not match\n", s->devtype->name, val); val 613 drivers/tty/serial/max310x.c unsigned int val; val 615 drivers/tty/serial/max310x.c regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); val 616 drivers/tty/serial/max310x.c if (!(val & MAX310X_STS_CLKREADY_BIT)) { val 833 drivers/tty/serial/max310x.c unsigned int val = ~0; val 836 drivers/tty/serial/max310x.c MAX310X_GLOBALIRQ_REG, &val)); val 837 drivers/tty/serial/max310x.c val = ((1 << s->devtype->nr) - 1) & ~val; val 838 drivers/tty/serial/max310x.c if (!val) val 840 drivers/tty/serial/max310x.c if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) val 1051 drivers/tty/serial/max310x.c unsigned int val; val 1060 drivers/tty/serial/max310x.c val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; val 1061 drivers/tty/serial/max310x.c max310x_port_write(port, MAX310X_MODE2_REG, val); val 1066 drivers/tty/serial/max310x.c val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | val 1068 drivers/tty/serial/max310x.c max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); val 1090 drivers/tty/serial/max310x.c val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; val 1091 drivers/tty/serial/max310x.c max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); val 1189 drivers/tty/serial/max310x.c unsigned int val; val 1193 drivers/tty/serial/max310x.c val = max310x_port_read(port, MAX310X_GPIODATA_REG); val 1195 drivers/tty/serial/max310x.c return !!((val >> 4) & (1 << (offset % 4))); val 137 drivers/tty/serial/men_z135_uart.c u32 addr, u32 val) val 146 drivers/tty/serial/men_z135_uart.c reg |= val; val 159 drivers/tty/serial/men_z135_uart.c u32 addr, u32 val) val 168 drivers/tty/serial/men_z135_uart.c reg &= ~val; val 95 drivers/tty/serial/meson_uart.c u32 val; val 97 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_STATUS); val 98 drivers/tty/serial/meson_uart.c val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY); val 99 drivers/tty/serial/meson_uart.c return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0; val 104 drivers/tty/serial/meson_uart.c u32 val; val 106 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 107 drivers/tty/serial/meson_uart.c val &= ~AML_UART_TX_INT_EN; val 108 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 113 drivers/tty/serial/meson_uart.c u32 val; val 115 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 116 drivers/tty/serial/meson_uart.c val &= ~AML_UART_RX_EN; val 117 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 123 drivers/tty/serial/meson_uart.c u32 val; val 129 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 130 drivers/tty/serial/meson_uart.c val &= ~AML_UART_RX_EN; val 131 drivers/tty/serial/meson_uart.c val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); val 132 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 141 drivers/tty/serial/meson_uart.c u32 val; val 166 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 167 drivers/tty/serial/meson_uart.c val |= AML_UART_TX_INT_EN; val 168 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 261 drivers/tty/serial/meson_uart.c u32 val; val 263 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 264 drivers/tty/serial/meson_uart.c val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); val 265 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 267 drivers/tty/serial/meson_uart.c val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); val 268 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 273 drivers/tty/serial/meson_uart.c u32 val; val 276 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 277 drivers/tty/serial/meson_uart.c val |= AML_UART_CLEAR_ERR; val 278 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 279 drivers/tty/serial/meson_uart.c val &= ~AML_UART_CLEAR_ERR; val 280 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 282 drivers/tty/serial/meson_uart.c val |= (AML_UART_RX_EN | AML_UART_TX_EN); val 283 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 285 drivers/tty/serial/meson_uart.c val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); val 286 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 288 drivers/tty/serial/meson_uart.c val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); val 289 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_MISC); val 299 drivers/tty/serial/meson_uart.c u32 val; val 305 drivers/tty/serial/meson_uart.c val = ((port->uartclk / 3) / baud) - 1; val 306 drivers/tty/serial/meson_uart.c val |= AML_UART_BAUD_XTAL; val 308 drivers/tty/serial/meson_uart.c val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1; val 310 drivers/tty/serial/meson_uart.c val |= AML_UART_BAUD_USE; val 311 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_REG5); val 320 drivers/tty/serial/meson_uart.c u32 val; val 327 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 329 drivers/tty/serial/meson_uart.c val &= ~AML_UART_DATA_LEN_MASK; val 332 drivers/tty/serial/meson_uart.c val |= AML_UART_DATA_LEN_8BIT; val 335 drivers/tty/serial/meson_uart.c val |= AML_UART_DATA_LEN_7BIT; val 338 drivers/tty/serial/meson_uart.c val |= AML_UART_DATA_LEN_6BIT; val 341 drivers/tty/serial/meson_uart.c val |= AML_UART_DATA_LEN_5BIT; val 346 drivers/tty/serial/meson_uart.c val |= AML_UART_PARITY_EN; val 348 drivers/tty/serial/meson_uart.c val &= ~AML_UART_PARITY_EN; val 351 drivers/tty/serial/meson_uart.c val |= AML_UART_PARITY_TYPE; val 353 drivers/tty/serial/meson_uart.c val &= ~AML_UART_PARITY_TYPE; val 355 drivers/tty/serial/meson_uart.c val &= ~AML_UART_STOP_BIT_LEN_MASK; val 357 drivers/tty/serial/meson_uart.c val |= AML_UART_STOP_BIT_2SB; val 359 drivers/tty/serial/meson_uart.c val |= AML_UART_STOP_BIT_1SB; val 362 drivers/tty/serial/meson_uart.c val &= ~AML_UART_TWO_WIRE_EN; val 364 drivers/tty/serial/meson_uart.c val |= AML_UART_TWO_WIRE_EN; val 366 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 450 drivers/tty/serial/meson_uart.c u32 val; val 452 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 453 drivers/tty/serial/meson_uart.c val |= AML_UART_TX_EN; val 454 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 472 drivers/tty/serial/meson_uart.c u32 val, tmp; val 484 drivers/tty/serial/meson_uart.c val = readl(port->membase + AML_UART_CONTROL); val 485 drivers/tty/serial/meson_uart.c tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN); val 489 drivers/tty/serial/meson_uart.c writel(val, port->membase + AML_UART_CONTROL); val 120 drivers/tty/serial/mpc52xx_uart.c void (*set_sicr)(struct uart_port *port, u32 val); val 121 drivers/tty/serial/mpc52xx_uart.c void (*set_imr)(struct uart_port *port, u16 val); val 178 drivers/tty/serial/mpc52xx_uart.c static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val) val 180 drivers/tty/serial/mpc52xx_uart.c out_be32(&PSC(port)->sicr, val); val 183 drivers/tty/serial/mpc52xx_uart.c static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val) val 185 drivers/tty/serial/mpc52xx_uart.c out_be16(&PSC(port)->mpc52xx_psc_imr, val); val 954 drivers/tty/serial/mpc52xx_uart.c static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val) val 956 drivers/tty/serial/mpc52xx_uart.c out_be32(&PSC_5125(port)->sicr, val); val 959 drivers/tty/serial/mpc52xx_uart.c static void mpc5125_psc_set_imr(struct uart_port *port, u16 val) val 961 drivers/tty/serial/mpc52xx_uart.c out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val); val 84 drivers/tty/serial/mps2-uart.c static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off) val 88 drivers/tty/serial/mps2-uart.c writeb(val, mps_port->port.membase + off); val 98 drivers/tty/serial/mps2-uart.c static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off) val 102 drivers/tty/serial/mps2-uart.c writel_relaxed(val, mps_port->port.membase + off); val 190 drivers/tty/serial/msm_serial.c void msm_write(struct uart_port *port, unsigned int val, unsigned int off) val 192 drivers/tty/serial/msm_serial.c writel_relaxed(val, port->membase + off); val 249 drivers/tty/serial/msm_serial.c u32 val; val 263 drivers/tty/serial/msm_serial.c val = msm_read(port, UARTDM_DMEN); val 264 drivers/tty/serial/msm_serial.c val &= ~dma->enable_bit; val 265 drivers/tty/serial/msm_serial.c msm_write(port, val, UARTDM_DMEN); val 436 drivers/tty/serial/msm_serial.c u32 val; val 448 drivers/tty/serial/msm_serial.c val = msm_read(port, UARTDM_DMEN); val 449 drivers/tty/serial/msm_serial.c val &= ~dma->enable_bit; val 450 drivers/tty/serial/msm_serial.c msm_write(port, val, UARTDM_DMEN); val 483 drivers/tty/serial/msm_serial.c u32 val; val 518 drivers/tty/serial/msm_serial.c val = msm_read(port, UARTDM_DMEN); val 519 drivers/tty/serial/msm_serial.c val |= dma->enable_bit; val 522 drivers/tty/serial/msm_serial.c msm_write(port, val, UARTDM_DMEN); val 527 drivers/tty/serial/msm_serial.c msm_write(port, val, UARTDM_DMEN); val 544 drivers/tty/serial/msm_serial.c u32 val; val 552 drivers/tty/serial/msm_serial.c val = msm_read(port, UARTDM_DMEN); val 553 drivers/tty/serial/msm_serial.c val &= ~dma->enable_bit; val 554 drivers/tty/serial/msm_serial.c msm_write(port, val, UARTDM_DMEN); val 603 drivers/tty/serial/msm_serial.c u32 val; val 650 drivers/tty/serial/msm_serial.c val = msm_read(uart, UARTDM_DMEN); val 651 drivers/tty/serial/msm_serial.c val |= dma->enable_bit; val 654 drivers/tty/serial/msm_serial.c msm_write(uart, val, UARTDM_DMEN); val 659 drivers/tty/serial/msm_serial.c msm_write(uart, val, UARTDM_DMEN); val 931 drivers/tty/serial/msm_serial.c u32 val; val 944 drivers/tty/serial/msm_serial.c val = UART_CR_CMD_STALE_EVENT_DISABLE; val 945 drivers/tty/serial/msm_serial.c msm_write(port, val, UART_CR); val 946 drivers/tty/serial/msm_serial.c val = UART_CR_CMD_RESET_STALE_INT; val 947 drivers/tty/serial/msm_serial.c msm_write(port, val, UART_CR); val 645 drivers/tty/serial/mvebu-uart.c u32 val; val 647 drivers/tty/serial/mvebu-uart.c readl_poll_timeout_atomic(port->membase + UART_STAT, val, val 648 drivers/tty/serial/mvebu-uart.c (val & STAT_TX_RDY(port)), 1, 10000); val 501 drivers/tty/serial/mxs-auart.c static void mxs_write(unsigned int val, struct mxs_auart_port *uap, val 506 drivers/tty/serial/mxs-auart.c writel_relaxed(val, addr); val 509 drivers/tty/serial/mxs-auart.c static void mxs_set(unsigned int val, struct mxs_auart_port *uap, val 514 drivers/tty/serial/mxs-auart.c writel_relaxed(val, addr + SET_REG); val 517 drivers/tty/serial/mxs-auart.c static void mxs_clr(unsigned int val, struct mxs_auart_port *uap, val 522 drivers/tty/serial/mxs-auart.c writel_relaxed(val, addr + CLR_REG); val 1400 drivers/tty/serial/omap-serial.c int val; val 1422 drivers/tty/serial/omap-serial.c val = (port->rs485.flags & SER_RS485_ENABLED) ? val 1424 drivers/tty/serial/omap-serial.c val = (port->rs485.flags & val) ? 1 : 0; val 1425 drivers/tty/serial/omap-serial.c gpio_set_value(up->rts_gpio, val); val 80 drivers/tty/serial/owl-uart.c static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off) val 82 drivers/tty/serial/owl-uart.c writel(val, port->membase + off); val 121 drivers/tty/serial/owl-uart.c u32 val; val 126 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_STAT); val 127 drivers/tty/serial/owl-uart.c ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0; val 136 drivers/tty/serial/owl-uart.c u32 val; val 138 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_CTL); val 139 drivers/tty/serial/owl-uart.c val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE); val 140 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_CTL); val 142 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_STAT); val 143 drivers/tty/serial/owl-uart.c val |= OWL_UART_STAT_RIP; val 144 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_STAT); val 149 drivers/tty/serial/owl-uart.c u32 val; val 151 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_CTL); val 152 drivers/tty/serial/owl-uart.c val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE); val 153 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_CTL); val 155 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_STAT); val 156 drivers/tty/serial/owl-uart.c val |= OWL_UART_STAT_TIP; val 157 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_STAT); val 162 drivers/tty/serial/owl-uart.c u32 val; val 169 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_STAT); val 170 drivers/tty/serial/owl-uart.c val |= OWL_UART_STAT_TIP; val 171 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_STAT); val 173 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_CTL); val 174 drivers/tty/serial/owl-uart.c val |= OWL_UART_CTL_TXIE; val 175 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_CTL); val 213 drivers/tty/serial/owl-uart.c u32 stat, val; val 215 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_CTL); val 216 drivers/tty/serial/owl-uart.c val &= ~OWL_UART_CTL_TRFS_TX; val 217 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_CTL); val 237 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_RXDAT); val 238 drivers/tty/serial/owl-uart.c val &= 0xff; val 241 drivers/tty/serial/owl-uart.c tty_insert_flip_char(&port->state->port, val, flag); val 278 drivers/tty/serial/owl-uart.c u32 val; val 283 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_CTL); val 284 drivers/tty/serial/owl-uart.c val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE val 286 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_CTL); val 295 drivers/tty/serial/owl-uart.c u32 val; val 306 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_STAT); val 307 drivers/tty/serial/owl-uart.c val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP val 309 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_STAT); val 311 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_CTL); val 312 drivers/tty/serial/owl-uart.c val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE; val 313 drivers/tty/serial/owl-uart.c val |= OWL_UART_CTL_EN; val 314 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_CTL); val 497 drivers/tty/serial/owl-uart.c u32 old_ctl, val; val 513 drivers/tty/serial/owl-uart.c val = old_ctl | OWL_UART_CTL_TRFS_TX; val 515 drivers/tty/serial/owl-uart.c val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE); val 516 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_CTL); val 525 drivers/tty/serial/owl-uart.c val = owl_uart_read(port, OWL_UART_STAT); val 526 drivers/tty/serial/owl-uart.c val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP; val 527 drivers/tty/serial/owl-uart.c owl_uart_write(port, val, OWL_UART_STAT); val 66 drivers/tty/serial/pic32_uart.c u32 val = pic32_uart_readl(sport, PIC32_UART_STA); val 68 drivers/tty/serial/pic32_uart.c return (val & PIC32_UART_STA_TRMT) ? 1 : 0; val 75 drivers/tty/serial/pic32_uart.h u32 reg, u32 val) val 79 drivers/tty/serial/pic32_uart.h __raw_writel(val, port->membase + reg); val 125 drivers/tty/serial/rda-uart.c static inline void rda_uart_write(struct uart_port *port, u32 val, val 128 drivers/tty/serial/rda-uart.c writel(val, port->membase + off); val 140 drivers/tty/serial/rda-uart.c u32 val; val 144 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_STATUS); val 145 drivers/tty/serial/rda-uart.c ret = (val & RDA_UART_TX_FIFO_MASK) ? TIOCSER_TEMT : 0; val 169 drivers/tty/serial/rda-uart.c u32 val; val 172 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_CMD_SET); val 173 drivers/tty/serial/rda-uart.c rda_uart_write(port, (val | RDA_UART_RTS), RDA_UART_CMD_SET); val 176 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_CMD_CLR); val 177 drivers/tty/serial/rda-uart.c rda_uart_write(port, (val | RDA_UART_RTS), RDA_UART_CMD_CLR); val 180 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_CTRL); val 183 drivers/tty/serial/rda-uart.c val |= RDA_UART_LOOP_BACK_EN; val 185 drivers/tty/serial/rda-uart.c val &= ~RDA_UART_LOOP_BACK_EN; val 187 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_CTRL); val 192 drivers/tty/serial/rda-uart.c u32 val; val 194 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_IRQ_MASK); val 195 drivers/tty/serial/rda-uart.c val &= ~RDA_UART_TX_DATA_NEEDED; val 196 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_IRQ_MASK); val 198 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_CMD_SET); val 199 drivers/tty/serial/rda-uart.c val |= RDA_UART_TX_FIFO_RESET; val 200 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_CMD_SET); val 205 drivers/tty/serial/rda-uart.c u32 val; val 207 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_IRQ_MASK); val 208 drivers/tty/serial/rda-uart.c val &= ~(RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT); val 209 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_IRQ_MASK); val 212 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_RXTX_BUFFER); val 214 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_CMD_SET); val 215 drivers/tty/serial/rda-uart.c val |= RDA_UART_RX_FIFO_RESET; val 216 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_CMD_SET); val 221 drivers/tty/serial/rda-uart.c u32 val; val 228 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_IRQ_MASK); val 229 drivers/tty/serial/rda-uart.c val |= RDA_UART_TX_DATA_NEEDED; val 230 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_IRQ_MASK); val 333 drivers/tty/serial/rda-uart.c u32 val; val 363 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_IRQ_MASK); val 364 drivers/tty/serial/rda-uart.c val |= RDA_UART_TX_DATA_NEEDED; val 365 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_IRQ_MASK); val 371 drivers/tty/serial/rda-uart.c u32 status, val; val 392 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_RXTX_BUFFER); val 393 drivers/tty/serial/rda-uart.c val &= 0xff; val 396 drivers/tty/serial/rda-uart.c tty_insert_flip_char(&port->state->port, val, flag); val 410 drivers/tty/serial/rda-uart.c u32 val, irq_mask; val 415 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_IRQ_CAUSE); val 416 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_IRQ_CAUSE); val 418 drivers/tty/serial/rda-uart.c if (val & (RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT)) val 421 drivers/tty/serial/rda-uart.c if (val & (RDA_UART_TX_DATA_NEEDED)) { val 438 drivers/tty/serial/rda-uart.c u32 val; val 451 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_CTRL); val 452 drivers/tty/serial/rda-uart.c val |= RDA_UART_ENABLE; val 453 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_CTRL); val 456 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_IRQ_MASK); val 457 drivers/tty/serial/rda-uart.c val |= (RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT); val 458 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_IRQ_MASK); val 468 drivers/tty/serial/rda-uart.c u32 val; val 475 drivers/tty/serial/rda-uart.c val = rda_uart_read(port, RDA_UART_CTRL); val 476 drivers/tty/serial/rda-uart.c val &= ~RDA_UART_ENABLE; val 477 drivers/tty/serial/rda-uart.c rda_uart_write(port, val, RDA_UART_CTRL); val 243 drivers/tty/serial/rp2.c static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val) val 245 drivers/tty/serial/rp2.c rp2_rmw(up, reg, val, 0); val 248 drivers/tty/serial/rp2.c static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val) val 250 drivers/tty/serial/rp2.c rp2_rmw(up, reg, 0, val); val 1614 drivers/tty/serial/samsung.c unsigned long val, void *data) val 1638 drivers/tty/serial/samsung.c if (val == CPUFREQ_PRECHANGE) { val 1642 drivers/tty/serial/samsung.c } else if (val == CPUFREQ_POSTCHANGE) { val 116 drivers/tty/serial/samsung.h #define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg)) val 117 drivers/tty/serial/samsung.h #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) val 125 drivers/tty/serial/samsung.h u32 val; val 128 drivers/tty/serial/samsung.h val = rd_regl(port, reg); val 129 drivers/tty/serial/samsung.h val |= (1 << idx); val 130 drivers/tty/serial/samsung.h wr_regl(port, reg, val); val 138 drivers/tty/serial/samsung.h u32 val; val 141 drivers/tty/serial/samsung.h val = rd_regl(port, reg); val 142 drivers/tty/serial/samsung.h val &= ~(1 << idx); val 143 drivers/tty/serial/samsung.h wr_regl(port, reg, val); val 356 drivers/tty/serial/sc16is7xx.c unsigned int val = 0; val 359 drivers/tty/serial/sc16is7xx.c regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); val 361 drivers/tty/serial/sc16is7xx.c return val; val 364 drivers/tty/serial/sc16is7xx.c static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) val 369 drivers/tty/serial/sc16is7xx.c regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); val 402 drivers/tty/serial/sc16is7xx.c u8 mask, u8 val) val 408 drivers/tty/serial/sc16is7xx.c mask, val); val 998 drivers/tty/serial/sc16is7xx.c unsigned int val; val 1003 drivers/tty/serial/sc16is7xx.c val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; val 1004 drivers/tty/serial/sc16is7xx.c sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); val 1042 drivers/tty/serial/sc16is7xx.c val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT; val 1043 drivers/tty/serial/sc16is7xx.c sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); val 1129 drivers/tty/serial/sc16is7xx.c unsigned int val; val 1133 drivers/tty/serial/sc16is7xx.c val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); val 1135 drivers/tty/serial/sc16is7xx.c return !!(val & BIT(offset)); val 1138 drivers/tty/serial/sc16is7xx.c static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) val 1144 drivers/tty/serial/sc16is7xx.c val ? BIT(offset) : 0); val 1159 drivers/tty/serial/sc16is7xx.c unsigned offset, int val) val 1165 drivers/tty/serial/sc16is7xx.c if (val) val 560 drivers/tty/serial/sccnxp.c u8 val; val 565 drivers/tty/serial/sccnxp.c val = sccnxp_port_read(port, SCCNXP_SR_REG); val 568 drivers/tty/serial/sccnxp.c return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; val 157 drivers/tty/serial/serial-tegra.c static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, val 160 drivers/tty/serial/serial-tegra.c writel(val, tup->uport.membase + (reg << tup->uport.regshift)); val 105 drivers/tty/serial/sirfsoc_uart.c unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0; val 132 drivers/tty/serial/sirfsoc_uart.c val |= current_val; val 133 drivers/tty/serial/sirfsoc_uart.c wr_regl(port, ureg->sirfsoc_afc_ctrl, val); val 135 drivers/tty/serial/sirfsoc_uart.c if (!val) val 441 drivers/tty/serial/sirfsoc_uart.h #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) val 168 drivers/tty/serial/sprd_serial.c u32 val = serial_in(port, SPRD_CTL1); val 171 drivers/tty/serial/sprd_serial.c val |= SPRD_LOOPBACK_EN; val 173 drivers/tty/serial/sprd_serial.c val &= ~SPRD_LOOPBACK_EN; val 175 drivers/tty/serial/sprd_serial.c serial_out(port, SPRD_CTL1, val); val 199 drivers/tty/serial/sprd_serial.c u32 val = serial_in(port, SPRD_CTL1); val 202 drivers/tty/serial/sprd_serial.c val |= SPRD_DMA_EN; val 204 drivers/tty/serial/sprd_serial.c val &= ~SPRD_DMA_EN; val 206 drivers/tty/serial/sprd_serial.c serial_out(port, SPRD_CTL1, val); val 352 drivers/tty/serial/sprd_serial.c u32 val = serial_in(port, SPRD_CTL2); val 354 drivers/tty/serial/sprd_serial.c val &= ~THLD_RX_FULL_MASK; val 355 drivers/tty/serial/sprd_serial.c val |= thld & THLD_RX_FULL_MASK; val 356 drivers/tty/serial/sprd_serial.c serial_out(port, SPRD_CTL2, val); val 50 drivers/tty/serial/stm32-usart.c u32 val; val 52 drivers/tty/serial/stm32-usart.c val = readl_relaxed(port->membase + reg); val 53 drivers/tty/serial/stm32-usart.c val |= bits; val 54 drivers/tty/serial/stm32-usart.c writel_relaxed(val, port->membase + reg); val 59 drivers/tty/serial/stm32-usart.c u32 val; val 61 drivers/tty/serial/stm32-usart.c val = readl_relaxed(port->membase + reg); val 62 drivers/tty/serial/stm32-usart.c val &= ~bits; val 63 drivers/tty/serial/stm32-usart.c writel_relaxed(val, port->membase + reg); val 594 drivers/tty/serial/stm32-usart.c u32 val; val 609 drivers/tty/serial/stm32-usart.c val = readl_relaxed(port->membase + ofs->cr3); val 610 drivers/tty/serial/stm32-usart.c val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); val 611 drivers/tty/serial/stm32-usart.c val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; val 612 drivers/tty/serial/stm32-usart.c val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; val 613 drivers/tty/serial/stm32-usart.c writel_relaxed(val, port->membase + ofs->cr3); val 617 drivers/tty/serial/stm32-usart.c val = stm32_port->cr1_irq | USART_CR1_RE; val 619 drivers/tty/serial/stm32-usart.c val |= USART_CR1_FIFOEN; val 620 drivers/tty/serial/stm32-usart.c stm32_set_bits(port, ofs->cr1, val); val 630 drivers/tty/serial/stm32-usart.c u32 val, isr; val 633 drivers/tty/serial/stm32-usart.c val = USART_CR1_TXEIE | USART_CR1_TE; val 634 drivers/tty/serial/stm32-usart.c val |= stm32_port->cr1_irq | USART_CR1_RE; val 635 drivers/tty/serial/stm32-usart.c val |= BIT(cfg->uart_enable_bit); val 637 drivers/tty/serial/stm32-usart.c val |= USART_CR1_FIFOEN; val 646 drivers/tty/serial/stm32-usart.c stm32_clr_bits(port, ofs->cr1, val); val 1351 drivers/tty/serial/stm32-usart.c u32 val; val 1359 drivers/tty/serial/stm32-usart.c val = readl_relaxed(port->membase + ofs->cr3); val 1360 drivers/tty/serial/stm32-usart.c val &= ~USART_CR3_WUS_MASK; val 1362 drivers/tty/serial/stm32-usart.c val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; val 1363 drivers/tty/serial/stm32-usart.c writel_relaxed(val, port->membase + ofs->cr3); val 391 drivers/tty/serial/sunsab.c unsigned char val; val 396 drivers/tty/serial/sunsab.c val = readb(&up->regs->r.pvr); val 397 drivers/tty/serial/sunsab.c result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR; val 399 drivers/tty/serial/sunsab.c val = readb(&up->regs->r.vstr); val 400 drivers/tty/serial/sunsab.c result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR; val 402 drivers/tty/serial/sunsab.c val = readb(&up->regs->r.star); val 403 drivers/tty/serial/sunsab.c result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0; val 505 drivers/tty/serial/sunsab.c unsigned char val; val 509 drivers/tty/serial/sunsab.c val = up->cached_dafo; val 511 drivers/tty/serial/sunsab.c val |= SAB82532_DAFO_XBRK; val 513 drivers/tty/serial/sunsab.c val &= ~SAB82532_DAFO_XBRK; val 514 drivers/tty/serial/sunsab.c up->cached_dafo = val; val 1141 drivers/tty/serial/sunzilog.c unsigned char val = readb(&channel->control); val 1142 drivers/tty/serial/sunzilog.c if (val & Tx_BUF_EMP) { val 73 drivers/tty/serial/uartlite.c void (*out)(u32 val, void __iomem *addr); val 81 drivers/tty/serial/uartlite.c static void uartlite_outbe32(u32 val, void __iomem *addr) val 83 drivers/tty/serial/uartlite.c iowrite32be(val, addr); val 96 drivers/tty/serial/uartlite.c static void uartlite_outle32(u32 val, void __iomem *addr) val 98 drivers/tty/serial/uartlite.c iowrite32(val, addr); val 113 drivers/tty/serial/uartlite.c static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) val 117 drivers/tty/serial/uartlite.c pdata->reg_ops->out(val, port->membase + offset); val 453 drivers/tty/serial/uartlite.c u8 val; val 462 drivers/tty/serial/uartlite.c val = uart_in32(ULITE_STATUS, port); val 463 drivers/tty/serial/uartlite.c if ((val & ULITE_STATUS_TXFULL) == 0) val 115 drivers/tty/serial/vt8500_serial.c static inline void vt8500_write(struct uart_port *port, unsigned int val, val 118 drivers/tty/serial/vt8500_serial.c writel(val, port->membase + off); val 690 drivers/tty/serial/xilinx_uartps.c unsigned int ctrl_reg, mode_reg, val; val 697 drivers/tty/serial/xilinx_uartps.c val, (val & CDNS_UART_SR_TXEMPTY), val 1020 drivers/tty/serial/xilinx_uartps.c u32 val; val 1027 drivers/tty/serial/xilinx_uartps.c val = readl(port->membase + CDNS_UART_MODEMCR); val 1030 drivers/tty/serial/xilinx_uartps.c val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR | val 1035 drivers/tty/serial/xilinx_uartps.c val |= CDNS_UART_MODEMCR_FCM; val 1041 drivers/tty/serial/xilinx_uartps.c writel(val, port->membase + CDNS_UART_MODEMCR); val 2268 drivers/tty/synclink_gt.c unsigned short val = rd_reg16(info, TCR); val 2269 drivers/tty/synclink_gt.c wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ val 2270 drivers/tty/synclink_gt.c wr_reg16(info, TCR, val); /* clear reset bit */ val 2757 drivers/tty/synclink_gt.c unsigned short val = rd_reg16(info, SCR); val 2758 drivers/tty/synclink_gt.c if (!(val & IRQ_RXIDLE)) val 2759 drivers/tty/synclink_gt.c wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); val 2844 drivers/tty/synclink_gt.c unsigned short val; val 2853 drivers/tty/synclink_gt.c val = rd_reg16(info, TCR); val 2855 drivers/tty/synclink_gt.c val |= BIT7; val 2857 drivers/tty/synclink_gt.c val &= ~BIT7; val 2858 drivers/tty/synclink_gt.c wr_reg16(info, TCR, val); val 3940 drivers/tty/synclink_gt.c unsigned short val; val 3943 drivers/tty/synclink_gt.c val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ val 3944 drivers/tty/synclink_gt.c wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ val 3945 drivers/tty/synclink_gt.c wr_reg16(info, RCR, val); /* clear reset bit */ val 3960 drivers/tty/synclink_gt.c unsigned short val; val 3968 drivers/tty/synclink_gt.c val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ val 3969 drivers/tty/synclink_gt.c wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ val 3970 drivers/tty/synclink_gt.c wr_reg16(info, RCR, val); /* clear reset bit */ val 4047 drivers/tty/synclink_gt.c unsigned short val; val 4054 drivers/tty/synclink_gt.c val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ val 4055 drivers/tty/synclink_gt.c wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ val 4093 drivers/tty/synclink_gt.c unsigned short val; val 4117 drivers/tty/synclink_gt.c val = 0x4000; val 4120 drivers/tty/synclink_gt.c val |= BIT7; val 4123 drivers/tty/synclink_gt.c val |= BIT9; val 4125 drivers/tty/synclink_gt.c val |= BIT8; val 4130 drivers/tty/synclink_gt.c case 6: val |= BIT4; break; val 4131 drivers/tty/synclink_gt.c case 7: val |= BIT5; break; val 4132 drivers/tty/synclink_gt.c case 8: val |= BIT5 + BIT4; break; val 4136 drivers/tty/synclink_gt.c val |= BIT3; val 4139 drivers/tty/synclink_gt.c val |= BIT0; val 4141 drivers/tty/synclink_gt.c wr_reg16(info, TCR, val); val 4160 drivers/tty/synclink_gt.c val = 0x4000; val 4163 drivers/tty/synclink_gt.c val |= BIT9; val 4165 drivers/tty/synclink_gt.c val |= BIT8; val 4170 drivers/tty/synclink_gt.c case 6: val |= BIT4; break; val 4171 drivers/tty/synclink_gt.c case 7: val |= BIT5; break; val 4172 drivers/tty/synclink_gt.c case 8: val |= BIT5 + BIT4; break; val 4176 drivers/tty/synclink_gt.c val |= BIT0; val 4178 drivers/tty/synclink_gt.c wr_reg16(info, RCR, val); val 4212 drivers/tty/synclink_gt.c val = BIT15 + BIT14 + BIT0; val 4218 drivers/tty/synclink_gt.c val |= BIT3; val 4224 drivers/tty/synclink_gt.c wr_reg16(info, SCR, val); val 4234 drivers/tty/synclink_gt.c unsigned short val; val 4260 drivers/tty/synclink_gt.c val = BIT2; val 4264 drivers/tty/synclink_gt.c val |= BIT15 + BIT13; val 4266 drivers/tty/synclink_gt.c case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; val 4267 drivers/tty/synclink_gt.c case MGSL_MODE_BISYNC: val |= BIT15; break; val 4268 drivers/tty/synclink_gt.c case MGSL_MODE_RAW: val |= BIT13; break; val 4271 drivers/tty/synclink_gt.c val |= BIT7; val 4275 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZB: val |= BIT10; break; val 4276 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; val 4277 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; val 4278 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; val 4279 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; val 4280 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; val 4281 drivers/tty/synclink_gt.c case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; val 4286 drivers/tty/synclink_gt.c case HDLC_CRC_16_CCITT: val |= BIT9; break; val 4287 drivers/tty/synclink_gt.c case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; val 4291 drivers/tty/synclink_gt.c val |= BIT6; val 4295 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; val 4296 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; val 4297 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; val 4301 drivers/tty/synclink_gt.c val |= BIT0; val 4303 drivers/tty/synclink_gt.c wr_reg16(info, TCR, val); val 4309 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; val 4310 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; val 4311 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; val 4312 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; val 4313 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; val 4314 drivers/tty/synclink_gt.c default: val = 0x7e; break; val 4316 drivers/tty/synclink_gt.c wr_reg8(info, TPR, (unsigned char)val); val 4335 drivers/tty/synclink_gt.c val = 0; val 4339 drivers/tty/synclink_gt.c val |= BIT15 + BIT13; val 4341 drivers/tty/synclink_gt.c case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; val 4342 drivers/tty/synclink_gt.c case MGSL_MODE_BISYNC: val |= BIT15; break; val 4343 drivers/tty/synclink_gt.c case MGSL_MODE_RAW: val |= BIT13; break; val 4348 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZB: val |= BIT10; break; val 4349 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; val 4350 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; val 4351 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; val 4352 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; val 4353 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; val 4354 drivers/tty/synclink_gt.c case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; val 4359 drivers/tty/synclink_gt.c case HDLC_CRC_16_CCITT: val |= BIT9; break; val 4360 drivers/tty/synclink_gt.c case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; val 4364 drivers/tty/synclink_gt.c val |= BIT0; val 4366 drivers/tty/synclink_gt.c wr_reg16(info, RCR, val); val 4375 drivers/tty/synclink_gt.c val = 0; val 4383 drivers/tty/synclink_gt.c val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ val 4385 drivers/tty/synclink_gt.c val |= BIT6; /* 010, txclk = BRG */ val 4388 drivers/tty/synclink_gt.c val |= BIT7; /* 100, txclk = DPLL Input */ val 4390 drivers/tty/synclink_gt.c val |= BIT5; /* 001, txclk = RXC Input */ val 4393 drivers/tty/synclink_gt.c val |= BIT3; /* 010, rxclk = BRG */ val 4395 drivers/tty/synclink_gt.c val |= BIT4; /* 100, rxclk = DPLL */ val 4397 drivers/tty/synclink_gt.c val |= BIT2; /* 001, rxclk = TXC Input */ val 4400 drivers/tty/synclink_gt.c val |= BIT1 + BIT0; val 4402 drivers/tty/synclink_gt.c wr_reg8(info, CCR, (unsigned char)val); val 4411 drivers/tty/synclink_gt.c val = BIT7; break; val 4414 drivers/tty/synclink_gt.c val = BIT7 + BIT6; break; val 4415 drivers/tty/synclink_gt.c default: val = BIT6; // NRZ encodings val 4417 drivers/tty/synclink_gt.c wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); val 4459 drivers/tty/synclink_gt.c unsigned char val; val 4479 drivers/tty/synclink_gt.c val = (unsigned char)(info->idle_mode & 0xff); val 4484 drivers/tty/synclink_gt.c case HDLC_TXIDLE_FLAGS: val = 0x7e; break; val 4486 drivers/tty/synclink_gt.c case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; val 4488 drivers/tty/synclink_gt.c case HDLC_TXIDLE_SPACE: val = 0x00; break; val 4489 drivers/tty/synclink_gt.c default: val = 0xff; val 4493 drivers/tty/synclink_gt.c wr_reg8(info, TIR, val); val 4521 drivers/tty/synclink_gt.c unsigned char val = 0; val 4535 drivers/tty/synclink_gt.c val |= BIT5; /* 0010 */ val 4538 drivers/tty/synclink_gt.c val |= BIT7 + BIT6 + BIT5; /* 1110 */ val 4541 drivers/tty/synclink_gt.c val |= BIT6; /* 0100 */ val 4546 drivers/tty/synclink_gt.c val |= BIT4; val 4548 drivers/tty/synclink_gt.c val |= BIT3; val 4550 drivers/tty/synclink_gt.c val |= BIT2; val 4552 drivers/tty/synclink_gt.c val |= BIT1; val 4554 drivers/tty/synclink_gt.c val |= BIT0; val 4555 drivers/tty/synclink_gt.c wr_reg8(info, VCR, val); val 4563 drivers/tty/synclink_gt.c unsigned char val = rd_reg8(info, VCR); val 4565 drivers/tty/synclink_gt.c val |= BIT3; val 4567 drivers/tty/synclink_gt.c val &= ~BIT3; val 4569 drivers/tty/synclink_gt.c val |= BIT2; val 4571 drivers/tty/synclink_gt.c val &= ~BIT2; val 4572 drivers/tty/synclink_gt.c wr_reg8(info, VCR, val); val 622 drivers/tty/synclinkmp.c static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val); val 624 drivers/tty/synclinkmp.c static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val); val 996 drivers/tty/sysrq.c unsigned long val; val 999 drivers/tty/sysrq.c error = kstrtoul(buffer, 0, &val); val 1003 drivers/tty/sysrq.c if (val > KEY_MAX) val 1006 drivers/tty/sysrq.c *((unsigned short *)kp->arg) = val; val 2444 drivers/tty/tty_io.c unsigned int set, clear, val; val 2449 drivers/tty/tty_io.c retval = get_user(val, p); val 2455 drivers/tty/tty_io.c set = val; val 2458 drivers/tty/tty_io.c clear = val; val 2461 drivers/tty/tty_io.c set = val; val 2462 drivers/tty/tty_io.c clear = ~val; val 376 drivers/tty/vt/keyboard.c unsigned int k, sym, val; val 386 drivers/tty/vt/keyboard.c val = KVAL(sym); val 387 drivers/tty/vt/keyboard.c if (val == KVAL(K_CAPSSHIFT)) val 388 drivers/tty/vt/keyboard.c val = KVAL(K_SHIFT); val 390 drivers/tty/vt/keyboard.c shift_down[val]++; val 391 drivers/tty/vt/keyboard.c shift_state |= BIT(val); val 1893 drivers/tty/vt/keyboard.c ushort *key_map, *new_map, val, ov; val 1908 drivers/tty/vt/keyboard.c val = U(key_map[i]); val 1909 drivers/tty/vt/keyboard.c if (kb->kbdmode != VC_UNICODE && KTYP(val) >= NR_TYPES) val 1910 drivers/tty/vt/keyboard.c val = K_HOLE; val 1912 drivers/tty/vt/keyboard.c val = (i ? K_HOLE : K_NOSUCHMAP); val 1914 drivers/tty/vt/keyboard.c return put_user(val, &user_kbe->kb_value); val 4705 drivers/tty/vt/vt.c void vcs_scr_writew(struct vc_data *vc, u16 val, u16 *org) val 4707 drivers/tty/vt/vt.c scr_writew(val, org); val 106 drivers/uio/uio_fsl_elbc_gpcm.c unsigned long val; val 112 drivers/uio/uio_fsl_elbc_gpcm.c if (kstrtoul(buf, 0, &val) != 0) val 114 drivers/uio/uio_fsl_elbc_gpcm.c reg_new = (u32)val; val 80 drivers/uio/uio_pruss.c int val, intr_mask = (1 << intr_bit); val 86 drivers/uio/uio_pruss.c val = ioread32(intren_reg); val 88 drivers/uio/uio_pruss.c if (!(val & intr_mask) && (ioread32(intrstat_reg) & HIPIR_NOPEND)) val 996 drivers/usb/atm/cxacru.c __le32 val; val 1001 drivers/usb/atm/cxacru.c val = cpu_to_le32(instance->modem_type->pll_f_clk); val 1002 drivers/usb/atm/cxacru.c ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, PLLFCLK_ADDR, (u8 *) &val, 4); val 1009 drivers/usb/atm/cxacru.c val = cpu_to_le32(instance->modem_type->pll_b_clk); val 1010 drivers/usb/atm/cxacru.c ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, PLLBCLK_ADDR, (u8 *) &val, 4); val 1017 drivers/usb/atm/cxacru.c val = cpu_to_le32(SDRAM_ENA); val 1018 drivers/usb/atm/cxacru.c ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, SDRAMEN_ADDR, (u8 *) &val, 4); val 1051 drivers/usb/atm/cxacru.c val = cpu_to_le32(BR_ADDR); val 1052 drivers/usb/atm/cxacru.c ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, BR_STACK_ADDR, (u8 *) &val, 4); val 556 drivers/usb/atm/ueagle-atm.c #define UPDATE_ATM_STAT(type, val) \ val 559 drivers/usb/atm/ueagle-atm.c sc->usbatm->atm_dev->type = val; \ val 562 drivers/usb/atm/ueagle-atm.c #define UPDATE_ATM_SIGNAL(val) \ val 565 drivers/usb/atm/ueagle-atm.c atm_dev_signal_change(sc->usbatm->atm_dev, val); \ val 251 drivers/usb/c67x00/c67x00-ll-hpi.c u16 val; val 253 drivers/usb/c67x00/c67x00-ll-hpi.c val = hpi_read_word(dev, SIEMSG_REG(sie_num)); val 257 drivers/usb/c67x00/c67x00-ll-hpi.c return val; val 136 drivers/usb/cdns3/drd.c int ret, val; val 144 drivers/usb/cdns3/drd.c ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val, val 145 drivers/usb/cdns3/drd.c val & OTGSTS_XHCI_READY, val 156 drivers/usb/cdns3/drd.c readl_poll_timeout_atomic(&cdns->otg_regs->state, val, val 157 drivers/usb/cdns3/drd.c !(val & OTGSTATE_HOST_STATE_MASK), val 173 drivers/usb/cdns3/drd.c int ret, val; val 182 drivers/usb/cdns3/drd.c ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val, val 183 drivers/usb/cdns3/drd.c val & OTGSTS_DEV_READY, val 199 drivers/usb/cdns3/drd.c readl_poll_timeout_atomic(&cdns->otg_regs->state, val, val 200 drivers/usb/cdns3/drd.c !(val & OTGSTATE_DEV_STATE_MASK), val 229 drivers/usb/cdns3/gadget.c int val; val 237 drivers/usb/cdns3/gadget.c readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, val 238 drivers/usb/cdns3/gadget.c !(val & EP_CMD_DFLUSH), 1, 1000); val 1020 drivers/usb/cdns3/gadget.c int val; val 1032 drivers/usb/cdns3/gadget.c readl_poll_timeout_atomic(&priv_dev->regs->usb_sts, val, val 1033 drivers/usb/cdns3/gadget.c val & USB_STS_CFGSTS_MASK, 1, 100); val 1780 drivers/usb/cdns3/gadget.c int val; val 1826 drivers/usb/cdns3/gadget.c ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, val 1827 drivers/usb/cdns3/gadget.c !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)), val 1892 drivers/usb/cdns3/gadget.c int val; val 1921 drivers/usb/cdns3/gadget.c readl_poll_timeout_atomic(&priv_dev->regs->ep_sts, val, val 1922 drivers/usb/cdns3/gadget.c !(val & EP_STS_DBUSY), 1, 10); val 1925 drivers/usb/cdns3/gadget.c readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, val 1926 drivers/usb/cdns3/gadget.c !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)), val 2158 drivers/usb/cdns3/gadget.c int val; val 2173 drivers/usb/cdns3/gadget.c ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, val 2174 drivers/usb/cdns3/gadget.c !(val & EP_CMD_EPRST), 1, 100); val 2399 drivers/usb/cdns3/gadget.c int val; val 2412 drivers/usb/cdns3/gadget.c readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, val 2413 drivers/usb/cdns3/gadget.c !(val & EP_CMD_EPRST), 1, 100); val 349 drivers/usb/chipidea/ci.h static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) val 351 drivers/usb/chipidea/ci.h __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); val 354 drivers/usb/chipidea/ci.h static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) val 359 drivers/usb/chipidea/ci.h static inline void __hw_write(struct ci_hdrc *ci, u32 val, val 363 drivers/usb/chipidea/ci.h imx28_ci_writel(val, addr); val 365 drivers/usb/chipidea/ci.h iowrite32(val, addr); val 396 drivers/usb/chipidea/ci.h u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; val 398 drivers/usb/chipidea/ci.h __hw_write(ci, val, ci->hw_bank.regmap[reg]); val 399 drivers/usb/chipidea/ci.h return val; val 414 drivers/usb/chipidea/ci.h u32 val = hw_read(ci, reg, ~0); val 417 drivers/usb/chipidea/ci.h return (val & mask) >> __ffs(mask); val 53 drivers/usb/chipidea/ci_hdrc_msm.c u32 val; val 60 drivers/usb/chipidea/ci_hdrc_msm.c val = readl_relaxed(addr); val 61 drivers/usb/chipidea/ci_hdrc_msm.c val |= HS_PHY_POR_ASSERT; val 62 drivers/usb/chipidea/ci_hdrc_msm.c writel(val, addr); val 69 drivers/usb/chipidea/ci_hdrc_msm.c val &= ~HS_PHY_POR_ASSERT; val 70 drivers/usb/chipidea/ci_hdrc_msm.c writel(val, addr); val 91 drivers/usb/chipidea/ci_hdrc_msm.c u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL); val 92 drivers/usb/chipidea/ci_hdrc_msm.c val |= HS_PHY_DIG_CLAMP_N; val 93 drivers/usb/chipidea/ci_hdrc_msm.c writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL); val 145 drivers/usb/chipidea/ci_hdrc_msm.c u32 val; val 164 drivers/usb/chipidea/ci_hdrc_msm.c val = readl_relaxed(ci->base + HS_PHY_SEC_CTRL); val 165 drivers/usb/chipidea/ci_hdrc_msm.c val |= HS_PHY_DIG_CLAMP_N; val 166 drivers/usb/chipidea/ci_hdrc_msm.c writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL); val 31 drivers/usb/chipidea/otg.c u32 val = hw_read(ci, OP_OTGSC, mask); val 40 drivers/usb/chipidea/otg.c val |= OTGSC_BSVIS; val 42 drivers/usb/chipidea/otg.c val &= ~OTGSC_BSVIS; val 45 drivers/usb/chipidea/otg.c val |= OTGSC_BSV; val 47 drivers/usb/chipidea/otg.c val &= ~OTGSC_BSV; val 50 drivers/usb/chipidea/otg.c val |= OTGSC_BSVIE; val 52 drivers/usb/chipidea/otg.c val &= ~OTGSC_BSVIE; val 58 drivers/usb/chipidea/otg.c val |= OTGSC_IDIS; val 60 drivers/usb/chipidea/otg.c val &= ~OTGSC_IDIS; val 63 drivers/usb/chipidea/otg.c val &= ~OTGSC_ID; /* host */ val 65 drivers/usb/chipidea/otg.c val |= OTGSC_ID; /* device */ val 68 drivers/usb/chipidea/otg.c val |= OTGSC_IDIE; val 70 drivers/usb/chipidea/otg.c val &= ~OTGSC_IDIE; val 73 drivers/usb/chipidea/otg.c return val & mask; val 51 drivers/usb/chipidea/ulpi.c static int ci_ulpi_write(struct device *dev, u8 addr, u8 val) val 62 drivers/usb/chipidea/ulpi.c ULPI_RUN | ULPI_WRITE | ULPI_ADDR(addr) | val); val 128 drivers/usb/chipidea/usbmisc_imx.c u32 val = 0; val 136 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base); val 137 drivers/usb/chipidea/usbmisc_imx.c val &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT); val 138 drivers/usb/chipidea/usbmisc_imx.c val |= (MX25_EHCI_INTERFACE_DIFF_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; val 139 drivers/usb/chipidea/usbmisc_imx.c val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT); val 146 drivers/usb/chipidea/usbmisc_imx.c val &= ~MX25_OTG_OCPOL_BIT; val 148 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base); val 151 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base); val 152 drivers/usb/chipidea/usbmisc_imx.c val &= ~(MX25_H1_SIC_MASK | MX25_H1_PP_BIT | MX25_H1_IPPUE_UP_BIT); val 153 drivers/usb/chipidea/usbmisc_imx.c val |= (MX25_EHCI_INTERFACE_SINGLE_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; val 154 drivers/usb/chipidea/usbmisc_imx.c val |= (MX25_H1_PM_BIT | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | val 162 drivers/usb/chipidea/usbmisc_imx.c val &= ~MX25_H1_OCPOL_BIT; val 164 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base); val 178 drivers/usb/chipidea/usbmisc_imx.c u32 val; val 188 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg); val 191 drivers/usb/chipidea/usbmisc_imx.c val |= MX25_BM_EXTERNAL_VBUS_DIVIDER; val 193 drivers/usb/chipidea/usbmisc_imx.c val &= ~MX25_BM_EXTERNAL_VBUS_DIVIDER; val 195 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 206 drivers/usb/chipidea/usbmisc_imx.c u32 val; val 210 drivers/usb/chipidea/usbmisc_imx.c val = MX27_OTG_PM_BIT; val 213 drivers/usb/chipidea/usbmisc_imx.c val = MX27_H1_PM_BIT; val 216 drivers/usb/chipidea/usbmisc_imx.c val = MX27_H2_PM_BIT; val 224 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base) | val; val 226 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base) & ~val; val 227 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base); val 238 drivers/usb/chipidea/usbmisc_imx.c u32 val = 0; val 244 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); val 245 drivers/usb/chipidea/usbmisc_imx.c val &= ~MX53_USB_PHYCTRL1_PLLDIV_MASK; val 246 drivers/usb/chipidea/usbmisc_imx.c val |= MX53_USB_PLL_DIV_24_MHZ; val 247 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); val 255 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG; val 256 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 262 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_BM_OVER_CUR_DIS_H1; val 263 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 270 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_USB_CTRL_1_UH2_ULPI_EN; val 272 drivers/usb/chipidea/usbmisc_imx.c val &= ~MX53_USB_CTRL_1_H2_XCVR_CLK_SEL_MASK; val 273 drivers/usb/chipidea/usbmisc_imx.c val |= MX53_USB_CTRL_1_H2_XCVR_CLK_SEL_ULPI; val 274 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 277 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_USB_UHx_CTRL_WAKE_UP_EN val 279 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 284 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | val 286 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 292 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx; val 293 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 300 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_USB_CTRL_1_UH3_ULPI_EN; val 302 drivers/usb/chipidea/usbmisc_imx.c val &= ~MX53_USB_CTRL_1_H3_XCVR_CLK_SEL_MASK; val 303 drivers/usb/chipidea/usbmisc_imx.c val |= MX53_USB_CTRL_1_H3_XCVR_CLK_SEL_ULPI; val 304 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 307 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_USB_UHx_CTRL_WAKE_UP_EN val 309 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 315 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | val 317 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 322 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx; val 323 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); val 338 drivers/usb/chipidea/usbmisc_imx.c u32 val; val 347 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + data->index * 4); val 349 drivers/usb/chipidea/usbmisc_imx.c val |= wakeup_setting; val 351 drivers/usb/chipidea/usbmisc_imx.c if (val & MX6_BM_WAKEUP_INTR) val 353 drivers/usb/chipidea/usbmisc_imx.c val &= ~wakeup_setting; val 355 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base + data->index * 4); val 440 drivers/usb/chipidea/usbmisc_imx.c u32 val; val 451 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset); val 452 drivers/usb/chipidea/usbmisc_imx.c if (!(val & MX6_BM_HSIC_DEV_CONN)) val 453 drivers/usb/chipidea/usbmisc_imx.c writel(val | MX6_BM_HSIC_DEV_CONN, val 464 drivers/usb/chipidea/usbmisc_imx.c u32 val; val 475 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset); val 476 drivers/usb/chipidea/usbmisc_imx.c val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON; val 478 drivers/usb/chipidea/usbmisc_imx.c val |= MX6_BM_HSIC_CLK_ON; val 480 drivers/usb/chipidea/usbmisc_imx.c val &= ~MX6_BM_HSIC_CLK_ON; val 482 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset); val 494 drivers/usb/chipidea/usbmisc_imx.c u32 val; val 502 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg); val 503 drivers/usb/chipidea/usbmisc_imx.c writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg); val 508 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + data->index * 4); val 509 drivers/usb/chipidea/usbmisc_imx.c writel(val & ~MX6SX_BM_DPDM_WAKEUP_EN, val 516 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET); val 517 drivers/usb/chipidea/usbmisc_imx.c val |= MX6SX_BM_HSIC_AUTO_RESUME; val 518 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET); val 549 drivers/usb/chipidea/usbmisc_imx.c u32 val; val 554 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base); val 556 drivers/usb/chipidea/usbmisc_imx.c writel(val | wakeup_setting, usbmisc->base); val 558 drivers/usb/chipidea/usbmisc_imx.c if (val & MX6_BM_WAKEUP_INTR) val 560 drivers/usb/chipidea/usbmisc_imx.c writel(val & ~wakeup_setting, usbmisc->base); val 639 drivers/usb/class/cdc-acm.c int val; val 643 drivers/usb/class/cdc-acm.c val = ACM_CTRL_DTR | ACM_CTRL_RTS; val 645 drivers/usb/class/cdc-acm.c val = 0; val 648 drivers/usb/class/cdc-acm.c acm->ctrlout = val; val 650 drivers/usb/class/cdc-acm.c res = acm_set_control(acm, val); val 622 drivers/usb/class/usbtmc.c __u8 val; val 635 drivers/usb/class/usbtmc.c rv = copy_from_user(&val, arg, sizeof(val)); val 640 drivers/usb/class/usbtmc.c wValue = val ? 1 : 0; val 28 drivers/usb/common/ulpi.c int ulpi_write(struct ulpi *ulpi, u8 addr, u8 val) val 30 drivers/usb/common/ulpi.c return ulpi->ops->write(ulpi->dev.parent, addr, val); val 28 drivers/usb/core/quirks.c static int quirks_param_set(const char *val, const struct kernel_param *kp) val 36 drivers/usb/core/quirks.c err = param_set_copystring(val, kp); val 42 drivers/usb/core/quirks.c if (!*val) { val 49 drivers/usb/core/quirks.c for (quirk_count = 1, i = 0; val[i]; i++) val 50 drivers/usb/core/quirks.c if (val[i] == ',') val 66 drivers/usb/core/quirks.c for (i = 0, p = (char *)val; p && *p;) { val 275 drivers/usb/core/sysfs.c int val, rc; val 277 drivers/usb/core/sysfs.c if (sscanf(buf, "%d", &val) != 1 || val < 0 || val > 1) val 282 drivers/usb/core/sysfs.c if (val) val 764 drivers/usb/core/sysfs.c unsigned val; val 765 drivers/usb/core/sysfs.c result = sscanf(buf, "%u\n", &val); val 768 drivers/usb/core/sysfs.c else if (val == 0) val 945 drivers/usb/core/sysfs.c unsigned int val; val 951 drivers/usb/core/sysfs.c result = sscanf(buf, "%u\n", &val); val 953 drivers/usb/core/sysfs.c hcd->dev_policy = val <= USB_DEVICE_AUTHORIZE_INTERNAL ? val 954 drivers/usb/core/sysfs.c val : USB_DEVICE_AUTHORIZE_ALL; val 992 drivers/usb/core/sysfs.c bool val; val 994 drivers/usb/core/sysfs.c if (strtobool(buf, &val) != 0) val 997 drivers/usb/core/sysfs.c if (val) val 1192 drivers/usb/core/sysfs.c bool val; val 1194 drivers/usb/core/sysfs.c if (strtobool(buf, &val) != 0) val 1197 drivers/usb/core/sysfs.c if (val) val 1029 drivers/usb/dwc2/core.c u32 hcfg, val; val 1036 drivers/usb/dwc2/core.c val = HCFG_FSLSPCLKSEL_48_MHZ; val 1039 drivers/usb/dwc2/core.c val = HCFG_FSLSPCLKSEL_30_60_MHZ; val 1042 drivers/usb/dwc2/core.c dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); val 1045 drivers/usb/dwc2/core.c hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; val 1206 drivers/usb/dwc2/core.h u32 val; val 1208 drivers/usb/dwc2/core.h val = readl(hsotg->regs + offset); val 1210 drivers/usb/dwc2/core.h return swab32(val); val 1212 drivers/usb/dwc2/core.h return val; val 186 drivers/usb/dwc2/debugfs.c u32 val; val 192 drivers/usb/dwc2/debugfs.c val = dwc2_readl(hsotg, GNPTXFSIZ); val 194 drivers/usb/dwc2/debugfs.c val >> FIFOSIZE_DEPTH_SHIFT, val 195 drivers/usb/dwc2/debugfs.c val & FIFOSIZE_STARTADDR_MASK); val 200 drivers/usb/dwc2/debugfs.c val = dwc2_readl(hsotg, DPTXFSIZN(idx)); val 203 drivers/usb/dwc2/debugfs.c val >> FIFOSIZE_DEPTH_SHIFT, val 204 drivers/usb/dwc2/debugfs.c val & FIFOSIZE_STARTADDR_MASK); val 52 drivers/usb/dwc2/gadget.c static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) val 54 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); val 57 drivers/usb/dwc2/gadget.c static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) val 59 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); val 302 drivers/usb/dwc2/gadget.c u32 val; val 334 drivers/usb/dwc2/gadget.c val = addr; val 335 drivers/usb/dwc2/gadget.c val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; val 340 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, val, DPTXFSIZN(ep)); val 341 drivers/usb/dwc2/gadget.c val = dwc2_readl(hsotg, DPTXFSIZN(ep)); val 358 drivers/usb/dwc2/gadget.c val = dwc2_readl(hsotg, GRSTCTL); val 360 drivers/usb/dwc2/gadget.c if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) val 366 drivers/usb/dwc2/gadget.c __func__, val); val 3331 drivers/usb/dwc2/gadget.c u32 val; val 3510 drivers/usb/dwc2/gadget.c val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; val 3512 drivers/usb/dwc2/gadget.c val |= DCTL_SFTDISCON; val 3513 drivers/usb/dwc2/gadget.c dwc2_set_bit(hsotg, DCTL, val); val 3934 drivers/usb/dwc2/gadget.c unsigned int i, val, size; val 4073 drivers/usb/dwc2/gadget.c val = dwc2_readl(hsotg, DPTXFSIZN(i)); val 4074 drivers/usb/dwc2/gadget.c val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; val 4075 drivers/usb/dwc2/gadget.c if (val < size) val 4078 drivers/usb/dwc2/gadget.c if (val < fifo_size) { val 4079 drivers/usb/dwc2/gadget.c fifo_size = val; val 4758 drivers/usb/dwc2/gadget.c u32 val; val 4774 drivers/usb/dwc2/gadget.c val = dwc2_readl(hsotg, DPTXFSIZN(idx)); val 4776 drivers/usb/dwc2/gadget.c val >> FIFOSIZE_DEPTH_SHIFT, val 4777 drivers/usb/dwc2/gadget.c val & FIFOSIZE_STARTADDR_MASK); val 4787 drivers/usb/dwc2/gadget.c val = dwc2_readl(hsotg, DOEPCTL(idx)); val 5094 drivers/usb/dwc2/gadget.c u32 val; val 5099 drivers/usb/dwc2/gadget.c val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; val 5100 drivers/usb/dwc2/gadget.c val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; val 5101 drivers/usb/dwc2/gadget.c val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; val 5102 drivers/usb/dwc2/gadget.c val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; val 5103 drivers/usb/dwc2/gadget.c val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; val 5104 drivers/usb/dwc2/gadget.c val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL; val 5105 drivers/usb/dwc2/gadget.c val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; val 5106 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, val, GLPMCFG); val 5122 drivers/usb/dwc2/gadget.c u32 val = 0; val 5124 drivers/usb/dwc2/gadget.c val |= GREFCLK_REF_CLK_MODE; val 5125 drivers/usb/dwc2/gadget.c val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT; val 5126 drivers/usb/dwc2/gadget.c val |= hsotg->params.sof_cnt_wkup_alert << val 5129 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, val, GREFCLK); val 195 drivers/usb/dwc2/params.c u8 val; val 199 drivers/usb/dwc2/params.c val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; val 204 drivers/usb/dwc2/params.c val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; val 207 drivers/usb/dwc2/params.c val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; val 211 drivers/usb/dwc2/params.c hsotg->params.otg_cap = val; val 216 drivers/usb/dwc2/params.c int val; val 219 drivers/usb/dwc2/params.c val = DWC2_PHY_TYPE_PARAM_FS; val 223 drivers/usb/dwc2/params.c val = DWC2_PHY_TYPE_PARAM_UTMI; val 225 drivers/usb/dwc2/params.c val = DWC2_PHY_TYPE_PARAM_ULPI; val 231 drivers/usb/dwc2/params.c hsotg->params.phy_type = val; val 236 drivers/usb/dwc2/params.c int val; val 238 drivers/usb/dwc2/params.c val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? val 242 drivers/usb/dwc2/params.c val = DWC2_SPEED_PARAM_FULL; val 245 drivers/usb/dwc2/params.c val = DWC2_SPEED_PARAM_HIGH; val 247 drivers/usb/dwc2/params.c hsotg->params.speed = val; val 252 drivers/usb/dwc2/params.c int val; val 254 drivers/usb/dwc2/params.c val = (hsotg->hw_params.utmi_phy_data_width == val 263 drivers/usb/dwc2/params.c val = 8; val 266 drivers/usb/dwc2/params.c hsotg->params.phy_utmi_width = val; val 286 drivers/usb/dwc2/params.c int val; val 289 drivers/usb/dwc2/params.c val = 2; val 291 drivers/usb/dwc2/params.c val = 1; val 293 drivers/usb/dwc2/params.c val = 0; val 295 drivers/usb/dwc2/params.c hsotg->params.power_down = val; val 286 drivers/usb/dwc3/debugfs.c u32 val; val 299 drivers/usb/dwc3/debugfs.c val = dwc3_readl(dwc->regs, DWC3_GDBGLSP); val 300 drivers/usb/dwc3/debugfs.c seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", sel, val); val 305 drivers/usb/dwc3/debugfs.c val = dwc3_readl(dwc->regs, DWC3_GDBGLSP); val 306 drivers/usb/dwc3/debugfs.c seq_printf(s, "GDBGLSP_DBC[%d] = 0x%08x\n", sel, val); val 638 drivers/usb/dwc3/debugfs.c u32 val; val 641 drivers/usb/dwc3/debugfs.c val = dwc3_core_fifo_space(dep, DWC3_TXFIFO); val 644 drivers/usb/dwc3/debugfs.c val *= DWC3_MDWIDTH(dwc->hwparams.hwparams0); val 645 drivers/usb/dwc3/debugfs.c val >>= 3; val 646 drivers/usb/dwc3/debugfs.c seq_printf(s, "%u\n", val); val 657 drivers/usb/dwc3/debugfs.c u32 val; val 660 drivers/usb/dwc3/debugfs.c val = dwc3_core_fifo_space(dep, DWC3_RXFIFO); val 663 drivers/usb/dwc3/debugfs.c val *= DWC3_MDWIDTH(dwc->hwparams.hwparams0); val 664 drivers/usb/dwc3/debugfs.c val >>= 3; val 665 drivers/usb/dwc3/debugfs.c seq_printf(s, "%u\n", val); val 676 drivers/usb/dwc3/debugfs.c u32 val; val 679 drivers/usb/dwc3/debugfs.c val = dwc3_core_fifo_space(dep, DWC3_TXREQQ); val 680 drivers/usb/dwc3/debugfs.c seq_printf(s, "%u\n", val); val 691 drivers/usb/dwc3/debugfs.c u32 val; val 694 drivers/usb/dwc3/debugfs.c val = dwc3_core_fifo_space(dep, DWC3_RXREQQ); val 695 drivers/usb/dwc3/debugfs.c seq_printf(s, "%u\n", val); val 706 drivers/usb/dwc3/debugfs.c u32 val; val 709 drivers/usb/dwc3/debugfs.c val = dwc3_core_fifo_space(dep, DWC3_RXINFOQ); val 710 drivers/usb/dwc3/debugfs.c seq_printf(s, "%u\n", val); val 721 drivers/usb/dwc3/debugfs.c u32 val; val 724 drivers/usb/dwc3/debugfs.c val = dwc3_core_fifo_space(dep, DWC3_DESCFETCHQ); val 725 drivers/usb/dwc3/debugfs.c seq_printf(s, "%u\n", val); val 736 drivers/usb/dwc3/debugfs.c u32 val; val 739 drivers/usb/dwc3/debugfs.c val = dwc3_core_fifo_space(dep, DWC3_EVENTQ); val 740 drivers/usb/dwc3/debugfs.c seq_printf(s, "%u\n", val); val 51 drivers/usb/dwc3/dwc3-keystone.c u32 val; val 53 drivers/usb/dwc3/dwc3-keystone.c val = kdwc3_readl(kdwc->usbss, USBSS_IRQENABLE_SET_0); val 54 drivers/usb/dwc3/dwc3-keystone.c val |= USBSS_IRQ_COREIRQ_EN; val 55 drivers/usb/dwc3/dwc3-keystone.c kdwc3_writel(kdwc->usbss, USBSS_IRQENABLE_SET_0, val); val 60 drivers/usb/dwc3/dwc3-keystone.c u32 val; val 62 drivers/usb/dwc3/dwc3-keystone.c val = kdwc3_readl(kdwc->usbss, USBSS_IRQENABLE_SET_0); val 63 drivers/usb/dwc3/dwc3-keystone.c val &= ~USBSS_IRQ_COREIRQ_EN; val 64 drivers/usb/dwc3/dwc3-keystone.c kdwc3_writel(kdwc->usbss, USBSS_IRQENABLE_SET_0, val); val 219 drivers/usb/dwc3/dwc3-omap.c u32 val; val 231 drivers/usb/dwc3/dwc3-omap.c val = dwc3_omap_read_utmi_ctrl(omap); val 232 drivers/usb/dwc3/dwc3-omap.c val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG; val 233 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_utmi_ctrl(omap, val); val 237 drivers/usb/dwc3/dwc3-omap.c val = dwc3_omap_read_utmi_ctrl(omap); val 238 drivers/usb/dwc3/dwc3-omap.c val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND; val 239 drivers/usb/dwc3/dwc3-omap.c val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID val 241 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_utmi_ctrl(omap, val); val 247 drivers/usb/dwc3/dwc3-omap.c val = dwc3_omap_read_utmi_ctrl(omap); val 248 drivers/usb/dwc3/dwc3-omap.c val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG; val 249 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_utmi_ctrl(omap, val); val 253 drivers/usb/dwc3/dwc3-omap.c val = dwc3_omap_read_utmi_ctrl(omap); val 254 drivers/usb/dwc3/dwc3-omap.c val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID val 256 drivers/usb/dwc3/dwc3-omap.c val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND; val 257 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_utmi_ctrl(omap, val); val 81 drivers/usb/dwc3/dwc3-qcom.c static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) val 86 drivers/usb/dwc3/dwc3-qcom.c reg |= val; val 93 drivers/usb/dwc3/dwc3-qcom.c static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val) val 98 drivers/usb/dwc3/dwc3-qcom.c reg &= ~val; val 241 drivers/usb/dwc3/dwc3-qcom.c u32 val; val 247 drivers/usb/dwc3/dwc3-qcom.c val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); val 248 drivers/usb/dwc3/dwc3-qcom.c if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) val 117 drivers/usb/dwc3/dwc3-st.c u32 val; val 120 drivers/usb/dwc3/dwc3-st.c err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val); val 124 drivers/usb/dwc3/dwc3-st.c val &= USB3_CONTROL_MASK; val 129 drivers/usb/dwc3/dwc3-st.c val &= ~(USB3_DELAY_VBUSVALID val 140 drivers/usb/dwc3/dwc3-st.c val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID; val 145 drivers/usb/dwc3/dwc3-st.c val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID val 157 drivers/usb/dwc3/dwc3-st.c val |= USB3_DELAY_VBUSVALID; val 166 drivers/usb/dwc3/dwc3-st.c return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val); val 59 drivers/usb/dwc3/ulpi.c static int dwc3_ulpi_write(struct device *dev, u8 addr, u8 val) val 71 drivers/usb/dwc3/ulpi.c reg |= DWC3_GUSB2PHYACC_WRITE | val; val 42 drivers/usb/early/xhci-dbc.c u32 val, sz; val 45 drivers/usb/early/xhci-dbc.c val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0); val 48 drivers/usb/early/xhci-dbc.c write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, val); val 50 drivers/usb/early/xhci-dbc.c if (val == 0xffffffff || sz == 0xffffffff) { val 55 drivers/usb/early/xhci-dbc.c val64 = val & PCI_BASE_ADDRESS_MEM_MASK; val 59 drivers/usb/early/xhci-dbc.c if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) { val 60 drivers/usb/early/xhci-dbc.c val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4); val 63 drivers/usb/early/xhci-dbc.c write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, val); val 65 drivers/usb/early/xhci-dbc.c val64 |= (u64)val << 32; val 153 drivers/usb/early/xhci-dbc.c u32 val; val 156 drivers/usb/early/xhci-dbc.c val = readl(xdbc.xhci_base + offset); val 158 drivers/usb/early/xhci-dbc.c if (val & XHCI_HC_BIOS_OWNED) { val 159 drivers/usb/early/xhci-dbc.c writel(val | XHCI_HC_OS_OWNED, xdbc.xhci_base + offset); val 164 drivers/usb/early/xhci-dbc.c writel(val & ~XHCI_HC_BIOS_OWNED, xdbc.xhci_base + offset); val 169 drivers/usb/early/xhci-dbc.c val = readl(xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET); val 170 drivers/usb/early/xhci-dbc.c val &= XHCI_LEGACY_DISABLE_SMI; val 171 drivers/usb/early/xhci-dbc.c val |= XHCI_LEGACY_SMI_EVENTS; val 172 drivers/usb/early/xhci-dbc.c writel(val, xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET); val 351 drivers/usb/early/xhci-dbc.c u32 val, cap_length; val 360 drivers/usb/early/xhci-dbc.c val = readl(portsc); val 361 drivers/usb/early/xhci-dbc.c if (!(val & PORT_CONNECT)) val 362 drivers/usb/early/xhci-dbc.c writel(val | PORT_RESET, portsc); val 368 drivers/usb/early/xhci-dbc.c u32 val, port_offset, port_count; val 376 drivers/usb/early/xhci-dbc.c val = readl(xdbc.xhci_base + offset); val 377 drivers/usb/early/xhci-dbc.c if (XHCI_EXT_PORT_MAJOR(val) != 0x3) val 380 drivers/usb/early/xhci-dbc.c val = readl(xdbc.xhci_base + offset + 8); val 381 drivers/usb/early/xhci-dbc.c port_offset = XHCI_EXT_PORT_OFF(val); val 382 drivers/usb/early/xhci-dbc.c port_count = XHCI_EXT_PORT_COUNT(val); val 220 drivers/usb/early/xhci-dbc.h #define xdbc_write64(val, regs) xhci_write_64(NULL, (val), (regs)) val 432 drivers/usb/gadget/composite.c unsigned val; val 435 drivers/usb/gadget/composite.c val = c->MaxPower; val 437 drivers/usb/gadget/composite.c val = CONFIG_USB_GADGET_VBUS_DRAW; val 438 drivers/usb/gadget/composite.c if (!val) val 441 drivers/usb/gadget/composite.c return min(val, 500U) / 2; val 447 drivers/usb/gadget/composite.c return min(val, 900U) / 8; val 152 drivers/usb/gadget/configfs.c u8 val; \ val 154 drivers/usb/gadget/configfs.c ret = kstrtou8(page, 0, &val); \ val 157 drivers/usb/gadget/configfs.c to_gadget_info(item)->cdev.desc._name = val; \ val 165 drivers/usb/gadget/configfs.c u16 val; \ val 167 drivers/usb/gadget/configfs.c ret = kstrtou16(page, 0, &val); \ val 170 drivers/usb/gadget/configfs.c to_gadget_info(item)->cdev.desc._name = cpu_to_le16p(&val); \ val 470 drivers/usb/gadget/configfs.c u16 val; val 472 drivers/usb/gadget/configfs.c ret = kstrtou16(page, 0, &val); val 475 drivers/usb/gadget/configfs.c if (DIV_ROUND_UP(val, 8) > 0xff) val 477 drivers/usb/gadget/configfs.c to_config_usb_cfg(item)->c.MaxPower = val; val 491 drivers/usb/gadget/configfs.c u8 val; val 493 drivers/usb/gadget/configfs.c ret = kstrtou8(page, 0, &val); val 496 drivers/usb/gadget/configfs.c if (!(val & USB_CONFIG_ATT_ONE)) val 498 drivers/usb/gadget/configfs.c if (val & ~(USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER | val 501 drivers/usb/gadget/configfs.c to_config_usb_cfg(item)->c.bmAttributes = val; val 2050 drivers/usb/gadget/function/f_fs.c #define __entity_check_INTERFACE(val) 1 val 2051 drivers/usb/gadget/function/f_fs.c #define __entity_check_STRING(val) (val) val 2052 drivers/usb/gadget/function/f_fs.c #define __entity_check_ENDPOINT(val) ((val) & USB_ENDPOINT_NUMBER_MASK) val 2053 drivers/usb/gadget/function/f_fs.c #define __entity(type, val) do { \ val 2054 drivers/usb/gadget/function/f_fs.c pr_vdebug("entity " #type "(%02x)\n", (val)); \ val 2055 drivers/usb/gadget/function/f_fs.c if (unlikely(!__entity_check_ ##type(val))) { \ val 2059 drivers/usb/gadget/function/f_fs.c ret = entity(FFS_ ##type, &val, _ds, priv); \ val 2062 drivers/usb/gadget/function/f_fs.c (val), ret); \ val 487 drivers/usb/gadget/function/f_ncm.c static inline void put_ncm(__le16 **p, unsigned size, unsigned val) val 491 drivers/usb/gadget/function/f_ncm.c put_unaligned_le16((u16)val, *p); val 494 drivers/usb/gadget/function/f_ncm.c put_unaligned_le32((u32)val, *p); val 115 drivers/usb/gadget/function/u_ether_configfs.h u8 val; \ val 124 drivers/usb/gadget/function/u_ether_configfs.h ret = kstrtou8(page, 0, &val); \ val 128 drivers/usb/gadget/function/u_ether_configfs.h gether_set_qmult(opts->net, val); \ val 173 drivers/usb/gadget/function/u_ether_configfs.h u8 val; \ val 176 drivers/usb/gadget/function/u_ether_configfs.h ret = sscanf(page, "%02hhx", &val); \ val 178 drivers/usb/gadget/function/u_ether_configfs.h opts->_n_ = val; \ val 29 drivers/usb/gadget/function/u_uac1_legacy.c static int snd_interval_refine_set(struct snd_interval *i, unsigned int val) val 33 drivers/usb/gadget/function/u_uac1_legacy.c t.min = t.max = val; val 40 drivers/usb/gadget/function/u_uac1_legacy.c snd_pcm_hw_param_t var, unsigned int val, val 46 drivers/usb/gadget/function/u_uac1_legacy.c if (val == 0 && dir < 0) { val 51 drivers/usb/gadget/function/u_uac1_legacy.c val++; val 53 drivers/usb/gadget/function/u_uac1_legacy.c val--; val 55 drivers/usb/gadget/function/u_uac1_legacy.c hw_param_mask(params, var), val); val 59 drivers/usb/gadget/function/u_uac1_legacy.c if (val == 0 && dir < 0) { val 63 drivers/usb/gadget/function/u_uac1_legacy.c changed = snd_interval_refine_set(i, val); val 71 drivers/usb/gadget/function/u_uac1_legacy.c t.min = val - 1; val 72 drivers/usb/gadget/function/u_uac1_legacy.c t.max = val; val 74 drivers/usb/gadget/function/u_uac1_legacy.c t.min = val; val 75 drivers/usb/gadget/function/u_uac1_legacy.c t.max = val+1; val 290 drivers/usb/gadget/legacy/inode.c int val; val 299 drivers/usb/gadget/legacy/inode.c val = -EAGAIN; val 301 drivers/usb/gadget/legacy/inode.c val = 0; val 302 drivers/usb/gadget/legacy/inode.c return val; val 305 drivers/usb/gadget/legacy/inode.c val = mutex_lock_interruptible(&epdata->lock); val 306 drivers/usb/gadget/legacy/inode.c if (val < 0) val 307 drivers/usb/gadget/legacy/inode.c return val; val 91 drivers/usb/gadget/udc/at91_udc.c #define at91_udp_write(udc, reg, val) \ val 92 drivers/usb/gadget/udc/at91_udc.c __raw_writel((val), (udc)->udp_baseaddr + (reg)) val 1787 drivers/usb/gadget/udc/at91_udc.c u32 val; val 1789 drivers/usb/gadget/udc/at91_udc.c if (of_property_read_u32(np, "atmel,vbus-polled", &val) == 0) val 364 drivers/usb/gadget/udc/atmel_usba_udc.c u32 val; val 366 drivers/usb/gadget/udc/atmel_usba_udc.c val = udc->int_enb_cache | mask; val 367 drivers/usb/gadget/udc/atmel_usba_udc.c usba_writel(udc, INT_ENB, val); val 368 drivers/usb/gadget/udc/atmel_usba_udc.c udc->int_enb_cache = val; val 373 drivers/usb/gadget/udc/atmel_usba_udc.c u32 val; val 375 drivers/usb/gadget/udc/atmel_usba_udc.c val = udc->int_enb_cache & ~mask; val 376 drivers/usb/gadget/udc/atmel_usba_udc.c usba_writel(udc, INT_ENB, val); val 377 drivers/usb/gadget/udc/atmel_usba_udc.c udc->int_enb_cache = val; val 2057 drivers/usb/gadget/udc/atmel_usba_udc.c u32 val; val 2105 drivers/usb/gadget/udc/atmel_usba_udc.c ret = of_property_read_u32(pp, "reg", &val); val 2110 drivers/usb/gadget/udc/atmel_usba_udc.c ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : val; val 2112 drivers/usb/gadget/udc/atmel_usba_udc.c ret = of_property_read_u32(pp, "atmel,fifo-size", &val); val 2118 drivers/usb/gadget/udc/atmel_usba_udc.c if (val < udc->fifo_cfg[i].fifo_size) { val 2121 drivers/usb/gadget/udc/atmel_usba_udc.c ep->fifo_size = val; val 2126 drivers/usb/gadget/udc/atmel_usba_udc.c ep->fifo_size = val; val 2129 drivers/usb/gadget/udc/atmel_usba_udc.c ret = of_property_read_u32(pp, "atmel,nb-banks", &val); val 2135 drivers/usb/gadget/udc/atmel_usba_udc.c if (val < udc->fifo_cfg[i].nr_banks) { val 2138 drivers/usb/gadget/udc/atmel_usba_udc.c ep->nr_banks = val; val 2143 drivers/usb/gadget/udc/atmel_usba_udc.c ep->nr_banks = val; val 359 drivers/usb/gadget/udc/bcm63xx_udc.c static inline void usbd_writel(struct bcm63xx_udc *udc, u32 val, u32 off) val 361 drivers/usb/gadget/udc/bcm63xx_udc.c bcm_writel(val, udc->usbd_regs + off); val 369 drivers/usb/gadget/udc/bcm63xx_udc.c static inline void usb_dma_writel(struct bcm63xx_udc *udc, u32 val, u32 off) val 371 drivers/usb/gadget/udc/bcm63xx_udc.c bcm_writel(val, udc->iudma_regs + off); val 380 drivers/usb/gadget/udc/bcm63xx_udc.c static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off, val 383 drivers/usb/gadget/udc/bcm63xx_udc.c bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off + val 393 drivers/usb/gadget/udc/bcm63xx_udc.c static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off, val 396 drivers/usb/gadget/udc/bcm63xx_udc.c bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off + val 427 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val = usbd_readl(udc, USBD_CONTROL_REG); val 429 drivers/usb/gadget/udc/bcm63xx_udc.c val &= ~USBD_CONTROL_INIT_SEL_MASK; val 430 drivers/usb/gadget/udc/bcm63xx_udc.c val |= idx << USBD_CONTROL_INIT_SEL_SHIFT; val 431 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_CONTROL_REG); val 446 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val; val 448 drivers/usb/gadget/udc/bcm63xx_udc.c val = USBD_STALL_UPDATE_MASK | val 451 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_STALL_REG); val 464 drivers/usb/gadget/udc/bcm63xx_udc.c u32 i, val, rx_fifo_slot, tx_fifo_slot; val 474 drivers/usb/gadget/udc/bcm63xx_udc.c val = (rx_fifo_slot << USBD_RXFIFO_CONFIG_START_SHIFT) | val 478 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_RXFIFO_CONFIG_REG); val 483 drivers/usb/gadget/udc/bcm63xx_udc.c val = (tx_fifo_slot << USBD_TXFIFO_CONFIG_START_SHIFT) | val 487 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_TXFIFO_CONFIG_REG); val 503 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val; val 507 drivers/usb/gadget/udc/bcm63xx_udc.c val = usbd_readl(udc, USBD_CONTROL_REG); val 508 drivers/usb/gadget/udc/bcm63xx_udc.c val |= USBD_CONTROL_FIFO_RESET_MASK; val 509 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_CONTROL_REG); val 531 drivers/usb/gadget/udc/bcm63xx_udc.c u32 i, val; val 540 drivers/usb/gadget/udc/bcm63xx_udc.c val = (cfg->ep_type << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) | val 542 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_EPNUM_TYPEMAP_REG); val 554 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val, i; val 570 drivers/usb/gadget/udc/bcm63xx_udc.c val = (idx << USBD_CSR_EP_LOG_SHIFT) | val 577 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_CSR_EP_REG(idx)); val 846 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val; val 850 drivers/usb/gadget/udc/bcm63xx_udc.c val = BIT(USBD_EVENT_IRQ_USB_RESET) | val 855 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, enable_irqs ? val : 0, USBD_EVENT_IRQ_MASK_REG); val 856 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_EVENT_IRQ_STATUS_REG); val 872 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val, portmask = BIT(udc->pd->port_no); val 876 drivers/usb/gadget/udc/bcm63xx_udc.c val = bcm_gpio_readl(GPIO_PINMUX_OTHR_REG); val 877 drivers/usb/gadget/udc/bcm63xx_udc.c val &= ~GPIO_PINMUX_OTHR_6328_USB_MASK; val 878 drivers/usb/gadget/udc/bcm63xx_udc.c val |= is_device ? GPIO_PINMUX_OTHR_6328_USB_DEV : val 880 drivers/usb/gadget/udc/bcm63xx_udc.c bcm_gpio_writel(val, GPIO_PINMUX_OTHR_REG); val 883 drivers/usb/gadget/udc/bcm63xx_udc.c val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); val 885 drivers/usb/gadget/udc/bcm63xx_udc.c val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); val 886 drivers/usb/gadget/udc/bcm63xx_udc.c val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); val 888 drivers/usb/gadget/udc/bcm63xx_udc.c val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); val 889 drivers/usb/gadget/udc/bcm63xx_udc.c val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); val 891 drivers/usb/gadget/udc/bcm63xx_udc.c bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); val 893 drivers/usb/gadget/udc/bcm63xx_udc.c val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); val 895 drivers/usb/gadget/udc/bcm63xx_udc.c val |= USBH_PRIV_SWAP_USBD_MASK; val 897 drivers/usb/gadget/udc/bcm63xx_udc.c val &= ~USBH_PRIV_SWAP_USBD_MASK; val 898 drivers/usb/gadget/udc/bcm63xx_udc.c bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); val 912 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val, portmask = BIT(udc->pd->port_no); val 914 drivers/usb/gadget/udc/bcm63xx_udc.c val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); val 916 drivers/usb/gadget/udc/bcm63xx_udc.c val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); val 918 drivers/usb/gadget/udc/bcm63xx_udc.c val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); val 919 drivers/usb/gadget/udc/bcm63xx_udc.c bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); val 946 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val; val 987 drivers/usb/gadget/udc/bcm63xx_udc.c val = USBD_CONTROL_AUTO_CSRS_MASK | val 990 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_CONTROL_REG); val 992 drivers/usb/gadget/udc/bcm63xx_udc.c val = USBD_STRAPS_APP_SELF_PWR_MASK | val 999 drivers/usb/gadget/udc/bcm63xx_udc.c val |= (BCM63XX_SPD_HIGH << USBD_STRAPS_SPEED_SHIFT); val 1001 drivers/usb/gadget/udc/bcm63xx_udc.c val |= (BCM63XX_SPD_FULL << USBD_STRAPS_SPEED_SHIFT); val 1002 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_STRAPS_REG); val 1008 drivers/usb/gadget/udc/bcm63xx_udc.c val = USBD_EVENT_IRQ_CFG_FALLING(USBD_EVENT_IRQ_ENUM_ON) | val 1010 drivers/usb/gadget/udc/bcm63xx_udc.c usbd_writel(udc, val, USBD_EVENT_IRQ_CFG_HI_REG); val 85 drivers/usb/gadget/udc/fotg210-udc.c u32 val; val 92 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_EPMAP); val 93 drivers/usb/gadget/udc/fotg210-udc.c val &= ~EPMAP_FIFONOMSK(epnum, dir_in); val 94 drivers/usb/gadget/udc/fotg210-udc.c val |= EPMAP_FIFONO(epnum, dir_in); val 95 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_EPMAP); val 98 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_FIFOMAP); val 99 drivers/usb/gadget/udc/fotg210-udc.c val &= ~FIFOMAP_EPNOMSK(epnum); val 100 drivers/usb/gadget/udc/fotg210-udc.c val |= FIFOMAP_EPNO(epnum); val 101 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_FIFOMAP); val 104 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_FIFOCF); val 105 drivers/usb/gadget/udc/fotg210-udc.c val |= FIFOCF_FIFO_EN(epnum - 1); val 106 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_FIFOCF); val 112 drivers/usb/gadget/udc/fotg210-udc.c u32 val; val 114 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_FIFOMAP); val 115 drivers/usb/gadget/udc/fotg210-udc.c val |= (dir_in ? FIFOMAP_DIRIN(epnum - 1) : FIFOMAP_DIROUT(epnum - 1)); val 116 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_FIFOMAP); val 122 drivers/usb/gadget/udc/fotg210-udc.c u32 val; val 124 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_FIFOCF); val 125 drivers/usb/gadget/udc/fotg210-udc.c val |= FIFOCF_TYPE(type, epnum - 1); val 126 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_FIFOCF); val 133 drivers/usb/gadget/udc/fotg210-udc.c u32 val; val 137 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + offset); val 138 drivers/usb/gadget/udc/fotg210-udc.c val |= INOUTEPMPSR_MPS(mps); val 139 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + offset); val 75 drivers/usb/gadget/udc/fusb300_udc.c u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); val 77 drivers/usb/gadget/udc/fusb300_udc.c val &= ~FUSB300_EPSET1_FIFOENTRY_MSK; val 78 drivers/usb/gadget/udc/fusb300_udc.c val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM); val 79 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); val 1284 drivers/usb/gadget/udc/fusb300_udc.c u32 val = 0; val 1287 drivers/usb/gadget/udc/fusb300_udc.c mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON; val 1290 drivers/usb/gadget/udc/fusb300_udc.c reg |= val; val 1294 drivers/usb/gadget/udc/fusb300_udc.c mask = val = FUSB300_HSCR_HS_LPM_PERMIT; val 1297 drivers/usb/gadget/udc/fusb300_udc.c reg |= val; val 541 drivers/usb/gadget/udc/m66592-udc.h static inline void m66592_write(struct m66592 *m66592, u16 val, val 544 drivers/usb/gadget/udc/m66592-udc.h iowrite16(val, m66592->reg + offset); val 547 drivers/usb/gadget/udc/m66592-udc.h static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, val 553 drivers/usb/gadget/udc/m66592-udc.h tmp = tmp | val; val 557 drivers/usb/gadget/udc/m66592-udc.h #define m66592_bclr(m66592, val, offset) \ val 558 drivers/usb/gadget/udc/m66592-udc.h m66592_mdfy(m66592, 0, val, offset) val 559 drivers/usb/gadget/udc/m66592-udc.h #define m66592_bset(m66592, val, offset) \ val 560 drivers/usb/gadget/udc/m66592-udc.h m66592_mdfy(m66592, val, 0, offset) val 2109 drivers/usb/gadget/udc/net2272.c u8 val, refval; val 2115 drivers/usb/gadget/udc/net2272.c val = net2272_read(dev, SCRATCH); val 2116 drivers/usb/gadget/udc/net2272.c if (val != ii) { val 2120 drivers/usb/gadget/udc/net2272.c __func__, ii, val); val 2131 drivers/usb/gadget/udc/net2272.c val = net2272_read(dev, CHIPREV_2272); val 2132 drivers/usb/gadget/udc/net2272.c if (val != refval) { val 2136 drivers/usb/gadget/udc/net2272.c __func__, ii, val, refval); val 2148 drivers/usb/gadget/udc/net2272.c val = net2272_read(dev, CHIPREV_LEGACY); val 2149 drivers/usb/gadget/udc/net2272.c if (val != NET2270_LEGACY_REV) { val 2157 drivers/usb/gadget/udc/net2272.c __func__, NET2270_LEGACY_REV, val); val 2166 drivers/usb/gadget/udc/net2272.c val = net2272_read(dev, CHIPREV_2272); val 2167 drivers/usb/gadget/udc/net2272.c switch (val) { val 2184 drivers/usb/gadget/udc/net2272.c __func__, val); val 2195 drivers/usb/gadget/udc/net2280.c u32 tmp, val; val 2247 drivers/usb/gadget/udc/net2280.c val = readl(&dev->llregs->ll_lfps_5); val 2248 drivers/usb/gadget/udc/net2280.c val &= ~(0xf << TIMER_LFPS_6US); val 2249 drivers/usb/gadget/udc/net2280.c val |= 0x5 << TIMER_LFPS_6US; val 2250 drivers/usb/gadget/udc/net2280.c writel(val, &dev->llregs->ll_lfps_5); val 2252 drivers/usb/gadget/udc/net2280.c val = readl(&dev->llregs->ll_lfps_6); val 2253 drivers/usb/gadget/udc/net2280.c val &= ~(0xffff << TIMER_LFPS_80US); val 2254 drivers/usb/gadget/udc/net2280.c val |= 0x0100 << TIMER_LFPS_80US; val 2255 drivers/usb/gadget/udc/net2280.c writel(val, &dev->llregs->ll_lfps_6); val 2262 drivers/usb/gadget/udc/net2280.c val = readl(&dev->llregs->ll_tsn_counters_2); val 2263 drivers/usb/gadget/udc/net2280.c val &= ~(0x1f << HOT_TX_NORESET_TS2); val 2264 drivers/usb/gadget/udc/net2280.c val |= 0x10 << HOT_TX_NORESET_TS2; val 2265 drivers/usb/gadget/udc/net2280.c writel(val, &dev->llregs->ll_tsn_counters_2); val 2267 drivers/usb/gadget/udc/net2280.c val = readl(&dev->llregs->ll_tsn_counters_3); val 2268 drivers/usb/gadget/udc/net2280.c val &= ~(0x1f << HOT_RX_RESET_TS2); val 2269 drivers/usb/gadget/udc/net2280.c val |= 0x3 << HOT_RX_RESET_TS2; val 2270 drivers/usb/gadget/udc/net2280.c writel(val, &dev->llregs->ll_tsn_counters_3); val 2278 drivers/usb/gadget/udc/net2280.c val = readl(&dev->llregs->ll_lfps_timers_2); val 2279 drivers/usb/gadget/udc/net2280.c writel((val & 0xffff0000) | LFPS_TIMERS_2_WORKAROUND_VALUE, val 2290 drivers/usb/gadget/udc/net2280.c val = readl(&dev->llregs->ll_tsn_chicken_bit); val 2291 drivers/usb/gadget/udc/net2280.c val |= BIT(RECOVERY_IDLE_TO_RECOVER_FMW); val 2292 drivers/usb/gadget/udc/net2280.c writel(val, &dev->llregs->ll_tsn_chicken_bit); val 2849 drivers/usb/gadget/udc/net2280.c u32 val; val 2852 drivers/usb/gadget/udc/net2280.c val = readl(&dev->plregs->pl_ep_ctrl) & ~0x1f; val 2853 drivers/usb/gadget/udc/net2280.c val |= ep_pl[ep->num]; val 2854 drivers/usb/gadget/udc/net2280.c writel(val, &dev->plregs->pl_ep_ctrl); val 2855 drivers/usb/gadget/udc/net2280.c val |= BIT(SEQUENCE_NUMBER_RESET); val 2856 drivers/usb/gadget/udc/net2280.c writel(val, &dev->plregs->pl_ep_ctrl); val 3110 drivers/usb/gadget/udc/net2280.c u32 val = readl(&dev->usb->usbstat); val 3111 drivers/usb/gadget/udc/net2280.c if (val & BIT(SUPER_SPEED)) { val 3115 drivers/usb/gadget/udc/net2280.c } else if (val & BIT(HIGH_SPEED)) { val 264 drivers/usb/gadget/udc/net2280.h u32 val = readl(&dev->regs->gpioctl); val 267 drivers/usb/gadget/udc/net2280.h val |= BIT(GPIO0_DATA) | BIT(GPIO1_DATA); val 270 drivers/usb/gadget/udc/net2280.h val &= ~BIT(GPIO0_DATA); val 271 drivers/usb/gadget/udc/net2280.h val |= BIT(GPIO1_DATA); val 274 drivers/usb/gadget/udc/net2280.h val &= ~BIT(GPIO1_DATA); val 275 drivers/usb/gadget/udc/net2280.h val |= BIT(GPIO0_DATA); val 278 drivers/usb/gadget/udc/net2280.h val &= ~(BIT(GPIO1_DATA) | BIT(GPIO0_DATA)); val 281 drivers/usb/gadget/udc/net2280.h writel(val, &dev->regs->gpioctl); val 287 drivers/usb/gadget/udc/net2280.h u32 val = readl(&dev->regs->gpioctl); val 291 drivers/usb/gadget/udc/net2280.h val |= GPIO2_DATA; val 293 drivers/usb/gadget/udc/net2280.h val &= ~GPIO2_DATA; val 294 drivers/usb/gadget/udc/net2280.h writel(val, &dev->regs->gpioctl); val 414 drivers/usb/gadget/udc/pch_udc.c unsigned long val, unsigned long reg) val 416 drivers/usb/gadget/udc/pch_udc.c iowrite32(val, dev->base_addr + reg); val 439 drivers/usb/gadget/udc/pch_udc.c unsigned long val, unsigned long reg) val 441 drivers/usb/gadget/udc/pch_udc.c iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg); val 480 drivers/usb/gadget/udc/pch_udc.c static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val, val 486 drivers/usb/gadget/udc/pch_udc.c pch_udc_writel(dev, val, reg); val 836 drivers/usb/gadget/udc/pch_udc.c u32 val) val 838 drivers/usb/gadget/udc/pch_udc.c pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR); val 857 drivers/usb/gadget/udc/pch_udc.c u32 val) val 859 drivers/usb/gadget/udc/pch_udc.c pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR); val 978 drivers/usb/gadget/udc/pch_udc.c u32 val = 0; val 991 drivers/usb/gadget/udc/pch_udc.c val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT | val 1000 drivers/usb/gadget/udc/pch_udc.c pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num)); val 1002 drivers/usb/gadget/udc/pch_udc.c pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num)); val 2489 drivers/usb/gadget/udc/pch_udc.c u32 val; val 2509 drivers/usb/gadget/udc/pch_udc.c val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT; val 2510 drivers/usb/gadget/udc/pch_udc.c pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX); val 297 drivers/usb/gadget/udc/pxa25x_udc.c static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val) val 299 drivers/usb/gadget/udc/pxa25x_udc.c iowrite32be(val, dev->regs + reg); val 307 drivers/usb/gadget/udc/pxa25x_udc.c static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val) val 309 drivers/usb/gadget/udc/pxa25x_udc.c writel(val, dev->regs + reg); val 173 drivers/usb/gadget/udc/r8a66597-udc.h static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, val 176 drivers/usb/gadget/udc/r8a66597-udc.h iowrite16(val, r8a66597->reg + offset); val 180 drivers/usb/gadget/udc/r8a66597-udc.h u16 val, u16 pat, unsigned long offset) val 185 drivers/usb/gadget/udc/r8a66597-udc.h tmp = tmp | val; val 189 drivers/usb/gadget/udc/r8a66597-udc.h #define r8a66597_bclr(r8a66597, val, offset) \ val 190 drivers/usb/gadget/udc/r8a66597-udc.h r8a66597_mdfy(r8a66597, 0, val, offset) val 191 drivers/usb/gadget/udc/r8a66597-udc.h #define r8a66597_bset(r8a66597, val, offset) \ val 192 drivers/usb/gadget/udc/r8a66597-udc.h r8a66597_mdfy(r8a66597, val, 0, offset) val 263 drivers/usb/gadget/udc/r8a66597-udc.h static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val, val 266 drivers/usb/gadget/udc/r8a66597-udc.h iowrite32(val, r8a66597->sudmac_reg + offset); val 408 drivers/usb/gadget/udc/renesas_usb3.c u32 val = usb3_read(usb3, offs); val 410 drivers/usb/gadget/udc/renesas_usb3.c val |= bits; val 411 drivers/usb/gadget/udc/renesas_usb3.c usb3_write(usb3, val, offs); val 416 drivers/usb/gadget/udc/renesas_usb3.c u32 val = usb3_read(usb3, offs); val 418 drivers/usb/gadget/udc/renesas_usb3.c val &= ~bits; val 419 drivers/usb/gadget/udc/renesas_usb3.c usb3_write(usb3, val, offs); val 511 drivers/usb/gadget/udc/renesas_usb3.c u32 val = usb3_read(usb3, USB3_USB20_CON); val 513 drivers/usb/gadget/udc/renesas_usb3.c val &= ~USB20_CON_B2_TSTMOD_MASK; val 514 drivers/usb/gadget/udc/renesas_usb3.c val |= USB20_CON_B2_TSTMOD(usb3->test_mode); val 515 drivers/usb/gadget/udc/renesas_usb3.c usb3_write(usb3, val | USB20_CON_B2_TSTMOD_EN, USB3_USB20_CON); val 548 drivers/usb/gadget/udc/renesas_usb3.c u32 val = usb3_read(usb3, USB3_SSIFCMD); val 552 drivers/usb/gadget/udc/renesas_usb3.c if (!(val & mask_u2)) val 554 drivers/usb/gadget/udc/renesas_usb3.c if (!(val & mask_u1)) val 945 drivers/usb/gadget/udc/renesas_usb3.c u32 val = usb3_read(usb3, USB3_P0_CON); val 947 drivers/usb/gadget/udc/renesas_usb3.c val &= ~(P0_CON_ST_RES_MASK | P0_CON_OT_RES_MASK | P0_CON_IN_RES_MASK); val 948 drivers/usb/gadget/udc/renesas_usb3.c val |= res | P0_CON_RES_WEN; val 949 drivers/usb/gadget/udc/renesas_usb3.c usb3_write(usb3, val, USB3_P0_CON); val 1013 drivers/usb/gadget/udc/renesas_usb3.c u32 val = usb3_read(usb3, USB3_PN_CON); val 1015 drivers/usb/gadget/udc/renesas_usb3.c val &= ~PN_CON_RES_MASK; val 1016 drivers/usb/gadget/udc/renesas_usb3.c val |= res & PN_CON_RES_MASK; val 1017 drivers/usb/gadget/udc/renesas_usb3.c val |= PN_CON_RES_WEN; val 1018 drivers/usb/gadget/udc/renesas_usb3.c usb3_write(usb3, val, USB3_PN_CON); val 1068 drivers/usb/gadget/udc/renesas_usb3.c u32 val = usb3_read(usb3, con_reg); val 1070 drivers/usb/gadget/udc/renesas_usb3.c val |= PX_CON_SEND | PX_CON_BYTE_EN_BYTES(bytes); val 1071 drivers/usb/gadget/udc/renesas_usb3.c val |= (usb3_ep->num && last) ? PN_CON_LAST : 0; val 1072 drivers/usb/gadget/udc/renesas_usb3.c usb3_write(usb3, val, con_reg); val 2076 drivers/usb/gadget/udc/renesas_usb3.c u32 val = 0; val 2078 drivers/usb/gadget/udc/renesas_usb3.c val |= usb3_ep->dir_in ? PN_MOD_DIR : 0; val 2079 drivers/usb/gadget/udc/renesas_usb3.c val |= PN_MOD_TYPE(usb_endpoint_type(desc)); val 2080 drivers/usb/gadget/udc/renesas_usb3.c val |= PN_MOD_EPNUM(usb_endpoint_num(desc)); val 2081 drivers/usb/gadget/udc/renesas_usb3.c usb3_write(usb3, val, USB3_PN_MOD); val 2629 drivers/usb/gadget/udc/renesas_usb3.c u32 val; val 2654 drivers/usb/gadget/udc/renesas_usb3.c val = PN_RAMMAP_RAMIF(*cur_ramif); val 2655 drivers/usb/gadget/udc/renesas_usb3.c val |= usb3_calc_ramarea(priv->ramsize_per_pipe); val 2656 drivers/usb/gadget/udc/renesas_usb3.c val |= PN_RAMMAP_BASEAD(*cur_basead); val 2657 drivers/usb/gadget/udc/renesas_usb3.c usb3_ep->rammap_val = val; val 2660 drivers/usb/gadget/udc/renesas_usb3.c i, val, *cur_ramif, *cur_basead); val 184 drivers/usb/gadget/udc/s3c-hsudc.c static inline void __orr32(void __iomem *ptr, u32 val) val 186 drivers/usb/gadget/udc/s3c-hsudc.c writel(readl(ptr) | val, ptr); val 218 drivers/usb/gadget/udc/udc-xilinx.c static void xudc_write32(void __iomem *addr, u32 offset, u32 val) val 220 drivers/usb/gadget/udc/udc-xilinx.c iowrite32(val, addr + offset); val 239 drivers/usb/gadget/udc/udc-xilinx.c static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val) val 241 drivers/usb/gadget/udc/udc-xilinx.c iowrite32be(val, addr + offset); val 54 drivers/usb/host/bcma-hcd.c u32 val; val 57 drivers/usb/host/bcma-hcd.c val = bcma_read32(dev, reg); val 58 drivers/usb/host/bcma-hcd.c if ((val & bitmask) == bitmask) val 243 drivers/usb/host/bcma-hcd.c u32 val; val 246 drivers/usb/host/bcma-hcd.c val = bcma_read32(dev, 0x94); val 247 drivers/usb/host/bcma-hcd.c val &= 0xffff; val 248 drivers/usb/host/bcma-hcd.c val |= 0x80 << 16; val 249 drivers/usb/host/bcma-hcd.c bcma_write32(dev, 0x94, val); val 252 drivers/usb/host/bcma-hcd.c val = bcma_read32(dev, 0x9c); val 253 drivers/usb/host/bcma-hcd.c val |= 1; val 254 drivers/usb/host/bcma-hcd.c bcma_write32(dev, 0x9c, val); val 284 drivers/usb/host/bcma-hcd.c static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val) val 291 drivers/usb/host/bcma-hcd.c gpiod_set_value(usb_dev->gpio_desc, val); val 60 drivers/usb/host/ehci-omap.c static inline void ehci_write(void __iomem *base, u32 reg, u32 val) val 62 drivers/usb/host/ehci-omap.c __raw_writel(val, base + reg); val 26 drivers/usb/host/ehci-orion.c #define wrl(off, val) writel_relaxed((val), hcd->regs + (off)) val 44 drivers/usb/host/ehci-pmcmsp.c u32 val; val 53 drivers/usb/host/ehci-pmcmsp.c val = ehci_readl(ehci, (u32 *)base); val 54 drivers/usb/host/ehci-pmcmsp.c ehci_writel(ehci, (val | USB_CTRL_MODE_STREAM_DISABLE), val 58 drivers/usb/host/ehci-pmcmsp.c val = ehci_readl(ehci, (u32 *)statreg); val 59 drivers/usb/host/ehci-pmcmsp.c val = val & ~USB_EHCI_REG_BIT_STAT_STS; val 60 drivers/usb/host/ehci-pmcmsp.c ehci_writel(ehci, val, (u32 *)statreg); val 735 drivers/usb/host/ehci.h #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) val 751 drivers/usb/host/ehci.h static inline void imx28_ehci_writel(const unsigned int val, val 754 drivers/usb/host/ehci.h __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); val 757 drivers/usb/host/ehci.h static inline void imx28_ehci_writel(const unsigned int val, val 763 drivers/usb/host/ehci.h const unsigned int val, __u32 __iomem *regs) val 767 drivers/usb/host/ehci.h writel_be(val, regs) : val 768 drivers/usb/host/ehci.h writel(val, regs); val 771 drivers/usb/host/ehci.h imx28_ehci_writel(val, regs); val 773 drivers/usb/host/ehci.h writel(val, regs); val 659 drivers/usb/host/fotg210.h const unsigned int val, __u32 __iomem *regs) val 661 drivers/usb/host/fotg210.h writel(val, regs); val 1282 drivers/usb/host/isp116x-hcd.c u32 val; val 1289 drivers/usb/host/isp116x-hcd.c val = isp116x_read_reg32(isp116x, HCRHDESCA); val 1290 drivers/usb/host/isp116x-hcd.c val &= ~(RH_A_NPS | RH_A_PSM); val 1291 drivers/usb/host/isp116x-hcd.c isp116x_write_reg32(isp116x, HCRHDESCA, val); val 1305 drivers/usb/host/isp116x-hcd.c u32 val; val 1314 drivers/usb/host/isp116x-hcd.c val = isp116x_read_reg16(isp116x, HCCHIPID); val 1315 drivers/usb/host/isp116x-hcd.c if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) { val 1316 drivers/usb/host/isp116x-hcd.c ERR("Invalid chip ID %04x\n", val); val 1328 drivers/usb/host/isp116x-hcd.c val = HCHWCFG_INT_ENABLE | HCHWCFG_DBWIDTH(1); val 1330 drivers/usb/host/isp116x-hcd.c val |= HCHWCFG_15KRSEL; val 1333 drivers/usb/host/isp116x-hcd.c val |= HCHWCFG_CLKNOTSTOP; val 1335 drivers/usb/host/isp116x-hcd.c val |= HCHWCFG_ANALOG_OC; val 1337 drivers/usb/host/isp116x-hcd.c val |= HCHWCFG_INT_POL; val 1339 drivers/usb/host/isp116x-hcd.c val |= HCHWCFG_INT_TRIGGER; val 1340 drivers/usb/host/isp116x-hcd.c isp116x_write_reg16(isp116x, HCHWCFG, val); val 1343 drivers/usb/host/isp116x-hcd.c val = (25 << 24) & RH_A_POTPGT; val 1347 drivers/usb/host/isp116x-hcd.c val |= RH_A_PSM; val 1349 drivers/usb/host/isp116x-hcd.c val |= RH_A_OCPM; val 1350 drivers/usb/host/isp116x-hcd.c isp116x_write_reg32(isp116x, HCRHDESCA, val); val 1353 drivers/usb/host/isp116x-hcd.c val = RH_B_PPCM; val 1354 drivers/usb/host/isp116x-hcd.c isp116x_write_reg32(isp116x, HCRHDESCB, val); val 1357 drivers/usb/host/isp116x-hcd.c val = 0; val 1361 drivers/usb/host/isp116x-hcd.c val |= RH_HS_DRWE; val 1363 drivers/usb/host/isp116x-hcd.c isp116x_write_reg32(isp116x, HCRHSTATUS, val); val 1379 drivers/usb/host/isp116x-hcd.c val = HCCONTROL_USB_OPER; val 1381 drivers/usb/host/isp116x-hcd.c val |= HCCONTROL_RWE; val 1382 drivers/usb/host/isp116x-hcd.c isp116x_write_reg32(isp116x, HCCONTROL, val); val 1399 drivers/usb/host/isp116x-hcd.c u32 val; val 1403 drivers/usb/host/isp116x-hcd.c val = isp116x_read_reg32(isp116x, HCCONTROL); val 1405 drivers/usb/host/isp116x-hcd.c switch (val & HCCONTROL_HCFS) { val 1408 drivers/usb/host/isp116x-hcd.c val &= (~HCCONTROL_HCFS & ~HCCONTROL_RWE); val 1409 drivers/usb/host/isp116x-hcd.c val |= HCCONTROL_USB_SUSPEND; val 1411 drivers/usb/host/isp116x-hcd.c val |= HCCONTROL_RWE; val 1415 drivers/usb/host/isp116x-hcd.c isp116x_write_reg32(isp116x, HCCONTROL, val); val 1422 drivers/usb/host/isp116x-hcd.c (val & ~HCCONTROL_HCFS) | val 1439 drivers/usb/host/isp116x-hcd.c u32 val; val 1444 drivers/usb/host/isp116x-hcd.c val = isp116x_read_reg32(isp116x, HCCONTROL); val 1445 drivers/usb/host/isp116x-hcd.c switch (val & HCCONTROL_HCFS) { val 1447 drivers/usb/host/isp116x-hcd.c val &= ~HCCONTROL_HCFS; val 1448 drivers/usb/host/isp116x-hcd.c val |= HCCONTROL_USB_RESUME; val 1449 drivers/usb/host/isp116x-hcd.c isp116x_write_reg32(isp116x, HCCONTROL, val); val 1470 drivers/usb/host/isp116x-hcd.c val = isp116x->rhdesca & RH_A_NDP; val 1471 drivers/usb/host/isp116x-hcd.c while (val--) { val 1473 drivers/usb/host/isp116x-hcd.c isp116x_read_reg32(isp116x, val ? HCRHPORT2 : HCRHPORT1); val 1477 drivers/usb/host/isp116x-hcd.c DBG("%s: Resuming port %d\n", __func__, val); val 1478 drivers/usb/host/isp116x-hcd.c isp116x_write_reg32(isp116x, RH_PS_POCI, val val 1488 drivers/usb/host/isp116x-hcd.c val = isp116x_read_reg32(isp116x, HCCONTROL); val 1490 drivers/usb/host/isp116x-hcd.c (val & ~HCCONTROL_HCFS) | HCCONTROL_USB_OPER); val 364 drivers/usb/host/isp116x.h static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val) val 366 drivers/usb/host/isp116x.h writew(val, isp116x->data_reg); val 370 drivers/usb/host/isp116x.h static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val) val 372 drivers/usb/host/isp116x.h __raw_writew(val, isp116x->data_reg); val 378 drivers/usb/host/isp116x.h u16 val; val 380 drivers/usb/host/isp116x.h val = readw(isp116x->data_reg); val 382 drivers/usb/host/isp116x.h return val; val 387 drivers/usb/host/isp116x.h u16 val; val 389 drivers/usb/host/isp116x.h val = __raw_readw(isp116x->data_reg); val 391 drivers/usb/host/isp116x.h return val; val 394 drivers/usb/host/isp116x.h static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val) val 396 drivers/usb/host/isp116x.h writew(val & 0xffff, isp116x->data_reg); val 398 drivers/usb/host/isp116x.h writew(val >> 16, isp116x->data_reg); val 404 drivers/usb/host/isp116x.h u32 val; val 406 drivers/usb/host/isp116x.h val = (u32) readw(isp116x->data_reg); val 408 drivers/usb/host/isp116x.h val |= ((u32) readw(isp116x->data_reg)) << 16; val 410 drivers/usb/host/isp116x.h return val; val 429 drivers/usb/host/isp116x.h unsigned val) val 432 drivers/usb/host/isp116x.h isp116x_write_data16(isp116x, (u16) (val & 0xffff)); val 436 drivers/usb/host/isp116x.h unsigned val) val 439 drivers/usb/host/isp116x.h isp116x_write_data32(isp116x, (u32) val); val 595 drivers/usb/host/isp1362.h static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val) val 598 drivers/usb/host/isp1362.h writew(val, isp1362_hcd->data_reg); val 603 drivers/usb/host/isp1362.h u16 val; val 606 drivers/usb/host/isp1362.h val = readw(isp1362_hcd->data_reg); val 608 drivers/usb/host/isp1362.h return val; val 611 drivers/usb/host/isp1362.h static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val) val 615 drivers/usb/host/isp1362.h writel(val, isp1362_hcd->data_reg); val 618 drivers/usb/host/isp1362.h writew((u16)val, isp1362_hcd->data_reg); val 620 drivers/usb/host/isp1362.h writew(val >> 16, isp1362_hcd->data_reg); val 626 drivers/usb/host/isp1362.h u32 val; val 630 drivers/usb/host/isp1362.h val = readl(isp1362_hcd->data_reg); val 633 drivers/usb/host/isp1362.h val = (u32)readw(isp1362_hcd->data_reg); val 635 drivers/usb/host/isp1362.h val |= (u32)readw(isp1362_hcd->data_reg) << 16; val 637 drivers/usb/host/isp1362.h return val; val 332 drivers/usb/host/max3421-hcd.c #define field(val, bit) ((val) << (bit)) val 379 drivers/usb/host/max3421-hcd.c spi_wr8(struct usb_hcd *hcd, unsigned int reg, u8 val) val 393 drivers/usb/host/max3421-hcd.c max3421_hcd->tx->data[1] = val; val 1460 drivers/usb/host/max3421-hcd.c u8 val = spi_rd8(hcd, MAX3421_REG_IOPINS1); val 1462 drivers/usb/host/max3421-hcd.c val = ((val & 0xf0) | val 1464 drivers/usb/host/max3421-hcd.c spi_wr8(hcd, MAX3421_REG_IOPINS1 + i, val); val 1465 drivers/usb/host/max3421-hcd.c max3421_hcd->iopins[i] = val; val 470 drivers/usb/host/ohci-at91.c int val, port; val 484 drivers/usb/host/ohci-at91.c val = gpiod_get_value(pdata->overcurrent_pin[port]); val 489 drivers/usb/host/ohci-at91.c if (!val) { val 496 drivers/usb/host/ohci-at91.c val ? "exited" : "notified"); val 547 drivers/usb/host/ohci-hcd.c u32 mask, val; val 556 drivers/usb/host/ohci-hcd.c val = ohci_readl (ohci, &ohci->regs->fminterval); val 557 drivers/usb/host/ohci-hcd.c ohci->fminterval = val & 0x3fff; val 576 drivers/usb/host/ohci-hcd.c val = 0; val 582 drivers/usb/host/ohci-hcd.c val = 10 /* msec wait */; val 588 drivers/usb/host/ohci-hcd.c val = 50 /* msec wait */; val 594 drivers/usb/host/ohci-hcd.c msleep(val); val 604 drivers/usb/host/ohci-hcd.c val = 30; /* ... allow extra time */ val 606 drivers/usb/host/ohci-hcd.c if (--val == 0) { val 675 drivers/usb/host/ohci-hcd.c val = roothub_a (ohci); val 676 drivers/usb/host/ohci-hcd.c val &= ~(RH_A_PSM | RH_A_OCPM); val 679 drivers/usb/host/ohci-hcd.c val |= RH_A_NOCP; val 680 drivers/usb/host/ohci-hcd.c val &= ~(RH_A_POTPGT | RH_A_NPS); val 681 drivers/usb/host/ohci-hcd.c ohci_writel (ohci, val, &ohci->regs->roothub.a); val 687 drivers/usb/host/ohci-hcd.c val |= RH_A_NPS; val 688 drivers/usb/host/ohci-hcd.c ohci_writel (ohci, val, &ohci->regs->roothub.a); val 691 drivers/usb/host/ohci-hcd.c ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, val 700 drivers/usb/host/ohci-hcd.c mdelay ((val >> 23) & 0x1fe); val 574 drivers/usb/host/ohci.h const unsigned int val, __hc32 __iomem *regs) val 578 drivers/usb/host/ohci.h writel_be (val, regs) : val 579 drivers/usb/host/ohci.h writel (val, regs); val 581 drivers/usb/host/ohci.h writel (val, regs); val 684 drivers/usb/host/oxu210hp-hcd.c static inline void oxu_writel(void *base, u32 reg, u32 val) val 686 drivers/usb/host/oxu210hp-hcd.c writel(val, base + reg); val 339 drivers/usb/host/pci-quirks.c u32 addr, addr_low, addr_high, val; val 371 drivers/usb/host/pci-quirks.c val = inl_p(AB_DATA(addr)); val 379 drivers/usb/host/pci-quirks.c val = inl(AB_DATA(addr)); val 386 drivers/usb/host/pci-quirks.c val &= ~0x08; val 387 drivers/usb/host/pci-quirks.c val |= (1 << 4) | (1 << 9); val 389 drivers/usb/host/pci-quirks.c val |= 0x08; val 390 drivers/usb/host/pci-quirks.c val &= ~((1 << 4) | (1 << 9)); val 392 drivers/usb/host/pci-quirks.c outl_p(val, AB_DATA(addr)); val 404 drivers/usb/host/pci-quirks.c NB_PCIE_INDX_DATA, &val); val 406 drivers/usb/host/pci-quirks.c val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); val 407 drivers/usb/host/pci-quirks.c val |= bit | (bit << 3) | (bit << 12); val 408 drivers/usb/host/pci-quirks.c val |= ((!bit) << 4) | ((!bit) << 9); val 410 drivers/usb/host/pci-quirks.c NB_PCIE_INDX_DATA, val); val 416 drivers/usb/host/pci-quirks.c NB_PCIE_INDX_DATA, &val); val 417 drivers/usb/host/pci-quirks.c val &= ~(1 << 8); val 418 drivers/usb/host/pci-quirks.c val |= bit << 8; val 421 drivers/usb/host/pci-quirks.c NB_PCIE_INDX_DATA, val); val 427 drivers/usb/host/pci-quirks.c NB_PCIE_INDX_DATA, &val); val 429 drivers/usb/host/pci-quirks.c val &= ~(0x3f << 7); val 431 drivers/usb/host/pci-quirks.c val |= 0x3f << 7; val 434 drivers/usb/host/pci-quirks.c NB_PCIE_INDX_DATA, val); val 440 drivers/usb/host/pci-quirks.c NB_PCIE_INDX_DATA, &val); val 442 drivers/usb/host/pci-quirks.c val &= ~(0x3f << 7); val 444 drivers/usb/host/pci-quirks.c val |= 0x3f << 7; val 447 drivers/usb/host/pci-quirks.c NB_PCIE_INDX_DATA, val); val 882 drivers/usb/host/pci-quirks.c pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); val 884 drivers/usb/host/pci-quirks.c val | EHCI_USBLEGCTLSTS_SOOE); val 929 drivers/usb/host/pci-quirks.c u32 hcc_params, cap, val; val 971 drivers/usb/host/pci-quirks.c val = readl(op_reg_base + EHCI_USBSTS); val 972 drivers/usb/host/pci-quirks.c if ((val & EHCI_USBSTS_HALTED) == 0) { val 973 drivers/usb/host/pci-quirks.c val = readl(op_reg_base + EHCI_USBCMD); val 974 drivers/usb/host/pci-quirks.c val &= ~EHCI_USBCMD_RUN; val 975 drivers/usb/host/pci-quirks.c writel(val, op_reg_base + EHCI_USBCMD); val 982 drivers/usb/host/pci-quirks.c val = readl(op_reg_base + EHCI_USBSTS); val 983 drivers/usb/host/pci-quirks.c if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { val 1146 drivers/usb/host/pci-quirks.c u32 val; val 1166 drivers/usb/host/pci-quirks.c if ((ext_cap_offset + sizeof(val)) > len) { val 1171 drivers/usb/host/pci-quirks.c val = readl(base + ext_cap_offset); val 1177 drivers/usb/host/pci-quirks.c val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED; val 1178 drivers/usb/host/pci-quirks.c writel(val, base + ext_cap_offset); val 1182 drivers/usb/host/pci-quirks.c if (val & XHCI_HC_BIOS_OWNED) { val 1183 drivers/usb/host/pci-quirks.c writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); val 1193 drivers/usb/host/pci-quirks.c val); val 1194 drivers/usb/host/pci-quirks.c writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); val 1198 drivers/usb/host/pci-quirks.c val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); val 1200 drivers/usb/host/pci-quirks.c val &= XHCI_LEGACY_DISABLE_SMI; val 1202 drivers/usb/host/pci-quirks.c val |= XHCI_LEGACY_SMI_EVENTS; val 1204 drivers/usb/host/pci-quirks.c writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); val 1219 drivers/usb/host/pci-quirks.c val = readl(op_reg_base + XHCI_STS_OFFSET); val 1222 drivers/usb/host/pci-quirks.c val); val 1226 drivers/usb/host/pci-quirks.c val = readl(op_reg_base + XHCI_CMD_OFFSET); val 1227 drivers/usb/host/pci-quirks.c val &= ~(XHCI_CMD_RUN | XHCI_IRQS); val 1228 drivers/usb/host/pci-quirks.c writel(val, op_reg_base + XHCI_CMD_OFFSET); val 1234 drivers/usb/host/pci-quirks.c val = readl(op_reg_base + XHCI_STS_OFFSET); val 1237 drivers/usb/host/pci-quirks.c XHCI_MAX_HALT_USEC, val); val 71 drivers/usb/host/r8a66597-hcd.c u16 val; val 74 drivers/usb/host/r8a66597-hcd.c val = (upphub << 11) | (hubport << 8) | (usbspd << 6) | (port & 0x0001); val 75 drivers/usb/host/r8a66597-hcd.c r8a66597_write(r8a66597, val, devadd_reg); val 138 drivers/usb/host/r8a66597-hcd.c u16 val; val 140 drivers/usb/host/r8a66597-hcd.c val = port ? DRPD : DCFM | DRPD; val 141 drivers/usb/host/r8a66597-hcd.c r8a66597_bset(r8a66597, val, get_syscfg_reg(port)); val 151 drivers/usb/host/r8a66597-hcd.c u16 val, tmp; val 163 drivers/usb/host/r8a66597-hcd.c val = port ? DRPD : DCFM | DRPD; val 164 drivers/usb/host/r8a66597-hcd.c r8a66597_bclr(r8a66597, val, get_syscfg_reg(port)); val 607 drivers/usb/host/r8a66597-hcd.c u16 val = 0; val 616 drivers/usb/host/r8a66597-hcd.c val |= R8A66597_DIR; val 618 drivers/usb/host/r8a66597-hcd.c val |= R8A66597_DBLB | R8A66597_SHTNAK; val 619 drivers/usb/host/r8a66597-hcd.c val |= info->type | info->epnum; val 620 drivers/usb/host/r8a66597-hcd.c r8a66597_write(r8a66597, val, PIPECFG); val 187 drivers/usb/host/r8a66597.h static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, val 190 drivers/usb/host/r8a66597.h iowrite16(val, r8a66597->reg + offset); val 194 drivers/usb/host/r8a66597.h u16 val, u16 pat, unsigned long offset) val 199 drivers/usb/host/r8a66597.h tmp = tmp | val; val 203 drivers/usb/host/r8a66597.h #define r8a66597_bclr(r8a66597, val, offset) \ val 204 drivers/usb/host/r8a66597.h r8a66597_mdfy(r8a66597, 0, val, offset) val 205 drivers/usb/host/r8a66597.h #define r8a66597_bset(r8a66597, val, offset) \ val 206 drivers/usb/host/r8a66597.h r8a66597_mdfy(r8a66597, val, 0, offset) val 204 drivers/usb/host/sl811.h static inline void sl811_write(struct sl811 *sl811, int reg, u8 val) val 207 drivers/usb/host/sl811.h writeb(val, sl811->data_reg); val 519 drivers/usb/host/uhci-hcd.h static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) val 521 drivers/usb/host/uhci-hcd.h outl(val, uhci->io_addr + reg); val 529 drivers/usb/host/uhci-hcd.h static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) val 531 drivers/usb/host/uhci-hcd.h outw(val, uhci->io_addr + reg); val 539 drivers/usb/host/uhci-hcd.h static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) val 541 drivers/usb/host/uhci-hcd.h outb(val, uhci->io_addr + reg); val 605 drivers/usb/host/uhci-hcd.h static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) val 608 drivers/usb/host/uhci-hcd.h outl(val, uhci->io_addr + reg); val 610 drivers/usb/host/uhci-hcd.h writel(val, uhci->regs + uhci_aspeed_reg(reg)); val 613 drivers/usb/host/uhci-hcd.h writel_be(val, uhci->regs + reg); val 616 drivers/usb/host/uhci-hcd.h writel(val, uhci->regs + reg); val 633 drivers/usb/host/uhci-hcd.h static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) val 636 drivers/usb/host/uhci-hcd.h outw(val, uhci->io_addr + reg); val 638 drivers/usb/host/uhci-hcd.h writel(val, uhci->regs + uhci_aspeed_reg(reg)); val 641 drivers/usb/host/uhci-hcd.h writew_be(val, uhci->regs + reg); val 644 drivers/usb/host/uhci-hcd.h writew(val, uhci->regs + reg); val 661 drivers/usb/host/uhci-hcd.h static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) val 664 drivers/usb/host/uhci-hcd.h outb(val, uhci->io_addr + reg); val 666 drivers/usb/host/uhci-hcd.h writel(val, uhci->regs + uhci_aspeed_reg(reg)); val 669 drivers/usb/host/uhci-hcd.h writeb_be(val, uhci->regs + reg); val 672 drivers/usb/host/uhci-hcd.h writeb(val, uhci->regs + reg); val 86 drivers/usb/host/xhci-ext-caps.c u32 offset, val; val 92 drivers/usb/host/xhci-ext-caps.c val = readl(base + offset); val 94 drivers/usb/host/xhci-ext-caps.c switch (XHCI_EXT_CAPS_ID(val)) { val 99 drivers/usb/host/xhci-ext-caps.h u32 val; val 105 drivers/usb/host/xhci-ext-caps.h val = readl(base + XHCI_HCC_PARAMS_OFFSET); val 106 drivers/usb/host/xhci-ext-caps.h if (val == ~0) val 108 drivers/usb/host/xhci-ext-caps.h offset = XHCI_HCC_EXT_CAPS(val) << 2; val 113 drivers/usb/host/xhci-ext-caps.h val = readl(base + offset); val 114 drivers/usb/host/xhci-ext-caps.h if (val == ~0) val 116 drivers/usb/host/xhci-ext-caps.h if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id)) val 119 drivers/usb/host/xhci-ext-caps.h next = XHCI_EXT_CAPS_NEXT(val); val 102 drivers/usb/host/xhci-mem.c u32 val; val 112 drivers/usb/host/xhci-mem.c val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); val 113 drivers/usb/host/xhci-mem.c val &= ~TRB_TYPE_BITMASK; val 114 drivers/usb/host/xhci-mem.c val |= TRB_TYPE(TRB_LINK); val 120 drivers/usb/host/xhci-mem.c val |= TRB_CHAIN; val 121 drivers/usb/host/xhci-mem.c prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); val 1803 drivers/usb/host/xhci-mem.c unsigned int val; val 1816 drivers/usb/host/xhci-mem.c for (val = 0; val < evt_ring->num_segs; val++) { val 1817 drivers/usb/host/xhci-mem.c entry = &erst->entries[val]; val 2376 drivers/usb/host/xhci-mem.c unsigned int val, val2; val 2410 drivers/usb/host/xhci-mem.c val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1)); val 2412 drivers/usb/host/xhci-mem.c "// xHC can handle at most %d device slots.", val); val 2414 drivers/usb/host/xhci-mem.c val |= (val2 & ~HCS_SLOTS_MASK); val 2416 drivers/usb/host/xhci-mem.c "// Setting Max device slots reg = 0x%x.", val); val 2417 drivers/usb/host/xhci-mem.c writel(val, &xhci->op_regs->config_reg); val 2493 drivers/usb/host/xhci-mem.c val = readl(&xhci->cap_regs->db_off); val 2494 drivers/usb/host/xhci-mem.c val &= DBOFF_MASK; val 2497 drivers/usb/host/xhci-mem.c " from cap regs base addr", val); val 2498 drivers/usb/host/xhci-mem.c xhci->dba = (void __iomem *) xhci->cap_regs + val; val 2519 drivers/usb/host/xhci-mem.c val = readl(&xhci->ir_set->erst_size); val 2520 drivers/usb/host/xhci-mem.c val &= ERST_SIZE_MASK; val 2521 drivers/usb/host/xhci-mem.c val |= ERST_NUM_SEGS; val 2524 drivers/usb/host/xhci-mem.c val); val 2525 drivers/usb/host/xhci-mem.c writel(val, &xhci->ir_set->erst_size); val 295 drivers/usb/host/xhci-mtk.c u32 reg, msk, val; val 301 drivers/usb/host/xhci-mtk.c val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; val 306 drivers/usb/host/xhci-mtk.c val = enable ? msk : 0; val 311 drivers/usb/host/xhci-mtk.c regmap_update_bits(mtk->uwk, reg, msk, val); val 419 drivers/usb/host/xhci-pci.c u32 val; val 429 drivers/usb/host/xhci-pci.c val = readl(reg) & ~PROG_DONE; val 430 drivers/usb/host/xhci-pci.c writel(val, reg); val 433 drivers/usb/host/xhci-pci.c val = readl(reg); val 435 drivers/usb/host/xhci-pci.c val |= SSIC_PORT_UNUSED; val 437 drivers/usb/host/xhci-pci.c val &= ~SSIC_PORT_UNUSED; val 438 drivers/usb/host/xhci-pci.c writel(val, reg); val 441 drivers/usb/host/xhci-pci.c val = readl(reg) | PROG_DONE; val 442 drivers/usb/host/xhci-pci.c writel(val, reg); val 455 drivers/usb/host/xhci-pci.c u32 val; val 458 drivers/usb/host/xhci-pci.c val = readl(reg); val 459 drivers/usb/host/xhci-pci.c writel(val | BIT(28), reg); val 132 drivers/usb/host/xhci-rcar.c u32 data, val, temp; val 170 drivers/usb/host/xhci-rcar.c val = readl(regs + RCAR_USB3_DL_CTRL); val 171 drivers/usb/host/xhci-rcar.c if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0) val 186 drivers/usb/host/xhci-rcar.c val = readl(regs + RCAR_USB3_DL_CTRL); val 187 drivers/usb/host/xhci-rcar.c if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) { val 204 drivers/usb/host/xhci-rcar.c u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK; val 207 drivers/usb/host/xhci-rcar.c val = readl(hcd->regs + RCAR_USB3_AXH_STA); val 208 drivers/usb/host/xhci-rcar.c if ((val & mask) == mask) val 230 drivers/usb/host/xhci.c u64 val; val 252 drivers/usb/host/xhci.c val = readl(&xhci->op_regs->command); val 253 drivers/usb/host/xhci.c val &= ~CMD_HSEIE; val 254 drivers/usb/host/xhci.c writel(val, &xhci->op_regs->command); val 257 drivers/usb/host/xhci.c val = readl(&xhci->op_regs->status); val 258 drivers/usb/host/xhci.c val |= STS_FATAL; val 259 drivers/usb/host/xhci.c writel(val, &xhci->op_regs->status); val 262 drivers/usb/host/xhci.c val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); val 263 drivers/usb/host/xhci.c if (upper_32_bits(val)) val 265 drivers/usb/host/xhci.c val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); val 266 drivers/usb/host/xhci.c if (upper_32_bits(val)) val 273 drivers/usb/host/xhci.c val = xhci_read_64(xhci, &ir->erst_base); val 274 drivers/usb/host/xhci.c if (upper_32_bits(val)) val 276 drivers/usb/host/xhci.c val= xhci_read_64(xhci, &ir->erst_dequeue); val 277 drivers/usb/host/xhci.c if (upper_32_bits(val)) val 1961 drivers/usb/host/xhci.h const u64 val, __le64 __iomem *regs) val 1963 drivers/usb/host/xhci.h lo_hi_writeq(val, regs); val 60 drivers/usb/isp1760/isp1760-core.h static inline void isp1760_write32(void __iomem *base, u32 reg, u32 val) val 62 drivers/usb/isp1760/isp1760-core.h writel(val, base + reg); val 168 drivers/usb/isp1760/isp1760-hcd.c static void reg_write32(void __iomem *base, u32 reg, u32 val) val 170 drivers/usb/isp1760/isp1760-hcd.c isp1760_write32(base, reg, val); val 190 drivers/usb/isp1760/isp1760-hcd.c u32 val; val 219 drivers/usb/isp1760/isp1760-hcd.c val = le32_to_cpu(__raw_readl(src)); val 221 drivers/usb/isp1760/isp1760-hcd.c val = __raw_readl(src); val 224 drivers/usb/isp1760/isp1760-hcd.c src_byteptr = (void *) &val; val 53 drivers/usb/isp1760/isp1760-udc.c static inline void isp1760_udc_write(struct isp1760_udc *udc, u16 reg, u32 val) val 55 drivers/usb/isp1760/isp1760-udc.c isp1760_write32(udc->regs, reg, val); val 203 drivers/usb/misc/lvstest.c unsigned long val; val 206 drivers/usb/misc/lvstest.c ret = kstrtoul(buf, 10, &val); val 212 drivers/usb/misc/lvstest.c if (val > 127) val 215 drivers/usb/misc/lvstest.c ret = lvs_rh_set_port_feature(hdev, lvs->portnum | (val << 8), val 218 drivers/usb/misc/lvstest.c dev_err(dev, "Error %d while setting U2 timeout %ld\n", ret, val); val 232 drivers/usb/misc/lvstest.c unsigned long val; val 235 drivers/usb/misc/lvstest.c ret = kstrtoul(buf, 10, &val); val 241 drivers/usb/misc/lvstest.c if (val > 127) val 244 drivers/usb/misc/lvstest.c ret = lvs_rh_set_port_feature(hdev, lvs->portnum | (val << 8), val 247 drivers/usb/misc/lvstest.c dev_err(dev, "Error %d while setting U1 timeout %ld\n", ret, val); val 250 drivers/usb/misc/usb3503.c int val = hub->secondary_ref_clk ? GPIOF_OUT_INIT_LOW : val 252 drivers/usb/misc/usb3503.c err = devm_gpio_request_one(dev, hub->gpio_intn, val, val 192 drivers/usb/misc/uss720.c static int get_1284_register(struct parport *pp, unsigned char reg, unsigned char *val, gfp_t mem_flags) val 210 drivers/usb/misc/uss720.c if (!val) { val 216 drivers/usb/misc/uss720.c *val = priv->reg[(reg >= 9) ? 0 : regindex[reg]]; val 228 drivers/usb/misc/uss720.c static int set_1284_register(struct parport *pp, unsigned char reg, unsigned char val, gfp_t mem_flags) val 236 drivers/usb/misc/uss720.c rq = submit_async_request(priv, 4, 0x40, (((unsigned int)reg) << 8) | val, 0, mem_flags); val 239 drivers/usb/misc/uss720.c (unsigned int)reg, (unsigned int)val); val 364 drivers/usb/misc/uss720.c static unsigned char parport_uss720_frob_control(struct parport *pp, unsigned char mask, unsigned char val) val 370 drivers/usb/misc/uss720.c val &= 0x0f; val 371 drivers/usb/misc/uss720.c d = (priv->reg[1] & (~mask)) ^ val; val 321 drivers/usb/mtu3/mtu3_debugfs.c u32 val; val 327 drivers/usb/mtu3/mtu3_debugfs.c if (kstrtou32(buf, 0, &val)) val 336 drivers/usb/mtu3/mtu3_debugfs.c mtu3_writel(mtu->ippc_base, (u32)regs->offset, val); val 43 drivers/usb/mtu3/mtu3_host.c u32 reg, msk, val; val 49 drivers/usb/mtu3/mtu3_host.c val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; val 54 drivers/usb/mtu3/mtu3_host.c val = enable ? msk : 0; val 59 drivers/usb/mtu3/mtu3_host.c regmap_update_bits(ssusb->uwk, reg, msk, val); val 392 drivers/usb/musb/am35x.c u32 val; val 413 drivers/usb/musb/am35x.c val = musb_readl(fifo, 0); val 414 drivers/usb/musb/am35x.c memcpy(dst, &val, len); val 456 drivers/usb/musb/cppi_dma.c u32 val; val 464 drivers/usb/musb/cppi_dma.c val = tmp & ~((0x3) << (rx->index * 2)); val 472 drivers/usb/musb/cppi_dma.c val |= ((0x3) << (rx->index * 2)); val 476 drivers/usb/musb/cppi_dma.c val |= ((0x1) << (rx->index * 2)); val 480 drivers/usb/musb/cppi_dma.c if (val != tmp) { val 484 drivers/usb/musb/cppi_dma.c musb_writel(tibase, DAVINCI_AUTOREQ_REG, val); val 487 drivers/usb/musb/cppi_dma.c if (tmp == val) val 498 drivers/usb/musb/cppi_dma.c val = musb_readw(regs, MUSB_RXCSR); val 499 drivers/usb/musb/cppi_dma.c if (!(val & MUSB_RXCSR_H_REQPKT)) { val 500 drivers/usb/musb/cppi_dma.c val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS; val 501 drivers/usb/musb/cppi_dma.c musb_writew(regs, MUSB_RXCSR, val); val 503 drivers/usb/musb/cppi_dma.c val = musb_readw(regs, MUSB_RXCSR); val 79 drivers/usb/musb/davinci.c u32 tmp, old, val; val 91 drivers/usb/musb/davinci.c val = ~MUSB_INTR_SOF; val 92 drivers/usb/musb/davinci.c tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT); val 173 drivers/usb/musb/musb_core.c static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg) val 189 drivers/usb/musb/musb_core.c musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val); val 1762 drivers/usb/musb/musb_core.c unsigned long val; val 1764 drivers/usb/musb/musb_core.c if (sscanf(buf, "%lu", &val) < 1) { val 1771 drivers/usb/musb/musb_core.c musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; val 1774 drivers/usb/musb/musb_core.c musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); val 1785 drivers/usb/musb/musb_core.c unsigned long val; val 1791 drivers/usb/musb/musb_core.c val = musb->a_wait_bcon; val 1806 drivers/usb/musb/musb_core.c vbus ? "on" : "off", val); val 433 drivers/usb/musb/musb_dsps.c u32 rev, val; val 475 drivers/usb/musb/musb_dsps.c val = musb_readl(reg_base, wrp->phy_utmi); val 476 drivers/usb/musb/musb_dsps.c val &= ~(1 << wrp->otg_disable); val 477 drivers/usb/musb/musb_dsps.c musb_writel(musb->ctrl_base, wrp->phy_utmi, val); val 485 drivers/usb/musb/musb_dsps.c val = musb_readb(musb->mregs, MUSB_BABBLE_CTL); val 486 drivers/usb/musb/musb_dsps.c if (val & MUSB_BABBLE_RCV_DISABLE) { val 488 drivers/usb/musb/musb_dsps.c val |= MUSB_BABBLE_SW_SESSION_CTRL; val 489 drivers/usb/musb/musb_dsps.c musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val); val 635 drivers/usb/musb/musb_dsps.c u32 val = musb_readl(fifo, 0); val 636 drivers/usb/musb/musb_dsps.c memcpy(dst, &val, len); val 714 drivers/usb/musb/musb_dsps.c u32 val; val 716 drivers/usb/musb/musb_dsps.c ret = of_property_read_u32(dn, s, &val); val 719 drivers/usb/musb/musb_dsps.c return val; val 732 drivers/usb/musb/musb_dsps.c int ret, val; val 786 drivers/usb/musb/musb_dsps.c ret = of_property_read_u32(dn, "mentor,multipoint", &val); val 787 drivers/usb/musb/musb_dsps.c if (!ret && val) val 1500 drivers/usb/musb/musb_host.c u16 val; val 1507 drivers/usb/musb/musb_host.c val = musb_readw(epio, MUSB_RXCSR); val 1508 drivers/usb/musb/musb_host.c val |= MUSB_RXCSR_DMAENAB; val 1509 drivers/usb/musb/musb_host.c musb_writew(hw_ep->regs, MUSB_RXCSR, val); val 1569 drivers/usb/musb/musb_host.c u16 val; val 1607 drivers/usb/musb/musb_host.c val = musb_readw(epio, MUSB_RXCSR); val 1608 drivers/usb/musb/musb_host.c val |= MUSB_RXCSR_H_REQPKT; val 1609 drivers/usb/musb/musb_host.c musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val); val 1641 drivers/usb/musb/musb_host.c u16 rx_count, val; val 1694 drivers/usb/musb/musb_host.c val = musb_readw(epio, MUSB_RXCSR); val 1695 drivers/usb/musb/musb_host.c val &= ~MUSB_RXCSR_H_REQPKT; val 1698 drivers/usb/musb/musb_host.c val &= ~MUSB_RXCSR_H_AUTOREQ; val 1700 drivers/usb/musb/musb_host.c val |= MUSB_RXCSR_H_AUTOREQ; val 1701 drivers/usb/musb/musb_host.c val |= MUSB_RXCSR_DMAENAB; val 1705 drivers/usb/musb/musb_host.c val |= MUSB_RXCSR_AUTOCLEAR; val 1707 drivers/usb/musb/musb_host.c musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val); val 1721 drivers/usb/musb/musb_host.c val = musb_readw(epio, MUSB_RXCSR); val 1722 drivers/usb/musb/musb_host.c val &= ~(MUSB_RXCSR_DMAENAB val 1725 drivers/usb/musb/musb_host.c musb_writew(epio, MUSB_RXCSR, val); val 1764 drivers/usb/musb/musb_host.c u16 rx_csr, val; val 1779 drivers/usb/musb/musb_host.c val = rx_csr; val 1787 drivers/usb/musb/musb_host.c epnum, val, musb_readw(epio, MUSB_RXCOUNT)); val 1899 drivers/usb/musb/musb_host.c val &= ~(MUSB_RXCSR_DMAENAB val 1903 drivers/usb/musb/musb_host.c musb_writew(hw_ep->regs, MUSB_RXCSR, val); val 1928 drivers/usb/musb/musb_host.c val &= ~MUSB_RXCSR_H_REQPKT; val 1929 drivers/usb/musb/musb_host.c musb_writew(epio, MUSB_RXCSR, val); val 383 drivers/usb/musb/omap2430.c int ret = -ENOMEM, val; val 426 drivers/usb/musb/omap2430.c ret = of_property_read_u32(np, "multipoint", &val); val 427 drivers/usb/musb/omap2430.c if (!ret && val) val 148 drivers/usb/musb/tusb6010.c u8 val; val 152 drivers/usb/musb/tusb6010.c val = (tmp >> 8); val 154 drivers/usb/musb/tusb6010.c val = tmp & 0xff; val 156 drivers/usb/musb/tusb6010.c return val; val 180 drivers/usb/musb/tusb6010.c u32 val; val 185 drivers/usb/musb/tusb6010.c memcpy(&val, buf, 4); val 186 drivers/usb/musb/tusb6010.c musb_writel(fifo, 0, val); val 193 drivers/usb/musb/tusb6010.c memcpy(&val, buf, len); val 194 drivers/usb/musb/tusb6010.c musb_writel(fifo, 0, val); val 201 drivers/usb/musb/tusb6010.c u32 val; val 206 drivers/usb/musb/tusb6010.c val = musb_readl(fifo, 0); val 207 drivers/usb/musb/tusb6010.c memcpy(buf, &val, 4); val 214 drivers/usb/musb/tusb6010.c val = musb_readl(fifo, 0); val 215 drivers/usb/musb/tusb6010.c memcpy(buf, &val, len); val 249 drivers/usb/musb/tusb6010.c u32 val; val 254 drivers/usb/musb/tusb6010.c val = (u32)(*(u16 *)buf); val 256 drivers/usb/musb/tusb6010.c val |= (*(u16 *)buf) << 16; val 258 drivers/usb/musb/tusb6010.c musb_writel(fifo, 0, val); val 296 drivers/usb/musb/tusb6010.c u32 val; val 301 drivers/usb/musb/tusb6010.c val = musb_readl(fifo, 0); val 302 drivers/usb/musb/tusb6010.c *(u16 *)buf = (u16)(val & 0xffff); val 304 drivers/usb/musb/tusb6010.c *(u16 *)buf = (u16)(val >> 16); val 34 drivers/usb/phy/phy-am335x-control.c u32 val; val 52 drivers/usb/phy/phy-am335x-control.c val = readl(usb_ctrl->wkup); val 55 drivers/usb/phy/phy-am335x-control.c val |= reg; val 57 drivers/usb/phy/phy-am335x-control.c val &= ~reg; val 59 drivers/usb/phy/phy-am335x-control.c writel(val, usb_ctrl->wkup); val 67 drivers/usb/phy/phy-am335x-control.c u32 val; val 84 drivers/usb/phy/phy-am335x-control.c val = readl(usb_ctrl->phy_reg + reg); val 87 drivers/usb/phy/phy-am335x-control.c val &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN | val 89 drivers/usb/phy/phy-am335x-control.c val |= USBPHY_OTGSESSEND_EN; val 91 drivers/usb/phy/phy-am335x-control.c val &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN); val 92 drivers/usb/phy/phy-am335x-control.c val |= USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN; val 95 drivers/usb/phy/phy-am335x-control.c val |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN; val 98 drivers/usb/phy/phy-am335x-control.c writel(val, usb_ctrl->phy_reg + reg); val 101 drivers/usb/phy/phy-fsl-usb.c #define fsl_writel(val, addr) writel(val, addr) val 47 drivers/usb/phy/phy-keystone.c u32 val; val 49 drivers/usb/phy/phy-keystone.c val = keystone_usbphy_readl(k_phy->phy_ctrl, USB_PHY_CTL_CLOCK); val 51 drivers/usb/phy/phy-keystone.c val | PHY_REF_SSP_EN); val 58 drivers/usb/phy/phy-keystone.c u32 val; val 60 drivers/usb/phy/phy-keystone.c val = keystone_usbphy_readl(k_phy->phy_ctrl, USB_PHY_CTL_CLOCK); val 62 drivers/usb/phy/phy-keystone.c val &= ~PHY_REF_SSP_EN); val 575 drivers/usb/phy/phy-mxs-usb.c u32 val; val 578 drivers/usb/phy/phy-mxs-usb.c regmap_read(regmap, ANADIG_USB1_VBUS_DET_STAT, &val); val 579 drivers/usb/phy/phy-mxs-usb.c if (!(val & ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)) { val 597 drivers/usb/phy/phy-mxs-usb.c regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); val 598 drivers/usb/phy/phy-mxs-usb.c if (val & ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT) { val 628 drivers/usb/phy/phy-mxs-usb.c u32 val; val 642 drivers/usb/phy/phy-mxs-usb.c regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); val 643 drivers/usb/phy/phy-mxs-usb.c if (!(val & ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) { val 663 drivers/usb/phy/phy-mxs-usb.c int val; val 667 drivers/usb/phy/phy-mxs-usb.c regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); val 668 drivers/usb/phy/phy-mxs-usb.c if (val & ANADIG_USB1_CHRG_DET_STAT_DM_STATE) { val 720 drivers/usb/phy/phy-mxs-usb.c u32 val; val 754 drivers/usb/phy/phy-mxs-usb.c if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) && val 755 drivers/usb/phy/phy-mxs-usb.c val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { val 757 drivers/usb/phy/phy-mxs-usb.c val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF val 760 drivers/usb/phy/phy-mxs-usb.c mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DN(val); val 763 drivers/usb/phy/phy-mxs-usb.c if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) && val 764 drivers/usb/phy/phy-mxs-usb.c val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { val 766 drivers/usb/phy/phy-mxs-usb.c val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF val 769 drivers/usb/phy/phy-mxs-usb.c mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DP(val); val 772 drivers/usb/phy/phy-mxs-usb.c if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) && val 773 drivers/usb/phy/phy-mxs-usb.c val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) { val 777 drivers/usb/phy/phy-mxs-usb.c val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF val 781 drivers/usb/phy/phy-mxs-usb.c mxs_phy->tx_reg_set |= GM_USBPHY_TX_D_CAL(val); val 200 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 203 drivers/usb/phy/phy-tegra-usb.c val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); val 204 drivers/usb/phy/phy-tegra-usb.c val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); val 205 drivers/usb/phy/phy-tegra-usb.c val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); val 206 drivers/usb/phy/phy-tegra-usb.c writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); val 208 drivers/usb/phy/phy-tegra-usb.c val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; val 209 drivers/usb/phy/phy-tegra-usb.c val &= ~TEGRA_USB_PORTSC1_PTS(~0); val 210 drivers/usb/phy/phy-tegra-usb.c val |= TEGRA_USB_PORTSC1_PTS(pts_val); val 211 drivers/usb/phy/phy-tegra-usb.c writel(val, base + TEGRA_USB_PORTSC1); val 218 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 221 drivers/usb/phy/phy-tegra-usb.c val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); val 223 drivers/usb/phy/phy-tegra-usb.c val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; val 225 drivers/usb/phy/phy-tegra-usb.c val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; val 226 drivers/usb/phy/phy-tegra-usb.c writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); val 228 drivers/usb/phy/phy-tegra-usb.c val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; val 230 drivers/usb/phy/phy-tegra-usb.c val |= TEGRA_USB_PORTSC1_PHCD; val 232 drivers/usb/phy/phy-tegra-usb.c val &= ~TEGRA_USB_PORTSC1_PHCD; val 233 drivers/usb/phy/phy-tegra-usb.c writel(val, base + TEGRA_USB_PORTSC1); val 320 drivers/usb/phy/phy-tegra-usb.c unsigned long val, flags; val 329 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BIAS_CFG0); val 330 drivers/usb/phy/phy-tegra-usb.c val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); val 333 drivers/usb/phy/phy-tegra-usb.c val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | val 337 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); val 338 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); val 339 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); val 341 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BIAS_CFG0); val 351 drivers/usb/phy/phy-tegra-usb.c unsigned long val, flags; val 364 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BIAS_CFG0); val 365 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_OTGPD | UTMIP_BIASPD; val 366 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BIAS_CFG0); val 386 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 398 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 399 drivers/usb/phy/phy-tegra-usb.c val |= USB_SUSP_SET; val 400 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 404 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 405 drivers/usb/phy/phy-tegra-usb.c val &= ~USB_SUSP_SET; val 406 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 417 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 430 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 431 drivers/usb/phy/phy-tegra-usb.c val |= USB_SUSP_CLR; val 432 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 436 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 437 drivers/usb/phy/phy-tegra-usb.c val &= ~USB_SUSP_CLR; val 438 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 450 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 454 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 455 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_RESET; val 456 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 459 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB1_LEGACY_CTRL); val 460 drivers/usb/phy/phy-tegra-usb.c val |= USB1_NO_LEGACY_MODE; val 461 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB1_LEGACY_CTRL); val 464 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_TX_CFG0); val 465 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_FS_PREABMLE_J; val 466 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_TX_CFG0); val 468 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_HSRX_CFG0); val 469 drivers/usb/phy/phy-tegra-usb.c val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); val 470 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); val 471 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); val 472 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_HSRX_CFG0); val 474 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_HSRX_CFG1); val 475 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_HS_SYNC_START_DLY(~0); val 476 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); val 477 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_HSRX_CFG1); val 479 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_DEBOUNCE_CFG0); val 480 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); val 481 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); val 482 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_DEBOUNCE_CFG0); val 484 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG0); val 485 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; val 486 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG0); val 489 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG1); val 490 drivers/usb/phy/phy-tegra-usb.c val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | val 492 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | val 494 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG1); val 496 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_PLL_CFG1); val 497 drivers/usb/phy/phy-tegra-usb.c val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | val 499 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | val 501 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_PLL_CFG1); val 505 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 506 drivers/usb/phy/phy-tegra-usb.c val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); val 507 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 509 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BAT_CHRG_CFG0); val 510 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_PD_CHRG; val 511 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BAT_CHRG_CFG0); val 513 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BAT_CHRG_CFG0); val 514 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_PD_CHRG; val 515 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BAT_CHRG_CFG0); val 520 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_XCVR_CFG0); val 521 drivers/usb/phy/phy-tegra-usb.c val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | val 527 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_XCVR_SETUP(config->xcvr_setup); val 528 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); val 530 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); val 531 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); val 534 drivers/usb/phy/phy-tegra-usb.c val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); val 535 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); val 536 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); val 538 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_XCVR_CFG0); val 540 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_XCVR_CFG1); val 541 drivers/usb/phy/phy-tegra-usb.c val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | val 543 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); val 544 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_XCVR_CFG1); val 546 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BIAS_CFG1); val 547 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); val 548 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_BIAS_PDTRK_COUNT(0x5); val 549 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BIAS_CFG1); val 551 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_SPARE_CFG0); val 553 drivers/usb/phy/phy-tegra-usb.c val |= FUSE_SETUP_SEL; val 555 drivers/usb/phy/phy-tegra-usb.c val &= ~FUSE_SETUP_SEL; val 556 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_SPARE_CFG0); val 559 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 560 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_PHY_ENABLE; val 561 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 564 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 565 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_RESET; val 566 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 569 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB1_LEGACY_CTRL); val 570 drivers/usb/phy/phy-tegra-usb.c val &= ~USB1_VBUS_SENSE_CTL_MASK; val 571 drivers/usb/phy/phy-tegra-usb.c val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; val 572 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB1_LEGACY_CTRL); val 574 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 575 drivers/usb/phy/phy-tegra-usb.c val &= ~USB_SUSP_SET; val 576 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 582 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_USBMODE); val 583 drivers/usb/phy/phy-tegra-usb.c val &= ~USB_USBMODE_MASK; val 585 drivers/usb/phy/phy-tegra-usb.c val |= USB_USBMODE_HOST; val 587 drivers/usb/phy/phy-tegra-usb.c val |= USB_USBMODE_DEVICE; val 588 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_USBMODE); val 599 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 605 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 606 drivers/usb/phy/phy-tegra-usb.c val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); val 607 drivers/usb/phy/phy-tegra-usb.c val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); val 608 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 611 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 612 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_RESET; val 613 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 615 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BAT_CHRG_CFG0); val 616 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_PD_CHRG; val 617 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BAT_CHRG_CFG0); val 619 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_XCVR_CFG0); val 620 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | val 622 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_XCVR_CFG0); val 624 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_XCVR_CFG1); val 625 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | val 627 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_XCVR_CFG1); val 634 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 637 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_TX_CFG0); val 638 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_HS_DISCON_DISABLE; val 639 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_TX_CFG0); val 644 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 647 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_TX_CFG0); val 648 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_HS_DISCON_DISABLE; val 649 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_TX_CFG0); val 655 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 658 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG0); val 659 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); val 661 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; val 663 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; val 664 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG0); val 667 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG0); val 668 drivers/usb/phy/phy-tegra-usb.c val |= UTMIP_DPDM_OBSERVE; val 669 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG0); val 675 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 678 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG0); val 679 drivers/usb/phy/phy-tegra-usb.c val &= ~UTMIP_DPDM_OBSERVE; val 680 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG0); val 687 drivers/usb/phy/phy-tegra-usb.c unsigned long val; val 707 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 708 drivers/usb/phy/phy-tegra-usb.c val |= UHSIC_RESET; val 709 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 711 drivers/usb/phy/phy-tegra-usb.c val = readl(base + ULPI_TIMING_CTRL_0); val 712 drivers/usb/phy/phy-tegra-usb.c val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; val 713 drivers/usb/phy/phy-tegra-usb.c writel(val, base + ULPI_TIMING_CTRL_0); val 715 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 716 drivers/usb/phy/phy-tegra-usb.c val |= ULPI_PHY_ENABLE; val 717 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 719 drivers/usb/phy/phy-tegra-usb.c val = 0; val 720 drivers/usb/phy/phy-tegra-usb.c writel(val, base + ULPI_TIMING_CTRL_1); val 722 drivers/usb/phy/phy-tegra-usb.c val |= ULPI_DATA_TRIMMER_SEL(4); val 723 drivers/usb/phy/phy-tegra-usb.c val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); val 724 drivers/usb/phy/phy-tegra-usb.c val |= ULPI_DIR_TRIMMER_SEL(4); val 725 drivers/usb/phy/phy-tegra-usb.c writel(val, base + ULPI_TIMING_CTRL_1); val 728 drivers/usb/phy/phy-tegra-usb.c val |= ULPI_DATA_TRIMMER_LOAD; val 729 drivers/usb/phy/phy-tegra-usb.c val |= ULPI_STPDIRNXT_TRIMMER_LOAD; val 730 drivers/usb/phy/phy-tegra-usb.c val |= ULPI_DIR_TRIMMER_LOAD; val 731 drivers/usb/phy/phy-tegra-usb.c writel(val, base + ULPI_TIMING_CTRL_1); val 746 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 747 drivers/usb/phy/phy-tegra-usb.c val |= USB_SUSP_CLR; val 748 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 751 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); val 752 drivers/usb/phy/phy-tegra-usb.c val &= ~USB_SUSP_CLR; val 753 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); val 53 drivers/usb/phy/phy-ulpi-viewport.c static int ulpi_viewport_write(struct usb_phy *otg, u32 val, u32 reg) val 63 drivers/usb/phy/phy-ulpi-viewport.c writel(ULPI_VIEW_RUN | ULPI_VIEW_WRITE | ULPI_VIEW_DATA_WRITE(val) | val 145 drivers/usb/phy/phy-ulpi.c unsigned int val = 0x55; val 148 drivers/usb/phy/phy-ulpi.c ret = usb_phy_io_write(phy, val, ULPI_SCRATCH); val 156 drivers/usb/phy/phy-ulpi.c if (ret != val) { val 160 drivers/usb/phy/phy-ulpi.c val = val << 1; val 74 drivers/usb/renesas_usbhs/common.c u16 val = usbhs_read(priv, reg); val 76 drivers/usb/renesas_usbhs/common.c val &= ~mask; val 77 drivers/usb/renesas_usbhs/common.c val |= data & mask; val 79 drivers/usb/renesas_usbhs/common.c usbhs_write(priv, reg, val); val 103 drivers/usb/renesas_usbhs/common.c u16 val = DCFM | DRPD | HSE | USBE; val 111 drivers/usb/renesas_usbhs/common.c usbhs_bset(priv, SYSCFG, mask, enable ? val : 0); val 117 drivers/usb/renesas_usbhs/common.c u16 val = HSE | USBE; val 122 drivers/usb/renesas_usbhs/common.c val |= CNEN; val 133 drivers/usb/renesas_usbhs/common.c usbhs_bset(priv, SYSCFG, mask, enable ? val : 0); val 159 drivers/usb/renesas_usbhs/common.c u16 val; val 161 drivers/usb/renesas_usbhs/common.c val = usbhs_read(priv, USBREQ); val 162 drivers/usb/renesas_usbhs/common.c req->bRequest = (val >> 8) & 0xFF; val 163 drivers/usb/renesas_usbhs/common.c req->bRequestType = (val >> 0) & 0xFF; val 50 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipectrl_set(struct usbhs_pipe *pipe, u16 mask, u16 val) val 56 drivers/usb/renesas_usbhs/pipe.c usbhs_bset(priv, DCPCTR, mask, val); val 58 drivers/usb/renesas_usbhs/pipe.c usbhs_bset(priv, PIPEnCTR + offset, mask, val); val 77 drivers/usb/renesas_usbhs/pipe.c u16 mask, u16 val) val 82 drivers/usb/renesas_usbhs/pipe.c usbhs_bset(priv, dcp_reg, mask, val); val 84 drivers/usb/renesas_usbhs/pipe.c usbhs_bset(priv, pipe_reg, mask, val); val 101 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_cfg_set(struct usbhs_pipe *pipe, u16 mask, u16 val) val 103 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, DCPCFG, PIPECFG, mask, val); val 114 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_trn_set(struct usbhs_pipe *pipe, u16 mask, u16 val) val 147 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, 0, reg, mask, val); val 150 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_tre_set(struct usbhs_pipe *pipe, u16 mask, u16 val) val 184 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, 0, reg, mask, val); val 190 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_buf_set(struct usbhs_pipe *pipe, u16 mask, u16 val) val 195 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, 0, PIPEBUF, mask, val); val 201 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_maxp_set(struct usbhs_pipe *pipe, u16 mask, u16 val) val 203 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, DCPMAXP, PIPEMAXP, mask, val); val 271 drivers/usb/renesas_usbhs/pipe.c u16 val; val 273 drivers/usb/renesas_usbhs/pipe.c val = usbhsp_pipectrl_get(pipe); val 274 drivers/usb/renesas_usbhs/pipe.c if (val & BSTS) val 282 drivers/usb/renesas_usbhs/pipe.c u16 val; val 288 drivers/usb/renesas_usbhs/pipe.c val = usbhsp_pipectrl_get(pipe); val 289 drivers/usb/renesas_usbhs/pipe.c if (val & INBUFM) val 320 drivers/usb/renesas_usbhs/pipe.c u16 val; val 328 drivers/usb/renesas_usbhs/pipe.c val = usbhsp_pipectrl_get(pipe); val 329 drivers/usb/renesas_usbhs/pipe.c val &= PBUSY; val 330 drivers/usb/renesas_usbhs/pipe.c if (!val) val 571 drivers/usb/renesas_usbhs/pipe.c u16 val; val 581 drivers/usb/renesas_usbhs/pipe.c val = SQCLR; val 584 drivers/usb/renesas_usbhs/pipe.c val = SQSET; val 590 drivers/usb/renesas_usbhs/pipe.c usbhsp_pipectrl_set(pipe, mask, val); val 47 drivers/usb/renesas_usbhs/rcar3.c static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val) val 49 drivers/usb/renesas_usbhs/rcar3.c usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3); val 75 drivers/usb/renesas_usbhs/rcar3.c u32 val; val 85 drivers/usb/renesas_usbhs/rcar3.c val = usbhs_read32(priv, UGSTS); val 87 drivers/usb/renesas_usbhs/rcar3.c } while (!(val & UGSTS_LOCK) && timeout--); val 59 drivers/usb/roles/intel-xhci-usb-role-switch.c u32 glk, val; val 81 drivers/usb/roles/intel-xhci-usb-role-switch.c val = readl(data->base + DUAL_ROLE_CFG0); val 84 drivers/usb/roles/intel-xhci-usb-role-switch.c val |= SW_IDPIN; val 85 drivers/usb/roles/intel-xhci-usb-role-switch.c val &= ~SW_VBUS_VALID; val 89 drivers/usb/roles/intel-xhci-usb-role-switch.c val &= ~SW_IDPIN; val 90 drivers/usb/roles/intel-xhci-usb-role-switch.c val &= ~SW_VBUS_VALID; val 94 drivers/usb/roles/intel-xhci-usb-role-switch.c val |= SW_IDPIN; val 95 drivers/usb/roles/intel-xhci-usb-role-switch.c val |= SW_VBUS_VALID; val 99 drivers/usb/roles/intel-xhci-usb-role-switch.c val |= SW_IDPIN_EN; val 101 drivers/usb/roles/intel-xhci-usb-role-switch.c val &= ~DRD_CONFIG_MASK; val 102 drivers/usb/roles/intel-xhci-usb-role-switch.c val |= SW_SWITCH_EN | drd_config; val 104 drivers/usb/roles/intel-xhci-usb-role-switch.c writel(val, data->base + DUAL_ROLE_CFG0); val 113 drivers/usb/roles/intel-xhci-usb-role-switch.c val = readl(data->base + DUAL_ROLE_CFG1); val 114 drivers/usb/roles/intel-xhci-usb-role-switch.c if (!!(val & HOST_MODE) == (role == USB_ROLE_HOST)) { val 133 drivers/usb/roles/intel-xhci-usb-role-switch.c u32 val; val 136 drivers/usb/roles/intel-xhci-usb-role-switch.c val = readl(data->base + DUAL_ROLE_CFG0); val 139 drivers/usb/roles/intel-xhci-usb-role-switch.c if (!(val & SW_IDPIN)) val 141 drivers/usb/roles/intel-xhci-usb-role-switch.c else if (val & SW_VBUS_VALID) val 78 drivers/usb/serial/ark3116.c unsigned reg, __u8 val) val 84 drivers/usb/serial/ark3116.c 0xfe, 0x40, val, reg, val 571 drivers/usb/serial/cp210x.c static int cp210x_read_u32_reg(struct usb_serial_port *port, u8 req, u32 *val) val 582 drivers/usb/serial/cp210x.c *val = 0; val 586 drivers/usb/serial/cp210x.c *val = le32_to_cpu(le32_val); val 594 drivers/usb/serial/cp210x.c static int cp210x_read_u16_reg(struct usb_serial_port *port, u8 req, u16 *val) val 603 drivers/usb/serial/cp210x.c *val = le16_to_cpu(le16_val); val 611 drivers/usb/serial/cp210x.c static int cp210x_read_u8_reg(struct usb_serial_port *port, u8 req, u8 *val) val 613 drivers/usb/serial/cp210x.c return cp210x_read_reg_block(port, req, val, sizeof(*val)); val 620 drivers/usb/serial/cp210x.c static int cp210x_read_vendor_block(struct usb_serial *serial, u8 type, u16 val, val 631 drivers/usb/serial/cp210x.c CP210X_VENDOR_SPECIFIC, type, val, val 639 drivers/usb/serial/cp210x.c "failed to get vendor val 0x%04x size %d: %d\n", val, val 654 drivers/usb/serial/cp210x.c static int cp210x_write_u16_reg(struct usb_serial_port *port, u8 req, u16 val) val 661 drivers/usb/serial/cp210x.c req, REQTYPE_HOST_TO_INTERFACE, val, val 710 drivers/usb/serial/cp210x.c static int cp210x_write_u32_reg(struct usb_serial_port *port, u8 req, u32 val) val 714 drivers/usb/serial/cp210x.c le32_val = cpu_to_le32(val); val 725 drivers/usb/serial/cp210x.c u16 val, void *buf, int bufsize) val 735 drivers/usb/serial/cp210x.c CP210X_VENDOR_SPECIFIC, type, val, val 745 drivers/usb/serial/cp210x.c "failed to set vendor val 0x%04x size %d: %d\n", val, val 880 drivers/usb/serial/digi_acceleport.c unsigned int val; val 884 drivers/usb/serial/digi_acceleport.c val = priv->dp_modem_signals; val 886 drivers/usb/serial/digi_acceleport.c return val; val 895 drivers/usb/serial/digi_acceleport.c unsigned int val; val 899 drivers/usb/serial/digi_acceleport.c val = (priv->dp_modem_signals & ~clear) | set; val 901 drivers/usb/serial/digi_acceleport.c return digi_set_modem_signals(port, val, 1); val 1477 drivers/usb/serial/digi_acceleport.c int opcode, line, status, val; val 1490 drivers/usb/serial/digi_acceleport.c val = buf[i + 3]; val 1493 drivers/usb/serial/digi_acceleport.c opcode, line, status, val); val 1513 drivers/usb/serial/digi_acceleport.c if (val & DIGI_READ_INPUT_SIGNALS_CTS) { val 1522 drivers/usb/serial/digi_acceleport.c if (val & DIGI_READ_INPUT_SIGNALS_DSR) val 1526 drivers/usb/serial/digi_acceleport.c if (val & DIGI_READ_INPUT_SIGNALS_RI) val 1530 drivers/usb/serial/digi_acceleport.c if (val & DIGI_READ_INPUT_SIGNALS_DCD) val 87 drivers/usb/serial/f81232.c static int f81232_get_register(struct usb_serial_port *port, u16 reg, u8 *val) val 93 drivers/usb/serial/f81232.c tmp = kmalloc(sizeof(*val), GFP_KERNEL); val 104 drivers/usb/serial/f81232.c sizeof(*val), val 106 drivers/usb/serial/f81232.c if (status != sizeof(*val)) { val 115 drivers/usb/serial/f81232.c *val = *tmp; val 122 drivers/usb/serial/f81232.c static int f81232_set_register(struct usb_serial_port *port, u16 reg, u8 val) val 128 drivers/usb/serial/f81232.c tmp = kmalloc(sizeof(val), GFP_KERNEL); val 132 drivers/usb/serial/f81232.c *tmp = val; val 141 drivers/usb/serial/f81232.c sizeof(val), val 143 drivers/usb/serial/f81232.c if (status != sizeof(val)) { val 159 drivers/usb/serial/f81232.c u8 mask, u8 val) val 168 drivers/usb/serial/f81232.c tmp = (tmp & ~mask) | (val & mask); val 220 drivers/usb/serial/f81232.c u8 val; val 232 drivers/usb/serial/f81232.c val = UART_MCR_OUT2 | priv->modem_control; val 235 drivers/usb/serial/f81232.c val &= ~UART_MCR_DTR; val 238 drivers/usb/serial/f81232.c val &= ~UART_MCR_RTS; val 241 drivers/usb/serial/f81232.c val |= UART_MCR_DTR; val 244 drivers/usb/serial/f81232.c val |= UART_MCR_RTS; val 247 drivers/usb/serial/f81232.c val, priv->modem_control); val 249 drivers/usb/serial/f81232.c status = f81232_set_register(port, MODEM_CONTROL_REGISTER, val); val 256 drivers/usb/serial/f81232.c priv->modem_control = val; val 490 drivers/usb/serial/f81232.c u8 val; val 494 drivers/usb/serial/f81232.c val = UART_FCR_TRIGGER_8 | UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | val 497 drivers/usb/serial/f81232.c status = f81232_set_register(port, FIFO_CONTROL_REGISTER, val); val 1795 drivers/usb/serial/ftdi_sio.c u16 val; val 1801 drivers/usb/serial/ftdi_sio.c val = (mode << 8) | (priv->gpio_output << 4) | priv->gpio_value; val 1805 drivers/usb/serial/ftdi_sio.c FTDI_SIO_SET_BITMODE_REQUEST_TYPE, val, val 1810 drivers/usb/serial/ftdi_sio.c val, result); val 538 drivers/usb/serial/mos7720.c unsigned char val) val 544 drivers/usb/serial/mos7720.c val &= 0x0f; val 547 drivers/usb/serial/mos7720.c mos_parport->shadowDCR = (mos_parport->shadowDCR & (~mask)) ^ val; val 250 drivers/usb/serial/mos7840.c __u16 val) val 253 drivers/usb/serial/mos7840.c val = val & 0x00ff; val 254 drivers/usb/serial/mos7840.c dev_dbg(&port->dev, "mos7840_set_reg_sync offset is %x, value %x\n", reg, val); val 257 drivers/usb/serial/mos7840.c MCS_WR_RTYPE, val, reg, NULL, 0, val 268 drivers/usb/serial/mos7840.c __u16 *val) val 287 drivers/usb/serial/mos7840.c *val = buf[0]; val 288 drivers/usb/serial/mos7840.c dev_dbg(&port->dev, "%s offset is %x, return val %x\n", __func__, reg, *val); val 301 drivers/usb/serial/mos7840.c __u16 val) val 305 drivers/usb/serial/mos7840.c val = val & 0x00ff; val 309 drivers/usb/serial/mos7840.c val |= ((__u16)port->port_number + 2) << 8; val 311 drivers/usb/serial/mos7840.c val |= ((__u16)port->port_number + 1) << 8; val 312 drivers/usb/serial/mos7840.c dev_dbg(&port->dev, "%s application number is %x\n", __func__, val); val 314 drivers/usb/serial/mos7840.c MCS_WR_RTYPE, val, reg, NULL, 0, val 325 drivers/usb/serial/mos7840.c __u16 *val) val 350 drivers/usb/serial/mos7840.c *val = buf[0]; val 485 drivers/usb/serial/mos7840.c __u16 *val) val 550 drivers/usb/serial/mos7840.c __u16 val) val 555 drivers/usb/serial/mos7840.c val, reg, NULL, 0, MOS_WDR_TIMEOUT); val 100 drivers/usb/serial/opticon.c u8 val) val 110 drivers/usb/serial/opticon.c buffer[0] = val; val 232 drivers/usb/serial/pl2303.c static int pl2303_update_reg(struct usb_serial *serial, u8 reg, u8 mask, u8 val) val 246 drivers/usb/serial/pl2303.c *buf |= val & mask; val 804 drivers/usb/serial/quatech2.c u16 val; val 808 drivers/usb/serial/quatech2.c val = (break_state == -1) ? 1 : 0; val 811 drivers/usb/serial/quatech2.c val, port_priv->device_port); val 312 drivers/usb/serial/sierra.c int val = 0; val 319 drivers/usb/serial/sierra.c val |= 0x01; val 321 drivers/usb/serial/sierra.c val |= 0x02; val 354 drivers/usb/serial/sierra.c 0x22, 0x21, val, interface, NULL, 0, USB_CTRL_SET_TIMEOUT); val 44 drivers/usb/serial/usb_wwan.c int val = 0; val 51 drivers/usb/serial/usb_wwan.c val |= 0x01; val 53 drivers/usb/serial/usb_wwan.c val |= 0x02; val 62 drivers/usb/serial/usb_wwan.c 0x22, 0x21, val, ifnum, NULL, 0, val 699 drivers/usb/storage/realtek_cr.c u8 val; val 704 drivers/usb/storage/realtek_cr.c retval = rts51x_read_mem(us, 0xFD6F, &val, 1); val 705 drivers/usb/storage/realtek_cr.c if (retval == STATUS_SUCCESS && (val & 0x1F) == 0) { val 706 drivers/usb/storage/realtek_cr.c val = 0x1F; val 707 drivers/usb/storage/realtek_cr.c retval = rts51x_write_mem(us, 0xFD70, &val, 1); val 191 drivers/usb/typec/mux.c u16 *val; val 222 drivers/usb/typec/mux.c val = kcalloc(nval, sizeof(*val), GFP_KERNEL); val 223 drivers/usb/typec/mux.c if (!val) val 226 drivers/usb/typec/mux.c nval = fwnode_property_read_u16_array(con->fwnode, "svid", val, nval); val 228 drivers/usb/typec/mux.c kfree(val); val 233 drivers/usb/typec/mux.c match = val[i] == desc->svid; val 235 drivers/usb/typec/mux.c kfree(val); val 239 drivers/usb/typec/mux.c kfree(val); val 46 drivers/usb/typec/tcpm/tcpci.c static int tcpci_read16(struct tcpci *tcpci, unsigned int reg, u16 *val) val 48 drivers/usb/typec/tcpm/tcpci.c return regmap_raw_read(tcpci->regmap, reg, val, sizeof(u16)); val 51 drivers/usb/typec/tcpm/tcpci.c static int tcpci_write16(struct tcpci *tcpci, unsigned int reg, u16 val) val 53 drivers/usb/typec/tcpm/tcpci.c return regmap_raw_write(tcpci->regmap, reg, &val, sizeof(u16)); val 557 drivers/usb/typec/tcpm/tcpci.c u16 val = 0; val 570 drivers/usb/typec/tcpm/tcpci.c err = regmap_raw_write(chip->data.regmap, TCPC_ALERT_MASK, &val, val 44 drivers/usb/typec/tcpm/tcpci_rt1711h.c static int rt1711h_read16(struct rt1711h_chip *chip, unsigned int reg, u16 *val) val 46 drivers/usb/typec/tcpm/tcpci_rt1711h.c return regmap_raw_read(chip->data.regmap, reg, val, sizeof(u16)); val 49 drivers/usb/typec/tcpm/tcpci_rt1711h.c static int rt1711h_write16(struct rt1711h_chip *chip, unsigned int reg, u16 val) val 51 drivers/usb/typec/tcpm/tcpci_rt1711h.c return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u16)); val 54 drivers/usb/typec/tcpm/tcpci_rt1711h.c static int rt1711h_read8(struct rt1711h_chip *chip, unsigned int reg, u8 *val) val 56 drivers/usb/typec/tcpm/tcpci_rt1711h.c return regmap_raw_read(chip->data.regmap, reg, val, sizeof(u8)); val 59 drivers/usb/typec/tcpm/tcpci_rt1711h.c static int rt1711h_write8(struct rt1711h_chip *chip, unsigned int reg, u8 val) val 61 drivers/usb/typec/tcpm/tcpci_rt1711h.c return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u8)); val 4520 drivers/usb/typec/tcpm/tcpm.c union power_supply_propval *val) val 4524 drivers/usb/typec/tcpm/tcpm.c val->intval = TCPM_PSY_PROG_ONLINE; val 4526 drivers/usb/typec/tcpm/tcpm.c val->intval = TCPM_PSY_FIXED_ONLINE; val 4528 drivers/usb/typec/tcpm/tcpm.c val->intval = TCPM_PSY_OFFLINE; val 4535 drivers/usb/typec/tcpm/tcpm.c union power_supply_propval *val) val 4538 drivers/usb/typec/tcpm/tcpm.c val->intval = port->pps_data.min_volt * 1000; val 4540 drivers/usb/typec/tcpm/tcpm.c val->intval = port->supply_voltage * 1000; val 4546 drivers/usb/typec/tcpm/tcpm.c union power_supply_propval *val) val 4549 drivers/usb/typec/tcpm/tcpm.c val->intval = port->pps_data.max_volt * 1000; val 4551 drivers/usb/typec/tcpm/tcpm.c val->intval = port->supply_voltage * 1000; val 4557 drivers/usb/typec/tcpm/tcpm.c union power_supply_propval *val) val 4559 drivers/usb/typec/tcpm/tcpm.c val->intval = port->supply_voltage * 1000; val 4565 drivers/usb/typec/tcpm/tcpm.c union power_supply_propval *val) val 4568 drivers/usb/typec/tcpm/tcpm.c val->intval = port->pps_data.max_curr * 1000; val 4570 drivers/usb/typec/tcpm/tcpm.c val->intval = port->current_limit * 1000; val 4576 drivers/usb/typec/tcpm/tcpm.c union power_supply_propval *val) val 4578 drivers/usb/typec/tcpm/tcpm.c val->intval = port->current_limit * 1000; val 4585 drivers/usb/typec/tcpm/tcpm.c union power_supply_propval *val) val 4592 drivers/usb/typec/tcpm/tcpm.c val->intval = port->usb_type; val 4595 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_psy_get_online(port, val); val 4598 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_psy_get_voltage_min(port, val); val 4601 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_psy_get_voltage_max(port, val); val 4604 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_psy_get_voltage_now(port, val); val 4607 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_psy_get_current_max(port, val); val 4610 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_psy_get_current_now(port, val); val 4621 drivers/usb/typec/tcpm/tcpm.c const union power_supply_propval *val) val 4625 drivers/usb/typec/tcpm/tcpm.c switch (val->intval) { val 4642 drivers/usb/typec/tcpm/tcpm.c const union power_supply_propval *val) val 4649 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_psy_set_online(port, val); val 4652 drivers/usb/typec/tcpm/tcpm.c if (val->intval < port->pps_data.min_volt * 1000 || val 4653 drivers/usb/typec/tcpm/tcpm.c val->intval > port->pps_data.max_volt * 1000) val 4656 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_pps_set_out_volt(port, val->intval / 1000); val 4659 drivers/usb/typec/tcpm/tcpm.c if (val->intval > port->pps_data.max_curr * 1000) val 4662 drivers/usb/typec/tcpm/tcpm.c ret = tcpm_pps_set_op_curr(port, val->intval / 1000); val 334 drivers/usb/typec/tcpm/wcove.c unsigned int val; val 342 drivers/usb/typec/tcpm/wcove.c val = role; val 343 drivers/usb/typec/tcpm/wcove.c val |= data << USBC_PDCFG3_DATAROLE_SHIFT; val 344 drivers/usb/typec/tcpm/wcove.c val |= PD_REV20 << USBC_PDCFG3_SOP_SHIFT; val 346 drivers/usb/typec/tcpm/wcove.c return regmap_write(wcove->regmap, USBC_PDCFG3, val); val 676 drivers/usb/typec/tcpm/wcove.c unsigned int val; val 679 drivers/usb/typec/tcpm/wcove.c regmap_read(wcove->regmap, USBC_IRQMASK1, &val); val 680 drivers/usb/typec/tcpm/wcove.c regmap_write(wcove->regmap, USBC_IRQMASK1, val | USBC_IRQMASK1_ALL); val 681 drivers/usb/typec/tcpm/wcove.c regmap_read(wcove->regmap, USBC_IRQMASK2, &val); val 682 drivers/usb/typec/tcpm/wcove.c regmap_write(wcove->regmap, USBC_IRQMASK2, val | USBC_IRQMASK2_ALL); val 107 drivers/usb/typec/tps6598x.c tps6598x_block_read(struct tps6598x *tps, u8 reg, void *val, size_t len) val 116 drivers/usb/typec/tps6598x.c return regmap_raw_read(tps->regmap, reg, val, len); val 125 drivers/usb/typec/tps6598x.c memcpy(val, &data[1], len); val 130 drivers/usb/typec/tps6598x.c const void *val, size_t len) val 135 drivers/usb/typec/tps6598x.c return regmap_raw_write(tps->regmap, reg, val, len); val 138 drivers/usb/typec/tps6598x.c memcpy(&data[1], val, len); val 143 drivers/usb/typec/tps6598x.c static inline int tps6598x_read16(struct tps6598x *tps, u8 reg, u16 *val) val 145 drivers/usb/typec/tps6598x.c return tps6598x_block_read(tps, reg, val, sizeof(u16)); val 148 drivers/usb/typec/tps6598x.c static inline int tps6598x_read32(struct tps6598x *tps, u8 reg, u32 *val) val 150 drivers/usb/typec/tps6598x.c return tps6598x_block_read(tps, reg, val, sizeof(u32)); val 153 drivers/usb/typec/tps6598x.c static inline int tps6598x_read64(struct tps6598x *tps, u8 reg, u64 *val) val 155 drivers/usb/typec/tps6598x.c return tps6598x_block_read(tps, reg, val, sizeof(u64)); val 158 drivers/usb/typec/tps6598x.c static inline int tps6598x_write16(struct tps6598x *tps, u8 reg, u16 val) val 160 drivers/usb/typec/tps6598x.c return tps6598x_block_write(tps, reg, &val, sizeof(u16)); val 163 drivers/usb/typec/tps6598x.c static inline int tps6598x_write32(struct tps6598x *tps, u8 reg, u32 val) val 165 drivers/usb/typec/tps6598x.c return tps6598x_block_write(tps, reg, &val, sizeof(u32)); val 168 drivers/usb/typec/tps6598x.c static inline int tps6598x_write64(struct tps6598x *tps, u8 reg, u64 val) val 170 drivers/usb/typec/tps6598x.c return tps6598x_block_write(tps, reg, &val, sizeof(u64)); val 174 drivers/usb/typec/tps6598x.c tps6598x_write_4cc(struct tps6598x *tps, u8 reg, const char *val) val 176 drivers/usb/typec/tps6598x.c return tps6598x_block_write(tps, reg, val, 4); val 252 drivers/usb/typec/tps6598x.c u32 val; val 255 drivers/usb/typec/tps6598x.c ret = tps6598x_read32(tps, TPS_REG_CMD1, &val); val 258 drivers/usb/typec/tps6598x.c if (val && !INVALID_CMD(val)) val 276 drivers/usb/typec/tps6598x.c ret = tps6598x_read32(tps, TPS_REG_CMD1, &val); val 279 drivers/usb/typec/tps6598x.c if (INVALID_CMD(val)) val 284 drivers/usb/typec/tps6598x.c } while (val); val 291 drivers/usb/typec/tps6598x.c val = out_data[0]; val 293 drivers/usb/typec/tps6598x.c ret = tps6598x_block_read(tps, TPS_REG_DATA1, &val, sizeof(u8)); val 298 drivers/usb/typec/tps6598x.c switch (val) { val 1114 drivers/usb/usbip/vhci_hcd.c long val; val 1121 drivers/usb/usbip/vhci_hcd.c ret = kstrtol(c+1, 10, &val); val 1125 drivers/usb/usbip/vhci_hcd.c return val; val 133 drivers/usb/usbip/vhci_sysfs.c long val; val 140 drivers/usb/usbip/vhci_sysfs.c ret = kstrtol(c+1, 10, &val); val 144 drivers/usb/usbip/vhci_sysfs.c return val; val 228 drivers/vfio/mdev/mdev_sysfs.c unsigned long val; val 230 drivers/vfio/mdev/mdev_sysfs.c if (kstrtoul(buf, 0, &val) < 0) val 233 drivers/vfio/mdev/mdev_sysfs.c if (val && device_remove_file_self(dev, attr)) { val 112 drivers/vfio/pci/vfio_pci_config.c struct perm_bits *perm, int offset, __le32 *val); val 114 drivers/vfio/pci/vfio_pci_config.c struct perm_bits *perm, int offset, __le32 val); val 123 drivers/vfio/pci/vfio_pci_config.c __le32 *val, int count) val 148 drivers/vfio/pci/vfio_pci_config.c *val = cpu_to_le32(tmp_val); val 154 drivers/vfio/pci/vfio_pci_config.c __le32 val, int count) val 157 drivers/vfio/pci/vfio_pci_config.c u32 tmp_val = le32_to_cpu(val); val 176 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 *val) val 180 drivers/vfio/pci/vfio_pci_config.c memcpy(val, vdev->vconfig + pos, count); val 194 drivers/vfio/pci/vfio_pci_config.c *val = (phys_val & ~virt) | (*val & virt); val 202 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 220 drivers/vfio/pci/vfio_pci_config.c virt_val |= (val & (write & virt)); val 236 drivers/vfio/pci/vfio_pci_config.c phys_val |= (val & (write & ~virt)); val 249 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 *val) val 253 drivers/vfio/pci/vfio_pci_config.c ret = vfio_user_config_read(vdev->pdev, pos, val, count); val 259 drivers/vfio/pci/vfio_pci_config.c memcpy(val, vdev->vconfig + pos, count); val 262 drivers/vfio/pci/vfio_pci_config.c memcpy(val, vdev->vconfig + pos, val 265 drivers/vfio/pci/vfio_pci_config.c memcpy(val, vdev->vconfig + pos, 1); val 274 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 278 drivers/vfio/pci/vfio_pci_config.c ret = vfio_user_config_write(vdev->pdev, pos, val, count); val 287 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 *val) val 291 drivers/vfio/pci/vfio_pci_config.c ret = vfio_user_config_read(vdev->pdev, pos, val, count); val 301 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 303 drivers/vfio/pci/vfio_pci_config.c memcpy(vdev->vconfig + pos, &val, count); val 309 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 *val) val 311 drivers/vfio/pci/vfio_pci_config.c memcpy(val, vdev->vconfig + pos, count); val 429 drivers/vfio/pci/vfio_pci_config.c u32 val; val 434 drivers/vfio/pci/vfio_pci_config.c val = PCI_BASE_ADDRESS_SPACE_MEMORY; val 437 drivers/vfio/pci/vfio_pci_config.c val |= PCI_BASE_ADDRESS_MEM_PREFETCH; val 440 drivers/vfio/pci/vfio_pci_config.c val |= PCI_BASE_ADDRESS_MEM_TYPE_64; val 442 drivers/vfio/pci/vfio_pci_config.c return cpu_to_le32(val); val 500 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 *val) val 505 drivers/vfio/pci/vfio_pci_config.c count = vfio_default_config_read(vdev, pos, count, perm, offset, val); val 510 drivers/vfio/pci/vfio_pci_config.c u32 tmp_val = le32_to_cpu(*val); val 513 drivers/vfio/pci/vfio_pci_config.c *val = cpu_to_le32(tmp_val); val 538 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 555 drivers/vfio/pci/vfio_pci_config.c new_cmd = le32_to_cpu(val); val 579 drivers/vfio/pci/vfio_pci_config.c count = vfio_default_config_write(vdev, pos, count, perm, offset, val); val 666 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 668 drivers/vfio/pci/vfio_pci_config.c count = vfio_default_config_write(vdev, pos, count, perm, offset, val); val 675 drivers/vfio/pci/vfio_pci_config.c switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { val 721 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 734 drivers/vfio/pci/vfio_pci_config.c count = vfio_default_config_write(vdev, pos, count, perm, offset, val); val 803 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 809 drivers/vfio/pci/vfio_pci_config.c count = vfio_default_config_write(vdev, pos, count, perm, offset, val); val 884 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 888 drivers/vfio/pci/vfio_pci_config.c count = vfio_default_config_write(vdev, pos, count, perm, offset, val); val 1057 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 *val) val 1072 drivers/vfio/pci/vfio_pci_config.c return vfio_default_config_read(vdev, pos, count, perm, offset, val); val 1077 drivers/vfio/pci/vfio_pci_config.c int offset, __le32 val) val 1079 drivers/vfio/pci/vfio_pci_config.c count = vfio_default_config_write(vdev, pos, count, perm, offset, val); val 1552 drivers/vfio/pci/vfio_pci_config.c u32 val = epos = PCI_EXT_CAP_NEXT(header); val 1554 drivers/vfio/pci/vfio_pci_config.c *prev |= cpu_to_le32(val << 20); val 1754 drivers/vfio/pci/vfio_pci_config.c __le32 val = 0; val 1813 drivers/vfio/pci/vfio_pci_config.c if (copy_from_user(&val, buf, count)) val 1816 drivers/vfio/pci/vfio_pci_config.c ret = perm->writefn(vdev, *ppos, count, perm, offset, val); val 1820 drivers/vfio/pci/vfio_pci_config.c perm, offset, &val); val 1825 drivers/vfio/pci/vfio_pci_config.c if (copy_to_user(buf, &val, count)) val 126 drivers/vfio/pci/vfio_pci_igd.c u8 val; val 128 drivers/vfio/pci/vfio_pci_igd.c ret = pci_user_read_config_byte(pdev, pos, &val); val 132 drivers/vfio/pci/vfio_pci_igd.c if (copy_to_user(buf + count - size, &val, 1)) val 140 drivers/vfio/pci/vfio_pci_igd.c u16 val; val 142 drivers/vfio/pci/vfio_pci_igd.c ret = pci_user_read_config_word(pdev, pos, &val); val 146 drivers/vfio/pci/vfio_pci_igd.c val = cpu_to_le16(val); val 147 drivers/vfio/pci/vfio_pci_igd.c if (copy_to_user(buf + count - size, &val, 2)) val 155 drivers/vfio/pci/vfio_pci_igd.c u32 val; val 157 drivers/vfio/pci/vfio_pci_igd.c ret = pci_user_read_config_dword(pdev, pos, &val); val 161 drivers/vfio/pci/vfio_pci_igd.c val = cpu_to_le32(val); val 162 drivers/vfio/pci/vfio_pci_igd.c if (copy_to_user(buf + count - size, &val, 4)) val 170 drivers/vfio/pci/vfio_pci_igd.c u16 val; val 172 drivers/vfio/pci/vfio_pci_igd.c ret = pci_user_read_config_word(pdev, pos, &val); val 176 drivers/vfio/pci/vfio_pci_igd.c val = cpu_to_le16(val); val 177 drivers/vfio/pci/vfio_pci_igd.c if (copy_to_user(buf + count - size, &val, 2)) val 185 drivers/vfio/pci/vfio_pci_igd.c u8 val; val 187 drivers/vfio/pci/vfio_pci_igd.c ret = pci_user_read_config_byte(pdev, pos, &val); val 191 drivers/vfio/pci/vfio_pci_igd.c if (copy_to_user(buf + count - size, &val, 1)) val 63 drivers/vfio/pci/vfio_pci_rdwr.c u32 val; val 66 drivers/vfio/pci/vfio_pci_rdwr.c if (copy_from_user(&val, buf, 4)) val 69 drivers/vfio/pci/vfio_pci_rdwr.c vfio_iowrite32(val, io + off); val 71 drivers/vfio/pci/vfio_pci_rdwr.c val = vfio_ioread32(io + off); val 73 drivers/vfio/pci/vfio_pci_rdwr.c if (copy_to_user(buf, &val, 4)) val 79 drivers/vfio/pci/vfio_pci_rdwr.c u16 val; val 82 drivers/vfio/pci/vfio_pci_rdwr.c if (copy_from_user(&val, buf, 2)) val 85 drivers/vfio/pci/vfio_pci_rdwr.c vfio_iowrite16(val, io + off); val 87 drivers/vfio/pci/vfio_pci_rdwr.c val = vfio_ioread16(io + off); val 89 drivers/vfio/pci/vfio_pci_rdwr.c if (copy_to_user(buf, &val, 2)) val 95 drivers/vfio/pci/vfio_pci_rdwr.c u8 val; val 98 drivers/vfio/pci/vfio_pci_rdwr.c if (copy_from_user(&val, buf, 1)) val 101 drivers/vfio/pci/vfio_pci_rdwr.c vfio_iowrite8(val, io + off); val 103 drivers/vfio/pci/vfio_pci_rdwr.c val = vfio_ioread8(io + off); val 105 drivers/vfio/pci/vfio_pci_rdwr.c if (copy_to_user(buf, &val, 1)) val 114 drivers/vfio/pci/vfio_pci_rdwr.c u8 val = 0xFF; val 118 drivers/vfio/pci/vfio_pci_rdwr.c if (copy_to_user(buf + i, &val, 1)) val 422 drivers/vfio/platform/vfio_platform_common.c u32 val; val 424 drivers/vfio/platform/vfio_platform_common.c val = ioread32(reg->ioaddr + off); val 425 drivers/vfio/platform/vfio_platform_common.c if (copy_to_user(buf, &val, 4)) val 430 drivers/vfio/platform/vfio_platform_common.c u16 val; val 432 drivers/vfio/platform/vfio_platform_common.c val = ioread16(reg->ioaddr + off); val 433 drivers/vfio/platform/vfio_platform_common.c if (copy_to_user(buf, &val, 2)) val 438 drivers/vfio/platform/vfio_platform_common.c u8 val; val 440 drivers/vfio/platform/vfio_platform_common.c val = ioread8(reg->ioaddr + off); val 441 drivers/vfio/platform/vfio_platform_common.c if (copy_to_user(buf, &val, 1)) val 499 drivers/vfio/platform/vfio_platform_common.c u32 val; val 501 drivers/vfio/platform/vfio_platform_common.c if (copy_from_user(&val, buf, 4)) val 503 drivers/vfio/platform/vfio_platform_common.c iowrite32(val, reg->ioaddr + off); val 507 drivers/vfio/platform/vfio_platform_common.c u16 val; val 509 drivers/vfio/platform/vfio_platform_common.c if (copy_from_user(&val, buf, 2)) val 511 drivers/vfio/platform/vfio_platform_common.c iowrite16(val, reg->ioaddr + off); val 515 drivers/vfio/platform/vfio_platform_common.c u8 val; val 517 drivers/vfio/platform/vfio_platform_common.c if (copy_from_user(&val, buf, 1)) val 519 drivers/vfio/platform/vfio_platform_common.c iowrite8(val, reg->ioaddr + off); val 1878 drivers/vhost/scsi.c unsigned long val; val 1879 drivers/vhost/scsi.c int ret = kstrtoul(page, 0, &val); val 1885 drivers/vhost/scsi.c if (val != 0 && val != 1 && val != 3) { val 1886 drivers/vhost/scsi.c pr_err("Invalid vhost_scsi fabric_prot_type: %lu\n", val); val 1889 drivers/vhost/scsi.c tpg->tv_fabric_prot_type = val; val 269 drivers/vhost/vhost.h static inline u16 vhost16_to_cpu(struct vhost_virtqueue *vq, __virtio16 val) val 271 drivers/vhost/vhost.h return __virtio16_to_cpu(vhost_is_little_endian(vq), val); val 274 drivers/vhost/vhost.h static inline __virtio16 cpu_to_vhost16(struct vhost_virtqueue *vq, u16 val) val 276 drivers/vhost/vhost.h return __cpu_to_virtio16(vhost_is_little_endian(vq), val); val 279 drivers/vhost/vhost.h static inline u32 vhost32_to_cpu(struct vhost_virtqueue *vq, __virtio32 val) val 281 drivers/vhost/vhost.h return __virtio32_to_cpu(vhost_is_little_endian(vq), val); val 284 drivers/vhost/vhost.h static inline __virtio32 cpu_to_vhost32(struct vhost_virtqueue *vq, u32 val) val 286 drivers/vhost/vhost.h return __cpu_to_virtio32(vhost_is_little_endian(vq), val); val 289 drivers/vhost/vhost.h static inline u64 vhost64_to_cpu(struct vhost_virtqueue *vq, __virtio64 val) val 291 drivers/vhost/vhost.h return __virtio64_to_cpu(vhost_is_little_endian(vq), val); val 294 drivers/vhost/vhost.h static inline __virtio64 cpu_to_vhost64(struct vhost_virtqueue *vq, u64 val) val 296 drivers/vhost/vhost.h return __cpu_to_virtio64(vhost_is_little_endian(vq), val); val 35 drivers/vhost/vringh.c u16 *val, const __virtio16 *p), val 406 drivers/vhost/vringh.c __virtio16 *p, u16 val), val 453 drivers/vhost/vringh.c u16 *val, val 500 drivers/vhost/vringh.c u16 *val, const __virtio16 *p), val 502 drivers/vhost/vringh.c __virtio16 *p, u16 val)) val 540 drivers/vhost/vringh.c __virtio16 *p, u16 val)) val 553 drivers/vhost/vringh.c static inline int getu16_user(const struct vringh *vrh, u16 *val, const __virtio16 *p) val 557 drivers/vhost/vringh.c *val = vringh16_to_cpu(vrh, v); val 561 drivers/vhost/vringh.c static inline int putu16_user(const struct vringh *vrh, __virtio16 *p, u16 val) val 563 drivers/vhost/vringh.c __virtio16 v = cpu_to_vringh16(vrh, val); val 823 drivers/vhost/vringh.c u16 *val, const __virtio16 *p) val 825 drivers/vhost/vringh.c *val = vringh16_to_cpu(vrh, READ_ONCE(*p)); val 829 drivers/vhost/vringh.c static inline int putu16_kern(const struct vringh *vrh, __virtio16 *p, u16 val) val 831 drivers/vhost/vringh.c WRITE_ONCE(*p, cpu_to_vringh16(vrh, val)); val 204 drivers/vhost/vsock.c int val; val 206 drivers/vhost/vsock.c val = atomic_dec_return(&vsock->queued_replies); val 211 drivers/vhost/vsock.c if (val + 1 == tx_vq->num) val 379 drivers/vhost/vsock.c int val; val 382 drivers/vhost/vsock.c val = atomic_read(&vsock->queued_replies); val 384 drivers/vhost/vsock.c return val < vq->num; val 32 drivers/video/backlight/aat2870_bl.c int val; val 34 drivers/video/backlight/aat2870_bl.c val = brightness * (aat2870_bl->max_current - 1); val 35 drivers/video/backlight/aat2870_bl.c val /= bd->props.max_brightness; val 37 drivers/video/backlight/aat2870_bl.c return val; val 163 drivers/video/backlight/adp5520_bl.c unsigned long val; val 166 drivers/video/backlight/adp5520_bl.c ret = kstrtoul(buf, 10, &val); val 171 drivers/video/backlight/adp5520_bl.c adp5520_write(data->master, reg, val); val 119 drivers/video/backlight/adp8860_bl.c static int adp8860_read(struct i2c_client *client, int reg, uint8_t *val) val 129 drivers/video/backlight/adp8860_bl.c *val = (uint8_t)ret; val 133 drivers/video/backlight/adp8860_bl.c static int adp8860_write(struct i2c_client *client, u8 reg, u8 val) val 135 drivers/video/backlight/adp8860_bl.c return i2c_smbus_write_byte_data(client, reg, val); val 449 drivers/video/backlight/adp8860_bl.c unsigned long val; val 452 drivers/video/backlight/adp8860_bl.c ret = kstrtoul(buf, 10, &val); val 457 drivers/video/backlight/adp8860_bl.c adp8860_write(data->client, reg, val); val 608 drivers/video/backlight/adp8860_bl.c unsigned long val; val 612 drivers/video/backlight/adp8860_bl.c ret = kstrtoul(buf, 10, &val); val 616 drivers/video/backlight/adp8860_bl.c if (val == 0) { val 619 drivers/video/backlight/adp8860_bl.c } else if ((val > 0) && (val <= 3)) { val 628 drivers/video/backlight/adp8860_bl.c reg_val |= (val - 1) << CFGR_BLV_SHIFT; val 128 drivers/video/backlight/adp8870_bl.c static int adp8870_read(struct i2c_client *client, int reg, uint8_t *val) val 138 drivers/video/backlight/adp8870_bl.c *val = ret; val 143 drivers/video/backlight/adp8870_bl.c static int adp8870_write(struct i2c_client *client, u8 reg, u8 val) val 145 drivers/video/backlight/adp8870_bl.c int ret = i2c_smbus_write_byte_data(client, reg, val); val 570 drivers/video/backlight/adp8870_bl.c unsigned long val; val 573 drivers/video/backlight/adp8870_bl.c ret = kstrtoul(buf, 10, &val); val 578 drivers/video/backlight/adp8870_bl.c adp8870_write(data->client, reg, val); val 792 drivers/video/backlight/adp8870_bl.c unsigned long val; val 796 drivers/video/backlight/adp8870_bl.c ret = kstrtoul(buf, 10, &val); val 800 drivers/video/backlight/adp8870_bl.c if (val == 0) { val 803 drivers/video/backlight/adp8870_bl.c } else if ((val > 0) && (val < 6)) { val 812 drivers/video/backlight/adp8870_bl.c reg_val |= (val - 1) << CFGR_BLV_SHIFT; val 115 drivers/video/backlight/arcxcnn_bl.c u8 val; val 118 drivers/video/backlight/arcxcnn_bl.c val = (brightness & 0xF) << ARCXCNN_WLED_ISET_LSB_SHIFT; val 120 drivers/video/backlight/arcxcnn_bl.c ARCXCNN_WLED_ISET_LSB, val); val 125 drivers/video/backlight/arcxcnn_bl.c val = (brightness >> 4); val 127 drivers/video/backlight/arcxcnn_bl.c ARCXCNN_WLED_ISET_MSB, val); val 100 drivers/video/backlight/corgi_lcd.c static int corgi_ssp_lcdtg_send(struct corgi_lcd *lcd, int reg, uint8_t val); val 44 drivers/video/backlight/da903x_bl.c uint8_t val; val 65 drivers/video/backlight/da903x_bl.c val = DA9030_WLED_TRIM(brightness); val 66 drivers/video/backlight/da903x_bl.c val |= brightness ? DA9030_WLED_CP_EN : 0; val 67 drivers/video/backlight/da903x_bl.c ret = da903x_write(dev, DA9030_WLED_CONTROL, val); val 53 drivers/video/backlight/ili9320.h int (*write)(struct ili9320 *ili, unsigned int reg, unsigned int val); val 55 drivers/video/backlight/lm3533_bl.c u8 val; val 58 drivers/video/backlight/lm3533_bl.c ret = lm3533_ctrlbank_get_brightness(&bl->cb, &val); val 62 drivers/video/backlight/lm3533_bl.c return val; val 92 drivers/video/backlight/lm3533_bl.c u8 val; val 97 drivers/video/backlight/lm3533_bl.c ret = lm3533_read(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, &val); val 102 drivers/video/backlight/lm3533_bl.c enable = val & mask; val 114 drivers/video/backlight/lm3533_bl.c u8 val; val 124 drivers/video/backlight/lm3533_bl.c val = mask; val 126 drivers/video/backlight/lm3533_bl.c val = 0; val 128 drivers/video/backlight/lm3533_bl.c ret = lm3533_update(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, val, val 140 drivers/video/backlight/lm3533_bl.c u8 val; val 145 drivers/video/backlight/lm3533_bl.c ret = lm3533_read(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, &val); val 151 drivers/video/backlight/lm3533_bl.c if (val & mask) val 166 drivers/video/backlight/lm3533_bl.c u8 val; val 175 drivers/video/backlight/lm3533_bl.c val = mask; val 177 drivers/video/backlight/lm3533_bl.c val = 0; val 179 drivers/video/backlight/lm3533_bl.c ret = lm3533_update(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, val, val 192 drivers/video/backlight/lm3533_bl.c u8 val; val 195 drivers/video/backlight/lm3533_bl.c ret = lm3533_ctrlbank_get_pwm(&bl->cb, &val); val 199 drivers/video/backlight/lm3533_bl.c return scnprintf(buf, PAGE_SIZE, "%u\n", val); val 207 drivers/video/backlight/lm3533_bl.c u8 val; val 210 drivers/video/backlight/lm3533_bl.c if (kstrtou8(buf, 0, &val)) val 213 drivers/video/backlight/lm3533_bl.c ret = lm3533_ctrlbank_set_pwm(&bl->cb, val); val 406 drivers/video/backlight/lm3630a_bl.c u32 bank, val; val 456 drivers/video/backlight/lm3630a_bl.c &val); val 459 drivers/video/backlight/lm3630a_bl.c pdata->ledb_init_brt = val; val 461 drivers/video/backlight/lm3630a_bl.c pdata->leda_init_brt = val; val 464 drivers/video/backlight/lm3630a_bl.c ret = fwnode_property_read_u32(node, "max-brightness", &val); val 467 drivers/video/backlight/lm3630a_bl.c pdata->ledb_max_brt = val; val 469 drivers/video/backlight/lm3630a_bl.c pdata->leda_max_brt = val; val 169 drivers/video/backlight/lp855x_bl.c u8 val, addr; val 197 drivers/video/backlight/lp855x_bl.c val = pd->initial_brightness; val 198 drivers/video/backlight/lp855x_bl.c ret = lp855x_write_byte(lp, lp->cfg->reg_brightness, val); val 202 drivers/video/backlight/lp855x_bl.c val = pd->device_control; val 203 drivers/video/backlight/lp855x_bl.c ret = lp855x_write_byte(lp, lp->cfg->reg_devicectrl, val); val 210 drivers/video/backlight/lp855x_bl.c val = pd->rom_data[i].val; val 214 drivers/video/backlight/lp855x_bl.c ret = lp855x_write_byte(lp, addr, val); val 379 drivers/video/backlight/lp855x_bl.c of_property_read_u8(child, "rom-val", &rom[i].val); val 76 drivers/video/backlight/lp8788_bl.c u8 val; val 92 drivers/video/backlight/lp8788_bl.c val = (cfg->rise_time << LP8788_BL_RAMP_RISE_SHIFT) | cfg->fall_time; val 93 drivers/video/backlight/lp8788_bl.c ret = lp8788_write_byte(bl->lp, LP8788_BL_RAMP, val); val 98 drivers/video/backlight/lp8788_bl.c val = (cfg->full_scale << LP8788_BL_FULLSCALE_SHIFT) | val 104 drivers/video/backlight/lp8788_bl.c val |= LP8788_BL_EN; val 108 drivers/video/backlight/lp8788_bl.c val |= LP8788_BL_EN | LP8788_BL_PWM_INPUT_EN | val 118 drivers/video/backlight/lp8788_bl.c return lp8788_write_byte(bl->lp, LP8788_BL_CONFIG, val); val 37 drivers/video/backlight/ltv350qv.c static int ltv350qv_write_reg(struct ltv350qv *lcd, u8 reg, u16 val) val 59 drivers/video/backlight/ltv350qv.c lcd->buffer[5] = val >> 8; val 60 drivers/video/backlight/ltv350qv.c lcd->buffer[6] = val; val 105 drivers/video/backlight/max8925_bl.c u32 val; val 122 drivers/video/backlight/max8925_bl.c if (!of_property_read_u32(np, "maxim,max8925-dual-string", &val)) val 123 drivers/video/backlight/max8925_bl.c pdata->dual_string = val; val 84 drivers/video/backlight/pm8941-wled.c u16 val = bl->props.brightness; val 92 drivers/video/backlight/pm8941-wled.c val = 0; val 94 drivers/video/backlight/pm8941-wled.c if (val != 0) val 104 drivers/video/backlight/pm8941-wled.c u8 v[2] = { val & 0xff, (val >> 8) & 0xf }; val 270 drivers/video/backlight/pm8941-wled.c u32 val; val 316 drivers/video/backlight/pm8941-wled.c rc = of_property_read_u32(dev->of_node, "reg", &val); val 317 drivers/video/backlight/pm8941-wled.c if (rc || val > 0xffff) { val 321 drivers/video/backlight/pm8941-wled.c wled->addr = val; val 329 drivers/video/backlight/pm8941-wled.c rc = of_property_read_u32(dev->of_node, u32_opts[i].name, &val); val 338 drivers/video/backlight/pm8941-wled.c for (j = 0; c != val; j++) { val 371 drivers/video/backlight/pm8941-wled.c u32 val; val 394 drivers/video/backlight/pm8941-wled.c val = PM8941_WLED_DEFAULT_BRIGHTNESS; val 395 drivers/video/backlight/pm8941-wled.c of_property_read_u32(pdev->dev.of_node, "default-brightness", &val); val 399 drivers/video/backlight/pm8941-wled.c props.brightness = val; val 189 drivers/video/backlight/tps65217_bl.c u32 val; val 202 drivers/video/backlight/tps65217_bl.c if (!of_property_read_u32(node, "isel", &val)) { val 203 drivers/video/backlight/tps65217_bl.c if (val < TPS65217_BL_ISET1 || val 204 drivers/video/backlight/tps65217_bl.c val > TPS65217_BL_ISET2) { val 211 drivers/video/backlight/tps65217_bl.c pdata->isel = val; val 215 drivers/video/backlight/tps65217_bl.c if (!of_property_read_u32(node, "fdim", &val)) { val 216 drivers/video/backlight/tps65217_bl.c switch (val) { val 241 drivers/video/backlight/tps65217_bl.c if (!of_property_read_u32(node, "default-brightness", &val)) { val 242 drivers/video/backlight/tps65217_bl.c if (val > 100) { val 249 drivers/video/backlight/tps65217_bl.c pdata->dft_brightness = val; val 108 drivers/video/console/mdacon.c static void write_mda_b(unsigned int val, unsigned char reg) val 115 drivers/video/console/mdacon.c outb_p(val, mda_value_port); val 120 drivers/video/console/mdacon.c static void write_mda_w(unsigned int val, unsigned char reg) val 126 drivers/video/console/mdacon.c outb_p(reg, mda_index_port); outb_p(val >> 8, mda_value_port); val 127 drivers/video/console/mdacon.c outb_p(reg+1, mda_index_port); outb_p(val & 0xff, mda_value_port); val 133 drivers/video/console/mdacon.c static int test_mda_b(unsigned char val, unsigned char reg) val 140 drivers/video/console/mdacon.c outb (val, mda_value_port); val 142 drivers/video/console/mdacon.c udelay(20); val = (inb_p(mda_value_port) == val); val 145 drivers/video/console/mdacon.c return val; val 70 drivers/video/console/newport_con.c #define XSTI_TO_FXSTART(val) (((val) & 0xffff) << 11) val 146 drivers/video/console/vgacon.c static inline void write_vga(unsigned char reg, unsigned int val) val 156 drivers/video/console/vgacon.c v1 = reg + (val & 0xff00); val 157 drivers/video/console/vgacon.c v2 = reg + 1 + ((val << 8) & 0xff00); val 315 drivers/video/fbdev/68328fb.c #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) val 65 drivers/video/fbdev/amba-clcd.c u32 val; val 75 drivers/video/fbdev/amba-clcd.c val = readl(fb->regs + fb->off_cntl); val 76 drivers/video/fbdev/amba-clcd.c if (val & CNTL_LCDPWR) { val 77 drivers/video/fbdev/amba-clcd.c val &= ~CNTL_LCDPWR; val 78 drivers/video/fbdev/amba-clcd.c writel(val, fb->regs + fb->off_cntl); val 82 drivers/video/fbdev/amba-clcd.c if (val & CNTL_LCDEN) { val 83 drivers/video/fbdev/amba-clcd.c val &= ~CNTL_LCDEN; val 84 drivers/video/fbdev/amba-clcd.c writel(val, fb->regs + fb->off_cntl); val 336 drivers/video/fbdev/amba-clcd.c static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) val 340 drivers/video/fbdev/amba-clcd.c return (val >> (16 - bf->length) & mask) << bf->offset; val 361 drivers/video/fbdev/amba-clcd.c u32 val, mask, newval; val 381 drivers/video/fbdev/amba-clcd.c val = readl(fb->regs + hw_reg) & mask; val 382 drivers/video/fbdev/amba-clcd.c writel(val | newval, fb->regs + hw_reg); val 637 drivers/video/fbdev/amifb.c #define CMOVE(val, reg) (CUSTOM_OFS(reg) << 16 | (val)) val 638 drivers/video/fbdev/amifb.c #define CMOVE2(val, reg) ((CUSTOM_OFS(reg) + 2) << 16 | (val)) val 3032 drivers/video/fbdev/amifb.c unsigned long val = pat; val 3039 drivers/video/fbdev/amifb.c val |= val << 32; val 3049 drivers/video/fbdev/amifb.c *dst = comp(val, *dst, first); val 3054 drivers/video/fbdev/amifb.c *dst = comp(val, *dst, first); val 3062 drivers/video/fbdev/amifb.c *dst++ = val; val 3063 drivers/video/fbdev/amifb.c *dst++ = val; val 3064 drivers/video/fbdev/amifb.c *dst++ = val; val 3065 drivers/video/fbdev/amifb.c *dst++ = val; val 3066 drivers/video/fbdev/amifb.c *dst++ = val; val 3067 drivers/video/fbdev/amifb.c *dst++ = val; val 3068 drivers/video/fbdev/amifb.c *dst++ = val; val 3069 drivers/video/fbdev/amifb.c *dst++ = val; val 3073 drivers/video/fbdev/amifb.c *dst++ = val; val 3077 drivers/video/fbdev/amifb.c *dst = comp(val, *dst, last); val 3088 drivers/video/fbdev/amifb.c unsigned long val = pat; val 3095 drivers/video/fbdev/amifb.c val |= val << 32; val 3105 drivers/video/fbdev/amifb.c *dst = xor(val, *dst, first); val 3110 drivers/video/fbdev/amifb.c *dst = xor(val, *dst, first); val 3118 drivers/video/fbdev/amifb.c *dst++ ^= val; val 3119 drivers/video/fbdev/amifb.c *dst++ ^= val; val 3120 drivers/video/fbdev/amifb.c *dst++ ^= val; val 3121 drivers/video/fbdev/amifb.c *dst++ ^= val; val 3125 drivers/video/fbdev/amifb.c *dst++ ^= val; val 3129 drivers/video/fbdev/amifb.c *dst = xor(val, *dst, last); val 253 drivers/video/fbdev/arcfb.c unsigned char val; val 270 drivers/video/fbdev/arcfb.c val = 0; val 273 drivers/video/fbdev/arcfb.c val |= (*(src + (i*linesize)) & bitmask) val 276 drivers/video/fbdev/arcfb.c val |= (*(src + (i*linesize)) & bitmask) val 280 drivers/video/fbdev/arcfb.c ks108_writeb_data(par, chipindex, val); val 181 drivers/video/fbdev/arkfb.c u32 val; val 192 drivers/video/fbdev/arkfb.c val = *(src++) * 0x01010101; val 193 drivers/video/fbdev/arkfb.c val = (val & fg) | (~val & bg); val 194 drivers/video/fbdev/arkfb.c fb_writel(val, dst++); val 239 drivers/video/fbdev/arkfb.c u32 val; val 250 drivers/video/fbdev/arkfb.c val = expand_pixel(*(src++)); val 251 drivers/video/fbdev/arkfb.c val = (val & fg) | (~val & bg); val 252 drivers/video/fbdev/arkfb.c fb_writel(val, dst++); val 333 drivers/video/fbdev/arkfb.c static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val) val 335 drivers/video/fbdev/arkfb.c u8 code[2] = {reg, val}; val 50 drivers/video/fbdev/asiliantfb.c #define mm_write_ind(num, val, ap, dp) do { \ val 51 drivers/video/fbdev/asiliantfb.c writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \ val 58 drivers/video/fbdev/asiliantfb.c #define write_xr(num, val) mm_write_xr(p, num, val) val 64 drivers/video/fbdev/asiliantfb.c #define write_fr(num, val) mm_write_fr(p, num, val) val 70 drivers/video/fbdev/asiliantfb.c #define write_cr(num, val) mm_write_cr(p, num, val) val 76 drivers/video/fbdev/asiliantfb.c #define write_gr(num, val) mm_write_gr(p, num, val) val 82 drivers/video/fbdev/asiliantfb.c #define write_sr(num, val) mm_write_sr(p, num, val) val 89 drivers/video/fbdev/asiliantfb.c #define write_ar(num, val) mm_write_ar(p, num, val) val 2200 drivers/video/fbdev/atafb.c #define OUTB(port,val) \ val 2201 drivers/video/fbdev/atafb.c *((unsigned volatile char *) ((port)+external_vgaiobase)) = (val) val 71 drivers/video/fbdev/atmel_lcdfb.c #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg)) val 729 drivers/video/fbdev/atmel_lcdfb.c unsigned int val; val 742 drivers/video/fbdev/atmel_lcdfb.c val = chan_to_field(red, &info->var.red); val 743 drivers/video/fbdev/atmel_lcdfb.c val |= chan_to_field(green, &info->var.green); val 744 drivers/video/fbdev/atmel_lcdfb.c val |= chan_to_field(blue, &info->var.blue); val 746 drivers/video/fbdev/atmel_lcdfb.c pal[regno] = val; val 755 drivers/video/fbdev/atmel_lcdfb.c val = ((red >> 11) & 0x001f); val 756 drivers/video/fbdev/atmel_lcdfb.c val |= ((green >> 6) & 0x03e0); val 757 drivers/video/fbdev/atmel_lcdfb.c val |= ((blue >> 1) & 0x7c00); val 766 drivers/video/fbdev/atmel_lcdfb.c val = ((blue >> 11) & 0x001f); val 767 drivers/video/fbdev/atmel_lcdfb.c val |= ((red >> 0) & 0xf800); val 769 drivers/video/fbdev/atmel_lcdfb.c val = ((red >> 11) & 0x001f); val 770 drivers/video/fbdev/atmel_lcdfb.c val |= ((blue >> 0) & 0xf800); val 773 drivers/video/fbdev/atmel_lcdfb.c val |= ((green >> 5) & 0x07e0); val 776 drivers/video/fbdev/atmel_lcdfb.c lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val); val 783 drivers/video/fbdev/atmel_lcdfb.c val = (regno == 0) ? 0x00 : 0x1F; val 784 drivers/video/fbdev/atmel_lcdfb.c lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val); val 537 drivers/video/fbdev/aty/aty128fb.c static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, val 540 drivers/video/fbdev/aty/aty128fb.c writel (val, par->regbase + regindex); val 549 drivers/video/fbdev/aty/aty128fb.c static inline void _aty_st_8(unsigned int regindex, u8 val, val 552 drivers/video/fbdev/aty/aty128fb.c writeb (val, par->regbase + regindex); val 556 drivers/video/fbdev/aty/aty128fb.c #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) val 558 drivers/video/fbdev/aty/aty128fb.c #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) val 565 drivers/video/fbdev/aty/aty128fb.c #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) val 576 drivers/video/fbdev/aty/aty128fb.c static void _aty_st_pll(unsigned int pll_index, u32 val, val 580 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(CLOCK_CNTL_DATA, val); val 620 drivers/video/fbdev/aty/aty128fb.c u32 val; val 623 drivers/video/fbdev/aty/aty128fb.c val = aty_ld_le32(BIOS_0_SCRATCH); val 633 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(BIOS_0_SCRATCH, val); // restore value val 239 drivers/video/fbdev/aty/atyfb.h static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par) val 246 drivers/video/fbdev/aty/atyfb.h out_le32(par->ati_regbase + regindex, val); val 248 drivers/video/fbdev/aty/atyfb.h writel(val, par->ati_regbase + regindex); val 252 drivers/video/fbdev/aty/atyfb.h static inline void aty_st_le16(int regindex, u16 val, val 259 drivers/video/fbdev/aty/atyfb.h out_le16(par->ati_regbase + regindex, val); val 261 drivers/video/fbdev/aty/atyfb.h writel(val, par->ati_regbase + regindex); val 277 drivers/video/fbdev/aty/atyfb.h static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par) val 284 drivers/video/fbdev/aty/atyfb.h out_8(par->ati_regbase + regindex, val); val 286 drivers/video/fbdev/aty/atyfb.h writeb(val, par->ati_regbase + regindex); val 292 drivers/video/fbdev/aty/atyfb.h extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par); val 149 drivers/video/fbdev/aty/atyfb_base.c void aty_st_lcd(int index, u32 val, const struct atyfb_par *par) val 152 drivers/video/fbdev/aty/atyfb_base.c aty_st_le32(lt_lcd_regs[index], val, par); val 160 drivers/video/fbdev/aty/atyfb_base.c aty_st_le32(LCD_DATA, val, par); val 34 drivers/video/fbdev/aty/mach64_ct.c static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par) val 39 drivers/video/fbdev/aty/mach64_ct.c aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par); val 69 drivers/video/fbdev/aty/mach64_gx.c static void aty_st_514(int offset, u8 val, const struct atyfb_par *par) val 76 drivers/video/fbdev/aty/mach64_gx.c aty_st_8(DAC_MASK, val, par); val 235 drivers/video/fbdev/aty/radeon_base.c u32 val; val 315 drivers/video/fbdev/aty/radeon_base.c void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask) val 323 drivers/video/fbdev/aty/radeon_base.c tmp |= (val); val 339 drivers/video/fbdev/aty/radeon_base.c void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val) val 343 drivers/video/fbdev/aty/radeon_base.c OUTREG(CLOCK_CNTL_DATA, val); val 348 drivers/video/fbdev/aty/radeon_base.c u32 val, u32 mask) val 354 drivers/video/fbdev/aty/radeon_base.c tmp |= (val); val 551 drivers/video/fbdev/aty/radeon_base.c const u32 *val; val 555 drivers/video/fbdev/aty/radeon_base.c val = of_get_property(dp, "ATY,RefCLK", NULL); val 556 drivers/video/fbdev/aty/radeon_base.c if (!val || !*val) { val 561 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = (*val) / 10; val 563 drivers/video/fbdev/aty/radeon_base.c val = of_get_property(dp, "ATY,SCLK", NULL); val 564 drivers/video/fbdev/aty/radeon_base.c if (val && *val) val 565 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = (*val) / 10; val 567 drivers/video/fbdev/aty/radeon_base.c val = of_get_property(dp, "ATY,MCLK", NULL); val 568 drivers/video/fbdev/aty/radeon_base.c if (val && *val) val 569 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = (*val) / 10; val 1049 drivers/video/fbdev/aty/radeon_base.c u32 val; val 1058 drivers/video/fbdev/aty/radeon_base.c val = INREG(CRTC_EXT_CNTL); val 1059 drivers/video/fbdev/aty/radeon_base.c val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | val 1063 drivers/video/fbdev/aty/radeon_base.c val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS); val 1066 drivers/video/fbdev/aty/radeon_base.c val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS); val 1069 drivers/video/fbdev/aty/radeon_base.c val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | val 1073 drivers/video/fbdev/aty/radeon_base.c val |= CRTC_DISPLAY_DIS; val 1079 drivers/video/fbdev/aty/radeon_base.c OUTREG(CRTC_EXT_CNTL, val); val 1095 drivers/video/fbdev/aty/radeon_base.c val = INREG(LVDS_GEN_CNTL); val 1097 drivers/video/fbdev/aty/radeon_base.c u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON val 1100 drivers/video/fbdev/aty/radeon_base.c if ((val ^ target_val) == LVDS_DISPLAY_DIS) val 1102 drivers/video/fbdev/aty/radeon_base.c else if ((val ^ target_val) != 0) { val 1120 drivers/video/fbdev/aty/radeon_base.c val |= LVDS_DISPLAY_DIS; val 1121 drivers/video/fbdev/aty/radeon_base.c OUTREG(LVDS_GEN_CNTL, val); val 1133 drivers/video/fbdev/aty/radeon_base.c val &= ~(LVDS_BL_MOD_EN); val 1134 drivers/video/fbdev/aty/radeon_base.c OUTREG(LVDS_GEN_CNTL, val); val 1136 drivers/video/fbdev/aty/radeon_base.c val &= ~(LVDS_ON | LVDS_EN); val 1137 drivers/video/fbdev/aty/radeon_base.c OUTREG(LVDS_GEN_CNTL, val); val 1138 drivers/video/fbdev/aty/radeon_base.c val &= ~LVDS_DIGON; val 1139 drivers/video/fbdev/aty/radeon_base.c rinfo->pending_lvds_gen_cntl = val; val 1144 drivers/video/fbdev/aty/radeon_base.c rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; val 1480 drivers/video/fbdev/aty/radeon_base.c OUTREG(common_regs[i].reg, common_regs[i].val); val 22 drivers/video/fbdev/aty/radeon_i2c.c u32 val; val 24 drivers/video/fbdev/aty/radeon_i2c.c val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN); val 26 drivers/video/fbdev/aty/radeon_i2c.c val |= VGA_DDC_CLK_OUT_EN; val 28 drivers/video/fbdev/aty/radeon_i2c.c OUTREG(chan->ddc_reg, val); val 36 drivers/video/fbdev/aty/radeon_i2c.c u32 val; val 38 drivers/video/fbdev/aty/radeon_i2c.c val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN); val 40 drivers/video/fbdev/aty/radeon_i2c.c val |= VGA_DDC_DATA_OUT_EN; val 42 drivers/video/fbdev/aty/radeon_i2c.c OUTREG(chan->ddc_reg, val); val 50 drivers/video/fbdev/aty/radeon_i2c.c u32 val; val 52 drivers/video/fbdev/aty/radeon_i2c.c val = INREG(chan->ddc_reg); val 54 drivers/video/fbdev/aty/radeon_i2c.c return (val & VGA_DDC_CLK_INPUT) ? 1 : 0; val 61 drivers/video/fbdev/aty/radeon_i2c.c u32 val; val 63 drivers/video/fbdev/aty/radeon_i2c.c val = INREG(chan->ddc_reg); val 65 drivers/video/fbdev/aty/radeon_i2c.c return (val & VGA_DDC_DATA_INPUT) ? 1 : 0; val 377 drivers/video/fbdev/aty/radeonfb.h #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) val 379 drivers/video/fbdev/aty/radeonfb.h #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) val 381 drivers/video/fbdev/aty/radeonfb.h #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) val 383 drivers/video/fbdev/aty/radeonfb.h void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask); val 385 drivers/video/fbdev/aty/radeonfb.h #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) val 419 drivers/video/fbdev/aty/radeonfb.h void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val); val 421 drivers/video/fbdev/aty/radeonfb.h u32 val, u32 mask); val 424 drivers/video/fbdev/aty/radeonfb.h #define OUTPLL(index, val) __OUTPLL(rinfo, index, val) val 425 drivers/video/fbdev/aty/radeonfb.h #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) val 1291 drivers/video/fbdev/au1200fb.c unsigned int val, bpp; val 1295 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_OX | val 1297 drivers/video/fbdev/au1200fb.c val |= ((pdata->xpos << 21) & LCD_WINCTRL0_OX); val 1298 drivers/video/fbdev/au1200fb.c val |= ((pdata->ypos << 10) & LCD_WINCTRL0_OY); val 1299 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl0 = val; val 1302 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_A); val 1303 drivers/video/fbdev/au1200fb.c val |= ((pdata->alpha_color << 2) & LCD_WINCTRL0_A); val 1304 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl0 = val; val 1307 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_AEN); val 1308 drivers/video/fbdev/au1200fb.c val |= ((pdata->alpha_mode << 1) & LCD_WINCTRL0_AEN); val 1309 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl0 = val; val 1314 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PRI); val 1315 drivers/video/fbdev/au1200fb.c val |= ((pdata->priority << 30) & LCD_WINCTRL1_PRI); val 1316 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl1 = val; val 1319 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PIPE); val 1320 drivers/video/fbdev/au1200fb.c val |= ((pdata->channel << 29) & LCD_WINCTRL1_PIPE); val 1321 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl1 = val; val 1324 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_FRM); val 1325 drivers/video/fbdev/au1200fb.c val |= ((pdata->buffer_format << 25) & LCD_WINCTRL1_FRM); val 1326 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl1 = val; val 1329 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_CCO); val 1330 drivers/video/fbdev/au1200fb.c val |= ((pdata->color_order << 24) & LCD_WINCTRL1_CCO); val 1331 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl1 = val; val 1334 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PO); val 1335 drivers/video/fbdev/au1200fb.c val |= ((pdata->pixel_order << 22) & LCD_WINCTRL1_PO); val 1336 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl1 = val; val 1339 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_SZX | val 1341 drivers/video/fbdev/au1200fb.c val |= (((pdata->xsize << 11) - 1) & LCD_WINCTRL1_SZX); val 1342 drivers/video/fbdev/au1200fb.c val |= (((pdata->ysize) - 1) & LCD_WINCTRL1_SZY); val 1343 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl1 = val; val 1345 drivers/video/fbdev/au1200fb.c bpp = winbpp(val) / 8; val 1346 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_BX); val 1347 drivers/video/fbdev/au1200fb.c val |= (((pdata->xsize * bpp) << 8) & LCD_WINCTRL2_BX); val 1348 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl2 = val; val 1353 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_CKMODE); val 1354 drivers/video/fbdev/au1200fb.c val |= ((pdata->colorkey_mode << 24) & LCD_WINCTRL2_CKMODE); val 1355 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl2 = val; val 1358 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_DBM); val 1359 drivers/video/fbdev/au1200fb.c val |= ((pdata->double_buffer_mode << 23) & LCD_WINCTRL2_DBM); val 1360 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl2 = val; val 1363 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_RAM); val 1364 drivers/video/fbdev/au1200fb.c val |= ((pdata->ram_array_mode << 21) & LCD_WINCTRL2_RAM); val 1365 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl2 = val; val 1371 drivers/video/fbdev/au1200fb.c val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_SCX | val 1373 drivers/video/fbdev/au1200fb.c val |= ((pdata->xsize << 11) & LCD_WINCTRL2_SCX); val 1374 drivers/video/fbdev/au1200fb.c val |= ((pdata->ysize) & LCD_WINCTRL2_SCY); val 1375 drivers/video/fbdev/au1200fb.c lcd->window[plane].winctrl2 = val; val 1379 drivers/video/fbdev/au1200fb.c val = lcd->winenable; val 1380 drivers/video/fbdev/au1200fb.c val &= ~(1<<plane); val 1381 drivers/video/fbdev/au1200fb.c val |= (pdata->enable & 1) << plane; val 1382 drivers/video/fbdev/au1200fb.c lcd->winenable = val; val 1419 drivers/video/fbdev/au1200fb.c int val; val 1475 drivers/video/fbdev/au1200fb.c val = copy_to_user((void __user *) arg, &iodata, sizeof(iodata)); val 1476 drivers/video/fbdev/au1200fb.c if (val) { val 1477 drivers/video/fbdev/au1200fb.c print_dbg("error: could not copy %d bytes\n", val); val 364 drivers/video/fbdev/broadsheetfb.c u16 reg, int bitnum, int val, val 371 drivers/video/fbdev/broadsheetfb.c if (((tmp >> bitnum) & 1) == val) val 30 drivers/video/fbdev/bt431.h static inline u16 bt431_set_value(u8 val) val 32 drivers/video/fbdev/bt431.h return ((val << 8) | (val & 0xff)) & 0xffff; val 35 drivers/video/fbdev/bt431.h static inline u8 bt431_get_value(u16 val) val 37 drivers/video/fbdev/bt431.h return val & 0xff; val 214 drivers/video/fbdev/bt431.h u16 val = 0; val 217 drivers/video/fbdev/bt431.h val = mask[i]; val 219 drivers/video/fbdev/bt431.h val = (val << 8) | (val ^ data[i]); val 221 drivers/video/fbdev/bt431.h val = (val << 8) | (val & data[i]); val 224 drivers/video/fbdev/bt431.h bt431_write_cmap_inc(regs, val); val 128 drivers/video/fbdev/bw2.c u8 val; val 134 drivers/video/fbdev/bw2.c val = sbus_readb(®s->control); val 135 drivers/video/fbdev/bw2.c val |= BWTWO_CTL_ENABLE_VIDEO; val 136 drivers/video/fbdev/bw2.c sbus_writeb(val, ®s->control); val 144 drivers/video/fbdev/bw2.c val = sbus_readb(®s->control); val 145 drivers/video/fbdev/bw2.c val &= ~BWTWO_CTL_ENABLE_VIDEO; val 146 drivers/video/fbdev/bw2.c sbus_writeb(val, ®s->control); val 140 drivers/video/fbdev/carminefb.c u32 offset, u32 val) val 142 drivers/video/fbdev/carminefb.c writel(val, par->display_reg + offset); val 152 drivers/video/fbdev/carminefb.c u32 offset, u32 val) val 154 drivers/video/fbdev/carminefb.c writel(val, hw->v_regs + offset); val 210 drivers/video/fbdev/cg14.c u8 val; val 212 drivers/video/fbdev/cg14.c val = sbus_readb(®s->mcr); val 213 drivers/video/fbdev/cg14.c val &= ~(CG14_MCR_PIXMODE_MASK); val 214 drivers/video/fbdev/cg14.c sbus_writeb(val, ®s->mcr); val 250 drivers/video/fbdev/cg14.c u32 val; val 258 drivers/video/fbdev/cg14.c val = (red | (green << 8) | (blue << 16)); val 261 drivers/video/fbdev/cg14.c sbus_writel(val, &clut->c_clut[regno]); val 190 drivers/video/fbdev/cg3.c u8 val; val 196 drivers/video/fbdev/cg3.c val = sbus_readb(®s->control); val 197 drivers/video/fbdev/cg3.c val |= CG3_CR_ENABLE_VIDEO; val 198 drivers/video/fbdev/cg3.c sbus_writeb(val, ®s->control); val 206 drivers/video/fbdev/cg3.c val = sbus_readb(®s->control); val 207 drivers/video/fbdev/cg3.c val &= ~CG3_CR_ENABLE_VIDEO; val 208 drivers/video/fbdev/cg3.c sbus_writeb(val, ®s->control); val 322 drivers/video/fbdev/cg6.c s32 val; val 341 drivers/video/fbdev/cg6.c val = sbus_readl(&fbc->draw); val 342 drivers/video/fbdev/cg6.c } while (val < 0 && (val & 0x20000000)); val 429 drivers/video/fbdev/cg6.c u32 val; val 435 drivers/video/fbdev/cg6.c val = ((u32)data[0] << 24) | val 439 drivers/video/fbdev/cg6.c sbus_writel(val, &fbc->font); val 446 drivers/video/fbdev/cg6.c u32 val; val 452 drivers/video/fbdev/cg6.c val = (u32) data[0] << 24; val 455 drivers/video/fbdev/cg6.c val = ((u32) data[0] << 24) | val 459 drivers/video/fbdev/cg6.c val = ((u32) data[0] << 24) | val 464 drivers/video/fbdev/cg6.c sbus_writel(val, &fbc->font); val 522 drivers/video/fbdev/cg6.c u32 val; val 525 drivers/video/fbdev/cg6.c val = sbus_readl(&thc->thc_misc); val 529 drivers/video/fbdev/cg6.c val |= CG6_THC_MISC_VIDEO; val 537 drivers/video/fbdev/cg6.c val &= ~CG6_THC_MISC_VIDEO; val 542 drivers/video/fbdev/cg6.c sbus_writel(val, &thc->thc_misc); val 39 drivers/video/fbdev/chipsfb.c #define write_ind(num, val, ap, dp) do { \ val 40 drivers/video/fbdev/chipsfb.c outb((num), (ap)); outb((val), (dp)); \ val 47 drivers/video/fbdev/chipsfb.c #define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7) val 50 drivers/video/fbdev/chipsfb.c #define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1) val 53 drivers/video/fbdev/chipsfb.c #define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5) val 56 drivers/video/fbdev/chipsfb.c #define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf) val 59 drivers/video/fbdev/chipsfb.c #define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5) val 62 drivers/video/fbdev/chipsfb.c #define write_ar(num, val) do { \ val 63 drivers/video/fbdev/chipsfb.c inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \ val 383 drivers/video/fbdev/cirrusfb.c int regnum, unsigned char val); val 386 drivers/video/fbdev/cirrusfb.c static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val); val 387 drivers/video/fbdev/cirrusfb.c static void WSFR(struct cirrusfb_info *cinfo, unsigned char val); val 388 drivers/video/fbdev/cirrusfb.c static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val); val 1390 drivers/video/fbdev/cirrusfb.c unsigned char val; val 1406 drivers/video/fbdev/cirrusfb.c val = 0; val 1409 drivers/video/fbdev/cirrusfb.c val = 0x20; val 1411 drivers/video/fbdev/cirrusfb.c val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf; val 1412 drivers/video/fbdev/cirrusfb.c vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val); val 1417 drivers/video/fbdev/cirrusfb.c val = 0x00; val 1420 drivers/video/fbdev/cirrusfb.c val = 0x04; val 1423 drivers/video/fbdev/cirrusfb.c val = 0x02; val 1426 drivers/video/fbdev/cirrusfb.c val = 0x06; val 1433 drivers/video/fbdev/cirrusfb.c vga_wgfx(cinfo->regbase, CL_GRE, val); val 2408 drivers/video/fbdev/cirrusfb.c int regnum, unsigned char val) val 2420 drivers/video/fbdev/cirrusfb.c vga_w(cinfo->regbase, regofs + regnum, val); val 2464 drivers/video/fbdev/cirrusfb.c static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val) val 2490 drivers/video/fbdev/cirrusfb.c WGen(cinfo, VGA_PEL_MSK, val); val 2506 drivers/video/fbdev/cirrusfb.c static void WSFR(struct cirrusfb_info *cinfo, unsigned char val) val 2510 drivers/video/fbdev/cirrusfb.c cinfo->SFR = val; val 2511 drivers/video/fbdev/cirrusfb.c z_writeb(val, cinfo->regbase + 0x8000); val 2516 drivers/video/fbdev/cirrusfb.c static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val) val 2522 drivers/video/fbdev/cirrusfb.c cinfo->SFR = val; val 2523 drivers/video/fbdev/cirrusfb.c z_writeb(val, cinfo->regbase + 0x9000); val 2819 drivers/video/fbdev/cirrusfb.c unsigned char val = 0; val 2831 drivers/video/fbdev/cirrusfb.c val = vga_rcrt(regbase, (unsigned char) reg); val 2834 drivers/video/fbdev/cirrusfb.c val = vga_rseq(regbase, (unsigned char) reg); val 2842 drivers/video/fbdev/cirrusfb.c dev_dbg(info->device, "%8s = 0x%02X\n", name, val); val 70 drivers/video/fbdev/clps711x-fb.c u32 val; val 79 drivers/video/fbdev/clps711x-fb.c val = DIV_ROUND_UP(var->xres, 16) - 1; val 80 drivers/video/fbdev/clps711x-fb.c if (val < 0x01 || val > 0x3f) val 83 drivers/video/fbdev/clps711x-fb.c val = DIV_ROUND_UP(var->yres * var->xres * var->bits_per_pixel, 128); val 84 drivers/video/fbdev/clps711x-fb.c val--; val 85 drivers/video/fbdev/clps711x-fb.c if (val < 0x001 || val > 0x1fff) val 217 drivers/video/fbdev/clps711x-fb.c u32 val; val 305 drivers/video/fbdev/clps711x-fb.c ret = regmap_read(cfb->syscon, SYSCON_OFFSET, &val); val 309 drivers/video/fbdev/clps711x-fb.c if (!(val & SYSCON1_LCDEN)) { val 76 drivers/video/fbdev/cobalt_lcdfb.c u8 val = 0; val 80 drivers/video/fbdev/cobalt_lcdfb.c val = lcd_read_control(info); val 81 drivers/video/fbdev/cobalt_lcdfb.c val &= LCD_BUSY; val 82 drivers/video/fbdev/cobalt_lcdfb.c if (val != LCD_BUSY) val 91 drivers/video/fbdev/cobalt_lcdfb.c if (val == LCD_BUSY) val 150 drivers/video/fbdev/core/cfbfillrect.c unsigned long val = pat, dat; val 164 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(comp(dat ^ val, dat, first), dst); val 170 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(comp(dat ^ val, dat, first), dst); val 178 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 180 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 182 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 184 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 186 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 188 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 190 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 192 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 197 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(FB_READL(dst) ^ val, dst); val 203 drivers/video/fbdev/core/cfbfillrect.c FB_WRITEL(comp(dat ^ val, dat, last), dst); val 82 drivers/video/fbdev/core/cfbimgblt.c u32 color = 0, val, shift; val 94 drivers/video/fbdev/core/cfbimgblt.c val = 0; val 99 drivers/video/fbdev/core/cfbimgblt.c val = FB_READL(dst) & start_mask; val 109 drivers/video/fbdev/core/cfbimgblt.c val |= FB_SHIFT_HIGH(p, color, shift ^ bswapmask); val 111 drivers/video/fbdev/core/cfbimgblt.c FB_WRITEL(val, dst++); val 113 drivers/video/fbdev/core/cfbimgblt.c val = (shift == null_bits) ? 0 : val 124 drivers/video/fbdev/core/cfbimgblt.c FB_WRITEL((FB_READL(dst) & end_mask) | val, dst); val 145 drivers/video/fbdev/core/cfbimgblt.c u32 val, pitch = p->fix.line_length; val 157 drivers/video/fbdev/core/cfbimgblt.c shift = val = 0; val 167 drivers/video/fbdev/core/cfbimgblt.c val = FB_READL(dst) & start_mask; val 174 drivers/video/fbdev/core/cfbimgblt.c val |= FB_SHIFT_HIGH(p, color, shift ^ bswapmask); val 178 drivers/video/fbdev/core/cfbimgblt.c FB_WRITEL(val, dst++); val 179 drivers/video/fbdev/core/cfbimgblt.c val = (shift == null_bits) ? 0 : val 192 drivers/video/fbdev/core/cfbimgblt.c FB_WRITEL((FB_READL(dst) & end_mask) | val, dst); val 89 drivers/video/fbdev/core/fb_draw.h static inline unsigned long fb_rev_pixels_in_long(unsigned long val, val 93 drivers/video/fbdev/core/fb_draw.h val = comp(val >> 1, val << 1, REV_PIXELS_MASK1); val 95 drivers/video/fbdev/core/fb_draw.h val = comp(val >> 2, val << 2, REV_PIXELS_MASK2); val 97 drivers/video/fbdev/core/fb_draw.h val = comp(val >> 4, val << 4, REV_PIXELS_MASK4); val 98 drivers/video/fbdev/core/fb_draw.h return val; val 162 drivers/video/fbdev/core/fb_draw.h static inline unsigned long fb_rev_pixels_in_long(unsigned long val, val 165 drivers/video/fbdev/core/fb_draw.h return val; val 43 drivers/video/fbdev/core/fb_notify.c int fb_notifier_call_chain(unsigned long val, void *v) val 45 drivers/video/fbdev/core/fb_notify.c return blocking_notifier_call_chain(&fb_notifier_list, val, v); val 2730 drivers/video/fbdev/core/fbcon.c u8 val; val 2742 drivers/video/fbdev/core/fbcon.c val = vc->vc_palette[j++]; val 2743 drivers/video/fbdev/core/fbcon.c palette_red[k] = (val << 8) | val; val 2744 drivers/video/fbdev/core/fbcon.c val = vc->vc_palette[j++]; val 2745 drivers/video/fbdev/core/fbcon.c palette_green[k] = (val << 8) | val; val 2746 drivers/video/fbdev/core/fbcon.c val = vc->vc_palette[j++]; val 2747 drivers/video/fbdev/core/fbcon.c palette_blue[k] = (val << 8) | val; val 1215 drivers/video/fbdev/core/fbmon.c int fb_get_mode(int flags, u32 val, struct fb_var_screeninfo *var, struct fb_info *info) val 1273 drivers/video/fbdev/core/fbmon.c timings->vfreq = val; val 1277 drivers/video/fbdev/core/fbmon.c timings->hfreq = val; val 1281 drivers/video/fbdev/core/fbmon.c timings->dclk = PICOS2KHZ(val) * 1000; val 1414 drivers/video/fbdev/core/fbmon.c int fb_get_mode(int flags, u32 val, struct fb_var_screeninfo *var, val 138 drivers/video/fbdev/core/sysfillrect.c unsigned long val = pat; val 151 drivers/video/fbdev/core/sysfillrect.c *dst = comp(*dst ^ val, *dst, first); val 156 drivers/video/fbdev/core/sysfillrect.c *dst = comp(*dst ^ val, *dst, first); val 164 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 165 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 166 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 167 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 168 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 169 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 170 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 171 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 175 drivers/video/fbdev/core/sysfillrect.c *dst++ ^= val; val 178 drivers/video/fbdev/core/sysfillrect.c *dst = comp(*dst ^ val, *dst, last); val 57 drivers/video/fbdev/core/sysimgblt.c u32 color = 0, val, shift; val 68 drivers/video/fbdev/core/sysimgblt.c val = 0; val 73 drivers/video/fbdev/core/sysimgblt.c val = *dst & start_mask; val 83 drivers/video/fbdev/core/sysimgblt.c val |= FB_SHIFT_HIGH(p, color, shift); val 85 drivers/video/fbdev/core/sysimgblt.c *dst++ = val; val 87 drivers/video/fbdev/core/sysimgblt.c val = (shift == null_bits) ? 0 : val 98 drivers/video/fbdev/core/sysimgblt.c *dst |= val; val 117 drivers/video/fbdev/core/sysimgblt.c u32 val, pitch = p->fix.line_length; val 128 drivers/video/fbdev/core/sysimgblt.c shift = val = 0; val 138 drivers/video/fbdev/core/sysimgblt.c val = *dst & start_mask; val 145 drivers/video/fbdev/core/sysimgblt.c val |= FB_SHIFT_HIGH(p, color, shift); val 149 drivers/video/fbdev/core/sysimgblt.c *dst++ = val; val 150 drivers/video/fbdev/core/sysimgblt.c val = (shift == null_bits) ? 0 : val 163 drivers/video/fbdev/core/sysimgblt.c *dst |= val; val 110 drivers/video/fbdev/cyber2000fb.c #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg)) val 111 drivers/video/fbdev/cyber2000fb.c #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg)) val 112 drivers/video/fbdev/cyber2000fb.c #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg)) val 117 drivers/video/fbdev/cyber2000fb.c cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb) val 119 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb); val 123 drivers/video/fbdev/cyber2000fb.c cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb) val 125 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb); val 136 drivers/video/fbdev/cyber2000fb.c cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb) val 141 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writeb(val, 0x3c0, cfb); val 145 drivers/video/fbdev/cyber2000fb.c cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb) val 147 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb); val 261 drivers/video/fbdev/cyber2000fb.c static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf) val 265 drivers/video/fbdev/cyber2000fb.c return (val >> (16 - bf->length) & mask) << bf->offset; val 443 drivers/video/fbdev/cyber2000fb.c unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown; val 448 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writeb(val, 0x3c6, cfb); val 1175 drivers/video/fbdev/cyber2000fb.c static void cyber2000fb_ddc_setscl(void *data, int val) val 1182 drivers/video/fbdev/cyber2000fb.c if (!val) /* bit is inverted */ val 1190 drivers/video/fbdev/cyber2000fb.c static void cyber2000fb_ddc_setsda(void *data, int val) val 1197 drivers/video/fbdev/cyber2000fb.c if (!val) /* bit is inverted */ val 1396 drivers/video/fbdev/cyber2000fb.c unsigned char val; val 1398 drivers/video/fbdev/cyber2000fb.c val = cyber2000fb_readb(0x3cf, cfb) & 0x80; val 1399 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writeb(val, 0x3cf, cfb); val 1652 drivers/video/fbdev/cyber2000fb.c unsigned char val; val 1696 drivers/video/fbdev/cyber2000fb.c val = cyber2000_grphr(EXT_BUS_CTL, cfb); val 1697 drivers/video/fbdev/cyber2000fb.c if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) { val 1701 drivers/video/fbdev/cyber2000fb.c val |= EXT_BUS_CTL_PCIBURST_WRITE; val 1704 drivers/video/fbdev/cyber2000fb.c val |= EXT_BUS_CTL_PCIBURST_READ; val 1706 drivers/video/fbdev/cyber2000fb.c cyber2000_grphw(EXT_BUS_CTL, val, cfb); val 136 drivers/video/fbdev/da8xx-fb.c static void lcdc_write(unsigned int val, unsigned int addr) val 138 drivers/video/fbdev/da8xx-fb.c __raw_writel(val, da8xx_fb_reg_base + (addr)); val 591 drivers/video/fbdev/da8xx-fb.c #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) val 1034 drivers/video/fbdev/da8xx-fb.c unsigned long val, void *data) val 1039 drivers/video/fbdev/da8xx-fb.c if (val == CPUFREQ_POSTCHANGE) { val 129 drivers/video/fbdev/ep93xx-fb.c unsigned int val, unsigned int off) val 131 drivers/video/fbdev/ep93xx-fb.c __raw_writel(val, fbi->mmio_base + off); val 138 drivers/video/fbdev/ep93xx-fb.c unsigned int val, unsigned int reg) val 145 drivers/video/fbdev/ep93xx-fb.c ep93xxfb_writel(fbi, val, reg); val 161 drivers/video/fbdev/ep93xx-fb.c unsigned int val; val 168 drivers/video/fbdev/ep93xx-fb.c val = EP93XXFB_PIXELMODE_8BPP | EP93XXFB_PIXELMODE_COLOR_LUT | val 181 drivers/video/fbdev/ep93xx-fb.c val = EP93XXFB_PIXELMODE_16BPP | EP93XXFB_PIXELMODE_COLOR_555 | val 194 drivers/video/fbdev/ep93xx-fb.c val = EP93XXFB_PIXELMODE_24BPP | EP93XXFB_PIXELMODE_COLOR_888 | val 207 drivers/video/fbdev/ep93xx-fb.c val = EP93XXFB_PIXELMODE_32BPP | EP93XXFB_PIXELMODE_COLOR_888 | val 223 drivers/video/fbdev/ep93xx-fb.c ep93xxfb_writel(fbi, val, EP93XXFB_PIXELMODE); val 344 drivers/video/fbdev/ep93xx-fb.c static inline int ep93xxfb_convert_color(int val, int width) val 346 drivers/video/fbdev/ep93xx-fb.c return ((val << width) + 0x7fff - val) >> 16; val 567 drivers/video/fbdev/fb-puv3.c #define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16) val 593 drivers/video/fbdev/ffb.c u32 val = (((u32)data[0] << 24) | val 598 drivers/video/fbdev/ffb.c upa_writel(val, &fbc->font); val 613 drivers/video/fbdev/ffb.c u32 val = (((u32)data[0] << 24) | val 618 drivers/video/fbdev/ffb.c upa_writel(val, &fbc->font); val 678 drivers/video/fbdev/ffb.c u32 val; val 686 drivers/video/fbdev/ffb.c val = upa_readl(&dac->value); val 689 drivers/video/fbdev/ffb.c val |= FFB_DAC_TGEN_VIDE; val 697 drivers/video/fbdev/ffb.c val &= ~FFB_DAC_TGEN_VIDE; val 702 drivers/video/fbdev/ffb.c upa_writel(val, &dac->value); val 472 drivers/video/fbdev/fsl-diu-fb.c unsigned long val; val 475 drivers/video/fbdev/fsl-diu-fb.c if (!kstrtoul(s, 10, &val) && (val <= 2)) val 476 drivers/video/fbdev/fsl-diu-fb.c port = (enum fsl_diu_monitor_port) val; val 493 drivers/video/fbdev/fsl-diu-fb.c void wr_reg_wa(u32 *reg, u32 val) val 496 drivers/video/fbdev/fsl-diu-fb.c out_be32(reg, val); val 497 drivers/video/fbdev/fsl-diu-fb.c } while (in_be32(reg) != val); val 1181 drivers/video/fbdev/fsl-diu-fb.c static inline __u32 CNVT_TOHW(__u32 val, __u32 width) val 1183 drivers/video/fbdev/fsl-diu-fb.c return ((val << width) + 0x7FFF - val) >> 16; val 1847 drivers/video/fbdev/fsl-diu-fb.c unsigned long val; val 1858 drivers/video/fbdev/fsl-diu-fb.c if (!kstrtoul(opt + 4, 10, &val)) val 1859 drivers/video/fbdev/fsl-diu-fb.c default_bpp = val; val 201 drivers/video/fbdev/gbefb.c unsigned int val, x, y, vpixen_off; val 206 drivers/video/fbdev/gbefb.c val = gbe->vt_xy; val 207 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(VT_XY, FREEZE, val) == 1) val 211 drivers/video/fbdev/gbefb.c val = gbe->ovr_control; val 212 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(OVR_CONTROL, OVR_DMA_ENABLE, val, 0); val 213 drivers/video/fbdev/gbefb.c gbe->ovr_control = val; val 215 drivers/video/fbdev/gbefb.c val = gbe->frm_control; val 216 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, val, 0); val 217 drivers/video/fbdev/gbefb.c gbe->frm_control = val; val 219 drivers/video/fbdev/gbefb.c val = gbe->did_control; val 220 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DID_CONTROL, DID_DMA_ENABLE, val, 0); val 221 drivers/video/fbdev/gbefb.c gbe->did_control = val; val 227 drivers/video/fbdev/gbefb.c val = gbe->frm_inhwctrl; val 228 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, val)) { val 231 drivers/video/fbdev/gbefb.c val = gbe->ovr_inhwctrl; val 232 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(OVR_INHWCTRL, OVR_DMA_ENABLE, val)) { val 235 drivers/video/fbdev/gbefb.c val = gbe->did_inhwctrl; val 236 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(DID_INHWCTRL, DID_DMA_ENABLE, val)) { val 247 drivers/video/fbdev/gbefb.c val = gbe->vt_vpixen; val 248 drivers/video/fbdev/gbefb.c vpixen_off = GET_GBE_FIELD(VT_VPIXEN, VPIXEN_OFF, val); val 251 drivers/video/fbdev/gbefb.c val = gbe->vt_xy; val 252 drivers/video/fbdev/gbefb.c x = GET_GBE_FIELD(VT_XY, X, val); val 253 drivers/video/fbdev/gbefb.c y = GET_GBE_FIELD(VT_XY, Y, val); val 262 drivers/video/fbdev/gbefb.c val = gbe->vt_xy; val 263 drivers/video/fbdev/gbefb.c x = GET_GBE_FIELD(VT_XY, X, val); val 264 drivers/video/fbdev/gbefb.c y = GET_GBE_FIELD(VT_XY, Y, val); val 273 drivers/video/fbdev/gbefb.c val = 0; val 274 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_XY, FREEZE, val, 1); val 275 drivers/video/fbdev/gbefb.c gbe->vt_xy = val; val 278 drivers/video/fbdev/gbefb.c val = gbe->vt_xy; val 279 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(VT_XY, FREEZE, val) != 1) val 288 drivers/video/fbdev/gbefb.c val = gbe->dotclock; val 289 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, RUN, val, 0); val 290 drivers/video/fbdev/gbefb.c gbe->dotclock = val; val 293 drivers/video/fbdev/gbefb.c val = gbe->dotclock; val 294 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(DOTCLK, RUN, val)) val 303 drivers/video/fbdev/gbefb.c val = gbe->frm_size_tile; val 304 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_SIZE_TILE, FRM_FIFO_RESET, val, 1); val 305 drivers/video/fbdev/gbefb.c gbe->frm_size_tile = val; val 306 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_SIZE_TILE, FRM_FIFO_RESET, val, 0); val 307 drivers/video/fbdev/gbefb.c gbe->frm_size_tile = val; val 312 drivers/video/fbdev/gbefb.c unsigned int val, i; val 319 drivers/video/fbdev/gbefb.c val = gbe->vt_xy; val 320 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(VT_XY, FREEZE, val) == 0) val 325 drivers/video/fbdev/gbefb.c val = gbe->dotclock; val 326 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, RUN, val, 1); val 327 drivers/video/fbdev/gbefb.c gbe->dotclock = val; val 330 drivers/video/fbdev/gbefb.c val = gbe->dotclock; val 331 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(DOTCLK, RUN, val) != 1) val 340 drivers/video/fbdev/gbefb.c val = 0; val 341 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_XY, FREEZE, val, 0); val 342 drivers/video/fbdev/gbefb.c gbe->vt_xy = val; val 345 drivers/video/fbdev/gbefb.c val = gbe->vt_xy; val 346 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(VT_XY, FREEZE, val)) val 355 drivers/video/fbdev/gbefb.c val = gbe->frm_control; val 356 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, val, 1); val 357 drivers/video/fbdev/gbefb.c gbe->frm_control = val; val 360 drivers/video/fbdev/gbefb.c val = gbe->frm_inhwctrl; val 361 drivers/video/fbdev/gbefb.c if (GET_GBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, val) != 1) val 535 drivers/video/fbdev/gbefb.c unsigned int val; val 538 drivers/video/fbdev/gbefb.c val = 0; val 539 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, M, val, timing->pll_m - 1); val 540 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, N, val, timing->pll_n - 1); val 541 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, P, val, timing->pll_p); val 542 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, RUN, val, 0); /* do not start yet */ val 543 drivers/video/fbdev/gbefb.c gbe->dotclock = val; val 547 drivers/video/fbdev/gbefb.c val = 0; val 548 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_XYMAX, MAXX, val, timing->htotal); val 549 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_XYMAX, MAXY, val, timing->vtotal); val 550 drivers/video/fbdev/gbefb.c gbe->vt_xymax = val; val 553 drivers/video/fbdev/gbefb.c val = 0; val 554 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VSYNC, VSYNC_ON, val, timing->vsync_start); val 555 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VSYNC, VSYNC_OFF, val, timing->vsync_end); val 556 drivers/video/fbdev/gbefb.c gbe->vt_vsync = val; val 557 drivers/video/fbdev/gbefb.c val = 0; val 558 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HSYNC, HSYNC_ON, val, timing->hsync_start); val 559 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HSYNC, HSYNC_OFF, val, timing->hsync_end); val 560 drivers/video/fbdev/gbefb.c gbe->vt_hsync = val; val 561 drivers/video/fbdev/gbefb.c val = 0; val 562 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VBLANK, VBLANK_ON, val, timing->vblank_start); val 563 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end); val 564 drivers/video/fbdev/gbefb.c gbe->vt_vblank = val; val 565 drivers/video/fbdev/gbefb.c val = 0; val 566 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HBLANK, HBLANK_ON, val, val 568 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HBLANK, HBLANK_OFF, val, val 570 drivers/video/fbdev/gbefb.c gbe->vt_hblank = val; val 573 drivers/video/fbdev/gbefb.c val = 0; val 574 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VCMAP, VCMAP_ON, val, timing->vblank_start); val 575 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end); val 576 drivers/video/fbdev/gbefb.c gbe->vt_vcmap = val; val 577 drivers/video/fbdev/gbefb.c val = 0; val 578 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HCMAP, HCMAP_ON, val, timing->hblank_start); val 579 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HCMAP, HCMAP_OFF, val, timing->hblank_end); val 580 drivers/video/fbdev/gbefb.c gbe->vt_hcmap = val; val 582 drivers/video/fbdev/gbefb.c val = 0; val 590 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DID_START_XY, DID_STARTY, val, (u32) temp); val 592 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DID_START_XY, DID_STARTX, val, val 595 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DID_START_XY, DID_STARTX, val, val 597 drivers/video/fbdev/gbefb.c gbe->did_start_xy = val; val 599 drivers/video/fbdev/gbefb.c val = 0; val 600 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(CRS_START_XY, CRS_STARTY, val, (u32) (temp + 1)); val 602 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(CRS_START_XY, CRS_STARTX, val, val 605 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(CRS_START_XY, CRS_STARTX, val, val 608 drivers/video/fbdev/gbefb.c gbe->crs_start_xy = val; val 610 drivers/video/fbdev/gbefb.c val = 0; val 611 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VC_START_XY, VC_STARTY, val, (u32) temp); val 612 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VC_START_XY, VC_STARTX, val, timing->hblank_end - 4); val 613 drivers/video/fbdev/gbefb.c gbe->vc_start_xy = val; val 615 drivers/video/fbdev/gbefb.c val = 0; val 620 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HPIXEN, HPIXEN_ON, val, temp); val 621 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HPIXEN, HPIXEN_OFF, val, val 624 drivers/video/fbdev/gbefb.c gbe->vt_hpixen = val; val 626 drivers/video/fbdev/gbefb.c val = 0; val 627 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end); val 628 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VPIXEN, VPIXEN_OFF, val, timing->vblank_start); val 629 drivers/video/fbdev/gbefb.c gbe->vt_vpixen = val; val 632 drivers/video/fbdev/gbefb.c val = 0; val 633 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_FLAGS, SYNC_LOW, val, 1); val 634 drivers/video/fbdev/gbefb.c gbe->vt_flags = val; val 644 drivers/video/fbdev/gbefb.c unsigned int val; val 665 drivers/video/fbdev/gbefb.c val = 0; val 668 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(WID, TYP, val, GBE_CMODE_I8); val 672 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(WID, TYP, val, GBE_CMODE_ARGB5); val 676 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(WID, TYP, val, GBE_CMODE_RGB8); val 680 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(WID, BUF, val, GBE_BMODE_BOTH); val 683 drivers/video/fbdev/gbefb.c gbe->mode_regs[i] = val; val 756 drivers/video/fbdev/gbefb.c val = 0; val 757 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_CONTROL, FRM_TILE_PTR, val, gbe_tiles.dma >> 9); val 758 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, val, 0); /* do not start */ val 759 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_CONTROL, FRM_LINEAR, val, 0); val 760 drivers/video/fbdev/gbefb.c gbe->frm_control = val; val 767 drivers/video/fbdev/gbefb.c val = 0; val 768 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_SIZE_TILE, FRM_WIDTH_TILE, val, wholeTilesX); val 769 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_SIZE_TILE, FRM_RHS, val, partTilesX); val 773 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, val, val 777 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, val, val 781 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, val, val 785 drivers/video/fbdev/gbefb.c gbe->frm_size_tile = val; val 790 drivers/video/fbdev/gbefb.c val = 0; val 791 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(FRM_SIZE_PIXEL, FB_HEIGHT_PIX, val, height_pix); val 792 drivers/video/fbdev/gbefb.c gbe->frm_size_pixel = val; val 22 drivers/video/fbdev/geode/display_gx.c unsigned int val; val 31 drivers/video/fbdev/geode/display_gx.c val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); val 33 drivers/video/fbdev/geode/display_gx.c val -= (lo & 0x000fffff); val 34 drivers/video/fbdev/geode/display_gx.c val += 1; val 37 drivers/video/fbdev/geode/display_gx.c return (val << 12); val 47 drivers/video/fbdev/geode/display_gx.c val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFFl; val 48 drivers/video/fbdev/geode/display_gx.c return (val << 19); val 171 drivers/video/fbdev/geode/display_gx.c int val; val 174 drivers/video/fbdev/geode/display_gx.c val = (red << 8) & 0xff0000; val 175 drivers/video/fbdev/geode/display_gx.c val |= (green) & 0x00ff00; val 176 drivers/video/fbdev/geode/display_gx.c val |= (blue >> 8) & 0x0000ff; val 179 drivers/video/fbdev/geode/display_gx.c write_dc(par, DC_PAL_DATA, val); val 25 drivers/video/fbdev/geode/display_gx1.c u8 val, ccr3; val 35 drivers/video/fbdev/geode/display_gx1.c val = inb(0x23); val 41 drivers/video/fbdev/geode/display_gx1.c return val; val 80 drivers/video/fbdev/geode/display_gx1.c u32 gcfg, tcfg, ocfg, dclk_div, val; val 161 drivers/video/fbdev/geode/display_gx1.c val = (hactive - 1) | ((htotal - 1) << 16); val 162 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_H_TIMING_1); val 163 drivers/video/fbdev/geode/display_gx1.c val = (hblankstart - 1) | ((hblankend - 1) << 16); val 164 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_H_TIMING_2); val 165 drivers/video/fbdev/geode/display_gx1.c val = (hsyncstart - 1) | ((hsyncend - 1) << 16); val 166 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_H_TIMING_3); val 167 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_FP_H_TIMING); val 168 drivers/video/fbdev/geode/display_gx1.c val = (vactive - 1) | ((vtotal - 1) << 16); val 169 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_V_TIMING_1); val 170 drivers/video/fbdev/geode/display_gx1.c val = (vblankstart - 1) | ((vblankend - 1) << 16); val 171 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_V_TIMING_2); val 172 drivers/video/fbdev/geode/display_gx1.c val = (vsyncstart - 1) | ((vsyncend - 1) << 16); val 173 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_V_TIMING_3); val 174 drivers/video/fbdev/geode/display_gx1.c val = (vsyncstart - 2) | ((vsyncend - 2) << 16); val 175 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_FP_V_TIMING); val 196 drivers/video/fbdev/geode/display_gx1.c int val; val 199 drivers/video/fbdev/geode/display_gx1.c val = (red << 2) & 0x3f000; val 200 drivers/video/fbdev/geode/display_gx1.c val |= (green >> 4) & 0x00fc0; val 201 drivers/video/fbdev/geode/display_gx1.c val |= (blue >> 10) & 0x0003f; val 204 drivers/video/fbdev/geode/display_gx1.c writel(val, par->dc_regs + DC_PAL_DATA); val 303 drivers/video/fbdev/geode/gxfb.h static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val) val 305 drivers/video/fbdev/geode/gxfb.h writel(val, par->gp_regs + 4*reg); val 313 drivers/video/fbdev/geode/gxfb.h static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val) val 315 drivers/video/fbdev/geode/gxfb.h writel(val, par->dc_regs + 4*reg); val 323 drivers/video/fbdev/geode/gxfb.h static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val) val 325 drivers/video/fbdev/geode/gxfb.h writel(val, par->vid_regs + 8*reg); val 333 drivers/video/fbdev/geode/gxfb.h static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val) val 335 drivers/video/fbdev/geode/gxfb.h writel(val, par->vid_regs + 8*reg + VP_FP_START); val 366 drivers/video/fbdev/geode/gxfb_core.c unsigned long val; val 383 drivers/video/fbdev/geode/gxfb_core.c rdmsrl(MSR_GX_GLD_MSR_CONFIG, val); val 385 drivers/video/fbdev/geode/gxfb_core.c if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP) val 386 drivers/video/fbdev/geode/lxfb.h static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val) val 388 drivers/video/fbdev/geode/lxfb.h writel(val, par->gp_regs + 4*reg); val 396 drivers/video/fbdev/geode/lxfb.h static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val) val 398 drivers/video/fbdev/geode/lxfb.h writel(val, par->dc_regs + 4*reg); val 406 drivers/video/fbdev/geode/lxfb.h static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val) val 408 drivers/video/fbdev/geode/lxfb.h writel(val, par->vp_regs + 8*reg); val 416 drivers/video/fbdev/geode/lxfb.h static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val) val 418 drivers/video/fbdev/geode/lxfb.h writel(val, par->vp_regs + 8*reg + VP_FP_START); val 183 drivers/video/fbdev/geode/lxfb_ops.c unsigned int val, gcfg; val 192 drivers/video/fbdev/geode/lxfb_ops.c val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE | val 195 drivers/video/fbdev/geode/lxfb_ops.c write_dc(par, DC_GENERAL_CFG, val); val 197 drivers/video/fbdev/geode/lxfb_ops.c val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN; val 198 drivers/video/fbdev/geode/lxfb_ops.c write_vp(par, VP_VCFG, val); val 203 drivers/video/fbdev/geode/lxfb_ops.c val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN; val 204 drivers/video/fbdev/geode/lxfb_ops.c write_dc(par, DC_GENLK_CTL, val); val 206 drivers/video/fbdev/geode/lxfb_ops.c val = read_dc(par, DC_CLR_KEY); val 207 drivers/video/fbdev/geode/lxfb_ops.c write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN); val 212 drivers/video/fbdev/geode/lxfb_ops.c val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN; val 213 drivers/video/fbdev/geode/lxfb_ops.c write_vp(par, VP_MISC, val); val 217 drivers/video/fbdev/geode/lxfb_ops.c val = read_vp(par, VP_DCFG); val 218 drivers/video/fbdev/geode/lxfb_ops.c write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN | val 226 drivers/video/fbdev/geode/lxfb_ops.c val = read_dc(par, DC_DISPLAY_CFG); val 227 drivers/video/fbdev/geode/lxfb_ops.c val &= ~DC_DISPLAY_CFG_TGEN; val 228 drivers/video/fbdev/geode/lxfb_ops.c write_dc(par, DC_DISPLAY_CFG, val); val 241 drivers/video/fbdev/geode/lxfb_ops.c val = read_gp(par, GP_BLT_STATUS); val 242 drivers/video/fbdev/geode/lxfb_ops.c } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE)); val 312 drivers/video/fbdev/geode/lxfb_ops.c unsigned int val; val 321 drivers/video/fbdev/geode/lxfb_ops.c val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); val 323 drivers/video/fbdev/geode/lxfb_ops.c val -= (lo & 0x000fffff); val 324 drivers/video/fbdev/geode/lxfb_ops.c val += 1; val 327 drivers/video/fbdev/geode/lxfb_ops.c return (val << 12); val 337 drivers/video/fbdev/geode/lxfb_ops.c val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE; val 338 drivers/video/fbdev/geode/lxfb_ops.c return (val << 20); val 346 drivers/video/fbdev/geode/lxfb_ops.c unsigned int max, dv, val, size; val 386 drivers/video/fbdev/geode/lxfb_ops.c val = read_dc(par, DC_GENLK_CTL); val 387 drivers/video/fbdev/geode/lxfb_ops.c val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN | val 394 drivers/video/fbdev/geode/lxfb_ops.c write_dc(par, DC_GENLK_CTL, val); val 412 drivers/video/fbdev/geode/lxfb_ops.c val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE; val 413 drivers/video/fbdev/geode/lxfb_ops.c write_dc(par, DC_DV_CTL, val | dv); val 509 drivers/video/fbdev/geode/lxfb_ops.c int val; val 513 drivers/video/fbdev/geode/lxfb_ops.c val = (red << 8) & 0xff0000; val 514 drivers/video/fbdev/geode/lxfb_ops.c val |= (green) & 0x00ff00; val 515 drivers/video/fbdev/geode/lxfb_ops.c val |= (blue >> 8) & 0x0000ff; val 518 drivers/video/fbdev/geode/lxfb_ops.c write_dc(par, DC_PAL_DATA, val); val 178 drivers/video/fbdev/geode/video_gx.c unsigned long val; val 183 drivers/video/fbdev/geode/video_gx.c rdmsrl(MSR_GX_MSR_PADSEL, val); val 184 drivers/video/fbdev/geode/video_gx.c val &= ~MSR_GX_MSR_PADSEL_MASK; val 185 drivers/video/fbdev/geode/video_gx.c val |= MSR_GX_MSR_PADSEL_TFT; val 186 drivers/video/fbdev/geode/video_gx.c wrmsrl(MSR_GX_MSR_PADSEL, val); val 64 drivers/video/fbdev/goldfishfb.c static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) val 68 drivers/video/fbdev/goldfishfb.c return (val >> (16 - bf->length) & mask) << bf->offset; val 203 drivers/video/fbdev/grvga.c #define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16) val 142 drivers/video/fbdev/gxt4500.c #define writereg(par, reg, val) writel((val), (par)->regs + (reg)) val 527 drivers/video/fbdev/gxt4500.c u32 val = reg; val 530 drivers/video/fbdev/gxt4500.c val |= (reg << 11) | (reg << 5); val 533 drivers/video/fbdev/gxt4500.c val |= (reg << 10) | (reg << 5); val 536 drivers/video/fbdev/gxt4500.c val |= (reg << 24); val 539 drivers/video/fbdev/gxt4500.c val |= (reg << 16) | (reg << 8); val 542 drivers/video/fbdev/gxt4500.c pal[reg] = val; val 144 drivers/video/fbdev/hgafb.c static void write_hga_b(unsigned int val, unsigned char reg) val 147 drivers/video/fbdev/hgafb.c outb_p(val, HGA_VALUE_PORT); val 150 drivers/video/fbdev/hgafb.c static void write_hga_w(unsigned int val, unsigned char reg) val 152 drivers/video/fbdev/hgafb.c outb_p(reg, HGA_INDEX_PORT); outb_p(val >> 8, HGA_VALUE_PORT); val 153 drivers/video/fbdev/hgafb.c outb_p(reg+1, HGA_INDEX_PORT); outb_p(val & 0xff, HGA_VALUE_PORT); val 156 drivers/video/fbdev/hgafb.c static int test_hga_b(unsigned char val, unsigned char reg) val 159 drivers/video/fbdev/hgafb.c outb (val, HGA_VALUE_PORT); val 160 drivers/video/fbdev/hgafb.c udelay(20); val = (inb_p(HGA_VALUE_PORT) == val); val 161 drivers/video/fbdev/hgafb.c return val; val 95 drivers/video/fbdev/i740fb.c static inline void i740outb(struct i740fb_par *par, u16 port, u8 val) val 97 drivers/video/fbdev/i740fb.c vga_mm_w(par->regs, port, val); val 103 drivers/video/fbdev/i740fb.c static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val) val 105 drivers/video/fbdev/i740fb.c vga_mm_w_fast(par->regs, port, reg, val); val 113 drivers/video/fbdev/i740fb.c u8 val, u8 mask) val 115 drivers/video/fbdev/i740fb.c vga_mm_w_fast(par->regs, port, reg, (val & mask) val 124 drivers/video/fbdev/i740fb.c static void i740fb_ddc_setscl(void *data, int val) val 129 drivers/video/fbdev/i740fb.c i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL); val 132 drivers/video/fbdev/i740fb.c static void i740fb_ddc_setsda(void *data, int val) val 137 drivers/video/fbdev/i740fb.c i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA); val 294 drivers/video/fbdev/i810/i810.h #define i810_writeb(where, mmio, val) writeb(val, mmio + where) val 295 drivers/video/fbdev/i810/i810.h #define i810_writew(where, mmio, val) writew(val, mmio + where) val 296 drivers/video/fbdev/i810/i810.h #define i810_writel(where, mmio, val) writel(val, mmio + where) val 170 drivers/video/fbdev/i810/i810_main.c u8 val; val 173 drivers/video/fbdev/i810/i810_main.c val = i810_readb(SR_DATA, mmio); val 174 drivers/video/fbdev/i810/i810_main.c val = (mode == OFF) ? val | SCR_OFF : val 175 drivers/video/fbdev/i810/i810_main.c val & ~SCR_OFF; val 179 drivers/video/fbdev/i810/i810_main.c i810_writeb(SR_DATA, mmio, val); val 193 drivers/video/fbdev/i810/i810_main.c u8 val; val 195 drivers/video/fbdev/i810/i810_main.c val = i810_readb(DRAMCH, mmio); val 196 drivers/video/fbdev/i810/i810_main.c val &= DRAM_OFF; val 197 drivers/video/fbdev/i810/i810_main.c val = (mode == OFF) ? val : val | DRAM_ON; val 198 drivers/video/fbdev/i810/i810_main.c i810_writeb(DRAMCH, mmio, val); val 350 drivers/video/fbdev/i810/i810_main.c u8 val; val 353 drivers/video/fbdev/i810/i810_main.c val = i810_readb(CR_DATA_CGA, mmio); val 355 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, val | 1); val 370 drivers/video/fbdev/i810/i810_main.c u8 val; val 375 drivers/video/fbdev/i810/i810_main.c val = i810_readb(SR_DATA, mmio); val 376 drivers/video/fbdev/i810/i810_main.c val &= 0xE0; val 377 drivers/video/fbdev/i810/i810_main.c val |= 1 | 1 << 2; val 379 drivers/video/fbdev/i810/i810_main.c i810_writeb(SR_DATA, mmio, val); val 387 drivers/video/fbdev/i810/i810_main.c val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F; val 389 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val); val 413 drivers/video/fbdev/imsttfb.c static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val) val 416 drivers/video/fbdev/imsttfb.c out_le32(base + regindex, val); val 418 drivers/video/fbdev/imsttfb.c writel(val, base + regindex); val 262 drivers/video/fbdev/imxfb.c u_int val, ret = 1; val 264 drivers/video/fbdev/imxfb.c #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) val 266 drivers/video/fbdev/imxfb.c val = (CNVT_TOHW(red, 4) << 8) | val 270 drivers/video/fbdev/imxfb.c writel(val, fbi->regs + 0x800 + (regno << 2)); val 280 drivers/video/fbdev/imxfb.c unsigned int val; val 312 drivers/video/fbdev/imxfb.c val = chan_to_field(red, &info->var.red); val 313 drivers/video/fbdev/imxfb.c val |= chan_to_field(green, &info->var.green); val 314 drivers/video/fbdev/imxfb.c val |= chan_to_field(blue, &info->var.blue); val 316 drivers/video/fbdev/imxfb.c pal[regno] = val; val 58 drivers/video/fbdev/intelfb/intelfb_i2c.c u32 val; val 62 drivers/video/fbdev/intelfb/intelfb_i2c.c val = INREG(chan->reg); val 69 drivers/video/fbdev/intelfb/intelfb_i2c.c u32 val; val 73 drivers/video/fbdev/intelfb/intelfb_i2c.c val = INREG(chan->reg); val 80 drivers/video/fbdev/intelfb/intelfb_i2c.c u32 val; val 84 drivers/video/fbdev/intelfb/intelfb_i2c.c val = INREG(chan->reg); val 85 drivers/video/fbdev/intelfb/intelfb_i2c.c return ((val & SCL_VAL_IN) != 0); val 92 drivers/video/fbdev/intelfb/intelfb_i2c.c u32 val; val 96 drivers/video/fbdev/intelfb/intelfb_i2c.c val = INREG(chan->reg); val 97 drivers/video/fbdev/intelfb/intelfb_i2c.c return ((val & SDA_VAL_IN) != 0); val 526 drivers/video/fbdev/intelfb/intelfbhw.h #define OUTREG8(addr, val) writeb((val),(u8 __iomem *)(dinfo->mmio_base + \ val 528 drivers/video/fbdev/intelfb/intelfbhw.h #define OUTREG16(addr, val) writew((val),(u16 __iomem *)(dinfo->mmio_base + \ val 530 drivers/video/fbdev/intelfb/intelfbhw.h #define OUTREG(addr, val) writel((val),(u32 __iomem *)(dinfo->mmio_base + \ val 215 drivers/video/fbdev/leo.c u32 val; val 236 drivers/video/fbdev/leo.c val = sbus_readl(&par->lc_ss0_usr->csr); val 237 drivers/video/fbdev/leo.c } while (val & 0x20000000); val 279 drivers/video/fbdev/leo.c u32 val; val 300 drivers/video/fbdev/leo.c val = sbus_readl(&lx_krn->krn_csr); val 301 drivers/video/fbdev/leo.c val |= (LEO_KRN_CSR_UNK | LEO_KRN_CSR_UNK2); val 302 drivers/video/fbdev/leo.c sbus_writel(val, &lx_krn->krn_csr); val 319 drivers/video/fbdev/leo.c u32 val; val 325 drivers/video/fbdev/leo.c val = sbus_readl(&lx_krn->krn_csr); val 326 drivers/video/fbdev/leo.c val |= LEO_KRN_CSR_ENABLE; val 327 drivers/video/fbdev/leo.c sbus_writel(val, &lx_krn->krn_csr); val 335 drivers/video/fbdev/leo.c val = sbus_readl(&lx_krn->krn_csr); val 336 drivers/video/fbdev/leo.c val &= ~LEO_KRN_CSR_ENABLE; val 337 drivers/video/fbdev/leo.c sbus_writel(val, &lx_krn->krn_csr); val 454 drivers/video/fbdev/leo.c u32 val; val 479 drivers/video/fbdev/leo.c val = sbus_readl(&lx_krn->krn_csr); val 480 drivers/video/fbdev/leo.c val |= (LEO_KRN_CSR_UNK | LEO_KRN_CSR_UNK2); val 481 drivers/video/fbdev/leo.c sbus_writel(val, &lx_krn->krn_csr); val 512 drivers/video/fbdev/leo.c u32 val; val 514 drivers/video/fbdev/leo.c val = sbus_readl(&par->ld_ss1->ss1_misc); val 515 drivers/video/fbdev/leo.c val |= LEO_SS1_MISC_ENABLE; val 516 drivers/video/fbdev/leo.c sbus_writel(val, &par->ld_ss1->ss1_misc); val 51 drivers/video/fbdev/matrox/i2c-matroxfb.c static void matroxfb_set_gpio(struct matrox_fb_info* minfo, int mask, int val) { val 56 drivers/video/fbdev/matrox/i2c-matroxfb.c v = (matroxfb_DAC_in(minfo, DAC_XGENIOCTRL) & mask) | val; val 912 drivers/video/fbdev/matrox/matroxfb_base.c int val; val 921 drivers/video/fbdev/matrox/matroxfb_base.c val = -ENXIO; val 924 drivers/video/fbdev/matrox/matroxfb_base.c val = 0; val 926 drivers/video/fbdev/matrox/matroxfb_base.c val = -EINVAL; val 929 drivers/video/fbdev/matrox/matroxfb_base.c val = oproc->verifymode(minfo->outputs[mom.output].data, mom.mode); val 931 drivers/video/fbdev/matrox/matroxfb_base.c if (!val) { val 934 drivers/video/fbdev/matrox/matroxfb_base.c val = 1; val 938 drivers/video/fbdev/matrox/matroxfb_base.c if (val != 1) val 939 drivers/video/fbdev/matrox/matroxfb_base.c return val; val 962 drivers/video/fbdev/matrox/matroxfb_base.c int val; val 971 drivers/video/fbdev/matrox/matroxfb_base.c val = -ENXIO; val 974 drivers/video/fbdev/matrox/matroxfb_base.c val = 0; val 977 drivers/video/fbdev/matrox/matroxfb_base.c if (val) val 978 drivers/video/fbdev/matrox/matroxfb_base.c return val; val 116 drivers/video/fbdev/matrox/matroxfb_base.h #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) val 668 drivers/video/fbdev/matrox/matroxfb_base.h #define mga_outb(addr,val) mga_writeb(minfo->mmio.vbase, (addr), (val)) val 669 drivers/video/fbdev/matrox/matroxfb_base.h #define mga_outw(addr,val) mga_writew(minfo->mmio.vbase, (addr), (val)) val 670 drivers/video/fbdev/matrox/matroxfb_base.h #define mga_outl(addr,val) mga_writel(minfo->mmio.vbase, (addr), (val)) val 672 drivers/video/fbdev/matrox/matroxfb_base.h #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port)) val 694 drivers/video/fbdev/matrox/matroxfb_base.h int val); val 101 drivers/video/fbdev/matrox/matroxfb_g450.c int val; val 105 drivers/video/fbdev/matrox/matroxfb_g450.c val = matroxfb_DAC_in(minfo, 0x88); val 107 drivers/video/fbdev/matrox/matroxfb_g450.c return val; val 110 drivers/video/fbdev/matrox/matroxfb_g450.c static void cve2_set_reg(struct matrox_fb_info *minfo, int reg, int val) val 116 drivers/video/fbdev/matrox/matroxfb_g450.c matroxfb_DAC_out(minfo, 0x88, val); val 120 drivers/video/fbdev/matrox/matroxfb_g450.c static void cve2_set_reg10(struct matrox_fb_info *minfo, int reg, int val) val 126 drivers/video/fbdev/matrox/matroxfb_g450.c matroxfb_DAC_out(minfo, 0x88, val >> 2); val 128 drivers/video/fbdev/matrox/matroxfb_g450.c matroxfb_DAC_out(minfo, 0x88, val & 3); val 205 drivers/video/fbdev/matrox/matroxfb_g450.c unsigned char val = cve2_get_reg(minfo, 0x05); val 206 drivers/video/fbdev/matrox/matroxfb_g450.c if (p->value) val |= 0x02; val 207 drivers/video/fbdev/matrox/matroxfb_g450.c else val &= ~0x02; val 208 drivers/video/fbdev/matrox/matroxfb_g450.c cve2_set_reg(minfo, 0x05, val); val 163 drivers/video/fbdev/matrox/matroxfb_maven.c static int maven_set_reg(struct i2c_client* c, int reg, int val) { val 166 drivers/video/fbdev/matrox/matroxfb_maven.c err = i2c_smbus_write_byte_data(c, reg, val); val 172 drivers/video/fbdev/matrox/matroxfb_maven.c static int maven_set_reg_pair(struct i2c_client* c, int reg, int val) { val 175 drivers/video/fbdev/matrox/matroxfb_maven.c err = i2c_smbus_write_word_data(c, reg, val); val 526 drivers/video/fbdev/matrox/matroxfb_maven.c int val; val 672 drivers/video/fbdev/matrox/matroxfb_maven.c val = maven_get_reg(c, 0x8D); val 673 drivers/video/fbdev/matrox/matroxfb_maven.c val &= 0x14; /* 0x10 or anything ored with it */ val 674 drivers/video/fbdev/matrox/matroxfb_maven.c maven_set_reg(c, 0x8D, val); val 1118 drivers/video/fbdev/matrox/matroxfb_maven.c unsigned char val val 1120 drivers/video/fbdev/matrox/matroxfb_maven.c if (p->value) val |= 0x10; val 1121 drivers/video/fbdev/matrox/matroxfb_maven.c else val &= ~0x10; val 1122 drivers/video/fbdev/matrox/matroxfb_maven.c maven_set_reg(md->client, 0x8d, val); val 93 drivers/video/fbdev/matrox/matroxfb_misc.c void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val) val 97 drivers/video/fbdev/matrox/matroxfb_misc.c mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val); val 64 drivers/video/fbdev/maxinefb.c void maxinefb_ims332_write_register(int regno, register unsigned int val) val 70 drivers/video/fbdev/maxinefb.c *((volatile unsigned int *) (regs)) = (val >> 8) & 0xff00; val 71 drivers/video/fbdev/maxinefb.c *((volatile unsigned short *) (wptr)) = val; val 115 drivers/video/fbdev/mb862xx/mb862xxfb.h #define outreg(type, off, val) \ val 116 drivers/video/fbdev/mb862xx/mb862xxfb.h gdc_write((val), (par->type + (off))) val 82 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned int val; val 87 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c val = chan_to_field(red, &info->var.red); val 88 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c val |= chan_to_field(green, &info->var.green); val 89 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c val |= chan_to_field(blue, &info->var.blue); val 90 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c par->pseudo_palette[regno] = val; val 95 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c val = (red >> 8) << 16; val 96 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c val |= (green >> 8) << 8; val 97 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c val |= blue >> 8; val 98 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0PAL0 + (regno * 4), val); val 38 drivers/video/fbdev/mbx/mbxfb.c #define write_reg(val, reg) do { writel((val), (reg)); } while(0) val 44 drivers/video/fbdev/mbx/mbxfb.c #define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0) val 168 drivers/video/fbdev/mbx/mbxfb.c u32 val, ret = 1; val 173 drivers/video/fbdev/mbx/mbxfb.c val = (red & 0xf800) | ((green & 0xfc00) >> 5) | val 175 drivers/video/fbdev/mbx/mbxfb.c pal[regno] = val; val 652 drivers/video/fbdev/mbx/mbxfb.c tmp |= reg.val & reg.mask; val 663 drivers/video/fbdev/mbx/mbxfb.c reg.val = readl(virt_base_2700 + reg.addr); val 318 drivers/video/fbdev/mmp/fb/mmpfb.c u32 val; val 321 drivers/video/fbdev/mmp/fb/mmpfb.c val = chan_to_field(red, &info->var.red); val 322 drivers/video/fbdev/mmp/fb/mmpfb.c val |= chan_to_field(green, &info->var.green); val 323 drivers/video/fbdev/mmp/fb/mmpfb.c val |= chan_to_field(blue , &info->var.blue); val 324 drivers/video/fbdev/mmp/fb/mmpfb.c fbi->pseudo_palette[regno] = val; val 328 drivers/video/fbdev/mmp/fb/mmpfb.c val = to_rgb(red, green, blue); val 51 drivers/video/fbdev/mmp/hw/mmp_ctrl.c csc_en = 0, val = 0, val 80 drivers/video/fbdev/mmp/hw/mmp_ctrl.c val = 0x1; val 84 drivers/video/fbdev/mmp/hw/mmp_ctrl.c val = 0x2; val 88 drivers/video/fbdev/mmp/hw/mmp_ctrl.c val = 0x3; val 92 drivers/video/fbdev/mmp/hw/mmp_ctrl.c val = 0x4; val 97 drivers/video/fbdev/mmp/hw/mmp_ctrl.c val = 0x5; val 102 drivers/video/fbdev/mmp/hw/mmp_ctrl.c val = 0x6; val 107 drivers/video/fbdev/mmp/hw/mmp_ctrl.c val = 0x7; val 114 drivers/video/fbdev/mmp/hw/mmp_ctrl.c return (dma_palette(0) | dma_fmt(vid, val) | val 480 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define dma_palette(val) ((val ? 1 : 0) << 28) val 481 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define dma_fmt(vid, val) ((val & 0xf) << ((vid) ? 20 : 16)) val 482 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define dma_swaprb(vid, val) ((val ? 1 : 0) << ((vid) ? 4 : 12)) val 483 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define dma_swapuv(vid, val) ((val ? 1 : 0) << ((vid) ? 3 : 11)) val 484 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define dma_swapyuv(vid, val) ((val ? 1 : 0) << ((vid) ? 2 : 10)) val 485 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define dma_csc(vid, val) ((val ? 1 : 0) << ((vid) ? 1 : 9)) val 486 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define dma_hsmooth(vid, val) ((val ? 1 : 0) << ((vid) ? 6 : 14)) val 1030 drivers/video/fbdev/mx3fb.c u32 val; val 1052 drivers/video/fbdev/mx3fb.c val = chan_to_field(red, &fbi->var.red); val 1053 drivers/video/fbdev/mx3fb.c val |= chan_to_field(green, &fbi->var.green); val 1054 drivers/video/fbdev/mx3fb.c val |= chan_to_field(blue, &fbi->var.blue); val 1056 drivers/video/fbdev/mx3fb.c pal[regno] = val; val 145 drivers/video/fbdev/neofb.c static inline void write_le32(int regindex, u32 val, const struct neofb_par *par) val 147 drivers/video/fbdev/neofb.c writel(val, par->neo2200 + par->cursorOff + regindex); val 32 drivers/video/fbdev/nvidia/nv_i2c.c u32 val; val 34 drivers/video/fbdev/nvidia/nv_i2c.c val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; val 37 drivers/video/fbdev/nvidia/nv_i2c.c val |= 0x20; val 39 drivers/video/fbdev/nvidia/nv_i2c.c val &= ~0x20; val 41 drivers/video/fbdev/nvidia/nv_i2c.c NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); val 48 drivers/video/fbdev/nvidia/nv_i2c.c u32 val; val 50 drivers/video/fbdev/nvidia/nv_i2c.c val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; val 53 drivers/video/fbdev/nvidia/nv_i2c.c val |= 0x10; val 55 drivers/video/fbdev/nvidia/nv_i2c.c val &= ~0x10; val 57 drivers/video/fbdev/nvidia/nv_i2c.c NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); val 64 drivers/video/fbdev/nvidia/nv_i2c.c u32 val = 0; val 67 drivers/video/fbdev/nvidia/nv_i2c.c val = 1; val 69 drivers/video/fbdev/nvidia/nv_i2c.c return val; val 76 drivers/video/fbdev/nvidia/nv_i2c.c u32 val = 0; val 79 drivers/video/fbdev/nvidia/nv_i2c.c val = 1; val 81 drivers/video/fbdev/nvidia/nv_i2c.c return val; val 57 drivers/video/fbdev/omap2/omapfb/displays/panel-lgphilips-lb035q02.c static int lb035q02_write_reg(struct spi_device *spi, u8 reg, u16 val) val 80 drivers/video/fbdev/omap2/omapfb/displays/panel-lgphilips-lb035q02.c buffer[5] = val >> 8; val 81 drivers/video/fbdev/omap2/omapfb/displays/panel-lgphilips-lb035q02.c buffer[6] = val; val 196 drivers/video/fbdev/omap2/omapfb/displays/panel-sharp-ls037v7dw01.c static int sharp_ls_get_gpio_of(struct device *dev, int index, int val, val 119 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c u8 i, val; val 122 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c for (val = i = 0; i < 4; i++) val 123 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c val |= (gamma[i] & 0x300) >> ((i + 1) * 2); val 124 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c tpo_td043_write(spi, 0x11, val); val 126 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c for (val = i = 0; i < 4; i++) val 127 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c val |= (gamma[i+4] & 0x300) >> ((i + 1) * 2); val 128 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c tpo_td043_write(spi, 0x12, val); val 130 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c for (val = i = 0; i < 4; i++) val 131 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c val |= (gamma[i+8] & 0x300) >> ((i + 1) * 2); val 132 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c tpo_td043_write(spi, 0x13, val); val 135 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c for (val = i = 0; i < 12; i++) val 179 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c int val; val 182 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c ret = kstrtoint(buf, 0, &val); val 186 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c val = !!val; val 188 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c ret = tpo_td043_write_mirror(ddata->spi, ddata->hmirror, val); val 192 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c ddata->vmirror = val; val 209 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c long val; val 212 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c ret = kstrtol(buf, 0, &val); val 213 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c if (ret != 0 || val & ~7) val 216 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c ddata->mode = val; val 218 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c val |= TPO_R02_NCLK_RISING; val 219 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c tpo_td043_write(ddata->spi, 2, val); val 51 drivers/video/fbdev/omap2/omapfb/dss/dispc.c #define REG_FLD_MOD(idx, val, start, end) \ val 52 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) val 251 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static inline void dispc_write_reg(const u16 idx, u32 val) val 253 drivers/video/fbdev/omap2/omapfb/dss/dispc.c __raw_writel(val, dispc.base + idx); val 268 drivers/video/fbdev/omap2/omapfb/dss/dispc.c enum mgr_reg_fields regfld, int val) { val 276 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); val 748 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 753 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); val 755 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_POSITION(plane), val); val 761 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); val 764 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_SIZE(plane), val); val 766 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); val 772 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 776 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); val 779 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); val 781 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_SIZE(plane), val); val 932 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 949 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); val 982 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_MOD(val, chan, shift, shift); val 983 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_MOD(val, chan2, 31, 30); val 985 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_MOD(val, channel, shift, shift); val 987 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); val 994 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 1010 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); val 1012 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (FLD_GET(val, shift, shift) == 1) val 1018 drivers/video/fbdev/omap2/omapfb/dss/dispc.c switch (FLD_GET(val, 31, 30)) { val 1111 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 1115 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); val 1116 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_MOD(val, enable, 9, 9); val 1117 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); val 1136 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 1138 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | val 1141 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_SIZE_MGR(channel), val); val 1406 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 1415 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(vinc, vinc_start, vinc_end) | val 1418 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_FIR(plane), val); val 1420 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); val 1421 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_FIR2(plane), val); val 1427 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 1433 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(vaccu, vert_start, vert_end) | val 1436 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_ACCU0(plane), val); val 1441 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 1447 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(vaccu, vert_start, vert_end) | val 1450 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_ACCU1(plane), val); val 1456 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 1458 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); val 1459 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); val 1465 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 val; val 1467 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); val 1468 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); val 2147 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u64 val, blank; val 2171 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); val 2173 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val, max(0, ds - 2) * width); val 2174 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (val < max(0, ds - 2) * width) val 2182 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = div_u64((u64)nonactive * lclk, pclk); val 2184 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val, max(0, ds - 1) * width); val 2185 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (val < max(0, ds - 1) * width) val 3231 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 mask, val; val 3234 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = (rf << 0) | (ipc << 3) | (onoff << 6); val 3237 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val <<= 16 + shifts[channel]; val 3240 drivers/video/fbdev/omap2/omapfb/dss/dispc.c mask, val); val 113 drivers/video/fbdev/omap2/omapfb/dss/dsi.c #define REG_FLD_MOD(dsidev, idx, val, start, end) \ val 114 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) val 432 drivers/video/fbdev/omap2/omapfb/dss/dsi.c const struct dsi_reg idx, u32 val) val 444 drivers/video/fbdev/omap2/omapfb/dss/dsi.c __raw_writel(val, base + idx.idx); val 1766 drivers/video/fbdev/omap2/omapfb/dss/dsi.c int val; val 1775 drivers/video/fbdev/omap2/omapfb/dss/dsi.c val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ val 1777 drivers/video/fbdev/omap2/omapfb/dss/dsi.c switch (val) { val 2507 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u32 val; val 2508 drivers/video/fbdev/omap2/omapfb/dss/dsi.c val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); val 2510 drivers/video/fbdev/omap2/omapfb/dss/dsi.c (val >> 0) & 0xff, val 2511 drivers/video/fbdev/omap2/omapfb/dss/dsi.c (val >> 8) & 0xff, val 2512 drivers/video/fbdev/omap2/omapfb/dss/dsi.c (val >> 16) & 0xff, val 2513 drivers/video/fbdev/omap2/omapfb/dss/dsi.c (val >> 24) & 0xff); val 2559 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u32 val; val 2561 drivers/video/fbdev/omap2/omapfb/dss/dsi.c val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); val 2562 drivers/video/fbdev/omap2/omapfb/dss/dsi.c DSSERR("\trawval %#08x\n", val); val 2563 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dt = FLD_GET(val, 5, 0); val 2565 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u16 err = FLD_GET(val, 23, 8); val 2569 drivers/video/fbdev/omap2/omapfb/dss/dsi.c FLD_GET(val, 23, 8)); val 2572 drivers/video/fbdev/omap2/omapfb/dss/dsi.c FLD_GET(val, 23, 8)); val 2575 drivers/video/fbdev/omap2/omapfb/dss/dsi.c FLD_GET(val, 23, 8)); val 2655 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u32 val; val 2662 drivers/video/fbdev/omap2/omapfb/dss/dsi.c val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | val 2665 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); val 2671 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u32 val; val 2673 drivers/video/fbdev/omap2/omapfb/dss/dsi.c val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; val 2678 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); val 2934 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u32 val; val 2945 drivers/video/fbdev/omap2/omapfb/dss/dsi.c val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); val 2947 drivers/video/fbdev/omap2/omapfb/dss/dsi.c DSSDBG("\theader: %08x\n", val); val 2948 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dt = FLD_GET(val, 5, 0); val 2950 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u16 err = FLD_GET(val, 23, 8); val 2958 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u8 data = FLD_GET(val, 15, 8); val 2975 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u16 data = FLD_GET(val, 23, 8); val 2994 drivers/video/fbdev/omap2/omapfb/dss/dsi.c int len = FLD_GET(val, 23, 8); val 3008 drivers/video/fbdev/omap2/omapfb/dss/dsi.c val = dsi_read_reg(dsidev, val 3012 drivers/video/fbdev/omap2/omapfb/dss/dsi.c (val >> 0) & 0xff, val 3013 drivers/video/fbdev/omap2/omapfb/dss/dsi.c (val >> 8) & 0xff, val 3014 drivers/video/fbdev/omap2/omapfb/dss/dsi.c (val >> 16) & 0xff, val 3015 drivers/video/fbdev/omap2/omapfb/dss/dsi.c (val >> 24) & 0xff); val 3019 drivers/video/fbdev/omap2/omapfb/dss/dsi.c buf[w] = (val >> (b * 8)) & 0xff; val 58 drivers/video/fbdev/omap2/omapfb/dss/dss.c #define REG_FLD_MOD(idx, val, start, end) \ val 59 drivers/video/fbdev/omap2/omapfb/dss/dss.c dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) val 113 drivers/video/fbdev/omap2/omapfb/dss/dss.c static inline void dss_write_reg(const struct dss_reg idx, u32 val) val 115 drivers/video/fbdev/omap2/omapfb/dss/dss.c __raw_writel(val, dss.base + idx.idx); val 169 drivers/video/fbdev/omap2/omapfb/dss/dss.c unsigned val; val 174 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = !enable; val 192 drivers/video/fbdev/omap2/omapfb/dss/dss.c 1 << shift, val << shift); val 198 drivers/video/fbdev/omap2/omapfb/dss/dss.c unsigned shift, val; val 209 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 0; break; val 211 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 1; break; val 223 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 0; break; val 225 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 1; break; val 227 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 2; break; val 239 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 1; break; val 241 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 0; break; val 243 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 2; break; val 256 drivers/video/fbdev/omap2/omapfb/dss/dss.c 0x3 << shift, val << shift); val 662 drivers/video/fbdev/omap2/omapfb/dss/dss.c int val; val 666 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 0; val 669 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 1; val 675 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, val, 17, 17); val 682 drivers/video/fbdev/omap2/omapfb/dss/dss.c int val; val 686 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 1; val 689 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 2; val 692 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 3; val 695 drivers/video/fbdev/omap2/omapfb/dss/dss.c val = 0; val 701 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, val, 17, 16); val 60 drivers/video/fbdev/omap2/omapfb/dss/dss.h #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) val 61 drivers/video/fbdev/omap2/omapfb/dss/dss.h #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) val 62 drivers/video/fbdev/omap2/omapfb/dss/dss.h #define FLD_MOD(orig, val, start, end) \ val 63 drivers/video/fbdev/omap2/omapfb/dss/dss.h (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) val 248 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h u32 val) val 250 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h __raw_writel(val, base_addr + idx); val 258 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h #define REG_FLD_MOD(base, idx, val, start, end) \ val 260 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h val, start, end)) val 265 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h const u32 idx, int b2, int b1, u32 val) val 268 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h while (val != (v = REG_GET(base_addr, idx, b2, b1))) { val 284 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); val 285 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); val 638 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c u8 val; val 669 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c val = 1; val 671 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c val = 0; val 674 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); val 675 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); val 676 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); val 677 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); val 680 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c val = 1; val 681 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); val 682 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); val 690 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA; val 691 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); val 694 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c val = (cfg->iec60958_cfg->status[0] & val 696 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); val 703 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6; val 704 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); val 707 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE; val 708 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); val 68 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val) val 71 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) val 75 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); val 78 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) val 79 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c != val) { val 80 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c DSSERR("Failed to set PHY power mode to %d\n", val); val 88 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val) val 91 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); val 94 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) val 95 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c != val) { val 301 drivers/video/fbdev/omap2/omapfb/dss/venc.c static inline void venc_write_reg(int idx, u32 val) val 303 drivers/video/fbdev/omap2/omapfb/dss/venc.c __raw_writel(val, venc.base + idx); val 27 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c #define REG_MOD(reg, val, start, end) \ val 28 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg) val 71 drivers/video/fbdev/omap2/omapfb/vrfb.c static void omap2_sms_write_rot_control(u32 val, unsigned ctx) val 73 drivers/video/fbdev/omap2/omapfb/vrfb.c __raw_writel(val, vrfb_base + SMS_ROT_CONTROL(ctx)); val 76 drivers/video/fbdev/omap2/omapfb/vrfb.c static void omap2_sms_write_rot_size(u32 val, unsigned ctx) val 78 drivers/video/fbdev/omap2/omapfb/vrfb.c __raw_writel(val, vrfb_base + SMS_ROT_SIZE(ctx)); val 81 drivers/video/fbdev/omap2/omapfb/vrfb.c static void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx) val 83 drivers/video/fbdev/omap2/omapfb/vrfb.c __raw_writel(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx)); val 187 drivers/video/fbdev/p9100.c u32 val; val 193 drivers/video/fbdev/p9100.c val = sbus_readl(®s->vid_screenpaint_timectl1); val 194 drivers/video/fbdev/p9100.c val |= SCREENPAINT_TIMECTL1_ENABLE_VIDEO; val 195 drivers/video/fbdev/p9100.c sbus_writel(val, ®s->vid_screenpaint_timectl1); val 203 drivers/video/fbdev/p9100.c val = sbus_readl(®s->vid_screenpaint_timectl1); val 204 drivers/video/fbdev/p9100.c val &= ~SCREENPAINT_TIMECTL1_ENABLE_VIDEO; val 205 drivers/video/fbdev/p9100.c sbus_writel(val, ®s->vid_screenpaint_timectl1); val 906 drivers/video/fbdev/pm2fb.c #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16) val 1105 drivers/video/fbdev/pm3fb.c #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) val 144 drivers/video/fbdev/pmag-aa-fb.c u8 val = blank ? 0x00 : 0x0f; val 146 drivers/video/fbdev/pmag-aa-fb.c bt455_write_cmap_entry(par->bt455, 1, val); val 778 drivers/video/fbdev/ps3fb.c u32 val; val 812 drivers/video/fbdev/ps3fb.c if (copy_from_user(&val, argp, sizeof(val))) val 815 drivers/video/fbdev/ps3fb.c if (!(val & PS3AV_MODE_MASK)) { val 818 drivers/video/fbdev/ps3fb.c val = (val & ~PS3AV_MODE_MASK) | id; val 820 drivers/video/fbdev/ps3fb.c dev_dbg(info->device, "PS3FB_IOCTL_SETMODE:%x\n", val); val 822 drivers/video/fbdev/ps3fb.c vmode = ps3fb_vmode(val); val 830 drivers/video/fbdev/ps3fb.c par->new_mode_id = val; val 839 drivers/video/fbdev/ps3fb.c val = ps3av_get_mode(); val 840 drivers/video/fbdev/ps3fb.c dev_dbg(info->device, "PS3FB_IOCTL_GETMODE:%x\n", val); val 841 drivers/video/fbdev/ps3fb.c if (!copy_to_user(argp, &val, sizeof(val))) val 873 drivers/video/fbdev/ps3fb.c if (copy_from_user(&val, argp, sizeof(val))) val 876 drivers/video/fbdev/ps3fb.c dev_dbg(info->device, "PS3FB_IOCTL_FSEL:%d\n", val); val 878 drivers/video/fbdev/ps3fb.c retval = ps3fb_sync(info, val); val 115 drivers/video/fbdev/pvr2fb.c struct pvr2_params { unsigned int val; char *name; }; val 238 drivers/video/fbdev/pvr2fb.c unsigned int val) val 240 drivers/video/fbdev/pvr2fb.c fb_writel(val, par->mmio_base + 0x1000 + (4 * regno)); val 732 drivers/video/fbdev/pvr2fb.c return p[i].val; val 738 drivers/video/fbdev/pvr2fb.c static char *pvr2_get_param_name(const struct pvr2_params *p, int val, val 744 drivers/video/fbdev/pvr2fb.c if (p[i].val == val) val 493 drivers/video/fbdev/pxa168fb.c u32 val; val 500 drivers/video/fbdev/pxa168fb.c val = chan_to_field(red, &info->var.red); val 501 drivers/video/fbdev/pxa168fb.c val |= chan_to_field(green, &info->var.green); val 502 drivers/video/fbdev/pxa168fb.c val |= chan_to_field(blue , &info->var.blue); val 503 drivers/video/fbdev/pxa168fb.c fbi->pseudo_palette[regno] = val; val 507 drivers/video/fbdev/pxa168fb.c val = to_rgb(red, green, blue); val 508 drivers/video/fbdev/pxa168fb.c writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT); val 111 drivers/video/fbdev/pxa3xx-gcu.c gc_writel(struct pxa3xx_gcu_priv *priv, unsigned int off, unsigned long val) val 113 drivers/video/fbdev/pxa3xx-gcu.c __raw_writel(val, priv->mmio_base + off); val 102 drivers/video/fbdev/pxafb.c lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val) val 104 drivers/video/fbdev/pxafb.c __raw_writel(val, fbi->mmio_base + off); val 146 drivers/video/fbdev/pxafb.c u_int val; val 158 drivers/video/fbdev/pxafb.c val = ((red >> 0) & 0xf800); val 159 drivers/video/fbdev/pxafb.c val |= ((green >> 5) & 0x07e0); val 160 drivers/video/fbdev/pxafb.c val |= ((blue >> 11) & 0x001f); val 161 drivers/video/fbdev/pxafb.c fbi->palette_cpu[regno] = val; val 164 drivers/video/fbdev/pxafb.c val = ((red << 8) & 0x00f80000); val 165 drivers/video/fbdev/pxafb.c val |= ((green >> 0) & 0x0000fc00); val 166 drivers/video/fbdev/pxafb.c val |= ((blue >> 8) & 0x000000f8); val 167 drivers/video/fbdev/pxafb.c ((u32 *)(fbi->palette_cpu))[regno] = val; val 170 drivers/video/fbdev/pxafb.c val = ((red << 8) & 0x00fc0000); val 171 drivers/video/fbdev/pxafb.c val |= ((green >> 0) & 0x0000fc00); val 172 drivers/video/fbdev/pxafb.c val |= ((blue >> 8) & 0x000000fc); val 173 drivers/video/fbdev/pxafb.c ((u32 *)(fbi->palette_cpu))[regno] = val; val 176 drivers/video/fbdev/pxafb.c val = ((red << 8) & 0x00ff0000); val 177 drivers/video/fbdev/pxafb.c val |= ((green >> 0) & 0x0000ff00); val 178 drivers/video/fbdev/pxafb.c val |= ((blue >> 8) & 0x000000ff); val 179 drivers/video/fbdev/pxafb.c ((u32 *)(fbi->palette_cpu))[regno] = val; val 191 drivers/video/fbdev/pxafb.c unsigned int val; val 223 drivers/video/fbdev/pxafb.c val = chan_to_field(red, &fbi->fb.var.red); val 224 drivers/video/fbdev/pxafb.c val |= chan_to_field(green, &fbi->fb.var.green); val 225 drivers/video/fbdev/pxafb.c val |= chan_to_field(blue, &fbi->fb.var.blue); val 227 drivers/video/fbdev/pxafb.c pal[regno] = val; val 1657 drivers/video/fbdev/pxafb.c pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) val 1663 drivers/video/fbdev/pxafb.c switch (val) { val 389 drivers/video/fbdev/riva/fbdev.c unsigned char val) val 392 drivers/video/fbdev/riva/fbdev.c VGA_WR08(par->riva.PCIO, 0x3d5, val); val 403 drivers/video/fbdev/riva/fbdev.c unsigned char val) val 406 drivers/video/fbdev/riva/fbdev.c VGA_WR08(par->riva.PVIO, 0x3cf, val); val 417 drivers/video/fbdev/riva/fbdev.c unsigned char val) val 420 drivers/video/fbdev/riva/fbdev.c VGA_WR08(par->riva.PVIO, 0x3c5, val); val 431 drivers/video/fbdev/riva/fbdev.c unsigned char val) val 434 drivers/video/fbdev/riva/fbdev.c VGA_WR08(par->riva.PCIO, 0x3c0, val); val 444 drivers/video/fbdev/riva/fbdev.c static inline void MISCout(struct riva_par *par, unsigned char val) val 446 drivers/video/fbdev/riva/fbdev.c VGA_WR08(par->riva.PVIO, 0x3c2, val); val 31 drivers/video/fbdev/riva/rivafb-i2c.c u32 val; val 34 drivers/video/fbdev/riva/rivafb-i2c.c val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; val 37 drivers/video/fbdev/riva/rivafb-i2c.c val |= 0x20; val 39 drivers/video/fbdev/riva/rivafb-i2c.c val &= ~0x20; val 42 drivers/video/fbdev/riva/rivafb-i2c.c VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); val 49 drivers/video/fbdev/riva/rivafb-i2c.c u32 val; val 52 drivers/video/fbdev/riva/rivafb-i2c.c val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; val 55 drivers/video/fbdev/riva/rivafb-i2c.c val |= 0x10; val 57 drivers/video/fbdev/riva/rivafb-i2c.c val &= ~0x10; val 60 drivers/video/fbdev/riva/rivafb-i2c.c VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); val 67 drivers/video/fbdev/riva/rivafb-i2c.c u32 val = 0; val 71 drivers/video/fbdev/riva/rivafb-i2c.c val = 1; val 73 drivers/video/fbdev/riva/rivafb-i2c.c return val; val 80 drivers/video/fbdev/riva/rivafb-i2c.c u32 val = 0; val 84 drivers/video/fbdev/riva/rivafb-i2c.c val = 1; val 86 drivers/video/fbdev/riva/rivafb-i2c.c return val; val 202 drivers/video/fbdev/s1d13xxxfb.c unsigned int val; val 207 drivers/video/fbdev/s1d13xxxfb.c val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */ val 209 drivers/video/fbdev/s1d13xxxfb.c val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */ val 211 drivers/video/fbdev/s1d13xxxfb.c val &= ~0x07; val 217 drivers/video/fbdev/s1d13xxxfb.c val |= 2; val 222 drivers/video/fbdev/s1d13xxxfb.c val |= 3; val 227 drivers/video/fbdev/s1d13xxxfb.c val |= 5; val 235 drivers/video/fbdev/s1d13xxxfb.c dbg("writing %02x to display mode register\n", val); val 238 drivers/video/fbdev/s1d13xxxfb.c s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val); val 240 drivers/video/fbdev/s1d13xxxfb.c s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val); val 745 drivers/video/fbdev/s3c-fb.c unsigned int val; val 759 drivers/video/fbdev/s3c-fb.c val = chan_to_field(red, &info->var.red); val 760 drivers/video/fbdev/s3c-fb.c val |= chan_to_field(green, &info->var.green); val 761 drivers/video/fbdev/s3c-fb.c val |= chan_to_field(blue, &info->var.blue); val 763 drivers/video/fbdev/s3c-fb.c pal[regno] = val; val 769 drivers/video/fbdev/s3c-fb.c val = chan_to_field(red, &win->palette.r); val 770 drivers/video/fbdev/s3c-fb.c val |= chan_to_field(green, &win->palette.g); val 771 drivers/video/fbdev/s3c-fb.c val |= chan_to_field(blue, &win->palette.b); val 773 drivers/video/fbdev/s3c-fb.c s3c_fb_update_palette(sfb, win, regno, val); val 455 drivers/video/fbdev/s3c2410fb.c unsigned int regno, unsigned int val) val 463 drivers/video/fbdev/s3c2410fb.c fbi->palette_buffer[regno] = val; val 492 drivers/video/fbdev/s3c2410fb.c unsigned int val; val 504 drivers/video/fbdev/s3c2410fb.c val = chan_to_field(red, &info->var.red); val 505 drivers/video/fbdev/s3c2410fb.c val |= chan_to_field(green, &info->var.green); val 506 drivers/video/fbdev/s3c2410fb.c val |= chan_to_field(blue, &info->var.blue); val 508 drivers/video/fbdev/s3c2410fb.c pal[regno] = val; val 516 drivers/video/fbdev/s3c2410fb.c val = (red >> 0) & 0xf800; val 517 drivers/video/fbdev/s3c2410fb.c val |= (green >> 5) & 0x07e0; val 518 drivers/video/fbdev/s3c2410fb.c val |= (blue >> 11) & 0x001f; val 520 drivers/video/fbdev/s3c2410fb.c writel(val, regs + S3C2410_TFTPAL(regno)); val 521 drivers/video/fbdev/s3c2410fb.c schedule_palette_update(fbi, regno, val); val 773 drivers/video/fbdev/s3c2410fb.c unsigned long val, void *data) val 785 drivers/video/fbdev/s3c2410fb.c if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) || val 786 drivers/video/fbdev/s3c2410fb.c (val == CPUFREQ_PRECHANGE && delta_f < 0)) { val 199 drivers/video/fbdev/s3fb.c static void s3fb_ddc_write(struct s3fb_info *par, u8 val) val 202 drivers/video/fbdev/s3fb.c writeb(val, par->mmio + DDC_MMIO_REG); val 204 drivers/video/fbdev/s3fb.c vga_wcrt(par->state.vgabase, DDC_REG, val); val 207 drivers/video/fbdev/s3fb.c static void s3fb_ddc_setscl(void *data, int val) val 213 drivers/video/fbdev/s3fb.c if (val) val 220 drivers/video/fbdev/s3fb.c static void s3fb_ddc_setsda(void *data, int val) val 226 drivers/video/fbdev/s3fb.c if (val) val 354 drivers/video/fbdev/s3fb.c u32 val; val 365 drivers/video/fbdev/s3fb.c val = *(src++) * 0x01010101; val 366 drivers/video/fbdev/s3fb.c val = (val & fg) | (~val & bg); val 367 drivers/video/fbdev/s3fb.c fb_writel(val, dst++); val 411 drivers/video/fbdev/s3fb.c u32 val; val 422 drivers/video/fbdev/s3fb.c val = expand_pixel(*(src++)); val 423 drivers/video/fbdev/s3fb.c val = (val & fg) | (~val & bg); val 424 drivers/video/fbdev/s3fb.c fb_writel(val, dst++); val 274 drivers/video/fbdev/sa1100fb.c u_int val, ret = 1; val 277 drivers/video/fbdev/sa1100fb.c val = ((red >> 4) & 0xf00); val 278 drivers/video/fbdev/sa1100fb.c val |= ((green >> 8) & 0x0f0); val 279 drivers/video/fbdev/sa1100fb.c val |= ((blue >> 12) & 0x00f); val 282 drivers/video/fbdev/sa1100fb.c val |= palette_pbs(&fbi->fb.var); val 284 drivers/video/fbdev/sa1100fb.c fbi->palette_cpu[regno] = val; val 296 drivers/video/fbdev/sa1100fb.c unsigned int val; val 326 drivers/video/fbdev/sa1100fb.c val = chan_to_field(red, &fbi->fb.var.red); val 327 drivers/video/fbdev/sa1100fb.c val |= chan_to_field(green, &fbi->fb.var.green); val 328 drivers/video/fbdev/sa1100fb.c val |= chan_to_field(blue, &fbi->fb.var.blue); val 330 drivers/video/fbdev/sa1100fb.c fbi->pseudo_palette[regno] = val; val 989 drivers/video/fbdev/sa1100fb.c sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val, val 995 drivers/video/fbdev/sa1100fb.c switch (val) { val 45 drivers/video/fbdev/savage/savagefb-i2c.c static void savage4_gpio_setscl(void *data, int val) val 51 drivers/video/fbdev/savage/savagefb-i2c.c if(val) val 59 drivers/video/fbdev/savage/savagefb-i2c.c static void savage4_gpio_setsda(void *data, int val) val 65 drivers/video/fbdev/savage/savagefb-i2c.c if(val) val 87 drivers/video/fbdev/savage/savagefb-i2c.c static void prosavage_gpio_setscl(void* data, int val) val 94 drivers/video/fbdev/savage/savagefb-i2c.c if (val) { val 103 drivers/video/fbdev/savage/savagefb-i2c.c static void prosavage_gpio_setsda(void* data, int val) val 110 drivers/video/fbdev/savage/savagefb-i2c.c if (val) { val 269 drivers/video/fbdev/savage/savagefb.h static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par) val 271 drivers/video/fbdev/savage/savagefb.h writeb(val, par->mmio.vbase + addr); val 274 drivers/video/fbdev/savage/savagefb.h static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par) val 276 drivers/video/fbdev/savage/savagefb.h writew(val, par->mmio.vbase + addr); val 279 drivers/video/fbdev/savage/savagefb.h static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par) val 281 drivers/video/fbdev/savage/savagefb.h writel(val, par->mmio.vbase + addr); val 299 drivers/video/fbdev/savage/savagefb.h static inline void vga_out8(int addr, u8 val, struct savagefb_par *par) val 301 drivers/video/fbdev/savage/savagefb.h savage_out8(0x8000 + addr, val, par); val 304 drivers/video/fbdev/savage/savagefb.h static inline void vga_out16(int addr, u16 val, struct savagefb_par *par) val 306 drivers/video/fbdev/savage/savagefb.h savage_out16(0x8000 + addr, val, par); val 309 drivers/video/fbdev/savage/savagefb.h static inline void vga_out32(int addr, u32 val, struct savagefb_par *par) val 311 drivers/video/fbdev/savage/savagefb.h savage_out32(0x8000 + addr, val, par); val 332 drivers/video/fbdev/savage/savagefb.h static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par) val 335 drivers/video/fbdev/savage/savagefb.h vga_out8(0x3d5, val, par); val 338 drivers/video/fbdev/savage/savagefb.h static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par) val 341 drivers/video/fbdev/savage/savagefb.h vga_out8(0x3cf, val, par); val 344 drivers/video/fbdev/savage/savagefb.h static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par) val 347 drivers/video/fbdev/savage/savagefb.h vga_out8 (0x3c5, val, par); val 1683 drivers/video/fbdev/savage/savagefb_driver.c unsigned char val; val 1687 drivers/video/fbdev/savage/savagefb_driver.c val = vga_in8(0x3c3, par); val 1688 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c3, val | 0x01, par); val 1689 drivers/video/fbdev/savage/savagefb_driver.c val = vga_in8(0x3cc, par); val 1690 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c2, val | 0x01, par); val 1694 drivers/video/fbdev/savage/savagefb_driver.c val = vga_in8(0x3d5, par); val 1695 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, val | 1, par); val 1702 drivers/video/fbdev/savage/savagefb_driver.c unsigned char val; val 1708 drivers/video/fbdev/savage/savagefb_driver.c val = vga_in8(0x3d5, par); val 1709 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, val | 1, par); val 57 drivers/video/fbdev/sh7760fb.c static int wait_for_lps(struct sh7760fb_par *par, int val) val 60 drivers/video/fbdev/sh7760fb.c while (--i && ((ioread16(par->base + LDPMMR) & 3) != val)) val 3326 drivers/video/fbdev/sis/init.c #define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to)) val 412 drivers/video/fbdev/sis/init301.c static void SiS_SetCH70xx(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val); val 9101 drivers/video/fbdev/sis/init301.c SiS_SetChReg(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val, unsigned short myor) val 9115 drivers/video/fbdev/sis/init301.c temp = SiS_WriteDDC2Data(SiS_Pr, val); /* Write data */ val 9126 drivers/video/fbdev/sis/init301.c SiS_SetCH700x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val) val 9139 drivers/video/fbdev/sis/init301.c if( (!(SiS_SetChReg(SiS_Pr, reg, val, 0x80))) && val 9146 drivers/video/fbdev/sis/init301.c SiS_SetChReg(SiS_Pr, reg, val, 0x80); val 9153 drivers/video/fbdev/sis/init301.c SiS_SetCH701x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val) val 9160 drivers/video/fbdev/sis/init301.c SiS_SetChReg(SiS_Pr, reg, val, 0); val 9165 drivers/video/fbdev/sis/init301.c SiS_SetCH70xx(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val) val 9168 drivers/video/fbdev/sis/init301.c SiS_SetCH700x(SiS_Pr, reg, val); val 9170 drivers/video/fbdev/sis/init301.c SiS_SetCH701x(SiS_Pr, reg, val); val 90 drivers/video/fbdev/sis/init301.h void SiS_SetCH700x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val); val 92 drivers/video/fbdev/sis/init301.h void SiS_SetCH701x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val); val 382 drivers/video/fbdev/sis/sis.h unsigned int val); val 386 drivers/video/fbdev/sis/sis.h unsigned char val); val 396 drivers/video/fbdev/sis/sis.h #define MMIO_OUT8(base, offset, val) writeb(((u8)(val)), (base+offset)) val 397 drivers/video/fbdev/sis/sis.h #define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset)) val 398 drivers/video/fbdev/sis/sis.h #define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset)) val 667 drivers/video/fbdev/sis/sis.h void sisfb_write_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg, unsigned int val); val 671 drivers/video/fbdev/sis/sis.h void sisfb_write_nbridge_pci_byte(struct SiS_Private *SiS_Pr, int reg, unsigned char val); val 92 drivers/video/fbdev/sis/sis_main.c static void sisfb_set_TVxposoffset(struct sis_video_info *ivideo, int val); val 93 drivers/video/fbdev/sis/sis_main.c static void sisfb_set_TVyposoffset(struct sis_video_info *ivideo, int val); val 1030 drivers/video/fbdev/sis/sis_main.c u32 val = 0; val 1032 drivers/video/fbdev/sis/sis_main.c pci_read_config_dword(ivideo->nbridge, reg, &val); val 1033 drivers/video/fbdev/sis/sis_main.c return (unsigned int)val; val 1037 drivers/video/fbdev/sis/sis_main.c sisfb_write_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg, unsigned int val) val 1041 drivers/video/fbdev/sis/sis_main.c pci_write_config_dword(ivideo->nbridge, reg, (u32)val); val 1048 drivers/video/fbdev/sis/sis_main.c u32 val = 0; val 1052 drivers/video/fbdev/sis/sis_main.c pci_read_config_dword(ivideo->lpcdev, reg, &val); val 1053 drivers/video/fbdev/sis/sis_main.c return (unsigned int)val; val 1059 drivers/video/fbdev/sis/sis_main.c sisfb_write_nbridge_pci_byte(struct SiS_Private *SiS_Pr, int reg, unsigned char val) val 1063 drivers/video/fbdev/sis/sis_main.c pci_write_config_byte(ivideo->nbridge, reg, (u8)val); val 1070 drivers/video/fbdev/sis/sis_main.c u16 val = 0; val 1074 drivers/video/fbdev/sis/sis_main.c pci_read_config_word(ivideo->lpcdev, reg, &val); val 1075 drivers/video/fbdev/sis/sis_main.c return (unsigned int)val; val 3704 drivers/video/fbdev/sis/sis_main.c sisfb_set_TVxposoffset(struct sis_video_info *ivideo, int val) val 3706 drivers/video/fbdev/sis/sis_main.c if(val > 32) val = 32; val 3707 drivers/video/fbdev/sis/sis_main.c if(val < -32) val = -32; val 3708 drivers/video/fbdev/sis/sis_main.c ivideo->tvxpos = val; val 3721 drivers/video/fbdev/sis/sis_main.c x += val; val 3744 drivers/video/fbdev/sis/sis_main.c temp += (val * 2); val 3747 drivers/video/fbdev/sis/sis_main.c p2_2b = ((p2_2b & 0x0f) + (val * 2)) & 0x0f; val 3749 drivers/video/fbdev/sis/sis_main.c temp += (val * 2); val 3762 drivers/video/fbdev/sis/sis_main.c sisfb_set_TVyposoffset(struct sis_video_info *ivideo, int val) val 3764 drivers/video/fbdev/sis/sis_main.c if(val > 32) val = 32; val 3765 drivers/video/fbdev/sis/sis_main.c if(val < -32) val = -32; val 3766 drivers/video/fbdev/sis/sis_main.c ivideo->tvypos = val; val 3779 drivers/video/fbdev/sis/sis_main.c y -= val; val 3793 drivers/video/fbdev/sis/sis_main.c val /= 2; val 3797 drivers/video/fbdev/sis/sis_main.c p2_01 += val; val 3798 drivers/video/fbdev/sis/sis_main.c p2_02 += val; val 362 drivers/video/fbdev/skeletonfb.c #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) val 918 drivers/video/fbdev/sm501fb.c unsigned int val; val 932 drivers/video/fbdev/sm501fb.c val = chan_to_field(red, &info->var.red); val 933 drivers/video/fbdev/sm501fb.c val |= chan_to_field(green, &info->var.green); val 934 drivers/video/fbdev/sm501fb.c val |= chan_to_field(blue, &info->var.blue); val 936 drivers/video/fbdev/sm501fb.c pal[regno] = val; val 942 drivers/video/fbdev/sm501fb.c val = (red >> 8) << 16; val 943 drivers/video/fbdev/sm501fb.c val |= (green >> 8) << 8; val 944 drivers/video/fbdev/sm501fb.c val |= blue >> 8; val 946 drivers/video/fbdev/sm501fb.c smc501_writel(val, base + (regno * 4)); val 42 drivers/video/fbdev/sm712.h static inline void smtc_crtcw(int reg, int val) val 45 drivers/video/fbdev/sm712.h smtc_mmiowb(val, 0x3d5); val 48 drivers/video/fbdev/sm712.h static inline void smtc_grphw(int reg, int val) val 51 drivers/video/fbdev/sm712.h smtc_mmiowb(val, 0x3cf); val 54 drivers/video/fbdev/sm712.h static inline void smtc_attrw(int reg, int val) val 59 drivers/video/fbdev/sm712.h smtc_mmiowb(val, 0x3c0); val 62 drivers/video/fbdev/sm712.h static inline void smtc_seqw(int reg, int val) val 65 drivers/video/fbdev/sm712.h smtc_mmiowb(val, 0x3c5); val 96 drivers/video/fbdev/sm712.h #define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \ val 106 drivers/video/fbdev/sm712.h #define pal_rgb(r, g, b, val) val val 976 drivers/video/fbdev/sm712fb.c u32 val; val 994 drivers/video/fbdev/sm712fb.c val = chan_to_field(red, &sfb->fb->var.red); val 995 drivers/video/fbdev/sm712fb.c val |= chan_to_field(green, &sfb->fb->var.green); val 996 drivers/video/fbdev/sm712fb.c val |= chan_to_field(blue, &sfb->fb->var.blue); val 997 drivers/video/fbdev/sm712fb.c pal[regno] = pal_rgb(red, green, blue, val); val 1001 drivers/video/fbdev/sm712fb.c val = chan_to_field(red, &sfb->fb->var.red); val 1002 drivers/video/fbdev/sm712fb.c val |= chan_to_field(green, &sfb->fb->var.green); val 1003 drivers/video/fbdev/sm712fb.c val |= chan_to_field(blue, &sfb->fb->var.blue); val 1004 drivers/video/fbdev/sm712fb.c pal[regno] = big_swap(val); val 444 drivers/video/fbdev/ssd1307fb.c u8 val = par->lookup_table[i]; val 446 drivers/video/fbdev/ssd1307fb.c if (val < 31 || val > 63) val 449 drivers/video/fbdev/ssd1307fb.c i, val); val 450 drivers/video/fbdev/ssd1307fb.c ret = ssd1307fb_write_cmd(par->client, val); val 128 drivers/video/fbdev/sstfb.c static void sst_dbg_print_read_reg(u32 reg, u32 val) { val 141 drivers/video/fbdev/sstfb.c r_ddprintk("sst_read(%#x): %#x\n", reg, val); val 143 drivers/video/fbdev/sstfb.c r_dprintk(" sst_read(%s): %#x\n", regname, val); val 146 drivers/video/fbdev/sstfb.c static void sst_dbg_print_write_reg(u32 reg, u32 val) { val 159 drivers/video/fbdev/sstfb.c r_ddprintk("sst_write(%#x, %#x)\n", reg, val); val 161 drivers/video/fbdev/sstfb.c r_dprintk(" sst_write(%s, %#x)\n", regname, val); val 164 drivers/video/fbdev/sstfb.c # define sst_dbg_print_read_reg(reg, val) do {} while(0) val 165 drivers/video/fbdev/sstfb.c # define sst_dbg_print_write_reg(reg, val) do {} while(0) val 174 drivers/video/fbdev/sstfb.c #define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val) val 175 drivers/video/fbdev/sstfb.c #define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val) val 176 drivers/video/fbdev/sstfb.c #define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val) val 178 drivers/video/fbdev/sstfb.c #define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val) val 180 drivers/video/fbdev/sstfb.c #define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val) val 189 drivers/video/fbdev/sstfb.c static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val) val 191 drivers/video/fbdev/sstfb.c sst_dbg_print_write_reg(reg, val); val 192 drivers/video/fbdev/sstfb.c writel(val, vbase + reg); val 195 drivers/video/fbdev/sstfb.c static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val) val 197 drivers/video/fbdev/sstfb.c r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val); val 198 drivers/video/fbdev/sstfb.c __sst_write(vbase, reg, __sst_read(vbase, reg) | val); val 201 drivers/video/fbdev/sstfb.c static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val) val 203 drivers/video/fbdev/sstfb.c r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val); val 204 drivers/video/fbdev/sstfb.c __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val); val 255 drivers/video/fbdev/sstfb.c static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val) val 257 drivers/video/fbdev/sstfb.c r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val); val 259 drivers/video/fbdev/sstfb.c __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val); val 273 drivers/video/fbdev/sstfb.c static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val) val 275 drivers/video/fbdev/sstfb.c r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val); val 277 drivers/video/fbdev/sstfb.c __sst_dac_write(vbase, DACREG_DATA_I, val); val 723 drivers/video/fbdev/sstfb.c int val; val 725 drivers/video/fbdev/sstfb.c val = simple_strtoul(buf, last, 0); val 726 drivers/video/fbdev/sstfb.c sstfb_setvgapass(info, val); val 747 drivers/video/fbdev/sstfb.c u32 val; val 752 drivers/video/fbdev/sstfb.c if (copy_from_user(&val, (void __user *)arg, sizeof(val))) val 754 drivers/video/fbdev/sstfb.c sstfb_setvgapass(info, val); val 758 drivers/video/fbdev/sstfb.c val = par->vgapass; val 759 drivers/video/fbdev/sstfb.c if (copy_to_user((void __user *)arg, &val, sizeof(val))) val 391 drivers/video/fbdev/stifb.c #define NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb, val) \ val 392 drivers/video/fbdev/stifb.c WRITE_WORD(val, fb, REG_14) val 394 drivers/video/fbdev/stifb.c #define NGLE_QUICK_SET_DST_BM_ACCESS(fb, val) \ val 395 drivers/video/fbdev/stifb.c WRITE_WORD(val, fb, REG_11) val 397 drivers/video/fbdev/stifb.c #define NGLE_QUICK_SET_CTL_PLN_REG(fb, val) \ val 398 drivers/video/fbdev/stifb.c WRITE_WORD(val, fb, REG_12) val 406 drivers/video/fbdev/stifb.c #define NGLE_SET_TRANSFERDATA(fb, val) \ val 407 drivers/video/fbdev/stifb.c WRITE_WORD(val, fb, REG_8) val 409 drivers/video/fbdev/stifb.c #define NGLE_SET_DSTXY(fb, val) \ val 410 drivers/video/fbdev/stifb.c WRITE_WORD(val, fb, REG_6) val 98 drivers/video/fbdev/sunxvr500.c static void e3d_clut_write(struct e3d_info *ep, int index, u32 val) val 106 drivers/video/fbdev/sunxvr500.c writel(val, ramdac + RAMDAC_DATA); val 208 drivers/video/fbdev/tcx.c u32 val; val 212 drivers/video/fbdev/tcx.c val = sbus_readl(&thc->thc_misc); val 216 drivers/video/fbdev/tcx.c val &= ~(TCX_THC_MISC_VSYNC_DIS | val 218 drivers/video/fbdev/tcx.c val |= TCX_THC_MISC_VIDEO; val 223 drivers/video/fbdev/tcx.c val &= ~TCX_THC_MISC_VIDEO; val 228 drivers/video/fbdev/tcx.c val |= TCX_THC_MISC_VSYNC_DIS; val 231 drivers/video/fbdev/tcx.c val |= TCX_THC_MISC_HSYNC_DIS; val 238 drivers/video/fbdev/tcx.c sbus_writel(val, &thc->thc_misc); val 164 drivers/video/fbdev/tdfxfb.c static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) val 166 drivers/video/fbdev/tdfxfb.c outb(val, par->iobase + reg - 0x300); val 169 drivers/video/fbdev/tdfxfb.c static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) val 173 drivers/video/fbdev/tdfxfb.c vga_outb(par, GRA_D, val); val 177 drivers/video/fbdev/tdfxfb.c static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) val 181 drivers/video/fbdev/tdfxfb.c vga_outb(par, SEQ_D, val); val 192 drivers/video/fbdev/tdfxfb.c static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) val 196 drivers/video/fbdev/tdfxfb.c vga_outb(par, CRT_D, val); val 207 drivers/video/fbdev/tdfxfb.c static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val) val 213 drivers/video/fbdev/tdfxfb.c vga_outb(par, ATT_IW, val); val 248 drivers/video/fbdev/tdfxfb.c static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val) val 250 drivers/video/fbdev/tdfxfb.c writel(val, par->regbase_virt + reg); val 738 drivers/video/fbdev/tdfxfb.c #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) val 1168 drivers/video/fbdev/tdfxfb.c static void tdfxfb_i2c_setscl(void *data, int val) val 1175 drivers/video/fbdev/tdfxfb.c if (val) val 1183 drivers/video/fbdev/tdfxfb.c static void tdfxfb_i2c_setsda(void *data, int val) val 1190 drivers/video/fbdev/tdfxfb.c if (val) val 1218 drivers/video/fbdev/tdfxfb.c static void tdfxfb_ddc_setscl(void *data, int val) val 1225 drivers/video/fbdev/tdfxfb.c if (val) val 1233 drivers/video/fbdev/tdfxfb.c static void tdfxfb_ddc_setsda(void *data, int val) val 1240 drivers/video/fbdev/tdfxfb.c if (val) val 164 drivers/video/fbdev/tridentfb.c static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) val 166 drivers/video/fbdev/tridentfb.c fb_writeb(val, p->io_virt + reg); val 190 drivers/video/fbdev/tridentfb.c static void tridentfb_ddc_setscl_tgui(void *data, int val) val 195 drivers/video/fbdev/tridentfb.c if (val) val 203 drivers/video/fbdev/tridentfb.c static void tridentfb_ddc_setsda_tgui(void *data, int val) val 208 drivers/video/fbdev/tridentfb.c if (val) val 229 drivers/video/fbdev/tridentfb.c static void tridentfb_ddc_setscl(void *data, int val) val 235 drivers/video/fbdev/tridentfb.c if (val) val 242 drivers/video/fbdev/tridentfb.c static void tridentfb_ddc_setsda(void *data, int val) val 248 drivers/video/fbdev/tridentfb.c if (!val) val 701 drivers/video/fbdev/tridentfb.c unsigned char val) val 703 drivers/video/fbdev/tridentfb.c vga_mm_wcrt(par->io_virt, reg, val); val 713 drivers/video/fbdev/tridentfb.c unsigned char val) val 716 drivers/video/fbdev/tridentfb.c vga_mm_wattr(par->io_virt, reg, val); val 720 drivers/video/fbdev/tridentfb.c unsigned char val) val 722 drivers/video/fbdev/tridentfb.c vga_mm_wgfx(par->io_virt, reg, val); val 90 drivers/video/fbdev/udlfb.c static char *dlfb_set_register(char *buf, u8 reg, u8 val) val 95 drivers/video/fbdev/udlfb.c *buf++ = val; val 35 drivers/video/fbdev/uvesafb.c .val = CN_VAL_V86D_UVESAFB val 1943 drivers/video/fbdev/uvesafb.c static int param_set_scroll(const char *val, const struct kernel_param *kp) val 1947 drivers/video/fbdev/uvesafb.c if (!strcmp(val, "redraw")) val 1949 drivers/video/fbdev/uvesafb.c else if (!strcmp(val, "ypan")) val 1951 drivers/video/fbdev/uvesafb.c else if (!strcmp(val, "ywrap")) val 308 drivers/video/fbdev/vfb.c #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) val 639 drivers/video/fbdev/vga16fb.c int val; val 643 drivers/video/fbdev/vga16fb.c val = map[red>>14] | ((map[green>>14]) << 1) | ((map[blue>>14]) << 2); val 645 drivers/video/fbdev/vga16fb.c vga_io_wattr(regno, val); val 25 drivers/video/fbdev/via/via_i2c.c u8 val; val 30 drivers/video/fbdev/via/via_i2c.c val = via_read_reg(adap_data->io_port, adap_data->ioport_index) & 0xF0; val 32 drivers/video/fbdev/via/via_i2c.c val |= 0x20; val 34 drivers/video/fbdev/via/via_i2c.c val &= ~0x20; val 37 drivers/video/fbdev/via/via_i2c.c val |= 0x01; val 40 drivers/video/fbdev/via/via_i2c.c val |= 0x82; val 45 drivers/video/fbdev/via/via_i2c.c via_write_reg(adap_data->io_port, adap_data->ioport_index, val); val 83 drivers/video/fbdev/via/via_i2c.c u8 val; val 88 drivers/video/fbdev/via/via_i2c.c val = via_read_reg(adap_data->io_port, adap_data->ioport_index) & 0xF0; val 90 drivers/video/fbdev/via/via_i2c.c val |= 0x10; val 92 drivers/video/fbdev/via/via_i2c.c val &= ~0x10; val 95 drivers/video/fbdev/via/via_i2c.c val |= 0x01; val 98 drivers/video/fbdev/via/via_i2c.c val |= 0x42; val 103 drivers/video/fbdev/via/via_i2c.c via_write_reg(adap_data->io_port, adap_data->ioport_index, val); val 144 drivers/video/fbdev/vt8500lcdfb.c unsigned int val; val 157 drivers/video/fbdev/vt8500lcdfb.c val = chan_to_field(red, &fbi->fb.var.red); val 158 drivers/video/fbdev/vt8500lcdfb.c val |= chan_to_field(green, &fbi->fb.var.green); val 159 drivers/video/fbdev/vt8500lcdfb.c val |= chan_to_field(blue, &fbi->fb.var.blue); val 161 drivers/video/fbdev/vt8500lcdfb.c pal[regno] = val; val 148 drivers/video/fbdev/vt8623fb.c u32 val; val 159 drivers/video/fbdev/vt8623fb.c val = *(src++) * 0x01010101; val 160 drivers/video/fbdev/vt8623fb.c val = (val & fg) | (~val & bg); val 161 drivers/video/fbdev/vt8623fb.c fb_writel(val, dst++); val 204 drivers/video/fbdev/vt8623fb.c u32 val; val 215 drivers/video/fbdev/vt8623fb.c val = expand_pixel(*(src++)); val 216 drivers/video/fbdev/vt8623fb.c val = (val & fg) | (~val & bg); val 217 drivers/video/fbdev/vt8623fb.c fb_writel(val, dst++); val 205 drivers/video/fbdev/w100fb.c unsigned int val; val 222 drivers/video/fbdev/w100fb.c val = (red & 0xf800) | ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); val 223 drivers/video/fbdev/w100fb.c pal[regno] = val; val 269 drivers/video/fbdev/w100fb.c status.val = readl(remapped_regs + mmRBBM_STATUS); val 284 drivers/video/fbdev/w100fb.c status.val = readl(remapped_regs + mmRBBM_STATUS); val 313 drivers/video/fbdev/w100fb.c dp_cntl.val = 0; val 320 drivers/video/fbdev/w100fb.c writel(dp_cntl.val, remapped_regs + mmDP_CNTL); val 322 drivers/video/fbdev/w100fb.c gmc.val = 0; val 337 drivers/video/fbdev/w100fb.c writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); val 339 drivers/video/fbdev/w100fb.c dp_datatype.val = dp_mix.val = 0; val 346 drivers/video/fbdev/w100fb.c writel(dp_datatype.val, remapped_regs + mmDP_DATATYPE); val 352 drivers/video/fbdev/w100fb.c writel(dp_mix.val, remapped_regs + mmDP_MIX); val 368 drivers/video/fbdev/w100fb.c gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL); val 372 drivers/video/fbdev/w100fb.c writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); val 396 drivers/video/fbdev/w100fb.c gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL); val 400 drivers/video/fbdev/w100fb.c writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); val 812 drivers/video/fbdev/w100fb.c u16 val = readw((u16 *) remapped_base + cfgSTATUS); val 813 drivers/video/fbdev/w100fb.c writew(val | 0x08, (u16 *) remapped_base + cfgSTATUS); val 827 drivers/video/fbdev/w100fb.c writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL); val 838 drivers/video/fbdev/w100fb.c writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL); val 890 drivers/video/fbdev/w100fb.c cif_io.val = defCIF_IO; val 891 drivers/video/fbdev/w100fb.c writel((u32)(cif_io.val), remapped_regs + mmCIF_IO); val 893 drivers/video/fbdev/w100fb.c cif_write_dbg.val = readl(remapped_regs + mmCIF_WRITE_DBG); val 897 drivers/video/fbdev/w100fb.c writel((u32) (cif_write_dbg.val), remapped_regs + mmCIF_WRITE_DBG); val 899 drivers/video/fbdev/w100fb.c cif_read_dbg.val = readl(remapped_regs + mmCIF_READ_DBG); val 901 drivers/video/fbdev/w100fb.c writel((u32) (cif_read_dbg.val), remapped_regs + mmCIF_READ_DBG); val 903 drivers/video/fbdev/w100fb.c cif_cntl.val = readl(remapped_regs + mmCIF_CNTL); val 909 drivers/video/fbdev/w100fb.c writel((u32) (cif_cntl.val), remapped_regs + mmCIF_CNTL); val 912 drivers/video/fbdev/w100fb.c intf_cntl.val = defINTF_CNTL; val 917 drivers/video/fbdev/w100fb.c writeb((u8) (intf_cntl.val), remapped_base + cfgINTF_CNTL); val 919 drivers/video/fbdev/w100fb.c cpu_default.val = defCPU_DEFAULTS; val 924 drivers/video/fbdev/w100fb.c writeb((u8) (cpu_default.val), remapped_base + cfgCPU_DEFAULTS); val 929 drivers/video/fbdev/w100fb.c cfgreg_base.val = defCFGREG_BASE; val 931 drivers/video/fbdev/w100fb.c writel((u32) (cfgreg_base.val), remapped_regs + mmCFGREG_BASE); val 933 drivers/video/fbdev/w100fb.c wrap_start_dir.val = defWRAP_START_DIR; val 935 drivers/video/fbdev/w100fb.c writel((u32) (wrap_start_dir.val), remapped_regs + mmWRAP_START_DIR); val 937 drivers/video/fbdev/w100fb.c wrap_top_dir.val = defWRAP_TOP_DIR; val 939 drivers/video/fbdev/w100fb.c writel((u32) (wrap_top_dir.val), remapped_regs + mmWRAP_TOP_DIR); val 1041 drivers/video/fbdev/w100fb.c writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL); val 1044 drivers/video/fbdev/w100fb.c writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL); val 1048 drivers/video/fbdev/w100fb.c writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL); val 1054 drivers/video/fbdev/w100fb.c clk_test_cntl.val = readl(remapped_regs + mmCLK_TEST_CNTL); val 1056 drivers/video/fbdev/w100fb.c writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL); val 1083 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); val 1089 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); val 1129 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); val 1135 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); val 1139 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); val 1157 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); val 1162 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); val 1168 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV); val 1171 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); val 1179 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); val 1208 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.clk_pin_cntl.val), remapped_regs + mmCLK_PIN_CNTL); val 1228 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); val 1233 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL); val 1240 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV); val 1260 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); val 1271 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); val 1290 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); val 1306 drivers/video/fbdev/w100fb.c active_h_disp.val = 0; val 1309 drivers/video/fbdev/w100fb.c writel(active_h_disp.val, remapped_regs + mmACTIVE_H_DISP); val 1311 drivers/video/fbdev/w100fb.c active_v_disp.val = 0; val 1314 drivers/video/fbdev/w100fb.c writel(active_v_disp.val, remapped_regs + mmACTIVE_V_DISP); val 1316 drivers/video/fbdev/w100fb.c graphic_h_disp.val = 0; val 1319 drivers/video/fbdev/w100fb.c writel(graphic_h_disp.val, remapped_regs + mmGRAPHIC_H_DISP); val 1321 drivers/video/fbdev/w100fb.c graphic_v_disp.val = 0; val 1324 drivers/video/fbdev/w100fb.c writel(graphic_v_disp.val, remapped_regs + mmGRAPHIC_V_DISP); val 1326 drivers/video/fbdev/w100fb.c crtc_total.val = 0; val 1329 drivers/video/fbdev/w100fb.c writel(crtc_total.val, remapped_regs + mmCRTC_TOTAL); val 1373 drivers/video/fbdev/w100fb.c writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION); val 1379 drivers/video/fbdev/w100fb.c writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION); val 1384 drivers/video/fbdev/w100fb.c writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION); val 1389 drivers/video/fbdev/w100fb.c writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION); val 1436 drivers/video/fbdev/w100fb.c graphic_ctrl.val = 0; /* w32xx doesn't like undefined bits */ val 1493 drivers/video/fbdev/w100fb.c writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL); val 1495 drivers/video/fbdev/w100fb.c writel(graphic_ctrl.val, remapped_regs + mmGRAPHIC_CTRL); val 1518 drivers/video/fbdev/w100fb.c crtc_ss.val = readl(remapped_regs + mmCRTC_SS); val 1519 drivers/video/fbdev/w100fb.c if (crtc_ss.val) val 1527 drivers/video/fbdev/w100fb.c u32 val; val 1532 drivers/video/fbdev/w100fb.c val = readl(remapped_regs + mmMEM_EXT_TIMING_CNTL); val 1533 drivers/video/fbdev/w100fb.c val &= ~(0x00100000); /* bit20=0 */ val 1534 drivers/video/fbdev/w100fb.c val |= 0xFF000000; /* bit31:24=0xff */ val 1535 drivers/video/fbdev/w100fb.c writel(val, remapped_regs + mmMEM_EXT_TIMING_CNTL); val 1537 drivers/video/fbdev/w100fb.c val = readl(remapped_regs + mmMEM_EXT_CNTL); val 1538 drivers/video/fbdev/w100fb.c val &= ~(0x00040000); /* bit18=0 */ val 1539 drivers/video/fbdev/w100fb.c val |= 0x00080000; /* bit19=1 */ val 1540 drivers/video/fbdev/w100fb.c writel(val, remapped_regs + mmMEM_EXT_CNTL); val 1546 drivers/video/fbdev/w100fb.c val = readl(remapped_regs + mmMEM_EXT_CNTL); val 1547 drivers/video/fbdev/w100fb.c val |= 0x40000000; /* bit30=1 */ val 1548 drivers/video/fbdev/w100fb.c writel(val, remapped_regs + mmMEM_EXT_CNTL); val 1551 drivers/video/fbdev/w100fb.c val = readl(remapped_regs + mmMEM_EXT_CNTL); val 1552 drivers/video/fbdev/w100fb.c val &= ~(0x00000001); /* bit0=0 */ val 1553 drivers/video/fbdev/w100fb.c writel(val, remapped_regs + mmMEM_EXT_CNTL); val 1561 drivers/video/fbdev/w100fb.c val = readl(remapped_regs + mmPLL_CNTL); val 1562 drivers/video/fbdev/w100fb.c val |= 0x00000004; /* bit2=1 */ val 1563 drivers/video/fbdev/w100fb.c writel(val, remapped_regs + mmPLL_CNTL); val 1571 drivers/video/fbdev/w100fb.c val = readl(remapped_regs + mmMEM_EXT_CNTL); val 1572 drivers/video/fbdev/w100fb.c val |= 0xF0000000; val 1573 drivers/video/fbdev/w100fb.c val &= ~(0x00000001); val 1574 drivers/video/fbdev/w100fb.c writel(val, remapped_regs + mmMEM_EXT_CNTL); val 247 drivers/video/fbdev/w100fb.h u32 val : 32; val 257 drivers/video/fbdev/w100fb.h u32 val : 32; val 286 drivers/video/fbdev/w100fb.h u32 val : 32; val 296 drivers/video/fbdev/w100fb.h u32 val : 32; val 317 drivers/video/fbdev/w100fb.h u32 val : 32; val 349 drivers/video/fbdev/w100fb.h u32 val : 32; val 382 drivers/video/fbdev/w100fb.h u32 val : 32; val 399 drivers/video/fbdev/w100fb.h unsigned char val : 8; val 415 drivers/video/fbdev/w100fb.h unsigned char val : 8; val 427 drivers/video/fbdev/w100fb.h u32 val : 32; val 443 drivers/video/fbdev/w100fb.h u32 val : 32; val 455 drivers/video/fbdev/w100fb.h u32 val : 32; val 467 drivers/video/fbdev/w100fb.h u32 val : 32; val 479 drivers/video/fbdev/w100fb.h u32 val : 32; val 491 drivers/video/fbdev/w100fb.h u32 val : 32; val 528 drivers/video/fbdev/w100fb.h u32 val : 32; val 556 drivers/video/fbdev/w100fb.h u32 val : 32; val 568 drivers/video/fbdev/w100fb.h u32 val : 32; val 580 drivers/video/fbdev/w100fb.h u32 val : 32; val 592 drivers/video/fbdev/w100fb.h u32 val : 32; val 604 drivers/video/fbdev/w100fb.h u32 val : 32; val 621 drivers/video/fbdev/w100fb.h u32 val : 32; val 631 drivers/video/fbdev/w100fb.h u32 val : 32; val 641 drivers/video/fbdev/w100fb.h u32 val : 32; val 656 drivers/video/fbdev/w100fb.h u32 val : 32; val 672 drivers/video/fbdev/w100fb.h u32 val : 32; val 698 drivers/video/fbdev/w100fb.h u32 val : 32; val 726 drivers/video/fbdev/w100fb.h u32 val : 32; val 740 drivers/video/fbdev/w100fb.h u32 val : 32; val 761 drivers/video/fbdev/w100fb.h u32 val : 32; val 779 drivers/video/fbdev/w100fb.h u32 val : 32; val 814 drivers/video/fbdev/w100fb.h u32 val : 32; val 843 drivers/video/fbdev/w100fb.h u32 val : 32; val 860 drivers/video/fbdev/w100fb.h u32 val : 32; val 875 drivers/video/fbdev/w100fb.h u32 val : 32; val 892 drivers/video/fbdev/w100fb.h u32 val : 32; val 907 drivers/video/fbdev/w100fb.h u32 val : 32; val 919 drivers/video/fbdev/w100fb.h u32 val : 32; val 197 drivers/video/fbdev/wm8505fb.c unsigned int val; val 210 drivers/video/fbdev/wm8505fb.c val = chan_to_field(red, &fbi->fb.var.red); val 211 drivers/video/fbdev/wm8505fb.c val |= chan_to_field(green, &fbi->fb.var.green); val 212 drivers/video/fbdev/wm8505fb.c val |= chan_to_field(blue, &fbi->fb.var.blue); val 214 drivers/video/fbdev/wm8505fb.c pal[regno] = val; val 223 drivers/video/fbdev/xen-fbfront.c #define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16) val 370 drivers/video/fbdev/xen-fbfront.c int val; val 380 drivers/video/fbdev/xen-fbfront.c if (xenbus_scanf(XBT_NIL, dev->otherend, "videoram", "%d", &val) == 1) { val 381 drivers/video/fbdev/xen-fbfront.c if (val < video[KPARAM_MEM]) val 382 drivers/video/fbdev/xen-fbfront.c video[KPARAM_MEM] = val; val 168 drivers/video/fbdev/xilinxfb.c u32 val) val 172 drivers/video/fbdev/xilinxfb.c iowrite32(val, drvdata->regs + (offset << 2)); val 174 drivers/video/fbdev/xilinxfb.c iowrite32be(val, drvdata->regs + (offset << 2)); val 178 drivers/video/fbdev/xilinxfb.c dcr_write(drvdata->dcr_host, offset, val); val 59 drivers/video/of_display_timing.c u32 val = 0; val 75 drivers/video/of_display_timing.c if (!of_property_read_u32(np, "vsync-active", &val)) val 76 drivers/video/of_display_timing.c dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH : val 78 drivers/video/of_display_timing.c if (!of_property_read_u32(np, "hsync-active", &val)) val 79 drivers/video/of_display_timing.c dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH : val 81 drivers/video/of_display_timing.c if (!of_property_read_u32(np, "de-active", &val)) val 82 drivers/video/of_display_timing.c dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH : val 84 drivers/video/of_display_timing.c if (!of_property_read_u32(np, "pixelclk-active", &val)) val 85 drivers/video/of_display_timing.c dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE : val 88 drivers/video/of_display_timing.c if (!of_property_read_u32(np, "syncclk-active", &val)) val 89 drivers/video/of_display_timing.c dt->flags |= val ? DISPLAY_FLAGS_SYNC_POSEDGE : val 42 drivers/video/vgastate.c unsigned char reg, unsigned char val) val 45 drivers/video/vgastate.c vga_w(regbase, iobase + 0x5, val); val 272 drivers/virtio/virtio_balloon.c u16 tag, u64 val) val 276 drivers/virtio/virtio_balloon.c vb->stats[idx].val = cpu_to_virtio64(vb->vdev, val); val 58 drivers/virtio/virtio_pci_modern.c static void vp_iowrite64_twopart(u64 val, val 61 drivers/virtio/virtio_pci_modern.c vp_iowrite32((u32)val, lo); val 62 drivers/virtio/virtio_pci_modern.c vp_iowrite32(val >> 32, hi); val 165 drivers/visorbus/visorchipset.c int val, err; val 168 drivers/visorbus/visorchipset.c if (kstrtoint(buf, 10, &val)) val 170 drivers/visorbus/visorchipset.c efi_visor_indication.boot_to_tool = val; val 129 drivers/vlynq/vlynq.c u32 val; val 133 drivers/vlynq/vlynq.c val = readl(&dev->remote->int_device[virq >> 2]); val 134 drivers/vlynq/vlynq.c val |= (VINT_ENABLE | virq) << VINT_OFFSET(virq); val 135 drivers/vlynq/vlynq.c writel(val, &dev->remote->int_device[virq >> 2]); val 142 drivers/vlynq/vlynq.c u32 val; val 146 drivers/vlynq/vlynq.c val = readl(&dev->remote->int_device[virq >> 2]); val 147 drivers/vlynq/vlynq.c val &= ~(VINT_ENABLE << VINT_OFFSET(virq)); val 148 drivers/vlynq/vlynq.c writel(val, &dev->remote->int_device[virq >> 2]); val 155 drivers/vlynq/vlynq.c u32 val; val 159 drivers/vlynq/vlynq.c val = readl(&dev->remote->int_device[virq >> 2]); val 164 drivers/vlynq/vlynq.c val |= VINT_TYPE_EDGE << VINT_OFFSET(virq); val 165 drivers/vlynq/vlynq.c val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq)); val 168 drivers/vlynq/vlynq.c val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq)); val 169 drivers/vlynq/vlynq.c val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq)); val 172 drivers/vlynq/vlynq.c val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq)); val 173 drivers/vlynq/vlynq.c val |= VINT_LEVEL_LOW << VINT_OFFSET(virq); val 178 drivers/vlynq/vlynq.c writel(val, &dev->remote->int_device[virq >> 2]); val 247 drivers/vlynq/vlynq.c u32 val; val 262 drivers/vlynq/vlynq.c val = VLYNQ_CTRL_INT_VECTOR(dev->local_irq); val 263 drivers/vlynq/vlynq.c val |= VLYNQ_CTRL_INT_ENABLE | VLYNQ_CTRL_INT_LOCAL | val 265 drivers/vlynq/vlynq.c val |= readl(&dev->local->control); val 267 drivers/vlynq/vlynq.c writel(val, &dev->local->control); val 269 drivers/vlynq/vlynq.c val = VLYNQ_CTRL_INT_VECTOR(dev->remote_irq); val 270 drivers/vlynq/vlynq.c val |= VLYNQ_CTRL_INT_ENABLE; val 271 drivers/vlynq/vlynq.c val |= readl(&dev->remote->control); val 273 drivers/vlynq/vlynq.c writel(val, &dev->remote->int_ptr); val 274 drivers/vlynq/vlynq.c writel(val, &dev->remote->control); val 95 drivers/vme/bridges/vme_ca91cx42.c int val; val 100 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); val 102 drivers/vme/bridges/vme_ca91cx42.c if (!(val & 0x00000800)) { val 104 drivers/vme/bridges/vme_ca91cx42.c "Read Error DGCS=%08X\n", val); val 112 drivers/vme/bridges/vme_ca91cx42.c int val; val 117 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); val 119 drivers/vme/bridges/vme_ca91cx42.c if (!(val & 0x00000800)) val 121 drivers/vme/bridges/vme_ca91cx42.c "Read Error DGCS=%08X\n", val); val 1183 drivers/vme/bridges/vme_ca91cx42.c u32 val; val 1219 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); val 1222 drivers/vme/bridges/vme_ca91cx42.c val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M); val 1224 drivers/vme/bridges/vme_ca91cx42.c val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT | val 1228 drivers/vme/bridges/vme_ca91cx42.c iowrite32(val, bridge->base + DGCS); val 1230 drivers/vme/bridges/vme_ca91cx42.c val |= CA91CX42_DGCS_GO; val 1232 drivers/vme/bridges/vme_ca91cx42.c iowrite32(val, bridge->base + DGCS); val 1238 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); val 1239 drivers/vme/bridges/vme_ca91cx42.c iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); val 1251 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); val 1253 drivers/vme/bridges/vme_ca91cx42.c if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | val 1256 drivers/vme/bridges/vme_ca91cx42.c dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val); val 1257 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DCTL); val 119 drivers/vme/bridges/vme_tsi148.c u32 val; val 127 drivers/vme/bridges/vme_tsi148.c val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); val 129 drivers/vme/bridges/vme_tsi148.c ": 0x%x\n", i, val); val 1422 drivers/vme/bridges/vme_tsi148.c u32 val; val 1424 drivers/vme/bridges/vme_tsi148.c val = be32_to_cpu(*attr); val 1429 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_2eSSTM_160; val 1432 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_2eSSTM_267; val 1435 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_2eSSTM_320; val 1441 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_TM_SCT; val 1444 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_TM_BLT; val 1447 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_TM_MBLT; val 1450 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_TM_2eVME; val 1453 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_TM_2eSST; val 1458 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_TM_2eSSTB; val 1464 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_DBW_16; val 1467 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_DBW_32; val 1477 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_A16; val 1480 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_A24; val 1483 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_A32; val 1486 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_A64; val 1489 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_CRCSR; val 1492 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_USER1; val 1495 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_USER2; val 1498 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_USER3; val 1501 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_AMODE_USER4; val 1510 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_SUP; val 1512 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_PGM; val 1514 drivers/vme/bridges/vme_tsi148.c *attr = cpu_to_be32(val); val 1522 drivers/vme/bridges/vme_tsi148.c u32 val; val 1524 drivers/vme/bridges/vme_tsi148.c val = be32_to_cpu(*attr); val 1529 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_2eSSTM_160; val 1532 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_2eSSTM_267; val 1535 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_2eSSTM_320; val 1541 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_TM_SCT; val 1544 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_TM_BLT; val 1547 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_TM_MBLT; val 1550 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_TM_2eVME; val 1553 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_TM_2eSST; val 1558 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_TM_2eSSTB; val 1564 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_DBW_16; val 1567 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_DBW_32; val 1577 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_A16; val 1580 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_A24; val 1583 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_A32; val 1586 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_A64; val 1589 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_CRCSR; val 1592 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_USER1; val 1595 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_USER2; val 1598 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_USER3; val 1601 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_AMODE_USER4; val 1610 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_SUP; val 1612 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DDAT_PGM; val 1614 drivers/vme/bridges/vme_tsi148.c *attr = cpu_to_be32(val); val 1628 drivers/vme/bridges/vme_tsi148.c u32 address_high, address_low, val; val 1665 drivers/vme/bridges/vme_tsi148.c val = TSI148_LCSR_DSAT_TYP_PAT; val 1669 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_PSZ; val 1673 drivers/vme/bridges/vme_tsi148.c val |= TSI148_LCSR_DSAT_NIN; val 1674 drivers/vme/bridges/vme_tsi148.c entry->descriptor.dsat = cpu_to_be32(val); val 1813 drivers/vme/bridges/vme_tsi148.c u32 val, dctlreg = 0; val 1877 drivers/vme/bridges/vme_tsi148.c val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + val 1880 drivers/vme/bridges/vme_tsi148.c if (val & TSI148_LCSR_DSTA_VBE) { val 1881 drivers/vme/bridges/vme_tsi148.c dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val); val 117 drivers/w1/masters/ds1wm.c u8 val) val 122 drivers/w1/masters/ds1wm.c iowrite8(val, ds1wm_data->map + (reg << 0)); val 125 drivers/w1/masters/ds1wm.c iowrite16be((u16)val, ds1wm_data->map + (reg << 1)); val 128 drivers/w1/masters/ds1wm.c iowrite32be((u32)val, ds1wm_data->map + (reg << 2)); val 134 drivers/w1/masters/ds1wm.c iowrite8(val, ds1wm_data->map + (reg << 0)); val 137 drivers/w1/masters/ds1wm.c iowrite16((u16)val, ds1wm_data->map + (reg << 1)); val 140 drivers/w1/masters/ds1wm.c iowrite32((u32)val, ds1wm_data->map + (reg << 2)); val 148 drivers/w1/masters/ds1wm.c u32 val = 0; val 153 drivers/w1/masters/ds1wm.c val = ioread8(ds1wm_data->map + (reg << 0)); val 156 drivers/w1/masters/ds1wm.c val = ioread16be(ds1wm_data->map + (reg << 1)); val 159 drivers/w1/masters/ds1wm.c val = ioread32be(ds1wm_data->map + (reg << 2)); val 165 drivers/w1/masters/ds1wm.c val = ioread8(ds1wm_data->map + (reg << 0)); val 168 drivers/w1/masters/ds1wm.c val = ioread16(ds1wm_data->map + (reg << 1)); val 171 drivers/w1/masters/ds1wm.c val = ioread32(ds1wm_data->map + (reg << 2)); val 176 drivers/w1/masters/ds1wm.c "ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val); val 177 drivers/w1/masters/ds1wm.c return (u8)val; val 78 drivers/w1/masters/matrox_w1.c static __inline__ void matrox_w1_write_reg(struct matrox_device *dev, u8 reg, u8 val) val 81 drivers/w1/masters/matrox_w1.c writeb(val, dev->port_data); val 87 drivers/w1/masters/omap_hdq.c static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val) val 89 drivers/w1/masters/omap_hdq.c __raw_writel(val, hdq_data->hdq_base + offset); val 93 drivers/w1/masters/omap_hdq.c u8 val, u8 mask) val 96 drivers/w1/masters/omap_hdq.c | (val & mask); val 146 drivers/w1/masters/omap_hdq.c static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) val 161 drivers/w1/masters/omap_hdq.c hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val); val 349 drivers/w1/masters/omap_hdq.c static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) val 389 drivers/w1/masters/omap_hdq.c *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA); val 569 drivers/w1/masters/omap_hdq.c u8 val = 0; val 576 drivers/w1/masters/omap_hdq.c ret = hdq_read_byte(hdq_data, &val); val 604 drivers/w1/masters/omap_hdq.c return val; val 145 drivers/w1/slaves/w1_ds2405.c unsigned int val; val 151 drivers/w1/slaves/w1_ds2405.c if (sscanf(buf, " %u%n", &val, &ret) < 1) val 154 drivers/w1/slaves/w1_ds2405.c if (val != 0 && val != 1) val 169 drivers/w1/slaves/w1_ds2405.c if (current_pio == val) val 351 drivers/w1/slaves/w1_ds28e04.c char val; val 356 drivers/w1/slaves/w1_ds28e04.c if (get_user(val, buf)) val 360 drivers/w1/slaves/w1_ds28e04.c val = val - 0x30; val 361 drivers/w1/slaves/w1_ds28e04.c if (val != 0 && val != 1) val 365 drivers/w1/slaves/w1_ds28e04.c w1_enable_crccheck = val; val 109 drivers/w1/slaves/w1_therm.c long *val); val 118 drivers/w1/slaves/w1_therm.c u32 attr, int channel, long *val) val 122 drivers/w1/slaves/w1_therm.c return w1_read_temp(dev, attr, channel, val); val 201 drivers/w1/slaves/w1_therm.c int (*precision)(struct device *device, int val); val 209 drivers/w1/slaves/w1_therm.c static inline int w1_DS18B20_precision(struct device *device, int val); val 210 drivers/w1/slaves/w1_therm.c static inline int w1_DS18S20_precision(struct device *device, int val); val 323 drivers/w1/slaves/w1_therm.c static inline int w1_DS18S20_precision(struct device *device, int val) val 328 drivers/w1/slaves/w1_therm.c static inline int w1_DS18B20_precision(struct device *device, int val) val 338 drivers/w1/slaves/w1_therm.c if (val > 12 || val < 9) { val 359 drivers/w1/slaves/w1_therm.c switch (val) { val 452 drivers/w1/slaves/w1_therm.c int val, ret; val 456 drivers/w1/slaves/w1_therm.c ret = kstrtoint(buf, 0, &val); val 463 drivers/w1/slaves/w1_therm.c if (val == 0) val 466 drivers/w1/slaves/w1_therm.c ret = w1_therm_families[i].precision(device, val); val 602 drivers/w1/slaves/w1_therm.c long *val) val 620 drivers/w1/slaves/w1_therm.c *val = w1_convert_temp(info.rom, fid); val 223 drivers/w1/w1_netlink.c packet.cn.id.val = CN_W1_VAL; val 409 drivers/w1/w1_netlink.c cn->id.val = CN_W1_VAL; val 665 drivers/w1/w1_netlink.c __func__, cn->id.idx, cn->id.val, val 715 drivers/w1/w1_netlink.c struct cb_id w1_id = {.idx = CN_W1_IDX, .val = CN_W1_VAL}; val 722 drivers/w1/w1_netlink.c struct cb_id w1_id = {.idx = CN_W1_IDX, .val = CN_W1_VAL}; val 54 drivers/watchdog/alim1535_wdt.c u32 val; val 58 drivers/watchdog/alim1535_wdt.c pci_read_config_dword(ali_pci, 0xCC, &val); val 59 drivers/watchdog/alim1535_wdt.c val &= ~0x3F; /* Mask count */ val 60 drivers/watchdog/alim1535_wdt.c val |= (1 << 25) | ali_timeout_bits; val 61 drivers/watchdog/alim1535_wdt.c pci_write_config_dword(ali_pci, 0xCC, val); val 74 drivers/watchdog/alim1535_wdt.c u32 val; val 78 drivers/watchdog/alim1535_wdt.c pci_read_config_dword(ali_pci, 0xCC, &val); val 79 drivers/watchdog/alim1535_wdt.c val &= ~0x3F; /* Mask count to zero (disabled) */ val 80 drivers/watchdog/alim1535_wdt.c val &= ~(1 << 25); /* and for safety mask the reset enable */ val 81 drivers/watchdog/alim1535_wdt.c pci_write_config_dword(ali_pci, 0xCC, val); val 87 drivers/watchdog/armada_37xx_wdt.c u64 val; val 93 drivers/watchdog/armada_37xx_wdt.c val = readl(dev->reg + CNTR_COUNT_LOW(id)); val 94 drivers/watchdog/armada_37xx_wdt.c val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32; val 96 drivers/watchdog/armada_37xx_wdt.c return val; val 99 drivers/watchdog/armada_37xx_wdt.c static void set_counter_value(struct armada_37xx_watchdog *dev, int id, u64 val) val 101 drivers/watchdog/armada_37xx_wdt.c writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id)); val 102 drivers/watchdog/armada_37xx_wdt.c writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id)); val 187 drivers/watchdog/aspeed_wdt.c unsigned long val; val 189 drivers/watchdog/aspeed_wdt.c if (kstrtoul(buf, 10, &val)) val 192 drivers/watchdog/aspeed_wdt.c if (val) val 42 drivers/watchdog/at91sam9_wdt.c #define wdt_write(wtd, field, val) \ val 43 drivers/watchdog/at91sam9_wdt.c writel_relaxed((val), (wdt)->base + (field)) val 71 drivers/watchdog/ath79_wdt.c static inline void ath79_wdt_wr(unsigned reg, u32 val) val 73 drivers/watchdog/ath79_wdt.c iowrite32(val, wdt_base + reg); val 112 drivers/watchdog/ath79_wdt.c static int ath79_wdt_set_timeout(int val) val 114 drivers/watchdog/ath79_wdt.c if (val < 1 || val > max_timeout) val 117 drivers/watchdog/ath79_wdt.c timeout = val; val 102 drivers/watchdog/bcm2835_wdt.c u32 val; val 106 drivers/watchdog/bcm2835_wdt.c val = readl_relaxed(wdt->base + PM_RSTC); val 107 drivers/watchdog/bcm2835_wdt.c val &= PM_RSTC_WRCFG_CLR; val 108 drivers/watchdog/bcm2835_wdt.c val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET; val 109 drivers/watchdog/bcm2835_wdt.c writel_relaxed(val, wdt->base + PM_RSTC); val 155 drivers/watchdog/bcm2835_wdt.c u32 val; val 162 drivers/watchdog/bcm2835_wdt.c val = readl_relaxed(wdt->base + PM_RSTS); val 163 drivers/watchdog/bcm2835_wdt.c val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT; val 164 drivers/watchdog/bcm2835_wdt.c writel_relaxed(val, wdt->base + PM_RSTS); val 60 drivers/watchdog/bcm_kona_wdt.c uint32_t val; val 71 drivers/watchdog/bcm_kona_wdt.c val = readl_relaxed(wdt->base + offset); val 73 drivers/watchdog/bcm_kona_wdt.c } while ((val & SECWDOG_WD_LOAD_FLAG) && count < SECWDOG_MAX_TRY); val 82 drivers/watchdog/bcm_kona_wdt.c if (val & SECWDOG_WD_LOAD_FLAG) val 86 drivers/watchdog/bcm_kona_wdt.c val &= SECWDOG_RESERVED_MASK; val 88 drivers/watchdog/bcm_kona_wdt.c return val; val 170 drivers/watchdog/bcm_kona_wdt.c int val; val 176 drivers/watchdog/bcm_kona_wdt.c val = secure_register_read(wdt, SECWDOG_CTRL_REG); val 177 drivers/watchdog/bcm_kona_wdt.c if (val < 0) { val 178 drivers/watchdog/bcm_kona_wdt.c ret = val; val 180 drivers/watchdog/bcm_kona_wdt.c val &= ~mask; val 181 drivers/watchdog/bcm_kona_wdt.c val |= newval; val 182 drivers/watchdog/bcm_kona_wdt.c writel_relaxed(val, wdt->base + SECWDOG_CTRL_REG); val 219 drivers/watchdog/bcm_kona_wdt.c int val; val 223 drivers/watchdog/bcm_kona_wdt.c val = secure_register_read(wdt, SECWDOG_COUNT_REG); val 226 drivers/watchdog/bcm_kona_wdt.c if (val < 0) val 227 drivers/watchdog/bcm_kona_wdt.c return val; val 229 drivers/watchdog/bcm_kona_wdt.c return TICKS_TO_SECS(val & SECWDOG_COUNT_MASK, wdt); val 104 drivers/watchdog/booke_wdt.c u32 val; val 107 drivers/watchdog/booke_wdt.c val = mfspr(SPRN_TCR); val 108 drivers/watchdog/booke_wdt.c val &= ~WDTP_MASK; val 109 drivers/watchdog/booke_wdt.c val |= WDTP(sec_to_period(wdog->timeout)); val 111 drivers/watchdog/booke_wdt.c mtspr(SPRN_TCR, val); val 133 drivers/watchdog/booke_wdt.c u32 val; val 138 drivers/watchdog/booke_wdt.c val = mfspr(SPRN_TCR); val 139 drivers/watchdog/booke_wdt.c val &= ~WDTP_MASK; val 140 drivers/watchdog/booke_wdt.c val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(sec_to_period(wdog->timeout))); val 142 drivers/watchdog/booke_wdt.c mtspr(SPRN_TCR, val); val 155 drivers/watchdog/booke_wdt.c u32 val; val 157 drivers/watchdog/booke_wdt.c val = mfspr(SPRN_TCR); val 158 drivers/watchdog/booke_wdt.c val &= ~(TCR_WIE | WDTP_MASK); val 159 drivers/watchdog/booke_wdt.c mtspr(SPRN_TCR, val); val 85 drivers/watchdog/cadence_wdt.c static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val) val 87 drivers/watchdog/cadence_wdt.c writel_relaxed(val, wdt->regs + offset); val 85 drivers/watchdog/coh901327_wdt.c u16 val; val 90 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_D2R); val 91 drivers/watchdog/coh901327_wdt.c if (val == U300_WDOG_D2R_DISABLE_STATUS_DISABLED) val 115 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_D2R); val 116 drivers/watchdog/coh901327_wdt.c if (val != U300_WDOG_D2R_DISABLE_STATUS_ENABLED) val 119 drivers/watchdog/coh901327_wdt.c __func__, val); val 124 drivers/watchdog/coh901327_wdt.c u16 val; val 129 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_D2R); val 130 drivers/watchdog/coh901327_wdt.c if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) { val 139 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_D2R); val 140 drivers/watchdog/coh901327_wdt.c if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) val 143 drivers/watchdog/coh901327_wdt.c __func__, val); val 180 drivers/watchdog/coh901327_wdt.c u16 val; val 183 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_CR); val 184 drivers/watchdog/coh901327_wdt.c while (val & U300_WDOG_CR_VALID_IND) val 185 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_CR); val 186 drivers/watchdog/coh901327_wdt.c val &= U300_WDOG_CR_COUNT_VALUE_MASK; val 187 drivers/watchdog/coh901327_wdt.c if (val != 0) val 188 drivers/watchdog/coh901327_wdt.c val /= 100; val 190 drivers/watchdog/coh901327_wdt.c return val; val 198 drivers/watchdog/coh901327_wdt.c u16 val; val 210 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_IER); val 211 drivers/watchdog/coh901327_wdt.c if (val == U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND) val 250 drivers/watchdog/coh901327_wdt.c u16 val; val 270 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_SR); val 271 drivers/watchdog/coh901327_wdt.c switch (val) { val 281 drivers/watchdog/coh901327_wdt.c dev_info(dev, "contains an illegal status code (%08x)\n", val); val 285 drivers/watchdog/coh901327_wdt.c val = readw(virtbase + U300_WDOG_D2R); val 286 drivers/watchdog/coh901327_wdt.c switch (val) { val 296 drivers/watchdog/coh901327_wdt.c val); val 205 drivers/watchdog/cpu5wdt.c unsigned int val; val 223 drivers/watchdog/cpu5wdt.c val = inb(port + CPU5WDT_STATUS_REG); val 224 drivers/watchdog/cpu5wdt.c val = (val >> 2) & 1; val 225 drivers/watchdog/cpu5wdt.c if (!val) val 177 drivers/watchdog/cpwd.c static void cpwd_writew(u16 val, void __iomem *addr) val 179 drivers/watchdog/cpwd.c writew(cpu_to_le16(val), addr); val 183 drivers/watchdog/cpwd.c u16 val = readw(addr); val 185 drivers/watchdog/cpwd.c return le16_to_cpu(val); val 188 drivers/watchdog/cpwd.c static void cpwd_writeb(u8 val, void __iomem *addr) val 190 drivers/watchdog/cpwd.c writeb(val, addr); val 53 drivers/watchdog/da9063_wdt.c unsigned int val; val 55 drivers/watchdog/da9063_wdt.c regmap_read(da9063->regmap, DA9063_REG_CONTROL_D, &val); val 57 drivers/watchdog/da9063_wdt.c return val & DA9063_TWDSCALE_MASK; val 121 drivers/watchdog/davinci_wdt.c u32 val; val 125 drivers/watchdog/davinci_wdt.c val = ioread32(davinci_wdt->base + WDTCR); val 126 drivers/watchdog/davinci_wdt.c if (val & WDFLAG) val 124 drivers/watchdog/dw_wdt.c u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); val 127 drivers/watchdog/dw_wdt.c val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; val 129 drivers/watchdog/dw_wdt.c val |= WDOG_CONTROL_REG_WDT_EN_MASK; val 130 drivers/watchdog/dw_wdt.c writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); val 95 drivers/watchdog/ep93xx_wdt.c unsigned long val; val 106 drivers/watchdog/ep93xx_wdt.c val = readl(priv->mmio + EP93XX_WATCHDOG); val 109 drivers/watchdog/ep93xx_wdt.c wdd->bootstatus = (val & 0x01) ? WDIOF_CARDRESET : 0; val 128 drivers/watchdog/ep93xx_wdt.c (val & 0x08) ? " (nCS1 disable detected)" : ""); val 132 drivers/watchdog/f71808e_wdt.c static inline void superio_outb(int base, int reg, u8 val); val 168 drivers/watchdog/f71808e_wdt.c int val; val 169 drivers/watchdog/f71808e_wdt.c val = superio_inb(base, reg) << 8; val 170 drivers/watchdog/f71808e_wdt.c val |= superio_inb(base, reg + 1); val 171 drivers/watchdog/f71808e_wdt.c return val; val 174 drivers/watchdog/f71808e_wdt.c static inline void superio_outb(int base, int reg, u8 val) val 177 drivers/watchdog/f71808e_wdt.c outb(val, base + 1); val 182 drivers/watchdog/f71808e_wdt.c unsigned long val = superio_inb(base, reg); val 183 drivers/watchdog/f71808e_wdt.c __set_bit(bit, &val); val 184 drivers/watchdog/f71808e_wdt.c superio_outb(base, reg, val); val 189 drivers/watchdog/f71808e_wdt.c unsigned long val = superio_inb(base, reg); val 190 drivers/watchdog/f71808e_wdt.c __clear_bit(bit, &val); val 191 drivers/watchdog/f71808e_wdt.c superio_outb(base, reg, val); val 68 drivers/watchdog/geodewdt.c static int geodewdt_set_heartbeat(int val) val 70 drivers/watchdog/geodewdt.c if (val < 1 || val > GEODEWDT_MAX_SECONDS) val 74 drivers/watchdog/geodewdt.c cs5535_mfgpt_write(wdt_timer, MFGPT_REG_CMP2, val * GEODEWDT_HZ); val 78 drivers/watchdog/geodewdt.c timeout = val; val 96 drivers/watchdog/hpwdt.c static void hpwdt_ping_ticks(int val) val 98 drivers/watchdog/hpwdt.c val = min(val, HPWDT_MAX_TICKS); val 99 drivers/watchdog/hpwdt.c iowrite16(val, hpwdt_timer_reg); val 117 drivers/watchdog/hpwdt.c static int hpwdt_settimeout(struct watchdog_device *wdd, unsigned int val) val 119 drivers/watchdog/hpwdt.c dev_dbg(wdd->parent, "set_timeout = %d\n", val); val 121 drivers/watchdog/hpwdt.c wdd->timeout = val; val 122 drivers/watchdog/hpwdt.c if (val <= wdd->pretimeout) { val 137 drivers/watchdog/hpwdt.c unsigned int val = 0; val 141 drivers/watchdog/hpwdt.c val = PRETIMEOUT_SEC; val 142 drivers/watchdog/hpwdt.c if (val >= wdd->timeout) val 146 drivers/watchdog/hpwdt.c if (val != req) val 147 drivers/watchdog/hpwdt.c dev_dbg(wdd->parent, "Rounding pretimeout to: %d\n", val); val 149 drivers/watchdog/hpwdt.c wdd->pretimeout = val; val 150 drivers/watchdog/hpwdt.c pretimeout = !!val; val 188 drivers/watchdog/hpwdt.c unsigned int val = max((unsigned int)kdumptimeout, hpwdt_dev.timeout); val 189 drivers/watchdog/hpwdt.c hpwdt_ping_ticks(SECS_TO_TICKS(val)); val 120 drivers/watchdog/i6300esb.c u8 val; val 125 drivers/watchdog/i6300esb.c val = ESB_WDT_ENABLE | (_wdd_nowayout ? ESB_WDT_LOCK : 0x00); val 126 drivers/watchdog/i6300esb.c pci_write_config_byte(edev->pdev, ESB_LOCK_REG, val); val 133 drivers/watchdog/i6300esb.c u8 val; val 140 drivers/watchdog/i6300esb.c pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val); val 143 drivers/watchdog/i6300esb.c return val & ESB_WDT_ENABLE; val 160 drivers/watchdog/i6300esb.c u32 val; val 166 drivers/watchdog/i6300esb.c val = time << 9; val 170 drivers/watchdog/i6300esb.c writel(val, ESB_TIMER1_REG(edev)); val 174 drivers/watchdog/i6300esb.c writel(val, ESB_TIMER2_REG(edev)); val 222 drivers/watchdog/iTCO_wdt.c u16 val, newval; val 224 drivers/watchdog/iTCO_wdt.c val = inw(TCO1_CNT(p)); val 226 drivers/watchdog/iTCO_wdt.c val |= BIT(0); val 228 drivers/watchdog/iTCO_wdt.c val &= ~BIT(0); val 229 drivers/watchdog/iTCO_wdt.c outw(val, TCO1_CNT(p)); val 233 drivers/watchdog/iTCO_wdt.c return val != newval ? -EIO : 0; val 260 drivers/watchdog/iTCO_wdt.c unsigned int val; val 281 drivers/watchdog/iTCO_wdt.c val = inw(TCO1_CNT(p)); val 282 drivers/watchdog/iTCO_wdt.c val &= 0xf7ff; val 283 drivers/watchdog/iTCO_wdt.c outw(val, TCO1_CNT(p)); val 284 drivers/watchdog/iTCO_wdt.c val = inw(TCO1_CNT(p)); val 287 drivers/watchdog/iTCO_wdt.c if (val & 0x0800) val 295 drivers/watchdog/iTCO_wdt.c unsigned int val; val 302 drivers/watchdog/iTCO_wdt.c val = inw(TCO1_CNT(p)); val 303 drivers/watchdog/iTCO_wdt.c val |= 0x0800; val 304 drivers/watchdog/iTCO_wdt.c outw(val, TCO1_CNT(p)); val 305 drivers/watchdog/iTCO_wdt.c val = inw(TCO1_CNT(p)); val 312 drivers/watchdog/iTCO_wdt.c if ((val & 0x0800) == 0) val 101 drivers/watchdog/imgpdc_wdt.c unsigned int val; val 104 drivers/watchdog/imgpdc_wdt.c val = readl(wdt->base + PDC_WDT_CONFIG); val 105 drivers/watchdog/imgpdc_wdt.c val &= ~PDC_WDT_CONFIG_ENABLE; val 106 drivers/watchdog/imgpdc_wdt.c writel(val, wdt->base + PDC_WDT_CONFIG); val 117 drivers/watchdog/imgpdc_wdt.c unsigned int val; val 119 drivers/watchdog/imgpdc_wdt.c val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK; val 120 drivers/watchdog/imgpdc_wdt.c val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; val 121 drivers/watchdog/imgpdc_wdt.c writel(val, wdt->base + PDC_WDT_CONFIG); val 139 drivers/watchdog/imgpdc_wdt.c unsigned int val; val 144 drivers/watchdog/imgpdc_wdt.c val = readl(wdt->base + PDC_WDT_CONFIG); val 145 drivers/watchdog/imgpdc_wdt.c val |= PDC_WDT_CONFIG_ENABLE; val 146 drivers/watchdog/imgpdc_wdt.c writel(val, wdt->base + PDC_WDT_CONFIG); val 187 drivers/watchdog/imgpdc_wdt.c int ret, val; val 263 drivers/watchdog/imgpdc_wdt.c val = readl(pdc_wdt->base + PDC_WDT_TICKLE1); val 264 drivers/watchdog/imgpdc_wdt.c val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT; val 265 drivers/watchdog/imgpdc_wdt.c switch (val) { val 284 drivers/watchdog/imgpdc_wdt.c dev_info(dev, "contains an illegal status code (%08x)\n", val); val 125 drivers/watchdog/imx2_wdt.c u32 val; val 127 drivers/watchdog/imx2_wdt.c regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); val 130 drivers/watchdog/imx2_wdt.c val |= IMX2_WDT_WCR_WDZST; val 132 drivers/watchdog/imx2_wdt.c val &= ~IMX2_WDT_WCR_WT; val 135 drivers/watchdog/imx2_wdt.c val &= ~IMX2_WDT_WCR_WRE; val 138 drivers/watchdog/imx2_wdt.c val |= IMX2_WDT_WCR_WRE; val 140 drivers/watchdog/imx2_wdt.c val &= ~IMX2_WDT_WCR_WDE; val 142 drivers/watchdog/imx2_wdt.c val |= WDOG_SEC_TO_COUNT(wdog->timeout); val 144 drivers/watchdog/imx2_wdt.c regmap_write(wdev->regmap, IMX2_WDT_WCR, val); val 147 drivers/watchdog/imx2_wdt.c val |= IMX2_WDT_WCR_WDE; val 148 drivers/watchdog/imx2_wdt.c regmap_write(wdev->regmap, IMX2_WDT_WCR, val); val 153 drivers/watchdog/imx2_wdt.c u32 val; val 155 drivers/watchdog/imx2_wdt.c regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); val 157 drivers/watchdog/imx2_wdt.c return val & IMX2_WDT_WCR_WDE; val 254 drivers/watchdog/imx2_wdt.c u32 val; val 295 drivers/watchdog/imx2_wdt.c regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val); val 296 drivers/watchdog/imx2_wdt.c wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0; val 52 drivers/watchdog/imx7ulp_wdt.c u32 val = readl(base + WDOG_CS); val 56 drivers/watchdog/imx7ulp_wdt.c writel(val | WDOG_CS_EN, base + WDOG_CS); val 58 drivers/watchdog/imx7ulp_wdt.c writel(val & ~WDOG_CS_EN, base + WDOG_CS); val 63 drivers/watchdog/imx7ulp_wdt.c u32 val = readl(base + WDOG_CS); val 65 drivers/watchdog/imx7ulp_wdt.c return val & WDOG_CS_EN; val 99 drivers/watchdog/imx7ulp_wdt.c u32 val = WDOG_CLOCK_RATE * timeout; val 102 drivers/watchdog/imx7ulp_wdt.c writel(val, wdt->base + WDOG_TOVAL); val 141 drivers/watchdog/imx7ulp_wdt.c u32 val; val 150 drivers/watchdog/imx7ulp_wdt.c val = BIT(13) | BIT(8) | BIT(5); val 151 drivers/watchdog/imx7ulp_wdt.c writel(val, base + WDOG_CS); val 99 drivers/watchdog/it8712f_wdt.c static void superio_outb(int val, int reg) val 102 drivers/watchdog/it8712f_wdt.c outb(val, VAL); val 107 drivers/watchdog/it8712f_wdt.c int val; val 109 drivers/watchdog/it8712f_wdt.c val = inb(VAL) << 8; val 111 drivers/watchdog/it8712f_wdt.c val |= inb(VAL); val 112 drivers/watchdog/it8712f_wdt.c return val; val 136 drivers/watchdog/it87_wdt.c static inline void superio_outb(int val, int reg) val 139 drivers/watchdog/it87_wdt.c outb(val, VAL); val 144 drivers/watchdog/it87_wdt.c int val; val 146 drivers/watchdog/it87_wdt.c val = inb(VAL) << 8; val 148 drivers/watchdog/it87_wdt.c val |= inb(VAL); val 149 drivers/watchdog/it87_wdt.c return val; val 152 drivers/watchdog/it87_wdt.c static inline void superio_outw(int val, int reg) val 155 drivers/watchdog/it87_wdt.c outb(val >> 8, VAL); val 157 drivers/watchdog/it87_wdt.c outb(val, VAL); val 72 drivers/watchdog/lantiq_wdt.c static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset) val 74 drivers/watchdog/lantiq_wdt.c __raw_writel(val, priv->membase + offset); val 80 drivers/watchdog/lantiq_wdt.c u32 val = ltq_wdt_r32(priv, offset); val 82 drivers/watchdog/lantiq_wdt.c val &= ~(clear); val 83 drivers/watchdog/lantiq_wdt.c val |= set; val 84 drivers/watchdog/lantiq_wdt.c ltq_wdt_w32(priv, val, offset); val 161 drivers/watchdog/lantiq_wdt.c u32 val; val 168 drivers/watchdog/lantiq_wdt.c err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val); val 172 drivers/watchdog/lantiq_wdt.c if (val & LTQ_XRX_RCU_RST_STAT_WDT) val 181 drivers/watchdog/lantiq_wdt.c u32 val; val 189 drivers/watchdog/lantiq_wdt.c err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val); val 193 drivers/watchdog/lantiq_wdt.c if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT) val 105 drivers/watchdog/lpc18xx_wdt.c unsigned int val; val 107 drivers/watchdog/lpc18xx_wdt.c val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate, val 109 drivers/watchdog/lpc18xx_wdt.c writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC); val 126 drivers/watchdog/lpc18xx_wdt.c unsigned int val; val 128 drivers/watchdog/lpc18xx_wdt.c val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV); val 129 drivers/watchdog/lpc18xx_wdt.c return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; val 135 drivers/watchdog/lpc18xx_wdt.c unsigned int val; val 140 drivers/watchdog/lpc18xx_wdt.c val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD); val 141 drivers/watchdog/lpc18xx_wdt.c val |= LPC18XX_WDT_MOD_WDEN; val 142 drivers/watchdog/lpc18xx_wdt.c val |= LPC18XX_WDT_MOD_WDRESET; val 143 drivers/watchdog/lpc18xx_wdt.c writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD); val 160 drivers/watchdog/lpc18xx_wdt.c int val; val 167 drivers/watchdog/lpc18xx_wdt.c val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD); val 168 drivers/watchdog/lpc18xx_wdt.c val |= LPC18XX_WDT_MOD_WDEN; val 169 drivers/watchdog/lpc18xx_wdt.c val |= LPC18XX_WDT_MOD_WDRESET; val 170 drivers/watchdog/lpc18xx_wdt.c writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD); val 162 drivers/watchdog/max63xx_wdt.c u8 val; val 166 drivers/watchdog/max63xx_wdt.c val = __raw_readb(wdt->base); val 168 drivers/watchdog/max63xx_wdt.c __raw_writeb(val | MAX6369_WDI, wdt->base); val 169 drivers/watchdog/max63xx_wdt.c __raw_writeb(val & ~MAX6369_WDI, wdt->base); val 176 drivers/watchdog/max63xx_wdt.c u8 val; val 180 drivers/watchdog/max63xx_wdt.c val = __raw_readb(wdt->base); val 181 drivers/watchdog/max63xx_wdt.c val &= ~MAX6369_WDSET; val 182 drivers/watchdog/max63xx_wdt.c val |= set & MAX6369_WDSET; val 183 drivers/watchdog/max63xx_wdt.c __raw_writeb(val, wdt->base); val 167 drivers/watchdog/mena21_wdt.c int val; val 169 drivers/watchdog/mena21_wdt.c val = gpiod_get_value(drv->gpios[i]); val 170 drivers/watchdog/mena21_wdt.c gpiod_direction_output(drv->gpios[i], val); val 37 drivers/watchdog/menz69_wdt.c u16 val; val 39 drivers/watchdog/menz69_wdt.c val = readw(drv->base + MEN_Z069_WTR); val 40 drivers/watchdog/menz69_wdt.c val |= MEN_Z069_WTR_WDEN; val 41 drivers/watchdog/menz69_wdt.c writew(val, drv->base + MEN_Z069_WTR); val 49 drivers/watchdog/menz69_wdt.c u16 val; val 51 drivers/watchdog/menz69_wdt.c val = readw(drv->base + MEN_Z069_WTR); val 52 drivers/watchdog/menz69_wdt.c val &= ~MEN_Z069_WTR_WDEN; val 53 drivers/watchdog/menz69_wdt.c writew(val, drv->base + MEN_Z069_WTR); val 61 drivers/watchdog/menz69_wdt.c u16 val; val 64 drivers/watchdog/menz69_wdt.c val = readw(drv->base + MEN_Z069_WVR); val 65 drivers/watchdog/menz69_wdt.c val ^= 0xffff; val 66 drivers/watchdog/menz69_wdt.c writew(val, drv->base + MEN_Z069_WVR); val 75 drivers/watchdog/menz69_wdt.c u16 reg, val, ena; val 78 drivers/watchdog/menz69_wdt.c val = timeout * MEN_Z069_TIMER_FREQ; val 82 drivers/watchdog/menz69_wdt.c reg = ena | val; val 43 drivers/watchdog/mt7621_wdt.c static inline void rt_wdt_w32(unsigned reg, u32 val) val 45 drivers/watchdog/mt7621_wdt.c iowrite32(val, mt7621_wdt_base + reg); val 56 drivers/watchdog/npcm_wdt.c u32 val; val 58 drivers/watchdog/npcm_wdt.c val = readl(wdt->reg); val 59 drivers/watchdog/npcm_wdt.c writel(val | NPCM_WTR, wdt->reg); val 67 drivers/watchdog/npcm_wdt.c u32 val; val 70 drivers/watchdog/npcm_wdt.c val = 0x800; val 72 drivers/watchdog/npcm_wdt.c val = 0x420; val 74 drivers/watchdog/npcm_wdt.c val = 0x810; val 76 drivers/watchdog/npcm_wdt.c val = 0x430; val 78 drivers/watchdog/npcm_wdt.c val = 0x820; val 80 drivers/watchdog/npcm_wdt.c val = 0xC00; val 82 drivers/watchdog/npcm_wdt.c val = 0x830; val 84 drivers/watchdog/npcm_wdt.c val = 0xC10; val 86 drivers/watchdog/npcm_wdt.c val = 0xC20; val 88 drivers/watchdog/npcm_wdt.c val = 0xC30; val 90 drivers/watchdog/npcm_wdt.c val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; val 92 drivers/watchdog/npcm_wdt.c writel(val, wdt->reg); val 77 drivers/watchdog/nv_tco.c u32 val; val 81 drivers/watchdog/nv_tco.c val = inl(TCO_CNT(tcobase)); val 82 drivers/watchdog/nv_tco.c val &= ~TCO_CNT_TCOHALT; val 83 drivers/watchdog/nv_tco.c outl(val, TCO_CNT(tcobase)); val 89 drivers/watchdog/nv_tco.c u32 val; val 93 drivers/watchdog/nv_tco.c val = inl(TCO_CNT(tcobase)); val 94 drivers/watchdog/nv_tco.c val |= TCO_CNT_TCOHALT; val 95 drivers/watchdog/nv_tco.c outl(val, TCO_CNT(tcobase)); val 113 drivers/watchdog/nv_tco.c u8 val; val 130 drivers/watchdog/nv_tco.c val = inb(TCO_TMR(tcobase)); val 131 drivers/watchdog/nv_tco.c val &= 0xc0; val 132 drivers/watchdog/nv_tco.c val |= tmrval; val 133 drivers/watchdog/nv_tco.c outb(val, TCO_TMR(tcobase)); val 134 drivers/watchdog/nv_tco.c val = inb(TCO_TMR(tcobase)); val 136 drivers/watchdog/nv_tco.c if ((val & 0x3f) != tmrval) val 308 drivers/watchdog/nv_tco.c u32 val; val 322 drivers/watchdog/nv_tco.c pci_read_config_dword(tco_pci, 0x64, &val); val 323 drivers/watchdog/nv_tco.c val &= 0xffff; val 324 drivers/watchdog/nv_tco.c if (val == 0x0001 || val == 0x0000) { val 329 drivers/watchdog/nv_tco.c val &= 0xff00; val 330 drivers/watchdog/nv_tco.c tcobase = val + 0x40; val 353 drivers/watchdog/nv_tco.c val = inl(MCP51_SMI_EN(tcobase)); val 354 drivers/watchdog/nv_tco.c val &= ~MCP51_SMI_EN_TCO; val 355 drivers/watchdog/nv_tco.c outl(val, MCP51_SMI_EN(tcobase)); val 356 drivers/watchdog/nv_tco.c val = inl(MCP51_SMI_EN(tcobase)); val 358 drivers/watchdog/nv_tco.c if (val & MCP51_SMI_EN_TCO) { val 364 drivers/watchdog/nv_tco.c pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); val 365 drivers/watchdog/nv_tco.c val |= MCP51_SMBUS_SETUP_B_TCO_REBOOT; val 366 drivers/watchdog/nv_tco.c pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val); val 367 drivers/watchdog/nv_tco.c pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); val 368 drivers/watchdog/nv_tco.c if (!(val & MCP51_SMBUS_SETUP_B_TCO_REBOOT)) { val 428 drivers/watchdog/nv_tco.c u32 val; val 435 drivers/watchdog/nv_tco.c pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); val 436 drivers/watchdog/nv_tco.c val &= ~MCP51_SMBUS_SETUP_B_TCO_REBOOT; val 437 drivers/watchdog/nv_tco.c pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val); val 438 drivers/watchdog/nv_tco.c pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); val 439 drivers/watchdog/nv_tco.c if (val & MCP51_SMBUS_SETUP_B_TCO_REBOOT) { val 458 drivers/watchdog/nv_tco.c u32 val; val 464 drivers/watchdog/nv_tco.c pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); val 465 drivers/watchdog/nv_tco.c val &= ~MCP51_SMBUS_SETUP_B_TCO_REBOOT; val 466 drivers/watchdog/nv_tco.c pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val); val 34 drivers/watchdog/omap_wdt.h #define GET_WCCR_SECS(val) ((0xffffffff - (val) + 1) / (32768/(1<<PTV))) val 166 drivers/watchdog/orion_wdt.c u32 val; val 178 drivers/watchdog/orion_wdt.c val = WDT_AXP_FIXED_ENABLE_BIT | TIMER1_FIXED_ENABLE_BIT; val 179 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, val, val); val 65 drivers/watchdog/pic32-dmt.c u32 val; val 67 drivers/watchdog/pic32-dmt.c val = readl(dmt->regs + DMTSTAT_REG); val 68 drivers/watchdog/pic32-dmt.c val &= (DMTSTAT_BAD1 | DMTSTAT_BAD2 | DMTSTAT_EVENT); val 69 drivers/watchdog/pic32-dmt.c if (val) val 59 drivers/watchdog/rdc321x_wdt.c u32 val; val 67 drivers/watchdog/rdc321x_wdt.c rdc321x_wdt_device.base_reg, &val); val 68 drivers/watchdog/rdc321x_wdt.c val |= RDC_WDT_EN; val 70 drivers/watchdog/rdc321x_wdt.c rdc321x_wdt_device.base_reg, val); val 55 drivers/watchdog/renesas_wdt.c static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg) val 58 drivers/watchdog/renesas_wdt.c val |= 0x5a5a0000; val 60 drivers/watchdog/renesas_wdt.c val |= 0xa5a5a500; val 62 drivers/watchdog/renesas_wdt.c writel_relaxed(val, priv->base + reg); val 86 drivers/watchdog/renesas_wdt.c u8 val; val 91 drivers/watchdog/renesas_wdt.c val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME; val 92 drivers/watchdog/renesas_wdt.c rwdt_write(priv, val, RWTCSRA); val 123 drivers/watchdog/renesas_wdt.c u16 val = readw_relaxed(priv->base + RWTCNT); val 125 drivers/watchdog/renesas_wdt.c return DIV_BY_CLKS_PER_SEC(priv, 65536 - val); val 68 drivers/watchdog/riowd.c static void riowd_writereg(struct riowd *p, u8 val, int index) val 74 drivers/watchdog/riowd.c writeb(val, p->regs + 1); val 110 drivers/watchdog/rn5t618_wdt.c unsigned int val; val 114 drivers/watchdog/rn5t618_wdt.c ret = regmap_read(wdt->rn5t618->regmap, RN5T618_WATCHDOG, &val); val 118 drivers/watchdog/rn5t618_wdt.c ret = regmap_write(wdt->rn5t618->regmap, RN5T618_WATCHDOG, val); val 54 drivers/watchdog/rt2880_wdt.c static inline void rt_wdt_w32(unsigned reg, u32 val) val 56 drivers/watchdog/rt2880_wdt.c iowrite32(val, rt288x_wdt_base + reg); val 36 drivers/watchdog/rtd119x_wdt.c u32 val; val 38 drivers/watchdog/rtd119x_wdt.c val = readl_relaxed(data->base + RTD119X_TCWCR); val 39 drivers/watchdog/rtd119x_wdt.c val &= ~RTD119X_TCWCR_WDEN_MASK; val 40 drivers/watchdog/rtd119x_wdt.c val |= RTD119X_TCWCR_WDEN_ENABLED; val 41 drivers/watchdog/rtd119x_wdt.c writel(val, data->base + RTD119X_TCWCR); val 49 drivers/watchdog/rtd119x_wdt.c u32 val; val 51 drivers/watchdog/rtd119x_wdt.c val = readl_relaxed(data->base + RTD119X_TCWCR); val 52 drivers/watchdog/rtd119x_wdt.c val &= ~RTD119X_TCWCR_WDEN_MASK; val 53 drivers/watchdog/rtd119x_wdt.c val |= RTD119X_TCWCR_WDEN_DISABLED; val 54 drivers/watchdog/rtd119x_wdt.c writel(val, data->base + RTD119X_TCWCR); val 68 drivers/watchdog/rtd119x_wdt.c static int rtd119x_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val) val 72 drivers/watchdog/rtd119x_wdt.c writel(val * clk_get_rate(data->clk), data->base + RTD119X_TCWOV); val 74 drivers/watchdog/rtd119x_wdt.c data->wdt_dev.timeout = val; val 207 drivers/watchdog/s3c2410_wdt.c u32 val = 0; val 214 drivers/watchdog/s3c2410_wdt.c val = mask_val; val 218 drivers/watchdog/s3c2410_wdt.c mask_val, val); val 224 drivers/watchdog/s3c2410_wdt.c mask_val, val); val 416 drivers/watchdog/s3c2410_wdt.c unsigned long val, void *data) val 424 drivers/watchdog/s3c2410_wdt.c if (val == CPUFREQ_PRECHANGE) { val 431 drivers/watchdog/s3c2410_wdt.c } else if (val == CPUFREQ_POSTCHANGE) { val 56 drivers/watchdog/sama5d4_wdt.c static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) val 65 drivers/watchdog/sama5d4_wdt.c writel_relaxed(val, wdt->reg_base + field); val 69 drivers/watchdog/sama5d4_wdt.c static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val) val 73 drivers/watchdog/sama5d4_wdt.c writel_relaxed(val, wdt->reg_base + field); val 99 drivers/watchdog/sch311x_wdt.c static inline void sch311x_sio_outb(int sio_config_port, int reg, int val) val 102 drivers/watchdog/sch311x_wdt.c outb(val, sio_config_port + 1); val 95 drivers/watchdog/sp5100_tco.c u32 val; val 97 drivers/watchdog/sp5100_tco.c val = readl(SP5100_WDT_CONTROL(tco->tcobase)); val 98 drivers/watchdog/sp5100_tco.c val |= SP5100_WDT_START_STOP_BIT; val 99 drivers/watchdog/sp5100_tco.c writel(val, SP5100_WDT_CONTROL(tco->tcobase)); val 107 drivers/watchdog/sp5100_tco.c u32 val; val 109 drivers/watchdog/sp5100_tco.c val = readl(SP5100_WDT_CONTROL(tco->tcobase)); val 110 drivers/watchdog/sp5100_tco.c val &= ~SP5100_WDT_START_STOP_BIT; val 111 drivers/watchdog/sp5100_tco.c writel(val, SP5100_WDT_CONTROL(tco->tcobase)); val 119 drivers/watchdog/sp5100_tco.c u32 val; val 121 drivers/watchdog/sp5100_tco.c val = readl(SP5100_WDT_CONTROL(tco->tcobase)); val 122 drivers/watchdog/sp5100_tco.c val |= SP5100_WDT_TRIGGER_BIT; val 123 drivers/watchdog/sp5100_tco.c writel(val, SP5100_WDT_CONTROL(tco->tcobase)); val 149 drivers/watchdog/sp5100_tco.c u8 val; val 152 drivers/watchdog/sp5100_tco.c val = inb(SP5100_IO_PM_DATA_REG); val 153 drivers/watchdog/sp5100_tco.c val &= reset; val 154 drivers/watchdog/sp5100_tco.c val |= set; val 155 drivers/watchdog/sp5100_tco.c outb(val, SP5100_IO_PM_DATA_REG); val 160 drivers/watchdog/sp5100_tco.c u32 val; val 179 drivers/watchdog/sp5100_tco.c &val); val 181 drivers/watchdog/sp5100_tco.c val |= SP5100_PCI_WATCHDOG_DECODE_EN; val 185 drivers/watchdog/sp5100_tco.c val); val 203 drivers/watchdog/sp5100_tco.c u32 val = 0; val 207 drivers/watchdog/sp5100_tco.c val = (val << 8) + sp5100_tco_read_pm_reg8(index + i); val 209 drivers/watchdog/sp5100_tco.c return val; val 217 drivers/watchdog/sp5100_tco.c u32 mmio_addr = 0, val; val 244 drivers/watchdog/sp5100_tco.c val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN); val 245 drivers/watchdog/sp5100_tco.c if (val & EFCH_PM_DECODEEN_WDT_TMREN) val 292 drivers/watchdog/sp5100_tco.c val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL); val 293 drivers/watchdog/sp5100_tco.c if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) { val 325 drivers/watchdog/sp5100_tco.c val = readl(SP5100_WDT_CONTROL(tco->tcobase)); val 326 drivers/watchdog/sp5100_tco.c if (val & SP5100_WDT_DISABLED) { val 336 drivers/watchdog/sp5100_tco.c if (val & SP5100_WDT_FIRED) val 339 drivers/watchdog/sp5100_tco.c val &= ~SP5100_WDT_ACTION_RESET; val 340 drivers/watchdog/sp5100_tco.c writel(val, SP5100_WDT_CONTROL(tco->tcobase)); val 94 drivers/watchdog/sprd_wdt.c u32 val; val 96 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) << val 98 drivers/watchdog/sprd_wdt.c val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) & val 101 drivers/watchdog/sprd_wdt.c return val; val 107 drivers/watchdog/sprd_wdt.c u32 val, delay_cnt = 0; val 128 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_INT_RAW); val 129 drivers/watchdog/sprd_wdt.c if (!(val & SPRD_WDT_LD_BUSY_BIT)) val 142 drivers/watchdog/sprd_wdt.c u32 val; val 155 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); val 156 drivers/watchdog/sprd_wdt.c val |= SPRD_WDT_NEW_VER_EN; val 157 drivers/watchdog/sprd_wdt.c writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); val 177 drivers/watchdog/sprd_wdt.c u32 val; val 185 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); val 186 drivers/watchdog/sprd_wdt.c val |= SPRD_WDT_CNT_EN_BIT | SPRD_WDT_INT_EN_BIT | SPRD_WDT_RST_EN_BIT; val 187 drivers/watchdog/sprd_wdt.c writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); val 197 drivers/watchdog/sprd_wdt.c u32 val; val 200 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); val 201 drivers/watchdog/sprd_wdt.c val &= ~(SPRD_WDT_CNT_EN_BIT | SPRD_WDT_RST_EN_BIT | val 203 drivers/watchdog/sprd_wdt.c writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); val 237 drivers/watchdog/sprd_wdt.c u32 val; val 239 drivers/watchdog/sprd_wdt.c val = sprd_wdt_get_cnt_value(wdt); val 240 drivers/watchdog/sprd_wdt.c return val / SPRD_WDT_CNT_STEP; val 82 drivers/watchdog/stm32_iwdg.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) val 84 drivers/watchdog/stm32_iwdg.c writel_relaxed(val, base + reg); val 88 drivers/watchdog/sunxi_wdt.c u32 val; val 91 drivers/watchdog/sunxi_wdt.c val = readl(wdt_base + regs->wdt_cfg); val 92 drivers/watchdog/sunxi_wdt.c val &= ~(regs->wdt_reset_mask); val 93 drivers/watchdog/sunxi_wdt.c val |= regs->wdt_reset_val; val 94 drivers/watchdog/sunxi_wdt.c writel(val, wdt_base + regs->wdt_cfg); val 97 drivers/watchdog/sunxi_wdt.c val = readl(wdt_base + regs->wdt_mode); val 98 drivers/watchdog/sunxi_wdt.c val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); val 99 drivers/watchdog/sunxi_wdt.c val |= WDT_MODE_EN; val 100 drivers/watchdog/sunxi_wdt.c writel(val, wdt_base + regs->wdt_mode); val 110 drivers/watchdog/sunxi_wdt.c val = readl(wdt_base + regs->wdt_mode); val 111 drivers/watchdog/sunxi_wdt.c val |= WDT_MODE_EN; val 112 drivers/watchdog/sunxi_wdt.c writel(val, wdt_base + regs->wdt_mode); val 81 drivers/watchdog/tegra_wdt.c u32 val; val 89 drivers/watchdog/tegra_wdt.c val = 1000000ul / 4; val 90 drivers/watchdog/tegra_wdt.c val |= (TIMER_EN | TIMER_PERIODIC); val 91 drivers/watchdog/tegra_wdt.c writel(val, wdt->tmr_regs + TIMER_PTV); val 100 drivers/watchdog/tegra_wdt.c val = WDT_TIMER_ID | val 103 drivers/watchdog/tegra_wdt.c writel(val, wdt->wdt_regs + WDT_CFG); val 146 drivers/watchdog/tegra_wdt.c u32 val; val 150 drivers/watchdog/tegra_wdt.c val = readl(wdt->wdt_regs + WDT_STS); val 153 drivers/watchdog/tegra_wdt.c count = (val >> WDT_STS_COUNT_SHIFT) & WDT_STS_COUNT_MASK; val 156 drivers/watchdog/tegra_wdt.c exp = (val >> WDT_STS_EXP_SHIFT) & WDT_STS_EXP_MASK; val 47 drivers/watchdog/tqmx86_wdt.c u8 val; val 50 drivers/watchdog/tqmx86_wdt.c val = ilog2(t) | 0x90; val 51 drivers/watchdog/tqmx86_wdt.c val += 3; /* values 0,1,2 correspond to 0.125,0.25,0.5s timeouts */ val 52 drivers/watchdog/tqmx86_wdt.c iowrite8(val, priv->io_base + TQMX86_WDCFG); val 59 drivers/watchdog/ts4800_wdt.c static void ts4800_write_feed(struct ts4800_wdt *wdt, u32 val) val 61 drivers/watchdog/ts4800_wdt.c regmap_write(wdt->regmap, wdt->feed_offset, val); val 23 drivers/watchdog/twl4030_wdt.c static int twl4030_wdt_write(unsigned char val) val 25 drivers/watchdog/twl4030_wdt.c return twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, val, val 58 drivers/watchdog/uniphier_wdt.c unsigned int val; val 69 drivers/watchdog/uniphier_wdt.c ret = regmap_read_poll_timeout(wdev->regmap, WDTCTRL, val, val 70 drivers/watchdog/uniphier_wdt.c (val & WDTCTRL_STATUS), val 78 drivers/watchdog/uniphier_wdt.c unsigned int val; val 81 drivers/watchdog/uniphier_wdt.c ret = regmap_read_poll_timeout(regmap, WDTCTRL, val, val 82 drivers/watchdog/uniphier_wdt.c !(val & WDTCTRL_STATUS), val 100 drivers/watchdog/uniphier_wdt.c ret = regmap_read_poll_timeout(regmap, WDTCTRL, val, val 101 drivers/watchdog/uniphier_wdt.c (val & WDTCTRL_STATUS), val 115 drivers/watchdog/w83627hf_wdt.c static void superio_outb(int reg, int val) val 118 drivers/watchdog/w83627hf_wdt.c outb(val, WDT_EFDR); val 334 drivers/watchdog/w83627hf_wdt.c u8 val; val 345 drivers/watchdog/w83627hf_wdt.c val = superio_inb(0x20); val 346 drivers/watchdog/w83627hf_wdt.c switch (val) { val 425 drivers/watchdog/w83627hf_wdt.c pr_err("Unsupported chip ID: 0x%02x\n", val); val 487 drivers/watchdog/watchdog_dev.c unsigned int val; val 490 drivers/watchdog/watchdog_dev.c status = watchdog_get_timeleft(wdd, &val); val 493 drivers/watchdog/watchdog_dev.c status = sprintf(buf, "%u\n", val); val 699 drivers/watchdog/watchdog_dev.c unsigned int val; val 720 drivers/watchdog/watchdog_dev.c val = watchdog_get_status(wdd); val 721 drivers/watchdog/watchdog_dev.c err = put_user(val, p); val 727 drivers/watchdog/watchdog_dev.c if (get_user(val, p)) { val 731 drivers/watchdog/watchdog_dev.c if (val & WDIOS_DISABLECARD) { val 736 drivers/watchdog/watchdog_dev.c if (val & WDIOS_ENABLECARD) val 747 drivers/watchdog/watchdog_dev.c if (get_user(val, p)) { val 751 drivers/watchdog/watchdog_dev.c err = watchdog_set_timeout(wdd, val); val 770 drivers/watchdog/watchdog_dev.c err = watchdog_get_timeleft(wdd, &val); val 773 drivers/watchdog/watchdog_dev.c err = put_user(val, p); val 776 drivers/watchdog/watchdog_dev.c if (get_user(val, p)) { val 780 drivers/watchdog/watchdog_dev.c err = watchdog_set_pretimeout(wdd, val); val 105 drivers/watchdog/wdt.c static void wdt_ctr_load(int ctr, int val) val 107 drivers/watchdog/wdt.c outb_p(val&0xFF, WDT_COUNT0+ctr); val 108 drivers/watchdog/wdt.c outb_p(val>>8, WDT_COUNT0+ctr); val 107 drivers/watchdog/wdt_pci.c static void wdtpci_ctr_load(int ctr, int val) val 109 drivers/watchdog/wdt_pci.c outb(val & 0xFF, WDT_COUNT0 + ctr); val 111 drivers/watchdog/wdt_pci.c outb(val >> 8, WDT_COUNT0 + ctr); val 40 drivers/watchdog/wm831x_wdt.c u16 val; /* WDOG_TO value */ val 156 drivers/watchdog/wm831x_wdt.c wm831x_wdt_cfgs[i].val); val 220 drivers/watchdog/wm831x_wdt.c if (wm831x_wdt_cfgs[i].val == reg) val 29 drivers/watchdog/wm8350_wdt.c u16 val; /* To be set in WM8350_SYSTEM_CONTROL_2 */ val 54 drivers/watchdog/wm8350_wdt.c reg |= wm8350_wdt_cfgs[i].val; val 603 drivers/watchdog/ziirave_wdt.c int val; val 632 drivers/watchdog/ziirave_wdt.c val = i2c_smbus_read_byte_data(client, ZIIRAVE_WDT_TIMEOUT); val 633 drivers/watchdog/ziirave_wdt.c if (val < 0) { val 635 drivers/watchdog/ziirave_wdt.c return val; val 638 drivers/watchdog/ziirave_wdt.c if (val > ZIIRAVE_TIMEOUT_MAX || val 639 drivers/watchdog/ziirave_wdt.c val < ZIIRAVE_TIMEOUT_MIN) val 640 drivers/watchdog/ziirave_wdt.c val = ZIIRAVE_TIMEOUT_DEFAULT; val 642 drivers/watchdog/ziirave_wdt.c w_priv->wdd.timeout = val; val 658 drivers/watchdog/ziirave_wdt.c val = i2c_smbus_read_byte_data(client, ZIIRAVE_WDT_STATE); val 659 drivers/watchdog/ziirave_wdt.c if (val < 0) { val 661 drivers/watchdog/ziirave_wdt.c return val; val 664 drivers/watchdog/ziirave_wdt.c if (val == ZIIRAVE_STATE_INITIAL) val 59 drivers/watchdog/zx2967_wdt.c static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val) val 61 drivers/watchdog/zx2967_wdt.c writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg); val 66 drivers/watchdog/zx2967_wdt.c u32 val; val 68 drivers/watchdog/zx2967_wdt.c val = zx2967_wdt_readl(wdt, ZX2967_WDT_REFRESH_REG); val 75 drivers/watchdog/zx2967_wdt.c val ^= ZX2967_WDT_REFRESH_MASK; val 77 drivers/watchdog/zx2967_wdt.c val & ZX2967_WDT_VAL_MASK); val 103 drivers/watchdog/zx2967_wdt.c u32 val; val 105 drivers/watchdog/zx2967_wdt.c val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG); val 106 drivers/watchdog/zx2967_wdt.c val |= ZX2967_WDT_START_EN; val 108 drivers/watchdog/zx2967_wdt.c val & ZX2967_WDT_VAL_MASK); val 113 drivers/watchdog/zx2967_wdt.c u32 val; val 115 drivers/watchdog/zx2967_wdt.c val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG); val 116 drivers/watchdog/zx2967_wdt.c val &= ~ZX2967_WDT_START_EN; val 118 drivers/watchdog/zx2967_wdt.c val & ZX2967_WDT_VAL_MASK); val 383 drivers/xen/balloon.c static int xen_memory_notifier(struct notifier_block *nb, unsigned long val, void *v) val 385 drivers/xen/balloon.c if (val == MEM_ONLINE) val 109 drivers/xen/pcpu.c unsigned long long val; val 115 drivers/xen/pcpu.c if (kstrtoull(buf, 0, &val) < 0) val 118 drivers/xen/pcpu.c switch (val) { val 139 drivers/xen/sys-hypervisor.c char *vm, *val; val 149 drivers/xen/sys-hypervisor.c val = xenbus_read(XBT_NIL, vm, "uuid", NULL); val 151 drivers/xen/sys-hypervisor.c if (IS_ERR(val)) val 152 drivers/xen/sys-hypervisor.c return PTR_ERR(val); val 153 drivers/xen/sys-hypervisor.c ret = sprintf(buffer, "%s\n", val); val 154 drivers/xen/sys-hypervisor.c kfree(val); val 425 drivers/xen/sys-hypervisor.c xp.val = pmu_modes[i].mode; val 455 drivers/xen/sys-hypervisor.c mode = (uint32_t)xp.val; val 476 drivers/xen/sys-hypervisor.c xp.val = features; val 497 drivers/xen/sys-hypervisor.c return sprintf(buffer, "0x%x\n", (uint32_t)xp.val); val 113 drivers/xen/xen-pciback/conf_space.c static inline u32 merge_value(u32 val, u32 new_val, u32 new_val_mask, val 123 drivers/xen/xen-pciback/conf_space.c val = (val & ~new_val_mask) | (new_val & new_val_mask); val 125 drivers/xen/xen-pciback/conf_space.c return val; val 16 drivers/xen/xen-pciback/conf_space_header.c u16 val; val 20 drivers/xen/xen-pciback/conf_space_header.c u32 val; val 41 drivers/xen/xen-pciback/conf_space_header.c err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val); val 56 drivers/xen/xen-pciback/conf_space_header.c *value |= cmd->val & ~PCI_COMMAND_GUEST; val 65 drivers/xen/xen-pciback/conf_space_header.c u16 val; val 99 drivers/xen/xen-pciback/conf_space_header.c if (!(cmd->val & PCI_COMMAND_INVALIDATE) && val 111 drivers/xen/xen-pciback/conf_space_header.c } else if ((cmd->val & PCI_COMMAND_INVALIDATE) && val 120 drivers/xen/xen-pciback/conf_space_header.c cmd->val = value; val 126 drivers/xen/xen-pciback/conf_space_header.c err = pci_read_config_word(dev, offset, &val); val 127 drivers/xen/xen-pciback/conf_space_header.c if (err || val == value) val 131 drivers/xen/xen-pciback/conf_space_header.c value |= val & ~PCI_COMMAND_GUEST; val 154 drivers/xen/xen-pciback/conf_space_header.c if (tmpval != bar->val && value == bar->val) { val 156 drivers/xen/xen-pciback/conf_space_header.c pci_write_config_dword(dev, offset, bar->val); val 197 drivers/xen/xen-pciback/conf_space_header.c if (tmpval != bar->val && value == bar->val) { val 199 drivers/xen/xen-pciback/conf_space_header.c pci_write_config_dword(dev, offset, bar->val); val 217 drivers/xen/xen-pciback/conf_space_header.c *value = bar->which ? bar->len_val : bar->val; val 236 drivers/xen/xen-pciback/conf_space_header.c bar->val = res[pos - 1].start >> 32; val 247 drivers/xen/xen-pciback/conf_space_header.c bar->val = res[pos].start | val 1058 drivers/xen/xen-scsiback.c char *val; val 1073 drivers/xen/xen-scsiback.c val = xenbus_read(XBT_NIL, dev->nodename, str, NULL); val 1074 drivers/xen/xen-scsiback.c if (IS_ERR(val)) { val 1082 drivers/xen/xen-scsiback.c strlcpy(phy, val, VSCSI_NAMELEN); val 1083 drivers/xen/xen-scsiback.c kfree(val); val 573 drivers/xen/xenbus/xenbus_xs.c char *val; val 575 drivers/xen/xenbus/xenbus_xs.c val = xenbus_read(t, dir, node, NULL); val 576 drivers/xen/xenbus/xenbus_xs.c if (IS_ERR(val)) val 577 drivers/xen/xenbus/xenbus_xs.c return PTR_ERR(val); val 580 drivers/xen/xenbus/xenbus_xs.c ret = vsscanf(val, fmt, ap); val 582 drivers/xen/xenbus/xenbus_xs.c kfree(val); val 594 drivers/xen/xenbus/xenbus_xs.c unsigned int val; val 597 drivers/xen/xenbus/xenbus_xs.c ret = xenbus_scanf(XBT_NIL, dir, node, "%u", &val); val 599 drivers/xen/xenbus/xenbus_xs.c val = default_val; val 601 drivers/xen/xenbus/xenbus_xs.c return val; val 261 fs/9p/vfs_super.c buf->f_fsid.val[0] = rs.fsid & 0xFFFFFFFFUL; val 262 fs/9p/vfs_super.c buf->f_fsid.val[1] = (rs.fsid >> 32) & 0xFFFFFFFFUL; val 178 fs/adfs/adfs.h static inline __u32 signed_asl(__u32 val, signed int shift) val 181 fs/adfs/adfs.h val <<= shift; val 183 fs/adfs/adfs.h val >>= -shift; val 184 fs/adfs/adfs.h return val; val 19 fs/adfs/dir_f.c unsigned int val = 0; val 22 fs/adfs/dir_f.c case 4: val |= p[3] << 24; val 24 fs/adfs/dir_f.c case 3: val |= p[2] << 16; val 26 fs/adfs/dir_f.c case 2: val |= p[1] << 8; val 28 fs/adfs/dir_f.c default: val |= p[0]; val 30 fs/adfs/dir_f.c return val; val 33 fs/adfs/dir_f.c static inline void adfs_writeval(unsigned char *p, int len, unsigned int val) val 36 fs/adfs/dir_f.c case 4: p[3] = val >> 24; val 38 fs/adfs/dir_f.c case 3: p[2] = val >> 16; val 40 fs/adfs/dir_f.c case 2: p[1] = val >> 8; val 42 fs/adfs/dir_f.c default: p[0] = val; val 263 fs/adfs/super.c buf->f_fsid.val[0] = (u32)id; val 264 fs/adfs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 281 fs/affs/affs.h affs_adjust_checksum(struct buffer_head *bh, u32 val) val 284 fs/affs/affs.h ((__be32 *)bh->b_data)[5] = cpu_to_be32(tmp - val); val 287 fs/affs/affs.h affs_adjust_bitmapchecksum(struct buffer_head *bh, u32 val) val 290 fs/affs/affs.h ((__be32 *)bh->b_data)[0] = cpu_to_be32(tmp - val); val 623 fs/affs/super.c buf->f_fsid.val[0] = (u32)id; val 624 fs/affs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 82 fs/afs/vl_list.c u16 val; val 84 fs/afs/vl_list.c val = (u16)*(*_b)++ << 0; val 85 fs/afs/vl_list.c val |= (u16)*(*_b)++ << 8; val 86 fs/afs/vl_list.c return val; val 965 fs/befs/linuxvfs.c buf->f_fsid.val[0] = (u32)id; val 966 fs/befs/linuxvfs.c buf->f_fsid.val[1] = (u32)(id >> 32); val 232 fs/bfs/inode.c buf->f_fsid.val[0] = (u32)id; val 233 fs/bfs/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 231 fs/binfmt_elf.c #define NEW_AUX_ENT(id, val) \ val 234 fs/binfmt_elf.c elf_info[ei_index++] = val; \ val 605 fs/binfmt_elf_fdpic.c #define NEW_AUX_ENT(id, val) \ val 611 fs/binfmt_elf_fdpic.c __put_user((val), &ent[nr]._val); \ val 389 fs/binfmt_flat.c unsigned long val; val 397 fs/binfmt_flat.c get_user(val, ptr); val 401 fs/binfmt_flat.c r.reloc.offset, ptr, val, segment[r.reloc.type]); val 405 fs/binfmt_flat.c val += current->mm->start_code; val 408 fs/binfmt_flat.c val += current->mm->start_data; val 411 fs/binfmt_flat.c val += current->mm->end_data; val 417 fs/binfmt_flat.c put_user(val, ptr); val 419 fs/binfmt_flat.c pr_debug("Relocation became %lx\n", val); val 956 fs/binfmt_flat.c unsigned long val = libinfo.lib_list[j].loaded ? val 961 fs/binfmt_flat.c if (put_user(val, p)) val 676 fs/btrfs/backref.c ref->parent = node ? node->val : 0; val 691 fs/btrfs/backref.c new_ref->parent = node->val; val 1430 fs/btrfs/backref.c bytenr = node->val; val 1513 fs/btrfs/backref.c bytenr = node->val; val 1936 fs/btrfs/backref.c ret = btrfs_find_all_roots_safe(trans, fs_info, ref_node->val, val 1945 fs/btrfs/backref.c root_node->val, ref_node->val, val 1950 fs/btrfs/backref.c root_node->val, val 2160 fs/btrfs/backref.c fspath_min = (char *)ipath->fspath->val + (i + 1) * s_ptr; val 2167 fs/btrfs/backref.c ipath->fspath->val[i] = (u64)(unsigned long)fspath; val 1330 fs/btrfs/ctree.h unsigned long off, u##bits val, \ val 1335 fs/btrfs/ctree.h unsigned long off, u##bits val); val 1350 fs/btrfs/ctree.h u##bits val) \ val 1353 fs/btrfs/ctree.h btrfs_set_##bits(eb, s, offsetof(type, member), val); \ val 1363 fs/btrfs/ctree.h type *s, u##bits val, \ val 1367 fs/btrfs/ctree.h btrfs_set_token_##bits(eb, s, offsetof(type, member), val, token); \ val 1378 fs/btrfs/ctree.h u##bits val) \ val 1381 fs/btrfs/ctree.h p->member = cpu_to_le##bits(val); \ val 1389 fs/btrfs/ctree.h static inline void btrfs_set_##name(type *s, u##bits val) \ val 1391 fs/btrfs/ctree.h s->member = cpu_to_le##bits(val); \ val 1405 fs/btrfs/ctree.h u64 val) val 1409 fs/btrfs/ctree.h WARN_ON(!IS_ALIGNED(val, eb->fs_info->sectorsize)); val 1410 fs/btrfs/ctree.h btrfs_set_64(eb, s, offsetof(struct btrfs_dev_item, total_bytes), val); val 1678 fs/btrfs/ctree.h int nr, u64 val) val 1683 fs/btrfs/ctree.h btrfs_set_key_blockptr(eb, (struct btrfs_key_ptr *)ptr, val); val 1695 fs/btrfs/ctree.h int nr, u64 val) val 1700 fs/btrfs/ctree.h btrfs_set_key_generation(eb, (struct btrfs_key_ptr *)ptr, val); val 1398 fs/btrfs/delayed-inode.c int val = atomic_read(&delayed_root->items_seq); val 1400 fs/btrfs/delayed-inode.c if (val < seq || val >= seq + BTRFS_DELAYED_BATCH) val 58 fs/btrfs/delayed-ref.c u64 val; val 62 fs/btrfs/delayed-ref.c val = num_entries * avg_runtime; val 63 fs/btrfs/delayed-ref.c if (val >= NSEC_PER_SEC) val 65 fs/btrfs/delayed-ref.c if (val >= NSEC_PER_SEC / 2) val 652 fs/btrfs/disk-io.c u32 val; val 657 fs/btrfs/disk-io.c read_extent_buffer(eb, &val, 0, csum_size); val 661 fs/btrfs/disk-io.c val, found, btrfs_header_level(eb)); val 413 fs/btrfs/free-space-cache.c __le64 *val; val 429 fs/btrfs/free-space-cache.c val = io_ctl->cur; val 430 fs/btrfs/free-space-cache.c *val = cpu_to_le64(generation); val 487 fs/btrfs/free-space-cache.c u32 *tmp, val; val 501 fs/btrfs/free-space-cache.c val = *tmp; val 506 fs/btrfs/free-space-cache.c if (val != crc) { val 4419 fs/btrfs/ioctl.c rel_ptr = ipath->fspath->val[i] - val 4420 fs/btrfs/ioctl.c (u64)(unsigned long)ipath->fspath->val; val 4421 fs/btrfs/ioctl.c ipath->fspath->val[i] = rel_ptr; val 4446 fs/btrfs/ioctl.c inodes->val[inodes->elem_cnt] = inum; val 4447 fs/btrfs/ioctl.c inodes->val[inodes->elem_cnt + 1] = offset; val 4448 fs/btrfs/ioctl.c inodes->val[inodes->elem_cnt + 2] = root; val 2223 fs/btrfs/qgroup.c qg = find_qgroup_rb(fs_info, unode->val); val 2412 fs/btrfs/qgroup.c return is_fstree(unode->val); val 3453 fs/btrfs/qgroup.c clear_extent_bit(&BTRFS_I(inode)->io_tree, unode->val, val 3479 fs/btrfs/qgroup.c u64 range_start = unode->val; val 3775 fs/btrfs/qgroup.c inode->i_ino, unode->val, unode->aux); val 712 fs/btrfs/scrub.c (char *)(unsigned long)ipath->fspath->val[i]); val 15 fs/btrfs/struct-funcs.c static inline void put_unaligned_le8(u8 val, void *p) val 17 fs/btrfs/struct-funcs.c *(u8 *)p = val; val 106 fs/btrfs/struct-funcs.c u##bits val, \ val 125 fs/btrfs/struct-funcs.c put_unaligned_le##bits(val, p + off); \ val 133 fs/btrfs/struct-funcs.c val2 = cpu_to_le##bits(val); \ val 138 fs/btrfs/struct-funcs.c put_unaligned_le##bits(val, p + off); \ val 143 fs/btrfs/struct-funcs.c unsigned long off, u##bits val) \ val 159 fs/btrfs/struct-funcs.c val2 = cpu_to_le##bits(val); \ val 164 fs/btrfs/struct-funcs.c put_unaligned_le##bits(val, p + off); \ val 2125 fs/btrfs/super.c buf->f_fsid.val[0] = be32_to_cpu(fsid[0]) ^ be32_to_cpu(fsid[2]); val 2126 fs/btrfs/super.c buf->f_fsid.val[1] = be32_to_cpu(fsid[1]) ^ be32_to_cpu(fsid[3]); val 2128 fs/btrfs/super.c buf->f_fsid.val[0] ^= val 2130 fs/btrfs/super.c buf->f_fsid.val[1] ^= val 114 fs/btrfs/sysfs.c int val = 0; val 136 fs/btrfs/sysfs.c val |= 1; val 138 fs/btrfs/sysfs.c val |= 2; val 140 fs/btrfs/sysfs.c return val; val 146 fs/btrfs/sysfs.c int val = 0; val 152 fs/btrfs/sysfs.c val = 1; val 154 fs/btrfs/sysfs.c val = can_modify_feature(fa); val 156 fs/btrfs/sysfs.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 166 fs/btrfs/sysfs.c unsigned long val; val 176 fs/btrfs/sysfs.c ret = kstrtoul(skip_spaces(buf), 0, &val); val 194 fs/btrfs/sysfs.c if ((val && (features & fa->feature_bit)) || val 195 fs/btrfs/sysfs.c (!val && !(features & fa->feature_bit))) val 198 fs/btrfs/sysfs.c if ((val && !(set & fa->feature_bit)) || val 199 fs/btrfs/sysfs.c (!val && !(clear & fa->feature_bit))) { val 202 fs/btrfs/sysfs.c val ? "En" : "Dis", fa->kobj_attr.attr.name); val 207 fs/btrfs/sysfs.c val ? "Setting" : "Clearing", fa->kobj_attr.attr.name); val 211 fs/btrfs/sysfs.c if (val) val 335 fs/btrfs/sysfs.c u64 val; val 338 fs/btrfs/sysfs.c val = *value_ptr; val 341 fs/btrfs/sysfs.c return snprintf(buf, PAGE_SIZE, "%llu\n", val); val 377 fs/btrfs/sysfs.c u64 val = 0; val 382 fs/btrfs/sysfs.c val += block_group->key.offset; val 384 fs/btrfs/sysfs.c val += btrfs_block_group_used(&block_group->item); val 387 fs/btrfs/sysfs.c return snprintf(buf, PAGE_SIZE, "%llu\n", val); val 423 fs/btrfs/sysfs.c s64 val = percpu_counter_sum(&sinfo->total_bytes_pinned); val 424 fs/btrfs/sysfs.c return snprintf(buf, PAGE_SIZE, "%lld\n", val); val 118 fs/btrfs/ulist.c static struct ulist_node *ulist_rbtree_search(struct ulist *ulist, u64 val) val 125 fs/btrfs/ulist.c if (u->val < val) val 127 fs/btrfs/ulist.c else if (u->val > val) val 154 fs/btrfs/ulist.c if (cur->val < ins->val) val 156 fs/btrfs/ulist.c else if (cur->val > ins->val) val 186 fs/btrfs/ulist.c int ulist_add(struct ulist *ulist, u64 val, u64 aux, gfp_t gfp_mask) val 188 fs/btrfs/ulist.c return ulist_add_merge(ulist, val, aux, NULL, gfp_mask); val 191 fs/btrfs/ulist.c int ulist_add_merge(struct ulist *ulist, u64 val, u64 aux, val 197 fs/btrfs/ulist.c node = ulist_rbtree_search(ulist, val); val 207 fs/btrfs/ulist.c node->val = val; val 228 fs/btrfs/ulist.c int ulist_del(struct ulist *ulist, u64 val, u64 aux) val 232 fs/btrfs/ulist.c node = ulist_rbtree_search(ulist, val); val 28 fs/btrfs/ulist.h u64 val; /* value to store */ val 50 fs/btrfs/ulist.h int ulist_add(struct ulist *ulist, u64 val, u64 aux, gfp_t gfp_mask); val 51 fs/btrfs/ulist.h int ulist_add_merge(struct ulist *ulist, u64 val, u64 aux, val 53 fs/btrfs/ulist.h int ulist_del(struct ulist *ulist, u64 val, u64 aux); val 56 fs/btrfs/ulist.h static inline int ulist_add_merge_ptr(struct ulist *ulist, u64 val, void *aux, val 61 fs/btrfs/ulist.h int ret = ulist_add_merge(ulist, val, (uintptr_t)aux, &old64, gfp_mask); val 65 fs/btrfs/ulist.h return ulist_add_merge(ulist, val, (u64)aux, (u64 *)old_aux, gfp_mask); val 7351 fs/btrfs/volumes.c u64 val; val 7353 fs/btrfs/volumes.c read_extent_buffer(eb, &val, val 7356 fs/btrfs/volumes.c sizeof(val)); val 7357 fs/btrfs/volumes.c return val; val 7362 fs/btrfs/volumes.c int index, u64 val) val 7364 fs/btrfs/volumes.c write_extent_buffer(eb, &val, val 7367 fs/btrfs/volumes.c sizeof(val)); val 536 fs/btrfs/volumes.h int index, unsigned long val) val 538 fs/btrfs/volumes.h atomic_set(dev->dev_stat_values + index, val); val 217 fs/ceph/debugfs.c static int congestion_kb_set(void *data, u64 val) val 221 fs/ceph/debugfs.c fsc->mount_options->congestion_kb = (int)val; val 225 fs/ceph/debugfs.c static int congestion_kb_get(void *data, u64 *val) val 229 fs/ceph/debugfs.c *val = (u64)fsc->mount_options->congestion_kb; val 2016 fs/ceph/mds_client.c int val; val 2019 fs/ceph/mds_client.c val = atomic_add_return(nr, &mdsc->cap_reclaim_pending); val 2020 fs/ceph/mds_client.c if (!(val % CEPH_CAPS_PER_RELEASE)) { val 103 fs/ceph/super.c buf->f_fsid.val[0] = fsid & 0xffffffff; val 104 fs/ceph/super.c buf->f_fsid.val[1] = fsid >> 32; val 259 fs/ceph/super.h const char *val; val 36 fs/ceph/xattr.c ssize_t (*getxattr_cb)(struct ceph_inode_info *ci, char *val, val 56 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_layout(struct ceph_inode_info *ci, char *val, val 93 fs/ceph/xattr.c memcpy(val, buf, len); val 97 fs/ceph/xattr.c memcpy(val + ret, pool_name, len); val 102 fs/ceph/xattr.c memcpy(val + ret, ns_field, len); val 104 fs/ceph/xattr.c memcpy(val + ret, pool_ns->str, pool_ns->len); val 119 fs/ceph/xattr.c static int ceph_fmt_xattr(char *val, size_t size, const char *fmt, ...) val 136 fs/ceph/xattr.c memcpy(val, buf, ret); val 141 fs/ceph/xattr.c char *val, size_t size) val 143 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%u", ci->i_layout.stripe_unit); val 147 fs/ceph/xattr.c char *val, size_t size) val 149 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%u", ci->i_layout.stripe_count); val 153 fs/ceph/xattr.c char *val, size_t size) val 155 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%u", ci->i_layout.object_size); val 159 fs/ceph/xattr.c char *val, size_t size) val 172 fs/ceph/xattr.c memcpy(val, pool_name, ret); val 174 fs/ceph/xattr.c ret = ceph_fmt_xattr(val, size, "%lld", pool); val 181 fs/ceph/xattr.c char *val, size_t size) val 189 fs/ceph/xattr.c memcpy(val, ns->str, ret); val 197 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_entries(struct ceph_inode_info *ci, char *val, val 200 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld", ci->i_files + ci->i_subdirs); val 203 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_files(struct ceph_inode_info *ci, char *val, val 206 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld", ci->i_files); val 209 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_subdirs(struct ceph_inode_info *ci, char *val, val 212 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld", ci->i_subdirs); val 215 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_rentries(struct ceph_inode_info *ci, char *val, val 218 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld", val 222 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_rfiles(struct ceph_inode_info *ci, char *val, val 225 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld", ci->i_rfiles); val 228 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_rsubdirs(struct ceph_inode_info *ci, char *val, val 231 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld", ci->i_rsubdirs); val 234 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_rbytes(struct ceph_inode_info *ci, char *val, val 237 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld", ci->i_rbytes); val 240 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_rctime(struct ceph_inode_info *ci, char *val, val 243 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld.%09ld", ci->i_rctime.tv_sec, val 253 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_dir_pin(struct ceph_inode_info *ci, char *val, val 256 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%d", (int)ci->i_dir_pin); val 273 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_quota(struct ceph_inode_info *ci, char *val, val 276 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "max_bytes=%llu max_files=%llu", val 281 fs/ceph/xattr.c char *val, size_t size) val 283 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%llu", ci->i_max_bytes); val 287 fs/ceph/xattr.c char *val, size_t size) val 289 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%llu", ci->i_max_files); val 298 fs/ceph/xattr.c static ssize_t ceph_vxattrcb_snap_btime(struct ceph_inode_info *ci, char *val, val 301 fs/ceph/xattr.c return ceph_fmt_xattr(val, size, "%lld.%09ld", ci->i_snap_btime.tv_sec, val 435 fs/ceph/xattr.c const char *val, int val_len, val 474 fs/ceph/xattr.c kfree(val); val 500 fs/ceph/xattr.c kfree((void *)xattr->val); val 511 fs/ceph/xattr.c if (val) val 512 fs/ceph/xattr.c xattr->val = val; val 514 fs/ceph/xattr.c xattr->val = ""; val 518 fs/ceph/xattr.c xattr->should_free_val = (val && update_xattr); val 527 fs/ceph/xattr.c ceph_vinop(&ci->vfs_inode), xattr, name_len, name, val_len, val); val 554 fs/ceph/xattr.c xattr->val_len, xattr->val); val 571 fs/ceph/xattr.c kfree((void *)xattr->val); val 587 fs/ceph/xattr.c kfree((void *)xattr->val); val 656 fs/ceph/xattr.c const char *name, *val; val 709 fs/ceph/xattr.c val = p; val 712 fs/ceph/xattr.c err = __set_xattr(ci, name, namelen, val, len, val 786 fs/ceph/xattr.c memcpy(dest, xattr->val, xattr->val_len); val 893 fs/ceph/xattr.c memcpy(value, xattr->val, xattr->val_len); val 119 fs/cifs/asn1.c asn1_enum_decode(struct asn1_ctx *ctx, __le32 *val) val 130 fs/cifs/asn1.c *val = *(++(ctx->pointer)); /* value has enum value */ val 270 fs/cifs/cifsfs.c buf->f_fsid.val[0] = tcon->vol_serial_number; val 272 fs/cifs/cifsfs.c buf->f_fsid.val[1] = (int)le64_to_cpu(tcon->vol_create_time); val 248 fs/cifs/cifsglob.h const unsigned int val); val 815 fs/cifs/cifsglob.h set_credits(struct TCP_Server_Info *server, const int val) val 817 fs/cifs/cifsglob.h server->ops->set_credits(server, val); val 846 fs/cifs/cifsglob.h revert_current_mid(struct TCP_Server_Info *server, const unsigned int val) val 849 fs/cifs/cifsglob.h server->ops->revert_current_mid(server, val); val 601 fs/cifs/cifssmb.c int val, seconds, remain, result; val 609 fs/cifs/cifssmb.c val = (int)(utc - ts.tv_sec); val 610 fs/cifs/cifssmb.c seconds = abs(val); val 615 fs/cifs/cifssmb.c if (val < 0) val 776 fs/cifs/connect.c int val; val 779 fs/cifs/connect.c val = server->credits + server->echo_credits + server->oplock_credits; val 780 fs/cifs/connect.c if (server->in_flight == 0 && val == 0) { val 3920 fs/cifs/connect.c int val = 1; val 3922 fs/cifs/connect.c (char *)&val, sizeof(val)); val 119 fs/cifs/smb1ops.c cifs_set_credits(struct TCP_Server_Info *server, const int val) val 122 fs/cifs/smb1ops.c server->credits = val; val 123 fs/cifs/smb1ops.c server->oplocks = val > 1 ? enable_oplocks : false; val 61 fs/cifs/smb2ops.c int *val, rc = -1; val 67 fs/cifs/smb2ops.c val = server->ops->get_credits_field(server, optype); val 70 fs/cifs/smb2ops.c if (((optype & CIFS_OP_MASK) == CIFS_NEG_OP) && (*val != 0)) val 72 fs/cifs/smb2ops.c server->hostname, *val); val 74 fs/cifs/smb2ops.c *val += add; val 78 fs/cifs/smb2ops.c if (*val > 65000) { val 79 fs/cifs/smb2ops.c *val = 65000; /* Don't get near 64K credits, avoid srv bugs */ val 126 fs/cifs/smb2ops.c smb2_set_credits(struct TCP_Server_Info *server, const int val) val 129 fs/cifs/smb2ops.c server->credits = val; val 130 fs/cifs/smb2ops.c if (val == 1) val 134 fs/cifs/smb2ops.c if (val == 1) val 253 fs/cifs/smb2ops.c smb2_revert_current_mid(struct TCP_Server_Info *server, const unsigned int val) val 256 fs/cifs/smb2ops.c if (server->CurrentMid >= val) val 257 fs/cifs/smb2ops.c server->CurrentMid -= val; val 38 fs/cifs/smbencrypt.c #define SSVALX(buf,pos,val) (CVAL(buf,pos)=(val)&0xFF,CVAL(buf,pos+1)=(val)>>8) val 39 fs/cifs/smbencrypt.c #define SSVAL(buf,pos,val) SSVALX((buf),(pos),((__u16)(val))) val 328 fs/cifs/transport.c int val = 1; val 349 fs/cifs/transport.c (char *)&val, sizeof(val)); val 438 fs/cifs/transport.c val = 0; val 440 fs/cifs/transport.c (char *)&val, sizeof(val)); val 77 fs/compat_ioctl.c typeof(*srcptr) val; \ val 79 fs/compat_ioctl.c get_user(val, srcptr) || put_user(val, dstptr); \ val 693 fs/cramfs/inode.c buf->f_fsid.val[0] = (u32)id; val 694 fs/cramfs/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 409 fs/debugfs/file.c static int debugfs_u8_set(void *data, u64 val) val 411 fs/debugfs/file.c *(u8 *)data = val; val 414 fs/debugfs/file.c static int debugfs_u8_get(void *data, u64 *val) val 416 fs/debugfs/file.c *val = *(u8 *)data; val 454 fs/debugfs/file.c static int debugfs_u16_set(void *data, u64 val) val 456 fs/debugfs/file.c *(u16 *)data = val; val 459 fs/debugfs/file.c static int debugfs_u16_get(void *data, u64 *val) val 461 fs/debugfs/file.c *val = *(u16 *)data; val 499 fs/debugfs/file.c static int debugfs_u32_set(void *data, u64 val) val 501 fs/debugfs/file.c *(u32 *)data = val; val 504 fs/debugfs/file.c static int debugfs_u32_get(void *data, u64 *val) val 506 fs/debugfs/file.c *val = *(u32 *)data; val 544 fs/debugfs/file.c static int debugfs_u64_set(void *data, u64 val) val 546 fs/debugfs/file.c *(u64 *)data = val; val 550 fs/debugfs/file.c static int debugfs_u64_get(void *data, u64 *val) val 552 fs/debugfs/file.c *val = *(u64 *)data; val 590 fs/debugfs/file.c static int debugfs_ulong_set(void *data, u64 val) val 592 fs/debugfs/file.c *(unsigned long *)data = val; val 596 fs/debugfs/file.c static int debugfs_ulong_get(void *data, u64 *val) val 598 fs/debugfs/file.c *val = *(unsigned long *)data; val 739 fs/debugfs/file.c static int debugfs_size_t_set(void *data, u64 val) val 741 fs/debugfs/file.c *(size_t *)data = val; val 744 fs/debugfs/file.c static int debugfs_size_t_get(void *data, u64 *val) val 746 fs/debugfs/file.c *val = *(size_t *)data; val 773 fs/debugfs/file.c static int debugfs_atomic_t_set(void *data, u64 val) val 775 fs/debugfs/file.c atomic_set((atomic_t *)data, val); val 778 fs/debugfs/file.c static int debugfs_atomic_t_get(void *data, u64 *val) val 780 fs/debugfs/file.c *val = atomic_read((atomic_t *)data); val 814 fs/debugfs/file.c bool val; val 821 fs/debugfs/file.c val = *(bool *)file->private_data; val 824 fs/debugfs/file.c if (val) val 839 fs/debugfs/file.c bool *val = file->private_data; val 847 fs/debugfs/file.c *val = bv; val 93 fs/dlm/lockspace.c int val; val 94 fs/dlm/lockspace.c int rc = kstrtoint(buf, 0, &val); val 98 fs/dlm/lockspace.c if (val == 1) val 344 fs/efs/super.c buf->f_fsid.val[0] = (u32)id; val 345 fs/efs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 124 fs/erofs/internal.h int val) val 127 fs/erofs/internal.h if (val != atomic_cmpxchg(&grp->refcount, val, EROFS_LOCKED_MAGIC)) { val 153 fs/erofs/internal.h int val) val 157 fs/erofs/internal.h if (val != atomic_read(&grp->refcount)) { val 541 fs/erofs/super.c buf->f_fsid.val[0] = (u32)id; val 542 fs/erofs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 48 fs/erofs/tagptr.h #define tagptr_init(type, val) \ val 49 fs/erofs/tagptr.h ((typeof(type)){ .v = (uintptr_t)(val) }) val 1474 fs/ext2/super.c buf->f_fsid.val[0] = fsid & 0xFFFFFFFFUL; val 1475 fs/ext2/super.c buf->f_fsid.val[1] = (fsid >> 32) & 0xFFFFFFFFUL; val 574 fs/ext2/xattr.c char *val = (char *)header + offs; val 582 fs/ext2/xattr.c memset(val + size - EXT2_XATTR_PAD, 0, val 584 fs/ext2/xattr.c memcpy(val, value, value_len); val 589 fs/ext2/xattr.c memmove(first_val + size, first_val, val - first_val); val 619 fs/ext2/xattr.c char *val = (char *)header + min_offs - size; val 621 fs/ext2/xattr.c cpu_to_le16((char *)val - (char *)header); val 622 fs/ext2/xattr.c memset(val + size - EXT2_XATTR_PAD, 0, val 624 fs/ext2/xattr.c memcpy(val, value, value_len); val 137 fs/ext4/hash.c __u32 pad, val; val 144 fs/ext4/hash.c val = pad; val 148 fs/ext4/hash.c val = ((int) scp[i]) + (val << 8); val 150 fs/ext4/hash.c *buf++ = val; val 151 fs/ext4/hash.c val = pad; val 156 fs/ext4/hash.c *buf++ = val; val 163 fs/ext4/hash.c __u32 pad, val; val 170 fs/ext4/hash.c val = pad; val 174 fs/ext4/hash.c val = ((int) ucp[i]) + (val << 8); val 176 fs/ext4/hash.c *buf++ = val; val 177 fs/ext4/hash.c val = pad; val 182 fs/ext4/hash.c *buf++ = val; val 4813 fs/ext4/inode.c static inline void ext4_inode_set_iversion_queried(struct inode *inode, u64 val) val 4816 fs/ext4/inode.c inode_set_iversion_raw(inode, val); val 4818 fs/ext4/inode.c inode_set_iversion_queried(inode, val); val 6145 fs/ext4/inode.c int ext4_change_inode_journal_flag(struct inode *inode, int val) val 6179 fs/ext4/inode.c if (val) { val 6199 fs/ext4/inode.c if (val) val 6215 fs/ext4/inode.c if (val) val 5654 fs/ext4/super.c buf->f_fsid.val[0] = fsid & 0xFFFFFFFFUL; val 5655 fs/ext4/super.c buf->f_fsid.val[1] = (fsid >> 32) & 0xFFFFFFFFUL; val 100 fs/ext4/sysfs.c unsigned long long val; val 105 fs/ext4/sysfs.c ret = kstrtoull(skip_spaces(buf), 0, &val); val 106 fs/ext4/sysfs.c if (ret || val >= clusters) val 109 fs/ext4/sysfs.c atomic64_set(&sbi->s_resv_clusters, val); val 1585 fs/ext4/xattr.c void *val = s->base + offs; val 1589 fs/ext4/xattr.c memset(val, 0, new_size); val 1591 fs/ext4/xattr.c memcpy(val, i->value, i->value_len); val 1593 fs/ext4/xattr.c memset(val + i->value_len, 0, new_size - i->value_len); val 1703 fs/ext4/xattr.c void *val = s->base + offs; val 1705 fs/ext4/xattr.c memmove(first_val + old_size, first_val, val - first_val); val 1751 fs/ext4/xattr.c void *val = s->base + min_offs - new_size; val 1755 fs/ext4/xattr.c memset(val, 0, new_size); val 1757 fs/ext4/xattr.c memcpy(val, i->value, i->value_len); val 1759 fs/ext4/xattr.c memset(val + i->value_len, 0, val 3146 fs/f2fs/f2fs.h unsigned int val, int alloc); val 46 fs/f2fs/hash.c unsigned pad, val; val 52 fs/f2fs/hash.c val = pad; val 57 fs/f2fs/hash.c val = pad; val 58 fs/f2fs/hash.c val = msg[i] + (val << 8); val 60 fs/f2fs/hash.c *buf++ = val; val 61 fs/f2fs/hash.c val = pad; val 66 fs/f2fs/hash.c *buf++ = val; val 47 fs/f2fs/node.c struct sysinfo val; val 52 fs/f2fs/node.c si_meminfo(&val); val 55 fs/f2fs/node.c avail_ram = val.totalram - val.totalhigh; val 92 fs/f2fs/node.c res = mem_size < (val.totalram / 5); val 3692 fs/f2fs/segment.c unsigned int val, int alloc) val 3698 fs/f2fs/segment.c if (le32_to_cpu(nid_in_journal(journal, i)) == val) val 3705 fs/f2fs/segment.c if (le32_to_cpu(segno_in_journal(journal, i)) == val) val 1288 fs/f2fs/super.c buf->f_fsid.val[0] = (u32)id; val 1289 fs/f2fs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 839 fs/fat/inode.c buf->f_fsid.val[0] = (u32)id; val 840 fs/fat/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 21 fs/fscache/page.c void *val; val 24 fs/fscache/page.c val = radix_tree_lookup(&cookie->stores, page->index); val 26 fs/fscache/page.c trace_fscache_check_page(cookie, page, val, 0); val 28 fs/fscache/page.c return val != NULL; val 67 fs/fscache/page.c void *val; val 75 fs/fscache/page.c val = radix_tree_lookup(&cookie->stores, page->index); val 76 fs/fscache/page.c if (!val) { val 150 fs/fscache/page.c struct page *xpage = NULL, *val; val 168 fs/fscache/page.c val = radix_tree_lookup(&cookie->stores, page->index); val 169 fs/fscache/page.c trace_fscache_check_page(cookie, page, val, 1); val 68 fs/fuse/control.c size_t len, loff_t *ppos, unsigned val) val 71 fs/fuse/control.c size_t size = sprintf(tmp, "%u\n", val); val 77 fs/fuse/control.c size_t count, loff_t *ppos, unsigned *val, val 97 fs/fuse/control.c *val = t; val 107 fs/fuse/control.c unsigned val; val 113 fs/fuse/control.c val = READ_ONCE(fc->max_background); val 116 fs/fuse/control.c return fuse_conn_limit_read(file, buf, len, ppos, val); val 123 fs/fuse/control.c unsigned uninitialized_var(val); val 126 fs/fuse/control.c ret = fuse_conn_limit_write(file, buf, count, ppos, &val, val 132 fs/fuse/control.c fc->max_background = val; val 149 fs/fuse/control.c unsigned val; val 155 fs/fuse/control.c val = READ_ONCE(fc->congestion_threshold); val 158 fs/fuse/control.c return fuse_conn_limit_read(file, buf, len, ppos, val); val 165 fs/fuse/control.c unsigned uninitialized_var(val); val 169 fs/fuse/control.c ret = fuse_conn_limit_write(file, buf, count, ppos, &val, val 178 fs/fuse/control.c fc->congestion_threshold = val; val 220 fs/fuse/cuse.c char *key, *val; val 232 fs/fuse/cuse.c key = val = p; val 236 fs/fuse/cuse.c strsep(&val, "="); val 237 fs/fuse/cuse.c if (!val) val 238 fs/fuse/cuse.c val = key + strlen(key); val 240 fs/fuse/cuse.c val = strstrip(val); val 252 fs/fuse/cuse.c *valp = val; val 273 fs/fuse/cuse.c char *uninitialized_var(key), *uninitialized_var(val); val 277 fs/fuse/cuse.c rc = cuse_parse_one(&p, end, &key, &val); val 283 fs/fuse/cuse.c devinfo->name = val; val 742 fs/fuse/dev.c static int fuse_copy_do(struct fuse_copy_state *cs, void **val, unsigned *size) val 745 fs/fuse/dev.c if (val) { val 750 fs/fuse/dev.c memcpy(buf, *val, ncpy); val 752 fs/fuse/dev.c memcpy(*val, buf, ncpy); val 755 fs/fuse/dev.c *val += ncpy; val 971 fs/fuse/dev.c static int fuse_copy_one(struct fuse_copy_state *cs, void *val, unsigned size) val 979 fs/fuse/dev.c fuse_copy_do(cs, &val, &size); val 35 fs/fuse/inode.c static int set_global_limit(const char *val, const struct kernel_param *kp); val 838 fs/fuse/inode.c static int set_global_limit(const char *val, const struct kernel_param *kp) val 842 fs/fuse/inode.c rv = param_set_uint(val, kp); val 1045 fs/gfs2/super.c int val; val 1100 fs/gfs2/super.c val = sdp->sd_tune.gt_logd_secs; val 1101 fs/gfs2/super.c if (val != 30) val 1102 fs/gfs2/super.c seq_printf(s, ",commit=%d", val); val 1103 fs/gfs2/super.c val = sdp->sd_tune.gt_statfs_quantum; val 1104 fs/gfs2/super.c if (val != 30) val 1105 fs/gfs2/super.c seq_printf(s, ",statfs_quantum=%d", val); val 1108 fs/gfs2/super.c val = sdp->sd_tune.gt_quota_quantum; val 1109 fs/gfs2/super.c if (val != 60) val 1110 fs/gfs2/super.c seq_printf(s, ",quota_quantum=%d", val); val 127 fs/gfs2/sys.c int error, val; val 132 fs/gfs2/sys.c error = kstrtoint(buf, 0, &val); val 136 fs/gfs2/sys.c if (val != 1) val 147 fs/gfs2/sys.c int error, val; val 152 fs/gfs2/sys.c error = kstrtoint(buf, 0, &val); val 156 fs/gfs2/sys.c if (val != 1) val 166 fs/gfs2/sys.c int error, val; val 171 fs/gfs2/sys.c error = kstrtoint(buf, 0, &val); val 175 fs/gfs2/sys.c if (val != 1) val 329 fs/gfs2/sys.c int val = 0; val 332 fs/gfs2/sys.c val = 1; val 333 fs/gfs2/sys.c ret = sprintf(buf, "%d\n", val); val 340 fs/gfs2/sys.c int ret, val; val 342 fs/gfs2/sys.c ret = kstrtoint(buf, 0, &val); val 346 fs/gfs2/sys.c if (val == 1) val 348 fs/gfs2/sys.c else if (val == 0) { val 360 fs/gfs2/sys.c int val = completion_done(&sdp->sd_wdack) ? 1 : 0; val 362 fs/gfs2/sys.c return sprintf(buf, "%d\n", val); val 367 fs/gfs2/sys.c int ret, val; val 369 fs/gfs2/sys.c ret = kstrtoint(buf, 0, &val); val 373 fs/gfs2/sys.c if ((val == 1) && val 33 fs/hfs/bitmap.c __be32 val; val 44 fs/hfs/bitmap.c val = *curr; val 45 fs/hfs/bitmap.c if (~val) { val 46 fs/hfs/bitmap.c n = be32_to_cpu(val); val 57 fs/hfs/bitmap.c val = *curr; val 58 fs/hfs/bitmap.c if (~val) { val 59 fs/hfs/bitmap.c n = be32_to_cpu(val); val 107 fs/hfs/super.c buf->f_fsid.val[0] = (u32)id; val 108 fs/hfs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 27 fs/hfsplus/bitmap.c __be32 val; val 52 fs/hfsplus/bitmap.c val = *curr; val 53 fs/hfsplus/bitmap.c if (~val) { val 54 fs/hfsplus/bitmap.c n = be32_to_cpu(val); val 66 fs/hfsplus/bitmap.c val = *curr; val 67 fs/hfsplus/bitmap.c if (~val) { val 68 fs/hfsplus/bitmap.c n = be32_to_cpu(val); val 323 fs/hfsplus/super.c buf->f_fsid.val[0] = (u32)id; val 324 fs/hfsplus/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 195 fs/hpfs/super.c buf->f_fsid.val[0] = (u32)id; val 196 fs/hpfs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 1046 fs/isofs/inode.c buf->f_fsid.val[0] = (u32)id; val 1047 fs/isofs/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 220 fs/jffs2/fs.c buf->f_fsid.val[0] = JFFS2_SUPER_MAGIC; val 221 fs/jffs2/fs.c buf->f_fsid.val[1] = c->mtd->index; val 146 fs/jfs/super.c buf->f_fsid.val[0] = crc32_le(0, (char *)&sbi->uuid, val 148 fs/jfs/super.c buf->f_fsid.val[1] = crc32_le(0, val 336 fs/jfs/super.c uid_t val; val 337 fs/jfs/super.c int rc = kstrtouint(uid, 0, &val); val 341 fs/jfs/super.c sbi->uid = make_kuid(current_user_ns(), val); val 350 fs/jfs/super.c gid_t val; val 351 fs/jfs/super.c int rc = kstrtouint(gid, 0, &val); val 355 fs/jfs/super.c sbi->gid = make_kgid(current_user_ns(), val); val 869 fs/libfs.c u64 val; val 870 fs/libfs.c ret = attr->get(attr->data, &val); val 875 fs/libfs.c attr->fmt, (unsigned long long)val); val 890 fs/libfs.c u64 val; val 908 fs/libfs.c val = simple_strtoll(attr->set_buf, NULL, 0); val 909 fs/libfs.c ret = attr->set(attr->data, val); val 624 fs/lockd/svc.c static int param_set_##name(const char *val, const struct kernel_param *kp) \ val 627 fs/lockd/svc.c __typeof__(type) num = which_strtol(val, &endp, 0); \ val 628 fs/lockd/svc.c if (endp == val || *endp || num < (min) || num > (max)) \ val 366 fs/minix/inode.c buf->f_fsid.val[0] = (u32)id; val 367 fs/minix/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 166 fs/nfs/nfs4idmap.c unsigned long val; val 173 fs/nfs/nfs4idmap.c if (kstrtoul(buf, 0, &val) != 0) val 175 fs/nfs/nfs4idmap.c *res = val; val 5615 fs/nfs/nfs4xdr.c u32 nr_attrs, val; val 5620 fs/nfs/nfs4xdr.c val = be32_to_cpup(p++); /* headerpadsz */ val 5621 fs/nfs/nfs4xdr.c if (val) val 2965 fs/nfs/super.c static int param_set_portnr(const char *val, const struct kernel_param *kp) val 2970 fs/nfs/super.c if (!val) val 2972 fs/nfs/super.c ret = kstrtoul(val, 0, &num); val 204 fs/nfsd/blocklayoutxdr.c u64 val; val 206 fs/nfsd/blocklayoutxdr.c p = xdr_decode_hyper(p, &val); val 207 fs/nfsd/blocklayoutxdr.c if (val & (block_size - 1)) { val 208 fs/nfsd/blocklayoutxdr.c dprintk("%s: unaligned offset 0x%llx\n", __func__, val); val 211 fs/nfsd/blocklayoutxdr.c iomaps[i].offset = val; val 213 fs/nfsd/blocklayoutxdr.c p = xdr_decode_hyper(p, &val); val 214 fs/nfsd/blocklayoutxdr.c if (val & (block_size - 1)) { val 215 fs/nfsd/blocklayoutxdr.c dprintk("%s: unaligned length 0x%llx\n", __func__, val); val 218 fs/nfsd/blocklayoutxdr.c iomaps[i].length = val; val 32 fs/nfsd/fault_inject.c static u64 val; val 39 fs/nfsd/fault_inject.c val = op->get(); val 40 fs/nfsd/fault_inject.c size = scnprintf(read_buf, sizeof(read_buf), "%llu\n", val); val 53 fs/nfsd/fault_inject.c u64 val; val 69 fs/nfsd/fault_inject.c val = op->set_clnt(&sa, size); val 70 fs/nfsd/fault_inject.c if (val) val 72 fs/nfsd/fault_inject.c op->file, write_buf, val); val 74 fs/nfsd/fault_inject.c val = simple_strtoll(write_buf, NULL, 0); val 75 fs/nfsd/fault_inject.c if (val == 0) val 79 fs/nfsd/fault_inject.c op->file, val); val 80 fs/nfsd/fault_inject.c val = op->set_val(val); val 81 fs/nfsd/fault_inject.c pr_info("NFSD: %s: found %llu", op->file, val); val 169 fs/nfsd/trace.h #define show_nf_flags(val) \ val 170 fs/nfsd/trace.h __print_flags(val, "|", \ val 178 fs/nfsd/trace.h #define show_nf_may(val) \ val 179 fs/nfsd/trace.h __print_flags(val, "|", \ val 650 fs/nilfs2/super.c buf->f_fsid.val[0] = (u32)id; val 651 fs/nilfs2/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 1195 fs/nilfs2/super.c unsigned long long val; val 1204 fs/nilfs2/super.c err = kstrtoull(arg->from, 0, &val); val 1211 fs/nilfs2/super.c } else if (val == 0) { val 1215 fs/nilfs2/super.c sd->cno = val; val 777 fs/nilfs2/sysfs.c unsigned int val; val 780 fs/nilfs2/sysfs.c err = kstrtouint(skip_spaces(buf), 0, &val); val 787 fs/nilfs2/sysfs.c if (val < NILFS_SB_FREQ) { val 788 fs/nilfs2/sysfs.c val = NILFS_SB_FREQ; val 794 fs/nilfs2/sysfs.c nilfs->ns_sb_update_freq = val; val 257 fs/notify/fanotify/fanotify.c fsid->val[0], fsid->val[1], type, bytes, err); val 377 fs/notify/fanotify/fanotify.c if (WARN_ON_ONCE(!fsid.val[0] && !fsid.val[1])) val 438 fs/notify/fanotify/fanotify.c if (!fsid.val[0] && !fsid.val[1]) val 50 fs/notify/fanotify/fanotify.h return fid1->fsid.val[0] == fid2->fsid.val[0] && val 51 fs/notify/fanotify/fanotify.h fid1->fsid.val[1] == fid2->fsid.val[1] && val 902 fs/notify/fanotify/fanotify_user.c if (!fsid->val[0] && !fsid->val[1]) val 913 fs/notify/fanotify/fanotify_user.c if (root_fsid.val[0] != fsid->val[0] || val 914 fs/notify/fanotify/fanotify_user.c root_fsid.val[1] != fsid->val[1]) val 491 fs/notify/mark.c conn->fsid.val[0] = conn->fsid.val[1] = 0; val 556 fs/notify/mark.c if (fsid && WARN_ON_ONCE(!fsid->val[0] && !fsid->val[1])) val 574 fs/notify/mark.c (fsid->val[0] != conn->fsid.val[0] || val 575 fs/notify/mark.c fsid->val[1] != conn->fsid.val[1])) { val 585 fs/notify/mark.c fsid->val[0], fsid->val[1], val 586 fs/notify/mark.c conn->fsid.val[0], conn->fsid.val[1]); val 577 fs/ntfs/attrib.c const u8 *val, const u32 val_len, ntfs_attr_search_ctx *ctx) val 648 fs/ntfs/attrib.c if (!val) val 654 fs/ntfs/attrib.c rc = memcmp(val, (u8*)a + le16_to_cpu( val 846 fs/ntfs/attrib.c const u8 *val, const u32 val_len, ntfs_attr_search_ctx *ctx) val 1057 fs/ntfs/attrib.c if (!val || (!a->non_resident && le32_to_cpu( val 1061 fs/ntfs/attrib.c val, val_len))) { val 1093 fs/ntfs/attrib.c return ntfs_attr_find(AT_END, name, name_len, ic, val, val_len, val 1127 fs/ntfs/attrib.c err = ntfs_attr_find(type, name, name_len, ic, val, val_len, val 1175 fs/ntfs/attrib.c const VCN lowest_vcn, const u8 *val, const u32 val_len, val 1189 fs/ntfs/attrib.c return ntfs_attr_find(type, name, name_len, ic, val, val_len, val 1192 fs/ntfs/attrib.c val, val_len, ctx); val 2479 fs/ntfs/attrib.c int ntfs_attr_set(ntfs_inode *ni, const s64 ofs, const s64 cnt, const u8 val) val 2489 fs/ntfs/attrib.c (long long)ofs, (long long)cnt, val); val 2529 fs/ntfs/attrib.c memset(kaddr + start_ofs, val, size - start_ofs); val 2550 fs/ntfs/attrib.c memset(kaddr, val, PAGE_SIZE); val 2587 fs/ntfs/attrib.c memset(kaddr, val, end_ofs); val 61 fs/ntfs/attrib.h const VCN lowest_vcn, const u8 *val, const u32 val_len, val 98 fs/ntfs/attrib.h const u8 val); val 2300 fs/ntfs/inode.c for (i = 0; on_errors_arr[i].val; i++) { val 2301 fs/ntfs/inode.c if (on_errors_arr[i].val & vol->on_errors) val 83 fs/ntfs/ntfs.h int val; val 152 fs/ntfs/super.c bool val; \ val 153 fs/ntfs/super.c if (!simple_getbool(v, &val)) \ val 155 fs/ntfs/super.c variable = val; \ val 167 fs/ntfs/super.c variable |= opt_array[_i].val; \ val 219 fs/ntfs/super.c bool val = false; val 226 fs/ntfs/super.c val = true; val 227 fs/ntfs/super.c else if (!simple_getbool(v, &val)) val 229 fs/ntfs/super.c if (val) { val 2646 fs/ntfs/super.c sfs->f_fsid.val[0] = vol->serial_no & 0xffffffff; val 2647 fs/ntfs/super.c sfs->f_fsid.val[1] = (vol->serial_no >> 32) & 0xffffffff; val 227 fs/ocfs2/blockcheck.c static int blockcheck_u64_get(void *data, u64 *val) val 229 fs/ocfs2/blockcheck.c *val = *(u64 *)data; val 427 fs/ocfs2/cluster/nodemanager.c unsigned int *val) val 441 fs/ocfs2/cluster/nodemanager.c *val = tmp; val 457 fs/ocfs2/cluster/nodemanager.c unsigned int val; val 459 fs/ocfs2/cluster/nodemanager.c ret = o2nm_cluster_attr_write(page, count, &val); val 462 fs/ocfs2/cluster/nodemanager.c if (cluster->cl_idle_timeout_ms != val val 470 fs/ocfs2/cluster/nodemanager.c } else if (val <= cluster->cl_keepalive_delay_ms) { val 475 fs/ocfs2/cluster/nodemanager.c cluster->cl_idle_timeout_ms = val; val 494 fs/ocfs2/cluster/nodemanager.c unsigned int val; val 496 fs/ocfs2/cluster/nodemanager.c ret = o2nm_cluster_attr_write(page, count, &val); val 499 fs/ocfs2/cluster/nodemanager.c if (cluster->cl_keepalive_delay_ms != val val 507 fs/ocfs2/cluster/nodemanager.c } else if (val >= cluster->cl_idle_timeout_ms) { val 512 fs/ocfs2/cluster/nodemanager.c cluster->cl_keepalive_delay_ms = val; val 1446 fs/ocfs2/cluster/tcp.c int val = 1; val 1449 fs/ocfs2/cluster/tcp.c (void *)&val, sizeof(val)); val 228 fs/ocfs2/dir.c __u32 pad, val; val 234 fs/ocfs2/dir.c val = pad; val 239 fs/ocfs2/dir.c val = pad; val 240 fs/ocfs2/dir.c val = msg[i] + (val << 8); val 242 fs/ocfs2/dir.c *buf++ = val; val 243 fs/ocfs2/dir.c val = pad; val 248 fs/ocfs2/dir.c *buf++ = val; val 3558 fs/ocfs2/dir.c u32 val = le32_to_cpu(dl_list->de_entries[0].dx_major_hash); val 3560 fs/ocfs2/dir.c if (val == insert_hash) { val 3571 fs/ocfs2/dir.c if (val == leaf_cpos) { val 3588 fs/ocfs2/dir.c if (val > insert_hash) { val 3596 fs/ocfs2/dir.c *split_hash = val; val 76 fs/ocfs2/dlmfs/dlmfs.c static int param_set_dlmfs_capabilities(const char *val, val 533 fs/ocfs2/dlmfs/userdlm.c const char *val, val 545 fs/ocfs2/dlmfs/userdlm.c memcpy(lvb, val, len); val 551 fs/ocfs2/dlmfs/userdlm.c char *val, val 565 fs/ocfs2/dlmfs/userdlm.c memcpy(val, lvb, len); val 67 fs/ocfs2/dlmfs/userdlm.h const char *val, val 70 fs/ocfs2/dlmfs/userdlm.h char *val, val 243 fs/ocfs2/filecheck.c unsigned long *val) val 250 fs/ocfs2/filecheck.c if (kstrtoul(buffer, 0, val)) val 275 fs/ocfs2/filecheck.c unsigned long val = 0; val 284 fs/ocfs2/filecheck.c if (ocfs2_filecheck_args_get_long(buf, count, &val)) val 287 fs/ocfs2/filecheck.c if (val <= 0) val 292 fs/ocfs2/filecheck.c args->fa_len = (unsigned int)val; val 294 fs/ocfs2/filecheck.c args->fa_ino = val; val 1660 fs/ocfs2/super.c buf->f_fsid.val[0] = crc32_le(0, osb->uuid_str, OCFS2_VOL_UUID_LEN) val 1662 fs/ocfs2/super.c buf->f_fsid.val[1] = crc32_le(0, osb->uuid_str + OCFS2_VOL_UUID_LEN, val 2371 fs/ocfs2/xattr.c void *val; val 2381 fs/ocfs2/xattr.c val = (void *)header + val 2384 fs/ocfs2/xattr.c (val + OCFS2_XATTR_SIZE(entry->xe_name_len)); val 285 fs/omfs/inode.c buf->f_fsid.val[0] = (u32)id; val 286 fs/omfs/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 55 fs/openpromfs/inode.c unsigned char val = p[i]; val 57 fs/openpromfs/inode.c if ((i && !val) || val 58 fs/openpromfs/inode.c (val >= ' ' && val <= '~')) val 62 fs/orangefs/downcall.h char val[ORANGEFS_MAX_XATTR_VALUELEN]; val 360 fs/orangefs/file.c __u64 val = 0; val 365 fs/orangefs/file.c &val, sizeof(val)); val 369 fs/orangefs/file.c val = 0; val 370 fs/orangefs/file.c *uval = val; val 381 fs/orangefs/file.c __u64 val = 0; val 424 fs/orangefs/file.c val = uval; val 427 fs/orangefs/file.c (unsigned long long)val); val 430 fs/orangefs/file.c &val, sizeof(val), 0); val 230 fs/orangefs/orangefs-kernel.h char val[ORANGEFS_MAX_XATTR_VALUELEN]; val 539 fs/orangefs/orangefs-sysfs.c int val = 0; val 565 fs/orangefs/orangefs-sysfs.c rc = kstrtoint(buf, 0, &val); val 584 fs/orangefs/orangefs-sysfs.c if (val > 0) { val 593 fs/orangefs/orangefs-sysfs.c if (val > 0) { val 602 fs/orangefs/orangefs-sysfs.c if ((val == 0) || (val == 1)) { val 611 fs/orangefs/orangefs-sysfs.c if ((val >= 0)) { val 620 fs/orangefs/orangefs-sysfs.c if ((val >= 0)) { val 647 fs/orangefs/orangefs-sysfs.c if ((val >= 0)) { val 658 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 666 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 675 fs/orangefs/orangefs-sysfs.c if ((val > -1) && (val < 101)) { val 683 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 694 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 702 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 711 fs/orangefs/orangefs-sysfs.c if ((val > -1) && (val < 101)) { val 719 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 730 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 738 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 747 fs/orangefs/orangefs-sysfs.c if ((val > -1) && (val < 101)) { val 755 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 766 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 774 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 783 fs/orangefs/orangefs-sysfs.c if ((val > -1) && (val < 101)) { val 791 fs/orangefs/orangefs-sysfs.c if (val > -1) { val 807 fs/orangefs/orangefs-sysfs.c new_op->upcall.req.param.u.value64 = val; val 221 fs/orangefs/protocol.h char val[ORANGEFS_MAX_XATTR_VALUELEN]; val 141 fs/orangefs/xattr.c memcpy(buffer, cx->val, cx->length); val 206 fs/orangefs/xattr.c memcpy(buffer, new_op->downcall.resp.getxattr.val, length); val 222 fs/orangefs/xattr.c memcpy(cx->val, buffer, length); val 229 fs/orangefs/xattr.c memcpy(cx->val, buffer, length); val 364 fs/orangefs/xattr.c memcpy(new_op->upcall.req.setxattr.keyval.val, value, size); val 554 fs/overlayfs/util.c char val; val 559 fs/overlayfs/util.c res = vfs_getxattr(dentry, name, &val, 1); val 560 fs/overlayfs/util.c if (res == 1 && val == 'y') val 2724 fs/proc/base.c unsigned int val; val 2729 fs/proc/base.c ret = kstrtouint_from_user(buf, count, 0, &val); val 2744 fs/proc/base.c if (val & mask) val 28 fs/proc/task_mmu.c #define SEQ_PUT_DEC(str, val) \ val 29 fs/proc/task_mmu.c seq_put_decimal_ull_width(m, str, (val) << (PAGE_SHIFT-10), 8) val 783 fs/proc/task_mmu.c #define SEQ_PUT_DEC(str, val) \ val 784 fs/proc/task_mmu.c seq_put_decimal_ull_width(m, str, (val) >> 10, 8) val 100 fs/pstore/ftrace.c char val[] = { '0' + pstore_ftrace_enabled, '\n' }; val 102 fs/pstore/ftrace.c return simple_read_from_buffer(buf, count, ppos, val, sizeof(val)); val 140 fs/qnx4/inode.c buf->f_fsid.val[0] = (u32)id; val 141 fs/qnx4/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 170 fs/qnx6/inode.c buf->f_fsid.val[0] = (u32)id; val 171 fs/qnx6/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 1073 fs/reiserfs/reiserfs.h #define PUT_SB_BLOCK_COUNT(s, val) \ val 1074 fs/reiserfs/reiserfs.h do { SB_V1_DISK_SUPER_BLOCK(s)->s_block_count = cpu_to_le32(val); } while (0) val 1075 fs/reiserfs/reiserfs.h #define PUT_SB_FREE_BLOCKS(s, val) \ val 1076 fs/reiserfs/reiserfs.h do { SB_V1_DISK_SUPER_BLOCK(s)->s_free_blocks = cpu_to_le32(val); } while (0) val 1077 fs/reiserfs/reiserfs.h #define PUT_SB_ROOT_BLOCK(s, val) \ val 1078 fs/reiserfs/reiserfs.h do { SB_V1_DISK_SUPER_BLOCK(s)->s_root_block = cpu_to_le32(val); } while (0) val 1079 fs/reiserfs/reiserfs.h #define PUT_SB_TREE_HEIGHT(s, val) \ val 1080 fs/reiserfs/reiserfs.h do { SB_V1_DISK_SUPER_BLOCK(s)->s_tree_height = cpu_to_le16(val); } while (0) val 1081 fs/reiserfs/reiserfs.h #define PUT_SB_REISERFS_STATE(s, val) \ val 1082 fs/reiserfs/reiserfs.h do { SB_V1_DISK_SUPER_BLOCK(s)->s_umount_state = cpu_to_le16(val); } while (0) val 1083 fs/reiserfs/reiserfs.h #define PUT_SB_VERSION(s, val) \ val 1084 fs/reiserfs/reiserfs.h do { SB_V1_DISK_SUPER_BLOCK(s)->s_version = cpu_to_le16(val); } while (0) val 1085 fs/reiserfs/reiserfs.h #define PUT_SB_BMAP_NR(s, val) \ val 1086 fs/reiserfs/reiserfs.h do { SB_V1_DISK_SUPER_BLOCK(s)->s_bmap_nr = cpu_to_le16 (val); } while (0) val 1404 fs/reiserfs/reiserfs.h #define put_ih_free_space(ih, val) do { (ih)->u.ih_free_space_reserved = cpu_to_le16(val); } while(0) val 1405 fs/reiserfs/reiserfs.h #define put_ih_version(ih, val) do { (ih)->ih_version = cpu_to_le16(val); } while (0) val 1406 fs/reiserfs/reiserfs.h #define put_ih_entry_count(ih, val) do { (ih)->u.ih_entry_count = cpu_to_le16(val); } while (0) val 1407 fs/reiserfs/reiserfs.h #define put_ih_location(ih, val) do { (ih)->ih_item_location = cpu_to_le16(val); } while (0) val 1408 fs/reiserfs/reiserfs.h #define put_ih_item_len(ih, val) do { (ih)->ih_item_len = cpu_to_le16(val); } while (0) val 1413 fs/reiserfs/reiserfs.h #define set_ih_free_space(ih,val) put_ih_free_space((ih), ((ih_version(ih) == KEY_FORMAT_3_6) ? 0 : (val))) val 1490 fs/reiserfs/reiserfs.h loff_t val = le32_to_cpu(key->u.k_offset_v1.k_uniqueness); val 1491 fs/reiserfs/reiserfs.h return uniqueness2type(val); val 1663 fs/reiserfs/reiserfs.h #define set_blkh_level(p_blkh,val) ((p_blkh)->blk_level = cpu_to_le16(val)) val 1664 fs/reiserfs/reiserfs.h #define set_blkh_nr_item(p_blkh,val) ((p_blkh)->blk_nr_item = cpu_to_le16(val)) val 1665 fs/reiserfs/reiserfs.h #define set_blkh_free_space(p_blkh,val) ((p_blkh)->blk_free_space = cpu_to_le16(val)) val 1666 fs/reiserfs/reiserfs.h #define set_blkh_reserved(p_blkh,val) ((p_blkh)->blk_reserved = cpu_to_le16(val)) val 1668 fs/reiserfs/reiserfs.h #define set_blkh_right_delim_key(p_blkh,val) ((p_blkh)->blk_right_delim_key = val) val 1690 fs/reiserfs/reiserfs.h #define PUT_B_NR_ITEMS(bh, val) do { set_blkh_nr_item(B_BLK_HEAD(bh), val); } while (0) val 1691 fs/reiserfs/reiserfs.h #define PUT_B_LEVEL(bh, val) do { set_blkh_level(B_BLK_HEAD(bh), val); } while (0) val 1692 fs/reiserfs/reiserfs.h #define PUT_B_FREE_SPACE(bh, val) do { set_blkh_free_space(B_BLK_HEAD(bh), val); } while (0) val 2046 fs/reiserfs/reiserfs.h #define put_dc_block_number(dc_p, val) do { (dc_p)->dc_block_number = cpu_to_le32(val); } while(0) val 2047 fs/reiserfs/reiserfs.h #define put_dc_size(dc_p, val) do { (dc_p)->dc_size = cpu_to_le16(val); } while(0) val 2055 fs/reiserfs/reiserfs.h #define PUT_B_N_CHILD_NUM(bh, n_pos, val) \ val 2056 fs/reiserfs/reiserfs.h (put_dc_block_number(B_N_CHILD(bh, n_pos), val)) val 2690 fs/reiserfs/reiserfs.h #define PUT_B_I_POS_UNFM_POINTER(bh, ih, pos, val) \ val 2691 fs/reiserfs/reiserfs.h (*(((unp_t *)ih_item_body(bh, ih)) + (pos)) = cpu_to_le32(val)) val 2724 fs/reiserfs/reiserfs.h #define set_desc_trans_id(d,val) do { (d)->j_trans_id = cpu_to_le32 (val); } while (0) val 2725 fs/reiserfs/reiserfs.h #define set_desc_trans_len(d,val) do { (d)->j_len = cpu_to_le32 (val); } while (0) val 2726 fs/reiserfs/reiserfs.h #define set_desc_mount_id(d,val) do { (d)->j_mount_id = cpu_to_le32 (val); } while (0) val 2739 fs/reiserfs/reiserfs.h #define set_commit_trans_id(c,val) do { (c)->j_trans_id = cpu_to_le32 (val); } while (0) val 2740 fs/reiserfs/reiserfs.h #define set_commit_trans_len(c,val) do { (c)->j_len = cpu_to_le32 (val); } while (0) val 3128 fs/reiserfs/reiserfs.h #define PROC_INFO_ADD( sb, field, val ) ( __PINFO( sb ).field += ( val ) ) val 3158 fs/reiserfs/reiserfs.h #define PROC_INFO_ADD( sb, field, val ) VOID_V val 1219 fs/reiserfs/super.c unsigned long val = simple_strtoul(arg, &p, 0); val 1221 fs/reiserfs/super.c if (*p != '\0' || val >= (unsigned int)-1) { val 1227 fs/reiserfs/super.c *commit_max_age = (unsigned int)val; val 2262 fs/reiserfs/super.c buf->f_fsid.val[0] = (u32)crc32_le(0, rs->s_uuid, sizeof(rs->s_uuid)/2); val 2263 fs/reiserfs/super.c buf->f_fsid.val[1] = (u32)crc32_le(0, rs->s_uuid + sizeof(rs->s_uuid)/2, val 418 fs/romfs/super.c buf->f_fsid.val[0] = (u32)id; val 419 fs/romfs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 383 fs/squashfs/super.c buf->f_fsid.val[0] = (u32)id; val 384 fs/squashfs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 46 fs/squashfs/xattr.c struct squashfs_xattr_val val; val 88 fs/squashfs/xattr.c err = squashfs_read_metadata(sb, &val, &start, &offset, val 89 fs/squashfs/xattr.c sizeof(val)); val 94 fs/squashfs/xattr.c le32_to_cpu(val.vsize)); val 124 fs/squashfs/xattr.c struct squashfs_xattr_val val; val 152 fs/squashfs/xattr.c err = squashfs_read_metadata(sb, &val, &start, val 153 fs/squashfs/xattr.c &offset, sizeof(val)); val 166 fs/squashfs/xattr.c err = squashfs_read_metadata(sb, &val, &start, &offset, val 167 fs/squashfs/xattr.c sizeof(val)); val 171 fs/squashfs/xattr.c vsize = le32_to_cpu(val.vsize); val 186 fs/squashfs/xattr.c err = squashfs_read_metadata(sb, &val, &start, &offset, val 187 fs/squashfs/xattr.c sizeof(val)); val 191 fs/squashfs/xattr.c le32_to_cpu(val.vsize)); val 287 fs/statfs.c buf.f_fsid.val[0] = kbuf->f_fsid.val[0]; val 288 fs/statfs.c buf.f_fsid.val[1] = kbuf->f_fsid.val[1]; val 334 fs/statfs.c buf.f_fsid.val[0] = kbuf->f_fsid.val[0]; val 335 fs/statfs.c buf.f_fsid.val[1] = kbuf->f_fsid.val[1]; val 101 fs/sysv/inode.c buf->f_fsid.val[0] = (u32)id; val 102 fs/sysv/inode.c buf->f_fsid.val[1] = (u32)(id >> 32); val 2663 fs/ubifs/debug.c static int provide_user_output(int val, char __user *u, size_t count, val 2668 fs/ubifs/debug.c if (val) val 2684 fs/ubifs/debug.c int val; val 2687 fs/ubifs/debug.c val = d->chk_gen; val 2689 fs/ubifs/debug.c val = d->chk_index; val 2691 fs/ubifs/debug.c val = d->chk_orph; val 2693 fs/ubifs/debug.c val = d->chk_lprops; val 2695 fs/ubifs/debug.c val = d->chk_fs; val 2697 fs/ubifs/debug.c val = d->tst_rcvry; val 2699 fs/ubifs/debug.c val = c->ro_error; val 2703 fs/ubifs/debug.c return provide_user_output(val, u, count, ppos); val 2738 fs/ubifs/debug.c int val; val 2767 fs/ubifs/debug.c val = interpret_user_input(u, count); val 2768 fs/ubifs/debug.c if (val < 0) val 2769 fs/ubifs/debug.c return val; val 2772 fs/ubifs/debug.c d->chk_gen = val; val 2774 fs/ubifs/debug.c d->chk_index = val; val 2776 fs/ubifs/debug.c d->chk_orph = val; val 2778 fs/ubifs/debug.c d->chk_lprops = val; val 2780 fs/ubifs/debug.c d->chk_fs = val; val 2782 fs/ubifs/debug.c d->tst_rcvry = val; val 2784 fs/ubifs/debug.c c->ro_error = !!val; val 2889 fs/ubifs/debug.c int val; val 2892 fs/ubifs/debug.c val = ubifs_dbg.chk_gen; val 2894 fs/ubifs/debug.c val = ubifs_dbg.chk_index; val 2896 fs/ubifs/debug.c val = ubifs_dbg.chk_orph; val 2898 fs/ubifs/debug.c val = ubifs_dbg.chk_lprops; val 2900 fs/ubifs/debug.c val = ubifs_dbg.chk_fs; val 2902 fs/ubifs/debug.c val = ubifs_dbg.tst_rcvry; val 2906 fs/ubifs/debug.c return provide_user_output(val, u, count, ppos); val 2913 fs/ubifs/debug.c int val; val 2915 fs/ubifs/debug.c val = interpret_user_input(u, count); val 2916 fs/ubifs/debug.c if (val < 0) val 2917 fs/ubifs/debug.c return val; val 2920 fs/ubifs/debug.c ubifs_dbg.chk_gen = val; val 2922 fs/ubifs/debug.c ubifs_dbg.chk_index = val; val 2924 fs/ubifs/debug.c ubifs_dbg.chk_orph = val; val 2926 fs/ubifs/debug.c ubifs_dbg.chk_lprops = val; val 2928 fs/ubifs/debug.c ubifs_dbg.chk_fs = val; val 2930 fs/ubifs/debug.c ubifs_dbg.tst_rcvry = val; val 222 fs/ubifs/lpt.c static void pack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, uint32_t val, int nrbits) val 231 fs/ubifs/lpt.c ubifs_assert(c, (val >> nrbits) == 0 || nrbits == 32); val 233 fs/ubifs/lpt.c *p |= ((uint8_t)val) << b; val 236 fs/ubifs/lpt.c *++p = (uint8_t)(val >>= (8 - b)); val 238 fs/ubifs/lpt.c *++p = (uint8_t)(val >>= 8); val 240 fs/ubifs/lpt.c *++p = (uint8_t)(val >>= 8); val 242 fs/ubifs/lpt.c *++p = (uint8_t)(val >>= 8); val 247 fs/ubifs/lpt.c *p = (uint8_t)val; val 249 fs/ubifs/lpt.c *++p = (uint8_t)(val >>= 8); val 251 fs/ubifs/lpt.c *++p = (uint8_t)(val >>= 8); val 253 fs/ubifs/lpt.c *++p = (uint8_t)(val >>= 8); val 278 fs/ubifs/lpt.c uint32_t uninitialized_var(val); val 288 fs/ubifs/lpt.c val = p[1]; val 291 fs/ubifs/lpt.c val = p[1] | ((uint32_t)p[2] << 8); val 294 fs/ubifs/lpt.c val = p[1] | ((uint32_t)p[2] << 8) | val 298 fs/ubifs/lpt.c val = p[1] | ((uint32_t)p[2] << 8) | val 302 fs/ubifs/lpt.c val <<= (8 - b); val 303 fs/ubifs/lpt.c val |= *p >> b; val 308 fs/ubifs/lpt.c val = p[0]; val 311 fs/ubifs/lpt.c val = p[0] | ((uint32_t)p[1] << 8); val 314 fs/ubifs/lpt.c val = p[0] | ((uint32_t)p[1] << 8) | val 318 fs/ubifs/lpt.c val = p[0] | ((uint32_t)p[1] << 8) | val 324 fs/ubifs/lpt.c val <<= k; val 325 fs/ubifs/lpt.c val >>= k; val 330 fs/ubifs/lpt.c ubifs_assert(c, (val >> nrbits) == 0 || nrbits - b == 32); val 331 fs/ubifs/lpt.c return val; val 412 fs/ubifs/super.c buf->f_fsid.val[0] = le32_to_cpu(uuid[0]) ^ le32_to_cpu(uuid[2]); val 413 fs/ubifs/super.c buf->f_fsid.val[1] = le32_to_cpu(uuid[1]) ^ le32_to_cpu(uuid[3]); val 2409 fs/udf/super.c buf->f_fsid.val[0] = (u32)id; val 2410 fs/udf/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 1434 fs/ufs/super.c buf->f_fsid.val[0] = (u32)id; val 1435 fs/ufs/super.c buf->f_fsid.val[1] = (u32)(id >> 32); val 568 fs/ufs/util.h static inline void ufs_cpu_to_data_ptr(struct super_block *sb, void *p, u64 val) val 571 fs/ufs/util.h *(__fs64 *)p = cpu_to_fs64(sb, val); val 573 fs/ufs/util.h *(__fs32 *)p = cpu_to_fs32(sb, val); val 262 fs/unicode/mkutf8data.c static int utf8encode(char *str, unsigned int val) val 266 fs/unicode/mkutf8data.c if (val < 0x80) { val 267 fs/unicode/mkutf8data.c str[0] = val; val 269 fs/unicode/mkutf8data.c } else if (val < 0x800) { val 270 fs/unicode/mkutf8data.c str[1] = val & UTF8_V_MASK; val 272 fs/unicode/mkutf8data.c val >>= UTF8_V_SHIFT; val 273 fs/unicode/mkutf8data.c str[0] = val; val 276 fs/unicode/mkutf8data.c } else if (val < 0x10000) { val 277 fs/unicode/mkutf8data.c str[2] = val & UTF8_V_MASK; val 279 fs/unicode/mkutf8data.c val >>= UTF8_V_SHIFT; val 280 fs/unicode/mkutf8data.c str[1] = val & UTF8_V_MASK; val 282 fs/unicode/mkutf8data.c val >>= UTF8_V_SHIFT; val 283 fs/unicode/mkutf8data.c str[0] = val; val 286 fs/unicode/mkutf8data.c } else if (val < 0x110000) { val 287 fs/unicode/mkutf8data.c str[3] = val & UTF8_V_MASK; val 289 fs/unicode/mkutf8data.c val >>= UTF8_V_SHIFT; val 290 fs/unicode/mkutf8data.c str[2] = val & UTF8_V_MASK; val 292 fs/unicode/mkutf8data.c val >>= UTF8_V_SHIFT; val 293 fs/unicode/mkutf8data.c str[1] = val & UTF8_V_MASK; val 295 fs/unicode/mkutf8data.c val >>= UTF8_V_SHIFT; val 296 fs/unicode/mkutf8data.c str[0] = val; val 300 fs/unicode/mkutf8data.c printf("%#x: illegal val\n", val); val 119 fs/unicode/utf8-norm.c utf8encode3(char *str, unsigned int val) val 121 fs/unicode/utf8-norm.c str[2] = (val & 0x3F) | 0x80; val 122 fs/unicode/utf8-norm.c val >>= 6; val 123 fs/unicode/utf8-norm.c str[1] = (val & 0x3F) | 0x80; val 124 fs/unicode/utf8-norm.c val >>= 6; val 125 fs/unicode/utf8-norm.c str[0] = val | 0xE0; val 90 fs/xfs/libxfs/xfs_btree.h #define XFS_BTREE_STATS_ADD(cur, stat, val) \ val 91 fs/xfs/libxfs/xfs_btree.h XFS_STATS_ADD_OFF((cur)->bc_mp, (cur)->bc_statoff + __XBTS_ ## stat, val) val 604 fs/xfs/libxfs/xfs_fs.h typedef struct { __u32 val[2]; } xfs_fsid_t; /* file system id type */ val 537 fs/xfs/libxfs/xfs_rtbitmap.c int val) /* 1 for free, 0 for allocated */ val 572 fs/xfs/libxfs/xfs_rtbitmap.c val = -val; val 586 fs/xfs/libxfs/xfs_rtbitmap.c if (val) val 629 fs/xfs/libxfs/xfs_rtbitmap.c *b = val; val 668 fs/xfs/libxfs/xfs_rtbitmap.c if (val) val 769 fs/xfs/libxfs/xfs_rtbitmap.c int val, /* 1 for free, 0 for allocated */ val 806 fs/xfs/libxfs/xfs_rtbitmap.c val = -val; val 823 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = (*b ^ val) & mask)) { val 869 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = *b ^ val)) { val 914 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = (*b ^ val) & mask)) { val 87 fs/xfs/xfs_error.c unsigned int val; val 90 fs/xfs/xfs_error.c val = xfs_errortag_random_default[xfs_attr->tag]; val 92 fs/xfs/xfs_error.c ret = kstrtouint(buf, 0, &val); val 97 fs/xfs/xfs_error.c ret = xfs_errortag_set(mp, xfs_attr->tag, val); val 83 fs/xfs/xfs_error.h #define xfs_errortag_set(mp, tag, val) (ENOSYS) val 87 fs/xfs/xfs_linux.h #define irix_sgid_inherit xfs_params.sgid_inherit.val val 88 fs/xfs/xfs_linux.h #define irix_symlink_mode xfs_params.symlink_mode.val val 89 fs/xfs/xfs_linux.h #define xfs_panic_mask xfs_params.panic_mask.val val 90 fs/xfs/xfs_linux.h #define xfs_error_level xfs_params.error_level.val val 91 fs/xfs/xfs_linux.h #define xfs_syncd_centisecs xfs_params.syncd_timer.val val 92 fs/xfs/xfs_linux.h #define xfs_stats_clear xfs_params.stats_clear.val val 93 fs/xfs/xfs_linux.h #define xfs_inherit_sync xfs_params.inherit_sync.val val 94 fs/xfs/xfs_linux.h #define xfs_inherit_nodump xfs_params.inherit_nodump.val val 95 fs/xfs/xfs_linux.h #define xfs_inherit_noatime xfs_params.inherit_noatim.val val 96 fs/xfs/xfs_linux.h #define xfs_inherit_nosymlinks xfs_params.inherit_nosym.val val 97 fs/xfs/xfs_linux.h #define xfs_rotorstep xfs_params.rotorstep.val val 98 fs/xfs/xfs_linux.h #define xfs_inherit_nodefrag xfs_params.inherit_nodfrg.val val 99 fs/xfs/xfs_linux.h #define xfs_fstrm_centisecs xfs_params.fstrm_timer.val val 100 fs/xfs/xfs_linux.h #define xfs_eofb_secs xfs_params.eofb_timer.val val 101 fs/xfs/xfs_linux.h #define xfs_cowb_secs xfs_params.cowb_timer.val val 467 fs/xfs/xfs_log_priv.h xfs_lsn_t val = atomic64_read(lsn); val 469 fs/xfs/xfs_log_priv.h *cycle = CYCLE_LSN(val); val 470 fs/xfs/xfs_log_priv.h *block = BLOCK_LSN(val); val 488 fs/xfs/xfs_log_priv.h xlog_crack_grant_head_val(int64_t val, int *cycle, int *space) val 490 fs/xfs/xfs_log_priv.h *cycle = val >> 32; val 491 fs/xfs/xfs_log_priv.h *space = val & 0xffffffff; val 106 fs/xfs/xfs_rtalloc.h xfs_rtblock_t start, xfs_extlen_t len, int val, val 115 fs/xfs/xfs_rtalloc.h xfs_rtblock_t start, xfs_extlen_t len, int val); val 12 fs/xfs/xfs_stats.c int val = 0, cpu; val 15 fs/xfs/xfs_stats.c val += *(((__u32 *)per_cpu_ptr(stats, cpu) + idx)); val 16 fs/xfs/xfs_stats.c return val; val 1095 fs/xfs/xfs_super.c statp->f_fsid.val[0] = (u32)id; val 1096 fs/xfs/xfs_super.c statp->f_fsid.val[1] = (u32)(id >> 32); val 56 fs/xfs/xfs_sysctl.c .data = &xfs_params.sgid_inherit.val, val 65 fs/xfs/xfs_sysctl.c .data = &xfs_params.symlink_mode.val, val 74 fs/xfs/xfs_sysctl.c .data = &xfs_params.panic_mask.val, val 84 fs/xfs/xfs_sysctl.c .data = &xfs_params.error_level.val, val 93 fs/xfs/xfs_sysctl.c .data = &xfs_params.syncd_timer.val, val 102 fs/xfs/xfs_sysctl.c .data = &xfs_params.inherit_sync.val, val 111 fs/xfs/xfs_sysctl.c .data = &xfs_params.inherit_nodump.val, val 120 fs/xfs/xfs_sysctl.c .data = &xfs_params.inherit_noatim.val, val 129 fs/xfs/xfs_sysctl.c .data = &xfs_params.inherit_nosym.val, val 138 fs/xfs/xfs_sysctl.c .data = &xfs_params.rotorstep.val, val 147 fs/xfs/xfs_sysctl.c .data = &xfs_params.inherit_nodfrg.val, val 156 fs/xfs/xfs_sysctl.c .data = &xfs_params.fstrm_timer.val, val 165 fs/xfs/xfs_sysctl.c .data = &xfs_params.eofb_timer.val, val 174 fs/xfs/xfs_sysctl.c .data = &xfs_params.cowb_timer.val, val 185 fs/xfs/xfs_sysctl.c .data = &xfs_params.stats_clear.val, val 17 fs/xfs/xfs_sysctl.h int val; val 86 fs/xfs/xfs_sysfs.c int val; val 88 fs/xfs/xfs_sysfs.c ret = kstrtoint(buf, 0, &val); val 92 fs/xfs/xfs_sysfs.c if (val == 1) val 94 fs/xfs/xfs_sysfs.c else if (val == 0) val 118 fs/xfs/xfs_sysfs.c int val; val 120 fs/xfs/xfs_sysfs.c ret = kstrtoint(buf, 0, &val); val 124 fs/xfs/xfs_sysfs.c if (val < 0 || val > 60) val 127 fs/xfs/xfs_sysfs.c xfs_globals.log_recovery_delay = val; val 148 fs/xfs/xfs_sysfs.c int val; val 150 fs/xfs/xfs_sysfs.c ret = kstrtoint(buf, 0, &val); val 154 fs/xfs/xfs_sysfs.c if (val < 0 || val > 60) val 157 fs/xfs/xfs_sysfs.c xfs_globals.mount_delay = val; val 207 fs/xfs/xfs_sysfs.c int val; val 209 fs/xfs/xfs_sysfs.c ret = kstrtoint(buf, 0, &val); val 213 fs/xfs/xfs_sysfs.c if (val < -1 || val > num_possible_cpus()) val 216 fs/xfs/xfs_sysfs.c xfs_globals.pwork_threads = val; val 278 fs/xfs/xfs_sysfs.c int val; val 281 fs/xfs/xfs_sysfs.c ret = kstrtoint(buf, 0, &val); val 285 fs/xfs/xfs_sysfs.c if (val != 1) val 438 fs/xfs/xfs_sysfs.c int val; val 440 fs/xfs/xfs_sysfs.c ret = kstrtoint(buf, 0, &val); val 444 fs/xfs/xfs_sysfs.c if (val < -1) val 447 fs/xfs/xfs_sysfs.c if (val == -1) val 450 fs/xfs/xfs_sysfs.c cfg->max_retries = val; val 479 fs/xfs/xfs_sysfs.c int val; val 481 fs/xfs/xfs_sysfs.c ret = kstrtoint(buf, 0, &val); val 486 fs/xfs/xfs_sysfs.c if (val < -1 || val > 86400) val 489 fs/xfs/xfs_sysfs.c if (val == -1) val 492 fs/xfs/xfs_sysfs.c cfg->retry_timeout = msecs_to_jiffies(val * MSEC_PER_SEC); val 493 fs/xfs/xfs_sysfs.c ASSERT(msecs_to_jiffies(val * MSEC_PER_SEC) < LONG_MAX); val 517 fs/xfs/xfs_sysfs.c int val; val 519 fs/xfs/xfs_sysfs.c ret = kstrtoint(buf, 0, &val); val 523 fs/xfs/xfs_sysfs.c if (val < 0 || val > 1) val 526 fs/xfs/xfs_sysfs.c mp->m_fail_unmount = val; val 987 include/acpi/actypes.h char *val; val 143 include/acpi/cppc_acpi.h extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); val 144 include/acpi/cppc_acpi.h extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); val 18 include/asm-generic/export.h .macro __put, val, name val 32 include/asm-generic/export.h .macro ___EXPORT_SYMBOL name,val,sec val 70 include/asm-generic/export.h #define __EXPORT_SYMBOL(sym, val, sec) \ val 72 include/asm-generic/export.h __cond_export_sym(sym, val, sec, __is_defined(__KSYM_##sym)) val 73 include/asm-generic/export.h #define __cond_export_sym(sym, val, sec, conf) \ val 74 include/asm-generic/export.h ___cond_export_sym(sym, val, sec, conf) val 75 include/asm-generic/export.h #define ___cond_export_sym(sym, val, sec, enabled) \ val 76 include/asm-generic/export.h __cond_export_sym_##enabled(sym, val, sec) val 77 include/asm-generic/export.h #define __cond_export_sym_1(sym, val, sec) ___EXPORT_SYMBOL sym, val, sec val 78 include/asm-generic/export.h #define __cond_export_sym_0(sym, val, sec) /* nothing */ val 81 include/asm-generic/export.h #define __EXPORT_SYMBOL(sym, val, sec) ___EXPORT_SYMBOL sym, val, sec val 98 include/asm-generic/futex.h u32 val; val 101 include/asm-generic/futex.h if (unlikely(get_user(val, uaddr) != 0)) { val 106 include/asm-generic/futex.h if (val == oldval && unlikely(put_user(newval, uaddr) != 0)) { val 111 include/asm-generic/futex.h *uval = val; val 150 include/asm-generic/io.h u8 val; val 153 include/asm-generic/io.h val = __raw_readb(addr); val 154 include/asm-generic/io.h __io_ar(val); val 155 include/asm-generic/io.h return val; val 163 include/asm-generic/io.h u16 val; val 166 include/asm-generic/io.h val = __le16_to_cpu(__raw_readw(addr)); val 167 include/asm-generic/io.h __io_ar(val); val 168 include/asm-generic/io.h return val; val 176 include/asm-generic/io.h u32 val; val 179 include/asm-generic/io.h val = __le32_to_cpu(__raw_readl(addr)); val 180 include/asm-generic/io.h __io_ar(val); val 181 include/asm-generic/io.h return val; val 190 include/asm-generic/io.h u64 val; val 193 include/asm-generic/io.h val = __le64_to_cpu(__raw_readq(addr)); val 194 include/asm-generic/io.h __io_ar(val); val 195 include/asm-generic/io.h return val; val 463 include/asm-generic/io.h u8 val; val 466 include/asm-generic/io.h val = __raw_readb(PCI_IOBASE + addr); val 467 include/asm-generic/io.h __io_par(val); val 468 include/asm-generic/io.h return val; val 476 include/asm-generic/io.h u16 val; val 479 include/asm-generic/io.h val = __le16_to_cpu(__raw_readw(PCI_IOBASE + addr)); val 480 include/asm-generic/io.h __io_par(val); val 481 include/asm-generic/io.h return val; val 489 include/asm-generic/io.h u32 val; val 492 include/asm-generic/io.h val = __le32_to_cpu(__raw_readl(PCI_IOBASE + addr)); val 493 include/asm-generic/io.h __io_par(val); val 494 include/asm-generic/io.h return val; val 65 include/asm-generic/iomap.h extern void iowrite64_lo_hi(u64 val, void __iomem *addr); val 66 include/asm-generic/iomap.h extern void iowrite64_hi_lo(u64 val, void __iomem *addr); val 67 include/asm-generic/iomap.h extern void iowrite64be_lo_hi(u64 val, void __iomem *addr); val 68 include/asm-generic/iomap.h extern void iowrite64be_hi_lo(u64 val, void __iomem *addr); val 70 include/asm-generic/percpu.h #define raw_cpu_generic_to_op(pcp, val, op) \ val 72 include/asm-generic/percpu.h *raw_cpu_ptr(&(pcp)) op val; \ val 75 include/asm-generic/percpu.h #define raw_cpu_generic_add_return(pcp, val) \ val 79 include/asm-generic/percpu.h *__p += val; \ val 144 include/asm-generic/percpu.h #define this_cpu_generic_to_op(pcp, val, op) \ val 148 include/asm-generic/percpu.h raw_cpu_generic_to_op(pcp, val, op); \ val 153 include/asm-generic/percpu.h #define this_cpu_generic_add_return(pcp, val) \ val 158 include/asm-generic/percpu.h __ret = raw_cpu_generic_add_return(pcp, val); \ val 208 include/asm-generic/percpu.h #define raw_cpu_write_1(pcp, val) raw_cpu_generic_to_op(pcp, val, =) val 211 include/asm-generic/percpu.h #define raw_cpu_write_2(pcp, val) raw_cpu_generic_to_op(pcp, val, =) val 214 include/asm-generic/percpu.h #define raw_cpu_write_4(pcp, val) raw_cpu_generic_to_op(pcp, val, =) val 217 include/asm-generic/percpu.h #define raw_cpu_write_8(pcp, val) raw_cpu_generic_to_op(pcp, val, =) val 221 include/asm-generic/percpu.h #define raw_cpu_add_1(pcp, val) raw_cpu_generic_to_op(pcp, val, +=) val 224 include/asm-generic/percpu.h #define raw_cpu_add_2(pcp, val) raw_cpu_generic_to_op(pcp, val, +=) val 227 include/asm-generic/percpu.h #define raw_cpu_add_4(pcp, val) raw_cpu_generic_to_op(pcp, val, +=) val 230 include/asm-generic/percpu.h #define raw_cpu_add_8(pcp, val) raw_cpu_generic_to_op(pcp, val, +=) val 234 include/asm-generic/percpu.h #define raw_cpu_and_1(pcp, val) raw_cpu_generic_to_op(pcp, val, &=) val 237 include/asm-generic/percpu.h #define raw_cpu_and_2(pcp, val) raw_cpu_generic_to_op(pcp, val, &=) val 240 include/asm-generic/percpu.h #define raw_cpu_and_4(pcp, val) raw_cpu_generic_to_op(pcp, val, &=) val 243 include/asm-generic/percpu.h #define raw_cpu_and_8(pcp, val) raw_cpu_generic_to_op(pcp, val, &=) val 247 include/asm-generic/percpu.h #define raw_cpu_or_1(pcp, val) raw_cpu_generic_to_op(pcp, val, |=) val 250 include/asm-generic/percpu.h #define raw_cpu_or_2(pcp, val) raw_cpu_generic_to_op(pcp, val, |=) val 253 include/asm-generic/percpu.h #define raw_cpu_or_4(pcp, val) raw_cpu_generic_to_op(pcp, val, |=) val 256 include/asm-generic/percpu.h #define raw_cpu_or_8(pcp, val) raw_cpu_generic_to_op(pcp, val, |=) val 260 include/asm-generic/percpu.h #define raw_cpu_add_return_1(pcp, val) raw_cpu_generic_add_return(pcp, val) val 263 include/asm-generic/percpu.h #define raw_cpu_add_return_2(pcp, val) raw_cpu_generic_add_return(pcp, val) val 266 include/asm-generic/percpu.h #define raw_cpu_add_return_4(pcp, val) raw_cpu_generic_add_return(pcp, val) val 269 include/asm-generic/percpu.h #define raw_cpu_add_return_8(pcp, val) raw_cpu_generic_add_return(pcp, val) val 333 include/asm-generic/percpu.h #define this_cpu_write_1(pcp, val) this_cpu_generic_to_op(pcp, val, =) val 336 include/asm-generic/percpu.h #define this_cpu_write_2(pcp, val) this_cpu_generic_to_op(pcp, val, =) val 339 include/asm-generic/percpu.h #define this_cpu_write_4(pcp, val) this_cpu_generic_to_op(pcp, val, =) val 342 include/asm-generic/percpu.h #define this_cpu_write_8(pcp, val) this_cpu_generic_to_op(pcp, val, =) val 346 include/asm-generic/percpu.h #define this_cpu_add_1(pcp, val) this_cpu_generic_to_op(pcp, val, +=) val 349 include/asm-generic/percpu.h #define this_cpu_add_2(pcp, val) this_cpu_generic_to_op(pcp, val, +=) val 352 include/asm-generic/percpu.h #define this_cpu_add_4(pcp, val) this_cpu_generic_to_op(pcp, val, +=) val 355 include/asm-generic/percpu.h #define this_cpu_add_8(pcp, val) this_cpu_generic_to_op(pcp, val, +=) val 359 include/asm-generic/percpu.h #define this_cpu_and_1(pcp, val) this_cpu_generic_to_op(pcp, val, &=) val 362 include/asm-generic/percpu.h #define this_cpu_and_2(pcp, val) this_cpu_generic_to_op(pcp, val, &=) val 365 include/asm-generic/percpu.h #define this_cpu_and_4(pcp, val) this_cpu_generic_to_op(pcp, val, &=) val 368 include/asm-generic/percpu.h #define this_cpu_and_8(pcp, val) this_cpu_generic_to_op(pcp, val, &=) val 372 include/asm-generic/percpu.h #define this_cpu_or_1(pcp, val) this_cpu_generic_to_op(pcp, val, |=) val 375 include/asm-generic/percpu.h #define this_cpu_or_2(pcp, val) this_cpu_generic_to_op(pcp, val, |=) val 378 include/asm-generic/percpu.h #define this_cpu_or_4(pcp, val) this_cpu_generic_to_op(pcp, val, |=) val 381 include/asm-generic/percpu.h #define this_cpu_or_8(pcp, val) this_cpu_generic_to_op(pcp, val, |=) val 385 include/asm-generic/percpu.h #define this_cpu_add_return_1(pcp, val) this_cpu_generic_add_return(pcp, val) val 388 include/asm-generic/percpu.h #define this_cpu_add_return_2(pcp, val) this_cpu_generic_add_return(pcp, val) val 391 include/asm-generic/percpu.h #define this_cpu_add_return_4(pcp, val) this_cpu_generic_add_return(pcp, val) val 394 include/asm-generic/percpu.h #define this_cpu_add_return_8(pcp, val) this_cpu_generic_add_return(pcp, val) val 52 include/asm-generic/preempt.h static __always_inline void __preempt_count_add(int val) val 54 include/asm-generic/preempt.h *preempt_count_ptr() += val; val 57 include/asm-generic/preempt.h static __always_inline void __preempt_count_sub(int val) val 59 include/asm-generic/preempt.h *preempt_count_ptr() -= val; val 26 include/asm-generic/qspinlock.h return atomic_read(&lock->val); val 41 include/asm-generic/qspinlock.h return !atomic_read(&lock.val); val 51 include/asm-generic/qspinlock.h return atomic_read(&lock->val) & ~_Q_LOCKED_MASK; val 60 include/asm-generic/qspinlock.h u32 val = atomic_read(&lock->val); val 62 include/asm-generic/qspinlock.h if (unlikely(val)) val 65 include/asm-generic/qspinlock.h return likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL)); val 68 include/asm-generic/qspinlock.h extern void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); val 76 include/asm-generic/qspinlock.h u32 val = 0; val 78 include/asm-generic/qspinlock.h if (likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL))) val 81 include/asm-generic/qspinlock.h queued_spin_lock_slowpath(lock, val); val 24 include/asm-generic/qspinlock_types.h atomic_t val; val 57 include/asm-generic/qspinlock_types.h #define __ARCH_SPIN_LOCK_UNLOCKED { { .val = ATOMIC_INIT(0) } } val 99 include/asm-generic/syscall.h int error, long val); val 17 include/asm-generic/word-at-a-time.h static inline long prep_zero_mask(unsigned long val, unsigned long rhs, const struct word_at_a_time *c) val 19 include/asm-generic/word-at-a-time.h unsigned long mask = (val & c->low_bits) + c->low_bits; val 41 include/asm-generic/word-at-a-time.h static inline bool has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) val 43 include/asm-generic/word-at-a-time.h unsigned long rhs = val | c->low_bits; val 45 include/asm-generic/word-at-a-time.h return (val + c->high_bits) & ~rhs; val 266 include/clocksource/timer-ti-dm.h u32 reg, u32 val, int posted) val 272 include/clocksource/timer-ti-dm.h writel_relaxed(val, timer->func_base + (reg & 0xff)); val 785 include/drm/drm_connector.h uint64_t val); val 917 include/drm/drm_connector.h uint64_t val); val 940 include/drm/drm_connector.h uint64_t *val); val 1505 include/drm/drm_connector.h const char *drm_get_dpms_name(int val); val 1506 include/drm/drm_connector.h const char *drm_get_dvi_i_subconnector_name(int val); val 1507 include/drm/drm_connector.h const char *drm_get_dvi_i_select_name(int val); val 1508 include/drm/drm_connector.h const char *drm_get_tv_subconnector_name(int val); val 1509 include/drm/drm_connector.h const char *drm_get_tv_select_name(int val); val 1510 include/drm/drm_connector.h const char *drm_get_content_protection_name(int val); val 1511 include/drm/drm_connector.h const char *drm_get_hdcp_content_type_name(int val); val 62 include/drm/drm_crtc.h static inline int64_t U642I64(uint64_t val) val 64 include/drm/drm_crtc.h return (int64_t)*((int64_t *)&val); val 66 include/drm/drm_crtc.h static inline uint64_t I642U64(int64_t val) val 68 include/drm/drm_crtc.h return (uint64_t)*((uint64_t *)&val); val 604 include/drm/drm_crtc.h struct drm_property *property, uint64_t val); val 695 include/drm/drm_crtc.h uint64_t val); val 717 include/drm/drm_crtc.h uint64_t *val); val 74 include/drm/drm_encoder_slave.h uint64_t val); val 52 include/drm/drm_flip_work.h typedef void (*drm_flip_func_t)(struct drm_flip_work *work, void *val); val 85 include/drm/drm_flip_work.h void drm_flip_work_queue(struct drm_flip_work *work, void *val); val 261 include/drm/drm_hdcp.h void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val) val 263 include/drm/drm_hdcp.h seq_num[0] = val >> 16; val 264 include/drm/drm_hdcp.h seq_num[1] = val >> 8; val 265 include/drm/drm_hdcp.h seq_num[2] = val; val 296 include/drm/drm_hdcp.h u64 val); val 159 include/drm/drm_mipi_dbi.h int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val); val 107 include/drm/drm_mode_object.h const char *fnname(int val) \ val 111 include/drm/drm_mode_object.h if (list[i].type == val) \ val 125 include/drm/drm_mode_object.h uint64_t val); val 22 include/drm/drm_os_linux.h #define DRM_WRITE8(map, offset, val) writeb(val, ((void __iomem *)(map)->handle) + (offset)) val 24 include/drm/drm_os_linux.h #define DRM_WRITE16(map, offset, val) writew(val, ((void __iomem *)(map)->handle) + (offset)) val 26 include/drm/drm_os_linux.h #define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset)) val 31 include/drm/drm_os_linux.h #define DRM_WRITE64(map, offset, val) writeq(val, ((void __iomem *)(map)->handle) + (offset)) val 326 include/drm/drm_plane.h struct drm_property *property, uint64_t val); val 417 include/drm/drm_plane.h uint64_t val); val 440 include/drm/drm_plane.h uint64_t *val); val 52 include/dt-bindings/pinctrl/am43xx.h #define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) val 71 include/dt-bindings/pinctrl/dra.h #define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) val 74 include/dt-bindings/pinctrl/dra.h #define A_DELAY_PS(val) ((val) & 0xffff) val 75 include/dt-bindings/pinctrl/dra.h #define G_DELAY_PS(val) ((val) & 0xffff) val 32 include/dt-bindings/pinctrl/k3.h #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) val 33 include/dt-bindings/pinctrl/k3.h #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) val 35 include/dt-bindings/pinctrl/k3.h #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) val 36 include/dt-bindings/pinctrl/k3.h #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) val 59 include/dt-bindings/pinctrl/omap.h #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) val 60 include/dt-bindings/pinctrl/omap.h #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) val 61 include/dt-bindings/pinctrl/omap.h #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) val 62 include/dt-bindings/pinctrl/omap.h #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) val 63 include/dt-bindings/pinctrl/omap.h #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) val 64 include/dt-bindings/pinctrl/omap.h #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) val 65 include/dt-bindings/pinctrl/omap.h #define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) val 66 include/dt-bindings/pinctrl/omap.h #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) val 67 include/dt-bindings/pinctrl/omap.h #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) val 76 include/dt-bindings/pinctrl/omap.h #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) val 77 include/dt-bindings/pinctrl/omap.h #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) val 110 include/kvm/arm_arch_timer.h u64 val); val 35 include/kvm/arm_pmu.h void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val); val 40 include/kvm/arm_pmu.h void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val); val 41 include/kvm/arm_pmu.h void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val); val 46 include/kvm/arm_pmu.h void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val); val 47 include/kvm/arm_pmu.h void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val); val 70 include/kvm/arm_pmu.h u64 select_idx, u64 val) {} val 78 include/kvm/arm_pmu.h static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {} val 79 include/kvm/arm_pmu.h static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {} val 87 include/kvm/arm_pmu.h static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {} val 88 include/kvm/arm_pmu.h static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {} val 22 include/kvm/iodev.h void *val); val 27 include/kvm/iodev.h const void *val); val 354 include/linux/acpi.h extern int ec_read(u8 addr, u8 *val); val 355 include/linux/acpi.h extern int ec_write(u8 addr, u8 val); val 1059 include/linux/acpi.h void *val); val 1062 include/linux/acpi.h void *val, size_t nval); val 1064 include/linux/acpi.h enum dev_prop_type proptype, void *val, size_t nval); val 1165 include/linux/acpi.h void *val) val 1173 include/linux/acpi.h void *val, size_t nval) val 1181 include/linux/acpi.h void *val, size_t nval) val 279 include/linux/alcor_pci.h void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr); val 280 include/linux/alcor_pci.h void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr); val 281 include/linux/alcor_pci.h void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr); val 282 include/linux/alcor_pci.h void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr); val 146 include/linux/amba/clcd.h u32 val, cpl; val 151 include/linux/amba/clcd.h val = ((var->xres / 16) - 1) << 2; val 152 include/linux/amba/clcd.h val |= (var->hsync_len - 1) << 8; val 153 include/linux/amba/clcd.h val |= (var->right_margin - 1) << 16; val 154 include/linux/amba/clcd.h val |= (var->left_margin - 1) << 24; val 155 include/linux/amba/clcd.h regs->tim0 = val; val 157 include/linux/amba/clcd.h val = var->yres; val 159 include/linux/amba/clcd.h val /= 2; val 160 include/linux/amba/clcd.h val -= 1; val 161 include/linux/amba/clcd.h val |= (var->vsync_len - 1) << 10; val 162 include/linux/amba/clcd.h val |= var->lower_margin << 16; val 163 include/linux/amba/clcd.h val |= var->upper_margin << 24; val 164 include/linux/amba/clcd.h regs->tim1 = val; val 166 include/linux/amba/clcd.h val = fb->panel->tim2; val 167 include/linux/amba/clcd.h val |= var->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS; val 168 include/linux/amba/clcd.h val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS; val 180 include/linux/amba/clcd.h regs->tim2 = val | ((cpl - 1) << 16); val 184 include/linux/amba/clcd.h val = fb->panel->cntl; val 186 include/linux/amba/clcd.h val |= CNTL_LCDBW; val 199 include/linux/amba/clcd.h val &= ~CNTL_BGR; val 201 include/linux/amba/clcd.h val |= CNTL_BGR; val 203 include/linux/amba/clcd.h val ^= CNTL_BGR; val 208 include/linux/amba/clcd.h val |= CNTL_LCDBPP1; val 211 include/linux/amba/clcd.h val |= CNTL_LCDBPP2; val 214 include/linux/amba/clcd.h val |= CNTL_LCDBPP4; val 217 include/linux/amba/clcd.h val |= CNTL_LCDBPP8; val 227 include/linux/amba/clcd.h val |= CNTL_LCDBPP16; val 229 include/linux/amba/clcd.h val |= CNTL_LCDBPP16_565; val 231 include/linux/amba/clcd.h val |= CNTL_LCDBPP16_444; val 234 include/linux/amba/clcd.h val |= CNTL_LCDBPP24; val 238 include/linux/amba/clcd.h regs->cntl = val; val 586 include/linux/ata.h u16 val = id[ATA_ID_SATA_CAPABILITY]; val 588 include/linux/ata.h if (val == 0 || val == 0xffff) val 591 include/linux/ata.h return val & (1 << 9); val 596 include/linux/ata.h u16 val = id[ATA_ID_FEATURE_SUPP]; val 598 include/linux/ata.h if (val == 0 || val == 0xffff) val 601 include/linux/ata.h return val & (1 << 3); val 902 include/linux/ata.h u16 val = id[168]; val 904 include/linux/ata.h if (ata_id_major_version(id) < 7 || val == 0 || val == 0xffff) val 907 include/linux/ata.h val &= 0xf; val 909 include/linux/ata.h if (val > 5) val 912 include/linux/ata.h return val; val 917 include/linux/ata.h u16 val = id[217]; val 919 include/linux/ata.h if (ata_id_major_version(id) < 7 || val == 0 || val == 0xffff) val 922 include/linux/ata.h if (val > 1 && val < 0x401) val 925 include/linux/ata.h return val; val 63 include/linux/audit.h u32 val; val 499 include/linux/audit.h enum audit_ntp_type type, long long val) val 501 include/linux/audit.h ad->vals[type].oldval = val; val 505 include/linux/audit.h enum audit_ntp_type type, long long val) val 507 include/linux/audit.h ad->vals[type].newval = val; val 636 include/linux/audit.h enum audit_ntp_type type, long long val) val 640 include/linux/audit.h enum audit_ntp_type type, long long val) val 54 include/linux/average.h unsigned long val) \ val 67 include/linux/average.h (val << precision)) >> weight_rcp : \ val 68 include/linux/average.h (val << precision)); \ val 20 include/linux/bcd.h unsigned _bcd2bin(unsigned char val) __attribute_const__; val 21 include/linux/bcd.h unsigned char _bin2bcd(unsigned val) __attribute_const__; val 15 include/linux/bcm47xx_nvram.h int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len); val 27 include/linux/bcm47xx_nvram.h static inline int bcm47xx_nvram_getenv(const char *name, char *val, val 660 include/linux/bcma/bcma_driver_chipcommon.h #define bcma_cc_write32(cc, offset, val) \ val 661 include/linux/bcma/bcma_driver_chipcommon.h bcma_write32((cc)->core, offset, val) val 673 include/linux/bcma/bcma_driver_chipcommon.h #define bcma_pmu_write32(cc, offset, val) \ val 674 include/linux/bcma/bcma_driver_chipcommon.h bcma_write32((cc)->pmu.core, offset, val) val 92 include/linux/bcma/bcma_driver_gmac_cmn.h #define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val) val 93 include/linux/bcma/bcma_driver_gmac_cmn.h #define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val) val 239 include/linux/bcma/bcma_driver_pci.h #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val) val 240 include/linux/bcma/bcma_driver_pci.h #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val) val 153 include/linux/bcma/bcma_driver_pcie2.h #define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val) val 154 include/linux/bcma/bcma_driver_pcie2.h #define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val) val 121 include/linux/bitfield.h base val, base field) \ val 123 include/linux/bitfield.h return (old & ~to(field)) | type##_encode_bits(val, field); \ val 126 include/linux/bitfield.h base val, base field) \ val 128 include/linux/bitfield.h *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ val 615 include/linux/blk-cgroup.h unsigned int op, uint64_t val) val 626 include/linux/blk-cgroup.h percpu_counter_add_batch(cnt, val, BLKG_STAT_CPU_BATCH); val 633 include/linux/blk-cgroup.h percpu_counter_add_batch(cnt, val, BLKG_STAT_CPU_BATCH); val 32 include/linux/btree-128.h void *val; val 34 include/linux/btree-128.h val = btree_get_prev(&head->h, &btree_geo128, val 38 include/linux/btree-128.h return val; val 42 include/linux/btree-128.h void *val, gfp_t gfp) val 46 include/linux/btree-128.h (unsigned long *)&key, val, gfp); val 50 include/linux/btree-128.h void *val) val 54 include/linux/btree-128.h (unsigned long *)&key, val); val 66 include/linux/btree-128.h void *val; val 68 include/linux/btree-128.h val = btree_last(&head->h, &btree_geo128, (unsigned long *)&key[0]); val 69 include/linux/btree-128.h if (val) { val 74 include/linux/btree-128.h return val; val 106 include/linux/btree-128.h #define btree_for_each_safe128(head, k1, k2, val) \ val 107 include/linux/btree-128.h for (val = btree_last128(head, &k1, &k2); \ val 108 include/linux/btree-128.h val; \ val 109 include/linux/btree-128.h val = btree_get_prev128(head, &k1, &k2)) val 45 include/linux/btree-type.h void *val, gfp_t gfp) val 48 include/linux/btree-type.h return btree_insert(&head->h, BTREE_TYPE_GEO, &_key, val, gfp); val 52 include/linux/btree-type.h void *val) val 55 include/linux/btree-type.h return btree_update(&head->h, BTREE_TYPE_GEO, &_key, val); val 67 include/linux/btree-type.h void *val = btree_last(&head->h, BTREE_TYPE_GEO, &_key); val 68 include/linux/btree-type.h if (val) val 70 include/linux/btree-type.h return val; val 76 include/linux/btree-type.h void *val = btree_get_prev(&head->h, BTREE_TYPE_GEO, &_key); val 77 include/linux/btree-type.h if (val) val 79 include/linux/btree-type.h return val; val 88 include/linux/btree-type.h void *val, gfp_t gfp) val 91 include/linux/btree-type.h val, gfp); val 95 include/linux/btree-type.h void *val) val 97 include/linux/btree-type.h return btree_update(&head->h, BTREE_TYPE_GEO, (unsigned long *)&key, val); val 116 include/linux/btree.h unsigned long *key, void *val, gfp_t gfp); val 129 include/linux/btree.h unsigned long *key, void *val); val 216 include/linux/btree.h #define btree_for_each_safel(head, key, val) \ val 217 include/linux/btree.h for (val = btree_lastl(head, &key); \ val 218 include/linux/btree.h val; \ val 219 include/linux/btree.h val = btree_get_prevl(head, &key)) val 227 include/linux/btree.h #define btree_for_each_safe32(head, key, val) \ val 228 include/linux/btree.h for (val = btree_last32(head, &key); \ val 229 include/linux/btree.h val; \ val 230 include/linux/btree.h val = btree_get_prev32(head, &key)) val 239 include/linux/btree.h #define btree_for_each_safe64(head, key, val) \ val 240 include/linux/btree.h for (val = btree_last64(head, &key); \ val 241 include/linux/btree.h val; \ val 242 include/linux/btree.h val = btree_get_prev64(head, &key)) val 144 include/linux/byteorder/generic.h static inline void le16_add_cpu(__le16 *var, u16 val) val 146 include/linux/byteorder/generic.h *var = cpu_to_le16(le16_to_cpu(*var) + val); val 149 include/linux/byteorder/generic.h static inline void le32_add_cpu(__le32 *var, u32 val) val 151 include/linux/byteorder/generic.h *var = cpu_to_le32(le32_to_cpu(*var) + val); val 154 include/linux/byteorder/generic.h static inline void le64_add_cpu(__le64 *var, u64 val) val 156 include/linux/byteorder/generic.h *var = cpu_to_le64(le64_to_cpu(*var) + val); val 176 include/linux/byteorder/generic.h static inline void be16_add_cpu(__be16 *var, u16 val) val 178 include/linux/byteorder/generic.h *var = cpu_to_be16(be16_to_cpu(*var) + val); val 181 include/linux/byteorder/generic.h static inline void be32_add_cpu(__be32 *var, u32 val) val 183 include/linux/byteorder/generic.h *var = cpu_to_be32(be32_to_cpu(*var) + val); val 186 include/linux/byteorder/generic.h static inline void be64_add_cpu(__be64 *var, u64 val) val 188 include/linux/byteorder/generic.h *var = cpu_to_be64(be64_to_cpu(*var) + val); val 601 include/linux/cgroup-defs.h u64 val); val 606 include/linux/cgroup-defs.h s64 val); val 813 include/linux/cgroup-defs.h u64 val; val 841 include/linux/cgroup-defs.h struct sock_cgroup_data skcd_buf = {{ .val = READ_ONCE(skcd->val) }}; val 847 include/linux/cgroup-defs.h skcd_buf.val = 0; val 852 include/linux/cgroup-defs.h WRITE_ONCE(skcd->val, skcd_buf.val); /* see sock_cgroup_ptr() */ val 858 include/linux/cgroup-defs.h struct sock_cgroup_data skcd_buf = {{ .val = READ_ONCE(skcd->val) }}; val 864 include/linux/cgroup-defs.h skcd_buf.val = 0; val 869 include/linux/cgroup-defs.h WRITE_ONCE(skcd->val, skcd_buf.val); /* see sock_cgroup_ptr() */ val 763 include/linux/cgroup.h void cpuacct_account_field(struct task_struct *tsk, int index, u64 val); val 767 include/linux/cgroup.h u64 val) {} val 836 include/linux/cgroup.h v = READ_ONCE(skcd->val); val 843 include/linux/cgroup.h return (struct cgroup *)(unsigned long)skcd->val; val 402 include/linux/clk-provider.h unsigned int val; val 472 include/linux/clk-provider.h unsigned int val, const struct clk_div_table *table, val 481 include/linux/clk-provider.h unsigned long flags, unsigned int val); val 581 include/linux/clk-provider.h unsigned int val); val 865 include/linux/clk-provider.h unsigned int val) val 869 include/linux/clk-provider.h val); val 232 include/linux/clk/ti.h void (*clk_writel)(u32 val, const struct clk_omap_reg *reg); val 233 include/linux/clk/ti.h void (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg); val 26 include/linux/cnt32_to_63.h u64 val; val 101 include/linux/cnt32_to_63.h __x.val; \ val 17 include/linux/compiler.h void ftrace_likely_update(struct ftrace_likely_data *f, int val, val 284 include/linux/compiler.h #define WRITE_ONCE(x, val) \ val 287 include/linux/compiler.h { .__val = (__force typeof(x)) (val) }; \ val 358 include/linux/counter.h struct counter_signal_read_value *val); val 361 include/linux/counter.h struct counter_count_read_value *val); val 364 include/linux/counter.h struct counter_count_write_value *val); val 493 include/linux/counter.h void counter_signal_read_value_set(struct counter_signal_read_value *const val, val 496 include/linux/counter.h void counter_count_read_value_set(struct counter_count_read_value *const val, val 501 include/linux/counter.h const struct counter_count_write_value *const val); val 126 include/linux/cs5535.h uint16_t val; val 135 include/linux/cs5535.h val = inw(VSA_VRC_DATA); val 136 include/linux/cs5535.h has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG); val 97 include/linux/cyclades.h #define cy_writeb(port,val) do { writeb((val), (port)); mb(); } while (0) val 98 include/linux/cyclades.h #define cy_writew(port,val) do { writew((val), (port)); mb(); } while (0) val 99 include/linux/cyclades.h #define cy_writel(port,val) do { writel((val), (port)); mb(); } while (0) val 501 include/linux/dcache.h static inline unsigned long vfs_pressure_ratio(unsigned long val) val 503 include/linux/dcache.h return mult_frac(val, sysctl_vfs_cache_pressure, 100); val 1406 include/linux/device.h static inline void dev_set_uevent_suppress(struct device *dev, int val) val 1408 include/linux/device.h dev->kobj.uevent_suppress = val; val 1443 include/linux/device.h static inline void dev_pm_syscore_device(struct device *dev, bool val) val 1446 include/linux/device.h dev->power.syscore = val; val 19 include/linux/dim.h #define IS_SIGNIFICANT_DIFF(val, ref) \ val 20 include/linux/dim.h (((100UL * abs((val) - (ref))) / (ref)) > 10) val 10 include/linux/dsa/lan9303.h int regnum, u16 val); val 58 include/linux/dynamic_debug.h extern int ddebug_dyndbg_module_param_cb(char *param, char *val, val 191 include/linux/dynamic_debug.h static inline int ddebug_dyndbg_module_param_cb(char *param, char *val, val 154 include/linux/fb.h extern int fb_notifier_call_chain(unsigned long val, void *v); val 166 include/linux/fb.h static inline int fb_notifier_call_chain(unsigned long val, void *v) val 580 include/linux/fb.h #define FB_SHIFT_HIGH(p, val, bits) (fb_be_math(p) ? (val) >> (bits) : \ val 581 include/linux/fb.h (val) << (bits)) val 582 include/linux/fb.h #define FB_SHIFT_LOW(p, val, bits) (fb_be_math(p) ? (val) << (bits) : \ val 583 include/linux/fb.h (val) >> (bits)) val 712 include/linux/fb.h extern int fb_get_mode(int flags, u32 val, struct fb_var_screeninfo *var, val 50 include/linux/firmware/imx/svc/misc.h u8 ctrl, u32 val); val 53 include/linux/firmware/imx/svc/misc.h u8 ctrl, u32 *val); val 48 include/linux/firmware/trusted_foundations.h static inline void tf_dummy_write_sec(unsigned long val, unsigned int reg) val 23 include/linux/fsi.h void *val, size_t size); val 25 include/linux/fsi.h const void *val, size_t size); val 26 include/linux/fsi.h extern int fsi_device_peek(struct fsi_device *dev, void *val); val 67 include/linux/fsi.h void *val, size_t size); val 69 include/linux/fsi.h const void *val, size_t size); val 161 include/linux/fsl/ptp_qoriq.h void (*write)(unsigned __iomem *addr, u32 val); val 169 include/linux/fsl/ptp_qoriq.h static inline void qoriq_write_be(unsigned __iomem *addr, u32 val) val 171 include/linux/fsl/ptp_qoriq.h iowrite32be(val, addr); val 179 include/linux/fsl/ptp_qoriq.h static inline void qoriq_write_le(unsigned __iomem *addr, u32 val) val 181 include/linux/fsl/ptp_qoriq.h iowrite32(val, addr); val 855 include/linux/fsl_ifc.h u32 val; val 858 include/linux/fsl_ifc.h val = ioread32(addr); val 860 include/linux/fsl_ifc.h val = ioread32be(addr); val 862 include/linux/fsl_ifc.h return val; val 867 include/linux/fsl_ifc.h u16 val; val 870 include/linux/fsl_ifc.h val = ioread16(addr); val 872 include/linux/fsl_ifc.h val = ioread16be(addr); val 874 include/linux/fsl_ifc.h return val; val 882 include/linux/fsl_ifc.h static inline void ifc_out32(u32 val, void __iomem *addr) val 885 include/linux/fsl_ifc.h iowrite32(val, addr); val 887 include/linux/fsl_ifc.h iowrite32be(val, addr); val 890 include/linux/fsl_ifc.h static inline void ifc_out16(u16 val, void __iomem *addr) val 893 include/linux/fsl_ifc.h iowrite16(val, addr); val 895 include/linux/fsl_ifc.h iowrite16be(val, addr); val 898 include/linux/fsl_ifc.h static inline void ifc_out8(u8 val, void __iomem *addr) val 900 include/linux/fsl_ifc.h iowrite8(val, addr); val 78 include/linux/futex.h long do_futex(u32 __user *uaddr, int op, u32 val, ktime_t *timeout, val 85 include/linux/futex.h static inline long do_futex(u32 __user *uaddr, int op, u32 val, val 79 include/linux/fwnode.h unsigned int elem_size, void *val, val 83 include/linux/fwnode.h const char *propname, const char **val, val 58 include/linux/genl_magic_func.h __u64 val = valp ? *(__u32 *)valp : 1; val 60 include/linux/genl_magic_func.h case NLA_U8: val = (__u8)val; val 61 include/linux/genl_magic_func.h case NLA_U16: val = (__u16)val; val 62 include/linux/genl_magic_func.h case NLA_U32: val = (__u32)val; val 64 include/linux/genl_magic_func.h name, (int)val, (unsigned)val); val 67 include/linux/genl_magic_func.h val = *(__u64*)valp; val 69 include/linux/genl_magic_func.h name, (long long)val, (unsigned long long)val); val 72 include/linux/genl_magic_func.h if (val) val 79 include/linux/genl_magic_func.h const char *name, const char *val, unsigned len) val 83 include/linux/genl_magic_func.h if (len && val[len-1] == '\0') val 85 include/linux/genl_magic_func.h pr_info("%s attr %s: [len:%u] '%s'\n", dir, name, len, val); val 91 include/linux/genl_magic_func.h dir, name, len, val[0], val[1], val[2], val[3]); val 16 include/linux/hash.h #define hash_long(val, bits) hash_32(val, bits) val 18 include/linux/hash.h #define hash_long(val, bits) hash_64(val, bits) val 60 include/linux/hash.h static inline u32 __hash_32_generic(u32 val) val 62 include/linux/hash.h return val * GOLDEN_RATIO_32; val 68 include/linux/hash.h static inline u32 hash_32_generic(u32 val, unsigned int bits) val 71 include/linux/hash.h return __hash_32(val) >> (32 - bits); val 77 include/linux/hash.h static __always_inline u32 hash_64_generic(u64 val, unsigned int bits) val 81 include/linux/hash.h return val * GOLDEN_RATIO_64 >> (64 - bits); val 84 include/linux/hash.h return hash_32((u32)val ^ __hash_32(val >> 32), bits); val 96 include/linux/hash.h unsigned long val = (unsigned long)ptr; val 99 include/linux/hash.h val ^= (val >> 32); val 101 include/linux/hash.h return (u32)val; val 31 include/linux/hashtable.h #define hash_min(val, bits) \ val 32 include/linux/hashtable.h (sizeof(val) <= 4 ? hash_32(val, bits) : hash_long(val, bits)) val 187 include/linux/hdlcdrv.h unsigned short val; val 192 include/linux/hdlcdrv.h val = 0; val 195 include/linux/hdlcdrv.h val = hb->buf[hb->rd]; val 199 include/linux/hdlcdrv.h return val; val 205 include/linux/hdlcdrv.h unsigned short val) val 213 include/linux/hdlcdrv.h hb->buf[hb->wr] = val & 0xffff; val 60 include/linux/highmem.h static inline void totalhigh_pages_set(long val) val 62 include/linux/highmem.h atomic_long_set(&_totalhigh_pages, val); val 165 include/linux/hp_sdc.h #define HP_SDC_XTD_REV_STRINGS(val, str) \ val 166 include/linux/hp_sdc.h switch (val) { \ val 14 include/linux/hwmon-vid.h int vid_from_reg(int val, u8 vrm); val 21 include/linux/hwmon-vid.h static inline int vid_to_reg(int val, u8 vrm) val 26 include/linux/hwmon-vid.h return ((val >= 1100) && (val <= 1850) ? val 27 include/linux/hwmon-vid.h ((18499 - val * 10) / 25 + 5) / 10 : -1); val 358 include/linux/hwmon.h u32 attr, int channel, long *val); val 362 include/linux/hwmon.h u32 attr, int channel, long val); val 58 include/linux/i2c-algo-pca.h void (*write_byte) (void *data, int reg, int val); val 19 include/linux/i2c-algo-pcf.h void (*setpcf) (void *data, int ctl, int val); val 15 include/linux/i2c-pxa.h void (*write)(void *ptr, unsigned int val); val 40 include/linux/i2c.h enum i2c_slave_event event, u8 *val); val 376 include/linux/i2c.h enum i2c_slave_event event, u8 *val) val 378 include/linux/i2c.h return client->slave_cb(client, event, val); val 615 include/linux/i2c.h void (*set_scl)(struct i2c_adapter *adap, int val); val 617 include/linux/i2c.h void (*set_sda)(struct i2c_adapter *adap, int val); val 1262 include/linux/ide.h u8 val; /* value of masked reg when "enabled" */ val 79 include/linux/idr.h static inline void idr_set_cursor(struct idr *idr, unsigned int val) val 81 include/linux/idr.h WRITE_ONCE(idr->idr_next, val); val 113 include/linux/iio/adc/ad_sigma_delta.h unsigned int size, unsigned int val); val 115 include/linux/iio/adc/ad_sigma_delta.h unsigned int size, unsigned int *val); val 121 include/linux/iio/adc/ad_sigma_delta.h const struct iio_chan_spec *chan, int *val); val 158 include/linux/iio/common/cros_ec_sensors_core.h int *val, int *val2, long mask); val 190 include/linux/iio/common/cros_ec_sensors_core.h int val, int val2, long mask); val 304 include/linux/iio/common/st_sensors.h struct iio_chan_spec const *ch, int *val); val 196 include/linux/iio/consumer.h int *val); val 209 include/linux/iio/consumer.h int iio_read_channel_average_raw(struct iio_channel *chan, int *val); val 224 include/linux/iio/consumer.h int iio_read_channel_processed(struct iio_channel *chan, int *val); val 235 include/linux/iio/consumer.h int iio_write_channel_attribute(struct iio_channel *chan, int val, val 249 include/linux/iio/consumer.h int iio_read_channel_attribute(struct iio_channel *chan, int *val, val 260 include/linux/iio/consumer.h int iio_write_channel_raw(struct iio_channel *chan, int val); val 271 include/linux/iio/consumer.h int iio_read_max_channel_raw(struct iio_channel *chan, int *val); val 324 include/linux/iio/consumer.h int iio_read_channel_offset(struct iio_channel *chan, int *val, val 337 include/linux/iio/consumer.h int iio_read_channel_scale(struct iio_channel *chan, int *val, val 116 include/linux/iio/gyro/itg3200.h u8 reg_address, u8 val); val 119 include/linux/iio/gyro/itg3200.h u8 reg_address, u8 *val); val 399 include/linux/iio/iio.h int *val, val 419 include/linux/iio/iio.h int val, val 442 include/linux/iio/iio.h enum iio_event_info info, int *val, int *val2); val 448 include/linux/iio/iio.h enum iio_event_info info, int val, int val2); val 459 include/linux/iio/iio.h int (*hwfifo_set_watermark)(struct iio_dev *indio_dev, unsigned val); val 79 include/linux/iio/imu/adis.h unsigned int val, unsigned int size); val 81 include/linux/iio/imu/adis.h unsigned int *val, unsigned int size); val 90 include/linux/iio/imu/adis.h uint8_t val) val 92 include/linux/iio/imu/adis.h return adis_write_reg(adis, reg, val, 1); val 102 include/linux/iio/imu/adis.h uint16_t val) val 104 include/linux/iio/imu/adis.h return adis_write_reg(adis, reg, val, 2); val 114 include/linux/iio/imu/adis.h uint32_t val) val 116 include/linux/iio/imu/adis.h return adis_write_reg(adis, reg, val, 4); val 126 include/linux/iio/imu/adis.h uint16_t *val) val 132 include/linux/iio/imu/adis.h *val = tmp; val 144 include/linux/iio/imu/adis.h uint32_t *val) val 150 include/linux/iio/imu/adis.h *val = tmp; val 162 include/linux/iio/imu/adis.h int *val); val 64 include/linux/inetdevice.h int val) val 68 include/linux/inetdevice.h in_dev->cnf.data[index] = val; val 78 include/linux/inetdevice.h #define IN_DEV_CONF_SET(in_dev, attr, val) \ val 79 include/linux/inetdevice.h ipv4_devconf_set((in_dev), IPV4_DEVCONF_ ## attr, (val)) val 478 include/linux/input.h unsigned int axis, int val) \ val 482 include/linux/input.h dev->absinfo[axis]._item = val; \ val 485 include/linux/input.h INPUT_GENERATE_ABS_ACCESSORS(val, value) val 21 include/linux/input/lm8333.h extern int lm8333_write8(struct lm8333 *lm8333, u8 cmd, u8 val); val 12 include/linux/input/matrix_keypad.h #define KEY(row, col, val) ((((row) & (MATRIX_MAX_ROWS - 1)) << 24) |\ val 14 include/linux/input/matrix_keypad.h ((val) & 0xffff)) val 197 include/linux/intel-iommu.h #define DMA_TLB_IAIG(val) (((val) >> 57) & 3) val 603 include/linux/intel-iommu.h u64 val; val 608 include/linux/intel-iommu.h pte->val = 0; val 614 include/linux/intel-iommu.h return pte->val & VTD_PAGE_MASK; val 617 include/linux/intel-iommu.h return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; val 623 include/linux/intel-iommu.h return (pte->val & 3) != 0; val 628 include/linux/intel-iommu.h return (pte->val & DMA_PTE_LARGE_PAGE); val 709 include/linux/interrupt.h static inline int probe_irq_off(unsigned long val) val 713 include/linux/interrupt.h static inline unsigned int probe_irq_mask(unsigned long val) val 19 include/linux/io-64-nonatomic-hi-lo.h static inline void hi_lo_writeq(__u64 val, volatile void __iomem *addr) val 21 include/linux/io-64-nonatomic-hi-lo.h writel(val >> 32, addr + 4); val 22 include/linux/io-64-nonatomic-hi-lo.h writel(val, addr); val 36 include/linux/io-64-nonatomic-hi-lo.h static inline void hi_lo_writeq_relaxed(__u64 val, volatile void __iomem *addr) val 38 include/linux/io-64-nonatomic-hi-lo.h writel_relaxed(val >> 32, addr + 4); val 39 include/linux/io-64-nonatomic-hi-lo.h writel_relaxed(val, addr); val 73 include/linux/io-64-nonatomic-hi-lo.h static inline void iowrite64_hi_lo(u64 val, void __iomem *addr) val 75 include/linux/io-64-nonatomic-hi-lo.h iowrite32(val >> 32, addr + sizeof(u32)); val 76 include/linux/io-64-nonatomic-hi-lo.h iowrite32(val, addr); val 95 include/linux/io-64-nonatomic-hi-lo.h static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr) val 97 include/linux/io-64-nonatomic-hi-lo.h iowrite32be(val >> 32, addr); val 98 include/linux/io-64-nonatomic-hi-lo.h iowrite32be(val, addr + sizeof(u32)); val 19 include/linux/io-64-nonatomic-lo-hi.h static inline void lo_hi_writeq(__u64 val, volatile void __iomem *addr) val 21 include/linux/io-64-nonatomic-lo-hi.h writel(val, addr); val 22 include/linux/io-64-nonatomic-lo-hi.h writel(val >> 32, addr + 4); val 36 include/linux/io-64-nonatomic-lo-hi.h static inline void lo_hi_writeq_relaxed(__u64 val, volatile void __iomem *addr) val 38 include/linux/io-64-nonatomic-lo-hi.h writel_relaxed(val, addr); val 39 include/linux/io-64-nonatomic-lo-hi.h writel_relaxed(val >> 32, addr + 4); val 73 include/linux/io-64-nonatomic-lo-hi.h static inline void iowrite64_lo_hi(u64 val, void __iomem *addr) val 75 include/linux/io-64-nonatomic-lo-hi.h iowrite32(val, addr); val 76 include/linux/io-64-nonatomic-lo-hi.h iowrite32(val >> 32, addr + sizeof(u32)); val 95 include/linux/io-64-nonatomic-lo-hi.h static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr) val 97 include/linux/io-64-nonatomic-lo-hi.h iowrite32be(val, addr + sizeof(u32)); val 98 include/linux/io-64-nonatomic-lo-hi.h iowrite32be(val >> 32, addr); val 34 include/linux/iopoll.h #define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \ val 41 include/linux/iopoll.h (val) = op(addr); \ val 46 include/linux/iopoll.h (val) = op(addr); \ val 72 include/linux/iopoll.h #define readx_poll_timeout_atomic(op, addr, val, cond, delay_us, timeout_us) \ val 78 include/linux/iopoll.h (val) = op(addr); \ val 83 include/linux/iopoll.h (val) = op(addr); \ val 93 include/linux/iopoll.h #define readb_poll_timeout(addr, val, cond, delay_us, timeout_us) \ val 94 include/linux/iopoll.h readx_poll_timeout(readb, addr, val, cond, delay_us, timeout_us) val 96 include/linux/iopoll.h #define readb_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ val 97 include/linux/iopoll.h readx_poll_timeout_atomic(readb, addr, val, cond, delay_us, timeout_us) val 99 include/linux/iopoll.h #define readw_poll_timeout(addr, val, cond, delay_us, timeout_us) \ val 100 include/linux/iopoll.h readx_poll_timeout(readw, addr, val, cond, delay_us, timeout_us) val 102 include/linux/iopoll.h #define readw_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ val 103 include/linux/iopoll.h readx_poll_timeout_atomic(readw, addr, val, cond, delay_us, timeout_us) val 105 include/linux/iopoll.h #define readl_poll_timeout(addr, val, cond, delay_us, timeout_us) \ val 106 include/linux/iopoll.h readx_poll_timeout(readl, addr, val, cond, delay_us, timeout_us) val 108 include/linux/iopoll.h #define readl_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ val 109 include/linux/iopoll.h readx_poll_timeout_atomic(readl, addr, val, cond, delay_us, timeout_us) val 111 include/linux/iopoll.h #define readq_poll_timeout(addr, val, cond, delay_us, timeout_us) \ val 112 include/linux/iopoll.h readx_poll_timeout(readq, addr, val, cond, delay_us, timeout_us) val 114 include/linux/iopoll.h #define readq_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ val 115 include/linux/iopoll.h readx_poll_timeout_atomic(readq, addr, val, cond, delay_us, timeout_us) val 117 include/linux/iopoll.h #define readb_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \ val 118 include/linux/iopoll.h readx_poll_timeout(readb_relaxed, addr, val, cond, delay_us, timeout_us) val 120 include/linux/iopoll.h #define readb_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ val 121 include/linux/iopoll.h readx_poll_timeout_atomic(readb_relaxed, addr, val, cond, delay_us, timeout_us) val 123 include/linux/iopoll.h #define readw_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \ val 124 include/linux/iopoll.h readx_poll_timeout(readw_relaxed, addr, val, cond, delay_us, timeout_us) val 126 include/linux/iopoll.h #define readw_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ val 127 include/linux/iopoll.h readx_poll_timeout_atomic(readw_relaxed, addr, val, cond, delay_us, timeout_us) val 129 include/linux/iopoll.h #define readl_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \ val 130 include/linux/iopoll.h readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us) val 132 include/linux/iopoll.h #define readl_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ val 133 include/linux/iopoll.h readx_poll_timeout_atomic(readl_relaxed, addr, val, cond, delay_us, timeout_us) val 135 include/linux/iopoll.h #define readq_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \ val 136 include/linux/iopoll.h readx_poll_timeout(readq_relaxed, addr, val, cond, delay_us, timeout_us) val 138 include/linux/iopoll.h #define readq_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ val 139 include/linux/iopoll.h readx_poll_timeout_atomic(readq_relaxed, addr, val, cond, delay_us, timeout_us) val 255 include/linux/ipmi.h int ipmi_set_gets_events(struct ipmi_user *user, bool val); val 1011 include/linux/irq.h void (*reg_writel)(u32 val, void __iomem *addr); val 1161 include/linux/irq.h u32 val, int reg_offset) val 1164 include/linux/irq.h gc->reg_writel(val, gc->reg_base + reg_offset); val 1166 include/linux/irq.h writel(val, gc->reg_base + reg_offset); val 628 include/linux/irqchip/arm-gic-v3.h u32 val; val 630 include/linux/irqchip/arm-gic-v3.h val = gic_read_sre(); val 631 include/linux/irqchip/arm-gic-v3.h if (val & ICC_SRE_EL1_SRE) val 634 include/linux/irqchip/arm-gic-v3.h val |= ICC_SRE_EL1_SRE; val 635 include/linux/irqchip/arm-gic-v3.h gic_write_sre(val); val 636 include/linux/irqchip/arm-gic-v3.h val = gic_read_sre(); val 638 include/linux/irqchip/arm-gic-v3.h return !!(val & ICC_SRE_EL1_SRE); val 67 include/linux/isapnp.h void isapnp_write_byte(unsigned char idx, unsigned char val); val 93 include/linux/isapnp.h static inline void isapnp_write_byte(unsigned char idx, unsigned char val) { ; } val 33 include/linux/isdn/capiutil.h static inline void capimsg_setu8(void *m, int off, __u8 val) val 35 include/linux/isdn/capiutil.h ((__u8 *)m)[off] = val; val 38 include/linux/isdn/capiutil.h static inline void capimsg_setu16(void *m, int off, __u16 val) val 40 include/linux/isdn/capiutil.h ((__u8 *)m)[off] = val & 0xff; val 41 include/linux/isdn/capiutil.h ((__u8 *)m)[off+1] = (val >> 8) & 0xff; val 44 include/linux/isdn/capiutil.h static inline void capimsg_setu32(void *m, int off, __u32 val) val 46 include/linux/isdn/capiutil.h ((__u8 *)m)[off] = val & 0xff; val 47 include/linux/isdn/capiutil.h ((__u8 *)m)[off+1] = (val >> 8) & 0xff; val 48 include/linux/isdn/capiutil.h ((__u8 *)m)[off+2] = (val >> 16) & 0xff; val 49 include/linux/isdn/capiutil.h ((__u8 *)m)[off+3] = (val >> 24) & 0xff; val 93 include/linux/iversion.h inode_set_iversion_raw(struct inode *inode, u64 val) val 95 include/linux/iversion.h atomic64_set(&inode->i_version, val); val 124 include/linux/iversion.h inode_set_max_iversion_raw(struct inode *inode, u64 val) val 130 include/linux/iversion.h if (cur > val) val 132 include/linux/iversion.h old = atomic64_cmpxchg(&inode->i_version, cur, val); val 152 include/linux/iversion.h inode_set_iversion(struct inode *inode, u64 val) val 154 include/linux/iversion.h inode_set_iversion_raw(inode, val << I_VERSION_QUERIED_SHIFT); val 174 include/linux/iversion.h inode_set_iversion_queried(struct inode *inode, u64 val) val 176 include/linux/iversion.h inode_set_iversion_raw(inode, (val << I_VERSION_QUERIED_SHIFT) | val 387 include/linux/jbd2.h int val = (expr); \ val 388 include/linux/jbd2.h if (!val) { \ val 394 include/linux/jbd2.h val; \ val 17 include/linux/jz4740-adc.h int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val); val 5 include/linux/kbuild.h #define DEFINE(sym, val) \ val 6 include/linux/kbuild.h asm volatile("\n.ascii \"->" #sym " %0 " #val "\"" : : "i" (val)) val 14 include/linux/kconfig.h #define __take_second_arg(__ignored, val, ...) val val 42 include/linux/kconfig.h #define ___is_defined(val) ____is_defined(__ARG_PLACEHOLDER_##val) val 20 include/linux/kdebug.h int notify_die(enum die_val val, const char *str, val 34 include/linux/kdev_t.h static inline dev_t old_decode_dev(u16 val) val 36 include/linux/kdev_t.h return MKDEV((val >> 8) & 255, val & 255); val 306 include/linux/kernel.h static inline u32 reciprocal_scale(u32 val, u32 ep_ro) val 308 include/linux/kernel.h return (u32)(((u64) val * ep_ro) >> 32); val 502 include/linux/kernel.h extern char *next_arg(char *args, char **param, char **val); val 919 include/linux/kernel.h #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) val 954 include/linux/kernel.h #define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi) val 967 include/linux/kernel.h #define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi) val 163 include/linux/kfifo.h __kfifo_uint_must_check_helper(unsigned int val) val 165 include/linux/kfifo.h return val; val 169 include/linux/kfifo.h __kfifo_int_must_check_helper(int val) val 171 include/linux/kfifo.h return val; val 374 include/linux/kfifo.h #define kfifo_put(fifo, val) \ val 377 include/linux/kfifo.h typeof(*__tmp->const_type) __val = (val); \ val 411 include/linux/kfifo.h #define kfifo_get(fifo, val) \ val 415 include/linux/kfifo.h typeof(__tmp->ptr) __val = (val); \ val 450 include/linux/kfifo.h #define kfifo_peek(fifo, val) \ val 454 include/linux/kfifo.h typeof(__tmp->ptr) __val = (val); \ val 188 include/linux/kvm_host.h int len, const void *val); val 190 include/linux/kvm_host.h gpa_t addr, int len, const void *val, long cookie); val 192 include/linux/kvm_host.h int len, void *val); val 1311 include/linux/kvm_host.h static inline void kvm_vcpu_set_in_spin_loop(struct kvm_vcpu *vcpu, bool val) val 1313 include/linux/kvm_host.h vcpu->spin_loop.in_spin_loop = val; val 1315 include/linux/kvm_host.h static inline void kvm_vcpu_set_dy_eligible(struct kvm_vcpu *vcpu, bool val) val 1317 include/linux/kvm_host.h vcpu->spin_loop.dy_eligible = val; val 1322 include/linux/kvm_host.h static inline void kvm_vcpu_set_in_spin_loop(struct kvm_vcpu *vcpu, bool val) val 1326 include/linux/kvm_host.h static inline void kvm_vcpu_set_dy_eligible(struct kvm_vcpu *vcpu, bool val) val 62 include/linux/led-class-flash.h u32 val; val 931 include/linux/libata.h int (*scr_read)(struct ata_link *link, unsigned int sc_reg, u32 *val); val 932 include/linux/libata.h int (*scr_write)(struct ata_link *link, unsigned int sc_reg, u32 val); val 979 include/linux/libata.h enum sw_activity val); val 1127 include/linux/libata.h extern int sata_scr_read(struct ata_link *link, int reg, u32 *val); val 1128 include/linux/libata.h extern int sata_scr_write(struct ata_link *link, int reg, u32 val); val 1129 include/linux/libata.h extern int sata_scr_write_flush(struct ata_link *link, int reg, u32 val); val 1148 include/linux/libata.h u32 val, unsigned long interval, unsigned long timeout); val 1219 include/linux/libata.h unsigned long val; val 380 include/linux/lockdep.h struct pin_cookie { unsigned int val; }; val 382 include/linux/lockdep.h #define NIL_COOKIE (struct pin_cookie){ .val = 0U, } val 32 include/linux/logic_pio.h void (*out)(void *hostdata, unsigned long addr, u32 val, val 1515 include/linux/lsm_hooks.h int (*sb_add_mnt_opt)(const char *option, const char *val, int len, val 129 include/linux/mdio.h u16 addr, u16 val); val 318 include/linux/mdio.h int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val); val 322 include/linux/mdio.h int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val); val 323 include/linux/mdio.h int mdiobus_write_nested(struct mii_bus *bus, int addr, u32 regnum, u16 val); val 623 include/linux/memcontrol.h void __mod_memcg_state(struct mem_cgroup *memcg, int idx, int val); val 627 include/linux/memcontrol.h int idx, int val) val 632 include/linux/memcontrol.h __mod_memcg_state(memcg, idx, val); val 654 include/linux/memcontrol.h int idx, int val) val 657 include/linux/memcontrol.h __mod_memcg_state(page->mem_cgroup, idx, val); val 661 include/linux/memcontrol.h int idx, int val) val 664 include/linux/memcontrol.h mod_memcg_state(page->mem_cgroup, idx, val); val 706 include/linux/memcontrol.h int val); val 707 include/linux/memcontrol.h void __mod_lruvec_slab_state(void *p, enum node_stat_item idx, int val); val 708 include/linux/memcontrol.h void mod_memcg_obj_state(void *p, int idx, int val); val 711 include/linux/memcontrol.h enum node_stat_item idx, int val) val 716 include/linux/memcontrol.h __mod_lruvec_state(lruvec, idx, val); val 721 include/linux/memcontrol.h enum node_stat_item idx, int val) val 728 include/linux/memcontrol.h __mod_node_page_state(pgdat, idx, val); val 733 include/linux/memcontrol.h __mod_lruvec_state(lruvec, idx, val); val 737 include/linux/memcontrol.h enum node_stat_item idx, int val) val 742 include/linux/memcontrol.h __mod_lruvec_page_state(page, idx, val); val 1103 include/linux/memcontrol.h enum node_stat_item idx, int val) val 1105 include/linux/memcontrol.h __mod_node_page_state(lruvec_pgdat(lruvec), idx, val); val 1109 include/linux/memcontrol.h enum node_stat_item idx, int val) val 1111 include/linux/memcontrol.h mod_node_page_state(lruvec_pgdat(lruvec), idx, val); val 1115 include/linux/memcontrol.h enum node_stat_item idx, int val) val 1117 include/linux/memcontrol.h __mod_node_page_state(page_pgdat(page), idx, val); val 1121 include/linux/memcontrol.h enum node_stat_item idx, int val) val 1123 include/linux/memcontrol.h mod_node_page_state(page_pgdat(page), idx, val); val 1127 include/linux/memcontrol.h int val) val 1131 include/linux/memcontrol.h __mod_node_page_state(page_pgdat(page), idx, val); val 1134 include/linux/memcontrol.h static inline void mod_memcg_obj_state(void *p, int idx, int val) val 93 include/linux/memory.h static inline int memory_notify(unsigned long val, void *v) val 104 include/linux/memory.h static inline int memory_isolate_notify(unsigned long val, void *v) val 116 include/linux/memory.h extern int memory_notify(unsigned long val, void *v); val 117 include/linux/memory.h extern int memory_isolate_notify(unsigned long val, void *v); val 133 include/linux/mfd/aat2870.h int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val); val 134 include/linux/mfd/aat2870.h int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val); val 135 include/linux/mfd/aat2870.h int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val); val 287 include/linux/mfd/adp5520.h extern int adp5520_read(struct device *dev, int reg, uint8_t *val); val 288 include/linux/mfd/adp5520.h extern int adp5520_write(struct device *dev, int reg, u8 val); val 409 include/linux/mfd/as3722.h u32 mask, u8 val) val 411 include/linux/mfd/as3722.h return regmap_update_bits(as3722->regmap, reg, mask, val); val 310 include/linux/mfd/asic3.h extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val); val 241 include/linux/mfd/da903x.h extern int da903x_write(struct device *dev, int reg, uint8_t val); val 242 include/linux/mfd/da903x.h extern int da903x_writes(struct device *dev, int reg, int len, uint8_t *val); val 243 include/linux/mfd/da903x.h extern int da903x_read(struct device *dev, int reg, uint8_t *val); val 244 include/linux/mfd/da903x.h extern int da903x_reads(struct device *dev, int reg, int len, uint8_t *val); val 245 include/linux/mfd/da903x.h extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask); val 107 include/linux/mfd/da9052/da9052.h int val, ret; val 109 include/linux/mfd/da9052/da9052.h ret = regmap_read(da9052->regmap, reg, &val); val 119 include/linux/mfd/da9052/da9052.h return val; val 123 include/linux/mfd/da9052/da9052.h unsigned char val) val 127 include/linux/mfd/da9052/da9052.h ret = regmap_write(da9052->regmap, reg, val); val 141 include/linux/mfd/da9052/da9052.h unsigned reg_cnt, unsigned char *val) val 149 include/linux/mfd/da9052/da9052.h val[i] = (unsigned char)tmp; val 164 include/linux/mfd/da9052/da9052.h unsigned reg_cnt, unsigned char *val) val 170 include/linux/mfd/da9052/da9052.h ret = regmap_write(da9052->regmap, reg + i, val[i]); val 40 include/linux/mfd/da9055/core.h int val, ret; val 42 include/linux/mfd/da9055/core.h ret = regmap_read(da9055->regmap, reg, &val); val 46 include/linux/mfd/da9055/core.h return val; val 50 include/linux/mfd/da9055/core.h unsigned char val) val 52 include/linux/mfd/da9055/core.h return regmap_write(da9055->regmap, reg, val); val 56 include/linux/mfd/da9055/core.h unsigned reg_cnt, unsigned char *val) val 58 include/linux/mfd/da9055/core.h return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt); val 62 include/linux/mfd/da9055/core.h unsigned reg_cnt, unsigned char *val) val 64 include/linux/mfd/da9055/core.h return regmap_raw_write(da9055->regmap, reg, val, reg_cnt); val 75 include/linux/mfd/da9150/core.h void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val); val 76 include/linux/mfd/da9150/core.h void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val); val 520 include/linux/mfd/db8500-prcmu.h int db8500_prcmu_load_a9wdog(u8 id, u32 val); val 734 include/linux/mfd/db8500-prcmu.h static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val) val 18 include/linux/mfd/htc-pasic3.h extern void pasic3_write_register(struct device *dev, u32 reg, u8 val); val 433 include/linux/mfd/intel_msic.h extern int intel_msic_reg_read(unsigned short reg, u8 *val); val 434 include/linux/mfd/intel_msic.h extern int intel_msic_reg_write(unsigned short reg, u8 val); val 435 include/linux/mfd/intel_msic.h extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask); val 451 include/linux/mfd/intel_msic.h u8 *val); val 89 include/linux/mfd/lm3533.h extern int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val); val 90 include/linux/mfd/lm3533.h extern int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val); val 93 include/linux/mfd/lm3533.h extern int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val); val 94 include/linux/mfd/lm3533.h extern int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val); val 96 include/linux/mfd/lm3533.h extern int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val); val 97 include/linux/mfd/lm3533.h extern int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val); val 98 include/linux/mfd/lm3533.h extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask); val 187 include/linux/mfd/lp8788.h u8 val; val 444 include/linux/mfd/max14577-private.h unsigned int val; val 447 include/linux/mfd/max14577-private.h ret = regmap_read(map, reg, &val); val 448 include/linux/mfd/max14577-private.h *dest = val; val 471 include/linux/mfd/max14577-private.h u8 val) val 473 include/linux/mfd/max14577-private.h return regmap_update_bits(map, reg, mask, val); val 409 include/linux/mfd/max8997-private.h extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); val 167 include/linux/mfd/max8998-private.h extern int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); val 16 include/linux/mfd/mc13xxx.h int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val); val 17 include/linux/mfd/mc13xxx.h int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val); val 19 include/linux/mfd/mc13xxx.h u32 mask, u32 val); val 39 include/linux/mfd/menelaus.h extern int menelaus_set_regulator_sleep(int enable, u32 val); val 260 include/linux/mfd/motorola-cpcap.h unsigned int val; val 263 include/linux/mfd/motorola-cpcap.h ret = regmap_read(regmap, CPCAP_REG_VERSC1, &val); val 270 include/linux/mfd/motorola-cpcap.h *revision = ((val >> 3) & 0x7) | ((val << 3) & 0x38); val 279 include/linux/mfd/motorola-cpcap.h unsigned int val; val 282 include/linux/mfd/motorola-cpcap.h ret = regmap_read(regmap, CPCAP_REG_VERSC1, &val); val 289 include/linux/mfd/motorola-cpcap.h *vendor = (val >> 6) & 0x7; val 3752 include/linux/mfd/palmas.h unsigned int reg, unsigned int *val) val 3757 include/linux/mfd/palmas.h return regmap_read(palmas->regmap[slave_id], addr, val); val 3770 include/linux/mfd/palmas.h unsigned int reg, const void *val, size_t val_count) val 3776 include/linux/mfd/palmas.h val, val_count); val 3780 include/linux/mfd/palmas.h unsigned int reg, void *val, size_t val_count) val 3786 include/linux/mfd/palmas.h val, val_count); val 3790 include/linux/mfd/palmas.h unsigned int reg, unsigned int mask, unsigned int val) val 3795 include/linux/mfd/palmas.h return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); val 66 include/linux/mfd/pcf50633/core.h int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); val 68 include/linux/mfd/pcf50633/core.h int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); val 38 include/linux/mfd/pcf50633/gpio.h int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val); val 326 include/linux/mfd/rc5t583.h static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) val 329 include/linux/mfd/rc5t583.h return regmap_write(rc5t583->regmap, reg, val); val 332 include/linux/mfd/rc5t583.h static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val) val 339 include/linux/mfd/rc5t583.h *val = (uint8_t)ival; val 358 include/linux/mfd/rc5t583.h unsigned int val, unsigned int mask) val 361 include/linux/mfd/rc5t583.h return regmap_update_bits(rc5t583->regmap, reg, mask, val); val 196 include/linux/mfd/sta2x11-mfd.h sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) val 198 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg); val 229 include/linux/mfd/sta2x11-mfd.h u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) val 231 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl); val 368 include/linux/mfd/sta2x11-mfd.h u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) val 370 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs); val 154 include/linux/mfd/stmpe.h extern int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val); val 99 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_CSA(cs, val) (val << (cs)) val 131 include/linux/mfd/tc3589x.h extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val); val 51 include/linux/mfd/ti_am335x_tscadc.h #define STEPENB(val) ((val) << 0) val 52 include/linux/mfd/ti_am335x_tscadc.h #define ENB(val) (1 << (val)) val 69 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_MODE(val) ((val) << 0) val 73 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_AVG(val) ((val) << 2) val 81 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_RFP(val) ((val) << 12) val 84 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_INM(val) ((val) << 15) val 87 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_INP(val) ((val) << 19) val 91 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_RFM(val) ((val) << 23) val 96 include/linux/mfd/ti_am335x_tscadc.h #define STEPDELAY_OPEN(val) ((val) << 0) val 99 include/linux/mfd/ti_am335x_tscadc.h #define STEPDELAY_SAMPLE(val) ((val) << 24) val 104 include/linux/mfd/ti_am335x_tscadc.h #define STEPCHARGE_RFP(val) ((val) << 12) val 107 include/linux/mfd/ti_am335x_tscadc.h #define STEPCHARGE_INM(val) ((val) << 15) val 110 include/linux/mfd/ti_am335x_tscadc.h #define STEPCHARGE_INP(val) ((val) << 19) val 112 include/linux/mfd/ti_am335x_tscadc.h #define STEPCHARGE_RFM(val) ((val) << 23) val 117 include/linux/mfd/ti_am335x_tscadc.h #define CHARGEDLY_OPEN(val) ((val) << 0) val 126 include/linux/mfd/ti_am335x_tscadc.h #define CNTRLREG_AFE_CTRL(val) ((val) << 5) val 197 include/linux/mfd/ti_am335x_tscadc.h void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val); val 198 include/linux/mfd/ti_am335x_tscadc.h void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val); val 199 include/linux/mfd/ti_am335x_tscadc.h void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val); val 19 include/linux/mfd/tmio.h #define tmio_iowrite8(val, addr) writeb((val), (addr)) val 20 include/linux/mfd/tmio.h #define tmio_iowrite16(val, addr) writew((val), (addr)) val 22 include/linux/mfd/tmio.h #define tmio_iowrite32(val, addr) \ val 24 include/linux/mfd/tmio.h writew((val), (addr)); \ val 25 include/linux/mfd/tmio.h writew((val) >> 16, (addr) + 2); \ val 28 include/linux/mfd/tmio.h #define sd_config_write8(base, shift, reg, val) \ val 29 include/linux/mfd/tmio.h tmio_iowrite8((val), (base) + ((reg) << (shift))) val 30 include/linux/mfd/tmio.h #define sd_config_write16(base, shift, reg, val) \ val 31 include/linux/mfd/tmio.h tmio_iowrite16((val), (base) + ((reg) << (shift))) val 32 include/linux/mfd/tmio.h #define sd_config_write32(base, shift, reg, val) \ val 34 include/linux/mfd/tmio.h tmio_iowrite16((val), (base) + ((reg) << (shift))); \ val 35 include/linux/mfd/tmio.h tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ val 114 include/linux/mfd/tps65090.h static inline int tps65090_write(struct device *dev, int reg, uint8_t val) val 118 include/linux/mfd/tps65090.h return regmap_write(tps->rmap, reg, val); val 121 include/linux/mfd/tps65090.h static inline int tps65090_read(struct device *dev, int reg, uint8_t *val) val 129 include/linux/mfd/tps65090.h *val = temp_val; val 281 include/linux/mfd/tps65217.h unsigned int *val); val 283 include/linux/mfd/tps65217.h unsigned int val, unsigned int level); val 285 include/linux/mfd/tps65217.h unsigned int mask, unsigned int val, unsigned int level); val 275 include/linux/mfd/tps65218.h unsigned int val, unsigned int level); val 277 include/linux/mfd/tps65218.h unsigned int mask, unsigned int val, unsigned int level); val 101 include/linux/mfd/tps6586x.h extern int tps6586x_write(struct device *dev, int reg, uint8_t val); val 102 include/linux/mfd/tps6586x.h extern int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val); val 103 include/linux/mfd/tps6586x.h extern int tps6586x_read(struct device *dev, int reg, uint8_t *val); val 104 include/linux/mfd/tps6586x.h extern int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val); val 107 include/linux/mfd/tps6586x.h extern int tps6586x_update(struct device *dev, int reg, uint8_t val, val 917 include/linux/mfd/tps65910.h unsigned int *val) val 919 include/linux/mfd/tps65910.h return regmap_read(tps65910->regmap, reg, val); val 923 include/linux/mfd/tps65910.h unsigned int val) val 925 include/linux/mfd/tps65910.h return regmap_write(tps65910->regmap, reg, val); val 941 include/linux/mfd/tps65910.h u8 mask, u8 val) val 943 include/linux/mfd/tps65910.h return regmap_update_bits(tps65910->regmap, reg, mask, val); val 548 include/linux/mfd/tps80031.h int reg, uint8_t val) val 552 include/linux/mfd/tps80031.h return regmap_write(tps80031->regmap[sid], reg, val); val 556 include/linux/mfd/tps80031.h int len, uint8_t *val) val 560 include/linux/mfd/tps80031.h return regmap_bulk_write(tps80031->regmap[sid], reg, val, len); val 564 include/linux/mfd/tps80031.h int reg, uint8_t *val) val 576 include/linux/mfd/tps80031.h *val = ival; val 581 include/linux/mfd/tps80031.h int reg, int len, uint8_t *val) val 585 include/linux/mfd/tps80031.h return regmap_bulk_read(tps80031->regmap[sid], reg, val, len); val 606 include/linux/mfd/tps80031.h int reg, uint8_t val, uint8_t mask) val 610 include/linux/mfd/tps80031.h return regmap_update_bits(tps80031->regmap[sid], reg, mask, val); val 175 include/linux/mfd/twl.h static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { val 176 include/linux/mfd/twl.h return twl_i2c_write(mod_no, &val, reg, 1); val 179 include/linux/mfd/twl.h static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { val 180 include/linux/mfd/twl.h return twl_i2c_read(mod_no, val, reg, 1); val 183 include/linux/mfd/twl.h static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) { val 184 include/linux/mfd/twl.h val = cpu_to_le16(val); val 185 include/linux/mfd/twl.h return twl_i2c_write(mod_no, (u8*) &val, reg, 2); val 188 include/linux/mfd/twl.h static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) { val 190 include/linux/mfd/twl.h ret = twl_i2c_read(mod_no, (u8*) val, reg, 2); val 191 include/linux/mfd/twl.h *val = le16_to_cpu(*val); val 237 include/linux/mfd/twl6040.h u8 val); val 209 include/linux/mfd/ucb1x00.h static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val) val 211 include/linux/mfd/ucb1x00.h mcp_reg_write(ucb->mcp, reg, val); val 407 include/linux/mfd/wm831x/core.h unsigned short val); val 411 include/linux/mfd/wm831x/core.h unsigned short mask, unsigned short val); val 648 include/linux/mfd/wm8350/core.h int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val); val 84 include/linux/mfd/wm8994/core.h unsigned int val; val 87 include/linux/mfd/wm8994/core.h ret = regmap_read(wm8994->regmap, reg, &val); val 92 include/linux/mfd/wm8994/core.h return val; val 96 include/linux/mfd/wm8994/core.h unsigned short val) val 98 include/linux/mfd/wm8994/core.h return regmap_write(wm8994->regmap, reg, val); val 114 include/linux/mfd/wm8994/core.h unsigned short mask, unsigned short val) val 116 include/linux/mfd/wm8994/core.h return regmap_update_bits(wm8994->regmap, reg, mask, val); val 30 include/linux/mii.h void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val); val 1463 include/linux/mlx4/device.h int i, int val); val 55 include/linux/mlx4/doorbell.h static inline void mlx4_write64(__be32 val[2], void __iomem *dest, val 58 include/linux/mlx4/doorbell.h __raw_writeq(*(u64 *) val, dest); val 73 include/linux/mlx4/doorbell.h static inline void mlx4_write64(__be32 val[2], void __iomem *dest, val 79 include/linux/mlx4/doorbell.h __raw_writel((__force u32) val[0], dest); val 80 include/linux/mlx4/doorbell.h __raw_writel((__force u32) val[1], dest + 4); val 50 include/linux/mlx5/doorbell.h static inline void mlx5_write64(__be32 val[2], void __iomem *dest) val 53 include/linux/mlx5/doorbell.h __raw_writeq(*(u64 *)val, dest); val 55 include/linux/mlx5/doorbell.h __raw_writel((__force u32) val[0], dest); val 56 include/linux/mlx5/doorbell.h __raw_writel((__force u32) val[1], dest + 4); val 73 include/linux/mm.h static inline void totalram_pages_set(long val) val 75 include/linux/mm.h atomic_long_set(&_totalram_pages, val); val 1645 include/linux/mm.h long val = atomic_long_read(&mm->rss_stat.count[member]); val 1652 include/linux/mm.h if (val < 0) val 1653 include/linux/mm.h val = 0; val 1655 include/linux/mm.h return (unsigned long)val; val 2218 include/linux/mm.h extern void si_meminfo(struct sysinfo * val); val 2219 include/linux/mm.h extern void si_meminfo_node(struct sysinfo *val, int nid); val 754 include/linux/mm_types.h unsigned long val; val 86 include/linux/mmc/sh_mmcif.h static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val) val 88 include/linux/mmc/sh_mmcif.h __raw_writel(val, addr + reg); val 51 include/linux/moduleparam.h int (*set)(const char *val, const struct kernel_param *kp); val 320 include/linux/moduleparam.h int (*unknown)(char *param, char *val, val 340 include/linux/moduleparam.h extern int param_set_byte(const char *val, const struct kernel_param *kp); val 345 include/linux/moduleparam.h extern int param_set_short(const char *val, const struct kernel_param *kp); val 350 include/linux/moduleparam.h extern int param_set_ushort(const char *val, const struct kernel_param *kp); val 355 include/linux/moduleparam.h extern int param_set_int(const char *val, const struct kernel_param *kp); val 360 include/linux/moduleparam.h extern int param_set_uint(const char *val, const struct kernel_param *kp); val 365 include/linux/moduleparam.h extern int param_set_long(const char *val, const struct kernel_param *kp); val 370 include/linux/moduleparam.h extern int param_set_ulong(const char *val, const struct kernel_param *kp); val 375 include/linux/moduleparam.h extern int param_set_ullong(const char *val, const struct kernel_param *kp); val 380 include/linux/moduleparam.h extern int param_set_charp(const char *val, const struct kernel_param *kp); val 387 include/linux/moduleparam.h extern int param_set_bool(const char *val, const struct kernel_param *kp); val 392 include/linux/moduleparam.h extern int param_set_bool_enable_only(const char *val, val 398 include/linux/moduleparam.h extern int param_set_invbool(const char *val, const struct kernel_param *kp); val 404 include/linux/moduleparam.h extern int param_set_bint(const char *val, const struct kernel_param *kp); val 511 include/linux/moduleparam.h extern int param_set_copystring(const char *val, const struct kernel_param *); val 98 include/linux/moxtet.h extern int moxtet_device_write(struct device *dev, u8 val); val 298 include/linux/mtd/cfi.h unsigned long cfi_merge_status(map_word val, struct map_info *map, val 308 include/linux/mtd/cfi.h map_word val = map_read(map, addr); val 311 include/linux/mtd/cfi.h return val.x[0]; val 313 include/linux/mtd/cfi.h return cfi16_to_cpu(map, val.x[0]); val 318 include/linux/mtd/cfi.h return cfi32_to_cpu(map, val.x[0]); val 324 include/linux/mtd/cfi.h map_word val = map_read(map, addr); val 327 include/linux/mtd/cfi.h return val.x[0] & 0xff; val 329 include/linux/mtd/cfi.h return cfi16_to_cpu(map, val.x[0]); val 334 include/linux/mtd/cfi.h return cfi32_to_cpu(map, val.x[0]); val 47 include/linux/mtd/hyperbus.h unsigned long addr, u16 val); val 81 include/linux/mtd/qinfo.h map_word val = { {0} }; val 82 include/linux/mtd/qinfo.h val.x[0] = cmd; val 83 include/linux/mtd/qinfo.h return val; val 458 include/linux/mtd/spinand.h int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); val 192 include/linux/net.h int (*set_peek_off)(struct sock *sk, int val); val 204 include/linux/net.h int (*set_rcvlowat)(struct sock *sk, int val); val 549 include/linux/netdevice.h unsigned long val, new; val 552 include/linux/netdevice.h val = READ_ONCE(n->state); val 553 include/linux/netdevice.h if (val & NAPIF_STATE_DISABLE) val 556 include/linux/netdevice.h if (!(val & NAPIF_STATE_SCHED)) val 559 include/linux/netdevice.h new = val | NAPIF_STATE_MISSED; val 560 include/linux/netdevice.h } while (cmpxchg(&n->state, val, new) != val); val 721 include/linux/netdevice.h u32 val = hash & ~rps_cpu_mask; val 724 include/linux/netdevice.h val |= raw_smp_processor_id(); val 726 include/linux/netdevice.h if (table->ents[index] != val) val 727 include/linux/netdevice.h table->ents[index] = val; val 2552 include/linux/netdevice.h int call_netdevice_notifiers(unsigned long val, struct net_device *dev); val 190 include/linux/netfilter/nf_conntrack_sip.h unsigned int *matchen, unsigned int *val); val 167 include/linux/notifier.h unsigned long val, void *v); val 169 include/linux/notifier.h unsigned long val, void *v, int nr_to_call, int *nr_calls); val 171 include/linux/notifier.h unsigned long val, void *v); val 173 include/linux/notifier.h unsigned long val, void *v, int nr_to_call, int *nr_calls); val 175 include/linux/notifier.h unsigned long val, void *v); val 177 include/linux/notifier.h unsigned long val, void *v, int nr_to_call, int *nr_calls); val 179 include/linux/notifier.h unsigned long val, void *v); val 181 include/linux/notifier.h unsigned long val, void *v, int nr_to_call, int *nr_calls); val 315 include/linux/ntb.h int (*spad_write)(struct ntb_dev *ntb, int sidx, u32 val); val 321 include/linux/ntb.h u32 val); val 1339 include/linux/ntb.h static inline int ntb_spad_write(struct ntb_dev *ntb, int sidx, u32 val) val 1344 include/linux/ntb.h return ntb->ops->spad_write(ntb, sidx, val); val 1398 include/linux/ntb.h u32 val) val 1403 include/linux/ntb.h return ntb->ops->peer_spad_write(ntb, pidx, sidx, val); val 573 include/linux/nvme.h #define show_nvm_opcode_name(val) \ val 574 include/linux/nvme.h __print_symbolic(val, \ val 822 include/linux/nvme.h #define show_admin_opcode_name(val) \ val 823 include/linux/nvme.h __print_symbolic(val, \ val 64 include/linux/nvmem-consumer.h int nvmem_cell_read_u16(struct device *dev, const char *cell_id, u16 *val); val 65 include/linux/nvmem-consumer.h int nvmem_cell_read_u32(struct device *dev, const char *cell_id, u32 *val); val 127 include/linux/nvmem-consumer.h const char *cell_id, u16 *val) val 133 include/linux/nvmem-consumer.h const char *cell_id, u32 *val) val 18 include/linux/nvmem-provider.h void *val, size_t bytes); val 20 include/linux/nvmem-provider.h void *val, size_t bytes); val 70 include/linux/nvram.h static inline void nvram_write_byte(unsigned char val, int addr) val 74 include/linux/nvram.h ppc_md.nvram_write_val(addr, val); val 77 include/linux/nvram.h arch_nvram_ops.write_byte(val, addr); val 281 include/linux/omap-dma.h void (*dma_write)(u32 val, int reg, int lch); val 73 include/linux/omap-gpmc.h extern void gpmc_cs_write_reg(int cs, int idx, u32 val); val 135 include/linux/oprofile.h char const * name, ulong * val); val 139 include/linux/oprofile.h char const * name, ulong * val); val 143 include/linux/oprofile.h char const * name, atomic_t * val); val 158 include/linux/oprofile.h ssize_t oprofilefs_ulong_to_user(unsigned long val, char __user * buf, size_t count, loff_t * offset); val 164 include/linux/oprofile.h int oprofilefs_ulong_from_user(unsigned long * val, char const __user * buf, size_t count); val 192 include/linux/oprofile.h int oprofile_add_data(struct op_entry *entry, unsigned long val); val 193 include/linux/oprofile.h int oprofile_add_data64(struct op_entry *entry, u64 val); val 73 include/linux/parport.h unsigned char val); val 434 include/linux/parport.h unsigned char val); val 437 include/linux/parport.h unsigned char val, val 73 include/linux/parport_pc.h unsigned char val = inb (DATA (p)); val 76 include/linux/parport_pc.h p, val); val 78 include/linux/parport_pc.h return val; val 130 include/linux/parport_pc.h unsigned char val) val 137 include/linux/parport_pc.h mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); val 139 include/linux/parport_pc.h ctr = (ctr & ~mask) ^ val; val 186 include/linux/parport_pc.h unsigned char val) val 197 include/linux/parport_pc.h (val & 0x20) ? "reverse" : "forward"); val 198 include/linux/parport_pc.h if (val & 0x20) val 206 include/linux/parport_pc.h val &= wm; val 208 include/linux/parport_pc.h return __parport_pc_frob_control (p, mask, val); val 700 include/linux/pci.h int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); val 701 include/linux/pci.h int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); val 709 include/linux/pci.h int reg, int len, u32 *val); val 711 include/linux/pci.h int reg, int len, u32 val); val 1063 include/linux/pci.h int where, u8 *val); val 1065 include/linux/pci.h int where, u16 *val); val 1067 include/linux/pci.h int where, u32 *val); val 1069 include/linux/pci.h int where, u8 val); val 1071 include/linux/pci.h int where, u16 val); val 1073 include/linux/pci.h int where, u32 val); val 1076 include/linux/pci.h int where, int size, u32 *val); val 1078 include/linux/pci.h int where, int size, u32 val); val 1080 include/linux/pci.h int where, int size, u32 *val); val 1082 include/linux/pci.h int where, int size, u32 val); val 1086 include/linux/pci.h int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); val 1087 include/linux/pci.h int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); val 1088 include/linux/pci.h int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); val 1089 include/linux/pci.h int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); val 1090 include/linux/pci.h int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); val 1091 include/linux/pci.h int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); val 1093 include/linux/pci.h int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); val 1094 include/linux/pci.h int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); val 1095 include/linux/pci.h int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); val 1096 include/linux/pci.h int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); val 1127 include/linux/pci.h int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); val 1128 include/linux/pci.h int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); val 1129 include/linux/pci.h int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); val 1130 include/linux/pci.h int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); val 1131 include/linux/pci.h int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); val 1132 include/linux/pci.h int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); val 1657 include/linux/pci.h int where, t val) \ val 421 include/linux/percpu-defs.h #define raw_cpu_write(pcp, val) __pcpu_size_call(raw_cpu_write_, pcp, val) val 422 include/linux/percpu-defs.h #define raw_cpu_add(pcp, val) __pcpu_size_call(raw_cpu_add_, pcp, val) val 423 include/linux/percpu-defs.h #define raw_cpu_and(pcp, val) __pcpu_size_call(raw_cpu_and_, pcp, val) val 424 include/linux/percpu-defs.h #define raw_cpu_or(pcp, val) __pcpu_size_call(raw_cpu_or_, pcp, val) val 425 include/linux/percpu-defs.h #define raw_cpu_add_return(pcp, val) __pcpu_size_call_return2(raw_cpu_add_return_, pcp, val) val 432 include/linux/percpu-defs.h #define raw_cpu_sub(pcp, val) raw_cpu_add(pcp, -(val)) val 435 include/linux/percpu-defs.h #define raw_cpu_sub_return(pcp, val) raw_cpu_add_return(pcp, -(typeof(pcp))(val)) val 449 include/linux/percpu-defs.h #define __this_cpu_write(pcp, val) \ val 452 include/linux/percpu-defs.h raw_cpu_write(pcp, val); \ val 455 include/linux/percpu-defs.h #define __this_cpu_add(pcp, val) \ val 458 include/linux/percpu-defs.h raw_cpu_add(pcp, val); \ val 461 include/linux/percpu-defs.h #define __this_cpu_and(pcp, val) \ val 464 include/linux/percpu-defs.h raw_cpu_and(pcp, val); \ val 467 include/linux/percpu-defs.h #define __this_cpu_or(pcp, val) \ val 470 include/linux/percpu-defs.h raw_cpu_or(pcp, val); \ val 473 include/linux/percpu-defs.h #define __this_cpu_add_return(pcp, val) \ val 476 include/linux/percpu-defs.h raw_cpu_add_return(pcp, val); \ val 496 include/linux/percpu-defs.h #define __this_cpu_sub(pcp, val) __this_cpu_add(pcp, -(typeof(pcp))(val)) val 499 include/linux/percpu-defs.h #define __this_cpu_sub_return(pcp, val) __this_cpu_add_return(pcp, -(typeof(pcp))(val)) val 508 include/linux/percpu-defs.h #define this_cpu_write(pcp, val) __pcpu_size_call(this_cpu_write_, pcp, val) val 509 include/linux/percpu-defs.h #define this_cpu_add(pcp, val) __pcpu_size_call(this_cpu_add_, pcp, val) val 510 include/linux/percpu-defs.h #define this_cpu_and(pcp, val) __pcpu_size_call(this_cpu_and_, pcp, val) val 511 include/linux/percpu-defs.h #define this_cpu_or(pcp, val) __pcpu_size_call(this_cpu_or_, pcp, val) val 512 include/linux/percpu-defs.h #define this_cpu_add_return(pcp, val) __pcpu_size_call_return2(this_cpu_add_return_, pcp, val) val 519 include/linux/percpu-defs.h #define this_cpu_sub(pcp, val) this_cpu_add(pcp, -(typeof(pcp))(val)) val 522 include/linux/percpu-defs.h #define this_cpu_sub_return(pcp, val) this_cpu_add_return(pcp, -(typeof(pcp))(val)) val 93 include/linux/perf/arm_pmu.h void (*write_counter)(struct perf_event *event, u64 val); val 993 include/linux/perf_event.h data->data_src.val = PERF_MEM_NA; val 14 include/linux/pfn.h u64 val; val 31 include/linux/pfn_t.h pfn_t pfn_t = { .val = pfn | (flags & PFN_FLAGS_MASK), }; val 49 include/linux/pfn_t.h return (pfn.val & PFN_MAP) == PFN_MAP || (pfn.val & PFN_DEV) == 0; val 54 include/linux/pfn_t.h return pfn.val & ~PFN_FLAGS_MASK; val 105 include/linux/pfn_t.h return (pfn.val & flags) == flags; val 123 include/linux/pfn_t.h return (pfn.val & PFN_SPECIAL) == PFN_SPECIAL; val 218 include/linux/phy.h int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val); val 607 include/linux/phy.h u16 val); val 723 include/linux/phy.h static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val) val 725 include/linux/phy.h return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val); val 736 include/linux/phy.h static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val) val 739 include/linux/phy.h val); val 774 include/linux/phy.h int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); val 786 include/linux/phy.h int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); val 812 include/linux/phy.h static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) val 814 include/linux/phy.h return __phy_modify(phydev, regnum, 0, val); val 826 include/linux/phy.h u16 val) val 828 include/linux/phy.h return __phy_modify(phydev, regnum, val, 0); val 837 include/linux/phy.h static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) val 839 include/linux/phy.h return phy_modify(phydev, regnum, 0, val); val 848 include/linux/phy.h static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val) val 850 include/linux/phy.h return phy_modify(phydev, regnum, val, 0); val 864 include/linux/phy.h u32 regnum, u16 val) val 866 include/linux/phy.h return __phy_modify_mmd(phydev, devad, regnum, 0, val); val 880 include/linux/phy.h u32 regnum, u16 val) val 882 include/linux/phy.h return __phy_modify_mmd(phydev, devad, regnum, val, 0); val 894 include/linux/phy.h u32 regnum, u16 val) val 896 include/linux/phy.h return phy_modify_mmd(phydev, devad, regnum, 0, val); val 908 include/linux/phy.h u32 regnum, u16 val) val 910 include/linux/phy.h return phy_modify_mmd(phydev, devad, regnum, val, 0); val 993 include/linux/phy.h int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val); val 1110 include/linux/phy.h u16 regnum, u16 val); val 3095 include/linux/platform_data/cros_ec_commands.h float val[0]; val 3103 include/linux/platform_data/cros_ec_commands.h float val[0]; val 3687 include/linux/platform_data/cros_ec_commands.h uint8_t val; val 3699 include/linux/platform_data/cros_ec_commands.h uint8_t val; val 3718 include/linux/platform_data/cros_ec_commands.h uint8_t val; val 3721 include/linux/platform_data/cros_ec_commands.h uint8_t val; val 4428 include/linux/platform_data/cros_ec_commands.h uint8_t val; val 4450 include/linux/platform_data/cros_ec_commands.h uint8_t val; val 11 include/linux/platform_data/keypad-omap.h #define omap_writew(val, reg) do {} while (0) val 123 include/linux/platform_data/lp855x.h u8 val; val 36 include/linux/platform_data/rtc-v3020.h #define V3020_IS_COMMAND(val) ((val)>=0x0E) val 181 include/linux/platform_data/wilco-ec.h u8 *val); val 192 include/linux/platform_data/wilco-ec.h u8 val); val 118 include/linux/pm_qos.h enum pm_qos_req_action action, s32 val); val 159 include/linux/pm_qos.h int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val); val 241 include/linux/pm_qos.h static inline int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val) val 98 include/linux/pm_wakeup.h extern int device_init_wakeup(struct device *dev, bool val); val 156 include/linux/pm_wakeup.h static inline int device_init_wakeup(struct device *dev, bool val) val 158 include/linux/pm_wakeup.h device_set_wakeup_capable(dev, val); val 159 include/linux/pm_wakeup.h device_set_wakeup_enable(dev, val); val 128 include/linux/poll.h static inline __u16 mangle_poll(__poll_t val) val 130 include/linux/poll.h __u16 v = (__force __u16)val; val 138 include/linux/poll.h static inline __poll_t demangle_poll(u16 val) val 140 include/linux/poll.h #define M(X) (__force __poll_t)__MAP(val, POLL##X, (__force __u16)EPOLL##X) val 239 include/linux/power_supply.h union power_supply_propval *val); val 242 include/linux/power_supply.h const union power_supply_propval *val); val 398 include/linux/power_supply.h union power_supply_propval *val); val 401 include/linux/power_supply.h const union power_supply_propval *val); val 151 include/linux/preempt.h extern void preempt_count_add(int val); val 152 include/linux/preempt.h extern void preempt_count_sub(int val); val 156 include/linux/preempt.h #define preempt_count_add(val) __preempt_count_add(val) val 157 include/linux/preempt.h #define preempt_count_sub(val) __preempt_count_sub(val) val 23 include/linux/projid.h projid_t val; val 28 include/linux/projid.h return projid.val; val 38 include/linux/property.h u8 *val, size_t nval); val 40 include/linux/property.h u16 *val, size_t nval); val 42 include/linux/property.h u32 *val, size_t nval); val 44 include/linux/property.h u64 *val, size_t nval); val 46 include/linux/property.h const char **val, size_t nval); val 48 include/linux/property.h const char **val); val 56 include/linux/property.h const char *propname, u8 *val, val 59 include/linux/property.h const char *propname, u16 *val, val 62 include/linux/property.h const char *propname, u32 *val, val 65 include/linux/property.h const char *propname, u64 *val, val 68 include/linux/property.h const char *propname, const char **val, val 71 include/linux/property.h const char *propname, const char **val); val 125 include/linux/property.h const char *propname, u8 *val) val 127 include/linux/property.h return device_property_read_u8_array(dev, propname, val, 1); val 131 include/linux/property.h const char *propname, u16 *val) val 133 include/linux/property.h return device_property_read_u16_array(dev, propname, val, 1); val 137 include/linux/property.h const char *propname, u32 *val) val 139 include/linux/property.h return device_property_read_u32_array(dev, propname, val, 1); val 143 include/linux/property.h const char *propname, u64 *val) val 145 include/linux/property.h return device_property_read_u64_array(dev, propname, val, 1); val 175 include/linux/property.h const char *propname, u8 *val) val 177 include/linux/property.h return fwnode_property_read_u8_array(fwnode, propname, val, 1); val 181 include/linux/property.h const char *propname, u16 *val) val 183 include/linux/property.h return fwnode_property_read_u16_array(fwnode, propname, val, 1); val 187 include/linux/property.h const char *propname, u32 *val) val 189 include/linux/property.h return fwnode_property_read_u32_array(fwnode, propname, val, 1); val 193 include/linux/property.h const char *propname, u64 *val) val 195 include/linux/property.h return fwnode_property_read_u64_array(fwnode, propname, val, 1); val 247 include/linux/pstore.h pstore_ftrace_write_timestamp(struct pstore_ftrace_record *rec, u64 val) val 249 include/linux/pstore.h rec->ts = val; val 272 include/linux/pstore.h pstore_ftrace_write_timestamp(struct pstore_ftrace_record *rec, u64 val) val 274 include/linux/pstore.h rec->ts = (rec->ts & TS_CPU_MASK) | (val << TS_CPU_SHIFT); val 232 include/linux/pxa2xx_ssp.h static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) val 234 include/linux/pxa2xx_ssp.h __raw_writel(val, dev->mmio_base + reg); val 244 include/linux/qcom-geni-se.h u32 val; val 246 include/linux/qcom-geni-se.h val = readl_relaxed(se->base + GENI_FW_REVISION_RO); val 248 include/linux/qcom-geni-se.h return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT; val 350 include/linux/qcom-geni-se.h u32 val; val 352 include/linux/qcom-geni-se.h val = readl_relaxed(se->base + SE_HW_PARAM_0); val 354 include/linux/qcom-geni-se.h return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT; val 368 include/linux/qcom-geni-se.h u32 val; val 370 include/linux/qcom-geni-se.h val = readl_relaxed(se->base + SE_HW_PARAM_0); val 372 include/linux/qcom-geni-se.h return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT; val 386 include/linux/qcom-geni-se.h u32 val; val 388 include/linux/qcom-geni-se.h val = readl_relaxed(se->base + SE_HW_PARAM_1); val 390 include/linux/qcom-geni-se.h return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT; val 19 include/linux/qcom_scm.h u32 val; val 61 include/linux/qcom_scm.h extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); val 62 include/linux/qcom_scm.h extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); val 100 include/linux/qcom_scm.h static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; } val 101 include/linux/qcom_scm.h static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; } val 46 include/linux/qed/common_hsi.h #define DMA_REGPAIR_LE(x, val) do { \ val 47 include/linux/qed/common_hsi.h (x).hi = DMA_HI_LE((val)); \ val 48 include/linux/qed/common_hsi.h (x).lo = DMA_LO_LE((val)); \ val 461 include/linux/qed/qed_if.h #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ val 466 include/linux/qed/qed_if.h #define DIRECT_REG_WR64(reg_addr, val) writeq((u32)val, \ val 1162 include/linux/qed/qed_if.h int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val); val 52 include/linux/qed/qed_iov_if.h int (*set_spoof) (struct qed_dev *cdev, int vfid, bool val); val 81 include/linux/random.h unsigned long val = get_random_long(); val 83 include/linux/random.h return val & CANARY_MASK; val 24 include/linux/range.h static inline resource_size_t cap_resource(u64 val) val 26 include/linux/range.h if (val > MAX_RESOURCE) val 29 include/linux/range.h return val; val 74 include/linux/regmap.h #define regmap_update_bits(map, reg, mask, val) \ val 75 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, false, false) val 76 include/linux/regmap.h #define regmap_update_bits_async(map, reg, mask, val)\ val 77 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, true, false) val 78 include/linux/regmap.h #define regmap_update_bits_check(map, reg, mask, val, change)\ val 79 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, change, false, false) val 80 include/linux/regmap.h #define regmap_update_bits_check_async(map, reg, mask, val, change)\ val 81 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, change, true, false) val 83 include/linux/regmap.h #define regmap_write_bits(map, reg, mask, val) \ val 84 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, false, true) val 86 include/linux/regmap.h #define regmap_field_write(field, val) \ val 87 include/linux/regmap.h regmap_field_update_bits_base(field, ~0, val, NULL, false, false) val 88 include/linux/regmap.h #define regmap_field_force_write(field, val) \ val 89 include/linux/regmap.h regmap_field_update_bits_base(field, ~0, val, NULL, false, true) val 90 include/linux/regmap.h #define regmap_field_update_bits(field, mask, val)\ val 91 include/linux/regmap.h regmap_field_update_bits_base(field, mask, val, NULL, false, false) val 92 include/linux/regmap.h #define regmap_field_force_update_bits(field, mask, val) \ val 93 include/linux/regmap.h regmap_field_update_bits_base(field, mask, val, NULL, false, true) val 95 include/linux/regmap.h #define regmap_fields_write(field, id, val) \ val 96 include/linux/regmap.h regmap_fields_update_bits_base(field, id, ~0, val, NULL, false, false) val 97 include/linux/regmap.h #define regmap_fields_force_write(field, id, val) \ val 98 include/linux/regmap.h regmap_fields_update_bits_base(field, id, ~0, val, NULL, false, true) val 99 include/linux/regmap.h #define regmap_fields_update_bits(field, id, mask, val)\ val 100 include/linux/regmap.h regmap_fields_update_bits_base(field, id, mask, val, NULL, false, false) val 101 include/linux/regmap.h #define regmap_fields_force_update_bits(field, id, mask, val) \ val 102 include/linux/regmap.h regmap_fields_update_bits_base(field, id, mask, val, NULL, false, true) val 123 include/linux/regmap.h #define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_us) \ val 131 include/linux/regmap.h __ret = regmap_read((map), (addr), &(val)); \ val 138 include/linux/regmap.h __ret = regmap_read((map), (addr), &(val)); \ val 165 include/linux/regmap.h #define regmap_field_read_poll_timeout(field, val, cond, sleep_us, timeout_us) \ val 173 include/linux/regmap.h pollret = regmap_field_read((field), &(val)); \ val 179 include/linux/regmap.h pollret = regmap_field_read((field), &(val)); \ val 372 include/linux/regmap.h int (*reg_read)(void *context, unsigned int reg, unsigned int *val); val 373 include/linux/regmap.h int (*reg_write)(void *context, unsigned int reg, unsigned int val); val 452 include/linux/regmap.h const void *val, size_t val_len); val 455 include/linux/regmap.h const void *val, size_t val_len, val 461 include/linux/regmap.h unsigned int *val); val 463 include/linux/regmap.h unsigned int val); val 465 include/linux/regmap.h unsigned int mask, unsigned int val); val 1009 include/linux/regmap.h int regmap_write(struct regmap *map, unsigned int reg, unsigned int val); val 1010 include/linux/regmap.h int regmap_write_async(struct regmap *map, unsigned int reg, unsigned int val); val 1012 include/linux/regmap.h const void *val, size_t val_len); val 1014 include/linux/regmap.h const void *val, size_t val_len); val 1015 include/linux/regmap.h int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val, val 1023 include/linux/regmap.h const void *val, size_t val_len); val 1024 include/linux/regmap.h int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val); val 1026 include/linux/regmap.h void *val, size_t val_len); val 1028 include/linux/regmap.h void *val, size_t val_len); val 1029 include/linux/regmap.h int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val, val 1032 include/linux/regmap.h unsigned int mask, unsigned int val, val 1057 include/linux/regmap.h unsigned int *val); val 1100 include/linux/regmap.h int regmap_field_read(struct regmap_field *field, unsigned int *val); val 1102 include/linux/regmap.h unsigned int mask, unsigned int val, val 1105 include/linux/regmap.h unsigned int *val); val 1107 include/linux/regmap.h unsigned int mask, unsigned int val, val 1291 include/linux/regmap.h unsigned int val) val 1298 include/linux/regmap.h unsigned int val) val 1305 include/linux/regmap.h const void *val, size_t val_len) val 1312 include/linux/regmap.h const void *val, size_t val_len) val 1319 include/linux/regmap.h const void *val, size_t val_len) val 1326 include/linux/regmap.h const void *val, size_t val_count) val 1333 include/linux/regmap.h unsigned int *val) val 1340 include/linux/regmap.h void *val, size_t val_len) val 1347 include/linux/regmap.h void *val, size_t val_len) val 1354 include/linux/regmap.h void *val, size_t val_count) val 1361 include/linux/regmap.h unsigned int mask, unsigned int val, val 1369 include/linux/regmap.h unsigned int mask, unsigned int val, val 1378 include/linux/regmap.h unsigned int mask, unsigned int val, val 1452 include/linux/regmap.h unsigned int *val) val 67 include/linux/reset/bcm63xx_pmb.h u32 off, u32 *val) val 72 include/linux/reset/bcm63xx_pmb.h *val = readl(master + PMB_RD_DATA); val 78 include/linux/reset/bcm63xx_pmb.h u32 off, u32 val) val 82 include/linux/reset/bcm63xx_pmb.h writel(val, master + PMB_WR_DATA); val 31 include/linux/restart_block.h u32 val; val 111 include/linux/ring_buffer.h void ring_buffer_change_overwrite(struct ring_buffer *buffer, int val); val 50 include/linux/rtc/m48t59.h void (*write_byte)(struct device *dev, u32 ofs, u8 val); val 17 include/linux/rtc/sirfsoc_rtciobrg.h extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr); val 17 include/linux/rtsx_common.h #define RTSX_REG_PAIR(addr, val) (((u32)(addr) << 16) | (u8)(val)) val 102 include/linux/rtsx_pci.h #define rtsx_pci_read_config_byte(pcr, where, val) \ val 103 include/linux/rtsx_pci.h pci_read_config_byte((pcr)->pci, where, val) val 105 include/linux/rtsx_pci.h #define rtsx_pci_write_config_byte(pcr, where, val) \ val 106 include/linux/rtsx_pci.h pci_write_config_byte((pcr)->pci, where, val) val 108 include/linux/rtsx_pci.h #define rtsx_pci_read_config_dword(pcr, where, val) \ val 109 include/linux/rtsx_pci.h pci_read_config_dword((pcr)->pci, where, val) val 111 include/linux/rtsx_pci.h #define rtsx_pci_write_config_dword(pcr, where, val) \ val 112 include/linux/rtsx_pci.h pci_write_config_dword((pcr)->pci, where, val) val 1064 include/linux/rtsx_pci.h int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val); val 1065 include/linux/rtsx_pci.h int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val); val 1084 include/linux/rtsx_pci.h int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val); val 1092 include/linux/rtsx_pci.h int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val); val 1274 include/linux/rtsx_pci.h #define SDR104_PHASE(val) ((val) & 0xFF) val 1275 include/linux/rtsx_pci.h #define SDR50_PHASE(val) (((val) >> 8) & 0xFF) val 1276 include/linux/rtsx_pci.h #define DDR50_PHASE(val) (((val) >> 16) & 0xFF) val 1289 include/linux/rtsx_pci.h int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val); val 1290 include/linux/rtsx_pci.h int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val); val 1326 include/linux/rtsx_pci.h u8 val; val 1328 include/linux/rtsx_pci.h err = pci_read_config_byte(pcr->pci, addr, &val); val 1331 include/linux/rtsx_pci.h return pci_write_config_byte(pcr->pci, addr, (val & mask) | append); val 1334 include/linux/rtsx_pci.h static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) val 1336 include/linux/rtsx_pci.h rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); val 1337 include/linux/rtsx_pci.h rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16); val 1338 include/linux/rtsx_pci.h rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8); val 1339 include/linux/rtsx_pci.h rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); val 1346 include/linux/rtsx_pci.h u16 val; val 1348 include/linux/rtsx_pci.h err = rtsx_pci_read_phy_register(pcr, addr, &val); val 1352 include/linux/rtsx_pci.h return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append); val 21 include/linux/scc.h #define Outb(port, val) outb_p(val, port) val 24 include/linux/scc.h #define Outb(port, val) outb(val, port) val 304 include/linux/security.h int security_add_mnt_opt(const char *option, const char *val, val 670 include/linux/security.h static inline int security_add_mnt_opt(const char *option, const char *val, val 46 include/linux/selection.h extern void vcs_scr_writew(struct vc_data *vc, u16 val, u16 *org); val 31 include/linux/semaphore.h static inline void sema_init(struct semaphore *sem, int val) val 34 include/linux/semaphore.h *sem = (struct semaphore) __SEMAPHORE_INITIALIZER(*sem, val); val 1432 include/linux/skbuff.h static inline void skb_zcopy_set_nouarg(struct sk_buff *skb, void *val) val 1434 include/linux/skbuff.h skb_shinfo(skb)->destructor_arg = (void *)((uintptr_t) val | 0x1UL); val 2218 include/linux/skbuff.h static inline void __skb_put_u8(struct sk_buff *skb, u8 val) val 2220 include/linux/skbuff.h *(u8 *)__skb_put(skb, 1) = val; val 2242 include/linux/skbuff.h static inline void skb_put_u8(struct sk_buff *skb, u8 val) val 2244 include/linux/skbuff.h *(u8 *)skb_put(skb, 1) = val; val 4301 include/linux/skbuff.h static inline void skb_set_dst_pending_confirm(struct sk_buff *skb, u32 val) val 4303 include/linux/skbuff.h skb->dst_pending_confirm = val; val 198 include/linux/slimbus.h int slim_read(struct slim_device *sdev, u32 addr, size_t count, u8 *val); val 199 include/linux/slimbus.h int slim_write(struct slim_device *sdev, u32 addr, size_t count, u8 *val); val 166 include/linux/sm501.h #define smc501_writel(val, addr) iowrite32be((val), (addr)) val 169 include/linux/sm501.h #define smc501_writel(val, addr) writel(val, addr) val 57 include/linux/soc/ixp4xx/qmgr.h void qmgr_put_entry(unsigned int queue, u32 val); val 880 include/linux/soundwire/sdw.h int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); val 881 include/linux/soundwire/sdw.h int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); val 56 include/linux/spi/ads7846.h int (*filter) (void *filter_data, int data_idx, int *val); val 18 include/linux/spi/max7301.h int (*write)(struct device *dev, unsigned int reg, unsigned int val); val 25 include/linux/spi/spi-mem.h .val = __val, \ val 100 include/linux/spi/spi-mem.h u64 val; val 606 include/linux/ssb/ssb_driver_chipcommon.h #define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val) val 16 include/linux/ssbi.h ssbi_reg_read(void *context, unsigned int reg, unsigned int *val) val 23 include/linux/ssbi.h *val = v; val 29 include/linux/ssbi.h ssbi_reg_write(void *context, unsigned int reg, unsigned int val) val 31 include/linux/ssbi.h u8 v = val; val 58 include/linux/sungem_phy.h void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val); val 121 include/linux/sunrpc/rpc_rdma.h rpcrdma_decode_buffer_size(u8 val) val 123 include/linux/sunrpc/rpc_rdma.h return ((unsigned int)val + 1) << 10; val 186 include/linux/sunrpc/svc.h __be32 val, *vp; val 188 include/linux/sunrpc/svc.h val = *vp++; val 191 include/linux/sunrpc/svc.h return ntohl(val); val 194 include/linux/sunrpc/svc.h static inline void svc_putnl(struct kvec *iov, u32 val) val 197 include/linux/sunrpc/svc.h *vp = htonl(val); val 203 include/linux/sunrpc/svc.h __be32 val, *vp; val 205 include/linux/sunrpc/svc.h val = *vp++; val 208 include/linux/sunrpc/svc.h return val; val 218 include/linux/sunrpc/svc.h static inline void svc_putu32(struct kvec *iov, __be32 val) val 221 include/linux/sunrpc/svc.h *vp = val; val 147 include/linux/sunrpc/xdr.h xdr_encode_hyper(__be32 *p, __u64 val) val 149 include/linux/sunrpc/xdr.h put_unaligned_be64(val, p); val 500 include/linux/swap.h #define si_swapinfo(val) \ val 501 include/linux/swap.h do { (val)->freeswap = (val)->totalswap = 0; } while (0) val 613 include/linux/swap.h entry.val = 0; val 33 include/linux/swapops.h ret.val = (type << SWP_TYPE_SHIFT) | (offset & SWP_OFFSET_MASK); val 43 include/linux/swapops.h return (entry.val >> SWP_TYPE_SHIFT); val 52 include/linux/swapops.h return entry.val & SWP_OFFSET_MASK; val 91 include/linux/swapops.h entry.val = xa_to_value(arg); val 97 include/linux/swapops.h return xa_mk_value(entry.val); val 575 include/linux/syscalls.h asmlinkage long sys_futex(u32 __user *uaddr, int op, u32 val, val 578 include/linux/syscalls.h asmlinkage long sys_futex_time32(u32 __user *uaddr, int op, u32 val, val 61 include/linux/tcp.h __le64 val[DIV_ROUND_UP(TCP_FASTOPEN_COOKIE_MAX, sizeof(u64))]; val 23 include/linux/trace_events.h const char *trace_print_symbols_seq(struct trace_seq *p, unsigned long val, val 32 include/linux/trace_events.h unsigned long long val, val 15 include/linux/ts-nbus.h extern int ts_nbus_read(struct ts_nbus *ts_nbus, u8 adr, u16 *val); val 16 include/linux/ts-nbus.h extern int ts_nbus_write(struct ts_nbus *ts_nbus, u8 adr, u16 val); val 378 include/linux/tty.h static inline void __tty_set_flow_change(struct tty_struct *tty, int val) val 380 include/linux/tty.h tty->flow_change = val; val 383 include/linux/tty.h static inline void tty_set_flow_change(struct tty_struct *tty, int val) val 385 include/linux/tty.h tty->flow_change = val; val 613 include/linux/tty.h static inline void tty_port_set_cts_flow(struct tty_port *port, bool val) val 615 include/linux/tty.h if (val) val 626 include/linux/tty.h static inline void tty_port_set_active(struct tty_port *port, bool val) val 628 include/linux/tty.h if (val) val 639 include/linux/tty.h static inline void tty_port_set_check_carrier(struct tty_port *port, bool val) val 641 include/linux/tty.h if (val) val 652 include/linux/tty.h static inline void tty_port_set_suspended(struct tty_port *port, bool val) val 654 include/linux/tty.h if (val) val 665 include/linux/tty.h static inline void tty_port_set_initialized(struct tty_port *port, bool val) val 667 include/linux/tty.h if (val) val 678 include/linux/tty.h static inline void tty_port_set_kopened(struct tty_port *port, bool val) val 680 include/linux/tty.h if (val) val 117 include/linux/ucb1400.h static inline void ucb1400_reg_write(struct snd_ac97 *ac97, u16 reg, u16 val) val 119 include/linux/ucb1400.h ac97->bus->ops->write(ac97, reg, val); val 128 include/linux/ucb1400.h u16 val) val 130 include/linux/ucb1400.h ucb1400_reg_write(ac97, UCB_IO_DATA, val ? val 101 include/linux/udp.h static inline void udp_set_no_check6_tx(struct sock *sk, bool val) val 103 include/linux/udp.h udp_sk(sk)->no_check6_tx = val; val 106 include/linux/udp.h static inline void udp_set_no_check6_rx(struct sock *sk, bool val) val 108 include/linux/udp.h udp_sk(sk)->no_check6_rx = val; val 22 include/linux/uidgid.h uid_t val; val 27 include/linux/uidgid.h gid_t val; val 36 include/linux/uidgid.h return uid.val; val 41 include/linux/uidgid.h return gid.val; val 63 include/linux/ulpi/driver.h int ulpi_write(struct ulpi *ulpi, u8 addr, u8 val); val 17 include/linux/ulpi/interface.h int (*write)(struct device *dev, u8 addr, u8 val); val 38 include/linux/unaligned/access_ok.h static __always_inline void put_unaligned_le16(u16 val, void *p) val 40 include/linux/unaligned/access_ok.h *((__le16 *)p) = cpu_to_le16(val); val 43 include/linux/unaligned/access_ok.h static __always_inline void put_unaligned_le32(u32 val, void *p) val 45 include/linux/unaligned/access_ok.h *((__le32 *)p) = cpu_to_le32(val); val 48 include/linux/unaligned/access_ok.h static __always_inline void put_unaligned_le64(u64 val, void *p) val 50 include/linux/unaligned/access_ok.h *((__le64 *)p) = cpu_to_le64(val); val 53 include/linux/unaligned/access_ok.h static __always_inline void put_unaligned_be16(u16 val, void *p) val 55 include/linux/unaligned/access_ok.h *((__be16 *)p) = cpu_to_be16(val); val 58 include/linux/unaligned/access_ok.h static __always_inline void put_unaligned_be32(u32 val, void *p) val 60 include/linux/unaligned/access_ok.h *((__be32 *)p) = cpu_to_be32(val); val 63 include/linux/unaligned/access_ok.h static __always_inline void put_unaligned_be64(u64 val, void *p) val 65 include/linux/unaligned/access_ok.h *((__be64 *)p) = cpu_to_be64(val); val 23 include/linux/unaligned/be_byteshift.h static inline void __put_unaligned_be16(u16 val, u8 *p) val 25 include/linux/unaligned/be_byteshift.h *p++ = val >> 8; val 26 include/linux/unaligned/be_byteshift.h *p++ = val; val 29 include/linux/unaligned/be_byteshift.h static inline void __put_unaligned_be32(u32 val, u8 *p) val 31 include/linux/unaligned/be_byteshift.h __put_unaligned_be16(val >> 16, p); val 32 include/linux/unaligned/be_byteshift.h __put_unaligned_be16(val, p + 2); val 35 include/linux/unaligned/be_byteshift.h static inline void __put_unaligned_be64(u64 val, u8 *p) val 37 include/linux/unaligned/be_byteshift.h __put_unaligned_be32(val >> 32, p); val 38 include/linux/unaligned/be_byteshift.h __put_unaligned_be32(val, p + 4); val 56 include/linux/unaligned/be_byteshift.h static inline void put_unaligned_be16(u16 val, void *p) val 58 include/linux/unaligned/be_byteshift.h __put_unaligned_be16(val, p); val 61 include/linux/unaligned/be_byteshift.h static inline void put_unaligned_be32(u32 val, void *p) val 63 include/linux/unaligned/be_byteshift.h __put_unaligned_be32(val, p); val 66 include/linux/unaligned/be_byteshift.h static inline void put_unaligned_be64(u64 val, void *p) val 68 include/linux/unaligned/be_byteshift.h __put_unaligned_be64(val, p); val 22 include/linux/unaligned/be_memmove.h static inline void put_unaligned_be16(u16 val, void *p) val 24 include/linux/unaligned/be_memmove.h __put_unaligned_memmove16(val, p); val 27 include/linux/unaligned/be_memmove.h static inline void put_unaligned_be32(u32 val, void *p) val 29 include/linux/unaligned/be_memmove.h __put_unaligned_memmove32(val, p); val 32 include/linux/unaligned/be_memmove.h static inline void put_unaligned_be64(u64 val, void *p) val 34 include/linux/unaligned/be_memmove.h __put_unaligned_memmove64(val, p); val 22 include/linux/unaligned/be_struct.h static inline void put_unaligned_be16(u16 val, void *p) val 24 include/linux/unaligned/be_struct.h __put_unaligned_cpu16(val, p); val 27 include/linux/unaligned/be_struct.h static inline void put_unaligned_be32(u32 val, void *p) val 29 include/linux/unaligned/be_struct.h __put_unaligned_cpu32(val, p); val 32 include/linux/unaligned/be_struct.h static inline void put_unaligned_be64(u64 val, void *p) val 34 include/linux/unaligned/be_struct.h __put_unaligned_cpu64(val, p); val 27 include/linux/unaligned/generic.h #define __put_unaligned_le(val, ptr) ({ \ val 31 include/linux/unaligned/generic.h *(u8 *)__gu_p = (__force u8)(val); \ val 34 include/linux/unaligned/generic.h put_unaligned_le16((__force u16)(val), __gu_p); \ val 37 include/linux/unaligned/generic.h put_unaligned_le32((__force u32)(val), __gu_p); \ val 40 include/linux/unaligned/generic.h put_unaligned_le64((__force u64)(val), __gu_p); \ val 48 include/linux/unaligned/generic.h #define __put_unaligned_be(val, ptr) ({ \ val 52 include/linux/unaligned/generic.h *(u8 *)__gu_p = (__force u8)(val); \ val 55 include/linux/unaligned/generic.h put_unaligned_be16((__force u16)(val), __gu_p); \ val 58 include/linux/unaligned/generic.h put_unaligned_be32((__force u32)(val), __gu_p); \ val 61 include/linux/unaligned/generic.h put_unaligned_be64((__force u64)(val), __gu_p); \ val 23 include/linux/unaligned/le_byteshift.h static inline void __put_unaligned_le16(u16 val, u8 *p) val 25 include/linux/unaligned/le_byteshift.h *p++ = val; val 26 include/linux/unaligned/le_byteshift.h *p++ = val >> 8; val 29 include/linux/unaligned/le_byteshift.h static inline void __put_unaligned_le32(u32 val, u8 *p) val 31 include/linux/unaligned/le_byteshift.h __put_unaligned_le16(val >> 16, p + 2); val 32 include/linux/unaligned/le_byteshift.h __put_unaligned_le16(val, p); val 35 include/linux/unaligned/le_byteshift.h static inline void __put_unaligned_le64(u64 val, u8 *p) val 37 include/linux/unaligned/le_byteshift.h __put_unaligned_le32(val >> 32, p + 4); val 38 include/linux/unaligned/le_byteshift.h __put_unaligned_le32(val, p); val 56 include/linux/unaligned/le_byteshift.h static inline void put_unaligned_le16(u16 val, void *p) val 58 include/linux/unaligned/le_byteshift.h __put_unaligned_le16(val, p); val 61 include/linux/unaligned/le_byteshift.h static inline void put_unaligned_le32(u32 val, void *p) val 63 include/linux/unaligned/le_byteshift.h __put_unaligned_le32(val, p); val 66 include/linux/unaligned/le_byteshift.h static inline void put_unaligned_le64(u64 val, void *p) val 68 include/linux/unaligned/le_byteshift.h __put_unaligned_le64(val, p); val 22 include/linux/unaligned/le_memmove.h static inline void put_unaligned_le16(u16 val, void *p) val 24 include/linux/unaligned/le_memmove.h __put_unaligned_memmove16(val, p); val 27 include/linux/unaligned/le_memmove.h static inline void put_unaligned_le32(u32 val, void *p) val 29 include/linux/unaligned/le_memmove.h __put_unaligned_memmove32(val, p); val 32 include/linux/unaligned/le_memmove.h static inline void put_unaligned_le64(u64 val, void *p) val 34 include/linux/unaligned/le_memmove.h __put_unaligned_memmove64(val, p); val 22 include/linux/unaligned/le_struct.h static inline void put_unaligned_le16(u16 val, void *p) val 24 include/linux/unaligned/le_struct.h __put_unaligned_cpu16(val, p); val 27 include/linux/unaligned/le_struct.h static inline void put_unaligned_le32(u32 val, void *p) val 29 include/linux/unaligned/le_struct.h __put_unaligned_cpu32(val, p); val 32 include/linux/unaligned/le_struct.h static inline void put_unaligned_le64(u64 val, void *p) val 34 include/linux/unaligned/le_struct.h __put_unaligned_cpu64(val, p); val 31 include/linux/unaligned/memmove.h static inline void __put_unaligned_memmove16(u16 val, void *p) val 33 include/linux/unaligned/memmove.h memmove(p, &val, 2); val 36 include/linux/unaligned/memmove.h static inline void __put_unaligned_memmove32(u32 val, void *p) val 38 include/linux/unaligned/memmove.h memmove(p, &val, 4); val 41 include/linux/unaligned/memmove.h static inline void __put_unaligned_memmove64(u64 val, void *p) val 43 include/linux/unaligned/memmove.h memmove(p, &val, 8); val 28 include/linux/unaligned/packed_struct.h static inline void __put_unaligned_cpu16(u16 val, void *p) val 31 include/linux/unaligned/packed_struct.h ptr->x = val; val 34 include/linux/unaligned/packed_struct.h static inline void __put_unaligned_cpu32(u32 val, void *p) val 37 include/linux/unaligned/packed_struct.h ptr->x = val; val 40 include/linux/unaligned/packed_struct.h static inline void __put_unaligned_cpu64(u64 val, void *p) val 43 include/linux/unaligned/packed_struct.h ptr->x = val; val 134 include/linux/uprobes.h extern int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data); val 603 include/linux/usb/composite.h int val); val 74 include/linux/usb/phy.h int (*write)(struct usb_phy *x, u32 val, u32 reg); val 174 include/linux/usb/phy.h static inline int usb_phy_io_write(struct usb_phy *x, u32 val, u32 reg) val 177 include/linux/usb/phy.h return x->io_ops->write(x, val, reg); val 16 include/linux/virtio_byteorder.h static inline u16 __virtio16_to_cpu(bool little_endian, __virtio16 val) val 19 include/linux/virtio_byteorder.h return le16_to_cpu((__force __le16)val); val 21 include/linux/virtio_byteorder.h return be16_to_cpu((__force __be16)val); val 24 include/linux/virtio_byteorder.h static inline __virtio16 __cpu_to_virtio16(bool little_endian, u16 val) val 27 include/linux/virtio_byteorder.h return (__force __virtio16)cpu_to_le16(val); val 29 include/linux/virtio_byteorder.h return (__force __virtio16)cpu_to_be16(val); val 32 include/linux/virtio_byteorder.h static inline u32 __virtio32_to_cpu(bool little_endian, __virtio32 val) val 35 include/linux/virtio_byteorder.h return le32_to_cpu((__force __le32)val); val 37 include/linux/virtio_byteorder.h return be32_to_cpu((__force __be32)val); val 40 include/linux/virtio_byteorder.h static inline __virtio32 __cpu_to_virtio32(bool little_endian, u32 val) val 43 include/linux/virtio_byteorder.h return (__force __virtio32)cpu_to_le32(val); val 45 include/linux/virtio_byteorder.h return (__force __virtio32)cpu_to_be32(val); val 48 include/linux/virtio_byteorder.h static inline u64 __virtio64_to_cpu(bool little_endian, __virtio64 val) val 51 include/linux/virtio_byteorder.h return le64_to_cpu((__force __le64)val); val 53 include/linux/virtio_byteorder.h return be64_to_cpu((__force __be64)val); val 56 include/linux/virtio_byteorder.h static inline __virtio64 __cpu_to_virtio64(bool little_endian, u64 val) val 59 include/linux/virtio_byteorder.h return (__force __virtio64)cpu_to_le64(val); val 61 include/linux/virtio_byteorder.h return (__force __virtio64)cpu_to_be64(val); val 260 include/linux/virtio_config.h static inline u16 virtio16_to_cpu(struct virtio_device *vdev, __virtio16 val) val 262 include/linux/virtio_config.h return __virtio16_to_cpu(virtio_is_little_endian(vdev), val); val 265 include/linux/virtio_config.h static inline __virtio16 cpu_to_virtio16(struct virtio_device *vdev, u16 val) val 267 include/linux/virtio_config.h return __cpu_to_virtio16(virtio_is_little_endian(vdev), val); val 270 include/linux/virtio_config.h static inline u32 virtio32_to_cpu(struct virtio_device *vdev, __virtio32 val) val 272 include/linux/virtio_config.h return __virtio32_to_cpu(virtio_is_little_endian(vdev), val); val 275 include/linux/virtio_config.h static inline __virtio32 cpu_to_virtio32(struct virtio_device *vdev, u32 val) val 277 include/linux/virtio_config.h return __cpu_to_virtio32(virtio_is_little_endian(vdev), val); val 280 include/linux/virtio_config.h static inline u64 virtio64_to_cpu(struct virtio_device *vdev, __virtio64 val) val 282 include/linux/virtio_config.h return __virtio64_to_cpu(virtio_is_little_endian(vdev), val); val 285 include/linux/virtio_config.h static inline __virtio64 cpu_to_virtio64(struct virtio_device *vdev, u64 val) val 287 include/linux/virtio_config.h return __cpu_to_virtio64(virtio_is_little_endian(vdev), val); val 393 include/linux/virtio_config.h unsigned int offset, u8 val) val 396 include/linux/virtio_config.h vdev->config->set(vdev, offset, &val, sizeof(val)); val 410 include/linux/virtio_config.h unsigned int offset, u16 val) val 413 include/linux/virtio_config.h val = (__force u16)cpu_to_virtio16(vdev, val); val 414 include/linux/virtio_config.h vdev->config->set(vdev, offset, &val, sizeof(val)); val 428 include/linux/virtio_config.h unsigned int offset, u32 val) val 431 include/linux/virtio_config.h val = (__force u32)cpu_to_virtio32(vdev, val); val 432 include/linux/virtio_config.h vdev->config->set(vdev, offset, &val, sizeof(val)); val 444 include/linux/virtio_config.h unsigned int offset, u64 val) val 447 include/linux/virtio_config.h val = (__force u64)cpu_to_virtio64(vdev, val); val 448 include/linux/virtio_config.h vdev->config->set(vdev, offset, &val, sizeof(val)); val 98 include/linux/virtio_vsock.h void virtio_transport_set_buffer_size(struct vsock_sock *vsk, u64 val); val 99 include/linux/virtio_vsock.h void virtio_transport_set_min_buffer_size(struct vsock_sock *vsk, u64 val); val 100 include/linux/virtio_vsock.h void virtio_transport_set_max_buffer_size(struct vsock_sock *vs, u64 val); val 222 include/linux/vringh.h static inline u16 vringh16_to_cpu(const struct vringh *vrh, __virtio16 val) val 224 include/linux/vringh.h return __virtio16_to_cpu(vringh_is_little_endian(vrh), val); val 227 include/linux/vringh.h static inline __virtio16 cpu_to_vringh16(const struct vringh *vrh, u16 val) val 229 include/linux/vringh.h return __cpu_to_virtio16(vringh_is_little_endian(vrh), val); val 232 include/linux/vringh.h static inline u32 vringh32_to_cpu(const struct vringh *vrh, __virtio32 val) val 234 include/linux/vringh.h return __virtio32_to_cpu(vringh_is_little_endian(vrh), val); val 237 include/linux/vringh.h static inline __virtio32 cpu_to_vringh32(const struct vringh *vrh, u32 val) val 239 include/linux/vringh.h return __cpu_to_virtio32(vringh_is_little_endian(vrh), val); val 242 include/linux/vringh.h static inline u64 vringh64_to_cpu(const struct vringh *vrh, __virtio64 val) val 244 include/linux/vringh.h return __virtio64_to_cpu(vringh_is_little_endian(vrh), val); val 247 include/linux/vringh.h static inline __virtio64 cpu_to_vringh64(const struct vringh *vrh, u64 val) val 249 include/linux/vringh.h return __cpu_to_virtio64(vringh_is_little_endian(vrh), val); val 24 include/linux/vt_buffer.h #define scr_writew(val, addr) (*(addr) = (val)) val 29 include/linux/win_minmax.h struct minmax_sample val = { .t = t, .v = meas }; val 31 include/linux/win_minmax.h m->s[2] = m->s[1] = m->s[0] = val; val 329 include/linux/wm97xx.h void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val); val 74 include/math-emu/double.h #define FP_UNPACK_RAW_D(X,val) _FP_UNPACK_RAW_2(D,X,val) val 75 include/math-emu/double.h #define FP_UNPACK_RAW_DP(X,val) _FP_UNPACK_RAW_2_P(D,X,val) val 76 include/math-emu/double.h #define FP_PACK_RAW_D(val,X) _FP_PACK_RAW_2(D,val,X) val 77 include/math-emu/double.h #define FP_PACK_RAW_DP(val,X) \ val 80 include/math-emu/double.h _FP_PACK_RAW_2_P(D,val,X); \ val 83 include/math-emu/double.h #define FP_UNPACK_D(X,val) \ val 85 include/math-emu/double.h _FP_UNPACK_RAW_2(D,X,val); \ val 89 include/math-emu/double.h #define FP_UNPACK_DP(X,val) \ val 91 include/math-emu/double.h _FP_UNPACK_RAW_2_P(D,X,val); \ val 95 include/math-emu/double.h #define FP_PACK_D(val,X) \ val 98 include/math-emu/double.h _FP_PACK_RAW_2(D,val,X); \ val 101 include/math-emu/double.h #define FP_PACK_DP(val,X) \ val 105 include/math-emu/double.h _FP_PACK_RAW_2_P(D,val,X); \ val 146 include/math-emu/double.h #define FP_UNPACK_RAW_D(X,val) _FP_UNPACK_RAW_1(D,X,val) val 147 include/math-emu/double.h #define FP_UNPACK_RAW_DP(X,val) _FP_UNPACK_RAW_1_P(D,X,val) val 148 include/math-emu/double.h #define FP_PACK_RAW_D(val,X) _FP_PACK_RAW_1(D,val,X) val 149 include/math-emu/double.h #define FP_PACK_RAW_DP(val,X) \ val 152 include/math-emu/double.h _FP_PACK_RAW_1_P(D,val,X); \ val 155 include/math-emu/double.h #define FP_UNPACK_D(X,val) \ val 157 include/math-emu/double.h _FP_UNPACK_RAW_1(D,X,val); \ val 161 include/math-emu/double.h #define FP_UNPACK_DP(X,val) \ val 163 include/math-emu/double.h _FP_UNPACK_RAW_1_P(D,X,val); \ val 167 include/math-emu/double.h #define FP_PACK_D(val,X) \ val 170 include/math-emu/double.h _FP_PACK_RAW_1(D,val,X); \ val 173 include/math-emu/double.h #define FP_PACK_DP(val,X) \ val 177 include/math-emu/double.h _FP_PACK_RAW_1_P(D,val,X); \ val 75 include/math-emu/op-1.h #define _FP_UNPACK_RAW_1(fs, X, val) \ val 77 include/math-emu/op-1.h union _FP_UNION_##fs _flo; _flo.flt = (val); \ val 84 include/math-emu/op-1.h #define _FP_UNPACK_RAW_1_P(fs, X, val) \ val 87 include/math-emu/op-1.h (union _FP_UNION_##fs *)(val); \ val 98 include/math-emu/op-1.h #define _FP_PACK_RAW_1(fs, val, X) \ val 106 include/math-emu/op-1.h (val) = _flo.flt; \ val 109 include/math-emu/op-1.h #define _FP_PACK_RAW_1_P(fs, val, X) \ val 112 include/math-emu/op-1.h (union _FP_UNION_##fs *)(val); \ val 180 include/math-emu/op-2.h #define _FP_UNPACK_RAW_2(fs, X, val) \ val 182 include/math-emu/op-2.h union _FP_UNION_##fs _flo; _flo.flt = (val); \ val 190 include/math-emu/op-2.h #define _FP_UNPACK_RAW_2_P(fs, X, val) \ val 193 include/math-emu/op-2.h (union _FP_UNION_##fs *)(val); \ val 206 include/math-emu/op-2.h #define _FP_PACK_RAW_2(fs, val, X) \ val 215 include/math-emu/op-2.h (val) = _flo.flt; \ val 218 include/math-emu/op-2.h #define _FP_PACK_RAW_2_P(fs, val, X) \ val 221 include/math-emu/op-2.h (union _FP_UNION_##fs *)(val); \ val 184 include/math-emu/op-4.h #define _FP_UNPACK_RAW_4(fs, X, val) \ val 186 include/math-emu/op-4.h union _FP_UNION_##fs _flo; _flo.flt = (val); \ val 195 include/math-emu/op-4.h #define _FP_UNPACK_RAW_4_P(fs, X, val) \ val 198 include/math-emu/op-4.h (union _FP_UNION_##fs *)(val); \ val 208 include/math-emu/op-4.h #define _FP_PACK_RAW_4(fs, val, X) \ val 217 include/math-emu/op-4.h (val) = _flo.flt; \ val 220 include/math-emu/op-4.h #define _FP_PACK_RAW_4_P(fs, val, X) \ val 223 include/math-emu/op-4.h (union _FP_UNION_##fs *)(val); \ val 80 include/math-emu/quad.h #define FP_UNPACK_RAW_Q(X,val) _FP_UNPACK_RAW_4(Q,X,val) val 81 include/math-emu/quad.h #define FP_UNPACK_RAW_QP(X,val) _FP_UNPACK_RAW_4_P(Q,X,val) val 82 include/math-emu/quad.h #define FP_PACK_RAW_Q(val,X) _FP_PACK_RAW_4(Q,val,X) val 83 include/math-emu/quad.h #define FP_PACK_RAW_QP(val,X) \ val 86 include/math-emu/quad.h _FP_PACK_RAW_4_P(Q,val,X); \ val 89 include/math-emu/quad.h #define FP_UNPACK_Q(X,val) \ val 91 include/math-emu/quad.h _FP_UNPACK_RAW_4(Q,X,val); \ val 95 include/math-emu/quad.h #define FP_UNPACK_QP(X,val) \ val 97 include/math-emu/quad.h _FP_UNPACK_RAW_4_P(Q,X,val); \ val 101 include/math-emu/quad.h #define FP_PACK_Q(val,X) \ val 104 include/math-emu/quad.h _FP_PACK_RAW_4(Q,val,X); \ val 107 include/math-emu/quad.h #define FP_PACK_QP(val,X) \ val 111 include/math-emu/quad.h _FP_PACK_RAW_4_P(Q,val,X); \ val 153 include/math-emu/quad.h #define FP_UNPACK_RAW_Q(X,val) _FP_UNPACK_RAW_2(Q,X,val) val 154 include/math-emu/quad.h #define FP_UNPACK_RAW_QP(X,val) _FP_UNPACK_RAW_2_P(Q,X,val) val 155 include/math-emu/quad.h #define FP_PACK_RAW_Q(val,X) _FP_PACK_RAW_2(Q,val,X) val 156 include/math-emu/quad.h #define FP_PACK_RAW_QP(val,X) \ val 159 include/math-emu/quad.h _FP_PACK_RAW_2_P(Q,val,X); \ val 162 include/math-emu/quad.h #define FP_UNPACK_Q(X,val) \ val 164 include/math-emu/quad.h _FP_UNPACK_RAW_2(Q,X,val); \ val 168 include/math-emu/quad.h #define FP_UNPACK_QP(X,val) \ val 170 include/math-emu/quad.h _FP_UNPACK_RAW_2_P(Q,X,val); \ val 174 include/math-emu/quad.h #define FP_PACK_Q(val,X) \ val 177 include/math-emu/quad.h _FP_PACK_RAW_2(Q,val,X); \ val 180 include/math-emu/quad.h #define FP_PACK_QP(val,X) \ val 184 include/math-emu/quad.h _FP_PACK_RAW_2_P(Q,val,X); \ val 63 include/math-emu/single.h #define FP_UNPACK_RAW_S(X,val) _FP_UNPACK_RAW_1(S,X,val) val 64 include/math-emu/single.h #define FP_UNPACK_RAW_SP(X,val) _FP_UNPACK_RAW_1_P(S,X,val) val 65 include/math-emu/single.h #define FP_PACK_RAW_S(val,X) _FP_PACK_RAW_1(S,val,X) val 66 include/math-emu/single.h #define FP_PACK_RAW_SP(val,X) \ val 69 include/math-emu/single.h _FP_PACK_RAW_1_P(S,val,X); \ val 72 include/math-emu/single.h #define FP_UNPACK_S(X,val) \ val 74 include/math-emu/single.h _FP_UNPACK_RAW_1(S,X,val); \ val 78 include/math-emu/single.h #define FP_UNPACK_SP(X,val) \ val 80 include/math-emu/single.h _FP_UNPACK_RAW_1_P(S,X,val); \ val 84 include/math-emu/single.h #define FP_PACK_S(val,X) \ val 87 include/math-emu/single.h _FP_PACK_RAW_1(S,val,X); \ val 90 include/math-emu/single.h #define FP_PACK_SP(val,X) \ val 94 include/math-emu/single.h _FP_PACK_RAW_1_P(S,val,X); \ val 330 include/media/davinci/vpbe_osd.h void (*set_left_margin)(struct osd_state *sd, u32 val); val 331 include/media/davinci/vpbe_osd.h void (*set_top_margin)(struct osd_state *sd, u32 val); val 96 include/media/drv-intf/cx2341x.h int (*s_audio_sampling_freq)(struct cx2341x_handler *hdl, u32 val); val 98 include/media/drv-intf/cx2341x.h int (*s_audio_mode)(struct cx2341x_handler *hdl, u32 val); val 100 include/media/drv-intf/cx2341x.h int (*s_video_encoding)(struct cx2341x_handler *hdl, u32 val); val 102 include/media/drv-intf/cx2341x.h int (*s_stream_vbi_fmt)(struct cx2341x_handler *hdl, u32 val); val 28 include/media/drv-intf/tea575x.h void (*write_val)(struct snd_tea575x *tea, u32 val); val 48 include/media/drv-intf/tea575x.h unsigned int val; /* hw value */ val 252 include/media/v4l2-ctrls.h s32 val; val 254 include/media/v4l2-ctrls.h s32 val; val 953 include/media/v4l2-ctrls.h int __v4l2_ctrl_s_ctrl(struct v4l2_ctrl *ctrl, s32 val); val 967 include/media/v4l2-ctrls.h static inline int v4l2_ctrl_s_ctrl(struct v4l2_ctrl *ctrl, s32 val) val 972 include/media/v4l2-ctrls.h rval = __v4l2_ctrl_s_ctrl(ctrl, val); val 1004 include/media/v4l2-ctrls.h int __v4l2_ctrl_s_ctrl_int64(struct v4l2_ctrl *ctrl, s64 val); val 1019 include/media/v4l2-ctrls.h static inline int v4l2_ctrl_s_ctrl_int64(struct v4l2_ctrl *ctrl, s64 val) val 1024 include/media/v4l2-ctrls.h rval = __v4l2_ctrl_s_ctrl_int64(ctrl, val); val 192 include/media/v4l2-subdev.h int (*init)(struct v4l2_subdev *sd, u32 val); val 194 include/media/v4l2-subdev.h int (*reset)(struct v4l2_subdev *sd, u32 val); val 195 include/media/v4l2-subdev.h int (*s_gpio)(struct v4l2_subdev *sd, u32 val); val 254 include/misc/ocxl.h enum ocxl_endian endian, u32 *val); val 267 include/misc/ocxl.h enum ocxl_endian endian, u64 *val); val 280 include/misc/ocxl.h enum ocxl_endian endian, u32 val); val 293 include/misc/ocxl.h enum ocxl_endian endian, u64 val); val 291 include/net/addrconf.h int inet6addr_notifier_call_chain(unsigned long val, void *v); val 295 include/net/addrconf.h int inet6addr_validator_notifier_call_chain(unsigned long val, void *v); val 16 include/net/arp.h u32 val = key ^ hash32_ptr(dev); val 18 include/net/arp.h return val * hash_rnd[0]; val 125 include/net/bluetooth/hci_core.h u8 val[16]; val 138 include/net/bluetooth/hci_core.h u8 val[16]; val 147 include/net/bluetooth/hci_core.h u8 val[16]; val 155 include/net/bluetooth/hci_core.h u8 val[HCI_LINK_KEY_SIZE]; val 1107 include/net/bluetooth/hci_core.h bdaddr_t *bdaddr, u8 *val, u8 type, val 1122 include/net/bluetooth/hci_core.h u8 addr_type, u8 val[16], bdaddr_t *rpa); val 325 include/net/bluetooth/l2cap.h __u8 val[0]; val 120 include/net/bluetooth/mgmt.h __u8 val; val 129 include/net/bluetooth/mgmt.h __u8 val; val 177 include/net/bluetooth/mgmt.h __u8 val[16]; val 202 include/net/bluetooth/mgmt.h __u8 val[16]; val 409 include/net/bluetooth/mgmt.h __u8 val[16]; val 810 include/net/bluetooth/mgmt.h __u8 val[16]; val 99 include/net/bond_options.h int (*set)(struct bonding *bond, const struct bond_opt_value *val); val 103 include/net/bond_options.h struct bond_opt_value *val); val 105 include/net/bond_options.h struct bond_opt_value *val); val 109 include/net/bond_options.h struct bond_opt_value *val); val 112 include/net/bond_options.h const struct bond_opt_value *bond_opt_get_val(unsigned int option, u64 val); val 90 include/net/codel.h static inline u32 codel_time_to_us(codel_time_t val) val 92 include/net/codel.h u64 valns = ((u64)val << CODEL_SHIFT); val 80 include/net/codel_impl.h u64 val = (3LL << 32) - ((u64)vars->count * invsqrt2); val 82 include/net/codel_impl.h val >>= 2; /* avoid overflow in following multiply */ val 83 include/net/codel_impl.h val = (val * invsqrt) >> (32 - 2 + 1); val 85 include/net/codel_impl.h vars->rec_inv_sqrt = val >> REC_INV_SQRT_SHIFT; val 18 include/net/dcbevent.h int call_dcbevent_notifiers(unsigned long val, void *v); val 31 include/net/dcbevent.h static inline int call_dcbevent_notifiers(unsigned long val, void *v) val 352 include/net/devlink.h union devlink_param_value val; val 382 include/net/devlink.h union devlink_param_value val, val 367 include/net/dsa.h int regnum, u16 val); val 615 include/net/dsa.h int call_dsa_notifiers(unsigned long val, struct net_device *dev, val 628 include/net/dsa.h static inline int call_dsa_notifiers(unsigned long val, struct net_device *dev, val 106 include/net/dst.h unsigned long val = dst->_metrics; val 107 include/net/dst.h if (!(val & DST_METRICS_READ_ONLY)) val 108 include/net/dst.h __dst_destroy_metrics_generic(dst, val); val 177 include/net/dst.h static inline void dst_metric_set(struct dst_entry *dst, int metric, u32 val) val 182 include/net/dst.h p[metric-1] = val; val 56 include/net/dst_ops.h static inline void dst_entries_add(struct dst_ops *dst, int val) val 58 include/net/dst_ops.h percpu_counter_add(&dst->pcpuc_entries, val); val 175 include/net/flow_offload.h u32 val; val 144 include/net/inet_frag.h static inline void sub_frag_mem_limit(struct fqdir *fqdir, long val) val 146 include/net/inet_frag.h atomic_long_sub(val, &fqdir->mem); val 149 include/net/inet_frag.h static inline void add_frag_mem_limit(struct fqdir *fqdir, long val) val 151 include/net/inet_frag.h atomic_long_add(val, &fqdir->mem); val 287 include/net/ip.h #define IP_ADD_STATS(net, field, val) SNMP_ADD_STATS64((net)->mib.ip_statistics, field, val) val 288 include/net/ip.h #define __IP_ADD_STATS(net, field, val) __SNMP_ADD_STATS64((net)->mib.ip_statistics, field, val) val 289 include/net/ip.h #define IP_UPD_PO_STATS(net, field, val) SNMP_UPD_PO_STATS64((net)->mib.ip_statistics, field, val) val 290 include/net/ip.h #define __IP_UPD_PO_STATS(net, field, val) __SNMP_UPD_PO_STATS64((net)->mib.ip_statistics, field, val) val 501 include/net/ip6_fib.h void fib6_metric_set(struct fib6_info *f6i, int metric, u32 val); val 232 include/net/ipv6.h #define _DEVADD(net, statname, mod, idev, field, val) \ val 236 include/net/ipv6.h mod##SNMP_ADD_STATS((_idev)->stats.statname, (field), (val)); \ val 237 include/net/ipv6.h mod##SNMP_ADD_STATS((net)->mib.statname##_statistics, (field), (val));\ val 240 include/net/ipv6.h #define _DEVUPD(net, statname, mod, idev, field, val) \ val 244 include/net/ipv6.h mod##SNMP_UPD_PO_STATS((_idev)->stats.statname, field, (val)); \ val 245 include/net/ipv6.h mod##SNMP_UPD_PO_STATS((net)->mib.statname##_statistics, field, (val));\ val 254 include/net/ipv6.h #define IP6_ADD_STATS(net, idev,field,val) \ val 255 include/net/ipv6.h _DEVADD(net, ipv6, , idev, field, val) val 256 include/net/ipv6.h #define __IP6_ADD_STATS(net, idev,field,val) \ val 257 include/net/ipv6.h _DEVADD(net, ipv6, __, idev, field, val) val 258 include/net/ipv6.h #define IP6_UPD_PO_STATS(net, idev,field,val) \ val 259 include/net/ipv6.h _DEVUPD(net, ipv6, , idev, field, val) val 260 include/net/ipv6.h #define __IP6_UPD_PO_STATS(net, idev,field,val) \ val 261 include/net/ipv6.h _DEVUPD(net, ipv6, __, idev, field, val) val 65 include/net/ndisc.h #define ND_PRINTK(val, level, fmt, ...) \ val 67 include/net/ndisc.h if (val <= ND_DEBUG) \ val 88 include/net/neighbour.h static inline void neigh_var_set(struct neigh_parms *p, int index, int val) val 91 include/net/neighbour.h p->data[index] = val; val 99 include/net/neighbour.h #define NEIGH_VAR_INIT(p, attr, val) (NEIGH_VAR(p, attr) = val) val 100 include/net/neighbour.h #define NEIGH_VAR_SET(p, attr, val) neigh_var_set(p, NEIGH_VAR_ ## attr, val) val 36 include/net/netevent.h int call_netevent_notifiers(unsigned long val, void *v); val 284 include/net/netfilter/nf_conntrack.h int nf_conntrack_set_hashsize(const char *val, const struct kernel_param *kp); val 111 include/net/netfilter/nf_tables.h static inline void nft_reg_store8(u32 *dreg, u8 val) val 114 include/net/netfilter/nf_tables.h *(u8 *)dreg = val; val 122 include/net/netfilter/nf_tables.h static inline void nft_reg_store16(u32 *dreg, u16 val) val 125 include/net/netfilter/nf_tables.h *(u16 *)dreg = val; val 133 include/net/netfilter/nf_tables.h static inline void nft_reg_store64(u32 *dreg, u64 val) val 135 include/net/netfilter/nf_tables.h put_unaligned(val, (u64 *)dreg); val 239 include/net/netfilter/nf_tables.h struct nft_data val; val 228 include/net/nfc/nci.h __u8 val[NCI_MAX_PARAM_LEN]; val 288 include/net/nfc/nci_core.h int nci_set_config(struct nci_dev *ndev, __u8 id, size_t len, __u8 *val); val 539 include/net/pkt_cls.h u32 val; val 114 include/net/red.h #define MAX_P_ALPHA(val) min(MAX_P_MIN, val / 4) val 538 include/net/sock.h int sk_set_peek_off(struct sock *sk, int val); val 549 include/net/sock.h static inline void sk_peek_offset_bwd(struct sock *sk, int val) val 554 include/net/sock.h off = max_t(s32, off - val, 0); val 559 include/net/sock.h static inline void sk_peek_offset_fwd(struct sock *sk, int val) val 561 include/net/sock.h sk_peek_offset_bwd(sk, -val); val 894 include/net/sock.h static inline void sk_wmem_queued_add(struct sock *sk, int val) val 896 include/net/sock.h WRITE_ONCE(sk->sk_wmem_queued, sk->sk_wmem_queued + val); val 1397 include/net/sock.h long val = sk->sk_prot->sysctl_mem[index]; val 1400 include/net/sock.h val <<= PAGE_SHIFT - SK_MEM_QUANTUM_SHIFT; val 1402 include/net/sock.h val >>= SK_MEM_QUANTUM_SHIFT - PAGE_SHIFT; val 1404 include/net/sock.h return val; val 2233 include/net/sock.h u32 val; val 2238 include/net/sock.h val = min(sk->sk_sndbuf, sk->sk_wmem_queued >> 1); val 2240 include/net/sock.h WRITE_ONCE(sk->sk_sndbuf, max_t(u32, val, SOCK_MIN_SNDBUF)); val 2590 include/net/sock.h static inline void sk_pacing_shift_update(struct sock *sk, int val) val 2592 include/net/sock.h if (!sk || !sk_fullsock(sk) || READ_ONCE(sk->sk_pacing_shift) == val) val 2594 include/net/sock.h WRITE_ONCE(sk->sk_pacing_shift, val); val 169 include/net/switchdev.h int call_switchdev_notifiers(unsigned long val, struct net_device *dev, val 175 include/net/switchdev.h int call_switchdev_blocking_notifiers(unsigned long val, struct net_device *dev, val 237 include/net/switchdev.h static inline int call_switchdev_notifiers(unsigned long val, val 258 include/net/switchdev.h call_switchdev_blocking_notifiers(unsigned long val, val 47 include/net/tc_act/tc_ife.h int (*validate)(void *val, int len); val 60 include/net/tc_act/tc_ife.h int ife_validate_meta_u32(void *val, int len); val 61 include/net/tc_act/tc_ife.h int ife_validate_meta_u16(void *val, int len); val 60 include/net/tc_act/tc_pedit.h return to_pedit(a)->tcfp_keys[index].val; val 311 include/net/tcp.h #define TCP_ADD_STATS(net, field, val) SNMP_ADD_STATS((net)->mib.tcp_statistics, field, val) val 402 include/net/tcp.h void tcp_set_keepalive(struct sock *sk, int val); val 406 include/net/tcp.h int tcp_set_rcvlowat(struct sock *sk, int val); val 542 include/net/tcp.h u64 val = get_jiffies_64(); val 544 include/net/tcp.h do_div(val, TCP_SYNCOOKIE_PERIOD); val 545 include/net/tcp.h return val; val 1698 include/net/tcp.h !memcmp(orig->val, foc->val, foc->len)) val 200 include/pcmcia/ds.h int pcmcia_read_config_byte(struct pcmcia_device *p_dev, off_t where, u8 *val); val 201 include/pcmcia/ds.h int pcmcia_write_config_byte(struct pcmcia_device *p_dev, off_t where, u8 val); val 157 include/rdma/ib_hdrs.h static inline void ib_u64_put(u64 val, __be64 *p) val 159 include/rdma/ib_hdrs.h put_unaligned_be64(val, p); val 167 include/rdma/ib_hdrs.h static inline void put_ib_reth_vaddr(u64 val, struct ib_reth *reth) val 169 include/rdma/ib_hdrs.h ib_u64_put(val, &reth->vaddr); val 177 include/rdma/ib_hdrs.h static inline void put_ib_ateth_vaddr(u64 val, struct ib_atomic_eth *ateth) val 179 include/rdma/ib_hdrs.h ib_u64_put(val, &ateth->vaddr); val 187 include/rdma/ib_hdrs.h static inline void put_ib_ateth_swap(u64 val, struct ib_atomic_eth *ateth) val 189 include/rdma/ib_hdrs.h ib_u64_put(val, &ateth->swap_data); val 197 include/rdma/ib_hdrs.h static inline void put_ib_ateth_compare(u64 val, struct ib_atomic_eth *ateth) val 199 include/rdma/ib_hdrs.h ib_u64_put(val, &ateth->compare_data); val 1869 include/rdma/ib_verbs.h struct ib_flow_eth_filter val; val 1883 include/rdma/ib_verbs.h struct ib_flow_ib_filter val; val 1908 include/rdma/ib_verbs.h struct ib_flow_ipv4_filter val; val 1926 include/rdma/ib_verbs.h struct ib_flow_ipv6_filter val; val 1940 include/rdma/ib_verbs.h struct ib_flow_tcp_udp_filter val; val 1955 include/rdma/ib_verbs.h struct ib_flow_tunnel_filter val; val 1969 include/rdma/ib_verbs.h struct ib_flow_esp_filter val; val 1984 include/rdma/ib_verbs.h struct ib_flow_gre_filter val; val 1997 include/rdma/ib_verbs.h struct ib_flow_mpls_filter val; val 68 include/rdma/rdmavt_cq.h #define RDMA_READ_UAPI_ATOMIC(member) smp_load_acquire(&(member).val) val 74 include/rdma/rdmavt_cq.h #define RDMA_WRITE_UAPI_ATOMIC(member, x) smp_store_release(&(member).val, x) val 778 include/rdma/rdmavt_qp.h rvt_qp_swqe_incr(struct rvt_qp *qp, u32 val) val 780 include/rdma/rdmavt_qp.h if (++val >= qp->s_size) val 781 include/rdma/rdmavt_qp.h val = 0; val 782 include/rdma/rdmavt_qp.h return val; val 25 include/soc/at91/atmel-sfr.h #define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs)) val 166 include/soc/fsl/qe/qe.h extern int par_io_data_set(u8 port, u8 pin, u8 val); val 172 include/soc/fsl/qe/qe.h static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } val 427 include/soc/fsl/qman.h static inline int qm_fqd_set_taildrop(struct qm_fqd *fqd, u32 val, val 433 include/soc/fsl/qman.h if (val > QM_FQD_TD_MAX) val 436 include/soc/fsl/qman.h while (val > QM_FQD_TD_MANT_MAX) { val 437 include/soc/fsl/qman.h oddbit = val & 1; val 438 include/soc/fsl/qman.h val >>= 1; val 441 include/soc/fsl/qman.h val++; val 444 include/soc/fsl/qman.h td = (val << QM_FQD_TD_MANT_OFF) & QM_FQD_TD_MANT_MASK; val 472 include/soc/fsl/qman.h static inline void qm_fqd_set_oac(struct qm_fqd *fqd, u8 val) val 474 include/soc/fsl/qman.h fqd->oac_init.oac = val << QM_FQD_OAC_OFF; val 477 include/soc/fsl/qman.h static inline void qm_fqd_set_oal(struct qm_fqd *fqd, s8 val) val 479 include/soc/fsl/qman.h fqd->oac_init.oal = val; val 584 include/soc/fsl/qman.h static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val, val 590 include/soc/fsl/qman.h while (val > 0xff) { val 591 include/soc/fsl/qman.h oddbit = val & 1; val 592 include/soc/fsl/qman.h val >>= 1; val 595 include/soc/fsl/qman.h val++; val 597 include/soc/fsl/qman.h th->word = cpu_to_be16(((val & 0xff) << 5) | (e & 0x1f)); val 58 include/sound/ac97/controller.h unsigned short reg, unsigned short val); val 192 include/sound/ac97_codec.h void (*write) (struct snd_ac97 *ac97, unsigned short reg, unsigned short val); val 16 include/sound/ad1843.h int (*write)(void *chip, int reg, int val); val 304 include/sound/ak4113.h unsigned char mask, unsigned char val); val 185 include/sound/ak4114.h void snd_ak4114_reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char mask, unsigned char val); val 172 include/sound/ak4117.h void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val); val 54 include/sound/ak4531_codec.h unsigned short val); val 22 include/sound/ak4xxx-adda.h unsigned char val); val 71 include/sound/ak4xxx-adda.h unsigned char val); val 78 include/sound/ak4xxx-adda.h #define snd_akm4xxx_set(ak,chip,reg,val) \ val 79 include/sound/ak4xxx-adda.h ((ak)->images[(chip) * 16 + (reg)] = (val)) val 82 include/sound/ak4xxx-adda.h #define snd_akm4xxx_set_vol(ak,chip,reg,val) \ val 83 include/sound/ak4xxx-adda.h ((ak)->volumes[(chip) * 16 + (reg)] = (val)) val 403 include/sound/core.h #define SND_PCI_QUIRK(vend,dev,xname,val) \ val 404 include/sound/core.h {_SND_PCI_QUIRK_ID(vend, dev), .value = (val), .name = (xname)} val 405 include/sound/core.h #define SND_PCI_QUIRK_VENDOR(vend, xname, val) \ val 406 include/sound/core.h {_SND_PCI_QUIRK_ID_MASK(vend, 0, 0), .value = (val), .name = (xname)} val 407 include/sound/core.h #define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ val 409 include/sound/core.h .value = (val), .name = (xname)} val 412 include/sound/core.h #define SND_PCI_QUIRK(vend,dev,xname,val) \ val 413 include/sound/core.h {_SND_PCI_QUIRK_ID(vend, dev), .value = (val)} val 414 include/sound/core.h #define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ val 415 include/sound/core.h {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), .value = (val)} val 416 include/sound/core.h #define SND_PCI_QUIRK_VENDOR(vend, xname, val) \ val 417 include/sound/core.h {_SND_PCI_QUIRK_ID_MASK(vend, 0, 0), .value = (val)} val 180 include/sound/cs8427.h unsigned char val); val 91 include/sound/emu8000.h unsigned int val); val 95 include/sound/emu8000.h unsigned int val); val 108 include/sound/emu8000_reg.h #define EMU8000_CPF_WRITE(emu, chan, val) \ val 109 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val)) val 110 include/sound/emu8000_reg.h #define EMU8000_PTRX_WRITE(emu, chan, val) \ val 111 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val)) val 112 include/sound/emu8000_reg.h #define EMU8000_CVCF_WRITE(emu, chan, val) \ val 113 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val)) val 114 include/sound/emu8000_reg.h #define EMU8000_VTFT_WRITE(emu, chan, val) \ val 115 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val)) val 116 include/sound/emu8000_reg.h #define EMU8000_PSST_WRITE(emu, chan, val) \ val 117 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val)) val 118 include/sound/emu8000_reg.h #define EMU8000_CSL_WRITE(emu, chan, val) \ val 119 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan)), (val)) val 120 include/sound/emu8000_reg.h #define EMU8000_CCCA_WRITE(emu, chan, val) \ val 121 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan)), (val)) val 122 include/sound/emu8000_reg.h #define EMU8000_HWCF4_WRITE(emu, val) \ val 123 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9), (val)) val 124 include/sound/emu8000_reg.h #define EMU8000_HWCF5_WRITE(emu, val) \ val 125 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10), (val)) val 126 include/sound/emu8000_reg.h #define EMU8000_HWCF6_WRITE(emu, val) \ val 127 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13), (val)) val 129 include/sound/emu8000_reg.h #define EMU8000_HWCF7_WRITE(emu, val) \ val 130 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 14), (val)) val 131 include/sound/emu8000_reg.h #define EMU8000_SMALR_WRITE(emu, val) \ val 132 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20), (val)) val 133 include/sound/emu8000_reg.h #define EMU8000_SMARR_WRITE(emu, val) \ val 134 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21), (val)) val 135 include/sound/emu8000_reg.h #define EMU8000_SMALW_WRITE(emu, val) \ val 136 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22), (val)) val 137 include/sound/emu8000_reg.h #define EMU8000_SMARW_WRITE(emu, val) \ val 138 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23), (val)) val 139 include/sound/emu8000_reg.h #define EMU8000_SMLD_WRITE(emu, val) \ val 140 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26), (val)) val 141 include/sound/emu8000_reg.h #define EMU8000_SMRD_WRITE(emu, val) \ val 142 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26), (val)) val 143 include/sound/emu8000_reg.h #define EMU8000_WC_WRITE(emu, val) \ val 144 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27), (val)) val 145 include/sound/emu8000_reg.h #define EMU8000_HWCF1_WRITE(emu, val) \ val 146 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29), (val)) val 147 include/sound/emu8000_reg.h #define EMU8000_HWCF2_WRITE(emu, val) \ val 148 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30), (val)) val 149 include/sound/emu8000_reg.h #define EMU8000_HWCF3_WRITE(emu, val) \ val 150 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31), (val)) val 151 include/sound/emu8000_reg.h #define EMU8000_INIT1_WRITE(emu, chan, val) \ val 152 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan)), (val)) val 153 include/sound/emu8000_reg.h #define EMU8000_INIT2_WRITE(emu, chan, val) \ val 154 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan)), (val)) val 155 include/sound/emu8000_reg.h #define EMU8000_INIT3_WRITE(emu, chan, val) \ val 156 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan)), (val)) val 157 include/sound/emu8000_reg.h #define EMU8000_INIT4_WRITE(emu, chan, val) \ val 158 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan)), (val)) val 159 include/sound/emu8000_reg.h #define EMU8000_ENVVOL_WRITE(emu, chan, val) \ val 160 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan)), (val)) val 161 include/sound/emu8000_reg.h #define EMU8000_DCYSUSV_WRITE(emu, chan, val) \ val 162 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan)), (val)) val 163 include/sound/emu8000_reg.h #define EMU8000_ENVVAL_WRITE(emu, chan, val) \ val 164 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan)), (val)) val 165 include/sound/emu8000_reg.h #define EMU8000_DCYSUS_WRITE(emu, chan, val) \ val 166 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan)), (val)) val 167 include/sound/emu8000_reg.h #define EMU8000_ATKHLDV_WRITE(emu, chan, val) \ val 168 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan)), (val)) val 169 include/sound/emu8000_reg.h #define EMU8000_LFO1VAL_WRITE(emu, chan, val) \ val 170 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan)), (val)) val 171 include/sound/emu8000_reg.h #define EMU8000_ATKHLD_WRITE(emu, chan, val) \ val 172 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan)), (val)) val 173 include/sound/emu8000_reg.h #define EMU8000_LFO2VAL_WRITE(emu, chan, val) \ val 174 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan)), (val)) val 175 include/sound/emu8000_reg.h #define EMU8000_IP_WRITE(emu, chan, val) \ val 176 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan)), (val)) val 177 include/sound/emu8000_reg.h #define EMU8000_IFATN_WRITE(emu, chan, val) \ val 178 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan)), (val)) val 179 include/sound/emu8000_reg.h #define EMU8000_PEFE_WRITE(emu, chan, val) \ val 180 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan)), (val)) val 181 include/sound/emu8000_reg.h #define EMU8000_FMMOD_WRITE(emu, chan, val) \ val 182 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan)), (val)) val 183 include/sound/emu8000_reg.h #define EMU8000_TREMFRQ_WRITE(emu, chan, val) \ val 184 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan)), (val)) val 185 include/sound/emu8000_reg.h #define EMU8000_FM2FRQ2_WRITE(emu, chan, val) \ val 186 include/sound/emu8000_reg.h snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan)), (val)) val 188 include/sound/emu8000_reg.h #define EMU8000_0080_WRITE(emu, chan, val) \ val 189 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(4, (chan)), (val)) val 190 include/sound/emu8000_reg.h #define EMU8000_00A0_WRITE(emu, chan, val) \ val 191 include/sound/emu8000_reg.h snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(5, (chan)), (val)) val 209 include/sound/emux_synth.h short val[EMUX_NUM_EFFECTS]; val 20 include/sound/hda_regmap.h unsigned int *val); val 22 include/sound/hda_regmap.h unsigned int reg, unsigned int *val); val 24 include/sound/hda_regmap.h unsigned int val); val 26 include/sound/hda_regmap.h unsigned int mask, unsigned int val); val 28 include/sound/hda_regmap.h unsigned int mask, unsigned int val); val 80 include/sound/hda_regmap.h unsigned int verb, unsigned int val) val 84 include/sound/hda_regmap.h return snd_hdac_regmap_write_raw(codec, cmd, val); val 99 include/sound/hda_regmap.h unsigned int val) val 103 include/sound/hda_regmap.h return snd_hdac_regmap_update_raw(codec, cmd, mask, val); val 116 include/sound/hda_regmap.h unsigned int verb, unsigned int *val) val 120 include/sound/hda_regmap.h return snd_hdac_regmap_read_raw(codec, cmd, val); val 140 include/sound/hda_regmap.h int err, val; val 142 include/sound/hda_regmap.h err = snd_hdac_regmap_read_raw(codec, cmd, &val); val 143 include/sound/hda_regmap.h return err < 0 ? err : val; val 161 include/sound/hda_regmap.h int ch, int dir, int idx, int mask, int val) val 165 include/sound/hda_regmap.h return snd_hdac_regmap_update_raw(codec, cmd, mask, val); val 185 include/sound/hda_regmap.h int err, val; val 187 include/sound/hda_regmap.h err = snd_hdac_regmap_read_raw(codec, cmd, &val); val 188 include/sound/hda_regmap.h return err < 0 ? err : val; val 206 include/sound/hda_regmap.h int dir, int idx, int mask, int val) val 210 include/sound/hda_regmap.h return snd_hdac_regmap_update_raw(codec, cmd, mask, val); val 134 include/sound/hdaudio.h unsigned int parm, unsigned int val); val 169 include/sound/hdaudio.h unsigned int val; val 171 include/sound/hdaudio.h return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; val 386 include/sound/hdaudio.h int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); val 409 include/sound/hdaudio.h void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, val 415 include/sound/hdaudio.h #define snd_hdac_aligned_write(val, addr, mask) do {} while (0) val 419 include/sound/hdaudio.h u8 val) val 422 include/sound/hdaudio.h snd_hdac_aligned_write(val, addr, 0xff); val 424 include/sound/hdaudio.h writeb(val, addr); val 428 include/sound/hdaudio.h u16 val) val 431 include/sound/hdaudio.h snd_hdac_aligned_write(val, addr, 0xffff); val 433 include/sound/hdaudio.h writew(val, addr); val 448 include/sound/hdaudio.h #define snd_hdac_reg_writel(bus, addr, val) writel(val, addr) val 482 include/sound/hdaudio.h #define snd_hdac_chip_updatel(chip, reg, mask, val) \ val 484 include/sound/hdaudio.h (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) val 485 include/sound/hdaudio.h #define snd_hdac_chip_updatew(chip, reg, mask, val) \ val 487 include/sound/hdaudio.h (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) val 488 include/sound/hdaudio.h #define snd_hdac_chip_updateb(chip, reg, mask, val) \ val 490 include/sound/hdaudio.h (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) val 586 include/sound/hdaudio.h #define snd_hdac_stream_updatel(dev, reg, mask, val) \ val 589 include/sound/hdaudio.h ~(mask)) | (val)) val 590 include/sound/hdaudio.h #define snd_hdac_stream_updatew(dev, reg, mask, val) \ val 593 include/sound/hdaudio.h ~(mask)) | (val)) val 594 include/sound/hdaudio.h #define snd_hdac_stream_updateb(dev, reg, mask, val) \ val 597 include/sound/hdaudio.h ~(mask)) | (val)) val 135 include/sound/hdaudio_ext.h #define snd_hdac_updatel(addr, reg, mask, val) \ val 136 include/sound/hdaudio_ext.h writel(((readl(addr + reg) & ~(mask)) | (val)), \ val 139 include/sound/hdaudio_ext.h #define snd_hdac_updatew(addr, reg, mask, val) \ val 140 include/sound/hdaudio_ext.h writew(((readw(addr + reg) & ~(mask)) | (val)), \ val 290 include/sound/opl3.h void (*command) (struct snd_opl3 * opl3, unsigned short cmd, unsigned char val); val 1023 include/sound/pcm.h unsigned int val) val 1025 include/sound/pcm.h return snd_pcm_hw_constraint_minmax(runtime, var, val, val); val 70 include/sound/pcm_params.h static inline void snd_mask_set(struct snd_mask *mask, unsigned int val) val 72 include/sound/pcm_params.h mask->bits[MASK_OFS(val)] |= MASK_BIT(val); val 82 include/sound/pcm_params.h static inline void snd_mask_reset(struct snd_mask *mask, unsigned int val) val 84 include/sound/pcm_params.h mask->bits[MASK_OFS(val)] &= ~MASK_BIT(val); val 103 include/sound/pcm_params.h static inline void snd_mask_leave(struct snd_mask *mask, unsigned int val) val 106 include/sound/pcm_params.h v = mask->bits[MASK_OFS(val)] & MASK_BIT(val); val 108 include/sound/pcm_params.h mask->bits[MASK_OFS(val)] = v; val 131 include/sound/pcm_params.h static inline int snd_mask_test(const struct snd_mask *mask, unsigned int val) val 133 include/sound/pcm_params.h return mask->bits[MASK_OFS(val)] & MASK_BIT(val); val 178 include/sound/pcm_params.h static inline int snd_mask_refine_min(struct snd_mask *mask, unsigned int val) val 180 include/sound/pcm_params.h if (snd_mask_min(mask) >= val) val 182 include/sound/pcm_params.h snd_mask_reset_range(mask, 0, val - 1); val 188 include/sound/pcm_params.h static inline int snd_mask_refine_max(struct snd_mask *mask, unsigned int val) val 190 include/sound/pcm_params.h if (snd_mask_max(mask) <= val) val 192 include/sound/pcm_params.h snd_mask_reset_range(mask, val + 1, SNDRV_MASK_BITS); val 198 include/sound/pcm_params.h static inline int snd_mask_refine_set(struct snd_mask *mask, unsigned int val) val 202 include/sound/pcm_params.h snd_mask_leave(mask, val); val 266 include/sound/pcm_params.h static inline int snd_interval_test(const struct snd_interval *i, unsigned int val) val 268 include/sound/pcm_params.h return !((i->min > val || (i->min == val && i->openmin) || val 269 include/sound/pcm_params.h i->max < val || (i->max == val && i->openmax))); val 32 include/sound/pxa2xx-lib.h extern int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val); val 276 include/sound/sb.h int snd_sbdsp_command(struct snd_sb *chip, unsigned char val); val 51 include/sound/soc-component.h unsigned int reg, unsigned int val); val 258 include/sound/soc-component.h unsigned int reg, unsigned int *val); val 262 include/sound/soc-component.h unsigned int reg, unsigned int val); val 265 include/sound/soc-component.h unsigned int val); val 268 include/sound/soc-component.h unsigned int val); val 653 include/sound/soc-dapm.h int val; val 1237 include/sound/soc.h unsigned int val) val 1242 include/sound/soc.h return val; val 1245 include/sound/soc.h if (val == e->values[i]) val 78 include/sound/vx_core.h void (*out8)(struct vx_core *chip, int reg, unsigned char val); val 79 include/sound/vx_core.h void (*out32)(struct vx_core *chip, int reg, unsigned int val); val 234 include/sound/vx_core.h static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val) val 236 include/sound/vx_core.h chip->ops->out8(chip, reg, val); val 239 include/sound/vx_core.h static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val) val 241 include/sound/vx_core.h chip->ops->out32(chip, reg, val); val 245 include/sound/vx_core.h #define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val) val 247 include/sound/vx_core.h #define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val) val 121 include/sound/wss.h void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char val); val 124 include/sound/wss.h unsigned char reg, unsigned char val); val 21 include/trace/events/asoc.h TP_PROTO(struct snd_soc_card *card, int val), val 23 include/trace/events/asoc.h TP_ARGS(card, val), val 27 include/trace/events/asoc.h __field( int, val ) val 32 include/trace/events/asoc.h __entry->val = val; val 35 include/trace/events/asoc.h TP_printk("card=%s val=%d", __get_str(name), (int)__entry->val) val 40 include/trace/events/asoc.h TP_PROTO(struct snd_soc_card *card, int val), val 42 include/trace/events/asoc.h TP_ARGS(card, val) val 48 include/trace/events/asoc.h TP_PROTO(struct snd_soc_card *card, int val), val 50 include/trace/events/asoc.h TP_ARGS(card, val) val 89 include/trace/events/asoc.h TP_PROTO(struct snd_soc_dapm_widget *w, int val), val 91 include/trace/events/asoc.h TP_ARGS(w, val), val 95 include/trace/events/asoc.h __field( int, val ) val 100 include/trace/events/asoc.h __entry->val = val; val 104 include/trace/events/asoc.h (int)__entry->val) val 109 include/trace/events/asoc.h TP_PROTO(struct snd_soc_dapm_widget *w, int val), val 111 include/trace/events/asoc.h TP_ARGS(w, val) val 117 include/trace/events/asoc.h TP_PROTO(struct snd_soc_dapm_widget *w, int val), val 119 include/trace/events/asoc.h TP_ARGS(w, val) val 125 include/trace/events/asoc.h TP_PROTO(struct snd_soc_dapm_widget *w, int val), val 127 include/trace/events/asoc.h TP_ARGS(w, val) val 229 include/trace/events/asoc.h TP_PROTO(struct snd_soc_jack *jack, int mask, int val), val 231 include/trace/events/asoc.h TP_ARGS(jack, mask, val), val 236 include/trace/events/asoc.h __field( int, val ) val 242 include/trace/events/asoc.h __entry->val = val; val 245 include/trace/events/asoc.h TP_printk("jack=%s %x/%x", __get_str(name), (int)__entry->val, val 251 include/trace/events/asoc.h TP_PROTO(struct snd_soc_jack *jack, int val), val 253 include/trace/events/asoc.h TP_ARGS(jack, val), val 257 include/trace/events/asoc.h __field( int, val ) val 262 include/trace/events/asoc.h __entry->val = val; val 265 include/trace/events/asoc.h TP_printk("jack=%s %x", __get_str(name), (int)__entry->val) val 1021 include/trace/events/btrfs.h TP_PROTO(const struct btrfs_fs_info *fs_info, char *type, u64 val, val 1024 include/trace/events/btrfs.h TP_ARGS(fs_info, type, val, bytes, reserve), val 1028 include/trace/events/btrfs.h __field( u64, val ) val 1035 include/trace/events/btrfs.h __entry->val = val; val 1040 include/trace/events/btrfs.h TP_printk_btrfs("%s: %llu %s %llu", __get_str(type), __entry->val, val 168 include/trace/events/cgroup.h TP_PROTO(struct cgroup *cgrp, const char *path, int val), val 170 include/trace/events/cgroup.h TP_ARGS(cgrp, path, val), val 177 include/trace/events/cgroup.h __field( int, val ) val 185 include/trace/events/cgroup.h __entry->val = val; val 190 include/trace/events/cgroup.h __entry->val) val 195 include/trace/events/cgroup.h TP_PROTO(struct cgroup *cgrp, const char *path, int val), val 197 include/trace/events/cgroup.h TP_ARGS(cgrp, path, val) val 202 include/trace/events/cgroup.h TP_PROTO(struct cgroup *cgrp, const char *path, int val), val 204 include/trace/events/cgroup.h TP_ARGS(cgrp, path, val) val 18 include/trace/events/filelock.h #define show_fl_flags(val) \ val 19 include/trace/events/filelock.h __print_flags(val, "|", \ val 32 include/trace/events/filelock.h #define show_fl_type(val) \ val 33 include/trace/events/filelock.h __print_symbolic(val, \ val 126 include/trace/events/fs_dax.h __entry->pfn_val = pfn.val; val 392 include/trace/events/fscache.h void *val, int n), val 394 include/trace/events/fscache.h TP_ARGS(cookie, page, val, n), val 399 include/trace/events/fscache.h __field(void *, val ) val 406 include/trace/events/fscache.h __entry->val = val; val 411 include/trace/events/fscache.h __entry->cookie, __entry->page, __entry->val, __entry->n) val 219 include/trace/events/host1x.h TP_PROTO(u32 id, u32 val), val 221 include/trace/events/host1x.h TP_ARGS(id, val), val 225 include/trace/events/host1x.h __field(u32, val) val 230 include/trace/events/host1x.h __entry->val = val; val 233 include/trace/events/host1x.h TP_printk("id=%d, val=%d", __entry->id, __entry->val) val 59 include/trace/events/hswadsp.h TP_PROTO(const char *name, int val), val 61 include/trace/events/hswadsp.h TP_ARGS(name, val), val 65 include/trace/events/hswadsp.h __field( unsigned int, val ) val 70 include/trace/events/hswadsp.h __entry->val = val; val 73 include/trace/events/hswadsp.h TP_printk("%s 0x%8.8x", __get_str(name), (unsigned int)__entry->val) val 79 include/trace/events/hswadsp.h TP_PROTO(const char *name, int val), val 81 include/trace/events/hswadsp.h TP_ARGS(name, val) val 87 include/trace/events/hswadsp.h TP_PROTO(const char *name, int val), val 89 include/trace/events/hswadsp.h TP_ARGS(name, val) val 95 include/trace/events/hswadsp.h TP_PROTO(const char *name, int val), val 97 include/trace/events/hswadsp.h TP_ARGS(name, val) val 103 include/trace/events/hswadsp.h TP_PROTO(const char *name, int val), val 105 include/trace/events/hswadsp.h TP_ARGS(name, val) val 111 include/trace/events/hswadsp.h TP_PROTO(const char *name, int val), val 113 include/trace/events/hswadsp.h TP_ARGS(name, val) val 12 include/trace/events/hwmon.h TP_PROTO(int index, const char *attr_name, long val), val 14 include/trace/events/hwmon.h TP_ARGS(index, attr_name, val), val 19 include/trace/events/hwmon.h __field(long, val) val 25 include/trace/events/hwmon.h __entry->val = val; val 29 include/trace/events/hwmon.h __entry->index, __get_str(attr_name), __entry->val) val 34 include/trace/events/hwmon.h TP_PROTO(int index, const char *attr_name, long val), val 36 include/trace/events/hwmon.h TP_ARGS(index, attr_name, val) val 41 include/trace/events/hwmon.h TP_PROTO(int index, const char *attr_name, long val), val 43 include/trace/events/hwmon.h TP_ARGS(index, attr_name, val) val 21 include/trace/events/intel-sst.h TP_PROTO(unsigned int val), val 23 include/trace/events/intel-sst.h TP_ARGS(val), val 26 include/trace/events/intel-sst.h __field( unsigned int, val ) val 30 include/trace/events/intel-sst.h __entry->val = val; val 33 include/trace/events/intel-sst.h TP_printk("0x%8.8x", (unsigned int)__entry->val) val 38 include/trace/events/intel-sst.h TP_PROTO(unsigned int val), val 40 include/trace/events/intel-sst.h TP_ARGS(val) val 46 include/trace/events/intel-sst.h TP_PROTO(unsigned int val), val 48 include/trace/events/intel-sst.h TP_ARGS(val) val 54 include/trace/events/intel-sst.h TP_PROTO(unsigned int offset, unsigned int val), val 56 include/trace/events/intel-sst.h TP_ARGS(offset, val), val 60 include/trace/events/intel-sst.h __field( unsigned int, val ) val 65 include/trace/events/intel-sst.h __entry->val = val; val 69 include/trace/events/intel-sst.h (unsigned int)__entry->offset, (unsigned int)__entry->val) val 74 include/trace/events/intel-sst.h TP_PROTO(unsigned int offset, unsigned int val), val 76 include/trace/events/intel-sst.h TP_ARGS(offset, val) val 82 include/trace/events/intel-sst.h TP_PROTO(unsigned int offset, unsigned int val), val 84 include/trace/events/intel-sst.h TP_ARGS(offset, val) val 90 include/trace/events/intel-sst.h TP_PROTO(unsigned int offset, unsigned int val), val 92 include/trace/events/intel-sst.h TP_ARGS(offset, val) val 98 include/trace/events/intel-sst.h TP_PROTO(unsigned int offset, unsigned int val), val 100 include/trace/events/intel-sst.h TP_ARGS(offset, val) val 39 include/trace/events/irq.h #define show_softirq_name(val) \ val 40 include/trace/events/irq.h __print_symbolic(val, SOFTIRQ_NAME_LIST) val 214 include/trace/events/kvm.h TP_PROTO(int type, int len, u64 gpa, void *val), val 215 include/trace/events/kvm.h TP_ARGS(type, len, gpa, val), val 221 include/trace/events/kvm.h __field( u64, val ) val 228 include/trace/events/kvm.h __entry->val = 0; val 229 include/trace/events/kvm.h if (val) val 230 include/trace/events/kvm.h memcpy(&__entry->val, val, val 231 include/trace/events/kvm.h min_t(u32, sizeof(__entry->val), len)); val 236 include/trace/events/kvm.h __entry->len, __entry->gpa, __entry->val) val 14 include/trace/events/libata.h #define show_opcode_name(val) \ val 15 include/trace/events/libata.h __print_symbolic(val, \ val 111 include/trace/events/libata.h #define show_error_name(val) \ val 112 include/trace/events/libata.h __print_symbolic(val, \ val 123 include/trace/events/libata.h #define show_protocol_name(val) \ val 124 include/trace/events/libata.h __print_symbolic(val, \ val 13 include/trace/events/mdio.h u8 addr, unsigned regnum, u16 val, int err), val 15 include/trace/events/mdio.h TP_ARGS(bus, read, addr, regnum, val, err), val 23 include/trace/events/mdio.h __field(u16, val) val 32 include/trace/events/mdio.h __entry->val = val; val 37 include/trace/events/mdio.h __entry->addr, __entry->regnum, __entry->val) val 26 include/trace/events/page_ref.h __field(int, val) val 36 include/trace/events/page_ref.h __entry->val = v; val 44 include/trace/events/page_ref.h __entry->val) val 74 include/trace/events/page_ref.h __field(int, val) val 85 include/trace/events/page_ref.h __entry->val = v; val 94 include/trace/events/page_ref.h __entry->val, __entry->ret) val 228 include/trace/events/power.h TP_PROTO(const char *action, int val, bool start), val 230 include/trace/events/power.h TP_ARGS(action, val, start), val 234 include/trace/events/power.h __field(int, val) val 240 include/trace/events/power.h __entry->val = val; val 244 include/trace/events/power.h TP_printk("%s[%u] %s", __entry->action, (unsigned int)__entry->val, val 113 include/trace/events/regulator.h TP_PROTO(const char *name, unsigned int val), val 115 include/trace/events/regulator.h TP_ARGS(name, val), val 119 include/trace/events/regulator.h __field( unsigned int, val ) val 124 include/trace/events/regulator.h __entry->val = val; val 128 include/trace/events/regulator.h (int)__entry->val) val 14 include/trace/events/scsi.h #define show_opcode_name(val) \ val 15 include/trace/events/scsi.h __print_symbolic(val, \ val 108 include/trace/events/scsi.h #define show_hostbyte_name(val) \ val 109 include/trace/events/scsi.h __print_symbolic(val, \ val 128 include/trace/events/scsi.h #define show_driverbyte_name(val) \ val 129 include/trace/events/scsi.h __print_symbolic(val, \ val 141 include/trace/events/scsi.h #define show_msgbyte_name(val) \ val 142 include/trace/events/scsi.h __print_symbolic(val, \ val 172 include/trace/events/scsi.h #define show_statusbyte_name(val) \ val 173 include/trace/events/scsi.h __print_symbolic(val, \ val 187 include/trace/events/scsi.h #define show_prot_op_name(val) \ val 188 include/trace/events/scsi.h __print_symbolic(val, \ val 58 include/trace/events/sock.h #define show_family_name(val) \ val 59 include/trace/events/sock.h __print_symbolic(val, family_names) val 61 include/trace/events/sock.h #define show_inet_protocol_name(val) \ val 62 include/trace/events/sock.h __print_symbolic(val, inet_protocol_names) val 64 include/trace/events/sock.h #define show_tcp_state_name(val) \ val 65 include/trace/events/sock.h __print_symbolic(val, tcp_state_names) val 67 include/trace/events/sock.h #define show_skmem_kind_names(val) \ val 68 include/trace/events/sock.h __print_symbolic(val, skmem_kind_names) val 16 include/trace/events/target.h #define show_opcode_name(val) \ val 17 include/trace/events/target.h __print_symbolic(val, \ val 111 include/trace/events/target.h #define show_task_attribute_name(val) \ val 112 include/trace/events/target.h __print_symbolic(val, \ val 118 include/trace/events/target.h #define show_scsi_status_name(val) \ val 119 include/trace/events/target.h __print_symbolic(val, \ val 394 include/trace/events/timer.h #define show_tick_dep_name(val) \ val 395 include/trace/events/timer.h __print_symbolic(val, TICK_DEP_NAMES) val 13 include/trace/events/vsock_virtio_transport_common.h #define show_type(val) \ val 14 include/trace/events/vsock_virtio_transport_common.h __print_symbolic(val, { VIRTIO_VSOCK_TYPE_STREAM, "STREAM" }) val 25 include/trace/events/vsock_virtio_transport_common.h #define show_op(val) \ val 26 include/trace/events/vsock_virtio_transport_common.h __print_symbolic(val, \ val 80 include/uapi/asm-generic/posix_types.h int val[2]; val 317 include/uapi/drm/drm_fourcc.h #define fourcc_mod_code(vendor, val) \ val 318 include/uapi/drm/drm_fourcc.h ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) val 544 include/uapi/drm/drm_fourcc.h #define fourcc_mod_broadcom_code(val, params) \ val 545 include/uapi/drm/drm_fourcc.h fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) val 1783 include/uapi/drm/i915_drm.h __u64 val; /* Return value */ val 156 include/uapi/drm/via_drm.h __u32 val; val 17 include/uapi/linux/atm_he.h unsigned addr, val; val 3593 include/uapi/linux/bpf.h __u32 val; val 100 include/uapi/linux/btf.h __s32 val; val 131 include/uapi/linux/btf.h #define BTF_MEMBER_BITFIELD_SIZE(val) ((val) >> 24) val 132 include/uapi/linux/btf.h #define BTF_MEMBER_BIT_OFFSET(val) ((val) & 0xffffff) val 615 include/uapi/linux/btrfs.h __u64 val[0]; /* out */ val 67 include/uapi/linux/connector.h __u32 val; val 174 include/uapi/linux/dvb/osd.h long val; val 24 include/uapi/linux/lirc.h #define LIRC_SPACE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_SPACE) val 25 include/uapi/linux/lirc.h #define LIRC_PULSE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_PULSE) val 26 include/uapi/linux/lirc.h #define LIRC_FREQUENCY(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_FREQUENCY) val 27 include/uapi/linux/lirc.h #define LIRC_TIMEOUT(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_TIMEOUT) val 29 include/uapi/linux/lirc.h #define LIRC_VALUE(val) ((val)&LIRC_VALUE_MASK) val 30 include/uapi/linux/lirc.h #define LIRC_MODE2(val) ((val)&LIRC_MODE2_MASK) val 32 include/uapi/linux/lirc.h #define LIRC_IS_SPACE(val) (LIRC_MODE2(val) == LIRC_MODE2_SPACE) val 33 include/uapi/linux/lirc.h #define LIRC_IS_PULSE(val) (LIRC_MODE2(val) == LIRC_MODE2_PULSE) val 34 include/uapi/linux/lirc.h #define LIRC_IS_FREQUENCY(val) (LIRC_MODE2(val) == LIRC_MODE2_FREQUENCY) val 35 include/uapi/linux/lirc.h #define LIRC_IS_TIMEOUT(val) (LIRC_MODE2(val) == LIRC_MODE2_TIMEOUT) val 35 include/uapi/linux/netfilter/nfnetlink_osf.h __u32 val; val 1051 include/uapi/linux/perf_event.h __u64 val; val 1066 include/uapi/linux/perf_event.h __u64 val; val 209 include/uapi/linux/pkt_cls.h __be32 val; val 229 include/uapi/linux/pkt_cls.h __u32 val; val 36 include/uapi/linux/ppdev.h unsigned char val; val 81 include/uapi/linux/seccomp.h __s64 val; val 44 include/uapi/linux/selinux_netlink.h __s32 val; val 48 include/uapi/linux/sem.h int val; /* value for SETVAL */ val 48 include/uapi/linux/swab.h static inline __attribute_const__ __u16 __fswab16(__u16 val) val 51 include/uapi/linux/swab.h return __arch_swab16(val); val 53 include/uapi/linux/swab.h return ___constant_swab16(val); val 57 include/uapi/linux/swab.h static inline __attribute_const__ __u32 __fswab32(__u32 val) val 60 include/uapi/linux/swab.h return __arch_swab32(val); val 62 include/uapi/linux/swab.h return ___constant_swab32(val); val 66 include/uapi/linux/swab.h static inline __attribute_const__ __u64 __fswab64(__u64 val) val 69 include/uapi/linux/swab.h return __arch_swab64(val); val 71 include/uapi/linux/swab.h __u32 h = val >> 32; val 72 include/uapi/linux/swab.h __u32 l = val & ((1ULL << 32) - 1); val 75 include/uapi/linux/swab.h return ___constant_swab64(val); val 79 include/uapi/linux/swab.h static inline __attribute_const__ __u32 __fswahw32(__u32 val) val 82 include/uapi/linux/swab.h return __arch_swahw32(val); val 84 include/uapi/linux/swab.h return ___constant_swahw32(val); val 88 include/uapi/linux/swab.h static inline __attribute_const__ __u32 __fswahb32(__u32 val) val 91 include/uapi/linux/swab.h return __arch_swahb32(val); val 93 include/uapi/linux/swab.h return ___constant_swahb32(val); val 54 include/uapi/linux/tc_act/tc_pedit.h __u32 val; /*XOR */ val 9 include/uapi/linux/tc_ematch/tc_em_cmp.h __u32 val; val 2375 include/uapi/linux/videodev2.h __u64 val; val 108 include/uapi/linux/virtio_balloon.h __virtio64 val; val 283 include/uapi/linux/wimax/i2400m.h __le32 val; val 927 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_eth_filter val; val 949 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_ipv4_filter val; val 967 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_tcp_udp_filter val; val 990 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_ipv6_filter val; val 1057 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_tunnel_filter val; val 1075 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_spec_esp_filter val; val 1102 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_gre_filter val; val 1125 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_mpls_filter val; val 14 include/uapi/rdma/rvt-abi.h #define RDMA_ATOMIC_UAPI(_type, _name) struct{ _type val; } _name val 816 include/uapi/sound/asound.h unsigned int val; val 49 include/video/broadsheetfb.h void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val); val 184 include/video/ili9320.h void (*reset)(unsigned int val); val 88 include/video/mbxfb.h __u32 val; /* value */ val 388 include/video/newport.h unsigned short val) val 392 include/video/newport.h regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8); val 207 include/video/vga.h static inline void vga_io_w (unsigned short port, unsigned char val) val 209 include/video/vga.h outb_p(val, port); val 213 include/video/vga.h unsigned char val) val 215 include/video/vga.h outw(VGA_OUT16VAL (val, reg), port); val 223 include/video/vga.h static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) val 225 include/video/vga.h writeb (val, regbase + port); val 229 include/video/vga.h unsigned char reg, unsigned char val) val 231 include/video/vga.h writew (VGA_OUT16VAL (val, reg), regbase + port); val 242 include/video/vga.h static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) val 245 include/video/vga.h vga_mm_w (regbase, port, val); val 247 include/video/vga.h vga_io_w (port, val); val 252 include/video/vga.h unsigned char reg, unsigned char val) val 255 include/video/vga.h vga_mm_w_fast (regbase, port, reg, val); val 257 include/video/vga.h vga_io_w_fast (port, reg, val); val 271 include/video/vga.h static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) val 274 include/video/vga.h vga_w_fast (regbase, VGA_CRT_IC, reg, val); val 277 include/video/vga.h vga_w (regbase, VGA_CRT_DC, val); val 287 include/video/vga.h static inline void vga_io_wcrt (unsigned char reg, unsigned char val) val 290 include/video/vga.h vga_io_w_fast (VGA_CRT_IC, reg, val); val 293 include/video/vga.h vga_io_w (VGA_CRT_DC, val); val 303 include/video/vga.h static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) val 306 include/video/vga.h vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val); val 309 include/video/vga.h vga_mm_w (regbase, VGA_CRT_DC, val); val 324 include/video/vga.h static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) val 327 include/video/vga.h vga_w_fast (regbase, VGA_SEQ_I, reg, val); val 330 include/video/vga.h vga_w (regbase, VGA_SEQ_D, val); val 340 include/video/vga.h static inline void vga_io_wseq (unsigned char reg, unsigned char val) val 343 include/video/vga.h vga_io_w_fast (VGA_SEQ_I, reg, val); val 346 include/video/vga.h vga_io_w (VGA_SEQ_D, val); val 356 include/video/vga.h static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) val 359 include/video/vga.h vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val); val 362 include/video/vga.h vga_mm_w (regbase, VGA_SEQ_D, val); val 376 include/video/vga.h static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) val 379 include/video/vga.h vga_w_fast (regbase, VGA_GFX_I, reg, val); val 382 include/video/vga.h vga_w (regbase, VGA_GFX_D, val); val 392 include/video/vga.h static inline void vga_io_wgfx (unsigned char reg, unsigned char val) val 395 include/video/vga.h vga_io_w_fast (VGA_GFX_I, reg, val); val 398 include/video/vga.h vga_io_w (VGA_GFX_D, val); val 408 include/video/vga.h static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) val 411 include/video/vga.h vga_mm_w_fast (regbase, VGA_GFX_I, reg, val); val 414 include/video/vga.h vga_mm_w (regbase, VGA_GFX_D, val); val 429 include/video/vga.h static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) val 432 include/video/vga.h vga_w (regbase, VGA_ATT_W, val); val 441 include/video/vga.h static inline void vga_io_wattr (unsigned char reg, unsigned char val) val 444 include/video/vga.h vga_io_w (VGA_ATT_W, val); val 453 include/video/vga.h static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) val 456 include/video/vga.h vga_mm_w (regbase, VGA_ATT_W, val); val 24 include/xen/arm/interface.h #define set_xen_guest_handle(hnd, val) \ val 28 include/xen/arm/interface.h (hnd).p = val; \ val 479 include/xen/interface/xen.h uint64_t val; /* New contents of PTE. */ val 36 include/xen/interface/xenpmu.h uint64_t val; val 249 init/main.c static int __init repair_env_string(char *param, char *val, val 252 init/main.c if (val) { val 254 init/main.c if (val == param+strlen(param)+1) val 255 init/main.c val[-1] = '='; val 256 init/main.c else if (val == param+strlen(param)+2) { val 257 init/main.c val[-2] = '='; val 258 init/main.c memmove(val-1, val, strlen(val)+1); val 259 init/main.c val--; val 267 init/main.c static int __init set_init_arg(char *param, char *val, val 275 init/main.c repair_env_string(param, val, unused, NULL); val 292 init/main.c static int __init unknown_bootoption(char *param, char *val, val 295 init/main.c repair_env_string(param, val, unused, NULL); val 302 init/main.c if (strchr(param, '.') && (!val || strchr(param, '.') < val)) val 308 init/main.c if (val) { val 316 init/main.c if (!strncmp(param, envp_init[i], val - param)) val 455 init/main.c static int __init do_early_param(char *param, char *val, val 465 init/main.c if (p->setup_func(val) != 0) val 1325 ipc/sem.c int val) val 1333 ipc/sem.c if (val > SEMVMX || val < 0) val 1375 ipc/sem.c curr->semval = val; val 1666 ipc/sem.c int val; val 1669 ipc/sem.c val = arg >> 32; val 1672 ipc/sem.c val = arg; val 1674 ipc/sem.c return semctl_setval(ns, semid, semnum, val); val 221 kernel/auditfilter.c switch(audit_classify_arch(arch->val)) { val 414 kernel/auditfilter.c if ((f->val != 0) && (f->val != 1)) val 418 kernel/auditfilter.c if (f->val & ~15) val 422 kernel/auditfilter.c if (f->val & ~S_IFMT) val 426 kernel/auditfilter.c if (f->val > AUDIT_MAX_FIELD_COMPARE) val 430 kernel/auditfilter.c if (f->val >= AF_MAX) val 503 kernel/auditfilter.c f->val = f_val; val 560 kernel/auditfilter.c f->val = f_val; val 594 kernel/auditfilter.c f->val = f_val; val 679 kernel/auditfilter.c if (krule->pflags & AUDIT_LOGINUID_LEGACY && !f->val) { val 686 kernel/auditfilter.c data->values[i] = f->val; val 765 kernel/auditfilter.c if (a->fields[i].val != b->fields[i].val) val 899 kernel/auditfilter.c h = audit_hash_ino(entry->rule.inode_f->val); val 1339 kernel/auditfilter.c result = audit_comparator(pid, f->op, f->val); val 1353 kernel/auditfilter.c f->op, f->val); val 1356 kernel/auditfilter.c result = audit_comparator(msgtype, f->op, f->val); val 176 kernel/auditsc.c static int audit_match_filetype(struct audit_context *ctx, int val) val 179 kernel/auditsc.c umode_t mode = (umode_t)val; val 360 kernel/auditsc.c switch (f->val) { val 461 kernel/auditsc.c result = audit_comparator(pid, f->op, f->val); val 467 kernel/auditsc.c result = audit_comparator(ctx->ppid, f->op, f->val); val 515 kernel/auditsc.c result = audit_comparator(sessionid, f->op, f->val); val 518 kernel/auditsc.c result = audit_comparator(tsk->personality, f->op, f->val); val 522 kernel/auditsc.c result = audit_comparator(ctx->arch, f->op, f->val); val 527 kernel/auditsc.c result = audit_comparator(ctx->return_code, f->op, f->val); val 531 kernel/auditsc.c if (f->val) val 539 kernel/auditsc.c if (audit_comparator(MAJOR(name->dev), f->op, f->val) || val 540 kernel/auditsc.c audit_comparator(MAJOR(name->rdev), f->op, f->val)) val 544 kernel/auditsc.c if (audit_comparator(MAJOR(n->dev), f->op, f->val) || val 545 kernel/auditsc.c audit_comparator(MAJOR(n->rdev), f->op, f->val)) { val 554 kernel/auditsc.c if (audit_comparator(MINOR(name->dev), f->op, f->val) || val 555 kernel/auditsc.c audit_comparator(MINOR(name->rdev), f->op, f->val)) val 559 kernel/auditsc.c if (audit_comparator(MINOR(n->dev), f->op, f->val) || val 560 kernel/auditsc.c audit_comparator(MINOR(n->rdev), f->op, f->val)) { val 569 kernel/auditsc.c result = audit_comparator(name->ino, f->op, f->val); val 572 kernel/auditsc.c if (audit_comparator(n->ino, f->op, f->val)) { val 624 kernel/auditsc.c result = audit_comparator(audit_loginuid_set(tsk), f->op, f->val); val 629 kernel/auditsc.c f->op, f->val); val 692 kernel/auditsc.c result = audit_comparator(ctx->argv[f->type-AUDIT_ARG0], f->op, f->val); val 699 kernel/auditsc.c result = audit_match_perm(ctx, f->val); val 704 kernel/auditsc.c result = audit_match_filetype(ctx, f->val); val 759 kernel/auditsc.c static int audit_in_mask(const struct audit_krule *rule, unsigned long val) val 763 kernel/auditsc.c if (val > 0xffffffff) val 766 kernel/auditsc.c word = AUDIT_WORD(val); val 770 kernel/auditsc.c bit = AUDIT_BIT(val); val 1965 kernel/auditsc.c f->op, f->val) val 2083 kernel/auditsc.c f->op, f->val) val 2529 kernel/auditsc.c const struct audit_ntp_val *val = &ad->vals[type]; val 2531 kernel/auditsc.c if (val->newval == val->oldval) val 2535 kernel/auditsc.c "op=%s old=%lli new=%lli", op, val->oldval, val->newval); val 277 kernel/bpf/arraymap.c char *val; val 299 kernel/bpf/arraymap.c val = array->value + val 302 kernel/bpf/arraymap.c copy_map_value_locked(map, val, value, false); val 304 kernel/bpf/arraymap.c copy_map_value(map, val, value); val 2411 kernel/bpf/btf.c enums[i].val); val 2432 kernel/bpf/btf.c if (v == enums[i].val) { val 595 kernel/bpf/core.c unsigned long val = (unsigned long)key; val 602 kernel/bpf/core.c if (val < symbol_start) val 604 kernel/bpf/core.c if (val >= symbol_end) val 225 kernel/bpf/helpers.c __u32 val; val 229 kernel/bpf/helpers.c compiletime_assert(u.val == 0, "__ARCH_SPIN_LOCK_UNLOCKED not 0"); val 68 kernel/bpf/syscall.c unsigned char val; val 84 kernel/bpf/syscall.c err = get_user(val, addr); val 87 kernel/bpf/syscall.c if (val) val 3147 kernel/bpf/verifier.c u64 val = reg->var_off.value; val 3180 kernel/bpf/verifier.c if (map->spin_lock_off != val + reg->off) { val 3182 kernel/bpf/verifier.c val + reg->off); val 4202 kernel/bpf/verifier.c s64 val = reg->var_off.value; val 4205 kernel/bpf/verifier.c if (known && (val >= BPF_MAX_VAR_OFF || val <= -BPF_MAX_VAR_OFF)) { val 4207 kernel/bpf/verifier.c reg_type_str[type], val); val 5226 kernel/bpf/verifier.c static int is_branch_taken(struct bpf_reg_state *reg, u64 val, u8 opcode, val 5264 kernel/bpf/verifier.c val = (u32)val; val 5265 kernel/bpf/verifier.c sval = (s64)(s32)val; val 5267 kernel/bpf/verifier.c sval = (s64)val; val 5273 kernel/bpf/verifier.c return !!tnum_equals_const(reg->var_off, val); val 5277 kernel/bpf/verifier.c return !tnum_equals_const(reg->var_off, val); val 5280 kernel/bpf/verifier.c if ((~reg->var_off.mask & reg->var_off.value) & val) val 5282 kernel/bpf/verifier.c if (!((reg->var_off.mask | reg->var_off.value) & val)) val 5286 kernel/bpf/verifier.c if (reg->umin_value > val) val 5288 kernel/bpf/verifier.c else if (reg->umax_value <= val) val 5298 kernel/bpf/verifier.c if (reg->umax_value < val) val 5300 kernel/bpf/verifier.c else if (reg->umin_value >= val) val 5310 kernel/bpf/verifier.c if (reg->umin_value >= val) val 5312 kernel/bpf/verifier.c else if (reg->umax_value < val) val 5322 kernel/bpf/verifier.c if (reg->umax_value <= val) val 5324 kernel/bpf/verifier.c else if (reg->umin_value > val) val 5431 kernel/bpf/verifier.c struct bpf_reg_state *false_reg, u64 val, val 5445 kernel/bpf/verifier.c val = is_jmp32 ? (u32)val : val; val 5446 kernel/bpf/verifier.c sval = is_jmp32 ? (s64)(s32)val : (s64)val; val 5463 kernel/bpf/verifier.c reg->var_off.value = (old_v & hi_mask) | val; val 5466 kernel/bpf/verifier.c __mark_reg_known(reg, val); val 5472 kernel/bpf/verifier.c tnum_const(~val)); val 5473 kernel/bpf/verifier.c if (is_power_of_2(val)) val 5475 kernel/bpf/verifier.c tnum_const(val)); val 5480 kernel/bpf/verifier.c set_upper_bound(false_reg, val, is_jmp32, opcode == BPF_JGE); val 5481 kernel/bpf/verifier.c set_lower_bound(true_reg, val, is_jmp32, opcode == BPF_JGT); val 5502 kernel/bpf/verifier.c set_lower_bound(false_reg, val, is_jmp32, opcode == BPF_JLE); val 5503 kernel/bpf/verifier.c set_upper_bound(true_reg, val, is_jmp32, opcode == BPF_JLT); val 5539 kernel/bpf/verifier.c struct bpf_reg_state *false_reg, u64 val, val 5547 kernel/bpf/verifier.c val = is_jmp32 ? (u32)val : val; val 5548 kernel/bpf/verifier.c sval = is_jmp32 ? (s64)(s32)val : (s64)val; val 5561 kernel/bpf/verifier.c reg->var_off.value = (old_v & hi_mask) | val; val 5564 kernel/bpf/verifier.c __mark_reg_known(reg, val); val 5570 kernel/bpf/verifier.c tnum_const(~val)); val 5571 kernel/bpf/verifier.c if (is_power_of_2(val)) val 5573 kernel/bpf/verifier.c tnum_const(val)); val 5578 kernel/bpf/verifier.c set_lower_bound(false_reg, val, is_jmp32, opcode == BPF_JGE); val 5579 kernel/bpf/verifier.c set_upper_bound(true_reg, val, is_jmp32, opcode == BPF_JGT); val 5597 kernel/bpf/verifier.c set_upper_bound(false_reg, val, is_jmp32, opcode == BPF_JLE); val 5598 kernel/bpf/verifier.c set_lower_bound(true_reg, val, is_jmp32, opcode == BPF_JLT); val 587 kernel/cgroup/cgroup-v1.c struct cftype *cft, u64 val) val 589 kernel/cgroup/cgroup-v1.c if (val) val 603 kernel/cgroup/cgroup-v1.c struct cftype *cft, u64 val) val 605 kernel/cgroup/cgroup-v1.c if (val) val 6386 kernel/cgroup/cgroup.c if (skcd->val) { val 6408 kernel/cgroup/cgroup.c skcd->val = (unsigned long)cset->dfl_cgrp; val 76 kernel/cgroup/cpuset.c int val; /* most recent output value */ val 1827 kernel/cgroup/cpuset.c static int update_relax_domain_level(struct cpuset *cs, s64 val) val 1830 kernel/cgroup/cpuset.c if (val < -1 || val >= sched_domain_level_max) val 1834 kernel/cgroup/cpuset.c if (val != cs->relax_domain_level) { val 1835 kernel/cgroup/cpuset.c cs->relax_domain_level = val; val 1920 kernel/cgroup/cpuset.c static int update_prstate(struct cpuset *cs, int val) val 1926 kernel/cgroup/cpuset.c if ((val != 0) && (val != 1)) val 1928 kernel/cgroup/cpuset.c if (val == cs->partition_root_state) val 1935 kernel/cgroup/cpuset.c if (val && cs->partition_root_state) val 2055 kernel/cgroup/cpuset.c fmp->val = 0; val 2074 kernel/cgroup/cpuset.c fmp->val = (FM_COEF * fmp->val) / FM_SCALE; val 2077 kernel/cgroup/cpuset.c fmp->val += ((FM_SCALE - FM_COEF) * fmp->cnt) / FM_SCALE; val 2093 kernel/cgroup/cpuset.c int val; val 2097 kernel/cgroup/cpuset.c val = fmp->val; val 2099 kernel/cgroup/cpuset.c return val; val 2254 kernel/cgroup/cpuset.c u64 val) val 2269 kernel/cgroup/cpuset.c retval = update_flag(CS_CPU_EXCLUSIVE, cs, val); val 2272 kernel/cgroup/cpuset.c retval = update_flag(CS_MEM_EXCLUSIVE, cs, val); val 2275 kernel/cgroup/cpuset.c retval = update_flag(CS_MEM_HARDWALL, cs, val); val 2278 kernel/cgroup/cpuset.c retval = update_flag(CS_SCHED_LOAD_BALANCE, cs, val); val 2281 kernel/cgroup/cpuset.c retval = update_flag(CS_MEMORY_MIGRATE, cs, val); val 2284 kernel/cgroup/cpuset.c cpuset_memory_pressure_enabled = !!val; val 2287 kernel/cgroup/cpuset.c retval = update_flag(CS_SPREAD_PAGE, cs, val); val 2290 kernel/cgroup/cpuset.c retval = update_flag(CS_SPREAD_SLAB, cs, val); val 2303 kernel/cgroup/cpuset.c s64 val) val 2316 kernel/cgroup/cpuset.c retval = update_relax_domain_level(cs, val); val 2504 kernel/cgroup/cpuset.c int val; val 2513 kernel/cgroup/cpuset.c val = PRS_ENABLED; val 2515 kernel/cgroup/cpuset.c val = PRS_DISABLED; val 2525 kernel/cgroup/cpuset.c retval = update_prstate(cs, val); val 792 kernel/debug/debug_core.c static int module_event(struct notifier_block *self, unsigned long val, val 318 kernel/debug/kdb/kdb_main.c unsigned long val; val 321 kernel/debug/kdb/kdb_main.c diag = kdbgetulenv(match, &val); val 323 kernel/debug/kdb/kdb_main.c *value = (int) val; val 340 kernel/debug/kdb/kdb_main.c unsigned long val; val 342 kernel/debug/kdb/kdb_main.c val = simple_strtoul(arg, &endp, 0); val 349 kernel/debug/kdb/kdb_main.c val = simple_strtoul(arg, &endp, 16); val 354 kernel/debug/kdb/kdb_main.c *value = val; val 362 kernel/debug/kdb/kdb_main.c u64 val; val 364 kernel/debug/kdb/kdb_main.c val = simple_strtoull(arg, &endp, 0); val 368 kernel/debug/kdb/kdb_main.c val = simple_strtoull(arg, &endp, 16); val 373 kernel/debug/kdb/kdb_main.c *value = val; val 1621 kernel/debug/kdb/kdb_main.c unsigned long val; val 1631 kernel/debug/kdb/kdb_main.c diag = kdbgetularg(argv[nextarg], &val); val 1633 kernel/debug/kdb/kdb_main.c mdcount = (int) val; val 1641 kernel/debug/kdb/kdb_main.c diag = kdbgetularg(argv[nextarg+1], &val); val 1643 kernel/debug/kdb/kdb_main.c radix = (int) val; val 2188 kernel/debug/kdb/kdb_main.c static int kdb_param_enable_nmi(const char *val, const struct kernel_param *kp) val 2386 kernel/debug/kdb/kdb_main.c unsigned long val; val 2396 kernel/debug/kdb/kdb_main.c diag = kdbgetularg(argv[1], &val); val 2400 kernel/debug/kdb/kdb_main.c p = find_task_by_pid_ns((pid_t)val, &init_pid_ns); val 2402 kernel/debug/kdb/kdb_main.c kdb_printf("No task with pid=%d\n", (pid_t)val); val 2492 kernel/debug/kdb/kdb_main.c static void kdb_sysinfo(struct sysinfo *val) val 2496 kernel/debug/kdb/kdb_main.c memset(val, 0, sizeof(*val)); val 2497 kernel/debug/kdb/kdb_main.c val->uptime = div_u64(uptime, NSEC_PER_SEC); val 2498 kernel/debug/kdb/kdb_main.c val->loads[0] = avenrun[0]; val 2499 kernel/debug/kdb/kdb_main.c val->loads[1] = avenrun[1]; val 2500 kernel/debug/kdb/kdb_main.c val->loads[2] = avenrun[2]; val 2501 kernel/debug/kdb/kdb_main.c val->procs = nr_threads-1; val 2502 kernel/debug/kdb/kdb_main.c si_meminfo(val); val 2514 kernel/debug/kdb/kdb_main.c struct sysinfo val; val 2534 kernel/debug/kdb/kdb_main.c kdb_sysinfo(&val); val 2536 kernel/debug/kdb/kdb_main.c if (val.uptime > (24*60*60)) { val 2537 kernel/debug/kdb/kdb_main.c int days = val.uptime / (24*60*60); val 2538 kernel/debug/kdb/kdb_main.c val.uptime %= (24*60*60); val 2541 kernel/debug/kdb/kdb_main.c kdb_printf("%02ld:%02ld\n", val.uptime/(60*60), (val.uptime/60)%60); val 2544 kernel/debug/kdb/kdb_main.c LOAD_INT(val.loads[0]), LOAD_FRAC(val.loads[0]), val 2545 kernel/debug/kdb/kdb_main.c LOAD_INT(val.loads[1]), LOAD_FRAC(val.loads[1]), val 2546 kernel/debug/kdb/kdb_main.c LOAD_INT(val.loads[2]), LOAD_FRAC(val.loads[2])); val 2552 kernel/debug/kdb/kdb_main.c K(val.totalram), K(val.freeram), K(val.bufferram)); val 2563 kernel/debug/kdb/kdb_main.c unsigned long addr, symaddr, val, bytesperword = 0, whichcpu = ~0UL; val 2611 kernel/debug/kdb/kdb_main.c diag = kdb_getword(&val, addr, bytesperword); val 210 kernel/debug/kdb/kdb_private.h extern void kdb_print_nameval(const char *name, unsigned long val); val 674 kernel/debug/kdb/kdb_support.c void kdb_print_nameval(const char *name, unsigned long val) val 678 kernel/debug/kdb/kdb_support.c if (kdbnearsym(val, &symtab)) val 679 kernel/debug/kdb/kdb_support.c kdb_symbol_print(val, &symtab, val 682 kernel/debug/kdb/kdb_support.c kdb_printf("0x%lx\n", val); val 186 kernel/dma/remap.c unsigned long val; val 194 kernel/dma/remap.c val = gen_pool_alloc(atomic_pool, size); val 195 kernel/dma/remap.c if (val) { val 196 kernel/dma/remap.c phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); val 199 kernel/dma/remap.c ptr = (void *)val; val 52 kernel/dma/swiotlb.c #define OFFSET(val,align) ((unsigned long) \ val 53 kernel/dma/swiotlb.c ( (val) & ( (align) - 1))) val 146 kernel/dma/swiotlb.c void swiotlb_set_max_segment(unsigned int val) val 151 kernel/dma/swiotlb.c max_segment = rounddown(val, PAGE_SIZE); val 1753 kernel/events/core.c size += sizeof(data->data_src.val); val 6061 kernel/events/core.c u64 val; val 6063 kernel/events/core.c val = perf_reg_value(regs, bit); val 6064 kernel/events/core.c perf_output_put(handle, val); val 6484 kernel/events/core.c perf_output_put(handle, data->data_src.val); val 8255 kernel/events/core.c s64 old, val; val 8260 kernel/events/core.c old = val = local64_read(&hwc->period_left); val 8261 kernel/events/core.c if (val < 0) val 8264 kernel/events/core.c nr = div64_u64(period + val, period); val 8266 kernel/events/core.c val -= offset; val 8267 kernel/events/core.c if (local64_cmpxchg(&hwc->period_left, old, val) != old) val 8365 kernel/events/core.c u64 val = event_id | (type << 32); val 8367 kernel/events/core.c return hash_64(val, SWEVENT_HLIST_BITS); val 12213 kernel/events/core.c perf_reboot(struct notifier_block *notifier, unsigned long val, void *v) val 107 kernel/fail_function.c static int fei_retval_set(void *data, u64 val) val 110 kernel/fail_function.c unsigned long retv = (unsigned long)val; val 126 kernel/fail_function.c val) != retv) val 130 kernel/fail_function.c attr->retval = val; val 137 kernel/fail_function.c static int fei_retval_get(void *data, u64 *val) val 147 kernel/fail_function.c *val = attr->retval; val 2743 kernel/futex.c static int futex_wait_setup(u32 __user *uaddr, u32 val, unsigned int flags, val 2791 kernel/futex.c if (uval != val) { val 2802 kernel/futex.c static int futex_wait(u32 __user *uaddr, unsigned int flags, u32 val, val 2822 kernel/futex.c ret = futex_wait_setup(uaddr, val, flags, &q, &hb); val 2852 kernel/futex.c restart->futex.val = val; val 2880 kernel/futex.c restart->futex.val, tp, restart->futex.bitset); val 3312 kernel/futex.c u32 val, ktime_t *abs_time, u32 bitset, val 3353 kernel/futex.c ret = futex_wait_setup(uaddr, val, flags, &q, &hb); val 3867 kernel/futex.c long do_futex(u32 __user *uaddr, int op, u32 val, ktime_t *timeout, val 3898 kernel/futex.c return futex_wait(uaddr, flags, val, timeout, val3); val 3903 kernel/futex.c return futex_wake(uaddr, flags, val, val3); val 3905 kernel/futex.c return futex_requeue(uaddr, flags, uaddr2, val, val2, NULL, 0); val 3907 kernel/futex.c return futex_requeue(uaddr, flags, uaddr2, val, val2, &val3, 0); val 3909 kernel/futex.c return futex_wake_op(uaddr, flags, uaddr2, val, val2, val3); val 3918 kernel/futex.c return futex_wait_requeue_pi(uaddr, flags, val, timeout, val3, val 3921 kernel/futex.c return futex_requeue(uaddr, flags, uaddr2, val, val2, &val3, 1); val 3927 kernel/futex.c SYSCALL_DEFINE6(futex, u32 __user *, uaddr, int, op, u32, val, val 3959 kernel/futex.c return do_futex(uaddr, op, val, tp, uaddr2, val2, val3); val 4121 kernel/futex.c SYSCALL_DEFINE6(futex_time32, u32 __user *, uaddr, int, op, u32, val, val 4147 kernel/futex.c return do_futex(uaddr, op, val, tp, uaddr2, val2, val3); val 75 kernel/gcov/fs.c unsigned long val; val 77 kernel/gcov/fs.c if (kstrtoul(str, 0, &val)) { val 81 kernel/gcov/fs.c gcov_persist = val; val 117 kernel/irq/autoprobe.c unsigned int probe_irq_mask(unsigned long val) val 136 kernel/irq/autoprobe.c return mask & val; val 157 kernel/irq/autoprobe.c int probe_irq_off(unsigned long val) val 209 kernel/irq/generic-chip.c static void irq_writel_be(u32 val, void __iomem *addr) val 211 kernel/irq/generic-chip.c iowrite32be(val, addr); val 2681 kernel/irq/manage.c bool val) val 2707 kernel/irq/manage.c err = chip->irq_set_irqchip_state(data, which, val); val 222 kernel/jump_label.c int val; val 224 kernel/jump_label.c val = atomic_fetch_add_unless(&key->enabled, -1, 1); val 225 kernel/jump_label.c if (val == 1) val 235 kernel/jump_label.c WARN(val < 0, "jump label: negative count!\n"); val 719 kernel/jump_label.c jump_label_module_notify(struct notifier_block *self, unsigned long val, val 728 kernel/jump_label.c switch (val) { val 201 kernel/kcov.c void notrace __sanitizer_cov_trace_switch(u64 val, u64 *cases) val 225 kernel/kcov.c write_comp_data(type, cases[i + 2], val, _RET_IP_); val 1837 kernel/kprobes.c unsigned long val, void *data) val 2220 kernel/kprobes.c unsigned long val, void *data) val 2226 kernel/kprobes.c int checkcore = (val == MODULE_STATE_GOING); val 2228 kernel/kprobes.c if (val != MODULE_STATE_GOING && val != MODULE_STATE_LIVE) val 378 kernel/livepatch/core.c bool val; val 380 kernel/livepatch/core.c ret = kstrtobool(buf, &val); val 384 kernel/livepatch/core.c if (!val) val 4340 kernel/locking/lockdep.c cookie.val = 1 + (prandom_u32() >> 16); val 4341 kernel/locking/lockdep.c hlock->pin_count += cookie.val; val 4362 kernel/locking/lockdep.c hlock->pin_count += cookie.val; val 4385 kernel/locking/lockdep.c hlock->pin_count -= cookie.val; val 195 kernel/locking/qspinlock.c atomic_andnot(_Q_PENDING_VAL, &lock->val); val 206 kernel/locking/qspinlock.c atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val); val 221 kernel/locking/qspinlock.c u32 old, new, val = atomic_read(&lock->val); val 224 kernel/locking/qspinlock.c new = (val & _Q_LOCKED_PENDING_MASK) | tail; val 230 kernel/locking/qspinlock.c old = atomic_cmpxchg_relaxed(&lock->val, val, new); val 231 kernel/locking/qspinlock.c if (old == val) val 234 kernel/locking/qspinlock.c val = old; val 250 kernel/locking/qspinlock.c return atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val); val 314 kernel/locking/qspinlock.c void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) val 334 kernel/locking/qspinlock.c if (val == _Q_PENDING_VAL) { val 336 kernel/locking/qspinlock.c val = atomic_cond_read_relaxed(&lock->val, val 343 kernel/locking/qspinlock.c if (val & ~_Q_LOCKED_MASK) val 351 kernel/locking/qspinlock.c val = queued_fetch_set_pending_acquire(lock); val 360 kernel/locking/qspinlock.c if (unlikely(val & ~_Q_LOCKED_MASK)) { val 363 kernel/locking/qspinlock.c if (!(val & _Q_PENDING_MASK)) val 380 kernel/locking/qspinlock.c if (val & _Q_LOCKED_MASK) val 381 kernel/locking/qspinlock.c atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_MASK)); val 507 kernel/locking/qspinlock.c if ((val = pv_wait_head_or_lock(lock, node))) val 510 kernel/locking/qspinlock.c val = atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK)); val 534 kernel/locking/qspinlock.c if ((val & _Q_TAIL_MASK) == tail) { val 535 kernel/locking/qspinlock.c if (atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL)) val 88 kernel/locking/qspinlock_paravirt.h int val = atomic_read(&lock->val); val 90 kernel/locking/qspinlock_paravirt.h if (!(val & _Q_LOCKED_PENDING_MASK) && val 95 kernel/locking/qspinlock_paravirt.h if (!(val & _Q_TAIL_MASK) || (val & _Q_PENDING_MASK)) val 128 kernel/locking/qspinlock_paravirt.h atomic_or(_Q_PENDING_VAL, &lock->val); val 133 kernel/locking/qspinlock_paravirt.h int val = atomic_read(&lock->val); val 138 kernel/locking/qspinlock_paravirt.h if (val & _Q_LOCKED_MASK) val 144 kernel/locking/qspinlock_paravirt.h old = val; val 145 kernel/locking/qspinlock_paravirt.h new = (val & ~_Q_PENDING_MASK) | _Q_LOCKED_VAL; val 146 kernel/locking/qspinlock_paravirt.h val = atomic_cmpxchg_acquire(&lock->val, old, new); val 148 kernel/locking/qspinlock_paravirt.h if (val == old) val 485 kernel/locking/qspinlock_paravirt.h return (u32)(atomic_read(&lock->val) | _Q_LOCKED_VAL); val 500 kernel/locking/qspinlock_paravirt.h (unsigned long)lock, atomic_read(&lock->val)); val 120 kernel/locking/qspinlock_stat.h static inline void __pv_wait(u8 *ptr, u8 val) val 125 kernel/locking/qspinlock_stat.h pv_wait(ptr, val); val 55 kernel/locking/rtmutex.c unsigned long val = (unsigned long)owner; val 58 kernel/locking/rtmutex.c val |= RT_MUTEX_HAS_WAITERS; val 60 kernel/locking/rtmutex.c lock->owner = (struct task_struct *)val; val 206 kernel/locking/rwsem.c unsigned long val = (unsigned long)owner | RWSEM_READER_OWNED | val 209 kernel/locking/rwsem.c atomic_long_set(&sem->owner, val); val 243 kernel/locking/rwsem.c unsigned long val = atomic_long_read(&sem->owner); val 245 kernel/locking/rwsem.c while ((val & ~RWSEM_OWNER_FLAGS_MASK) == (unsigned long)current) { val 246 kernel/locking/rwsem.c if (atomic_long_try_cmpxchg(&sem->owner, &val, val 247 kernel/locking/rwsem.c val & RWSEM_OWNER_FLAGS_MASK)) val 128 kernel/module.c unsigned long val = (unsigned long)key; val 132 kernel/module.c if (val < start) val 136 kernel/module.c if (val >= end) val 3765 kernel/module.c static int unknown_module_param_cb(char *param, char *val, const char *modname, val 3777 kernel/module.c ret = ddebug_dyndbg_module_param_cb(param, val, modname); val 77 kernel/notifier.c unsigned long val, void *v, val 95 kernel/notifier.c ret = nb->notifier_call(nb, val, v); val 179 kernel/notifier.c unsigned long val, void *v, val 185 kernel/notifier.c ret = notifier_call_chain(&nh->head, val, v, nr_to_call, nr_calls); val 193 kernel/notifier.c unsigned long val, void *v) val 195 kernel/notifier.c return __atomic_notifier_call_chain(nh, val, v, -1, NULL); val 307 kernel/notifier.c unsigned long val, void *v, val 319 kernel/notifier.c ret = notifier_call_chain(&nh->head, val, v, nr_to_call, val 328 kernel/notifier.c unsigned long val, void *v) val 330 kernel/notifier.c return __blocking_notifier_call_chain(nh, val, v, -1, NULL); val 393 kernel/notifier.c unsigned long val, void *v, val 396 kernel/notifier.c return notifier_call_chain(&nh->head, val, v, nr_to_call, nr_calls); val 401 kernel/notifier.c unsigned long val, void *v) val 403 kernel/notifier.c return __raw_notifier_call_chain(nh, val, v, -1, NULL); val 493 kernel/notifier.c unsigned long val, void *v, val 500 kernel/notifier.c ret = notifier_call_chain(&nh->head, val, v, nr_to_call, nr_calls); val 507 kernel/notifier.c unsigned long val, void *v) val 509 kernel/notifier.c return __srcu_notifier_call_chain(nh, val, v, -1, NULL); val 538 kernel/notifier.c int notrace notify_die(enum die_val val, const char *str, val 551 kernel/notifier.c return atomic_notifier_call_chain(&die_chain, val, &args); val 638 kernel/panic.c static int clear_warn_once_set(void *data, u64 val) val 41 kernel/params.c char val[]; val 58 kernel/params.c return p->val; val 68 kernel/params.c if (p->val == param) { val 116 kernel/params.c char *val, val 123 kernel/params.c int (*handle_unknown)(char *param, char *val, val 136 kernel/params.c if (!val && val 143 kernel/params.c err = params[i].ops->set(val, ¶ms[i]); val 152 kernel/params.c pr_debug("doing %s: %s='%s'\n", doing, param, val); val 153 kernel/params.c return handle_unknown(param, val, doing, arg); val 168 kernel/params.c int (*unknown)(char *param, char *val, val 171 kernel/params.c char *param, *val, *err = NULL; val 183 kernel/params.c args = next_arg(args, ¶m, &val); val 185 kernel/params.c if (!val && strcmp(param, "--") == 0) val 188 kernel/params.c ret = parse_one(param, val, doing, params, num, val 202 kernel/params.c doing, val ?: "", param); val 206 kernel/params.c doing, val ?: "", param); val 218 kernel/params.c int param_set_##name(const char *val, const struct kernel_param *kp) \ val 220 kernel/params.c return strtolfn(val, 0, (type *)kp->arg); \ val 245 kernel/params.c int param_set_charp(const char *val, const struct kernel_param *kp) val 247 kernel/params.c if (strlen(val) > 1024) { val 257 kernel/params.c *(char **)kp->arg = kmalloc_parameter(strlen(val)+1); val 260 kernel/params.c strcpy(*(char **)kp->arg, val); val 262 kernel/params.c *(const char **)kp->arg = val; val 288 kernel/params.c int param_set_bool(const char *val, const struct kernel_param *kp) val 291 kernel/params.c if (!val) val = "1"; val 294 kernel/params.c return strtobool(val, kp->arg); val 312 kernel/params.c int param_set_bool_enable_only(const char *val, const struct kernel_param *kp) val 321 kernel/params.c err = param_set_bool(val, &dummy_kp); val 330 kernel/params.c err = param_set_bool(val, kp); val 344 kernel/params.c int param_set_invbool(const char *val, const struct kernel_param *kp) val 351 kernel/params.c ret = param_set_bool(val, &dummy); val 370 kernel/params.c int param_set_bint(const char *val, const struct kernel_param *kp) val 379 kernel/params.c ret = param_set_bool(val, &boolkp); val 396 kernel/params.c const char *val, val 421 kernel/params.c len = strcspn(val, ","); val 424 kernel/params.c save = val[len]; val 425 kernel/params.c ((char *)val)[len] = '\0'; val 427 kernel/params.c ret = set(val, &kp); val 432 kernel/params.c val += len+1; val 443 kernel/params.c static int param_array_set(const char *val, const struct kernel_param *kp) val 448 kernel/params.c return param_array(kp->mod, kp->name, val, 1, arr->max, arr->elem, val 491 kernel/params.c int param_set_copystring(const char *val, const struct kernel_param *kp) val 495 kernel/params.c if (strlen(val)+1 > kps->maxlen) { val 500 kernel/params.c strcpy(kps->string, val); val 83 kernel/power/main.c int __pm_notifier_call_chain(unsigned long val, int nr_to_call, int *nr_calls) val 87 kernel/power/main.c ret = __blocking_notifier_call_chain(&pm_chain_head, val, NULL, val 92 kernel/power/main.c int pm_notifier_call_chain(unsigned long val) val 94 kernel/power/main.c return __pm_notifier_call_chain(val, -1, NULL); val 109 kernel/power/main.c unsigned long val; val 111 kernel/power/main.c if (kstrtoul(buf, 10, &val)) val 114 kernel/power/main.c if (val > 1) val 117 kernel/power/main.c pm_async_enabled = val; val 452 kernel/power/main.c unsigned long val; val 454 kernel/power/main.c if (kstrtoul(buf, 10, &val)) val 457 kernel/power/main.c if (val > 1) val 460 kernel/power/main.c pm_print_times_enabled = !!val; val 492 kernel/power/main.c unsigned long val; val 494 kernel/power/main.c if (kstrtoul(buf, 10, &val)) val 497 kernel/power/main.c if (val > 1) val 500 kernel/power/main.c pm_debug_messages_on = !!val; val 666 kernel/power/main.c unsigned int val; val 668 kernel/power/main.c return pm_get_wakeup_count(&val, true) ? val 669 kernel/power/main.c sprintf(buf, "%u\n", val) : -EINTR; val 676 kernel/power/main.c unsigned int val; val 689 kernel/power/main.c if (sscanf(buf, "%u", &val) == 1) { val 690 kernel/power/main.c if (pm_save_wakeup_count(val)) val 797 kernel/power/main.c int val; val 799 kernel/power/main.c if (sscanf(buf, "%d", &val) == 1) { val 800 kernel/power/main.c pm_trace_enabled = !!val; val 834 kernel/power/main.c unsigned long val; val 836 kernel/power/main.c if (kstrtoul(buf, 10, &val)) val 839 kernel/power/main.c freeze_timeout_msecs = val; val 213 kernel/power/power.h extern int __pm_notifier_call_chain(unsigned long val, int nr_to_call, val 215 kernel/power/power.h extern int pm_notifier_call_chain(unsigned long val); val 275 kernel/power/qos.c s32 val = 0; val 279 kernel/power/qos.c val |= req->flags; val 281 kernel/power/qos.c pqf->effective_flags = val; val 297 kernel/power/qos.c enum pm_qos_req_action action, s32 val) val 314 kernel/power/qos.c req->flags = val; val 317 kernel/power/qos.c pqf->effective_flags |= val; val 1345 kernel/rcu/srcutree.c unsigned long val, void *data) val 1350 kernel/rcu/srcutree.c switch (val) { val 460 kernel/rcu/tree.c static int param_set_first_fqs_jiffies(const char *val, const struct kernel_param *kp) val 463 kernel/rcu/tree.c int ret = kstrtoul(val, 0, &j); val 472 kernel/rcu/tree.c static int param_set_next_fqs_jiffies(const char *val, const struct kernel_param *kp) val 475 kernel/rcu/tree.c int ret = kstrtoul(val, 0, &j); val 302 kernel/sched/clock.c u64 *ptr, old_val, val; val 344 kernel/sched/clock.c val = this_clock; val 351 kernel/sched/clock.c val = remote_clock; val 354 kernel/sched/clock.c if (cmpxchg64(ptr, old_val, val) != old_val) val 357 kernel/sched/clock.c return val; val 383 kernel/sched/core.c typeof(ti->flags) old, val = READ_ONCE(ti->flags); val 386 kernel/sched/core.c if (!(val & _TIF_POLLING_NRFLAG)) val 388 kernel/sched/core.c if (val & _TIF_NEED_RESCHED) val 390 kernel/sched/core.c old = cmpxchg(&ti->flags, val, val | _TIF_NEED_RESCHED); val 391 kernel/sched/core.c if (old == val) val 393 kernel/sched/core.c val = old; val 3760 kernel/sched/core.c static inline void preempt_latency_start(int val) val 3762 kernel/sched/core.c if (preempt_count() == val) { val 3771 kernel/sched/core.c void preempt_count_add(int val) val 3780 kernel/sched/core.c __preempt_count_add(val); val 3788 kernel/sched/core.c preempt_latency_start(val); val 3797 kernel/sched/core.c static inline void preempt_latency_stop(int val) val 3799 kernel/sched/core.c if (preempt_count() == val) val 3803 kernel/sched/core.c void preempt_count_sub(int val) val 3809 kernel/sched/core.c if (DEBUG_LOCKS_WARN_ON(val > preempt_count())) val 3814 kernel/sched/core.c if (DEBUG_LOCKS_WARN_ON((val < PREEMPT_MASK) && val 3819 kernel/sched/core.c preempt_latency_stop(val); val 3820 kernel/sched/core.c __preempt_count_sub(val); val 3826 kernel/sched/core.c static inline void preempt_latency_start(int val) { } val 3827 kernel/sched/core.c static inline void preempt_latency_stop(int val) { } val 7639 kernel/sched/core.c struct cftype *cft, s64 val) val 7641 kernel/sched/core.c return sched_group_set_rt_runtime(css_tg(css), val); val 134 kernel/sched/cpuacct.c static void cpuacct_cpuusage_write(struct cpuacct *ca, int cpu, u64 val) val 147 kernel/sched/cpuacct.c cpuusage->usages[i] = val; val 186 kernel/sched/cpuacct.c u64 val) val 194 kernel/sched/cpuacct.c if (val) val 272 kernel/sched/cpuacct.c s64 val[CPUACCT_STAT_NSTATS]; val 276 kernel/sched/cpuacct.c memset(val, 0, sizeof(val)); val 280 kernel/sched/cpuacct.c val[CPUACCT_STAT_USER] += cpustat[CPUTIME_USER]; val 281 kernel/sched/cpuacct.c val[CPUACCT_STAT_USER] += cpustat[CPUTIME_NICE]; val 282 kernel/sched/cpuacct.c val[CPUACCT_STAT_SYSTEM] += cpustat[CPUTIME_SYSTEM]; val 283 kernel/sched/cpuacct.c val[CPUACCT_STAT_SYSTEM] += cpustat[CPUTIME_IRQ]; val 284 kernel/sched/cpuacct.c val[CPUACCT_STAT_SYSTEM] += cpustat[CPUTIME_SOFTIRQ]; val 290 kernel/sched/cpuacct.c (long long)nsec_to_clock_t(val[stat])); val 360 kernel/sched/cpuacct.c void cpuacct_account_field(struct task_struct *tsk, int index, u64 val) val 366 kernel/sched/cpuacct.c this_cpu_ptr(ca->cpustat)->cpustat[index] += val; val 2793 kernel/sched/fair.c typeof(_val) val = (_val); \ val 2796 kernel/sched/fair.c res = var + val; \ val 2798 kernel/sched/fair.c if (val < 0 && res > var) \ val 2813 kernel/sched/fair.c typeof(*ptr) val = (_val); \ val 2815 kernel/sched/fair.c res = var - val; \ val 5829 kernel/sched/fair.c static inline void set_idle_cores(int cpu, int val) val 5835 kernel/sched/fair.c WRITE_ONCE(sds->has_idle_cores, val); val 37 kernel/sched/pelt.c static u64 decay_load(u64 val, u64 n) val 55 kernel/sched/pelt.c val >>= local_n / LOAD_AVG_PERIOD; val 59 kernel/sched/pelt.c val = mul_u64_u32_shr(val, runnable_avg_yN_inv[local_n], 32); val 60 kernel/sched/pelt.c return val; val 38 kernel/sched/stats.h #define __schedstat_set(var, val) do { var = (val); } while (0) val 39 kernel/sched/stats.h #define schedstat_set(var, val) do { if (schedstat_enabled()) { var = (val); } } while (0) val 52 kernel/sched/stats.h # define __schedstat_set(var, val) do { } while (0) val 53 kernel/sched/stats.h # define schedstat_set(var, val) do { } while (0) val 15 kernel/sched/wait_bit.c unsigned long val = (unsigned long)word << shift | bit; val 17 kernel/sched/wait_bit.c return bit_wait_table + hash_long(val, WAIT_TABLE_BITS); val 77 kernel/seccomp.c long val; val 765 kernel/seccomp.c ret = n.val; val 999 kernel/seccomp.c knotif->val = 0; val 1125 kernel/seccomp.c knotif->val = resp.val; val 1904 kernel/sys.c u64 val = *(u64 *)((char *)prctl_map + offsets[i]); val 1906 kernel/sys.c if ((unsigned long)val >= mmap_max_addr || val 1907 kernel/sys.c (unsigned long)val < mmap_min_addr) val 2577 kernel/sys.c struct sysinfo val; val 2579 kernel/sys.c do_sysinfo(&val); val 2581 kernel/sys.c if (copy_to_user(info, &val, sizeof(struct sysinfo))) val 2200 kernel/sysctl.c unsigned long *val, bool *neg, val 2225 kernel/sysctl.c if (strtoul_lenient(p, &p, 0, val)) val 2259 kernel/sysctl.c static int proc_put_long(void __user **buf, size_t *size, unsigned long val, val 2265 kernel/sysctl.c sprintf(p, "%s%lu", neg ? "-" : "", val); val 2304 kernel/sysctl.c int val = *valp; val 2305 kernel/sysctl.c if (val < 0) { val 2307 kernel/sysctl.c *lvalp = -(unsigned long)val; val 2310 kernel/sysctl.c *lvalp = (unsigned long)val; val 2325 kernel/sysctl.c unsigned int val = *valp; val 2326 kernel/sysctl.c *lvalp = (unsigned long)val; val 2791 kernel/sysctl.c unsigned int val; val 2793 kernel/sysctl.c val = round_pipe_size(*lvalp); val 2794 kernel/sysctl.c if (val == 0) val 2797 kernel/sysctl.c *valp = val; val 2799 kernel/sysctl.c unsigned int val = *valp; val 2800 kernel/sysctl.c *lvalp = (unsigned long) val; val 2881 kernel/sysctl.c unsigned long val; val 2890 kernel/sysctl.c err = proc_get_long(&p, &left, &val, &neg, val 2897 kernel/sysctl.c val = convmul * val / convdiv; val 2898 kernel/sysctl.c if ((min && val < *min) || (max && val > *max)) { val 2902 kernel/sysctl.c *i = val; val 2904 kernel/sysctl.c val = convdiv * (*i) / convmul; val 2910 kernel/sysctl.c err = proc_put_long(&buffer, &left, val, false); val 2998 kernel/sysctl.c int val = *valp; val 3000 kernel/sysctl.c if (val < 0) { val 3002 kernel/sysctl.c lval = -(unsigned long)val; val 3005 kernel/sysctl.c lval = (unsigned long)val; val 3021 kernel/sysctl.c int val = *valp; val 3023 kernel/sysctl.c if (val < 0) { val 3025 kernel/sysctl.c lval = -(unsigned long)val; val 3028 kernel/sysctl.c lval = (unsigned long)val; val 3046 kernel/sysctl.c int val = *valp; val 3048 kernel/sysctl.c if (val < 0) { val 3050 kernel/sysctl.c lval = -(unsigned long)val; val 3053 kernel/sysctl.c lval = (unsigned long)val; val 3392 kernel/sysctl.c int val, ret; val 3394 kernel/sysctl.c .data = &val, val 3395 kernel/sysctl.c .maxlen = sizeof(val), val 3405 kernel/sysctl.c val = static_key_enabled(key); val 3408 kernel/sysctl.c if (val) val 50 kernel/time/itimer.c u64 val, interval; val 55 kernel/time/itimer.c val = it->expires; val 57 kernel/time/itimer.c if (val) { val 63 kernel/time/itimer.c if (val < t) val 65 kernel/time/itimer.c val = TICK_NSEC; val 67 kernel/time/itimer.c val -= t; val 72 kernel/time/itimer.c value->it_value = ns_to_timeval(val); val 565 kernel/time/posix-cpu-timers.c u64 old_expires, new_expires, old_incr, val; val 615 kernel/time/posix-cpu-timers.c val = cpu_clock_sample(clkid, p); val 617 kernel/time/posix-cpu-timers.c val = cpu_clock_sample_group(clkid, p, true); val 631 kernel/time/posix-cpu-timers.c u64 exp = bump_cpu_timer(timer, val); val 633 kernel/time/posix-cpu-timers.c if (val < exp) { val 634 kernel/time/posix-cpu-timers.c old_expires = exp - val; val 655 kernel/time/posix-cpu-timers.c new_expires += val; val 664 kernel/time/posix-cpu-timers.c if (new_expires != 0 && val < new_expires) { val 685 kernel/time/posix-cpu-timers.c if (new_expires != 0 && !(val < new_expires)) { val 183 kernel/time/tick-sched.c int val = atomic_read(dep); val 185 kernel/time/tick-sched.c if (val & TICK_DEP_MASK_POSIX_TIMER) { val 190 kernel/time/tick-sched.c if (val & TICK_DEP_MASK_PERF_EVENTS) { val 195 kernel/time/tick-sched.c if (val & TICK_DEP_MASK_SCHED) { val 200 kernel/time/tick-sched.c if (val & TICK_DEP_MASK_CLOCK_UNSTABLE) { val 52 kernel/trace/blktrace.c .val = 0, val 171 kernel/trace/blktrace.c if (!(blk_tracer_flags.val & TRACE_BLK_OPT_CGROUP)) val 764 kernel/trace/blktrace.c if (!bt || !(blk_tracer_flags.val & TRACE_BLK_OPT_CGROUP)) val 1262 kernel/trace/blktrace.c const __u64 *val = pdu_start(ent, has_cg); val 1263 kernel/trace/blktrace.c return be64_to_cpu(*val); val 1307 kernel/trace/blktrace.c if (blk_tracer_flags.val & TRACE_BLK_OPT_CGNAME) { val 1454 kernel/trace/blktrace.c if (!(blk_tracer_flags.val & TRACE_BLK_OPT_CLASSIC)) val 1569 kernel/trace/blktrace.c if (!(blk_tracer_flags.val & TRACE_BLK_OPT_CLASSIC)) val 19 kernel/trace/fgraph.c #define ASSIGN_OPS_HASH(opsname, val) \ val 20 kernel/trace/fgraph.c .func_hash = val, \ val 23 kernel/trace/fgraph.c #define ASSIGN_OPS_HASH(opsname, val) val 892 kernel/trace/ftrace.c unsigned long val; val 895 kernel/trace/ftrace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 899 kernel/trace/ftrace.c val = !!val; val 902 kernel/trace/ftrace.c if (ftrace_profile_enabled ^ val) { val 903 kernel/trace/ftrace.c if (val) { val 3914 kernel/trace/ftrace.c unsigned long val; val 3922 kernel/trace/ftrace.c val = module_kallsyms_lookup_name(modname); val 3923 kernel/trace/ftrace.c return val != 0; val 855 kernel/trace/ring_buffer.c unsigned long val = (unsigned long)list; val 857 kernel/trace/ring_buffer.c return (struct list_head *)(val & ~RB_FLAG_MASK); val 872 kernel/trace/ring_buffer.c unsigned long val; val 874 kernel/trace/ring_buffer.c val = (unsigned long)list->next; val 876 kernel/trace/ring_buffer.c if ((val & ~RB_FLAG_MASK) != (unsigned long)&page->list) val 879 kernel/trace/ring_buffer.c return val & RB_FLAG_MASK; val 954 kernel/trace/ring_buffer.c unsigned long val = (unsigned long)&head->list; val 959 kernel/trace/ring_buffer.c val &= ~RB_FLAG_MASK; val 962 kernel/trace/ring_buffer.c val | old_flag, val | new_flag); val 965 kernel/trace/ring_buffer.c if ((ret & ~RB_FLAG_MASK) != val) val 1048 kernel/trace/ring_buffer.c unsigned long val; val 1051 kernel/trace/ring_buffer.c val = *ptr & ~RB_FLAG_MASK; val 1052 kernel/trace/ring_buffer.c val |= RB_PAGE_HEAD; val 1054 kernel/trace/ring_buffer.c ret = cmpxchg(ptr, val, (unsigned long)&new->list); val 1056 kernel/trace/ring_buffer.c return ret == val; val 1095 kernel/trace/ring_buffer.c unsigned long val = old_write & ~RB_WRITE_MASK; val 1108 kernel/trace/ring_buffer.c (void)local_cmpxchg(&next_page->write, old_write, val); val 1126 kernel/trace/ring_buffer.c unsigned long val = (unsigned long)bpage; val 1128 kernel/trace/ring_buffer.c if (RB_WARN_ON(cpu_buffer, val & RB_FLAG_MASK)) val 1894 kernel/trace/ring_buffer.c void ring_buffer_change_overwrite(struct ring_buffer *buffer, int val) val 1897 kernel/trace/ring_buffer.c if (val) val 2694 kernel/trace/ring_buffer.c unsigned int val = cpu_buffer->current_context; val 2704 kernel/trace/ring_buffer.c if (unlikely(val & (1 << (bit + cpu_buffer->nest)))) val 2707 kernel/trace/ring_buffer.c val |= (1 << (bit + cpu_buffer->nest)); val 2708 kernel/trace/ring_buffer.c cpu_buffer->current_context = val; val 502 kernel/trace/trace.c unsigned long val; val 559 kernel/trace/trace.c if (kstrtoul(parser.buffer, 0, &val)) val 561 kernel/trace/trace.c if (val >= pid_list->pid_max) val 564 kernel/trace/trace.c pid = (pid_t)val; val 1026 kernel/trace/trace.c static void set_buffer_entries(struct trace_buffer *buf, unsigned long val); val 1838 kernel/trace/trace.c type->flags->val = 0; val 1963 kernel/trace/trace.c static int allocate_cmdlines_buffer(unsigned int val, val 1966 kernel/trace/trace.c s->map_cmdline_to_pid = kmalloc_array(val, val 1972 kernel/trace/trace.c s->saved_cmdlines = kmalloc_array(TASK_COMM_LEN, val, GFP_KERNEL); val 1979 kernel/trace/trace.c s->cmdline_num = val; val 1983 kernel/trace/trace.c val * sizeof(*s->map_cmdline_to_pid)); val 2491 kernel/trace/trace.c int val; val 2499 kernel/trace/trace.c val = this_cpu_inc_return(trace_buffered_event_cnt); val 2500 kernel/trace/trace.c if (val == 1) { val 4533 kernel/trace/trace.c tracer_flags = tr->current_trace->flags->val; val 4561 kernel/trace/trace.c ret = trace->set_flag(tr, tracer_flags->val, opts->bit, !neg); val 4566 kernel/trace/trace.c tracer_flags->val &= ~opts->bit; val 4568 kernel/trace/trace.c tracer_flags->val |= opts->bit; val 5202 kernel/trace/trace.c static int tracing_resize_saved_cmdlines(unsigned int val) val 5210 kernel/trace/trace.c if (allocate_cmdlines_buffer(val, s) < 0) { val 5228 kernel/trace/trace.c unsigned long val; val 5231 kernel/trace/trace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 5236 kernel/trace/trace.c if (!val || val > PID_MAX_DEFAULT) val 5239 kernel/trace/trace.c ret = tracing_resize_saved_cmdlines((unsigned int)val); val 5454 kernel/trace/trace.c static void set_buffer_entries(struct trace_buffer *buf, unsigned long val) val 5459 kernel/trace/trace.c per_cpu_ptr(buf->data, cpu)->entries = val; val 5794 kernel/trace/trace.c unsigned long val; val 5797 kernel/trace/trace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 5801 kernel/trace/trace.c *ptr = val * 1000; val 6303 kernel/trace/trace.c unsigned long val; val 6306 kernel/trace/trace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 6311 kernel/trace/trace.c if (!val) val 6315 kernel/trace/trace.c val <<= 10; val 6316 kernel/trace/trace.c ret = tracing_resize_ring_buffer(tr, val, tracing_get_cpu(inode)); val 6732 kernel/trace/trace.c unsigned long val; val 6739 kernel/trace/trace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 6757 kernel/trace/trace.c switch (val) { val 7873 kernel/trace/trace.c if (topt->flags->val & topt->opt->bit) val 7886 kernel/trace/trace.c unsigned long val; val 7889 kernel/trace/trace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 7893 kernel/trace/trace.c if (val != 0 && val != 1) val 7896 kernel/trace/trace.c if (!!(topt->flags->val & topt->opt->bit) != val) { val 7899 kernel/trace/trace.c topt->opt, !val); val 7977 kernel/trace/trace.c unsigned long val; val 7982 kernel/trace/trace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 7986 kernel/trace/trace.c if (val != 0 && val != 1) val 7991 kernel/trace/trace.c ret = set_tracer_flag(tr, 1 << index, val); val 8180 kernel/trace/trace.c unsigned long val; val 8183 kernel/trace/trace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 8189 kernel/trace/trace.c if (!!val == tracer_tracing_is_on(tr)) { val 8190 kernel/trace/trace.c val = 0; /* do nothing */ val 8191 kernel/trace/trace.c } else if (val) { val 8235 kernel/trace/trace.c unsigned long val; val 8238 kernel/trace/trace.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 8242 kernel/trace/trace.c if (val > 100) val 8245 kernel/trace/trace.c if (!val) val 8246 kernel/trace/trace.c val = 1; val 8248 kernel/trace/trace.c tr->buffer_percent = val; val 8757 kernel/trace/trace.c unsigned long val, void *data) val 8761 kernel/trace/trace.c switch (val) { val 8844 kernel/trace/trace.c unsigned long val, val 8847 kernel/trace/trace.c switch (val) { val 430 kernel/trace/trace.h u32 val; val 641 kernel/trace/trace.h unsigned int val = current->trace_recursion; val 645 kernel/trace/trace.h if ((val & TRACE_CONTEXT_MASK) > max) val 649 kernel/trace/trace.h if (unlikely(val & (1 << bit))) val 652 kernel/trace/trace.h val |= 1 << bit; val 653 kernel/trace/trace.h current->trace_recursion = val; val 661 kernel/trace/trace.h unsigned int val = current->trace_recursion; val 667 kernel/trace/trace.h val &= ~bit; val 670 kernel/trace/trace.h current->trace_recursion = val; val 1539 kernel/trace/trace.h u64 val; val 31 kernel/trace/trace_branch.c probe_likely_condition(struct ftrace_likely_data *f, int val, int expect) val 83 kernel/trace/trace_branch.c entry->correct = val == expect; val 94 kernel/trace/trace_branch.c void trace_likely_condition(struct ftrace_likely_data *f, int val, int expect) val 99 kernel/trace/trace_branch.c probe_likely_condition(f, val, expect); val 200 kernel/trace/trace_branch.c void trace_likely_condition(struct ftrace_likely_data *f, int val, int expect) val 205 kernel/trace/trace_branch.c void ftrace_likely_update(struct ftrace_likely_data *f, int val, val 213 kernel/trace/trace_branch.c val = expect; val 221 kernel/trace/trace_branch.c trace_likely_condition(f, val, expect); val 224 kernel/trace/trace_branch.c if (val == expect) val 1060 kernel/trace/trace_events.c unsigned long val; val 1063 kernel/trace/trace_events.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 1071 kernel/trace/trace_events.c switch (val) { val 1078 kernel/trace/trace_events.c ret = ftrace_event_enable_disable(file, val); val 1144 kernel/trace/trace_events.c unsigned long val; val 1147 kernel/trace/trace_events.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 1155 kernel/trace/trace_events.c if (val != 0 && val != 1) val 1165 kernel/trace/trace_events.c ret = __ftrace_set_clr_event(dir->tr, NULL, name, NULL, val); val 2427 kernel/trace/trace_events.c unsigned long val, void *data) val 2433 kernel/trace/trace_events.c switch (val) { val 596 kernel/trace/trace_events_filter.c type val = (type)pred->val; \ val 597 kernel/trace/trace_events_filter.c return *addr < val; \ val 602 kernel/trace/trace_events_filter.c type val = (type)pred->val; \ val 603 kernel/trace/trace_events_filter.c return *addr <= val; \ val 608 kernel/trace/trace_events_filter.c type val = (type)pred->val; \ val 609 kernel/trace/trace_events_filter.c return *addr > val; \ val 614 kernel/trace/trace_events_filter.c type val = (type)pred->val; \ val 615 kernel/trace/trace_events_filter.c return *addr >= val; \ val 620 kernel/trace/trace_events_filter.c type val = (type)pred->val; \ val 621 kernel/trace/trace_events_filter.c return !!(*addr & val); \ val 635 kernel/trace/trace_events_filter.c u##size val = (u##size)pred->val; \ val 638 kernel/trace/trace_events_filter.c match = (val == *addr) ^ pred->not; \ val 715 kernel/trace/trace_events_filter.c cmp = pred->val; val 1162 kernel/trace/trace_events_filter.c u64 val; val 1360 kernel/trace/trace_events_filter.c ret = kstrtoll(num_buf, 0, &val); val 1362 kernel/trace/trace_events_filter.c ret = kstrtoull(num_buf, 0, &val); val 1368 kernel/trace/trace_events_filter.c pred->val = val; val 208 kernel/trace/trace_events_hist.c u64 val = operand->fn(operand, elt, rbe, event); val 210 kernel/trace/trace_events_hist.c return (u64) ilog2(roundup_pow_of_two(val)); val 249 kernel/trace/trace_events_hist.c u64 val = (u64)-sval; val 251 kernel/trace/trace_events_hist.c return val; val 339 kernel/trace/trace_events_hist.c struct hist_field *val; val 816 kernel/trace/trace_events_hist.c int size, u64 val, char *space) val 820 kernel/trace/trace_events_hist.c trace_seq_printf(s, print_fmt, name, (u8)val, space); val 824 kernel/trace/trace_events_hist.c trace_seq_printf(s, print_fmt, name, (u16)val, space); val 828 kernel/trace/trace_events_hist.c trace_seq_printf(s, print_fmt, name, (u32)val, space); val 832 kernel/trace/trace_events_hist.c trace_seq_printf(s, print_fmt, name, val, space); val 944 kernel/trace/trace_events_hist.c u64 val = var_ref_vals[val_idx]; val 948 kernel/trace/trace_events_hist.c *(u8 *)&entry->fields[n_u64] = (u8)val; val 952 kernel/trace/trace_events_hist.c *(u16 *)&entry->fields[n_u64] = (u16)val; val 956 kernel/trace/trace_events_hist.c *(u32 *)&entry->fields[n_u64] = (u32)val; val 960 kernel/trace/trace_events_hist.c entry->fields[n_u64] = val; val 3475 kernel/trace/trace_events_hist.c struct hist_field *val = field_var->val; val 3477 kernel/trace/trace_events_hist.c var_val = val->fn(val, elt, rbe, rec); val 3480 kernel/trace/trace_events_hist.c if (val->flags & HIST_FIELD_FL_STRING) { val 3555 kernel/trace/trace_events_hist.c struct hist_field *val = NULL, *var = NULL; val 3567 kernel/trace/trace_events_hist.c val = parse_atom(hist_data, file, field_name, &flags, NULL); val 3568 kernel/trace/trace_events_hist.c if (IS_ERR(val)) { val 3570 kernel/trace/trace_events_hist.c ret = PTR_ERR(val); val 3574 kernel/trace/trace_events_hist.c var = create_var(hist_data, file, field_name, val->size, val->type); val 3577 kernel/trace/trace_events_hist.c kfree(val); val 3584 kernel/trace/trace_events_hist.c kfree(val); val 3591 kernel/trace/trace_events_hist.c field_var->val = val; val 3831 kernel/trace/trace_events_hist.c struct hist_field *save_val = hist_data->save_vars[i]->val; val 3833 kernel/trace/trace_events_hist.c u64 val; val 3837 kernel/trace/trace_events_hist.c val = tracing_map_read_var(elt, save_var_idx); val 3841 kernel/trace/trace_events_hist.c (char *)(uintptr_t)(val)); val 3843 kernel/trace/trace_events_hist.c seq_printf(m, " %s: %10llu", save_var->var.name, val); val 4153 kernel/trace/trace_events_hist.c destroy_hist_field(field_var->val, 0); val 4174 kernel/trace/trace_events_hist.c if (field_var->val->flags & HIST_FIELD_FL_STRING) val 4434 kernel/trace/trace_events_hist.c if (field_var->val->flags & HIST_FIELD_FL_STRING) val 97 kernel/trace/trace_functions.c func_flags.val & TRACE_FUNC_OPT_STACK) val 216 kernel/trace/trace_functions.c .val = 0, /* By default: all flags disabled */ val 241 kernel/trace/trace_functions.c if (!!set == !!(func_flags.val & TRACE_FUNC_OPT_STACK)) val 74 kernel/trace/trace_functions_graph.c .val = TRACE_GRAPH_PRINT_CPU | TRACE_GRAPH_PRINT_OVERHEAD | val 1102 kernel/trace/trace_functions_graph.c return print_graph_function_flags(iter, tracer_flags.val); val 1178 kernel/trace/trace_functions_graph.c print_graph_headers_flags(s, tracer_flags.val); val 1304 kernel/trace/trace_functions_graph.c unsigned long val; val 1307 kernel/trace/trace_functions_graph.c ret = kstrtoul_from_user(ubuf, cnt, 10, &val); val 1311 kernel/trace/trace_functions_graph.c fgraph_max_depth = val; val 412 kernel/trace/trace_hwlat.c u64 val; val 421 kernel/trace/trace_hwlat.c val = *entry; val 423 kernel/trace/trace_hwlat.c len = snprintf(buf, sizeof(buf), "%llu\n", val); val 447 kernel/trace/trace_hwlat.c u64 val; val 450 kernel/trace/trace_hwlat.c err = kstrtoull_from_user(ubuf, cnt, 10, &val); val 455 kernel/trace/trace_hwlat.c if (val < hwlat_data.sample_window) val 456 kernel/trace/trace_hwlat.c hwlat_data.sample_width = val; val 486 kernel/trace/trace_hwlat.c u64 val; val 489 kernel/trace/trace_hwlat.c err = kstrtoull_from_user(ubuf, cnt, 10, &val); val 494 kernel/trace/trace_hwlat.c if (hwlat_data.sample_width < val) val 495 kernel/trace/trace_hwlat.c hwlat_data.sample_window = val; val 672 kernel/trace/trace_kprobe.c unsigned long val, void *data) val 679 kernel/trace/trace_kprobe.c if (val != MODULE_STATE_COMING) val 1131 kernel/trace/trace_kprobe.c unsigned long val; val 1137 kernel/trace/trace_kprobe.c val = regs_get_register(regs, code->param); val 1140 kernel/trace/trace_kprobe.c val = regs_get_kernel_stack_nth(regs, code->param); val 1143 kernel/trace/trace_kprobe.c val = kernel_stack_pointer(regs); val 1146 kernel/trace/trace_kprobe.c val = regs_return_value(regs); val 1149 kernel/trace/trace_kprobe.c val = code->immediate; val 1152 kernel/trace/trace_kprobe.c val = (unsigned long)current->comm; val 1155 kernel/trace/trace_kprobe.c val = (unsigned long)code->data; val 1159 kernel/trace/trace_kprobe.c val = regs_get_kernel_argument(regs, code->param); val 1170 kernel/trace/trace_kprobe.c return process_fetch_insn_bottom(code, val, dest, base); val 31 kernel/trace/trace_nop.c .val = 0, /* By default: all flags disabled */ val 103 kernel/trace/trace_output.c trace_print_symbols_seq(struct trace_seq *p, unsigned long val, val 111 kernel/trace/trace_output.c if (val != symbol_array[i].mask) val 119 kernel/trace/trace_output.c trace_seq_printf(p, "0x%lx", val); val 167 kernel/trace/trace_output.c trace_print_symbols_seq_u64(struct trace_seq *p, unsigned long long val, val 175 kernel/trace/trace_output.c if (val != symbol_array[i].mask) val 183 kernel/trace/trace_output.c trace_seq_printf(p, "0x%llx", val); val 492 kernel/trace/trace_output.c #define MARK(v, s) {.val = v, .sym = s} val 495 kernel/trace/trace_output.c unsigned long long val; /* unit: nsec */ val 513 kernel/trace/trace_output.c if (d > mark[i].val) val 89 kernel/trace/trace_printk.c unsigned long val, void *data) val 96 kernel/trace/trace_printk.c if (val == MODULE_STATE_COMING) val 175 kernel/trace/trace_printk.c unsigned long val, void *data) val 7 kernel/trace/trace_probe_tmpl.h fetch_store_raw(unsigned long val, struct fetch_insn *code, void *buf) val 11 kernel/trace/trace_probe_tmpl.h *(u8 *)buf = (u8)val; val 14 kernel/trace/trace_probe_tmpl.h *(u16 *)buf = (u16)val; val 17 kernel/trace/trace_probe_tmpl.h *(u32 *)buf = (u32)val; val 21 kernel/trace/trace_probe_tmpl.h *(u64 *)buf = (u64)val; val 24 kernel/trace/trace_probe_tmpl.h *(unsigned long *)buf = val; val 72 kernel/trace/trace_probe_tmpl.h process_fetch_insn_bottom(struct fetch_insn *code, unsigned long val, val 78 kernel/trace/trace_probe_tmpl.h unsigned long lval = val; val 84 kernel/trace/trace_probe_tmpl.h lval = val; val 85 kernel/trace/trace_probe_tmpl.h ret = probe_mem_read(&val, (void *)val + code->offset, val 86 kernel/trace/trace_probe_tmpl.h sizeof(val)); val 88 kernel/trace/trace_probe_tmpl.h lval = val; val 89 kernel/trace/trace_probe_tmpl.h ret = probe_mem_read_user(&val, val 90 kernel/trace/trace_probe_tmpl.h (void *)val + code->offset, sizeof(val)); val 103 kernel/trace/trace_probe_tmpl.h ret = fetch_store_strlen(val + code->offset); val 107 kernel/trace/trace_probe_tmpl.h ret += fetch_store_strlen_user(val + code->offset); val 116 kernel/trace/trace_probe_tmpl.h fetch_store_raw(val, code, dest); val 119 kernel/trace/trace_probe_tmpl.h probe_mem_read(dest, (void *)val + code->offset, code->size); val 122 kernel/trace/trace_probe_tmpl.h probe_mem_read_user(dest, (void *)val + code->offset, code->size); val 126 kernel/trace/trace_probe_tmpl.h ret = fetch_store_string(val + code->offset, dest, base); val 130 kernel/trace/trace_probe_tmpl.h ret = fetch_store_string_user(val + code->offset, dest, base); val 152 kernel/trace/trace_probe_tmpl.h val += s3->size; val 156 kernel/trace/trace_probe_tmpl.h val = lval + sizeof(char *); val 343 kernel/trace/trace_stack.c unsigned long val, flags; val 346 kernel/trace/trace_stack.c ret = kstrtoul_from_user(ubuf, count, 10, &val); val 360 kernel/trace/trace_stack.c *ptr = val; val 223 kernel/trace/trace_uprobe.c unsigned long val; val 228 kernel/trace/trace_uprobe.c val = regs_get_register(regs, code->param); val 231 kernel/trace/trace_uprobe.c val = get_user_stack_nth(regs, code->param); val 234 kernel/trace/trace_uprobe.c val = user_stack_pointer(regs); val 237 kernel/trace/trace_uprobe.c val = regs_return_value(regs); val 240 kernel/trace/trace_uprobe.c val = code->immediate; val 243 kernel/trace/trace_uprobe.c val = FETCH_TOKEN_COMM; val 246 kernel/trace/trace_uprobe.c val = (unsigned long)code->data; val 249 kernel/trace/trace_uprobe.c val = translate_user_vaddr(code->immediate); val 256 kernel/trace/trace_uprobe.c return process_fetch_insn_bottom(code, val, dest, base); val 518 kernel/trace/tracing_map.c struct tracing_map_elt *val; val 531 kernel/trace/tracing_map.c val = READ_ONCE(entry->val); val 532 kernel/trace/tracing_map.c if (val && val 533 kernel/trace/tracing_map.c keys_match(key, val->key, map->key_size)) { val 536 kernel/trace/tracing_map.c return val; val 537 kernel/trace/tracing_map.c } else if (unlikely(!val)) { val 574 kernel/trace/tracing_map.c entry->val = elt; val 577 kernel/trace/tracing_map.c return entry->val; val 1078 kernel/trace/tracing_map.c if (!entry->key || !entry->val) val 1081 kernel/trace/tracing_map.c entries[n_entries] = create_sort_entry(entry->val->key, val 1082 kernel/trace/tracing_map.c entry->val); val 149 kernel/trace/tracing_map.h struct tracing_map_elt *val; val 507 kernel/tracepoint.c unsigned long val, void *data) val 512 kernel/tracepoint.c switch (val) { val 2338 kernel/workqueue.c static void set_pf_worker(bool val) val 2341 kernel/workqueue.c if (val) val 5371 kernel/workqueue.c int val; val 5373 kernel/workqueue.c if (sscanf(buf, "%d", &val) != 1 || val <= 0) val 5376 kernel/workqueue.c workqueue_set_max_active(wq, val); val 5801 kernel/workqueue.c static int wq_watchdog_param_set_thresh(const char *val, val 5807 kernel/workqueue.c ret = kstrtoul(val, 0, &thresh); val 49 lib/atomic64.c s64 val; val 52 lib/atomic64.c val = v->counter; val 54 lib/atomic64.c return val; val 86 lib/atomic64.c s64 val; \ val 89 lib/atomic64.c val = (v->counter c_op a); \ val 91 lib/atomic64.c return val; \ val 100 lib/atomic64.c s64 val; \ val 103 lib/atomic64.c val = v->counter; \ val 106 lib/atomic64.c return val; \ val 137 lib/atomic64.c s64 val; val 140 lib/atomic64.c val = v->counter - 1; val 141 lib/atomic64.c if (val >= 0) val 142 lib/atomic64.c v->counter = val; val 144 lib/atomic64.c return val; val 152 lib/atomic64.c s64 val; val 155 lib/atomic64.c val = v->counter; val 156 lib/atomic64.c if (val == o) val 159 lib/atomic64.c return val; val 167 lib/atomic64.c s64 val; val 170 lib/atomic64.c val = v->counter; val 173 lib/atomic64.c return val; val 181 lib/atomic64.c s64 val; val 184 lib/atomic64.c val = v->counter; val 185 lib/atomic64.c if (val != u) val 189 lib/atomic64.c return val; val 20 lib/atomic64_test.c #define TEST(bit, op, c_op, val) \ val 24 lib/atomic64_test.c atomic##bit##_##op(val, &v); \ val 25 lib/atomic64_test.c r c_op val; \ val 44 lib/atomic64_test.c #define TEST_RETURN(bit, op, c_op, val) \ val 48 lib/atomic64_test.c r c_op val; \ val 49 lib/atomic64_test.c BUG_ON(atomic##bit##_##op(val, &v) != r); \ val 53 lib/atomic64_test.c #define TEST_FETCH(bit, op, c_op, val) \ val 57 lib/atomic64_test.c r c_op val; \ val 58 lib/atomic64_test.c BUG_ON(atomic##bit##_##op(val, &v) != v0); \ val 62 lib/atomic64_test.c #define RETURN_FAMILY_TEST(bit, op, c_op, val) \ val 64 lib/atomic64_test.c FAMILY_TEST(TEST_RETURN, bit, op, c_op, val); \ val 67 lib/atomic64_test.c #define FETCH_FAMILY_TEST(bit, op, c_op, val) \ val 69 lib/atomic64_test.c FAMILY_TEST(TEST_FETCH, bit, op, c_op, val); \ val 5 lib/bcd.c unsigned _bcd2bin(unsigned char val) val 7 lib/bcd.c return (val & 0x0f) + (val >> 4) * 10; val 11 lib/bcd.c unsigned char _bin2bcd(unsigned val) val 13 lib/bcd.c return ((val / 10) << 4) + val % 10; val 357 lib/bitmap.c #define nbits_to_hold_value(val) fls(val) val 137 lib/btree.c unsigned long val; val 141 lib/btree.c val = key[i]; val 142 lib/btree.c key[i] = val - 1; val 143 lib/btree.c if (val) val 165 lib/btree.c void *val) val 167 lib/btree.c node[geo->no_longs + n] = (unsigned long) val; val 272 lib/btree.c unsigned long *key, void *val) val 296 lib/btree.c setval(geo, node, i, val); val 449 lib/btree.c unsigned long *key, void *val, int level, val 455 lib/btree.c BUG_ON(!val); val 505 lib/btree.c setval(geo, node, pos, val); val 511 lib/btree.c unsigned long *key, void *val, gfp_t gfp) val 513 lib/btree.c BUG_ON(!val); val 514 lib/btree.c return btree_insert_level(head, geo, key, val, 1, gfp); val 644 lib/btree.c void *val; val 663 lib/btree.c val = btree_lookup(victim, geo, key); val 664 lib/btree.c err = btree_insert(target, geo, key, val, gfp); val 17 lib/clz_ctz.c int __weak __ctzsi2(int val); val 18 lib/clz_ctz.c int __weak __ctzsi2(int val) val 20 lib/clz_ctz.c return __ffs(val); val 24 lib/clz_ctz.c int __weak __clzsi2(int val); val 25 lib/clz_ctz.c int __weak __clzsi2(int val) val 27 lib/clz_ctz.c return 32 - fls(val); val 31 lib/clz_ctz.c int __weak __clzdi2(long val); val 32 lib/clz_ctz.c int __weak __ctzdi2(long val); val 35 lib/clz_ctz.c int __weak __clzdi2(long val) val 37 lib/clz_ctz.c return 32 - fls((int)val); val 41 lib/clz_ctz.c int __weak __ctzdi2(long val) val 43 lib/clz_ctz.c return __ffs((u32)val); val 49 lib/clz_ctz.c int __weak __clzdi2(long val) val 51 lib/clz_ctz.c return 64 - fls64((u64)val); val 55 lib/clz_ctz.c int __weak __ctzdi2(long val) val 57 lib/clz_ctz.c return __ffs64((u64)val); val 201 lib/cmdline.c char *next_arg(char *args, char **param, char **val) val 226 lib/cmdline.c *val = NULL; val 229 lib/cmdline.c *val = args + equals + 1; val 232 lib/cmdline.c if (**val == '"') { val 233 lib/cmdline.c (*val)++; val 23 lib/crc-t10dif.c static int crc_t10dif_rehash(struct notifier_block *self, unsigned long val, void *data) val 28 lib/crc-t10dif.c if (val != CRYPTO_MSG_ALG_LOADED || val 278 lib/dynamic_debug.c static inline int parse_lineno(const char *str, unsigned int *val) val 282 lib/dynamic_debug.c *val = 0; val 285 lib/dynamic_debug.c if (kstrtouint(str, 10, val) < 0) { val 912 lib/dynamic_debug.c static int ddebug_dyndbg_param_cb(char *param, char *val, val 927 lib/dynamic_debug.c ddebug_exec_queries((val ? val : "+p"), modname); val 933 lib/dynamic_debug.c static int ddebug_dyndbg_boot_param_cb(char *param, char *val, val 936 lib/dynamic_debug.c vpr_info("%s=\"%s\"\n", param, val); val 937 lib/dynamic_debug.c return ddebug_dyndbg_param_cb(param, val, NULL, 0); val 945 lib/dynamic_debug.c int ddebug_dyndbg_module_param_cb(char *param, char *val, const char *module) val 947 lib/dynamic_debug.c vpr_info("module: %s %s=\"%s\"\n", module, param, val); val 948 lib/dynamic_debug.c return ddebug_dyndbg_param_cb(param, val, module, -ENOENT); val 129 lib/error-inject.c unsigned long val, void *data) val 133 lib/error-inject.c if (val == MODULE_STATE_COMING) val 135 lib/error-inject.c else if (val == MODULE_STATE_GOING) val 155 lib/fault-inject.c static int debugfs_ul_set(void *data, u64 val) val 157 lib/fault-inject.c *(unsigned long *)data = val; val 161 lib/fault-inject.c static int debugfs_ul_get(void *data, u64 *val) val 163 lib/fault-inject.c *val = *(unsigned long *)data; val 177 lib/fault-inject.c static int debugfs_stacktrace_depth_set(void *data, u64 val) val 180 lib/fault-inject.c min_t(unsigned long, val, MAX_STACK_TRACE_DEPTH); val 134 lib/find_bit.c unsigned long val = BITMAP_LAST_WORD_MASK(size); val 138 lib/find_bit.c val &= addr[idx]; val 139 lib/find_bit.c if (val) val 140 lib/find_bit.c return idx * BITS_PER_LONG + __fls(val); val 142 lib/find_bit.c val = ~0ul; val 206 lib/flex_proportions.c s64 val = percpu_counter_read(&pl->events); val 208 lib/flex_proportions.c if (val < (nr_cpu_ids * PROP_BATCH)) val 209 lib/flex_proportions.c val = percpu_counter_sum(&pl->events); val 212 lib/flex_proportions.c -val + (val >> (period-pl->period)), PROP_BATCH); val 45 lib/genalloc.c unsigned long val, nval; val 49 lib/genalloc.c val = nval; val 50 lib/genalloc.c if (val & mask_to_set) val 53 lib/genalloc.c } while ((nval = cmpxchg(addr, val, val | mask_to_set)) != val); val 60 lib/genalloc.c unsigned long val, nval; val 64 lib/genalloc.c val = nval; val 65 lib/genalloc.c if ((val & mask_to_clear) != mask_to_clear) val 68 lib/genalloc.c } while ((nval = cmpxchg(addr, val, val & ~mask_to_clear)) != val); val 179 lib/iomap.c #define pio_write16be(val,port) outw(swab16(val),port) val 180 lib/iomap.c #define pio_write32be(val,port) outl(swab32(val),port) val 184 lib/iomap.c #define mmio_write16be(val,port) writew(swab16(val),port) val 185 lib/iomap.c #define mmio_write32be(val,port) writel(swab32(val),port) val 186 lib/iomap.c #define mmio_write64be(val,port) writeq(swab64(val),port) val 189 lib/iomap.c void iowrite8(u8 val, void __iomem *addr) val 191 lib/iomap.c IO_COND(addr, outb(val,port), writeb(val, addr)); val 193 lib/iomap.c void iowrite16(u16 val, void __iomem *addr) val 195 lib/iomap.c IO_COND(addr, outw(val,port), writew(val, addr)); val 197 lib/iomap.c void iowrite16be(u16 val, void __iomem *addr) val 199 lib/iomap.c IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr)); val 201 lib/iomap.c void iowrite32(u32 val, void __iomem *addr) val 203 lib/iomap.c IO_COND(addr, outl(val,port), writel(val, addr)); val 205 lib/iomap.c void iowrite32be(u32 val, void __iomem *addr) val 207 lib/iomap.c IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr)); val 216 lib/iomap.c static void pio_write64_lo_hi(u64 val, unsigned long port) val 218 lib/iomap.c outl(val, port); val 219 lib/iomap.c outl(val >> 32, port + sizeof(u32)); val 222 lib/iomap.c static void pio_write64_hi_lo(u64 val, unsigned long port) val 224 lib/iomap.c outl(val >> 32, port + sizeof(u32)); val 225 lib/iomap.c outl(val, port); val 228 lib/iomap.c static void pio_write64be_lo_hi(u64 val, unsigned long port) val 230 lib/iomap.c pio_write32be(val, port + sizeof(u32)); val 231 lib/iomap.c pio_write32be(val >> 32, port); val 234 lib/iomap.c static void pio_write64be_hi_lo(u64 val, unsigned long port) val 236 lib/iomap.c pio_write32be(val >> 32, port); val 237 lib/iomap.c pio_write32be(val, port + sizeof(u32)); val 240 lib/iomap.c void iowrite64_lo_hi(u64 val, void __iomem *addr) val 242 lib/iomap.c IO_COND(addr, pio_write64_lo_hi(val, port), val 243 lib/iomap.c writeq(val, addr)); val 246 lib/iomap.c void iowrite64_hi_lo(u64 val, void __iomem *addr) val 248 lib/iomap.c IO_COND(addr, pio_write64_hi_lo(val, port), val 249 lib/iomap.c writeq(val, addr)); val 252 lib/iomap.c void iowrite64be_lo_hi(u64 val, void __iomem *addr) val 254 lib/iomap.c IO_COND(addr, pio_write64be_lo_hi(val, port), val 255 lib/iomap.c mmio_write64be(val, addr)); val 258 lib/iomap.c void iowrite64be_hi_lo(u64 val, void __iomem *addr) val 260 lib/iomap.c IO_COND(addr, pio_write64be_hi_lo(val, port), val 261 lib/iomap.c mmio_write64be(val, addr)); val 412 lib/kfifo.c #define __KFIFO_POKE(data, in, mask, val) \ val 414 lib/kfifo.c (data)[(in) & (mask)] = (unsigned char)(val) \ val 58 lib/kstrtox.c unsigned int val; val 61 lib/kstrtox.c val = c - '0'; val 63 lib/kstrtox.c val = lc - 'a' + 10; val 67 lib/kstrtox.c if (val >= base) val 74 lib/kstrtox.c if (res > div_u64(ULLONG_MAX - val, base)) val 77 lib/kstrtox.c res = res * base + val; val 57 lib/lru_cache.c unsigned long val; val 59 lib/lru_cache.c val = cmpxchg(&lc->flags, 0, LC_LOCKED); val 60 lib/lru_cache.c } while (unlikely (val == LC_PARANOIA)); val 62 lib/lru_cache.c return 0 == val; val 66 lib/lru_cache.c unsigned long old, new, val; val 70 lib/lru_cache.c val = cmpxchg(&lc->flags, old, new); val 71 lib/lru_cache.c } while (unlikely (val == (old ^ LC_PARANOIA))); val 72 lib/lru_cache.c return old == val; val 173 lib/lz4/lz4defs.h static FORCE_INLINE unsigned int LZ4_NbCommonBytes(register size_t val) val 176 lib/lz4/lz4defs.h return __ffs(val) >> 3; val 178 lib/lz4/lz4defs.h return (BITS_PER_LONG - 1 - __fls(val)) >> 3; val 41 lib/mpi/mpicoder.c MPI val = NULL; val 57 lib/mpi/mpicoder.c val = mpi_alloc(nlimbs); val 58 lib/mpi/mpicoder.c if (!val) val 60 lib/mpi/mpicoder.c val->nbits = nbits; val 61 lib/mpi/mpicoder.c val->sign = 0; val 62 lib/mpi/mpicoder.c val->nlimbs = nlimbs; val 74 lib/mpi/mpicoder.c val->d[j - 1] = a; val 77 lib/mpi/mpicoder.c return val; val 85 lib/mpi/mpicoder.c MPI val; val 103 lib/mpi/mpicoder.c val = mpi_read_raw_data(buffer + 2, nbytes); val 104 lib/mpi/mpicoder.c if (!val) val 108 lib/mpi/mpicoder.c return val; val 338 lib/mpi/mpicoder.c MPI val = NULL; val 382 lib/mpi/mpicoder.c val = mpi_alloc(nlimbs); val 383 lib/mpi/mpicoder.c if (!val) val 386 lib/mpi/mpicoder.c val->nbits = nbits; val 387 lib/mpi/mpicoder.c val->sign = 0; val 388 lib/mpi/mpicoder.c val->nlimbs = nlimbs; val 391 lib/mpi/mpicoder.c return val; val 406 lib/mpi/mpicoder.c val->d[j--] = a; val 413 lib/mpi/mpicoder.c return val; val 6 lib/notifier-error-inject.c static int debugfs_errno_set(void *data, u64 val) val 8 lib/notifier-error-inject.c *(int *)data = clamp_t(int, val, -MAX_ERRNO, 0); val 12 lib/notifier-error-inject.c static int debugfs_errno_get(void *data, u64 *val) val 14 lib/notifier-error-inject.c *val = *(int *)data; val 28 lib/notifier-error-inject.c unsigned long val, void *p) val 36 lib/notifier-error-inject.c if (action->val == val) { val 7 lib/notifier-error-inject.h unsigned long val; val 13 lib/notifier-error-inject.h .name = #action, .val = (action), val 32 lib/packing.c static u64 bit_reverse(u64 val, unsigned int width) val 39 lib/packing.c bit = (val & (1 << i)) != 0; val 131 lib/parser.c long val; val 138 lib/parser.c val = simple_strtol(buf, &endp, base); val 141 lib/parser.c else if (val < (long)INT_MIN || val > (long)INT_MAX) val 144 lib/parser.c *result = (int) val; val 163 lib/parser.c u64 val; val 169 lib/parser.c ret = kstrtoull(buf, base, &val); val 171 lib/parser.c *result = val; val 18 lib/raid6/recov_neon_inner.c uint8x16_t val; val 153 lib/random32.c unsigned int val = 0; val 155 lib/random32.c (void)(arch_get_random_seed_int(&val) || val 156 lib/random32.c arch_get_random_int(&val)); val 158 lib/random32.c return val; val 23 lib/rbtree_test.c u32 val; val 80 lib/rbtree_test.c #define NODE_VAL(node) ((node)->val) val 90 lib/rbtree_test.c u32 val = node->val; val 96 lib/rbtree_test.c if (parent->augmented < val) val 97 lib/rbtree_test.c parent->augmented = val; val 104 lib/rbtree_test.c node->augmented = val; val 114 lib/rbtree_test.c u32 val = node->val; val 121 lib/rbtree_test.c if (parent->augmented < val) val 122 lib/rbtree_test.c parent->augmented = val; val 131 lib/rbtree_test.c node->augmented = val; val 154 lib/rbtree_test.c nodes[i].val = prandom_u32_state(&rnd); val 225 lib/rbtree_test.c u32 subtree, max = node->val; val 66 lib/refcount.c unsigned int new, val = atomic_read(&r->refs); val 69 lib/refcount.c if (!val) val 72 lib/refcount.c if (unlikely(val == UINT_MAX)) val 75 lib/refcount.c new = val + i; val 76 lib/refcount.c if (new < val) val 79 lib/refcount.c } while (!atomic_try_cmpxchg_relaxed(&r->refs, &val, new)); val 123 lib/refcount.c unsigned int new, val = atomic_read(&r->refs); val 126 lib/refcount.c new = val + 1; val 128 lib/refcount.c if (!val) val 134 lib/refcount.c } while (!atomic_try_cmpxchg_relaxed(&r->refs, &val, new)); val 182 lib/refcount.c unsigned int new, val = atomic_read(&r->refs); val 185 lib/refcount.c if (unlikely(val == UINT_MAX)) val 188 lib/refcount.c new = val - i; val 189 lib/refcount.c if (new > val) { val 190 lib/refcount.c WARN_ONCE(new > val, "refcount_t: underflow; use-after-free.\n"); val 194 lib/refcount.c } while (!atomic_try_cmpxchg_release(&r->refs, &val, new)); val 258 lib/refcount.c int val = 1; val 260 lib/refcount.c return atomic_try_cmpxchg_release(&r->refs, &val, 0); val 277 lib/refcount.c unsigned int new, val = atomic_read(&r->refs); val 280 lib/refcount.c if (unlikely(val == UINT_MAX)) val 283 lib/refcount.c if (val == 1) val 286 lib/refcount.c new = val - 1; val 287 lib/refcount.c if (new > val) { val 288 lib/refcount.c WARN_ONCE(new > val, "refcount_t: underflow; use-after-free.\n"); val 292 lib/refcount.c } while (!atomic_try_cmpxchg_release(&r->refs, &val, new)); val 17 lib/sbitmap.c unsigned long mask, val; val 35 lib/sbitmap.c val = sb->map[index].word; val 36 lib/sbitmap.c } while (cmpxchg(&sb->map[index].word, val, val & ~mask) != val); val 38 lib/sha1.c #define setW(x, val) (*(volatile __u32 *)&W(x) = (val)) val 40 lib/sha1.c #define setW(x, val) do { W(x) = (val); __asm__("":::"memory"); } while (0) val 42 lib/sha1.c #define setW(x, val) (W(x) = (val)) val 316 lib/test_firmware.c bool val; val 319 lib/test_firmware.c val = config; val 322 lib/test_firmware.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 327 lib/test_firmware.c int val; val 330 lib/test_firmware.c val = cfg; val 333 lib/test_firmware.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 358 lib/test_firmware.c u8 val; val 361 lib/test_firmware.c val = cfg; val 364 lib/test_firmware.c return snprintf(buf, PAGE_SIZE, "%u\n", val); val 960 lib/test_kmod.c int val; val 963 lib/test_kmod.c val = config; val 966 lib/test_kmod.c return snprintf(buf, PAGE_SIZE, "%d\n", val); val 973 lib/test_kmod.c unsigned int val; val 976 lib/test_kmod.c val = config; val 979 lib/test_kmod.c return snprintf(buf, PAGE_SIZE, "%u\n", val); val 173 lib/test_printf.c char val = -16; val 174 lib/test_printf.c test("0xfffffff0|0xf0|0xf0", "%#02x|%#02x|%#02x", val, val & 0xff, (u8)val); val 89 lib/test_rhashtable.c const struct test_obj_val *val = arg->key; val 91 lib/test_rhashtable.c return test_obj->value.id - val->id; val 10 lib/test_ubsan.c volatile int val = INT_MAX; val 12 lib/test_ubsan.c val += 2; val 17 lib/test_ubsan.c volatile int val = INT_MIN; val 20 lib/test_ubsan.c val -= val2; val 25 lib/test_ubsan.c volatile int val = INT_MAX / 2; val 27 lib/test_ubsan.c val *= 3; val 32 lib/test_ubsan.c volatile int val = INT_MIN; val 34 lib/test_ubsan.c val = -val; val 39 lib/test_ubsan.c volatile int val = 16; val 42 lib/test_ubsan.c val /= val2; val 47 lib/test_ubsan.c volatile int val = -1; val 50 lib/test_ubsan.c val2 <<= val; val 64 lib/test_ubsan.c bool val, val2, *ptr; val 67 lib/test_ubsan.c dst = (char *)&val; val 72 lib/test_ubsan.c val2 = val; val 78 lib/test_ubsan.c int val; val 80 lib/test_ubsan.c val = *ptr; val 86 lib/test_ubsan.c volatile int *ptr, val = 6; val 89 lib/test_ubsan.c *ptr = val; val 95 lib/test_ubsan.c volatile int val __aligned(8) = 4; val 98 lib/test_ubsan.c ptr = (long long *)&val; val 86 lib/ubsan.c static s_max get_signed_val(struct type_descriptor *type, void *val) val 90 lib/ubsan.c unsigned long ulong_val = (unsigned long)val; val 96 lib/ubsan.c return *(s64 *)val; val 98 lib/ubsan.c return *(s_max *)val; val 101 lib/ubsan.c static bool val_is_negative(struct type_descriptor *type, void *val) val 103 lib/ubsan.c return type_is_signed(type) && get_signed_val(type, val) < 0; val 106 lib/ubsan.c static u_max get_unsigned_val(struct type_descriptor *type, void *val) val 109 lib/ubsan.c return (unsigned long)val; val 112 lib/ubsan.c return *(u64 *)val; val 114 lib/ubsan.c return *(u_max *)val; val 123 lib/ubsan.c u_max val = get_unsigned_val(type, value); val 126 lib/ubsan.c (u32)(val >> 96), val 127 lib/ubsan.c (u32)(val >> 64), val 128 lib/ubsan.c (u32)(val >> 32), val 129 lib/ubsan.c (u32)(val)); val 407 lib/ubsan.c void *val) val 416 lib/ubsan.c val_to_string(val_str, sizeof(val_str), data->type, val); val 52 lib/usercopy.c unsigned long val; val 64 lib/usercopy.c unsafe_get_user(val, (unsigned long __user *) from, err_fault); val 66 lib/usercopy.c val &= ~aligned_byte_mask(align); val 69 lib/usercopy.c if (unlikely(val)) val 75 lib/usercopy.c unsafe_get_user(val, (unsigned long __user *) from, err_fault); val 79 lib/usercopy.c val &= aligned_byte_mask(size); val 83 lib/usercopy.c return (val == 0); val 1142 lib/vsprintf.c u32 chunkmask, val; val 1148 lib/vsprintf.c val = (bitmap[word] >> bit) & chunkmask; val 1158 lib/vsprintf.c buf = number(buf, end, val, spec); val 3142 lib/vsprintf.c } val; val 3346 lib/vsprintf.c val.s = qualifier != 'L' ? val 3350 lib/vsprintf.c val.u = qualifier != 'L' ? val 3359 lib/vsprintf.c val.s = div_s64(val.s, base); val 3361 lib/vsprintf.c val.u = div_u64(val.u, base); val 3369 lib/vsprintf.c *va_arg(args, signed char *) = val.s; val 3371 lib/vsprintf.c *va_arg(args, unsigned char *) = val.u; val 3375 lib/vsprintf.c *va_arg(args, short *) = val.s; val 3377 lib/vsprintf.c *va_arg(args, unsigned short *) = val.u; val 3381 lib/vsprintf.c *va_arg(args, long *) = val.s; val 3383 lib/vsprintf.c *va_arg(args, unsigned long *) = val.u; val 3387 lib/vsprintf.c *va_arg(args, long long *) = val.s; val 3389 lib/vsprintf.c *va_arg(args, unsigned long long *) = val.u; val 3392 lib/vsprintf.c *va_arg(args, size_t *) = val.u; val 3396 lib/vsprintf.c *va_arg(args, int *) = val.s; val 3398 lib/vsprintf.c *va_arg(args, unsigned int *) = val.u; val 30 lib/win_minmax.c const struct minmax_sample *val) val 32 lib/win_minmax.c u32 dt = val->t - m->s[0].t; val 44 lib/win_minmax.c m->s[2] = *val; val 45 lib/win_minmax.c if (unlikely(val->t - m->s[0].t > win)) { val 48 lib/win_minmax.c m->s[2] = *val; val 55 lib/win_minmax.c m->s[2] = m->s[1] = *val; val 61 lib/win_minmax.c m->s[2] = *val; val 69 lib/win_minmax.c struct minmax_sample val = { .t = t, .v = meas }; val 71 lib/win_minmax.c if (unlikely(val.v >= m->s[0].v) || /* found new max? */ val 72 lib/win_minmax.c unlikely(val.t - m->s[2].t > win)) /* nothing left in window? */ val 75 lib/win_minmax.c if (unlikely(val.v >= m->s[1].v)) val 76 lib/win_minmax.c m->s[2] = m->s[1] = val; val 77 lib/win_minmax.c else if (unlikely(val.v >= m->s[2].v)) val 78 lib/win_minmax.c m->s[2] = val; val 80 lib/win_minmax.c return minmax_subwin_update(m, win, &val); val 87 lib/win_minmax.c struct minmax_sample val = { .t = t, .v = meas }; val 89 lib/win_minmax.c if (unlikely(val.v <= m->s[0].v) || /* found new min? */ val 90 lib/win_minmax.c unlikely(val.t - m->s[2].t > win)) /* nothing left in window? */ val 93 lib/win_minmax.c if (unlikely(val.v <= m->s[1].v)) val 94 lib/win_minmax.c m->s[2] = m->s[1] = val; val 95 lib/win_minmax.c else if (unlikely(val.v <= m->s[2].v)) val 96 lib/win_minmax.c m->s[2] = val; val 98 lib/win_minmax.c return minmax_subwin_update(m, win, &val); val 164 lib/xxhash.c static uint64_t xxh64_merge_round(uint64_t acc, uint64_t val) val 166 lib/xxhash.c val = xxh64_round(0, val); val 167 lib/xxhash.c acc ^= val; val 208 lib/zlib_deflate/deftree.c int val = value;\ val 209 lib/zlib_deflate/deftree.c s->bi_buf |= (val << s->bi_valid);\ val 211 lib/zlib_deflate/deftree.c s->bi_buf = (ush)val >> (Buf_size - s->bi_valid);\ val 153 lib/zlib_inflate/inffast.c PUP(out) = (unsigned char)(this.val); val 156 lib/zlib_inflate/inffast.c len = (unsigned)(this.val); val 180 lib/zlib_inflate/inffast.c dist = (unsigned)(this.val); val 308 lib/zlib_inflate/inffast.c this = dcode[this.val + (hold & ((1U << op) - 1))]; val 318 lib/zlib_inflate/inffast.c this = lcode[this.val + (hold & ((1U << op) - 1))]; val 497 lib/zlib_inflate/inflate.c if (this.val < 16) { val 500 lib/zlib_inflate/inflate.c state->lens[state->have++] = this.val; val 503 lib/zlib_inflate/inflate.c if (this.val == 16) { val 515 lib/zlib_inflate/inflate.c else if (this.val == 17) { val 579 lib/zlib_inflate/inflate.c this = state->lencode[last.val + val 587 lib/zlib_inflate/inflate.c state->length = (unsigned)this.val; val 621 lib/zlib_inflate/inflate.c this = state->distcode[last.val + val 634 lib/zlib_inflate/inflate.c state->offset = (unsigned)this.val; val 106 lib/zlib_inflate/inftrees.c this.val = (unsigned short)0; val 207 lib/zlib_inflate/inftrees.c this.val = work[sym]; val 211 lib/zlib_inflate/inftrees.c this.val = base[work[sym]]; val 215 lib/zlib_inflate/inftrees.c this.val = 0; val 273 lib/zlib_inflate/inftrees.c (*table)[low].val = (unsigned short)(next - *table); val 286 lib/zlib_inflate/inftrees.c this.val = (unsigned short)0; val 30 lib/zlib_inflate/inftrees.h unsigned short val; /* offset in table or code value */ val 148 lib/zstd/bitstream.h ZSTD_STATIC unsigned BIT_highbit32(register U32 val) { return 31 - __builtin_clz(val); } val 150 lib/zstd/compress.c #define CLAMPCHECK(val, min, max) \ val 152 lib/zstd/compress.c if ((val < min) | (val > max)) \ val 890 lib/zstd/compress.c static unsigned ZSTD_NbCommonBytes(register size_t val) val 894 lib/zstd/compress.c return (__builtin_ctzll((U64)val) >> 3); val 896 lib/zstd/compress.c return (__builtin_ctz((U32)val) >> 3); val 900 lib/zstd/compress.c return (__builtin_clzll(val) >> 3); val 902 lib/zstd/compress.c return (__builtin_clz((U32)val) >> 3); val 145 lib/zstd/huf_compress.c U16 val; val 276 lib/zstd/huf_compress.c CTable[n].val = valPerRank[CTable[n].nbBits]++; val 495 lib/zstd/huf_compress.c tree[n].val = valPerRank[tree[n].nbBits]++; /* assign value within rank, symbol order */ val 523 lib/zstd/huf_compress.c BIT_addBitsFast(bitCPtr, CTable[symbol].val, CTable[symbol].nbBits); val 160 lib/zstd/huf_decompress.c size_t const val = BIT_lookBitsFast(Dstream, dtLog); /* note : dtLog >= 1 */ val 161 lib/zstd/huf_decompress.c BYTE const c = dt[val].byte; val 162 lib/zstd/huf_decompress.c BIT_skipBits(Dstream, dt[val].nbBits); val 597 lib/zstd/huf_decompress.c size_t const val = BIT_lookBitsFast(DStream, dtLog); /* note : dtLog >= 1 */ val 598 lib/zstd/huf_decompress.c memcpy(op, dt + val, 2); val 599 lib/zstd/huf_decompress.c BIT_skipBits(DStream, dt[val].nbBits); val 600 lib/zstd/huf_decompress.c return dt[val].length; val 605 lib/zstd/huf_decompress.c size_t const val = BIT_lookBitsFast(DStream, dtLog); /* note : dtLog >= 1 */ val 606 lib/zstd/huf_decompress.c memcpy(op, dt + val, 1); val 607 lib/zstd/huf_decompress.c if (dt[val].length == 1) val 608 lib/zstd/huf_decompress.c BIT_skipBits(DStream, dt[val].nbBits); val 611 lib/zstd/huf_decompress.c BIT_skipBits(DStream, dt[val].nbBits); val 77 lib/zstd/mem.h ZSTD_STATIC void ZSTD_writeLE16(void *memPtr, U16 val) { put_unaligned_le16(val, memPtr); } val 81 lib/zstd/mem.h ZSTD_STATIC void ZSTD_writeLE24(void *memPtr, U32 val) val 83 lib/zstd/mem.h ZSTD_writeLE16(memPtr, (U16)val); val 84 lib/zstd/mem.h ((BYTE *)memPtr)[2] = (BYTE)(val >> 16); val 103 lib/zstd/mem.h ZSTD_STATIC void ZSTD_writeLEST(void *memPtr, size_t val) val 106 lib/zstd/mem.h ZSTD_writeLE32(memPtr, (U32)val); val 108 lib/zstd/mem.h ZSTD_writeLE64(memPtr, (U64)val); val 129 lib/zstd/mem.h ZSTD_STATIC void ZSTD_writeBEST(void *memPtr, size_t val) val 132 lib/zstd/mem.h ZSTD_writeBE32(memPtr, (U32)val); val 134 lib/zstd/mem.h ZSTD_writeBE64(memPtr, (U64)val); val 246 lib/zstd/zstd_internal.h ZSTD_STATIC U32 ZSTD_highbit32(U32 val) { return 31 - __builtin_clz(val); } val 24 mm/cma_debug.c static int cma_debugfs_get(void *data, u64 *val) val 28 mm/cma_debug.c *val = *p; val 34 mm/cma_debug.c static int cma_used_get(void *data, u64 *val) val 43 mm/cma_debug.c *val = (u64)used << cma->order_per_bit; val 49 mm/cma_debug.c static int cma_maxchunk_get(void *data, u64 *val) val 65 mm/cma_debug.c *val = (u64)maxchunk << cma->order_per_bit; val 122 mm/cma_debug.c static int cma_free_write(void *data, u64 val) val 124 mm/cma_debug.c int pages = val; val 154 mm/cma_debug.c static int cma_alloc_write(void *data, u64 val) val 156 mm/cma_debug.c int pages = val; val 248 mm/frontswap.c swp_entry_t entry = { .val = page_private(page), }; val 297 mm/frontswap.c swp_entry_t entry = { .val = page_private(page), }; val 2514 mm/huge_memory.c swp_entry_t entry = { .val = page_private(head) }; val 2803 mm/huge_memory.c swp_entry_t entry = { .val = page_private(head) }; val 2967 mm/huge_memory.c static int split_huge_pages_set(void *data, u64 val) val 2974 mm/huge_memory.c if (val != 1) val 30 mm/hugetlb_cgroup.c #define MEMFILE_PRIVATE(x, val) (((x) << 16) | (val)) val 31 mm/hugetlb_cgroup.c #define MEMFILE_IDX(val) (((val) >> 16) & 0xffff) val 32 mm/hugetlb_cgroup.c #define MEMFILE_ATTR(val) ((val) & 0xffff) val 14 mm/hwpoison-inject.c static int hwpoison_inject(void *data, u64 val) val 16 mm/hwpoison-inject.c unsigned long pfn = val; val 62 mm/hwpoison-inject.c static int hwpoison_unpoison(void *data, u64 val) val 67 mm/hwpoison-inject.c return unpoison_memory(val); val 228 mm/memcontrol.c #define MEMFILE_PRIVATE(x, val) ((x) << 16 | (val)) val 229 mm/memcontrol.c #define MEMFILE_TYPE(val) ((val) >> 16 & 0xffff) val 230 mm/memcontrol.c #define MEMFILE_ATTR(val) ((val) & 0xffff) val 691 mm/memcontrol.c void __mod_memcg_state(struct mem_cgroup *memcg, int idx, int val) val 698 mm/memcontrol.c x = val + __this_cpu_read(memcg->vmstats_percpu->stat[idx]); val 736 mm/memcontrol.c int val) val 744 mm/memcontrol.c __mod_node_page_state(pgdat, idx, val); val 753 mm/memcontrol.c __mod_memcg_state(memcg, idx, val); val 756 mm/memcontrol.c __this_cpu_add(pn->lruvec_stat_local->count[idx], val); val 758 mm/memcontrol.c x = val + __this_cpu_read(pn->lruvec_stat_cpu->count[idx]); val 769 mm/memcontrol.c void __mod_lruvec_slab_state(void *p, enum node_stat_item idx, int val) val 781 mm/memcontrol.c __mod_node_page_state(pgdat, idx, val); val 784 mm/memcontrol.c __mod_lruvec_state(lruvec, idx, val); val 789 mm/memcontrol.c void mod_memcg_obj_state(void *p, int idx, int val) val 796 mm/memcontrol.c mod_memcg_state(memcg, idx, val); val 880 mm/memcontrol.c unsigned long val, next; val 882 mm/memcontrol.c val = __this_cpu_read(memcg->vmstats_percpu->nr_page_events); val 885 mm/memcontrol.c if ((long)(next - val) < 0) { val 888 mm/memcontrol.c next = val + THRESHOLDS_EVENTS_TARGET; val 891 mm/memcontrol.c next = val + SOFTLIMIT_EVENTS_TARGET; val 894 mm/memcontrol.c next = val + NUMAINFO_EVENTS_TARGET; val 3375 mm/memcontrol.c struct cftype *cft, u64 val) val 3381 mm/memcontrol.c if (memcg->use_hierarchy == val) val 3393 mm/memcontrol.c (val == 1 || val == 0)) { val 3395 mm/memcontrol.c memcg->use_hierarchy = val; val 3406 mm/memcontrol.c unsigned long val; val 3409 mm/memcontrol.c val = memcg_page_state(memcg, MEMCG_CACHE) + val 3412 mm/memcontrol.c val += memcg_page_state(memcg, MEMCG_SWAP); val 3415 mm/memcontrol.c val = page_counter_read(&memcg->memory); val 3417 mm/memcontrol.c val = page_counter_read(&memcg->memsw); val 3419 mm/memcontrol.c return val; val 3767 mm/memcontrol.c struct cftype *cft, u64 val) val 3771 mm/memcontrol.c if (val & ~MOVE_MASK) val 3780 mm/memcontrol.c memcg->move_charge_at_immigrate = val; val 3785 mm/memcontrol.c struct cftype *cft, u64 val) val 4007 mm/memcontrol.c struct cftype *cft, u64 val) val 4011 mm/memcontrol.c if (val > 100) val 4015 mm/memcontrol.c memcg->swappiness = val; val 4017 mm/memcontrol.c vm_swappiness = val; val 4360 mm/memcontrol.c struct cftype *cft, u64 val) val 4365 mm/memcontrol.c if (!css->parent || !((val == 0) || (val == 1))) val 4368 mm/memcontrol.c memcg->oom_kill_disable = val; val 4369 mm/memcontrol.c if (!val) val 5424 mm/memcontrol.c entry->val = ent.val; val 5599 mm/memcontrol.c swp_entry_t ent = { .val = 0 }; val 5608 mm/memcontrol.c if (!page && !ent.val) val 5630 mm/memcontrol.c if (ent.val && !ret && (!page || !PageTransCompound(page)) && val 6537 mm/memcontrol.c swp_entry_t ent = { .val = page_private(page), }; val 6615 mm/memcontrol.c swp_entry_t entry = { .val = page_private(page) }; val 7116 mm/memcontrol.c if (!entry.val) { val 159 mm/memory.c static void add_mm_counter_fast(struct mm_struct *mm, int member, int val) val 164 mm/memory.c task->rss_stat.count[member] += val; val 166 mm/memory.c add_mm_counter(mm, member, val); val 692 mm/memory.c return entry.val; val 823 mm/memory.c entry.val = copy_one_pte(dst_mm, src_mm, dst_pte, src_pte, val 825 mm/memory.c if (entry.val) val 837 mm/memory.c if (entry.val) { val 2798 mm/memory.c set_page_private(page, entry.val); val 2850 mm/memory.c page_private(page) != entry.val)) && swapcache) val 3378 mm/memory.c static int fault_around_bytes_get(void *data, u64 *val) val 3380 mm/memory.c *val = fault_around_bytes; val 3388 mm/memory.c static int fault_around_bytes_set(void *data, u64 val) val 3390 mm/memory.c if (val / PAGE_SIZE > PTRS_PER_PTE) val 3392 mm/memory.c if (val > PAGE_SIZE) val 3393 mm/memory.c fault_around_bytes = rounddown_pow_of_two(val); val 2509 mm/mmap.c unsigned long val; val 2512 mm/mmap.c val = simple_strtoul(p, &endptr, 10); val 2514 mm/mmap.c stack_guard_gap = val << PAGE_SHIFT; val 5144 mm/page_alloc.c void si_meminfo(struct sysinfo *val) val 5146 mm/page_alloc.c val->totalram = totalram_pages(); val 5147 mm/page_alloc.c val->sharedram = global_node_page_state(NR_SHMEM); val 5148 mm/page_alloc.c val->freeram = global_zone_page_state(NR_FREE_PAGES); val 5149 mm/page_alloc.c val->bufferram = nr_blockdev_pages(); val 5150 mm/page_alloc.c val->totalhigh = totalhigh_pages(); val 5151 mm/page_alloc.c val->freehigh = nr_free_highpages(); val 5152 mm/page_alloc.c val->mem_unit = PAGE_SIZE; val 5158 mm/page_alloc.c void si_meminfo_node(struct sysinfo *val, int nid) val 5168 mm/page_alloc.c val->totalram = managed_pages; val 5169 mm/page_alloc.c val->sharedram = node_page_state(pgdat, NR_SHMEM); val 5170 mm/page_alloc.c val->freeram = sum_zone_node_page_state(nid, NR_FREE_PAGES); val 5180 mm/page_alloc.c val->totalhigh = managed_highpages; val 5181 mm/page_alloc.c val->freehigh = free_highpages; val 5183 mm/page_alloc.c val->totalhigh = managed_highpages; val 5184 mm/page_alloc.c val->freehigh = free_highpages; val 5186 mm/page_alloc.c val->mem_unit = PAGE_SIZE; val 5537 mm/page_alloc.c int n, val; val 5555 mm/page_alloc.c val = node_distance(node, n); val 5558 mm/page_alloc.c val += (n < node); val 5563 mm/page_alloc.c val += PENALTY_FOR_NODE_WITH_CPUS; val 5566 mm/page_alloc.c val *= (MAX_NODE_LOAD*MAX_NUMNODES); val 5567 mm/page_alloc.c val += node_load[n]; val 5569 mm/page_alloc.c if (val < min_val) { val 5570 mm/page_alloc.c min_val = val; val 108 mm/page_io.c entry.val = page_private(page); val 1580 mm/rmap.c swp_entry_t entry = { .val = page_private(subpage) }; val 1357 mm/shmem.c if (!swap.val) val 1563 mm/shmem.c entry.val = page_private(oldpage); val 1583 mm/shmem.c set_page_private(newpage, entry.val); val 1662 mm/shmem.c if (!PageSwapCache(page) || page_private(page) != swap.val || val 42 mm/shuffle.c static __meminit int shuffle_store(const char *val, val 45 mm/shuffle.c int rc = param_set_bool(val, kp); val 1440 mm/slab.c static void poison_obj(struct kmem_cache *cachep, void *addr, unsigned char val) val 1445 mm/slab.c memset(addr, val, size); val 2326 mm/slab.c unsigned int idx, freelist_idx_t val) val 2328 mm/slab.c ((freelist_idx_t *)(page->freelist))[idx] = val; val 710 mm/slub.c static void init_object(struct kmem_cache *s, void *object, u8 val) val 715 mm/slub.c memset(p - s->red_left_pad, val, s->red_left_pad); val 723 mm/slub.c memset(p + s->object_size, val, s->inuse - s->object_size); val 855 mm/slub.c void *object, u8 val) val 862 mm/slub.c object - s->red_left_pad, val, s->red_left_pad)) val 866 mm/slub.c endobject, val, s->inuse - s->object_size)) val 877 mm/slub.c if (val != SLUB_RED_ACTIVE && (s->flags & __OBJECT_POISON) && val 889 mm/slub.c if (!s->offset && val == SLUB_RED_ACTIVE) val 1358 mm/slub.c void *object, u8 val) { return 1; } val 315 mm/swap_slots.c entry.val = 0; val 341 mm/swap_slots.c pentry->val = 0; val 349 mm/swap_slots.c if (entry.val) val 357 mm/swap_slots.c entry.val = 0; val 135 mm/swap_state.c set_page_private(page + i, entry.val + i); val 197 mm/swap_state.c if (!entry.val) val 246 mm/swap_state.c swp_entry_t entry = { .val = page_private(page) }; val 1109 mm/swapfile.c if (!entry.val) val 1122 mm/swapfile.c pr_err("swap_info_get: %s%08lx\n", Bad_offset, entry.val); val 1125 mm/swapfile.c pr_err("swap_info_get: %s%08lx\n", Unused_file, entry.val); val 1128 mm/swapfile.c pr_err("swap_info_get: %s%08lx\n", Bad_file, entry.val); val 1145 mm/swapfile.c pr_err("swap_info_get: %s%08lx\n", Unused_offset, entry.val); val 1254 mm/swapfile.c if (!entry.val) val 1269 mm/swapfile.c pr_err("%s: %s%08lx\n", __func__, Bad_file, entry.val); val 1333 mm/swapfile.c unsigned char val; val 1345 mm/swapfile.c val = map[i]; val 1346 mm/swapfile.c VM_BUG_ON(!(val & SWAP_HAS_CACHE)); val 1347 mm/swapfile.c if (val == SWAP_HAS_CACHE) val 1360 mm/swapfile.c for (i = 0; i < size; i++, entry.val++) { val 1437 mm/swapfile.c entry.val = page_private(page); val 1574 mm/swapfile.c entry.val = page_private(page); val 1609 mm/swapfile.c entry.val = page_private(page); val 1676 mm/swapfile.c entry.val = page_private(page); val 2277 mm/swapfile.c entry.val = page_private(page); val 3349 mm/swapfile.c void si_swapinfo(struct sysinfo *val) val 3361 mm/swapfile.c val->freeswap = atomic_long_read(&nr_swap_pages) + nr_to_be_unused; val 3362 mm/swapfile.c val->totalswap = total_swap_pages + nr_to_be_unused; val 3486 mm/swapfile.c swp_entry_t entry = { .val = page_private(page) }; val 3501 mm/swapfile.c swp_entry_t swap = { .val = page_private(page) }; val 679 mm/util.c entry.val = page_private(page); val 946 mm/vmscan.c swp_entry_t swap = { .val = page_private(page) }; val 1761 mm/vmstat.c long val; val 1781 mm/vmstat.c val = atomic_long_read(&vm_zone_stat[i]); val 1782 mm/vmstat.c if (val < 0) { val 1784 mm/vmstat.c __func__, vmstat_text[i], val); val 1790 mm/vmstat.c val = atomic_long_read(&vm_numa_stat[i]); val 1791 mm/vmstat.c if (val < 0) { val 1793 mm/vmstat.c __func__, vmstat_text[i + NR_VM_ZONE_STAT_ITEMS], val); val 481 mm/zsmalloc.c static inline void mod_zspage_inuse(struct zspage *zspage, int val) val 483 mm/zsmalloc.c zspage->inuse += val; val 666 mm/zswap.c static int __zswap_param_set(const char *val, const struct kernel_param *kp, val 670 mm/zswap.c char *s = strstrip((char *)val); val 761 mm/zswap.c static int zswap_compressor_param_set(const char *val, val 764 mm/zswap.c return __zswap_param_set(val, kp, zswap_zpool_type, NULL); val 767 mm/zswap.c static int zswap_zpool_param_set(const char *val, val 770 mm/zswap.c return __zswap_param_set(val, kp, NULL, zswap_compressor); val 773 mm/zswap.c static int zswap_enabled_param_set(const char *val, val 785 mm/zswap.c return param_set_bool(val, kp); val 17 net/6lowpan/debugfs.c static int lowpan_ctx_flag_active_set(void *data, u64 val) val 21 net/6lowpan/debugfs.c if (val != 0 && val != 1) val 24 net/6lowpan/debugfs.c if (val) val 32 net/6lowpan/debugfs.c static int lowpan_ctx_flag_active_get(void *data, u64 *val) val 34 net/6lowpan/debugfs.c *val = lowpan_iphc_ctx_is_active(data); val 42 net/6lowpan/debugfs.c static int lowpan_ctx_flag_c_set(void *data, u64 val) val 46 net/6lowpan/debugfs.c if (val != 0 && val != 1) val 49 net/6lowpan/debugfs.c if (val) val 57 net/6lowpan/debugfs.c static int lowpan_ctx_flag_c_get(void *data, u64 *val) val 59 net/6lowpan/debugfs.c *val = lowpan_iphc_ctx_is_compression(data); val 66 net/6lowpan/debugfs.c static int lowpan_ctx_plen_set(void *data, u64 val) val 72 net/6lowpan/debugfs.c if (val > 128) val 76 net/6lowpan/debugfs.c ctx->plen = val; val 82 net/6lowpan/debugfs.c static int lowpan_ctx_plen_get(void *data, u64 *val) val 89 net/6lowpan/debugfs.c *val = ctx->plen; val 215 net/6lowpan/debugfs.c static int lowpan_short_addr_get(void *data, u64 *val) val 220 net/6lowpan/debugfs.c *val = le16_to_cpu(wdev->short_addr); val 546 net/6lowpan/iphc.c u8 val) val 551 net/6lowpan/iphc.c switch (val) { val 1020 net/6lowpan/iphc.c u8 tc = lowpan_iphc_get_tc(hdr), tf[4], val; val 1028 net/6lowpan/iphc.c val = LOWPAN_IPHC_TF_11; val 1038 net/6lowpan/iphc.c val = LOWPAN_IPHC_TF_10; val 1058 net/6lowpan/iphc.c val = LOWPAN_IPHC_TF_01; val 1078 net/6lowpan/iphc.c val = LOWPAN_IPHC_TF_00; val 1082 net/6lowpan/iphc.c return val; val 1103 net/6lowpan/iphc.c u8 val; val 1109 net/6lowpan/iphc.c val = LOWPAN_IPHC_DAM_11; val 1115 net/6lowpan/iphc.c val = LOWPAN_IPHC_DAM_10; val 1121 net/6lowpan/iphc.c val = LOWPAN_IPHC_DAM_01; val 1125 net/6lowpan/iphc.c val = LOWPAN_IPHC_DAM_00; val 1128 net/6lowpan/iphc.c return val; val 39 net/6lowpan/nhc_udp.c u8 tmp = 0, val = 0; val 54 net/6lowpan/nhc_udp.c fail |= lowpan_fetch_skb(skb, &val, sizeof(val)); val 55 net/6lowpan/nhc_udp.c uh.dest = htons(val + LOWPAN_NHC_UDP_8BIT_PORT); val 58 net/6lowpan/nhc_udp.c fail |= lowpan_fetch_skb(skb, &val, sizeof(val)); val 59 net/6lowpan/nhc_udp.c uh.source = htons(val + LOWPAN_NHC_UDP_8BIT_PORT); val 63 net/6lowpan/nhc_udp.c fail |= lowpan_fetch_skb(skb, &val, sizeof(val)); val 64 net/6lowpan/nhc_udp.c uh.source = htons(LOWPAN_NHC_UDP_4BIT_PORT + (val >> 4)); val 65 net/6lowpan/nhc_udp.c uh.dest = htons(LOWPAN_NHC_UDP_4BIT_PORT + (val & 0x0f)); val 32 net/9p/error.c int val; val 217 net/9p/error.c errno = c->val; val 101 net/9p/protocol.c int8_t *val = va_arg(ap, int8_t *); val 102 net/9p/protocol.c if (pdu_read(pdu, val, sizeof(*val))) { val 109 net/9p/protocol.c int16_t *val = va_arg(ap, int16_t *); val 115 net/9p/protocol.c *val = le16_to_cpu(le_val); val 119 net/9p/protocol.c int32_t *val = va_arg(ap, int32_t *); val 125 net/9p/protocol.c *val = le32_to_cpu(le_val); val 129 net/9p/protocol.c int64_t *val = va_arg(ap, int64_t *); val 135 net/9p/protocol.c *val = le64_to_cpu(le_val); val 360 net/9p/protocol.c int8_t val = va_arg(ap, int); val 361 net/9p/protocol.c if (pdu_write(pdu, &val, sizeof(val))) val 366 net/9p/protocol.c __le16 val = cpu_to_le16(va_arg(ap, int)); val 367 net/9p/protocol.c if (pdu_write(pdu, &val, sizeof(val))) val 372 net/9p/protocol.c __le32 val = cpu_to_le32(va_arg(ap, int32_t)); val 373 net/9p/protocol.c if (pdu_write(pdu, &val, sizeof(val))) val 378 net/9p/protocol.c __le64 val = cpu_to_le64(va_arg(ap, int64_t)); val 379 net/9p/protocol.c if (pdu_write(pdu, &val, sizeof(val))) val 398 net/9p/protocol.c __le32 val = cpu_to_le32( val 400 net/9p/protocol.c if (pdu_write(pdu, &val, sizeof(val))) val 405 net/9p/protocol.c __le32 val = cpu_to_le32( val 407 net/9p/protocol.c if (pdu_write(pdu, &val, sizeof(val))) val 689 net/ax25/af_ax25.c int val = 0; val 701 net/ax25/af_ax25.c valptr = (void *) &val; val 709 net/ax25/af_ax25.c val = ax25->window; val 713 net/ax25/af_ax25.c val = ax25->t1 / HZ; val 717 net/ax25/af_ax25.c val = ax25->t2 / HZ; val 721 net/ax25/af_ax25.c val = ax25->n2; val 725 net/ax25/af_ax25.c val = ax25->t3 / HZ; val 729 net/ax25/af_ax25.c val = ax25->idle / (60 * HZ); val 733 net/ax25/af_ax25.c val = ax25->backoff; val 737 net/ax25/af_ax25.c val = (ax25->modulus == AX25_EMODULUS); val 741 net/ax25/af_ax25.c val = ax25->pidincl; val 745 net/ax25/af_ax25.c val = ax25->iamdigi; val 749 net/ax25/af_ax25.c val = ax25->paclen; val 136 net/batman-adv/bat_algo.c static int batadv_param_set_ra(const char *val, const struct kernel_param *kp) val 139 net/batman-adv/bat_algo.c char *algo_name = (char *)val; val 1083 net/bluetooth/6lowpan.c static int lowpan_enable_set(void *data, u64 val) val 1091 net/bluetooth/6lowpan.c set_enable->flag = !!val; val 1099 net/bluetooth/6lowpan.c static int lowpan_enable_get(void *data, u64 *val) val 1101 net/bluetooth/6lowpan.c *val = enable_6lowpan; val 196 net/bluetooth/amp.c memcpy(&keybuf[0], key->val, HCI_LINK_KEY_SIZE); val 197 net/bluetooth/amp.c memcpy(&keybuf[HCI_LINK_KEY_SIZE], key->val, HCI_LINK_KEY_SIZE); val 2411 net/bluetooth/hci_core.c if (smp_irk_matches(hdev, irk->val, rpa)) { val 2445 net/bluetooth/hci_core.c bdaddr_t *bdaddr, u8 *val, u8 type, val 2476 net/bluetooth/hci_core.c memcpy(key->val, val, HCI_LINK_KEY_SIZE); val 2510 net/bluetooth/hci_core.c memcpy(key->val, tk, sizeof(key->val)); val 2521 net/bluetooth/hci_core.c u8 addr_type, u8 val[16], bdaddr_t *rpa) val 2537 net/bluetooth/hci_core.c memcpy(irk->val, val, 16); val 162 net/bluetooth/hci_debugfs.c u8 i, val[16]; val 169 net/bluetooth/hci_debugfs.c val[i] = uuid->uuid[15 - i]; val 171 net/bluetooth/hci_debugfs.c seq_printf(f, "%pUb\n", val); val 199 net/bluetooth/hci_debugfs.c static int conn_info_min_age_set(void *data, u64 val) val 203 net/bluetooth/hci_debugfs.c if (val == 0 || val > hdev->conn_info_max_age) val 207 net/bluetooth/hci_debugfs.c hdev->conn_info_min_age = val; val 213 net/bluetooth/hci_debugfs.c static int conn_info_min_age_get(void *data, u64 *val) val 218 net/bluetooth/hci_debugfs.c *val = hdev->conn_info_min_age; val 227 net/bluetooth/hci_debugfs.c static int conn_info_max_age_set(void *data, u64 val) val 231 net/bluetooth/hci_debugfs.c if (val == 0 || val < hdev->conn_info_min_age) val 235 net/bluetooth/hci_debugfs.c hdev->conn_info_max_age = val; val 241 net/bluetooth/hci_debugfs.c static int conn_info_max_age_get(void *data, u64 *val) val 246 net/bluetooth/hci_debugfs.c *val = hdev->conn_info_max_age; val 371 net/bluetooth/hci_debugfs.c HCI_LINK_KEY_SIZE, key->val, key->pin_len); val 393 net/bluetooth/hci_debugfs.c static int voice_setting_get(void *data, u64 *val) val 398 net/bluetooth/hci_debugfs.c *val = hdev->voice_setting; val 425 net/bluetooth/hci_debugfs.c static int auto_accept_delay_set(void *data, u64 val) val 430 net/bluetooth/hci_debugfs.c hdev->auto_accept_delay = val; val 436 net/bluetooth/hci_debugfs.c static int min_encrypt_key_size_set(void *data, u64 val) val 440 net/bluetooth/hci_debugfs.c if (val < 1 || val > 16) val 444 net/bluetooth/hci_debugfs.c hdev->min_enc_key_size = val; val 450 net/bluetooth/hci_debugfs.c static int min_encrypt_key_size_get(void *data, u64 *val) val 455 net/bluetooth/hci_debugfs.c *val = hdev->min_enc_key_size; val 465 net/bluetooth/hci_debugfs.c static int auto_accept_delay_get(void *data, u64 *val) val 470 net/bluetooth/hci_debugfs.c *val = hdev->auto_accept_delay; val 479 net/bluetooth/hci_debugfs.c static int idle_timeout_set(void *data, u64 val) val 483 net/bluetooth/hci_debugfs.c if (val != 0 && (val < 500 || val > 3600000)) val 487 net/bluetooth/hci_debugfs.c hdev->idle_timeout = val; val 493 net/bluetooth/hci_debugfs.c static int idle_timeout_get(void *data, u64 *val) val 498 net/bluetooth/hci_debugfs.c *val = hdev->idle_timeout; val 507 net/bluetooth/hci_debugfs.c static int sniff_min_interval_set(void *data, u64 val) val 511 net/bluetooth/hci_debugfs.c if (val == 0 || val % 2 || val > hdev->sniff_max_interval) val 515 net/bluetooth/hci_debugfs.c hdev->sniff_min_interval = val; val 521 net/bluetooth/hci_debugfs.c static int sniff_min_interval_get(void *data, u64 *val) val 526 net/bluetooth/hci_debugfs.c *val = hdev->sniff_min_interval; val 535 net/bluetooth/hci_debugfs.c static int sniff_max_interval_set(void *data, u64 val) val 539 net/bluetooth/hci_debugfs.c if (val == 0 || val % 2 || val < hdev->sniff_min_interval) val 543 net/bluetooth/hci_debugfs.c hdev->sniff_max_interval = val; val 549 net/bluetooth/hci_debugfs.c static int sniff_max_interval_get(void *data, u64 *val) val 554 net/bluetooth/hci_debugfs.c *val = hdev->sniff_max_interval; val 613 net/bluetooth/hci_debugfs.c static int rpa_timeout_set(void *data, u64 val) val 620 net/bluetooth/hci_debugfs.c if (val < 30 || val > (60 * 60 * 24)) val 624 net/bluetooth/hci_debugfs.c hdev->rpa_timeout = val; val 630 net/bluetooth/hci_debugfs.c static int rpa_timeout_get(void *data, u64 *val) val 635 net/bluetooth/hci_debugfs.c *val = hdev->rpa_timeout; val 752 net/bluetooth/hci_debugfs.c 16, irk->val, &irk->rpa); val 771 net/bluetooth/hci_debugfs.c __le64_to_cpu(ltk->rand), 16, ltk->val); val 779 net/bluetooth/hci_debugfs.c static int conn_min_interval_set(void *data, u64 val) val 783 net/bluetooth/hci_debugfs.c if (val < 0x0006 || val > 0x0c80 || val > hdev->le_conn_max_interval) val 787 net/bluetooth/hci_debugfs.c hdev->le_conn_min_interval = val; val 793 net/bluetooth/hci_debugfs.c static int conn_min_interval_get(void *data, u64 *val) val 798 net/bluetooth/hci_debugfs.c *val = hdev->le_conn_min_interval; val 807 net/bluetooth/hci_debugfs.c static int conn_max_interval_set(void *data, u64 val) val 811 net/bluetooth/hci_debugfs.c if (val < 0x0006 || val > 0x0c80 || val < hdev->le_conn_min_interval) val 815 net/bluetooth/hci_debugfs.c hdev->le_conn_max_interval = val; val 821 net/bluetooth/hci_debugfs.c static int conn_max_interval_get(void *data, u64 *val) val 826 net/bluetooth/hci_debugfs.c *val = hdev->le_conn_max_interval; val 835 net/bluetooth/hci_debugfs.c static int conn_latency_set(void *data, u64 val) val 839 net/bluetooth/hci_debugfs.c if (val > 0x01f3) val 843 net/bluetooth/hci_debugfs.c hdev->le_conn_latency = val; val 849 net/bluetooth/hci_debugfs.c static int conn_latency_get(void *data, u64 *val) val 854 net/bluetooth/hci_debugfs.c *val = hdev->le_conn_latency; val 863 net/bluetooth/hci_debugfs.c static int supervision_timeout_set(void *data, u64 val) val 867 net/bluetooth/hci_debugfs.c if (val < 0x000a || val > 0x0c80) val 871 net/bluetooth/hci_debugfs.c hdev->le_supv_timeout = val; val 877 net/bluetooth/hci_debugfs.c static int supervision_timeout_get(void *data, u64 *val) val 882 net/bluetooth/hci_debugfs.c *val = hdev->le_supv_timeout; val 891 net/bluetooth/hci_debugfs.c static int adv_channel_map_set(void *data, u64 val) val 895 net/bluetooth/hci_debugfs.c if (val < 0x01 || val > 0x07) val 899 net/bluetooth/hci_debugfs.c hdev->le_adv_channel_map = val; val 905 net/bluetooth/hci_debugfs.c static int adv_channel_map_get(void *data, u64 *val) val 910 net/bluetooth/hci_debugfs.c *val = hdev->le_adv_channel_map; val 919 net/bluetooth/hci_debugfs.c static int adv_min_interval_set(void *data, u64 val) val 923 net/bluetooth/hci_debugfs.c if (val < 0x0020 || val > 0x4000 || val > hdev->le_adv_max_interval) val 927 net/bluetooth/hci_debugfs.c hdev->le_adv_min_interval = val; val 933 net/bluetooth/hci_debugfs.c static int adv_min_interval_get(void *data, u64 *val) val 938 net/bluetooth/hci_debugfs.c *val = hdev->le_adv_min_interval; val 947 net/bluetooth/hci_debugfs.c static int adv_max_interval_set(void *data, u64 val) val 951 net/bluetooth/hci_debugfs.c if (val < 0x0020 || val > 0x4000 || val < hdev->le_adv_min_interval) val 955 net/bluetooth/hci_debugfs.c hdev->le_adv_max_interval = val; val 961 net/bluetooth/hci_debugfs.c static int adv_max_interval_get(void *data, u64 *val) val 966 net/bluetooth/hci_debugfs.c *val = hdev->le_adv_max_interval; val 975 net/bluetooth/hci_debugfs.c static int auth_payload_timeout_set(void *data, u64 val) val 979 net/bluetooth/hci_debugfs.c if (val < 0x0001 || val > 0xffff) val 983 net/bluetooth/hci_debugfs.c hdev->auth_payload_timeout = val; val 989 net/bluetooth/hci_debugfs.c static int auth_payload_timeout_get(void *data, u64 *val) val 994 net/bluetooth/hci_debugfs.c *val = hdev->auth_payload_timeout; val 3917 net/bluetooth/hci_event.c memcpy(cp.link_key, key->val, HCI_LINK_KEY_SIZE); val 5598 net/bluetooth/hci_event.c memcpy(cp.ltk, ltk->val, ltk->enc_size); val 2093 net/bluetooth/hci_request.c u8 val = 0; val 2096 net/bluetooth/hci_request.c val |= uuid->svc_hint; val 2098 net/bluetooth/hci_request.c return val; val 2989 net/bluetooth/l2cap_core.c unsigned long *val) val 3002 net/bluetooth/l2cap_core.c *val = *((u8 *) opt->val); val 3006 net/bluetooth/l2cap_core.c *val = get_unaligned_le16(opt->val); val 3010 net/bluetooth/l2cap_core.c *val = get_unaligned_le32(opt->val); val 3014 net/bluetooth/l2cap_core.c *val = (unsigned long) opt->val; val 3018 net/bluetooth/l2cap_core.c BT_DBG("type 0x%2.2x len %u val 0x%lx", *type, opt->len, *val); val 3022 net/bluetooth/l2cap_core.c static void l2cap_add_conf_opt(void **ptr, u8 type, u8 len, unsigned long val, size_t size) val 3026 net/bluetooth/l2cap_core.c BT_DBG("type 0x%2.2x len %u val 0x%lx", type, len, val); val 3036 net/bluetooth/l2cap_core.c *((u8 *) opt->val) = val; val 3040 net/bluetooth/l2cap_core.c put_unaligned_le16(val, opt->val); val 3044 net/bluetooth/l2cap_core.c put_unaligned_le32(val, opt->val); val 3048 net/bluetooth/l2cap_core.c memcpy(opt->val, (void *) val, len); val 3359 net/bluetooth/l2cap_core.c unsigned long val; val 3370 net/bluetooth/l2cap_core.c len -= l2cap_get_conf_opt(&req, &type, &olen, &val); val 3381 net/bluetooth/l2cap_core.c mtu = val; val 3387 net/bluetooth/l2cap_core.c chan->flush_to = val; val 3396 net/bluetooth/l2cap_core.c memcpy(&rfc, (void *) val, olen); val 3402 net/bluetooth/l2cap_core.c if (val == L2CAP_FCS_NONE) val 3410 net/bluetooth/l2cap_core.c memcpy(&efs, (void *) val, olen); val 3421 net/bluetooth/l2cap_core.c chan->remote_tx_win = val; val 3583 net/bluetooth/l2cap_core.c unsigned long val; val 3590 net/bluetooth/l2cap_core.c len -= l2cap_get_conf_opt(&rsp, &type, &olen, &val); val 3598 net/bluetooth/l2cap_core.c if (val < L2CAP_DEFAULT_MIN_MTU) { val 3602 net/bluetooth/l2cap_core.c chan->imtu = val; val 3610 net/bluetooth/l2cap_core.c chan->flush_to = val; val 3618 net/bluetooth/l2cap_core.c memcpy(&rfc, (void *)val, olen); val 3630 net/bluetooth/l2cap_core.c chan->ack_win = min_t(u16, val, chan->ack_win); val 3638 net/bluetooth/l2cap_core.c memcpy(&efs, (void *)val, olen); val 3651 net/bluetooth/l2cap_core.c if (val == L2CAP_FCS_NONE) val 3758 net/bluetooth/l2cap_core.c unsigned long val; val 3777 net/bluetooth/l2cap_core.c len -= l2cap_get_conf_opt(&rsp, &type, &olen, &val); val 3785 net/bluetooth/l2cap_core.c memcpy(&rfc, (void *)val, olen); val 3790 net/bluetooth/l2cap_core.c txwin_ext = val; val 873 net/bluetooth/mgmt.c if (cp->val == 0x01) val 875 net/bluetooth/mgmt.c else if (cp->val == 0x02) val 898 net/bluetooth/mgmt.c return cp->val; val 1164 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 1176 net/bluetooth/mgmt.c if (!!cp->val == hdev_is_powered(hdev)) { val 1187 net/bluetooth/mgmt.c if (cp->val) { val 1349 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01 && cp->val != 0x02) val 1358 net/bluetooth/mgmt.c if ((cp->val == 0x00 && timeout > 0) || val 1359 net/bluetooth/mgmt.c (cp->val == 0x02 && timeout == 0)) val 1391 net/bluetooth/mgmt.c if (!!cp->val != hci_dev_test_flag(hdev, HCI_DISCOVERABLE)) { val 1410 net/bluetooth/mgmt.c if (!!cp->val == hci_dev_test_flag(hdev, HCI_DISCOVERABLE) && val 1411 net/bluetooth/mgmt.c (cp->val == 0x02) == hci_dev_test_flag(hdev, val 1416 net/bluetooth/mgmt.c if (cp->val && hdev->discov_timeout > 0) { val 1439 net/bluetooth/mgmt.c if (cp->val) val 1445 net/bluetooth/mgmt.c if (cp->val == 0x02) val 1487 net/bluetooth/mgmt.c struct sock *sk, u8 val) val 1492 net/bluetooth/mgmt.c if (!!val != hci_dev_test_flag(hdev, HCI_CONNECTABLE)) val 1495 net/bluetooth/mgmt.c if (val) { val 1529 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 1536 net/bluetooth/mgmt.c err = set_connectable_update_settings(hdev, sk, cp->val); val 1553 net/bluetooth/mgmt.c if (cp->val) { val 1581 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 1587 net/bluetooth/mgmt.c if (cp->val) val 1620 net/bluetooth/mgmt.c u8 val, status; val 1630 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 1639 net/bluetooth/mgmt.c if (!!cp->val != hci_dev_test_flag(hdev, HCI_LINK_SECURITY)) { val 1660 net/bluetooth/mgmt.c val = !!cp->val; val 1662 net/bluetooth/mgmt.c if (test_bit(HCI_AUTH, &hdev->flags) == val) { val 1673 net/bluetooth/mgmt.c err = hci_send_cmd(hdev, HCI_OP_WRITE_AUTH_ENABLE, sizeof(val), &val); val 1701 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 1710 net/bluetooth/mgmt.c if (cp->val) { val 1739 net/bluetooth/mgmt.c if (!!cp->val == hci_dev_test_flag(hdev, HCI_SSP_ENABLED)) { val 1750 net/bluetooth/mgmt.c if (!cp->val && hci_dev_test_flag(hdev, HCI_USE_DEBUG_KEYS)) val 1752 net/bluetooth/mgmt.c sizeof(cp->val), &cp->val); val 1754 net/bluetooth/mgmt.c err = hci_send_cmd(hdev, HCI_OP_WRITE_SSP_MODE, 1, &cp->val); val 1786 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 1798 net/bluetooth/mgmt.c if (cp->val) { val 1876 net/bluetooth/mgmt.c u8 val, enabled; val 1884 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 1898 net/bluetooth/mgmt.c if (cp->val == 0x01) val 1907 net/bluetooth/mgmt.c val = !!cp->val; val 1910 net/bluetooth/mgmt.c if (!val) val 1913 net/bluetooth/mgmt.c if (!hdev_is_powered(hdev) || val == enabled) { val 1916 net/bluetooth/mgmt.c if (val != hci_dev_test_flag(hdev, HCI_LE_ENABLED)) { val 1921 net/bluetooth/mgmt.c if (!val && hci_dev_test_flag(hdev, HCI_ADVERTISING)) { val 1953 net/bluetooth/mgmt.c if (val) { val 1954 net/bluetooth/mgmt.c hci_cp.le = val; val 2006 net/bluetooth/mgmt.c u32 val; val 2011 net/bluetooth/mgmt.c val = get_unaligned_le32(&uuid[12]); val 2012 net/bluetooth/mgmt.c if (val > 0xffff) val 2350 net/bluetooth/mgmt.c hci_add_link_key(hdev, NULL, &key->addr.bdaddr, key->val, val 4306 net/bluetooth/mgmt.c u8 val, status; val 4316 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01 && cp->val != 0x02) val 4322 net/bluetooth/mgmt.c val = !!cp->val; val 4330 net/bluetooth/mgmt.c (val == hci_dev_test_flag(hdev, HCI_ADVERTISING) && val 4331 net/bluetooth/mgmt.c (cp->val == 0x02) == hci_dev_test_flag(hdev, HCI_ADVERTISING_CONNECTABLE)) || val 4337 net/bluetooth/mgmt.c if (cp->val) { val 4340 net/bluetooth/mgmt.c if (cp->val == 0x02) val 4374 net/bluetooth/mgmt.c if (cp->val == 0x02) val 4381 net/bluetooth/mgmt.c if (val) { val 4528 net/bluetooth/mgmt.c if (cp->val) val 4558 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 4570 net/bluetooth/mgmt.c if (!!cp->val == hci_dev_test_flag(hdev, HCI_FAST_CONNECTABLE)) { val 4593 net/bluetooth/mgmt.c __hci_req_write_fast_connectable(&req, cp->val); val 4657 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01) val 4663 net/bluetooth/mgmt.c if (cp->val == hci_dev_test_flag(hdev, HCI_BREDR_ENABLED)) { val 4669 net/bluetooth/mgmt.c if (!cp->val) { val 4688 net/bluetooth/mgmt.c if (!cp->val) { val 4773 net/bluetooth/mgmt.c switch (cp->val) { val 4803 net/bluetooth/mgmt.c u8 val; val 4819 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01 && cp->val != 0x02) val 4829 net/bluetooth/mgmt.c if (cp->val) { val 4832 net/bluetooth/mgmt.c if (cp->val == 0x02) val 4858 net/bluetooth/mgmt.c val = !!cp->val; val 4860 net/bluetooth/mgmt.c if (val == hci_dev_test_flag(hdev, HCI_SC_ENABLED) && val 4861 net/bluetooth/mgmt.c (cp->val == 0x02) == hci_dev_test_flag(hdev, HCI_SC_ONLY)) { val 4873 net/bluetooth/mgmt.c hci_req_add(&req, HCI_OP_WRITE_SC_SUPPORT, 1, &val); val 4894 net/bluetooth/mgmt.c if (cp->val != 0x00 && cp->val != 0x01 && cp->val != 0x02) val 4900 net/bluetooth/mgmt.c if (cp->val) val 4906 net/bluetooth/mgmt.c if (cp->val == 0x02) val 4915 net/bluetooth/mgmt.c u8 mode = (cp->val == 0x02) ? 0x01 : 0x00; val 5055 net/bluetooth/mgmt.c le_addr_type(irk->addr.type), irk->val, val 5164 net/bluetooth/mgmt.c key->val, key->enc_size, key->ediv, key->rand); val 7098 net/bluetooth/mgmt.c memcpy(ev.key.val, key->val, HCI_LINK_KEY_SIZE); val 7159 net/bluetooth/mgmt.c memcpy(ev.key.val, key->val, key->enc_size); val 7160 net/bluetooth/mgmt.c memset(ev.key.val + key->enc_size, 0, val 7161 net/bluetooth/mgmt.c sizeof(ev.key.val) - key->enc_size); val 7177 net/bluetooth/mgmt.c memcpy(ev.irk.val, irk->val, sizeof(irk->val)); val 7207 net/bluetooth/mgmt.c memcpy(ev.key.val, csrk->val, sizeof(csrk->val)); val 7303 net/bluetooth/mgmt.c if (!cp->val) val 318 net/bluetooth/smp.c const u8 x[16], const u8 y[16], u32 *val) val 335 net/bluetooth/smp.c *val = get_unaligned_le32(tmp); val 336 net/bluetooth/smp.c *val %= 1000000; val 338 net/bluetooth/smp.c SMP_DBG("val %06u", *val); val 1215 net/bluetooth/smp.c if (smp_h7(smp->tfm_cmac, key->val, salt, smp->tk)) val 1221 net/bluetooth/smp.c if (smp_h6(smp->tfm_cmac, key->val, tmp2, smp->tk)) val 1342 net/bluetooth/smp.c memcpy(csrk->val, sign.csrk, sizeof(csrk->val)); val 2222 net/bluetooth/smp.c hci_le_start_enc(hcon, key->ediv, key->rand, key->val, key->enc_size); val 2619 net/bluetooth/smp.c memcpy(csrk->val, rp->csrk, sizeof(csrk->val)); val 3751 net/bluetooth/smp.c u32 val; val 3754 net/bluetooth/smp.c err = smp_g2(tfm_cmac, u, v, x, y, &val); val 3758 net/bluetooth/smp.c if (val != exp_val) val 1942 net/bridge/br_multicast.c int br_multicast_set_router(struct net_bridge *br, unsigned long val) val 1948 net/bridge/br_multicast.c switch (val) { val 1951 net/bridge/br_multicast.c br_mc_router_state_change(br, val == MDB_RTR_TYPE_PERM); val 1953 net/bridge/br_multicast.c br->multicast_router = val; val 1959 net/bridge/br_multicast.c br->multicast_router = val; val 1982 net/bridge/br_multicast.c int br_multicast_set_port_router(struct net_bridge_port *p, unsigned long val) val 1989 net/bridge/br_multicast.c if (p->multicast_router == val) { val 1997 net/bridge/br_multicast.c switch (val) { val 2049 net/bridge/br_multicast.c int br_multicast_toggle(struct net_bridge *br, unsigned long val) val 2054 net/bridge/br_multicast.c if (!!br_opt_get(br, BROPT_MULTICAST_ENABLED) == !!val) val 2057 net/bridge/br_multicast.c br_mc_disabled_update(br->dev, val); val 2058 net/bridge/br_multicast.c br_opt_toggle(br, BROPT_MULTICAST_ENABLED, !!val); val 2097 net/bridge/br_multicast.c int br_multicast_set_querier(struct net_bridge *br, unsigned long val) val 2101 net/bridge/br_multicast.c val = !!val; val 2104 net/bridge/br_multicast.c if (br_opt_get(br, BROPT_MULTICAST_QUERIER) == val) val 2107 net/bridge/br_multicast.c br_opt_toggle(br, BROPT_MULTICAST_QUERIER, !!val); val 2108 net/bridge/br_multicast.c if (!val) val 2131 net/bridge/br_multicast.c int br_multicast_set_igmp_version(struct net_bridge *br, unsigned long val) val 2134 net/bridge/br_multicast.c switch (val) { val 2143 net/bridge/br_multicast.c br->multicast_igmp_version = val; val 2150 net/bridge/br_multicast.c int br_multicast_set_mld_version(struct net_bridge *br, unsigned long val) val 2153 net/bridge/br_multicast.c switch (val) { val 2162 net/bridge/br_multicast.c br->multicast_mld_version = val; val 1180 net/bridge/br_netlink.c u8 val; val 1182 net/bridge/br_netlink.c val = nla_get_u8(data[IFLA_BR_MCAST_QUERY_USE_IFADDR]); val 1183 net/bridge/br_netlink.c br_opt_toggle(br, BROPT_MULTICAST_QUERY_USE_IFADDR, !!val); val 1202 net/bridge/br_netlink.c u32 val = nla_get_u32(data[IFLA_BR_MCAST_LAST_MEMBER_CNT]); val 1204 net/bridge/br_netlink.c br->multicast_last_member_count = val; val 1208 net/bridge/br_netlink.c u32 val = nla_get_u32(data[IFLA_BR_MCAST_STARTUP_QUERY_CNT]); val 1210 net/bridge/br_netlink.c br->multicast_startup_query_count = val; val 1214 net/bridge/br_netlink.c u64 val = nla_get_u64(data[IFLA_BR_MCAST_LAST_MEMBER_INTVL]); val 1216 net/bridge/br_netlink.c br->multicast_last_member_interval = clock_t_to_jiffies(val); val 1220 net/bridge/br_netlink.c u64 val = nla_get_u64(data[IFLA_BR_MCAST_MEMBERSHIP_INTVL]); val 1222 net/bridge/br_netlink.c br->multicast_membership_interval = clock_t_to_jiffies(val); val 1226 net/bridge/br_netlink.c u64 val = nla_get_u64(data[IFLA_BR_MCAST_QUERIER_INTVL]); val 1228 net/bridge/br_netlink.c br->multicast_querier_interval = clock_t_to_jiffies(val); val 1232 net/bridge/br_netlink.c u64 val = nla_get_u64(data[IFLA_BR_MCAST_QUERY_INTVL]); val 1234 net/bridge/br_netlink.c br->multicast_query_interval = clock_t_to_jiffies(val); val 1238 net/bridge/br_netlink.c u64 val = nla_get_u64(data[IFLA_BR_MCAST_QUERY_RESPONSE_INTVL]); val 1240 net/bridge/br_netlink.c br->multicast_query_response_interval = clock_t_to_jiffies(val); val 1244 net/bridge/br_netlink.c u64 val = nla_get_u64(data[IFLA_BR_MCAST_STARTUP_QUERY_INTVL]); val 1246 net/bridge/br_netlink.c br->multicast_startup_query_interval = clock_t_to_jiffies(val); val 1278 net/bridge/br_netlink.c u8 val = nla_get_u8(data[IFLA_BR_NF_CALL_IPTABLES]); val 1280 net/bridge/br_netlink.c br_opt_toggle(br, BROPT_NF_CALL_IPTABLES, !!val); val 1284 net/bridge/br_netlink.c u8 val = nla_get_u8(data[IFLA_BR_NF_CALL_IP6TABLES]); val 1286 net/bridge/br_netlink.c br_opt_toggle(br, BROPT_NF_CALL_IP6TABLES, !!val); val 1290 net/bridge/br_netlink.c u8 val = nla_get_u8(data[IFLA_BR_NF_CALL_ARPTABLES]); val 1292 net/bridge/br_netlink.c br_opt_toggle(br, BROPT_NF_CALL_ARPTABLES, !!val); val 673 net/bridge/br_private.h int br_multicast_set_router(struct net_bridge *br, unsigned long val); val 674 net/bridge/br_private.h int br_multicast_set_port_router(struct net_bridge_port *p, unsigned long val); val 675 net/bridge/br_private.h int br_multicast_toggle(struct net_bridge *br, unsigned long val); val 676 net/bridge/br_private.h int br_multicast_set_querier(struct net_bridge *br, unsigned long val); val 677 net/bridge/br_private.h int br_multicast_set_hash_max(struct net_bridge *br, unsigned long val); val 678 net/bridge/br_private.h int br_multicast_set_igmp_version(struct net_bridge *br, unsigned long val); val 680 net/bridge/br_private.h int br_multicast_set_mld_version(struct net_bridge *br, unsigned long val); val 881 net/bridge/br_private.h int __br_vlan_filter_toggle(struct net_bridge *br, unsigned long val); val 882 net/bridge/br_private.h int br_vlan_filter_toggle(struct net_bridge *br, unsigned long val); val 884 net/bridge/br_private.h int br_vlan_set_proto(struct net_bridge *br, unsigned long val); val 885 net/bridge/br_private.h int br_vlan_set_stats(struct net_bridge *br, unsigned long val); val 886 net/bridge/br_private.h int br_vlan_set_stats_per_port(struct net_bridge *br, unsigned long val); val 888 net/bridge/br_private.h int br_vlan_set_default_pvid(struct net_bridge *br, unsigned long val); val 1046 net/bridge/br_private.h unsigned long val) val 1131 net/bridge/br_private.h void br_stp_set_enabled(struct net_bridge *br, unsigned long val); val 60 net/bridge/br_private_stp.h void __br_set_topology_change(struct net_bridge *br, unsigned char val); val 530 net/bridge/br_stp.c int br_set_hello_time(struct net_bridge *br, unsigned long val) val 532 net/bridge/br_stp.c unsigned long t = clock_t_to_jiffies(val); val 545 net/bridge/br_stp.c int br_set_max_age(struct net_bridge *br, unsigned long val) val 547 net/bridge/br_stp.c unsigned long t = clock_t_to_jiffies(val); val 607 net/bridge/br_stp.c void __br_set_topology_change(struct net_bridge *br, unsigned char val) val 612 net/bridge/br_stp.c if (br->stp_enabled == BR_KERNEL_STP && br->topology_change != val) { val 617 net/bridge/br_stp.c if (val) { val 632 net/bridge/br_stp.c br->topology_change = val; val 642 net/bridge/br_stp.c int br_set_forward_delay(struct net_bridge *br, unsigned long val) val 644 net/bridge/br_stp.c unsigned long t = clock_t_to_jiffies(val); val 199 net/bridge/br_stp_if.c void br_stp_set_enabled(struct net_bridge *br, unsigned long val) val 203 net/bridge/br_stp_if.c if (val) { val 33 net/bridge/br_sysfs_br.c unsigned long val; val 39 net/bridge/br_sysfs_br.c val = simple_strtoul(buf, &endp, 0); val 46 net/bridge/br_sysfs_br.c err = (*set)(br, val); val 106 net/bridge/br_sysfs_br.c static int set_ageing_time(struct net_bridge *br, unsigned long val) val 108 net/bridge/br_sysfs_br.c return br_set_ageing_time(br, val); val 127 net/bridge/br_sysfs_br.c static int set_stp_state(struct net_bridge *br, unsigned long val) val 129 net/bridge/br_sysfs_br.c br_stp_set_enabled(br, val); val 150 net/bridge/br_sysfs_br.c static int set_group_fwd_mask(struct net_bridge *br, unsigned long val) val 152 net/bridge/br_sysfs_br.c if (val & BR_GROUPFWD_RESTRICTED) val 155 net/bridge/br_sysfs_br.c br->group_fwd_mask = val; val 177 net/bridge/br_sysfs_br.c static int set_priority(struct net_bridge *br, unsigned long val) val 179 net/bridge/br_sysfs_br.c br_stp_set_bridge_priority(br, (u16) val); val 313 net/bridge/br_sysfs_br.c static int set_flush(struct net_bridge *br, unsigned long val) val 335 net/bridge/br_sysfs_br.c static int set_no_linklocal_learn(struct net_bridge *br, unsigned long val) val 337 net/bridge/br_sysfs_br.c return br_boolopt_toggle(br, BR_BOOLOPT_NO_LL_LEARN, !!val, NULL); val 389 net/bridge/br_sysfs_br.c static int set_query_use_ifaddr(struct net_bridge *br, unsigned long val) val 391 net/bridge/br_sysfs_br.c br_opt_toggle(br, BROPT_MULTICAST_QUERY_USE_IFADDR, !!val); val 426 net/bridge/br_sysfs_br.c static int set_elasticity(struct net_bridge *br, unsigned long val) val 448 net/bridge/br_sysfs_br.c static int set_hash_max(struct net_bridge *br, unsigned long val) val 450 net/bridge/br_sysfs_br.c br->hash_max = val; val 486 net/bridge/br_sysfs_br.c static int set_last_member_count(struct net_bridge *br, unsigned long val) val 488 net/bridge/br_sysfs_br.c br->multicast_last_member_count = val; val 507 net/bridge/br_sysfs_br.c static int set_startup_query_count(struct net_bridge *br, unsigned long val) val 509 net/bridge/br_sysfs_br.c br->multicast_startup_query_count = val; val 529 net/bridge/br_sysfs_br.c static int set_last_member_interval(struct net_bridge *br, unsigned long val) val 531 net/bridge/br_sysfs_br.c br->multicast_last_member_interval = clock_t_to_jiffies(val); val 551 net/bridge/br_sysfs_br.c static int set_membership_interval(struct net_bridge *br, unsigned long val) val 553 net/bridge/br_sysfs_br.c br->multicast_membership_interval = clock_t_to_jiffies(val); val 574 net/bridge/br_sysfs_br.c static int set_querier_interval(struct net_bridge *br, unsigned long val) val 576 net/bridge/br_sysfs_br.c br->multicast_querier_interval = clock_t_to_jiffies(val); val 597 net/bridge/br_sysfs_br.c static int set_query_interval(struct net_bridge *br, unsigned long val) val 599 net/bridge/br_sysfs_br.c br->multicast_query_interval = clock_t_to_jiffies(val); val 620 net/bridge/br_sysfs_br.c static int set_query_response_interval(struct net_bridge *br, unsigned long val) val 622 net/bridge/br_sysfs_br.c br->multicast_query_response_interval = clock_t_to_jiffies(val); val 643 net/bridge/br_sysfs_br.c static int set_startup_query_interval(struct net_bridge *br, unsigned long val) val 645 net/bridge/br_sysfs_br.c br->multicast_startup_query_interval = clock_t_to_jiffies(val); val 667 net/bridge/br_sysfs_br.c static int set_stats_enabled(struct net_bridge *br, unsigned long val) val 669 net/bridge/br_sysfs_br.c br_opt_toggle(br, BROPT_MULTICAST_STATS_ENABLED, !!val); val 709 net/bridge/br_sysfs_br.c static int set_nf_call_iptables(struct net_bridge *br, unsigned long val) val 711 net/bridge/br_sysfs_br.c br_opt_toggle(br, BROPT_NF_CALL_IPTABLES, !!val); val 730 net/bridge/br_sysfs_br.c static int set_nf_call_ip6tables(struct net_bridge *br, unsigned long val) val 732 net/bridge/br_sysfs_br.c br_opt_toggle(br, BROPT_NF_CALL_IP6TABLES, !!val); val 751 net/bridge/br_sysfs_br.c static int set_nf_call_arptables(struct net_bridge *br, unsigned long val) val 753 net/bridge/br_sysfs_br.c br_opt_toggle(br, BROPT_NF_CALL_ARPTABLES, !!val); val 310 net/bridge/br_sysfs_if.c unsigned long val; val 332 net/bridge/br_sysfs_if.c val = simple_strtoul(buf, &endp, 0); val 336 net/bridge/br_sysfs_if.c ret = brport_attr->store(p, val); val 762 net/bridge/br_vlan.c int __br_vlan_filter_toggle(struct net_bridge *br, unsigned long val) val 768 net/bridge/br_vlan.c .u.vlan_filtering = val, val 772 net/bridge/br_vlan.c if (br_opt_get(br, BROPT_VLAN_ENABLED) == !!val) val 779 net/bridge/br_vlan.c br_opt_toggle(br, BROPT_VLAN_ENABLED, !!val); val 787 net/bridge/br_vlan.c int br_vlan_filter_toggle(struct net_bridge *br, unsigned long val) val 789 net/bridge/br_vlan.c return __br_vlan_filter_toggle(br, val); val 859 net/bridge/br_vlan.c int br_vlan_set_proto(struct net_bridge *br, unsigned long val) val 861 net/bridge/br_vlan.c if (val != ETH_P_8021Q && val != ETH_P_8021AD) val 864 net/bridge/br_vlan.c return __br_vlan_set_proto(br, htons(val)); val 867 net/bridge/br_vlan.c int br_vlan_set_stats(struct net_bridge *br, unsigned long val) val 869 net/bridge/br_vlan.c switch (val) { val 872 net/bridge/br_vlan.c br_opt_toggle(br, BROPT_VLAN_STATS_ENABLED, !!val); val 881 net/bridge/br_vlan.c int br_vlan_set_stats_per_port(struct net_bridge *br, unsigned long val) val 893 net/bridge/br_vlan.c switch (val) { val 896 net/bridge/br_vlan.c br_opt_toggle(br, BROPT_VLAN_STATS_PER_PORT, !!val); val 1030 net/bridge/br_vlan.c int br_vlan_set_default_pvid(struct net_bridge *br, unsigned long val) val 1032 net/bridge/br_vlan.c u16 pvid = val; val 1035 net/bridge/br_vlan.c if (val >= VLAN_VID_MASK) val 264 net/can/gw.c u8 val = xor->init_xor_val; val 272 net/can/gw.c val ^= cf->data[i]; val 275 net/can/gw.c val ^= cf->data[i]; val 278 net/can/gw.c cf->data[res] = val; val 283 net/can/gw.c u8 val = xor->init_xor_val; val 287 net/can/gw.c val ^= cf->data[i]; val 289 net/can/gw.c cf->data[xor->result_idx] = val; val 294 net/can/gw.c u8 val = xor->init_xor_val; val 298 net/can/gw.c val ^= cf->data[i]; val 300 net/can/gw.c cf->data[xor->result_idx] = val; val 730 net/can/j1939/socket.c void *val = &tmp; val 763 net/can/j1939/socket.c else if (copy_to_user(optval, val, len)) val 654 net/can/raw.c void *val; val 686 net/can/raw.c val = &ro->err_mask; val 692 net/can/raw.c val = &ro->loopback; val 698 net/can/raw.c val = &ro->recv_own_msgs; val 704 net/can/raw.c val = &ro->fd_frames; val 710 net/can/raw.c val = &ro->join_filters; val 719 net/can/raw.c if (copy_to_user(optval, val, len)) val 160 net/core/dev.c static int call_netdevice_notifiers_info(unsigned long val, val 162 net/core/dev.c static int call_netdevice_notifiers_extack(unsigned long val, val 1508 net/core/dev.c #define N(val) \ val 1509 net/core/dev.c case NETDEV_##val: \ val 1510 net/core/dev.c return "NETDEV_" __stringify(val); val 1528 net/core/dev.c static int call_netdevice_notifier(struct notifier_block *nb, unsigned long val, val 1535 net/core/dev.c return nb->notifier_call(nb, val, &info); val 1663 net/core/dev.c static int call_netdevice_notifiers_info(unsigned long val, val 1667 net/core/dev.c return raw_notifier_call_chain(&netdev_chain, val, info); val 1670 net/core/dev.c static int call_netdevice_notifiers_extack(unsigned long val, val 1679 net/core/dev.c return call_netdevice_notifiers_info(val, &info); val 1691 net/core/dev.c int call_netdevice_notifiers(unsigned long val, struct net_device *dev) val 1693 net/core/dev.c return call_netdevice_notifiers_extack(val, dev, NULL); val 1706 net/core/dev.c static int call_netdevice_notifiers_mtu(unsigned long val, val 1716 net/core/dev.c return call_netdevice_notifiers_info(val, &info.info); val 5929 net/core/dev.c unsigned long val, new; val 5932 net/core/dev.c val = READ_ONCE(n->state); val 5933 net/core/dev.c if (unlikely(val & NAPIF_STATE_DISABLE)) val 5935 net/core/dev.c new = val | NAPIF_STATE_SCHED; val 5943 net/core/dev.c new |= (val & NAPIF_STATE_SCHED) / NAPIF_STATE_SCHED * val 5945 net/core/dev.c } while (cmpxchg(&n->state, val, new) != val); val 5947 net/core/dev.c return !(val & NAPIF_STATE_SCHED); val 5965 net/core/dev.c unsigned long flags, val, new; val 6003 net/core/dev.c val = READ_ONCE(n->state); val 6005 net/core/dev.c WARN_ON_ONCE(!(val & NAPIF_STATE_SCHED)); val 6007 net/core/dev.c new = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED); val 6013 net/core/dev.c new |= (val & NAPIF_STATE_MISSED) / NAPIF_STATE_MISSED * val 6015 net/core/dev.c } while (cmpxchg(&n->state, val, new) != val); val 6017 net/core/dev.c if (unlikely(val & NAPIF_STATE_MISSED)) { val 6105 net/core/dev.c unsigned long val = READ_ONCE(napi->state); val 6110 net/core/dev.c if (val & (NAPIF_STATE_DISABLE | NAPIF_STATE_SCHED | val 6113 net/core/dev.c if (cmpxchg(&napi->state, val, val 6114 net/core/dev.c val | NAPIF_STATE_IN_BUSY_POLL | val 6115 net/core/dev.c NAPIF_STATE_SCHED) != val) val 7424 net/core/dev.c bool val) val 7430 net/core/dev.c adj->ignore = val; val 7434 net/core/dev.c adj->ignore = val; val 235 net/core/devlink.c u16 val; val 240 net/core/devlink.c val = nla_get_u16(attrs[DEVLINK_ATTR_SB_POOL_INDEX]); val 241 net/core/devlink.c if (val >= devlink_sb_pool_count(devlink_sb)) val 243 net/core/devlink.c *p_pool_index = val; val 259 net/core/devlink.c u8 val; val 264 net/core/devlink.c val = nla_get_u8(attrs[DEVLINK_ATTR_SB_POOL_TYPE]); val 265 net/core/devlink.c if (val != DEVLINK_SB_POOL_TYPE_INGRESS && val 266 net/core/devlink.c val != DEVLINK_SB_POOL_TYPE_EGRESS) val 268 net/core/devlink.c *p_pool_type = val; val 283 net/core/devlink.c u8 val; val 288 net/core/devlink.c val = nla_get_u8(attrs[DEVLINK_ATTR_SB_POOL_THRESHOLD_TYPE]); val 289 net/core/devlink.c if (val != DEVLINK_SB_THRESHOLD_TYPE_STATIC && val 290 net/core/devlink.c val != DEVLINK_SB_THRESHOLD_TYPE_DYNAMIC) val 292 net/core/devlink.c *p_th_type = val; val 309 net/core/devlink.c u16 val; val 314 net/core/devlink.c val = nla_get_u16(attrs[DEVLINK_ATTR_SB_TC_INDEX]); val 316 net/core/devlink.c val >= devlink_sb->ingress_tc_count) val 319 net/core/devlink.c val >= devlink_sb->egress_tc_count) val 321 net/core/devlink.c *p_tc_index = val; val 2987 net/core/devlink.c union devlink_param_value val) val 3001 net/core/devlink.c if (nla_put_u8(msg, DEVLINK_ATTR_PARAM_VALUE_DATA, val.vu8)) val 3005 net/core/devlink.c if (nla_put_u16(msg, DEVLINK_ATTR_PARAM_VALUE_DATA, val.vu16)) val 3009 net/core/devlink.c if (nla_put_u32(msg, DEVLINK_ATTR_PARAM_VALUE_DATA, val.vu32)) val 3014 net/core/devlink.c val.vstr)) val 3018 net/core/devlink.c if (val.vbool && val 3065 net/core/devlink.c param_value[i] = ctx.val; val 3352 net/core/devlink.c ctx.val = value; val 5296 net/core/devlink.c u8 val; val 5298 net/core/devlink.c val = nla_get_u8(info->attrs[DEVLINK_ATTR_TRAP_ACTION]); val 5299 net/core/devlink.c switch (val) { val 5302 net/core/devlink.c *p_trap_action = val; val 1160 net/core/drop_monitor.c u8 val; val 1162 net/core/drop_monitor.c val = nla_get_u8(info->attrs[NET_DM_ATTR_ALERT_MODE]); val 1164 net/core/drop_monitor.c switch (val) { val 1167 net/core/drop_monitor.c *p_alert_mode = val; val 4242 net/core/filter.c int val; val 4250 net/core/filter.c val = *((int *)optval); val 4255 net/core/filter.c val = min_t(u32, val, sysctl_rmem_max); val 4258 net/core/filter.c max_t(int, val * 2, SOCK_MIN_RCVBUF)); val 4261 net/core/filter.c val = min_t(u32, val, sysctl_wmem_max); val 4264 net/core/filter.c max_t(int, val * 2, SOCK_MIN_SNDBUF)); val 4267 net/core/filter.c if (val != ~0U) val 4271 net/core/filter.c sk->sk_max_pacing_rate = (val == ~0U) ? ~0UL : val; val 4276 net/core/filter.c sk->sk_priority = val; val 4279 net/core/filter.c if (val < 0) val 4280 net/core/filter.c val = INT_MAX; val 4281 net/core/filter.c WRITE_ONCE(sk->sk_rcvlowat, val ? : 1); val 4284 net/core/filter.c if (sk->sk_mark != val) { val 4285 net/core/filter.c sk->sk_mark = val; val 4297 net/core/filter.c val = *((int *)optval); val 4301 net/core/filter.c if (val < -1 || val > 0xff) { val 4306 net/core/filter.c if (val == -1) val 4307 net/core/filter.c val = 0; val 4308 net/core/filter.c inet->tos = val; val 4319 net/core/filter.c val = *((int *)optval); val 4323 net/core/filter.c if (val < -1 || val > 0xff) { val 4328 net/core/filter.c if (val == -1) val 4329 net/core/filter.c val = 0; val 4330 net/core/filter.c np->tclass = val; val 4354 net/core/filter.c val = *((int *)optval); val 4358 net/core/filter.c if (val <= 0 || tp->data_segs_out > tp->syn_data) val 4361 net/core/filter.c tp->snd_cwnd = val; val 4364 net/core/filter.c if (val <= 0) { val 4367 net/core/filter.c tp->snd_cwnd_clamp = val; val 4368 net/core/filter.c tp->snd_ssthresh = val; val 4372 net/core/filter.c if (val < 0 || val > 1) val 4375 net/core/filter.c tp->save_syn = val; val 4486 net/core/filter.c int val = argval & BPF_SOCK_OPS_ALL_CB_FLAGS; val 4491 net/core/filter.c tcp_sk(sk)->bpf_sock_ops_cb_flags = val; val 356 net/core/net-sysfs.c static int change_gro_flush_timeout(struct net_device *dev, unsigned long val) val 358 net/core/net-sysfs.c dev->gro_flush_timeout = val; val 770 net/core/net-sysfs.c unsigned long val = 0; val 775 net/core/net-sysfs.c val = (unsigned long)flow_table->mask + 1; val 778 net/core/net-sysfs.c return sprintf(buf, "%lu\n", val); val 59 net/core/netevent.c int call_netevent_notifiers(unsigned long val, void *v) val 61 net/core/netevent.c return atomic_notifier_call_chain(&netevent_notif_chain, val, v); val 144 net/core/sock.c static void sock_inuse_add(struct net *net, int val); val 727 net/core/sock.c int val; val 742 net/core/sock.c if (get_user(val, (int __user *)optval)) val 745 net/core/sock.c valbool = val ? 1 : 0; val 751 net/core/sock.c if (val && !capable(CAP_NET_ADMIN)) val 781 net/core/sock.c val = min_t(u32, val, sysctl_wmem_max); val 786 net/core/sock.c val = min_t(int, val, INT_MAX / 2); val 789 net/core/sock.c max_t(int, val * 2, SOCK_MIN_SNDBUF)); val 803 net/core/sock.c if (val < 0) val 804 net/core/sock.c val = 0; val 813 net/core/sock.c val = min_t(u32, val, sysctl_rmem_max); val 818 net/core/sock.c val = min_t(int, val, INT_MAX / 2); val 836 net/core/sock.c max_t(int, val * 2, SOCK_MIN_RCVBUF)); val 848 net/core/sock.c if (val < 0) val 849 net/core/sock.c val = 0; val 867 net/core/sock.c if ((val >= 0 && val <= 6) || val 869 net/core/sock.c sk->sk_priority = val; val 934 net/core/sock.c if (val & ~SOF_TIMESTAMPING_MASK) { val 939 net/core/sock.c if (val & SOF_TIMESTAMPING_OPT_ID && val 954 net/core/sock.c if (val & SOF_TIMESTAMPING_OPT_STATS && val 955 net/core/sock.c !(val & SOF_TIMESTAMPING_OPT_TSONLY)) { val 960 net/core/sock.c sk->sk_tsflags = val; val 961 net/core/sock.c if (val & SOF_TIMESTAMPING_RX_SOFTWARE) val 974 net/core/sock.c if (val < 0) val 975 net/core/sock.c val = INT_MAX; val 977 net/core/sock.c ret = sock->ops->set_rcvlowat(sk, val); val 979 net/core/sock.c WRITE_ONCE(sk->sk_rcvlowat, val ? : 1); val 1068 net/core/sock.c } else if (val != sk->sk_mark) { val 1069 net/core/sock.c sk->sk_mark = val; val 1084 net/core/sock.c ret = sock->ops->set_peek_off(sk, val); val 1100 net/core/sock.c if ((val > sk->sk_ll_usec) && !capable(CAP_NET_ADMIN)) val 1103 net/core/sock.c if (val < 0) val 1106 net/core/sock.c sk->sk_ll_usec = val; val 1113 net/core/sock.c unsigned long ulval = (val == ~0U) ? ~0UL : val; val 1115 net/core/sock.c if (sizeof(ulval) != sizeof(val) && val 1130 net/core/sock.c WRITE_ONCE(sk->sk_incoming_cpu, val); val 1134 net/core/sock.c if (val == 1) val 1149 net/core/sock.c if (val < 0 || val > 1) val 1177 net/core/sock.c ret = sock_setbindtodevice_locked(sk, val); val 1221 net/core/sock.c int val; val 1243 net/core/sock.c v.val = sock_flag(sk, SOCK_DBG); val 1247 net/core/sock.c v.val = sock_flag(sk, SOCK_LOCALROUTE); val 1251 net/core/sock.c v.val = sock_flag(sk, SOCK_BROADCAST); val 1255 net/core/sock.c v.val = sk->sk_sndbuf; val 1259 net/core/sock.c v.val = sk->sk_rcvbuf; val 1263 net/core/sock.c v.val = sk->sk_reuse; val 1267 net/core/sock.c v.val = sk->sk_reuseport; val 1271 net/core/sock.c v.val = sock_flag(sk, SOCK_KEEPOPEN); val 1275 net/core/sock.c v.val = sk->sk_type; val 1279 net/core/sock.c v.val = sk->sk_protocol; val 1283 net/core/sock.c v.val = sk->sk_family; val 1287 net/core/sock.c v.val = -sock_error(sk); val 1288 net/core/sock.c if (v.val == 0) val 1289 net/core/sock.c v.val = xchg(&sk->sk_err_soft, 0); val 1293 net/core/sock.c v.val = sock_flag(sk, SOCK_URGINLINE); val 1297 net/core/sock.c v.val = sk->sk_no_check_tx; val 1301 net/core/sock.c v.val = sk->sk_priority; val 1315 net/core/sock.c v.val = sock_flag(sk, SOCK_RCVTSTAMP) && val 1321 net/core/sock.c v.val = sock_flag(sk, SOCK_RCVTSTAMPNS) && !sock_flag(sk, SOCK_TSTAMP_NEW); val 1325 net/core/sock.c v.val = sock_flag(sk, SOCK_RCVTSTAMP) && sock_flag(sk, SOCK_TSTAMP_NEW); val 1329 net/core/sock.c v.val = sock_flag(sk, SOCK_RCVTSTAMPNS) && sock_flag(sk, SOCK_TSTAMP_NEW); val 1333 net/core/sock.c v.val = sk->sk_tsflags; val 1347 net/core/sock.c v.val = sk->sk_rcvlowat; val 1351 net/core/sock.c v.val = 1; val 1355 net/core/sock.c v.val = !!test_bit(SOCK_PASSCRED, &sock->flags); val 1408 net/core/sock.c v.val = sk->sk_state == TCP_LISTEN; val 1412 net/core/sock.c v.val = !!test_bit(SOCK_PASSSEC, &sock->flags); val 1419 net/core/sock.c v.val = sk->sk_mark; val 1423 net/core/sock.c v.val = sock_flag(sk, SOCK_RXQ_OVFL); val 1427 net/core/sock.c v.val = sock_flag(sk, SOCK_WIFI_STATUS); val 1434 net/core/sock.c v.val = sk->sk_peek_off; val 1437 net/core/sock.c v.val = sock_flag(sk, SOCK_NOFCS); val 1451 net/core/sock.c v.val = sock_flag(sk, SOCK_FILTER_LOCKED); val 1455 net/core/sock.c v.val = bpf_tell_extensions(); val 1459 net/core/sock.c v.val = sock_flag(sk, SOCK_SELECT_ERR_QUEUE); val 1464 net/core/sock.c v.val = sk->sk_ll_usec; val 1469 net/core/sock.c if (sizeof(v.ulval) != sizeof(v.val) && len >= sizeof(v.ulval)) { val 1474 net/core/sock.c v.val = min_t(unsigned long, sk->sk_max_pacing_rate, ~0U); val 1479 net/core/sock.c v.val = READ_ONCE(sk->sk_incoming_cpu); val 1497 net/core/sock.c v.val = READ_ONCE(sk->sk_napi_id); val 1500 net/core/sock.c if (v.val < MIN_NAPI_ID) val 1501 net/core/sock.c v.val = 0; val 1514 net/core/sock.c v.val = sock_flag(sk, SOCK_ZEROCOPY); val 1527 net/core/sock.c v.val = sk->sk_bound_dev_if; val 2632 net/core/sock.c int sk_set_peek_off(struct sock *sk, int val) val 2634 net/core/sock.c sk->sk_peek_off = val; val 3227 net/core/sock.c int val[PROTO_INUSE_NR]; val 3232 net/core/sock.c void sock_prot_inuse_add(struct net *net, struct proto *prot, int val) val 3234 net/core/sock.c __this_cpu_add(net->core.prot_inuse->val[prot->inuse_idx], val); val 3244 net/core/sock.c res += per_cpu_ptr(net->core.prot_inuse, cpu)->val[idx]; val 3250 net/core/sock.c static void sock_inuse_add(struct net *net, int val) val 3252 net/core/sock.c this_cpu_add(*net->core.sock_inuse, val); val 3333 net/core/sock.c static void sock_inuse_add(struct net *net, int val) val 53 net/core/utils.c unsigned int val; val 60 net/core/utils.c val = 0; val 62 net/core/utils.c val *= 10; val 63 net/core/utils.c val += *str - '0'; val 66 net/core/utils.c l |= val; val 88 net/core/utils.c int val; val 97 net/core/utils.c val = hex_to_bin(c); val 98 net/core/utils.c if (val >= 0) val 99 net/core/utils.c return val | IN6PTON_XDIGIT | (val < 10 ? IN6PTON_DIGIT : 0); val 27 net/dcb/dcbevent.c int call_dcbevent_notifiers(unsigned long val, void *v) val 29 net/dcb/dcbevent.c return atomic_notifier_call_chain(&dcbevent_notif_chain, val, v); val 63 net/dccp/ccid.h u8 opt, u8 *val, u8 len); val 69 net/dccp/ccid.h u8 opt, u8 *val, u8 len); val 200 net/dccp/ccid.h u8 pkt, u8 opt, u8 *val, u8 len) val 204 net/dccp/ccid.h return ccid->ccid_ops->ccid_hc_tx_parse_options(sk, pkt, opt, val, len); val 212 net/dccp/ccid.h u8 pkt, u8 opt, u8 *val, u8 len) val 216 net/dccp/ccid.h return ccid->ccid_ops->ccid_hc_rx_parse_options(sk, pkt, opt, val, len); val 74 net/dccp/ccids/ccid2.c static void ccid2_change_l_ack_ratio(struct sock *sk, u32 val) val 84 net/dccp/ccids/ccid2.c if (val == 0 || val > max_ratio) { val 85 net/dccp/ccids/ccid2.c DCCP_WARN("Limiting Ack Ratio (%u) to %u\n", val, max_ratio); val 86 net/dccp/ccids/ccid2.c val = max_ratio; val 89 net/dccp/ccids/ccid2.c min_t(u32, val, DCCPF_ACK_RATIO_MAX)); val 110 net/dccp/ccids/ccid2.c static void ccid2_change_l_seq_window(struct sock *sk, u64 val) val 113 net/dccp/ccids/ccid2.c clamp_val(val, DCCPF_SEQ_WMIN, val 520 net/dccp/ccids/ccid3.c const void *val; val 535 net/dccp/ccids/ccid3.c val = &tfrc; val 541 net/dccp/ccids/ccid3.c if (put_user(len, optlen) || copy_to_user(optval, val, len)) val 814 net/dccp/ccids/ccid3.c const void *val; val 824 net/dccp/ccids/ccid3.c val = &rx_info; val 830 net/dccp/ccids/ccid3.c if (put_user(len, optlen) || copy_to_user(optval, val, len)) val 133 net/dccp/feat.c int (*activation_hdlr)(struct sock *sk, u64 val, bool rx); val 252 net/dccp/feat.c static void dccp_feat_printval(u8 feat_num, dccp_feat_val const *val) val 256 net/dccp/feat.c if (val == NULL || (type == FEAT_SP && val->sp.vec == NULL)) val 259 net/dccp/feat.c for (i = 0; i < val->sp.len; i++) val 260 net/dccp/feat.c dccp_pr_debug_cat("%s%u", i ? " " : "", val->sp.vec[i]); val 262 net/dccp/feat.c dccp_pr_debug_cat("%llu", (unsigned long long)val->nn); val 281 net/dccp/feat.c dccp_feat_printval(entry->feat_num, &entry->val); val 286 net/dccp/feat.c #define dccp_feat_print_opt(opt, feat, val, len, mandatory) do { \ val 288 net/dccp/feat.c dccp_feat_printvals(feat, val, len); \ val 299 net/dccp/feat.c #define dccp_feat_print_opt(opt, feat, val, len, mandatory) val 307 net/dccp/feat.c u64 val; val 315 net/dccp/feat.c val = dccp_feat_table[idx].default_value; val 324 net/dccp/feat.c val = dccp_feat_table[idx].default_value; val 326 net/dccp/feat.c val = fval->sp.vec[0]; val 329 net/dccp/feat.c val = fval->nn; val 337 net/dccp/feat.c fval ? "" : "default ", (unsigned long long)val); val 339 net/dccp/feat.c return dccp_feat_table[idx].activation_hdlr(sk, val, rx); val 365 net/dccp/feat.c static int dccp_feat_clone_sp_val(dccp_feat_val *fval, u8 const *val, u8 len) val 369 net/dccp/feat.c fval->sp.vec = kmemdup(val, len, gfp_any()); val 378 net/dccp/feat.c static void dccp_feat_val_destructor(u8 feat_num, dccp_feat_val *val) val 380 net/dccp/feat.c if (unlikely(val == NULL)) val 383 net/dccp/feat.c kfree(val->sp.vec); val 384 net/dccp/feat.c memset(val, 0, sizeof(*val)); val 400 net/dccp/feat.c if (type == FEAT_SP && dccp_feat_clone_sp_val(&new->val, val 401 net/dccp/feat.c original->val.sp.vec, val 402 net/dccp/feat.c original->val.sp.len)) { val 412 net/dccp/feat.c dccp_feat_val_destructor(entry->feat_num, &entry->val); val 455 net/dccp/feat.c dccp_feat_val_destructor(entry->feat_num, &entry->val); val 492 net/dccp/feat.c new->val = *fval; val 520 net/dccp/feat.c new->val.nn = 0; /* zeroes the whole structure */ val 522 net/dccp/feat.c new->val = *fval; val 582 net/dccp/feat.c static u8 dccp_feat_is_valid_nn_val(u8 feat_num, u64 val) val 586 net/dccp/feat.c return val <= DCCPF_ACK_RATIO_MAX; val 588 net/dccp/feat.c return val >= DCCPF_SEQ_WMIN && val <= DCCPF_SEQ_WMAX; val 594 net/dccp/feat.c static u8 dccp_feat_is_valid_sp_val(u8 feat_num, u8 val) val 598 net/dccp/feat.c return val == DCCPC_CCID2 || val == DCCPC_CCID3; val 606 net/dccp/feat.c return val < 2; val 608 net/dccp/feat.c return val < 16; val 648 net/dccp/feat.c len = pos->val.sp.len; val 649 net/dccp/feat.c ptr = pos->val.sp.vec; val 654 net/dccp/feat.c dccp_encode_value_var(pos->val.nn, ptr, len); val 779 net/dccp/feat.c return entry->val.nn; val 820 net/dccp/feat.c (unsigned long long)entry->val.nn, val 851 net/dccp/feat.c .val = 1 val 860 net/dccp/feat.c .val = 1 val 873 net/dccp/feat.c .val = 0 val 879 net/dccp/feat.c .val = 1 val 885 net/dccp/feat.c .val = 1 val 901 net/dccp/feat.c .val = 0 val 907 net/dccp/feat.c .val = 1 val 913 net/dccp/feat.c .val = 0 val 919 net/dccp/feat.c .val = 1 val 952 net/dccp/feat.c &table[i].val, 1); val 956 net/dccp/feat.c table[i].val); val 984 net/dccp/feat.c if (entry->feat_num == DCCPF_CCID && entry->val.sp.len == 1) val 985 net/dccp/feat.c ccids[entry->is_local] = entry->val.sp.vec[0]; val 1008 net/dccp/feat.c ccid = entry->val.sp.vec[0]; val 1098 net/dccp/feat.c u8 feat, u8 *val, u8 len, const bool server) val 1108 net/dccp/feat.c dccp_feat_print_opt(opt, feat, val, len, is_mandatory); val 1119 net/dccp/feat.c fval.nn = dccp_decode_value_var(val, len); val 1141 net/dccp/feat.c if (dccp_feat_clone_sp_val(&fval, val, 1)) val 1146 net/dccp/feat.c if (dccp_feat_preflist_match(&defval, 1, val, len) > -1) val 1165 net/dccp/feat.c if (dccp_feat_reconcile(&entry->val, val, len, server, true)) { val 1180 net/dccp/feat.c if (!dccp_feat_reconcile(&entry->val, &defval, 1, server, true)) val 1209 net/dccp/feat.c u8 feat, u8 *val, u8 len, const bool server) val 1215 net/dccp/feat.c dccp_feat_print_opt(opt, feat, val, len, is_mandatory); val 1244 net/dccp/feat.c if (len > sizeof(entry->val.nn)) val 1247 net/dccp/feat.c if (entry->val.nn == dccp_decode_value_var(val, len)) val 1259 net/dccp/feat.c if (!dccp_feat_is_valid_sp_val(feat, *val)) val 1263 net/dccp/feat.c plist = val; val 1266 net/dccp/feat.c plist = val + 1; val 1271 net/dccp/feat.c if (dccp_feat_reconcile(&entry->val, plist, plen, server, 0) != *val) { val 1272 net/dccp/feat.c DCCP_WARN("Confirm selected the wrong value %u\n", *val); val 1275 net/dccp/feat.c entry->val.sp.vec[0] = *val; val 1306 net/dccp/feat.c u8 feat, u8 *val, u8 len) val 1314 net/dccp/feat.c dccp_feat_print_opt(opt, feat, val, len, mandatory); val 1335 net/dccp/feat.c fval.nn = dccp_decode_value_var(val, len); val 1351 net/dccp/feat.c fval.nn = dccp_decode_value_var(val, len); val 1358 net/dccp/feat.c if (fval.nn != entry->val.nn) val 1395 net/dccp/feat.c u8 mandatory, u8 opt, u8 feat, u8 *val, u8 len) val 1412 net/dccp/feat.c val, len, server); val 1416 net/dccp/feat.c val, len, server); val 1425 net/dccp/feat.c val, len); val 1446 net/dccp/feat.c u8 *val; val 1474 net/dccp/feat.c if (ccid_get_builtin_ccids(&tx.val, &tx.len)) val 1476 net/dccp/feat.c if (ccid_get_builtin_ccids(&rx.val, &rx.len)) { val 1477 net/dccp/feat.c kfree(tx.val); val 1481 net/dccp/feat.c if (!dccp_feat_prefer(sysctl_dccp_tx_ccid, tx.val, tx.len) || val 1482 net/dccp/feat.c !dccp_feat_prefer(sysctl_dccp_rx_ccid, rx.val, rx.len)) val 1485 net/dccp/feat.c rc = __feat_register_sp(fn, DCCPF_CCID, true, false, tx.val, tx.len); val 1489 net/dccp/feat.c rc = __feat_register_sp(fn, DCCPF_CCID, false, false, rx.val, rx.len); val 1492 net/dccp/feat.c kfree(tx.val); val 1493 net/dccp/feat.c kfree(rx.val); val 1527 net/dccp/feat.c fvals[idx][cur->is_local] = &cur->val; val 67 net/dccp/feat.h dccp_feat_val val; val 97 net/dccp/feat.h u8 val; val 112 net/dccp/feat.h u8 mand, u8 opt, u8 feat, u8 *val, u8 len); val 132 net/dccp/feat.h int dccp_insert_fn_opt(struct sk_buff *skb, u8 type, u8 feat, u8 *val, u8 len, val 501 net/dccp/options.c u8 *val, u8 len, bool repeat_first) val 511 net/dccp/options.c if (unlikely(val == NULL || len == 0)) val 527 net/dccp/options.c *to++ = *val; val 529 net/dccp/options.c memcpy(to, val, len); val 478 net/dccp/proto.c u8 *val; val 484 net/dccp/proto.c val = memdup_user(optval, optlen); val 485 net/dccp/proto.c if (IS_ERR(val)) val 486 net/dccp/proto.c return PTR_ERR(val); val 490 net/dccp/proto.c rc = dccp_feat_register_sp(sk, DCCPF_CCID, 1, val, optlen); val 493 net/dccp/proto.c rc = dccp_feat_register_sp(sk, DCCPF_CCID, 0, val, optlen); val 496 net/dccp/proto.c kfree(val); val 504 net/dccp/proto.c int val, err = 0; val 523 net/dccp/proto.c if (get_user(val, (int __user *)optval)) val 527 net/dccp/proto.c return dccp_setsockopt_service(sk, val, optval, optlen); val 535 net/dccp/proto.c dp->dccps_server_timewait = (val != 0); val 538 net/dccp/proto.c err = dccp_setsockopt_cscov(sk, val, false); val 541 net/dccp/proto.c err = dccp_setsockopt_cscov(sk, val, true); val 546 net/dccp/proto.c else if (val < 0 || val >= DCCPQ_POLICY_MAX) val 549 net/dccp/proto.c dp->dccps_qpolicy = val; val 552 net/dccp/proto.c if (val < 0) val 555 net/dccp/proto.c dp->dccps_tx_qlen = val; val 623 net/dccp/proto.c int val, len; val 641 net/dccp/proto.c val = dp->dccps_mss_cache; val 646 net/dccp/proto.c val = ccid_get_current_tx_ccid(dp); val 647 net/dccp/proto.c if (val < 0) val 651 net/dccp/proto.c val = ccid_get_current_rx_ccid(dp); val 652 net/dccp/proto.c if (val < 0) val 656 net/dccp/proto.c val = dp->dccps_server_timewait; val 659 net/dccp/proto.c val = dp->dccps_pcslen; val 662 net/dccp/proto.c val = dp->dccps_pcrlen; val 665 net/dccp/proto.c val = dp->dccps_qpolicy; val 668 net/dccp/proto.c val = dp->dccps_tx_qlen; val 680 net/dccp/proto.c len = sizeof(val); val 681 net/dccp/proto.c if (put_user(len, optlen) || copy_to_user(optval, &val, len)) val 1221 net/decnet/af_decnet.c int val; val 1231 net/decnet/af_decnet.c val = !skb_queue_empty(&scp->other_receive_queue); val 1233 net/decnet/af_decnet.c val = -ENOTCONN; val 1235 net/decnet/af_decnet.c return val; val 1351 net/decnet/af_decnet.c int val; val 1461 net/decnet/af_decnet.c scp->nonagle = (u.val == 0) ? 0 : TCP_NAGLE_OFF; val 1470 net/decnet/af_decnet.c scp->nonagle = (u.val == 0) ? 0 : TCP_NAGLE_CORK; val 1535 net/decnet/af_decnet.c unsigned int val; val 1598 net/decnet/af_decnet.c val = (scp->nonagle == TCP_NAGLE_OFF); val 1599 net/decnet/af_decnet.c r_data = &val; val 1605 net/decnet/af_decnet.c val = (scp->nonagle == TCP_NAGLE_CORK); val 1606 net/decnet/af_decnet.c r_data = &val; val 324 net/dsa/dsa.c int call_dsa_notifiers(unsigned long val, struct net_device *dev, val 328 net/dsa/dsa.c return atomic_notifier_call_chain(&dsa_notif_chain, val, info); val 38 net/dsa/slave.c static int dsa_slave_phy_write(struct mii_bus *bus, int addr, int reg, u16 val) val 43 net/dsa/slave.c return ds->ops->phy_write(ds, addr, reg, val); val 1375 net/dsa/slave.c static void dsa_slave_notify(struct net_device *dev, unsigned long val) val 1386 net/dsa/slave.c call_dsa_notifiers(val, dev, &rinfo.info); val 836 net/ieee802154/socket.c int val, len; val 848 net/ieee802154/socket.c val = ro->want_ack; val 851 net/ieee802154/socket.c val = ro->want_lqi; val 855 net/ieee802154/socket.c val = WPAN_SECURITY_DEFAULT; val 857 net/ieee802154/socket.c val = WPAN_SECURITY_ON; val 859 net/ieee802154/socket.c val = WPAN_SECURITY_OFF; val 863 net/ieee802154/socket.c val = WPAN_SECURITY_LEVEL_DEFAULT; val 865 net/ieee802154/socket.c val = ro->seclevel; val 873 net/ieee802154/socket.c if (copy_to_user(optval, &val, len)) val 883 net/ieee802154/socket.c int val; val 889 net/ieee802154/socket.c if (get_user(val, (int __user *)optval)) val 896 net/ieee802154/socket.c ro->want_ack = !!val; val 899 net/ieee802154/socket.c ro->want_lqi = !!val; val 908 net/ieee802154/socket.c switch (val) { val 932 net/ieee802154/socket.c if (val < WPAN_SECURITY_LEVEL_DEFAULT || val 933 net/ieee802154/socket.c val > IEEE802154_SCF_SECLEVEL_ENC_MIC128) { val 935 net/ieee802154/socket.c } else if (val == WPAN_SECURITY_LEVEL_DEFAULT) { val 939 net/ieee802154/socket.c ro->seclevel = val; val 123 net/ipv4/devinet.c u32 val = (__force u32) addr ^ net_hash_mix(net); val 125 net/ipv4/devinet.c return hash_32(val, IN4_ADDR_HSIZE_SHIFT); val 2427 net/ipv4/devinet.c int val = *valp; val 2431 net/ipv4/devinet.c if (write && *valp != val) { val 2437 net/ipv4/devinet.c *valp = val; val 2471 net/ipv4/devinet.c int val = *valp; val 2475 net/ipv4/devinet.c if (write && *valp != val) val 319 net/ipv4/fib_semantics.c static inline unsigned int fib_devindex_hashfn(unsigned int val) val 323 net/ipv4/fib_semantics.c return (val ^ val 324 net/ipv4/fib_semantics.c (val >> DEVINDEX_HASHBITS) ^ val 325 net/ipv4/fib_semantics.c (val >> (DEVINDEX_HASHBITS * 2))) & mask; val 331 net/ipv4/fib_semantics.c unsigned int val = init_val; val 333 net/ipv4/fib_semantics.c val ^= (protocol << 8) | scope; val 334 net/ipv4/fib_semantics.c val ^= prefsrc; val 335 net/ipv4/fib_semantics.c val ^= priority; val 337 net/ipv4/fib_semantics.c return val; val 340 net/ipv4/fib_semantics.c static unsigned int fib_info_hashfn_result(unsigned int val) val 344 net/ipv4/fib_semantics.c return (val ^ (val >> 7) ^ (val >> 12)) & mask; val 349 net/ipv4/fib_semantics.c unsigned int val; val 351 net/ipv4/fib_semantics.c val = fib_info_hashfn_1(fi->fib_nhs, fi->fib_protocol, val 356 net/ipv4/fib_semantics.c val ^= fib_devindex_hashfn(fi->nh->id); val 359 net/ipv4/fib_semantics.c val ^= fib_devindex_hashfn(nh->fib_nh_oif); val 363 net/ipv4/fib_semantics.c return fib_info_hashfn_result(val); val 956 net/ipv4/fib_semantics.c u32 fi_val, val; val 968 net/ipv4/fib_semantics.c val = tcp_ca_get_key_by_name(fi->fib_net, tmp, &ecn_ca); val 972 net/ipv4/fib_semantics.c val = nla_get_u32(nla); val 979 net/ipv4/fib_semantics.c if (fi_val != val) val 1198 net/ipv4/fib_semantics.c static inline unsigned int fib_laddr_hashfn(__be32 val) val 1202 net/ipv4/fib_semantics.c return ((__force u32)val ^ val 1203 net/ipv4/fib_semantics.c ((__force u32)val >> 7) ^ val 1204 net/ipv4/fib_semantics.c ((__force u32)val >> 14)) & mask; val 2626 net/ipv4/fib_trie.c __be32 val = htonl(n->key); val 2630 net/ipv4/fib_trie.c seq_printf(seq, " |-- %pI4\n", &val); val 115 net/ipv4/gre_demux.c u8 _val, *val; val 117 net/ipv4/gre_demux.c val = skb_header_pointer(skb, nhs + hdr_len, val 119 net/ipv4/gre_demux.c if (!val) val 122 net/ipv4/gre_demux.c if ((*val & 0xF0) != 0x40) val 106 net/ipv4/ip_sockglue.c int val; val 111 net/ipv4/ip_sockglue.c val = IPCB(skb)->frag_max_size; val 112 net/ipv4/ip_sockglue.c put_cmsg(msg, SOL_IP, IP_RECVFRAGSIZE, sizeof(val), &val); val 245 net/ipv4/ip_sockglue.c int err, val; val 302 net/ipv4/ip_sockglue.c val = *(int *)CMSG_DATA(cmsg); val 303 net/ipv4/ip_sockglue.c if (val < 1 || val > 255) val 305 net/ipv4/ip_sockglue.c ipc->ttl = val; val 309 net/ipv4/ip_sockglue.c val = *(int *)CMSG_DATA(cmsg); val 311 net/ipv4/ip_sockglue.c val = *(u8 *)CMSG_DATA(cmsg); val 314 net/ipv4/ip_sockglue.c if (val < 0 || val > 255) val 316 net/ipv4/ip_sockglue.c ipc->tos = val; val 595 net/ipv4/ip_sockglue.c int val = 0, err; val 624 net/ipv4/ip_sockglue.c if (get_user(val, (int __user *) optval)) val 631 net/ipv4/ip_sockglue.c val = (int) ucval; val 638 net/ipv4/ip_sockglue.c return ip_ra_control(sk, val ? 1 : 0, NULL); val 683 net/ipv4/ip_sockglue.c if (val) val 689 net/ipv4/ip_sockglue.c if (val) val 695 net/ipv4/ip_sockglue.c if (val) val 701 net/ipv4/ip_sockglue.c if (val) val 707 net/ipv4/ip_sockglue.c if (val) val 713 net/ipv4/ip_sockglue.c if (val) val 719 net/ipv4/ip_sockglue.c if (val) val 725 net/ipv4/ip_sockglue.c if (val) { val 740 net/ipv4/ip_sockglue.c if (val) val 747 net/ipv4/ip_sockglue.c val &= ~INET_ECN_MASK; val 748 net/ipv4/ip_sockglue.c val |= inet->tos & INET_ECN_MASK; val 750 net/ipv4/ip_sockglue.c if (inet->tos != val) { val 751 net/ipv4/ip_sockglue.c inet->tos = val; val 752 net/ipv4/ip_sockglue.c sk->sk_priority = rt_tos2priority(val); val 759 net/ipv4/ip_sockglue.c if (val != -1 && (val < 1 || val > 255)) val 761 net/ipv4/ip_sockglue.c inet->uc_ttl = val; val 768 net/ipv4/ip_sockglue.c inet->hdrincl = val ? 1 : 0; val 775 net/ipv4/ip_sockglue.c inet->nodefrag = val ? 1 : 0; val 778 net/ipv4/ip_sockglue.c inet->bind_address_no_port = val ? 1 : 0; val 781 net/ipv4/ip_sockglue.c if (val < IP_PMTUDISC_DONT || val > IP_PMTUDISC_OMIT) val 783 net/ipv4/ip_sockglue.c inet->pmtudisc = val; val 786 net/ipv4/ip_sockglue.c inet->recverr = !!val; val 787 net/ipv4/ip_sockglue.c if (!val) val 795 net/ipv4/ip_sockglue.c if (val == -1) val 796 net/ipv4/ip_sockglue.c val = 1; val 797 net/ipv4/ip_sockglue.c if (val < 0 || val > 255) val 799 net/ipv4/ip_sockglue.c inet->mc_ttl = val; val 804 net/ipv4/ip_sockglue.c inet->mc_loop = !!val; val 815 net/ipv4/ip_sockglue.c ifindex = (__force int)ntohl((__force __be32)val); val 1145 net/ipv4/ip_sockglue.c if (val != 0 && val != 1) val 1147 net/ipv4/ip_sockglue.c inet->mc_all = val; val 1153 net/ipv4/ip_sockglue.c inet->freebind = !!val; val 1165 net/ipv4/ip_sockglue.c if (!!val && !ns_capable(sock_net(sk)->user_ns, CAP_NET_RAW) && val 1172 net/ipv4/ip_sockglue.c inet->transparent = !!val; val 1178 net/ipv4/ip_sockglue.c if (val < 0 || val > 255) val 1180 net/ipv4/ip_sockglue.c inet->min_ttl = val; val 1314 net/ipv4/ip_sockglue.c int val, err = 0; val 1361 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_PKTINFO) != 0; val 1364 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_TTL) != 0; val 1367 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_TOS) != 0; val 1370 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_RECVOPTS) != 0; val 1373 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_RETOPTS) != 0; val 1376 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_PASSSEC) != 0; val 1379 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_ORIGDSTADDR) != 0; val 1382 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_CHECKSUM) != 0; val 1385 net/ipv4/ip_sockglue.c val = (inet->cmsg_flags & IP_CMSG_RECVFRAGSIZE) != 0; val 1388 net/ipv4/ip_sockglue.c val = inet->tos; val 1393 net/ipv4/ip_sockglue.c val = (inet->uc_ttl == -1 ? val 1399 net/ipv4/ip_sockglue.c val = inet->hdrincl; val 1402 net/ipv4/ip_sockglue.c val = inet->nodefrag; val 1405 net/ipv4/ip_sockglue.c val = inet->bind_address_no_port; val 1408 net/ipv4/ip_sockglue.c val = inet->pmtudisc; val 1413 net/ipv4/ip_sockglue.c val = 0; val 1416 net/ipv4/ip_sockglue.c val = dst_mtu(dst); val 1419 net/ipv4/ip_sockglue.c if (!val) { val 1426 net/ipv4/ip_sockglue.c val = inet->recverr; val 1429 net/ipv4/ip_sockglue.c val = inet->mc_ttl; val 1432 net/ipv4/ip_sockglue.c val = inet->mc_loop; val 1435 net/ipv4/ip_sockglue.c val = (__force int)htonl((__u32) inet->uc_index); val 1484 net/ipv4/ip_sockglue.c val = inet->mc_all; val 1519 net/ipv4/ip_sockglue.c val = inet->freebind; val 1522 net/ipv4/ip_sockglue.c val = inet->transparent; val 1525 net/ipv4/ip_sockglue.c val = inet->min_ttl; val 1533 net/ipv4/ip_sockglue.c if (len < sizeof(int) && len > 0 && val >= 0 && val <= 255) { val 1534 net/ipv4/ip_sockglue.c unsigned char ucval = (unsigned char)val; val 1544 net/ipv4/ip_sockglue.c if (copy_to_user(optval, &val, len)) val 1377 net/ipv4/ipmr.c int val, ret = 0, parent = 0; val 1487 net/ipv4/ipmr.c if (optlen != sizeof(val)) { val 1491 net/ipv4/ipmr.c if (get_user(val, (int __user *)optval)) { val 1495 net/ipv4/ipmr.c mroute_clean_tables(mrt, val); val 1499 net/ipv4/ipmr.c if (optlen != sizeof(val)) { val 1503 net/ipv4/ipmr.c if (get_user(val, (int __user *)optval)) { val 1507 net/ipv4/ipmr.c mrt->mroute_do_assert = val; val 1514 net/ipv4/ipmr.c if (optlen != sizeof(val)) { val 1518 net/ipv4/ipmr.c if (get_user(val, (int __user *)optval)) { val 1523 net/ipv4/ipmr.c do_wrvifwhole = (val == IGMPMSG_WRVIFWHOLE); val 1524 net/ipv4/ipmr.c val = !!val; val 1525 net/ipv4/ipmr.c if (val != mrt->mroute_do_pim) { val 1526 net/ipv4/ipmr.c mrt->mroute_do_pim = val; val 1527 net/ipv4/ipmr.c mrt->mroute_do_assert = val; val 1569 net/ipv4/ipmr.c int val; val 1583 net/ipv4/ipmr.c val = 0x0305; val 1588 net/ipv4/ipmr.c val = mrt->mroute_do_pim; val 1591 net/ipv4/ipmr.c val = mrt->mroute_do_assert; val 1604 net/ipv4/ipmr.c if (copy_to_user(optval, &val, olr)) val 22 net/ipv4/metrics.c u32 val; val 35 net/ipv4/metrics.c val = tcp_ca_get_key_by_name(net, tmp, &ecn_ca); val 36 net/ipv4/metrics.c if (val == TCP_CA_UNSPEC) { val 46 net/ipv4/metrics.c val = nla_get_u32(nla); val 48 net/ipv4/metrics.c if (type == RTAX_ADVMSS && val > 65535 - 40) val 49 net/ipv4/metrics.c val = 65535 - 40; val 50 net/ipv4/metrics.c if (type == RTAX_MTU && val > 65535 - 15) val 51 net/ipv4/metrics.c val = 65535 - 15; val 52 net/ipv4/metrics.c if (type == RTAX_HOPLIMIT && val > 255) val 53 net/ipv4/metrics.c val = 255; val 54 net/ipv4/metrics.c if (type == RTAX_FEATURES && (val & ~RTAX_FEATURE_MASK)) { val 58 net/ipv4/metrics.c metrics[type - 1] = val; val 674 net/ipv4/netfilter/ipt_CLUSTERIP.c unsigned long val; /* current value */ val 697 net/ipv4/netfilter/ipt_CLUSTERIP.c idx->val = local_nodes; val 698 net/ipv4/netfilter/ipt_CLUSTERIP.c clear_bit(idx->bit - 1, &idx->val); val 712 net/ipv4/netfilter/ipt_CLUSTERIP.c idx->bit = ffs(idx->val); val 713 net/ipv4/netfilter/ipt_CLUSTERIP.c clear_bit(idx->bit - 1, &idx->val); val 39 net/ipv4/nexthop.c static unsigned int nh_dev_hashfn(unsigned int val) val 43 net/ipv4/nexthop.c return (val ^ val 44 net/ipv4/nexthop.c (val >> NH_DEV_HASHBITS) ^ val 45 net/ipv4/nexthop.c (val >> (NH_DEV_HASHBITS * 2))) & mask; val 318 net/ipv4/proc.c unsigned long vals[PERLINE], val; val 323 net/ipv4/proc.c val = atomic_long_read(&net->mib.icmpmsg_statistics->mibs[i]); val 324 net/ipv4/proc.c if (val) { val 326 net/ipv4/proc.c vals[count++] = val; val 228 net/ipv4/sysctl_net_ipv4.c char val[TCP_CA_NAME_MAX]; val 230 net/ipv4/sysctl_net_ipv4.c .data = val, val 235 net/ipv4/sysctl_net_ipv4.c tcp_get_default_congestion_control(net, val); val 239 net/ipv4/sysctl_net_ipv4.c ret = tcp_set_default_congestion_control(net, val); val 327 net/ipv4/tcp.c unsigned long val; val 331 net/ipv4/tcp.c val = jiffies; val 333 net/ipv4/tcp.c if (!val) val 334 net/ipv4/tcp.c val--; val 335 net/ipv4/tcp.c if (!cmpxchg(&tcp_memory_pressure, 0, val)) val 342 net/ipv4/tcp.c unsigned long val; val 346 net/ipv4/tcp.c val = xchg(&tcp_memory_pressure, 0); val 347 net/ipv4/tcp.c if (val) val 349 net/ipv4/tcp.c jiffies_to_msecs(jiffies - val)); val 1701 net/ipv4/tcp.c int tcp_set_rcvlowat(struct sock *sk, int val) val 1709 net/ipv4/tcp.c val = min(val, cap); val 1710 net/ipv4/tcp.c WRITE_ONCE(sk->sk_rcvlowat, val ? : 1); val 1718 net/ipv4/tcp.c val <<= 1; val 1719 net/ipv4/tcp.c if (val > sk->sk_rcvbuf) { val 1720 net/ipv4/tcp.c WRITE_ONCE(sk->sk_rcvbuf, val); val 1721 net/ipv4/tcp.c tcp_sk(sk)->window_clamp = tcp_win_from_space(sk, val); val 2808 net/ipv4/tcp.c int val; val 2819 net/ipv4/tcp.c val = strncpy_from_user(name, optval, val 2821 net/ipv4/tcp.c if (val < 0) val 2823 net/ipv4/tcp.c name[val] = 0; val 2838 net/ipv4/tcp.c val = strncpy_from_user(name, optval, val 2841 net/ipv4/tcp.c if (val < 0) val 2843 net/ipv4/tcp.c name[val] = 0; val 2877 net/ipv4/tcp.c if (get_user(val, (int __user *)optval)) val 2888 net/ipv4/tcp.c if (val && (val < TCP_MIN_MSS || val > MAX_TCP_WINDOW)) { val 2892 net/ipv4/tcp.c tp->rx_opt.user_mss = val; val 2896 net/ipv4/tcp.c if (val) { val 2913 net/ipv4/tcp.c if (val < 0 || val > 1) val 2916 net/ipv4/tcp.c tp->thin_lto = val; val 2920 net/ipv4/tcp.c if (val < 0 || val > 1) val 2927 net/ipv4/tcp.c else if (val == TCP_REPAIR_ON) { val 2931 net/ipv4/tcp.c } else if (val == TCP_REPAIR_OFF) { val 2935 net/ipv4/tcp.c } else if (val == TCP_REPAIR_OFF_NO_WP) { val 2946 net/ipv4/tcp.c else if ((unsigned int)val < TCP_QUEUES_NR) val 2947 net/ipv4/tcp.c tp->repair_queue = val; val 2956 net/ipv4/tcp.c WRITE_ONCE(tp->write_seq, val); val 2958 net/ipv4/tcp.c WRITE_ONCE(tp->rcv_nxt, val); val 2959 net/ipv4/tcp.c WRITE_ONCE(tp->copied_seq, val); val 2988 net/ipv4/tcp.c if (val) { val 2999 net/ipv4/tcp.c if (val < 1 || val > MAX_TCP_KEEPIDLE) val 3002 net/ipv4/tcp.c tp->keepalive_time = val * HZ; val 3016 net/ipv4/tcp.c if (val < 1 || val > MAX_TCP_KEEPINTVL) val 3019 net/ipv4/tcp.c tp->keepalive_intvl = val * HZ; val 3022 net/ipv4/tcp.c if (val < 1 || val > MAX_TCP_KEEPCNT) val 3025 net/ipv4/tcp.c tp->keepalive_probes = val; val 3028 net/ipv4/tcp.c if (val < 1 || val > MAX_TCP_SYNCNT) val 3031 net/ipv4/tcp.c icsk->icsk_syn_retries = val; val 3035 net/ipv4/tcp.c if (val < 0 || val > 1) val 3038 net/ipv4/tcp.c tp->save_syn = val; val 3042 net/ipv4/tcp.c if (val < 0) val 3044 net/ipv4/tcp.c else if (val > net->ipv4.sysctl_tcp_fin_timeout / HZ) val 3047 net/ipv4/tcp.c tp->linger2 = val * HZ; val 3053 net/ipv4/tcp.c secs_to_retrans(val, TCP_TIMEOUT_INIT / HZ, val 3058 net/ipv4/tcp.c if (!val) { val 3065 net/ipv4/tcp.c tp->window_clamp = val < SOCK_MIN_RCVBUF / 2 ? val 3066 net/ipv4/tcp.c SOCK_MIN_RCVBUF / 2 : val; val 3070 net/ipv4/tcp.c if (!val) { val 3079 net/ipv4/tcp.c if (!(val & 1)) val 3098 net/ipv4/tcp.c if (val < 0) val 3101 net/ipv4/tcp.c icsk->icsk_user_timeout = val; val 3105 net/ipv4/tcp.c if (val >= 0 && ((1 << sk->sk_state) & (TCPF_CLOSE | val 3109 net/ipv4/tcp.c fastopen_queue_tune(sk, val); val 3115 net/ipv4/tcp.c if (val > 1 || val < 0) { val 3119 net/ipv4/tcp.c tp->fastopen_connect = val; val 3127 net/ipv4/tcp.c if (val > 1 || val < 0) val 3132 net/ipv4/tcp.c tp->fastopen_no_cookie = val; val 3138 net/ipv4/tcp.c tp->tsoffset = val - tcp_time_stamp_raw(); val 3144 net/ipv4/tcp.c tp->notsent_lowat = val; val 3148 net/ipv4/tcp.c if (val > 1 || val < 0) val 3151 net/ipv4/tcp.c tp->recvmsg_inq = val; val 3154 net/ipv4/tcp.c if (val) val 3156 net/ipv4/tcp.c tp->tcp_tx_delay = val; val 3417 net/ipv4/tcp.c int val, len; val 3429 net/ipv4/tcp.c val = tp->mss_cache; val 3430 net/ipv4/tcp.c if (!val && ((1 << sk->sk_state) & (TCPF_CLOSE | TCPF_LISTEN))) val 3431 net/ipv4/tcp.c val = tp->rx_opt.user_mss; val 3433 net/ipv4/tcp.c val = tp->rx_opt.mss_clamp; val 3436 net/ipv4/tcp.c val = !!(tp->nonagle&TCP_NAGLE_OFF); val 3439 net/ipv4/tcp.c val = !!(tp->nonagle&TCP_NAGLE_CORK); val 3442 net/ipv4/tcp.c val = keepalive_time_when(tp) / HZ; val 3445 net/ipv4/tcp.c val = keepalive_intvl_when(tp) / HZ; val 3448 net/ipv4/tcp.c val = keepalive_probes(tp); val 3451 net/ipv4/tcp.c val = icsk->icsk_syn_retries ? : net->ipv4.sysctl_tcp_syn_retries; val 3454 net/ipv4/tcp.c val = tp->linger2; val 3455 net/ipv4/tcp.c if (val >= 0) val 3456 net/ipv4/tcp.c val = (val ? : net->ipv4.sysctl_tcp_fin_timeout) / HZ; val 3459 net/ipv4/tcp.c val = retrans_to_secs(icsk->icsk_accept_queue.rskq_defer_accept, val 3463 net/ipv4/tcp.c val = tp->window_clamp; val 3501 net/ipv4/tcp.c val = !inet_csk_in_pingpong_mode(sk); val 3554 net/ipv4/tcp.c val = tp->thin_lto; val 3558 net/ipv4/tcp.c val = 0; val 3562 net/ipv4/tcp.c val = tp->repair; val 3567 net/ipv4/tcp.c val = tp->repair_queue; val 3596 net/ipv4/tcp.c val = tp->write_seq; val 3598 net/ipv4/tcp.c val = tp->rcv_nxt; val 3604 net/ipv4/tcp.c val = icsk->icsk_user_timeout; val 3608 net/ipv4/tcp.c val = icsk->icsk_accept_queue.fastopenq.max_qlen; val 3612 net/ipv4/tcp.c val = tp->fastopen_connect; val 3616 net/ipv4/tcp.c val = tp->fastopen_no_cookie; val 3620 net/ipv4/tcp.c val = tp->tcp_tx_delay; val 3624 net/ipv4/tcp.c val = tcp_time_stamp_raw() + tp->tsoffset; val 3627 net/ipv4/tcp.c val = tp->notsent_lowat; val 3630 net/ipv4/tcp.c val = tp->recvmsg_inq; val 3633 net/ipv4/tcp.c val = tp->save_syn; val 3693 net/ipv4/tcp.c if (copy_to_user(optval, &val, len)) val 293 net/ipv4/tcp_cong.c int tcp_set_allowed_congestion_control(char *val) val 299 net/ipv4/tcp_cong.c saved_clone = clone = kstrdup(val, GFP_USER); val 318 net/ipv4/tcp_cong.c while ((name = strsep(&val, " ")) && *name) { val 121 net/ipv4/tcp_fastopen.c foc->val[0] = cpu_to_le64(siphash(&iph->saddr, val 132 net/ipv4/tcp_fastopen.c foc->val[0] = cpu_to_le64(siphash(&ip6h->saddr, val 3770 net/ipv4/tcp_input.c memcpy(foc->val, cookie, len); val 73 net/ipv4/tcp_metrics.c u32 val) val 75 net/ipv4/tcp_metrics.c tm->tcpm_vals[idx] = val; val 98 net/ipv4/tcp_metrics.c u32 val; val 102 net/ipv4/tcp_metrics.c val = 0; val 104 net/ipv4/tcp_metrics.c val |= 1 << TCP_METRIC_RTT; val 106 net/ipv4/tcp_metrics.c val |= 1 << TCP_METRIC_RTTVAR; val 108 net/ipv4/tcp_metrics.c val |= 1 << TCP_METRIC_SSTHRESH; val 110 net/ipv4/tcp_metrics.c val |= 1 << TCP_METRIC_CWND; val 112 net/ipv4/tcp_metrics.c val |= 1 << TCP_METRIC_REORDERING; val 113 net/ipv4/tcp_metrics.c tm->tcpm_lock = val; val 328 net/ipv4/tcp_metrics.c u32 val; val 389 net/ipv4/tcp_metrics.c val = tcp_metric_get(tm, TCP_METRIC_SSTHRESH); val 390 net/ipv4/tcp_metrics.c if (val && (tp->snd_cwnd >> 1) > val) val 395 net/ipv4/tcp_metrics.c val = tcp_metric_get(tm, TCP_METRIC_CWND); val 396 net/ipv4/tcp_metrics.c if (tp->snd_cwnd > val) val 407 net/ipv4/tcp_metrics.c val = tcp_metric_get(tm, TCP_METRIC_CWND); val 408 net/ipv4/tcp_metrics.c tcp_metric_set(tm, TCP_METRIC_CWND, (val + tp->snd_cwnd) >> 1); val 415 net/ipv4/tcp_metrics.c val = tcp_metric_get(tm, TCP_METRIC_CWND); val 417 net/ipv4/tcp_metrics.c (val + tp->snd_ssthresh) >> 1); val 420 net/ipv4/tcp_metrics.c val = tcp_metric_get(tm, TCP_METRIC_SSTHRESH); val 421 net/ipv4/tcp_metrics.c if (val && tp->snd_ssthresh > val) val 426 net/ipv4/tcp_metrics.c val = tcp_metric_get(tm, TCP_METRIC_REORDERING); val 427 net/ipv4/tcp_metrics.c if (val < tp->reordering && val 445 net/ipv4/tcp_metrics.c u32 val, crtt = 0; /* cached RTT scaled by 8 */ val 461 net/ipv4/tcp_metrics.c val = tcp_metric_get(tm, TCP_METRIC_SSTHRESH); val 462 net/ipv4/tcp_metrics.c if (val) { val 463 net/ipv4/tcp_metrics.c tp->snd_ssthresh = val; val 472 net/ipv4/tcp_metrics.c val = tcp_metric_get(tm, TCP_METRIC_REORDERING); val 473 net/ipv4/tcp_metrics.c if (val && tp->reordering != val) val 474 net/ipv4/tcp_metrics.c tp->reordering = val; val 655 net/ipv4/tcp_metrics.c u32 val = tm->tcpm_vals[i]; val 657 net/ipv4/tcp_metrics.c if (!val) val 661 net/ipv4/tcp_metrics.c val) < 0) val 664 net/ipv4/tcp_metrics.c val = max(val / 1000, 1U); val 668 net/ipv4/tcp_metrics.c val) < 0) val 671 net/ipv4/tcp_metrics.c val = max(val / 1000, 1U); val 673 net/ipv4/tcp_metrics.c if (nla_put_u32(msg, i + 1, val) < 0) val 706 net/ipv4/tcp_metrics.c tfom->cookie.len, tfom->cookie.val) < 0) val 171 net/ipv4/tcp_nv.c inline u32 nv_get_bounded_rtt(struct tcpnv *ca, u32 val) val 173 net/ipv4/tcp_nv.c if (ca->nv_lower_bound_rtt > 0 && val < ca->nv_lower_bound_rtt) val 175 net/ipv4/tcp_nv.c else if (ca->nv_base_rtt > 0 && val > ca->nv_base_rtt) val 178 net/ipv4/tcp_nv.c return val; val 54 net/ipv4/tcp_output.c u64 val = tcp_clock_ns(); val 56 net/ipv4/tcp_output.c tp->tcp_clock_cache = val; val 57 net/ipv4/tcp_output.c tp->tcp_mstamp = div_u64(val, NSEC_PER_USEC); val 543 net/ipv4/tcp_output.c memcpy(p, foc->val, foc->len); val 637 net/ipv4/tcp_timer.c void tcp_set_keepalive(struct sock *sk, int val) val 642 net/ipv4/tcp_timer.c if (val && !sock_flag(sk, SOCK_KEEPOPEN)) val 644 net/ipv4/tcp_timer.c else if (!val) val 2532 net/ipv4/udp.c int val, valbool; val 2539 net/ipv4/udp.c if (get_user(val, (int __user *)optval)) val 2542 net/ipv4/udp.c valbool = val ? 1 : 0; val 2546 net/ipv4/udp.c if (val != 0) { val 2557 net/ipv4/udp.c switch (val) { val 2564 net/ipv4/udp.c up->encap_type = val; val 2584 net/ipv4/udp.c if (val < 0 || val > USHRT_MAX) val 2586 net/ipv4/udp.c up->gso_size = val; val 2605 net/ipv4/udp.c if (val != 0 && val < 8) /* Illegal coverage: use default (8) */ val 2606 net/ipv4/udp.c val = 8; val 2607 net/ipv4/udp.c else if (val > USHRT_MAX) val 2608 net/ipv4/udp.c val = USHRT_MAX; val 2609 net/ipv4/udp.c up->pcslen = val; val 2619 net/ipv4/udp.c if (val != 0 && val < 8) /* Avoid silly minimal values. */ val 2620 net/ipv4/udp.c val = 8; val 2621 net/ipv4/udp.c else if (val > USHRT_MAX) val 2622 net/ipv4/udp.c val = USHRT_MAX; val 2623 net/ipv4/udp.c up->pcrlen = val; val 2660 net/ipv4/udp.c int val, len; val 2672 net/ipv4/udp.c val = up->corkflag; val 2676 net/ipv4/udp.c val = up->encap_type; val 2680 net/ipv4/udp.c val = up->no_check6_tx; val 2684 net/ipv4/udp.c val = up->no_check6_rx; val 2688 net/ipv4/udp.c val = up->gso_size; val 2694 net/ipv4/udp.c val = up->pcslen; val 2698 net/ipv4/udp.c val = up->pcrlen; val 2707 net/ipv4/udp.c if (copy_to_user(optval, &val, len)) val 993 net/ipv6/addrconf.c u32 val = ipv6_addr_hash(addr) ^ net_hash_mix(net); val 995 net/ipv6/addrconf.c return hash_32(val, IN6_ADDR_HSIZE_SHIFT); val 6062 net/ipv6/addrconf.c int val = *valp; val 6072 net/ipv6/addrconf.c lctl.data = &val; val 6077 net/ipv6/addrconf.c ret = addrconf_fixup_forwarding(ctl, valp, val); val 6160 net/ipv6/addrconf.c int val = *valp; val 6170 net/ipv6/addrconf.c lctl.data = &val; val 6175 net/ipv6/addrconf.c ret = addrconf_disable_ipv6(ctl, valp, val); val 6359 net/ipv6/addrconf.c int val = *valp; val 6368 net/ipv6/addrconf.c lctl.data = &val; val 6373 net/ipv6/addrconf.c ret = addrconf_fixup_linkdown(ctl, valp, val); val 6391 net/ipv6/addrconf.c void addrconf_disable_policy_idev(struct inet6_dev *idev, int val) val 6404 net/ipv6/addrconf.c ifa->rt->dst_nopolicy = val ? true : false; val 6410 net/ipv6/addrconf.c addrconf_set_nopolicy(*rtp, val); val 6421 net/ipv6/addrconf.c int addrconf_disable_policy(struct ctl_table *ctl, int *valp, int val) val 6429 net/ipv6/addrconf.c *valp = val; val 6443 net/ipv6/addrconf.c addrconf_disable_policy_idev(idev, val); val 6447 net/ipv6/addrconf.c addrconf_disable_policy_idev(idev, val); val 6460 net/ipv6/addrconf.c int val = *valp; val 6466 net/ipv6/addrconf.c lctl.data = &val; val 6469 net/ipv6/addrconf.c if (write && (*valp != val)) val 6470 net/ipv6/addrconf.c ret = addrconf_disable_policy(ctl, valp, val); val 107 net/ipv6/addrconf_core.c int inet6addr_notifier_call_chain(unsigned long val, void *v) val 109 net/ipv6/addrconf_core.c return atomic_notifier_call_chain(&inet6addr_chain, val, v); val 126 net/ipv6/addrconf_core.c int inet6addr_validator_notifier_call_chain(unsigned long val, void *v) val 128 net/ipv6/addrconf_core.c return blocking_notifier_call_chain(&inet6addr_validator_chain, val, v); val 54 net/ipv6/anycast.c u32 val = ipv6_addr_hash(addr) ^ net_hash_mix(net); val 56 net/ipv6/anycast.c return hash_32(val, IN6_ADDR_HSIZE_SHIFT); val 723 net/ipv6/datagram.c int val = opt->frag_max_size; val 725 net/ipv6/datagram.c put_cmsg(msg, SOL_IPV6, IPV6_RECVFRAGSIZE, sizeof(val), &val); val 659 net/ipv6/ip6_fib.c void fib6_metric_set(struct fib6_info *f6i, int metric, u32 val) val 674 net/ipv6/ip6_fib.c f6i->fib6_metrics->metrics[metric - 1] = val; val 28 net/ipv6/ip6_udp_tunnel.c int val = 1; val 31 net/ipv6/ip6_udp_tunnel.c (char *) &val, sizeof(val)); val 1803 net/ipv6/ip6mr.c int val; val 1817 net/ipv6/ip6mr.c val = 0x0305; val 1821 net/ipv6/ip6mr.c val = mrt->mroute_do_pim; val 1825 net/ipv6/ip6mr.c val = mrt->mroute_do_assert; val 1840 net/ipv6/ip6mr.c if (copy_to_user(optval, &val, olr)) val 144 net/ipv6/ipv6_sockglue.c int val, valbool; val 149 net/ipv6/ipv6_sockglue.c val = 0; val 152 net/ipv6/ipv6_sockglue.c if (get_user(val, (int __user *) optval)) val 155 net/ipv6/ipv6_sockglue.c val = 0; val 158 net/ipv6/ipv6_sockglue.c valbool = (val != 0); val 172 net/ipv6/ipv6_sockglue.c if (val == PF_INET) { val 341 net/ipv6/ipv6_sockglue.c if (val < -1 || val > 0xff) val 344 net/ipv6/ipv6_sockglue.c if (val == -1) val 345 net/ipv6/ipv6_sockglue.c val = 0; val 346 net/ipv6/ipv6_sockglue.c np->tclass = val; val 555 net/ipv6/ipv6_sockglue.c if (val > 255 || val < -1) val 557 net/ipv6/ipv6_sockglue.c np->hop_limit = val; val 566 net/ipv6/ipv6_sockglue.c if (val > 255 || val < -1) val 568 net/ipv6/ipv6_sockglue.c np->mcast_hops = (val == -1 ? IPV6_DEFAULT_MCASTHOPS : val); val 575 net/ipv6/ipv6_sockglue.c if (val != valbool) val 589 net/ipv6/ipv6_sockglue.c ifindex = (__force int)ntohl((__force __be32)val); val 617 net/ipv6/ipv6_sockglue.c if (val) { val 623 net/ipv6/ipv6_sockglue.c dev = dev_get_by_index_rcu(net, val); val 634 net/ipv6/ipv6_sockglue.c sk->sk_bound_dev_if != val && val 638 net/ipv6/ipv6_sockglue.c np->mcast_oif = val; val 792 net/ipv6/ipv6_sockglue.c retv = ip6_ra_control(sk, val); val 803 net/ipv6/ipv6_sockglue.c if (val < IPV6_PMTUDISC_DONT || val > IPV6_PMTUDISC_OMIT) val 805 net/ipv6/ipv6_sockglue.c np->pmtudisc = val; val 811 net/ipv6/ipv6_sockglue.c if (val && val < IPV6_MIN_MTU) val 813 net/ipv6/ipv6_sockglue.c np->frag_size = val; val 820 net/ipv6/ipv6_sockglue.c if (!val) val 852 net/ipv6/ipv6_sockglue.c switch (val & (IPV6_PREFER_SRC_PUBLIC| val 874 net/ipv6/ipv6_sockglue.c switch (val & (IPV6_PREFER_SRC_HOME|IPV6_PREFER_SRC_COA)) { val 889 net/ipv6/ipv6_sockglue.c switch (val & (IPV6_PREFER_SRC_CGA|IPV6_PREFER_SRC_NONCGA)) { val 906 net/ipv6/ipv6_sockglue.c if (val < 0 || val > 255) val 908 net/ipv6/ipv6_sockglue.c np->min_hopcount = val; val 1033 net/ipv6/ipv6_sockglue.c int val; val 1048 net/ipv6/ipv6_sockglue.c val = sk->sk_family; val 1127 net/ipv6/ipv6_sockglue.c val = 0; val 1131 net/ipv6/ipv6_sockglue.c val = dst_mtu(dst); val 1133 net/ipv6/ipv6_sockglue.c if (!val) val 1139 net/ipv6/ipv6_sockglue.c val = sk->sk_ipv6only; val 1143 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.rxinfo; val 1147 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.rxoinfo; val 1151 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.rxhlim; val 1155 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.rxohlim; val 1159 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.srcrt; val 1163 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.osrcrt; val 1185 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.hopopts; val 1189 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.ohopopts; val 1193 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.dstopts; val 1197 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.odstopts; val 1201 net/ipv6/ipv6_sockglue.c val = np->tclass; val 1205 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.rxtclass; val 1209 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.rxflow; val 1213 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.rxpmtu; val 1244 net/ipv6/ipv6_sockglue.c val = inet_sk(sk)->transparent; val 1248 net/ipv6/ipv6_sockglue.c val = inet_sk(sk)->freebind; val 1252 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.rxorigdstaddr; val 1261 net/ipv6/ipv6_sockglue.c val = np->hop_limit; val 1263 net/ipv6/ipv6_sockglue.c val = np->mcast_hops; val 1265 net/ipv6/ipv6_sockglue.c if (val < 0) { val 1269 net/ipv6/ipv6_sockglue.c val = ip6_dst_hoplimit(dst); val 1273 net/ipv6/ipv6_sockglue.c if (val < 0) val 1274 net/ipv6/ipv6_sockglue.c val = sock_net(sk)->ipv6.devconf_all->hop_limit; val 1279 net/ipv6/ipv6_sockglue.c val = np->mc_loop; val 1283 net/ipv6/ipv6_sockglue.c val = np->mcast_oif; val 1287 net/ipv6/ipv6_sockglue.c val = np->mc_all; val 1291 net/ipv6/ipv6_sockglue.c val = (__force int)htonl((__u32) np->ucast_oif); val 1295 net/ipv6/ipv6_sockglue.c val = np->pmtudisc; val 1299 net/ipv6/ipv6_sockglue.c val = np->recverr; val 1303 net/ipv6/ipv6_sockglue.c val = np->sndflow; val 1325 net/ipv6/ipv6_sockglue.c val = ipv6_flowlabel_opt_get(sk, &freq, flags); val 1326 net/ipv6/ipv6_sockglue.c if (val < 0) val 1327 net/ipv6/ipv6_sockglue.c return val; val 1338 net/ipv6/ipv6_sockglue.c val = 0; val 1341 net/ipv6/ipv6_sockglue.c val |= IPV6_PREFER_SRC_TMP; val 1343 net/ipv6/ipv6_sockglue.c val |= IPV6_PREFER_SRC_PUBLIC; val 1346 net/ipv6/ipv6_sockglue.c val |= IPV6_PREFER_SRC_PUBTMP_DEFAULT; val 1350 net/ipv6/ipv6_sockglue.c val |= IPV6_PREFER_SRC_COA; val 1352 net/ipv6/ipv6_sockglue.c val |= IPV6_PREFER_SRC_HOME; val 1356 net/ipv6/ipv6_sockglue.c val = np->min_hopcount; val 1360 net/ipv6/ipv6_sockglue.c val = np->dontfrag; val 1364 net/ipv6/ipv6_sockglue.c val = ip6_autoflowlabel(sock_net(sk), np); val 1368 net/ipv6/ipv6_sockglue.c val = np->rxopt.bits.recvfragsize; val 1372 net/ipv6/ipv6_sockglue.c val = np->rtalert_isolate; val 1381 net/ipv6/ipv6_sockglue.c if (copy_to_user(optval, &val, len)) val 165 net/ipv6/proc.c unsigned long val; val 167 net/ipv6/proc.c val = atomic_long_read(smib + i); val 168 net/ipv6/proc.c if (!val) val 172 net/ipv6/proc.c seq_printf(seq, "%-32s\t%lu\n", name, val); val 1021 net/ipv6/raw.c int val; val 1023 net/ipv6/raw.c if (get_user(val, (int __user *)optval)) val 1030 net/ipv6/raw.c inet_sk(sk)->hdrincl = !!val; val 1048 net/ipv6/raw.c if (val > 0 && (val&1)) val 1050 net/ipv6/raw.c if (val < 0) { val 1054 net/ipv6/raw.c rp->offset = val; val 1115 net/ipv6/raw.c int val, len; val 1122 net/ipv6/raw.c val = inet_sk(sk)->hdrincl; val 1131 net/ipv6/raw.c val = -1; val 1133 net/ipv6/raw.c val = rp->offset; val 1144 net/ipv6/raw.c if (copy_to_user(optval, &val, len)) val 1503 net/ipv6/route.c u32 val; val 1506 net/ipv6/route.c val = jhash(dst, sizeof(*dst), seed); val 1510 net/ipv6/route.c val = jhash(src, sizeof(*src), val); val 1512 net/ipv6/route.c return hash_32(val, FIB6_EXCEPTION_BUCKET_SIZE_SHIFT); val 168 net/ipv6/seg6.c struct in6_addr *val, *t_old, *t_new; val 176 net/ipv6/seg6.c val = nla_data(info->attrs[SEG6_ATTR_DST]); val 177 net/ipv6/seg6.c t_new = kmemdup(val, sizeof(*val), GFP_KERNEL); val 1641 net/iucv/af_iucv.c int val; val 1650 net/iucv/af_iucv.c if (get_user(val, (int __user *) optval)) val 1658 net/iucv/af_iucv.c if (val) val 1667 net/iucv/af_iucv.c if (val < 1 || val > (u16)(~0)) val 1670 net/iucv/af_iucv.c iucv->msglimit = val; val 1691 net/iucv/af_iucv.c unsigned int val; val 1707 net/iucv/af_iucv.c val = (iucv->flags & IUCV_IPRMDATA) ? 1 : 0; val 1711 net/iucv/af_iucv.c val = (iucv->path != NULL) ? iucv->path->msglim /* connected */ val 1718 net/iucv/af_iucv.c val = (iucv->hs_dev) ? iucv->hs_dev->mtu - val 1728 net/iucv/af_iucv.c if (copy_to_user(optval, &val, len)) val 1273 net/kcm/kcmsock.c int val, valbool; val 1282 net/kcm/kcmsock.c if (get_user(val, (int __user *)optval)) val 1285 net/kcm/kcmsock.c valbool = val ? 1 : 0; val 1307 net/kcm/kcmsock.c int val, len; val 1321 net/kcm/kcmsock.c val = kcm->rx_disabled; val 1329 net/kcm/kcmsock.c if (copy_to_user(optval, &val, len)) val 1152 net/l2tp/l2tp_ppp.c int optname, int val) val 1158 net/l2tp/l2tp_ppp.c tunnel->debug = val; val 1175 net/l2tp/l2tp_ppp.c int optname, int val) val 1181 net/l2tp/l2tp_ppp.c if ((val != 0) && (val != 1)) { val 1185 net/l2tp/l2tp_ppp.c session->recv_seq = !!val; val 1192 net/l2tp/l2tp_ppp.c if ((val != 0) && (val != 1)) { val 1196 net/l2tp/l2tp_ppp.c session->send_seq = !!val; val 1200 net/l2tp/l2tp_ppp.c po->chan.hdrlen = val ? PPPOL2TP_L2TP_HDR_SIZE_SEQ : val 1210 net/l2tp/l2tp_ppp.c if ((val != 0) && (val != 1)) { val 1214 net/l2tp/l2tp_ppp.c session->lns_mode = !!val; val 1221 net/l2tp/l2tp_ppp.c session->debug = val; val 1227 net/l2tp/l2tp_ppp.c session->reorder_timeout = msecs_to_jiffies(val); val 1252 net/l2tp/l2tp_ppp.c int val; val 1261 net/l2tp/l2tp_ppp.c if (get_user(val, (int __user *)optval)) val 1279 net/l2tp/l2tp_ppp.c err = pppol2tp_tunnel_setsockopt(sk, tunnel, optname, val); val 1281 net/l2tp/l2tp_ppp.c err = pppol2tp_session_setsockopt(sk, session, optname, val); val 1293 net/l2tp/l2tp_ppp.c int optname, int *val) val 1299 net/l2tp/l2tp_ppp.c *val = tunnel->debug; val 1316 net/l2tp/l2tp_ppp.c int optname, int *val) val 1322 net/l2tp/l2tp_ppp.c *val = session->recv_seq; val 1324 net/l2tp/l2tp_ppp.c "%s: get recv_seq=%d\n", session->name, *val); val 1328 net/l2tp/l2tp_ppp.c *val = session->send_seq; val 1330 net/l2tp/l2tp_ppp.c "%s: get send_seq=%d\n", session->name, *val); val 1334 net/l2tp/l2tp_ppp.c *val = session->lns_mode; val 1336 net/l2tp/l2tp_ppp.c "%s: get lns_mode=%d\n", session->name, *val); val 1340 net/l2tp/l2tp_ppp.c *val = session->debug; val 1342 net/l2tp/l2tp_ppp.c session->name, *val); val 1346 net/l2tp/l2tp_ppp.c *val = (int) jiffies_to_msecs(session->reorder_timeout); val 1348 net/l2tp/l2tp_ppp.c "%s: get reorder_timeout=%d\n", session->name, *val); val 1369 net/l2tp/l2tp_ppp.c int val, len; val 1397 net/l2tp/l2tp_ppp.c err = pppol2tp_tunnel_getsockopt(sk, tunnel, optname, &val); val 1401 net/l2tp/l2tp_ppp.c err = pppol2tp_session_getsockopt(sk, session, optname, &val); val 1410 net/l2tp/l2tp_ppp.c if (copy_to_user((void __user *) optval, &val, len)) val 1139 net/llc/af_llc.c int val = 0, len = 0, rc = -EINVAL; val 1152 net/llc/af_llc.c val = llc->n2; break; val 1154 net/llc/af_llc.c val = llc->n1; break; val 1156 net/llc/af_llc.c val = llc->ack_timer.expire / HZ; break; val 1158 net/llc/af_llc.c val = llc->pf_cycle_timer.expire / HZ; break; val 1160 net/llc/af_llc.c val = llc->rej_sent_timer.expire / HZ; break; val 1162 net/llc/af_llc.c val = llc->busy_state_timer.expire / HZ; break; val 1164 net/llc/af_llc.c val = llc->k; break; val 1166 net/llc/af_llc.c val = llc->rw; break; val 1168 net/llc/af_llc.c val = (llc->cmsg_flags & LLC_CMSG_PKTINFO) != 0; val 1175 net/llc/af_llc.c if (put_user(len, optlen) || copy_to_user(optval, &val, len)) val 1425 net/mac80211/cfg.c u8 val = (params->ext_capab[7] & val 1433 net/mac80211/cfg.c val |= val_msb; val 1436 net/mac80211/cfg.c switch (val) { val 400 net/mac80211/debugfs_netdev.c u8 val; val 403 net/mac80211/debugfs_netdev.c ret = kstrtou8(buf, 0, &val); val 407 net/mac80211/debugfs_netdev.c if (val & ~IEEE80211_WMM_IE_STA_QOSINFO_AC_MASK) val 410 net/mac80211/debugfs_netdev.c ifmgd->uapsd_queues = val; val 428 net/mac80211/debugfs_netdev.c unsigned long val; val 431 net/mac80211/debugfs_netdev.c ret = kstrtoul(buf, 0, &val); val 435 net/mac80211/debugfs_netdev.c if (val & ~IEEE80211_WMM_IE_STA_QOSINFO_SP_MASK) val 438 net/mac80211/debugfs_netdev.c ifmgd->uapsd_max_sp_len = val; val 460 net/mac80211/debugfs_netdev.c u8 val; val 463 net/mac80211/debugfs_netdev.c ret = kstrtou8(buf, 0, &val); val 467 net/mac80211/debugfs_netdev.c ifmgd->tdls_wider_bw_prohibited = !val; val 1594 net/mac80211/iface.c u64 mask, start, addr, val, inc; val 1688 net/mac80211/iface.c val = (start & mask); val 1689 net/mac80211/iface.c addr = (start & ~mask) | (val & mask); val 1700 net/mac80211/iface.c val += inc; val 1713 net/mac80211/iface.c addr = (start & ~mask) | (val & mask); val 13 net/mac80211/michael.c static void michael_block(struct michael_mic_ctx *mctx, u32 val) val 15 net/mac80211/michael.c mctx->l ^= val; val 56 net/mac80211/michael.c u32 val; val 71 net/mac80211/michael.c val = 0x5a; val 73 net/mac80211/michael.c val <<= 8; val 75 net/mac80211/michael.c val |= data[blocks * 4 + left]; val 78 net/mac80211/michael.c michael_block(&mctx, val); val 15 net/mac80211/rc80211_minstrel.h #define MINSTREL_FRAC(val, div) (((val) << MINSTREL_SCALE) / div) val 16 net/mac80211/rc80211_minstrel.h #define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE) val 583 net/mac80211/rx.c #define HE_PREP(f, val) le16_encode_bits(val, IEEE80211_RADIOTAP_HE_##f) val 446 net/mac80211/status.c #define HE_PREP(f, val) le16_encode_bits(val, IEEE80211_RADIOTAP_HE_##f) val 62 net/mac80211/tkip.c static u16 tkipS(u16 val) val 64 net/mac80211/tkip.c return tkip_sbox[val & 0xff] ^ swab16(tkip_sbox[val >> 8]); val 1375 net/mpls/af_mpls.c int val = *(int *)ctl->data; val 1378 net/mpls/af_mpls.c val != oval) { val 1737 net/netfilter/ipvs/ip_vs_ctl.c int val = *valp; val 1741 net/netfilter/ipvs/ip_vs_ctl.c .data = &val, val 1747 net/netfilter/ipvs/ip_vs_ctl.c if (write && (*valp != val)) { val 1748 net/netfilter/ipvs/ip_vs_ctl.c if (val < 0 || val > 3) { val 1751 net/netfilter/ipvs/ip_vs_ctl.c *valp = val; val 1763 net/netfilter/ipvs/ip_vs_ctl.c int val[2]; val 1766 net/netfilter/ipvs/ip_vs_ctl.c .data = &val, val 1771 net/netfilter/ipvs/ip_vs_ctl.c memcpy(val, valp, sizeof(val)); val 1774 net/netfilter/ipvs/ip_vs_ctl.c if (val[0] < 0 || val[1] < 0 || val 1775 net/netfilter/ipvs/ip_vs_ctl.c (val[0] >= val[1] && val[1])) val 1778 net/netfilter/ipvs/ip_vs_ctl.c memcpy(valp, val, sizeof(val)); val 1788 net/netfilter/ipvs/ip_vs_ctl.c int val = *valp; val 1792 net/netfilter/ipvs/ip_vs_ctl.c .data = &val, val 1798 net/netfilter/ipvs/ip_vs_ctl.c if (write && (*valp != val)) { val 1799 net/netfilter/ipvs/ip_vs_ctl.c if (val < 1 || !is_power_of_2(val)) val 1802 net/netfilter/ipvs/ip_vs_ctl.c *valp = val; val 190 net/netfilter/ipvs/ip_vs_proto_sctp.c __le32 cmp, val; val 201 net/netfilter/ipvs/ip_vs_proto_sctp.c val = sctp_compute_cksum(skb, sctphoff); val 203 net/netfilter/ipvs/ip_vs_proto_sctp.c if (val != cmp) { val 1279 net/netfilter/ipvs/ip_vs_sync.c static void set_sock_size(struct sock *sk, int mode, int val) val 1285 net/netfilter/ipvs/ip_vs_sync.c val = clamp_t(int, val, (SOCK_MIN_SNDBUF + 1) / 2, val 1287 net/netfilter/ipvs/ip_vs_sync.c sk->sk_sndbuf = val * 2; val 1290 net/netfilter/ipvs/ip_vs_sync.c val = clamp_t(int, val, (SOCK_MIN_RCVBUF + 1) / 2, val 1292 net/netfilter/ipvs/ip_vs_sync.c sk->sk_rcvbuf = val * 2; val 1341 net/netfilter/ipvs/ip_vs_sync.c static void set_mcast_pmtudisc(struct sock *sk, int val) val 1347 net/netfilter/ipvs/ip_vs_sync.c inet->pmtudisc = val; val 1353 net/netfilter/ipvs/ip_vs_sync.c np->pmtudisc = val; val 2386 net/netfilter/nf_conntrack_core.c int nf_conntrack_set_hashsize(const char *val, const struct kernel_param *kp) val 2396 net/netfilter/nf_conntrack_core.c return param_set_uint(val, kp); val 2398 net/netfilter/nf_conntrack_core.c rc = kstrtouint(val, 0, &hashsize); val 830 net/netfilter/nf_conntrack_netlink.c u_int32_t val; val 853 net/netfilter/nf_conntrack_netlink.c filter->mark.val = ntohl(nla_get_be32(cda[CTA_MARK])); val 892 net/netfilter/nf_conntrack_netlink.c if ((ct->mark & filter->mark.mask) != filter->mark.val) val 597 net/netfilter/nf_conntrack_sip.c unsigned int *val) val 612 net/netfilter/nf_conntrack_sip.c *val = simple_strtoul(start, &end, 0); val 143 net/netfilter/nf_nat_ftp.c static int warn_set(const char *val, const struct kernel_param *kp) val 114 net/netfilter/nf_nat_irc.c static int warn_set(const char *val, const struct kernel_param *kp) val 63 net/netfilter/nf_sockopt.c int val, int get) val 74 net/netfilter/nf_sockopt.c if (val >= ops->get_optmin && val 75 net/netfilter/nf_sockopt.c val < ops->get_optmax) val 78 net/netfilter/nf_sockopt.c if (val >= ops->set_optmin && val 79 net/netfilter/nf_sockopt.c val < ops->set_optmax) val 93 net/netfilter/nf_sockopt.c static int nf_sockopt(struct sock *sk, u_int8_t pf, int val, val 99 net/netfilter/nf_sockopt.c ops = nf_sockopt_find(sk, pf, val, get); val 104 net/netfilter/nf_sockopt.c ret = ops->get(sk, val, opt, len); val 106 net/netfilter/nf_sockopt.c ret = ops->set(sk, val, opt, *len); val 112 net/netfilter/nf_sockopt.c int nf_setsockopt(struct sock *sk, u_int8_t pf, int val, char __user *opt, val 115 net/netfilter/nf_sockopt.c return nf_sockopt(sk, pf, val, opt, &len, 0); val 119 net/netfilter/nf_sockopt.c int nf_getsockopt(struct sock *sk, u_int8_t pf, int val, char __user *opt, val 122 net/netfilter/nf_sockopt.c return nf_sockopt(sk, pf, val, opt, len, 1); val 127 net/netfilter/nf_sockopt.c static int compat_nf_sockopt(struct sock *sk, u_int8_t pf, int val, val 133 net/netfilter/nf_sockopt.c ops = nf_sockopt_find(sk, pf, val, get); val 139 net/netfilter/nf_sockopt.c ret = ops->compat_get(sk, val, opt, len); val 141 net/netfilter/nf_sockopt.c ret = ops->get(sk, val, opt, len); val 144 net/netfilter/nf_sockopt.c ret = ops->compat_set(sk, val, opt, *len); val 146 net/netfilter/nf_sockopt.c ret = ops->set(sk, val, opt, *len); val 154 net/netfilter/nf_sockopt.c int val, char __user *opt, unsigned int len) val 156 net/netfilter/nf_sockopt.c return compat_nf_sockopt(sk, pf, val, opt, &len, 0); val 161 net/netfilter/nf_sockopt.c int val, char __user *opt, int *len) val 163 net/netfilter/nf_sockopt.c return compat_nf_sockopt(sk, pf, val, opt, len, 1); val 4287 net/netfilter/nf_tables_api.c err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &desc, val 4294 net/netfilter/nf_tables_api.c nft_data_release(&elem.key.val, desc.type); val 4568 net/netfilter/nf_tables_api.c err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &d1, val 4649 net/netfilter/nf_tables_api.c elem.priv = nft_set_elem_init(set, &tmpl, elem.key.val.data, data.data, val 4718 net/netfilter/nf_tables_api.c nft_data_release(&elem.key.val, d1.type); val 4839 net/netfilter/nf_tables_api.c err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &desc, val 4851 net/netfilter/nf_tables_api.c elem.priv = nft_set_elem_init(set, &tmpl, elem.key.val.data, NULL, 0, val 4885 net/netfilter/nf_tables_api.c nft_data_release(&elem.key.val, desc.type); val 7330 net/netfilter/nf_tables_api.c u32 val; val 7332 net/netfilter/nf_tables_api.c val = ntohl(nla_get_be32(attr)); val 7333 net/netfilter/nf_tables_api.c if (val > max) val 7336 net/netfilter/nf_tables_api.c *dest = val; val 129 net/netfilter/nfnetlink_osf.c if (f->wss.val == 0 || ctx->window == f->wss.val) val 141 net/netfilter/nfnetlink_osf.c if (ctx->window == f->wss.val * mss || val 142 net/netfilter/nfnetlink_osf.c ctx->window == f->wss.val * SMART_MSS_1 || val 143 net/netfilter/nfnetlink_osf.c ctx->window == f->wss.val * SMART_MSS_2) val 147 net/netfilter/nfnetlink_osf.c if (ctx->window == f->wss.val * (mss + 40) || val 148 net/netfilter/nfnetlink_osf.c ctx->window == f->wss.val * (SMART_MSS_1 + 40) || val 149 net/netfilter/nfnetlink_osf.c ctx->window == f->wss.val * (SMART_MSS_2 + 40)) val 153 net/netfilter/nfnetlink_osf.c if ((ctx->window % f->wss.val) == 0) val 114 net/netfilter/nft_set_bitmap.c if (memcmp(nft_set_ext_key(&be->ext), elem->key.val.data, set->klen) || val 201 net/netfilter/nft_set_bitmap.c nft_bitmap_location(set, elem->key.val.data, &idx, &off); val 103 net/netfilter/nft_set_hash.c .key = elem->key.val.data, val 167 net/netfilter/nft_set_hash.c .key = elem->key.val.data, val 213 net/netfilter/nft_set_hash.c .key = elem->key.val.data, val 450 net/netfilter/nft_set_hash.c hash = jhash(elem->key.val.data, set->klen, priv->seed); val 453 net/netfilter/nft_set_hash.c if (!memcmp(nft_set_ext_key(&he->ext), elem->key.val.data, set->klen) && val 550 net/netfilter/nft_set_hash.c if (!memcmp(nft_set_ext_key(&he->ext), &elem->key.val, val 199 net/netfilter/nft_set_rbtree.c const u32 *key = (const u32 *)&elem->key.val; val 326 net/netfilter/nft_set_rbtree.c d = memcmp(nft_set_ext_key(&rbe->ext), &elem->key.val, val 27 net/netfilter/xt_u32.c u_int32_t val; val 44 net/netfilter/xt_u32.c val = ntohl(n); val 52 net/netfilter/xt_u32.c val &= number; val 55 net/netfilter/xt_u32.c val <<= number; val 58 net/netfilter/xt_u32.c val >>= number; val 61 net/netfilter/xt_u32.c if (at + val < at) val 63 net/netfilter/xt_u32.c at += val; val 72 net/netfilter/xt_u32.c val = ntohl(n); val 80 net/netfilter/xt_u32.c if (ct->value[i].min <= val && val <= ct->value[i].max) val 107 net/netlabel/netlabel_domainhash.c u32 val; val 113 net/netlabel/netlabel_domainhash.c for (iter = 0, val = 0, len = strlen(key); iter < len; iter++) val 114 net/netlabel/netlabel_domainhash.c val = (val << 4 | (val >> (8 * sizeof(u32) - 4))) ^ key[iter]; val 115 net/netlabel/netlabel_domainhash.c return val & (netlbl_domhsh_rcu_deref(netlbl_domhsh)->size - 1); val 1407 net/netlink/af_netlink.c int val; val 1467 net/netlink/af_netlink.c val = netlink_broadcast_deliver(sk, p->skb2); val 1468 net/netlink/af_netlink.c if (val < 0) { val 1473 net/netlink/af_netlink.c p->congested |= val; val 1627 net/netlink/af_netlink.c unsigned int val = 0; val 1634 net/netlink/af_netlink.c get_user(val, (unsigned int __user *)optval)) val 1639 net/netlink/af_netlink.c if (val) val 1652 net/netlink/af_netlink.c if (!val || val - 1 >= nlk->ngroups) val 1655 net/netlink/af_netlink.c err = nlk->netlink_bind(sock_net(sk), val); val 1660 net/netlink/af_netlink.c netlink_update_socket_mc(nlk, val, val 1664 net/netlink/af_netlink.c nlk->netlink_unbind(sock_net(sk), val); val 1670 net/netlink/af_netlink.c if (val) val 1677 net/netlink/af_netlink.c if (val) { val 1690 net/netlink/af_netlink.c if (val) val 1697 net/netlink/af_netlink.c if (val) val 1704 net/netlink/af_netlink.c if (val) val 1711 net/netlink/af_netlink.c if (val) val 1728 net/netlink/af_netlink.c int len, val, err; val 1743 net/netlink/af_netlink.c val = nlk->flags & NETLINK_F_RECV_PKTINFO ? 1 : 0; val 1745 net/netlink/af_netlink.c put_user(val, optval)) val 1753 net/netlink/af_netlink.c val = nlk->flags & NETLINK_F_BROADCAST_SEND_ERROR ? 1 : 0; val 1755 net/netlink/af_netlink.c put_user(val, optval)) val 1763 net/netlink/af_netlink.c val = nlk->flags & NETLINK_F_RECV_NO_ENOBUFS ? 1 : 0; val 1765 net/netlink/af_netlink.c put_user(val, optval)) val 1795 net/netlink/af_netlink.c val = nlk->flags & NETLINK_F_CAP_ACK ? 1 : 0; val 1797 net/netlink/af_netlink.c put_user(val, optval)) val 1805 net/netlink/af_netlink.c val = nlk->flags & NETLINK_F_EXT_ACK ? 1 : 0; val 1806 net/netlink/af_netlink.c if (put_user(len, optlen) || put_user(val, optval)) val 1814 net/netlink/af_netlink.c val = nlk->flags & NETLINK_F_STRICT_CHK ? 1 : 0; val 1815 net/netlink/af_netlink.c if (put_user(len, optlen) || put_user(val, optval)) val 331 net/netrom/af_netrom.c int val = 0; val 345 net/netrom/af_netrom.c val = nr->t1 / HZ; val 349 net/netrom/af_netrom.c val = nr->t2 / HZ; val 353 net/netrom/af_netrom.c val = nr->n2; val 357 net/netrom/af_netrom.c val = nr->t4 / HZ; val 361 net/netrom/af_netrom.c val = nr->idle / (60 * HZ); val 373 net/netrom/af_netrom.c return copy_to_user(optval, &val, len) ? -EFAULT : 0; val 210 net/nfc/nci/core.c __u8 *val; val 223 net/nfc/nci/core.c memcpy(cmd.param.val, param->val, param->len); val 613 net/nfc/nci/core.c int nci_set_config(struct nci_dev *ndev, __u8 id, size_t len, __u8 *val) val 617 net/nfc/nci/core.c if (!val || !len) val 622 net/nfc/nci/core.c param.val = val; val 736 net/nfc/nci/core.c param.val = nfc_get_local_general_bytes(nfc_dev, ¶m.len); val 737 net/nfc/nci/core.c if ((param.val == NULL) || (param.len == 0)) val 760 net/nfc/nci/core.c __u8 val; val 762 net/nfc/nci/core.c val = NCI_LA_SEL_INFO_NFC_DEP_MASK; val 764 net/nfc/nci/core.c rc = nci_set_config(ndev, NCI_LA_SEL_INFO, 1, &val); val 768 net/nfc/nci/core.c val = NCI_LF_PROTOCOL_TYPE_NFC_DEP_MASK; val 770 net/nfc/nci/core.c rc = nci_set_config(ndev, NCI_LF_PROTOCOL_TYPE, 1, &val); val 774 net/nfc/nci/core.c val = NCI_LF_CON_BITR_F_212 | NCI_LF_CON_BITR_F_424; val 776 net/nfc/nci/core.c return nci_set_config(ndev, NCI_LF_CON_BITR_F, 1, &val); val 1719 net/openvswitch/flow_netlink.c static void nlattr_set(struct nlattr *attr, u8 val, val 1728 net/openvswitch/flow_netlink.c nlattr_set(nla, val, tbl[nla_type(nla)].next ? : tbl); val 1730 net/openvswitch/flow_netlink.c memset(nla_data(nla), val, nla_len(nla)); val 1737 net/openvswitch/flow_netlink.c static void mask_set_nlattr(struct nlattr *attr, u8 val) val 1739 net/openvswitch/flow_netlink.c nlattr_set(attr, val, ovs_key_lens); val 1328 net/packet/af_packet.c unsigned int val = atomic_inc_return(&f->rr_cur); val 1330 net/packet/af_packet.c return val % num; val 3716 net/packet/af_packet.c int val; val 3718 net/packet/af_packet.c if (optlen != sizeof(val)) val 3720 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3723 net/packet/af_packet.c pkt_sk(sk)->copy_thresh = val; val 3728 net/packet/af_packet.c int val; val 3730 net/packet/af_packet.c if (optlen != sizeof(val)) val 3732 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3734 net/packet/af_packet.c switch (val) { val 3746 net/packet/af_packet.c po->tp_version = val; val 3754 net/packet/af_packet.c unsigned int val; val 3756 net/packet/af_packet.c if (optlen != sizeof(val)) val 3758 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3760 net/packet/af_packet.c if (val > INT_MAX) val 3766 net/packet/af_packet.c po->tp_reserve = val; val 3774 net/packet/af_packet.c unsigned int val; val 3776 net/packet/af_packet.c if (optlen != sizeof(val)) val 3778 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3785 net/packet/af_packet.c po->tp_loss = !!val; val 3793 net/packet/af_packet.c int val; val 3795 net/packet/af_packet.c if (optlen < sizeof(val)) val 3797 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3801 net/packet/af_packet.c po->auxdata = !!val; val 3807 net/packet/af_packet.c int val; val 3809 net/packet/af_packet.c if (optlen < sizeof(val)) val 3811 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3815 net/packet/af_packet.c po->origdev = !!val; val 3821 net/packet/af_packet.c int val; val 3825 net/packet/af_packet.c if (optlen < sizeof(val)) val 3827 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3834 net/packet/af_packet.c po->has_vnet_hdr = !!val; val 3842 net/packet/af_packet.c int val; val 3844 net/packet/af_packet.c if (optlen != sizeof(val)) val 3846 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3849 net/packet/af_packet.c po->tp_tstamp = val; val 3854 net/packet/af_packet.c int val; val 3856 net/packet/af_packet.c if (optlen != sizeof(val)) val 3858 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3861 net/packet/af_packet.c return fanout_add(sk, val & 0xffff, val >> 16); val 3872 net/packet/af_packet.c int val; val 3874 net/packet/af_packet.c if (optlen != sizeof(val)) val 3876 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3878 net/packet/af_packet.c if (val < 0 || val > 1) val 3881 net/packet/af_packet.c po->prot_hook.ignore_outgoing = !!val; val 3886 net/packet/af_packet.c unsigned int val; val 3888 net/packet/af_packet.c if (optlen != sizeof(val)) val 3890 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3897 net/packet/af_packet.c po->tp_tx_has_off = !!val; val 3905 net/packet/af_packet.c int val; val 3907 net/packet/af_packet.c if (optlen != sizeof(val)) val 3909 net/packet/af_packet.c if (copy_from_user(&val, optval, sizeof(val))) val 3912 net/packet/af_packet.c po->xmit = val ? packet_direct_xmit : dev_queue_xmit; val 3924 net/packet/af_packet.c int val, lv = sizeof(val); val 3927 net/packet/af_packet.c void *data = &val; val 3963 net/packet/af_packet.c val = po->auxdata; val 3966 net/packet/af_packet.c val = po->origdev; val 3969 net/packet/af_packet.c val = po->has_vnet_hdr; val 3972 net/packet/af_packet.c val = po->tp_version; val 3979 net/packet/af_packet.c if (copy_from_user(&val, optval, len)) val 3981 net/packet/af_packet.c switch (val) { val 3983 net/packet/af_packet.c val = sizeof(struct tpacket_hdr); val 3986 net/packet/af_packet.c val = sizeof(struct tpacket2_hdr); val 3989 net/packet/af_packet.c val = sizeof(struct tpacket3_hdr); val 3996 net/packet/af_packet.c val = po->tp_reserve; val 3999 net/packet/af_packet.c val = po->tp_loss; val 4002 net/packet/af_packet.c val = po->tp_tstamp; val 4005 net/packet/af_packet.c val = (po->fanout ? val 4012 net/packet/af_packet.c val = po->prot_hook.ignore_outgoing; val 4024 net/packet/af_packet.c val = po->tp_tx_has_off; val 4027 net/packet/af_packet.c val = packet_use_direct_xmit(po); val 119 net/packet/diag.c u32 val; val 121 net/packet/diag.c val = (u32)po->fanout->id | ((u32)po->fanout->type << 16); val 122 net/packet/diag.c ret = nla_put_u32(nlskb, PACKET_DIAG_FANOUT, val); val 981 net/phonet/pep.c int val = 0, err = 0; val 986 net/phonet/pep.c if (get_user(val, (int __user *) optval)) val 993 net/phonet/pep.c if (val && val != PNPIPE_ENCAP_IP) { val 997 net/phonet/pep.c if (!pn->ifindex == !val) val 1003 net/phonet/pep.c if (val) { val 1020 net/phonet/pep.c (val >= 0) && (val < PN_PIPE_INVALID_HANDLE)) val 1021 net/phonet/pep.c pn->pipe_handle = val; val 1027 net/phonet/pep.c pn->init_enable = !!val; val 1043 net/phonet/pep.c int len, val; val 1052 net/phonet/pep.c val = pn->ifindex ? PNPIPE_ENCAP_IP : PNPIPE_ENCAP_NONE; val 1056 net/phonet/pep.c val = pn->ifindex; val 1060 net/phonet/pep.c val = pn->pipe_handle; val 1061 net/phonet/pep.c if (val == PN_PIPE_INVALID_HANDLE) val 1066 net/phonet/pep.c val = pn->init_enable; val 1076 net/phonet/pep.c if (put_user(val, (int __user *) optval)) val 386 net/rds/af_rds.c int val, valbool; val 391 net/rds/af_rds.c if (get_user(val, (int __user *)optval)) val 394 net/rds/af_rds.c valbool = val ? 1 : 0; val 420 net/rds/ib.h u32 rds_ib_ring_alloc(struct rds_ib_work_ring *ring, u32 val, u32 *pos); val 421 net/rds/ib.h void rds_ib_ring_free(struct rds_ib_work_ring *ring, u32 val); val 422 net/rds/ib.h void rds_ib_ring_unalloc(struct rds_ib_work_ring *ring, u32 val); val 97 net/rds/ib_ring.c u32 rds_ib_ring_alloc(struct rds_ib_work_ring *ring, u32 val, u32 *pos) val 103 net/rds/ib_ring.c rdsdebug("ring %p val %u next %u free %u\n", ring, val, val 106 net/rds/ib_ring.c if (val && avail) { val 107 net/rds/ib_ring.c ret = min(val, avail); val 117 net/rds/ib_ring.c void rds_ib_ring_free(struct rds_ib_work_ring *ring, u32 val) val 119 net/rds/ib_ring.c ring->w_free_ptr = (ring->w_free_ptr + val) % ring->w_nr; val 120 net/rds/ib_ring.c atomic_add(val, &ring->w_free_ctr); val 127 net/rds/ib_ring.c void rds_ib_ring_unalloc(struct rds_ib_work_ring *ring, u32 val) val 129 net/rds/ib_ring.c ring->w_alloc_ptr = (ring->w_alloc_ptr - val) % ring->w_nr; val 130 net/rds/ib_ring.c ring->w_alloc_ctr -= val; val 96 net/rds/tcp.c int val = 1; val 98 net/rds/tcp.c kernel_setsockopt(sock, SOL_TCP, TCP_NODELAY, (void *)&val, val 99 net/rds/tcp.c sizeof(val)); val 41 net/rds/tcp_send.c static void rds_tcp_cork(struct socket *sock, int val) val 43 net/rds/tcp_send.c kernel_setsockopt(sock, SOL_TCP, TCP_CORK, (void *)&val, sizeof(val)); val 410 net/rose/af_rose.c int val = 0; val 424 net/rose/af_rose.c val = rose->defer; val 428 net/rose/af_rose.c val = rose->t1 / HZ; val 432 net/rose/af_rose.c val = rose->t2 / HZ; val 436 net/rose/af_rose.c val = rose->t3 / HZ; val 440 net/rose/af_rose.c val = rose->hb / HZ; val 444 net/rose/af_rose.c val = rose->idle / (60 * HZ); val 448 net/rose/af_rose.c val = rose->qbitincl; val 460 net/rose/af_rose.c return copy_to_user(optval, &val, len) ? -EFAULT : 0; val 570 net/sched/act_ct.c void *val, int val_type, val 576 net/sched/act_ct.c nla_memcpy(val, tb[val_type], len); val 767 net/sched/act_ct.c void *val, int val_type, val 776 net/sched/act_ct.c err = nla_put(skb, val_type, len, val); val 140 net/sched/act_ife.c int ife_validate_meta_u32(void *val, int len) val 149 net/sched/act_ife.c int ife_validate_meta_u16(void *val, int len) val 227 net/sched/act_ife.c static int ife_validate_metatype(struct tcf_meta_ops *ops, void *val, int len) val 237 net/sched/act_ife.c return ops->validate(val, len); val 240 net/sched/act_ife.c ret = ife_validate_meta_u32(val, len); val 242 net/sched/act_ife.c ret = ife_validate_meta_u16(val, len); val 265 net/sched/act_ife.c static int load_metaops_and_vet(u32 metaid, void *val, int len, bool rtnl_held) val 285 net/sched/act_ife.c ret = ife_validate_metatype(ops, val, len); val 445 net/sched/act_ife.c void *val; val 449 net/sched/act_ife.c val = nla_data(tb[i]); val 452 net/sched/act_ife.c rc = load_metaops_and_vet(i, val, len, rtnl_held); val 456 net/sched/act_ife.c rc = add_metainfo(ife, i, val, len, exists); val 332 net/sched/act_pedit.c u32 val; val 382 net/sched/act_pedit.c val = tkey->val; val 385 net/sched/act_pedit.c val = (*ptr + tkey->val) & ~tkey->mask; val 393 net/sched/act_pedit.c *ptr = ((*ptr & tkey->mask) ^ val); val 3516 net/sched/cls_api.c entry->mangle.val = tcf_pedit_val(act, k); val 710 net/sched/cls_flower.c void *val, int val_type, val 715 net/sched/cls_flower.c nla_memcpy(val, tb[val_type], len); val 1964 net/sched/cls_flower.c void *val, int val_type, val 1971 net/sched/cls_flower.c err = nla_put(skb, val_type, len, val); val 58 net/sched/cls_u32.c u32 val; val 140 net/sched/cls_u32.c if ((skb->mark & n->mask) != n->val) { val 158 net/sched/cls_u32.c if ((*data ^ key->val) & key->mask) { val 543 net/sched/cls_u32.c cls_u32.knode.val = n->val; val 546 net/sched/cls_u32.c cls_u32.knode.val = 0; val 828 net/sched/cls_u32.c new->val = n->val; val 1063 net/sched/cls_u32.c n->val = mark->val; val 1189 net/sched/cls_u32.c cls_u32.knode.val = n->val; val 1192 net/sched/cls_u32.c cls_u32.knode.val = 0; val 1323 net/sched/cls_u32.c if ((n->val || n->mask)) { val 1324 net/sched/cls_u32.c struct tc_u32_mark mark = {.val = n->val, val 26 net/sched/em_cmp.c u32 val = 0; val 33 net/sched/em_cmp.c val = *ptr; val 37 net/sched/em_cmp.c val = get_unaligned_be16(ptr); val 40 net/sched/em_cmp.c val = be16_to_cpu(val); val 47 net/sched/em_cmp.c val = get_unaligned_be32(ptr); val 50 net/sched/em_cmp.c val = be32_to_cpu(val); val 58 net/sched/em_cmp.c val &= cmp->mask; val 62 net/sched/em_cmp.c return val == cmp->val; val 64 net/sched/em_cmp.c return val < cmp->val; val 66 net/sched/em_cmp.c return val > cmp->val; val 80 net/sched/em_meta.c unsigned long val; val 673 net/sched/em_meta.c static inline struct meta_ops *meta_ops(struct meta_value *val) val 675 net/sched/em_meta.c return &__meta_ops[meta_type(val)][meta_id(val)]; val 696 net/sched/em_meta.c dst->val = (unsigned long)kmemdup(nla_data(nla), len, GFP_KERNEL); val 697 net/sched/em_meta.c if (dst->val == 0UL) val 705 net/sched/em_meta.c kfree((void *) v->val); val 719 net/sched/em_meta.c if (v->val && v->len && val 720 net/sched/em_meta.c nla_put(skb, tlv, v->len, (void *) v->val)) val 748 net/sched/em_meta.c dst->val = *(unsigned long *) nla_data(nla); val 751 net/sched/em_meta.c dst->val = nla_get_u32(nla); val 765 net/sched/em_meta.c if (v->val) val 766 net/sched/em_meta.c dst->value &= v->val; val 772 net/sched/em_meta.c if (nla_put(skb, tlv, sizeof(unsigned long), &v->val)) val 775 net/sched/em_meta.c if (nla_put_u32(skb, tlv, v->val)) val 828 net/sched/em_meta.c dst->value = v->val; val 894 net/sched/em_meta.c static inline int meta_is_supported(struct meta_value *val) val 896 net/sched/em_meta.c return !meta_id(val) || meta_ops(val)->get; val 34 net/sched/em_u32.c return !(((*(__be32 *) ptr) ^ key->val) & key->mask); val 376 net/sched/sch_cake.c u64 val; val 380 net/sched/sch_cake.c val = (3LL << 32) - ((u64)vars->count * invsqrt2); val 382 net/sched/sch_cake.c val >>= 2; /* avoid overflow in following multiply */ val 383 net/sched/sch_cake.c val = (val * invsqrt) >> (32 - 2 + 1); val 385 net/sched/sch_cake.c vars->rec_inv_sqrt = val; val 158 net/sched/sch_codel.c u64 val = nla_get_u32(tb[TCA_CODEL_CE_THRESHOLD]); val 160 net/sched/sch_codel.c q->params.ce_threshold = (val * NSEC_PER_USEC) >> CODEL_SHIFT; val 399 net/sched/sch_fq_codel.c u64 val = nla_get_u32(tb[TCA_FQ_CODEL_CE_THRESHOLD]); val 401 net/sched/sch_fq_codel.c q->cparams.ce_threshold = (val * NSEC_PER_USEC) >> CODEL_SHIFT; val 400 net/sched/sch_generic.c unsigned long val, res; val 409 net/sched/sch_generic.c val = netdev_get_tx_queue(dev, i)->trans_start; val 410 net/sched/sch_generic.c if (val && time_after(val, res)) val 411 net/sched/sch_generic.c res = val; val 1159 net/sched/sch_generic.c int val; val 1167 net/sched/sch_generic.c val = (qdisc_is_running(q) || val 1172 net/sched/sch_generic.c if (val) val 292 net/sched/sch_hhf.c u32 val; val 299 net/sched/sch_hhf.c val = q->hhf_arrays[i][filter_pos[i]] + pkt_len; val 300 net/sched/sch_hhf.c if (min_hhf_val > val) val 301 net/sched/sch_hhf.c min_hhf_val = val; val 150 net/sched/sch_sfq.c static inline struct sfq_head *sfq_dep_head(struct sfq_sched_data *q, sfq_index val) val 152 net/sched/sch_sfq.c if (val < SFQ_MAX_FLOWS) val 153 net/sched/sch_sfq.c return &q->slots[val].dep; val 154 net/sched/sch_sfq.c return &q->dep[val - SFQ_MAX_FLOWS]; val 72 net/sctp/input.c __le32 val = sctp_compute_cksum(skb, 0); val 74 net/sctp/input.c if (val != cmp) { val 2210 net/sctp/socket.c int val; val 2215 net/sctp/socket.c if (get_user(val, (int __user *)optval)) val 2218 net/sctp/socket.c sctp_sk(sk)->disable_fragments = (val == 0) ? 0 : 1; val 3083 net/sctp/socket.c int val; val 3087 net/sctp/socket.c if (get_user(val, (int __user *)optval)) val 3090 net/sctp/socket.c sctp_sk(sk)->nodelay = (val == 0) ? 0 : 1; val 3242 net/sctp/socket.c int val; val 3247 net/sctp/socket.c if (get_user(val, (int __user *)optval)) val 3249 net/sctp/socket.c if (val) val 3289 net/sctp/socket.c int val; val 3297 net/sctp/socket.c if (copy_from_user(&val, optval, optlen)) val 3303 net/sctp/socket.c val = params.assoc_value; val 3313 net/sctp/socket.c if (val) { val 3321 net/sctp/socket.c if (val < min_len || val > max_len) val 3326 net/sctp/socket.c asoc->user_frag = val; val 3329 net/sctp/socket.c sp->user_frag = val; val 3503 net/sctp/socket.c int val; val 3507 net/sctp/socket.c if (get_user(val, (int __user *)optval)) val 3510 net/sctp/socket.c sctp_sk(sk)->frag_interleave = !!val; val 3539 net/sctp/socket.c u32 val; val 3543 net/sctp/socket.c if (get_user(val, (int __user *)optval)) val 3549 net/sctp/socket.c if (val > (sk->sk_rcvbuf >> 1)) val 3552 net/sctp/socket.c sctp_sk(sk)->pd_point = val; val 3629 net/sctp/socket.c struct sctp_authchunk val; val 3636 net/sctp/socket.c if (copy_from_user(&val, optval, optlen)) val 3639 net/sctp/socket.c switch (val.sauth_chunk) { val 3648 net/sctp/socket.c return sctp_auth_ep_add_chunkid(ep, val.sauth_chunk); val 3769 net/sctp/socket.c struct sctp_authkeyid val; val 3774 net/sctp/socket.c if (copy_from_user(&val, optval, optlen)) val 3777 net/sctp/socket.c asoc = sctp_id2assoc(sk, val.scact_assoc_id); val 3778 net/sctp/socket.c if (!asoc && val.scact_assoc_id > SCTP_ALL_ASSOC && val 3783 net/sctp/socket.c return sctp_auth_set_active_key(ep, asoc, val.scact_keynumber); val 3786 net/sctp/socket.c val.scact_assoc_id = SCTP_FUTURE_ASSOC; val 3788 net/sctp/socket.c if (val.scact_assoc_id == SCTP_FUTURE_ASSOC || val 3789 net/sctp/socket.c val.scact_assoc_id == SCTP_ALL_ASSOC) { val 3790 net/sctp/socket.c ret = sctp_auth_set_active_key(ep, asoc, val.scact_keynumber); val 3795 net/sctp/socket.c if (val.scact_assoc_id == SCTP_CURRENT_ASSOC || val 3796 net/sctp/socket.c val.scact_assoc_id == SCTP_ALL_ASSOC) { val 3799 net/sctp/socket.c val.scact_keynumber); val 3820 net/sctp/socket.c struct sctp_authkeyid val; val 3825 net/sctp/socket.c if (copy_from_user(&val, optval, optlen)) val 3828 net/sctp/socket.c asoc = sctp_id2assoc(sk, val.scact_assoc_id); val 3829 net/sctp/socket.c if (!asoc && val.scact_assoc_id > SCTP_ALL_ASSOC && val 3834 net/sctp/socket.c return sctp_auth_del_key_id(ep, asoc, val.scact_keynumber); val 3837 net/sctp/socket.c val.scact_assoc_id = SCTP_FUTURE_ASSOC; val 3839 net/sctp/socket.c if (val.scact_assoc_id == SCTP_FUTURE_ASSOC || val 3840 net/sctp/socket.c val.scact_assoc_id == SCTP_ALL_ASSOC) { val 3841 net/sctp/socket.c ret = sctp_auth_del_key_id(ep, asoc, val.scact_keynumber); val 3846 net/sctp/socket.c if (val.scact_assoc_id == SCTP_CURRENT_ASSOC || val 3847 net/sctp/socket.c val.scact_assoc_id == SCTP_ALL_ASSOC) { val 3850 net/sctp/socket.c val.scact_keynumber); val 3870 net/sctp/socket.c struct sctp_authkeyid val; val 3875 net/sctp/socket.c if (copy_from_user(&val, optval, optlen)) val 3878 net/sctp/socket.c asoc = sctp_id2assoc(sk, val.scact_assoc_id); val 3879 net/sctp/socket.c if (!asoc && val.scact_assoc_id > SCTP_ALL_ASSOC && val 3884 net/sctp/socket.c return sctp_auth_deact_key_id(ep, asoc, val.scact_keynumber); val 3887 net/sctp/socket.c val.scact_assoc_id = SCTP_FUTURE_ASSOC; val 3889 net/sctp/socket.c if (val.scact_assoc_id == SCTP_FUTURE_ASSOC || val 3890 net/sctp/socket.c val.scact_assoc_id == SCTP_ALL_ASSOC) { val 3891 net/sctp/socket.c ret = sctp_auth_deact_key_id(ep, asoc, val.scact_keynumber); val 3896 net/sctp/socket.c if (val.scact_assoc_id == SCTP_CURRENT_ASSOC || val 3897 net/sctp/socket.c val.scact_assoc_id == SCTP_ALL_ASSOC) { val 3900 net/sctp/socket.c val.scact_keynumber); val 3927 net/sctp/socket.c int val; val 3932 net/sctp/socket.c if (get_user(val, (int __user *)optval)) val 3934 net/sctp/socket.c if (!sctp_is_ep_boundall(sk) && val) val 3936 net/sctp/socket.c if ((val && sp->do_auto_asconf) || (!val && !sp->do_auto_asconf)) val 3940 net/sctp/socket.c if (val == 0 && sp->do_auto_asconf) { val 3943 net/sctp/socket.c } else if (val && !sp->do_auto_asconf) { val 3963 net/sctp/socket.c struct sctp_paddrthlds val; val 3969 net/sctp/socket.c if (copy_from_user(&val, (struct sctp_paddrthlds __user *)optval, val 3973 net/sctp/socket.c if (!sctp_is_any(sk, (const union sctp_addr *)&val.spt_address)) { val 3974 net/sctp/socket.c trans = sctp_addr_id2transport(sk, &val.spt_address, val 3975 net/sctp/socket.c val.spt_assoc_id); val 3979 net/sctp/socket.c if (val.spt_pathmaxrxt) val 3980 net/sctp/socket.c trans->pathmaxrxt = val.spt_pathmaxrxt; val 3981 net/sctp/socket.c trans->pf_retrans = val.spt_pathpfthld; val 3986 net/sctp/socket.c asoc = sctp_id2assoc(sk, val.spt_assoc_id); val 3987 net/sctp/socket.c if (!asoc && val.spt_assoc_id != SCTP_FUTURE_ASSOC && val 3994 net/sctp/socket.c if (val.spt_pathmaxrxt) val 3995 net/sctp/socket.c trans->pathmaxrxt = val.spt_pathmaxrxt; val 3996 net/sctp/socket.c trans->pf_retrans = val.spt_pathpfthld; val 3999 net/sctp/socket.c if (val.spt_pathmaxrxt) val 4000 net/sctp/socket.c asoc->pathmaxrxt = val.spt_pathmaxrxt; val 4001 net/sctp/socket.c asoc->pf_retrans = val.spt_pathpfthld; val 4005 net/sctp/socket.c if (val.spt_pathmaxrxt) val 4006 net/sctp/socket.c sp->pathmaxrxt = val.spt_pathmaxrxt; val 4007 net/sctp/socket.c sp->pf_retrans = val.spt_pathpfthld; val 4017 net/sctp/socket.c int val; val 4021 net/sctp/socket.c if (get_user(val, (int __user *) optval)) val 4024 net/sctp/socket.c sctp_sk(sk)->recvrcvinfo = (val == 0) ? 0 : 1; val 4033 net/sctp/socket.c int val; val 4037 net/sctp/socket.c if (get_user(val, (int __user *) optval)) val 4040 net/sctp/socket.c sctp_sk(sk)->recvnxtinfo = (val == 0) ? 0 : 1; val 4415 net/sctp/socket.c int val; val 4426 net/sctp/socket.c if (get_user(val, (int __user *)optval)) val 4429 net/sctp/socket.c sctp_sk(sk)->reuse = !!val; val 5576 net/sctp/socket.c int val; val 5582 net/sctp/socket.c val = (sctp_sk(sk)->disable_fragments == 1); val 5585 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 6547 net/sctp/socket.c int val; val 6553 net/sctp/socket.c val = (sctp_sk(sk)->nodelay == 1); val 6556 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 6699 net/sctp/socket.c int val; val 6706 net/sctp/socket.c val = sp->v4mapped; val 6709 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 6826 net/sctp/socket.c int val; val 6833 net/sctp/socket.c val = sctp_sk(sk)->frag_interleave; val 6836 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 6850 net/sctp/socket.c u32 val; val 6857 net/sctp/socket.c val = sctp_sk(sk)->pd_point; val 6860 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 6950 net/sctp/socket.c struct sctp_authkeyid val; val 6957 net/sctp/socket.c if (copy_from_user(&val, optval, len)) val 6960 net/sctp/socket.c asoc = sctp_id2assoc(sk, val.scact_assoc_id); val 6961 net/sctp/socket.c if (!asoc && val.scact_assoc_id && sctp_style(sk, UDP)) val 6967 net/sctp/socket.c val.scact_keynumber = asoc->active_key_id; val 6971 net/sctp/socket.c val.scact_keynumber = ep->active_key_id; val 6976 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 6986 net/sctp/socket.c struct sctp_authchunks val; val 6995 net/sctp/socket.c if (copy_from_user(&val, optval, sizeof(val))) val 6999 net/sctp/socket.c asoc = sctp_id2assoc(sk, val.gauth_assoc_id); val 7031 net/sctp/socket.c struct sctp_authchunks val; val 7040 net/sctp/socket.c if (copy_from_user(&val, optval, sizeof(val))) val 7044 net/sctp/socket.c asoc = sctp_id2assoc(sk, val.gauth_assoc_id); val 7045 net/sctp/socket.c if (!asoc && val.gauth_assoc_id != SCTP_FUTURE_ASSOC && val 7087 net/sctp/socket.c u32 val = 0; val 7098 net/sctp/socket.c val++; val 7103 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 7116 net/sctp/socket.c int val = 0; val 7123 net/sctp/socket.c val = 1; val 7126 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 7192 net/sctp/socket.c struct sctp_paddrthlds val; val 7199 net/sctp/socket.c if (copy_from_user(&val, (struct sctp_paddrthlds __user *)optval, len)) val 7202 net/sctp/socket.c if (!sctp_is_any(sk, (const union sctp_addr *)&val.spt_address)) { val 7203 net/sctp/socket.c trans = sctp_addr_id2transport(sk, &val.spt_address, val 7204 net/sctp/socket.c val.spt_assoc_id); val 7208 net/sctp/socket.c val.spt_pathmaxrxt = trans->pathmaxrxt; val 7209 net/sctp/socket.c val.spt_pathpfthld = trans->pf_retrans; val 7214 net/sctp/socket.c asoc = sctp_id2assoc(sk, val.spt_assoc_id); val 7215 net/sctp/socket.c if (!asoc && val.spt_assoc_id != SCTP_FUTURE_ASSOC && val 7220 net/sctp/socket.c val.spt_pathpfthld = asoc->pf_retrans; val 7221 net/sctp/socket.c val.spt_pathmaxrxt = asoc->pathmaxrxt; val 7225 net/sctp/socket.c val.spt_pathpfthld = sp->pf_retrans; val 7226 net/sctp/socket.c val.spt_pathmaxrxt = sp->pathmaxrxt; val 7230 net/sctp/socket.c if (put_user(len, optlen) || copy_to_user(optval, &val, len)) val 7304 net/sctp/socket.c int val = 0; val 7311 net/sctp/socket.c val = 1; val 7314 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 7324 net/sctp/socket.c int val = 0; val 7331 net/sctp/socket.c val = 1; val 7334 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 7750 net/sctp/socket.c int val; val 7756 net/sctp/socket.c val = sctp_sk(sk)->reuse; val 7760 net/sctp/socket.c if (copy_to_user(optval, &val, len)) val 60 net/smc/af_smc.c static void smc_set_keepalive(struct sock *sk, int val) val 64 net/smc/af_smc.c smc->clcsock->sk->sk_prot->keepalive(smc->clcsock->sk, val); val 1710 net/smc/af_smc.c int val, rc; val 1726 net/smc/af_smc.c if (get_user(val, (int __user *)optval)) val 1750 net/smc/af_smc.c if (val) val 1759 net/smc/af_smc.c if (!val) val 1765 net/smc/af_smc.c smc->sockopt_defer_accept = val; val 58 net/smc/smc_wr.h static inline void smc_wr_tx_set_wr_id(atomic_long_t *wr_tx_id, long val) val 60 net/smc/smc_wr.h atomic_long_set(wr_tx_id, val); val 59 net/sunrpc/auth.c static int param_set_hashtbl_sz(const char *val, const struct kernel_param *kp) val 65 net/sunrpc/auth.c if (!val) val 67 net/sunrpc/auth.c ret = kstrtoul(val, 0, &num); val 54 net/sunrpc/svc.c param_set_pool_mode(const char *val, const struct kernel_param *kp) val 67 net/sunrpc/svc.c if (!strncmp(val, "auto", 4)) val 69 net/sunrpc/svc.c else if (!strncmp(val, "global", 6)) val 71 net/sunrpc/svc.c else if (!strncmp(val, "percpu", 6)) val 73 net/sunrpc/svc.c else if (!strncmp(val, "pernode", 7)) val 1406 net/sunrpc/svcsock.c int val; val 1442 net/sunrpc/svcsock.c val = 1; val 1445 net/sunrpc/svcsock.c (char *)&val, sizeof(val)); val 3267 net/sunrpc/xprtsock.c static int param_set_uint_minmax(const char *val, val 3274 net/sunrpc/xprtsock.c if (!val) val 3276 net/sunrpc/xprtsock.c ret = kstrtouint(val, 0, &num); val 3285 net/sunrpc/xprtsock.c static int param_set_portnr(const char *val, const struct kernel_param *kp) val 3287 net/sunrpc/xprtsock.c return param_set_uint_minmax(val, kp, val 3303 net/sunrpc/xprtsock.c static int param_set_slot_table_size(const char *val, val 3306 net/sunrpc/xprtsock.c return param_set_uint_minmax(val, kp, val 3319 net/sunrpc/xprtsock.c static int param_set_max_slot_table_size(const char *val, val 3322 net/sunrpc/xprtsock.c return param_set_uint_minmax(val, kp, val 411 net/switchdev/switchdev.c int call_switchdev_notifiers(unsigned long val, struct net_device *dev, val 417 net/switchdev/switchdev.c return atomic_notifier_call_chain(&switchdev_notif_chain, val, info); val 437 net/switchdev/switchdev.c int call_switchdev_blocking_notifiers(unsigned long val, struct net_device *dev, val 444 net/switchdev/switchdev.c val, info); val 189 net/tipc/core.h static inline int in_range(u16 val, u16 min, u16 max) val 191 net/tipc/core.h return !less(val, min) && !more(val, max); val 2375 net/tipc/link.c u32 val; val 2421 net/tipc/link.c if (nla_put_u32(skb, map[i].key, map[i].val)) val 2511 net/tipc/link.c __u32 val; val 2542 net/tipc/link.c if (nla_put_u32(skb, map[i].key, map[i].val)) val 163 net/tipc/msg.h static inline void msg_set_word(struct tipc_msg *m, u32 w, u32 val) val 165 net/tipc/msg.h m->hdr[w] = htonl(val); val 174 net/tipc/msg.h u32 pos, u32 mask, u32 val) val 176 net/tipc/msg.h val = (val & mask) << pos; val 179 net/tipc/msg.h m->hdr[w] |= htonl(val); val 796 net/tipc/msg.h static inline void msg_set_probe(struct tipc_msg *m, u32 val) val 798 net/tipc/msg.h msg_set_bits(m, 5, 0, 1, val); val 262 net/tipc/net.c u32 val; val 264 net/tipc/net.c val = nla_get_u32(attrs[TIPC_NLA_NET_ID]); val 265 net/tipc/net.c if (val < 1 || val > 9999) val 268 net/tipc/net.c tn->net_id = val; val 1108 net/tipc/netlink_compat.c u32 val; val 1111 net/tipc/netlink_compat.c val = ntohl(*(__be32 *)TLV_DATA(msg->req)); val 1118 net/tipc/netlink_compat.c if (nla_put_u32(skb, TIPC_NLA_NET_ADDR, val)) val 1121 net/tipc/netlink_compat.c if (nla_put_u32(skb, TIPC_NLA_NET_ID, val)) val 2384 net/tipc/node.c u32 val; val 2386 net/tipc/node.c val = nla_get_u32(attrs[TIPC_NLA_MON_ACTIVATION_THRESHOLD]); val 2387 net/tipc/node.c err = tipc_nl_monitor_set_threshold(net, val); val 2399 net/tipc/node.c u32 val; val 2410 net/tipc/node.c val = tipc_nl_monitor_get_threshold(net); val 2412 net/tipc/node.c if (nla_put_u32(msg->skb, TIPC_NLA_MON_ACTIVATION_THRESHOLD, val)) val 78 net/tipc/trace.h #define state_sym(val) \ val 79 net/tipc/trace.h __print_symbolic(val, \ val 97 net/tipc/trace.h #define evt_sym(val) \ val 98 net/tipc/trace.h __print_symbolic(val, \ val 117 net/tipc/trace.h #define dev_evt_sym(val) \ val 118 net/tipc/trace.h __print_symbolic(val, \ val 668 net/unix/af_unix.c static int unix_set_peek_off(struct sock *sk, int val) val 675 net/unix/af_unix.c sk->sk_peek_off = val; val 1378 net/vmw_vsock/af_vsock.c u64 val; val 1403 net/vmw_vsock/af_vsock.c COPY_IN(val); val 1404 net/vmw_vsock/af_vsock.c transport->set_buffer_size(vsk, val); val 1408 net/vmw_vsock/af_vsock.c COPY_IN(val); val 1409 net/vmw_vsock/af_vsock.c transport->set_max_buffer_size(vsk, val); val 1413 net/vmw_vsock/af_vsock.c COPY_IN(val); val 1414 net/vmw_vsock/af_vsock.c transport->set_min_buffer_size(vsk, val); val 1455 net/vmw_vsock/af_vsock.c u64 val; val 1481 net/vmw_vsock/af_vsock.c val = transport->get_buffer_size(vsk); val 1482 net/vmw_vsock/af_vsock.c COPY_OUT(val); val 1486 net/vmw_vsock/af_vsock.c val = transport->get_max_buffer_size(vsk); val 1487 net/vmw_vsock/af_vsock.c COPY_OUT(val); val 1491 net/vmw_vsock/af_vsock.c val = transport->get_min_buffer_size(vsk); val 1492 net/vmw_vsock/af_vsock.c COPY_OUT(val); val 796 net/vmw_vsock/hyperv_transport.c static void hvs_set_buffer_size(struct vsock_sock *vsk, u64 val) val 801 net/vmw_vsock/hyperv_transport.c static void hvs_set_min_buffer_size(struct vsock_sock *vsk, u64 val) val 806 net/vmw_vsock/hyperv_transport.c static void hvs_set_max_buffer_size(struct vsock_sock *vsk, u64 val) val 187 net/vmw_vsock/virtio_transport.c int val; val 189 net/vmw_vsock/virtio_transport.c val = atomic_dec_return(&vsock->queued_replies); val 192 net/vmw_vsock/virtio_transport.c if (val + 1 == virtqueue_get_vring_size(rx_vq)) val 365 net/vmw_vsock/virtio_transport.c int val; val 368 net/vmw_vsock/virtio_transport.c val = atomic_read(&vsock->queued_replies); val 370 net/vmw_vsock/virtio_transport.c return val < virtqueue_get_vring_size(vq); val 453 net/vmw_vsock/virtio_transport_common.c void virtio_transport_set_buffer_size(struct vsock_sock *vsk, u64 val) val 457 net/vmw_vsock/virtio_transport_common.c if (val > VIRTIO_VSOCK_MAX_BUF_SIZE) val 458 net/vmw_vsock/virtio_transport_common.c val = VIRTIO_VSOCK_MAX_BUF_SIZE; val 459 net/vmw_vsock/virtio_transport_common.c if (val < vvs->buf_size_min) val 460 net/vmw_vsock/virtio_transport_common.c vvs->buf_size_min = val; val 461 net/vmw_vsock/virtio_transport_common.c if (val > vvs->buf_size_max) val 462 net/vmw_vsock/virtio_transport_common.c vvs->buf_size_max = val; val 463 net/vmw_vsock/virtio_transport_common.c vvs->buf_size = val; val 464 net/vmw_vsock/virtio_transport_common.c vvs->buf_alloc = val; val 471 net/vmw_vsock/virtio_transport_common.c void virtio_transport_set_min_buffer_size(struct vsock_sock *vsk, u64 val) val 475 net/vmw_vsock/virtio_transport_common.c if (val > VIRTIO_VSOCK_MAX_BUF_SIZE) val 476 net/vmw_vsock/virtio_transport_common.c val = VIRTIO_VSOCK_MAX_BUF_SIZE; val 477 net/vmw_vsock/virtio_transport_common.c if (val > vvs->buf_size) val 478 net/vmw_vsock/virtio_transport_common.c vvs->buf_size = val; val 479 net/vmw_vsock/virtio_transport_common.c vvs->buf_size_min = val; val 483 net/vmw_vsock/virtio_transport_common.c void virtio_transport_set_max_buffer_size(struct vsock_sock *vsk, u64 val) val 487 net/vmw_vsock/virtio_transport_common.c if (val > VIRTIO_VSOCK_MAX_BUF_SIZE) val 488 net/vmw_vsock/virtio_transport_common.c val = VIRTIO_VSOCK_MAX_BUF_SIZE; val 489 net/vmw_vsock/virtio_transport_common.c if (val < vvs->buf_size) val 490 net/vmw_vsock/virtio_transport_common.c vvs->buf_size = val; val 491 net/vmw_vsock/virtio_transport_common.c vvs->buf_size_max = val; val 1899 net/vmw_vsock/vmci_transport.c static void vmci_transport_set_buffer_size(struct vsock_sock *vsk, u64 val) val 1901 net/vmw_vsock/vmci_transport.c if (val < vmci_trans(vsk)->queue_pair_min_size) val 1902 net/vmw_vsock/vmci_transport.c vmci_trans(vsk)->queue_pair_min_size = val; val 1903 net/vmw_vsock/vmci_transport.c if (val > vmci_trans(vsk)->queue_pair_max_size) val 1904 net/vmw_vsock/vmci_transport.c vmci_trans(vsk)->queue_pair_max_size = val; val 1905 net/vmw_vsock/vmci_transport.c vmci_trans(vsk)->queue_pair_size = val; val 1909 net/vmw_vsock/vmci_transport.c u64 val) val 1911 net/vmw_vsock/vmci_transport.c if (val > vmci_trans(vsk)->queue_pair_size) val 1912 net/vmw_vsock/vmci_transport.c vmci_trans(vsk)->queue_pair_size = val; val 1913 net/vmw_vsock/vmci_transport.c vmci_trans(vsk)->queue_pair_min_size = val; val 1917 net/vmw_vsock/vmci_transport.c u64 val) val 1919 net/vmw_vsock/vmci_transport.c if (val < vmci_trans(vsk)->queue_pair_size) val 1920 net/vmw_vsock/vmci_transport.c vmci_trans(vsk)->queue_pair_size = val; val 1921 net/vmw_vsock/vmci_transport.c vmci_trans(vsk)->queue_pair_max_size = val; val 137 net/wireless/lib80211_crypt_tkip.c static inline u16 RotR1(u16 val) val 139 net/wireless/lib80211_crypt_tkip.c return (val >> 1) | (val << 15); val 142 net/wireless/lib80211_crypt_tkip.c static inline u8 Lo8(u16 val) val 144 net/wireless/lib80211_crypt_tkip.c return val & 0xff; val 147 net/wireless/lib80211_crypt_tkip.c static inline u8 Hi8(u16 val) val 149 net/wireless/lib80211_crypt_tkip.c return val >> 8; val 152 net/wireless/lib80211_crypt_tkip.c static inline u16 Lo16(u32 val) val 154 net/wireless/lib80211_crypt_tkip.c return val & 0xffff; val 157 net/wireless/lib80211_crypt_tkip.c static inline u16 Hi16(u32 val) val 159 net/wireless/lib80211_crypt_tkip.c return val >> 16; val 350 net/wireless/pmsr.c #define PUT(tp, attr, val) \ val 354 net/wireless/pmsr.c res->ftm.val)) \ val 358 net/wireless/pmsr.c #define PUTOPT(tp, attr, val) \ val 360 net/wireless/pmsr.c if (res->ftm.val##_valid) \ val 361 net/wireless/pmsr.c PUT(tp, attr, val); \ val 364 net/wireless/pmsr.c #define PUT_U64(attr, val) \ val 368 net/wireless/pmsr.c res->ftm.val, \ val 373 net/wireless/pmsr.c #define PUTOPT_U64(attr, val) \ val 375 net/wireless/pmsr.c if (res->ftm.val##_valid) \ val 376 net/wireless/pmsr.c PUT_U64(attr, val); \ val 871 net/wireless/scan.c u16 mask, val; val 880 net/wireless/scan.c val = WLAN_CAPABILITY_DMG_TYPE_AP; val 883 net/wireless/scan.c val = WLAN_CAPABILITY_DMG_TYPE_PBSS; val 886 net/wireless/scan.c val = WLAN_CAPABILITY_DMG_TYPE_IBSS; val 895 net/wireless/scan.c val = WLAN_CAPABILITY_ESS; val 898 net/wireless/scan.c val = WLAN_CAPABILITY_IBSS; val 901 net/wireless/scan.c val = 0; val 908 net/wireless/scan.c ret = ((capability & mask) == val); val 882 net/wireless/wext-compat.c int err, val; val 892 net/wireless/wext-compat.c err = rdev_get_tx_power(rdev, wdev, &val); val 899 net/wireless/wext-compat.c data->txpower.value = val; val 464 net/x25/af_x25.c int val, len, rc = -ENOPROTOOPT; val 483 net/x25/af_x25.c val = test_bit(X25_Q_BIT_FLAG, &x25_sk(sk)->flags); val 484 net/x25/af_x25.c rc = copy_to_user(optval, &val, len) ? -EFAULT : 0; val 57 samples/bpf/bpf_load.c static int write_kprobe_events(const char *val) val 61 samples/bpf/bpf_load.c if (val == NULL) val 63 samples/bpf/bpf_load.c else if (val[0] == '\0') val 70 samples/bpf/bpf_load.c ret = write(fd, val, strlen(val)); val 108 samples/bpf/cpustat_kern.c u64 *val; val 176 samples/bpf/cpustat_kern.c val = bpf_map_lookup_elem(&pstate_duration, &key); val 177 samples/bpf/cpustat_kern.c if (val) val 178 samples/bpf/cpustat_kern.c __sync_fetch_and_add((long *)val, delta); val 199 samples/bpf/cpustat_kern.c val = bpf_map_lookup_elem(&cstate_duration, &key); val 200 samples/bpf/cpustat_kern.c if (val) val 201 samples/bpf/cpustat_kern.c __sync_fetch_and_add((long *)val, delta); val 216 samples/bpf/cpustat_kern.c u64 *val; val 273 samples/bpf/cpustat_kern.c val = bpf_map_lookup_elem(&pstate_duration, &key); val 274 samples/bpf/cpustat_kern.c if (val) val 275 samples/bpf/cpustat_kern.c __sync_fetch_and_add((long *)val, delta); val 80 samples/bpf/ibumad_kern.c u64 zero = 0, *val; val 85 samples/bpf/ibumad_kern.c val = bpf_map_lookup_elem(&read_count, &class); val 86 samples/bpf/ibumad_kern.c if (!val) { val 88 samples/bpf/ibumad_kern.c val = bpf_map_lookup_elem(&read_count, &class); val 89 samples/bpf/ibumad_kern.c if (!val) val 93 samples/bpf/ibumad_kern.c (*val) += 1; val 100 samples/bpf/ibumad_kern.c u64 zero = 0, *val; val 105 samples/bpf/ibumad_kern.c val = bpf_map_lookup_elem(&read_count, &class); val 106 samples/bpf/ibumad_kern.c if (!val) { val 108 samples/bpf/ibumad_kern.c val = bpf_map_lookup_elem(&read_count, &class); val 109 samples/bpf/ibumad_kern.c if (!val) val 113 samples/bpf/ibumad_kern.c (*val) += 1; val 120 samples/bpf/ibumad_kern.c u64 zero = 0, *val; val 125 samples/bpf/ibumad_kern.c val = bpf_map_lookup_elem(&write_count, &class); val 126 samples/bpf/ibumad_kern.c if (!val) { val 128 samples/bpf/ibumad_kern.c val = bpf_map_lookup_elem(&write_count, &class); val 129 samples/bpf/ibumad_kern.c if (!val) val 133 samples/bpf/ibumad_kern.c (*val) += 1; val 76 samples/bpf/lathist_kern.c long *val; val 90 samples/bpf/lathist_kern.c val = bpf_map_lookup_elem(&my_lat, &key); val 91 samples/bpf/lathist_kern.c if (val) val 92 samples/bpf/lathist_kern.c __sync_fetch_and_add((long *)val, 1); val 24 samples/bpf/lathist_user.c static void stars(char *str, long val, long max, int width) val 28 samples/bpf/lathist_user.c for (i = 0; i < (width * val / max) - 1 && i < width - 1; i++) val 30 samples/bpf/lathist_user.c if (val > max) val 18 samples/bpf/lwt_len_hist_user.c static void stars(char *str, long val, long max, int width) val 22 samples/bpf/lwt_len_hist_user.c for (i = 0; i < (width * val / max) - 1 && i < width - 1; i++) val 24 samples/bpf/lwt_len_hist_user.c if (val > max) val 173 samples/bpf/map_perf_test_kern.c long val = 1; val 196 samples/bpf/map_perf_test_kern.c ret = bpf_map_update_elem(&lru_hash_map, &key, &val, BPF_ANY); val 198 samples/bpf/map_perf_test_kern.c ret = bpf_map_update_elem(&nocommon_lru_hash_map, &key, &val, val 211 samples/bpf/map_perf_test_kern.c ret = bpf_map_update_elem(nolocal_lru_map, &key, &val, val 94 samples/bpf/map_perf_test_user.c long val = 1; val 108 samples/bpf/map_perf_test_user.c ret = bpf_map_update_elem(fd, &key, &val, BPF_NOEXIST); val 14 samples/bpf/offwaketime_kern.c #define _(P) ({typeof(P) val; bpf_probe_read(&val, sizeof(val), &P); val;}) val 79 samples/bpf/offwaketime_kern.c u64 zero = 0, *val; val 94 samples/bpf/offwaketime_kern.c val = bpf_map_lookup_elem(&counts, &key); val 95 samples/bpf/offwaketime_kern.c if (!val) { val 97 samples/bpf/offwaketime_kern.c val = bpf_map_lookup_elem(&counts, &key); val 98 samples/bpf/offwaketime_kern.c if (!val) val 101 samples/bpf/offwaketime_kern.c (*val) += delta; val 215 samples/bpf/sockex2_kern.c struct pair val = {1, skb->len}; val 217 samples/bpf/sockex2_kern.c bpf_map_update_elem(&hash_map, &key, &val, BPF_ANY); val 132 samples/bpf/sockex3_kern.c struct pair val = {1, skb->len}; val 134 samples/bpf/sockex3_kern.c bpf_map_update_elem(&hash_map, &key, &val, BPF_ANY); val 37 samples/bpf/spintest_kern.c long v = PT_REGS_IP(ctx), *val; \ val 39 samples/bpf/spintest_kern.c val = bpf_map_lookup_elem(&my_map, &v); \ val 33 samples/bpf/syscall_tp_user.c __u32 val; val 35 samples/bpf/syscall_tp_user.c if (bpf_map_lookup_elem(map_id, &key, &val) != 0) { val 39 samples/bpf/syscall_tp_user.c if (val == 0) { val 43 samples/bpf/syscall_tp_user.c val = 0; val 44 samples/bpf/syscall_tp_user.c if (bpf_map_update_elem(map_id, &key, &val, BPF_ANY) != 0) { val 12 samples/bpf/test_overhead_kprobe_kern.c #define _(P) ({typeof(P) val = 0; bpf_probe_read(&val, sizeof(val), &P); val;}) val 47 samples/bpf/trace_event_kern.c u64 *val, one = 1; val 71 samples/bpf/trace_event_kern.c val = bpf_map_lookup_elem(&counts, &key); val 72 samples/bpf/trace_event_kern.c if (val) val 73 samples/bpf/trace_event_kern.c (*val)++; val 13 samples/bpf/tracex1_kern.c #define _(P) ({typeof(P) val = 0; bpf_probe_read(&val, sizeof(val), &P); val;}) val 17 samples/bpf/tracex2_user.c static void stars(char *str, long val, long max, int width) val 21 samples/bpf/tracex2_user.c for (i = 0; i < (width * val / max) - 1 && i < width - 1; i++) val 23 samples/bpf/tracex2_user.c if (val > max) val 27 samples/bpf/tracex3_kern.c u64 val = bpf_ktime_get_ns(); val 29 samples/bpf/tracex3_kern.c bpf_map_update_elem(&my_map, &rq, &val, BPF_ANY); val 13 samples/bpf/tracex4_kern.c u64 val; val 46 samples/bpf/tracex4_kern.c .val = bpf_ktime_get_ns(), val 18 samples/bpf/tracex4_user.c long long val; val 32 samples/bpf/tracex4_user.c long long val = time_get_ns(); val 42 samples/bpf/tracex4_user.c if (val - v.val < 1000000000ll) val 46 samples/bpf/tracex4_user.c next_key, (val - v.val) / 1000000000ll, v.ip); val 29 samples/bpf/tracex6_kern.c u64 count, *val; val 37 samples/bpf/tracex6_kern.c val = bpf_map_lookup_elem(&values, &key); val 38 samples/bpf/tracex6_kern.c if (val) val 39 samples/bpf/tracex6_kern.c *val = count; val 50 samples/bpf/tracex6_kern.c struct bpf_perf_event_value *val, buf; val 57 samples/bpf/tracex6_kern.c val = bpf_map_lookup_elem(&values2, &key); val 58 samples/bpf/tracex6_kern.c if (val) val 59 samples/bpf/tracex6_kern.c *val = buf; val 62 samples/bpf/xdp_monitor_user.c long_options[i].val); val 131 samples/bpf/xdp_redirect_cpu_user.c long_options[i].val); val 161 samples/bpf/xdp_rxq_info_user.c long_options[i].val); val 28 samples/connector/cn_test.c __func__, jiffies, msg->id.idx, msg->id.val, val 70 samples/connector/cn_test.c msg->id.val = -1; val 94 samples/connector/cn_test.c req->first = cn_test_id.val; val 101 samples/connector/cn_test.c req->first = cn_test_id.val + 20; val 151 samples/connector/cn_test.c cn_test_id.val++; val 162 samples/connector/cn_test.c cn_test_id.idx, cn_test_id.val); val 177 samples/connector/cn_test.c cn_test_id.val--; val 66 samples/connector/ucon.c __func__, msg->id.idx, msg->id.val, msg->len, msg->seq, msg->ack); val 171 samples/connector/ucon.c data->id.val = CN_TEST_VAL; val 181 samples/connector/ucon.c ulog("%d messages have been sent to %08x.%08x.\n", i, data->id.idx, data->id.val); val 226 samples/connector/ucon.c ctime(&tm), data->id.idx, data->id.val, data->seq, data->ack); val 112 samples/seccomp/user-trap.c resp->val = 0; val 216 samples/timers/hpet_example.c hpet_sigio(int val) val 88 samples/vfio-mdev/mbochs.c #define STORE_LE16(addr, val) (*(u16 *)addr = val) val 89 samples/vfio-mdev/mbochs.c #define STORE_LE32(addr, val) (*(u32 *)addr = val) val 594 samples/vfio-mdev/mbochs.c u32 val; val 596 samples/vfio-mdev/mbochs.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 601 samples/vfio-mdev/mbochs.c if (copy_to_user(buf, &val, sizeof(val))) val 606 samples/vfio-mdev/mbochs.c u16 val; val 608 samples/vfio-mdev/mbochs.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 613 samples/vfio-mdev/mbochs.c if (copy_to_user(buf, &val, sizeof(val))) val 618 samples/vfio-mdev/mbochs.c u8 val; val 620 samples/vfio-mdev/mbochs.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 625 samples/vfio-mdev/mbochs.c if (copy_to_user(buf, &val, sizeof(val))) val 653 samples/vfio-mdev/mbochs.c u32 val; val 655 samples/vfio-mdev/mbochs.c if (copy_from_user(&val, buf, sizeof(val))) val 658 samples/vfio-mdev/mbochs.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 665 samples/vfio-mdev/mbochs.c u16 val; val 667 samples/vfio-mdev/mbochs.c if (copy_from_user(&val, buf, sizeof(val))) val 670 samples/vfio-mdev/mbochs.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 677 samples/vfio-mdev/mbochs.c u8 val; val 679 samples/vfio-mdev/mbochs.c if (copy_from_user(&val, buf, sizeof(val))) val 682 samples/vfio-mdev/mbochs.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 40 samples/vfio-mdev/mdpy.c #define STORE_LE16(addr, val) (*(u16 *)addr = val) val 41 samples/vfio-mdev/mdpy.c #define STORE_LE32(addr, val) (*(u32 *)addr = val) val 301 samples/vfio-mdev/mdpy.c u32 val; val 303 samples/vfio-mdev/mdpy.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 308 samples/vfio-mdev/mdpy.c if (copy_to_user(buf, &val, sizeof(val))) val 313 samples/vfio-mdev/mdpy.c u16 val; val 315 samples/vfio-mdev/mdpy.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 320 samples/vfio-mdev/mdpy.c if (copy_to_user(buf, &val, sizeof(val))) val 325 samples/vfio-mdev/mdpy.c u8 val; val 327 samples/vfio-mdev/mdpy.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 332 samples/vfio-mdev/mdpy.c if (copy_to_user(buf, &val, sizeof(val))) val 360 samples/vfio-mdev/mdpy.c u32 val; val 362 samples/vfio-mdev/mdpy.c if (copy_from_user(&val, buf, sizeof(val))) val 365 samples/vfio-mdev/mdpy.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 372 samples/vfio-mdev/mdpy.c u16 val; val 374 samples/vfio-mdev/mdpy.c if (copy_from_user(&val, buf, sizeof(val))) val 377 samples/vfio-mdev/mdpy.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 384 samples/vfio-mdev/mdpy.c u8 val; val 386 samples/vfio-mdev/mdpy.c if (copy_from_user(&val, buf, sizeof(val))) val 389 samples/vfio-mdev/mdpy.c ret = mdev_access(mdev, (char *)&val, sizeof(val), val 51 samples/vfio-mdev/mtty.c #define STORE_LE16(addr, val) (*(u16 *)addr = val) val 52 samples/vfio-mdev/mtty.c #define STORE_LE32(addr, val) (*(u32 *)addr = val) val 809 samples/vfio-mdev/mtty.c u32 val; val 811 samples/vfio-mdev/mtty.c ret = mdev_access(mdev, (u8 *)&val, sizeof(val), val 816 samples/vfio-mdev/mtty.c if (copy_to_user(buf, &val, sizeof(val))) val 821 samples/vfio-mdev/mtty.c u16 val; val 823 samples/vfio-mdev/mtty.c ret = mdev_access(mdev, (u8 *)&val, sizeof(val), val 828 samples/vfio-mdev/mtty.c if (copy_to_user(buf, &val, sizeof(val))) val 833 samples/vfio-mdev/mtty.c u8 val; val 835 samples/vfio-mdev/mtty.c ret = mdev_access(mdev, (u8 *)&val, sizeof(val), val 840 samples/vfio-mdev/mtty.c if (copy_to_user(buf, &val, sizeof(val))) val 868 samples/vfio-mdev/mtty.c u32 val; val 870 samples/vfio-mdev/mtty.c if (copy_from_user(&val, buf, sizeof(val))) val 873 samples/vfio-mdev/mtty.c ret = mdev_access(mdev, (u8 *)&val, sizeof(val), val 880 samples/vfio-mdev/mtty.c u16 val; val 882 samples/vfio-mdev/mtty.c if (copy_from_user(&val, buf, sizeof(val))) val 885 samples/vfio-mdev/mtty.c ret = mdev_access(mdev, (u8 *)&val, sizeof(val), val 892 samples/vfio-mdev/mtty.c u8 val; val 894 samples/vfio-mdev/mtty.c if (copy_from_user(&val, buf, sizeof(val))) val 897 samples/vfio-mdev/mtty.c ret = mdev_access(mdev, (u8 *)&val, sizeof(val), val 83 samples/vfs/test-fsmount.c const char *key, const void *val, int aux) val 85 samples/vfs/test-fsmount.c return syscall(__NR_fsconfig, fsfd, cmd, key, val, aux); val 97 samples/vfs/test-fsmount.c #define E_fsconfig(fd, cmd, key, val, aux) \ val 99 samples/vfs/test-fsmount.c if (fsconfig(fd, cmd, key, val, aux) == -1) \ val 322 scripts/asn1_compiler.c int val; val 329 scripts/asn1_compiler.c val = memcmp(token->content, dir, clen); val 330 scripts/asn1_compiler.c if (val != 0) { val 332 scripts/asn1_compiler.c return val; val 208 scripts/dtc/checks.c if (!data_is_one_string(prop->val)) val 228 scripts/dtc/checks.c str = prop->val.val; val 229 scripts/dtc/checks.c rem = prop->val.len; val 255 scripts/dtc/checks.c if (prop->val.len != sizeof(cell_t)) val 346 scripts/dtc/checks.c if (prop && !prop->val.len) val 451 scripts/dtc/checks.c struct marker *m = prop->val.markers; val 474 scripts/dtc/checks.c if (prop->val.len != sizeof(cell_t)) { val 476 scripts/dtc/checks.c prop->val.len, prop->name); val 480 scripts/dtc/checks.c m = prop->val.markers; val 559 scripts/dtc/checks.c if ((prop->val.len != node->basenamelen+1) val 560 scripts/dtc/checks.c || (memcmp(prop->val.val, node->name, node->basenamelen) != 0)) { val 562 scripts/dtc/checks.c " of base node name)", prop->val.val); val 568 scripts/dtc/checks.c data_free(prop->val); val 586 scripts/dtc/checks.c struct marker *m = prop->val.markers; val 591 scripts/dtc/checks.c assert(m->offset + sizeof(cell_t) <= prop->val.len); val 599 scripts/dtc/checks.c *((fdt32_t *)(prop->val.val + m->offset)) = val 605 scripts/dtc/checks.c *((fdt32_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle); val 621 scripts/dtc/checks.c struct marker *m = prop->val.markers; val 626 scripts/dtc/checks.c assert(m->offset <= prop->val.len); val 636 scripts/dtc/checks.c prop->val = data_insert_at_marker(prop->val, m, path, val 694 scripts/dtc/checks.c if (!prop->val.val || !get_node_by_path(dti->dt, prop->val.val)) { val 696 scripts/dtc/checks.c prop->val.val); val 744 scripts/dtc/checks.c if (prop->val.len == 0) val 751 scripts/dtc/checks.c if (!entrylen || (prop->val.len % entrylen) != 0) val 754 scripts/dtc/checks.c prop->val.len, addr_cells, size_cells); val 779 scripts/dtc/checks.c if (prop->val.len == 0) { val 790 scripts/dtc/checks.c } else if ((prop->val.len % entrylen) != 0) { val 793 scripts/dtc/checks.c "#size-cells == %d)", prop->val.len, val 809 scripts/dtc/checks.c if (!prop || !streq(prop->val.val, "pci")) val 831 scripts/dtc/checks.c if (prop->val.len != (sizeof(cell_t) * 2)) { val 835 scripts/dtc/checks.c cells = (cell_t *)prop->val.val; val 857 scripts/dtc/checks.c cells = (cell_t *)prop->val.val; val 864 scripts/dtc/checks.c cells = (cell_t *)prop->val.val; val 891 scripts/dtc/checks.c cells = (cell_t *)prop->val.val; val 932 scripts/dtc/checks.c for (str = prop->val.val, end = str + prop->val.len; str < end; val 962 scripts/dtc/checks.c cells = (cell_t *)prop->val.val; val 965 scripts/dtc/checks.c if (prop && prop->val.len) val 967 scripts/dtc/checks.c cells = ((cell_t *)prop->val.val) + node_addr_cells(node); val 1031 scripts/dtc/checks.c cells = (cell_t *)prop->val.val; val 1044 scripts/dtc/checks.c for (len = prop->val.len; len > 0; len -= 4) { val 1115 scripts/dtc/checks.c cells = (cell_t *)prop->val.val; val 1208 scripts/dtc/checks.c char *str = prop->val.val; val 1356 scripts/dtc/checks.c if (prop->val.len % sizeof(cell_t)) { val 1359 scripts/dtc/checks.c prop->val.len, sizeof(cell_t)); val 1363 scripts/dtc/checks.c for (cell = 0; cell < prop->val.len / sizeof(cell_t); cell += cellsize + 1) { val 1383 scripts/dtc/checks.c if (prop->val.markers) { val 1384 scripts/dtc/checks.c struct marker *m = prop->val.markers; val 1416 scripts/dtc/checks.c if (prop->val.len < ((cell + cellsize + 1) * sizeof(cell_t))) { val 1419 scripts/dtc/checks.c prop->val.len, cellsize); val 1555 scripts/dtc/checks.c if (irq_prop->val.len % sizeof(cell_t)) val 1557 scripts/dtc/checks.c irq_prop->val.len, sizeof(cell_t)); val 1604 scripts/dtc/checks.c if (irq_prop->val.len % (irq_cells * sizeof(cell_t))) { val 1607 scripts/dtc/checks.c irq_prop->val.len, (int)(irq_cells * sizeof(cell_t))); val 1679 scripts/dtc/checks.c if (!(prop->val.val && prop->val.len == sizeof(cell_t))) { val 20 scripts/dtc/data.c if (d.val) val 21 scripts/dtc/data.c free(d.val); val 39 scripts/dtc/data.c nd.val = xrealloc(d.val, newsize); val 51 scripts/dtc/data.c memcpy(d.val, mem, len); val 65 scripts/dtc/data.c q = d.val; val 93 scripts/dtc/data.c ret = fread(d.val + d.len, 1, chunksize, f); val 110 scripts/dtc/data.c memcpy(d.val + d.len, p, len); val 119 scripts/dtc/data.c memmove(d.val + m->offset + len, d.val + m->offset, d.len - m->offset); val 120 scripts/dtc/data.c memcpy(d.val + m->offset, p, len); val 146 scripts/dtc/data.c d = data_append_markers(data_append_data(d1, d2.val, d2.len), m2); val 216 scripts/dtc/data.c memset(d.val + d.len, 0, len); val 249 scripts/dtc/data.c if (d.val[i] == '\0') val 252 scripts/dtc/data.c if (d.val[len-1] != '\0') val 399 scripts/dtc/dtc-parser.y uint64_t val = ~0ULL >> (64 - $1.bits); val 409 scripts/dtc/dtc-parser.y $$.data = data_append_integer($1.data, val, $1.bits); val 84 scripts/dtc/dtc.h char *val; val 142 scripts/dtc/dtc.h struct data val; val 196 scripts/dtc/dtc.h struct property *build_property(char *name, struct data val, val 45 scripts/dtc/flattree.c static void bin_emit_cell(void *e, cell_t val) val 49 scripts/dtc/flattree.c *dtbuf = data_append_cell(*dtbuf, val); val 74 scripts/dtc/flattree.c *dtbuf = data_append_data(*dtbuf, d.val, d.len); val 123 scripts/dtc/flattree.c static void asm_emit_cell(void *e, cell_t val) val 128 scripts/dtc/flattree.c (val >> 24) & 0xff, (val >> 16) & 0xff, val 129 scripts/dtc/flattree.c (val >> 8) & 0xff, val & 0xff); val 159 scripts/dtc/flattree.c asm_emit_cell(e, fdt32_to_cpu(*((fdt32_t *)(d.val+off)))); val 164 scripts/dtc/flattree.c fprintf(f, "\t.byte\t0x%hhx\n", d.val[off]); val 227 scripts/dtc/flattree.c if (streq(str, d->val + i)) val 264 scripts/dtc/flattree.c emit->cell(etarget, prop->val.len); val 267 scripts/dtc/flattree.c if ((vi->flags & FTF_VARALIGN) && (prop->val.len >= 8)) val 270 scripts/dtc/flattree.c emit->data(etarget, prop->val); val 417 scripts/dtc/flattree.c if (fwrite(blob.val, blob.len, 1, f) != 1) { val 437 scripts/dtc/flattree.c p = strbuf.val; val 439 scripts/dtc/flattree.c while (p < (strbuf.val + strbuf.len)) { val 588 scripts/dtc/flattree.c fdt32_t val; val 590 scripts/dtc/flattree.c assert(((inb->ptr - inb->base) % sizeof(val)) == 0); val 592 scripts/dtc/flattree.c flat_read_chunk(inb, &val, sizeof(val)); val 594 scripts/dtc/flattree.c return fdt32_to_cpu(val); val 637 scripts/dtc/flattree.c flat_read_chunk(inb, d.val, len); val 668 scripts/dtc/flattree.c struct data val; val 678 scripts/dtc/flattree.c val = flat_read_data(dtbuf, proplen); val 680 scripts/dtc/flattree.c return build_property(name, val, NULL); val 736 scripts/dtc/flattree.c uint32_t val; val 751 scripts/dtc/flattree.c val = flat_read_word(dtbuf); val 752 scripts/dtc/flattree.c switch (val) { val 783 scripts/dtc/flattree.c val); val 785 scripts/dtc/flattree.c } while (val != FDT_END_NODE); val 810 scripts/dtc/flattree.c uint32_t val; val 909 scripts/dtc/flattree.c val = flat_read_word(&dtbuf); val 911 scripts/dtc/flattree.c if (val != FDT_BEGIN_NODE) val 912 scripts/dtc/flattree.c die("Device tree blob doesn't begin with FDT_BEGIN_NODE (begins with 0x%08x)\n", val); val 916 scripts/dtc/flattree.c val = flat_read_word(&dtbuf); val 917 scripts/dtc/flattree.c if (val != FDT_END) val 52 scripts/dtc/include-prefixes/dt-bindings/pinctrl/am43xx.h #define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) val 71 scripts/dtc/include-prefixes/dt-bindings/pinctrl/dra.h #define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) val 74 scripts/dtc/include-prefixes/dt-bindings/pinctrl/dra.h #define A_DELAY_PS(val) ((val) & 0xffff) val 75 scripts/dtc/include-prefixes/dt-bindings/pinctrl/dra.h #define G_DELAY_PS(val) ((val) & 0xffff) val 32 scripts/dtc/include-prefixes/dt-bindings/pinctrl/k3.h #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) val 33 scripts/dtc/include-prefixes/dt-bindings/pinctrl/k3.h #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) val 35 scripts/dtc/include-prefixes/dt-bindings/pinctrl/k3.h #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) val 36 scripts/dtc/include-prefixes/dt-bindings/pinctrl/k3.h #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) val 59 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) val 60 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) val 61 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) val 62 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) val 63 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) val 64 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) val 65 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) val 66 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) val 67 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) val 76 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) val 77 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) val 17 scripts/dtc/libfdt/fdt_addresses.c int val; val 27 scripts/dtc/libfdt/fdt_addresses.c val = fdt32_to_cpu(*c); val 28 scripts/dtc/libfdt/fdt_addresses.c if ((val <= 0) || (val > FDT_MAX_NCELLS)) val 31 scripts/dtc/libfdt/fdt_addresses.c return val; val 36 scripts/dtc/libfdt/fdt_addresses.c int val; val 38 scripts/dtc/libfdt/fdt_addresses.c val = fdt_cells(fdt, nodeoffset, "#address-cells"); val 39 scripts/dtc/libfdt/fdt_addresses.c if (val == -FDT_ERR_NOTFOUND) val 41 scripts/dtc/libfdt/fdt_addresses.c return val; val 46 scripts/dtc/libfdt/fdt_addresses.c int val; val 48 scripts/dtc/libfdt/fdt_addresses.c val = fdt_cells(fdt, nodeoffset, "#size-cells"); val 49 scripts/dtc/libfdt/fdt_addresses.c if (val == -FDT_ERR_NOTFOUND) val 51 scripts/dtc/libfdt/fdt_addresses.c return val; val 30 scripts/dtc/libfdt/fdt_overlay.c const fdt32_t *val; val 33 scripts/dtc/libfdt/fdt_overlay.c val = fdt_getprop(fdto, fragment, "target", &len); val 34 scripts/dtc/libfdt/fdt_overlay.c if (!val) val 37 scripts/dtc/libfdt/fdt_overlay.c if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1)) val 40 scripts/dtc/libfdt/fdt_overlay.c return fdt32_to_cpu(*val); val 119 scripts/dtc/libfdt/fdt_overlay.c const fdt32_t *val; val 123 scripts/dtc/libfdt/fdt_overlay.c val = fdt_getprop(fdt, node, name, &len); val 124 scripts/dtc/libfdt/fdt_overlay.c if (!val) val 127 scripts/dtc/libfdt/fdt_overlay.c if (len != sizeof(*val)) val 130 scripts/dtc/libfdt/fdt_overlay.c adj_val = fdt32_to_cpu(*val); val 634 scripts/dtc/libfdt/fdt_ro.c const void *val; val 647 scripts/dtc/libfdt/fdt_ro.c val = fdt_getprop(fdt, offset, propname, &len); val 648 scripts/dtc/libfdt/fdt_ro.c if (val && (len == proplen) val 649 scripts/dtc/libfdt/fdt_ro.c && (memcmp(val, propval, len) == 0)) val 262 scripts/dtc/libfdt/fdt_rw.c const void *val, int len) val 272 scripts/dtc/libfdt/fdt_rw.c memcpy(prop_data, val, len); val 277 scripts/dtc/libfdt/fdt_rw.c const void *val, int len) val 293 scripts/dtc/libfdt/fdt_rw.c memcpy(prop->data + oldlen, val, len); val 298 scripts/dtc/libfdt/fdt_rw.c memcpy(prop->data, val, len); val 18 scripts/dtc/libfdt/fdt_strerror.c #define FDT_ERRTABENT(val) \ val 19 scripts/dtc/libfdt/fdt_strerror.c [(val)] = { .str = #val, } val 317 scripts/dtc/libfdt/fdt_sw.c int fdt_property(void *fdt, const char *name, const void *val, int len) val 325 scripts/dtc/libfdt/fdt_sw.c memcpy(ptr, val, len); val 15 scripts/dtc/libfdt/fdt_wip.c uint32_t idx, const void *val, val 29 scripts/dtc/libfdt/fdt_wip.c memcpy((char *)propval + idx, val, len); val 34 scripts/dtc/libfdt/fdt_wip.c const void *val, int len) val 48 scripts/dtc/libfdt/fdt_wip.c val, len); val 248 scripts/dtc/libfdt/libfdt.h static inline void fdt_set_##name(void *fdt, uint32_t val) \ val 251 scripts/dtc/libfdt/libfdt.h fdth->name = cpu_to_fdt32(val); \ val 1219 scripts/dtc/libfdt/libfdt.h uint32_t idx, const void *val, val 1253 scripts/dtc/libfdt/libfdt.h const void *val, int len); val 1285 scripts/dtc/libfdt/libfdt.h const char *name, uint32_t val) val 1287 scripts/dtc/libfdt/libfdt.h fdt32_t tmp = cpu_to_fdt32(val); val 1320 scripts/dtc/libfdt/libfdt.h const char *name, uint64_t val) val 1322 scripts/dtc/libfdt/libfdt.h fdt64_t tmp = cpu_to_fdt64(val); val 1332 scripts/dtc/libfdt/libfdt.h const char *name, uint32_t val) val 1334 scripts/dtc/libfdt/libfdt.h return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); val 1434 scripts/dtc/libfdt/libfdt.h int fdt_property(void *fdt, const char *name, const void *val, int len); val 1435 scripts/dtc/libfdt/libfdt.h static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) val 1437 scripts/dtc/libfdt/libfdt.h fdt32_t tmp = cpu_to_fdt32(val); val 1440 scripts/dtc/libfdt/libfdt.h static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) val 1442 scripts/dtc/libfdt/libfdt.h fdt64_t tmp = cpu_to_fdt64(val); val 1447 scripts/dtc/libfdt/libfdt.h static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) val 1449 scripts/dtc/libfdt/libfdt.h return fdt_property_u32(fdt, name, val); val 1584 scripts/dtc/libfdt/libfdt.h const void *val, int len); val 1646 scripts/dtc/libfdt/libfdt.h uint32_t val) val 1648 scripts/dtc/libfdt/libfdt.h fdt32_t tmp = cpu_to_fdt32(val); val 1681 scripts/dtc/libfdt/libfdt.h uint64_t val) val 1683 scripts/dtc/libfdt/libfdt.h fdt64_t tmp = cpu_to_fdt64(val); val 1693 scripts/dtc/libfdt/libfdt.h uint32_t val) val 1695 scripts/dtc/libfdt/libfdt.h return fdt_setprop_u32(fdt, nodeoffset, name, val); val 1787 scripts/dtc/libfdt/libfdt.h const void *val, int len); val 1818 scripts/dtc/libfdt/libfdt.h const char *name, uint32_t val) val 1820 scripts/dtc/libfdt/libfdt.h fdt32_t tmp = cpu_to_fdt32(val); val 1853 scripts/dtc/libfdt/libfdt.h const char *name, uint64_t val) val 1855 scripts/dtc/libfdt/libfdt.h fdt64_t tmp = cpu_to_fdt64(val); val 1865 scripts/dtc/libfdt/libfdt.h const char *name, uint32_t val) val 1867 scripts/dtc/libfdt/libfdt.h return fdt_appendprop_u32(fdt, nodeoffset, name, val); val 39 scripts/dtc/livetree.c struct property *build_property(char *name, struct data val, val 47 scripts/dtc/livetree.c new->val = val; val 175 scripts/dtc/livetree.c old_prop->val = new_prop->val; val 347 scripts/dtc/livetree.c d = data_add_marker(p->val, type, name); val 349 scripts/dtc/livetree.c p->val = d; val 437 scripts/dtc/livetree.c assert(prop->val.len == sizeof(cell_t)); val 438 scripts/dtc/livetree.c return fdt32_to_cpu(*((fdt32_t *)prop->val.val)); val 443 scripts/dtc/livetree.c assert(prop->val.len / sizeof(cell_t) >= n); val 444 scripts/dtc/livetree.c return fdt32_to_cpu(*((fdt32_t *)prop->val.val + n)); val 484 scripts/dtc/livetree.c m = p->val.markers; val 639 scripts/dtc/livetree.c if (!reg || (reg->val.len != sizeof(uint32_t))) val 872 scripts/dtc/livetree.c m = prop->val.markers; val 918 scripts/dtc/livetree.c m = prop->val.markers; val 937 scripts/dtc/livetree.c m = prop->val.markers; val 999 scripts/dtc/livetree.c m = prop->val.markers; val 165 scripts/dtc/treesource.c int len = prop->val.len; val 166 scripts/dtc/treesource.c const char *p = prop->val.val; val 167 scripts/dtc/treesource.c struct marker *m = prop->val.markers; val 180 scripts/dtc/treesource.c if ((m->offset > 0) && (prop->val.val[m->offset - 1] != '\0')) val 198 scripts/dtc/treesource.c size_t len = prop->val.len; val 199 scripts/dtc/treesource.c struct marker *m = prop->val.markers; val 222 scripts/dtc/treesource.c dummy_marker.next = prop->val.markers; val 231 scripts/dtc/treesource.c const char *p = &prop->val.val[m->offset]; val 147 scripts/dtc/util.c long val; val 152 scripts/dtc/util.c val = strtol(x, &endx, 8); val 157 scripts/dtc/util.c return val; val 170 scripts/dtc/util.c long val; val 175 scripts/dtc/util.c val = strtol(x, &endx, 16); val 180 scripts/dtc/util.c return val; val 187 scripts/dtc/util.c char val; val 191 scripts/dtc/util.c val = '\a'; val 194 scripts/dtc/util.c val = '\b'; val 197 scripts/dtc/util.c val = '\t'; val 200 scripts/dtc/util.c val = '\n'; val 203 scripts/dtc/util.c val = '\v'; val 206 scripts/dtc/util.c val = '\f'; val 209 scripts/dtc/util.c val = '\r'; val 221 scripts/dtc/util.c val = get_oct_char(s, &j); val 224 scripts/dtc/util.c val = get_hex_char(s, &j); val 227 scripts/dtc/util.c val = c; val 231 scripts/dtc/util.c return val; val 446 scripts/dtc/util.c if (long_opts[i].val > '~') val 449 scripts/dtc/util.c fprintf(fp, " -%c, ", long_opts[i].val); val 115 scripts/dtc/yamltree.c int len = prop->val.len; val 116 scripts/dtc/yamltree.c struct marker *m = prop->val.markers; val 143 scripts/dtc/yamltree.c char *data = &prop->val.val[m->offset]; val 621 scripts/gcc-plugins/randomize_layout_plugin.c tree field, val; val 624 scripts/gcc-plugins/randomize_layout_plugin.c FOR_EACH_CONSTRUCTOR_ELT(CONSTRUCTOR_ELTS(init), idx, field, val) { val 625 scripts/gcc-plugins/randomize_layout_plugin.c if (TREE_CODE(val) == CONSTRUCTOR) { val 626 scripts/gcc-plugins/randomize_layout_plugin.c check_bad_casts_in_constructor(var, val); val 635 scripts/gcc-plugins/randomize_layout_plugin.c val_type = TREE_TYPE(val); val 280 scripts/kconfig/confdata.c sym->def[def].val = xstrdup(p); val 404 scripts/kconfig/confdata.c if (sym->def[def].val) val 405 scripts/kconfig/confdata.c free(sym->def[def].val); val 408 scripts/kconfig/confdata.c sym->def[def].val = NULL; val 502 scripts/kconfig/confdata.c cs->def[def].val = sym; val 541 scripts/kconfig/confdata.c if (!strcmp(sym->curr.val, sym->def[S_DEF_USER].val)) val 566 scripts/kconfig/confdata.c if (sym_string_within_range(sym, sym->def[S_DEF_USER].val)) val 1022 scripts/kconfig/confdata.c sym->def[S_DEF_AUTO].val)) val 1202 scripts/kconfig/confdata.c csym->def[S_DEF_USER].val = sym; val 1001 scripts/kconfig/expr.c union string_value *val) val 1010 scripts/kconfig/expr.c val->s = !strcmp(str, "n") ? 0 : val 1015 scripts/kconfig/expr.c val->s = strtoll(str, &tail, 10); val 1019 scripts/kconfig/expr.c val->u = strtoull(str, &tail, 16); val 1023 scripts/kconfig/expr.c val->s = strtoll(str, &tail, 0); val 60 scripts/kconfig/expr.h void *val; val 79 scripts/kconfig/gconf.c static const char *dbg_sym_flags(int val) val 85 scripts/kconfig/gconf.c if (val & SYMBOL_CONST) val 87 scripts/kconfig/gconf.c if (val & SYMBOL_CHECK) val 89 scripts/kconfig/gconf.c if (val & SYMBOL_CHOICE) val 91 scripts/kconfig/gconf.c if (val & SYMBOL_CHOICEVAL) val 93 scripts/kconfig/gconf.c if (val & SYMBOL_VALID) val 95 scripts/kconfig/gconf.c if (val & SYMBOL_OPTIONAL) val 97 scripts/kconfig/gconf.c if (val & SYMBOL_WRITE) val 99 scripts/kconfig/gconf.c if (val & SYMBOL_CHANGED) val 101 scripts/kconfig/gconf.c if (val & SYMBOL_NO_WRITE) val 1042 scripts/kconfig/gconf.c tristate val; val 1118 scripts/kconfig/gconf.c val = sym_get_tristate_value(sym); val 1119 scripts/kconfig/gconf.c switch (val) { val 1139 scripts/kconfig/gconf.c if (val != no && sym_tristate_within_range(sym, no)) val 1141 scripts/kconfig/gconf.c if (val != mod && sym_tristate_within_range(sym, mod)) val 1143 scripts/kconfig/gconf.c if (val != yes && sym_tristate_within_range(sym, yes)) val 126 scripts/kconfig/lkc.h return (struct symbol *)sym->curr.val; val 146 scripts/kconfig/lxdialog/dialog.h void item_set_selected(int val); val 633 scripts/kconfig/lxdialog/util.c void item_set_selected(int val) val 635 scripts/kconfig/lxdialog/util.c item_cur->node.selected = val; val 471 scripts/kconfig/mconf.c tristate val; val 538 scripts/kconfig/mconf.c val = sym_get_tristate_value(sym); val 542 scripts/kconfig/mconf.c item_make("[%c]", val == no ? ' ' : '*'); val 545 scripts/kconfig/mconf.c switch (val) { val 562 scripts/kconfig/mconf.c if (val == yes) { val 582 scripts/kconfig/mconf.c val = sym_get_tristate_value(sym); val 583 scripts/kconfig/mconf.c if (sym_is_choice_value(sym) && val == yes) { val 591 scripts/kconfig/mconf.c item_make("[%c]", val == no ? ' ' : '*'); val 593 scripts/kconfig/mconf.c item_make("-%c-", val == no ? ' ' : '*'); val 598 scripts/kconfig/mconf.c switch (val) { val 741 scripts/kconfig/nconf.c tristate val; val 805 scripts/kconfig/nconf.c val = sym_get_tristate_value(sym); val 810 scripts/kconfig/nconf.c val == no ? ' ' : '*'); val 813 scripts/kconfig/nconf.c switch (val) { val 833 scripts/kconfig/nconf.c if (val == yes) { val 854 scripts/kconfig/nconf.c val = sym_get_tristate_value(sym); val 855 scripts/kconfig/nconf.c if (sym_is_choice_value(sym) && val == yes) { val 862 scripts/kconfig/nconf.c val == no ? ' ' : '*'); val 865 scripts/kconfig/nconf.c val == no ? ' ' : '*'); val 868 scripts/kconfig/nconf.c switch (val) { val 465 scripts/kconfig/qconf.cc void ConfigList::setValue(ConfigItem* item, tristate val) val 481 scripts/kconfig/qconf.cc if (!sym_set_tristate_value(sym, val)) val 67 scripts/kconfig/qconf.h void setValue(ConfigItem* item, tristate val); val 114 scripts/kconfig/symbol.c return strtoll(sym->curr.val, NULL, base); val 121 scripts/kconfig/symbol.c long long val, val2; val 137 scripts/kconfig/symbol.c val = strtoll(sym->curr.val, NULL, base); val 139 scripts/kconfig/symbol.c if (val >= val2) { val 141 scripts/kconfig/symbol.c if (val <= val2) val 148 scripts/kconfig/symbol.c sym->curr.val = xstrdup(str); val 285 scripts/kconfig/symbol.c def_sym = sym->def[S_DEF_USER].val; val 353 scripts/kconfig/symbol.c sym->curr.val = sym->name; val 372 scripts/kconfig/symbol.c newval.tri = (prop_get_symbol(prop)->curr.val == sym) ? yes : no; val 412 scripts/kconfig/symbol.c newval.val = sym->def[S_DEF_USER].val; val 421 scripts/kconfig/symbol.c newval.val = ds->curr.val; val 431 scripts/kconfig/symbol.c sym->curr.val = sym_calc_choice(sym); val 473 scripts/kconfig/symbol.c bool sym_tristate_within_range(struct symbol *sym, tristate val) val 483 scripts/kconfig/symbol.c if (type == S_BOOLEAN && val == mod) val 487 scripts/kconfig/symbol.c if (sym->implied.tri == yes && val == mod) val 490 scripts/kconfig/symbol.c return val == yes; val 491 scripts/kconfig/symbol.c return val >= sym->rev_dep.tri && val <= sym->visible; val 494 scripts/kconfig/symbol.c bool sym_set_tristate_value(struct symbol *sym, tristate val) val 498 scripts/kconfig/symbol.c if (oldval != val && !sym_tristate_within_range(sym, val)) val 509 scripts/kconfig/symbol.c if (sym_is_choice_value(sym) && val == yes) { val 514 scripts/kconfig/symbol.c cs->def[S_DEF_USER].val = sym; val 523 scripts/kconfig/symbol.c sym->def[S_DEF_USER].tri = val; val 524 scripts/kconfig/symbol.c if (oldval != val) val 599 scripts/kconfig/symbol.c long long val; val 610 scripts/kconfig/symbol.c val = strtoll(str, NULL, 10); val 611 scripts/kconfig/symbol.c return val >= sym_get_range_val(prop->expr->left.sym, 10) && val 612 scripts/kconfig/symbol.c val <= sym_get_range_val(prop->expr->right.sym, 10); val 619 scripts/kconfig/symbol.c val = strtoll(str, NULL, 16); val 620 scripts/kconfig/symbol.c return val >= sym_get_range_val(prop->expr->left.sym, 16) && val 621 scripts/kconfig/symbol.c val <= sym_get_range_val(prop->expr->right.sym, 16); val 641 scripts/kconfig/symbol.c char *val; val 668 scripts/kconfig/symbol.c oldval = sym->def[S_DEF_USER].val; val 672 scripts/kconfig/symbol.c sym->def[S_DEF_USER].val = val = xmalloc(size); val 673 scripts/kconfig/symbol.c *val++ = '0'; val 674 scripts/kconfig/symbol.c *val++ = 'x'; val 676 scripts/kconfig/symbol.c sym->def[S_DEF_USER].val = val = xmalloc(size); val 680 scripts/kconfig/symbol.c strcpy(val, newval); val 699 scripts/kconfig/symbol.c tristate val; val 703 scripts/kconfig/symbol.c val = symbol_no.curr.tri; val 704 scripts/kconfig/symbol.c str = symbol_empty.curr.val; val 713 scripts/kconfig/symbol.c val = EXPR_AND(expr_calc_value(prop->expr), prop->visible.tri); val 724 scripts/kconfig/symbol.c str = (const char *)ds->curr.val; val 730 scripts/kconfig/symbol.c val = EXPR_OR(val, sym->rev_dep.tri); val 733 scripts/kconfig/symbol.c if (val == mod) val 735 scripts/kconfig/symbol.c val = yes; val 738 scripts/kconfig/symbol.c if (sym->type == S_BOOLEAN && val == mod) val 739 scripts/kconfig/symbol.c val = yes; val 742 scripts/kconfig/symbol.c if (val < sym->implied.tri) val 743 scripts/kconfig/symbol.c val = sym->implied.tri; val 748 scripts/kconfig/symbol.c switch (val) { val 766 scripts/kconfig/symbol.c tristate val; val 771 scripts/kconfig/symbol.c val = sym_get_tristate_value(sym); val 772 scripts/kconfig/symbol.c switch (val) { val 785 scripts/kconfig/symbol.c return (const char *)sym->curr.val; val 86 scripts/pnmtologo.c int c, val; val 104 scripts/pnmtologo.c val = 0; val 106 scripts/pnmtologo.c val = 10*val+c-'0'; val 116 scripts/pnmtologo.c return val; val 121 scripts/pnmtologo.c unsigned int val = get_number(fp); val 122 scripts/pnmtologo.c return (255*val+maxval/2)/maxval; val 286 scripts/pnmtologo.c unsigned char val, bit; val 300 scripts/pnmtologo.c for (val = 0, bit = 0x80; bit && j < logo_width; j++, bit >>= 1) val 302 scripts/pnmtologo.c val |= bit; val 303 scripts/pnmtologo.c write_hex(val); val 314 scripts/pnmtologo.c unsigned char val; val 337 scripts/pnmtologo.c val = k<<4; val 342 scripts/pnmtologo.c val |= k; val 344 scripts/pnmtologo.c write_hex(val); val 137 scripts/sortextable.c static void w8be(uint64_t val, uint64_t *x) val 139 scripts/sortextable.c put_unaligned_be64(val, x); val 141 scripts/sortextable.c static void wbe(uint32_t val, uint32_t *x) val 143 scripts/sortextable.c put_unaligned_be32(val, x); val 145 scripts/sortextable.c static void w2be(uint16_t val, uint16_t *x) val 147 scripts/sortextable.c put_unaligned_be16(val, x); val 149 scripts/sortextable.c static void w8le(uint64_t val, uint64_t *x) val 151 scripts/sortextable.c put_unaligned_le64(val, x); val 153 scripts/sortextable.c static void wle(uint32_t val, uint32_t *x) val 155 scripts/sortextable.c put_unaligned_le32(val, x); val 157 scripts/sortextable.c static void w2le(uint16_t val, uint16_t *x) val 159 scripts/sortextable.c put_unaligned_le16(val, x); val 917 scripts/unifdef.c int val; val 934 scripts/unifdef.c rt = ops->inner(ops+1, &val, &cp); val 937 scripts/unifdef.c lt = op->fn(valp, lt, *valp, rt, val); val 955 scripts/unifdef.c int val = 0; val 959 scripts/unifdef.c ret = eval_table(eval_ops, &val, cpp); val 960 scripts/unifdef.c debug("eval = %d", val); val 1157 scripts/unifdef.c char *val; val 1167 scripts/unifdef.c val = sym + (skipsym(sym) - sym); val 1169 scripts/unifdef.c if (*val == '=') { val 1170 scripts/unifdef.c value[symind] = val+1; val 1171 scripts/unifdef.c *val = '\0'; val 1172 scripts/unifdef.c } else if (*val == '\0') val 1177 scripts/unifdef.c if (*val != '\0') val 1248 security/apparmor/lsm.c static int param_set_aabool(const char *val, const struct kernel_param *kp); val 1257 security/apparmor/lsm.c static int param_set_aauint(const char *val, const struct kernel_param *kp); val 1265 security/apparmor/lsm.c static int param_set_aalockpolicy(const char *val, const struct kernel_param *kp); val 1274 security/apparmor/lsm.c static int param_set_audit(const char *val, const struct kernel_param *kp); val 1277 security/apparmor/lsm.c static int param_set_mode(const char *val, const struct kernel_param *kp); val 1336 security/apparmor/lsm.c static int param_set_aaintbool(const char *val, const struct kernel_param *kp); val 1358 security/apparmor/lsm.c static int param_set_aalockpolicy(const char *val, const struct kernel_param *kp) val 1364 security/apparmor/lsm.c return param_set_bool(val, kp); val 1376 security/apparmor/lsm.c static int param_set_aabool(const char *val, const struct kernel_param *kp) val 1382 security/apparmor/lsm.c return param_set_bool(val, kp); val 1394 security/apparmor/lsm.c static int param_set_aauint(const char *val, const struct kernel_param *kp) val 1404 security/apparmor/lsm.c error = param_set_uint(val, kp); val 1420 security/apparmor/lsm.c static int param_set_aaintbool(const char *val, const struct kernel_param *kp) val 1434 security/apparmor/lsm.c error = param_set_bool(val, &kp_local); val 1468 security/apparmor/lsm.c static int param_set_audit(const char *val, const struct kernel_param *kp) val 1474 security/apparmor/lsm.c if (!val) val 1479 security/apparmor/lsm.c i = match_string(audit_mode_names, AUDIT_MAX_INDEX, val); val 1497 security/apparmor/lsm.c static int param_set_mode(const char *val, const struct kernel_param *kp) val 1503 security/apparmor/lsm.c if (!val) val 1509 security/apparmor/lsm.c val); val 36 security/integrity/ima/ima_crypto.c static int param_set_bufsize(const char *val, const struct kernel_param *kp) val 41 security/integrity/ima/ima_crypto.c size = memparse(val, NULL); val 43 security/integrity/ima/ima_fs.c loff_t *ppos, atomic_long_t *val) val 48 security/integrity/ima/ima_fs.c len = scnprintf(tmpbuf, sizeof(tmpbuf), "%li\n", atomic_long_read(val)); val 894 security/security.c int security_add_mnt_opt(const char *option, const char *val, int len, val 898 security/security.c option, val, len, mnt_opts); val 1038 security/selinux/hooks.c static int selinux_add_mnt_opt(const char *option, const char *val, int len, val 1055 security/selinux/hooks.c val = kmemdup_nul(val, len, GFP_KERNEL); val 1056 security/selinux/hooks.c if (!val) { val 1061 security/selinux/hooks.c rc = selinux_add_opt(token, val, mnt_opts); val 1063 security/selinux/hooks.c kfree(val); val 390 security/selinux/include/security.h extern void selnl_notify_setenforce(int val); val 50 security/selinux/netlink.c msg->val = *((int *)data); val 98 security/selinux/netlink.c void selnl_notify_setenforce(int val) val 100 security/selinux/netlink.c selnl_notify(SELNL_MSG_SETENFORCE, &val); val 394 security/selinux/ss/avtab.c u32 items, items2, val, vers = pol->policyvers; val 424 security/selinux/ss/avtab.c val = le32_to_cpu(buf32[items++]); val 425 security/selinux/ss/avtab.c key.source_type = (u16)val; val 426 security/selinux/ss/avtab.c if (key.source_type != val) { val 430 security/selinux/ss/avtab.c val = le32_to_cpu(buf32[items++]); val 431 security/selinux/ss/avtab.c key.target_type = (u16)val; val 432 security/selinux/ss/avtab.c if (key.target_type != val) { val 436 security/selinux/ss/avtab.c val = le32_to_cpu(buf32[items++]); val 437 security/selinux/ss/avtab.c key.target_class = (u16)val; val 438 security/selinux/ss/avtab.c if (key.target_class != val) { val 443 security/selinux/ss/avtab.c val = le32_to_cpu(buf32[items++]); val 444 security/selinux/ss/avtab.c enabled = (val & AVTAB_ENABLED_OLD) ? AVTAB_ENABLED : 0; val 446 security/selinux/ss/avtab.c if (!(val & (AVTAB_AV | AVTAB_TYPE))) { val 450 security/selinux/ss/avtab.c if ((val & AVTAB_AV) && val 451 security/selinux/ss/avtab.c (val & AVTAB_TYPE)) { val 455 security/selinux/ss/avtab.c if (val & AVTAB_XPERMS) { val 461 security/selinux/ss/avtab.c if (val & spec_order[i]) { val 16 security/selinux/ss/symtab.c unsigned int val; val 18 security/selinux/ss/symtab.c val = 0; val 22 security/selinux/ss/symtab.c val = (val << 4 | (val >> (8*sizeof(unsigned int)-4))) ^ (*p); val 23 security/selinux/ss/symtab.c return val & (h->size - 1); val 40 sound/ac97/bus.c unsigned short reg, unsigned short val) val 39 sound/ac97/snd_ac97_compat.c unsigned short val) val 44 sound/ac97/snd_ac97_compat.c actrl->ops->write(actrl, ac97->num, reg, val); val 581 sound/aoa/codecs/onyx.c u8 val; val 586 sound/aoa/codecs/onyx.c if (onyx_read_register(onyx, ONYX_REG_CONTROL, &val)) val 588 sound/aoa/codecs/onyx.c val &= ~ONYX_SILICONVERSION; val 589 sound/aoa/codecs/onyx.c val |= initial_values[3]; val 590 sound/aoa/codecs/onyx.c regs[3] = val; val 118 sound/aoa/codecs/tas.c unsigned char val[6]; val 121 sound/aoa/codecs/tas.c val[0] = 0x50; /* 3:1 above threshold */ val 123 sound/aoa/codecs/tas.c val[0] = 0x51; /* disabled */ val 124 sound/aoa/codecs/tas.c val[1] = 0x02; /* 1:1 below threshold */ val 126 sound/aoa/codecs/tas.c val[2] = 0xef; val 128 sound/aoa/codecs/tas.c val[2] = 0x00; val 130 sound/aoa/codecs/tas.c val[2] = tas->drc_range; val 131 sound/aoa/codecs/tas.c val[3] = 0xb0; val 132 sound/aoa/codecs/tas.c val[4] = 0x60; val 133 sound/aoa/codecs/tas.c val[5] = 0xa0; val 135 sound/aoa/codecs/tas.c tas_write_reg(tas, TAS_REG_DRC, 6, val); val 190 sound/aoa/codecs/tas.c u8 val; val 193 sound/aoa/codecs/tas.c val = tas->mixer_l[i]; val 194 sound/aoa/codecs/tas.c if (val > 177) val = 177; val 195 sound/aoa/codecs/tas.c tmp = tas_gaintable[val]; val 203 sound/aoa/codecs/tas.c val = tas->mixer_r[i]; val 204 sound/aoa/codecs/tas.c if (val > 177) val = 177; val 205 sound/aoa/codecs/tas.c tmp = tas_gaintable[val]; val 67 sound/arm/aaci.c unsigned short val) val 84 sound/arm/aaci.c writel(val << 4, aaci->base + AACI_SL2TX); val 182 sound/arm/aaci.c u32 val; val 187 sound/arm/aaci.c val = readl(aacirun->base + AACI_SR); val 188 sound/arm/aaci.c } while (val & mask && timeout--); val 224 sound/arm/aaci.c u32 val; val 233 sound/arm/aaci.c val = readl(aacirun->base + AACI_SR); val 234 sound/arm/aaci.c if (!(val & SR_RXHF)) val 236 sound/arm/aaci.c if (!(val & SR_RXFF)) val 284 sound/arm/aaci.c u32 val; val 293 sound/arm/aaci.c val = readl(aacirun->base + AACI_SR); val 294 sound/arm/aaci.c if (!(val & SR_TXHE)) val 296 sound/arm/aaci.c if (!(val & SR_TXFE)) val 48 sound/arm/pxa2xx-ac97-lib.c int val = -ENODEV; val 66 sound/arm/pxa2xx-ac97-lib.c val = (*reg_addr & 0xffff); val 73 sound/arm/pxa2xx-ac97-lib.c val = -ETIMEDOUT; val 80 sound/arm/pxa2xx-ac97-lib.c val = (*reg_addr & 0xffff); val 85 sound/arm/pxa2xx-ac97-lib.c return val; val 89 sound/arm/pxa2xx-ac97-lib.c int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val) val 105 sound/arm/pxa2xx-ac97-lib.c *reg_addr = val; val 48 sound/arm/pxa2xx-ac97.c unsigned short reg, unsigned short val) val 52 sound/arm/pxa2xx-ac97.c ret = pxa2xx_ac97_write(ac97->num, reg, val); val 59 sound/atmel/ac97c.c #define ac97c_writel(chip, reg, val) \ val 60 sound/atmel/ac97c.c __raw_writel((val), (chip)->regs + AC97C_##reg) val 624 sound/atmel/ac97c.c unsigned short val) val 630 sound/atmel/ac97c.c word = (reg & 0x7f) << 16 | val; val 674 sound/atmel/ac97c.c unsigned short val = ac97c_readl(chip, CORHR); val 675 sound/atmel/ac97c.c return val; val 243 sound/core/control_compat.c int val; val 244 sound/core/control_compat.c if (get_user(val, &intp[i])) val 246 sound/core/control_compat.c data->value.integer.value[i] = val; val 275 sound/core/control_compat.c int val; val 276 sound/core/control_compat.c val = data->value.integer.value[i]; val 277 sound/core/control_compat.c if (put_user(val, &intp[i])) val 24 sound/core/hwdep_compat.c u32 val; val 34 sound/core/hwdep_compat.c if (get_user(val, &src->length) || val 35 sound/core/hwdep_compat.c put_user(val, &dst->length)) val 37 sound/core/hwdep_compat.c if (get_user(val, &src->driver_data) || val 38 sound/core/hwdep_compat.c put_user(val, &dst->driver_data)) val 415 sound/core/oss/mixer_oss.c static long snd_mixer_oss_conv(long val, long omin, long omax, long nmin, long nmax) val 421 sound/core/oss/mixer_oss.c return ((nrange * (val - omin)) + (orange / 2)) / orange + nmin; val 425 sound/core/oss/mixer_oss.c static long snd_mixer_oss_conv1(long val, long min, long max, int *old) val 427 sound/core/oss/mixer_oss.c if (val == snd_mixer_oss_conv(*old, 0, 100, min, max)) val 429 sound/core/oss/mixer_oss.c return snd_mixer_oss_conv(val, min, max, 0, 100); val 433 sound/core/oss/mixer_oss.c static long snd_mixer_oss_conv2(long val, long min, long max) val 435 sound/core/oss/mixer_oss.c return snd_mixer_oss_conv(val, 0, 100, min, max); val 35 sound/core/oss/mulaw.c static inline int val_seg(int val) val 38 sound/core/oss/mulaw.c val >>= 7; val 39 sound/core/oss/mulaw.c if (val & 0xf0) { val 40 sound/core/oss/mulaw.c val >>= 4; val 43 sound/core/oss/mulaw.c if (val & 0x0c) { val 44 sound/core/oss/mulaw.c val >>= 2; val 47 sound/core/oss/mulaw.c if (val & 0x02) val 106 sound/core/oss/pcm_oss.c static int snd_interval_refine_set(struct snd_interval *i, unsigned int val) val 110 sound/core/oss/pcm_oss.c t.min = t.max = val; val 170 sound/core/oss/pcm_oss.c const struct snd_mask *val) val 173 sound/core/oss/pcm_oss.c changed = snd_mask_refine(hw_param_mask(params, var), val); val 184 sound/core/oss/pcm_oss.c const struct snd_mask *val) val 186 sound/core/oss/pcm_oss.c int changed = _snd_pcm_hw_param_mask(params, var, val); val 198 sound/core/oss/pcm_oss.c snd_pcm_hw_param_t var, unsigned int val, val 207 sound/core/oss/pcm_oss.c if (val > 0) { val 209 sound/core/oss/pcm_oss.c val--; val 215 sound/core/oss/pcm_oss.c val + !!open); val 218 sound/core/oss/pcm_oss.c val, open); val 242 sound/core/oss/pcm_oss.c snd_pcm_hw_param_t var, unsigned int val, val 245 sound/core/oss/pcm_oss.c int changed = _snd_pcm_hw_param_min(params, var, val, dir ? *dir : 0); val 257 sound/core/oss/pcm_oss.c snd_pcm_hw_param_t var, unsigned int val, val 267 sound/core/oss/pcm_oss.c val++; val 271 sound/core/oss/pcm_oss.c if (val == 0 && open) { val 276 sound/core/oss/pcm_oss.c val - !!open); val 279 sound/core/oss/pcm_oss.c val, open); val 303 sound/core/oss/pcm_oss.c snd_pcm_hw_param_t var, unsigned int val, val 306 sound/core/oss/pcm_oss.c int changed = _snd_pcm_hw_param_max(params, var, val, dir ? *dir : 0); val 447 sound/core/oss/pcm_oss.c snd_pcm_hw_param_t var, unsigned int val, val 453 sound/core/oss/pcm_oss.c if (val == 0 && dir < 0) { val 458 sound/core/oss/pcm_oss.c val++; val 460 sound/core/oss/pcm_oss.c val--; val 461 sound/core/oss/pcm_oss.c changed = snd_mask_refine_set(hw_param_mask(params, var), val); val 465 sound/core/oss/pcm_oss.c if (val == 0 && dir < 0) { val 469 sound/core/oss/pcm_oss.c changed = snd_interval_refine_set(i, val); val 477 sound/core/oss/pcm_oss.c t.min = val - 1; val 478 sound/core/oss/pcm_oss.c t.max = val; val 480 sound/core/oss/pcm_oss.c t.min = val; val 481 sound/core/oss/pcm_oss.c t.max = val+1; val 508 sound/core/oss/pcm_oss.c snd_pcm_hw_param_t var, unsigned int val, val 511 sound/core/oss/pcm_oss.c int changed = _snd_pcm_hw_param_set(params, var, val, dir); val 1934 sound/core/oss/pcm_oss.c static int snd_pcm_oss_set_fragment1(struct snd_pcm_substream *substream, unsigned int val) val 1941 sound/core/oss/pcm_oss.c runtime->oss.fragshift = val & 0xffff; val 1942 sound/core/oss/pcm_oss.c runtime->oss.maxfrags = (val >> 16) & 0xffff; val 1951 sound/core/oss/pcm_oss.c static int snd_pcm_oss_set_fragment(struct snd_pcm_oss_file *pcm_oss_file, unsigned int val) val 1965 sound/core/oss/pcm_oss.c err = snd_pcm_oss_set_fragment1(substream, val); val 70 sound/core/oss/rate.c signed int val; val 107 sound/core/oss/rate.c val = S1 + ((S2 - S1) * (signed int)pos) / BITS; val 108 sound/core/oss/rate.c if (val < -32768) val 109 sound/core/oss/rate.c val = -32768; val 110 sound/core/oss/rate.c else if (val > 32767) val 111 sound/core/oss/rate.c val = 32767; val 112 sound/core/oss/rate.c *dst = val; val 129 sound/core/oss/rate.c signed int val; val 165 sound/core/oss/rate.c val = S1 + ((S2 - S1) * (signed int)pos) / BITS; val 166 sound/core/oss/rate.c if (val < -32768) val 167 sound/core/oss/rate.c val = -32768; val 168 sound/core/oss/rate.c else if (val > 32767) val 169 sound/core/oss/rate.c val = 32767; val 170 sound/core/oss/rate.c *dst = val; val 153 sound/core/pcm.c int val; val 155 sound/core/pcm.c if (get_user(val, (int __user *)arg)) val 157 sound/core/pcm.c control->preferred_subdevice[SND_CTL_SUBDEV_PCM] = val; val 261 sound/core/pcm_misc.c int val; val 264 sound/core/pcm_misc.c if ((val = pcm_formats[(INT)format].signd) < 0) val 266 sound/core/pcm_misc.c return val; val 279 sound/core/pcm_misc.c int val; val 281 sound/core/pcm_misc.c val = snd_pcm_format_signed(format); val 282 sound/core/pcm_misc.c if (val < 0) val 283 sound/core/pcm_misc.c return val; val 284 sound/core/pcm_misc.c return !val; val 309 sound/core/pcm_misc.c int val; val 312 sound/core/pcm_misc.c if ((val = pcm_formats[(INT)format].le) < 0) val 314 sound/core/pcm_misc.c return val; val 327 sound/core/pcm_misc.c int val; val 329 sound/core/pcm_misc.c val = snd_pcm_format_little_endian(format); val 330 sound/core/pcm_misc.c if (val < 0) val 331 sound/core/pcm_misc.c return val; val 332 sound/core/pcm_misc.c return !val; val 345 sound/core/pcm_misc.c int val; val 348 sound/core/pcm_misc.c if ((val = pcm_formats[(INT)format].width) == 0) val 350 sound/core/pcm_misc.c return val; val 363 sound/core/pcm_misc.c int val; val 366 sound/core/pcm_misc.c if ((val = pcm_formats[(INT)format].phys) == 0) val 368 sound/core/pcm_misc.c return val; val 798 sound/core/rawmidi.c int val; val 800 sound/core/rawmidi.c if (get_user(val, (int __user *) argp)) val 802 sound/core/rawmidi.c switch (val) { val 813 sound/core/rawmidi.c int val; val 815 sound/core/rawmidi.c if (get_user(val, (int __user *) argp)) val 817 sound/core/rawmidi.c switch (val) { val 869 sound/core/rawmidi.c int val; val 871 sound/core/rawmidi.c if (get_user(val, (int __user *)argp)) val 873 sound/core/rawmidi.c control->preferred_subdevice[SND_CTL_SUBDEV_RAWMIDI] = val; val 23 sound/core/rawmidi_compat.c unsigned int val; val 28 sound/core/rawmidi_compat.c get_user(val, &src->no_active_sensing)) val 30 sound/core/rawmidi_compat.c params.no_active_sensing = val; val 31 sound/core/seq/oss/seq_oss_event.c static int set_control_event(struct seq_oss_devinfo *dp, int dev, int type, int ch, int param, int val, struct snd_seq_event *ev); val 123 sound/core/seq/oss/seq_oss_event.c int val; val 142 sound/core/seq/oss/seq_oss_event.c val = (char)q->e.p1; val 143 sound/core/seq/oss/seq_oss_event.c val = (val + 128) / 2; val 145 sound/core/seq/oss/seq_oss_event.c q->e.chn, CTL_PAN, val, ev); val 148 sound/core/seq/oss/seq_oss_event.c val = ((short)q->e.p3 << 8) | (short)q->e.p2; val 154 sound/core/seq/oss/seq_oss_event.c q->e.chn, 0, val, ev); val 159 sound/core/seq/oss/seq_oss_event.c q->e.chn, 0, val*128/100, ev); val 163 sound/core/seq/oss/seq_oss_event.c q->e.chn, q->e.p1, val, ev); val 207 sound/core/seq/oss/seq_oss_event.c q->l.chn, q->l.p1, q->l.val, ev); val 212 sound/core/seq/oss/seq_oss_event.c q->l.chn, 0, q->l.val - 8192, ev); val 216 sound/core/seq/oss/seq_oss_event.c q->l.chn, 0, q->l.val, ev); val 390 sound/core/seq/oss/seq_oss_event.c set_control_event(struct seq_oss_devinfo *dp, int dev, int type, int ch, int param, int val, struct snd_seq_event *ev) val 399 sound/core/seq/oss/seq_oss_event.c ev->data.control.value = val; val 58 sound/core/seq/oss/seq_oss_event.h unsigned short val; val 464 sound/core/seq/oss/seq_oss_init.c filemode_str(int val) val 469 sound/core/seq/oss/seq_oss_init.c return str[val & SNDRV_SEQ_OSS_FILE_ACMODE]; val 63 sound/core/seq/oss/seq_oss_ioctl.c int dev, val; val 128 sound/core/seq/oss/seq_oss_ioctl.c val = snd_seq_oss_synth_ioctl(dp, dev, cmd, carg); val 129 sound/core/seq/oss/seq_oss_ioctl.c return put_user(val, p) ? -EFAULT : 0; val 150 sound/core/seq/oss/seq_oss_ioctl.c if (get_user(val, p)) val 152 sound/core/seq/oss/seq_oss_ioctl.c if (val < 1) val 153 sound/core/seq/oss/seq_oss_ioctl.c val = 1; val 154 sound/core/seq/oss/seq_oss_ioctl.c if (val >= dp->writeq->maxlen) val 155 sound/core/seq/oss/seq_oss_ioctl.c val = dp->writeq->maxlen - 1; val 156 sound/core/seq/oss/seq_oss_ioctl.c snd_seq_oss_writeq_set_output(dp->writeq, val); val 162 sound/core/seq/oss/seq_oss_ioctl.c if (get_user(val, p)) val 164 sound/core/seq/oss/seq_oss_ioctl.c if (val <= 0) val 165 sound/core/seq/oss/seq_oss_ioctl.c val = -1; val 167 sound/core/seq/oss/seq_oss_ioctl.c val = (HZ * val) / 10; val 168 sound/core/seq/oss/seq_oss_ioctl.c dp->readq->pre_event_timeout = val; val 169 sound/core/seq/oss/seq_oss_ioctl.c return put_user(val, p) ? -EFAULT : 0; val 575 sound/core/seq/oss/seq_oss_midi.c ossev.l.val = ev->data.control.value; val 580 sound/core/seq/oss/seq_oss_midi.c ossev.l.val = ev->data.control.value + 8192; val 661 sound/core/seq/oss/seq_oss_midi.c capmode_str(int val) val 663 sound/core/seq/oss/seq_oss_midi.c val &= PERM_READ|PERM_WRITE; val 664 sound/core/seq/oss/seq_oss_midi.c if (val == (PERM_READ|PERM_WRITE)) val 666 sound/core/seq/oss/seq_oss_midi.c else if (val == PERM_READ) val 668 sound/core/seq/oss/seq_oss_midi.c else if (val == PERM_WRITE) val 151 sound/core/seq/oss/seq_oss_writeq.c snd_seq_oss_writeq_set_output(struct seq_oss_writeq *q, int val) val 156 sound/core/seq/oss/seq_oss_writeq.c pool.output_room = val; val 409 sound/core/seq/seq_midi_emul.c int val; val 414 sound/core/seq/seq_midi_emul.c val = (chan->control[MIDI_CTL_MSB_DATA_ENTRY] << 7) | val 420 sound/core/seq/seq_midi_emul.c chan->gm_rpn_pitch_bend_range = val; val 425 sound/core/seq/seq_midi_emul.c chan->gm_rpn_fine_tuning = val - 8192; val 430 sound/core/seq/seq_midi_emul.c chan->gm_rpn_coarse_tuning = val - 8192; val 1353 sound/core/timer.c r1.val = resolution; val 1396 sound/core/timer.c r1.val = resolution; val 1410 sound/core/timer.c r->val += ticks; val 1417 sound/core/timer.c r1.val = ticks; val 1864 sound/core/timer.c tread.val = 0; val 34 sound/core/vmaster.c int val; /* the master value */ val 129 sound/core/vmaster.c master->val = master->info.max_val; val 131 sound/core/vmaster.c master->hook(master->hook_private_data, master->val); val 163 sound/core/vmaster.c !!slave->master->val; val 169 sound/core/vmaster.c vol += slave->master->val - slave->master->info.max_val; val 308 sound/core/vmaster.c ucontrol->value.integer.value[0] = master->val; val 321 sound/core/vmaster.c master->val = old_val; val 324 sound/core/vmaster.c master->val = new_val; val 342 sound/core/vmaster.c old_val = master->val; val 351 sound/core/vmaster.c master->hook(master->hook_private_data, master->val); val 479 sound/core/vmaster.c err = sync_slaves(master, master->val, master->val); val 485 sound/core/vmaster.c master->hook(master->hook_private_data, master->val); val 820 sound/drivers/aloop.c unsigned int val; val 823 sound/drivers/aloop.c val = ucontrol->value.integer.value[0]; val 824 sound/drivers/aloop.c if (val < 80000) val 825 sound/drivers/aloop.c val = 80000; val 826 sound/drivers/aloop.c if (val > 120000) val 827 sound/drivers/aloop.c val = 120000; val 829 sound/drivers/aloop.c if (val != loopback->setup[kcontrol->id.subdevice] val 832 sound/drivers/aloop.c [kcontrol->id.device].rate_shift = val; val 856 sound/drivers/aloop.c unsigned int val; val 859 sound/drivers/aloop.c val = ucontrol->value.integer.value[0] ? 1 : 0; val 861 sound/drivers/aloop.c if (val != loopback->setup[kcontrol->id.subdevice] val 864 sound/drivers/aloop.c [kcontrol->id.device].notify = val; val 877 sound/drivers/aloop.c unsigned int val = 0; val 884 sound/drivers/aloop.c val = (running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) ? 1 : 0; val 887 sound/drivers/aloop.c ucontrol->value.integer.value[0] = val; val 1004 sound/drivers/dummy.c unsigned long long val; val 1015 sound/drivers/dummy.c if (kstrtoull(item, 0, &val)) val 1018 sound/drivers/dummy.c *get_dummy_int_ptr(dummy, fields[i].offset) = val; val 1020 sound/drivers/dummy.c *get_dummy_ll_ptr(dummy, fields[i].offset) = val; val 940 sound/drivers/ml403-ac97cr.c unsigned short val) val 964 sound/drivers/ml403-ac97cr.c if ((val & lm4550_regfile[reg / 2].wmask) != val) { val 968 sound/drivers/ml403-ac97cr.c reg, val, val); val 969 sound/drivers/ml403-ac97cr.c val = val & lm4550_regfile[reg / 2].wmask; val 975 sound/drivers/ml403-ac97cr.c "val=0x%x / %d\n", reg, val, val); val 976 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value = (val & val 987 sound/drivers/ml403-ac97cr.c CR_CODEC_DATAWRITE(val)); val 1008 sound/drivers/ml403-ac97cr.c reg, val, val); val 1013 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value = val; val 1027 sound/drivers/ml403-ac97cr.c reg, val, val, stat, rafaccess, ml403_ac97cr->ac97_write, val 1032 sound/drivers/ml403-ac97cr.c reg, val, val); val 1046 sound/drivers/ml403-ac97cr.c reg, val, val); val 224 sound/drivers/mtpav.c static inline void snd_mtpav_mputreg(struct mtpav *chip, u16 reg, u8 val) val 227 sound/drivers/mtpav.c outb(val, chip->port + reg); val 449 sound/drivers/mts64.c int val = !!uctl->value.integer.value[0]; val 452 sound/drivers/mts64.c if (mts->smpte_switch == val) val 456 sound/drivers/mts64.c mts->smpte_switch = val; val 26 sound/drivers/opl3/opl3_lib.c static void snd_opl2_command(struct snd_opl3 * opl3, unsigned short cmd, unsigned char val) val 43 sound/drivers/opl3/opl3_lib.c outb((unsigned char) val, port + 1); val 49 sound/drivers/opl3/opl3_lib.c static void snd_opl3_command(struct snd_opl3 * opl3, unsigned short cmd, unsigned char val) val 67 sound/drivers/opl3/opl3_lib.c outb((unsigned char) val, port + 1); val 46 sound/drivers/pcsp/pcsp_lib.c unsigned char timer_cnt, val; val 64 sound/drivers/pcsp/pcsp_lib.c val = runtime->dma_area[chip->playback_ptr + chip->fmt_size - 1]; val 66 sound/drivers/pcsp/pcsp_lib.c val ^= 0x80; val 67 sound/drivers/pcsp/pcsp_lib.c timer_cnt = val * CUR_DIV() / 256; val 149 sound/drivers/vx/vx_core.c int i, err, val, size; val 163 sound/drivers/vx/vx_core.c val = vx_inb(chip, RXH) << 16; val 164 sound/drivers/vx/vx_core.c val |= vx_inb(chip, RXM) << 8; val 165 sound/drivers/vx/vx_core.c val |= vx_inb(chip, RXL); val 170 sound/drivers/vx/vx_core.c size = val & 0xff; val 171 sound/drivers/vx/vx_core.c rmh->Stat[0] = val & 0xffff00; val 176 sound/drivers/vx/vx_core.c rmh->Stat[0] = val; val 178 sound/drivers/vx/vx_core.c while (val) { val 179 sound/drivers/vx/vx_core.c if (val & 0x01) val 181 sound/drivers/vx/vx_core.c val >>= 1; val 188 sound/drivers/vx/vx_core.c rmh->Stat[0] = val; /* Val is the status 1st word */ val 74 sound/drivers/vx/vx_mixer.c static void vx_set_codec_reg(struct vx_core *chip, int codec, int reg, int val) val 80 sound/drivers/vx/vx_mixer.c SET_CDC_DATA_VAL(data, val); val 425 sound/drivers/vx/vx_mixer.c unsigned int val[2], vmax; val 428 sound/drivers/vx/vx_mixer.c val[0] = ucontrol->value.integer.value[0]; val 429 sound/drivers/vx/vx_mixer.c val[1] = ucontrol->value.integer.value[1]; val 430 sound/drivers/vx/vx_mixer.c if (val[0] > vmax || val[1] > vmax) val 433 sound/drivers/vx/vx_mixer.c if (val[0] != chip->output_level[codec][0] || val 434 sound/drivers/vx/vx_mixer.c val[1] != chip->output_level[codec][1]) { val 435 sound/drivers/vx/vx_mixer.c vx_set_analog_output_level(chip, codec, val[0], val[1]); val 436 sound/drivers/vx/vx_mixer.c chip->output_level[codec][0] = val[0]; val 437 sound/drivers/vx/vx_mixer.c chip->output_level[codec][1] = val[1]; val 586 sound/drivers/vx/vx_mixer.c unsigned int val[2]; val 588 sound/drivers/vx/vx_mixer.c val[0] = ucontrol->value.integer.value[0]; val 589 sound/drivers/vx/vx_mixer.c val[1] = ucontrol->value.integer.value[1]; val 590 sound/drivers/vx/vx_mixer.c if (val[0] > CVAL_MAX || val[1] > CVAL_MAX) val 593 sound/drivers/vx/vx_mixer.c if (val[0] != chip->audio_gain[capture][audio] || val 594 sound/drivers/vx/vx_mixer.c val[1] != chip->audio_gain[capture][audio+1]) { val 595 sound/drivers/vx/vx_mixer.c vx_set_audio_gain(chip, audio, capture, val[0]); val 596 sound/drivers/vx/vx_mixer.c vx_set_audio_gain(chip, audio+1, capture, val[1]); val 620 sound/drivers/vx/vx_mixer.c unsigned int val[2]; val 622 sound/drivers/vx/vx_mixer.c val[0] = ucontrol->value.integer.value[0]; val 623 sound/drivers/vx/vx_mixer.c val[1] = ucontrol->value.integer.value[1]; val 624 sound/drivers/vx/vx_mixer.c if (val[0] > CVAL_MAX || val[1] > CVAL_MAX) val 628 sound/drivers/vx/vx_mixer.c if (val[0] != chip->audio_monitor[audio] || val 629 sound/drivers/vx/vx_mixer.c val[1] != chip->audio_monitor[audio+1]) { val 630 sound/drivers/vx/vx_mixer.c vx_set_monitor_level(chip, audio, val[0], val 632 sound/drivers/vx/vx_mixer.c vx_set_monitor_level(chip, audio+1, val[1], val 778 sound/drivers/vx/vx_mixer.c unsigned int val; val 780 sound/drivers/vx/vx_mixer.c val = (ucontrol->value.iec958.status[0] << 0) | val 785 sound/drivers/vx/vx_mixer.c if (chip->uer_bits != val) { val 786 sound/drivers/vx/vx_mixer.c chip->uer_bits = val; val 787 sound/drivers/vx/vx_mixer.c vx_set_iec958_status(chip, val); val 919 sound/drivers/vx/vx_mixer.c int val = i * 2; val 923 sound/drivers/vx/vx_mixer.c temp.private_value = val; val 928 sound/drivers/vx/vx_mixer.c temp.private_value = val; val 933 sound/drivers/vx/vx_mixer.c temp.private_value = val; val 938 sound/drivers/vx/vx_mixer.c temp.private_value = val; val 966 sound/drivers/vx/vx_mixer.c int val = (i * 2) | (c << 8); val 970 sound/drivers/vx/vx_mixer.c temp.private_value = val; val 978 sound/drivers/vx/vx_mixer.c temp.private_value = val; val 985 sound/drivers/vx/vx_mixer.c temp.private_value = val; val 50 sound/drivers/vx/vx_uer.c int val; val 56 sound/drivers/vx/vx_uer.c val = (vx_inb(chip, RUER) >> 7) & 0x01; val 60 sound/drivers/vx/vx_uer.c val = (vx_inl(chip, RUER) >> 7) & 0x01; val 63 sound/drivers/vx/vx_uer.c return val; val 71 sound/drivers/vx/vx_uer.c static void vx_write_one_cbit(struct vx_core *chip, int index, int val) val 73 sound/drivers/vx/vx_uer.c val = !!val; /* 0 or 1 */ val 77 sound/drivers/vx/vx_uer.c vx_outb(chip, RUER, (val << 7) | (index & XX_UER_CBITS_OFFSET_MASK)); val 80 sound/drivers/vx/vx_uer.c vx_outl(chip, RUER, (val << 7) | (index & XX_UER_CBITS_OFFSET_MASK)); val 94 sound/drivers/vx/vx_uer.c int val, freq; val 101 sound/drivers/vx/vx_uer.c val = vx_inb(chip, CSUER); val 103 sound/drivers/vx/vx_uer.c val = vx_inl(chip, CSUER); val 104 sound/drivers/vx/vx_uer.c if (val < 0) val 105 sound/drivers/vx/vx_uer.c return val; val 107 sound/drivers/vx/vx_uer.c if (val & VX_SUER_CLOCK_PRESENT_MASK) { val 108 sound/drivers/vx/vx_uer.c switch (val & VX_SUER_FREQ_MASK) { val 120 sound/drivers/vx/vx_uer.c if (val & VX_SUER_DATA_PRESENT_MASK) val 457 sound/firewire/bebob/bebob_maudio.c int err, val; val 470 sound/firewire/bebob/bebob_maudio.c val = (params->dig_in_fmt << 1) | (dig_in_iface & 0x01); val 473 sound/firewire/bebob/bebob_maudio.c if (val > 2) val 474 sound/firewire/bebob/bebob_maudio.c val = 2; val 476 sound/firewire/bebob/bebob_maudio.c uval->value.enumerated.item[0] = val; val 31 sound/firewire/dice/dice-presonus.c int key, val, model_id; val 36 sound/firewire/dice/dice-presonus.c while (fw_csr_iterator_next(&it, &key, &val)) { val 38 sound/firewire/dice/dice-presonus.c model_id = val; val 73 sound/firewire/dice/dice-tcelectronic.c int key, val, model_id; val 78 sound/firewire/dice/dice-tcelectronic.c while (fw_csr_iterator_next(&it, &key, &val)) { val 80 sound/firewire/dice/dice-tcelectronic.c model_id = val; val 34 sound/firewire/dice/dice.c int key, val, vendor = -1, model = -1; val 44 sound/firewire/dice/dice.c while (fw_csr_iterator_next(&it, &key, &val)) { val 47 sound/firewire/dice/dice.c vendor = val; val 50 sound/firewire/dice/dice.c model = val; val 93 sound/firewire/motu/motu-protocol-v3.c unsigned int val; val 102 sound/firewire/motu/motu-protocol-v3.c val = data & V3_CLOCK_SOURCE_MASK; val 103 sound/firewire/motu/motu-protocol-v3.c if (val == 0x00) { val 105 sound/firewire/motu/motu-protocol-v3.c } else if (val == 0x01) { val 107 sound/firewire/motu/motu-protocol-v3.c } else if (val == 0x10) { val 109 sound/firewire/motu/motu-protocol-v3.c } else if (val == 0x18 || val == 0x19) { val 116 sound/firewire/motu/motu-protocol-v3.c if (val == 0x18) { val 32 sound/firewire/motu/motu.c int key, val; val 36 sound/firewire/motu/motu.c while (fw_csr_iterator_next(&it, &key, &val)) { val 39 sound/firewire/motu/motu.c version = val; val 128 sound/firewire/oxfw/oxfw.c int key, val; val 165 sound/firewire/oxfw/oxfw.c while (fw_csr_iterator_next(&it, &key, &val)) { val 167 sound/firewire/oxfw/oxfw.c vendor = val; val 169 sound/firewire/oxfw/oxfw.c model = val; val 166 sound/hda/ext/hdac_ext_controller.c u32 val; val 173 sound/hda/ext/hdac_ext_controller.c val = readl(link->ml_addr + AZX_REG_ML_LCTL); val 175 sound/hda/ext/hdac_ext_controller.c if (((val & mask) >> AZX_MLCTL_CPA_SHIFT)) val 178 sound/hda/ext/hdac_ext_controller.c if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT)) val 119 sound/hda/ext/hdac_ext_stream.c u32 val; val 123 sound/hda/ext/hdac_ext_stream.c val = readw(bus->ppcap + AZX_REG_PP_PPCTL) & mask; val 125 sound/hda/ext/hdac_ext_stream.c if (decouple && !val) val 127 sound/hda/ext/hdac_ext_stream.c else if (!decouple && val) val 162 sound/hda/ext/hdac_ext_stream.c unsigned char val; val 172 sound/hda/ext/hdac_ext_stream.c val = readl(stream->pplc_addr + AZX_REG_PPLCCTL) & val 174 sound/hda/ext/hdac_ext_stream.c if (val) val 178 sound/hda/ext/hdac_ext_stream.c val &= ~AZX_PPLCCTL_STRST; val 179 sound/hda/ext/hdac_ext_stream.c writel(val, stream->pplc_addr + AZX_REG_PPLCCTL); val 185 sound/hda/ext/hdac_ext_stream.c val = readl(stream->pplc_addr + AZX_REG_PPLCCTL) & AZX_PPLCCTL_STRST; val 186 sound/hda/ext/hdac_ext_stream.c if (!val) val 202 sound/hda/ext/hdac_ext_stream.c unsigned int val; val 207 sound/hda/ext/hdac_ext_stream.c val = readl(stream->pplc_addr + AZX_REG_PPLCCTL); val 208 sound/hda/ext/hdac_ext_stream.c val = (val & ~AZX_PPLCCTL_STRM_MASK) | val 210 sound/hda/ext/hdac_ext_stream.c writel(val, stream->pplc_addr + AZX_REG_PPLCCTL); val 234 sound/hda/hdac_bus.c void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, val 244 sound/hda/hdac_bus.c v |= val << shift; val 141 sound/hda/hdac_controller.c int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) val 143 sound/hda/hdac_controller.c unsigned int addr = azx_command_addr(val); val 148 sound/hda/hdac_controller.c bus->last_cmd[azx_command_addr(val)] = val; val 168 sound/hda/hdac_controller.c bus->corb.buf[wp] = cpu_to_le32(val); val 225 sound/hda/hdac_device.c u32 val, addr; val 235 sound/hda/hdac_device.c val = addr << 28; val 236 sound/hda/hdac_device.c val |= (u32)nid << 20; val 237 sound/hda/hdac_device.c val |= verb << 8; val 238 sound/hda/hdac_device.c val |= parm; val 239 sound/hda/hdac_device.c return val; val 309 sound/hda/hdac_device.c unsigned int cmd, val; val 312 sound/hda/hdac_device.c if (snd_hdac_regmap_read_raw_uncached(codec, cmd, &val) < 0) val 314 sound/hda/hdac_device.c return val; val 326 sound/hda/hdac_device.c unsigned int parm, unsigned int val) val 335 sound/hda/hdac_device.c err = snd_hdac_regmap_write_raw(codec, verb, val); val 502 sound/hda/hdac_device.c hda_nid_t val, n; val 512 sound/hda/hdac_device.c val = parm & mask; val 513 sound/hda/hdac_device.c if (val == 0 && null_count++) { /* no second chance */ val 522 sound/hda/hdac_device.c if (!prev_nid || prev_nid >= val) { val 525 sound/hda/hdac_device.c prev_nid, val); val 528 sound/hda/hdac_device.c for (n = prev_nid + 1; n <= val; n++) { val 540 sound/hda/hdac_device.c conn_list[conns] = val; val 544 sound/hda/hdac_device.c prev_nid = val; val 739 sound/hda/hdac_device.c unsigned int val = 0; val 743 sound/hda/hdac_device.c val = rate_bits[i].hda_fmt; val 751 sound/hda/hdac_device.c val |= channels - 1; val 755 sound/hda/hdac_device.c val |= AC_FMT_BITS_8; val 758 sound/hda/hdac_device.c val |= AC_FMT_BITS_16; val 764 sound/hda/hdac_device.c val |= AC_FMT_BITS_32; val 766 sound/hda/hdac_device.c val |= AC_FMT_BITS_24; val 768 sound/hda/hdac_device.c val |= AC_FMT_BITS_20; val 775 sound/hda/hdac_device.c val |= AC_FMT_TYPE_NON_PCM; val 777 sound/hda/hdac_device.c return val; val 783 sound/hda/hdac_device.c unsigned int val = 0; val 787 sound/hda/hdac_device.c val = snd_hdac_read_parm(codec, nid, AC_PAR_PCM); val 788 sound/hda/hdac_device.c if (!val || val == -1) val 789 sound/hda/hdac_device.c val = snd_hdac_read_parm(codec, codec->afg, AC_PAR_PCM); val 790 sound/hda/hdac_device.c if (!val || val == -1) val 792 sound/hda/hdac_device.c return val; val 822 sound/hda/hdac_device.c unsigned int i, val, wcaps; val 825 sound/hda/hdac_device.c val = query_pcm_param(codec, nid); val 830 sound/hda/hdac_device.c if (val & (1 << i)) val 836 sound/hda/hdac_device.c nid, val, val 853 sound/hda/hdac_device.c if (val & AC_SUPPCM_BITS_8) { val 857 sound/hda/hdac_device.c if (val & AC_SUPPCM_BITS_16) { val 862 sound/hda/hdac_device.c if (val & AC_SUPPCM_BITS_32) val 864 sound/hda/hdac_device.c if (val & (AC_SUPPCM_BITS_20|AC_SUPPCM_BITS_24)) val 866 sound/hda/hdac_device.c if (val & AC_SUPPCM_BITS_24) val 868 sound/hda/hdac_device.c else if (val & AC_SUPPCM_BITS_20) val 870 sound/hda/hdac_device.c } else if (val & (AC_SUPPCM_BITS_20|AC_SUPPCM_BITS_24| val 873 sound/hda/hdac_device.c if (val & AC_SUPPCM_BITS_32) val 875 sound/hda/hdac_device.c else if (val & AC_SUPPCM_BITS_24) val 877 sound/hda/hdac_device.c else if (val & AC_SUPPCM_BITS_20) val 899 sound/hda/hdac_device.c nid, val, val 928 sound/hda/hdac_device.c unsigned int val = 0, rate, stream; val 930 sound/hda/hdac_device.c val = query_pcm_param(codec, nid); val 931 sound/hda/hdac_device.c if (!val) val 937 sound/hda/hdac_device.c if (val & (1 << i)) val 951 sound/hda/hdac_device.c if (!(val & AC_SUPPCM_BITS_8)) val 955 sound/hda/hdac_device.c if (!(val & AC_SUPPCM_BITS_16)) val 959 sound/hda/hdac_device.c if (!(val & AC_SUPPCM_BITS_20)) val 963 sound/hda/hdac_device.c if (!(val & AC_SUPPCM_BITS_24)) val 967 sound/hda/hdac_device.c if (!(val & AC_SUPPCM_BITS_32)) val 158 sound/hda/hdac_regmap.c unsigned int reg, unsigned int *val) val 170 sound/hda/hdac_regmap.c *val = left | (right << 8); val 176 sound/hda/hdac_regmap.c unsigned int reg, unsigned int val) val 188 sound/hda/hdac_regmap.c left = val & 0xff; val 189 sound/hda/hdac_regmap.c right = (val >> 8) & 0xff; val 206 sound/hda/hdac_regmap.c unsigned int *val) val 219 sound/hda/hdac_regmap.c return snd_hdac_exec_verb(codec, verb, 0, val); val 224 sound/hda/hdac_regmap.c unsigned int val) val 237 sound/hda/hdac_regmap.c (val & 0xffff); val 241 sound/hda/hdac_regmap.c static int hda_reg_read(void *context, unsigned int reg, unsigned int *val) val 255 sound/hda/hdac_regmap.c err = hda_reg_read_stereo_amp(codec, reg, val); val 259 sound/hda/hdac_regmap.c err = hda_reg_read_coef(codec, reg, val); val 265 sound/hda/hdac_regmap.c err = snd_hdac_exec_verb(codec, reg, 0, val); val 270 sound/hda/hdac_regmap.c if (*val & AC_PWRST_ERROR) val 271 sound/hda/hdac_regmap.c *val = -1; val 273 sound/hda/hdac_regmap.c *val = (*val >> 4) & 0x0f; val 280 sound/hda/hdac_regmap.c static int hda_reg_write(void *context, unsigned int reg, unsigned int val) val 301 sound/hda/hdac_regmap.c err = hda_reg_write_stereo_amp(codec, reg, val); val 306 sound/hda/hdac_regmap.c err = hda_reg_write_coef(codec, reg, val); val 312 sound/hda/hdac_regmap.c if ((reg & AC_AMP_FAKE_MUTE) && (val & AC_AMP_MUTE)) val 313 sound/hda/hdac_regmap.c val = 0; val 342 sound/hda/hdac_regmap.c reg |= (verb + i) << 8 | ((val >> (8 * i)) & 0xff); val 427 sound/hda/hdac_regmap.c unsigned int val) val 433 sound/hda/hdac_regmap.c err = hda_reg_write(codec, reg, val); val 435 sound/hda/hdac_regmap.c err = regmap_write(codec->regmap, reg, val); val 461 sound/hda/hdac_regmap.c unsigned int val) val 463 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_write(codec, reg, val)); val 468 sound/hda/hdac_regmap.c unsigned int *val, bool uncached) val 474 sound/hda/hdac_regmap.c err = hda_reg_read(codec, reg, val); val 476 sound/hda/hdac_regmap.c err = regmap_read(codec->regmap, reg, val); val 482 sound/hda/hdac_regmap.c unsigned int reg, unsigned int *val, val 485 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_read(codec, reg, val, uncached)); val 497 sound/hda/hdac_regmap.c unsigned int *val) val 499 sound/hda/hdac_regmap.c return __snd_hdac_regmap_read_raw(codec, reg, val, false); val 507 sound/hda/hdac_regmap.c unsigned int reg, unsigned int *val) val 509 sound/hda/hdac_regmap.c return __snd_hdac_regmap_read_raw(codec, reg, val, true); val 513 sound/hda/hdac_regmap.c unsigned int mask, unsigned int val) val 521 sound/hda/hdac_regmap.c err = regmap_update_bits_check(codec->regmap, reg, mask, val, val 528 sound/hda/hdac_regmap.c val &= mask; val 529 sound/hda/hdac_regmap.c val |= orig & ~mask; val 530 sound/hda/hdac_regmap.c if (val != orig) { val 531 sound/hda/hdac_regmap.c err = hda_reg_write(codec, reg, val); val 551 sound/hda/hdac_regmap.c unsigned int mask, unsigned int val) val 553 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_update(codec, reg, mask, val)); val 558 sound/hda/hdac_regmap.c unsigned int mask, unsigned int val) val 564 sound/hda/hdac_regmap.c return reg_raw_update(codec, reg, mask, val); val 571 sound/hda/hdac_regmap.c err = regmap_update_bits(codec->regmap, reg, mask, val); val 588 sound/hda/hdac_regmap.c unsigned int mask, unsigned int val) val 590 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_update_once(codec, reg, mask, val)); val 151 sound/hda/hdac_stream.c unsigned char val; val 160 sound/hda/hdac_stream.c val = snd_hdac_stream_readb(azx_dev, SD_CTL) & val 162 sound/hda/hdac_stream.c if (val) val 165 sound/hda/hdac_stream.c val &= ~SD_CTL_STREAM_RESET; val 166 sound/hda/hdac_stream.c snd_hdac_stream_writeb(azx_dev, SD_CTL, val); val 172 sound/hda/hdac_stream.c val = snd_hdac_stream_readb(azx_dev, SD_CTL) & val 174 sound/hda/hdac_stream.c if (!val) val 192 sound/hda/hdac_stream.c unsigned int val; val 201 sound/hda/hdac_stream.c val = snd_hdac_stream_readl(azx_dev, SD_CTL); val 202 sound/hda/hdac_stream.c val = (val & ~SD_CTL_STREAM_TAG_MASK) | val 205 sound/hda/hdac_stream.c val |= SD_CTL_TRAFFIC_PRIO; val 206 sound/hda/hdac_stream.c snd_hdac_stream_writel(azx_dev, SD_CTL, val); val 599 sound/hda/hdac_stream.c unsigned int val; val 603 sound/hda/hdac_stream.c val = _snd_hdac_chip_readl(bus, reg); val 605 sound/hda/hdac_stream.c val |= streams; val 607 sound/hda/hdac_stream.c val &= ~streams; val 608 sound/hda/hdac_stream.c _snd_hdac_chip_writel(bus, reg, val); val 179 sound/hda/hdac_sysfs.c unsigned int val; val 183 sound/hda/hdac_sysfs.c if (snd_hdac_read(codec, nid, AC_VERB_GET_CONFIG_DEFAULT, 0, &val)) val 185 sound/hda/hdac_sysfs.c return sprintf(buf, "0x%08x\n", val); val 46 sound/i2c/cs8427.c unsigned char val) val 52 sound/i2c/cs8427.c buf[1] = val; val 30 sound/i2c/other/ak4113.c unsigned char val) val 32 sound/i2c/other/ak4113.c ak4113->write(ak4113->private_data, reg, val); val 34 sound/i2c/other/ak4113.c ak4113->regmap[reg] = val; val 102 sound/i2c/other/ak4113.c unsigned char mask, unsigned char val) val 106 sound/i2c/other/ak4113.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); val 470 sound/i2c/other/ak4113.c int reg, val; val 473 sound/i2c/other/ak4113.c val = reg_read(ak4113, reg); val 474 sound/i2c/other/ak4113.c snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val); val 27 sound/i2c/other/ak4114.c static void reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char val) val 29 sound/i2c/other/ak4114.c ak4114->write(ak4114->private_data, reg, val); val 31 sound/i2c/other/ak4114.c ak4114->regmap[reg] = val; val 33 sound/i2c/other/ak4114.c ak4114->txcsb[reg-AK4114_REG_TXCSB0] = val; val 113 sound/i2c/other/ak4114.c void snd_ak4114_reg_write(struct ak4114 *chip, unsigned char reg, unsigned char mask, unsigned char val) val 116 sound/i2c/other/ak4114.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); val 119 sound/i2c/other/ak4114.c (chip->txcsb[reg-AK4114_REG_TXCSB0] & ~mask) | val); val 443 sound/i2c/other/ak4114.c int reg, val; val 446 sound/i2c/other/ak4114.c val = reg_read(ak4114, reg); val 447 sound/i2c/other/ak4114.c snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val); val 25 sound/i2c/other/ak4117.c static void reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char val) val 27 sound/i2c/other/ak4117.c ak4117->write(ak4117->private_data, reg, val); val 29 sound/i2c/other/ak4117.c ak4117->regmap[reg] = val; val 101 sound/i2c/other/ak4117.c void snd_ak4117_reg_write(struct ak4117 *chip, unsigned char reg, unsigned char mask, unsigned char val) val 105 sound/i2c/other/ak4117.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); val 27 sound/i2c/other/ak4xxx-adda.c unsigned char val) val 30 sound/i2c/other/ak4xxx-adda.c ak->ops.write(ak, chip, reg, val); val 33 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_set(ak, chip, reg, val); val 341 sound/i2c/other/ak4xxx-adda.c #define AK_GET_CHIP(val) (((val) >> 8) & 0xff) val 342 sound/i2c/other/ak4xxx-adda.c #define AK_GET_ADDR(val) ((val) & 0xff) val 343 sound/i2c/other/ak4xxx-adda.c #define AK_GET_SHIFT(val) (((val) >> 16) & 0x0f) val 344 sound/i2c/other/ak4xxx-adda.c #define AK_GET_VOL_CVT(val) (((val) >> 21) & 1) val 345 sound/i2c/other/ak4xxx-adda.c #define AK_GET_IPGA(val) (((val) >> 20) & 1) val 346 sound/i2c/other/ak4xxx-adda.c #define AK_GET_NEEDSMSB(val) (((val) >> 22) & 1) val 347 sound/i2c/other/ak4xxx-adda.c #define AK_GET_INVERT(val) (((val) >> 23) & 1) val 348 sound/i2c/other/ak4xxx-adda.c #define AK_GET_MASK(val) (((val) >> 24) & 0xff) val 404 sound/i2c/other/ak4xxx-adda.c unsigned int val = ucontrol->value.integer.value[0]; val 405 sound/i2c/other/ak4xxx-adda.c if (val > mask) val 407 sound/i2c/other/ak4xxx-adda.c return put_ak_reg(kcontrol, AK_GET_ADDR(kcontrol->private_value), val); val 439 sound/i2c/other/ak4xxx-adda.c unsigned int val[2]; val 442 sound/i2c/other/ak4xxx-adda.c val[0] = ucontrol->value.integer.value[0]; val 443 sound/i2c/other/ak4xxx-adda.c val[1] = ucontrol->value.integer.value[1]; val 444 sound/i2c/other/ak4xxx-adda.c if (val[0] > mask || val[1] > mask) val 446 sound/i2c/other/ak4xxx-adda.c change = put_ak_reg(kcontrol, addr, val[0]); val 447 sound/i2c/other/ak4xxx-adda.c change |= put_ak_reg(kcontrol, addr + 1, val[1]); val 501 sound/i2c/other/ak4xxx-adda.c unsigned char val = snd_akm4xxx_get(ak, chip, addr) & (1<<shift); val 503 sound/i2c/other/ak4xxx-adda.c val = ! val; val 504 sound/i2c/other/ak4xxx-adda.c ucontrol->value.integer.value[0] = (val & (1<<shift)) != 0; val 517 sound/i2c/other/ak4xxx-adda.c unsigned char val, oval; val 524 sound/i2c/other/ak4xxx-adda.c val = oval | (1<<shift); val 526 sound/i2c/other/ak4xxx-adda.c val = oval & ~(1<<shift); val 527 sound/i2c/other/ak4xxx-adda.c change = (oval != val); val 529 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_write(ak, chip, addr, val); val 568 sound/i2c/other/ak4xxx-adda.c unsigned char val; val 570 sound/i2c/other/ak4xxx-adda.c val = snd_akm4xxx_get(ak, chip, addr) & mask; val 571 sound/i2c/other/ak4xxx-adda.c ucontrol->value.enumerated.item[0] = val; val 583 sound/i2c/other/ak4xxx-adda.c unsigned char oval, val; val 590 sound/i2c/other/ak4xxx-adda.c val = oval & ~mask; val 591 sound/i2c/other/ak4xxx-adda.c val |= ucontrol->value.enumerated.item[0] & mask; val 592 sound/i2c/other/ak4xxx-adda.c if (val != oval) { val 593 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_write(ak, chip, addr, val); val 669 sound/i2c/other/ak4xxx-adda.c int val = idx < 6 ? idx + 2 : (idx - 6) + 0xb; val 671 sound/i2c/other/ak4xxx-adda.c AK_COMPOSE(0, val, 0, 255) | AK_INVERT; val 853 sound/i2c/other/ak4xxx-adda.c int reg, val, chip; val 856 sound/i2c/other/ak4xxx-adda.c val = snd_akm4xxx_get(ak, chip, reg); val 858 sound/i2c/other/ak4xxx-adda.c reg, val); val 147 sound/i2c/other/pt2258.c int val; val 149 sound/i2c/other/pt2258.c val = !ucontrol->value.integer.value[0]; val 150 sound/i2c/other/pt2258.c if (pt->mute == val) val 153 sound/i2c/other/pt2258.c pt->mute = val; val 154 sound/i2c/other/pt2258.c bytes[0] = val ? PT2258_CMD_MUTE : PT2258_CMD_UNMUTE; val 729 sound/isa/ad1816a/ad1816a_lib.c unsigned short val; val 732 sound/isa/ad1816a/ad1816a_lib.c val = snd_ad1816a_read(chip, AD1816A_ADC_SOURCE_SEL); val 734 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.enumerated.item[0] = (val >> 12) & 7; val 735 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.enumerated.item[1] = (val >> 4) & 7; val 743 sound/isa/ad1816a/ad1816a_lib.c unsigned short val; val 749 sound/isa/ad1816a/ad1816a_lib.c val = (ucontrol->value.enumerated.item[0] << 12) | val 752 sound/isa/ad1816a/ad1816a_lib.c change = snd_ad1816a_read(chip, AD1816A_ADC_SOURCE_SEL) != val; val 753 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_write(chip, AD1816A_ADC_SOURCE_SEL, val); val 807 sound/isa/ad1816a/ad1816a_lib.c unsigned short old_val, val; val 809 sound/isa/ad1816a/ad1816a_lib.c val = (ucontrol->value.integer.value[0] & mask); val 811 sound/isa/ad1816a/ad1816a_lib.c val = mask - val; val 812 sound/isa/ad1816a/ad1816a_lib.c val <<= shift; val 815 sound/isa/ad1816a/ad1816a_lib.c val = (old_val & ~(mask << shift)) | val; val 816 sound/isa/ad1816a/ad1816a_lib.c change = val != old_val; val 817 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_write(chip, reg, val); val 855 sound/isa/ad1816a/ad1816a_lib.c unsigned short val; val 858 sound/isa/ad1816a/ad1816a_lib.c val = snd_ad1816a_read(chip, reg); val 859 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[0] = (val >> shift_left) & mask; val 860 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[1] = (val >> shift_right) & mask; val 138 sound/isa/azt2320.c static int snd_card_azt2320_command(unsigned long port, unsigned char val) val 146 sound/isa/azt2320.c outb(val, port + 0x0c); val 122 sound/isa/cmi8328.c static void snd_cmi8328_cfg_write(u16 port, u8 reg, u8 val) val 127 sound/isa/cmi8328.c outb(val, port + 3); /* yes, value goes to the same port as index */ val 238 sound/isa/cmi8328.c u8 val; val 278 sound/isa/cmi8328.c val = irq_bits[pos] << 3; val 285 sound/isa/cmi8328.c val |= dma_bits[pos]; val 293 sound/isa/cmi8328.c val |= 0x04; /* enable separate capture DMA */ val 295 sound/isa/cmi8328.c outb(val, port); val 304 sound/isa/cmi8328.c cmi->wss_cfg = val; val 337 sound/isa/cmi8328.c val = CFG2_MPU_ENABLE; val 343 sound/isa/cmi8328.c val |= mpu_port_bits[pos] << 5; val 349 sound/isa/cmi8328.c val |= mpu_irq_bits[pos] << 3; val 350 sound/isa/cmi8328.c snd_cmi8328_cfg_write(port, CFG2, val); val 109 sound/isa/cs423x/cs4236_lib.c unsigned char reg, unsigned char val) val 112 sound/isa/cs423x/cs4236_lib.c outb(chip->cimage[reg] = val, chip->cport + 4); val 431 sound/isa/cs423x/cs4236_lib.c unsigned short val; val 433 sound/isa/cs423x/cs4236_lib.c val = (ucontrol->value.integer.value[0] & mask); val 435 sound/isa/cs423x/cs4236_lib.c val = mask - val; val 436 sound/isa/cs423x/cs4236_lib.c val <<= shift; val 438 sound/isa/cs423x/cs4236_lib.c val = (chip->eimage[CS4236_REG(reg)] & ~(mask << shift)) | val; val 439 sound/isa/cs423x/cs4236_lib.c change = val != chip->eimage[CS4236_REG(reg)]; val 440 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ext_out(chip, reg, val); val 477 sound/isa/cs423x/cs4236_lib.c unsigned short val; val 479 sound/isa/cs423x/cs4236_lib.c val = (ucontrol->value.integer.value[0] & mask); val 481 sound/isa/cs423x/cs4236_lib.c val = mask - val; val 482 sound/isa/cs423x/cs4236_lib.c val <<= shift; val 484 sound/isa/cs423x/cs4236_lib.c val = (chip->cimage[reg] & ~(mask << shift)) | val; val 485 sound/isa/cs423x/cs4236_lib.c change = val != chip->cimage[reg]; val 486 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ctrl_out(chip, reg, val); val 957 sound/isa/cs423x/cs4236_lib.c unsigned short enable, val; val 964 sound/isa/cs423x/cs4236_lib.c val = (chip->image[CS4231_ALT_FEATURE_1] & ~0x0e) | (0<<2) | (enable << 1); val 965 sound/isa/cs423x/cs4236_lib.c change = val != chip->image[CS4231_ALT_FEATURE_1]; val 966 sound/isa/cs423x/cs4236_lib.c snd_wss_out(chip, CS4231_ALT_FEATURE_1, val); val 967 sound/isa/cs423x/cs4236_lib.c val = snd_cs4236_ctrl_in(chip, 4) | 0xc0; val 968 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ctrl_out(chip, 4, val); val 970 sound/isa/cs423x/cs4236_lib.c val &= ~0x40; val 971 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ctrl_out(chip, 4, val); val 24 sound/isa/es1688/es1688_lib.c static int snd_es1688_dsp_command(struct snd_es1688 *chip, unsigned char val) val 30 sound/isa/es1688/es1688_lib.c outb(val, ES1688P(chip, COMMAND)); val 34 sound/isa/es1688/es1688_lib.c printk(KERN_DEBUG "snd_es1688_dsp_command: timeout (0x%x)\n", val); val 320 sound/isa/es1688/es1688_lib.c int val; val 329 sound/isa/es1688/es1688_lib.c val = snd_es1688_read(chip, 0xb8); val 330 sound/isa/es1688/es1688_lib.c if ((val < 0) || (val & 0x0f) == value) { val 335 sound/isa/es1688/es1688_lib.c printk(KERN_DEBUG "trigger: val = 0x%x, value = 0x%x\n", val, value); val 339 sound/isa/es1688/es1688_lib.c snd_es1688_write(chip, 0xb8, (val & 0xf0) | value); val 989 sound/isa/es1688/es1688_lib.c unsigned char reg, val; val 1002 sound/isa/es1688/es1688_lib.c val = snd_es1688_init_table[idx][1]; val 1004 sound/isa/es1688/es1688_lib.c snd_es1688_mixer_write(chip, reg, val); val 1006 sound/isa/es1688/es1688_lib.c snd_es1688_write(chip, reg, val); val 162 sound/isa/es18xx.c static int snd_es18xx_dsp_command(struct snd_es18xx *chip, unsigned char val) val 168 sound/isa/es18xx.c outb(val, chip->port + 0x0C); val 171 sound/isa/es18xx.c snd_printk(KERN_ERR "dsp_command: timeout (0x%x)\n", val); val 231 sound/isa/es18xx.c unsigned char mask, unsigned char val) val 249 sound/isa/es18xx.c if (val != oval) { val 253 sound/isa/es18xx.c new = (old & ~mask) | (val & mask); val 297 sound/isa/es18xx.c unsigned char mask, unsigned char val) val 305 sound/isa/es18xx.c if (val != oval) { val 306 sound/isa/es18xx.c new = (old & ~mask) | (val & mask); val 998 sound/isa/es18xx.c unsigned char val = ucontrol->value.enumerated.item[0]; val 1005 sound/isa/es18xx.c if (val > 4) val 1007 sound/isa/es18xx.c if (val == 4) { val 1009 sound/isa/es18xx.c val = 3; val 1016 sound/isa/es18xx.c if (val > 3) val 1018 sound/isa/es18xx.c val = map4Source[val]; val 1023 sound/isa/es18xx.c if (val > 7) val 1029 sound/isa/es18xx.c return (snd_es18xx_mixer_bits(chip, 0x1c, 0x07, val) != val) || retVal; val 1037 sound/isa/es18xx.c unsigned char val = snd_es18xx_mixer_read(chip, 0x50); val 1038 sound/isa/es18xx.c ucontrol->value.integer.value[0] = !!(val & 8); val 1094 sound/isa/es18xx.c unsigned char mask, unsigned char val) val 1097 sound/isa/es18xx.c return snd_es18xx_mixer_bits(chip, reg, mask, val); val 1099 sound/isa/es18xx.c return snd_es18xx_bits(chip, reg, mask, val); val 1138 sound/isa/es18xx.c int val; val 1141 sound/isa/es18xx.c val = inb(chip->port + ES18XX_PM); val 1143 sound/isa/es18xx.c val = snd_es18xx_reg_read(chip, reg); val 1144 sound/isa/es18xx.c ucontrol->value.integer.value[0] = (val >> shift) & mask; val 1158 sound/isa/es18xx.c unsigned char val; val 1160 sound/isa/es18xx.c val = (ucontrol->value.integer.value[0] & mask); val 1162 sound/isa/es18xx.c val = mask - val; val 1164 sound/isa/es18xx.c val <<= shift; val 1168 sound/isa/es18xx.c if ((cur & mask) == val) val 1170 sound/isa/es18xx.c outb((cur & ~mask) | val, chip->port + ES18XX_PM); val 1174 sound/isa/es18xx.c return snd_es18xx_reg_bits(chip, reg, mask, val) != val; val 74 sound/isa/galaxy/galaxy.c static int dsp_get_byte(void __iomem *port, u8 *val) val 83 sound/isa/galaxy/galaxy.c *val = ioread8(port + DSP_PORT_READ); val 89 sound/isa/galaxy/galaxy.c u8 val; val 95 sound/isa/galaxy/galaxy.c if (dsp_get_byte(port, &val) < 0 || val != DSP_SIGNATURE) val 356 sound/isa/gus/gus_main.c unsigned char val, rev; val 362 sound/isa/gus/gus_main.c val = inb(GUSP(gus, REGCNTRLS)); val 365 sound/isa/gus/gus_main.c snd_printdd("GF1 [0x%lx] init - val = 0x%x, rev = 0x%x\n", gus->gf1.port, val, rev); val 368 sound/isa/gus/gus_main.c if ((val != 255 && (val & 0x06)) || (rev >= 5 && rev != 255)) { val 390 sound/isa/gus/gus_main.c snd_printk(KERN_ERR "unknown GF1 revision number at 0x%lx - 0x%x (0x%x)\n", gus->gf1.port, rev, val); val 601 sound/isa/gus/gus_pcm.c int val; val 604 sound/isa/gus/gus_pcm.c val = gus->gf1.pcm_rcntrl_reg; val 606 sound/isa/gus/gus_pcm.c val = 0; val 612 sound/isa/gus/gus_pcm.c snd_gf1_write8(gus, SNDRV_GF1_GB_REC_DMA_CONTROL, val); val 117 sound/isa/msnd/msnd_midi.c unsigned char val = readw(pwMIDQData + 2 * head); val 120 sound/isa/msnd/msnd_midi.c snd_rawmidi_receive(mpu->substream_input, &val, 1); val 82 sound/isa/msnd/msnd_pinnacle_mixer.c static int snd_msndmix_set_mux(struct snd_msnd *chip, int val) val 88 sound/isa/msnd/msnd_pinnacle_mixer.c switch (val) { val 366 sound/isa/opl3sa2.c unsigned short val, oval; val 368 sound/isa/opl3sa2.c val = (ucontrol->value.integer.value[0] & mask); val 370 sound/isa/opl3sa2.c val = mask - val; val 371 sound/isa/opl3sa2.c val <<= shift; val 374 sound/isa/opl3sa2.c val = (oval & ~(mask << shift)) | val; val 375 sound/isa/opl3sa2.c change = val != oval; val 376 sound/isa/opl3sa2.c __snd_opl3sa2_write(chip, reg, val); val 35 sound/isa/sb/emu8000.c void snd_emu8000_poke(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, unsigned int val) val 43 sound/isa/sb/emu8000.c outw((unsigned short)val, port); /* Send data */ val 63 sound/isa/sb/emu8000.c void snd_emu8000_poke_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, unsigned int val) val 71 sound/isa/sb/emu8000.c outw((unsigned short)val, port); /* Send low word of data */ val 72 sound/isa/sb/emu8000.c outw((unsigned short)(val>>16), port+2); /* Send high word of data */ val 173 sound/isa/sb/emu8000_callback.c int state, val; val 183 sound/isa/sb/emu8000_callback.c val = (EMU8000_CVCF_READ(hw, vp->ch) >> 16) & 0xffff; val 184 sound/isa/sb/emu8000_callback.c if (! val) val 195 sound/isa/sb/emu8000_callback.c val = EMU8000_CCCA_READ(hw, vp->ch) & 0xffffff; val 196 sound/isa/sb/emu8000_callback.c if (val >= vp->reg.loopstart) val 173 sound/isa/sb/emu8000_pcm.c int val = EMU8000_CCCA_READ(rec->emu, ch) & 0xfffffff; val 174 sound/isa/sb/emu8000_pcm.c val -= rec->loop_start[ch] - 1; val 175 sound/isa/sb/emu8000_pcm.c return val; val 84 sound/isa/sb/jazz16.c unsigned char val; val 94 sound/isa/sb/jazz16.c val = port & 0x70; val 95 sound/isa/sb/jazz16.c val |= (mpu_port & 0x30) >> 4; val 96 sound/isa/sb/jazz16.c outb(val, 0x201); val 106 sound/isa/sb/jazz16.c int val; val 118 sound/isa/sb/jazz16.c for (val = 0; val < 4; val++) { val 119 sound/isa/sb/jazz16.c err = jazz16_configure_ports(port, mpu_port, val); val 135 sound/isa/sb/jazz16.c val = snd_sbdsp_get_byte(&chip); val 136 sound/isa/sb/jazz16.c if (val >= 0x30) val 139 sound/isa/sb/jazz16.c if ((val & 0xf0) != 0x10) { val 150 sound/isa/sb/jazz16.c val, err); val 72 sound/isa/sb/sb16_csp.c static int set_codec_parameter(struct snd_sb *chip, unsigned char par, unsigned char val); val 73 sound/isa/sb/sb16_csp.c static int set_register(struct snd_sb *chip, unsigned char reg, unsigned char val); val 487 sound/isa/sb/sb16_csp.c static int set_codec_parameter(struct snd_sb *chip, unsigned char par, unsigned char val) val 492 sound/isa/sb/sb16_csp.c dsp_cmd[1] = val; /* Parameter value */ val 504 sound/isa/sb/sb16_csp.c static int set_register(struct snd_sb *chip, unsigned char reg, unsigned char val) val 510 sound/isa/sb/sb16_csp.c dsp_cmd[2] = val; /* value */ val 30 sound/isa/sb/sb_common.c int snd_sbdsp_command(struct snd_sb *chip, unsigned char val) val 34 sound/isa/sb/sb_common.c snd_printk(KERN_DEBUG "command 0x%x\n", val); val 38 sound/isa/sb/sb_common.c outb(val, SBP(chip, COMMAND)); val 41 sound/isa/sb/sb_common.c snd_printd("%s [0x%lx]: timeout (0x%x)\n", __func__, chip->port, val); val 47 sound/isa/sb/sb_common.c int val; val 51 sound/isa/sb/sb_common.c val = inb(SBP(chip, READ)); val 53 sound/isa/sb/sb_common.c snd_printk(KERN_DEBUG "get_byte 0x%x\n", val); val 55 sound/isa/sb/sb_common.c return val; val 63 sound/isa/sb/sb_mixer.c unsigned char val; val 66 sound/isa/sb/sb_mixer.c val = (snd_sbmixer_read(sb, reg) >> shift) & mask; val 68 sound/isa/sb/sb_mixer.c ucontrol->value.integer.value[0] = val; val 80 sound/isa/sb/sb_mixer.c unsigned char val, oval; val 82 sound/isa/sb/sb_mixer.c val = (ucontrol->value.integer.value[0] & mask) << shift; val 85 sound/isa/sb/sb_mixer.c val = (oval & ~(mask << shift)) | val; val 86 sound/isa/sb/sb_mixer.c change = val != oval; val 88 sound/isa/sb/sb_mixer.c snd_sbmixer_write(sb, reg, val); val 877 sound/isa/sb/sb_mixer.c unsigned char *val = chip->saved_regs; val 881 sound/isa/sb/sb_mixer.c *val++ = snd_sbmixer_read(chip, *regs++); val 886 sound/isa/sb/sb_mixer.c unsigned char *val = chip->saved_regs; val 890 sound/isa/sb/sb_mixer.c snd_sbmixer_write(chip, *regs++, *val++); val 113 sound/isa/sc6000.c unsigned char val = 0; val 117 sound/isa/sc6000.c val = 0x28; val 120 sound/isa/sc6000.c val = 0x8; val 123 sound/isa/sc6000.c val = 0x10; val 126 sound/isa/sc6000.c val = 0x18; val 129 sound/isa/sc6000.c val = 0x20; val 134 sound/isa/sc6000.c return val; val 142 sound/isa/sc6000.c unsigned char val = 0; val 146 sound/isa/sc6000.c val = 1; val 149 sound/isa/sc6000.c val = 2; val 152 sound/isa/sc6000.c val = 3; val 157 sound/isa/sc6000.c return val; val 165 sound/isa/sc6000.c unsigned char val = 0; val 169 sound/isa/sc6000.c val = 4; val 172 sound/isa/sc6000.c val = 0x44; val 175 sound/isa/sc6000.c val = 0x84; val 178 sound/isa/sc6000.c val = 0xc4; val 183 sound/isa/sc6000.c return val; val 189 sound/isa/sc6000.c unsigned char val = 0; val 192 sound/isa/sc6000.c val = ioread8(vport + DSP_DATAVAIL); val 193 sound/isa/sc6000.c if (val & 0x80) val 212 sound/isa/sc6000.c unsigned char val; val 216 sound/isa/sc6000.c val = ioread8(vport + DSP_STATUS); val 220 sound/isa/sc6000.c if (!(val & 0x80)) { val 243 sound/isa/sc6000.c int val = sc6000_read(vport); val 245 sound/isa/sc6000.c if (val < 0) val 248 sound/isa/sc6000.c data[len++] = val; val 189 sound/isa/sscape.c unsigned char val) val 192 sound/isa/sscape.c outb(val, ODIE_DATA_IO(io_base)); val 200 sound/isa/sscape.c unsigned char val) val 205 sound/isa/sscape.c sscape_write_unsafe(s->io_base, reg, val); val 325 sound/isa/sscape.c unsigned char val = sscape_read_unsafe(io_base, GA_HMCTL_REG); val 326 sound/isa/sscape.c sscape_write_unsafe(io_base, GA_HMCTL_REG, (val & 0xcf) | 0x10); val 431 sound/isa/sscape.c unsigned char val; val 441 sound/isa/sscape.c val = sscape_read_unsafe(s->io_base, GA_HMCTL_REG); val 442 sound/isa/sscape.c sscape_write_unsafe(s->io_base, GA_HMCTL_REG, val & 0x3f); val 447 sound/isa/sscape.c val = (s->chip->dma1 << 4) | DMA_8BIT; val 448 sound/isa/sscape.c sscape_write_unsafe(s->io_base, GA_DMAA_REG, val); val 454 sound/isa/sscape.c val = sscape_read_unsafe(s->io_base, GA_HMCTL_REG); val 455 sound/isa/sscape.c sscape_write_unsafe(s->io_base, GA_HMCTL_REG, val | 0x80); val 490 sound/isa/sscape.c val = sscape_read_unsafe(s->io_base, GA_HMCTL_REG); val 491 sound/isa/sscape.c sscape_write_unsafe(s->io_base, GA_HMCTL_REG, val | 0x40); val 937 sound/isa/sscape.c int val; val 1038 sound/isa/sscape.c val = sscape_read_unsafe(sscape->io_base, GA_HMCTL_REG) & 0xF7; val 1040 sound/isa/sscape.c val |= 8; val 1041 sound/isa/sscape.c sscape_write_unsafe(sscape->io_base, GA_HMCTL_REG, val | 0x10); val 1277 sound/isa/wavefront/wavefront_synth.c int val; val 1279 sound/isa/wavefront/wavefront_synth.c if ((val = wavefront_read (dev)) == -1) { val 1284 sound/isa/wavefront/wavefront_synth.c d[0] = val; val 1286 sound/isa/wavefront/wavefront_synth.c if ((val = wavefront_read (dev)) == -1) { val 1291 sound/isa/wavefront/wavefront_synth.c d[1] = val; val 1778 sound/isa/wavefront/wavefront_synth.c int val, int port, unsigned long timeout) val 1787 sound/isa/wavefront/wavefront_synth.c outb (val,port); val 151 sound/isa/wss/wss_lib.c static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val) val 153 sound/isa/wss/wss_lib.c outb(val, chip->port + offset); val 217 sound/isa/wss/wss_lib.c unsigned char val) val 222 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REG), val); val 223 sound/isa/wss/wss_lib.c chip->eimage[CS4236_REG(reg)] = val; val 225 sound/isa/wss/wss_lib.c printk(KERN_DEBUG "ext out : reg = 0x%x, val = 0x%x\n", reg, val); val 2082 sound/isa/wss/wss_lib.c unsigned short val; val 2084 sound/isa/wss/wss_lib.c val = (ucontrol->value.integer.value[0] & mask); val 2086 sound/isa/wss/wss_lib.c val = mask - val; val 2087 sound/isa/wss/wss_lib.c val <<= shift; val 2089 sound/isa/wss/wss_lib.c val = (chip->image[reg] & ~(mask << shift)) | val; val 2090 sound/isa/wss/wss_lib.c change = val != chip->image[reg]; val 2091 sound/isa/wss/wss_lib.c snd_wss_out(chip, reg, val); val 347 sound/mips/ad1843.c int val = ad1843_read_bits(ad1843, &ad1843_LSS); val 349 sound/mips/ad1843.c if (val < 0 || val > 2) { val 350 sound/mips/ad1843.c val = 2; val 352 sound/mips/ad1843.c &ad1843_LSS, val, &ad1843_RSS, val); val 354 sound/mips/ad1843.c return val; val 97 sound/mips/hal2.c static inline void hal2_write(u32 val, u32 *reg) val 99 sound/mips/hal2.c __raw_writel(val, reg); val 117 sound/mips/hal2.c static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val) val 121 sound/mips/hal2.c hal2_write(val, ®s->idr0); val 129 sound/mips/hal2.c static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val) val 133 sound/mips/hal2.c hal2_write(val & 0xffff, ®s->idr0); val 134 sound/mips/hal2.c hal2_write(val >> 16, ®s->idr1); val 105 sound/mips/sgio2audio.c int val; val 113 sound/mips/sgio2audio.c val = readq(&mace->perif.audio.codec_control); /* flush bus */ val 116 sound/mips/sgio2audio.c val = readq(&mace->perif.audio.codec_read); val 119 sound/mips/sgio2audio.c return val; val 128 sound/mips/sgio2audio.c int val; val 137 sound/mips/sgio2audio.c val = readq(&mace->perif.audio.codec_control); /* flush bus */ val 991 sound/oss/dmasound/dmasound_core.c int val, result; val 1143 sound/oss/dmasound/dmasound_core.c val = dmasound.mach.capabilities & 0xffffff00; val 1144 sound/oss/dmasound/dmasound_core.c return IOCTL_OUT(arg,val); val 461 sound/pci/ac97/ac97_codec.c unsigned short val, bitmask; val 465 sound/pci/ac97/ac97_codec.c val = snd_ac97_read_cache(ac97, e->reg); val 466 sound/pci/ac97/ac97_codec.c ucontrol->value.enumerated.item[0] = (val >> e->shift_l) & (bitmask - 1); val 468 sound/pci/ac97/ac97_codec.c ucontrol->value.enumerated.item[1] = (val >> e->shift_r) & (bitmask - 1); val 478 sound/pci/ac97/ac97_codec.c unsigned short val; val 485 sound/pci/ac97/ac97_codec.c val = ucontrol->value.enumerated.item[0] << e->shift_l; val 490 sound/pci/ac97/ac97_codec.c val |= ucontrol->value.enumerated.item[1] << e->shift_r; val 493 sound/pci/ac97/ac97_codec.c return snd_ac97_update_bits(ac97, e->reg, mask, val); val 568 sound/pci/ac97/ac97_codec.c unsigned short val, val2, val_mask; val 571 sound/pci/ac97/ac97_codec.c val = (ucontrol->value.integer.value[0] & mask); val 573 sound/pci/ac97/ac97_codec.c val = mask - val; val 575 sound/pci/ac97/ac97_codec.c val = val << shift; val 581 sound/pci/ac97/ac97_codec.c val |= val2 << rshift; val 583 sound/pci/ac97/ac97_codec.c err = snd_ac97_update_bits(ac97, reg, val_mask, val); val 589 sound/pci/ac97/ac97_codec.c if (val & AC97_PD_EAPD) val 733 sound/pci/ac97/ac97_codec.c unsigned short val = 0; val 736 sound/pci/ac97/ac97_codec.c new = val = ucontrol->value.iec958.status[0] & (IEC958_AES0_PROFESSIONAL|IEC958_AES0_NONAUDIO); val 740 sound/pci/ac97/ac97_codec.c case IEC958_AES0_PRO_FS_44100: val |= 0<<12; break; val 741 sound/pci/ac97/ac97_codec.c case IEC958_AES0_PRO_FS_48000: val |= 2<<12; break; val 742 sound/pci/ac97/ac97_codec.c case IEC958_AES0_PRO_FS_32000: val |= 3<<12; break; val 743 sound/pci/ac97/ac97_codec.c default: val |= 1<<12; break; val 746 sound/pci/ac97/ac97_codec.c val |= 1<<3; val 752 sound/pci/ac97/ac97_codec.c val |= 1<<3; val 754 sound/pci/ac97/ac97_codec.c val |= 1<<2; val 755 sound/pci/ac97/ac97_codec.c val |= ((new >> 8) & 0xff) << 4; // category + original val 757 sound/pci/ac97/ac97_codec.c case IEC958_AES3_CON_FS_44100: val |= 0<<12; break; val 758 sound/pci/ac97/ac97_codec.c case IEC958_AES3_CON_FS_48000: val |= 2<<12; break; val 759 sound/pci/ac97/ac97_codec.c case IEC958_AES3_CON_FS_32000: val |= 3<<12; break; val 760 sound/pci/ac97/ac97_codec.c default: val |= 1<<12; break; val 769 sound/pci/ac97/ac97_codec.c int x = (val >> 12) & 0x03; val 775 sound/pci/ac97/ac97_codec.c change |= snd_ac97_update_bits_nolock(ac97, AC97_CSR_SPDIF, 0x3fff, ((val & 0xcfff) | (x << 12))); val 787 sound/pci/ac97/ac97_codec.c ((val << 4) & 0xff00) | val 788 sound/pci/ac97/ac97_codec.c ((val << 2) & 0x0038)); val 793 sound/pci/ac97/ac97_codec.c change |= snd_ac97_update_bits_nolock(ac97, AC97_SPDIF, 0x3fff, val); val 910 sound/pci/ac97/ac97_codec.c unsigned short val, valmask; val 912 sound/pci/ac97/ac97_codec.c val = (mask - (ucontrol->value.integer.value[0] & mask)) << lshift; val 915 sound/pci/ac97/ac97_codec.c val |= (mask - (ucontrol->value.integer.value[1] & mask)) << rshift; val 918 sound/pci/ac97/ac97_codec.c return snd_ac97_ad18xx_update_pcm_bits(ac97, codec, valmask, val); val 1027 sound/pci/ac97/ac97_codec.c unsigned short val, mask = AC97_MUTE_MASK_MONO; val 1041 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); val 1043 sound/pci/ac97/ac97_codec.c return val == 0; val 1062 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); val 1063 sound/pci/ac97/ac97_codec.c if (!(val & mask)) { val 1066 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, val | mask); val 1067 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); val 1068 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); val 1069 sound/pci/ac97/ac97_codec.c if (!(val & mask)) val 1095 sound/pci/ac97/ac97_codec.c unsigned short val; val 1104 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); val 1105 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); val 1106 sound/pci/ac97/ac97_codec.c if (! *lo_max && (val & 0x7f) == cbit[i]) val 1108 sound/pci/ac97/ac97_codec.c if (! *hi_max && ((val >> 8) & 0x7f) == cbit[i]) val 1117 sound/pci/ac97/ac97_codec.c unsigned short mask, val, orig, res; val 1121 sound/pci/ac97/ac97_codec.c val = orig ^ mask; val 1122 sound/pci/ac97/ac97_codec.c snd_ac97_write(ac97, reg, val); val 1125 sound/pci/ac97/ac97_codec.c return res == val; val 1131 sound/pci/ac97/ac97_codec.c unsigned short val, val1; val 1134 sound/pci/ac97/ac97_codec.c val = AC97_MUTE_MASK_STEREO | (0x20 << shift); val 1135 sound/pci/ac97/ac97_codec.c snd_ac97_write(ac97, reg, val); val 1137 sound/pci/ac97/ac97_codec.c if (val != val1) { val 1173 sound/pci/ac97/ac97_codec.c unsigned short val, val1, mute_mask; val 1179 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); val 1182 sound/pci/ac97/ac97_codec.c val1 = val | AC97_MUTE_MASK_STEREO; val 1204 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, val | mute_mask); val 1590 sound/pci/ac97/ac97_codec.c unsigned short val; val 1591 sound/pci/ac97/ac97_codec.c val = 0x0707; val 1592 sound/pci/ac97/ac97_codec.c snd_ac97_write(ac97, AC97_3D_CONTROL, val); val 1593 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, AC97_3D_CONTROL); val 1594 sound/pci/ac97/ac97_codec.c val = val == 0x0606; val 1597 sound/pci/ac97/ac97_codec.c if (val) val 1601 sound/pci/ac97/ac97_codec.c if (val) val 1681 sound/pci/ac97/ac97_codec.c unsigned short val; val 1688 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); val 1689 sound/pci/ac97/ac97_codec.c return val == (tmp & 0xffff); val 1841 sound/pci/ac97/ac97_codec.c unsigned short val; val 1852 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, AC97_EXTENDED_MID); val 1853 sound/pci/ac97/ac97_codec.c if (val != 0xffff && (val & 1) != 0) val 1858 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, AC97_VENDOR_ID1); val 1859 sound/pci/ac97/ac97_codec.c if (val != 0 && val != 0xffff) val 2562 sound/pci/ac97/ac97_codec.c unsigned short val = snd_ac97_read(ac97, AC97_EXTENDED_MID); val 2563 sound/pci/ac97/ac97_codec.c if (val != 0xffff && (val & 1) != 0) val 229 sound/pci/ac97/ac97_patch.c unsigned short val; val 231 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_YMF7X3_3D_MODE_SEL]; val 232 sound/pci/ac97/ac97_patch.c val = (val >> 10) & 3; val 233 sound/pci/ac97/ac97_patch.c if (val > 0) /* 0 = invalid */ val 234 sound/pci/ac97/ac97_patch.c val--; val 235 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = val; val 243 sound/pci/ac97/ac97_patch.c unsigned short val; val 247 sound/pci/ac97/ac97_patch.c val = (ucontrol->value.enumerated.item[0] + 1) << 10; val 248 sound/pci/ac97/ac97_patch.c return snd_ac97_update(ac97, AC97_YMF7X3_3D_MODE_SEL, val); val 274 sound/pci/ac97/ac97_patch.c unsigned short val; val 276 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_YMF7X3_DIT_CTRL]; val 277 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = (val >> 1) & 1; val 285 sound/pci/ac97/ac97_patch.c unsigned short val; val 289 sound/pci/ac97/ac97_patch.c val = ucontrol->value.enumerated.item[0] << 1; val 290 sound/pci/ac97/ac97_patch.c return snd_ac97_update_bits(ac97, AC97_YMF7X3_DIT_CTRL, 0x0002, val); val 375 sound/pci/ac97/ac97_patch.c unsigned short val; val 377 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_YMF7X3_DIT_CTRL]; val 378 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = (val & 0x0008) ? 2 : (val & 0x0020) ? 1 : 0; val 385 sound/pci/ac97/ac97_patch.c unsigned short val; val 389 sound/pci/ac97/ac97_patch.c val = (ucontrol->value.enumerated.item[0] == 2) ? 0x0008 : val 391 sound/pci/ac97/ac97_patch.c return snd_ac97_update_bits(ac97, AC97_YMF7X3_DIT_CTRL, 0x0028, val); val 1074 sound/pci/ac97/ac97_patch.c unsigned short val; val 1076 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_SIGMATEL_OUTSEL] >> shift; val 1077 sound/pci/ac97/ac97_patch.c if (!(val & 4)) val 1080 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = 1 + (val & 3); val 1088 sound/pci/ac97/ac97_patch.c unsigned short val; val 1093 sound/pci/ac97/ac97_patch.c val = 0; val 1095 sound/pci/ac97/ac97_patch.c val = 4 | (ucontrol->value.enumerated.item[0] - 1); val 1097 sound/pci/ac97/ac97_patch.c 7 << shift, val << shift, 0); val 1113 sound/pci/ac97/ac97_patch.c unsigned short val; val 1115 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_SIGMATEL_INSEL]; val 1116 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = (val >> shift) & 7; val 1457 sound/pci/ac97/ac97_patch.c unsigned short val; val 1462 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_VENDOR_ID2); val 1463 sound/pci/ac97/ac97_patch.c if ((val & 0xff40) != 0x5340) val 1466 sound/pci/ac97/ac97_patch.c ac97->spec.ad18xx.id[idx] = val; val 1474 sound/pci/ac97/ac97_patch.c unsigned short val; val 1478 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_VENDOR_ID2); val 1479 sound/pci/ac97/ac97_patch.c if ((val & 0xff40) != 0x5340) val 1484 sound/pci/ac97/ac97_patch.c ac97->spec.ad18xx.id[idx] = val; val 1531 sound/pci/ac97/ac97_patch.c unsigned short val; val 1534 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_AD_SERIAL_CFG); val 1535 sound/pci/ac97/ac97_patch.c snd_ac97_write_cache(ac97, AC97_AD_SERIAL_CFG, val); val 1758 sound/pci/ac97/ac97_patch.c unsigned short val; val 1760 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_AD_SERIAL_CFG]; val 1761 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = (val >> 2) & 1; val 1768 sound/pci/ac97/ac97_patch.c unsigned short val; val 1772 sound/pci/ac97/ac97_patch.c val = ucontrol->value.enumerated.item[0] << 2; val 1773 sound/pci/ac97/ac97_patch.c return snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x0004, val); val 1909 sound/pci/ac97/ac97_patch.c unsigned short val; val 1911 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_AD_MISC]; val 1912 sound/pci/ac97/ac97_patch.c ucontrol->value.integer.value[0] = !(val & AC97_AD198X_LOSEL); val 1922 sound/pci/ac97/ac97_patch.c unsigned short val; val 1924 sound/pci/ac97/ac97_patch.c val = !ucontrol->value.integer.value[0]; val 1926 sound/pci/ac97/ac97_patch.c val = !val; val 1927 sound/pci/ac97/ac97_patch.c val = val ? (AC97_AD198X_LOSEL | AC97_AD198X_HPSEL) : 0; val 1929 sound/pci/ac97/ac97_patch.c AC97_AD198X_LOSEL | AC97_AD198X_HPSEL, val); val 1942 sound/pci/ac97/ac97_patch.c unsigned short val; val 1944 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_AD_MISC]; val 1945 sound/pci/ac97/ac97_patch.c if (!(val & AC97_AD198X_DMIX1)) val 1948 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = 1 + ((val >> 8) & 1); val 1955 sound/pci/ac97/ac97_patch.c unsigned short val; val 1960 sound/pci/ac97/ac97_patch.c val = 0; val 1962 sound/pci/ac97/ac97_patch.c val = AC97_AD198X_DMIX1 | val 1965 sound/pci/ac97/ac97_patch.c AC97_AD198X_DMIX0 | AC97_AD198X_DMIX1, val); val 1970 sound/pci/ac97/ac97_patch.c unsigned short val = 0; val 1973 sound/pci/ac97/ac97_patch.c val |= (1 << 12); val 1976 sound/pci/ac97/ac97_patch.c val |= (1 << 11); val 1978 sound/pci/ac97/ac97_patch.c snd_ac97_update_bits(ac97, AC97_AD_MISC, (1 << 11) | (1 << 12), val); val 2099 sound/pci/ac97/ac97_patch.c unsigned short val; val 2100 sound/pci/ac97/ac97_patch.c val = (ac97->regs[AC97_AD_MISC] & AC97_AD198X_VREF_MASK) val 2102 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = reg2ctrl[val]; val 2111 sound/pci/ac97/ac97_patch.c unsigned short val; val 2115 sound/pci/ac97/ac97_patch.c val = ctrl2reg[ucontrol->value.enumerated.item[0]] val 2118 sound/pci/ac97/ac97_patch.c AC97_AD198X_VREF_MASK, val); val 2218 sound/pci/ac97/ac97_patch.c unsigned short val; val 2220 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_AD_MISC3]; val 2221 sound/pci/ac97/ac97_patch.c ucontrol->value.integer.value[0] = (val & AC97_AD1986_LOSEL) != 0; val 2254 sound/pci/ac97/ac97_patch.c unsigned short val; val 2256 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_AD_MISC]; val 2257 sound/pci/ac97/ac97_patch.c ucontrol->value.integer.value[0] = (val & AC97_AD1986_SPRD) != 0; val 2315 sound/pci/ac97/ac97_patch.c unsigned short val; val 2318 sound/pci/ac97/ac97_patch.c val = 2; val 2320 sound/pci/ac97/ac97_patch.c val = 3; val 2322 sound/pci/ac97/ac97_patch.c val = 1; val 2324 sound/pci/ac97/ac97_patch.c val = 0; val 2325 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = val; val 2604 sound/pci/ac97/ac97_patch.c unsigned short val; val 2609 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_ALC650_REVISION) & 0x3f; val 2610 sound/pci/ac97/ac97_patch.c if (val < 3) val 2612 sound/pci/ac97/ac97_patch.c else if (val < 0x10) val 2614 sound/pci/ac97/ac97_patch.c else if (val < 0x20) val 2616 sound/pci/ac97/ac97_patch.c else if (val < 0x30) val 2629 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_ALC650_CLOCK); val 2635 sound/pci/ac97/ac97_patch.c val |= 0x03; /* enable */ val 2637 sound/pci/ac97/ac97_patch.c val &= ~0x03; /* disable */ val 2638 sound/pci/ac97/ac97_patch.c snd_ac97_write_cache(ac97, AC97_ALC650_CLOCK, val); val 2702 sound/pci/ac97/ac97_patch.c unsigned short val; val 2704 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_ALC650_MULTICH]; val 2705 sound/pci/ac97/ac97_patch.c val = (val >> 12) & 3; val 2706 sound/pci/ac97/ac97_patch.c if (ac97->spec.dev_flags && val == 3) val 2707 sound/pci/ac97/ac97_patch.c val = 0; val 2708 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = val; val 2754 sound/pci/ac97/ac97_patch.c unsigned int val; val 2770 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, 0x7a); /* misc control */ val 2772 sound/pci/ac97/ac97_patch.c val &= ~(1 << 1); /* Pin 47 is spdif input pin */ val 2780 sound/pci/ac97/ac97_patch.c val &= ~(1 << 1); /* Pin 47 is EAPD (for internal speaker) */ val 2782 sound/pci/ac97/ac97_patch.c val |= (1 << 1); /* Pin 47 is spdif input pin */ val 2786 sound/pci/ac97/ac97_patch.c val &= ~(1 << 12); /* vref enable */ val 2787 sound/pci/ac97/ac97_patch.c snd_ac97_write_cache(ac97, 0x7a, val); val 2990 sound/pci/ac97/ac97_patch.c unsigned short val; val 2992 sound/pci/ac97/ac97_patch.c val = ac97->regs[AC97_CM9739_SPDIF_CTRL]; val 2993 sound/pci/ac97/ac97_patch.c ucontrol->value.enumerated.item[0] = (val >> 1) & 0x01; val 3057 sound/pci/ac97/ac97_patch.c unsigned short val; val 3067 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_EXTENDED_STATUS); val 3068 sound/pci/ac97/ac97_patch.c if (val & AC97_EA_SPCV) { val 3087 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_CM9739_MULTI_CHAN) & (1 << 4); val 3088 sound/pci/ac97/ac97_patch.c val |= (1 << 3); val 3089 sound/pci/ac97/ac97_patch.c val |= (1 << 13); val 3091 sound/pci/ac97/ac97_patch.c val |= (1 << 14); val 3092 sound/pci/ac97/ac97_patch.c snd_ac97_write_cache(ac97, AC97_CM9739_MULTI_CHAN, val); val 3139 sound/pci/ac97/ac97_patch.c unsigned short val = 0; val 3141 sound/pci/ac97/ac97_patch.c val |= surr_on[ac97->spec.dev_flags][is_surround_on(ac97)]; val 3142 sound/pci/ac97/ac97_patch.c val |= clfe_on[ac97->spec.dev_flags][is_clfe_on(ac97)]; val 3143 sound/pci/ac97/ac97_patch.c val |= surr_shared[ac97->spec.dev_flags][is_shared_surrout(ac97)]; val 3144 sound/pci/ac97/ac97_patch.c val |= clfe_shared[ac97->spec.dev_flags][is_shared_clfeout(ac97)]; val 3146 sound/pci/ac97/ac97_patch.c snd_ac97_update_bits(ac97, AC97_CM9761_MULTI_CHAN, 0x3c88, val); val 3227 sound/pci/ac97/ac97_patch.c unsigned short val; val 3241 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_INT_PAGING); val 3242 sound/pci/ac97/ac97_patch.c snd_ac97_write_cache(ac97, AC97_INT_PAGING, (val & ~0x0f) | 0x01); val 3245 sound/pci/ac97/ac97_patch.c snd_ac97_write_cache(ac97, AC97_INT_PAGING, val); val 3280 sound/pci/ac97/ac97_patch.c val = 0x0214; val 3282 sound/pci/ac97/ac97_patch.c val = 0x321c; val 3284 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_CM9761_MULTI_CHAN); val 3285 sound/pci/ac97/ac97_patch.c val |= (1 << 4); /* front on */ val 3286 sound/pci/ac97/ac97_patch.c snd_ac97_write_cache(ac97, AC97_CM9761_MULTI_CHAN, val); val 3324 sound/pci/ac97/ac97_patch.c unsigned short val; val 3331 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, AC97_CM9780_SPDIF); val 3332 sound/pci/ac97/ac97_patch.c val |= 0x1; /* SPDI_EN */ val 3333 sound/pci/ac97/ac97_patch.c snd_ac97_write_cache(ac97, AC97_CM9780_SPDIF, val); val 3569 sound/pci/ac97/ac97_patch.c int val; val 3583 sound/pci/ac97/ac97_patch.c val = snd_ac97_read(ac97, 0x5c); val 3584 sound/pci/ac97/ac97_patch.c if (!(val & 0x20)) val 95 sound/pci/ac97/ac97_proc.c unsigned short val, tmp, ext, mext; val 115 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_INT_PAGING); val 126 sound/pci/ac97/ac97_proc.c AC97_PAGE_MASK, val & AC97_PAGE_MASK); val 130 sound/pci/ac97/ac97_proc.c val = ac97->caps; val 132 sound/pci/ac97/ac97_proc.c val & AC97_BC_DEDICATED_MIC ? " -dedicated MIC PCM IN channel-" : "", val 133 sound/pci/ac97/ac97_proc.c val & AC97_BC_RESERVED1 ? " -reserved1-" : "", val 134 sound/pci/ac97/ac97_proc.c val & AC97_BC_BASS_TREBLE ? " -bass & treble-" : "", val 135 sound/pci/ac97/ac97_proc.c val & AC97_BC_SIM_STEREO ? " -simulated stereo-" : "", val 136 sound/pci/ac97/ac97_proc.c val & AC97_BC_HEADPHONE ? " -headphone out-" : "", val 137 sound/pci/ac97/ac97_proc.c val & AC97_BC_LOUDNESS ? " -loudness-" : ""); val 151 sound/pci/ac97/ac97_proc.c snd_ac97_stereo_enhancements[(val >> 10) & 0x1f]); val 153 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_MIC); val 154 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "Mic gain : %s [%s]\n", val & 0x0040 ? "+20dB" : "+0dB", ac97->regs[AC97_MIC] & 0x0040 ? "+20dB" : "+0dB"); val 155 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_GENERAL_PURPOSE); val 163 sound/pci/ac97/ac97_proc.c val & 0x8000 ? "post" : "pre", val 164 sound/pci/ac97/ac97_proc.c val & 0x4000 ? "on" : "off", val 165 sound/pci/ac97/ac97_proc.c val & 0x2000 ? "on" : "off", val 166 sound/pci/ac97/ac97_proc.c val & 0x1000 ? "on" : "off", val 167 sound/pci/ac97/ac97_proc.c val & 0x0200 ? "Mic" : "MIX", val 168 sound/pci/ac97/ac97_proc.c val & 0x0100 ? "Mic2" : "Mic1", val 169 sound/pci/ac97/ac97_proc.c val & 0x0080 ? "on" : "off"); val 172 sound/pci/ac97/ac97_proc.c double_rate_slots[(val >> 10) & 3]); val 190 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_EXTENDED_STATUS); val 192 sound/pci/ac97/ac97_proc.c val & AC97_EA_PRL ? " PRL" : "", val 193 sound/pci/ac97/ac97_proc.c val & AC97_EA_PRK ? " PRK" : "", val 194 sound/pci/ac97/ac97_proc.c val & AC97_EA_PRJ ? " PRJ" : "", val 195 sound/pci/ac97/ac97_proc.c val & AC97_EA_PRI ? " PRI" : "", val 196 sound/pci/ac97/ac97_proc.c val & AC97_EA_SPCV ? " SPCV" : "", val 197 sound/pci/ac97/ac97_proc.c val & AC97_EA_MDAC ? " MADC" : "", val 198 sound/pci/ac97/ac97_proc.c val & AC97_EA_LDAC ? " LDAC" : "", val 199 sound/pci/ac97/ac97_proc.c val & AC97_EA_SDAC ? " SDAC" : "", val 200 sound/pci/ac97/ac97_proc.c val & AC97_EA_CDAC ? " CDAC" : "", val 201 sound/pci/ac97/ac97_proc.c ext & AC97_EI_SPDIF ? spdif_slots[(val & AC97_EA_SPSA_SLOT_MASK) >> AC97_EA_SPSA_SLOT_SHIFT] : "", val 202 sound/pci/ac97/ac97_proc.c val & AC97_EA_VRM ? " VRM" : "", val 203 sound/pci/ac97/ac97_proc.c val & AC97_EA_SPDIF ? " SPDIF" : "", val 204 sound/pci/ac97/ac97_proc.c val & AC97_EA_DRA ? " DRA" : "", val 205 sound/pci/ac97/ac97_proc.c val & AC97_EA_VRA ? " VRA" : ""); val 207 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_PCM_FRONT_DAC_RATE); val 208 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "PCM front DAC : %iHz\n", val); val 210 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_PCM_SURR_DAC_RATE); val 211 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "PCM Surr DAC : %iHz\n", val); val 214 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_PCM_LFE_DAC_RATE); val 215 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "PCM LFE DAC : %iHz\n", val); val 217 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_PCM_LR_ADC_RATE); val 218 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "PCM ADC : %iHz\n", val); val 221 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_PCM_MIC_ADC_RATE); val 222 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "PCM MIC ADC : %iHz\n", val); val 227 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_CSR_SPDIF); val 229 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_YMF7X3_DIT_CTRL); val 230 sound/pci/ac97/ac97_proc.c val = 0x2000 | (val & 0xff00) >> 4 | (val & 0x38) >> 2; val 232 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_SPDIF); val 235 sound/pci/ac97/ac97_proc.c val & AC97_SC_PRO ? " PRO" : " Consumer", val 236 sound/pci/ac97/ac97_proc.c val & AC97_SC_NAUDIO ? " Non-audio" : " PCM", val 237 sound/pci/ac97/ac97_proc.c val & AC97_SC_COPY ? "" : " Copyright", val 238 sound/pci/ac97/ac97_proc.c val & AC97_SC_PRE ? " Preemph50/15" : "", val 239 sound/pci/ac97/ac97_proc.c (val & AC97_SC_CC_MASK) >> AC97_SC_CC_SHIFT, val 240 sound/pci/ac97/ac97_proc.c (val & AC97_SC_L) >> 11, val 242 sound/pci/ac97/ac97_proc.c spdif_rates_cs4205[(val & AC97_SC_SPSR_MASK) >> AC97_SC_SPSR_SHIFT] : val 243 sound/pci/ac97/ac97_proc.c spdif_rates[(val & AC97_SC_SPSR_MASK) >> AC97_SC_SPSR_SHIFT], val 245 sound/pci/ac97/ac97_proc.c (val & AC97_SC_DRS ? " Validity" : "") : val 246 sound/pci/ac97/ac97_proc.c (val & AC97_SC_DRS ? " DRS" : ""), val 248 sound/pci/ac97/ac97_proc.c (val & AC97_SC_V ? " Enabled" : "") : val 249 sound/pci/ac97/ac97_proc.c (val & AC97_SC_V ? " Validity" : "")); val 253 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS2); val 254 sound/pci/ac97/ac97_proc.c if (val & AC97_ALC650_CLOCK_LOCK) { val 255 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS1); val 257 sound/pci/ac97/ac97_proc.c val & AC97_ALC650_PRO ? " PRO" : " Consumer", val 258 sound/pci/ac97/ac97_proc.c val & AC97_ALC650_NAUDIO ? " Non-audio" : " PCM", val 259 sound/pci/ac97/ac97_proc.c val & AC97_ALC650_COPY ? "" : " Copyright", val 260 sound/pci/ac97/ac97_proc.c val & AC97_ALC650_PRE ? " Preemph50/15" : "", val 261 sound/pci/ac97/ac97_proc.c (val & AC97_ALC650_CC_MASK) >> AC97_ALC650_CC_SHIFT, val 262 sound/pci/ac97/ac97_proc.c (val & AC97_ALC650_L) >> 15); val 263 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS2); val 265 sound/pci/ac97/ac97_proc.c spdif_rates[(val & AC97_ALC650_SPSR_MASK) >> AC97_ALC650_SPSR_SHIFT], val 266 sound/pci/ac97/ac97_proc.c (val & AC97_ALC650_CLOCK_ACCURACY) >> AC97_ALC650_CLOCK_SHIFT, val 267 sound/pci/ac97/ac97_proc.c (val & AC97_ALC650_CLOCK_LOCK ? " Locked" : " Unlocked"), val 268 sound/pci/ac97/ac97_proc.c (val & AC97_ALC650_V ? " Validity?" : "")); val 275 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_INT_PAGING); val 280 sound/pci/ac97/ac97_proc.c AC97_PAGE_MASK, val & AC97_PAGE_MASK); val 296 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_EXTENDED_MSTATUS); val 298 sound/pci/ac97/ac97_proc.c val & AC97_MEA_GPIO ? " GPIO" : "", val 299 sound/pci/ac97/ac97_proc.c val & AC97_MEA_MREF ? " MREF" : "", val 300 sound/pci/ac97/ac97_proc.c val & AC97_MEA_ADC1 ? " ADC1" : "", val 301 sound/pci/ac97/ac97_proc.c val & AC97_MEA_DAC1 ? " DAC1" : "", val 302 sound/pci/ac97/ac97_proc.c val & AC97_MEA_ADC2 ? " ADC2" : "", val 303 sound/pci/ac97/ac97_proc.c val & AC97_MEA_DAC2 ? " DAC2" : "", val 304 sound/pci/ac97/ac97_proc.c val & AC97_MEA_HADC ? " HADC" : "", val 305 sound/pci/ac97/ac97_proc.c val & AC97_MEA_HDAC ? " HDAC" : "", val 306 sound/pci/ac97/ac97_proc.c val & AC97_MEA_PRA ? " PRA(GPIO)" : "", val 307 sound/pci/ac97/ac97_proc.c val & AC97_MEA_PRB ? " PRB(res)" : "", val 308 sound/pci/ac97/ac97_proc.c val & AC97_MEA_PRC ? " PRC(ADC1)" : "", val 309 sound/pci/ac97/ac97_proc.c val & AC97_MEA_PRD ? " PRD(DAC1)" : "", val 310 sound/pci/ac97/ac97_proc.c val & AC97_MEA_PRE ? " PRE(ADC2)" : "", val 311 sound/pci/ac97/ac97_proc.c val & AC97_MEA_PRF ? " PRF(DAC2)" : "", val 312 sound/pci/ac97/ac97_proc.c val & AC97_MEA_PRG ? " PRG(HADC)" : "", val 313 sound/pci/ac97/ac97_proc.c val & AC97_MEA_PRH ? " PRH(HDAC)" : ""); val 315 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_LINE1_RATE); val 316 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "Line1 rate : %iHz\n", val); val 319 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_LINE2_RATE); val 320 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "Line2 rate : %iHz\n", val); val 323 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, AC97_HANDSET_RATE); val 324 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "Headset rate : %iHz\n", val); val 367 sound/pci/ac97/ac97_proc.c unsigned int reg, val; val 370 sound/pci/ac97/ac97_proc.c if (sscanf(line, "%x %x", ®, &val) != 2) val 373 sound/pci/ac97/ac97_proc.c if (reg < 0x80 && (reg & 1) == 0 && val <= 0xffff) val 374 sound/pci/ac97/ac97_proc.c snd_ac97_write_cache(ac97, reg, val); val 382 sound/pci/ac97/ac97_proc.c int reg, val; val 385 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, reg); val 386 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "%i:%02x = %04x\n", subidx, reg, val); val 104 sound/pci/ad1889.c ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val) val 106 sound/pci/ad1889.c writew(val, chip->iobase + reg); val 116 sound/pci/ad1889.c ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val) val 118 sound/pci/ad1889.c writel(val, chip->iobase + reg); val 236 sound/pci/ad1889.c snd_ad1889_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) val 239 sound/pci/ad1889.c ad1889_writew(chip, AD_AC97_BASE + reg, val); val 78 sound/pci/ak4531_codec.c int val; val 81 sound/pci/ak4531_codec.c val = (ak4531->regs[reg] >> shift) & mask; val 84 sound/pci/ak4531_codec.c val = mask - val; val 86 sound/pci/ak4531_codec.c ucontrol->value.integer.value[0] = val; val 98 sound/pci/ak4531_codec.c int val; val 100 sound/pci/ak4531_codec.c val = ucontrol->value.integer.value[0] & mask; val 102 sound/pci/ak4531_codec.c val = mask - val; val 104 sound/pci/ak4531_codec.c val <<= shift; val 106 sound/pci/ak4531_codec.c val = (ak4531->regs[reg] & ~(mask << shift)) | val; val 107 sound/pci/ak4531_codec.c change = val != ak4531->regs[reg]; val 108 sound/pci/ak4531_codec.c ak4531->write(ak4531, reg, ak4531->regs[reg] = val); val 275 sound/pci/ali5451/ali5451.c unsigned int val) val 277 sound/pci/ali5451/ali5451.c outl((unsigned int)val, ALI_REG(codec, port)); val 325 sound/pci/ali5451/ali5451.c unsigned short val) val 344 sound/pci/ali5451/ali5451.c dwVal |= 0x8000 | (val << 16); val 392 sound/pci/ali5451/ali5451.c unsigned short val ) val 396 sound/pci/ali5451/ali5451.c dev_dbg(codec->card->dev, "codec_write: reg=%xh data=%xh.\n", reg, val); val 398 sound/pci/ali5451/ali5451.c outl((val << ALI_AC97_GPIO_DATA_SHIFT) | ALI_AC97_GPIO_ENABLE, val 402 sound/pci/ali5451/ali5451.c snd_ali_codec_poke(codec, ac97->num, reg, val); val 1075 sound/pci/ali5451/ali5451.c unsigned int val; val 1120 sound/pci/ali5451/ali5451.c val = inl(ALI_REG(codec, ALI_AINTEN)); val 1122 sound/pci/ali5451/ali5451.c val |= whati; val 1124 sound/pci/ali5451/ali5451.c val &= ~whati; val 1125 sound/pci/ali5451/ali5451.c outl(val, ALI_REG(codec, ALI_AINTEN)); val 145 sound/pci/als300.c unsigned short reg, u32 val) val 148 sound/pci/als300.c outl(val, port+GCR_DATA); val 279 sound/pci/als300.c unsigned short reg, unsigned short val) val 289 sound/pci/als300.c outl((reg << 24) | val, chip->port+AC97_ACCESS); val 179 sound/pci/als4000.c u8 val) val 181 sound/pci/als4000.c outb(val, iobase + reg); val 186 sound/pci/als4000.c u32 val) val 188 sound/pci/als4000.c outl(val, iobase + reg); val 205 sound/pci/als4000.c u32 val) val 208 sound/pci/als4000.c snd_als4k_iobase_writel(iobase, ALS4K_IOD_08_GCR_DATA, val); val 213 sound/pci/als4000.c u32 val) val 215 sound/pci/als4000.c snd_als4k_gcr_write_addr(sb->alt_port, reg, val); val 320 sound/pci/atiixp.c #define atiixp_update(chip,reg,mask,val) \ val 321 sound/pci/atiixp.c snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) val 458 sound/pci/atiixp.c unsigned short reg, unsigned short val) val 464 sound/pci/atiixp.c data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | val 480 sound/pci/atiixp.c unsigned short val) val 483 sound/pci/atiixp.c snd_atiixp_codec_write(chip, ac97->num, reg, val); val 288 sound/pci/atiixp_modem.c #define atiixp_update(chip,reg,mask,val) \ val 289 sound/pci/atiixp_modem.c snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) val 429 sound/pci/atiixp_modem.c unsigned short reg, unsigned short val) val 435 sound/pci/atiixp_modem.c data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | val 451 sound/pci/atiixp_modem.c unsigned short val) val 456 sound/pci/atiixp_modem.c (val << ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT) | ATI_REG_MODEM_OUT_GPIO_EN); val 459 sound/pci/atiixp_modem.c snd_atiixp_codec_write(chip, ac97->num, reg, val); val 23 sound/pci/au88x0/au88x0_synth.c u32 val); val 159 sound/pci/au88x0/au88x0_synth.c u16 val) val 183 sound/pci/au88x0/au88x0_synth.c u32 val) val 211 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_RUN(wt), val); val 218 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_PARM(wt, 0), val); val 225 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_PARM(wt, 1), val); val 232 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_PARM(wt, 2), val); val 239 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_PARM(wt, 3), val); val 246 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_MUTE(wt), val); val 254 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_DELAY(wt, 3), val); val 255 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_DELAY(wt, 2), val); val 256 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_DELAY(wt, 1), val); val 257 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, WT_DELAY(wt, 0), val); val 281 sound/pci/au88x0/au88x0_synth.c hwwrite(vortex->mmio, ecx, val); val 711 sound/pci/azt3328.c unsigned short reg_ac97, unsigned short val) val 719 sound/pci/azt3328.c reg_ac97, val); val 727 sound/pci/azt3328.c val val 869 sound/pci/azt3328.c static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val) val 871 sound/pci/azt3328.c r->reg = val & 0xff; val 872 sound/pci/azt3328.c r->lchan_shift = (val >> 8) & 0x0f; val 873 sound/pci/azt3328.c r->rchan_shift = (val >> 12) & 0x0f; val 874 sound/pci/azt3328.c r->mask = (val >> 16) & 0xff; val 875 sound/pci/azt3328.c r->invert = (val >> 24) & 1; val 876 sound/pci/azt3328.c r->stereo = (val >> 25) & 1; val 877 sound/pci/azt3328.c r->enum_c = (val >> 26) & 0x0f; val 940 sound/pci/azt3328.c u16 oreg, val; val 945 sound/pci/azt3328.c val = (oreg >> reg.lchan_shift) & reg.mask; val 947 sound/pci/azt3328.c val = reg.mask - val; val 948 sound/pci/azt3328.c ucontrol->value.integer.value[0] = val; val 950 sound/pci/azt3328.c val = (oreg >> reg.rchan_shift) & reg.mask; val 952 sound/pci/azt3328.c val = reg.mask - val; val 953 sound/pci/azt3328.c ucontrol->value.integer.value[1] = val; val 969 sound/pci/azt3328.c u16 oreg, nreg, val; val 973 sound/pci/azt3328.c val = ucontrol->value.integer.value[0] & reg.mask; val 975 sound/pci/azt3328.c val = reg.mask - val; val 977 sound/pci/azt3328.c nreg |= (val << reg.lchan_shift); val 979 sound/pci/azt3328.c val = ucontrol->value.integer.value[1] & reg.mask; val 981 sound/pci/azt3328.c val = reg.mask - val; val 983 sound/pci/azt3328.c nreg |= (val << reg.rchan_shift); val 1049 sound/pci/azt3328.c unsigned short val; val 1052 sound/pci/azt3328.c val = snd_azf3328_mixer_inw(chip, reg.reg); val 1054 sound/pci/azt3328.c ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); val 1055 sound/pci/azt3328.c ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); val 1057 sound/pci/azt3328.c ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); val 1061 sound/pci/azt3328.c reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], val 1072 sound/pci/azt3328.c u16 oreg, nreg, val; val 1076 sound/pci/azt3328.c val = oreg; val 1081 sound/pci/azt3328.c val = (ucontrol->value.enumerated.item[0] << 8) | val 1086 sound/pci/azt3328.c val &= ~((reg.enum_c - 1) << reg.lchan_shift); val 1087 sound/pci/azt3328.c val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); val 1089 sound/pci/azt3328.c snd_azf3328_mixer_outw(chip, reg.reg, val); val 1090 sound/pci/azt3328.c nreg = val; val 1093 sound/pci/azt3328.c "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); val 1230 sound/pci/azt3328.c u16 val = 0xff00; val 1264 sound/pci/azt3328.c val |= freq; val 1267 sound/pci/azt3328.c val |= SOUNDFORMAT_FLAG_2CHANNELS; val 1270 sound/pci/azt3328.c val |= SOUNDFORMAT_FLAG_16BIT; val 1275 sound/pci/azt3328.c snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val); val 1751 sound/pci/azt3328.c u8 val; val 1758 sound/pci/azt3328.c val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE); val 1759 sound/pci/azt3328.c *buttons = (~(val) >> 4) & 0xf; val 1771 sound/pci/azt3328.c val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG); val 1772 sound/pci/azt3328.c if (val & GAME_AXES_SAMPLING_READY) { val 1775 sound/pci/azt3328.c val = (i << 4) | 0x0f; val 1776 sound/pci/azt3328.c snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); val 1790 sound/pci/azt3328.c val = 0x03; /* we're able to monitor axes 1 and 2 only */ val 1791 sound/pci/azt3328.c snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); val 2305 sound/pci/azt3328.c unsigned char val, valoff, valon; val 2307 sound/pci/azt3328.c val = inb(reg); val 2309 sound/pci/azt3328.c outb(val & ~(1 << bit), reg); val 2312 sound/pci/azt3328.c outb(val|(1 << bit), reg); val 2315 sound/pci/azt3328.c outb(val, reg); val 2318 sound/pci/azt3328.c reg, bit, val, valoff, valon val 337 sound/pci/ca0106/ca0106_main.c unsigned int regptr, val; val 343 sound/pci/ca0106/ca0106_main.c val = inl(emu->port + DATA); val 345 sound/pci/ca0106/ca0106_main.c return val; val 1190 sound/pci/ca0106/ca0106_main.c unsigned short val; val 1194 sound/pci/ca0106/ca0106_main.c val = inw(emu->port + AC97DATA); val 1196 sound/pci/ca0106/ca0106_main.c return val; val 1200 sound/pci/ca0106/ca0106_main.c unsigned short reg, unsigned short val) val 1207 sound/pci/ca0106/ca0106_main.c outw(val, emu->port + AC97DATA); val 65 sound/pci/ca0106/ca0106_mixer.c unsigned int val; val 71 sound/pci/ca0106/ca0106_mixer.c val = snd_ca0106_ptr_read(emu, CAPTURE_CONTROL, 0) & ~0x1000; val 72 sound/pci/ca0106/ca0106_mixer.c snd_ca0106_ptr_write(emu, CAPTURE_CONTROL, 0, val); val 73 sound/pci/ca0106/ca0106_mixer.c val = inl(emu->port + GPIO) & ~0x101; val 74 sound/pci/ca0106/ca0106_mixer.c outl(val, emu->port + GPIO); val 80 sound/pci/ca0106/ca0106_mixer.c val = snd_ca0106_ptr_read(emu, CAPTURE_CONTROL, 0) | 0x1000; val 81 sound/pci/ca0106/ca0106_mixer.c snd_ca0106_ptr_write(emu, CAPTURE_CONTROL, 0, val); val 82 sound/pci/ca0106/ca0106_mixer.c val = inl(emu->port + GPIO) | 0x101; val 83 sound/pci/ca0106/ca0106_mixer.c outl(val, emu->port + GPIO); val 89 sound/pci/ca0106/ca0106_mixer.c unsigned int val = emu->capture_source; val 91 sound/pci/ca0106/ca0106_mixer.c source = (val << 28) | (val << 24) | (val << 20) | (val << 16); val 97 sound/pci/ca0106/ca0106_mixer.c unsigned int val, int force) val 103 sound/pci/ca0106/ca0106_mixer.c ngain = emu->i2c_capture_volume[val][0]; /* Left */ val 107 sound/pci/ca0106/ca0106_mixer.c ngain = emu->i2c_capture_volume[val][1]; /* Right */ val 111 sound/pci/ca0106/ca0106_mixer.c source = 1 << val; val 113 sound/pci/ca0106/ca0106_mixer.c emu->i2c_capture_source = val; val 159 sound/pci/ca0106/ca0106_mixer.c unsigned int val; val 162 sound/pci/ca0106/ca0106_mixer.c val = !!ucontrol->value.integer.value[0]; val 163 sound/pci/ca0106/ca0106_mixer.c change = (emu->spdif_enable != val); val 165 sound/pci/ca0106/ca0106_mixer.c emu->spdif_enable = val; val 194 sound/pci/ca0106/ca0106_mixer.c unsigned int val; val 197 sound/pci/ca0106/ca0106_mixer.c val = ucontrol->value.enumerated.item[0] ; val 198 sound/pci/ca0106/ca0106_mixer.c if (val >= 6) val 200 sound/pci/ca0106/ca0106_mixer.c change = (emu->capture_source != val); val 202 sound/pci/ca0106/ca0106_mixer.c emu->capture_source = val; val 276 sound/pci/ca0106/ca0106_mixer.c unsigned int val; val 279 sound/pci/ca0106/ca0106_mixer.c val = ucontrol->value.enumerated.item[0] ; val 280 sound/pci/ca0106/ca0106_mixer.c if (val > 1) val 282 sound/pci/ca0106/ca0106_mixer.c change = (emu->capture_mic_line_in != val); val 284 sound/pci/ca0106/ca0106_mixer.c emu->capture_mic_line_in = val; val 370 sound/pci/ca0106/ca0106_mixer.c unsigned int val; val 372 sound/pci/ca0106/ca0106_mixer.c val = encode_spdif_bits(ucontrol->value.iec958.status); val 373 sound/pci/ca0106/ca0106_mixer.c if (val != emu->spdif_bits[idx]) { val 374 sound/pci/ca0106/ca0106_mixer.c emu->spdif_bits[idx] = val; val 378 sound/pci/ca0106/ca0106_mixer.c emu->spdif_str_bits[idx] = val; val 390 sound/pci/ca0106/ca0106_mixer.c unsigned int val; val 392 sound/pci/ca0106/ca0106_mixer.c val = encode_spdif_bits(ucontrol->value.iec958.status); val 393 sound/pci/ca0106/ca0106_mixer.c if (val != emu->spdif_str_bits[idx]) { val 394 sound/pci/ca0106/ca0106_mixer.c emu->spdif_str_bits[idx] = val; val 65 sound/pci/ca0106/ca0106_proc.c int val; val 131 sound/pci/ca0106/ca0106_proc.c if ((status[1] & IEC958_AES1_CON_CATEGORY) == snd_ca0106_con_category[i].val) { val 286 sound/pci/ca0106/ca0106_proc.c u32 reg, val; val 288 sound/pci/ca0106/ca0106_proc.c if (sscanf(line, "%x %x", ®, &val) != 2) val 290 sound/pci/ca0106/ca0106_proc.c if (reg < 0x40 && val <= 0xffffffff) { val 292 sound/pci/ca0106/ca0106_proc.c outl(val, emu->port + (reg & 0xfffffffc)); val 387 sound/pci/ca0106/ca0106_proc.c unsigned int reg, channel_id , val; val 389 sound/pci/ca0106/ca0106_proc.c if (sscanf(line, "%x %x %x", ®, &channel_id, &val) != 3) val 391 sound/pci/ca0106/ca0106_proc.c if (reg < 0x80 && val <= 0xffffffff && channel_id <= 3) val 392 sound/pci/ca0106/ca0106_proc.c snd_ca0106_ptr_write(emu, reg, channel_id, val); val 401 sound/pci/ca0106/ca0106_proc.c unsigned int reg, val; val 403 sound/pci/ca0106/ca0106_proc.c if (sscanf(line, "%x %x", ®, &val) != 2) val 405 sound/pci/ca0106/ca0106_proc.c if ((reg <= 0x7f) || (val <= 0x1ff)) { val 406 sound/pci/ca0106/ca0106_proc.c snd_ca0106_i2c_write(emu, reg, val); val 537 sound/pci/cmipci.c unsigned int val, oval; val 538 sound/pci/cmipci.c val = oval = inl(cm->iobase + cmd); val 539 sound/pci/cmipci.c val |= flag; val 540 sound/pci/cmipci.c if (val == oval) val 542 sound/pci/cmipci.c outl(val, cm->iobase + cmd); val 548 sound/pci/cmipci.c unsigned int val, oval; val 549 sound/pci/cmipci.c val = oval = inl(cm->iobase + cmd); val 550 sound/pci/cmipci.c val &= ~flag; val 551 sound/pci/cmipci.c if (val == oval) val 553 sound/pci/cmipci.c outl(val, cm->iobase + cmd); val 560 sound/pci/cmipci.c unsigned char val, oval; val 561 sound/pci/cmipci.c val = oval = inb(cm->iobase + cmd); val 562 sound/pci/cmipci.c val |= flag; val 563 sound/pci/cmipci.c if (val == oval) val 565 sound/pci/cmipci.c outb(val, cm->iobase + cmd); val 571 sound/pci/cmipci.c unsigned char val, oval; val 572 sound/pci/cmipci.c val = oval = inb(cm->iobase + cmd); val 573 sound/pci/cmipci.c val &= ~flag; val 574 sound/pci/cmipci.c if (val == oval) val 576 sound/pci/cmipci.c outb(val, cm->iobase + cmd); val 772 sound/pci/cmipci.c unsigned int reg, freq, freq_ext, val; val 811 sound/pci/cmipci.c val = rec->ch ? CM_CHADC1 : CM_CHADC0; val 813 sound/pci/cmipci.c cm->ctrl &= ~val; val 815 sound/pci/cmipci.c cm->ctrl |= val; val 831 sound/pci/cmipci.c val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); val 833 sound/pci/cmipci.c val &= ~CM_DSFC_MASK; val 834 sound/pci/cmipci.c val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; val 836 sound/pci/cmipci.c val &= ~CM_ASFC_MASK; val 837 sound/pci/cmipci.c val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; val 839 sound/pci/cmipci.c snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); val 840 sound/pci/cmipci.c dev_dbg(cm->card->dev, "functrl1 = %08x\n", val); val 843 sound/pci/cmipci.c val = snd_cmipci_read(cm, CM_REG_CHFORMAT); val 845 sound/pci/cmipci.c val &= ~CM_CH1FMT_MASK; val 846 sound/pci/cmipci.c val |= rec->fmt << CM_CH1FMT_SHIFT; val 848 sound/pci/cmipci.c val &= ~CM_CH0FMT_MASK; val 849 sound/pci/cmipci.c val |= rec->fmt << CM_CH0FMT_SHIFT; val 852 sound/pci/cmipci.c val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); val 853 sound/pci/cmipci.c val |= freq_ext << (rec->ch * 2); val 855 sound/pci/cmipci.c snd_cmipci_write(cm, CM_REG_CHFORMAT, val); val 856 sound/pci/cmipci.c dev_dbg(cm->card->dev, "chformat = %08x\n", val); val 1023 sound/pci/cmipci.c unsigned int val; val 1025 sound/pci/cmipci.c val = 0; val 1028 sound/pci/cmipci.c val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); val 1029 sound/pci/cmipci.c change = val != chip->dig_status; val 1030 sound/pci/cmipci.c chip->dig_status = val; val 1097 sound/pci/cmipci.c unsigned int val; val 1099 sound/pci/cmipci.c val = 0; val 1102 sound/pci/cmipci.c val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); val 1103 sound/pci/cmipci.c change = val != chip->dig_pcm_status; val 1104 sound/pci/cmipci.c chip->dig_pcm_status = val; val 1126 sound/pci/cmipci.c struct snd_ctl_elem_value *val; val 1129 sound/pci/cmipci.c val = kmalloc(sizeof(*val), GFP_KERNEL); val 1130 sound/pci/cmipci.c if (!val) val 1136 sound/pci/cmipci.c memset(val, 0, sizeof(*val)); val 1137 sound/pci/cmipci.c ctl->get(ctl, val); val 1138 sound/pci/cmipci.c cm->mixer_res_status[i] = val->value.integer.value[0]; val 1139 sound/pci/cmipci.c val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; val 1141 sound/pci/cmipci.c if (cm->mixer_res_status[i] != val->value.integer.value[0]) { val 1142 sound/pci/cmipci.c ctl->put(ctl, val); /* toggle */ val 1149 sound/pci/cmipci.c kfree(val); val 1160 sound/pci/cmipci.c struct snd_ctl_elem_value *val; val 1163 sound/pci/cmipci.c val = kmalloc(sizeof(*val), GFP_KERNEL); val 1164 sound/pci/cmipci.c if (!val) val 1173 sound/pci/cmipci.c memset(val, 0, sizeof(*val)); val 1175 sound/pci/cmipci.c ctl->get(ctl, val); val 1177 sound/pci/cmipci.c if (val->value.integer.value[0] != cm->mixer_res_status[i]) { val 1178 sound/pci/cmipci.c val->value.integer.value[0] = cm->mixer_res_status[i]; val 1179 sound/pci/cmipci.c ctl->put(ctl, val); val 1185 sound/pci/cmipci.c kfree(val); val 1325 sound/pci/cmipci.c unsigned int reg, val; val 1331 sound/pci/cmipci.c val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16); val 1332 sound/pci/cmipci.c snd_cmipci_write(cm, reg, val); val 1338 sound/pci/cmipci.c val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); val 1339 sound/pci/cmipci.c val &= ~(CM_ASFC_MASK << (rec->ch * 3)); val 1340 sound/pci/cmipci.c val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3); val 1341 sound/pci/cmipci.c snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); val 1342 sound/pci/cmipci.c val = snd_cmipci_read(cm, CM_REG_CHFORMAT); val 1343 sound/pci/cmipci.c val &= ~(CM_CH0FMT_MASK << (rec->ch * 2)); val 1344 sound/pci/cmipci.c val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2); val 1346 sound/pci/cmipci.c val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); val 1347 sound/pci/cmipci.c snd_cmipci_write(cm, CM_REG_CHFORMAT, val); val 1359 sound/pci/cmipci.c val = CM_RST_CH0 << rec->ch; val 1360 sound/pci/cmipci.c snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val); val 1361 sound/pci/cmipci.c snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val); val 2011 sound/pci/cmipci.c static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val) val 2013 sound/pci/cmipci.c r->left_reg = val & 0xff; val 2014 sound/pci/cmipci.c r->right_reg = (val >> 8) & 0xff; val 2015 sound/pci/cmipci.c r->left_shift = (val >> 16) & 0x07; val 2016 sound/pci/cmipci.c r->right_shift = (val >> 19) & 0x07; val 2017 sound/pci/cmipci.c r->invert = (val >> 22) & 1; val 2018 sound/pci/cmipci.c r->stereo = (val >> 23) & 1; val 2019 sound/pci/cmipci.c r->mask = (val >> 24) & 0xff; val 2040 sound/pci/cmipci.c int val; val 2044 sound/pci/cmipci.c val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; val 2046 sound/pci/cmipci.c val = reg.mask - val; val 2047 sound/pci/cmipci.c ucontrol->value.integer.value[0] = val; val 2049 sound/pci/cmipci.c val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; val 2051 sound/pci/cmipci.c val = reg.mask - val; val 2052 sound/pci/cmipci.c ucontrol->value.integer.value[1] = val; val 2212 sound/pci/cmipci.c unsigned char oreg, val; val 2217 sound/pci/cmipci.c val = (oreg >> reg.left_shift) & reg.mask; val 2219 sound/pci/cmipci.c val = reg.mask - val; val 2220 sound/pci/cmipci.c ucontrol->value.integer.value[0] = val; val 2222 sound/pci/cmipci.c val = (oreg >> reg.right_shift) & reg.mask; val 2224 sound/pci/cmipci.c val = reg.mask - val; val 2225 sound/pci/cmipci.c ucontrol->value.integer.value[1] = val; val 2236 sound/pci/cmipci.c unsigned char oreg, nreg, val; val 2241 sound/pci/cmipci.c val = ucontrol->value.integer.value[0] & reg.mask; val 2243 sound/pci/cmipci.c val = reg.mask - val; val 2245 sound/pci/cmipci.c nreg |= (val << reg.left_shift); val 2247 sound/pci/cmipci.c val = ucontrol->value.integer.value[1] & reg.mask; val 2249 sound/pci/cmipci.c val = reg.mask - val; val 2251 sound/pci/cmipci.c nreg |= (val << reg.right_shift); val 2338 sound/pci/cmipci.c unsigned int val; val 2348 sound/pci/cmipci.c val = inb(cm->iobase + args->reg); val 2350 sound/pci/cmipci.c val = snd_cmipci_read(cm, args->reg); val 2351 sound/pci/cmipci.c ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; val 2370 sound/pci/cmipci.c unsigned int val; val 2381 sound/pci/cmipci.c val = inb(cm->iobase + args->reg); val 2383 sound/pci/cmipci.c val = snd_cmipci_read(cm, args->reg); val 2384 sound/pci/cmipci.c change = (val & args->mask) != (ucontrol->value.integer.value[0] ? val 2387 sound/pci/cmipci.c val &= ~args->mask; val 2389 sound/pci/cmipci.c val |= args->mask_on; val 2391 sound/pci/cmipci.c val |= (args->mask & ~args->mask_on); val 2393 sound/pci/cmipci.c outb((unsigned char)val, cm->iobase + args->reg); val 2395 sound/pci/cmipci.c snd_cmipci_write(cm, args->reg, val); val 2513 sound/pci/cmipci.c unsigned int val; val 2515 sound/pci/cmipci.c val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); val 2516 sound/pci/cmipci.c if (val & (CM_CENTR2LIN | CM_BASE2LIN)) val 2519 sound/pci/cmipci.c val = snd_cmipci_read_b(cm, CM_REG_MIXER1); val 2520 sound/pci/cmipci.c if (val & CM_REAR2LIN) val 2944 sound/pci/cmipci.c unsigned int val; val 2961 sound/pci/cmipci.c val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; val 2964 sound/pci/cmipci.c case 0x3E8: val |= CM_FMSEL_3E8; break; val 2965 sound/pci/cmipci.c case 0x3E0: val |= CM_FMSEL_3E0; break; val 2966 sound/pci/cmipci.c case 0x3C8: val |= CM_FMSEL_3C8; break; val 2967 sound/pci/cmipci.c case 0x388: val |= CM_FMSEL_388; break; val 2971 sound/pci/cmipci.c snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); val 3003 sound/pci/cmipci.c unsigned int val; val 3113 sound/pci/cmipci.c val = pci->device < 0x110 ? 8338 : 8738; val 3117 sound/pci/cmipci.c val = 8769; val 3120 sound/pci/cmipci.c val = 8762; val 3131 sound/pci/cmipci.c val = 8770; val 3134 sound/pci/cmipci.c val = 8768; val 3139 sound/pci/cmipci.c sprintf(card->shortname, "C-Media CMI%d", val); val 3153 sound/pci/cmipci.c val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1); val 3154 sound/pci/cmipci.c if (val != 0x00 && val != 0xff) { val 3160 sound/pci/cmipci.c val = 0; val 3163 sound/pci/cmipci.c case 0x320: val = CM_VMPU_320; break; val 3164 sound/pci/cmipci.c case 0x310: val = CM_VMPU_310; break; val 3165 sound/pci/cmipci.c case 0x300: val = CM_VMPU_300; break; val 3166 sound/pci/cmipci.c case 0x330: val = CM_VMPU_330; break; val 3171 sound/pci/cmipci.c snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); val 3227 sound/pci/cmipci.c for (val = 0; val < ARRAY_SIZE(rates); val++) val 3228 sound/pci/cmipci.c snd_cmipci_set_pll(cm, rates[val], val); val 500 sound/pci/cs4281.c unsigned int val) val 502 sound/pci/cs4281.c writel(val, chip->ba0 + offset); val 511 sound/pci/cs4281.c unsigned short reg, unsigned short val) val 536 sound/pci/cs4281.c snd_cs4281_pokeBA0(chip, BA0_ACCDA, val); val 553 sound/pci/cs4281.c "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); val 697 sound/pci/cs4281.c unsigned int val; val 712 sound/pci/cs4281.c val = 1536000 / rate; val 714 sound/pci/cs4281.c *real_rate = 1536000 / val; val 715 sound/pci/cs4281.c return val; val 755 sound/pci/cs4281.c unsigned int val = snd_cs4281_rate(runtime->rate, NULL); val 757 sound/pci/cs4281.c snd_cs4281_pokeBA0(chip, BA0_DACSR, val); val 761 sound/pci/cs4281.c unsigned int val = snd_cs4281_rate(runtime->rate, NULL); val 763 sound/pci/cs4281.c snd_cs4281_pokeBA0(chip, BA0_ADCSR, val); val 1790 sound/pci/cs4281.c unsigned int status, dma, val; val 1807 sound/pci/cs4281.c val = snd_cs4281_peekBA0(chip, cdma->regHDSR); val 1811 sound/pci/cs4281.c if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { val 1817 sound/pci/cs4281.c if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { val 1862 sound/pci/cs4281.c unsigned char val) val 1878 sound/pci/cs4281.c writel((unsigned int)val, port + 4); val 205 sound/pci/cs46xx/cs46xx_lib.c unsigned short val; val 212 sound/pci/cs46xx/cs46xx_lib.c val = snd_cs46xx_codec_read(chip, reg, codec_index); val 214 sound/pci/cs46xx/cs46xx_lib.c return val; val 220 sound/pci/cs46xx/cs46xx_lib.c unsigned short val, val 252 sound/pci/cs46xx/cs46xx_lib.c snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val); val 280 sound/pci/cs46xx/cs46xx_lib.c codec_index, reg, val); val 287 sound/pci/cs46xx/cs46xx_lib.c unsigned short val) val 296 sound/pci/cs46xx/cs46xx_lib.c snd_cs46xx_codec_write(chip, reg, val, codec_index); val 1904 sound/pci/cs46xx/cs46xx_lib.c unsigned int val = snd_cs46xx_peek(chip, reg); val 1905 sound/pci/cs46xx/cs46xx_lib.c ucontrol->value.integer.value[0] = 0xffff - (val >> 16); val 1906 sound/pci/cs46xx/cs46xx_lib.c ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff); val 1914 sound/pci/cs46xx/cs46xx_lib.c unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | val 1917 sound/pci/cs46xx/cs46xx_lib.c int change = (old != val); val 1920 sound/pci/cs46xx/cs46xx_lib.c snd_cs46xx_poke(chip, reg, val); val 2169 sound/pci/cs46xx/cs46xx_lib.c unsigned int val; val 2173 sound/pci/cs46xx/cs46xx_lib.c val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | val 2180 sound/pci/cs46xx/cs46xx_lib.c change = (unsigned int)ins->spdif_csuv_default != val; val 2181 sound/pci/cs46xx/cs46xx_lib.c ins->spdif_csuv_default = val; val 2184 sound/pci/cs46xx/cs46xx_lib.c cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); val 2222 sound/pci/cs46xx/cs46xx_lib.c unsigned int val; val 2226 sound/pci/cs46xx/cs46xx_lib.c val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | val 2233 sound/pci/cs46xx/cs46xx_lib.c change = ins->spdif_csuv_stream != val; val 2234 sound/pci/cs46xx/cs46xx_lib.c ins->spdif_csuv_stream = val; val 2237 sound/pci/cs46xx/cs46xx_lib.c cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); val 2347 sound/pci/cs46xx/cs46xx_lib.c unsigned short val; val 2348 sound/pci/cs46xx/cs46xx_lib.c val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE); val 2349 sound/pci/cs46xx/cs46xx_lib.c ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1; val 3445 sound/pci/cs46xx/cs46xx_lib.c int oval, val; val 3450 sound/pci/cs46xx/cs46xx_lib.c val = oval; val 3453 sound/pci/cs46xx/cs46xx_lib.c val |= 0x8000; val 3456 sound/pci/cs46xx/cs46xx_lib.c val &= ~0x8000; val 3458 sound/pci/cs46xx/cs46xx_lib.c if (val != oval) { val 3459 sound/pci/cs46xx/cs46xx_lib.c snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val, val 45 sound/pci/cs46xx/cs46xx_lib.h static inline void snd_cs46xx_poke(struct snd_cs46xx *chip, unsigned long reg, unsigned int val) val 55 sound/pci/cs46xx/cs46xx_lib.h writel(val, chip->region.idx[bank+1].remap_addr + offset); val 65 sound/pci/cs46xx/cs46xx_lib.h static inline void snd_cs46xx_pokeBA0(struct snd_cs46xx *chip, unsigned long offset, unsigned int val) val 67 sound/pci/cs46xx/cs46xx_lib.h writel(val, chip->region.name.ba0.remap_addr + offset); val 558 sound/pci/cs46xx/dsp_spos.c u32 val; val 563 sound/pci/cs46xx/dsp_spos.c val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32)); val 564 sound/pci/cs46xx/dsp_spos.c snd_iprintf(buffer,"%08x ",val); val 174 sound/pci/cs46xx/dsp_spos.h static inline u8 _wrap_all_bits (u8 val) val 180 sound/pci/cs46xx/dsp_spos.h ((val & 0x1 ) << 7) | val 181 sound/pci/cs46xx/dsp_spos.h ((val & 0x2 ) << 5) | val 182 sound/pci/cs46xx/dsp_spos.h ((val & 0x4 ) << 3) | val 183 sound/pci/cs46xx/dsp_spos.h ((val & 0x8 ) << 1) | val 184 sound/pci/cs46xx/dsp_spos.h ((val & 0x10) >> 1) | val 185 sound/pci/cs46xx/dsp_spos.h ((val & 0x20) >> 3) | val 186 sound/pci/cs46xx/dsp_spos.h ((val & 0x40) >> 5) | val 187 sound/pci/cs46xx/dsp_spos.h ((val & 0x80) >> 7); val 207 sound/pci/cs46xx/dsp_spos.h unsigned int val = ((0xffff - left) << 16 | (0xffff - right)); val 209 sound/pci/cs46xx/dsp_spos.h snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl) << 2, val); val 210 sound/pci/cs46xx/dsp_spos.h snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl + 1) << 2, val); val 82 sound/pci/cs5535audio/cs5535audio.c unsigned int val; val 93 sound/pci/cs5535audio/cs5535audio.c val = cs_readl(cs5535au, ACC_CODEC_STATUS); val 94 sound/pci/cs5535audio/cs5535audio.c if ((val & STS_NEW) && reg == (val >> 24)) val 101 sound/pci/cs5535audio/cs5535audio.c reg, val); val 103 sound/pci/cs5535audio/cs5535audio.c return (unsigned short) val; val 107 sound/pci/cs5535audio/cs5535audio.c unsigned short reg, unsigned short val) val 112 sound/pci/cs5535audio/cs5535audio.c regdata |= val; val 122 sound/pci/cs5535audio/cs5535audio.c unsigned short reg, unsigned short val) val 125 sound/pci/cs5535audio/cs5535audio.c snd_cs5535audio_codec_write(cs5535au, reg, val); val 5 sound/pci/cs5535audio/cs5535audio.h #define cs_writel(cs5535au, reg, val) outl(val, (cs5535au)->port + reg) val 6 sound/pci/cs5535audio/cs5535audio.h #define cs_writeb(cs5535au, reg, val) outb(val, (cs5535au)->port + reg) val 347 sound/pci/ctxfi/ctmixer.c int i, val; val 352 sound/pci/ctxfi/ctmixer.c val = amixer->ops->get_scale(amixer) / VOL_SCALE; val 353 sound/pci/ctxfi/ctmixer.c if (val < 0) val 354 sound/pci/ctxfi/ctmixer.c val = 0; val 355 sound/pci/ctxfi/ctmixer.c else if (val > VOL_MAX) val 356 sound/pci/ctxfi/ctmixer.c val = VOL_MAX; val 357 sound/pci/ctxfi/ctmixer.c ucontrol->value.integer.value[i] = val; val 370 sound/pci/ctxfi/ctmixer.c int i, j, val, oval, change = 0; val 373 sound/pci/ctxfi/ctmixer.c val = ucontrol->value.integer.value[i]; val 374 sound/pci/ctxfi/ctmixer.c if (val < 0) val 375 sound/pci/ctxfi/ctmixer.c val = 0; val 376 sound/pci/ctxfi/ctmixer.c else if (val > VOL_MAX) val 377 sound/pci/ctxfi/ctmixer.c val = VOL_MAX; val 378 sound/pci/ctxfi/ctmixer.c val *= VOL_SCALE; val 381 sound/pci/ctxfi/ctmixer.c if (val != oval) { val 382 sound/pci/ctxfi/ctmixer.c amixer->ops->set_scale(amixer, val); val 390 sound/pci/ctxfi/ctmixer.c amixer->ops->set_scale(amixer, val); val 225 sound/pci/emu10k1/emu10k1_callback.c int state, val; val 241 sound/pci/emu10k1/emu10k1_callback.c val = snd_emu10k1_ptr_read(hw, CVCF_CURRENTVOL, vp->ch); val 242 sound/pci/emu10k1/emu10k1_callback.c if (! val) val 256 sound/pci/emu10k1/emu10k1_callback.c val = snd_emu10k1_ptr_read(hw, CCCA_CURRADDR, vp->ch); val 257 sound/pci/emu10k1/emu10k1_callback.c if (val >= vp->reg.loopstart) val 411 sound/pci/emu10k1/emu10k1_callback.c unsigned int val, sample; val 412 sound/pci/emu10k1/emu10k1_callback.c val = 32; val 417 sound/pci/emu10k1/emu10k1_callback.c val *= 2; val 431 sound/pci/emu10k1/emu10k1_callback.c val -= 4; val 432 sound/pci/emu10k1/emu10k1_callback.c val <<= 25; val 433 sound/pci/emu10k1/emu10k1_callback.c val |= 0x1c << 16; val 434 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, CCR, ch, val); val 533 sound/pci/emu10k1/emu10k1_callback.c unsigned int val; val 534 sound/pci/emu10k1/emu10k1_callback.c val = snd_emu10k1_ptr_read(hw, CCCA, vp->ch) & ~CCCA_RESONANCE; val 535 sound/pci/emu10k1/emu10k1_callback.c val |= (vp->reg.parm.filterQ << 28); val 536 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, CCCA, vp->ch, val); val 2097 sound/pci/emu10k1/emu10k1_main.c unsigned int *val; val 2099 sound/pci/emu10k1/emu10k1_main.c val = emu->saved_ptr; val 2101 sound/pci/emu10k1/emu10k1_main.c for (i = 0; i < NUM_G; i++, val++) val 2102 sound/pci/emu10k1/emu10k1_main.c *val = snd_emu10k1_ptr_read(emu, *reg, i); val 2105 sound/pci/emu10k1/emu10k1_main.c for (i = 0; i < NUM_G; i++, val++) val 2106 sound/pci/emu10k1/emu10k1_main.c *val = snd_emu10k1_ptr_read(emu, *reg, i); val 2130 sound/pci/emu10k1/emu10k1_main.c unsigned int *val; val 2139 sound/pci/emu10k1/emu10k1_main.c val = emu->saved_ptr; val 2141 sound/pci/emu10k1/emu10k1_main.c for (i = 0; i < NUM_G; i++, val++) val 2142 sound/pci/emu10k1/emu10k1_main.c snd_emu10k1_ptr_write(emu, *reg, i, *val); val 2145 sound/pci/emu10k1/emu10k1_main.c for (i = 0; i < NUM_G; i++, val++) val 2146 sound/pci/emu10k1/emu10k1_main.c snd_emu10k1_ptr_write(emu, *reg, i, *val); val 286 sound/pci/emu10k1/emu10k1x.c unsigned int regptr, val; val 292 sound/pci/emu10k1/emu10k1x.c val = inl(emu->port + DATA); val 294 sound/pci/emu10k1/emu10k1x.c return val; val 699 sound/pci/emu10k1/emu10k1x.c unsigned short val; val 703 sound/pci/emu10k1/emu10k1x.c val = inw(emu->port + AC97DATA); val 705 sound/pci/emu10k1/emu10k1x.c return val; val 709 sound/pci/emu10k1/emu10k1x.c unsigned short reg, unsigned short val) val 716 sound/pci/emu10k1/emu10k1x.c outw(val, emu->port + AC97DATA); val 1041 sound/pci/emu10k1/emu10k1x.c unsigned int reg, channel_id , val; val 1044 sound/pci/emu10k1/emu10k1x.c if (sscanf(line, "%x %x %x", ®, &channel_id, &val) != 3) val 1047 sound/pci/emu10k1/emu10k1x.c if (reg < 0x49 && val <= 0xffffffff && channel_id <= 2) val 1048 sound/pci/emu10k1/emu10k1x.c snd_emu10k1x_ptr_write(emu, reg, channel_id, val); val 1076 sound/pci/emu10k1/emu10k1x.c unsigned int val; val 1078 sound/pci/emu10k1/emu10k1x.c val = ucontrol->value.integer.value[0] ; val 1080 sound/pci/emu10k1/emu10k1x.c if (val) { val 1139 sound/pci/emu10k1/emu10k1x.c unsigned int val; val 1141 sound/pci/emu10k1/emu10k1x.c val = (ucontrol->value.iec958.status[0] << 0) | val 1145 sound/pci/emu10k1/emu10k1x.c change = val != emu->spdif_bits[idx]; val 1147 sound/pci/emu10k1/emu10k1x.c snd_emu10k1x_ptr_write(emu, SPCS0 + idx, 0, val); val 1148 sound/pci/emu10k1/emu10k1x.c emu->spdif_bits[idx] = val; val 340 sound/pci/emu10k1/emufx.c unsigned int nval, val; val 353 sound/pci/emu10k1/emufx.c val = ctl->value[i] = nval; val 356 sound/pci/emu10k1/emufx.c snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val); val 359 sound/pci/emu10k1/emufx.c snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]); val 367 sound/pci/emu10k1/emufx.c snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]); val 375 sound/pci/emu10k1/emufx.c snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]); val 378 sound/pci/emu10k1/emufx.c snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]); val 510 sound/pci/emu10k1/emufx.c u32 val; val 516 sound/pci/emu10k1/emufx.c val = *(__force u32 *)&icode->gpr_map[gpr]; val 517 sound/pci/emu10k1/emufx.c else if (get_user(val, &icode->gpr_map[gpr])) val 519 sound/pci/emu10k1/emufx.c snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val); val 528 sound/pci/emu10k1/emufx.c u32 val; val 532 sound/pci/emu10k1/emufx.c val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0); val 533 sound/pci/emu10k1/emufx.c if (put_user(val, &icode->gpr_map[gpr])) val 544 sound/pci/emu10k1/emufx.c u32 addr, val; val 550 sound/pci/emu10k1/emufx.c val = *(__force u32 *)&icode->tram_data_map[tram]; val 553 sound/pci/emu10k1/emufx.c if (get_user(val, &icode->tram_data_map[tram]) || val 557 sound/pci/emu10k1/emufx.c snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val); val 572 sound/pci/emu10k1/emufx.c u32 val, addr; val 577 sound/pci/emu10k1/emufx.c val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0); val 584 sound/pci/emu10k1/emufx.c if (put_user(val, &icode->tram_data_map[tram]) || val 789 sound/pci/emu10k1/emufx.c struct snd_ctl_elem_value *val; val 792 sound/pci/emu10k1/emufx.c val = kmalloc(sizeof(*val), GFP_KERNEL); val 795 sound/pci/emu10k1/emufx.c if (!val || !gctl || !nctl) { val 835 sound/pci/emu10k1/emufx.c val->value.integer.value[j] = gctl->value[j]; val 865 sound/pci/emu10k1/emufx.c snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val); val 870 sound/pci/emu10k1/emufx.c kfree(val); val 409 sound/pci/emu10k1/emumixer.c unsigned int val; val 412 sound/pci/emu10k1/emumixer.c val = ucontrol->value.enumerated.item[0]; val 413 sound/pci/emu10k1/emumixer.c if (val >= 53 || val 415 sound/pci/emu10k1/emumixer.c val >= 49)) val 423 sound/pci/emu10k1/emumixer.c if (emu->emu1010.output_source[channel] == val) val 425 sound/pci/emu10k1/emumixer.c emu->emu1010.output_source[channel] = val; val 428 sound/pci/emu10k1/emumixer.c emu1616_output_dst[channel], emu1616_src_regs[val]); val 431 sound/pci/emu10k1/emumixer.c emu1010_output_dst[channel], emu1010_src_regs[val]); val 453 sound/pci/emu10k1/emumixer.c unsigned int val; val 456 sound/pci/emu10k1/emumixer.c val = ucontrol->value.enumerated.item[0]; val 457 sound/pci/emu10k1/emumixer.c if (val >= 53 || val 459 sound/pci/emu10k1/emumixer.c val >= 49)) val 465 sound/pci/emu10k1/emumixer.c if (emu->emu1010.input_source[channel] == val) val 467 sound/pci/emu10k1/emumixer.c emu->emu1010.input_source[channel] = val; val 470 sound/pci/emu10k1/emumixer.c emu1010_input_dst[channel], emu1616_src_regs[val]); val 473 sound/pci/emu10k1/emumixer.c emu1010_input_dst[channel], emu1010_src_regs[val]); val 589 sound/pci/emu10k1/emumixer.c unsigned int val, cache; val 590 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[0]; val 592 sound/pci/emu10k1/emumixer.c if (val == 1) val 637 sound/pci/emu10k1/emumixer.c unsigned int val, cache; val 638 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[0]; val 640 sound/pci/emu10k1/emumixer.c if (val == 1) val 696 sound/pci/emu10k1/emumixer.c unsigned int val; val 699 sound/pci/emu10k1/emumixer.c val = ucontrol->value.enumerated.item[0] ; val 701 sound/pci/emu10k1/emumixer.c if (val >= 4) val 703 sound/pci/emu10k1/emumixer.c change = (emu->emu1010.internal_clock != val); val 705 sound/pci/emu10k1/emumixer.c emu->emu1010.internal_clock = val; val 706 sound/pci/emu10k1/emumixer.c switch (val) { val 818 sound/pci/emu10k1/emumixer.c unsigned int val; val 822 sound/pci/emu10k1/emumixer.c val = ucontrol->value.enumerated.item[0]; val 824 sound/pci/emu10k1/emumixer.c if (val >= 2) val 826 sound/pci/emu10k1/emumixer.c change = (emu->emu1010.optical_out != val); val 828 sound/pci/emu10k1/emumixer.c emu->emu1010.optical_out = val; val 869 sound/pci/emu10k1/emumixer.c unsigned int val; val 873 sound/pci/emu10k1/emumixer.c val = ucontrol->value.enumerated.item[0]; val 875 sound/pci/emu10k1/emumixer.c if (val >= 2) val 877 sound/pci/emu10k1/emumixer.c change = (emu->emu1010.optical_in != val); val 879 sound/pci/emu10k1/emumixer.c emu->emu1010.optical_in = val; val 1099 sound/pci/emu10k1/emumixer.c unsigned int reg, val, tmp; val 1104 sound/pci/emu10k1/emumixer.c val = A_SPDIF_44100; val 1107 sound/pci/emu10k1/emumixer.c val = A_SPDIF_48000; val 1110 sound/pci/emu10k1/emumixer.c val = A_SPDIF_96000; val 1113 sound/pci/emu10k1/emumixer.c val = A_SPDIF_48000; val 1121 sound/pci/emu10k1/emumixer.c tmp |= val; val 1146 sound/pci/emu10k1/emumixer.c unsigned int val; val 1152 sound/pci/emu10k1/emumixer.c val = (ucontrol->value.iec958.status[0] << 0) | val 1157 sound/pci/emu10k1/emumixer.c change = val != emu->spdif_bits[idx]; val 1159 sound/pci/emu10k1/emumixer.c snd_emu10k1_ptr_write(emu, SPCS0 + idx, 0, val); val 1160 sound/pci/emu10k1/emumixer.c emu->spdif_bits[idx] = val; val 1207 sound/pci/emu10k1/emumixer.c unsigned int val = ((unsigned int)volume[4] << 24) | val 1211 sound/pci/emu10k1/emumixer.c snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, voice, val); val 1254 sound/pci/emu10k1/emumixer.c int change = 0, voice, idx, val; val 1261 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[(voice * num_efx) + idx] & mask; val 1262 sound/pci/emu10k1/emumixer.c if (mix->send_routing[voice][idx] != val) { val 1263 sound/pci/emu10k1/emumixer.c mix->send_routing[voice][idx] = val; val 1327 sound/pci/emu10k1/emumixer.c int change = 0, idx, val; val 1332 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[idx] & 255; val 1333 sound/pci/emu10k1/emumixer.c if (mix->send_volume[idx/num_efx][idx%num_efx] != val) { val 1334 sound/pci/emu10k1/emumixer.c mix->send_volume[idx/num_efx][idx%num_efx] = val; val 1396 sound/pci/emu10k1/emumixer.c int change = 0, idx, val; val 1400 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[idx] & 0xffff; val 1401 sound/pci/emu10k1/emumixer.c if (mix->attn[idx] != val) { val 1402 sound/pci/emu10k1/emumixer.c mix->attn[idx] = val; val 1467 sound/pci/emu10k1/emumixer.c int change = 0, idx, val; val 1473 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[idx] & mask; val 1474 sound/pci/emu10k1/emumixer.c if (mix->send_routing[0][idx] != val) { val 1475 sound/pci/emu10k1/emumixer.c mix->send_routing[0][idx] = val; val 1535 sound/pci/emu10k1/emumixer.c int change = 0, idx, val; val 1540 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[idx] & 255; val 1541 sound/pci/emu10k1/emumixer.c if (mix->send_volume[0][idx] != val) { val 1542 sound/pci/emu10k1/emumixer.c mix->send_volume[0][idx] = val; val 1598 sound/pci/emu10k1/emumixer.c int change = 0, val; val 1601 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[0] & 0xffff; val 1602 sound/pci/emu10k1/emumixer.c if (mix->attn[0] != val) { val 1603 sound/pci/emu10k1/emumixer.c mix->attn[0] = val; val 1649 sound/pci/emu10k1/emumixer.c unsigned int reg, val, sw; val 1660 sound/pci/emu10k1/emumixer.c val = sw ? A_IOCFG_GPOUT0 : 0; val 1661 sound/pci/emu10k1/emumixer.c change = (reg & A_IOCFG_GPOUT0) != val; val 1664 sound/pci/emu10k1/emumixer.c reg |= val; val 1665 sound/pci/emu10k1/emumixer.c outl(reg | val, emu->port + A_IOCFG); val 1669 sound/pci/emu10k1/emumixer.c val = sw ? HCFG_GPOUT0 : 0; val 1670 sound/pci/emu10k1/emumixer.c change |= (reg & HCFG_GPOUT0) != val; val 1673 sound/pci/emu10k1/emumixer.c reg |= val; val 1674 sound/pci/emu10k1/emumixer.c outl(reg | val, emu->port + HCFG); val 1706 sound/pci/emu10k1/emumixer.c unsigned int val; val 1709 sound/pci/emu10k1/emumixer.c val = snd_ac97_read(emu->ac97, AC97_REC_GAIN); val 1710 sound/pci/emu10k1/emumixer.c ucontrol->value.integer.value[0] = !!val; val 1718 sound/pci/emu10k1/emumixer.c unsigned int val; val 1721 sound/pci/emu10k1/emumixer.c val = 0x0f0f; val 1723 sound/pci/emu10k1/emumixer.c val = 0; val 1724 sound/pci/emu10k1/emumixer.c return snd_ac97_update(emu->ac97, AC97_REC_GAIN, val); val 173 sound/pci/emu10k1/emuproc.c unsigned int val, val1; val 186 sound/pci/emu10k1/emuproc.c val = emu->audigy ? val 195 sound/pci/emu10k1/emuproc.c val & 0x3f, val 196 sound/pci/emu10k1/emuproc.c (val >> 8) & 0x3f, val 197 sound/pci/emu10k1/emuproc.c (val >> 16) & 0x3f, val 198 sound/pci/emu10k1/emuproc.c (val >> 24) & 0x3f); val 207 sound/pci/emu10k1/emuproc.c (val >> 16) & 0x0f, val 208 sound/pci/emu10k1/emuproc.c (val >> 20) & 0x0f, val 209 sound/pci/emu10k1/emuproc.c (val >> 24) & 0x0f, val 210 sound/pci/emu10k1/emuproc.c (val >> 28) & 0x0f); val 255 sound/pci/emu10k1/emuproc.c val = snd_emu10k1_ptr_read(emu, ZVSRCS, 0); val 257 sound/pci/emu10k1/emuproc.c snd_iprintf(buffer, "Rate Locked : %s\n", val & SRCS_RATELOCKED ? "on" : "off"); val 258 sound/pci/emu10k1/emuproc.c snd_iprintf(buffer, "Estimated Sample Rate : 0x%x\n", val & SRCS_ESTSAMPLERATE); val 267 sound/pci/emu10k1/emuproc.c unsigned int val, tmp, n; val 268 sound/pci/emu10k1/emuproc.c val = snd_emu10k1_ptr20_read(emu, CAPTURE_RATE_STATUS, 0); val 270 sound/pci/emu10k1/emuproc.c tmp = val >> (16 + (n*4)); val 346 sound/pci/emu10k1/emuproc.c unsigned int val; val 347 sound/pci/emu10k1/emuproc.c val = snd_emu10k1_ptr_read(emu, offset + idx + (pos >> 2), 0); val 349 sound/pci/emu10k1/emuproc.c val >>= 11; val 350 sound/pci/emu10k1/emuproc.c val |= snd_emu10k1_ptr_read(emu, 0x100 + idx + (pos >> 2), 0) << 20; val 352 sound/pci/emu10k1/emuproc.c tmp[idx] = val; val 419 sound/pci/emu10k1/emuproc.c u32 reg, val; val 421 sound/pci/emu10k1/emuproc.c if (sscanf(line, "%x %x", ®, &val) != 2) val 423 sound/pci/emu10k1/emuproc.c if (reg < 0x40 && val <= 0xffffffff) { val 425 sound/pci/emu10k1/emuproc.c outl(val, emu->port + (reg & 0xfffffffc)); val 437 sound/pci/emu10k1/emuproc.c unsigned int regptr, val; val 443 sound/pci/emu10k1/emuproc.c val = inl(emu->port + iobase + DATA); val 445 sound/pci/emu10k1/emuproc.c return val; val 495 sound/pci/emu10k1/emuproc.c unsigned int reg, channel_id , val; val 497 sound/pci/emu10k1/emuproc.c if (sscanf(line, "%x %x %x", ®, &channel_id, &val) != 3) val 499 sound/pci/emu10k1/emuproc.c if (reg < 0xa0 && val <= 0xffffffff && channel_id <= 3) val 500 sound/pci/emu10k1/emuproc.c snd_ptr_write(emu, iobase, reg, channel_id, val); val 24 sound/pci/emu10k1/io.c unsigned int regptr, val; val 39 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 42 sound/pci/emu10k1/io.c return (val & mask) >> offset; val 46 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 48 sound/pci/emu10k1/io.c return val; val 93 sound/pci/emu10k1/io.c unsigned int regptr, val; val 99 sound/pci/emu10k1/io.c val = inl(emu->port + 0x20 + DATA); val 101 sound/pci/emu10k1/io.c return val; val 313 sound/pci/emu10k1/io.c unsigned int val; val 319 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 320 sound/pci/emu10k1/io.c val |= 1 << (voicenum - 32); val 323 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 324 sound/pci/emu10k1/io.c val |= 1 << voicenum; val 326 sound/pci/emu10k1/io.c outl(val, emu->port + DATA); val 333 sound/pci/emu10k1/io.c unsigned int val; val 339 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 340 sound/pci/emu10k1/io.c val &= ~(1 << (voicenum - 32)); val 343 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 344 sound/pci/emu10k1/io.c val &= ~(1 << voicenum); val 346 sound/pci/emu10k1/io.c outl(val, emu->port + DATA); val 370 sound/pci/emu10k1/io.c unsigned int val; val 376 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 377 sound/pci/emu10k1/io.c val |= 1 << (voicenum - 32); val 380 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 381 sound/pci/emu10k1/io.c val |= 1 << voicenum; val 383 sound/pci/emu10k1/io.c outl(val, emu->port + DATA); val 390 sound/pci/emu10k1/io.c unsigned int val; val 396 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 397 sound/pci/emu10k1/io.c val &= ~(1 << (voicenum - 32)); val 400 sound/pci/emu10k1/io.c val = inl(emu->port + DATA); val 401 sound/pci/emu10k1/io.c val &= ~(1 << voicenum); val 403 sound/pci/emu10k1/io.c outl(val, emu->port + DATA); val 487 sound/pci/emu10k1/io.c unsigned short val; val 491 sound/pci/emu10k1/io.c val = inw(emu->port + AC97DATA); val 493 sound/pci/emu10k1/io.c return val; val 49 sound/pci/emu10k1/irq.c u32 val; val 52 sound/pci/emu10k1/irq.c val = snd_emu10k1_ptr_read(emu, CLIPL, 0); val 55 sound/pci/emu10k1/irq.c val = snd_emu10k1_ptr_read(emu, CLIPH, 0); val 56 sound/pci/emu10k1/irq.c if (val & 1) { val 64 sound/pci/emu10k1/irq.c val >>= 1; val 67 sound/pci/emu10k1/irq.c val = snd_emu10k1_ptr_read(emu, HLIPL, 0); val 70 sound/pci/emu10k1/irq.c val = snd_emu10k1_ptr_read(emu, HLIPH, 0); val 71 sound/pci/emu10k1/irq.c if (val & 1) { val 79 sound/pci/emu10k1/irq.c val >>= 1; val 748 sound/pci/emu10k1/p16v.c unsigned int val; val 753 sound/pci/emu10k1/p16v.c val = ucontrol->value.enumerated.item[0] ; val 754 sound/pci/emu10k1/p16v.c if (val > 7) val 756 sound/pci/emu10k1/p16v.c change = (emu->p16v_capture_source != val); val 758 sound/pci/emu10k1/p16v.c emu->p16v_capture_source = val; val 759 sound/pci/emu10k1/p16v.c source = (val << 28) | (val << 24) | (val << 20) | (val << 16); val 787 sound/pci/emu10k1/p16v.c unsigned int val; val 791 sound/pci/emu10k1/p16v.c val = ucontrol->value.enumerated.item[0] ; val 792 sound/pci/emu10k1/p16v.c if (val > 3) val 794 sound/pci/emu10k1/p16v.c change = (emu->p16v_capture_channel != val); val 796 sound/pci/emu10k1/p16v.c emu->p16v_capture_channel = val; val 798 sound/pci/emu10k1/p16v.c snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, tmp | val); val 874 sound/pci/emu10k1/p16v.c unsigned int *val; val 876 sound/pci/emu10k1/p16v.c val = emu->p16v_saved; val 878 sound/pci/emu10k1/p16v.c for (i = 0; i < 0x80; i++, val++) val 879 sound/pci/emu10k1/p16v.c *val = snd_emu10k1_ptr20_read(emu, i, ch); val 885 sound/pci/emu10k1/p16v.c unsigned int *val; val 887 sound/pci/emu10k1/p16v.c val = emu->p16v_saved; val 889 sound/pci/emu10k1/p16v.c for (i = 0; i < 0x80; i++, val++) val 890 sound/pci/emu10k1/p16v.c snd_emu10k1_ptr20_write(emu, i, ch, *val); val 570 sound/pci/ens1370.c unsigned short reg, unsigned short val) val 578 sound/pci/ens1370.c reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); val 582 sound/pci/ens1370.c outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); val 601 sound/pci/ens1370.c unsigned short reg, unsigned short val) val 628 sound/pci/ens1370.c outl(ES_1371_CODEC_WRITE(reg, val) | flag, val 1355 sound/pci/ens1370.c unsigned int val; val 1358 sound/pci/ens1370.c val = ((u32)ucontrol->value.iec958.status[0] << 0) | val 1363 sound/pci/ens1370.c change = ensoniq->spdif_default != val; val 1364 sound/pci/ens1370.c ensoniq->spdif_default = val; val 1367 sound/pci/ens1370.c outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); val 1399 sound/pci/ens1370.c unsigned int val; val 1402 sound/pci/ens1370.c val = ((u32)ucontrol->value.iec958.status[0] << 0) | val 1407 sound/pci/ens1370.c change = ensoniq->spdif_stream != val; val 1408 sound/pci/ens1370.c ensoniq->spdif_stream = val; val 1411 sound/pci/ens1370.c outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); val 1488 sound/pci/ens1370.c int val = 0; val 1493 sound/pci/ens1370.c val = 1; val 1494 sound/pci/ens1370.c ucontrol->value.integer.value[0] = val; val 1533 sound/pci/ens1370.c int val = 0; val 1537 sound/pci/ens1370.c val = 1; val 1538 sound/pci/ens1370.c ucontrol->value.integer.value[0] = val; val 244 sound/pci/es1938.c static void snd_es1938_mixer_write(struct es1938 *chip, unsigned char reg, unsigned char val) val 249 sound/pci/es1938.c outb(val, SLSB_REG(chip, MIXERDATA)); val 251 sound/pci/es1938.c dev_dbg(chip->card->dev, "Mixer reg %02x set to %02x\n", reg, val); val 273 sound/pci/es1938.c unsigned char mask, unsigned char val) val 281 sound/pci/es1938.c if (val != oval) { val 282 sound/pci/es1938.c new = (old & ~mask) | (val & mask); val 326 sound/pci/es1938.c static void snd_es1938_write(struct es1938 *chip, unsigned char reg, unsigned char val) val 331 sound/pci/es1938.c snd_es1938_write_cmd(chip, val); val 333 sound/pci/es1938.c dev_dbg(chip->card->dev, "Reg %02x set to %02x\n", reg, val); val 341 sound/pci/es1938.c unsigned char val; val 346 sound/pci/es1938.c val = snd_es1938_get_byte(chip); val 348 sound/pci/es1938.c dev_dbg(chip->card->dev, "Reg %02x now is %02x\n", reg, val); val 349 sound/pci/es1938.c return val; val 356 sound/pci/es1938.c unsigned char val) val 365 sound/pci/es1938.c if (val != oval) { val 367 sound/pci/es1938.c new = (old & ~mask) | (val & mask); val 520 sound/pci/es1938.c int val; val 524 sound/pci/es1938.c val = 0x0f; val 529 sound/pci/es1938.c val = 0x00; val 535 sound/pci/es1938.c snd_es1938_write(chip, ESS_CMD_DMACONTROL, val); val 573 sound/pci/es1938.c int val; val 577 sound/pci/es1938.c val = 5; val 582 sound/pci/es1938.c val = 0; val 588 sound/pci/es1938.c snd_es1938_write(chip, ESS_CMD_DMACONTROL, val); val 1069 sound/pci/es1938.c unsigned char val = ucontrol->value.enumerated.item[0]; val 1071 sound/pci/es1938.c if (val > 7) val 1073 sound/pci/es1938.c return snd_es1938_mixer_bits(chip, 0x1c, 0x07, val) != val; val 1082 sound/pci/es1938.c unsigned char val = snd_es1938_mixer_read(chip, 0x50); val 1083 sound/pci/es1938.c ucontrol->value.integer.value[0] = !!(val & 8); val 1143 sound/pci/es1938.c unsigned char mask, unsigned char val) val 1146 sound/pci/es1938.c return snd_es1938_mixer_bits(chip, reg, mask, val); val 1148 sound/pci/es1938.c return snd_es1938_bits(chip, reg, mask, val); val 1193 sound/pci/es1938.c int val; val 1195 sound/pci/es1938.c val = snd_es1938_reg_read(chip, reg); val 1196 sound/pci/es1938.c ucontrol->value.integer.value[0] = (val >> shift) & mask; val 1210 sound/pci/es1938.c unsigned char val; val 1212 sound/pci/es1938.c val = (ucontrol->value.integer.value[0] & mask); val 1214 sound/pci/es1938.c val = mask - val; val 1216 sound/pci/es1938.c val <<= shift; val 1217 sound/pci/es1938.c return snd_es1938_reg_bits(chip, reg, mask, val) != val; val 637 sound/pci/es1968.c static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) val 644 sound/pci/es1968.c outw(val, chip->io_port + ESM_AC97_DATA); val 1882 sound/pci/es1968.c int x, val; val 1901 sound/pci/es1968.c val = snd_ac97_read(chip->ac97, AC97_MASTER); val 1905 sound/pci/es1968.c val ^= 0x8000; val 1909 sound/pci/es1968.c if ((val & 0x7f) > 0) val 1910 sound/pci/es1968.c val--; val 1911 sound/pci/es1968.c if ((val & 0x7f00) > 0) val 1912 sound/pci/es1968.c val -= 0x0100; val 1916 sound/pci/es1968.c if ((val & 0x7f) < 0x1f) val 1917 sound/pci/es1968.c val++; val 1918 sound/pci/es1968.c if ((val & 0x7f00) < 0x1f00) val 1919 sound/pci/es1968.c val += 0x0100; val 1922 sound/pci/es1968.c if (snd_ac97_update(chip->ac97, AC97_MASTER, val)) val 1929 sound/pci/es1968.c val = 0; val 1935 sound/pci/es1968.c val = KEY_MUTE; val 1939 sound/pci/es1968.c val = KEY_VOLUMEUP; val 1943 sound/pci/es1968.c val = KEY_VOLUMEDOWN; val 1947 sound/pci/es1968.c if (val) { val 1948 sound/pci/es1968.c input_report_key(chip->input_dev, val, 1); val 1950 sound/pci/es1968.c input_report_key(chip->input_dev, val, 0); val 2440 sound/pci/es1968.c u16 val; val 2457 sound/pci/es1968.c pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val); val 2458 sound/pci/es1968.c pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04); val 2549 sound/pci/es1968.c u16 val = 0; val 2551 sound/pci/es1968.c val |= (pins & TEA575X_DATA) ? (1 << gpio.data) : 0; val 2552 sound/pci/es1968.c val |= (pins & TEA575X_CLK) ? (1 << gpio.clk) : 0; val 2553 sound/pci/es1968.c val |= (pins & TEA575X_WREN) ? (1 << gpio.wren) : 0; val 2555 sound/pci/es1968.c outw(val, chip->io_port + GPIO_DATA); val 2562 sound/pci/es1968.c u16 val = inw(chip->io_port + GPIO_DATA); val 2565 sound/pci/es1968.c if (val & (1 << gpio.data)) val 2567 sound/pci/es1968.c if (val & (1 << gpio.most)) val 274 sound/pci/fm801.c unsigned short val) val 287 sound/pci/fm801.c fm801_writew(chip, AC97_DATA, val); val 876 sound/pci/fm801.c unsigned short val; val 878 sound/pci/fm801.c val = (ucontrol->value.integer.value[0] & mask); val 880 sound/pci/fm801.c val = mask - val; val 881 sound/pci/fm801.c return snd_fm801_update_bits(chip, reg, mask << shift, val << shift); val 966 sound/pci/fm801.c unsigned short val; val 968 sound/pci/fm801.c val = fm801_readw(chip, REC_SRC) & 7; val 969 sound/pci/fm801.c if (val > 4) val 970 sound/pci/fm801.c val = 4; val 971 sound/pci/fm801.c ucontrol->value.enumerated.item[0] = val; val 979 sound/pci/fm801.c unsigned short val; val 981 sound/pci/fm801.c if ((val = ucontrol->value.enumerated.item[0]) > 4) val 983 sound/pci/fm801.c return snd_fm801_update_bits(chip, FM801_REC_SRC, 7, val); val 809 sound/pci/hda/hda_auto_parser.c snd_hda_codec_set_pincfg(codec, cfg->nid, cfg->val); val 817 sound/pci/hda/hda_auto_parser.c snd_hda_set_pin_ctl_cache(codec, cfg->nid, cfg->val); val 904 sound/pci/hda/hda_auto_parser.c if ((t_pins->val & IGNORE_SEQ_ASSOC) == (cfg & IGNORE_SEQ_ASSOC)) val 906 sound/pci/hda/hda_auto_parser.c else if ((cfg & 0xf0000000) == 0x40000000 && (t_pins->val & 0xf0000000) == 0x40000000) val 565 sound/pci/hda/hda_codec.c unsigned int val) val 572 sound/pci/hda/hda_codec.c pin->target = val; val 1295 sound/pci/hda/hda_codec.c int ch, int dir, int idx, int mask, int val) val 1299 sound/pci/hda/hda_codec.c return snd_hdac_regmap_update_raw(&codec->core, cmd, mask, val); val 1316 sound/pci/hda/hda_codec.c int direction, int idx, int mask, int val) val 1324 sound/pci/hda/hda_codec.c idx, mask, val); val 1344 sound/pci/hda/hda_codec.c int dir, int idx, int mask, int val) val 1350 sound/pci/hda/hda_codec.c return snd_hdac_regmap_update_raw_once(&codec->core, cmd, mask, val); val 1366 sound/pci/hda/hda_codec.c int dir, int idx, int mask, int val) val 1374 sound/pci/hda/hda_codec.c idx, mask, val); val 1426 sound/pci/hda/hda_codec.c unsigned int val; val 1427 sound/pci/hda/hda_codec.c val = snd_hda_codec_amp_read(codec, nid, ch, dir, idx); val 1428 sound/pci/hda/hda_codec.c val &= HDA_AMP_VOLMASK; val 1429 sound/pci/hda/hda_codec.c if (val >= ofs) val 1430 sound/pci/hda/hda_codec.c val -= ofs; val 1432 sound/pci/hda/hda_codec.c val = 0; val 1433 sound/pci/hda/hda_codec.c return val; val 1439 sound/pci/hda/hda_codec.c unsigned int val) val 1443 sound/pci/hda/hda_codec.c if (val > 0) val 1444 sound/pci/hda/hda_codec.c val += ofs; val 1447 sound/pci/hda/hda_codec.c if (val > maxval) val 1448 sound/pci/hda/hda_codec.c val = maxval; val 1450 sound/pci/hda/hda_codec.c HDA_AMP_VOLMASK, val); val 1839 sound/pci/hda/hda_codec.c static int put_kctl_with_value(struct snd_kcontrol *kctl, int val) val 1845 sound/pci/hda/hda_codec.c ucontrol->value.integer.value[0] = val; val 1846 sound/pci/hda/hda_codec.c ucontrol->value.integer.value[1] = val; val 1866 sound/pci/hda/hda_codec.c int val; val 1895 sound/pci/hda/hda_codec.c val = -tlv[SNDRV_CTL_TLVO_DB_SCALE_MIN] / step; val 1896 sound/pci/hda/hda_codec.c if (val > 0) { val 1897 sound/pci/hda/hda_codec.c put_kctl_with_value(slave, val); val 1898 sound/pci/hda/hda_codec.c return val; val 2228 sound/pci/hda/hda_codec.c unsigned short val = 0; val 2231 sound/pci/hda/hda_codec.c val |= AC_DIG1_PROFESSIONAL; val 2233 sound/pci/hda/hda_codec.c val |= AC_DIG1_NONAUDIO; val 2237 sound/pci/hda/hda_codec.c val |= AC_DIG1_EMPHASIS; val 2241 sound/pci/hda/hda_codec.c val |= AC_DIG1_EMPHASIS; val 2243 sound/pci/hda/hda_codec.c val |= AC_DIG1_COPYRIGHT; val 2245 sound/pci/hda/hda_codec.c val |= AC_DIG1_LEVEL; val 2246 sound/pci/hda/hda_codec.c val |= sbits & (IEC958_AES1_CON_CATEGORY << 8); val 2248 sound/pci/hda/hda_codec.c return val; val 2253 sound/pci/hda/hda_codec.c static unsigned int convert_to_spdif_status(unsigned short val) val 2257 sound/pci/hda/hda_codec.c if (val & AC_DIG1_NONAUDIO) val 2259 sound/pci/hda/hda_codec.c if (val & AC_DIG1_PROFESSIONAL) val 2262 sound/pci/hda/hda_codec.c if (val & AC_DIG1_EMPHASIS) val 2265 sound/pci/hda/hda_codec.c if (val & AC_DIG1_EMPHASIS) val 2267 sound/pci/hda/hda_codec.c if (!(val & AC_DIG1_COPYRIGHT)) val 2269 sound/pci/hda/hda_codec.c if (val & AC_DIG1_LEVEL) val 2271 sound/pci/hda/hda_codec.c sbits |= val & (0x7f << 8); val 2278 sound/pci/hda/hda_codec.c int mask, int val) val 2283 sound/pci/hda/hda_codec.c mask, val); val 2289 sound/pci/hda/hda_codec.c AC_VERB_SET_DIGI_CONVERT_1, mask, val); val 2296 sound/pci/hda/hda_codec.c unsigned int val = 0; val 2300 sound/pci/hda/hda_codec.c val = dig1; val 2304 sound/pci/hda/hda_codec.c val |= dig2 << 8; val 2306 sound/pci/hda/hda_codec.c set_dig_out(codec, nid, mask, val); val 2316 sound/pci/hda/hda_codec.c unsigned short val; val 2328 sound/pci/hda/hda_codec.c val = convert_from_spdif_status(spdif->status); val 2329 sound/pci/hda/hda_codec.c val |= spdif->ctls & 1; val 2330 sound/pci/hda/hda_codec.c change = spdif->ctls != val; val 2331 sound/pci/hda/hda_codec.c spdif->ctls = val; val 2333 sound/pci/hda/hda_codec.c set_dig_out_convert(codec, nid, val & 0xff, (val >> 8) & 0xff); val 2374 sound/pci/hda/hda_codec.c unsigned short val; val 2382 sound/pci/hda/hda_codec.c val = spdif->ctls & ~AC_DIG1_ENABLE; val 2384 sound/pci/hda/hda_codec.c val |= AC_DIG1_ENABLE; val 2385 sound/pci/hda/hda_codec.c change = spdif->ctls != val; val 2386 sound/pci/hda/hda_codec.c spdif->ctls = val; val 2388 sound/pci/hda/hda_codec.c set_spdif_ctls(codec, nid, val & 0xff, -1); val 2445 sound/pci/hda/hda_codec.c int val = 0; val 2487 sound/pci/hda/hda_codec.c AC_VERB_GET_DIGI_CONVERT_1, &val); val 2488 sound/pci/hda/hda_codec.c spdif->ctls = val; val 2546 sound/pci/hda/hda_codec.c unsigned short val; val 2554 sound/pci/hda/hda_codec.c val = spdif->ctls; val 2555 sound/pci/hda/hda_codec.c set_spdif_ctls(codec, nid, val & 0xff, (val >> 8) & 0xff); val 2629 sound/pci/hda/hda_codec.c unsigned int val = !!ucontrol->value.integer.value[0]; val 2633 sound/pci/hda/hda_codec.c change = codec->spdif_in_enable != val; val 2635 sound/pci/hda/hda_codec.c codec->spdif_in_enable = val; val 2637 sound/pci/hda/hda_codec.c AC_VERB_SET_DIGI_CONVERT_1, val); val 2648 sound/pci/hda/hda_codec.c unsigned int val; val 2652 sound/pci/hda/hda_codec.c AC_VERB_GET_DIGI_CONVERT_1, &val); val 2653 sound/pci/hda/hda_codec.c sbits = convert_to_spdif_status(val); val 3872 sound/pci/hda/hda_codec.c hda_nid_t pin, unsigned int val) val 3882 sound/pci/hda/hda_codec.c if (!val) val 3886 sound/pci/hda/hda_codec.c return val; /* don't know what to do... */ val 3888 sound/pci/hda/hda_codec.c if (val & AC_PINCTL_OUT_EN) { val 3890 sound/pci/hda/hda_codec.c val &= ~(AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN); val 3891 sound/pci/hda/hda_codec.c else if ((val & AC_PINCTL_HP_EN) && !(cap & AC_PINCAP_HP_DRV)) val 3892 sound/pci/hda/hda_codec.c val &= ~AC_PINCTL_HP_EN; val 3895 sound/pci/hda/hda_codec.c if (val & AC_PINCTL_IN_EN) { val 3897 sound/pci/hda/hda_codec.c val &= ~(AC_PINCTL_IN_EN | AC_PINCTL_VREFEN); val 3902 sound/pci/hda/hda_codec.c vref = val & AC_PINCTL_VREFEN; val 3912 sound/pci/hda/hda_codec.c val &= ~AC_PINCTL_VREFEN; val 3913 sound/pci/hda/hda_codec.c val |= vref; val 3917 sound/pci/hda/hda_codec.c return val; val 3935 sound/pci/hda/hda_codec.c unsigned int val, bool cached) val 3937 sound/pci/hda/hda_codec.c val = snd_hda_correct_pin_ctl(codec, pin, val); val 3938 sound/pci/hda/hda_codec.c snd_hda_codec_set_pin_target(codec, pin, val); val 3941 sound/pci/hda/hda_codec.c AC_VERB_SET_PIN_WIDGET_CONTROL, val); val 3944 sound/pci/hda/hda_codec.c AC_VERB_SET_PIN_WIDGET_CONTROL, val); val 928 sound/pci/hda/hda_controller.c static int azx_single_send_cmd(struct hdac_bus *bus, u32 val) val 931 sound/pci/hda/hda_controller.c unsigned int addr = azx_command_addr(val); val 934 sound/pci/hda/hda_controller.c bus->last_cmd[azx_command_addr(val)] = val; val 941 sound/pci/hda/hda_controller.c azx_writel(chip, IC, val); val 951 sound/pci/hda/hda_controller.c azx_readw(chip, IRS), val); val 972 sound/pci/hda/hda_controller.c static int azx_send_cmd(struct hdac_bus *bus, unsigned int val) val 979 sound/pci/hda/hda_controller.c return azx_single_send_cmd(bus, val); val 981 sound/pci/hda/hda_controller.c return snd_hdac_bus_send_cmd(bus, val); val 125 sound/pci/hda/hda_eld.c unsigned int val; val 127 sound/pci/hda/hda_eld.c val = snd_hda_codec_read(codec, nid, 0, val 130 sound/pci/hda/hda_eld.c codec_info(codec, "HDMI: ELD data byte %d: 0x%x\n", byte_index, val); val 132 sound/pci/hda/hda_eld.c return val; val 149 sound/pci/hda/hda_eld.c int val; val 151 sound/pci/hda/hda_eld.c val = GRAB_BITS(buf, 1, 0, 7); val 154 sound/pci/hda/hda_eld.c if (val & (1 << i)) val 170 sound/pci/hda/hda_eld.c val = GRAB_BITS(buf, 2, 0, 3); val 172 sound/pci/hda/hda_eld.c if (val & (1 << i)) val 319 sound/pci/hda/hda_eld.c unsigned int val = hdmi_get_eld_data(codec, nid, i); val 324 sound/pci/hda/hda_eld.c if (!(val & AC_ELDD_ELD_VALID)) { val 329 sound/pci/hda/hda_eld.c val &= AC_ELDD_ELD_DATA; val 336 sound/pci/hda/hda_eld.c if (!val && !i) { val 341 sound/pci/hda/hda_eld.c buf[i] = val; val 497 sound/pci/hda/hda_eld.c long long val; val 501 sound/pci/hda/hda_eld.c if (sscanf(line, "%s %llx", name, &val) != 2) val 509 sound/pci/hda/hda_eld.c eld->monitor_present = val; val 511 sound/pci/hda/hda_eld.c eld->eld_valid = val; val 513 sound/pci/hda/hda_eld.c e->conn_type = val; val 515 sound/pci/hda/hda_eld.c e->port_id = val; val 517 sound/pci/hda/hda_eld.c e->support_hdcp = val; val 519 sound/pci/hda/hda_eld.c e->support_ai = val; val 521 sound/pci/hda/hda_eld.c e->aud_synch_delay = val; val 523 sound/pci/hda/hda_eld.c e->spk_alloc = val; val 525 sound/pci/hda/hda_eld.c e->sad_count = val; val 536 sound/pci/hda/hda_eld.c e->sad[n].format = val; val 538 sound/pci/hda/hda_eld.c e->sad[n].channels = val; val 540 sound/pci/hda/hda_eld.c e->sad[n].rates = val; val 542 sound/pci/hda/hda_eld.c e->sad[n].sample_bits = val; val 544 sound/pci/hda/hda_eld.c e->sad[n].max_bitrate = val; val 546 sound/pci/hda/hda_eld.c e->sad[n].profile = val; val 102 sound/pci/hda/hda_generic.c int val; val 104 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "jack_detect"); val 105 sound/pci/hda/hda_generic.c if (val >= 0) val 106 sound/pci/hda/hda_generic.c codec->no_jack_detect = !val; val 107 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "inv_jack_detect"); val 108 sound/pci/hda/hda_generic.c if (val >= 0) val 109 sound/pci/hda/hda_generic.c codec->inv_jack_detect = !!val; val 110 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "trigger_sense"); val 111 sound/pci/hda/hda_generic.c if (val >= 0) val 112 sound/pci/hda/hda_generic.c codec->no_trigger_sense = !val; val 113 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "inv_eapd"); val 114 sound/pci/hda/hda_generic.c if (val >= 0) val 115 sound/pci/hda/hda_generic.c codec->inv_eapd = !!val; val 116 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "pcm_format_first"); val 117 sound/pci/hda/hda_generic.c if (val >= 0) val 118 sound/pci/hda/hda_generic.c codec->pcm_format_first = !!val; val 119 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "sticky_stream"); val 120 sound/pci/hda/hda_generic.c if (val >= 0) val 121 sound/pci/hda/hda_generic.c codec->no_sticky_stream = !val; val 122 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "spdif_status_reset"); val 123 sound/pci/hda/hda_generic.c if (val >= 0) val 124 sound/pci/hda/hda_generic.c codec->spdif_status_reset = !!val; val 125 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "pin_amp_workaround"); val 126 sound/pci/hda/hda_generic.c if (val >= 0) val 127 sound/pci/hda/hda_generic.c codec->pin_amp_workaround = !!val; val 128 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "single_adc_amp"); val 129 sound/pci/hda/hda_generic.c if (val >= 0) val 130 sound/pci/hda/hda_generic.c codec->single_adc_amp = !!val; val 131 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "power_save_node"); val 132 sound/pci/hda/hda_generic.c if (val >= 0) val 133 sound/pci/hda/hda_generic.c codec->power_save_node = !!val; val 135 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "auto_mute"); val 136 sound/pci/hda/hda_generic.c if (val >= 0) val 137 sound/pci/hda/hda_generic.c spec->suppress_auto_mute = !val; val 138 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "auto_mic"); val 139 sound/pci/hda/hda_generic.c if (val >= 0) val 140 sound/pci/hda/hda_generic.c spec->suppress_auto_mic = !val; val 141 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "line_in_auto_switch"); val 142 sound/pci/hda/hda_generic.c if (val >= 0) val 143 sound/pci/hda/hda_generic.c spec->line_in_auto_switch = !!val; val 144 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "auto_mute_via_amp"); val 145 sound/pci/hda/hda_generic.c if (val >= 0) val 146 sound/pci/hda/hda_generic.c spec->auto_mute_via_amp = !!val; val 147 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "need_dac_fix"); val 148 sound/pci/hda/hda_generic.c if (val >= 0) val 149 sound/pci/hda/hda_generic.c spec->need_dac_fix = !!val; val 150 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "primary_hp"); val 151 sound/pci/hda/hda_generic.c if (val >= 0) val 152 sound/pci/hda/hda_generic.c spec->no_primary_hp = !val; val 153 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "multi_io"); val 154 sound/pci/hda/hda_generic.c if (val >= 0) val 155 sound/pci/hda/hda_generic.c spec->no_multi_io = !val; val 156 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "multi_cap_vol"); val 157 sound/pci/hda/hda_generic.c if (val >= 0) val 158 sound/pci/hda/hda_generic.c spec->multi_cap_vol = !!val; val 159 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "inv_dmic_split"); val 160 sound/pci/hda/hda_generic.c if (val >= 0) val 161 sound/pci/hda/hda_generic.c spec->inv_dmic_split = !!val; val 162 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "indep_hp"); val 163 sound/pci/hda/hda_generic.c if (val >= 0) val 164 sound/pci/hda/hda_generic.c spec->indep_hp = !!val; val 165 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "add_stereo_mix_input"); val 166 sound/pci/hda/hda_generic.c if (val >= 0) val 167 sound/pci/hda/hda_generic.c spec->add_stereo_mix_input = !!val; val 169 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "add_out_jack_modes"); val 170 sound/pci/hda/hda_generic.c if (val >= 0) val 171 sound/pci/hda/hda_generic.c spec->add_jack_modes = !!val; val 172 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "add_in_jack_modes"); val 173 sound/pci/hda/hda_generic.c if (val >= 0) val 174 sound/pci/hda/hda_generic.c spec->add_jack_modes = !!val; val 175 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "add_jack_modes"); val 176 sound/pci/hda/hda_generic.c if (val >= 0) val 177 sound/pci/hda/hda_generic.c spec->add_jack_modes = !!val; val 178 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "power_down_unused"); val 179 sound/pci/hda/hda_generic.c if (val >= 0) val 180 sound/pci/hda/hda_generic.c spec->power_down_unused = !!val; val 181 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "add_hp_mic"); val 182 sound/pci/hda/hda_generic.c if (val >= 0) val 183 sound/pci/hda/hda_generic.c spec->hp_mic = !!val; val 184 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "hp_mic_detect"); val 185 sound/pci/hda/hda_generic.c if (val >= 0) val 186 sound/pci/hda/hda_generic.c spec->suppress_hp_mic_detect = !val; val 187 sound/pci/hda/hda_generic.c val = snd_hda_get_bool_hint(codec, "vmaster"); val 188 sound/pci/hda/hda_generic.c if (val >= 0) val 189 sound/pci/hda/hda_generic.c spec->suppress_vmaster = !val; val 191 sound/pci/hda/hda_generic.c if (!snd_hda_get_int_hint(codec, "mixer_nid", &val)) val 192 sound/pci/hda/hda_generic.c spec->mixer_nid = val; val 199 sound/pci/hda/hda_generic.c #define update_pin_ctl(codec, pin, val) \ val 201 sound/pci/hda/hda_generic.c AC_VERB_SET_PIN_WIDGET_CONTROL, val) val 211 sound/pci/hda/hda_generic.c unsigned int val, bool do_write) val 215 sound/pci/hda/hda_generic.c val = snd_hda_correct_pin_ctl(codec, pin, val); val 216 sound/pci/hda/hda_generic.c snd_hda_codec_set_pin_target(codec, pin, val); val 218 sound/pci/hda/hda_generic.c update_pin_ctl(codec, pin, val); val 223 sound/pci/hda/hda_generic.c hda_nid_t *pins, unsigned int val) val 227 sound/pci/hda/hda_generic.c set_pin_target(codec, pins[i], val, false); val 339 sound/pci/hda/hda_generic.c static bool is_ctl_used(struct hda_codec *codec, unsigned int val, int type) val 345 sound/pci/hda/hda_generic.c val &= AMP_VAL_COMPARE_MASK; val 347 sound/pci/hda/hda_generic.c if ((path->ctls[type] & AMP_VAL_COMPARE_MASK) == val) val 357 sound/pci/hda/hda_generic.c unsigned int val = HDA_COMPOSE_AMP_VAL(nid, 3, idx, dir); val 358 sound/pci/hda/hda_generic.c return is_ctl_used(codec, val, type); val 542 sound/pci/hda/hda_generic.c static unsigned int amp_val_replace_channels(unsigned int val, unsigned int chs) val 544 sound/pci/hda/hda_generic.c val &= ~(0x3U << 16); val 545 sound/pci/hda/hda_generic.c val |= chs << 16; val 546 sound/pci/hda/hda_generic.c return val; val 666 sound/pci/hda/hda_generic.c unsigned int val = 0; val 671 sound/pci/hda/hda_generic.c val = (caps & AC_AMPCAP_OFFSET) >> AC_AMPCAP_OFFSET_SHIFT; val 675 sound/pci/hda/hda_generic.c val |= HDA_AMP_MUTE; val 677 sound/pci/hda/hda_generic.c return val; val 701 sound/pci/hda/hda_generic.c int val = get_amp_val_to_activate(codec, nid, dir, caps, false); val 704 sound/pci/hda/hda_generic.c snd_hda_codec_amp_init_stereo(codec, nid, dir, idx, 0xff, val); val 706 sound/pci/hda/hda_generic.c snd_hda_codec_amp_init(codec, nid, 0, dir, idx, 0xff, val); val 711 sound/pci/hda/hda_generic.c unsigned int mask, unsigned int val) val 715 sound/pci/hda/hda_generic.c mask, val); val 718 sound/pci/hda/hda_generic.c mask, val); val 746 sound/pci/hda/hda_generic.c unsigned int mask, val; val 749 sound/pci/hda/hda_generic.c val = get_amp_val_to_activate(codec, nid, dir, caps, enable); val 754 sound/pci/hda/hda_generic.c val &= mask; val 755 sound/pci/hda/hda_generic.c update_amp(codec, nid, dir, idx, mask, val); val 974 sound/pci/hda/hda_generic.c int cidx, unsigned long val) val 982 sound/pci/hda/hda_generic.c if (get_amp_nid_(val)) val 984 sound/pci/hda/hda_generic.c knew->private_value = val; val 990 sound/pci/hda/hda_generic.c const char *sfx, int cidx, unsigned long val) val 994 sound/pci/hda/hda_generic.c if (!add_control(spec, type, name, cidx, val)) val 999 sound/pci/hda/hda_generic.c #define add_pb_vol_ctrl(spec, type, pfx, val) \ val 1000 sound/pci/hda/hda_generic.c add_control_with_pfx(spec, type, pfx, "Playback", "Volume", 0, val) val 1001 sound/pci/hda/hda_generic.c #define add_pb_sw_ctrl(spec, type, pfx, val) \ val 1002 sound/pci/hda/hda_generic.c add_control_with_pfx(spec, type, pfx, "Playback", "Switch", 0, val) val 1003 sound/pci/hda/hda_generic.c #define __add_pb_vol_ctrl(spec, type, pfx, cidx, val) \ val 1004 sound/pci/hda/hda_generic.c add_control_with_pfx(spec, type, pfx, "Playback", "Volume", cidx, val) val 1005 sound/pci/hda/hda_generic.c #define __add_pb_sw_ctrl(spec, type, pfx, cidx, val) \ val 1006 sound/pci/hda/hda_generic.c add_control_with_pfx(spec, type, pfx, "Playback", "Switch", cidx, val) val 1011 sound/pci/hda/hda_generic.c unsigned int val; val 1014 sound/pci/hda/hda_generic.c val = path->ctls[NID_PATH_VOL_CTL]; val 1015 sound/pci/hda/hda_generic.c if (!val) val 1017 sound/pci/hda/hda_generic.c val = amp_val_replace_channels(val, chs); val 1018 sound/pci/hda/hda_generic.c return __add_pb_vol_ctrl(codec->spec, HDA_CTL_WIDGET_VOL, pfx, cidx, val); val 1047 sound/pci/hda/hda_generic.c unsigned int val; val 1052 sound/pci/hda/hda_generic.c val = path->ctls[NID_PATH_MUTE_CTL]; val 1053 sound/pci/hda/hda_generic.c if (!val) val 1055 sound/pci/hda/hda_generic.c val = amp_val_replace_channels(val, chs); val 1056 sound/pci/hda/hda_generic.c if (get_amp_direction_(val) == HDA_INPUT) { val 1057 sound/pci/hda/hda_generic.c hda_nid_t nid = get_amp_nid_(val); val 1061 sound/pci/hda/hda_generic.c val |= nums << 19; val 1064 sound/pci/hda/hda_generic.c return __add_pb_sw_ctrl(codec->spec, type, pfx, cidx, val); val 1270 sound/pci/hda/hda_generic.c unsigned int val; val 1282 sound/pci/hda/hda_generic.c val = HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT); val 1284 sound/pci/hda/hda_generic.c val |= HDA_AMP_VAL_MIN_MUTE; val 1285 sound/pci/hda/hda_generic.c if (is_ctl_used(codec, val, NID_PATH_VOL_CTL)) val 1288 sound/pci/hda/hda_generic.c path->ctls[NID_PATH_VOL_CTL] = val; val 1296 sound/pci/hda/hda_generic.c val = HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT); val 1298 sound/pci/hda/hda_generic.c val = HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_INPUT); val 1299 sound/pci/hda/hda_generic.c if (is_ctl_used(codec, val, NID_PATH_MUTE_CTL)) val 1302 sound/pci/hda/hda_generic.c path->ctls[NID_PATH_MUTE_CTL] = val; val 1967 sound/pci/hda/hda_generic.c unsigned int val; val 2062 sound/pci/hda/hda_generic.c val = PIN_HP; val 2064 sound/pci/hda/hda_generic.c val = PIN_OUT; val 2065 sound/pci/hda/hda_generic.c set_pin_targets(codec, cfg->line_outs, cfg->line_out_pins, val); val 2069 sound/pci/hda/hda_generic.c val = spec->prefer_hp_amp ? PIN_HP : PIN_OUT; val 2071 sound/pci/hda/hda_generic.c cfg->speaker_pins, val); val 2489 sound/pci/hda/hda_generic.c unsigned int val = ucontrol->value.enumerated.item[0]; val 2491 sound/pci/hda/hda_generic.c if (val == spec->aamix_mode) val 2493 sound/pci/hda/hda_generic.c spec->aamix_mode = val; val 2495 sound/pci/hda/hda_generic.c update_aamix_paths(codec, val, spec->out_paths[0], val 2498 sound/pci/hda/hda_generic.c update_aamix_paths(codec, val, spec->hp_paths[0], val 2501 sound/pci/hda/hda_generic.c update_aamix_paths(codec, val, spec->speaker_paths[0], val 2546 sound/pci/hda/hda_generic.c unsigned int val; val 2553 sound/pci/hda/hda_generic.c val = snd_hda_codec_get_pin_target(codec, pin); val 2555 sound/pci/hda/hda_generic.c if (val & PIN_IN) val 2558 sound/pci/hda/hda_generic.c if (val & PIN_OUT) val 2563 sound/pci/hda/hda_generic.c val = snd_hda_get_default_vref(codec, pin); val 2567 sound/pci/hda/hda_generic.c if (val == AC_PINCTL_VREF_HIZ && spec->shared_mic_vref_pin) { val 2577 sound/pci/hda/hda_generic.c val |= PIN_IN; val 2579 sound/pci/hda/hda_generic.c val = PIN_HP; val 2580 sound/pci/hda/hda_generic.c set_pin_target(codec, pin, val, true); val 2668 sound/pci/hda/hda_generic.c unsigned int val; val 2670 sound/pci/hda/hda_generic.c val = ucontrol->value.enumerated.item[0] ? PIN_HP : PIN_OUT; val 2671 sound/pci/hda/hda_generic.c if (snd_hda_codec_get_pin_target(codec, nid) == val) val 2673 sound/pci/hda/hda_generic.c snd_hda_set_pin_ctl_cache(codec, nid, val); val 2832 sound/pci/hda/hda_generic.c unsigned int val, idx; val 2834 sound/pci/hda/hda_generic.c val = snd_hda_codec_get_pin_target(codec, nid); val 2835 sound/pci/hda/hda_generic.c idx = cvt_from_vref_idx(vref_caps, val & AC_PINCTL_VREFEN); val 2839 sound/pci/hda/hda_generic.c val &= ~AC_PINCTL_VREFEN; val 2840 sound/pci/hda/hda_generic.c val |= get_vref_idx(vref_caps, ucontrol->value.enumerated.item[0]); val 2841 sound/pci/hda/hda_generic.c snd_hda_set_pin_ctl_cache(codec, nid, val); val 2929 sound/pci/hda/hda_generic.c unsigned int val = snd_hda_codec_get_pin_target(codec, nid); val 2932 sound/pci/hda/hda_generic.c if (val & PIN_OUT) { val 2933 sound/pci/hda/hda_generic.c if (out_jacks > 1 && val == PIN_HP) val 2935 sound/pci/hda/hda_generic.c } else if (val & PIN_IN) { val 2939 sound/pci/hda/hda_generic.c val &= AC_PINCTL_VREFEN; val 2940 sound/pci/hda/hda_generic.c idx += cvt_from_vref_idx(vref_caps, val); val 2963 sound/pci/hda/hda_generic.c unsigned int val, oldval, idx; val 2972 sound/pci/hda/hda_generic.c val = idx ? PIN_HP : PIN_OUT; val 2974 sound/pci/hda/hda_generic.c val = PIN_HP; val 2979 sound/pci/hda/hda_generic.c val = snd_hda_codec_get_pin_target(codec, nid); val 2980 sound/pci/hda/hda_generic.c val &= ~(AC_PINCTL_VREFEN | PIN_HP); val 2981 sound/pci/hda/hda_generic.c val |= get_vref_idx(vref_caps, idx) | PIN_IN; val 2983 sound/pci/hda/hda_generic.c val = snd_hda_get_default_vref(codec, nid) | PIN_IN; val 2985 sound/pci/hda/hda_generic.c snd_hda_set_pin_ctl_cache(codec, nid, val); val 3313 sound/pci/hda/hda_generic.c unsigned int val; val 3330 sound/pci/hda/hda_generic.c val = PIN_IN; val 3332 sound/pci/hda/hda_generic.c val |= snd_hda_get_default_vref(codec, pin); val 3335 sound/pci/hda/hda_generic.c set_pin_target(codec, pin, val, false); val 3559 sound/pci/hda/hda_generic.c unsigned int val; val 3569 sound/pci/hda/hda_generic.c val = snd_hda_codec_get_pincfg(codec, nid); val 3570 sound/pci/hda/hda_generic.c return snd_hda_get_input_pin_attr(val) == INPUT_PIN_ATTR_INT; val 3824 sound/pci/hda/hda_generic.c unsigned int val = 0; val 3833 sound/pci/hda/hda_generic.c val = HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT); val 3837 sound/pci/hda/hda_generic.c val = HDA_COMPOSE_AMP_VAL(nid, 3, path->idx[depth], val 3843 sound/pci/hda/hda_generic.c return val; val 3858 sound/pci/hda/hda_generic.c unsigned int val; val 3874 sound/pci/hda/hda_generic.c val = look_for_boost_amp(codec, path); val 3875 sound/pci/hda/hda_generic.c if (!val) val 3882 sound/pci/hda/hda_generic.c spec->input_label_idxs[idx], val)) val 3885 sound/pci/hda/hda_generic.c path->ctls[NID_PATH_BOOST_CTL] = val; val 3903 sound/pci/hda/hda_generic.c unsigned int val; val 3907 sound/pci/hda/hda_generic.c val = 1; val 3910 sound/pci/hda/hda_generic.c val = 0; val 3913 sound/pci/hda/hda_generic.c val = !!spec->micmute_led.capture; val 3917 sound/pci/hda/hda_generic.c val = !spec->micmute_led.capture; val 3921 sound/pci/hda/hda_generic.c if (val == spec->micmute_led.led_value) val 3923 sound/pci/hda/hda_generic.c spec->micmute_led.led_value = val; val 4431 sound/pci/hda/hda_generic.c unsigned int val, oldval; val 4459 sound/pci/hda/hda_generic.c val = oldval & ~PIN_HP; val 4461 sound/pci/hda/hda_generic.c val = 0; val 4463 sound/pci/hda/hda_generic.c val |= oldval; val 4469 sound/pci/hda/hda_generic.c update_pin_ctl(codec, nid, val); val 4687 sound/pci/hda/hda_generic.c unsigned int val = 0; val 4689 sound/pci/hda/hda_generic.c val++; val 4691 sound/pci/hda/hda_generic.c val++; val 4693 sound/pci/hda/hda_generic.c ucontrol->value.enumerated.item[0] = val; val 166 sound/pci/hda/hda_intel.c static int param_set_xint(const char *val, const struct kernel_param *kp); val 404 sound/pci/hda/hda_intel.c unsigned char mask, unsigned char val) val 410 sound/pci/hda/hda_intel.c data |= (val & mask); val 483 sound/pci/hda/hda_intel.c u32 val; val 485 sound/pci/hda/hda_intel.c val = azx_readl(chip, VS_EM4L); val 486 sound/pci/hda/hda_intel.c val &= (0x3 << 20); val 487 sound/pci/hda/hda_intel.c azx_writel(chip, VS_EM4L, val); val 503 sound/pci/hda/hda_intel.c u32 val, t; val 506 sound/pci/hda/hda_intel.c val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); val 510 sound/pci/hda/hda_intel.c if (val & (1 << t)) val 521 sound/pci/hda/hda_intel.c u32 val; val 528 sound/pci/hda/hda_intel.c val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); val 529 sound/pci/hda/hda_intel.c val &= ~AZX_MLCTL_SPA; val 530 sound/pci/hda/hda_intel.c val |= state << AZX_MLCTL_SPA_SHIFT; val 531 sound/pci/hda/hda_intel.c writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); val 548 sound/pci/hda/hda_intel.c u32 val; val 552 sound/pci/hda/hda_intel.c val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); val 554 sound/pci/hda/hda_intel.c if ((val & ML_LCTL_SCF_MASK) != 0) val 561 sound/pci/hda/hda_intel.c if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != val 562 sound/pci/hda/hda_intel.c ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) val 572 sound/pci/hda/hda_intel.c val &= ~ML_LCTL_SCF_MASK; val 573 sound/pci/hda/hda_intel.c val |= intel_get_lctl_scf(chip); val 574 sound/pci/hda/hda_intel.c writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); val 586 sound/pci/hda/hda_intel.c u32 val; val 590 sound/pci/hda/hda_intel.c pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); val 591 sound/pci/hda/hda_intel.c val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; val 592 sound/pci/hda/hda_intel.c pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); val 596 sound/pci/hda/hda_intel.c pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); val 597 sound/pci/hda/hda_intel.c val = val | INTEL_HDA_CGCTL_MISCBDCGE; val 598 sound/pci/hda/hda_intel.c pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); val 940 sound/pci/hda/hda_intel.c static int param_set_xint(const char *val, const struct kernel_param *kp) val 945 sound/pci/hda/hda_intel.c int ret = param_set_int(val, kp); val 1653 sound/pci/hda/hda_intel.c u8 val; val 1654 sound/pci/hda/hda_intel.c pci_read_config_byte(chip->pci, 0x42, &val); val 1655 sound/pci/hda/hda_intel.c if (!(val & 0x80) && (chip->pci->revision == 0x30 || val 2198 sound/pci/hda/hda_intel.c int val = power_save; val 2205 sound/pci/hda/hda_intel.c if (q && val) { val 2208 sound/pci/hda/hda_intel.c val = 0; val 2212 sound/pci/hda/hda_intel.c snd_hda_set_power_save(&chip->bus, val * 1000); val 49 sound/pci/hda/hda_jack.c u32 val; val 57 sound/pci/hda/hda_jack.c val = snd_hda_codec_read(codec, nid, 0, val 60 sound/pci/hda/hda_jack.c val ^= AC_PINSENSE_PRESENCE; val 61 sound/pci/hda/hda_jack.c return val; val 120 sound/pci/hda/hda_local.h int ch, int dir, int idx, int mask, int val); val 122 sound/pci/hda/hda_local.h int dir, int idx, int mask, int val); val 124 sound/pci/hda/hda_local.h int direction, int idx, int mask, int val); val 126 sound/pci/hda/hda_local.h int dir, int idx, int mask, int val); val 282 sound/pci/hda/hda_local.h u32 val; val 402 sound/pci/hda/hda_local.h hda_nid_t pin, unsigned int val); val 404 sound/pci/hda/hda_local.h unsigned int val, bool cached); val 422 sound/pci/hda/hda_local.h snd_hda_set_pin_ctl(struct hda_codec *codec, hda_nid_t pin, unsigned int val) val 424 sound/pci/hda/hda_local.h return _snd_hda_set_pin_ctl(codec, pin, val, false); val 437 sound/pci/hda/hda_local.h unsigned int val) val 439 sound/pci/hda/hda_local.h return _snd_hda_set_pin_ctl(codec, pin, val, true); val 444 sound/pci/hda/hda_local.h unsigned int val); val 479 sound/pci/hda/hda_local.h hda_nid_t nid, u32 val) val 483 sound/pci/hda/hda_local.h codec->wcaps[nid - codec->core.start_nid] = val; val 137 sound/pci/hda/hda_proc.c unsigned int val; val 146 sound/pci/hda/hda_proc.c val = snd_hda_codec_read(codec, nid, 0, val 149 sound/pci/hda/hda_proc.c snd_iprintf(buffer, "0x%02x", val); val 151 sound/pci/hda/hda_proc.c val = snd_hda_codec_read(codec, nid, 0, val 154 sound/pci/hda/hda_proc.c snd_iprintf(buffer, " 0x%02x", val); val 311 sound/pci/hda/hda_proc.c unsigned int caps, val; val 363 sound/pci/hda/hda_proc.c val = snd_hda_codec_read(codec, nid, 0, val 365 sound/pci/hda/hda_proc.c snd_iprintf(buffer, " EAPD 0x%x:", val); val 366 sound/pci/hda/hda_proc.c if (val & AC_EAPDBTL_BALANCED) val 368 sound/pci/hda/hda_proc.c if (val & AC_EAPDBTL_EAPD) val 370 sound/pci/hda/hda_proc.c if (val & AC_EAPDBTL_LR_SWAP) val 589 sound/pci/hda/hda_proc.c unsigned int val; val 591 sound/pci/hda/hda_proc.c val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PROC_COEF, val 593 sound/pci/hda/hda_proc.c snd_iprintf(buffer, " Coeff 0x%02x: 0x%04x\n", i, val); val 26 sound/pci/hda/hda_sysfs.c const char *val; /* contained in the same alloc as key */ val 172 sound/pci/hda/hda_sysfs.c unsigned long val; \ val 173 sound/pci/hda/hda_sysfs.c int err = kstrtoul(buf, 0, &val); \ val 176 sound/pci/hda/hda_sysfs.c codec->field = val; \ val 276 sound/pci/hda/hda_sysfs.c "%s = %s\n", hint->key, hint->val); val 311 sound/pci/hda/hda_sysfs.c char *key, *val; val 324 sound/pci/hda/hda_sysfs.c val = strchr(key, '='); val 325 sound/pci/hda/hda_sysfs.c if (!val) { val 329 sound/pci/hda/hda_sysfs.c *val++ = 0; val 330 sound/pci/hda/hda_sysfs.c val = skip_spaces(val); val 332 sound/pci/hda/hda_sysfs.c remove_trail_spaces(val); val 339 sound/pci/hda/hda_sysfs.c hint->val = val; val 349 sound/pci/hda/hda_sysfs.c hint->val = val; val 424 sound/pci/hda/hda_sysfs.c return hint ? hint->val : NULL; val 476 sound/pci/hda/hda_sysfs.c unsigned long val; val 483 sound/pci/hda/hda_sysfs.c else if (kstrtoul(p, 0, &val)) val 486 sound/pci/hda/hda_sysfs.c *valp = val; val 598 sound/pci/hda/hda_sysfs.c unsigned long val; \ val 599 sound/pci/hda/hda_sysfs.c if (!kstrtoul(buf, 0, &val)) \ val 600 sound/pci/hda/hda_sysfs.c (*codecp)->core.name = val; \ val 482 sound/pci/hda/patch_analog.c unsigned int val = ucontrol->value.enumerated.item[0]; val 486 sound/pci/hda/patch_analog.c if (val >= num_conns) val 488 sound/pci/hda/patch_analog.c if (spec->cur_smux == val) val 490 sound/pci/hda/patch_analog.c spec->cur_smux = val; val 492 sound/pci/hda/patch_analog.c AC_VERB_SET_CONNECT_SEL, val); val 757 sound/pci/hda/patch_analog.c unsigned int val = ucontrol->value.enumerated.item[0]; val 761 sound/pci/hda/patch_analog.c if (val >= num_conns) val 763 sound/pci/hda/patch_analog.c if (spec->cur_smux == val) val 771 sound/pci/hda/patch_analog.c path = snd_hda_get_path_from_idx(codec, spec->smux_paths[val]); val 774 sound/pci/hda/patch_analog.c spec->cur_smux = val; val 704 sound/pci/hda/patch_ca0132.c unsigned int val; val 709 sound/pci/hda/patch_ca0132.c .val = 0xa0 val 712 sound/pci/hda/patch_ca0132.c .val = 0xc0 val 715 sound/pci/hda/patch_ca0132.c .val = 0x80 val 1448 sound/pci/hda/patch_ca0132.c unsigned int val; val 1452 sound/pci/hda/patch_ca0132.c val = (flag_bit << 7) | (flag_id); val 1454 sound/pci/hda/patch_ca0132.c VENDOR_CHIPIO_FLAG_SET, val); val 1464 sound/pci/hda/patch_ca0132.c int val; val 1467 sound/pci/hda/patch_ca0132.c val = (param_val << 5) | (param_id); val 1469 sound/pci/hda/patch_ca0132.c VENDOR_CHIPIO_PARAM_SET, val); val 1490 sound/pci/hda/patch_ca0132.c int val; val 1493 sound/pci/hda/patch_ca0132.c val = (param_val << 5) | (param_id); val 1495 sound/pci/hda/patch_ca0132.c VENDOR_CHIPIO_PARAM_SET, val); val 2475 sound/pci/hda/patch_ca0132.c u8 val; val 2481 sound/pci/hda/patch_ca0132.c val = start_device << 6; val 2482 sound/pci/hda/patch_ca0132.c val |= (ports_per_channel - 1) << 4; val 2483 sound/pci/hda/patch_ca0132.c val |= num_chans - 1; val 2487 sound/pci/hda/patch_ca0132.c val); val 4153 sound/pci/hda/patch_ca0132.c static int ae5_headphone_gain_set(struct hda_codec *codec, long val); val 4154 sound/pci/hda/patch_ca0132.c static int zxr_headphone_gain_set(struct hda_codec *codec, long val); val 4155 sound/pci/hda/patch_ca0132.c static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); val 4473 sound/pci/hda/patch_ca0132.c static int ca0132_mic_boost_set(struct hda_codec *codec, long val); val 4477 sound/pci/hda/patch_ca0132.c static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); val 4482 sound/pci/hda/patch_ca0132.c static int ca0132_set_vipsource(struct hda_codec *codec, int val) val 4492 sound/pci/hda/patch_ca0132.c (val == 0)) { val 4514 sound/pci/hda/patch_ca0132.c chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); val 4520 sound/pci/hda/patch_ca0132.c static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) val 4535 sound/pci/hda/patch_ca0132.c (val == 0) || spec->in_enum_val == REAR_LINE_IN) { val 4576 sound/pci/hda/patch_ca0132.c chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); val 4850 sound/pci/hda/patch_ca0132.c static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) val 4865 sound/pci/hda/patch_ca0132.c val = 0; val 4867 sound/pci/hda/patch_ca0132.c val = 0; val 4874 sound/pci/hda/patch_ca0132.c val = 0; val 4878 sound/pci/hda/patch_ca0132.c val = 0; val 4889 sound/pci/hda/patch_ca0132.c val = 1; val 4918 sound/pci/hda/patch_ca0132.c val = 0; val 4922 sound/pci/hda/patch_ca0132.c nid, val); val 4924 sound/pci/hda/patch_ca0132.c on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; val 5014 sound/pci/hda/patch_ca0132.c static int ca0132_mic_boost_set(struct hda_codec *codec, long val) val 5019 sound/pci/hda/patch_ca0132.c if (val) /* on */ val 5029 sound/pci/hda/patch_ca0132.c static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) val 5035 sound/pci/hda/patch_ca0132.c HDA_INPUT, 0, HDA_AMP_VOLMASK, val); val 5039 sound/pci/hda/patch_ca0132.c static int ae5_headphone_gain_set(struct hda_codec *codec, long val) val 5045 sound/pci/hda/patch_ca0132.c ae5_headphone_gain_presets[val].vals[i]); val 5053 sound/pci/hda/patch_ca0132.c static int zxr_headphone_gain_set(struct hda_codec *codec, long val) val 5055 sound/pci/hda/patch_ca0132.c ca0113_mmio_gpio_set(codec, 1, val); val 5426 sound/pci/hda/patch_ca0132.c ae5_filter_presets[sel].val); val 6742 sound/pci/hda/patch_ca0132.c u8 val; val 6754 sound/pci/hda/patch_ca0132.c val = spec->dmic_ctl; val 6755 sound/pci/hda/patch_ca0132.c val |= 0x80; val 6757 sound/pci/hda/patch_ca0132.c VENDOR_CHIPIO_DMIC_CTL_SET, val); val 6766 sound/pci/hda/patch_ca0132.c val = spec->dmic_ctl; val 6768 sound/pci/hda/patch_ca0132.c val &= 0x5f; val 6770 sound/pci/hda/patch_ca0132.c VENDOR_CHIPIO_DMIC_CTL_SET, val); val 6785 sound/pci/hda/patch_ca0132.c u8 val; val 6796 sound/pci/hda/patch_ca0132.c val = 0x01; val 6798 sound/pci/hda/patch_ca0132.c VENDOR_CHIPIO_DMIC_MCLK_SET, val); val 6806 sound/pci/hda/patch_ca0132.c val = 0x83; val 6808 sound/pci/hda/patch_ca0132.c VENDOR_CHIPIO_DMIC_PIN_SET, val); val 6818 sound/pci/hda/patch_ca0132.c val = 0x33; val 6820 sound/pci/hda/patch_ca0132.c val = 0x23; val 6822 sound/pci/hda/patch_ca0132.c spec->dmic_ctl = val; val 6824 sound/pci/hda/patch_ca0132.c VENDOR_CHIPIO_DMIC_CTL_SET, val); val 177 sound/pci/hda/patch_cirrus.c unsigned int val; val 178 sound/pci/hda/patch_cirrus.c val = snd_hda_codec_get_pincfg(codec, nid); val 179 sound/pci/hda/patch_cirrus.c return (get_defcfg_connect(val) != AC_JACK_PORT_NONE); val 319 sound/pci/hda/patch_conexant.c #define update_mic_pin(codec, nid, val) \ val 321 sound/pci/hda/patch_conexant.c AC_VERB_SET_PIN_WIDGET_CONTROL, val) val 335 sound/pci/hda/patch_conexant.c int ch, val; val 338 sound/pci/hda/patch_conexant.c val = AC_AMP_SET_OUTPUT | val 341 sound/pci/hda/patch_conexant.c val |= snd_hda_codec_amp_read(codec, 0x17, ch, HDA_OUTPUT, 0); val 343 sound/pci/hda/patch_conexant.c AC_VERB_SET_AMP_GAIN_MUTE, val); val 350 sound/pci/hda/patch_conexant.c int cur_input, val; val 390 sound/pci/hda/patch_conexant.c val = olpc_xo_dc_bias.items[spec->dc_input_bias].index; val 392 sound/pci/hda/patch_conexant.c val = 0; val 393 sound/pci/hda/patch_conexant.c update_mic_pin(codec, 0x1a, val); val 429 sound/pci/hda/patch_hdmi.c int val; val 431 sound/pci/hda/patch_hdmi.c val = snd_hda_codec_read(codec, pin_nid, 0, val 434 sound/pci/hda/patch_hdmi.c *packet_index = val >> 5; val 435 sound/pci/hda/patch_hdmi.c *byte_index = val & 0x1f; val 442 sound/pci/hda/patch_hdmi.c int val; val 444 sound/pci/hda/patch_hdmi.c val = (packet_index << 5) | (byte_index & 0x1f); val 446 sound/pci/hda/patch_hdmi.c snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); val 450 sound/pci/hda/patch_hdmi.c unsigned char val) val 452 sound/pci/hda/patch_hdmi.c snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); val 644 sound/pci/hda/patch_hdmi.c u8 val; val 653 sound/pci/hda/patch_hdmi.c val = snd_hda_codec_read(codec, pin_nid, 0, val 655 sound/pci/hda/patch_hdmi.c if (val != dip[i]) val 2453 sound/pci/hda/patch_hdmi.c unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); val 2455 sound/pci/hda/patch_hdmi.c AC_VERB_SET_UNSOLICITED_ENABLE, val); val 135 sound/pci/hda/patch_realtek.c unsigned int val; val 138 sound/pci/hda/patch_realtek.c val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PROC_COEF, 0); val 139 sound/pci/hda/patch_realtek.c return val; val 159 sound/pci/hda/patch_realtek.c unsigned int val = alc_read_coefex_idx(codec, nid, coef_idx); val 161 sound/pci/hda/patch_realtek.c if (val != -1) val 163 sound/pci/hda/patch_realtek.c (val & ~mask) | bits_set); val 184 sound/pci/hda/patch_realtek.c unsigned short val; val 188 sound/pci/hda/patch_realtek.c { .nid = (_nid), .idx = (_idx), .mask = (_mask), .val = (_val) } val 198 sound/pci/hda/patch_realtek.c alc_write_coefex_idx(codec, fw->nid, fw->idx, fw->val); val 201 sound/pci/hda/patch_realtek.c fw->mask, fw->val); val 316 sound/pci/hda/patch_realtek.c unsigned int val; val 326 sound/pci/hda/patch_realtek.c val = snd_hda_codec_read(codec, jack->nid, 0, val 328 sound/pci/hda/patch_realtek.c val &= HDA_AMP_VOLMASK; val 329 sound/pci/hda/patch_realtek.c uctl->value.integer.value[0] = val; val 330 sound/pci/hda/patch_realtek.c uctl->value.integer.value[1] = val; val 1978 sound/pci/hda/patch_realtek.c unsigned int val = snd_hda_codec_get_pincfg(codec, nids[i]); val 1979 sound/pci/hda/patch_realtek.c if (get_defcfg_device(val) != AC_JACK_HP_OUT) val 1981 sound/pci/hda/patch_realtek.c val = snd_hda_codec_get_pin_target(codec, nids[i]); val 1982 sound/pci/hda/patch_realtek.c val |= AC_PINCTL_VREF_80; val 1983 sound/pci/hda/patch_realtek.c snd_hda_set_pin_ctl(codec, nids[i], val); val 1996 sound/pci/hda/patch_realtek.c unsigned int val; val 1997 sound/pci/hda/patch_realtek.c val = snd_hda_codec_get_pin_target(codec, nids[i]); val 1998 sound/pci/hda/patch_realtek.c val |= AC_PINCTL_VREF_50; val 1999 sound/pci/hda/patch_realtek.c snd_hda_set_pin_ctl(codec, nids[i], val); val 3609 sound/pci/hda/patch_realtek.c int i, val; val 3627 sound/pci/hda/patch_realtek.c val = alc_read_coefex_idx(codec, 0x58, 0x01); val 3628 sound/pci/hda/patch_realtek.c for (i = 0; i < 20 && val & 0x0080; i++) { val 3630 sound/pci/hda/patch_realtek.c val = alc_read_coefex_idx(codec, 0x58, 0x01); val 3651 sound/pci/hda/patch_realtek.c unsigned int val) val 3654 sound/pci/hda/patch_realtek.c snd_hda_codec_write(codec, 0x51, 0, AC_VERB_SET_PROC_COEF, val & 0xffff); /* LSB */ val 3655 sound/pci/hda/patch_realtek.c snd_hda_codec_write(codec, 0x51, 0, AC_VERB_SET_PROC_COEF, val >> 16); /* MSB */ val 3660 sound/pci/hda/patch_realtek.c unsigned int val; val 3663 sound/pci/hda/patch_realtek.c val = snd_hda_codec_read(codec, 0x51, 0, AC_VERB_GET_PROC_COEF, 0) val 3665 sound/pci/hda/patch_realtek.c val |= snd_hda_codec_read(codec, 0x51, 0, AC_VERB_GET_PROC_COEF, 0) val 3667 sound/pci/hda/patch_realtek.c return val; val 3672 sound/pci/hda/patch_realtek.c unsigned int val; val 3681 sound/pci/hda/patch_realtek.c val = alc5505_coef_get(codec, 0x6220); val 3682 sound/pci/hda/patch_realtek.c alc5505_coef_set(codec, 0x6220, (val | 0x3000)); /* switch Ringbuffer clock to DBUS clock */ val 3697 sound/pci/hda/patch_realtek.c unsigned int val; val 3715 sound/pci/hda/patch_realtek.c val = alc5505_coef_get(codec, 0x6200) >> 16; /* Read revision ID */ val 3716 sound/pci/hda/patch_realtek.c if (val <= 3) val 4823 sound/pci/hda/patch_realtek.c int val; val 4895 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x50); val 4896 sound/pci/hda/patch_realtek.c if (val & (1 << 12)) { val 4927 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x45); val 4928 sound/pci/hda/patch_realtek.c if (val & (1 << 9)) val 5041 sound/pci/hda/patch_realtek.c int val; val 5086 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x46); val 5087 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x0070) == 0x0070; val 5103 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x46); val 5104 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x0070) == 0x0070; val 5120 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x46); val 5121 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x00f0) == 0x00f0; val 5127 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x46); val 5128 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x0070) == 0x0070; val 5138 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x50); val 5139 sound/pci/hda/patch_realtek.c if (val & (1 << 12)) { val 5143 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x50); val 5144 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x0070) == 0x0070; val 5149 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x50); val 5150 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x0070) == 0x0070; val 5163 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x50); val 5164 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x0070) == 0x0070; val 5169 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x6c); val 5170 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x001c) == 0x001c; val 5175 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x46); val 5176 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x0070) == 0x0070; val 5181 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0xbe); val 5182 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x1c02) == 0x1c02; val 5198 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x45); val 5199 sound/pci/hda/patch_realtek.c if (val & (1 << 9)) { val 5203 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x46); val 5204 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x00f0) == 0x00f0; val 5209 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x46); val 5210 sound/pci/hda/patch_realtek.c is_ctia = (val & 0x00f0) == 0x00f0; val 8190 sound/pci/hda/patch_realtek.c int val; val 8211 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0xd); val 8212 sound/pci/hda/patch_realtek.c if (val != -1 && (val & 0x0c00) >> 10 != 0x1) { val 8214 sound/pci/hda/patch_realtek.c alc_write_coef_idx(codec, 0xd, val | (1<<10)); val 8216 sound/pci/hda/patch_realtek.c val = alc_read_coef_idx(codec, 0x17); val 8217 sound/pci/hda/patch_realtek.c if (val != -1 && (val & 0x01c0) >> 6 != 0x4) { val 8219 sound/pci/hda/patch_realtek.c alc_write_coef_idx(codec, 0x17, val | (1<<7)); val 8438 sound/pci/hda/patch_realtek.c unsigned int val; val 8442 sound/pci/hda/patch_realtek.c val = snd_hda_codec_get_pin_target(codec, 0x0f); val 8443 sound/pci/hda/patch_realtek.c if (!(val & (AC_PINCTL_IN_EN | AC_PINCTL_OUT_EN))) val 8444 sound/pci/hda/patch_realtek.c val |= AC_PINCTL_IN_EN; val 8445 sound/pci/hda/patch_realtek.c val |= AC_PINCTL_VREF_50; val 8446 sound/pci/hda/patch_realtek.c snd_hda_set_pin_ctl(codec, 0x0f, val); val 65 sound/pci/hda/patch_si3054.c #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val)) val 66 sound/pci/hda/patch_si3054.c #define SET_REG_CACHE(codec,reg,val) \ val 67 sound/pci/hda/patch_si3054.c snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val) val 80 sound/pci/hda/patch_si3054.c #define PRIVATE_REG(val) ((val>>16)&0xffff) val 81 sound/pci/hda/patch_si3054.c #define PRIVATE_MASK(val) (val&0xffff) val 141 sound/pci/hda/patch_si3054.c u16 val; val 144 sound/pci/hda/patch_si3054.c val = GET_REG(codec, SI3054_LINE_LEVEL); val 145 sound/pci/hda/patch_si3054.c val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)); val 146 sound/pci/hda/patch_si3054.c val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)); val 147 sound/pci/hda/patch_si3054.c SET_REG(codec, SI3054_LINE_LEVEL, val); val 209 sound/pci/hda/patch_si3054.c u16 val; val 224 sound/pci/hda/patch_si3054.c val = GET_REG(codec, SI3054_EXTENDED_MID); val 225 sound/pci/hda/patch_si3054.c } while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--); val 227 sound/pci/hda/patch_si3054.c if((val&SI3054_MEI_READY) != SI3054_MEI_READY) { val 228 sound/pci/hda/patch_si3054.c codec_err(codec, "si3054: cannot initialize. EXT MID = %04x\n", val); val 396 sound/pci/hda/patch_sigmatel.c static void stac_vmaster_hook(void *private_data, int val) val 398 sound/pci/hda/patch_sigmatel.c stac_update_led_status(private_data, val); val 414 sound/pci/hda/patch_sigmatel.c unsigned int val = spec->gpio_data; val 416 sound/pci/hda/patch_sigmatel.c val &= ~spec->eapd_mask; val 418 sound/pci/hda/patch_sigmatel.c val |= spec->eapd_mask; val 419 sound/pci/hda/patch_sigmatel.c if (spec->gpio_data != val) { val 420 sound/pci/hda/patch_sigmatel.c spec->gpio_data = val; val 422 sound/pci/hda/patch_sigmatel.c val); val 431 sound/pci/hda/patch_sigmatel.c unsigned int idx, val; val 442 sound/pci/hda/patch_sigmatel.c val = spec->power_map_bits; val 444 sound/pci/hda/patch_sigmatel.c val &= ~idx; val 446 sound/pci/hda/patch_sigmatel.c val |= idx; val 449 sound/pci/hda/patch_sigmatel.c if (val != spec->power_map_bits) { val 450 sound/pci/hda/patch_sigmatel.c spec->power_map_bits = val; val 453 sound/pci/hda/patch_sigmatel.c AC_VERB_IDT_SET_POWER_MAP, val); val 540 sound/pci/hda/patch_sigmatel.c int val; val 554 sound/pci/hda/patch_sigmatel.c val = snd_hda_get_bool_hint(codec, "eapd_switch"); val 555 sound/pci/hda/patch_sigmatel.c if (val >= 0) val 556 sound/pci/hda/patch_sigmatel.c spec->eapd_switch = val; val 584 sound/pci/hda/patch_sigmatel.c unsigned int val, idx_val; val 588 sound/pci/hda/patch_sigmatel.c val = spec->aloopback | idx_val; val 590 sound/pci/hda/patch_sigmatel.c val = spec->aloopback & ~idx_val; val 591 sound/pci/hda/patch_sigmatel.c if (spec->aloopback == val) val 594 sound/pci/hda/patch_sigmatel.c spec->aloopback = val; val 233 sound/pci/hda/patch_via.c bool val = !!ucontrol->value.enumerated.item[0]; val 235 sound/pci/hda/patch_via.c if (val == spec->gen.power_down_unused) val 238 sound/pci/hda/patch_via.c spec->gen.power_down_unused = val; val 472 sound/pci/hda/patch_via.c int val; val 476 sound/pci/hda/patch_via.c val = !!ucontrol->value.integer.value[0]; val 477 sound/pci/hda/patch_via.c if (spec->vt1708_jack_detect == val) val 479 sound/pci/hda/patch_via.c spec->vt1708_jack_detect = val; val 19 sound/pci/ice1712/amp.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) val 22 sound/pci/ice1712/amp.c cval = (reg << 9) | val; val 103 sound/pci/ice1712/aureon.c unsigned char val = 0; val 141 sound/pci/ice1712/aureon.c val = dev; val 144 sound/pci/ice1712/aureon.c val = reg; val 147 sound/pci/ice1712/aureon.c val = data; val 154 sound/pci/ice1712/aureon.c if (val & (1 << i)) val 230 sound/pci/ice1712/aureon.c unsigned short val) val 248 sound/pci/ice1712/aureon.c tmp |= val & AUREON_AC97_DATA_MASK; val 260 sound/pci/ice1712/aureon.c tmp |= (val >> 8) & AUREON_AC97_DATA_MASK; val 280 sound/pci/ice1712/aureon.c spec->stac9744[(reg & 0x7F) >> 1] = val; val 580 sound/pci/ice1712/aureon.c unsigned char val; val 582 sound/pci/ice1712/aureon.c aureon_spi_read(ice, AUREON_CS8415_CS, 0x21, 8, &val, 1); val 583 sound/pci/ice1712/aureon.c return val; val 594 sound/pci/ice1712/aureon.c unsigned char val) val 596 sound/pci/ice1712/aureon.c aureon_spi_write(ice, AUREON_CS8415_CS, 0x200000 | (reg << 8) | val, 24); val 612 sound/pci/ice1712/aureon.c static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val) val 618 sound/pci/ice1712/aureon.c (reg << 9) | (val & 0x1ff), 16); val 624 sound/pci/ice1712/aureon.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) val 626 sound/pci/ice1712/aureon.c wm_put_nocache(ice, reg, val); val 628 sound/pci/ice1712/aureon.c ice->akm[0].images[reg] = val >> 8; val 629 sound/pci/ice1712/aureon.c ice->akm[0].images[reg + 1] = val; val 871 sound/pci/ice1712/aureon.c int val = (spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1; val 872 sound/pci/ice1712/aureon.c if (ucontrol->value.integer.value[i] != val) { val 911 sound/pci/ice1712/aureon.c int val = (spec->master[i] & WM_VOL_MUTE) ? 0 : 1; val 912 sound/pci/ice1712/aureon.c if (ucontrol->value.integer.value[i] != val) { val 945 sound/pci/ice1712/aureon.c unsigned short val; val 948 sound/pci/ice1712/aureon.c val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff; val 949 sound/pci/ice1712/aureon.c val = val > PCM_MIN ? (val - PCM_MIN) : 0; val 950 sound/pci/ice1712/aureon.c ucontrol->value.integer.value[0] = val; val 984 sound/pci/ice1712/aureon.c unsigned short val; val 989 sound/pci/ice1712/aureon.c val = wm_get(ice, WM_ADC_GAIN + i); val 990 sound/pci/ice1712/aureon.c ucontrol->value.integer.value[i] = ~val>>5 & 0x1; val 1098 sound/pci/ice1712/aureon.c unsigned short val; val 1101 sound/pci/ice1712/aureon.c val = wm_get(ice, WM_ADC_MUX); val 1102 sound/pci/ice1712/aureon.c ucontrol->value.enumerated.item[0] = val & 7; val 1103 sound/pci/ice1712/aureon.c ucontrol->value.enumerated.item[1] = (val >> 4) & 7; val 204 sound/pci/ice1712/delta.c unsigned int val; val 207 sound/pci/ice1712/delta.c val = snd_cs8403_encode_spdif_bits(&ucontrol->value.iec958); val 209 sound/pci/ice1712/delta.c change = ice->spdif.cs8403_bits != val; val 210 sound/pci/ice1712/delta.c ice->spdif.cs8403_bits = val; val 213 sound/pci/ice1712/delta.c snd_ice1712_delta_cs8403_spdif_write(ice, val); val 227 sound/pci/ice1712/delta.c unsigned int val; val 230 sound/pci/ice1712/delta.c val = snd_cs8403_encode_spdif_bits(&ucontrol->value.iec958); val 232 sound/pci/ice1712/delta.c change = ice->spdif.cs8403_stream_bits != val; val 233 sound/pci/ice1712/delta.c ice->spdif.cs8403_stream_bits = val; val 236 sound/pci/ice1712/delta.c snd_ice1712_delta_cs8403_spdif_write(ice, val); val 356 sound/pci/ice1712/delta.c unsigned char val; val 358 sound/pci/ice1712/delta.c val = (rate > 48000) ? 0x65 : 0x60; val 359 sound/pci/ice1712/delta.c if (snd_akm4xxx_get(ak, 0, 0x02) != val || val 360 sound/pci/ice1712/delta.c snd_akm4xxx_get(ak, 1, 0x02) != val) { val 362 sound/pci/ice1712/delta.c snd_akm4xxx_write(ak, 0, 0x02, val); val 363 sound/pci/ice1712/delta.c snd_akm4xxx_write(ak, 1, 0x02, val); val 259 sound/pci/ice1712/ews.c unsigned int val; val 262 sound/pci/ice1712/ews.c val = snd_cs8404_encode_spdif_bits(&ucontrol->value.iec958); val 264 sound/pci/ice1712/ews.c change = ice->spdif.cs8403_bits != val; val 265 sound/pci/ice1712/ews.c ice->spdif.cs8403_bits = val; val 268 sound/pci/ice1712/ews.c snd_ice1712_ews_cs8404_spdif_write(ice, val); val 282 sound/pci/ice1712/ews.c unsigned int val; val 285 sound/pci/ice1712/ews.c val = snd_cs8404_encode_spdif_bits(&ucontrol->value.iec958); val 287 sound/pci/ice1712/ews.c change = ice->spdif.cs8403_stream_bits != val; val 288 sound/pci/ice1712/ews.c ice->spdif.cs8403_stream_bits = val; val 291 sound/pci/ice1712/ews.c snd_ice1712_ews_cs8404_spdif_write(ice, val); val 587 sound/pci/ice1712/ews.c int val, nval; val 593 sound/pci/ice1712/ews.c val = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA); val 594 sound/pci/ice1712/ews.c nval |= val & ~mask; val 597 sound/pci/ice1712/ews.c return val != nval; val 137 sound/pci/ice1712/ice1712.c unsigned short val) val 152 sound/pci/ice1712/ice1712.c outw(val, ICEREG(ice, AC97_DATA)); val 191 sound/pci/ice1712/ice1712.c unsigned short val) val 206 sound/pci/ice1712/ice1712.c outw(val, ICEMT(ice, AC97_DATA)); val 256 sound/pci/ice1712/ice1712.c unsigned char val, nval; val 259 sound/pci/ice1712/ice1712.c val = inb(ICEMT(ice, MONITOR_ROUTECTRL)); val 260 sound/pci/ice1712/ice1712.c nval = val & ~ICE1712_ROUTE_AC97; val 265 sound/pci/ice1712/ice1712.c return val != nval; val 307 sound/pci/ice1712/ice1712.c static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val) val 309 sound/pci/ice1712/ice1712.c snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val); val 326 sound/pci/ice1712/ice1712.c unsigned char val, nval; val 334 sound/pci/ice1712/ice1712.c if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) { val 338 sound/pci/ice1712/ice1712.c nval = val & 0xf0; val 343 sound/pci/ice1712/ice1712.c if (val != nval) { val 991 sound/pci/ice1712/ice1712.c unsigned char val, old; val 995 sound/pci/ice1712/ice1712.c case 8000: val = 6; break; val 996 sound/pci/ice1712/ice1712.c case 9600: val = 3; break; val 997 sound/pci/ice1712/ice1712.c case 11025: val = 10; break; val 998 sound/pci/ice1712/ice1712.c case 12000: val = 2; break; val 999 sound/pci/ice1712/ice1712.c case 16000: val = 5; break; val 1000 sound/pci/ice1712/ice1712.c case 22050: val = 9; break; val 1001 sound/pci/ice1712/ice1712.c case 24000: val = 1; break; val 1002 sound/pci/ice1712/ice1712.c case 32000: val = 4; break; val 1003 sound/pci/ice1712/ice1712.c case 44100: val = 8; break; val 1004 sound/pci/ice1712/ice1712.c case 48000: val = 0; break; val 1005 sound/pci/ice1712/ice1712.c case 64000: val = 15; break; val 1006 sound/pci/ice1712/ice1712.c case 88200: val = 11; break; val 1007 sound/pci/ice1712/ice1712.c case 96000: val = 7; break; val 1010 sound/pci/ice1712/ice1712.c val = 0; val 1027 sound/pci/ice1712/ice1712.c if (!force && old == val) val 1031 sound/pci/ice1712/ice1712.c outb(val, ICEMT(ice, RATE)); val 1279 sound/pci/ice1712/ice1712.c unsigned short val = 0; val 1281 sound/pci/ice1712/ice1712.c val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f; val 1282 sound/pci/ice1712/ice1712.c val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8; val 1284 sound/pci/ice1712/ice1712.c outw(val, ICEMT(ice, MONITOR_VOLUME)); val 1770 sound/pci/ice1712/ice1712.c unsigned int val, nval; val 1776 sound/pci/ice1712/ice1712.c val = snd_ice1712_gpio_read(ice); val 1777 sound/pci/ice1712/ice1712.c nval |= val & ~mask; val 1778 sound/pci/ice1712/ice1712.c if (val != nval) val 1781 sound/pci/ice1712/ice1712.c return val != nval; val 1816 sound/pci/ice1712/ice1712.c unsigned char val; val 1822 sound/pci/ice1712/ice1712.c val = xlate[inb(ICEMT(ice, RATE)) & 15]; val 1823 sound/pci/ice1712/ice1712.c if (val == 255) { val 1825 sound/pci/ice1712/ice1712.c val = 0; val 1827 sound/pci/ice1712/ice1712.c ucontrol->value.enumerated.item[0] = val; val 1897 sound/pci/ice1712/ice1712.c int val; val 1903 sound/pci/ice1712/ice1712.c for (val = 0; val < 13; val++) { val 1904 sound/pci/ice1712/ice1712.c if (xrate[val] == PRO_RATE_DEFAULT) val 1908 sound/pci/ice1712/ice1712.c ucontrol->value.enumerated.item[0] = val; val 2021 sound/pci/ice1712/ice1712.c unsigned int val, cval; val 2024 sound/pci/ice1712/ice1712.c val = inw(ICEMT(ice, ROUTE_PSDOUT03)); val 2028 sound/pci/ice1712/ice1712.c val >>= ((idx % 2) * 8) + ((idx / 2) * 2); val 2029 sound/pci/ice1712/ice1712.c val &= 3; val 2031 sound/pci/ice1712/ice1712.c if (val == 1 && idx < 2) val 2033 sound/pci/ice1712/ice1712.c else if (val == 2) val 2035 sound/pci/ice1712/ice1712.c else if (val == 3) val 2048 sound/pci/ice1712/ice1712.c unsigned int val, old_val, nval; val 2061 sound/pci/ice1712/ice1712.c val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03)); val 2062 sound/pci/ice1712/ice1712.c val &= ~(0x03 << shift); val 2063 sound/pci/ice1712/ice1712.c val |= nval << shift; val 2064 sound/pci/ice1712/ice1712.c change = val != old_val; val 2066 sound/pci/ice1712/ice1712.c outw(val, ICEMT(ice, ROUTE_PSDOUT03)); val 2073 sound/pci/ice1712/ice1712.c val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE)); val 2077 sound/pci/ice1712/ice1712.c val &= ~(0x07 << shift); val 2078 sound/pci/ice1712/ice1712.c val |= nval << shift; val 2081 sound/pci/ice1712/ice1712.c val &= ~(0x08 << shift); val 2082 sound/pci/ice1712/ice1712.c val |= nval << shift; val 2084 sound/pci/ice1712/ice1712.c if (val != old_val) { val 2086 sound/pci/ice1712/ice1712.c outl(val, ICEMT(ice, ROUTE_CAPTURE)); val 2097 sound/pci/ice1712/ice1712.c unsigned int val, cval; val 2098 sound/pci/ice1712/ice1712.c val = inw(ICEMT(ice, ROUTE_SPDOUT)); val 2099 sound/pci/ice1712/ice1712.c cval = (val >> (idx * 4 + 8)) & 0x0f; val 2100 sound/pci/ice1712/ice1712.c val = (val >> (idx * 2)) & 0x03; val 2101 sound/pci/ice1712/ice1712.c if (val == 1) val 2103 sound/pci/ice1712/ice1712.c else if (val == 2) val 2105 sound/pci/ice1712/ice1712.c else if (val == 3) val 2118 sound/pci/ice1712/ice1712.c unsigned int val, old_val, nval; val 2122 sound/pci/ice1712/ice1712.c val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT)); val 2132 sound/pci/ice1712/ice1712.c val &= ~(0x03 << shift); val 2133 sound/pci/ice1712/ice1712.c val |= nval << shift; val 2137 sound/pci/ice1712/ice1712.c val &= ~(0x07 << shift); val 2138 sound/pci/ice1712/ice1712.c val |= nval << shift; val 2141 sound/pci/ice1712/ice1712.c val &= ~(0x08 << shift); val 2142 sound/pci/ice1712/ice1712.c val |= nval << shift; val 2144 sound/pci/ice1712/ice1712.c change = val != old_val; val 2146 sound/pci/ice1712/ice1712.c outw(val, ICEMT(ice, ROUTE_SPDOUT)); val 410 sound/pci/ice1712/ice1712.h static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val) val 412 sound/pci/ice1712/ice1712.h ice->gpio.set_data(ice, val); val 456 sound/pci/ice1712/ice1712.h unsigned val; val 460 sound/pci/ice1712/ice1712.h val = snd_ice1712_gpio_read(ice); val 461 sound/pci/ice1712/ice1712.h val &= ~mask; val 462 sound/pci/ice1712/ice1712.h val |= mask & bits; val 463 sound/pci/ice1712/ice1712.h snd_ice1712_gpio_write(ice, val); val 476 sound/pci/ice1712/ice1712.h int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val, val 151 sound/pci/ice1712/ice1724.c unsigned short val) val 160 sound/pci/ice1712/ice1724.c outw(val, ICEMT1724(ice, AC97_DATA)); val 626 sound/pci/ice1712/ice1724.c unsigned char val, old; val 629 sound/pci/ice1712/ice1724.c val = old = inb(ICEMT1724(ice, I2S_FORMAT)); val 631 sound/pci/ice1712/ice1724.c val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */ val 633 sound/pci/ice1712/ice1724.c val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */ val 634 sound/pci/ice1712/ice1724.c if (val != old) { val 635 sound/pci/ice1712/ice1724.c outb(val, ICEMT1724(ice, I2S_FORMAT)); val 770 sound/pci/ice1712/ice1724.c unsigned char val; val 774 sound/pci/ice1712/ice1724.c val = (8 - substream->runtime->channels) >> 1; val 775 sound/pci/ice1712/ice1724.c outb(val, ICEMT1724(ice, BURST)); val 1163 sound/pci/ice1712/ice1724.c static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val) val 1171 sound/pci/ice1712/ice1724.c outw(val, ICEMT1724(ice, SPDIF_CTRL)); val 1174 sound/pci/ice1712/ice1724.c outw(val, ICEMT1724(ice, SPDIF_CTRL)); val 1180 sound/pci/ice1712/ice1724.c unsigned int val, nval; val 1184 sound/pci/ice1712/ice1724.c nval = val = inw(ICEMT1724(ice, SPDIF_CTRL)); val 1195 sound/pci/ice1712/ice1724.c if (val != nval) val 1384 sound/pci/ice1712/ice1724.c unsigned char val; val 1387 sound/pci/ice1712/ice1724.c val = 3 - substream->number; val 1388 sound/pci/ice1712/ice1724.c if (inb(ICEMT1724(ice, BURST)) < val) val 1389 sound/pci/ice1712/ice1724.c outb(val, ICEMT1724(ice, BURST)); val 1607 sound/pci/ice1712/ice1724.c unsigned int val, rbits; val 1609 sound/pci/ice1712/ice1724.c val = diga->status[0] & 0x03; /* professional, non-audio */ val 1610 sound/pci/ice1712/ice1724.c if (val & 0x01) { val 1614 sound/pci/ice1712/ice1724.c val |= 1U << 3; val 1618 sound/pci/ice1712/ice1724.c case 2: val |= 5 << 12; break; /* 96k */ val 1619 sound/pci/ice1712/ice1724.c case 3: val |= 6 << 12; break; /* 192k */ val 1620 sound/pci/ice1712/ice1724.c case 10: val |= 4 << 12; break; /* 88.2k */ val 1621 sound/pci/ice1712/ice1724.c case 11: val |= 7 << 12; break; /* 176.4k */ val 1628 sound/pci/ice1712/ice1724.c val |= 3U << 12; val 1631 sound/pci/ice1712/ice1724.c val |= 2U << 12; val 1637 sound/pci/ice1712/ice1724.c val |= diga->status[1] & 0x04; /* copyright */ val 1640 sound/pci/ice1712/ice1724.c val |= 1U << 3; val 1641 sound/pci/ice1712/ice1724.c val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */ val 1642 sound/pci/ice1712/ice1724.c val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */ val 1644 sound/pci/ice1712/ice1724.c return val; val 1647 sound/pci/ice1712/ice1724.c static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val) val 1650 sound/pci/ice1712/ice1724.c diga->status[0] = val & 0x03; /* professional, non-audio */ val 1651 sound/pci/ice1712/ice1724.c if (val & 0x01) { val 1653 sound/pci/ice1712/ice1724.c if (val & (1U << 3)) val 1655 sound/pci/ice1712/ice1724.c switch ((val >> 12) & 0x7) { val 1667 sound/pci/ice1712/ice1724.c diga->status[0] |= val & (1U << 2); /* copyright */ val 1668 sound/pci/ice1712/ice1724.c if (val & (1U << 3)) val 1670 sound/pci/ice1712/ice1724.c diga->status[1] |= (val >> 4) & 0x3f; /* category */ val 1671 sound/pci/ice1712/ice1724.c diga->status[3] |= (val >> 12) & 0x07; /* fs */ val 1679 sound/pci/ice1712/ice1724.c unsigned int val; val 1680 sound/pci/ice1712/ice1724.c val = inw(ICEMT1724(ice, SPDIF_CTRL)); val 1681 sound/pci/ice1712/ice1724.c decode_spdif_bits(&ucontrol->value.iec958, val); val 1689 sound/pci/ice1712/ice1724.c unsigned int val, old; val 1691 sound/pci/ice1712/ice1724.c val = encode_spdif_bits(&ucontrol->value.iec958); val 1694 sound/pci/ice1712/ice1724.c if (val != old) val 1695 sound/pci/ice1712/ice1724.c update_spdif_bits(ice, val); val 1697 sound/pci/ice1712/ice1724.c return val != old; val 1765 sound/pci/ice1712/ice1724.c unsigned char old, val; val 1768 sound/pci/ice1712/ice1724.c old = val = inb(ICEREG1724(ice, SPDIF_CFG)); val 1769 sound/pci/ice1712/ice1724.c val &= ~VT1724_CFG_SPDIF_OUT_EN; val 1771 sound/pci/ice1712/ice1724.c val |= VT1724_CFG_SPDIF_OUT_EN; val 1772 sound/pci/ice1712/ice1724.c if (old != val) val 1773 sound/pci/ice1712/ice1724.c outb(val, ICEREG1724(ice, SPDIF_CFG)); val 1775 sound/pci/ice1712/ice1724.c return old != val; val 1817 sound/pci/ice1712/ice1724.c unsigned int val, nval; val 1823 sound/pci/ice1712/ice1724.c val = snd_ice1712_gpio_read(ice); val 1824 sound/pci/ice1712/ice1724.c nval |= val & ~(1 << shift); val 1825 sound/pci/ice1712/ice1724.c if (val != nval) val 1828 sound/pci/ice1712/ice1724.c return val != nval; val 2051 sound/pci/ice1712/ice1724.c unsigned long val; val 2057 sound/pci/ice1712/ice1724.c val = inl(ICEMT1724(ice, ROUTE_PLAYBACK)); val 2058 sound/pci/ice1712/ice1724.c val >>= shift; val 2059 sound/pci/ice1712/ice1724.c val &= 7; /* we now have 3 bits per output */ val 2060 sound/pci/ice1712/ice1724.c eitem = xlate[val]; val 2068 sound/pci/ice1712/ice1724.c int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val, val 2081 sound/pci/ice1712/ice1724.c nval = xroute[val % 5]; val 2082 sound/pci/ice1712/ice1724.c val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK)); val 2083 sound/pci/ice1712/ice1724.c val &= ~(0x07 << shift); val 2084 sound/pci/ice1712/ice1724.c val |= nval << shift; val 2085 sound/pci/ice1712/ice1724.c change = val != old_val; val 2087 sound/pci/ice1712/ice1724.c outl(val, ICEMT1724(ice, ROUTE_PLAYBACK)); val 2259 sound/pci/ice1712/ice1724.c unsigned char val; val 2266 sound/pci/ice1712/ice1724.c val = inb(ICEREG1724(ice, I2C_DATA)); val 2271 sound/pci/ice1712/ice1724.c return val; val 150 sound/pci/ice1712/juli.c unsigned char val) val 153 sound/pci/ice1712/juli.c reg, val); val 293 sound/pci/ice1712/juli.c unsigned int val; val 294 sound/pci/ice1712/juli.c val = ice->gpio.get_data(ice) & (unsigned int) kcontrol->private_value; val 297 sound/pci/ice1712/juli.c ucontrol->value.integer.value[0] = (val) ? 0 : 1; val 300 sound/pci/ice1712/juli.c ucontrol->value.integer.value[0] = (val) ? 1 : 0; val 519 sound/pci/ice1712/juli.c unsigned char val; val 529 sound/pci/ice1712/juli.c val = inb(ICEMT1724(ice, RATE)); val 530 sound/pci/ice1712/juli.c outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); val 77 sound/pci/ice1712/maya44.c unsigned char reg, unsigned short val) val 84 sound/pci/ice1712/maya44.c (reg << 1) | ((val >> 8) & 1), val 85 sound/pci/ice1712/maya44.c val & 0xff); val 86 sound/pci/ice1712/maya44.c wm->regs[reg] = val; val 94 sound/pci/ice1712/maya44.c unsigned short mask, unsigned short val) val 96 sound/pci/ice1712/maya44.c val |= wm->regs[reg] & ~mask; val 97 sound/pci/ice1712/maya44.c if (val != wm->regs[reg]) { val 98 sound/pci/ice1712/maya44.c wm8776_write(ice, wm, reg, val); val 193 sound/pci/ice1712/maya44.c unsigned int val, data; val 198 sound/pci/ice1712/maya44.c val = ucontrol->value.integer.value[ch]; val 199 sound/pci/ice1712/maya44.c if (val > vol->maxval) val 200 sound/pci/ice1712/maya44.c val = vol->maxval; val 201 sound/pci/ice1712/maya44.c if (val == wm->volumes[idx][ch]) val 203 sound/pci/ice1712/maya44.c if (!val) val 206 sound/pci/ice1712/maya44.c data = (val - 1) + vol->offset; val 213 sound/pci/ice1712/maya44.c val ? 0 : vol->mux_bits[ch]); val 214 sound/pci/ice1712/maya44.c wm->volumes[idx][ch] = val; val 225 sound/pci/ice1712/maya44.c #define GET_SW_VAL_IDX(val) ((val) & 0xff) val 226 sound/pci/ice1712/maya44.c #define GET_SW_VAL_REG(val) (((val) >> 8) & 0xff) val 227 sound/pci/ice1712/maya44.c #define GET_SW_VAL_MASK(val) (((val) >> 16) & 0xff) val 250 sound/pci/ice1712/maya44.c unsigned int mask, val; val 256 sound/pci/ice1712/maya44.c val = ucontrol->value.integer.value[0]; val 257 sound/pci/ice1712/maya44.c if (val) val 262 sound/pci/ice1712/maya44.c mask, val ? mask : 0); val 280 sound/pci/ice1712/maya44.c #define GET_GPIO_VAL_SHIFT(val) ((val) & 0xff) val 281 sound/pci/ice1712/maya44.c #define GET_GPIO_VAL_INV(val) (((val) >> 8) & 1) val 301 sound/pci/ice1712/maya44.c unsigned int val; val 303 sound/pci/ice1712/maya44.c val = (snd_ice1712_gpio_read(chip->ice) >> shift) & 1; val 305 sound/pci/ice1712/maya44.c val = !val; val 306 sound/pci/ice1712/maya44.c ucontrol->value.integer.value[0] = val; val 315 sound/pci/ice1712/maya44.c unsigned int val, mask; val 320 sound/pci/ice1712/maya44.c val = ucontrol->value.integer.value[0]; val 322 sound/pci/ice1712/maya44.c val = !val; val 323 sound/pci/ice1712/maya44.c val = val ? mask : 0; val 324 sound/pci/ice1712/maya44.c changed = maya_set_gpio_bits(chip->ice, mask, val); val 590 sound/pci/ice1712/maya44.c unsigned int ratio, adc_ratio, val; val 633 sound/pci/ice1712/maya44.c val = adc_ratio; val 635 sound/pci/ice1712/maya44.c val |= 8; val 636 sound/pci/ice1712/maya44.c val |= ratio << 4; val 642 sound/pci/ice1712/maya44.c 0x180, val); val 249 sound/pci/ice1712/phase.c static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val) val 251 sound/pci/ice1712/phase.c phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16); val 257 sound/pci/ice1712/phase.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) val 259 sound/pci/ice1712/phase.c wm_put_nocache(ice, reg, val); val 261 sound/pci/ice1712/phase.c ice->akm[0].images[reg] = val >> 8; val 262 sound/pci/ice1712/phase.c ice->akm[0].images[reg + 1] = val; val 559 sound/pci/ice1712/phase.c int val = (spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1; val 560 sound/pci/ice1712/phase.c if (ucontrol->value.integer.value[i] != val) { val 602 sound/pci/ice1712/phase.c int val = (spec->master[i] & WM_VOL_MUTE) ? 0 : 1; val 603 sound/pci/ice1712/phase.c if (ucontrol->value.integer.value[i] != val) { val 639 sound/pci/ice1712/phase.c unsigned short val; val 642 sound/pci/ice1712/phase.c val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff; val 643 sound/pci/ice1712/phase.c val = val > PCM_MIN ? (val - PCM_MIN) : 0; val 644 sound/pci/ice1712/phase.c ucontrol->value.integer.value[0] = val; val 77 sound/pci/ice1712/pontis.c static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val) val 80 sound/pci/ice1712/pontis.c cval = (reg << 9) | val; val 84 sound/pci/ice1712/pontis.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) val 86 sound/pci/ice1712/pontis.c wm_put_nocache(ice, reg, val); val 88 sound/pci/ice1712/pontis.c ice->akm[0].images[reg] = val >> 8; val 89 sound/pci/ice1712/pontis.c ice->akm[0].images[reg + 1] = val; val 112 sound/pci/ice1712/pontis.c unsigned short val; val 117 sound/pci/ice1712/pontis.c val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff; val 118 sound/pci/ice1712/pontis.c val = val > DAC_MIN ? (val - DAC_MIN) : 0; val 119 sound/pci/ice1712/pontis.c ucontrol->value.integer.value[i] = val; val 167 sound/pci/ice1712/pontis.c unsigned short val; val 172 sound/pci/ice1712/pontis.c val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff; val 173 sound/pci/ice1712/pontis.c val = val > ADC_MIN ? (val - ADC_MIN) : 0; val 174 sound/pci/ice1712/pontis.c ucontrol->value.integer.value[i] = val; val 256 sound/pci/ice1712/pontis.c unsigned short val, oval; val 260 sound/pci/ice1712/pontis.c val = oval = wm_get(ice, WM_OUT_MUX); val 262 sound/pci/ice1712/pontis.c val |= 0x04; val 264 sound/pci/ice1712/pontis.c val &= ~0x04; val 265 sound/pci/ice1712/pontis.c if (val != oval) { val 266 sound/pci/ice1712/pontis.c wm_put(ice, WM_OUT_MUX, val); val 291 sound/pci/ice1712/pontis.c unsigned short val, oval; val 296 sound/pci/ice1712/pontis.c val = oval & 0x0f; val 298 sound/pci/ice1712/pontis.c val |= 0x60; val 300 sound/pci/ice1712/pontis.c val |= 0x90; val 301 sound/pci/ice1712/pontis.c if (val != oval) { val 302 sound/pci/ice1712/pontis.c wm_put(ice, WM_DAC_CTRL1, val); val 303 sound/pci/ice1712/pontis.c wm_put_nocache(ice, WM_DAC_CTRL1, val); val 313 sound/pci/ice1712/pontis.c static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val) val 316 sound/pci/ice1712/pontis.c if (val) val 340 sound/pci/ice1712/pontis.c unsigned int val = 0; val 343 sound/pci/ice1712/pontis.c val <<= 1; val 347 sound/pci/ice1712/pontis.c val |= 1; val 352 sound/pci/ice1712/pontis.c return val; val 374 sound/pci/ice1712/pontis.c unsigned int val; val 385 sound/pci/ice1712/pontis.c val = spi_read_byte(ice); val 392 sound/pci/ice1712/pontis.c return val; val 422 sound/pci/ice1712/pontis.c unsigned char val; val 428 sound/pci/ice1712/pontis.c val = 0x80 | (ice->gpio.saved[0] << 3); val 429 sound/pci/ice1712/pontis.c spi_write(ice, CS_DEV, 0x04, val); val 462 sound/pci/ice1712/pontis.c unsigned int val; val 466 sound/pci/ice1712/pontis.c val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0; val 467 sound/pci/ice1712/pontis.c changed = val != ice->gpio.write_mask; val 468 sound/pci/ice1712/pontis.c ice->gpio.write_mask = val; val 486 sound/pci/ice1712/pontis.c unsigned int val; val 490 sound/pci/ice1712/pontis.c val = ucontrol->value.integer.value[0] & 0xff0f; val 491 sound/pci/ice1712/pontis.c changed = (val != ice->gpio.direction); val 492 sound/pci/ice1712/pontis.c ice->gpio.direction = val; val 511 sound/pci/ice1712/pontis.c unsigned int val, nval; val 516 sound/pci/ice1712/pontis.c val = snd_ice1712_gpio_read(ice) & 0xffff; val 518 sound/pci/ice1712/pontis.c if (val != nval) { val 622 sound/pci/ice1712/pontis.c unsigned int reg, val; val 625 sound/pci/ice1712/pontis.c if (sscanf(line, "%x %x", ®, &val) != 2) val 627 sound/pci/ice1712/pontis.c if (reg <= 0x17 && val <= 0xffff) val 628 sound/pci/ice1712/pontis.c wm_put(ice, reg, val); val 636 sound/pci/ice1712/pontis.c int reg, val; val 640 sound/pci/ice1712/pontis.c val = wm_get(ice, reg); val 641 sound/pci/ice1712/pontis.c snd_iprintf(buffer, "%02x = %04x\n", reg, val); val 655 sound/pci/ice1712/pontis.c int reg, val; val 659 sound/pci/ice1712/pontis.c val = spi_read(ice, CS_DEV, reg); val 660 sound/pci/ice1712/pontis.c snd_iprintf(buffer, "%02x = %02x\n", reg, val); val 662 sound/pci/ice1712/pontis.c val = spi_read(ice, CS_DEV, 0x7f); val 663 sound/pci/ice1712/pontis.c snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val); val 61 sound/pci/ice1712/prodigy192.c static inline void stac9460_put(struct snd_ice1712 *ice, int reg, unsigned char val) val 63 sound/pci/ice1712/prodigy192.c snd_vt1724_write_i2c(ice, PRODIGY192_STAC9460_ADDR, reg, val); val 97 sound/pci/ice1712/prodigy192.c unsigned char val; val 104 sound/pci/ice1712/prodigy192.c val = stac9460_get(ice, idx); val 105 sound/pci/ice1712/prodigy192.c ucontrol->value.integer.value[0] = (~val >> 7) & 0x1; val 192 sound/pci/ice1712/prodigy192.c unsigned char val; val 196 sound/pci/ice1712/prodigy192.c val = stac9460_get(ice, STAC946X_MIC_L_VOLUME + i); val 197 sound/pci/ice1712/prodigy192.c ucontrol->value.integer.value[i] = ~val>>7 & 0x1; val 281 sound/pci/ice1712/prodigy192.c unsigned char val; val 283 sound/pci/ice1712/prodigy192.c val = stac9460_get(ice, STAC946X_GENERAL_PURPOSE); val 284 sound/pci/ice1712/prodigy192.c ucontrol->value.enumerated.item[0] = (val >> 7) & 0x1; val 552 sound/pci/ice1712/prodigy192.c unsigned char val; val 554 sound/pci/ice1712/prodigy192.c val = prodigy192_ak4114_read(ice, AK4114_REG_IO1); val 558 sound/pci/ice1712/prodigy192.c ucontrol->value.enumerated.item[0] = (val & AK4114_IPS0) ? 1 : 0; val 629 sound/pci/ice1712/prodigy192.c int reg, val; val 632 sound/pci/ice1712/prodigy192.c val = stac9460_get(ice, reg); val 633 sound/pci/ice1712/prodigy192.c snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val); val 123 sound/pci/ice1712/prodigy_hifi.c static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val) val 126 sound/pci/ice1712/prodigy_hifi.c cval = (reg << 9) | val; val 130 sound/pci/ice1712/prodigy_hifi.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) val 132 sound/pci/ice1712/prodigy_hifi.c wm_put_nocache(ice, reg, val); val 134 sound/pci/ice1712/prodigy_hifi.c ice->akm[0].images[reg] = val >> 8; val 135 sound/pci/ice1712/prodigy_hifi.c ice->akm[0].images[reg + 1] = val; val 142 sound/pci/ice1712/prodigy_hifi.c static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val) val 145 sound/pci/ice1712/prodigy_hifi.c if (val) val 586 sound/pci/ice1712/prodigy_hifi.c unsigned short val; val 591 sound/pci/ice1712/prodigy_hifi.c val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff; val 592 sound/pci/ice1712/prodigy_hifi.c val = val > ADC_MIN ? (val - ADC_MIN) : 0; val 593 sound/pci/ice1712/prodigy_hifi.c ucontrol->value.integer.value[i] = val; val 682 sound/pci/ice1712/prodigy_hifi.c unsigned short val, oval; val 686 sound/pci/ice1712/prodigy_hifi.c val = oval = wm_get(ice, WM_OUT_MUX); val 688 sound/pci/ice1712/prodigy_hifi.c val |= 0x04; val 690 sound/pci/ice1712/prodigy_hifi.c val &= ~0x04; val 691 sound/pci/ice1712/prodigy_hifi.c if (val != oval) { val 692 sound/pci/ice1712/prodigy_hifi.c wm_put(ice, WM_OUT_MUX, val); val 720 sound/pci/ice1712/prodigy_hifi.c unsigned short val, oval; val 725 sound/pci/ice1712/prodigy_hifi.c val = oval & 0x0f; val 727 sound/pci/ice1712/prodigy_hifi.c val |= 0x60; val 729 sound/pci/ice1712/prodigy_hifi.c val |= 0x90; val 730 sound/pci/ice1712/prodigy_hifi.c if (val != oval) { val 731 sound/pci/ice1712/prodigy_hifi.c wm_put(ice, WM_DAC_CTRL1, val); val 732 sound/pci/ice1712/prodigy_hifi.c wm_put_nocache(ice, WM_DAC_CTRL1, val); val 866 sound/pci/ice1712/prodigy_hifi.c unsigned int reg, val; val 869 sound/pci/ice1712/prodigy_hifi.c if (sscanf(line, "%x %x", ®, &val) != 2) val 871 sound/pci/ice1712/prodigy_hifi.c if (reg <= 0x17 && val <= 0xffff) val 872 sound/pci/ice1712/prodigy_hifi.c wm_put(ice, reg, val); val 881 sound/pci/ice1712/prodigy_hifi.c int reg, val; val 885 sound/pci/ice1712/prodigy_hifi.c val = wm_get(ice, reg); val 886 sound/pci/ice1712/prodigy_hifi.c snd_iprintf(buffer, "%02x = %04x\n", reg, val); val 33 sound/pci/ice1712/quartet.c void (*set_register)(struct snd_ice1712 *ice, unsigned int val); val 237 sound/pci/ice1712/quartet.c unsigned char val) val 240 sound/pci/ice1712/quartet.c reg, val); val 453 sound/pci/ice1712/quartet.c static void set_scr(struct snd_ice1712 *ice, unsigned int val) val 456 sound/pci/ice1712/quartet.c reg_write(ice, GPIO_SCR, val); val 457 sound/pci/ice1712/quartet.c spec->scr = val; val 460 sound/pci/ice1712/quartet.c static void set_mcr(struct snd_ice1712 *ice, unsigned int val) val 463 sound/pci/ice1712/quartet.c reg_write(ice, GPIO_MCR, val); val 464 sound/pci/ice1712/quartet.c spec->mcr = val; val 467 sound/pci/ice1712/quartet.c static void set_cpld(struct snd_ice1712 *ice, unsigned int val) val 470 sound/pci/ice1712/quartet.c reg_write(ice, GPIO_CPLD_CSN, val); val 471 sound/pci/ice1712/quartet.c spec->cpld = val; val 497 sound/pci/ice1712/quartet.c unsigned int val; val 498 sound/pci/ice1712/quartet.c val = get_scr(ice) & SCR_MUTE; val 499 sound/pci/ice1712/quartet.c ucontrol->value.integer.value[0] = (val) ? 0 : 1; val 543 sound/pci/ice1712/quartet.c unsigned int val, result; val 544 sound/pci/ice1712/quartet.c val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0); val 545 sound/pci/ice1712/quartet.c switch (val) { val 612 sound/pci/ice1712/quartet.c unsigned int val; val 614 sound/pci/ice1712/quartet.c val = get_scr(ice) & SCR_PHP_V; val 615 sound/pci/ice1712/quartet.c ucontrol->value.integer.value[0] = val ? 1 : 0; val 849 sound/pci/ice1712/quartet.c unsigned char val; val 851 sound/pci/ice1712/quartet.c val = inb(ICEMT1724(ice, RATE)); val 852 sound/pci/ice1712/quartet.c outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); val 899 sound/pci/ice1712/quartet.c unsigned int val; val 901 sound/pci/ice1712/quartet.c val = get_cpld(ice); val 903 sound/pci/ice1712/quartet.c val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL); val 904 sound/pci/ice1712/quartet.c if (!(val & CPLD_SYNC_SEL)) { val 908 sound/pci/ice1712/quartet.c switch (val) { val 985 sound/pci/ice1712/quartet.c unsigned char val; val 988 sound/pci/ice1712/quartet.c val = inb(ICEMT1724(ice, RATE)); val 989 sound/pci/ice1712/quartet.c outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); val 96 sound/pci/ice1712/revo.c unsigned int mask, val; val 98 sound/pci/ice1712/revo.c val = 0; val 100 sound/pci/ice1712/revo.c val |= VT1724_REVO_I2C_CLOCK; /* write SCL */ val 102 sound/pci/ice1712/revo.c val |= VT1724_REVO_I2C_DATA; /* write SDA */ val 105 sound/pci/ice1712/revo.c ice->gpio.direction |= val; val 113 sound/pci/ice1712/revo.c unsigned int val = 0; val 116 sound/pci/ice1712/revo.c val |= VT1724_REVO_I2C_CLOCK; val 118 sound/pci/ice1712/revo.c val |= VT1724_REVO_I2C_DATA; val 121 sound/pci/ice1712/revo.c VT1724_REVO_I2C_CLOCK, val); val 220 sound/pci/ice1712/se.c unsigned int val; val 222 sound/pci/ice1712/se.c val = (addr << 9) | data; val 223 sound/pci/ice1712/se.c snd_vt1724_write_i2c(ice, 0x34, val >> 8, val & 0xff); val 166 sound/pci/ice1712/wm8766.c u16 val = wm->regs[WM8766_REG_IFCTRL] & ~WM8766_IF_MASK; val 169 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, WM8766_REG_IFCTRL, val | dac); val 174 sound/pci/ice1712/wm8766.c u16 val = wm->regs[WM8766_REG_DACR1]; val 176 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, WM8766_REG_DACR1, val | WM8766_VOL_UPDATE); val 241 sound/pci/ice1712/wm8766.c u16 val, regval1, regval2; val 253 sound/pci/ice1712/wm8766.c val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; val 254 sound/pci/ice1712/wm8766.c val |= regval1 << __ffs(wm->ctl[n].mask1); val 258 sound/pci/ice1712/wm8766.c val &= ~wm->ctl[n].mask2; val 259 sound/pci/ice1712/wm8766.c val |= regval2 << __ffs(wm->ctl[n].mask2); val 261 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, wm->ctl[n].reg1, val); val 265 sound/pci/ice1712/wm8766.c val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; val 266 sound/pci/ice1712/wm8766.c val |= regval2 << __ffs(wm->ctl[n].mask2); val 268 sound/pci/ice1712/wm8766.c val |= WM8766_VOL_UPDATE; val 269 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, wm->ctl[n].reg2, val); val 448 sound/pci/ice1712/wm8776.c u16 val = wm->regs[WM8776_REG_DACRVOL]; val 450 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, WM8776_REG_DACRVOL, val | WM8776_VOL_UPDATE); val 515 sound/pci/ice1712/wm8776.c u16 val, regval1, regval2; val 527 sound/pci/ice1712/wm8776.c val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; val 528 sound/pci/ice1712/wm8776.c val |= regval1 << __ffs(wm->ctl[n].mask1); val 532 sound/pci/ice1712/wm8776.c val &= ~wm->ctl[n].mask2; val 533 sound/pci/ice1712/wm8776.c val |= regval2 << __ffs(wm->ctl[n].mask2); val 535 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, wm->ctl[n].reg1, val); val 539 sound/pci/ice1712/wm8776.c val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; val 540 sound/pci/ice1712/wm8776.c val |= regval2 << __ffs(wm->ctl[n].mask2); val 542 sound/pci/ice1712/wm8776.c val |= WM8776_VOL_UPDATE; val 543 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, wm->ctl[n].reg2, val); val 36 sound/pci/ice1712/wtm.c unsigned char val) val 38 sound/pci/ice1712/wtm.c snd_vt1724_write_i2c(ice, STAC9460_I2C_ADDR, reg, val); val 50 sound/pci/ice1712/wtm.c unsigned char val) val 52 sound/pci/ice1712/wtm.c snd_vt1724_write_i2c(ice, STAC9460_2_I2C_ADDR, reg, val); val 118 sound/pci/ice1712/wtm.c unsigned char val; val 131 sound/pci/ice1712/wtm.c val = stac9460_get(ice, idx); val 133 sound/pci/ice1712/wtm.c val = stac9460_2_get(ice, idx - 6); val 134 sound/pci/ice1712/wtm.c ucontrol->value.integer.value[0] = (~val >> 7) & 0x1; val 262 sound/pci/ice1712/wtm.c unsigned char val; val 268 sound/pci/ice1712/wtm.c val = stac9460_get(ice, STAC946X_MIC_L_VOLUME + i); val 269 sound/pci/ice1712/wtm.c ucontrol->value.integer.value[i] = ~val>>7 & 0x1; val 273 sound/pci/ice1712/wtm.c val = stac9460_2_get(ice, STAC946X_MIC_L_VOLUME + i); val 274 sound/pci/ice1712/wtm.c ucontrol->value.integer.value[i] = ~val>>7 & 0x1; val 399 sound/pci/ice1712/wtm.c unsigned char val; val 404 sound/pci/ice1712/wtm.c val = stac9460_get(ice, STAC946X_GENERAL_PURPOSE); val 406 sound/pci/ice1712/wtm.c val = stac9460_2_get(ice, STAC946X_GENERAL_PURPOSE); val 407 sound/pci/ice1712/wtm.c ucontrol->value.enumerated.item[0] = (val >> 7) & 0x1; val 456 sound/pci/intel8x0.c static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) val 458 sound/pci/intel8x0.c iowrite8(val, chip->bmaddr + offset); val 461 sound/pci/intel8x0.c static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) val 463 sound/pci/intel8x0.c iowrite16(val, chip->bmaddr + offset); val 466 sound/pci/intel8x0.c static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) val 468 sound/pci/intel8x0.c iowrite32(val, chip->bmaddr + offset); val 480 sound/pci/intel8x0.c static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) val 482 sound/pci/intel8x0.c iowrite16(val, chip->addr + offset); val 535 sound/pci/intel8x0.c unsigned short val) val 545 sound/pci/intel8x0.c iaputword(chip, reg + ac97->num * 0x80, val); val 599 sound/pci/intel8x0.c int val = igetbyte(chip, ICHREG(ALI_CSPSR)); val 600 sound/pci/intel8x0.c if (val & mask) val 639 sound/pci/intel8x0.c unsigned short val) val 645 sound/pci/intel8x0.c iputword(chip, ICHREG(ALI_CPR), val); val 807 sound/pci/intel8x0.c unsigned char val = 0; val 816 sound/pci/intel8x0.c val = ICH_IOCE | ICH_STARTBM; val 823 sound/pci/intel8x0.c val = 0; val 826 sound/pci/intel8x0.c val = ICH_IOCE; val 831 sound/pci/intel8x0.c iputbyte(chip, port + ICH_REG_OFF_CR, val); val 849 sound/pci/intel8x0.c unsigned int val, fifo; val 851 sound/pci/intel8x0.c val = igetdword(chip, ICHREG(ALI_DMACR)); val 866 sound/pci/intel8x0.c val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ val 868 sound/pci/intel8x0.c iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); val 876 sound/pci/intel8x0.c iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); val 1255 sound/pci/intel8x0.c unsigned int val; val 1258 sound/pci/intel8x0.c val = igetdword(chip, ICHREG(ALI_INTERFACECR)); val 1259 sound/pci/intel8x0.c val |= ICH_ALI_IF_AC97SP; val 1260 sound/pci/intel8x0.c iputdword(chip, ICHREG(ALI_INTERFACECR), val); val 1270 sound/pci/intel8x0.c unsigned int val; val 1274 sound/pci/intel8x0.c val = igetdword(chip, ICHREG(ALI_INTERFACECR)); val 1275 sound/pci/intel8x0.c val &= ~ICH_ALI_IF_AC97SP; val 1276 sound/pci/intel8x0.c iputdword(chip, ICHREG(ALI_INTERFACECR), val); val 2311 sound/pci/intel8x0.c u32 val; val 2312 sound/pci/intel8x0.c val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; val 2313 sound/pci/intel8x0.c val |= ICH_PCM_SPDIF_1011; val 2314 sound/pci/intel8x0.c iputdword(chip, ICHREG(GLOB_CNT), val); val 2476 sound/pci/intel8x0.c unsigned int val; val 2477 sound/pci/intel8x0.c pci_read_config_dword(chip->pci, 0x4c, &val); val 2478 sound/pci/intel8x0.c val |= 0x1000000; val 2479 sound/pci/intel8x0.c pci_write_config_dword(chip->pci, 0x4c, val); val 2569 sound/pci/intel8x0.c unsigned int val; val 2570 sound/pci/intel8x0.c pci_read_config_dword(chip->pci, 0x4c, &val); val 2571 sound/pci/intel8x0.c val &= ~0x1000000; val 2572 sound/pci/intel8x0.c pci_write_config_dword(chip->pci, 0x4c, val); val 251 sound/pci/intel8x0m.c static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val) val 253 sound/pci/intel8x0m.c iowrite8(val, chip->bmaddr + offset); val 256 sound/pci/intel8x0m.c static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val) val 258 sound/pci/intel8x0m.c iowrite16(val, chip->bmaddr + offset); val 261 sound/pci/intel8x0m.c static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val) val 263 sound/pci/intel8x0m.c iowrite32(val, chip->bmaddr + offset); val 275 sound/pci/intel8x0m.c static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val) val 277 sound/pci/intel8x0m.c iowrite16(val, chip->addr + offset); val 332 sound/pci/intel8x0m.c unsigned short val) val 342 sound/pci/intel8x0m.c iaputword(chip, reg + ac97->num * 0x80, val); val 525 sound/pci/intel8x0m.c unsigned char val = 0; val 531 sound/pci/intel8x0m.c val = ICH_IOCE | ICH_STARTBM; val 535 sound/pci/intel8x0m.c val = 0; val 538 sound/pci/intel8x0m.c val = ICH_IOCE; val 541 sound/pci/intel8x0m.c val = ICH_IOCE | ICH_STARTBM; val 546 sound/pci/intel8x0m.c iputbyte(chip, port + ICH_REG_OFF_CR, val); val 1746 sound/pci/korg1212/korg1212.c int i, val; val 1754 sound/pci/korg1212/korg1212.c val = korg1212->sharedBufferPtr->volumeData[kcontrol->private_value]; val 1756 sound/pci/korg1212/korg1212.c if ((u->value.integer.value[0] != 0) != (val < 0)) { val 1757 sound/pci/korg1212/korg1212.c val = abs(val) * (korg1212->volumePhase[i] > 0 ? -1 : 1); val 1758 sound/pci/korg1212/korg1212.c korg1212->sharedBufferPtr->volumeData[i] = val; val 1765 sound/pci/korg1212/korg1212.c val = korg1212->sharedBufferPtr->volumeData[kcontrol->private_value+1]; val 1767 sound/pci/korg1212/korg1212.c if ((u->value.integer.value[1] != 0) != (val < 0)) { val 1768 sound/pci/korg1212/korg1212.c val = abs(val) * (korg1212->volumePhase[i+1] > 0 ? -1 : 1); val 1769 sound/pci/korg1212/korg1212.c korg1212->sharedBufferPtr->volumeData[i+1] = val; val 1814 sound/pci/korg1212/korg1212.c int val; val 1824 sound/pci/korg1212/korg1212.c val = korg1212->volumePhase[i] > 0 ? -1 : 1; val 1825 sound/pci/korg1212/korg1212.c val *= u->value.integer.value[0]; val 1826 sound/pci/korg1212/korg1212.c korg1212->sharedBufferPtr->volumeData[i] = val; val 1835 sound/pci/korg1212/korg1212.c val = korg1212->volumePhase[i+1] > 0 ? -1 : 1; val 1836 sound/pci/korg1212/korg1212.c val *= u->value.integer.value[1]; val 1837 sound/pci/korg1212/korg1212.c korg1212->sharedBufferPtr->volumeData[i+1] = val; val 1982 sound/pci/korg1212/korg1212.c unsigned int val; val 1985 sound/pci/korg1212/korg1212.c val = ucontrol->value.enumerated.item[0] % 3; val 1987 sound/pci/korg1212/korg1212.c change = val != korg1212->clkSource; val 1988 sound/pci/korg1212/korg1212.c snd_korg1212_SetClockSource(korg1212, val); val 138 sound/pci/lola/lola.c static int rirb_get_response(struct lola *chip, unsigned int *val, val 152 sound/pci/lola/lola.c *val = chip->res; val 193 sound/pci/lola/lola.c unsigned int *val, unsigned int *extval) val 202 sound/pci/lola/lola.c err = rirb_get_response(chip, val, extval); val 325 sound/pci/lola/lola.c unsigned int val; val 328 sound/pci/lola/lola.c val = (1 << chip->pcm[PLAY].num_streams) - 1; val 329 sound/pci/lola/lola.c lola_writel(chip, BAR1, DOINTCTL, val); val 330 sound/pci/lola/lola.c val = (1 << chip->pcm[CAPT].num_streams) - 1; val 331 sound/pci/lola/lola.c lola_writel(chip, BAR1, DIINTCTL, val); val 334 sound/pci/lola/lola.c val = LOLA_DINT_GLOBAL | LOLA_DINT_CTRL | LOLA_DINT_FIFOERR | val 336 sound/pci/lola/lola.c lola_writel(chip, BAR1, DINTCTL, val); val 437 sound/pci/lola/lola.c unsigned int val; val 440 sound/pci/lola/lola.c err = lola_read_param(chip, 0, LOLA_PAR_VENDOR_ID, &val); val 445 sound/pci/lola/lola.c val >>= 16; val 446 sound/pci/lola/lola.c if (val != 0x1369) { val 447 sound/pci/lola/lola.c dev_err(chip->card->dev, "Unknown codec vendor 0x%x\n", val); val 451 sound/pci/lola/lola.c err = lola_read_param(chip, 1, LOLA_PAR_FUNCTION_TYPE, &val); val 456 sound/pci/lola/lola.c if (val != 1) { val 457 sound/pci/lola/lola.c dev_err(chip->card->dev, "Unknown function type %d\n", val); val 461 sound/pci/lola/lola.c err = lola_read_param(chip, 1, LOLA_PAR_SPECIFIC_CAPS, &val); val 466 sound/pci/lola/lola.c chip->lola_caps = val; val 475 sound/pci/lola/lola.c dev_err(chip->card->dev, "Invalid Lola-spec caps 0x%x\n", val); val 383 sound/pci/lola/lola.h #define lola_writel(chip, idx, name, val) \ val 384 sound/pci/lola/lola.h writel((val), (chip)->bar[idx].remap_addr + LOLA_##idx##_##name) val 385 sound/pci/lola/lola.h #define lola_writew(chip, idx, name, val) \ val 386 sound/pci/lola/lola.h writew((val), (chip)->bar[idx].remap_addr + LOLA_##idx##_##name) val 387 sound/pci/lola/lola.h #define lola_writeb(chip, idx, name, val) \ val 388 sound/pci/lola/lola.h writeb((val), (chip)->bar[idx].remap_addr + LOLA_##idx##_##name) val 393 sound/pci/lola/lola.h #define lola_dsd_write(chip, dsd, name, val) \ val 394 sound/pci/lola/lola.h writel((val), (chip)->bar[BAR1].remap_addr + LOLA_BAR1_DSD0_OFFSET + \ val 476 sound/pci/lola/lola.h unsigned int *val, unsigned int *extval); val 478 sound/pci/lola/lola.h #define lola_read_param(chip, nid, param, val) \ val 479 sound/pci/lola/lola.h lola_codec_read(chip, nid, LOLA_VERB_PARAMETERS, param, 0, val, NULL) val 489 sound/pci/lola/lola.h int lola_set_granularity(struct lola *chip, unsigned int val, bool force); val 494 sound/pci/lola/lola.h bool lola_update_ext_clock_freq(struct lola *chip, unsigned int val); val 56 sound/pci/lola/lola_clock.c unsigned int val, val 62 sound/pci/lola/lola_clock.c if (val < LOLA_GRANULARITY_MIN || val > LOLA_GRANULARITY_MAX || val 63 sound/pci/lola/lola_clock.c (val % LOLA_GRANULARITY_STEP) != 0) val 66 sound/pci/lola/lola_clock.c if (val == LOLA_GRANULARITY_MIN) { val 69 sound/pci/lola/lola_clock.c } else if (val < LOLA_GRANULARITY_MAX) { val 76 sound/pci/lola/lola_clock.c int lola_set_granularity(struct lola *chip, unsigned int val, bool force) val 81 sound/pci/lola/lola_clock.c if (val == chip->granularity) val 88 sound/pci/lola/lola_clock.c if (!check_gran_clock_compatibility(chip, val, val 93 sound/pci/lola/lola_clock.c chip->granularity = val; val 94 sound/pci/lola/lola_clock.c val /= LOLA_GRANULARITY_STEP; val 98 sound/pci/lola/lola_clock.c val, 0); val 102 sound/pci/lola/lola_clock.c usleep_range(400 * val, 20000); val 112 sound/pci/lola/lola_clock.c unsigned int val; val 116 sound/pci/lola/lola_clock.c err = lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); val 122 sound/pci/lola/lola_clock.c if ((val & 0xfff00000) != 0x01f00000) { /* test SubType and Type */ val 128 sound/pci/lola/lola_clock.c chip->clock.items = val & 0xff; val 146 sound/pci/lola/lola_clock.c idx, 0, &val, &res_ex); val 152 sound/pci/lola/lola_clock.c items[0] = val & 0xfff; val 153 sound/pci/lola/lola_clock.c items[1] = (val >> 16) & 0xfff; val 238 sound/pci/lola/lola_clock.c bool lola_update_ext_clock_freq(struct lola *chip, unsigned int val) val 245 sound/pci/lola/lola_clock.c if (!val) val 247 sound/pci/lola/lola_clock.c tag = (val >> LOLA_UNSOL_RESP_TAG_OFFSET) & LOLA_UNSOLICITED_TAG_MASK; val 254 sound/pci/lola/lola_clock.c chip->clock.cur_freq = lola_sample_rate_convert(val & 0x7f); val 255 sound/pci/lola/lola_clock.c chip->clock.cur_valid = (val & 0x100) != 0; val 21 sound/pci/lola/lola_mixer.c unsigned int val; val 25 sound/pci/lola/lola_mixer.c err = lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); val 30 sound/pci/lola/lola_mixer.c val &= 0x00f00fff; /* test TYPE and bits 0..11 */ val 31 sound/pci/lola/lola_mixer.c if (val == 0x00400200) /* Type = 4, Digital = 1 */ val 33 sound/pci/lola/lola_mixer.c else if (val == 0x0040000a && dir == CAPT) /* Dig=0, InAmp/ovrd */ val 35 sound/pci/lola/lola_mixer.c else if (val == 0x0040000c && dir == PLAY) /* Dig=0, OutAmp/ovrd */ val 38 sound/pci/lola/lola_mixer.c dev_err(chip->card->dev, "Invalid wcaps 0x%x for 0x%x\n", val, nid); val 48 sound/pci/lola/lola_mixer.c err = lola_read_param(chip, nid, LOLA_PAR_AMP_OUT_CAP, &val); val 50 sound/pci/lola/lola_mixer.c err = lola_read_param(chip, nid, LOLA_PAR_AMP_IN_CAP, &val); val 56 sound/pci/lola/lola_mixer.c pin->amp_mute = LOLA_AMP_MUTE_CAPABLE(val); val 57 sound/pci/lola/lola_mixer.c pin->amp_step_size = LOLA_AMP_STEP_SIZE(val); val 58 sound/pci/lola/lola_mixer.c pin->amp_num_steps = LOLA_AMP_NUM_STEPS(val); val 64 sound/pci/lola/lola_mixer.c pin->amp_offset = LOLA_AMP_OFFSET(val); val 66 sound/pci/lola/lola_mixer.c err = lola_codec_read(chip, nid, LOLA_VERB_GET_MAX_LEVEL, 0, 0, &val, val 72 sound/pci/lola/lola_mixer.c pin->max_level = val & 0x3ff; /* 10 bits */ val 103 sound/pci/lola/lola_mixer.c unsigned int val; val 106 sound/pci/lola/lola_mixer.c err = lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); val 112 sound/pci/lola/lola_mixer.c if ((val & 0xfff00000) != 0x02f00000) { /* test SubType and Type */ val 118 sound/pci/lola/lola_mixer.c chip->mixer.caps = val; val 137 sound/pci/lola/lola_mixer.c LOLA_MIXER_SRC_INPUT_PLAY_SEPARATION(val); val 139 sound/pci/lola/lola_mixer.c LOLA_MIXER_DEST_REC_OUTPUT_SEPARATION(val); val 211 sound/pci/lola/lola_mixer.c unsigned int oldval, val; val 215 sound/pci/lola/lola_mixer.c oldval = val = readl(&chip->mixer.array->src_gain_enable); val 217 sound/pci/lola/lola_mixer.c val |= (1 << id); val 219 sound/pci/lola/lola_mixer.c val &= ~(1 << id); val 221 sound/pci/lola/lola_mixer.c if ((val == oldval) && val 227 sound/pci/lola/lola_mixer.c id, gain, val); val 229 sound/pci/lola/lola_mixer.c writel(val, &chip->mixer.array->src_gain_enable); val 272 sound/pci/lola/lola_mixer.c unsigned int val; val 279 sound/pci/lola/lola_mixer.c val = readl(&chip->mixer.array->dest_mix_gain_enable[dest]); val 281 sound/pci/lola/lola_mixer.c val |= (1 << src); val 283 sound/pci/lola/lola_mixer.c val &= ~(1 << src); val 284 sound/pci/lola/lola_mixer.c writel(val, &chip->mixer.array->dest_mix_gain_enable[dest]); val 317 sound/pci/lola/lola_mixer.c unsigned int idx, unsigned int val, val 329 sound/pci/lola/lola_mixer.c unsigned int val = mute ? 0 : pin[idx].cur_gain_step; val 331 sound/pci/lola/lola_mixer.c set_analog_volume(chip, dir, idx, val, false); val 384 sound/pci/lola/lola_mixer.c unsigned int idx, unsigned int val, val 393 sound/pci/lola/lola_mixer.c if (!pin->is_analog || pin->amp_num_steps <= val) val 395 sound/pci/lola/lola_mixer.c if (external_call && pin->cur_gain_step == val) val 401 sound/pci/lola/lola_mixer.c dir, idx, val); val 403 sound/pci/lola/lola_mixer.c LOLA_VERB_SET_AMP_GAIN_MUTE, val, 0); val 407 sound/pci/lola/lola_mixer.c pin->cur_gain_step = val; val 682 sound/pci/lola/lola_mixer.c unsigned short val; val 686 sound/pci/lola/lola_mixer.c val = readw(&chip->mixer.array->src_gain[idx]) + 1; val 688 sound/pci/lola/lola_mixer.c val = 0; val 689 sound/pci/lola/lola_mixer.c ucontrol->value.integer.value[i] = val; val 704 sound/pci/lola/lola_mixer.c unsigned short val = ucontrol->value.integer.value[i]; val 705 sound/pci/lola/lola_mixer.c if (val) val 706 sound/pci/lola/lola_mixer.c val--; val 707 sound/pci/lola/lola_mixer.c err = lola_mixer_set_src_gain(chip, idx, val, !!val); val 765 sound/pci/lola/lola_mixer.c unsigned short val; val 769 sound/pci/lola/lola_mixer.c val = readw(&chip->mixer.array->dest_mix_gain[dst][src]) + 1; val 771 sound/pci/lola/lola_mixer.c val = 0; val 772 sound/pci/lola/lola_mixer.c ucontrol->value.integer.value[i] = val; val 791 sound/pci/lola/lola_mixer.c unsigned short val = ucontrol->value.integer.value[i]; val 792 sound/pci/lola/lola_mixer.c if (val) { val 793 sound/pci/lola/lola_mixer.c gains[num++] = val - 1; val 54 sound/pci/lola/lola_pcm.c unsigned int val = lola_dsd_read(chip, str->dsd, STS); val 55 sound/pci/lola/lola_pcm.c val &= LOLA_DSD_STS_DESE | LOLA_DSD_STS_BCIS; val 56 sound/pci/lola/lola_pcm.c if (val) val 57 sound/pci/lola/lola_pcm.c lola_dsd_write(chip, str->dsd, STS, val); val 87 sound/pci/lola/lola_pcm.c unsigned int val; val 88 sound/pci/lola/lola_pcm.c val = lola_dsd_read(chip, str->dsd, CTL); val 89 sound/pci/lola/lola_pcm.c if (!(val & LOLA_DSD_CTL_SRST)) val 100 sound/pci/lola/lola_pcm.c unsigned int val = ready ? LOLA_DSD_STS_FIFORDY : 0; val 104 sound/pci/lola/lola_pcm.c if ((reg & LOLA_DSD_STS_FIFORDY) == val) val 119 sound/pci/lola/lola_pcm.c unsigned int val = ready ? LOLA_DSD_STS_FIFORDY : 0; val 134 sound/pci/lola/lola_pcm.c if ((reg & LOLA_DSD_STS_FIFORDY) != val) { val 397 sound/pci/lola/lola_pcm.c unsigned int verb, val; val 403 sound/pci/lola/lola_pcm.c str->format_verb, 0, &val, NULL); val 415 sound/pci/lola/lola_pcm.c &val, NULL); val 632 sound/pci/lola/lola_pcm.c unsigned int val; val 640 sound/pci/lola/lola_pcm.c err = lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); val 647 sound/pci/lola/lola_pcm.c if ((val & 0x00f00dff) != 0x00000010) { val 650 sound/pci/lola/lola_pcm.c val, nid); val 657 sound/pci/lola/lola_pcm.c if ((val & 0x00f00cff) != 0x00100010) { val 660 sound/pci/lola/lola_pcm.c val, nid); val 664 sound/pci/lola/lola_pcm.c if ((val & 0x00001200) == 0x00001200) val 668 sound/pci/lola/lola_pcm.c err = lola_read_param(chip, nid, LOLA_PAR_STREAM_FORMATS, &val); val 673 sound/pci/lola/lola_pcm.c val &= 3; val 674 sound/pci/lola/lola_pcm.c if (val == 3) val 676 sound/pci/lola/lola_pcm.c if (!(val & 1)) { val 678 sound/pci/lola/lola_pcm.c "Invalid formats 0x%x for 0x%x", val, nid); val 19 sound/pci/lola/lola_proc.c unsigned int val; val 21 sound/pci/lola/lola_proc.c lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); val 22 sound/pci/lola/lola_proc.c snd_iprintf(buffer, "Node 0x%02x %s wcaps 0x%x\n", nid, name, val); val 23 sound/pci/lola/lola_proc.c lola_read_param(chip, nid, LOLA_PAR_STREAM_FORMATS, &val); val 24 sound/pci/lola/lola_proc.c snd_iprintf(buffer, " Formats: 0x%x\n", val); val 31 sound/pci/lola/lola_proc.c unsigned int val; val 33 sound/pci/lola/lola_proc.c lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); val 34 sound/pci/lola/lola_proc.c snd_iprintf(buffer, "Node 0x%02x %s wcaps 0x%x\n", nid, name, val); val 35 sound/pci/lola/lola_proc.c if (val == 0x00400200) val 37 sound/pci/lola/lola_proc.c lola_read_param(chip, nid, ampcap, &val); val 38 sound/pci/lola/lola_proc.c snd_iprintf(buffer, " Amp-Caps: 0x%x\n", val); val 40 sound/pci/lola/lola_proc.c LOLA_AMP_MUTE_CAPABLE(val), val 41 sound/pci/lola/lola_proc.c LOLA_AMP_STEP_SIZE(val), val 42 sound/pci/lola/lola_proc.c LOLA_AMP_NUM_STEPS(val), val 43 sound/pci/lola/lola_proc.c LOLA_AMP_OFFSET(val)); val 44 sound/pci/lola/lola_proc.c lola_codec_read(chip, nid, LOLA_VERB_GET_MAX_LEVEL, 0, 0, &val, NULL); val 45 sound/pci/lola/lola_proc.c snd_iprintf(buffer, " Max-level: 0x%x\n", val); val 52 sound/pci/lola/lola_proc.c unsigned int val; val 54 sound/pci/lola/lola_proc.c lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); val 55 sound/pci/lola/lola_proc.c snd_iprintf(buffer, "Node 0x%02x [Clock] wcaps 0x%x\n", nid, val); val 56 sound/pci/lola/lola_proc.c num_clocks = val & 0xff; val 63 sound/pci/lola/lola_proc.c i, 0, &val, &res_ex); val 64 sound/pci/lola/lola_proc.c items[0] = val & 0xfff; val 65 sound/pci/lola/lola_proc.c items[1] = (val >> 16) & 0xfff; val 91 sound/pci/lola/lola_proc.c unsigned int val; val 93 sound/pci/lola/lola_proc.c lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); val 94 sound/pci/lola/lola_proc.c snd_iprintf(buffer, "Node 0x%02x [Mixer] wcaps 0x%x\n", nid, val); val 101 sound/pci/lola/lola_proc.c unsigned int val; val 104 sound/pci/lola/lola_proc.c lola_read_param(chip, 0, LOLA_PAR_VENDOR_ID, &val); val 105 sound/pci/lola/lola_proc.c snd_iprintf(buffer, "Vendor: 0x%08x\n", val); val 106 sound/pci/lola/lola_proc.c lola_read_param(chip, 1, LOLA_PAR_FUNCTION_TYPE, &val); val 107 sound/pci/lola/lola_proc.c snd_iprintf(buffer, "Function Type: %d\n", val); val 108 sound/pci/lola/lola_proc.c lola_read_param(chip, 1, LOLA_PAR_SPECIFIC_CAPS, &val); val 109 sound/pci/lola/lola_proc.c snd_iprintf(buffer, "Specific-Caps: 0x%08x\n", val); val 974 sound/pci/maestro3.c static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val) val 978 sound/pci/maestro3.c val); val 984 sound/pci/maestro3.c u16 val; val 988 sound/pci/maestro3.c val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, val 992 sound/pci/maestro3.c val); val 1259 sound/pci/maestro3.c u16 addr, val; val 1319 sound/pci/maestro3.c s->inst.data + pv[i].addr, pv[i].val); val 1326 sound/pci/maestro3.c u16 addr, val; val 1377 sound/pci/maestro3.c s->inst.data + rv[i].addr, rv[i].val); val 1531 sound/pci/maestro3.c int x, val; val 1561 sound/pci/maestro3.c val = snd_ac97_read(chip->ac97, AC97_MASTER); val 1567 sound/pci/maestro3.c val ^= 0x8000; val 1571 sound/pci/maestro3.c if ((val & 0x7f) > 0) val 1572 sound/pci/maestro3.c val--; val 1573 sound/pci/maestro3.c if ((val & 0x7f00) > 0) val 1574 sound/pci/maestro3.c val -= 0x0100; val 1578 sound/pci/maestro3.c if ((val & 0x7f) < 0x1f) val 1579 sound/pci/maestro3.c val++; val 1580 sound/pci/maestro3.c if ((val & 0x7f00) < 0x1f00) val 1581 sound/pci/maestro3.c val += 0x0100; val 1584 sound/pci/maestro3.c if (snd_ac97_update(chip->ac97, AC97_MASTER, val)) val 1591 sound/pci/maestro3.c val = 0; val 1597 sound/pci/maestro3.c val = KEY_MUTE; val 1601 sound/pci/maestro3.c val = KEY_VOLUMEUP; val 1605 sound/pci/maestro3.c val = KEY_VOLUMEDOWN; val 1609 sound/pci/maestro3.c if (val) { val 1610 sound/pci/maestro3.c input_report_key(chip->input_dev, val, 1); val 1612 sound/pci/maestro3.c input_report_key(chip->input_dev, val, 0); val 1909 sound/pci/maestro3.c snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) val 1915 sound/pci/maestro3.c snd_m3_outw(chip, val, CODEC_DATA); val 1924 sound/pci/maestro3.c snd_m3_outw(chip, val, CODEC_DATA); val 2253 sound/pci/maestro3.c u16 val = GPI_VOL_DOWN | GPI_VOL_UP; val 2265 sound/pci/maestro3.c outw(~val, io + GPIO_MASK); val 2266 sound/pci/maestro3.c outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION); val 2267 sound/pci/maestro3.c outw(val, io + GPIO_MASK); val 2333 sound/pci/maestro3.c unsigned short val; val 2336 sound/pci/maestro3.c val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/; val 2338 sound/pci/maestro3.c val |= HV_INT_ENABLE; val 2339 sound/pci/maestro3.c outb(val, chip->iobase + HOST_INT_STATUS); val 2340 sound/pci/maestro3.c outw(val, io + HOST_INT_CTRL); val 336 sound/pci/mixart/mixart_hwdep.c u32 val; val 494 sound/pci/mixart/mixart_hwdep.c val = readl_be( MIXART_MEM( mgr, MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET )); val 495 sound/pci/mixart/mixart_hwdep.c if (!val) val 499 sound/pci/mixart/mixart_hwdep.c memcpy_toio( MIXART_MEM( mgr, val), dsp->data, dsp->size); val 284 sound/pci/nm256/nm256.c snd_nm256_writeb(struct nm256 *chip, int offset, u8 val) val 286 sound/pci/nm256/nm256.c writeb(val, chip->cport + offset); val 290 sound/pci/nm256/nm256.c snd_nm256_writew(struct nm256 *chip, int offset, u16 val) val 292 sound/pci/nm256/nm256.c writew(val, chip->cport + offset); val 296 sound/pci/nm256/nm256.c snd_nm256_writel(struct nm256 *chip, int offset, u32 val) val 298 sound/pci/nm256/nm256.c writel(val, chip->cport + offset); val 1232 sound/pci/nm256/nm256.c unsigned short reg, unsigned short val) val 1248 sound/pci/nm256/nm256.c snd_nm256_writew(chip, base + reg, val); val 1252 sound/pci/nm256/nm256.c chip->ac97_regs[idx] = val; val 105 sound/pci/oxygen/xonar_dg_mixer.c struct snd_ctl_elem_value *val) val 113 sound/pci/oxygen/xonar_dg_mixer.c val->value.integer.value[0] = tmp; val 115 sound/pci/oxygen/xonar_dg_mixer.c val->value.integer.value[1] = tmp; val 121 sound/pci/oxygen/xonar_dg_mixer.c struct snd_ctl_elem_value *val) val 127 sound/pci/oxygen/xonar_dg_mixer.c long new1 = val->value.integer.value[0]; val 128 sound/pci/oxygen/xonar_dg_mixer.c long new2 = val->value.integer.value[1]; val 151 sound/pci/oxygen/xonar_dg_mixer.c struct snd_ctl_elem_value *val) val 157 sound/pci/oxygen/xonar_dg_mixer.c val->value.integer.value[0] = val 164 sound/pci/oxygen/xonar_dg_mixer.c struct snd_ctl_elem_value *val) val 171 sound/pci/oxygen/xonar_dg_mixer.c if (val->value.integer.value[0] > 1) val 176 sound/pci/oxygen/xonar_dg_mixer.c (~val->value.integer.value[0] << 2) & CS4245_MUTE_DAC; val 238 sound/pci/pcxhr/pcxhr.c unsigned int val, realfreq, pllreg; val 246 sound/pci/pcxhr/pcxhr.c case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break; val 247 sound/pci/pcxhr/pcxhr.c case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break; val 248 sound/pci/pcxhr/pcxhr.c case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break; val 249 sound/pci/pcxhr/pcxhr.c case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break; val 250 sound/pci/pcxhr/pcxhr.c case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break; val 251 sound/pci/pcxhr/pcxhr.c case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break; val 252 sound/pci/pcxhr/pcxhr.c case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break; val 253 sound/pci/pcxhr/pcxhr.c case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break; val 254 sound/pci/pcxhr/pcxhr.c case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break; val 255 sound/pci/pcxhr/pcxhr.c case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break; val 256 sound/pci/pcxhr/pcxhr.c case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break; val 257 sound/pci/pcxhr/pcxhr.c case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break; val 258 sound/pci/pcxhr/pcxhr.c case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break; val 259 sound/pci/pcxhr/pcxhr.c case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break; val 260 sound/pci/pcxhr/pcxhr.c case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break; val 262 sound/pci/pcxhr/pcxhr.c val = PCXHR_FREQ_PLL; val 282 sound/pci/pcxhr/pcxhr.c val = PCXHR_FREQ_WORD_CLOCK; val 285 sound/pci/pcxhr/pcxhr.c val = PCXHR_FREQ_SYNC_AES; val 288 sound/pci/pcxhr/pcxhr.c val = PCXHR_FREQ_AES_1; val 291 sound/pci/pcxhr/pcxhr.c val = PCXHR_FREQ_AES_2; val 294 sound/pci/pcxhr/pcxhr.c val = PCXHR_FREQ_AES_3; val 297 sound/pci/pcxhr/pcxhr.c val = PCXHR_FREQ_AES_4; val 302 sound/pci/pcxhr/pcxhr.c *reg = val; val 312 sound/pci/pcxhr/pcxhr.c unsigned int val, realfreq, speed; val 316 sound/pci/pcxhr/pcxhr.c err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq); val 347 sound/pci/pcxhr/pcxhr.c dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val); val 349 sound/pci/pcxhr/pcxhr.c val, changed); val 698 sound/pci/riptide/riptide.c u32 laddr, saddr, t, val; val 717 sound/pci/riptide/riptide.c val = atoh(&in[9], 8); val 718 sound/pci/riptide/riptide.c if (SEND_GOTO(cif, val) != 0) val 1728 sound/pci/riptide/riptide.c unsigned short val) val 1738 sound/pci/riptide/riptide.c snd_printdd("Write AC97 reg 0x%x 0x%x\n", reg, val); val 1740 sound/pci/riptide/riptide.c SEND_SACR(cif, val, reg); val 1742 sound/pci/riptide/riptide.c } while (rptr.retwords[1] != val && i++ < MAX_WRITE_RETRY); val 2052 sound/pci/riptide/riptide.c unsigned short val; val 2077 sound/pci/riptide/riptide.c val = LEGACY_ENABLE_ALL; val 2079 sound/pci/riptide/riptide.c val |= LEGACY_ENABLE_FM; val 2082 sound/pci/riptide/riptide.c val |= LEGACY_ENABLE_GAMEPORT; val 2085 sound/pci/riptide/riptide.c val |= LEGACY_ENABLE_MPU_INT | LEGACY_ENABLE_MPU; val 2086 sound/pci/riptide/riptide.c val |= (chip->irq << 4) & 0xf0; val 2087 sound/pci/riptide/riptide.c pci_write_config_word(chip->pci, PCI_EXT_Legacy_Mask, val); val 2089 sound/pci/riptide/riptide.c val = mpu_port[dev]; val 2090 sound/pci/riptide/riptide.c pci_write_config_word(chip->pci, PCI_EXT_MPU_Base, val); val 2092 sound/pci/riptide/riptide.c val, MPU401_INFO_IRQ_HOOK, -1, val 2097 sound/pci/riptide/riptide.c val); val 2099 sound/pci/riptide/riptide.c chip->mpuaddr = val; val 2102 sound/pci/riptide/riptide.c val = opl3_port[dev]; val 2103 sound/pci/riptide/riptide.c pci_write_config_word(chip->pci, PCI_EXT_FM_Base, val); val 2104 sound/pci/riptide/riptide.c err = snd_opl3_create(card, val, val + 2, val 2109 sound/pci/riptide/riptide.c val); val 2111 sound/pci/riptide/riptide.c chip->opladdr = val; val 2120 sound/pci/riptide/riptide.c val = joystick_port[dev]; val 2121 sound/pci/riptide/riptide.c pci_write_config_word(chip->pci, PCI_EXT_Game_Base, val); val 2122 sound/pci/riptide/riptide.c chip->gameaddr = val; val 1583 sound/pci/rme32.c unsigned int val; val 1586 sound/pci/rme32.c val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL; val 1588 sound/pci/rme32.c val = (rme32->wcreg & ~RME32_WCR_SEL) | val; val 1589 sound/pci/rme32.c change = val != rme32->wcreg; val 1591 sound/pci/rme32.c val &= ~RME32_WCR_MUTE; val 1593 sound/pci/rme32.c val |= RME32_WCR_MUTE; val 1594 sound/pci/rme32.c rme32->wcreg = val; val 1595 sound/pci/rme32.c writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER); val 1658 sound/pci/rme32.c unsigned int val; val 1673 sound/pci/rme32.c val = ucontrol->value.enumerated.item[0] % items; val 1676 sound/pci/rme32.c change = val != (unsigned int)snd_rme32_getinputtype(rme32); val 1677 sound/pci/rme32.c snd_rme32_setinputtype(rme32, val); val 1709 sound/pci/rme32.c unsigned int val; val 1712 sound/pci/rme32.c val = ucontrol->value.enumerated.item[0] % 3; val 1714 sound/pci/rme32.c change = val != (unsigned int)snd_rme32_getclockmode(rme32); val 1715 sound/pci/rme32.c snd_rme32_setclockmode(rme32, val); val 1722 sound/pci/rme32.c u32 val = 0; val 1723 sound/pci/rme32.c val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0; val 1724 sound/pci/rme32.c if (val & RME32_WCR_PRO) val 1725 sound/pci/rme32.c val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0; val 1727 sound/pci/rme32.c val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0; val 1728 sound/pci/rme32.c return val; val 1731 sound/pci/rme32.c static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val) val 1733 sound/pci/rme32.c aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0); val 1734 sound/pci/rme32.c if (val & RME32_WCR_PRO) val 1735 sound/pci/rme32.c aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; val 1737 sound/pci/rme32.c aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; val 1763 sound/pci/rme32.c u32 val; val 1765 sound/pci/rme32.c val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); val 1767 sound/pci/rme32.c change = val != rme32->wcreg_spdif; val 1768 sound/pci/rme32.c rme32->wcreg_spdif = val; val 1798 sound/pci/rme32.c u32 val; val 1800 sound/pci/rme32.c val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); val 1802 sound/pci/rme32.c change = val != rme32->wcreg_spdif_stream; val 1803 sound/pci/rme32.c rme32->wcreg_spdif_stream = val; val 1805 sound/pci/rme32.c rme32->wcreg |= val; val 499 sound/pci/rme96.c snd_rme96_write_SPI(struct rme96 *rme96, u16 val) val 504 sound/pci/rme96.c if (val & 0x8000) { val 515 sound/pci/rme96.c val <<= 1; val 1880 sound/pci/rme96.c unsigned int val; val 1883 sound/pci/rme96.c val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; val 1885 sound/pci/rme96.c val = (rme96->wcreg & ~RME96_WCR_SEL) | val; val 1886 sound/pci/rme96.c change = val != rme96->wcreg; val 1887 sound/pci/rme96.c rme96->wcreg = val; val 1888 sound/pci/rme96.c writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); val 1972 sound/pci/rme96.c unsigned int val; val 1994 sound/pci/rme96.c val = ucontrol->value.enumerated.item[0] % items; val 1998 sound/pci/rme96.c if (val == RME96_INPUT_XLR) { val 1999 sound/pci/rme96.c val = RME96_INPUT_ANALOG; val 2004 sound/pci/rme96.c change = (int)val != snd_rme96_getinputtype(rme96); val 2005 sound/pci/rme96.c snd_rme96_setinputtype(rme96, val); val 2031 sound/pci/rme96.c unsigned int val; val 2034 sound/pci/rme96.c val = ucontrol->value.enumerated.item[0] % 3; val 2036 sound/pci/rme96.c change = (int)val != snd_rme96_getclockmode(rme96); val 2037 sound/pci/rme96.c snd_rme96_setclockmode(rme96, val); val 2065 sound/pci/rme96.c unsigned int val; val 2068 sound/pci/rme96.c val = ucontrol->value.enumerated.item[0] % 4; val 2071 sound/pci/rme96.c change = (int)val != snd_rme96_getattenuation(rme96); val 2072 sound/pci/rme96.c snd_rme96_setattenuation(rme96, val); val 2098 sound/pci/rme96.c unsigned int val; val 2101 sound/pci/rme96.c val = ucontrol->value.enumerated.item[0] % 4; val 2103 sound/pci/rme96.c change = (int)val != snd_rme96_getmontracks(rme96); val 2104 sound/pci/rme96.c snd_rme96_setmontracks(rme96, val); val 2111 sound/pci/rme96.c u32 val = 0; val 2112 sound/pci/rme96.c val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; val 2113 sound/pci/rme96.c val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; val 2114 sound/pci/rme96.c if (val & RME96_WCR_PRO) val 2115 sound/pci/rme96.c val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; val 2117 sound/pci/rme96.c val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; val 2118 sound/pci/rme96.c return val; val 2121 sound/pci/rme96.c static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) val 2123 sound/pci/rme96.c aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | val 2124 sound/pci/rme96.c ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); val 2125 sound/pci/rme96.c if (val & RME96_WCR_PRO) val 2126 sound/pci/rme96.c aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; val 2128 sound/pci/rme96.c aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; val 2150 sound/pci/rme96.c u32 val; val 2152 sound/pci/rme96.c val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); val 2154 sound/pci/rme96.c change = val != rme96->wcreg_spdif; val 2155 sound/pci/rme96.c rme96->wcreg_spdif = val; val 2179 sound/pci/rme96.c u32 val; val 2181 sound/pci/rme96.c val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); val 2183 sound/pci/rme96.c change = val != rme96->wcreg_spdif_stream; val 2184 sound/pci/rme96.c rme96->wcreg_spdif_stream = val; val 2186 sound/pci/rme96.c rme96->wcreg |= val; val 2448 sound/pci/rme96.c u8 val; val 2494 sound/pci/rme96.c pci_read_config_byte(rme96->pci, 8, &val); val 2495 sound/pci/rme96.c if (val < 5) { val 646 sound/pci/rme9652/hdsp.c static void hdsp_write(struct hdsp *hdsp, int reg, int val) val 648 sound/pci/rme9652/hdsp.c writel(val, hdsp->iobase + reg); val 1277 sound/pci/rme9652/hdsp.c static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val) val 1281 sound/pci/rme9652/hdsp.c hdsp_write(hdsp, HDSP_midiDataOut1, val); val 1283 sound/pci/rme9652/hdsp.c hdsp_write(hdsp, HDSP_midiDataOut0, val); val 1546 sound/pci/rme9652/hdsp.c u32 val = 0; val 1547 sound/pci/rme9652/hdsp.c val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; val 1548 sound/pci/rme9652/hdsp.c val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; val 1549 sound/pci/rme9652/hdsp.c if (val & HDSP_SPDIFProfessional) val 1550 sound/pci/rme9652/hdsp.c val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; val 1552 sound/pci/rme9652/hdsp.c val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; val 1553 sound/pci/rme9652/hdsp.c return val; val 1556 sound/pci/rme9652/hdsp.c static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) val 1558 sound/pci/rme9652/hdsp.c aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | val 1559 sound/pci/rme9652/hdsp.c ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); val 1560 sound/pci/rme9652/hdsp.c if (val & HDSP_SPDIFProfessional) val 1561 sound/pci/rme9652/hdsp.c aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; val 1563 sound/pci/rme9652/hdsp.c aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; val 1585 sound/pci/rme9652/hdsp.c u32 val; val 1587 sound/pci/rme9652/hdsp.c val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); val 1589 sound/pci/rme9652/hdsp.c change = val != hdsp->creg_spdif; val 1590 sound/pci/rme9652/hdsp.c hdsp->creg_spdif = val; val 1614 sound/pci/rme9652/hdsp.c u32 val; val 1616 sound/pci/rme9652/hdsp.c val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); val 1618 sound/pci/rme9652/hdsp.c change = val != hdsp->creg_spdif_stream; val 1619 sound/pci/rme9652/hdsp.c hdsp->creg_spdif_stream = val; val 1621 sound/pci/rme9652/hdsp.c hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); val 1683 sound/pci/rme9652/hdsp.c unsigned int val; val 1687 sound/pci/rme9652/hdsp.c val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); val 1689 sound/pci/rme9652/hdsp.c change = val != hdsp_spdif_in(hdsp); val 1691 sound/pci/rme9652/hdsp.c hdsp_set_spdif_input(hdsp, val); val 1741 sound/pci/rme9652/hdsp.c unsigned int val; val 1745 sound/pci/rme9652/hdsp.c val = ucontrol->value.integer.value[0] & 1; val 1747 sound/pci/rme9652/hdsp.c change = (int) val != hdsp_toggle_setting(hdsp, regmask); val 1749 sound/pci/rme9652/hdsp.c hdsp_set_toggle_setting(hdsp, regmask, val); val 2043 sound/pci/rme9652/hdsp.c int val; val 2047 sound/pci/rme9652/hdsp.c val = ucontrol->value.enumerated.item[0]; val 2048 sound/pci/rme9652/hdsp.c if (val < 0) val = 0; val 2050 sound/pci/rme9652/hdsp.c if (val > 9) val 2051 sound/pci/rme9652/hdsp.c val = 9; val 2053 sound/pci/rme9652/hdsp.c if (val > 6) val 2054 sound/pci/rme9652/hdsp.c val = 6; val 2057 sound/pci/rme9652/hdsp.c if (val != hdsp_clock_source(hdsp)) val 2058 sound/pci/rme9652/hdsp.c change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; val 2149 sound/pci/rme9652/hdsp.c int val; val 2153 sound/pci/rme9652/hdsp.c val = ucontrol->value.enumerated.item[0]; val 2154 sound/pci/rme9652/hdsp.c if (val < 0) val = 0; val 2155 sound/pci/rme9652/hdsp.c if (val > 2) val = 2; val 2157 sound/pci/rme9652/hdsp.c if (val != hdsp_da_gain(hdsp)) val 2158 sound/pci/rme9652/hdsp.c change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; val 2228 sound/pci/rme9652/hdsp.c int val; val 2232 sound/pci/rme9652/hdsp.c val = ucontrol->value.enumerated.item[0]; val 2233 sound/pci/rme9652/hdsp.c if (val < 0) val = 0; val 2234 sound/pci/rme9652/hdsp.c if (val > 2) val = 2; val 2236 sound/pci/rme9652/hdsp.c if (val != hdsp_ad_gain(hdsp)) val 2237 sound/pci/rme9652/hdsp.c change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; val 2307 sound/pci/rme9652/hdsp.c int val; val 2311 sound/pci/rme9652/hdsp.c val = ucontrol->value.enumerated.item[0]; val 2312 sound/pci/rme9652/hdsp.c if (val < 0) val = 0; val 2313 sound/pci/rme9652/hdsp.c if (val > 2) val = 2; val 2315 sound/pci/rme9652/hdsp.c if (val != hdsp_phone_gain(hdsp)) val 2316 sound/pci/rme9652/hdsp.c change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; val 2424 sound/pci/rme9652/hdsp.c unsigned int val; val 2444 sound/pci/rme9652/hdsp.c val = ucontrol->value.enumerated.item[0] % max; val 2446 sound/pci/rme9652/hdsp.c change = (int)val != hdsp_pref_sync_ref(hdsp); val 2447 sound/pci/rme9652/hdsp.c hdsp_set_pref_sync_ref(hdsp, val); val 2538 sound/pci/rme9652/hdsp.c unsigned int val; val 2542 sound/pci/rme9652/hdsp.c val = ucontrol->value.integer.value[0] & 1; val 2544 sound/pci/rme9652/hdsp.c change = (int)val != hdsp->precise_ptr; val 2545 sound/pci/rme9652/hdsp.c hdsp_set_precise_pointer(hdsp, val); val 2584 sound/pci/rme9652/hdsp.c unsigned int val; val 2588 sound/pci/rme9652/hdsp.c val = ucontrol->value.integer.value[0] & 1; val 2590 sound/pci/rme9652/hdsp.c change = (int)val != hdsp->use_midi_tasklet; val 2591 sound/pci/rme9652/hdsp.c hdsp_set_use_midi_tasklet(hdsp, val); val 2873 sound/pci/rme9652/hdsp.c int val; val 2877 sound/pci/rme9652/hdsp.c val = ucontrol->value.integer.value[0]; val 2879 sound/pci/rme9652/hdsp.c if (val != hdsp_dds_offset(hdsp)) val 2880 sound/pci/rme9652/hdsp.c change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0; val 3018 sound/pci/rme9652/hdsp.c int val; val 3022 sound/pci/rme9652/hdsp.c val = ucontrol->value.enumerated.item[0]; val 3023 sound/pci/rme9652/hdsp.c if (val < 0) val 3024 sound/pci/rme9652/hdsp.c val = 0; val 3025 sound/pci/rme9652/hdsp.c if (val > 4) val 3026 sound/pci/rme9652/hdsp.c val = 4; val 3028 sound/pci/rme9652/hdsp.c if (val != hdsp_rpm_input12(hdsp)) val 3029 sound/pci/rme9652/hdsp.c change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0; val 3103 sound/pci/rme9652/hdsp.c int val; val 3107 sound/pci/rme9652/hdsp.c val = ucontrol->value.enumerated.item[0]; val 3108 sound/pci/rme9652/hdsp.c if (val < 0) val 3109 sound/pci/rme9652/hdsp.c val = 0; val 3110 sound/pci/rme9652/hdsp.c if (val > 4) val 3111 sound/pci/rme9652/hdsp.c val = 4; val 3113 sound/pci/rme9652/hdsp.c if (val != hdsp_rpm_input34(hdsp)) val 3114 sound/pci/rme9652/hdsp.c change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0; val 3153 sound/pci/rme9652/hdsp.c unsigned int val; val 3157 sound/pci/rme9652/hdsp.c val = ucontrol->value.integer.value[0] & 1; val 3159 sound/pci/rme9652/hdsp.c change = (int)val != hdsp_rpm_bypass(hdsp); val 3160 sound/pci/rme9652/hdsp.c hdsp_set_rpm_bypass(hdsp, val); val 3205 sound/pci/rme9652/hdsp.c unsigned int val; val 3209 sound/pci/rme9652/hdsp.c val = ucontrol->value.integer.value[0] & 1; val 3211 sound/pci/rme9652/hdsp.c change = (int)val != hdsp_rpm_disconnect(hdsp); val 3212 sound/pci/rme9652/hdsp.c hdsp_set_rpm_disconnect(hdsp, val); val 4569 sound/pci/rme9652/hdsp.c u32 val = readl(src); val 4570 sound/pci/rme9652/hdsp.c return copy_to_user(dest, &val, 4); val 1132 sound/pci/rme9652/hdspm.c unsigned int val) val 1134 sound/pci/rme9652/hdspm.c writel(val, hdspm->iobase + reg); val 1813 sound/pci/rme9652/hdspm.c int val) val 1816 sound/pci/rme9652/hdspm.c return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); val 2571 sound/pci/rme9652/hdspm.c int val; val 2576 sound/pci/rme9652/hdspm.c val = ucontrol->value.enumerated.item[0]; val 2577 sound/pci/rme9652/hdspm.c if (val < 0) val 2578 sound/pci/rme9652/hdspm.c val = 0; val 2579 sound/pci/rme9652/hdspm.c else if (val > 1) val 2580 sound/pci/rme9652/hdspm.c val = 1; val 2582 sound/pci/rme9652/hdspm.c hdspm_set_system_clock_mode(hdspm, val); val 2664 sound/pci/rme9652/hdspm.c int val; val 2668 sound/pci/rme9652/hdspm.c val = ucontrol->value.enumerated.item[0]; val 2669 sound/pci/rme9652/hdspm.c if (val < 0) val 2670 sound/pci/rme9652/hdspm.c val = 0; val 2671 sound/pci/rme9652/hdspm.c if (val > 9) val 2672 sound/pci/rme9652/hdspm.c val = 9; val 2674 sound/pci/rme9652/hdspm.c if (val != hdspm_clock_source(hdspm)) val 2675 sound/pci/rme9652/hdspm.c change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; val 2989 sound/pci/rme9652/hdspm.c int val, change = 0; val 2994 sound/pci/rme9652/hdspm.c val = ucontrol->value.enumerated.item[0]; val 2996 sound/pci/rme9652/hdspm.c if (val < 0) val 2997 sound/pci/rme9652/hdspm.c val = 0; val 2998 sound/pci/rme9652/hdspm.c else if (val >= hdspm->texts_autosync_items) val 2999 sound/pci/rme9652/hdspm.c val = hdspm->texts_autosync_items-1; val 3002 sound/pci/rme9652/hdspm.c if (val != hdspm_pref_sync_ref(hdspm)) val 3003 sound/pci/rme9652/hdspm.c change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; val 3253 sound/pci/rme9652/hdspm.c unsigned int val; val 3257 sound/pci/rme9652/hdspm.c val = ucontrol->value.integer.value[0] & 1; val 3259 sound/pci/rme9652/hdspm.c change = (int) val != hdspm_toggle_setting(hdspm, regmask); val 3260 sound/pci/rme9652/hdspm.c hdspm_set_toggle_setting(hdspm, regmask, val); val 3314 sound/pci/rme9652/hdspm.c unsigned int val; val 3318 sound/pci/rme9652/hdspm.c val = ucontrol->value.integer.value[0] & 1; val 3320 sound/pci/rme9652/hdspm.c change = (int) val != hdspm_input_select(hdspm); val 3321 sound/pci/rme9652/hdspm.c hdspm_set_input_select(hdspm, val); val 3376 sound/pci/rme9652/hdspm.c unsigned int val; val 3380 sound/pci/rme9652/hdspm.c val = ucontrol->value.integer.value[0] & 1; val 3382 sound/pci/rme9652/hdspm.c change = (int) val != hdspm_ds_wire(hdspm); val 3383 sound/pci/rme9652/hdspm.c hdspm_set_ds_wire(hdspm, val); val 3449 sound/pci/rme9652/hdspm.c int val; val 3453 sound/pci/rme9652/hdspm.c val = ucontrol->value.integer.value[0]; val 3454 sound/pci/rme9652/hdspm.c if (val < 0) val 3455 sound/pci/rme9652/hdspm.c val = 0; val 3456 sound/pci/rme9652/hdspm.c if (val > 2) val 3457 sound/pci/rme9652/hdspm.c val = 2; val 3459 sound/pci/rme9652/hdspm.c change = val != hdspm_qs_wire(hdspm); val 3460 sound/pci/rme9652/hdspm.c hdspm_set_qs_wire(hdspm, val); val 3526 sound/pci/rme9652/hdspm.c int val; val 3530 sound/pci/rme9652/hdspm.c val = ucontrol->value.integer.value[0]; val 3531 sound/pci/rme9652/hdspm.c if (val < 0) val 3532 sound/pci/rme9652/hdspm.c val = 0; val 3533 sound/pci/rme9652/hdspm.c if (val > 2) val 3534 sound/pci/rme9652/hdspm.c val = 2; val 3537 sound/pci/rme9652/hdspm.c change = val != hdspm_tristate(hdspm, regmask); val 3538 sound/pci/rme9652/hdspm.c hdspm_set_tristate(hdspm, val, regmask); val 3603 sound/pci/rme9652/hdspm.c int val; val 3607 sound/pci/rme9652/hdspm.c val = ucontrol->value.integer.value[0]; val 3608 sound/pci/rme9652/hdspm.c if (val < 0) val 3609 sound/pci/rme9652/hdspm.c val = 0; val 3610 sound/pci/rme9652/hdspm.c if (val > 2) val 3611 sound/pci/rme9652/hdspm.c val = 2; val 3613 sound/pci/rme9652/hdspm.c change = val != hdspm_madi_speedmode(hdspm); val 3614 sound/pci/rme9652/hdspm.c hdspm_set_madi_speedmode(hdspm, val); val 4015 sound/pci/rme9652/hdspm.c int val = -1; val 4021 sound/pci/rme9652/hdspm.c val = hdspm_wc_sync_check(hdspm); break; val 4023 sound/pci/rme9652/hdspm.c val = hdspm_tco_sync_check(hdspm); break; val 4025 sound/pci/rme9652/hdspm.c val = hdspm_sync_in_sync_check(hdspm); break; val 4027 sound/pci/rme9652/hdspm.c val = hdspm_s1_sync_check(hdspm, val 4035 sound/pci/rme9652/hdspm.c val = hdspm_wc_sync_check(hdspm); break; val 4037 sound/pci/rme9652/hdspm.c val = hdspm_tco_sync_check(hdspm); break; val 4039 sound/pci/rme9652/hdspm.c val = hdspm_sync_in_sync_check(hdspm); break; val 4041 sound/pci/rme9652/hdspm.c val = hdspm_s1_sync_check(hdspm, val 4049 sound/pci/rme9652/hdspm.c val = hdspm_wc_sync_check(hdspm); break; val 4051 sound/pci/rme9652/hdspm.c val = hdspm_madi_sync_check(hdspm); break; val 4053 sound/pci/rme9652/hdspm.c val = hdspm_tco_sync_check(hdspm); break; val 4055 sound/pci/rme9652/hdspm.c val = hdspm_sync_in_sync_check(hdspm); break; val 4060 sound/pci/rme9652/hdspm.c val = hdspm_madi_sync_check(hdspm); /* MADI */ val 4066 sound/pci/rme9652/hdspm.c val = hdspm_wc_sync_check(hdspm); break; val 4068 sound/pci/rme9652/hdspm.c val = hdspm_tco_sync_check(hdspm); break; val 4070 sound/pci/rme9652/hdspm.c val = hdspm_sync_in_sync_check(hdspm); break; val 4072 sound/pci/rme9652/hdspm.c val = hdspm_aes_sync_check(hdspm, val 4083 sound/pci/rme9652/hdspm.c val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); val 4087 sound/pci/rme9652/hdspm.c val = hdspm_tco_input_check(hdspm, val 4095 sound/pci/rme9652/hdspm.c if (-1 == val) val 4096 sound/pci/rme9652/hdspm.c val = 3; val 4098 sound/pci/rme9652/hdspm.c ucontrol->value.enumerated.item[0] = val; val 6156 sound/pci/rme9652/hdspm.c u32 val = readl(src); val 6157 sound/pci/rme9652/hdspm.c return copy_to_user(dest, &val, 4); val 309 sound/pci/rme9652/rme9652.c static inline void rme9652_write(struct snd_rme9652 *rme9652, int reg, int val) val 311 sound/pci/rme9652/rme9652.c writel(val, rme9652->iobase + reg); val 634 sound/pci/rme9652/rme9652.c static void rme9652_spdif_write_byte (struct snd_rme9652 *rme9652, const int val) val 640 sound/pci/rme9652/rme9652.c if (val & mask) val 653 sound/pci/rme9652/rme9652.c long val; val 656 sound/pci/rme9652/rme9652.c val = 0; val 661 sound/pci/rme9652/rme9652.c val |= mask; val 665 sound/pci/rme9652/rme9652.c return val; val 777 sound/pci/rme9652/rme9652.c u32 val = 0; val 778 sound/pci/rme9652/rme9652.c val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME9652_PRO : 0; val 779 sound/pci/rme9652/rme9652.c val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME9652_Dolby : 0; val 780 sound/pci/rme9652/rme9652.c if (val & RME9652_PRO) val 781 sound/pci/rme9652/rme9652.c val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME9652_EMP : 0; val 783 sound/pci/rme9652/rme9652.c val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME9652_EMP : 0; val 784 sound/pci/rme9652/rme9652.c return val; val 787 sound/pci/rme9652/rme9652.c static void snd_rme9652_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) val 789 sound/pci/rme9652/rme9652.c aes->status[0] = ((val & RME9652_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | val 790 sound/pci/rme9652/rme9652.c ((val & RME9652_Dolby) ? IEC958_AES0_NONAUDIO : 0); val 791 sound/pci/rme9652/rme9652.c if (val & RME9652_PRO) val 792 sound/pci/rme9652/rme9652.c aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; val 794 sound/pci/rme9652/rme9652.c aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; val 816 sound/pci/rme9652/rme9652.c u32 val; val 818 sound/pci/rme9652/rme9652.c val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958); val 820 sound/pci/rme9652/rme9652.c change = val != rme9652->creg_spdif; val 821 sound/pci/rme9652/rme9652.c rme9652->creg_spdif = val; val 845 sound/pci/rme9652/rme9652.c u32 val; val 847 sound/pci/rme9652/rme9652.c val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958); val 849 sound/pci/rme9652/rme9652.c change = val != rme9652->creg_spdif_stream; val 850 sound/pci/rme9652/rme9652.c rme9652->creg_spdif_stream = val; val 852 sound/pci/rme9652/rme9652.c rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= val); val 929 sound/pci/rme9652/rme9652.c unsigned int val; val 933 sound/pci/rme9652/rme9652.c val = ucontrol->value.enumerated.item[0] % 2; val 935 sound/pci/rme9652/rme9652.c change = val != rme9652_adat1_in(rme9652); val 937 sound/pci/rme9652/rme9652.c rme9652_set_adat1_input(rme9652, val); val 994 sound/pci/rme9652/rme9652.c unsigned int val; val 998 sound/pci/rme9652/rme9652.c val = ucontrol->value.enumerated.item[0] % 3; val 1000 sound/pci/rme9652/rme9652.c change = val != rme9652_spdif_in(rme9652); val 1002 sound/pci/rme9652/rme9652.c rme9652_set_spdif_input(rme9652, val); val 1056 sound/pci/rme9652/rme9652.c unsigned int val; val 1060 sound/pci/rme9652/rme9652.c val = ucontrol->value.integer.value[0] & 1; val 1062 sound/pci/rme9652/rme9652.c change = (int)val != rme9652_spdif_out(rme9652); val 1063 sound/pci/rme9652/rme9652.c rme9652_set_spdif_output(rme9652, val); val 1139 sound/pci/rme9652/rme9652.c unsigned int val; val 1141 sound/pci/rme9652/rme9652.c val = ucontrol->value.enumerated.item[0] % 3; val 1143 sound/pci/rme9652/rme9652.c change = (int)val != rme9652_sync_mode(rme9652); val 1144 sound/pci/rme9652/rme9652.c rme9652_set_sync_mode(rme9652, val); val 1229 sound/pci/rme9652/rme9652.c unsigned int val; val 1234 sound/pci/rme9652/rme9652.c val = ucontrol->value.enumerated.item[0] % max; val 1236 sound/pci/rme9652/rme9652.c change = (int)val != rme9652_sync_pref(rme9652); val 1237 sound/pci/rme9652/rme9652.c rme9652_set_sync_pref(rme9652, val); val 1314 sound/pci/rme9652/rme9652.c unsigned int val; val 1320 sound/pci/rme9652/rme9652.c val = ucontrol->value.integer.value[0] & 1; val 1324 sound/pci/rme9652/rme9652.c err = rme9652_set_passthru(rme9652, val); val 1374 sound/pci/rme9652/rme9652.c unsigned int mask1, mask2, val; val 1382 sound/pci/rme9652/rme9652.c val = rme9652_read(rme9652, RME9652_status_register); val 1383 sound/pci/rme9652/rme9652.c ucontrol->value.enumerated.item[0] = (val & mask1) ? 1 : 0; val 1384 sound/pci/rme9652/rme9652.c ucontrol->value.enumerated.item[0] |= (val & mask2) ? 2 : 0; val 916 sound/pci/sis7019.c unsigned short val = 0xffff; val 966 sound/pci/sis7019.c val = inl(io + SIS_AC97_CMD) >> 16; val 978 sound/pci/sis7019.c return val; val 982 sound/pci/sis7019.c unsigned short val) val 990 sound/pci/sis7019.c (val << 16) | (reg << 8) | cmd[ac97->num]); val 985 sound/pci/sonicvibes.c unsigned short val, oval; val 987 sound/pci/sonicvibes.c val = (ucontrol->value.integer.value[0] & mask); val 989 sound/pci/sonicvibes.c val = mask - val; val 990 sound/pci/sonicvibes.c val <<= shift; val 993 sound/pci/sonicvibes.c val = (oval & ~(mask << shift)) | val; val 994 sound/pci/sonicvibes.c change = val != oval; val 995 sound/pci/sonicvibes.c snd_sonicvibes_out1(sonic, reg, val); val 55 sound/pci/trident/trident_main.c unsigned int val, tmp; val 59 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, CH_LBA)); val 60 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "LBA: 0x%x\n", val); val 61 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, CH_GVSEL_PAN_VOL_CTRL_EC)); val 62 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "GVSel: %i\n", val >> 31); val 63 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "Pan: 0x%x\n", (val >> 24) & 0x7f); val 64 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "Vol: 0x%x\n", (val >> 16) & 0xff); val 65 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "CTRL: 0x%x\n", (val >> 12) & 0x0f); val 66 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "EC: 0x%x\n", val & 0x0fff); val 68 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, CH_DX_CSO_ALPHA_FMS)); val 69 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "CSO: 0x%x\n", val >> 16); val 70 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "Alpha: 0x%x\n", (val >> 4) & 0x0fff); val 71 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "FMS: 0x%x\n", val & 0x0f); val 72 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, CH_DX_ESO_DELTA)); val 73 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "ESO: 0x%x\n", val >> 16); val 74 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "Delta: 0x%x\n", val & 0xffff); val 75 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, CH_DX_FMC_RVOL_CVOL)); val 77 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, CH_NX_DELTA_CSO)); val 78 sound/pci/trident/trident_main.c tmp = (val >> 24) & 0xff; val 79 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "CSO: 0x%x\n", val & 0x00ffffff); val 80 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, CH_NX_DELTA_ESO)); val 81 sound/pci/trident/trident_main.c tmp |= (val >> 16) & 0xff00; val 83 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "ESO: 0x%x\n", val & 0x00ffffff); val 84 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, CH_NX_ALPHA_FMS_FMC_RVOL_CVOL)); val 85 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "Alpha: 0x%x\n", val >> 20); val 86 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "FMS: 0x%x\n", (val >> 16) & 0x0f); val 88 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "FMC: 0x%x\n", (val >> 14) & 3); val 89 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "RVol: 0x%x\n", (val >> 7) & 0x7f); val 90 sound/pci/trident/trident_main.c dev_dbg(trident->card->dev, "CVol: 0x%x\n", val & 0x7f); val 238 sound/pci/trident/trident_main.c unsigned int val; val 240 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, T4D_LFO_GC_CIR)); val 241 sound/pci/trident/trident_main.c val |= ENDLP_IE; val 242 sound/pci/trident/trident_main.c val |= MIDLP_IE; val 244 sound/pci/trident/trident_main.c val |= BANK_B_EN; val 245 sound/pci/trident/trident_main.c outl(val, TRID_REG(trident, T4D_LFO_GC_CIR)); val 1041 sound/pci/trident/trident_main.c unsigned int val, ESO_bytes; val 1064 sound/pci/trident/trident_main.c val = (((unsigned int) 48000L << 12) + (runtime->rate/2)) / runtime->rate; val 1065 sound/pci/trident/trident_main.c outw(val, TRID_REG(trident, T4D_SBDELTA_DELTA_R)); val 1069 sound/pci/trident/trident_main.c val = (unsigned short) ((ESO_bytes >> 1) - 1); val 1071 sound/pci/trident/trident_main.c val = (unsigned short) (ESO_bytes - 1); val 1074 sound/pci/trident/trident_main.c outl((val << 16) | val, TRID_REG(trident, T4D_SBBL_SBCL)); val 1537 sound/pci/trident/trident_main.c unsigned int val, go; val 1555 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, T4D_STIMER)) & 0x00ffffff; val 1567 sound/pci/trident/trident_main.c evoice->stimer = val; val 1571 sound/pci/trident/trident_main.c voice->stimer = val; val 1585 sound/pci/trident/trident_main.c val = trident->spdif_pcm_ctrl; val 1587 sound/pci/trident/trident_main.c val &= ~(0x28); val 1588 sound/pci/trident/trident_main.c outb(val, TRID_REG(trident, NX_SPCTRL_SPCSO + 3)); val 1591 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, SI_SERIAL_INTF_CTRL)) | SPDIF_EN; val 1592 sound/pci/trident/trident_main.c outl(val, TRID_REG(trident, SI_SERIAL_INTF_CTRL)); val 1597 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, T4D_AINTEN_B)); val 1599 sound/pci/trident/trident_main.c val |= whati; val 1601 sound/pci/trident/trident_main.c val &= ~whati; val 1603 sound/pci/trident/trident_main.c outl(val, TRID_REG(trident, T4D_AINTEN_B)); val 2305 sound/pci/trident/trident_main.c unsigned char val; val 2308 sound/pci/trident/trident_main.c val = trident->spdif_ctrl; val 2309 sound/pci/trident/trident_main.c ucontrol->value.integer.value[0] = val == kcontrol->private_value; val 2318 sound/pci/trident/trident_main.c unsigned char val; val 2321 sound/pci/trident/trident_main.c val = ucontrol->value.integer.value[0] ? (unsigned char) kcontrol->private_value : 0x00; val 2324 sound/pci/trident/trident_main.c change = trident->spdif_ctrl != val; val 2325 sound/pci/trident/trident_main.c trident->spdif_ctrl = val; val 2336 sound/pci/trident/trident_main.c if (val) val 2387 sound/pci/trident/trident_main.c unsigned int val; val 2390 sound/pci/trident/trident_main.c val = (ucontrol->value.iec958.status[0] << 0) | val 2395 sound/pci/trident/trident_main.c change = trident->spdif_bits != val; val 2396 sound/pci/trident/trident_main.c trident->spdif_bits = val; val 2482 sound/pci/trident/trident_main.c unsigned int val; val 2485 sound/pci/trident/trident_main.c val = (ucontrol->value.iec958.status[0] << 0) | val 2490 sound/pci/trident/trident_main.c change = trident->spdif_pcm_bits != val; val 2491 sound/pci/trident/trident_main.c trident->spdif_pcm_bits = val; val 2525 sound/pci/trident/trident_main.c unsigned char val; val 2528 sound/pci/trident/trident_main.c val = trident->ac97_ctrl = inl(TRID_REG(trident, NX_ACR0_AC97_COM_STAT)); val 2529 sound/pci/trident/trident_main.c ucontrol->value.integer.value[0] = (val & (1 << kcontrol->private_value)) ? 1 : 0; val 2538 sound/pci/trident/trident_main.c unsigned char val; val 2542 sound/pci/trident/trident_main.c val = trident->ac97_ctrl = inl(TRID_REG(trident, NX_ACR0_AC97_COM_STAT)); val 2543 sound/pci/trident/trident_main.c val &= ~(1 << kcontrol->private_value); val 2545 sound/pci/trident/trident_main.c val |= 1 << kcontrol->private_value; val 2546 sound/pci/trident/trident_main.c change = val != trident->ac97_ctrl; val 2547 sound/pci/trident/trident_main.c trident->ac97_ctrl = val; val 2548 sound/pci/trident/trident_main.c outl(trident->ac97_ctrl = val, TRID_REG(trident, NX_ACR0_AC97_COM_STAT)); val 2583 sound/pci/trident/trident_main.c unsigned int val; val 2585 sound/pci/trident/trident_main.c val = trident->musicvol_wavevol; val 2586 sound/pci/trident/trident_main.c ucontrol->value.integer.value[0] = 255 - ((val >> kcontrol->private_value) & 0xff); val 2587 sound/pci/trident/trident_main.c ucontrol->value.integer.value[1] = 255 - ((val >> (kcontrol->private_value + 8)) & 0xff); val 2597 sound/pci/trident/trident_main.c unsigned int val; val 2601 sound/pci/trident/trident_main.c val = trident->musicvol_wavevol; val 2602 sound/pci/trident/trident_main.c val &= ~(0xffff << kcontrol->private_value); val 2603 sound/pci/trident/trident_main.c val |= ((255 - (ucontrol->value.integer.value[0] & 0xff)) | val 2605 sound/pci/trident/trident_main.c change = val != trident->musicvol_wavevol; val 2606 sound/pci/trident/trident_main.c outl(trident->musicvol_wavevol = val, TRID_REG(trident, T4D_MUSICVOL_WAVEVOL)); val 2672 sound/pci/trident/trident_main.c unsigned int val; val 2676 sound/pci/trident/trident_main.c val = 1023 - (ucontrol->value.integer.value[0] & 1023); val 2678 sound/pci/trident/trident_main.c val = (255 - (ucontrol->value.integer.value[0] & 255)) << 2; val 2681 sound/pci/trident/trident_main.c change = val != mix->vol; val 2682 sound/pci/trident/trident_main.c mix->vol = val; val 2684 sound/pci/trident/trident_main.c snd_trident_write_vol_reg(trident, mix->voice, val); val 2737 sound/pci/trident/trident_main.c unsigned char val; val 2741 sound/pci/trident/trident_main.c val = ucontrol->value.integer.value[0] & 0x3f; val 2743 sound/pci/trident/trident_main.c val = (0x3f - (ucontrol->value.integer.value[0] & 0x3f)) | 0x40; val 2745 sound/pci/trident/trident_main.c change = val != mix->pan; val 2746 sound/pci/trident/trident_main.c mix->pan = val; val 2748 sound/pci/trident/trident_main.c snd_trident_write_pan_reg(trident, mix->voice, val); val 2795 sound/pci/trident/trident_main.c unsigned short val; val 2798 sound/pci/trident/trident_main.c val = 0x7f - (ucontrol->value.integer.value[0] & 0x7f); val 2800 sound/pci/trident/trident_main.c change = val != mix->rvol; val 2801 sound/pci/trident/trident_main.c mix->rvol = val; val 2803 sound/pci/trident/trident_main.c snd_trident_write_rvol_reg(trident, mix->voice, val); val 2853 sound/pci/trident/trident_main.c unsigned short val; val 2856 sound/pci/trident/trident_main.c val = 0x7f - (ucontrol->value.integer.value[0] & 0x7f); val 2858 sound/pci/trident/trident_main.c change = val != mix->cvol; val 2859 sound/pci/trident/trident_main.c mix->cvol = val; val 2861 sound/pci/trident/trident_main.c snd_trident_write_cvol_reg(trident, mix->voice, val); val 3876 sound/pci/trident/trident_main.c unsigned int i, val, mask[2] = { 0, 0 }; val 3884 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, T4D_AINTEN_A)); val 3885 sound/pci/trident/trident_main.c outl(val & ~mask[0], TRID_REG(trident, T4D_AINTEN_A)); val 3889 sound/pci/trident/trident_main.c val = inl(TRID_REG(trident, T4D_AINTEN_B)); val 3890 sound/pci/trident/trident_main.c outl(val & ~mask[1], TRID_REG(trident, T4D_AINTEN_B)); val 164 sound/pci/via82xx.c #define DEFINE_VIA_REGSET(name,val) \ val 166 sound/pci/via82xx.c VIA_REG_##name##_STATUS = (val),\ val 167 sound/pci/via82xx.c VIA_REG_##name##_CONTROL = (val) + 0x01,\ val 168 sound/pci/via82xx.c VIA_REG_##name##_TYPE = (val) + 0x02,\ val 169 sound/pci/via82xx.c VIA_REG_##name##_TABLE_PTR = (val) + 0x04,\ val 170 sound/pci/via82xx.c VIA_REG_##name##_CURR_PTR = (val) + 0x04,\ val 171 sound/pci/via82xx.c VIA_REG_##name##_STOP_IDX = (val) + 0x08,\ val 172 sound/pci/via82xx.c VIA_REG_##name##_CURR_COUNT = (val) + 0x0c,\ val 505 sound/pci/via82xx.c static inline void snd_via82xx_codec_xwrite(struct via82xx *chip, unsigned int val) val 507 sound/pci/via82xx.c outl(val, VIAREG(chip, AC97)); val 513 sound/pci/via82xx.c unsigned int val; val 517 sound/pci/via82xx.c if (!((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)) val 518 sound/pci/via82xx.c return val & 0xffff; val 528 sound/pci/via82xx.c unsigned int val, val1; val 533 sound/pci/via82xx.c val = snd_via82xx_codec_xread(chip); val 534 sound/pci/via82xx.c val1 = val & (VIA_REG_AC97_BUSY | stat); val 536 sound/pci/via82xx.c return val & 0xffff; val 554 sound/pci/via82xx.c unsigned short val) val 562 sound/pci/via82xx.c xval |= val << VIA_REG_AC97_DATA_SHIFT; val 570 sound/pci/via82xx.c unsigned int xval, val = 0xffff; val 588 sound/pci/via82xx.c val = snd_via82xx_codec_xread(chip); val 592 sound/pci/via82xx.c return val & 0xffff; val 724 sound/pci/via82xx.c unsigned char val; val 727 sound/pci/via82xx.c val = VIA_REG_CTRL_INT; val 729 sound/pci/via82xx.c val = 0; val 733 sound/pci/via82xx.c val |= VIA_REG_CTRL_START; val 738 sound/pci/via82xx.c val = VIA_REG_CTRL_TERMINATE; val 742 sound/pci/via82xx.c val |= VIA_REG_CTRL_PAUSE; val 751 sound/pci/via82xx.c outb(val, VIADEV_REG(viadev, OFFSET_CONTROL)); val 1621 sound/pci/via82xx.c u8 val, oval; val 1625 sound/pci/via82xx.c val = oval & ~VIA_REG_CAPTURE_CHANNEL_MIC; val 1627 sound/pci/via82xx.c val |= VIA_REG_CAPTURE_CHANNEL_MIC; val 1628 sound/pci/via82xx.c if (val != oval) val 1629 sound/pci/via82xx.c outb(val, port); val 1631 sound/pci/via82xx.c return val != oval; val 1648 sound/pci/via82xx.c u8 val; val 1650 sound/pci/via82xx.c pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &val); val 1651 sound/pci/via82xx.c ucontrol->value.integer.value[0] = (val & VIA8233_SPDIF_DX3) ? 1 : 0; val 1659 sound/pci/via82xx.c u8 val, oval; val 1662 sound/pci/via82xx.c val = oval & ~VIA8233_SPDIF_DX3; val 1664 sound/pci/via82xx.c val |= VIA8233_SPDIF_DX3; val 1667 sound/pci/via82xx.c if (val != oval) { val 1668 sound/pci/via82xx.c pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, val); val 1718 sound/pci/via82xx.c unsigned char val; val 1722 sound/pci/via82xx.c val = ucontrol->value.integer.value[i]; val 1723 sound/pci/via82xx.c if (val > VIA_DXS_MAX_VOLUME) val 1724 sound/pci/via82xx.c val = VIA_DXS_MAX_VOLUME; val 1725 sound/pci/via82xx.c val = VIA_DXS_MAX_VOLUME - val; val 1726 sound/pci/via82xx.c change |= val != chip->playback_volume[idx][i]; val 1728 sound/pci/via82xx.c chip->playback_volume[idx][i] = val; val 1729 sound/pci/via82xx.c outb(val, port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i); val 1740 sound/pci/via82xx.c unsigned char val; val 1744 sound/pci/via82xx.c val = ucontrol->value.integer.value[i]; val 1745 sound/pci/via82xx.c if (val > VIA_DXS_MAX_VOLUME) val 1746 sound/pci/via82xx.c val = VIA_DXS_MAX_VOLUME; val 1747 sound/pci/via82xx.c val = VIA_DXS_MAX_VOLUME - val; val 1748 sound/pci/via82xx.c if (val != chip->playback_volume_c[i]) { val 1750 sound/pci/via82xx.c chip->playback_volume_c[i] = val; val 1753 sound/pci/via82xx.c chip->playback_volume[idx][i] = val; val 1754 sound/pci/via82xx.c outb(val, port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i); val 1985 sound/pci/via82xx.c unsigned char val; val 2032 sound/pci/via82xx.c pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &val); val 2033 sound/pci/via82xx.c val = (val & ~VIA8233_SPDIF_SLOT_MASK) | VIA8233_SPDIF_SLOT_1011; val 2034 sound/pci/via82xx.c val &= ~VIA8233_SPDIF_DX3; /* SPDIF off as default */ val 2035 sound/pci/via82xx.c pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, val); val 2143 sound/pci/via82xx.c unsigned int val; val 2194 sound/pci/via82xx.c if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY) val 2196 sound/pci/via82xx.c "AC'97 codec is not ready [0x%x]\n", val); val 2207 sound/pci/via82xx.c if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_SECONDARY_VALID) { val 100 sound/pci/via82xx_modem.c #define DEFINE_VIA_REGSET(name,val) \ val 102 sound/pci/via82xx_modem.c VIA_REG_##name##_STATUS = (val),\ val 103 sound/pci/via82xx_modem.c VIA_REG_##name##_CONTROL = (val) + 0x01,\ val 104 sound/pci/via82xx_modem.c VIA_REG_##name##_TYPE = (val) + 0x02,\ val 105 sound/pci/via82xx_modem.c VIA_REG_##name##_TABLE_PTR = (val) + 0x04,\ val 106 sound/pci/via82xx_modem.c VIA_REG_##name##_CURR_PTR = (val) + 0x04,\ val 107 sound/pci/via82xx_modem.c VIA_REG_##name##_STOP_IDX = (val) + 0x08,\ val 108 sound/pci/via82xx_modem.c VIA_REG_##name##_CURR_COUNT = (val) + 0x0c,\ val 359 sound/pci/via82xx_modem.c static inline void snd_via82xx_codec_xwrite(struct via82xx_modem *chip, unsigned int val) val 361 sound/pci/via82xx_modem.c outl(val, VIAREG(chip, AC97)); val 367 sound/pci/via82xx_modem.c unsigned int val; val 371 sound/pci/via82xx_modem.c if (!((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)) val 372 sound/pci/via82xx_modem.c return val & 0xffff; val 382 sound/pci/via82xx_modem.c unsigned int val, val1; val 387 sound/pci/via82xx_modem.c val = snd_via82xx_codec_xread(chip); val 388 sound/pci/via82xx_modem.c val1 = val & (VIA_REG_AC97_BUSY | stat); val 390 sound/pci/via82xx_modem.c return val & 0xffff; val 407 sound/pci/via82xx_modem.c unsigned short val) val 412 sound/pci/via82xx_modem.c outl(val, VIAREG(chip, GPI_STATUS)); val 418 sound/pci/via82xx_modem.c xval |= val << VIA_REG_AC97_DATA_SHIFT; val 426 sound/pci/via82xx_modem.c unsigned int xval, val = 0xffff; val 444 sound/pci/via82xx_modem.c val = snd_via82xx_codec_xread(chip); val 448 sound/pci/via82xx_modem.c return val & 0xffff; val 513 sound/pci/via82xx_modem.c unsigned char val = 0; val 518 sound/pci/via82xx_modem.c val |= VIA_REG_CTRL_START; val 522 sound/pci/via82xx_modem.c val = VIA_REG_CTRL_TERMINATE; val 526 sound/pci/via82xx_modem.c val |= VIA_REG_CTRL_PAUSE; val 535 sound/pci/via82xx_modem.c outb(val, VIADEV_REG(viadev, OFFSET_CONTROL)); val 934 sound/pci/via82xx_modem.c unsigned int val; val 982 sound/pci/via82xx_modem.c if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY) val 984 sound/pci/via82xx_modem.c "AC'97 codec is not ready [0x%x]\n", val); val 994 sound/pci/via82xx_modem.c if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_SECONDARY_VALID) { val 96 sound/pci/vx222/vx222_ops.c static void vx2_outb(struct vx_core *chip, int offset, unsigned char val) val 98 sound/pci/vx222/vx222_ops.c outb(val, vx2_reg_addr(chip, offset)); val 120 sound/pci/vx222/vx222_ops.c static void vx2_outl(struct vx_core *chip, int offset, unsigned int val) val 125 sound/pci/vx222/vx222_ops.c outl(val, vx2_reg_addr(chip, offset)); val 134 sound/pci/vx222/vx222_ops.c #define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val) val 138 sound/pci/vx222/vx222_ops.c #define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val) val 329 sound/pci/vx222/vx222_ops.c unsigned int val; val 332 sound/pci/vx222/vx222_ops.c val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK; val 333 sound/pci/vx222/vx222_ops.c vx2_outl(chip, port, val); val 338 sound/pci/vx222/vx222_ops.c val |= VX_USERBIT1_MASK; val 340 sound/pci/vx222/vx222_ops.c val &= ~VX_USERBIT1_MASK; val 341 sound/pci/vx222/vx222_ops.c vx2_outl(chip, port, val); val 345 sound/pci/vx222/vx222_ops.c val |= VX_USERBIT0_MASK; val 346 sound/pci/vx222/vx222_ops.c vx2_outl(chip, port, val); val 666 sound/pci/vx222/vx222_ops.c unsigned int val; val 682 sound/pci/vx222/vx222_ops.c val = AKM_CODEC_LEFT_LEVEL_CMD; val 685 sound/pci/vx222/vx222_ops.c val = AKM_CODEC_RIGHT_LEVEL_CMD; val 691 sound/pci/vx222/vx222_ops.c val |= vx2_akm_gains_lut[data]; val 693 sound/pci/vx222/vx222_ops.c vx2_write_codec_reg(chip, val); val 39 sound/pci/ymfpci/ymfpci_main.c static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val) val 41 sound/pci/ymfpci/ymfpci_main.c writeb(val, chip->reg_area_virt + offset); val 49 sound/pci/ymfpci/ymfpci_main.c static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val) val 51 sound/pci/ymfpci/ymfpci_main.c writew(val, chip->reg_area_virt + offset); val 59 sound/pci/ymfpci/ymfpci_main.c static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val) val 61 sound/pci/ymfpci/ymfpci_main.c writel(val, chip->reg_area_virt + offset); val 81 sound/pci/ymfpci/ymfpci_main.c static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val) val 87 sound/pci/ymfpci/ymfpci_main.c cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val; val 132 sound/pci/ymfpci/ymfpci_main.c static u32 val[8] = { val 141 sound/pci/ymfpci/ymfpci_main.c return val[i]; val 142 sound/pci/ymfpci/ymfpci_main.c return val[0]; val 148 sound/pci/ymfpci/ymfpci_main.c static u32 val[8] = { val 157 sound/pci/ymfpci/ymfpci_main.c return val[i]; val 158 sound/pci/ymfpci/ymfpci_main.c return val[0]; val 1291 sound/pci/ymfpci/ymfpci_main.c unsigned int val; val 1294 sound/pci/ymfpci/ymfpci_main.c val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) | val 1297 sound/pci/ymfpci/ymfpci_main.c change = chip->spdif_bits != val; val 1298 sound/pci/ymfpci/ymfpci_main.c chip->spdif_bits = val; val 1366 sound/pci/ymfpci/ymfpci_main.c unsigned int val; val 1369 sound/pci/ymfpci/ymfpci_main.c val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) | val 1372 sound/pci/ymfpci/ymfpci_main.c change = chip->spdif_pcm_bits != val; val 1373 sound/pci/ymfpci/ymfpci_main.c chip->spdif_pcm_bits = val; val 1475 sound/pci/ymfpci/ymfpci_main.c unsigned int val, oval; val 1482 sound/pci/ymfpci/ymfpci_main.c val = (ucontrol->value.integer.value[0] & mask); val 1483 sound/pci/ymfpci/ymfpci_main.c val <<= shift; val 1486 sound/pci/ymfpci/ymfpci_main.c val = (oval & ~(mask << shift)) | val; val 1487 sound/pci/ymfpci/ymfpci_main.c change = val != oval; val 1488 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writel(chip, reg, val); val 1521 sound/pci/ymfpci/ymfpci_main.c unsigned int val; val 1526 sound/pci/ymfpci/ymfpci_main.c val = snd_ymfpci_readl(chip, reg); val 1528 sound/pci/ymfpci/ymfpci_main.c ucontrol->value.integer.value[0] = (val >> shift_left) & mask; val 1529 sound/pci/ymfpci/ymfpci_main.c ucontrol->value.integer.value[1] = (val >> shift_right) & mask; val 2006 sound/pci/ymfpci/ymfpci_main.c u32 val; val 2009 sound/pci/ymfpci/ymfpci_main.c val = snd_ymfpci_readl(chip, YDSXGR_CONFIG); val 2010 sound/pci/ymfpci/ymfpci_main.c if (val) val 2013 sound/pci/ymfpci/ymfpci_main.c val = snd_ymfpci_readl(chip, YDSXGR_STATUS); val 2014 sound/pci/ymfpci/ymfpci_main.c if ((val & 0x00000002) == 0) val 106 sound/pcmcia/pdaudiocf/pdaudiocf.h static inline void pdacf_reg_write(struct snd_pdacf *chip, unsigned char reg, unsigned short val) val 108 sound/pcmcia/pdaudiocf/pdaudiocf.h outw(chip->regmap[reg>>1] = val, chip->port + reg); val 50 sound/pcmcia/pdaudiocf/pdaudiocf_core.c static void pdacf_ak4117_write(void *private_data, unsigned char reg, unsigned char val) val 66 sound/pcmcia/pdaudiocf/pdaudiocf_core.c outw((u16)reg << 8 | val | (1<<13), chip->port + PDAUDIOCF_REG_AK_IFR); val 93 sound/pcmcia/pdaudiocf/pdaudiocf_core.c u16 val; val 95 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val = pdacf_reg_read(chip, PDAUDIOCF_REG_SCR); val 96 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val |= PDAUDIOCF_PDN; val 97 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~PDAUDIOCF_RECORD; /* for sure */ val 98 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); val 100 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val |= PDAUDIOCF_RST; val 101 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); val 103 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~PDAUDIOCF_RST; val 104 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); val 107 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~PDAUDIOCF_PDN; val 108 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); val 160 sound/pcmcia/pdaudiocf/pdaudiocf_core.c u16 val; val 165 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val = chip->regmap[PDAUDIOCF_REG_SCR>>1]; val 167 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val |= PDAUDIOCF_BLUE_LED_OFF; val 169 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~PDAUDIOCF_BLUE_LED_OFF; val 170 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); val 177 sound/pcmcia/pdaudiocf/pdaudiocf_core.c u16 val; val 197 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val = pdacf_reg_read(chip, PDAUDIOCF_REG_TCR); val 199 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~(PDAUDIOCF_ELIMAKMBIT|PDAUDIOCF_TESTDATASEL); val 201 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val |= PDAUDIOCF_ELIMAKMBIT; val 202 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~PDAUDIOCF_TESTDATASEL; val 204 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_TCR, val); val 207 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val = pdacf_reg_read(chip, PDAUDIOCF_REG_SCR); val 208 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~(PDAUDIOCF_CLKDIV0 | PDAUDIOCF_CLKDIV1); /* use 24.576Mhz clock */ val 209 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~(PDAUDIOCF_RED_LED_OFF|PDAUDIOCF_BLUE_LED_OFF); val 210 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val |= PDAUDIOCF_DATAFMT0 | PDAUDIOCF_DATAFMT1; /* 24-bit data */ val 211 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); val 214 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val = pdacf_reg_read(chip, PDAUDIOCF_REG_IER); val 215 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~(PDAUDIOCF_IRQLVLEN0 | PDAUDIOCF_IRQLVLEN1); val 216 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~(PDAUDIOCF_BLUEDUTY0 | PDAUDIOCF_REDDUTY0 | PDAUDIOCF_REDDUTY1); val 217 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val |= PDAUDIOCF_BLUEDUTY1 | PDAUDIOCF_HALFRATE; val 218 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val |= PDAUDIOCF_IRQOVREN | PDAUDIOCF_IRQAKMEN; val 219 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_IER, val); val 232 sound/pcmcia/pdaudiocf/pdaudiocf_core.c u16 val; val 234 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val = pdacf_reg_read(chip, PDAUDIOCF_REG_SCR); val 235 sound/pcmcia/pdaudiocf/pdaudiocf_core.c chip->suspend_reg_scr = val; val 236 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val |= PDAUDIOCF_RED_LED_OFF | PDAUDIOCF_BLUE_LED_OFF; val 237 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); val 239 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val = inw(chip->port + PDAUDIOCF_REG_IER); val 240 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~(PDAUDIOCF_IRQOVREN|PDAUDIOCF_IRQAKMEN|PDAUDIOCF_IRQLVLEN0|PDAUDIOCF_IRQLVLEN1); val 241 sound/pcmcia/pdaudiocf/pdaudiocf_core.c outw(val, chip->port + PDAUDIOCF_REG_IER); val 249 sound/pcmcia/pdaudiocf/pdaudiocf_core.c u16 val; val 253 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val = inw(chip->port + PDAUDIOCF_REG_IER); val 254 sound/pcmcia/pdaudiocf/pdaudiocf_core.c val &= ~(PDAUDIOCF_IRQOVREN|PDAUDIOCF_IRQAKMEN|PDAUDIOCF_IRQLVLEN0|PDAUDIOCF_IRQLVLEN1); val 255 sound/pcmcia/pdaudiocf/pdaudiocf_core.c outw(val, chip->port + PDAUDIOCF_REG_IER); val 39 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c unsigned short mask, val, tmp; val 52 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c val = PDAUDIOCF_RECORD; val 60 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c val = 0; val 78 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c tmp |= val; val 111 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c u16 val, nval, aval; val 131 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c val = nval = pdacf_reg_read(chip, PDAUDIOCF_REG_SCR); val 161 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c if (val != nval) { val 166 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c val = pdacf_reg_read(chip, PDAUDIOCF_REG_IER); val 167 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c val &= ~(PDAUDIOCF_IRQLVLEN1); val 168 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c val |= PDAUDIOCF_IRQLVLEN0; val 169 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c pdacf_reg_write(chip, PDAUDIOCF_REG_IER, val); val 42 sound/pcmcia/vx/vxp_mixer.c unsigned int val = ucontrol->value.integer.value[0]; val 44 sound/pcmcia/vx/vxp_mixer.c if (val > MIC_LEVEL_MAX) val 87 sound/pcmcia/vx/vxp_mixer.c int val = !!ucontrol->value.integer.value[0]; val 89 sound/pcmcia/vx/vxp_mixer.c if (chip->mic_level != val) { val 90 sound/pcmcia/vx/vxp_mixer.c vx_set_mic_boost(_chip, val); val 91 sound/pcmcia/vx/vxp_mixer.c chip->mic_level = val; val 58 sound/pcmcia/vx/vxp_ops.c static void vxp_outb(struct vx_core *chip, int offset, unsigned char val) val 60 sound/pcmcia/vx/vxp_ops.c outb(val, vxp_reg_addr(chip, offset)); val 69 sound/pcmcia/vx/vxp_ops.c #define vx_outb(chip,reg,val) vxp_outb((struct vx_core *)(chip), VX_##reg,val) val 51 sound/ppc/awacs.c snd_pmac_awacs_write(struct snd_pmac *chip, int val) val 57 sound/ppc/awacs.c out_le32(&chip->awacs->codec_ctrl, val | (chip->subframe << 22)); val 67 sound/ppc/awacs.c snd_pmac_awacs_write_reg(struct snd_pmac *chip, int reg, int val) val 69 sound/ppc/awacs.c snd_pmac_awacs_write(chip, val | (reg << 12)); val 70 sound/ppc/awacs.c chip->awacs_reg[reg] = val; val 74 sound/ppc/awacs.c snd_pmac_awacs_write_noreg(struct snd_pmac *chip, int reg, int val) val 76 sound/ppc/awacs.c snd_pmac_awacs_write(chip, val | (reg << 12)); val 162 sound/ppc/awacs.c int val, oldval; val 178 sound/ppc/awacs.c val = oldval & ~(0xf | (0xf << lshift)); val 179 sound/ppc/awacs.c val |= vol[0] << lshift; val 180 sound/ppc/awacs.c val |= vol[1]; val 181 sound/ppc/awacs.c if (oldval != val) val 182 sound/ppc/awacs.c snd_pmac_awacs_write_reg(chip, reg, val); val 205 sound/ppc/awacs.c int val; val 209 sound/ppc/awacs.c val = (chip->awacs_reg[reg] >> shift) & 1; val 212 sound/ppc/awacs.c val = 1 - val; val 213 sound/ppc/awacs.c ucontrol->value.integer.value[0] = val; val 225 sound/ppc/awacs.c int val, changed; val 229 sound/ppc/awacs.c val = chip->awacs_reg[reg] & ~mask; val 231 sound/ppc/awacs.c val |= mask; val 232 sound/ppc/awacs.c changed = chip->awacs_reg[reg] != val; val 234 sound/ppc/awacs.c snd_pmac_awacs_write_reg(chip, reg, val); val 254 sound/ppc/awacs.c static void awacs_set_cuda(int reg, int val) val 258 sound/ppc/awacs.c reg, val); val 413 sound/ppc/awacs.c unsigned int val; val 415 sound/ppc/awacs.c val = ucontrol->value.integer.value[0]; val 416 sound/ppc/awacs.c if (val > 14) val 418 sound/ppc/awacs.c if (val != amp->amp_tone[index]) { val 419 sound/ppc/awacs.c amp->amp_tone[index] = val; val 451 sound/ppc/awacs.c unsigned int val; val 453 sound/ppc/awacs.c val = ucontrol->value.integer.value[0]; val 454 sound/ppc/awacs.c if (val > 99) val 456 sound/ppc/awacs.c if (val != amp->amp_master) { val 457 sound/ppc/awacs.c amp->amp_master = val; val 542 sound/ppc/awacs.c int val = 0; val 547 sound/ppc/awacs.c val |= 2; val 549 sound/ppc/awacs.c val |= 1; val 551 sound/ppc/awacs.c ucontrol->value.integer.value[0] = val; val 45 sound/ppc/burgundy.c snd_pmac_burgundy_wcw(struct snd_pmac *chip, unsigned addr, unsigned val) val 47 sound/ppc/burgundy.c out_le32(&chip->awacs->codec_ctrl, addr + 0x200c00 + (val & 0xff)); val 49 sound/ppc/burgundy.c out_le32(&chip->awacs->codec_ctrl, addr + 0x200d00 +((val>>8) & 0xff)); val 51 sound/ppc/burgundy.c out_le32(&chip->awacs->codec_ctrl, addr + 0x200e00 +((val>>16) & 0xff)); val 53 sound/ppc/burgundy.c out_le32(&chip->awacs->codec_ctrl, addr + 0x200f00 +((val>>24) & 0xff)); val 60 sound/ppc/burgundy.c unsigned val = 0; val 68 sound/ppc/burgundy.c val += (in_le32(&chip->awacs->codec_stat) >> 4) & 0xff; val 73 sound/ppc/burgundy.c val += ((in_le32(&chip->awacs->codec_stat)>>4) & 0xff) <<8; val 78 sound/ppc/burgundy.c val += ((in_le32(&chip->awacs->codec_stat)>>4) & 0xff) <<16; val 83 sound/ppc/burgundy.c val += ((in_le32(&chip->awacs->codec_stat)>>4) & 0xff) <<24; val 87 sound/ppc/burgundy.c return val; val 92 sound/ppc/burgundy.c unsigned int val) val 94 sound/ppc/burgundy.c out_le32(&chip->awacs->codec_ctrl, addr + 0x300000 + (val & 0xff)); val 101 sound/ppc/burgundy.c unsigned val = 0; val 109 sound/ppc/burgundy.c val += (in_le32(&chip->awacs->codec_stat) >> 4) & 0xff; val 113 sound/ppc/burgundy.c return val; val 319 sound/ppc/burgundy.c int oval, val; val 324 sound/ppc/burgundy.c val = ucontrol->value.integer.value[0]; val 326 sound/ppc/burgundy.c val |= ucontrol->value.integer.value[1] << 4; val 328 sound/ppc/burgundy.c val |= ucontrol->value.integer.value[0] << 4; val 330 sound/ppc/burgundy.c val = ~val & 0xff; val 331 sound/ppc/burgundy.c snd_pmac_burgundy_wcb(chip, addr, val); val 332 sound/ppc/burgundy.c return val != oval; val 364 sound/ppc/burgundy.c int val = snd_pmac_burgundy_rcw(chip, addr); val 365 sound/ppc/burgundy.c ucontrol->value.integer.value[0] = (val & lmask) ? 1 : 0; val 367 sound/ppc/burgundy.c ucontrol->value.integer.value[1] = (val & rmask) ? 1 : 0; val 379 sound/ppc/burgundy.c int val, oval; val 381 sound/ppc/burgundy.c val = oval & ~(lmask | (stereo ? rmask : 0)); val 383 sound/ppc/burgundy.c val |= lmask; val 385 sound/ppc/burgundy.c val |= rmask; val 386 sound/ppc/burgundy.c snd_pmac_burgundy_wcw(chip, addr, val); val 387 sound/ppc/burgundy.c return val != oval; val 420 sound/ppc/burgundy.c int val = snd_pmac_burgundy_rcb(chip, addr); val 421 sound/ppc/burgundy.c ucontrol->value.integer.value[0] = (val & lmask) ? 1 : 0; val 423 sound/ppc/burgundy.c ucontrol->value.integer.value[1] = (val & rmask) ? 1 : 0; val 435 sound/ppc/burgundy.c int val, oval; val 437 sound/ppc/burgundy.c val = oval & ~(lmask | rmask); val 439 sound/ppc/burgundy.c val |= lmask; val 441 sound/ppc/burgundy.c val |= rmask; val 442 sound/ppc/burgundy.c snd_pmac_burgundy_wcb(chip, addr, val); val 443 sound/ppc/burgundy.c return val != oval; val 61 sound/ppc/snd_ps3.c static inline void write_reg(unsigned int reg, u32 val) val 63 sound/ppc/snd_ps3.c out_be32(the_card.mapped_mmio_vaddr + reg, val); val 852 sound/ppc/snd_ps3.c uint64_t val; val 855 sound/ppc/snd_ps3.c val = (ioaddr_start & (0x0fUL << 32)) >> (32 - 20) | val 860 sound/ppc/snd_ps3.c ret = lv1_gpu_attribute(0x100, 0x007, val); val 158 sound/ppc/tumbler.c #define do_gpio_write(gp, val) \ val 159 sound/ppc/tumbler.c pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, (gp)->addr, val) val 324 sound/ppc/tumbler.c unsigned char val[2]; val 330 sound/ppc/tumbler.c val[0] = 0xc1; /* enable, 3:1 compression */ val 332 sound/ppc/tumbler.c val[1] = 0xf0; val 334 sound/ppc/tumbler.c val[1] = 0x91; val 336 sound/ppc/tumbler.c val[1] = mix->drc_range + 0x91; val 338 sound/ppc/tumbler.c val[0] = 0; val 339 sound/ppc/tumbler.c val[1] = 0; val 343 sound/ppc/tumbler.c 2, val) < 0) { val 347 sound/ppc/tumbler.c DBG("(I) succeeded to set DRC (%u, %u)\n", val[0], val[1]); val 359 sound/ppc/tumbler.c unsigned char val[6]; val 365 sound/ppc/tumbler.c val[0] = 0x50; /* 3:1 above threshold */ val 367 sound/ppc/tumbler.c val[0] = 0x51; /* disabled */ val 368 sound/ppc/tumbler.c val[1] = 0x02; /* 1:1 below threshold */ val 370 sound/ppc/tumbler.c val[2] = 0xef; val 372 sound/ppc/tumbler.c val[2] = 0x00; val 374 sound/ppc/tumbler.c val[2] = mix->drc_range; val 375 sound/ppc/tumbler.c val[3] = 0xb0; val 376 sound/ppc/tumbler.c val[4] = 0x60; val 377 sound/ppc/tumbler.c val[5] = 0xa0; val 380 sound/ppc/tumbler.c 6, val) < 0) { val 384 sound/ppc/tumbler.c DBG("(I) succeeded to set DRC (%u, %u)\n", val[0], val[1]); val 416 sound/ppc/tumbler.c unsigned int val; val 421 sound/ppc/tumbler.c val = ucontrol->value.integer.value[0]; val 423 sound/ppc/tumbler.c if (val > TAS3001_DRC_MAX) val 426 sound/ppc/tumbler.c if (val > TAS3004_DRC_MAX) val 429 sound/ppc/tumbler.c change = mix->drc_range != val; val 431 sound/ppc/tumbler.c mix->drc_range = val; val 743 sound/ppc/tumbler.c int val; val 762 sound/ppc/tumbler.c val = ! check_audio_gpio(gp); val 763 sound/ppc/tumbler.c if (val != ucontrol->value.integer.value[0]) { val 943 sound/ppc/tumbler.c static void check_mute(struct snd_pmac *chip, struct pmac_gpio *gp, int val, int do_notify, val 946 sound/ppc/tumbler.c if (check_audio_gpio(gp) != val) { val 947 sound/ppc/tumbler.c write_audio_gpio(gp, val); val 1248 sound/ppc/tumbler.c unsigned char val; val 1252 sound/ppc/tumbler.c val = do_gpio_read(&mix->hp_detect); val 1253 sound/ppc/tumbler.c do_gpio_write(&mix->hp_detect, val | 0x80); val 1458 sound/ppc/tumbler.c unsigned char val; val 1463 sound/ppc/tumbler.c val = do_gpio_read(&mix->hp_detect); val 1464 sound/ppc/tumbler.c do_gpio_write(&mix->hp_detect, val | 0x80); val 1467 sound/ppc/tumbler.c unsigned char val; val 1472 sound/ppc/tumbler.c val = do_gpio_read(&mix->line_detect); val 1473 sound/ppc/tumbler.c do_gpio_write(&mix->line_detect, val | 0x80); val 110 sound/sh/aica.c u32 val; val 116 sound/sh/aica.c val = *froml; val 118 sound/sh/aica.c writel(val, to); val 61 sound/soc/adi/axi-i2s.c unsigned int mask, val; val 72 sound/soc/adi/axi-i2s.c val = mask; val 77 sound/soc/adi/axi-i2s.c val = 0; val 83 sound/soc/adi/axi-i2s.c regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); val 52 sound/soc/adi/axi-spdif.c unsigned int val; val 58 sound/soc/adi/axi-spdif.c val = AXI_SPDIF_CTRL_TXDATA; val 63 sound/soc/adi/axi-spdif.c val = 0; val 70 sound/soc/adi/axi-spdif.c AXI_SPDIF_CTRL_TXDATA, val); val 123 sound/soc/amd/acp-pcm-dma.c static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) val 125 sound/soc/amd/acp-pcm-dma.c writel(val, acp_mmio + (reg * 4)); val 361 sound/soc/amd/acp-pcm-dma.c u32 val, ch_reg, imr_reg, res_reg; val 376 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, val 378 sound/soc/amd/acp-pcm-dma.c if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { val 383 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, imr_reg); val 384 sound/soc/amd/acp-pcm-dma.c val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; val 385 sound/soc/amd/acp-pcm-dma.c val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; val 386 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, imr_reg); val 393 sound/soc/amd/acp-pcm-dma.c u32 val, ch_reg, imr_reg; val 406 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, imr_reg); val 407 sound/soc/amd/acp-pcm-dma.c val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; val 408 sound/soc/amd/acp-pcm-dma.c val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; val 409 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, imr_reg); val 506 sound/soc/amd/acp-pcm-dma.c u32 val, req_reg, sts_reg, sts_reg_mask; val 521 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, req_reg); val 522 sound/soc/amd/acp-pcm-dma.c if (val & (1 << bank)) { val 526 sound/soc/amd/acp-pcm-dma.c val &= ~(1 << bank); val 534 sound/soc/amd/acp-pcm-dma.c val |= 1 << bank; val 539 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, req_reg); val 554 sound/soc/amd/acp-pcm-dma.c u32 val, count, sram_pte_offset; val 557 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); val 559 sound/soc/amd/acp-pcm-dma.c val |= ACP_SOFT_RESET__SoftResetAud_MASK; val 560 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); val 564 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); val 566 sound/soc/amd/acp-pcm-dma.c (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) val 576 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_CONTROL); val 577 sound/soc/amd/acp-pcm-dma.c val = val | ACP_CONTROL__ClkEn_MASK; val 578 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, mmACP_CONTROL); val 583 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_STATUS); val 584 sound/soc/amd/acp-pcm-dma.c if (val & (u32)0x1) val 594 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); val 595 sound/soc/amd/acp-pcm-dma.c val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; val 596 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); val 600 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); val 601 sound/soc/amd/acp-pcm-dma.c val |= ACP_BT_UART_PAD_SELECT_MASK; val 602 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); val 647 sound/soc/amd/acp-pcm-dma.c u32 val; val 651 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); val 653 sound/soc/amd/acp-pcm-dma.c val |= ACP_SOFT_RESET__SoftResetAud_MASK; val 654 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); val 658 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); val 660 sound/soc/amd/acp-pcm-dma.c (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) val 669 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_CONTROL); val 670 sound/soc/amd/acp-pcm-dma.c val &= ~ACP_CONTROL__ClkEn_MASK; val 671 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, acp_mmio, mmACP_CONTROL); val 676 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(acp_mmio, mmACP_STATUS); val 677 sound/soc/amd/acp-pcm-dma.c if (!(val & (u32)0x1)) val 842 sound/soc/amd/acp-pcm-dma.c u32 val = 0; val 867 sound/soc/amd/acp-pcm-dma.c val = acp_reg_read(adata->acp_mmio, val 872 sound/soc/amd/acp-pcm-dma.c val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; val 876 sound/soc/amd/acp-pcm-dma.c val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; val 881 sound/soc/amd/acp-pcm-dma.c val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; val 885 sound/soc/amd/acp-pcm-dma.c val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; val 888 sound/soc/amd/acp-pcm-dma.c acp_reg_write(val, adata->acp_mmio, val 81 sound/soc/amd/raven/acp3x-pcm-dma.c u16 val, mask; val 85 sound/soc/amd/raven/acp3x-pcm-dma.c val = 1; val 88 sound/soc/amd/raven/acp3x-pcm-dma.c val = 0; val 92 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, acp3x_base + mmACP_PGFSM_CONTROL); val 95 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(acp3x_base + mmACP_PGFSM_STATUS); val 96 sound/soc/amd/raven/acp3x-pcm-dma.c if ((val & ACP3x_POWER_OFF_IN_PROGRESS) == mask) val 110 sound/soc/amd/raven/acp3x-pcm-dma.c u32 val, timeout; val 115 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(acp3x_base + mmACP_SOFT_RESET); val 116 sound/soc/amd/raven/acp3x-pcm-dma.c if ((val & ACP3x_SOFT_RESET__SoftResetAudDone_MASK) || val 118 sound/soc/amd/raven/acp3x-pcm-dma.c if (val & ACP3x_SOFT_RESET__SoftResetAudDone_MASK) val 129 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(acp3x_base + mmACP_SOFT_RESET); val 130 sound/soc/amd/raven/acp3x-pcm-dma.c if (!val || timeout > 100) { val 131 sound/soc/amd/raven/acp3x-pcm-dma.c if (!val) val 182 sound/soc/amd/raven/acp3x-pcm-dma.c u32 val; val 190 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT); val 191 sound/soc/amd/raven/acp3x-pcm-dma.c if ((val & BIT(BT_TX_THRESHOLD)) && rv_i2s_data->play_stream) { val 198 sound/soc/amd/raven/acp3x-pcm-dma.c if ((val & BIT(BT_RX_THRESHOLD)) && rv_i2s_data->capture_stream) { val 214 sound/soc/amd/raven/acp3x-pcm-dma.c u32 low, high, val, acp_fifo_addr; val 219 sound/soc/amd/raven/acp3x-pcm-dma.c val = 0; val 221 sound/soc/amd/raven/acp3x-pcm-dma.c val = rtd->num_pages * 8; val 234 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val); val 236 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val val 239 sound/soc/amd/raven/acp3x-pcm-dma.c val += 8; val 458 sound/soc/amd/raven/acp3x-pcm-dma.c u32 val = 0; val 480 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER); val 481 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel((val | 0x2), adata->acp3x_base + mmACP_BTTDM_ITER); val 482 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER); val 483 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel((val | 0x2), adata->acp3x_base + mmACP_BTTDM_IRER); val 485 sound/soc/amd/raven/acp3x-pcm-dma.c val = (FRM_LEN | (slots << 15) | (slot_len << 18)); val 486 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, adata->acp3x_base + mmACP_BTTDM_TXFRMT); val 487 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, adata->acp3x_base + mmACP_BTTDM_RXFRMT); val 489 sound/soc/amd/raven/acp3x-pcm-dma.c adata->tdm_fmt = val; val 497 sound/soc/amd/raven/acp3x-pcm-dma.c u32 val = 0; val 517 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER); val 518 sound/soc/amd/raven/acp3x-pcm-dma.c val = val | (rtd->xfer_resolution << 3); val 520 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER); val 522 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER); val 532 sound/soc/amd/raven/acp3x-pcm-dma.c u32 val, period_bytes; val 544 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER); val 545 sound/soc/amd/raven/acp3x-pcm-dma.c val = val | BIT(0); val 546 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER); val 550 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER); val 551 sound/soc/amd/raven/acp3x-pcm-dma.c val = val | BIT(0); val 552 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER); val 560 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER); val 561 sound/soc/amd/raven/acp3x-pcm-dma.c val = val & ~BIT(0); val 562 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER); val 564 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER); val 565 sound/soc/amd/raven/acp3x-pcm-dma.c val = val & ~BIT(0); val 566 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER); val 705 sound/soc/amd/raven/acp3x-pcm-dma.c u32 val; val 721 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER); val 722 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel((val | 0x2), adata->acp3x_base + val 736 sound/soc/amd/raven/acp3x-pcm-dma.c val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER); val 737 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel((val | 0x2), adata->acp3x_base + val 55 sound/soc/amd/raven/acp3x.h static inline void rv_writel(u32 val, void __iomem *base_addr) val 57 sound/soc/amd/raven/acp3x.h writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS); val 26 sound/soc/amd/raven/pci-acp3x.c u32 addr, val; val 67 sound/soc/amd/raven/pci-acp3x.c val = rv_readl(adata->acp3x_base + mmACP_I2S_PIN_CONFIG); val 68 sound/soc/amd/raven/pci-acp3x.c switch (val) { val 108 sound/soc/amd/raven/pci-acp3x.c dev_err(&pci->dev, "Invalid ACP audio mode : %d\n", val); val 253 sound/soc/atmel/atmel-classd.c u32 mask, val; val 256 sound/soc/atmel/atmel-classd.c val = pdata->pwm_type << CLASSD_MR_PWMTYP_SHIFT; val 260 sound/soc/atmel/atmel-classd.c val |= (CLASSD_MR_NON_OVERLAP_EN val 266 sound/soc/atmel/atmel-classd.c val |= (CLASSD_MR_NOVR_VAL_5NS val 270 sound/soc/atmel/atmel-classd.c val |= (CLASSD_MR_NOVR_VAL_10NS val 274 sound/soc/atmel/atmel-classd.c val |= (CLASSD_MR_NOVR_VAL_15NS val 278 sound/soc/atmel/atmel-classd.c val |= (CLASSD_MR_NOVR_VAL_20NS val 282 sound/soc/atmel/atmel-classd.c val |= (CLASSD_MR_NOVR_VAL_10NS val 291 sound/soc/atmel/atmel-classd.c snd_soc_component_update_bits(component, CLASSD_MR, mask, val); val 334 sound/soc/atmel/atmel-classd.c u32 mask, val; val 339 sound/soc/atmel/atmel-classd.c val = mask; val 341 sound/soc/atmel/atmel-classd.c val = 0; val 343 sound/soc/atmel/atmel-classd.c snd_soc_component_update_bits(component, CLASSD_MR, mask, val); val 385 sound/soc/atmel/atmel-classd.c u32 mask, val; val 411 sound/soc/atmel/atmel-classd.c val = (sample_rates[best].dsp_clk << CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT) val 414 sound/soc/atmel/atmel-classd.c snd_soc_component_update_bits(component, CLASSD_INTPMR, mask, val); val 446 sound/soc/atmel/atmel-classd.c u32 mask, val; val 454 sound/soc/atmel/atmel-classd.c val = mask; val 459 sound/soc/atmel/atmel-classd.c val = (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT) val 466 sound/soc/atmel/atmel-classd.c snd_soc_component_update_bits(component, CLASSD_MR, mask, val); val 307 sound/soc/atmel/atmel-i2s.c int val = abs(fs - gck_param->fs); val 309 sound/soc/atmel/atmel-i2s.c if (val < best) { val 310 sound/soc/atmel/atmel-i2s.c best = val; val 150 sound/soc/atmel/atmel-pdmic.c u32 val; val 153 sound/soc/atmel/atmel-pdmic.c return regmap_read(dd->regmap, PDMIC_CDR, &val); val 315 sound/soc/atmel/atmel-pdmic.c unsigned int val; val 318 sound/soc/atmel/atmel-pdmic.c val = ucontrol->value.integer.value[0]; val 320 sound/soc/atmel/atmel-pdmic.c if (val > max) val 324 sound/soc/atmel/atmel-pdmic.c mic_gain_table[val].dgain << PDMIC_DSPR1_DGAIN_SHIFT); val 329 sound/soc/atmel/atmel-pdmic.c mic_gain_table[val].scale << PDMIC_DSPR0_SCALE_SHIFT); val 463 sound/soc/atmel/atmel-pdmic.c u32 val; val 469 sound/soc/atmel/atmel-pdmic.c val = PDMIC_CR_ENPDM_EN << PDMIC_CR_ENPDM_SHIFT; val 474 sound/soc/atmel/atmel-pdmic.c val = PDMIC_CR_ENPDM_DIS << PDMIC_CR_ENPDM_SHIFT; val 480 sound/soc/atmel/atmel-pdmic.c snd_soc_component_update_bits(component, PDMIC_CR, PDMIC_CR_ENPDM_MASK, val); val 79 sound/soc/atmel/tse850-pcm5142.c unsigned int val = ucontrol->value.enumerated.item[0]; val 81 sound/soc/atmel/tse850-pcm5142.c if (val >= e->items) val 84 sound/soc/atmel/tse850-pcm5142.c gpiod_set_value_cansleep(tse850->loop1, val); val 85 sound/soc/atmel/tse850-pcm5142.c tse850->loop1_cache = val; val 109 sound/soc/atmel/tse850-pcm5142.c unsigned int val = ucontrol->value.enumerated.item[0]; val 111 sound/soc/atmel/tse850-pcm5142.c if (val >= e->items) val 114 sound/soc/atmel/tse850-pcm5142.c gpiod_set_value_cansleep(tse850->loop2, val); val 115 sound/soc/atmel/tse850-pcm5142.c tse850->loop2_cache = val; val 113 sound/soc/au1x/psc-ac97.c unsigned short val) val 125 sound/soc/au1x/psc-ac97.c __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), val 773 sound/soc/bcm/cygnus-ssp.c u32 val; val 775 sound/soc/bcm/cygnus-ssp.c val = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg); val 776 sound/soc/bcm/cygnus-ssp.c val &= CYGNUS_PLLCLKSEL_MASK; val 777 sound/soc/bcm/cygnus-ssp.c if (val >= ARRAY_SIZE(aio->cygaud->audio_clk)) { val 779 sound/soc/bcm/cygnus-ssp.c val); val 786 sound/soc/bcm/cygnus-ssp.c audio_clk[val]); val 792 sound/soc/bcm/cygnus-ssp.c audio_clk[val]); val 841 sound/soc/bcm/cygnus-ssp.c u32 val; val 908 sound/soc/bcm/cygnus-ssp.c val = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE); val 921 sound/soc/bcm/cygnus-ssp.c val |= mask; val 924 sound/soc/bcm/cygnus-ssp.c val &= ~mask; val 926 sound/soc/bcm/cygnus-ssp.c dev_dbg(aio->cygaud->dev, "%s Set OE bits 0x%x\n", __func__, val); val 927 sound/soc/bcm/cygnus-ssp.c writel(val, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE); val 1060 sound/soc/bcm/cygnus-ssp.c u32 val; val 1062 sound/soc/bcm/cygnus-ssp.c val = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg); val 1063 sound/soc/bcm/cygnus-ssp.c val &= CYGNUS_PLLCLKSEL_MASK; val 1064 sound/soc/bcm/cygnus-ssp.c if (val >= ARRAY_SIZE(aio->cygaud->audio_clk)) { val 1066 sound/soc/bcm/cygnus-ssp.c val); val 1071 sound/soc/bcm/cygnus-ssp.c clk_disable_unprepare(aio->cygaud->audio_clk[val]); val 1073 sound/soc/bcm/cygnus-ssp.c clk_disable_unprepare(aio->cygaud->audio_clk[val]); val 1075 sound/soc/bcm/cygnus-ssp.c aio->pll_clk_num = val; val 125 sound/soc/cirrus/ep93xx-ac97.c unsigned reg, unsigned val) val 127 sound/soc/cirrus/ep93xx-ac97.c __raw_writel(val, info->regs + reg); val 134 sound/soc/cirrus/ep93xx-ac97.c unsigned short val; val 145 sound/soc/cirrus/ep93xx-ac97.c val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA); val 148 sound/soc/cirrus/ep93xx-ac97.c return val; val 153 sound/soc/cirrus/ep93xx-ac97.c unsigned short val) val 163 sound/soc/cirrus/ep93xx-ac97.c ep93xx_ac97_write_reg(info, AC97S2DATA, val); val 96 sound/soc/cirrus/ep93xx-i2s.c unsigned reg, unsigned val) val 98 sound/soc/cirrus/ep93xx-i2s.c __raw_writel(val, info->regs + reg); val 275 sound/soc/codecs/88pm860x-codec.c int val[2], val2[2], i; val 277 sound/soc/codecs/88pm860x-codec.c val[0] = snd_soc_component_read32(component, reg) & 0x3f; val 278 sound/soc/codecs/88pm860x-codec.c val[1] = (snd_soc_component_read32(component, PM860X_SIDETONE_SHIFT) >> 4) & 0xf; val 283 sound/soc/codecs/88pm860x-codec.c if ((st_table[i].m == val[0]) && (st_table[i].n == val[1])) val 300 sound/soc/codecs/88pm860x-codec.c unsigned int val, val2; val 302 sound/soc/codecs/88pm860x-codec.c val = ucontrol->value.integer.value[0]; val 305 sound/soc/codecs/88pm860x-codec.c if (val >= ARRAY_SIZE(st_table) || val2 >= ARRAY_SIZE(st_table)) val 308 sound/soc/codecs/88pm860x-codec.c err = snd_soc_component_update_bits(component, reg, 0x3f, st_table[val].m); val 312 sound/soc/codecs/88pm860x-codec.c st_table[val].n << 4); val 333 sound/soc/codecs/88pm860x-codec.c int max = mc->max, val, val2; val 336 sound/soc/codecs/88pm860x-codec.c val = snd_soc_component_read32(component, reg) >> shift; val 338 sound/soc/codecs/88pm860x-codec.c ucontrol->value.integer.value[0] = (max - val) & mask; val 356 sound/soc/codecs/88pm860x-codec.c unsigned int val, val2, val_mask; val 359 sound/soc/codecs/88pm860x-codec.c val = ((max - ucontrol->value.integer.value[0]) & mask); val 362 sound/soc/codecs/88pm860x-codec.c val = val << shift; val 365 sound/soc/codecs/88pm860x-codec.c err = snd_soc_component_update_bits(component, reg, val_mask, val); val 1038 sound/soc/codecs/ab8500-codec.c unsigned int bnk, unsigned int par, unsigned int val) val 1045 sound/soc/codecs/ab8500-codec.c snd_soc_component_write(component, AB8500_ANCCONF5, val >> 8 & 0xff); val 1046 sound/soc/codecs/ab8500-codec.c snd_soc_component_write(component, AB8500_ANCCONF6, val & 0xff); val 1055 sound/soc/codecs/ab8500-codec.c unsigned int par, unsigned int val) val 1073 sound/soc/codecs/ab8500-codec.c snd_soc_component_write(component, AB8500_ANCCONF8, val >> 16 & 0xff); val 1076 sound/soc/codecs/ab8500-codec.c snd_soc_component_write(component, AB8500_ANCCONF7, val >> 8 & 0xff); val 1077 sound/soc/codecs/ab8500-codec.c snd_soc_component_write(component, AB8500_ANCCONF8, val & 0xff); val 1089 sound/soc/codecs/ab8500-codec.c unsigned int bnk, par, val; val 1103 sound/soc/codecs/ab8500-codec.c val = snd_soc_component_read32(component, val 1105 sound/soc/codecs/ab8500-codec.c anc_fir(component, bnk, par, val); val 1111 sound/soc/codecs/ab8500-codec.c val = snd_soc_component_read32(component, val 1113 sound/soc/codecs/ab8500-codec.c anc_iir(component, bnk, par, val); val 1142 sound/soc/codecs/ab8500-codec.c unsigned int param, sidconf, val; val 1171 sound/soc/codecs/ab8500-codec.c val = snd_soc_component_read32(component, drvdata->sid_fir_values[param]); val 1172 sound/soc/codecs/ab8500-codec.c snd_soc_component_write(component, AB8500_SIDFIRCOEF1, val >> 8 & 0xff); val 1173 sound/soc/codecs/ab8500-codec.c snd_soc_component_write(component, AB8500_SIDFIRCOEF2, val & 0xff); val 2039 sound/soc/codecs/ab8500-codec.c unsigned int mask, val; val 2043 sound/soc/codecs/ab8500-codec.c val = 0; val 2049 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0DEL); val 2060 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); val 2070 sound/soc/codecs/ab8500-codec.c unsigned int val; val 2075 sound/soc/codecs/ab8500-codec.c val = BIT(AB8500_DIGIFCONF1_ENMASTGEN); val 2081 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); val 2094 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val); val 2102 sound/soc/codecs/ab8500-codec.c unsigned int val; val 2112 sound/soc/codecs/ab8500-codec.c val = 0; val 2118 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF3_IF0MASTER); val 2137 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val); val 2154 sound/soc/codecs/ab8500-codec.c val = 0; val 2159 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1); val 2166 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); val 2173 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); val 2194 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); val 2200 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); val 2206 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); val 2207 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); val 2216 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); val 2226 sound/soc/codecs/ab8500-codec.c unsigned int val, mask, slot, slots_active; val 2230 sound/soc/codecs/ab8500-codec.c val = 0; val 2236 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0WL0); val 2239 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0WL1); val 2242 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0WL1) | val 2253 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); val 2261 sound/soc/codecs/ab8500-codec.c val = AB8500_MASK_NONE; val 2264 sound/soc/codecs/ab8500-codec.c val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0); val 2267 sound/soc/codecs/ab8500-codec.c val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); val 2270 sound/soc/codecs/ab8500-codec.c val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | val 2279 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val); val 554 sound/soc/codecs/adau1373.c unsigned int val; val 557 sound/soc/codecs/adau1373.c val = ADAU1373_PLL_CTRL6_PLL_EN; val 559 sound/soc/codecs/adau1373.c val = 0; val 562 sound/soc/codecs/adau1373.c ADAU1373_PLL_CTRL6_PLL_EN, val); val 1355 sound/soc/codecs/adau1373.c unsigned int val; val 1374 sound/soc/codecs/adau1373.c val = 0; val 1377 sound/soc/codecs/adau1373.c val |= BIT(i); val 1379 sound/soc/codecs/adau1373.c regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val); val 1381 sound/soc/codecs/adau1373.c val = 0; val 1383 sound/soc/codecs/adau1373.c val |= ADAU1373_OUTPUT_CTRL_LDIFF; val 1385 sound/soc/codecs/adau1373.c val |= ADAU1373_OUTPUT_CTRL_LNFBEN; val 1386 sound/soc/codecs/adau1373.c regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val); val 261 sound/soc/codecs/adau1701.c unsigned int val; val 266 sound/soc/codecs/adau1701.c ret = regmap_read(adau1701->regmap, ADAU1701_DSPCTRL, &val); val 270 sound/soc/codecs/adau1701.c if (val & ADAU1701_DSPCTRL_IST) val 369 sound/soc/codecs/adau1701.c unsigned int val; val 373 sound/soc/codecs/adau1701.c val = ADAU1701_SEROCTL_WORD_LEN_16; val 376 sound/soc/codecs/adau1701.c val = ADAU1701_SEROCTL_WORD_LEN_20; val 379 sound/soc/codecs/adau1701.c val = ADAU1701_SEROCTL_WORD_LEN_24; val 388 sound/soc/codecs/adau1701.c val |= ADAU1701_SEROCTL_MSB_DEALY16; val 391 sound/soc/codecs/adau1701.c val |= ADAU1701_SEROCTL_MSB_DEALY12; val 394 sound/soc/codecs/adau1701.c val |= ADAU1701_SEROCTL_MSB_DEALY8; val 400 sound/soc/codecs/adau1701.c regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val); val 409 sound/soc/codecs/adau1701.c unsigned int val; val 416 sound/soc/codecs/adau1701.c val = ADAU1701_SERICTL_RIGHTJ_16; val 419 sound/soc/codecs/adau1701.c val = ADAU1701_SERICTL_RIGHTJ_20; val 422 sound/soc/codecs/adau1701.c val = ADAU1701_SERICTL_RIGHTJ_24; val 429 sound/soc/codecs/adau1701.c ADAU1701_SERICTL_MODE_MASK, val); val 440 sound/soc/codecs/adau1701.c unsigned int val; val 456 sound/soc/codecs/adau1701.c val = ADAU1701_DSPCTRL_SR_192; val 459 sound/soc/codecs/adau1701.c val = ADAU1701_DSPCTRL_SR_96; val 462 sound/soc/codecs/adau1701.c val = ADAU1701_DSPCTRL_SR_48; val 469 sound/soc/codecs/adau1701.c ADAU1701_DSPCTRL_SR_MASK, val); val 581 sound/soc/codecs/adau1701.c unsigned int val; val 584 sound/soc/codecs/adau1701.c val = 0; val 586 sound/soc/codecs/adau1701.c val = mask; val 588 sound/soc/codecs/adau1701.c regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val); val 596 sound/soc/codecs/adau1701.c unsigned int val; val 601 sound/soc/codecs/adau1701.c val = 0x0; val 604 sound/soc/codecs/adau1701.c val = ADAU1701_OSCIPOW_OPD; val 611 sound/soc/codecs/adau1701.c ADAU1701_OSCIPOW_OPD, val); val 669 sound/soc/codecs/adau1701.c unsigned int val; val 697 sound/soc/codecs/adau1701.c val = 0; val 699 sound/soc/codecs/adau1701.c val |= adau1701->pin_config[i] << (i * 4); val 701 sound/soc/codecs/adau1701.c regmap_write(adau1701->regmap, ADAU1701_PINCONF_0, val); val 703 sound/soc/codecs/adau1701.c val = 0; val 705 sound/soc/codecs/adau1701.c val |= adau1701->pin_config[i + 6] << (i * 4); val 707 sound/soc/codecs/adau1701.c regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val); val 492 sound/soc/codecs/adau1761.c unsigned int val = 0; val 507 sound/soc/codecs/adau1761.c val |= pdata->jackdetect_debounce_time << 6; val 513 sound/soc/codecs/adau1761.c val |= ADAU1761_DIGMIC_JACKDETECT_ACTIVE_LOW; val 538 sound/soc/codecs/adau1761.c val |= ADAU1761_DIGMIC_JACKDETECT_DIGMIC; val 544 sound/soc/codecs/adau1761.c regmap_write(adau->regmap, ADAU1761_DIGMIC_JACKDETECT, val); val 371 sound/soc/codecs/adau1781.c unsigned int val; val 374 sound/soc/codecs/adau1781.c val = ADAU1781_INPUT_DIFFERNTIAL; val 376 sound/soc/codecs/adau1781.c val = 0; val 379 sound/soc/codecs/adau1781.c ADAU1781_INPUT_DIFFERNTIAL, val); val 195 sound/soc/codecs/adau17x1.c unsigned int val, change; val 203 sound/soc/codecs/adau17x1.c val = 0; val 207 sound/soc/codecs/adau17x1.c val = (adau->tdm_slot[stream] * 2) + 1; val 217 sound/soc/codecs/adau17x1.c change = snd_soc_component_test_bits(component, reg, 0xff, val); val 222 sound/soc/codecs/adau17x1.c update.val = val; val 238 sound/soc/codecs/adau17x1.c unsigned int reg, val; val 246 sound/soc/codecs/adau17x1.c ret = regmap_read(adau->regmap, reg, &val); val 250 sound/soc/codecs/adau17x1.c if (val != 0) val 251 sound/soc/codecs/adau17x1.c val = 1; val 252 sound/soc/codecs/adau17x1.c ucontrol->value.enumerated.item[0] = val; val 463 sound/soc/codecs/adau17x1.c unsigned int val, div, dsp_div; val 535 sound/soc/codecs/adau17x1.c val = ADAU17X1_SERIAL_PORT1_DELAY16; val 538 sound/soc/codecs/adau17x1.c val = ADAU17X1_SERIAL_PORT1_DELAY8; val 541 sound/soc/codecs/adau17x1.c val = ADAU17X1_SERIAL_PORT1_DELAY0; val 548 sound/soc/codecs/adau17x1.c ADAU17X1_SERIAL_PORT1_DELAY_MASK, val); val 405 sound/soc/codecs/adau1977.c unsigned int val; val 448 sound/soc/codecs/adau1977.c ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val); val 452 sound/soc/codecs/adau1977.c if (val == 0x41) { val 606 sound/soc/codecs/adau1977.c unsigned int val; val 609 sound/soc/codecs/adau1977.c val = ADAU1977_MISC_CONTROL_MMUTE; val 611 sound/soc/codecs/adau1977.c val = 0; val 614 sound/soc/codecs/adau1977.c ADAU1977_MISC_CONTROL_MMUTE, val); val 732 sound/soc/codecs/adau1977.c unsigned int val; val 735 sound/soc/codecs/adau1977.c val = ADAU1977_SAI_OVERTEMP_DRV_HIZ; val 737 sound/soc/codecs/adau1977.c val = 0; val 740 sound/soc/codecs/adau1977.c ADAU1977_SAI_OVERTEMP_DRV_HIZ, val); val 286 sound/soc/codecs/adav80x.c unsigned int val; val 291 sound/soc/codecs/adav80x.c val = ADAV80X_DAC_CTRL2_DEEMPH_32; val 294 sound/soc/codecs/adav80x.c val = ADAV80X_DAC_CTRL2_DEEMPH_44; val 300 sound/soc/codecs/adav80x.c val = ADAV80X_DAC_CTRL2_DEEMPH_48; val 303 sound/soc/codecs/adav80x.c val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; val 307 sound/soc/codecs/adav80x.c val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; val 311 sound/soc/codecs/adav80x.c ADAV80X_DAC_CTRL2_DEEMPH_MASK, val); val 421 sound/soc/codecs/adav80x.c unsigned int val; val 424 sound/soc/codecs/adav80x.c val = ADAV80X_ADC_CTRL1_MODULATOR_128FS; val 426 sound/soc/codecs/adav80x.c val = ADAV80X_ADC_CTRL1_MODULATOR_64FS; val 429 sound/soc/codecs/adav80x.c ADAV80X_ADC_CTRL1_MODULATOR_MASK, val); val 438 sound/soc/codecs/adav80x.c unsigned int val; val 441 sound/soc/codecs/adav80x.c val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS; val 443 sound/soc/codecs/adav80x.c val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS; val 447 sound/soc/codecs/adav80x.c val); val 456 sound/soc/codecs/adav80x.c unsigned int val; val 460 sound/soc/codecs/adav80x.c val = ADAV80X_CAPTURE_WORD_LEN16; val 463 sound/soc/codecs/adav80x.c val = ADAV80X_CAPTRUE_WORD_LEN18; val 466 sound/soc/codecs/adav80x.c val = ADAV80X_CAPTURE_WORD_LEN20; val 469 sound/soc/codecs/adav80x.c val = ADAV80X_CAPTURE_WORD_LEN24; val 476 sound/soc/codecs/adav80x.c ADAV80X_CAPTURE_WORD_LEN_MASK, val); val 485 sound/soc/codecs/adav80x.c unsigned int val; val 492 sound/soc/codecs/adav80x.c val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16; val 495 sound/soc/codecs/adav80x.c val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18; val 498 sound/soc/codecs/adav80x.c val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20; val 501 sound/soc/codecs/adav80x.c val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24; val 508 sound/soc/codecs/adav80x.c ADAV80X_PLAYBACK_MODE_MASK, val); val 66 sound/soc/codecs/ak4104.c int val = 0; val 74 sound/soc/codecs/ak4104.c val |= AK4104_CONTROL1_DIF0; val 77 sound/soc/codecs/ak4104.c val |= AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1; val 90 sound/soc/codecs/ak4104.c val); val 103 sound/soc/codecs/ak4104.c int ret, val = 0; val 106 sound/soc/codecs/ak4104.c val |= IEC958_AES0_CON_NOT_COPYRIGHT; val 107 sound/soc/codecs/ak4104.c regmap_write(ak4104->regmap, AK4104_REG_CHN_STATUS(0), val); val 109 sound/soc/codecs/ak4104.c val = 0; val 113 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_22050; val 116 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_24000; val 119 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_32000; val 122 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_44100; val 125 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_48000; val 128 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_88200; val 131 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_96000; val 134 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_176400; val 137 sound/soc/codecs/ak4104.c val |= IEC958_AES3_CON_FS_192000; val 144 sound/soc/codecs/ak4104.c ret = regmap_write(ak4104->regmap, AK4104_REG_CHN_STATUS(3), val); val 269 sound/soc/codecs/ak4104.c unsigned int val; val 305 sound/soc/codecs/ak4104.c ret = regmap_read(ak4104->regmap, AK4104_REG_RESERVED, &val); val 308 sound/soc/codecs/ak4104.c if (val != AK4104_RESERVED_VAL) val 129 sound/soc/codecs/ak4642.c #define FSs(val) (((val & 0x7) << 0) | ((val & 0x8) << 2)) val 130 sound/soc/codecs/ak4642.c #define PSs(val) ((val & 0x3) << 6) val 86 sound/soc/codecs/arizona.c int val; val 90 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, val 92 sound/soc/codecs/arizona.c if (val & ARIZONA_SPK_OVERHEAT_STS) { val 117 sound/soc/codecs/arizona.c unsigned int val; val 121 sound/soc/codecs/arizona.c &val); val 125 sound/soc/codecs/arizona.c } else if (val & ARIZONA_SPK_OVERHEAT_WARN_STS) { val 135 sound/soc/codecs/arizona.c unsigned int val; val 139 sound/soc/codecs/arizona.c &val); val 143 sound/soc/codecs/arizona.c } else if (val & ARIZONA_SPK_OVERHEAT_STS) { val 296 sound/soc/codecs/arizona.c unsigned int val, mask; val 304 sound/soc/codecs/arizona.c val = ARIZONA_OUT1_MONO; val 306 sound/soc/codecs/arizona.c val = 0; val 310 sound/soc/codecs/arizona.c ARIZONA_OUT1_MONO, val); val 330 sound/soc/codecs/arizona.c val = pdata->dmic_ref[i] << ARIZONA_IN1_DMIC_SUP_SHIFT; val 332 sound/soc/codecs/arizona.c val |= 1 << ARIZONA_IN1_MODE_SHIFT; val 354 sound/soc/codecs/arizona.c val |= 1 << ARIZONA_IN1_SINGLE_ENDED_SHIFT; val 364 sound/soc/codecs/arizona.c mask, val); val 883 sound/soc/codecs/arizona.c unsigned int val; val 887 sound/soc/codecs/arizona.c val = ARIZONA_IN_VU; val 889 sound/soc/codecs/arizona.c val = 0; val 894 sound/soc/codecs/arizona.c ARIZONA_IN_VU, val); val 900 sound/soc/codecs/arizona.c unsigned int val = snd_soc_component_read32(component, reg); val 902 sound/soc/codecs/arizona.c return !(val & ARIZONA_IN1_MODE_MASK); val 1078 sound/soc/codecs/arizona.c unsigned int val; val 1082 sound/soc/codecs/arizona.c val = mask; val 1085 sound/soc/codecs/arizona.c val = 0; val 1096 sound/soc/codecs/arizona.c priv->arizona->hp_ena |= val; val 1100 sound/soc/codecs/arizona.c val = 0; val 1103 sound/soc/codecs/arizona.c mask, val); val 1242 sound/soc/codecs/arizona.c unsigned int val; val 1246 sound/soc/codecs/arizona.c val = 1 << w->shift; val 1249 sound/soc/codecs/arizona.c val = 1 << (w->shift + 1); val 1255 sound/soc/codecs/arizona.c snd_soc_component_write(component, ARIZONA_CLOCK_CONTROL, val); val 1329 sound/soc/codecs/arizona.c unsigned int val; val 1333 sound/soc/codecs/arizona.c ret = regmap_read(arizona->regmap, w->reg, &val); val 1339 sound/soc/codecs/arizona.c val = (val & ARIZONA_SYSCLK_SRC_MASK) >> ARIZONA_SYSCLK_SRC_SHIFT; val 1341 sound/soc/codecs/arizona.c switch (val) { val 1372 sound/soc/codecs/arizona.c unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT; val 1400 sound/soc/codecs/arizona.c val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; val 1404 sound/soc/codecs/arizona.c val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; val 1408 sound/soc/codecs/arizona.c val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; val 1412 sound/soc/codecs/arizona.c val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; val 1416 sound/soc/codecs/arizona.c val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; val 1420 sound/soc/codecs/arizona.c val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; val 1433 sound/soc/codecs/arizona.c val |= ARIZONA_SYSCLK_FRAC; val 1437 sound/soc/codecs/arizona.c return regmap_update_bits(arizona->regmap, reg, mask, val); val 1756 sound/soc/codecs/arizona.c int val; val 1758 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, base + ARIZONA_AIF_BCLK_CTRL); val 1759 sound/soc/codecs/arizona.c if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK)) val 1762 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, base + ARIZONA_AIF_TX_BCLK_RATE); val 1763 sound/soc/codecs/arizona.c if (lrclk != (val & ARIZONA_AIF1TX_BCPF_MASK)) val 1766 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, base + ARIZONA_AIF_FRAME_CTRL_1); val 1767 sound/soc/codecs/arizona.c if (frame != (val & (ARIZONA_AIF1TX_WL_MASK | val 1783 sound/soc/codecs/arizona.c int i, ret, val; val 1816 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, base + ARIZONA_AIF_FORMAT); val 1817 sound/soc/codecs/arizona.c val &= ARIZONA_AIF1_FMT_MASK; val 1818 sound/soc/codecs/arizona.c if ((channels & 1) && (val == ARIZONA_FMT_I2S_MODE)) { val 2382 sound/soc/codecs/arizona.c unsigned int val; val 2386 sound/soc/codecs/arizona.c ret = regmap_read(arizona->regmap, base + 6, &val); val 2393 sound/soc/codecs/arizona.c val &= ARIZONA_FLL1_CLK_REF_SRC_MASK; val 2394 sound/soc/codecs/arizona.c val >>= ARIZONA_FLL1_CLK_REF_SRC_SHIFT; val 2396 sound/soc/codecs/arizona.c switch (val) { val 2423 sound/soc/codecs/arizona.c unsigned int val; val 2510 sound/soc/codecs/arizona.c val = 0; val 2519 sound/soc/codecs/arizona.c &val); val 2520 sound/soc/codecs/arizona.c if (val & (ARIZONA_FLL1_CLOCK_OK_STS << (fll->id - 1))) val 2615 sound/soc/codecs/arizona.c unsigned int val; val 2623 sound/soc/codecs/arizona.c regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val); val 2624 sound/soc/codecs/arizona.c switch (val & ARIZONA_CLK_32K_SRC_MASK) { val 2627 sound/soc/codecs/arizona.c fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK; val 2664 sound/soc/codecs/arizona.c unsigned int reg, val; val 2672 sound/soc/codecs/arizona.c val = ARIZONA_OUT1_MONO; val 2674 sound/soc/codecs/arizona.c val = 0; val 2677 sound/soc/codecs/arizona.c ARIZONA_OUT1_MONO, val); val 2729 sound/soc/codecs/arizona.c unsigned int val; val 2752 sound/soc/codecs/arizona.c ret = regmap_read(arizona->regmap, params->base, &val); val 2756 sound/soc/codecs/arizona.c val &= ~ARIZONA_EQ1_B1_MODE; val 2757 sound/soc/codecs/arizona.c data[0] |= cpu_to_be16(val); val 2773 sound/soc/codecs/arizona.c s16 val = be16_to_cpu(*data); val 2775 sound/soc/codecs/arizona.c if (abs(val) >= 4096) { val 2790 sound/soc/codecs/arizona.c u32 val; val 2796 sound/soc/codecs/arizona.c of_property_for_each_u32(np, "wlf,inmode", prop, cur, val) { val 2800 sound/soc/codecs/arizona.c pdata->inmode[count] = val; val 2805 sound/soc/codecs/arizona.c of_property_for_each_u32(np, "wlf,dmic-ref", prop, cur, val) { val 2809 sound/soc/codecs/arizona.c pdata->dmic_ref[count] = val; val 2814 sound/soc/codecs/arizona.c of_property_for_each_u32(np, "wlf,out-mono", prop, cur, val) { val 2818 sound/soc/codecs/arizona.c pdata->out_mono[count] = !!val; val 2823 sound/soc/codecs/arizona.c of_property_for_each_u32(np, "wlf,max-channels-clocked", prop, cur, val) { val 2827 sound/soc/codecs/arizona.c pdata->max_channels_clocked[count] = val; val 2832 sound/soc/codecs/arizona.c of_property_for_each_u32(np, "wlf,out-volume-limit", prop, cur, val) { val 2836 sound/soc/codecs/arizona.c pdata->out_vol_limit[count] = val; val 220 sound/soc/codecs/cpcap.c u16 val; val 955 sound/soc/codecs/cpcap.c u16 mask, val; val 989 sound/soc/codecs/cpcap.c val = BIT(CPCAP_BIT_CDC_PLL_SEL); val 991 sound/soc/codecs/cpcap.c mask, val); val 1156 sound/soc/codecs/cpcap.c u16 val = 0x0000; val 1167 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_SMB_ST_DAC); val 1176 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_FS_INV); val 1177 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_CLK_INV); val 1180 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_FS_INV); val 1181 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_CLK_INV); val 1184 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_FS_INV); val 1185 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_CLK_INV); val 1188 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_FS_INV); val 1189 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_CLK_INV); val 1196 sound/soc/codecs/cpcap.c if (val & BIT(CPCAP_BIT_ST_CLK_INV)) val 1197 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_CLK_INV); val 1199 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_CLK_INV); val 1203 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0); val 1204 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1); val 1208 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0); val 1209 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1); val 1211 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0); val 1215 sound/soc/codecs/cpcap.c dev_dbg(dev, "HiFi dai format: val=%04x", val); val 1216 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); val 1225 sound/soc/codecs/cpcap.c u16 val; val 1228 sound/soc/codecs/cpcap.c val = 0; val 1230 sound/soc/codecs/cpcap.c val = BIT(CPCAP_BIT_ST_DAC_SW); val 1233 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); val 1254 sound/soc/codecs/cpcap.c u16 val, mask; val 1272 sound/soc/codecs/cpcap.c val = 0x0000; val 1274 sound/soc/codecs/cpcap.c val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0); val 1275 sound/soc/codecs/cpcap.c err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val); val 1304 sound/soc/codecs/cpcap.c u16 val = 0x0000; val 1316 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_SMB_CDC); val 1320 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_SMB_CDC); val 1326 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CLK_INV); val 1327 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_FS_INV); val 1330 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CLK_INV); val 1331 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_FS_INV); val 1334 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_CLK_INV); val 1335 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_FS_INV); val 1338 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_CLK_INV); val 1339 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_FS_INV); val 1346 sound/soc/codecs/cpcap.c if (val & BIT(CPCAP_BIT_CLK_INV)) val 1347 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_CLK_INV); val 1349 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CLK_INV); val 1354 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0); val 1355 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); val 1359 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0); val 1360 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); val 1364 sound/soc/codecs/cpcap.c dev_dbg(component->dev, "Voice dai format: val=%04x", val); val 1365 sound/soc/codecs/cpcap.c err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val); val 1369 sound/soc/codecs/cpcap.c cpcap->codec_format = val; val 1379 sound/soc/codecs/cpcap.c u16 val; val 1382 sound/soc/codecs/cpcap.c val = 0; val 1384 sound/soc/codecs/cpcap.c val = BIT(CPCAP_BIT_CDC_SW); val 1387 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); val 1475 sound/soc/codecs/cpcap.c cpcap_default_regs[i].val); val 204 sound/soc/codecs/cs35l32.c unsigned int val; val 208 sound/soc/codecs/cs35l32.c val = CS35L32_MCLK_RATIO; val 211 sound/soc/codecs/cs35l32.c val = CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO; val 214 sound/soc/codecs/cs35l32.c val = 0; val 217 sound/soc/codecs/cs35l32.c val = CS35L32_MCLK_DIV2_MASK; val 224 sound/soc/codecs/cs35l32.c CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO_MASK, val); val 270 sound/soc/codecs/cs35l32.c unsigned int val; val 272 sound/soc/codecs/cs35l32.c if (of_property_read_u32(np, "cirrus,sdout-share", &val) >= 0) val 273 sound/soc/codecs/cs35l32.c pdata->sdout_share = val; val 275 sound/soc/codecs/cs35l32.c if (of_property_read_u32(np, "cirrus,boost-manager", &val)) val 276 sound/soc/codecs/cs35l32.c val = -1u; val 278 sound/soc/codecs/cs35l32.c switch (val) { val 283 sound/soc/codecs/cs35l32.c pdata->boost_mng = val; val 288 sound/soc/codecs/cs35l32.c "Wrong cirrus,boost-manager DT value %d\n", val); val 292 sound/soc/codecs/cs35l32.c if (of_property_read_u32(np, "cirrus,sdout-datacfg", &val)) val 293 sound/soc/codecs/cs35l32.c val = -1u; val 294 sound/soc/codecs/cs35l32.c switch (val) { val 299 sound/soc/codecs/cs35l32.c pdata->sdout_datacfg = val; val 304 sound/soc/codecs/cs35l32.c "Wrong cirrus,sdout-datacfg DT value %d\n", val); val 308 sound/soc/codecs/cs35l32.c if (of_property_read_u32(np, "cirrus,battery-threshold", &val)) val 309 sound/soc/codecs/cs35l32.c val = -1u; val 310 sound/soc/codecs/cs35l32.c switch (val) { val 315 sound/soc/codecs/cs35l32.c pdata->batt_thresh = val; val 320 sound/soc/codecs/cs35l32.c "Wrong cirrus,battery-threshold DT value %d\n", val); val 324 sound/soc/codecs/cs35l32.c if (of_property_read_u32(np, "cirrus,battery-recovery", &val)) val 325 sound/soc/codecs/cs35l32.c val = -1u; val 326 sound/soc/codecs/cs35l32.c switch (val) { val 333 sound/soc/codecs/cs35l32.c pdata->batt_recov = val; val 338 sound/soc/codecs/cs35l32.c "Wrong cirrus,battery-recovery DT value %d\n", val); val 230 sound/soc/codecs/cs35l33.c unsigned int val; val 236 sound/soc/codecs/cs35l33.c val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM; val 238 sound/soc/codecs/cs35l33.c CS35L33_PDN_TDM, val); val 273 sound/soc/codecs/cs35l33.c unsigned int val, val2; val 279 sound/soc/codecs/cs35l33.c val = CS35L33_SDOUT_3ST_I2S; val 284 sound/soc/codecs/cs35l33.c val = CS35L33_PDN_TDM; val 291 sound/soc/codecs/cs35l33.c val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM; val 301 sound/soc/codecs/cs35l33.c mask, val); val 362 sound/soc/codecs/cs35l33.c unsigned int val; val 377 sound/soc/codecs/cs35l33.c regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val); val 379 sound/soc/codecs/cs35l33.c if (val & CS35L33_PDN_DONE) val 809 sound/soc/codecs/cs35l34.c unsigned int val; val 812 sound/soc/codecs/cs35l34.c &val) >= 0) { val 814 sound/soc/codecs/cs35l34.c if (val > 8000 || (val < 3300 && val > 0)) { val 816 sound/soc/codecs/cs35l34.c "Invalid Boost Voltage %d mV\n", val); val 819 sound/soc/codecs/cs35l34.c if (val == 0) val 822 sound/soc/codecs/cs35l34.c pdata->boost_vtge = ((val - 3300)/100) + 1; val 828 sound/soc/codecs/cs35l34.c if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) { val 829 sound/soc/codecs/cs35l34.c pdata->boost_ind = val; val 835 sound/soc/codecs/cs35l34.c if (of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val) >= 0) { val 836 sound/soc/codecs/cs35l34.c if (val > 3840 || val < 1200) { val 838 sound/soc/codecs/cs35l34.c "Invalid Boost Peak Current %d mA\n", val); val 841 sound/soc/codecs/cs35l34.c pdata->boost_peak = ((val - 1200)/80) + 1; val 853 sound/soc/codecs/cs35l34.c if (of_property_read_u32(np, "cirrus,i2s-sdinloc", &val) >= 0) val 854 sound/soc/codecs/cs35l34.c pdata->i2s_sdinloc = val; val 855 sound/soc/codecs/cs35l34.c if (of_property_read_u32(np, "cirrus,tdm-rising-edge", &val) >= 0) val 856 sound/soc/codecs/cs35l34.c pdata->tdm_rising_edge = val; val 476 sound/soc/codecs/cs35l36.c int val = (ucontrol->value.integer.value[0]) ? CS35L36_NG_AMP_EN_MASK : val 479 sound/soc/codecs/cs35l36.c cs35l36->ldm_mode_sel = val; val 482 sound/soc/codecs/cs35l36.c CS35L36_NG_AMP_EN_MASK, val); val 1437 sound/soc/codecs/cs35l36.c unsigned int val; val 1443 sound/soc/codecs/cs35l36.c ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val); val 1445 sound/soc/codecs/cs35l36.c if (val < 2550 || val > 12000) { val 1447 sound/soc/codecs/cs35l36.c "Invalid Boost Voltage %d mV\n", val); val 1450 sound/soc/codecs/cs35l36.c pdata->bst_vctl = (((val - 2550) / 100) + 1) << 1; val 1457 sound/soc/codecs/cs35l36.c ret = of_property_read_u32(np, "cirrus,boost-ctl-select", &val); val 1459 sound/soc/codecs/cs35l36.c pdata->bst_vctl_sel = val | CS35L36_VALID_PDATA; val 1461 sound/soc/codecs/cs35l36.c ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val); val 1463 sound/soc/codecs/cs35l36.c if (val < 1600 || val > 4500) { val 1465 sound/soc/codecs/cs35l36.c "Invalid Boost Peak Current %u mA\n", val); val 1469 sound/soc/codecs/cs35l36.c pdata->bst_ipk = (val - 1600) / 50; val 1491 sound/soc/codecs/cs35l36.c if (of_property_read_u32(np, "cirrus,temp-warn-threshold", &val) >= 0) val 1492 sound/soc/codecs/cs35l36.c pdata->temp_warn_thld = val | CS35L36_VALID_PDATA; val 1494 sound/soc/codecs/cs35l36.c if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) { val 1495 sound/soc/codecs/cs35l36.c pdata->boost_ind = val; val 1501 sound/soc/codecs/cs35l36.c if (of_property_read_u32(np, "cirrus,irq-drive-select", &val) >= 0) val 1502 sound/soc/codecs/cs35l36.c pdata->irq_drv_sel = val | CS35L36_VALID_PDATA; val 1504 sound/soc/codecs/cs35l36.c if (of_property_read_u32(np, "cirrus,irq-gpio-select", &val) >= 0) val 1505 sound/soc/codecs/cs35l36.c pdata->irq_gpio_sel = val | CS35L36_VALID_PDATA; val 1512 sound/soc/codecs/cs35l36.c &val) >= 0) val 1513 sound/soc/codecs/cs35l36.c vpbr_config->vpbr_en = val; val 1515 sound/soc/codecs/cs35l36.c &val) >= 0) val 1516 sound/soc/codecs/cs35l36.c vpbr_config->vpbr_thld = val; val 1518 sound/soc/codecs/cs35l36.c &val) >= 0) val 1519 sound/soc/codecs/cs35l36.c vpbr_config->vpbr_atk_rate = val; val 1521 sound/soc/codecs/cs35l36.c &val) >= 0) val 1522 sound/soc/codecs/cs35l36.c vpbr_config->vpbr_atk_vol = val; val 1524 sound/soc/codecs/cs35l36.c &val) >= 0) val 1525 sound/soc/codecs/cs35l36.c vpbr_config->vpbr_max_attn = val; val 1527 sound/soc/codecs/cs35l36.c &val) >= 0) val 1528 sound/soc/codecs/cs35l36.c vpbr_config->vpbr_wait = val; val 1530 sound/soc/codecs/cs35l36.c &val) >= 0) val 1531 sound/soc/codecs/cs35l36.c vpbr_config->vpbr_rel_rate = val; val 1533 sound/soc/codecs/cs35l36.c &val) >= 0) val 1534 sound/soc/codecs/cs35l36.c vpbr_config->vpbr_mute_en = val; val 1544 sound/soc/codecs/cs35l36.c unsigned int val; val 1573 sound/soc/codecs/cs35l36.c ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS, &val); val 1580 sound/soc/codecs/cs35l36.c while (!(val & CS35L36_MCU_CONFIG_CLR)) { val 1585 sound/soc/codecs/cs35l36.c &val); val 664 sound/soc/codecs/cs4270.c unsigned int val; val 693 sound/soc/codecs/cs4270.c ret = regmap_read(cs4270->regmap, CS4270_CHIPID, &val); val 700 sound/soc/codecs/cs4270.c if ((val & 0xF0) != 0xC0) { val 708 sound/soc/codecs/cs4270.c dev_info(&i2c_client->dev, "hardware revision %X\n", val & 0xF); val 212 sound/soc/codecs/cs4271.c unsigned int val = 0; val 221 sound/soc/codecs/cs4271.c val |= CS4271_MODE1_MASTER; val 230 sound/soc/codecs/cs4271.c val |= CS4271_MODE1_DAC_DIF_LJ; val 237 sound/soc/codecs/cs4271.c val |= CS4271_MODE1_DAC_DIF_I2S; val 249 sound/soc/codecs/cs4271.c CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val); val 261 sound/soc/codecs/cs4271.c int val = CS4271_DACCTL_DEM_DIS; val 265 sound/soc/codecs/cs4271.c val = 1; val 268 sound/soc/codecs/cs4271.c abs(cs4271_deemph[val] - cs4271->rate)) val 269 sound/soc/codecs/cs4271.c val = i; val 270 sound/soc/codecs/cs4271.c val <<= 4; val 274 sound/soc/codecs/cs4271.c CS4271_DACCTL_DEM_MASK, val); val 346 sound/soc/codecs/cs4271.c unsigned int ratio, val; val 379 sound/soc/codecs/cs4271.c val = CS4271_MODE1_MODE_1X; val 381 sound/soc/codecs/cs4271.c val = CS4271_MODE1_MODE_2X; val 383 sound/soc/codecs/cs4271.c val = CS4271_MODE1_MODE_4X; val 388 sound/soc/codecs/cs4271.c (cs4271_clk_tab[i].speed_mode == val) && val 397 sound/soc/codecs/cs4271.c val |= cs4271_clk_tab[i].ratio_mask; val 400 sound/soc/codecs/cs4271.c CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val); val 1573 sound/soc/codecs/cs42l42.c unsigned int val; val 1578 sound/soc/codecs/cs42l42.c ret = of_property_read_u32(np, "cirrus,ts-inv", &val); val 1581 sound/soc/codecs/cs42l42.c switch (val) { val 1584 sound/soc/codecs/cs42l42.c cs42l42->ts_inv = val; val 1589 sound/soc/codecs/cs42l42.c val); val 1600 sound/soc/codecs/cs42l42.c ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val); val 1603 sound/soc/codecs/cs42l42.c switch (val) { val 1612 sound/soc/codecs/cs42l42.c cs42l42->ts_dbnc_rise = val; val 1617 sound/soc/codecs/cs42l42.c val); val 1629 sound/soc/codecs/cs42l42.c ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val); val 1632 sound/soc/codecs/cs42l42.c switch (val) { val 1641 sound/soc/codecs/cs42l42.c cs42l42->ts_dbnc_fall = val; val 1646 sound/soc/codecs/cs42l42.c val); val 1658 sound/soc/codecs/cs42l42.c ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val); val 1661 sound/soc/codecs/cs42l42.c if ((val >= CS42L42_BTN_DET_INIT_DBNCE_MIN) && val 1662 sound/soc/codecs/cs42l42.c (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)) val 1663 sound/soc/codecs/cs42l42.c cs42l42->btn_det_init_dbnce = val; val 1667 sound/soc/codecs/cs42l42.c val); val 1676 sound/soc/codecs/cs42l42.c ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val); val 1679 sound/soc/codecs/cs42l42.c if ((val >= CS42L42_BTN_DET_EVENT_DBNCE_MIN) && val 1680 sound/soc/codecs/cs42l42.c (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)) val 1681 sound/soc/codecs/cs42l42.c cs42l42->btn_det_event_dbnce = val; val 1684 sound/soc/codecs/cs42l42.c "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); val 1714 sound/soc/codecs/cs42l42.c ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val); val 1717 sound/soc/codecs/cs42l42.c switch (val) { val 1719 sound/soc/codecs/cs42l42.c cs42l42->hs_bias_ramp_rate = val; val 1723 sound/soc/codecs/cs42l42.c cs42l42->hs_bias_ramp_rate = val; val 1727 sound/soc/codecs/cs42l42.c cs42l42->hs_bias_ramp_rate = val; val 1731 sound/soc/codecs/cs42l42.c cs42l42->hs_bias_ramp_rate = val; val 1737 sound/soc/codecs/cs42l42.c val); val 737 sound/soc/codecs/cs42l42.h #define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff) val 738 sound/soc/codecs/cs42l42.h #define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8) val 739 sound/soc/codecs/cs42l42.h #define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16) val 92 sound/soc/codecs/cs42l51.c unsigned char val; val 97 sound/soc/codecs/cs42l51.c val = CHAN_MIX_NORMAL; val 100 sound/soc/codecs/cs42l51.c val = CHAN_MIX_BOTH; val 103 sound/soc/codecs/cs42l51.c val = CHAN_MIX_SWAP; val 107 sound/soc/codecs/cs42l51.c snd_soc_component_write(component, CS42L51_PCM_MIXER, val); val 683 sound/soc/codecs/cs42l51.c unsigned int val; val 733 sound/soc/codecs/cs42l51.c ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val); val 739 sound/soc/codecs/cs42l51.c if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) && val 740 sound/soc/codecs/cs42l51.c (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) { val 741 sound/soc/codecs/cs42l51.c dev_err(dev, "Invalid chip id: %x\n", val); val 746 sound/soc/codecs/cs42l51.c val & CS42L51_CHIP_REV_MASK); val 904 sound/soc/codecs/cs42l52.c int val = 0; val 917 sound/soc/codecs/cs42l52.c val = (best << CS42L52_BEEP_RATE_SHIFT); val 926 sound/soc/codecs/cs42l52.c CS42L52_BEEP_RATE_MASK, val); val 968 sound/soc/codecs/cs42l56.c int val = 0; val 981 sound/soc/codecs/cs42l56.c val = (best << CS42L56_BEEP_RATE_SHIFT); val 990 sound/soc/codecs/cs42l56.c CS42L56_BEEP_FREQ_MASK, val); val 219 sound/soc/codecs/cs42xx8.c u32 val; val 224 sound/soc/codecs/cs42xx8.c val = CS42XX8_INTF_DAC_DIF_LEFTJ | CS42XX8_INTF_ADC_DIF_LEFTJ; val 227 sound/soc/codecs/cs42xx8.c val = CS42XX8_INTF_DAC_DIF_I2S | CS42XX8_INTF_ADC_DIF_I2S; val 230 sound/soc/codecs/cs42xx8.c val = CS42XX8_INTF_DAC_DIF_RIGHTJ | CS42XX8_INTF_ADC_DIF_RIGHTJ; val 233 sound/soc/codecs/cs42xx8.c val = CS42XX8_INTF_DAC_DIF_TDM | CS42XX8_INTF_ADC_DIF_TDM; val 242 sound/soc/codecs/cs42xx8.c CS42XX8_INTF_ADC_DIF_MASK, val); val 270 sound/soc/codecs/cs42xx8.c u32 i, val, mask; val 340 sound/soc/codecs/cs42xx8.c val = cs42xx8_ratios[i].mfreq; val 344 sound/soc/codecs/cs42xx8.c CS42XX8_FUNCMOD_xC_FM(tx, fm[tx]) | val); val 526 sound/soc/codecs/cs42xx8.c int ret, val, i; val 587 sound/soc/codecs/cs42xx8.c ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val); val 594 sound/soc/codecs/cs42xx8.c if (((val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4) != 0x00) { val 596 sound/soc/codecs/cs42xx8.c (val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4); val 602 sound/soc/codecs/cs42xx8.c val & CS42XX8_CHIPID_REV_ID_MASK); val 892 sound/soc/codecs/cs43130.c regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val); val 1025 sound/soc/codecs/cs43130.c unsigned int val; val 1029 sound/soc/codecs/cs43130.c val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; val 1034 sound/soc/codecs/cs43130.c if (val >= 2) val 2378 sound/soc/codecs/cs43130.c unsigned int val; val 2381 sound/soc/codecs/cs43130.c if (of_property_read_u32(np, "cirrus,xtal-ibias", &val) < 0) { val 2387 sound/soc/codecs/cs43130.c switch (val) { val 2399 sound/soc/codecs/cs43130.c "Invalid cirrus,xtal-ibias value: %d\n", val); val 476 sound/soc/codecs/cs43130.h int val; val 131 sound/soc/codecs/cs47l35.c unsigned int val; val 138 sound/soc/codecs/cs47l35.c &val); val 145 sound/soc/codecs/cs47l35.c val &= (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA); val 147 sound/soc/codecs/cs47l35.c if (val != (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA)) val 193 sound/soc/codecs/cs47l85.c unsigned int val; val 200 sound/soc/codecs/cs47l85.c &val); val 207 sound/soc/codecs/cs47l85.c val &= (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA); val 209 sound/soc/codecs/cs47l85.c if (val != (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA)) val 736 sound/soc/codecs/cs53l30.c u8 val = tristate ? CS53L30_ASP_3ST : 0; val 739 sound/soc/codecs/cs53l30.c CS53L30_ASP_3ST_MASK, val); val 926 sound/soc/codecs/cs53l30.c u8 val; val 1022 sound/soc/codecs/cs53l30.c if (!of_property_read_u8(np, "cirrus,micbias-lvl", &val)) val 1024 sound/soc/codecs/cs53l30.c CS53L30_MIC_BIAS_CTRL_MASK, val); val 491 sound/soc/codecs/cx2072x.c const void *val, size_t val_count) val 503 sound/soc/codecs/cx2072x.c memcpy(buf + 2, val, val_count); val 353 sound/soc/codecs/da7210.c u8 val; val 368 sound/soc/codecs/da7210.c val = snd_soc_component_read32(component, DA7210_IN_GAIN); val 369 sound/soc/codecs/da7210.c if (((val & DA7210_INPGA_L_VOL) < DA7210_INPGA_MIN_VOL_NS) || val 370 sound/soc/codecs/da7210.c (((val & DA7210_INPGA_R_VOL) >> 4) < val 1590 sound/soc/codecs/da7213.c da7213_of_micbias_lvl(struct snd_soc_component *component, u32 val) val 1592 sound/soc/codecs/da7213.c switch (val) { val 1634 sound/soc/codecs/da7213.c da7213_of_dmic_clkrate(struct snd_soc_component *component, u32 val) val 1636 sound/soc/codecs/da7213.c switch (val) { val 477 sound/soc/codecs/da7218.c u16 val; val 484 sound/soc/codecs/da7218.c ret = regmap_raw_read(da7218->regmap, reg, &val, 2); val 488 sound/soc/codecs/da7218.c ucontrol->value.integer.value[0] = le16_to_cpu(val); val 501 sound/soc/codecs/da7218.c u16 val; val 508 sound/soc/codecs/da7218.c val = cpu_to_le16(ucontrol->value.integer.value[0]); val 510 sound/soc/codecs/da7218.c return regmap_raw_write(da7218->regmap, reg, &val, 2); val 2299 sound/soc/codecs/da7218.c da7218_of_micbias_lvl(struct snd_soc_component *component, u32 val) val 2301 sound/soc/codecs/da7218.c switch (val) { val 2368 sound/soc/codecs/da7218.c da7218_of_dmic_clkrate(struct snd_soc_component *component, u32 val) val 2370 sound/soc/codecs/da7218.c switch (val) { val 2382 sound/soc/codecs/da7218.c da7218_of_jack_rate(struct snd_soc_component *component, u32 val) val 2384 sound/soc/codecs/da7218.c switch (val) { val 2408 sound/soc/codecs/da7218.c da7218_of_jack_debounce(struct snd_soc_component *component, u32 val) val 2410 sound/soc/codecs/da7218.c switch (val) { val 2426 sound/soc/codecs/da7218.c da7218_of_jack_thr(struct snd_soc_component *component, u32 val) val 2428 sound/soc/codecs/da7218.c switch (val) { val 463 sound/soc/codecs/da7219-aad.c da7219_aad_fw_micbias_pulse_lvl(struct snd_soc_component *component, u32 val) val 465 sound/soc/codecs/da7219-aad.c switch (val) { val 477 sound/soc/codecs/da7219-aad.c da7219_aad_fw_btn_cfg(struct snd_soc_component *component, u32 val) val 479 sound/soc/codecs/da7219-aad.c switch (val) { val 501 sound/soc/codecs/da7219-aad.c da7219_aad_fw_mic_det_thr(struct snd_soc_component *component, u32 val) val 503 sound/soc/codecs/da7219-aad.c switch (val) { val 519 sound/soc/codecs/da7219-aad.c da7219_aad_fw_jack_ins_deb(struct snd_soc_component *component, u32 val) val 521 sound/soc/codecs/da7219-aad.c switch (val) { val 562 sound/soc/codecs/da7219-aad.c da7219_aad_fw_jack_rem_deb(struct snd_soc_component *component, u32 val) val 564 sound/soc/codecs/da7219-aad.c switch (val) { val 580 sound/soc/codecs/da7219-aad.c da7219_aad_fw_btn_avg(struct snd_soc_component *component, u32 val) val 582 sound/soc/codecs/da7219-aad.c switch (val) { val 598 sound/soc/codecs/da7219-aad.c da7219_aad_fw_adc_1bit_rpt(struct snd_soc_component *component, u32 val) val 600 sound/soc/codecs/da7219-aad.c switch (val) { val 422 sound/soc/codecs/da7219.c __le16 val; val 426 sound/soc/codecs/da7219.c ret = regmap_raw_read(da7219->regmap, reg, &val, sizeof(val)); val 436 sound/soc/codecs/da7219.c ucontrol->value.integer.value[0] = le16_to_cpu(val); val 449 sound/soc/codecs/da7219.c __le16 val; val 457 sound/soc/codecs/da7219.c val = cpu_to_le16(ucontrol->value.integer.value[0]); val 460 sound/soc/codecs/da7219.c ret = regmap_raw_write(da7219->regmap, reg, &val, sizeof(val)); val 1718 sound/soc/codecs/da7219.c da7219_fw_micbias_lvl(struct device *dev, u32 val) val 1720 sound/soc/codecs/da7219.c switch (val) { val 170 sound/soc/codecs/da732x.c int val; val 174 sound/soc/codecs/da732x.c val = DA732X_MCLK_RET_0_10MHZ; val 178 sound/soc/codecs/da732x.c val = DA732X_MCLK_RET_10_20MHZ; val 182 sound/soc/codecs/da732x.c val = DA732X_MCLK_RET_20_40MHZ; val 186 sound/soc/codecs/da732x.c val = DA732X_MCLK_RET_40_54MHZ; val 192 sound/soc/codecs/da732x.c snd_soc_component_write(component, DA732X_REG_PLL_CTRL, val); val 362 sound/soc/codecs/da732x.c int val; val 364 sound/soc/codecs/da732x.c val = snd_soc_component_read32(component, reg) & DA732X_HPF_MASK; val 366 sound/soc/codecs/da732x.c switch (val) { val 107 sound/soc/codecs/es8328.c unsigned int val; val 118 sound/soc/codecs/es8328.c int val, i, best; val 132 sound/soc/codecs/es8328.c val = deemph_settings[best].val; val 134 sound/soc/codecs/es8328.c val = ES8328_DACCONTROL6_DEEMPH_OFF; val 137 sound/soc/codecs/es8328.c dev_dbg(component->dev, "Set deemphasis %d\n", val); val 140 sound/soc/codecs/es8328.c ES8328_DACCONTROL6_DEEMPH_MASK, val); val 344 sound/soc/codecs/hdac_hdmi.c int val; val 346 sound/soc/codecs/hdac_hdmi.c val = (packet_index << 5) | (byte_index & 0x1f); val 347 sound/soc/codecs/hdac_hdmi.c snd_hdac_codec_write(hdev, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); val 760 sound/soc/codecs/hdac_hdmi.c hda_nid_t nid, int val) val 764 sound/soc/codecs/hdac_hdmi.c AC_VERB_SET_AMP_GAIN_MUTE, val); val 51 sound/soc/codecs/inno_rk3036.c int val, ret, regval; val 56 sound/soc/codecs/inno_rk3036.c val = ((regval >> INNO_R09_HPL_ANITPOP_SHIFT) & val 58 sound/soc/codecs/inno_rk3036.c ucontrol->value.integer.value[0] = val; val 60 sound/soc/codecs/inno_rk3036.c val = ((regval >> INNO_R09_HPR_ANITPOP_SHIFT) & val 62 sound/soc/codecs/inno_rk3036.c ucontrol->value.integer.value[1] = val; val 71 sound/soc/codecs/inno_rk3036.c int val, ret, regmsk; val 73 sound/soc/codecs/inno_rk3036.c val = (ucontrol->value.integer.value[0] ? val 76 sound/soc/codecs/inno_rk3036.c val |= (ucontrol->value.integer.value[1] ? val 84 sound/soc/codecs/inno_rk3036.c regmsk, val); val 197 sound/soc/codecs/jz4725b.c unsigned int val; val 205 sound/soc/codecs/jz4725b.c val, val & BIT(REG_IFR_RAMP_UP_DONE_OFFSET), val 212 sound/soc/codecs/jz4725b.c val, val & BIT(REG_IFR_RAMP_DOWN_DONE_OFFSET), val 476 sound/soc/codecs/jz4725b.c unsigned int *val) val 494 sound/soc/codecs/jz4725b.c *val = readl(icdc->base + ICDC_RGDATA_OFFSET) & val 501 sound/soc/codecs/jz4725b.c unsigned int val) val 510 sound/soc/codecs/jz4725b.c writel(ICDC_RGADW_RGWR | (reg << ICDC_RGADW_RGADDR_OFFSET) | val, val 154 sound/soc/codecs/jz4740.c uint32_t val; val 158 sound/soc/codecs/jz4740.c val = 0; val 161 sound/soc/codecs/jz4740.c val = 1; val 164 sound/soc/codecs/jz4740.c val = 2; val 167 sound/soc/codecs/jz4740.c val = 3; val 170 sound/soc/codecs/jz4740.c val = 4; val 173 sound/soc/codecs/jz4740.c val = 5; val 176 sound/soc/codecs/jz4740.c val = 6; val 179 sound/soc/codecs/jz4740.c val = 7; val 182 sound/soc/codecs/jz4740.c val = 8; val 188 sound/soc/codecs/jz4740.c val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET; val 191 sound/soc/codecs/jz4740.c JZ4740_CODEC_2_SAMPLE_RATE_MASK, val); val 86 sound/soc/codecs/l3.c static void l3_set_clk(struct l3_pins *adap, int val) val 88 sound/soc/codecs/l3.c gpio_set_value(adap->gpio_clk, val); val 91 sound/soc/codecs/l3.c static void l3_set_data(struct l3_pins *adap, int val) val 93 sound/soc/codecs/l3.c gpio_set_value(adap->gpio_data, val); val 96 sound/soc/codecs/l3.c static void l3_set_mode(struct l3_pins *adap, int val) val 98 sound/soc/codecs/l3.c gpio_set_value(adap->gpio_mode, val); val 169 sound/soc/codecs/madera.c unsigned int val; val 181 sound/soc/codecs/madera.c ret = regmap_read(madera->regmap, MADERA_SOFTWARE_RESET, &val); val 205 sound/soc/codecs/madera.c unsigned int val; val 208 sound/soc/codecs/madera.c ret = regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_15, &val); val 215 sound/soc/codecs/madera.c *warn = val & MADERA_SPK_OVERHEAT_WARN_STS1; val 216 sound/soc/codecs/madera.c *shutdown = val & MADERA_SPK_OVERHEAT_STS1; val 580 sound/soc/codecs/madera.c unsigned int val; val 583 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, MADERA_OUTPUT_ENABLES_1, &val); val 587 sound/soc/codecs/madera.c val &= MADERA_EP_SEL_MASK; val 588 sound/soc/codecs/madera.c val >>= MADERA_EP_SEL_SHIFT; val 589 sound/soc/codecs/madera.c ucontrol->value.enumerated.item[0] = val; val 606 sound/soc/codecs/madera.c unsigned int mux, val, mask; val 615 sound/soc/codecs/madera.c val = mux << e->shift_l; val 636 sound/soc/codecs/madera.c val |= 1 << MADERA_IN1L_SRC_SE_SHIFT; val 639 sound/soc/codecs/madera.c mux, e->reg, inmode, mask, val); val 641 sound/soc/codecs/madera.c ret = regmap_update_bits_check(regmap, e->reg, mask, val, &changed); val 917 sound/soc/codecs/madera.c unsigned int val; val 921 sound/soc/codecs/madera.c val = priv->adsp_rate_cache[dsp->num - 1] << MADERA_DSP_RATE_SHIFT; val 929 sound/soc/codecs/madera.c val |= (freq << MADERA_DSP_CLK_SEL_SHIFT); val 944 sound/soc/codecs/madera.c mask, val); val 948 sound/soc/codecs/madera.c dev_dbg(priv->madera->dev, "Set DSP clocking to 0x%x\n", val); val 1009 sound/soc/codecs/madera.c unsigned int val; val 1021 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, e->reg, &val); val 1027 sound/soc/codecs/madera.c val >>= e->shift_l; val 1028 sound/soc/codecs/madera.c val &= e->mask; val 1029 sound/soc/codecs/madera.c if (snd_soc_enum_item_to_val(e, item) == val) { val 1172 sound/soc/codecs/madera.c unsigned int val; val 1185 sound/soc/codecs/madera.c val = MADERA_OUT1_MONO; val 1189 sound/soc/codecs/madera.c val = 0; val 1194 sound/soc/codecs/madera.c MADERA_OUT1_MONO, val); val 1196 sound/soc/codecs/madera.c dev_dbg(madera->dev, "OUT%d mono=0x%x\n", i + 1, val); val 2121 sound/soc/codecs/madera.c unsigned int val; val 2128 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, reg, &val); val 2132 sound/soc/codecs/madera.c if (val & MADERA_DFC1_ENA) { val 2155 sound/soc/codecs/madera.c unsigned int val, mask; val 2161 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, MADERA_INPUT_ENABLES, &val); val 2167 sound/soc/codecs/madera.c if (val & (1 << mask)) { val 2202 sound/soc/codecs/madera.c unsigned int val; val 2206 sound/soc/codecs/madera.c val = MADERA_IN_VU; val 2208 sound/soc/codecs/madera.c val = 0; val 2213 sound/soc/codecs/madera.c MADERA_IN_VU, val); val 2225 sound/soc/codecs/madera.c unsigned int reg, val; val 2256 sound/soc/codecs/madera.c &val); val 2257 sound/soc/codecs/madera.c if (!ret && !val) val 2376 sound/soc/codecs/madera.c unsigned int val; val 2381 sound/soc/codecs/madera.c val = mask; val 2384 sound/soc/codecs/madera.c val = 0; val 2395 sound/soc/codecs/madera.c madera->hp_ena |= val; val 2412 sound/soc/codecs/madera.c val = 0; val 2414 sound/soc/codecs/madera.c regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1, mask, val); val 2424 sound/soc/codecs/madera.c unsigned int val; val 2428 sound/soc/codecs/madera.c val = 1 << w->shift; val 2431 sound/soc/codecs/madera.c val = 1 << (w->shift + 1); val 2437 sound/soc/codecs/madera.c snd_soc_component_write(component, MADERA_CLOCK_CONTROL, val); val 2462 sound/soc/codecs/madera.c unsigned int reg, val; val 2497 sound/soc/codecs/madera.c val = (div << MADERA_OPCLK_DIV_SHIFT) | ref; val 2500 sound/soc/codecs/madera.c mask, val); val 2643 sound/soc/codecs/madera.c unsigned int val = source << MADERA_SYSCLK_SRC_SHIFT; val 2690 sound/soc/codecs/madera.c val |= clk_freq_sel; val 2709 sound/soc/codecs/madera.c val |= MADERA_SYSCLK_FRAC; val 2713 sound/soc/codecs/madera.c return regmap_update_bits(madera->regmap, reg, mask, val); val 3036 sound/soc/codecs/madera.c unsigned int val; val 3040 sound/soc/codecs/madera.c &val); val 3043 sound/soc/codecs/madera.c if (bclk != (val & MADERA_AIF1_BCLK_FREQ_MASK)) val 3047 sound/soc/codecs/madera.c &val); val 3050 sound/soc/codecs/madera.c if (lrclk != (val & MADERA_AIF1RX_BCPF_MASK)) val 3054 sound/soc/codecs/madera.c &val); val 3057 sound/soc/codecs/madera.c if (frame != (val & (MADERA_AIF1TX_WL_MASK | val 3074 sound/soc/codecs/madera.c unsigned int val; val 3112 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, base + MADERA_AIF_FORMAT, &val); val 3116 sound/soc/codecs/madera.c val &= MADERA_AIF1_FMT_MASK; val 3117 sound/soc/codecs/madera.c if ((channels & 1) && val == MADERA_FMT_I2S_MODE) { val 3760 sound/soc/codecs/madera.c unsigned int val = 0; val 3767 sound/soc/codecs/madera.c regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_2, &val); val 3768 sound/soc/codecs/madera.c status = val & (MADERA_FLL1_LOCK_STS1 << (fll->id - 1)); val 3794 sound/soc/codecs/madera.c unsigned int val; val 3798 sound/soc/codecs/madera.c val = (1 << MADERA_FLL1_PHASE_ENA_SHIFT) | val 3801 sound/soc/codecs/madera.c val = 2 << MADERA_FLL1_PHASE_GAIN_SHIFT; val 3807 sound/soc/codecs/madera.c val, ®_change); val 4138 sound/soc/codecs/madera.c unsigned int val; val 4156 sound/soc/codecs/madera.c val = patch[i].def; val 4160 sound/soc/codecs/madera.c val &= ~MADERA_FLL_AO_REFCLK_SRC_MASK; val 4161 sound/soc/codecs/madera.c val |= (fll->ref_src << MADERA_FLL_AO_REFCLK_SRC_SHIFT) val 4165 sound/soc/codecs/madera.c regmap_write(madera->regmap, patch[i].reg, val); val 4310 sound/soc/codecs/madera.c unsigned int gains, val, num; val 4431 sound/soc/codecs/madera.c val = hp << MADERA_FLL1_HP_SHIFT; val 4432 sound/soc/codecs/madera.c val |= 1 << MADERA_FLL1_PHASEDET_ENA_SHIFT; val 4436 sound/soc/codecs/madera.c val); val 4583 sound/soc/codecs/madera.c unsigned int reg, val; val 4592 sound/soc/codecs/madera.c val = MADERA_OUT1_MONO; val 4594 sound/soc/codecs/madera.c val = 0; val 4597 sound/soc/codecs/madera.c val); val 4628 sound/soc/codecs/madera.c unsigned int val; val 4651 sound/soc/codecs/madera.c ret = regmap_read(madera->regmap, params->base, &val); val 4655 sound/soc/codecs/madera.c val &= ~MADERA_EQ1_B1_MODE; val 4656 sound/soc/codecs/madera.c data[0] |= cpu_to_be16(val); val 4675 sound/soc/codecs/madera.c s16 val = be16_to_cpu(*data); val 4677 sound/soc/codecs/madera.c if (abs(val) >= 4096) { val 173 sound/soc/codecs/madera.h int val; val 45 sound/soc/codecs/max9768.c int val = gpio_get_value_cansleep(max9768->mute_gpio); val 47 sound/soc/codecs/max9768.c ucontrol->value.integer.value[0] = !val; val 356 sound/soc/codecs/max98090.c unsigned int val = snd_soc_component_read32(component, mc->reg); val 373 sound/soc/codecs/max98090.c val = (val >> mc->shift) & mask; val 375 sound/soc/codecs/max98090.c if (val >= 1) { val 377 sound/soc/codecs/max98090.c val = val - 1; val 378 sound/soc/codecs/max98090.c *select = val; val 381 sound/soc/codecs/max98090.c val = *select; val 384 sound/soc/codecs/max98090.c ucontrol->value.integer.value[0] = val; val 397 sound/soc/codecs/max98090.c unsigned int val = snd_soc_component_read32(component, mc->reg); val 414 sound/soc/codecs/max98090.c val = (val >> mc->shift) & mask; val 419 sound/soc/codecs/max98090.c if (val >= 1) { val 423 sound/soc/codecs/max98090.c sel = val; val 733 sound/soc/codecs/max98090.c unsigned int val = snd_soc_component_read32(component, w->reg); val 736 sound/soc/codecs/max98090.c val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; val 738 sound/soc/codecs/max98090.c val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; val 740 sound/soc/codecs/max98090.c if (val >= 1) { val 742 sound/soc/codecs/max98090.c max98090->pa1en = val - 1; /* Update for volatile */ val 744 sound/soc/codecs/max98090.c max98090->pa2en = val - 1; /* Update for volatile */ val 752 sound/soc/codecs/max98090.c val = max98090->pa1en + 1; val 754 sound/soc/codecs/max98090.c val = max98090->pa2en + 1; val 758 sound/soc/codecs/max98090.c val = 0; val 766 sound/soc/codecs/max98090.c val << M98090_MIC_PA1EN_SHIFT); val 769 sound/soc/codecs/max98090.c val << M98090_MIC_PA2EN_SHIFT); val 185 sound/soc/codecs/max98371.c unsigned int val = 0; val 197 sound/soc/codecs/max98371.c val |= 0; val 200 sound/soc/codecs/max98371.c val |= MAX98371_DAI_RIGHT; val 203 sound/soc/codecs/max98371.c val |= MAX98371_DAI_LEFT; val 210 sound/soc/codecs/max98371.c MAX98371_FMT_MODE_MASK, val); val 118 sound/soc/codecs/mc13783.c unsigned int val; val 122 sound/soc/codecs/mc13783.c val = 0; val 125 sound/soc/codecs/mc13783.c val = AUDIO_CODEC_CDCFS8K16K; val 132 sound/soc/codecs/mc13783.c val); val 151 sound/soc/codecs/mc13783.c unsigned int val = 0; val 159 sound/soc/codecs/mc13783.c val |= AUDIO_CFS(2); val 162 sound/soc/codecs/mc13783.c val |= AUDIO_CFS(1); val 171 sound/soc/codecs/mc13783.c val |= AUDIO_BCL_INV; val 174 sound/soc/codecs/mc13783.c val |= AUDIO_BCL_INV | AUDIO_CFS_INV; val 179 sound/soc/codecs/mc13783.c val |= AUDIO_CFS_INV; val 186 sound/soc/codecs/mc13783.c val |= AUDIO_C_CLK_EN; val 189 sound/soc/codecs/mc13783.c val |= AUDIO_CSM; val 196 sound/soc/codecs/mc13783.c val |= AUDIO_C_RESET; val 198 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, reg, mask, val); val 247 sound/soc/codecs/mc13783.c unsigned int val = 0; val 261 sound/soc/codecs/mc13783.c val |= AUDIO_CLK_SEL; val 263 sound/soc/codecs/mc13783.c val |= AUDIO_CLK(clk); val 265 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, reg, mask, val); val 299 sound/soc/codecs/mc13783.c unsigned int val = 0; val 305 sound/soc/codecs/mc13783.c val |= SSI_NETWORK_DAC_SLOTS_2; val 308 sound/soc/codecs/mc13783.c val |= SSI_NETWORK_DAC_SLOTS_4; val 311 sound/soc/codecs/mc13783.c val |= SSI_NETWORK_DAC_SLOTS_8; val 319 sound/soc/codecs/mc13783.c val |= SSI_NETWORK_DAC_RXSLOT_0_1; val 322 sound/soc/codecs/mc13783.c val |= SSI_NETWORK_DAC_RXSLOT_2_3; val 325 sound/soc/codecs/mc13783.c val |= SSI_NETWORK_DAC_RXSLOT_4_5; val 328 sound/soc/codecs/mc13783.c val |= SSI_NETWORK_DAC_RXSLOT_6_7; val 334 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, MC13783_SSI_NETWORK, mask, val); val 344 sound/soc/codecs/mc13783.c unsigned int val = 0; val 353 sound/soc/codecs/mc13783.c val |= (0x00 << 2); /* primary timeslot RX/TX(?) is 0 */ val 354 sound/soc/codecs/mc13783.c val |= (0x01 << 4); /* secondary timeslot TX is 1 */ val 356 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, MC13783_SSI_NETWORK, mask, val); val 967 sound/soc/codecs/msm8916-wcd-analog.c u32 val = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1); val 970 sound/soc/codecs/msm8916-wcd-analog.c if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK)) val 566 sound/soc/codecs/nau8540.c fll_param->clk_ref_div = fll_pre_scalar[i].val; val 575 sound/soc/codecs/nau8540.c fll_param->ratio = fll_ratio[i].val; val 594 sound/soc/codecs/nau8540.c fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; val 229 sound/soc/codecs/nau8540.h unsigned int val; val 171 sound/soc/codecs/nau8810.c u16 *val; val 173 sound/soc/codecs/nau8810.c val = (u16 *)ucontrol->value.bytes.data; val 181 sound/soc/codecs/nau8810.c memcpy(val + i, ®_val, sizeof(reg_val)); val 202 sound/soc/codecs/nau8810.c u16 *val, value; val 210 sound/soc/codecs/nau8810.c val = (u16 *)data; val 216 sound/soc/codecs/nau8810.c value = be16_to_cpu(*(val + i)); val 186 sound/soc/codecs/nau8822.c u16 reg_val, *val; val 188 sound/soc/codecs/nau8822.c val = (u16 *)ucontrol->value.bytes.data; val 196 sound/soc/codecs/nau8822.c memcpy(val + i, ®_val, sizeof(reg_val)); val 217 sound/soc/codecs/nau8822.c u16 *val, value; val 225 sound/soc/codecs/nau8822.c val = (u16 *)data; val 231 sound/soc/codecs/nau8822.c value = be16_to_cpu(*(val + i)); val 1285 sound/soc/codecs/nau8824.c fll_param->clk_ref_div = fll_pre_scalar[i].val; val 1294 sound/soc/codecs/nau8824.c fll_param->ratio = fll_ratio[i].val; val 1313 sound/soc/codecs/nau8824.c fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; val 462 sound/soc/codecs/nau8824.h unsigned int val; val 61 sound/soc/codecs/nau8825.c unsigned int val; val 2002 sound/soc/codecs/nau8825.c fll_param->clk_ref_div = fll_pre_scalar[i].val; val 2011 sound/soc/codecs/nau8825.c fll_param->ratio = fll_ratio[i].val; val 2030 sound/soc/codecs/nau8825.c fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; val 87 sound/soc/codecs/pcm1681.c int i = 0, val = -1, enable = 0; val 92 sound/soc/codecs/pcm1681.c val = i; val 98 sound/soc/codecs/pcm1681.c if (val != -1) { val 100 sound/soc/codecs/pcm1681.c PCM1681_DEEMPH_RATE_MASK, val << 3); val 154 sound/soc/codecs/pcm1681.c int val; val 157 sound/soc/codecs/pcm1681.c val = PCM1681_SOFT_MUTE_ALL; val 159 sound/soc/codecs/pcm1681.c val = 0; val 161 sound/soc/codecs/pcm1681.c return regmap_write(priv->regmap, PCM1681_SOFT_MUTE, val); val 170 sound/soc/codecs/pcm1681.c int val = 0, ret; val 178 sound/soc/codecs/pcm1681.c val = 0; val 181 sound/soc/codecs/pcm1681.c val = 3; val 188 sound/soc/codecs/pcm1681.c val = 0x04; val 191 sound/soc/codecs/pcm1681.c val = 0x05; val 198 sound/soc/codecs/pcm1681.c ret = regmap_update_bits(priv->regmap, PCM1681_FMT_CONTROL, 0x0f, val); val 79 sound/soc/codecs/pcm1789.c int val = 0, ret; val 87 sound/soc/codecs/pcm1789.c val = 2; val 90 sound/soc/codecs/pcm1789.c val = 3; val 101 sound/soc/codecs/pcm1789.c val = 0; val 112 sound/soc/codecs/pcm1789.c val = 1; val 124 sound/soc/codecs/pcm1789.c PCM1789_FMT_MASK, val); val 99 sound/soc/codecs/pcm179x.c int val = 0, ret; val 108 sound/soc/codecs/pcm179x.c val = 2; val 111 sound/soc/codecs/pcm179x.c val = 0; val 121 sound/soc/codecs/pcm179x.c val = 5; val 124 sound/soc/codecs/pcm179x.c val = 4; val 135 sound/soc/codecs/pcm179x.c val = val << PCM179X_FMT_SHIFT | PCM179X_ATLD_ENABLE; val 138 sound/soc/codecs/pcm179x.c PCM179X_FMT_MASK | PCM179X_ATLD_ENABLE, val); val 22 sound/soc/codecs/pcm3060.c unsigned int val; val 31 sound/soc/codecs/pcm3060.c val = 0; val 35 sound/soc/codecs/pcm3060.c val = (dai->id == PCM3060_DAI_ID_DAC ? PCM3060_REG_CSEL : 0); val 39 sound/soc/codecs/pcm3060.c val = (dai->id == PCM3060_DAI_ID_DAC ? 0 : PCM3060_REG_CSEL); val 52 sound/soc/codecs/pcm3060.c regmap_update_bits(priv->regmap, reg, PCM3060_REG_CSEL, val); val 64 sound/soc/codecs/pcm3060.c unsigned int val; val 85 sound/soc/codecs/pcm3060.c val = PCM3060_REG_FMT_I2S; val 88 sound/soc/codecs/pcm3060.c val = PCM3060_REG_FMT_RJ; val 91 sound/soc/codecs/pcm3060.c val = PCM3060_REG_FMT_LJ; val 103 sound/soc/codecs/pcm3060.c regmap_update_bits(priv->regmap, reg, PCM3060_REG_MASK_FMT, val); val 117 sound/soc/codecs/pcm3060.c unsigned int val; val 120 sound/soc/codecs/pcm3060.c val = PCM3060_REG_MS_S; val 134 sound/soc/codecs/pcm3060.c val = PCM3060_REG_MS_M768; val 137 sound/soc/codecs/pcm3060.c val = PCM3060_REG_MS_M512; val 140 sound/soc/codecs/pcm3060.c val = PCM3060_REG_MS_M384; val 143 sound/soc/codecs/pcm3060.c val = PCM3060_REG_MS_M256; val 146 sound/soc/codecs/pcm3060.c val = PCM3060_REG_MS_M192; val 149 sound/soc/codecs/pcm3060.c val = PCM3060_REG_MS_M128; val 162 sound/soc/codecs/pcm3060.c regmap_update_bits(priv->regmap, reg, PCM3060_REG_MASK_MS, val); val 423 sound/soc/codecs/pcm3168a.c u32 val, mask, shift, reg; val 514 sound/soc/codecs/pcm3168a.c val = ((i + 1) << shift); val 516 sound/soc/codecs/pcm3168a.c val = 0; val 518 sound/soc/codecs/pcm3168a.c regmap_update_bits(pcm3168a->regmap, reg, mask, val); val 1595 sound/soc/codecs/pcm512x.c u32 val; val 1597 sound/soc/codecs/pcm512x.c if (of_property_read_u32(np, "pll-in", &val) >= 0) { val 1598 sound/soc/codecs/pcm512x.c if (val > 6) { val 1603 sound/soc/codecs/pcm512x.c pcm512x->pll_in = val; val 1606 sound/soc/codecs/pcm512x.c if (of_property_read_u32(np, "pll-out", &val) >= 0) { val 1607 sound/soc/codecs/pcm512x.c if (val > 6) { val 1612 sound/soc/codecs/pcm512x.c pcm512x->pll_out = val; val 69 sound/soc/codecs/rk3328_codec.c unsigned int val; val 73 sound/soc/codecs/rk3328_codec.c val = PIN_DIRECTION_IN | DAC_I2S_MODE_SLAVE; val 76 sound/soc/codecs/rk3328_codec.c val = PIN_DIRECTION_OUT | DAC_I2S_MODE_MASTER; val 83 sound/soc/codecs/rk3328_codec.c PIN_DIRECTION_MASK | DAC_I2S_MODE_MASK, val); val 88 sound/soc/codecs/rk3328_codec.c val = DAC_MODE_PCM; val 91 sound/soc/codecs/rk3328_codec.c val = DAC_MODE_I2S; val 94 sound/soc/codecs/rk3328_codec.c val = DAC_MODE_RJM; val 97 sound/soc/codecs/rk3328_codec.c val = DAC_MODE_LJM; val 104 sound/soc/codecs/rk3328_codec.c DAC_MODE_MASK, val); val 111 sound/soc/codecs/rk3328_codec.c unsigned int val = BIT(17); val 114 sound/soc/codecs/rk3328_codec.c val |= BIT(1); val 116 sound/soc/codecs/rk3328_codec.c regmap_write(rk3328->grf, RK3328_GRF_SOC_CON10, val); val 123 sound/soc/codecs/rk3328_codec.c unsigned int val; val 126 sound/soc/codecs/rk3328_codec.c val = HPOUTL_MUTE | HPOUTR_MUTE; val 128 sound/soc/codecs/rk3328_codec.c val = HPOUTL_UNMUTE | HPOUTR_UNMUTE; val 131 sound/soc/codecs/rk3328_codec.c HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK, val); val 203 sound/soc/codecs/rk3328_codec.c playback_open_list[i].val); val 260 sound/soc/codecs/rk3328_codec.c playback_close_list[i].val); val 280 sound/soc/codecs/rk3328_codec.c unsigned int val = 0; val 284 sound/soc/codecs/rk3328_codec.c val = DAC_VDL_16BITS; val 287 sound/soc/codecs/rk3328_codec.c val = DAC_VDL_20BITS; val 290 sound/soc/codecs/rk3328_codec.c val = DAC_VDL_24BITS; val 293 sound/soc/codecs/rk3328_codec.c val = DAC_VDL_32BITS; val 298 sound/soc/codecs/rk3328_codec.c regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL2, DAC_VDL_MASK, val); val 300 sound/soc/codecs/rk3328_codec.c val = DAC_WL_32BITS | DAC_RST_DIS; val 302 sound/soc/codecs/rk3328_codec.c DAC_WL_MASK | DAC_RST_MASK, val); val 207 sound/soc/codecs/rk3328_codec.h unsigned int val; val 28 sound/soc/codecs/rl6231.c int pd, val; val 30 sound/soc/codecs/rl6231.c regmap_read(map, reg, &val); val 32 sound/soc/codecs/rl6231.c val = (val >> sft) & 0x7; val 34 sound/soc/codecs/rl6231.c switch (val) { val 39 sound/soc/codecs/rl6231.c pd = val + 1; val 1148 sound/soc/codecs/rt1011.c params[i].val = bq_drc_info[i].val; val 1190 sound/soc/codecs/rt1011.c bq_drc_info[i].val = params[i].val; val 1198 sound/soc/codecs/rt1011.c bq_drc_info[i].val); val 1808 sound/soc/codecs/rt1011.c unsigned int val = 0, tdm_en = 0; val 1817 sound/soc/codecs/rt1011.c val |= RT1011_I2S_TX_4CH; val 1818 sound/soc/codecs/rt1011.c val |= RT1011_I2S_RX_4CH; val 1821 sound/soc/codecs/rt1011.c val |= RT1011_I2S_TX_6CH; val 1822 sound/soc/codecs/rt1011.c val |= RT1011_I2S_RX_6CH; val 1825 sound/soc/codecs/rt1011.c val |= RT1011_I2S_TX_8CH; val 1826 sound/soc/codecs/rt1011.c val |= RT1011_I2S_RX_8CH; val 1836 sound/soc/codecs/rt1011.c val |= RT1011_I2S_CH_TX_LEN_20B; val 1837 sound/soc/codecs/rt1011.c val |= RT1011_I2S_CH_RX_LEN_20B; val 1840 sound/soc/codecs/rt1011.c val |= RT1011_I2S_CH_TX_LEN_24B; val 1841 sound/soc/codecs/rt1011.c val |= RT1011_I2S_CH_RX_LEN_24B; val 1844 sound/soc/codecs/rt1011.c val |= RT1011_I2S_CH_TX_LEN_32B; val 1845 sound/soc/codecs/rt1011.c val |= RT1011_I2S_CH_RX_LEN_32B; val 1855 sound/soc/codecs/rt1011.c RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val); val 1858 sound/soc/codecs/rt1011.c RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val); val 2218 sound/soc/codecs/rt1011.c unsigned int val; val 2235 sound/soc/codecs/rt1011.c regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val); val 2236 sound/soc/codecs/rt1011.c if (val != RT1011_DEVICE_ID_NUM) { val 2238 sound/soc/codecs/rt1011.c "Device with ID register %x is not rt1011\n", val); val 637 sound/soc/codecs/rt1011.h unsigned short val; val 412 sound/soc/codecs/rt1305.c unsigned int val; val 414 sound/soc/codecs/rt1305.c snd_soc_component_read(component, RT1305_CLK_1, &val); val 417 sound/soc/codecs/rt1305.c (val & RT1305_SEL_PLL_SRC_2_RCCLK)) val 1125 sound/soc/codecs/rt1305.c unsigned int val; val 1142 sound/soc/codecs/rt1305.c regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val); val 1143 sound/soc/codecs/rt1305.c if (val != RT1305_DEVICE_ID_NUM) { val 1145 sound/soc/codecs/rt1305.c "Device with ID register %x is not rt1305\n", val); val 822 sound/soc/codecs/rt1308.c unsigned int val; val 839 sound/soc/codecs/rt1308.c regmap_read(rt1308->regmap, RT1308_VEN_DEV_ID, &val); val 841 sound/soc/codecs/rt1308.c if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) { val 843 sound/soc/codecs/rt1308.c "Device with ID register %x is not rt1308\n", val); val 619 sound/soc/codecs/rt274.c unsigned int val = 0; val 653 sound/soc/codecs/rt274.c val |= (params_channels(params) - 1); val 665 sound/soc/codecs/rt274.c val |= (0x1 << 4); val 670 sound/soc/codecs/rt274.c val |= (0x4 << 4); val 675 sound/soc/codecs/rt274.c val |= (0x2 << 4); val 680 sound/soc/codecs/rt274.c val |= (0x3 << 4); val 695 sound/soc/codecs/rt274.c dev_dbg(component->dev, "format val = 0x%x\n", val); val 697 sound/soc/codecs/rt274.c snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x407f, val); val 698 sound/soc/codecs/rt274.c snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x407f, val); val 1121 sound/soc/codecs/rt274.c unsigned int val; val 1137 sound/soc/codecs/rt274.c RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val); val 1141 sound/soc/codecs/rt274.c if (val != RT274_VENDOR_ID) { val 1143 sound/soc/codecs/rt274.c "Device with ID register %#x is not rt274\n", val); val 215 sound/soc/codecs/rt286.c unsigned int val, buf; val 245 sound/soc/codecs/rt286.c regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val); val 247 sound/soc/codecs/rt286.c if (0x0070 == (val & 0x0070)) { val 254 sound/soc/codecs/rt286.c RT286_CBJ_CTRL2, &val); val 255 sound/soc/codecs/rt286.c if (0x0070 == (val & 0x0070)) val 677 sound/soc/codecs/rt286.c unsigned int val = 0; val 683 sound/soc/codecs/rt286.c val |= 0x4000; val 713 sound/soc/codecs/rt286.c val |= (params_channels(params) - 1); val 725 sound/soc/codecs/rt286.c val |= (0x1 << 4); val 729 sound/soc/codecs/rt286.c val |= (0x4 << 4); val 733 sound/soc/codecs/rt286.c val |= (0x2 << 4); val 737 sound/soc/codecs/rt286.c val |= (0x3 << 4); val 748 sound/soc/codecs/rt286.c dev_dbg(component->dev, "format val = 0x%x\n", val); val 750 sound/soc/codecs/rt286.c snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x407f, val); val 751 sound/soc/codecs/rt286.c snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x407f, val); val 1134 sound/soc/codecs/rt286.c int i, ret, val; val 1150 sound/soc/codecs/rt286.c RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val); val 1155 sound/soc/codecs/rt286.c if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) { val 1157 sound/soc/codecs/rt286.c "Device with ID register %#x is not rt286\n", val); val 222 sound/soc/codecs/rt298.c unsigned int val, buf; val 260 sound/soc/codecs/rt298.c regmap_read(rt298->regmap, RT298_CBJ_CTRL2, &val); val 262 sound/soc/codecs/rt298.c if (0x0070 == (val & 0x0070)) { val 269 sound/soc/codecs/rt298.c RT298_CBJ_CTRL2, &val); val 270 sound/soc/codecs/rt298.c if (0x0070 == (val & 0x0070)) val 748 sound/soc/codecs/rt298.c unsigned int val = 0; val 782 sound/soc/codecs/rt298.c val |= (params_channels(params) - 1); val 794 sound/soc/codecs/rt298.c val |= (0x1 << 4); val 798 sound/soc/codecs/rt298.c val |= (0x4 << 4); val 802 sound/soc/codecs/rt298.c val |= (0x2 << 4); val 806 sound/soc/codecs/rt298.c val |= (0x3 << 4); val 817 sound/soc/codecs/rt298.c dev_dbg(component->dev, "format val = 0x%x\n", val); val 819 sound/soc/codecs/rt298.c snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x407f, val); val 820 sound/soc/codecs/rt298.c snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x407f, val); val 966 sound/soc/codecs/rt5514.c unsigned int val = 0, val2 = 0; val 969 sound/soc/codecs/rt5514.c val |= RT5514_TDM_MODE; val 1000 sound/soc/codecs/rt5514.c val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH; val 1004 sound/soc/codecs/rt5514.c val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH; val 1008 sound/soc/codecs/rt5514.c val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH; val 1018 sound/soc/codecs/rt5514.c val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20; val 1022 sound/soc/codecs/rt5514.c val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24; val 1026 sound/soc/codecs/rt5514.c val |= RT5514_TDM_MODE2; val 1030 sound/soc/codecs/rt5514.c val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32; val 1041 sound/soc/codecs/rt5514.c RT5514_TDM_MODE2, val); val 1118 sound/soc/codecs/rt5514.c static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val) val 1123 sound/soc/codecs/rt5514.c regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val); val 1128 sound/soc/codecs/rt5514.c static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val) val 1133 sound/soc/codecs/rt5514.c regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val); val 1243 sound/soc/codecs/rt5514.c unsigned int val; val 1250 sound/soc/codecs/rt5514.c regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); val 1261 sound/soc/codecs/rt5514.c unsigned int val = ~0; val 1297 sound/soc/codecs/rt5514.c ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); val 1298 sound/soc/codecs/rt5514.c if (ret || val != RT5514_DEVICE_ID) val 1299 sound/soc/codecs/rt5514.c ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val); val 1300 sound/soc/codecs/rt5514.c if (ret || val != RT5514_DEVICE_ID) { val 1302 sound/soc/codecs/rt5514.c "Device with ID register %x is not rt5514\n", val); val 349 sound/soc/codecs/rt5616.c unsigned int val; val 351 sound/soc/codecs/rt5616.c val = snd_soc_component_read32(snd_soc_dapm_to_component(source->dapm), RT5616_GLB_CLK); val 352 sound/soc/codecs/rt5616.c val &= RT5616_SCLK_SRC_MASK; val 353 sound/soc/codecs/rt5616.c if (val == RT5616_SCLK_SRC_PLL1) val 1344 sound/soc/codecs/rt5616.c unsigned int val; val 1362 sound/soc/codecs/rt5616.c regmap_read(rt5616->regmap, RT5616_DEVICE_ID, &val); val 1363 sound/soc/codecs/rt5616.c if (val != 0x6281) { val 1366 sound/soc/codecs/rt5616.c val); val 1574 sound/soc/codecs/rt5631.c unsigned int val; val 1576 sound/soc/codecs/rt5631.c val = rt5631_read_index(component, RT5631_ADDA_MIXER_INTL_REG3); val 1577 sound/soc/codecs/rt5631.c if (val & 0x0002) val 1649 sound/soc/codecs/rt5640.c int ret = 0, val; val 1654 sound/soc/codecs/rt5640.c val = snd_soc_component_read32(component, RT5640_I2S1_SDP); val 1655 sound/soc/codecs/rt5640.c val = (val & RT5640_I2S_IF_MASK) >> RT5640_I2S_IF_SFT; val 1658 sound/soc/codecs/rt5640.c switch (val) { val 1674 sound/soc/codecs/rt5640.c switch (val) { val 2147 sound/soc/codecs/rt5640.c int val; val 2149 sound/soc/codecs/rt5640.c val = snd_soc_component_read32(component, RT5640_IRQ_CTRL2); val 2150 sound/soc/codecs/rt5640.c dev_dbg(component->dev, "irq ctrl2 %#04x\n", val); val 2152 sound/soc/codecs/rt5640.c return (val & RT5640_MB1_OC_STATUS); val 2158 sound/soc/codecs/rt5640.c int val; val 2160 sound/soc/codecs/rt5640.c val = snd_soc_component_read32(component, RT5640_INT_IRQ_ST); val 2161 sound/soc/codecs/rt5640.c dev_dbg(component->dev, "irq status %#04x\n", val); val 2164 sound/soc/codecs/rt5640.c return !(val & RT5640_JD_STATUS); val 2166 sound/soc/codecs/rt5640.c return (val & RT5640_JD_STATUS); val 2472 sound/soc/codecs/rt5640.c u32 val; val 2534 sound/soc/codecs/rt5640.c &val) == 0 && val) { val 2535 sound/soc/codecs/rt5640.c dmic1_data_pin = val - 1; val 2540 sound/soc/codecs/rt5640.c &val) == 0 && val) { val 2541 sound/soc/codecs/rt5640.c dmic2_data_pin = val - 1; val 2549 sound/soc/codecs/rt5640.c "realtek,jack-detect-source", &val) == 0) { val 2550 sound/soc/codecs/rt5640.c if (val <= RT5640_JD_SRC_GPIO4) val 2551 sound/soc/codecs/rt5640.c rt5640->jd_src = val << RT5640_JD_SFT; val 2554 sound/soc/codecs/rt5640.c val); val 2569 sound/soc/codecs/rt5640.c "realtek,over-current-threshold-microamp", &val) == 0) { val 2570 sound/soc/codecs/rt5640.c switch (val) { val 2582 sound/soc/codecs/rt5640.c val); val 2587 sound/soc/codecs/rt5640.c "realtek,over-current-scale-factor", &val) == 0) { val 2588 sound/soc/codecs/rt5640.c if (val <= RT5640_OVCD_SF_1P5) val 2589 sound/soc/codecs/rt5640.c rt5640->ovcd_sf = val << RT5640_MIC_OVCD_SF_SFT; val 2592 sound/soc/codecs/rt5640.c val); val 2776 sound/soc/codecs/rt5640.c unsigned int val; val 2812 sound/soc/codecs/rt5640.c regmap_read(rt5640->regmap, RT5640_VENDOR_ID2, &val); val 2813 sound/soc/codecs/rt5640.c if (val != RT5640_DEVICE_ID) { val 2815 sound/soc/codecs/rt5640.c "Device with ID register %#x is not rt5640/39\n", val); val 398 sound/soc/codecs/rt5645.c unsigned short val; val 403 sound/soc/codecs/rt5645.c __be16 val; val 683 sound/soc/codecs/rt5645.c eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); val 709 sound/soc/codecs/rt5645.c rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val); val 867 sound/soc/codecs/rt5645.c unsigned int val; val 869 sound/soc/codecs/rt5645.c val = snd_soc_component_read32(component, RT5645_GLB_CLK); val 870 sound/soc/codecs/rt5645.c val &= RT5645_SCLK_SRC_MASK; val 871 sound/soc/codecs/rt5645.c if (val == RT5645_SCLK_SRC_PLL1) val 881 sound/soc/codecs/rt5645.c unsigned int reg, shift, val; val 912 sound/soc/codecs/rt5645.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; val 913 sound/soc/codecs/rt5645.c switch (val) { val 933 sound/soc/codecs/rt5645.c rt5645->eq_param[i].val); val 2989 sound/soc/codecs/rt5645.c unsigned int mask, val = 0; val 3008 sound/soc/codecs/rt5645.c val |= (1 << en_sft); val 3016 sound/soc/codecs/rt5645.c val |= (1 << i_slot_sft) | (1 << o_slot_sft); val 3019 sound/soc/codecs/rt5645.c val |= (2 << i_slot_sft) | (2 << o_slot_sft); val 3022 sound/soc/codecs/rt5645.c val |= (3 << i_slot_sft) | (3 << o_slot_sft); val 3031 sound/soc/codecs/rt5645.c val |= (1 << i_width_sht) | (1 << o_width_sht); val 3034 sound/soc/codecs/rt5645.c val |= (2 << i_width_sht) | (2 << o_width_sht); val 3037 sound/soc/codecs/rt5645.c val |= (3 << i_width_sht) | (3 << o_width_sht); val 3044 sound/soc/codecs/rt5645.c snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val); val 3141 sound/soc/codecs/rt5645.c unsigned int val; val 3172 sound/soc/codecs/rt5645.c regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); val 3173 sound/soc/codecs/rt5645.c val &= 0x7; val 3174 sound/soc/codecs/rt5645.c dev_dbg(component->dev, "val = %d\n", val); val 3176 sound/soc/codecs/rt5645.c if (val == 1 || val == 2) { val 3217 sound/soc/codecs/rt5645.c int btn_type, val; val 3219 sound/soc/codecs/rt5645.c val = snd_soc_component_read32(component, RT5650_4BTN_IL_CMD1); val 3220 sound/soc/codecs/rt5645.c pr_debug("val=0x%x\n", val); val 3221 sound/soc/codecs/rt5645.c btn_type = val & 0xfff0; val 3222 sound/soc/codecs/rt5645.c snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val); val 3255 sound/soc/codecs/rt5645.c int val, btn_type, gpio_state = 0, report = 0; val 3274 sound/soc/codecs/rt5645.c val = snd_soc_component_read32(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020; val 3277 sound/soc/codecs/rt5645.c val = snd_soc_component_read32(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000; val 3282 sound/soc/codecs/rt5645.c if (!val && (rt5645->jack_type == 0)) { /* jack in */ val 3284 sound/soc/codecs/rt5645.c } else if (!val && rt5645->jack_type != 0) { val 3783 sound/soc/codecs/rt5645.c unsigned int val; val 3861 sound/soc/codecs/rt5645.c regmap_read(regmap, RT5645_VENDOR_ID2, &val); val 3863 sound/soc/codecs/rt5645.c switch (val) { val 3875 sound/soc/codecs/rt5645.c val); val 3889 sound/soc/codecs/rt5645.c regmap_read(regmap, RT5645_VENDOR_ID, &val); val 3890 sound/soc/codecs/rt5645.c rt5645->v_id = val & 0xff; val 1609 sound/soc/codecs/rt5651.c int val; val 1611 sound/soc/codecs/rt5651.c val = snd_soc_component_read32(component, RT5651_IRQ_CTRL2); val 1612 sound/soc/codecs/rt5651.c dev_dbg(component->dev, "irq ctrl2 %#04x\n", val); val 1614 sound/soc/codecs/rt5651.c return (val & RT5651_MB1_OC_CLR); val 1620 sound/soc/codecs/rt5651.c int val; val 1623 sound/soc/codecs/rt5651.c val = gpiod_get_value_cansleep(rt5651->gpiod_hp_det); val 1624 sound/soc/codecs/rt5651.c dev_dbg(component->dev, "jack-detect gpio %d\n", val); val 1625 sound/soc/codecs/rt5651.c return val; val 1628 sound/soc/codecs/rt5651.c val = snd_soc_component_read32(component, RT5651_INT_IRQ_ST); val 1629 sound/soc/codecs/rt5651.c dev_dbg(component->dev, "irq status %#04x\n", val); val 1633 sound/soc/codecs/rt5651.c val &= 0x1000; val 1636 sound/soc/codecs/rt5651.c val &= 0x2000; val 1639 sound/soc/codecs/rt5651.c val &= 0x4000; val 1646 sound/soc/codecs/rt5651.c return val != 0; val 1648 sound/soc/codecs/rt5651.c return val == 0; val 2005 sound/soc/codecs/rt5651.c u32 val; val 2016 sound/soc/codecs/rt5651.c "realtek,jack-detect-source", &val) == 0) val 2017 sound/soc/codecs/rt5651.c rt5651->jd_src = val; val 2031 sound/soc/codecs/rt5651.c "realtek,over-current-threshold-microamp", &val) == 0) { val 2032 sound/soc/codecs/rt5651.c switch (val) { val 2044 sound/soc/codecs/rt5651.c val); val 2049 sound/soc/codecs/rt5651.c "realtek,over-current-scale-factor", &val) == 0) { val 2050 sound/soc/codecs/rt5651.c if (val <= RT5651_OVCD_SF_1P5) val 2051 sound/soc/codecs/rt5651.c rt5651->ovcd_sf = val << RT5651_MIC_OVCD_SF_SFT; val 2054 sound/soc/codecs/rt5651.c val); val 1299 sound/soc/codecs/rt5659.c int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; val 1326 sound/soc/codecs/rt5659.c val = snd_soc_component_read32(component, RT5659_EJD_CTRL_2) & 0x0003; val 1328 sound/soc/codecs/rt5659.c if (val == 0x1 || val == 0x2 || val == 0x3) val 1332 sound/soc/codecs/rt5659.c switch (val) { val 1358 sound/soc/codecs/rt5659.c int btn_type, val; val 1360 sound/soc/codecs/rt5659.c val = snd_soc_component_read32(component, RT5659_4BTN_IL_CMD_1); val 1361 sound/soc/codecs/rt5659.c btn_type = val & 0xfff0; val 1362 sound/soc/codecs/rt5659.c snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, val); val 1394 sound/soc/codecs/rt5659.c int val, btn_type, report = 0; val 1399 sound/soc/codecs/rt5659.c val = snd_soc_component_read32(rt5659->component, RT5659_INT_ST_1) & 0x0080; val 1400 sound/soc/codecs/rt5659.c if (!val) { val 1696 sound/soc/codecs/rt5659.c unsigned int val; val 1699 sound/soc/codecs/rt5659.c val = snd_soc_component_read32(component, RT5659_GLB_CLK); val 1700 sound/soc/codecs/rt5659.c val &= RT5659_SCLK_SRC_MASK; val 1701 sound/soc/codecs/rt5659.c if (val == RT5659_SCLK_SRC_PLL1) val 1710 sound/soc/codecs/rt5659.c unsigned int reg, shift, val; val 1742 sound/soc/codecs/rt5659.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; val 1743 sound/soc/codecs/rt5659.c switch (val) { val 3566 sound/soc/codecs/rt5659.c unsigned int val = 0; val 3569 sound/soc/codecs/rt5659.c val |= (1 << 15); val 3573 sound/soc/codecs/rt5659.c val |= (1 << 10); val 3574 sound/soc/codecs/rt5659.c val |= (1 << 8); val 3577 sound/soc/codecs/rt5659.c val |= (2 << 10); val 3578 sound/soc/codecs/rt5659.c val |= (2 << 8); val 3581 sound/soc/codecs/rt5659.c val |= (3 << 10); val 3582 sound/soc/codecs/rt5659.c val |= (3 << 8); val 3592 sound/soc/codecs/rt5659.c val |= (1 << 6); val 3593 sound/soc/codecs/rt5659.c val |= (1 << 4); val 3596 sound/soc/codecs/rt5659.c val |= (2 << 6); val 3597 sound/soc/codecs/rt5659.c val |= (2 << 4); val 3600 sound/soc/codecs/rt5659.c val |= (3 << 6); val 3601 sound/soc/codecs/rt5659.c val |= (3 << 4); val 3609 sound/soc/codecs/rt5659.c snd_soc_component_update_bits(component, RT5659_TDM_CTRL_1, 0x8ff0, val); val 4118 sound/soc/codecs/rt5659.c unsigned int val; val 4152 sound/soc/codecs/rt5659.c regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val); val 4153 sound/soc/codecs/rt5659.c if (val != DEVICE_ID) { val 4155 sound/soc/codecs/rt5659.c "Device with ID register %x is not rt5659\n", val); val 374 sound/soc/codecs/rt5660.c unsigned int val; val 376 sound/soc/codecs/rt5660.c val = snd_soc_component_read32(component, RT5660_GLB_CLK); val 377 sound/soc/codecs/rt5660.c val &= RT5660_SCLK_SRC_MASK; val 378 sound/soc/codecs/rt5660.c if (val == RT5660_SCLK_SRC_PLL1) val 1271 sound/soc/codecs/rt5660.c unsigned int val; val 1299 sound/soc/codecs/rt5660.c regmap_read(rt5660->regmap, RT5660_VENDOR_ID2, &val); val 1300 sound/soc/codecs/rt5660.c if (val != RT5660_DEVICE_ID) { val 1302 sound/soc/codecs/rt5660.c "Device with ID register %#x is not rt5660\n", val); val 1467 sound/soc/codecs/rt5663.c int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; val 1485 sound/soc/codecs/rt5663.c val = snd_soc_component_read32(component, RT5663_CBJ_TYPE_2) & 0x0003; val 1486 sound/soc/codecs/rt5663.c if (val == 0x1 || val == 0x2 || val == 0x3) val 1489 sound/soc/codecs/rt5663.c __func__, val, sleep_time[i]); val 1492 sound/soc/codecs/rt5663.c dev_dbg(component->dev, "%s val = %d\n", __func__, val); val 1493 sound/soc/codecs/rt5663.c switch (val) { val 1538 sound/soc/codecs/rt5663.c int val, i = 0; val 1587 sound/soc/codecs/rt5663.c regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val); val 1588 sound/soc/codecs/rt5663.c if (!(val & 0x80)) val 1598 sound/soc/codecs/rt5663.c val = snd_soc_component_read32(component, RT5663_EM_JACK_TYPE_2) & 0x0003; val 1599 sound/soc/codecs/rt5663.c dev_dbg(component->dev, "%s val = %d\n", __func__, val); val 1605 sound/soc/codecs/rt5663.c switch (val) { val 1844 sound/soc/codecs/rt5663.c int btn_type, val; val 1846 sound/soc/codecs/rt5663.c val = snd_soc_component_read32(component, RT5663_IL_CMD_5); val 1847 sound/soc/codecs/rt5663.c dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val); val 1848 sound/soc/codecs/rt5663.c btn_type = val & 0xfff0; val 1849 sound/soc/codecs/rt5663.c snd_soc_component_write(component, RT5663_IL_CMD_5, val); val 1882 sound/soc/codecs/rt5663.c int val = snd_soc_component_read32(component, RT5663_INT_ST_1); val 1884 sound/soc/codecs/rt5663.c dev_dbg(component->dev, "%s val=%x\n", __func__, val); val 1889 sound/soc/codecs/rt5663.c return !(val & 0x2000); val 1891 sound/soc/codecs/rt5663.c return !(val & 0x1000); val 2072 sound/soc/codecs/rt5663.c unsigned int val; val 2075 sound/soc/codecs/rt5663.c val = snd_soc_component_read32(component, RT5663_GLB_CLK); val 2076 sound/soc/codecs/rt5663.c val &= RT5663_SCLK_SRC_MASK; val 2077 sound/soc/codecs/rt5663.c if (val == RT5663_SCLK_SRC_PLL1) val 2086 sound/soc/codecs/rt5663.c unsigned int reg, shift, val; val 2118 sound/soc/codecs/rt5663.c val = (snd_soc_component_read32(component, reg) >> shift) & 0x7; val 2120 sound/soc/codecs/rt5663.c if (val) val 2899 sound/soc/codecs/rt5663.c int mask, shift, val; val 2931 sound/soc/codecs/rt5663.c val = 0x0; val 2934 sound/soc/codecs/rt5663.c val = 0x1; val 2940 sound/soc/codecs/rt5663.c snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift)); val 2970 sound/soc/codecs/rt5663.c unsigned int val = 0, reg; val 2973 sound/soc/codecs/rt5663.c val |= RT5663_TDM_MODE_TDM; val 2977 sound/soc/codecs/rt5663.c val |= RT5663_TDM_IN_CH_4; val 2978 sound/soc/codecs/rt5663.c val |= RT5663_TDM_OUT_CH_4; val 2981 sound/soc/codecs/rt5663.c val |= RT5663_TDM_IN_CH_6; val 2982 sound/soc/codecs/rt5663.c val |= RT5663_TDM_OUT_CH_6; val 2985 sound/soc/codecs/rt5663.c val |= RT5663_TDM_IN_CH_8; val 2986 sound/soc/codecs/rt5663.c val |= RT5663_TDM_OUT_CH_8; val 2996 sound/soc/codecs/rt5663.c val |= RT5663_TDM_IN_LEN_20; val 2997 sound/soc/codecs/rt5663.c val |= RT5663_TDM_OUT_LEN_20; val 3000 sound/soc/codecs/rt5663.c val |= RT5663_TDM_IN_LEN_24; val 3001 sound/soc/codecs/rt5663.c val |= RT5663_TDM_OUT_LEN_24; val 3004 sound/soc/codecs/rt5663.c val |= RT5663_TDM_IN_LEN_32; val 3005 sound/soc/codecs/rt5663.c val |= RT5663_TDM_OUT_LEN_32; val 3027 sound/soc/codecs/rt5663.c RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val); val 3494 sound/soc/codecs/rt5663.c unsigned int val; val 3550 sound/soc/codecs/rt5663.c ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val); val 3551 sound/soc/codecs/rt5663.c if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) { val 3554 sound/soc/codecs/rt5663.c val); val 3556 sound/soc/codecs/rt5663.c regmap_read(regmap, RT5663_VENDOR_ID_2, &val); val 3559 sound/soc/codecs/rt5663.c switch (val) { val 3571 sound/soc/codecs/rt5663.c val); val 1127 sound/soc/codecs/rt5665.c int btn_type, val; val 1129 sound/soc/codecs/rt5665.c val = snd_soc_component_read32(component, RT5665_4BTN_IL_CMD_1); val 1130 sound/soc/codecs/rt5665.c btn_type = val & 0xfff0; val 1131 sound/soc/codecs/rt5665.c snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val); val 1171 sound/soc/codecs/rt5665.c unsigned int sar_hs_type, val; val 1180 sound/soc/codecs/rt5665.c regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); val 1181 sound/soc/codecs/rt5665.c if (val & 0x4) { val 1185 sound/soc/codecs/rt5665.c regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); val 1186 sound/soc/codecs/rt5665.c while (val & 0x4) { val 1189 sound/soc/codecs/rt5665.c &val); val 1294 sound/soc/codecs/rt5665.c int val, btn_type; val 1313 sound/soc/codecs/rt5665.c val = snd_soc_component_read32(rt5665->component, RT5665_AJD1_CTRL) & 0x0010; val 1314 sound/soc/codecs/rt5665.c if (!val) { val 1522 sound/soc/codecs/rt5665.c unsigned int val; val 1525 sound/soc/codecs/rt5665.c val = snd_soc_component_read32(component, RT5665_GLB_CLK); val 1526 sound/soc/codecs/rt5665.c val &= RT5665_SCLK_SRC_MASK; val 1527 sound/soc/codecs/rt5665.c if (val == RT5665_SCLK_SRC_PLL1) val 1536 sound/soc/codecs/rt5665.c unsigned int reg, shift, val; val 1576 sound/soc/codecs/rt5665.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; val 1577 sound/soc/codecs/rt5665.c switch (val) { val 4053 sound/soc/codecs/rt5665.c unsigned int val = 0; val 4056 sound/soc/codecs/rt5665.c val |= RT5665_I2S1_MODE_TDM; val 4060 sound/soc/codecs/rt5665.c val |= RT5665_TDM_IN_CH_4; val 4061 sound/soc/codecs/rt5665.c val |= RT5665_TDM_OUT_CH_4; val 4064 sound/soc/codecs/rt5665.c val |= RT5665_TDM_IN_CH_6; val 4065 sound/soc/codecs/rt5665.c val |= RT5665_TDM_OUT_CH_6; val 4068 sound/soc/codecs/rt5665.c val |= RT5665_TDM_IN_CH_8; val 4069 sound/soc/codecs/rt5665.c val |= RT5665_TDM_OUT_CH_8; val 4079 sound/soc/codecs/rt5665.c val |= RT5665_TDM_IN_LEN_20; val 4080 sound/soc/codecs/rt5665.c val |= RT5665_TDM_OUT_LEN_20; val 4083 sound/soc/codecs/rt5665.c val |= RT5665_TDM_IN_LEN_24; val 4084 sound/soc/codecs/rt5665.c val |= RT5665_TDM_OUT_LEN_24; val 4087 sound/soc/codecs/rt5665.c val |= RT5665_TDM_IN_LEN_32; val 4088 sound/soc/codecs/rt5665.c val |= RT5665_TDM_OUT_LEN_32; val 4099 sound/soc/codecs/rt5665.c RT5665_TDM_OUT_LEN_MASK, val); val 4766 sound/soc/codecs/rt5665.c unsigned int val; val 4815 sound/soc/codecs/rt5665.c regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val); val 4816 sound/soc/codecs/rt5665.c if (val != DEVICE_ID) { val 4818 sound/soc/codecs/rt5665.c "Device with ID register %x is not rt5665\n", val); val 4822 sound/soc/codecs/rt5665.c regmap_read(rt5665->regmap, RT5665_RESET, &val); val 4823 sound/soc/codecs/rt5665.c switch (val) { val 848 sound/soc/codecs/rt5668.c int btn_type, val; val 850 sound/soc/codecs/rt5668.c val = snd_soc_component_read32(component, RT5668_4BTN_IL_CMD_1); val 851 sound/soc/codecs/rt5668.c btn_type = val & 0xfff0; val 852 sound/soc/codecs/rt5668.c snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val); val 901 sound/soc/codecs/rt5668.c unsigned int val, count; val 910 sound/soc/codecs/rt5668.c val = snd_soc_component_read32(component, RT5668_CBJ_CTRL_2) val 912 sound/soc/codecs/rt5668.c while (val == 0 && count < 50) { val 914 sound/soc/codecs/rt5668.c val = snd_soc_component_read32(component, val 919 sound/soc/codecs/rt5668.c switch (val) { val 1023 sound/soc/codecs/rt5668.c int val, btn_type; val 1033 sound/soc/codecs/rt5668.c val = snd_soc_component_read32(rt5668->component, RT5668_AJD1_CTRL) val 1035 sound/soc/codecs/rt5668.c if (!val) { val 1191 sound/soc/codecs/rt5668.c int ref, val, reg, idx = -EINVAL; val 1194 sound/soc/codecs/rt5668.c val = snd_soc_component_read32(component, RT5668_GPIO_CTRL_1) & val 1197 sound/soc/codecs/rt5668.c val == RT5668_GP4_PIN_ADCDAT2) val 1218 sound/soc/codecs/rt5668.c unsigned int val; val 1222 sound/soc/codecs/rt5668.c val = snd_soc_component_read32(component, RT5668_GLB_CLK); val 1223 sound/soc/codecs/rt5668.c val &= RT5668_SCLK_SRC_MASK; val 1224 sound/soc/codecs/rt5668.c if (val == RT5668_SCLK_SRC_PLL1) val 1233 sound/soc/codecs/rt5668.c unsigned int reg, shift, val; val 1250 sound/soc/codecs/rt5668.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; val 1251 sound/soc/codecs/rt5668.c switch (val) { val 1869 sound/soc/codecs/rt5668.c unsigned int val = 0; val 1873 sound/soc/codecs/rt5668.c val |= RT5668_TDM_TX_CH_4; val 1874 sound/soc/codecs/rt5668.c val |= RT5668_TDM_RX_CH_4; val 1877 sound/soc/codecs/rt5668.c val |= RT5668_TDM_TX_CH_6; val 1878 sound/soc/codecs/rt5668.c val |= RT5668_TDM_RX_CH_6; val 1881 sound/soc/codecs/rt5668.c val |= RT5668_TDM_TX_CH_8; val 1882 sound/soc/codecs/rt5668.c val |= RT5668_TDM_RX_CH_8; val 1891 sound/soc/codecs/rt5668.c RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val); val 1895 sound/soc/codecs/rt5668.c val = RT5668_TDM_CL_16; val 1898 sound/soc/codecs/rt5668.c val = RT5668_TDM_CL_20; val 1901 sound/soc/codecs/rt5668.c val = RT5668_TDM_CL_24; val 1904 sound/soc/codecs/rt5668.c val = RT5668_TDM_CL_32; val 1911 sound/soc/codecs/rt5668.c RT5668_TDM_CL_MASK, val); val 2460 sound/soc/codecs/rt5668.c unsigned int val; val 2512 sound/soc/codecs/rt5668.c regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val); val 2513 sound/soc/codecs/rt5668.c if (val != DEVICE_ID) { val 2514 sound/soc/codecs/rt5668.c pr_err("Device with ID register %x is not rt5668\n", val); val 433 sound/soc/codecs/rt5670.c int val; val 455 sound/soc/codecs/rt5670.c val = snd_soc_component_read32(component, RT5670_CJ_CTRL3) & 0x7; val 456 sound/soc/codecs/rt5670.c if (val == 0x1 || val == 0x2) { val 499 sound/soc/codecs/rt5670.c int btn_type, val; val 501 sound/soc/codecs/rt5670.c val = snd_soc_component_read32(component, RT5670_IL_CMD); val 502 sound/soc/codecs/rt5670.c btn_type = val & 0xff80; val 503 sound/soc/codecs/rt5670.c snd_soc_component_write(component, RT5670_IL_CMD, val); val 506 sound/soc/codecs/rt5670.c val = snd_soc_component_read32(component, RT5670_IL_CMD); val 507 sound/soc/codecs/rt5670.c snd_soc_component_write(component, RT5670_IL_CMD, val); val 518 sound/soc/codecs/rt5670.c int val, btn_type, report = jack->status; val 521 sound/soc/codecs/rt5670.c val = snd_soc_component_read32(rt5670->component, RT5670_A_JD_CTRL1) & 0x0070; val 523 sound/soc/codecs/rt5670.c val = snd_soc_component_read32(rt5670->component, RT5670_A_JD_CTRL1) & 0x0020; val 525 sound/soc/codecs/rt5670.c switch (val) { val 730 sound/soc/codecs/rt5670.c unsigned int reg, shift, val; val 765 sound/soc/codecs/rt5670.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; val 766 sound/soc/codecs/rt5670.c switch (val) { val 2504 sound/soc/codecs/rt5670.c unsigned int val = 0; val 2507 sound/soc/codecs/rt5670.c val |= (1 << 14); val 2511 sound/soc/codecs/rt5670.c val |= (1 << 12); val 2514 sound/soc/codecs/rt5670.c val |= (2 << 12); val 2517 sound/soc/codecs/rt5670.c val |= (3 << 12); val 2527 sound/soc/codecs/rt5670.c val |= (1 << 10); val 2530 sound/soc/codecs/rt5670.c val |= (2 << 10); val 2533 sound/soc/codecs/rt5670.c val |= (3 << 10); val 2541 sound/soc/codecs/rt5670.c snd_soc_component_update_bits(component, RT5670_TDM_CTRL_1, 0x7c00, val); val 2903 sound/soc/codecs/rt5670.c unsigned int val; val 2981 sound/soc/codecs/rt5670.c regmap_read(rt5670->regmap, RT5670_VENDOR_ID2, &val); val 2982 sound/soc/codecs/rt5670.c if (val != RT5670_DEVICE_ID) { val 2984 sound/soc/codecs/rt5670.c "Device with ID register %#x is not rt5670/72\n", val); val 2996 sound/soc/codecs/rt5670.c regmap_read(rt5670->regmap, RT5670_VENDOR_ID, &val); val 2997 sound/soc/codecs/rt5670.c if (val >= 4) val 937 sound/soc/codecs/rt5677.c unsigned int val; val 939 sound/soc/codecs/rt5677.c regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); val 940 sound/soc/codecs/rt5677.c val &= RT5677_SCLK_SRC_MASK; val 941 sound/soc/codecs/rt5677.c if (val == RT5677_SCLK_SRC_PLL1) val 952 sound/soc/codecs/rt5677.c unsigned int reg, shift, val; val 1018 sound/soc/codecs/rt5677.c regmap_read(rt5677->regmap, reg, &val); val 1019 sound/soc/codecs/rt5677.c val = (val >> shift) & 0xf; val 1021 sound/soc/codecs/rt5677.c switch (val) { val 4399 sound/soc/codecs/rt5677.c unsigned int val = 0, slot_width_25 = 0; val 4402 sound/soc/codecs/rt5677.c val |= (1 << 12); val 4406 sound/soc/codecs/rt5677.c val |= (1 << 10); val 4409 sound/soc/codecs/rt5677.c val |= (2 << 10); val 4412 sound/soc/codecs/rt5677.c val |= (3 << 10); val 4421 sound/soc/codecs/rt5677.c val |= (1 << 8); val 4427 sound/soc/codecs/rt5677.c val |= (2 << 8); val 4430 sound/soc/codecs/rt5677.c val |= (3 << 8); val 4440 sound/soc/codecs/rt5677.c val); val 4446 sound/soc/codecs/rt5677.c val); val 4789 sound/soc/codecs/rt5677.c static int rt5677_read(void *context, unsigned int reg, unsigned int *val) val 4799 sound/soc/codecs/rt5677.c rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); val 4802 sound/soc/codecs/rt5677.c rt5677_dsp_mode_i2c_read(rt5677, reg, val); val 4805 sound/soc/codecs/rt5677.c regmap_read(rt5677->regmap_physical, reg, val); val 4811 sound/soc/codecs/rt5677.c static int rt5677_write(void *context, unsigned int reg, unsigned int val) val 4822 sound/soc/codecs/rt5677.c val); val 4825 sound/soc/codecs/rt5677.c rt5677_dsp_mode_i2c_write(rt5677, reg, val); val 4828 sound/soc/codecs/rt5677.c regmap_write(rt5677->regmap_physical, reg, val); val 5010 sound/soc/codecs/rt5677.c u32 val; val 5036 sound/soc/codecs/rt5677.c if (!device_property_read_u32(dev, "DCLK", &val) || val 5037 sound/soc/codecs/rt5677.c !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val)) val 5038 sound/soc/codecs/rt5677.c rt5677->pdata.dmic2_clk_pin = val; val 5040 sound/soc/codecs/rt5677.c if (!device_property_read_u32(dev, "JD1", &val) || val 5041 sound/soc/codecs/rt5677.c !device_property_read_u32(dev, "realtek,jd1-gpio", &val)) val 5042 sound/soc/codecs/rt5677.c rt5677->pdata.jd1_gpio = val; val 5044 sound/soc/codecs/rt5677.c if (!device_property_read_u32(dev, "JD2", &val) || val 5045 sound/soc/codecs/rt5677.c !device_property_read_u32(dev, "realtek,jd2-gpio", &val)) val 5046 sound/soc/codecs/rt5677.c rt5677->pdata.jd2_gpio = val; val 5048 sound/soc/codecs/rt5677.c if (!device_property_read_u32(dev, "JD3", &val) || val 5049 sound/soc/codecs/rt5677.c !device_property_read_u32(dev, "realtek,jd3-gpio", &val)) val 5050 sound/soc/codecs/rt5677.c rt5677->pdata.jd3_gpio = val; val 5267 sound/soc/codecs/rt5677.c unsigned int val; val 5339 sound/soc/codecs/rt5677.c regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); val 5340 sound/soc/codecs/rt5677.c if (val != RT5677_DEVICE_ID) { val 5342 sound/soc/codecs/rt5677.c "Device with ID register %#x is not rt5677\n", val); val 858 sound/soc/codecs/rt5682.c int btn_type, val; val 860 sound/soc/codecs/rt5682.c val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1); val 861 sound/soc/codecs/rt5682.c btn_type = val & 0xfff0; val 862 sound/soc/codecs/rt5682.c snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); val 911 sound/soc/codecs/rt5682.c unsigned int val, count; val 930 sound/soc/codecs/rt5682.c val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2) val 932 sound/soc/codecs/rt5682.c while (val == 0 && count < 50) { val 934 sound/soc/codecs/rt5682.c val = snd_soc_component_read32(component, val 939 sound/soc/codecs/rt5682.c switch (val) { val 1053 sound/soc/codecs/rt5682.c int val, btn_type; val 1063 sound/soc/codecs/rt5682.c val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) val 1065 sound/soc/codecs/rt5682.c if (!val) { val 1217 sound/soc/codecs/rt5682.c int ref, val, reg, idx = -EINVAL; val 1221 sound/soc/codecs/rt5682.c val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) & val 1224 sound/soc/codecs/rt5682.c val == RT5682_GP4_PIN_ADCDAT2) val 1255 sound/soc/codecs/rt5682.c unsigned int val; val 1259 sound/soc/codecs/rt5682.c val = snd_soc_component_read32(component, RT5682_GLB_CLK); val 1260 sound/soc/codecs/rt5682.c val &= RT5682_SCLK_SRC_MASK; val 1261 sound/soc/codecs/rt5682.c if (val == RT5682_SCLK_SRC_PLL1) val 1270 sound/soc/codecs/rt5682.c unsigned int reg, shift, val; val 1287 sound/soc/codecs/rt5682.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; val 1288 sound/soc/codecs/rt5682.c switch (val) { val 1929 sound/soc/codecs/rt5682.c unsigned int cl, val = 0; val 1940 sound/soc/codecs/rt5682.c val |= RT5682_TDM_TX_CH_4; val 1941 sound/soc/codecs/rt5682.c val |= RT5682_TDM_RX_CH_4; val 1944 sound/soc/codecs/rt5682.c val |= RT5682_TDM_TX_CH_6; val 1945 sound/soc/codecs/rt5682.c val |= RT5682_TDM_RX_CH_6; val 1948 sound/soc/codecs/rt5682.c val |= RT5682_TDM_TX_CH_8; val 1949 sound/soc/codecs/rt5682.c val |= RT5682_TDM_RX_CH_8; val 1958 sound/soc/codecs/rt5682.c RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); val 1967 sound/soc/codecs/rt5682.c val = RT5682_TDM_CL_16; val 1971 sound/soc/codecs/rt5682.c val = RT5682_TDM_CL_20; val 1975 sound/soc/codecs/rt5682.c val = RT5682_TDM_CL_24; val 1979 sound/soc/codecs/rt5682.c val = RT5682_TDM_CL_32; val 1987 sound/soc/codecs/rt5682.c RT5682_TDM_CL_MASK, val); val 2536 sound/soc/codecs/rt5682.c unsigned int val; val 2590 sound/soc/codecs/rt5682.c regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val); val 2591 sound/soc/codecs/rt5682.c if (val != DEVICE_ID) { val 2592 sound/soc/codecs/rt5682.c pr_err("Device with ID register %x is not rt5682\n", val); val 1560 sound/soc/codecs/sgtl5000.c int i, ret, val, index; val 1563 sound/soc/codecs/sgtl5000.c val = sgtl5000_reg_defaults[i].def; val 1565 sound/soc/codecs/sgtl5000.c ret = regmap_write(sgtl5000->regmap, index, val); val 1569 sound/soc/codecs/sgtl5000.c __func__, ret, index, val); val 23 sound/soc/codecs/simple-amplifier.c int val; val 27 sound/soc/codecs/simple-amplifier.c val = 1; val 30 sound/soc/codecs/simple-amplifier.c val = 0; val 37 sound/soc/codecs/simple-amplifier.c gpiod_set_value_cansleep(priv->gpiod_enable, val); val 394 sound/soc/codecs/ssm2518.c unsigned int val; val 397 sound/soc/codecs/ssm2518.c val = SSM2518_MUTE_CTRL_MUTE_MASTER; val 399 sound/soc/codecs/ssm2518.c val = 0; val 402 sound/soc/codecs/ssm2518.c SSM2518_MUTE_CTRL_MUTE_MASTER, val); val 647 sound/soc/codecs/ssm2518.c unsigned int val; val 654 sound/soc/codecs/ssm2518.c val = 0; val 660 sound/soc/codecs/ssm2518.c val = SSM2518_POWER1_NO_BCLK; val 709 sound/soc/codecs/ssm2518.c SSM2518_POWER1_NO_BCLK, val); val 226 sound/soc/codecs/ssm4567.c unsigned int val; val 228 sound/soc/codecs/ssm4567.c val = mute ? SSM4567_DAC_MUTE : 0; val 230 sound/soc/codecs/ssm4567.c SSM4567_DAC_MUTE, val); val 275 sound/soc/codecs/sta32x.c unsigned int cfud, val; val 300 sound/soc/codecs/sta32x.c regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val); val 301 sound/soc/codecs/sta32x.c ucontrol->value.bytes.data[i] = val; val 312 sound/soc/codecs/sta350.c unsigned int cfud, val; val 337 sound/soc/codecs/sta350.c regmap_read(sta350->regmap, STA350_B1CF1 + i, &val); val 338 sound/soc/codecs/sta350.c ucontrol->value.bytes.data[i] = val; val 256 sound/soc/codecs/sta529.c u8 val = 0; val 259 sound/soc/codecs/sta529.c val |= CODEC_MUTE_VAL; val 261 sound/soc/codecs/sta529.c snd_soc_component_update_bits(dai->component, STA529_FFXCFG0, AUDIO_MUTE_MSK, val); val 89 sound/soc/codecs/sti-sas.c u32 val; val 91 sound/soc/codecs/sti-sas.c status = regmap_read(drvdata->dac.regmap, reg, &val); val 92 sound/soc/codecs/sti-sas.c *value = (unsigned int)val; val 398 sound/soc/codecs/tas2552.c u8 reg, mask, val; val 414 sound/soc/codecs/tas2552.c val = (clk_id << 3) & mask; /* bit 4:5 in the register */ val 424 sound/soc/codecs/tas2552.c val = (clk_id >> 1) & mask; /* bit 0:1 in the register */ val 434 sound/soc/codecs/tas2552.c snd_soc_component_update_bits(component, reg, mask, val); val 54 sound/soc/codecs/tas5086.c #define TAS5086_CLOCK_RATE(val) (val << 5) val 56 sound/soc/codecs/tas5086.c #define TAS5086_CLOCK_RATIO(val) (val << 2) val 258 sound/soc/codecs/tas5086.c int i, val = 0; val 263 sound/soc/codecs/tas5086.c val = i; val 270 sound/soc/codecs/tas5086.c TAS5086_DEEMPH_MASK, val); val 357 sound/soc/codecs/tas5086.c int val; val 363 sound/soc/codecs/tas5086.c val = index_in_array(tas5086_sample_rates, val 366 sound/soc/codecs/tas5086.c if (val < 0) { val 373 sound/soc/codecs/tas5086.c TAS5086_CLOCK_RATE(val)); val 378 sound/soc/codecs/tas5086.c val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios), val 380 sound/soc/codecs/tas5086.c if (val < 0) { val 387 sound/soc/codecs/tas5086.c TAS5086_CLOCK_RATIO(val)); val 409 sound/soc/codecs/tas5086.c val = 0x00; val 412 sound/soc/codecs/tas5086.c val = 0x03; val 415 sound/soc/codecs/tas5086.c val = 0x06; val 425 sound/soc/codecs/tas5086.c val += 0; val 428 sound/soc/codecs/tas5086.c val += 1; val 431 sound/soc/codecs/tas5086.c val += 2; val 438 sound/soc/codecs/tas5086.c ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val); val 455 sound/soc/codecs/tas5086.c unsigned int val = 0; val 458 sound/soc/codecs/tas5086.c val = TAS5086_SOFT_MUTE_ALL; val 460 sound/soc/codecs/tas5086.c return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val); val 279 sound/soc/codecs/tas571x.c u32 val; val 283 sound/soc/codecs/tas571x.c val = 0x00; val 286 sound/soc/codecs/tas571x.c val = 0x03; val 289 sound/soc/codecs/tas571x.c val = 0x06; val 296 sound/soc/codecs/tas571x.c val += 2; val 298 sound/soc/codecs/tas571x.c val += 1; val 301 sound/soc/codecs/tas571x.c TAS571X_SDI_FMT_MASK, val); val 509 sound/soc/codecs/tas5720.c unsigned int val; val 511 sound/soc/codecs/tas5720.c snd_soc_component_read(component, TAS5720_VOLUME_CTRL_REG, &val); val 512 sound/soc/codecs/tas5720.c ucontrol->value.integer.value[0] = val << 1; val 514 sound/soc/codecs/tas5720.c snd_soc_component_read(component, TAS5722_DIGITAL_CTRL2_REG, &val); val 515 sound/soc/codecs/tas5720.c ucontrol->value.integer.value[0] |= val & TAS5722_VOL_CONTROL_LSB; val 259 sound/soc/codecs/tas6424.c unsigned int val; val 269 sound/soc/codecs/tas6424.c val = TAS6424_ALL_STATE_MUTE; val 271 sound/soc/codecs/tas6424.c val = TAS6424_ALL_STATE_PLAY; val 273 sound/soc/codecs/tas6424.c snd_soc_component_write(component, TAS6424_CH_STATE_CTRL, val); val 156 sound/soc/codecs/tda7419.c static inline int tda7419_vol_get_value(int val, unsigned int mask, val 160 sound/soc/codecs/tda7419.c val &= mask; val 161 sound/soc/codecs/tda7419.c if (val < thresh) { val 163 sound/soc/codecs/tda7419.c val = 0 - val; val 164 sound/soc/codecs/tda7419.c } else if (val > thresh) { val 166 sound/soc/codecs/tda7419.c val = val - thresh; val 168 sound/soc/codecs/tda7419.c val = thresh - val; val 171 sound/soc/codecs/tda7419.c if (val < min) val 172 sound/soc/codecs/tda7419.c val = min; val 174 sound/soc/codecs/tda7419.c return val; val 189 sound/soc/codecs/tda7419.c int val; val 192 sound/soc/codecs/tda7419.c ret = snd_soc_component_read(component, reg, &val); val 196 sound/soc/codecs/tda7419.c tda7419_vol_get_value(val, mask, min, thresh, invert); val 199 sound/soc/codecs/tda7419.c ret = snd_soc_component_read(component, rreg, &val); val 203 sound/soc/codecs/tda7419.c tda7419_vol_get_value(val, mask, min, thresh, invert); val 209 sound/soc/codecs/tda7419.c static inline int tda7419_vol_put_value(int val, int thresh, val 212 sound/soc/codecs/tda7419.c if (val < 0) { val 214 sound/soc/codecs/tda7419.c val = abs(val); val 216 sound/soc/codecs/tda7419.c val = thresh - val; val 217 sound/soc/codecs/tda7419.c } else if ((val > 0) && invert) { val 218 sound/soc/codecs/tda7419.c val += thresh; val 221 sound/soc/codecs/tda7419.c return val; val 236 sound/soc/codecs/tda7419.c int val; val 239 sound/soc/codecs/tda7419.c val = tda7419_vol_put_value(ucontrol->value.integer.value[0], val 242 sound/soc/codecs/tda7419.c mask, val); val 247 sound/soc/codecs/tda7419.c val = tda7419_vol_put_value(ucontrol->value.integer.value[1], val 250 sound/soc/codecs/tda7419.c mask, val); val 81 sound/soc/codecs/tlv320aic23.c u16 val, reg; val 83 sound/soc/codecs/tlv320aic23.c val = (ucontrol->value.integer.value[0] & 0x07); val 92 sound/soc/codecs/tlv320aic23.c val = (val >= 4) ? 4 : (3 - val); val 95 sound/soc/codecs/tlv320aic23.c snd_soc_component_write(component, TLV320AIC23_ANLG, reg | (val << 6)); val 104 sound/soc/codecs/tlv320aic23.c u16 val; val 106 sound/soc/codecs/tlv320aic23.c val = snd_soc_component_read32(component, TLV320AIC23_ANLG) & (0x1C0); val 107 sound/soc/codecs/tlv320aic23.c val = val >> 6; val 108 sound/soc/codecs/tlv320aic23.c val = (val >= 4) ? 4 : (3 - val); val 109 sound/soc/codecs/tlv320aic23.c ucontrol->value.integer.value[0] = val; val 299 sound/soc/codecs/tlv320aic23.c int val = (mclk / bosr_usb_divisor_table[src & 3]); val 300 sound/soc/codecs/tlv320aic23.c int adc = (val * sr_adc_mult_table[sr]) / SR_MULT; val 301 sound/soc/codecs/tlv320aic23.c int dac = (val * sr_dac_mult_table[sr]) / SR_MULT; val 267 sound/soc/codecs/tlv320aic26.c int val, amp, freq, len; val 269 sound/soc/codecs/tlv320aic26.c val = snd_soc_component_read32(aic26->component, AIC26_REG_AUDIO_CTRL2); val 270 sound/soc/codecs/tlv320aic26.c amp = (val >> 12) & 0x7; val 271 sound/soc/codecs/tlv320aic26.c freq = (125 << ((val >> 8) & 0x7)) >> 1; val 272 sound/soc/codecs/tlv320aic26.c len = 2 * (1 + ((val >> 4) & 0xf)); val 1426 sound/soc/codecs/tlv320aic31xx.c unsigned int val; val 1430 sound/soc/codecs/tlv320aic31xx.c &val); val 1437 sound/soc/codecs/tlv320aic31xx.c if (val & AIC31XX_BUTTONPRESS) val 1440 sound/soc/codecs/tlv320aic31xx.c ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val); val 1446 sound/soc/codecs/tlv320aic31xx.c switch ((val & AIC31XX_HSD_TYPE_MASK) >> val 67 sound/soc/codecs/tlv320aic32x4-clk.c unsigned int val; val 70 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); val 74 sound/soc/codecs/tlv320aic32x4-clk.c return !!(val & AIC32X4_PLLEN); val 81 sound/soc/codecs/tlv320aic32x4-clk.c unsigned int val; val 84 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); val 87 sound/soc/codecs/tlv320aic32x4-clk.c settings->r = val & AIC32X4_PLL_R_MASK; val 88 sound/soc/codecs/tlv320aic32x4-clk.c settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT; val 90 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val); val 93 sound/soc/codecs/tlv320aic32x4-clk.c settings->j = val; val 95 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val); val 98 sound/soc/codecs/tlv320aic32x4-clk.c settings->d = val << 8; val 100 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val); val 103 sound/soc/codecs/tlv320aic32x4-clk.c settings->d |= val; val 249 sound/soc/codecs/tlv320aic32x4-clk.c unsigned int val; val 251 sound/soc/codecs/tlv320aic32x4-clk.c regmap_read(pll->regmap, AIC32X4_PLLPR, &val); val 253 sound/soc/codecs/tlv320aic32x4-clk.c return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT; val 280 sound/soc/codecs/tlv320aic32x4-clk.c unsigned int val; val 282 sound/soc/codecs/tlv320aic32x4-clk.c regmap_read(mux->regmap, AIC32X4_CLKMUX, &val); val 284 sound/soc/codecs/tlv320aic32x4-clk.c return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT; val 339 sound/soc/codecs/tlv320aic32x4-clk.c unsigned int val; val 341 sound/soc/codecs/tlv320aic32x4-clk.c regmap_read(div->regmap, div->reg, &val); val 343 sound/soc/codecs/tlv320aic32x4-clk.c return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK); val 365 sound/soc/codecs/tlv320aic32x4-clk.c unsigned int val; val 367 sound/soc/codecs/tlv320aic32x4-clk.c regmap_read(mux->regmap, AIC32X4_IFACE3, &val); val 369 sound/soc/codecs/tlv320aic32x4-clk.c return val & AIC32X4_BDIVCLK_MASK; val 83 sound/soc/codecs/tlv320aic32x4.c u8 val; val 85 sound/soc/codecs/tlv320aic32x4.c val = snd_soc_component_read32(component, AIC32X4_DINCTL); val 87 sound/soc/codecs/tlv320aic32x4.c ucontrol->value.integer.value[0] = (val & 0x01); val 96 sound/soc/codecs/tlv320aic32x4.c u8 val; val 99 sound/soc/codecs/tlv320aic32x4.c val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); val 100 sound/soc/codecs/tlv320aic32x4.c gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); val 107 sound/soc/codecs/tlv320aic32x4.c if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) val 111 sound/soc/codecs/tlv320aic32x4.c val |= ucontrol->value.integer.value[0]; val 113 sound/soc/codecs/tlv320aic32x4.c val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; val 115 sound/soc/codecs/tlv320aic32x4.c snd_soc_component_write(component, AIC32X4_DOUTCTL, val); val 124 sound/soc/codecs/tlv320aic32x4.c u8 val; val 126 sound/soc/codecs/tlv320aic32x4.c val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); val 128 sound/soc/codecs/tlv320aic32x4.c ucontrol->value.integer.value[0] = (val & 0x01); val 137 sound/soc/codecs/tlv320aic32x4.c u8 val; val 140 sound/soc/codecs/tlv320aic32x4.c val = snd_soc_component_read32(component, AIC32X4_MISOCTL); val 141 sound/soc/codecs/tlv320aic32x4.c gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); val 148 sound/soc/codecs/tlv320aic32x4.c if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) val 152 sound/soc/codecs/tlv320aic32x4.c val |= ucontrol->value.integer.value[0]; val 154 sound/soc/codecs/tlv320aic32x4.c val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; val 156 sound/soc/codecs/tlv320aic32x4.c snd_soc_component_write(component, AIC32X4_MISOCTL, val); val 165 sound/soc/codecs/tlv320aic32x4.c u8 val; val 167 sound/soc/codecs/tlv320aic32x4.c val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); val 168 sound/soc/codecs/tlv320aic32x4.c ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); val 177 sound/soc/codecs/tlv320aic32x4.c u8 val; val 180 sound/soc/codecs/tlv320aic32x4.c val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); val 181 sound/soc/codecs/tlv320aic32x4.c gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); val 188 sound/soc/codecs/tlv320aic32x4.c if (ucontrol->value.integer.value[0] == (val & 0x1)) val 192 sound/soc/codecs/tlv320aic32x4.c val |= ucontrol->value.integer.value[0]; val 194 sound/soc/codecs/tlv320aic32x4.c val &= 0xfe; val 196 sound/soc/codecs/tlv320aic32x4.c snd_soc_component_write(component, AIC32X4_GPIOCTL, val); val 171 sound/soc/codecs/tlv320aic3x.c unsigned short val; val 175 sound/soc/codecs/tlv320aic3x.c val = (ucontrol->value.integer.value[0] & mask); val 178 sound/soc/codecs/tlv320aic3x.c if (val) val 179 sound/soc/codecs/tlv320aic3x.c val = mask; val 181 sound/soc/codecs/tlv320aic3x.c connect = !!val; val 184 sound/soc/codecs/tlv320aic3x.c val = mask - val; val 187 sound/soc/codecs/tlv320aic3x.c val <<= shift; val 189 sound/soc/codecs/tlv320aic3x.c change = snd_soc_component_test_bits(component, reg, mask, val); val 194 sound/soc/codecs/tlv320aic3x.c update.val = val; val 232 sound/soc/codecs/tlv320aic3x.h #define INVERT_VOL(val) (0x7f - val) val 186 sound/soc/codecs/tlv320dac33.c int val, ret = 0; val 192 sound/soc/codecs/tlv320dac33.c val = i2c_smbus_read_byte_data(dac33->i2c, value[0]); val 193 sound/soc/codecs/tlv320dac33.c if (val < 0) { val 194 sound/soc/codecs/tlv320dac33.c dev_err(component->dev, "Read failed (%d)\n", val); val 196 sound/soc/codecs/tlv320dac33.c ret = val; val 198 sound/soc/codecs/tlv320dac33.c value[0] = val; val 199 sound/soc/codecs/tlv320dac33.c dac33_write_reg_cache(component, reg, val); val 194 sound/soc/codecs/tscs42xx.c unsigned int val; val 200 sound/soc/codecs/tscs42xx.c val = RV_PLLCTL1C_PDB_PLL1_ENABLE; val 204 sound/soc/codecs/tscs42xx.c val = RV_PLLCTL1C_PDB_PLL2_ENABLE; val 215 sound/soc/codecs/tscs42xx.c ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val); val 942 sound/soc/codecs/tscs42xx.c unsigned int val; val 1078 sound/soc/codecs/tscs42xx.c pll_ctl->settings[i].val); val 1276 sound/soc/codecs/tscs42xx.c int val; val 1284 sound/soc/codecs/tscs42xx.c val = reg << 8; val 1289 sound/soc/codecs/tscs42xx.c val |= reg; val 1291 sound/soc/codecs/tscs42xx.c switch (val) { val 304 sound/soc/codecs/tscs454.c unsigned int val; val 348 sound/soc/codecs/tscs454.c unsigned int val; val 356 sound/soc/codecs/tscs454.c ret = snd_soc_component_read(component, r_stat, &val); val 362 sound/soc/codecs/tscs454.c if (!val) val 409 sound/soc/codecs/tscs454.c unsigned int val; val 447 sound/soc/codecs/tscs454.c ret = snd_soc_component_read(component, R_PLLSTAT, &val); val 453 sound/soc/codecs/tscs454.c if (val) { /* PLLs locked */ val 658 sound/soc/codecs/tscs454.c pll_ctl->settings[i].val); val 722 sound/soc/codecs/tscs454.c unsigned int val; val 738 sound/soc/codecs/tscs454.c val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE; val 740 sound/soc/codecs/tscs454.c val = pll1 ? FV_PLL1CLKEN_DISABLE : FV_PLL2CLKEN_DISABLE; val 742 sound/soc/codecs/tscs454.c ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val); val 769 sound/soc/codecs/tscs454.c unsigned int val; val 788 sound/soc/codecs/tscs454.c val = master ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE; val 790 sound/soc/codecs/tscs454.c ret = snd_soc_component_update_bits(component, reg, mask, val); val 2643 sound/soc/codecs/tscs454.c unsigned int val; val 2649 sound/soc/codecs/tscs454.c ret = snd_soc_component_read(component, R_PLLCTL, &val); val 2653 sound/soc/codecs/tscs454.c bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL; val 2667 sound/soc/codecs/tscs454.c unsigned int val; val 2694 sound/soc/codecs/tscs454.c val = I2SCMC_BCMP_32X; val 2697 sound/soc/codecs/tscs454.c val = I2SCMC_BCMP_40X; val 2700 sound/soc/codecs/tscs454.c val = I2SCMC_BCMP_64X; val 2709 sound/soc/codecs/tscs454.c R_I2SCMC, mask, val << shift); val 2777 sound/soc/codecs/tscs454.c unsigned int val; val 2799 sound/soc/codecs/tscs454.c val = FV_FORMAT_RIGHT; val 2802 sound/soc/codecs/tscs454.c val = FV_FORMAT_LEFT; val 2805 sound/soc/codecs/tscs454.c val = FV_FORMAT_I2S; val 2811 sound/soc/codecs/tscs454.c val = FV_FORMAT_TDM; val 2817 sound/soc/codecs/tscs454.c val = FV_FORMAT_TDM; val 2826 sound/soc/codecs/tscs454.c reg, FM_I2SPCTL_FORMAT, val); val 2841 sound/soc/codecs/tscs454.c unsigned int val; val 2863 sound/soc/codecs/tscs454.c val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED; val 2866 sound/soc/codecs/tscs454.c val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED; val 2869 sound/soc/codecs/tscs454.c val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED; val 2872 sound/soc/codecs/tscs454.c val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED; val 2881 sound/soc/codecs/tscs454.c FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val); val 2919 sound/soc/codecs/tscs454.c unsigned int val; val 2933 sound/soc/codecs/tscs454.c val = FV_TDMSO_2 | FV_TDMSI_2; val 2936 sound/soc/codecs/tscs454.c val = FV_TDMSO_4 | FV_TDMSI_4; val 2939 sound/soc/codecs/tscs454.c val = FV_TDMSO_6 | FV_TDMSI_6; val 2949 sound/soc/codecs/tscs454.c val = val | FV_TDMDSS_16; val 2952 sound/soc/codecs/tscs454.c val = val | FV_TDMDSS_24; val 2955 sound/soc/codecs/tscs454.c val = val | FV_TDMDSS_32; val 2962 sound/soc/codecs/tscs454.c ret = snd_soc_component_write(component, R_TDMCTL1, val); val 2977 sound/soc/codecs/tscs454.c unsigned int val; val 3005 sound/soc/codecs/tscs454.c val = FV_PCMSOP_1 | FV_PCMSIP_1; val 3008 sound/soc/codecs/tscs454.c val = FV_PCMSOP_2 | FV_PCMSIP_2; val 3018 sound/soc/codecs/tscs454.c val = val | FV_PCMDSSP_16; val 3021 sound/soc/codecs/tscs454.c val = val | FV_PCMDSSP_24; val 3024 sound/soc/codecs/tscs454.c val = val | FV_PCMDSSP_32; val 3031 sound/soc/codecs/tscs454.c ret = snd_soc_component_write(component, reg, val); val 3186 sound/soc/codecs/tscs454.c unsigned int val; val 3207 sound/soc/codecs/tscs454.c ret = snd_soc_component_read(component, R_ISRC, &val); val 3211 sound/soc/codecs/tscs454.c if ((val & FM_ISRC_IBR) == FV_IBR_48) val 3297 sound/soc/codecs/tscs454.c unsigned int val; val 3302 sound/soc/codecs/tscs454.c val = FV_PLLISEL_XTAL; val 3305 sound/soc/codecs/tscs454.c val = FV_PLLISEL_MCLK1; val 3308 sound/soc/codecs/tscs454.c val = FV_PLLISEL_MCLK2; val 3311 sound/soc/codecs/tscs454.c val = FV_PLLISEL_BCLK; val 3320 sound/soc/codecs/tscs454.c FM_PLLCTL_PLLISEL, val); val 866 sound/soc/codecs/twl4030.c unsigned short val, val2, val_mask; val 868 sound/soc/codecs/twl4030.c val = (ucontrol->value.integer.value[0] & mask); val 871 sound/soc/codecs/twl4030.c if (val) val 872 sound/soc/codecs/twl4030.c val = max + 1 - val; val 873 sound/soc/codecs/twl4030.c val = val << shift; val 879 sound/soc/codecs/twl4030.c val |= val2 << rshift; val 881 sound/soc/codecs/twl4030.c return snd_soc_component_update_bits(component, reg, val_mask, val); val 923 sound/soc/codecs/twl4030.c unsigned short val, val2, val_mask; val 926 sound/soc/codecs/twl4030.c val = (ucontrol->value.integer.value[0] & mask); val 929 sound/soc/codecs/twl4030.c if (val) val 930 sound/soc/codecs/twl4030.c val = max + 1 - val; val 934 sound/soc/codecs/twl4030.c val = val << shift; val 937 sound/soc/codecs/twl4030.c err = snd_soc_component_update_bits(component, reg, val_mask, val); val 328 sound/soc/codecs/twl6040.c unsigned int val; val 331 sound/soc/codecs/twl6040.c val = twl6040_read(component, e->reg); val 332 sound/soc/codecs/twl6040.c if (val & TWL6040_VIBENA && !(val & TWL6040_VIBSEL)) val 532 sound/soc/codecs/twl6040.c u8 val = twl6040_read(component, TWL6040_REG_HSLCTL); val 533 sound/soc/codecs/twl6040.c if (val & TWL6040_HSDACMODE) val 129 sound/soc/codecs/uda1334.c unsigned int val; val 136 sound/soc/codecs/uda1334.c val = freq / lrclk_ratios[i].ratio; val 143 sound/soc/codecs/uda1334.c switch (val) { val 152 sound/soc/codecs/uda1334.c val); val 153 sound/soc/codecs/uda1334.c uda1334->rate_constraint_list[j++] = val; val 158 sound/soc/codecs/uda1334.c val); val 124 sound/soc/codecs/uda134x.c unsigned int val; val 129 sound/soc/codecs/uda134x.c val = mask; val 131 sound/soc/codecs/uda134x.c val = 0; val 133 sound/soc/codecs/uda134x.c return regmap_update_bits(uda134x->regmap, UDA134X_DATA010, mask, val); val 117 sound/soc/codecs/uda1380.c unsigned int val; val 120 sound/soc/codecs/uda1380.c val = (data[0]<<8) | data[1]; val 121 sound/soc/codecs/uda1380.c if (val != value) { val 198 sound/soc/codecs/wcd-clsh-v2.c int val = 0; val 203 sound/soc/codecs/wcd-clsh-v2.c val = WCD9XXX_HPH_CONST_SEL_BYPASS; val 206 sound/soc/codecs/wcd-clsh-v2.c val = WCD9XXX_HPH_CONST_SEL_HQ_PATH; val 209 sound/soc/codecs/wcd-clsh-v2.c val = WCD9XXX_HPH_CONST_SEL_LP_PATH; val 215 sound/soc/codecs/wcd-clsh-v2.c val); val 219 sound/soc/codecs/wcd-clsh-v2.c val); val 225 sound/soc/codecs/wcd-clsh-v2.c int val = 0, gain = 0, res_val; val 232 sound/soc/codecs/wcd-clsh-v2.c val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL; val 237 sound/soc/codecs/wcd-clsh-v2.c val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL; val 242 sound/soc/codecs/wcd-clsh-v2.c val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA; val 247 sound/soc/codecs/wcd-clsh-v2.c val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP; val 253 sound/soc/codecs/wcd-clsh-v2.c WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK, val); val 430 sound/soc/codecs/wcd9335.c u8 val; val 1477 sound/soc/codecs/wcd9335.c unsigned int val, reg, sel; val 1479 sound/soc/codecs/wcd9335.c val = ucontrol->value.enumerated.item[0]; val 1514 sound/soc/codecs/wcd9335.c sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; val 1527 sound/soc/codecs/wcd9335.c int reg, val; val 1530 sound/soc/codecs/wcd9335.c val = ucontrol->value.enumerated.item[0]; val 1544 sound/soc/codecs/wcd9335.c val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); val 1616 sound/soc/codecs/wcd9335.c int val, j; val 1620 sound/soc/codecs/wcd9335.c val = snd_soc_component_read32(component, val 1624 sound/soc/codecs/wcd9335.c if (val == (ch->shift + INTn_2_INP_SEL_RX0)) val 2621 sound/soc/codecs/wcd9335.c u8 val; val 2627 sound/soc/codecs/wcd9335.c val = set ? mask : 0x00; val 2633 sound/soc/codecs/wcd9335.c val); val 2638 sound/soc/codecs/wcd9335.c val); val 2643 sound/soc/codecs/wcd9335.c val); val 2998 sound/soc/codecs/wcd9335.c unsigned int val = 0; val 3011 sound/soc/codecs/wcd9335.c regmap_read(wcd->if_regmap, reg, &val); val 3012 sound/soc/codecs/wcd9335.c if (!(val & BIT(port_num % 8))) val 3014 sound/soc/codecs/wcd9335.c val | BIT(port_num % 8)); val 3045 sound/soc/codecs/wcd9335.c int val = 0; val 3083 sound/soc/codecs/wcd9335.c val = snd_soc_component_read32(comp, gain_reg); val 3084 sound/soc/codecs/wcd9335.c val += offset_val; val 3085 sound/soc/codecs/wcd9335.c snd_soc_component_write(comp, gain_reg, val); val 3304 sound/soc/codecs/wcd9335.c int val; val 3347 sound/soc/codecs/wcd9335.c val = snd_soc_component_read32(comp, gain_reg); val 3348 sound/soc/codecs/wcd9335.c val += offset_val; val 3349 sound/soc/codecs/wcd9335.c snd_soc_component_write(comp, gain_reg, val); val 3970 sound/soc/codecs/wcd9335.c unsigned int val, int_val = 0; val 3977 sound/soc/codecs/wcd9335.c regmap_read(wcd->if_regmap, i, &val); val 3978 sound/soc/codecs/wcd9335.c status |= ((u32)val << (8 * j)); val 3985 sound/soc/codecs/wcd9335.c WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); val 3986 sound/soc/codecs/wcd9335.c if (val) { val 4003 sound/soc/codecs/wcd9335.c if (val & WCD9335_SLIM_IRQ_OVERFLOW) val 4006 sound/soc/codecs/wcd9335.c __func__, (tx ? "TX" : "RX"), port_id, val); val 4008 sound/soc/codecs/wcd9335.c if (val & WCD9335_SLIM_IRQ_UNDERFLOW) val 4011 sound/soc/codecs/wcd9335.c __func__, (tx ? "TX" : "RX"), port_id, val); val 4013 sound/soc/codecs/wcd9335.c if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || val 4014 sound/soc/codecs/wcd9335.c (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { val 4839 sound/soc/codecs/wcd9335.c wcd9335_codec_reg_init[i].val); val 5084 sound/soc/codecs/wcd9335.c int val, byte0; val 5086 sound/soc/codecs/wcd9335.c regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); val 5089 sound/soc/codecs/wcd9335.c if ((val < 0) || (byte0 < 0)) { val 217 sound/soc/codecs/wl1273.c int val, r = 0; val 221 sound/soc/codecs/wl1273.c val = ucontrol->value.enumerated.item[0]; val 222 sound/soc/codecs/wl1273.c if (wl1273->core->audio_mode == val) val 225 sound/soc/codecs/wl1273.c r = wl1273->core->set_audio(wl1273->core, val); val 104 sound/soc/codecs/wm2000.c unsigned int val; val 106 sound/soc/codecs/wm2000.c regmap_read(wm2000->regmap, reg, &val); val 108 sound/soc/codecs/wm2000.c while (!(val & mask) && --timeout) { val 110 sound/soc/codecs/wm2000.c regmap_read(wm2000->regmap, reg, &val); val 123 sound/soc/codecs/wm2000.c unsigned int val; val 202 sound/soc/codecs/wm2000.c ret = regmap_read(wm2000->regmap, WM2000_REG_SPEECH_CLARITY, &val); val 209 sound/soc/codecs/wm2000.c val |= WM2000_SPEECH_CLARITY; val 211 sound/soc/codecs/wm2000.c val &= ~WM2000_SPEECH_CLARITY; val 212 sound/soc/codecs/wm2000.c wm2000_write(i2c, WM2000_REG_SPEECH_CLARITY, val); val 647 sound/soc/codecs/wm2000.c unsigned int val = ucontrol->value.integer.value[0]; val 650 sound/soc/codecs/wm2000.c if (val > 1) val 655 sound/soc/codecs/wm2000.c wm2000->spk_ena = val; val 2060 sound/soc/codecs/wm2200.c unsigned int val = 0; val 2067 sound/soc/codecs/wm2200.c val = WM2200_AIF1TX_LRCLK_SRC; val 2074 sound/soc/codecs/wm2200.c WM2200_AIF1TX_LRCLK_SRC, val); val 2121 sound/soc/codecs/wm2200.c unsigned int val, mask; val 2124 sound/soc/codecs/wm2200.c ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, &val); val 2137 sound/soc/codecs/wm2200.c val &= ~mask; val 2139 sound/soc/codecs/wm2200.c if (val & WM2200_FLL_LOCK_EINT) { val 2144 sound/soc/codecs/wm2200.c if (val) { val 2145 sound/soc/codecs/wm2200.c regmap_write(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, val); val 2194 sound/soc/codecs/wm2200.c int val; val 2355 sound/soc/codecs/wm2200.c val = (wm2200->pdata.micbias[i].mb_lvl -1) val 2359 sound/soc/codecs/wm2200.c val |= WM2200_MICB1_DISCH; val 2362 sound/soc/codecs/wm2200.c val |= WM2200_MICB1_RATE; val 2365 sound/soc/codecs/wm2200.c val |= WM2200_MICB1_MODE; val 2372 sound/soc/codecs/wm2200.c WM2200_MICB1_RATE, val); val 737 sound/soc/codecs/wm5100.c u16 val, expect, i; val 743 sound/soc/codecs/wm5100.c val = snd_soc_component_read32(component, WM5100_OUTPUT_STATUS_1); val 744 sound/soc/codecs/wm5100.c if (val == expect) { val 758 sound/soc/codecs/wm5100.c val = snd_soc_component_read32(component, WM5100_OUTPUT_STATUS_2); val 759 sound/soc/codecs/wm5100.c if (val == expect) { val 792 sound/soc/codecs/wm5100.c static void wm5100_log_status3(struct wm5100_priv *wm5100, int val) val 794 sound/soc/codecs/wm5100.c if (val & WM5100_SPK_SHUTDOWN_WARN_EINT) val 796 sound/soc/codecs/wm5100.c if (val & WM5100_SPK_SHUTDOWN_EINT) val 798 sound/soc/codecs/wm5100.c if (val & WM5100_CLKGEN_ERR_EINT) val 800 sound/soc/codecs/wm5100.c if (val & WM5100_CLKGEN_ERR_ASYNC_EINT) val 804 sound/soc/codecs/wm5100.c static void wm5100_log_status4(struct wm5100_priv *wm5100, int val) val 806 sound/soc/codecs/wm5100.c if (val & WM5100_AIF3_ERR_EINT) val 808 sound/soc/codecs/wm5100.c if (val & WM5100_AIF2_ERR_EINT) val 810 sound/soc/codecs/wm5100.c if (val & WM5100_AIF1_ERR_EINT) val 812 sound/soc/codecs/wm5100.c if (val & WM5100_CTRLIF_ERR_EINT) val 814 sound/soc/codecs/wm5100.c if (val & WM5100_ISRC2_UNDERCLOCKED_EINT) val 816 sound/soc/codecs/wm5100.c if (val & WM5100_ISRC1_UNDERCLOCKED_EINT) val 818 sound/soc/codecs/wm5100.c if (val & WM5100_FX_UNDERCLOCKED_EINT) val 820 sound/soc/codecs/wm5100.c if (val & WM5100_AIF3_UNDERCLOCKED_EINT) val 822 sound/soc/codecs/wm5100.c if (val & WM5100_AIF2_UNDERCLOCKED_EINT) val 824 sound/soc/codecs/wm5100.c if (val & WM5100_AIF1_UNDERCLOCKED_EINT) val 826 sound/soc/codecs/wm5100.c if (val & WM5100_ASRC_UNDERCLOCKED_EINT) val 828 sound/soc/codecs/wm5100.c if (val & WM5100_DAC_UNDERCLOCKED_EINT) val 830 sound/soc/codecs/wm5100.c if (val & WM5100_ADC_UNDERCLOCKED_EINT) val 832 sound/soc/codecs/wm5100.c if (val & WM5100_MIXER_UNDERCLOCKED_EINT) val 2008 sound/soc/codecs/wm5100.c unsigned int val; val 2011 sound/soc/codecs/wm5100.c ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val); val 2018 sound/soc/codecs/wm5100.c dev_dbg(wm5100->dev, "Microphone event: %x\n", val); val 2020 sound/soc/codecs/wm5100.c if (!(val & WM5100_ACCDET_VALID)) { val 2026 sound/soc/codecs/wm5100.c if (!(val & WM5100_ACCDET_STS)) { val 2045 sound/soc/codecs/wm5100.c if (val & 0x400) { val 2073 sound/soc/codecs/wm5100.c if (wm5100->jack_detecting && (val & 0x3f8)) { val 2087 sound/soc/codecs/wm5100.c if (val & 0x3fc) { val 2224 sound/soc/codecs/wm5100.c irqreturn_t val; val 2227 sound/soc/codecs/wm5100.c val = wm5100_irq(irq, data); val 2228 sound/soc/codecs/wm5100.c if (val != IRQ_NONE) val 2229 sound/soc/codecs/wm5100.c ret = val; val 2230 sound/soc/codecs/wm5100.c } while (val != IRQ_NONE); val 2248 sound/soc/codecs/wm5100.c int val, ret; val 2250 sound/soc/codecs/wm5100.c val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT); val 2254 sound/soc/codecs/wm5100.c WM5100_GP1_LVL, val); val 293 sound/soc/codecs/wm5110.c unsigned int val = snd_soc_component_read32(component, ARIZONA_DRE_ENABLE); val 299 sound/soc/codecs/wm5110.c if (val & ARIZONA_DRE1L_ENA_MASK) { val 309 sound/soc/codecs/wm5110.c if (val & ARIZONA_DRE1R_ENA_MASK) { val 329 sound/soc/codecs/wm5110.c unsigned int val = snd_soc_component_read32(component, ARIZONA_DRE_ENABLE); val 333 sound/soc/codecs/wm5110.c if (!(val & ARIZONA_DRE1L_ENA_MASK)) { val 345 sound/soc/codecs/wm5110.c if (!(val & ARIZONA_DRE1R_ENA_MASK)) { val 80 sound/soc/codecs/wm8350.c u16 reg, val; val 84 sound/soc/codecs/wm8350.c val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; val 88 sound/soc/codecs/wm8350.c if (val < out1->left_vol) { val 89 sound/soc/codecs/wm8350.c val++; val 92 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1L_VOL_SHIFT)); val 97 sound/soc/codecs/wm8350.c if (val > 0) { val 98 sound/soc/codecs/wm8350.c val--; val 101 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1L_VOL_SHIFT)); val 109 sound/soc/codecs/wm8350.c val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; val 112 sound/soc/codecs/wm8350.c if (val < out1->right_vol) { val 113 sound/soc/codecs/wm8350.c val++; val 116 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1R_VOL_SHIFT)); val 121 sound/soc/codecs/wm8350.c if (val > 0) { val 122 sound/soc/codecs/wm8350.c val--; val 125 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1R_VOL_SHIFT)); val 145 sound/soc/codecs/wm8350.c u16 reg, val; val 149 sound/soc/codecs/wm8350.c val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; val 152 sound/soc/codecs/wm8350.c if (val < out2->left_vol) { val 153 sound/soc/codecs/wm8350.c val++; val 156 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1L_VOL_SHIFT)); val 161 sound/soc/codecs/wm8350.c if (val > 0) { val 162 sound/soc/codecs/wm8350.c val--; val 165 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1L_VOL_SHIFT)); val 173 sound/soc/codecs/wm8350.c val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; val 176 sound/soc/codecs/wm8350.c if (val < out2->right_vol) { val 177 sound/soc/codecs/wm8350.c val++; val 180 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1R_VOL_SHIFT)); val 185 sound/soc/codecs/wm8350.c if (val > 0) { val 186 sound/soc/codecs/wm8350.c val--; val 189 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1R_VOL_SHIFT)); val 306 sound/soc/codecs/wm8350.c u16 val; val 334 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, reg); val 335 sound/soc/codecs/wm8350.c snd_soc_component_write(component, reg, val | WM8350_OUT1_VU); val 789 sound/soc/codecs/wm8350.c u16 val; val 793 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, WM8350_ADC_DIVIDER) & val 795 sound/soc/codecs/wm8350.c snd_soc_component_write(component, WM8350_ADC_DIVIDER, val | div); val 798 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, WM8350_DAC_CLOCK_CONTROL) & val 800 sound/soc/codecs/wm8350.c snd_soc_component_write(component, WM8350_DAC_CLOCK_CONTROL, val | div); val 803 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, WM8350_CLOCK_CONTROL_1) & val 805 sound/soc/codecs/wm8350.c snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div); val 808 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, WM8350_CLOCK_CONTROL_1) & val 810 sound/soc/codecs/wm8350.c snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div); val 813 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, WM8350_CLOCK_CONTROL_1) & val 815 sound/soc/codecs/wm8350.c snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div); val 818 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, WM8350_DAC_LR_RATE) & val 820 sound/soc/codecs/wm8350.c snd_soc_component_write(component, WM8350_DAC_LR_RATE, val | div); val 823 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, WM8350_ADC_LR_RATE) & val 825 sound/soc/codecs/wm8350.c snd_soc_component_write(component, WM8350_ADC_LR_RATE, val | div); val 948 sound/soc/codecs/wm8350.c unsigned int val; val 951 sound/soc/codecs/wm8350.c val = WM8350_DAC_MUTE_ENA; val 953 sound/soc/codecs/wm8350.c val = 0; val 955 sound/soc/codecs/wm8350.c snd_soc_component_update_bits(component, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val); val 94 sound/soc/codecs/wm8400.c u16 val; val 101 sound/soc/codecs/wm8400.c val = snd_soc_component_read32(component, reg); val 102 sound/soc/codecs/wm8400.c return snd_soc_component_write(component, reg, val | 0x0100); val 1110 sound/soc/codecs/wm8400.c u16 val = snd_soc_component_read32(component, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE; val 1113 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); val 1115 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_DAC_CTRL, val); val 1125 sound/soc/codecs/wm8400.c u16 val; val 1134 sound/soc/codecs/wm8400.c val = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1) & val 1136 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val | 0x2); val 1160 sound/soc/codecs/wm8400.c val = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1); val 1161 sound/soc/codecs/wm8400.c val |= 0x2 | WM8400_VREF_ENA; val 1162 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val); val 1174 sound/soc/codecs/wm8400.c val = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1) & val 1176 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val | 0x4); val 1190 sound/soc/codecs/wm8400.c val = snd_soc_component_read32(component, WM8400_DAC_CTRL); val 1191 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); val 1194 sound/soc/codecs/wm8400.c val = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1); val 1195 sound/soc/codecs/wm8400.c val |= WM8400_SPK_ENA | WM8400_OUT3_ENA | val 1198 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val); val 1201 sound/soc/codecs/wm8400.c val &= ~WM8400_VMID_MODE_MASK; val 1202 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val); val 1213 sound/soc/codecs/wm8400.c val &= ~WM8400_VREF_ENA; val 1214 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val); val 213 sound/soc/codecs/wm8523.c unsigned int val; val 220 sound/soc/codecs/wm8523.c val = freq / lrclk_ratios[i].ratio; val 225 sound/soc/codecs/wm8523.c switch (val) { val 239 sound/soc/codecs/wm8523.c val); val 240 sound/soc/codecs/wm8523.c wm8523->rate_constraint_list[i] = val; val 245 sound/soc/codecs/wm8523.c val); val 450 sound/soc/codecs/wm8523.c unsigned int val; val 482 sound/soc/codecs/wm8523.c ret = regmap_read(wm8523->regmap, WM8523_DEVICE_ID, &val); val 487 sound/soc/codecs/wm8523.c if (val != 0x8523) { val 493 sound/soc/codecs/wm8523.c ret = regmap_read(wm8523->regmap, WM8523_REVISION, &val); val 499 sound/soc/codecs/wm8523.c (val & WM8523_CHIP_REV_MASK) + 'A'); val 97 sound/soc/codecs/wm8524.c unsigned int val; val 104 sound/soc/codecs/wm8524.c val = freq / lrclk_ratios[i].ratio; val 109 sound/soc/codecs/wm8524.c switch (val) { val 119 sound/soc/codecs/wm8524.c val); val 120 sound/soc/codecs/wm8524.c wm8524->rate_constraint_list[j++] = val; val 125 sound/soc/codecs/wm8524.c val); val 91 sound/soc/codecs/wm8731.c int val, i, best; val 104 sound/soc/codecs/wm8731.c val = best << 1; val 107 sound/soc/codecs/wm8731.c val = 0; val 113 sound/soc/codecs/wm8731.c return snd_soc_component_update_bits(component, WM8731_APDIGI, 0x6, val); val 164 sound/soc/codecs/wm8804.c unsigned int val = ucontrol->value.enumerated.item[0] << e->shift_l; val 168 sound/soc/codecs/wm8804.c if (val != 0 && val != mask) val 173 sound/soc/codecs/wm8804.c if (snd_soc_component_test_bits(component, e->reg, mask, val)) { val 181 sound/soc/codecs/wm8804.c snd_soc_component_update_bits(component, e->reg, mask, val); val 294 sound/soc/codecs/wm8903.c int i, val; val 345 sound/soc/codecs/wm8903.c val = snd_soc_component_read32(component, val 348 sound/soc/codecs/wm8903.c 3 - i, val); val 349 sound/soc/codecs/wm8903.c wm8903->dcs_cache[i] = val; val 419 sound/soc/codecs/wm8903.c int val, i, best; val 432 sound/soc/codecs/wm8903.c val = best << WM8903_DEEMPH_SHIFT; val 435 sound/soc/codecs/wm8903.c val = 0; val 442 sound/soc/codecs/wm8903.c WM8903_DEEMPH_MASK, val); val 1786 sound/soc/codecs/wm8903.c unsigned int mask, val; val 1790 sound/soc/codecs/wm8903.c val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) | val 1794 sound/soc/codecs/wm8903.c WM8903_GPIO_CONTROL_1 + offset, mask, val); val 1815 sound/soc/codecs/wm8903.c unsigned int mask, val; val 1819 sound/soc/codecs/wm8903.c val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) | val 1823 sound/soc/codecs/wm8903.c WM8903_GPIO_CONTROL_1 + offset, mask, val); val 1992 sound/soc/codecs/wm8903.c unsigned int val, irq_pol; val 2053 sound/soc/codecs/wm8903.c ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val); val 2058 sound/soc/codecs/wm8903.c if (val != 0x8903) { val 2059 sound/soc/codecs/wm8903.c dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val); val 2064 sound/soc/codecs/wm8903.c ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val); val 2070 sound/soc/codecs/wm8903.c (val & WM8903_CHIP_REV_MASK) + 'A'); val 2086 sound/soc/codecs/wm8903.c val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK) val 2089 sound/soc/codecs/wm8903.c switch (val) { val 493 sound/soc/codecs/wm8904.c int val, i, best; val 506 sound/soc/codecs/wm8904.c val = best << WM8904_DEEMPH_SHIFT; val 508 sound/soc/codecs/wm8904.c val = 0; val 511 sound/soc/codecs/wm8904.c dev_dbg(component->dev, "Set deemphasis %d\n", val); val 514 sound/soc/codecs/wm8904.c WM8904_DEEMPH_MASK, val); val 559 sound/soc/codecs/wm8904.c unsigned int val; val 567 sound/soc/codecs/wm8904.c val = 0; val 569 sound/soc/codecs/wm8904.c val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5; val 573 sound/soc/codecs/wm8904.c val); val 696 sound/soc/codecs/wm8904.c int reg, val; val 779 sound/soc/codecs/wm8904.c val = snd_soc_component_read32(component, WM8904_DC_SERVO_READBACK_0); val 780 sound/soc/codecs/wm8904.c if ((val & dcs_mask) == dcs_mask) val 786 sound/soc/codecs/wm8904.c if ((val & dcs_mask) != dcs_mask) val 1694 sound/soc/codecs/wm8904.c int ret, val; val 1758 sound/soc/codecs/wm8904.c val = WM8904_FLL_FRC_NCO; val 1760 sound/soc/codecs/wm8904.c val = 0; val 1764 sound/soc/codecs/wm8904.c val); val 1786 sound/soc/codecs/wm8904.c val = WM8904_FLL_FRACN_ENA; val 1788 sound/soc/codecs/wm8904.c val = 0; val 1790 sound/soc/codecs/wm8904.c WM8904_FLL_FRACN_ENA, val); val 1830 sound/soc/codecs/wm8904.c int val; val 1833 sound/soc/codecs/wm8904.c val = WM8904_DAC_MUTE; val 1835 sound/soc/codecs/wm8904.c val = 0; val 1837 sound/soc/codecs/wm8904.c snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); val 2146 sound/soc/codecs/wm8904.c unsigned int val; val 2200 sound/soc/codecs/wm8904.c ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val); val 2205 sound/soc/codecs/wm8904.c if (val != 0x8904) { val 2206 sound/soc/codecs/wm8904.c dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val); val 2211 sound/soc/codecs/wm8904.c ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val); val 2217 sound/soc/codecs/wm8904.c dev_info(&i2c->dev, "revision %c\n", val + 'A'); val 470 sound/soc/codecs/wm8940.c u16 val; val 479 sound/soc/codecs/wm8940.c val = snd_soc_component_read32(component, WM8940_OUTPUTCTL); val 480 sound/soc/codecs/wm8940.c ret = snd_soc_component_write(component, WM8940_OUTPUTCTL, val | 0x2); val 245 sound/soc/codecs/wm8955.c int i, ret, val; val 309 sound/soc/codecs/wm8955.c val = WM8955_PLL_RB | WM8955_PLLOUTDIV2; val 311 sound/soc/codecs/wm8955.c val = WM8955_PLL_RB; val 315 sound/soc/codecs/wm8955.c WM8955_PLL_RB | WM8955_PLLOUTDIV2, val); val 363 sound/soc/codecs/wm8955.c int val, i, best; val 376 sound/soc/codecs/wm8955.c val = best << WM8955_DEEMPH_SHIFT; val 378 sound/soc/codecs/wm8955.c val = 0; val 381 sound/soc/codecs/wm8955.c dev_dbg(component->dev, "Set deemphasis %d\n", val); val 384 sound/soc/codecs/wm8955.c WM8955_DEEMPH_MASK, val); val 751 sound/soc/codecs/wm8955.c int val; val 754 sound/soc/codecs/wm8955.c val = WM8955_DACMU; val 756 sound/soc/codecs/wm8955.c val = 0; val 758 sound/soc/codecs/wm8955.c snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, WM8955_DACMU, val); val 171 sound/soc/codecs/wm8960.c int val, i, best; val 184 sound/soc/codecs/wm8960.c val = best << 1; val 186 sound/soc/codecs/wm8960.c val = 0; val 189 sound/soc/codecs/wm8960.c dev_dbg(component->dev, "Set deemphasis %d\n", val); val 192 sound/soc/codecs/wm8960.c 0x6, val); val 579 sound/soc/codecs/wm8960.c unsigned int val; val 855 sound/soc/codecs/wm8960.c alc_rates[i].val); val 471 sound/soc/codecs/wm8961.c u16 val; val 488 sound/soc/codecs/wm8961.c u16 val; val 526 sound/soc/codecs/wm8961.c reg |= wm8961_srate[best].val; val 559 sound/soc/codecs/wm8961.c reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT; val 917 sound/soc/codecs/wm8961.c unsigned int val; val 929 sound/soc/codecs/wm8961.c ret = regmap_read(wm8961->regmap, WM8961_SOFTWARE_RESET, &val); val 935 sound/soc/codecs/wm8961.c if (val != 0x1801) { val 936 sound/soc/codecs/wm8961.c dev_err(&i2c->dev, "Device is not a WM8961: ID=0x%x\n", val); val 942 sound/soc/codecs/wm8961.c ret = regmap_read(wm8961->regmap, WM8961_RIGHT_INPUT_VOLUME, &val); val 951 sound/soc/codecs/wm8961.c (val & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT, val 952 sound/soc/codecs/wm8961.c ((val & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT) val 1482 sound/soc/codecs/wm8962.c static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val) val 1494 sound/soc/codecs/wm8962.c snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val); val 2923 sound/soc/codecs/wm8962.c int val, ret; val 2926 sound/soc/codecs/wm8962.c val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT; val 2928 sound/soc/codecs/wm8962.c val = 0; val 2935 sound/soc/codecs/wm8962.c WM8962_DAC_MUTE_ALT, val); val 2940 sound/soc/codecs/wm8962.c WM8962_DAC_MUTE, val); val 3284 sound/soc/codecs/wm8962.c int val = 0; val 3291 sound/soc/codecs/wm8962.c val = 1 << WM8962_CLKOUT2_SEL_SHIFT; val 3295 sound/soc/codecs/wm8962.c val = 1 << WM8962_CLKOUT3_SEL_SHIFT; val 3303 sound/soc/codecs/wm8962.c mask, val); val 3344 sound/soc/codecs/wm8962.c int ret, val; val 3347 sound/soc/codecs/wm8962.c val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); val 3350 sound/soc/codecs/wm8962.c WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); val 136 sound/soc/codecs/wm8990.c u16 val; val 143 sound/soc/codecs/wm8990.c val = snd_soc_component_read32(component, reg); val 144 sound/soc/codecs/wm8990.c return snd_soc_component_write(component, reg, val | 0x0100); val 1091 sound/soc/codecs/wm8990.c u16 val; val 1093 sound/soc/codecs/wm8990.c val = snd_soc_component_read32(component, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; val 1096 sound/soc/codecs/wm8990.c snd_soc_component_write(component, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); val 1098 sound/soc/codecs/wm8990.c snd_soc_component_write(component, WM8990_DAC_CTRL, val); val 135 sound/soc/codecs/wm8991.c u16 val; val 142 sound/soc/codecs/wm8991.c val = snd_soc_component_read32(component, reg); val 143 sound/soc/codecs/wm8991.c return snd_soc_component_write(component, reg, val | 0x0100); val 1078 sound/soc/codecs/wm8991.c u16 val; val 1080 sound/soc/codecs/wm8991.c val = snd_soc_component_read32(component, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE; val 1082 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); val 1084 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_DAC_CTRL, val); val 1092 sound/soc/codecs/wm8991.c u16 val; val 1100 sound/soc/codecs/wm8991.c val = snd_soc_component_read32(component, WM8991_POWER_MANAGEMENT_1) & val 1102 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x2); val 1157 sound/soc/codecs/wm8991.c val = snd_soc_component_read32(component, WM8991_POWER_MANAGEMENT_1) & val 1159 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x4); val 1173 sound/soc/codecs/wm8991.c val = snd_soc_component_read32(component, WM8991_DAC_CTRL); val 1174 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); val 1271 sound/soc/codecs/wm8991.c unsigned int val; val 1284 sound/soc/codecs/wm8991.c ret = regmap_read(wm8991->regmap, WM8991_RESET, &val); val 1289 sound/soc/codecs/wm8991.c if (val != 0x8991) { val 1290 sound/soc/codecs/wm8991.c dev_err(&i2c->dev, "Device with ID %x is not a WM8991\n", val); val 1407 sound/soc/codecs/wm8993.c int mask, val, ret; val 1409 sound/soc/codecs/wm8993.c ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val); val 1424 sound/soc/codecs/wm8993.c val &= ~(mask | WM8993_IRQ); val 1425 sound/soc/codecs/wm8993.c if (!val) val 1428 sound/soc/codecs/wm8993.c if (val & WM8993_TEMPOK_EINT) val 1431 sound/soc/codecs/wm8993.c if (val & WM8993_FLL_LOCK_EINT) { val 1436 sound/soc/codecs/wm8993.c ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val); val 109 sound/soc/codecs/wm8994.c int best, i, sysclk, val; val 144 sound/soc/codecs/wm8994.c val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT val 153 sound/soc/codecs/wm8994.c WM8958_MICD_RATE_MASK, val); val 1051 sound/soc/codecs/wm8994.c int val; val 1068 sound/soc/codecs/wm8994.c val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_1); val 1069 sound/soc/codecs/wm8994.c if ((val & WM8994_AIF1ADCL_SRC) && val 1070 sound/soc/codecs/wm8994.c (val & WM8994_AIF1ADCR_SRC)) val 1072 sound/soc/codecs/wm8994.c else if (!(val & WM8994_AIF1ADCL_SRC) && val 1073 sound/soc/codecs/wm8994.c !(val & WM8994_AIF1ADCR_SRC)) val 1079 sound/soc/codecs/wm8994.c val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_2); val 1080 sound/soc/codecs/wm8994.c if ((val & WM8994_AIF1DACL_SRC) && val 1081 sound/soc/codecs/wm8994.c (val & WM8994_AIF1DACR_SRC)) val 1083 sound/soc/codecs/wm8994.c else if (!(val & WM8994_AIF1DACL_SRC) && val 1084 sound/soc/codecs/wm8994.c !(val & WM8994_AIF1DACR_SRC)) val 1125 sound/soc/codecs/wm8994.c val = snd_soc_component_read32(component, WM8994_CLOCKING_1); val 1126 sound/soc/codecs/wm8994.c if (val & WM8994_AIF2DSPCLK_ENA) val 1127 sound/soc/codecs/wm8994.c val = WM8994_SYSDSPCLK_ENA; val 1129 sound/soc/codecs/wm8994.c val = 0; val 1132 sound/soc/codecs/wm8994.c WM8994_AIF1DSPCLK_ENA, val); val 1146 sound/soc/codecs/wm8994.c int val; val 1150 sound/soc/codecs/wm8994.c val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_1); val 1151 sound/soc/codecs/wm8994.c if ((val & WM8994_AIF2ADCL_SRC) && val 1152 sound/soc/codecs/wm8994.c (val & WM8994_AIF2ADCR_SRC)) val 1154 sound/soc/codecs/wm8994.c else if (!(val & WM8994_AIF2ADCL_SRC) && val 1155 sound/soc/codecs/wm8994.c !(val & WM8994_AIF2ADCR_SRC)) val 1161 sound/soc/codecs/wm8994.c val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_2); val 1162 sound/soc/codecs/wm8994.c if ((val & WM8994_AIF2DACL_SRC) && val 1163 sound/soc/codecs/wm8994.c (val & WM8994_AIF2DACR_SRC)) val 1165 sound/soc/codecs/wm8994.c else if (!(val & WM8994_AIF2DACL_SRC) && val 1166 sound/soc/codecs/wm8994.c !(val & WM8994_AIF2DACR_SRC)) val 1210 sound/soc/codecs/wm8994.c val = snd_soc_component_read32(component, WM8994_CLOCKING_1); val 1211 sound/soc/codecs/wm8994.c if (val & WM8994_AIF1DSPCLK_ENA) val 1212 sound/soc/codecs/wm8994.c val = WM8994_SYSDSPCLK_ENA; val 1214 sound/soc/codecs/wm8994.c val = 0; val 1217 sound/soc/codecs/wm8994.c WM8994_AIF2DSPCLK_ENA, val); val 2746 sound/soc/codecs/wm8994.c int val, rate; val 2868 sound/soc/codecs/wm8994.c rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; val 3024 sound/soc/codecs/wm8994.c int reg, val, mask; val 3040 sound/soc/codecs/wm8994.c val = mask; val 3042 sound/soc/codecs/wm8994.c val = 0; val 3044 sound/soc/codecs/wm8994.c return snd_soc_component_update_bits(component, reg, mask, val); val 589 sound/soc/codecs/wm8995.c unsigned int reg, unsigned int val, unsigned int mask) val 594 sound/soc/codecs/wm8995.c __func__, reg, val, mask); val 596 sound/soc/codecs/wm8995.c snd_soc_component_write(component, reg, val); val 599 sound/soc/codecs/wm8995.c val = snd_soc_component_read32(component, WM8995_DC_SERVO_READBACK_0); val 600 sound/soc/codecs/wm8995.c if ((val & mask) == mask) val 1684 sound/soc/codecs/wm8995.c int reg, val, mask; val 1704 sound/soc/codecs/wm8995.c val = mask; val 1706 sound/soc/codecs/wm8995.c val = 0; val 1708 sound/soc/codecs/wm8995.c return snd_soc_component_update_bits(component, reg, mask, val); val 689 sound/soc/codecs/wm8996.c u16 val, mask; val 707 sound/soc/codecs/wm8996.c val = 0; val 710 sound/soc/codecs/wm8996.c val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; val 719 sound/soc/codecs/wm8996.c val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; val 727 sound/soc/codecs/wm8996.c snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1, mask, val); val 729 sound/soc/codecs/wm8996.c val = 0; val 732 sound/soc/codecs/wm8996.c val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; val 741 sound/soc/codecs/wm8996.c val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; val 749 sound/soc/codecs/wm8996.c snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_2, mask, val); val 2151 sound/soc/codecs/wm8996.c int val; val 2153 sound/soc/codecs/wm8996.c val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT); val 2157 sound/soc/codecs/wm8996.c WM8996_GP1_LVL, val); val 2287 sound/soc/codecs/wm8996.c int val, reg, report; val 2305 sound/soc/codecs/wm8996.c val = reg & WM8996_HP_LVL_MASK; val 2307 sound/soc/codecs/wm8996.c dev_dbg(component->dev, "HPDET measured %d ohms\n", val); val 2312 sound/soc/codecs/wm8996.c if (val >= 126) val 2384 sound/soc/codecs/wm8996.c int val, reg; val 2386 sound/soc/codecs/wm8996.c val = snd_soc_component_read32(component, WM8996_MIC_DETECT_3); val 2388 sound/soc/codecs/wm8996.c dev_dbg(component->dev, "Microphone event: %x\n", val); val 2390 sound/soc/codecs/wm8996.c if (!(val & WM8996_MICD_VALID)) { val 2396 sound/soc/codecs/wm8996.c if (!(val & WM8996_MICD_STS)) { val 2417 sound/soc/codecs/wm8996.c if (val & 0x400) { val 2444 sound/soc/codecs/wm8996.c if (wm8996->detecting && (val & 0x3f0)) { val 2472 sound/soc/codecs/wm8996.c if (val & 0x3fc) { val 2527 sound/soc/codecs/wm8996.c irqreturn_t val; val 2530 sound/soc/codecs/wm8996.c val = wm8996_irq(irq, data); val 2531 sound/soc/codecs/wm8996.c if (val != IRQ_NONE) val 2532 sound/soc/codecs/wm8996.c ret = val; val 2533 sound/soc/codecs/wm8996.c } while (val != IRQ_NONE); val 42 sound/soc/codecs/wm8998.c unsigned int val; val 46 sound/soc/codecs/wm8998.c val = snd_soc_component_read32(component, ARIZONA_ASRC_RATE1); val 47 sound/soc/codecs/wm8998.c val &= ARIZONA_ASRC_RATE1_MASK; val 48 sound/soc/codecs/wm8998.c val >>= ARIZONA_ASRC_RATE1_SHIFT; val 50 sound/soc/codecs/wm8998.c switch (val) { val 54 sound/soc/codecs/wm8998.c val = snd_soc_component_read32(component, val 55 sound/soc/codecs/wm8998.c ARIZONA_SAMPLE_RATE_1 + val); val 56 sound/soc/codecs/wm8998.c if (val >= 0x11) { val 59 sound/soc/codecs/wm8998.c arizona_sample_rate_val_to_name(val)); val 66 sound/soc/codecs/wm8998.c val); val 70 sound/soc/codecs/wm8998.c val = snd_soc_component_read32(component, ARIZONA_ASRC_RATE2); val 71 sound/soc/codecs/wm8998.c val &= ARIZONA_ASRC_RATE2_MASK; val 72 sound/soc/codecs/wm8998.c val >>= ARIZONA_ASRC_RATE2_SHIFT; val 74 sound/soc/codecs/wm8998.c switch (val) { val 77 sound/soc/codecs/wm8998.c val -= 0x8; val 78 sound/soc/codecs/wm8998.c val = snd_soc_component_read32(component, val 79 sound/soc/codecs/wm8998.c ARIZONA_ASYNC_SAMPLE_RATE_1 + val); val 80 sound/soc/codecs/wm8998.c if (val >= 0x11) { val 83 sound/soc/codecs/wm8998.c arizona_sample_rate_val_to_name(val)); val 90 sound/soc/codecs/wm8998.c val); val 221 sound/soc/codecs/wm9712.c unsigned int val = ucontrol->value.integer.value[0]; val 246 sound/soc/codecs/wm9712.c update.val = 0x0; val 248 sound/soc/codecs/wm9712.c update.val = 0x8000; val 250 sound/soc/codecs/wm9712.c snd_soc_dapm_mixer_update_power(dapm, kcontrol, val, val 230 sound/soc/codecs/wm9713.c unsigned int val = ucontrol->value.integer.value[0]; val 255 sound/soc/codecs/wm9713.c update.val = 0x0; val 257 sound/soc/codecs/wm9713.c update.val = 0x8000; val 259 sound/soc/codecs/wm9713.c snd_soc_dapm_mixer_update_power(dapm, kcontrol, val, val 974 sound/soc/codecs/wm_adsp.c u32 val = cpu_to_be32(event_id); val 986 sound/soc/codecs/wm_adsp.c ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); val 1010 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); val 1016 sound/soc/codecs/wm_adsp.c if (val == 0) { val 1117 sound/soc/codecs/wm_adsp.c unsigned int val = ucontrol->value.integer.value[0]; val 1120 sound/soc/codecs/wm_adsp.c if (val == 0) val 1126 sound/soc/codecs/wm_adsp.c ret = wm_coeff_write_acked_control(ctl, val); val 1561 sound/soc/codecs/wm_adsp.c int val = 0; val 1565 sound/soc/codecs/wm_adsp.c val = le16_to_cpu(*((__le16 *)*pos)); val 1568 sound/soc/codecs/wm_adsp.c val = le32_to_cpu(*((__le32 *)*pos)); val 1576 sound/soc/codecs/wm_adsp.c return val; val 2019 sound/soc/codecs/wm_adsp.c __be32 val; val 2034 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); val 2041 sound/soc/codecs/wm_adsp.c if (be32_to_cpu(val) != 0xbedead) val 2043 sound/soc/codecs/wm_adsp.c reg, be32_to_cpu(val)); val 2707 sound/soc/codecs/wm_adsp.c unsigned int val; val 2723 sound/soc/codecs/wm_adsp.c ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); val 2730 sound/soc/codecs/wm_adsp.c val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; val 2734 sound/soc/codecs/wm_adsp.c ADSP1_CLK_SEL_MASK, val); val 2815 sound/soc/codecs/wm_adsp.c unsigned int val; val 2820 sound/soc/codecs/wm_adsp.c ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); val 2824 sound/soc/codecs/wm_adsp.c if (val & ADSP2_RAM_RDY) val 2830 sound/soc/codecs/wm_adsp.c if (!(val & ADSP2_RAM_RDY)) { val 3750 sound/soc/codecs/wm_adsp.c unsigned int val, reg; val 3758 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val)); val 3762 sound/soc/codecs/wm_adsp.c if (val) val 3768 sound/soc/codecs/wm_adsp.c if (!val) { val 3778 sound/soc/codecs/wm_adsp.c buf->host_buf_ptr = be32_to_cpu(val); val 3799 sound/soc/codecs/wm_adsp.c val = coeff_v1.versions & HOST_BUF_COEFF_COMPAT_VER_MASK; val 3800 sound/soc/codecs/wm_adsp.c val >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT; val 3802 sound/soc/codecs/wm_adsp.c if (val > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) { val 3805 sound/soc/codecs/wm_adsp.c val, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER); val 3820 sound/soc/codecs/wm_adsp.c buf->host_buf_ptr, val); val 3822 sound/soc/codecs/wm_adsp.c return val; val 4252 sound/soc/codecs/wm_adsp.c unsigned int val; val 4258 sound/soc/codecs/wm_adsp.c ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); val 4265 sound/soc/codecs/wm_adsp.c if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { val 4271 sound/soc/codecs/wm_adsp.c if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { val 4272 sound/soc/codecs/wm_adsp.c if (val & ADSP2_SLAVE_ERR_MASK) val 4277 sound/soc/codecs/wm_adsp.c ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); val 4286 sound/soc/codecs/wm_adsp.c val & ADSP2_BUS_ERR_ADDR_MASK); val 4290 sound/soc/codecs/wm_adsp.c &val); val 4299 sound/soc/codecs/wm_adsp.c val & ADSP2_XMEM_ERR_ADDR_MASK); val 4301 sound/soc/codecs/wm_adsp.c (val & ADSP2_PMEM_ERR_ADDR_MASK) >> val 65 sound/soc/codecs/wm_hubs.c unsigned int val; val 67 sound/soc/codecs/wm_hubs.c val = op | WM8993_DCS_ENA_CHAN_0 | WM8993_DCS_ENA_CHAN_1; val 70 sound/soc/codecs/wm_hubs.c snd_soc_component_write(component, WM8993_DC_SERVO_0, val); val 1241 sound/soc/codecs/wm_hubs.c int val = 0; val 1244 sound/soc/codecs/wm_hubs.c val |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA; val 1247 sound/soc/codecs/wm_hubs.c val |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA; val 1250 sound/soc/codecs/wm_hubs.c snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_3, val, val); val 1258 sound/soc/codecs/wm_hubs.c int mask, val; val 1269 sound/soc/codecs/wm_hubs.c val = 0; val 1279 sound/soc/codecs/wm_hubs.c val |= WM8993_LINEOUT1N_ENA; val 1282 sound/soc/codecs/wm_hubs.c val |= WM8993_LINEOUT1P_ENA; val 1285 sound/soc/codecs/wm_hubs.c val |= WM8993_LINEOUT2N_ENA; val 1288 sound/soc/codecs/wm_hubs.c val |= WM8993_LINEOUT2P_ENA; val 1291 sound/soc/codecs/wm_hubs.c mask, val); val 278 sound/soc/codecs/zx_aud96p22.c unsigned int val; val 283 sound/soc/codecs/zx_aud96p22.c val = 0; val 286 sound/soc/codecs/zx_aud96p22.c val = I2S1_MS_MODE; val 292 sound/soc/codecs/zx_aud96p22.c regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MS_MODE, val); val 297 sound/soc/codecs/zx_aud96p22.c val = I2S1_MODE_RIGHT_J; val 300 sound/soc/codecs/zx_aud96p22.c val = I2S1_MODE_I2S; val 303 sound/soc/codecs/zx_aud96p22.c val = I2S1_MODE_LEFT_J; val 309 sound/soc/codecs/zx_aud96p22.c regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MODE_MASK, val); val 29 sound/soc/dwc/dwc-i2s.c static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) val 31 sound/soc/dwc/dwc-i2s.c writel(val, io_base + reg); val 118 sound/soc/fsl/fsl_audmix.c unsigned int reg_val, val, mix_clk; val 128 sound/soc/fsl/fsl_audmix.c val = snd_soc_enum_item_to_val(e, item[0]); val 130 sound/soc/fsl/fsl_audmix.c dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val); val 143 sound/soc/fsl/fsl_audmix.c if (!(priv->tdms & BIT(val))) { val 146 sound/soc/fsl/fsl_audmix.c val + 1); val 161 sound/soc/fsl/fsl_audmix.c unsigned int reg_val, val, mask = 0, ctr = 0; val 176 sound/soc/fsl/fsl_audmix.c val = snd_soc_enum_item_to_val(e, item[0]); val 178 sound/soc/fsl/fsl_audmix.c dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val); val 181 sound/soc/fsl/fsl_audmix.c if (out_src == val) val 195 sound/soc/fsl/fsl_audmix.c ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]); val 201 sound/soc/fsl/fsl_audmix.c ctr |= FSL_AUDMIX_CTR_OUTSRC(val); val 514 sound/soc/fsl/fsl_esai.c u32 bclk, mask, val; val 528 sound/soc/fsl/fsl_esai.c val = ESAI_xCR_xSWS(slot_width, width); val 530 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); val 533 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val); val 545 sound/soc/fsl/fsl_esai.c val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | val 548 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); val 396 sound/soc/fsl/fsl_micfil.c unsigned int val; val 418 sound/soc/fsl/fsl_micfil.c val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1; val 421 sound/soc/fsl/fsl_micfil.c val); val 148 sound/soc/fsl/fsl_spdif.c u32 *pos, size, val, reg; val 175 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, reg, &val); val 176 sound/soc/fsl/fsl_spdif.c ctrl->subcode[*pos++] = val >> 16; val 177 sound/soc/fsl/fsl_spdif.c ctrl->subcode[*pos++] = val >> 8; val 178 sound/soc/fsl/fsl_spdif.c ctrl->subcode[*pos++] = val; val 203 sound/soc/fsl/fsl_spdif.c u32 val; val 208 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, REG_SPDIF_SRU, &val); val 209 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, REG_SPDIF_SRQ, &val); val 221 sound/soc/fsl/fsl_spdif.c u32 val, val2; val 223 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, REG_SPDIF_SIS, &val); val 226 sound/soc/fsl/fsl_spdif.c regmap_write(regmap, REG_SPDIF_SIC, val & val2); val 228 sound/soc/fsl/fsl_spdif.c return val; val 301 sound/soc/fsl/fsl_spdif.c u32 val, cycle = 1000; val 312 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, REG_SPDIF_SCR, &val); val 313 sound/soc/fsl/fsl_spdif.c } while ((val & SCR_SOFT_RESET) && cycle--); val 692 sound/soc/fsl/fsl_spdif.c u32 cstatus, val; val 694 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, REG_SPDIF_SIS, &val); val 695 sound/soc/fsl/fsl_spdif.c if (!(val & INT_CNEW)) val 790 sound/soc/fsl/fsl_spdif.c u32 val; val 792 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, REG_SPDIF_SIS, &val); val 793 sound/soc/fsl/fsl_spdif.c ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; val 889 sound/soc/fsl/fsl_spdif.c u32 val; val 891 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, REG_SPDIF_SRCD, &val); val 892 sound/soc/fsl/fsl_spdif.c ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; val 908 sound/soc/fsl/fsl_spdif.c u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; val 910 sound/soc/fsl/fsl_spdif.c regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); val 1016 sound/soc/fsl/fsl_ssi.c u32 val; val 1036 sound/soc/fsl/fsl_ssi.c regmap_read(regs, REG_SSI_SCR, &val); val 1044 sound/soc/fsl/fsl_ssi.c regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val); val 1163 sound/soc/fsl/fsl_ssi.c unsigned short val) val 1185 sound/soc/fsl/fsl_ssi.c lval = val << 4; val 1202 sound/soc/fsl/fsl_ssi.c unsigned short val = 0; val 1223 sound/soc/fsl/fsl_ssi.c val = (reg_val >> 4) & 0xffff; val 1229 sound/soc/fsl/fsl_ssi.c return val; val 251 sound/soc/fsl/imx-audmux.c unsigned int val; val 268 sound/soc/fsl/imx-audmux.c "fsl,port-config", i, &val)) == 0; val 272 sound/soc/fsl/imx-audmux.c pdcr |= val; val 274 sound/soc/fsl/imx-audmux.c ptcr |= val; val 276 sound/soc/fsl/imx-audmux.c pcr |= val; val 342 sound/soc/fsl/imx-ssi.c uint32_t val; val 346 sound/soc/fsl/imx-ssi.c val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.maxburst) | val 348 sound/soc/fsl/imx-ssi.c writel(val, ssi->base + SSI_SFCSR); val 431 sound/soc/fsl/imx-ssi.c unsigned short val) val 441 sound/soc/fsl/imx-ssi.c pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val); val 446 sound/soc/fsl/imx-ssi.c lval = val << 4; val 459 sound/soc/fsl/imx-ssi.c unsigned short val = -1; val 468 sound/soc/fsl/imx-ssi.c val = (readl(base + SSI_SACDAT) >> 4) & 0xffff; val 470 sound/soc/fsl/imx-ssi.c pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val); val 472 sound/soc/fsl/imx-ssi.c return val; val 33 sound/soc/fsl/mpc5200_psc_ac97.c unsigned int val; val 62 sound/soc/fsl/mpc5200_psc_ac97.c val = in_be32(&psc_dma->psc_regs->ac97_data); val 63 sound/soc/fsl/mpc5200_psc_ac97.c if (((val >> 24) & 0x7f) != reg) { val 68 sound/soc/fsl/mpc5200_psc_ac97.c val = (val >> 8) & 0xffff; val 71 sound/soc/fsl/mpc5200_psc_ac97.c return (unsigned short) val; val 75 sound/soc/fsl/mpc5200_psc_ac97.c unsigned short reg, unsigned short val) val 90 sound/soc/fsl/mpc5200_psc_ac97.c ((reg & 0x7f) << 24) | (val << 8)); val 166 sound/soc/generic/simple-card-utils.c u32 val; val 179 sound/soc/generic/simple-card-utils.c } else if (!of_property_read_u32(node, "system-clock-frequency", &val)) { val 180 sound/soc/generic/simple-card-utils.c simple_dai->sysclk = val; val 81 sound/soc/hisilicon/hi6210-i2s.c static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val) val 83 sound/soc/hisilicon/hi6210-i2s.c writel(val, i2s->base + reg); val 96 sound/soc/hisilicon/hi6210-i2s.c u32 val; val 99 sound/soc/hisilicon/hi6210-i2s.c regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val); val 100 sound/soc/hisilicon/hi6210-i2s.c if (val & BIT(4)) val 130 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK); val 131 sound/soc/hisilicon/hi6210-i2s.c val |= 0x3f; val 132 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val); val 136 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1); val 137 sound/soc/hisilicon/hi6210-i2s.c val |= (BIT(5) | BIT(4)); val 138 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val); val 140 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1); val 141 sound/soc/hisilicon/hi6210-i2s.c val &= ~(BIT(5) | BIT(4)); val 142 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val); val 145 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_SW_RST_N); val 146 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK << val 148 sound/soc/hisilicon/hi6210-i2s.c val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT); val 149 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_SW_RST_N, val); val 151 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_MISC_CFG); val 153 sound/soc/hisilicon/hi6210-i2s.c val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL; val 155 sound/soc/hisilicon/hi6210-i2s.c val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL; val 156 sound/soc/hisilicon/hi6210-i2s.c val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL; val 158 sound/soc/hisilicon/hi6210-i2s.c val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL; val 160 sound/soc/hisilicon/hi6210-i2s.c val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL; val 161 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_MISC_CFG, val); val 163 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_SW_RST_N); val 164 sound/soc/hisilicon/hi6210-i2s.c val |= HII2S_SW_RST_N__SW_RST_N; val 165 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_SW_RST_N, val); val 185 sound/soc/hisilicon/hi6210-i2s.c u32 val; val 190 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 191 sound/soc/hisilicon/hi6210-i2s.c val |= HII2S_I2S_CFG__S2_IF_TX_EN; val 192 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 195 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 196 sound/soc/hisilicon/hi6210-i2s.c val &= ~HII2S_I2S_CFG__S2_IF_TX_EN; val 197 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 205 sound/soc/hisilicon/hi6210-i2s.c u32 val; val 209 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 210 sound/soc/hisilicon/hi6210-i2s.c val |= HII2S_I2S_CFG__S2_IF_RX_EN; val 211 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 213 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 214 sound/soc/hisilicon/hi6210-i2s.c val &= ~HII2S_I2S_CFG__S2_IF_RX_EN; val 215 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 258 sound/soc/hisilicon/hi6210-i2s.c u32 val; val 325 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG); val 326 sound/soc/hisilicon/hi6210-i2s.c val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK << val 334 sound/soc/hisilicon/hi6210-i2s.c val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) | val 338 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val); val 341 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG); val 342 sound/soc/hisilicon/hi6210-i2s.c val |= (BIT(19) | BIT(18) | BIT(17) | val 348 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val); val 351 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG); val 352 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN | val 358 sound/soc/hisilicon/hi6210-i2s.c val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN | val 360 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val); val 363 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG); val 364 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE | val 366 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val); val 368 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG); val 369 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE | val 373 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val); val 379 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 380 sound/soc/hisilicon/hi6210-i2s.c val |= HII2S_I2S_CFG__S2_MST_SLV; val 381 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 385 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 386 sound/soc/hisilicon/hi6210-i2s.c val &= ~HII2S_I2S_CFG__S2_MST_SLV; val 387 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 409 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 410 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK << val 412 sound/soc/hisilicon/hi6210-i2s.c val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT; val 413 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 416 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_CLK_SEL); val 417 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */ val 419 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_CLK_SEL, val); val 430 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 431 sound/soc/hisilicon/hi6210-i2s.c val |= HII2S_I2S_CFG__S2_FRAME_MODE; val 432 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 435 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 436 sound/soc/hisilicon/hi6210-i2s.c val &= ~HII2S_I2S_CFG__S2_FRAME_MODE; val 437 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 442 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_I2S_CFG); val 443 sound/soc/hisilicon/hi6210-i2s.c val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT; val 444 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK << val 446 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK << val 448 sound/soc/hisilicon/hi6210-i2s.c val |= signed_data; val 449 sound/soc/hisilicon/hi6210-i2s.c val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT); val 450 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_I2S_CFG, val); val 457 sound/soc/hisilicon/hi6210-i2s.c val = hi6210_read_reg(i2s, HII2S_FS_CFG); val 458 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT); val 459 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT); val 460 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK << val 462 sound/soc/hisilicon/hi6210-i2s.c val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK << val 464 sound/soc/hisilicon/hi6210-i2s.c val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT); val 465 sound/soc/hisilicon/hi6210-i2s.c val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT); val 466 sound/soc/hisilicon/hi6210-i2s.c val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT); val 467 sound/soc/hisilicon/hi6210-i2s.c val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT); val 468 sound/soc/hisilicon/hi6210-i2s.c hi6210_write_reg(i2s, HII2S_FS_CFG, val); val 88 sound/soc/img/img-i2s-in.c static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg) val 90 sound/soc/img/img-i2s-in.c writel(val, i2s->base + reg); val 99 sound/soc/img/img-i2s-in.c u32 val, u32 reg) val 101 sound/soc/img/img-i2s-in.c writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg); val 98 sound/soc/img/img-i2s-out.c static inline void img_i2s_out_writel(struct img_i2s_out *i2s, u32 val, val 101 sound/soc/img/img-i2s-out.c writel(val, i2s->base + reg); val 110 sound/soc/img/img-i2s-out.c u32 chan, u32 val, u32 reg) val 112 sound/soc/img/img-i2s-out.c writel(val, i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg); val 68 sound/soc/img/img-parallel-out.c u32 val, u32 reg) val 70 sound/soc/img/img-parallel-out.c writel(val, prl->base + reg); val 114 sound/soc/img/img-spdif-in.c u32 val, u32 reg) val 116 sound/soc/img/img-spdif-in.c writel(val, spdif->base + reg); val 83 sound/soc/img/img-spdif-out.c static inline void img_spdif_out_writel(struct img_spdif_out *spdif, u32 val, val 86 sound/soc/img/img-spdif-out.c writel(val, spdif->base + reg); val 64 sound/soc/img/pistachio-internal-dac.c u32 val, u32 reg) val 72 sound/soc/img/pistachio-internal-dac.c val << PISTACHIO_INTERNAL_DAC_GTI_CTRL_WDATA_SHIFT); val 159 sound/soc/intel/atom/sst-atom-controls.c unsigned int val, mux; val 163 sound/soc/intel/atom/sst-atom-controls.c val = 1 << ctl_no; val 166 sound/soc/intel/atom/sst-atom-controls.c if (map[mux - 1] & val) val 219 sound/soc/intel/atom/sst-atom-controls.c unsigned int val, mux; val 224 sound/soc/intel/atom/sst-atom-controls.c val = 1 << ctl_no; val 232 sound/soc/intel/atom/sst-atom-controls.c map[i] &= ~val; val 244 sound/soc/intel/atom/sst-atom-controls.c map[slot_channel_no] |= val; val 613 sound/soc/intel/atom/sst-atom-controls.c int val = 0; val 624 sound/soc/intel/atom/sst-atom-controls.c val |= 1 << mc->shift; val 627 sound/soc/intel/atom/sst-atom-controls.c dev_dbg(cmpnt->dev, "val = %#x\n", val); val 657 sound/soc/intel/atom/sst-atom-controls.c cmd.nb_inputs = fill_swm_input(cmpnt, &cmd.input[0], val); val 44 sound/soc/intel/atom/sst/sst_pvt.c u64 val = 0; val 46 sound/soc/intel/atom/sst/sst_pvt.c memcpy_fromio(&val, addr + offset, sizeof(val)); val 48 sound/soc/intel/atom/sst/sst_pvt.c return val; val 59 sound/soc/intel/atom/sst/sst_pvt.c u64 val = 0; val 61 sound/soc/intel/atom/sst/sst_pvt.c memcpy_fromio(&val, addr + offset, sizeof(val)); val 62 sound/soc/intel/atom/sst/sst_pvt.c return val; val 43 sound/soc/intel/common/sst-dsp.c u64 val; val 45 sound/soc/intel/common/sst-dsp.c memcpy_fromio(&val, addr + offset, sizeof(val)); val 46 sound/soc/intel/common/sst-dsp.c return val; val 96 sound/soc/intel/common/sst-dsp.c u32 val; val 99 sound/soc/intel/common/sst-dsp.c val = sst->ops->read(sst->addr.shim, offset); val 102 sound/soc/intel/common/sst-dsp.c return val; val 119 sound/soc/intel/common/sst-dsp.c u64 val; val 122 sound/soc/intel/common/sst-dsp.c val = sst->ops->read64(sst->addr.shim, offset); val 125 sound/soc/intel/common/sst-dsp.c return val; val 248 sound/soc/intel/haswell/sst-haswell-dsp.c u32 val; val 257 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_VDRTCTL0); val 258 sound/soc/intel/haswell/sst-haswell-dsp.c val |= SST_VDRTCL0_DSRAMPGE_MASK | val 260 sound/soc/intel/haswell/sst-haswell-dsp.c val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD); val 261 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val, sst->addr.pci_cfg + SST_VDRTCTL0); val 264 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_VDRTCTL2); val 265 sound/soc/intel/haswell/sst-haswell-dsp.c val |= SST_VDRTCL2_APLLSE_MASK; val 266 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val, sst->addr.pci_cfg + SST_VDRTCTL2); val 273 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_PMCS); val 274 sound/soc/intel/haswell/sst-haswell-dsp.c val |= SST_PMCS_PS_MASK; val 275 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val, sst->addr.pci_cfg + SST_PMCS); val 537 sound/soc/intel/haswell/sst-haswell-dsp.c u32 bit, val; val 546 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_VDRTCTL2); val 547 sound/soc/intel/haswell/sst-haswell-dsp.c val &= ~SST_VDRTCL2_DCLCGE; val 548 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val, sst->addr.pci_cfg + SST_VDRTCTL2); val 550 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_VDRTCTL0); val 552 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0); val 558 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_VDRTCTL2); val 559 sound/soc/intel/haswell/sst-haswell-dsp.c val |= SST_VDRTCL2_DCLCGE; val 560 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val, sst->addr.pci_cfg + SST_VDRTCTL2); val 573 sound/soc/intel/haswell/sst-haswell-dsp.c u32 bit, val; val 582 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_VDRTCTL2); val 583 sound/soc/intel/haswell/sst-haswell-dsp.c val &= ~SST_VDRTCL2_DCLCGE; val 584 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val, sst->addr.pci_cfg + SST_VDRTCTL2); val 587 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_VDRTCTL0); val 591 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0); val 597 sound/soc/intel/haswell/sst-haswell-dsp.c val = readl(sst->addr.pci_cfg + SST_VDRTCTL2); val 598 sound/soc/intel/haswell/sst-haswell-dsp.c val |= SST_VDRTCL2_DCLCGE; val 599 sound/soc/intel/haswell/sst-haswell-dsp.c writel(val, sst->addr.pci_cfg + SST_VDRTCTL2); val 1224 sound/soc/intel/haswell/sst-haswell-ipc.c struct sst_hsw_stream *stream, snd_pcm_uframes_t val) val 1226 sound/soc/intel/haswell/sst-haswell-ipc.c stream->old_position = val; val 1236 sound/soc/intel/haswell/sst-haswell-ipc.c struct sst_hsw_stream *stream, bool val) val 1238 sound/soc/intel/haswell/sst-haswell-ipc.c stream->play_silence = val; val 456 sound/soc/intel/haswell/sst-haswell-ipc.h struct sst_hsw_stream *stream, snd_pcm_uframes_t val); val 460 sound/soc/intel/haswell/sst-haswell-ipc.h struct sst_hsw_stream *stream, bool val); val 61 sound/soc/intel/skylake/cnl-sst-dsp.c int val; val 64 sound/soc/intel/skylake/cnl-sst-dsp.c val = sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPCS); val 66 sound/soc/intel/skylake/cnl-sst-dsp.c is_enable = (val & CNL_ADSPCS_CPA(core_mask)) && val 67 sound/soc/intel/skylake/cnl-sst-dsp.c (val & CNL_ADSPCS_SPA(core_mask)) && val 68 sound/soc/intel/skylake/cnl-sst-dsp.c !(val & CNL_ADSPCS_CRST(core_mask)) && val 69 sound/soc/intel/skylake/cnl-sst-dsp.c !(val & CNL_ADSPCS_CSTALL(core_mask)); val 187 sound/soc/intel/skylake/cnl-sst-dsp.c u32 val; val 192 sound/soc/intel/skylake/cnl-sst-dsp.c val = sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPIS); val 193 sound/soc/intel/skylake/cnl-sst-dsp.c ctx->intr_status = val; val 195 sound/soc/intel/skylake/cnl-sst-dsp.c if (val == 0xffffffff) { val 200 sound/soc/intel/skylake/cnl-sst-dsp.c if (val & CNL_ADSPIS_IPC) { val 522 sound/soc/intel/skylake/skl-messages.c node_id.node.vindex = ssp_node.val; val 548 sound/soc/intel/skylake/skl-messages.c node_id.val = 0xFFFFFFFF; val 552 sound/soc/intel/skylake/skl-messages.c return node_id.val; val 30 sound/soc/intel/skylake/skl-sst-cldma.c unsigned char val; val 41 sound/soc/intel/skylake/skl-sst-cldma.c val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) & val 43 sound/soc/intel/skylake/skl-sst-cldma.c if (enable && val) val 45 sound/soc/intel/skylake/skl-sst-cldma.c else if (!enable && !val) val 51 sound/soc/intel/skylake/skl-sst-cldma.c dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable); val 53 sound/soc/intel/skylake/skl-sst-dsp.c u32 val; val 57 sound/soc/intel/skylake/skl-sst-dsp.c val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS); val 60 sound/soc/intel/skylake/skl-sst-dsp.c en_cores_mask = (val & SKL_ADSPCS_CPA_MASK(core_mask)) >> val 64 sound/soc/intel/skylake/skl-sst-dsp.c en_cores_mask &= (~val & SKL_ADSPCS_CRST_MASK(core_mask)) >> val 68 sound/soc/intel/skylake/skl-sst-dsp.c en_cores_mask &= (~val & SKL_ADSPCS_CSTALL_MASK(core_mask)) >> val 137 sound/soc/intel/skylake/skl-sst-dsp.c int val; val 140 sound/soc/intel/skylake/skl-sst-dsp.c val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS); val 142 sound/soc/intel/skylake/skl-sst-dsp.c is_enable = ((val & SKL_ADSPCS_CPA_MASK(core_mask)) && val 143 sound/soc/intel/skylake/skl-sst-dsp.c (val & SKL_ADSPCS_SPA_MASK(core_mask)) && val 144 sound/soc/intel/skylake/skl-sst-dsp.c !(val & SKL_ADSPCS_CRST_MASK(core_mask)) && val 145 sound/soc/intel/skylake/skl-sst-dsp.c !(val & SKL_ADSPCS_CSTALL_MASK(core_mask))); val 305 sound/soc/intel/skylake/skl-sst-dsp.c u32 val; val 310 sound/soc/intel/skylake/skl-sst-dsp.c val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPIS); val 311 sound/soc/intel/skylake/skl-sst-dsp.c ctx->intr_status = val; val 313 sound/soc/intel/skylake/skl-sst-dsp.c if (val == 0xffffffff) { val 318 sound/soc/intel/skylake/skl-sst-dsp.c if (val & SKL_ADSPIS_IPC) { val 323 sound/soc/intel/skylake/skl-sst-dsp.c if (val & SKL_ADSPIS_CL_DMA) { val 115 sound/soc/intel/skylake/skl-sst-utils.c static inline int skl_getid_32(struct uuid_module *module, u64 *val, val 122 sound/soc/intel/skylake/skl-sst-utils.c mask_val = (u32)(*val >> word1_mask); val 128 sound/soc/intel/skylake/skl-sst-utils.c *val |= 1ULL << (index + word1_mask); val 2120 sound/soc/intel/skylake/skl-topology.c u32 tkn, u32 val, u32 dir, int fmt_idx) val 2141 sound/soc/intel/skylake/skl-topology.c return skl_tplg_fill_fmt(dev, dst_fmt, tkn, val); val 176 sound/soc/intel/skylake/skl-topology.h u8 val; val 184 sound/soc/intel/skylake/skl-topology.h u32 val; val 45 sound/soc/intel/skylake/skl.c unsigned char mask, unsigned char val) val 51 sound/soc/intel/skylake/skl.c data |= (val & mask); val 71 sound/soc/intel/skylake/skl.c unsigned int reg, u32 mask, u32 val) val 77 sound/soc/intel/skylake/skl.c data |= (val & mask); val 90 sound/soc/intel/skylake/skl.c u32 val; val 92 sound/soc/intel/skylake/skl.c val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; val 94 sound/soc/intel/skylake/skl.c update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); val 107 sound/soc/intel/skylake/skl.c u32 val; val 110 sound/soc/intel/skylake/skl.c val = enable ? AZX_CGCTL_ADSPDCGE : 0; val 111 sound/soc/intel/skylake/skl.c update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); val 114 sound/soc/intel/skylake/skl.c val = enable ? AZX_REG_VS_EM2_L1SEN : 0; val 115 sound/soc/intel/skylake/skl.c snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); val 118 sound/soc/intel/skylake/skl.c val = enable ? 0 : AZX_PGCTL_ADSPPGD; val 119 sound/soc/intel/skylake/skl.c update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); val 21 sound/soc/mediatek/common/mtk-afe-fe-dai.c unsigned int val, int shift) val 25 sound/soc/mediatek/common/mtk-afe-fe-dai.c return regmap_update_bits(map, reg, mask << shift, val << shift); val 28 sound/soc/mediatek/common/mtk-afe-fe-dai.c static int mtk_regmap_write(struct regmap *map, int reg, unsigned int val) val 32 sound/soc/mediatek/common/mtk-afe-fe-dai.c return regmap_write(map, reg, val); val 87 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c int val = num - MT2701_IO_I2S; val 89 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c if (val < 0 || val >= afe_priv->soc->i2s_num) { val 91 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c __func__, num, val); val 94 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c return val; val 180 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c unsigned int mask, val; val 193 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c val = ASYS_I2S_CON_FS_SET(fs) | val 199 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c val |= ASYS_I2S_IN_PHASE_FIX; val 204 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c val |= ASYS_I2S_CON_ONE_HEART_MODE; val 209 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val); val 309 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c u32 val, msk; val 322 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY val 324 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c msk = val; val 327 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN; val 331 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val); val 198 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c unsigned int val; val 209 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val = AFE_I2S_CON2_LOW_JITTER_CLK | val 213 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val); val 216 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val = AFE_I2S_CON1_LOW_JITTER_CLK | val 220 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val); val 226 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c unsigned int val; val 228 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c regmap_read(afe->regmap, AFE_I2S_CON2, &val); val 229 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c if (!!(val & AFE_I2S_CON2_EN) == enable) val 378 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c unsigned int val; val 385 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val = AFE_TDM_CON1_BCK_INV | val 392 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val); val 398 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val = AFE_TDM_CH_START_O30_O31; val 399 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_ZERO << 4); val 400 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_ZERO << 8); val 401 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_ZERO << 12); val 405 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val = AFE_TDM_CH_START_O30_O31; val 406 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_START_O32_O33 << 4); val 407 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_ZERO << 8); val 408 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_ZERO << 12); val 412 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val = AFE_TDM_CH_START_O30_O31; val 413 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_START_O32_O33 << 4); val 414 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_START_O34_O35 << 8); val 415 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_ZERO << 12); val 419 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val = AFE_TDM_CH_START_O30_O31; val 420 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_START_O32_O33 << 4); val 421 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_START_O34_O35 << 8); val 422 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val |= (AFE_TDM_CH_START_O36_O37 << 12); val 425 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c val = 0; val 427 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val); val 116 sound/soc/meson/axg-pdm.c unsigned int val = enable ? PDM_FILTER_EN : 0; val 118 sound/soc/meson/axg-pdm.c regmap_update_bits(map, PDM_HCIC_CTRL1, PDM_FILTER_EN, val); val 119 sound/soc/meson/axg-pdm.c regmap_update_bits(map, PDM_F1_CTRL, PDM_FILTER_EN, val); val 120 sound/soc/meson/axg-pdm.c regmap_update_bits(map, PDM_F2_CTRL, PDM_FILTER_EN, val); val 121 sound/soc/meson/axg-pdm.c regmap_update_bits(map, PDM_F3_CTRL, PDM_FILTER_EN, val); val 122 sound/soc/meson/axg-pdm.c regmap_update_bits(map, PDM_HPF_CTRL, PDM_FILTER_EN, val); val 183 sound/soc/meson/axg-pdm.c unsigned int spmax, sp, val; val 197 sound/soc/meson/axg-pdm.c for (i = 0, val = 0; i < PDM_CHAN_CTRL_NUM; i++) val 198 sound/soc/meson/axg-pdm.c val |= sp << (PDM_CHAN_CTRL_POINTER_WIDTH * i); val 200 sound/soc/meson/axg-pdm.c regmap_write(priv->map, PDM_CHAN_CTRL, val); val 201 sound/soc/meson/axg-pdm.c regmap_write(priv->map, PDM_CHAN_CTRL1, val); val 230 sound/soc/meson/axg-pdm.c unsigned int val; val 235 sound/soc/meson/axg-pdm.c val = PDM_CTRL_OUT_MODE; val 238 sound/soc/meson/axg-pdm.c val = 0; val 245 sound/soc/meson/axg-pdm.c regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_OUT_MODE, val); val 307 sound/soc/meson/axg-pdm.c unsigned int val; val 309 sound/soc/meson/axg-pdm.c val = PDM_HCIC_CTRL1_STAGE_NUM(hcic->steps); val 310 sound/soc/meson/axg-pdm.c val |= PDM_HCIC_CTRL1_DSR(hcic->ds); val 311 sound/soc/meson/axg-pdm.c val |= PDM_HCIC_CTRL1_GAIN_MULT(hcic->mult); val 312 sound/soc/meson/axg-pdm.c val |= PDM_HCIC_CTRL1_GAIN_SFT(hcic->shift); val 319 sound/soc/meson/axg-pdm.c val); val 327 sound/soc/meson/axg-pdm.c unsigned int val; val 329 sound/soc/meson/axg-pdm.c val = PDM_LPF_STAGE_NUM(lpf->tap_num); val 330 sound/soc/meson/axg-pdm.c val |= PDM_LPF_DSR(lpf->ds); val 331 sound/soc/meson/axg-pdm.c val |= PDM_LPF_ROUND_MODE(lpf->round_mode); val 337 sound/soc/meson/axg-pdm.c val); val 343 sound/soc/meson/axg-pdm.c unsigned int val; val 345 sound/soc/meson/axg-pdm.c val = PDM_HPF_OUT_FACTOR(hpf->out_factor); val 346 sound/soc/meson/axg-pdm.c val |= PDM_HPF_SFT_STEPS(hpf->steps); val 351 sound/soc/meson/axg-pdm.c val); val 144 sound/soc/meson/axg-spdifin.c unsigned int val, val 158 sound/soc/meson/axg-spdifin.c val << shift); val 162 sound/soc/meson/axg-spdifin.c unsigned int val) val 164 sound/soc/meson/axg-spdifin.c axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_TIMER_PER_REG, val 169 sound/soc/meson/axg-spdifin.c unsigned int val) val 171 sound/soc/meson/axg-spdifin.c axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_THRES_PER_REG, val 303 sound/soc/meson/axg-spdifin.c unsigned int val; val 309 sound/soc/meson/axg-spdifin.c regmap_read(priv->map, SPDIFIN_STAT1, &val); val 315 sound/soc/meson/axg-spdifin.c (val >> (j * 8)) & 0xff; val 126 sound/soc/meson/axg-spdifout.c unsigned int val; val 131 sound/soc/meson/axg-spdifout.c val = SPDIFOUT_CTRL0_MASK(0x1); val 134 sound/soc/meson/axg-spdifout.c val = SPDIFOUT_CTRL0_MASK(0x3); val 143 sound/soc/meson/axg-spdifout.c SPDIFOUT_CTRL0_MASK_MASK, val); val 149 sound/soc/meson/axg-spdifout.c val = SPDIFOUT_CTRL1_TYPE(0); val 153 sound/soc/meson/axg-spdifout.c val = SPDIFOUT_CTRL1_TYPE(2); val 157 sound/soc/meson/axg-spdifout.c val = SPDIFOUT_CTRL1_TYPE(4); val 166 sound/soc/meson/axg-spdifout.c val |= SPDIFOUT_CTRL1_MSB_POS(params_width(params) - 1); val 170 sound/soc/meson/axg-spdifout.c SPDIFOUT_CTRL1_TYPE_MASK, val); val 186 sound/soc/meson/axg-spdifout.c u32 val; val 194 sound/soc/meson/axg-spdifout.c val = cs[0] | cs[1] << 8 | cs[2] << 16 | cs[3] << 24; val 197 sound/soc/meson/axg-spdifout.c regmap_write(priv->map, SPDIFOUT_CHSTS0, val); val 205 sound/soc/meson/axg-spdifout.c regmap_write(priv->map, SPDIFOUT_CHSTS6, val); val 33 sound/soc/meson/axg-tdm-formatter.c unsigned int val, ch = ts->channels; val 42 sound/soc/meson/axg-tdm-formatter.c val = 0; val 48 sound/soc/meson/axg-tdm-formatter.c val |= 1 << j; val 52 sound/soc/meson/axg-tdm-formatter.c regmap_write(map, offset, val); val 115 sound/soc/meson/axg-tdmin.c unsigned int val, skew = quirks->skew_offset; val 134 sound/soc/meson/axg-tdmin.c val = TDMIN_CTRL_IN_BIT_SKEW(skew); val 141 sound/soc/meson/axg-tdmin.c val |= TDMIN_CTRL_I2S_MODE; val 147 sound/soc/meson/axg-tdmin.c val |= TDMIN_CTRL_WS_INV; val 150 sound/soc/meson/axg-tdmin.c val |= TDMIN_CTRL_BITNUM(ts->iface->slot_width - 1); val 159 sound/soc/meson/axg-tdmin.c TDMIN_CTRL_BITNUM_MASK), val); val 113 sound/soc/meson/axg-tdmout.c unsigned int val, skew = quirks->skew_offset; val 132 sound/soc/meson/axg-tdmout.c val = TDMOUT_CTRL0_INIT_BITNUM(skew); val 135 sound/soc/meson/axg-tdmout.c val |= TDMOUT_CTRL0_BITNUM(ts->iface->slot_width - 1); val 138 sound/soc/meson/axg-tdmout.c val |= TDMOUT_CTRL0_SLOTNUM(ts->iface->slots - 1); val 143 sound/soc/meson/axg-tdmout.c TDMOUT_CTRL0_SLOTNUM_MASK, val); val 146 sound/soc/meson/axg-tdmout.c val = TDMOUT_CTRL1_MSB_POS(ts->width - 1); val 152 sound/soc/meson/axg-tdmout.c val |= TDMOUT_CTRL1_TYPE(0); val 156 sound/soc/meson/axg-tdmout.c val |= TDMOUT_CTRL1_TYPE(2); val 160 sound/soc/meson/axg-tdmout.c val |= TDMOUT_CTRL1_TYPE(4); val 170 sound/soc/meson/axg-tdmout.c val |= TDMOUT_CTRL1_WS_INV; val 174 sound/soc/meson/axg-tdmout.c TDMOUT_CTRL1_WS_INV), val); val 86 sound/soc/meson/g12a-tohdmitx.c unsigned int val; val 88 sound/soc/meson/g12a-tohdmitx.c snd_soc_component_read(component, TOHDMITX_CTRL0, &val); val 89 sound/soc/meson/g12a-tohdmitx.c return (val & mask) >> __ffs(mask); val 113 sound/soc/meson/g12a-tohdmitx.c unsigned int val = g12a_tohdmitx_get_input_val(component, val 117 sound/soc/meson/g12a-tohdmitx.c if (val != mux) val 166 sound/soc/meson/g12a-tohdmitx.c unsigned int val = g12a_tohdmitx_get_input_val(component, val 170 sound/soc/meson/g12a-tohdmitx.c if (val != mux) val 39 sound/soc/pxa/mmp-sspa.c static void mmp_sspa_write_reg(struct ssp_device *sspa, u32 reg, u32 val) val 41 sound/soc/pxa/mmp-sspa.c __raw_writel(val, sspa->mmio_base + reg); val 307 sound/soc/pxa/pxa-ssp.c u32 val; val 312 sound/soc/pxa/pxa-ssp.c val = tmp; val 314 sound/soc/pxa/pxa-ssp.c val = (val << 16) | 64; val 315 sound/soc/pxa/pxa-ssp.c pxa_ssp_write_reg(ssp, SSACDD, val); val 321 sound/soc/pxa/pxa-ssp.c val, freq); val 737 sound/soc/pxa/pxa-ssp.c int val; val 745 sound/soc/pxa/pxa-ssp.c val = pxa_ssp_read_reg(ssp, SSSR); val 746 sound/soc/pxa/pxa-ssp.c pxa_ssp_write_reg(ssp, SSSR, val); val 49 sound/soc/pxa/pxa2xx-ac97.c unsigned short reg, unsigned short val) val 51 sound/soc/pxa/pxa2xx-ac97.c return pxa2xx_ac97_write(slot, reg, val); val 197 sound/soc/qcom/lpass-cpu.c unsigned int val, mask; val 200 sound/soc/qcom/lpass-cpu.c val = LPAIF_I2SCTL_SPKEN_ENABLE; val 203 sound/soc/qcom/lpass-cpu.c val = LPAIF_I2SCTL_MICEN_ENABLE; val 209 sound/soc/qcom/lpass-cpu.c mask, val); val 221 sound/soc/qcom/lpass-cpu.c unsigned int val, mask; val 228 sound/soc/qcom/lpass-cpu.c val = LPAIF_I2SCTL_SPKEN_ENABLE; val 231 sound/soc/qcom/lpass-cpu.c val = LPAIF_I2SCTL_MICEN_ENABLE; val 238 sound/soc/qcom/lpass-cpu.c mask, val); val 247 sound/soc/qcom/lpass-cpu.c val = LPAIF_I2SCTL_SPKEN_DISABLE; val 250 sound/soc/qcom/lpass-cpu.c val = LPAIF_I2SCTL_MICEN_DISABLE; val 257 sound/soc/qcom/lpass-cpu.c mask, val); val 92 sound/soc/rockchip/rockchip_i2s.c unsigned int val = 0; val 122 sound/soc/rockchip/rockchip_i2s.c regmap_read(i2s->regmap, I2S_CLR, &val); val 125 sound/soc/rockchip/rockchip_i2s.c while (val) { val 126 sound/soc/rockchip/rockchip_i2s.c regmap_read(i2s->regmap, I2S_CLR, &val); val 139 sound/soc/rockchip/rockchip_i2s.c unsigned int val = 0; val 169 sound/soc/rockchip/rockchip_i2s.c regmap_read(i2s->regmap, I2S_CLR, &val); val 172 sound/soc/rockchip/rockchip_i2s.c while (val) { val 173 sound/soc/rockchip/rockchip_i2s.c regmap_read(i2s->regmap, I2S_CLR, &val); val 188 sound/soc/rockchip/rockchip_i2s.c unsigned int mask = 0, val = 0; val 194 sound/soc/rockchip/rockchip_i2s.c val = I2S_CKR_MSS_MASTER; val 198 sound/soc/rockchip/rockchip_i2s.c val = I2S_CKR_MSS_SLAVE; val 205 sound/soc/rockchip/rockchip_i2s.c regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); val 210 sound/soc/rockchip/rockchip_i2s.c val = I2S_CKR_CKP_NEG; val 213 sound/soc/rockchip/rockchip_i2s.c val = I2S_CKR_CKP_POS; val 219 sound/soc/rockchip/rockchip_i2s.c regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); val 224 sound/soc/rockchip/rockchip_i2s.c val = I2S_TXCR_IBM_RSJM; val 227 sound/soc/rockchip/rockchip_i2s.c val = I2S_TXCR_IBM_LSJM; val 230 sound/soc/rockchip/rockchip_i2s.c val = I2S_TXCR_IBM_NORMAL; val 233 sound/soc/rockchip/rockchip_i2s.c val = I2S_TXCR_TFS_PCM; val 236 sound/soc/rockchip/rockchip_i2s.c val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); val 242 sound/soc/rockchip/rockchip_i2s.c regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); val 247 sound/soc/rockchip/rockchip_i2s.c val = I2S_RXCR_IBM_RSJM; val 250 sound/soc/rockchip/rockchip_i2s.c val = I2S_RXCR_IBM_LSJM; val 253 sound/soc/rockchip/rockchip_i2s.c val = I2S_RXCR_IBM_NORMAL; val 256 sound/soc/rockchip/rockchip_i2s.c val = I2S_RXCR_TFS_PCM; val 259 sound/soc/rockchip/rockchip_i2s.c val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); val 265 sound/soc/rockchip/rockchip_i2s.c regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); val 276 sound/soc/rockchip/rockchip_i2s.c unsigned int val = 0; val 300 sound/soc/rockchip/rockchip_i2s.c val |= I2S_TXCR_VDW(8); val 303 sound/soc/rockchip/rockchip_i2s.c val |= I2S_TXCR_VDW(16); val 306 sound/soc/rockchip/rockchip_i2s.c val |= I2S_TXCR_VDW(20); val 309 sound/soc/rockchip/rockchip_i2s.c val |= I2S_TXCR_VDW(24); val 312 sound/soc/rockchip/rockchip_i2s.c val |= I2S_TXCR_VDW(32); val 320 sound/soc/rockchip/rockchip_i2s.c val |= I2S_CHN_8; val 323 sound/soc/rockchip/rockchip_i2s.c val |= I2S_CHN_6; val 326 sound/soc/rockchip/rockchip_i2s.c val |= I2S_CHN_4; val 329 sound/soc/rockchip/rockchip_i2s.c val |= I2S_CHN_2; val 340 sound/soc/rockchip/rockchip_i2s.c val); val 344 sound/soc/rockchip/rockchip_i2s.c val); val 347 sound/soc/rockchip/rockchip_i2s.c regmap_read(i2s->regmap, I2S_TXCR, &val); val 348 sound/soc/rockchip/rockchip_i2s.c val &= I2S_TXCR_CSR_MASK; val 350 sound/soc/rockchip/rockchip_i2s.c switch (val) { val 352 sound/soc/rockchip/rockchip_i2s.c val = I2S_IO_4CH_OUT_6CH_IN; val 355 sound/soc/rockchip/rockchip_i2s.c val = I2S_IO_6CH_OUT_4CH_IN; val 358 sound/soc/rockchip/rockchip_i2s.c val = I2S_IO_8CH_OUT_2CH_IN; val 361 sound/soc/rockchip/rockchip_i2s.c val = I2S_IO_2CH_OUT_8CH_IN; val 365 sound/soc/rockchip/rockchip_i2s.c val <<= i2s->pins->shift; val 366 sound/soc/rockchip/rockchip_i2s.c val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16; val 367 sound/soc/rockchip/rockchip_i2s.c regmap_write(i2s->grf, i2s->pins->reg_offset, val); val 375 sound/soc/rockchip/rockchip_i2s.c val = I2S_CKR_TRCM_TXRX; val 377 sound/soc/rockchip/rockchip_i2s.c val = I2S_CKR_TRCM_TXONLY; val 381 sound/soc/rockchip/rockchip_i2s.c val); val 586 sound/soc/rockchip/rockchip_i2s.c int val; val 658 sound/soc/rockchip/rockchip_i2s.c if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { val 659 sound/soc/rockchip/rockchip_i2s.c if (val >= 2 && val <= 8) val 660 sound/soc/rockchip/rockchip_i2s.c soc_dai->playback.channels_max = val; val 663 sound/soc/rockchip/rockchip_i2s.c if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { val 664 sound/soc/rockchip/rockchip_i2s.c if (val >= 2 && val <= 8) val 665 sound/soc/rockchip/rockchip_i2s.c soc_dai->capture.channels_max = val; val 150 sound/soc/rockchip/rockchip_pdm.c unsigned int val = 0; val 175 sound/soc/rockchip/rockchip_pdm.c val = (m << PDM_FD_NUMERATOR_SFT) | val 180 sound/soc/rockchip/rockchip_pdm.c val, &change); val 188 sound/soc/rockchip/rockchip_pdm.c val = PDM_CLK_FD_RATIO_40; val 190 sound/soc/rockchip/rockchip_pdm.c val = PDM_CLK_FD_RATIO_35; val 195 sound/soc/rockchip/rockchip_pdm.c val); val 197 sound/soc/rockchip/rockchip_pdm.c val = get_pdm_ds_ratio(samplerate); val 198 sound/soc/rockchip/rockchip_pdm.c regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val); val 208 sound/soc/rockchip/rockchip_pdm.c val = 0; val 211 sound/soc/rockchip/rockchip_pdm.c val |= PDM_VDW(8); val 214 sound/soc/rockchip/rockchip_pdm.c val |= PDM_VDW(16); val 217 sound/soc/rockchip/rockchip_pdm.c val |= PDM_VDW(20); val 220 sound/soc/rockchip/rockchip_pdm.c val |= PDM_VDW(24); val 223 sound/soc/rockchip/rockchip_pdm.c val |= PDM_VDW(32); val 231 sound/soc/rockchip/rockchip_pdm.c val |= PDM_PATH3_EN; val 234 sound/soc/rockchip/rockchip_pdm.c val |= PDM_PATH2_EN; val 237 sound/soc/rockchip/rockchip_pdm.c val |= PDM_PATH1_EN; val 240 sound/soc/rockchip/rockchip_pdm.c val |= PDM_PATH0_EN; val 250 sound/soc/rockchip/rockchip_pdm.c val); val 262 sound/soc/rockchip/rockchip_pdm.c unsigned int mask = 0, val = 0; val 267 sound/soc/rockchip/rockchip_pdm.c val = PDM_CKP_NORMAL; val 270 sound/soc/rockchip/rockchip_pdm.c val = PDM_CKP_INVERTED; val 277 sound/soc/rockchip/rockchip_pdm.c regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, mask, val); val 110 sound/soc/rockchip/rockchip_spdif.c unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE; val 119 sound/soc/rockchip/rockchip_spdif.c val |= SPDIF_CFGR_VDW_16; val 122 sound/soc/rockchip/rockchip_spdif.c val |= SPDIF_CFGR_VDW_20; val 125 sound/soc/rockchip/rockchip_spdif.c val |= SPDIF_CFGR_VDW_24; val 142 sound/soc/rockchip/rockchip_spdif.c val); val 476 sound/soc/samsung/i2s.c u32 val; val 490 sound/soc/samsung/i2s.c val = msecs_to_loops(1) / 1000; /* 1 usec */ val 491 sound/soc/samsung/i2s.c while (--val) val 506 sound/soc/samsung/i2s.c u32 mod, mask, val = 0; val 519 sound/soc/samsung/i2s.c val = (dir << MOD_OPCLK_SHIFT) & MOD_OPCLK_MASK; val 540 sound/soc/samsung/i2s.c val = 1 << i2s_regs->cdclkcon_off; val 601 sound/soc/samsung/i2s.c val = 1 << i2s_regs->rclksrc_off; val 611 sound/soc/samsung/i2s.c mod = (mod & ~mask) | val; val 724 sound/soc/samsung/i2s.c u32 mod, mask = 0, val = 0; val 735 sound/soc/samsung/i2s.c val |= MOD_DC2_EN; val 738 sound/soc/samsung/i2s.c val |= MOD_DC1_EN; val 770 sound/soc/samsung/i2s.c val |= MOD_BLCS_8BIT; val 772 sound/soc/samsung/i2s.c val |= MOD_BLCP_8BIT; val 774 sound/soc/samsung/i2s.c val |= MOD_BLC_8BIT; val 778 sound/soc/samsung/i2s.c val |= MOD_BLCS_16BIT; val 780 sound/soc/samsung/i2s.c val |= MOD_BLCP_16BIT; val 782 sound/soc/samsung/i2s.c val |= MOD_BLC_16BIT; val 786 sound/soc/samsung/i2s.c val |= MOD_BLCS_24BIT; val 788 sound/soc/samsung/i2s.c val |= MOD_BLCP_24BIT; val 790 sound/soc/samsung/i2s.c val |= MOD_BLC_24BIT; val 800 sound/soc/samsung/i2s.c mod = (mod & ~mask) | val; val 1297 sound/soc/samsung/i2s.c u32 val = readl(priv->addr + I2SPSR); val 1298 sound/soc/samsung/i2s.c writel(val | PSR_PSREN, priv->addr + I2SPSR); val 68 sound/soc/samsung/idma.c u32 val; val 75 sound/soc/samsung/idma.c val = idma.lp_tx_addr + prtd->periodsz; val 76 sound/soc/samsung/idma.c writel(val, idma.regs + I2SLVL0ADDR); val 79 sound/soc/samsung/idma.c val = idma.lp_tx_addr; val 80 sound/soc/samsung/idma.c writel(val, idma.regs + I2SSTR0); val 86 sound/soc/samsung/idma.c val = readl(idma.regs + I2SSIZE); val 87 sound/soc/samsung/idma.c val &= ~(I2SSIZE_TRNMSK << I2SSIZE_SHIFT); val 88 sound/soc/samsung/idma.c val |= (((runtime->dma_bytes >> 2) & val 90 sound/soc/samsung/idma.c writel(val, idma.regs + I2SSIZE); val 92 sound/soc/samsung/idma.c val = readl(idma.regs + I2SAHB); val 93 sound/soc/samsung/idma.c val |= AHB_INTENLVL0; val 94 sound/soc/samsung/idma.c writel(val, idma.regs + I2SAHB); val 111 sound/soc/samsung/idma.c u32 val = readl(idma.regs + I2SAHB); val 117 sound/soc/samsung/idma.c val |= (AHB_INTENLVL0 | AHB_DMAEN); val 120 sound/soc/samsung/idma.c val &= ~(AHB_INTENLVL0 | AHB_DMAEN); val 127 sound/soc/samsung/idma.c writel(val, idma.regs + I2SAHB); val 257 sound/soc/samsung/idma.c u32 iisahb, val, addr; val 261 sound/soc/samsung/idma.c val = (iisahb & AHB_LVL0INT) ? AHB_CLRLVL0INT : 0; val 263 sound/soc/samsung/idma.c if (val) { val 264 sound/soc/samsung/idma.c iisahb |= val; val 326 sound/soc/sh/fsi.c u32 val = __fsi_reg_read(reg); val 328 sound/soc/sh/fsi.c val &= ~mask; val 329 sound/soc/sh/fsi.c val |= data & mask; val 331 sound/soc/sh/fsi.c __fsi_reg_write(reg, val); val 714 sound/soc/sh/fsi.c u32 mask, val; val 717 sound/soc/sh/fsi.c val = enable ? mask : 0; val 720 sound/soc/sh/fsi.c fsi_core_mask_set(master, a_mclk, mask, val) : val 721 sound/soc/sh/fsi.c fsi_core_mask_set(master, b_mclk, mask, val); val 1837 sound/soc/sh/fsi.c unsigned int val; val 1847 sound/soc/sh/fsi.c flags |= of_parse_property[i].val; val 138 sound/soc/sh/hac.c unsigned short val; val 154 sound/soc/sh/hac.c val = 0; val 155 sound/soc/sh/hac.c if (hac_get_codec_data(hac, reg, &val) != 0) val 159 sound/soc/sh/hac.c return i ? val : ~0; val 163 sound/soc/sh/hac.c unsigned short val) val 173 sound/soc/sh/hac.c HACREG(HACCSDR) = (val << CSDR_SHIFT); val 115 sound/soc/sh/rcar/adg.c unsigned int val, en; val 126 sound/soc/sh/rcar/adg.c val = 0; val 138 sound/soc/sh/rcar/adg.c val = (sel << 8) | idx; val 162 sound/soc/sh/rcar/adg.c *target_val = val; val 216 sound/soc/sh/rcar/adg.c u32 mask, val; val 221 sound/soc/sh/rcar/adg.c NULL, &val, NULL); val 223 sound/soc/sh/rcar/adg.c val = val << shift; val 226 sound/soc/sh/rcar/adg.c rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); val 263 sound/soc/sh/rcar/adg.c static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) val 275 sound/soc/sh/rcar/adg.c val = val << shift; val 284 sound/soc/sh/rcar/adg.c rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val); val 286 sound/soc/sh/rcar/adg.c dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val); val 546 sound/soc/sh/rcar/core.c u8 val = (*status >> shift) & 0xF; val 547 sound/soc/sh/rcar/core.c u8 next_val = (val + add) & 0xF; val 548 sound/soc/sh/rcar/core.c int func_call = (val == timing); val 1511 sound/soc/sh/rcar/core.c uc->value.enumerated.item[i] = cfg->val[i]; val 1513 sound/soc/sh/rcar/core.c uc->value.integer.value[i] = cfg->val[i]; val 1529 sound/soc/sh/rcar/core.c change |= (uc->value.enumerated.item[i] != cfg->val[i]); val 1530 sound/soc/sh/rcar/core.c cfg->val[i] = uc->value.enumerated.item[i]; val 1532 sound/soc/sh/rcar/core.c change |= (uc->value.integer.value[i] != cfg->val[i]); val 1533 sound/soc/sh/rcar/core.c cfg->val[i] = uc->value.integer.value[i]; val 1564 sound/soc/sh/rcar/core.c cfg->cfg.val = cfg->val; val 1571 sound/soc/sh/rcar/core.c cfg->cfg.val = &cfg->val; val 123 sound/soc/sh/rcar/ctu.c u32 val = rsnd_kctrl_valm(ctu->pass, i); val 125 sound/soc/sh/rcar/ctu.c cpmdr |= val << (28 - (i * 4)); val 127 sound/soc/sh/rcar/ctu.c if ((val > 0x8) && (scmdr < (val - 0x8))) val 128 sound/soc/sh/rcar/ctu.c scmdr = val - 0x8; val 421 sound/soc/sh/rcar/dma.c u32 val = ioread32(addr); val 423 sound/soc/sh/rcar/dma.c val &= ~mask; val 424 sound/soc/sh/rcar/dma.c val |= (data & mask); val 426 sound/soc/sh/rcar/dma.c iowrite32(val, addr); val 77 sound/soc/sh/rcar/dvc.c u32 val[RSND_MAX_CHANNELS]; val 83 sound/soc/sh/rcar/dvc.c val[i] = rsnd_kctrl_max(dvc->volume); val 86 sound/soc/sh/rcar/dvc.c val[i] = rsnd_kctrl_valm(dvc->volume, i); val 90 sound/soc/sh/rcar/dvc.c rsnd_mod_write(mod, DVC_VOLxR(i), val[i]); val 87 sound/soc/sh/rcar/gen.c u32 val; val 92 sound/soc/sh/rcar/gen.c regmap_fields_read(gen->regs[reg], rsnd_mod_id_cmd(mod), &val); val 96 sound/soc/sh/rcar/gen.c rsnd_reg_name(gen, reg), reg, val); val 98 sound/soc/sh/rcar/gen.c return val; val 705 sound/soc/sh/rcar/rsnd.h u32 *val; val 718 sound/soc/sh/rcar/rsnd.h u32 val[RSND_MAX_CHANNELS]; val 723 sound/soc/sh/rcar/rsnd.h u32 val; val 727 sound/soc/sh/rcar/rsnd.h #define rsnd_kctrl_valm(x, i) ((x).val[i]) /* = (x).cfg.val[i] */ val 728 sound/soc/sh/rcar/rsnd.h #define rsnd_kctrl_vals(x) ((x).val) /* = (x).cfg.val[0] */ val 35 sound/soc/sh/rcar/src.c #define rsnd_src_sync_is_enabled(mod) (rsnd_mod_to_src(mod)->sen.val) val 93 sound/soc/sh/rcar/src.c convert_rate = src->sync.val; val 388 sound/soc/sh/rcar/src.c u32 val = OUF_SRC(rsnd_mod_id(mod)); val 390 sound/soc/sh/rcar/src.c rsnd_mod_write(mod, SCU_SYS_STATUS0, val); val 391 sound/soc/sh/rcar/src.c rsnd_mod_write(mod, SCU_SYS_STATUS1, val); val 428 sound/soc/sh/rcar/src.c u32 val; val 435 sound/soc/sh/rcar/src.c val = (rsnd_io_to_mod_dvc(io) && !rsnd_src_sync_is_enabled(mod)) ? val 438 sound/soc/sh/rcar/src.c rsnd_mod_write(mod, SRC_CTRL, val); val 459 sound/soc/sh/rcar/src.c src->sync.val = 0; val 483 sound/soc/sh/rcar/src.c src->sync.val = 0; val 624 sound/soc/sh/rcar/ssi.c u32 val = 0; val 636 sound/soc/sh/rcar/ssi.c val = rsnd_ssi_is_dma_mode(mod) ? 0x0e000000 : 0x0f000000; val 638 sound/soc/sh/rcar/ssi.c rsnd_mod_write(mod, SSI_INT_ENABLE, val); val 211 sound/soc/sh/rcar/ssiu.c u32 val; val 217 sound/soc/sh/rcar/ssiu.c val = i << 16 | val 225 sound/soc/sh/rcar/ssiu.c val = (val & ~(0xF << shift)) | val 230 sound/soc/sh/rcar/ssiu.c rsnd_mod_write(mod, HDMI0_SEL, val); val 232 sound/soc/sh/rcar/ssiu.c rsnd_mod_write(mod, HDMI1_SEL, val); val 134 sound/soc/sh/siu.h static inline void siu_write32(u32 __iomem *addr, u32 val) val 136 sound/soc/sh/siu.h __raw_writel(val, addr); val 3068 sound/soc/soc-core.c u32 val; val 3069 sound/soc/soc-core.c const __be32 *of_slot_mask = of_get_property(np, prop_name, &val); val 3074 sound/soc/soc-core.c val /= sizeof(u32); val 3075 sound/soc/soc-core.c for (i = 0; i < val; i++) val 3079 sound/soc/soc-core.c return val; val 3089 sound/soc/soc-core.c u32 val; val 3098 sound/soc/soc-core.c ret = of_property_read_u32(np, "dai-tdm-slot-num", &val); val 3103 sound/soc/soc-core.c *slots = val; val 3107 sound/soc/soc-core.c ret = of_property_read_u32(np, "dai-tdm-slot-width", &val); val 3112 sound/soc/soc-core.c *slot_width = val; val 3206 sound/soc/soc-core.c unsigned int val; val 3235 sound/soc/soc-core.c format |= of_fmt_table[i].val; val 42 sound/soc/soc-dapm.c #define DAPM_UPDATE_STAT(widget, val) widget->dapm->card->dapm_stats.val++; val 754 sound/soc/soc-dapm.c unsigned int val, item; val 758 sound/soc/soc-dapm.c soc_dapm_read(dapm, e->reg, &val); val 759 sound/soc/soc-dapm.c val = (val >> e->shift_l) & e->mask; val 760 sound/soc/soc-dapm.c item = snd_soc_enum_val_to_item(e, val); val 792 sound/soc/soc-dapm.c unsigned int val; val 795 sound/soc/soc-dapm.c soc_dapm_read(p->sink->dapm, reg, &val); val 810 sound/soc/soc-dapm.c soc_dapm_read(p->sink->dapm, mc->rreg, &val); val 811 sound/soc/soc-dapm.c val = (val >> mc->rshift) & mask; val 813 sound/soc/soc-dapm.c val = (val >> shift) & mask; val 816 sound/soc/soc-dapm.c val = max - val; val 817 sound/soc/soc-dapm.c p->connect = !!val; val 1762 sound/soc/soc-dapm.c update->val); val 3206 sound/soc/soc-dapm.c unsigned int val; val 3249 sound/soc/soc-dapm.c soc_dapm_read(w->dapm, w->reg, &val); val 3250 sound/soc/soc-dapm.c val = val >> w->shift; val 3251 sound/soc/soc-dapm.c val &= w->mask; val 3252 sound/soc/soc-dapm.c if (val == w->on_val) val 3290 sound/soc/soc-dapm.c unsigned int reg_val, val, rval = 0; val 3296 sound/soc/soc-dapm.c val = (reg_val >> shift) & mask; val 3305 sound/soc/soc-dapm.c val = reg_val & mask; val 3316 sound/soc/soc-dapm.c ucontrol->value.integer.value[0] = max - val; val 3318 sound/soc/soc-dapm.c ucontrol->value.integer.value[0] = val; val 3353 sound/soc/soc-dapm.c unsigned int val, rval = 0; val 3358 sound/soc/soc-dapm.c val = (ucontrol->value.integer.value[0] & mask); val 3359 sound/soc/soc-dapm.c connect = !!val; val 3362 sound/soc/soc-dapm.c val = max - val; val 3378 sound/soc/soc-dapm.c change = dapm_kcontrol_set_value(kcontrol, val | (rval << width)); val 3381 sound/soc/soc-dapm.c val = val << shift; val 3384 sound/soc/soc-dapm.c reg_change = soc_dapm_test_bits(dapm, reg, mask << shift, val); val 3403 sound/soc/soc-dapm.c update.val = val; val 3438 sound/soc/soc-dapm.c unsigned int reg_val, val; val 3452 sound/soc/soc-dapm.c val = (reg_val >> e->shift_l) & e->mask; val 3453 sound/soc/soc-dapm.c ucontrol->value.enumerated.item[0] = snd_soc_enum_val_to_item(e, val); val 3455 sound/soc/soc-dapm.c val = (reg_val >> e->shift_r) & e->mask; val 3456 sound/soc/soc-dapm.c val = snd_soc_enum_val_to_item(e, val); val 3457 sound/soc/soc-dapm.c ucontrol->value.enumerated.item[1] = val; val 3480 sound/soc/soc-dapm.c unsigned int val, change, reg_change = 0; val 3488 sound/soc/soc-dapm.c val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; val 3493 sound/soc/soc-dapm.c val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r; val 3499 sound/soc/soc-dapm.c change = dapm_kcontrol_set_value(kcontrol, val); val 3502 sound/soc/soc-dapm.c reg_change = soc_dapm_test_bits(dapm, e->reg, mask, val); val 3509 sound/soc/soc-dapm.c update.val = val; val 24 sound/soc/soc-io.c unsigned int reg, unsigned int *val) val 29 sound/soc/soc-io.c ret = regmap_read(component->regmap, reg, val); val 31 sound/soc/soc-io.c *val = component->driver->read(component, reg); val 44 sound/soc/soc-io.c unsigned int val; val 47 sound/soc/soc-io.c ret = snd_soc_component_read(component, reg, &val); val 51 sound/soc/soc-io.c return val; val 64 sound/soc/soc-io.c unsigned int reg, unsigned int val) val 67 sound/soc/soc-io.c return regmap_write(component->regmap, reg, val); val 69 sound/soc/soc-io.c return component->driver->write(component, reg, val); val 77 sound/soc/soc-io.c unsigned int mask, unsigned int val, bool *change) val 88 sound/soc/soc-io.c new = (old & ~mask) | (val & mask); val 110 sound/soc/soc-io.c unsigned int reg, unsigned int mask, unsigned int val) val 117 sound/soc/soc-io.c val, &change); val 120 sound/soc/soc-io.c mask, val, &change); val 146 sound/soc/soc-io.c unsigned int reg, unsigned int mask, unsigned int val) val 153 sound/soc/soc-io.c mask, val, &change); val 156 sound/soc/soc-io.c mask, val, &change); val 64 sound/soc/soc-ops.c unsigned int val, item; val 71 sound/soc/soc-ops.c val = (reg_val >> e->shift_l) & e->mask; val 72 sound/soc/soc-ops.c item = snd_soc_enum_val_to_item(e, val); val 75 sound/soc/soc-ops.c val = (reg_val >> e->shift_r) & e->mask; val 76 sound/soc/soc-ops.c item = snd_soc_enum_val_to_item(e, val); val 99 sound/soc/soc-ops.c unsigned int val; val 104 sound/soc/soc-ops.c val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; val 109 sound/soc/soc-ops.c val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r; val 113 sound/soc/soc-ops.c return snd_soc_component_update_bits(component, e->reg, mask, val); val 137 sound/soc/soc-ops.c unsigned int val; val 139 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg, &val); val 143 sound/soc/soc-ops.c val = (val >> shift) & mask; val 146 sound/soc/soc-ops.c *signed_val = val; val 151 sound/soc/soc-ops.c if (!(val & BIT(sign_bit))) { val 152 sound/soc/soc-ops.c *signed_val = val; val 156 sound/soc/soc-ops.c ret = val; val 257 sound/soc/soc-ops.c int val; val 263 sound/soc/soc-ops.c ret = snd_soc_read_signed(component, reg, mask, shift, sign_bit, &val); val 267 sound/soc/soc-ops.c ucontrol->value.integer.value[0] = val - min; val 275 sound/soc/soc-ops.c sign_bit, &val); val 278 sound/soc/soc-ops.c sign_bit, &val); val 282 sound/soc/soc-ops.c ucontrol->value.integer.value[1] = val - min; val 320 sound/soc/soc-ops.c unsigned int val, val_mask; val 325 sound/soc/soc-ops.c val = ((ucontrol->value.integer.value[0] + min) & mask); val 327 sound/soc/soc-ops.c val = max - val; val 329 sound/soc/soc-ops.c val = val << shift; val 336 sound/soc/soc-ops.c val |= val2 << rshift; val 342 sound/soc/soc-ops.c err = snd_soc_component_update_bits(component, reg, val_mask, val); val 377 sound/soc/soc-ops.c unsigned int val; val 380 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg, &val); val 384 sound/soc/soc-ops.c ucontrol->value.integer.value[0] = ((val >> shift) - min) & mask; val 387 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg2, &val); val 391 sound/soc/soc-ops.c val = ((val >> rshift) - min) & mask; val 392 sound/soc/soc-ops.c ucontrol->value.integer.value[1] = val; val 423 sound/soc/soc-ops.c unsigned int val, val_mask, val2 = 0; val 426 sound/soc/soc-ops.c val = (ucontrol->value.integer.value[0] + min) & mask; val 427 sound/soc/soc-ops.c val = val << shift; val 429 sound/soc/soc-ops.c err = snd_soc_component_update_bits(component, reg, val_mask, val); val 498 sound/soc/soc-ops.c unsigned int val, val_mask; val 502 sound/soc/soc-ops.c val = (max - ucontrol->value.integer.value[0]) & mask; val 504 sound/soc/soc-ops.c val = ((ucontrol->value.integer.value[0] + min) & mask); val 506 sound/soc/soc-ops.c val = val << shift; val 508 sound/soc/soc-ops.c ret = snd_soc_component_update_bits(component, reg, val_mask, val); val 514 sound/soc/soc-ops.c val = (max - ucontrol->value.integer.value[1]) & mask; val 516 sound/soc/soc-ops.c val = ((ucontrol->value.integer.value[1] + min) & mask); val 518 sound/soc/soc-ops.c val = val << shift; val 521 sound/soc/soc-ops.c val); val 550 sound/soc/soc-ops.c unsigned int val; val 553 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg, &val); val 557 sound/soc/soc-ops.c ucontrol->value.integer.value[0] = (val >> shift) & mask; val 566 sound/soc/soc-ops.c ret = snd_soc_component_read(component, rreg, &val); val 570 sound/soc/soc-ops.c ucontrol->value.integer.value[1] = (val >> shift) & mask; val 678 sound/soc/soc-ops.c unsigned int val, mask; val 696 sound/soc/soc-ops.c ret = regmap_read(component->regmap, params->base, &val); val 700 sound/soc/soc-ops.c val &= params->mask; val 705 sound/soc/soc-ops.c ((u8 *)data)[0] |= val; val 717 sound/soc/soc-ops.c &val, &val); val 721 sound/soc/soc-ops.c ((u16 *)data)[0] |= val; val 733 sound/soc/soc-ops.c &val, &val); val 737 sound/soc/soc-ops.c ((u32 *)data)[0] |= val; val 840 sound/soc/soc-ops.c long val = 0; val 849 sound/soc/soc-ops.c val |= (regval & regwmask) << (regwshift*(regcount-i-1)); val 851 sound/soc/soc-ops.c val &= mask; val 852 sound/soc/soc-ops.c if (min < 0 && val > max) val 853 sound/soc/soc-ops.c val |= ~mask; val 855 sound/soc/soc-ops.c val = max - val; val 856 sound/soc/soc-ops.c ucontrol->value.integer.value[0] = val; val 888 sound/soc/soc-ops.c long val = ucontrol->value.integer.value[0]; val 893 sound/soc/soc-ops.c val = max - val; val 894 sound/soc/soc-ops.c val &= mask; val 896 sound/soc/soc-ops.c regval = (val >> (regwshift*(regcount-i-1))) & regwmask; val 927 sound/soc/soc-ops.c unsigned int val; val 930 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg, &val); val 934 sound/soc/soc-ops.c val &= mask; val 936 sound/soc/soc-ops.c if (shift != 0 && val != 0) val 937 sound/soc/soc-ops.c val = val >> shift; val 938 sound/soc/soc-ops.c ucontrol->value.enumerated.item[0] = val ^ invert; val 31 sound/soc/sof/intel/hda-ctrl.c u32 val; val 34 sound/soc/sof/intel/hda-ctrl.c val = reset ? 0 : SOF_HDA_GCTL_RESET; val 38 sound/soc/sof/intel/hda-ctrl.c SOF_HDA_GCTL_RESET, val); val 44 sound/soc/sof/intel/hda-ctrl.c if ((gctl & SOF_HDA_GCTL_RESET) == val) val 114 sound/soc/sof/intel/hda-ctrl.c u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0; val 117 sound/soc/sof/intel/hda-ctrl.c SOF_HDA_PPCTL_GPROCEN, val); val 122 sound/soc/sof/intel/hda-ctrl.c u32 val = enable ? SOF_HDA_PPCTL_PIE : 0; val 125 sound/soc/sof/intel/hda-ctrl.c SOF_HDA_PPCTL_PIE, val); val 130 sound/soc/sof/intel/hda-ctrl.c u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0; val 132 sound/soc/sof/intel/hda-ctrl.c snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val); val 142 sound/soc/sof/intel/hda-ctrl.c u32 val; val 145 sound/soc/sof/intel/hda-ctrl.c val = enable ? PCI_CGCTL_ADSPDCGE : 0; val 146 sound/soc/sof/intel/hda-ctrl.c snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val); val 149 sound/soc/sof/intel/hda-ctrl.c val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0; val 151 sound/soc/sof/intel/hda-ctrl.c HDA_VS_INTEL_EM2_L1SEN, val); val 154 sound/soc/sof/intel/hda-ctrl.c val = enable ? 0 : PCI_PGCTL_ADSPPGD; val 155 sound/soc/sof/intel/hda-ctrl.c snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val); val 190 sound/soc/sof/intel/hda-dsp.c int val; val 193 sound/soc/sof/intel/hda-dsp.c val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS); val 195 sound/soc/sof/intel/hda-dsp.c is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) && val 196 sound/soc/sof/intel/hda-dsp.c (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) && val 197 sound/soc/sof/intel/hda-dsp.c !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) && val 198 sound/soc/sof/intel/hda-dsp.c !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask))); val 330 sound/soc/sof/intel/hda-stream.c u32 val, mask; val 372 sound/soc/sof/intel/hda-stream.c val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, val 374 sound/soc/sof/intel/hda-stream.c if (val & 0x1) val 389 sound/soc/sof/intel/hda-stream.c val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, val 391 sound/soc/sof/intel/hda-stream.c if ((val & 0x1) == 0) val 417 sound/soc/sof/ops.h #define snd_sof_dsp_read_poll_timeout(sdev, bar, offset, val, cond, sleep_us, timeout_us) \ val 424 sound/soc/sof/ops.h (val) = snd_sof_dsp_read(sdev, bar, offset); \ val 427 sound/soc/sof/ops.h "FW Poll Status: reg=%#x successful\n", (val)); \ val 432 sound/soc/sof/ops.h (val) = snd_sof_dsp_read(sdev, bar, offset); \ val 434 sound/soc/sof/ops.h "FW Poll Status: reg=%#x timedout\n", (val)); \ val 609 sound/soc/sof/topology.c u32 *val = (u32 *)((u8 *)object + offset); val 611 sound/soc/sof/topology.c *val = le32_to_cpu(velem->value); val 618 sound/soc/sof/topology.c u16 *val = (u16 *)((u8 *)object + offset); val 620 sound/soc/sof/topology.c *val = (u16)le32_to_cpu(velem->value); val 627 sound/soc/sof/topology.c u32 *val = (u32 *)((u8 *)object + offset); val 629 sound/soc/sof/topology.c *val = find_format(velem->string); val 636 sound/soc/sof/topology.c u32 *val = (u32 *)((u8 *)object + offset); val 638 sound/soc/sof/topology.c *val = find_dai(velem->string); val 646 sound/soc/sof/topology.c u32 *val = (u32 *)((u8 *)object + offset); val 648 sound/soc/sof/topology.c *val = find_process(velem->string); val 194 sound/soc/spear/spdif_out.c u32 val; val 197 sound/soc/spear/spdif_out.c val = readl(host->io_base + SPDIF_OUT_CTRL); val 198 sound/soc/spear/spdif_out.c val &= ~SPDIF_OPMODE_MASK; val 201 sound/soc/spear/spdif_out.c val |= SPDIF_OPMODE_MUTE_PCM; val 204 sound/soc/spear/spdif_out.c val |= SPDIF_OPMODE_AUD_DATA | SPDIF_STATE_NORMAL; val 206 sound/soc/spear/spdif_out.c val |= SPDIF_OPMODE_OFF; val 209 sound/soc/spear/spdif_out.c writel(val, host->io_base + SPDIF_OUT_CTRL); val 118 sound/soc/sprd/sprd-mcdt.c static void sprd_mcdt_update(struct sprd_mcdt_dev *mcdt, u32 reg, u32 val, val 124 sound/soc/sprd/sprd-mcdt.c tmp = (orig & ~mask) | val; val 183 sound/soc/sprd/sprd-mcdt.c u32 val) val 187 sound/soc/sprd/sprd-mcdt.c writel_relaxed(val, mcdt->base + reg); val 191 sound/soc/sprd/sprd-mcdt.c u32 *val) val 195 sound/soc/sprd/sprd-mcdt.c *val = readl_relaxed(mcdt->base + reg); val 882 sound/soc/stm/stm32_i2s.c u32 val; val 926 sound/soc/stm/stm32_i2s.c ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val); val 930 sound/soc/stm/stm32_i2s.c if (val == I2S_IPIDR_NUMBER) { val 931 sound/soc/stm/stm32_i2s.c ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val); val 935 sound/soc/stm/stm32_i2s.c if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) { val 941 sound/soc/stm/stm32_i2s.c ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val); val 944 sound/soc/stm/stm32_i2s.c FIELD_GET(I2S_VERR_MAJ_MASK, val), val 945 sound/soc/stm/stm32_i2s.c FIELD_GET(I2S_VERR_MIN_MASK, val)); val 156 sound/soc/stm/stm32_sai.c u32 val; val 214 sound/soc/stm/stm32_sai.c val = FIELD_GET(SAI_IDR_ID_MASK, val 216 sound/soc/stm/stm32_sai.c if (val == SAI_IPIDR_NUMBER) { val 217 sound/soc/stm/stm32_sai.c val = readl_relaxed(sai->base + STM_SAI_HWCFGR); val 218 sound/soc/stm/stm32_sai.c sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val); val 220 sound/soc/stm/stm32_sai.c val); val 222 sound/soc/stm/stm32_sai.c val = readl_relaxed(sai->base + STM_SAI_VERR); val 223 sound/soc/stm/stm32_sai.c sai->conf.version = val; val 226 sound/soc/stm/stm32_sai.c FIELD_GET(SAI_VERR_MAJ_MASK, val), val 227 sound/soc/stm/stm32_sai.c FIELD_GET(SAI_VERR_MIN_MASK, val)); val 189 sound/soc/stm/stm32_sai_sub.c unsigned int val) val 197 sound/soc/stm/stm32_sai_sub.c ret = regmap_update_bits(sai->regmap, reg, mask, val); val 206 sound/soc/stm/stm32_sai_sub.c unsigned int val) val 214 sound/soc/stm/stm32_sai_sub.c ret = regmap_write_bits(sai->regmap, reg, mask, val); val 222 sound/soc/stm/stm32_sai_sub.c unsigned int reg, unsigned int *val) val 230 sound/soc/stm/stm32_sai_sub.c ret = regmap_read(sai->regmap, reg, val); val 365 sound/soc/sunxi/sun4i-codec.c u32 val; val 379 sound/soc/sunxi/sun4i-codec.c val = 0; val 382 sound/soc/sunxi/sun4i-codec.c val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION); val 386 sound/soc/sunxi/sun4i-codec.c val); val 527 sound/soc/sunxi/sun4i-codec.c u32 val; val 536 sound/soc/sunxi/sun4i-codec.c val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN); val 538 sound/soc/sunxi/sun4i-codec.c val = 0; val 542 sound/soc/sunxi/sun4i-codec.c val); val 186 sound/soc/sunxi/sun4i-i2s.c u8 val; val 190 sound/soc/sunxi/sun4i-i2s.c { .div = 2, .val = 0 }, val 191 sound/soc/sunxi/sun4i-i2s.c { .div = 4, .val = 1 }, val 192 sound/soc/sunxi/sun4i-i2s.c { .div = 6, .val = 2 }, val 193 sound/soc/sunxi/sun4i-i2s.c { .div = 8, .val = 3 }, val 194 sound/soc/sunxi/sun4i-i2s.c { .div = 12, .val = 4 }, val 195 sound/soc/sunxi/sun4i-i2s.c { .div = 16, .val = 5 }, val 200 sound/soc/sunxi/sun4i-i2s.c { .div = 1, .val = 0 }, val 201 sound/soc/sunxi/sun4i-i2s.c { .div = 2, .val = 1 }, val 202 sound/soc/sunxi/sun4i-i2s.c { .div = 4, .val = 2 }, val 203 sound/soc/sunxi/sun4i-i2s.c { .div = 6, .val = 3 }, val 204 sound/soc/sunxi/sun4i-i2s.c { .div = 8, .val = 4 }, val 205 sound/soc/sunxi/sun4i-i2s.c { .div = 12, .val = 5 }, val 206 sound/soc/sunxi/sun4i-i2s.c { .div = 16, .val = 6 }, val 207 sound/soc/sunxi/sun4i-i2s.c { .div = 24, .val = 7 }, val 212 sound/soc/sunxi/sun4i-i2s.c { .div = 1, .val = 1 }, val 213 sound/soc/sunxi/sun4i-i2s.c { .div = 2, .val = 2 }, val 214 sound/soc/sunxi/sun4i-i2s.c { .div = 4, .val = 3 }, val 215 sound/soc/sunxi/sun4i-i2s.c { .div = 6, .val = 4 }, val 216 sound/soc/sunxi/sun4i-i2s.c { .div = 8, .val = 5 }, val 217 sound/soc/sunxi/sun4i-i2s.c { .div = 12, .val = 6 }, val 218 sound/soc/sunxi/sun4i-i2s.c { .div = 16, .val = 7 }, val 219 sound/soc/sunxi/sun4i-i2s.c { .div = 24, .val = 8 }, val 220 sound/soc/sunxi/sun4i-i2s.c { .div = 32, .val = 9 }, val 221 sound/soc/sunxi/sun4i-i2s.c { .div = 48, .val = 10 }, val 222 sound/soc/sunxi/sun4i-i2s.c { .div = 64, .val = 11 }, val 223 sound/soc/sunxi/sun4i-i2s.c { .div = 96, .val = 12 }, val 224 sound/soc/sunxi/sun4i-i2s.c { .div = 128, .val = 13 }, val 225 sound/soc/sunxi/sun4i-i2s.c { .div = 176, .val = 14 }, val 226 sound/soc/sunxi/sun4i-i2s.c { .div = 192, .val = 15 }, val 253 sound/soc/sunxi/sun4i-i2s.c return bdiv->val; val 271 sound/soc/sunxi/sun4i-i2s.c return mdiv->val; val 522 sound/soc/sunxi/sun4i-i2s.c u32 val; val 528 sound/soc/sunxi/sun4i-i2s.c val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED | val 533 sound/soc/sunxi/sun4i-i2s.c val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED; val 537 sound/soc/sunxi/sun4i-i2s.c val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED; val 540 sound/soc/sunxi/sun4i-i2s.c val = 0; val 549 sound/soc/sunxi/sun4i-i2s.c val); val 554 sound/soc/sunxi/sun4i-i2s.c val = SUN4I_I2S_FMT0_FMT_I2S; val 558 sound/soc/sunxi/sun4i-i2s.c val = SUN4I_I2S_FMT0_FMT_LEFT_J; val 562 sound/soc/sunxi/sun4i-i2s.c val = SUN4I_I2S_FMT0_FMT_RIGHT_J; val 570 sound/soc/sunxi/sun4i-i2s.c SUN4I_I2S_FMT0_FMT_MASK, val); val 576 sound/soc/sunxi/sun4i-i2s.c val = SUN4I_I2S_CTRL_MODE_MASTER; val 581 sound/soc/sunxi/sun4i-i2s.c val = SUN4I_I2S_CTRL_MODE_SLAVE; val 588 sound/soc/sunxi/sun4i-i2s.c SUN4I_I2S_CTRL_MODE_MASK, val); val 595 sound/soc/sunxi/sun4i-i2s.c u32 mode, val; val 608 sound/soc/sunxi/sun4i-i2s.c val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; val 612 sound/soc/sunxi/sun4i-i2s.c val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | val 617 sound/soc/sunxi/sun4i-i2s.c val = 0; val 620 sound/soc/sunxi/sun4i-i2s.c val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; val 629 sound/soc/sunxi/sun4i-i2s.c val); val 675 sound/soc/sunxi/sun4i-i2s.c val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT; val 680 sound/soc/sunxi/sun4i-i2s.c val = 0; val 689 sound/soc/sunxi/sun4i-i2s.c val); val 29 sound/soc/sunxi/sun8i-adda-pr-regmap.c static int adda_reg_read(void *context, unsigned int reg, unsigned int *val) val 47 sound/soc/sunxi/sun8i-adda-pr-regmap.c *val = readl(base) & ADDA_PR_DATA_OUT_MASK; val 52 sound/soc/sunxi/sun8i-adda-pr-regmap.c static int adda_reg_write(void *context, unsigned int reg, unsigned int val) val 69 sound/soc/sunxi/sun8i-adda-pr-regmap.c tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT; val 253 sound/soc/sunxi/sun8i-codec.c u8 val; val 257 sound/soc/sunxi/sun8i-codec.c { .div = 1, .val = 0 }, val 258 sound/soc/sunxi/sun8i-codec.c { .div = 2, .val = 1 }, val 259 sound/soc/sunxi/sun8i-codec.c { .div = 4, .val = 2 }, val 260 sound/soc/sunxi/sun8i-codec.c { .div = 6, .val = 3 }, val 261 sound/soc/sunxi/sun8i-codec.c { .div = 8, .val = 4 }, val 262 sound/soc/sunxi/sun8i-codec.c { .div = 12, .val = 5 }, val 263 sound/soc/sunxi/sun8i-codec.c { .div = 16, .val = 6 }, val 264 sound/soc/sunxi/sun8i-codec.c { .div = 24, .val = 7 }, val 265 sound/soc/sunxi/sun8i-codec.c { .div = 32, .val = 8 }, val 266 sound/soc/sunxi/sun8i-codec.c { .div = 48, .val = 9 }, val 267 sound/soc/sunxi/sun8i-codec.c { .div = 64, .val = 10 }, val 268 sound/soc/sunxi/sun8i-codec.c { .div = 96, .val = 11 }, val 269 sound/soc/sunxi/sun8i-codec.c { .div = 128, .val = 12 }, val 270 sound/soc/sunxi/sun8i-codec.c { .div = 192, .val = 13 }, val 288 sound/soc/sunxi/sun8i-codec.c best_val = bdiv->val; val 113 sound/soc/tegra/tegra20_ac97.c unsigned short reg, unsigned short val) val 121 sound/soc/tegra/tegra20_ac97.c ((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) & val 22 sound/soc/tegra/tegra20_das.c static inline void tegra20_das_write(u32 reg, u32 val) val 24 sound/soc/tegra/tegra20_das.c regmap_write(das->regmap, reg, val); val 29 sound/soc/tegra/tegra20_das.c u32 val; val 31 sound/soc/tegra/tegra20_das.c regmap_read(das->regmap, reg, &val); val 32 sound/soc/tegra/tegra20_das.c return val; val 63 sound/soc/tegra/tegra20_i2s.c unsigned int mask = 0, val = 0; val 75 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_MASTER_ENABLE; val 87 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; val 88 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_LRCK_L_LOW; val 91 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; val 92 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_LRCK_R_LOW; val 95 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S; val 96 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_LRCK_L_LOW; val 99 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM; val 100 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_LRCK_L_LOW; val 103 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM; val 104 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_LRCK_L_LOW; val 110 sound/soc/tegra/tegra20_i2s.c regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val); val 121 sound/soc/tegra/tegra20_i2s.c unsigned int mask, val; val 127 sound/soc/tegra/tegra20_i2s.c val = TEGRA20_I2S_CTRL_BIT_SIZE_16; val 131 sound/soc/tegra/tegra20_i2s.c val = TEGRA20_I2S_CTRL_BIT_SIZE_24; val 135 sound/soc/tegra/tegra20_i2s.c val = TEGRA20_I2S_CTRL_BIT_SIZE_32; val 143 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED; val 145 sound/soc/tegra/tegra20_i2s.c regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val); val 161 sound/soc/tegra/tegra20_i2s.c val = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; val 164 sound/soc/tegra/tegra20_i2s.c val |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE; val 166 sound/soc/tegra/tegra20_i2s.c regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val); val 56 sound/soc/tegra/tegra20_spdif.c unsigned int mask = 0, val = 0; val 63 sound/soc/tegra/tegra20_spdif.c val |= TEGRA20_SPDIF_CTRL_PACK | val 70 sound/soc/tegra/tegra20_spdif.c regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val); val 25 sound/soc/tegra/tegra30_ahub.c static inline void tegra30_apbif_write(u32 reg, u32 val) val 27 sound/soc/tegra/tegra30_ahub.c regmap_write(ahub->regmap_apbif, reg, val); val 32 sound/soc/tegra/tegra30_ahub.c u32 val; val 34 sound/soc/tegra/tegra30_ahub.c regmap_read(ahub->regmap_apbif, reg, &val); val 35 sound/soc/tegra/tegra30_ahub.c return val; val 38 sound/soc/tegra/tegra30_ahub.c static inline void tegra30_audio_write(u32 reg, u32 val) val 40 sound/soc/tegra/tegra30_ahub.c regmap_write(ahub->regmap_ahub, reg, val); val 92 sound/soc/tegra/tegra30_ahub.c u32 reg, val; val 111 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); val 112 sound/soc/tegra/tegra30_ahub.c val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK | val 114 sound/soc/tegra/tegra30_ahub.c val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) | val 117 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); val 144 sound/soc/tegra/tegra30_ahub.c int reg, val; val 150 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); val 151 sound/soc/tegra/tegra30_ahub.c val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; val 152 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); val 163 sound/soc/tegra/tegra30_ahub.c int reg, val; val 169 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); val 170 sound/soc/tegra/tegra30_ahub.c val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; val 171 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); val 194 sound/soc/tegra/tegra30_ahub.c u32 reg, val; val 213 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); val 214 sound/soc/tegra/tegra30_ahub.c val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK | val 216 sound/soc/tegra/tegra30_ahub.c val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) | val 219 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); val 246 sound/soc/tegra/tegra30_ahub.c int reg, val; val 252 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); val 253 sound/soc/tegra/tegra30_ahub.c val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; val 254 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); val 265 sound/soc/tegra/tegra30_ahub.c int reg, val; val 271 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); val 272 sound/soc/tegra/tegra30_ahub.c val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; val 273 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); val 69 sound/soc/tegra/tegra30_i2s.c unsigned int mask = 0, val = 0; val 81 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_MASTER_ENABLE; val 93 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; val 94 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; val 97 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; val 98 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_LRCK_R_LOW; val 101 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; val 102 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; val 105 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; val 106 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; val 109 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; val 110 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; val 117 sound/soc/tegra/tegra30_i2s.c regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); val 129 sound/soc/tegra/tegra30_i2s.c unsigned int mask, val, reg; val 139 sound/soc/tegra/tegra30_i2s.c val = TEGRA30_I2S_CTRL_BIT_SIZE_16; val 146 sound/soc/tegra/tegra30_i2s.c regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); val 163 sound/soc/tegra/tegra30_i2s.c val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; val 166 sound/soc/tegra/tegra30_i2s.c val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE; val 168 sound/soc/tegra/tegra30_i2s.c regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val); val 191 sound/soc/tegra/tegra30_i2s.c val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) | val 193 sound/soc/tegra/tegra30_i2s.c regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val); val 167 sound/soc/ti/davinci-i2s.c int reg, u32 val) val 169 sound/soc/ti/davinci-i2s.c __raw_writel(val, dev->base + reg); val 128 sound/soc/ti/davinci-mcasp.c u32 val) val 131 sound/soc/ti/davinci-mcasp.c __raw_writel(__raw_readl(reg) | val, reg); val 135 sound/soc/ti/davinci-mcasp.c u32 val) val 138 sound/soc/ti/davinci-mcasp.c __raw_writel((__raw_readl(reg) & ~(val)), reg); val 142 sound/soc/ti/davinci-mcasp.c u32 val, u32 mask) val 145 sound/soc/ti/davinci-mcasp.c __raw_writel((__raw_readl(reg) & ~mask) | val, reg); val 149 sound/soc/ti/davinci-mcasp.c u32 val) val 151 sound/soc/ti/davinci-mcasp.c __raw_writel(val, mcasp->base + offset); val 159 sound/soc/ti/davinci-mcasp.c static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) val 163 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, ctl_reg, val); val 168 sound/soc/ti/davinci-mcasp.c if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) val 172 sound/soc/ti/davinci-mcasp.c if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) val 321 sound/soc/ti/davinci-mcasp.c u32 val = 0; val 332 sound/soc/ti/davinci-mcasp.c val = TXHCLKRST | TXCLKRST | TXFSRST; val 337 sound/soc/ti/davinci-mcasp.c mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); val 1736 sound/soc/ti/davinci-mcasp.c u32 val; val 1756 sound/soc/ti/davinci-mcasp.c ret = of_property_read_u32(np, "op-mode", &val); val 1758 sound/soc/ti/davinci-mcasp.c pdata->op_mode = val; val 1760 sound/soc/ti/davinci-mcasp.c ret = of_property_read_u32(np, "tdm-slots", &val); val 1762 sound/soc/ti/davinci-mcasp.c if (val < 2 || val > 32) { val 1769 sound/soc/ti/davinci-mcasp.c pdata->tdm_slots = val; val 1772 sound/soc/ti/davinci-mcasp.c of_serial_dir32 = of_get_property(np, "serial-dir", &val); val 1773 sound/soc/ti/davinci-mcasp.c val /= sizeof(u32); val 1776 sound/soc/ti/davinci-mcasp.c (sizeof(*of_serial_dir) * val), val 1783 sound/soc/ti/davinci-mcasp.c for (i = 0; i < val; i++) val 1786 sound/soc/ti/davinci-mcasp.c pdata->num_serializer = val; val 1815 sound/soc/ti/davinci-mcasp.c ret = of_property_read_u32(np, "tx-num-evt", &val); val 1817 sound/soc/ti/davinci-mcasp.c pdata->txnumevt = val; val 1819 sound/soc/ti/davinci-mcasp.c ret = of_property_read_u32(np, "rx-num-evt", &val); val 1821 sound/soc/ti/davinci-mcasp.c pdata->rxnumevt = val; val 1823 sound/soc/ti/davinci-mcasp.c ret = of_property_read_u32(np, "sram-size-playback", &val); val 1825 sound/soc/ti/davinci-mcasp.c pdata->sram_size_playback = val; val 1827 sound/soc/ti/davinci-mcasp.c ret = of_property_read_u32(np, "sram-size-capture", &val); val 1829 sound/soc/ti/davinci-mcasp.c pdata->sram_size_capture = val; val 1831 sound/soc/ti/davinci-mcasp.c ret = of_property_read_u32(np, "dismod", &val); val 1833 sound/soc/ti/davinci-mcasp.c if (val == 0 || val == 2 || val == 3) { val 1834 sound/soc/ti/davinci-mcasp.c pdata->dismod = DISMOD_VAL(val); val 1836 sound/soc/ti/davinci-mcasp.c dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); val 1977 sound/soc/ti/davinci-mcasp.c u32 val; val 1984 sound/soc/ti/davinci-mcasp.c val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); val 1985 sound/soc/ti/davinci-mcasp.c if (!(val & BIT(offset))) { val 2011 sound/soc/ti/davinci-mcasp.c u32 val; val 2013 sound/soc/ti/davinci-mcasp.c val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); val 2014 sound/soc/ti/davinci-mcasp.c if (!(val & BIT(offset))) { val 2028 sound/soc/ti/davinci-mcasp.c u32 val; val 2030 sound/soc/ti/davinci-mcasp.c val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); val 2031 sound/soc/ti/davinci-mcasp.c if (val & BIT(offset)) val 2041 sound/soc/ti/davinci-mcasp.c u32 val; val 2043 sound/soc/ti/davinci-mcasp.c val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); val 2044 sound/soc/ti/davinci-mcasp.c if (val & BIT(offset)) val 2089 sound/soc/ti/davinci-mcasp.c u32 val; val 2094 sound/soc/ti/davinci-mcasp.c ret = of_property_read_u32(np, "auxclk-fs-ratio", &val); val 2096 sound/soc/ti/davinci-mcasp.c mcasp->auxclk_fs_ratio = val; val 131 sound/soc/ti/davinci-mcasp.h #define TXROT(val) (val) val 133 sound/soc/ti/davinci-mcasp.h #define TXSSZ(val) (val<<4) val 134 sound/soc/ti/davinci-mcasp.h #define TXPBIT(val) (val<<8) val 135 sound/soc/ti/davinci-mcasp.h #define TXPAD(val) (val<<13) val 137 sound/soc/ti/davinci-mcasp.h #define FSXDLY(val) (val<<16) val 142 sound/soc/ti/davinci-mcasp.h #define RXROT(val) (val) val 144 sound/soc/ti/davinci-mcasp.h #define RXSSZ(val) (val<<4) val 145 sound/soc/ti/davinci-mcasp.h #define RXPBIT(val) (val<<8) val 146 sound/soc/ti/davinci-mcasp.h #define RXPAD(val) (val<<13) val 148 sound/soc/ti/davinci-mcasp.h #define FSRDLY(val) (val<<16) val 156 sound/soc/ti/davinci-mcasp.h #define FSXMOD(val) (val<<7) val 164 sound/soc/ti/davinci-mcasp.h #define FSRMOD(val) (val<<7) val 169 sound/soc/ti/davinci-mcasp.h #define ACLKXDIV(val) (val) val 178 sound/soc/ti/davinci-mcasp.h #define ACLKRDIV(val) (val) val 188 sound/soc/ti/davinci-mcasp.h #define AHCLKXDIV(val) (val) val 197 sound/soc/ti/davinci-mcasp.h #define AHCLKRDIV(val) (val) val 205 sound/soc/ti/davinci-mcasp.h #define MODE(val) (val) val 221 sound/soc/ti/davinci-mcasp.h #define LBGENMODE(val) (val<<2) val 257 sound/soc/ti/davinci-mcasp.h #define MUTENA(val) (val) val 28 sound/soc/ti/davinci-vcif.c #define MOD_REG_BIT(val, mask, set) do { \ val 30 sound/soc/ti/davinci-vcif.c val |= mask; \ val 32 sound/soc/ti/davinci-vcif.c val &= ~mask; \ val 51 sound/soc/ti/omap-dmic.c static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val) val 53 sound/soc/ti/omap-dmic.c writel_relaxed(val, dmic->io_base + reg); val 282 sound/soc/ti/omap-mcbsp-priv.h static inline void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) val 287 sound/soc/ti/omap-mcbsp-priv.h ((u16 *)mcbsp->reg_cache)[reg] = (u16)val; val 288 sound/soc/ti/omap-mcbsp-priv.h writew_relaxed((u16)val, addr); val 290 sound/soc/ti/omap-mcbsp-priv.h ((u32 *)mcbsp->reg_cache)[reg] = val; val 291 sound/soc/ti/omap-mcbsp-priv.h writel_relaxed(val, addr); val 311 sound/soc/ti/omap-mcbsp-priv.h #define MCBSP_WRITE(mcbsp, reg, val) \ val 312 sound/soc/ti/omap-mcbsp-priv.h omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val) val 65 sound/soc/ti/omap-mcbsp-st.c static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) val 67 sound/soc/ti/omap-mcbsp-st.c writel_relaxed(val, mcbsp->st_data->io_base_st + reg); val 76 sound/soc/ti/omap-mcbsp-st.c #define MCBSP_ST_WRITE(mcbsp, reg, val) \ val 77 sound/soc/ti/omap-mcbsp-st.c omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val) val 119 sound/soc/ti/omap-mcbsp-st.c u16 val, i; val 121 sound/soc/ti/omap-mcbsp-st.c val = MCBSP_ST_READ(mcbsp, SSELCR); val 123 sound/soc/ti/omap-mcbsp-st.c if (val & ST_COEFFWREN) val 124 sound/soc/ti/omap-mcbsp-st.c MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); val 126 sound/soc/ti/omap-mcbsp-st.c MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN); val 133 sound/soc/ti/omap-mcbsp-st.c val = MCBSP_ST_READ(mcbsp, SSELCR); val 134 sound/soc/ti/omap-mcbsp-st.c while (!(val & ST_COEFFWRDONE) && (++i < 1000)) val 135 sound/soc/ti/omap-mcbsp-st.c val = MCBSP_ST_READ(mcbsp, SSELCR); val 137 sound/soc/ti/omap-mcbsp-st.c MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); val 265 sound/soc/ti/omap-mcbsp-st.c int val, tmp, status, i = 0; val 272 sound/soc/ti/omap-mcbsp-st.c status = sscanf(buf, "%d%n", &val, &tmp); val 277 sound/soc/ti/omap-mcbsp-st.c if (val < -32768 || val > 32767) { val 281 sound/soc/ti/omap-mcbsp-st.c st_data->taps[i++] = val; val 410 sound/soc/ti/omap-mcbsp-st.c int val = uc->value.integer.value[0]; \ val 412 sound/soc/ti/omap-mcbsp-st.c if (val < min || val > max) \ val 416 sound/soc/ti/omap-mcbsp-st.c return omap_mcbsp_st_set_chgain(mcbsp, channel, val); \ val 517 sound/soc/ti/omap-mcbsp.c #define valid_threshold(m, val) ((val) <= max_thres(m)) val 532 sound/soc/ti/omap-mcbsp.c unsigned long val; \ val 535 sound/soc/ti/omap-mcbsp.c status = kstrtoul(buf, 0, &val); \ val 539 sound/soc/ti/omap-mcbsp.c if (!valid_threshold(mcbsp, val)) \ val 542 sound/soc/ti/omap-mcbsp.c mcbsp->prop = val; \ val 67 sound/soc/ti/omap-mcpdm.c static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val) val 69 sound/soc/ti/omap-mcpdm.c writel_relaxed(val, mcpdm->io_base + reg); val 79 sound/soc/txx9/txx9aclc-ac97.c unsigned short val) val 85 sound/soc/txx9/txx9aclc-ac97.c (val << ACREGACC_DAT_SHIFT), val 148 sound/soc/ux500/mop500_ab8500.c unsigned int val = ucontrol->value.enumerated.item[0]; val 150 sound/soc/ux500/mop500_ab8500.c if (val > (unsigned int)MCLK_ULPCLK) val 152 sound/soc/ux500/mop500_ab8500.c if (drvdata->mclk_sel == val) val 155 sound/soc/ux500/mop500_ab8500.c drvdata->mclk_sel = val; val 247 sound/soc/xilinx/xlnx_formatter_pcm.c u32 val, retries = 0; val 249 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(mmio_base + XLNX_AUD_CTRL); val 250 sound/soc/xilinx/xlnx_formatter_pcm.c val |= AUD_CTRL_RESET_MASK; val 251 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val, mmio_base + XLNX_AUD_CTRL); val 253 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(mmio_base + XLNX_AUD_CTRL); val 255 sound/soc/xilinx/xlnx_formatter_pcm.c while ((val & AUD_CTRL_RESET_MASK) && (retries < 100)) { val 258 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(mmio_base + XLNX_AUD_CTRL); val 260 sound/soc/xilinx/xlnx_formatter_pcm.c if (val & AUD_CTRL_RESET_MASK) val 268 sound/soc/xilinx/xlnx_formatter_pcm.c u32 val; val 270 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(mmio_base + XLNX_AUD_CTRL); val 271 sound/soc/xilinx/xlnx_formatter_pcm.c val &= ~AUD_CTRL_IOC_IRQ_MASK; val 273 sound/soc/xilinx/xlnx_formatter_pcm.c val &= ~AUD_CTRL_TOUT_IRQ_MASK; val 275 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val, mmio_base + XLNX_AUD_CTRL); val 280 sound/soc/xilinx/xlnx_formatter_pcm.c u32 val; val 286 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(reg); val 287 sound/soc/xilinx/xlnx_formatter_pcm.c if (val & AUD_STS_IOC_IRQ_MASK) { val 288 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val & AUD_STS_IOC_IRQ_MASK, reg); val 299 sound/soc/xilinx/xlnx_formatter_pcm.c u32 val; val 305 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(reg); val 306 sound/soc/xilinx/xlnx_formatter_pcm.c if (val & AUD_STS_IOC_IRQ_MASK) { val 307 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val & AUD_STS_IOC_IRQ_MASK, reg); val 319 sound/soc/xilinx/xlnx_formatter_pcm.c u32 val, data_format_mode; val 358 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG); val 360 sound/soc/xilinx/xlnx_formatter_pcm.c if (!(val & data_format_mode)) val 363 sound/soc/xilinx/xlnx_formatter_pcm.c stream_data->xfer_mode = (val & data_xfer_mode) >> data_xfer_shift; val 364 sound/soc/xilinx/xlnx_formatter_pcm.c stream_data->ch_limit = (val & ch_count_mask) >> ch_count_shift; val 383 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(stream_data->mmio + XLNX_AUD_CTRL); val 384 sound/soc/xilinx/xlnx_formatter_pcm.c val |= AUD_CTRL_IOC_IRQ_MASK; val 385 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val, stream_data->mmio + XLNX_AUD_CTRL); val 429 sound/soc/xilinx/xlnx_formatter_pcm.c u32 low, high, active_ch, val, bytes_per_ch, bits_per_sample; val 445 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(stream_data->mmio + XLNX_AUD_STS); val 446 sound/soc/xilinx/xlnx_formatter_pcm.c if (val & AUD_STS_CH_STS_MASK) { val 469 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(stream_data->mmio + XLNX_AUD_CTRL); val 473 sound/soc/xilinx/xlnx_formatter_pcm.c val |= (BIT_DEPTH_8 << AUD_CTRL_DATA_WIDTH_SHIFT); val 476 sound/soc/xilinx/xlnx_formatter_pcm.c val |= (BIT_DEPTH_16 << AUD_CTRL_DATA_WIDTH_SHIFT); val 479 sound/soc/xilinx/xlnx_formatter_pcm.c val |= (BIT_DEPTH_20 << AUD_CTRL_DATA_WIDTH_SHIFT); val 482 sound/soc/xilinx/xlnx_formatter_pcm.c val |= (BIT_DEPTH_24 << AUD_CTRL_DATA_WIDTH_SHIFT); val 485 sound/soc/xilinx/xlnx_formatter_pcm.c val |= (BIT_DEPTH_32 << AUD_CTRL_DATA_WIDTH_SHIFT); val 491 sound/soc/xilinx/xlnx_formatter_pcm.c val |= active_ch << AUD_CTRL_ACTIVE_CH_SHIFT; val 492 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val, stream_data->mmio + XLNX_AUD_CTRL); val 494 sound/soc/xilinx/xlnx_formatter_pcm.c val = (params_periods(params) << PERIOD_CFG_PERIODS_SHIFT) val 496 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val, stream_data->mmio + XLNX_AUD_PERIOD_CONFIG); val 511 sound/soc/xilinx/xlnx_formatter_pcm.c u32 val; val 519 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(stream_data->mmio + XLNX_AUD_CTRL); val 520 sound/soc/xilinx/xlnx_formatter_pcm.c val |= AUD_CTRL_DMA_EN_MASK; val 521 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val, stream_data->mmio + XLNX_AUD_CTRL); val 526 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(stream_data->mmio + XLNX_AUD_CTRL); val 527 sound/soc/xilinx/xlnx_formatter_pcm.c val &= ~AUD_CTRL_DMA_EN_MASK; val 528 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val, stream_data->mmio + XLNX_AUD_CTRL); val 565 sound/soc/xilinx/xlnx_formatter_pcm.c u32 val; val 600 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(aud_drv_data->mmio + XLNX_AUD_CORE_CONFIG); val 601 sound/soc/xilinx/xlnx_formatter_pcm.c if (val & AUD_CFG_MM2S_MASK) { val 627 sound/soc/xilinx/xlnx_formatter_pcm.c if (val & AUD_CFG_S2MM_MASK) { val 57 sound/soc/xilinx/xlnx_spdif.c u32 val; val 60 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + XSPDIF_IRQ_STS_REG); val 61 sound/soc/xilinx/xlnx_spdif.c if (val & XSPDIF_CH_STS_MASK) { val 62 sound/soc/xilinx/xlnx_spdif.c writel(val & XSPDIF_CH_STS_MASK, val 64 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + val 66 sound/soc/xilinx/xlnx_spdif.c writel(val & ~XSPDIF_CH_STS_MASK, val 80 sound/soc/xilinx/xlnx_spdif.c u32 val; val 83 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + XSPDIF_CONTROL_REG); val 84 sound/soc/xilinx/xlnx_spdif.c val |= XSPDIF_FIFO_FLUSH_MASK; val 85 sound/soc/xilinx/xlnx_spdif.c writel(val, ctx->base + XSPDIF_CONTROL_REG); val 109 sound/soc/xilinx/xlnx_spdif.c u32 val, clk_div, clk_cfg; val 141 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + XSPDIF_CONTROL_REG); val 142 sound/soc/xilinx/xlnx_spdif.c val &= ~XSPDIF_CLOCK_CONFIG_BITS_MASK; val 143 sound/soc/xilinx/xlnx_spdif.c val |= clk_cfg << XSPDIF_CLOCK_CONFIG_BITS_SHIFT; val 144 sound/soc/xilinx/xlnx_spdif.c writel(val, ctx->base + XSPDIF_CONTROL_REG); val 171 sound/soc/xilinx/xlnx_spdif.c u32 val; val 175 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + XSPDIF_CONTROL_REG); val 180 sound/soc/xilinx/xlnx_spdif.c val |= XSPDIF_CORE_ENABLE_MASK; val 181 sound/soc/xilinx/xlnx_spdif.c writel(val, ctx->base + XSPDIF_CONTROL_REG); val 188 sound/soc/xilinx/xlnx_spdif.c val &= ~XSPDIF_CORE_ENABLE_MASK; val 189 sound/soc/xilinx/xlnx_spdif.c writel(val, ctx->base + XSPDIF_CONTROL_REG); val 103 sound/soc/zte/zx-i2s.c unsigned long val; val 105 sound/soc/zte/zx-i2s.c val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL); val 107 sound/soc/zte/zx-i2s.c val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN; val 109 sound/soc/zte/zx-i2s.c val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN); val 110 sound/soc/zte/zx-i2s.c writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL); val 115 sound/soc/zte/zx-i2s.c unsigned long val; val 117 sound/soc/zte/zx-i2s.c val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL); val 119 sound/soc/zte/zx-i2s.c val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN; val 121 sound/soc/zte/zx-i2s.c val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN); val 122 sound/soc/zte/zx-i2s.c writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL); val 127 sound/soc/zte/zx-i2s.c unsigned long val; val 129 sound/soc/zte/zx-i2s.c val = readl_relaxed(base + ZX_I2S_FIFO_CTRL); val 130 sound/soc/zte/zx-i2s.c val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8); val 132 sound/soc/zte/zx-i2s.c val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN; val 134 sound/soc/zte/zx-i2s.c val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN; val 135 sound/soc/zte/zx-i2s.c writel_relaxed(val, base + ZX_I2S_FIFO_CTRL); val 140 sound/soc/zte/zx-i2s.c unsigned long val; val 142 sound/soc/zte/zx-i2s.c val = readl_relaxed(base + ZX_I2S_FIFO_CTRL); val 143 sound/soc/zte/zx-i2s.c val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16); val 145 sound/soc/zte/zx-i2s.c val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN; val 147 sound/soc/zte/zx-i2s.c val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN; val 148 sound/soc/zte/zx-i2s.c writel_relaxed(val, base + ZX_I2S_FIFO_CTRL); val 178 sound/soc/zte/zx-i2s.c unsigned long val; val 180 sound/soc/zte/zx-i2s.c val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL); val 181 sound/soc/zte/zx-i2s.c val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK | val 187 sound/soc/zte/zx-i2s.c val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S); val 190 sound/soc/zte/zx-i2s.c val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF); val 193 sound/soc/zte/zx-i2s.c val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF); val 204 sound/soc/zte/zx-i2s.c val |= ZX_I2S_TIMING_SLAVE; val 209 sound/soc/zte/zx-i2s.c val |= ZX_I2S_TIMING_MAST; val 216 sound/soc/zte/zx-i2s.c writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL); val 228 sound/soc/zte/zx-i2s.c unsigned long val; val 234 sound/soc/zte/zx-i2s.c val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL); val 235 sound/soc/zte/zx-i2s.c val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK | val 253 sound/soc/zte/zx-i2s.c val |= ZX_I2S_TIMING_TS_WIDTH(ts_width) | ZX_I2S_TIMING_DATA_SIZE(len); val 272 sound/soc/zte/zx-i2s.c val |= ZX_I2S_TIMING_LANE(lane); val 273 sound/soc/zte/zx-i2s.c val |= ZX_I2S_TIMING_TSCFG(chn_cfg); val 274 sound/soc/zte/zx-i2s.c val |= ZX_I2S_TIMING_CHN(ch_num); val 275 sound/soc/zte/zx-i2s.c writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL); val 143 sound/soc/zte/zx-spdif.c u32 val, ch_num, rate; val 148 sound/soc/zte/zx-spdif.c val = readl_relaxed(zx_spdif->reg_base + ZX_CTRL); val 149 sound/soc/zte/zx-spdif.c val &= ~ZX_CTRL_MODA_MASK; val 152 sound/soc/zte/zx-spdif.c val |= ZX_CTRL_MODA_16; val 156 sound/soc/zte/zx-spdif.c val |= ZX_CTRL_MODA_18; val 160 sound/soc/zte/zx-spdif.c val |= ZX_CTRL_MODA_20; val 164 sound/soc/zte/zx-spdif.c val |= ZX_CTRL_MODA_24; val 173 sound/soc/zte/zx-spdif.c val |= ZX_CTRL_DOUBLE_TRACK; val 175 sound/soc/zte/zx-spdif.c val |= ZX_CTRL_LEFT_TRACK; val 176 sound/soc/zte/zx-spdif.c writel_relaxed(val, zx_spdif->reg_base + ZX_CTRL); val 178 sound/soc/zte/zx-spdif.c val = readl_relaxed(zx_spdif->reg_base + ZX_VALID_BIT); val 179 sound/soc/zte/zx-spdif.c val &= ~ZX_VALID_TRACK_MASK; val 181 sound/soc/zte/zx-spdif.c val |= ZX_VALID_DOUBLE_TRACK; val 183 sound/soc/zte/zx-spdif.c val |= ZX_VALID_RIGHT_TRACK; val 184 sound/soc/zte/zx-spdif.c writel_relaxed(val, zx_spdif->reg_base + ZX_VALID_BIT); val 195 sound/soc/zte/zx-spdif.c u32 val; val 197 sound/soc/zte/zx-spdif.c val = readl_relaxed(base + ZX_CTRL); val 198 sound/soc/zte/zx-spdif.c val &= ~(ZX_CTRL_ENB_MASK | ZX_CTRL_TX_MASK); val 199 sound/soc/zte/zx-spdif.c val |= on ? ZX_CTRL_OPEN : ZX_CTRL_CLOSE; val 200 sound/soc/zte/zx-spdif.c writel_relaxed(val, base + ZX_CTRL); val 202 sound/soc/zte/zx-spdif.c val = readl_relaxed(base + ZX_FIFOCTRL); val 203 sound/soc/zte/zx-spdif.c val &= ~ZX_FIFOCTRL_TX_DMA_EN_MASK; val 205 sound/soc/zte/zx-spdif.c val |= ZX_FIFOCTRL_TX_DMA_EN; val 206 sound/soc/zte/zx-spdif.c writel_relaxed(val, base + ZX_FIFOCTRL); val 212 sound/soc/zte/zx-spdif.c u32 val; val 218 sound/soc/zte/zx-spdif.c val = readl_relaxed(zx_spdif->reg_base + ZX_FIFOCTRL); val 219 sound/soc/zte/zx-spdif.c val |= ZX_FIFOCTRL_TX_FIFO_RST; val 220 sound/soc/zte/zx-spdif.c writel_relaxed(val, zx_spdif->reg_base + ZX_FIFOCTRL); val 292 sound/soc/zte/zx-spdif.c u32 val; val 299 sound/soc/zte/zx-spdif.c val = readl_relaxed(base + ZX_FIFOCTRL); val 300 sound/soc/zte/zx-spdif.c val &= ~(ZX_FIFOCTRL_TXTH_MASK | ZX_FIFOCTRL_TX_FIFO_RST_MASK); val 301 sound/soc/zte/zx-spdif.c val |= ZX_FIFOCTRL_TXTH(8); val 302 sound/soc/zte/zx-spdif.c writel_relaxed(val, base + ZX_FIFOCTRL); val 88 sound/soc/zte/zx-tdm.c static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val) val 90 sound/soc/zte/zx-tdm.c writel_relaxed(val, tdm->regbase + reg); val 95 sound/soc/zte/zx-tdm.c unsigned long val; val 97 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_PROCESS_CTRL); val 99 sound/soc/zte/zx-tdm.c val |= PROCESS_TX_EN | PROCESS_TDM_EN; val 101 sound/soc/zte/zx-tdm.c val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN); val 102 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_PROCESS_CTRL, val); val 107 sound/soc/zte/zx-tdm.c unsigned long val; val 109 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_PROCESS_CTRL); val 111 sound/soc/zte/zx-tdm.c val |= PROCESS_RX_EN | PROCESS_TDM_EN; val 113 sound/soc/zte/zx-tdm.c val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN); val 114 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_PROCESS_CTRL, val); val 119 sound/soc/zte/zx-tdm.c unsigned long val; val 121 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL); val 122 sound/soc/zte/zx-tdm.c val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES; val 124 sound/soc/zte/zx-tdm.c val |= FIFO_CTRL_TX_DMA_EN; val 126 sound/soc/zte/zx-tdm.c val &= ~FIFO_CTRL_TX_DMA_EN; val 127 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val); val 132 sound/soc/zte/zx-tdm.c unsigned long val; val 134 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL); val 135 sound/soc/zte/zx-tdm.c val |= FIFO_CTRL_RX_RST | DEAGULT_FIFO_THRES; val 137 sound/soc/zte/zx-tdm.c val |= FIFO_CTRL_RX_DMA_EN; val 139 sound/soc/zte/zx-tdm.c val &= ~FIFO_CTRL_RX_DMA_EN; val 140 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val); val 166 sound/soc/zte/zx-tdm.c unsigned long val; val 168 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_TIMING_CTRL); val 169 sound/soc/zte/zx-tdm.c val &= ~(TIMING_SYNC_WIDTH_MASK | TIMING_MS_MASK); val 170 sound/soc/zte/zx-tdm.c val |= TIMING_DEFAULT_WIDTH << TIMING_WIDTH_SHIFT; val 175 sound/soc/zte/zx-tdm.c val |= TIMING_MASTER_MODE; val 179 sound/soc/zte/zx-tdm.c val &= ~TIMING_MASTER_MODE; val 187 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_TIMING_CTRL, val); val 202 sound/soc/zte/zx-tdm.c unsigned long val; val 218 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_TIMING_CTRL); val 219 sound/soc/zte/zx-tdm.c val |= TIMING_TS_WIDTH(ts_width) | TIMING_TS_NUM(1); val 220 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_TIMING_CTRL, val); val 235 sound/soc/zte/zx-tdm.c unsigned int val; val 241 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(zx_tdm, REG_RX_FIFO_CTRL); val 242 sound/soc/zte/zx-tdm.c val |= FIFOCTRL_RX_FIFO_RST; val 243 sound/soc/zte/zx-tdm.c zx_tdm_writel(zx_tdm, REG_RX_FIFO_CTRL, val); val 247 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(zx_tdm, REG_TX_FIFO_CTRL); val 248 sound/soc/zte/zx-tdm.c val |= FIFOCTRL_TX_FIFO_RST; val 249 sound/soc/zte/zx-tdm.c zx_tdm_writel(zx_tdm, REG_TX_FIFO_CTRL, val); val 324 sound/soc/zte/zx-tdm.c unsigned int val; val 328 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_TIMING_CTRL); val 329 sound/soc/zte/zx-tdm.c val |= TIMING_LSB_FIRST; val 330 sound/soc/zte/zx-tdm.c val &= ~TIMING_CLK_SEL_MASK; val 331 sound/soc/zte/zx-tdm.c val |= TIMING_CLK_SEL_DEF; val 332 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_TIMING_CTRL, val); val 342 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL); val 343 sound/soc/zte/zx-tdm.c val &= ~(RXTH_MASK | RX_FIFO_RST_MASK); val 344 sound/soc/zte/zx-tdm.c val |= FIFOCTRL_THRESHOLD(8); val 345 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val); val 347 sound/soc/zte/zx-tdm.c val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL); val 348 sound/soc/zte/zx-tdm.c val &= ~(TXTH_MASK | TX_FIFO_RST_MASK); val 349 sound/soc/zte/zx-tdm.c val |= FIFOCTRL_THRESHOLD(8); val 350 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val); val 265 sound/sparc/cs4231.c static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val, val 269 sound/sparc/cs4231.c return writeb(val, reg_addr); val 271 sound/sparc/cs4231.c return sbus_writeb(val, reg_addr); val 283 sound/sparc/cs4231.c int val = __cs4231_readb(chip, CS4231U(chip, REGSEL)); val 284 sound/sparc/cs4231.c if ((val & CS4231_INIT) == 0) val 351 sound/sparc/cs4231.c int val = __cs4231_readb(chip, CS4231U(chip, REGSEL)); val 352 sound/sparc/cs4231.c if ((val & CS4231_INIT) == 0) val 1383 sound/sparc/cs4231.c unsigned short val; val 1385 sound/sparc/cs4231.c val = (ucontrol->value.integer.value[0] & mask); val 1387 sound/sparc/cs4231.c val = mask - val; val 1388 sound/sparc/cs4231.c val <<= shift; val 1392 sound/sparc/cs4231.c val = (chip->image[reg] & ~(mask << shift)) | val; val 1393 sound/sparc/cs4231.c change = val != chip->image[reg]; val 1394 sound/sparc/cs4231.c snd_cs4231_out(chip, reg, val); val 898 sound/sparc/dbri.c int val; val 931 sound/sparc/dbri.c val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; val 932 sound/sparc/dbri.c *(cmd++) = DBRI_CMD(D_DTS, 0, val); val 937 sound/sparc/dbri.c val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; val 938 sound/sparc/dbri.c *(cmd++) = DBRI_CMD(D_DTS, 0, val); val 957 sound/sparc/dbri.c int val; val 970 sound/sparc/dbri.c val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe; val 971 sound/sparc/dbri.c *(cmd++) = DBRI_CMD(D_DTS, 0, val); val 975 sound/sparc/dbri.c val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe; val 976 sound/sparc/dbri.c *(cmd++) = DBRI_CMD(D_DTS, 0, val); val 1246 sound/sparc/dbri.c int val; val 1251 sound/sparc/dbri.c val = D_DTS_VO | D_DTS_VI | D_DTS_INS val 1253 sound/sparc/dbri.c *(cmd++) = DBRI_CMD(D_DTS, 0, val); val 1484 sound/sparc/dbri.c int i, val; val 1500 sound/sparc/dbri.c val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); val 1501 sound/sparc/dbri.c sbus_writel(val, dbri->regs + REG2); val 1502 sound/sparc/dbri.c dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val); val 1843 sound/sparc/dbri.c int val = D_INTR_GETVAL(x); val 1853 sound/sparc/dbri.c cmds[command], val); val 1896 sound/sparc/dbri.c val = reverse_bytes(val, dbri->pipes[channel].length); val 1899 sound/sparc/dbri.c *(dbri->pipes[channel].recv_fixed_ptr) = val; val 2374 sound/sparc/dbri.c unsigned short val; val 2379 sound/sparc/dbri.c val = (ucontrol->value.integer.value[0] & mask); val 2381 sound/sparc/dbri.c val = mask - val; val 2382 sound/sparc/dbri.c val <<= shift; val 2386 sound/sparc/dbri.c ~(mask << shift)) | val; val 2387 sound/sparc/dbri.c changed = (val != dbri->mm.data[elem]); val 2390 sound/sparc/dbri.c ~(mask << shift)) | val; val 2391 sound/sparc/dbri.c changed = (val != dbri->mm.ctrl[elem - 4]); val 84 sound/spi/at73c213.c snd_at73c213_write_reg(struct snd_at73c213 *chip, u8 reg, u8 val) val 96 sound/spi/at73c213.c chip->spi_wbuffer[1] = val; val 105 sound/spi/at73c213.c chip->reg_image[reg] = val; val 239 sound/spi/at73c213.c int val; val 241 sound/spi/at73c213.c val = ssc_readl(chip->ssc->regs, TFMR); val 242 sound/spi/at73c213.c val = SSC_BFINS(TFMR_DATNB, channels - 1, val); val 243 sound/spi/at73c213.c ssc_writel(chip->ssc->regs, TFMR, val); val 433 sound/spi/at73c213.c unsigned short val; val 435 sound/spi/at73c213.c val = (ucontrol->value.integer.value[0] & mask); val 437 sound/spi/at73c213.c val = mask - val; val 438 sound/spi/at73c213.c val <<= shift; val 442 sound/spi/at73c213.c val = (chip->reg_image[reg] & ~(mask << shift)) | val; val 443 sound/spi/at73c213.c change = val != chip->reg_image[reg]; val 444 sound/spi/at73c213.c retval = snd_at73c213_write_reg(chip, reg, val); val 581 sound/spi/at73c213.c unsigned short val; val 584 sound/spi/at73c213.c val = mask; val 586 sound/spi/at73c213.c val = 0; val 589 sound/spi/at73c213.c val = mask - val; val 590 sound/spi/at73c213.c val <<= shift; val 594 sound/spi/at73c213.c val |= (chip->reg_image[reg] & ~(mask << shift)); val 595 sound/spi/at73c213.c change = val != chip->reg_image[reg]; val 597 sound/spi/at73c213.c retval = snd_at73c213_write_reg(chip, reg, val); val 91 sound/synth/emux/emux_effect.c effect = fx->val[type]; val 112 sound/synth/emux/emux_effect.c effect = *(unsigned short*)&fx->val[type]; val 130 sound/synth/emux/emux_effect.c addr = (short)fx->val[hi]; val 133 sound/synth/emux/emux_effect.c addr += (short)fx->val[lo]; val 143 sound/synth/emux/emux_effect.c struct snd_midi_channel *chan, int type, int val) val 155 sound/synth/emux/emux_effect.c snd_emux_send_effect(port, chan, type, val, mode); val 164 sound/synth/emux/emux_effect.c int type, int val, int mode) val 180 sound/synth/emux/emux_effect.c fx->val[type] = val; val 19 sound/synth/emux/emux_nrpn.c int (*convert)(int val); val 41 sound/synth/emux/emux_nrpn.c int type, int val, int mode) val 46 sound/synth/emux/emux_nrpn.c cval = table[i].convert(val); val 86 sound/synth/emux/emux_nrpn.c static int fx_delay(int val); val 87 sound/synth/emux/emux_nrpn.c static int fx_attack(int val); val 88 sound/synth/emux/emux_nrpn.c static int fx_hold(int val); val 89 sound/synth/emux/emux_nrpn.c static int fx_decay(int val); val 90 sound/synth/emux/emux_nrpn.c static int fx_the_value(int val); val 91 sound/synth/emux/emux_nrpn.c static int fx_twice_value(int val); val 92 sound/synth/emux/emux_nrpn.c static int fx_conv_pitch(int val); val 93 sound/synth/emux/emux_nrpn.c static int fx_conv_Q(int val); val 128 sound/synth/emux/emux_nrpn.c static int fx_delay(int val) val 130 sound/synth/emux/emux_nrpn.c return (unsigned short)snd_sf_calc_parm_delay(val); val 133 sound/synth/emux/emux_nrpn.c static int fx_attack(int val) val 135 sound/synth/emux/emux_nrpn.c return (unsigned short)snd_sf_calc_parm_attack(val); val 138 sound/synth/emux/emux_nrpn.c static int fx_hold(int val) val 140 sound/synth/emux/emux_nrpn.c return (unsigned short)snd_sf_calc_parm_hold(val); val 143 sound/synth/emux/emux_nrpn.c static int fx_decay(int val) val 145 sound/synth/emux/emux_nrpn.c return (unsigned short)snd_sf_calc_parm_decay(val); val 148 sound/synth/emux/emux_nrpn.c static int fx_the_value(int val) val 150 sound/synth/emux/emux_nrpn.c return (unsigned short)(val & 0xff); val 153 sound/synth/emux/emux_nrpn.c static int fx_twice_value(int val) val 155 sound/synth/emux/emux_nrpn.c return (unsigned short)((val * 2) & 0xff); val 158 sound/synth/emux/emux_nrpn.c static int fx_conv_pitch(int val) val 160 sound/synth/emux/emux_nrpn.c return (short)(val * 4096 / 1200); val 163 sound/synth/emux/emux_nrpn.c static int fx_conv_Q(int val) val 165 sound/synth/emux/emux_nrpn.c return (unsigned short)((val / 8) & 0xff); val 209 sound/synth/emux/emux_nrpn.c static int gs_cutoff(int val) val 211 sound/synth/emux/emux_nrpn.c return (val - 64) * gs_sense[FX_CUTOFF] / 50; val 215 sound/synth/emux/emux_nrpn.c static int gs_filterQ(int val) val 217 sound/synth/emux/emux_nrpn.c return (val - 64) * gs_sense[FX_RESONANCE] / 50; val 221 sound/synth/emux/emux_nrpn.c static int gs_attack(int val) val 223 sound/synth/emux/emux_nrpn.c return -(val - 64) * gs_sense[FX_ATTACK] / 50; val 227 sound/synth/emux/emux_nrpn.c static int gs_decay(int val) val 229 sound/synth/emux/emux_nrpn.c return -(val - 64) * gs_sense[FX_RELEASE] / 50; val 233 sound/synth/emux/emux_nrpn.c static int gs_release(int val) val 235 sound/synth/emux/emux_nrpn.c return -(val - 64) * gs_sense[FX_RELEASE] / 50; val 239 sound/synth/emux/emux_nrpn.c static int gs_vib_rate(int val) val 241 sound/synth/emux/emux_nrpn.c return (val - 64) * gs_sense[FX_VIBRATE] / 50; val 245 sound/synth/emux/emux_nrpn.c static int gs_vib_depth(int val) val 247 sound/synth/emux/emux_nrpn.c return (val - 64) * gs_sense[FX_VIBDEPTH] / 50; val 251 sound/synth/emux/emux_nrpn.c static int gs_vib_delay(int val) val 253 sound/synth/emux/emux_nrpn.c return -(val - 64) * gs_sense[FX_VIBDELAY] / 50; val 284 sound/synth/emux/emux_nrpn.c int val; val 287 sound/synth/emux/emux_nrpn.c val = (chan->control[MIDI_CTL_MSB_DATA_ENTRY] << 7) | val 289 sound/synth/emux/emux_nrpn.c val -= 8192; val 293 sound/synth/emux/emux_nrpn.c val, EMUX_FX_FLAG_SET); val 299 sound/synth/emux/emux_nrpn.c int val; val 302 sound/synth/emux/emux_nrpn.c val = chan->control[MIDI_CTL_MSB_DATA_ENTRY]; val 306 sound/synth/emux/emux_nrpn.c val, EMUX_FX_FLAG_ADD); val 317 sound/synth/emux/emux_nrpn.c static int xg_cutoff(int val) val 319 sound/synth/emux/emux_nrpn.c return (val - 64) * xg_sense[FX_CUTOFF] / 64; val 323 sound/synth/emux/emux_nrpn.c static int xg_filterQ(int val) val 325 sound/synth/emux/emux_nrpn.c return (val - 64) * xg_sense[FX_RESONANCE] / 64; val 329 sound/synth/emux/emux_nrpn.c static int xg_attack(int val) val 331 sound/synth/emux/emux_nrpn.c return -(val - 64) * xg_sense[FX_ATTACK] / 64; val 335 sound/synth/emux/emux_nrpn.c static int xg_release(int val) val 337 sound/synth/emux/emux_nrpn.c return -(val - 64) * xg_sense[FX_RELEASE] / 64; val 34 sound/synth/emux/emux_oss.c int ch, int param, int val, int atomic, int hop); val 481 sound/synth/emux/emux_oss.c fake_event(struct snd_emux *emu, struct snd_emux_port *port, int ch, int param, int val, int atomic, int hop) val 488 sound/synth/emux/emux_oss.c ev.data.control.value = val; val 779 sound/synth/emux/emux_synth.c vol += fx->val[EMUX_FX_ATTEN]; val 842 sound/synth/emux/emux_synth.c offset += fx->val[EMUX_FX_INIT_PITCH]; val 862 sound/synth/emux/emux_synth.c int val; val 866 sound/synth/emux/emux_synth.c val = chan->control[MIDI_CTL_MSB_BANK]; val 867 sound/synth/emux/emux_synth.c if (val == 127) val 54 sound/synth/emux/emux_voice.h struct snd_midi_channel *chan, int type, int val); val 56 sound/synth/emux/emux_voice.h struct snd_midi_channel *chan, int type, int val, int mode); val 886 sound/synth/emux/soundfont.c int val = (0x7f * 92 - msec) / 92; val 887 sound/synth/emux/soundfont.c if (val < 1) val = 1; val 888 sound/synth/emux/soundfont.c if (val >= 126) val = 126; val 889 sound/synth/emux/soundfont.c return val; val 933 sound/synth/emux/soundfont.c #define calc_gus_sustain(val) (0x7f - snd_sf_vol_table[(val)/2]) val 934 sound/synth/emux/soundfont.c #define calc_gus_attenuation(val) snd_sf_vol_table[(val)/2] val 61 sound/usb/6fire/firmware.c u8 val = 0; val 66 sound/usb/6fire/firmware.c val |= (hval << 4); val 70 sound/usb/6fire/firmware.c val |= hval; val 72 sound/usb/6fire/firmware.c *crc += val; val 73 sound/usb/6fire/firmware.c return val; val 310 sound/usb/caiaq/device.c char val[4]; val 317 sound/usb/caiaq/device.c val[0] = 0x00; val 318 sound/usb/caiaq/device.c val[1] = 0x00; val 319 sound/usb/caiaq/device.c val[2] = 0x01; val 320 sound/usb/caiaq/device.c snd_usb_caiaq_send_command(cdev, EP1_CMD_WRITE_IO, val, 3); val 324 sound/usb/caiaq/device.c val[0] = 0x00; val 325 sound/usb/caiaq/device.c val[1] = 0x40; val 326 sound/usb/caiaq/device.c val[2] = 0x40; val 327 sound/usb/caiaq/device.c val[3] = 0x00; val 328 sound/usb/caiaq/device.c snd_usb_caiaq_send_command(cdev, EP1_CMD_WRITE_IO, val, 4); val 332 sound/usb/caiaq/device.c val[0] = 0x00; val 333 sound/usb/caiaq/device.c snd_usb_caiaq_send_command(cdev, EP1_CMD_WRITE_IO, val, 1); val 37 sound/usb/line6/playback.c int val = (pv * volume[chn & 1]) >> 8; val 38 sound/usb/line6/playback.c pv = clamp(val, -0x8000, 0x7fff); val 49 sound/usb/line6/playback.c int val; val 51 sound/usb/line6/playback.c val = p[0] + (p[1] << 8) + ((signed char)p[2] << 16); val 52 sound/usb/line6/playback.c val = (val * volume[chn & 1]) >> 8; val 53 sound/usb/line6/playback.c val = clamp(val, -0x800000, 0x7fffff); val 54 sound/usb/line6/playback.c p[0] = val; val 55 sound/usb/line6/playback.c p[1] = val >> 8; val 56 sound/usb/line6/playback.c p[2] = val >> 16; val 124 sound/usb/line6/playback.c int val = pov + ((piv * volume) >> 8); val 125 sound/usb/line6/playback.c pov = clamp(val, -0x8000, 0x7fff); val 203 sound/usb/mixer.c static int convert_signed_value(struct usb_mixer_elem_info *cval, int val) val 207 sound/usb/mixer.c return !!val; val 209 sound/usb/mixer.c return !val; val 211 sound/usb/mixer.c val &= 0xff; val 214 sound/usb/mixer.c val &= 0xff; val 215 sound/usb/mixer.c if (val >= 0x80) val 216 sound/usb/mixer.c val -= 0x100; val 219 sound/usb/mixer.c val &= 0xffff; val 222 sound/usb/mixer.c val &= 0xffff; val 223 sound/usb/mixer.c if (val >= 0x8000) val 224 sound/usb/mixer.c val -= 0x10000; val 227 sound/usb/mixer.c return val; val 233 sound/usb/mixer.c static int convert_bytes_value(struct usb_mixer_elem_info *cval, int val) val 237 sound/usb/mixer.c return !!val; val 239 sound/usb/mixer.c return !val; val 242 sound/usb/mixer.c return val & 0xff; val 245 sound/usb/mixer.c return val & 0xffff; val 250 sound/usb/mixer.c static int get_relative_value(struct usb_mixer_elem_info *cval, int val) val 254 sound/usb/mixer.c if (val < cval->min) val 256 sound/usb/mixer.c else if (val >= cval->max) val 259 sound/usb/mixer.c return (val - cval->min) / cval->res; val 262 sound/usb/mixer.c static int get_abs_value(struct usb_mixer_elem_info *cval, int val) val 264 sound/usb/mixer.c if (val < 0) val 268 sound/usb/mixer.c val *= cval->res; val 269 sound/usb/mixer.c val += cval->min; val 270 sound/usb/mixer.c if (val > cval->max) val 272 sound/usb/mixer.c return val; val 337 sound/usb/mixer.c unsigned char *val; val 375 sound/usb/mixer.c val = buf; val 378 sound/usb/mixer.c val = buf + sizeof(__u16); val 381 sound/usb/mixer.c val = buf + sizeof(__u16) + val_size; val 384 sound/usb/mixer.c val = buf + sizeof(__u16) + val_size * 2; val 391 sound/usb/mixer.c snd_usb_combine_bytes(val, val_size)); val 1338 sound/usb/mixer.c int c, cnt, val, err; val 1346 sound/usb/mixer.c err = snd_usb_get_cur_mix_value(cval, c + 1, cnt, &val); val 1349 sound/usb/mixer.c val = get_relative_value(cval, val); val 1350 sound/usb/mixer.c ucontrol->value.integer.value[cnt] = val; val 1356 sound/usb/mixer.c err = snd_usb_get_cur_mix_value(cval, 0, 0, &val); val 1359 sound/usb/mixer.c val = get_relative_value(cval, val); val 1360 sound/usb/mixer.c ucontrol->value.integer.value[0] = val; val 1370 sound/usb/mixer.c int c, cnt, val, oval, err; val 1381 sound/usb/mixer.c val = ucontrol->value.integer.value[cnt]; val 1382 sound/usb/mixer.c val = get_abs_value(cval, val); val 1383 sound/usb/mixer.c if (oval != val) { val 1384 sound/usb/mixer.c snd_usb_set_cur_mix_value(cval, c + 1, cnt, val); val 1394 sound/usb/mixer.c val = ucontrol->value.integer.value[0]; val 1395 sound/usb/mixer.c val = get_abs_value(cval, val); val 1396 sound/usb/mixer.c if (val != oval) { val 1397 sound/usb/mixer.c snd_usb_set_cur_mix_value(cval, 0, 0, val); val 1409 sound/usb/mixer.c int val, err; val 1411 sound/usb/mixer.c err = snd_usb_get_cur_mix_value(cval, 0, 0, &val); val 1414 sound/usb/mixer.c val = (val != 0); val 1415 sound/usb/mixer.c ucontrol->value.integer.value[0] = val; val 1425 sound/usb/mixer.c int idx = 0, validx, ret, val; val 1440 sound/usb/mixer.c val = !!uac2_conn.bNrChannels; val 1447 sound/usb/mixer.c val = !!uac3_conn.bmConInserted; val 1460 sound/usb/mixer.c ucontrol->value.integer.value[0] = val; val 2183 sound/usb/mixer.c int err, val; val 2185 sound/usb/mixer.c err = get_cur_ctl_value(cval, cval->control << 8, &val); val 2190 sound/usb/mixer.c val = get_relative_value(cval, val); val 2191 sound/usb/mixer.c ucontrol->value.integer.value[0] = val; val 2200 sound/usb/mixer.c int val, oval, err; val 2205 sound/usb/mixer.c val = ucontrol->value.integer.value[0]; val 2206 sound/usb/mixer.c val = get_abs_value(cval, val); val 2207 sound/usb/mixer.c if (val != oval) { val 2208 sound/usb/mixer.c set_cur_ctl_value(cval, cval->control << 8, val); val 2539 sound/usb/mixer.c int val, err; val 2541 sound/usb/mixer.c err = get_cur_ctl_value(cval, cval->control << 8, &val); val 2546 sound/usb/mixer.c val = get_relative_value(cval, val); val 2547 sound/usb/mixer.c ucontrol->value.enumerated.item[0] = val; val 2556 sound/usb/mixer.c int val, oval, err; val 2561 sound/usb/mixer.c val = ucontrol->value.enumerated.item[0]; val 2562 sound/usb/mixer.c val = get_abs_value(cval, val); val 2563 sound/usb/mixer.c if (val != oval) { val 2564 sound/usb/mixer.c set_cur_ctl_value(cval, cval->control << 8, val); val 603 sound/usb/mixer_quirks.c static int snd_mbox1_switch_update(struct usb_mixer_interface *mixer, int val) val 636 sound/usb/mixer_quirks.c if (val == 0) { val 238 sound/usb/mixer_scarlett.c int i, err, val; val 241 sound/usb/mixer_scarlett.c err = snd_usb_get_cur_mix_value(elem, i, i, &val); val 245 sound/usb/mixer_scarlett.c val = !val; /* invert mute logic for mixer */ val 246 sound/usb/mixer_scarlett.c ucontrol->value.integer.value[i] = val; val 257 sound/usb/mixer_scarlett.c int err, oval, val; val 264 sound/usb/mixer_scarlett.c val = ucontrol->value.integer.value[i]; val 265 sound/usb/mixer_scarlett.c val = !val; val 266 sound/usb/mixer_scarlett.c if (oval != val) { val 267 sound/usb/mixer_scarlett.c err = snd_usb_set_cur_mix_value(elem, i, i, val); val 308 sound/usb/mixer_scarlett.c int i, err, val; val 311 sound/usb/mixer_scarlett.c err = snd_usb_get_cur_mix_value(elem, i, i, &val); val 315 sound/usb/mixer_scarlett.c val = clamp(val / 256, -128, (int)kctl->private_value) + val 317 sound/usb/mixer_scarlett.c ucontrol->value.integer.value[i] = val; val 328 sound/usb/mixer_scarlett.c int err, oval, val; val 335 sound/usb/mixer_scarlett.c val = ucontrol->value.integer.value[i] - val 337 sound/usb/mixer_scarlett.c val = val * 256; val 338 sound/usb/mixer_scarlett.c if (oval != val) { val 339 sound/usb/mixer_scarlett.c err = snd_usb_set_cur_mix_value(elem, i, i, val); val 404 sound/usb/mixer_scarlett.c int err, val; val 406 sound/usb/mixer_scarlett.c err = snd_usb_get_cur_mix_value(elem, 0, 0, &val); val 410 sound/usb/mixer_scarlett.c val = clamp(val - opt->start, 0, opt->len-1); val 412 sound/usb/mixer_scarlett.c ucontrol->value.enumerated.item[0] = val; val 422 sound/usb/mixer_scarlett.c int err, oval, val; val 428 sound/usb/mixer_scarlett.c val = ucontrol->value.integer.value[0]; val 429 sound/usb/mixer_scarlett.c val = val + opt->start; val 430 sound/usb/mixer_scarlett.c if (val != oval) { val 431 sound/usb/mixer_scarlett.c snd_usb_set_cur_mix_value(elem, 0, 0, val); val 1066 sound/usb/mixer_scarlett_gen2.c int oval, val, err = 0; val 1071 sound/usb/mixer_scarlett_gen2.c val = ucontrol->value.integer.value[0]; val 1073 sound/usb/mixer_scarlett_gen2.c if (oval == val) val 1076 sound/usb/mixer_scarlett_gen2.c private->vol[index] = val; val 1078 sound/usb/mixer_scarlett_gen2.c index, val - SCARLETT2_VOLUME_BIAS); val 1145 sound/usb/mixer_scarlett_gen2.c int oval, val, err = 0; val 1150 sound/usb/mixer_scarlett_gen2.c val = !!ucontrol->value.integer.value[0]; val 1152 sound/usb/mixer_scarlett_gen2.c if (oval == val) val 1155 sound/usb/mixer_scarlett_gen2.c private->vol_sw_hw_switch[index] = val; val 1160 sound/usb/mixer_scarlett_gen2.c if (val) val 1183 sound/usb/mixer_scarlett_gen2.c index, val); val 1229 sound/usb/mixer_scarlett_gen2.c int oval, val, err = 0; val 1234 sound/usb/mixer_scarlett_gen2.c val = !!ucontrol->value.integer.value[0]; val 1236 sound/usb/mixer_scarlett_gen2.c if (oval == val) val 1239 sound/usb/mixer_scarlett_gen2.c private->level_switch[index] = val; val 1243 sound/usb/mixer_scarlett_gen2.c index, val); val 1279 sound/usb/mixer_scarlett_gen2.c int oval, val, err = 0; val 1284 sound/usb/mixer_scarlett_gen2.c val = !!ucontrol->value.integer.value[0]; val 1286 sound/usb/mixer_scarlett_gen2.c if (oval == val) val 1289 sound/usb/mixer_scarlett_gen2.c private->pad_switch[index] = val; val 1293 sound/usb/mixer_scarlett_gen2.c index, val); val 1335 sound/usb/mixer_scarlett_gen2.c int oval, val, err = 0; val 1340 sound/usb/mixer_scarlett_gen2.c val = !!ucontrol->value.integer.value[0]; val 1342 sound/usb/mixer_scarlett_gen2.c if (oval == val) val 1345 sound/usb/mixer_scarlett_gen2.c private->buttons[index] = val; val 1349 sound/usb/mixer_scarlett_gen2.c index, val); val 1497 sound/usb/mixer_scarlett_gen2.c int oval, val, num_mixer_in, mix_num, err = 0; val 1502 sound/usb/mixer_scarlett_gen2.c val = ucontrol->value.integer.value[0]; val 1506 sound/usb/mixer_scarlett_gen2.c if (oval == val) val 1509 sound/usb/mixer_scarlett_gen2.c private->mix[elem->control] = val; val 1614 sound/usb/mixer_scarlett_gen2.c int oval, val, err = 0; val 1619 sound/usb/mixer_scarlett_gen2.c val = clamp(ucontrol->value.integer.value[0], val 1622 sound/usb/mixer_scarlett_gen2.c if (oval == val) val 1625 sound/usb/mixer_scarlett_gen2.c private->mux[index] = val; val 199 sound/usb/mixer_us16x08.c int val, val_org, err; val 202 sound/usb/mixer_us16x08.c val = ucontrol->value.enumerated.item[0]; val 205 sound/usb/mixer_us16x08.c if (val < 0 || val > 9) val 211 sound/usb/mixer_us16x08.c if (val < 2) { val 213 sound/usb/mixer_us16x08.c val_org = val; val 218 sound/usb/mixer_us16x08.c val_org = val - 2; val 230 sound/usb/mixer_us16x08.c elem->cache_val[index] = val; val 266 sound/usb/mixer_us16x08.c int val, err; val 270 sound/usb/mixer_us16x08.c val = ucontrol->value.integer.value[0]; val 273 sound/usb/mixer_us16x08.c if (val < SND_US16X08_KCMIN(kcontrol) val 274 sound/usb/mixer_us16x08.c || val > SND_US16X08_KCMAX(kcontrol)) val 280 sound/usb/mixer_us16x08.c buf[8] = val - SND_US16X08_KCBIAS(kcontrol); val 289 sound/usb/mixer_us16x08.c elem->cache_val[index] = val; val 303 sound/usb/mixer_us16x08.c int val, err = 0; val 305 sound/usb/mixer_us16x08.c val = ucontrol->value.integer.value[0]; val 311 sound/usb/mixer_us16x08.c buf[2] = val; val 316 sound/usb/mixer_us16x08.c buf[2] = val; val 321 sound/usb/mixer_us16x08.c buf[8] = val; val 330 sound/usb/mixer_us16x08.c elem->cache_val[0] = val; val 376 sound/usb/mixer_us16x08.c int val, err; val 379 sound/usb/mixer_us16x08.c val = ucontrol->value.integer.value[0]; val 382 sound/usb/mixer_us16x08.c if (val < SND_US16X08_KCMIN(kcontrol) val 383 sound/usb/mixer_us16x08.c || val > SND_US16X08_KCMAX(kcontrol)) val 390 sound/usb/mixer_us16x08.c buf[8] = val - SND_US16X08_KCBIAS(kcontrol); val 398 sound/usb/mixer_us16x08.c elem->cache_val[index] = val; val 425 sound/usb/mixer_us16x08.c ucontrol->value.integer.value[0] = store->val[val_idx][index]; val 438 sound/usb/mixer_us16x08.c int val_idx, val; val 441 sound/usb/mixer_us16x08.c val = ucontrol->value.integer.value[0]; val 444 sound/usb/mixer_us16x08.c if (val < SND_US16X08_KCMIN(kcontrol) val 445 sound/usb/mixer_us16x08.c || val > SND_US16X08_KCMAX(kcontrol)) val 451 sound/usb/mixer_us16x08.c store->val[val_idx][index] = ucontrol->value.integer.value[0]; val 457 sound/usb/mixer_us16x08.c buf[8] = store->val[ val 460 sound/usb/mixer_us16x08.c buf[11] = ratio_map[store->val[ val 462 sound/usb/mixer_us16x08.c buf[14] = store->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_ATTACK)][index] val 464 sound/usb/mixer_us16x08.c buf[17] = store->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_RELEASE)][index] val 466 sound/usb/mixer_us16x08.c buf[20] = store->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_GAIN)][index]; val 467 sound/usb/mixer_us16x08.c buf[26] = store->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_SWITCH)][index]; val 476 sound/usb/mixer_us16x08.c elem->cache_val[index] = val; val 487 sound/usb/mixer_us16x08.c int val; val 493 sound/usb/mixer_us16x08.c val = store->val[EQ_STORE_BAND_IDX(elem->head.id)] val 495 sound/usb/mixer_us16x08.c ucontrol->value.integer.value[0] = val; val 508 sound/usb/mixer_us16x08.c int val, err = 0; val 512 sound/usb/mixer_us16x08.c val = ucontrol->value.integer.value[0] + SND_US16X08_KCBIAS(kcontrol); val 521 sound/usb/mixer_us16x08.c buf[20] = val; val 522 sound/usb/mixer_us16x08.c buf[17] = store->val[b_idx][2][index]; val 523 sound/usb/mixer_us16x08.c buf[14] = store->val[b_idx][1][index]; val 524 sound/usb/mixer_us16x08.c buf[11] = store->val[b_idx][0][index]; val 529 sound/usb/mixer_us16x08.c store->val[b_idx][3][index] = val; val 535 sound/usb/mixer_us16x08.c elem->cache_val[index] = val; val 546 sound/usb/mixer_us16x08.c int val; val 553 sound/usb/mixer_us16x08.c val = store->val[b_idx][p_idx][index]; val 555 sound/usb/mixer_us16x08.c ucontrol->value.integer.value[0] = val; val 568 sound/usb/mixer_us16x08.c int val, err; val 572 sound/usb/mixer_us16x08.c val = ucontrol->value.integer.value[0]; val 575 sound/usb/mixer_us16x08.c if (val < SND_US16X08_KCMIN(kcontrol) val 576 sound/usb/mixer_us16x08.c || val > SND_US16X08_KCMAX(kcontrol)) val 582 sound/usb/mixer_us16x08.c store->val[b_idx][p_idx][index] = val; val 583 sound/usb/mixer_us16x08.c buf[20] = store->val[b_idx][3][index]; val 584 sound/usb/mixer_us16x08.c buf[17] = store->val[b_idx][2][index]; val 585 sound/usb/mixer_us16x08.c buf[14] = store->val[b_idx][1][index]; val 586 sound/usb/mixer_us16x08.c buf[11] = store->val[b_idx][0][index]; val 599 sound/usb/mixer_us16x08.c elem->cache_val[index] = val; val 640 sound/usb/mixer_us16x08.c while (!store->comp_store->val[ val 658 sound/usb/mixer_us16x08.c int val = MUC2(meter_urb, s) + (MUC3(meter_urb, s) << 8); val 663 sound/usb/mixer_us16x08.c store->meter_level[MUB2(meter_urb, s) - 1] = val; val 665 sound/usb/mixer_us16x08.c store->comp_level[MUB2(meter_urb, s) - 1] = val; val 669 sound/usb/mixer_us16x08.c store->master_level[MUB2(meter_urb, s) - 1] = val; val 749 sound/usb/mixer_us16x08.c int val; val 751 sound/usb/mixer_us16x08.c val = ucontrol->value.integer.value[0]; val 754 sound/usb/mixer_us16x08.c if (val < 0 || val >= SND_US16X08_MAX_CHANNELS) val 757 sound/usb/mixer_us16x08.c store->comp_active_index = val; val 758 sound/usb/mixer_us16x08.c store->comp_index = val; val 970 sound/usb/mixer_us16x08.c tmp->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_THRESHOLD)][i] val 972 sound/usb/mixer_us16x08.c tmp->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_RATIO)][i] = 0x00; val 973 sound/usb/mixer_us16x08.c tmp->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_GAIN)][i] = 0x00; val 974 sound/usb/mixer_us16x08.c tmp->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_SWITCH)][i] = 0x00; val 975 sound/usb/mixer_us16x08.c tmp->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_ATTACK)][i] = 0x00; val 976 sound/usb/mixer_us16x08.c tmp->val[COMP_STORE_IDX(SND_US16X08_ID_COMP_RELEASE)][i] = 0x00; val 993 sound/usb/mixer_us16x08.c tmp->val[b_idx][0][i] = 0x0c; val 994 sound/usb/mixer_us16x08.c tmp->val[b_idx][3][i] = 0x00; val 997 sound/usb/mixer_us16x08.c tmp->val[b_idx][1][i] = 0x05; val 998 sound/usb/mixer_us16x08.c tmp->val[b_idx][2][i] = 0xff; val 1001 sound/usb/mixer_us16x08.c tmp->val[b_idx][1][i] = 0x0e; val 1002 sound/usb/mixer_us16x08.c tmp->val[b_idx][2][i] = 0x02; val 1005 sound/usb/mixer_us16x08.c tmp->val[b_idx][1][i] = 0x1b; val 1006 sound/usb/mixer_us16x08.c tmp->val[b_idx][2][i] = 0x02; val 1009 sound/usb/mixer_us16x08.c tmp->val[b_idx][1][i] = 0x2f val 1011 sound/usb/mixer_us16x08.c tmp->val[b_idx][2][i] = 0xff; val 93 sound/usb/mixer_us16x08.h u8 val[SND_US16X08_ID_EQ_BAND_COUNT][SND_US16X08_ID_EQ_PARAM_COUNT] val 98 sound/usb/mixer_us16x08.h u8 val[SND_US16X08_ID_COMP_COUNT][SND_US16X08_MAX_CHANNELS]; val 760 sound/usb/quirks.c int val[] = { val 802 sound/usb/quirks.c for (reg = 0; reg < ARRAY_SIZE(val); reg++) { val 803 sound/usb/quirks.c err = snd_usb_cm106_write_int_reg(dev, reg, val[reg]); val 80 sound/usb/usx2y/usbus428ctldefs.h } val; val 231 sound/usb/usx2y/usbusx2y.c usb_sndbulkpipe(usX2Y->dev, 0x04), &p4out->val.vol, val 213 sound/x86/intel_hdmi_audio.c int pipe, u32 reg, u32 val) val 215 sound/x86/intel_hdmi_audio.c iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); val 218 sound/x86/intel_hdmi_audio.c static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) val 221 sound/x86/intel_hdmi_audio.c *val = 0; val 223 sound/x86/intel_hdmi_audio.c *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); val 226 sound/x86/intel_hdmi_audio.c static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) val 229 sound/x86/intel_hdmi_audio.c had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); val 1013 sound/x86/intel_hdmi_audio.c u32 val; val 1017 sound/x86/intel_hdmi_audio.c had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); val 1018 sound/x86/intel_hdmi_audio.c if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) val 1022 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_HDMI_STATUS, val); val 1449 sound/x86/intel_hdmi_audio.c unsigned int val; val 1453 sound/x86/intel_hdmi_audio.c val = (ucontrol->value.iec958.status[0] << 0) | val 1458 sound/x86/intel_hdmi_audio.c if (intelhaddata->aes_bits != val) { val 1459 sound/x86/intel_hdmi_audio.c intelhaddata->aes_bits = val; val 244 sound/xen/xen_snd_front_cfg.c int val; val 254 sound/xen/xen_snd_front_cfg.c val = xenbus_read_unsigned(path, XENSND_FIELD_CHANNELS_MIN, 0); val 255 sound/xen/xen_snd_front_cfg.c if (val) val 256 sound/xen/xen_snd_front_cfg.c pcm_hw->channels_min = val; val 258 sound/xen/xen_snd_front_cfg.c val = xenbus_read_unsigned(path, XENSND_FIELD_CHANNELS_MAX, 0); val 259 sound/xen/xen_snd_front_cfg.c if (val) val 260 sound/xen/xen_snd_front_cfg.c pcm_hw->channels_max = val; val 20 tools/arch/x86/include/asm/rmwcc.h #define GEN_BINARY_RMWcc(op, var, vcon, val, arg0, cc) \ val 21 tools/arch/x86/include/asm/rmwcc.h __GEN_RMWcc(op " %1, " arg0, var, cc, vcon (val)) val 37 tools/arch/x86/include/asm/rmwcc.h #define GEN_BINARY_RMWcc(op, var, vcon, val, arg0, cc) \ val 38 tools/arch/x86/include/asm/rmwcc.h __GEN_RMWcc(op " %2, " arg0, var, cc, vcon (val)) val 219 tools/bpf/bpf_dbg.c int val = f.k; val 302 tools/bpf/bpf_dbg.c val = i + 1 + f.k; val 423 tools/bpf/bpf_dbg.c val = f.code; val 428 tools/bpf/bpf_dbg.c snprintf(buf, sizeof(buf), fmt, val); val 211 tools/bpf/bpftool/btf.c jsonw_uint_field(w, "val", v->val); val 214 tools/bpf/bpftool/btf.c printf("\n\t'%s' val=%u", name, v->val); val 580 tools/bpf/bpftool/common.c int parse_u32_arg(int *argc, char ***argv, __u32 *val, const char *what) val 586 tools/bpf/bpftool/common.c if (*val) { val 591 tools/bpf/bpftool/common.c *val = strtoul(**argv, &endptr, 0); val 201 tools/bpf/bpftool/json_writer.c void jsonw_bool(json_writer_t *self, bool val) val 203 tools/bpf/bpftool/json_writer.c jsonw_printf(self, "%s", val ? "true" : "false"); val 244 tools/bpf/bpftool/json_writer.c void jsonw_string_field(json_writer_t *self, const char *prop, const char *val) val 247 tools/bpf/bpftool/json_writer.c jsonw_string(self, val); val 250 tools/bpf/bpftool/json_writer.c void jsonw_bool_field(json_writer_t *self, const char *prop, bool val) val 253 tools/bpf/bpftool/json_writer.c jsonw_bool(self, val); val 257 tools/bpf/bpftool/json_writer.c void jsonw_float_field(json_writer_t *self, const char *prop, double val) val 260 tools/bpf/bpftool/json_writer.c jsonw_float(self, val); val 267 tools/bpf/bpftool/json_writer.c double val) val 270 tools/bpf/bpftool/json_writer.c jsonw_float_fmt(self, fmt, val); val 48 tools/bpf/bpftool/json_writer.h void jsonw_string_field(json_writer_t *self, const char *prop, const char *val); val 58 tools/bpf/bpftool/json_writer.h const char *fmt, double val); val 159 tools/bpf/bpftool/main.h int parse_u32_arg(int *argc, char ***argv, __u32 *val, const char *what); val 330 tools/bpf/bpftool/map.c static char **parse_bytes(char **argv, const char *name, unsigned char *val, val 342 tools/bpf/bpftool/map.c val[i] = strtoul(argv[i], &endptr, base); val 71 tools/bpf/bpftool/netlink_dumper.h #define NET_DUMP_UINT(name, fmt_str, val) \ val 74 tools/bpf/bpftool/netlink_dumper.h jsonw_uint_field(json_wtr, name, val); \ val 76 tools/bpf/bpftool/netlink_dumper.h fprintf(stdout, fmt_str, val); \ val 7 tools/build/feature/test-libcap.c cap_flag_value_t val; val 13 tools/build/feature/test-libcap.c if (cap_get_flag(caps, CAP_SYS_ADMIN, CAP_EFFECTIVE, &val) != 0) val 48 tools/firmware/ihex2fw.c uint8_t val = (nybble(data[0]) << 4) | nybble(data[1]); val 49 tools/firmware/ihex2fw.c *crc += val; val 50 tools/firmware/ihex2fw.c return val; val 80 tools/iio/iio_generic_buffer.c int8_t val = (int8_t)(input << (8 - info->bits_used)) >> val 82 tools/iio/iio_generic_buffer.c printf("%05f ", ((float)val + info->offset) * info->scale); val 103 tools/iio/iio_generic_buffer.c int16_t val = (int16_t)(input << (16 - info->bits_used)) >> val 105 tools/iio/iio_generic_buffer.c printf("%05f ", ((float)val + info->offset) * info->scale); val 126 tools/iio/iio_generic_buffer.c int32_t val = (int32_t)(input << (32 - info->bits_used)) >> val 128 tools/iio/iio_generic_buffer.c printf("%05f ", ((float)val + info->offset) * info->scale); val 149 tools/iio/iio_generic_buffer.c int64_t val = (int64_t)(input << (64 - info->bits_used)) >> val 153 tools/iio/iio_generic_buffer.c printf("%" PRId64 " ", val); val 156 tools/iio/iio_generic_buffer.c ((float)val + info->offset) * info->scale); val 655 tools/iio/iio_utils.c static int _write_sysfs_int(const char *filename, const char *basedir, int val, val 677 tools/iio/iio_utils.c ret = fprintf(sysfsfp, "%d", val); val 711 tools/iio/iio_utils.c if (test != val) { val 714 tools/iio/iio_utils.c val, basedir, filename); val 732 tools/iio/iio_utils.c int write_sysfs_int(const char *filename, const char *basedir, int val) val 734 tools/iio/iio_utils.c return _write_sysfs_int(filename, basedir, val, 0); val 747 tools/iio/iio_utils.c int val) val 749 tools/iio/iio_utils.c return _write_sysfs_int(filename, basedir, val, 1); val 753 tools/iio/iio_utils.c const char *val, int verify) val 775 tools/iio/iio_utils.c ret = fprintf(sysfsfp, "%s", val); val 809 tools/iio/iio_utils.c if (strcmp(temp, val) != 0) { val 812 tools/iio/iio_utils.c "Should be %s written to %s/%s\n", temp, val, val 833 tools/iio/iio_utils.c const char *val) val 835 tools/iio/iio_utils.c return _write_sysfs_string(filename, basedir, val, 1); val 847 tools/iio/iio_utils.c const char *val) val 849 tools/iio/iio_utils.c return _write_sysfs_string(filename, basedir, val, 0); val 907 tools/iio/iio_utils.c int read_sysfs_float(const char *filename, const char *basedir, float *val) val 929 tools/iio/iio_utils.c if (fscanf(sysfsfp, "%f\n", val) != 1) { val 71 tools/iio/iio_utils.h int write_sysfs_int(const char *filename, const char *basedir, int val); val 73 tools/iio/iio_utils.h int val); val 75 tools/iio/iio_utils.h const char *val); val 77 tools/iio/iio_utils.h const char *val); val 79 tools/iio/iio_utils.h int read_sysfs_float(const char *filename, const char *basedir, float *val); val 162 tools/include/linux/compiler.h #define WRITE_ONCE(x, val) \ val 165 tools/include/linux/compiler.h { .__val = (val) }; \ val 16 tools/include/linux/hash.h #define hash_long(val, bits) hash_32(val, bits) val 18 tools/include/linux/hash.h #define hash_long(val, bits) hash_64(val, bits) val 60 tools/include/linux/hash.h static inline u32 __hash_32_generic(u32 val) val 62 tools/include/linux/hash.h return val * GOLDEN_RATIO_32; val 68 tools/include/linux/hash.h static inline u32 hash_32_generic(u32 val, unsigned int bits) val 71 tools/include/linux/hash.h return __hash_32(val) >> (32 - bits); val 77 tools/include/linux/hash.h static __always_inline u32 hash_64_generic(u64 val, unsigned int bits) val 81 tools/include/linux/hash.h return val * GOLDEN_RATIO_64 >> (64 - bits); val 84 tools/include/linux/hash.h return hash_32((u32)val ^ __hash_32(val >> 32), bits); val 96 tools/include/linux/hash.h unsigned long val = (unsigned long)ptr; val 99 tools/include/linux/hash.h val ^= (val >> 32); val 101 tools/include/linux/hash.h return (u32)val; val 28 tools/include/linux/hashtable.h #define hash_min(val, bits) \ val 29 tools/include/linux/hashtable.h (sizeof(val) <= 4 ? hash_32(val, bits) : hash_long(val, bits)) val 78 tools/include/linux/refcount.h unsigned int old, new, val = atomic_read(&r->refs); val 81 tools/include/linux/refcount.h new = val + 1; val 83 tools/include/linux/refcount.h if (!val) val 89 tools/include/linux/refcount.h old = atomic_cmpxchg_relaxed(&r->refs, val, new); val 90 tools/include/linux/refcount.h if (old == val) val 93 tools/include/linux/refcount.h val = old; val 123 tools/include/linux/refcount.h unsigned int old, new, val = atomic_read(&r->refs); val 126 tools/include/linux/refcount.h if (unlikely(val == UINT_MAX)) val 129 tools/include/linux/refcount.h new = val - i; val 130 tools/include/linux/refcount.h if (new > val) { val 131 tools/include/linux/refcount.h REFCOUNT_WARN(new > val, "refcount_t: underflow; use-after-free.\n"); val 135 tools/include/linux/refcount.h old = atomic_cmpxchg_release(&r->refs, val, new); val 136 tools/include/linux/refcount.h if (old == val) val 139 tools/include/linux/refcount.h val = old; val 29 tools/include/linux/unaligned/packed_struct.h static inline void __put_unaligned_cpu16(u16 val, void *p) val 32 tools/include/linux/unaligned/packed_struct.h ptr->x = val; val 35 tools/include/linux/unaligned/packed_struct.h static inline void __put_unaligned_cpu32(u32 val, void *p) val 38 tools/include/linux/unaligned/packed_struct.h ptr->x = val; val 41 tools/include/linux/unaligned/packed_struct.h static inline void __put_unaligned_cpu64(u64 val, void *p) val 44 tools/include/linux/unaligned/packed_struct.h ptr->x = val; val 23 tools/include/tools/be_byteshift.h static inline void __put_unaligned_be16(uint16_t val, uint8_t *p) val 25 tools/include/tools/be_byteshift.h *p++ = val >> 8; val 26 tools/include/tools/be_byteshift.h *p++ = val; val 29 tools/include/tools/be_byteshift.h static inline void __put_unaligned_be32(uint32_t val, uint8_t *p) val 31 tools/include/tools/be_byteshift.h __put_unaligned_be16(val >> 16, p); val 32 tools/include/tools/be_byteshift.h __put_unaligned_be16(val, p + 2); val 35 tools/include/tools/be_byteshift.h static inline void __put_unaligned_be64(uint64_t val, uint8_t *p) val 37 tools/include/tools/be_byteshift.h __put_unaligned_be32(val >> 32, p); val 38 tools/include/tools/be_byteshift.h __put_unaligned_be32(val, p + 4); val 56 tools/include/tools/be_byteshift.h static inline void put_unaligned_be16(uint16_t val, void *p) val 58 tools/include/tools/be_byteshift.h __put_unaligned_be16(val, p); val 61 tools/include/tools/be_byteshift.h static inline void put_unaligned_be32(uint32_t val, void *p) val 63 tools/include/tools/be_byteshift.h __put_unaligned_be32(val, p); val 66 tools/include/tools/be_byteshift.h static inline void put_unaligned_be64(uint64_t val, void *p) val 68 tools/include/tools/be_byteshift.h __put_unaligned_be64(val, p); val 8 tools/include/tools/config.h #define __take_second_arg(__ignored, val, ...) val val 24 tools/include/tools/config.h #define ___is_defined(val) ____is_defined(__ARG_PLACEHOLDER_##val) val 23 tools/include/tools/le_byteshift.h static inline void __put_unaligned_le16(uint16_t val, uint8_t *p) val 25 tools/include/tools/le_byteshift.h *p++ = val; val 26 tools/include/tools/le_byteshift.h *p++ = val >> 8; val 29 tools/include/tools/le_byteshift.h static inline void __put_unaligned_le32(uint32_t val, uint8_t *p) val 31 tools/include/tools/le_byteshift.h __put_unaligned_le16(val >> 16, p + 2); val 32 tools/include/tools/le_byteshift.h __put_unaligned_le16(val, p); val 35 tools/include/tools/le_byteshift.h static inline void __put_unaligned_le64(uint64_t val, uint8_t *p) val 37 tools/include/tools/le_byteshift.h __put_unaligned_le32(val >> 32, p + 4); val 38 tools/include/tools/le_byteshift.h __put_unaligned_le32(val, p); val 56 tools/include/tools/le_byteshift.h static inline void put_unaligned_le16(uint16_t val, void *p) val 58 tools/include/tools/le_byteshift.h __put_unaligned_le16(val, p); val 61 tools/include/tools/le_byteshift.h static inline void put_unaligned_le32(uint32_t val, void *p) val 63 tools/include/tools/le_byteshift.h __put_unaligned_le32(val, p); val 66 tools/include/tools/le_byteshift.h static inline void put_unaligned_le64(uint64_t val, void *p) val 68 tools/include/tools/le_byteshift.h __put_unaligned_le64(val, p); val 1783 tools/include/uapi/drm/i915_drm.h __u64 val; /* Return value */ val 3593 tools/include/uapi/linux/bpf.h __u32 val; val 100 tools/include/uapi/linux/btf.h __s32 val; val 131 tools/include/uapi/linux/btf.h #define BTF_MEMBER_BITFIELD_SIZE(val) ((val) >> 24) val 132 tools/include/uapi/linux/btf.h #define BTF_MEMBER_BIT_OFFSET(val) ((val) & 0xffffff) val 24 tools/include/uapi/linux/lirc.h #define LIRC_SPACE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_SPACE) val 25 tools/include/uapi/linux/lirc.h #define LIRC_PULSE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_PULSE) val 26 tools/include/uapi/linux/lirc.h #define LIRC_FREQUENCY(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_FREQUENCY) val 27 tools/include/uapi/linux/lirc.h #define LIRC_TIMEOUT(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_TIMEOUT) val 29 tools/include/uapi/linux/lirc.h #define LIRC_VALUE(val) ((val)&LIRC_VALUE_MASK) val 30 tools/include/uapi/linux/lirc.h #define LIRC_MODE2(val) ((val)&LIRC_MODE2_MASK) val 32 tools/include/uapi/linux/lirc.h #define LIRC_IS_SPACE(val) (LIRC_MODE2(val) == LIRC_MODE2_SPACE) val 33 tools/include/uapi/linux/lirc.h #define LIRC_IS_PULSE(val) (LIRC_MODE2(val) == LIRC_MODE2_PULSE) val 34 tools/include/uapi/linux/lirc.h #define LIRC_IS_FREQUENCY(val) (LIRC_MODE2(val) == LIRC_MODE2_FREQUENCY) val 35 tools/include/uapi/linux/lirc.h #define LIRC_IS_TIMEOUT(val) (LIRC_MODE2(val) == LIRC_MODE2_TIMEOUT) val 1051 tools/include/uapi/linux/perf_event.h __u64 val; val 1066 tools/include/uapi/linux/perf_event.h __u64 val; val 167 tools/include/uapi/linux/pkt_cls.h __be32 val; val 187 tools/include/uapi/linux/pkt_cls.h __u32 val; val 816 tools/include/uapi/sound/asound.h unsigned int val; val 1790 tools/lib/bpf/btf.c if (m1->name_off != m2->name_off || m1->val != m2->val) val 951 tools/lib/bpf/btf_dump.c (__s32)v->val); val 955 tools/lib/bpf/btf_dump.c (__s32)v->val); val 5738 tools/lib/bpf/libbpf.c __u32 val) val 5743 tools/lib/bpf/libbpf.c array[offset / sizeof(__u32)] = val; val 5747 tools/lib/bpf/libbpf.c __u64 val) val 5752 tools/lib/bpf/libbpf.c array[offset / sizeof(__u64)] = val; val 225 tools/lib/subcmd/parse-options.c const char *val = *(const char **)opt->value; val 227 tools/lib/subcmd/parse-options.c if (!val) val 231 tools/lib/subcmd/parse-options.c if (val[0] == '\0') { val 2218 tools/lib/traceevent/event-parse.c eval_type_str(unsigned long long val, const char *type, int pointer) val 2230 tools/lib/traceevent/event-parse.c return val; val 2236 tools/lib/traceevent/event-parse.c return val; val 2243 tools/lib/traceevent/event-parse.c val = eval_type_str(val, ref, 0); val 2245 tools/lib/traceevent/event-parse.c return val; val 2250 tools/lib/traceevent/event-parse.c return val; val 2255 tools/lib/traceevent/event-parse.c return val; val 2258 tools/lib/traceevent/event-parse.c return val & 0xff; val 2261 tools/lib/traceevent/event-parse.c return val & 0xffff; val 2264 tools/lib/traceevent/event-parse.c return val & 0xffffffff; val 2268 tools/lib/traceevent/event-parse.c return val; val 2271 tools/lib/traceevent/event-parse.c return (unsigned long long)(char)val & 0xff; val 2274 tools/lib/traceevent/event-parse.c return (unsigned long long)(short)val & 0xffff; val 2277 tools/lib/traceevent/event-parse.c return (unsigned long long)(int)val & 0xffffffff; val 2286 tools/lib/traceevent/event-parse.c return (unsigned long long)(char)val & 0xff; val 2288 tools/lib/traceevent/event-parse.c return val & 0xff; val 2293 tools/lib/traceevent/event-parse.c return (unsigned long long)(short)val & 0xffff; val 2295 tools/lib/traceevent/event-parse.c return val & 0xffff; val 2300 tools/lib/traceevent/event-parse.c return (unsigned long long)(int)val & 0xffffffff; val 2302 tools/lib/traceevent/event-parse.c return val & 0xffffffff; val 2305 tools/lib/traceevent/event-parse.c return val; val 2312 tools/lib/traceevent/event-parse.c eval_type(unsigned long long val, struct tep_print_arg *arg, int pointer) val 2319 tools/lib/traceevent/event-parse.c return eval_type_str(val, arg->typecast.type, pointer); val 2322 tools/lib/traceevent/event-parse.c static int arg_num_eval(struct tep_print_arg *arg, long long *val) val 2329 tools/lib/traceevent/event-parse.c *val = strtoll(arg->atom.atom, NULL, 0); val 2332 tools/lib/traceevent/event-parse.c ret = arg_num_eval(arg->typecast.item, val); val 2335 tools/lib/traceevent/event-parse.c *val = eval_type(*val, arg, 0); val 2347 tools/lib/traceevent/event-parse.c *val = left || right; val 2349 tools/lib/traceevent/event-parse.c *val = left | right; val 2359 tools/lib/traceevent/event-parse.c *val = left && right; val 2361 tools/lib/traceevent/event-parse.c *val = left & right; val 2372 tools/lib/traceevent/event-parse.c *val = left < right; val 2375 tools/lib/traceevent/event-parse.c *val = left << right; val 2378 tools/lib/traceevent/event-parse.c *val = left <= right; val 2394 tools/lib/traceevent/event-parse.c *val = left > right; val 2397 tools/lib/traceevent/event-parse.c *val = left >> right; val 2400 tools/lib/traceevent/event-parse.c *val = left >= right; val 2419 tools/lib/traceevent/event-parse.c *val = left == right; val 2431 tools/lib/traceevent/event-parse.c *val = left != right; val 2449 tools/lib/traceevent/event-parse.c *val = left - right; val 2461 tools/lib/traceevent/event-parse.c *val = left + right; val 2467 tools/lib/traceevent/event-parse.c *val = ~right; val 2490 tools/lib/traceevent/event-parse.c long long val; val 2499 tools/lib/traceevent/event-parse.c if (!arg_num_eval(arg, &val)) val 2501 tools/lib/traceevent/event-parse.c sprintf(buf, "%lld", val); val 3401 tools/lib/traceevent/event-parse.c unsigned long long val; val 3411 tools/lib/traceevent/event-parse.c memcpy(&val, (ptr), sizeof(unsigned long long)); val 3412 tools/lib/traceevent/event-parse.c return tep_data2host8(tep, val); val 3602 tools/lib/traceevent/event-parse.c unsigned long long val = 0; val 3623 tools/lib/traceevent/event-parse.c val = tep_read_number(tep, data + arg->field.field->offset, val 3633 tools/lib/traceevent/event-parse.c val = eval_num_arg(data, size, event, arg->typecast.item); val 3634 tools/lib/traceevent/event-parse.c return eval_type(val, arg, 0); val 3642 tools/lib/traceevent/event-parse.c val = process_defined_func(&s, data, size, event, arg); val 3644 tools/lib/traceevent/event-parse.c return val; val 3696 tools/lib/traceevent/event-parse.c val = tep_read_number(tep, val 3699 tools/lib/traceevent/event-parse.c val = eval_type(val, typearg, 1); val 3705 tools/lib/traceevent/event-parse.c val = eval_num_arg(data, size, event, arg->op.left); val 3707 tools/lib/traceevent/event-parse.c val = eval_num_arg(data, size, event, arg->op.right); val 3717 tools/lib/traceevent/event-parse.c val = !right; val 3720 tools/lib/traceevent/event-parse.c val = left != right; val 3727 tools/lib/traceevent/event-parse.c val = ~right; val 3731 tools/lib/traceevent/event-parse.c val = left || right; val 3733 tools/lib/traceevent/event-parse.c val = left | right; val 3737 tools/lib/traceevent/event-parse.c val = left && right; val 3739 tools/lib/traceevent/event-parse.c val = left & right; val 3744 tools/lib/traceevent/event-parse.c val = left < right; val 3747 tools/lib/traceevent/event-parse.c val = left << right; val 3750 tools/lib/traceevent/event-parse.c val = left <= right; val 3759 tools/lib/traceevent/event-parse.c val = left > right; val 3762 tools/lib/traceevent/event-parse.c val = left >> right; val 3765 tools/lib/traceevent/event-parse.c val = left >= right; val 3775 tools/lib/traceevent/event-parse.c val = left == right; val 3778 tools/lib/traceevent/event-parse.c val = left - right; val 3781 tools/lib/traceevent/event-parse.c val = left + right; val 3784 tools/lib/traceevent/event-parse.c val = left / right; val 3787 tools/lib/traceevent/event-parse.c val = left % right; val 3790 tools/lib/traceevent/event-parse.c val = left * right; val 3805 tools/lib/traceevent/event-parse.c val = (unsigned long long)(offset >> 16); val 3818 tools/lib/traceevent/event-parse.c val = (unsigned long long)((unsigned long)data + offset); val 3823 tools/lib/traceevent/event-parse.c return val; val 3946 tools/lib/traceevent/event-parse.c long long val, fval; val 4018 tools/lib/traceevent/event-parse.c val = eval_num_arg(data, size, event, arg->flags.field); val 4022 tools/lib/traceevent/event-parse.c if (!val && fval < 0) { val 4026 tools/lib/traceevent/event-parse.c if (fval > 0 && (val & fval) == fval) { val 4031 tools/lib/traceevent/event-parse.c val &= ~fval; val 4034 tools/lib/traceevent/event-parse.c if (val) { val 4037 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "0x%llx", val); val 4041 tools/lib/traceevent/event-parse.c val = eval_num_arg(data, size, event, arg->symbol.field); val 4044 tools/lib/traceevent/event-parse.c if (val == fval) { val 4050 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "0x%llx", val); val 4169 tools/lib/traceevent/event-parse.c val = eval_num_arg(data, size, event, arg->op.left); val 4170 tools/lib/traceevent/event-parse.c if (val) val 4294 tools/lib/traceevent/event-parse.c unsigned long long ip, val; val 4422 tools/lib/traceevent/event-parse.c val = tep_read_number(tep, bptr, vsize); val 4432 tools/lib/traceevent/event-parse.c if (asprintf(&arg->atom.atom, "%lld", val) < 0) { val 4878 tools/lib/traceevent/event-parse.c unsigned long long val; val 4886 tools/lib/traceevent/event-parse.c val = tep_read_number(tep, data + offset, len); val 4887 tools/lib/traceevent/event-parse.c offset = val; val 4906 tools/lib/traceevent/event-parse.c val = tep_read_number(tep, data + field->offset, val 4909 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "0x%llx", val); val 4918 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "0x%x", (int)val); val 4920 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "%d", (int)val); val 4923 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "%2d", (short)val); val 4926 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "%1d", (char)val); val 4929 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "%lld", val); val 4933 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "0x%llx", val); val 4935 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "%llu", val); val 4960 tools/lib/traceevent/event-parse.c unsigned long long val; val 5104 tools/lib/traceevent/event-parse.c val = eval_num_arg(data, size, event, arg); val 5108 tools/lib/traceevent/event-parse.c func = find_func(tep, val); val 5114 tools/lib/traceevent/event-parse.c val - func->addr); val 5132 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, len_arg, (char)val); val 5134 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, (char)val); val 5138 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, len_arg, (short)val); val 5140 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, (short)val); val 5144 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, len_arg, (int)val); val 5146 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, (int)val); val 5150 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, len_arg, (long)val); val 5152 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, (long)val); val 5157 tools/lib/traceevent/event-parse.c (long long)val); val 5159 tools/lib/traceevent/event-parse.c trace_seq_printf(s, format, (long long)val); val 6399 tools/lib/traceevent/event-parse.c unsigned long long *val, int err) val 6407 tools/lib/traceevent/event-parse.c if (tep_read_number_field(field, record->data, val)) { val 6479 tools/lib/traceevent/event-parse.c unsigned long long *val, int err) val 6488 tools/lib/traceevent/event-parse.c return get_field_val(s, field, name, record, val, err); val 6504 tools/lib/traceevent/event-parse.c unsigned long long *val, int err) val 6513 tools/lib/traceevent/event-parse.c return get_field_val(s, field, name, record, val, err); val 6529 tools/lib/traceevent/event-parse.c unsigned long long *val, int err) val 6538 tools/lib/traceevent/event-parse.c return get_field_val(s, field, name, record, val, err); val 6558 tools/lib/traceevent/event-parse.c unsigned long long val; val 6563 tools/lib/traceevent/event-parse.c if (tep_read_number_field(field, record->data, &val)) val 6566 tools/lib/traceevent/event-parse.c return trace_seq_printf(s, fmt, val); val 6592 tools/lib/traceevent/event-parse.c unsigned long long val; val 6599 tools/lib/traceevent/event-parse.c if (tep_read_number_field(field, record->data, &val)) val 6602 tools/lib/traceevent/event-parse.c func = find_func(tep, val); val 6605 tools/lib/traceevent/event-parse.c snprintf(tmp, 128, "%s/0x%llx", func->func, func->addr - val); val 6607 tools/lib/traceevent/event-parse.c sprintf(tmp, "0x%08llx", val); val 418 tools/lib/traceevent/event-parse.h unsigned int val; val 420 tools/lib/traceevent/event-parse.h memcpy(&val, str, 4); val 421 tools/lib/traceevent/event-parse.h return val == 0x01020304; val 475 tools/lib/traceevent/event-parse.h unsigned long long *val, int err); val 478 tools/lib/traceevent/event-parse.h unsigned long long *val, int err); val 481 tools/lib/traceevent/event-parse.h unsigned long long *val, int err); val 662 tools/lib/traceevent/event-parse.h unsigned long long val; val 687 tools/lib/traceevent/event-parse.h char *val; val 49 tools/lib/traceevent/event-plugin.c static int update_option_value(struct tep_plugin_option *op, const char *val) val 53 tools/lib/traceevent/event-plugin.c if (!val) { val 67 tools/lib/traceevent/event-plugin.c op->value = val; val 73 tools/lib/traceevent/event-plugin.c op_val = strdup(val); val 78 tools/lib/traceevent/event-plugin.c if (strcmp(val, "1") == 0 || strcmp(val, "true") == 0) val 80 tools/lib/traceevent/event-plugin.c else if (strcmp(val, "0") == 0 || strcmp(val, "false") == 0) val 210 tools/lib/traceevent/parse-filter.c free(arg->str.val); val 368 tools/lib/traceevent/parse-filter.c arg->value.val = strtoull(token, NULL, 0); val 555 tools/lib/traceevent/parse-filter.c op->str.val = strdup(str); val 556 tools/lib/traceevent/parse-filter.c if (!op->str.val) { val 1547 tools/lib/traceevent/parse-filter.c unsigned long long val; val 1561 tools/lib/traceevent/parse-filter.c tep_read_number_field(field, record->data, &val); val 1564 tools/lib/traceevent/parse-filter.c return val; val 1568 tools/lib/traceevent/parse-filter.c return (char)val; val 1570 tools/lib/traceevent/parse-filter.c return (short)val; val 1572 tools/lib/traceevent/parse-filter.c return (int)val; val 1574 tools/lib/traceevent/parse-filter.c return (long long)val; val 1576 tools/lib/traceevent/parse-filter.c return val; val 1651 tools/lib/traceevent/parse-filter.c return arg->value.val; val 1709 tools/lib/traceevent/parse-filter.c const char *val = NULL; val 1715 tools/lib/traceevent/parse-filter.c val = record->data + arg->str.field->offset; val 1719 tools/lib/traceevent/parse-filter.c addr = *(unsigned int *)val; val 1720 tools/lib/traceevent/parse-filter.c val = record->data + (addr & 0xffff); val 1728 tools/lib/traceevent/parse-filter.c if (*(val + size - 1)) { val 1730 tools/lib/traceevent/parse-filter.c memcpy(arg->str.buffer, val, arg->str.field->size); val 1732 tools/lib/traceevent/parse-filter.c val = arg->str.buffer; val 1742 tools/lib/traceevent/parse-filter.c val = tep_find_function(tep, addr); val 1744 tools/lib/traceevent/parse-filter.c if (val == NULL) { val 1747 tools/lib/traceevent/parse-filter.c val = hex; val 1751 tools/lib/traceevent/parse-filter.c return val; val 1757 tools/lib/traceevent/parse-filter.c const char *val; val 1760 tools/lib/traceevent/parse-filter.c val = get_comm(event, record); val 1762 tools/lib/traceevent/parse-filter.c val = get_field_str(arg, record); val 1766 tools/lib/traceevent/parse-filter.c return strcmp(val, arg->str.val) == 0; val 1769 tools/lib/traceevent/parse-filter.c return strcmp(val, arg->str.val) != 0; val 1773 tools/lib/traceevent/parse-filter.c return !regexec(&arg->str.reg, val, 0, NULL, 0); val 1776 tools/lib/traceevent/parse-filter.c return regexec(&arg->str.reg, val, 0, NULL, 0); val 1914 tools/lib/traceevent/parse-filter.c int val; val 1950 tools/lib/traceevent/parse-filter.c val = 0; val 1953 tools/lib/traceevent/parse-filter.c val = left_val && right_val; val 1956 tools/lib/traceevent/parse-filter.c val = left_val || right_val; val 1961 tools/lib/traceevent/parse-filter.c asprintf(&str, val ? "TRUE" : "FALSE"); val 2014 tools/lib/traceevent/parse-filter.c asprintf(&str, "%lld", arg->value.val); val 2152 tools/lib/traceevent/parse-filter.c arg->str.field->name, op, arg->str.val); val 24 tools/lib/traceevent/plugins/plugin_cfg80211.c uint16_t *val = (uint16_t *) (unsigned long) args[0]; val 25 tools/lib/traceevent/plugins/plugin_cfg80211.c return val ? (long long) le16toh(*val) : 0; val 31 tools/lib/traceevent/plugins/plugin_kmem.c unsigned long long val, addr; val 39 tools/lib/traceevent/plugins/plugin_kmem.c if (tep_read_number_field(field, data, &val)) val 42 tools/lib/traceevent/plugins/plugin_kmem.c func = tep_find_function(event->tep, val); val 46 tools/lib/traceevent/plugins/plugin_kmem.c addr = tep_find_function_address(event->tep, val); val 48 tools/lib/traceevent/plugins/plugin_kmem.c trace_seq_printf(s, "(%s+0x%x) ", func, (int)(val - addr)); val 207 tools/lib/traceevent/plugins/plugin_kvm.c #define _ER(reason, val) { #reason, val }, val 210 tools/lib/traceevent/plugins/plugin_kvm.c int val; val 232 tools/lib/traceevent/plugins/plugin_kvm.c static const char *find_exit_reason(unsigned isa, int val) val 244 tools/lib/traceevent/plugins/plugin_kvm.c for (i = 0; strings[i].val >= 0; i++) val 245 tools/lib/traceevent/plugins/plugin_kvm.c if (strings[i].val == val) val 255 tools/lib/traceevent/plugins/plugin_kvm.c unsigned long long val; val 258 tools/lib/traceevent/plugins/plugin_kvm.c if (tep_get_field_val(s, event, field, record, &val, 1) < 0) val 264 tools/lib/traceevent/plugins/plugin_kvm.c reason = find_exit_reason(isa, val); val 268 tools/lib/traceevent/plugins/plugin_kvm.c trace_seq_printf(s, "reason UNKNOWN (%llu)", val); val 377 tools/lib/traceevent/plugins/plugin_kvm.c unsigned long long val; val 383 tools/lib/traceevent/plugins/plugin_kvm.c if (tep_get_field_val(s, event, "role", record, &val, 1) < 0) val 386 tools/lib/traceevent/plugins/plugin_kvm.c role.word = (int)val; val 413 tools/lib/traceevent/plugins/plugin_kvm.c if (tep_get_field_val(s, event, "unsync", record, &val, 1) < 0) val 416 tools/lib/traceevent/plugins/plugin_kvm.c trace_seq_printf(s, "%s%c", val ? "unsync" : "sync", 0); val 424 tools/lib/traceevent/plugins/plugin_kvm.c unsigned long long val; val 426 tools/lib/traceevent/plugins/plugin_kvm.c if (tep_get_field_val(s, event, "created", record, &val, 1) < 0) val 429 tools/lib/traceevent/plugins/plugin_kvm.c trace_seq_printf(s, "%s ", val ? "new" : "existing"); val 431 tools/lib/traceevent/plugins/plugin_kvm.c if (tep_get_field_val(s, event, "gfn", record, &val, 1) < 0) val 434 tools/lib/traceevent/plugins/plugin_kvm.c trace_seq_printf(s, "sp gfn %llx ", val); val 27 tools/lib/traceevent/plugins/plugin_sched_switch.c static void write_state(struct trace_seq *s, int val) val 34 tools/lib/traceevent/plugins/plugin_sched_switch.c if (!(val & (1 << i))) val 73 tools/lib/traceevent/plugins/plugin_sched_switch.c unsigned long long val; val 75 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "pid", record, &val, 1)) val 80 tools/lib/traceevent/plugins/plugin_sched_switch.c write_and_save_comm(field, record, s, val); val 83 tools/lib/traceevent/plugins/plugin_sched_switch.c trace_seq_printf(s, "%lld", val); val 85 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "prio", record, &val, 0) == 0) val 86 tools/lib/traceevent/plugins/plugin_sched_switch.c trace_seq_printf(s, " [%lld]", val); val 88 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "success", record, &val, 1) == 0) val 89 tools/lib/traceevent/plugins/plugin_sched_switch.c trace_seq_printf(s, " success=%lld", val); val 91 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "target_cpu", record, &val, 0) == 0) val 92 tools/lib/traceevent/plugins/plugin_sched_switch.c trace_seq_printf(s, " CPU:%03llu", val); val 102 tools/lib/traceevent/plugins/plugin_sched_switch.c unsigned long long val; val 104 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "prev_pid", record, &val, 1)) val 109 tools/lib/traceevent/plugins/plugin_sched_switch.c write_and_save_comm(field, record, s, val); val 112 tools/lib/traceevent/plugins/plugin_sched_switch.c trace_seq_printf(s, "%lld ", val); val 114 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "prev_prio", record, &val, 0) == 0) val 115 tools/lib/traceevent/plugins/plugin_sched_switch.c trace_seq_printf(s, "[%d] ", (int) val); val 117 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "prev_state", record, &val, 0) == 0) val 118 tools/lib/traceevent/plugins/plugin_sched_switch.c write_state(s, val); val 122 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "next_pid", record, &val, 1)) val 127 tools/lib/traceevent/plugins/plugin_sched_switch.c write_and_save_comm(field, record, s, val); val 130 tools/lib/traceevent/plugins/plugin_sched_switch.c trace_seq_printf(s, "%lld", val); val 132 tools/lib/traceevent/plugins/plugin_sched_switch.c if (tep_get_field_val(s, event, "next_prio", record, &val, 0) == 0) val 133 tools/lib/traceevent/plugins/plugin_sched_switch.c trace_seq_printf(s, " [%d]", (int) val); val 68 tools/perf/arch/arm/util/cs-etm.c u32 val; val 79 tools/perf/arch/arm/util/cs-etm.c err = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val); val 95 tools/perf/arch/arm/util/cs-etm.c val = BMVAL(val, 5, 9); val 96 tools/perf/arch/arm/util/cs-etm.c if (!val || val != 0x4) { val 117 tools/perf/arch/arm/util/cs-etm.c u32 val; val 128 tools/perf/arch/arm/util/cs-etm.c err = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val); val 144 tools/perf/arch/arm/util/cs-etm.c val &= GENMASK(28, 24); val 145 tools/perf/arch/arm/util/cs-etm.c if (!val) { val 229 tools/perf/arch/arm/util/cs-etm.c sink = term->val.drv_cfg; val 536 tools/perf/arch/arm/util/cs-etm.c unsigned int val; val 544 tools/perf/arch/arm/util/cs-etm.c scan = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val); val 557 tools/perf/arch/arm/util/cs-etm.c unsigned int val = 0; val 562 tools/perf/arch/arm/util/cs-etm.c scan = perf_pmu__scan_file(pmu, pmu_path, "%x", &val); val 566 tools/perf/arch/arm/util/cs-etm.c return val; val 14 tools/perf/arch/arm/util/unwind-libdw.c Dwarf_Word val = 0; \ val 15 tools/perf/arch/arm/util/unwind-libdw.c perf_reg_value(&val, user_regs, PERF_REG_ARM_##r); \ val 16 tools/perf/arch/arm/util/unwind-libdw.c val; \ val 14 tools/perf/arch/arm64/util/unwind-libdw.c Dwarf_Word val = 0; \ val 15 tools/perf/arch/arm64/util/unwind-libdw.c perf_reg_value(&val, user_regs, PERF_REG_ARM64_##r); \ val 16 tools/perf/arch/arm64/util/unwind-libdw.c val; \ val 16 tools/perf/arch/csky/util/unwind-libdw.c Dwarf_Word val = 0; \ val 17 tools/perf/arch/csky/util/unwind-libdw.c perf_reg_value(&val, user_regs, PERF_REG_CSKY_##r); \ val 18 tools/perf/arch/csky/util/unwind-libdw.c val; \ val 23 tools/perf/arch/powerpc/util/unwind-libdw.c Dwarf_Word val = 0; \ val 24 tools/perf/arch/powerpc/util/unwind-libdw.c perf_reg_value(&val, user_regs, PERF_REG_POWERPC_##r); \ val 25 tools/perf/arch/powerpc/util/unwind-libdw.c val; \ val 66 tools/perf/arch/powerpc/util/unwind-libdw.c Dwarf_Word val = 0; val 67 tools/perf/arch/powerpc/util/unwind-libdw.c perf_reg_value(&val, user_regs, special_regs[i][1]); val 70 tools/perf/arch/powerpc/util/unwind-libdw.c &val)) val 16 tools/perf/arch/riscv/util/unwind-libdw.c Dwarf_Word val = 0; \ val 17 tools/perf/arch/riscv/util/unwind-libdw.c perf_reg_value(&val, user_regs, PERF_REG_RISCV_##r); \ val 18 tools/perf/arch/riscv/util/unwind-libdw.c val; \ val 16 tools/perf/arch/s390/util/unwind-libdw.c Dwarf_Word val = 0; \ val 17 tools/perf/arch/s390/util/unwind-libdw.c perf_reg_value(&val, user_regs, PERF_REG_S390_##r); \ val 18 tools/perf/arch/s390/util/unwind-libdw.c val; \ val 39 tools/perf/arch/x86/tests/insn-x86.c int val; val 53 tools/perf/arch/x86/tests/insn-x86.c struct val_data *val; val 58 tools/perf/arch/x86/tests/insn-x86.c for (val = vals; val->name; val++) { val 59 tools/perf/arch/x86/tests/insn-x86.c if (!strcmp(val->name, op_str)) val 60 tools/perf/arch/x86/tests/insn-x86.c return val->val; val 72 tools/perf/arch/x86/tests/insn-x86.c int val; val 80 tools/perf/arch/x86/tests/insn-x86.c struct val_data *val; val 85 tools/perf/arch/x86/tests/insn-x86.c for (val = vals; val->name; val++) { val 86 tools/perf/arch/x86/tests/insn-x86.c if (!strcmp(val->name, branch_str)) val 87 tools/perf/arch/x86/tests/insn-x86.c return val->val; val 140 tools/perf/arch/x86/util/intel-pt.c u64 val; val 157 tools/perf/arch/x86/util/intel-pt.c err = intel_pt_read_config(intel_pt_pmu, "psb_period", evlist, &val); val 159 tools/perf/arch/x86/util/intel-pt.c val = 0; val 161 tools/perf/arch/x86/util/intel-pt.c psb_period = 1 << (val + 11); val 434 tools/perf/arch/x86/util/intel-pt.c unsigned int val, last = 0, state = 1; val 439 tools/perf/arch/x86/util/intel-pt.c for (val = 0; val <= 64; val++, valid >>= 1) { val 441 tools/perf/arch/x86/util/intel-pt.c last = val; val 447 tools/perf/arch/x86/util/intel-pt.c p += scnprintf(str + p, len - p, "%u", val); val 15 tools/perf/arch/x86/util/unwind-libdw.c Dwarf_Word val = 0; \ val 16 tools/perf/arch/x86/util/unwind-libdw.c perf_reg_value(&val, user_regs, PERF_REG_X86_##r); \ val 17 tools/perf/arch/x86/util/unwind-libdw.c val; \ val 190 tools/perf/bench/epoll-wait.c uint64_t val; val 217 tools/perf/bench/epoll-wait.c r = read(fd, &val, sizeof(val)); val 372 tools/perf/bench/epoll-wait.c const uint64_t val = 1; val 394 tools/perf/bench/epoll-wait.c sz = write(w->fdmap[j], &val, sizeof(val)); val 36 tools/perf/bench/futex.h #define futex(uaddr, op, val, timeout, uaddr2, val3, opflags) \ val 37 tools/perf/bench/futex.h syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3) val 44 tools/perf/bench/futex.h futex_wait(u_int32_t *uaddr, u_int32_t val, struct timespec *timeout, int opflags) val 46 tools/perf/bench/futex.h return futex(uaddr, FUTEX_WAIT, val, timeout, NULL, 0, opflags); val 83 tools/perf/bench/futex.h futex_cmp_requeue(u_int32_t *uaddr, u_int32_t val, u_int32_t *uaddr2, int nr_wake, val 87 tools/perf/bench/futex.h val, opflags); val 64 tools/perf/bench/numa.c u64 val; val 750 tools/perf/bench/numa.c static inline u64 access_data(u64 *data, u64 val) val 753 tools/perf/bench/numa.c val += *data; val 755 tools/perf/bench/numa.c *data = val + 1; val 756 tools/perf/bench/numa.c return val; val 767 tools/perf/bench/numa.c static u64 do_work(u8 *__data, long bytes, int nr, int nr_max, int loop, u64 val) val 780 tools/perf/bench/numa.c return val; val 785 tools/perf/bench/numa.c return val; val 797 tools/perf/bench/numa.c u32 lfsr = nr + loop + val; val 812 tools/perf/bench/numa.c val = access_data(data + j, val); val 828 tools/perf/bench/numa.c val = access_data(d, val); val 846 tools/perf/bench/numa.c val = access_data(d, val); val 852 tools/perf/bench/numa.c return val; val 1101 tools/perf/bench/numa.c u64 val = td->val; val 1162 tools/perf/bench/numa.c val += do_work(global_data, g->p.bytes_global, process_nr, g->p.nr_proc, l, val); val 1163 tools/perf/bench/numa.c val += do_work(process_data, g->p.bytes_process, thread_nr, g->p.nr_threads, l, val); val 1164 tools/perf/bench/numa.c val += do_work(thread_data, g->p.bytes_thread, 0, 1, l, val); val 1176 tools/perf/bench/numa.c val += do_work(process_data, g->p.bytes_process_locked, thread_nr, g->p.nr_threads, l, val); val 1244 tools/perf/bench/numa.c process_nr, thread_nr, runtime_ns_max / bytes_done, val); val 1322 tools/perf/bench/numa.c td->val = rand(); val 1473 tools/perf/bench/numa.c static void print_res(const char *name, double val, val 1480 tools/perf/bench/numa.c printf(" %-30s %15.3f, %-15s %s\n", name, val, txt_unit, txt_short); val 1482 tools/perf/bench/numa.c printf(" %14.3f %s\n", val, txt_long); val 70 tools/perf/builtin-ftrace.c static int __write_tracing_file(const char *name, const char *val, bool append) val 74 tools/perf/builtin-ftrace.c ssize_t size = strlen(val); val 101 tools/perf/builtin-ftrace.c val_copy = strdup(val); val 110 tools/perf/builtin-ftrace.c val, name, str_error_r(errno, errbuf, sizeof(errbuf))); val 120 tools/perf/builtin-ftrace.c static int write_tracing_file(const char *name, const char *val) val 122 tools/perf/builtin-ftrace.c return __write_tracing_file(name, val, false); val 125 tools/perf/builtin-ftrace.c static int append_tracing_file(const char *name, const char *val) val 127 tools/perf/builtin-ftrace.c return __write_tracing_file(name, val, true); val 2016 tools/perf/builtin-record.c unsigned long val; val 2027 tools/perf/builtin-record.c val = parse_tag_value(s->str, tags_size); val 2028 tools/perf/builtin-record.c if (val != (unsigned long) -1) { val 2029 tools/perf/builtin-record.c s->size = val; val 2034 tools/perf/builtin-record.c val = parse_tag_value(s->str, tags_time); val 2035 tools/perf/builtin-record.c if (val != (unsigned long) -1) { val 2036 tools/perf/builtin-record.c s->time = val; val 2759 tools/perf/builtin-sched.c list_for_each_entry(chain, &node->val, list) { val 259 tools/perf/builtin-script.c u64 val; val 601 tools/perf/builtin-script.c u64 val = regs->regs[i++]; val 602 tools/perf/builtin-script.c printed += fprintf(fp, "%5s:0x%"PRIx64" ", perf_reg_name(r), val); val 1440 tools/perf/builtin-script.c unsigned int val, val 1443 tools/perf/builtin-script.c unsigned char ch = (unsigned char)val; val 1456 tools/perf/builtin-script.c printed += fprintf(fp, " %04x:", val); val 1459 tools/perf/builtin-script.c printed += fprintf(fp, " %02x", val); val 1670 tools/perf/builtin-script.c struct mem_info mi = { .data_src.val = data_src }; val 1695 tools/perf/builtin-script.c const char *unit, double val) val 1705 tools/perf/builtin-script.c color_fprintf(mctx->fp, color, fmt, val); val 1707 tools/perf/builtin-script.c printf(fmt, val); val 1739 tools/perf/builtin-script.c u64 val; val 1745 tools/perf/builtin-script.c val = sample->period * evsel->scale; val 1747 tools/perf/builtin-script.c val, val 1750 tools/perf/builtin-script.c evsel_script(evsel)->val = val; val 1754 tools/perf/builtin-script.c evsel_script(ev2)->val, val 1944 tools/perf/builtin-script.c counts->val, val 254 tools/perf/builtin-stat.c u64 val = rs->tv_nsec + rs->tv_sec*1000000000ULL; val 257 tools/perf/builtin-stat.c count->ena = count->run = val; val 258 tools/perf/builtin-stat.c count->val = val; val 316 tools/perf/builtin-stat.c count->val, count->ena, count->run); val 948 tools/perf/builtin-top.c set = term->val.overwrite ? 1 : 0; val 395 tools/perf/builtin-trace.c size_t strarray__scnprintf(struct strarray *sa, char *bf, size_t size, const char *intfmt, bool show_prefix, int val) val 397 tools/perf/builtin-trace.c int idx = val - sa->offset; val 400 tools/perf/builtin-trace.c size_t printed = scnprintf(bf, size, intfmt, val); val 413 tools/perf/builtin-trace.c return strarray__scnprintf(arg->parm, bf, size, intfmt, arg->show_string_prefix, arg->val); val 426 tools/perf/builtin-trace.c return strarray__scnprintf_flags(arg->parm, bf, size, arg->show_string_prefix, arg->val); val 429 tools/perf/builtin-trace.c size_t strarrays__scnprintf(struct strarrays *sas, char *bf, size_t size, const char *intfmt, bool show_prefix, int val) val 436 tools/perf/builtin-trace.c int idx = val - sa->offset; val 445 tools/perf/builtin-trace.c printed = scnprintf(bf, size, intfmt, val); val 454 tools/perf/builtin-trace.c return strarrays__scnprintf(arg->parm, bf, size, "%d", arg->show_string_prefix, arg->val); val 464 tools/perf/builtin-trace.c int fd = arg->val; val 482 tools/perf/builtin-trace.c return scnprintf(bf, size, "%#lx", arg->val); val 487 tools/perf/builtin-trace.c if (arg->val == 0) val 494 tools/perf/builtin-trace.c return scnprintf(bf, size, "%d", arg->val); val 499 tools/perf/builtin-trace.c return scnprintf(bf, size, "%ld", arg->val); val 588 tools/perf/builtin-trace.c int mode = arg->val; val 621 tools/perf/builtin-trace.c int printed = 0, flags = arg->val; val 653 tools/perf/builtin-trace.c int printed = 0, flags = arg->val; val 699 tools/perf/builtin-trace.c unsigned long (*mask_val)(struct syscall_arg *arg, unsigned long val); val 1217 tools/perf/builtin-trace.c int fd = arg->val; val 1247 tools/perf/builtin-trace.c int fd = arg->val; val 1285 tools/perf/builtin-trace.c unsigned long ptr = arg->val; val 1662 tools/perf/builtin-trace.c unsigned long val; val 1665 tools/perf/builtin-trace.c memcpy(&val, p, sizeof(val)); val 1666 tools/perf/builtin-trace.c return val; val 1683 tools/perf/builtin-trace.c static unsigned long syscall__mask_val(struct syscall *sc, struct syscall_arg *arg, unsigned long val) val 1686 tools/perf/builtin-trace.c return sc->arg_fmt[arg->idx].mask_val(arg, val); val 1688 tools/perf/builtin-trace.c return val; val 1692 tools/perf/builtin-trace.c struct syscall_arg *arg, unsigned long val) val 1695 tools/perf/builtin-trace.c arg->val = val; val 1700 tools/perf/builtin-trace.c return scnprintf(bf, size, "%ld", val); val 1708 tools/perf/builtin-trace.c unsigned long val; val 1739 tools/perf/builtin-trace.c val = syscall_arg__val(&arg, arg.idx); val 1744 tools/perf/builtin-trace.c val = syscall__mask_val(sc, &arg, val); val 1751 tools/perf/builtin-trace.c if (val == 0 && val 1765 tools/perf/builtin-trace.c printed += syscall__scnprintf_val(sc, bf + printed, size - printed, &arg, val); val 1776 tools/perf/builtin-trace.c val = syscall_arg__val(&arg, arg.idx); val 1780 tools/perf/builtin-trace.c printed += syscall__scnprintf_val(sc, bf + printed, size - printed, &arg, val); val 2184 tools/perf/builtin-trace.c .val = ret, val 2318 tools/perf/builtin-trace.c unsigned int val, void *extra __maybe_unused, FILE *fp) val 2320 tools/perf/builtin-trace.c unsigned char ch = (unsigned char)val; val 276 tools/perf/lib/include/perf/event.h __u64 val; val 294 tools/perf/lib/include/perf/event.h __u64 val; val 16 tools/perf/lib/include/perf/evsel.h uint64_t val; val 57 tools/perf/lib/tests/test-evlist.c struct perf_counts_values counts = { .val = 0 }; val 60 tools/perf/lib/tests/test-evlist.c __T("failed to read value for evsel", counts.val != 0); val 73 tools/perf/lib/tests/test-evlist.c struct perf_counts_values counts = { .val = 0 }; val 112 tools/perf/lib/tests/test-evlist.c __T("failed to read value for evsel", counts.val != 0); val 124 tools/perf/lib/tests/test-evlist.c struct perf_counts_values counts = { .val = 0 }; val 165 tools/perf/lib/tests/test-evlist.c __T("failed to read value for evsel", counts.val == 0); val 172 tools/perf/lib/tests/test-evlist.c __T("failed to read value for evsel", counts.val != 0); val 36 tools/perf/lib/tests/test-evsel.c struct perf_counts_values counts = { .val = 0 }; val 39 tools/perf/lib/tests/test-evsel.c __T("failed to read value for evsel", counts.val != 0); val 51 tools/perf/lib/tests/test-evsel.c struct perf_counts_values counts = { .val = 0 }; val 72 tools/perf/lib/tests/test-evsel.c __T("failed to read value for evsel", counts.val != 0); val 83 tools/perf/lib/tests/test-evsel.c struct perf_counts_values counts = { .val = 0 }; val 105 tools/perf/lib/tests/test-evsel.c __T("failed to read value for evsel", counts.val == 0); val 111 tools/perf/lib/tests/test-evsel.c __T("failed to read value for evsel", counts.val != 0); val 95 tools/perf/perf.c int val; val 102 tools/perf/perf.c c->val = perf_config_bool(var, value); val 112 tools/perf/perf.c c.val = -1; val 114 tools/perf/perf.c return err ?: c.val; val 121 tools/perf/perf.c c->val = perf_config_bool(var, value); val 123 tools/perf/perf.c c->val = perf_config_bool(var, value) ? 2 : 0; val 136 tools/perf/perf.c c.val = -1; val 138 tools/perf/perf.c return err ?: c.val; val 196 tools/perf/pmu-events/jevents.c char **event, jsmntok_t *val) val 199 tools/perf/pmu-events/jevents.c jsmntok_t newval = *val; val 210 tools/perf/pmu-events/jevents.c static struct msrmap *lookup_msr(char *map, jsmntok_t *val) val 212 tools/perf/pmu-events/jevents.c jsmntok_t newval = *val; val 223 tools/perf/pmu-events/jevents.c json_len(val), map + val->start); val 246 tools/perf/pmu-events/jevents.c static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val) val 251 tools/perf/pmu-events/jevents.c if (json_streq(map, val, table[i].json)) val 548 tools/perf/pmu-events/jevents.c jsmntok_t *field, *val; val 555 tools/perf/pmu-events/jevents.c val = tok + j + 1; val 556 tools/perf/pmu-events/jevents.c EXPECT(val->type == JSMN_STRING, tok + j + 1, val 559 tools/perf/pmu-events/jevents.c nz = !json_streq(map, val, "0"); val 560 tools/perf/pmu-events/jevents.c if (match_field(map, field, nz, &event, val)) { val 564 tools/perf/pmu-events/jevents.c addfield(map, &code, "", "", val); val 569 tools/perf/pmu-events/jevents.c addfield(map, &code, "", "", val); val 573 tools/perf/pmu-events/jevents.c addfield(map, &name, "", "", val); val 575 tools/perf/pmu-events/jevents.c addfield(map, &desc, "", "", val); val 579 tools/perf/pmu-events/jevents.c addfield(map, &long_desc, "", "", val); val 582 tools/perf/pmu-events/jevents.c precise = val; val 584 tools/perf/pmu-events/jevents.c msr = lookup_msr(map, val); val 586 tools/perf/pmu-events/jevents.c msrval = val; val 588 tools/perf/pmu-events/jevents.c !json_streq(map, val, "null")) { val 590 tools/perf/pmu-events/jevents.c " Spec update: ", val); val 598 tools/perf/pmu-events/jevents.c ppmu = field_to_perf(unit_to_pmu, map, val); val 604 tools/perf/pmu-events/jevents.c addfield(map, &pmu, "", "", val); val 612 tools/perf/pmu-events/jevents.c addfield(map, &filter, "", "", val); val 614 tools/perf/pmu-events/jevents.c addfield(map, &unit, "", "", val); val 616 tools/perf/pmu-events/jevents.c addfield(map, &perpkg, "", "", val); val 618 tools/perf/pmu-events/jevents.c addfield(map, &metric_name, "", "", val); val 620 tools/perf/pmu-events/jevents.c addfield(map, &metric_group, "", "", val); val 622 tools/perf/pmu-events/jevents.c addfield(map, &metric_expr, "", "", val); val 626 tools/perf/pmu-events/jevents.c addfield(map, &arch_std, "", "", val); val 11 tools/perf/tests/expr.c double val; val 13 tools/perf/tests/expr.c if (expr__parse(&val, ctx, &e)) val 15 tools/perf/tests/expr.c TEST_ASSERT_VAL("unexpected value", val == val2); val 23 tools/perf/tests/expr.c double val; val 47 tools/perf/tests/expr.c ret = expr__parse(&val, &ctx, &p); val 51 tools/perf/tests/expr.c ret = expr__parse(&val, &ctx, &p); val 228 tools/perf/tests/hists_cumulate.c list_for_each_entry(clist, &cnode->val, list) { val 113 tools/perf/tests/openat-syscall-all-cpus.c if (perf_counts(evsel->counts, cpu, 0)->val != expected) { val 115 tools/perf/tests/openat-syscall-all-cpus.c expected, cpus->map[cpu], perf_counts(evsel->counts, cpu, 0)->val); val 54 tools/perf/tests/openat-syscall.c if (perf_counts(evsel->counts, 0, 0)->val != nr_openat_calls) { val 56 tools/perf/tests/openat-syscall.c nr_openat_calls, perf_counts(evsel->counts, 0, 0)->val); val 604 tools/perf/tests/parse-events.c TEST_ASSERT_VAL("wrong val", term->val.num == 10); val 613 tools/perf/tests/parse-events.c TEST_ASSERT_VAL("wrong val", term->val.num == 1); val 622 tools/perf/tests/parse-events.c TEST_ASSERT_VAL("wrong val", term->val.num == 3); val 631 tools/perf/tests/parse-events.c TEST_ASSERT_VAL("wrong val", term->val.num == 1); val 30 tools/perf/tests/pmu.c .val.num = 15, val 36 tools/perf/tests/pmu.c .val.num = 170, val 42 tools/perf/tests/pmu.c .val.num = 1, val 48 tools/perf/tests/pmu.c .val.num = 27, val 54 tools/perf/tests/pmu.c .val.num = 1, val 60 tools/perf/tests/pmu.c .val.num = 2, val 66 tools/perf/tests/pmu.c .val.num = 119, val 72 tools/perf/tests/pmu.c .val.num = 11, val 78 tools/perf/tests/pmu.c .val.num = 2, val 11 tools/perf/tests/stat.c u64 tag, u64 val) val 17 tools/perf/tests/stat.c (config->data[i].val == val)) val 32 tools/perf/tests/stat.c #define HAS(term, val) \ val 33 tools/perf/tests/stat.c has_term(config, PERF_STAT_CONFIG_TERM__##term, val) val 74 tools/perf/tests/stat.c TEST_ASSERT_VAL("wrong val", st->val == 100); val 84 tools/perf/tests/stat.c count.val = 100; val 15 tools/perf/tests/tests.h #define TEST_ASSERT_EQUAL(text, val, expected) \ val 17 tools/perf/tests/tests.h if (val != expected) { \ val 19 tools/perf/tests/tests.h __FILE__, __LINE__, text, val, expected); \ val 14 tools/perf/tests/wp.c #define WP_TEST_ASSERT_VAL(fd, text, val) \ val 18 tools/perf/tests/wp.c TEST_ASSERT_VAL(text, count == val); \ val 30 tools/perf/trace/beauty/arch_prctl.c unsigned long code = arg->val; val 29 tools/perf/trace/beauty/beauty.h size_t strarray__scnprintf(struct strarray *sa, char *bf, size_t size, const char *intfmt, bool show_prefix, int val); val 52 tools/perf/trace/beauty/beauty.h size_t strarrays__scnprintf(struct strarrays *sas, char *bf, size_t size, const char *intfmt, bool show_prefix, int val); val 95 tools/perf/trace/beauty/beauty.h unsigned long val; val 58 tools/perf/trace/beauty/clone.c unsigned long flags = arg->val; val 18 tools/perf/trace/beauty/eventfd.c int printed = 0, flags = arg->val; val 12 tools/perf/trace/beauty/fcntl.c static size_t fcntl__scnprintf_getfd(unsigned long val, char *bf, size_t size, bool show_prefix) val 14 tools/perf/trace/beauty/fcntl.c return val ? scnprintf(bf, size, "%s", "0") : val 20 tools/perf/trace/beauty/fcntl.c return fcntl__scnprintf_getfd(arg->val, bf, size, arg->show_string_prefix); val 23 tools/perf/trace/beauty/fcntl.c static size_t fcntl__scnprintf_getlease(unsigned long val, char *bf, size_t size, bool show_prefix) val 28 tools/perf/trace/beauty/fcntl.c return strarray__scnprintf(&strarray__fcntl_setlease, bf, size, "%x", show_prefix, val); val 33 tools/perf/trace/beauty/fcntl.c return fcntl__scnprintf_getlease(arg->val, bf, size, arg->show_string_prefix); val 38 tools/perf/trace/beauty/fcntl.c if (arg->val == F_GETFL) { val 42 tools/perf/trace/beauty/fcntl.c if (arg->val == F_GETFD) { val 46 tools/perf/trace/beauty/fcntl.c if (arg->val == F_DUPFD_CLOEXEC || arg->val == F_DUPFD) { val 50 tools/perf/trace/beauty/fcntl.c if (arg->val == F_GETOWN) { val 54 tools/perf/trace/beauty/fcntl.c if (arg->val == F_GETLEASE) { val 61 tools/perf/trace/beauty/fcntl.c if (arg->val == F_GET_SEALS || val 62 tools/perf/trace/beauty/fcntl.c arg->val == F_GETSIG) { val 79 tools/perf/trace/beauty/fcntl.c return fcntl__scnprintf_getfd(arg->val, bf, size, show_prefix); val 82 tools/perf/trace/beauty/fcntl.c return open__scnprintf_flags(arg->val, bf, size, show_prefix); val 88 tools/perf/trace/beauty/fcntl.c return fcntl__scnprintf_getlease(arg->val, bf, size, show_prefix); val 27 tools/perf/trace/beauty/flock.c int printed = 0, op = arg->val; val 31 tools/perf/trace/beauty/fsmount.c unsigned long flags = arg->val; val 21 tools/perf/trace/beauty/fspick.c unsigned long flags = arg->val; val 32 tools/perf/trace/beauty/futex_op.c int op = arg->val; val 11 tools/perf/trace/beauty/futex_val3.c unsigned int bitset = arg->val; val 177 tools/perf/trace/beauty/ioctl.c unsigned long cmd = arg->val; val 18 tools/perf/trace/beauty/kcmp.c unsigned long fd = arg->val; val 37 tools/perf/trace/beauty/kcmp.c unsigned long type = arg->val; val 9 tools/perf/trace/beauty/mmap.c int printed = 0, prot = arg->val; val 47 tools/perf/trace/beauty/mmap.c unsigned long flags = arg->val; val 62 tools/perf/trace/beauty/mmap.c int printed = 0, flags = arg->val; val 96 tools/perf/trace/beauty/mmap.c return madvise__scnprintf_behavior(arg->val, bf, size); val 27 tools/perf/trace/beauty/mode_t.c int printed = 0, mode = arg->val; val 40 tools/perf/trace/beauty/mount_flags.c unsigned long flags = arg->val; val 21 tools/perf/trace/beauty/move_mount.c unsigned long flags = arg->val; val 26 tools/perf/trace/beauty/msg_flags.c int printed = 0, flags = arg->val; val 82 tools/perf/trace/beauty/open_flags.c int flags = arg->val; val 23 tools/perf/trace/beauty/perf_event_open.c int printed = 0, flags = arg->val; val 5 tools/perf/trace/beauty/pid.c int pid = arg->val; val 51 tools/perf/trace/beauty/pkey_alloc.c unsigned long cmd = arg->val; val 31 tools/perf/trace/beauty/prctl.c return prctl__scnprintf_set_mm(arg->val, bf, size, arg->show_string_prefix); val 54 tools/perf/trace/beauty/prctl.c unsigned long option = arg->val; val 16 tools/perf/trace/beauty/renameat.c unsigned long flags = arg->val; val 26 tools/perf/trace/beauty/sched_policy.c int policy = arg->val, val 13 tools/perf/trace/beauty/seccomp.c int op = arg->val; val 38 tools/perf/trace/beauty/seccomp.c int printed = 0, flags = arg->val; val 8 tools/perf/trace/beauty/signum.c int sig = arg->val; val 75 tools/perf/trace/beauty/sockaddr.c return scnprintf(bf, size, "%#x", arg->val); val 25 tools/perf/trace/beauty/socket.c return socket__scnprintf_ipproto(arg->val, bf, size, arg->show_string_prefix); val 26 tools/perf/trace/beauty/socket_type.c int type = arg->val, val 18 tools/perf/trace/beauty/statx.c int printed = 0, flags = arg->val; val 48 tools/perf/trace/beauty/statx.c int printed = 0, flags = arg->val; val 28 tools/perf/trace/beauty/sync_file_range.c unsigned long flags = arg->val; val 10 tools/perf/trace/beauty/waitid_options.c int printed = 0, options = arg->val; val 183 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &child->val, list) { val 215 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &node->val, list) { val 244 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &node->val, list) { val 334 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &child->val, list) { val 337 tools/perf/ui/browsers/hists.c chain->has_children = chain->list.next != &child->val || val 340 tools/perf/ui/browsers/hists.c chain->has_children = chain->list.next == &child->val && val 353 tools/perf/ui/browsers/hists.c chain = list_entry(node->val.next, struct callchain_list, list); val 356 tools/perf/ui/browsers/hists.c if (!list_empty(&node->val)) { val 357 tools/perf/ui/browsers/hists.c chain = list_entry(node->val.prev, struct callchain_list, list); val 471 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &child->val, list) { val 490 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &node->val, list) { val 903 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &child->val, list) { val 1016 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &child->val, list) { val 1073 tools/perf/ui/browsers/hists.c list_for_each_entry(chain, &child->val, list) { val 137 tools/perf/ui/gtk/hists.c list_for_each_entry(chain, &node->val, list) { val 193 tools/perf/ui/gtk/hists.c list_for_each_entry(chain, &node->val, list) { val 238 tools/perf/ui/gtk/hists.c list_for_each_entry(chain, &node->val, list) { val 152 tools/perf/ui/stdio/hist.c list_for_each_entry(chain, &child->val, list) { val 232 tools/perf/ui/stdio/hist.c list_for_each_entry(chain, &cnode->val, list) { val 294 tools/perf/ui/stdio/hist.c list_for_each_entry(chain, &node->val, list) { val 343 tools/perf/ui/stdio/hist.c list_for_each_entry(chain, &node->val, list) { val 1102 tools/perf/util/auxtrace.c unsigned int val; val 1104 tools/perf/util/auxtrace.c val = strtoul(p, &endptr, 10); val 1106 tools/perf/util/auxtrace.c if (!val || val > PERF_ITRACE_MAX_CALLCHAIN_SZ) val 1108 tools/perf/util/auxtrace.c synth_opts->callchain_sz = val; val 1118 tools/perf/util/auxtrace.c unsigned int val; val 1120 tools/perf/util/auxtrace.c val = strtoul(p, &endptr, 10); val 1122 tools/perf/util/auxtrace.c if (!val || val 1123 tools/perf/util/auxtrace.c val > PERF_ITRACE_MAX_LAST_BRANCH_SZ) val 1125 tools/perf/util/auxtrace.c synth_opts->last_branch_sz = val; val 1042 tools/perf/util/bpf-loader.c op->v.value = term->val.num; val 1074 tools/perf/util/bpf-loader.c evsel = perf_evlist__find_evsel_by_str(evlist, term->val.str); val 1077 tools/perf/util/bpf-loader.c map_name, term->val.str); val 1372 tools/perf/util/bpf-loader.c size_t val_size, u64 val) val 1378 tools/perf/util/bpf-loader.c u8 _val = (u8)(val); val 1383 tools/perf/util/bpf-loader.c u16 _val = (u16)(val); val 1388 tools/perf/util/bpf-loader.c u32 _val = (u32)(val); val 1393 tools/perf/util/bpf-loader.c err = bpf_map_update_elem(map_fd, pkey, &val, BPF_ANY); val 1686 tools/perf/util/bpf-loader.c #define bpf__strerror_entry(val, fmt...)\ val 1687 tools/perf/util/bpf-loader.c case val: {\ val 536 tools/perf/util/callchain.c INIT_LIST_HEAD(&new->val); val 621 tools/perf/util/callchain.c list_add_tail(&call->list, &node->val); val 643 tools/perf/util/callchain.c list_for_each_entry_safe(call, tmp, &new->val, list) { val 804 tools/perf/util/callchain.c old_tail = parent->val.prev; val 806 tools/perf/util/callchain.c new->val.next = &to_split->list; val 807 tools/perf/util/callchain.c new->val.prev = old_tail; val 808 tools/perf/util/callchain.c to_split->list.prev = &new->val; val 809 tools/perf/util/callchain.c old_tail->next = &new->val; val 844 tools/perf/util/callchain.c cnode = list_first_entry(&first->val, struct callchain_list, val 930 tools/perf/util/callchain.c list_for_each_entry(cnode, &root->val, list) { val 1006 tools/perf/util/callchain.c list_for_each_entry_safe(list, next_list, &src->val, list) { val 1237 tools/perf/util/callchain.c list_for_each_entry(clist, &node->val, list) { val 1466 tools/perf/util/callchain.c list_for_each_entry_safe(list, tmp, &node->val, list) { val 1526 tools/perf/util/callchain.c list_for_each_entry_reverse(chain, &parent->val, list) { val 1545 tools/perf/util/callchain.c chain = list_first_entry(&node->val, struct callchain_list, list); val 61 tools/perf/util/callchain.h struct list_head val; val 167 tools/perf/util/callchain.h INIT_LIST_HEAD(&root->node.val); val 14 tools/perf/util/cap.c cap_flag_value_t val; val 20 tools/perf/util/cap.c if (cap_get_flag(caps, cap, CAP_EFFECTIVE, &val) != 0) val 21 tools/perf/util/cap.c val = CAP_CLEAR; val 26 tools/perf/util/cap.c return val == CAP_SET; val 297 tools/perf/util/config.c static int parse_unit_factor(const char *end, unsigned long *val) val 302 tools/perf/util/config.c *val *= 1024; val 306 tools/perf/util/config.c *val *= 1024 * 1024; val 310 tools/perf/util/config.c *val *= 1024 * 1024 * 1024; val 320 tools/perf/util/config.c long long val = strtoll(value, &end, 0); val 325 tools/perf/util/config.c *ret = val * factor; val 335 tools/perf/util/config.c long val = strtol(value, &end, 0); val 339 tools/perf/util/config.c *ret = val * factor; val 575 tools/perf/util/config.c char *val = strdup(value); val 577 tools/perf/util/config.c if (!val) val 581 tools/perf/util/config.c item->value = val; val 513 tools/perf/util/cpumap.c static char hex_char(unsigned char val) val 515 tools/perf/util/cpumap.c if (val < 10) val 516 tools/perf/util/cpumap.c return val + '0'; val 517 tools/perf/util/cpumap.c if (val < 16) val 518 tools/perf/util/cpumap.c return val - 10 + 'a'; val 2377 tools/perf/util/cs-etm.c static void cs_etm__print_auxtrace_info(__u64 *val, int num) val 2382 tools/perf/util/cs-etm.c fprintf(stdout, cs_etm_global_header_fmts[i], val[i]); val 2385 tools/perf/util/cs-etm.c if (val[i] == __perf_cs_etmv3_magic) val 2387 tools/perf/util/cs-etm.c fprintf(stdout, cs_etm_priv_fmts[j], val[i]); val 2388 tools/perf/util/cs-etm.c else if (val[i] == __perf_cs_etmv4_magic) val 2390 tools/perf/util/cs-etm.c fprintf(stdout, cs_etmv4_priv_fmts[j], val[i]); val 166 tools/perf/util/cs-etm.h #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) val 97 tools/perf/util/data-convert-bt.c const char *name, u64 val) val 110 tools/perf/util/data-convert-bt.c ret = bt_ctf_field_signed_integer_set_value(field, val); val 116 tools/perf/util/data-convert-bt.c ret = bt_ctf_field_unsigned_integer_set_value(field, val); val 129 tools/perf/util/data-convert-bt.c pr2(" SET [%s = %" PRIu64 "]\n", name, val); val 140 tools/perf/util/data-convert-bt.c _val_type val) \ val 143 tools/perf/util/data-convert-bt.c return value_set(type, event, name, (u64) val); \ val 116 tools/perf/util/debug.c unsigned int val, void *extra, FILE *fp) val 120 tools/perf/util/debug.c unsigned char ch = (unsigned char)val; val 133 tools/perf/util/debug.c printed += color_fprintf(fp, color, " %04x: ", val); val 136 tools/perf/util/debug.c printed += color_fprintf(fp, color, " %02x", val); val 100 tools/perf/util/dso.h #define DSO__SWAP(dso, type, val) \ val 102 tools/perf/util/dso.h type ____r = val; \ val 107 tools/perf/util/dso.h ____r = bswap_16(val); \ val 110 tools/perf/util/dso.h ____r = bswap_32(val); \ val 113 tools/perf/util/dso.h ____r = bswap_64(val); \ val 130 tools/perf/util/event.c config->__val = event->data[i].val; \ val 802 tools/perf/util/evlist.c unsigned long pages, val; val 814 tools/perf/util/evlist.c val = parse_tag_value(str, tags); val 815 tools/perf/util/evlist.c if (val != (unsigned long) -1) { val 817 tools/perf/util/evlist.c pages = PERF_ALIGN(val, page_size) / page_size; val 1333 tools/perf/util/evlist.c union sigval val; val 1335 tools/perf/util/evlist.c val.sival_int = errno; val 1336 tools/perf/util/evlist.c if (sigqueue(getppid(), SIGUSR1, val)) val 792 tools/perf/util/evsel.c attr->sample_period = term->val.period; val 799 tools/perf/util/evsel.c attr->sample_freq = term->val.freq; val 805 tools/perf/util/evsel.c if (term->val.time) val 811 tools/perf/util/evsel.c callgraph_buf = term->val.callgraph; val 814 tools/perf/util/evsel.c if (term->val.branch && strcmp(term->val.branch, "no")) { val 816 tools/perf/util/evsel.c parse_branch_str(term->val.branch, val 822 tools/perf/util/evsel.c dump_size = term->val.stack_user; val 825 tools/perf/util/evsel.c max_stack = term->val.max_stack; val 828 tools/perf/util/evsel.c evsel->max_events = term->val.max_events; val 837 tools/perf/util/evsel.c attr->inherit = term->val.inherit ? 1 : 0; val 840 tools/perf/util/evsel.c attr->write_backward = term->val.overwrite ? 1 : 0; val 847 tools/perf/util/evsel.c attr->aux_output = term->val.aux_output ? 1 : 0; val 1282 tools/perf/util/evsel.c count->val = count->val - tmp.val; val 1295 tools/perf/util/evsel.c count->val = 0; val 1298 tools/perf/util/evsel.c count->val = (u64)((double) count->val * count->ena / count->run); val 1316 tools/perf/util/evsel.c u64 val, u64 ena, u64 run) val 1322 tools/perf/util/evsel.c count->val = val; val 1519 tools/perf/util/evsel.c static int __open_attr__fprintf(FILE *fp, const char *name, const char *val, val 1522 tools/perf/util/evsel.c return fprintf(fp, " %-32s %s\n", name, val); val 47 tools/perf/util/evsel_config.h } val; val 33 tools/perf/util/evsel_fprintf.c static int __print_attr__fprintf(FILE *fp, const char *name, const char *val, void *priv) val 35 tools/perf/util/evsel_fprintf.c return comma_fprintf(fp, (bool *)priv, " %s: %s", name, val); val 10 tools/perf/util/expr.h double val; val 19 tools/perf/util/expr.h void expr__add_id(struct parse_ctx *ctx, const char *id, double val); val 49 tools/perf/util/expr.y static int lookup_id(struct parse_ctx *ctx, char *id, double *val) val 55 tools/perf/util/expr.y *val = ctx->ids[i].val; val 172 tools/perf/util/expr.y void expr__add_id(struct parse_ctx *ctx, const char *name, double val) val 178 tools/perf/util/expr.y ctx->ids[idx].val = val; val 186 tools/perf/util/expr.y static bool already_seen(const char *val, const char *one, const char **other, val 191 tools/perf/util/expr.y if (one && !strcasecmp(one, val)) val 194 tools/perf/util/expr.y if (!strcasecmp(other[i], val)) val 212 tools/perf/util/expr.y YYSTYPE val; val 213 tools/perf/util/expr.y int tok = expr__lex(&val, &p); val 218 tools/perf/util/expr.y if (tok == ID && !already_seen(val.id, one, *other, num_other)) { val 223 tools/perf/util/expr.y (*other)[num_other] = strdup(val.id); val 1671 tools/perf/util/header.c static int __desc_attr__fprintf(FILE *fp, const char *name, const char *val, val 1674 tools/perf/util/header.c return fprintf(fp, ", %s = %s", name, val); val 1663 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c decoder->state.items.val[pos][id] = decoder->packet.payload; val 155 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint64_t val[INTEL_PT_BLK_TYPE_CNT][INTEL_PT_BLK_ITEM_ID_CNT]; val 407 tools/perf/util/intel-pt.c long val; val 410 tools/perf/util/intel-pt.c val = strtol(value, NULL, 0); val 411 tools/perf/util/intel-pt.c if (val > 0 && val <= INT_MAX) val 412 tools/perf/util/intel-pt.c *d = val; val 1598 tools/perf/util/intel-pt.c const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS]; val 1684 tools/perf/util/intel-pt.c const u64 *from = items->val[i]; val 1975 tools/perf/util/machine.c mi->data_src.val = sample->data_src; val 2444 tools/perf/util/machine.c list_for_each_entry(ilist, &inline_node->val, list) { val 314 tools/perf/util/parse-events.c return term->val.str; val 1020 tools/perf/util/parse-events.c attr->config = term->val.num; val 1024 tools/perf/util/parse-events.c attr->config1 = term->val.num; val 1028 tools/perf/util/parse-events.c attr->config2 = term->val.num; val 1038 tools/perf/util/parse-events.c if (strcmp(term->val.str, "no") && val 1039 tools/perf/util/parse-events.c parse_branch_str(term->val.str, &attr->branch_sample_type)) { val 1047 tools/perf/util/parse-events.c if (term->val.num > 1) { val 1082 tools/perf/util/parse-events.c if ((unsigned int)term->val.num > 1) { val 1182 tools/perf/util/parse-events.c __t->val.__name = __val; \ val 1192 tools/perf/util/parse-events.c ADD_CONFIG_TERM(PERIOD, period, term->val.num); val 1195 tools/perf/util/parse-events.c ADD_CONFIG_TERM(FREQ, freq, term->val.num); val 1198 tools/perf/util/parse-events.c ADD_CONFIG_TERM(TIME, time, term->val.num); val 1201 tools/perf/util/parse-events.c ADD_CONFIG_TERM(CALLGRAPH, callgraph, term->val.str); val 1204 tools/perf/util/parse-events.c ADD_CONFIG_TERM(BRANCH, branch, term->val.str); val 1207 tools/perf/util/parse-events.c ADD_CONFIG_TERM(STACK_USER, stack_user, term->val.num); val 1210 tools/perf/util/parse-events.c ADD_CONFIG_TERM(INHERIT, inherit, term->val.num ? 1 : 0); val 1213 tools/perf/util/parse-events.c ADD_CONFIG_TERM(INHERIT, inherit, term->val.num ? 0 : 1); val 1216 tools/perf/util/parse-events.c ADD_CONFIG_TERM(MAX_STACK, max_stack, term->val.num); val 1219 tools/perf/util/parse-events.c ADD_CONFIG_TERM(MAX_EVENTS, max_events, term->val.num); val 1222 tools/perf/util/parse-events.c ADD_CONFIG_TERM(OVERWRITE, overwrite, term->val.num ? 1 : 0); val 1225 tools/perf/util/parse-events.c ADD_CONFIG_TERM(OVERWRITE, overwrite, term->val.num ? 0 : 1); val 1228 tools/perf/util/parse-events.c ADD_CONFIG_TERM(DRV_CFG, drv_cfg, term->val.str); val 1232 tools/perf/util/parse-events.c term->val.num ? true : false); val 1235 tools/perf/util/parse-events.c ADD_CONFIG_TERM(AUX_OUTPUT, aux_output, term->val.num ? 1 : 0); val 1304 tools/perf/util/parse-events.c return term->val.percore; val 2677 tools/perf/util/parse-events.c term->val.num = num; val 2680 tools/perf/util/parse-events.c term->val.str = str; val 2756 tools/perf/util/parse-events.c return new_term(new, &temp, term->val.str, term->val.num); val 97 tools/perf/util/parse-events.h } val; val 22 tools/perf/util/parse-events.y #define ABORT_ON(val) \ val 24 tools/perf/util/parse-events.y if (val) \ val 73 tools/perf/util/perf_event_attr_fprintf.c #define p_hex(val) snprintf(buf, BUF_SIZE, "%#"PRIx64, (uint64_t)(val)) val 74 tools/perf/util/perf_event_attr_fprintf.c #define p_unsigned(val) snprintf(buf, BUF_SIZE, "%"PRIu64, (uint64_t)(val)) val 75 tools/perf/util/perf_event_attr_fprintf.c #define p_signed(val) snprintf(buf, BUF_SIZE, "%"PRId64, (int64_t)(val)) val 76 tools/perf/util/perf_event_attr_fprintf.c #define p_sample_type(val) __p_sample_type(buf, BUF_SIZE, val) val 77 tools/perf/util/perf_event_attr_fprintf.c #define p_branch_sample_type(val) __p_branch_sample_type(buf, BUF_SIZE, val) val 78 tools/perf/util/perf_event_attr_fprintf.c #define p_read_format(val) __p_read_format(buf, BUF_SIZE, val) val 307 tools/perf/util/pmu.c char *desc, char *val, val 329 tools/perf/util/pmu.c ret = parse_events_terms(&alias->terms, val); val 331 tools/perf/util/pmu.c pr_err("Cannot parse alias %s: %d\n", val, ret); val 351 tools/perf/util/pmu.c "%s=%#x", term->config, term->val.num); val 354 tools/perf/util/pmu.c "%s=%s", term->config, term->val.str); val 978 tools/perf/util/pmu.c *value = t->val.num; val 1024 tools/perf/util/pmu.c __u64 val, max_val; val 1083 tools/perf/util/pmu.c val = term->val.num; val 1085 tools/perf/util/pmu.c if (strcmp(term->val.str, "?")) { val 1088 tools/perf/util/pmu.c term->config, term->val.str); val 1097 tools/perf/util/pmu.c if (pmu_resolve_param_term(term, head_terms, &val)) val 1103 tools/perf/util/pmu.c if (val > max_val) { val 1118 tools/perf/util/pmu.c pmu_format_value(format->bits, val, vp, zero); val 1164 tools/perf/util/pmu.c if (term->val.num != 1) val 1172 tools/perf/util/pmu.c name = term->val.str; val 1314 tools/perf/util/pmu.c term->val.str); val 15 tools/perf/util/pmu.y #define ABORT_ON(val) \ val 17 tools/perf/util/pmu.y if (val) \ val 22 tools/perf/util/print_binary.h unsigned int val, void *extra, FILE *fp); val 1197 tools/perf/util/probe-event.c static int parse_line_num(char **ptr, int *val, const char *what) val 1202 tools/perf/util/probe-event.c *val = strtol(*ptr, ptr, 0); val 360 tools/perf/util/python.c unsigned long long val; val 367 tools/perf/util/python.c val = tep_read_number(pevent, data + offset, len); val 368 tools/perf/util/python.c offset = val; val 380 tools/perf/util/python.c val = tep_read_number(pevent, data + field->offset, val 383 tools/perf/util/python.c ret = PyLong_FromUnsignedLong((unsigned long) val); val 385 tools/perf/util/python.c ret = PyLong_FromLong((long) val); val 387 tools/perf/util/python.c ret = PyLong_FromUnsignedLong((unsigned long) val); val 346 tools/perf/util/scripting-engines/trace-event-perl.c unsigned long long val; val 402 tools/perf/util/scripting-engines/trace-event-perl.c val = read_size(event, data + field->offset, val 405 tools/perf/util/scripting-engines/trace-event-perl.c XPUSHs(sv_2mortal(newSViv(val))); val 407 tools/perf/util/scripting-engines/trace-event-perl.c XPUSHs(sv_2mortal(newSVuv(val))); val 137 tools/perf/util/scripting-engines/trace-event-python.c static void pydict_set_item_string_decref(PyObject *dict, const char *key, PyObject *val) val 139 tools/perf/util/scripting-engines/trace-event-python.c PyDict_SetItemString(dict, key, val); val 140 tools/perf/util/scripting-engines/trace-event-python.c Py_DECREF(val); val 344 tools/perf/util/scripting-engines/trace-event-python.c unsigned long long val; val 358 tools/perf/util/scripting-engines/trace-event-python.c val = read_size(event, data + field->offset + i * item_size, val 361 tools/perf/util/scripting-engines/trace-event-python.c if ((long long)val >= LONG_MIN && val 362 tools/perf/util/scripting-engines/trace-event-python.c (long long)val <= LONG_MAX) val 363 tools/perf/util/scripting-engines/trace-event-python.c obj = _PyLong_FromLong(val); val 365 tools/perf/util/scripting-engines/trace-event-python.c obj = PyLong_FromLongLong(val); val 367 tools/perf/util/scripting-engines/trace-event-python.c if (val <= LONG_MAX) val 368 tools/perf/util/scripting-engines/trace-event-python.c obj = _PyLong_FromLong(val); val 370 tools/perf/util/scripting-engines/trace-event-python.c obj = PyLong_FromUnsignedLongLong(val); val 676 tools/perf/util/scripting-engines/trace-event-python.c struct mem_info mi = { .data_src.val = sample->data_src }; val 696 tools/perf/util/scripting-engines/trace-event-python.c u64 val = regs->regs[i++]; val 700 tools/perf/util/scripting-engines/trace-event-python.c perf_reg_name(r), val); val 871 tools/perf/util/scripting-engines/trace-event-python.c unsigned long long val; val 877 tools/perf/util/scripting-engines/trace-event-python.c val = tep_read_number(scripting_context->pevent, val 879 tools/perf/util/scripting-engines/trace-event-python.c offset = val; val 932 tools/perf/util/scripting-engines/trace-event-python.c static int tuple_set_u64(PyObject *t, unsigned int pos, u64 val) val 935 tools/perf/util/scripting-engines/trace-event-python.c return PyTuple_SetItem(t, pos, _PyLong_FromLong(val)); val 938 tools/perf/util/scripting-engines/trace-event-python.c return PyTuple_SetItem(t, pos, PyLong_FromLongLong(val)); val 942 tools/perf/util/scripting-engines/trace-event-python.c static int tuple_set_s32(PyObject *t, unsigned int pos, s32 val) val 944 tools/perf/util/scripting-engines/trace-event-python.c return PyTuple_SetItem(t, pos, _PyLong_FromLong(val)); val 1380 tools/perf/util/scripting-engines/trace-event-python.c tuple_set_u64(t, n++, count->val); val 897 tools/perf/util/session.c event->stat.val = bswap_64(event->stat.val); val 1096 tools/perf/util/session.c u64 val = regs[i++]; val 1099 tools/perf/util/session.c perf_reg_name(rid), val); val 52 tools/perf/util/srcline.c list_add_tail(&ilist->list, &node->val); val 54 tools/perf/util/srcline.c list_add(&ilist->list, &node->val); val 375 tools/perf/util/srcline.c INIT_LIST_HEAD(&node->val); val 476 tools/perf/util/srcline.c INIT_LIST_HEAD(&node->val); val 693 tools/perf/util/srcline.c list_for_each_entry_safe(ilist, tmp, &node->val, list) { val 38 tools/perf/util/srcline.h struct list_head val; val 164 tools/perf/util/stat-display.c const char *unit, double val) val 183 tools/perf/util/stat-display.c n += color_fprintf(out, color, fmt, val); val 185 tools/perf/util/stat-display.c n += fprintf(out, fmt, val); val 205 tools/perf/util/stat-display.c const char *fmt, const char *unit, double val) val 215 tools/perf/util/stat-display.c snprintf(buf, sizeof(buf), fmt, val); val 250 tools/perf/util/stat-display.c const char *unit, double val) val 266 tools/perf/util/stat-display.c color_snprintf(str, sizeof(str), color ?: "", fmt, val); val 273 tools/perf/util/stat-display.c const char *unit, double val) val 283 tools/perf/util/stat-display.c snprintf(buf, sizeof buf, fmt, val); val 299 tools/perf/util/stat-display.c const char *unit, double val __maybe_unused) val 496 tools/perf/util/stat-display.c u64 val; val 502 tools/perf/util/stat-display.c val = 0; val 507 tools/perf/util/stat-display.c val += perf_counts(counter->counts, cpu, 0)->val; val 509 tools/perf/util/stat-display.c perf_stat__update_shadow_stats(counter, val, val 582 tools/perf/util/stat-display.c u64 ena, run, val; val 613 tools/perf/util/stat-display.c ad->val += counts->val; val 626 tools/perf/util/stat-display.c u64 ena, run, val; val 631 tools/perf/util/stat-display.c ad.val = ad.ena = ad.run = 0; val 639 tools/perf/util/stat-display.c val = ad.val; val 647 tools/perf/util/stat-display.c uval = val * counter->scale; val 690 tools/perf/util/stat-display.c return ((struct perf_aggr_thread_value *)b)->val - val 691 tools/perf/util/stat-display.c ((struct perf_aggr_thread_value *)a)->val; val 709 tools/perf/util/stat-display.c u64 ena = 0, run = 0, val = 0; val 712 tools/perf/util/stat-display.c val += perf_counts(counter->counts, cpu, thread)->val; val 717 tools/perf/util/stat-display.c uval = val * counter->scale; val 729 tools/perf/util/stat-display.c buf[i].val = val; val 825 tools/perf/util/stat-display.c ad->val += perf_counts(counter->counts, ad->cpu, 0)->val; val 838 tools/perf/util/stat-display.c u64 ena, run, val; val 847 tools/perf/util/stat-display.c val = ad.val; val 854 tools/perf/util/stat-display.c uval = val * counter->scale; val 869 tools/perf/util/stat-display.c u64 ena, run, val; val 883 tools/perf/util/stat-display.c val = perf_counts(counter->counts, cpu, 0)->val; val 887 tools/perf/util/stat-display.c uval = val * counter->scale; val 18 tools/perf/util/stat.c void update_stats(struct stats *stats, u64 val) val 23 tools/perf/util/stat.c delta = val - stats->mean; val 25 tools/perf/util/stat.c stats->M2 += delta*(val - stats->mean); val 27 tools/perf/util/stat.c if (val > stats->max) val 28 tools/perf/util/stat.c stats->max = val; val 30 tools/perf/util/stat.c if (val < stats->min) val 31 tools/perf/util/stat.c stats->min = val; val 168 tools/perf/util/stat.c evsel->prev_raw_counts->aggr.val = 0; val 307 tools/perf/util/stat.c perf_stat__update_shadow_stats(evsel, count->val, val 314 tools/perf/util/stat.c count->val, 0, &config->stats[thread]); val 317 tools/perf/util/stat.c count->val, 0, &rt_stat); val 321 tools/perf/util/stat.c aggr->val += count->val; val 361 tools/perf/util/stat.c aggr->val = aggr->ena = aggr->run = 0; val 410 tools/perf/util/stat.c count.val = st->val; val 433 tools/perf/util/stat.c st->val, st->ena, st->run); val 131 tools/perf/util/stat.h void update_stats(struct stats *stats, u64 val); val 152 tools/perf/util/stat.h u64 val; val 168 tools/perf/util/stat.h const char *fmt, double val); val 42 tools/perf/util/symbol-elf.c #define GELF_ST_VISIBILITY(val) ELF64_ST_VISIBILITY (val) val 1071 tools/perf/util/synthetic-events.c event->data[i].val = __val; \ val 1103 tools/perf/util/synthetic-events.c event.val = count->val; val 84 tools/perf/util/trace-event-parse.c unsigned long long val; val 90 tools/perf/util/trace-event-parse.c tep_read_number_field(field, data, &val); val 92 tools/perf/util/trace-event-parse.c return val; val 111 tools/perf/util/unwind-libunwind-local.c static int __dw_read_encoded_value(u8 **p, u8 *end, u64 *val, val 115 tools/perf/util/unwind-libunwind-local.c *val = 0; val 119 tools/perf/util/unwind-libunwind-local.c *val = 0; val 122 tools/perf/util/unwind-libunwind-local.c *val = dw_read(cur, unsigned long, end); val 132 tools/perf/util/unwind-libunwind-local.c *val = (unsigned long) cur; val 143 tools/perf/util/unwind-libunwind-local.c *val += dw_read(cur, s32, end); val 146 tools/perf/util/unwind-libunwind-local.c *val += dw_read(cur, u32, end); val 149 tools/perf/util/unwind-libunwind-local.c *val += dw_read(cur, s64, end); val 152 tools/perf/util/unwind-libunwind-local.c *val += dw_read(cur, u64, end); val 431 tools/perf/util/unwind-libunwind-local.c unw_fpreg_t __maybe_unused *val, val 537 tools/perf/util/unwind-libunwind-local.c u64 val; val 554 tools/perf/util/unwind-libunwind-local.c ret = perf_reg_value(&val, &ui->sample->user_regs, id); val 560 tools/perf/util/unwind-libunwind-local.c *valp = (unw_word_t) val; val 643 tools/perf/util/unwind-libunwind-local.c u64 val; val 649 tools/perf/util/unwind-libunwind-local.c ret = perf_reg_value(&val, &ui->sample->user_regs, val 654 tools/perf/util/unwind-libunwind-local.c ips[i++] = (unw_word_t) val; val 158 tools/power/cpupower/bench/parse.c char opt[16], val[32], *line = NULL; val 178 tools/power/cpupower/bench/parse.c if (sscanf(line, "%14s = %30s", opt, val) < 2) val 181 tools/power/cpupower/bench/parse.c dprintf("parsing: %s -> %s\n", opt, val); val 184 tools/power/cpupower/bench/parse.c sscanf(val, "%li", &config->sleep); val 187 tools/power/cpupower/bench/parse.c sscanf(val, "%li", &config->load); val 190 tools/power/cpupower/bench/parse.c sscanf(val, "%li", &config->load_step); val 193 tools/power/cpupower/bench/parse.c sscanf(val, "%li", &config->sleep_step); val 196 tools/power/cpupower/bench/parse.c sscanf(val, "%u", &config->cycles); val 199 tools/power/cpupower/bench/parse.c sscanf(val, "%u", &config->rounds); val 202 tools/power/cpupower/bench/parse.c sscanf(val, "%u", &config->verbose); val 205 tools/power/cpupower/bench/parse.c config->output = prepare_output(val); val 208 tools/power/cpupower/bench/parse.c sscanf(val, "%u", &config->cpu); val 211 tools/power/cpupower/bench/parse.c strncpy(config->governor, val, val 217 tools/power/cpupower/bench/parse.c if (string_to_prio(val) != SCHED_ERR) val 218 tools/power/cpupower/bench/parse.c config->prio = string_to_prio(val); val 33 tools/power/cpupower/debug/i386/centrino-decode.c unsigned long long val; val 50 tools/power/cpupower/debug/i386/centrino-decode.c if (read(fd, &val, 8) != 8) val 53 tools/power/cpupower/debug/i386/centrino-decode.c *lo = (uint32_t )(val & 0xffffffffull); val 54 tools/power/cpupower/debug/i386/centrino-decode.c *hi = (uint32_t )(val>>32 & 0xffffffffull); val 39 tools/power/cpupower/utils/helpers/amd.c unsigned long long val; val 47 tools/power/cpupower/utils/helpers/amd.c t = pstate.val & 0xf; val 93 tools/power/cpupower/utils/helpers/amd.c unsigned long long val; val 102 tools/power/cpupower/utils/helpers/amd.c if (read_msr(cpu, MSR_AMD_PSTATE_LIMIT, &val)) val 105 tools/power/cpupower/utils/helpers/amd.c psmax = (val >> 4) & 0x7; val 107 tools/power/cpupower/utils/helpers/amd.c if (read_msr(cpu, MSR_AMD_PSTATE_STATUS, &val)) val 110 tools/power/cpupower/utils/helpers/amd.c pscur = val & 0x7; val 120 tools/power/cpupower/utils/helpers/amd.c if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val)) val 137 tools/power/cpupower/utils/helpers/amd.c uint8_t val = 0; val 146 tools/power/cpupower/utils/helpers/amd.c val = pci_read_byte(device, 0x15c); val 147 tools/power/cpupower/utils/helpers/amd.c if (val & 3) val 151 tools/power/cpupower/utils/helpers/amd.c *states = (val >> 2) & 7; val 104 tools/power/cpupower/utils/helpers/helpers.h extern int read_msr(int cpu, unsigned int idx, unsigned long long *val); val 105 tools/power/cpupower/utils/helpers/helpers.h extern int write_msr(int cpu, unsigned int idx, unsigned long long val); val 107 tools/power/cpupower/utils/helpers/helpers.h extern int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val); val 148 tools/power/cpupower/utils/helpers/helpers.h static inline int read_msr(int cpu, unsigned int idx, unsigned long long *val) val 150 tools/power/cpupower/utils/helpers/helpers.h static inline int write_msr(int cpu, unsigned int idx, unsigned long long val) val 152 tools/power/cpupower/utils/helpers/helpers.h static inline int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val) val 13 tools/power/cpupower/utils/helpers/misc.c unsigned long long val; val 30 tools/power/cpupower/utils/helpers/misc.c if (!read_msr(cpu, MSR_AMD_HWCR, &val)) { val 31 tools/power/cpupower/utils/helpers/misc.c if (!(val & CPUPOWER_AMD_CPBDIS)) val 27 tools/power/cpupower/utils/helpers/msr.c int read_msr(int cpu, unsigned int idx, unsigned long long *val) val 38 tools/power/cpupower/utils/helpers/msr.c if (read(fd, val, sizeof *val) != sizeof *val) val 56 tools/power/cpupower/utils/helpers/msr.c int write_msr(int cpu, unsigned int idx, unsigned long long val) val 67 tools/power/cpupower/utils/helpers/msr.c if (write(fd, &val, sizeof val) != sizeof val) val 78 tools/power/cpupower/utils/helpers/msr.c unsigned long long val; val 84 tools/power/cpupower/utils/helpers/msr.c ret = read_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &val); val 87 tools/power/cpupower/utils/helpers/msr.c return val; val 90 tools/power/cpupower/utils/helpers/msr.c int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val) val 97 tools/power/cpupower/utils/helpers/msr.c ret = write_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, val); val 105 tools/power/cpupower/utils/helpers/msr.c unsigned long long val; val 111 tools/power/cpupower/utils/helpers/msr.c ret = read_msr(cpu, MSR_NEHALEM_TURBO_RATIO_LIMIT, &val); val 114 tools/power/cpupower/utils/helpers/msr.c return val; val 468 tools/power/cpupower/utils/helpers/sysfs.c int sysfs_set_sched(const char *smt_mc, int val) val 37 tools/power/cpupower/utils/helpers/sysfs.h extern int sysfs_set_sched(const char *smt_mc, int val); val 127 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c uint32_t val; val 135 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val = pci_read_long(amd_fam14h_pci_dev, pci_offset); val 136 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val |= 1 << enable_bit; val 137 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val = pci_write_long(amd_fam14h_pci_dev, pci_offset, val); val 142 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val = pci_read_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG); val 144 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c PCI_MONITOR_ENABLE_REG, (unsigned int) val); val 145 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val |= 1 << enable_bit; val 146 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c pci_write_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG, val); val 150 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c (unsigned int) val, cpu); val 162 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c uint32_t val; val 168 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val = pci_read_long(amd_fam14h_pci_dev, pci_offset); val 169 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c dprint("%s: offset: 0x%x %u\n", state->name, pci_offset, val); val 172 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c nbp1_entered = (val & (1 << PCI_NBP1_ACTIVE_BIT)) | val 173 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c (val & (1 << PCI_NBP1_ENTERED_BIT)); val 178 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val, enable_bit, pci_offset); val 181 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c current_count[state->id][cpu] = val; val 188 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val = pci_read_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG); val 189 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val &= ~(1 << enable_bit); val 190 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c pci_write_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG, val); val 271 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c uint32_t val; val 272 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c val = pci_read_long(amd_fam14h_pci_dev, PCI_NBP1_CAP_OFFSET); val 273 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c return val & (1 << 31); val 62 tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c static int hsw_ext_get_count(enum intel_hsw_ext_id id, unsigned long long *val, val 83 tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c if (read_msr(cpu, msr, val)) val 116 tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c unsigned long long val; val 120 tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c hsw_ext_get_count(num, &val, cpu); val 121 tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c previous_count[num][cpu] = val; val 130 tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c unsigned long long val; val 137 tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c is_valid[cpu] = !hsw_ext_get_count(num, &val, cpu); val 138 tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c current_count[num][cpu] = val; val 91 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c unsigned long long val; val 94 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c ret = read_msr(cpu, MSR_APERF, &val); val 95 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c aperf_previous_count[cpu] = val; val 96 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c ret |= read_msr(cpu, MSR_MPERF, &val); val 97 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c mperf_previous_count[cpu] = val; val 105 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c unsigned long long val; val 108 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c ret = read_msr(cpu, MSR_APERF, &val); val 109 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c aperf_current_count[cpu] = val; val 110 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c ret |= read_msr(cpu, MSR_MPERF, &val); val 111 tools/power/cpupower/utils/idle_monitor/mperf_monitor.c mperf_current_count[cpu] = val; val 71 tools/power/cpupower/utils/idle_monitor/nhm_idle.c static int nhm_get_count(enum intel_nhm_id id, unsigned long long *val, val 95 tools/power/cpupower/utils/idle_monitor/nhm_idle.c if (read_msr(cpu, msr, val)) val 129 tools/power/cpupower/utils/idle_monitor/nhm_idle.c unsigned long long dbg, val; val 135 tools/power/cpupower/utils/idle_monitor/nhm_idle.c is_valid[cpu] = !nhm_get_count(num, &val, cpu); val 136 tools/power/cpupower/utils/idle_monitor/nhm_idle.c previous_count[num][cpu] = val; val 146 tools/power/cpupower/utils/idle_monitor/nhm_idle.c unsigned long long val; val 154 tools/power/cpupower/utils/idle_monitor/nhm_idle.c is_valid[cpu] = !nhm_get_count(num, &val, cpu); val 155 tools/power/cpupower/utils/idle_monitor/nhm_idle.c current_count[num][cpu] = val; val 60 tools/power/cpupower/utils/idle_monitor/snb_idle.c static int snb_get_count(enum intel_snb_id id, unsigned long long *val, val 81 tools/power/cpupower/utils/idle_monitor/snb_idle.c if (read_msr(cpu, msr, val)) val 114 tools/power/cpupower/utils/idle_monitor/snb_idle.c unsigned long long val; val 118 tools/power/cpupower/utils/idle_monitor/snb_idle.c snb_get_count(num, &val, cpu); val 119 tools/power/cpupower/utils/idle_monitor/snb_idle.c previous_count[num][cpu] = val; val 128 tools/power/cpupower/utils/idle_monitor/snb_idle.c unsigned long long val; val 135 tools/power/cpupower/utils/idle_monitor/snb_idle.c is_valid[cpu] = !snb_get_count(num, &val, cpu); val 136 tools/power/cpupower/utils/idle_monitor/snb_idle.c current_count[num][cpu] = val; val 291 tools/power/x86/intel-speed-select/isst-display.c unsigned int val) val 304 tools/power/x86/intel-speed-select/isst-display.c snprintf(value, sizeof(value), "%u", val); val 199 tools/power/x86/intel-speed-select/isst.h unsigned int val); val 231 tools/power/x86/intel-speed-select/isst.h extern int isst_read_reg(unsigned short reg, unsigned int *val); val 232 tools/power/x86/intel-speed-select/isst.h extern int isst_write_reg(int reg, unsigned int val); val 1569 tools/testing/nvdimm/test/nfit.c unsigned long val; val 1575 tools/testing/nvdimm/test/nfit.c rc = kstrtol(buf, 0, &val); val 1579 tools/testing/nvdimm/test/nfit.c dimm_fail_cmd_flags[dimm] = val; val 1599 tools/testing/nvdimm/test/nfit.c unsigned long val; val 1605 tools/testing/nvdimm/test/nfit.c rc = kstrtol(buf, 0, &val); val 1609 tools/testing/nvdimm/test/nfit.c dimm_fail_cmd_code[dimm] = val; val 2 tools/testing/radix-tree/linux/percpu.h #define DECLARE_PER_CPU(type, val) extern type val val 3 tools/testing/radix-tree/linux/percpu.h #define DEFINE_PER_CPU(type, val) type val val 8 tools/testing/radix-tree/linux/percpu.h #define this_cpu_xchg(var, val) uatomic_xchg(&var, val) val 5 tools/testing/selftests/bpf/bpf_helpers.h #define __uint(name, val) int (*name)[val] val 6 tools/testing/selftests/bpf/bpf_helpers.h #define __type(name, val) typeof(val) *name val 77 tools/testing/selftests/bpf/prog_tests/global_data.c struct foo val; val 86 tools/testing/selftests/bpf/prog_tests/global_data.c struct foo val; val 95 tools/testing/selftests/bpf/prog_tests/global_data.c err = bpf_map_lookup_elem(map_fd, &tests[i].key, &val); val 96 tools/testing/selftests/bpf/prog_tests/global_data.c CHECK(err || memcmp(&val, &tests[i].val, sizeof(val)), val 98 tools/testing/selftests/bpf/prog_tests/global_data.c err, val.a, val.b, val.c, tests[i].val.a, tests[i].val.b, tests[i].val.c); val 12 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c __u32 vals[MAP_SIZE], duration, retval, size, val; val 53 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c val = vals[i]; val 56 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c val = vals[MAP_SIZE - 1 - i]; val 63 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c iph->daddr != val) val 67 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c CHECK(err || retval || size != sizeof(pkt_v4) || iph->daddr != val, val 82 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c err = bpf_map_lookup_and_delete_elem(map_out_fd, NULL, &val); val 83 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c if (err || val != vals[i] * 5) val 87 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c CHECK(i != MAP_SIZE && (err || val != vals[i] * 5), val 88 tools/testing/selftests/bpf/prog_tests/queue_stack_map.c "bpf_map_push_elem", "err %d value %u\n", err, val); val 22 tools/testing/selftests/bpf/prog_tests/send_signal.c __u64 val; val 113 tools/testing/selftests/bpf/prog_tests/send_signal.c val = (((__u64)(SIGUSR1)) << 32) | pid; val 114 tools/testing/selftests/bpf/prog_tests/send_signal.c bpf_map_update_elem(info_map_fd, &key, &val, 0); val 10 tools/testing/selftests/bpf/prog_tests/stacktrace_build_id.c __u32 key, previous_key, val, duration = 0; val 60 tools/testing/selftests/bpf/prog_tests/stacktrace_build_id.c val = 1; val 61 tools/testing/selftests/bpf/prog_tests/stacktrace_build_id.c bpf_map_update_elem(control_map_fd, &key, &val, 0); val 28 tools/testing/selftests/bpf/prog_tests/stacktrace_build_id_nmi.c __u32 key, previous_key, val, duration = 0; val 95 tools/testing/selftests/bpf/prog_tests/stacktrace_build_id_nmi.c val = 1; val 96 tools/testing/selftests/bpf/prog_tests/stacktrace_build_id_nmi.c bpf_map_update_elem(control_map_fd, &key, &val, 0); val 10 tools/testing/selftests/bpf/prog_tests/stacktrace_map.c __u32 key, val, duration = 0; val 49 tools/testing/selftests/bpf/prog_tests/stacktrace_map.c val = 1; val 50 tools/testing/selftests/bpf/prog_tests/stacktrace_map.c bpf_map_update_elem(control_map_fd, &key, &val, 0); val 9 tools/testing/selftests/bpf/prog_tests/stacktrace_map_raw_tp.c __u32 key, val, duration = 0; val 45 tools/testing/selftests/bpf/prog_tests/stacktrace_map_raw_tp.c val = 1; val 46 tools/testing/selftests/bpf/prog_tests/stacktrace_map_raw_tp.c bpf_map_update_elem(control_map_fd, &key, &val, 0); val 50 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c struct tcp_rtt_storage val; val 52 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c if (CHECK_FAIL(bpf_map_lookup_elem(map_fd, &client_fd, &val) < 0)) { val 57 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c if (val.invoked != invoked) { val 59 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c msg, val.invoked, invoked); val 63 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c if (val.dsack_dups != dsack_dups) { val 65 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c msg, val.dsack_dups, dsack_dups); val 69 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c if (val.delivered != delivered) { val 71 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c msg, val.delivered, delivered); val 75 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c if (val.delivered_ce != delivered_ce) { val 77 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c msg, val.delivered_ce, delivered_ce); val 81 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c if (val.icsk_retransmits != icsk_retransmits) { val 83 tools/testing/selftests/bpf/prog_tests/tcp_rtt.c msg, val.icsk_retransmits, icsk_retransmits); val 78 tools/testing/selftests/bpf/progs/bpf_flow.c struct bpf_flow_keys val; val 80 tools/testing/selftests/bpf/progs/bpf_flow.c memcpy(&val, keys, sizeof(val)); val 81 tools/testing/selftests/bpf/progs/bpf_flow.c bpf_map_update_elem(&last_dissection, &key, &val, BPF_ANY); val 26 tools/testing/selftests/bpf/progs/get_cgroup_id_kern.c __u64 *val; val 32 tools/testing/selftests/bpf/progs/get_cgroup_id_kern.c val = bpf_map_lookup_elem(&cg_ids, &key); val 33 tools/testing/selftests/bpf/progs/get_cgroup_id_kern.c if (val) val 34 tools/testing/selftests/bpf/progs/get_cgroup_id_kern.c *val = bpf_get_current_cgroup_id(); val 14 tools/testing/selftests/bpf/progs/sockopt_inherit.c __u8 val; val 70 tools/testing/selftests/bpf/progs/sockopt_inherit.c optval[0] = storage->val; val 93 tools/testing/selftests/bpf/progs/sockopt_inherit.c storage->val = optval[0]; val 14 tools/testing/selftests/bpf/progs/sockopt_sk.c __u8 val; val 72 tools/testing/selftests/bpf/progs/sockopt_sk.c optval[0] = storage->val; val 127 tools/testing/selftests/bpf/progs/sockopt_sk.c storage->val = optval[0]; val 55 tools/testing/selftests/bpf/progs/strobemeta.h int64_t val; val 77 tools/testing/selftests/bpf/progs/strobemeta.h const char* val; val 247 tools/testing/selftests/bpf/progs/strobemeta.h void* val; val 340 tools/testing/selftests/bpf/progs/strobemeta.h data->int_vals[idx] = value->val; val 429 tools/testing/selftests/bpf/progs/strobemeta.h map.entries[i].val); val 36 tools/testing/selftests/bpf/progs/test_map_lock.c struct hmap_elem zero = {}, *val; val 41 tools/testing/selftests/bpf/progs/test_map_lock.c val = bpf_map_lookup_elem(&hash_map, &key); val 42 tools/testing/selftests/bpf/progs/test_map_lock.c if (!val) val 45 tools/testing/selftests/bpf/progs/test_map_lock.c bpf_spin_lock(&val->lock); val 47 tools/testing/selftests/bpf/progs/test_map_lock.c val->var[i] = rnd; val 48 tools/testing/selftests/bpf/progs/test_map_lock.c bpf_spin_unlock(&val->lock); val 52 tools/testing/selftests/bpf/progs/test_spin_lock.c struct hmap_elem zero = {}, *val; val 59 tools/testing/selftests/bpf/progs/test_spin_lock.c val = bpf_map_lookup_elem(&hmap, &key); val 60 tools/testing/selftests/bpf/progs/test_spin_lock.c if (!val) { val 62 tools/testing/selftests/bpf/progs/test_spin_lock.c val = bpf_map_lookup_elem(&hmap, &key); val 63 tools/testing/selftests/bpf/progs/test_spin_lock.c if (!val) { val 69 tools/testing/selftests/bpf/progs/test_spin_lock.c bpf_spin_lock(&val->lock); val 70 tools/testing/selftests/bpf/progs/test_spin_lock.c if (val->cnt) val 71 tools/testing/selftests/bpf/progs/test_spin_lock.c val->cnt--; val 73 tools/testing/selftests/bpf/progs/test_spin_lock.c val->cnt++; val 74 tools/testing/selftests/bpf/progs/test_spin_lock.c if (val->cnt != 0 && val->cnt != 1) val 76 tools/testing/selftests/bpf/progs/test_spin_lock.c bpf_spin_unlock(&val->lock); val 55 tools/testing/selftests/bpf/progs/test_stacktrace_build_id.c __u32 key = 0, val = 0, *value_p; val 65 tools/testing/selftests/bpf/progs/test_stacktrace_build_id.c bpf_map_update_elem(&stackid_hmap, &key, &val, 0); val 57 tools/testing/selftests/bpf/progs/test_stacktrace_map.c __u32 key = 0, val = 0, *value_p; val 67 tools/testing/selftests/bpf/progs/test_stacktrace_map.c bpf_map_update_elem(&stackid_hmap, &key, &val, 0); val 41 tools/testing/selftests/bpf/progs/test_tcp_estats.c #define _(P) ({typeof(P) val = 0; bpf_probe_read(&val, sizeof(val), &P); val;}) val 41 tools/testing/selftests/bpf/test_btf.h #define BTF_ENUM_ENC(name, val) (name), (val) val 219 tools/testing/selftests/bpf/test_cgroup_attach.c static int prog_load_cnt(int verdict, int val) val 253 tools/testing/selftests/bpf/test_cgroup_attach.c BPF_MOV64_IMM(BPF_REG_1, val), /* r1 = 1 */ val 259 tools/testing/selftests/bpf/test_cgroup_attach.c BPF_MOV64_IMM(BPF_REG_1, val), val 185 tools/testing/selftests/bpf/test_flow_dissector.c uint16_t val, *ptr = (uint16_t *)ip6h; val 187 tools/testing/selftests/bpf/test_flow_dissector.c val = ntohs(*ptr); val 188 tools/testing/selftests/bpf/test_flow_dissector.c val &= 0xF00F; val 189 tools/testing/selftests/bpf/test_flow_dissector.c val |= ((uint16_t) dsfield) << 4; val 190 tools/testing/selftests/bpf/test_flow_dissector.c *ptr = htons(val); val 33 tools/testing/selftests/bpf/test_libbpf_open.c long_options[i].val); val 529 tools/testing/selftests/bpf/test_maps.c __u32 vals[MAP_SIZE + MAP_SIZE/2], val; val 537 tools/testing/selftests/bpf/test_maps.c fd = bpf_create_map(BPF_MAP_TYPE_QUEUE, 4, sizeof(val), MAP_SIZE, val 541 tools/testing/selftests/bpf/test_maps.c fd = bpf_create_map(BPF_MAP_TYPE_QUEUE, 0, sizeof(val), MAP_SIZE, val 558 tools/testing/selftests/bpf/test_maps.c assert(bpf_map_update_elem(fd, NULL, &val, 0) == -1 && val 562 tools/testing/selftests/bpf/test_maps.c assert(bpf_map_lookup_elem(fd, NULL, &val) == 0 && val == vals[0]); val 570 tools/testing/selftests/bpf/test_maps.c assert(bpf_map_lookup_and_delete_elem(fd, NULL, &val) == 0 && val 571 tools/testing/selftests/bpf/test_maps.c val == vals[i]); val 574 tools/testing/selftests/bpf/test_maps.c assert(bpf_map_lookup_and_delete_elem(fd, NULL, &val) == -1 && val 587 tools/testing/selftests/bpf/test_maps.c __u32 vals[MAP_SIZE + MAP_SIZE/2], val; val 595 tools/testing/selftests/bpf/test_maps.c fd = bpf_create_map(BPF_MAP_TYPE_STACK, 4, sizeof(val), MAP_SIZE, val 599 tools/testing/selftests/bpf/test_maps.c fd = bpf_create_map(BPF_MAP_TYPE_STACK, 0, sizeof(val), MAP_SIZE, val 616 tools/testing/selftests/bpf/test_maps.c assert(bpf_map_update_elem(fd, NULL, &val, 0) == -1 && val 620 tools/testing/selftests/bpf/test_maps.c assert(bpf_map_lookup_elem(fd, NULL, &val) == 0 && val == vals[i - 1]); val 628 tools/testing/selftests/bpf/test_maps.c assert(bpf_map_lookup_and_delete_elem(fd, NULL, &val) == 0 && val 629 tools/testing/selftests/bpf/test_maps.c val == vals[i]); val 632 tools/testing/selftests/bpf/test_maps.c assert(bpf_map_lookup_and_delete_elem(fd, NULL, &val) == -1 && val 97 tools/testing/selftests/bpf/test_socket_cookie.c struct socket_cookie val; val 108 tools/testing/selftests/bpf/test_socket_cookie.c err = bpf_map_lookup_elem(map_fd, &client_fd, &val); val 117 tools/testing/selftests/bpf/test_socket_cookie.c if (val.cookie_value != cookie_expected_value) { val 118 tools/testing/selftests/bpf/test_socket_cookie.c log_err("Unexpected value in map: %x != %x", val.cookie_value, val 129 tools/testing/selftests/bpf/test_sockmap.c printf(" -%c\n", long_options[i].val); val 210 tools/testing/selftests/bpf/test_verifier.c uint64_t val = bpf_semi_rand_get(); val 211 tools/testing/selftests/bpf/test_verifier.c struct bpf_insn tmp[2] = { BPF_LD_IMM64(BPF_REG_1, val) }; val 213 tools/testing/selftests/bpf/test_verifier.c res ^= val; val 206 tools/testing/selftests/breakpoints/breakpoint_test.c char val; val 154 tools/testing/selftests/futex/functional/futex_requeue_pi.c while (waiters_blocked.val < THREAD_MAX) val 172 tools/testing/selftests/futex/functional/futex_requeue_pi.c if (task_count < THREAD_MAX - waiters_woken.val) val 202 tools/testing/selftests/futex/functional/futex_requeue_pi.c while (waiters_blocked.val < THREAD_MAX) val 206 tools/testing/selftests/futex/functional/futex_requeue_pi.c while (task_count < THREAD_MAX && waiters_woken.val < THREAD_MAX) { val 208 tools/testing/selftests/futex/functional/futex_requeue_pi.c task_count, waiters_woken.val); val 253 tools/testing/selftests/futex/functional/futex_requeue_pi.c info("Waker: waiters_woken: %d\n", waiters_woken.val); val 89 tools/testing/selftests/futex/functional/futex_requeue_pi_signal_restart.c requeued.val ? "after" : "prior to"); val 104 tools/testing/selftests/futex/functional/futex_requeue_pi_signal_restart.c if (!requeued.val || errno != EWOULDBLOCK) { val 37 tools/testing/selftests/futex/functional/futex_wait_private_mapped_file.c futex_t val = 1; val 57 tools/testing/selftests/futex/functional/futex_wait_private_mapped_file.c ret = futex_wait(&val, 1, &wait_timeout, 0); val 111 tools/testing/selftests/futex/functional/futex_wait_private_mapped_file.c val = 2; val 112 tools/testing/selftests/futex/functional/futex_wait_private_mapped_file.c res = futex_wake(&val, 1, 0); val 22 tools/testing/selftests/futex/include/atomic.h volatile int val; val 38 tools/testing/selftests/futex/include/atomic.h return __sync_val_compare_and_swap(&addr->val, oldval, newval); val 50 tools/testing/selftests/futex/include/atomic.h return __sync_add_and_fetch(&addr->val, 1); val 62 tools/testing/selftests/futex/include/atomic.h return __sync_sub_and_fetch(&addr->val, 1); val 75 tools/testing/selftests/futex/include/atomic.h addr->val = newval; val 70 tools/testing/selftests/futex/include/futextest.h #define futex(uaddr, op, val, timeout, uaddr2, val3, opflags) \ val 71 tools/testing/selftests/futex/include/futextest.h syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3) val 78 tools/testing/selftests/futex/include/futextest.h futex_wait(futex_t *uaddr, futex_t val, struct timespec *timeout, int opflags) val 80 tools/testing/selftests/futex/include/futextest.h return futex(uaddr, FUTEX_WAIT, val, timeout, NULL, 0, opflags); val 98 tools/testing/selftests/futex/include/futextest.h futex_wait_bitset(futex_t *uaddr, futex_t val, struct timespec *timeout, val 101 tools/testing/selftests/futex/include/futextest.h return futex(uaddr, FUTEX_WAIT_BITSET, val, timeout, NULL, bitset, val 169 tools/testing/selftests/futex/include/futextest.h futex_cmp_requeue(futex_t *uaddr, futex_t val, futex_t *uaddr2, int nr_wake, val 173 tools/testing/selftests/futex/include/futextest.h val, opflags); val 185 tools/testing/selftests/futex/include/futextest.h futex_wait_requeue_pi(futex_t *uaddr, futex_t val, futex_t *uaddr2, val 188 tools/testing/selftests/futex/include/futextest.h return futex(uaddr, FUTEX_WAIT_REQUEUE_PI, val, timeout, uaddr2, 0, val 200 tools/testing/selftests/futex/include/futextest.h futex_cmp_requeue_pi(futex_t *uaddr, futex_t val, futex_t *uaddr2, int nr_wake, val 204 tools/testing/selftests/futex/include/futextest.h val, opflags); val 47 tools/testing/selftests/kvm/include/aarch64/processor.h static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id, uint64_t val) val 51 tools/testing/selftests/kvm/include/aarch64/processor.h reg.addr = (uint64_t)&val; val 227 tools/testing/selftests/kvm/include/evmcs.h u64 val = (vp_assist_pa & HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK) | val 230 tools/testing/selftests/kvm/include/evmcs.h wrmsr(HV_X64_MSR_VP_ASSIST_PAGE, val); val 216 tools/testing/selftests/kvm/include/x86_64/processor.h static inline void set_cr4(uint64_t val) val 218 tools/testing/selftests/kvm/include/x86_64/processor.h __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); val 240 tools/testing/selftests/kvm/include/x86_64/processor.h static inline void set_xmm(int n, unsigned long val) val 244 tools/testing/selftests/kvm/include/x86_64/processor.h SET_XMM(val, xmm0); val 247 tools/testing/selftests/kvm/include/x86_64/processor.h SET_XMM(val, xmm1); val 250 tools/testing/selftests/kvm/include/x86_64/processor.h SET_XMM(val, xmm2); val 253 tools/testing/selftests/kvm/include/x86_64/processor.h SET_XMM(val, xmm3); val 256 tools/testing/selftests/kvm/include/x86_64/processor.h SET_XMM(val, xmm4); val 259 tools/testing/selftests/kvm/include/x86_64/processor.h SET_XMM(val, xmm5); val 262 tools/testing/selftests/kvm/include/x86_64/processor.h SET_XMM(val, xmm6); val 265 tools/testing/selftests/kvm/include/x86_64/processor.h SET_XMM(val, xmm7); val 1634 tools/testing/selftests/kvm/lib/kvm_util.c char val = 'N'; val 1648 tools/testing/selftests/kvm/lib/kvm_util.c count = fread(&val, sizeof(char), 1, f); val 1653 tools/testing/selftests/kvm/lib/kvm_util.c return val == 'Y'; val 122 tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c static void report(int64_t val) val 125 tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c val, val / TSC_ADJUST_VALUE, val % TSC_ADJUST_VALUE); val 109 tools/testing/selftests/mqueue/mq_perf_tests.c .val = 'c', val 130 tools/testing/selftests/mqueue/mq_perf_tests.c .val = 0, val 144 tools/testing/selftests/mqueue/mq_perf_tests.c .val = 'p', val 129 tools/testing/selftests/net/ipv6_flowlabel.c char val; val 135 tools/testing/selftests/net/ipv6_flowlabel.c ret = read(fd, &val, 1); val 144 tools/testing/selftests/net/ipv6_flowlabel.c return val == '1'; val 136 tools/testing/selftests/net/msg_zerocopy.c static void do_setsockopt(int fd, int level, int optname, int val) val 138 tools/testing/selftests/net/msg_zerocopy.c if (setsockopt(fd, level, optname, &val, sizeof(val))) val 139 tools/testing/selftests/net/msg_zerocopy.c error(1, errno, "setsockopt %d.%d: %d", level, optname, val); val 1253 tools/testing/selftests/net/nettest.c int val = 0, sz = sizeof(val); val 1271 tools/testing/selftests/net/nettest.c if (getsockopt(sd, SOL_SOCKET, SO_ERROR, &val, (socklen_t *)&sz) < 0) { val 1276 tools/testing/selftests/net/nettest.c if (val != 0) { val 1277 tools/testing/selftests/net/nettest.c log_error("connect failed: %d: %s\n", val, strerror(val)); val 64 tools/testing/selftests/net/psock_fanout.c int fd, val; val 86 tools/testing/selftests/net/psock_fanout.c val = (((int) typeflags) << 16) | group_id; val 87 tools/testing/selftests/net/psock_fanout.c if (setsockopt(fd, SOL_PACKET, PACKET_FANOUT, &val, sizeof(val))) { val 185 tools/testing/selftests/net/psock_fanout.c int val = TPACKET_V2; val 187 tools/testing/selftests/net/psock_fanout.c if (setsockopt(fd, SOL_PACKET, PACKET_VERSION, (void *) &val, val 188 tools/testing/selftests/net/psock_fanout.c sizeof(val))) { val 417 tools/testing/selftests/net/reuseport_bpf.c int val, size; val 424 tools/testing/selftests/net/reuseport_bpf.c val = atoi(buf); val 427 tools/testing/selftests/net/reuseport_bpf.c if ((val & rw_mask) != rw_mask) { val 432 tools/testing/selftests/net/reuseport_bpf.c val |= rw_mask; val 433 tools/testing/selftests/net/reuseport_bpf.c size = snprintf(buf, 16, "%d", val); val 306 tools/testing/selftests/net/udpgso.c int val; val 308 tools/testing/selftests/net/udpgso.c val = get_device_mtu(fd, cfg_ifname); val 309 tools/testing/selftests/net/udpgso.c fprintf(stderr, "device mtu (orig): %u\n", val); val 312 tools/testing/selftests/net/udpgso.c val = get_device_mtu(fd, cfg_ifname); val 313 tools/testing/selftests/net/udpgso.c if (val != mtu) val 314 tools/testing/selftests/net/udpgso.c error(1, 0, "unable to set device mtu to %u\n", val); val 316 tools/testing/selftests/net/udpgso.c fprintf(stderr, "device mtu (test): %u\n", val); val 321 tools/testing/selftests/net/udpgso.c int level, name, val; val 326 tools/testing/selftests/net/udpgso.c val = IP_PMTUDISC_DO; val 330 tools/testing/selftests/net/udpgso.c val = IPV6_PMTUDISC_DO; val 333 tools/testing/selftests/net/udpgso.c if (setsockopt(fd, level, name, &val, sizeof(val))) val 508 tools/testing/selftests/net/udpgso.c int i, ret, val, mss; val 516 tools/testing/selftests/net/udpgso.c val = test->gso_len; val 518 tools/testing/selftests/net/udpgso.c if (setsockopt(fdt, SOL_UDP, UDP_SEGMENT, &val, sizeof(val))) val 574 tools/testing/selftests/net/udpgso.c int fdr, fdt, val; val 606 tools/testing/selftests/net/udpgso.c val = get_path_mtu(fdt, addr->sa_family == AF_INET); val 607 tools/testing/selftests/net/udpgso.c if (val != CONST_MTU_TEST) val 608 tools/testing/selftests/net/udpgso.c error(1, 0, "bad path mtu %u\n", val); val 125 tools/testing/selftests/net/udpgso_bench_rx.c int fd, val; val 131 tools/testing/selftests/net/udpgso_bench_rx.c val = 1 << 21; val 132 tools/testing/selftests/net/udpgso_bench_rx.c if (setsockopt(fd, SOL_SOCKET, SO_RCVBUF, &val, sizeof(val))) val 134 tools/testing/selftests/net/udpgso_bench_rx.c val = 1; val 135 tools/testing/selftests/net/udpgso_bench_rx.c if (setsockopt(fd, SOL_SOCKET, SO_REUSEPORT, &val, sizeof(val))) val 184 tools/testing/selftests/net/udpgso_bench_rx.c static char sanitized_char(char val) val 186 tools/testing/selftests/net/udpgso_bench_rx.c return (val >= 'a' && val <= 'z') ? val : '.'; val 357 tools/testing/selftests/net/udpgso_bench_rx.c int val = 1; val 358 tools/testing/selftests/net/udpgso_bench_rx.c if (setsockopt(fd, IPPROTO_UDP, UDP_GRO, &val, sizeof(val))) val 524 tools/testing/selftests/net/udpgso_bench_tx.c int level, name, val; val 529 tools/testing/selftests/net/udpgso_bench_tx.c val = IP_PMTUDISC_DO; val 533 tools/testing/selftests/net/udpgso_bench_tx.c val = IPV6_PMTUDISC_DO; val 536 tools/testing/selftests/net/udpgso_bench_tx.c if (setsockopt(fd, level, name, &val, sizeof(val))) val 542 tools/testing/selftests/net/udpgso_bench_tx.c int val = SOF_TIMESTAMPING_OPT_CMSG | SOF_TIMESTAMPING_OPT_ID | val 546 tools/testing/selftests/net/udpgso_bench_tx.c val |= SOF_TIMESTAMPING_SOFTWARE; val 548 tools/testing/selftests/net/udpgso_bench_tx.c val |= SOF_TIMESTAMPING_RAW_HARDWARE; val 550 tools/testing/selftests/net/udpgso_bench_tx.c if (setsockopt(fd, SOL_SOCKET, SO_TIMESTAMPING, &val, sizeof(val))) val 613 tools/testing/selftests/net/udpgso_bench_tx.c int fd, i, val, ret; val 632 tools/testing/selftests/net/udpgso_bench_tx.c val = 1; val 635 tools/testing/selftests/net/udpgso_bench_tx.c &val, sizeof(val)); val 313 tools/testing/selftests/networking/timestamping/timestamping.c int val; val 432 tools/testing/selftests/networking/timestamping/timestamping.c len = sizeof(val); val 433 tools/testing/selftests/networking/timestamping/timestamping.c if (getsockopt(sock, SOL_SOCKET, SO_TIMESTAMP, &val, &len) < 0) val 436 tools/testing/selftests/networking/timestamping/timestamping.c printf("SO_TIMESTAMP %d\n", val); val 438 tools/testing/selftests/networking/timestamping/timestamping.c if (getsockopt(sock, SOL_SOCKET, SO_TIMESTAMPNS, &val, &len) < 0) val 442 tools/testing/selftests/networking/timestamping/timestamping.c printf("SO_TIMESTAMPNS %d\n", val); val 444 tools/testing/selftests/networking/timestamping/timestamping.c if (getsockopt(sock, SOL_SOCKET, SO_TIMESTAMPING, &val, &len) < 0) { val 448 tools/testing/selftests/networking/timestamping/timestamping.c printf("SO_TIMESTAMPING %d\n", val); val 449 tools/testing/selftests/networking/timestamping/timestamping.c if (val != so_timestamping_flags) val 394 tools/testing/selftests/networking/timestamping/txtimestamp.c int fd, i, val = 1, total_len; val 426 tools/testing/selftests/networking/timestamping/txtimestamp.c (char*) &val, sizeof(val))) val 441 tools/testing/selftests/networking/timestamping/txtimestamp.c &val, sizeof(val))) val 445 tools/testing/selftests/networking/timestamping/txtimestamp.c &val, sizeof(val))) val 523 tools/testing/selftests/networking/timestamping/txtimestamp.c val = sendmsg(fd, &msg, 0); val 524 tools/testing/selftests/networking/timestamping/txtimestamp.c if (val != total_len) val 263 tools/testing/selftests/powerpc/benchmarks/context_switch.c static unsigned long xchg(unsigned long *p, unsigned long val) val 265 tools/testing/selftests/powerpc/benchmarks/context_switch.c return __atomic_exchange_n(p, val, __ATOMIC_SEQ_CST); val 44 tools/testing/selftests/powerpc/benchmarks/null_syscall.c struct itimerval val; val 46 tools/testing/selftests/powerpc/benchmarks/null_syscall.c memset(&val, 0, sizeof(val)); val 47 tools/testing/selftests/powerpc/benchmarks/null_syscall.c val.it_value.tv_usec = usecs; val 50 tools/testing/selftests/powerpc/benchmarks/null_syscall.c setitimer(ITIMER_REAL, &val, NULL); val 31 tools/testing/selftests/powerpc/cache_shape/cache_shape.c static void print_size(const char *label, uint32_t val) val 33 tools/testing/selftests/powerpc/cache_shape/cache_shape.c printf("%s cache size: %#10x %10dB %10dK\n", label, val, val, val / 1024); val 36 tools/testing/selftests/powerpc/cache_shape/cache_shape.c static void print_geo(const char *label, uint32_t val) val 40 tools/testing/selftests/powerpc/cache_shape/cache_shape.c printf("%s line size: %#10x ", label, val & 0xFFFF); val 42 tools/testing/selftests/powerpc/cache_shape/cache_shape.c assoc = val >> 16; val 51 tools/testing/selftests/powerpc/dscr/dscr.h inline void set_dscr(unsigned long val) val 53 tools/testing/selftests/powerpc/dscr/dscr.h asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR_PRIV)); val 66 tools/testing/selftests/powerpc/dscr/dscr.h inline void set_dscr_usr(unsigned long val) val 68 tools/testing/selftests/powerpc/dscr/dscr.h asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR)); val 76 tools/testing/selftests/powerpc/dscr/dscr.h unsigned long val; val 92 tools/testing/selftests/powerpc/dscr/dscr.h sscanf(buf, "%lx", &val); val 94 tools/testing/selftests/powerpc/dscr/dscr.h return val; val 97 tools/testing/selftests/powerpc/dscr/dscr.h void set_default_dscr(unsigned long val) val 109 tools/testing/selftests/powerpc/dscr/dscr.h sprintf(buf, "%lx\n", val); val 13 tools/testing/selftests/powerpc/dscr/dscr_sysfs_test.c static int check_cpu_dscr_default(char *file, unsigned long val) val 32 tools/testing/selftests/powerpc/dscr/dscr_sysfs_test.c if (strtol(buf, NULL, 16) != val) { val 34 tools/testing/selftests/powerpc/dscr/dscr_sysfs_test.c val, strtol(buf, NULL, 16)); val 40 tools/testing/selftests/powerpc/dscr/dscr_sysfs_test.c static int check_all_cpu_dscr_defaults(unsigned long val) val 68 tools/testing/selftests/powerpc/dscr/dscr_sysfs_test.c if (check_cpu_dscr_default(file, val)) val 15 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c static int test_thread_dscr(unsigned long val) val 22 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c if (val != cur_dscr) { val 24 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c sched_getcpu(), val, cur_dscr); val 28 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c if (val != cur_dscr_usr) { val 30 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c sched_getcpu(), val, cur_dscr_usr); val 36 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c static int check_cpu_dscr_thread(unsigned long val) val 47 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c if (test_thread_dscr(val)) val 37 tools/testing/selftests/powerpc/include/utils.h void set_dscr(unsigned long val); val 62 tools/testing/selftests/powerpc/mm/subpage_prot.c int val = 0x1234567; val 65 tools/testing/selftests/powerpc/mm/subpage_prot.c : : "r" (val), "r" (addr) : "memory"); val 29 tools/testing/selftests/powerpc/pmu/ebb/back_to_back_ebbs_test.c uint64_t siar, val; val 31 tools/testing/selftests/powerpc/pmu/ebb/back_to_back_ebbs_test.c val = mfspr(SPRN_BESCR); val 32 tools/testing/selftests/powerpc/pmu/ebb/back_to_back_ebbs_test.c if (!(val & BESCR_PMEO)) { val 55 tools/testing/selftests/powerpc/pmu/ebb/back_to_back_ebbs_test.c val = mfspr(SPRN_PMC1); val 56 tools/testing/selftests/powerpc/pmu/ebb/back_to_back_ebbs_test.c trace_log_reg(ebb_state.trace, SPRN_PMC1, val); val 58 tools/testing/selftests/powerpc/pmu/ebb/back_to_back_ebbs_test.c val = mfspr(SPRN_MMCR0); val 59 tools/testing/selftests/powerpc/pmu/ebb/back_to_back_ebbs_test.c trace_log_reg(ebb_state.trace, SPRN_MMCR0, val); val 26 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c uint64_t mask, val; val 30 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c val = mfspr(SPRN_BESCR); val 31 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c if (!(val & BESCR_PMEO)) { val 39 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c val = mfspr(SPRN_MMCR0); val 40 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c trace_log_reg(ebb_state.trace, SPRN_MMCR0, val); val 56 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c uint64_t val; val 92 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c val = mfspr(SPRN_MMCR0); val 93 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c if (! (val & MMCR0_FC)) { val 94 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c printf("Outside of loop, FC NOT set MMCR0 0x%lx\n", val); val 25 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_mmcr2_test.c uint64_t val, expected[2], actual; val 62 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_mmcr2_test.c val = mfspr(SPRN_MMCR2); val 63 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_mmcr2_test.c if (val != expected[i % 2]) { val 65 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_mmcr2_test.c actual = val; val 35 tools/testing/selftests/powerpc/pmu/ebb/ebb.c u64 val; val 39 tools/testing/selftests/powerpc/pmu/ebb/ebb.c val = mfspr(SPRN_MMCR0); val 40 tools/testing/selftests/powerpc/pmu/ebb/ebb.c mtspr(SPRN_MMCR0, (val & ~mmcr0_clear_mask) | MMCR0_PMAE); val 59 tools/testing/selftests/powerpc/pmu/ebb/ebb.c u64 val; val 61 tools/testing/selftests/powerpc/pmu/ebb/ebb.c val = mfspr(SPRN_MMCR0); val 62 tools/testing/selftests/powerpc/pmu/ebb/ebb.c if ((val & (MMCR0_FC | MMCR0_PMAO)) == MMCR0_FC) { val 64 tools/testing/selftests/powerpc/pmu/ebb/ebb.c printf("Outside of loop, only FC set 0x%llx\n", val); val 102 tools/testing/selftests/powerpc/pmu/ebb/ebb.c u64 val; val 104 tools/testing/selftests/powerpc/pmu/ebb/ebb.c val = mfspr(SPRN_BESCR); val 105 tools/testing/selftests/powerpc/pmu/ebb/ebb.c if (!(val & BESCR_PMEO)) { val 113 tools/testing/selftests/powerpc/pmu/ebb/ebb.c val = mfspr(SPRN_MMCR0); val 114 tools/testing/selftests/powerpc/pmu/ebb/ebb.c trace_log_reg(ebb_state.trace, SPRN_MMCR0, val); val 255 tools/testing/selftests/powerpc/pmu/ebb/ebb.c u64 val; val 260 tools/testing/selftests/powerpc/pmu/ebb/ebb.c val = read_pmc(pmc); val 261 tools/testing/selftests/powerpc/pmu/ebb/ebb.c if (val < start_value) val 264 tools/testing/selftests/powerpc/pmu/ebb/ebb.c ebb_state.stats.pmc_count[PMC_INDEX(pmc)] += val - start_value; val 266 tools/testing/selftests/powerpc/pmu/ebb/ebb.c trace_log_reg(ebb_state.trace, SPRN_PMC1 + pmc - 1, val); val 272 tools/testing/selftests/powerpc/pmu/ebb/ebb.c return val >= COUNTER_OVERFLOW; val 352 tools/testing/selftests/powerpc/pmu/ebb/ebb.c uint64_t val; val 391 tools/testing/selftests/powerpc/pmu/ebb/ebb.c val = mfspr(SPRN_MMCRA); val 392 tools/testing/selftests/powerpc/pmu/ebb/ebb.c val |= mfspr(SPRN_MMCR2); val 393 tools/testing/selftests/powerpc/pmu/ebb/ebb.c val |= mfspr(SPRN_MMCR0); val 92 tools/testing/selftests/powerpc/pmu/ebb/instruction_count_test.c uint64_t val; val 94 tools/testing/selftests/powerpc/pmu/ebb/instruction_count_test.c val = mfspr(SPRN_BESCR); val 95 tools/testing/selftests/powerpc/pmu/ebb/instruction_count_test.c if (!(val & BESCR_PMEO)) { val 19 tools/testing/selftests/powerpc/pmu/ebb/no_handler_test.c u64 val; val 34 tools/testing/selftests/powerpc/pmu/ebb/no_handler_test.c val = mfspr(SPRN_EBBHR); val 35 tools/testing/selftests/powerpc/pmu/ebb/no_handler_test.c FAIL_IF(val != 0); val 48 tools/testing/selftests/powerpc/pmu/ebb/no_handler_test.c val = mfspr(SPRN_MMCR0); val 49 tools/testing/selftests/powerpc/pmu/ebb/no_handler_test.c FAIL_IF(val != 0x0000000080000080); val 33 tools/testing/selftests/powerpc/pmu/ebb/pmae_handling_test.c uint64_t val; val 35 tools/testing/selftests/powerpc/pmu/ebb/pmae_handling_test.c val = mfspr(SPRN_BESCR); val 36 tools/testing/selftests/powerpc/pmu/ebb/pmae_handling_test.c if (!(val & BESCR_PMEO)) { val 21 tools/testing/selftests/powerpc/pmu/ebb/pmc56_overflow_test.c uint64_t val; val 23 tools/testing/selftests/powerpc/pmu/ebb/pmc56_overflow_test.c val = mfspr(SPRN_BESCR); val 24 tools/testing/selftests/powerpc/pmu/ebb/pmc56_overflow_test.c if (!(val & BESCR_PMEO)) { val 32 tools/testing/selftests/powerpc/pmu/ebb/pmc56_overflow_test.c val = mfspr(SPRN_PMC5); val 33 tools/testing/selftests/powerpc/pmu/ebb/pmc56_overflow_test.c if (val >= COUNTER_OVERFLOW) val 38 tools/testing/selftests/powerpc/pmu/ebb/pmc56_overflow_test.c val = mfspr(SPRN_PMC6); val 39 tools/testing/selftests/powerpc/pmu/ebb/pmc56_overflow_test.c if (val >= COUNTER_OVERFLOW) val 18 tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c uint64_t val, expected; val 24 tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c val = mfspr(SPRN_BESCR); val 26 tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c FAIL_IF(val != expected); val 30 tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c val = mfspr(SPRN_EBBHR); val 32 tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c FAIL_IF(val != expected); val 39 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ val 46 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h FTR_ENTRY_LONG val; \ val 61 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define END_FTR_SECTION_NESTED(msk, val, label) \ val 63 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) val 65 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define END_FTR_SECTION(msk, val) \ val 66 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h END_FTR_SECTION_NESTED(msk, val, 97) val 76 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define ALT_FTR_SECTION_END_NESTED(msk, val, label) \ val 77 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) val 82 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define ALT_FTR_SECTION_END(msk, val) \ val 83 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h ALT_FTR_SECTION_END_NESTED(msk, val, 97) val 93 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define END_MMU_FTR_SECTION_NESTED(msk, val, label) \ val 95 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup) val 97 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define END_MMU_FTR_SECTION(msk, val) \ val 98 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h END_MMU_FTR_SECTION_NESTED(msk, val, 97) val 109 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define ALT_MMU_FTR_SECTION_END_NESTED(msk, val, label) \ val 110 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup) val 115 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define ALT_MMU_FTR_SECTION_END(msk, val) \ val 116 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h ALT_MMU_FTR_SECTION_END_NESTED(msk, val, 97) val 126 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define END_FW_FTR_SECTION_NESTED(msk, val, label) \ val 128 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup) val 130 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define END_FW_FTR_SECTION(msk, val) \ val 131 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h END_FW_FTR_SECTION_NESTED(msk, val, 97) val 139 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label) \ val 140 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup) val 145 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define ALT_FW_FTR_SECTION_END(msk, val) \ val 146 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97) val 154 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define ASM_FTR_IF(section_if, section_else, msk, val) \ val 159 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h stringify_in_c(ALT_FTR_SECTION_END((msk), (val))) val 167 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h #define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \ val 172 tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h stringify_in_c(ALT_MMU_FTR_SECTION_END((msk), (val))) val 21 tools/testing/selftests/powerpc/primitives/word-at-a-time.h static inline long prep_zero_mask(unsigned long val, unsigned long rhs, const struct word_at_a_time *c) val 23 tools/testing/selftests/powerpc/primitives/word-at-a-time.h unsigned long mask = (val & c->low_bits) + c->low_bits; val 37 tools/testing/selftests/powerpc/primitives/word-at-a-time.h static inline bool has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) val 39 tools/testing/selftests/powerpc/primitives/word-at-a-time.h unsigned long rhs = val | c->low_bits; val 41 tools/testing/selftests/powerpc/primitives/word-at-a-time.h return (val + c->high_bits) & ~rhs; val 21 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h int validate_gpr(unsigned long *gpr, unsigned long val) val 26 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h if (gpr[i] != val) { val 28 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h i+14, gpr[i], val); val 39 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h int validate_fpr(unsigned long *fpr, unsigned long val) val 44 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h if (fpr[i] != val) { val 45 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h printf("FPR[%d]: %lx Expected: %lx\n", i, fpr[i], val); val 56 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h int validate_fpr_float(float *fpr, float val) val 61 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h if (fpr[i] != val) { val 62 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h printf("FPR[%d]: %f Expected: %f\n", i, fpr[i], val); val 340 tools/testing/selftests/powerpc/ptrace/ptrace.h int write_fpr(pid_t child, unsigned long val) val 353 tools/testing/selftests/powerpc/ptrace/ptrace.h regs->fpr[i] = val; val 387 tools/testing/selftests/powerpc/ptrace/ptrace.h int write_ckpt_fpr(pid_t child, unsigned long val) val 404 tools/testing/selftests/powerpc/ptrace/ptrace.h regs->fpr[i] = val; val 440 tools/testing/selftests/powerpc/ptrace/ptrace.h int write_gpr(pid_t child, unsigned long val) val 458 tools/testing/selftests/powerpc/ptrace/ptrace.h regs->gpr[i] = val; val 497 tools/testing/selftests/powerpc/ptrace/ptrace.h int write_ckpt_gpr(pid_t child, unsigned long val) val 518 tools/testing/selftests/powerpc/ptrace/ptrace.h regs->gpr[i] = val; val 32 tools/testing/selftests/powerpc/stringloops/asm/ppc_asm.h #define END_FTR_SECTION_IFSET(val) val 260 tools/testing/selftests/powerpc/utils.c void set_dscr(unsigned long val) val 274 tools/testing/selftests/powerpc/utils.c asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR)); val 381 tools/testing/selftests/powerpc/vphn/test-vphn.c u32 val = be32_to_cpu(output[i]); val 382 tools/testing/selftests/powerpc/vphn/test-vphn.c if (val != test->expected[i]) { val 383 tools/testing/selftests/powerpc/vphn/test-vphn.c printf("element #%d is 0x%x, should be 0x%x\n", i, val, val 33 tools/testing/selftests/proc/proc.h unsigned long long val; val 36 tools/testing/selftests/proc/proc.h val = strtoull(p, end, 10); val 38 tools/testing/selftests/proc/proc.h return val; val 39 tools/testing/selftests/rcutorture/formal/srcu-cbmc/src/barriers.h #define WRITE_ONCE(x) ((*(volatile typeof(x) *) &(x)) = (val)) val 191 tools/testing/selftests/seccomp/seccomp_bpf.c __s64 val; val 1615 tools/testing/selftests/seccomp/seccomp_bpf.c # define EXPECT_SYSCALL_RETURN(val, action) EXPECT_EQ(-1, action) val 1617 tools/testing/selftests/seccomp/seccomp_bpf.c # define EXPECT_SYSCALL_RETURN(val, action) \ val 1620 tools/testing/selftests/seccomp/seccomp_bpf.c if (val < 0) { \ val 1622 tools/testing/selftests/seccomp/seccomp_bpf.c EXPECT_EQ(-(val), errno); \ val 1624 tools/testing/selftests/seccomp/seccomp_bpf.c EXPECT_EQ(val, action); \ val 3173 tools/testing/selftests/seccomp/seccomp_bpf.c resp.val = USER_NOTIF_MAGIC; val 3295 tools/testing/selftests/seccomp/seccomp_bpf.c resp.val = 0; val 3305 tools/testing/selftests/seccomp/seccomp_bpf.c resp.val = 0; val 3374 tools/testing/selftests/seccomp/seccomp_bpf.c resp.val = USER_NOTIF_MAGIC; val 3438 tools/testing/selftests/seccomp/seccomp_bpf.c resp.val = USER_NOTIF_MAGIC; val 3484 tools/testing/selftests/seccomp/seccomp_bpf.c resp.val = USER_NOTIF_MAGIC; val 37 tools/testing/selftests/timers/adjtick.c long long llabs(long long val) val 39 tools/testing/selftests/timers/adjtick.c if (val < 0) val 40 tools/testing/selftests/timers/adjtick.c val = -val; val 41 tools/testing/selftests/timers/adjtick.c return val; val 81 tools/testing/selftests/timers/posix_timers.c struct itimerval val = { val 111 tools/testing/selftests/timers/posix_timers.c err = setitimer(which, &val, NULL); val 143 tools/testing/selftests/timers/posix_timers.c struct itimerspec val = { val 169 tools/testing/selftests/timers/posix_timers.c err = timer_settime(id, 0, &val, NULL); val 39 tools/testing/selftests/timers/raw_skew.c long long llabs(long long val) val 41 tools/testing/selftests/timers/raw_skew.c if (val < 0) val 42 tools/testing/selftests/timers/raw_skew.c val = -val; val 43 tools/testing/selftests/timers/raw_skew.c return val; val 115 tools/testing/selftests/vm/thuge-gen.c unsigned long val = 0; val 128 tools/testing/selftests/vm/thuge-gen.c sscanf(line, "%lu", &val); val 132 tools/testing/selftests/vm/thuge-gen.c return val; val 53 tools/testing/vsock/control.c int val = 1; val 69 tools/testing/vsock/control.c &val, sizeof(val)) < 0) { val 556 tools/testing/vsock/vsock_diag_test.c .val = 'H', val 561 tools/testing/vsock/vsock_diag_test.c .val = 'P', val 566 tools/testing/vsock/vsock_diag_test.c .val = 'm', val 571 tools/testing/vsock/vsock_diag_test.c .val = 'p', val 576 tools/testing/vsock/vsock_diag_test.c .val = '?', val 32 tools/thermal/tmon/sysfs.c int sysfs_set_ulong(char *path, char *filename, unsigned long val) val 45 tools/thermal/tmon/sysfs.c ret = fprintf(fd, "%lu", val); val 510 tools/thermal/tmon/sysfs.c unsigned long val; val 515 tools/thermal/tmon/sysfs.c val = ptdata.cdi[i].cur_state; val 516 tools/thermal/tmon/sysfs.c if (val > 1000000) val 517 tools/thermal/tmon/sysfs.c val = 0; val 519 tools/thermal/tmon/sysfs.c fprintf(tmon_log, "%lu ", val); val 165 tools/thermal/tmon/tmon.h extern int sysfs_set_ulong(char *path, char *filename, unsigned long val); val 409 tools/thermal/tmon/tui.c int val; val 416 tools/thermal/tmon/tui.c val = atoi(buf); val 419 tools/thermal/tmon/tui.c snprintf(buf, 31, "Invalid Temp %d! %d-%d", val, val 421 tools/thermal/tmon/tui.c if (val < MIN_CTRL_TEMP || val > MAX_CTRL_TEMP) val 424 tools/thermal/tmon/tui.c p_param.t_target = val; val 425 tools/thermal/tmon/tui.c snprintf(buf, 31, "Set New Target Temp %d", val); val 431 tools/thermal/tmon/tui.c sysfs_set_ulong(path, "cur_state", val); val 352 tools/usb/testusb.c unsigned long val; val 356 tools/usb/testusb.c val = strtoul(str, &end, 0); val 357 tools/usb/testusb.c if (errno || *end || val > UINT_MAX) val 359 tools/usb/testusb.c *num = val; val 212 tools/usb/usbip/src/usbip_network.c const int val = 1; val 215 tools/usb/usbip/src/usbip_network.c ret = setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val)); val 224 tools/usb/usbip/src/usbip_network.c const int val = 1; val 227 tools/usb/usbip/src/usbip_network.c ret = setsockopt(sockfd, IPPROTO_TCP, TCP_NODELAY, &val, sizeof(val)); val 236 tools/usb/usbip/src/usbip_network.c const int val = 1; val 239 tools/usb/usbip/src/usbip_network.c ret = setsockopt(sockfd, SOL_SOCKET, SO_KEEPALIVE, &val, sizeof(val)); val 248 tools/usb/usbip/src/usbip_network.c const int val = 1; val 251 tools/usb/usbip/src/usbip_network.c ret = setsockopt(sockfd, IPPROTO_IPV6, IPV6_V6ONLY, &val, sizeof(val)); val 5 tools/virtio/linux/compiler.h #define WRITE_ONCE(var, val) \ val 6 tools/virtio/linux/compiler.h (*((volatile typeof(val) *)(&(var))) = (val)) val 64 tools/virtio/linux/virtio_config.h static inline u16 virtio16_to_cpu(struct virtio_device *vdev, __virtio16 val) val 66 tools/virtio/linux/virtio_config.h return __virtio16_to_cpu(virtio_is_little_endian(vdev), val); val 69 tools/virtio/linux/virtio_config.h static inline __virtio16 cpu_to_virtio16(struct virtio_device *vdev, u16 val) val 71 tools/virtio/linux/virtio_config.h return __cpu_to_virtio16(virtio_is_little_endian(vdev), val); val 74 tools/virtio/linux/virtio_config.h static inline u32 virtio32_to_cpu(struct virtio_device *vdev, __virtio32 val) val 76 tools/virtio/linux/virtio_config.h return __virtio32_to_cpu(virtio_is_little_endian(vdev), val); val 79 tools/virtio/linux/virtio_config.h static inline __virtio32 cpu_to_virtio32(struct virtio_device *vdev, u32 val) val 81 tools/virtio/linux/virtio_config.h return __cpu_to_virtio32(virtio_is_little_endian(vdev), val); val 84 tools/virtio/linux/virtio_config.h static inline u64 virtio64_to_cpu(struct virtio_device *vdev, __virtio64 val) val 86 tools/virtio/linux/virtio_config.h return __virtio64_to_cpu(virtio_is_little_endian(vdev), val); val 89 tools/virtio/linux/virtio_config.h static inline __virtio64 cpu_to_virtio64(struct virtio_device *vdev, u64 val) val 91 tools/virtio/linux/virtio_config.h return __cpu_to_virtio64(virtio_is_little_endian(vdev), val); val 218 tools/virtio/ringtest/main.c .val = 'h', val 223 tools/virtio/ringtest/main.c .val = 'H', val 228 tools/virtio/ringtest/main.c .val = 'G', val 233 tools/virtio/ringtest/main.c .val = 'R', val 238 tools/virtio/ringtest/main.c .val = 'C', val 243 tools/virtio/ringtest/main.c .val = 'o', val 248 tools/virtio/ringtest/main.c .val = 'b', val 253 tools/virtio/ringtest/main.c .val = 'p', val 258 tools/virtio/ringtest/main.c .val = 's', val 263 tools/virtio/ringtest/main.c .val = 'x', val 268 tools/virtio/ringtest/main.c .val = 'e', val 186 tools/virtio/ringtest/main.h #define WRITE_ONCE(x, val) \ val 189 tools/virtio/ringtest/main.h { .__val = (typeof(x)) (val) }; \ val 146 tools/virtio/virtio_test.c unsigned long long val; val 150 tools/virtio/virtio_test.c read(dev->fds[i].fd, &val, sizeof val); val 213 tools/virtio/virtio_test.c .val = 'h', val 217 tools/virtio/virtio_test.c .val = 'E', val 221 tools/virtio/virtio_test.c .val = 'e', val 225 tools/virtio/virtio_test.c .val = 'I', val 229 tools/virtio/virtio_test.c .val = 'i', val 233 tools/virtio/virtio_test.c .val = '1', val 237 tools/virtio/virtio_test.c .val = '0', val 241 tools/virtio/virtio_test.c .val = 'D', val 245 tools/virtio/virtio_test.c .val = 'd', val 306 tools/vm/page-types.c static unsigned long pagemap_pfn(uint64_t val) val 310 tools/vm/page-types.c if (val & PM_PRESENT) val 311 tools/vm/page-types.c pfn = PM_PFRAME(val); val 318 tools/vm/page-types.c static unsigned long pagemap_swap_offset(uint64_t val) val 320 tools/vm/page-types.c return val & PM_SWAP ? PM_SWAP_OFFSET(val) : 0; val 49 virt/kvm/arm/arch_timer.c u64 val); val 803 virt/kvm/arm/arch_timer.c u64 val; val 807 virt/kvm/arm/arch_timer.c val = timer->cnt_cval - kvm_phys_timer_read() + timer->cntvoff; val 808 virt/kvm/arm/arch_timer.c val &= lower_32_bits(val); val 812 virt/kvm/arm/arch_timer.c val = read_timer_ctl(timer); val 816 virt/kvm/arm/arch_timer.c val = timer->cnt_cval; val 820 virt/kvm/arm/arch_timer.c val = kvm_phys_timer_read() - timer->cntvoff; val 827 virt/kvm/arm/arch_timer.c return val; val 834 virt/kvm/arm/arch_timer.c u64 val; val 839 virt/kvm/arm/arch_timer.c val = kvm_arm_timer_read(vcpu, vcpu_get_timer(vcpu, tmr), treg); val 844 virt/kvm/arm/arch_timer.c return val; val 850 virt/kvm/arm/arch_timer.c u64 val) val 854 virt/kvm/arm/arch_timer.c timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + (s32)val; val 858 virt/kvm/arm/arch_timer.c timer->cnt_ctl = val & ~ARCH_TIMER_CTRL_IT_STAT; val 862 virt/kvm/arm/arch_timer.c timer->cnt_cval = val; val 873 virt/kvm/arm/arch_timer.c u64 val) val 878 virt/kvm/arm/arch_timer.c kvm_arm_timer_write(vcpu, vcpu_get_timer(vcpu, tmr), treg, val); val 1094 virt/kvm/arm/arch_timer.c u64 val; val 1100 virt/kvm/arm/arch_timer.c val = read_sysreg(cnthctl_el2); val 1101 virt/kvm/arm/arch_timer.c val |= (CNTHCTL_EL1PCEN << cnthctl_shift); val 1102 virt/kvm/arm/arch_timer.c val |= (CNTHCTL_EL1PCTEN << cnthctl_shift); val 1103 virt/kvm/arm/arch_timer.c write_sysreg(val, cnthctl_el2); val 25 virt/kvm/arm/hyp/timer-sr.c u64 val; val 28 virt/kvm/arm/hyp/timer-sr.c val = read_sysreg(cnthctl_el2); val 29 virt/kvm/arm/hyp/timer-sr.c val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN; val 30 virt/kvm/arm/hyp/timer-sr.c write_sysreg(val, cnthctl_el2); val 39 virt/kvm/arm/hyp/timer-sr.c u64 val; val 45 virt/kvm/arm/hyp/timer-sr.c val = read_sysreg(cnthctl_el2); val 46 virt/kvm/arm/hyp/timer-sr.c val &= ~CNTHCTL_EL1PCEN; val 47 virt/kvm/arm/hyp/timer-sr.c val |= CNTHCTL_EL1PCTEN; val 48 virt/kvm/arm/hyp/timer-sr.c write_sysreg(val, cnthctl_el2); val 59 virt/kvm/arm/hyp/vgic-v3-sr.c static void __hyp_text __gic_v3_set_lr(u64 val, int lr) val 63 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR0_EL2); val 66 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR1_EL2); val 69 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR2_EL2); val 72 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR3_EL2); val 75 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR4_EL2); val 78 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR5_EL2); val 81 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR6_EL2); val 84 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR7_EL2); val 87 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR8_EL2); val 90 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR9_EL2); val 93 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR10_EL2); val 96 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR11_EL2); val 99 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR12_EL2); val 102 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR13_EL2); val 105 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR14_EL2); val 108 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_LR15_EL2); val 113 virt/kvm/arm/hyp/vgic-v3-sr.c static void __hyp_text __vgic_v3_write_ap0rn(u32 val, int n) val 117 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_AP0R0_EL2); val 120 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_AP0R1_EL2); val 123 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_AP0R2_EL2); val 126 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_AP0R3_EL2); val 131 virt/kvm/arm/hyp/vgic-v3-sr.c static void __hyp_text __vgic_v3_write_ap1rn(u32 val, int n) val 135 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_AP1R0_EL2); val 138 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_AP1R1_EL2); val 141 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_AP1R2_EL2); val 144 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val, ICH_AP1R3_EL2); val 151 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val; val 155 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_AP0R0_EL2); val 158 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_AP0R1_EL2); val 161 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_AP0R2_EL2); val 164 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_AP0R3_EL2); val 170 virt/kvm/arm/hyp/vgic-v3-sr.c return val; val 175 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val; val 179 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_AP1R0_EL2); val 182 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_AP1R1_EL2); val 185 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_AP1R2_EL2); val 188 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_AP1R3_EL2); val 194 virt/kvm/arm/hyp/vgic-v3-sr.c return val; val 312 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val; val 318 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICC_SRE_EL2); val 319 virt/kvm/arm/hyp/vgic-v3-sr.c write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); val 339 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val; val 345 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_VTR_EL2); val 346 virt/kvm/arm/hyp/vgic-v3-sr.c nr_pre_bits = vtr_to_nr_pre_bits(val); val 376 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val; val 382 virt/kvm/arm/hyp/vgic-v3-sr.c val = read_gicreg(ICH_VTR_EL2); val 383 virt/kvm/arm/hyp/vgic-v3-sr.c nr_pre_bits = vtr_to_nr_pre_bits(val); val 461 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val = __gic_v3_get_lr(i); val 462 virt/kvm/arm/hyp/vgic-v3-sr.c u8 lr_prio = (val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT; val 465 virt/kvm/arm/hyp/vgic-v3-sr.c if ((val & ICH_LR_STATE) != ICH_LR_PENDING_BIT) val 469 virt/kvm/arm/hyp/vgic-v3-sr.c if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK)) val 473 virt/kvm/arm/hyp/vgic-v3-sr.c if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK)) val 482 virt/kvm/arm/hyp/vgic-v3-sr.c *lr_val = val; val 499 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val = __gic_v3_get_lr(i); val 501 virt/kvm/arm/hyp/vgic-v3-sr.c if ((val & ICH_LR_VIRTUAL_ID_MASK) == intid && val 502 virt/kvm/arm/hyp/vgic-v3-sr.c (val & ICH_LR_ACTIVE_BIT)) { val 503 virt/kvm/arm/hyp/vgic-v3-sr.c *lr_val = val; val 519 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val; val 531 virt/kvm/arm/hyp/vgic-v3-sr.c val = __vgic_v3_read_ap0rn(i); val 532 virt/kvm/arm/hyp/vgic-v3-sr.c val |= __vgic_v3_read_ap1rn(i); val 533 virt/kvm/arm/hyp/vgic-v3-sr.c if (!val) { val 538 virt/kvm/arm/hyp/vgic-v3-sr.c return (hap + __ffs(val)) << __vgic_v3_bpr_min(); val 589 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val; val 597 virt/kvm/arm/hyp/vgic-v3-sr.c val = __vgic_v3_read_ap0rn(apr); val 598 virt/kvm/arm/hyp/vgic-v3-sr.c __vgic_v3_write_ap0rn(val | BIT(ap % 32), apr); val 600 virt/kvm/arm/hyp/vgic-v3-sr.c val = __vgic_v3_read_ap1rn(apr); val 601 virt/kvm/arm/hyp/vgic-v3-sr.c __vgic_v3_write_ap1rn(val | BIT(ap % 32), apr); val 774 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val = vcpu_get_reg(vcpu, rt); val 776 virt/kvm/arm/hyp/vgic-v3-sr.c if (val & 1) val 786 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val = vcpu_get_reg(vcpu, rt); val 788 virt/kvm/arm/hyp/vgic-v3-sr.c if (val & 1) val 808 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val = vcpu_get_reg(vcpu, rt); val 812 virt/kvm/arm/hyp/vgic-v3-sr.c if (val < bpr_min) val 813 virt/kvm/arm/hyp/vgic-v3-sr.c val = bpr_min; val 815 virt/kvm/arm/hyp/vgic-v3-sr.c val <<= ICH_VMCR_BPR0_SHIFT; val 816 virt/kvm/arm/hyp/vgic-v3-sr.c val &= ICH_VMCR_BPR0_MASK; val 818 virt/kvm/arm/hyp/vgic-v3-sr.c vmcr |= val; val 825 virt/kvm/arm/hyp/vgic-v3-sr.c u64 val = vcpu_get_reg(vcpu, rt); val 832 virt/kvm/arm/hyp/vgic-v3-sr.c if (val < bpr_min) val 833 virt/kvm/arm/hyp/vgic-v3-sr.c val = bpr_min; val 835 virt/kvm/arm/hyp/vgic-v3-sr.c val <<= ICH_VMCR_BPR1_SHIFT; val 836 virt/kvm/arm/hyp/vgic-v3-sr.c val &= ICH_VMCR_BPR1_MASK; val 838 virt/kvm/arm/hyp/vgic-v3-sr.c vmcr |= val; val 845 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val; val 848 virt/kvm/arm/hyp/vgic-v3-sr.c val = __vgic_v3_read_ap0rn(n); val 850 virt/kvm/arm/hyp/vgic-v3-sr.c val = __vgic_v3_read_ap1rn(n); val 852 virt/kvm/arm/hyp/vgic-v3-sr.c vcpu_set_reg(vcpu, rt, val); val 857 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val = vcpu_get_reg(vcpu, rt); val 860 virt/kvm/arm/hyp/vgic-v3-sr.c __vgic_v3_write_ap0rn(val, n); val 862 virt/kvm/arm/hyp/vgic-v3-sr.c __vgic_v3_write_ap1rn(val, n); val 944 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val = vcpu_get_reg(vcpu, rt); val 946 virt/kvm/arm/hyp/vgic-v3-sr.c val <<= ICH_VMCR_PMR_SHIFT; val 947 virt/kvm/arm/hyp/vgic-v3-sr.c val &= ICH_VMCR_PMR_MASK; val 949 virt/kvm/arm/hyp/vgic-v3-sr.c vmcr |= val; val 957 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val = __vgic_v3_get_highest_active_priority(); val 958 virt/kvm/arm/hyp/vgic-v3-sr.c vcpu_set_reg(vcpu, rt, val); val 964 virt/kvm/arm/hyp/vgic-v3-sr.c u32 vtr, val; val 968 virt/kvm/arm/hyp/vgic-v3-sr.c val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT; val 970 virt/kvm/arm/hyp/vgic-v3-sr.c val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT; val 972 virt/kvm/arm/hyp/vgic-v3-sr.c val |= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT; val 974 virt/kvm/arm/hyp/vgic-v3-sr.c val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT; val 976 virt/kvm/arm/hyp/vgic-v3-sr.c val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT; val 978 virt/kvm/arm/hyp/vgic-v3-sr.c val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; val 980 virt/kvm/arm/hyp/vgic-v3-sr.c vcpu_set_reg(vcpu, rt, val); val 986 virt/kvm/arm/hyp/vgic-v3-sr.c u32 val = vcpu_get_reg(vcpu, rt); val 988 virt/kvm/arm/hyp/vgic-v3-sr.c if (val & ICC_CTLR_EL1_CBPR_MASK) val 993 virt/kvm/arm/hyp/vgic-v3-sr.c if (val & ICC_CTLR_EL1_EOImode_MASK) val 162 virt/kvm/arm/pmu.c void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) val 168 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx); val 196 virt/kvm/arm/pmu.c u64 counter, reg, val; val 206 virt/kvm/arm/pmu.c val = counter; val 209 virt/kvm/arm/pmu.c val = lower_32_bits(counter); val 212 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, reg) = val; val 266 virt/kvm/arm/pmu.c u64 val = __vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMU_PMCR_N_SHIFT; val 268 virt/kvm/arm/pmu.c val &= ARMV8_PMU_PMCR_N_MASK; val 269 virt/kvm/arm/pmu.c if (val == 0) val 272 virt/kvm/arm/pmu.c return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX); val 282 virt/kvm/arm/pmu.c void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) val 288 virt/kvm/arm/pmu.c if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val) val 292 virt/kvm/arm/pmu.c if (!(val & BIT(i))) val 323 virt/kvm/arm/pmu.c void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) val 329 virt/kvm/arm/pmu.c if (!val) val 333 virt/kvm/arm/pmu.c if (!(val & BIT(i))) val 481 virt/kvm/arm/pmu.c void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) val 490 virt/kvm/arm/pmu.c val &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); val 495 virt/kvm/arm/pmu.c if (!(val & BIT(i))) val 531 virt/kvm/arm/pmu.c void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) val 537 virt/kvm/arm/pmu.c if (val & ARMV8_PMU_PMCR_E) { val 544 virt/kvm/arm/pmu.c if (val & ARMV8_PMU_PMCR_C) val 547 virt/kvm/arm/pmu.c if (val & ARMV8_PMU_PMCR_P) { val 225 virt/kvm/arm/psci.c unsigned long val; val 234 virt/kvm/arm/psci.c val = KVM_ARM_PSCI_0_2; val 238 virt/kvm/arm/psci.c val = kvm_psci_vcpu_suspend(vcpu); val 242 virt/kvm/arm/psci.c val = PSCI_RET_SUCCESS; val 247 virt/kvm/arm/psci.c val = kvm_psci_vcpu_on(vcpu); val 252 virt/kvm/arm/psci.c val = kvm_psci_vcpu_affinity_info(vcpu); val 260 virt/kvm/arm/psci.c val = PSCI_0_2_TOS_MP; val 274 virt/kvm/arm/psci.c val = PSCI_RET_INTERNAL_FAILURE; val 283 virt/kvm/arm/psci.c val = PSCI_RET_INTERNAL_FAILURE; val 287 virt/kvm/arm/psci.c val = PSCI_RET_NOT_SUPPORTED; val 291 virt/kvm/arm/psci.c smccc_set_retval(vcpu, val, 0, 0, 0); val 299 virt/kvm/arm/psci.c unsigned long val; val 304 virt/kvm/arm/psci.c val = KVM_ARM_PSCI_1_0; val 322 virt/kvm/arm/psci.c val = 0; val 325 virt/kvm/arm/psci.c val = PSCI_RET_NOT_SUPPORTED; val 333 virt/kvm/arm/psci.c smccc_set_retval(vcpu, val, 0, 0, 0); val 341 virt/kvm/arm/psci.c unsigned long val; val 346 virt/kvm/arm/psci.c val = PSCI_RET_SUCCESS; val 350 virt/kvm/arm/psci.c val = kvm_psci_vcpu_on(vcpu); val 354 virt/kvm/arm/psci.c val = PSCI_RET_NOT_SUPPORTED; val 358 virt/kvm/arm/psci.c smccc_set_retval(vcpu, val, 0, 0, 0); val 393 virt/kvm/arm/psci.c u32 val = SMCCC_RET_NOT_SUPPORTED; val 398 virt/kvm/arm/psci.c val = ARM_SMCCC_VERSION_1_1; val 408 virt/kvm/arm/psci.c val = SMCCC_RET_SUCCESS; val 411 virt/kvm/arm/psci.c val = SMCCC_RET_NOT_REQUIRED; val 421 virt/kvm/arm/psci.c val = SMCCC_RET_SUCCESS; val 425 virt/kvm/arm/psci.c val = SMCCC_RET_NOT_REQUIRED; val 435 virt/kvm/arm/psci.c smccc_set_retval(vcpu, val, 0, 0, 0); val 499 virt/kvm/arm/psci.c u64 val; val 503 virt/kvm/arm/psci.c val = kvm_psci_version(vcpu, vcpu->kvm); val 506 virt/kvm/arm/psci.c val = get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; val 509 virt/kvm/arm/psci.c val = get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; val 511 virt/kvm/arm/psci.c if (val == KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL && val 513 virt/kvm/arm/psci.c val |= KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED; val 519 virt/kvm/arm/psci.c if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id))) val 528 virt/kvm/arm/psci.c u64 val; val 531 virt/kvm/arm/psci.c if (copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id))) val 541 virt/kvm/arm/psci.c switch (val) { val 545 virt/kvm/arm/psci.c vcpu->kvm->arch.psci_version = val; val 551 virt/kvm/arm/psci.c vcpu->kvm->arch.psci_version = val; val 558 virt/kvm/arm/psci.c if (val & ~KVM_REG_FEATURE_LEVEL_MASK) val 561 virt/kvm/arm/psci.c if (get_kernel_wa_level(reg->id) < val) val 567 virt/kvm/arm/psci.c if (val & ~(KVM_REG_FEATURE_LEVEL_MASK | val 571 virt/kvm/arm/psci.c wa_level = val & KVM_REG_FEATURE_LEVEL_MASK; val 578 virt/kvm/arm/psci.c wa_level != val) val 592 virt/kvm/arm/psci.c val & KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED); val 492 virt/kvm/arm/vgic/vgic-its.c u32 val; val 494 virt/kvm/arm/vgic/vgic-its.c val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK; val 495 virt/kvm/arm/vgic/vgic-its.c val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM; val 496 virt/kvm/arm/vgic/vgic-its.c return val; val 502 virt/kvm/arm/vgic/vgic-its.c unsigned long val) val 504 virt/kvm/arm/vgic/vgic-its.c u32 rev = GITS_IIDR_REV(val); val 1488 virt/kvm/arm/vgic/vgic-its.c unsigned long val) val 1495 virt/kvm/arm/vgic/vgic-its.c its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val); val 1549 virt/kvm/arm/vgic/vgic-its.c unsigned long val) val 1558 virt/kvm/arm/vgic/vgic-its.c reg = update_64bit_reg(its->cwriter, addr & 7, len, val); val 1588 virt/kvm/arm/vgic/vgic-its.c unsigned long val) val 1600 virt/kvm/arm/vgic/vgic-its.c cmd_offset = ITS_CMD_OFFSET(val); val 1638 virt/kvm/arm/vgic/vgic-its.c unsigned long val) val 1664 virt/kvm/arm/vgic/vgic-its.c reg = update_64bit_reg(*regptr, addr & 7, len, val); val 1707 virt/kvm/arm/vgic/vgic-its.c unsigned long val) val 1715 virt/kvm/arm/vgic/vgic-its.c if (!its->enabled && (val & GITS_CTLR_ENABLE) && val 1721 virt/kvm/arm/vgic/vgic-its.c its->enabled = !!(val & GITS_CTLR_ENABLE); val 1755 virt/kvm/arm/vgic/vgic-its.c gpa_t addr, unsigned int len, unsigned long val) val 2119 virt/kvm/arm/vgic/vgic-its.c u64 val; val 2122 virt/kvm/arm/vgic/vgic-its.c val = ((u64)next_offset << KVM_ITS_ITE_NEXT_SHIFT) | val 2125 virt/kvm/arm/vgic/vgic-its.c val = cpu_to_le64(val); val 2126 virt/kvm/arm/vgic/vgic-its.c return kvm_write_guest_lock(kvm, gpa, &val, ite_esz); val 2142 virt/kvm/arm/vgic/vgic-its.c u64 val; val 2149 virt/kvm/arm/vgic/vgic-its.c val = *p; val 2151 virt/kvm/arm/vgic/vgic-its.c val = le64_to_cpu(val); val 2153 virt/kvm/arm/vgic/vgic-its.c coll_id = val & KVM_ITS_ITE_ICID_MASK; val 2154 virt/kvm/arm/vgic/vgic-its.c lpi_id = (val & KVM_ITS_ITE_PINTID_MASK) >> KVM_ITS_ITE_PINTID_SHIFT; val 2162 virt/kvm/arm/vgic/vgic-its.c offset = val >> KVM_ITS_ITE_NEXT_SHIFT; val 2263 virt/kvm/arm/vgic/vgic-its.c u64 val, itt_addr_field; val 2268 virt/kvm/arm/vgic/vgic-its.c val = (1ULL << KVM_ITS_DTE_VALID_SHIFT | val 2272 virt/kvm/arm/vgic/vgic-its.c val = cpu_to_le64(val); val 2273 virt/kvm/arm/vgic/vgic-its.c return kvm_write_guest_lock(kvm, ptr, &val, dte_esz); val 2447 virt/kvm/arm/vgic/vgic-its.c u64 val; val 2449 virt/kvm/arm/vgic/vgic-its.c val = (1ULL << KVM_ITS_CTE_VALID_SHIFT | val 2452 virt/kvm/arm/vgic/vgic-its.c val = cpu_to_le64(val); val 2453 virt/kvm/arm/vgic/vgic-its.c return kvm_write_guest_lock(its->dev->kvm, gpa, &val, esz); val 2461 virt/kvm/arm/vgic/vgic-its.c u64 val; val 2464 virt/kvm/arm/vgic/vgic-its.c BUG_ON(esz > sizeof(val)); val 2465 virt/kvm/arm/vgic/vgic-its.c ret = kvm_read_guest_lock(kvm, gpa, &val, esz); val 2468 virt/kvm/arm/vgic/vgic-its.c val = le64_to_cpu(val); val 2469 virt/kvm/arm/vgic/vgic-its.c if (!(val & KVM_ITS_CTE_VALID_MASK)) val 2472 virt/kvm/arm/vgic/vgic-its.c target_addr = (u32)(val >> KVM_ITS_CTE_RDBASE_SHIFT); val 2473 virt/kvm/arm/vgic/vgic-its.c coll_id = val & KVM_ITS_CTE_ICID_MASK; val 2499 virt/kvm/arm/vgic/vgic-its.c u64 val; val 2523 virt/kvm/arm/vgic/vgic-its.c val = 0; val 2524 virt/kvm/arm/vgic/vgic-its.c BUG_ON(cte_esz > sizeof(val)); val 2525 virt/kvm/arm/vgic/vgic-its.c ret = kvm_write_guest_lock(its->dev->kvm, gpa, &val, cte_esz); val 174 virt/kvm/arm/vgic/vgic-kvm-device.c u32 val; val 177 virt/kvm/arm/vgic/vgic-kvm-device.c if (get_user(val, uaddr)) val 186 virt/kvm/arm/vgic/vgic-kvm-device.c if (val < (VGIC_NR_PRIVATE_IRQS + 32) || val 187 virt/kvm/arm/vgic/vgic-kvm-device.c val > VGIC_MAX_RESERVED || val 188 virt/kvm/arm/vgic/vgic-kvm-device.c (val & 31)) val 197 virt/kvm/arm/vgic/vgic-kvm-device.c val - VGIC_NR_PRIVATE_IRQS; val 54 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 61 virt/kvm/arm/vgic/vgic-mmio-v2.c dist->enabled = val & GICD_ENABLE; val 74 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 78 virt/kvm/arm/vgic/vgic-mmio-v2.c if (val != vgic_mmio_read_v2_misc(vcpu, addr, len)) val 94 virt/kvm/arm/vgic/vgic-mmio-v2.c vgic_mmio_write_v2_misc(vcpu, addr, len, val); val 100 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 103 virt/kvm/arm/vgic/vgic-mmio-v2.c vgic_mmio_write_group(vcpu, addr, len, val); val 110 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 113 virt/kvm/arm/vgic/vgic-mmio-v2.c int intid = val & 0xf; val 114 virt/kvm/arm/vgic/vgic-mmio-v2.c int targets = (val >> 16) & 0xff; val 115 virt/kvm/arm/vgic/vgic-mmio-v2.c int mode = (val >> 24) & 0x03; val 156 virt/kvm/arm/vgic/vgic-mmio-v2.c u64 val = 0; val 161 virt/kvm/arm/vgic/vgic-mmio-v2.c val |= (u64)irq->targets << (i * 8); val 166 virt/kvm/arm/vgic/vgic-mmio-v2.c return val; val 171 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 188 virt/kvm/arm/vgic/vgic-mmio-v2.c irq->targets = (val >> (i * 8)) & cpu_mask; val 202 virt/kvm/arm/vgic/vgic-mmio-v2.c u64 val = 0; val 207 virt/kvm/arm/vgic/vgic-mmio-v2.c val |= (u64)irq->source << (i * 8); val 211 virt/kvm/arm/vgic/vgic-mmio-v2.c return val; val 216 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 227 virt/kvm/arm/vgic/vgic-mmio-v2.c irq->source &= ~((val >> (i * 8)) & 0xff); val 238 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 249 virt/kvm/arm/vgic/vgic-mmio-v2.c irq->source |= (val >> (i * 8)) & 0xff; val 268 virt/kvm/arm/vgic/vgic-mmio-v2.c u32 val; val 274 virt/kvm/arm/vgic/vgic-mmio-v2.c val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT; val 275 virt/kvm/arm/vgic/vgic-mmio-v2.c val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT; val 276 virt/kvm/arm/vgic/vgic-mmio-v2.c val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT; val 277 virt/kvm/arm/vgic/vgic-mmio-v2.c val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT; val 278 virt/kvm/arm/vgic/vgic-mmio-v2.c val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT; val 279 virt/kvm/arm/vgic/vgic-mmio-v2.c val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT; val 290 virt/kvm/arm/vgic/vgic-mmio-v2.c val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >> val 294 virt/kvm/arm/vgic/vgic-mmio-v2.c val = vmcr.bpr; val 297 virt/kvm/arm/vgic/vgic-mmio-v2.c val = vmcr.abpr; val 300 virt/kvm/arm/vgic/vgic-mmio-v2.c val = ((PRODUCT_ID_KVM << 20) | val 308 virt/kvm/arm/vgic/vgic-mmio-v2.c return val; val 313 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 321 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0); val 322 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1); val 323 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl); val 324 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn); val 325 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR); val 326 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS); val 337 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) & val 341 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.bpr = val; val 344 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.abpr = val; val 378 virt/kvm/arm/vgic/vgic-mmio-v2.c unsigned long val) val 388 virt/kvm/arm/vgic/vgic-mmio-v2.c vcpu->arch.vgic_cpu.vgic_v2.vgic_apr = val; val 398 virt/kvm/arm/vgic/vgic-mmio-v2.c vgicv3->vgic_ap1r[n] = val; val 525 virt/kvm/arm/vgic/vgic-mmio-v2.c int offset, u32 *val) val 533 virt/kvm/arm/vgic/vgic-mmio-v2.c return vgic_uaccess(vcpu, &dev, is_write, offset, val); val 537 virt/kvm/arm/vgic/vgic-mmio-v2.c int offset, u32 *val) val 545 virt/kvm/arm/vgic/vgic-mmio-v2.c return vgic_uaccess(vcpu, &dev, is_write, offset, val); val 28 virt/kvm/arm/vgic/vgic-mmio-v3.c unsigned long val) val 34 virt/kvm/arm/vgic/vgic-mmio-v3.c val &= GENMASK_ULL(len * 8 - 1, 0); val 36 virt/kvm/arm/vgic/vgic-mmio-v3.c return reg | ((u64)val << lower); val 97 virt/kvm/arm/vgic/vgic-mmio-v3.c unsigned long val) val 104 virt/kvm/arm/vgic/vgic-mmio-v3.c dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; val 117 virt/kvm/arm/vgic/vgic-mmio-v3.c unsigned long val) val 121 virt/kvm/arm/vgic/vgic-mmio-v3.c if (val != vgic_mmio_read_v3_misc(vcpu, addr, len)) val 125 virt/kvm/arm/vgic/vgic-mmio-v3.c vgic_mmio_write_v3_misc(vcpu, addr, len, val); val 149 virt/kvm/arm/vgic/vgic-mmio-v3.c unsigned long val) val 167 virt/kvm/arm/vgic/vgic-mmio-v3.c irq->mpidr = val & GENMASK(23, 0); val 185 virt/kvm/arm/vgic/vgic-mmio-v3.c unsigned long val) val 193 virt/kvm/arm/vgic/vgic-mmio-v3.c vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS; val 272 virt/kvm/arm/vgic/vgic-mmio-v3.c unsigned long val) val 282 virt/kvm/arm/vgic/vgic-mmio-v3.c if (test_bit(i, &val)) { val 394 virt/kvm/arm/vgic/vgic-mmio-v3.c unsigned long val) val 407 virt/kvm/arm/vgic/vgic-mmio-v3.c propbaser = update_64bit_reg(propbaser, addr & 4, len, val); val 423 virt/kvm/arm/vgic/vgic-mmio-v3.c unsigned long val) val 435 virt/kvm/arm/vgic/vgic-mmio-v3.c pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); val 953 virt/kvm/arm/vgic/vgic-mmio-v3.c int offset, u32 *val) val 960 virt/kvm/arm/vgic/vgic-mmio-v3.c return vgic_uaccess(vcpu, &dev, is_write, offset, val); val 964 virt/kvm/arm/vgic/vgic-mmio-v3.c int offset, u32 *val) val 971 virt/kvm/arm/vgic/vgic-mmio-v3.c return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val); val 975 virt/kvm/arm/vgic/vgic-mmio-v3.c u32 intid, u64 *val) val 981 virt/kvm/arm/vgic/vgic-mmio-v3.c vgic_write_irq_line_level_info(vcpu, intid, *val); val 983 virt/kvm/arm/vgic/vgic-mmio-v3.c *val = vgic_read_irq_line_level_info(vcpu, intid); val 30 virt/kvm/arm/vgic/vgic-mmio.c unsigned int len, unsigned long val) val 36 virt/kvm/arm/vgic/vgic-mmio.c unsigned int len, unsigned long val) val 63 virt/kvm/arm/vgic/vgic-mmio.c unsigned int len, unsigned long val) val 73 virt/kvm/arm/vgic/vgic-mmio.c irq->group = !!(val & BIT(i)); val 106 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 112 virt/kvm/arm/vgic/vgic-mmio.c for_each_set_bit(i, &val, len * 8) { val 141 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 147 virt/kvm/arm/vgic/vgic-mmio.c for_each_set_bit(i, &val, len * 8) { val 222 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 229 virt/kvm/arm/vgic/vgic-mmio.c for_each_set_bit(i, &val, len * 8) { val 275 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 282 virt/kvm/arm/vgic/vgic-mmio.c for_each_set_bit(i, &val, len * 8) { val 362 virt/kvm/arm/vgic/vgic-mmio.c u32 val; val 367 virt/kvm/arm/vgic/vgic-mmio.c val = __vgic_mmio_read_active(vcpu, addr, len); val 372 virt/kvm/arm/vgic/vgic-mmio.c return val; val 434 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 439 virt/kvm/arm/vgic/vgic-mmio.c for_each_set_bit(i, &val, len * 8) { val 448 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 455 virt/kvm/arm/vgic/vgic-mmio.c __vgic_mmio_write_cactive(vcpu, addr, len, val); val 463 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 465 virt/kvm/arm/vgic/vgic-mmio.c __vgic_mmio_write_cactive(vcpu, addr, len, val); val 471 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 476 virt/kvm/arm/vgic/vgic-mmio.c for_each_set_bit(i, &val, len * 8) { val 485 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 492 virt/kvm/arm/vgic/vgic-mmio.c __vgic_mmio_write_sactive(vcpu, addr, len, val); val 500 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 502 virt/kvm/arm/vgic/vgic-mmio.c __vgic_mmio_write_sactive(vcpu, addr, len, val); val 511 virt/kvm/arm/vgic/vgic-mmio.c u64 val = 0; val 516 virt/kvm/arm/vgic/vgic-mmio.c val |= (u64)irq->priority << (i * 8); val 521 virt/kvm/arm/vgic/vgic-mmio.c return val; val 533 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 544 virt/kvm/arm/vgic/vgic-mmio.c irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS); val 572 virt/kvm/arm/vgic/vgic-mmio.c unsigned long val) val 593 virt/kvm/arm/vgic/vgic-mmio.c if (test_bit(i * 2 + 1, &val)) val 606 virt/kvm/arm/vgic/vgic-mmio.c u64 val = 0; val 617 virt/kvm/arm/vgic/vgic-mmio.c val |= (1U << i); val 622 virt/kvm/arm/vgic/vgic-mmio.c return val; val 626 virt/kvm/arm/vgic/vgic-mmio.c const u64 val) val 646 virt/kvm/arm/vgic/vgic-mmio.c new_level = !!(val & (1U << i)); val 705 virt/kvm/arm/vgic/vgic-mmio.c unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len) val 707 virt/kvm/arm/vgic/vgic-mmio.c unsigned long data = kvm_mmio_read_buf(val, len); val 801 virt/kvm/arm/vgic/vgic-mmio.c gpa_t addr, u32 *val) val 809 virt/kvm/arm/vgic/vgic-mmio.c *val = 0; val 815 virt/kvm/arm/vgic/vgic-mmio.c *val = region->uaccess_read(r_vcpu, addr, sizeof(u32)); val 817 virt/kvm/arm/vgic/vgic-mmio.c *val = region->read(r_vcpu, addr, sizeof(u32)); val 823 virt/kvm/arm/vgic/vgic-mmio.c gpa_t addr, const u32 *val) val 835 virt/kvm/arm/vgic/vgic-mmio.c return region->uaccess_write(r_vcpu, addr, sizeof(u32), *val); val 837 virt/kvm/arm/vgic/vgic-mmio.c region->write(r_vcpu, addr, sizeof(u32), *val); val 845 virt/kvm/arm/vgic/vgic-mmio.c bool is_write, int offset, u32 *val) val 848 virt/kvm/arm/vgic/vgic-mmio.c return vgic_uaccess_write(vcpu, &dev->dev, offset, val); val 850 virt/kvm/arm/vgic/vgic-mmio.c return vgic_uaccess_read(vcpu, &dev->dev, offset, val); val 854 virt/kvm/arm/vgic/vgic-mmio.c gpa_t addr, int len, void *val) val 862 virt/kvm/arm/vgic/vgic-mmio.c memset(val, 0, len); val 881 virt/kvm/arm/vgic/vgic-mmio.c vgic_data_host_to_mmio_bus(val, len, data); val 886 virt/kvm/arm/vgic/vgic-mmio.c gpa_t addr, int len, const void *val) val 890 virt/kvm/arm/vgic/vgic-mmio.c unsigned long data = vgic_data_mmio_bus_to_host(val, len); val 21 virt/kvm/arm/vgic/vgic-mmio.h unsigned int len, unsigned long val); val 24 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 30 virt/kvm/arm/vgic/vgic-mmio.h unsigned int len, unsigned long val); val 33 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 106 virt/kvm/arm/vgic/vgic-mmio.h unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len); val 115 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 124 virt/kvm/arm/vgic/vgic-mmio.h unsigned int len, unsigned long val); val 127 virt/kvm/arm/vgic/vgic-mmio.h unsigned int len, unsigned long val); val 133 virt/kvm/arm/vgic/vgic-mmio.h unsigned int len, unsigned long val); val 140 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 144 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 151 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 155 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 165 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 169 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 173 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 177 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 184 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 191 virt/kvm/arm/vgic/vgic-mmio.h unsigned long val); val 194 virt/kvm/arm/vgic/vgic-mmio.h bool is_write, int offset, u32 *val); val 199 virt/kvm/arm/vgic/vgic-mmio.h const u64 val); val 14 virt/kvm/arm/vgic/vgic-v2.c static inline void vgic_v2_write_lr(int lr, u32 val) val 18 virt/kvm/arm/vgic/vgic-v2.c writel_relaxed(val, base + GICH_LR0 + (lr * 4)); val 60 virt/kvm/arm/vgic/vgic-v2.c u32 val = cpuif->vgic_lr[lr]; val 61 virt/kvm/arm/vgic/vgic-v2.c u32 cpuid, intid = val & GICH_LR_VIRTUALID; val 65 virt/kvm/arm/vgic/vgic-v2.c cpuid = val & GICH_LR_PHYSID_CPUID; val 70 virt/kvm/arm/vgic/vgic-v2.c if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) val 79 virt/kvm/arm/vgic/vgic-v2.c irq->active = !!(val & GICH_LR_ACTIVE_BIT); val 86 virt/kvm/arm/vgic/vgic-v2.c (val & GICH_LR_PENDING_BIT)) { val 96 virt/kvm/arm/vgic/vgic-v2.c if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE)) val 112 virt/kvm/arm/vgic/vgic-v2.c if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) { val 139 virt/kvm/arm/vgic/vgic-v2.c u32 val = irq->intid; val 143 virt/kvm/arm/vgic/vgic-v2.c val |= GICH_LR_ACTIVE_BIT; val 145 virt/kvm/arm/vgic/vgic-v2.c val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT; val 148 virt/kvm/arm/vgic/vgic-v2.c val |= GICH_LR_EOI; val 153 virt/kvm/arm/vgic/vgic-v2.c val |= GICH_LR_GROUP1; val 156 virt/kvm/arm/vgic/vgic-v2.c val |= GICH_LR_HW; val 157 virt/kvm/arm/vgic/vgic-v2.c val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT; val 167 virt/kvm/arm/vgic/vgic-v2.c val |= GICH_LR_EOI; val 179 virt/kvm/arm/vgic/vgic-v2.c val |= GICH_LR_PENDING_BIT; val 191 virt/kvm/arm/vgic/vgic-v2.c val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; val 195 virt/kvm/arm/vgic/vgic-v2.c val |= GICH_LR_EOI; val 206 virt/kvm/arm/vgic/vgic-v2.c if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) val 210 virt/kvm/arm/vgic/vgic-v2.c val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT; val 212 virt/kvm/arm/vgic/vgic-v2.c vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val; val 43 virt/kvm/arm/vgic/vgic-v3.c u64 val = cpuif->vgic_lr[lr]; val 48 virt/kvm/arm/vgic/vgic-v3.c cpuid = val & GICH_LR_PHYSID_CPUID; val 52 virt/kvm/arm/vgic/vgic-v3.c intid = val & ICH_LR_VIRTUAL_ID_MASK; val 54 virt/kvm/arm/vgic/vgic-v3.c intid = val & GICH_LR_VIRTUALID; val 59 virt/kvm/arm/vgic/vgic-v3.c if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) val 70 virt/kvm/arm/vgic/vgic-v3.c irq->active = !!(val & ICH_LR_ACTIVE_BIT); val 77 virt/kvm/arm/vgic/vgic-v3.c (val & ICH_LR_PENDING_BIT)) { val 87 virt/kvm/arm/vgic/vgic-v3.c if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE)) val 103 virt/kvm/arm/vgic/vgic-v3.c if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT)) { val 121 virt/kvm/arm/vgic/vgic-v3.c u64 val = irq->intid; val 128 virt/kvm/arm/vgic/vgic-v3.c val |= ICH_LR_ACTIVE_BIT; val 130 virt/kvm/arm/vgic/vgic-v3.c val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT; val 133 virt/kvm/arm/vgic/vgic-v3.c val |= ICH_LR_EOI; val 138 virt/kvm/arm/vgic/vgic-v3.c val |= ICH_LR_HW; val 139 virt/kvm/arm/vgic/vgic-v3.c val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; val 149 virt/kvm/arm/vgic/vgic-v3.c val |= ICH_LR_EOI; val 161 virt/kvm/arm/vgic/vgic-v3.c val |= ICH_LR_PENDING_BIT; val 174 virt/kvm/arm/vgic/vgic-v3.c val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; val 178 virt/kvm/arm/vgic/vgic-v3.c val |= ICH_LR_EOI; val 189 virt/kvm/arm/vgic/vgic-v3.c if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT)) val 193 virt/kvm/arm/vgic/vgic-v3.c val |= ICH_LR_GROUP; val 195 virt/kvm/arm/vgic/vgic-v3.c val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT; val 197 virt/kvm/arm/vgic/vgic-v3.c vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val; val 320 virt/kvm/arm/vgic/vgic-v3.c u8 val; val 335 virt/kvm/arm/vgic/vgic-v3.c ret = kvm_read_guest_lock(kvm, ptr, &val, 1); val 339 virt/kvm/arm/vgic/vgic-v3.c status = val & (1 << bit_nr); val 351 virt/kvm/arm/vgic/vgic-v3.c val &= ~(1 << bit_nr); val 352 virt/kvm/arm/vgic/vgic-v3.c ret = kvm_write_guest_lock(kvm, ptr, &val, 1); val 369 virt/kvm/arm/vgic/vgic-v3.c u8 val; val 388 virt/kvm/arm/vgic/vgic-v3.c ret = kvm_read_guest_lock(kvm, ptr, &val, 1); val 394 virt/kvm/arm/vgic/vgic-v3.c stored = val & (1U << bit_nr); val 399 virt/kvm/arm/vgic/vgic-v3.c val |= 1 << bit_nr; val 401 virt/kvm/arm/vgic/vgic-v3.c val &= ~(1 << bit_nr); val 403 virt/kvm/arm/vgic/vgic-v3.c ret = kvm_write_guest_lock(kvm, ptr, &val, 1); val 39 virt/kvm/arm/vgic/vgic.h #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \ val 40 virt/kvm/arm/vgic/vgic.h VGIC_AFFINITY_LEVEL(val, 1) | \ val 41 virt/kvm/arm/vgic/vgic.h VGIC_AFFINITY_LEVEL(val, 2) | \ val 42 virt/kvm/arm/vgic/vgic.h VGIC_AFFINITY_LEVEL(val, 3)) val 183 virt/kvm/arm/vgic/vgic.h int offset, u32 *val); val 185 virt/kvm/arm/vgic/vgic.h int offset, u32 *val); val 237 virt/kvm/arm/vgic/vgic.h int offset, u32 *val); val 239 virt/kvm/arm/vgic/vgic.h int offset, u32 *val); val 241 virt/kvm/arm/vgic/vgic.h u64 id, u64 *val); val 245 virt/kvm/arm/vgic/vgic.h u32 intid, u64 *val); val 66 virt/kvm/coalesced_mmio.c int len, const void *val) val 88 virt/kvm/coalesced_mmio.c memcpy(ring->coalesced_mmio[insert].data, val, len); val 683 virt/kvm/eventfd.c ioeventfd_in_range(struct _ioeventfd *p, gpa_t addr, int len, const void *val) val 705 virt/kvm/eventfd.c BUG_ON(!IS_ALIGNED((unsigned long)val, len)); val 709 virt/kvm/eventfd.c _val = *(u8 *)val; val 712 virt/kvm/eventfd.c _val = *(u16 *)val; val 715 virt/kvm/eventfd.c _val = *(u32 *)val; val 718 virt/kvm/eventfd.c _val = *(u64 *)val; val 730 virt/kvm/eventfd.c int len, const void *val) val 734 virt/kvm/eventfd.c if (!ioeventfd_in_range(p, addr, len, val)) val 2411 virt/kvm/kvm_main.c unsigned int old, val, grow, grow_start; val 2413 virt/kvm/kvm_main.c old = val = vcpu->halt_poll_ns; val 2419 virt/kvm/kvm_main.c val *= grow; val 2420 virt/kvm/kvm_main.c if (val < grow_start) val 2421 virt/kvm/kvm_main.c val = grow_start; val 2423 virt/kvm/kvm_main.c if (val > halt_poll_ns) val 2424 virt/kvm/kvm_main.c val = halt_poll_ns; val 2426 virt/kvm/kvm_main.c vcpu->halt_poll_ns = val; val 2428 virt/kvm/kvm_main.c trace_kvm_halt_poll_ns_grow(vcpu->vcpu_id, val, old); val 2433 virt/kvm/kvm_main.c unsigned int old, val, shrink; val 2435 virt/kvm/kvm_main.c old = val = vcpu->halt_poll_ns; val 2438 virt/kvm/kvm_main.c val = 0; val 2440 virt/kvm/kvm_main.c val /= shrink; val 2442 virt/kvm/kvm_main.c vcpu->halt_poll_ns = val; val 2443 virt/kvm/kvm_main.c trace_kvm_halt_poll_ns_shrink(vcpu->vcpu_id, val, old); val 3768 virt/kvm/kvm_main.c static int kvm_reboot(struct notifier_block *notifier, unsigned long val, val 3855 virt/kvm/kvm_main.c struct kvm_io_range *range, const void *val) val 3866 virt/kvm/kvm_main.c range->len, val)) val 3876 virt/kvm/kvm_main.c int len, const void *val) val 3890 virt/kvm/kvm_main.c r = __kvm_io_bus_write(vcpu, bus, &range, val); val 3897 virt/kvm/kvm_main.c gpa_t addr, int len, const void *val, long cookie) val 3915 virt/kvm/kvm_main.c val)) val 3922 virt/kvm/kvm_main.c return __kvm_io_bus_write(vcpu, bus, &range, val); val 3926 virt/kvm/kvm_main.c struct kvm_io_range *range, void *val) val 3937 virt/kvm/kvm_main.c range->len, val)) val 3947 virt/kvm/kvm_main.c int len, void *val) val 3961 virt/kvm/kvm_main.c r = __kvm_io_bus_read(vcpu, bus, &range, val); val 4108 virt/kvm/kvm_main.c static int vm_stat_get_per_vm(void *data, u64 *val) val 4112 virt/kvm/kvm_main.c *val = *(ulong *)((void *)stat_data->kvm + stat_data->offset); val 4117 virt/kvm/kvm_main.c static int vm_stat_clear_per_vm(void *data, u64 val) val 4121 virt/kvm/kvm_main.c if (val) val 4145 virt/kvm/kvm_main.c static int vcpu_stat_get_per_vm(void *data, u64 *val) val 4151 virt/kvm/kvm_main.c *val = 0; val 4154 virt/kvm/kvm_main.c *val += *(u64 *)((void *)vcpu + stat_data->offset); val 4159 virt/kvm/kvm_main.c static int vcpu_stat_clear_per_vm(void *data, u64 val) val 4165 virt/kvm/kvm_main.c if (val) val 4195 virt/kvm/kvm_main.c static int vm_stat_get(void *_offset, u64 *val) val 4202 virt/kvm/kvm_main.c *val = 0; val 4207 virt/kvm/kvm_main.c *val += tmp_val; val 4213 virt/kvm/kvm_main.c static int vm_stat_clear(void *_offset, u64 val) val 4219 virt/kvm/kvm_main.c if (val) val 4234 virt/kvm/kvm_main.c static int vcpu_stat_get(void *_offset, u64 *val) val 4241 virt/kvm/kvm_main.c *val = 0; val 4246 virt/kvm/kvm_main.c *val += tmp_val; val 4252 virt/kvm/kvm_main.c static int vcpu_stat_clear(void *_offset, u64 val) val 4258 virt/kvm/kvm_main.c if (val)