v5 127 arch/powerpc/lib/xor_vmx.c DEFINE(v5); v5 135 arch/powerpc/lib/xor_vmx.c LOAD(v5); v5 138 arch/powerpc/lib/xor_vmx.c XOR(v1, v5); v5 146 arch/powerpc/lib/xor_vmx.c v5 += 4; v5 106 arch/s390/include/asm/vx-insn.h .ifc \vxr,%v5 v5 99 drivers/char/mwave/mwavedd.h #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ v5 101 drivers/char/mwave/mwavedd.h printk(s,v1,v2,v3,v4,v5); \ v5 104 drivers/char/mwave/mwavedd.h #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ v5 106 drivers/char/mwave/mwavedd.h printk(s,v1,v2,v3,v4,v5,v6); \ v5 109 drivers/char/mwave/mwavedd.h #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ v5 111 drivers/char/mwave/mwavedd.h printk(s,v1,v2,v3,v4,v5,v6,v7); \ v5 120 drivers/char/mwave/mwavedd.h #define PRINTK_6(f,s,v1,v2,v3,v4,v5) v5 121 drivers/char/mwave/mwavedd.h #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) v5 122 drivers/char/mwave/mwavedd.h #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) v5 991 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; v5 1037 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); v5 1039 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; v5 1043 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->post_div = args.v5.ucPostDiv; v5 1044 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->enable_post_div = (args.v5.ucCntlFlag & v5 1046 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->enable_dithen = (args.v5.ucCntlFlag & v5 1048 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); v5 1049 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); v5 1050 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->ref_div = args.v5.ucRefDiv; v5 1051 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->vco_mode = (args.v5.ucCntlFlag & v5 463 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c PIXEL_CLOCK_PARAMETERS_V5 v5; v5 492 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucCRTC = ATOM_CRTC_INVALID; v5 493 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.usPixelClock = cpu_to_le16(dispclk); v5 494 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucPpll = ATOM_DCPLL; v5 644 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucCRTC = crtc_id; v5 645 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.usPixelClock = cpu_to_le16(clock / 10); v5 646 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucRefDiv = ref_div; v5 647 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.usFbDiv = cpu_to_le16(fb_div); v5 648 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); v5 649 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucPostDiv = post_div; v5 650 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ v5 653 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; v5 658 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; v5 662 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; v5 666 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; v5 670 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucTransmitterID = encoder_id; v5 671 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucEncoderMode = encoder_mode; v5 672 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucPpll = pll_id; v5 568 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c DIG_ENCODER_CONTROL_PARAMETERS_V5 v5; v5 699 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asDPPanelModeParam.ucAction = action; v5 700 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asDPPanelModeParam.ucPanelMode = panel_mode; v5 701 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asDPPanelModeParam.ucDigId = dig->dig_encoder; v5 704 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ucAction = action; v5 705 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ucDigId = dig->dig_encoder; v5 706 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ucDigMode = v5 708 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c if (ENCODER_MODE_IS_DP(args.v5.asStreamParam.ucDigMode)) v5 709 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ucLaneNum = dp_lane_count; v5 712 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ucLaneNum = 8; v5 714 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ucLaneNum = 4; v5 715 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ulPixelClock = v5 717 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ucBitPerColor = v5 719 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asStreamParam.ucLinkRateIn270Mhz = dp_clock / 27000; v5 729 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asCmdParam.ucAction = action; v5 730 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asCmdParam.ucDigId = dig->dig_encoder; v5 756 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; v5 1058 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucAction = action; v5 1060 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.usSymClock = cpu_to_le16(dp_clock / 10); v5 1062 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.usSymClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); v5 1067 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; v5 1069 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; v5 1073 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; v5 1075 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; v5 1079 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; v5 1081 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; v5 1084 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; v5 1088 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucLaneNum = dp_lane_count; v5 1090 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucLaneNum = 8; v5 1092 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucLaneNum = 4; v5 1093 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucConnObjId = connector_object_id; v5 1094 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucDigMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); v5 1097 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; v5 1099 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asConfig.ucPhyClkSrcId = pll_id; v5 1102 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ v5 1105 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asConfig.ucCoherentMode = 1; v5 1108 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asConfig.ucHPDSel = 0; v5 1110 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.asConfig.ucHPDSel = hpd_id + 1; v5 1111 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucDigEncoderSel = 1 << dig_encoder; v5 1112 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v5.ucDPLaneSet = lane_set; v5 101 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) v5 103 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5); v5 38 drivers/gpu/drm/amd/display/dc/inc/dcn_calc_math.h float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5); v5 86 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5) \ v5 92 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5) v5 95 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6) \ v5 101 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ v5 105 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7) \ v5 111 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ v5 116 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7, f8, v8) \ v5 122 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ v5 128 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9) \ v5 134 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 141 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ v5 147 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 178 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ v5 184 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5) v5 186 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ v5 192 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ v5 195 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ v5 201 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ v5 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ v5 211 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ v5 252 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ v5 258 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5) v5 260 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ v5 266 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 269 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ v5 275 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ v5 285 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ v5 296 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ v5 308 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v5 322 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v5 340 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v5 363 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ v5 767 drivers/gpu/drm/radeon/atombios_crtc.c PIXEL_CLOCK_PARAMETERS_V5 v5; v5 795 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucCRTC = ATOM_CRTC_INVALID; v5 796 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.usPixelClock = cpu_to_le16(dispclk); v5 797 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucPpll = ATOM_DCPLL; v5 891 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucCRTC = crtc_id; v5 892 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.usPixelClock = cpu_to_le16(clock / 10); v5 893 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucRefDiv = ref_div; v5 894 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.usFbDiv = cpu_to_le16(fb_div); v5 895 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); v5 896 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucPostDiv = post_div; v5 897 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ v5 899 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; v5 904 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; v5 908 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; v5 912 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; v5 916 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucTransmitterID = encoder_id; v5 917 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucEncoderMode = encoder_mode; v5 918 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucPpll = pll_id; v5 1012 drivers/gpu/drm/radeon/atombios_encoders.c DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; v5 1313 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucAction = action; v5 1315 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.usSymClock = cpu_to_le16(dp_clock / 10); v5 1317 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); v5 1322 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; v5 1324 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; v5 1328 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; v5 1330 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; v5 1334 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; v5 1336 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; v5 1339 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; v5 1343 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucLaneNum = dp_lane_count; v5 1345 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucLaneNum = 8; v5 1347 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucLaneNum = 4; v5 1348 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucConnObjId = connector_object_id; v5 1349 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucDigMode = atombios_get_encoder_mode(encoder); v5 1352 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; v5 1354 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.asConfig.ucPhyClkSrcId = pll_id; v5 1357 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ v5 1360 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.asConfig.ucCoherentMode = 1; v5 1363 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.asConfig.ucHPDSel = 0; v5 1365 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.asConfig.ucHPDSel = hpd_id + 1; v5 1366 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); v5 1367 drivers/gpu/drm/radeon/atombios_encoders.c args.v5.ucDPLaneSet = lane_set; v5 2832 drivers/gpu/drm/radeon/radeon_atombios.c struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; v5 2904 drivers/gpu/drm/radeon/radeon_atombios.c args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); v5 2906 drivers/gpu/drm/radeon/radeon_atombios.c args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; v5 2910 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_div = args.v5.ucPostDiv; v5 2911 drivers/gpu/drm/radeon/radeon_atombios.c dividers->enable_post_div = (args.v5.ucCntlFlag & v5 2913 drivers/gpu/drm/radeon/radeon_atombios.c dividers->enable_dithen = (args.v5.ucCntlFlag & v5 2915 drivers/gpu/drm/radeon/radeon_atombios.c dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); v5 2916 drivers/gpu/drm/radeon/radeon_atombios.c dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); v5 2917 drivers/gpu/drm/radeon/radeon_atombios.c dividers->ref_div = args.v5.ucRefDiv; v5 2918 drivers/gpu/drm/radeon/radeon_atombios.c dividers->vco_mode = (args.v5.ucCntlFlag & v5 58 drivers/input/rmi4/rmi_f34.c init_completion(&f34->v5.cmd_done); v5 60 drivers/input/rmi4/rmi_f34.c ret = rmi_read(rmi_dev, f34->v5.ctrl_address, &f34->v5.status); v5 68 drivers/input/rmi4/rmi_f34.c f34->v5.status |= command & 0x0f; v5 70 drivers/input/rmi4/rmi_f34.c ret = rmi_write(rmi_dev, f34->v5.ctrl_address, f34->v5.status); v5 78 drivers/input/rmi4/rmi_f34.c if (!wait_for_completion_timeout(&f34->v5.cmd_done, v5 81 drivers/input/rmi4/rmi_f34.c ret = rmi_read(rmi_dev, f34->v5.ctrl_address, &f34->v5.status); v5 89 drivers/input/rmi4/rmi_f34.c if (f34->v5.status & 0x7f) { v5 92 drivers/input/rmi4/rmi_f34.c __func__, command, f34->v5.status); v5 108 drivers/input/rmi4/rmi_f34.c ret = rmi_read(f34->fn->rmi_dev, f34->v5.ctrl_address, v5 114 drivers/input/rmi4/rmi_f34.c complete(&f34->v5.cmd_done); v5 149 drivers/input/rmi4/rmi_f34.c data, f34->v5.block_size); v5 167 drivers/input/rmi4/rmi_f34.c data += f34->v5.block_size; v5 168 drivers/input/rmi4/rmi_f34.c f34->update_progress += f34->v5.block_size; v5 178 drivers/input/rmi4/rmi_f34.c return rmi_f34_write_blocks(f34, data, f34->v5.fw_blocks, v5 184 drivers/input/rmi4/rmi_f34.c return rmi_f34_write_blocks(f34, data, f34->v5.config_blocks, v5 266 drivers/input/rmi4/rmi_f34.c if (image_size && image_size != f34->v5.fw_blocks * f34->v5.block_size) { v5 269 drivers/input/rmi4/rmi_f34.c image_size, f34->v5.fw_blocks * f34->v5.block_size); v5 275 drivers/input/rmi4/rmi_f34.c config_size != f34->v5.config_blocks * f34->v5.block_size) { v5 279 drivers/input/rmi4/rmi_f34.c f34->v5.config_blocks * f34->v5.block_size); v5 291 drivers/input/rmi4/rmi_f34.c mutex_lock(&f34->v5.flash_mutex); v5 295 drivers/input/rmi4/rmi_f34.c mutex_unlock(&f34->v5.flash_mutex); v5 552 drivers/input/rmi4/rmi_f34.c mutex_init(&f34->v5.flash_mutex); v5 553 drivers/input/rmi4/rmi_f34.c init_completion(&f34->v5.cmd_done); v5 555 drivers/input/rmi4/rmi_f34.c f34->v5.block_size = get_unaligned_le16(&f34_queries[3]); v5 556 drivers/input/rmi4/rmi_f34.c f34->v5.fw_blocks = get_unaligned_le16(&f34_queries[5]); v5 557 drivers/input/rmi4/rmi_f34.c f34->v5.config_blocks = get_unaligned_le16(&f34_queries[7]); v5 558 drivers/input/rmi4/rmi_f34.c f34->v5.ctrl_address = fn->fd.data_base_addr + F34_BLOCK_DATA_OFFSET + v5 559 drivers/input/rmi4/rmi_f34.c f34->v5.block_size; v5 565 drivers/input/rmi4/rmi_f34.c f34->v5.block_size); v5 567 drivers/input/rmi4/rmi_f34.c f34->v5.fw_blocks); v5 569 drivers/input/rmi4/rmi_f34.c f34->v5.config_blocks); v5 303 drivers/input/rmi4/rmi_f34.h struct f34v5_data v5; v5 603 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h } v5; v5 845 drivers/net/wireless/intel/iwlwifi/mvm/fw.c struct iwl_dev_tx_power_cmd v5; v5 856 drivers/net/wireless/intel/iwlwifi/mvm/fw.c cmd.v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS); v5 860 drivers/net/wireless/intel/iwlwifi/mvm/fw.c len = sizeof(cmd.v5); v5 895 drivers/net/wireless/intel/iwlwifi/mvm/fw.c cmd.v5.v3.per_chain_restriction[i][j] = v5 1283 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c struct iwl_dev_tx_power_cmd v5; v5 1286 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_MAC), v5 1287 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .v5.v3.mac_context_id = v5 1289 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .v5.v3.pwr_restriction = cpu_to_le16(8 * tx_power), v5 1293 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c cmd.v5.v3.pwr_restriction = cpu_to_le16(IWL_DEV_MAX_TX_POWER); v5 1297 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c len = sizeof(cmd.v5); v5 873 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; v5 884 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c v5 = phy_regarray_table_pg[i+4]; v5 889 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c v4, v5, v6); v5 714 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; v5 725 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c v5 = phy_regarray_table_pg[i+4]; v5 734 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c v1, v2, v3, v4, v5, v6); v5 2009 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u32 v1, v2, v3, v4, v5, v6; v5 2029 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c v5 = array[i+4]; v5 2054 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c v4, v5, v6); v5 629 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c u32 v5 = Array[i+4]; v5 632 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c odm_ConfigBB_PHY_REG_PG_8723B(pDM_Odm, v1, v2, v3, v4, v5, v6); v5 4351 drivers/video/fbdev/sis/sis_main.c u8 reg, v1, v2, v3, v4, v5, v6, v7, v8; v5 4372 drivers/video/fbdev/sis/sis_main.c v4 = 0x44; v5 = 0x42; v5 4375 drivers/video/fbdev/sis/sis_main.c v4 = 0x68; v5 = 0x43; /* Assume 125Mhz ECLK */ v5 4384 drivers/video/fbdev/sis/sis_main.c v5 = bios[rindex++]; v5 4392 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x2f, v5); v5 4403 drivers/video/fbdev/sis/sis_main.c v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00; v5 4410 drivers/video/fbdev/sis/sis_main.c v5 = bios[memtype + 32]; v5 4421 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x19, v5); v5 4465 drivers/video/fbdev/sis/sis_main.c v4 = 0x00; v5 = 0x00; v6 = 0x10; v5 4468 drivers/video/fbdev/sis/sis_main.c v5 = bios[0xf6]; v5 4472 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISPART4, 0x0e, v5); v5 5110 drivers/video/fbdev/sis/sis_main.c u8 v1, v2, v3, v4, v5, reg, ramtype; v5 5626 drivers/video/fbdev/sis/sis_main.c v1 = 0x31; v2 = 0x03; v3 = 0x83; v4 = 0x03; v5 = 0x83; v5 5633 drivers/video/fbdev/sis/sis_main.c v5 = bios[index + 3]; v5 5645 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x16, v5); v5 958 security/apparmor/policy_unpack.c if (VERSION_LT(e->version, v5) || VERSION_GT(e->version, v7)) {