v3 19 arch/arm64/lib/xor-neon.c register uint64x2_t v0, v1, v2, v3; v3 27 arch/arm64/lib/xor-neon.c v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); v3 33 arch/arm64/lib/xor-neon.c vst1q_u64(dp1 + 6, v3); v3 47 arch/arm64/lib/xor-neon.c register uint64x2_t v0, v1, v2, v3; v3 55 arch/arm64/lib/xor-neon.c v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); v3 61 arch/arm64/lib/xor-neon.c v3 = veorq_u64(v3, vld1q_u64(dp3 + 6)); v3 67 arch/arm64/lib/xor-neon.c vst1q_u64(dp1 + 6, v3); v3 83 arch/arm64/lib/xor-neon.c register uint64x2_t v0, v1, v2, v3; v3 91 arch/arm64/lib/xor-neon.c v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); v3 97 arch/arm64/lib/xor-neon.c v3 = veorq_u64(v3, vld1q_u64(dp3 + 6)); v3 103 arch/arm64/lib/xor-neon.c v3 = veorq_u64(v3, vld1q_u64(dp4 + 6)); v3 109 arch/arm64/lib/xor-neon.c vst1q_u64(dp1 + 6, v3); v3 128 arch/arm64/lib/xor-neon.c register uint64x2_t v0, v1, v2, v3; v3 136 arch/arm64/lib/xor-neon.c v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); v3 142 arch/arm64/lib/xor-neon.c v3 = veorq_u64(v3, vld1q_u64(dp3 + 6)); v3 148 arch/arm64/lib/xor-neon.c v3 = veorq_u64(v3, vld1q_u64(dp4 + 6)); v3 154 arch/arm64/lib/xor-neon.c v3 = veorq_u64(v3, vld1q_u64(dp5 + 6)); v3 160 arch/arm64/lib/xor-neon.c vst1q_u64(dp1 + 6, v3); v3 75 arch/powerpc/lib/xor_vmx.c DEFINE(v3); v3 81 arch/powerpc/lib/xor_vmx.c LOAD(v3); v3 83 arch/powerpc/lib/xor_vmx.c XOR(v1, v3); v3 88 arch/powerpc/lib/xor_vmx.c v3 += 4; v3 98 arch/powerpc/lib/xor_vmx.c DEFINE(v3); v3 105 arch/powerpc/lib/xor_vmx.c LOAD(v3); v3 108 arch/powerpc/lib/xor_vmx.c XOR(v3, v4); v3 109 arch/powerpc/lib/xor_vmx.c XOR(v1, v3); v3 114 arch/powerpc/lib/xor_vmx.c v3 += 4; v3 125 arch/powerpc/lib/xor_vmx.c DEFINE(v3); v3 133 arch/powerpc/lib/xor_vmx.c LOAD(v3); v3 137 arch/powerpc/lib/xor_vmx.c XOR(v3, v4); v3 139 arch/powerpc/lib/xor_vmx.c XOR(v1, v3); v3 144 arch/powerpc/lib/xor_vmx.c v3 += 4; v3 100 arch/s390/include/asm/vx-insn.h .ifc \vxr,%v3 v3 200 arch/s390/include/asm/vx-insn.h .macro RXB rxb v1 v2=0 v3=0 v4=0 v3 224 arch/s390/include/asm/vx-insn.h .macro MRXB m v1 v2=0 v3=0 v4=0 v3 239 arch/s390/include/asm/vx-insn.h .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0 v3 347 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr v3 348 arch/s390/include/asm/vx-insn.h .word 0xE700 | (r1 << 4) | (v3&15) v3 350 arch/s390/include/asm/vx-insn.h MRXBOPC \m, 0x21, v3 v3 368 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vto v3 370 arch/s390/include/asm/vx-insn.h .word 0xE700 | ((v1&15) << 4) | (v3&15) v3 372 arch/s390/include/asm/vx-insn.h MRXBOPC \hint, 0x36, v1, v3 v3 378 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vto v3 380 arch/s390/include/asm/vx-insn.h .word 0xE700 | ((v1&15) << 4) | (v3&15) v3 382 arch/s390/include/asm/vx-insn.h MRXBOPC \hint, 0x3E, v1, v3 v3 389 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr3 v3 392 arch/s390/include/asm/vx-insn.h .word ((v3&15) << 12) v3 393 arch/s390/include/asm/vx-insn.h MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4 v3 421 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr3 v3 423 arch/s390/include/asm/vx-insn.h .word ((v3&15) << 12) v3 424 arch/s390/include/asm/vx-insn.h MRXBOPC 0, 0x68, v1, v2, v3 v3 431 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr3 v3 433 arch/s390/include/asm/vx-insn.h .word ((v3&15) << 12) v3 434 arch/s390/include/asm/vx-insn.h MRXBOPC 0, 0x6D, v1, v2, v3 v3 441 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr3 v3 443 arch/s390/include/asm/vx-insn.h .word ((v3&15) << 12) v3 444 arch/s390/include/asm/vx-insn.h MRXBOPC \m4, 0xB4, v1, v2, v3 v3 463 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr3 v3 466 arch/s390/include/asm/vx-insn.h .word ((v3&15) << 12) | (\m5 << 8) v3 467 arch/s390/include/asm/vx-insn.h MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4 v3 486 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr3 v3 488 arch/s390/include/asm/vx-insn.h .word ((v3&15) << 12) v3 489 arch/s390/include/asm/vx-insn.h MRXBOPC 0, 0x7D, v1, v2, v3 v3 516 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr3 v3 518 arch/s390/include/asm/vx-insn.h .word ((v3&15) << 12) v3 519 arch/s390/include/asm/vx-insn.h MRXBOPC \m4, 0xF3, v1, v2, v3 v3 541 arch/s390/include/asm/vx-insn.h VX_NUM v3, \vr3 v3 543 arch/s390/include/asm/vx-insn.h .word ((v3&15) << 12) v3 544 arch/s390/include/asm/vx-insn.h MRXBOPC \m4, 0x7A, v1, v2, v3 v3 114 arch/um/drivers/cow_user.c struct cow_header_v3 v3; v3 337 arch/um/drivers/cow_user.c else if (version == 3 && (*((int*)header->v3.backing_file) != 0)) { v3 338 arch/um/drivers/cow_user.c if (n < sizeof(header->v3)) { v3 343 arch/um/drivers/cow_user.c *mtime_out = be32toh(header->v3.mtime); v3 344 arch/um/drivers/cow_user.c *size_out = be64toh(header->v3.size); v3 345 arch/um/drivers/cow_user.c *sectorsize_out = be32toh(header->v3.sectorsize); v3 346 arch/um/drivers/cow_user.c *align_out = be32toh(header->v3.alignment); v3 351 arch/um/drivers/cow_user.c *bitmap_offset_out = ROUND_UP(sizeof(header->v3), *align_out); v3 352 arch/um/drivers/cow_user.c file = header->v3.backing_file; v3 89 drivers/char/mwave/mwavedd.h #define PRINTK_4(f,s,v1,v2,v3) \ v3 91 drivers/char/mwave/mwavedd.h printk(s,v1,v2,v3); \ v3 94 drivers/char/mwave/mwavedd.h #define PRINTK_5(f,s,v1,v2,v3,v4) \ v3 96 drivers/char/mwave/mwavedd.h printk(s,v1,v2,v3,v4); \ v3 99 drivers/char/mwave/mwavedd.h #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ v3 101 drivers/char/mwave/mwavedd.h printk(s,v1,v2,v3,v4,v5); \ v3 104 drivers/char/mwave/mwavedd.h #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ v3 106 drivers/char/mwave/mwavedd.h printk(s,v1,v2,v3,v4,v5,v6); \ v3 109 drivers/char/mwave/mwavedd.h #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ v3 111 drivers/char/mwave/mwavedd.h printk(s,v1,v2,v3,v4,v5,v6,v7); \ v3 118 drivers/char/mwave/mwavedd.h #define PRINTK_4(f,s,v1,v2,v3) v3 119 drivers/char/mwave/mwavedd.h #define PRINTK_5(f,s,v1,v2,v3,v4) v3 120 drivers/char/mwave/mwavedd.h #define PRINTK_6(f,s,v1,v2,v3,v4,v5) v3 121 drivers/char/mwave/mwavedd.h #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) v3 122 drivers/char/mwave/mwavedd.h #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) v3 42 drivers/clocksource/acpi_pm.c u32 v1 = 0, v2 = 0, v3 = 0; v3 53 drivers/clocksource/acpi_pm.c v3 = read_pmtmr(); v3 54 drivers/clocksource/acpi_pm.c } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1) v3 55 drivers/clocksource/acpi_pm.c || (v3 > v1 && v3 < v2))); v3 39 drivers/clocksource/h8300_timer16.c unsigned short v1, v2, v3; v3 49 drivers/clocksource/h8300_timer16.c v3 = ioread16be(p->mapbase + TCNT); v3 51 drivers/clocksource/h8300_timer16.c } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) v3 52 drivers/clocksource/h8300_timer16.c || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); v3 44 drivers/clocksource/h8300_tpu.c unsigned long v1, v2, v3; v3 54 drivers/clocksource/h8300_tpu.c v3 = read_tcnt32(p); v3 56 drivers/clocksource/h8300_tpu.c } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) v3 57 drivers/clocksource/h8300_tpu.c || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); v3 277 drivers/clocksource/sh_cmt.c u32 v1, v2, v3; v3 287 drivers/clocksource/sh_cmt.c v3 = sh_cmt_read_cmcnt(ch); v3 289 drivers/clocksource/sh_cmt.c } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) v3 290 drivers/clocksource/sh_cmt.c || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); v3 119 drivers/dma/fsl-edma-common.c if (fsl_chan->edma->drvdata->version == v3) v3 237 drivers/dma/fsl-edma.c .version = v3, v3 877 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; v3 955 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if ((ss_assign->v3.ucClockIndication == id) && v3 956 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { v3 958 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); v3 959 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c ss->type = ss_assign->v3.ucSpreadSpectrumMode; v3 960 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); v3 961 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if (ss_assign->v3.ucSpreadSpectrumMode & v3 989 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; v3 1019 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); v3 1023 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->post_div = args.v3.ucPostDiv; v3 1024 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->enable_post_div = (args.v3.ucCntlFlag & v3 1026 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->enable_dithen = (args.v3.ucCntlFlag & v3 1028 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); v3 1029 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); v3 1030 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->ref_div = args.v3.ucRefDiv; v3 1031 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->vco_mode = (args.v3.ucCntlFlag & v3 1186 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; v3 1212 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v3.ucVoltageType = voltage_type; v3 1213 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; v3 1214 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v3.usVoltageLevel = cpu_to_le16(voltage_id); v3 1218 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c *voltage = le16_to_cpu(args.v3.usVoltageLevel); v3 1248 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v3.ucVoltageType = 0; v3 1249 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; v3 1250 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c args.v3.usVoltageLevel = 0; v3 1254 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); v3 1389 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; v3 1395 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c union _ATOM_VOLTAGE_OBJECT_V3 v3; v3 1399 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, v3 1402 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c u32 size = le16_to_cpu(v3->sHeader.usStructureSize); v3 1404 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c u8 *start = (u8*)v3; v3 1436 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, v3 1440 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; v3 1441 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; v3 1478 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, v3 1517 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, v3 1521 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c &voltage_object->v3.asGpioVoltageObj; v3 238 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; v3 278 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); v3 279 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; v3 282 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; v3 285 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; v3 288 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; v3 293 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); v3 294 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); v3 295 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucEnable = enable; v3 302 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; v3 403 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); v3 404 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id; v3 405 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucEncodeMode = encoder_mode; v3 406 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucDispPllConfig = 0; v3 408 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucDispPllConfig |= v3 411 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucDispPllConfig |= v3 414 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); v3 418 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucDispPllConfig |= v3 421 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucDispPllConfig |= v3 426 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucExtTransmitterID = v3 429 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.sInput.ucExtTransmitterID = 0; v3 433 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; v3 434 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c if (args.v3.sOutput.ucRefDiv) { v3 437 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; v3 439 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c if (args.v3.sOutput.ucPostDiv) { v3 442 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; v3 462 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c PIXEL_CLOCK_PARAMETERS_V3 v3; v3 628 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.usPixelClock = cpu_to_le16(clock / 10); v3 629 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.usRefDiv = cpu_to_le16(ref_div); v3 630 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.usFbDiv = cpu_to_le16(fb_div); v3 631 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucFracFbDiv = frac_fb_div; v3 632 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucPostDiv = post_div; v3 633 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucPpll = pll_id; v3 635 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; v3 637 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; v3 639 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; v3 640 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucTransmitterId = encoder_id; v3 641 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucEncoderMode = encoder_mode; v3 566 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; v3 613 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucPanelMode = panel_mode; v3 645 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucAction = action; v3 646 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); v3 648 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucPanelMode = panel_mode; v3 650 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); v3 652 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) v3 653 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucLaneNum = dp_lane_count; v3 655 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucLaneNum = 8; v3 657 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucLaneNum = 4; v3 659 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) v3 661 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.ucDigSel = dig->dig_encoder; v3 662 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder); v3 754 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; v3 937 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucAction = action; v3 939 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.usInitInfo = cpu_to_le16(connector_object_id); v3 941 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.asMode.ucLaneSel = lane_num; v3 942 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.asMode.ucLaneSet = lane_set; v3 945 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); v3 947 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10); v3 949 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); v3 953 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucLaneNum = dp_lane_count; v3 955 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucLaneNum = 8; v3 957 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucLaneNum = 4; v3 960 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.ucLinkSel = 1; v3 962 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.ucEncoderSel = 1; v3 970 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.ucRefClkSource = 2; /* external src */ v3 972 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.ucRefClkSource = pll_id; v3 976 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.ucTransmitterSel = 0; v3 979 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.ucTransmitterSel = 1; v3 982 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.ucTransmitterSel = 2; v3 987 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ v3 990 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.fCoherentMode = 1; v3 992 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.acConfig.fDualLinkConnector = 1; v3 1219 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; v3 1284 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucAction = action; v3 1286 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); v3 1288 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); v3 1289 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucEncoderMode = v3 1292 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { v3 1294 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; v3 1296 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; v3 1297 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucLaneNum = dp_lane_count; v3 1299 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucLaneNum = 8; v3 1301 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucLaneNum = 4; v3 1304 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; v3 1307 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; v3 1310 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; v3 1313 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.sExtEncoder.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder); v3 1462 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c SELECT_CRTC_SOURCE_PARAMETERS_V3 v3; v3 1594 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucCRTC = amdgpu_crtc->crtc_id; v3 1609 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucDstBpc = amdgpu_atombios_encoder_get_bpc(encoder); v3 1619 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; v3 1622 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; v3 1625 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; v3 1628 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; v3 1631 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; v3 1634 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; v3 1637 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; v3 1642 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; v3 1646 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; v3 1648 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; v3 1650 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; v3 1654 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; v3 1656 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; v3 1658 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.v3.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; v3 96 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c float dcn_bw_max3(float v1, float v2, float v3) v3 98 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2); v3 101 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) v3 103 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5); v3 56 drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h struct bw_fixed v3) v3 58 drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h return bw_min2(bw_min2(v1, v2), v3); v3 63 drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h struct bw_fixed v3) v3 65 drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h return bw_max2(bw_max2(v1, v2), v3); v3 37 drivers/gpu/drm/amd/display/dc/inc/dcn_calc_math.h float dcn_bw_max3(float v1, float v2, float v3); v3 38 drivers/gpu/drm/amd/display/dc/inc/dcn_calc_math.h float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5); v3 72 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ v3 76 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3) v3 78 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ v3 82 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ v3 85 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ v3 90 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ v3 94 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ v3 99 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ v3 104 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ v3 109 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ v3 115 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ v3 120 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ v3 127 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ v3 132 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 140 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ v3 145 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 165 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \ v3 169 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3) v3 171 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ v3 175 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ v3 178 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ v3 182 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ v3 186 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ v3 190 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ v3 195 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ v3 199 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ v3 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ v3 209 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ v3 239 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ v3 243 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3) v3 245 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ v3 249 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 252 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ v3 256 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 260 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ v3 264 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 269 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ v3 273 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ v3 283 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ v3 294 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ v3 306 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v3 320 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v3 338 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v3 361 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ v3 386 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \ v3 389 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET(reg, val, f3, v3); } v3 44 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; v3 213 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c return (ATOM_VOLTAGE_OBJECT_INFO *) &(voltage_info->v3); v3 395 drivers/gpu/drm/i915/intel_csr.c const struct intel_dmc_header_v3 *v3 = v3 401 drivers/gpu/drm/i915/intel_csr.c mmioaddr = v3->mmioaddr; v3 402 drivers/gpu/drm/i915/intel_csr.c mmiodata = v3->mmiodata; v3 403 drivers/gpu/drm/i915/intel_csr.c mmio_count = v3->mmio_count; v3 407 drivers/gpu/drm/i915/intel_csr.c dmc_header_size = sizeof(*v3); v3 441 drivers/gpu/drm/radeon/atombios_crtc.c ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; v3 482 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); v3 483 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; v3 486 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; v3 489 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; v3 492 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; v3 497 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); v3 498 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); v3 499 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucEnable = enable; v3 555 drivers/gpu/drm/radeon/atombios_crtc.c ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; v3 707 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); v3 708 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; v3 709 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucEncodeMode = encoder_mode; v3 710 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucDispPllConfig = 0; v3 712 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucDispPllConfig |= v3 715 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucDispPllConfig |= v3 718 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); v3 722 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucDispPllConfig |= v3 725 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucDispPllConfig |= v3 730 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucExtTransmitterID = v3 733 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.sInput.ucExtTransmitterID = 0; v3 737 drivers/gpu/drm/radeon/atombios_crtc.c adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; v3 738 drivers/gpu/drm/radeon/atombios_crtc.c if (args.v3.sOutput.ucRefDiv) { v3 741 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; v3 743 drivers/gpu/drm/radeon/atombios_crtc.c if (args.v3.sOutput.ucPostDiv) { v3 746 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; v3 766 drivers/gpu/drm/radeon/atombios_crtc.c PIXEL_CLOCK_PARAMETERS_V3 v3; v3 875 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.usPixelClock = cpu_to_le16(clock / 10); v3 876 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.usRefDiv = cpu_to_le16(ref_div); v3 877 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.usFbDiv = cpu_to_le16(fb_div); v3 878 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucFracFbDiv = frac_fb_div; v3 879 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucPostDiv = post_div; v3 880 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucPpll = pll_id; v3 882 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; v3 884 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; v3 886 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; v3 887 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucTransmitterId = encoder_id; v3 888 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucEncoderMode = encoder_mode; v3 841 drivers/gpu/drm/radeon/atombios_encoders.c DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; v3 895 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucPanelMode = panel_mode; v3 929 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucAction = action; v3 930 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); v3 932 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucPanelMode = panel_mode; v3 934 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); v3 936 drivers/gpu/drm/radeon/atombios_encoders.c if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) v3 937 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucLaneNum = dp_lane_count; v3 939 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucLaneNum = 8; v3 941 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucLaneNum = 4; v3 943 drivers/gpu/drm/radeon/atombios_encoders.c if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) v3 946 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucDigSel = enc_override; v3 948 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucDigSel = dig->dig_encoder; v3 949 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); v3 1010 drivers/gpu/drm/radeon/atombios_encoders.c DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; v3 1192 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucAction = action; v3 1194 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.usInitInfo = cpu_to_le16(connector_object_id); v3 1196 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.asMode.ucLaneSel = lane_num; v3 1197 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.asMode.ucLaneSet = lane_set; v3 1200 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); v3 1202 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); v3 1204 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); v3 1208 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucLaneNum = dp_lane_count; v3 1210 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucLaneNum = 8; v3 1212 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.ucLaneNum = 4; v3 1215 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucLinkSel = 1; v3 1217 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucEncoderSel = 1; v3 1225 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucRefClkSource = 2; /* external src */ v3 1227 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucRefClkSource = pll_id; v3 1231 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucTransmitterSel = 0; v3 1234 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucTransmitterSel = 1; v3 1237 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.ucTransmitterSel = 2; v3 1242 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ v3 1245 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.fCoherentMode = 1; v3 1247 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.acConfig.fDualLinkConnector = 1; v3 1434 drivers/gpu/drm/radeon/atombios_encoders.c EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; v3 1498 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucAction = action; v3 1500 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); v3 1502 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); v3 1503 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); v3 1505 drivers/gpu/drm/radeon/atombios_encoders.c if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { v3 1507 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; v3 1509 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; v3 1510 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucLaneNum = dp_lane_count; v3 1512 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucLaneNum = 8; v3 1514 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucLaneNum = 4; v3 1517 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; v3 1520 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; v3 1523 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; v3 1526 drivers/gpu/drm/radeon/atombios_encoders.c args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); v3 1515 drivers/gpu/drm/radeon/radeon_atombios.c struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; v3 1593 drivers/gpu/drm/radeon/radeon_atombios.c if ((ss_assign->v3.ucClockIndication == id) && v3 1594 drivers/gpu/drm/radeon/radeon_atombios.c (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { v3 1596 drivers/gpu/drm/radeon/radeon_atombios.c le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); v3 1597 drivers/gpu/drm/radeon/radeon_atombios.c ss->type = ss_assign->v3.ucSpreadSpectrumMode; v3 1598 drivers/gpu/drm/radeon/radeon_atombios.c ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); v3 1599 drivers/gpu/drm/radeon/radeon_atombios.c if (ss_assign->v3.ucSpreadSpectrumMode & v3 2830 drivers/gpu/drm/radeon/radeon_atombios.c struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; v3 2886 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); v3 2890 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_div = args.v3.ucPostDiv; v3 2891 drivers/gpu/drm/radeon/radeon_atombios.c dividers->enable_post_div = (args.v3.ucCntlFlag & v3 2893 drivers/gpu/drm/radeon/radeon_atombios.c dividers->enable_dithen = (args.v3.ucCntlFlag & v3 2895 drivers/gpu/drm/radeon/radeon_atombios.c dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); v3 2896 drivers/gpu/drm/radeon/radeon_atombios.c dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); v3 2897 drivers/gpu/drm/radeon/radeon_atombios.c dividers->ref_div = args.v3.ucRefDiv; v3 2898 drivers/gpu/drm/radeon/radeon_atombios.c dividers->vco_mode = (args.v3.ucCntlFlag & v3 3104 drivers/gpu/drm/radeon/radeon_atombios.c struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; v3 3132 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.ucVoltageType = voltage_type; v3 3133 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; v3 3134 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.usVoltageLevel = cpu_to_le16(voltage_level); v3 3167 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.ucVoltageType = voltage_type; v3 3168 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; v3 3169 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.usVoltageLevel = cpu_to_le16(voltage_id); v3 3173 drivers/gpu/drm/radeon/radeon_atombios.c *voltage = le16_to_cpu(args.v3.usVoltageLevel); v3 3203 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.ucVoltageType = 0; v3 3204 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; v3 3205 drivers/gpu/drm/radeon/radeon_atombios.c args.v3.usVoltageLevel = 0; v3 3209 drivers/gpu/drm/radeon/radeon_atombios.c *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); v3 3383 drivers/gpu/drm/radeon/radeon_atombios.c struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; v3 3389 drivers/gpu/drm/radeon/radeon_atombios.c union _ATOM_VOLTAGE_OBJECT_V3 v3; v3 3426 drivers/gpu/drm/radeon/radeon_atombios.c static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, v3 3429 drivers/gpu/drm/radeon/radeon_atombios.c u32 size = le16_to_cpu(v3->sHeader.usStructureSize); v3 3431 drivers/gpu/drm/radeon/radeon_atombios.c u8 *start = (u8*)v3; v3 3484 drivers/gpu/drm/radeon/radeon_atombios.c if (atom_lookup_voltage_object_v3(&voltage_info->v3, v3 3522 drivers/gpu/drm/radeon/radeon_atombios.c atom_lookup_voltage_object_v3(&voltage_info->v3, v3 3526 drivers/gpu/drm/radeon/radeon_atombios.c *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; v3 3527 drivers/gpu/drm/radeon/radeon_atombios.c *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; v3 3781 drivers/gpu/drm/radeon/radeon_atombios.c atom_lookup_voltage_object_v3(&voltage_info->v3, v3 3785 drivers/gpu/drm/radeon/radeon_atombios.c &voltage_object->v3.asGpioVoltageObj; v3 101 drivers/net/ethernet/chelsio/cxgb3/mc5.c u32 v3) v3 105 drivers/net/ethernet/chelsio/cxgb3/mc5.c t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3); v3 418 drivers/net/wireless/broadcom/b43legacy/main.c u16 v3; v3 424 drivers/net/wireless/broadcom/b43legacy/main.c v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3); v3 432 drivers/net/wireless/broadcom/b43legacy/main.c } while (v3 != test3 || v2 != test2 || v1 != test1); v3 434 drivers/net/wireless/broadcom/b43legacy/main.c *tsf = v3; v3 483 drivers/net/wireless/broadcom/b43legacy/main.c u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; v3 486 drivers/net/wireless/broadcom/b43legacy/main.c b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3); v3 1759 drivers/net/wireless/broadcom/b43legacy/phy.c s8 v3; v3 1787 drivers/net/wireless/broadcom/b43legacy/phy.c v3 = (s8)((tmp & 0xFF00) >> 8); v3 1790 drivers/net/wireless/broadcom/b43legacy/phy.c if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) { v3 1798 drivers/net/wireless/broadcom/b43legacy/phy.c v3 = (s8)((tmp & 0xFF00) >> 8); v3 1799 drivers/net/wireless/broadcom/b43legacy/phy.c if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) v3 1804 drivers/net/wireless/broadcom/b43legacy/phy.c v3 = (v3 + 0x20) & 0x3F; v3 1809 drivers/net/wireless/broadcom/b43legacy/phy.c average = (v0 + v1 + v2 + v3 + 2) / 4; v3 21255 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 v0 = 0x211, v1 = 0x222, v2 = 0x144, v3 = 0x188; v3 21268 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 1, 0x0C, 16, &v3); v3 21279 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 1, 0x1C, 16, &v3); v3 366 drivers/net/wireless/intel/iwlwifi/fw/api/power.h struct iwl_dev_tx_power_cmd_v3 v3; v3 386 drivers/net/wireless/intel/iwlwifi/fw/api/power.h struct iwl_dev_tx_power_cmd_v3 v3; v3 685 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h struct iwl_rx_mpdu_desc_v3 v3; v3 856 drivers/net/wireless/intel/iwlwifi/mvm/fw.c cmd.v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS); v3 865 drivers/net/wireless/intel/iwlwifi/mvm/fw.c len = sizeof(cmd.v4.v3); v3 895 drivers/net/wireless/intel/iwlwifi/mvm/fw.c cmd.v5.v3.per_chain_restriction[i][j] = v3 1286 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_MAC), v3 1287 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .v5.v3.mac_context_id = v3 1289 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .v5.v3.pwr_restriction = cpu_to_le16(8 * tx_power), v3 1293 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c cmd.v5.v3.pwr_restriction = cpu_to_le16(IWL_DEV_MAX_TX_POWER); v3 1302 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c len = sizeof(cmd.v4.v3); v3 1572 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c rate_n_flags = le32_to_cpu(desc->v3.rate_n_flags); v3 1573 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c channel = desc->v3.channel; v3 1574 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c gp2_on_air_rise = le32_to_cpu(desc->v3.gp2_on_air_rise); v3 1575 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c energy_a = desc->v3.energy_a; v3 1576 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c energy_b = desc->v3.energy_b; v3 1579 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c phy_data.d0 = desc->v3.phy_data0; v3 1580 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c phy_data.d1 = desc->v3.phy_data1; v3 1581 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c phy_data.d2 = desc->v3.phy_data2; v3 1582 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c phy_data.d3 = desc->v3.phy_data3; v3 1674 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c tsf_on_air_rise = le64_to_cpu(desc->v3.tsf_on_air_rise); v3 51 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c mt76x02_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4) v3 57 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v3 & (BIT(6) - 1)) << 16; v3 652 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c u32 v1 = 0, v2 = 0, v3 = 0; v3 661 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c v3 = phy_reg_page[i+2]; v3 692 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c v3 = phy_reg_page[i+2]; v3 698 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c v3 = phy_reg_page[i+2]; v3 873 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; v3 882 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c v3 = phy_regarray_table_pg[i+2]; v3 888 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c _rtl92ee_store_tx_power_by_rate(hw, v1, v2, v3, v3 714 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; v3 723 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c v3 = phy_regarray_table_pg[i+2]; v3 734 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c v1, v2, v3, v4, v5, v6); v3 2009 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u32 v1, v2, v3, v4, v5, v6; v3 2027 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c v3 = array[i+2]; v3 2053 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3, v3 2062 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c v3 = array[i+2]; v3 2067 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c v3 = array[i+2]; v3 318 drivers/pci/controller/pci-v3-semi.c struct v3_pci *v3 = bus->sysdata; v3 370 drivers/pci/controller/pci-v3-semi.c writel(v3_addr_to_lb_base(v3->non_pre_mem) | v3 372 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE0); v3 378 drivers/pci/controller/pci-v3-semi.c writel(v3_addr_to_lb_base(v3->config_mem) | v3 380 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE1); v3 381 drivers/pci/controller/pci-v3-semi.c writew(mapaddress, v3->base + V3_LB_MAP1); v3 383 drivers/pci/controller/pci-v3-semi.c return v3->config_base + address + offset; v3 386 drivers/pci/controller/pci-v3-semi.c static void v3_unmap_bus(struct v3_pci *v3) v3 391 drivers/pci/controller/pci-v3-semi.c writel(v3_addr_to_lb_base(v3->pre_mem) | v3 394 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE1); v3 395 drivers/pci/controller/pci-v3-semi.c writew(v3_addr_to_lb_map(v3->pre_bus_addr) | v3 397 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_MAP1); v3 402 drivers/pci/controller/pci-v3-semi.c writel(v3_addr_to_lb_base(v3->non_pre_mem) | v3 404 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE0); v3 410 drivers/pci/controller/pci-v3-semi.c struct v3_pci *v3 = bus->sysdata; v3 417 drivers/pci/controller/pci-v3-semi.c v3_unmap_bus(v3); v3 424 drivers/pci/controller/pci-v3-semi.c struct v3_pci *v3 = bus->sysdata; v3 431 drivers/pci/controller/pci-v3-semi.c v3_unmap_bus(v3); v3 443 drivers/pci/controller/pci-v3-semi.c struct v3_pci *v3 = data; v3 444 drivers/pci/controller/pci-v3-semi.c struct device *dev = v3->dev; v3 447 drivers/pci/controller/pci-v3-semi.c status = readw(v3->base + V3_PCI_STAT); v3 456 drivers/pci/controller/pci-v3-semi.c writew(status, v3->base + V3_PCI_STAT); v3 458 drivers/pci/controller/pci-v3-semi.c status = readb(v3->base + V3_LB_ISTAT); v3 476 drivers/pci/controller/pci-v3-semi.c writeb(0, v3->base + V3_LB_ISTAT); v3 477 drivers/pci/controller/pci-v3-semi.c if (v3->map) v3 478 drivers/pci/controller/pci-v3-semi.c regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, v3 485 drivers/pci/controller/pci-v3-semi.c static int v3_integrator_init(struct v3_pci *v3) v3 489 drivers/pci/controller/pci-v3-semi.c v3->map = v3 491 drivers/pci/controller/pci-v3-semi.c if (IS_ERR(v3->map)) { v3 492 drivers/pci/controller/pci-v3-semi.c dev_err(v3->dev, "no syscon\n"); v3 496 drivers/pci/controller/pci-v3-semi.c regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val); v3 498 drivers/pci/controller/pci-v3-semi.c regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, v3 507 drivers/pci/controller/pci-v3-semi.c writel(0x6200, v3->base + V3_LB_IO_BASE); v3 511 drivers/pci/controller/pci-v3-semi.c writeb(0xaa, v3->base + V3_MAIL_DATA); v3 512 drivers/pci/controller/pci-v3-semi.c writeb(0x55, v3->base + V3_MAIL_DATA + 4); v3 513 drivers/pci/controller/pci-v3-semi.c } while (readb(v3->base + V3_MAIL_DATA) != 0xaa && v3 514 drivers/pci/controller/pci-v3-semi.c readb(v3->base + V3_MAIL_DATA) != 0x55); v3 517 drivers/pci/controller/pci-v3-semi.c dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n"); v3 522 drivers/pci/controller/pci-v3-semi.c static int v3_pci_setup_resource(struct v3_pci *v3, v3 527 drivers/pci/controller/pci-v3-semi.c struct device *dev = v3->dev; v3 536 drivers/pci/controller/pci-v3-semi.c v3->io_mem = io_base; v3 537 drivers/pci/controller/pci-v3-semi.c v3->io_bus_addr = io->start - win->offset; v3 539 drivers/pci/controller/pci-v3-semi.c io, &v3->io_bus_addr); v3 548 drivers/pci/controller/pci-v3-semi.c writel(v3_addr_to_lb_base2(v3->io_mem) | v3 550 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE2); v3 551 drivers/pci/controller/pci-v3-semi.c writew(v3_addr_to_lb_map2(v3->io_bus_addr), v3 552 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_MAP2); v3 558 drivers/pci/controller/pci-v3-semi.c v3->pre_mem = mem->start; v3 559 drivers/pci/controller/pci-v3-semi.c v3->pre_bus_addr = mem->start - win->offset; v3 561 drivers/pci/controller/pci-v3-semi.c mem, &v3->pre_bus_addr); v3 566 drivers/pci/controller/pci-v3-semi.c if (v3->non_pre_mem && v3 567 drivers/pci/controller/pci-v3-semi.c (mem->start != v3->non_pre_mem + SZ_256M)) { v3 573 drivers/pci/controller/pci-v3-semi.c writel(v3_addr_to_lb_base(v3->pre_mem) | v3 577 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE1); v3 578 drivers/pci/controller/pci-v3-semi.c writew(v3_addr_to_lb_map(v3->pre_bus_addr) | v3 580 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_MAP1); v3 583 drivers/pci/controller/pci-v3-semi.c v3->non_pre_mem = mem->start; v3 584 drivers/pci/controller/pci-v3-semi.c v3->non_pre_bus_addr = mem->start - win->offset; v3 586 drivers/pci/controller/pci-v3-semi.c mem, &v3->non_pre_bus_addr); v3 593 drivers/pci/controller/pci-v3-semi.c writel(v3_addr_to_lb_base(v3->non_pre_mem) | v3 596 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE0); v3 597 drivers/pci/controller/pci-v3-semi.c writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) | v3 599 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_MAP0); v3 615 drivers/pci/controller/pci-v3-semi.c static int v3_get_dma_range_config(struct v3_pci *v3, v3 619 drivers/pci/controller/pci-v3-semi.c struct device *dev = v3->dev; v3 675 drivers/pci/controller/pci-v3-semi.c dev_err(v3->dev, "illegal dma memory chunk size\n"); v3 692 drivers/pci/controller/pci-v3-semi.c static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3, v3 697 drivers/pci/controller/pci-v3-semi.c struct device *dev = v3->dev; v3 712 drivers/pci/controller/pci-v3-semi.c ret = v3_get_dma_range_config(v3, &range, &pci_base, &pci_map); v3 717 drivers/pci/controller/pci-v3-semi.c writel(pci_base, v3->base + V3_PCI_BASE0); v3 718 drivers/pci/controller/pci-v3-semi.c writel(pci_map, v3->base + V3_PCI_MAP0); v3 720 drivers/pci/controller/pci-v3-semi.c writel(pci_base, v3->base + V3_PCI_BASE1); v3 721 drivers/pci/controller/pci-v3-semi.c writel(pci_map, v3->base + V3_PCI_MAP1); v3 738 drivers/pci/controller/pci-v3-semi.c struct v3_pci *v3; v3 746 drivers/pci/controller/pci-v3-semi.c host = pci_alloc_host_bridge(sizeof(*v3)); v3 756 drivers/pci/controller/pci-v3-semi.c v3 = pci_host_bridge_priv(host); v3 757 drivers/pci/controller/pci-v3-semi.c host->sysdata = v3; v3 758 drivers/pci/controller/pci-v3-semi.c v3->dev = dev; v3 773 drivers/pci/controller/pci-v3-semi.c v3->base = devm_ioremap_resource(dev, regs); v3 774 drivers/pci/controller/pci-v3-semi.c if (IS_ERR(v3->base)) v3 775 drivers/pci/controller/pci-v3-semi.c return PTR_ERR(v3->base); v3 781 drivers/pci/controller/pci-v3-semi.c if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) v3 783 drivers/pci/controller/pci-v3-semi.c readl(v3->base + V3_LB_IO_BASE), regs); v3 791 drivers/pci/controller/pci-v3-semi.c v3->config_mem = regs->start; v3 792 drivers/pci/controller/pci-v3-semi.c v3->config_base = devm_ioremap_resource(dev, regs); v3 793 drivers/pci/controller/pci-v3-semi.c if (IS_ERR(v3->config_base)) v3 794 drivers/pci/controller/pci-v3-semi.c return PTR_ERR(v3->config_base); v3 812 drivers/pci/controller/pci-v3-semi.c "PCIv3 error", v3); v3 823 drivers/pci/controller/pci-v3-semi.c if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) v3 824 drivers/pci/controller/pci-v3-semi.c writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); v3 827 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); v3 829 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); v3 832 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); v3 834 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); v3 837 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CFG); v3 839 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CFG); v3 842 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_LB_CFG); v3 847 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_LB_CFG); v3 850 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); v3 852 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); v3 856 drivers/pci/controller/pci-v3-semi.c ret = v3_pci_setup_resource(v3, io_base, host, win); v3 862 drivers/pci/controller/pci-v3-semi.c ret = v3_pci_parse_map_dma_ranges(v3, np); v3 871 drivers/pci/controller/pci-v3-semi.c writel(0x00000000, v3->base + V3_PCI_IO_BASE); v3 879 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CFG); v3 890 drivers/pci/controller/pci-v3-semi.c v3->base + V3_FIFO_PRIORITY); v3 897 drivers/pci/controller/pci-v3-semi.c writeb(0, v3->base + V3_LB_ISTAT); v3 898 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_LB_CFG); v3 900 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_LB_CFG); v3 902 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_IMASK); v3 906 drivers/pci/controller/pci-v3-semi.c ret = v3_integrator_init(v3); v3 912 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); v3 914 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); v3 917 drivers/pci/controller/pci-v3-semi.c writeb(0, v3->base + V3_LB_ISTAT); v3 920 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_IMASK); v3 923 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); v3 925 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); v3 930 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); v3 932 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); v3 940 drivers/pci/controller/pci-v3-semi.c v3->bus = host->bus; v3 942 drivers/pci/controller/pci-v3-semi.c pci_bus_assign_resources(v3->bus); v3 943 drivers/pci/controller/pci-v3-semi.c pci_bus_add_devices(v3->bus); v3 569 drivers/staging/rtl8188eu/hal/bb_cfg.c u32 v3 = array[i + 2]; v3 572 drivers/staging/rtl8188eu/hal/bb_cfg.c rtl_addr_delay(adapt, v1, v2, v3); v3 627 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c u32 v3 = Array[i+2]; v3 632 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c odm_ConfigBB_PHY_REG_PG_8723B(pDM_Odm, v1, v2, v3, v4, v5, v6); v3 4351 drivers/video/fbdev/sis/sis_main.c u8 reg, v1, v2, v3, v4, v5, v6, v7, v8; v3 4369 drivers/video/fbdev/sis/sis_main.c v3 = 0x80; v6 = 0x80; v3 4381 drivers/video/fbdev/sis/sis_main.c v3 = bios[rindex++]; v3 4390 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x2a, v3); v3 4402 drivers/video/fbdev/sis/sis_main.c v1 = 0x01; v2 = 0x43; v3 = 0x1e; v4 = 0x2a; v3 4408 drivers/video/fbdev/sis/sis_main.c v3 = bios[memtype + 16]; v3 4416 drivers/video/fbdev/sis/sis_main.c v3 &= 0xfd; v3 4419 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x17, v3); v3 4437 drivers/video/fbdev/sis/sis_main.c v1 = 0xf6; v2 = 0x0d; v3 = 0x00; v3 4441 drivers/video/fbdev/sis/sis_main.c v3 = bios[0xea]; v3 4445 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x25, v3); v3 4885 drivers/video/fbdev/sis/sis_main.c u8 v1, v2, v3; v3 4911 drivers/video/fbdev/sis/sis_main.c v1 = cs90[index]; v2 = cs90[index + 1]; v3 = cs90[index + 2]; v3 4915 drivers/video/fbdev/sis/sis_main.c v3 = ivideo->bios_abase[0x90 + index + 2]; v3 4919 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x2a, v3); v3 4924 drivers/video/fbdev/sis/sis_main.c v1 = csb8[index]; v2 = csb8[index + 1]; v3 = csb8[index + 2]; v3 4928 drivers/video/fbdev/sis/sis_main.c v3 = ivideo->bios_abase[0xb8 + index + 2]; v3 4932 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x30, v3); v3 5035 drivers/video/fbdev/sis/sis_main.c u8 v3; v3 5043 drivers/video/fbdev/sis/sis_main.c v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb]; v3 5047 drivers/video/fbdev/sis/sis_main.c v3 = bios[regb + 0x158]; v3 5056 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, 0x82, v3); v3 5110 drivers/video/fbdev/sis/sis_main.c u8 v1, v2, v3, v4, v5, reg, ramtype; v3 5503 drivers/video/fbdev/sis/sis_main.c v1 = 0xb5; v2 = 0x20; v3 = 0xf0; v4 = 0x13; v3 5507 drivers/video/fbdev/sis/sis_main.c v3 = bios[0x120 + regb]; v3 5523 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, 0x59, v3); v3 5570 drivers/video/fbdev/sis/sis_main.c v1 = cs158[regb]; v2 = cs160[regb]; v3 = cs168[regb]; v3 5574 drivers/video/fbdev/sis/sis_main.c v3 = bios[regb + 0x168]; v3 5578 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, 0x86, v3); v3 5626 drivers/video/fbdev/sis/sis_main.c v1 = 0x31; v2 = 0x03; v3 = 0x83; v4 = 0x03; v5 = 0x83; v3 5631 drivers/video/fbdev/sis/sis_main.c v3 = bios[index + 1]; v3 5638 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x16, v3); v3 93 fs/adfs/super.c unsigned int v0, v1, v2, v3; v3 96 fs/adfs/super.c v0 = v1 = v2 = v3 = 0; v3 98 fs/adfs/super.c v0 += map[i] + (v3 >> 8); v3 99 fs/adfs/super.c v3 &= 0xff; v3 104 fs/adfs/super.c v3 += map[i + 3] + (v2 >> 8); v3 107 fs/adfs/super.c v0 += v3 >> 8; v3 110 fs/adfs/super.c v3 += map[3] + (v2 >> 8); v3 112 fs/adfs/super.c return v0 ^ v1 ^ v2 ^ v3; v3 921 fs/ntfs/layout.h } __attribute__ ((__packed__)) v3; v3 151 include/linux/xxhash.h uint32_t v3; v3 164 include/linux/xxhash.h uint64_t v3; v3 34 include/pcmcia/device_id.h #define PCMCIA_DEVICE_PROD_ID3(v3, vh3) { \ v3 36 include/pcmcia/device_id.h .prod_id = { NULL, NULL, (v3), NULL }, \ v3 45 include/pcmcia/device_id.h #define PCMCIA_DEVICE_PROD_ID13(v1, v3, vh1, vh3) { \ v3 48 include/pcmcia/device_id.h .prod_id = { (v1), NULL, (v3), NULL }, \ v3 57 include/pcmcia/device_id.h #define PCMCIA_DEVICE_PROD_ID123(v1, v2, v3, vh1, vh2, vh3) { \ v3 61 include/pcmcia/device_id.h .prod_id = { (v1), (v2), (v3), NULL },\ v3 71 include/pcmcia/device_id.h #define PCMCIA_DEVICE_PROD_ID134(v1, v3, v4, vh1, vh3, vh4) { \ v3 75 include/pcmcia/device_id.h .prod_id = { (v1), NULL, (v3), (v4) }, \ v3 78 include/pcmcia/device_id.h #define PCMCIA_DEVICE_PROD_ID1234(v1, v2, v3, v4, vh1, vh2, vh3, vh4) { \ v3 83 include/pcmcia/device_id.h .prod_id = { (v1), (v2), (v3), (v4) }, \ v3 95 include/pcmcia/device_id.h #define PCMCIA_DEVICE_MANF_CARD_PROD_ID3(manf, card, v3, vh3) { \ v3 101 include/pcmcia/device_id.h .prod_id = { NULL, NULL, (v3), NULL }, \ v3 137 include/pcmcia/device_id.h #define PCMCIA_MFC_DEVICE_PROD_ID13(mfc, v1, v3, vh1, vh3) { \ v3 141 include/pcmcia/device_id.h .prod_id = { (v1), NULL, (v3), NULL }, \ v3 145 include/pcmcia/device_id.h #define PCMCIA_MFC_DEVICE_PROD_ID123(mfc, v1, v2, v3, vh1, vh2, vh3) { \ v3 150 include/pcmcia/device_id.h .prod_id = { (v1), (v2), (v3), NULL },\ v3 186 include/pcmcia/device_id.h #define PCMCIA_PFC_DEVICE_PROD_ID13(mfc, v1, v3, vh1, vh3) { \ v3 190 include/pcmcia/device_id.h .prod_id = { (v1), NULL, (v3), NULL }, \ v3 194 include/pcmcia/device_id.h #define PCMCIA_PFC_DEVICE_PROD_ID123(mfc, v1, v2, v3, vh1, vh2, vh3) { \ v3 199 include/pcmcia/device_id.h .prod_id = { (v1), (v2), (v3), NULL },\ v3 221 include/pcmcia/device_id.h #define PCMCIA_DEVICE_CIS_PROD_ID123(v1, v2, v3, vh1, vh2, vh3, _cisfile) { \ v3 226 include/pcmcia/device_id.h .prod_id = { (v1), (v2), (v3), NULL },\ v3 152 lib/atomic64_test.c long long v3 = 0x8000000000000000LL; v3 243 lib/atomic64_test.c INIT(v3); v3 24 lib/siphash.c v2 += v3; v3 = rol64(v3, 16); v3 ^= v2; \ v3 25 lib/siphash.c v0 += v3; v3 = rol64(v3, 21); v3 ^= v0; \ v3 33 lib/siphash.c u64 v3 = 0x7465646279746573ULL; \ v3 35 lib/siphash.c v3 ^= key->key[1]; \ v3 41 lib/siphash.c v3 ^= b; \ v3 50 lib/siphash.c return (v0 ^ v1) ^ (v2 ^ v3); v3 60 lib/siphash.c v3 ^= m; v3 93 lib/siphash.c v3 ^= m; v3 126 lib/siphash.c v3 ^= first; v3 143 lib/siphash.c v3 ^= first; v3 147 lib/siphash.c v3 ^= second; v3 166 lib/siphash.c v3 ^= first; v3 170 lib/siphash.c v3 ^= second; v3 174 lib/siphash.c v3 ^= third; v3 194 lib/siphash.c v3 ^= first; v3 198 lib/siphash.c v3 ^= second; v3 202 lib/siphash.c v3 ^= third; v3 206 lib/siphash.c v3 ^= forth; v3 227 lib/siphash.c v3 ^= combined; v3 244 lib/siphash.c v3 ^= b; \ v3 251 lib/siphash.c return (v0 ^ v1) ^ (v2 ^ v3); v3 261 lib/siphash.c v3 ^= m; v3 294 lib/siphash.c v3 ^= m; v3 341 lib/siphash.c v3 ^= combined; v3 360 lib/siphash.c v3 ^= combined; v3 381 lib/siphash.c v3 ^= combined; v3 385 lib/siphash.c v3 ^= combined; v3 395 lib/siphash.c v2 += v3; v3 = rol32(v3, 8); v3 ^= v2; \ v3 396 lib/siphash.c v0 += v3; v3 = rol32(v3, 7); v3 ^= v0; \ v3 404 lib/siphash.c u32 v3 = 0x74656462U; \ v3 406 lib/siphash.c v3 ^= key->key[1]; \ v3 412 lib/siphash.c v3 ^= b; \ v3 419 lib/siphash.c return v1 ^ v3; v3 429 lib/siphash.c v3 ^= m; v3 452 lib/siphash.c v3 ^= m; v3 474 lib/siphash.c v3 ^= first; v3 490 lib/siphash.c v3 ^= first; v3 493 lib/siphash.c v3 ^= second; v3 511 lib/siphash.c v3 ^= first; v3 514 lib/siphash.c v3 ^= second; v3 517 lib/siphash.c v3 ^= third; v3 536 lib/siphash.c v3 ^= first; v3 539 lib/siphash.c v3 ^= second; v3 542 lib/siphash.c v3 ^= third; v3 545 lib/siphash.c v3 ^= forth; v3 112 lib/xxhash.c uint32_t v3 = seed + 0; v3 120 lib/xxhash.c v3 = xxh32_round(v3, get_unaligned_le32(p)); v3 127 lib/xxhash.c xxh_rotl32(v3, 12) + xxh_rotl32(v4, 18); v3 182 lib/xxhash.c uint64_t v3 = seed + 0; v3 190 lib/xxhash.c v3 = xxh64_round(v3, get_unaligned_le64(p)); v3 197 lib/xxhash.c xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18); v3 200 lib/xxhash.c h64 = xxh64_merge_round(h64, v3); v3 250 lib/xxhash.c state.v3 = seed + 0; v3 264 lib/xxhash.c state.v3 = seed + 0; v3 297 lib/xxhash.c state->v3 = xxh32_round(state->v3, get_unaligned_le32(p32)); v3 310 lib/xxhash.c uint32_t v3 = state->v3; v3 318 lib/xxhash.c v3 = xxh32_round(v3, get_unaligned_le32(p)); v3 326 lib/xxhash.c state->v3 = v3; v3 348 lib/xxhash.c xxh_rotl32(state->v3, 12) + xxh_rotl32(state->v4, 18); v3 350 lib/xxhash.c h32 = state->v3 /* == seed */ + PRIME32_5; v3 403 lib/xxhash.c state->v3 = xxh64_round(state->v3, get_unaligned_le64(p64)); v3 415 lib/xxhash.c uint64_t v3 = state->v3; v3 423 lib/xxhash.c v3 = xxh64_round(v3, get_unaligned_le64(p)); v3 431 lib/xxhash.c state->v3 = v3; v3 454 lib/xxhash.c const uint64_t v3 = state->v3; v3 458 lib/xxhash.c xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18); v3 461 lib/xxhash.c h64 = xxh64_merge_round(h64, v3); v3 464 lib/xxhash.c h64 = state->v3 + PRIME64_5; v3 37 tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c u32 v1=0,v2=0,v3=0; v3 46 tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c v3 = inl(pm_tmr_ioport); v3 47 tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c } while ((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1) v3 48 tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c || (v3 > v1 && v3 < v2)); v3 145 virt/kvm/arm/vgic/vgic-debug.c bool v3 = dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3; v3 149 virt/kvm/arm/vgic/vgic-debug.c seq_printf(s, "vgic_model:\t%s\n", v3 ? "GICv3" : "GICv2"); v3 151 virt/kvm/arm/vgic/vgic-debug.c if (v3)